1996_Harris_Linear_ICs 1996 Harris Linear ICs

User Manual: 1996_Harris_Linear_ICs

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$5.00

HARRIS
SEMICONDUCTOR
TECHNICAL ASSISTANCE
Harris Marketing Support Services (HMSS)
HMSS provides world-class service to customers requiring information on all products offered by Harris
Semiconductor. Ask Harris Marketing Support Services for answers concerning:
• Product Identification
• Availability
• Competitive and Obsolete Cross-Reference

• Distributor Stocking Levels
• Requests for Literature and Samples

HMSS services are available from 8:00am to 8:00pm EST. Within the United States, call1-800-4HARRIS.
Callers from outside the United States, dial (407) 727-9207.
HMSS is the initial contact for customers who need technical assistance with the selection and use of
our products. Callers have the option to be connected directly to the Central Applications Group.

Central Applications
Ask our experienced staff of engineers for assistance with:
• Device Selection
• Specification Interpretation
• Applications for Any Harris Product
Central Applications serves you Monday through Thursday 8:00am to 7:00pm and Friday 8:00am to
5:00pm EST. Within the United States, call1-800-4HARRIS. Callers from outside the United States dial
(407) 727-9207.
Central Applications' knowledge of our portfolio can provide you with a total system design solution
using the latest Harris devices!

Electronic Technical Support
Electronic services from Harris Semiconductor offer you the most current information possible.

http://www.semi.harris.com
•
•
•
•
•

Latest Literature Revisions
New Product Listing
Product Information
Design Support
Contact Information

t.nHARRlS
W

SEMICONDUCTOR

(407) 724-7S00
• Latest Literature Revisions
• New Product Listing
• Data Book Request Form

ENTRAL

~APPLICATIONS
EMAIL

centapp@harris.com, or 1-S00-4HARRIS
• Technical Application Assistance

Copyright © Harris Corporation 1996
(All Rights Reserved)
Printed in USA, 11/1996

See our
specs in

CAPS

HARRIS LINEAR PRODUCTS
Harris Semiconductor is .a pioneer in developing and producing advanced Linear
products for the most demanding Commercial, Industrial and Automotive applications
worldwide. Harris offers an extensive line of Linear components including: High Speed
and General Purpose Op Amps, Comparators, Sample/Hold Amps, Video Crosspoint
Switches, Special Analog.Circuits and Transistor Arrays.
This data book fully describes Harris Semiconductor's Linear ICs. It includes a
complete set of data sheets for product specifications, application notes with design
details for specific applications of Harris products, and a description of the Harris
Quality and Reliability program. Section 12, Harris' On-Line Services, describes how
our customers have access to the most recent technical updates.
It is our intention to provide you with the most up-to-date information on Linear
Products. For complete, current and detailed technical specifications on any Harris
devices, please contact the nearest Harris sales, representative or distributor office,
listed in Section 13; or direct literature requests to:
Harris Semiconductor Data Services Department
P.O. Box 883, MS 53-204·
Melbourne, FL 32902
Phone: 1-800-442-7747
Fax: 407-724-7240

For a complete listing of all Harris Semiconductor products, please refer to the Product
Selection Guide (PSG201; ordering information above).

See Section 12 for Harris' On-Line Services

Harris Semiconductor products are sold by description only. Harris Semiconductor reserves
the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing
orders. Information furnished by Harris is believed to be accurate and reliable. However, no
responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of
patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Harris or its subsidiaries.

LINEAR INTEGRATED CIRCUITS
FOR COMMERCIAL AND INDUSTRIAL APPLICATIONS
New Products •
Table of Contents and General Information •

* Operational Amplifiers •
*Comparators •
*Sample and Hold Amplifiers.
*Video Crosspoint Switches.
*Transistor and Diode Arrays, and Differential Amplifiers.
Special Analog Circuits •
Harris Quality and Reliability.

II
Packaging Information III

Application ,Notes, Abstracts and Spice Model Listing

Harris' On-Line Services
Sales Offices
* A Product Selection Guide is located at the beginning of the section.

iii

III

II

1
NEW PRODUCTS

PAGE
VIDEO OP AMPS AND BUFFERS . ................................................................. .

1·3

SAMPLElHOLD ................................................................................. .

1·5

PIN DRIVER ................................................................................... .

1·6

WIRELESS COMMUNICATIONS . ...........................•.......................................

1·6

VIDEO CROSSPOINT SWITCHES . ................................................................. .

1·7

t

::;)

Q

0

a::
A.

~
w
Z

New High Speed Linear Products
VIDEO OP AMPS AND BUFFERS
HFA1145
LOW POWER VIDEO OP AMP WITH DISABLE

HFA1109
LOW POWER, WIDE BAND, VIDEO OP AMP

AnswerFAX DOCUMENT 4# 3955
• -3dB Bandwidth ..................•....... 330MHz
• High Slew Rate .......................... 1000VlJ.lS

AnswerFAX DOCUMENT # 4019
• Wide -3dB Bandwidth ..................... 5S0MHz
• High Slew Rate ......................... 1200V/lls
•
•
•
•
•

• Differential Gain/Phase ........... 0.02%/0.03 Degrees

Gain Flatness to 250M Hz ..... '.............. ±O.SdB
Fast Settling Time (0.1 %) ...................... 17ns
Differential Gain/Phase .......... 0.02%/0.02 Degrees
Low Supply Current. ........................ 10mA
8 Lead PDIP and SOIC

•
•
•
•

=

HFA1113
PROG. GAIN VIDEO BUFFER WITH OUTPUT LIMITING

HFA1105.
LOW POWER VIDEO OP AMP

t

:;)

AnswerFAX DOCUMENT 4# 1342
• Wide -3dB Bandwidth ...................... 850MHz
• High Slew Rate ...............•.......... 2400V/lls

AnswerFAX DOCUMENT # 3395
• -3dB Bandwidth (Av +2) .................. 330MHz

=

•
•
•
•
•

Gain Flatness to 7SMHz ....................... ±0.1dB
Low Supply Current. . . . . . . . . . . . . . . . . . . . . . . . .. 6mA
Output Enable/Disable (TONITOFF 180ns/3Sns)
8 Lead PDIP and SOIC

High Slew Rate ......................... 1000VlJ.lS
Gain Flatness to 7SMHz ....................... ±0.1 dB
Fast Settling Time (0.1 %) ...................... 1Sns
Differential Gain/Phase . . . . . . . . .. 0.02%/0.03 Degrees
Low Supply Current .......................... 6mA

•
•
•
•

Differential Gain/Phase .......... 0.02"1010.04 Degrees
User Programmable Gain of +2, ±1
User Programmable Output Limiting
8 Lead PDIP and SOIC

• 8 Lead PDIP and SOIC
HFA1114
CABLE DRIVING BUFFER WITH SUMMING NODE

HFA1106
VIDEO OP AMP WITH EXTERNAL COMPENSATION

AnswerFAX DOCUMENT 4# 3151
AnswerFAX DOCUMENT # 3922

• Wide -3dB Bandwidth ........... , .......... 8S0MHz

• -3dB Bandwidth .......................... 31SMHz

• High Slew Rate .......................... 2400VlIlS

• High Slew Rate .......................... 700V/lls
• Differential Gain/Phase ........... 0.02°/010.05 Degrees

• Differential Gain/Phase. . . . . . . . .. 0.02"1010.04 Degrees

• Low Supply Current. . . . . . . . . . . . . . . . . . . . . . .. S.8mA
• Compensation Pin for Bandwidth Limiting

• Summing Node Pinout Enables Tailoring of System
Response For Cable Length

• 8 Lead PDIP and SOIC

• 8 Lead PDIP and SOIC

• User Programmable Gain (+2, ±1)

HA4600
400MHz VIDEO BUFFER WITH OUTPUT DISABLE

HFA1149
LOW POWER, WIDEBAND OP AMP
WITH OUTPUT DISABLE

AnswerFAX DOCUMENT # 3990
• Low Power DiSSipation ..................... 10SmW

AnswerFAX DOCUMENT # 4019
• Wide -3dB Bandwidth ..... . . . . . . . . . . . . . . .. 5S0MHz
• High Slew Rate ........................ , 1200VlllS

• Symmetrical Slew Rates. . . . . . . . . . . . . . . . .. 1700VlJ.lS
• 0.1dB Gain Flatness ................•.••.. 2S0MHz
• Off Isolation (100MHz) ....................... 8SdB

• Gain Flatness to 250M Hz ................... ±O.SdB

• Differential Gain and Phase ....... 0.01"1010.01Degrees

• Differential Gain/Phase . . . . . . . . .. 0.02"1010.02 Degrees

• High ESD Rating ................•......... >2000V

• Low Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . 10mA

• 8 Lead PDIP and SOIC

• Fast Enable/Disable Times ................ 18nsl11 ns
• 8 Lead PDIP and SOIC

1-3

o
o

a:
a..

3:
w
z

New High Speed Linear Products
HFA1135
VIDEO OP AMP WITH OUTPUT LIMITING

•
•
•
•
•
•
•
•

AnswerFAX DOCUMENT # 3653
·3dB Bandwidth ........................... 36.oMHz
High Slew Rate ......................... 12.o.oV/lls
Fast Settling Time (.0.1 %) ...................... 15ns
Differential Gain/Phase. . . . . . . . . .. .0..02%/.0..04 Degrees
Low Supply Current. .........................7mA
User Programmable Output Limiting
Fast Overdrive Recovery ...................... S

LT1225CSB

HA9P2841-5

Yes

For Gains >S

Yes

LT1225MJ8

HA7-2841/883

LT1226CJ8

HA7-2B40-5

LT1226CNB

HA3-2840-S

LT1226CSB

HA9P2B40-S

LT1226MJB

HA7-2840/BB3

LT1227CNB

HA3-5020-5

Yes

Lower Cost

LT1227CSB

HA9P5020-S

Yes

Lower Cost

LT1227MJB

HA7-S020/BB3

Yes

Lower Cost

LT1229CN8

HA50231P

Yes

Better Video and DC Specifications, ±SV Only

LT1229CSB

HA50231B

Yes

Better Video and DC Specifications, ±SV Only

For Gains >5

t
t

For Gains >25

t
t

For Gains >25

For Gains >2S

For Gains >25

LT1230CS

HAS02SIB

Yes

Better Video and DC Specifications

LT1230CN

HAS02SIP

Yes

Better Video and DC Specifications

LT12S2CNB

HA3-S020-S

Yes

LT12S2CS8

HA9PS020-S

Yes

LT1253CNB

HA50231P

Yes

Better AC and Video Specs

LT1253CSB

HAS0231B

Yes

Better AC and Video Specs

LT12S4CN

HAS0251P

Yes

Better AC and Video Specs

LT1254CS

HAS02SIB

Yes

Better Slew Rate and Video Specs

LT1259CN

HA50221P

Yes

Functional Equivalent

LT12S9CS

HA50221B

Yes

Functional Equivalent

LT1260CN

HA50131P

Yes

LT1260CS

HAS0131B

Yes

LT1360CNB

HA3-2841-5

Yes

LT1360CNB

HA3-S020-S

Yes

VFB vs CFB

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-27

LLen

o!z
WW

..J",

IIlZ

~8

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

PIN·TO·PIN

HARRIS ADVANTAGE/COMMENT

LT1360CS8

HA9P2841-S

Ves

LT1360CS8

HA9PS020-S

Ves

LT1361CN8

HAS0231P

Ves

VFB vs CFB

LT1361CS8

HAS0231B

Ves

VFB vs CFB

LT1362CN

HAS02SIP

Ves

VFB vs CFB

LT1362CS

HAS0251B

Ves

Functional Equivalent

LT1363CN8

HA3-2841-S

Ves

LT1363CNB

HA3-5020-5

Ves

LT1363CS8

HA9P2841-S

Ves

LT1363CS8

HA9P5020-5

Ves

VFB vs CFB

LT1364CNB

HAS0231P

Ves

VFB vs CFB

LT1364CSB

HAS0231B

Ves

VFB vs CFB

LT136SCN

HAS0251P

Ves

VFB vs CFB

LT1365CS

HAS0251B

Ves

VFB vs CFB

LTC1050ACH

ICL76S0SITV-l

LTC1050ACN8

ICL7650SIPA,1

LTC1050AMH

ICL76S0SMTV-l

LTC1050CH

ICL76S0SITV-l

LTC1050CN8

ICL7650SIPA-l

LTC1050CP

ICL7650SIPA-l

LTC1050MH

ICL7650SMTV-l

MAX404CPA

HA3-2B42-5

VFBvS CFB

VFB vs CFB

t
t
t
t
t
t
t

Reduced 'BIAs/I'O
Reduced IBIAs/I,O
Reduced IBIAs/I'O
Reduced 'BIAs/I,oIgreater fJ.vOL
Reduced 'BIAsli,olgreater AVOL
Reduced 'BIAs/I'O
Reduced 'BIAs/I,oIgreater AVOL

Ves

MAX404CSA

HA9P2842-S

Ves

Better Video Specs, Lower Power

MAX404EPA

HA3-2842-9

Yes

Better Video Specs, Lower Power

MAX404ESA

HA9P2B42-S

Ves

Better Video Specs, Lower. Power

MAX4S2CPA

HA3-2841-S

Yes

Lower Power

MAX4S2CSA

HA9P2841-S

Ves

Lower Power

MAX4S2EJA

HA3-2841-9

Ves

Lower Power

MAX4S2EPA

HA3-2841-9

Ves

Lower Power

MAX457CPA

HA50231P

Ves

Better Performance, Lower Power

MAX457CSA

HA50231B

Ves

Better Performance, Lower Power

MAX4S7EPA

HA50231P

Yes

MAX460lGC

HA2-5033-5

MAX460MGC

HA2-S033-2

MAX467CPE

HAS0131P

MAX467CWE
MC1776CD

Better Performance, Lower Power
Greater Bandwidth

t
t

Greater Bandwidth

Ves

Better AC Specs, Lower Power

HA50131B

Ves

Better AC Specs, Lower Power

ICL7611DCBA

Yes

Lower Power Drain

MCl776CG

ICL7611 BCTV

Ves

Lower Power Drain

MCl776CPl

ICL7611BCPA

Ves

Lower Power Drain

MCl776G

ICL7611 BMTV

Ves

Lower Power Drain

MC3302N

CA3290E

Ves

Moslet Input

MC3303D

CA5470M

Ves

Mos Input/enhanced ACs

MC3303N

CAS470E

Yes

Femos Input/enhanced ACs

MC33071P

CA3140AE

Ves

Reduced IBIASIi,O

MC33072P

CA3240AE

Ves

Reduced 'BIASIi,O

MC3346D

CA3046M

Ves

Full-S5 To 12SoC Operation

MC3346P

CA3046E

Ves

Full -5S To 12SoC Operation

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-28

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

PIN·TO·PIN

HARRIS ADVANTAGE/COMMENT

MC34001BG

CA3140AT

Yes

Reduced IBIAs/IIO

MC34001BP

CA3140AE

Yes

Reduced IBIAs/IIO

MC34001G

CA3140T

Yes

Reduced IBIAs/IIO

MC34001P

CA3140E

Yes

Reduced IBIAs/IIO

MC34002BG

CA3240AT

Yes

Reduced IBIASillO

MC34002BP

CA3240AE

Yes

Reduced IBIASillO

MC34002G

CA3240T

Yes

Reduced IBIAs/IIO

MC34002P

CA3240E

Yes

Reduced IBIAS/IIO

MC3403D

CA5470M

Yes

Mos Input/enhanced ACs

MC3403N

CA5470E

Yes

Mos Input/enhanced ACs

MC34071P

CA3140AE

Yes

Reduced IBIAs/IIO

MC34072P

CA3240AE

Yes

Reduced IBIAs/IIO

MC3456L

ICM7556MJD

Yes

CMOS/Reduced ICC

MC3456P

ICM75561PD

Yes

CMOS/Reduced Icc

MC3556L

ICM7556MJD

Yes

CMOS/Reduced Icc

MC66BACN·B

ICL7650SCPA·1

Yes

Enhanced VOUT

NE5230N

CA5160AE

No

Mos Input

NE5517AN

CA32BOAE

No

Reduced VIO

NE5517D

CA32BOM

No

Reduced VIO

NE5517N

CA3280E

No

Reduced VIO

NE5532AFE

HA7-51 02-5

Yes

Enhanced VOUT/Reduced ICC

NE5532AN

HA3-51 02-5

Yes

Enhanced VOUT/Reduced ICC

NE5532FE

HA7-51 02-5

Yes

Enhanced VOUT/Reduced ICC

NE5532N

HA3-51 02-5

Yes

Enhanced VOUT/Reduced Icc

NES534AFE

HA7-5101-S

NE5534AN

HA3-51 01-5

NE5534FE

HA7-5101-5

NE5534N

HA3-51 01-5

NES539D

HA9P-2539-5

NE5539F

HAl-2839-5

NE5539N

HA3-2B39-5

t
t
t
t
t
t
t

NE556-1N

ICM75561PD

Yes

CMOS/Reduced Icc

Enhanced VOUT
Enhanced VOUT
Enhanced VOUT
Enhanced VOUT
Specified at ±15V Supplies
Specified at ±15V Supplies
Specified at ±lSV Supplies

NE556N

ICM7SS61PD

Yes

CMOS/Reduced IcC

OP-15CH

CA3140AT

Yes

Reduced IBIAs/IIO

OP-15GN8

CA3140AE

Yes

Reduced IBIAs/IIO

OP11AY

HA1-S134-2

Yes

Enhanced ACs

OP11EY

HA1-5134-5

Yes

Enhanced ACs

OP11FY

HA1-5104-5

Yes

Enhanced ACs

OP160GP

HA3-S020-9

Yes

OP160GS

HA9PS020-S

Yes

OP21SGZ

CA3240AE (PDIP)

Yes

OP220CJ

HA2-5142-2

Yes

OP220CZ

HA7-5142-2

Yes

Enhanced ACs

OP220GJ

HA2-S142-5

Yes

Enhanced ACs

OP220GZ

HA7-S142-S

Yes

Enhanced ACs

OP271AZ

HA7-51 02-2

Yes

Lower Voltage Noise/greater Bandwidth

Enhanced ACs

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-29

u.Ul

01Z
WW
...II-

mz
~8

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

PIN·TO·PIN

HARRIS ADVANTAGE/COMMENT

OP271EZ

HA7-51 02-5

Yes

Lower Voltage Noise/greater Bandwidth

OP271FZ

HA7-51 02-5

Yes

Lower Voltage Noise/greater Bandwidth

OP271GP

HA3-51 02-5

Yes

Lower Voltage Noise/greater Bandwidth

OP271GS

HA9P-5102-9

Yes

Lower Voltage Noise/greater Bandwidth

OP27AJ8

HA7-S127A-2

Yes

Enhanced ACS/Reduced Icc

OP27AZ

HA7-5127A-2

Yes

Enhanced ACS/Reduced Icc

OP27CJ8

HA7-S127-2

Yes

Enhanced ACs/Reduced Icc

OP27CZ

HA7-5127-2

Yes

Enhanced ACs/Reduced Icc

OP27EJ8

HA7-5127A-5

Yes

Enhanced ACs/Reduced Icc

OP27EZ

HA7-S127A-5

Yes

Enhanced ACS/Reduced Icc

OP27GJ8

HA7-5127-S

Yes

Enhanced ACS/Reduced Icc

OP27GZ

HA7-5127-S

Yes

Enhanced ACs/Reduced Icc

OP37AJ8

HA7-5137A-2

Yes

Enhanced ACS/Reduced Icc

OP37AZ

HA7-S137A-2

Yes

Enhanced ACs/Reduced Icc

OP37CJ8

HA7-S137-2

Yes

Enhanced ACs/Reduced Icc

OP37CZ

HA7-5137-2

Yes

Enhanced ACS/Reduced Icc

OP37EJ8

HA7-5137A-5

Yes

Enhanced ACS/Reduced Icc

OP37EZ

HA7-5137A-5

Yes

Enhanced ACS/Reduced Icc

OP37GJ8

HA7-5137-S

Yes

Enhanced ACS/Reduced Icc

OP37GZ

HA7-5137-S

Yes

Enhanced ACs/Reduced Icc

OP400AY

HA1-5134A-2

Yes

OP400EY

HA1-S134A-S

Yes

OP400FY

HA1-S134-S

Yes

OP420BY

HA1-S144-2

Yes

Enhanced ACs

OP420CY

HA1-S144-2

Yes

Enhanced ACs

OP420HY

HA1-S144-S

Yes

Enhanced ACs

OP470AY

HA1-S104-2

Yes

OP470EY

HA1-S104-S

Yes

OP470FY

HA1-S104-S

Yes

OP470GP

HA3-S104-S

Yes

OP470GS

HA9PS104-S

Yes

OP470GS

HA9PS104-S

Yes

OP47AD

HA7-S147A-2

Yes

OP47AT

HA2-S147A-2

Yes

OP47CD

HA7-S147-2

Yes

OP47CT

HA2-S147-2

Yes

OP47EN

HA7-S147A-S (CDIP)

Yes

OP47GN

HA7-S147-S (CDIP)

Yes

OP62AJ

HA2-S221-S

OP62AZ

HA7-S221-9

OP62EJ

HA2-S221-S

OP62EZ

HA7-S221-9

OP62FJ

HA2-S221-S

OP62FZ

HA7-5221-9

OP63AJ

HA2-S221-S

OP63AZ

HA7-S221-9

OP63EJ

HA2-S221-S

=10
=10
Greater Bandwidth/min AcL =10
Greater Bandwidth/min AcL =10
Greater Bandwidth/min AcL =10
Greater Bandwidth/min AcL = 10
Greater Bandwidth/min AcL

Greater Bandwidth/min AcL

t
t

Greater Slew Rate

t
t

Greater Slew Rate

t
t
t
t
t

Greater Slew Rate

Greater Slew Rate

Greater Slew Rate

Greater Slew Rate
ReducedVIO
Reduced VIO
Reduced VIO

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-30

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

PIN-TO-PIN

HARRIS ADVANTAGE/COMMENT

HA7·S221·9

t
t
t

Reduced VIO

OP64AJ

HA2·5221·S

t

Reduced VIO

OP64AZ

HA7·2622·2

Yes

OP64AZ

HA7·5221·9

OP64EJ

HA2·5221·S

OP64EZ

HA7·S221·9

OP64FJ

HA2·5221-5

t
t
t
t

OP64FZ

HA7·262S·S

Yes

OP64FZ

HA7-S221·9

OPBOFJ

CAS420AT

OP63EZ

HA7·S221·9

OP63FJ

HA2·S221·5

OP63FZ

Reduced VIO
Reduced VIO

Reduced VIO
Reduced VIO
Reduced VIO
Reduced VIO

OPBOGJ

CA5420T

OPBOGP

CA5420E

OPA121KP

CA3140AE

t
t
t
t
t

OPA2111KM

HA2-51 02-5

Yes

Greater Bandwidth

OPA2111KP

HA3-S102-5

Yes

Greater Bandwidth

OPA27AZ

HA7-S127A-2

Yes

Enhanced ACslReduced Icc

OPA27CZ

HA7-S127-2

Yes

Enhanced ACslReduced IcC

OPA27EZ

HA7-S127A-5

Yes

Enhanced ACs/Reduced Icc

OPA27GZ

HA7·S127-S

Yes

Enhanced ACs/Reduced Icc

OPA37AZ

HA7-S137A-2

Yes

Enhanced ACs/Reduced IcC

OPA37CZ

HA7-S137-2

Yes

Enhanced ACs/Reduced Icc

OPA37EZ

HA7-S137A-S

Yes

Enhanced ACslReduced Icc

OPA37GZ

HA7-S137-S

Yes

Enhanced ACs/Reduced Icc

OPA404AG

HA1-S114-S

Yes

Lower Voltage Noise/enhanced ACs

OPA404BG

HA1-S114-S

Yes

Lower Voltage Noise/enhanced ACs

OPA404KP

HA3-S114-S

Yes

Lower Voltage Noise/enhanced ACs

OPA404KU

HA9PS114-S

Yes

Lower Voltage Noise/enhanced ACs

OPA404SG

HA1-S114-2

Yes

Lower Voltage Noise/enhanced ACs

OPA44SAP

HA7-264S-S

Yes

Reduced VIO
Single Supply Operation
Single Supply Operation
Single Supply Operation
Mos InpuVenhanced ACs

OPA44SBM

HA2-2640-2'

Yes

OPA44SSM

HA2-2640-2

Yes

OPA623AU

HFA110SIB

Yes

OPA633AH

HA2-S033-2

Yes

OPA633KP

HA3-S033-S

Yes

OPA633SH

HA2-S033-S

Yes

OPA644H

HFA1100lJ

Yes

Better Bandwidth

OPA644HB

HFA1100lJ

Yes

Better Bandwidth

OPA644P

HFA1100lP

Yes

Better Bandwidth

OPA644PB

HFA1100lP

Yes

Better Bandwidth

OPA644U

HFA1100lB

Yes

Better Bandwidth

OPA644UB

HFA1100lB

Yes

Better Bandwidth

OPA64BH

HFA1100lJ

Yes

OPA648P

HFA1100lP

Yes

OPA648U

HFA1100lB

Yes

Better Video and DC Specifications

Primary Pins are pin-to-pin; secondary/optional pins are not

2-31

u..~

Oz
WW

..JI-

mz
~8

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

PIN-TO-PIN

HARRIS ADVANTAGE/COMMENT

OPA658P

HFAll00lP

Yes

Harris Is Higher ICC

OPA658PB

HFA1100lP

Yes

Harris Is Higher Icc

OPA658U

HFAll00lB

Yes

Harris Is Higher Icc

OPA658U

HFA11051B

Ye~

Harris Is Lower AC

OPA658UB

HFAll00lB

Yes

Harris Is Higher Icc

OPA658UB

HFAll051B

Yes

Harris Is Lower ACs

RC3403AN

CA5470E

Yes

Mos Input/enhanced ACs

RC47410

HAI-4741-2

Yes

Guaranteed ACs

RC4741M

HA9P4741-9

Yes

Guaranteed ACs

RC5532AN

HA3-51 02-5

Yes

Enhanced Your/Reduced Icc

RC5532N

HA3-51 02-5

Yes

Enhanced Vour/Reduced Icc

RC5534AN

HA3-5101-5

Enhanced YOur/Reduced Icc

RC5534N

HA3-5101-5

RM5334T

HA2-51 01-2

t
t
t

RM5532AD

HA7-51 02-2

Yes

Reduced Icc

RM5532AT

HA2-51 02-2

Yes

Reduced Icc

RM5532D

HA7-51 02-2

Yes

Reduced Icc

RM5532T

HA2-51 02-2

Yes

Reduced Icc

RM5534AD

HA7-5101-2

Reduced IcC

RM5534AT

HA2-5101-2

RM5534D

HA7-5101-2

t
t
t

SA556-1N

ICM75561PD

Yes

CMOS/Reduced Icc

SA556N

ICM75561PD

Yes

CMOS/Reduced Icc

SE5532AFE

HA7-51 02-2

Yes

Reduced Icc

SE5532FE

HA7-51 02-2

Yes

SE5534AFE

HA7-5101-2

SE5534FE

HA7-5101-2

SE5539F

HA1-2539-2

t
t
t

SE556-1CN

ICM7556MJD

Yes

CMOS/Reduced Icc

SE556-1F

ICM7556MJD

Yes

CMOS/Reduced Icc

SE556F

ICM7556MJD

Yes

CMOS/Reduced ICC

SG1536T

HA2-2640-2

SG1536Y

HA7-2640-2

SG3045J

CA3045F

SG3049T

CA3049T

Yes

SG3083

CA3083

Yes

SG3183D

CA3183M

Yes

Identical Specs at 25°C

SG3183N

CA3183E

Yes

Identical Specs at 25°C

SHC5320KH

HAI-5320-5

Yes

SHC5320SH

HA1-5320-2

Yes

SHC85

HA1-2425-5

No

SHC85ET

HA1-2420-2

No

Enhanced ACs

SHM-20C

HA1-5320-5

Yes

Guaranteed Acquisition Time

SHM-20M

HA1-5320-2

Yes

Guaranteed Acquisition Time

SHM-IC-1

HAI-2425-5

Yes

Almost Identical

SHM-IC-1M

HA1-2420-2

Yes

Almost Identical

I

Enhanced Vour/Reduced Icc
Reduced Icc

Reduced Icc
Reduced Icc

Reduced Icc
Reduced IBIAs/IIG
Reduced IBIAS"IO
Specified at ±15V Supplies

Reduced Violenhanced ACs

t
t

Reduced Violenhanced ACs

Yes
Greater Bandwidth/Reduced Noise

Enhanced ACs

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-32

Commercial Linear Product Cross Reference
PART NUMBER

SL3045C-DG

t

HARRIS DEVICE

PIN-TO-PIN

CA3045F

HARRIS ADVANTAGE/COMMENT

Yes

SL3046C-DP

CA3046E

Yes

SL3127C-DC

CA3127F

Yes

SL3127C-DP

CA3127E

Yes

SL3145C-DC

CA3045F

Yes

Greater Breakdown Voltages

SL3145C-DP

CA3046E

Yes

Greater Breakdown Voltages

SL3227-DP

CA3227E

Yes

Greater Breakdown Voltages

SL3227-MP

CA3227M

Yes

Greater Breakdown Voltages

SL3245-DP

CA3246E

Yes

Programmable Biasing Current

SL3245-MP

CA3246M

Yes

Faster Acquisition/lower Droop

SMP10AY

HA1-2420-2

t

Faster Acquisition/lower Droop

SMP10BY

HA1-2420-2

t

Faster Acquisition~ower Droop

SMP10EY

HA1-2425-5

t

Faster Acquisition/lower Droop

SMP10FY

HA1-2425-5

t

Faster Acquisition/lower Droop

SMP11AY

HA1-2420-2

Faster Acquisition/lower Droop

SMP11BY

HA1-2420-2

SMP11EY

HAI-2425-5

SMP11FY

HA1-2425-5

t
t
t
t

SP1-2541-2

HA1-2541-2

Yes

SP1-2541-5

HA1-2541-5

Yes

SP1-2542-2

HAI-2542-2

Yes

SPI-2542-5

HAI-2542-5

Yes

SPI-5330-2

HAI-5330-2

Yes

SPI-5330-5

HAI-5330-5

Yes

SP2-2500-2

HA2-2500-2

Yes

SP2-2502-2

HA2-2502-2

Yes

SP2-2505-5

HA2-2505-5

Yes

SP2-251 0-2

HA2-251 0-2

Yes

SP2-2512-2

HA2-2512-2

Yes

VOUT Version Available

Faster Acquisition/lower Droop

ILC/)

01Z
WW

...JI-

IXlZ

~8

SP2-2515-5

HA2-2515-5

Yes

SP2-2520-2

HA2-2520-2

Yes

Substitute HA2-2529-2

SP2-2522-2

HA2-2522-2

Yes

Substitute HA2-2529-2

SP2-2525-5

HA2-2525-5

Yes

Substitute HA2-2529-5

SP2-2541-2

HA2-2541-2

Yes

SP2-2541-5

HA2-2541-5

Yes

SP2-2542-2

HA2-2542-2

Yes

SP2-2542-5

HA2-2542-5

Yes

SP2-2600-2

HA2-2600-2

Yes

SP2-2602-2

HA2-2602-2

Yes

SP2-2605-5

HA2-2605-5

Yes

SP2-2620-2

HA2-2620-2

Yes

SP2-2622-2

HA2-2622-2

Yes

SP2-2625-5

HA2-2625-5

Yes

SP3-2505-5

HA3-2505-5

Yes

SP3-2515-5

HA3-2515-5

Yes

SP3-2525-5

HA3-2525-5

Yes

SP3-2542-5

HA3B2842-5

Yes

Substitute HA3-2529-5

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-33

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

PIN-TO-PIN

HARRIS ADVANTAGE/COMMENT

SP3-2605-5

HA3-2605-5

Yes

SP3-2625-5

HA3-2625-5

Yes

SP7-2500-2

HA7-2500-2

Yes

SP7-2502-2

HA7-2502-2

Yes

SP7-2505-5

HA7-2505-5

Yes

SP7-2510-2

HA7-251 0-2

Yes

SP7-2512-2

HA7-2512-2

Yes

SP7-2515-5

HA7-2515-5

Yes

SP7-2520-2

HA7-2520-2

Yes

Substitute HA7-2529-2

SP7-2522-2

HA7-2522-2

Yes

Substitute HA7-2529-2

SP7-2525-5

HA7-2525-5

Yes

Substitute HA7 -2529-5

SP7-2600-2

HA7-2600-2

Yes

SP7-2602-2

HA7-2602-2

Yes

SP7-2605-5

HA7-2605-5

Yes

SP7-2620-2

HA7-2620-2

Yes

SP7-2622-2

HA7-2622-2

Yes

SP7-2625-5

HA7-2625-5

Yes

TA75393P

CA3290AE/CA3290E

Yes

Reduced ISIAsliioIlcc

TA75557F

HA9P5102-9

No

Greater Bandwidth/Reduced Vnoise

TA75557P

HA3-51 02-5

Yes

Greater Bandwidth/Reduced Vnoise

TA75559F

HA9P5112-9

No

Greater Bandwidth/Reduced Vnoise

TA75559P

HA3-5112-5

Yes

Greater Bandwidth/Reduced Vnoise

TCA971

CA3146AE/CA3046E

Yes

Greater \lCBO With CA3146

TCA971G

CA3146AM/CA3046M

Yes

Greater VCBO With CA3146

TCA991

CA3146E/CA3046E

Yes

Greater VCBO With CA3146

TCA991G

CA3146M/CA3046M

Yes

Greater VCBO With CA3146

TD62507F

CA3183AM

No

All. Product Is CA3083

TD62507P

CA3183AE

No

All. Product Is CA3083

TDB2046DP

CA3046E

Yes

Full-55 To 125°C Operation

TDB2046FP

CA3046M

Yes

Full-55 To 125°C Operation

TLC252ACD

CA5260AM

Yes

Specified at +5V Supply

TLC252ACP

CA5260AE

Yes

Specified at +5V Supply

TLC252CD

CA5260M

Yes

Specified at +5V Supply

TLC252CP

CA5260E

Yes

Specified at +5V Supply

TLC254CD

CA5470M

Yes

Specified at +5V Supply

TLC254CN

CA5470E

Yes

Specified at +5V Supply

TLC272ACD

CA5260AM

Yes

Greater VOUT Range/Reduced Icc

TLC272ACP

CA5260AE

Yes

Greater VOUT Range/Reduced Icc

TLC272AID

CA5260AM

Yes

Greater VOUT Range/Reduced Icc

TLC272AIP

CA5260AE

Yes

Greater VOUT Range/Reduced ICC

TLC272CD

CA5260M

Yes

Greater VOUT Range/Reduced Icc

TLC272CP

CA5260E

Yes

Greater VOUT Range/Reduced Icc

TLC2721D

CA5260M

Yes

Greater VOUT Range/Reduced Icc

TLC2721P

CA5260E

Yes

Greater VOUT Range/Reduced Icc

TLC272MJG

CA5260E (PDIP)

Yes

Greater VOUT Range/Reduced Icc

TLC274CD

CA5470M

Yes

Greater VOUTlbandwidth/slew Rate

TLC274.CN

CA5470E

Yes

Greater VOUT/bandwidth/slew Rate

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-34

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

PIN·TO·PIN

HARRIS ADVANTAGE/COMMENT

TLC2741D

CA5470M

Yes

Greater VOUTlbandwidth/slew Rate

TLC2741N

CA5470E

Yes

Greater VOUT/bandwidth/slew Rate

TLC274MJ

CA5470E (PDIP)

Yes

Greater VOUT/bandwidth/slew Rate

TLC27M2ACD

CA5260AM

Yes

Greater VOUTlbandwidth/slew Rate

TLC27M2ACP

CA5260AE

Yes

Greater VOUTlbandwidthlslew Rate

TLC27M2AID

CA5260AM

Yes

Greater VOUTlbandwidthlslew Rate

TLC27M2AIP

CA5260AE

Yes

Greater VOUT/bandwidth/slew Rate

TLC27M2CD

CA5260M

Yes

Greater VOUT/bandwidthlslew Rate

TLC27M2CP

CA5260E

Yes

Greater VouTlbandwidthlslew Rate

TLC27M21D

CA5260M

Yes

Greater VOUTlbandwidthlslew Rate

TLC27M21P

CA5260E

Yes

Greater VOUT/bandwidth/slew Rate

TLC27M2MJG

CA5260E (PDIP)

Yes

Greater VOUT/bandwidth/slew Rate

TLC555CD

ICM7555CBA

Yes

Reduced Icc

TLC5551P

ICM75551PA

Yes

Reduced Icc

TLC556CN

ICM75561PD

Yes

Reduced Icc

TLC5561N

ICM75561PD

Yes

Reduced Icc

TLC556MJ

ICM7556MJD

Yes

Reduced Icc

TP1321

HA·5195

Yes

TP1322

HA-2520

Yes

TP1326

HA-2600

Yes

TP1332

HA-2645

Yes

TP1339

HA-2620

No

TP1341

HA-2840

Yes

TP1342

HA-2839

Yes

TP1344

HA-5160

Yes

LLcn

01Z
WW

...JIIIlZ

~8

TP1345

HA-5162

Yes

TP4856

HA 1-2420/25

Yes

Guaranteed Acquisition Time

TP4866

HAl-5320

Yes

Guaranteed Acquisition Time

TSC7650ACPA

ICL7650SCPA-l

Yes

Reduced Tempco/voltage Noise

TSC7650ACPD

ICL7650SCPD

Yes

Reduced Tempco/voltage Noise

TSC7650AIJA

ICL7650SIJA-l

Yes

Reduced Tempco/voltage Noise

TSC7650AIJD

ICL7650SIJD

Yes

Reduced Tempco/voltage Noise

UCOP01CN

CA3140AE

Yes

Moslet Input

UCOP01GJ

CA3140AE (PDIP)

Yes

Moslel Inpul
Full -40 To 85°C Operation

ULN2046A-l

CA3146E

Yes

ULN2046L-l

CA3146M

Yes

ULN2083A

CA3083

Yes

Full-55 To 125°C Operation

ULN2083A-l

CA3183E

Yes

Full -40 To 85°C Operation
Full-55 To 125°C Operation

ULN2083L

CA3083M

Yes

ULN2086A

CA3086

Yes

Full-55 To 125°C Operation

XR-13600AP

CA3280AE

No

Reduced Violenhanced ACs

XR-13600CP

CA3280E

No

Reduced Violenhanced ACs

XR-2242CP

ICM72421PA

Yes

Greatiy Reduced Icc

XR-3403CP

CA5470E

Yes

Mos Input/enhanced ACs

XR-4739CN

HA7-51 02-5

No

Enhanced ACs/DCs

XR-4739CP

HA3-51 02-5

No

Enhanced ACslDCs

XR-4741CN

HAI-4741-5

Yes

Guaranteed Channel Separation

Primary Pins are pin-to-pin; secondary/optional pins are not.

2·35

Commercial Linear Product Cross Reference
PART NUMBER

t

HARRIS DEVICE

XR-4741CP

HA3-4741-5

XR-4741M
XR-5532AN

PIN-TO-PIN

HARRIS ADVANTAGE/COMMENT

Yes

Guaranteed Channel Separation

HA1-4741-2

Yes

Guaranteed Channel Separation

HA7-51 02-5

Yes

Reduced VloIlslAS

XR-5532AP

HA3-51 02-5

Yes

Reduced VloIlslAS

XR-5532N

HA7-51 02-5

Yes

Reduced VloIlslAS

XR-5532P

HA3-51 02-5

Yes

XR-5534ACN

HA7-5101-5

XR-5534ACP

HA3-5101-5

XR-5534AM

HA7-5101-2

XR-5534CN

HA7-5101-5

XR-5534CP

HA3-5101-5

XR-5534M

HA7-51 01-2

t
t
t
t
t
t

XR-8038CN

ICL8038CCJD

Yes

XR-8038CP

ICL8038CCPD

Yes

XR-8038M

ICL8038AMJD

Yes

XR-8038N

ICL8038BCJD

Yes

uPA103G

HFA3046B

Yes

Lower Cost

uPC357C

CA3130E

Yes

Reduced ISlAS

uPC4741C

HA3-4741-5

Yes

Guaranteed Specs Over Temp

uPC4741G2

HA9P4741-9

t

Guaranteed Specs Over Temp

uPD5555C

ICM7555CPA

Yes

Reduced Icc

uPD5556C

ICM7556CPD

Yes

Reduced Icc

Reduced VloIlslAS
Greater AVOL/Reduced VIO
Greater AVOL/Reduced VIO
Greater AVOL
Greater AVOL/reduced VIO
Greater AVOL/reduced VIO
Greater AVOL

Primary Pins are pin-to-pin; secondary/optional pins are not.

2-36

Data Acquisition Products
AID CONVERTERS DISPLAY
CA3162/CA3162A

AID Converter lor"3 112-Digit Display

ICL71 C03/1CL8052

Precision 41/2-Digit AID Converter

ICL 71 C03/1CL8068

Precision 41/2-Digit AID Converter

ICL7106

31/2-Digit LCD Single-Chip AID Converter

ICL7107

31/2-Digit LED Single-Chip AID Converter

ICL7116n117

31/2-Digit with Display Hold Single-Chip AID Converter

ICL7126

31/2-Digit Low Power Single-Chip AID Converter

ICL7129

41/2-Digit LCD Single-Chip AID Converter

ICL7136

31/2-Digit LCD Low Power AID Converter

ICL7137

31/2-Digit LED Low Power Single-Chip AID Converter

ICL7139

33/4-Digit Autoranging Multimeter

ICL7149

Low Cost 33/4-Digit Autoranging Multimeter

AID CONVERTERS INTEGRATING

u..cn
01-

ICL7104/1CL8052

14/16-Bit IlP-Compatible 2-Chip AID Converter

..JI-

ICL7104/1CL8068

14/16-Bit

ICL7109

12-Bit

ICL7135

41/2-Digit BCD Output AID Converter

~P-Compatible

~P-Compatible

2-Chip AID Converter

AID Converter

AID SUCCESSIVE APPROXIMATION
~P-Compatible

ADC0802/3/4

8-Bit

CA331 0/CA331 OA

CMOS 10-Bit AID Converter with Internal Track and Hold

AID Converter

HI-574A

Fast, Complete 12-Bit AID Converter with Microprocessor Interface

HI5812

Low Power, Sampling 12-Bit AID Converter

HI-674A

12~s,

HI-774

8~s

Complete 12-Bit AID Converter with Microprocessor Interface

Complete 12-Bit AID Converter with Microprocessor Interface

AID CONVERTERS FLASH
HI3304

4-Bit 25 MSPS AID Converter

HI1826

6-Bit 140 MSPS AID Converter

HI1866

6-Bit 140 MSPS AID Converter

HI3306

6-Bit 15 MSPS AID Converter

HI-5701

6-Bit 30 MSPS AID Converter

HI3318

8-Bit 15 MSPS AID Converter

HI1386

8-Bit 75 MSPS AID Converter

HI1396

8-Bit 125 MSPS AID Converter

HI1166

8-Bit 250 MSPS AID Converter

HI1276

8-Bit 500 MSPS AID Converter

D/A CONVERTERS
AD7520

10/12-Bit Multiplying DIA Converter

AD7521

10/12-Bit Multiplying DIA Converter

AD7530

10/12-Bit Multiplying DIA Converter

2-37

Z
WW

ccz

~8

Data Acquisition Products
AD7531

10/12-Bit Multiplying D1A Converter

AD7523

8-Bit Multiplying D/A Converter

AD7533

10-Bit Multiplying D/A Converter

AD7541

l2-Bit Multiplying D/A Converter

AD7545

l2-Bit Buffered Multiplying CMOS DAC

HI-DAC80V

l2-Bit, Low Cost, Monolithic D/A Converter

HI-DAC85V

l2-Bit, Low Cost, Monolithic D/A Converter

DIA CONVERTERS HIGH SPEED
HI2304

Triple 8-Bit 20MHz D/A Converter

Hlll06

8-Bit 35MHz D/A Converter

HI1260

Triple 8-Bit 35MHz D/A Converter

HI20206

Triple 8-Bit 35MHz D/A Converter

HI117l

8-Bit 40MHz CMOS D/A Converter

HI1178

Triple 8-Bit 40MHz D/A Converter

HI1177

Dual 8-Bit 40MHz D/A Converter

HI3338

8-Bit 50MHz D/A Converter

HI20203

8-Bit l60MHz D/A Converter

HI3050

Triple 10-Bit 50MHz D/A Converter

HI2307

Triple 10-Bit 50MHz D/A Converter

ANALOG SWITCHES
DG18l

Dual SPST (30Q) Switch

DG182

Dual SPST (75Q) Switch

DG184

Dual DPST (30Q) Switch

DG185

Dual DPST (75Q) Switch

DG187

SPST (30Q) Switch

DG188

SPST (75Q) Switch

DG190

Dual SPST (30Q) Switch

DG19l

Dual SPST (75Q) Switch

DG200

Dual SPST CMOS Analog Switch

DG201A

Quad Monolithic SPST CMOS Analog Switch

DG202

Quad Monolithic SPST CMOS Analog Switch

DG2ll

Quad Monolithic SPST CMOS Analog Switch

DG2l2

Quad Monolithic SPST CMOS Analog Switch

DG300A

Dual SPST TTL Compatible CMOS Analog Switch

DG301A

SPOT TTL Compatible CMOS Analog Switch

DG302A

Dual DPST TTL Compatible CMOS Analog Switch

DG303A

Dual SPDT TTL Compatible CMOS Analog Switch

DG308A

Quad Monolithic SPST CMOS Analog Switch

DG309

Quad Monolithic SPST CMOS Analog Switch

DG401/403/405

Dual CMOS Analog Switches

DG4ll/4l2/4l3

Quad SPST CMOS Analog Switches

DG441 1442

Quad SPST CMOS Analog Switches

HI-200

Dual SPST CMOS Analog Switch

HI-20l

Quad SPST CMOS Analog Switch

2-38

Data Acquisition Products
HI-201HS

High-Speed Quad SPST CMOS Analog Switch

HI-222

High Frequency Video Switch

HI-300

Dual SPST CMOS Analog Switch

HI-301

SPOT CMOS Analog Switch

HI-302

Dual DPST CMOS Analog Switch

HI-303

Dual SPOT CMOS Analog Switch

HI-304

Dual SPST CMOS Analog Switch

HI-305

SPOT CMOS Analog Switch

HI-306

Dual DPST CMOS Analog Switch

HI-307

Dual SPOT CMOS Analog Switch

HI-381

Dual SPST CMOS Analog Switch

HI-384

Dual DPST CMOS Analog Switch

HI-387

SPOT CMOS Analog Switch

HI-390

Dual SPDT CMOS Analog Switch

HI-5040

SPST CMOS Analog Switch

HI-5041

Dual SPST CMOS Analog Switch

HI-5042

SPOT CMOS Analog Switch

HI-5043

Dual SPDT CMOS Analog Switch

HI-5044

DPST CMOS Analog Switch

HI-5045

Dual DPST CMOS Analog Switch

HI-5046

DPOT CMOS Analog Switch

HI-5046A

OPDT CMOS Analog Switch

HI-5047

4PST CMOS Analog Switch

HI-5047A

4PST CMOS Analog Switch

HI-5048

Dual SPST CMOS Analog Switch

HI-5049

Dual DPST CMOS Analog Switch

HI-5050

SPDT CMOS Analog Switch

HI-5051

Dual SPDT CMOS Analog Switch

&.LCf)

01Z

ww

...JI-

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t!8

IH401A

Quad Varafet Analog Switch

IH5040

SPST 75 Ohm High-Level CMOS Analog Switch

IH5041

Dual SPST 75 Ohm High-Level CMOS Analog Switch

IH5042

SPOT 75 Ohm High-Level CMOS Analog Switch

IH5043

Dual SPOT 75 Ohm High-Level CMOS Analog Switch

IH5044

DPST 75 Ohm High-Level CMOS Analog Switch

IH5045

Dual OPST 75 Ohm High-Level CMOS Analog Switch

IH5046

OPOT 75 Ohm High-Level CMOS Analog Switch

IH5047

4PST 75 Ohm High-Level CMOS Analog Switch

IH5052

Quad SPST CMOS Analog Switch

IH5053

Quad SPST CMOS Analog Switch

IH5140

SPST High-Level CMOS Analog Switch

IH5141

Dual SPST High-Level CMOS Analog Switch

IH5142

SPOT High-Level CMOS Analog Switch

IH5143

Dual SPOT High-Level CMOS Analog Switch

IH5144

DPST High-Level CMOS Analog Switch

IH5145

Dual DPST High-Level CMOS Analog Switch

2-39

Data Acquisition Products
IHS148

Dual SPST High-Level CMOS Analog Switch

IHS149

Dual DPST High-Level CMOS Analog Switch

IHS1S0

SPDT High-Level CMOS Analog Switch

IHS1S1

Dual SPDT High-Level CMOS Analog Switch

IHS341

Dual SPST CMOS RFNideo Switch

IHS3S2

Quad SPST CMOS RFNideo Switch

MULTIPLEXERS
DG406/407

16-Channel/Dual 8-Channel CMOS Analog Multiplexer

DG408/409

Single 8-Channel/Differential 4-Channel CMOS Analog Multiplexers

DGS06A

16-Channel/Dual 8-Channel CMOS Analog Multiplexer

DGS07A

16-ChanneI/DuaI8-Channel CMOS Analog Multiplexer

DGS08A

8-Channel/Dual 4-Channel CMOS Analog Multiplexer

DGS09A

8-Channel/Dual 4-Channel CMOS Analog Multiplexer

DGS26

16-Channel/Dual 8-Channel CMOS Latchable Multiplexer

DGS27

16-Channel/Dual 8-Channel CMOS Latchable Multiplexer

DGS28

8-Channel/Dual 4-Channel Latchable Multiplexer

DGS29

8-Channel/Dual 4-Channel Latchable Multiplexer

HI-1818A11828A

Low Resistance Single 8/Differential 4-Channel CMOS Analog Multiplexers

HI-S06

Single 16/Differential 8-Channel CMOS Analog Multiplexer

HI-S07

Single 16/Differential 8-Channel CMOS Analog Multiplexer

HI-S06A

Single 16/Differential 8-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-S07A

Single 16/Differential 8-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-S08

Single 8/Differential 4-Channel CMOS Analog Multiplexer

HI-S09

Single 8/Differential 4-Channel CMOS Analog Multiplexer

HI-S08A

Single 8/Differential 4-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-S09A

Single a/Differential 4-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-S16

16-Channel/Differential 8-Channel CMOS High-Speed Analog Multiplexer

HI-S18

8-Channel/Differential 4-Channel CMOS High-Speed Analog Mulitplexer

HI-S24

4-Channel Wideband and Video Multiplexer

HI-S39

Monolithic, 4-Channel, Low Level, Differential Multiplexer

HI-S46

Single 16/Differential 8-Channel CMOS Analog Mulitplexer with Active Overvoltage Protection

HI-S47

Single 16/Differential 8-Channel CMOS Analog Mulitplexer with Active Overvoltage Protection

HI-S48

Single 8/Differential 4-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-S49

Single 8/Differential 4-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

IH6108

a-Channel CMOS Analog Multiplexer

IH6208

4-Channel Differential CMOS Analog Multiplexer

DISPLAY DRIVERS
CA3161

BCD to Seven Segment Decoder/Driver

CA3168

2-Digit BCD to Seven Segment Decoder/Driver

ICM7211

4-Digit LCD/LED Display Driver

ICM7212

4-Digit LCD/LED Display Driver

ICM7218

8-Digit LED Multiplexed Display Driver

ICM7228

8-Digit LED Multiplexed Display Driver

ICM7231

Numeric/Alphanumeric Triplexed LCD Display Driver

2-40

Data Acquisition Products
ICM7232

Numeric/Alphanumeric Triplexed LCD Display Driver

ICM7243

B-Character IJP-Compatible LED Display Driver

REAL-TIME CLOCK
ICM7170

IJP-Compatible Real-Time Clock

COUNTERS WITH DISPLAY DRIVERSfTlMEBASE GENERATORS
ICM7207/A

CMOS Timebase Generator

ICM720B

7-Digit LED Display Counter

ICM7209

Timebase Generator

ICM7213

One Second/One Minute Timebase Generator

ICM7216A1B/D

B-Digit Multi-Function Frequency CounterlTimer

ICM7217

4-Digit LED Display Programmable Up/Down Counter

ICM7224

41/2-Digit LCD/LED Display Counter

ICM7226A1B

B-Digit Multi-Function Frequency CounterlTimer

ICM7249

5 1/2-Digit LCD IJ-Power Event/Hour Meter
u.C/)

O~

SPECIAL PURPOSE

Z

AD590

2-Wire Current Output Temperature Transducer

ICLB069

Low Voltage Reference

DATA COMMUNICATIONS
ICL232

+5 Volt Powered Dual RS-232 Transmitter/Receiver

HIN200

+5 Volt 5T/OR Powered Dual RS-232 Transmitter/Receiver

HIN201

+5 Volt 2T/2R Powered Dual RS-232 Transmitter/Receiver

HIN202

+5 Volt 2T/2R Powered Dual RS-232 Transmitter/Receiver

HIN204

+5 Volt 4T/OR Powered Dual RS-232 Transmitter/Receiver

HIN206

+5 Volt 4T/3R Powered Dual RS-232 Transmitter/Receiver

HIN207

+5 Volt 5T/3R Powered Dual RS-232 Transmitter/Receiver

HIN20B

+5 Volt 4T/4R Powered Dual RS-232 Transmitter/Receiver

HIN209

+5 Volt 3T/5R Powered Dual RS-232 Transmitter/Receiver

HIN211

+5 Volt 4T/4R Powered Dual RS-232 Transmitter/Receiver

HIN213

+5 Volt 4T/5R Powered Dual RS-232 Transmitter/Receiver

2-41

WW
..J~

mz
~8

r------

Digital Signal Processing Products - - - - - - ,

MULTIPLIERS
HMA510

16 x 16-Bit CMOS Parallel Multiplier Accumulator
16 x 16-Bit CMOS Parallel Multipliers

HMU16/HMU17

ONE DIMENSIONAL FILTERS
DECI· MATE

Harris HSP43220 Decimating Digital Filter Development Software
Serial I/O Filter

HSP43124
HSP43168

Dual FIR Filter
Half Band Filter

HSP43216
HSP43220
HSP43881

Decimating Digital Filter
Digital Filter

HSP43891

Digital Filter

TWO DIMENSIONAL FILTERS
HSP48901
HSP48908

3 x 3 Image Filter
Two Dimensional Convolver

SIGNAL SYNTHESIZERS
HSP45102
HSP45106
HSP45116

12-Bit Numerically Controlled Oscillator
16-Bit Numerically Controlled Oscillator
Numerically Controlled Oscillator/Modulator

HSP45116A

Numerically Controlled Oscillator/Modulator
HSP45116 Evaluation Daughter Board

HSP45116-DB

SPECIAL FUNCTION
HSP45240

Address Sequencer

HSP45256
HSP48410

Binary Correlator
Histogrammer/Accumulating Buffer

HSP9501

Programmable Data Butter

HSP9520/9521
HSP-EVAL

Binary Correlator
DSP Evaluation Platform

COMMUNICATIONS
HSP50016

Digital Down Converter

HSP50110

Digital Quadrature Tuner

HSP50210
HSP5011 0/21 OEVAL

Digital Costas Loop
Demo Chipset Evaluation Board

HSP50306

QPSK Demodulator (Note 1)

HSP50307

Burst QPSK Modulator (Note 1)

HSP50307EVAL

Burst QPSK Modulator Evaluation Board

HSP50214
HSP50215
NOTES:

Programmable Downconverter (Note 1)
Programmable Upconverter (Note 2)

1. New Product Offerings
2. New Product Offerings In Short Term Road Map

FOR MORE INFORMATION CONTACT YOUR LOCAL SALES OFFICE OR DISTRIBUTOR

2-42

3
OPERATIONAL AMPLIFIERS

PAGE
SELECTION GUIDE .............................................................................. .

3-4

OPERATIONAL AMPLIFIER DATA SHEETS
CA124, CA224, CA324, Quad, 1MHz, Operational Amplifiers for Commercial, Industrial, and Military Applications .....
LM324, LM2902

3-17

CA 158, CA 158A,
CA258, CA258A,
CA358, CA358A,
CA2904,
LM358, LM2904

Dual, 1MHz, Operational Amplifiers for Commercial Industrial, and Military Applications ...... .

3-22

CA741 , CA741C,
CA1458,
CA1558, LM741 ,
LM741C, LM1458

Single and Dual, High Gain Operational Amplifiers
for Military, Industrial and Commercial Applications ....................................•...

oJ

«C/)
Za:

O!:!:!
-u.

!;;::::i
a:c.
W:li

:5«
3-29

CA3020, CA3020A

8MHz Power Amps For Military, Industrial and Commercial Equipment ......................... .

3-34

CA3060

110kHz, Operational Transconductance Amplifier Array ............................... .

3-35

CA3078, CA3078A

2kHz, Micropower Operational Amplifier ........................................... .

3-36

CA3080, CA3080A

2MHz, Operational Transconductance Amplifier (OTA) ............................... .

3-45

CA3094, CA3094A,
CA3094B

30M Hz, High Output Current Operational Transconductance Amplifier (OTA) .............. .

3-56

CA31 00

38M Hz, Operational Amplifier ................................................... .

3-57

CA3130, CA3130A

15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output ................. .

3-64

CA3140, CA3140A

4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output ................ .

3-79

CA3160, CA3160A

4MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output .................. .

3-98

CA3193, CA3193A

1.2MHz, BiCMOS Precision Operational Amplifiers .................................. .

3-114

CA3240, CA3240A

Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output ........... .

3-115

CA3260, CA3260A

4MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output ............... , .. .

3-129

CA3280, CA3280A

Dual, 9MHz, Operational Transconductance Amplifier (OTA) ........................... .

3-132

CA3420, CA3420A

O.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifiers ............ .

3-141

CA3440, CA3440A

63kHz, Nanopower, BiMOS Operational Amplifiers .................................. .

3-142

CA3450

220M Hz, Video Line Driver, High Speed Operational Amplifier ......................... .

3-143

CA5130, CA5130A

15MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output ... .

3-144

CA5160, CA5160A

4MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output .... .

3-145

CA5260, CA5260A

3M Hz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output ....... .

3-146

3-1

Operational Amplifiers

(Continued)

CA5420, CA5420A

0.5MHz, Low Supply Voltage, Low Input Current.BiMOS Operational Amplifiers.... .........

3-150

CA5470

Quad, 14MHz, Microprocessor BiMOS-E Operational Amplifier with MOSFET InpLiVBipolar Output.

3-156

HA-2400, HA-2404,
HA-2405

40MHz, PRAM Four Channel Programmable Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-161

HA-2406

30MHz, Digitally Selectable Four Channel Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . ..

3-167

HA-2444

50MHz, Selectable, Four Channel Video Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . ..

3-173

HA-2500, HA-2502,
HA-2505

12MHz, High Input Impedance, Operational Amplifiers. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . ..

3-174

HA-2510, HA-2512,
HA-2515

12MHz, High Input Impedance, Operational Amplifiers. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . ..

3-181

HA-2520, HA-2522,
HA-2525

20M Hz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers. . . ..

3-188

HA-2529

20M Hz, High Input Impedance, High Slew Rate Operational Amplifier. . . . . . . . . . . . . . . . . . . ..

3-196

HA-2539

600MHz, Very High Slew Rate Operational Amplifier. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..

3-197

HA-2540

400MHz, Fast Settling Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-205

HA-2541

40MHz, Fast Settling, Unity Gain Stable, Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . ..

3-213

HA-2542

70MHz, High Slew Rate, High Output Current Operational Amplifier. . . . . . . . . . . . . . . . . . . . ..

3-222

HA-2544

50MHz, Video Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-233

HA-2548

150M Hz, High Slew Rate, Precision Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . .. ..

3-244

HA-2600, HA-2602,
HA-2605

12MHz, High Input Impedance Operational Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-245

HA-2620, HA-2622,
HA-2625

100MHz, High Input Impedance, Very Wideband, Uncompensated Operational Amplifiers. . . ..

3-252

HA-2640, HA-2645

4MHz, High Supply Voltage Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-259

HA-2839

600MHz, Very High Slew Rate Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-265

HA-2840

600MHz, Very High Slew Rate Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-266

HA-2841

50MHz, Fast Settling, Unity Gain Stable, Video Operational Amplifier. . . . . . . . . . . . . . . . . . . ..

3-273

HA-2842

80MHz, High Slew Rate, High Output Current, Video Operational Amplifier. . . . . . . . . . . . . . ..

3-281

HA-2850

470MHz, Low Power, High Slew Rate Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-290

HA-4741

Quad, 3.5MHz, Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . ..

3-291

HA-5002

110MHz, High Slew Rate, High Output Current Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-297

HA-5004

1OOMHz Current Feedback Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-305

HA5013

Triple, 125MHz Video Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-306

HA-5020

1OOMHz Current Feedback Video Amplifier With Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-320

HA5022

Dual, 125MHz, Video Current Feedback Amplifier with Disable. . . . . . . . . . . . . . . . . . .. . . . . ..

3-340

HA5023

Dual 125MHz Video Current Feedback Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-356

HA5024

Quad 125MHz Video Current Feedback Amplifier with Disable. . . . . . . . . . . . . . . . . . . . . . . . ..

3-370

HA5025

Quad, 125MHz Video Current Feedback Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-386

HA-5033

250M Hz Video Buffer ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-399

HA-51 01 , HA-5111

10MHz and 100MHz, Low Noise, Operational Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-408

3-2

Operational Amplifiers

(Continued)

HA-5102, HA-5104,
HA-5112, HA-5114

Dual and Quad, 8M Hz and 60MHz, Low Noise Operational Amplifiers ................... .

3-419

HA-5127, HA-5127A

8.5MHz, Ultra-Low Noise Precision Operational Amplifier ............................. .

3-432

HA-5130, HA-5135

2.5MHz, Precision Operational Amplifiers .......................................... .

3-441

HA-5134

4MHz, Precision, Quad Operational Amplifier ....................................... .

3-450

HA-5137, HA-5137A

63MHz, Ultra-Low Noise Precision Operational Amplifier .............................. .

3-458

HA-5142, HA-5144

Dual/Quad, 400kHz, Ultra-Low Power Operational Amplifiers .......................... .

3-466

HA-5147, HA-5147A

120MHz, Ultra-Low Noise Precision Operational Amplifiers ............................ .

3-474

HA-5160, HA-5162

1OOMHz, JFET Input, High Slew Rate, Uncompensated, Operational Amplifiers ............ .

3-482

HA-5170

8MHz, Precision, JFET Input Operational Amplifier .................................. .

3-489

HA-5177

2MHz, Ultra-Low Offset Voltage Operational Amplifier ................................ .

3-497

HA-5190, HA-5195

150MHz, Fast Settling Operational Amplifiers ....................................... .

3-498

HA-5221, HA-5222

100MHz, Single and Dual Low Noise, Precision Operational Amplifiers ................... .

3-506

HFA1100, HFA 1120

850MHz, Low Distortion Current Feedback Operational Amplifiers ...................... .

3-518

HFA1102

600MHz Current Feedback Amplifier with Compensation Pin ........................... .

3-528

HFA 1103

200MHz, Video Op Amp with High Speed Sync Stripper .............................. .

3-533

0:((1)

HFA1105

330MHz, Low Power, Current Feedback Video Operational Amplifier .................... .

3-539

HFAll06

315MHz, Low Power, Video Operational Amplifier with Compensation Pin ................ .

3-550

Ow
-u::
!;:~

HFA1109, HFAll49

550MHz, Low Power, Current Feedback Operational Amplifiers ........................ .

3-564

HFA 1110

750MHz, Low Distortion Unity Gain, Closed Loop Buffer .............................. .

3-565

HFA 1112

850M Hz, Low Distortion Programmable Gain Buffer Amplifier .......................... .

3-573

HFA 1113

850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier ............ .

3-585

HFA 1114

850MHz Video Cable Driving Buffer .............................................. .

3-600

HFA 1115

225M Hz, Low Power, Output Limiting, Closed Loop Buffer Amplifier ..................... .

3-605

HFA 1118, HFA 1119

500MHz Programmable Gain Video Buffers with Output Limiting and Output Disable ........ .

3-611

HFA 1130

850M Hz, Output Limiting, Low Distortion Current Feedback Operational Amplifier .......... .

3-612

HFA 1135

360M Hz, Low Power, Video Operational Amplifier with Output Limiting ................... .

3-623

HFA 1145

330M Hz, Low Power. Current Feedback Video Operational Amplifier with Output Disable .... .

3-628

-I

HFA 1205

Dual, 400MHz, Low Power, Video Operational Amplifier .............................. .

3-640

HFA1212

Dual 350MHz, Low Power Closed Loop Buffer Amplifier .............................. .

3-647

HFA 1245

Dual, 530MHz, Low Power, Video Operational Amplifier with Disable .................... .

3-657

HFAl405

Quad, 560MHz, Low Power, Video Operational Amplifier .............................. .

3-663

HFA1412

Quad, 350MHz, Low Power, Programmable Gain Buffer Amplifier ....................... .

3-676

ICL7611, ICL7612

l.4MHz, Low Power CMOS Operational Amplifiers .................................. .

3-689

ICL7621, ICL7641,
ICL7642

Dual/Quad, Low Power CMOS Operational Amplifiers ................................ .

3-700

ICL7650S

2MHz, Super Chopper-Stabilized Operational Amplifier ............................... .

3-711

Operational Amplifiers Glossary of Terms ........................................................... .

3-721

3-3

Z£C

£CQ.

W::iE
~o:(

Selection Guide
WIDEBAND:

MiniMax Limits at 25°C, Unless Otherwise Specified

GBWP
(TYP)
(MHz)

FPBW
(TYP)
(MHz)

SLEW
RATE
(TYP)
(V/l1s)

HFA1112

850

260

HFAl113

850

260

HFAl114

850

260

2400

HFA1110

750

150

1300

HA4600

400

HA-5033

250

HFA1115
HA-5002

DEVICE

AVOL
(dB)/
AZOL
(V/mA)

PSRR
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

35000

39

26.0

35000

39

26.0

39

26.0

39

26.0

54

25.0

MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(nA)

2400

+1, -1, +2

25

2400

+1,-1, +2

25

+1, ·1, +2

25

=i5000

+1

25

40000

1700

+1

10

50000

17.5

1100

+1

15

35000

225

140

1100

·

+1, ·1, +2

10

15000

110

20.7

1300

·

+1

20

7000

140

1100

·

+1, ·1, +2

10

15000

140

1100

·

+1, ·1, +2

10

CMRR
(dB)

BUFFERS

·

·

13.0

·

45

7.1

54

10.0

·

45

6.1

15000

·

45

6.1

DUAL BUFFERS
HFA1212

340

QUAD BUFFERS
HFA1412

225

SINGLE OP AMPS
HFA1100

850

300

2300

500
(Note 1)

1

6.0

40000

40

45

26.0

HFA1120

850

300

2300

500
(Note 1)

1

6.0

40000

40

45

26.0

HFA1130

850

300

2300

500
(Note 1)

1

6.0

40000

40

45

26.0

HA-2539

600

9.5

600

80

10

10.0

20000

60

60

25.0

HA-2839

600

10.0

625

86

10

2.0

14500

75

75

15.0

HA-2840

600

10.0

625

86

10

2.0

14500

75

75

15.0

HFA1109

500

TBD

1200

500
(Note 1)

1

5.0

15000

47

50

10.0

HFA1149

500

TBD

1200

500
(Note 1)

1

5.0

15000

47

50

10.0

HA-2850

470

.5.4

340

86

10

2.0

14500

75

75

8.0

HA-2540

400

6.0

400

80

10

10.0

20000

60

60

25.0

HFA1105

350

140

1000

500
(Note 1)

1

5.0

15000

47

50

6.1

HFA1145

350

140

1000

500
(Note 1)

1

5.0

15000

47

50

6_1

HFA1135

350

170

1200

500
(Note 1)

1

5.0

15000

47

50

7.1

HFAll06

315

100

700

500
(Note 1)

1
(Note 2)

5.0

15000

47

50

6.1

HA·5190

150

6.5

200

83

5

5.0

15000

74

70

28.0

HA-5195

150

6.5

200

83

5

6.0

15000

74

70

28.0

HA-5147

140

0.5

35

117

10

0.1

80

100

86

4.0

NOTE: Bold type designates a new product from Harris.
3·4

Selection Guide
WIDEBAND:

MiniMax Limits at 25°C, Unless Otherwise Specified (Continued)

DEVICE

GBWP
(TYP)
(MHz)

FPBW
(TYP)
(MHz)

SLEW
RATE
(TYP)
(VlIlS)

AVOL
(dBY
AZOL
(VIrnA)

MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(nA)

CMRR
(dB)

PSRR
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

HA-5147A

120

0.5

35

120

10

0.03

40

114

lOB

4.0

HA-5020

100

17.5

1100

3500
(Note 1)

1

B.O

BOOO

60

64

10.0

HA-2620

100

0.6

35

100

5
(Note 2)

4.0

15

BO

BO

3.7

HA-2622

100

0.6

35

9B

5

5.0

25

74

74

4.0

(Note 2)
HA-2625

100

0.6

35

9B

5
(Note 2)

5.0

25

74

74

4.0

HA-5111

100

O.B

50

120

10
(Note 2)

3.0

200

BO

BO

6.0

HA-5160

100

1.9

120

97

10
(Note 2)

3.0

0.05

74

74

10.0

HA-5162

100

1.10

70

BB

10
(Note 2)

15.0

0.065

70

70

12.0

HA-5221

100

0.56

35

106

1

0.75

BO

B6

B6

11.0

....J
«(J)

HA-2842C

150

18.0

1200

94

2
(Note 2)

3.0

10000

80

70

15_0

O!!!
-IL

HA-2B42

BO

6.0

400

94

2

3.0

10000

BO

70

15.0

HA-2B41

50

3.B

240

BB

1

3.0

10000

BO

70

11.0

HFA1245

530

150

1050

500
(Notal)

1

5

15000

45

48

6.1

HFA1205

400

180

1275

500
(Note 1)

1

5

15000

45

48

6.1

HA5022

125

28

475

1000
(Note 1)

1

3.0

8000

53

60

10.0

HA5023

125

28

475

1000
(Note 1)

1

3.0

BOOO

53

60

10.0

HA-5222

100.0

0.56

35

106

1

0.75

BO.O

B6

B6

11.0

HA-5112

60.0

0.32

20

100

10

2.0

200.0

B6

B6

2.5

28

475

3500
(Note 1)

1

3.0

8000

53

60

10_0

!;;:::::i

DUAL OP AMPS

TRIPLE OP AMPS
HA5013

125

QUADOPAMPS
HFA1405

400

TBD

1000

500
(Note 1)

1

5

15000

45

48

6.1

HA5024

125

28

475

3500
(Note 1)

1

3.0

SOOO

53

60

10.0

HA5025

125

28

475

3500
(Note 1)

1

3.0

8000

53

60

10.0

HA-5114

60.0

0.32

20.0

100

10

2.5

200.0

B6

B6

1.63

HA-2444

50.0

5.1

160

71

1

7.0

15000

70

65

6.25

NOTE: Bold type designates a new product from Harris.

3-5

Za:

a:

11.

W::!:

~cr:

Selection Guide
WIDEBAND: MinIMax Limits at 25°C, Unless Otherwise Specified (Continued)
GBWP
(TYP)
(MHz)

FPBW
(TYP)
(MHz)

SLEW
RATE
(TYP)
(VlIlS)

HA-2400

40.0

0.95

30.0

HA-2404

40.0

0.95

HA-2405

40.0

0.95

DEVICE

MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(nA)

CMRR
(dB)

PSRR
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

94 .

10
(Note 2)

9.0

200.0

80

74

1.5

30.0

94

10
(Note 2)

9.0

200.0

80

74

1.5

30.0

94

10
(Note 2)

9.0

250.0

74

74

1.5

AYOL
(dBY
AZOL
(VIrnA)

NOTES:
1. AZOL applies to current feedback amplifiers only (HA-5004, HA-502X, HFA 11 XX, HFA 12XX, HFA 14XX).
2. Product features an external compensation pin to limit bandwidth for noise reduction or to allow unity gain operation.

HIGH SLEW RATE: MinIMax Limits at 25°C, Unless Otherwise Specified
SLEW
RATE
(TYP)
(V/JUI)

GBWP
(TYP)
(MHz)

FPBW
(TYP)
(MHz)

HFAll12

2400

850

HFAll13

2400

850

HFA1114

2400

850

260

DEVICE

AYOL
(dBY
AZOL
(VIrnA)

PSRR
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

35000

39

26.0

35000

39

26.0

39

26.0

MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(nA)

260

+1, -1, +2

25.0

260

+1, -1, +2

25.0

+1, -1, +2

25

35000

CMRR
(dB)

BUFFERS

-

-

HA4600

1700

400

-

+1

10

50000

-

13.0

HFAlll0

1300

750

150

+1

25.0

40000

39

26.0

HA-5002

1300

110

20.7

-

+1

20.0

7000

54

10.0

HFA1115

1100

225

140

-

+1, -1, +2

10

15000

HA·5033

1100

250

17.5

+1

15.0

35000

340

140

-

+1,-1,+2

10

15000

225

140

-

+1, -1, +2

10

-

45

7.1

54

25.0

-

45

6.1

15000

-

45

6.1

DUAL BUFFERS
HFA1212

1100

QUAD BUFFERS
HFA1412

1100

SINGLE OP AMPS
HFAll00

2300

850

300

500
(Note 1)

1

6.0

40000

40

45

26.0

HFAl120

2300

850

300

500
(Note 1)

1

6.0

40000

40

45

26.0

HFAl130

2300

850

300

500
(Note 1)

1

6.0

40000

40

45

26.0

HFA1109

1200

500

TBD

500
(Note 1)

1

5.0

15000

47

50

10.0

HFA1149

1200

500

TBD

500
(Note 1)

1

5.0

15000

47

50

10.0

HFA1135

1200

350

170

500
(Note 1)

1

5.0

15000

47

50

7.1

HA-2842C

1200

150

18.0

94

2
(Note 2)

3.0

10000

80

70

15.0

NOTE: Bold type designates a new product from Harris.

3-6

Selection Guide
HIGH SLEW RATE: MinIMax Limits at 25°C, Unless Otherwise Specified (Continued)
MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(nA)

CMRR
(dB)

PSRR
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

3500
(Note 1)

1

8.0

BOOO

60

64

10.0

140

500
(Note 1)

1

5.0

15000

47

50

6.1

350

140

500
(Note 1)

1

5.0

15000

47

50

6.1

600

10.0

86

10

2.0

14500

75

75

15.0

SLEW
RATE
(TYP)
(V/IlS)

GBWP
(TYP)
(MHz)

FPBW
(TYP)
(MHz)

HA·5020

1100

100

17.5

HFA1105

1000

350

HFA1145

1000

HA·2839

625

DEVICE

AVOL
(dB)I
AZOL
(V/mA)

HA·2840

625

600

10.0

86

10

2.0

14500

75

75

15.0

HA·2539

600

600

9.5

80

10

10.0

20000

60

60

25.0

HA·2540

400

400

6.0

80

10

10.0

20000

60

60

25.0

HA·2842

400

80

6.0

94

2

3.0

10000

80

70

15.0

HA·2542

350

70

5.5

80

2
(Note 2)

10.0

35000

70

70

34.5

HA·2850

340

400

5.4

86

10

2.0

14500

75

75

8.0

HA·2841

240

50

3.8

88

1

3.0

10000

80

70

11.0

HA·2541

250

40

4.0

80

1

2.0

35000

70

70

40.0

HA·5190

200

150

6.5

83

5

5.0

15000

74

70

28.0

lci::::i

HA·5195

200

150

6.5

83

5

6.0

15000

74

70

28.0

W:i

HA·2544

150

50

4.2

71

1

15.0

15000

75

70

12.0

HA·2520

120

20

2

80

3
(Note 2)

6.0

200

80

60

6.0

HA·2522

120

20

2

76

3
(Note 2)

10.0

250

74

74

6.0

HA·2525

120

20

2

76

3
(Note 2)

10.0

250

74

74

6.0

HA·5160

120

100

1.9

97

10
(Note 2)

3.0

0.05

74

74

10.0

DUAL OP AMPS
HFA1205

1275

400

140

500
(Note 1)

1

5

15000

45

48

6.1

HFA1245

1050

530

130

500
(Note 1)

1

5

15000

45

48

6.1

HA5022

475

125

28

1000
(Note 1)

1

3.0

SOOO

53

60

10.0

HA5023

475

125

28

1000
(Note 1)

1

3.0

8000

53

60

10.0

CA3260

125

9.0

1.99

94

1

3.0

5000

60

66

2.4

CA3260A

125

9.0

1.99

94

1

0.5

5000

94

94

2.4

125

28

3500
(Note 1)

1

3.0

8000

53

60

10.0

TRIPLE OP AMPS
HA5013

475

NOTE: Bold type designates a new produC1 from Harris.

3·7

...I

oct(/)
Oll:!
-u..

Za:
a:

11.

~oct

Selection Guide
HIGH SLEW RATE: MinIMax Limits at 25°C, Unless Otherwise Specified (Continued)

DEVICE

SLEW
RATE
(TYP)
(V/1UI)

GBWP
(TYP)
(MHz)

FPBW
(TYP)
(MHz)

AYOL
(dBY
AZOL
(VIrnA)

MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(nA)

CMRR
(dB)

PSRR
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

QUADOPAMPS
HFA1405

1000

400

TBD

500
(Note 1)

1

5,0

15000

45

48

6.1

HA5024

475

125

28

3500
(Note 1)

1

3.0

8000

53

60

10.0

HA5025

475

125

28

3500
(Note 1)

1

3.0

8000

53

60

10.0

HA-2444

160

50

5.1

71

1

7.0

15000

70

65

6.25

NOTES:
1. AZOL applies to current feedback amplifiers only (HA-5004, HA-502X, HFA11 XX, HFA 12XX, HFA14XX).
2. Product features an external compensation pin to limit bandwidth for noise reduction or to allow unity gain operation.

VIDEO:

Typical Values at 25°C, Unless Otherwise Specified
O.ldB
FLAT
GAIN
(MHz)

GBWP
(MHz)

SLEW
RATE
(V/IUI)

SUPPLY
SUPPLY
OUTPUT VOLTAGE CURRENT
CURRENT RANGE
(mAlOP
(±V)
(mA)
AMP)

FEATURES

DIF.
GAIN
(%)

HA4600

Video Buffer wlOutput Disable

0.01

0.01

250

480

1700

20

4.5 - 5.5

10.5

HFAlll0

+ I, Std. Buffer Pinout

0.02

0.02

>100

750

1300

60

4.5-5.5

21.0

HFA1112

-I, +1, +2 (Selectable) Standard
Op Amp Pinout

0.02

0.04

>100

850

2400

60

4.5-5.5

21.0

HFA1113

-I, +1, +2 (Selectable) Standard
Op Amp Pinout, VOUT Limits

0.02

0.04

>100

850

2400

60

4.5 - 5.5

21.0

HFA1114

-I, +1, +2 (Selectable)
Summing Node Pinout

0.02

0.04

>100

850

1100

60

4.5 - 5.5

21.0

HFA1115

-I, +1, +2 (Selectable) Standard
Op Amp Pinout, VOUT Limits

0.02

0.03

>50

225

1100

60

4.5-5.5

5.9

HA-5033

+ 1, Std. Buffer Pinout

0.03

0.02

250

1100

100

5-16

21.0

HA-5002

+ I, Std. Buffer Pinout

0.06

0.21

110

1300

200

5-20

8.3

0.02

0.02

>50

340

1100

60

4.5 - 5.5

5.9

0.02

0.02

>50

225

1100

60

4.5-5.5

5.9

DEVICE

OfF.
PHASE
(DEG)

BUFFERS

DUAL BUFFERS
HFA1212

-I, +1, +2 (Selectable)

QUAD BUFFERS
HFA1412

-I, +1, +2 (Selectable)

SINGLE OP AMPS
HFAll09

Ay ~ I, CFB, Wideband

0.02

0.03

100

500

1200

30

4.5 - 5.5

10.0

HFA1149

Ay ~ I, CFB, Programmable
Output Disable

0.02

0.03

100

500

1200

30

4.5 - 5.5

10.0

HFA1105

Ay ~ I, Low

Icc, CFB
Ay ~ I, Low Icc, CFB,

0.02

0.03

>50

350

1000

60

4.5 - 5.5

5.9

0.02

0.03

>50

350

1000

60

4.5-5.5

5.9

0.02

0.04

>50

360

1200

60

4.5-5.5

6.9

HFA1145

Output Disable
HFA1135

Ay ~ I, Low Icc, CFB,
Programmable Output Limiting

NOTE: Bold type deSignates a new product from Harris.

3-8

Selection Guide
VIDEO: Typical Values at 25°C, Unless Otherwise Specified (Continued)

DEVICE

FEATURES

DIF.
GAIN
(%)

DIF.
PHASE
(DEG)

O.ldB
FLAT
GAIN
(MHz)

GBWP
(MHz)

SLEW
RATE
(V/IlS)

0.02

0.05

100

315

700

60

HFA1106

HFA1105 with Compensation
Pin for Bandwidth Limiting

HA-2842

Av ~ 2, Cable Driver

0.02

0.03

>10

80

400

HA-5020

Av ~ 1, Output Disable, CFB
(Current Feedback)

0.02

0.03

5

100

1100

HFAll00

Av~

0.03

0.05

75

850

1, CFB

SUPPLY
OUTPUT VOLTAGE
CURRENT RANGE
(rnA)
(±V)

SUPPLY
CURRENT
(mAlOP
AMP)

4.5 - 5.5

5.9

100

6 ·17

14.2

32

4.5 -18

7.5

2300

60

4.5 - 5.5

21.0

HFAl120

HFA 1100 with Offset Adjust

0.03

0.05

75

850

2300

60

4.5-5.5

21.0

HFA1130

Av ~ 1, CFB, Programmable
Output Limiting

0.03

0.05

75

850

2300

60

4.5·5-5

21.0

HA-2544

Av~

0.03

0.03

5

50

150

35

8 - 17

10.0

HA-2841

Av ~ 1, Low Icc

0.03

0.03

>10

50

240

30

6-17

10.0

1

DUAL OP AMPS
HFA1245

Ay ~ 1, Low Icc, CFB,
Output Disable

0.02

0.03

50

530

1050

60

4.5 - 5.5

5~9

HFA1205

Ay ~ 1, Low Icc, CFB

0.03

0.03

>50

400

1275

60

4.5 - 5.5

5.9

eten

HA5022

Ay ~ 1, CFB, Output Disable

0.03

0.03

20

125

475

20

4.5 -18

7.5

O!:!:!
-u.

HA5023

Ay~1,CFB

0.03

0.03

20

125

475

20

4.5 -18

7.5

..J

~et

Ay~l,CFB

0.03

0.03

20

125

475

20

4.5 -18

7.5

Ay ~ 1, Low Icc, CFB

0.03

0.03

TBD

400

>1000

60

4.5 - 5.5

5.9

HA5024

Ay ~ 1, CFB, Output Disable

0.03

0.03

20

125

475

20

4.5 -18

7.5

HA5025

Ay~1,CFB

0.03

0.03

20

125

475

20

4.5 -18

7.5

HA-2444

IV ~ 1, 4-ChanneJ, Mux'd Output

0.03

0.03

10

50

160

25

8.5 -17

5.0

QUAD OP AMPS
HFA1405

NOTES:
1. Single Supply Range.

LOW NOISE: MiniMax Limits at 25°C, Unless Otherwise Specified

DEVICE

!cc:::i
a:: 0.
W::iii

TRIPLE OP AMPS
HA5013

Za::

NOISE
VOLTAGE
lkHz(TYP)
(nVNHz)

NOISE
CURRENT
1kHz (TYP)
(pANHz)

,
GBWP
(TYP)
(MHz)

SLEW
RATE
(TYP)
(V/IlS)

MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
. CURRENT
(nA)

SUPPLY
CURRENT
(mAlOPAMP)

SINGLE OP AMPS
HA-5127A

3.0

0.4

8.5

10

1

0.025

40

HA-5137A

3.0

0.4

63

20

5

0.025

40

4.0

HA-5147A

3.0

0.4

120

35

10

0.025

40

4.0

HA-5101

3.0

0.6

10

10

1

3.0

200

6.0

4.0

HA-5111

3.0

0.6

100

50

10

3.0

200

6.0

HA-5221

3.4

0.97

100

35

1

0.75

80

11.0

HA-5020

4.5

2.5
(Note 1)

100

1100

1

8.0

8000
(Note 1)

10.0

NOTE: Bold type designates a new product from Harris.

3-9

Selection Guide
LOW NOISE:

MiniMax Limits at 2SoC. Unless Otherwise Specified (Continued)

NOISE
VOLTAGE
1kHz (TYP)
(nVNHz)

NOISE
CURRENT
1kHz (TYP)

GBWP
(TYP)
(MHz)

SLEW
RATE
(TYPJ
(V/I1S)

MINIMUM
STABLE
GAIN

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(nA)

SUPPLY
CURRENT
(mAlOPAMP)

HFAll0S

3.5

2.5
(Note 1)

350

1000

1

5.0

15000

6.1

HFAll06

3.5

2.5
(Note 1)

315

700

1
(Note 2)

5.0

15000

6.1

HFAl135

3.5

2.5
(Note 1)

350

1200

1

5.0

15000

6.1

HFA1145

3.5

2.5
(Note 1)

350

1000

1

5.0

15000

7.1

HA·S190

6.0

5.0

150

200

5

5.0

15000

28.0
15.0

DEVICE

(pANHz)

HA-2839

6.0

6.0

600

625

10

2.0

14500

HA-2840

6.0

6.0

600

625

10

2.0

14500

15.0

HA-2539

6.0

6.0

600

600

10

10.0

20000

25.0

HA-2540

6:0

6.0

400

400

10

10.0

20000

25.0

0.3

0.1

2.5

HA-5170

10.0

0.01

8.0

8.0

1

HA-2542

10.0

3.0

70

350

2
(Note 2)

10.0

35000

34.5

HA-2541

10.0

4.0

40

250

1

2.0

35000

40.0

HA-5222

3.4

0.97

100

35

1

0.75

80

11.0

HFA1205

3.5

2.5
(Note 1)

400

1275

1

5.0

15000

6.1

HFA1245

3.5

2.5
(Note 1)

530

1050

1

5.0

15000

6.1

HA-5102

4.3

0.57

'8.0

3.0

1

2.0

200

2.5

HA-5112

4.3

0.57

60

20

10

2.0

200

2.5

HA5022

4.5

2.5
(Note 1)

125

475

1

3.0

8000
(Note 1)

10.0

HA5023

4.5

2.5
(Note 1)

125

475

1

3.0

8000
(Note 1)

10.0

HFA1405

3.5

2.5
(Note 1)

400

>1000

1

5.0

15000

6.1

HA-5104

4.3

0.57

8.0

3.0

1

2.5

200

1.63

HA-5114

4.3

0.57

60

20

10

2.5

200

1.63

HA5024

4.5

2.5
(Note 1)

125

475

1

3.0

8000
(Note 1)

10.0

HA5025

4.5

2.5
(Note 1)

125

475

1

3.0

8000
(Note 1)

10.0

HA-5134

7.0

1.0

4.0

1.0

1

0.2

50

2.0

DUAL OP AMPS

QUADOPAMPS

NOTES:
1. +Input. These are current feedback amplifiers. so value for -Input will be larger.
2. Product features an extemal compensation pin to limit bandwidth for additional noise reduction or to allow unity gain operation.

NOTE: Bold type designates a new product from Harris.

3·10

Selection Guide
GENERAL PURPOSE: Typical Values at 25°C, Unless Otherwise Specified

GBWP
(MHz)

SLEW
RATE
(V/jlS)

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT
(jtA)

SUPPLY
VOLTAGE
RANGE
(±V)

SUPPLY
CURRENT
(mAlOP
AMP)

1

50

150

6.0

7.00

8-17.5

10.0

1

38

70

1.0

0.7

7-18

8.5

SiMOS, CMOS Output, Output
Strobe

1

15

30

2.0

5.0pA

2.5-8

2.0

HA-2500

Wideband, High Slew Rate,
High Input Impedance

1

12

30

2.0

0.1

10-20

4.0

HA-2510

Wideband, High Slew Rate,
High Input Impedance

1

12

60

4.0

0.1

10-20

4.0

HA-2600

Wideband, Compensated, High
Input Impedance

1

12

7

0.5

0.001

4-22.5

3.0

HA-5101

Low NOise, High Performance

1

10

10

0.5

0.1

3-20

4.0

HA-5127A

Low Noise, Precision,
Compensated

1

8.5

10

0.01

0.Q1

5-22

3.5

HA-5170

JFET Input, Precision

1

8

8

0.1

20pA

5-22

1.9

CA3140A

SiMOS, Output Strobe Capability

1

4.5

9

2.0

1O.0pA

2-18

4.0

HA-2640

High Voltage, Compensated

1

4

5

2.0

0.01

10-50

3.2

Ol!!
-u..
~:::;

2.5-8

2.0

w:E

DESCRIPTION

MINIMUM
STABLE
GAIN

HA-2544

Ultra-Stable, High Performance

CA31 00

Wideband Amplifier

CA3130A

DEVICE
SINGLE OP AMPS

CA3160A

SiMOS, CMOS Output, Output
Strobe

1

4

10

2.0

5.0pA

CA3080

Operational Transconductance
Amp

1

2

75

0.4

2.0

2-18

1.0
1.7

CA741

Low Cost, Mil/Com Temp

1

1

0.5

1.0

0.08

5-22

LM741

Low Cost, Mil/Com Temp

1

1

0.5

1.0

0.08

5-22

1.7

HA-2520

Uncompensated

20

120

5.0

0.125

10-20

4.0

HA-5137A

Low Noise, Precision

HA-2620

Wideband, Uncompensated,
High Input Impedance

3
(Note 1)
5

80

20

0.Q1

0.01

5-22

3.5

5
(Note 1)

100

35

0.5

0.001

4-22.5

3.0

HA-5195

Wideband, Fast Settling

5

150

200

3.0

5.0

12-17.5

19.0

HA-5147A

Low Noise, Precision,
Wideband

10

140

35

0.01

0.01

5-22

3.5

HA-5111

Low NOise, High Performance,
Uncompensated

10
(Note 1)

100

50

0.5

0.1

3-20

4.0

CA3280A

Operational Transconductance
Amp

1

9

125

0.25

1.8

2-18

2.0

HA-5102

Low Noise, High Performance

1

8

3

0.5

0.13

3-20

1.5

CA3240A

SiMOS, High Input Impedance

1

4.5

9

2.0

10.0pA

2-18

4.0

CA3260A

SiMOS, CMOS Output, High
Input Impedance

1

4

10

2.0

5.0pA

2-8

0.6

CA5260A

Mil Temp Version of CA3260A

1

3

5

2.0

5.0pA

2.25-8

0.6

CA158A

Wide Supply Range, Mil Temp

1

1

0.25

1.0

0.02

1.5-16

0.75

CA1558

Low Cost, Mil Temp Range

1

1

0.5

1.0

0.08

5-22

1.7

DUAL

NOTE: Sold type deSignates a new product from Harris.

3-11

....I

«U)
Za:

a:

0.

~«

Selection Guide
GENERAL PURPOSE: Typical Values. at 25°C, Unless Otherwise Specified (Continued)

DESCRIPTION

MINIMUM
STABLE
GAIN

LM358

Wide Supply Range, Low Cost

LM1458

Low Cost

LM2904

Wide Supply Range, Ind. Temp

HA-5112

Low Noise, High Performance,
Uncompensated

CA5470

High Input Impedance, Wide
Supply Range, Mil Temp

HA-5104

Low NOise, High Performance

DEVICE

(J1A)

SUPPLY
VOLTAGE
RANGE
(±V)

SUPPLY
CURRENT
(mAlOP
AMP)

0.05

1.5-16

0.7

0.08

5-18

1.7

2.0

0.05

1.5-13

0.7

0.5

0.13

3-20

1.5

5.0

1.0pA

1.5-8

2.5

0.5

0.13

3-20

1.25
0.2

GBWP
(MHz)

SLEW
RATE
(V/IlS)

OFFSET
VOLTAGE
(mV)

BIAS
CURRENT

1

1

0.5

2.0

1

1

0.5

2.0

1

1

0.5

10

60

20

1

14

5

1

8

3

QUAD

CA124

Wide Supply Range, Mil Temp

1

1

0.5

2.0

0.045

2.5-16

HA-4741

Quad 741, Wide Supply

1

3.5

1.6

0.5

0.06

2-20

4.5

HA-5114

Low Noise, High Performance,
Uncompensated

10

60

20

0.5

0.13

3-20

1.25

LM2902

Low Cost, Ind. Temp

1

1

0.5

2.0

0.04

2.5 -16

0.2

LM324

Low Cost

1

1

0.5

2.0

0.05

2.5-16

0.2

NOTE:
1. Can be compensated to unity gain.

PRECISION: MinIMax Limits at 25°C, Unless Otherwise Specified

DEVICE

OFFSET
VOLTAGE
(mV)

VIO
DRIFT
(TYP)
(IlVfOC)

BIAS
CURRENT
(nA)

OFFSET
CURRENT
(nA)

CMRR
(dB)

PSRR
(dB)

GBWP
(TYP)
(MHz)

SLEW
RATE
(TYP)
(V/IlS)

AVOL
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

SINGLE OP AMPS
ICL7650S

0.005

0.02

0.01

0.02

120

120

2.0

2.5

135

3.0

HA-5127A

0.025

0.20

40.0

35.0

114

108

8.5

10.0

120

4.0

HA-5130

0.025

0.40

2.0

2.0

110

100

2.5

0.8

120

1.7

HA-5137A

0.025

0.20

40.0

35.0

114

108

63.0

20.0

120

4.0

HA-5147A

0.025

0.20

40.0

35.0

114

108

120.0

35.0

120

4.0

HA-5135

0.075

0.40

4.0

4.0

106

94

2.5

0.8

120

1.7
4.0

HA-5137

0.100

0.40

80.0

75.0

100

96

63.0

20.0

117

HA-5147

0.100

0.40

80.0

75.0

100

96

120.0

35.0

117

4.0

HA-5170

0.300

2.0

0.1

0.03

85

85

8.0

8.0

109

2.5

HA-5221

0.750

0.5

80.0

50.0

86

86

100.0

35.0

106

11.0

11.0

DUALOPAMPS
HA-5222

0.75

0.5

80

50

86

86

100.0

35.0

106

CA158A

2.0

7.0

50

10

70

65

1.0

0.5

94

1.5

HA-5102

2.0

3.0

200

75

86

86

8.0

3.0

100

2.5

HA-5112

2.0

3.0

200

75

86

86

60.0

20.0

100

2.5

ICL7621A

2.0

10.0

0.05

0.03

76

80

0.5

0.16

86

0.25

NOTE: Bold type designates a new product from Harris.

3-12

Selection Guide
PRECISION: MinIMax Limits at 25°C, Unless Otherwise Specified (Continued)
OFFSET
VOLTAGE
(mV)

VIO
DRIFT
(TVP)
(IlVJOC)

BIAS
CURRENT
(nA)

OFFSET
CURRENT
(nA)

CA3280A

0.5

3.0

5000

CA258A

3.0

7.0

80

CA358A

3.0

7.0

HA-5142

6.0

3.0

DEVICE

SLEW
RATE
(TVP)
(V/IlS)

AVOL
(dB)

SUPPLY
CURRENT
(mAlOP
AMP)

CMRR
(dB)

PSRR
(dB)

GBWP
(TVP)
(MHz)

700

94

94

9.0

125.0

94

2.4

15

70

65

1.0

0.5

94

1.5

100

30

65

65

1.0

0.5

88

1.5

100.0

10.0

77

77

0.4

1.5

86

0.15

QUAD OP AMPS
HA-5134

0.2

0.3

50.0

50.0

100

100

4.0

1.0

118

2.0

HA-5114

2.5

3.0

200.0

75.0

86

86

60.0

20.0

100

1.63

HA-5104

2.5

3.0

200.0

75.0

86

86

8.0

3.0

100

1.63

CA124

5.0

7.0

150.0

30.0

70

65

1.0

0.5

94

0.5

HA-5144

6.0

3.0

100.0

10.0

77

77

0.4

1.5

86

0.15

CA224

7.0

7.0

250.0

50.0

65

65

1.0

0.5

88

0.5

CA324

7.0

7.0

250.0

50.0

65

65

1.0

0.5

86

0.5

CA2902

7.0

7.0

250.0

50.0

65

65

1.0

0.5

86

0.3

....I

 15V can cause
excessive power dissipation and eventual destruction. Short circuits from the output to V+ can cause overheating and eventual destruction of the device.
3. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Values Apply for Each Operational Amplifier. Supply Voltage V+ = 5V, V- = OV,
Unless Otherwise Specified
CA224, CA324, LM324

CA124
TEST
CONDITIONS

PARAMETER
Input Offset
Voltage (Note 6)
Average Input
Offset Voltage
Drift

Rs=OQ

Differential Input
Voltage (Note 5)

TEMP.
("C)

MIN

TYP

MAX

25

-

2

5

Full

-

7

Full

7

-

Full

TYP

MAX

MIN

2

7

-

-

-

9

-

7

-

-

V+

-

V+

V

V+-l.5

-

-

V

-

-

V+-2

V

MIN

V+

V+=30V

25

0

-

V+-l.5

0

V+=30V

Full

0

-

V+-2

0

V+=26V

Full

-

-

Common Mode
Rejection Ratio

DC

25

70

85

65

Power Supply
Rejection Ratio

DC

25

65

100

Input Bias
Current (Note 4)

11+ or 11-

25

-

45

150

11+ or II"

Full

-

-

300

11+-11"

25
Full

-

3

11+-1 1-

Input Common
Mode Voltage
Range (Note 5)

Input Offset
Current
Average Input
Offset Current
Drift

Full

-

10

3-18

-

V+-2
0

70

-

65

100

-

-

-

45

250

-

500

-

50

-

30
100

LM2902

5

-

-

150
10

-

-

TYP

MAX

UNITS
mV

-

10

7

mV
',!VfC

-

V

dB

dB

40

nA
500

nA

-

-

nA

45

200

nA

10

-

pAfC

CA 124, CA224, CA324, LM324, LM2902
Electrical Specifications

Values Apply for Each Operational Amplifier. Supply Voltage v+ = 5V, v- = OV,
Unless Otherwise Specified (Continued)
CA124

PARAMETER
Large Signal
Voltage Gain

Output
Voltage
Swing

MIN

TYP

RL,,2kQ,V+=15V
(For Large Vo Swing)

25

94

100

RL " 2kn, V+ = 15V
(For Large Vo Swing)

Full

88

-

V+-l.5

25

a

-

RL = 2kn, V+ = 30V

Full

26

-

RL = 2kn, V+ = 26V

Full

RL = 10kn, V+ = 30V

Full

RL = 10kn

Full

Source V,+ = +IV, V,- = OV,
V+=15V

25

V,+ = IV, V,- = 0,
V+=15V

Low
Level
Output
Current

TEMP.
(OC)

RL = 2kn
High
Level

Sink

Crosstalk

Total Supply
Current

MAX

MIN

TYP

88

100

83

-

a
26

MAX

-

27

28

-

5

20

40

-

20

40

Full

10

20

10

20

V,+ = OV, V,. = IV,
V+ = 15V

25

10

20

-

10

V,+ = OV, V,- = IV,
Vo=200mV

25

12

50

-

V,. = IV, V,+ = 0,
V+= 15V

Full

5

8

-

f= 1 to 20kHz
(Input Referred)

25

-120

RL=

00

Full

0.8

RL =

00,

UNITS
dB

83

dB

-

V
V

22

20

-

TYP

V+-l.5

5

23
20

V
28
5

V
100

mV

-

mA

10

20

mA

20

-

-

mA

12

50

-

-

IlA

5

8

5

8

mA

-

-120

-

2

0.8

-

Full

MIN

-

28

V+ = 26V

MAX

27

LM2902

CA224, CA324, LM324

TEST
CONDITIONS

2

-

dB

0.7

1.2

mA

1.5

3

mA

NOTES:
4. Due to the PNP input stage the direction of the input current is out of the IC. No loading change exists on the input lines because the
current is essentially constant, independent of the state of the output.
5. The input signal voltage and the input common mode voltage should not be allowed to go negative by more than 0.3V. The positive limit
of the common mode voltage range is V+ - 1.5V, but either or both inputs can go to +32V without damage.
6. Vo = 1.4V, Rs = on with V+ from 5V to 30V, and over the full input common mode voltage range (OV to V+ - 1.5V).

3-19

CA 124, CA224, CA324, LM324, LM2902
Schematic Diagram

(One of Four Operational Amplifiers)

+
~
2

6

7

•

2+
~
4

13

4

•

O+
~
3

9

8

•

V. 11

Typical Performance Curves
iii' 120

r--;---+---t

iii!:
100
~

r-~~~-+---t

~

w

-+
~ 601---I---+~~~-'---T--r--~
~

...
02;

Z

80 1-_-1-.....3"""....

....-r--~

lK

10K

~WE

450 1--1--

~V:I
: SOpF ~ VO_-I-_-I-_f---I

~

400 ........_

..;.

o
1M

lOOK

350

="

I--fl--+--+--+--+---fll/~---i----l

10M

Vl

__

__

2S00~-~~2-~3-~4-~S~~6~~7~~8-~9
TIME()ls)

FREQUENCY (Hz)

FIGURE 1. OPEN LOOP FREQUENCY RESPONSE

FIGURE 2. VOLTAGE FOLLOWER PULSE RESPONSE (SMALL
SIGNAL)

TA =2S·C
V+ = lSV
RL=2k.1l

J

-

\

J

\.

-"

o

... INPUT

....L..

~ 3OO~-+\~O~~T.,PU~T~~ ~ ~r__+--+~

&201---I---+--1---I-.....3~
100

~

~

401---I---+--1-~~~-+--~-~

10

SOOI---+-

10

20

30

40

TIME (118)

FIGURE 3. VOLTAGE FOLLOWER PULSE RESPONSE (LARGE SIGNAL)

3·20

CA 124, CA224, CA324, LM324, LM2902
Typical Performance Curves

(Continued)

VieR =OV
60
~

.~

!

V+ =30V

50

:c
S

~
zw

a:
a:

!ztI! 41---r--+--+-~--~
a:
i3 3 I - - \ - - \ - - \ - - \ - - f -

15V

40

.1-"""'"
30

5V

::)

~

Q.

(,)
~
::)

Q.

~ 21--1--1--1--1--1--11--11--11--1

20

TA = OOC TO 125°C

i!!:
10

·55"C

o

·75

·50

·25

0

25

50

75

100

125

5

10

FIGURE 4. INPUT CURRENT vs AMBIENT TEMPERATURE

TA = 25°C

>
(;'

15

~
w

CI

~ 10

\

~
~

S
o

5

>

,@.Ii1
2

,N'

10K

60

!zw

50

a:
a:
::>
u
w
u
a:

= =

::>

c(CIl

Za:

O!!:!
-IL

r--.. r---..~

40

30

!;;(:::i
a: a..
W:!ii
~c(

I'-- .........

r---.

0

II>
~

20

~

10

::>
Q.

...

o
1K

1 Vo

.J

V+ =15V

:c

.§.

'!Z~

\.

'\

30

70

i~+15V

,~

i!!:

25

FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE

100kQ

-

20

POSITIVE SUPPLY VOLTAGE M

TEMPERATURE (OC)

20

15

0

.........

o

·75

1M

100K

·50

·25

0

25

50

75

100

125

TEMPERATURE ("C)

FREQUENCY (Hz)

FIGURE 7. OUTPUT CURRENT vs AMBIENT TEMPERATURE

FIGURE 6. LARGE SIGNAL FREQUENCY RESPONSE

TA =25°C

TA = 25"C

75

iii' 150
~

:c
s
!zw
a:
a:

~
~

50

::)

(,)
~
::)

- ---

Q.

i!!:

25

o

~

",

l /V"

30
10
20
POSITIVE SUPPLY VOLTAGE M

100

~

75

!:i

§
zw

!!i

./

."

'"

RL =20kQ'RL=2kQ -

50
25

o
o

40

-- ~

125

w
~

10

20

30

40

POSITIVE SUPPLY VOLTAGE M

FIGURE 8. INPUT CURRENT vs SUPPLY VOLTAGE

FIGURE 9. VOLTAGE GAIN vs SUPPLY VOLTAGE

3·21

CA158, CA158A, CA258, CA258A,.
CA358, CA358A, CA2904,
LM358, LM2904
Dual, 1MHz, Operational Amplifiers for Commercial
Industrial, and Military Applications

June 1996

Features

Description

• Internal Frequency Compensation tor Unity Gain

The CA158, CA158A, CA258, CA258A, CA358, CA358A
and CA2904 types consist of two independent, high gain,
internally frequency compensated operational amplifiers
which are designed specifically to operate from a single
power supply over a wide range of voltages. They may also
be operated from split power supplies. The supply current is
basically indepe~dent of the supply voltage over the
recommended voltage range.

• High DC Voltage Gain •••••••••••••••.• 10OdB(Typ)
• Wide Bandwidth at Unity Gain •••••••••. 1MHz(Typ)
• Wide Power Supply Range:
- Single Supply •••••••••••••••••••••••• 3V to 30V
- Dual Supplies •••••••••••••.•••••. ±1.5Vto±15V
• Low Supply Current .•••.••.•••••••••• 1.5 mA(Typ)
• Low Input Bias Current
• Low Input Offset Voltage and Current
• Input Common-Mode Voltage Range Includes Ground
• Differential Input Voltage Range Equal to V+ Range
• Large Output Voltage Swing •••••••••• OV to V+ -1.5V

Ordering Information
PART
NUMBER

TEMP.
RANGE ("C)

PACKAGE

PKG.
NO.

CA0158E

·55 to 125 8Ld PDIP

CA0158AE

-55 to 125 8 Ld PDIP

E8.3

CA0158M

-55 to 125 8Ld SOIC

M8.15

CA0158M96

-55 to 125 8 lei SOIC Tape and Reel

M8.15

CA0158T

-55 to 125 8 Pin Can

T8.C

CA0158AT

-55 to 125 8 Pin Can

T8.C

CA0258E

-25 t08?

8Ld PDIP

E8.3

CA0258AE

-25 to 85

8Ld PDIP

E8.3
M8.15

These devices are particularly useful in interface circuits with
digital systems and can be operated from the single
common 5Voc power supply. They are also intended for
transducer amplifiers, DC gain blocks and many other
conventional op amp circuits which can benefit from the
single power supply capability.
The CA158, CA158A, CA258, CA258A, CA358, CA358A, and
CA2904 types are an equivalent to or a replacement for the
industry types 158, 158A, 258, 258A, 358, 358A, and CA2904.
Technical Data on LM Branded !ypes is identical to the
corresponding CA Branded types.

E8.3

CA0258M

-25 to 85

BLd SOIC

CA0258M96

-25 t085

8 lei SOIC Tape and Reel

MB.15

CA0258AM

-25 t085

8Ld SOIC

M8.15

Pinouts
CA158, CA258, CA358 (METAL CAN)
TOP VIEW
INV.
INPUT (A)

CA0258AM96

-25 t085

8 lei SOIC Tape and Reel

MB.15

CA0258T

-25 to 85

8 Pin Can

T8.C

CA0258AT

-25 to 85

8 Pin Can

TB.C

CA0358E

o t070

8Ld PDIP

E8.3

CA0358AE

o to 70

8Ld PDIP

E8.3

CA0358M

o to 70

8 Ld SOIC

M8.15

CA0358AM

o to 70

8 LdSOIC

M8.15

CA158, CA258, CA358, CA2904 (PDIP, SOIC)
LM358, LM2904 (PDIP)

CA0358M96

o to 70

8 lei SOIC Tape and Reel

M8.15

TOP VIEW

CA0358AM96

o to 70

8 Ld SOIC Tape and Reel

MB.15

CA0358T

o to 70

8 Pin Can

T8.C

CA0358AT

o to 70

8 Pin Can

T8.C

CA2904E

-40 t085

8Ld PDIP

EB.3

CA2904M
CA2904M96

-40 toB5
·40 t085

8Ld SOIC
8 Ld SOIC Tape and Reel

INV.
INPUT (B)

OUTPUT (A) 1
INV.INPUT (A) ...,20=""""'''
NON-INV. INPUT (A) 3

M8.15
M8.15

LM358N

o t070

8Ld PDIP

E8.3

LM2904N

o to 70

8Ld PDIP

EB.3

CAUTION: These devices are sensRive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation t996

3-22

7

OUTPUT (B)

6

INV. INPUT (B)

5

NON·INV. INPUT (B)

File Number

1019.3

CA 158, CA 158A, CA258, CA258A, CA358, CA358A, CA2904, LM358, LM2904
Absolute Maximum Ratings

Thermal Information

Supply Voltage
CA2904, LM2904 ........................... 26V or ±13V
Other Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 32V or ±16V
Differential Input Voltage (All Types) ...................... 32V
Input Voltage .................................. -0.3V to V+
Input Current (VI < -0.3V, Note 1) ....................... SOmA
Output Short Circuit Duration (V+';; 15V, Note 2) ...... Continuous

Thermal Resistance (Typical, Note 3)
9JA (OCNY) 9Jc (OCNY)
PDIP Package.... .. ... .. . .. . . . ..
130
N/A
SOIC Package. . . . . . . . . . . . . . . . . . .
170
N/A
Can Package. . . . . . . . . . . . . . . . . . . .
155
67
Maximum Junction Temperature (Can Package) .......... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range .......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300 DC
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
CA15B, CA15BA .......................... -55 DC to 125DC
CA25B, CA25BA ........................... -25 DC to B5DC
CA2904, LM2904 .......................... -40 DC to B5DC
CA35B, CA35BA, LM35B ....................... ODC to 70DC

CAUTION: Stresses above those listed in "Absolute Maximum Ra#ngs" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the opera#onal sections of this specification is not implied.

NOTES:
1. This input current will only exist when the voltage at any of the input leads is driven negative. This current is due to the collector base junction
of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also
lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the amplifiers to go to the V+
voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This transistor action is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than -0.3V.
2. The maximum output current is approximately 40mA independent olthe magnitude of V+. Continuous short circuits at V+ > 15V can cause
excessive power dissipation and eventual destruction. Short circuits from the output to V+ can cause overheating and eventual destruction of the device. Destructive dissipation can result from simultaneous short circuits on both amplifiers.
3. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Input Offset
Voltage (Note 6)

W::

TEMP
(OC)
25
Full

CA158A
MIN

-

Full

CA258A

TYP

MAX

1

2

-

4

7

15

MIN

~<

CA358A

TYP

MAX

MIN

TYP

MAX

1

3

2

3

mV

4

-

5

mV

15

7

20

flVJOC

UNITS

Average Input
Offset Voltage
Drift

Rs=On

Input Common
Mode Voltage
Range (Note 5)

V+=30V

25

0

V+-l.5

0

V+-1.5

0

-

V+-l.5

V

V+=30V

Full

0

V+-2

0

V+-2

0

-

V+-2

V

Common Mode
Rejection Ratio

DC

25

70

B5

-

70

B5

-

65

B5

-

dB

Power Supply
Rejection Ratio

DC

25

65

100

65

100

65

100

-

dB

Input Bias
Current (Note 4)

11+ or 11-

25

20

50

40

BO

45

100

nA

11+ or 11-

Full

40

100

40

100

40

200

nA

Input Offset
Current

11+-1 1-

25

2

10

2

15

5

30

nA

11+ -I r

Full

30

-

75

nA

10

200

10

300

pAi"C

100

-

Average Input
Offset Current
Drift
Large Signal
Voltage Gain

"
g

~

!:i

~
~

~

I--~f-­

450

I--~f--

1\

4OO1-.....f-

I 350r-~Hl~.-

o !:i
o

__, -__

Ilou,TPUT

INPUT

~ ~~~I/~;__+-~
f
__

3oor-~I~l~A~~__~__+-~~-t__~~
~

o

10

20

30
TIME (".)

250L-__
o

40

FIGURE 7. VOLTAGE FOLLOWER PULSE RESPONSE
(LARGE SIGNAL)

20

500

w

2 ~

\

~ 4
w
:..0

~

L-\n~__~__

- L__- L__- L__

234
TIME ("s)

~ ~~
__

6789

FIGURE 8. VOLTAGE FOLLOWER PULSE RESPONSE
(SMALL SIGNAL)

.....I

TA = 25°C

«en
Za:

TA = 25°C

100kn
75

~
CI

~~.,w

15

~

~

'"

w

CI

~

10

VI

+7V

-u.

,

~:::i
a: a..

C

.s.

_ ) . . 0Vo
-

~
w 50

2kn

)

:\-

~

!:i...
!:i0

;

O!!!

a:
a:

-= -=-=

~

u

!:i...

- ---

l!: 25

5

'\
"I"'-......

o
1K

10K

100K

o

1M

o

~

l/

"

/'

~«

10
20
30
POSITIVE SUPPLY VOLTAGE (V)

FREQUENCY (Hz)

40

FIGURE 10. INPUT CURRENT vs SUPPLY VOLTAGE

FIGURE 9. LARGE-SIGNAL FREQUENCY RESPONSE

10

8

:-:ft-

V+

7

~

W::i

V+ = +5Voc
V+=+ 15VOC

~,

w

~
~

":'"

~

-

-

--

+

~If

rlV

V
0.01
0.1
10
OUTPUT SOURCE CURRENT (rnA)

0.1

0

I
0.001

V+/2

~

/

-

V+

I-

INDEPENDENT OF V+
TA = 25°C

2

~+,i t~VDII ~

~
CI

10+

":'"

"->I

0.01
0.001

100

FIGURE 11. OUTPUT SOURCE CURRENT CHARACTERISTICS

3-27

V

V
0.01

--

TA =25OC

0.1
10
OUTPUT SINK CURRENT (rnA)

10

Vo

100

FIGURE 12. OUTPUT SINK CURRENT CHARACTERISTICS

CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904, LM358, LM2904
Typical Performance Curves

(Continued)

70
V+ = 15V

C

60

Iiw

50

:)

40

.§.

r--.... ........ ....

II:
II:

U

w

U

II:

30

:)

r--.... ........

. . . r--..,

0

5...'"

20

I:)

10

0

o

-75

-50

-25

0

25

50

75

100

125

TEMPERATURE (DC)

FIGURE 13. OUTPUT CURRENT vs AMBIENT TEMPERATURE

Meta~lization

Mask Layout
o

10

20

30

40

50

60 66

72--70-

605069-n
(1.753 - 1.956)

30 20 10 -

-o-~"~~~I*""---•

•

Dimensions in parentheses are in millimeters and derived
from the basic inch dimensions as indicated. Grid
graduations are in mils (10-3 inch).
The photographs and dimensions represent a chip when it
is part of the wafer. When the wafer is cut into chips, the
cleavage angles are 5~ instead of 90° with respect to the
face of the chip. Therefore, the isolated chip is actually 7mils
(O.17mm) larger in both dimensions.

3-28

CA741, CA741C, CA1458,
CA 1558, LM741, LM741C, LM1458

HARRIS
SEMICONDUCTOR

Single and Dual, High Gain Operational Amplifiers
for Military, Industrial and Commercial Applications

November 1996

Features

Description

• Input Bias Current ..••.•........•...• 500nA (Max)

The CA1458, CA1558 (dual types); CA741C, CA741 (single
types); high-gain operational amplifiers for use in military,
industrial, and commercial applications.

• Input Offset Current .................. 200nA (Max)

Applications
• Comparator
• DC Amplifier
• Integrator or Differentiator

• Multiyibrator
• Summing Amplifier
• Narrow Band or Band
Pass Filter

Ordering Information
PART
NUMBER
CA0741E

TEMP. RANGE
(DC)

-55 to 125.
-55 to 125
Ot070
-55 to 125

BLd PDIP
BLd PDIP
B Ld PDIP
B Pin Metal Can
B Pin Metal Can
B Pin Metal Can
B Pin Metal Can
B Ld PDIP
BLd PDIP
B Pin Metal Can

PKG.NO.
EB.3
EB.3
E8.3
EB.3
TB.C
TB.C
TB.C
TB.C
EB.3
EB.3
TB.C

Ot070
Ot070

B Pin Metal Can
B Ld PDIP

TB.C
EB.3

-55 to 125

CA0741CE
CA145BE
CA155BE
CA0741T
CA0741CT
CA145BT
CA155BT
LM741N
LM741CN
LM741H

o to 70
Ot070
-55 to 125
-55 to 125
Ot070
o to 70

LM741CH
LM145BN

PACKAGE
BLd PDIP

These monolithic silicon integrated circuit devices provide
output short circuit protection and latch-free operation.
These types also feature wide common mode and
differential mode signal ranges and have low offset voltage
nulling capability when used with an appropriately valued
potentiometer. A 10ka potentiometer is used for offset
nulling types CA741C, CA741 (see Figure 1). Types
CA1458, CA1558 have no specific terminals for offset
nUlling. Each type consists of a differential input amplifier
that effectively drives a gain and level shifting stage having
a complementary emitter follower output.
The manufacturing process make it possible to produce IC
operational amplifiers with low burst "popcorn" noise
characteristics. The CA741 gives limit specifications for burst
noise in the data bulletin, File Number 530. Contact your
Sales Representative for information pertinent to other operational amplifier types that meet low burst noise
specifications.
Technical Data on LM Branded types is identical to the corresponding CA Branded types.

Pinouts
CA741 , CA741C, LM741 , LM741C (CAN)
TOP VIEW

CA1458, CA1558 (METAL CAN)
TOP VIEW

NC

v+

IN~Wr

INV.INPIi~ 2~~~11~~,"-, 6 l~r INPUT

2

88

v-

CA741 , CA741C, LM741 , LM741C (PDIP)
TOP VIEW
OFFSET NULL
INV. INPUT
NON-INV.INPUT

y-

2

3

7

+

CA1458, CA155B, LM1458 (PDIP)
TOP VIEW
OUTPUT (A)

NC

v+

1.,-;.,._...--

INV. INPUT (A) 2

6 OUTPUT

NON-INV. INPUT (A) 3

5 OFFSET NULL

7 OUTPUT (B)
6 INY. INPUT (B)
NON-INY. INPUT (B)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-29

File Number

531.3

..J
C(C/)

Za:

O!!:!
-IL

!ct:::i
a: a..
W::i

~C(

CA741, CA741C, CA1458, CA1558, LM741, LM741C, LM1458
.Absolute Maximum Ratings

Thermal Information

Supply Voltage
CA741C, CA1458, LM741C, LM1458 (Note 1) ............. 36V
CA741, CA1558, LM741 (Note 1) ..................... , 44V
Differential Input Voltage . .............................. 30V
Input Voltage . .................................. ±VSUPPLY
Offset Terminal to V- Terminal Voltage (CA741C, CA741) ... ±0.5V
Output Short Circuit Duration ....................... Indefinite

Thermal Resistance (Typical, Note 3)
9JA (OC/w)
9JC (OC/W)
PDIP Package. . . . . . . . . . . . . . . . . . .
130
N/A
Can Package. . . . . . . . . . . . . . . . . . . .
155
67
Maximum Junction Temperature (Can Package) .......... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os) ............. 300°C

Operating Conditions
Temperature Range
CA741 , CA1558, LM741. ................... -55°C to 125°C
CA741C, CA1458, LM741C, LM1458 (Note 2) ..... OOC to 70°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is 8 stress only rating and operation
01 the device at these or any other conditions above those Indicated in the operational sections 01 this specilication is not implied.

NOTES:
1. Values apply for each section of the dual amplifiers.
2. All types in any package style can be operated over the temperature range of -55°C to 125°C, although the published limits for certain
electrical specification apply only over the temperature range of OOC to 70°C.
3. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications
PARAMETER
Input Capacitance

Typical Values Intended Only for Design Guidance, VSUPPLY = ±15V

SYMBOL

TEST CONDITIONS

TYPICAL VALUE
(ALL TYPES)

UNITS

1.4

pF

±15

mV

CI

Offset Voltage Adjustment Range
Output Resistance

Flo

Output Short Circuit Current
Transient Response
Rise Time

t,

Overshoot

0.5.

Slew Rate (Closed Loop)

Electrical Specifications

PARAMETER
Input Offset Voltage

SR

Unity Gain, VI = 20mV, RL = 2kn,
C L S100pF

RL ;;,2kn

TEST
CONDITIONS
Rs s10kn

Input Common Mode Voltage
Range

Power Supply Rejection Ratio

Input Resistance

n

25

mA

0.3

IlS

5.0

%

0.5

VIIlS

For Equipment Design, VSUPPLY = ±15V

TEMP
(OC)

(NOTE 4)
CA741 , CA1558, LM741

MIN

25

-

Full

±12V

25
Full

Common Mode Rejection Ratio

75

Rs s10kn

RsS10kn

(NOTE 4)
CA741C, CA1458, LM741C,
LM1458

MAX

UNIT
S

2

6

mV

-

-

7.5

mV

±12V

±13V

TYP

MAX

MIN

TYP

1

5

-

1

6

-

-

25

-

-

Full

70

90

-

Full

-

-

30

150

-

25

0.3

2

-

0.3

25

3-30

V

-

±13V

70

V
90

30

dB

-

dB

150

IlVN
IlVN

2

Mn

CA741, CA741C, CA1458, CA1558, LM741, LM741C, LM1458
Electrical Specifications

For Equipment Design, VSUPPLY = ±15V (Continued)

TEST
CONDITIONS

PARAMETER

(NOTE 4)
CA741C, CA1458, LM741C,
LM1458
TYP

MAX

UNIT
S

500

80

500

nA

800

nA

300

1500

-

125

30

500

25

20

200

20

200

nA

300

nA

85

500

7

200

200,000

-

TEMP
(DC)

Input Bias Current

(NOTE 4)
CA741, CA1558, LM741
MIN

25

TYP

MAX

80

MIN

Full
-55

Input Offset Current

nA

-

Full
-55
125
Large Signal Voltage Gain

Output Voltage Swing

RL ,,2kQ, Vo =±10V

RL " 10k.Q

25

50,000

Full

25,000

RL ,,2kQ

-

nA

200,000

VN
VN

±12V

±14V

V
..J
«II)

ZIX

-

±10V

±13V

-

±13V

-

±10V

±13V

-

25

1.7

2.8

1.7

2.8

mA

-55

2

3.3

1.5

2.5

-

mA

125

-

±10V

V

IXD.

mA

50

85

50

85

mW

-

60

100

-

-

mW

125

-

45

75

-

mW

NOTE:
4. Values apply for each section of the dual amplifiers.

Test Circuits

INVERTING
INPUT
OUTPUT

NON-INVERTING
INPUT --,."..,---.

}-_--VOUT

V-

FIGURE 2. TRANSIENT RESPONSE TEST CIRCUIT FOR ALL
TYPES

FIGURE 1. OFFSET VOLTAGE NULL CIRCUIT FOR CA741C,
CA741, LM741C, AND LM741

3-31

O!:!:!
-u.

!;:::J

-55

25

Device Power Dissipation

20,000

nA

-

±14V

25
Full

Supply Current

±12V

-

15,000

25
Full

nA

W:i:

~«

CA741, CA741C, CA1458, CA1558,LM741, LM741C, LM1458
Schematic Diagram

(Notes 5, 6)

CA741C, CA74,1, LM741C, LM741 AND FOR EACH AMPLIFIER OF THE CA1458, CA1558, AND LM1458

,. 01

INVERTING
INPUT

NON-INVERTING
INPUT

."

Ql0

Q3

"II- 0 4

Q4

t1

~~ Qll

"

R9
25

Rg

- 0 OUTPUT
RIO
50

,)Q1S

8

Q16

Q9~

~

(.).

OFFSET-C ......

... Q17

Q14

0
Rl
1K

".Q13

.... -

7.5K

Q

Os
NULL

Q12

r--i

Rs
39K

Q2

,~

R7
4.5K

Cl

'i' 30pF

_~c

V+

O2

.... QS

.
.

.

R3
50K

"

R.c

R2
1K

03

Rl1
aOK

R12
50K

3K

.

V-

NOTES:
5. See Pinouts for Terminal Numbers of Respective Types.
6. All Resistance Values are in Ohms.

Typical Performance Curves
40

TA = 25°C

E
w
CJ

./

z
a:

0(

...5

1
~
CJ

~

/

w
Q
0
::Ii

z

~

/

10

~

0
::Ii
::Ii

5...
50

/

5

/

8
o

TA = 25°C
RL ,,2kn

35

15

25
20
15
10

5

/

5

o
o

10

15

20

/

30

V

V

V

/
o

5

10

15

20

DC SUPPLY (v+, V-)

DC SUPPLY (V+, V-)

FIGURE 3. COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY
VOLTAGE FOR ALL TYPES

3-32

FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE FOR ALL
TYPES

CA741, CA741C, CA1458, CA1558, LM741, LM741C, LM1458
Typical Performance Curves

(Continued)

30

DC SUPPLY VOLTS (V+ = 15, V- = -15)
TA = 25°C, CL = 100pF

25

20

:;-

§.

....
::)
.......
::)

r- r- 90% I
II

15

0

...

~

20

I

I
II, 10%
RISE TIME

5

o

o

-0.5

1.0

-0.5

TIME

1.5

2.0

2.5

3.0

(~.)

FIGURE 5. TRANSIENT RESPONSE FOR CA741C AND CA741

Metallization Mask Layout
-I

CA741CH

57

o

10

20

I

I

I

ctCll

30

40

50

I

I

I

Za:

6064

Ow

-u:::

~::i

"--...-

a:1l.

W:E

~ct

54-62
(1.372 -1.575)

61-69
(1.549 -1.753)

CA1458H

o

10

20

55_.1.1[ll!!1

50-

30

I

40

50

60

70

80

11111

I

104
90 100

1

1

~ 1

403020100-

_-;-_

52-60
(1.321 - 1.524)

.."'_liiiiiii
---

'-'1

1-- ~:1~~ - 0.254)

..

J
(2.m:~~68)

------

NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in
mils (10. 3 inch).

3-33

8MHz Power Amps For Military,
ustrial and Commercial Equipment
Description
• High Power Output Class B Amplifier
- CA3020 .................... O.5W (Typ) at Vee 9V
- CA3020A .................. 1.0W (Typ) at Vee = 12V

=

• Wide Frequency Range •• Up to 8MHz with Resistive Loads
• High Power Gain .•......•....••••...••••• 75dB (Typ)
• Single Power Supply For Class B Operation With
Transformer
- CA3020 ................................ 3V to 9V
- CA3020A .............................. 3V to 12V
• Built-In Temperature-Tracking Voltage Regulator Provides
Stable Operation OVer -550 C to 125°C Temperature Range

Applications
• AF Power Amplifiers For Portable and Fixed Sound and
Communications Systems
• Servo-Control Amplifiers
• Wide-Band Linear Mixers
• Video Power Amplifiers
• Transmission-Line Driver Amplifiers (Balanced and
Unbalanced)
• Fan-ln and Fan-out Amplifiers For Computer Logic Circuits
• Lamp-Control Amplifiers
• Motor-Control Amplifiers
• Power Multivibrators
• Power Switches

Pinout

The CA3020 and CA3020A are integrated-circuit, multistage, multipurpose, wide-band power amplifiers on a single
monolithic silicon chip. They employ a highly versatile and
stable direct coupled circuit configuration featuring wide
frequency range, high voltage and power gain, and high
power output. These features plus inherent stability over a
wide temperature range make the CA3020 and CA3020A
extremely useful for a wide variety of applications in military,
industrial, and commercial equipment.
The CA3020 and CA3020A are particularly suited for service
as class B power amplifiers. The CA3020A can provide a
maximum power output of 1W from a 12VDC supply with a
typical power gain of 75dB. The CA3020 provides O.5W
power output from a 9V supply with the same power gain.
Refer to AN5766 for application information.

Ordering Information
TEMP.
RANGEfe)

PACKAGE

CA3020

-55 to 125

12 Pin Metal Can

T12.B

CA3020A

-55 to 125

12 Pin Metal Can

T12.B

PART NUMBER

PKG.
NO.

Schematic Diagram
CA3020
(METAL CAN)
TOP VIEW

9

R10

8

11

1.SK

V-

OUTPUT 6

The resistance values included on the schematic diagram have been supplied as a convenience to assist
Equipment Manufacturers in optimizing the selection of 'outboard" components of equipment designs.
The values shown may vary as much as 30"10.
Harris reserves the right to make any changes In the Resistance Values provided such changes do not
adversely affect the published performance characteristics of the device.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-34

File Numi:>er

339.4

November 19

h

¥",

.

&f!I/I>~'*~";'i!',N;"'I!."I'iIM,.;.tM,."",w!pJ,;#I.W'-I

Features l-"",,_'''"''~'"'''~w''-''

Description

• Low Power Consumption as Low as 100mW Per
Amplifier

The CA3060 monolithic integrated circuit consists of an array of
three independent Operational Transconductance Amplifiers
(see Note). This type of amplifier has the generic characteristics of an operational voltage amplifier with the exception that
the forward gain characteristic is best described by transconductance rather than voltage gain (open-loop voltage gain is the
product of the transconductance and the load resistance,
gMRLl. When operated into a suitable load resistor and with
provisions for feedback, these amplifiers are well suited for a
wide variety of operational-amplifier and related applications. In
addition, the extremely high output impedance makes these
types particularly well suited for service in active filters.

• Independent Biasing for Each Amplifier
• High Forward Transconductance
• Programmable Range of Input Characteristics
• Low Input Bias and Input Offset Current
• High Input and Output Impedance
• No Effect on Device Under Output Short-Circuit
Conditions

The three amplifiers in the CA3060 are identical push-pull
Class A types which can be independently biased to achieve a
wide range of characteristics for specific application. The electrical characteristics of each amplifier are a function of the
amplifier bias current (lABe)' This feature offers the system
designer maximum flexibility with regard to output current capability, power consumption, slew rate, input resistance, input bias
current, and input offset current. The linear variation of the
parameters with respect to bias and the ability to maintain a
constant DC level between input and output of each amplifier
also makes the CA3060 suitable for a variety of nonlinear applications such as mixers, mUltipliers, and modulators.

• Zener Diode Bias Regulator

Applications
• For Low Power Conventional Operational Amplifier
Applications
• Active Filters
• Comparators
• Gyrators
• Mixers

In addition, the CA3060 incorporates a unique Zener diode
regulator system that permits current regulation below supply voltages normally associated with such systems.

• Modulators
• Multiplexers
• Multipliers

• Sample and Hold Functions

NOTE: Generic applications of the OTA are described in AN-6668.
For improved input operating ranges, refer to CA3080 and CA3280
data sheets (File Nos. 475 and 1174) and application notes AN6668
and AN6818.

Pinout

Od
r ermg I norma
it
Ion

• Strobing and Gating Functions

CA3060
(PDlP)
TOP VIEW

PART NUMBER
CA3060E

REGULATOR OUT

1

REGULATOR IN

2

TEMP.
RANGE ("C)
·40 to 85

PACKAGE
16 Ld PDIP

PKG.
NO.
E16.3

OUTPUT NO. 1
BIAS NO. 1
NON-INV. INPUT NO.1

INV. INPUT NO.3

4

INV. INPUT NO.1

NON·INV. INPUT NO. 3 ...5_..,~~,.
BIAS NO. 3

6

OUTPUT NO.3

7

INV. INPUT NO.2
NON-INV. INPUT NO.2
BIAS NO.2
9

OUTPUT NO.2

CAUTION: These devices are senSitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyrtght

© Harrts Corporation 1996

3-35

File Number

537.3

..J

 > - RI+RF

assuming RB > > RI

FIGURE 3. OFFSET VOLTAGE NULL CIRCUITS
5.1MD

5.1MD

1.5V

"AA"CELL

+
-

1.5V

"AA"CELL

+

+

5~F

10MD

FIGURE 4. INVERTING 20dB AMPLIFIER CIRCUIT

FIGURE 5. NON-INVERTING 20dB AMPLIFIER CIRCUIT

3-39

+
-

CA3078, CA3078A
TABLE 1. UNITY GAIN SLEW RATE VB COMPENSATION - CA3078 AND CA3078A
VSUPPLY = ±6V, Output Voltage (Vol = ±5V, Load Resistance (RLl = 10kQ, Transient Response: 10% overshoot for an output voltage of
100mV, Ambient Temperature (TA) = 25°C
UNITY GAIN (INVERTING)
FIGURE 1
COMPENSATION
TECHNIQUE

UNITY GAIN (NON-INVERTING)
FIGURE 2

Rl

Ct

R2

C2

SLEW RATE

Rt

Cl

R2

C2

kQ

pF

kQ

IlF

VlIlS

kQ

pF

kQ

IlF

I SLEW RATE
I VlIlS

CA3078 - 10 = 1001lA
0

750

00

0

0.0085

0

1500

00

0

0.0095

3.5

350

00

0

0.04

5.3

500

00

0

0.024

00

0

0.25

0.306

0.67

00

0

0.311

0.45

0.67

Single Capacitor

0

300

00

0

0.0095

0

800

00

0

0.003

Resistor and Capacitor

14

100

00

0

0.027

34

125

00

0

0.02

Input

00

0

0.644

0.156

00

0

0.77

0.4

0.4

Single Capacitor
Resistor and Capacitor
Input
CA3078A - 10 = 20llA

0.29 •

Application Information
Compensation Techniques
The CA3078A and CA3078 can be phase compensated with
one or two external components depending upon the closed
loop gain, power consumption, and speed desired. The
recommended compensation is a resistor in series with a
capacitor connected from Terminal 1 to Terminal 8. Values of
the resistor and capacitor required for compensation as a
function of closed loop gain are shown in Figures 25 and 26.
These curves represent the compensation neoessary at
quiescent currents of 1001lA and 20!!A, respectively, for a
transient response with 10% overshoot. Figures 23 and 24
show the slew rates that can be obtained with the two different
compensation techniques. Higher speeds can be achieved
with input compensation, but this increases noise output.

Compensation can also be accomplished with a single
capacitor connected from Terminal 1 to Terminal 8, with speed
being sacrificed for simplicity. Table 1 gives an indication of
slew rates that can be obtained with various compensation
techniques at quiescent currents of 1001lA and 201lA.

Single Supply Operation
.The CA3078A and CA3078 can operate from a single supply
with a minimum total supply voltage of 1.5V. Figures 4 and 5
show the CA3078A or CA3078 in inverting and non-inverting
20dB amplifier configurations utilizing a 1.5V type "AA" cell
for a supply. The total consumption for either circuit is
approximately 675nW. The output voltage swing in this configuration is 300mVp_p with a 20kn load.

Typical Performance Curves
VS=±6
TA =2SoC
Rs:510kO

.s
!zw

~w

Sl

!:i

~

~O
5II.
iii!:

..,

VS~±6

0('

TA=2SoC

10

r-

II:
II:

I

I II

CA3078

:::I

,;

..,

,

CJ

3.0

!Ai

......

~

III

2.4

0

CA3078

I.B
1.2

5II.

0.1

..,

CA3078A

iii!:

CA3078A

0.6

o

1

10

100

0.01

1000

1

TOTAL QUIESCENT CURRENT (1lA)

FIGURE 6. INPUT OFFSET VOLTAGE vs TOTAL QUIESCENT
CURRENT

10
100
1000
TOTAL QUIESCENT CURRENT (1lA)

10000

FIGURE 7. INPUT OFFSET CURRENT vs TOTAL QUIESCENT
CURRENT

3-40

CA3078, CA3078A
Typical Performance Curves
~
/~

VS=±6
TA =2S OC
100

L

10

a:
a:

TA =2So C

:i

m r;

~

<
.s
!zw

(Continued)

::::J
til

~ 108

CA3078A

~

1/ ~

:!
III

II.

§

5...

Z

~

iii!:

0.1

1

126

w 126

Cl

~

U

~

"'"

~~

F= C~30~8

S

i

10

100

1000

10000

90
72
54

RL=lMn

108

.::::::::; ~10kO

90
72
54

r--

36

r-::::?!i

18

o

1

o

10
100
TOTAL QUIESCENT CURRENT (J1A)

TOTAL QUIESCENT CURRENT (~)

FIGURE 8. INPUT BIAS CURRENT vs TOTAL QUIESCENT
CURRENT

36
18

I
I

1000

FIGURE 9. OPEN LOOP VOLTAGE GAIN vs TOTAL
QUIESCENT CURRENT

1000

100

a
l!. 100

VS=±6TOVS=±lS
TA =2S oC

Vs =±lS

....I

cccn
Za:
OW

w

U

~

~a:

10

"""

+3
·3

"

Cl

z

~

~

TA = 2So C
RsET CONNECTED BETWEEN
TERMINAL 5 AND V+

0.1

III

0.01
1000

0.1
100

10
0.1
0.01
TDTAL QUIESCENT CURRENT (~)

0.001

1

FIGURE 10. BIAS SETTING RESISTANCE vs TOTAL
QUIESCENT CURRENT

1.5

-

z

1.0

.,

~

~
~

1o=100~

~ 100 1 - - - f - - - f - - + -.......0;:1-......".....;F- Ct =0pF

~ 80~--F~~~~~~~~~~~~~~

/' ~

W

~

CA3078
120 Vs=±6

RL= SOkO

,.. ....-

Cl

w
100
~603oo
~
1000

~ ~lOkn
SkO

II.

§

I

50

II.

o

o

o

1.5
0.5
1.0
TOTAL QUIESCENT CURRENT (~)

201---f---f--+---+~~~~~-~

Z

w

2.0

0'
0100

w~

-

e.
w

~ 40r---+---+---~~~~~~~~~

'~~kO

"lkO
soon

0.5

::::J
II.

10
100
1000
TOTAL QUIESCENT CURRENT !ItA)

FIGURE 11. MAXIMUM OUTPUT CURRENT va TOTAL
QUIESCENT CURRENT

I

Vs =±1.3V
TA =2So C

E
itil

~CC

+1
·1

til

~

fi~
a: 0..
w==

+6
-6

z

~
cw

~

o RL = 10k1l, TA = 25°C
Ct. BETWEEN TERMINALS 1 AND 8
·20 L -_ _ _---"-:,.--_::-_---:-_-'-::-_......L:,..:---'
102
103
104
0.1
101
FREQUENCY (Hz)

FIGURE 12. OUTPUT VOLTAGE SWING vs TOTAL QUIESCENT
CURRENT

FIGURE 13. OPEN LOOP VOLTAGE GAIN vs FREQUENCY FOR
CA3078

3·41

CA3078, CA3078A

Typical Performance Curves

(Continued)

100

Ia =20""
TA = 25°C

~

10

VIC~

~

~ II'VOM

i

/ /

w

I

~
S!""
I!:l

~

0.1

z

~

~

g
w

+1
-1

+0.1
.0.1

.0.1

+10

+100

·10

·100

FIGURE 15. OPEN LOOP VOLTAGE GAIN vs FREQUENCY FOR
CA3078A

SUPPLY VOLTS (V+, V.)

~

l

1.75
VS=±6

~

:;-

S!

i

~

-VIC~

!Ii:

~

,

.§.
w 1.25

~

1

./

1.50

!:i

g
t:i
UI

-YOM

~

II.
II.

,

-1 0

0

!;

...i!:

~A3078
IQ=1OO""

1.00

--

0.75
0.50
0.25
0

-75

·50

-25

~

/

0

_

t/

25

~

~3078A
IQ=20""

50

75

-

100

125

TEMPERATURE (oC)
FIGURE 14. OUTPUT AND COMMON MODE VOLTAGE vs
SUPPLY VOLTAGE

tt

VS=±6

j

I!

• 2.5

10 '

!i 2.0
~
!;
~

6

'" N:
CA3078A

1.0
0.5

0
-75

-SO

-25

I"

4

"

0
25
50
TEMPERATURE <"C)

iw

100

~

3

12•5

! 10.0

!!5

i

t:i

G 5.0

~

I

~u

Ia = 20""
100

..........

7.5

!;

2.5

o i!:

~

o

·75

125

~

C~~ ~

~ID

2~

K

75

VS=±6

tt 15.0

u

II:

1.5

U

~

8

",CA3078
IQ=100""

w

II:

!!5

FIGURE 16. INPUT OFFSET VOLTAGE vs TEMPERATURE

IQ = 100""
-I
I

-50

-25

0
25
50
TEMPERATURE (oC)

75

r-....

75

~

100

3-42

ffi

II:
II:

50

G

25

!;

o

125

FIGURE 18. INPUT BIAS CURRENT vs TEMPERATURE

FIGURE 17. INPUT OFFSET CURRENT vs TEMPERATURE

~

~ID

...i!:

CA3078, CA3078A
Typical Performance Curves

(Continued)

VS=±6

VS=±6
110

in
:!:!. 105

~

~

w

~

!:i

g

...
§
z
...w
0

"I"'"

i

40

1/

~

CA3078
10 = 10011A

95

~

50

!i:

CA3078A
10 = 2011A

CJ 100

030

!i:w

90

~ 20

85

aID

CA3078-.

·25

o

25

50

75

100

125

~ ~75

ffl

5

o
·50

"-

I

·25

0

25

50

75

100

125

~

~

VS=±6
TA = 25°C
CA3078AT

~

I

........

Ia = lOO11A-

III
1""00

10= 2011A

1~

104

FREQUENCY (Hz)

FIGURE 21. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY

'"

'" "-

10 = lool1A

103

o

FIGURE 20. TOTAL QUIESCENT CURRENT VB TEMPERATURE

I~=~IIA r-

102

!i:
w

50

TEMPERATURE (oC)

-

o

TEMPERATURE ("C)

FIGURE 19. OPEN LOOP VOLTAGE GAIN VB TEMPERATURE

VS=±6
TA=25oC
CA3078AT

150
100

~

·50

a:
a:

~

K3078A

5

80
·75

200

!i:w

1~

1~

FREQUENCY (Hz)

FIGURE 22. EQUIVALENT INPUT NOISE CURRENT VB
FREQUENCY

3·43

..J
c(Ul

zo:

OW

-u::

!C(:::i
0:11.
W::i

~c(

CA3078, CA3078A
Typical Performance Curves

1.5

...

REs.JoR~ckcrrbR
COMPENSATION
(R1 - C1 BETWEEN
TERMINALS 1 AND

0.75

III

0.5

~
...

I
If

I
J

/

0.25

0.6 r RES!SlOJAPACL
COMPENSATION
(R1 - C1 BETWEEN
~ 0.5 r
TERMINALS 1 AND.,...
~
III 0.4

V'

81

1.25

'"

~

~

I

(Continued)

I

CAPACITOR
COMPENSATION
(BETWEEN
TERMINALS 1 AND 8)

-

~
a: Q.3

-

~

III

/

10
20
30
40
50
60
70
80
80
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)

6

s'o

do

ao

19.1 29.7
40
70
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)

~

/cAPACITOR
COMPENSATION
(BETWEEN
TERMINALS 1 AND 8)

I

~V

II

I

10
20
30
40
50
60
70
80
90
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)

so

do

ao

/;
19.1 29.7
40
70
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)

Supply Volts: V+

=IOOI1A

9'0

=+6, V- =-6

Quiescent Current (Io) = 20l1A

Ambient Temperature (TA) = 25°C
Load Impedance: RL

V /

90

Supply Volts: V+ = +6, V- = -6
Quiescent Current (IO)

r~

0.2

0.1

~",

/

Ambient Temperature (TA) = 25°C

=10kQ, CL =100pF

Load Impedance: RL

=10kQ, CL =100pF

Feedback Resistance (RF) = 0.1 MQ

Feedback Resistance (RF) = 0.1 MQ

Output Voltage (Vop-p) = 10V

Output Voltage (Vop-p) = 10V

R1 determined for transient response with 10% overshoot on a
100mVoutput signal (Rt xCI = 2.5 x to- 6)

R t determined for transient response with 10% overshoot on a
100mV output signal (Rt x Ct = 2x 10-6 )

FIGURE 23_ SLEW RATE VB CLOSED LOOP GAIN FOR
IQ 100l1A - CA3078

FIGURE 24. SLEW RATE VB CLOSED LOOP GAIN FOR IQ =20l1A
-CA3078A

=

~

~1000

5

If
t§

~

100

~

I

"

~

III

...ffi

8
...~

-1000

~

If
t§

I

_ RESISlOR-CAPACITOR
COMPENSATION
(R1 - C1 BETWEEN
"
TERMINALS 1 AND 8)

"

4b

...ffi

10

TERMINALS 1 AND 8)

"~

III

~

~

10
20
30
40
50
60
70
80
90
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)

6

100

8

CAPACITOR

COMPENSATION
==
- (BETWEEN

';j?

z

o
~

~

to

1 0

~

CAPACITOR
COMPENSATION
(BETWEEN
~RMINALS 1 AND 8)

So

ao io

ld.l 29.7
80
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)

-

RESISlOR-CAPACITOR
COMPENSATION
(R1 - C1 BETWEEN
TERMINALS lAND 8)

....

I""..
1 0

10
20
30
40
50
60
70
80
80
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)

"""""""

Supply Volts: V+ = +6, V- = -6

Supply Volts: V+ = +6, V- = -6

Quiescent Current (IO) = 1001lA
Ambient Temperature (TA) = 25°C

Quiescent Current (lo) = 20l1A

Load Impedance: RL

So $0 io

19.1 ad.7 ~o
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)

6

IAl

ao

IAl

Ambient Temperature (TA) = 25°C

=10kQ, CL =100pF

Load Impedance: RL = 10kQ, CL = 100pF

Feedback Resistance (RF) = 0.1 MQ

Feedback Resistance (RF) = 0.1 MQ

Output Voltage (Vop-p) = 100mV

Output Voltage (vop-p) = 100mV

Rt determined for transient response with 10% overshoot on a
1OOmV output signal (Rt x Ct = 2.5 x 10-6)

Rt determined for transient response with 10% overshoot on a
1OOmV output signal (Rt x Ct = 2 x to- 6)

FIGURE 25. PHASE COMPENSATION CAPACITANCE VB
CLOSED LOOP GAIN - CA3078

FIGURE 26. PHASE COMPENSATION CAPACITANCE VB
CLOSED LOOP GAIN - CA3078A

3-44

CA30BO, CA30BOA

HARRIS
SEMICONDUCTOR

2MHz, Operational
Transconductance Amplifier (OTA)

November 1996

Features

Description

• Slew Rate (Unity Gain, Compensated) ••...... 50Vl/lS

The CA3080 and CA3080A types are Gatable-Gain Blocks
which utilize the unique operational-transconductanceamplifier (OTA) concept described in Application Note
AN6668, "Applications of the CA3080 and CA3080A HighPerformance Operational Transconductance Amplifiers".

• Adjustable Power Consumption ••..•.... 10/lW to 30/lW
• Flexible Supply Voltage Range .....•...• ±2V to ±15V
• Fully Adju~table Gain •.......••.••. 0 to gMRL Limit
• Tight gM Spread:
- CA3080 .•.......•..................•.•... 2:1
- CA3080A ...••...•...•..•....•..•..•.•... 1.6:1
• Extended gM Linearity •••.•••.••••••••.• 3 Decades

Applications
• Sample and Hold

• Multiplier

• Multiplexer
• Voltage Follower

• Comparator

The CA3080 and CA3080A types are notable for their excellent
slew rate (50V//lS), which makes them especially useful for
multiplexer and fast unity-gain voltage followers. These types
are especially applicable for multiplexer applications because
power is consumed only when the devices are in the "ON"
channel state.

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

PACKAGE

PKG.
NO.

o to 70

B Pin Metal Can

TB.C

CA30BOA

-55 to 125

B Pin Metal Can

TB.C

CA30BOAE

-55 to 125

B LdPDIP

EB.3

CA30BOAM
(30BOA)

-55 to 125

B Ld SOIC

MB.15

CA30BOAM96
(3080A)

-55 to 125

8 Ld SOIC Tape
and Reel

MB.15

CA30BO

The CA3080 and CA3080A types have differential input and a
single-ended, push-pull, class A output. In addition, these types
have an amplifier bias input which may be used either for gating
or for linear gain control. These types also have a high output
impedance and their transconductance (gM) is directly
proportional to the amplifier bias current (lABel.

CA30BOE

Oto 70

8 Ld PDIP

EB.3

CA3080M
(3080)

Oto 70

BLdSOIC

MB.15

CA30BOM96
(30BO)

Oto 70

8 Ld SOIC Tape
and Reel

MB.15

The CA3080A's characteristics are specifically controlled for
applications such as sample-hold, gain-control, multiplexing, etc.

Pinouts
CA30BO
(METAL CAN)
TOP VIEW

CA30BO
(PDIP, SOIC)
TOP VIEW

INV.
INPUT
NON-INV.
INPUT

:~~'UT

3

e

NON-INV.
INPUT

AMPLIFIER
BIAS INPUT

:

3

:+

TA

OUTPUT
BIAS

v-

NOTE: Pin 4 is connected to case.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

3-45

File Number

475.3

....I

c(1J)

Za:

O!!:!
-IL

!ci:::i
a: a..
W:ii

~c(

:,

'w

CA30BO, CA30BOA
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V- Terminal) ....... , , , , . , , 36V
Differential Input Voltage . .... , . , .... , , ... , , , , ........... 5V
Input Voltage. , , . , , ........ , .... , , . , . , .......... , , V+ to VInput Signal Current .... ,. , ... , ......... ' , .. , ........ lmA
Amplifier Bias Current (lABel, .. , . , . , , , .. , . , , , . . . . . . . .. 2mA
Output Short Circuit Duration (Note 1) ........ , .. , No Limitation

Thermal Resistance (Typical, Note 2)
6JA (oCIW) 6JC (oCIW)
PDIP Package ..... , . , , , . . . . . . . . .
130
N/A
SOIC Package ... , . , , . , . . . . . . . . . .
170
N/A
Metal Can Package ....... , , , . . . . .
200
120
Maximum Junction Temperature (Metal Can) •...... , .... , 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ..... , . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ...... , ... " 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
CA30BO ............. , , , .................. , .
to 70°C
CA30BOA .. , , . , ......... , .... , .. , ....... -55°C to 125°C

ooc

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device, This is a stress only reting and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied,

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. 6JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

For Equipment Design, VSUPPLY = ±15V, Unless Otherwise Specified

CA3080
PARAMETER
Input Offset Voltage

TEST CONDITIONS

TEMP

Input Offset Voltage Temp. Drift
Input Offset Voltage
Sensitivity

IPositive
INegative

TYP

IABC=5IlA ·

25

0,3

IABC= 5OOIlA

25

0.4

Full
Input Offset Voltage Change

MIN

IABC = 500ilA to 51lA

25

IABC = 1001lA

Full

IABC = 500ilA

25

-

IABC = 5001lA

25

Input Bias Current

IABC= 500ilA

25

-

5

MIN

TYP

MAX

UNITS

-

0.3

2

mV

-

0.4

2

mV

-

5

mV

0.1

3

6
0.2

-

-

-

3.0

150
150

-

0.12

0.6

-

2

5

-

25

Input Offset Current

CA3080A
MAX

Full

7

Differential Input Current

IABC = 0, VDIFF = 4V

25

Amplifier Bias Voltage

IABC= 500ilA

25

-

Input Resistance

IABC= 5OOIlA

25

10

Input Capacitance

IABC = 500IlA, f = 1 MHz

25

Input-to-Output Capacitance

IABC = 500IlA, f = 1MHz

25

Common-Mode Input-Voltage
Range

IABC = 5001lA

25

Forward Transconductance
(Large Signal)

IABC = 5001lA

Output Capacitance

IABC = 500IlA. f = 1MHz

25

Output Resistance

IABC= 500ilA

25

Peak Output Current

IABC = 51lA, RL = 00

25

IABC = 5001lA, RL = 00

25

350

500

Full

300

-

-

150

IlVN

150

IlVN

0.12

0,6

IlA

2

5

-

15

IlA
IlA
nA

0.008

5

0.71

-

0.71

-

26

10

26
3,6
0.024

0.008

-

0.024

-

12to
-12

13.610
-14.6

12to
-12

13.610
-14.6

25

6700

9600

13000

7700

9600

Full

5400

-

-

4000
5.6

-

-

3-46

-

3.6

-

5.6
15
5
650

mV
IlVPC

V
kO

-

pF
pF

V
12000

IlS

-

IlS

15

-

MO

3

5

7

IlA

350

500

650

IlA

300

pF

IlA

CA30BO, CA30BOA
Electrical Specifications

For Equipment Design, VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
CA3080

PARAMETER
Peak Output
Voltage

TEST CONDITIONS
Positive

13.8

V

-14.5

-12

-14.5

V

12

13.5

V

25
25

-

25

12

13.5

IABC = 500~A, RL = ~

MAX

-

-12

-14.4

-12

-14.4

25

0.8

1

1.2

0.8

1

1.2

mA

36

24

30

36

mW

-

0.08

5

nA

5

nA

-

dB

'ABC'= 500~A

25

24

30

25

-

0.08

'ABC = 0, VTP = 36V

25

0.3

0.3

Propagation Delay

IABC =500~A

25

45

4S

Common-Mode RejeC1ion Ratio

'ABC =500~A

25

Open-Loop Bandwidth

IABC = 500~A

25

Uncompensated

25

Compensated

25

Magnitude of Leakage Current

Slew Rate

UNITS

25

IABC = 0, VTP = 0

Device Dissipation

MAX

'ABC=500~A

Negative
Amplifier Supply Current

12

TYP

Negative
Positive

TYP

13.8

MIN

'ABC = 5~A, RL = ~

CA3080A

MIN

TEMP

80

110
2
75

-

50

-

80

110

-

2
75

-

50

V

ns

MHz

-

V/~s

V/~s

Schematic Diagram

...J

c(C/)

Za:

O!!:!
-II..

!i:i
a: a..
W:E
~c(

INVERTING
INPUT
NONINVERTING
INPUT
AMPLIFIER 5
BIAS INPUT

Typical Applications
V+ = 15V

VS=±15V

-,

62k.Q

LOAD
(SCOPE PROBE)

OUTPUT
WIDIV.

:fs;l

1

1MQ.J:---J

10k.Q V-

-.L

= -15V

INPUT
5VIDIV.

T

O.OOI~F

TIME ..o.II'81DIV.

FIGURE 1. SCHEMATIC DIAGRAM OF THE CA3080 AND CA3080A IN A UN/TY-GA/N VOLTAGE FOLLOWER CONFIGURATION
AND ASSOCIATED WAVEFORM

3-47

CA3080, CA3080A
Typical Applications

(Continued)

20pF

CENTERING

BUFFER VOLTAGE
FOLLOWER

+7.SV

THRESHOLD
DETECTOR

l00ka
+7.SV

7.SV
MAX FREQ. SET

MIN FREQ. SET

+7.SV o-,\".,.......W.,--W~-M- -7.SV
10kQ 6.2kQ
soon soon
FREQ.
ADJUST

2kQ

-

HIGH-FREQ.
LEVEL
ADJUST

FIGURE 2. 1,000,00011 SINGLEoCONTROL FUNCTION GENERATOR - 1MHz TO 1Hz

,NOTE: A Square-Wave Signal Modulates The External Sweeping
Input to Produce 1Hz and 1MHz, showing the 1,000,000/1 frequency
range of the function generator.

NOTE: The bottom trace is the sweeping signal and the top trace is
the actual generator output. The center trace displays the 1MHz signal
via delayed oscilloscope triggering of the upper swept output signal.

FIGURE 3A_ TWO-TONE OUTPUT SIGNAL FROM THE
FUNCTION GENERATOR

FIGURE 38. TRIPLE-TRACE OF THE FUNCTION GENERATOR
SWEEPING TO 1MHz

FIGURE 3. FUNCTION GENERATOR DYNAMIC CHARACTERISTICS WAVEFORMS

3-48

CA30BO, CA30BOA

Typical Applications

(Continued)

V+= +15V

2.0kn

SAMPLEOV

SLEW RATE (IN SAMPLE MODE) = 1.3V1lls
ACQUISmON TIME = 31ls (NOTE)

If
0----'

HOLD .15V

V·=·15V

NOTE: Time required for output to settle within ±3mV of a 4V step.

FIGURE 4. SCHEMATIC DIAGRAM OF THE CA3080A IN A SAMPLE-HOLD CONFIGURATION
..J

«In
Za:
O!!d
-u.

30kn
STROBE

01 nrSAMPLE
·15 UU HOLD

!cc:::i
a: a.

1N914

W::il

~«

3.6kn
INPUT

200pF

2kn

FI

200P
4000

L--IE--.......~ ....... !
O.lIlF

......

~; 30pF

SIMULATED LOAV.L
NOT REQUIRED
.::.

FIGURE 5. SAMPLE AND HOLD CIRCUIT

3-49

,.I
I'~

:

.;~:

CA30BO, CA30BOA
Typical Applications

(Continued)

Top Trace:
Bottom Trace:
Center Trace:

Output Signal
5V/Div.,211S/Div.
Input Signal
5V/Div.,211S/Div.
Difference of Input and Output Signals Through
Tektronix Amplilier 7A13
5mV/Div., 211S/Div.

FIGURE 6. LARGE SIGNAL RESPONSE AND SETTLING TIME FOR CIRCUIT SHOWN IN FIGURE 23

Top Trace:
Bottom Trace:

System Output; 1OOmV/Div., 500ns/Div.

Top Trace:

Sampling Signal; 20V/Div., 500ns/Div.

Bottom Trace:

Output; 50mV/Div., 200nslDiv.
Input; 50mV/Div., 200nS/Div.

FIGURE 8. INPUT AND OUTPUT RESPONSE FOR CIRCUIT
SHOWN IN FIGURE 23

FIGURE 7. SAMPLING RESPONSE FOR CIRCUIT SHOWN IN
FIGURE 23

120VAC
60Hz
2OK~"''"''i-W''''''''

NOTE: All resistors 1/2 watt,
unless otherwise specified.
FIGURE 9. THERMOCOUPLE TEMPERATURE CONTROL WITH CA3079 ZERO VOLTAGE SWITCH AS THE OUTPUT AMPLIFIER

3-50

CA30BO, CA30BOA
Typical Applications

INPUT

(Continued)

2K
2K

R7 j;PUT TCl
2K

=e.

SAMPLE OV
HOLD

1f.

-7.5

-;;OBE

g.30pF

(TYP)

200~~I}
'----~.
R3
!~R:~SEL-___________~_·5_V____~
400 =
NULLING

15K

COMPENSATION

FIGURE 10. SCHEMATIC DIAGRAM OF THE CA3080A IN A SAMPLE-HOLD CIRCUIT WITH SIMOS OUTPUT AMPLIFIER

-I

c:t(J)

Za:

O!!:!
-LL

tc:J

a: a.

W::i

~c:t

o
o
Top Trace:
Center Trace:
Bottom Trace:

Oulpul; 5V/Div., 2I's/Div.
Differential Comparison of Input and Output
2mV/Div., 21'S/Div.
Input; 5VlDiv., 21'S/Div.

Top Trace:
Bottom Trace:

FIGURE 11. LARGE-SIGNAL RESPONSE FOR CIRCUIT
SHOWN IN FIGURE 28

Output
20mV/Div.,100nslDiv.
Input
200mV/Div.,100nS/Div.

FIGURE 12. SMALL-SIGNAL RESPONSE FOR CIRCUIT SHOWN
IN FIGURE 28

3-51

CA30BO,CA30BOA
Typical Applications

som~ __
·SOmV-

-n-

(Continued)

IN 0 - . . - - - (

N-O

J-1--,.....,~--O OUT

S10

FIGURE 13. PROPAGATION DELAY TEST CIRCUIT AND ASSOCIATED WAVEFORMS

Typical Performance Curves
S

.s.
III

~

!:l

3

0

Iii
0

4
-4

:::)

-5

Ie
LL.

III.

2SOC

12SOC

SUPPLY VOLTS: Vs

19~!c r-"7

-5~C lU
~=J7 ~ooc

2
1

·1 ~t'""It I
90°C
·2

i

HI

SUPPLY VOLTS: Vs =±1SV
I
I II

4

>

III

r

.r

l: -5
-7
-8
0.1

10

Iii
Ie

1

il:

YSifl

I

8
~

/I
h

102

I

~

I I.'t.:" 25~
-5SOC
700 C

V-

~
-

IIII
I III
1

10

100

,

25°C
~

0.1

104

"

"
:....o!:

~

IE

t..oo":lI'!:;

1

a:
a:

f"....

I

10

=
=

100

1000

dl;E

·' 250

103

"..

8

102

!50

10

~

2SoC

/

~

~

,
0.1

1000

'"

1/
0.1

FIGURE 16. INPUT BIAS CURRENT vs AMPLIFIER BIAS CURRENT

.

·Ssoc

..,'"

S

......... 12SoC

1
10
100
AMPLIFIER BIAS CURRENT (IIA)

I

SUPPLY VOLTS: Vs ±1SV
LOAD RESISTANCE 00

II.

0.1
0.1

125°C

III

-ss°c

........

~.,

FIGURE 15. INPUT OFFSET CURRENT va AMPLIFIER BIAS
CURRENT

SUPPLY VOLTS: Vs =±15V

.....-.! ~

-5SoC

AMPLIFIER BIAS CURRENT (IIA)

FIGURE 14. INPUT OFFSET VOLTAGE vs AMPLIFIER BIAS
CURRENT

I""" I"""

"
" "

.,

AMPLIFIER BIAS CURRENT (IIA)

~

~~

/

0.01
0.1

1000

=+1SV

1
10
100
AMPLIFIER BIAS CURRENT (IIA)

1000

FIGURE 17. PEAK OUTPUT CURRENT va AMPLIFIER BIAS
CURRENT

3-52

CA30BO, CA30BOA

Typical Performance Curves
15

g

I

SUPPLY VOLTS: Vs = ±15V
TA= 25°C
LOAD RESISTANCE = 00

~ 14.5

~~

(Continued)

II

14

~~

0

"

",UI

Sg

-13

~ ~-13.5
«0
~ ~

125°C
V-OM
V-CMR

-15
0.1

I II

1
10
100
AMPLIFIER BIAS CURRENT ("A)

1000

~

ioI""

,

UI

~

0

gz
0

Z

102

10

105 SUPPLY VOLTS: Vs = +15V

.....
....
......

0

....

-55~
25°C

103

I-I--

III

z

Vs =±6V

«

II:
I-

102

~
II:

~

10

100

1

1000

!;:::i
a: a.

~

~

10

W::E

~<

100

1000

AMPLIFIER BIAS CURRENT (!!A)

FIGURE 21. TRANSCONDUCTANCE VB AMPLIFIER BIAS
CURRENT

~>OO
+36V

~

0.1

AMPLIFIER BIAS CURRENT (!!AI

FIGURE 20. TOTAL POWER DISSIPATION vs AMPLIFIER BIAS
CURRENT

iJ

~

...0

1
10

,

125°C

0

0

0.1

-

II:

I

UI

O!:!:!
-II.

104

0

Vs =±3V

III

..J


:.J I-

25°C

SUPPLY VOLTS: Vs = +15V

!zUI

SUPPLY VOLTS: Vs = ±15V

/'

II:

~ 10

~

o

UI

36V

OV

~

V2 = V3 = Va = 36V / '

......

~
.......o

~

UI

o
E
0.1

/'

z
~

I;tI"

::&
0.01
-50

/'
-25

OV

I/"

tr

/'

/'
,/

o

25
50
75
TEMPERATURE (oC)

100

FIGURE 23. LEAKAGE CURRENT vs TEMPERATURE

FIGURE 22. LEAKAGE CURRENT TEST CIRCUIT

3-53

'"

/'

125

CA30BO, CA30BOA

Typical Performance Curves

(Continued)

SUPPLY VOLTS: Vs = ±1SV
V+= 1SV

C

...Soz
w

II:
II:

104

103

::::>
CJ

125°C

..

~ 102

""

;r;

-'
!$

!zw

./
25°C

10

"

II:
W

""-

I

is

o

V· = ·1SV

SUPPLY VOLTS: Vs =±1SV
TA= 25°C

~

>

10

z

~

.,.

~
!:i

g

;r;

ID
II:

I!!

.
~

200
100

0.01
10
100
AMPLIFIER BIAS CURRENT (1lA)

z

~

~

~

o

~

Co

4
3

2

a

~

~

V"
".

---

!.

~ 103

iii
w

...

102

0

10

II:

~
~

=

"'"

i"'""

125°C

1000

SUPPLY VOLTS: Vs=±1SV
... TA = 25°C

--

z

In

",'"

~f-

104

CJ

~

25°C

1
10
100
AMPLIFIER BIAS CURRENT (1lA)

~S

!--

w

V
CI

~

P"'"

FIGURE 27. AMPLIFIER BIAS VOLTAGE VB AMPLIFIER BIAS
CURRENT

105

5

'-"~
I"'""

~

0.1

FIGURE 26. INPUT RESISTANCE VB AMPLIFIER BIAS CURRENT

CJ

-

o

1000

SUPPLY VOLTS: VS=±1SV
f= 1 MHz
TA= 25°C

·SSoC

- -

300

::I!

-<

6

500

!$ 400

--

..

~ 0.1

7

600

In

~

~
w

-

w 700

!!l

0.1

800

.§.

.....

CJ

7

6

SUPPLY VOLTS: Vs = ±1SV

900

100

w

2
3
4
5
INPUT DIFFERENTIAL VOLTAGE (V)

FIGURE 25. INPUT CURRENT vs INPUT DIFFERENTIAL VOLTAGE

FIGURE 24. DIFFERENTIAL INPUT CURRENT TEST CIRCUIT

.......

I

,,

... ...

...

~

;r;

o

0.1

1
1
10
100
AMPLIFIER BIAS CURRENT (1lA)

0.1

1000

FIGURE 28. INPUT AND OUTPUT CAPACITANCE VB AMPLIFIER
BIAS CURRENT

1
10
100
AMPLIFIER BIAS CURRENT (1lA)

FIGURE 29. OUTPUT RESISTANCE VB AMPLIFIER BIAS
CURRENT

3-54

1000

CA30BO,. CA30BOA
Typical Performance Curves

(Continued)

f= 1 MHz

[;"

So 0.06

V+

TA =2SoC

~
z

~ 0.05

13
~

..: 0.04

o

~

0.03

o

~ 0.02

i

" -r--.. """'-

-.... r--

r- I---

0.01

ii!:

o

V-

2

4

6

8

10

12

14

16

18

POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V)

FIGURE 30. INPUT-TO-OUTPUT CAPACITANCE TEST CIRCUIT

FIGURE 31. INPUT-TO-OUTPUT CAPACITANCE vs SUPPLY
VOLTAGE

..J

etC/)

Za:
O!!:!
-LL

~:J
a: a.

W:ail

~et

3-55

-----.:':~~094,

.CA3094A,
CA30948

30M Hz, High Output Current
ra lonal Transconductance Amplifier (OTA)
12

Features

Description

• CA3094T, E, M for Operation Up to 24V

The CA3094 is a differential input power control sw~chlampli·
fier with auxiliary circuit features for ease of programmability.
For example, an error or unbalance signal can be amplified by
the CA3094 to provide an on·off signal or proportional control
output signal u~to 100mA. This signal is sufficient to directly
drive high current thyristors, relays, DC loads, or power tran·
sistors. The CA3094 has the generic characteristics of the
CA30BO operational amplifier directly coupled to an integral
Darlington power transistor capable of sinking or driving currents up to 100mA.

• CA3094AT, E, M for Operation Up to 36V
• CA3094BT, M for Operation Up to ·44V
• Designed for Single or Dual Power Supply
• Programmable: Strobing, Gating, Squelching, AGC
Capabilities
• Can Deliver 3W (Average) or lOW (Peak) to External
Load (in Switching Mode)
• High Power, Single Ended Class A Amplifier will Deliver
Power Output of O.6W (l.6W Device Dissipation)
• Total Harmonic Distortion (THO) at O.6W in Class A
Operation 1.4% (Typ)

Applications
• Error Signal Detector: Temperature Control with
Thermistor Sensor; Speed Control for Shunt Wound
DC Motor
• Over Current, Over Voltage, Over Temperature Protectors
• Dual Tracking Power Supply with CA3085
• Wide Frequency Range Oscillator
• Analog Timer
• Level Detector

The gain of the differential input stage is proportional to the
amplifier bias current (lABC), permitting programmable
variation of the integrated circuit sensitivity with either digital
and/or analog programming signals. For example, at an IABC
of 1001lA, a 1mV change at the input will change the output
from 0 to 1001lA (typical).
The CA3094 is intended for operation up to 24V and is
especially useful for timing circuits, in automotive equipment,
and in other applications where operation up to 24V is a
primary design requirement (see Figures 2B, 29 and 30 in
Typical Applications text). The CA3094A and CA3094B are
like the CA3094 but are intended for operation up to 36V and
44V, respectively (single or dual supply).

Ordering Information

• Alarm Systems
• Voltage Follower
• Ramp Voltage Generator

PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

• High Power Comparator

CA3094T, AT, BT

·55 to 125

B Pin Metal Can

• Ground Fault Interrupter (GFI) Circuits

CA3094E, AE, BE

·5510 125

BLdPDIP

EB.3

CA3094M, AM, BM
(3094, A, B)

·5510 125

BLdSOIC

MB.15

PKG.
NO.

PACKAGE

TB.C

Pinouts
CA3094 (PDIP, SOle)
TOP VIEW
EXT. FREQUENCY
COMPENSATION
OR INHIBIT INPlIT

8

CA3094 (METAL CAN)
TOP VIEW
SINK OllTPlIT
(COLLECTOR)

SINK 0l1TPl1T
(COLLECTOR)

DRIVE OllTPlIT
(EMrrrER)
5

8

IABC CURRENT
PROGRAMMABLE ]
[ INPUT
(STROBE OR AGC)

DRIVE OllTPlIT
(EMrrrERI

IABC CURRENT

NOTE: Pin 4 is connected to case.

GND (V. IN DUAL
SUPPLY OPERATION)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-56

fi'ROGRAMMABLE INPlIT]
~STROBE OR AGC)

File Number

598.4

CA3100
38M Hz, Operational Amplifier

November 1996

Features

Description

• High Open Loop Gain at Video
Frequencies .................. 42dB (Typ) at 1MHz

The CA3100 is a large signal wideband, high speed
operational amplifier which has a unity gain cross over
frequency (fT) of approximately 38MHz and an open loop,
3dB corner frequency of approximately 110kHz. It can
operate at a total supply voltage of from 14V to 36V (±7V to
±18V when using split supplies) and can provide at least
18Vp_p and 30mAp_p at the output when operating from
±15V supplies. The CA3100 can be compensated with a
single external capacitor and has DC offset adjust terminals
for those applications requiring offset null. (See Figure 1).

• Unity Gain
Crossover Frequency (fT) •.•...•••.••. 38MHz (Typ)
• Full Power Bandwidth
Vo 18Vp_p ....................... 1.2MHz (Typ)

=

• Slew Rate
- 20dB Amplifier .................... 70Vl/ls (Typ)
- Unity Gain Amplifier .•..•.....•.•••• 25V1/ls (Typ)
• Settling Time .. .. .. .. .. .. .. .. .. .. .... O.6/ls (Typ)

The CA31 00 circuit contains both bipolar and PMOS transistors on a single monolithic chip.

• Output Current. .•..••••••••.••.•••.• ±15mA (Min)

Ordering Information

• Single Capacitor Compensation

PART NUMBER
(BRAND)

• Offset Null Terminals

Applications
• Video Amplifiers

TEMP.
RANGE (oC)

PACKAGE

PKG.
NO.

CA3100E

-4010B5

B Ld PDIP

EB.3

CA3100M
(3100)

-40 10 B5

BLdSOIC

MB.15

CA3100T

-5510125

B Pin Metal Can

TB.C

• Fast Peak Detectors
• Meter Driver Amplifiers
• High Frequency Feedback Amplifiers
• Video Pre-Drivers
• Oscillators
• Multivlbrators
• Voltage Controlled Oscillator
• Fast Comparators

Pinouts
CA3100
(PDIP, SOIC)
TOP VIEW

OFFSET
NULL
INV.
INPUT

CA31 00
(METAL CAN)

TOP VIEW

1
2

NO~j~~~ o.;3:..r---,•.-5 OFFSET
NULL

v-

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper Ie Handling Procedures.
Copyrighl © Harris Corporation 1996

3-57

File Number

625.3

CA3100
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V- Terminals) ............. 36V
Differential Input Voltage............................... 12V
Input Voltage to Ground ........................•... V+ to VOffset Terminal to V- Terminal Voltage. . . . . . . . . . . . . . . . .. ±0.5V
Output Current (Note 2) ................ , ............. 50rnA

Thermal Resistance (Typical, Note 1)
BJA (oCIW) BJC (oCIW)
PDIP Package...................
100
N/A
SOIC Package...................
165
N/A
170
85
Metal Can Package.. .. .. .. .. .. .. .
Maximum Junction Temperature (Metal Can) . . . . . . . . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range •....•..• _65°C to 150°C
Maximum Lead Temperature (Soldering 10s). • . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
CA3100E, CA3100M ....................... -40°C to 85°C
CA3100T ............................... -55°C to 125°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. BJA is measured with the component mounted on an evaluation PC board in Iree air.
2. CA31 00 does not contain circuitry to protect against short circuits in the output.

Electrical Specifications

TA = 25°C, VSUPPLY = ±15V, Unless Otherwise Specified

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

-

±1

±5

mV

DC
Input Offset Voltage

Via

Vo=O±D.W

Input Bias Current

liB

Vo=O±1V

0.7

2

IJA

Input Offset Current

110

Vo=O±1V

±D.05

±D.4

IJA

Common Mode Input Voltage Range

VICR

CMRR:?:76dB

±12

+14
-13

V

-

Common Mode Rejection Ratio

CMRR

VCM=±12V

76

90

Maximum Output Voltage

VOM+

Differential Input Voltage = 0 ±D.1V,
RL=2kQ

+9

'+11

-9

-11

V

Differential Input Voltage = 0 + O.W,
RL= 250Q

+15

+30

mA

-15

-30

-

mA

VOMMaximum Output Current

10M+

10MSupply Current
Power Supply Rejection Ratio

1+
PSRR

Va = 0 ±D.1V, RL:?: 10kQ

IN+=±1V,IN-=±W

dB
V

8.5

10.5

rnA

60

70

-

dB

DYNAMIC
Unity-Gain Crossover Frequency

IT

Open Loop Voltage Gain

AoL

Slew Rate

SR

Cc = 0, Vo = 0.3Vp_p

-

38

1= 1kHz, Va = ±1V, (Note 3)

56

61

1= 1MHz, Cc = 0, Vo = 10Vp_p

36

42

50

70

-

25

Av = 10, Cc = 0, VI = 1V (Pulse)
Av = 1, Cc = 10pF, VI = 10V (Pulse)

Full Power Bandwidth (Note 4)

FPBW

0.8

1.2

Av = 1, Cc = 10pF, Vo = 1BVp_p

-

0.4

Av = 10, Cc = 0, Va = 18Vp_p

Open Loop Differential Input Impedance

ZI

1= 1MHz

-

30

Open Loop Output Impedance

Zo

1= 1MHz

-

110

3-58

-

MHz
dB
dB
V/JJS
V/JJS
MHz
MHz
kQ
Q

CA3100
Electrical Specifications

TA = 25°C, V SUPPLY = ±15V, Unless Otherwise Specified (Continued)

PARAMETER

SYMBOL

Wideband Noise Voltage (RTI)

eN (Total)

Settling Time (To Within ±50mV of 9V
Output Swing)

ts

TEST CONDITIONS

MIN

BW= lMHz, Rs = lkQ
RL = 2kQ, CL = 20pF

TYP

MAX

UNITS

8

~VRMS

0.6

~s

NOTES:
3. Low frequency dynamic characteristic.
ew Rate.
4. Full Power Bandwidth = Siv
1t op-p

Test Circuits
V+

-'

 1MHz VI
POTENTIOMETER AND Vo MEASURED WITH
HF8405A VECTOR
VOLTMETER

~<

2200

V-

FIGURE 2. SLEW RATE IN lOX AMPLIFIER TEST CIRCUIT

FIGURE 1. OPEN-LOOP VOLTAGE GAIN TEST CIRCUIT AND
OFFSET ADJUST CIRCUIT

....- - - - - - - Av=100
1

10pF V+

..

+15V

RS

O.IIlF

-

V-

FIGURE 3. FOLLOWER SLEW RATE TEST CIRCUIT

- 1
=

-15V

FIGURE 4. WIDE BAND INPUT NOISE VOLTAGE TEST CIRCUIT

3-59

CA3100
Test Circuits

(Continued)
1pF
RL = 250n FOR 10M TEST

2kn

Vo

10M = 2"5oQ
9.1kn

Vo =±9V
> - - - ( 6 } -.....-f(»)

t
VOM
RL
2kn

-15V

-

+

1

51n

-

-

2kn

FIGURE 5. OUTPUT VOLTAGE SWING (VOM). OUTPUT
CURRENT SWING (10M) TEST CIRCUIT

12pF
2kn
SETTLING POINT TO SCOPE

FIGURE 6. SETTLING TIME TEST CIRCUIT

Schematic Diagram

R6
12kn
NONINVERT
INPUT

+

3~~-+--~-----+------,

OUTPUT

t--+--{6
~1r-~~~--+---~8
PHASE
COMP

Rg
200n
018

OFFSET
NULL

+-----+--+------(5
R14
1.1kn

~------+---------+---+------(1
R18
OFFSET
NULL
150n
AND PHASE
COMP

3-60

CA3100
Typical Applications
3dB BANDWIDTH
AcL = 20dB

= 15MHz

INPUT

r

·33~F
31en

3pF

g~~~~~;A~EL~~NG t-~~-+--r
SOQ LINE:
-3dB BANDWIDTH ~ 20MHz
TOTAL INPUT NOISE
'---~I--"" VOLTAGE REFERRED TO
INPUT ~ 3S~VRMS

FREQ
lMHz
2MHz
4MHz
6MHz

Vo
8V
5V
2V
lV

FIGURE 7. 20dB VIDEO AMPLIFIER

220Q
GAIN = 20dB

t-t-..---.......- '

-lSV

FIGURE 8. 20dB VIDEO LINE DRIVER

ZE~£~DJ

201en

+lSV

...I



iie

\

7.5

c

~

~

"

'-vICR

w
0

5.0

::E

z

~~

o

..,

w 12.5

Il.

~

15.0

CI

10

5

TA= 25°C

w

CI

Sl::E
8

~ p...

1

10

100

2.5

o

o

±2.5

±5

±7.5

FREQUENCY (MHz)

±10

±12.5 ±15

±17.5

FIGURE 19. MAXIMUM OUTPUT VOLTAGE SWING vs
FREQUENCY

FIGURE 20. COMMON MODE INPUT VOLTAGE RANGE vs
SUPPLY VOLTAGE

TA = 25°C
~
w

15

g

~
o
~

~

10

~

7.5

::E

::>
~

i

TA = 25°C
15

vt~~

~ 12.5

!:i

.c

~

~

~OM+

ztow

a:
a:

""

::>
0

::>

'"

±5

±7.5

±10

±12.5

±15

±17.5

~

7.5
5

-'"

2.5

o

±2.5

±5

SUPPLY VOLTAGE (V)

FIGURE 21. MAXIMUM OUTPUT VOLTAGE vs SUPPLY VOLTAGE

/"

12.5

w
a: 10.0
a:

::>

",. ~

0

'"~

7.5

!:i

5.0



II.

~

0

Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2
and zener diode ZI serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor Rl, diodes
01 through 04, and PMOS transistor 01. A tap at the junction
of resistor Rl and diode 04 provides a gate-bias potential of
about 4.5V for PMOS transistors 04 and Os with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected ,PMOS transistor 01 with respect to Terminal
7 to provide gate bias for PMOS transistors 02 and 03' It
should be noted that 01 is "mirror-connected (see Note 8)" to
both 02 and 03. Since transistors 01, 02, 03 are designed to
be identical,. the approximately 200llA current in 01 establishes a similar current in 02 and 03 as constant current
sources for both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener
diode ZI becomes nonconductive and the potential,
developed across series-connected Rl, 01-04, and 01, varies directly with variations in supply voltage. Consequently,
the gate bias for 04. 05 and 02, 03 varies in accordance
with supply-voltage variations. This variation results in

2.5

5

7.5

10

12.5

15

17.5

20

22.5

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE

Input Current Variation with Common Mode Input
Voltage

As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
TA = 250 C when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at TA 25°C.
These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the common-mode input voltage does not exceed 2V. As previously
noted, the input current is essentially the result of the leakage
current through the gate-protection diodes in the input circuit
and, therefore, a function of the applied voltage. Although the
finite resistance of the glass terminal-to-case insulator of the

3-68

=

CA3130, CA3130A
metal can package also contributes an increment of leakage
current, there are useful compensating factors. Because the
gate-protection network functions as if H is connected to Terminal 4 potential, and the Metal Can case of the CA3130 is
also internally tied to Terminal 4, input Terminal 3 is essentially "guarded" from spurious leakage currents.
r-~--~--r--'--~---r--r-~r-~--'

10

~

Input Offset Voltage (VIO) Variation with DC Bias and
Device Operating Life

7.5

w

CI

~
~

In applications requiring the lowest practical input current
and incremental increases in current because of "warm-up"
effects, it is suggested that an appropriate heat sink be used
with the CA3130. In addition, when "sinking" or "sourcing"
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input
current variations.

5

I-

::;)

A-

~

2.5

0
-1

0

2

3
4
5
6
INPUT CURRENT (pAl

7

FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,OOOQ potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer's total range.

It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users
of the CA3130 should be alert to the possible impacts of this
effect if the application of the device involves extended operation at high temperatures with a Significant differential DC
bias voltage applied across Terminals 2 and 3. Figure 5
shows typical data pertinent to shifts in offset voltage
encountered with CA3130 devices (metal can package) during life testing. At lower temperatures (metal can and plastic), for example at 850 C, this change in voltage is
considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental
changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The 2VDC differential voltage example
represents conditions when the amplifier output stage is
"toggled", e.g., as in comparator applications.
7
TA = 1250 C FOR TO-5 PACKAGES

Input-Current Variation with Temperature
The input current of the CA3130 Series circuits is typically
5pA at 250 C. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor-junction device, including
op amps with a junction-FET input stage, the leakage current
approximately doubles for every 100 C increase in temperature. Figure 4 provides data on the typical variation of input
bias current as a function of temperature in the CA3130.

>"

6

t:

5

III

4

§.

:E
II)

~

/"-

~

3

Iii
Ie

2

15

4000
Vs =±7.5V

1000

IZ

II:
II:

/

0
~

./

~
o

,

500

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) =OV
OUTPUT VOLTAGE =V+/2

1000 1500

2000 2500

3000 3500

4000

FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE
SHIFT VB OPERATING LIFE

,J

100

::;)

5
A-

..o!'V

~

TIME (HOURS)

i

w

o

/

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED

/
".

10

/

1

-80 -60 -40 -20

0

20

40

60

80

100 120 140

TEMPERATURE (DC)

FIGURE 4. INPUT CURRENT vs TEMPERATURE

3-69

--'
V,o/I>T

-

8

NOTES:
3. At Va = 26Vp_p, +12V, -14Vand RL = 2kn.
4. At RL = 2kn.

Electrical Specifications

For Design Guidance At V+ = 5V, V- = OV, TA = 25°C
TYPICAL VALUES

PARAMETER

SYMBOL

CA3140

CA3140A

UNITS

IVIOI

5

2

mV

11101

0.1

0.1

pA

Input Current

II

2

2

pA

O!:!:!
-LL

Input Resistance

RI

1

1

Tn

a:

AoL

100

100

kVN

100

100

dB

32

32

IlVN

90

90

dB

-0.5

-0.5

V

2.6

2.6

V

100

100

IlVN
dB

Input Offset Voltage
Input Offset Current

Large Signal Voltage Gain (See Figures 6, 29)

Common Mode Rejection Ratio

CMRR

Common Mode Input Voltage Range (See Figure 8)

VieR

Power Supply Rejection Ratio

PSRR

I>VIOII>VS
Maximum Output Voltage (See Figures 2, 8)

Maximum Output Current:

ISource

ISink

80

80

VOM+

3

3

V

VOM-

0.13

0.13

V

10M+

10

10

mA

10M-

1

1

mA

Slew Rate (See Figure 31)

SR

7

7

V/IlS

Gain-Bandwidth Product (See Figure 30)

fT

3.7

3.7

MHz

Supply Current (See Figure 32)

1+

1.6

1.6

mA

Po

8

8

mW

200

200

IlA

Device Dissipation
Sink Current from Terminal 8 to Terminal 4 to Swing Output Low

3·81

..J
oI(U)

Za:

tcc:J0.

W:iii

~01(

CA3140, CA3140A
Block Diagram

- - - - - - - - - - - -2;; - - - - - - - - - - 4';A~
7

v+

I

I

2mA:

L-~~----~~~-i------

__--~~4

~

8::.:. ;';;B; ~
Schematic Diagram
BIAS CIRCUIT

INPUT STAGE

SECOND STAGE

p-------- .. ------------. r-----

01~

OUTPUT STAGE

DYNAMIC CURRENT SINK

____•

Ra

+-~~

______ ________
~

~~

____

1K ala
-;~~~-,

~~~

____

+-~~~-<'6

._------- ._------OFFSET NULL

STROBE

NOTE: All resistance values are in ohms.

3-82

v-

OUTPUT

CA3140, CA3140A
Application Information
Circuit Description

As shown in the block diagram, the input terminals may be
operated down to O.5V below the negative supply rail. Two
class A amplifier stages provide the voltage gain, and a
unique class AB amplifier stage provides the current gain
necessary to drive low-impedance loads.
A biasing circuit provides control of cascoded constant current
flow circuijs in the first and second stages. The CA3140
includes an on chip phase compensating capacitor that is
sufficient for the unity gain voltage follower configuration.
Input Stage

The schematic diagram consists of a differential input stage
using PMOS field-effect transistors (09, 010) working into a
mirror pair of bipolar transistors (011, 012) functioning as load
resistors together wijh resistors R2 through Rs. The mirror pair
transistors also function as a differential-to-single-ended
converter to provide base current drive to the second stage
bipolar transistor (Od. Offset nulling, when desired, can be
effected with a 10kn potentiometer connected across
Terminals 1 and 5 and wijh ijs slider arm connected to Terminal
4. Cascode-connected bipolar transistors 02, 05 are the
constant current source for the input stage. The base biasing
circuij for the constant current source is described
subsequently. The small diodes D3, D4, D5 provide gate oxide
protection against high voHage transients, e.g., static electricity.
Second Stage

Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor 013
and its cascode connected load resistance provided by
bipolar transistors 03, 04' On-chip phase compensation,
sufficient for a majority of the applications is provided by C1.
Additional Miller-Effect compensation (roll off) can be
accomplished, when desired, by simply connecting a small
capacitor between Terminals 1 and 8. Terminal 8 is also
used to strobe the output stage into quiescence. When
terminal 8 is tied to the negative supply rail (Terminal 4) by
mechanical or electrical means, the output Terminal 6
swings low, I.e., approximately to Terminal 4 potential.
Output Stage

The CA3140 Series circuits employ a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Ouiescent current in the emitter-follower cascade
circuit (017, 018) is established by transistors (014, 015)
whose base currents are "mirrored" to current flowing through
diode D2 in the bias circuit section. When the CA3140 is
operating such that output Terminal 6 is sourcing current,
transistor 018 functions as an emitter-follower to source current
from the V+ bus (Terminal 7), via ~, R9, and R11' Under these
conditions, the collector potential of 013 is sufficiently high to
permit the necessary flow of base current to emitter follower
017 which, in turn, drives 018'
When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor 016 is the current
sinking element. Transistor 016 is mirror connected to D6, R7,

wijh current fed by way of 021, R12, and 020' Transistor 020, in
turn, is biased by current flow through R13, zener D8, and R14'
The dynamic current sink is controlled by voltage level sensing.
For purposes of explanation, it is assumed that output Terminal
6 is quiescently established at the potential midpoint between
the V+ and V- supply rails. When output current sinking mode
operation is required, the collector potential of transistor 013 is
driven below its quiescent level, thereby causing 017, 018 to
decrease the output voltage at Terminal 6. Thus, the gate
terminal of PMOS transistor 021 is displaced toward the V- bus,
thereby reducing the channel resistance of 021' As a
consequence, there is an incremental increase in current flow
through 020, R12, 021, D6, R70 and the base of 016. As a
result, 016 sinks current from Terminal 6 in direct response to
the incremental change in output voltage caused by 018' This
sink current flows regardless of load; any excess current is
intemally supplied by the emitter-follower 018' Short circuit
protection of the output circuit is provided by 019, which is
driven into conduction by the high voltage drop developed
across R11 under output short circuij conditions. Under these
conditions, the collector of 019 diverts current from ~ so as to
reduce the base current drive from 017, thereby limiting current
flow in 018 to the short circuited load terminal.
Bias Circuit

..J

Ouiescent current in all stages (except the dynamic current
sink) of the CA3140 is dependent upon bias current flow in R1'
The function of the bias circuit is to establish and maintain
constant current flow through D1, 06, 08 and D2. D1 is a diode
connected transistor mirror connected in parallel wijh the base
emitter junctions of 01, 02, and Os. D1 may be considered as a
current sampling diode that senses the emitter current of 06
and automatically adjusts the base current of 06 (via 01) to
maintain a constant current through 06, 08, D2. The base
currents in 02, 03 are also determined by constant current flow
D1' Furthermore, current in diode connected transistor 02
establishes the currents in transistors 014 and 015'

O!!!
-II..

Typical Applications
Wide dynamic range of input and output characteristics with
the most desirable high input impedance characteristics is
achieved in the CA3140 by the use of an unique design based
upon the PMOS Bipolar process. Input common mode voltage
range and output swing capabilities are complementary,
allowing operation with the single supply down to 4V.
The wide dynamic range of these parameters also means
that this device is suitable for many single supply applications, such as, for example, where one input is driven below
the potential of Terminal 4 and the phase sense of the output
signal must be maintained - a most important consideration
in comparator applications.
Output Circuit Considerations

Excellent interfaCing with TTL circuitry is easily achieved with a
single 6.2V zener diode connected to Terminal 8 as shown in
Figure 1. This connection assures that the maximum output signal swing will not go more positive than the zener voltage minus
two base-to-emitter voltage drops wijhin the CA3140. These
voltages are independent of the operating supply voltage.

3-83

etC/)

za:

!ci:J
a: 0..
w:a
~et

CA3140, CA3140A
Figure 4 shows some typical configurations. Note that a
series resistor, RL, is used in both cases to limit the drive
available to the driven device. Moreover, it is recommended
that a series diode and shunt diode be used at the thyristor
input to prevent large negative transient surges that can
appear at the gate of thyristors, from damaging the
integrated circuit.

TYPICAL
TTL GATE

Offset Voltage Nulling
The input offset voltage can be nulled by connecting a 10kn
potentiometer between Terminals 1 and 5 and returning its
wiper arm to terminal 4, see Figure 3A. This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is
not fully utilized. Typical values of series resistors (R) that
may be placed at either end of the potentiometer, see Figure
3B, to optimize its utilization range are given in the Electrical
Specifications table.

FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO
TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT
SWING TO TTL LEVELS

1000

q;

a

SUPPLY VOLTAGE (V.) = OY
TA = 25°C

I I III I

:2>

!!E

a:~

L&I

~~

100

v

10

An alternate system is shown in Figure 3C. This circuit uses
only one additional resistor of approximately the value
shown in the table. For potentiometers, in which the resistance does not drop to on at either end of rotation, a value of
resistance 10% lower than the values shown in the table
should be used.

1/ 1/ +:lOY

.~

!!=i5
~:::)

i/
+15V

/

~~
~~

)

I-

SUPPLY YOLTAGE (Y+) = +5Y

~~

~

v

sa
s""

Low Voltage Operation
Operation at total supply voltages as low as 4V is possible
with the CA3140. A current regulator based upon the PMOS
threshold voltage maintains reasonable constant operating
current and hence consistent performance down to these
lower voltages.

0

1
0.1

C!,01

1.0

10

LOAD (SINKING) CURRENT (mA)

FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15
AND Q16) VB LOAD CURRENT

Figure 2 shows output current sinking capabilities of the
CA3140 at various supply voltages. Output voltage swing to
the negative supply rail permits this device to operate both
power transistors and thyristors directly without the need for
level shifting circuitry usually associated with the 741 series
of operational amplifiers.

The low voltage IimHation occurs when the upper extreme of
the input common mode voltage range extends down to the
voltage at Terminal 4. This limit is reached at a total supply
voltage just below 4V. The output voltage range also begins to
extend down to the negative supply rail, but is slightly higher
than that of the input. Figure 8 shows these characteristics and
shows that with 2V dual supplies, the lower extreme of the input
common mode voltage range is below ground potential.

v·
FIGURE 3A. BASIC

Y·
FIGURE 3B. IMPROVED RESOLUTION

FIGURE 3C. SIMPLER IMPROVED
RESOLUTION

FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS

3-84

CA3140, CA3140A

30V

t-----. NO LOAD
120VAC

FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
FOLLOWER

SIMULATED
LOAD

>!.. ~

l00pF ;:; ~ 2k.Q

: ?
"-"
.~'::

....I

LOAD RESISTANCE (RLl = 2k.Q
LOAD CAPACITANCE (CU = l00pF
SUPPLY VOLTAGE: Vs =±15V
TA = 25°C
10

J

8
6

~

4

UJ

Cl

~
:.J

~

!:iCo
~

2
0

·2

·4
·6
·8

·10
0.1

10mV"

,

lm~

'lOmV

L,'

~

~

-r-.

""
~

~

-

tt::i0..

INVERTING
5k.Q

,lmV

a:

W:i:

g,et

.,'"

V ,
1..11 .......
/ "
1-

. .'...

etC/)
za:
O!!!
-1.1..

O.o5Ilf"

SIMULATED
LOAD

FOLLOWER

• • • • INVERTING

~~

~~IlmV- r-

lmV

l°iV~ ,\:omv '
1.0
SETTUNG TIME (1lS)

,~\

10

FIGURE SA. WAVEFORM

FIGURE SB. TEST CIRCUITS

FIGURE 5. SETTLING TIME vs INPUT VOLTAGE

Bandwidth and Slew Rate

Input Circuit Considerations

For those cases where bandwidth reduction is desired, for
example, broadband noise reduction, an external capacitor
connected between Terminals 1 and 8 can reduce the open
loop ·3dB bandwidth. The slew rate will, however, also be
proportionally reduced by using this additional capacitor.
Thus, a 20% reduction in bandwidth by this technique will
also reduce the slew rate by about 20%.

As mentioned previously, the amplifier inputs can be driven
below the Terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input pro·
tection circuitry.

Figure 5 shows the typical settling time required to reach
1mV or 10mV of the final value for various levels of large
signal inputs for the voltage follower and inverting unity gain
amplifiers. The exceptionally fast settling time characteristics
are largely due to the high combination of high gain and wide
bandwidth of the CA3140; as shown in Figure 6.

Moreover, some current limiting resistance should be
provided between the inverting input and the output when
the CA3140 is used as a unity gain voltage follower. This
resistance prevents the possibility of extremely large input
signal transients from forcing a signal through the input
protection network and directly driving the internal constant
current source which could result in positive feedback via the
output terminal. A 3.9k.Q resistor is sufficient.

3·85

CA3140, CA3140A
10K

SUPPLY VOLTAGE: Vs = +15V

/
C

1K

...az

~

Ul

It:
It:

60
40

RL=2kn,
CL=100pF

20

~

::>

U

!;
I>.

iiE

103
104
106
105
FREQUENCY (Hz)

102

-60

It:

~;t
UlCl ....

~~

$!:ii

-0.5

+VICR ATTA = 125°C !--

-1.0

+VICR AT TA = -55°C

+VICR ATTA = 25°C

r--

I J

~

1

I!::I
::>0

::>

U

+VOUT AT TA = 125°C

-2.5

~
!;

-3.0

...

iiE

1.0

Cl ...

0.5 --VOUTFOR
T = -ss°c to 125°C
0

j!ic

g~

!:i~

-2.0

-

111~

Ul ...

+VOUTATTA=250C
+VOUT AT TA = -550C

-1.5

oClio
It:

20
40
60
60
TEMPERATURE (OC)

1.5

It:

... It:

::>j!!

0

100

120

140

Z

1 11

::>

-20

UI

RL=OO
0

-40

FIGURE 7. INPUT CURRENT vs TEMPERATURE

UI

Z

~

1

108

107

FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY

9

/

10

1/

~

0
101

UI

1/

100

11

I

-VICR AT TA = 125°C
-VICR AT TA = 25°C
-VICR AT TA = -55 0C

1>.:1 -0.5

!:iii!

gil.
Z
C

-1.5

!:iI>.
o

5

10
15
,SUPPLY VOLTAGE (V+, V-)

20

-1.0

iiE

25

o

5

10
15
SUPPLY VOLTAGE (V+, V-)

20

25

FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE

The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, device dissipation will increase,
raising the chip temperature and resulting in increased input
current. Figure 7 shows typical input terminal current versus
ambient temperature for the CA3140.

same magnitude as those encountered in an operational
amplifier employing a bipolar transistor input stage.

It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in
input offset voltage) due to the application of large differential input voltages that are sustained over long periods at elevated temperatures.
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts of
the opposite polarity reverse the offset. Figure 9 shows the
typical offset voltage change as a function of various stress
voltages at the maximum rating of 12SoC (for metal can); at
lower temperatures (metal can .and plastic), for example, at
8SoC, this change in voltage is considerably less. In typical linear applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the

3-86

7

Ii:

TA = 125°C
FOR METAL CAN PACKAGES
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
5 I- OUTPUT STAGE TOGGLED

III
Ul

4

.s>
:f

~

!j

$!

IiiIII

...

6

V

3

2

II.

0

o

tt
....
o

r
_

/

./

~
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = ov
OUTPUT VOLTAGE = V+ 12

_

-

I

500 1000 1SOD ,2000 2500 3000 3500 4000 4500
TIME (HOURS)

FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT VB OPERATING LIFE

CA3140, CA3140A
Super Sweep Function Generator
A function generator having a wide tuning range is shown in
Figure 10. The 1,000,000/1 adjustment range is accomplished by a single variable potentiometer or by an auxiliary
sweeping signal. The CA3140 functions as a non-inverting
readout amplifier of the triangular signal developed across
the integrating capacitor network connected to the output of
the CA30S0A current source.
Buffered triangular output signals are then applied to a second CA30S0 functioning as a high speed hysteresis switch.
Output from the switch is returned directly back to the input
of the CA30S0A current source, thereby, completing the pos·
itive feedback loop
The triangular output level is determined by the four 1N914
level limiting diodes of the second CA30S0 and the resistor
divider network connected to Terminal No.2 (input) of the
CA30S0. These diodes establish the input trip level to this
switching stage and, therefore, indirectly determine the
amplitude of the output triangle.
Compensation for propagation delays around the entire loop
is provided by one adjustment on the input of the CA30S0.
This adjustment, which provides for a constant generator
amplitude output, is most easily made while the generator is
sweeping. High frequency ramp linearity is adjusted by the
single 7pF to 60pF capacitor in the output of the CA30S0A.
It must be emphasized that only the CA30S0A is
characterized for maximum output linearity in the current
generator function.

Now, only the reference voltage must be established to set
the lower limit on the meter. The three remaining transistors
from the CA30S6 Array used in the sweep generator are
used for this reference voltage. In addition, this reference
generator arrangement tends to track ambient temperature
variations, and thus compensates for the effects of the normal negative temperature coefficient of the CA30S0A VABC
terminal voltage.
Another output voltage from the reference generator is used
to insure temperature tracking of the lower end of the
Frequency Adjustment Potentiometer. A large series
resistance simulates a current source, assuring similar
temperature coefficients at both ends of the Frequency
Adjustment Control.
To calibrate this circuit, set the Frequency Adjustment
Potentiometer at its low end. Then adjust the Minimum
Frequency Calibration Control for the lowest frequency. To
establish the upper frequency limit, set the Frequency
Adjustment Potentiometer to its upper end and then adjust
the Maximum Frequency Calibration Control for the
maximum frequency. Because there is interaction among
these controls, repetition of the adjustment procedure may
be necessary. Two adjustments are used for the meter. The
meter sensitivity control sets the meter scale width of each
decade, while the meter position control adjusts the pOinter
on the scale with negligible effect on the sensitivity
adjustment. Thus, the meter sensitivity adjustment control
calibrates the meter so that it deflects 1/6 of full scale for
each decade change in frequency.
Sine Wave Shaper

Meter Driver and Buffer Amplifier
Figure 11 shows the CA3140 connected as a meter driver
and buffer amplifier. Low driving impedance is required of
the CA30S0A current source to assure smooth operation of
the Frequency Adjustment Control. This low-driving
impedance requirement is easily met by using a CA3140
connected as a voltage follower. Moreover, a meter may be
placed across the input to the CA30S0A to give a logarithmic
analog indication of the function generator's frequency.
Analog frequency readout is readily accomplished by the
means described above because the output current of the
CA30S0A varies approximately one decade for each 60mV
change in the applied voltage, VABC (voltage between
Terminals 5 and 4 of the CA30S0A of the function generator).
Therefore, six decades represent 360mV change in VABC.

The circuit shown in Figure 12 uses a CA3140 as a voltage
follower in combination with diodes from the CA3019 Array
to convert the triangular signal from the function generator to
a sine-wave output signal having typically less than 2% THO.
The basic zero crossing slope is established by the 10kQ
potentiometer connected between Terminals 2 and 6 of the
CA3140 and the 9.1ka resistor and 10ka potentiometer
from Terminal 2 to ground. Two break points are established
by diodes 01 through 04. Positive feedback via 05 and 06
establishes the zero slope at the maximum and minimum
levels of the sine wave. This technique is necessary because
the voltage follower configuration approaches unity gain
rather than the zero gain required to shape the sine wave at
the two extremes.

3-S7

..J

;;b_

7. 25Vp_p output at 20kHz.

5.1
MO

8. -3dB at 24kHz from 1kHz reference .

BOOST

FOR DUAL SUPPLIES

TREBLE
CUT
2OOkO
(LINEAR) O.OOlIlF

+15V

100pF

2.2MO

lMO
100kO
10kO
CCW(LOG)
BOOST
BASS
CUT
TONE CONTROL NETWORK

-=-

--------------_.
FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)

FOR SINGLE SUPPLY
BOOST

0.0471lF

BASS
CUT
(LINEAR)
240kO
5MO
240kO
FOR DUAL SUPPLIES

750
pF

+15V

SMa
51kO
(LINEAR)
BOOST TREBLE
CUT
TONE CONTROL NETWORK

NOTES:
9. ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively,
10, 25Vp_p Output at 20kHz.
11. -3dB at 70kHz from 1kHz Reference.
12. OdB Flat Position Gain.

FIGURE 20. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES

3-92

CA3140, CA3140A
Wien Bridge Oscillator

.....

r-----~----

Another application of the CA3140 that makes excellent use
of its high input impedance, high slew rate, and high voltage
qualities is the Wien Bridge sine wave oscillator. A basic Wien
R2 R
Bridge oscillator is shown in Figure 21. When Rl
C2
C, the frequency equation reduces to the
and Cl
familiar f = 1/(27tRC) and the gain required for oscillation,
Aosc is equal to 3. Note that if C2 is increased by a factor of
four and R2 is reduced by a factor of four, the gain required
for oscillation becomes 1.5, thus permitting a potentially
higher operating frequency closer to the gain bandwidth
product of the CA3140.

=

=

=

f =

OUTPUT

-O

19Vp.p TO 22Vp.p
THO <0.3%

=

50Hz,
100Hz,
1kHz,
10kHz,
30kHz,

;:-2"-Jr.R;;=1~C:=1~R2=;C""'2

R = 3.3MO

R= 1.6MO
R = 160MO
R = l6MO
R = 5.1MO

soon

FIGURE 22. WIEN BRIDGE OSCILLATOR CIRCUIT USING

CA3140
Simple Sample-and-Hold System

FIGURE 21. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT
USING AN OPERATIONAL AMPLIFIER

Oscillator stabilization takes on many forms. It must be
precisely set, otherwise the amplitude will either diminish or
reach some form of limiting with high levels of distortion. The
element, RS, is commonly replaced with some variable
resistance element. Thus, through some control means, the
value of RS is adjusted to maintain constant oscillator
output. A FET channel resistance, a thermistor, a lamp bulb,
or other device whose resistance increases as the output
amplitude is increased are a few of the elements often
utilized.
Figure 22 shows another means of stabilizing the oscillator
with a zener diode shunting the feedback resistor (RF of
Figure 21). As the output signal amplitude increases, the
zener diode impedance decreases resulting in more
feedback with consequent reduction in gain; thus stabilizing
the amplitude of the output signal. Furthermore, this
combination of a monolithic zener diode and bridge rectifier
circuit tends to provide a zero temperature coefficient for this
regulating system. Because this bridge rectifier system has
no time constant, i.e., thermal time constant for the lamp
bulb, and RC time constant for filters often used in detector
networks, there is no lower frequency limit. For example,
with 11!F polycarbonate capaCitors and 22MQ for the
frequency determining network, the operating frequency is
O.007Hz.
As the frequency is increased, the output amplitude must be
reduced to prevent the output signal from becoming slewrate limited. An output frequency of 180kHz will reach a slew
rate of approximately 9V11!S when its amplitude is 16Vp_p.

Figure 23 shows a very simple sample-and·hold system
using the CA3140 as the readout amplifier for the storage
capacitor. The CA3080A serves as both input buffer
amplifier and low feed-through transmission switch (see
Note 13). System offset nulling is accomplished with the
CA3140 via its offset nulling terminals. A typical simulated
load of 2kQ and 30pF is shown in the schematic.
30k!:!

smoBE

0,

o-~y.,...,

lN914

·15

n

rSAMPLE

UU

HOLD

3.5k!:!
INPUT{~~IIo-Q}I

2k!:!

.-

'-1E-.............. ,.t l

=

0.1""

30pF ;;

SIMULATED LOAD .......
NOT REQUIRED
'.V

.•

··.V

FIGURE 23. SAMPLE AND HOLD CIRCUIT

In this circuit, the storage compensation capacitance (Cl) is
only 200pF. Larger value capacitors provide longer "hold"
periods but with slower slew rates. The slew rate is:
dv

dt

=

cI = O.5mA1200pF = 2.5V/I1S

NOTE:
13. AN666B "Applications of the CA30BO and CA 30BOA High Per·

formance Operational Transconductance Amplifiers".

3·93

..J

«en
Za:

O!!:!
-u.
!;:~

a:

0.

W:E

~«

CA3140, CA3140A
Pulse "droop" during the hold interval is 170pAl200pF which is
(Le., 170pAl200pF). In this case, 170pA represents
the typical leakage current of the CA3080A when strobed off. If
C1 were increased to 2000pF, the "hold-droop" rate will
decrease to O.085~V1~, but the slew rate would decrease to
O.25V/~s. The parallel diode network connected between
Terminal.3 of the CA3080A and Terminal 6 of the CA3140
prevents large input signal feedthrough across the input
terminals of the CA3080A to the 200pF storage capacitor when
the CA3080A is strobed off. Figure 24 shows dynamic
characteristic waveforms of this sample-and-hold system.

Current Amplifier

O.85!lV/~s;

The low input terminal current needed to drive the CA3140
makes it ideal for use in current amplifier applications such
as the one shown in Figure 25 (see Note 14). In this circuit,
low current is supplied at the input potential as the power
supply to load resistor RL. This load current is increased by
the multiplication factor R2/R1, when the load current is monitored by the power supply meter M. Thus, if the load current
is 100nA, with values shown, the load current presented to
the supply will be 100IlA; a much easier current to measure
in many systems.

1Dk!1
+15V

I

10M!1

IL

.L.

Top Trace: Output; 50mV/Div., 200nS/Div.

'j

Bottom Trace: Input; 50mV/Div" 200nS/Div.
4.3kQ

-15V
FIGURE 25. BASIC CURRENT AMPLIFIER FOR LOW CURRENT
MEASUREMENT SYSTEMS

Note that the input and output voltages are transferred at the
same potential and only the output current is multiplied by
the scale factor.

Top Trace: Output Signal; 5V/Div, 2I's/Div.
Center Trace: Difference of Input and Output Signals through
Tektronix Amplifier 7A13; 5mV/Div., 21'S/Div.
Bottom Trace: Input Signal; 5V/Div., 21'S/Div.
LARGE SIGNAL RESPONSE AND SETTLING TIME

The dotted components show a method of decoupling the
circuit from the effects of high output load capacitance and
the potential oscillation in this situation. Essentially, the
necessary high frequency feedback is provided by the
capacitor with the dotted series resistor providing load
decoupling.
Full Wave Rectifier

Figure 26 shows a single supply, absolute value, ideal fullwave rectifier with associated waveforms. During positive
excursions, the input signal is fed through the feedback
network directly to the output. Simultaneously, the positive
excursion of the input signal also drives the output terminal
(No.6) of the inverting amplifier in a negative going
excursion such that the 1N914 diode effectively disconnects
the amplifier from the signal path. During a negative going
excursion of the input signal, the CA3140 functions as a
normal inverting amplifier with a gain equal to -R21R1' When
the equality of the two equations shown in Figure 26 is
satisfied, the full wave output is symmetrical.
SAMPLING RESPONSE
Top Trace: Output; 1OOmV/Div., 500ns/Div.
Bottom Trace: Input; 20V/Div., 500ns/Div.
FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC
CHARACTERISTICS WAVEFORMS

NOTE:
14. "Operational Amplifiers Design and Applications", J. G. Graeme,
McGraw-Hili Book Company, page 308, "Negative Immittance
Converter Circuits".

3-94

CA3140, CA3140A
~

Skn

~w

+1SV

NVV\

10kn

SIMULATED
LOAD

INPUT

> ..... -,
I

100pF ;.;

.: 2kn

I

".r,.
-1SV

=
R2

GAIN = -

R1

R3
= X = .....""---.;R1R2+R3

SW (-3dS) = 4.SMHz
SR = 9V1I1S

O.OSI1F

FIGURE 28A. TEST CIRCUIT

X + X2)
R3 = ( ~ R1
Skn
R2
FOR X = O.S 10kn = R

1

R3 = 10kn(0.7S) = 1Skn
O.S

20Vp_p Input BW (-3d B) = 290kHz, DC Output (Avg) = 3.2V

OUTPUT

Top Trace: Output; SOmV/Div., 200nS/Div.

o

Bottom Trace: Input; SOmV/Div., 200nS/Div.

FIGURE 28B. SMALL SIGNAL RESPONSE

INPUT

o

FIGURE 26. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL
WAVE RECTIFIER WITH ASSOCIATED
WAVEFORMS

NOISE VOLTAGE
OUTPUT

(Measurement made with Tektronix 7A13, differential amplifier.)
Top Trace: Output Signal; SV/Div., S~S/Div.
Center Trace: Difference Signal; SmV/Div., S/ls/Div.
Bottom Trace: Input Signal; SV/Div., S/ls/Div.
SW (-3dS) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 4811V (TYP)

1kn

FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME

FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENT

FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST
CIRCUIT AND ASSOCIATED WAVEFORMS

3-95

CA3140, CA3140A

Typical Performance Curves
20
RL=2kll

RL = 2kll
CL= 100pF

"N'

:r:

!.
."

Z
~
w

~~

125

~Do

Z

25

~

z

a'i
z

c

o
o

1

5

15
10
SUPPLY VOLTAGE (V)

20

25

25°C
125°C

20

~ 15

..

10

-

c
L.

TA-,550C

IE
II!a::

25°C
~250C

TA=~
5

25

~~

Do

~

IE
~
III

10
15
SUPPLY VOLTAGE (V)

20

25

5

100K

_

25°C

-

3

.All ~

-

r

2
1

o
o

5

10
15
SUPPLY VOLTAGE (V)

20

25

FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE AND TEMPERATURE

SUPPLY VOLTAGE: Vs = t15V
TA = 25°C

1111 I

~

\

,

..........:: ~ "."
125°C

~

SUPPLY VOLTAGE: Vs d15V
TA=25oC

10K

20

6

~

FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND
TEMPERATURE

o

15

7

u 4

8
5

10

5

RL=OO

5

S oo

o

FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGE AND TEMPERATURE

g

Ie

LL

SUPPLY VOLTAGE (V)

RL = 2kll
CL= 100pF

a::

TA=-550C

"

RGURE 29. OPEN-LOOP VOLTAGE GAIN lIs SUPPLY
VOLTAGE AND TEMPERATURE



r-..

.....

sz
LJJ

10

10 3

10 2
MAGNITUDE OF LOAD CURRENT (mA)

FREQUENCY (Hz)

FIGURE 23. EQUIVALENT NOISE VOLTAGE vs FREQUENCY

FIGURE 22. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q12) vs LOAD CURRENT

4000

-I

Vs =±7.5V

/

1000
7.5

I

<"

~

/

~

...

LJJ

C,?

Z
LJJ

~

II:
II:

~
~

0.
~

2.5

L

If

10
I

·1

__-L________________
2

3

4

5

6

1/

~

~

__
o

~

~

~

J

o

1

~

7

~

4

~

0

~

~

FIGURE 24. INPUT CURRENT vs COMMON MODE VOLTAGE

;:

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED

6

I

5

LJJ
C,?

4

~

3

~

2

~

V'

/'

IL
IL

/

o

o

I

TA = 125°C FOR
METAL CAN PACKAGES"""'"

U)

/
V"

I/.
o

00

l00l~l~

FIGURE 25. INPUT CURRENT vs TEMPERATURE

7

lti:

ro

TEMPERATURE (oC)

INPUT CURRENT (pA)

500

V
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3)
OUTPUT VOLTAGE = V+/2
1

= OV
1

1000 1500 2000 2500 3000 3500 4000
TIME (HOURS)

FIGURE 26. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE

3-113

a: a.
w~

:::>

...:::>0

0.
~

O!!:!
-II.

!;i::::i

g;«

I

100

«en
Za:

~';~"'-'1193,. CA3193A
1.2MHz, BiCMOS

____..... recision Operational Amplifiers
Description
LowVIO
- CA3193A .....••........•.....•... 200!!V (Max)
- CA3193 ......••........•......•.. 500!!V (Max)
• Low t..VloIt..T
- CA3193A ...............•........ 3!!vflc (Max)
- CA3193 ......•..........•••...•. 5!!vflC (Max)
• Low 110 and II
• Low t..lloIt..T: CA3193 .•.•.••....... 150pAflC (Max)
• Low t..ltlt..T: CA3193 ..•..........•.. 3.7nAflC (Max)

Applications
• Thermocouple Preamplifiers
• Strain Gauge Bridge Amplifiers
• Summing Amplifiers

The CA3193A and CA3193 are ultra-stable, precIsion
instrumentation, operational amplifiers that employ both
PMOS and bipolar transistors on a single monolithic chip.
The CA3193A and CA3193 amplifiers are internally phase
compensated and provide a gain bandwidth product of
1.2MHz. They are pin compatible with the industry 741
series and many other IC op amps, and may be used as
replacements for 741 series types in most applications.
The CA3193A and CA3193 can also be used as functional
replacements for op amp types 725, 108A, OP-5, OP-7,
LM11 and LM714 in many applications where nulling is not
employed. Because of their low offset voltage and low offset
voltage vs temperature coefficient the CA3193A and
CA3193 amplifiers have a wider range of applications than
most op amps and are particularly well suited for use as
thermocouple amplifiers, high gain filters, buffer, strain
gauge bridge amplifiers and precision voltage references.
The two types in the CA3193 series are functionally
identical. The CA3193A and CA3193 operate from supply
voltages of ±3.5V to ±18V.

• Differential Amplifiers
• Bilateral Current Sources

Ordering Information

• Log Amplifiers
• Differential Voltmeters

PART NUMBER

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

• Precision Voltage References

CA3193AE

-25 to 85

8 Ld PDIP

E8.3

• Active Filters

CA3193AT

-25 to 85

8 Pin Metal Can

T8.C

• Buffers

CA3193E

Ot070

8Ld PDIP

E8.3

CA3193T

Ot070

8 Pin Metal Can

T8.C

• Integrators
• Sample-and-Hold Circuits
• Low Frequency Filters

Pinouts
CA3193
(METAL CAN)
TOP VIEW

CA3193
(PDIP)
TOP VIEW

NC

OFFSET NULL

1

INV.INPUT

2

NON-INV. INPUT

3
5

OFFSET NULL

NOTE: Pin 4 is connected to case on Sand T suffix.

)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

3-114

File Number

1249.2

CA3240, CA3240A

HARRIS
SEMICONDUCTOR

Dual, 4.5MHz, BiMOS Operational Amplifier
with MOSFET Input/Bipolar Output

November 1996

Features

Description

• Dual Version of CA3140

The CA3240A and CA3240 are dual versions of the popular
CA3140 series integrated circuit operational amplifiers. They
combine the advantages of MOS and bipolar transistors on the
same monolithic Chip. The gate-protected MOSFET (PMOS)
input transistors provide high input impedance and a wide
common-mode input voltage range (typically to O.5V below the
negative supply rail). The bipolar output transistors allow a wide
output voltage swing and provide a high output current capability.

• Internally Compensated
• MOSFET Input Stage
- Very High Input Impedance (ZIN) 1.5TO (Typ)
- Very Low Input Current (II) 10pA Typ. at ±15V
- Wide Common-Mode Input Voltage Range (VICR):
Can Be Swung O.5V Below Negative Supply Voltage
Rail
• Directly Replaces Industry Type 741 in Most
Applications

Applications
Ground Referenced Single Amplifiers in Automobile
and Portable Instrumentation

The CA3240A and CA3240 are compatible with the industry
standard 1458 operational amplifiers in similar packages.The offset null feature is available only when these types are supplied in
the 14 lead PDIP package (E1 suffix).

Ordering Information

• Sample and Hold Amplifiers

PART NUMBER

• Long Duration Timers/Multivibrators (MicrosecondsMinutes-Hours)
• Photocurrent Instrumentation
• Intrusion Alarm System

• Active Filters

• Comparators

• Function Generators

• Instrumentation Amplifiers

• Power Supplies

Pinouts

TEMP.
RANGE (OC)

PKG.
NO.

PACKAGE

CA3240AE

·40 to 85

8 Ld PDIP

E8.3

CA3240AE1

·40 to 85

14 Ld PDIP

E14.3

CA3240E

·40 to 85

8 Ld PDIP

E8.3

CA3240E1

·40 to 85

14 Ld PDIP

E14.3

2mA

O U T P U T ( A ) O S v+
INV.
INPUT (A) 2
7 OUTPUT
NON·INV.
INPUT (A)
V
•

:~~UT (B)

3

6

4

5 NON-INV.
INPUT (B)

CA3240, CA3240A, (PDIP)
TOP VIEW
INV.
INPUT (A) 1
NON·INV.
INPUT (A)
OFFSET 3
NULL (A)
y. 4

OFFSET
4 NULL(A)

3

v+t
12pF

2 OUTPUT (A)

OFFSET 5
o OUTPUT(B)
NULL (B)
NON·INV.
9
v+t
INPUT(B) 6
OFFSET
INY. 7
I...-_ _...J S NULL (B)
INPUT (B)

V-

OFFSET NULL

NOTE: Only available with 14 lead DIP (E1 Suffix).

t Pins 9 and 13 internally connected through approximately 30.

CAUTION: These devices are sensitive to electroslatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

3-115

File Number

etC/)
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Functional Diagram
CA3240, CA3240A, (PDIP)
TOP VIEW

...J

1050.3

CA3240, CA3240A
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V-) ...•..•..........•... 36V
Differential Input Voltage........•....................... 8V
Input Voltage .....................•..•. (V+ +8V) to (V- -0.5V)
Input Current. .............•.......................•. 1mA
Output Short Circuit Duration (Note 1) ..............•• Indefinite

Thermal Resistance (Typical, Note 2)

8JA (oCIW)
8 Lead PDIP Package..... ... ....... ........
100
14 Lead PDIP Package ..... ,. ... .... ........
100
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range . • . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) .......••.... 300°C

Operating Conditions
Temperature Range ••....................•... -40°C to 85°C
Voltage Range ....••.• : ••..•••.••.. 4V to 36V or ±2V to ±18V

CAUTION: Stresses above those /lsted In "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within
maximum rating.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

For Equipment Design, VSUPPLY = ±15V, TA = 25°C, Unless Otherwise Specified
CA3240

PARAMETER

SYMBOL

Input Offset Voltage

VIO

Input Offset Current

110

Input Current

MIN

MAX

MIN

TYP

MAX

UNITS

5

15

-

2

5

mV

0.5

30

0.5

20

pA

10

SO

-

10

40

pA

20

100

-

20

100

-

kVN

86

100

-

II

Large-Signal Voltage Gain
(See Figures 13, 28) (Note 3)
Common Mode Rejection
Ratio (See Figure 18)
Common Mode Input Voltage
Range (See Figure 25)
Power Supply Rejection Ratio
(See Figure 20)

AoL

CA3240A

TYP

86

100

32

320

-

32

320

IlVN

70

90

-

70

90

-

dB

-15

-15.5 to
+12.5

11

-15

-15.Sto
+12.5

12

V

PSRR

-

100

150

-

100

150

IlVN

(/!NldIlV±)

76

80

-

76

80

-

dB

CMRR

VieR

dB

Maximum Output Voltage (Note 4)
(See Figures 24, 25)

, VOM+

12

13

12

13

VOM-

-14

-14.4

-14

-14.4

Maximum Output Voltage (Note 5)

VOM-

0.4

0.13

0.4

0.13

-

V

Total Supply Current
(See Figure 16) For Both Amps

1+

-

8

12

-

8

12

rnA

Total Device Dissipation

Po

-

240

360

-

240

360

mW

V
V

NOTES:
3. At Vo

=26Vp_p, +12V, -14V and RL =2kO.

4. At RL = 2ill.
5. At V+

=5V, V- =GND, ISINK =200JlA.

Electrical Specifications

For Equipment Design, VSUPPLY

=±15V, TA =25°C, Unless Otherwise Specified
TYPICAL VALUES

PARAMETER

SYMBOL

TEST CONDITIONS
Typical Value of Resistor Between Terminals 4 and
3(5) or Between 4 and 14(8) to Adjust Maximum VIO

Input Offset Voltage Adjustment Resistor
(E1 Package Only)

CA3240A CA3240 UNITS
18

4.7

ill

Input Resistance

RI

1.5"·

1.5

TO

Input Capacitance

CI

4

4

pF

Output Resistance

Ro

60

60

n

Equivalent Wideband Input Noise Voltage
(See Figure 2)

eN

48

48

IlV

BW = 140kHz, Rs = 1MO

3-116

CA3240, CA3240A
Electrical Specifications

For Equipment Design, VSUPPLY = ±15V, TA = 25°C, Unless Otherwise Specified
TYPICAL VALUES

PARAMETER

SYMBOL

Equivalent Input Noise Voltage
(See Rgure 19)

CA3240A CA3240 UNITS

f = 1kHz, Rs = 100n

40

40

nV"/Hz

f = 10kHz, Rs = 100n

12

12

nVl.JHz

IOM+

Source

40

40

mA

10M-

Sink

11

11

mA

4.5

4.5

MHz

eN

Short-Circuit Current to Opposite Supply

TEST CONDITIONS

Gain Bandwidth Product (See Figures 14, 28)

fT

Slew Rate (See Figure 15)

SR

Transient Response (See Figure 1)

Settling Time at 10 VP_P (See Figure 26)

9

9

V/Jls

tr

RL = 2kn, CL = 100pF

Rise Time

0.08

0.08

Jls

OS

RL = 2kn, CL = 100pF

Overshoot

10

10

%

ts

Av = +1, RL = 2kn, CL = 100pF,
Voltage Follower

To 1mV

4.5

4.5

Jls

Crosstalk (See Figure 23)

To 10mV

f= 1kHz

Electrical Specifications

1.4

1.4

Jls

120

120

dB

For Equipment Design, at VSUPPLY = ±15V, TA = -40 to 85°C, Unless Otherwise Specified
TYPICAL VALUES

PARAMETER

SYMBOL

CA3240A

CA3240

UNITS

Input Offset Voltage

IVlol

3

10

mV

Input Offset Current (Note 8)

11101

32

32

pA

II

640

640

pA

AoL

63

63

kVN

96

96

dB

CMRR

32

32

JlVN

90

90

dB

Common Mode Input Voltage Range (See Figure 25)

VieR

-15 to +12.3

-15 to +12.3

V

Power Supply Rejection Ratio (See Figure 20)

PSRR

150

150

JlVN
dB

Input Current (Note 8)
Large Signal Voltage Gain (See Figures 13, 28), (Note 6)

Common Mode Rejection Ratio (See Figure 18)

"

(tNloIAV±)

76

76

VOM+

12.4

12.4

V

VOM-

-14.2

-14.2

V

Maximum Output Voltage (Note 7) (See Figures 24, 25)

Supply Current (See Figure 16) Total For Both Amps

1+

8.4

8.4

mA

Total Device Dissipation

PD

252

252

mW

AVloIAT

15

15

JlVfOC

Temperature Coefficient of Input Offset Voltage
NOTES:
6. AtVo = 26Vp_p, +12V, -14V and RL = 2kn.
7. At RL = 2kn.

8. At TA = 85°C.

Electrical Specifications

For Equipment Design, at V+ = 5V, V- = OV, TA = 25°C, Unless Otherwise Specified
TYPICAL VALUES

PARAMETER

SYMBOL

CA3240A

CA3240

UNITS

Input Offset Voltage

IVIOI

2

5

mV

Input Offset Current

"10 1

0.1

0.1

pA

II

2

2

pA

Input Current
Input Resistance

RIN

1

1

Tn

Large Signal Voltage Gain (See Figures 13, 28)

AoL

100

100

kVN

100

100

dB

3-117

CA3240, CA3240A
Electrical Specifications

For Equipment Design, at v+ = 5V, V- = OV, TA = 25°C, Unless Otherwise Specified (Continued)
TYPICAL VALUES

PARAMETER
Common-Mode Rejection Ratio

SYMBOL

CA3240A

CA3240

UNITS

CMRR

32

32

IlVN

90

90

dB

-0.5

-0.5

V

2.6

2.6

V

31.6

31.6

IlVN
dB

Common-Mode Input Voltage Range (See Figure 25)

VieR

Power Supply Rejection Ratio

PSRR

90

90

Maximum Output Voltage (See Figures 24, 25)

VOM+

3

3

V

VOM-

0.3

0.3

V
mA

I

Source

IOM+

20

20

J

Sink

IOM-

1

1

mA

Slew Rate (See Figure 15)

SR

7

7

V/IJ.S

Gain Bandwidth Product (See Figure 14)

fT

4.5

4.5

MHz

Supply Current (See Figure 16)

1+

4

4

rnA

Device Dissipation

Po

20

20

mW

Maximum Output Current

Test Circuits and Waveforms

5OmVlDiv., 200nslDiv.
Top Trace: Input, Bottom Trace: Output

5VlDiv.,1IlslDiv.
Top Trace: Input, Bottom Trace: Output

FIGURE 1A. SMALL SIGNAL RESPONSE

FIGURE 1B. LARGE SIGNAL RESPONSE

SIMULATED
LOAD

>-. -,

100pF

+.....~

2kQ

-:.!,.-

BW (-3dB) = 4.SMHz
SR= 9Y/Jill
O.OSI'F
FIGURE 1C. TEST CIRCUIT
FIGURE 1. SPLlT·SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS

3-118

CA3240, CA3240A
Test Circuits and Waveforms

(Continued)

NOISE
VOLTAGE
OUTPUT

BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 48~V (TYP)
FIGURE 2. TEST CIRCUIT AMPLIFIER (3DdB GAIN) USED FOR WIDE BAND NOISE MEASUREMENT

Schematic Diagram (One Amplifier of Two)
..J



L

,

100

CJ

5II.
~

,

10

"

,/

,/
-60

Input Circuit Considerations

-40

-20

~
0

20

40

60

80

100

120 140

TEMPERATURE <"C)

As indicated by the typical VICR, this device will accept
inputs as low as 0.5V below V-. However, a series currentlimiting resistor is recommended to limit the maximum input
terminal current to less than 1mA to prevent damage to the
input protection circuitry.
Moreover, some current-limiting resistance should be provided between the inverting input and the output when the

FIGURE 4. INPUT CURRENT vs TEMPERATURE

It is well known that MOSFET devices can exhibit slight
,changes in characteristics (for example, small changes in
input offset voltage) due to the application of large differential input voltages that are sustained over long periods at
elevated temperatures.

3-120

CA3240, CA3240A
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts
of the opposite polarity reverse the offset. In typical linear
applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same
magnitude as those encountered in an operational amplifier
employing a bipolar transistor input stage.
Offset-Voltage Nulling
The input offset voltage of the CA3240AE1 and CA3240E1
can be nulled by connecting a 10kQ potentiometer between
Terminals 3 and 14 or Sand 8 and returning its wiper arm to
Terminal 4, see Figure SA. This technique, however, gives
more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized.
Typical values of series resistors that may be placed at either
end of the potentiometer, see Figure SB, to optimize its utilization range are given in the table "Electrical Specifications for
Equipment Design" shown on third page of this data sheetAn
alternate system is shown in Figure SC. This circuit uses only
one additional resistor of approximately the value shown in
the table. For potentiometers, in which the resistance does not
drop to OQ at either end of rotation, a value of resistance 10%
lower than the values shown in the table should be used.

Typical Applications
On/Off Touch Switch
The onloff touch switch shown in Figure 6 uses the
CA3240E to sense small currents flowing between two contact points on a touch plate consisting of a PC board metalli-

zation "grid". When the "on" plate is touched, current flows
between the two halves of the grid causing a positive shift in
the output voltage (Terminal 7) of the CA3240E. These positive transitions are fed into the CA30S9, which is used as a
latching circuit and zero-crossing TRIAC driver. When a positive pulse occurs at Terminal 7 of the CA3240E, the TRIAC
is turned on and held on by the CA30S9 and its associated
positive feedback circuitry (S1kfl resistor and 36kQ/42kfl
voltage divider). When the positive pulse occurs at Terminal
1 (CA3240E), the TRIAC is turned off and held off in a similar manner. Note that power for the CA3240E is supplied by
the CA30S9 internal power supply.
The advantage of using the CA3240E in this circuit is that it
can sense the small currents associated with skin conduction while allowing sufficiently high circuit impedance to provide protection against electrical shock.
Dual Level Detector (Window Comparator)
Figure 7 illustrates a simple dual liquid level detector using
the CA3240E as the sensing amplifier. This circuit operates
on the principle that most liquids contain enough ions in
solution to sustain a small amount of current flow between
two electrodes submersed in the liquid. The current, induced
by an O.SV potential applied between two halves of a PC
board grid, is converted to a voltage level by the CA3240E in
a circuit similar to that of the onloff touch switch shown in
Figure 6. The changes in voltage for both the upper and
lower level sensors are processed by the CA3140 to activate
an LED whenever the liquid level is above the upper sensor
or below the lower sensor..

1(7)
12(10)
2(6)

v-

v-

FIGURE SA. BASIC

FIGURE 5B. IMPROVED RESOLUTION

R
FIGURE 5C. SIMPLER IMPROVED RESOLUTION
NOTE:
11. See Electrical Specification Table on Third page of this data sheet for value of R.
FIGURE 5. THREE OFFSET-VOLTAGE NULLING METHODS, (CA3240AE1, CA3240E1 ONLY)

3-121

~

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CA3240, CA3240A
44M

10K(2W)
120V1220V
AC
60Hz/50Hz

+6V

T2300B (NOTE 10)

COMMON
1N914
+6VSOURCE

44M

NOTE:
12.

At 220V operation, TRIAC should be T2300D, Rs

~

18K, 5W.

FIGURE 6. ON/OFF TOUCH SWITCH
12M
+15V

LED

LED ON WHEN
LIQUID OUTSIDE
OF LIMITS
.LOW
LEVEL

12M

FIGURE 7. DUAL LEVEL DETECTER

Constant-VoltagelConstant-Current Power Supply

Precision Differential Amplifier

The constant-voltage/constant-current power supply show~
in Figure 8 uses the CA3240E1 as a vOltage-error and current-sensing amplifier. The CA3240E1 is ideal for this application because its input common-mode voltage range
includes ground, allowing the supply to adjust from 20mV to
25V without requiring a negative supply voltage. Also, the
ground reference capability of the CA3240E1 allows it to
sense the voltage across the 1n current-sensing resistor in
the negative output lead of the power supply. The CA3086
transistor array functions as a reference for both constantvoltage and constant-current limiting. The 2N6385 power
Darlington is used as the pass element and may be required
to dissipate as much as 40W. Figure 9 shows the transient
response of the supply during a 1OOmA to 1A load transition.

Figure 10 shows the CA3240E in the classical precision differential amplifier circuit. The CA3240E is ideally suited for
biomedical applications because of its extremely high input
impedance. To insure patient safety, an extremely high electrode series resistance is required to limit any current that
might result in patient discomfort in the event of a fault condition. In this case, 10Mn resistors have been used to limit the
current to less than 2~ without affecting the performance of
the circuit. Figure 11 shows a typical electrocardiogram
waveform obtained with this circuit.

3-122

CA3240, CA3240A
~------------------------------------------~~Vo

2N6385
DARLINGTON

---------..
V+

..

10-10K

180K

+ 500
- ~F

_________ • 10011
lN914
lOOK

0.OS6~F

82K

CA3086E
TRANSISTOR
ARRAY

680K
SOK

--'
«CIl
ZCC

Ow
-ii:

~:J

CCQ..

w:!:

-!-

lOOK

CHASSIS GROUND
Vo RANGE = 20mV TO 2SV
LOAD REGULATION:
VOLTAGE <0.08%
CURRENT <0.05%

111
lW

OUTPUT HUM AND NOISE,; 150~VRMS
(10MHz BANDWIDTH)
SINE REGULATION" 0.1%IV0
10 RANGE = 10mA-l.3A

FIGURE 8. CONSTANT-VOLTAGEICONSTANT-CURRENT POWER SUPPLY

Top Trace:

Output Voltage;
50OmVlDiv., 5JlS/Div.

Bottom Trace: Collector Of Load Switching Transistor
Load =100mA to 1A; 5VlDiv., 5JlS1Div.

FIGURE 9. TRANSIENT RESPONSE

3-123

~«

CA3240, CA3240A

100Kl%
10M

GAIN
CONTROL

"

~,

~
TWOCOND.
SHIELDED
CABLE
FREQUENCY RESPONSE (-3dB) DC TO 1MHz
SLEW RATE = 1.5V1lls
COMMON MODE REJ: 86dB
GAIN RANGE: 35dB TO 60dB

10M

-15V

FI~URE

10. PRECISION DIFFERENTIAL AMPLIFIER

Vertical: 1.0mVlDiv.
AmplHier Gain = 100X
Scope Sensitivity = 0.1 VlDiv.
Horizontal: >O.2slDiv. (Uncal) ,
FIGURE 11. TYPICAL ELECTROCARIOGRAM WAVEFORM

Differential Light Detector
In the circuit shown in Figure 12, the CA3240E converts the
current from two photo diodes to voltage, and applies 1V of
reverse bias to the diodes. The voltages from the CA3240E
outputs are subtracted in the second stage (CA3140) so that
only the difference is amplified. In this manner, the circuit
can be used over a wide range of ambient light conditions
without circuit component adjustment. Also, when used with
a light source, the circuit will not be sensitive to changes in
light level as the source ages.

3-124

CA3240, CA3240A
0.015~F

C30809

PHOTO
OUTPUT

DIODE

C30809

PHOTO
DIODE
0.015~F

FIGURE 12. DIFFERENTIAL LIGHT DETECTOR
..J
c(lI)

Typical Performance Curves

Za:

RL = 2kil

"N
:t: 20

iii
:!!.

~

t;

~

~

Q

"~

100

0

75

Z

50

9
w

5!a..

TA =-40oC

TA _-40°C

:t:

b

25~

I

..-.;::

~

85°C

25°C

85°C

Z
C

III

Z

a..

0

W:E
~c(

10

::I

w 125

~
a..

o!:!:!
-u..
~::i
a: a..

RL = 2kil
CL = 100pF

;(

25

"
o

5

10
15
SUPPLY VOLTAGE (V)

20

FIGURE 13. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE
20

o

25

10
15
SUPPLY VOLTAGE (V)

5

10

IZI/I

TA _ -40oC

.-

~ a..

7

L

o;Z:

6

"'

::10
0 ...

!!i~
~6

... 111

a.. a:

85°C

...I

~

10
15
SUPPLY VOLTAGE (V)

20

FIGURE 15. SLEW RATE VB SUPPLY VOLTAGE

25

t=looc

8

/~

/~~

~
25°C

~

~C

/ ~

5

~

4
3
2

5

,
~

RL=OO
9

25jC _

25

FIGURE 14. GAIN BANDWIDTH PRODUCT VB SUPPLY VOLTAGE

RL = 2kil
CL = l00pF

15

20

o

5

10

15

20

25

SUPPLY VOLTAGE (V)

FIGURE 16. QUIESCENT SUPPLY CURRENT va SUPPLY VOLTAGE

3-125

CA3240, CA3240A

Typical Performance Curves

(Continued)

SUPPLY VOLTAGE: Vs = ±15V
TA = 25°C
25

rL

20

fi
g

15

w

!j

0

~

1\

~

~

r\\

0

z

80

~

60

w
Q
0
::Ii

40

~~

I"

~

..........

a::

,

...........

z

I""'i"o
0
10K

SUPPLY VOLTAGE: Vs = ±15V
TA = 25°C
100

~w

\

10

~

120

a::

I-

;:)

iii'
:!!.

100K

0
::Ii
::Ii

r---..

1M

20

~

0
0

FIGURE 18. COMMON MODE REJECTION RATIO vs
FREQUENCY,

iii'
:!!.

SUPPLY VOLTAGE: Vs = +15V
TA = 25°C

0

I

~z

RS= 1000

SUPPLY VOLTAGE: Vs = ±1SV
TA = 25°C

~

.... +PSRR
I.....

60

~

.....

·PSRR

a::

~

~

r-...

w

20

~

1

1\

10

\

ffi

4

o

,2

·10

~

a::m

J

/

o

\

Ww
a:: ...

;:);:)

08
~~

10

a.::Ii

7.5

0.0.

::'oe

Vs =±15V
RL=oo

\

15

!;;li! 12.5

j

~

TA = 25°C

~a::

/

"I"
·15

Em

If

~

o

C(~

L

ONE AMPLIFIER OPERATING

6

~

I

1\

Goe

l.!! iii
1ija.

I

,

~!1i 8

FIGURE 20. POWER SUPPLY REJECTION RATIO vs
FREQUENCY

17.5

I

10S

FREQUENCY (Hz)

t
I

104

103

103

FIGURE 19. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY

I

~

.....

FREQUENCY (Hz)

Vsl=±115V

"

40

rn
a::

1"'1

I

1111

....

80

::.

TA=2S0C

I II

REJECTION RATIO = IN,oIl!.vS

a.
a.'

12

I II

POW~R ~~~PL~ I I II I I I

100

~
w

...... ....

102

105

FREQUENCY (Hz)

FIGURE 17. MAXIMUM OUTPUT VOLTAGE SWING vs
FREQUENCY

~

104

103

4M

FREQUENCY (Hz)

\

"

rna::

w

I

a.

5

\..

.....

2.5

5

10

15

·15

OUTPUT VOLTAGE (V)

·10

·5

0

5

10

15

OUTPUT VOLTAGE (V)

FIGURE 21. OUTPUT SINK CURRENT VB OUTPUT VOLTAGE

FIGURE 22. SUPPLY CURRENT VB OUTPUT VOLTAGE

3·126

CA3240, CA3240A
Typical Performance Curves

(Continued)

1000

iD
~
~

TA = 25°C
c- AMPA .... AMPB
AMPB .... AMPA
Vs = ±15V

140

-

130

--. ~~O=5VRMS

120

[""0.

..J

~

'"'"5!
0

110

V-=OV
TA -25°C

V+=+5V

100

,

~

~

..... ....

100

-

V

10

....

1.0
0.01

101

~

~

0

I I

60!:

;: iii!
i~

-1

W~ 1.5

I

~ ffi

11.1-

!;o
01-

0.5

-2

§! fa

-0.5

-2.5

!; II!

-1.0

~~

R1.S

-3

TA=2(OC

I
0

I
5

,

/

TA
I

=-4Q°C

TA

+lOV

10

II.W

=_40oC

I

10
15
SUPPLY VOLTAGE (V)

20

25

FIGURE 25A.

oJ

«en
Za:

I

I

O!!:!
-IL.

!;t::i

COMMON MODE VOLTAGE (+VICR)

I

I

I

a:

a..
W:E

. . .. . . -. ..

~«

TA = -40oC TO 85°C
TA = 85°C

W

<~

I I

0

.-,

~

""..

'"

lmV~

#

lDmV,

6

I

6

..

100pF

FOLLOWER
• ••• INVERTING

+~

2kil

•••

~

lm:~~V- f-

~omv

....

~
4

8 1.0

6

0.05~F

8 10

'TIME(~s)

FIGURE 26A. SETTLING TIME vs INPUT VOLTAGE

FIGURE 26B. TEST CIRCUIT (FOLLOWER)
5kil

SIMULATED
LOAD

>.-.

100pF

+~

2kil

'.'

5.11ka

FIGURE 26C. TEST CIRCUIT (INVERTING)
FIGURE 26. INPUT VOLTAGE vs SETTLING TIME
10K

~

/

i

lK

II:
II:

100

Vs =±15V
TA=25oC

i= Vs =±15V
~
CI

z~
W

w

~

80

!j

~

!l
II.

§

40

II.

20

!:

1111

·75

I

·90
·105

RL=2kO,
CL=loopF

·150

1
-60

,

/

§

zW

0

~
-40

·20

0

20

40

80

80

100

120

o

101

140

TEMPERATURE (oC)

FIGURE 27. INPUT CURRENT vs TEMPERATURE

zw

1"1

102

103

104

105

FREQUENCY (Hz)

~
106

"

107

108

FIGURE 28. OPEN LOOP VOLTAGE GAIN AND PHASE V5
FREQUENCY

3·128

W-

i

GAIN

II.

10

i3

II!CI
·135 l!l
·120

U l

"

60

:::I
U

II

RL =2kil
II~JA!! ~ ~L=OpF

100

~

/

III

CA3260, CA3260A

HARRIS
SEMICONDUCTOR

4MHz, SiMOS Operational Amplifier
with MOSFET Input/CMOS Output

November 1996

Features

Description

• MOSFET Input Stage provides
• Very High ZI 1.STO (1.S x 10120) (Typ)
• Very Low II = SpA (Typ) at 1SV Operation
= 2pA (Typ) at SV Operation

CA3260A and CA3260 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA3260 series
circuits are dual versions of the popular CA3160 series.

• Ideal for Single Supply Applications

Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common mode input voltage capability
down to O.SV below the negative supply terminal, an
important attribute in single supply applications.

=

• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be Swung
O.SV Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(Or Both) Supply Rails

A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.

Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers

The CA3260 Series circuits operate at supply voltages
ranging from 4V to 16V, or ±2.V to ±8V when using split
supplies. The CA3260A offers superior input characteristics
over those of the CA3260.

• Long Duration TimersiMonostables
• Ideal Interface with Digital CMOS
• High Input Impedance Wideband Amplifiers

Ordering Information

• Voltage Followers (e.g. Follower for Single Supply D/A
Converter)

PART NUMBER

TEMP.
RANGE (DC)

PKG.
NO.

PACKAGE

• Voltage Regulators (Permits Control of Output Voltage
Down to OV)

CA3260E

-5510125

B Ld PDIP

EB.3

CA3260T

-5510125

B Pin Metal Can

TB.C

• Wien Bridge Oscillators

CA3260AE

-5510125

B Ld PDIP

EB.3

• Voltage Controlled Oscillators

CA3260AT

-5510125

B Pin Metal Can

TB.C

• Photo Diode Sensor Amplifiers

Pinouts

CA3260, CA3260A (PDIP)
TOP VIEW

CA3260, CA3260A (METAL CAN)
TOP VIEW
V+

OUTPUT (A)

1

INV. INPUT (A)

2

7

OUTPUT (B)

NON INV. INPUT (A)

3

6

INV. INPUT (B)

5

NON INV. INPUT (B)

tNV. 2

6

INPUT (A)

tNV.
INPUT (B)

V-

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

3-129

File Number

1266.3

...I
C(I/)

zo::

O!!!
-1.1.

!;;::::i
0::0..

W:::a:
~C(

CA3260, CA3260A
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage (V+ to V-) ........................... 16V
DC lilput Voltage ...................... (V+ +BV) to (V- -0.5V)
Differential Input Voltage .............•.................. BV
InputTermirialCurrent ................................ 1mA
Output Short Circuit Duration (Note 1) ................ Indefinite

Thermal Resistance (Typical, Note 2)
8JA (oC/W) 8JC fc/W)
PDIP Package. ..................
100
N/A
Metal Can Package. . . . . . . . . . . . . . .
165
75
Maximum Junction Temperature (Metal Can Package) ....... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ......... '.... 300°C

Operating Conditions
Temperature Range ........................ -55°C to 125°C

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

TA = 25°C, Typical Values Intended Only for Design Guidance
TYPICAL VALUES

PARAMETER

SYMBOL

TEST CONDITIONS

CA3260A

CA3260

UNITS
TO

Input Resistance

RI

Vs=±7·5V

1.5

1.5

Input Capacitance

CI

f = 1MHz, Vs =±7.5V

4.3

4.3

pF

Unity Gain Crossover Frequency

tr

Vs=±7.5V

4

4

MHz

Slew Rate

SR

Vs=±7.5V

10

10

V/IJS

CL = 25pF, RL = 2kQ,Av = +1,
VS=±7.5V

0.09

0.09

~s

10

10

%

Ct. = 25pF, RL = 2kQ, Av= +1,

1.8

1.B

~s

Transient Response

I

Rise Time

tr

I

Overshoot

OS

Settling Time (to <0.1 %, VIN = 4Vp_p)

ts

VS=±7.5V
Input Offset Voltage

VIO

V+ =5V, V- = OV

2

6

mV

Input Offset Current

110

V+ = 5V, V- = OV

0.1

0.1

pA

II

V+ = 5V, V- = OV

2

2

pA

CMRR

V+ = 5V, V- = OV

70

60

dB

Va = 4Vp_p, RL = 20kQ,
V+ = 5V, V- = OV

100

100

kVN

100

100

dB

Ot02.5

Ot02.5

V

1

1

mA

1.2

1.2

mA

200

200

~VN

Input Current
Common Mode Rejection Ratio
Large Signal Voltage Gain

AoL

Common Mode Input Voltage Range

VICR

Supply Current

1+

V+=5V, V-=OV
Va =5V, RL =~, V+= 5V, V-= OV
Va = 2.5V,

Power Supply Rejection Ratio

Electrical Specifications
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Large Signal Voltage Gain

Common Mode Rejection Ratio

PSRR

RL=~,

V+=5V, V-=OV

IlVld/!N+, V+ = 5V, V- = OV

For Each Amplifier at TA = 25°C, V+ = 15V, V- = OV, Unless Otherwise Specified

SYMBOL

TEST
CONDITIONS

CA3260A
MIN

CA3260

TYP

MAX

IVIOI

Vs =±7.5V

2

5

11101

Vs =±7.5V

0.5

20

II

Vs =±7.5V

30

AoL

CMRR

Vo= 10Vp_p,
RL= 10kQ

-

5

50

320

94

110

80

95

3·130

-

MIN

TYP

MAX

UNITS

6

15

mV

0.5

30

pA

5

50

50

320

94

110

70

90

-

pA
kVN
dB
dB

CA3260, CA3260A
Electrical Specifications
PARAMETER

For Each Amplifier at TA = 25°C. V+ = 15V. V- = OV. Unless Otherwise Specified (Continued)

SYMBOL

Common Mode Input Voltage
Range

VieR

Power Supply Rejection Ratio

PSRR

CA3260A

TEST
CONDITIONS

CA3260

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

0

-0.5 to
12

10

0

-0.5 to
12

10

V

-

32

150

32

320

IlVN

11

13.3

11

13.3

-

V

INloIIN+
V+=17.5V

Maximum Output Voltage
VOM+

RL = 10kQ

0.002

VOMVOM+

RL=

14.99

00

VOMMaximum Output Current

0.01

15

-

0.002

0.Q1

V

14.99

15

-

V
V

0

0.01

-

0

0.01

Va = 7.5V
IOM+Source

12

22

45

12

22

45

mA

IOM- Sink

12

20

45

12

20

45

mA

Vo (Amplifier A) = 7.5V
Va (Amplifier B) = 7.5V

-

9

15.5

9

15.5

mA

Vo (Amplifier A) = OV
Vo (Amplifier B) = OV

-

1.2

3

1.2

3

mA

5

8.5

5

8.5

mA

Total Supply Current

1+

RL =

00

..J

ov

Va (Amplifier A) =
Va (Amplifier B) = 7.5V

-

"
!.

1

1600

w
CI 1400

I

~

§1

1200

Ul

:$ 1000
III
II:

II!
!!:

......
::;;

,-

Vg=V'0=V'2=OV -

<

10.2
·75

·50

·25

0

25

50

75

100

125

150 175

TEMPERATURE ("C)

FIGURE 17. LEAKAGE CURRENT vs TEMPERATURE

AMPLIFIER BIAS CURRENT (1lA)

FIGURE 18. AMPLIFIER BIAS VOLTAGE VB AMPLIFIER BIAS
CURRENT

3·138

CA3280, CA3280A
Typical Performance Curves

(Continued)

24
22

If>:

20

.s

16

w

~

14

!:i

12

g

18

8

Z

6

'"5
,

~

Vs =+ISV

IZ

""

.......

w
II:
II:
::>

...::>

I-

::>
0

.:;'

....

~

101

104

103

VB

FIGURE 20. PEAK OUTPUT CURRENT VB AMPLIFIER BIAS
CURRENT

FREQUENCY

TA - +25oC
VS= +ISV

......
~ 105

9-

.....

w
Z

....I

<(J)

105

106

;!

102

AMPLIFIER BIAS CURRENT (IlA)

FREQUENCY (Hz)

FIGURE 19. 1ff NOISE

~

J:-TA = 125°C
TA --55°C
TA _25°C

~~

...

102

~.

101

«
w

4

--.

g

~

102

0
I-

... IABC=SOO~

2

0

TA =-5SoC
TA = 25°C
TA = 125°C -

~

I'-

10

w

103

TA =2SoC

104

Qiii' 104

~~ ~ -S~O~I

<~

TA _25°C
TA = 125°C

II:E

~~

.....

oz

u.e
oi:>

'"w

iii

ZQ

103

W
Q

~8

.....

0

~'"

AMPLIFIER BIAS CURRENT (~)

DIODE CURRENT (IlA)

Vs

VB

~<

~

101

FIGURE 22. AMPLIFIER GAIN

DIODE CURRENT

+I5V

VB

AMPLIFIER BIAS CURRENT

VS=+I5V

....-!:

~.,

~

~

~

I-- r- TA = 125°C~....

~

10-1
10-1

~~ TA = 25°C

~

'TA = -55°C. 25°C

P'" ~TA=-550C
I

1

1~

III

I

101

1~

~

TA = 125°C

1~

~

102

AMPLIFIER BIAS CURRENT (~)

AMPLIFIER BIAS CURRENT (IlA)

FIGURE 23. SUPPLY CURRENT VB AMPLIFIER BIAS CURRENT

FIGURE 24. INPUT BIAS CURRENT
CURRENT

3-139

VB

Za:
o!!!
-II..
~:::i
a: 0..
W:!E

"'~

is 102

FIGURE 21. DIODE RESISTANCE

~

102

!2z

3
II: 10

~:

F

AMPLIFIER BIAS

CA3280, CA3280A
Metallization Mask Layout

Dimensions in parentheses are in millimeters and derived from
the basic inch dimensions as indicated. Grid graduations are in
mils (10- 3 inch).
The photographs and dimensions represent a chip when it Is
part of the wafer. When the wafer is cut into chips, the cleavage
angles are 5~ instead of 900 with respect to the face of the
chip. Therefore, the isolated chip is actually 7 mils (0.17mm)
larger in both dimensions.
.

3-140

~J~~kfJt~~20, CA3420A

~I
\

r-

.

.

liV[O!f\N2.(;;'·'!.!1,;,{dl;)~M~~, Low Supply Voltage, Low Input

'.'

~0~fI,b~\-~'9W::H"·:::~,, __,.. ~.,,~w,-_~~t BiMOS Operational Amplifiers
t~Fea;u;';~* r.~

''''''/iI,U-ril.j;/iI·...,.,».. ·,'ii«'

Description

• 2V Supply at 300llA Supply Current
• 1pA Input Current (Typ) (Essentially Constant to 85°C)
• Rail-to-Rail Output Swing (Drive ±2mA into 1kn Load)
• Pin Compatible with 741 Operational Amplifiers

Applications
• pH Probe Amplifiers
• Picoammeters
• Electrometer (High Z) Instruments
• Portable Equipment
• Inaccessible Field Equipment
• Battery-Dependent Equipment (Medical and Military)

Ordering Information
TEMP.
RANGE('lC)

PART NUMBER

PACKAGE

PKG.
NO.

CA3420AE

-55 to 125

B Ld PDIP

EB.3
TB.C

CA3420AT

-55 to 125

B Pin Metal Can

CA3420E

-55 to 125

B Ld PDIP

EB.3

CA3420T

-55 to 125

B Pin Metal Can

TB.C

Pinouts

The CA3420A andCA3420 are integrated circuit operational
amplifiers that combine PMOS transistors and bipolar
transistors on a single monolithic chip. The CA3420A and
CA3420 BiMOS operational amplifiers feature gate
protected PMOS transistors in the input circuit to provide
very high input impedance, very low input currents (less than
1pA). The internal bootstrapping network features a unique
guard banding technique for reducing the doubling of leakage
current for every 10°C increase in temperature. The CA3420
series operates at total supply voltages from 2V to 20V
either single or dual supply. These operational amplifiers are
internally phase compensated to achieve stable operation in
the unity gain follower configuration. Additionally, they have
access terminals for a supplementary external capacitor if
additional frequency roll-off is desired. Terminals are also
provided for use in applications requiring input offset voltage
nUlling. The use of PMOS in the input stage results in
common mode input voltage capability down to 0.45V below
the negative supply terminal, an important attribute for Single
supply application. The output stage uses a feedback OTA
type amplifier that can swing essentially from rail-to-rail. The
output driving current of 1.5mA (Min) is provided by using
nonlinear current mirrors.

Functional Diagram
CA3420 (PDIP)
TOP VIEW

OFFSET NULL 1
INV.
INPUT
NON-INV. 3
INPUT
5 OFFSET NULL

CA3420 (METAL CAN)
TOP VIEW

e

TAB ,STROBE

OFFSET NULL

IN~Ji

2

8

;

NON-INV. 3
INPUT

v+
6

BUFFER AMPS;
BOOTSTRAPPED
INPUT PROTEcnON
NETWORK

HIGH GAIN

OTABUFFER

(50K)

(X2)

OUTPUT

OFFSET NULL

v-

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-141

File Number

1320.3

...J

4OdB at f
• Power Bandwidth of 10MHz ••... ACL

=5MHz

=5; Vo =±3.5V

• Slew Rate at Full Load ..•.••...... 330Vll!s (Av ~ 10)

=

=

OpF With a Load of 50'1 1120pFII
• fT 220MHz; Cc
1M'1 (Scope Input)
• VOUT =±4.1V Into 75'1
• Offset Null Terminals

The CA34S0 (see Note) is a large signal video line driver
and high speed operational amplifier capable of driving SO'1
transmission lines and flash AIDs. The uncompensated unity
gain crossing occurs at 230MHz without load. It can operate
at dual or single supplies of ±7.2SV or 14.SV, respectively.
The CA34S0 can be compensated with a single capacitor
network. It has output drive capability of 7SmA SINK or
SOURCE. The CA34S0 is capable of driving Flash AIDs in
video or high speed instrumentation (accurate) applications
with bandwidth up to 10MHz. Offset voltage nulling terminals
are also available.
NOTE: Formerly Developmental Type No. TA11371A.

Applications

Ordering Information

• Video Line Driver
• High Frequency Unity Gain Buffer

PART NUMBER

TEMP.
RANGE ("C)

PKG.
NO.

PACKAGE

• Pulse Amplifier
CA3450E

• High Speed Comparator

-401085

16Ld PDIP

E16.3

~<

• Driver for AIDs in Video Applications ..... 10MHz BW

Block Diagram
CA3450
(PDIP)
TOP VIEW

INPUT CURRENT
COMPENSATED
DIFFERENTIAL
AMPLIFIER

1
6
'-v--"

9 11
'-v--"

OFFSET
NULL

PHASE

3·143

V-

COMP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

~::::i
a: a..
W~

• High Frequency Oscillator and Video Amplifiers

Pinout

..J

ij"I-lI--J-J"{-.>;;j-Yi1i'/HI'l-j-i!.fr!;;!J-/.'''f,;C;I!;-('(O

tif~eatu;;~#'~W"f'~"

Description

• MOSFET Input Stage
- Very High ZI ............ 1.5T12 (1.5 x 101212) (Typ)
- Very Low II ... , ......• 5pA (Typ) at 15V Operation
2pA (Typ) at 5V Operation
• Ideal for Single Supply Applications
• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be
Swung 0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
Both) Supply Rails
• CA5130A, CA5130 Have Full Military Temperature Range
Guaranteed Specifications for V+ 5V

=

• CA5130A, CA5130 Are Guaranteed to Operate Down to
V+ = 4.5V for AoL
• CA5130A, CA5130 Are Guaranteed to Operate at ±7.5V
CA3130A, CA3130 Specifications

Applications
•
•
•
•
•
•
•
•
•
•
•
•

Ground Referenced Single Supply Amplifiers
Fast Sample-Hold Amplifiers
Long Duration Timers/Monostables
High Input Impedance Comparators (Ideal Interface
with Digital CMOS)
High Input Impedance Wideband Amplifiers
Voltage Followers (e.g., Follower for Single-Supply
D/A Converter)
Voltage Regulators (Permits Control of Output Voltage
Down to OV)
Peak Detectors
Single Supply Full Wave Precision Rectifiers
Photo Diode Sensor Amplifiers
5V Logic Systems
Microprocessor Interface

CA5130A and CA5130 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip, They are designed
and guaranteed to operate in microprocessors or logic
systems that use +5V supplies,
Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common mode input voltage capability
down to O,SV below the negative supply terminal, an
important attribute in single supply applications,
A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuil.
The CAS130 Series circuits operate at supply voltages ranging
from 4V to 16V, or ±2V to ±8V when using split supplies, They
can be phase compensated with a single external capacitor,
and have terminals for adjustment of offset voltage for
applications requiring offset null capability, Terminal provisions
are also made to permit strobing of the output stage.
The CA5130A, CAS130 have guaranteed speCifications for
SV operation over the full military temperature range of
-SSoC to 12SOC.

Ordering Information
PART NUMBER
(BRAND)
CA5130AE
CA5130AM
(5130A)
CA5130AT
CA5130E
CA5130M
(5130)
CA5130T

TEMP.
RANGE (0C)
PACKAGE
-55 to 125 B Ld PDIP
-55 to 125 8 Ld SOIC

PKG.
NO.
EB,3
MB,15

-55 to 125
-55 to 125
-55 to 125

B Pin Metal Can
B Ld PDIP
B Ld SOIC

TB,C
EB,3
MB.15

-55 to 125

B Pin Metal Can

TB.C

Pinouts
CA5130 (PDIP, SOl C)
TOP VIEW
OFFSET NULL

1

INV.INPUT

2

NON-INV. INPUT

3

CA5130 (METAL CAN)
TOP VIEW
PHASE
TAB
COMPENSATION ~
____ '-'./--..
OFFSET NULL

INV.INPUT

1

2

5 OFFSET NULL

V-AND CASE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper
Copyright

© Harris Corporation 1996

3-144

Ie Handling Procedures.

File Number

1923.3

'iY";,;;;··,·,,,<;,
t Feat(icS& ,""

Description

• MOSFET Input Stage
- Very High ZI; 1.5TO (1.5 x 10120) (Typ)
- Very Low II; 5pA (Typ) at 15V Operation
2pA (Typ) at 5V Operation

CAS160A and CAS160 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CAS160 series
circuits are frequency compensated versions of the popular
CAS130 series. They are designed and guaranteed to operate
in microprocessor or logic systems that use +SV supplies.

• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be
Swung 0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails
• CA5160A, CA5160 Have Full Military Temperature
Range Guaranteed Specifications for V+ = 5V
• CA5160A, CA5160 Are Guaranteed to Operate Down
to 4.5V for AOL
• CA5160A, CA5160 Are Guaranteed Up to ±7.5V

Applications

Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input impedance,
very low input current, and exceptional speed performance.
The use of PMOS field effect transistors in the input stage
results in common-mode input voltage capability down to O.SV
below the negative supply terminal, an important attribute in
single supply applications.
A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CAS160 Series circuits operate at supply voltages ranging from +SV to + 16V, or ±2.SV to ±8V when using split supplies, and have terminals for adjustment of offset voltage for
applications requiring offset-null capability. Terminal provisions are also made to permit strobing of the output stage.
They have guaranteed specifications for SV operation over the
full military temperature range of -SSoC to 12SoC.

• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long Duration TimersiMonostables
• Ideal Interface With Digital CMOS
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)

Ordering Information
PART NUMBER
(BRAND)

• Wien-Bridge Oscillators

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

• Voltage Controlled Oscillators

CAS160AE

-55 to 125

8 Ld PDIP

E8.3

• Photo Diode Sensor Amplifiers

CA5160AM (5160A)

-55 to 125

8 LdSOIC

MB.15

CA5160M

• 5V Logic Systems
• Microprocessor Interface

-55 to 125

8 Ld SOIC

M8.15

CA5160E

(5160)

-55 to 125

B Ld PDIP

EB.3

CA5160T

-55 to 125

8 Pin Metal Can TB.C

Pinouts
CA5160 (METAL CAN)
TOP VIEW
SUPPLEMENTARY _ _ TAB
8
COMPENSATION
OFFSET)ULL

#'"

CA5160A, CA5160 (PDIP, SOIC)
TOP VIEW

STROBE
OFFSET NULL

1

1
INV.INPUT 2

INV.INPUT 2
NON INV. INPUT 3
5

OFFSET NULL

4
V-AND CASE

NOTE: CA5160 Series devices have an on-chip·frequency compensation network Supplementary phase-compensation or frequency roll-oll (~desired) can be
connected externally between terminals 1 and 8.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-145

File Number

1924.3

..I

c:«(/)

Za:
O!:!:!
-u..
!ci:::i
a: 0..

w::
~c:(

CA5260, CA5260A

~HARRls.

(KJ

SEMICONDUCTOR

3M Hz, BiMOS Microprocessor Operational
Amplifiers with MOSFET Input/CMOS Output

November 1996

Features

Description

• MOSFET Input Stage provides
- Very High ZI 1.STO (1.5 x 10120) (Typ)
SpA (Typ) at lSV Operation
- Very Low II
2pA (Typ) at SV Operation

The CAS260A and CAS260 are integrated-circuit operational
amplifiers Ihat combine the advantage of both CMOS and
'bipolar transistors on a monolithic Chip. The CAS260 series
circuits are dual versions of the popular CAS160 series. They
are" designed and guaranteed to operate in microprocessor or
logic systems that use +SV supplies.

=
=
=

• Ideal for Single Supply Applications
• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be
Swung O.SV Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails
• CAS260A, CAS260 Have Full Military Temperature
Range Guaranteed Specifications for V+ SV

=

• CAS260A, CAS260 are Guaranteed to Operate Down to
4.SVfor AOL
• Fully Guaranteed to Operate from -55°C to 12SoC at
V+ = SV, V- = GND

Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input impedance,
very-low-input current, and exceptional speed performance.
The use of PMOS field-effect transistors in the input stage
results in common-mode input-voltage capability down to O.SV
below the negative-supply terminal, an important attribute in
single-supply applications.
A complementary-symmetry MOS (CMOS) tranSistor-pair,
capable of swinging the output voltage to within 1OmV of either
'supply-voltage terminal (at very high values of load impedance), is employed as the output circuit.
The CAS260 Series circuits operate at supply voltages ranging
from 4.SV to 16V, or ±2.2SV to ±BV when using split supplies,

Applications
• Fast Sample-Hold Amplifiers

The CAS260, CAS260A have guaranteed specifications for SV
operation over the full military temperature range of -SsoC to
12SoC.

• Long Duration TimersiMonostables

OrderinglnforlnaUon

• Ground Referenced Single Supply Amplifiers

• Ideal Interface with Digital CMOS

PART NUMBER
(BRAND)

• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)

TEMP.
RANGECOC)

PKG.
NO.

PACKAGE

CA5260AE

-55 to 125

B Ld PDIP

EB.3

CA5260AM
(5260A)

-55 to 125

B LdSOIC

MB.15

• Wien Bridge Oscillators

CA5260AM96
(5260A)

·55 to 125

B Ld SOIC Tape
and Reel

MB.15

• Voltage Controlled Oscillators

CA5260E

·55 to 125

B Ld PDIP

EB.3

• Photo Diode Sensor Amplifiers

CA5260M
(5260)

·55 to 125

B LdSOIC

MB.15

CA5260M96
(5260)

·55 to 125

B Ld SOIC Tape
and Reel

MB.15

• Voltage Regulators (Permits Control of Output Voltage
Down toOV)

• SV Logic Systems
• Microprocessor Interface

Pinout
CA5260 (PDIP, SOIC)
TOP VIEW
OUTPUT (A)

1

INV. INPUT (A)

2

7

OUTPUT (B)

NON INV. INPUT (A)

3

6

INV. INPUT (B)

5

NON INV. INPUT (B)

CAUTION: These devices are sensitive to electrostatic discharge, Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

3-146

File Number

1929.3

CA5260, CA5260A
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V- Terminals) ............. 16V
Differential Input Voltage ................................ 8V
Input Voltage ......................... (V+ +8V) to (V- -0.5V)
Input Current. ...................................... 1mA
Output Short Circuit Duration (Note 1) ................ Indefinite

Thermal Resistance (Typical, Note 2)

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . .. -55°C to 125°C

9JA (oCIW)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
157
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Die) ................. " 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............ 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other condiffons above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. IlJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Typical Values Intended Only for Design Guidance, V+ = 5V, V- = OV, TA = 25°C,
Unless Otherwise Specified
TYPICAL VALUES

PARAMETER

SYMBOL

Input Resistance

R,

Input Capacitance

C,

Unity Gain Crossover Frequency

fT

Slew Rate

SR

Transient Response
Rise Time

tr

Overshoot

OS

Settling Time (To <0.1%, Y,N = 4Vp_p)

Electrical Specifications
PARAMETER

ts

SYMBOL

Vo=2.5V

Input Offset Current

',0

Vo=2.5V

I,

Vo=2.5V

UNITS

1.5

TQ

4.3

4.3

pF

3

3

MHz

5

5

V/IlS

VOUT = 2.5Vp_p

..J
«II)

Za:
O~

-II.

CL = 25pF, RL = 2kQ
(Voltage Follower)

0.09

0.09

flS

~::::i
a: 0.

10

10

%

~«

1.8

1.8

IlS

CL = 25pF, RL = 2kQ
(Voltage Follower)

W:ii!

-

TYP

MAX

2

15

1

10

2

15

CMRR

Common Mode Input Voltage
Range

V,CR+
V'CR-

-

-0.5

Power Supply Rejection Ratio

PSRR

I'N+ = 1V; I!N- = 1V

70

84

RL = 00, Vo = 0.5 to 4V

105

111

RL= 10kQ,
Vo = 0.5 to 3.6V

80

86

VCM=Ot01V
VCM = 0 to 2.5V

AoL

10

pA

-

2

15

pA

80

85

-

dB

50

55

2.5

3

2.2

1.70

2

Output Voltage

VOM+

RL =00

4.99

5

-

0

4.4

4.7
0

VOM3

-

0.01

V
0

V

75

84

-

dB

107

113

83

86

1.75

2.2

1.70

2

4.99

dB

-

dB

-

mA
mA

5

-

-

0

0.01

V

4.4

4.7

0.01

0
3

0.01

dB

-0.5

0

3.4
0

3-147

1

3

1.75

VOM-

mV

-

55

VO=5V

RL=2kQ

UNITS

4

50

Vo=OV

VOM+

MAX

1.5

2.5

ISINK

RL= 10kQ

TVP

85

'SOURCE

VOM+

MIN

70

Sink Current

VOM-

CA5260A

CA5260
MIN

Common Mode Rejection Ratio

Source Current

CA5260A

1.5
f=1MHz

TEST
CONDITIONS

V,O

Large Signal Voltage Gain
(Note 3)

CA5260

TA = 25°C, V+ = 5V, V- = OV

Input Offset Voltage

Input Current

TEST CONDITIONS

V
0.01

V

V

3.4
0

V

0.01

V

CA5260, CA5260A
Electrical Specifications
PARAMETER
Supply Current

TA = 250 C, v+ = 5V, V- = OV (Continued)

SYMBOL
ISUPPlY

CA5260

TEST
CONDITIONS

MIN

MAX

MIN

TYP

MAX

UNITS

1.60

2.0

-

1.60

2.0

mA

1.80

2.25

1.80

2.25

mA

VO=OV

-

VO=2.5V

CA5260A

TYP

NOTE:
3. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at Rl = 10ka.

Electrical Specifications
PARAMETER

TA = -55°C to 1250 C, V+ = 5V, V- = OV

SYMBOL

CA5260A

CA5260

TEST
CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

-

2

15

mV

1

10

nA

2

15

nA

65

78

50

60

-

dB
V

Input Offset Voltage

VIO

Vo=2.5V

3

20

Input Offset Current

110

VO=2.5V

1

10

II

VO=2.5V

-

2

15

VCM = 0 to IV

60

78

VCM = 0 to 2.5V

50

60

Input Current
Common Mode Rejection Ratio

CMRR

3

0

V

62

65

-

dB

78

70

78

-

dB

60

65

60

65

dB

VO=OV

1.3

1.6

1.3

1.6

mA

ISINK

VO=5V

1.2

1.4

1.2

1.4

-

mA

VOM+

Rl =

4.99

5

4.99

5

-

V

-

0

0,01

-

0

0.01

V

4.2

4.4

-

4.2

4.4

-

V

VOM-

-

0

0.01

-

0

0,01

V

VOM+

Rl = 2ka

2.5

2.7

-

2.5

2.7

-

V

0

0

0,01

V

VO=OV

-

0.01

1.65

2.2

1.65

2.2

mA

1.95

2.35

1.95

2.35

mA

VICR+

2.5

3

VICR-

-

-0.5

Power Supply Rejection Ratio

PSRR

!:N+ = IV;
tN- = IV

60

65

Rl = 00,
Vo =0.5 t04V

70

Rl = 10ka,
Vo = 0.5 to 3.6V
ISOURCE

Source Current
Sink Current
Output Voltage

Aol

00

VOMVOM+

Rl = 10ka

VOMSupply Current

dB

-0.5

Common Mode Input Voltage
Range

Large Signal Voltage Gain
(Note 4)

-

ISUPPlY

Vo=2.5V

2.5
0

-

NOTE:
4. ForV+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at Rl = 10ka.

Electrical Specifications
PARAMETER

Each Amplifier at TA = 25°C, V+ = 15V, V- = OV, Unless Otherwise Specified

SYMBOL

TEST
CONDITIONS

CA5260A

CA5260
MIN

TYP

MAX

MIN

TYP

MAX

UNITS

-

6

15

-

2

5

mV

0.5

20

pA

5

30

pA

50

320

-

kVN

94

110

80

95

Input Offset Voltage

VIO

Vs = ±7.5

Input Offset Current

110

VS=±7.5

0.5

30

II

Vs =±7.5

5

50

Input Current
Large Signal Voltage Gain

Common Mode Rejection Ratio

Aol
CMRR

VO= 10Vp_p,
Rl = 10ka

50

320

94

110

70

90

3-148

-

dB

-

dB

CA5260, CA5260A
Electrical Specifications

Each Amplifier at TA

Common Mode Input Voltage
Range

VieR

Power Supply Rejection Ratio,

PSRR

VS=±7.5

VOM+

RL = 10kQ

(Continued)

CA5260A

CA5260

TEST
CONDITIONS

SYMBOL

PARAMETER

=25°C, V+ =15V, V- = OV, Unless Otherwise Specified
MIN

TYP

MAX

MIN

TYP

MAX

UNITS

10

-0.5 to
12

0

10

-0.5 to
12

0

V

32

320

32

150

I1VN

13.3

-

V

0.002

0.01

V

IWloItN±
Maximum Output Voltage

11

15

-

VOM+

0

0.01

12

22

45

12

14.99

00

VOMMaximum Output Current

IOM+
(Source)

VO=7.5V

1+

V

0

0.01

V

12

22

45

mA

45

12

20

45

mA

9

16.5

-

9

16.5

mA

Va (Amp A) = OV
Va (Amp B) = OV

1.2

4

1.2

4

mA

5

9.5

5

9.5

mA

ov

..J

-

I'Nrolf!.T
f= 1kHz

Crosstalk

15

20

Va (Amp A) =
Va (Amp B) = 7.5V
Input Offset Voltage
Temperature Drift

14.99

Va (Amp A)=7.5V
Va (Amp B) = 7.5V

IOM- (Sink)
Total Supply Current, RL = 00

11
0.01

VOMRL =

13.3
0.002

-

8

6

I1VPC

«en
Za:

120

dB

!;::::i

O!!:!
-1.1..

120

W::!!!

~«

Schematic Diagram

+IN

a: a.

·IN

OUT

3·149

·IN

+IN

v·

CA5420, CA5420A

HARRIS
SEMICONDUCTOR

O.5MHz, Low Supply Voltage, Low Input Current
BiMOS Operational Amplifiers

November 1996

Features

Description

• CA5420A, CA5420 at sv Supply Voltage with Full
Military Temperature Range Guaranteed
Specifications
• CA5420A, CA5420 Guaranteed to Operate from ±1V
to ±10V Supplies

The CA5420A and CAS420 (see Note) are integrated circuit
operational amplifiers that combine PMOS transistors and
bipolar transistors on a single monolithic Chip. They are
designed and guaranteed to operate in microprocessor logic
systems that use V+ = SV, V- = GND, since they can operate
down to ±lV supplies. They will also be suitable for 3.3V logic
systems.

•
•
•
•

2V Supply at 300llA Supply Current
1pA (Typ) Input Current (Essentially Constant to 85°C)
Rail-to-Rail Output Swing (Drive ±2mA Into 1kQ Load)
Pin Compatible with 741 Op Amp

The CA5420A and CA5420 BiMOS operational amplifiers feature gate-protected PMOS transistors in the input circuit to
provide very high input impedance, very low input currents
(less than 1pAl. The internal bootstrapping network features a
unique guardbanding technique for reducing the doubling of
leakage current for every 10°C increase in temperature. The
CAS420 series operates at total supply voltages from 2V to
20V either single or dual supply. These operational amplifiers
are internally phase compensated to achieve stable operation
in the unity gain follower configuration. Additionally, they have
access terminals for a supplementary external capaCitor if
additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS in the input stage results in commonmode input voltage capability down to 0.4SV below the negative supply terminal, an important attribute for single supply
application. The output stage uses a feedback OTA type
amplifier that can swing essentially from rail-to-rail. The output
driving current of 1.0mA (Min) is provided by using nonlinear
current mirrors.

Applications
• pH Probe Amplifiers
•
•
•
•
•

Picoammeters
Electrometer (High Z) Instruments
Portable Equipment
Inaccessible Field Equipment
Battery Dependent Equipment (Medical and Military)

• 5V Logic Systems
• Microprocessor Interface

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGEfC)

PKG.
NO.

PACKAGE

CA5420AM
(5420A)

-55 to 125

BLd SOIC

MB.15

CA5420AT

-55 to 125

B Pin Metal Can

TB.C

CA5420E

-55 to 125

B Ld PDIP

EB.3

CA5420M
(5420)

-55 to 125

B LdSOIC

MB.15

The CA5420 series has the same 8 lead pinout used for the
industry standard 741.

CA5420T

-55 to 125

B Pin Metal Can

TB.C

NOTE: Formerly Development Type No. TAl 0841.

These devices have guaranteed specifications for SV
operation over the full military temperature range of -SSoC to
125°C.

Functional Diagram

Pinouts
CA5420 (PDIP, SOIC)
TOP VIEW

CA5420 (METAL CAN)
TOP VIEW

CA5420

TAB ?ROBE

OF~~IT

1

IN~~

2

OF~~~eL

v+

IN~r-::r

NON-INV. 3
INPUT

;

OUTPUT

5 OFFSET NON-INV. 3
NULL

OFFSET
NULL

INPUT

VBUFFER AMPS;
BOOTSTRAPPED
INPUT PROTECTION
NE1WORK

NOTE: Pin is connected to Case.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-150

HIGH GAIN
(50K)

OTABUFFER
(X2)

File Number

1925.3

CA5420, CA5420A
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V- Terminals). . . . . .. . .... 22V
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15V
Input Voltage .......................... (V+ + 8V) to (V- -0.5V)
......................
. .... 1mA
Input Current. . .
Output Short Circuit Duration (Note 1) . . . . . . . . . . . . .. Indefinite

Thermal Resistance (Typical, Note 2)
9JA (oCIW) 9JC (OCIW)
PDIP Package....... . .. .. . . ... . .
96
N/A
SOIC Package...................
157
N/A
80
Metal Can Package. . . . . . . . . . . . . . .
165
r\iiaximum Junction Temperature (Metal Can) .............. 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range (All Types). .. -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range ........................ -55°C to 125°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. 9JA is measured with the component mounted on an evaluation PC board in Iree air.

Electrical Specifications

Typical Values Intended Only lor Design Guidance. V+ = +5V; V- = GND, TA = 25°C

PARAMETER

CA5420

CA5420A

UNITS

Input Resistance

RI

150

150

TQ

Input Capacitance

CI

4.9

4.9

pF

Output Resistance

Ro

300

300

Q

Equivalent Input
Noise Voltage

eN

62

62

nV/VHz

Short-Circuit Current
To Opposite Supply

SYMBOL

TEST CONDITIONS

1= 1kHz

ISink

etC/)

38

38

nVNF!Z

!cc:::i

2.6

2.6

mA

W:ii

10M-

2.4

2.4

mA

I

Gain Bandwidth Product

fT

0.5

0.5

MHz

Slew Rate

SR

0.5

0.5

V/JlS

Transient Response

I Rise Time

tr

0.7

0.7

JlS

I Overshoot

OS

15

15

%

Current Irom Terminal 8 To V-

18+

20

20

JIA

Current Irom Terminal 8 To V+

18-

2

2

mA

Settling Time

Electrical Specifications

PARAMETER

RL = 2kQ, CL = 100pF

0.01%

Av= 1

12Vp-p Input

8

8

JlS

0.10%

Av= 1

12Vp-p Input

4.5

4.5

JlS

TA = 25°C, V+ = 5V, V- = 0, Unless Otherwise Specilied

SYMBOL

Za::
o!!:!
-LL

10M+

I = 10kHz
ISource

I Rs=100Q

..J

TEST
CONDITIONS

CA5420

CA5420A

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

-

1.5

10

-

1

5

mV

VO=2.5V

0.02

1

0.02

0.5

pA

VO=2.5V

0.02

2

0.02

1

pA

Input Offset Voltage

VIO

Vo=2.5V

Input Offset Current

110

Input Current

II

Common Mode Rejection Ratio

CMRR

VCM = 0 to 3.7V, Vo = 2.5V

70

Common Mode Input Voltage
Range

VICR+

Vo=2.5V

3.7

4

-

-

-0.3

0

Power Supply Rejection Ratio

PSRR

70

80

-

VICR-

IN+ = 1V; IN- = 1V

3-151

75

80

3.7

75

4

-

-0.3

0

V

83

-

dB

83

dB
V

a::c..
~et

CA5420, CA5420A
Electrical Specifications

PARAMETER
Large Signal Voltage Gain

TA = 25°C, V+ = 5V, V- = 0, Unless Otherwise Specified (Continued)

SYMBOL

CA5420

TEST
CONDITIONS

TYP

MAX

MIN

-

AoL

80

B5

dB

1.2

2.7

mA

1.2

2.1

mA

4.9

4.94

RL=oo

B5

B7

Vo= 0.5 to4V

RL= 10kO

B5

B7

Vo= 0.7 to 3V

Sink Current
Output Voltage

RL=2W

BO

85

ISOURCE

VO=OV

1.2

2.7

ISINK

VO=5V

1.2

2.1

-

VOM+

RL=oo

4.9

4.94

-

0.13

0.15

VOMVOM+

ISUPPLY

PARAMETER

V

3.5

4.6

-

3.5

4.6

-

V

0.15

0.15

V

400

500

-

0.1

Vo=OV

-

0.1

400

500

430

550

-

430

550

ItA
ItA

4.9

-

V

0.12

0.15

V

4.7

TA = -55°C to 125°C, V+ = 5V, V- = 0, Unless Otherwise Specified

SYMBOL

TEST
CONDITIONS

110

Vo=2.5V

Up to TA = B50C

110

IIII

CA5420
MIN

-

Vo=2.5V

IIII

CA5420A

TYP

MAX

MIN

TYP

MAX

UNITS

3

15

-

2

10

mV

1.5

3

-

1.5

3

nA

2

10

2

10

pA

2

5

15

25

Common Mode Rejection Ratio

CMRR

VCM=Ot03.7V,
Vo=2.5V

65

Common Mode Input Voltage
Range

VICR+

Vo=2.5V

3.7

4

-

-

-0.3

0

Power Supply Rejection Ratio

PSRR

!N+= W;
!N-=W

65

BO

-

Vo=0.5t04V

RL=oo

80

Vo = 0.7 to 4V

RL= lOW

BO

Vo = 0.7 to 2.5V

RL=2W

75

VICR"

70

75

2

5

nA

10

15

pA

80

-

dB

4

-

V

-0.3

0

V

70

B3

-

dB

B5

B5

B7

dB

B5

BO

B7

dB

BO

75

BO

dB

1

2.7

1

2.7

mA

3.7

AoL

ISOURCE

VO=OV

Sink Current

ISINK

Vo=5V

1

2.1

Output Voltage

VOM+

RL=oo

4.B

4.9
0.16

VOMVOM+

RL= lOW

VOMVOM+

RL=2kO

4.7

4.9

-

0.15

3

VOMSupply Current

V
0.15

RL=2kO

Input Offset Current

Source Current

0.13

dB

-

Vo=2.5V

Large Signal Voltage Gain

-

dB

87

0.15

VIO

Up to TA = 85°C

87

85

4.9

Input Offset Voltage

Input Current

B5

0.12

VO=2.5V

Electrical Specifications

UNITS

-

VOMSupply Current

MAX

4.7

RL = 10kO

VOMVOM+

TYP

,

VO= 0.5 t04V

Source Current

CA5420A

MIN

ISUPPLY

VO=OV
VO=2.5V

-

3-152

0.2

1

2.1

4.B

4.9

-

V

-

0.16

0.2

V

0.2

V
V

4.7
0.20

mA

4.9
0.15

V

4

-

4

-

0.14

0.2

0.14

0.2

V

430

550

430

550

(.LA

480

600

480

600

ItA

3

CA5420, CA5420A
Electrical Specifications

PARAMETER

For Equipment Design at VSUPPLY = ±lV, TA = 25°C, Unless Otherwise Specified

SYMBOL

Input Offset Voltage

VIO

Input Offset Current

11101

Input Current
Large Signal Voltage Gain

Common Mode Rejection Ratio

TEST
CONDITIONS

CA5420
MIN

TYP

MAX

MIN

TYP

MAX

5

10

-

2

5

mV

0.01

4 (Note 3)

0.01

4 (Note 3)

pA

0.02

5 (Note 3)

-

0.02

5 (Note 3)

pA

10

100

-

20

100

-

kVN

80

100

86

100

-

560

1000

IlVN

65

60

65

-

dB

0.5

0.2

0.5

-1.3

-1

-1.3

-

V

32

320

IlVN

-

1111
AoL

RL = 10kO

CMRR

560
55

Common Mode Input Voltage
Range

0.2

VICR+

-

VICR"
Power Supply Rejection Ratio

Maximum Output Voltage

PSRR

VOM+

RL =

00

VOMSupply Current
Device Dissipation
Input Offset Voltage Temp. Drift

Electrical Specifications

PARAMETER

Po
!NIO'!'.T

SYMBOL
VIO

Input Offset Current

11101

Large Signal Voltage Gain

100

1000

UNITS

dB

V

-0.91

-

350

650

350

650

IJ.A

0.7

1.1

0.7

1.1

mW

4

-

60

80

-

70

90

0.95

-

0.9

0.95

-0.85

-0.91

-0.85

-

4

dB
V
V

IlVPC

TEST
CONDITIONS

1111
AoL

RL= 10kO

CA5420
MIN

TYP

MAX

MIN

TYP

MAX

UNITS

5

10

-

2

5

mV
pA

0.03

4 (Note 3)

0.05

5 (Note 3)

10

100

0.03

4 (Note 3)

-

0.05

5 (Note 3)

20

100

pA
kVN

80

100

-

86

100

CMRR

-

100

320

-

100

320

IlVN

70

80

70

80

-

dB

Common Mode Input Voltage
Range

VICR+

8.5

9.3

9

9.3

VICR-

-10

-10.3

-10

-10.3

-

V

Power Supply Rejection Ratio

PSRR

-

32

-

32

320

IlVN

70

90

70

90

9.7

9.9

9.7

9.9

-9.7

-9.85

-9.7

-9.85

-

-

450

1000

IJ.A

9

14

mW

4

-

IlVPC

Common Mode Rejection Ratio

Maximum Output Voltage

VOM+
VOM-

Supply Current
De,vice Dissipation
Input Offset Voltage
Temperature Drift

RL =

00

320

-

ISUPPLY

450

1000

Po

9

14

!'.VloI!'.T

4

-

dB

V

dB
V
V

NOTE:
3. The maximum limit represents the levels obtainable on high-speed automatic test equipment. Typical values are obtained under
laboratory conditions.

3-153

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zo::
O!:!:!
-LL.

~:::i

0::0.

~«

CA5420A

-

..J

w:=

For Equipment Design at VSUPPLY = ±10V, TA = 25°C, Unless Otherwise Specified

Input Offset Voltage

Input Current

1800

0.9

-

ISUPPLY

CA5420A

CA5420, CA5420A
Typical Applications
Picoammeter Circuit

High Input Resistance Voltmeter

The exceptionally low input current (typically 0.2pA) makes
the CA5420 highly suited for use in a picoammeter circuit.
With only a single 1000 resistor, this circuit covers the range
from ±1.5pA. Higher current ranges are possible with suitable
switching techniques and current scaling resistors. Input transient protection is provided by the 1MO resistor in series with
the input. Higher current ranges require that this resistor be
reduced. The 10MO resistor connected to pin 2 of the
CA5420 decouples the potentially high input capacitance
often associated with lower current circuits and reduces the
tendency for the circuit to oscillate under these conditions.

Advantage is taken of the high input impedance of the CA5420
in a high input resistance DC voltmeter. Only two 1.5V "AA"
type penlite batteries power this exceedingly high-input resistance (>1,000,OOOMO) DC voltmeter. Full-scale deflection is
±500mV, ±150mV, and ±15mV. Higher voltage ranges are easily added with external input voltage attenuator networks.

lOGO

The meter is placed in series with the gain network, thus
eliminating the meter temperature coefficient error term.
Supply current in the standby position with the meter undeflected is 300~A. At full-scale deflection this current rises to
800~. Carbon-zinc battery life should be in excess of 1,000
hours.

+1.5V

FtGURE 1. PtCOAMMETER CIRCUIT

FIGURE 2. HIGH INPUT RESISTANCE VOLTMETER

Typical Performance Curves
10
TA = 25°C
v-=ov

TA = 25°C
RL= 100kQ

I I
V+=2V ~
V+=5V
V+=10V
100 v+ =20V

Vovo+

VICR+

5
SUPPLY VOLTAGE

10

'IIIII~

I'

VleR-

1000
0.001

15

M

0.1

1

10

LOAD (SOURCING) CURRENT (rnA)

FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE
INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE

FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT

3-154

CA5420, CA5420A
Typical Performance Curves

(Continued)

V+=5V
V-=GND

TA = 25°C
V+=OV

L. ~
~

~

<
..=.
zfw

-~ ~t-- ~V-=-20V
V-=-10V

2400
2000

II:
II:

:::> 1600

V-=-5V
"V- = -2V

(J

~ 1200

"""":::>

II)

800
400

0.1
LOAD (SINKING) CURRENT (rnA)

10

3.75

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CD

f-

:::>

!:i

""

f- 1.25

:::>
0

""

1!:

/
o

10
100
LOAD RESISTANCE (kil)

~"'" V

-

V

o

1000

25

FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE

...

200
100

,/

35

45

55

65
75
85
95
TEMPERATURE (oC)

iii"
~

~
CI

I'" ~ ~

100
80

w

CI

~

~

""

0
0

....

""

~ "'-

125

-90

"-

60

1'00..

" "-

40

'"~

20

1

en
w
0
-45

~

o

104

102

103

104

"

"~

-135
-180

w

II:
CI

w

e.w
~

:r

""""

0

9
zw

""0

FREQUENCY (Hz)

FREQUENCY (Hz)

FIGURE 9. INPUT NOISE VOLTAGE vs FREQUENCY

105 115

TA = 25°C
V+ = +10V, V- = 10V
RL = 10kil
CL=OpF

Z

w
0

103

/

J

FIGURE 8. INPUT BIAS CURRENT DRIFT (AlslAT)

TA = 2SoC

Vs =+10V
Vs =±5V
_ Vs =±1V

~<

J

400

II)

0

5

800
TA = 25°C
V+=5V
V-=GND
RL TOGND

~

~

4

FIGURE 6. SUPPLY CURRENT vs OUTPUT VOLTAGE

5.00

z

3

OUTPUT VOLTAGE (V)

FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT

CI

2

0

FIGURE 10. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE

3-155

CA5470

HARRIS
SEMICONDUCTOR
November 1996

Quad, 14MHz, Microprocessor BiMOS-E
Operational Amplifier with MOSFET InputlBipolar Output

Features

Description

• High Speed CMOS Input Stage Provides
- Very High ZI •••••••••••••.•. 5Tn (5 x 1012n) (Typ)
- Very Low II ••••....••• 0.5pA (Typ) at 5V Operation
- Very Low 110 ••••••••• 0.5pA (Typ) at 5V Operation

The CA5470 is an operational amplifier that combines the
advantages of both high speed CMOS and bipolar transistors
on a single monolithic chip. It is construcled in the BiMOS-E
process which adds drain-extension implants to 3J.lm polygate
CMOS, enhancing both the voltage capability and providing
vertical bipolar transistors for broadband analog/digital functions. This process lends itself easily to high speed operational
amplifiers, comparators, analog swilches and interface peripherals, resulting in twice the speed of the conventional CMOS
transistors having similar feature size.

• ESD Protection to 2000V
• 3V to 16V Power Supply Operation
• Fully Guaranteed Specifications Over Full Military
Range
• Wide BW (14MHz)j High SR (SVlJ.ls) at SV Supply
• Wide VICR Range From -o.5V to 3.7V (Typ) at 5V Supply
• Ideally Suited for CMOS and HCMOS Applications

Applications
• Bar Code Readers

BiMOS-E are broadbased bipolar transistors that have high
transconductance, gains more constant with current level, stable "precision" base-emitter offset voltages and superior drive
capability. Excellent interface with environmental potentials
. enable use in SV logic systems and future 3.3V logic systems.
Refer to Application Note AN8811.
ESD capability exceeds the standard 2000V level. The
CAS470 series can operate with Single supply voltages from
3V to 16V or ±1.5V to ±8V. They have guaranteed specifications at both 5V and ±7.SV at room temperature as well as
over the full -SSoC to 12SoC military range.

• Photodiode Amplifiers (IR)
• Microprocessor Buffering
• Ground Reference Single Supply Amplifiers
• Fast Sample and Hold

Ordering Information

• Timers
• Voltage Controlled Oscillators

PART NUMBER
(BRAND)

• Voltage Followers

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

• V to I Converters

CA5470E

-5510125

14Ld PDIP

E14.3

• Peak Detectors

CA5470M
(5470)

-5510125

14 LdSOIC

M14.15

CA5470M96
(5470)

-55 to 125

14 Ld SOIC Tape
and Reel

M14.15

• Precision Rectifiers
• 5V Logic Systems
• 3V Logic Systems

Pinout
CA5470 (PDIP, SOle)
TOP VIEW
OUTPUT!

!

NEG. INPUT 1 2
POS.INPUT!

POS. INPUT 2 5
9

NEG. INPUT 2 6

NEG. INPUT 3

OUTPUT2 7

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-156

File Number

1946.3

CA5470
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage (Between V+ And V- Terminals) ......... 16V
Differential Input Voltage ................................ BV
Input Voltage .......................... (V+ +BV) to (V- -0.5V)
Input Current. ....................................... 1mA
Output Short Circuit Duration (Note 1) ................ Indefinite

Thermal Resistance (Typical, Note 1)
9JA (oCIW)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature (Die) .................... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os) ............. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range ......................... -55°C to 12SoC

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This Is a stress only rating and operation
01 the device at these or any other conditions above those Indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Typical Values Intended Only for Design Guidance at V+ = SV, V- = OV, TA = 2SoC, Unless Otherwise Specified
PARAMETER

SYMBOL

Input Resistance

TEST CONDITIONS

TYPICAL VALUES

UNITS

S

Tn

RI

Input Capacitance

CI

Unity Gain Crossover Frequency

fr

Slew Rate

SR

CL = 2SpF, RL= 2kn
(Voltage Follower)

tr

Overshoot

pF

14

MHz

S

V/Jls

27125

ns

20

%

a:c..

1

JlS

~<

436

kHz

VOUT = 3.6SVp_p

Transient Response:
Rise Time/Fall Time

3.1

f= 1MHz

OS

Settling Time (To <0.1%, VIN = 4Vp_p)

CL = 2SpF, RL= 2kQ
(Voltage Follower)

ts

Full Power BW, SR = SV/JlS

FPBW

Av = 1, VOUT = 3.6SVp_p

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-II.

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Electrical Specifications TA = 2SoC, V+ = SV, v- = GND
PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

6

22

mV

11101

-

O.S

SO (Note 3)

pA

II

-

0.5

50 (Note 3)

pA

VICR

3.5

-0.5 to 3.7

0

V

70

dB

Input Offset Voltage

IVIOI

Input Offset Current
Input Current
Common Mode Input Range

TEST CONDITIONS

Common Mode Rejection Ratio

CMRR

VICR = OV to 3.5V

55

Power Supply Rejection Ratio

PSRR

IN = 2V

60

75

-

Positive Output Voltage Swing

VOM+

RL = 2kQ to GND

4

4.4

-

V

Negative Output Voltage Swing

VOM-

RL = 2kn to GND

-

0.06

0.10

V

7

dB

-

6

Unity Gain Bandwidth Product

fT

10

14

MHz

Slew Rate

SR

4

5

V/Jls

ISOURCE

4

5.5

mA

ISINK

1.0

1.2

mA

BO

90

dB

Total Supply Current

ISUPPLY

VOUT = 2.5V, RL = 00

mA

Output Current
Source to opposite supply
Sink to opposite supply
Open Loop Gain

AoL

O.SV to 3.SV, RL = 10kQ

NOTE:
3. This is the lowest value that can be tested reliably. Almost all devices will be <10pA.

3-157

..J



~

10

8

,

6
4

2
10K

V+ = 5V, V· = OV

1111111

I

1111111

I

100K

I\.
~~
10M

1M

100M

FREQUENCY
FIGURE 1. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY

Metallization Mask Layout
97.2

o
10
_1......
1

_.1_.1_..1_.1..._1..I
20

30

40

50

60 69.7

90 -

80 70 -

Dimensions in parentheses are in millimeters and
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10.3 inch).

60 97.2
(2.46)

50 -

The layout represents a chip when it is part of the
wafer. When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the face
of the chip. Therefore, the isolated chip is actually 7
mils (0.17mm) larger in both dimensions.

40 -

30 20 10 -

69.7
(1.77)

3·160

·1

HA-2400, HA-2404,
HA-2405

HARRIS
SEMICONDUCTOR

40MHz, PRAM Four Channel
Programmable Amplifiers

November 1996

Features

Description

• Programmability

THA-2400/04/05 comprise a series of four-channel
programmable amplifiers providing a level of versatility
unsurpassed by any other monolithic operational amplifier.
Versatility is achieved by employing four input amplifier
channels, anyone (or none) of which may be electronically
selected and connected to a single output stage through
DTLlTTL compatible address inputs. The device formed by
the output and the selected pair of inputs is an op amp which
delivers excellent slew rate, gain bandwidth and power
bandwidth performance. Other advantageous features for
these dielectrically isolated amplifiers include high voltage
gain and input impedance coupled with low input offset
voltage and offset current. External compensation is not
required on this device at closed loop gains greater than 10.

• High Rate Slew ........................... 30VlJ.lS
• Wide Gain Bandwidth .................•... 40MHz
• High Gain ••.•...........•........••.•.. 150kVN
• Low Offset Current .................•.•....••5nA
• High Input Impedance ...................... 30MO
• Single Capacitor Compensation
• DTIJITL Compatible Inputs

Applications
• Thousands of Applications; Program
- Signal Selection/Multiplexing
- Operational Amplifier Gain
- Oscillator Frequency
- Filter Characteristics
- Add-Subtract Functions
- Integrator Characteristics
- Comparator Levels

Ordering Information
PART NUMBER
HA1-2400-2
HA1·2404·4
HA1·2405·5
HA3-2405-5

TEMP.
RANGE ("C)
-55 to 125
·25 to 85
Oto 75
Oto 75

PACKAGE
16LdCERDIP
16LdCERDIP
16 LdCERDIP
16 Ld PDIP

PKG.
NO.
F16.3
F16.3
F16.3
E16.3

Each channel of the HA-2400/04I05 can be controlled and
operated with suitable feedback networks in any of the
standard op amp configurations. This specialization makes
these amplifiers excellent components for multiplexing signal
selection and mathematical function designs. With 30Vll1s
slew rate, 40MHz gain bandwidth and 30MO input
impedance these devices are ideal building blocks for signal
generators, active filters and data acquisition designs.
Programmability, coupled with 4mV typical offset voltage and
5nA offset current, makes these amplifiers outstanding
components for signal conditioning circuits.
During Disable Mode VOUT goes to V-. For high output
impedance during Disable, see HA2444.
For further design ideas, see Application Note AN514.

Pinout

TRUTH TABLE
HA-2400/o4 (CERDIP)
HA-2405 (CERDIP, PDIP)
TOP VIEW)
00
01

ENABLE

D1

DO

EN

SELECTED CHANNEL

D1

L

L

H

1

L

L

H

H

2

L

H

L

H

3

H

H

H

H

4

H

X

X

L

None, VOUT goes to V-

X

GNO

---,

COMP

OUT

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-161

File Number

2891.2

-'
eelf)

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HA-2400, HA-2404, HA-2405
A~solute

Maximum Ratings

Thermal Information

TA = 25°C

Thermal Resistance (Typical, Note 2)
8JA (oC/W) 8JC (oCIW)
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . .. 45.0V
PDIP Package...................
80
N/A
Differentfallnput Voltage ......•..•..•.............. VSUPPLY
Digital Input Voltage. . . . . . . . . . . . . . . • • . . . . .. -0.76V to + 1O.OV
CERDIP Package . . . . . . . . . . . . . . . .
90
35
Output Current. • . . . . . . . .. Short Circuit Protected, Isc <±33mA) . Maximum Junction Temperature (Ceramic Package). . . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Internal Power Dissipation (Note 1)
Maximum Storage Temperature Range ... . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C)
Operating Conditions
Temperature Range
HA-2400-2 .................••.......... , -55°C to 125°C
HA-2404-4. . . . . . . . . • . . . . . . . . . . . . . . . . . . . .. -25°C to 85°C
HA-2405-5 ................•............... , OOC to 75°C
CAUTION: Stresses above ihose listed In "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated In the operatIonal sectIons of thIs specification is not implied.

NOTES:
1. Maximum power dissipation including output load, must be designed to maintain the junction temperature below 175°C for the ceramic
package, and below 150°C for the plastic packages.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Test Conditions: VSUPPLY = ±15V, Unless Otherwise Specified. Digital Inputs: VIL = +0.5V, VIH = +2.4.
Limits apply to each of the four channels, when addressed

PARAMETER

TEST
CONDITIONS

TEMP_
('IC)

HA-2400104

I

MIN

TYP

25

-

4

Full

-

HA-2405
MAX

I

MIN

I TYP

MAX

I UNITS

INPUT CHARACTERISTICS
Offset Voltage

Bias Current (Note 8)

25
Full

Offset Current (Note 8)

-

25

-

4

9

mV

-

-

11

mV

50

250

nA

-

500

nA

5

50

nA

-

100

50

200

-

400

5

50

Input Resistance (Note 8)

25

-

Common Mode Range

Full

±9.0

150

Full

9
11

-

-

30

±9.0

-

-

50

150

-

25
100

dB

-

100

30

-

nA
MO

-

V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

RL=2kQ

25

50

VOUT = 20Vp_p

Full

25

VCM = ±5V

Full

80

100

-

74

Gain Bandwidth (Notes 3, 9)

25

20

40

-

20

40

MHz

Gain Bandwidth (Notes 4, 9)

25

-

4

8

MHz

10

-

VN

±10.0

±12.0

10

20

mA

Common Mode Rejection Ratio

Minimum Stable Gain

4

8

10

-

Full

±10.0

±12.0

25

10

20

(CCOMP=O)

kVN
kVN

OUTPUT CHARACTERISTICS
Output VoHage Swing

RL=2kQ

Output Current

-

-

V

Full Power Bandwidth (Notes 3,10)

VOUT = 20Vp_p

25

640

950

640

950

kHz

Full Power Bandwidth (Notes 4, 10)

VOUT = 20Vp_p

25

200

250

200

250

kHz

TRANSIENT RESPONSE (Note 11)
Rise Time (Note 4)

VOUT = 200mVPEAK

25

20

45

Overshoot (Note 4)

VOUT = 200mVpEAK

25

-

25

40

Slew Rate (Note 3)

VOUT = 10Vp_p

25

20

30

Slew Rate (Notes 4, 9)

VOUT= 10Vp_p

25

6

8

3-162

:;

20

50

-

25

40

20

30

6

8

ns

%
V/iJ.s

-

V/jJ.S

HA-2400, HA-2404, HA-2405
Electrical Specifications

Test Conditions: VSUPPLY = ±15V, Unless Otherwise Specified. Digital Inputs: VIL = +0.5V, VIH = +2.4.
Limits apply to each of the four channels, when addressed (Continued)
TEST
CONDITIONS

PARAMETER
Settling Time (Notes 4, 5, 9)

HA-2400I04

HA-240S

TEMP.
fC)

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

25

-

1.5

2.5

-

1.5

2.5

IlS

-

1

1.5

5

VOUT= 10Vp.p

CHANNEL SELECT CHARACTERISTICS
Digital Input Current

VIN=OV

Full

Digital Input Current

VIN= +5.0V

Full

Output Delay (Notes 6, 9)

25

Crosstalk (Note 7)

25

100
-BO

1

1.5

rnA

5

-

nA

100

250

ns

·74

·110

-

dB

-

4.B

6.0

74

90

·250

-110

POWER SUPPLY CHARACTERISTICS
Supply Current

25

Power Supply Rejection Ratio

Vs = ±10V to±20V

Full

I

74

4.8

6.0

90

-

I

I

rnA
dB

NOTES:
3. Av = +10, CCOMP = 0, RL = 2kn, CL = 50pF.
4. Av = +1, CCOMP = 15pF, RL = 2kn, CL = 50pF.
5. To 0.1% offinal value.
6. To 10% of final value; output then slews at normal rate to final value.
7. Unselected input to output; VIN = ±10Voc·
B. Unselected channels have approximately the same input parameters.
9. Guaranteed by design.
SR
10. Full Power Bandwidth based on slew rate measurement using: FPBW = -2-V--: V pEAK = 5V.
"
PEAK
11. See Figure 13 for test circuit.

Schematic Diagram
HA-2400
IN+

DO

IN-

COMP

01

Diagram Includes: One Input Stage, Decode Control, Bias Network, and Output Stage

3-163

+Vcc

HA-2400, HA-2404, HA-2405

Typical Applications
IN

2K

Sample Charging Rate
Hold Drift Rate

12

= CV Is

1K

Switch Pedestal Error =
500

11

= CV/S

gv

11 ~ 150 x 1O-6A
x 10-9A at 25°C
~ 600 x 10-gA at -55°C

12 ~ 200
500

~ 100 x lO-g A at 125°C
Q ~ 2 x 1O- 12C
FIGURE 2_ HA·2400 SAMPLE AND HOLD

FIGURE 1_ HA·2400 AMPLIFIER, NONINVERTING
PROGRAMMABLE GAIN

For more examples, see Harris Application Note AN514_

3·164

HA-2400, HA-2404, HA-240S
Typical Performance Curves
140

o

120

'l!l

,

100

C

80

UJ

!iii

60

::>

40

S

II:
II:

0

S

f\.

c

~
...... ~

o

·55

·50

·25

II:
W

::>
-'

~

125

0.8

·55

·50

·25

1

:::--....
........

25
50
0
TEMPERATURE (oC)

II:

..J

J

....

en

~ ....
100.

~

Gl.~

3

·55

·50

·25

0
25
50
TEMPERATURE (oC)

75

100

II,

>
:!!
+1

........

)OPIFII

S
fa

1.1

........ ........ ;:::~

,/ 15pF
,/ 30pF

~

1.0

120

a

z
;;:

80

CI
UJ

CI

~

g
Q.

0
0

..J

z

......
...

60

~
40

100PF/

Q.

"" "
....

300P~~

20

l000pF

0

IIII
I

UJ

0

,~

·20
10

100

I'

~

~
i"o

i'"

lK

"

~~

UJ

::>
-'

~

i"o

c
~ 0.9

t'-ol' ~~ l"10M

W::i

)

.j
.. ,

N~
10M

c

120 ;;

en

150

"i!:

180
210
100M

1.2

~

10K
lOOK
1M
FREQUENCY (Hz)

PHASE 90 CI
w

FIGURE 6. OPEN LOOP FREQUENCY AND PHASE RESPONSE

FIGURE 5. POWER SUPPLY CURRENT vs TEMPERATURE

iii' 100

CCOMP= OpF
- - - CCOMP = 15pF
III I
·20 I IIII I 1111 I III
lK
10K
lOOK
1M
10
100
FREQUENCY (Hz)

125

O~
-II..
!;;::::;

u;

II:

r~

::>

UJ
UJ

60

1'0

"

Q.
Q.

cs:rn
za:

30

.~' 1"-,

~

i'"

~

125

100

0

~

4

,

CROSSTALK REJECTION, ""' = +1

~~.

!iiiUJ

75

FIGURE 4. NORMALIZED AC PARAMETERS vs TEMPERATURE

120
I
I
VSUPPLY = ±20V ,
VSUPPLY =±15V ,
VSUPPLY = +10V ,

f':

II:

li!

100

.....

~

I

75

"""
rWRi~

~ 0.9

OFFSET CURRENT _

0
25
50
TEMPERATURE (0C)

1.0

~

5

o

IBAND~IDTH

C

FIGURE 3. INPUT BIAS CURRENT AND OFFSET CURRENT vs
TEMPERATURE

~

,

W

...........

........... I"---

5

,

1.1

~

I-~CURRENT-:-

r--

10

,

1.2

~
~

100M

k: ----

0.8
±10

--"1 ""'"'"

--

BANDWI~

SLEj'Aj

±15
SUPPLY VOLTAGE (V)

FIGURE 8. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE

FIGURE 7. FREQUENCY RESPONSE vs CCOMP

3·165

±20

a: a.

~cs:

HA-2400, HA-2404, HA-2405
·Typical Performance Curves
110

r105

iii"
z

:!!.

I

I

VSUPPLY = ±20V
VSUPPLY = ±15V_

r- VSUPPLY = ±lOV

.....e?
...;.

100

~

(Continued)

~

~ -.....

~

-- ~

:;..~

rI.. 10

~

;;,...-"'"

~
CI

z

isUl

·50

~

!5"!5
0

95

90
·55

·25

0
25
50
TEMPERATURE (oC)

75

100

0.1
10K

125

1M
FREQUENCY (Hz)

1000

~~

..... ~

10K SOURCE RESISTANCE

10

iii'100

o

.-

z

~

~

1

~

ITI

~

......

z

1kHz

~

10

'N

~
I 11111111
10kHz

I 11111111
100kHz

~

1

UPPER 3dB FREQUENCY (LOWER 3dB FREQUENCY.l0Hz)
BROADBAND NOISE CHARACTERISTICS

450

I 111111 II 111111 III
1

100

10

1K

10K

FIGURE 12. INPUT NOISE vs FREQUENCY

SELECTED
CHANNEL

..........--_-0 +15.0V
......-o OUT

>--1t-~-

2000

FIGURE 13. SLEW RATE AND TRANSIENT RESPONSE

3-166

!5

0.1

~

i5
z

~~

111111

FREQUENCY (Hz)

FIGURE 11. EQUIVALENT INPUT NOISE vs BANDWIDTH

IN

11111

I I III
lMHz

ffi

a:

(J

Ul

i5

i

'L"

w

~

.,. THERMAL NOISE OF 10K RESISTOR
0.1
100Hz

10

CI

oSOURCE RESISTANCE

w

!!l

1.0

10M

lOOK

FIGURE 10. OUTPUT VOLTAGE SWING VS FREQUENCY

100

~~

......

1.0

FIGURE 9. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE

~

CcOMP=OpF
CcOMP= 15pF

.....

20

0.01
lOOK

HA-2406

HARRIS
SEMICONDUCTOR

30M Hz, Digitally Selectable Four Channel
Operational Amplifier

November 1996

Features

Description

• TTL Compatible Inputs

The HA-2406 is a monolithic device consisting of four op
amp input stages that can be individually connected to one
output stage by decoding two TTL lines into four channel
select signals. In addition to allowing each channel to be
addressed, an enable control disconnects all input stages
from the output stage when asserted low.

• Single Capacitor Compensation
• Low Crosstalk ............•••........•... -110dB
• High Slew Rate .............•......•...... 20VlllS
• Low Offset Current ..........................5nA
• Offset Voltage .............................• 7mV
• High Gain-Bandwidth •...................• 30MHz
• High Input Impedance ...................... 30MO

Applications
• Digital Control Of
- Analog Signal Multiplexing
- Op Amp Gains
- Oscillator Frequencies
- Filter Characteristics
- Comparator Levels

Dielectric isolation and short-circuit protected output stages
contribute to the quality and durability of the HA-2406.
When used as a simple amplifier, its dynamic performance
is very good and when its added versatility is considered,
the HA-2406 is unmatched in the analog world. It can
replace a number of individual components in analog signal
conditioning circuits for digital signal processing systems.
Its advantages include saving board space and reducing
power supply requirements.

Ordering Information
PART NO.

TEMP
RANGE (oC)

Each input-output combination of the HA-2406 is designed
to be a 20V/IlS, 30M Hz gain-bandwidth amplifier that is
stable at a gain of ten. By connecting one external 15pF
capacitor all amplifiers are compensated for unity gain
operation. The compensation lead may also be used to limit
the output swing to TTL levels through suitable clamping
diodes and divider networks (see Application Note AN514).

PKG.NO.

PACKAGE

HA1-2406-5

Ot075

16LdCERDIP

F16.3

HA3-2406-5

Ot075

16 Ld PDIP

E16.3

HA9P2406-5

oto 75

16Ld SOIC

M16.3

HA9P2406-9

-40 to 85

16 LdSOIC

M16.3

During Disable Mode VOUT goes to V-. For high output
impedance during Disable, see HA2444.
For further design ideas, see Application Note AN514.

Pinout
HA-2406
(PDIP, CERDIP, SOIC)
TOP VIEW)

TRUTH TABLE

01
00
01

ENABLE
GNO

SELECTED
CHANNEL

DO

EN

L

L

H

I

L

H

H

2

H

L

H

3

H

H

H

4

X

X

L

COMP

---,......

None, VOUT
goes toV·

v+

IT\
---"-0

OUTPUT
+IN2

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

3-167

File Number

2892.2

..J

cr:cn
za:
O!!:!
-u.

!;i::J

a: a..

w:=
~cr:

HA-2406
Absolute Maximum Ratings

Thermal Information

TA = 25PC

Supply Voltage Between V+ and V- Terminals .............. 45V
Differential Input Voltage........................... VSUPPLY
Output Current ........... Short Circuit Protected (ISC < ±33mA)

Operating Conditions
Temperature Range
HA-2406-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 75°C
HA-2406-9 ................................ -40°C to 85°C

Thermal Resistance (Typical, Note 1)
9JA (oCIW) 9JC (oCIW)
PDIP Package....... ............
80
N/A
SOIC Package. . . . . . . • . . . . . . . . . . .
96
N/A
CERDIP Package . . . . . . . . . . . . . . . .
90
35
Maximum Junction Temperature (Ceramic Package) ........ 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range .......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only raUng and operation
of the device at these or any other condiffons above those indicated in the operational secUons of this specification is not Implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Test Conditions: VSUPPLY = 15.0V, Unless Otherwise Specified. Digital Inputs: VIL = +0.5V, VIH = +2.4V.
Limits apply to each of the four channels, when addressed.

PARAMETER

TEST
CONDITIONS

HA-2406-5, -9
TEMP (oC)

I

MIN

TYP

MAX

UNITS

INPUT CHARACTERISTICS
Offset Voltage

25

7

Full
Bias Current (Note 7)

Offset Current (Note 7)

10

mV

12

mV

25

50

250

nA

Full

-

500

nA

25

5

50

nA

Full

-

Input Resistance (Note 7)

25

-

30

MQ

Common Mode Range

Full

±9.0

-

V

25

40

150

100

nA

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

RL=2kQ
VOUT = 20Vp_p

Common Mode Rejection Ratio

VCM=±5V

Gain Bandwidth Product (Notes 2, 9)
Gain Bandwidth Product (Notes 3, 9)
Minimum Stable Gain

Full

20

Full

74

80

25

15

30

3

6

25

-

10

CCOMP=O

kVN
kVN
dB
MHz
MHz
VN

OUTPUT CHARACTERISTICS
Output Voltage Swing

RL=2kQ

Full

±10.0

±12.0

Output Current

VOUT=±10V

25

10

15

Full Power Bandwidth (Notes 2, 8, 9)

VOUT = 20Vp_p

25

240

320

Full Power Bandwidth (Notes 3, 8)

VOUT = 20Vp_p

25

64

95

-

25

V

-

mA
kHz
kHz

TRANSIENT RESPONSE (Note 10)
30

100

25

-

25

40

25

15

20

VOUT = 10Vp_p

25

4

6

-

VI1S

VOUT = 10Vp_p

25

-

2.0

3.5

fJS

VIN=OV

Full

-

1

1.5

mA

Rise Time (Note 3)

VOUT = 200mVpEAK

Overshoot (Note 3)

VOUT = 200mVpEAK

Slew Rate (Notes 2, 9)

VOUT = 10Vp_p

Slew Rate (Note 3)
Settling Time (Notes 3, 4)

ns

%
V/fJS

CHANNEL SELECT CHARACTERISTICS
Digital Input Current

3-168

HA-2406
Electrical Specifications

Test Conditions: VSUPPLY

= 15.0V, Unless Otherwise Specified. Digital Inputs: VIL =+0.5V, VIH = +2.4V.

Limits apply to each of the four channels, when addressed. (Continued)
HA-2406-S, -9

TEST
CONDITIONS

PARAMETER
Digital Input Current

TEMP (oC)

TYP

MIN

Full

15

Output Delay (Notes 5, 9)

25

150

Crosstalk (Note 6)

25

VIN = +5.0V

·74

MAX

UNITS
nA

300

ns
dB

·110

POWER SUPPLY CHARACTERISTICS
Supply Current

25
Vs = ±10V to ±20V

Power Supply Rejection Ratio

Full

74

4.B

7.0

mA

90

.

dB

NOTES:
2. Av
3. Av

= +10, CCOMP =0, RL =2k.Q, CL = 50pF.
= + 1, CCOMP = 15pF, RL = 2kn, CL = 50pF.

4. To 0.1% offinal value.
5. To 10% of final value; output then slews at normal rate to final value.

6. Unselected input to output; VIN = ±1 OV
7. Unselected channels have approximately the same input parameters.
B. Full power Bandwidth based on slew rate measurement using: FPBW = Slew Rate .
2ltV pEAK

9. Sample tested.

-'
C(C/)

Za:

10. See Figure 11 for test circuit.

O!!!
-11..

!i::::i
a: a.

Schematic Diagram

W::l!!

IN-

IN+

rD,R.~ R,
0.

Ro

~aK
D.
R.
~2.9K

n~r

Os .....

....
II)

a......

0.9

ra.

Rs
a.OK

o.~

GND

_

~25 0,";-

023

VD

0"

~

0 ••

I~

P

D15l

03~
r ........

'--

,:J000

R.
'.5K

~OO

R.
34

r--- ~R OUT

....

094 j§.s ....

3'

36.5

o

••

V+

Do•
..... , 0••

0.0
I,Q91

}m~~
INPUT STAGES

a..

VA

R10
10K

0 ••

cif

'I

VB

R.
4K

1.2

097

9.0pF

VC

0'3

~O'7

ro,.

I,D••

a

0'0

Dt!

rD.,

I'll

0,.

R35
0.75K

.r

[D••

-

%4K
R33

D'03l",':::I:
?'I" 0.7
D••

~c(

+vcc

UK
R34

09.

-LJ
~IQD.'
K:l'

007

2-

L

*oW;

DO~

0'0' L.. D.s

Oo'IJ

~;

D.,

oE
083

"'1

~

D~

R7
5.6K
0,.

a..

.... 0.,

!'li,.1~~r"
0,.
022~ ~

R.
2.0K

R35
UK

0.0

o..~

~~~ -

J,.I J ~.~

R,o
2.0K

L.....:
0.7

4 o.

ffi

VE

~.
rD.

w

~
O.8K

R,.
UK

UK

COMP

R"
10K

R,s
10K

R,.
10K

R,.
UK

R"
1.6K
DO

R..
OAK

01

Diagram Includes: One Input Stage, Decode Control, Bias Network, and Output Stag

3·169

·VE

HA-2406
Typical Applications

IN

2K
1K

500
500

11
Sample Charging Rate = CV Is
12
Hold Drift Rate = CV/S
Switch Pedestal Error =

§V

11 ~ 150 x 10-SA
12 ~ 200 x 10-9A at 25°C
~ 600 x 10- 9A at -55°C

~ 100 x 1O-9A at 125°C
Q ~ 2 x 1O- 12C

FIGURE 2. HA-2406 SAMPLE AND HOLD

FIGURE 1. HA-2406 AMPLIFIER, NONINVERTING
PROGRAMMABLE GAIN

For more examples, see Harris Application Note AN514.

3-170

HA-2406
Typical Performance Curves

---- --

60

0

I
I
I I
BIAS CURRENT

=:::::

*

~~

~~

""'II

0

~

:::: ..... ,.....

BANDWIDTH

t-...

""'
5

0

OFFSET CURRENT
I
I

o

o

25
50
TEMPERATURE (oC)

4.50

120

C

i!:

j:' 4.25

C3 80

z

a:
a:

I'-

:::>

o

~

"'
i'--

4.0

"":::>

Ul

Cl

~

"

Vs=±20V
Vs =±15V
" VS=±10V

§!
"0

9

0

z

"0

o

25
50
TEMPERATURE (oC)

75

FIGURE 5. POWER SUPPLY CURRENT vs TEMPERATURE

~

z

:;(

100
80

Cl
LIJ

Cl

60

§!

40

~

"0
0

....

~

.. :::~ ~"
"", ...." ~~
...." ~~

I

~

100pF
300p~/
l000pF

20

:"~

~.
~

0
-20
10

40
20

~~

~~

~"

100

lK

0

CCOMP= OpF
• • • CCOMP = 15pF

-20
10

I 1111 I IIII I 11
100

lK

iii
LIJ

60

"

LIJ

a:

"'"

r,

~'
~

I( r· ~

lliti

10K
lOOK
1M
FREQUENCY (Hz)

PHASE 90 Cl
LIJ

II

./
~

,~
10M

e.
120
LIJ
Ul
c(

:z:

150 "180
210
100M

1.2

'!H

J2
5l

lpll

1.1

il

1/15pF
30pF

M:!
~

"f:::~

" t'oo'"

Z

LIJ

"-

0

"

60

.J

-I~.L--

FIGURE 13. SLEW RATE AND TRANSIENT RESPONSE

3-172

HA-2444
Features

Description

• Digital Selection of Input Channel

The HA-2444 is a channel-selectable video op amp
consisting of four differential inputs, a single-ended output,
and digital control circuitry allowing two digital inputs to
activate one of the four differential inputs. The HA-2444 also
includes a high impedance output state allowing the outputs
of multiple HA-2444s to be wire-OR'd. Functionally, the
HA-2444 is equivalent to four wideband video op amps and
a wideband multiplexer.

• Unity Gain Stability
• Gain Flatness to 10MHz......•..••.•.....••. 0.1dB
• Differential Gain ........................... 0.03%
• Differential Phase...•••............•• 0.03 Degrees
• Fast Channel Selection .•.•.••••....•.•••.••• 60ns
• Crosstalk Rejection ••••....••...••••.•.•.... 60dB

Unlike similar competitor devices, the HA-2444 is not
restricted to multiplexing. Any op amp configuration can be
used with any of the inputs. Signal amplification, addition,
integration, and more can be put under digital control with
broadcast quality performance.

Applications
• Video Multiplexer
• Programmable Gain Amplifier
• Special Effects Processors
• Video Distribution Systems
• Heads-up/Night Vision Displays
• Medical Imaging Systems
• Radar Video

Ordering Information
PART NUMBER

TEMP.
RANGE (oC)

PACKAGE

PKG.
NO.

HA3-2444-5

Ot075

16 Ld PDIP

E16.3

HA3-2444-9

-40 to 85

16Ld PDIP

E16.3

HA9P2444-5

Ot075

16 Ld sOle

M16.3

HA9P2444-9

-40 to 85

16 LdSOIC

M16.3

The key video parameters of the HA-2444 have been
optimized without compromising DC performance. Gain
Flatness to 10MHz is only 0.1 dB. Differential gain and phase
are typically 0.03% and 0.03 degrees, respectively. Laser
trimming allows offset voltages in the 4.0mV range and a
unique common current source deSign assures minimal
channel-to-channel mismatch, while maintaining 60dB of
crosstalk rejection at SMHz. Open loop gain of 76dB and low
input offset and bias currents enhance the performance of
this versatile device.
For information about military grade devices, please refer to
the HA-2444/883 data sheet.

' 0'Peratlon
L oglc

Pinout
HA-2444
(POIP, SOIC)
TOP VIEW

TRUTH TABLE
EN

01

DO

SELECTED
CHANNEL

H

L

L

1

H

L

H

2

H

H

L

3

H

H

H

4

L

X

X

NONE-OUT is set to a high
impedance state.

L = Low State (O.BV Max)
H = High State (2.4V Min)
X = Don't Care

CAUTION: These devices Bre sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © HarriS Corporation 1996

3-173

File Number

2490.6

HA-2S00, HA-2S02,
HA-2S0S

1m HARRIS
(.KJ

SE M ICON 0 U C TOR

12MHz, High Input Impedance,
Operational Amplifiers

November 1996

Description

Features
• Slew Rate •......•••...•..•....•.....••..

30V/~

• Fast Settling •..•...•••.......•......••...• 330ns
• Full Power Bandwidth •••...•.....•....••.. 500kHz
• Gain Bandwidth .••.•••.•.••..•••.••.•.•.. 12MHz
• High Input Impedance ••....••..•.....•....• SOMa
• Low Offset Current .••••...•.....•••..••.... 10nA
• Internally Compensated For Unity Gain Stability

Applications
• Data Acquisition Systems
• RF Amplifiers
• Video Amplifiers
• Signal Generators

Ordering Information
PART
NUMBER

TEMP
RANGE (DC)

PACKAGE

PKG. NO.

HA2-2500-2

-5510125

B Pin Metal Can

T8.C

HA2-2502-2

-5510125

B Pin Metal Can

TB.C

HA2-2505-5

010 75

B Pin Metal Can

TB.C

HA3-2505-5

01075

B Ld PDIP

EB.3

HA7-2500-2

-5510125

B LdCERDIP

FB.3A

HA7-2505-5

01075

B Ld CERDIP

FB.3A

HA-2500, HA-2502, HA-2505 comprises a series of
operational amplifiers whose designs are optimized to
deliver excellent slew rate, bandwidth, and settling time
specifications. The outstanding dynamic features of this
internally compensated device are complemented with low
offset voltage and offset cu rrent.
These dielectrically isolated amplifiers are ideally suited for
applications such as data acquisition, RF, video, and pulse
conditioning circuits. Slew rates of ±30V/jls and 330ns
(0.1 %) settling time make these devices excellent
components in fast, accurate data acquisition and pulse
amplification designs. 12MHz small signal bandwidth and
500kHz power bandwidth make these devices well suited to
RF and video applications. With 2mV typical offset voltage
plus offset trim capability and 10nA offset current, HA-2500,
HA-2502, HA-2505 are particularly useful components in
signal conditioning designs.
The gain and offset voltage figures of the HA-2500 series
are optimized by internal component value changes while
the similar design of the HA-2510 series is maximized for
slew rate.
.
MIL-STD-883 product and data sheets are available upon
request.

Pinouts
HA·2500102 (CERDIP)
HA·2505 (PDIP, CDIP)
TOP VIEW

HA-2500102I05
(METAL CAN)
TOP VIEW
COMP

v-

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-174

File Number

2890.2

HA-2500, HA-2502, HA-2505
Absolute Maximum Ratings

Thermal Information

Supply Voltage Between V+ and V- Terminals .............. 40V
Differential Input Voltage ............................... 15V
Peak Output Current. ................................ SOmA

Thermal Resistance (Typical, Note 1)
8JA (oCfIN) 8JC (oCfIN)
Metal Can Package. . . . . . . . . . . . . . .
165
80
96
N/A
PDIP Package. . . . . . . . . . . . . . . . . . .
CERDIP Package. . . . . . . . . . . . . . . .
135
50
Maximum Junction Temperature (Hermetic Package) ........ 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300°C

Operating Conditions
Temperature Range
HA-2500/2502-2 . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to 125°C
HA-2505-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 75°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification ;5 not implied.

NOTE:
1. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Vs = ±15V

PARAMETER

TEMP
(DC)

HA-2500-2
MIN

HA-2502-2

TVP

MAX

25

2

5

Full

-

8

MIN

TVP

HA-2505-5
MAX

MIN

TVP

MAX

UNITS

INPUT CHARACTERISTICS
Offset Voltage

Offset Voltage Average Drift

Full

20

-

Bias Current

25

100

200

Full
Offset Current

400

25

10

Full

25
50

Input Resistance (Note 2)

25

25

Common Mode Range

Full

±10

--

25

20

30

50

-

4

4

8
10

20

-

125

250

-

500

20

50
100

-

-

-

20

50

20

±10

-

±10

15

25

15

8

mV

10

mV

Full

15

-

10

Common Mode Rejection Ratio
(Note 4)

Full

80

90

74

-

IlVPC

125

250

nA

!;t::i

-

500

nA

~CC

20

50

nA

100

nA
MQ

50

-

V

kVN

90

-

Gain Bandwidth Product (Note 5)

25

12

-

12

-

MHz

-

25

10
90

-

74

12

kVN
dB

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)

Full

±10

±12

±10

±12

±10

±12

Output Current (Note 6)

25

±10

±20

±10

±20

±10

±20

V

Full Power Bandwidth (Notes 6, 11)

25

350

500

300

500

300

500

-

kHz

-

25

50

-

25

50

25

50

ns

25

40

25

50

25

50

%

-

±30

-

V/flS

0.33

-

flS

mA

TRANSIENT RESPONSE
Rise Time (Notes 3, 7, 8, 9)

25

Overshoot (Notes 3, 7, 8,9)

25

Slew Rate (Notes 3, 7, 9,12)

25

±25

±30

±20

±30

Settling Time to 0.1 %
(Notes 3,7,9,12)

25

-

0.33

-

0.33

3-175

±20

CCtJ)

20

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 3, 6)

..I

Za:
O!!!
-II.
a: a..

W:E

HA-2S00, HA-2S02, HA-2S0S
Electrical Specifications

Vs = ±15V (Continued)
HA-2S()()'2
TEMP
(oC)

PARAMETER

HA-2502-2

MIN

TYP

MAX

4

6

80

90

-

HA-2S0S-5

MIN

TYP

MAX

4

6

74

90

-

MIN

TYP

MAX

UNITS

-

4

6

mA

74

90

-

dB

POWER SUPPLY CHARACTERISTICS
Supply Current

25

PSRR (Note 10)

Full

NOTES:
2. This parameter value is based on design calculations.
3. RL

=2kQ.

4. VCM = ±1 OV.
5. Av> 10.
6. Vo=±10V.
7. CL=50pF.
8. Vo = ±200mV.
9. See Transient Response Test Circuits and Waveforms.

10. tN=±5V.
11. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = Slew Rate/2ltVpEAK'
12. VOUT=±5V.

Test Circuits and Waveforms
INPUT .J+SV

-5V
OUT:: :

+

L

io~:':'
-- --~ f toV
~ : . : - .- - -

J_ _

5V - - .!D!o_ -..!
_ , SLEW
- - - I , tot 'RATE
"
'=toVltot
I

I

i

J

L

200
+
INPUT
OmV

OVERSHOOT

,ERROR BAND
,±10mV FROM
,FINAL VALUE
,

+200mV - - 90% - -

I

,,
,
...-, ,-+- RISE TIME

OmV

: _ SETTLING
~
TIME
......'

NOTE: Measured on both positive and negative transitions from OV to +200mv and OV to -200mV at the output.
FIGURE 1. SLEW RATE AND SETTLING TIME

FIGURE 2. TRANSIENT RESPONSE

/

-

V
=

NOTE: Measured on both positive and negative transitions from OV
to +200mv and OV to -200mV at the output.

RL = 21<0, CL 50pF
Upper Trace: Input
Lower Trace: Output

'\..

'\.

I'"'

=

Vertical 5V/Div.
Horizontal = 200nsIDiv.
TA '= 250 C, Vs = ±15V

FIGURE 4. VOLTAGE FOLLOWER PULSE RESPONSE

FIGURE 3. SLEW RATE AND TRANSIENT RESPONSE

3-176

HA-2S00, HA-2S02, HA-2S0S

Test Circuits and Waveforms

(Continued)

v+
INPUT

2kn

5kO

IN

OUT

13. AV=-1.
14. Feedback and Summing Resistor Ratios should be 0.1 %
matched.

NOTE: Tested offset adjustment range is 1VOS + 1mVI minimum
referred to output. Typical ranges are ±6mV with AT = 20kO.

15. Clipping Diodes CRI and CR2 are optional. HP5082-2810
recommended.

...I

ctll)

FIGURE 5. SETTLING TIME TEST CIRCUIT

FIGURE 6. SUGGESTED Vos ADJUSTMENT AND COMPENSATION HOOK UP

Schematic

Za:
O!!:!
-LL

!ci::J
a: a..
W:E

~ct

BAL

BAL

v+
R5
200

Ql~r

Q2~'

o.c~~

R2
2K
R3
960

Ra
200

R7 RIO
1.8K

Rll
2K

~.&K

Rl
4K

f-

Q3~r

R6
R9
200 200

;-'

Q6

'III

.....

Q&
III

Ql0",

'"""

'" Q16

I'll

~Q5
.,.Q7

C2
10.6P

FT

Q~

'"

R12
1.1K

'"

Ql1

Cl
10pF

~~Q14

I'&Q12 Q1I

I

'101 Io' Q17

.....

n

~

COMP

1'.13K

K

o.co)-

Q37

+IN PUT
III

Q38
800

--,.,Q35

R25
"Q29

Q39r
800

J

R26
"'IQ28
" Q26

fr.
C

'Q30

R20
3.3K

rQ31

Q33 ....

Q3!1

R23J_-

12 ~
~ l(

~ ffl
a: ::I
ifC :>'~

1.0

~

r

0.9

-

. /~

~~ :::::

120

r-

100

r-

:cCl 80 ....
"Ii;
z

~

w

Cl

~

60

...0
0
...
zw
...
0

40

~

I

If

0.8
10

10K

lOOK

1M

10M

100M

FIGURE 10. OPEN LOOP FREQUENCY AND PHASE
RESPONSE

~

./

SLEW RATE -

~

lK

FREQUENCY (Hz)

FIGURE 9. NORMALIZED AC PARAMETERS VB TEMPERATURE

1.1

i

40

zw

::Ii
a:

ifi

60

0

I!;j~

PHASE

~
!:i
~

SLEW RATE

c:>' 0.9

~

1 MHz

o

w

"'w
a:::I

100kHz

"'"'"

FIGURE 8. EQUIVALENT INPUT NOISE VB BANDWIDTH
(WITH 10Hz HIGH PASS FILTER)

W
II:

ffi\I.

SE

1°~ ~~~lm-oR I

FREQUENCY (Hz)

FIGURE 7. INPUT BIAS AND OFFSET CURRENT vs
TEMPERATURE

W

~

"

.... ""

0.1
1ooHz

125

......
THE Fli

TEMPERATURE (oC)

c

~

~~

1.0

~
5

~

100

;r"

;.~

10

~

OFFSET CURRENT

·20
-40

w

z~

SUPPLY VOLTAGE (±V)

FIGURE 11. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE
.

~
I-

20

300pF
1000pF

0

"'"11

·20
10
15

~~

1111111
I~~FII
30pF
100pF

~
""

1"'0

i'

i'

~

~
~

1111111
100

~

lK

10K

lOOK

1M

~
10M

100M

FREQUENCY (Hz)

20

NOTE: External compensation components are not required for
stability, but may be added to reduce bandwidth if desired.
FIGURE 12. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

3·178

HA-2S00, HA-2S02, HA-2S0S
Typical Performance Curves
I
I
VSUPPLY = ±20V ......

-

35

............

-

.......,

VSUPPLY = ±15V

VSUPPLy=+l~

90

Vs = ±lSV, TA = 25°C, Unless Otherwise Specified (Continued)

~

~? ~ /

~

30

CJ

25

....

1111

II~

~

z

~



~

10

::>
0

5

111111111

VSUPPLY = ±2OV

~

VSUPPLY = ±lOV

\ I'

I!:

o

80
-50

-25

0

25

50

75

100

125

10K

lOOK

lMEG

10MEG

FREQUENCY (Hz)

TEMPERATURE (DC)

FIGURE 13. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE

FIGURE 14. OUTPUT VOLTAGE SWING

VB

FREQUENCY

5
..J

cern
za:
O!:!:!

-IL
VSUPPLY = ±20V .....

I--

VSUPPLY =±15V ...........

I - - VSUPPLY = +lOV ......

-........

.......

~

~

..:::::;;; ~

-

3
-50

-25

0

25

50

75

100

125

TEMPERATURE (oC)

FIGURE 15. POWER SUPPLY CURRENT vs TEMPERATURE

3-179

!ci::::J
a: a.
W:::E

~ce

HA-2S00, HA-2S02, HA-2S0S

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

57 mils x 65 mils x 19 mils
1450~m x 1650~m x 483~m

Unbiased
TRANSISTOR COUNT:

METALLIZATION:

40

Type: AI, 1% Cu
Thickness: 16kA ± 2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ± 2kA
Nitride Thickness: 3.5kA ± 1.5kA

Metallization Mask Layout
HA-2500, HA-2502
+IN

BAL

-IN

COMP

v-

v+

3-180

HA-2510, HA-2512,
HA-2515

HARRIS
SEMICONDUCTOR

12MHz, High Input Impedance,
Operational Amplifiers

November 1996

Features

Description

• Slew Rate ..........•...............•••.. 60V/~s

HA-251 0/12115 are a series of high performance operational
amplifiers which set the standards for maximum slew rate,
highest accuracy and widest bandwidths for internally compensated devices. In addition to excellent dynamic characteristics, these dielectrically isolated amplifiers also offer low
offset current and high input impedance.

• Fast Settling ••..•...•........•.......•.... 250ns
• Full Power Bandwidth •.•......•.•....•••..• 1 MHz
• Gain Bandwidth •••••••••••••••••••••••••• 12MHz
• High Input Impedance ••..••.....•.....•.•. l00Mn
• Low Offset Current ••••..•••..•••..•.••...•• 10nA
• Internally Compensated for Unity Gain Stability

Applications

The ±6OVI~ slew rate and 250ns (0.1 %) settling time of these
amplifiers is ideally suited for high speed D/A, AID, and pulse
amplification designs. HA-2510/12115's superior 12MHz gain
bandwidth and 1000kHz power bandwidth is extremely useful
in RF and video applications. For accurate signal conditioning
these amplifiers also provide 10nA offset current, coupled w~h
100Mn input impedance, and offset trim capabil~.
MIL-STD-883 product and data sheets available upon request.

• Data AcquiSition Systems
• RF Amplifiers

....I
10.

6. Vo=±10V.
7. CL = 50pF.
8. Vo = ±200mV.
9. See Transient Response Test Circuits and Waveforms.
10.IN=±5V.
11. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = Slew Rate/2"VpEAK'
12. VOUT = ±5V.

..oJ
«If)

Za:
O!!!
-IL

Test Circuits and Waveforms
+5V

r----------.L

+~0:J

INPUT]
-5V
+5V - - - - - - -It...._ _..-.~-..-....- ...-..
~
.....
-~

INPUT

+

- 90% - - -

OUTPUT
-5V :

10%

•

I

t

~
i!.v

=: ~ -,.::.3 SLEW

, At I RATE.
: =AVlt.t

+~-

OmV

"'

OVERSHOOT

!fo'
:.?:F~~~
FINAL VALUE

+200mV - - 90% ---

,.....,_iJII'_......._--- - - - - -

,
I

OUTPUT
10%

,
I

OmV

--',

__ SE:::;ri~NG_

L

:-- RISE TIME

NOTE: Measured on both positive and negative transitions from OV
to +200mV and OV to -200mV at the output.

NOTE: Measured on both positive and negative transitions from OV
to +200mV and OV to ,-200mV at the output.
.

FIGURE 1. SLEW RATE AND SETTLING TIME

FIGURE 2. TRANSIENT RESPONSE

I

v
NOTE: Measured on both positive and negative transitions from OV
to +200mV and OV to -200mV at the output.
FIGURE 3. SLEW RATE AND TRANSIENT RESPONSE

RL = 2k!l, CL = 50pF
Upper Trace: Input
Lower Trace: Output

Vertical = 5V/Div.
Horizontal = 200nS/Div.
TA = 25°C, Vs = ±15V

FI,GURE 4. VOLTAGE FOLLOWER PULSE RESPONSE

3-183

!ci:::J
a:c..
w::
~«

HA-2510, HA-2512, HA-2515
Test Circuits and Waveforms

INPUT

(Continued)

2kn

v+

5kn

5kn

IN

OUT

SETTLING TIME
TEST POINT
2kn

CR2
":'

'::"

NOTES:

13. Ay=-l.
14. Feedback and summing resistor ratios should be 0.1 % matched.
15. Clipping diodes CRl and CR2 are optional. HP5082-2810
recommended.

NOTE: Tested offset adjustment range is IVOS + 1mVI minimum
referred to output. Typical ranges are ±6mV with Rr = 20kQ.

FIGURE 5. SETTLING TIME TEST CIRCUIT

FIGURE 6•. SUGGESTED Vos ADJUSTMENT AND
COMPENSATION HOOK UP

Schematic
BAL

BAL

3-184

HA-2510, HA-2512, HA-2515

Typical Performance Curves
4.4

100

4.2

80

~

C

So

4.0

!zW

VSUPPLY
3.8 - VSUPPLY
VSUPPLY

a:
a:

::>
(.)

~

a.
a.

....

3.6

::>

Ul

3.4

.s
!zW

i""""
~

-

a:
a:

(.)

20
0

3.2
-50

-25

-

40

::>

0
25
50
TEMPERATURE (oC)

75

100

-20

125

FIGURE 7. POWER SUPPLY CURRENT vs TEMPERATURE

-50

1.1

a:

W

10

0
Z

E!OtSOURC~';'~~'"T'''''''
"""." '''''''''.

I-

::>

a.

!:
I-

Z

...W
~
5

....

fa

,~

0.1
100Hz

1kHz

iii"
:!:!.
z
;(
c:J

100
80

Ii!j

60

~

40

a.
0
0

...

THERMAL NOISE
OF 10K RESISTOR

II

I

I I I 111111

a.

«CI)

Zit:

SLEW RATE

-- ~ ~

-50

lMHz

-25

0

25

75

100

125

FIGURE 10. NORMALIZED AC PARAMETERS vs
TEMPERATURE

1.1

>

LEJRATEI_

Ul'"

iii"

1U!c

90 a:

~!!I

60

W
W

PHASE

iii

B

i'

120 ~

::c

150 II.

i'

::IEUl

If~
1iIj2
!:I iii
~a:

1.0
BANDWIDTH

..;~
0.9

~~

"

r-r

I

BANDWIDTH-

SLEW RATE

~

a: a:

OW

180
10K
lOOK
1M
FREQUENCY (Hz)

50

TEMPERATURE (OC)

ffi+i

lK

"

0.8

100kHz

~

100

.J

=

0
-20
10

125

I I

1-

II ""

10kHz
FREQUENCY (Hz)

~

100

.=

30

20

75

~

0

Z
W

0

0
25
50
TEMPERATURE (oC)

BANDWIDTH

rn.J~

W

-25

SLEW RATE

FIGURE 9. EQUIVALENT INPUT NOISE vs BANDWIDTH
(WITH 10Hz HIGH PASS FILTER)

120

..........

..,

".

1.0

...

-

........... ~T1URREi

;-"R:

en::E
!II

r"

FIGURE 8. INPUT BIAS AND OFFSET CURRENT vs
TEMPERATURE

100

~

BIAS CURRENT

1"'--....

60

C

~V

=±20V -..
/.
=±15V r--...
=±10V ...... l:;? ~ ~ ",.

--- -

....

10M

z:li
a:
0.8
±10

100M

FIGURE 11. OPEN LOOP GAIN AND PHASE RESPONSE

±15
SUPPLY VOLTAGE (V)

FIGURE 12. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE AT 250 C

3-185

±20

O!!!
-II.

ti:::i

1t:Q.

W:i
~«

HA-2510, HA-2512, HA-2515
Typical Performance Curves
120

~

C(
Cl

80

Cl

60

~

w

~

§2
~

g
z

1'-0
1'-0

40

i!Io

20 f-- 300p~~
1000pF

W

~

~
~

o

-20
10

~
80

1K

""

10K
100K
FREQUENCY (Hz)

~

r"I

1M

10M

I-fIi: 30
d.
25
20

w

15

I::l

10

!:i0

5

§2

-50

o

-25

fo"""'"

25

50

75

100

125

FIGURE 14_ OPEN LOOP VOLTAGE GAIN vs TEMPERATURE

1111

111111

~UPPLY

= ±20V

TA

= 25°C

VSUPPLY = ±15V

"""

Cl

~

--

~~

~~ ~P
.. v" V
L

11111

;::.
z

+10V~

TEMPERATURE (oC)

35

Cl

VSUPPLY

75
100M

FIGURE 13- OPEN LOOP GAIN RESPONSE FOR VARIOUS
VALUES OF CAPACITORS FROM COMPENSATION
PIN TO GROUND

iIII

±20V ......

~

r-.
r-.

11111111
100

85

~
~
~

I =l

VSUPPLY

I- VSUPPLY =±15V ......

30pF
100pF

roo.

111111111

Q.

90

l~

iil100

z

(Continued)

VSUPPLY = ±10V

."'"'''' -'

Q.

I'I'll

o
10K

100K

1MEG
10MEG
FREQUENCY (Hz)

FIGURE 15. OUTPUT VOLTAGE SWING vs FREQUENCY

3-186

HA-2510, HA-2512, HA-2515
Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

65 mils x 57 mils x 19 mils
1650llm x 1450llm x 4831lm

Unbiased
TRANSISTOR COUNT:

METALUZATION:
Type: AI, 1% Cu
Thickness: 16kA

40
PROCESS:

±2kA

Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-2510, HA-2512, HA-2515

+IN

-IN

BAL

..I
«I/)
za:

O!!:!

-LL
COMP

tc::::i

a: a.

W:1E

~«

v-

v+
BAL

3-187

OUT

HA-2520, HA-2522,
HA-2525

aD HARRIS
WJ SEMICONDUCTOR
November 1996

20M Hz, High Slew Rate, Uncompensated,
High Input Impedance, Operational Amplifiers

Features

Description

• High Slew Rate .......................... 120VlllS

HA-25201252212525 comprise a series of operational amplifiers
delivering an unsurpassed combination of specifications for
slew rate, bandwidth and settling time. These dielectrically
isolated amplifiers are controlled at close loop gains greater
than 3 without external compensation. In addition, these high
performance components also provide low offset current and
high input impedance.

• Fast Settling ••••••••...••.•.•..••.••••••.• 2oons
• Full Power Bandwidth ...................... 2MHz
• Gain Bandwidth (Av ~ 3) ................... 20MHz
• High Input Impedance ..••••....••.•..•••.• 100Mn
• Low Offset Current •••••.•....•.•..•.•...••• 10nA

Applications
• Data Acquisition Systems
• RF Amplifiers
• Video AmplHiers
• Signal Generators
• Pulse Amplification

120VlJ.lS slew rate and 200ns (0.2%) seWing time of these
amplifiers make them ideal components for pulse amplification
and data acquisition designs. These devices are valuable
components for RF and video circuitry requiring up to 20MHz
gain bandwidth and 2MHz power bandwidth. For accurate signal
conditioning designs the HA-252012522/2525's superior dynamic
specifications are complemented by 10nA offset current, l00Mn
input impedance and offset trim capability. MIL-STD-883 product
and data sheets are available upon request.

Ordering Information
PART NUMBER
(BRAND)
HA2·2520-2
HA2-2522-2
HA2·2525-5
HA3-2525-5
HA4P2525-5
HA7-2520-2
HA7-2522-2
HA7-2525·5
HA9P2525·5
(H25255)

TEMP.
RANGE ("C)
-5510125
-5510125
01075
010 75
010 75
-5510125
-5510125
01075
010 75

PACKAGE
B Pin Metal Can
B Pin Metal Can
B Pin Metal Can
B Ld PDIP
20 Ld PLCC
BLdCERDIP
BLdCERDIP
BLdCERDIP
B LdSOIC

PKG.
NO.
TB.C
TB.C
TB.C
EB.3
N20.35
FB.3A
FB.3A
FB.3A
MB.15

Pinouts
HA-2520/22 (CERDIP)
HA-2525 (PDIP, CERDIP, SOl C)
TOP VIEW

HA-2520/22125
(METAL CAN)
TOP VIEW
COMP

HA-2525
(PLCC)
TOP VIEW
~

~

...

8
NC

v+
NC

OUT
NC

~

CAUTION: These devices are sensijive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyrlght @ Hams Corporation 1996

3-188

~ ~

~

File Number

2894.2

HA-2520, HA-2522, HA-2525
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V- Terminals) ............. 40V
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50mA

Thermal Resistance (Typical, Note 1)
8JA (oCIW) 8JC (oCIW)
Metal Can Package. . . . . . . . . . . . . . .
165
BO
PDIP Package. . . . . . . . . . . . . . . . . . .
96
N/A
CERDIP Package............ ... .
135
50
PLCC Package................ ..
74
N/A
SOIC Package...................
157
N/A
Maximum Junction Temperature (Hermetic Packages) . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range .......... -650 C to 150°C
Maximum Lead Temperature (Soldering 10s) ............ 300°C
(SOIC and PLCC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-2520/2522-2. . . . . . . . . . . . . . . . . . . . . . . .. -550 C to 125°C
HA-2525-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 75°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those Indicated in the operational sections of this specification is not implied.

NOTE:
1. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLy=±15V

PARAMETER

TEMP
(DC)

HA-2520-2

I

MIN

TYP

HA-2522-2
MAX

MIN

HA-2525-5

TYP

MAX

5

10

-

14

MIN

TYP

MAX

UNITS

5

10

mV

..J

-

14

mV

INPUT CHARACTERISTICS
25

-

4

B

Full

-

-

11

Offset Voltage Drift

Full

-

20

-

25

-

30

Bias Current

25

100

200

125

250

125

Full

-

400

-

500

20

Offset Voltage

Offset Current

25

-

10

25

Full

-

-

50

Input Resistance (Note 2)

25

50

100

40

Common Mode Range

Full

±10.0

-

±10.0

15

7.5

15

5

-

-

JlVPC
250

nA

a:1l.

500

nA

~c(

nA

50

20

50

100

-

100

100

nA
Mn

40

100

±10.0

-

-

V

7.5

15

-

kVN

5

-

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Notes 3, 6)

25

10

Full

7.5

Common Mode Rejection Ratio
(Note 4)

Full

BO

90

74

90

74

90

Gain Bandwidth (Notes 2, 5)

25

10

20

10

20

10

20

MHz

Minimum Stable Gain

25

3

-

3

3

-

VN

Output Voltage Swing (Note 3)

Full

±10.0

±12.0

±10.0

±12.0

±10.0

±12.0

V

Output Current (Note 6)

25

±10

±20

±10

±20

±10

±20

mA

Full Power Bandwidth
(Notes 6, 11)

25

1.5

2.0

1.2

2.0

1.2

2.0

-

MHz

-

25

50

-

25

50

ns

25

50

25

50

%

±80

±120

±120

-

V/jJ.S

--

kVN

-

dB

OUTPUT CHARACTERISTICS

-

-

TRANSIENT RESPONSE ("",=+3)
Rise Time (Notes 3,7, B, 10)

25

25

50

Overshoot (Notes 3,7,8, 10)

25

-

25

40

Slew Rate (Notes 3,7, 10, 12)

25

±100

±120

SetUing Time (Notes 3, 7, 10, 12)

25

-

0.20

0.20

3-189

-

±BO

0.20

c((/)

Za:
O!:!:!
-u...

JlS

!(i:::i
W:i:

HA-2520, HA-2522, HA-2525
Electrical Specifications

VSUPPLY = ±lSV (Continued)

PARAMETER

UNITS

Supply Current

mA

Power Supply Rejection Ratio (Note 9

dB

NOTES:
2. This parameter value is based on design calculations.
3. RL= 2kQ.
4.
S.
6.
7.
B.
9.
10.
11.

VCM=±10V.
Av> 10.
Va = ±1 O.OV.

CL= SOpF.
Va = ±200mV.
!N = ±S.OV.
See Transient Response Test Circuits and Waveforms.
Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = Slew Rate.
2ltV pEAK
12. VOUT = ±5V.

Test Circuits and Waveforms

+1~.67V

INPUT

L

±67:J
INPUT

-1.67V
'- _ _ _
+5V - - - - - - -.r.~_"""'",!"iiiioOi;.!i"_....
OUTPUT

-~: -

- -,

-5V: :: :: - - , - -, -

'

::

,

'

OVERSHOOT

90% - --

FINAL VALUE

=AVlAt:

,
SETTLING
,
,TIME - ,

L

±200mV - - -

-SLEW : ;fO~:F':o~

.... , At , - - RATE

,

OV

fw -r-

OV

I

--:

,,
I

:..... RISE TIME

NOTE: Measured on both positive and negative transitions from OV
to +200mV and OV to -200mV at the output.
FIGURE 2. TRANSIENT RESPONSE

FIGURE 1. SLEW RATE AND SETTLING TIME

INPUT

667.20

16670

IN
>---1~"""---"""--OOUT

999.90
...._ _....._ _ SETTLING TIME
TEST POINT

20000

NOTES:
13. Av=-3.
14. Feedback and summing resistor ratios should be 0.1 % matched.
lS. Clipping diodes CRl and CR2 are optional. HP50B2-2Bl0
recommended.
FIGURE 3. SLEW RATE AND TRANSIENT RESPONSE

FIGURE 4. SETTLING TIME TEST CIRCUIT

3-190

HA-2520, HA-2522, HA-2525

Test Circuits and Waveforms

(Continued)

v+

OUT

IN

NOTE: Tested offset adjustment range is 1Vas + 1mVI minimum referred to output. Typical ranges are ±20mV with RT = 20kO,
FIGURE 5. SUGGESTED Vos ADJUSTMENT AND COMPENSATION HOOK-UP

Schematic Diagram
OFFSETPIN 1

OFFSET+

BALl
200
R2AA

~, 030

~"029
Rll

R10

440

440

UK

c:ecn
Za:

O!!:!
-II..

oJ

L

~

04A('

,...,,04B

~c

!B~~

~J

R1A) R1B
r 024
,,"018

~"019
021A

025
R&A

05A
4 ) 022

..... 012A
R17

011B

02B

02& "1

Rg

~

'0138

I. 017

.,,020

08

r

02A

f?*:

~
r

~

R15

~c:e

...... 015
C1
lpF

1M

~~027

a:c..

W:::i

03B

03A

~:::i

R12

UK

R1&

+IN PUT

....I

R21

~01&

~,. 028

v+

200
R2BB

~

R13

COMP

BAL2

121B
R&B

~

R3A

-INPUT

3-191

'-..J

50

OUTPUT

~

012B

R18
30

~, °13A

t--K

09

0 5B

010

~R3B

~R18

011A

,014
R10

v-

HA-2520, HA-2522, HA.,2525

Typical Application
Inverting Unity Gain Circuit
Figure 6 shows a Compensation Circuit for an inverting unity
gain amplifier. The circuit was tested for functionality with supply voltages from ±4V to ±15V, and the performance as tested
was: Slew Rate", 120Vl!1s; Bandwidth", 10MHz; and Settling
Time (0.1%) '" 5OOns. Figure 7 illustrates the amplifier's frequency response, and it is important to note that capacitance
at pin 8 must be minimized for maximum bandwidth.

'" r~

2K

51--4-~HH#--+-I-H4H#--4-~~~~H
GAIN

m

i"

w

\

w

\

OUT

.~

10K

lOOK

1M

-180

10M

FIGURE 7. FREQUENCY RESPONSE FOR INVERTING UNITY
GAIN CIRCUIT

FIGURE 6. INVERTING UNITY GAIN CIRCUIT

Vs

CJ

e.

0

-10 1--4-~HH#--+-I-H4H#--4-~f-RII.H-'\-lIH -90 ~
:c
-15 ~~rrHH*--+~rHH*--~rrHH~~H -135 "-

=5K

Typical Performance Curves

a:

0~~++~~~~~~~d-~~~-1~
IL
-45 :E
-5 1--++++l+HI--+-H-++tHl PHASE
-~..,..#tfr--II-l
rn
1

HA-2520

5OOPF~

Cii"
w
w

10~~rrHH*--+~rHH*--~rrHH*-~H

~

10K

IN

151--4-~HH#--+~H4H#--4-~HH#-~H

=±15V, TA =25°C, Unless Otherwise Specified

~~:~.~~+-+-~I-~-I-+-+-+-~I-1-1-+-I-~~

~-1~1-~~~+-+-~-+-+-I-4-+-~-1-+-I-4-+-~
m_1~~'~~~I~Y-~~-+-r;-~~-+~+-~~
-140
-150

HH~~-+--+-+-+-IH-+--+--+--t-+-I-t-+--+---i
t-.ll/~-t--t-H-++-+--IH-++-+-l-++-+-I

-160_6L..0-'-_..J4O--L-_..L20-'-~01.....JL...2..10--L-4O:'::-J.....J6':-0--'-..J
80--'--1OLO--'-1..J2-'0

TEMPERATURE (oC)

TEMPERATURE I"C)

FIGURE 8. OFFSET VOLTAGE va TEMPERATURE (6 TYPICAL
UNITS FROM 3 LOTS)

i

!zw

30
20

a:
a: 10

:::)

0

rn

~
Iii

...o~

I'"

~

r-. r-. ~' ........

-.... ....

r- I"'-

0

-20

s;l>
~
....

i

....

-10
.....

FIGURE 9. BIAS CURRENT vs TEMPERATURE (6 TYPICAL
UNITS FROM 3 LOTS)

~

22
21
i"'""
20
~
19
I"jII'
l...o"
18
~
'7
17 ,.~
16
f,J
15
,,~
~
14
.,1
13
12
11
10 1'1
IJ
9
8

--

...."

....
~:;;iil"""

....

...

~·I"

7
~O'--'~--'--'---'-~~L..J~--'--'---'---'-~~L.....J-'

-eo

-40

-20

0

~

40

60

80

100

6
-eO

1~

TEMPERATURE (OC)
FIGURE 10. OFFSET CURRENT va TEMPERATURE (5 TYPICAL
UNITS FROM 3 LOTS)

-40

-20

0

20
40
60
TEMPERATURE (oC)

80

100

120

FIGURE 11. OPEN LOOP GAIN va TEMPERATURE (6 TYPICAL
UNITS FROM 3 LOTS)

3-192

HA-2520, HA-2522, HA-2525
Typical Performance Curves

Vs = ±15V, TA = 25°C, Unless Otherwise Specified (Continued)

-

50
40

C

30

tJ.

20

E

!zw
II:
II:

:;)

U
I-

:;)

"-

!;
a

10
0

,.,.

-

~~

-20

---

-30
6

3!i

-..

1000..

8

10

12

-- -

,.,.

4

w

SUPPLY VOLTAGE (±V)

!:l

2
0

!;

-2
-4

i,..o-'

i""'ooo.

1,...000'

-..

-6

A

-

i"""-o iooo.

14

4

6

8

10

FIGURE 13. OUTPUT VOLTAGE SWING

-550 C

100
80

iii
If

-

0

14

14

...

- ...

...

SUPPLY VOLTAGE (±V)

III

..J

c(C/)

Za::

....

O~

-II.

iii
w
w

...

II:

"e.w

0

...
"cz

w
-45

"

-90

III.

I II I:10K
I I100K

100

SUPPLY VOLTAGE

vOPEN LOOP GAIN

OPEN LOOP PHASE

12

VB

1111

40

20

8

I

.iill I

!60
GUlt~~J~~
3!i
" P~AU ~T l ~ ~OO
C

10

......

12

SUPPLY VOLTAGE (±V)

25°C

8

...... ....

-10
-12

125°C

6

-"" I"""

-"" I"""

i""'ooo

S -8

FIGURE 12. OUTPUT CURRENT vs SUPPLY VOLTAGE

5.4
5.2
5.0
C 4.8
E 4.6
;- 4.4
4.2
4.0
II
3.8
II
> 3.6 fl
~ 3.4
!!; 3.2 'I1
til 3.0
2.8
2.6
2.4
4

8
6

~

-40
4

c;

~

i""""-

RL = 2k!l

~ 10

~

-.. i"'--

-10

i,..o-' ."""

14
12

1M

1K

w
-135 ~

~

10M

:z:

-180 "-

100M

FREQUENCY (Hz)

FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 15. FREQUENCY RESPONSE

f

100

1000
500

:5-

.....

....

w 100

'""' '""'

"CURRENT
INPUT
NOISEI"
I" """"
"""

~111I1ll

!:l 50
~

INPUT NOISE

VO~~~rr;;:

w

~
~

10

l"'R:I:IIIII..

~

!!l

50

5

U

10

1

1

10

100

1K

10K

0.1
100K

FREQUENCY (Hz)

FIGURE 16. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM COMP
PIN TO GROUND

3-193

w

!!l

a

0.5~
~
3!i

5

1

~

!z
II!
II:
:;)

h

3!i

FREQUENCY (Hz)

il

FIGURE 17. INPUT NOISE CHARACTERISTICS

~:::i
a::c.

w:=
~c(

HA-2520, HA-2522, HA-2525

Typical Performance Curves

Vs

= ±lSV. TA = 25°C. Unless Otherwise Specified (Continued)

1.2

35

RL=2kn

VSUPPLY = ±20V

1
~

30

CI

25

!

20

III

CI

~

15

!:i

10

~

.' "" III.

VSUPPLY = ±15V

vLL~!~~tv

~
~

CL=50pF

1.0

II

'H

0.9

12
c

0.8

~

0.7

II:
0
Z

0.6

~

"'r\

IU

1.1

~I\

III

::&

S
0

o

10K

~

~

!? ~ "
~ ~ ~ NEGATIVE

",

a1NO'wIOTH

",~

~

I:::::i

l.I ~

V

SLEW RATE

POSITIVE
SLEW RATE

0.5

0.4
100K

1M

5

10M

FIGURE 18. OUTPUT VOLTAGE SWING vs FREQUENCY

7

9

11

13

15

17

19 20

SUPPLY VOLTAGE (±V)

FREQUENCY (Hz)

FIGURE 19. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE

3-194

HA-2520, HA-2522, HA-2525
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

67 mils x 57 mils x 19 mils
(1700~m x 1440~m x 483~m)

Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

METALLIZATION:
TRANSISTOR COUNT:

Type: AI, 1% Cu
Thickness: 16kA ±2kA

40

SUBSTRATE POTENTIAL:

PROCESS:

Unbiased

Bipolar Dielectric Isolation

Metallization Mask Layout
HA-2520, HA-2522, HA-2525

-I

-.......- - - 0
900n

OUT

NOTES:
11. V s :±15V.

loon

12. Av: +10.
13. CL " 10pF.

FIGURE 1. TEST CIRCUIT

A

B

Vertical Scale: A: 0.5V/Div., B: 5.0V/Div.
Horizontal Scale: 50nS/Div.

Vertical Scale: Input: 1OmV/Div., Output: 50mV/Div.
Horizontal Scale: 20ns/Div.

FIGURE 2. LARGE SIGNAL RESPONSE

FIGURE 3. SMALL SIGNAL RESPONSE

3-199

HA-2539
Test Circuits and Waveforms

(Continued)

NOTES:
14. Av

= -10.

15. Load Capacitance should be less than 1OpF.

200n

OUTPUT

INPUT

17. SETTLE POINT (Summing Node) capacitance should be less
than 10pF. For optimum seWing time results, it is recommended
that the test circuit be constructed direcHy onto the device pins.
A Tektronix 568 Sampling Oscilloscope with S-3A sampling
heads is recommended as a settle point monitor:

500n
2kr.l

SETTLE
POINT

16. It Is recommended that resistors be carbon composition and that
feedback and summing network ratios be matched to 0.1 %.

5kn

FIGURE 4. SETTLING TIME CIRCUIT

Schematic Diagram
~~~--.---~~--~--~~---.-------------------.-------.--~ v+

Rs

...---+---+-+--------~ Qp5

+INPUT

0-+--+--+--------+
OUTPUT

-INPUT

o-----t---t--------------+--t---+-----'

3-200

HA-2539
Typical Applications

SETAv=~
R,

FIGURE 5. FREQUENCY COMPENSATION BY OVERDAMPING

=-3

FIGURE 6. STABILIZATION USING ZIN

R5 1kfl
INPUT

-!-

R,

OUTPUT

-!FIGURE 7. REDUCING DC ERRORS; COMPOSITE AMPLIFIER

FIGURE 8. DIFFERENTIAL GAIN ERROR (3%) HA-2539 20dB
VIDEO GAIN BLOCK

Typical Performance Curves
14

7

12

6

.;; 10

5

RSOURCE

a::
a::

-

....

8

::::I
(J

III

6

...

4

:$

1-"V

OFFSET VOLTAGE

I

...

3

tu
III

C!I

BIAS CURRENT

0

~

2

-40

o

~

~

80

120

40

f.eo...
z

w
30 a::

a::

::::I
(J

20 w

~

~

5

Z

10

VOLTAGE NOISE

CURRENT NO ISE
1111

o
40

50

10

W

~Z

Vs = ±15V

'"

w 15

II.
II.

1!:

20

.s

~

2

-80

~>

~

........... J.

o

w

4

CD

::::I

.5.

C!I

~'~Q

~

:>

C

!zw

25

o

160

10

TEMPERATURE (OC)

111111111
100

I

111111
lK

10K

TI11

o

lOOK

FREQUENCY (Hz)

FIGURE 9. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs
TEMPERATURE

FIGURE 10. INPUT NOISE VOLTAGE AND NOISE CURRENT vs
FREQUENCY

3-201

HA-2539
Typical Performance Curves

(Continued)

JOO

80

iii'

~
II: 60
II:

""""'

:;;

0

...
r-....

40

r" ro-

20

Vertical Scale: 10mV/Div.
Horizontal Scale: 50ms/Div.

lK

FIGURE 11. BROADBAND NOISE (0.1 Hz TO 1MHz)

10K

lOOK
FREQUENCY (Hz)

100

Il~![

80

60

80

"

PHAS EI"oo

iii'
~

1::::=0

z

:;;:

!'iii roo

:~

=

lK

10K

lOOK
FREQUENCY (Hz)

1M

·20
100

10M

~

w

e.

135 ~

~

:x:
c.
180
225

lK

10K

28

.

iii' 80

0
0

iii

lOOK
1M
10M
FREQUENCY (Hz)

100M

~~~1~15~

±15V

90

II.

f§

90

FIGURE 14. OPEN LOOP GAIN/PHASE vs FREQUENCY

1111

Cl

w

o

100 I-Vs

z
:;;:

Vi
w

20

FIGURE 13. POWER SUPPLY REJECTION RATIO vs
FREQUENCY

~

45

r--

I""

40

20

o

o

Cl

I:::::

10M

FIGURE 12. COMMON MODE REJECTION RATIO vs
FREQUENCY

100

40

1M

24

:tw 20

70
60

Cl

50

~

~ 16

oJ

40
w
If)
30
0
oJ 20
0
0

~

5

8

Vs ~±5V

10K

lOOK

1M

10M

a

100M

FREQUENCY (Hz)

"-

lllllilL

4

·10
lK

.,

\

I-

0
100

~+10V

~ 12

~

10

Vs

IIIIIII
tK

10K

tOOK

1M

10M

100M

FREQUENCY (Hz)

FIGURE 15. CLOSED LOOP FREQUENCY RESPONSE

FIGURE 16. OUTPUT VOLTAGE SWING vs FREQUENCY

3·202

HA-2539
Typical Performance Curves

(Continued)

1.4
28

(,) 1.3
",0

'0:.
d..

24

Cl
Z

20



a

!:;

4



V

I

~~
c>

1.0

~I:!
::::;
c

0.9

......

-,

-'

SLEW RATE

..........

;]~
!5 ~ 0.8

II
o

I

1.2 ~ANDWIDTH

'"

ZW

a: 0.7

200

400

600

800

lK

0.6
-80

1.2K

o

-40

40

FIGURE 17. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE

a

fu

6
4
2

Iii
w

~

'-'
~

!:;
~

o

Y

/
10mV

"

0
-2
-4

./

"

,

/-lmv-

/

....I

«en
za:

Vs=±15V

~ 20
....
15a: 16

O!!:!
-u.

a

..

\.

!;;::::i

I

a:

I\, "-" l m V -

o

160

I

24

10mV ~

-6
-8
-10

120

FIGURE 18. NORMALIZED AC PARAMETERS vs TEMPERATURE

28
10
~

80

TEMPERATURE (OC)

RESISTANCE (il)

Vs =±5V

12

a:

a..
W:E

I

:5«

~

-

11. Av=+10.
12. CL :> 10pF.

FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT

I

I

-

I

I

I

B

m

t::J
~

~mv

I

Vs =±5V

8

III

l\.

120
160
80
SETTLING TIME (ns)

I

ce
ce

:::>

·2
-4

160

C
.§. 20

I

J

120

Vs=±15V _

24

/

w
CI

g'"'

/

o
40
80
TEMPERATURE (OC)

FIGURE 8. NORMALIZED AC PARAMETERS vs TEMPERATURE

,

10mv/

100M

1.3

~
8! 'ill

/'

12

10M

1.4

28

z

1M

FIGURE 6. OUTPUT VOLTAGE SWING vs FREQUENCY

12

CI

lOOK

FREQUENCY (Hz)

FIGURE 5. CLOSED LOOP FREQUENCY RESPONSE

~

..

11111111

o

100M

~

lSIH~~1
"'""'

II.

10K

-I-

Vs =±10V

16

w

,

-

·10
100

-

~
CI 20

I'

9 20 ~

28

4

200

FIGURE 9. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES

o

-80

240

-40

o

40
80
TEMPERATURE (OC)

120

160

FIGURE 10; POWER SUPPLY CURRENT VB TEMPERATURE

3·210

HA-2540
Typical Performance Curves

(Continued)

14
RSOURCE

12

:;-

OFFSET VOLTAGE

.....

20~

oS
UJ

/

~

~:>

tii

CI

CI

4

...........

3

..... i'o

~
III

IL
IL

BIAS CURRENT

2 0
"0
~

2

.s
UJ

~

~

-80

-40

o

40

80

120

I--~ ~URRENT NOISE

15

~<

40

,~

i

30

10~+-~~&-1-++t#ffi--r,,~~~-+++&m20 ~

UJ
III

VOLTAG:

il'ii

5
z

~

~

~

10
O'-...L...l....L.J....W."--'-.L..1..1...IJ.W--L...L.J...L.JJWL......J.-'....J...J...lJ.WO
10
100
lK
10K
100K

o

o

=on, Vs =±15

25~+-~H*&-~+++*~~~~~~-+++~50

160

TEMPERATURE (DC)

FREQUENCY (Hz)

FIGURE 11. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs
TEMPERATURE

FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs
FREQUENCY

Vs = ±15,

R'~'= 1K

120
100

iii" 80
a:
a:

:!!.
:;;
0

60

-I"-

40

20

-

r--- ..

o
lK

Vertical Scale: 10mV/Div.
Horizontal Scale: 50ms/Div.

iii"

100

80

80

-

a:

:ea:

40

iii"
z

«
CI

60

9

40

...0

POSITIVE SUPPLY

NEGATIVE SUPPLY

10M

....... =:

o

~

:!!.

r=== 1=::

1M

FIGURE 14. COMMON MODE REJECTION RATIO vs FREQUENCY

100

60

lOOK
FREQUENCY (Hz)

FIGURE 13_ BROADBAND NOISE (0.1 Hz TO lMHz)

:!!.

10K

45

GAIN

1'1.

ffi'

PHASE

UJ

90

UJ

z

...
0

135 ~

UJ

..."

20

20

~

o

lK

-10

10K

lOOK

1M

10M

FREQUENCY (Hz)

100

180
225

1K

10K

100K

1M

10M

100M

FREQUENCY (Hz)

FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREQUENCY

3-211

ffi

UJ

e.

FIGURE 16. OPEN LOOP GAIN/PHASE vs FREQUENCY

HA-2540

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

v-

62 mils x 76 mils x 19 mils
1575 J.lmx 1930J.lm x 4831lm

TRANSISTOR COUNT:

METALLIZATION:

30

Type: AI. 1% Cu
Thickness: 16kA ±2kA

PROCESS:

Bipolar Dielectric Isolation

PASSIVATION:

Type: Nitride (Si 3N4) over Silox (Si02 • 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-2540

v+

v·

OUTPUT

3-212

HA-2541
40MHz, Fast Settling,
Unity Gain Stable, Operational Amplifier

November 1996

Features

Description

• Unity Gain Bandwidth .........•....•...... 40MHz

The HA-2541 is the first unity gain stable monolithic
operational amplifier to achieve 40MHz unity gain bandwidth. A major addition to the Harris series of high speed.
wideband op amps, the HA-2541 is designed for video and
pulse applications requiring stable amplifier response at low
closed loop gains.

• High Slew Rate ..........•......•........ 250VlflS
• Low Offset Voltage •••••.•••...•.••.....•... 0.8mV
• Fast Settling Time (0.1%) .•................•. 90ns

• Power Bandwidth .•....•.•....•.•......•... 4MHz . The uniqueness of the HA-2541 is that its slew rate and bandwidth characteristics are specified at unity gain. Historically,
• Output Voltage Swing (Min) . . . . • . • . . . . • . • • •. HOV
high slew rate, wide bandwidth and unity gain stability have
been incompatible features for a monolithic operational ampli• Unity Gain Stability
fier. But features such as 250V/flS slew rate and 40MHz unity
• Monolithic Bipolar Dielectric Isolation Construction
gain bandwidth clearly show that this is not the case for the
HA-2541. These features, along with 90ns settling time to
Applications
0.1 %, make this product an excellent choice for high speed
data acquisition systems.
• Pulse and Video Amplifiers
MIL-STD-883 product and data sheets are available upon
• Wideband Amplifiers
request, Harris AnswerFAX (407-724-7800) document
#3698.
• High Speed Sample-Hold Circuits
• Fast, Precise DIA Converters
• High Speed AID Input Buffer
For a lower power version of this product, please see
the HA-2841 data sheet.

For further application suggestions on the HA-2541, please
refer to Application Note AN550 (Using the HA-2541), and
Application Note AN556 (Thermal Safe Operating Areas for
High Current Operational Amplifiers), Harris AnswerFAX
(407-724-7800) document #9550 and 9556. Also see 'Applications' in this data sheet.

Ordering Information
PART
NUMBER

TEMP.
RANGE (OC)

PACKAGE

PKG. NO.
F14.3

-55 to 125

14 LdCERDIP

HAl-2541-5

Ot075

14LdCERDIP

F14.3

HA2-2541-2

-55 to 125

12 Pin Metal Can

T12.C

HA2-2541-5

01075

12 Pin Melal Can

T12.C

HAl-2541-2

Pinouts
HAl-2541
(CERDIP)
TOP VIEW

HA2-2541

(METAL CAN)
TOP VIEW

V CASE

= v-

CAUTION: These devices are sensitive to eleclrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporetion 1996

3-213

+IN

File Number

2898.2

---I

C

35

IlA

50

-

-

±10

-

6

85

IlA
nAflC

1

7

IlA

-

9

IlA

100
1

kO

-

pF

±10

±11

-

10

nV/-.fHi

4

pAl-.fHi

V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

-

25

10

16

10

16

Full

5

-

5

-

Full

70

90

70

90

dB

25

1

1

-

VN

Vo=90mV

25

-

40

-

40

Output Voltage Swing

RL = 1kQ

Full

±10

±11

±10

±11

Output Current

RL = 1kQ

25

±10

±15

±10

±15

-

2

0

3

4

MHz

Common Mode Rejection Ratio

Vo =±10V

V CM =±10V

Minimum Stable Gain
Unity Gain Bandwidth

kVN
kVN

-

MHz

-

mA

OUTPUT CHARACTERISTICS

25

-

2

Vp = 10V

25

3

4

Differential Gain

Note 4

25

Differential Phase

Note 4

25

Output Resistance
Full Power Bandwidth (Note 3)

3-214

-

-

0.1

-

0.2

-

-

0.1
0.2

V

-

%
Degrees

HA-2541
Electrical Specifications

VSUPPLY = ±15V, RL = 1kn,

PARAMETER
Harmonic Distortion

TEST
CONDITIONS

c L <; 10pF. Unless Otherwise Specified
HA-2S41-2
-SSoC to 12SoC

TEMP

(0C)

Note 6

MIN

TYP

HA-2S41-S

aOc to 75°C

MAX

MIN

<0.01

25

(Continued)

TYP

MAX

UNITS

<0.01

%

ns

TRANSIENT RESPONSE (Note 5)
Rise Time

25

4

4

Overshoot

25

40

40

%

Slew Rate

25

250

V/~s

Settling Time

200

250

200

10V Step To 0.1%

25

90

90

ns

10VStepToO.Ol%

25

175

175

ns

25

29

POWER REQUIREMENTS
Supply Current

Full
Power Supply Rejection Ratio

V s =±5Vto±15V

29

Full

70

80

mA
40

40
70

78

mA
dB

NOTES:
3. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW =
4. Differential Gain and Phase are measured with a tV differential voltage at SMHz.

~~w Rate.
1t

PEAK
..J
c((f)

5. Refer to Test Circuits section of this data sheet.

Za:
o!!!
-1.1..
~::i
a: a..

6. f = 10kHz; Av = 5; Va" 14Vp_p.

Test Circuits and Waveforms

w:!:
~c(

r-_ _ _ _....._ ....._O~~~~ING
NOTES:
7. Vs = ±15V.

8. Av=+I.
9. CL " 10pF.
NOTES:

10. Av =-1.
11. Feedback and summing resistor ratios should be 0.1 % matched.
12. HPS082-2810 clipping diodes recommended.
13. Tektronix P6201 FET probe used at settling point.
FIGURE 1. TRANSIENT RESPONSE TEST CIRCUIT

FIGURE 2. SETTLING TIME TEST CIRCUIT

ov

ov

ov

ov
Vertical Scale: 5V/Div.
Horizontal Scale: SOnS/Div.

Vertical Scale: V'N = 1OOmV/Div., V auT = 50mV/Div.
Horizontal Scale: 20nS/Div.
SMALL SIGNAL RESPONSE

LARGE SIGNAL RESPONSE

3-215

HA-2541
Test Circuits and Waveforms

(Continued)

NOTES:
14. Vs=±15V. Rl = 1kQ.
15. TA = 25°C.

16. Propagation delay variance is
negligible over full temperature range.

Vertical Scale: 100mV/Div.
Horizontal Scale: 5ns/Div.

PROPAGATION DELAY

Schematic Diagram

Y

BALANCE

JcR,o

R',
JcQp,s
L

""""':!.

.......

Qp14

Qp13

R23

~,

J

QN••

'3JR,;)
R~7J 5K
R.B
Qp33
,s 5K
.....,
,/

r-..

Qps

Y BALANCE

.....,

v+

Qps~

Qp3.

IM{P7
Qp3'..;t-+-_~----t----t----II~""";":""--;::~

---

+IN

r

-IN

~,

I

>-0 V OUT

;-::-

'---+---I----+--I--+---+---+----\:r....~

QN3.

R••

Rs

R.o

'----~--~--~----~~-~--~---4_--~--4---_4--_4------4_--_4----~~

3-216

HA-2541

Typical Applications

(Also see Application Note AN550)

Application 1

Application 2

High power amplifiers and buffers are in use in a wide variety
of applications. Many times the "high power" capability is
needed to drive large capacitive loads as well as low value
resistive loads. In both cases the final driver stage is usually a
power transistor of some type, but because of their inherently
low gain, several stages of pre-drivers are often required. The
H~-2541, with its 10mA output rating, is powerful enough to
drive a power transistor without additional stages of current
amplification. This capability is well demonstrated with the
high power buffer circuit in Figure 3.

Video

The HA-2541 acts as the pre-driver to the output power
transistor. Together, they form a unity gain buffer with the
ability to drive three 50Q coaxial cables in parallel, each with
a capacitance of 2000pF. The total combined load is 16.6Q
and 6000pF capacitance.

One of the primary uses of the HA-2541 is in the area of
video applications. These applications include signal
construction, synchronization addition and removal, as well
as signal modification. A wide bandwidth device such as the
HA-2541 is well suited for use in this class of amplifier. This,
however, is a more involved group of applications than
ordinary amplifier applications since video signals contain
precise DC levels which must be retained.
The addition of a clamping circuit restores DC levels at the
output of an amplifier stage. The circuit shown in Figure 4
utilizes the HA-5320 sample and hold amplifier as the DC
clamp. Also shown is a 3.57MHz trap in series, which will
block the color burst portion of the video signal and allow the
DC level to be amplified and restored.

....I

C(I/)

za::
Ow

~§
a::

w::0.
~C(

LOAD 16.611; 6000pF
OR 12.50; 6000pF
FIGURE 4. VIDEO DC RESTORER

FIGURE 3. DRIVING POWER TRANSISTORS TO GAIN
ADDITIONAL CURRENT BOOSTING

Suggested Offset Voltage Adjustment

NOTE: Tested Offset Adjustment Range is IVos + 1mVI
minimum referred to output. Typical range is ±15mV for
RT= 5k.Q.

3-217

HA-2541
Typical Performance Curves
TA = 25°C. Vs

3.0

= +15V

2.5

>

§:

oS
UI
!;i

UI

u

z

10K

~

III
UI

a: 1000

I;
a.
~

100

.;;:- .....

2.0

lOOK

~
~

~
:!"

v-

!:i

~

Il'I'to..

Iii
II.

0

rn

0

IlII::::::

~.5

-1.5

- ......-r-..
....
.....
......... .........

r-r--

-2.5
10M

~

100M

~

0

~

FREQUENCY (Hz)

1000

~

,
.!!:

1 00

!ZUI
a:
a:

~

B
UI


ENI

~

i5

10

Z

I;

100

l....
z

UI

a:
a:
::)
U


:!!
III

~

INI

"'1""t
lK

10K

1
lOOK

I"19
18
17
16
I"15
14
13
......
12
11
10
9
8
i"'"
7
6
5
4
-60
~

I-- r- -s5"C
I-- r- +VOUT

..

2

..

E

0

·2
~ -4
:>

~

""""'"

~

·6
-8

.550 C
+VOUT

·10

I

-

·12
·14

5

7

~~

~"

~

~

-- - -

~

....

I:'l1o.

..... o::!!

~

.....

....

....

.......
-20

o

~

40

60

80

100

-

120

+IOUT I':::>

20

~~

125°C /"
+VOUT

11

....

-30

!""III
13

3

5

7

-

25°C
-lOUT -

\.

9

125°C
-lOUT

\

-...

·40

15

~

_55°C
-lOUT

-

0

-~

......; iI!Ii!!!!! ...

,~ ~

10

-10
o:!!III

~~

~ ~ ~ P'"

-SSoC

30

:>

~ I!!!!!!.

125°C
+IOUT ........

25°C
+loUT

40

.

9

~

I"

50

..!'

25°C I
+VOUT

~

60

~

oS

.,..

~

FIGURE 8. BIAS CURRENT VB TEMPERATURE
(6 REPRESENTATIVE UNITS)

C

.... ~ !!IIIo.

3

125°C
+VOUT \

25°C
+VOUT \
\

~

r--

TEMPERATURE ("C)

FIGURE 7. NOISE DENSITY VB FREQUENCY

I

~

""
".... ..... "

FREQUENCY (Hz)

6
4

r--

21
20

a.

i'

8

-.....r-

FIGURE 6. OFFSET VOLTAGE vs TEMPERATURE
(6 REPRESENTATIVE UNITS)

1000

f- ff- f- TA = 25°C

I

-- -

TEMPERATURE <"C)

FIGURE 5. INPUT RESISTANCE VB FREQUENCY

10

......... i'-.....

-3.0

1M

12

r-

..........

-2.0

1000

10

1.0
0.5

~ -1.0

9000

10
lOOK

1.5

11

13

SUPPLY VOLTAGE (±V)

SUPPLY VOLTAGE (±V)

FIGURE 9. OUTPUT VOLTAGE SWING VB SUPPLY VOLTAGE

FIGURE 10. OUTPUT CURRENT VB SUPPLY VOLTAGE

3·218

15

HA-2541
Typical Performance Curves

:it

30
28
26
24

(Continued)

1.2
1.1

IJI'

1.0

~

So

22
20
II: 18
II:
:::> 16

'7
f!
i--

~

I-

zw

/.

0

,~

I

~ 14
Il.
Il. 12
:::>
III 10
8
6
4

I

J :

.~

."
I

J'~

"

~

0.8

..I
III

0.7

w

125°C

25°C

..I
c(

::2

II:

-55°C

0

Z

I

I
I

II:
II:

III
Il.

0.3

VIN

~r/

~~
~

25°C

5

7

'.55 C _

-

I

11
9
SUPPLY VOLTAGE (±V)
7

13

15

~250C

"

-550 C f-+PSRR
_+PSRR
f--

Your

-=RL~CL

RL=2k!l
CL :510pF

I

L

L

I

9
11
SUPPLY VOLTAGE (±V)

i

I

13

15

FIGURE 12. SLEW RATE VB SUPPLY VOLTAGE
(NORMALIZED WITH Vs ±15V AT 25°C)

=

_

122
120
118
116
114
112
110

!8

108

,-

-125°C
f--+PSRR

~
+

V.

O

0.1

,.

~~
iii'
~ 82 f-- -

0.4

0.2

86

83

0.5

~,

n

w 0.6

til

87

84

125°C

C

FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE

85

II

II:

--

5

3

w
!;( 0.9

'--

f--

-

II

::2
0 104

25°C

102
100
98
96
94
92

....

76

~

-'

II:

....

-, -

125°C

~108

81 f-125°C
80 f-- -~ ·PSRR
79
·550C
S250C
78 r ·PSRR - r--·PSRR ~""'77

,

I

./

-""I'"

J'

I

./

~

·550C

~

"
./

........

,.
~

./
r-

90

7
9
11
SUPPLY VOLTAGE (±V)

5

3

13

15

11
7
9
SUPPLY VOLTAGE (±V)

5

3

FIGURE 13. PSRR VB SUPPLY VOLTAGE (AVERAGE OF 3 LOTS)

13

15

FIGURE 14. CMRR VB SUPPLY VOLTAGE (AVERAGE OF 3 LOTS)

20
Vs =±15V, RL = 2kn, TA = 25°C
120
100

~

60

19
18

llcJRRI

....

+PSRR

80

iii'

~

·PSRR

17

~

.;;;:-.

~

J

r--. ...

40

±AvoL AT TA;, 25°C

16

~

20

15
14

1"""'-

13

±AYOL AT TA = ·550C

12

11

o

10

..",

9

100

lK

10K
lOOK
FREQUENCY (Hz)

1M

FIGURE 15. REJECTION RATIOS VB FREQUENCY

.---

r-"

8

10M

8

10

12
SUPPLY VOLTAGE (±V)

14

FIGURE 16. OPEN LOOP GAIN vs SUPPLY VOLTAGE
(AVERAGE OF 3 LOTS)

3·219

..J

«(/)

Za:

OW

-u:::

!;::J
a:c.

W:iE

~«

HA-2541

Typical Performance Curves
100

80

iii' 80
!!.

~
CJ

40

20
0

i~

..

'I'

'I~
+~
~
..
~
ff· .. ~

iW r

"'

100

OPENLOOP_

1111 I I
lK

10K lOOK 1M
FREQUENCY (Hz)

Av=·100·........

GA,IN,

qfl

5

.\.
0

sE

..

0

~

,

90

ie.

45

W

I

o

180
135

10M 100M

Av=·10 ....

-

9
6

GAIN

iii'3

...zO

R~

..
. ..tOO.

-=Av +10
Vs = ±15V
T = 25°C
lK

10K

\I

-=

1111

1111111

I

°
TA =125 ~,
TA =250~"
TA = ·55OC

~-3

""""'!'III.

~o

I,,\! .45
90

-6
PHASE

TA = 125°C
TA = 25°C

TAI~-S50C
1M

''-~

0
-45

:ij

• r• t
II ~ '.. I'.c'
r;J,~
10M

10M
FREQUENCY (Hz)

135

i\

II!

~

.180

W

225

0..

100M

FIGURE 19. CLOSED LOOP FREQUENCY RESPONSE

3·220

ffi

~

::z:

·90
·135
·180

100M

RS=50kO .....'

FIGURE 18. SMALL SIGNAL BANDWIDTH vs SOURCE
RESISTANCE

~

-8

. ;c .'.

•'0:;
roVOUT_
~
9000
l
1000- -

Rs=5kO "

'. '\.

~

lOOK
1M
FREQUENCY (Hz)

RS=OO_

Av=·l".

vs .. ±8V.Av=+1
RL .. 2kD, CL S 10pF

VIN

-1 0

~

I~

I

5

FIGURE 17. GAIN AND PHASE FREQUENCY RESPONSE

lOOK

'0

0

k/',

PH,Ji:

:""

.1..1

5

\ JJ ' n111;1;]
I.

II

Vs = ±15V. RL = lkn

20

II

Vs .. ±15V
RL=lkn
CL S10pF
TA =2S"C
10

(Continued)

iii'
w
w

a:

CI

iii

e.w
Ul

oCt

::z:

0..

HA-2541
Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

80 mils x 90 mils x 19 mils
2020!!m x 2280!!m x 483!!m

vTRANSISTOR COUNT:

METALLIZATION:

41

Type: AI, 1"10 Cu
Thickness: ISkA ±2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride(Si3N4) over Silox (Si02 , 5"10 Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-2541
-IN

+IN

BAL

..J
«II)

za:

O!!:!
-u...

!;;::::i
a:c..

w::

~«

v-

NC

BAL

OUTPUT

3-221

Vt

HA-2542
70MHz, High Slew Rate, High Output
Current Operational Amplifier

November 1996

Features

Description

• Stable at Gains of 2 or Greater

The HA-2542 is a wideband, high slew rate, monolithic
operational amplifier featuring an outstanding combination of
speed, bandwidth, and output drive capability.

• Gain Bandwidth .......................... 70MHz
• High Slew Rate ..................... 300VlJ.ls (Min)
• High Output Current ................. 100mA (Min)
• Power Bandwidth •..•..•..•..••••••.• s.sMHz (Typ)
• Output Voltage Swing. • • . . • . . . . . . . • • .. ±10V (Min)

Utilizing the advantages of the Harris 0.1. technology this
amplifier offers 350VlJ.ls slew rate, 70MHz gain bandwidth,
and ±100mA output current. Application of this device is
further enhanced through stable operation down to closed
loop gains of 2.

• Monolithic Bipolar Dielectric Isolation Construction

For additional flexibility, offset null and frequency
compensation controls are included in the HA-2542 pinout.

Applications

The capabilities of the HA-2542 are ideally suited for high
speed coaxial cable driver circuits where low gain and high
output drive requirements are necessary. With 5.5MHz full
power bandwidth, this amplifier is most suitable for high
frequency signal conditioning circuits and pulse video
amplifiers. Other applications utilizing the HA-2542
advantages include wideband amplifiers and fast samplehold circuits.

• Pulse and Video Amplifiers
• Wideband Amplifiers
• Coaxial Cable Drivers
• Fast Sample-Hold Circuits
• High Frequency Signal Conditioning Circuits

Ordering Information
PART NUMBER

TEMP.
RANGE (oC)

PACKAGE

PKG.
NO.

HA1·2542-2

-5510125

14Ld CERDIP

F14.S

HA1-2542-5

01075

14LdCERDIP

F14.S

HA2-2542-2

-5510125

12 Pin Metal Can

T12.C

HA2-2542-5

01075

12 Pin Metal Can

T12.C

HAS-2542-5

01075

14 Ld PDIP

E14.S

For more information on the HA-2542, please refer to
Application Note AN552 (Using the HA-2542), or Application
Note AN556 (Thermal Safe-Operating-Areas for High
Current Op Amps).

For a lower power version of this product, please see
the HA-2842 data sheet.

Pinouts
HA-2542
(PDIP, CERDIP)
TOP VIEW

HA-2542
(METAL CAN)
TOP VIEW

+IN

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-222

File Number

2899.2

HA-2542
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V- Terminals) ............. 35V
Differential Input Voltage ................................ 6V
Output Current ................ 50mA Continuous, 125mApEAK

Thermal Resistance (Typical, Note 2)
9JA (oCIW) 9JC (oCIW)
CERDIP Package ....... . . . . . . . . .
75
20
100
N/A
PDIP Package. . . . . . . . . . . . . . . . . . .
Metal Can Package. . . . . . . . . . . . . . .
65
34
Maximum Junction Temperature (Note 1, Hermetic Packages) . 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range· . . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300°C

Operating Conditions
Temperature Range
HA-2542-2 .............................. -55°C to 125°C
HA-2542-5 ................................. OOC to 75°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only ;"ting and operation
of the device at these or any other condiffons above those indicated in the operational sections of this specificaffon is not implied.

NOTES:
1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 175°C for
ceramic and can packages, and below 150°C for plastic packages. By using Application Note AN556 on Safe Operating Area equations,
along with the thermal resistances, proper load conditions can be determined. Heatsinking will be required in many applications. See the
"Application Information" section to determine if heat sinking is required for your application.
2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±15V, RL = lkQ, CL S 10pF, Unless Otherwise Specified

PARAMETER

TEST
CONDITIONS

HA-2S42-2
-5S DC to 12SDC

HA-2542-5
OOC to 75DC

TEMP.
(DC)

MIN

TYP

MAX

25

-

5

10

Full

B

20

Full

14

-

15

35

26

50

MIN

MAX

UNITS

 50mA (e.g. :;;50% duty cycle for 100mA).
4. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = ;Ie; Rate .
1t PEAK
5. Differential gain and phase are measured at 5MHz with a IV differential input voltage.

6. Refer to Test Circuits section of this data sheet.
7. VIN = 1VRMS; f = 10kHz; AV = 10.

Test Circuits and Waveforms

I N q : _ OUT
500n
500n

NOTES:

8. VS=±15V.

VOUT

9. Av=+2.
10. CL:;; 10pF.
Vertical Scale: VIN = 2.0V/Div., VOUT = 5.0V/Div.
Horizontal Scale: 200ns/Div.
LARGE SIGNAL RESPONSE

TEST CIRCUIT

3-224

HA-2542
Test Circuits and Waveforms

(Continued)

VOUT

Vertical Scale: IOOmV/Div.
Horizontal Scale: 50ns/Div.

Vertical Scale: 100mV/Div.
Horizontal Scale: 10ns/Div.
Vs ±15V. RL Ikn. Propagation delay variance
is negligible over full temperature range.

=

SMALL SIGNAL RESPONSE

=

PROPAGATION DELAY

..J

<1:0

.---. . .- - - - -......- 0 ( )

SETTLING
POINT

soon

11. Av = -2.

!;:::::i
a:c.
W:e:

13. HP5082-2810 clipping diodes recommended.
lkn

VIN

OW

12. Feedback and summing resistors must be matched (0.1%).

2.Skn

14. Tektronix P6201 FET probe used at settling point.

V+

o--..........."IV-4IO---~>_......___o()

VOUT

Za:

NOTES:

IS. For 0.01% settling time, heat sinking is suggested to reduce
thermal effects and an analog ground plane with supply
decoupling is suggested to minimize ground loop errors.

V-

SETTLING TIME TEST CIRCUIT (See Notes II - 15.)

3-225

-u::
~ 100 C (1500 C - 140°C).
Heatsinking would be required for operation at ambient
temperatures greater than 100 C.

=

=

=

Note that the problem isn't as severe with either the CERDI P
or Can packages due to their lower thermal resistances, and
higher TJMAX. Nevertheless, it is recommended that Figure
1 be used to ensure that heat sinking is not required.

3-226

HA-2542
As a result of speed and bandwidth optimization. the
HA-2542 can's case potential. when powered-up. is equal to
the V- potential. Therefore. contact with other circuitry or
ground should be avoided.

6
o

~ 100r-~---+--~--+---~-+--~­

z

iii

~

80

"!5
~

60

~~~__~~--~~~~--~--+---~~

Frequency Compensation
The HA-2542 may be externally compensated with a single
capacitor to ground. This provides the user the additional
flexibility in tailoring the frequency response of the amplifier.
A guideline to the response is demonstrated on the typical
performance curve showing the normalized AC parameters
versus compensation capacitance. It is suggested that the
user check and tailor the accurate compensation value for
each application. As shown additional phase margin is
achieved at the loss of slew rate and bandwidth.

I---+--+--+---t--

!::

;:
~401--+--+--+--+--I---+--+--+----jf----1
::;;

~

~
::;;

20

5
10 15 20 25 30 35 40 45
OUTPUT CURRENT (100% DUTY CYCLE, rnA)
FIGURE 1. MAXIMUM OPERATING TEMPERATURE
OUTPUT CURRENT

50

vs

Allowable output power can be increased by decreasing the
quiescent dissipation via lower supply voltages.
For more information please refer to Application Note
AN556, "Thermal Safe Operating Areas for High Current Op
Amps".
Prototyping Guidelines
For best overall performance in any application, it is recommended that high frequency layout techniques be used. This
should include: 1) mounting the device through a ground
plane: 2) connecting unused pins (NC) to the ground:
3) mounting feedback components on Teflon standoffs and
or locating these components as close to the device as possible: 4) placing power supply decoupling capacitors from
device supply pins to ground.

For example, for a voltage gain of +2 (or -1) and a load of
500pF/2kO, 20pF is needed for compensation to give a small
signal bandwidth of 30MHz with 40° of phase margin. If a full
power output voltage of ±1 OV is needed, this same configuration will provide a bandwidth of 5MHz and a slew rate of
200V/~s.

If maximum bandwidth is desired and no compensation is
needed, care must be given to minimize parasitic capacitance at ihe compensation pin. In some cases where minimum gain applications are desired, bending up or totally
removing this pin may be the solution. In this case, care
must also be given to minimize load capacitance.
For wideband positive unity gain applications, the HA-2542
can also be over-compensated with capacitance greater
than 30pF to achieve bandwidths of around 25M Hz. This
over-compensation will also improve capacitive load handling or lower the noise bandwidth. This versatility along with
the ±100mA output current makes the HA-2542 an excellent
high speed driver for many power applications.

Typical Applications
40

~

30

z 20

~

10

o

IN~_

o

OUT
990n

-45

fa
~

CJ

-90

e.
w

10n

-135 ~

-180 ...

Frequency (Od8) = 44.9MHz,
Phase Margin (Od8) = 40°
FREQUENCY RESPONSE
FIGURE 2. NON INVERTING CIRCUIT (AVCL

3-227

=100)

..J

«U)
Za:

O!!!
-LL

~:::i
a: 11.
W:i:

~«

HA-2542
Typical Applications

(Continued)

8

..,iii" 6

i'
~

I N I 1 : - OUT

son

4

2

o

o

son

-45

iil
w

Il!

e.w

Cl

m90

-135 ~
-180
Frequency (dB) = 56MHz. Phase Margin (3dB) = 40°
FREQUENCY RESPONSE

FIGURE 3. NONINVERTING CIRCUIT (AYCL

•

~

~l t:ro~
lkn.

=2)

IN

75n

lkn

OUT

1VIDiv.; 1OOns/Div.
PULSE RESPONSE
FIGURE 4. VIDEO CABLE DRIVER (AYCL

= 2)

NOTES:
16. Suggesled compensation scheme 5pF - 20pF.
17. Tested Offset Adjustment Range is IVas +1mVI
minimum referred to output.
18. Typical range is ±20mV with RT = 5kQ.

FIGURE 5. SUGGESTED OFFSET VOLTAGE ADJUSTMENT AND FREQUENCY COMPENSATION

3-228

:z:
0..

HA-2542
Typical Performance Curves
1000

1000

10
Vs =±12V

8

~:;;:

~

:;;-

.sw

S:

100 IZ

w

~

10

r- INPUT NOISE CURRENT

IIII

10

~

()

INPUT NOISE VOLTAGE

r"'o

!:;

0

10K

~

-2

~
II. -4

-

. ..

-60

-40

-20

0

~t

27
_

10K

~

~

::::I

"~

100

~

V-

19

!5

I

17

lSI 13
11

--

/

16

~
!zw

I.rt'

13

()

:$

I J'

14

a:
a:
::::I 12

UI

".

15

11

lSI 10
9
8
7

1:1

If.!

/

Oll:!
-II.

~

!;;:::::i
a:

"

~~ ~

100M

~«

I'..

I"""- ~ r-.... ~ ~
.......
~"'"
-40

-60

-20

0

20

40

60

-

-I80

TEMPERATURE (DC)

100

120

FIGURE 9. BIAS CURRENT vs TEMPERATURE

120
SIX REPRESENTATIVE UNITS

Vs _±15V

~

110
CMRR
100

....

I"""

90

[II ~
rll

80

Ifl
If
5

7

9
11
SUPPLY VOLTAGE (±V)

13

15

PSRR

-

70
-60

-40

-20

0

20

40

60

80

100

TEMPERATURE (DC)

FIGURE 10. BIAS CURRENT vs SUPPLY VOLTAGE

FIGURE 11. PSRR AND CMRR vs TEMPERATURE

3-229

0..

w:=

7

1M
10M
FREQUENCY (Hz)

TA=250 C

.J

«In
Za:

9

I 1IIIili

18

.....

~ 15

900n

FIGURE 8. INPUT RESISTANCE vs FREQUENCY

17

120

Vs =±12V
SIX REPRESENTATIVE UNITS

l"....
"'...... ~ ~

()

loon

10
lOOK

100

,

"-

~

a:

~
~

80

"- ~

23

cr:

.::; 21

I-

60

29

25

1000

40

FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE

lOOK

Cii

20

TEMPERATURE (OC)

TA =25oC
Vs=+15V

::!

~• .! -

-10

lOOK

FIGURE 6. INPUT NOISE VOLTAGE AND INPUT NOISE
CURRENTvsFREQUENCY

UI

-

-8 I .

1

FREQUENCY (Hz)

§:
z~

.

-6

~

i""" I"lK

Iii

"-

I

100

w
!!!
0
Z

....

--.

4
2

!j 0

::::I

~

IIII

~

a:
a:

SIX REPRESENTATIVE UNITS

6

120

HA-2542
Typical Performance Curves

(Continued)

32

28

~
zfw

IX:
IX:

;:)

~ 20

;:)

18 25°C

III

80

!

40

If

20

-

I

8
10
12
SUPPLY VOLTAGE (±V)

6

4

~

Av=2

±15V

Av=2

±10V

-

-'

i

-

±15V

III

Av=10
100

Av= 10

±10V

I

±5V

Av=10

I

I

-25

o

o
-50

25
50
75
TEMPERATURE (OC)

r--i'\

2.0

~

-2.0

~ 0.0

~

~

-4.0

-6.0
-8.0
0_10•0

!:i

+VOUT\

25

"i.'

-40

-20

...

1.3

0

1.2

!(
w
;:)

.....

1.1

:;l:

1.0

12Q

0.9

~

0.8

w

..:
::Ii

13

~~~

~

KI "

""'i..o" ~ "

VS=±7,_

Vs =±8

I,.,;~

"'"

0204060
TEMPERATURE fc)

80

100

120

_I

Q.

-~

~ ::::~

1.4

r+VOUT '

-55°C - -VOUT r-1250C
-12.0 -VOUT
-VOUT
-14.0
7
9
11
5
SUPPLY VOLTAGE (±V)

~~ ~:::: ~
~~ ~

I'::. ~~ ~

II ~"'"

~". L.oo' ~

10
-60

-'

~r- 2~~C

~

l-

....1"'"

FIGURE 15. OPEN LOOP GAIN VB TEMPERATURE,
AT VARIOUS SUPPLY VOLTAGES

-~

125°C

i'.

~~

15
125

100

12.0
25°C

35

20

FIGURE 14. SLEW RATE VB TEMPERATURE AT VARIOUS
SUPPLY VOLTAGES

10.0 -55°C
8.0 +VOUT
~ 6.0
CJ
Z 4.0

Vs = ±15

-' 30

±5V

~ ~".

Vs =±12""

40
~

Av=2

I I I.

45

L:::::>
~

i"-...

~-

50

~ 300
w

~

10M

55

400

w

1M

FIGURE 13. PSRR AND CMRR vs FREQUENCY

RL= lOOn

ii: 200

lOOK

10K

FREQUENCY (Hz)

500

IX:

lK

100

14

FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE,
AT VARIOUS TEMPERATURES

!(

....

1250C

12

~

.... ....

o

I

I

14

.... ~

-PSRR

60

II

16

....

+PSRR

I
1

22

CMRR

100

fl

24

Vs =±15V
TA=250C RL=2k!l _

I

120

I,
'I.

26 =-55 0C

0

II.
II.

I

,

30

-

IX:
0

PHASE MARGIN

"-

"

0.7

~

/

0.6
0.5

...-

~

z

15

FIGURE 16. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE,
AT VARIOUS TEMPERATURES

~

.-.t-

BANDWIDTH

I
o

~ ~6"

..... SLEWRATE-

~~

I

5
10
15
20
COMPENSA110N CAPACITANCE (pF)

25

FIGURE 17. NORMAUZED AC PARAMETERS VB COMPENSA110N
CAPACITANCE

3-230

HA-2542
Typical Performance Curves

(Continued)

II

.! If

12

~ 10
w

~

Cl

~

§!
....::>
....II.::>
0

HA-2542
Ay=10

8

j

RL=100n
MAXIMUM SWING
UNDISTORTED SWING

6
4

S =±1SV
TA =
25°C
MAXIMUM SWING
--- RL =1kn

~ 10
w

2

~

8

§!
....

~
5

~~
~~

6

1""'0 ...
4
2

o
0.1

10

RL=1kn
MAXIMUM SWING
/UNDISTORTED SWING

Cl

I 1111111

..... UNDISTORTED
SWING

V

HA-2542
Ay=10
Vs= ±10V
TA= 25°C

12

RL = 100n
MAXIMUM SWING ",
UNDISTORTED SWING

1 11111111111

o

100

70

~40
~

20
10

o

~II

0.1

I III
! I "
Av=10

iD9

:!!.

z

II
PHASE

o

~.
vIII(

I I II
1

10
FREQUENCY (MHz)

FIGURE 20. FREQUENCY RESPONSE CURVES

100

100K

I

I

Za:
O!:!:!
-,,!ci:::J
a: a..

-55°C

-

~

25°C ......

soon GAIN = +2
Vs=±8V
RL=1kn
soon CL" 10pF
VIN,,90mV
1M

«til

~

GAIN

6

Cl 3

......

..J

I I I 1111 25°C I
I I 125°C "-

C

Av=2

100

10

12

II.~
Av = 100

30

"""

1

FIGURE 19_ OUTPUT VOLTAGE SWING vs FREQUENCY

HA-2542
TA= 25°C
RL= 1kn
Vs= ±15Y

Av = 1000

z

~~

FREQUENCY (Hz)

FIGURE 18. OUTPUT VOLTAGE SWING vs FREQUENCY

50

~

0.1

FREQUENCY (Hz)

60

~
po

10M
FREQUENCY (Hz)

oc~_

115

1

45

II!

\ 9Oe.5l

I
125°C

W::E

o Iii
w

~

135

~

·180

II.

100M

FIGURE 21. HA·2542 CLOSED LOOP GAIN vs TEMPERATURE

3-231

~«

HA-2542

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

v-

106 mils x 73 mils x 19 mils
2700ilm x 1850llm x 4831lm

TRANSISTOR COUNT:

METALLIZATION:

43

Type: AI, 1% Cu
Thickness: 16kA ±2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION
Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-2542
-IN

+IN

BAL

BAL

v-

OUTPUT

3-232

V+

COMP

HA-2544

~HARRlS
~

SEMICONDUCTOR

50MHz, Video Operational Amplifier

November 1996

Features

Description

•
•
•
•
•
•

The HA-2544 is a fast, unity gain stable, monolithic op amp
designed to meet the needs required for accurate
reproduction of video or high speed signals. It offers high
voltage gain (6kVN) and high phase margin (65 degrees)
while maintaining tight gain flatness over the video
bandwidth. Built from high quality Dielectric Isolation, the
HA-2544 is another addition to the Harris series of high
speed, wideband op amps, and offers true video
performance combined with the versatility of an op amp.

Gain Bandwidth .•...•.............•...... SOMHz
High Slew Rate •.•...••.••.•.••..•••.•••. l50Vl~s
Low Supply Current ....•..•...•..•••...•.•. 10mA
Differential Gain Error ••.•..•.••..•...•••..• 0.03%
Differential Phase Error •.•..•.••.••..• 0.03 Degrees
Gain Flatness at 10MHz.....•.••.•....•••.. 0.12dB

Applications
•
•
•
•

Video Systems
• Imaging Systems
Video Test Equipment • Pulse Amplifiers
• Signal Conditioning Circuits
Radar Displays
Data Acquisition Systems

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

PACKAGE

PKG.
NO.

HA2·2544·2

·5510125

8 Pin Melal Can

T8.C

HA3·2544-5

01075

8 LdPDIP

E8.3

01075

HA3·2544C·5

8 LdPDIP

E8.3

HA7·2544-2

·5510125

8 LdCERDIP

F8.3A

HA7·2544·5

01075

8 LdCERDIP

F8.3A

HA9P2544·5
(H25445)

01075

8 LdSOIC

M8.15

HA9P2544·9
(H25449)

-401085

8 LdSOIC

M8.15

HA9P2544C-5
(H2544C5)

01075

8 LdSOIC

M8.15

HA9P2544C-9
(H2544C9)

-401085

8 LdSOIC

M8.15

The primary features of the HA-2544 include 50MHz Gain
Bandwidth, 150Vl~s slew rate, 0.03% differential gain error
and gain flatness of just 0.12dB at 10MHz. High performance and low power requirements are met with a supply
current of only 10mA.
Uses of the HA-2544 range from video test equipment,
guidance systems, radar displays and other precise imaging
systems where stringent gain and phase requirements have
previously been met with costly hybrids and discrete
circuitry. The HA-2544 will also be used in non-video
systems requiring high speed signal conditioning such as
data acquisition systems, medical electronics, specialized
instrumentation and communication systems.
Military (/883) product and data sheets are available upon
request.

Pinouts
HA-2544 (PDIP, CERDIP, SOIC)
HA-2544C (PDIP, SOIC)
TOP VIEW

HA-2544
(METAL CAN)
TOP VIEW
NC

v-

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-233

File Number

2900.2

..J

cCtn

Za:

O!!!
-LL

!;i:::;
a:

a..
W:E

~cC

HA-2544
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals ............ , .. , . .. 35V
,. . 6V
Differentiallnpul Voltage (Note 1) ............. ,
................ ±40mA
Peak Output Current

Thermal Resistance (Typical, Note 2)
8JA (oCIW) 8JC (oCIW)
Metal Can Package,
, , ... , . . . . . .
160
75
PDIP Package. . . . . . . . . . . . . . . . . . . .
92
N/A
CERDIP Package ...... , ... , .. , .. . .
135
50
SOIC Package..... ...............
157
N/A
Maximum Junction Temperature (Hermetic Packages) ...... 175°C
Maximum Junction Temperature (Plastic Packages) ........ 150°C
Maximum Storage Temperature Range
-6SoC to 150°C
Maximum Lead Temperature (Soldering 105) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-2544/2544C-5. . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 75°C
HA-2544/2544C-9 ........ ................. -40°C to 8SoC
HA-2544-2 .............. , .......... , ... , -55°C to 125°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. To achieve optimum AC performance, the input stage was designed without protective diode clamps. Exceeding the maximum differential
input voltage results in reverse breakdown of the base-emitter junction of the input transistors and probable degradation of the input
parameters especially Vas, los and Noise.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±15V, CL ,;10pF, RL = lkn, Unless Otherwise Specified

PARAMETER

TEST
CONDITIONS

TEMP
(0C)

HA-2544-2, -5, -9

I

MIN

TYP

MAX

HA-2544C-5, -9
MIN

TYP

MAX

15

25

I UNITS

INPUT CHARACTERISTICS
Offset Voltage

6

25

15

mV

-2, -5

20

40

mV

-9

25

40

mV

Average Offset Voltage Drift (Note 7)

Full

10

Bias Current

25

7

Full

10
15

9

20

Average Bias Current Drift (Note 7)

Full

0.04

Offset Current

25

0.2

I1A

30

I1A

0.04
2

0.8

3

Full

I1V;oC

18

I1AJDC
2

flA

3

I1A

Offset Current Drift

Full

Common Mode Range

Full

±10

±11.5

±10

±11.5

V

Differential Input Resistance

25

50

90

50

90

kn

3

3

pF

-

20

20

nV/..JHz
pAl..JHz

Differential Input Capacitance

10

25

10

nAJDC

Input Noise Voltage

f= 1kHz

25

Input Noise Current

f= 1kHz

25

2.4

2.4

Input Noise Voltage (Note 7)

O.IHz to 10Hz

25

1.5

1.5

I1VP_P

O.IHz to lMHz

25

-

4.6

4.6

I1V RMS

6

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 7)

Common Mode Rejection Ratio (Note 7)

Va = ±5V

AVCM=±10V

Minimum Stable Gain

3.5

2.5

-2, -5

75

89

70

89

-9

75

89

65

89

dB

25

+1

+1

-

VN

-

45

MHz

50

MHz

65

Degrees

Unity Gain Bandwidth (Note 7)

Va = ±100mV

25

45

Va = ±100mV

25

50

25

3-234

-

65

-

kVN

6

-

2

Gain Bandwidth Product (Note 7)
Phase Margin

3

25
Full

kVN
dB

HA-2544
Electrical Specifications

VSUPPLY = ±15V, CL ;S10pF, RL = 1kn, Unless Otherwise Specified (Continued)

PARAMETER

TEST
CONDITIONS

TEMP
(DC)

HA-2544-2, -5, -9

I

MIN

TYP

MAX

HA-2544C-5, -9

I

MIN

TYP

MAX

-

I UNITS

OUTPUT CHARACTERISTICS
Output Voltage Swing
Full Power Bandwidth (Note 6)

Full

±10

±11

±10

±11

25

3.2

4.2

-

3.2

4.2

Peak Output Current (Note 7)

25

±25

±35

-

±25

±35

Continuous Output Current (Note 7)

25

±10

-

25

-

20

Output Resistance

Open Loop

V
MHz

-

±10

mA
mA

20

n

TRANSIENT RESPONSE
Rise Time (Note 4)

25

7

Overshoot (Note 4)

25

10

Slew Rate

25

Settling Time (Note 5)

25

100

150
120

-

7

ns

-

10

-

%

100

150

-

V/1lS

-

120

-

ns

-

0.03

-

Degree

0.0026

-

dB

0.03

-

VIDEO PARAMETERS RL = 1kn (Note 8)
Differential Phase (Note 9)

25

0.03

Differential Gain (Notes 3, 9)

25

0.0026

25

0.03

5MHz

25

0.10

10MHz

25

Gain Flatness

Chrominance to Luminance Gain (Note 10)

25

Chrominance to Luminance Delay (Note 10)

25

-

0.12

-

0.1

-

7

-

0.10

-

0.12

-

-

0.1

%
dB
dB
dB

7

-

ns

15

mA

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 7)

10

12

-

10

-2, -5

70

80

-

70

80

dB

-9

65

80

-

65

80

dB

Full
Vs =±10V to ±20V

NOTES:

4. For Rise Time and Overshoot testing, VOUT is measured from 0 to +200mV and 0 to -200mV.
5. Settling Time is specified to 0.1 % of final value for a 10V step and Av = -1.
6. Full Power Bandwidth is guaranteed by equation: Full Power Bandwidth =
7. Refer to typical performance curve in Data Sheet.

:Ie~ Rate (VPEAK = 5V).
lt

PEAK

8. The video parameter specifications will degrade as the output load resistance decreases'.
9. Tested with a VM700A video tester, using a NTC-7 Composite input signal. For adequate test repeatability, a minimum warm-up of 2
minutes is suggested. Av = + 1.
.
10. Col Gain and Col Delay was less than the resolution of the test equipment used which is 0.1dB and 7ns, respectively.

3-235

,.

HA-2544
Test Circuits and Waveforms
NOTES:
V+

11. VS=±lSV.
12. AV=+l.

>~~""-,,,,-oVOUT

13. RS = son or 7Sn (Optional).
14. RL = lkn.
lS. CL < 10pF.
16. VIN for Large Signal = ±SV.

v-

17. VIN for Small Signal = 0 to
+200mV and 0 to -200mV.
FIGURE 1. TRANSIENT RESPONSE

VOUT = 0 to +10V
Vertical Scale: VIN = SV/Div.; VOUT = 2V/Div.
Horizontal Scale: 100nS/Div.

VOUT =0 to +200mV
Vertical Scale: VIN = 100mV/Div.; VOUT = 100mV/Div.
Horizontal Scale: 100ns/Div.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

.--....----~-o ~~~~ING
5kO

2kO
2kO

RT

>-.....-oVOUT
NOTES:
18. Av=-l.
19. Feedback and summing resistor ratios should be 0.1% matched.
20. HPS082-2810 clipping diodes recommended.
21. Tektronix P6201 FET probe used at settling point.

NOTE: Tested offset adjustment range is IVos + 1mVI minimum
referred to output. Typical range for RT = 20kn is approximately
±30mV.

FIGURE 3. OFFSET VOLTAGE ADJUSTMENT

FIGURE 2. SETTLING TIME TEST CIRCUIT

3-236

HA-2544
Schematic Diagram
v+

1:

R2
.tl
Qp24
R2A

QP57F=rlQP58
Qp23
v-

QN22
R8

R7

QN36

Q~:'~

L

r

R9

R28

T

Qp5

C1

f

..... Qp19

j~R36

R37
QP32'"

v-

QN51 ....
+INPUT

Qp33

-INPUT
QNl

D34

~

~

R24
2000

D37
"---

~

QN2

R32
36o
~ OUTPUT
R33
36 o

Qp51....1

'" D38

F 039
F 040

R35

R~

R25
2000

.. QN43

r QN5

O!!:!
-La.

..... Qp54

~::::i
a:: a.

W:i!E

f*041

Rl0
v+

~<

,!QN18
Rll

R12

QPla..,~.
QN17

R13

QN9

QN59
r

...

... QN10 ... QN46

..... Qp15
R14

v+
r QN14

QN55

QN13
~

R15

R16

5kn

QN60
5kn

R38

R39

BAL

BAL

QN11

QN12

R17

R18

QN48
R31

v-

Application Information
The HA-2544 is a true differential op amp that is as versatile In a video signal, the video information is carried in the amplias any op amp but offers the advantages of high unity gain tude and phase as well as in the DC level. The amplifier must
bandwidth, high speed and low supply current. More impor- pass the 30Hz line rate luminance level and the 3.58MHz
tant than its general purpose applications is that the (NTSC) or 4.43MHz (PAL) color band without altering phase
HA-2544 was especially designed to meet the requirements or gain. The HA-2544's key specifications aimed at meeting
found in a video amplifier system. These requirements this include high bandwidth (50MHz). very low gain flatness
include fine picture resolution and accurate color rendition, ' (0.12dB at 10MHz). near unmeasurable differential gain and
and must meet broadcast quality standards.
differential phase (0.03% and 0.03 degrees). and low noise
(20nVlv'Hz). The HA-2544 meets these quidelines.

3-237

...J

50MHz), and can tolerate
some slight gain peaking and lower phase margin, experimenting with various load capacitance can be done.
Shown in Application 1 is an excellent Differential Input, Unity
Gain Buffer which also will terminate a cable to 750 and reject
common mode voltages. Application 2 is a method of separating a video signal up into the Sync only signal and the Video
and Blanking signal. Application 3 shows the HA-2544 being
used as a 100kHz High Pass 2-Pole Butterworth Filter. Also
shown is the measured frequency response curves.

Typical Applications
SHIELDED

Cf

1.21K
1.21K

f'oo

~

1.21K

1K

1

1K

COMPOO-S-ITJE~r-~---~~-i+ HA-2544

VIDEO

SYNC ONLY

~, 1N5711
~, 1N5711

1K

1.21K

VIDEO AND
BLANK

FIGURE 4. APPLICATION 1, 750 DIFFERENTIAL INPUT BUFFER

FIGURE 5. APPLICATION 2, COMPOSITE VIDEO SYNC
SEPARATOR
0

~
Z

Q

z~

w

2.1K
750pF

""'" --i

1

~.J.2~54-4+--O
~

~

-40

MIIIIII
II
1111 I
fo = 105.3kHz

~O

-80

~ ·100

750pF

:,.

·20

11

180

I-o~

135
90

OUTPUT

45
0

7 L--_----'
fO=

ffiw
II:

"e.
w

w
cC

Ul

X

1
21t (2.1 K x 750pF)

10

100

1K
10K
100K
FREQUENCY (Hz)

1M

-45
10M

FIGURE 7. MEASURED FREQUENCY RESPONSE OF
APPLICATION 3

FIGURE 6. APPLICATION 3, 100kHz HIGH PASS 2-POLE
BUTTERWORTH FILTER

3-238

a.

HA-2544
Typical Performance Curves
1000

1000

I~
~

.5.
w 100

~

~

100

"~

_1111111

W
In

z

111111111 J..J..

I 1111111

10

1111111

II

1o

...:::>
~

IlImto..

I 1111111

1
10

1

100

0
-1

o

~

-2

!!!

ti:i

~

-3

o

-4

w

oz

"
LL

-6

1
100K

10K

.... "'"

-5

~

l"I'MIIIL

1K

1

~

!zw

!5...

11111

2

:>

oS
w

:::>

INPUT NOISE CURRENT

f-

~

IX:
IX:

INPUT NOISE VOLTAGE

~

(5

3

~

~

~

~
~
80
80
TEMPERATURE (OC)

0

FREQUENCY (Hz)
FIGURE 8. INPUT NOISE VOLTAGE AND NOISE CURRENT
vs FREQUENCY

100

1~

1~

FIGURE 9. INPUT OFFSET VOLTAGE vs TEMPERATURE
(3 TYPICAL UNITS)

.J

c(C/)

15
14
13
12

~

z

t;(:J

a: a..

:::>

9

In

8

III

7

0

:!!:

w==
~c(

I"'

w 10

IX:
IX:

O!!!
-II.

,

11

f-

Za:

RL = 11<11, Vs = ±15V

I'.

....
.... 1'00.

-l- i-- ....

6

1""'1-

5

4
-60

-40

-20

20
~
60 80
TEMPERATURE (OC)

0

0.1Hz to 10Hz. Noise Voltage = 0.97I1VP_P
FIGURE 10. NOISE VOLTAGE (AV = 1000)

100 120

FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE

92

9

RL = 11<11, Vs = ±15V

II

RL = 1kn, Vs = ±15V

90
88

~

CMRR

iii'
:!:!. 86
IX:

o!!.

z

IX:

:::;
0
Q

84

z

82

IX:
IX:

80

...

78
76

"...0

-

....

....I

z

...

w
0

6

~

5

~~

4

)~~

3

74
~

""'~

7

0

+PSRR

In

-AVOL

8

<

-PSRR

0(

~

~

0

~
~
80 80
TEMPERATURE (oC)

100

1~

1~

-60

1~

-40

'"
-20

~'
~

...

0

~

... ......
....... ",,~I""

20
40 60 80
TEMPERATURE (oC)

... ~rttP
+AvOL

100

120 140

FIGURE 13. OPEN LOOP GAIN vs TEMPERATURE

FIGURE 12. PSRR AND CMRR vs TEMPERATURE

3-239

HA-2544
Typical Performance Curves
12

~

I

10

I

I

E

8

~

6 I - +VOUT

\
\

~ 4
w 2
~ 0
-2

-SSoC -

!;

~

o~

-10

I-

I

!;;;:::;:::s ~

.~

20

o

OPEN LOOP

Ay=10

~

I III

-IIIIIS
100

FIGURE 14. OUTPUT VOLTAGE SWING va SUPPLY VOLTAGE

...

Ay=-1

~

I III
I III

IS

..

Ay= 100

~P~~W?P,

13

11
SUPPLY VOLTAGE (±V)

RL = lk1l, Vs = ±15V

...

I IIII

J. J.!!

I

9

7

40

I

-12

5

60

z

I

-

I

iii

Ifsac

fSOC -

,

-8 I - -VOUT

80

:Eo

\

,

!j

~

(Continued)

~

~

AV= 10
, -, "' 'Ay-10'-

I II , -'III

lK

180

"!

:\

,. ~ ......

40
30

g20
!5

10

!!5

0

L.~ ~
~

II:

~

-10

~

-20

:::0

o

.... '

r"1f

AV=-1

10K
lOOK
1M
FREQUENCY (Hz)

10M

\

\

..

\

-5SoC- 250 C

~ .:l.

j
~

Z
~

20

fi

..

11
9
SUPPLY VOLTAGE (tV)

7

13

----

VOUT .. tl00mV

15

100

FIGURE 16. OUTPUT CURRENT VB SUPPLY VOLTAGE

1.0

II:
II:
:::0

0.9

zw

0

0.8

~

0.7

II.
II.
:::0

en

C

w

!::!

....
C
::E
0

II:

z

lK

-

~

,. -.

-. ~r"-t15V

, ,1

t8~~

±SV

10K
lOOK
1M
FREQUENCY (Hz)

o
-45
-90

~~

-135
-180
100M

10M

m

l§

e
~

-

Ay=+I, VOUT=±loomV

I

J

If.... /

,/

/
1/
O.S
j /
0.4
V
0.3 /
0.2 /
0.6

i

o
100M

FIGURE 17. OPEN LOOP RESPONSE

1.1
f-

---

-~

-'"

r--

w

I±~~V

I

r..... ~

90
45

- ±8V
..... ±5V

1'1' ...

40

o

1250 C

-40

S

60

I

-30

-50

iii
"D

\

'"

z

!

FIGURE 15_ FREQUENCY RESPONSE AT VARIOUS GAINS

80

~ i'f'"

~:-.

/

50

~

135

r-...,
~

If'

RL=lkQ ,CL=,,10pF

~

6

/

iii 3
:Eo

z

~

1250 C
2SoC

-6

-ss°C

II-

_
=±I&V
.__ =±8V

t-

..... =±5V

"l!!

7

9

11

13

100

15

SUPPLY VOLTAGE (±V)

FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
(NORMALIZED TO Vs ±15V AT 25°C)

lK

10K
lOOK
1M
FREQUENCY (Hz)

~

o

~

-45

, f~~

1.,
I

1111 I 1111

0.1

5

.-

0
-3

10M

-90
-135

-180
100M

FIGURE 19. VOLTAGE'FOLLOWER RESPONSE

=

3-240

w

~

-

HA-2544
Typical Video Performance Curves
0.004

iii"
~
z

;;:

CI
-'

z~

w
w

0.002

CI
w

0.001
0

:--.....

-0.001

w -0.002
a:
~ -0.003

f

...........

....... ~

LL

..........

0.100

e.w

0.050

II)

0

...-'
:J::

-0.050

..:
f=
zw

-0.100

a:
w

...is
LL

-0.005

o

2
DC VOLTAGE LEVEL

0.150

a:

..:

= 3.58MHz AND 5.00MHz _

is -0.004
-0.006

0.200

u;

0.003

SYSTEM
ALONE

~

......... ~

~

-0.150
f

-0.200

-0.300

4

o

3.58MHz -

= 5.00MHz .............

I

-0.250

r--!..=
I

..............
.......... "'
4

2
3
DC VOLTAGE LEVEL

--

FIGURE 21. AC PHASE VARIATION vs DC OFFSET LEVELS
(DIFFERENTIAL PHASE)

FIGURE 20. AC GAIN VARIATION vs DC OFFSET LEVELS
(DIFFERENTIAL GAIN)

.../

eten

Za::
O~

-LL

~::i
a::c.
W:E

~et

=

NTSC Method, RL lkn, Differential Gain <0.05% at TA
No Visual Difference at TA = -55°C or 125°C

=75°C

NTSC Method, RL = 1kn,
Differential Phase < 0.05 Degree at TA = 75°C
No Visual Difference at TA = -55°C or 125°C
FIGURE 23. DIFFERENTIAL PHASE

FIGURE 22. DIFFERENTIAL GAIN

INPUT

AV = +1, VIN = ±l00mV
RL = lkn, CL < 10pF
0.15

iii"
~

0.10
0.05

OUTPUT

II)
II)

w

z
!;;:
-'
LL

0

"

-0.05

z
;;:

-0.10

CI

-0.15
-0.20
100

lK

10K
lOOK
1M
FREQUENCY (Hz)

10M

NTSC Method, RL = lkn, Col Delay <7ns at TA = 75°C
No Visual Difference at TA -55°C or 125°C
Vertical Scale: Input = 1OOmV/Diy., Output 50mV/Diy.
Horizontal Scale: 500ns/Diy.

=

\
100M

=

FIGURE 25. CHROMINANCE TO LUMINANCE DELAY

FIGURE 24. GAIN FLATNESS

3-241

HA-2544

Typical Video Performance Curves

,

1

L
-VOUT

~

1
1
1
1
-1-

I~

~

-t1

-250.000n8

L

"

1

~

1

r
--

.,

J
~

--

--

~

1
1
1
1
1
-1-

I~

~

0.00000n8

~

-t1

",
-~

(Continued)

L
J

--

z

,/.

X

''\

:2-

---~

7

~
~

=

6

~10

I

~

0

PHASE
(-3dB)

35.5
40.8
50.1
55.8
54.8

-77.1u
-89.&0
-122.00
-150.rD
-179.1 0

0

r

-3

-9

-12
-15

250.000n8

BANDWIDTH
(-3dB)

; .... 20
___ 30
40
3 .......

I

~ -6

I

Ay=+l,VS=±15V
RL = lk1l

!""':'.

II
I

50

iii'

lJ

o

II

'.~'
lK* CL

'~

45

~~

0

•
•

-18
lOOK

VIN = 2.0V/Div.• VOUT = 2.0V/Div.• Timebase = 50ns
FIGURE 26. ±2V OUTPUT SWING (WITH RLOAD
FREQUENCY 5.00MHz)

(~~
,

ii

i'""'"

9

= 750,

90

135
j

180
1M

10M

100M

FIGURE 27. BANDWIDTH vs LOAD CAPACITANCE

3-242

~

CI

~
Ii:
~

IIIct
if

HA-2544
Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

v-

80 mils x 64 mils x 19 mils
2030llm x 1630llm x 4831lm

TRANSISTOR COUNT:

METALLIZATION:

44

Type: AI, 1% Cu
Thickness: 16kA ±2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ± 2kA
Nitride Thickness: 3.5kA ±1.SkA

Metallization Mask Layout
HA-2544
SAL

-IN

+IN

v-

3-243

HA-2548
150M Hz, High Slew Rate,
cis ion Operational Amplifier
Features

Description

• High Slew Rate .•...••••...•••.....•.•..• 120Vl!1S

The HA-2548 is an op amp that offers a unique combination
of bandwidth, slew rate, and precision specifications. These
features can eliminate the need for composite op amp
designs and external calibration circuitry.

• Low Offset Voltage ...••..•.•••.•..... " .•.• 300!1V
• High Open Loop Gain ....•...•...•..•••.... 130dB
• Gain Bandwidth Product. ...•••••.•••.•••• 150MHz
• Low Noise Voltage at 1kHz ..•••.•..••..• 8.3nVlVHZ
• Minimum Gain Stability. . . . . • • . . • . . . . . . . . • . . •.

Applications
• High Speed Instrumentation
• Data Acquisition Systems
• Analog Signal Conditioning
• PreciSion, Wideband Amplifiers

~5

Optimized for gains ~5, the HA-2548 has a gain-bandwidth
product of 150MHz and a slew rate of 120V/1J.S while
maintaining extremely high open loop gain (130dB Typ) and
low offset voltage (300!1V Typ). These specifications are
achieved through uniquely designed input circuitry and a
single ultra-high gain stage that minimizes the AC Signal
path. Capable of delivering over 30mA of output current, the
HA-2548 is ideal for precision, high speed applications such
as signal conditioning, instrumentation, video/pulse
amplifiers and buffers.
For information on the military version of this device please
refer to the HA-25481883 datasheet.

- PulseJRF Amplifiers

Ordering Information
PART NUMBER

TEMP.
RANGEc<'C)

PACKAGE

PKG.
NO.

HA2·254B-5

01075

B Pin Melal Can

TB.C

HA2-254B-9

-40 10 B5

B Pin Metal Can

TB.C

HA3-254B-5

01075

B Ld POIP

EB.3

HA7-2548-5

01075

8LdSBOIP

08.3

HA9P2548-5

01075

16LdSOlC

M16.3

Pinouts
HA-2548
(PDIP, SBDIP)
TOP VIEW

HA-2548
(METAL CAN)
TOP VIEW

HA-2548
(SOIC)
TOP VIEW

COMP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-244

File Number

2901.2

HA-2600, HA-2602,
HA-2605
12MHz, High Input Impedance
Operational Amplifiers

November 1996

Features

Description

•
•
•
•
•
•
•
•
•

HA-2600/2602l260S are internally compensated bipolar
operational amplifiers that feature very high input impedance
(500MO, HA-2600) coupled with wideband AC performance.
The high resistance of the input stage is complemented by
low offset voltage (O.5mV, HA-2600) and low bias and offset
current (1nA, HA-2600) to facilitate accurate signal
processing. Input offset can be reduced further by means of
an external nulling potentiometer. 12MHz unity gainbandwidth, 7V/JlS slew rate and 150kVN open-loop gain
enables
HA-2600/2602l2605 to perform
high-gain
amplification of fast, wideband signals. These dynamic
characteristics, coupled with fast settling times, make these
amplifiers ideally suited to pulse amplification designs as
well as high frequency (e.g. video) applications. The
frequency response of the amplifier can be tailored to exact
design requirements by means of an external bandwidth
control capacitor.

Bandwidth .••.•..••..•.•..•.....•..•..... 12MHz
High Input Impedance ..•.•.•••.••••••...•. SOOMO
Low Input Bias Current. .••.•••....•.•...•...• 1nA
Low Input Offset Current .••.•.....•..••..•.... 1nA
Low Input Offset Voltage ....•••.•.•••.•••••• O.SmV
High Gain ..••.••..••••.••...•••••..•••. lS0kVN
Slew Rate ••..•....••................•.... 7V/IlS
Output Short Circuit Protection
Unity Gain Stable

Applications
•
•
•
•
•

Video Amplifier
Pulse Amplifier
Audio Amplifiers and Filters
Hlgh-Q Active Filters
High-Speed Comparators
• Low Distortion Oscillators

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE (DC)

PACKAGE

PKG.
NO.

HA2-2600·2

·55 to 125

B Pin Metal Can

TB.C

HA2·2602·2

·55 to 125

B Pin Metal Can

TB.C

HA2·2605·5

Ot075

B Pin Metal Can

TB.C

HA3·2605-5

010 75

B Ld PDIP

EB.3

HA7·2600-2

-55 to 125

B LdCERDIP

FB.3A

HA7·2602-2

-55 to 125

BLdCERDIP

FB.3A

HA7-2605-5

010 75

B LdCERDIP

FB.3A

HA9P2605-5
(H26055)

010 75

B LdSOIC

MB.15

In addition to its application in pulse and video amplifier
designs, HA-2600/2602l2605 are particularly suited to other
high performance designs such as high-gain low distortion
audio amplifiers, high-Q and wideband active filters and
high-speed comparators. For more information, please refer
to Application Note AN515.
The HA-2600 and HA-2602 are offered as 1883 Military
Grade; product and data sheets are available upon request.

Pinouts
HA-2600102 (CERDIP)
HA-2605 (PDIP, CERDIP, SOIC)
TOP VIEW

HA-26OO102I05
(METAL CAN)
TOP VIEW
COMP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-245

File Number

2902.2

....I



U

-5
·10
·15

L

/BIAS

~/

lMHz

o

·25

·50

25

75

50

10MHz

100 125

TEMPERATURE (aC)

FIGURE 10. BROADBAND NOISE CHARACTERISTICS

FIGURE 9. INPUT BIAS CURRENT AND OFFSET CURRENT
vs TEMPERATURE
120

iii" 100
~

z

~

80

Cl

60

w

~

'-'

§i!

40

9

20

...0
z

~

0

1000

~

.........

"

" ~AIN

,

"'PHASE

0
·20
10Hz 100Hz

1kHz

~

0
20

i3w

60

B

100

II:

fiI

w
....
Cl

z

oC

~

1

140
180

w

~
:z:

...

c:

I"""'--- .......

800

~

!.

w 600

U

z
i§

...w

200

o

10kHz 100kHz lMHz 10MHz 100MHz

·55

FREQUENCY

"

~

400

Ii!

-35

·15

5

25

45

65

,

""'"

85

..........
105

125

TEMPERATURE ("C)

FIGURE 11. OPEN LOOP FREQUENCY RESPONSE

FIGURE 12. INPUT IMPEDANCE vs TEMPERATURE (100Hz)

3·249

HA-2600, HA-2602, HA-2605

Typffal Performance Curve~ , Vs = ±15V, TA = 25°C, Unless Otherwise Specified

100Hz
0.01'--_ _ _-'-_ _ _-'-_ _ _ _'--_ _ _-'
10kHz

100kHz

IMHz
FREQUENCY

FIGURE 13. OUTPUT VOLTAGE SWING

10MHz

100MHz

vS FREdUENCY

(Continued)

1kHz

10kHz 100kHz
FREQUENCY (Hz)

lMHz

10MHz

NOTE: External rompensation components are not required for stability,
but may be added to reduce bandwidth if desired. If Extemal Compensation is used, also connect I OOpF capacitor from output to ground,
FIGURE 14. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

120

lvsuLy

-5S0 C TO 1250 C

.~
5

~
./

~

./
m
..,
Z 100
~

V

10
15
SUPPLY VOLTAGE (±V)

120

80

w
w

60

0
:Ii

40

:Ii
:Ii
0
U

o

5
25
45
65
TEMPERATURE (DC)

85

105

'

..

1kHz

10kHz .
FREQUENCY

125

10

~

~

~ L..Jf-HH-IIlIftooo.;l-INPUT NOISE
CURRENT ,*H+tIftIIII
l!z
;;;- 100...
" "

ro-...

CJ

w

~

IE
8

~

....

~

w

~
~~

20

100Hz

-15

1000 '-'r-T1mn:rr-T-r""rm--r-nTmtT-r"TTT

II:

15

-35

FIGURE 16. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE

Q 100

C

80
-55

20

:2-

~.,
w

-

±5VSUPPLY -

FIGURE 15." COMMON MODE VOLTAGE RANGE vs SUPPLY
VOLTAGE

~
z

+IOVSUPPLY

'"
5

m

-

±15V SUPPLY

I0

t-1-t<1-l4II1II-+-I'l+I-IUI--+-j..j.I.tIIfI-+-A'I1IIt~I-+I~ 0.1 ~
~~

I
100kHz

IMHz

FIGURE 17. COMMON MODE REJECTION RAllO VB FREQUENCY

3-250

I

10

100
IK
FREQUENCY (Hz)

10K

0.01
tOOK

FIGURE 18. NOISE DENSITY vs FREQUENCY

HA-2600, HA-2602, HA-2605

Die Characteristics
DIE DIMENSIONS:

.

PASSIVATION:

69 mils x 56 mils x 19 mils
1750llm x 1420llm x 4831lm

Type: Nitride (Si3N4) over Silox (Si02. 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

METALLIZATION:
TRANSISTOR COUNT:

Type: AI. 1% Cu
Thickness: 16kA ±2kA

140
PROCESS:

SUBSTRATE POTENTIAL (Powered Up):

Bipolar Dielectric Isolation

Unbiased

Metallization Mask Layout
HA-2600, HA-2602, HA-2605
+IN

-IN

....I

BAL

:...-_-+--......_
4.2SV

..J

-+-oVOUT
50pF(NOTE)

NOTE: A small load capacitance of at least 30pF (including stray capacitance)
is recommended to prevent possible high frequency oscillations.
FIGURE 3. VIDEO AMPLIFIER

Typical Performance Curves

Vs = ±15V. TA = 25°C. Unless otherwise Specified

100r-----------~------,_---_,----~

15

~
LII
I;z
5II.

10

cc.s

5

!zLII

0

II:
II:

..""

-5

·15

~

10

I-

~

Z

...

LII

~

::;)

VaIAS

aLII

I'~
-50

.1

10knSOURCE
RESISTANCE

a!5

OFFSET

::;)

U

·10

EQUIVALENT INPUT
NOISE va BANDWIDTH

1~~Hz~--~~---1-0~kH-Z----l-00~kHz-----l-M~Hz-----l~OMHz

o

·25

25

50

75

100

UPPER 3dB FREQUENCY
LOWER 3dB FREQUENCY = 10Hz

TEMPERATURE fc)

FIGURE 4. INPUT BIAS CURRENT AND OFFSET CURRENT vs
TEMPERATURE

FIGURE 5. BROADBAND NOISE CHARACTERISTICS

120
iii'100

:!i!.

~

80

CI
LII

~

60

~

40

9z

20

......

1000

......

'"\. " ~AIN
"'-

!j

PHASE

LII

0

0
·20
10Hz 100Hz

20

10kHz 100kHz

LII

II:

60

I[

100

!i!

140

~

...

LII

~

0(

~

1

1kHz

iii'
LII
CI

"-

II.

II.

Q

:c
180

Cf
!.
LII

800

z
~
LII

600

-....

U

""

II.

iii

5II.

400

a!5

II.

200

o

lMHz 10MHz 100MHz

·55

FREQUENCY

FIGURE 6. OPEN LOOP FREQUENCY RESPONSE

~

-35

·15

~

5
25
45
65
TEMPERATURE fC)

" i'...
85

.........

105

125

FIGURE 7. INPUT IMPEDANCE va TEMPERATURE, 100Hz

3·256

HA-2620, HA-2622, HA-2625
Typical Performance Curves

Vs

=±15V, TA =25°C, Unless Otherwise Specified

(Continued)

20V
10V

~
CJ

z

iUJ

1V

w
CJ

~

~
cw

0.1V

lI/!

...

100Hz

1kHz

0.01V '--_ _ _...J...._ _ _ _. l -_ _ _-1_ _ _---l
10kHz

100kHz

1MHz

10MHz

l00MHz

'FREQUENCY

10kHz 100kHz
FREQUENCY

lMHz

10MHz

NOTE: External Compensation is required for closed loop gain < 5,
If external compensation is used, also connect 100pF
capacitor from output to ground.
FIGURE 9. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM COMPo
PIN TOGND

FIGURE 8. OUTPUT VOLTAGE SWING va FREQUENCY

..J

ctU)

Za:

120

20
-55°C to 125°C

~

~

i

10

z

o
::;

~

U

5

~

5

./

V

~

V

w

V

-

±2LsuJLY

~

W 15

±15V SUPPLY

iii'

:!!.

z

~

100

±5VSUPPLY

10
15
SUPPLY VOLTAGE (±V)

80
-55

20

-35

-15

1000 r-

.s
w
CJ

~

'"~

w
!II
0

z
~
...

5
25
45
65
TEMPERATURE fC)

10

r-..~
100

"'-""

INPUT NOISE CURRENT

~

1.0

i!i:.eo
w

Ii' .. k
""

I

II:
II:
::I

U

w

I

0.1

10 I- INPUT NOISE VOLTAGE -

6
z
...iE
I::I

iE

1 '-1

10

85

105

125

FIGURE 11. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE

FIGURE 10. COMMON MODE VOLTAGE RANGE va SUPPLY
VOLTAGE

~>

--

±10VSUPPLY

100
lK
FREQUENCY (Hz)

10K

FIGURE 12. NOISE DENSITY va FREQUENCY

3-257

0.01
lOOK

O!:!:!
-II..
~:J
a:Q..
W:E

~ct

I

HA-2620, HA-2622, HA-2625
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

69 mils x 56 mils x 19 mils
1750~m x 1420~m x 483~m

Type: Nitride (SiaN4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

METALLIZATION:
TRANSISTOR COUNT:

Type: AI, 1% Cu
Thickness: 16kA ±2kA

140
PROCESS:

SUBSTRATE POTENTIAL (Powered Up)

Bipolar Dielectric Isolation

Unbiased

Metallization Mask Layout
HA-2620, HA-2622, HA-2625

COMP

v+

BAL

OUT

-IN

+IN

BAL

v-

3-258

m

HA-2640, HA-2645

HARRIS
SEMICONDUCTOR

4MHz, High Supply Voltage Operational Amplifiers

November 1996

Features

Description

• Output Voltage Swing . . . . . . . . . . . . . . . . . . . . .. ±3SV

HA-2640 and HA-2645 are monolithic operational amplifiers
which are designed to deliver unprecedented dynamic
specifications for a high voltage internally compensated
device. These dielectrically isolated devices offer very low
values for offset voltage and offset current coupled with large
output voltage swing and common mode input voltage.

• Supply Voltage ...........•..•...... ±10V to ±40V
• Offset Current. . • . . • . • . . . . • . . . . . . . . . . . . . . . .. SnA
• Bandwidth ..••........•..•.••..•....•..••. 4MHz
• Slew Rate ...••••••.•.••••................ SVJ!!S
• Common Mode Input Voltage Range. . . . . . . . .. ±3SV
• Output Overload Protection

Applications

For maximum reliability, these amplifiers offer unconditional
output overload protection through current limiting and a chip
temperature sensing circuit. This sensing device turns the
amplifier ·off", when the chip reaches a certain temperature
level.
These amplifiers deliver ±35V common mode input voltage
range, ±35V output voltage swing, and up to ±40V supply
range for use in such designs as regulators, power supplies,
and industrial control systems. 4MHz gain bandwidth and
5V/!!S slew rate make these devices excellent components
for high performance signal conditioning applications.
Outstanding input and output voltage swings coupled with a
low 5nA offset current make these amplifiers excitation
designs.

• Industrial Control Systems
• Power Supplies
• High Voltage Regulators
• Resolver Excitation
• Signal Conditioning

Ordering Information
PART NUMBER

TEMP.
RANGEfC)

PACKAGE

PKG.
NO.

HA2-2640-2

-55 to 125

B Pin Metal Can

TB.C

HA2-2645-5

010 75

B Pin Metal Can

TB.C

HA7-2640-2

-55 to 125

B LdCERDIP

FB.3A

HA7-2645-5

Ot075

B LdCERDIP

FB.3A

Pinouts
HA-2640J2645
(CERDIP)
TOP VIEW

HA-2640J2645
(METAL CAN)
TOP VIEW
COMP

v(TO-99 CASE VOLTAGE = FLOATING)

CAUTION: These devices are sensitive to electrostalic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-259

File Number

2904.2

..J

.

'""""

1

125

10

100

W
N

::::;

SLEW RATE

~

:cC1
w
C1

~

g

~

-25

o

120

.iANDWlj~
25

50

75

80

o

"~ ...

45

.........

0
0

40

'"

0

-'

zW

"-

100

I>.

0

125

,PHASE

G~'

I>.

........

............

a:: 0.8
0
z
-50

0.01
lOOK

10K

FIGURE 5. INPUT NOISE CHARACTERISTICS

z

oc(
~

lK

FREQUENCY (Hz)

.........

"I"

W

II)

0.10

l5

1.4

a::

o

!;

0

w
u. 1.2
w

:::J

z

FIGURE 4. INPUT BIAS AND OFFSET CURRENT vs
TEMPERATURE

c
w
a::
a::

a::
a::

,CURRENT

INPUT NOISE VOLTAGE

1

TEMPERATURE (oC)

°on
12'"

!z

-40

10

100

lK

10K

lOOK

-,

........

1M

......

~

FREQUENCY (Hz)

TEMPERATURE (oC)

FIGURE 6. NORMALIZED AC PARAMETERS vs TEMPERATURE

3-262

:il

e-

135 ~

C1

~

180 w
225

10M

FIGURE 7. OPEN LOOP FREQUENCY RESPONSE

13

w
90 a::

270

~

I>.

HA-2640, HA-2645

Typical Performance Curves
~

Vs

=±40V. TA =25°C. Unless Otherwise Specified

1.2

'i1
OJ'

1.1

~

II:
II:

z

w

u.

w

II:

w

3

~
c
w

~

Cl
0..

8

V V

BANDW

V

'"

:::;

zW

0

0..

0

V'

0.8
10

40

oJ

~-/
0.9

CL=
CCOMP';' . ; . 100pF

80

<

SLEW RATE

1.0

II:

~

~

120

~

fil

(Continued)

40

20

30

10

40

lK

100

10K

lOOK

1M

10M

FREQUENCY (Hz)

SUPPLY VOLTAGE (±V)

FIGURE 8. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE AT 2SoC

FIGURE 9. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

100

f::

0:
D.

z
j

ccrn
Za:

,

O~

.......

VSUPPLY = ±20V

~

Cl

....I
VSUPPLY = +40V

-IL.

W
Cl

~

§!

a:

~cc

~

1.0

::>
0..

I-

::>

'vrlllU
IVIII II

§!

5
~
o

10K

lOOK

11""1~oC

OUTPUT LOAD CURRENT (mA)

FIGURE 11. OUTPUT CURRENT CHARACTERISTIC

40

2.0

II:
II:

::>
0

~

0..
0..

::>

UI

;

+Icc

1.5

30

Cl

20

0.5

~

10

0

Cl

-0.5

§!

-1.0

I-

z

1.0

w

~

-1.5

-Icc

-2.0
-2.5
10

I

'-_'--_-'-_-'-_.1...- -40 VIN = -35V

1M

2.5

S-

t

r--jt--j~~.~~-25-C+--~0~AI.i~=71,7.V~SU~p-p~-y-=~~~0~V-r-~

FIGURE 10. OUTPUT VOLTAGE SWING vs FREQUENCY

!iiiw

~ l1 t

10
115
20
125 C 25"c -55°C

AI.i=I,VSUPPLy=±20V
-20 _v.::;IN:,=_-1_5_v,-_r-_t----1

FREQUENCY (Hz)

C

-10

I"~f-'.,l-.;!""_""_-i

-55°C

0

0.1
lK

15

20

25

30

11.

w:=

~

UI

I-

!;;::::i

~

10.0 I--- VSUPPLY = +10V

35

0
-1 Oi'oo.

~

-2 0

o

-3 0
-40
10

40

SUPPLY VOLTAGE (±V)

FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE

t""'"

-

I.---' t""'"

-:::::--.... .....

~

-

~

-r---.... --...........
-VOUT

I

15

20

25

30

35

40

SUPPLY VOLTAGE (±V)

FIGURE 13. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE

3-263

HA-2640, HA-2645
Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

93 mils x 68 mils x 19 mils
2360llm x 1720llm x 4831lm

Unbiased
TRANSISTOR COUNT:

METALLIZATION:

76

Type: AI, 1% Cu
Thickness: 16kA ±2kA

PROCESS:
HV200 Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02, S% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.SkA ±1.SkA

Metallization Mask Layout
HA-2640, HA-2645

BAL

COMP

v+

-IN

OUT
+IN

v-

BAL

3-264

HA-2839
.,"_~~vOOMHz,

Very High Slew Rate
Operational Amplifier

Description
• Low Supply Current •••••••••.....•...•••••• 13mA
• Very High Slew Rate ......••••••••••...•. 625Vi!ls
• Open Loop Gain •...•••••.•••••••..••••••. 25kVN
• Wide Gain-Bandwidth (Ay ~ 10) ...•...••••. 600MHz
• Full Power Bandwidth ••••••..•.•••...•••.. 10MHz
• Low Offset Voltage •.•••••.••••••••.••.••••. 0.6mV
• Differential Gain/Phase .....•••. 0.03%10.03 Degrees
• Enhanced Replacement for EL2039

Applications

The HA-2839 is a wideband, very high slew rate, operational
amplifier featuring superior speed and bandwidth characteristics. Bipolar construction, coupled with dielectric isolation,
delivers outstanding performance in circuits with a closed
loop gain of 10 or greater.
A 625V/!ls slew rate and a 600MHz gain bandwidth product
ensure high performance in video and RF amplifier designs.
Differential gain and phase are a low 0.03% and 0.03
degrees respectively, making the HA-2839 ideal for video
applications. A full ±10V output swing, high open loop gain,
and outstanding AC parameters, make the HA-2839 an
excellent choice for high speed Data Acquisition Systems.
The HA-2839 is available in commercial and industrial
temperature ranges, and a choice of packages. For military
grade product, refer to the HA-2839/883 data sheet.

• Pulse and Video Amplifiers
• Wideband Amplifiers

Ordering Information

• High Speed Sample-Hold Circuits
• RF Oscillators

PART NUMBER

TEMP.
RANGEfc)

PKG.
NO.

PACKAGE

HA1-2839-5

010 75

14 LdCERDIP

F14.3

HA3-2839-5

01075

14 Ld PDIP

E14.3

HA3-2839-9

-401085

14 Ld PDIP

E14,3

Pinout
HA-2839
(CERDIP, PDIP)
TOPYIEW

NOTE: No Connection (NC) pins may be tied 10 a ground
plane for better isolation and heat dissipation.

CAUTION: These devices are sensitive to electrostatic discharge, Users should follow proper IC Handling Procedures.
Copyrlght,© Harris Corporation 1996

3-265

File Number

2841.2

~

WJ

"HA-2840

I-IARRIS
SEMICONDUCTOR

60,OMHz, Very High Slew Rilte
, Operational Amplifier

November 1996

Features

Description

• Low Supply Current .......••.•..........••. 13mA

The HA-2840 is a wideband, very high slew rate, operational
amplifier featuring superior speed and bandwidth
characteristics. Bipolar construction, coupled with dielectric
isolation, delivers outstanding performance in 'Circuits with a
,closed loop gain of 10 or greater.

• Very HighSlew Rate •.••••...•.••• .- ••...• 625V11lS
• Open Loop Gain •..•...•..•.••...•....•.•• 25kVN
• Wide Gain-Bandwidth (Av ~ 10) •.....•.•..• 600MHz
• Full Power Bandwidth ..•..•.••..........•• 10MHz
• Low Offset Voltage •••.•..•.•.•••••.••....•. 0.6mV
• Differential GalnlPhase •...•••.• 0.03%10.03 Degrees
• Enhanced Replacement for EL2039

Applications
• Pulse and Video Amplifiers
• Wideband Amplifiers
• High Speed Sample-Hold Circuits
• RF Oscillators

A 62!:>VI~ slew rate and a 600MHz gain bandwidth product
ensure high performaflce in video and RF amplifier designs.
Differential gain and phase are a low 0.03% and 0.03
degrees respectively, making the HA-2840 ideal for video
applications. A full ±10V output swing, high open loop gain,
and outstanding AC parameters, make the HA-2840 an
excellent choice for high speed Data Acquisition Systems.
The' HA-2840 is availabl~ in commercial and industrial
temperature ranges, and a choice of packages. See the
"Ordering Information" below for more information. For military grade product, refer to the HA-2840/883 data sheet.

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE(lIC)

PKG.
NO.

PACKAGE

HA3B2840-5

01075

14Ld PDIP

HA3·2840-5

010 75

8 Ld PDIP

E8.. 3

HA9P2840-5
(H28405)

01075

8LdSOlC

M8.15

E14.3

HA3B2840-9

-401085

14 Ld PDIP

E14.3

HA7·2840-9

-401085

8 LdCERDIP

F8.3A

HA3-2840-9

-401085

8 Ld PDIP

E8.3

Pinouts
HA-2840
(CERDIP, PDIP, SOIC)
TOP VIEW

HA-2840
. (PDIP)
TOP VIEW

NOTE: No Connection (NC) pins may be lied 10 a ground plane for better isolalion and heal dissipalion.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-266

File Number

2842.2

HA-2840
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 35V
Differential Input Voltage ................................ 6V
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50mA

Thermal Resistance (Typical, Note 2)
8JA (oCIW) 8JC (oCIW)
14 Lead PDIP Package. . . . . . . . . . . . . .
80
N/A
8 Lead CERDIP Package . . . . . . . . . . . .
135
50
8 Lead PDIP Package. . . . . . . . . . . . . . .
96
N/A
157
N/A
8 Lead SOIC Package...............
Maximum Internal Quiescent Power Dissipation (Note I)
Maximum Junction Temperature (Ceramic Package) . . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 1as). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-2840-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 75 0 C
HA-2840-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Recommended Supply Voltage Range ............. ±7V to ±15V

CAUTION: Stresses above those listed in ''Absolure Maximum Rarlngs' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
I. Maximum power diSSipation with load conditions must be designed to maintain the maximum junction temperature below 175°C lor
ceramic packages and below 150°C lor plastic packages.
2. 8JA is measured with the component mounted on an evaluation PC board in Iree air.

Electrical Specifications

VSUPPLY = ±15V, RL = Ikn, CL';; 10pF, Unless Otherwise Specilied
HA-2840-5. -9

PARAMETER

TEST CONDITIONS

TEMP (oC)

MIN

TYP

MAX

UNITS
....I

INPUT CHARACTERISTICS

c(fJ)

Offset Voltage (Note 8)

Za:

25

0.6

2

mV

O!!:!
-II..

Full

2

6

mV

a: a.

I1vfOc

Average Offset Voltage Drift

Full

-

20

Bias Current (Note 8)

25

-

5

14.5

fJ.A

8

20

I1A

4

fJ.A

Full
25

Offset Current

Full

-

I

8

fJ.A

Input Resistance

25

10

kn

Input Capacitance

25

I

pF

Full

±IO

-

V

Input Noise Voltage (Note 8)

I = I kHz, RSOURCE = on

25

-

6

nV/./Hz

Input Noise Current (Note 8)

1= 1kHz, RSOURCE = 10kn

25

6

pAl./Hz

Common Mode Range

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

Common-Mode Rejection Ratio (Note 8)

Note 3

VCM=±IOV

Minimum Stable Gain
Gain Bandwidth Product (Note 8)

25

20

25

Full

15

20

Full

75

80

25

10

-

kVN

-

kVN
dB
VN

-

MHz

±20

-

rnA

30

-

n

-

MHz

Vo = 90mV, Av = +100

25

600

Output Voltage Swing (Note 8)

Note 3

Full

±IO

-

Output Current (Note 8)

Note 3

Full

±IO

OUTPUT CHARACTERISTICS

Output Resistance

25

Full Power Bandwidth (Note 4)

Note 3

25

8.7

10

Differential Gain (Note 7)

Av= 10

25

-

0.03

3-267

V

%

!cc::i
W:E
~c(

HA-2840
Electrical Specifications

VSUPPLY = ±15V, RL = lkO, CL $ 10pF, Unless Otherwise Specified (Continued)
HA-2840-5, -9

PARAMETER

TEMP (oC)

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Differential Phase (Note 7)

Av= 10

25

0.03

Degrees

Harmonic Distortion (Note 8)

Av = 10, Va = 2Vp_p, f = 1MHz

25

-79

dBc

TRANSIENT RESPONSE (Note 5)

-

Rise Time

25

4

Overshoot

25

20

%

ns

Slew Rate (Notes 6, 8)

Note 3

25

550

625

V/IlS

Settling Time

10V Step to 0.1%

25

-

180

ns

POWER REQUIREMENTS
Supply Current (Note 8)

Full

Power Supply Rejection Ratio (Note 8)

13
75

Full

Vs = ±10V to ±20V

15

90

NOTES:
3. RL = lkO, Va = ±10V, OV to ±10V for slew rate.
Slew Rate
4. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = 2-V-- : (V pEAK = 10V).
5. Refer to Test Circuit section of data sheet.

It

PEAK

6. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.
7. Differential gain and phase are measured with a VM700A video tester, using a NTC-7 composite VITS.
8. See ''Typical Performance Curves" for more information.

Test Circuits and Waveforms
IN

0---""

>-1--0

OUT

900n

9. Vs=±15V.

loon

10. Av = +10.
11. CL < 10pF.
TEST CIRCUIT

INPUT
INPUT

OUTPUT

OUTPUT

Input = lV/Div.
Output = 5V/Div.
50nslDiv.

Input = 10mVlDiv.
Output = 100mV/Div.
50ns/Div.
SMALL SIGNAL RESPONSE

LARGE SIGNAL RESPONSE

3-268

mA
dB

HA-2840
Test Circuits and Waveforms

(Continued)

~~~

200n
INPUT

NOTES:
12. Av=-10.
13. Load Capacitance should be less than 10pF.

iJY""":h J-l

-

H~,

soon

2k!l

14. It is recommended that resistors be carbon composition
and that feedback and summing network ratios be
matched to 0.1 %.

OUTPUT
PROBE
MONITOR

15. SETILING POINT (Summing Node) capacitance should
be less than 10pF. For optimum settling time results, it is
recommended that the test circuit be constructed directly
onto the device pins. A Tektronix 568 Sampling
Oscilloscope with S-3A sampling heads is recommended as a settle point monitor.

5kn

SETTLING
POINT

SETILING TIME TEST CtRCUIT

Typical Performance Curves

TA = 25°C, VSUPPLY = ±15V, RL = lkQ, CL < 10pF, Unless Otherwise Specified

100

650

BO

r-;..

Iii" 60
:Eo

z
:;;:

"

40

•

II

20

J:

~

r- ====. ...

iii

r

~

'"

r 0jEi ,00,
10K

"

~
1"'1

~

g 600
c

0

W

J:
I-

«J:

~ 550

(/)

0

...

90
lBO

c

./

J:

~ 650

10M

1M

100M

5

6

7

'"~

a: 550

...

J:
I-

5! 450

~
z

70

"

~

~

350

·40

·20

14

15

...

BO

0

250
-60

13

90

..........

C

"

10
11
12
B
9
SUPPLY VOLTAGE (±V)

FIGURE 2. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE

-,

ti
:::l

~
z
:;;:

W::lE

g;<

" 500
lOOK

FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS GAINS

750

",..

~

..,.,., ......... ~

I

z
~
z
:;;:

FREQUENCY (Hz)

"N

~::::i
a::/l.

I-

"e. ...a:

~~

AVCL= 10

i'

rI7'"'+I
lK

w
w
a:
w

I"'!!Io

AVCL = 100

~

Za::
O!!!
-11.

"N

0
AVCL = 1000

....I


.5.

~

~

!zw

~
1.5 I-

w
II)
LL
LL

0.5 0

...... ........

.......

80

I-

:::I

""A

7\

12

a:

§

10

U

~


c

-55

...c

-65

l - f-

II:

~

-75

~

-85

II

I

II

Vo = lVp.p

11

Vo=5Vp_p

i-'
~

Vo=0.5Vp_p

'"

,

~

.....

.---'-t
J- i-"""

---

"
'"

.....

IJ ....

~

.....-

c

-95
500K

,

"

II

II:

FIGURE 14. TOTAL HARMONIC DISTORTION VB FREQUENCY

Vo=2Vp_p

0

§l

10M

FREQUENCY (Hz)

",

~

..

~

:,...."
,.,."..

1M

i~

"

~
i0oi

Vo = O.25Vp_p

I
I
10M

FREQUENCY (Hz)

FIGURE 15. INTERMODULATION DISTORTION VB FREQUENCY (TWO TONE)

3-271

HA,;.2840

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

v-

65 mils x 52 mils x 19 mils
1650/Lm x 131 O/Lm x 483/Lm

TRANSISTOR COUNT:

METALLIZATION:

34

Type: Aluminum, 1% Copper
Thickness: ·16kA ±2kA

PROCESS:

High Frequency Bipolar Dielectric Isolation

PASSIVATION:

Type: Nitride over Silox
Silox Thickness: 12kA ±2kA
Nitride thickness: 3.5kA ±1 kA

Metallization Mask Layout
HA-2840

..

r r.==n

['-~r====nr===iiiII3811

OUT

-IN

+IN

,

....

...I.J

y-

3-272

HA-2841
50MHz, Fast Settling, Unity Gain Stable,
Video Operational Amplifier

November 1996

Features

Description

• Low Supply Current ••••••••••••.•..••••.••• 10mA

The HA-2841 is a wideband, unity gain stable, operational
amplifier featuring a SOMHz unity gain bandwidth, and excellent
DC specifications. This amplifier's performance is further
enhanced through stable operation down to closed loop gains of
+1. the inclusion of offset null controls, and by its excellent video
performance.

• Low AC Variability Over Process and Temperature
• Unity Gain Bandwidth ..•.••••••.••.•.•••.• 50MHz
• Gain Flatness to 10MHz.••••••••.••..••••.. 0.05dB
• High Slew Rate .••••••.••.••.....•.••.•.• 240V/ms
• Low Offset Voltage .••••••••..•...•.••••••••• 1mV
• Fast Settling Time (0.1%) ••....•.•••.•.•••••. 90ns
• Differential Gain/Phase ••.•.•••• 0.03%10.03 Degrees
• Enhanced Replacement for AD841 and EL2041

Applications
• Pulse and Video Amplifiers
• Wideband Amplifiers
• High Speed Sample-Hold Circuits
• Fast, Precise D/A Converters
• High Speed AID Input Buffer

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGEr'C)

PACKAGE

PKG.
NO.

01075

14 Ld PDIP

E14.3

HA3-2841-5

01075

8LdPDIP

E8.3

HA9P2841-5
(H28415)

Ot075

8 LdSOIC

M8.15

HA3B2841-9

-401085

14 Ld PDIP

E14.3

HA3-2841-9
(H28415)

-401085

8Ld PDIP

E8.3

HA3B2841-5

The capabilities of the HA-2841 are ideally suited for high speed
pulse and video amplifier circuits, where high slew rates and
wide bandwidth are required. Gain flatness of 0.05dB, combined
with differential gain and phase specifications of 0.03%, and 0.03
degrees, respectively, make the HA-2841 ideal for component
and composite video applications.
A zener/nichrome based reference circuit, coupled with
advanced laser trimming techniques, yields a supply current with
a low temperature coefficient and low Iot·to-Iot variability. Tighter
Icc control translates to more consistent AC parameters
ensuring that units from each lot perform the same way, and
easing the task of designing systems for wide temperature
ranges. Critical AC parameters, Slew Rate and Bandwidth, each
vary by less than ±5'7'0 over the industrial temperature range (see

characteristic curves).
For military grade product, refer to the HA-2841/883 data
sheet. Harris AnswerFAX (407 724-7800), document num·
ber 3621.

Pinouts
HA-2841
(PDIP)
TOP VIEW

HA-2841
(PDIP, SOIC)
TOP VIEW

CAUTION: These devices are sens"ive to eleclrostatlc discharge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporation 1996

3-273

File Number

2843.2

....I

c(CI)

Za:
O!:!:!
-IL.

ti::J0.

a:

W::::e
~c(

HA-2841
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 35V
Differential Input Voltage ................................ 6V
Output Current (Note 3) .............................. 50mA
10mA (50% Duty Cycle)

Thermal Resistance (Typical, Note 2)

Operating Conditions
Temperature Range
HA-2841-5. • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 75°C
HA-2841-9 ............................. '" -40°C to 85°C
Recommended Supply Voltage Range ............ ±6.5V to ±15V

9JA (oCIw)

14 Lead PDIP Package....... . . . ......... .. .
89
8 Lead PDIP Package. . . . . . . . . . . . . . . . . . . . . . .
92
157
8 Lead SOIC Package.......................
Maximum Junction Temperature (Die, Note 1) ............... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ....... " -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............. 300°C
(SOIC - Lead Tips Only)

CAUTION: Strasses abova those listed in "Absolute Maximum Ratings' may cause permanant damage to the device. This is a stress only "'ling and opa"'tion
of the device at these or any other conditions above those indicated In the ope"'tional sections of this specification is not implied.

NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 150°C for
plastic packages.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.
3. Va = ±10V, RL unconnected. Output duty cycle must be reduced if lOUT >10mA.

Electrical Specifications

VSUPPLY = ±15V, RL = 1kO, CL';; 10pF, Unless Otherwise Specified
HA-2841-5. -9

TEMP.
PARAMETER

TEST CONDITIONS

I

('IC)

MIN

TVP

25

-

1

3

-

-

6

mV

14

-

'IJ.vfJC

MAX

UNITS

INPUT CHARACTERISTICS

Offset Voltage (Note 10)

Full
Average Offset Voltage Drift

Full

Bias Current (Note 10)

mV

25

-

5

10

Full

-

8

15

I1A
I1A
nAPC

Average Bias Current Drift

Full

45

-

Offset Current

25

0.5

1.0

IJ.A

1.5

I1A

Full
Input ReSistance

25

Input Capacitance

25

-

Common Mode Range

Full

±10

1

-

-

-

170

kO
pF
V

Input Noise Voltage

10Hzt01MHz

25

16

Input Noise Voltage (Note 10)

f = 1kHz, RSOURCE = 00

25

16

nVl.../Hz

Input Noise Current (Note 10)

f = 1kHz, RSOURCE = 10kO

25

2

oAlJHZ

IJ.VRMS

TRANSFER CHARACTERISTICS

Large Signal Voltage Gain

Common-Mode Rejection Ratio (Note 10)

VO=±10V

VCM=±10V

Minimum Stable Gain

-

25

25

50

Full

10

30

kVN

Full

80

95

25

1

-

-

VN

kVN
dB

25

50

-

MHz

Gain Flatness to 5MHz (Note 10)

RL",750

25

±0.015

-

dB

Gain Flatness to 10MHz (Note 10)

RL",5000

25

±0.05

Full

±10

±10.5

"Iote3

Full

15

30

Va = ±10V

25

3.2

3.8

Gain Bandwidth Product (Notes 5, 10)

dB

OUTPUT CHARACTERISTICS

Output Voltage Swing (Note 10)
Output Current (Note 10)
Output Resistance
Full Power Bandwidth (Note 6)

25

3-274

8.5

-

V
mA
0
MHz

HA-2841
Electrical Specifications

VSUPPLY

=±15V. RL =IkO. CL $IOpF. Unless Olherwise Specilied

PARAMETER

HA-2841-5, -9

TEMP.
(oC)

TEST CONDITIONS

(Continued)

TYP

MIN

MAX

UNITS

Differential Gain (Note 10)

Note 4

25

0.03

%

Differential Phase (Note 10)

Note 4

25

0.03

Degrees

Harmonic Distortion (Note 10)

Va = 2Vp_p, I = IMHz, Av = +1

25

>S3

dBc

TRANSIENT RESPONSE (Note 7)
Rise Time

25

3

Overshoot

25

33

Slew Rate (Notes 9,10)

AV=+1

25

200

Settling Time

10V Step to 0.1%

25

90

25

10

Full

10

ns

-

240

%
V/flS

-

ns

POWER REQUIREMENTS
Supply Current (Note 10)

Power Supply Rejection Ratio (Note 10)

NoteS

Full

70

mA

11

mA
dB

SO

NOTES:
4. Differential gain and phase are measured with a VM700A video tester, using a NTC-7 composite VITS. RF = Rt

=IkO, RL = 7000.

5. AVCL = 1000, Measured at unity gain crossing.

6. Full Power Bandwidth guaranteed based on slew rate measurement using FPBW

Slew Rate
=2
-V
1t

7. Refer to Test Circuit section 01 data sheet.

PEAK

(V pEAK = 10V) .

S. VSUPPLY = ±IOVto ±20V.
9. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.
10. See "Typical Performance Curves" lor more information.

Test Circuits and Waveforms
NOTES:
II. VS=±15V.
12. AV = +1.
13. CL < 10pF.

TEST CIRCUIT

INPUT

INPUT

OUTPUT

OUTPUT

=

Input 100mVlDiv.
Output = 100mV/Div.
50ns/Div.

Input = 5V/Div.
Output = 5V/Div.
50ns/Div.
LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

3-275

HA·2841
Test Circuits and Waveforms

(Continued)
SeTI'UNG
POINT

Skn

2kn

NOTES:
14.
15.
16.
17.
18.

>--50mA, Duty Cycle must be derated accordingly.

Electrical Specifications

VSUPPlY = ±15V, RL = 1kn, CL S 1(JpF, Unless Otherwise Specified

I
PARAMETER

TEST CONDITIONS

TEMP (DC)

HA-2842-5, -9
MIN

TYP

MAX

UNITS

1

3

m,V

-

6

mV

INPUT CHARACTERISTICS
Offset Voltage (Note 10)

-

25
Full

. Average Offset Voltage Drift

Full

Bias Current (Note ,10)

25

13
5

Full

·JJ.vf>c
10

JJ.A

15

JJ.A.
nAPC

Average Bias Current Drift

Full

20

-

Offset Current

25

0.5

1.0

-

1.5

-

Full
Average Offset Current Drift

Full

Input Resistance

25

170

Input Capacitance,

25

1

Common Mode Range

Full

Input Noise Voltage

10Hz to 1MHz

25

Input !IIoise Voltage Density

f = 1kHz, RSOURCE = on

25

Input Noise Current (Note 10)

f = 1,kHz, RSOURCE = 100kn

25

"

..' nAPC

1.3

±10

IlA
IlA

-

kn
pF

-

V

16

JJ.VRMS

16

-

nV/JHz

2

-

pAlJHz

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

Common-Mode Rejection Ratio (Note 10)

VO=±10V

VCM= ±10V

Minimum Stable Gain

25

50

100

Full

30

60

Full

80

110

-

dB

25

2

-

-

VN

-

±0.035

±10

±11

Gain Bandwidth Product (Note 10)

AVCL= 100

25

Gain Flatness to 10MHz (Note 10)

RL;<:75n

25

Output Voltage Swing (Note, 10)

VO=±10V

Full

Output Current(Note 10) ,

Note 3

Full

80

kVN
kViv

-

MHz
dB

OUTPUT CHARACTERISTICS

3-282

I'

100

I

- I
-

V
mA

Electrical Specifications

VSUPPLY ~ ±15V, RL ~ 1k!.l, CL 0': 10pF, Unless Otherwise Specified (Continued)
HA-2842-5, -9
TEST CONDITIONS

PARAMETER

TEMP(°C)

Output Resistance

MIN

25

TYP

MAX

UNITS

8.5

n

6

MHz

Full Power Bandwidth (Note 6)

Vo~±10V

25

Differential Gain (Note 10)

Note 5

25

0.02

%

Differential Phase (Note 10)

Note 5

25

0.03

Degrees

Harmonic Distortion (Note 10)

Vo ~ 2Vp_p, f

25

>81

dBc

ns

~

1MHz, Av

~

2

5.2

TRANSIENT RESPONSE (Note 7)
Rise Time

25

4

Overshoot

25

25

%

400

ViI1S
ns

Slew Rate (Notes 9,10)

Av~+2

25

Settling Time

10V Step to 0.1%

25

100

25

14.2

Full

14.3

325

POWER REQUIREMENTS
Supply Current (Note 10)

Power Supply Rejection Ratio (Note 10)

Note 8

70

Full

mA
15

80

mA
dB

NOTES;
5. Differential gain and phase are measured with a VM700A video tester, using a NTC-7 composite VITS. RF ~ R1 ~ 1kn, RL ~ 700n.
, 6. Full Power Bandwidth guaranteed based on slew rate measurement using FPBW

~

Slew Rate. V
~ 10V
2"V PEAK' PEAK
.

..J

<0
Za:
O!!:!
-LL

7. Refer to Test Circuits section of this data sheet.

!;;::J

8. VSUPPLY ~ ±10V to ±20V.

a:e.

W::l:

9. This parameter is not tested. The limits are guaranteed based on lab characterization and reflect lot-to-Iot variation.

~<

10. See ''Typical Performance Curves" for more information.

Test Circuits and Waveforms
IN 0----1

>-- .....--yOUT
ySETTLING TIME TEST CIRCUIT

OUT

ySUGESTED OFFSET VOLTAGE ADJUSTMENT

Application Information
The Harris HA-2842 is a state of the art monolithic device
which also approaches the "ALL-IN-ONE" amplifier concept.
This device features an outstanding set of AC parameters
augmented by excellent output drive capability providing for
suitable application in both high speed and high output drive
circuits.
Primarily intended to be used in balanced son and 7S0
coaxial cable systems as a driver, the HA-2842 could also be
used as a power booster in audio systems as well as a
power amp in power supply circuits. This device would also
be suitable as a small DC motor driver.
Prototyplng Guidelines
For best overall performance in any application, it is recommended that high frequency layout techniques be used. This
should include:
1. Mounting the device through a ground plane.
2. Connecting unused pins (NC) to the ground plane.
3. Mounting feedback components on Teflon standoffs
and/or locating these components as close to the device
as possible.
4. PlaCing power supply depoupling capacitors from device
supply pins to ground.
Power Dissipation Considerations
At high output currents, especially with the 8 lead SOIC package,
care must be taken to ensure that the Maximum Junction
Temperature (TJ, see "Absolute Maximum Ratings" table) isn't
exceeded. As an example consider the HA-2842 in the SOIC

package, with a required output current of SOmA at VOUT =10V
with ±1SV supplies. The power dissipation is the quiescent power
(45OmW = 30V x 15rnA) plus the power dissipated in the output
stage (POUT=2SOmW=SOrnAx(1SV-10V», or a total of
700mW. The thermal resistance (8JA) of the SOIC package is
1S]DCNJ, which increases the junction temperature by 110°C
over the ambient temperature (TAl. Remaining below TJMAX
requires that TA be restricted to S 4()DC (1S00C - 1100C).
Heatsinking would be required lor operation at ambient
temperatures greater than 40°C.
Note that the problem isn't as severe with either of the PDIP
packages due to their lower thermal resistances, however it
is recommended that the above analysis be performed for
any package if operating outside the conditions listed below:
MAX POUT WITHOUT HEATSINK (VS

=±15V)

14LEADPDIP
(OJA 89°CJW)

8 LEAD PDIP
(OJA 92°CJW)

8LEADSOIC
(9JA 157°CJW)

85°C

280mW

260mW

Heatsink Required

70°C

450mW

420mW

60mW

25°C

950mW

910mW

350mW

TA

=

=

=

Allowable output power can be increased by decreasing the
quiescent dissipation via lower supply voltages.
For more information please refer to Application Note ANS56,
Thermal Safe Operating Areas for High Current Op Amps.

3-284

HA-2842

Typical Performance Curves
120

'"

80
60

=25°C. VSUPPLY =±15V. RL =1kn. CL < 10pF. Unless Otherwise Specified

~~CLI=ll00~

OPEN LOOP

100

TA

100
II

'N

I

:z: 90

~

........./AvCL=10
~AvCL=2

iii'
W

~

_40
III

a:

III

w

:g. 20

~

e.w

0

UI

...
f-

I-

OPEN LOOP

_1

Lli
10

100

..~
'/

"l

lK

~CL

o

f

90
180

AvCL AVCL AvCL
=1000 =100 = 10 =2

13
::I
0

...:z:
a:

70

!3

60

z

50

~

C
III

C( 40
III

1M

10M

----

80
70

:z:

~

40

7

8

14

15

...

....I

<
0

....

20

--

3

OFFSET VOLTAGE

~

10"-"'"

2

-I1

""- ........

BIAS CURRENT

60

!

'"CJ
~

Iii

Ul

...

II.

0

-1

~

14

CE

~ 12

'"a:a:

::> 10

(J

~
"-

"::>

l!:

6

4
100 120 140

80

8

Ul

~ f\1

I

A

~12.5

~

!;

O~

--

lr

CJ

10

25°C

7

8

-- I
!;

-7.5

~

-10

~

,

~

±8V,lkO

-20

'±811 1~00
'I

-

±8V, 750
40

12

13

60

80

/'

±8~,llkO

-

...

-

z

20

11

\

11l-12.5

0

10

r-- r-~8117L

-5

Ii

\
-40

9

FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE

7.5

±8V,1500

15

'\

6

5

±15V, 750

2.5
-60

14

25OC

SUPPLY VOLTAGE (±V)

±15V, 1500

r

15

l- -550~

-2.5

±lJV,l~

14

4

FIGURE 9. INPUT OFFSET VOLTAGE AND INPUT BIAS
CURRENT vs TEMPERATURE

r-

13

1\ I ~
1 1/ 1
r\1

TEMPERATURE (DC)

15

12

16

~

0

40

11

FIGURE 8. SLEW RATE vs SUPPLY VOLTAGE

I I I

I,

10

SUPPLY VOLTAGE (±V)

FIGURE 7. SLEW RATE vs TEMPERATURE

8

9

8

TEMPERATURE (DC)

-,

140

TEMPERATURE (oC)

-60

+15V, 1500

r--

II'

±15V,lkO

-15

100 120

I-- I-

±15V, 750

~

-40

-20

0

20

40

60

80

100

120 140

TEMPERATURE (DC)

FIGURE 11. POSITIVE OUTPUT SWING vs TEMPERATURE

FIGURE 12. NEGATIVE OUTPUT SWING vs TEMPERATURE

3-286

HA-2842
Typical Performance Curves
30

11111111

~

25 I--

"iz

20

~

til

w

"~
~

l-

::>

a..

TA = 25°C. VSUPPLY = ±15V. RL = 1kn. CL < 10pF, Unless Otherwise Specified (Continued)
-40

111111

IIII

VSUPPLY = +15V
·50

..... ""

i

-

15
VSUPPLY = ±8V

S

-

0

-

-60

c

i!=

I\.

~-.

-

·70

...

-80

I-

::>
0

10K

1K

lOOK

I

1M

:!!.

t3::>
c

li!a..
c

0
::E

·70
·80

I""""

~

~

i:

;!';
cC

"...

II

O!:!:!
-u.

0.020

!;::::i
a: a..

w:=

0.015

~«

~

~

w 0.010
a:
w
IL

l..,....o000o

"

...I

«U)
Za:

~

-

~o=2Vp.: "", ~

'"

C

a:

.!.

~

a:

~

0.025

....
....
"'
....
j ,rc ~ ....
....
~"" .. """'"~ ~ ... :::: ~
VO=5t.P

I I IIII 10M

1M

FIGURE 14. TOTAL HARMONIC DISTORTION va FREQUENCY

;;
·60

Vo=1Vp.p
Vo=0.5Vp.p

FREQUENCY (Hz)

·40
·50

..

r\

I

lOOK

100M

10M

FIGURE 13. MAXIMUM UNDISTORTED OUTPUT SWING
vs FREQUENCY

ID

~

~,

~ ~ ~:::

Vo= 2Vp.p

-

FREQUENCY (Hz)

..

~

11

·90

-

,

'l,~

:!!.

--

10

I

VO=10Vp.p

VSUPPLY = ±10V

IL

Vo=1Vp.p

is 0.005

·90
VO=0.25VP.P t = r o y - p ' l

1

OL-~_-L_~~L--L_-L_~_L-~

SOOK

1M

10M

100

200

300

FREQUENCY (Hz)
FIGURE 15. INTERMODULATION DISTORTION vs
FREQUENCY (TWO TONE)

w
w

\

0.12
0.10

\

til

cC

:c
a..

...
~
zw

a:
~

!!:

600

700

800

900 1000

0.04

a:

e."w

500

FIGURE 16. DIFFERENTIAL GAIN vs LOAD RESISTANCE

0.14

Iii
w

400

LOAD RESISTANCE (n)

0.08

•

0.06

\

0.04

c

,
"'-

".....

VSUPPLY = ±8V -

z

I

I

200 300

400 500

I

VSUPPLY = ±15V -

I
100

~
IL

VSUPPLY = ±10V

600

1"

-

0.02

,.

0.01

I--

I

700 800 900 1000

~
~

D.",

Z

~

~

\

!

I--

til
til
W

0.02
o

-

R! =751

iii' 0.03

o

o

1M

2M

~

~

f

I

RL= lson

II

RL= soon

r

3M

4M

5M

6M

RL= l000n

7M

8M

9M

10M

FREQUENCY (Hz)

LOAD RESISTANCE (n)
FIGURE 17. DIFFERENTIAL PHASE va LOAD RESISTANCE

FIGURE 18. GAIN FLATNESS va FREQUENCY (AvCL

3·287

=2)

HA-2842

Typical Performance Curves

TA:= 25°C. VSUPPLY = ±15V. RL = 1kO. CL < 1OpF. Unless Otherwise Specified (Continued)

85

I

""~

-

~

J
85

o

100 200

300

400

500 800

700 800

900 1000

LOAD RESISTANCE (n)

FIGURE 19. GAIN BANDWIDTH PRODUCT va LOAD RESISTANCE

3·288

HA-2842

Metallization Topology
SUBSTRATE POTENTIAL (Powered Up):

DIE DIMENSIONS:

V-

77 mils x 81 mils x 19 mils
19S0llm x 20S0llm x 4831lm

TRANSISTOR COUNT:

METALLIZATION:

58

Type: Aluminum. 1% Copper
Thickness: 1SkA ±2kA

PROCESS:
High Frequency Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride over Silox
Silox Thickness: 12kA ±2kA
Nitride thickness: 3.5kA ±1 kA

Metallization Mask Layout
HA-2842

BAL

BAL

....I

'Hz
• Input Offset Voltage ....•..........••....... O.5mV
• Input Bias Current ......................•...60nA
• Supply Range. . • . . . . . . . . . . . . . . • . . . .. ±2V to ±20V
• No Crossover Distortion
• Standard Quad Pinout

Applications
• Universal Active Filters

These excellent dynamic characteristics also make the HA4741 ideal for a wide range of active filter designs.
Performance integrity of multi-channel designs is assured by
a high level of amplifier-to-amplifier isolation (69dB at
10kHz).

• 03 Communications Filters
• Audio Amplifiers
• Battery-Powered Equipment

A wide range of supply volt

!50

0.1 _
_

10

100

lK
10K
lOOK
FREQUENCY (Hz)

1M

UI~

.... +l

!Sl~

10M

100

/~

If....l

0.9

I

<0
c ....
Ulc
!::lUI
....I a:


O~

(VOLTAGE FOLLOWER)
RL =00
CL =50pF
III

I I I

"'>
a: ....

i'

VS=±2V

I 11111111

FIGURE 4. OPEN LOOP FREQUENCY RESPONSE
1.1

VS =±5V

, "" 1--, '" "'"

100

·10
1

Vs =±10v

r--.

_ Vo=SV

±10
±15
SUPPLY VOLTAGE (V)

FIGURE 6. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE

±20

.S
·55

·25

r-~
BANDWIDTH

"

SLEW RATE

I II
o

25

50

75

100

125

TEMPERATURE (GC)

FIGURE 7. NORMALIZED AC PARAMETERS vs TEMPERATURE

3-294

HA-4741
Typical Performance Curves

VSUPPLY

=±15V, TA =25°C, Unless Otherwise Specified

35

1.4

i

30

1.2

S

25

1.0 oS

w

f'\

~ 20
~

w 15

!!!

o

z 10

~

!;

....
60

~
w

:::l

~

0.6 ~
0.4

i'..

5

I
100

10

lK

I

10K

6 N

40

II:

30

'w"

l:

~
5 %

til

!5

...'"

...

~

%

"

10

o

o

100

10

5

0

5

o
10,000

100,000

...I

c(U)

V

za:

...z

:

W

j

II:
II:
:::l

40

0

"

~

1'0.

20

o

o
100

lK

10K

·50

lOOK

..... "-

~ I""""

r--.
·25

LOAD RESISTANCE (Q)

OFFSET CURRENT

~
o

I

I160

:::l

~

8

80

II:

~
4.

I

Vs =+15

z

Q

I

.
.

!Vs = +10I

I

-

I

Vs=±5

-

40

o
·50

50

75

FIGURE 11. INPUT BIAS AND OFFSET CURRENT vs
TEMPERATURE

200

Ii:::I! 120

25

TEMPERATURE ("C)

FIGURE 10. MAXIMUM OUTPUT VOLTAGE SWING VB LOAD
RESISTANCE

·25

o

I
25

I
50

75

100

125

TEMPERATURE ("C)

FIGURE 12. POWER CONSUMPTION VB TEMPERATURE

3·295

O!:!:!
-IL

BIAS CURRENT

C

S 60

10

:::l

z

80

20

...~

:::l

~

CI

15

1

100

25

~

~
i;:

CI

FIGURE 9. SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN VB LOAD CAPACITANCE

30

w

1000

2

LOAD CAPACITANCE (pF)

FREQUENCY (Hz)

FIGURE 8. INPUT NOISE vs FREQUENCY

1
~

z

'"

3 ID

1'1

20

lOOK

I:i
~

4

~

::I!

~

CURRENT NOISE- 0.2 !;

o

e.z

G

o

I~ ~

RL=2K

iii'
w
w
II: 50
CI
w

0.8 ~

VOLTAGE NOISE

7

70

~
:;
CI

(Continued)

100

125

!;::::i
a:Q.
W:i
~c(

HA-4741
Die Characteristics
SUBStRATE POTENTIAL (Powered Up):

DIE DIMENSIONS:

V:

87 mils x 75 mils x 19 mils
2210j.lm x 1910j.lm x 483j.lm

TRANSISTOR COUNT:

METALLIZATION:

72

Type: AI, 1% Cu
Thickness: 16kA ±2kA

PROCESS:
Junction Isolated Bipolar/JFET

PASSIVATION:
Type: Nitride
Thickness: 7kA ±C.7kA

Metallization Mask Layout
HA-474l
-IN4

+IN4

v-

+IN3

-IN3

OUT3

OUT4

OUT2

OUTl

-IN1

+IN1

V+

3-296

+IN2

-IN2

HA-5002

HARRIS
SEMICONDUCTOR

110M Hz, High Slew Rate,
High Output Current Buffer

November 1996

Features

Description

• Voltage Gain .............................. 0.995

The HA·5002 is a monolithic, wideband, high slew rate, high
output current, buffer amplifier.

• High Input Impedance. . . . . . . . . . . . . . . . . . .. 3000kn

Utilizing the advantages of the Harris 0.1. technologies, the
HA·5002 current buffer offers 1300V/~s slew rate with
11 OM Hz of bandwidth. The ±200mA output current capability
is enhanced by a 30 output impedance.

• Low Output Impedance. . . . . . . . . . . . . . . . . • . . . .. 30
• Very High Slew Rate ....................

1300Vl~s

• Very Wide Bandwidth ............•....... 110MHz
• High Output Current ..............•...... ±200mA
• Pulsed Output Current ............•....... 400mA
• Monolithic Construction

Applications
• Line Driver
• Data Acquisition

The monolithic HA·5002 will replace the hybrid LH0002 with
corresponding performance increases. These characteristics
range from the 3000kO input impedance to the increased
output voltage swing. Monolithic design technologies have
allowed a more precise buffer to be developed with more than
an order of magnitude smaller gain error.
The HA-5002 will provide many present hybrid users with a
higher degree of reliability and at the same time increase
overall circuit performance.
For the military grade product, refer to the HA-5002l883
datasheet.

Ordering Information

• 110MHz Buffer

PART NUMBER
(BRAND)

• High Power Current Source

PACKAGE

HA2-5002-2

·55 to 125

B Pin Metal Can

TB.C

HA2-5002-5

B Pin Metal Can

TB.C

B Ld PDIP

EB.3
N20.35

PKG.NO.

• Sample and Holds

HA3-5002-5

o to 75
o to 75

• Radar Cable Driver

HA4P5002-5

Oto 75

20 Ld PLCC

HA7-5002-2

-55 to 125

B Ld CERDIP

F8.3A

HA7-5002-5

o to 75
o to 75

B Ld CERDIP

FB.3A

B Ld SOIC

MB.15

B Ld SOIC

MB.15

• Video Products

HA9P5002-5
(H50025)
HA9P5002-9
(H50029)

-40 to B5

Pinouts
HA-5002 (PDIP, CERDIP, SOIC)
TOP VIEW

HA-5002 (PLCC)
TOP VIEW

HA-5002 (METAL CAN)
TOP VIEW
IN

OUT

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

3-297

etC/)
O!!!
-I&.

~:J
a: a..

TEMP.
RANGE (DC)

• High Power Current Booster

...I

Za:

File Number

2921.2

w::e

~et

HA-5002
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 44V
Input Voltage ..............••................... V1+toV1Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . .. ±200mA
Output Current (50ms On, 1s Off) ................... ±400mA

Thermal Resistance (Typical, Note 2)
9JA (OC/W) 9JC (OC/W)
CERDIP Package
115
28
PDIP Package
92
N/A
Metal Can Package
155
67
PLCC Package
74
N/A
SOIC Package
157
N/A
Maximum Junction Temperature (Hermetic Packages, Note 1) ... 175°C
Maximum Junction Temperature (Plastic Packages, Note 1) ..... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............. 300°C
(PLCC and SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5002-2 ............................... -55°C to 125°C
HA-S002-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 7SoC
HA-S002-9 ..............•................. -40°C to 85°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 17SoC for
the ceramic and can packages, and below 1S0oC for the plastic packages.
2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±12V to±1SV, Rs = SOU, RL = 1kO, c L = 10pF, Unless Otherwise Specified
TEST
CONDITIONS

PARAMETER

TEMPi
(DC)

I

HA-5002-2
MIN

TYP

MAX

I
I

HA-5002-5, -9
MIN

TYP

MAX

I

UNITS

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Input Resistance

25

5

20

5

20

Full

10

30

-

10

30

Full

30

-

30

mV
mV

25

2

7

-

2

7

Full

3.4

10

-

2.4

10

jlA

3

-

1.S

3

-

18

-

MO
jlV p _p

0.900

-

VN

0.971

-

VN

-

MHz

Full

1.S

jlV/"C
jlA

10Hz-1MHz

25

18

-

RL=500

25

0.900

-

RL = 1000

25

0.971

-

RL = 1kO

25

-

0.995

-

RL = 1kO

Full

0.980

-

0.980

V 1N = 1Vp•p

25

-

110

-

110

25

-

40

-

40

RL= 1000

25

±10

±10.7

±10

±11.2

V

RL = 1kO, Vs = ±15V

Full

±10

±13.5

±10

±13.9

V

RL = 1kO, Vs = ±12V

Full

±10

±10.5

±10

±10.5

V

V1N = ±10V, RL = 400

25

-

220

mA

-

3

10

0

<0.005

-

%

-

20.7

Input Noise Voltage
TRANSFER CHARACTERISTICS
Voltage Gain
(VOUT = ±10V)

-3dB Bandwidth
AC Current Gain

0.995

VN
VN
AlmA

OUTPUT CHARACTERISTICS
Output Voltage Swing

Output Current
Output Resistance
Harmonic Distortion

V1N = 1VRMS, f= 10kHz

220

-

Full

3

10

25

<0.005

-

TRANSIENT RESPONSE
20.7

25

-

2S

1.0

-

0.06
0.22

Full Power Bandwidth (Note 3)

25

Rise Time

25

Propagation Delay

25

Overshoot
Slew Rate
Settling Time

To 0.1%

25

Differential Gain

RL = 5000

25

Differential Phase

RL = 5000

25

3-298

MHz

3.6

-

3.6

ns

2

2

ns

30

-

-

30

%

1.3

-

1.0

1.3

V/ns

50

-

-

50

-

0.06

-

0.22

ns

-

%
Degrees

HA-5002
Electrical Specifications

VSUPPLY = ±12V to±15V, Rs = 50Q, RL = lkQ,
TEST
CONDITIONS

PARAMETER

TEMP
(OC)

cL=

10pF, Unless Otherwise Specified (Continued)

HA-S002-2
MIN

TYP

HA-S002-S, -9
MAX

I

MIN

TYP

MAX

I
I

UNITS

POWER REQUIREMENTS
Supply Current

8.3

25
Full

Power Supply Rejection Ratio

Av = 10V

Full

54

-

8.3

10

-

64

54

64

rnA
10

rnA
dB

NOTE:

3. FPBW

= Slew Rate;

Vp

= tOV.

2"V PEAK

Test Circuit and Waveforms
+15V
Rs

IN

o-.JoI<>/V--I >--'9---0 OUT

FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE
...J



8SA = Heat Sink to Ambient Thermal Resistance

~

~~

0.4

Graph is based on:
0.2
0.0
25

65

45

85

105

125

TEMPERATURE (OC)

FIGURE 2. FREE AIR POWER DISSIPATION

Typical Application
.oJ
«(I)

Za:

O!!!
-LL

t:c:J

a: a..

W::!i

~«

FIGURE 3. COAXIAL CABLE DRIVER - SOQ SYSTEM

Typical Performance Curves
9

9
Vs

6

iii"

GAIN

0

~

-3

6 I-

11111

3

~

IIIII
PHASE

LIJ

~

= ±15V, Rs = son

-6

!:i

~ -9
-12
-15
-18

1

10

3

r\
\
\

,
"

LIJ

~~

III"
IIIII
PHASE

-6

-9

...

:\
\

-12

~

-15

1

FREQUENCY (MHz)

10

;:
III
LIJ

1350

if

100

FREQUENCY (MHz)

=1kQ)

FIGURE 5. GAINIPHASE vs FREQUENCY (RL

3-301

t:

45°

900

180"

-18

100

FIGURE 4. GAINIPHASE vs FREQUENCY (RL

=±15V, Rs =50n
Ici~I~1

iii"
~ 0
z
~ -3
Cl

Vs

=SOQ)

~

HA-5002
Typical Performance Curves

(Continued)
0.998

0.994

Vs =±15V

Vs = ±15V

0.992

....

0.997

0.990

~
z

C(

CI

w

VOUT = ·10V TO +10V

"'"

0.986
0.984

C(

1"'0 ........

0.982

g

0.980

~

~

0.996

.... ....

JOU~=10~O!10~

~

........

0.995

........ ""-

CI
1""""' ....

~

!j

~z

0.988

w

r-. ....

CI

0.994

g

0.993

~
;.a

0.978

.... 1-- 1"'0 ....

~

"""

0.992

-40

·20

0

20

40

60

80

100

VO UT =OTO ·10V

1"" ..

0.991
·60

120

1':--. ..

- .... ........ 1--"",

0.976
0.974
·60

-

·40

·20

0

TEMPERATURE (DC)

20

40

60

80

100

120

TEMPERATURE ("C)

FIGURE 6. VOLTAGE GAIN VB TEMPERATURE (RL

=100g)

FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (RL = 1kg)

7

Vs = ±15V

Vs =±15V
6

""- .........

"""

..... "'"

....
....

·9
·10
·11
-60

·40

·20

0

20

40

60

5

~

4

8

3

a::
a::

-

80

~

~m

~

100

"

r- ~

2

o

120

........

-60

·40

·20

14

«
So

+VOUT

w

13

80

100

120

Vs = ±15V,l oUT = OmA

Vs = ±15V, RLOAD = 100,1

~

60

10

15

g
5
~
0

40

FIGURE 9. BIAS CURRENT vs TEMPERATURE

FIGURE 8. OFFSET VOLTAGE VB TEMPERATURE

CI

20

TEMPERATURE (DC)

TEMPERATURE ("C)

€

0

~-

!.

.. "" ~"'""

I

!z
Il!a::

-

.VOUT

8

7

::I

o

~

6

~

5

...

1-- ...

12

9

Ul

... ~

-

4
11
-60

-40

·20

0

20

40

60

80

100

3
-60

120

TEMPERATURE (DC)

FIGURE 10. MAXIMUM OUTPUT VOLTAGE

-40

·20

0

20

40

60

80

100

TEMPERATURE (DC)
VB

TEMPERATURE

3-302

FIGURE 11. SUPPLY CURRENT vs TEMPERATURE

120

HA-5002
Typical Performance Curves
10

11250C~ 25°C I

lOUT = OmA
:(

§.

J

to-

ffi

II:
II:

6

o

-'

4

8:

:::>
Ul

~

Vs =±15V

lOOK

~550C

g

2

-

1'-- ..
ZIN

.........

w

z

1§
~

.........
..... 1"-

100
10

4

6

8

10

12

14

16

louT

1
lOOK

18

......

~ ~: f-----::::;

70

TA

iii" 50
:2-

'"

!E

40

~

30

~ l1f-----------f---------~~~,~~----_l

20

9f-----~----_+-~~~~~~

10

,
..........

~ 101-----------I----------I-,~~~-""O~--__I
........

. .,~~Q

8f------t-----~--~

715

8

12

V

1300

w

./

1200

-' 1100
1000

10M

..-- ..--

/'

Vs =±15V
TA = 25°C

100

>
§.

50

:>

0

z

;..

~

~ ·50

I

·100

900
6

100M

FIGURE 15. PSRR vs FREQUENCY

f~

~

Ul

1M

150

1400

~

lOOK

FREQUENCY (Hz)

1500

<-

W:i

~c(

r\

10K

FIGURE 14. VOUT MAXIMUM vs VSUPPLY

Oi

"i'

o

5

SUPPLY VOLTAGE (±V)



>

(Continued)

8

10

12

14

16

-150 L---L__-'-__..L..__L---'__- ' -__....L....__.L.--''--...:::l
-10
-8
-6
-4
-2
0
2
4
6
8
10

18

SUPPLY VOLTAGE (±V)

INPUT VOLTAGE (VOLTS)

FIGURE 17. GAIN ERROR vs INPUT VOLTAGE

FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE

3-303

HA-5002
Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

V1-

81 mils x 80 mils x 19 mils
2050~m x 2030~m x 483~m

TRANSISTOR COUNT:

METALLIZATION:

27

Type: AI, 1% Cu
Thickness: 20kA ±2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride
Thickness: 7kA ±O.7kA

Metallization Mask Layout
HA-5002

OUT

3-304

~-5004
rent Feedback Amplifier

November 19

Features

Description

• Slew Rate ••••••••••••••••••••••••••••• l200V/J18

The HA-5004 current feedback amplifier Is a videolwideband
amplifier optimized for low gain applications. The design is
based on current·mode feedback which allows the amplifier
to achieve higher closed loop bandwidth than voltage-mode
feedback operational amplifiers. Since feedback is
employed, the HA-5004 can offer better gain accuracy and
lower distortion than open loop buffers. Unlike conventional
op amps, the bandwidth and rise time of the HA-5004 are
nearly Independent of closed loop gain. The 100MHz band·
width at unity gain reduces to only 65MHz at a gain of 10.
The HA-5004 may be used in place of a conventional op
amp with a significant improvement In speed power product.

• Output Current •••••••••••••••••••••••••• ±l00mA
• Drives ••••••••••••••.••••.•..••••. ±tV Into loon
• VSUPPLY ••••••••••••••••••••••••••••• ±5V to ±18V
• Thermal Overload Protection and Output Flag
• Bandwidth Nesrly Independent of Gain
• Output Enable/Disable

Applications
• Unity Gain VldeolWldeband Buffer

Several features have been designed in for added value. A
thermal overload feature protects the part against excessive
junction temperature by shutting down the output. If this fea·
ture Is not needed, it can be inhibited via a TTL input (TOI).
A TTL chip enable/disable (OE) is also provided; when the
chip is disabled its output is high impedance. Finally, an
open collector output flag ('i'O[) is provided to indicate the
status of the chip. The status flag goes low to indicate when
the chip is disabled due to either the internal Thermal Over·
load shutdown or the external disable.

• Video Gain Block
• High Speed Peak Detector
• Fiber Optic Transmitters
• Zero Insertion Loss Transmisalon Line Drivers
• Current to Voltage Converter
• Radar Systems

Ordering Information
TEMP.
RANGE ("C)

PACKAGE

HAl-5004-5

01070

14LdCERDIP

F14.3

HA1-5004-9

-401085

14LdCERDIP

F14.3

PART NUMBER

PKG.NO.

In order to maximize bandwidth and output drive capacity,
internal current limiting is not provided. However, current lim·
iting may be applied via the Vc+ and Vc' pins which provide
power separately to the output stage.
For Military grade product refer to the HA-5004l883 data
sheet.

Pinout
HA-5004
(CERDlP)
TOP VIEW

TRUTH TABLE

OE

TOI

TJ

fO[OUTPUT
(OPEN
COLLECTOR)

0

0

Normal

1

Normal

0

0

High

0

Auto Shutdown,

INPUTS

Vc-

VEE
......._-n2l·IN

TEMP

(Note)

OPERATION

HI·ZOUT

0

1

X

1

Normal

1

X

X

0

ManualShutdown,
HI·ZOUT

NOTE: >1800C Typical

CAUTION: These devices are sensRIve to eIecIrostattc discharge. Users ahoukllollow proper IC HandUng Procedures.
CopyrIght Harris Corporation 1996

«>

3-305

File Number

2923.2

Ci!rn
Za::

Ow

ti§
a:: 0.
W::E

o0.0(

HA5013
Triple, 125MHz Video Amplifier

November 1996

Features

Description

• Wide Unity Gain Bandwidth •.••••••..••..• 125MHz

The HA5013 is a low cost triple amplifier optimized for RGB
video applications and gains between 1 and 10. It is a
current feedback amplifier and thus yields less bandwidth
degradation at high closed loop gains than voltage feedback
amplifiers.

• Slew Rate .••••••••.•.••.•.•..••.•••..•• 475V/!1S
• Input Offset Voltage ...• , ..••••.•..•.•..•.. BOOIlV
• Differential Gain. . . . . . . . . . • • • • • • • . . • • . • • •• 0.03%
• Differential Phase. • . . . . . • . • • • • • • • . .• 0.03 Degrees
• Supply Current (Per Amplifier) •..•.••••••••. 7.5mA
• ESD Protection. . • • • . • • • • • • • • . • • • • • • • • • • •• 4OO0V
• Guaranteed Specifications at ±5V Supplies
• LowCost

Applications

The low differential gain and phase, 0.1 dB gain flatness, and
ability to drive two back terminated 750 cables, make this
amplifier ideal for demanding video applications.
The current feedback design allows the user to take
advantage of the amplifier's bandwidth dependency on the
feedback resistor.
The performance of the HA5013 is very similar to the popular Harris HA-5020 single video amplifier.

Ordering Information

• PC Add-On Multimedia Boards
• Flash AID Driver

PART NUMBER

TEMP.
RANGEfC)

PKG.
NO.

PACKAGE

• Color Image Scanners

HA50131P

-401085

14Ld PDIP

E14.3

• CCD Cameras and Systems

HA50131B

-401085

14 Ld sOle

M14.15

• RGB Cab'e Driver

HA5025EVAL

High Speed Op Amp DIP Evalualion Board

• RGB Video Preamp
• PC Video Conferencing

Pinout
HA5013
(PDIP, SOIC)
TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-306

File Number

·3654.3

HA5013
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 36V
DC Input Voltage ............................... ±VSUPPLY
Dilferentiallnput Voltage ............................... 10V
Output Current (Note 2) ................ Short Circuit Protected
ESD Rating (Note 4)
Human Body Model (Per MIL-STD-883 Method 3015.7) .. 2000V

Thermal Resistance (Typical, Note 1)

Operating Conditions

8JA (oCIW)

PDIP Package .................. '" . . . ... . .
100
120
SOIC Package.............................
Maximum Junction Temperature (Die Only, Note 3) .......... 175°C
Maximum Junction Temperature (Plastic Package, Note 3) .. 150°C
Maximum Storage Temperature Range ., . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............. 300°C
(SOIC - Lead Tips Only)

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Supply Voltage Range (Typical) ................. ±4.5V to ±15V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.
2. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty
cycle) output current should not exceed 15mA for maximum reliability.
3. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below
150°C for plastic packages. See Application Information section for safe operating area information.
4. The non-inverting input of unused amplifiers must be connected to GND.

Electrical Specifications

VSUPPLY

PARAMETER

=±5V, RF =1kO, "'" =+1, RL =4000, CL ~1 OpF, Unless Otherwise Specified
TEST CONDITIONS

...I
c(Ul

(NOTE 9)
TEST
LEVEL

TEMP.

fC)

MIN

TYP

MAX

UNITS

A

25

-

0.8

3

mV

-

5

mV

-

1.2

3.5

mV

Za:

a:c.

INPUT CHARACTERISTICS
Input Offset Voltage (VIO)

Delta VIO Between Channels
Average Input Offset Voltage Drift
VIO Common Mode Rejection Ratio

VIO Power Supply Rejection Ratio

Input Common Mode Range

V CM

=±2.5V (Note 5)

±3.5V ~ Vs ~ ±6.5V

VCM

=±2.5V (Note 5)

Non-Inverting Input (+IN) Current

+IN Common Mode Rejection
(+IBCMR

r)

=+

VCM

=±2.5V (Note 5)

IN

+IN Power Supply Rejection

±3.5V ~ Vs" ±6.5V

Inverting Input (-IN) Current

Delta - IN BIAS Current Between Channels

-IN Common Mode Rejection

O!!:!
-u..
~:::i

V CM

=±2.5V (Note 5)

3-307

A

Full

A

Full

W::!!i

B

Full

-

5

-

flVPC

A

25

53

-

-

dB

A

Full

50

A

25

60

-

A

Full

55

-

dB
dB
dB

A

Full

±2.5

-

-

V

A

25

-

3

8

JiA

A

Full

/lA

25

-

20

A

0.15

J1A/V

A

Full

0.5

J1A/V

A

25

0.1

J1A/V

A

Full

0.3

J1A/V

A

25,85

4

12

/lA

A

-40

10

30

/lA

A

25,85

6

15

/lA

A

-40

10

30

/lA

A

25

-

-

0.4

J1A/V

A

Full

-

1.0

J1A/V

-

-

~c(

HA5013
Electrical Specifications

VSUPPLY= ±5V, RF = 11<0, "'" =+1, Rl

PARAMETER
-IN Power Supply Rejection

TEST CONDITIONS
±3.5V S Vs S ±6.5V

=4000, Cl S10pF, Unless Otherwise Specified

(Continued)

(NOTE 9)
TEST
LEVEL

TEMP.
(IIC)

MIN

TYP

MAX

UNITS

A

25

-

-

0.2

fJAN

A

Full

-

-

0.5

fJAN

4.5

-

nVNFiZ

2.5

pANFil

25.0

-

Input Noise VoHage

f= 1kHz

B

25

+Input Noise Current

f .. lkHz

B

25

-Input Noise Current

f= 1kHz

B

25

VOUT=:I:2.5V (Note 11)

A

25

1.0

-

-

MO

A

Full

0.85

-

-

MO

25

70

-

dB

-

pANFil

TRANSFER CHARACtERISTICS
Transimpadance

Opan Loop DC Voltaga Gain

Rl = 4000, VOUT =
:I:2.5V

A
A

Full

65

Open Loop DC Voltage Gain

Rl= 1000, VOUT=
:I:2.5V

A

25

50

-

-

A

Full

45

-

-

dB

RL= 1500

A

25

:1:2.5

±3.0

-

V

A

Full

:1:2.5

±3.0

-

B

Full

±16.6

:1:20.0

A

Full

±40

±SO

-

dB
dB

OUTPUT CHARACTERISTICS
Output Voltage Swing

Output Current

Rl= 1500

Short Circuit Output Current

VIN = :I:2.5V, VOUT

=OV

V

rnA
rnA

POWER SUPPLY CHARACTERISTICS
Supply Voltage Range

A

25

5

-

15

V

Quiescent Supply Currant

A

Full

-

7.5

10

mAIOp
Amp

B

25

275

350

-

AC CHARACTERISTICS"", = +1
Slew Rata

Note 6

Full Power Bandwidth (Nota 7)

B

25

22

28

VOUT = lV, Rl = 1000

B

25

-

6

Fall Time (Note 8)

VOUT = lV, Rl = 1000

B

25

-

6

Propagation Delay (Note 8)

VOUT = lV, Rl = 1000

B

25

B

25

-

4.5

Risa Time (Note 8)

Overshoot
-3dB Bandwidth

VOUT= l00mV

B

25

Settling Time

To 1%, 2V Output Step

B

25

Settling Time

To 0.25%, 2V OutputStap

B

25

-

Nota 6

B

25

B

6

125
50

-

V/fJS
MHz
ns

-

ns

-

MHz

ns
%

ns

75

-

ns

-

475

-

V/fJS

25

-

26

AC CHARACTERISTICS "'" = +2, RF" 6810
Slew Rate

Rise Time (Note 8)

VOUT = lV, Rl- 1000

B

25

-

6

-

Fall Time (Note 8)

VOUT = lV, Rl" 1000

B

25

-

6

-

Full Power Bandwidth (Nota 7)

3·308

MHz

ns

ns

HA5013
Electrical Specifications

VSUPPLY = ±5V, RF = 1kO, Av = +1, RL = 4000, CL :;;10pF, Unless Otherwise Specified (Continued)

PARAMETER
Propagation Delay (Note 8)

TEST CONDITIONS
VOUT = IV, RL = 1000

Overshoot

(NOTE 9)
TEST
LEVEL

TEMP.
fC)

B

25

B

25

·3dB Bandwidth

VOUT= 100mV

B

25

Settling Time

To 1%, 2V Output Step

B

25

Settling Time

To 0.25%, 2V Output Step

B

25

Gain Flatness

5MHz

B

20MHz

Note 6

MIN

-

TYP

MAX

UNITS

6

-

ns

12

-

%

95

-

MHz

-

50

25

-

0.02

B

25

-

0.07

B

25

350

475

-

VIlIS

B

25

28

38

-

MHz

-

8

-

9

-

100

ns
ns
dB
dB

AC CHARACTERISTICS Av = +10, RF = 3830
Slew Rate
Full Power Bandwidth (Note 7)
Rise Time (Note B)

VOUT = IV, RL = 1000

B

25

Fall Time (Note B)

VOUT = tv, RL = 1000

B

25

Propagation Delay (Note B)

VOUT = IV, RL = 1000

B

25

B

25

Overshoot
-adB Bandwidth

VOUT= 100mV

B

25

Settling Time

To 1%, 2V Output Step

B

25

To 0.1%, 2V Output Step

B

25

Differential Gain

RL = 1500, (Note 10)

B

25

Differential Phase

RL = 1500, (Note 10)

B

25

-

9
I.B

ns
ns
ns
%

65

-

MHz

75

-

ns

130

ns

VIDEO CHARACTERISTICS

-

0.03
0.03

%

-

NOTES:
5. At ·40oC Product is tested at VCM = ±2.25V because Short Test Duration does not allow self heating.
6. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
Slew Rate
7. FPBW = 2 V
; V pEAK = 2V.
" PEAK
8. Measured from 10% to 90% pOints for risellall times; from 50% points of input and output for propagation delay.
9. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only.
10. Measured with a VM700A video tester using an NTC· 7 composite VITS.
11. At -40°C Product is tested at VOUT = ±2.25V because Short Test Duration does not allow self heating.

3-309

Degrees

..J

etC/)
Za:
O!!:!
-II..

!;;::::i
a: a..

W:i

~et

HA5013
Test Circuits and Waveforms

son
HP4195
NETWORK
ANALYZER

son

I

FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS

'". f'a

VOUT

VOUT

son

FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT

FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT

=

Vertical Scale: VIN = 100mV/Div., VOUT = 100mV/Div.
Horizontal Scale: 20ns/Div.

Vertical Scale: VIN 1V/Div., VOUT
Horizontal Scale: SOns/Diy.

=lV/Div.

FIGURE 5. LARGE SIGNAL RESPONSE

FIGURE 4. SMALL SIGNAL RESPONSE

3-310

Schematic

(One Amplifier of Three)

V+

~.~K

R2

~----~r-~~-------r--

Q"~

o...l

I

II ~~,
apl0

~

5~

~Qp2

•

Q

--.-.;
R28
20

QN13

+IN

r•=---+------r--r
I

R3

I!!:"'QPI3

+QN2

~

~
1 •4 PF
T
QN1S

2

g:.....
Co)

r
R21

•

R14

ttN4

R32

280 QNI4)j
KQN7

S

QNI9~

R13

aN3

~

140

!:::::'QN10

QP7>J-

O
l

_Cl

1'1.4pF

-IN
R12
280

6K

t

Ir

QplS

P12

Rl

~QNl

R29
9.5

t:::.. apS

I ,
QNS?

'"~.....

~

oJ

800

lK
R16

R23 J.R 26

400

400 $200

C,

';R30

7
______ OUT

V-a

1

1 11
R4

800

R33
800

f=:o

lQN~QNll

1

OPERATIONAL
AMPLIFIERS

1 11

11

HA5013

Application Information

Driving Capacitive Loads

Optimum Feedback Resistor

Capacitive loads will degrade the amplifier's phase margin
resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as
shown in Figure 6.

The plots of inverting and non-inverting frequency response,
see Figure 8 and Figure 9 in the typical performance section,
illustrate the performance of the HA5013 in various closed loop
gain configurations. Although the bandwidth dependency on
closed loop gain isn't as severe as that of a voHage feedback
amplifier, there can be an appreciable decrease in bandwidth at
higher gains. This decrease may be minimized by taking
advantage of the current feedback amplifier's unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications,
and RF, in conjunction w~h the intemal compensation capacitor, sets the dominant pole of the frequency response. Thus,
the amplifier'S bandwidth is inversely proportional to RF. The
HA5013 design is optimized for a 10000 RF at a gain of +1.
Decreasing RF in a unity gain application decreases stability,
resuHing in excessive peaking and overshoot. At higher gains
the amplifier is more stable, so RF can be decreased in a tradeoff of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
GAIN

(AcLl

RF(O)

-1
+1
+2

750

+5
+10
-10

1000
681
1000
383
750

BANDWIDTH
(MHz)

....

VIN
RT

R

rP

"::,..::'

VOUT

±~

RF
R,

~
FIGURE 6. PLACEMENT OFTHE OUTPUT ISOLATION
RESISTOR,R

The selection criteria for the isolation resistor is highly
dependent on the load, but 270 has been determined to be
a good starting value.

Power Dissipation Considerations

100
125

Due to the high supply current inherent in triple amplifiers,
care must be taken to insure that the maximum junction temperature (TJ' see Absolute Maximum Ratings) is not
exceeded. Figure 7 shows the maximum ambient temperature versus supply voHage for the available package styles
(PDIP, SOIC). At Vs ±5V quiescent operation both package styles may be operated over the full industrial range of
-40°C to asoC. It is recommended that thermal calculations,
which take into account output power, be performed by the
designer.

95
52
65
22

=

PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors
and chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short especially for the power supply decoupling components and
those components connected to the inverting input.

130 r-~.,...-r-.,...-r-.,...-r--.---'r--r--'--'
120 t--...i""'-;;::-'If"""o"".......
~+~DIP -t----l-+--+-t--+--I
'; 110 t--f-.......
-P""oI::::--P'......~t--+-t--+---lt--+-I
~ 100~r-+--+~~~d-~-+~~~d-~--t--I--I

Attention must be given to decoupling the power supplies. A
large value (10IlF) tantalum or electrolytic capacitor in parallel with a small value (0.1IlF) chip capacitor works well in
most cases.
A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier's inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. It is recommended that the ground plane be removed under traces connected to -IN, and that connections to -IN be kept as short as
possible to minimize the capacitance from this node to
ground.

3-312

G'

ij 90~r-+--+--r-~-I~~~~---I~~~~~~
~ 80 t--t--_t_-t--+--+SOIC...........

m 70

......

i".

......

ffi

~
60t--~_t_-t--+--+-t--+-41__4__+~~

-

50r-r--r-r--r-r--r-r--r-r--r~~

i

30

~ ~r-r--r-r--r-r--r-r--r~r--r~~
~r-r--r-r--r-r--r-r--r-r--r~~
10~~~-~~-~~-~~-~~~~

5

7

9

11

13

15

SUPPLY VOLTAGE (±V)

FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE
va SUPPLY VOLTAGE

HA5013

=

Typical Performance Curves

II

YOUT " 0.2Vp..p
CL,,10pF

r

5

.I I I}..!. I
Av-+1,RF/IUl_

_I.!

YOUT " 0.2Vp..p
4 I - CL,,10pF
ii' 3 I - RF·7500

Av " 2, RF ,,8810
I

.
-3

1',.

2

I

1'2 r-

Ie:

.

"

100

-6

200

~

f

10

'"

Av" +1, RF .. 11Ul

\.
100

Av=+1

lc.a BANDWIDTH

:'"

"'~

IIII ~.

,.V"- t---. ....

1III

100

GAIN PEAKING

200

500

700

FREQUENCY (MHz)

FIGURE 10. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY

oJ

ern

YOUT =0.2Vp..p
CL,,10pF
"-

rl"

Av ••10, RF - 7500

10

200

FREQUENCY (MHz)

I,"

~ ~~

YOUT • 0.2Vp..p
CL-10pF

V

"

I 111111

~.\

2

~

I
2

·100

i~

/

Av--6

Av-·1,RF·7500
"'llll1iIIo.
Av-+10, Rp'• •,m

, ·135

Av=·2
~

FIGURE 9. INVERTING FREQUENCY RESPONSE

FIGURE 8. NON·INVERTING FREQUENCY RESPONSE

1=

--"""">

Av,,·1

-3

10
FREQUENCY (MHz)

-

'/

1

1 J

I

oS

Av,,·1

2

I
~ .~

1
~

Av-10,RF·

1

...-

I

Av-5,RF-1""

........ ....

=1kn, RL = 4000, TA =2SoC,

VSUPPLY ±5V, Av" +1, RF
Unless Otherwise Specified

za:
O!!:/
-u..

-

--

~:J

a:Q.
W::E
~e

-r- r-... ....

800
1100
1300
FEEDBACK RESISTOR (0)

FIGURE 11. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE

130
YOUT - O.2Vp.p

~

~_10pF

r--... ""'-

Av-+2

./
-3da BANDWIDTH

~

-

"1111\,.

"V "1-0..

GAIN PEAKING
350

500

,120

i::

.........

I

-

~ /~

10

80

850
800
NO
FEEDBACK RESISTOR (0)

FIGURE 12. BANDWIDTH AND GAIN PEAKING va FEEDBACK
RESISTANCE

Y-3da a:..DWlDTH

l-

•

I"-

,<

-

lV
o

200

~ I'"'"

GAIN PEAKING I-- YOUT" O.2Yp.p

1I I

400
800
LOAD RESISTOR (0)

~_10pF

Av-+1
800

o

1000

FIGURE 13. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE

3·313

6

HA5013
Typical Performance Curves

VSUPPLY = ±5V, Av = +1, RF = 1kQ, RL = 400Q, TA = 25°C,
Unless OthelWise Specified (Continued)
16r---------~_,--_.--,_--~_,--_.--,

80

1-

"" " \.

\

o

200

VOUT = 0.2Vp.p
CL = 10pF
Av = +10

\ .....

~

BOO

500
650
FEEDBACK RESISTOR (0)

350

":!S

0.06

""I . . . . . . .

I

/

II:

/

V

....I

!z:III

0.04

RL = 750

V

IL
IL

"

0.02

0.00

5

3

""

""""

A.
RL= 1500

III

C

7

9

11

0.06

~

0.04

e.

I --'-

'"

~

13

RL=l~OO

0.02

~

RL=lkn

FREQUENCY = 3.58MHz

Ili!

Q

0.00

15

3

If

FIGURE 16, DIFFERENTIAL GAIN VB SUPPLY VOLTAGE

o I-

VOUT = 2.0Vp_p
CL=30pF

I
5

7

11
9
SUPPLY VOLTAGE (±V)

~
~ i;'

I
HD~

'U
-60

z

3RD ORDER IMD
-70

Q

-80

13

15

AV= +1

-10

-so

~
~

\

~

FIGURE 17. DIFFERENTIAL PHASE VB SUPPLY VOLTAGE

-40

III

RL = 750

~

~=lkn~

SUPPLY VOLTAGE (±V)

:g.

1000

0.08
FREQUENCY = 3.58MHz

<

800

FIGURE 15. SMALL SIGNAL OVERSHOOT VB LOAD
RESISTANCE

0.10

0.08

600

LOAD RESISTANCE (0)

FIGURE 14. BANDWIDTH VB FEEDBACK RESISTANCE

tz

400

200

950

--

~

./

I

-20

o

-30

~

I~~

~

HD3

~

-50

f-

~ -60

CMRR

3.

~

-70

10
FREQUENCY (MHz)

FIGURE 18. DISTORTION VB FREQUENCY

0.001

--

NEGATIVE PSRR
I I

-80

-"""""'HD3

-90
0.3

~

z-40

II~

HD2,

~

POSITIVE PSRR
0.01

111111

I I 111111

11111

1111111

0.1
FREQUENCY (MHz)

10

FIGURE 19. REJECTION RATIOS VB FREQUENCY

3-314

30

HA5013
Typical Performance Curves

VSUPPLY = ±SV, Av = +1, RF = 1kQ, RL = 400Q, TA = 25°C,

Unless Otherwise Specified (Continued)
12

8.0
RL= 1000

...
S

...w~

Your = 1.0Vp_p
7.5

Z

7.0

IeCI
~

IfII.

-r--..

V
/

Q

Q

6.5

...

,,/

/

"..,.,

-"'"

"

-50

....

500

--

.

400

~ 350
w

300

~

...w

1

..........

Av=+l,RF=lkO

o

25
50
75
TEMPERATURE (oC)

-25

Your = 20Vp_p

450

250

III

1

Av=+2,RF=6810 -

.... i---

100

..V

200

+ SLEW RATE

--

-- -

0.8

I

r--......

iii"
:E.

0.2

~
CI
Q

w

~
II:

0

z

-25

...J

:

-

Ay:'l~ \ \

5

10

"-

, 1/

/

'{

15

a.

600

iii
sa0

400

!zw

isz

Ay=-5

-1.2

800,

sw

,/

'\., ""'-~ ~

c(

::i -0.4

1000

100

Av=-l

w

CI

-

z

40

~

~

II:
II:

~

200 U

20

Av=-2

"'

20

1
25

0
0.01

30

FREQUENCY (MHz)

FIGURE 24. INVERTING GAIN FLATNESS VB FREQUENCY

0.1

1
FREQUENCY (kHz)

10

0
100

FIGURE 25. INPUT NOISE CHARACTERISTICS

3-315

W:E

~mAm:E=OV

Full

0

5

7.5

mA

Disable Pin Input Current

'DiSAIJI:E .. OV

Full

0

1.0

1.5

mA

Quiescent Supply Current (Note 14)

Minimum Pin 8 Current to Disable (Note 16)

Full

Maximum Pin 8 Current to Enable (Note 5)

Full

350
0

0

IlA

0

0

20

ItA

AC CHARACTERISnCS (f;y .. +1)
Slew Rate (Note 17)

25

215

400

0

VlIlS

Full Power Bandwidth (Note 18)

25

22

28

0

MHz

Rise Time (Note 8)

25

0

6

0

ns

Fall Time (Note 8)

25

0

6

0

ns

Propagation Delay (Note 8)

25

0

6

0

ns

Overshoot

%

25

0

4.5

0

o3dB Bandwidth (Note 14)

VOUT= 100mV

25

0

125

0

MHz

Settling Time to 1%

2V Output Step

25

0

50

0

ns

Settling Time to 0.25%

2V Output Step

25

0

75

0

ns

Slew Rate (Note 17)

25

0

475

0

VIIJ.S

Full Power Bandwidth (Note 18)

25

0

26

0

MHz

Rise Time (Note 8)

25

0

6

-

ns

Fall Time (Note 8)

25

-

6

ns

Propagation Delay (Note 8)

25

-

-

6

-

ns

Overshoot

25

0

12

AC CHARACTERISnCS (f;y = +2, RF" 6810)

0

-

%

-3dB Bandwidth (Note 14)

VOUT= 100mV

25

0

95

MHz

sattllng Time to 1%

2V Output Step

25

0

50

Settling Time to 0.25%

2V Output Step

25

0

100

-

ns

ns

AC CHARACTERlsnCS (f;y .. +10, RF .. 3830)
Slew Rate (Note 17)

25

350

475

-

V/Jl.s

Full Power Bandwidth (Nota 18)

25

28

38

0

MHz
ns

Rise Time (Note 8)

25

0

8

0

Fall Time (Note 8)

25

0

9

0

ns

Propagation Delay (Note 8)

25

0

9

0

ns

Overshoot

25

-

1.8

0

o3dB Bandwidth (Note 14)

VOUT= 100mV

25

0

85

-

Settling Time to 1%

2V Output Step

25

-

75

0

3-324

%
MHz
ns

HA-5020
Electrical Specifications

V+ = +5V, V- = -5V, RF = 1kn, "'" = +1, RL = 400n, C L S;10pF, Unless Otherwise Specified.
Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect
lot-to-Iot variation. (Continued)

PARAMETER
Settling Time to 0.25%

TEST CONDITIONS

HA-5020-5. -9

TEMP.
("C)

MIN

TYP

MAX

UNITS

130

-

ns

4.5

-

nVNHz

2V Output Step

25

Input Noise Voltage (Note 14)

f= 1kHz

25

+Input Noise Current (Note 14)

f= 1kHz

25

2.5

-Input Noise Current (Note 14)

f= 1kHz

25

25

HARRIS VALUE ADDED SPECIFICATIONS

-

Input Common Mode Range

Full

±2.5V

Output Current, Short Circuit

VIN = ± 2.5VVour = OV

Full

±40

Output Current, Disabled (Note 14)

DISABLE = OV,
Your = ±2.5V, VIN = OV

Full
25

Output Enable Time (Notes 14, 21)

25

-

Supply Voltage Range

25

±5

DISABLE=OV

25

-

Differential Gain (Notes 13, 14)

RL = 150n

25

Differential Phase (Notes 13, 14)

RL = 150n

25

Gain Flatness to 5MHz

T05MHz

25

pAlVHz

-

V

±60

rnA

-

Output Disable Time (Notes 14, 20)

Output Capacitance, Disabled (Note 19)

pAlVHz

2

40

I!A
I!s

40

ns
±15

V

-

pF

6

-

0.03
0.03
0.1

-

!;;:::l

Degrees

w:=

dB

3. Suggested Vos Adjust Circuit: The inverting input current (-IBIAS) can be adjusted with an extemal10kO pot between pins 1 and 5, wiper
connected to V+. Since -I BIAS flows through the feedback resistor (RF), the result is an adjustment in offset voltage. The amount of offset
voltage adjustment is determined by the value of RF (/!Nos = a-IBIAS*RF)'
4. RL = 100n, VIN = 1OV. This is the minimum current which must be pulled out of the ,Disable pin in order to disable the output. The output
is considered disabled when -10mV S; Your S; +10mV.
5. VIN = OV. This is the maximum current that can be pulled out of the Disable pin with the HA-5020 remaining enabled. The HA-5020 is
considered disabled when the supply current has decreased by at least 0.5mA.
6. Your switches from -10V to +10V, or from +10V to -10V. Specification is from the 25% to 75% points.
FPBW = Slew Rate; V
= 10V.
2nVpEAK
PEAK

8. RL = 100n, Your = 1V. Measured from 10% to 90% points for riselfall times; from 50% points of input and output for propagation delay.
9. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.
10. VIN = +10V, Disable = +15V to OV. Measured from the 50% point of Disable to Vour = OV.
11. VIN = +10V, Disable = OVto +15V. Measured from the 50% point of Disable to Vour = 10V.
12. VIN = OV, Force Your from OV to ±10V, tR = tF = SOns.
13. Measured with a VM700A video tester using a NTC-7 composite VITS.
14. See "Typical Performance Curves' for more information.
15. V CM = ±2.5V. At -40°C product is tested at V CM = ±2.25V because short test duration does not allow self heating.
16. RL = 1oon. VIN = 2.5V. This is the minimum current which must be pulled out olthe Disable pin in order to disable the output. The output
is considered disabled when -10mV S; Vour S; +10mV.
17. Your switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
18. FPBW = Slew Rate. V
= 2V.
2nVpEAK' PEAK
19. VIN = OV, Force Your from OV to ±2.5V, tR = tF = SOns.
20. VIN = +2V, Disable = +5V to OV. Measured from the 50% point of Disable to Your = OV.
21. VIN = +2V, Disable = OV to +5V. Measured from the 50% point of Disable to Your = 2V.

3-325

O!:!:!
-u.

%

NOTES:

7.

-'
.::--""ftI"v---O

OUTPUT

27

NOTES:

26. U2: HA-S020.

INHIBIT .......T"I.....,

27. Uj: CD4011.

FIGURE 9. LOW IMPEDANCE MULTIPLEXER

Typical Performance Curves

VSUPPLY = ±lSV, Av = +1, RF = lkn, RL = 400n, TA = 2SoC,
Unless Otherwise Specified

100

2.5

100
Ay= +10

....

If
~

-INPUT NOISE CURRENT

!zw

~~

a:
a:

::>

10

(J

w

~z

INPUT NOISE VOLTAGE

~I
+~~~UT NOISE ~~RRENT

1
10

lK

100

!:iII.

-

>
.§.
w

~
!:i
~

Iii
Ie
II.
0

i!::

1
lOOK

10K

.... 1-'"

2.0

1.,,000
VSUPPLY = ±15V ....
1.5

I-'"

~"""

1.0

f-oo! ~t:
_ ....,.... :J.ooi""T

0.5

~ ~~

~

VSUPPLY = ±4.5V

0.0
-60

-40

_

...

J--r1'"

""'-

~II.!.!

VSUPPLY = ±10V

I I I I I
-20

0

20

40

60

80

100

120

140

TEMPERATURE (Oc)

FREQUENCY (Hz)

FIGURE 10. INPUT NOISE vs FREQUENCY (AVERAGE OF 18
UNITS FROM 3 LOTS)

FIGURE 11. INPUT OFFSET VOLTAGE vs TEMPERATURE
(ABSOLUTE VALUE AVERAGE OF 30 UNITS
FROM 3 LOTS)

o

2.0

-0.5

1.8

".

~

!z

-1.0

w

a:
a:

::>
(J

-f ....

~
III
-2.0

!zw

VSUPPLY = ±15V

?VSUPPLY = ±10V
.-o!

-1.5

~

~.

\

~i:== ~

==:::;;; '=-

....

-40

-20

0

.... ~

1.6

VSUPPLY =±15V

1.4

~

::>

""'' ' '

(J

20
40
60
80
TEMPERATURE <"C)

1.2

100

120

FIGURE 12. +INPUT BIAS CURRENT vs TEMPERATURE
(AVERAGE OF 30 UNITS FROM 3 LOTS)

.;~

1.0
-60

140

i.o"~

"",I'

...:
-40

i.-"
-20

0

".

,;

.... ~
,;i""'"

VSUPPLY = ±10V

I I I .... 1

,;

~

Ul

~

i;o" i""'"

,;

a:
a:

!:::S :::: .... i""'" '·VSUPPLY = ±4.5V
"

-2.5
-60

,;

_....

JA"'"

i""'"

1."ooo~1
I J..J
VSUPPLY = ±4.5V -

20
40
60
80
TEMPERATURE <"C)

100

120

FIGURE 13. -INPUT BIAS CURRENT vs TEMPERATURE
(ABSOLUTE VALUE AVERAGE OF 30 UNITS
FROM 3 LOTS)

3-330

140

HA-5020

Typical Performance Curves

VSUPPLy=±lSV, "v = +1, RF = lkCl, RL =400Cl, TA = 2SoC,
Unless Otherwise Specified (Continued)

8

--

!25"b
51--1--+-

"

~

i!i 4

~

CL

§ 3 1--I~.,.tC-+::""''F----I---I

25"c

IV
III

Joo"'" -sS"C

3

5

V

~

°21-"-"""""--+--t--+--I--+--t--+--11---l
4
lL-~_~_L-~_~_L-~_~_k-~

·60

·40

·20

20
40
60
80
TEMPERATURE ('IC)

0

100

120

140

FIGURE 14. TRANSIMPEDANCE vs TEMPERATURE (AVERAGE
OF 30 UNITS FROM 3 LOTS)

9

.s

5

!i:
II!
II:
B

3

~

2

~

..
,.k :::::

4

~

~

;,......-

,.

II)

o

""""':

e::: -

.sslc-

~

~

Fr

~

.s!i:

25:£'-

II!II:

125"C

P"""

7
11
9
SUPPLY VOLTAGE (±V)

5

3

,.,

~

iii'
~

:I:

l

j:.so

·70

.so

3

~

f./..

II
2
r-

r- r.... 1-00.

r- r....
3

...

5

I
I

I

J
J ..... r.... ... J
7

9

11

I

I I

",.,.,..

I

1 _ ......... ~

I

r~

VOUT=-10V

\
I~

II

f

o

15

13

VOUT=+10V

::"-

2

4

6

8
10
12 14
FREQUENCY (MHz)

16

18

-1.0
-4$0

20

FIGURE 18. DISABLE MODE FEEDTHROUGH VB FREQUENCY

-40

-20

0

20
40
80
80
TEMPERATURE ('IC)

100

120

140

FIGURE 19. DISABLED OUTPUT LEAKAGE VB TEMPERATURE
(AVERAGE OF 30 UNITS FROM 3 LOTS)

3-331

-II

ti:
a:1l

W"..
a..
OC

I

/

fil

II! ..ao

.... ioo.J

I

I

1.0

l

..,.

5

-

II

o~

~~

FIGURE 17. SUPPLY CURRENT VB ~ INPUT VOLTAGE

..a0

CI

--

i -2
~-3

z

Sl-4

~

~
z

10
FREQUENCY (MHz)

100

FIGURE 42_ PHASE RESPONSE AS A FUNCTION OF
FREQUENCY

130

100

200

I,

VOUT = 0.2Jp_p
C L =10pF
Av=+l

-

.......

~

III

"D

-3dB BANDWIDTH

1'-.

'?

~

/' I'- .......

-13S ~

!!!:

GAIN PEAKING

-180
500

700

10

~
III

:!:!.

CJ

.........

200

--

/
120

-45 CJ
-90

"'

10
FREQUENCY (MHz)

140

!.

-5
2

I
2

FIGURE 41. INVERTING FREQUENCY RESPONSE

iii'

~~o

c(

if

....

~ ~~
Av+l0/
7'11~

2

1.111-

~

Av=-l6'

-5

200

FIGURE 40. NON-INVERTING FREQUENCY RESPONSE

iii' 4

"'

~ -2
-3

~<

~

Av=-2

::Ii

-4
2

~

0

;t-l

:"icl"'-

w::a

~ Av=-l

~

-3

-5

~:::i
a: a.

iii' 3

Av

-2

--1'""""-'_-0 Your

son
Your

FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT

=

FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT

=

Vertical Scale: VIN 100mV/Oiv., Your 100mV/Oiv.
Horizontal Scale: 20nS/Oiv.

Vertical Scale: VIN = 1V/Oiv., Your = 1V/Oiv.
Horizontal Scale: 50ns/Oiv.

FIGURE 4. SMALL SIGNAL RESPONSE

FIGURE 5. LARGE SIGNAL RESPONSE

3·344

Schematic Diagram

(One Amplifier ofT'NO)

y+

liz

As

800

UK

~Dz

~~

RtO
820

~i

~~tt

.....aP5
a

.....

Rt
10K

R7
15K

--i<0r4t

,-~ ...... 5:
a,.~

r

I---

r a..t2

Ct

-,...

a..tz
Rt2
lID

Op,3

Rae
20

~
r

ONto

a,~

ar..

n

Rt4
lID
Rt3

--"""ar.r
r

il

r&

o,ts

-

aNI

tl

Opt.~
R3t

o,.!!

...

aNtS

+IN

5K

aN3

i

Aft
1.5

r'1ApF

Ra

~ ~D,

,....

~

r aP10

IB

~

~
a..t,

-

...

As

....
..... aP2

200

Rt7 IoRt,

1K

L

Au
2K

Ru

Op,t>t-

L

apt ......

~~ ~l
~0p,4

-::

IS
t1

20

ONts

t~

~

t.

ONt.

Au

a..t,

1K

'"---

ii:

lias

aL~~
lID

aNt~

"'0p,7

~~t7

Rt.

Raa

Aft

400

400

200

5

~;:::t- aNt.~
~28

~30

200

0 'UT

A4

800

y.

Raa
800

As
820

~a..tt

OPERATIONAL
AMPLIFIERS

HA5022
Application Information

Driving Capacitive Loads

Optimum Feedback Resistor

Capacitive loads will degrade the amplifier's phase margin
resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as
shown in Figure 6.

The plots of inverting and non-inverting frequency response,
see Figure 11 and Figure 12 in the Typical Performance
Curves section, Illustrate the performance of the HAS022 in
various closed loop gain configurations. Although the bandwidth dependency on closed loop gain isn't as severe as that
of a voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier's unique relationship between bandwidth and RF.
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier's bandwidth is
inversely proportional to RF' The HAS022 design is optimized for a 1000n RF at a gain of +1. Decreasing RF in a
unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the ampilfier is
more stable, so RF can be decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
RF(Q)

BANDWIDTH
(MHz)

-1

750

100

+1

1000

125

GAIN

(AcLl

+2

681

95

+5

1000·

52

+10

383

65

-10

750

22

....

VIN

-P

RT

"::~

R
VOUT

±~

RF

"::_::"

FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR,R

The selection criteria for the isolation resistor is highly
dependent on the load, but 27n has been determined to be
a good starting value.

Power DiSSipation Considerations
Due to the high supply current inherent in quad amplifiers,
care must be taken to insure that the maximum junction temperature (TJ, see Absolute Maximum Ratings) is not
exceeded. Figure 7 shows the maximum ambient temperature versus supply voltage for the available package styles
(PDIP, SOIC). At Vs = ±SV quiescent operation both package styles may be operated over the full industrial range of 400 C to 8SoC. It is recommended that thermal calculations,
which take into account output power, be performed by the
designer.
140

PC Board Layout

UI

The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board, The
use of low inductance components such as chip resistors
and chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short ·especially for the power supply decoupling components and
those components connected to the inverting input. .

Iea:

Attention must be given to decoupling the power supplieS. A
large value (10J.1F) tantalum or electrolytic capacitor In.parallei with a small value (0.1 J.1F) chip capacitor works well in
most cases.
.

lE

a:

A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier's inverting input (-IN)~ The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability.. It is
recommended that the ground plane be removed under
traces connected to -IN, and that connections to -IN. be kept
as short as possible to minimize the capacitance from this
node to ground.

::::I

130

...
lE

120

UI

UI
I-

!;:
~

r--..

I I
PDIP

r--.... ~r--..

r--..

110

~

,,
i""""o.

100

.......

lE

<

~

........

.............

90

SOIC

80

I I
5

7

·9
11
SUPPLY VOLTAGE (±V)

.......

r--..
13

15

FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE
va SUPPLY VOLTAGE

Enable/Disable Function
When enabled the amplifier functions as a normal current
feedback amplifier with all of the data in the electrical specifications table being valid and applicable. When disabled the
amplifier output assumes a true high impedance state and
the supply current is reduced significantly.

3-346

HA5022
The circuit shown in Figure 8 is a simplified schematic of the
enable/disable function. The large value resistors in series
with the DISABLE pin makes it appear as a current source to
the driver. When the driver pulls this pin low current flows out
of the pin and into the driver. This current, which may be as
large as 350~ when external circuit and process variables
are at their extremes, is required to insure that point "N
achieves the proper potential to disable the output. The
driver must have the compliance and capability of sinking all
of this current.

v+ _..-__- -....- - -.......
R6
15K

R7
15K

O--"",.,.........-

D~~

RaI

It::
1-_-0
....-f~of'_)QP3

ENABLEIDISABLE INPUT

tion 1. At position 1 the switch pulls the disable pin up to the
plus supply rail thereby enabling the amplifier. Since all of
the actual signal switching takes place within the amplifier,
it's differential gain and phase parameters, which are 0.03%
and 0.03 degrees respectively, determine the circuit's performance. The other circuit, U 1B, operates in a similar manner.
When the plus' supply rail is 5V the disable pin can be driven
by a dedicated TIL gate as discussed earlier. If a multiplexer
IC or its equivalent is used to select channels its logic must
be break before make. When these conditions are satisfied
the HA5022 is often used as a remote video multiplexer, and
the multiplexer may be extended by adding more amplifier
ICs.
Low Impedance Multiplexer

A

~

FIGURE 8. SIMPLIFIED SCHEMATIC OF ENABLEIDISABLE
FUNCTION

When Vee is +5V the DISABLE pin may be driven with a
dedicated TIL gate. The maximum low level output voltage
of the TIL gate, O.4V, has enough compliance to insure that
the amplifier will always be disabled even though D1 will not
turn on, and the TIL gate will sink enough current to keep
point "A" at its proper voltage. When Vee is greater than +5V
the DISABLE pin should be driven with an open collector
device that has a breakdown rating greater than Vee.
Referring to Figure 8, it can be seen that Rs will act as a pullup resistor to +Vee if the DISABLE pin is left open. In those
cases where the enable/disable function is not required on
all circuits some circuits can be permanently enabled by letting the DISABLE pin float. If a driver is used to set the
enable/disable level, be sure that the driver does not sink
more than 20~ when the DISABLE pin is at a high level.
TIL gates, especially CMOS versions, do not violate this criteria so it is permissible to control the enable/disable functionwithTIL.

Typical Applications
Two Channel Video Multiplexer
Referring to the amplifier U1A in Figure 9, R1 terminates the
cable in its characteristic impedance of 750. and R4 back
terminates the cable in its characteristic impedance. The
amplifier is set up in a gain configuration of +2 to yield an
overall network gain of + 1 when driving a double terminated
cable. The value of R3 can be changed if a different network
gain is desired. R5 holds the disable pin at ground thus
inhibiting the amplifier until the switch, S1, is thrown to posi-

Two common problems surface when you try to multiplex
multiple high speed signals into a low impedance source
such as an AID converter. The first problem is the low source
impedance which tends to make amplifiers oscillate and
causes gain errors. The second problem is the multiplexer
which supplies no gain, introduces all kinds of distortion and
limits the frequency response. Using op amps which have an
enable/disable function, such as the HA5022, eliminates the
multiplexer problems because the external mux chip is not
needed, and the HA5022 can drive low impedance (large
capacitance) loads if a series isolation resistor is used.
Referring to Figure 10, both inputs are terminated in their
characteristic impedance; 750 is typical for video applications. Since the drivers usually are terminated in their characteristic impedance the input gain is 0.5, thus the
amplifiers, U2, are configured in a gain of +2 to set the circuit
gain equal to one. Resistors R2 and Rs determine the amplifier gain, and if a different gain is desired R2 should be
changed according to the equation G = (1 + RslR2)' R3 sets
the frequency response of the amplifier so you should refer
to the manufacturers data sheet before changing its value.
R5, C1 and D1 are an asymmetrical charge/discharge time
circuit which configures U1 as a break before make switch to
prevent both amplifiers from being active simultaneously. If
this design is extended to more channels the drive logic
must be designed to be break before make. R4 is enclosed
in the feedback loop of the amplifier so that the large open
loop amplifier gain of U2 will present the load with a small
closed loop output impedance while keeping the amplifier
stable for all values of load capacitance.
The circuit shown in Figure 10 was tested for the full range of
capacitor values with no oscillations being observed; thus,
problem one has been solved. The frequency and gain characteristics of the circuit are now those of the amplifier independent of any multiplexing action; thus, problem two has
been solved. The multiplexer transition time is approximately
151lS with the component values shown.

3-347

...J

CCU)
Za:
O!!:!
-II.

~::J
a: a..

w:e
~cc

HA5022

VIDEO INPUT 11 -'"1r--"it~~"'"""~"""'~---VIDEO OUTPUT
10710
LOAD
R1
75

At

2OCJO

2

VIDEO INPUT 12 -""--if~4-.i~-'

ALL

'"

OFF

75

+&V IN •

G.1"F

1

I

..v IN

0

0.1J1f

11.

I .:t

..v

10"F

NOTES:
17. U1 is HA5022.
18. All resistors in O.
19. S1 Is break before make.
20. Use ground plana.

-=- -=-

':"

FIGURE 9. TWO CHANNEL HIGH IMPEDANCE MULTIPLEXER

INPUTB_------~~--------~

INPUTA_-.------~-~

CHANNEL _____..
SWITCH-

INHIBIT _ .....1....0,

NOTES:
21. Ua: HA5022.

22. U1: C04011.

FIGURE 10. LOW IMPEDANCE MULnPLEXER

3-348

HA5022

Typical Performance Curves

VSUPPlY = ±f>V, "'" = +1, RF = 1kn, RL = 400Q, TA = 25"C, Unless Otherwise Specified

5
VOUT = 0.2Vp.p

4 I-- CL= 10pF
3

e--

RF=750n
Av=·l

[7
!lot =·2
/

[7

~

~ ~
f", ...
)
!lot =·5
~

f-- !lot =·10

10
FREQUENCY (MHz)

2

·5

200

I

~

I

10

2

100

200

FREQUENCY (MHz)

FIGURE 12. INVERTING FREQUENCY RESPONSE

FIGURE 11. NON·INVERTING FREQUENCY RESPONSE

... 140

u;
~

0tj~e!!!t_i!t~C
180
.45
::eool..::+-H-+l--!.r---!135 ~

~ .90
~~ .135

90
45

~

~

·135

.......

-380

'/' I'-..

!l!
500

700

FREQUENCY (MHz)

... 100

130

:c

:c

b

VOUT = 0.2Vp.p
CL= 10pF
Av=+2

-

~

......... ........

95

III

~

90

'",

~

500

5

E
~
z
;Ii

" ...'1
z

r"""- r-....

"""

900
1100
1300
FEEDBACK RESISTOR (n)

~

o ~

90

80

FIGURE 15. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE

-I---

V 1)/\

III

1100

k
""

/

100

~l/

z

650
800
950
FEEDBACK RESISTOR (n)

Za:

O!!:!
-LL

~:::i
a:1l.

10

~

III

:l!5

- ........ ...... -.

'\.'
·3dB BANDWIDTH

I

:c 110

10 ~

'"~'" i'--

120

!.

·3dB BANDWIDTH

\.

GAIN PEAKING
350

...:c

r-

/

z

;Ii

etCl)

"i!:~
II.

o

~

1500

FIGURE 14. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE

FIGURE 13. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY

!.

r--... .....

GAIN PEAKING

10

2

·3dB BANDWIDTH

I\..

.180 i!:

VOUT = 0.2Vp.p H---+-+-+-H-+l-t+--3I
CL= 10pF

--

/

~~

-315

..J

-

0

~~
Z~

VOUT = 0.2Vp.p
CL=10pF
'!lot =+1

w

~~

·100

I,

t§

~
4~

if

:c

!.

o

200

GAIN PEAKING

,

-CL=10pF
Av=+l

600

800

o
1000

LOAD RESISTOR (D)

FIGURE 16. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE

3·349

6

I-- VOUT = 0.2Vp.p

I I I
400

-

w==

~et

HA5022
Typical Performance Curves
80

~
!.

I

,-

"

60

~

tv = +1, RF = 1ill, RL = 4000, TA = 25OC, Unless Olherwise Specified

. . 1\

\

40

~12~-4~~--~--+-~~-4--~--~--~~

8::c

..

i\

II!

......

ID

20

~ 6~-4-'~~~~~~~~

'-....

o

OL-~~~

200

350

800

650
FEEDBACK RESISTOR (n)
500

o

950

__

~

__

L-~

__

~

__

~

__J -__

600
LOAD RESISTANCE (n)

200

L-~

800

400

1000

FIGURE 18. SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE

FIGURE 17. BANDWIDTH vs FEEDBACK RESISTANCE

0.08

0.10

FREQUENCY = 3.58MHz

FREQUENCY = 3.58MHz

/
I

/

,

I

,~
RL=75n

...

I'\..

U;

..
..

0.06

II:

CJ

"
"f'.."-

e.

~
~
~ RL= 150n

1/1

cC

0.04

::c

., ~

RL = 1~on

a.
:!!i

...

..
U
-.......

0.02

I-

z

II:

0.02

5

7
9
11
SUPPLY VOLTAGE (±V)

13

3

15

1\

~

I

0.00
3

RL=75n

....
"\~
RL = 1kn

II.
II.

is

RL= 1kn
0.00

(Continued)

VOUT =O.1Vp.p
CL = 10pF

VOUT = 0.2Vp.p
CL= 10pF
Av=+10

z
~

;5}

VSUPPLY = i5V,

5

7
9
11
SUPPLY VOLTAGE (±V)

13

15

FIGURE 20. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE

FIGURE 19. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE

-40

VOUT = 2.0Vp.p
CL=30pF

o

-50

:!!.

H~

~

';

-60

z

0

~

~

~

Q ·30
Z -40
Q
-50 I--

..b

I~

·70
HD2, '

1/1

100..
·80

1-

"

~

V

tI'

·20

Ie
II:

:/.1'

3RD ORDER IMD

is

·10

';

'U

ID

AV=+1

HD3

;:a

II:

-60

~

~MRR

"'"

~

1
FREQUENCY (MHz)

POSITIVE PSRRI I
10

"

NEGATIVE PSRR

·70

HD3
·90
0.3

~"'"

0.001

0.01

"""
0.1

11111'
,11111

I--

" " "'

IIIIII
10

FREQUENCY (MHz)

FIGURE 22. REJECTION RATIOS vs FREQUENCY

FIGURE 21. DISTORTION vs FREQUENCY

3·350

30

HA5022

Typical Performance Curves

VSUPPLY = ±5V, "v = +1, RF = 1k.Q, RL = 400(1, TA = 2SoC, Unless Otherwise Specified (Continued)
12

8.0
RL= 1000
Your = 1.0Vp_p
Av=+l

Ii"
oS

RLOAD = 1000
Your = 1.0Vp_p

7.5

1&1

C

z

7.0

0

~

V
./

~

Ii!

0-

6.5

...

- 'V

6.0
-50

V

/

500
Your = 2OVp_p

-

400

Ii"
:I.

~

350

I
~ + SLEW RArE

1&1

~

100

~

oJ

'"

250

-- -

125

..........

-

"

m
:!!.

0.2

~

0

1&1

-0.2

oJ

-0.4

c

c-

..J

ct!/)

za:

Ay- +2, RF = 6810 -

~

"""""""-

............... "">-.....

.-:::f'.... ............ ......

-0.6

Ay=+l,RF=lk.r.1 ..... ~

I

-1.0

...........

Ay = +10, RF = 3830

-1.2

25
50
75
TEMPERATURE (oC)

100

5

125

FIGURE 25. SLEW RATE vs TEMPERATURE

10

m

:!!.

........... .......

~

..............

15
20
FREQUENCY (MHz)

25

z

0.2

C

0

1&1

c

-0.2

c(

~

-0.4

CI

::i

a:
0
z

,

.........-.:::: ~

"\..

-0.6
-0.8
-1.0

Ay=-l

,/
........

I-

-1.2

5

/

" "" "" "<

Ay=-5

Ay=-10

1

10

/1

\.\ .

'-J

15

20

/'

I
Av=-2

-

I
25

30

FIGURE 26. NON-INVERTING GAIN FLATNESS vs FREQUENCY

Your = 0.2Vp_p
CL= 10pF
RF= 7500

0.4

-

Av= +5, RF = lkO-

0.8
0.6

15

O!!:!
-II..

!:Ii

~

o

13

Vour = 0.2Vp_p
CL = 10pF

-0.8

-25

---

7
9
11
SUPPLY VOLTAGE (±V)

0.4

150

-50

I

I

FIGURE 24. PROPAGATION DELAY vs SUPPLY VOLTAGE

a:
0
z

100

Av= +2, RF= 6810 -

3

0.6

,

~~

-"

200

...
... --...

0.8

. / -SLEW RATE _

300

Av = +10, RF = 3830

4

25
50
75
TEMPERATURE (oC)

FIGURE 23. PROPAGATION DELAY vs TEMPERATURE

450

-

Av=+l,RF=lk.r.1

o

-25

---

V

~
oJ

30

FREQUENCY (MHz)

FIGURE 27. INVERTING GAIN FLATNESS vs FREQUENCY

O~

1
FREQUENCY (kHz)

10

FIGURE 28. INPUT NOISE CHARACTERISTICS

3-351

!ci:::i
a: a..
w:=
~ct

HA5022

Typical Performance Curves

="ffjV, tv =+1, RF =11<0, RL =400Q, TA =25OC, Unless OthelWise Specified

VSUPPLY

1.5

1.0

2

\

f' i'--

........

0.5

0.0
·60

-40·20

0

-

----

20

40

60

-

80

/

100

120

-4
-60

140

~
-40

·20

0

1\

18

16
-60

~

;;13000

o
z

1\~

8

·40

·20

g

i
....... ........
0

20

~

~

40

/'
2000

-

60

80

100

120

/

1000

~

140

V

25

120

I

\

jl
~

~

-40

0

74

..".

-4

5

I

~~

,.",...

-'

~

68

II:

66

......

I:

I--

~

25DC

I

6

7

8

9

10

""""

~

..

~

40

~

~

~

140

11

12

13

14

15

SUPPLY VOLTAGE (±V)

,

~ ....

iii' 70
:!:!.

~

"'""
'\
I

V'"

/

20

+PSRR

72

125DC

J.,. ~ -'

140

FIGURE 32. TRANSIMPEDANCE VB TEMPERATURE

I I

55DC

15

10

100

TEMPERATURE (DC)

FIGURE 31. ·INPUT BIAS CURRENT VB TEMPERATURE

!

80

V'

TEMPERATURE (DC)

20

60

4000

III

~
ID

40

FIGURE 30. +INPUT BIAS CURRENT VB TEMPERATURE

22

!z

20

TEMPERATURE (DC)

FIGURE 29. INPUT OFFSET VOLTAGE vs TEMPERATURE

20

- -'"

,-

.,.V

TEMPERATURE (DC)

l

(Continued)

58
·100

.

.pSRR

--r--.........

-...........
CMRR

I

r"o

.........

"""'"

50

~

r---100

150

200

TEMPERATURE fc)

FIGURE 34. REJECTION RATIO VB TEMPERATURE

FIGURE 33. SUPPLY CURRENT VB SUPPLY VOLTAGE

3·352

250

HA5022

Typical Performance Curves
40

VSUPPLY =:t5v, "v = +1, Ai: = 1kO, RL = 4000, TA = 25OC, Unless 0tI'IerMse SpecifIed (Continued)

I

I

I

.10V

I-- r+5V

~

", I--

I

r-- r-- ~ ....
l"- I'

r"""

.15V

.... ......

~

~~

J

J

.... .... ~

4.0

....

~

~

~

~

/

o

V"

v
:/

/

VV

3.8

o

1

2

3

4 5 6 7 8 9 10 11 12 13 14 15
DISABLE INPUT VOLTAGE (V)

..

FIGURE 35. SUPPLY CURRENT va DISABLE INPUT VOLTAGE

-20

-40

0

20
40 80
80
TEMPERATURE ("C)

100

1.2

1.1

s

\

! 1.0
~

\ i'...

0.'

0.10
1.00
LOAD RESISTANCE (leO)

....

0.8
..

10.00

-40·20

~

V
./

-

~

0

40

20

30

80

I

-S50C

25

..

" "" -

0.0
-80

-40

·20

250C

V

r-- ~

0

20
40 80
80
TEMPERATURE ("C)

/

80

100

120

140

FIGURE 38. INPUT OFFSET VOLTAGE CHANGE BETWEEN
CHANNELS va TEMPERATURE

1.5

"-

V

TEMPERATURE ("C)

FIGURE 37. OUTPUT SWING va LOAD RESISTANCE

\

140

FIGURE 36. OUTPUT SWING va TEMPERATURE

30r---------~--------_r--------~

0.01

120

10

5

100 120

FIGURE 39. INPUT BIAS CURRENT CHANGE BETWEEN
CHANNELS va TEMPERATURE

./

~~
3

140

~

4

~

l/
~

V

[> " ,

;r
~

~~ ~

~

",
~

-- -I""""

- -

~

~250C

J i
5

6

7
8
• 10 11
SUPPLY VOLTAGE (±V)

12

13

14

15

FIGURE 40. DISABLE SUPPLY CURRENT va SUPPLY VOLTAGE

3·353

HA5022

Typical Performance Curves

VSUPPLY = ±5V, J\J = +1, RF = 1kn, ~ = 4000, TA = 25OC, Unless otherwise SIJIICiIIed

·30
AyI=+11

32

,

I I I

VOUT=2Vp.p

30

20

f"""'o. ~

18

I\..

28

/'

ENABLE

S

L

...
III
C

~
1
FREQUENCY (MHz)

:)

-40

~
w

·50

II:

w ·60

IL

·70

·80

--

0.1

i-'" i-"~

:i

(DISABLE- J--

2

f

0

12 ~
10 J:

r-- I

.,......

"

14 ~

0.5

1.0

4

1.5

0
2.5

2.0

FIGURE 42. ENABLEIDISABLE TIME vs OUTPUT VOLTAGE

DmAiii:E = OV
0 - VIN=5Vp.p
_ RF=750n
·10

CI

rL

OUTPUT VOLTAGE (V)

FIGURE 41. CHANNEL SEPARATION vs FREQUENCY

iii' ·20
:!!.
:x: -30

,.
.A

12
·2.5 ·2.0 ·1.5 ·1.0 -0.5

30

10

ENABD

18 1- DISABLE
16
14

·80
0.1

0

20

""'-

~

V

"

w 24
J: 22
w

:Ii

zw
·70

16

A

... 26

~~

(Continued)

~

10

fil

0.01

~

---- -

---

i-"

III

RL=1000

1

"" .....

0.1

II.

i! 0.001

""'"

r-~

I'

~

...

,

180
135
90

m

I

459-

o

\

-45

aw
~w

\ -90:x::l
1
FREQUENCY (MHz)

10

20

0.001

FIGURE 43. DISABLE FEEDTHROUGH vs FREQUENCY

~
w

I.)

10

z

0.1

i!!i
w

0.01

II.

:Ii 0.001

-

....

....

11111
RL=400n

......

180

"'"

1'-00..

z

0.1
1
FREQUENCY (MHz)

~

11

I-

iii'

135 w

II!
~
w

90

CI

45

...

0

CI

z

c
-45 w
-90

:l:x:

.135
0.001

.0.01

10

0.1
FREQUENCY (MHz)

10

100

FIGURE 45. TRANSIMPEDENCE vs FREQUENCY

3-354

II.

.135 II.

100

FIGURE 44. TRANSIMPEDANCE vs FREQUENCY

--.

iii

0.01

HAS022

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:
Type: Nitride
Thickness: 4kA ±O.4kA

1650llm x 2540llm x 4831lm
METALLIZATION:

TRANSISTOR COUNT:

Type: Metal 1: AICu (1%)
Thickness: Metal 1: 8kA ±O.4kA

124

Type: Metal 2: AICu (1%)
Thickness: Metal 2: 16kA ±O.8kA

PROCESS:
High Frequency Bipolar Dielectric Isolation

SUBSTRATE POTENTIAL (Powered Up):

vMetallization Mask Layout
HA5022

-IN1

OUT1

v+

....I

«CI)
za::

O!!!
-II..

~::i
a:: a..

W::E

~«

Ne

-IN2

OUT2

3-355

HA5023
Dual 125MHz Video Current
Feedback Amplifier

November 1996

Features

Description

• Wide Unity Gain Bandwidth ••••••••••••••• 125MHz

The HAS023 is a wide bandwidth high slew rate dual
amplifier optimized for video applications and gains between
1 and 10. It is a current feedback amplifier and thus yields
less bandwidth degradation at high closed loop gains than
voltage feedback amplifiers.

• Slew Rate •••••••••••.•••••••••••••••••• 475V//-ls
• Input Offset YoRBge •••.••••••••••••••••••• BOO/-lV
• Differential Gain. • • .. • • • • • • • .. • • • • • • • • • ... 0.03%
• Differential Phase. • • . • . • • • • • • • • • • • •• 0.03 Degrees
• Supply Current (per Amplifier) •••••••••••••• 7.5mA
• ESD Protection ••••••••••••••••••••••••••• 4000V
• Guaranteed SpeCifications at ±5V Supplies

Applications
• Video Gain Block
• Video Distribution AmpllfierlRGB Amplifier

The low differential gain and phase, 0.1 dB gain flatness, and
ability to drive two back terminated 7S0 cables, make this
amplifier ideal for demanding video applications.
The current feedback design allows the user to take
advantage of the amplifier's bandwidth dependency on the
feedback resistor. By reducing RF, the bandwidth can be
increased to compensate for decreases at higher closed
loop gains or heavy output loads.
The performance of the HAS023 is very similar to the popular Harris HA-S020.

Ordering Information

• Flash AID Driver
PART NUMBER
(BRAND)

• Current to Voltage Converter

TEMP.
RANGE (DC)

PKG.
NO.

PACKAGE

• Medlciallmaglng

HAS0231P

-401085

8 Ld PDIP

E8.3

• Radar and Imaging Systams

HAS0231B
(H50231)

-40 to 85

8 LdSOIC

M8.15

• Video SWitching and Routing

HA5023EVAL

High Speed Op Amp DIP Evaluation Board

Pinout
HA5023
(PDlP, SOIC)
TOP VIEW

CAUTION: These devices are sensillve to electrostatic discharge. Users should follow proper Ie Handling Procedures.
Copyright C HarriS Corporation 1996

3-356

File Number

3393.5

HA5023
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 36V
DC Input Voltage (Note 3) ........................ ±VSUPPLY
Differential Input Voltage ............................... 10V
Output Current (Note 4) ................ Short Circuit Protected
ESD Rating (Note 3)
Human Body Model (Per MIL-STD-883 Method 3015.7) ... 2000V

Thermal Resistance (Typical, Note 2)

Operating Conditions

9JA (oclW)

130
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
SOIC Package. . . . . . . . . . . . . . . . . . . • . . . . . . . . .
Maximum Junction Temperature (Note 1) ................. 175°C
Maximum Junction Temperature (Plastic Package, Note 1) .. 150°C
Maximum Storage Temperature Range ....... " -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Temperature Range .......................... -40°C to 85°C
Supply Voltage Range (Typical) ................. ±4.5V to ±15V
CAUTION: Stresses above those listed in ''Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below
1500 C for plastic packages. See Application Information section for safe operating area information.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.
3. The non-inverting input of unused amplifiers must be connected to GND.
4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty
cycle) output current should not exceed 15mA for maximum reliability.

Electrical Specifications

VSUPPLY = ±5V, RF = 1kfl, Av = +1, RL = 4000, CL" 10pF,
Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

(NOTE 9)
TEST
LEVEL

TEMP.
(oC)

....I
«0
Za:

MIN

TYP

MAX

UNITS

Input Offset Voltage (VIO)

Delta VIO Between Channels
Average Input Offset Voltage Drift

VIO Power Supply Rejection Ratio

Input Common Mode Range

Note 5

±3.5V" Vs" ±6.5V

Note 5

Non-Inverting Input (+IN) Current

+IN Common Mode Rejection

Note 5

(+IBCMR=r)
+ IN
+IN Power Supply Rejection

a:

0.

w==

INPUT CHARACTERISTICS

VIO Common Mode Rejection Ratio

O!!:!
-LL

!;t:;j

±3.5V" VS" ±6.5V

Inverting Input (-IN) Current

Delta -IN BIAS Current Between Channels

3-357

A

25

0.8

3

mV

A

Full

-

5

mV

A

Full

1.2

3.5

mV

5

-

jlVPC

-

dB

-

dB

B

Full

A

25

53

A

Full

50

-

A

25

60

-

dB

A

Full

55

-

dB

A

Full

±2.5

-

V

A

25

-

3

A

Full

A

25

A

Full

A

25

A

Full

A

25,85

A

-40

A

25,85

A

-40

-

8

jlA

20

jlA

0.15

jlNV

0.5

jlNV

0.1

jlNV

0.3

jlNV

4

12

jlA

10

30

jlA

6

15

jlA

10

30

jlA

~«

HA5023
Electrical Specifications

VSUPPLY =±5V, RF = lkO, "'" = +1, RL = 4000, CL:S; 10pF,
Unless Otherwise Specified (Continued)

PARAMETER
·IN Common Mode Rejection

TEST CONDITIONS
Note 5

(NOTE 9)
TEST
LEVEL

TEMP.
(oC)

A

25

A

Full

A

25

MIN

TYP

-

-IN Power Supply Rejection

±3.5V:s; Vs:S; ±6.5V

A

Full

Input Noise Voltage

f= 1kHz

B

25

+Input Noise Current

f= 1kHz

B

25

-Input Noise Current

f = 1kHz

B

25

Note 11

A

25

1.0

A

Full

0.B5

A

25

70

A

Full

65

A

25

50

A

Full

45

A

25

±2.5

A

Full

MAX

UNITS

0.4

IlAIV

1.0

IlAIV

0.2

v.AN

0.5
4.5
2.5

-

25.0

-

v.AN
nVNHz
pANHz
pAl'I'Hz

TRANSFER CHARACTERISTICS
Transimpedence

Open Loop DC Voltage Gain

RL = 4000, Your = ±2.5V

Open Loop DC Voltage Gain

RL = 1000, Vour = ±2.5V

-

-

MO
MO
dB
dB
dB
dB

OUTPUT CHARACTERISTICS
Output Voltage Swing

RL= 1500

±3.0

V

±2.5

±3.0

V

±20.0

Output Current

RL= 1500

B

Full

±16.6

Output Current, Short Circuit

VIN = ±2.5V, Vour = OV

A

Full

±40

±SO

-

mA

Supply Voltage Range

A

25

5

-

15

V

Quiescent Supply Current

A

Full

7.5

10

mAlOpAmp

mA

POWER SUPPLY CHARACTERISTICS

AC CHARACTERISTICS (Av = + 1)
Slew Rate

Note 6

B

25

275

350

Full Power Bandwidth

Note 7

B

25

22

2B

RiSe Time

NoteB

B

25

Fall Time

NoteB

B

25

Propagation Delay

NoteS

B

25

B

25

-3dB Bandwidth

Vour= 100mV

B

25

Settling Time to 1%

2V Output Step

B

25

Settling Time to 0.25%

2V Output Step

B

25

Overshoot

3-358

-

-

V/IlS
MHz

6

ns

6

ns

6

ns

4.5
125
50
75

-

%
MHz
ns
ns

HA5023
Electrical Specifications

VSUPPlY = ±5V, RF = lkn, Av = +1, Rl = 400n, Cl:S; 10pF,
Unless Otherwise Specified (Continued)
(NOTE 9)
TEST
LEVEL

TEMP.
(DC)

Note 6

B

25

475

V/IlS

Full Power Bandwidth

Note 7

B

25

26

MHz

Rise Time

Note 8

B

25

6

ns

Fall Time

Note 8

B

25

6

ns

Propagation Delay

Note 8

B

25

B

25

12

TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

AC CHARACTERISTICS (Av = +2, RF = 681 Q)
Slew Rate

Overshoot

-

6

-

ns
%

·3dB Bandwidth

VOUT = 100mV

B

25

95

Settling Time to 1%

2V Output Step

B

25

50

-

ns

Settling Time to 0.25%

2V Output Step

B

25

100

-

ns

Gain Flatness

5MHz

B

25

20MHz

B

25

-

dB

MHz

0.02

-

0.07

dB
..J

O!!!
-I&.
~:;

AC CHARACTERISTICS (AV = +10, RF = 383n)
Slew Rate

Note 6

B

25

350

475

Full Power Bandwidth

Note 7

B

25

28

38

Rise Time

Note 8

B

25

Fall Time

Note 8

B

25

Propagation Delay

Note 8

B

25

Overshoot

B

-3dB Bandwidth

VOUT= 100mV

B

Settling Time to 1%

2V Output Step

Settling Time to 0.1 %

V/flS

-

8

MHz
ns

9

-

25

-

1.8

-

%

25

-

65

-

MHz

B

25

-

75

-

ns

2V Output Step

B

25

-

130

-

ns

Differential Gain (Note 10)

Rl= 150n

B

25

0.03

Differential Phase (Note 10)

Rl= 150n

B

25

0.03

9

ns
ns

VIDEO CHARACTERISTICS

-

%
Degrees

NOTES:
5. VCM = ±2.5V. At -40°C Product is tested at VCM = ±2.25V because Short Test Duration does not allow self heating.
6. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% pOints.
7. FPBW = Slew Rate; V
= 2V .
PEAK
21tV pEAK

8. Rl = lOOn, VOUT = IV. Measured from 10% to 90% points for riselfall times; from 50% points of input and outputfor propagation delay.
9. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only.
10. Measured with a VM700A video tester using an NTC-7 composite VITS.
11. VOUT = ±2.5V. At -40°C Product is tested at VOUT = ±2.25V because Short Test Duration does not allow self heating.

3-359

~UJ

Za:

a:1l.
W:!i

:s~

HA5023

Test Circuits and Waveforms

HP4195
NETWORK
ANALYZER

FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS

'.' I 'Cj

VOUT

VOUT

son

FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT

=

Vertical Scale: VIN 100mV/Div.• VOUT
Horizontal Scale: 20ns/Div.

FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT

=100mV/Div.

=

Vertical Scale: VIN lv/Div .• VOUT
Horizontal Scale: SOns/DiY.

=lV/Diy.

FIGURE 5. LARGE SIGNAL RESPONSE

FIGURE 4. SMALL SIGNAL RESPONSE

3-360

Schematic Diagram
v+.

(One Amplifier of Two)

T I T 1As

TIT

T

[

['

T

,

2.51(

~.GPz

•
Rt
10K

~

i

~

t:l

R32
5

~OUT

v-.!

~
800

1

At

FIa3

800

1 1

!

820

1

{l

1

OPERATIONAL
AMPLIFIERS

1 1 J

1I

HA5023
Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response,
see Figure 8 and Figure 9 in the typical performance section,
illustrate the performance of the HA5023 in various closed
loop gain configurations. Although the bandwidth dependency on closed loop gain isn't as severe as that of a voltage
feedback amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking advantage of the current feedback amplifier's
unique relationship between bandwidth and RF. All current
feedback amplifiers require a feedback resistor, even for
unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the
frequency response. Thus, the amplifier's bandwidth is
inversely proportional to RF. The HA5023 design is optimized for a 10000 RF at a gain of +1. Decreasing RF in a
unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is
more stable, so RF can be decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
GAIN
(AcLl

RF(Q)

BANDWIDTH
(MHz)

-1

750

100

+1

1000

125

+2

681

95

+5

1000

52

+10

383

65

-10

750

22

nected to -IN, and that connections to -IN be kept as short as
possible to minimize the capacitance from this node to
ground.

Driving Capacitive Loads
Capacitive loads will degrade the amplifier's phase margin
resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing
an isolation resistor (R) in series with the output as shown in
Figure 6.

....

VIN

rP

iRT
-

R

±~

Rf

RI

VOUT

'=.,?FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R

The selection criteria for the isolation resistor is highly
dependent on the load, but 270 has been de.termined to be
a good starting value.

Power Dissipation Considerations
Due to the high supply current inherent in quad amplifiers,
care must be taken to insure that the maximum junction temperature (TJ, see Absolute Maximum Ratings) is not
exceeded. Figure 7 shows the maximum ambient temperature
versus supply voltage for the available package styles (Plastic
DIP, SOl C). At ±5VDC quiescent operation both package
styles may be operated over the full industrial range of -40°C
to 850 C. It is recommended that thermal calculations, which
take into account output power, be performed by the designer.

UI40r-r--.--.---r--r--r--,--,---.--.--,-,

PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors
and chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short especially for the power supply decoupling components and
those components connected to the inverting input.
Attention must be given to decoupling the power supplies. A
large value (1 011 F) tantalum or electrolytic capacitor in parallel with a small value (0.11lF) chip capacitor works well in
most cases.

~130r-+~~7-~~~--t--+--~~r--r--+--1-1
!!; 120
-t"-- _ _~P_DIP
1.
~
~

~ 110r-+1--~~~---r--+--+--~I---'~~~E±--~~
w.....
- .......
!Ii 100 r-+--+---ll--=
--,.,.,o::::-t--+--~~r--r--+--1-1

~ ~r-+--+--~--~~--+~~~~---r--+--+--~~

!z

SOIC

........

waol--l--+--+-1--t--II--""d--t--t--IH
iii
.............
~

i

A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier's inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. It is recommended that the ground plane be removed under traces con-

3-362

70r-r-~--r--r~--;-~--~~f""'-.~+--+~

60r-+--+---l---r--r--+--1---r--t--f~d-~
50~~~--~--~~--~~---L--L-~--~~

5

7

9

11

13

15

SUPPLY VOLTAGE (±V)

FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE
vs SUPPLY VOLTAGE,

HA5023
Typical Performance Curves

VSUPPLY= ±SV. AV=+l. RF= lkn. RL=400n. TA=2SoC.
Unless Otherwise Specified

5
4

-

iii 3
!:!. 2
i!E
~

1

[il

0

~

-1

-2

Z

-3

:>

=lkQ
+, F /

'"

iii'

~

~

........

;;;;:;;;,.

z

'I

1/

-1

~

-2 -

0

!ll
c
f

"

100

ffi

1'-

-5

200

~

Ay=-10

0-

Ay=-5

:I-+++++f

..........

"

~

::I:

~~

e.
w

~

45

-1351--I--I-i"

UJ
C
::I:
0..

-100r--I-~++++rr---;--+-~~~~--~ 0

~

I,

130

100

10

........

100

200

-

-180
200

500

GAIN PEAKING
700

...I

--

--

O!!!
-II..

::I:

10 iii'
~
Cl

5

o

~

W
0..

~

1500

FIGURE 11. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE

!.

.......

::I:

95

"lOUT. 0.2Yp.p
CL= 10pF
Av=+2

-

-

-

-:ldB BANrklDTH

~

N'

"'-"

ED
~

" I r--....

Cl
Z

"""-.

GAIN PEAKING
SOD

6SO

5

i'"

r---. ....

800

950

120

::I:

!.
10 _

Si!

cW

::I:

110

6

Z

100

4 Cl
Z

~
~

iii'
~

Si!

ED

C

'D

'?

"lOUT = O.2Vp_p
CL= 10pF
Ay=+l

90

0..
Z

;;:
0
1100

80

Cl

0

FEEDBACK RESISTOR (Q)
FIGURE 12_ BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE

200

400
600
LDAD RESISTOR (Q)

BOO

2

3-363

W
0..

~

Cl

0
1000

FIGURE 13. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE

ti::J
w::

a: a..
Z

............

900
1100
1300
FEEDBACK RESISTOR (Q)



/

Z -3

FIGURE 8. NON-INVERTING FREQENCY RESPONSE

i

Ay=-l

If

~
;;!

o

II
10
FREQUENCY (MHz)

2

2

I

Cl

/

oS

1

;;: 1

Ay = 10, RF = 383
II
I
I

-4

"lOUT = 0.2Yp_p
- - CL=10pF
3 __ RF=750Q
4

~4

~

II:

5

~ '='l'~

VOUPO.2Vp_pll
CL=10pF
I!
Ay .2, RF- 681Q
I
I I
Ay = 5, RF= lkQ

~<

HA5023
Typical Performance Curves

VSUPPLY = ±SV, Av = +1, RF = 1kQ, RL = 4000, T~ = 2SoC,

Unless Otherwise Specified (Continued)

80
VOUT = 0.2Vp.p
CL= 10pF
Ay =+10

1-

"~

""'1\

\

i\.

"

o

200

~

BOO

500
650
FEEDBACK RESISTOR (0)

350

950
LOAD RESISTANCE (0)

FIGURE 15, SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE

FIGURE 14. BANDWIDTH VB FEEDBACK RESISTANCE

0.08

0.10

~ 0.08

z

~

~

I

/

0.06

/

II

,

0.04

0.02

~

I

RL = 750

w

1"'-

IE:

w

"

e.w
~
:z:

V .Lr..11'.....
RL=1500
"'-

5

7

9

11
SUPPLY VOLTAGE (±V)

0.04

II.

RL=1~00

-'

§w

I'...

"

IE:

w

--.........

I

3

0.06

CI

RL = 1k1l
0.00

FREQUENCY = 3.58MHz

enw

FREQUENCY = 3.58MHz

13

0.02

II.
II.

is

3

9

11

-10

-50

I'

HD2

z

0

3RD ORDER IMD

--

-90
0.3

r'II..

!

'i

IiiIE:
z
o

~

-40

fi

-50

Ul

-60

w

HD3

-

10

FREQUENCY (MHz)

CMRR
~

IE:

Da
1

~

-20

Q -30

~/I'
Ir...

I
./

HDa,

15

13

AV=+1

o

'U'
ID
:!!. -60

-80

I
7

5

FIGURE 17. DIFFERENTIAL PHASE VB SUPPLY VOLTAGE

VOUT = 2.0Vp.p
CL = 30pF

-70

../'

SUPPLY VOLTAGE (±V)

-40

~

\

~=1~~

W

0.00

15

FIGURE 16. DIFFERENTIAL GAIN VB SUPPLY VOLTAGE

~

RL=750

_\~

~

-70

NEGATIVE PSRR

-80

11111111 Jill

POSIT~~,~ PSRR

0.001

0.01

I

11111

0.1

l-

II
10

FREQUENCY (MHz)

FIGURE 18. DISTORTION VB FREQUENCY

FIGURE 19. REJECTION RATIOS VB FREQUENCY

3-364

30

HA5023
Typical Performance Curves

VSUPPLY = ±5V, Av = +1, RF = 1kO, RL = 4000, TA = 25°C,

Unless Otherwise Specified (Continued)
12

8.0

.
.s
~
w

RL = 1000
VOUT = 1.0Vp.p
Ay=+1
7.5

Z
Q 7.0

!;(

~
IfD.

6.5

...

--' ~

6.0
-50

o

-25

/
./

25

50

.s

/

/

Q

.

RlOAD=10Dn
VOUT = 1.0Vp_p

---

10

~w

Q

Z

8

0

~

...

~
CI

...

~

0

6

II:
D.

75

100

---

--

VOUT = 2OVp_p

. 400

.L'" + SLEW RATE

"~ 350
w
!;( 300

125

~

.----

250

-"""

..J

II)

200

/

0.8

~

iii'

-SLEW RATE

25

50

75

...........

Q

100

Av=+2,RF=6810-

.zF'-...... ........... .....
Ay=+1,RF=1kn ......
I

,

Ay=+5,RF=1kn -

'" .......... .................. -.............

Ay = +10, RF = 3830

5

10

TEMPERATURE (oC)
FIGURE 22. FIGURE 22. SLEW RATE VB TEMPERATURE

!c:::i
a:: a..

............... "">-....

-1.2

125

Za::

O!!:!
-u.

-

0

w -0.2
t!
..J
c( -0.4
:E
II: -0.6
0
z
-0.8

100

o(en

0.4

z

CI

..I

o.~Vp_p

:!:!. 0.2

~

o

15
20
FREQUENCY (MHz)

25

30

FIGURE 23. NON-INVERTING GAIN FLATNESS VB FREQUENCY

0.8

iii'

0.4

~
CI

0

1000

VOUT = 0.2Vp_p
CL = 10pF
RF = 7500

0.6

Av = +10, RF = 3830

:!:!. 0.2

,,

Q

w

-0.2

c(

-0.4

II:

-0.6

~
..J

:::;;
0

z

-0.8
-1.0

.......

~

1

-1.2

5

...

"""-

_'" \.
r- Av =~-10 '\.' \ .
10

15

VOUT =
CL = 10pF

0.6

-1.0
-25

13

FIGURE 21. PROPAGATION DELAY VB SUPPLY VOLTAGE

150
-50

""'"'"---

7
9
11
SUPPLY VOLTAGE (±V)

5

3

C

II:

I

4

FIGURE 20. PROPAGATION DELAY VB TEMPERATURE

450

I

Ay _ +2, RF= 6810 -

Av = +1, RF= 1kn

TEMPERATURE (C)

500

Ay = +10, RF = 3830

800f

w

600 ;

Ay=-1

.s

..).

!II

c.

!II
0

0

#

z

z

w
CI

Ay=-5

:,,-

'" 'X
15

~:>
;!;
..J
~

rAy=-21/

"-

20

I
25

30

FREQUENCY (MHz)

40

4OO!zw

20

200

II:
II:

0
0.01

0.1

10

0
100

FREQUENCY (kHz)

FIGURE 24. INVERTING GAIN FLATNESS VB FREQUENCY

FIGURE 25. INPUT NOISE CHARACTERISTICS

3-365

8

1IJ::ii1

~c

HA5023
Typical Performance Curves

VSUPPLY =±5V,AV= +1, RF= 1kQ, RL=400Q, TA=250C,
Unless Otherwise Specified (Continued)

1.5

2

\

1.0

"

~

........ ......

0.5

0.0

~o

-40

·20

0

20

-

40

.,.. ~

60

80

100

120

/

-4

140

~

,/
~

~

0

20

~

III

\

18

~

140

~O

""
"

",."".

~

~

\~

'""" ........

16
·40

·20

0

20

-

40

V

~

80

100

120 140

lL

1000
·60

-40

/

V

V

·20

0

TEMPERATURE fc)

20

40

60

"

100

120 140

TEMPERATURE fC)

FIGURE 28. ·INPUT BIAS CURRENT VB TEMPERATURE

FIGURE 29. TRANSIMPEDANCE VB TEMPERATURE

74

25

I I

I

20

\

--

~

......

~

"""

~

.)(

-~

" ,~

~

5

6

o

~Z

68
66

§ 64
III

ia
a: 62

7

8

9

10

11

12

13

14

I .... ~

:E-

'25°C
4

~

iii" 70

.J

...".

I
5 3

1PSRR

72

125°C

55°C

115
10

~

"

4000

22

!

~

FIGURE 27. +INPUT BIAS CURRENT VB TEMPERATURE

FIGURE 26. INPUT OFFSET VOLTAGE VB TEMPERATURE

20

40

TE;MPERATURE fc)

TEMPERATURE (oC)

l

-

"."",.

_i-

15

SUPPLY VOLTAGE (±V)

·PSRR

'""" ...........
~

~

60 i---,CMRR

'-

58
·100

o

·50

.......... I"-

-

50

r-100

150

200

TEMPERATURE fC)

FIGURE 31. REJECTION RATIO VB TEMPERATURE

FIGURE 30. SUPPLY CURRENT VB SUPPLY VOLTAGE

3·366

250

HA5023
Typical Performance Curves

VSUPPLy=±5V, Av= +1, RF= 1kQ, RL = 400Q, TA = 25°C,
Unless Otherwise Specified (Continued)
4.0

40

"
§.

30

I

-

i- +5V

IZ

:;)

20

U

......~

:;)

Ul

10

.....

~

'- . "

o
o

~

J

w

II:
II:

1

-

-

/.-. r-.. ......

2

3

I

I
+10V

r-.. r-..

+15V

fo""'"

J

J

~ r-...

~ r::

I
i"oooo.

V~

~
z

"~

3.8

!5...

I:;)

~

0

"

/
",
3.6
·60

4 5 6 7 8 9 10 11 12 13 14 15
DISABLE INPUT VOLTAGE (V)

/

V

./

·40

·20

~

0

/

20

40

60

80

100

120

140

TEMPERATURE (DC)

FIGURE 32. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE

FIGURE 33. OUTPUT SWING vs TEMPERATURE

30r----------.-----------r--------~

1.2

-J



§. 1.0

~

10r-------~~-----------+----------~

\

0.9

"-......

--

./

V

V

V

za:
O!!:!
-u.
~::::i
a:1l.

/

W:iE

~

0

a:

-40

b
w

·50

:z:

w -60

"-

·70

i-'
.,...,.". i"""'"

~

~

i

10

~
Z

0.1

2!i

0.01

; 0.001

I"RL=l~~~

....
"""

r""-I"o

iii

~

I'

180
~

""

A-

~'"

135

fff
w

90

l§

45

~
w

o S
\ ·45 ;

1

·80
0.1

_

10

1
FREQUENCY (MHz)

20

FIGURE 38. DISABLE FEEDTHROUGH vs FREQUENCY

~

~

0.1

0.001

0.1
1
FREQUENCY (MHz)

0.01

,..
=a:

~~~~~rH~~~~Hr-;-H~-;-H~

0.01

!w:

~~~~~~~~rHI~1-rH--HHt-l45 ~

o
~~H*--~H--+~~~H*--r+HHH·45

~

~~~~~rH~~rH~;-~-;-~;H·90 ~:z:
L........L..LJ.........J..J..L.I.......................-'--.....L--'--'"':"-:-"

0.001

0.01

100

FIGURE 39. TRANSIMPEDANCE vs FREQUENCY

1:-~
__f+-HI---1H-Hl---1H-Hl~r=""I:-HI--H1+II-l180
i!! 0.001
r--...
i'..
11 ::5
Z

10

0.1
1
10
FREQUENCY (MHz)

.135 ...

100

FIGURE 40. TRANSIMPEDENCE vs FREQUENCY

3·368

·90 ~
·135

...

HA5023

Die Characteristics
DIE DIMENSIONS:
1650l1m x 2540l1m

PASSIVATION:

x 4a311m

Type: Nitride
Thickness: 4kA ±O.4kA

METALLIZATION:
TRANSISTOR COUNT:

Type: Metal 1: AICu (1%)
Thickness: Metal 1: akA ±O.4kA

124

Type: Metal 2: AICu (1 %}
Thickness: Metal 2: 16kA ±o.akA

PROCESS:
High Frequency Bipolar Dielectric Isolation

SUBSTRATE POTENTIAL (Powered Up):

V-

Metallization Mask Layout
HA5023
OUT

NC

..J

v+
-IN1

etC/)
Za:
O!!:!
-II..
!i(::i
a: a..
W:E

~et

+IN1

NC
OUT2

...

NC

g

•

D

~

=:
•

v-

+IN

-IN

3-369

HA5024

~HARRlS

\KJ

SEMICONDUCTOR

Quad 125MHz Video Current
Feedback Amplifier with Disable

November 1996

Features

Description

• Quad Version of HA·5020

The HA5024 is a quad version of the popular Harris
HAS020. It features wide bandwidth and high slew rate, and
is optimized for video applications and gains between 1 and
10. It is a current feedback amplifier and thus yields less
bandwidth degradation at high closed loop gains than volt·
age feedback amplifiers.

• Individual Output Enable/Disable
• Input Offset Voltage •••••••.............•.. BOOI1V
• Wide Unity Gain Bandwidth ••.•.•••.•••... 125MHz
• Slew Rate ••••...•.••••...••••...••••••• 475V/jlS
• Differential Gain. • • • • • • . • . . • • • • • • • • • . . • • •• 0.03%
• Differential Phase .....••....••..... , 0.03 Degrees
• Supply Current (per Amplifier) ••••••.••..••• 7.SmA
• ESD Protection ..•••••••••••••••••.••••••• 4000V
• Guaranteed Specifications at ±5V Supplies

Applications
• Video Multiplexers; Video Switching and Routing

The low differential gain and phase, 0.1 dB gain flatness, and
ability to drive two back terminated 7S0 cables, make this
amplifier ideal for demanding video applications.
The HAS024 also features a disable function that signifi·
cantly reduces supply current while forcing the output to a
true high impedance state. This functionality allows 2:1 and
4:1 video multiplexers to be implemented with a single IC.
The current feedback design allows the user to take advantage of the amplifier's bandwidth dependency on the feedback resistor. By reducing RF, the bandwidth can be
increased to compensate for decreases at higher closed
loop gains or heavy output loads.

• Video Gain Block

Ordering Information

• Video Distribution Ampllfier/RGB Amplifier
• Flash AID Driver

PART NUMBER

• Current to Voltage Converter

HA50241P

• Medical Imaging

HA50241B

• Radar and Imaging Systems

HA5024EVAL

TEMP.
RANGEfC)

PKG.
NO.

PACKAGE

-401085

20Ld PDIP

E20.3

-401085

20 LdSOIC

M20.3

High Speed Op Amp DIP Evaluation Board

Pinout
HA5024
(PDIP, SOIC)
TOP VIEW

+INI

DISf

+IN2
-IN2
OUT2

-"'---~

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-370

File Number

3550.3

HA5024
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals •................... 36V
DC Input Voltage (Note 3) ........................ ±VSUPPLY
Differential Input Voltage ............................... 10V
Output Current (Note 4) ................ Short Circuit Protected
ESD Rating (Note 3)
Human Body Model (Per MIL-STD-883 Method 3015.7) .. 2000V

Thermal Resistance (Typical, Note 2)

Operating Conditions

6JA (oclW)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Junction Temperature (Note 1) ................. 175°C
Maximum Junction Temperature (Plastic Package, Note 1) .... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to B50C
Supply Voltage Range (Typical) ................. ±4.5V to ±15V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the opera/ional sections of this specification is not implied.

NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below
150°C for plastic packages. See Application Information section for safe operating area information.
2. 9JA is measured with the component mounted on an evaluation PC board in free air.
3. The non-inverting input of unused amplifiers must be connected to GND.
4. Output is protected for short circuits to ground. Brief short Circuits to ground will not degrade reliability, however, continuous (100% duty
cycle) output current should not exceed 15mA for maximum reliability.

Electrical Specifications

VSUPPLY = ±5V, RF= lk.Q, Jl.,.t = +1, RL = 4000, CL ~ 10pF,UnlessOtherwise Specified

PARAMETER

TEST CONDITIONS

(NOTE 11)
TEST
TEMP.
LEVEL
("C)

MIN

TYP

MAX

UNITS

INPUT CHARACTERISTICS

A

25

0.8

3

mV

A

Full

-

-

5

mV

Delta VIO Between Channels

A

Full

-

1.2

3.5

Average Input Offset Voltage Drift

B

Full

-

5

A

25

53

A

Full

50

Input Offset Voltage (VIO)

VIO Common Mode Rejection Ratio

VIO Power Supply Rejection Ratio

Input Common Mode Range

Note 5

±3.5V ~ Vs ~ ±6.5V

Note 5

Non-Inverting Input (+IN) Current

+IN Common Mode Rejection

Note 5

(+IBCMR=~)
RIN
+IN Power Supply Rejection

±3.5V ~ Vs

~

±6.5V

Inverting Input (-IN) Current

Delta -IN BIAS Current Between Channels

-IN Common Mode Rejection

-IN Power Supply Rejection

Note 5

±3.5V ~ Vs ~ ±6.5V

3-371

A

25

60

A

Full

55

A

Full

±2.5

A

25

A

Full

A

25

A

Full

-

3

-

-

mV

IlvfJc
dB
dB

-

dB

-

dB

-

V

8

IlA

20

IlA

0.15

IlAIV

0.5

jlAIV

A

25

-

-

0.1

jlAIV

A

Full

-

-

0.3

jlAIV

A

25,85

4

12

IlA

A

-40

10

30

IlA

A

25,85

6

15

IlA

A

-40

10

30

IlA

-

0.4

jlAIV

1.0

jlAIV

0.2

jlAIV

0.5

jlAIV

A

25

A

Full

A

25.

A

Full

-

-

HA5024
Electrical Specifications

VSUPPLY =±f>V, RF = lkQ, "v = +1, RL =400n, Ct.:s; 10pF,UniessOtherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

(NOTE 11)
TEMP.
TEST
(oC)
LEVEL

MIN

TYP

MAX

UNITS

-

4.5

-

nV/-JRZ

Input Noise Voltage

f= 1kHz

B

25

+Input Noise Current

f= 1kHz

B

25

2.5

-Input Noise Current

f= 1kHz

B

25

25.0

pAl-JRZ
pAl-JRZ

TRANSFER CHARACTERISTICS
Transimpedence

Open Loop DC Voltage Gain

Open Loop DC Voltage Gain

Note 16

RL = 400n, VOUT = ±2.5V

RL = lOOn, VOUT = ±2.5V

-

-

A

25

1.0

A

Full

0.85

25A

25

70

A

Full

65

A

25

50

dB

A

Full

45

dB

A

25

±2.5

±3.0

A

Full

±2.5

±3.0

-

V

-

mA

Mn
Mn
dB

-

dB

OUTPUT CHARACTERISTICS
Output Voltage Swing

RL= 150n

Output Current

RL= 150n

B

Full

±16.6

±20.0

Output Current, Short Circuit

VIN = ±2.5V, VOUT = OV

A

Full

±40

±60

Output Current, Disabled (Note 5)

DISABLE = OV,
VOUT = ±2.5V, VIN = OV

A

Full

V

-

mA

2

flA

Output Disable Time

Note 12

B

25

40

-

flS

Output Enable Time

Note 13

B

25

40

-

ns

Output Capacitance Disabled

Note 14

B

25

5

15

pF

POWER SUPPLY CHARACTERISTICS
Supply Voltage Range

A

25

Quiescent Supply Current

A

Full

-

15

V

7.5

10

mAlOpAmp

5

7.5

mAlOpAmp

1.0

1.5

mA

Supply Current, Disabled

DISABLE=OV

A

Full

Disable Pin Input Current

DISABLE=OV

A

Full

-

Minimum Pin 8 Current to Disable

Note 6

A

Full

350

-

flA

Maximum Pin 8 Current to Enable

Note 7

A

Full

-

20

flA

Note 8

B

25

275

350

-

V/flS

22

28

-

MHz

AC CHARACTERISTICS (Av = + 1)
Slew Rate
Full Power Bandwidth

Note 9

B

25

Rise Time

Note 10

B

25

Fall Time

Note 10

B

25

Propagation Delay

Note 10

B

25

6

B

25

4.5

25

Overshoot
-3dB Bandwidth

VOUT= 100mV

B

Settling Time to 1%

2V Output Step

B

25

Settling Time to 0.25%

2V Output Step

B

25

6

-

6

ns

-

ns
ns
%

125

-

MHz

50

-

ns

75

-

ns

475

-

V/flS

AC CHARACTERISTICS (Av = +2, RF = 681 n)
Slew Rate

Note 8

B

25

Full Power Bandwidth

Note 9

B

25

3-372

-

26

MHz

HA5024
Electrical Specifications

VSUPPLY = ±5V, RF = lkQ, Av = +1, RL = 400n, CL ~ 10pF,Unless O1herwise SpecWied (Continued)

MIN

TYP

MAX

UNITS

Rise Time

Note 10

B

25

-

6

-

ns

Fall Time

Note 10

B

25

-

6

Propagation Delay

Note 10

B

25

B

25

PARAMETER

TEST CONDITIONS

(NOTE 11)
TEST
TEMP.
(DC)
LEVEL

Overshoot

-

-

6

-

12

-

ns
ns
%

-3dB Bandwidth

VOUT= 100mV

B

25

Settling Time to 1%

2V Output Step

B

25

Settling Time to 0.25%

2V Output Step

B

25

100

Gain Flatness

5MHz

B

25

0.02

20MHz

B

25

0.07

dB

V/IlS

95
50

MHz

-

ns
ns

-

dB

AC CHARACTERISTICS (Av = +10, RF = 383n)
Slew Rate

Note 8

B

25

350

475

Full Power Bandwidth

Note 9

B

25

28

38

Rise Time

Note 10

B

25

-

8

Fall Time

Note 10

B

25

Propagation Delay

Note 10

B

25

9

-

9

MHz

-

-

ns

etcn

ns

OIY
-I&,.

1.8

-

65

25

-

B

25

-

130

-

RL= 150n

B

25

-

0.03

%

RL = 150n

B

25

0.03

Degrees

Overshoot

B

25

-3dB Bandwidth

VOUT= 100mV

B

25

Settling Time to 1%

2V Output Step

B

Settling Time to 0.1 %

2V Output Step

75

%
MHz
ns
ns

VIDEO CHARACTERISTICS
Differential Gain (Note 15)
Differential Phase (Note 15)
NOTES:
5. VCM = ±2.5V. At -40°C Product is tested at VCM = ±2.25V because short test duration does not allow self heating.
6. RL = 1DOn, VIN = 2.5V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output
is considered disabled when -10mV ~ VOUT ~ +10mV.
7. VIN = OV. This is the maximum current that can be pulled out of the Disable pin with the HA5024 remaining enabled. The HAS024 is
considered disabled when the supply current has decreased by at least 0.5mA.
8. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
9. FPBW = Slew Rate. V
= 2V.
2nV pEAK ' PEAK
to. RL = lOOn, VOUT = lV. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay.
11. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only.
12. VIN = +2V, DISABLE = +5V to OV. Measured from the 50% point of DISABLE to VOUT = OV.
13. VIN = +2V, DISABLE

=OV to +5V. Measured from the 50% point of DISABLE to VOUT =2V.

14. VIN = OV, Force VOUT from OV to ±2.5V, tR = tF = 50ns, DISABLE = OV.
15. Measured with a VM700A video tester using an NTC-7 composite VITS.
16. VOUT = ±2.5V. At -40°C Product is tested at VOUT = ±2.25V because short test duration does not allow self heating.

3-373

oJ

ns

Za:

!c~
a: a.

W2
~et

HA5024
Test Circuits and Waveforms

HP4195
NETWORK
ANALYZER

FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS

YIN

o-....,---;(+"'iii>_-_--o

YOUT

500
YOUT

FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT

FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT

Vertical Scale: VIN = lV/DiY., VOUT = lV/Diy.
Horizontal Scale: SOns/DiY.

Vertical Scale: VIN = 100mV/Diy., VOUT = l00mV/Diy.
Horizontal Scale: 20nS/Diy.

FIGURE 5. LARGE SIGNAL RESPONSE

FIGURE 4. SMALL SIGNAL RESPONSE

3·374

Y+~~~~~~
__ __

Schematic (One Amplifier of Four)

Qpl

~~~4-t---t~l~:t- ~_,

Rzo

I 1.2:~*
~QP2 ~QP3

,
R1

~QNl

_

I rK...Qp12

R7
15K

R)
6K

T

R4
800

Y-o

r-.

1'1.4pF
R28
20

R12

280

QN13

+IN

t::.--l----t·
II

II

Je:Qp13

1 ttl
R33
800

IJQ~

t
QP7~

----

t=:o

~

r;-l

CIt

T 1.4PF......
QN1;r

~ t:J~ I

J

.140

-IN

QN2

QN3

c1

I..

QP6

QN6....t-- .......

DiS

~

Qp15

2.c:..
Hzl

~

140

ICQN10
R14

280
R13
1K

R32

QN14

~8

R23 200

~:io>h. QN19;,;;:t-- R30
~R261
'I ~7
200

5

L-.-OUT

QNll
lQN?=5

1
OPERATIONAL
AMPLIFIERS

1 11 1

11

HA5024

Application Information

Driving Capacitive Loads

Optimum Feedback Resistor

Capacitive loads will degrade the amplifier's phase margin
resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as
shown in Figure 6.

The plots of inverting and non-inverting frequency response,
see Figure 11 and Figure 12 in the Typical Performance
Curves section, illustrate the performance of the HA5024 in
various closed loop gain configurations. Although the bandwidth dependency on closed loop gain isn't as severe as that
of a voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier's unique relationship between bandwidth and RI=All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier's bandwidth is
inversely proportional to RF. The HA5024 design is optimized for a 10000 RF at a gain of + 1. Decreasing RF in a
unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is
more stable, so RF can be decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth.
GAIN

(Act>

RF(O)

BANDWIDTH
(MHz)

-1

750

100

+1

1000

125

+2

681

95

+5

1000

52

+10

383

65

-10

750

22

.....

VIN

~

Ry

-=..::-

R
VOUT

'iCc

RF
RI

-=-=FIGURE 6_ PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR,R

The selection criteria for the isolation resister is highly
dependent on the load, but 270 has been determined to be
a good starting value.

Power Dissipation Considerations
Due to the high supply current inherent in quad amplifiers,
care must be taken to insure that the maximum junction temperature (TJ, see Absolute Maximum Ratings) is not
exceeded. Figure 7 shows the maximum ambient temperature
versus supply voltage for the available package styles (Plastic
DIP, SOIC). At ±5Voc quiescent operation both package
styles may be operated over the full industrial range of -40°C
to 85°C. It is recommended that thermal calculations, which
take into account output power, be performed by the designer.
130r-r--.--.--.--.-~--'--'--'-~r--r~

PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors
and chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short especially for the power supply decoupling components and
those components connected to the inverting input.
Attention must be given to decoupling the power supplies. A
large value (1 011 F) tantalum or electrolytic capacitor in parallel with a small value (0.1IlF) chip capacitor works well in
most cases.
A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier's inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. It is
recommended that the ground plane be removed under
traces connected to -IN, and that connections to -IN be kept
as short as possible to minimize the capacitance from this
node to ground.

5

7

9

11

13

15

SUPPLY VOLTAGE (±V)

FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE
VB SUPPLY VOLTAGE

EnableIDisable Function
When enabled the amplifier functions as a normal current
feedback amplifier with all of the data in the electrical specifications table being valid and applicable. When disabled the
amplifier output assumes a true high impedance state and
the supply current is reduced significantly.

3-376

HA5024
The circuit shown in Figure 8 is a simplified schematic of the
enable/disable function. The large value resistors in series with
the DISABLE pin makes it appear as a current source to the
driver. When the driver pulls this pin low current flows out of the
pin and into the driver. This current, which may be as large as
3501JA when external circuit and process variables are at their
extremes, is required to insure that point "A" achieves the
proper potential to disable the output.The driver must have the
compliance and capability of sinking all of this current.
When Vee is +5V the DISABLE pin may be driven with a
dedicated TIL gate. The maximum low level output voltage
of the TTL gate, 0.4V, has enough compliance to insure that
the amplifier will always be disabled even though D1 will not
turn on, and the TTL gate will sink enough current to keep
point "A" at its proper voltage. When Vee is greater than +5V
the DISABLE pin should be driven with an open collector
device that has a breakdown rating greater than Vee.
Referring to Figure 8, it can be seen that R6 will act as a pull-up
resistor to +VCC if the DISABLE pin is left open. In those cases
where the enable/disable function is not required on all circuits
some circuits can be permanently enabled by letting the DISABLE pin float. If a driver is used to set the enable/disable level,
be sure that the driver does not sink more than 201JA when the
DISABLE pin is at a high level. TTL gates, especially CMOS
versions, do not violate this criteria so it is permissible to control
the enable/disable function with TTL.
+vcc
R6
15K

its equivalent is used to select channels its logic must be break
before make. When these conditions are satisfied the
HA50241P is often used as a remote video mUltiplexer, and the
multiplexer may be extended by adding more amplifier ICs.
Low Impedance Multiplexer
Two common problems surface when you try to mUltiplex
multiple high speed signals into a low impedance source
such as an AID converter. The first problem is the low source
impedance which tends to make amplifiers oscillate and
causes gain errors. The second problem is the multiplexer
which supplies no gain, introduces all kinds of distortion and
limits the frequency response. Using op amps which have an
enable/disable function, such as the HA5024, eliminates the
multiplexer problems because the external mux chip is not
needed, and the HA5024 can drive low impedance (large
capacitance) loads if a series isolation resistor is used.
VIDEO
R4
INPUT
75
#1 o-'---il~~Miv-

R3
681

-

...I

r+

Za::
O!:!:!
-IL

100

!

R6
75

R33

5V

ALL
OFF

-

Qp18

-

-5V
VIDEO
INPUT
#3

A

C(CI)

1 R21

0,
R7
15K

VIDEO OUTPUT

TO 75(1 LOAD
__---':':~~:::;

R'4
75

R"
75

ENABLEIDISABLE INPUT

=

FIGURE 8. SIMPLIFIED SCHEMATIC OF ENABLEIDISABLE
FUNCTION

R'3
681

R'2
681
+5V

Typical Applications

VIDEO
INPUT
#4

R'9
75

Four Channel Video Multiplexer
Referring to the amplifier U1A in Figure 9, Rl terminates the
cable in its characteristic impedance of 750, and R4 back
terminates the cable in its characteristic impedance. The
amplifier is set up in a gain configuration of +2 to yield an
overall network gain of + 1 when driving a double terminated
cable. The value of R3 can be changed if a different network
gain is desired. R5 holds the disable pin at ground thus
inhibiting the amplifier until the switch, 81, is thrown to position 1. At position 1 the switch pulls the disable pin up to the
plus supply rail thereby enabling the amplifier. Since all of
the actual signal switching takes place within the amplifier,
its differential gain and phase parameters, which are 0.03%
and 0.03 degrees respectively, determine the circuit's performance. The other three circuits, U1 B through Ul [) operate in
a similar manner.
When the plus supply rail is 5V the disable pin can be driven by
a dedicated TIL gate as discussed earlier. If a multiplexer IC or

3-377

R,B
75

=
+5VIN.
O.lIlF

R,B
681

R'7
681

1 1·

JJ

+5V

10llF

-SVIN.
O.lIlF

11

JJ

.-sv
10JlF

NOTES:

17. U, is HA50241P.
1B. All resistors in U.
19. 5, is break before make.
20. Use ground plane.
FIGURE 9. FOUR CHANNEL VIDEO MULTIPLEXER

t(:::i
a:: 0..
W:::i
~C(

HAS024
Referring to Figure 10, both inputs are terminated in their
characteristic impedance; 750 is typical for video applications. Since the drivers usually are terminated in their characteristic impedance the input gain is 0.5, thus the amplifiers, U2,
are configured in a gain of +2 to set the circuit gain equal to
one. Resistors R2 and R3 determine the amplifier gain, and if a
different gain is desired R2 should be changed according to the
'equation G = (1 + R3"R2)' R3 sets the frequency response of
the amplifier so you should refer to the manufacturers data
sheet before changing its value. Rs, Cl and D1 are an asymmetrical charge/discharge time circuit which configures U1 as a
break before make switch to prevent both amplifiers from being
active simultaneously. If this design is extended to more chan-

nels the drive logic must be designed to be break before
make. R4 is enclosed in the feedback loop of the amplifier so
that the large open loop amplifier gain of U2 will present the
load with a small closed loop output impedance while keeping the amplifier stable for all values of load capacitance.
The circuit shown in Figure 10 was tested for the full range of
capacitor values with no oscillations being observed; thus,
problem one has been solved.The frequency and gain characteristics of the circuit are now those of the amplifier independent of any multiplexing action; thus, problem two has been
solved. The multiplexer transition time is approximately 15~s
with the component values shown.

INPUT B _----~~------.,

INPUTA_~~-----------, L-~~~~~~L:~_5~v~-t
D1A
lN4148

CHANNEL
SWITCH----+

>.:-......."Jtr-*--G

OUTPUT

+5V

NOTES:

INHIBIT ...........'1--'

1. U2: HAS022124.

D1B
lN4148

R6
lOOK

2. Uf CD4011.

FIGURE 9. LOW IMPEDANCE MULTIPLEXER

Typical Performance Curves
5
VOUT = 0.2Vp.p

4 I- CL=10pF

II

fI

130

;'

120

!l!z

=

!.
:z:

15
~z

i'

95

/

~

...'?

III

~

~

~

:2-

"I~

5

:--- r- GAIN PEAKING
I
500

~

iii'

"-

I

........ r-...

I

.....

o

650
800
950
FEEDBACK RESISTOR (0)

1100

130

........ 1000..

~

...z

o ~
1500

I

", ~ANLJH

120

,

110

/

III

10

',,-

350

li!:

-

-3dB BANDWIDTH

~

90

--

5

FIGURE 12. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE

VOUT 0.2Vp.p
CL= 10pF
Ay=+2

~

iii!:

900
1100
1300
FEEDBACK RESISTOR (0)

700

500

III

C!

~ ........ ....
GAIN PEAKING

200

10 ~

:2-

FREQUENCY (MHz)

N'loo

-r-

~

·180 -

FIGURE 11. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY

:z:

-

-

i\..

~

·135

VOUT = O.2Vp.p
CL=10pF
Ay=+l

·3dB BANDWIDTH

z

·90

~\.

Ay = ·10, RF = 7500

>
iii!: -315

:z:

C!

45

Ay = +10, RF'= 3830

c(

:z:

180

100

~

~

52

IV

90

~

~

80

~

o

/

200

V

..J

-- -

etC/)
Za:
O!!!
-I&..

I I I
VOUT = O.2Vp.p _
CL= 10pF
Ay=+l

a: a..

W:il

~

\
GAIN PEAKING

!;;::::i

6

iii'

4:2C!

~

2

~

~

oC!

800

400

800

1000

LOAD RESISTOR (0)

FIGURE 14. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE

FIGURE 13. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
80

"~.....1\

N' 60

:z:

!.
:z:

\

§
~

40

z
~

...'?
III

20

o

200

VOUT = O.1Vp.p
CL= 10pF

VOUT = 0.2Vp.p
CL=10pF
Ay = +10

1-

~12~~-'~---+--~--~--+---+---r-~~~

\

~

8!

~ 6r--+-7~~~~~~-

"- ~

OL-~~~

350

500
650
FEEDBACK RESISTOR (0)

800

FIGURE 15. BANDWIDTH vs FEEDBACK RESISTANCE

950

o

200

__

~~

__

~

__

~~

400
600
LOAD RESISTANCE (0)

__-L__
800

FIGURE 16. SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE

3-379

J-~

1000

~et

HA5024

Typical Performance Curves

VSUPPLY = f:SV,

"'v = +1, RF = lkn, RL = 400Q, TA = 2S0C,

Unless Otherwise Specified (Continued)
0.08

0.10

FREQUENCY = 3.58MHz

FREQUENCY" 3.58MHz

I

0.08

~

~

I

0.06

RL = 750

I

If

;i!

§

w 0.04

~

Cii"

""-

w 0.06
w

"""-"'

/'
V'RL=1500

,

a:
w

II..

~

0.02

0.00

,~

5

CI

I/J

e.
I/J

~
:z:

7
9
11
SUPPLY VOLTAGE (±V)

0.04
RL"~OO

"-

....
c(

~

"'

r-.........

~ RL" lkn
3

rr:

13

§

0.02

I/J

a:

-'-

w

II..
II..

is

3

15

~

~

tc

HD2,

,

~

~I/J

.-

/

I

I

~

a: -40r-rH~~++~ffi-~~~~-r~m&~

,I',"

·70

4OI-H-I+IH*--+~+mfr-~H+Hm~~~~~

Q

IY

3RD ORDER IMD

~ ......

H~

·50 ' -

~

1
FREQUENCY (MHz)

10

~~

~

NEGATIVE PSRR

0.001

0.01

__

I I IllJ!1 .111 Ulli

POS~~EPSRR

11111

111111

0.1
FREQUENCY (MHz)

10

30

FIGURE 20. REJECTION RATIOS va FREQUENCY

12

8.0
RL=1000
VOUT" 1.0Vp.p
Ay=+l

RLOAD = 1000
VOUT = 1.0Vp.p

7.5

...oS

/
L

~

w

Q

7.0

ElCIi
!

6.5

-IH-++IHH-7'1I.oo';,jo'Fl\I#I---f+f+tHII---f-l

·80 I-H-I+IH*--

FIGURE 19. DISTORTION VB FREQUENCY

5!

CMRR

-60
·70

HD3

·90
0.3

"-

15

m'~~~~*-++~ffi-~+H~~rH~~~
~

;

H:\

U" -60
III

Z

13

•1°1-+-IH-t*lt-+-Il+ttHtl-+-I+tHtflI-t-i+ttttllf--:loIII

-50

0

7
9
11
SUPPLY VOLTAGE (±V)

O~;Ay~=r+~ln*--~++~--+114~~4-~HHH--+1

VOUT" 2.0Vp..p
CL=30pF

...oS

I
5

FIGURE 18. DIFFERENTIAL PHASE VB SUPPLY VOLTAGE

-40

-80

\
./'

RL=lkn

0.00

FIGURE 17. DIFFERENTIAL GAIN VB SUPPLY VOLTAGE

~

~
"
r~ ~~

RL=750

- 'V

...

'/
./

-""--

10

~
w

Av = +10, RF = 3830

Q

Z

Q

V'

8

5!"-

I

...

tc
CI
!

... t--.

6

I

Ay=+2,RF=6810 -

---

Av=+l,RF=lkn

4

6.0
-50

·25

0
25
50
75
TEMPERATURE (oC)

100

125

3

FIGURE 21. PROPAGATION DELAY va TEMPERATURE

5

7
9
11
SUPPLY VOLTAGE (±V)

13

15

FIGURE 22. PROPAGATION DELAY va SUPPLY VOLTAGE

3·380

HA5024

Typical Performance Curves

VSUPPLY = ±5V. Av = +1. RF = 11<0. RL = 4000, TA = 2SoC,

Unless Otherwise Specified (Continued)

-

500
Your = 2OVp.p
450

Ul'

~

.-'

.

400

~

II:

...

250

w

l---'

..V

UI

200

0.4

-

iii"

:!!.

..........

0.2

~
CI

/~SLEW RATE . _ f-

w

;=

r--.....

-'

!( 300

I
Your = 0.2Vp.p
CL = 10pF

0.6

+ SLEW RATE

350

~

0.8

C

w

/'-

0

-..........

N

::i
c(

-0.4

:Ii
II:

-0.6

0

~

-0.8

I

-1.0

100

~

Ay=+1,RF=1k!l ......

z

150

Ay= +2, RF = 6810

~

-0.2

~

Ay= +5, RF = 1k!l-

..... ..........

/ ...........

Ay = +10, RF = 3830

-1.2
-SO

-25

0
25
50
75
TEMPERATURE <"C)

100

125

10

5

--=

.....

............

15
20
FREQUENCY (MHz)

r--........
30

25

FIGURE 24. NON-INVERTING GAIN FLATNESS VB FREQUENCY

FIGURE 23. SLEW RATE VB TEMPERATURE
0.8
Vour = 0.2Vp-p
CL = 10pF
RF =7500

0.6
0.4

iii"
z

:!!. 0.2
C

0

c

~

-0.2

0

-0.6

CI

:Ii
II:

z

"'-'\.,

-0.4

f-

Ay=-1

i

~~

'\.

-0.8
-1.0

-

~

"

/. \.' \

Ay=-10

"-

Av=-5

"

1

-1.2
5

15

10

/-

/
'{

/
Av=-2_

~~o
100

I
25

20

30

FREQUENCY (MHz)

FREQUENCY (kHz)

FIGURE 25. INVERTING GAIN FLATNESS vs FREQUENCY

FIGURE 26. INPUT NOISE CHARACTERISTICS

1.5

1.0

2

\

l

~

" .........t"-

t--

0.5

r- ~

.J'

~

J..--

--

V

0.0
-60

-4
-40

-20

0

20

40

60

80

100

120

140

TEMPERATURE (DC)

1/

-60

-40

-20

0

20
40
60
80
TEMPERATURE (DC)

100

120

140

FIGURE 28. +INPUT BIAS CURRENT VB TEMPERATURE

FIGURE 27. INPUT OFFSET VOLTAGE VB TEMPERATURE

3-381

HAS024

Typical Performance Curves

VSUPPLY = ±5V, Av = +1, RF = lkn, RL = 4000, TA = 25°C,

Unless Otherwise Specified (Continued)
4000

22

l

\

20

I

B
~

ID

~

;; 3000

1\

18

16

-60

'"

-40·20

.........

0

I
~

I'-- """-

20

40

2000

!/

60

100

80

120

1000
-60

140

~

/

·20

-40

0

FIGURE 29. -INPUT BIAS CURRENT VB TEMPERATURE

74

i

J

, """

~

15

~~~

]

~ I""""

~ I"'"

10

~

~~

iii'

70

0

68

3

4

5

to-...

a: 66
z

~

..,w

6

7

9

8

10

11

12

13

14

15

·PSRR

......

64

60

250 C

I

~~
t---

58
·100

CMRR

J

I"-.....

I"o

·50

SUPPLY VOLTAGE (±V)

I

I

J'V

.... ..... /...
'" -'
0

o

1

2

I

+10V

I-- f-+5V

+15V

.....

~

5

6

7

8

120 140

""""

r---r-..

50
100
150
TEMPERATURE (DC)

200

250

4.0

V~

II ~
",

I
J

/
4

--

J

J

..... r--.
-~ ..... ......
r--. .....

3

100

FIGURE 32. REJECTION RATIO VB TEMPERATURE

FIGURE 31. SUPPLY CURRENT VB SUPPLY VOLTAGE

40

80

~

I

:!!.

ij

I'
5

~

w
a: 62

I

60

~PSRR

72

550 C
1250 C

40

FIGURE 30. TRANSIMPEDANCE VB TEMPERATURE

25

20

20

TEMPERATURE (DC)

TEMPERATURE (DC)

I
\

/

/

~

i"'"

u

~~

/

9 10 11 12 13 14 15

DISABLE INPUT VOLTAGE (V)

V

V
~

~

~

/

3.6

-60

-40

·20

0

20

40

60

80

100

120

TEMPERATURE ~C)

FIGURE 33. SUPPLY CURRENT VB DISABLE INPUT VOLTAGE

3-382

FIGURE 34. OUTPUT SWING VB TEMPERATURE

140

HA5024

Typical Performance Curves

VSUPPLY= ±5V. AV= +1. RF= 1kO. RL = 4000. TA =2SoC.

Unless Otherwise Specified (Continued)
30

1.2

1.1

.

"iL

.s>- 1.0 \

~

I-

0

~

:>
0.9

/'

\ ".....

-

/

V

/

/

r-""

0.8
0.01

0.10

1.00

-60

10.00

·40

-20

0

LOAD RESISTANCE (len)

1.0

,

\

w

II:
II:
:::I
U

~

0.5

80

100

120

140

-

g

·40

t\..

-20

251-+-1--+

O!!:!
-u.

20

W:::ii

~c(

0

"""- r--.-.

20

40

60

80

100

120

3

140

4

5

6

FIGURE 37. INPUT BIAS CURRENT CHANGE BETWEEN
CHANNELS vs TEMPERATURE

32
1 1

3D

VOUT= 2Vp.p

".".

28

V

!

~

13

14

ENABLE

15

16

.A

26

'-

ENABL~

-...
Ay=+5,RF=lkn~
.~f".....
.....
Ay=+l,RF=lkn ......
r--......
r--...

-0.8

~

150
-1.0
100

-SO

-25

25

o

50

75

100

Ay = +10, RF = 3830

-1.2

125

5

10

25

15
20
FREQUENCY (MHz)

TEMPERATURE ("C)

FIGURE 22. SLEW RATE VB TEMPERATURE

--"'-

...........

30

FIGURE 23. NON-INVERTING GAIN FLATNESS VB FREQUENCY

0.8

1000
VOUT = 0.2Vp.p
CL= 10pF
RF = 7500

0.6

iii'
:!!.

z

0.4

~

0

w

-0.2

.J

-0.4

0

!:lI

~
a:
0

z

-,

0.2

-0.6

......

r- Ay(10

-1.2.

I

"',

L

IL

"<

Ay=~2

'"

\..
15

w

!II
0

z
w

~

-

z
~
w
a:
a:

400

:.J

§!

::>

()

200

I

20

25

30

FREQUENCY (MHz)

FREQUENCY (kHz)

FIGURE 24. INVERTING GAIN FLATNESS VB FREQUENCY

FIGURE 25. INPUT NOISE CHARACTERISTICS

1.5

1.0

~

600

w

!II

0

Ay=-S--""';- r-

\..

10

5

I

~~

'\.

-0.8
-1.0

.s.

Ay=-l

/"

I¥

800

~:>

2

1\
I" ~

l

--

......... :--.

0.5

-I-

G
~

L

-2

III

/

0.0
-60

0

~
w
a:
a:

-40

-20

0

20

40

60

80

100

120

140

-4
-60

,..",

".-

V
-40

-20

0

20

40

60

80

100

120

140

TEMPERATURE (DC)

TEMPERATURE ("C)

FIGURE 27. +INPUT BIAS CURRENT VB TEMPERATURE

FIGURE 26. INPUT OFFSET VOLTAGE va TEMPERATURE

3-394

HA5025
Typical Performance Curves

VSUPPLY = ±5V, A.J = +1, RF = 1kn, RL = 4000, TA = 25°C, Unless Otherwise Specified

4000

22

~

!i!

20

1\

0

~

~

1\~

'":::>

II:
II:

ID

18

16
-60

-40

-20

",

W 3000
U

~

........ .........

0

20

~

-

40

,/

:;

~

~

-

60

80

100

120

2000

1000

140

II

~

,/

~

I

I

20

~

15

~ -\
~~

~

10

--

i""""

."

~

,

~

~
~

5

0

~
II:
z

~

'"
ia
II:

I

68

.....

7

8

10

9

64
62

11

12

13

14

I

58
-100

15

I

I
30

-

r-+5V

IZ

'":::>

II:
II:

...... r--

0

~

a..
a..

:::>

III

J

20

10

o

'-

o

~ ......

i ' ......

~

"

......

~ r--.

~~

I
o

~

~<

...........

-

50

r-...
r--

100

~
Cl

J

J

-

W::i5

150

200

250

4.0

+15V

,.....



~

:::>
0

~

.;'V

V

/

,/

~

/'

,/

3.6
1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

DISABLE INPUT VOLTAGE (V)

~

~

-~

0

~

40

60

80

100

1~

TEMPERATURE (oC)

FIGURE 32. SUPPLY CURRENT VB DISABLE INPUT VOLTAGE

3-395

FIGURE 33. OUTPUT SWING vs TEMPERATURE

140

HA5025
Typical Perfonnance Curves

VSUPPLY = ±5V, IV = +1, RF = lkO, RL = 4000, TA = 25°C, Unless Otherwise Specified (Continued)

30r----------,-----------,----------,

1.2

1.1

~!;
~

>

\

.§. 1.0

~

10r-------~~-----------+----------,

0.9

O~

_________ L_ _ _ _ _ _ _ _ _ _L __ _ _ _ _ _ _ _
0.10

0.01

1.00

~

V

\ "-

.., . /

-

......

V

/

,,/

0.8
-60

10.00

-40

·20

0

LOAD RESISTANCE (leO)

20

40

60

80

100

120

FIGURE 35. INPUT OFFSET VOLTAGE CHANGE BETWEEN
CHANNELS vs TEMPERATURE

FIGURE 34. OUTPUT SWING va LOAD RESISTANCE

·30

1.5

Ayl=+ll

I I I

VOUT= 2Yp.p

~

~

~

\

"

'- .........
~

0.5

·60

/'

iii'
:!!. -50

-40

·20

0

20

,,~

~

.......

0.0
40

-

60

./

~ -60
11:
w

..,~

II)

·70

80

100

120

-eo

140

/

V

0.1

FREQUENCY (MHz)

FIGURE 36. INPUT BIAS CURRENT CHANGE BETWEEN
CHANNELSvsTEMPERATURE

FIGURE 37. CHANNEL SEPARATION vs FREQUENCY

~w.

ilI!ini:E = OY

0 '- VIN = 5Vp.p
·10 ;- RF =7500

iii' ·20
:!!.
:c -30
CI

:c

b
w

·50

w ·60

II.

·70

----

~

-40
~

...

-'

i"""

10
1-

~

0.1

~

0.01

iii 0.001

"'

RL= 1000
~

"'"

-i"o

~

!'-

:-....

,
~

\

·80
1

10

20

0.001

FREQUENCY (MHz)

180
135

~

0.01

0.1

1

10

o 5
z

-45 ~

FIGURE 39. TRANSIMPEDANCE VB FREQUENCY

3·396

II)

-90 ~

·135
100

FREQUENCY (MHz)

FIGURE 38. DISABLE FEEDTHROUGH va FREQUENCY

ffi

w
90 II:

45 _
w

~

0.1

30

10

1

TEMPERATURE (DC)

5II:

~

-40

.... 1.0

!

140

TEMPERATURE (DC)

...

HA5025

Typical Performance Curves

a

VSUPPLY =±5Y, "" = +1, RF = 1kn, RL = 4000, TA = ~c, Unless Otherwise Specified (Continued)
10

!.

~

II

"'"

w

0

z
~
w

0.1
0.01

Q.

l!l 0.001
-_..!.....-....- - o OUT

IN

OUT

loon

-'
«en

Za:

O!!:!
-II..

~::::i
a: a.
W:5

FIGURE 2. TRANSIENT RESPONSE

INP;V

IN;:::::Jr-----------------,~

Ir--------,L

OV~

1

,J__ _
- i- f

OUTPUT - 90% - - - ,
IN
__ .!0.!o __ J __ _
, _ , SLEW
,
'RATE=
: :
V/IlT

OVERSHOOT

, ERROR BAND
, ±10mVFROM
, FINAL VALUE
NOTE: Measured on both positive and negative transitions.

FIGURE 3. SETTLING TIME

FIGURE 4. RISE TIME

TA = 25°C, Rs = 50n, RL = 1kn

TA = 250 C, RS = 50n, RL = 100n
+10V RESPONSE

+10V RESPONSE

3-401

~«

HA-S033
Test Circuits and Waveforms

(Continued)

500mV

OV
500mV

VOUT
OV

TA = 25°C, RS

=500, RL = 1000

PULSE RESPONSE

Schematic Diagram
V+o-~~------~~~------~~--~--~

___

~---,

ApplicaUonlnformaUon
Layout Considerations
The wide bandwidth of the HA-5033 necessitates that high
frequency circuit layout procedures be' followed. Failure to
follow these guidelines can result in marginal performance.
Probably the most crucial of the RFlvideo layout rules is the
use of a ground plane. A ground plane provides isolation and
minimizes distributed circuit capacitance and inductance
which will degrade high frequency performance. This ground
plane shielding can also incorporate the metal case of the
HA-5033 since pin #2 is internally tied to the package. This
feature allows the user to make metal to metal contact
between the ground plane and the package, which extends
shielding, proVides additional heat sinking and eliminates the
use of a socket, IC sockets contribute inter-lead capacitance
which limits device bandwidth and should be avoided.

For the PDIp, pin 6 can be tied to either supply, grounded, or
simply not used. But to optimize device performance and
improve isolation, it is recommended that this pin be grounded.
Other considerations are proper power supply bypassing
and keeping the input and output connections as short as
possible which minimizes distributed capacitance and
reduces board space.
Power Supply Oecoupling
For optimum device performance, it is recommended that
the positive and negative power supplies be bypassed with
capacitors to ground. Ceramic capacitors ranging in value
from 0.011lF to O.1IlF will minimize high frequency variations
in supply voltage. Solid tantalum capaCitors 11lF or larger will
optimize low frequency performance.
It is also recommended that the bypass capacitors be
connected close to the HA-5033 (preferably directly to the
supply pins).

3-402

HA-5033
Graph is based on:

i

2.4
2.2
Q 2.0

Z

~

~

is

a:

~

..J

1.8

1.6
1.4
1.2
1.0

~ 0.8

12

~

!

0.6
0.4

~ 0.2
~

-,--

Where: TJMAX = Maximum Junction Temperature of the Device

QUIESCENT PD = 0.72W
AT Vs ±12V, ICC = 30mA

TA = Ambient Temperature
8JA = Junction to Ambient Thermal Resistance

O~----~r------r------~----~------,
25
45
65
85
125
105
TEMPERATURE (DC)

FIGURE 5. FREE AIR POWER DISSIPATION

Typical Applications

(Also see Application Note AN548)
V+
VIDEO
SIGNAL
INPUT

+12V
O.l~F

~

VIDEO
OUTPUT

Rl
60n

75n

R2
15n

RG-58

V+

V-

-

V-

"T~1
"":"

"="

goon

loon

FIGURE 7. VIDEO GAIN BLOCK

FIGURE 6. VIDEO COAXIAL LINE DRIVER 50Q SYSTEM

OV

OV

OV

OV

POSITIVE PULSE RESPONSE

NEGATIVE PULSE RESPONSE

3-403

-'
C(U)
Za:

O!:!!
-IL

!cc:::;
a: a.

W:i
~c(

HA-5033
Typical Performance Curves

>"

7

UJ

6

.s
C!I

~
~

Vs = ±15V

,I.
_VS=±12V

~~

5

4

~

3

~

/

~~

r

2

l.......r""
I

,

_~s=±5V

·80

t::=-

~
!z

-

If

I

Iii
~

40r-----r--------r--------~------_,

1

8

8~ 20F:!~~~~~~~

- - I~~
Vs=

III

~~

rOY

-I

1

-40

04080
TEMPERATURE (oC)

120

10~----~-------+--------+_------~

0-55

160

FIGURE 8. INPUT OFFSET VOLTAGE vs TEMPERATURE

30

30

UJ

a:

·25

25
75
TEMPERATURE (oc),

125

FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE

3000

I

Vs = ±15V, VIN = ±10V

I

Vs= ±15V

I 1

C

.s

!zUJ

20

~

vi ±l~V

a:
a:

:l

u

Vs= ±10V

;t
UJ
~

10

UI

1000

UI

-----

----

FALL (RL = lOOn)

""'-

UJ

!c
a:

Vs = ±5V

~

0.
0.
:l

~

/

\1

FALL (RL = 11<0)
2000

I
I
RISE (RL= 11<0) / '

./
,/

RISE (RL = lOOn)

I

o

·25

·55

25

·55

125

75

·25

FIGURE 10. SUPPLY CURRENT va TEMPERATURE

1400
1300
1200
1100
~ 1000
~ 900
;. 800
!c 700
a: 600

2200 Vs =±15V, RL = 11<0
TA = 25°C, VIN g ±10V
2000

'\..

"-

<~
UJ

!ca:

1400

J

,

I

",FALL

1200

...........

;t 1000
~ 800 --RiSE .................

UI

600
200

o

~UI

""~

""'- ...........

400

100
1000
CAPACITANCE (pF)

125

FIGURE 11. SLEW RATE va TEMPERATURE

2400

1800

75

TEMPERATURE (OC)

TEMPERATURE caC)

'iii' 1600

25

-5000

40

500
300
200
100

10,000

""
" " """
" "-"' ""
" ""-.................. ....

Vs =±15V, RL = loon
TA =25°C, VIN = ±10V

~

FALL

RIS~~ ~

~

o

100

1000

.....

5000

CAPACITANCE (pF)

FIGURE 13. SLEW RATE va LOAD CAPACITANCE

FIGURE 12. SLEW RATE VB LOAD CAPACITANCE

3·404

10,000

HA-5033
Typical Performance Curves

(Continued)

80
Vs = ±15V, TA = 25°C
60

5"

40

In

20

g

~

5...

0

5

·20

0

·40

jE

I!:::>

-60

-""

~~

RL='0kn

"...,..~

L

-80
·10

,/

/

II"""

900

V

RL= lkn

"
~ ~~I--"""

-

./

In

~

RL= 10kn

I

-8

-6

-4

X

~~
'#"

I-

...
::>

·2
0
+2 +4
INPUT VOLTAGE (V)

+6

+8

I'"

RL = 1000

./ ~

vr/

'" ~=500
V

·900
·10

+10

..".

.",

RL = 1000

...

·700

V

./ ~.Y

300

100
0
jE ·100
I::>
-300
I::>
0 ·500

I

RL = 500

5" 500

g

RL =lkn

I

I

Vs = ±15V, TA = 25°C
700

·8

-6

·4

·2
0
+2
+4
INPUT VOLTAGE (V)

+6

+8

+10

FIGURE 15. GAIN ERROR vs INPUT VOLTAGE

FIGURE 14. GAIN ERROR vs INPUT VOLTAGE

160
Vs = ±15, TA = 25°C

Vs =±15V, Vo=±10V

800

140

5" 120

g

In

~

5" 600

100

5
0

...:::>

RL= lkn

I-

...::>jE
5
...

g

80

r- -

VOUT = 0 SINKING
CURRENT

~

40

200

20

100

·55

·25

FIGURE

25
75
TEMPERATURE (oC)

0

125

,,~

/. ~

300

"

_I"""

I ~ ';/

,,
h

500

~ 400

60

I

I

700

-

VOUT=·10
VOUT=+10

I I

' "VOUT = 0 SOURCING
I
I
CURRENT

~ ~'
~~

~ ~~
10

16. GAIN ERROR vs TEMPERATURE

20

30

FIGURE

40

50 60 70
lOUT (mA)

80

90 100 110 120

17. VIN' VOUT vs lOUT

180

r--~

Y21

§Y21,Y21

135

iii
w
CJ
w

e.w

-'
c:I
Z

0(

w

~

90

1-1-'

W

II:

""'"

r\..

~ -!-o

Y"

45

11

Y,2
Y22
Y21

0
Y22

-I"-

i..I'!:

-45

!Ii
:r ·90

...

·135

i--"""Y12
-~

I

~ ,.J

"

10-4

-..

~Yll
Y,2

107
108
FREQUENCY (Hz)

107
108
FREQUENCY (Hz)

FIGURE 18. Y· PARAMETERS PHASE vs FREQUENCY

FIGURE 19. Y· PARAMETER MAGNITUDE VB FREQUENCY

3·405

....
 20
In
II:
W

~ 0.07

~

c 0.06
!:! 0.05

z

10K

lOOK
FREQUENCY (Hz)

1M

~
!:!

~

0.1

~

~

0.01

~
!:i 24

~

::Ii

II:

~

w

~

!:i
~

~

0

~

20

I!::::>

16

5

8

u-i
A-

4

2
INPUT VOLTAGE (RMS)

\

!~

NO HEAT SINK IN
FREE AIR

""

"" ......
'"

1M
10M
FREQUENCY (Hz)

100M

Vs =±10V

,

/

is = j5V

FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
6.0
5.5
'iii 5.0
::Ii 4.5
w 4.0
~ 3.5
!j
3.0
~ 2.5
5 2.0
1.5
0
1.0
0.5
0
10K

I

I

,,

VS=±15V,RL=lkQ

NOH~TSINK 1\

l

\

lOOK

,

0 100 200 300 400 500 600 700 800 900 lK
LOAD RESISTANCE (0)

3

Vs = ±15V, RL = loon

,

= 112v I
I

~~

:.= 12

I:!

t

sJl

u-i
A-

-,

1'-

1/

(

0

FIGURE 22. TOTAL HARMONIC DISTORTION vs INPUT VOLTAGE
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10K

TA = 25°C j,Vs= ±15V

w 28

~

1

lOOK

FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY

:.=

0

10K
lK
FREQUENCY (Hz)

100

.oJ

'iii

0.01

10M

./

0
::!i

.--"

0.02

€

f = 100kHz

z

II:

0.03

VS=±12V
RL= 1000

lz

~

0.04

«
:z:
.oJ

FIGURE 20. POWER SUPPLY REJECTION RATIO vs FREQUENCY·
1.0

0
::!i

II:

-'-~ 10

lK

Vs =-±12V, RL = loon
0.09- VIN=1VRM$
0.08

0

....

40

1".l

0.10

lZ

'" "
"" "'.

i

z 50

0

tiw

(Continued)
"

iD 70

IN FREE AIR

\

\

~

lG

FIGURE 24. OUTPUT SWING vs FREQUENCY (NOTE)

,

\

\.

"-

lOOK

1M
10M
FREQUENCY (Hz)

"

100M

lG

FIGURE 25. OUTPUT SWING vs FREQUENCY (NOTE)

NOTE:
This curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. If higher distortion
is acceptable, then a higher output voltage for a given frequency can be obtained. However, operating the HA-5033 with Increased distortion
(to the right of curve shown), will also be accompanied by an increase In supply current. The resulting increase In chip temperature must be
considered and heat sinking will be necessary to prevent thermal runaway. This characteristic is the result of the output transistor operation. If
the signal amplitude or signal frequency or both are Increased beyond the curve shown, the NPN, PNP output transistors Will approach a condition
of being simultaneously on. Under this condition, thermal runaway can occur.

3-406

Die Characteristics
SUBSTRATE POTENTIAL (Powered Up):

DIE DIMENSIONS:

51 mils x 67 mils x 19 mils
1300~m x 1700~m x 483~m

Unbiased
TRANSISTOR COUNT:

METALLIZATION:

20

Type: AI, 1% Cu
Thickness: 16kA ±2kA

PROCESS:

Bipolar Dielectric Isolation
PASSIVATION:

Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-5033

..J

4:0
Za:

IN

O!:!!
-u.
!ci::J
a: a..
W::::E
~4:

y-

3-407

~HARRlS

mJ

SEMICONDUCTOR

HA-5101, HA-5111
10MHz and 100MHz, Low Noise,
Operational Amplifiers

November 1996

Features

Description

• Low Noise •••.•••••..••••.••• ,. 3.0nVl..JHi at 1kHz

The HA-5101/5111 are dielectrically isolated operational
amplifiers featuring low noise. Both amplifiers have an
excellent noise voltage density of 3.0nV/--IHz at 1kHz. The
uncompensated HA-5111 is stable at a minimum gain of 10
and has the same DC specifications as the unity gain stable
HA-5101. The difference in compensation yields a 100MHz
gain-bandwidth product and a 50VlllS slew rate for the HA5111 versus a 10MHz unity gain bandwidth and a 10V/IlS
slew rate for the HA-51 01.

• Bandwidth................. 10MHz (Compensated)
100MHz (Uncompensated)
• Slew Rate • . • . . • . • • . • . . • . •• 10VlllS (Compensated)
SOViIlS (Uncompensated)
• Low Offset Voltage Drift. . . • • • • . • • • • • • . • .. 31lVJOC
• High Gain· •..•••••••••.••••.••••.••.•• 1 x 106VN
• High CMRRlPSRR ••.•••.••••••••..•••••.• 100dB
• High Output Drive Capability .•.•••....••..•. 30mA

Applications
• High Quality Audio Preamplifiers
• High Q Active Filters
• Low Noise Function Generators
• Low Distortion Oscillators
• Low Noise Comparators
• For Further Design Ideas, See Application Note AN554,
Harris AnswerFAX (407-724-7800) Document #9554

Pinouts

DC characteristics of the HA-5101/5111 assure accurate
performance. The O.5mV offset voltage is externally adjustable and offset voltage drift is just 3IlVf'C. An offset current
of only 30nA reduces input current errors and an open loop
voltage gain of 1 x 106VN increases loop gain for low distortion amplification.
The HA-5101/5111 are ideal for audio applications, especially low-level signal amplifiers such as microphone, tape
head and phono cartridge preamplifiers. Additionally, it is
well suited for low distortion oscillators, low noise function
generators and high Q filters.

Ordering Information

HA-5101, HA-5111 (PDIP, CERDIP, SOIC)
TOP VIEW

PART NUMBER
(BRAND)

TEMP.
RANGE ("C)

PKG.
NO.

PACKAGE

HA2·51 01-2

-55 to 125

B Pin Can

TB.C

HA3·5101-5

Oto 75

BLdPDIP

EB.3

HA7-51 01-2

-55 to 125

B LdCERDIP

FB.3A

HA9P51 01-5
(H51015)

01075

B LdSOIC

MB.15

HA9P5101-9
(H51019)

-4010 B5

B LdSOIC

MB.15

B Ld PDIP

EB.3

BLdCERDIP

FB.3A

HA-5101 (CAN)
TOP VIEW

HA3-5111-5

01075

NC

HA7-5111-2

-55 to 125

HA9P5111·5
(H51115)

01075

B LdSOIC

MB.15

HA9P5111-9
(H51119)

-40 10 B5

B LdSOIC

MB.15

4
V-leASE)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-408

File Number

2905.2

HA-5101, HA-5111
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 40V
Differential Input Voltage...................•............ 7V
Input Voltage ...................................... ±VSUPPLY
Output Current. . . . . . . . . . . . . . . . . .. Full Short Circuit Protection

Thermal Resistance (Typical, Note 2)
9JA (oCIW) 9JC (oCIW)
Can Package. . . . . . . . . . . . . . . . . . . .
165
80
94
N/A
PDIP Package. . . . . . . . . . . . . • . . . . .
CERDIP Package..... ...... .....
135
50
157
N/A
SOIC Package. . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5101/5111-2 ................•....•... -55°C to 125°C
HA-5101/5111-5 ............................ OOCt0750C
HA-5101/5111-9 .......................... -40°C to 85°C

CAUTION: Stresses abo"" those listed in "Absolute Maximum Ratings" may caUSe permanent damage to the device. This is a stress only rating and operaffon
of the device at these or any other conditions abo"" /hose indicated in the operational sections 01 this specification is not implied.

NOTES:
1. Maximum power diSSipation, including output load, must be designed to maintain the maximum junction temperature below 175°C for
hermetic packages, and below 150°C for the plastic packages.
2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±15V, Rs = 1000, RL = 2kO, CL = 50pF, Unless Otherwise Specified
HA-5101·2, -5; HA-5111·2,·5
TEST CONDITIONS

PARAMETER

TEMP
fC)

MIN

TYP

MAX

HA·5101·9. HA-5111-9
MIN

TYP

MAX

UNITS
..J



\.

1000

,.,..,..V

CI

~

r--

VOLTAGE

~

Iii
~

I!;

SOO

V

~

ICURRENT

~

o

o

10

100

10K

lK

·50

lOOK

·25

o

FREQUENCY (Hz)

25

50

75

100

125

TEMPERATURE (DC)

FIGURE 9. HA-5101111 NOISE SPECTRUM

FIGURE 10. OFFSET VOLTAGE vs TEMPERATURE

AV = 25000 Vs = ±15V (2.25I1Vp.P ATO)

AV = 25000, Vs = ±15V (12.89mVp.p RTO)

PEAK-To-PEAK NOISE O.lHz TO 10Hz

PEAK-To-PEAK TOTAL NOISE 0.1 Hz TO lMHz

20

250

200
~

/

·60

~/
·55

·25

I

V

-......

"""

.s
!Ew

150

~

a:
a:
:::)
u 100

~

~

III

"'-

"- ............r--

50

o

25

so

75

100

125

TEMPERATURE (DC)

o

·55

·25

o

25

-50

~

75

100

TEMPERATURE (DC)

FIGURE 11. INPUT OFFSET CURRENT vs TEMPERATURE

FIGURE 12. INPUT BIAS CURRENT vs TEMPERATURE

3-414

125

HA-5101, HA-5111

Typical Performance Curves
1.1

.....
Q 1.0

~

iI!

I I I I

!

1.1

I

"",io-' ",,'"

t...
SLEW RATE ..t
RISE TIME

~~

~; ~"'"

(Continued)

I""'r-- .......

140

100

~
~

iii" 80
:!!.
z 60

w

0.9

0.9

~

a:
0

~

0.8

a:

0.8

;=

!.
~
i=
w

!I!

~

0.7

II)

RL = 2kO, CL = 50pF
VS=±15V

I I I I I I I

0.6
·60

-40

·20

0
20
40
60
80
TEMPERATURE ('IC)

100

120

0 HA·5101

~

~ ..,..,

~

-- V --

-30

r::HASE

r-

~

50

100

10

100

lK

.c
!:i

;:;.- I"""

10M

100M

MlxIMU~

..J. :;;:::;;;-

l!i:

3

a:
a:
:::>
u

2

~

-

~
~

I

I

::::

400

450

a:c.

W:E

~ 30
u

g lOOK 1-_ _ _ _-+_ _ _ _ _+-_ _ _ _-1

!:iII.
!:i0

~

(100)

o

20
A
B
C
0

10
10K
(80) 5'-------10'-------11..
5- - - - - - ' 1 8
SUPPLY VOLTAGE (±V)

FIGURE 17. DC OPEN-LOOP VOLTAGE GAIN va SUPPLY
VOLTAGE

TA = 25°C, Vs =±15V

~~

C"

lM~~~~~~~~~~~~~~~~~

o

o

I

..........!,
VIN
+15mV
·15mV
+15mV
·15mV
20

40

VOUT
±15V
±15V
OV
OV
60

80
100
TIME (S)

120

140

FIGURE 18. SHORT CIRCUIT CURRENT vs TIME

3-415

Za:

!;t:::i

TYPICAL

II)

350

....


~
~

10K
lOOK
1M
FREQUENCY (Hz)

TA = 25°C

w

300

II.

FIGURE 14. OPEN·LOOP GAIN/PHASE vs FREQUENCY

FIGURE 15. INPUT OFFSET WARMUP DRIFT vs TIME
(NORMALIZED TO ZERO FINAL VALUE)
(SIX REPRESENTATIVE UNITS)

~~

135
180

TIME (SECONDS)

VN 10M
(dB)(140)

w

III

0.6

........ 1-0....

200 250

:E
II)

90 ~

~~

4

150

~

t:

jHilii

~

o

45

I""

5

~

·20

o

0.7 a:

TA=25oC,Vs=±15V

w 10

m
...o... ·10

III
a:

HA-5111

...

20

30

0

'iii

iili

...

w 40

~

GAIN

r'"

CI

~

~A~~~l

r'"
HA-5101

:cCI

FIGURE 13. SLEW RATE/RISE TIME vs TEMPERATURE

20

...

120
1.0 Q

160

HA-5101, HA-5111
Typical Performance Curves
25

(Continued)

1111111
11111"

20
15

-ss°C
PHASE

...

-5

'"'

:.1

- LI.

W

125°C
PHASE

~-10

-90~

~

-15

-135

'l1li

·20 Vs =±15V, Ao, = 10VN
RL =21<0, CL = 50pF
-25
10K
100K
1M
FREQUENCY (Hz)

iii

w

-180 ~

"

A:;'= 10

C 30
w
20

~

...'0~"'

~w

l1lllL

Q

w

-10

0

-20

9

~

10K

Ii

~

II!

::-55oC

9Q

III

10K

100K

1M
FREQUENCY (Hz)

%

~

~

-135 ...

~

V. =±15V, Ao, = 1VN
RL = 21<0, CL = 50pF

o

-90~

~l.

~

o

-60

iii'
:!!.

~

-460

1250CX'ASE
PHASE

w

-120

iii'
:!!.

z

10

"

0

·140

-40

!

..,'f'

,

,

,

-

~-

,

~+PSRR

1.1

,"

100

1K

10K
100K
FREQUENCY (Hz)

1M

TA = 25°C, v. = ±15V

10M

1111111

!;i

i

,,:::

~

II'"
-80

II: -100

·20

;"'
~
'f'-PSRRlCMRR

-60

II:

-10

,

o

---.",.

Ao, = 1

C

100M

FIGURE 22. HA·5111 REJECTION RATIOS VB FREQUENCY

i"~

I 11111

10M

-180

AV=10

20

I

-PSRRlCMRR

'f'

ia
II:

I
'f'

-100

~=11~bl

30

1M
FREQUENCY (Hz)

-LllI-U

-

z

FIGURE 21. HA-5101 FREQUENCY RESPONSE

40

100K

~ -80

-225
100M

10M

-

TA = 2SOC, V. = ±15V, Ao, = 100
10VN, RL = 21<0, CL = 50pF

TA=25oC,V.=±15V

~11I11

~ ·12

-

-

FIGURE 20. HA-5111 CLOSED·LOOP GAIN VB FREQUENCY

-6

~ ·9

-

-30

100M

GAIN

125°C\
GAIN

-3

!j

0

9

l5W

111111

r"

10

-225 ...

6

.......

11111

FIGURE 19. HA·5111 FREQUENCY RESPONSE

iii' 3
:!!. 0

1111

z

%

10M

Ao, =100

iii' 40
:!!.

1250~~
GAIN

iii' 10
:!!.
i!i 5
~ 0

~

50

IIJI
-55 C
GAIN

~~

IIIII
+PSRR

~

1,;''''

TA = 25°C, Vs = ±15V
RL = 21<0, CL = 50pF
10K

100K

1M
FREQUENCY (Hz)

10M

·120

100M

100

FIGURE 23. HA-5101 CLOSED·LOOP GAIN VB FREQUENCY

1K

10K
FREQUENCY (Hz)

100K

1M

FIGURE 24. HA-5101 REJECTION RATIOS VB FREQUENCY

3-416

HA-5101, HA-5111
Typical Performance Curves

1

1

•

1

1
1
1
1

(Continued)

,..

VOUT
4VIDIV.

VERROR

I

1
1
1
1
1

1
1

~

1
1

VSETTL~

---.1

+
If"

1'- 320n8

1

-

t;

FIGURE 26, HA-5101 SETTLING WAVEFORM 1,51lsID1V.

,

-8

J

I I

~
+ 11
10

I,

~L

1---1 '2S0C
9
11'1
100

I

12SoC

I 1000

-

1
200

+

~

1\
~
\
\

1

~

,

\

~ ·10

10kn

1I.().2V~
r-

1000

·9

12r--r~~~~--+--+--r-~~--~~

!:i

t
2.65IlV

1

·7

JI

........

+

1
1

FIGURE 25. HA-5111 SETTLING WAVEFORM 500nsID1V.

~

-:

;-

I

1

lmV

""""'i

lOOIlV
1

I

1

I--

:r!:i
VOUT

-11

2SoC

-12

~

RLOAD

\

- -5SoC
-13

I

I

300
400
RLOAD(O)

"
SOO

I

·14

600

VOUT

I
I

\

,

I
-

I
I

I
I

I

I

200

300
400
RLOAD(O)

500

O!!:!
-1.1..
W::aE
~«

I
I

-'- VSUPPLY = ±lSV

\

«en
Za:

~:J
a: 11.

LOAD

FIGURE 28, HA-5101 -VOUT vs RL

3-417

..J

I

I
100

FIGURE 27. HA-5101 +VOUT VS RL

-~
+

1,\ 12SoC

\
~,

10kO

600

HA-5101, HA-5111
Die Characteristics
DIE DIMENSIONS:
70 mils x 70 mils x 19 mils
1790~m x 1780~m x 483~m

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

METALLIZATION:
Type: AI, 1% Cu
Thickness: 16kA ±2kA

SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 54
PROCESS: Bipolar Dielectric Isolation

Metallization Mask Layout
HA-S101

BAL

NC

• • • • • ~iIIlJn!ln

-IN

v+

+IN

OUT

v-

BAL

HA-5111
COMP

BAL
-IN

v+

OUT

+IN

v-

3-418

HA-5102, HA-5104,
HA-5112, HA-5114

HARRIS
SEMICONDUCTOR

Dual and Quad, 8MHz and 60MHz, Low Noise
Operational Amplifiers

November 1996

Features

Description

• Low Noise ••.••..•.•.........•••...... 4.3nVlv'Hz

Low noise and high performance are key words describing HA-5102
and HA-5104, HA-5112, HA-5114. These general purpose amplifiers offer an array of dynamic specifications ranging from a 3VIllS
slew rate and BMHz bandwidth (5102104) to 20V/IlS slew rate and
BOMHz gain-bandwidth-product (HA-5112114). Complementing
these outstanding parameters is a very low noise specification of
4.3nVNHz at 1kHz.

• Bandwidth.................. 8MHz (Compensated)
60MHz (Uncompensated)
• Slew Rate • . . . . . • . . • . . . . . . .. 3V1lls (Compensated)
20VlllS (Uncompensated)

Fabricated using the Harris high frequency DI process, these operational amplifiers also offer excellent input specifications such as a
0.5mV offset voltage and 30nA offset current. Complementing these
specifications are 10BdS open loop gain and BOdS channel separation. Consuming a very modest amount of power (90mWI package
for duals and 150mW/package for quads), HA-5102l04/12114 also
provide 15mA of output current.

• Low Offset Voltage. . . . . . . . . . . . . . . . . . . • . . .. O.5mV
• Available in Duals or Quads

Applications
• Applications

This impressive combination of features make this series of amplifiers ideally suited for designs ranging from audio amplifiers and
active filters to the most demanding signal conditioning and instrumentation circuits.

• High Q, Active Filters
• Audio Amplifiers
• Instrumentation Amplifiers

These operational amplHiers are available in dual or quad form with
industry standard pinouts allowing form immediate interchangeability
with most other dual and quad operational amplifiers

• Integrators
• Signal Generators
• For Further Design Ideas, See Application Note AN554

HA-5102

Dual, Compo

HA-5104

Quad, Compo

HA-5112

Dual, Uncomp.

HA-5114

Quad, Uncomp.

Refer to the 1883 data sheet for military product.

Pinouts

(See Ordering Information on next page)

HA-5102l5112 (PDIP, CERDIP)
TOP VIEW

HA-5102 (METAL CAN)
TOP VIEW

HA-5102/S112 (SOIC)
TOP VIEW

v+

011T~1

011T2

~Nl

+lN1

-

-IN2
4

5 +IN2

v-

HA-5104/5114 (PDIP, CERDIP)
TOP VIEW

HA51 04/5114 (SOIC)
TOP VIEW·

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-419

File Number

2925.2

...J

CCUl

Za:

O!!:!
-u.

t:i:J

a: a.

W:::aE
~CC

HA-5102, HA-5104, HA-5112, HA-5114
Ordering Information
PART NUMBER

TEMP. RANGE (DC)

PACKAGE

PKG.NO

HA2-51 02-2

-5510125

B Pin Metal Can

TB.C

HA2-51 02-5

01075

B Pin Metal Can

TB.C

HA3-51 02-5

010 75

BLd PDIP

EB.3

HA7-51 02-2

-5510125

BLd CERDIP

FB.3A

HA7-51 02-5

01075

BLdCERDIP

FB.3A

HA9P51 02-5

01075

16LdSOlC

M16.3

HA9P51 02-9

-4010 B5

16LdSOlC

M16.3

HAl-51 04-2

-5510125

14LdCERDIP

F14.3

HAl-51 04-5

01075

14LdCERDIP

F14.3

HA3-51 04-5

010 75

14Ld PDIP

E14.3

HA9P51 04-5

010 75

16 Ld SOIC

M16.3

HA9P51 04-9

-40 10 B5

16 Ld SOIC

M16.3

HA3-5112-5

01075

BLd PDIP

EB.3

HA7-5112-2

-5510125

B LdCERDIP

FB.3A

HA9P5112-5

01075

16 Ld SOIC

M16.3

HA9P5112-9

-40 10 B5

16 Ld SOIC

M16.3

HAl-5114-2

-5510125

14LdCERDIP

F14.3

HAl-5114-5

010 75

14LdCERDIP

F14.3

HA3-5114-5

01075

14Ld PDIP

E14.3

HA9P5114-5

01075

16LdSOlC

M16.3

HA9P5114-9

-40 10 B5

16 Ld SOIC

M16.3

3-420

HA-5102, HA-5104, HA-5112, HA-5114
Absolute Maximum Ratings

Thermal Information

Supply Voltage Between V+ and V- Terminals ...........•.. 40V
Differential Input Voltage ................................ 7V
Input Voltage ................................... ±VSUPPLY
Output Short Circuit Duration (Note 3) ................ Indefinite

Thermal Resistance (Typical, Note 2)
9JA (OCIW) 9JC (,CIW)
Metal Can Package. . . . . . . . . . . . . . .
165
80
8 Lead PDIP Package. . . . . . . . . . . . .
92
N/A
135
50
8 Lead CERDIP Package . . . . . . . . . .
112
N/A
SOIC Package (HA-51 02, HA-5112)..
80
30
14 Lead CERDIP Package.... .....
86
N/A
14 Lead PDIP Package. . . . . . . . . . . .
SOIC Package (HA-5104, HA-5114). .
96
N/A
Maximum Junction Temperature (Note 1, Ceramic Package) ... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5102l5104/511215114-2 ................ -55°C to 125°C
HA-5102l5104/511215114-5 ................... OoC to 75°C
HA-5102l5104/511215114-9 .......•......... -400Ct0850C

CAUTION: Stresses above those listed in "Abso/ute Maximum Ratings" may cause permanent damage to the daviee. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operaUona/ sections of this specificaUon is not implied.

NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175°C for
hermetic packages, and below 150°C for plastic packages.
2. 9JA is measured with the component mounted on an evaluation PC board in free air.
3. Anyone amplifier may be shorted to ground indefinitely.

Electrical Specifications

VSUPPLY = ±15V, Unless Otherwise Specified

...J

c(CI)

HA-5102-2, -5
HA-5112-2, -5
PARAMETER

TEMP.
(oC)

MIN

HA-5104-2, -5
HA-5114-2, -s

TYP MAX MIN

TYP MAX

HA-5102-9
HA-SI12-9
MIN

HA-5104-9
HA-5114-9

TYP MAX

MIN

TYP MAX

UNITS

W:iE
~c(

INPUT CHARACTERISTICS
Offset Voltage

25

Offset Voltage Average Drift
Bias Current

25

-

2.0

Full

-

2.5

Full

3

-

130

200

Full
Offset Current

-

0.5

25
Full

Input Resistance

25

Common Mode Range

Full

30

500

2.5

-

0.5

2.0

-

3.0

mV

-

-

3

-

IlVPC

-

130

200

130

200

nA

325

-

-

500

-

500

nA

75

-

30

75

30

75

nA

125

-

-

125

-

125

nA

500

-

-

130

200

-

125

-

-

500

±12

-

-

±12

-

100

250

80

250

80

-

80

95

80

8

±12

mV

2.5

-

30

2.5

-

3.0

75

0.5

3

3

325

-

0.5

'-

-

500

±12

-

-

V

80

250

-

kVN

80

-

kVN

95

dB

1<0

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(VOUT = ±5V, RL = 21<0)
Common Mode Rejection Ratio
(V eM = ±5.0V)

25

100

Full

100

250

Full

86

95

25

-

8

-

100

-

86

95

-

-

8

-

-

-

-

-

Small Signal Bandwidth
HA-51 02151 04 (Av = 1)

-

8

-

MHz

60

-

MHz

Gain Bandwidth Product
HA-511215114 (Av = 10)

25

Channel Separation (Note 4)

25

60

-

60

-

60

-

3-421

60

60
60

-

-

60

Za:
O!!:!
-II.
~:::;
a:D.

dB

HA-5102, HA-5104, HA-5112, HA-5114
Electrical Specifications

VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
HA-5102-2, -5
HA-5112-2, -5

PARAMETER

HA-5104-2, -5
HA-5114-2, -5

TEMP.
fC)

MIN

TYP MAX

Full

±12

±13

MIN

TYP MAX

±12

±13

HA-51 02-9
HA-5112-9

'HA-5104'9
HA-5114-9

MIN

TYP MAX

±12

±13

MIN

TYP MAX

±12

±13

UNITS

OUTPUT CHARACTERISTICS
Output Voltage Swing

Full

±10

±12

-

Full

±10

±15

·

HA·51 02151 04

25

16

47

HA·511215114

25

191

318

Output Resistance

25

·

110

.

(RL = 10kQ)
(RL=2kQ)
Output Current (VOUT = ±5V)

-

-

±10

±12

·

±10

±12

..

±10.

±12

±10

±15

·

±7

±15

·

±7

±15'

16

47

16

47

-

16

47

191

318

-

191

318

·

191

318

110

·

·

110

·

110

·

V

·

mA

'V

Full Power Bandwidth (Note 5)

·

kHz

·

.kHz
Q

STABILITY
Minimum Stable Closed Loop Gain
HA·510215104

Full

1

HA·511215114

Full

10

1

.

10

.

200

-

108

200

ns

48

100

·

48

100

ns

1

.

·

1

·

.

·

10

-

·

10

200

·

108

200

·

108

48

100

-

48

100

·

,· .

VN
VN

TRANSIENT RESPONSE (Note 6)
Rise Time
HA-51 02151 04

25

108

25

·

HA·51 02151 04

25

·

20

35

·

20

35

20

35

·

20

35

%

HA·511215114

25

-

30

40

·

30

40

30

40

·

30

40

%

HA·51 02151 04

25

1

3

·

V/Jls

HA·511215114

25

12

20

HA·51 02151 04

25

-

HA-511215114

25

HA·511215114
Overshoot

Slew Rate

-

1

3

1

3

·

1

3

20

-

12

12

20

·

12

20

4.5

-

·

0.6

·

·

4.5

-

·

4.5

·

·

4.5

-

JlS

·

0.6

·

·

0.6

-

0.6

·

JlS

9

25

-

6.0

9

25

-

·

4.3

6.0

V/JlS

Settling Time (Note 7)

NOISE CHARACTERISTICS (Note 8)
Input Noise Voltage
f= 10Hz

25

f= 1kHz

25

·

4.3

f= 10Hz

25

·

5.1

15

-

5.1

15

f= 1kHz

25

·

0.57

3

-

0.57

3

25

·

870

-

·

870

·

9

25

4.3

6.0

5.1

15

0.57

3

870

·

9

25

nV/'I'HZ

4.3

6.0

nVl'I'HZ

·

5.1

15

pAl'I'HZ

-

0.57

3

pAl'I'HZ

- -

870

·

nVRMS

Input Noise Current

·

Broadband Noise Voltage
f = DC to 30kHz

3-422

·

HA-5102, HA-5104, HA-5112, HA-5114
Electrical Specifications

VSUPPLY

=±15V, Unless Otherwise Specified
HA-Sl02-2, -5
HA-5112-2, -S

TEMP.
(DC)

PARAMETER

MIN

(Continued)

HA-Sl04-2, -5
HA-Sl14-2, -S

TYP MAX

MIN

HA-Sl02-9
HA-Sl12-9

TYP MAX

MIN

TYP MAX

HA-Sl04-9
HA-Sl14-9
MIN

TYP MAX

UNITS

POWER SUPPLY CHARACTERISTICS
Supply Current (All Amps)

25

Power Supply Rejection Ratio
(tNs =±5V)

Full

3.0
86

5.0

5.0

100

86

6.5

3.0

100

80

-

5.0

6.5

mA

80

100

-

dB

5.0

100

NOTES:
4. Channel separation value is referred to the input of the amplifier. Input test conditions are: f

=10kHz; VIN =100mVpEAK; Rs =1kQ.

5. Full power bandwidth is guaranteed by equation: Full power bandwidth = ;Ie; Rate .
" PEAK
6. Refer to Test Circuits section of the data sheet.
7. Settling time is measured to 0.1% of final value for a 1V input step, and Ay = -10 for HA-5112/5114, and a 10V input step, Ay = -1 for
HA-51 02151 04.
8. The limits for these parameters are guaranteed based on lab characterization, and reflect lot-to-Iot variation.

Test Circuits and Waveforms
HA-Sl02, HA-5104
..J
2kD

---'W..,..........--1
2krl

IN

INO_~ I I~

>--41---.....- - _ OUT

O~UT

+5Y
INPUT
OV

200mV

I

INPUT
-5V

J

I

I

Vertical

\

,

OUTPUT
OV

=5V/Div., Horizontal =5llslDiv. (Ay =-1)

I~~

1.

1.1

OV

Vertical

FIGURE 1. LARGE SIGNAL RESPONSE CIRCUIT

,

II
I ~.

+5V

-5V

h

f-'

=40mVlDiv., Horizontal =50nslDiv. (Ay =+1)

FIGURE 2. SMALL SIGNAL RESPONSE CIRCUIT

3-423

etC/)
Za:
OW

-u:::

!ci::::i
0..

a:

W~

~et

HA-5102, HA-5104, HA-5112, HA-5114
Test Circuits and Waveforms

(Continued)
HA-5112, HA-5114

+O.5V
OUTPUT

OV

+5V

1

OUTPUT

,

-o.5V

INPUT

~

~

OV

\

INPUT

-5V

f\

200mV

I

I
J

\

\.

Input = O.SV/Oiv.• Output = SVlDiv., Time = SOnslDiv.

OV

""

Input = 10mV/Oiv., Output = SOmV/Oiv.• TIme = SOnS/Oiv.

+15V

IN

0-----1

>-_---_---0
1.8k.Q

OUT

T

50pF

2000

VIN

~

O-_-"V'.J'V.....- I

2k.Q

NOTES:
9. Av=·1 (HA-S102lS104).Av=-10(HA-S1121S114).
10. Feedback and summing resistors should be 0.1 % matched.
NOTE: Av = +10.

11. Clipping diodes are optional. HPS082-2810 recommended.

FIGURE 3. LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
(Av +10)

=

3-424

FIGURE 4. SETTLING TIME CIRCUIT

HA-5102, HA-5104, HA-5112, HA-5114

Simplified Schematic

rt
-"

J

.....

All"

.....

.....

I:

..)

,
~

~

..
I"

J

.....

I-

'

.....

.......

H r~

Ie

.

...

?~

"
~~ b-t::

t: ..

W

~

~

rJ

~
fj

OUTPUT

..J

ctrn

za:

ow

!i§
a: a..

~

W::E

~ct

.. II"

I)

v+INPUT

-INPUT

Typical Performance Curves
10

!
!zw
a:
a:

Vs

=±15V. TA" 25°C

5.0

1.0

::;)

(,)

w

!II

0.5

0

z

OL-------______
10

~

______________

100

~

lK

10

100
FREQUENCY (Hz)

FREQUENCY (Hz)

FIGURE 5. INPUT NOISE VOLTAGE DENSITY

FIGURE 6. INPUT NOISE CURRENT DENSITY

3-425

lK

HA-5102, HA-5104, HA-5112, HA-5114
Typical Performance Curves

Vs

(Continued)

=±1SV, TA =2SoC, SOIlV/Div., 1S/Div., AV =1000VN
Input Noise =0.232IlVp.p

Vs

=±lSV, TA =2SoC, SOOIlV/Div., 1s/Div., Ay =1000VN
Total Output Noise =2.07SIlVp.P

FIGURE 7. O.lHz TO 10Hz NOISE

FIGURE 8. 0.1 Hz TO 1MHz NOISE

2.0
TA = 25°C

!

1.5

-

~

~
§!

1.0

Iii

~

I!i

0.5

o

o

2

4

6

8

10

12

14

16

18

SUPPLY YOLTAGE (±Y)

FIGURE 9. VIO VB TEMPERATURE

C

.s
I-

zI1J

II:
II:
::;)

0
II1J

rn
IL
IL

0

I-

...ii!:
::;)

4
2 YS=±lSY
0
·2
-4
-6
-8
I\..
·10
~~
·12
·14
·16
·18
·20

FIGURE 10. VIO VB Vs

100
90

~

!

80

'Z

70

~

.... ~

I1J

~

60

G

50

~
ID

i"""!'ooo

!'ooo
~

40

!'ooo

~ 1-00

~ 30

r-

-~

ii!: 20

·22
·24
·26
-60

Ys = ±lSY

10
-40

·20

0

20

40

60

80

100

o

120

~

TEMPERATURE (OC)

-40

~

0

20

40

80

80

TEMPERATURE (oC)

FIGURE 12. IBIAS VB TEMPERATURE

FIGURE 11. 110 vs TEMPERATURE

3·426

~

m

HA-5102, HA-5104, HA-5112, HA-5i14
Typical Performance Curves
S

Vs

(Continued)

=±1SV, lOUT =0

I-I-

c

-

,5. 4 ~hH-;-;-;-;-;-;-;-+-+-+-+-+-+-+-l

!zw

II:
II:

i3

3

f-f-H-I-t-l-l-t-t-t-+-++-+++-+-I

8:

2

I-\.-JW-l.....l~~~~~=t:t~:++-t--+~

1

~-b+-~-+-r+-~-r+-r-l-+-l-+-l

~

:>

UI

-'

~
o

-40

-60

·20

0

20

60

40

80

100

o 0~'--:2~~4"""'~6""""~8-.L-l-:':0""""'-1~2-"--:1~4-"--:1'="6-'-,'""'18

120

SUPPLY VOLTAGE (±V)

TEMPERATURE (OC)

FIGURE 13. Icc vs TEMPERATURE (HA-5104114)

Vs

FIGURE 14. IcC VB Vs (HA-5102l12)

S.S

=±lSV, 1!.vO =tl0V, RL =2kn
~~

.~ ~

~~

....

~

-

~~

J

~

Vo = ±10V, Vs = ±15V,
S.O

0

.... r--

~

CI

w

4.0

~

!:l

~
~

0
0

3.0

-'
~

0

-60

-40

·20

20

0

60

40

80

100

120

TEMPERATURE (oC)

FIGURE 15. AVOL vs TEMPERATURE

290
280
270
260
~ 2S0
:!!. 240
z 230
~ 220
~ 210

13
12
11
:; 10

TA = 2SoC, RL = 2kn
~

z

~

130

UI

II

II

o

2

6

8

10

12

14

!ci:::J
a: a..

~

W:5

~CC

-5SoC

-I"'"

2K

4K

6K

8K 10K

LOAD RESISTANCE (a)

7

1.1"
~
~

16

18

SUPPLY VOLTAGE (tV)

00

'"

'"

~

~
~
2

4

6

8

10

12

SUPPLY VOLTAGE (±V)

FIGURE 17. AvOL vs Vs

FIGURE 18. VOUT VB Vs

3·427

..J

CCCl)

Za:
O!!!
-II.

2S0C

I......

2
1

4

.... 10-""

TA = 2SoC, RL = 2kn

:
~:
~ :
~

190
180
170
160
lS0
140

-

FIGURE 16. AVOL VB LOAD RESISTANCE

~ 200
-

-- --------

Z
W

o

~

12Slc

--- ~

C

14

16

18

HA-5102, HA-5104, HA-5112, HA-5114
Typical Performance Curves

(Continued)

45

0
Vs = ±15V, TA = 25°C

40

~

!

IE

...

-20

"

35

II:
II:

...........
......... I"-- """-

ij

5

30

§

VOUT=-15V

iii

-40

3

-60

~
II:
II:

,
V

VOUT=+15V
25

-80

./
20

o

50

100

150

200

250

300

350

400

'"

I'"

-100
1K

450

...... "'"

~

10K

100K

1M

FREQUENCY (Hz)

TIME (SECONDS)

FIGURE 20. CMRR vs FREQUENCY

FIGURE 19. OUTPUT SHORT CIRCUIT CURRENT vs TIME

0

iii'
~
z
0

fi...
ill
II:

~
......
::::I
VI

...II:

...~

-20

.....

-40

~

-80

~

+PSRR

-60

~
100""""

"'"

~
~

~

.... ~

~PSRR

111111

Lilli
11111

"100
1K.

10K

100K

1M
FREQUENCY (Hz)

FREQUENCY (Hz)

FIGURE 21. PSRR vs FREQUENCY

25
20

T1i\.

iii'

10

GAIN._

~

5

...CJCJ

0

~

120

AvCL = +10, TA = 25°C, RL = 2kO, CL = 5OpF, 1\

15
~

FIGURE 22. HA-5104102 UNITY GAIN FREQUENCY RESPONSE

~100

iii'

-

-

---

-5

~ -10

-15

PHASE....
I III I

-20

1111

-25
100

1K

10K

100K

1m

1M

......
II:

,

0

Sl

45

Ii:

90

iii...

.....

80

~
!:i

40 HA-51 02151 04
GAIN
20

...
~

e.

135 ~

:I:

10M

....

i""'"

~
CJ

100~80 !'-

60

0

~

Vs=±15V, TA=250C,
RL = 2kO, CL =50pF

r..

....

iii'

>-

HA-511215114
GAIN

~

i"-

I 1111 I

~

~:"5102l5104

'Tliu

1K

45

I

I II I

PHASE
100

o

HA-511215114

........ ""'"

100K

90 :

i""o

1111 I
10K

1M

"

10M

135 ~
180 ...
100M

FREQUENCY (Hz)

FREQUENCY (Hz)

FIGURE 23. HA-5112114 FREQUENCY RESPONSE

FIGURE 24. OPEN LOOP GAIN vs FREQUENCY

3-428

~

Ii;
:I:

HA-5102, HA-5104, HA-5112, HA-5114
Typical Performance Curves
60
Vs

(Continued)

1.1

=±lSV, TA =2SoC, RL =2kn

so

/

10

o

10

-----

V

,/

/

RL

/

C 1.0

III
~
..J

'"

::.
a:

~

0.9

",..'

..... .... i"'"

0
~

III

!;( 0.8
a:
~

./

100

=2kn, CL =SOpF, Vs =±lSV

III
..J

en 0.7

lK

0.6
-60

10K

-40

-20

LOAD CAPACITANCE (pF)

0

20

40

60

80

100

120

TEMPERATURE (oC)

FIGURE 26. SLEW RATE vs TEMPERATURE

FIGURE 25. SMALL SIGNAL OVERSHOOT vs CLOAD

1.1

"~

~

c

~
~

1.0

RL

"

=2kn, CL =SOpF, Vs =±15V

~

....I

«C/)

Za:

O!!:!
-II.
~::::i

a:n.

0.9

W:E

~«

0.8

1=
III

~ 0.7
0.6
-60

-40

-20

0

20

40

60

80

100

TEMPERATURE (oC)

FIGURE 27. RISE TIME vs TEMPERATURE

3-429

120

HA-5102, HA-5104, HA-5112, HA-5114

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

98.4 mils x 67.3 mils x 19 mils
2500/-lm x 1710/-lm x 483/-lm

Unbiased
TRANSISTOR COUNT:

METALLIZATION:

93

Type: AI, 1% Cu
Thickness:

PROCESS:

16kA ±2kA

Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02. 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA·51 02

v·

+IN1

·IN1

OUT1

HA-5112

v·

+lN1

·IN1

+IN2

-IN2

OUT2

3·430

OUT1

v+

HA-5102, HA-5104, HA-5112, HA-5114

Die Characteristics
SUBSTRATE POTENTIAL (Powered Up):

DIE DIMENSIONS:
95 mils x 99 mils x 19 mils
2420llm x 2530llm x 4831lm

Unbiased
TRANSISTOR COUNT:

METALLIZATION:

175

Type: AI, 1% Cu
Thickness: 16kA ±2kA

PROCESS:

PASSIVATION:

Bipolar Dielectric Isolation

Type: Nitride (Si3 N4 ) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-51 04
+IN2

v+

+IN1

-IN1

-IN2

....I
C(fI)

Za::

OUT2

OUT1

OUT3

OUT4

-IN3

-IN4

+IN3

v-

+IN4

HA-5114
+IN2

v+

+IN1

-IN2

-IN1

OUT2

OUT1

OUT3

OUT4

-IN3

-IN4

+IN3

v-

3-431

+IN4

O!!!
-u..
!cc::i
a:: a..
W::E
~C(

~

lKJ

HARRIS
SEMICONDUCTOR

HA-5127, HA-5127A
8.5MHz, Ultra-Low Noise
Precision Operational Amplifier

November 1996

Features

Description

• Slew Rate •.•.•••••..••...••.....•.•...•• 10V/IlS

The HA-5127 monolithic operational amplifier features an
unparalleled combination of precision DC and wideband
high speed characteristics. Utilizing the Harris D. I. technology and advanced processing techniques, this unique
design unites low noise (3nV/...JHz) precision instrumentation
performance with high speed (1 OV/~s) wideband capability.

• Unity Gain Bandwidth. . . . . . • . • • • • • • • • • • •• 8.5MHz
• Low Noise .......•.•.•.....•.•... 3nVNHZ at 1kHz
• Low Vas •...•...••••.....•.•.•.•.•.....•.

10~V

• High CMRR ........••..•.•...•..........• 126dB
• High Gain •••...••••.••...••••.•••.... 1800VlmV

Applications
• High Speed Signal Conditioners
• Wide Bandwidth Instrumentation Amplifiers

Using the HA-5127 allows designers to minimize errors while
maximizing speed and bandwidth.

• Low Level Transducer Amplifiers
• Fast, Low Level Voltage Comparators
• Highest Quality Audio Preamplifiers
• PuiseiRF Amplifiers

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

HA3-5127-5

01075

BLdPDIP

HA3-5127A-5

01075

B Ld PDIP

EB.3

-5510125

B LdCERDIP

FB.3A

HA7-5127-2
HA7-5127-5

This amplifier's impressive list of features include low VOS
(10~V). wide unity gain-bandwidth (8.5MHz). high open loop
gain (1800VlmV), and high CMRR (126dB). Additionally, this
flexible device operates over a wide supply range (±5V to
±20V) while consuming only 140mW of power.

This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5127's qualities include instrumentation amplifiers, pulse
amplifiers, audio preamplifiers, and signal conditioning circuits. This device can easily be used as a design enhancement by directly replacing the 725, OP25, OP06, OP07,
OP27 and OP37. For the military grade product, refer to the
HA-5127/883 data sheet.

EB.3

01075

B LdCERDIP

FB.3A

HA7-5127A-2

-5510125

B LdCERDIP

FB.3A

HA7-5127A-5

01075

B LdCERDIP

FB.3A

HA9P5127-5
(H51275)

01075

B LdSOIC

MB.15

Pinout
HA·5127
(PDIP, CERDIP, SOIC)
TOP VIEW

BAL88BAL
-IN

2

+IN

3

V-4

_..

7

v+

6 OUT
.

SNC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-432

File Number

2906.2

HA-5127, HA-5127A
Absolute Maximum Ratings

Thermal Information

Supply Voltage Between V+ and V- Terminals .............. 44V
Differential Input Voltage (Note 3) ........................ 0.7V
Output Current. . . . . . . . . . . . . . . . . .. Full Short Circuit Protection

Thermal Resistance (Typical, Note 2)
BJA (oC/W) BJC (oC/W)
CERDIP Package. .... ...... .... ...
135
50
PDIP Package. .. ..... ..... . .......
92
N/A
SOICPackage .....................
157
N/A
Maximum Junction Temperature (Ceramic Package, Note 1) ... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range . . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5127/27A-2 .......................... -55°C to 125°C
HA5127/27A-5 ............................. OoC to 75°C

CAUTION: Stresses above those lisled in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Maximum power dissipation, including output load must be designed to maintain the maximum junction temperature below 175°C lor
Hermetic packages, and below 150°C lor the plastic packages.
2. BJA is measured with the component mounted on an evaluatIon PC board in Iree air.
3. For differential input voltages greater than O.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.

Electrical Specifications

VSUPPLY = ±15V, CL < 50pF, Rs < 100Q
TEMP.

PARAMETER

TEST CONDITIONS

I

fc) I

I

HA-5127A
MIN

TYP

MAX

I

HA-5127
MIN

TYP

MAX

UNITS

-

30

100

IlV

..J

70

300

IlV

0.4

1.B

IlVPC

Za::
O!!:!
-u.

-

±15

±BO

nA

±35

±150

nA

12

75

nA

30

135

nA

INPUT CHARACTERISTICS
Offset Voltage

25

10

25

Full

30

60

Average Offset Voltage Drift

Full

0.2

0.6

Bias Current

25

±10

±40

Full

±20

±60

25

7

35

Full

15

50

Offset Current

-

Common Mode Range

Full

±10.3

±11.5·

±10.3

±11.5

-

V

Differential Input ReSistance (Note 4)

25

1.5

6

O.B

4

-

MQ

-

O.OB

O.lB

0.09

0.25

IlVp_p

3.5

8.0

3.B

B.O

nV/.JHz
nVl.JHz

Input Noise Voltage (Note 5)

0.lHztol0Hz

25

Input Noise Voltage Density
(Note 6)

f= 10Hz

25

-

f = 100Hz
f= 1000Hz

Input Noise Current Density
(Note 6)

f= 10Hz

-

25

-

I = 100Hz
1= 1000Hz

-

3.1

4.5

3.0

3.B

1'.7

4.0

1.0

2.3

-

0.4

0.6

700

1500

300

BOO

100

120

-

3.3

4.5

3.2

3.B

nV/.JHz

1.7

-

pAl.JHz

1.0

-

pAl.JHz

0.4

0.6

pA/.JHz

-

V/mV

-

VN

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

Common Mode Rejection Ratio

VOUT = ±10V, RL = 2kQ

25

1000

lBOO

-

Full

600

1200

-

Full

114

126

Minimum Stable Gain

25

1

-

Unity-Gain-Bandwidth

25

5

B.5

RL=600Q

25

±10.0

±11.5

-

RL=2kQ

Full

±11.7

±13.B

-

25

111

160

25

-

70

25

16.5

25

VCM=±10V

1
5

V/mV

dB

B.5

MHz

±10.0

±11.5

V

±11.5

±13.5

111

160

-

70

16.5

25

OUTPUT CHARACTERISTICS
Output Voltage Swing

Full Power Bandwidth (Note 7)
Output Resistance

Open Loop

Output Current

-

V

-

kHz
Q

rnA

TRANSIENT RESPONSE (Note B)
Rise Time
Slew Rate

VOUT= 10V

25

I -

25

I

3-433

7

150
10

J

-

-

I

7

10

150

I

ns

I

V/IlS

oCt

(I)

ti::::i
a::Q"
W::i

~oCt

HA-5127, HA-5127A
Electrical Specifications

VSUPPLY

=±15V, CL < 50pF, Rs < 1000

(Continued)
HA-5127

HA-5127A

TEMP,
(DC)

MIN

TYP

MAX

MIN

Settling Time (Note 9)

25

-

1.5

-

Overshoot

25

-

20

40

-

PARAMETER

TEST CONDITIONS

TYP

MAX

1.5
20

UNITS
f!s

40

%

POWER SUPPLY CHARACTERISTICS
Supply Current

25

Power Supply Rejection Ratio

Vs = ±4.5V to ±lBV

-

3.5

-

Full
Full

-

4.0

2

4

-

3.5

16

mA
4.0

mA

51

f!VN

NOTES:
4. This parameter value is based upon design calculations.
5. Refer to Typical Performance Curves.
6. The limits for this parameter are guaranteed based on lab characterization, and reflect lot-to-Iot variation.

7. Full power bandwidth guaranteed based on slew rate measurement using: FPBW =
B. Refer to Test Circuits section of the data sheet.
9. Settling time is specified to 0.1 % of final value for a 10V output step and Av -1.

~Ie: Rate.
1t

PEAK

=

Test Circuits and Waveforms

>_-_--0

IN

OUT

50pF

FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUITS

IN

IN

OUT

OUT

Vertical Scale: Input = 0.5V/Div., Output
Horizontal Scale: 1f!slDiv.

=5V/Div.

Vertical Scale: 100mV/Div.
Horizontal Scale: 200nslDiv.
SMALL SIGNAL RESPONSE

LARGE SIGNAL RESPONSE

NOTES:

5kQ

10. Av=·I.

>-+.....__. . . . .00 VOuT
~50pF

2kn

11. Feedback and summing resistors
should be 0.1% matched.
12. Clipping diodes are optional.
HP50B2·2Bl0 recommended.

2kn
FIGURE 2. SETTLING TIME TEST CIRCUIT

3-434

Schematic Diagram
y+

,

'(

I

t J tCJ ~:u

R16

R2S
OP32

R1S

15/"'1

OP3S ......

OP43

ir
_ L.

ON19
...... OPS6

~

I1Y . .

RIA

~ ...... ONSI

.,.,

O~

J

R17
OP38

......

~

C6 "

~
O~
R24

~

059

"-.J

tl

,r

y_ 4

D60

RS

C4

''''I N13

"C,

}.
.~l . "
-"'"

~17

R7

R3

..... ON29

09

033

l'o ON4

(aP36~~ .

D41

(ION2A

"

4+
034

~

Q~
ONI

J~

""lr

I~

Ir

~54

O~

OP40
ONS......

/"'I

ON2S
L

ON48r

ON!?

.....
RIO

RS

/'1
SUBSTRATE

3

s

~

~

~

r 0N6'

.....
Op-;O

R19

C3

ON4

RS

roO

r*

-y

ON42

t"I

y

.....

~OPI6
"OP26

~~

~

uN24 ....

r
D22

~ONI2
~ ~lj;s

.,

O~ ~! LOp~ O~
Rg

R14

--

Cs

.... ONS2

ON3~

'r

R21

"l0PSS

~ 08

o

R20

R2

I~

OP3~
o

4:

ON49

...Y
..... °NSO

r--

C2

F

lnt~

+INPUT
-INPUT

OPERATIONAL
AMPLIFIERS

R22

~

~R23

~

~Rll

S
~
.....
I\)

10.'0

i;!

HA-5127, HA-5127A
Application Information
v+

NOTE: Tested Offset Adjustment Range is IVOS + 1mVI minimum referred to output. Typical range is ±4mV with RT = 10ka
FIGURE 3. SUGGESTED OFFSET VOLTAGE ADJUSTMENT

~-·II·-~

. .
:

Cs

:

·1

--11--

1

1

C3

Low resistances are preferred for low noise applications as a 1kO resistor has 4nVNHz of thermal noise. Total resistances of greater than 10k0 on

either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will improve stability.
FIGURE 4. SUGGESTED STABILITY CIRCUITS

Typical Performance Curves
30
20

~
w
CI

~

g
Iii

If
...
0

Unless Otherwise Specified: TA = 25°C, VSUPPLY = ±15V

.

10

12

'-

0

10

i.s

~

:>

r-..~

·10
·20

~

-40

-50
·60
-60

,

6 I--

I--

I--

l-

I-

l-

w
II.! 4 I-lz

I-

0

2

-20

0

20

40

60

80

100

~

NOISE VOLTAGE

I--

~

1111111110

~

I NoiSE CURRENT

l-

~
-40

I-

l-

~

g

I" .....

-30

,

1\

8

w

CI

~

6

o '-

120

1

TEMPERATURE (DC)

10

100

1K

1111111
10K

100K

FREQUENCY (Hz)

FIGURE 5. TYPICAL OFFSET VOLTAGE DRIFT vs TEMPERATURE

3-436

FIGURE 6. NOISE CHARACTERISTICS

1M

o

HA-S127, HA-S127A

Typical Performance Curves

Unless Otherwise Specified: TA = 25°C. VSUPPLY = ±lSV

0.14

140

0.12

120

~ 0.1

100

~

,

~

w

i!:l

.....

0.08

a;-

t-

80

::I!

60

a:
a:

~

w 0.06

~~

:s
0

~
~

.....

40

0.04

~

20

!: 0.02

o

o
4

6

8

10

12

14

16

18

10

20

100

lK

6.0

TA = 45°C

8

"-

7

.-

t
i§

6

~

5

~w

5.0

z

4.0

CI

~

~ V' ~

ct

:z::
0
w

3.0

~

2.0

""0

1.0

i!:j

IiiUl

4
3

o

10

20

30

120
100

a;-

:s
a:
a:

If

~ .....

80

+PSRR

80

20

r-r--,

10

-PSRR

a;-

:s
z
'i

~

CI

~~

40

lK

10K

Za:

!ci:::J
a: a.

r

W::::E
~c(

~ ."".-

rr

5 TYPICAL UNITS

1.0

2.0

3.0

5.0

4.0

lOOK

1M

-10

---

100

10M

~-

11

-

11

GAIN

0
PHASE

.....

til
w
w

a:

CI

90

w

e.w

!Il:z::
180
lK

10K

lOOK

1M

10M

I>-

100M

FREQUENCY (Hz)

FREQUENCY (Hz)

FIGURE 11. PSRR vs FREQUENCY

0

-

-30 -40 -

o
100

c(cn

O!!!
-u.

-20

~

20

10

...I

FIGURE 10. OFFSET VOLTAGE WARM UP DRIFT

40

i'oo.

10M

TIME AFTER POWER ON (MINUTES)

30

r--'....."

"

~

0.0
0.0

40

FIGURE 9. OFFSET VOLTAGE DRIFT vs TIME

--

1M

,,--

DAYS

140

lOOK

FIGURE 8. CMRR vs FREQUENCY

AGURE 7. NOISE vs SUPPLY VOLTAGE

9

10K

FREQUENCY (Hz)

SUPPLY VOLTAGE (±V)

~

(Continued)

FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY

3-437

HA-5127, HA-5127A
Typical Performance Curves

---

17
16

~ 14

5

13

~
12
Q
zor(
10

...

8
7

0
0

C

i

~

,

J-

u

°...
0

AvOL -

tc
g

~

1.03

",

1.02

-

w 1.01

I

tc
II:

6

...rn==w

5

2

4

6

1..0'''''

,,""
1.00"

0.97

,,""

0.96
0.95
-60

10

8

0
20 40
60
TEMPERATURE (oC)

-20

-40

LOAD RESISTANCE (knl
FIGURE 13. AVOL AND VOUT VB LOAD RESISTANCE

2.80

C

§.

/

2.78
2.76

i3

2.74

II:
II:

......~

:>

/

2.72

!5

-'

!50

rn

~

\

I\..

12

"

8

25
TEMPERATURE (oC)

~

2.52

0.4

....

L

0.97 _

2.50

0.96

2.48

0.95

~

I

2.44

0.91

2.40

0.90
10
12
14
SUPPLY VOLTAGE (±Vl

16

18

FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE

2.0

I- io""'"

'7

I

,J
o

20

,...-.

'(

0.92

2.42

"

, i/L

0.93

8

1.6

~~

I

BANDWIDTH

0.94

I

6

............

0.8
1.2
FREQUENCY (MHz)

~ 1.02
BANDWIDTH AT OdB
1.01 AoL
i:I 1.00 VOUT = 10V STEP
0.99 RL = 2k.O. CL = 50pF

2.56

4

I'..

FIGURE 16. MAX UNDISTORTED SINEWAVE OUTPUT VB
FREQUENCY

i

2.48

1""0..
.........

o

125

2.58

.... ....

120

,

4

C

......~
:>

16

\

/

§. 2.54

:>

"~
52

2.60

u

20

:..I

FIGURE 15. SUPPLY CURRENT VB TEMPERATURE

II:
II:

~

w

-'

-55

!Z
w

,

'Ii:

/'

2.70

100

RL=2kn
CL=50pF

I\.

24

/

rn

2.68

-'

-'

-'
-'
-'

I-

zw

-'

80

FIGURE 14. NORMALIZED SLEW RATE VB TEMPERATURE

28
2.82 VO=OV

"""~

L..o''

1.0
or(
::Ii
II: 0.99
0
z
w 0.98

I

o

10-

",

...~

9

4

1.05
RL=2kn
1.04 CL=50pF

Q

VOUT -

/

(Continued)

~

.~

11

.

~

..,

.,

15

Unless Otherwise Specified: TA = 25°C, VSUPPLY = ±15V

2

4

SLEW RATE

I

I

6
8
10
12
14
SUPPLY VOLTAGE (±V)

16

18

FIGURE 18. BANDWIDTH AND SLEW RATE VB SUPPLY
VOLTAGE

3-438

20

HA-5127, HA-5127A
Typical Performance Curves

Unless Otherwise Specified: TA = 2SoC, VSUPPLY = ±1SV

20

140
RL= 2kCl
120
100

m~

i"'~

C 60
(!J

10

"

GAIN

o
-45

I'

I'"

~Htl~~
1111
100

lK

"Z

10

-90

5

GAIN

L.oo

-180
10M 100M

'\

!fi
II!

~

i

\

ll!c(
if:

,

\

PHASE

UJ

-135

10K
lOOK
1M
FREQUENCY (Hz)

AV=+l
RL = 2kn
CL= 50pF

o

....

40

0

15

(!J

80

z

mC

~

20

(Continued)

,

\
lK

FIGURE 19_ OPEN LOOP GAIN AND PHASE

10K

lOOK
1M
FREQUENCY (Hz)

10M

o
..45
-90

!fiw
l§

e.t

:E
UJ

-135 w
~
-180 :r
0..

100M

FIGURE 20. CLOSED LOOP GAIN AND PHASE

.J
«(I)

Za:
O!!:!
-II.

ti:J
w:=

a: a..
~«

Horizontal Scale = 1sJDiv.
Vertical Scale = O.002I!V/Div.
AcL =25,OOOVN, EN =O.OBI!Vp_p RTI
FIGURE 21. PEAK-TO-PEAK NOISE VOLTAGE (0.1 Hz TO 10Hz)

3-439

HA-5127, HA-5127A
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

104 mils x 65 mils x 19 mils
2650l1m x 1650l1m x 48311m

Type: Nitride (Si3N4) over Silox (Si02. 5% Phos.)
Silox Thickness: 12kA ±2.kA
Nitride Thickness: 3.5kA ±1.5kA

METALUZATION:
TRANSISTOR COUNT:

Type: AI. 1% Cu
Thickness: 16kA ±2.kA

63

SUBSTRATE POTENTIAL (Powered Up):

PROCESS:
Bipolar Dielectric Isolation

V-

Metallization Mask Layout
HA-S127

BAL

-IN
+IN

v-

3-440

HA-5130, HA-5135
2.5MHz, Precision Operational Amplifiers

November 1996

Features

Description

• Low Offset Voltage .................•..

25~V

(Max)

• Low Offset Voltage Drift .•............... O.4~V,aC
• Low Noise. . • . . . . . . . . • . • • . . . • . . . . • . . . .. 9nVNHZ
• Open Loop Gain .......•••...•.........•.. 140dB
• Unity Gain BandWidth . . . • . . . . . . . . . . . . . . .. 2.5MHz
• All Bipolar Construction

Applications
• Precision Data Acquisition
• Precision Integrators
• Biomedical Amplifiers
• Precision Threshold Detectors

Ordering Information
TEMP.
RANGE('IC)

A Super Bela input stage is combined with laser trimming,
dielectric isolation and matching techniques to produce
25~V (Maximum) input offset voltage and O.4~VflC input offset voltage average drift. Other features enhanced by this
process include 9nV/..JHz (Typ.) Input Noise Voltage, 1nA
Input Bias Current and 140dB Open Loop Gain.
These features coupled with 120dB CMRR and PSRR make
HA-5130/5135 an ideal device for preciSion DC instrumentation
amplifiers. Excellent input characteristics in conjunction with
2.5MHz bandwidth and O.8V1~ slew rate, make this amplifier
extremely useful for precision integrator and biomedical
amplifier designs. These amplifiers are also well suited for
precision data acquisition and for accurate threshold detector
applications.

• High Gain Instrumentation

PART NUMBER

The Harris HA-5130/5135 are precision operational amplifiers
manufactured using a combination of key technological
advancements to provide outstanding input characteristics.

PKG.
NO.

PACKAGE

HA2-5130-5

01075

B Pin Metal Can

TB.C

HA2-5135-5

01075

B Pin Metal Can

TB.C

HA7-5130-2

-5510125

B LdCERDIP

FB.3A

HA7-5130-5

01075

BLdCERDIP

FB.3A

HA7-5135-2

-5510125

B LdCERDIP

EB.3A

HA7-5135-5

01075

B LdCERDIP

EB.3A

HA-5130/5135 offers added features over the industry standard OP-07 in regards to bandwidth and slew rate specifications. For the military grade product, refer to the HA5135/883 data sheet.

Pinouts
HA-513015135
(CERDIP)
TOP VIEW

HA-513015135
(METAL CAN)
TOP VIEW

NOTE: Both BAL 1 pins are connected together inlernally.

CAUTION: These devices are sensHive to electrostatic discharge. Users should foliow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-441

File Number

2907.2

..J

500pF), a small value
resistor (=500) should be connected in series with the output and inside the feedback loop.

Offset Voltage Adjustment (See Figure 3)
1. Resolving low level signals requires minimizing leakage currents caused by external circuitry. Use of quality insulating
materials, thorough cleaning of insulating surfaces and implementation of moisture barriers when required is suggested.
2. Error voltages generated by thermocouples formed between
dissimilar metals in the presence of temperature gradients

A 20kn balance potentiometer is recommended if offset nulling is required. However, other potentiometer values such as
10kn, 50kO and 100kn may be used. The minimum
adjustment range for given values is ±2mV. Vos TC of the
amplifier is optimized at minimal Vos. Tested Offset Adjustment is IVos + 1mVI minimum referred to output.

3-444

HA-5130, HA-5135

Typical Applications

v+

The excellent input and gain characteristics of HA-5130 are
well suited for precision integrator applications. Accurate
integration over seven decades of frequency using HA-5130,
virtually nullifies the need for more expensive chopper-type
amplifiers.

c

OP1l0NAL
CONNECTION

R

FIGURE 3. OFFSET NULLING CONNECTIONS

OUT

Saturation Recovery
Input and output saturation recovery time is negligible in most
applications. However, care should be exercised to avoid
exceeding the absolute maximum ratings of the device.

Differential Input Voltages
Inputs are shunted with back-to-back diodes for overvoltage
'protection. In applications where differential input voltages in
excess of 1V are applied between the inputs, the use of limiting resistors at the inputs is recommended.

OUTPUT
±13V

1- L...II

.~

200J18/D11f.

.1 ,\
200J18/D1II

INPUT

J
II, .I

1\

INPUT
±5mV

FIGURE 4. PRECISION INTEGRATOR
Low Vas coupled with high open loop Gain, high CMRR and
high PSRR make HA-5130 ideally suited for precision detector applications, such as the zero crossing detector shown in
Figure 5.

II'

]

1\

OUT

f

I

J

I

-

RF

I

,------~------,
OPTIONAL FOR OUTPUT
SWING LIMITING

FIGURE 5. ZERO CROSSING DETECTOR
HA-5130

2kn
+15V

·15V

2kn

2kn

NOTE: Av = 100
-15V

FIGURE 6. PRECISION INSTRUMENTATION AMPLIFIER

3-445

...I

etC/)

Za:

O!!!
-I&.
~:::l
a:Q.
w:E
~et

HA-5130, HA-5135
Typical Performance Curves

"-

80

>' 70

.z,

4

"-

(/)c
...:.:.
m!Z

3

~T ~IAS CUR1RENT

Zll:
-~

~
~

50

(/)

tt:

30

°...~

20

1'-0...

iii!: 10

o

-80

o

tic
... !z
Ow

...-

0

TYPICAL
IVOSI

r-

·2

~

~II:
~

·10

ii!
Q

·5

~

I'-

\.........
\
\

~ 8

~

~

6

z 4

~

·10

iii!:

10

_140
III

i'12O

~
w

100

§
zw
...

°

'"

""III

~IS~ CURRENT

1K

0.4

./

10K

°z
~

0.2 iii!:

o

100K

FIGURE 10. INPUT NOISE vs FREQUENCY

45

" '""

.... ~

'100...

20

100

1K

10K

100K

w

II:

90 CI

w

e.w

"-

0
10

iii'

iii
w
PHASE ANGLE_

GAIN' ~

40

1

!Il

j

80

~~

60

·20

0.6

.9:

!z
II!
II:
i3w

FREQUENCY (Hz)

~,

~ 80

...

1.0

-'

0

!:i
~

10

0.8

100

FIGURE 9. HA·5130 OFFSET VOLTAGE STABILITY vs TIME

160

NOISE VOLTAGE

2

o
40

20
30
TIME (DAYS)

2 4 6 810

8

1.2,

~

10

~

oJ

g

·6
-4
·2
0
2
4
6
DIFFERENTIAL INPUT VOLTAGE (V)

1.4

~ 12

"I- _I

Ii:

·8

14

MEASUREMENT AND ENVIRONMENTAL
SYSTEMS ALLOWED 12 HOUR
STABILIZATION PERIOD
0

-

",i"'"

FIGURE 8. INPUT BIAS CURRENT vs DIFFERENTIAL INPUT
VOLTAGE

10

::t:

~

1..,...00'

~

",

-6

-4
160

I I I I I I I I I

IE

-4

...iii!:u

VSUPPLY = ±15V
Te = ±1 oC, Av = 1000

~

·2

(/)

~II:

FIGURE 7. INPUT OFFSET VOLTAGE, INPUT BIAS AND
OFFSET CURRENT vs TEMPERATURE

~
w

0

u

(/)e

-

",.

~

2

120

40
80
TEMPERATURE (DC)

-40

II:
II:

4

~UT OFFSET CURRENT

"."-, ............... .....> / '

w

2

!zW

0

...

~4O

4

~

u

w 60

!:i

6

~w
... 11:

2

(/)

",
L\

1M

135

;!i
...

:2-

~
CI

...
Q

30

9

20

w

U

180

'\.

60
50

§

.......

70

~

40

"

10

·10

1

FREQUENCY (Hz)

FIGURE 11. OPEN LOOP FREQUENCY RESPONSE

I\.

"

~

0

10M

~

10

100

1K
10K
100K
FREQUENCY (Hz)

"

1M

10M

FIGURE 12. CLOSED LOOP FREQUENCY RESPONSE

3·446

HA-5130, HA-5135

Typical Performance Curves

(Continued)
35

Ui 50
W

~
CJ

VSUPPLY = ±15~

I!:

CJ 40

PHASE MARGIN

W

e.z

"

C; 30
0:(

:2 20

W

III
0:(

10

10

~

CJ

W

2.4

15

5

~
z

lK

20

I
(

W

CJ

l:!i

'~"'

10

~

j

:::>

e:

:::>

Ir

15

5

o
1

10

..J

ctcn

1.1

~'H

i!!!j

If ...
U~

I

~12
wQ

0.9

I

0.8

0:(1!:

::sw

I!:'"

I

100

lK

0.7

OW
Zl!:

0.6

10K

o

2

4

8

10

12

14

16

18

20

FIGURE 16. NORMALIZED AC PARAMETERS vs SUPPLY
VOLTAGE

140

60

"~

100

"-~

80

'""-

120

~,

100

iii'
:!!.
I!:
I!:

If

,,~

40

""-"

80
60
40

20

o

6

SUPPLY VOLTAGE (±V)

~

120

u

~ct

"'I!:

140

:;;

W::i

SLEW RATE

!=!w

VSUPPLY = ±5V

FIGURE 15. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD
RESISTANCE

I!:
I!:

!cc:J
a:c..

(l

LOAD RESISTANCE (n)

iii'
:!!.

Za:
O!!:!
-u.

BANDWIDTH

1.0

::sic

VSUPPLY = ±10V

/'

0

1M

III>
I!:",

I

I

III

.........

lOOK

FIGURE 14. OUTPUT VOLTAGE SWING vs FREQUENCY

VSUPPLY = ±15V

i

"""

10K

FREQUENCY (Hz)

30

~

.\.

I

100

10,000

FIGURE 13. SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN vs LOAD CAPACITANCE

CJ

\

VSUPPLY = ±5V

LOAD CAPACITANCE (pF)

25

l\

1

10

0

2.35:::>

1000

~

VSUPPLY = ±10V

'"'
!;
...
!;
~

~
CJ

RL=2kO

I

20

l:!i

~
z
~

~BANDWIDTH

'\

100

:J:

:J:

!.
2.5

~

I!:

o

i!l: 25

2.6 'N

....

W

:J:

I
VSUPPLY = ±20V

rl. 30

60

...

~

1

10

100

lK

10K

"

20

lOOK

FREQUENCY (Hz)

o

1

10

100

lK

10K

FREQUENCY (Hz)

FIGURE 17. CMRR vs FREQUENCY

FIGURE 18. PSRR vs FREQUENCY

3-447

.......

lOOK

HA-5130, HA-5135
Typical Performance Curves

(Continued)

10

±1.4
±1.2

~~

:::~

I

I

5

~;

:..00

~f

0

5~

~

~~

~

O· -5

±1.0

±D.a

I

....

~I'-...."

!::'VS=±20V

~ i'--

±D.B

Vs =±15V
Vs =±10V

1""- Vs = ±5V

±DA
±D.2

-10
0

14

o

16

-60

SETTLING llME We)

-40

0

40

ao

120

160

TEMPERATURE (DC)

FIGURE 20. POWER SUPPLY CURRENT VB TEMPERATURE

FIGURE 19. SETTUNG TIME FOR VARIOUS OUTPUT STEP
VOLTAGES

3-448

HA-5130, HA-5135

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

72 mils x 103 mils x 19 mils
(1840llm x 2620llm x 4831lm)

Type: Nitride (Si3N4) over Silox (S102, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

METALLIZATION:
TRANSISTOR COUNT:

Type: AI, 1% Cu
Thickness: 16kA ±2kA

71

SUBSTRATE POTENTIAL (Powered Up):

PROCESS:

v-

Bipolar Dielectric Isolation

Metallization Mask Layout
HA-5130, HA-5135

-I

«en
Za:

O!!!
-II..

!;;:::::;
a:£l.
W:il

~«

BAL2

-IN

+IN

3-449

v-

HA-5134
November 1996

4MHz, Precision, Quad Operational Amplifier

Features

Description

• Low Offset Voltage ••••.••••••••••.••.• 200j!V (Max)

The HA-5134 is a precision quad operational amplifier that is
pin compatible with the OP·400, LT1014, OP11, RM4156.
and LM148 as well as the HA-4741. Each amplifier features
guaranteed maximum values for offset voltage of 200j!V, off·
set voltage drift of 2j!V{JC, and offset current of 75nA over
the full military temperature range while CMRRlPSRR is
guaranteed greater than 94dB and AVOL is guaranteed
above 500kVN from -55°C to 125°C.

• Low Offset Voltage Drift ...•.. . • • • . •• 2j!vfJc (Max)
• High Channel separ!ltion ••....••....•..•.. 120dB
• Low Noise •.•..•••••.••.....•••••••.•.• 7nV/-JHz
• Unity Gain Bandwidth ...................... 4MHz
• High CMRRlPSRR .... .. .. ... . .. • .... 120dB (Typ)

Applications
• Instrumentation Amplifiers
• State-Variable Filters

Precision performance of the HA·5134 is enhanced by a
noise voltage density of 7nV/..fFfZ at 1kHz, noise current den·
sity of 1pAl..fFfZ at 1kHz and channel separation of 120dB.
Each unity·gain stable quad amplifier is fabricated using the
dielectric isolation process to assure performance in the
most demanding applications.

• Precision Data Acquisition Systems

The HA-5134 is ideal for compact circuits such as instrumentation amplifiers, state-variable filters, and low-level
transducer amplifiers. Other applications include preciSion
data acquisition, precision integrators, and accurate threshold detectors in designs where board space is a limitation.

• Low-Level Transducer Amplifiers

For military grade product, refer to the HA-51341883 data sheet.

• Precision Integrators
• Threshold Detectors

Ordering Information
PART NUMBER

TEMP.
RANGE COC)

PKG.
NO.

PACKAGE

HA1-5134-2

-5510125

14 LdCERDIP

F14.3

HA1-5134-5

01075

14 LdCERDIP

F14.3

Pinout
HA-5134
(CERDIP)
TOP VIEW

CAunON: These devices are sensHive to electrostatic discharge. Users should follow proper IC Handling Procedures.
.Copyright © Harris Corporation 1996

3-450

File Number

2926.2

HA-5134
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 40V
Differential Input Voltage (Note 2) ......................... 6V
Output Current. . . . . . . . . . . . . . . . . .. Full Short Circuit Protection

Thermal Resistance (Typical, Note 1)
9JA (oCIW) 9JC (oCIW)
CERDIP Package . . . . . . . . . . . . . . . .
BO
30
Maximum Junction Temperature (Note 3) ................. 175°C
Maximum Storage Temperature Range .... . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C

Operating Conditions
Temperature Range
HA-5134-2 .............................. -55°C to 125°C
HA-5134-5 ................................. OoC to 75°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those Indicated In the operational sections of this specification Is not Implied.

NOTES:
1. 9JA is measured with the component mounted on an evaluation PC board in Iree air.
2. For differential input voltages greater than 6V, the input current must be limited to 25mA to protect the back-to-back input diodes.
3. Maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175°C.

Electrical Specifications

PARAMETER

VSUPPLY = ±15V, RL = 2kn. CL = 50pF. Rs:S; lOon. Unless Otherwise Specilied

TEST CONDITIONS

TEMP
(DC)

HA-5134-21-5
MIN

TVP

MAX

UNITS

INPUT CHARACTERISTICS

Average Offset Current Drift

Full

-

Common Mode Range

Full

±10

Differential Input Resistance

25

Offset Voltage

25
Full

Average Offset Voltage Drift

Full

Bias Current

25
Full

Offset Current

25
Full

Input Noise Voltage

0.lHztol0Hz

25

Input Noise Voltage Density

1= 10Hz

25

1= 100Hz
1= 1kHz
Input Noise Current Density

1= 10Hz

25

1= 1kHz

200

I1V

....I

350

I1V

0.3

2

I1 flC

O!!!
-IL

±10

±SO

nA

±20

±75

nA

10

50

nA

15

75

nA

0.05

-

nAflC

-

-

30

-

0.2
10

-

-

1= 100Hz

50
75

7.5
7

v

V
Mil

-

3

I1Vp_P
nVNHz
nVNHz
nVNHz
pAlVHz

1.5

-

pA/..JHz

1

-.

pAlVHz

TRANSFER CHARACTERISTICS

25

100

120

Full

94

115

-

Minimum Stable Gain

25

1

-

-

VN

Unity-Gain Bandwidth

25

-

4

-

MHz

Full

12

13.5

-

V

Large Signal Voltage Gain

Common Mode Rejection Ratio

VOUT=±10V

VCM=±10V

25

BOO

1200

Full

500

750

kVN
kVN
dB
dB

OUTPUT CHARACTERISTICS
Output Voltage Swing

3-451

c(rn

Za:

!;(:J
a: a..
W:E
~c(

HA-5134
Electrical Specifications

VSUPPLY = ±15V. RL = 2kO. CL = 50pF. Rs" 1000. Unless Otherwise Specified (Continued)

PARAMETER

TEMP
(oC)

TEST CONDITIONS

HA·5134·2/·5
MIN

TYP

MAX

UNITS

Output Current

25

20

rnA

Full Power Bandwidth (Note 4)

25

12

16

kHz

VOUT=±10V

25

120

136

-

Rise Time

Av = +1. VOUT = 200mV

25

200

400

ns

Slew Rate

Av=+l

25

1.0

-

V/Jls

Overshoot

Av=+l

25

20

40

25

13

Channel Separation

dB

TRANSIENT RESPONSE (Note 5)

Settling Time (Note 6)

0.75

%
JlS

POWER SUPPLY CHARACTERISTICS
Supply Current

All Amps

Full

-

6.5

Power Supply Rejection Ratio

Vs = ±5V to ±18V

25

100

120

dB

Full

94

115

dB

8

rnA

NOTES:
4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW =

2~e: Rate;

5. Refer to Test Circuits section of the data sheet.

V pEAK = 10V.

PEAK

6. Specified to 0.01 % of a 10V step. Av = -1.

Test Circuits and Waveforms
INO---........~

r---~V-I-I-I-O OUT
2kn

50pF

FIGURE 1. SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

Vertical: 50mV/Div.. Horizontal: 200nS/Div.
TA = 250 C. Vs =±15V. AV = +1. RL = 2kO. CL = 50pF

Vertical: 2V/Div., Horizontal: 2JlS/Div.
TA = 25°C, Vs = ±15V. Av = +1. RL = 2kO, CL = 50pF

SMALL SIGNAL RESPONSE

LARGE SIGNAL RESPONSE

3-452

HA-5134
Test Circuits and Waveforms

(Continued)

+15V

5kn

::" L~"""",
--¥.,.,.......,F

r--"""'-.....

>--+......._--0 VOUT
2kn
2kn

NOTES:
7. Av=·1.

TA = 2SoC, Vs = ±lSV, Av = 1000
en = 0.167I1Vp·P
O.OSI1VlDiv.,ls1Div.

8. Feedback and summing resistors should be 0.1 % matched.
9. Clipping diodes are optional. HPSOB2·2Bl0 recommended.

....I

ctUJ
Za:

PEAK-TO-PEAK NOISE O.lHz TO 10Hz

FIGURE 2. SETTLING TIME CIRCUIT

O!!:!
-u.
~:J
a: a.

Schematic Diagram (Each Amplifier)

W:E

~ct

V+

QN21

--+-o OUT

. ; t -.......

Rs

3-453

HA-5134

Application Information
materials, thorough cleaning of insulating surfaces and
implementation of moisture barriers when required is
suggested.

Power Supply Oecoupling
Although not absolutely necessary, it is recommended that
all power supply lines be decoupled with O.D1IlF ceramic
capacitors to. ground. Decoupling capacitors should be
located as near to the amplifier terminals as possible.

Considerations For Prototyping
The .following list of recommendations are suggested for
prototyping.
1. Resolving low level signals requires minimizing leakage
currents caused by external circunry. Use of qualny insulating

2. Error voltages generated by thermocouples formed between
dissimilar metals in the presence of temperature gradients
should be minimized. Isolation of low level Circuitry from heat
generating components is recommended.
3. Shielded cable input leads, guard rings and shield drivers are
recommended for the most critical applications.

Typical Applications

TA = 25°C, Vs =±15V. Av = 1, RL = 10k!l
20mV/Div.,1I1S/ Div.

VOUT = ±10V, RLOAD = son CLOAD = O.OlJ!F, Av = 3, Vs = ±lSV
Top: Input, 2V/Div.• 2011s1Div. Bottom: Output. SV/Div, 20J!S/Div.

FIGURE 3. SMALL SIGNAL TRANSIENT RESPONSE
(CLOAD 1nF)

TRANSIENT RESPONSE OF APPLICATION CIRCUIT #1

=

NOTES:
10.

-Ay = (1 +

~:)(~).

11. 10n - lOOn recommended for short circuit limiting.
12. When driving heavy loads the HA-5002 may
contribute to thermal errors. Proper thermal shielding
is recommended.

FIGURE 4. APPLICATION CIRCUIT #1: INSTRUMENTATION AMPUFIER WITH POWER OUTPUT

3-454

HA-S134

Typical Applications

(Continued)

R

8R

R

4R

Gl

Go

Av

0

0

-1

0

1

-2

1

0

-4

1

-8

1

High AvOL of HA-S134 reduces gain error.
Gain Error == 0.004% at Av = 8.
R

8R

1/4 HA-5134

VREF

FIGURE 5. APPLICATION CIRCUIT #2: PROGRAMMABLE GAIN AMPLIFIER

....I



.VOUT

~ ""'

14.0

..

iii

4.50

etC/)

Za:

OW

ti§

a: a..

~"

I:! 4.80
a:
B 4.70
8:~ 4.60

::Ii

..J

[...0' ~"'"

W::E
~et

'(

4.40
13.9
-60

4.30
-40

·20

0

20

40

60

60

100

~

120

·40

·20

TEMPERATURE (oC)

I
I

36

I
I

34 I--- I-- FALLING EDG;""-

~

8:z:
III

a:
w

~

32
30
28
26
24
22

.........

~~

..... ",.

.......

-

... ~
~

..... ,-

.......

~ RISING EDGE_

100

iii"
:E.-

r--

~

(!l

60

i-"""

80

120

....

60

....

40

GAIN

....

....

P~JEI.

o
45
90

=25°C, VS" ±15V
Ay =1, VOUT =200mV

TA

16

L
1

100

~

0

20
18
14

60

~

20

JIll"""
I"""

40

FIGURE 18. SUPPLY CURRENT VB TEMPERATURE

120

40

20

TEMPERATURE (OC)

FIGURE 17. MAXIMUM OUTPUT VOLTAGE VB TEMPERATURE

38

0

12

1A

I

1~

I
1~

1\

1

10

2

1K

10K

100K

1M

10M

Ii;
ili

i

w

180

100M

FREQUENCY (Hz)

LOAD CAPACITANCE (nF)
FIGURE 19. OVERSHOOT VB CLOAD

100

,

135

ie.

FIGURE 20. OPEN LOOP GAIN AND PHASE VB FREQUENCY

3·457

HA-5137,· HA-5137A
63MHz, Ultra-Low Noise Precision
Operational Amplifier

November 1996

Features

Description

• Slew Rate •••.......••••.•••..••.••••••.. 20V/j.1S

The HA-5137 operational amplifier features an unparalleled
combination of precision DC and wideband high speed
characteristics. Utilizing the Harris Dielectric Isolation
technology and advanced processing techniques, this
unique design unites low noise (3nV/,JFiZ) precision
instrumentation performance with high speed (20V/j.1S)
wideband capability.

• Wide Gain Bandwidth (Av 2!: 5) .••••.•.•••••• 63MHz
• Low Noise .•.•....•..•.•..•..... 3nV/.jHi at 1kHz
• Low VOS •••••.••.••••••.•.••...•.•••••..• 10j.1V
• High CMRR ••.••••.•.•••.•.•.••••..••••. , 126dB
• High Gain •••...••.•••••.••.••••..•••• 1800VlmV

Applications
• High Speed Signal Conditioners
• Wide Bandwidth Instrumentation Amplifiers

Using the HA-5137 allows designers to minimize errors while
maximizing speed and bandwidth in applications requiring
gains greater than five.

• Low Level Transducer Amplifiers
• Fast, Low Level Voltage Comparators
• Highest Quality Audio Preamplifiers
• PulseiRF Amplifiers
• For Further Design Ideas See Application Note 553

Ordering Information
PART NUMBER
(BRAND)
HA3-5137A-5

TEMP.
RANGE (oC)
010 75

PACKAGE

This amplifier's impressive list of features include low Vos
(10j.1V), wide gain bandwidth (63MHz), high open loop gain
(1800VlmV), and high CMRR (126dB). Additionally, this
flexible device operates over a wide supply range (±5V to
±20V) while consuming only 140mW of power.

PKG.
NO.

8 Ld PDIP

E8.3

HA7-5137-2

-55 to 125

8 LdCERDIP

F8.3A

HA7-5137-5

01075

8 LdCERDIP

F8.3A

HA7-5137A-2

-5510125

8LdCERDIP

F8.3A

HA7-5137A-5

01075

8 LdCERDIP

F8.3A

HA9P5137-5
(H51375)

010 75

8 LdSOIC

M8.15

This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5137's qualities include instrumentation amplifiers, pulse
or RF amplifiers, audio preamplifiers, and signal conditioning
circuits.
This device can easily be used as a design enhancement by
directly replacing the 725, OP25, OP06, CP07, OP27 and
OP37 where gains are greater than five. For the military
grade product, refer to the HA-5137/883 data sheet.

Pinout
HA-5137, HA-5137A
(PDIP, CERDIP, SOle)
TOP VIEW

CAUTION: These devices are sensnive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris CorporaHon 1996

3-458

File Number

2908.2

HA-5137, HA-5137A
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 44V
Differential Input Voltage (Note 1) ....................... 0.7V
Output Current. . . . . . . . . . . . . . . . . .. Full Short Circuit Protection

Thermal Resistance (Typical, Note 2)
8JA (oCIW) 8JC (oCIW)
CERDIP Package. . . . . . . . . . . . . . . .
135
50
PDIP Package........... . .... . ..
120
N/A
SOIC Package. ......... . . .... . ..
160
N/A
Maximum Junction Temperature (Hermetic Package) ........ 175°C
Maximum Junction Temperature (Plastic Packages) ....... 150°C
Maximum Storage Temperature Range . . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5137/37A-2. . . . . . . . . . . . . . . . . . . . . . . . .. -55 0 C to 125°C
HA-5137/37A-5 ............................. OoC to 75°C

Die Characteristics
Back Side Potential .................................... VNumber 01 Transistors .................................. 63
CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.
2. 8JA is measured with the component mounted on an evaluation PC board in Iree air.

Electrical Specifications

VSUPPLY = ±15V, CL" 50pF, Rs" loon
HA-5137

PARAMETER

TEST
CONDITIONS

TEMP.
(oC)

MIN

TYP

HA-5137A
MAX

MIN

TYP

MAX

UNITS

Za:
O!!:!
-I&.,

INPUT CHARACTERISTICS
Offset Voltage

25

Average Offset Voltage Drift
Bias Current

Offset Current

30

100

10

Full

70

300

30

Full

0.4

1.8

0.2

25

15

80

10

40

nA

Full

35

150

25

12

75

-

-

25

a:c..

60

I1V

~«

0.6

JlVfDC

20

60

nA

7

35

nA
nA

-

30

135

-

15

50

Common Mode Range

Full

±10.3

±11.5

-

±10.3

±11.5

-

Differential Input Resistance (Note 3)

25

0.8

4

1.5

6

V
Mn

Input Noise Voltage (Note 4)

O.lHz to 10Hz

25

-

0.09

0.25

0.08

0.18

Input Noise Voltage Density
(Note 5)

1= 10Hz

25

-

3.8

8.0

3.5

8.0

nV/./Hz

1= 100Hz

25

-

3.3

4.5

3.1

4.5

nV/./Hz

1= 1000Hz

25

3.8

3.0

3.8

nV/./Hz

25

1.7

4.0

pAl./Hz

I = 100Hz

25

1.0

2.3

pAl./Hz

1= 1000Hz

25

-

3.2

1= 10Hz

-

0.4

0.6

pAl./Hz

Large Signal Vol1age Gain

RL=2kn,
VOUT=±10V

25

700

1500

1000

1800

V/mV

Full

300

800

-

600

1200

Common Mode Rejection Ratio

VCM=±10V

Full

100

120

-

114

126

25

5

-

5

-

-

-

1.7
1.0

-

0.4

0.6

JlVp_p

TRANSFER CHARACTERISTICS

Minimum Stable Gain

3-459

ti:::J
W:E

I1V

Full

Input Noise Current Density
(Note 5)

-I
«II)

VlmV
dB
VN

HA-5137, HA-5137A
Electrical Specifications

VSUPPLY = ±15V, CL s; 50pF, Rs s; 100n (Continued)
HA-5137
TEST
CONDITIONS

PARAMETER
Galn·Bandwldth-Product

TEMP.
(DC)

MIN

TYP

f = 10kHz

25

60

80

f=IMHz

25

RL=600n

25

±10.0

±11.5

RL=2kn

Full

±11.4

25

220

HA-5137A
MAX

MIN

TYP

60

80

MHz

63

MHz

±10.0

±11.5

V

±13.5

±11.7

±13.8

V

320

220

320

kHz

70

n

25

rnA

63

MAX

UNITS

OUTPUT CHARACTERISTICS
Output Voltage Swing

Full Power Bandwidth (Note 6)
Output Resistance

Open Loop

Output Current

70

25
25

16.5

25

16.5

TRANSIENT RESPONSE (Note 7)
Rise Time

25

100

Slew Rate

Vour= ±3V

25

Settling Time

Note 8

25

1.0

25

20

25

3.5

Overshoot

14

20

100
14

20

V/IlS

1.0
40

20

ns

Ils
40

%

POWER SUPPLY CHARACTERISTICS
Supply Current

3.5

Full
Power Supply Rejection Ratio

Vs=±4Vto±18V

4.0

Full

16

51

NOTES:
3. This parameter value is based upon design calculations.
4. Refer to Typical Performance section of the data sheet.
5. The limits for this parameter are based on lab characterization, and reflect lot-to-Iot variation.
6. Full power bandwidth guaranteed based on slew rate measurement using: FPBW =
7. Refer to Test Circuits section of the data sheet.

Slew Rate
2ltV pEAK

8. SeWing time Is specified to 0.1% of final value for a 10Voutput step and Av = -5.

Test Circuits and Waveforms

'" j=t»1-.6-kn-,....-.....

_-O

OUT

~ 50pF
4000

FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT

3-460

2

rnA
4.0

rnA

4

IlVN

HA-5137, HA-5137A
Test Circuits and Waveforms

(Continued)

I
IN
IN

It!!

OUT

I

OUT

Vertical Scale: Input = 1V/Div.
Output = 5V/Div.
Horizontal Scale: 1~S/Div.

••

•-

•

IiiiII

I

Vertical Scale: Input = 20mV/Div.
Output = 100mV/Div.
Horizontal Scale: 100nS/Div.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

+15V

r-----~~--~~--~TO
1000n

OSCILLOSCOPE

2kn

IN o--4_...4Vo",on~_t-_£oo'>~~""- OUT

NOTES:

9. Av=-5.

-15V

10. Feedback and summing resistors should be
0.1 % matched.

2kn

11. Clipping diodes are optional. HP5082-2810
recommended.

FIGURE 2. SETTLING TIME TEST CIRCUIT

3-461

Schematic Diagram
y+
r-"

'-r'
I'

.,...

lR25

r-

:; C7

~

R15

~

~~

I~

lR1 I
E.,..J

]

~

3]

R2

R20

1

R17

I~

I

CJ

R21

°P35"'"

Op43 ,."

"Op44

OP38

~ OP'~1r;-----r---------------;----------i-----i----------,

5

0N4!

_~

..er

OoaI

Op:

Lf

C5
19

ON46

~~
R14

ON3
"1

, ~0D53

ON2

R~

r

Ir

0
N12

[oP36AI

OPV

~rr
0D41

.....

R5

R6

y-

SUBSTRATE

+INPUT

-U

Co)

ON1A

1

"ii"f

ION1

Co)

l.J...l.

0

~

N18--:J""1'

0D34

r

0N7..

~
~

r

0N11

2
-INPUT

...

~

r;

r

R10

R19

0

'"

~

.-R22

R23

N50

OP30

:-a
~
&.
....

IF

~-

~

&.
....

~

,-

1_~_ON10Ul
3

'" I

~

~

R8

/7

~

OP26

0N39

4

.....

IF .'

ON48 ..... ON49 ONS ;;:

......

OP16

R3

ON42

~

~N25

R7

OP17)1-

OP40

OD~
~

ON24tl

~~

r

~

~

--.... ON4

10N2A

~~Oz5a

~

f:I

ON15

I...

OD54 ,

OD~ ~

, r 0D59
,7('

rt.

~

ON52

""

~r-~P27LOp~

~

~ON14

~OD9

C6

c,.>

~-++-+--4

0- N1-i
3 r=it-l-.........

~

_~,

ON51 "1

C4 ~

lr-

~
TaN47lE
~R2A

R
1A

ON!

L-e:

R16

..... c

HA-5137, HA-5137A

Application Information

!--_-oV+

NOTE: Tested Offset Adjustment Range is IVas + 1mVI minimum referred to output. Typical range is ±4mV with Rp = 10kQ.
FIGURE 3. SUGGESTED OFFSET VOLTAGE ADJUSTMENT

Cs

·--11--,
I
I
I

..J


w

"-

-SO
-60
-60

~

10

~ -10
g
Iii
~
0

6

Vee = ±ISV. TA = 25°C

~

FIGURE 6. NOISE CHARACTERISTICS

o

1M

HA-5137, HA-5137A.
Typical Performance Curves
0.14

140

TA=250 C

'D: 0.12
II.

120

0.1

100

:;
w

...

CI

~

0.08

,.
~

~

w 0.06

r"o ....

..... 1'

60

z 0.04

40

l!;

20

0.02

o

.

8

6

10
12
14
16
SUPPLY VOLTAGE (±V)

18

10

20

100

2.60

2.56

C

.§. 2.54

::>

CJ

~
""::>

UI

1M

10M

1.10

2.58

II:
II:

1K
10K
100K
FREQUENCY (Hz)

FIGURE 8. CMRR vs FREQUENCY

FIGURE 7. NOISE vs SUPPLY VOLTAGE

!i:w

~

I"~

o

4

..... 1'

:!!. 80

~

0

-

iii
II:
II:

!1l

!5"-

=±1SV (Continued)

Unless Otherwise Specified: TA';' 2SoC. VSUPPLY

~~

2.52

l...o'

2.50

"".

-

II:'H
~

I-

:g12

III
~~
~

j

2.46

0.90 ~

...~ !c

~

2.48

-

-

~. ~ 1.00 JNl.JH

.... ~ i"'"

~

0.80

i

.,

,.",.

~

,.",.

"'"

~~

l-SLEWRATE

I

I

I

+sL~R1TE

0.70

zo

2.44

~ !. 0.60

2.42
0.50

2.40
4

8

6

10
12
14
16
SUPPLY VOLTAGE (tV)

18

120

1-I-

...

:!!.

II:
II:
UI

"-

'I'

"

"

+PSRR

:!!.

·PSRR

z

:cCI

~

1'"

10

100

1K
10K
100K
FREQUENCY (Hz)

FIGURE 11. PSRR vs FREQUENCY

10
0

·10

G11~

--

100

~~
1M

-

~
PHASE'

·20

I\..

20

o

,

iii" 20

....
....

40

III

30

....

60

20

40

.... 1'

80

15

FIGURE 10. BANDWIDTH AND SLEW RATE vs SUPPLY
VOLTAGE

~

100

iii"

10

SUPPLY VOLTAGE (±V)

FIGURE 9. SUPPLY CURRENT vs SUPPLY VOLTAGE

140

5

20

10M

'I1K

10K
100K
1M·
FREQUENCY (Hz)

':-:-

10M

100M

FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY

3·464

HA-5137, HA-5137A

Typical Performance Curves
17
16
15
~ 14
....
:::>
~ 13
12
C
z
..: 11
10
9
0
0
:c. 8
...J
0
7
~ 6
5
4

Unless Otherwise Specified: TA = 25°C, VSUPPLY = ±15V (Continued)

-

I

TA =2SoC

'-

AVOL

-~

V

,-,

~

YOUT_

J f

1.05
0

1.0

II:

0.99

z

~

o

2

4
6
LOAD RESISTANCE (kQ)

8

0.95
-60

10

2.72

-40

·20

0
20
40
60
TEMPERATURE (oC)

\

~
~ 20

III

~

100

120

g

./

..J

ctrn

Za:

\

O!!:!
-u.

" "-

i

8

./

./

8

./
4

~

w:s
~ct

I\.

.... 12

~

!ci:::J
a: a.

\.

~ 16

./

1"'0.

:.......

.......

",

25
TEMPERATURE (oC)

-55

80

RL = 2K, CL = 5OpF, TA = 25°C

~

2.70

./
./

~

24

./

Ul

2.68

/

FIGURE 14. NORMALIZED SLEW RATE vs TEMPERATURE

./
./
./

2.76

......~

~

28

Yo = OY, Ys = ±15Y

2.78

2.74

~

./

0.97

w 0.96
==

.J
Ul

r-

~

,

L'

w 0.98

I

0

:::>

~
..:

0

C(

:::>

1.02

::I!

2.80

II:
II:

1.03

12

",

w 1.01

'I

2.82

!zUJ

Ii

~

RL = 2K, CL = 50pF, TA = 25°C

C

I--

FIGURE 13. AYOL AND VOUT vs LOAD RESISTANCE

g

1.04

Ii!

I I

...~

°

o

125

FIGURE 15, SUPPLY CURRENT vs TEMPERATURE

-

......1.6
0.8
1.2
FREQUENCY (MHz)

0.4

.....
2

FIGURE 16, VOUT MAX (UNDISTORTED SINEWAVE OUTPUT)
VB FREQUENCY

140
120

iii"
z

1111
1111

i"'o~

100

~

:!!. 80

cc

60
40

0

iii'
w
w

i"o

CI

20

GAIN

i"o~

...

II:

1'00.

0

~~ASE

-45

,
10

100

1K

10K 100K 1M
FREQUENCY (Hz)

10M

-90

e."
w

Ii;

:r
Ul

w
-135 ~

AcL = 25,000VN

%

-180 ...
100M

Horizontal Scale = 1S/Oiv.
Vertical Scale 0.002I1V10iv., EN O.OBI1Vp_p RTI

=

FIGURE 17. OPEN LOOP GAIN AND PHASE vs FREQUENCY

=

FIGURE 18. PEAK-TO-PEAK NOISE VOLTAGE (0.1 Hz TO 10Hz)

3-465

HA-S142, HA-S144
Dual/Quad, 400kHz, Ultra-Low Power
Operational Amplifiers

November 1996

Features

Description

• Low Supply Current .•••••.•.•••..•••.•• 45IlAlAmp

The HA-5142144 ultra-low power operational amplifiers
provide AC and DC performance characteristics similar to or
better than most general purpose amplifiers while only
drawing 1/30 of the supply current of most general purpose
amplifiers. In applications which require low power dissipation and good AC electrical characteristics, this family offers
the industry's best speed/power ratio.

• Wide Supply Voltage Range Single • • • • • .• 3V to 30V
or Dual .............................. ±1.5V to ±15V
• High Slew Rate. . • . . . • • • . . . • • • . . • • . • . • • •. 1.5V1lls
• High Gain •....••••••••...••••••••••••.• 100kVN
• Unity Gain Stable

The HA-5142144 provides accurate signal processing by virtue of
their low input offset voHage (2mV), low input bias current (45nA),
high open loop gain (lOOkVN) and low noise (20nVNHz), for low
power operational amplifiers. These characteristics coupled with
a 1.5V/lls slew rate and a 400kHz bandwidth make the HA5142144 ideal for use in low power instrumentation, audio amplifier and active filler designs. The wide range of supply voKages
(3V to 3OV) also allow these amplifiers to be very useful in low
voKage battery powered equipment. These parts are also tested
and guaranteed at both ±15V and single ended +5V supplies.

• Available in Duals and Quads

Applications
• Portable Instruments
• Meter Amplifiers
• Telephone Headsets
• Microphone Amplifiers

These amplifiers are available with industry standard pinouts
which allow the HA-5142/5144s to be interchangeable with
most other operational amplifiers. For military grade product
refer to the 5142,5144/883 data sheet.

• Instrumentation
• For Further Design Ideas See Application Note 544

Pinouts

(See Ordering Information on Next Page)
HA-5142 (POIP, CEROIP)
HA-5142 (METAL CAN)
TOP VIEW
TOP VIEW

HA-5142 (SOIC)
TOP VIEW

v+

OUT1

NC

Ne
Ne
Ne
v-

HA-5144 (POIP, CERDlP)
TOP VIEW
OUT1

HA-5144 (SOIC)
TOP VIEW

OUT4

-IN1

-IN4

+IN1

+IN4

y+IN3
-IN2

-IN3

CAUTION: These devices are sens~iVe 10 electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Hams Corporation 1996

3-466

File Number

2909.2

HA-5142, HA-5144
Ordering Information
PART NUMBER

TEMP. RANGE (DC)

PACKAGE

PKG. NO.

HA2·5142·2

·55 to 125

8 Pin Metal Can

T8.C

HA2·5142·5

01075

B Pin Metal Can

TB.C

HA3·5142-5

01075

Bld POIP

EB.3

HA7-5142-2

-5510125

Bld CEROIP

FB.3A

HA7-5142-5

01075

Bld CEROIP

FB.3A

HA9P5142-9

-40 to 85

16ld SOIC

M16.3

HA1-5144-2

-55 to 125

14ldCEROIP

F14.3

HA1-5144-5

Oto 75

14ld CEROIP

F14.3

HA3-5144-5

Oto 75

14 Ld POIP

E14.3

HA9P5144-5

01075

16ldSOlC

M16.3

HA9P5144-9

-40 to 85

16ld SOIC

M16.3
..J

Schematic Diagram

<(I)
Zit:
O!!!
-II.

!i::;
It: a.
W:E

~<

t--t-''WI.-o

3-467

OUTPUT

HA-S142, HA-S144
Absolute Maximum Ratings

Thermal Information

Supply Voltage Between V+ and V- Terminals .............. 35V
Differential Input Voltage................................ 7V
Output Current ....................... Short Circuit Protected

Thermal Resistance (Typical, Note 1)
9JA (oc/W) 9JC (oc/w)
75
20
14 Lead CERDIP Package. . . . . . . . .
8 Pin Metal Can Package .. . . . . . . . •
155
67
14 Lead PDIP Package....... .....
100
N/A
120
N/A
8 Lead PDIP Package.... .........
135
50
8 Lead CERDIP Package...... ....
16 LeadSOIC Package (HA-5142) •..
110
N/A
100
NlA
16 Lead SOIC Package (HA-5144) ....
Maximum Junction Temperature (Hermetic Packages) ....... 175°C
Maximum Junction Temperature (Plastic Packages) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5142144-5 .......................•...... OoC to 75°C
HA-5142144-2 ......................... " -55°C to 125°C
HA-5142144-9 ....................... , .... -40°C to 85°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. 9JA is measured

w~h

the component mounted on an evaluation PC board in free air.

Electrical Specifications

Rs = 1000, CL S; 10pF. Unless Otherwise Specified
-2, -5, -9
V+ = +5V, V- = OV

PARAMETER

-2, -5,-9
V+ = +15V, V- = -15V

TEST
CONDITIONS

TEMP.
(oC)

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Note 11

25

-

2

6

-

2

6

mV

Full

-

-

8

8

mV

Full

3

-

3

-

JlVPC

25

-

45

100

45

100

nA

Full

-

125

nA

25

10

nA

20

nA

INPUT CHARACTERISTICS
Offset Voltage

Average Offset Voltage Drift
Bias Current

Note 11

Offset Current

Note 11

125

-

0.3

10
20

Ot03

-

Full
Common Mode Range

Full

Differential Input Resistance

25

0.6
20

-

tl0

0.3

-

V

Input Noise Voltage

f= 1kHz

25

Input Noise Current

f= 1kHz

25

-

0.25

-

Notes 2, 4

25

20

100

20

100

kVN

Full
-2,-5

15

-

15

-

kVN

Full
-9

12

-

12

-

-

kVN

Full
-2, -5

77

105

77

105

-

dB

Full
-9

70

105

70

105

-

dB

0.6

-

20
0.25

MO
nVNHz

-

pANHz

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

Common Mode Rejection Ratio

Note 7

3-468

-

-

HA-S142, HA-S144
Electrical Specifications

Rs = 100n, CL ~ 10pF, Unless Otherwise Specified (Continued)

PARAMETER
Bandwidth

TEST
CONDITIONS

TEMP.
(oC)

Notes 2, 3

25

Notes 2,10

25

-2, -5,-9

-2, -5,-9

V+ = +5V, V- =OV

V+ = +15V, V- = -15V

MIN

MIN

TYP

TYP

MAX

MAX

0.4

-

1.0 to
3.8

0.710
4.2

-

±10

±13

-

V

Full

1.210
3.5

0.9 to
4.0

-

±10

±13

-

V

25

-

240

-

0.4

UNITS
MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing

Full Power Bandwidth

Notes 2, 4, 8

24

kHz

TRANSIENT RESPONSE (Notes 2, 3)
25

-

600

Slew Rate

Note 6

25

0.8

1.5

Settling Time

Note 5'

25

10

Rise Time

-

600

-

ns

-

0.8

1.5

-

V/IlS

-

-

10

IlS
~

c(c/)

POWER SUPPLY CHARACTERISTICS
Supply Current

Power Supply Rejection Ratio

25

Note 9

45

Za:

100

150

IlAiAmp

100

-

-

200

IlAiAmp

80

Full

-

Full
-2, -5

77

105

-

77

105

-

dB

Full
·9

70

105

-

70

105

-

dB

NOTES:
2. RL=50kO.
3. CL = 50pF.
4. Vo = 1.4 to 2.5V for VSUPPLY = +5, OV; Vo = ±10V for VSUPPLY = ±15V.
'5. SetUingTime is specified 10 0.10/0 of final value for a3V output step and AV=·l forVSUPPLY = +5V, OV. Output step = 10V for VSUPPLY = ±15V.
6. Maximum input slew rate = 10V/',1S.
7. VCM = 0 10 3V forVSUPPLY = +5, OV; VCM = ±10V for VSUPPLY = ±15V.
8. Full Power Bandwidth is guaranteed by equation: FPBW = S2 1eVw Rate.
It

PEAK

9. INs = +10VforVSUPPLy=+5, OV; INs = ±5V for VSUPPLY =±15V.
10. For VSUPPLY = +5, OV terminate RL at +2.5V. Typical output current is ±3mA.
11. Vo = l.4V forVSUPPLY = +5V, OV.

3-469

O~

-u...

!i:::i
a:c..
W:E
~c(

HA-5142, HA-5144
Test Circuits and Waveforms

.~

I

11
f~

fVL
_ _ _ _..J_ 50kn

0 OUT

50pF

FIGURE 1. SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

INPUT
INPUT

OUTPUT

OUTPUT

+VSUPPLY

=+15V, -VSUPPLY =-15V

+VSUPPLV = +15V, -VSUPPLY

= -15V

Vertical Scale: Input = 5V/Diy.; Output = 2V/Diy.
Horizontal Scale: 2l!slDiy.

Vertical Scale: Input = 100mV/Div.; Output = 50mV/Div.
Horizontal Scale: 2l!slDiv.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

INPUT

INPUT

OUTPUT

OUTPUT

+VSUPPLY = +5V, -VSUPPLY = OV

+VSUPPLY

=+5V, -VSUPPLY =OV

Vertical Scale: Input = 2V/Diy.; Output = W/Diy.
Horizontal Scale: 5l!slDiv.

Vertical Scale: Input = 100mV/Diy.; Output = 50mV/Diy.
Horizontal Scale: 5l!slDiy.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

3-470

HA-5142, HA-5144
Typical Performance Curves
110
100

Vs = ±2.5V, TA = 25°C, Unless Otherwise Specified
70

u:

I-

I

RL=SOkn

iii'

90

II'

3!::

80

GAIN

0

(1i

70

II ,

20

'"Cl

60

~

~
!i!

~

CL=50pF

)oIJ

80

§

30

Z

20

120

10

140

o

160

~
o

100

1

10

100

1K

10K

100K

I

24

i"""

r-I-

i"""

20

r-. ...

40
30

8

INPUT OFFSET CURRENT

III

20

.... 1"'"

4

10
-60

1M

-40

·20

0

20

40

60

80

100

120

FIGURE 3. INPUT OFFSET CURRENT AND BIAS CURRENT va
TEMPERATURE
1.6

I

I

I I

600

I III

RL=50kn

-.....

PHASE MARGIN

~

!.
I'"

".....

:E

400

0.3

0.1 ::>

1.2

~

~12

:Ell:

~~

0.6

~

.... ~

10

100

o

1000

±1

±2

BANDWIDTH-

f--

FIGURE 4. BANDWIDTH AND PHASE MARGIN
CAPACITANCE
14
RL= SOkQ

II

I

I

II
I III

va LOAD

I I III

1.2

8! ~

1.1

~~
~ !!I

1.0

~

!tee

~ > 0.9

"'12
~Q
Il!
:Ell:

"

VSUPPLY = +5V

~

:;!

'- ~~

±7

±8

±9

±10

100K

I

I

-- ......

SLEW RATE

:..~

,~

t-

r-

...... 1-

BANDWIDTH -

0.8

11:",
OU.
Z

.....

VSUPPLY = +2.SV
10K

±6

RL=SOkQ

i........

11:-1

~

1K

±S

CL=SOpF

VSUPPLY = +10V

o

±4

FIGURE 5. NORMAUZED AC PARAMETERS vs SUPPLY
VOLTAGE

VSUPPLY = +1SV

VSUPPLY = +3V

±3

SUPPLY VOLTAGE (V)

LOAD CAPACITANCE (pF)

Il!

0.7
0.6

1M

-60

-40

·20

·10

0

20

40

60

TEMPERATURE ('IC)

FREQUENCY (Hz)

FIGURE 6. OUTPUT VOLTAGE SWING va FREQUENCY AND
SINGLE SUPPLY VOLTAGE

FIGURE 7. NORMAUZED AC PARAMETERS va
TEMPERATURE

3·471

zo:
O!!:!
-II..
0:0.

0.4

00

...J

.

35

1K
100
FREQUENCY (Hz)

10K

I
I
II/'

10

W

U

!5I>.
!50

~

70

80

a!

60
40

o

::E

100

50

II:

w

""-

IZ

w 40

II:
II:

~

;:)

U

r--.

1K

VSUPPLY = +3V
10K

-H""'"

30

."...,.

I>.
I>.

20

;:)

UJ

10
·60

1M

100K

",,-

VS=+5V"""

I

VI

Vs= +2V

Vs=~3V

,. .-·40

-

I--'"

·20

20

0

.120 f--+-+-+-f+ffl'l'_:::+--+-+-++H-I+--+-+-I~,.HH

iii"

·80

UJ

-60

w

..J

W

Z

~

100kn

~.~~--+-~~~
-=- 1kn

100kn

~
1kn·

-40

·20

60

80

100

120

140

FIGURE 11. POWER SUPPLY CURRENT vs TEMPERATURE
AND SINGLE SUPPLY VOLTAGE

FIGURE 10. PSRR AND CMRR vs FREQUENCY

iif

40

/"

/
..."".

TEMPERATURE (OC)

FREQUENCY (Hz)

i"o ·100

100K

~-

~

r--.
10K

I IIII

VSUPPLY = +5V

I I

I>.

IIIIIII I

10

cC

·PSRR

+~Sffil~~RRI

20

60

I>.

....

II:

:e

~

""-

r--.

::E

U

III

I- Vs =+30V

W

II:
II:

".

FIGURE 9. MAXIMUM OUTPUT VOLTAGE SWING vs LOAD
RESISTANCE AND SINGLE SUPPLY VOLTAGE

II:

....

VSUPPLY = +10V
II
III
I I III

1K

80

....

I III

11111

Ul

~~

100

120

~

I

III IIW

2

140

iii"

III

4

1o
100K

FIGURE 8. INPUT NOISE vs FREQUENCY

100

VSUPPLY = +20V

I

CJ 12
z

~

w

100

.,

16

"ii
~ 14

w

II:
II:

11111

lIlllIl 1L

1

IZ

NOISE CURRENT

-

~
=

(Continued)

Cs=20LOG

•

~

(

V02 )
100V01

V02

+Ht--i-i+++HH

1kn

1K
10K
FREQUENCY (Hz)

FIGURE 12. CHANNEL SEPARATION vs FREQUENCY

3·472

100K

HA-5142, HA-5144

Die Characteristics
DIE DIMENSIONS:

TRANSISTOR COUNT:

104 mils x 55 mils x 19 mils
2650llm x 1400ilm x 4831lm

72
SUBSTRATE POTENTIAL (Powered Up):

METALLIZATION:

v-

Type: AI. 1% Cu
Thickness: 16kA ±2kA

PROCESS:
Bipolar/JFET Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02. 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-S142

v-

-IN1

+IN1

OUT1

...I

<(f)

Za:

O!!:!
-u.

!;;::J
a:c.
w:e
~<

+IN2

-IN2

OUT2

3-473

NC

v+

~HARRlS

\KJ

SEMICONDUCTOR

HA-5147, HA-5147A
120MHz, Ultra-Low Noise Precision
Operational Amplifiers

November 1996

Features

Description

. • Slew Rate ..•.•..•....•...•...••..••..•.. 3SVI!!S
• Wide Gain Bandwidth (Ay >--.--.. .

,- +-

_OUT

2000

~

FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT

3-476

2

mA
4.0

mA

4

",VN

HA-5147, HA-5147A
Test Circuits and Waveforms

(Continued)

-

I

•

. .

I

IN

.,...

IN

I

OUT

OUT

I
I

I

=

Vertical Scale: Input O.5V/Div.
Output = 5VlDiv.
Horizontal Scale: 500ns/Div.

..

I

··1 ·

iiiiill

Vertical Scale: Input = lOmV/Div.
Output = lOOmV/Div.
Horizontal Scale: lOOnS/Div.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

..I

c(C/)

Za:

O!!:!
-II..
~::i

+15V

11:11.

W::E

TO
t---.---.-----o OSCILLOSCOPE

500n

>+-......-VOUT

NOTES:
9. Av=-lO.
10. Feedback and summing resistors should be 0.1 %
matched.

200n

11. Clipping diodes are optional. HP5082-281 0 recommended.

21ill

FIGURE 2. SETTLING TIME TEST CIRCUIT

3-477

~c(

Schematic Diagram

I'

r-'
;";

lR15

.t

"-J

~~
QN.

.'-.J

~~

rIR25

I~P32

1QP37

~
R2

R20

R21

R17

CJ

On5

1""1

Op.q

r"'I

.....

1

.J

I.

QP44

QP3a

QP5

~

1

~

T

Da
Qp:

'~--~--------~------~--~----~
~N19

11

f1

N3

~

QN2

~~Zsa

~ IrD59
QN24

I""

D54 -~~.

..

II
fQp

LQP31~
(Qp36A

f:I 27
1 1QN2A

1~ I..

~:;~'

R4

QN1S

~1

QN29

R7

Qp17)1-

Qp16

....
Qp26

-r - ..4

R5

...r-.. .

a..18!:",,"

~QN7r
~

~N4a .....

r

QNS ....

I

QN49

R19

I'

....

; i'

Ra

R10

••

R22

1_

QN10Ul

J~

3

QN11

2

R23

Qp30

.1:1,

D34 ....
......

~

.....
.... QN50

Cz

4

~

&.
.....

l....I..L

......1QN1

QN39

-rr

"'.....

~

.-

QN25

R6

~

&.
.....
.1:1,

Q~~ ~

D41......
.... Qp40 QN1A 1

.... 4

~
11""""

....

r--

~ IrD60

D
U

'R3

QN42

~

........,

~

~'.

I.......

QN12

tl

r-t..

.,

~QN14

~----------~----~QN~
...
~IrD
~
9
n...

~ Ir D53

~

0)

QN13

~R2A

~,

Q

r

1

~

Cf

R24

C4 .,
~--~~~4-~--~~~

TQN47~

~ .......... QNS1
R14

~

QN46

R
1A

QN,

L:

R16

R11

c

~

HA-5147, HA-5147A

Application Information
v+

NOTE: Tested Offset Adjustment
Range is IVOS +1mVI minimum referred to output. Typical range is ±4mV
with Rp = 10kCl.

FIGURE 3.

SUGGESTED OFFSET VOLTAGE ADJUSTMENT

Cs

.--11--.
I

I

..J

cr:cn
Za:

O!!!
-LL

~::J
a: a.

W::i

~cr:

NOTE: Low resistances are preferred for low noise applications as a 1kQ resistor has 4nVIVHz of thermal noise. Total resistances of greater
than 10kCl on either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will improve stability.
FIGURE 4. SUGGESTED STABILITY CIRCUITS

Typical Performance Curves

TA = 25°C, VSUPPLY = ±15V, Unless Otherwise Specified
6

30

20

>"

'-

10

"-

;u-"" 0
CI
i5 -10
6
> -20

\f

i'~
1-- ...

~

Iii

II!
~

I"""

0-40

~

g

-50

-20

0

20

40

60

80

4

H-tHIIIIIt~~foNIlIIt±tt
~

,
OL....L.ll.IIIIIIJ....~I..UIU.L.....L.u.

100 120

1

TEMPERATURE (oC)

II!

-+tHllIIt--+1tIII1III 3 ~

8 H-I\IIIIIIt-+ttlllIIt-+tt

~

1'",""-

-40

1
1-\1
• -ttHIIIt-+t+fll1ll-ttt

~ 8 HrttllIIIIt-+ttlllIIt-+tt

it -30
-60
-60

10 "

10

100

tHtIf1:ffll:fmlm
fJlJJllf
B
NOISECU~~~~~
2 a:

5IBIII!EffiiHlll::tItll

lK

10K

lOOK

FREQUENCY (Hz)

FIGURE 5. TYPICAL OFFSET VOLTAGE vs TEMPERATURE

FIGURE 6. NOISE CHARACTERISTICS

3-479

ffi

NOISE VOLTAGE

0
1M

HA-5147, HA-5147A
Typical Performance Curves

TA

=25°C, VSUPPLY = ±15V, Unless Otherwise Specified

(Continued)

0.14
TA-250C

>

~
j!

g
III
~

,. ....

-.

0.08

120

-

0.08

....

;;;

Iii

0.1

.;;!.

VS=±15V
I- TA=25oC

160

~ 0.12

~,.

iii

"Iii

I

:!!.

'IIiii

80

0.04

~

"

40
0.02

o

6

4

8

10

12

14

16

18

o

20

10

100

1K

10K

SUPPLY VOLTAGE (±V)

100

I-

80

l-

iii

..,

40

~

~
100" GAIN

Z 60 I-

60

IIC

~4O

~

,

80

~

20

""

I120

"'"

I100

1K

10K

100K

'":-

1M

1K

100

10K

5
.p
~
~

~

15
14
13
12
11

§

9

8

~

7

...

~

10

~

6
5
4

-

TA = 25°C

16

,-,,

"voL

~

--~

-

I""'"

VOUT

1.05

u

Ii:

-

-

1.03

12

1.02

I
i

I

!
2

4

100M

6

8

10

LOAD RESISTANCE (len)

RL = 2K, CL = 50pF, TA = 25°C

~

1.04

!c

~

~

o

10M
=-=

1M

FIGURE 10. OPEN LOOP GAIN AND PHASE VB FREQUENCY

FIGURE 9. PSRR VB FREQUENCY

17

100K

FREQUENCY (Hz)

FREQUENCY (Hz)

€

~

PHASE

o I-

100

10

10M

120

TA~250C

20

I

1M

FIGURE 8. CMRR VB FREQUENCY

FIGURE 7. NOISE VB SUPPLY VOLTAGE

o

100K

FREQUENCY (Hz)

~
~,
~

1.01

./'f'

1.0

""'"

.~.",

0.99

./

0.98

/

0.87
0.86
0.85
-60

/
-40

-20

o

20
40
60
TEMPERATURE (oC)

80

100

120

FIGURE 12. NORMALIZED SLEW RATE VB TEMPERATURE

FIGURE 11. AvoL AND VOUT VI LOAD RESISTANCE

3-480

HA-5147, HA-5147A
Typical Performance Curves

TA

=25°C, VSUPPLY =±15V, Unless Otherwise Specified
28

2.82

_

Vo = OV, Vs = ±15V

./

2.80

~

tzw

a:
a:

::>

0

2.78
2.76

./

2.74
2.72

2.68

,

~

16

I-

::>

12

5
0

8

= 2K, CL = 50pF, TA = 25°C

\

CI

-'

~

" "-

~

I\.

"-

L

2.70

\

w

./

rn

RL

........

"it
II. 20
~

, ./

~

""::>

'"

./

"'./

I .....

24

(Continued)

........

./

-'

-55

........

4

o

125

25
TEMPERATURE (DC)

0.4

0.8

......

1.2

1.6

FREQUENCY (MHz)

FIGURE 13. SUPPLY CURRENT vs TEMPERATURE

-2

FIGURE 14. VOUT MAX (UNDISTORTED SINEWAVE OUTPUT)
vs FREQUENCY

..J

-'--1~--1~-oOUT

·15V
2k.Q

NOTES:
5. Av=-10.
6. Feedback and summing resistors should be 0.1 % matched.
7. Clipping diodes are optional. HP5082-2810 recommended.
FIGURE 2. SETTLING TIME TEST CIRCUIT

AQURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT

I\.

II
OUTPUT B 1--I--+-'--f-+-.:j:--~I10-+--+-+-,"""

OUTPUTB

INPUT A 1---I--+'--f-+-1~"""-+--+-+--I

INPUT A

~

\

\

\.I

OV

Vertical Scale: A = O.SV/Div., B = SV/Div.
Horizontal Scale: SOOnS/Div.

Vertical Scale: A= 10mV/Div., B = 100mV/Div.
Horizontal Scale: 1OOnS/Div.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

3-484

ov

HA-5160, HA-5162
Schematic Diagram

~'n

Rg

R8

1;5,

087

~QN84

Rll

R12

Qp14

Qp16

Rl0

.t;]

R13

J4

J3

Qp12

-'*"QP27

C3

QN71
Rso

r 0 8S

'086

....

....

QP13

QplS

....

....

....

Qp24

Qp25

QP28

Qp17 ....

RSl
.... Qp18

.r
,'054
.)Qp48

"':~'£
J

+IN

QN47

'~QY+
QN46

~

,

055

056

1

~

057

.

C4
QN4

QN3

~17

R16

t

'1
"058

~

Is

C2

l'~~
~ ~060

R18

0103

r~~

QNS

J2

~,

..lb102

~

VOUT
Rl 02

QP3

-IN

~

,

~

'---

061

ti:::J

a: a..

--Ie: Qp8

W~

~ce

~~:

N82

QN78

QN76

QN77
R52
QN32

-....

QN34

QN37

R53

.....

QP79~QP80
Qp81

~

0tI40

QN41

~

Rl

.

QN39

088' II'

QN38
Rz

R3

QN33
QN3S

QN36

~
~ R4

3-485

Za:

-II.

N4S

QN44

...cern
O!!!

R19

LJe: Qp9

Qp7~

1

QN29

QP28
Rl 01

QN2

Qp75

De3

1-0

Qp11

QP73~

Qp49l.:

-

COMP

.....

Qp51
..

lJa

QP23

y-

QN70

Rl00

y+
R14

~
~R5

~ R6

~ R7

Y-

HA-5160, HA-5162

Application Information
Power Supply Oecoupllng
Although not absolutely necessary, it is· recommended that
all power supply lines be decoupled with 0.01 JlF ceramic
capacitors to ground. Decoupling capacitors should be
located as near to the amplifier terminals as possible.
Stability
The phase margin of the HA-5160/5162 will be improved by
connecting a small capacitor (>10pF) between the output

and the inverting input of the device This small capacitor
compensates for the input capacitance of the FET.
Capacitive Loads
When driving large capacitive loads (>100pF), it is suggested that a small resistor (",lOOn) be connected in series
with the output of the device and inside the feedback loop.
Power Supply Minimum
The absolute supply minimum is ±6V and the safe level is ±7V.

Typical Applications
SUGGESTED COMPENSATION FOR UNITY GAIN STABILITY (NOTE)

OUTPUT J-....-+---+-+--.,I--+-+--f~
.~-I--I
.

IN

2~

-'INv---+----I-

--V

2100

1

OUT

Vertical Scale: 2V1Div.
Horizontal Scale: SOOnsJDiv.
FIGURE 3A. INVERTING UNITY GAIN CIRCUIT

FIGURE 3B. INVERTING UNITY GAIN PULSE RESPONSE

FIGURE 3. GAIN OF·1

a

It
lSpF

,.;;.'
. . ·£2.~
.

IN _ _

rV
NOTE:

a

I

OUT

Vertical Scale: 2VIDlv.
Horizontal Scale: 500nsJDiv.

Values were determined experimentally for optimum speed and settling time.

FIGURE 4A. NONINVERTING UNITY GAIN CIRCUIT

FIGURE 4B. NONINVERTING UNITY GAIN PULSE RESPONSE

FIGURE 4. GAIN OF +1

3-486

HA-5160, HA-5162
Typical Performance Curves
+2.50
4K

!z:W

100

+2.0
+1.5

i

110

OFFSET VOLTAGE

3K

+1.0
+0.50

II:
II:

:>

+0.0

u 2K

~
ID

-0.50
BIAS CURRENT

1K

1.0

IJ
-80

0

-40

>
.§.
W

~

!:i

g
ti

Ie
...
0

:!:!.

z

80

"
"~

70

C
W

g
!!i0

20
10
0

I

IL 30

~

"~z
W

~
g'-'

~

0

I

VSUPPLY. ±20V

25

I

I

VSUPPLY

20

5

1K

I

I

I

10K

100

"
"~

i\

W

g
...
...8

100K

~

zW

...0

100K

1M

10M

...

180
100M

1M

10M

0.7
0.6
0.5

"

70

60
50

0.2
0.1

1K
10K
FREQUENCY (Hz)

.'"

~~

!ci:::i

a:: a..

~

.~~ ~

W::!i!

"

&.

20

~<

~

\.

,,~ ~,

10

1.1

!

1I):r

!z:W

::Ell)

So

u

0.3

20

,~

300pF / "

30

Za::
O!!!
-u,.

"I"

~

100pF

40

<(I)

OpF

"'
100

1K

~

10K
100K
1M
FREQUENCY (Hz)

\.
\."l \.
10M

100M

FIGURE S. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS COMPENSATION CAPACITANCES

II:

~z

"

50PF/~ ~

10

II:
0.4 :>
W

...I

,~

0

0.8

100

10K

·10

RGURE 7. OUTPUT VOLTAGE SWING vs FREQUENCY

10

1K

~

:!:!.
z 60
C

FREQUENCY (Hz)

...5a;

~
:z:

FIGURE 6. OPEN LOOP FREQUENCY RESPONSE

100

i\\
±rJ --............ .\

I

135

W
W

I\\.

iii" 90

~

' I

'VSUPPLY =

"e.

110

VSUPPLY = ±10V

15
10

-

=±15V

I

90

FREQUENCY (Hz)

RGURE 5. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs
TEMPERATURE
35

W

~

·10
10

iii"
W
II:

PHASE

30

~

45

"-

40

...z

0

,GAiN

60

2.0
160

120

"
,
'" ........ ""
'",,

........

50

0

1.50

40
80
TEMPERATURE <"C)

~

iii" 90

11:"'
W'"

ti Ii:
ce

0.9 f -

W

o~

III ~

~
a;

~ ~ 0.6
II: w
0 ...
Z
0.5

0.7

~ IIIIr...

'"

BANDWIDTH

... 0

"'~
~~
~

II!

0.4
-80

0
100K

FIGURE 9. INPUT NOISE VOLTAGE AND NOISE CURRENT vs
FREQUENCY

BA~j.DTHI

~ 30.8

W

6
z

)k- ~SLEWRATE

1.0

o

40
60
TEMPERATURE (oC)

120

160

FIGURE 10. NORMALIZED AC PARAMETERS vs TEMPERATURE

3·487

HA-5160, HA-5162
Typical Performance Curves

(Continued)

14

+10

NEGAllVE SWING / /

Iii
w

CI

~

~
~

2

o

V

~

0

g
!:i

~ POSITIVE SWING

~

;tI'"

200

/

w

~

~

-5

0

400

o

LOAD RESISTANCE (n)

-"

100

o
~
a:

80

z

Q

t;
w
iil
a:

60

w 40
c
0

::I!

z

0

::I!
::I!

20

:~

~,

100

~

200

300

'500

400

600

SETTLING TIME (ns)

FIGURE 11. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE

iD
:E-

"
10mV

·10

1K

800

600

V

10mV

~ +5

Go

,

FIGURE 12. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES

~~
~

0

u

OL-__

o
1

10

100

1K

10K

100K

1

1M

~

____

10

FREQUENCY (Hz)

~

____L-__

100

8.5

1---+----ioI'IE:---:bo-::...+--~...tL--_l

8.0

I--~I_:;,....M'-'I__'"

~

~
v.

7.5 1---I1'#---+---+---+---+----l

7.0 L-_-'-_ _-'-_ _-'-_ _'--_-'-_ _....J

·80

____

10K

~

__

100K

~

1M

FIGURE 14. POWER SUPPLY REJECTION RATIO VB FREQUENCY

8.8 ,---.....,r----,---,.---,--=__- - . ,

I8

~

FREQUENCY (Hz)

FIGURE 13. COMMON MODE REJEC110N RATIO VB FREQUENCY

I

1K

·40

0

40

80

120

160

TEMPERATURE ("C)

FIGURE 15. POWER SUPPLY CURRENT vs TEMPERATURE

3·488

HA-5170
8MHz, Precision, JFET Input
Operational Amplifier

November 1996

Features

Description

• Low Offset Voltage ••••.••.•.••••.••••..•..• 100IlV

The Harris HA-5170 is a precision, JFET input, operational
amplifier which features low noise, low offset voltage and low
offset voltage drift. Constructed using FET/Bipolar
technology, the Harris Dielectric Isolation (01) process, and
laser trimming this amplifier offers low input bias and offset
currents. This operational amplifier design also completely
eliminates the troublesome errors due to warm-up drift.

• Low Offset Voltage Drift ••..........••..... 21lVJOC
• Low Noise •••.•••••••.••..••.•..••••.. 10nV/jHi
• High Open Loop Gain •.••..••.•.•••••...• 600kVN
• Wide Bandwidth •••.••..•..•..•..•..•....•• 8MHz
• Unity Gain Stable

Complementing these excellent input characteristics are
dynamic performance characteristics never before available
from precision operational amplifiers. An 8V/lls slew rate and
8M Hz bandwidth allow the deSigner to extend precision
instrumentation applications in both speed and bandwidth.
These characteristics make the HA-5170 well suited for
precision integrator amplifier designs.

Applications
• High Gain Instrumentation Amplifiers
• Precision Data Acquisition
• Precision Integrators
• Precision Threshold Detectors
• For Further Design Ideas, Refer to Application Note 540

Ordering Information
PART NUMBER
HA2-5170-2

TEMP.
RANGEfc)

PACKAGE

PKG.
NO.

-55 to 125

B Pin Metal Can

TB.C

HA2-5170-5

Oto 75

B Pin Metal Can

TB.C

HA7-5170-2

-55 to 125

B LdCERDIP

FB.3A

HA7-5170-5

Ot075

BLdCERDIP

FB.3A

The superior input characteristics also make the HA-5170
ideally suited for transducer signal amplifiers, precision
voltage followers and preciSion data acquisition systems. For
application assistance, please refer to Application Note
AN540 addressing specifically this device.
Military version (-8) product and data sheets available upon
request.

Pinouts
HA-5170
(CERDIP)

HA·5170
(METAL CAN)

TOP VIEW

TOP VIEW

Ne

y-

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-489

File Number

2912.2

..J

cccn
Za:

O!!:!
-II..

!ct:J
a: a..
W:::!E

~cc

HA-5170
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 44V
Differential Input Voltage .••............................ 30V
Output Short Circuit Duration ..............•........ Indefinite

Thermal Resistance (Typical. Note 1)
9JA (oCIW) 9JC (oCIW)
135
50
CERDIP Package. . . . . . . . . . . . . . . .
Metal Can Package. . . . . . . . . . . . . . .
155
67
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .. 175°C
Maximum Storage Temperature Range ... . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os). . . . . . . . . . .. 300°C

Operating Conditions
Temperature Range
HA-5170-2 ............................ " -55°C to 125°C
HA-5170-5 ................................. OoC to 75°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±15V. Unless Otherwise Specified
HA-5170-2
-5SoC to 12SoC

PARAMETER

TEST
CONDITIONS

TEMP.
('IC)

MIN

HA-S170-5
OOC to 7SoC

TYP

MAX

0.1

0.3

MIN

TYP

MAX

UNITS

0.1

0.3

mV

0.5

mV

2

5

IlVPC

INPUT CHARACTERISTICS
Offset Voltage

-

25
Full

Average Offset Voltage Drift (Note 3)

Full

Bias Current

25
Full

Bias Current Average Drift

Full

Offset Current

25
Full

Offset Current Average Drift (Note 3)

Full

Common Mode Range

Full

2

5

-

20

100

-

20

100

pA

3

30

-

0.1

2

nA

3

-

3

-

pAf'c

3

30

3

60

pA

-

5

-

-

0.1

nA

0.3

1

0.3

1

pAf'C

0.5

Full

-12

-

Differential Input Capacitance

25

80

100

Differential Input Resistance (Note 3)

25

Input Capacitance (Single Ended)

25

Input Noise Voltage (Note 3)

±10

+15.1

±10

+15.1

V

-12
80

V
100

pF

12

-

-

12

-

25

0.5

5

-

0.5

5

IlVp_p

25

20

150

20

150

nV/JHz

f = 100Hz

25

12

50

12

50

nV/JHz

f = 1000Hz

25

10

25

10

25

nV/JHz

0.1Hz t010Hz

Input Noise Voltage Density (Note 3) f= 10Hz

Input Noise Current Density (Note 3) f = 10Hz

-

-

25

f= 100Hz

25

f= 1000Hz

25

1 x 1010 6 x 1010

1 x 1010 6 x 1010

3-490

0.01

-

0.01

0.1

0.05

0.05

-

Q

pF

pAlJHz

0.01

-

pAlJHz

0.01

0.1

pAlJHz

HA-S170
Electrical Specifications

VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
HA-5170-2
-55°C to 125°C
TEST
CONDITIONS

HA-5170-5
OOC to 75°C

TEMP.
fC)

MIN

TYP

MAX

MIN

TYP

25

300

600

300

600

kVN

Full

200

-

250

-

kVN

Full

85

-

90

100

dB

25

1

-

1

-

VN

AVCL=+l

25

4

8

-

4

8

-

MHz

Output Voltage Swing

RL=2kO

25

±10

±12

±10

±12

RL=2kO

25

80

120

80

120

Output Current (Note 5)

VOUT=±10V

25

±10

±15

±10

±15

-

V

Full Power Bandwidth (Note 4)

-

Output Resistance (Note 3)

Open Loop, 100Hz

25

-

45

100

45

100

PARAMETER

MAX

UNITS

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

Common Mode Rejection Ratio

Vour=±10V,
RL=2kO

l1VCM=±10V

Minimum Stable Gain
Closed Loop Bandwidth

100

OUTPUT CHARACTERISTICS

kHz
mA

a

..J

cccn

Za:

O!!!
-u...

~:::i
a: a..

TRANSIENT RESPONSE
Rise Time

Note 2

25

-

45

100

-

45

100

ns

Slew Rate

Note 2

25

5

8

-

5

8

-

VIi'S

25

-

1

5

1

5

i'S

Supply Current

Full

-

1.9

2.5

-

1.9

2.5

mA

Power Supply Rejection Ratio (Note 8)

Full

85

105

-

90

105

-

dB

Settling Time (Notes 3, 7)
POWER SUPPLY CHARACTERISTICS

NOTES:
2. See "Test Circuits and Waveforms" section.
3. Parameter is not 100% tested. 90% of all units meet or exceed these specifications.
4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW =
5. Isc tums on at =' 23mA.

;I~W Rate
"

6. Settling time is measured to 0.1 % of final value for a 10V output step and AV = -1.
7. V+ = +15V, V- = -10V to -20V and V- = -15V, V+ = +lOVto +20V.

3-491

PEAK

W:!i

~CC

HA-5170

Test Circuits and Waveforms

6

~--O

1

OUT

OOUT

~50PF

5

vTested Offset Adjustment Range is IVas + 1mVI minimum referred to
output. Typical range is ±5mV with RT = lkO and ±15mV with
RT= 100kO.
FIGURE 1.

Vos ADJUSTMENT

FIGURE 2_ LARGE AND SMALL SIGNAL RESPONSE CIRCUIT

Vertical Scale: 5V/Div.
Horizontal Scale: llJ.S/Div.

Vertical Scale: 10mVlDiv.
Horizontal Scale: 100nS/Div.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

+15V

1000
6

3.5kO

2.5MO
;: 1OHz FILTER

Av =25,000
Vertical Scale: 200nV/Div. (Noise Referred to Input)
5mV/Div. at Output, AVCL = 25,000
Horizontal Scale: 1S/Div.
FIGURE 3.

LOW FREQUENCY NOISE TEST CIRCUIT

HA-S170 LOW FREQUENCY NOISE (0.1 Hz TO 10Hz)

3-492

Schematic Diagram

'b~'

;

023

d~

R12

...... 019

"I

L
o l('"

r--

I

R14 •

J3

01 ~

~

042

0--

K

045

2~

R6

.
•

..... 022

,....

,....

·INPUT

R16

Va,

otl
..
otl
29.,

,. . . ~e:-

1:02Q
I

R22

021

~

,.... 09

....., 034

C2

'"

~01
I.

Q

5
R15

R21

R4

SAL

~

.... 017

r
Rl

~

R7

0111j..o

.....

-

013

06

"'au

SAL

0 UT

R24

041.:::t---

,.., 049

01~

~

J

R3

011

R19

0.

~

~l

O~

ji?I 025
r

I

,....

",,026

......

.J

04
I.,

051

r-

Ra

C3

3Dt'l

040

.... OS

024

~ ~Ir

R23

I":

033

04

'"

j

R17

,....

L3.

I....J

t-o

02

R20

r
016

,>:

avWea
~

J.

036

~03

035

~

R5

03

• ".. n

~

R11

:;

..... 015 .....

J4

".~' . _

RID

......

014

047

~5

046

......

043

NC

e:~

R9

Q

~I

~

",

048

v

05D~
r.....

052

R2

y.

OPERATIONAL
AMPLIFIERS

HA-5170

,

Typical Performance Curves

So

0.1

!zw

OA

>-

0.2 ~

CI

~

0.1

Iii

·0.1

§l

~

~

z

15

5
Q.

1

10

100

lK

10K

-

0

=SIE:

~

-

..,.,- V

./

./'

·0.5
-0.6

0.001
lOOK

-

V"
~ 1000..

-, -

·0.2
-0.3
·0.4

~

1

....

0.3

!.
w

a:
a:
=>
()
w
0.01

0.6
0.5

-ss

·25

0

25

50

75

100

125

TEMPERATURE (DC)

FREQUENCY (Hz)

FIGURE 4. INPUT NOISE vs FREQUENCY

FIGURE 5. OFFSET VOLTAGE DRIFT vs TEMPERATURE OF
REPRESENTATIVE UNITS

10
10r-------~r-----~~~------_r----_i

"
1 0.1

'"

~

ji

./

0.01
.10 1--______.......,1--____-"'......______'--+____-1

o

0.5

0.001
·50

1.5
SETTLING TIME (lUI)

·25

o

25

50

75

100

125

TEMPERATURE (DC)

FIGURE 6. SETTUNG TIME FOR VARIOUS OUTPUT STEP
VOLTAGES

FIGURE 7. BIAS CURRENT vs TEMPERATURE

1.2

3 r---------~----------r---------~

,..---...,.----r---....--...,.---,,..---....--..,

lu

II!~ 1.1 r---.3j,~--+---+---+----'I---+---I

(I)'"

a:!(

~K!

~ ~ 1.0 I--+--+-.;Ijo~:-t---l--t---\

~i
~~
... !'! 0.9 r---+---t---r--+--+.:::a.~~;::::t

I
±5

±10

±15

±20

SUPPLY VOLTAGE (V)

0.8 '--__--'-____-'-__....1....__--'-____' - -__....1...._-'
-55
·25
0
25
50
75
100
125
TEMPERATURE (DC)

FIGURE 8. POWER SUPPLY CURRENTvs SUPPLY VOLTAGE

3·494

FIGURE 9. NORMAUZED AC PARAMETERS VB TEMPERATURE

HA-5170
Typical Performance Curves

(Continued)

120
100

~

80

i:i

60

a::
a::

....

I'
...... 1"-

"

20

10

100

1K
10K
FREQUENCY (Hz)

100K

1M

FIGURE 10. POWER SUPPLY REJECTION RATIO vs FREQUENCY

~
w

IIIIIII

1> 28

40

Ii!c

3!1

30

::E

w
~
:z:

20

e.

A.

.

50

a::
Cl
w

PHASE MARGIN

"

10

~

16

i\

!5

8

~

o

4

BANDWIDTH

..

I 1111 II

o

10

~

~

~+t

0.8

::Etc

~!!I

if ...
(,)~

"'0

eFwe
~w
...
a::
ca::
::Elf
a:: w
~a::

I

~CI)
w

~

I

!:i

15

!:;

10

§

5

~

0.4
/SLEWRATE
0.2

±4

r:r:::1I..
W::E

1\

~«
~

I

±6 ±8 ±10 ±12 ±14 ±16 ±18 ±20
SUPPLY VOLTAGE (V)

FIGURE 14. NORMAUZED AC PARAMETERS vs SUPPLY
VOLTAGE

1M

III I I

30

20

±2

"\

10K
100K
FREQUENCY (Hz)

35

Cl 25

0

±~J~ I~~PPLI~S

FIGURE 13. OUTPUT VOLTAGE SWING vs FREQUENCY AND
SUPPLY VOLTAGE

BANDWIDTH

0.6

«en

O!!:!
-II..
~;:j

115~ !~PPLI~S

~

1K

~
a::..,

I

o

o

100
1000
10000
LOAD CAPACITANCE (pF)

TA= 25°C

1.0

..J

Zr:r:::

~

AGURE 12. SMALL SIGNAL BANDWIDTH AND PHASE MARGIN
vsLOADCAPACITANCE

CI»

RL=2kQ
CL= 50pF

IIIIIII

Cl

'-

1M

I ±~ ~~ I~~PPLI~S

.tCl 24
~20
w

i"'oo"

100K

AGURE 11. COMMON MODE REJECTION RATIO vs FREQUENCY

RL=2kQ
60

1K
10K
FREQUENCY (Hz)

100

10

VS=±15V

",.

1/"
f"

J
o ~ ""'"
100

"1JJ
IIlsJJ
II I I

1K
10K
LOAD RESISTANCE (0)

100K

FIGURE 15. MA)!:IMUM OUTPUT VOLTAGE SWING VB LOAD
RESISTANCE

3-495

HA-5170

Typical Performance Curves

(Continued)

110

RL= 2kn
CL= SOpF

100

iD

~

iii:

i3
li"'

80
60

z

"'a.

0

80

45~

~
<:I

60

II:

10

40

"'
13S:l!

9"'

20

a.

~

0
100

1K

10K

100K

1M

C

U

--

0
10

100M

-100

1K

10K

100K

1M

10M

100M

FREQUENCY (Hz)

FREQUENCY (Hz)

FIGURE 16. OPEN LOOP FREQUENCY RESPONSE

,

-

 5. Gains < 5 are covered
below. Feedback resistors should be of carbon composition
located as near to the input terminals as possible.

When driving heavy capacitive loads (>100pF) a small resistor (1 Oon) should be connected in series with the output and
inside the feedback loop.

Wiring Considerations

Video pulse circuits should be built on a ground plane. Minimum point to point connections directly to the amplifier
terminals should be used. When ground planes cannot be
used, good single point grounding techniques should be
applied.

3-501

HA-5190, HA-5195

Typical Applications
IN
l1pF

(Also see Application Notes AN525 and AN526)
IN

> ...._~-oOUT

(NOTE)

o-.JVVIr---1"

2000

:t

A

"

OUTPUT

OUTPUT

IA

u.L .....

V'
INPUT

---

111

111

INPUT

J

Vertical Scale: 2V/Dlv.
Horizontal Scale: 100nS/Div.
NOTE:

>-1-.....--0 OUT

2000

Vertical Scale: 2V1Div.
Horizontal Scale: l00nS/Div

Values were determined experimentally for optimum speed and settling time. RF and C1 should be optimized for each
particular application to ensure best overall frequency response.
FIGURE 3. SUGGESTED COMPENSATION FOR NONINVERTING UNITY GAIN AMPLIFIER

1kll

OUTPUT

1kll

IN

-J,f.'/r.....-C...

-

\
,,\.

I

II

OUT

INPUT

Vertical Scale: 2V/Div.
Horizontal Scale: 50nslDiv.
FIGURE 4. SUGGESTED COMPENSATION FOR INVERTING UNITY GAIN AMPLIFIER

IN

2000

'L:::rl""

1200

750

FIGURE 5. VIDEO PULSE AMPLIFIERI750 COAXIAL DRIVER

FIGURE 6. VIDEO PULSE AMPLIFIER COAXIAL LINE DRIVER

3-502

HA-5190, HA-5195

Typical Performance Curves
5

Vs = ±lSV, TA = 25°C, Unless Otherwise Specified

:: ~
"-"""~

I

I

1.6

BIAS CURRENT -

0.8

OFFSETVOL~~

0.4

-80

-40

0

:;-

iii 80 ~
~
z

W

W

~

~

40

9

20

.§.

1.2

"'-i'...

o

100

2.0

40

80

~

g
Iii
Ie
LL
0

~

60

zW

...0

GAIN

.....
PHASE

i\

0

225
lK

10K

TEMPERATURE (DC)

CI

14

~

~

W

~

:.J

r""'1-

1/)0

....

Ir~

~!c
:Ell!

1.1
1.0

~;:)
~;!
a:>i 0.9

~~

10

§l

c(w

:e

8

~
0

10M

100M

1.2
()

12

!:i

1M

FIGURE 8. OPEN LOOP FREQUENCY RESPONSE

18
16

lOOK

FREQUENCY (Hz)

FIGURE 7. INPUT OFFSET VOLTAGE AND BIAS CURRENT va
TEMPERATURE

...

180

-20

0
160

120

~

~

...0~

o

.....

lr
Irlr

---...

...I

........

SLEW RATE

/BANDWID~~

,

etC/)
Za:
O!!!
-II..

-

~:::i
a: 11.

W:E

~

/

0.8

~et

\

OW

zlfj 0.7

6

4
lK

Ir

l
10K

lOOK

1M

10M

100M

-80

FREQUENCY (Hz)

1.2

~

II!g

W

BANDW~

1.0

~

100

100

W

z~

10

100

200

z

...ii!i
~

250

LOADCAPACrrANCE(~

FIGURE 11. NORMALIZED AC PARAMETERS va LOAD
CAPACITANCE

!!!
0

...

!:i
...
ii!i

0.8
10

s:
W

~

l!ig
z ...

.!!:

;:)
()

W

0.9

,
Ir
Ir

~

SLEWRA~

at::

~a

va

~

II!~ 1.1
Ir ...
~!

~§

160

1000

1000

a'-

~~

120

80

FIGURE 10. NORMALIZED AC PARAMETERS
TEMPERATURE

~8-

~()

40

TEMPERATURE (DC)

FIGURE 9. OUTPUT VOLTAGE SWING va FREQUENCY

Ww

o

FREQUENCY (Hz)

FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT va
FREQUENCY

3-503

HA-5190. HA-5195
Typical Performance Curves

Vs= ±1SV, TA = 2SoC, Unless Otherwise Specified (Continued)

~ 12

~

~

5

~

r

10

8
6

I
I

4
2

5m~

2.5

~

i

I

0

;.J

_

5m';'.

-5

200

400

600

800

1K

UK

o

10

20

30

;00...... 0.5m~ ~

40

IeII:

...... 1-

i'..

~,

80
60

60

70

80

90

..

I I III

-

POSITIVE
SUPPLY

r--- ~.

NEGATIVE ......
SUPPLY

4Q

z

~
20

o

100

1K

10K

100K

1M

1K

FREQUENCY (Hz)

FIGURE 15. COMMON MODE REJECTION RATIO vs
FREQUENCY

10K
FREQUENCY (Hz)

VSUPPLY =±15V ~
VSUPPLY =±10V

~

o

-80

-

""""

-40

..

100K

FIGURE 16. POWER SUPPLY REJECTION RATIO vs
FREQUENCY

24
_

100 110

FIGURE 14. SETTLING TIME FOR VARIOUS OUTPUT STEP
VOLTAGES

~

~

50

SETTUNG TIME (n8)

120

iii"
:E.
Q 100

!

...

....

-2.5

o

FIGURE 13. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE

I

,

w

LOAD RESISTANCE (0)

ia
II:

o.sm~ ~

,

~

o

~

,

o

40
80
TEMPERATURE (oC)

120

160

FIGURE 17. POWER SUPPLY CURRENT va TEMPERATURE

3-504

1M

HA-5190, HA-5195
Die Characteristics
SUBSTRATE POTENTIAL (Powered Up):

DIE DIMENSIONS:
54 mils x 88 mils x 19 mils
1360j.l.m x 2240j.l.m x 483j.1.m

vTRANSISTOR COUNT:

METALLIZATION:

49

Type: AI. 1% Cu
Thickness: 16kA ±2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02. 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-5190

v+

-IN

3-505

HA-5221, HA-5222
100MHz, Single and Dual Low NOise,
Precision Operational Amplifiers

November 1996

Features

Description

• Gain Bandwidth Product .••••....••••••••• 100MHz

The HA-5221/5222 are single and dual high performance
dielectrically isolated, op amps, featuring precision DC
characteristics while providing excellent AC characteristics.
Designed for audio, video. and other demanding applications,
noise (3.4nVlVHZ at 1kHz), total harmonic distortion
«0.005%), and DC errors are kept to a minimum.

• Unity Gain Bandwidth .••...•.......•...•.. 25MHz
• Slew Rate •.•.•..••....•.••...•..•••.•••• 25V/IlS
• Low Offset Voltage. • . . . . . . • • . . . • . . • • . . • • .• O.3mV
• High Open Loop Gain ...••••••••••••.••••• 128dB
• Channel Separation at 10kHz ••••••••..••••• 110dB
• Low Noise Voltage at 1kHz ..•••••••.••.. 3.4nVl'i1ii
• High Output Current ••...••...•••••.•••.••. 56mA
• Low Supply Current per Amplifier ••.•••.•..••• 8mA

Applications
• Precision Test Systems
• Active Filtering
• Small Signal Video

The precision performance is shown by low offset voltage
(0.3mV), low bias currents (40nA), low offset currents
(15nA), and high open loop gain (128dB). The combination
of these excellent DC characteristics with the fast settling
time (0.41lS) make the HA-5221/5222 ideally suited for
precision signal conditioning.
The unique design of the HA-5221/5222 gives them
outstanding AC characteristics not normally associated with
precision op amps, high unity gain bandwidth (35M Hz) and
high slew rate (25V/IlS). Other key specifications include high
CMRR (95dB) and high PSRR (100dB). The combination of
these specifications will allow the HA-5221/5222 to be used in
RF signal conditioning as well as video amplifiers.

• RF Signal Conditioning

For MIL-STD-883C compliant product and Ceramic LCC packaging, consult the HA-5221/52221883C data sheet. Harris
AnswerFAX (407-724-7800) Document #3716.

Pinouts

Ordering Information

• Accurate Signal Processing

HA-5221
(PDIP, CERDIP, SOIC)
TOP VIEW

HA-5221
(METAL CAN)
TOP VIEW

PART NUMBER
(BRAND)

+BAL
.BALE}S+BAL
-IN 2
_
7 v+
+IN 3

4

Yo

PKG.
NO.

PACKAGE

HA2·5221-5

Ot075

8 Pin Metal Can

T8.C

HA3·5221-5

01075

8 Ld PolP

E8.3

HA7-5221-5

01075

8 LdCERolP

F8.3A

HA7-5221-9

-401085

8 LdCERolP

F8.3A

HA9P5221-5
(H52215)

010 75

8 LdSOIC

M8.15

HA3-5222-5

Ot075

16 Ld PolP

E16.3

HA7-5222-5

01075

8LdCERoIP

F8.3A

HA7-5222·9

-40 to 85

8 LdCERolP

F8.3A

HA9P5222-5

01075

16 Ld SOIC

M16.3

HA9P5222·9

-4010 85

16 Ld SOIC

M16.3

6 OUT

5 NC

HA-5222 (PDIP, SOIC)
TOP VIEW

NC
-INt

TEMP.
RANGEfc)

NC

+INt

V-

HA-5222 (CERDIP)
TOP VIEW

OUT1~SV+
-INt 2

70UT2

+INt 3

6 -IN2

V_4

5 +IN2

-IN2
+IN2

CAUTION: These devices ara sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation t996

3-506

File Number

2915.2

HA-5221, HA-5222
Absolute Maximum Ratings

Thermal Information

Supply Voltage Between V+ and V- Terminals .............. 35V
Differential Input Voltage (Note 1)......................... 5V
Output Current Short Circuit Duration ................ Indefinite

Thermal Resistance (Typical, Note 2)
BJA (oCIW) BJC (oCIW)
Metal Can Package. . . . . . . . . . • • . . . . .
165
80
CERDIP Package (HA7-5221). . . . . . . . .
135
50
115
30
CERDIP Package (HA7-5222).........
8 ld PDIP Package. . . . . . . . . . . . . . . . .
92
N/A
8ld SOIC Package.......... .......
157
N/A
85
N/A
16 ld PDIP Package. . . . . . . . . . . . . . . •
95
N/A
16 Ld SOIC Package. . . . . . . • . . • . . . . .
Maximum Junction Temperature (Hermetic Package) ........ 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ....•... , -65°C to 150°C
Maximum lead Temperature (Soldering 10s) ............. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5221/5222-9 .......................... -40°C to 85°C
HA-5221/5222-5 ............................ OoC to 75°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may cause permanent damage to the device. This Is a stress only raVng and operation
of the device at these or any other conditions above those indicated in the operational secVons of this specification is not implied.

NOTES:
1. Input is protected by back-to-back zener diodes. See applications section.
2. BJA is measured with the component mounted on an evaluation PC board In Iree air.

Electrical Specifications

VSUPPLY = ±15V, Unless Otherwise Specified
HA-5221-9, HA-5222-9

PARAMETER

TEST CONDITIONS

TEMP.
fC)

MIN

TYP

MAX

-

0.30

0.75

0.35

1.5

HA-5221-5, HA-5222-5
MIN

..J

TYP

MAX

UNITS

0.30

0.75

mV

0.35

1.5

mV

0.5

-

IlVtDC

40

100

nA

70

200

nA

15

100

nA

30

150

nA

400

750

Jl.V

-

1500

Jl.V

-

V

INPUT CHARACTERISTICS
Input Offset Voltage

25
Full

Average Offset Voltage Drift

Full

Input Bias Current

25
Full

Input Offset Current

25
Full

Input Offset Voltage Match

25

a:

0.5

-

40

80

70

200

15

50

30

150

400

Full
Common Mode Range
Differential Input Resistance

-

-

25

-

0.25

-

6.2

10

-

70

-

0.25

-

Jl.Vp_p

6.2

10

nVNHz

3.6

6

nV/.JFfZ

3.4

4.0

nVI.JFfZ

8.0

-

4.7

8.0

pAl.JFfZ

-

1= 0.1Hz to 10Hz

25

Input Noise Voltage

1= 10Hz

25

Density (Notes 3, 12)

1= 100Hz

25

-

3.6

6

I = 1000Hz

25

-

3.4

4.0

Input Noise Current

1=10Hz

25

4.7

Density (Notes 3, 12

I = 100Hz

25

-

I = 1000Hz

25

Note 4

25

3-507

-

±12

±12

-

-

750

25

70

-

1500

Input Noise Voltage

THD+N

o_-r>+

_

_

1
~lkn ~

v

o OUT

50pF

FIGURE 1. TRANSIENT RESPONSE TEST CIRCUIT

100mV

2.SV
OV

-100mV
-2.SV

2.SV

100mV
VOUT

OV

OV

...J

80pF, a small resistor, son
to 100n, should be connected in series with the output and
inside the feedback loop.

!
z

100
80
60

~40

~

!ct::i
a: 11.
W:E
~o(

Vs = ±1SV, TA = 2Soc

9

I

iD
"U

GAIN

iii
UJ
UJ

a:

i""" 1'-00

1-00
PHASE

-3
-6

135

6

lOOK

1M

10M

"-

PHASE

::IE

...

10K

FREQUENCY (Hz)

FIGURE 5. OPEN LOOP GAIN AND PHASE

UJ
UJ

a:

CI
UJ

c

180~

\

135 ~
C

~

90 ::IE

\

UJ

~
:c

100M

iii

r\

90~
45

10K

G~INI

~O

1809.

-,

I I

z3

UJ

1'-00

~=A ~~~ lK~ CL ~~O~~

6

CI

0
lK

When designing with the HA-S221 or the HA-S222, good
high frequency (RF) techniques should be used when building a PC board. Use of ground plane is recommended.
Power supply decoupling is very important. A O.Ol~F to
0.1 ~F high quality ceramic capacitor at each power supply
pin with a 2.2~F to 1O~F tantalum close by will provide excellent decoupling. Chip capacitors produce the best results
due to ease of placement next to the op amp and basically
no lead inductance. If leaded capacitors are used, the leads
should be kept as short as possible to minimize lead inductance.

12

20
0

O!!:!
-II..

lK, CL = 50pF
I I

--r-.

...I
0(0

PC Board Layout Guidelines

=

120

VOUT

Za:

4

Typical Performance Curves

It~6
V

6

·15V

RL

J RLlMIT3

lOOK

1M

10M

UJ

45 UI
C
0
100M

FREQUENCY (Hz)
V8

FIGURE 6. CLOSED LOOP GAIN

FREQUENCY

3-S11

V8

FREQUENCY

:c
...

HA-5221, HA-5222

Typical Performance Curves

Vs = ±15V. TA = 25°C (Continued)

Ay,,-10oo

Ay .. -1. RL" 1K. CL" 50pF

II 1

Ay =-100

-""

GAIN

Ay=-10

\

, I
, , !!

....... "'"
Ay = -10

180

....

135

\

, : !I

1M

10M

~I

·1 II

~

100K

10K

100M

Ay=+1,RL=1K

-.

-.

- --

i

~

100K

i"--o

1M

~

- -PSRR

:- i"--

60

.....

II:
II: 40

....

~

!f2O
o

100M

10M

80

100M

300

fIL .. 1K

18

w
@j

10M

FIGURE 10. PSRR vs FREQUENCY

20

~
z

......

FREQUENCY (Hz)

FIGURE 9. CMRR vs FREQUENCY

~

~~RR

1M

100K

10K

FREQUENCY (Hz)

14

100M

Ay=+1.RL=1K
100

~

10K

~

~

iE

FIGURE 8. VARIOUS CLOSED LOOP GAINS vs FREQUENCY

o

Z

10M

w

FIGURE 7. CLOSED LOOP GAIN vs FREQUENCY

20

16

1M

o

FREQUENCY (Hz)

40

>"

'"

I

e.

!:

:i

"'"'

Ay=-1000

100
~
II: 60

135

I\.

iIi!

FREQUENCY (Hz)

120

iii 80

180

~ -I'\,.

o

~

100K

..... .....

\

PHASE

10K

RL .. 1K. CL" 50pF

:"""- ~

250

~

200

12

w 150

10

:.J

100

8

Iii
UI

50

~
~

...0...

6
4

0

-50
-60

-40

~

0

20

40

80

80

~

-100
-60

~

TEMPERATURE (GC)

FIGURE 11. OPEN LOOP GAIN vs TEMPERATURE

-"'"

.-

...... l-

i-'-

-

~"",

-40

-20

0

20

40

60

80

TEMPERATURE (DC)

FIGURE 12. OFFSET VOLTAGE vs TEMPERATURE
(4 REPRESENTATIVE UNITS)

3-512

-'
100

120

HA-5221, HA-5222

Typical Performance Curves

VS=±15V, TA = 25°C (Continued)
14
RL = 6000
13.5

~
w

160

C

S.

!zw

~
~

120

:I

a:
a:

100
60

0

U>

60

~

'100..

....

40

'"

13

C!I

140

5

12

~

11.5

~

r-

20

12.5

.

.......

-

11
10.5

0
·20
-40
-60

10
·20

-40

0

40

20

60

60

100

-60

120

-40

·20

0

TEMPERATURE (DC)

40

20

60

80

100

120

TEMPERATURE (DC)

FIGURE 14. OUTPUT VOLTAGE SWING va TEMPERATURE

FIGURE 13. BIAS CURRENT va TEMPERATURE
(4 REPRESENTATIVE UNITS)
1.1

~::: 1.05

Ay

=+1, RL =lK, CL =50pF

70

~

;c
~

e
~ 0.95

I

HA-5222

w
z 50
0(
:c 40
0
w

. "" "'"

1-" ....

~
!:l
~

0.9

w

i
~
v,


CJ

FREQUENCY (Hz)

90

§

VOLTAGE NOISE 6
cliRRENTNO ISE 3

Z

!zw

o
1

17

15

100

a:

I'-

r--

FIGURE 19. OUTPUT VOLTAGE SWING VB SUPPLY VOLTAGE

ffi

9

o
7

~

12

2

o
5

I¥
Q.

~

".

,

5

It

.--

21

12

;; 10

~

!;

5

f

24

14 ~

1!z
w
a:
a:

110

90

::>
CJ

1'-.

\

!;

5
0

o

70

50

1000

LOAD CAPACITANCE (pF)

o

i'.. ..........
2

4

TIME AFTER SHORT CIRCUIT (MINUTES)

FIGURE 23. BANDWIDTH AND PHASE MARGIN VB LOAD
CAPACITANCE

FIGURE 24. SHORT CIRCUIT OUTPUT CURRENT VB TIME

3·514

HA-S221, HA-S222
Typical Performance Curves

Vs = ±15V. TA = 25°C (Continued)

Vertical Scale = lmV/Oiv.; Horizontal Scale = ls/0iv.
Av +25.000; EN 0.168I1Vp_P RTI

=

Vertical Scale = 10mV/Oiv.; Horizontal Scale = ls/0iv.
Ay = +25.000; EN = 1.5I1Vp_P RTI

=

FIGURE 25. O.lHz TO 10Hz NOISE

18
I I
Ys =±18

16

~
w

FIGURE 26. 0.1 Hz TO 1MHz

18

Ay = +1, RL = lK, CL = 15pF, THD,; 0.01%

~

14

Cl

~

~

w

12

Ys = +15

10

I

0..
f-

::>
C

I

I

4

w

~

2

10

::>

8

0

6

~

~

2

lOOK

o~

10M

1M

FIGURE 27. OUTPUT VOLTAGE SWING vs FREQUENCY

.,.

!!!
~

:s
~
!;;:

9

0..

~

8

!zw

7_5

..... ~

a:

a:
a:

i3
g;~

.....
~

'"

--

I""

N

a:Q.

!(:::i
W:::iE

~
III

III I
III

lOOK

iii

8.5

II~s=J5

FIGURE 28. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE

9.5

:i



Ay = +1, THD,; 0.01%, f = 1kHz

16

6

-60

-40

-20

0

20

40

60

80

100

10K

120

TEMPERATURE (DC)

lOOK

1M

10M

FREQUENCY (Hz)

FIGURE 29. SUPPLY CURRENT/AMPLIFIER vs TEMPERATURE

FIGURE 30. CHANNEL SEPARATION vs FREQUENCY
(HA-5222 ONLY)

3-515

100M

HA-5221, HA-5222

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

v-

72 mils x 94 mils x 19 mils
1840J.1m x 2400J.1m x 483J.1m

TRANSISTOR COUNT:

METALLIZATION:

62

Type: AI. 1% Cu
Thickness: 16kA ±2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (513N4) over 5i1ox (5102, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-5221

v-

+IN

-IN

-BAL

+BAL

v+

OUT

3-516

HA-5221, HA-5222

Die Characteristics
SUBSTRATE POTENTIAL (Powered Up):

DIE DIMENSIONS:

v-

78 mils x 185 mils x 19 mils
1980l1m x 4690l1m x 48311m

TRANSISTOR COUNT:

METALLIZATION:

128

Type: AI, 1% Cu
Thickness: 1skA ±2kA

PROCESS:
Bipolar Dielectric Isolation

PASSIVATION:
Type: Nitride (Si3N4) over Silox (Si02 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

Metallization Mask Layout
HA-5222
OUTl

v+

...I
«(I)

Za:

O!!:!
-II.

!ci::J
a: a.
~~

o

-INl
+INl

vOUT2

-IN2

3-517

HFA'1100, HFA1120
850M Hz, Low Distortion
Current Feedback Operational Amplifiers

November 1996

Features

Description

• Low Distortion (30MHz, HD2) . • . • • •. ·56dBc

The HFA 1100, 1120 are a family of high-speed, wideband, fast
settling current feedback amplifiers. Built with Harris' proprietary
complementary bipolar UHF-l process, these devices are the fastest
monolithic amplifiers available from any semiconductor manufacturer.

• ·3dB Bandwidth •..•....••....••.. 850M Hz
• Very Fast Slew Rate •••... , ..•.••. 2300Vl!1s
• Fast Settling Time (0.1 %) ••.•.•••..•. 11 ns
• Excellent Gain Flatness
• (100MHz) ..................... ±O.l4dB
• (50MHz)...................... ±O.04dB
• (30MHz) ...................... ±O.OldB
• High Output Current . . . . . • . • • • • • • •• 60mA

The HFA1100 is a basic op amp with uncommitted pins 1, 5, and 8.
The HFA 1120 includes inverting input bias current adjust pins (pins 1
and 5) for adjusting the output offset voltage.
These devices offer a significant performance improvement over the
AD811, AD9617/18, the CLC400-409, and the EL2070, EL2073,
EL2030.

• Overdrive Recovery •...•..•...•••.. <10ns

For Military grade product refer to the HFA1100/883, HFA1120/883
data sheet.

Applications

Ordering Information

• Video Switching and Routing

PART NUMBER
(BRAND)

TEMP.
RANGE (OC)

PACKAGE

-5510125

8 Ld CERDIP

F8.3A

HFA1100lJ, HFA1120lJ

-401085

8Ld CERDIP

F8.3A

• Medical Imaging Systems

HFA11001P. HFA1120lP

-40 to 85

8 Ld PDIP

E8.3

• Related Literature
• AN9420, Current Feedback Theory
• AN9202, HFA11XX Evaluation Fixture

HFA11001B, HFA1120lB
(H11001, H11201)

-401085

8LdSOlC

M8.15

Pinouts

The Op Amps With Fastest Edges

• Pulse and Video Amplifiers
• Wideband Amplifiers
• RFIIF Signal Processing
• Flash AID Driver

HFA1100
(PDIP, CERDIP, SOIC)
TOP VIEW

HFA1100MJ/883,
HFA1120MJ/883

HFA11XXEVAL

PKG.NO.

DIP Evaluation Board for High-Speed Op Amps

,~:!It,~.
:~
..~~
,
:.:
. : ::.

.~.::

'.:

INPUT

220MHz
SIGNAL

OUTPUT
(Ay=2)
HFA1130
OPAMP

HFA1120
(PDIP, CERDIP, SOIC)
TOP VIEW

Ons

25ns

CAUTION: These devices are sensijive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-518

File Number

2945.5

HFA1100, HFA1120
Absolute Maximum Ratings TA = 25°C

Thermal Information

Voltage Between V+ and V· ............................ 12V
Input Voltage .................................... VSUPPLY
Differential Input Voltage................................ 5V
Output Current (50% Duty Cycle) .•.................... 60mA

Thermal Resistance (Typical. Note I)
BJA (OCfW) BJC (OCIW)
CERDIP Package •.•. . . . . . . . . . . . .
115
35
PDIP Package...................
130
N/A
SOIC Package.. .....•.... .......
170
N/A
Maximum Junction Temperature (Die or CERDIP) ......... 175°C
Maximum Junction Temperature (Plastic Package) ••...... 150°C
Maximum Storage Temperature Range .. • . . • . .. -65°C to 1500 C
Maximum Lead Temperature (Soldering lOs) •...•.•.....• 3000 C
(SOIC • Lead Tips Only)

Operating Conditions
Temperature Range .......................... -40oC to 85°C

CAUTION: Stresses above those listed In "Absolute Maximum Ratings' may cause permanent damage to the device. This is

a stress only raUng and operation

.01 the device at these or any other conditions above those indicated in the operational sections 01 this speclffcation is not Implied.

NOTE:
I. BJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±5V. Av = +1. RF = 5100. RL = 1000. Unless Otherwise Specified
(NOTE 2)

TEST
LEVEL

TEMP.
(DC)

Input Offset Voltage (Note 3)

A

25

A

Full

Input Offset Voltage Drift

C

Full

-

10

A

25

40

46

-

A

Full

38

-

-

A

25

45

50

A

Full

42

-

-

A

25

-

25

40

jJ.A

A

Full

-

65

jJ.A

C

Full

40

-

nAfDC

A

25

20

40

A

Full

-

50

!lAIV
!lAIV
jJ.A

PARAMETER

TEST
CONDITIONS

MIN

TVP

MAX

UNITS

2

6

mV

-

10

INPUT CHARACTERISTICS

VloCMRR

INcM = ±2V

VloPSRR

AVS= ±1.25V

Non-Inverting Input Bias Current
(Note 3)

+IN=OV

+IBIAS Drift
+I BIAS CMS

Inverting Input Bias Current (Note 3)

AVCM=±2V

-IN=OV

-I BIAS Drift
-IBIASCMS

AVCM =±2V

-

-

mV
jJ.VI"C
dB
dB
dB
dB

A

25

12

50

A

Full

-

-

60

jJ.A

C

Full

-

40

-

nAfDC

A

25

6

15

-

27

!lAIV
!lAIV
!lAIV
!lAIV
kQ

I

7

-

10

A

25

A

Full

-

-I BIAS Adj. Range (HFAI120)

A

25

±IOO

±200

Non-Inverting Input ReSistance

A

25

25

50

-

Inverting Input Resistance

C

25

-

20

30

a

Input Capacitance (Either Input)

B

25

'.

2

·

pF

Input Common Mode Range

C

Full

±2.5

±S.O

-

V

-

4

-

nVNHz

18

·

pANHz

21

·

pANHz

A
-I BIAS PSS

AVs=±1.25V

Full

Input Noise Voltage (Note 3)

100kHz

B

25

+Input Noise Current (Note 3)

100kHz

B

25

·Input Noise Current (Note 3)

100kHz

B

25

3-519

jJ.A

....2.6
.§. 2.5
2.4
~ 2.3
~ 2.2
Iii 2.1
UI 2
II: 1.9
01.8
1.7
~ 1.6
- 1.5
1.4
1.3

./
/

III

-'
-'

-'

60

80

100 120

9

10

45
42
39
36
33 C
30 .=,

.J:L .....

+IB'AS

1'0'
·IBIAS

.-..
~

~

~

020

40

60

27 ~
24 III
21 ~
18
15 UI
12 ~
9
6
3

a

l-'

!:i

8

40

20

FIGURE 22. SUPPLY CURRENT VB TEMPERATURE

..- / '

5

.....

TEMPERATURE rC)

FIGURE 21. OVERSHOOT VB FEEDBACK RESISTOR

22
21
20
19
18
17
16
15
14
13

~<

..... i.'

A.

.......

W:5

~~

A.
::> 20
UI

........

!;;::J
a: a..

I

FEEDBACK RESISTOR (0)

~

900 1000

24

u 21

"-.......
360

!

800

25

::>

'"

~ 14~:

w

700

C
.§. 23

.......

o

-

600

Av = +2, tA = 200pa, VOUT = 2Vp•p

~~

!z

500

FIGURE 20. OVERSHOOT VB INPUT RISE TIME

FIGURE 19. OVERSHOOT VB INPUT RISE TIME

1

400

INPUT RISE TIME (ps)

INPUT RISE TIME (pa)

36
34
32
30
28
~ 26
- 24

(Continued)

Av=+1

I

'" ........

.....

VOUT = 0.5Vp.p

100

=5100, TA =25°C, RL =1000, Unless Otherwise Specified

i'o....... VOUT = 1Vp.p

1""00.

15 24 I ~22 l 12 20
w 18
f5 16

=

VSUPPLY ±5V, RF

80

100120

o

TEMPERATURE (OC)

TOTAL SUPPLY VOLTAGE (V+ • V" V)

FIGURE 23. SUPPLY CURRENT VB SUPPLY VOLTAGE

FIGURE 24. VIO AND BIAS CURRENTS VB TEMPERATURE

3·525

HFA1100, HFA1120
Typical Performance Curves

VSUPPLY = tSV, RF = 5100, TA = 25°C, RL = 1000, Unless Otherwise Specified (Continued)

3.7
Av =-1, RL = 500
3.6
I I I
3.5
3.4
:-"+VOUT
w
3.3
io'"
3.2
I-VOUT~ ........
~ 3.1
I::;)
i.o'"
3
II.
2.9

300

30

I'"-

€

!

t

'"'

50

,I

2.8

2.7
2.6
2.5
-60

-40

1'\

" "'"

~

-20

275

I!l
i1

,,~

--

5
0

20

40

60

80

o

100 120

100

TEMPERATURE <"C)

FIGURE 25. OUTPUT VOLTAGE VB TEMPERATURE

1K

i

...
~.

10K
FREQUENCY (Hz)

ENI
INI"
INI+

100K

FIGURE 26. INPUT NOISE VB FREQUENCY

3-526

i

250
225 ~
200 S:
175
150
125 !i
100
75 8
50
25

o

HFA1100, HFA1120

Die Characteristics
TRANSISTOR COUNT:

DIE DIMENSIONS:
63 mils x 44 mils x 19 mils
1600~m

52

x 1130~m

SUBSTRATE POTENTIAL (Powered Up):

METALLIZATION:

Floating (Recommend Connection to v-)

Type: Metal 1: AICu (2%)fTiW
Thickness: Metal 1:

akA ±O.4kA

Type: Metal 2: AICu (2%}
Thickness: Metal 2: 16kA

±O.akA

PASSIVATION:
Type: Nitride
Thickness:

4kA ±O.5kA

Metallization Mask Layout
HFA1100, HFA1120

.J

etC/)

r

&0070A

Za:

x•

O!!!
-II.

+IN

-IN

~:J
a: a..

W:E

~et
y-

BAL

BAL

y+

OUT

3-527

HFA1102
600MHz Current Feedback
Amplifier with Compensation Pin

November 1996

Features

Description

• Compensation Pin for Bandwidth Limiting

The HFA 1102 is a high speed wideband current feedback
amplifier featuring a compensation pin for bandwidth limiting.
Built with Harris' proprietary complementary bipolar UHF-1
process, it has excellent AC performance and low distortion.

• Low Distortion (HD2 at 30MHz). • . . • • • • • • • •• -56dBc
• -3dB Bandwidth •.••.•..••.•.•..•••.•...• 600MHz
• Very Fast Slew Rate •.•....•.•..••.•..••. 2000VlllS
• Fast Settling Time (0.1%) .•.•.•...••...•.•.• 11ns
• Excellent Gain Flatness
- (100MHz) .•••.......••..•.•••.••.....• ±O.05dB
- (50MHz) •.•••..••...•.•.•.•.••.•.....• ±O.02dB
- (30M Hz) •••••.•.•...••.••••.••.••.•... ±O.01dB
• High Output Current •.•••.•••••••.•.•.....• 60mA
• Overdrive Recovery •...•••••••....•...••• , <10ns

Because the HFA 1102 is already unity gain stable, the
primary purpose for limiting the bandwidth is to reduce the
total noise (broadband) of the circuit. The bandwidth of the
HFA1102 may be limited by connecting a capacitor and
series damping resistor from pin 8 to ground. Typical
bandwidths for various values of compensation capacitors
are shown in the Electrical Specifications section of this
datasheet.
A variety of packages and temperature grades are availal>le.
See the ordering information below for details.

Ordering Information

Applications

PART NUMBER
(BRAND)

• Low Noise Amplifiers
• Video Switching and Routing

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

HFA11021J

·401085

HFA11021P

·401085

8 Ld PDIP

E8.3

·401085

8LdSOlC

M8.15

• Flash AID Driver

HFA11021B
(HI1021)

• Medical Imaging Systems

HFA11XXEVAL

Pinout

The Op Amps with Fastest Edges

• Pulse and Video Amplifiers

8LdCERDIP

F8.3A

• RFIIF Signal Processing

DIP Evaluation Board for High Speed Op Amps

HFA1102
(PDIP, CERDIP, SOIC)
TOP VIEW
INPUT
220MHz
SIGNAL
N c l B a COMP
·IN 2
7 v+
+IN3

y-

4

+

6 OUT

OUTPUT
(Ay=2)
HFAll02
OPAMP

NC

OnB

CAUTION: These devices are sensitive 10 electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporalion 1996

3-528

25nB

File Number

3597.2

HFA1102
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ 12V
DC Input Voltage ..•...............•...•......... VSUPPLY
Differential Input Voltage ................................ 5V
Output Current (50% Duty Cycle) .....................•. 60mA

Thermal Resistance (Typical, Note 1)
9JA (oCIW) 9JC !!,CIW)
CERDIP Package................
120
35
PDIP Package. . . . . . . . . . . .. • . . . ..
130
N/A
SOIC Package...................
170
N/A
Maximum Junction Temperature (Ceramic Package and Die) .. 175°C
Maximum JunC1ion Temperature (Plastic Package) ..•..... 150°C
Maximum Storage Temperature Range . . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOS). . • • . . . . . . •. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may cause permanent damage to the device. This Is a stress only raNng and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification Is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

PARAMETER

VSUPPLY = ±5V, Av = +1, RF = 5100, RL = 1000, CCOMP = OpF,
Unless Otherwise Specified
TEST
CONDITIONS

TEMP.
(oC)

MIN

TYP

MAX

UNITS

6

mV

10

mV

INPUT CHARACTERISTICS
Input Offset Voltage

25
Full

Input Offset Voltage Drift
VIOCMRR

Full
AVCM=±2V

VIOPSRR

AVS=±1.25V

Non-Inv. Input Bias Current

+IN=OV

25

40

FUll

38

25

45

Full

42

25
Full
Full

+ISIAS Drift
+ISIASCMS

25

AVCM=±2V

Full
Inv. Input Bias Current

-IN=OV

-

25

-

10
46

50

-

-

-

-

25

40

-

65

-

40

-

20

40

-

-

50

Full
-ISlAS Drift

2

Jl.VPC
dB
dB
dB
dB

JJ.A
JJ.A
nAPC

12

50

-

60

JJ.AIV
JJ.AIV
JJ.A
JJ.A

-

nAPc

Full

-

40

25

-

1

7

Full

-

-

10

25

-

6

15

Full

-

-

27

JJ.AIV
JJ.AIV
JJ.AIV
JJ.AIV

Non-Inv. Input Resistance

25

25

50

-

kQ

Inv. Input ReSistance

25

-

16

30

0

-ISIASCMS

-ISlAS PSS

Input CapaCitance

AVCM=±2V

AVS= ±1.25V

Either Input

Input Common Mode Range

25

-

2

Full

±2.5

±3.0

Input Noise Voltage

100kHz

25

+Input Noise Current

100kHz

25

-Input Noise Current

100kHz

25

3-529

-

4
18
21

-

pF
V
nVNFfi
pANHz
pANHz

...J

etC/)
Za:
O~

-II..

tc::l
a: 11.
W:5

~et

HFA1102
Electrical Specifications

VSUPPLY ~±!5V, Av = +1, RF = 5100, RL = 1000, CCOMP = OpF,
Unless Otherwise Specified (Continued)

TEST
CONDITIONS

PARAMETER
TRANSFER CHARACTERISTICS

TEMP.
(oC)

MIN

TYP

Open Loop Translmpedance

25

·

500

Linear Phase Deviation

OCto 100MHz

25

·

0.6

Differential Gain

NTSC, RL = 750

25

0.03

Differential Phase

NTSC, RL = 750

25

·
·

Full

1

CCOMP=OpF

25

CCOMP = 1pF

25

·
·
·

Minimum Stable Gain
Bandwidth Limiting Characteristics
·3dB Bandwidth (VOUT = 0.2Vp.p, "-I = +1)

Gain Flatness (To 30M Hz)

Gain Flatness
Gain Flatness

OUTPUT CHARACTERISTICS

CCOMP= 3pF

25

CCOMP=7pF

25

CCOMP= OpF

25

UNITS

·
·
·
·

k.Q

CCOMP= 1pF
CCOMP=3pF

0.03

.
600
350
190
55

Degrees
%
Degrees
VN

·
·
·
·

MHz
MHz
MHz
MHz

25

·
·

±0.01

25

·

±0.10

To 100MHz

25

T050MHz

25

·
·

±D.05

25

±a.o

±a.3

·

Full

±2.5

±a.o

·

V

25

50

65

·

mA

Full

40

60

·
·

·56

dBc

·80

dBc

±D.05

dB

·

dB
dB

·

±D.02

dB
dB

Av = +2, Unless Otherwise Specified

Output Voltage

Av=·1

Output Current

RL = 50n, "-I = ·1

Closed Loop Output Impedance

DC

25

2nd Harmonic Distortion

30MHz, VOUT = 2Vp.p

25

3rd Harmonic Distortion

30MHz, VOUT = 2Vp.p

25

3rd Order Intercept

100MHz

25

1dB Compression

100MHz

25

TRANSIENT RESPONSE

MAX

"-I = +1, RF = 1500, ROAMP = 1200, Unless Otherwise Specified

0.1

30

·

20

V

mA

·

°

·
·

dBm
dBm

"-I = + 1, RF = 150n, ROAMP = 1200, Unless Otherwise Specified

Rise Time

VOUT = 2.0V Step

25

600

VOUT = 2.0V Step

25

10

·
·

ps

Overshoot
Slew Rate

"-1=+1, VOUT= 5Vp.p

25

1200

·

V/Jls

Av = +2, VOUT = 5Vp.p

25

0.1% Settling Time

VOUT = 2V to OV

25

0.2% Settling Time

VOUT = 2V to OV

25

·
·
·

Supply Voltage Range

Full

±4.5

Supply Current

25

·
·

%

2000

V/JlS

11

ns

7

·

ns

POWER SUPPLY CHARACTERISTICS

Full

3·530

±!5.5

V

21

26

mA

.

33

mA

HFA1102

Application Information

500a

500a

Optimum Feedback Resistor (RF)
All current feedback amplifiers require a feedback resistor, even
for unity gain applications. The RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifie~s bandwidth is inversely
proportional to RF' The HFA1102 design is optimized for a 150U
RF, at a gain of +1. Decreasing RF in a unity gain application
decreases stability, leading to excessive peaking and overshoot.
At higher gains the amplifier is more stable, so RF can be
decreased in a trade-off of stability for bandwidth.

H---...-.....-o+5
IN _ _----{:Jj

•.~------------~.
TOP LAYOUT

Bandwidth Umiting
The bandwidth of the HFA1102 may be limited by connecting a
resistor (RDAMP) and capacitor in series from pin 8 to GND. The
series resister is required to damp the interaction between the
package parasitics and CCOMP. Typical bandwidths for various
values of compensation capacitor are shown in the specification
tables. Because the HFA1102 is already unity gain stable, the
main reason for limiting the bandwidth is to reduce the total noise
(broadband) of the circuit. Additionally, compensating the
HFA 1102 allows the use of a lower value RF for a given gain. The
decreased bandwidth due to CCOMP offsets the bandwidth
increase from the lower RF, keeping the amplifier stable. Reducing RF provides the double benefits of reduced DC errors
(-IB x RF) and reduced total noise (lNI x RF and 4KTRF)·

+IN

•

•

BOTTOM LAYOUT

PC Board Layout

....I

ctU)

za:

O!!!
-II.
!ci:::i

a:

The frequency performance of this amplifier depends a great
deal on the amount of care taken in designing the PC board. The

use of low inductance components such as chip resistors
and chip capaCitors is strongly recommended, while a solid
ground plane is a mustl
Attention should be given to decoupling the power supplies. A
large value (10IlF) tantalum in parallel with a small value chip
(0.11lF) capaCitor works well in most cases.
Terminated microstrip signal lines are recommended at the input
and output of the device. Output capacnance, such as that resulting from an improperly terminated transmission line will degrade
the frequency response of the amplifier and may cause oscillations. In most cases, the oscillation can be avoided by placing a
resistor in series with the output.

FIGURE 1. EVALUATION BOARD SCHEMATIC AND LAYOUT

Care must also be taken to minimize the capacitance to ground
seen by the amplifier's inverting input. The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot
and possible instability. To this end, it is recommended that the
ground plane be removed under traces connected to pin 2, and
connections to pin 2 should be kept as short as possible.
An example of a good high frequency layout is the Evaluation
Board shown.

Evaluation Board
The HFA1102 may be evaluated using the HFA11XX Evaluation
Board which is available from your local sales office (part number
HFA11XXEVAL). RDAMP and CCOMP should be connected in
series from the socket pin to the GND plane. The trace from pin 8
to the VH connector should be cut near the socket to remove this
parallel capacitance.The layout and schematic of the board are
shown below:

800

60

~~

:

6

.dc~3PF ~ ~§§

~
0.06
0.6

g

I"

z

i

Cl

~ "'~~

;;:

CC=7pF

i-"

~

m

~

Lr- Cc=OpF

~-CC=3PF~

Ir-- CC=1pF
~

I-- CC=7pF- V

i ! JI

L-.-l. 0.1

0.01

1

Cc = OpF
Av = -1
CC=1pF'1

~

PHASE

I

N

180

~e.

135

!II

w

I90 IL~

.,

~.

I

45

o

0.30.61
3 610 3060100300600
FREQUENCY (MHz)

FIGURE 2. OPEN LOOP TRANSIMPEDANCE FOR VARIOUS
COMPENSATION CAPACITORS

3-531

0...

W:i
~ct

HFA1102

Die Characteristics
, PASSIVATION:

DIE DIMENSIONS:

Type: Nitride
Thickness: 4kA ±O.5kA

63 mils x 44 mils x 19 mils
160011m x 1130l1m
METALLIZATION:

TRANSISTOR COUNT:

52

Type: Metal 1: AICu (2%)/TiW
Thickness: Metal 1: akA ±O.4kA

SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu (2%)
Thickness: Metal 2: 16kA ±O.akA

Floating (Recommend Connection to V-)

Metallization Mask Layout
HFA1102
+IN

-IN

COMP

VH(NOTE)

V+

OUT

NOTE: Output Limiting Function (VH. VLlls available to users of the HFA1102 in die form. Please refer to the HFA1130 data sheet for
information regarding the operation and use of this function.

3-532

HFA1103

HARRIS
SEMICONDUCTOR

200M Hz, Video Op Amp with
High Speed Sync Stripper

November 1996

Features

Description

• Removes Sync Signal From Component Video

The HFA 1103 is a high-speed, wideband, fast settling current feedback op amp with a sync stripping function. The
HFA 1103 is a basic op amp with a modified output stage that
enables it to strip the sync from a component video signal.
The output stage has an open emitter NPN transistor that
prevents the output from going low during the sync pulse.
Removing the sync signal benefits digitizing systems
because only the active video information is applied to the
AID converter. This enables the full dynamic range of the
AID converter to be used to process the video signal. The
HFA 1103 includes inverting input bias current adjust pins
(pins 1 and 5) for adjusting the output offset voltage.

• Low Residual Sync ............•.....•. amV (Typ)
• -3dB Bandwidth .•...••.••..•••......•••. 200MHz
• Very Fast Slew Rate ....•.....•.•..•......

600V/~

• Fast Settling Time (0.1 %) ....••.•..•.•••....• 9ns
• Excellent Gain Flatness, 32MHz ............. ±O.1dB
• Overdrive Recovery. . . . . . . • . • . . . . . . . . . . . •. <12ns

Applications

Ordering Information

• RGB Video Sync Stripping
• RGB Video Distribution Amplifier for Workstations
and PC Networks

PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

..J

c(cn

za:

• Video Conferencing Systems

HFA11031P

-401085

8Ld PDIP

E8.3

O!!:!
-II.

• RGB Video Monitor Preamp

HFA11031B
(H11031)

-401085

8LdSOlC

M8.15

a:

• Fiberoptic Receivers

Pinout

OIO+O.7V!

o'O~.3vI

~

11 If

~~

COMPONENT (RGB)
VIDEO INPUT

Io'o+O.7V

HFA1103 OUTPUT

Application Schematic
+5V

4.7K} Rs
2K

VIN

VOUT
o-::t-~;::l>--+~'t!""---Er:=:Jl--lRIN
Rr
75

75

RL
75

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-533

W::!l

~c(

Sync Stripper Waveforms
HFA1103
(PDIP, SOIC)
TOP VIEW

ti:::::i0.

RT
75

File Number

3957.2

HFA1103
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ 12V
Input Voltage ............•....................... VSUPPLY
Differential Input Voltage ................................ 5V
Output Current (50% Duty Cycle) ...................... 60mA

Thermal Resistance (Typical, Note 1)

Operating Conditions
Temperature Range . . . . . . . . . . .. . . . . . . . . . . . .. _40°C to 85°C

9JA (oCIW)

130
PDIP Package.............................
170
SOIC Package.. .. . . . . . . . . .. . . . . . . . . . . . . . ..
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. ThIs is a stress only rating and operation
of the device at these or any other conditions above those Indicated In the operational sections of thIs specification is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±5V, Av = +2, RF = 7500, RL = 500, Unless Otherwise Specified
TEMP

PARAMETER

TEST CONDITIONS

fc)

MIN

TYP

MAX

UNITS

8

10

mV

-

12

mV

10

30

mV

-

40

mV

-

jlvf'c

DC CHARACTERISTICS

Residual Sync (Note 2)

Full

-

Full

-

10

25

39

45

Full

35

25

-

25

VIN = -300mV, Av = +1

Full
Output Offset Voltage (Notes 3, 5)

25

Output Offset Voltage Drift (Note 3)
VOS PSRR

Non-Inverting Input Bias Current

AVs=±1.25V

+IN=OV

Full
Inverting Input Bias Current

-IN=OV

25

-

dB

5

40

jJ.A

-

65

jJ.A

5

50

jJ.A
jlA

dB

-

60

-IBIAS Adjust Range (Notes 4, 6)

25

100

200

-

ItA

Non-Inverting Input Resistance

25

25

50

-

kO

Full

Inverting Input Resistance

25

30

0

25

-

16

Input CapaCitance

2

Input Common Mode Range

Full

±2.5

±S.O

-

pF

-

4

Input Noise Voltage

100kHz

25

+Input Noise Current

100kHz

25

-Input Noise Current

100kHz

25

18
21

-

V
nVNHz
pAl..JHi
pAl..JHi

TRANSFER CHARACTERISTICS "'" = +2, Unless Otherwise Specified

Open Loop Transimpedance

500

-

kO

200

-

MHz

32

-

MHz

1

-

-

VN

25,85

2.5

3.0

-

V

-40°C

1.75

2.5

-

V

25

-

-3dB Bandwidth

Your = 1.0Vp_p, Av = +2

25

Gain Flatness

To±O.ldB

25

-

Full

Minimum Stable Gain
OUTPUT CHARACTERISTICS

Po.! = +2, Unless Otherwise SpeCified

Output Voltage (Note 3)

3-534

HFA1103
Electrical Specifications

VSUPPLY

=±5V, "'" =+2, RF =750n, RL =50n, Unless Otherwise Specified
TEMP
(oC)

MIN

TYP

25,85

50

60

-40°C

35

50

25

-

0.01

25

25

-

Supply Voltage Range

Full

Supply Current (No Load)

25

PARAMETER

TEST CONDITIONS

Output Current

Linearity Near Zero
TRANSIENT RESPONSE
Rise Time
Overshoot
Slew Rate
0.1% Settling

"'" =+2, Unless Otherwise Specified
VOUT =2.0V Step
VOUT =2.0V Step
"'" =+2, VOUT =0 to 2V, +2V to OV
VOUT =2V to OV

Overdrive Recovery Time

2XOverdrive

25
25
25

(Continued)

MAX

UNITS

-

rnA

ns

rnA

%

9

-

12

-

±4.5

-

±5.5

V

-

11

16

rnA

-

23

rnA

2
10
600

%

V/IlS
ns
ns

POWER SUPPLY CHARACTERISTICS

Full
NOTES:

2. The residual sync is specified at the output of a doubly terminated circuit (see page 1 of this data sheet).
3. Since the HFA1103 has an open emitter NPN output stage, this maasurement is only valid for positive values.
4. The -IBIAS current can be used to adjust the offset voltage to zero, but -IBIAS does not flow bidirectionally because the HFAll03 output
stage Is an open emitter NPN transistor.
5. VOS includes the error contribution of IBSN at RF

=750n.

6. This is the minimum change in inverting input bias current when a BAL pin is connected to V- through a son resistor.

Test Circuit

...

OUT

VIN

----1...,.
Y'
RIN
500

RF

RG

RL

7500

7500

-=j:-

VOUT

"::,.!:

500

-=j:-

FIGURE 1. TEST CIRCUIT

Application Information
Offset Adjustment
The HFA 1103 allows for adjustment of the inverting input bias
current to null the output offset voltage. -IBIAS flows through
RF, so any change in bias current forces a corresponding
change in output voltage. The amount of adjustment is a function of RF' With RF 7500, the typical adjust range is 150mV.
For offset adjustment connect a 101<0 potentiometer between
pins 1 and 5 with the wiper connected to V-.

=

PC Board Layout
The frequency performance of these amplifiers depends a
great deal on the amount of care taken in designing the PC
board. The use of low Inductance components such as

chip resistors and chip capacHors Is strongly recommended, while a solid ground plane Is a mustl
Attention should be given to decoupling the power supplies.
A large value (IOIlF) tantalum in parallel with a small value
chip (O.IIlF) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor in series with the output.

3-535

..J

600V

Thermal Resistance (Typical. Note 2)
9JA fCIW)
130
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package.............................
170
Maximum Junction Temperature (Die) .............. , ..... 175°C
Maximum Junction Temperature (Plastic Package) •....... 150°C
Maximum Storage Temperature Range . . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ..•.......... 300°C
(SOIC - Lead TIps Only)

Operating Conditions
Temperature Range. . . • . . . . . • . . . . . . . . . . . . . .. -400 C to 85°C
CAUTION: Stresses abo1/8 tho8e listed In "Absolute Max/mum Ratings" may cause permanent damage to the device, This is a stress only rellng and operation
of the device at these or any othe, conditions 8bo1/8 those Indicated In the operational sections of this specification is not Implied.

NOTES:
1. Output Is short circuit protected to ground. Brief short circuits to ground will not degrade reliability. however continuous (100% duty cycle)
output current must not exceed 30mA for maximum reliability.
2. 9JA Is measured with the component mounted on an evaluation PC board In free air.

Electrical Specifications

VSUPPLY = ±5V. Av = +1. RF = 5100. RL = 1000. Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

(NOTE 3)
TEST
LEVEL

TEMP.
(DC)

MIN

TYP

MAX

UNITS

2

5

mV

3

8

mV

1

10

v.VJOC
dB

INPUT CHARACTERISTICS
A

25

A

Full

B

Full

-

AVCM=±1.8V

A

25

47

50

AVCM=±1.8V

A

85

45

49

-

AVCM=±1.2V

A

-40

45

49

-

dB

AVps=±1.8V

A

25

50

54

-

dB

AVps=±1.8V

A

85

47

50

-

dB

AVpS=±1.2V

A

-40

47

50

-

dB

A

25

-

6

15

v.A

A

Full

10

25

itA

B

Full

5

60

nAJOC

AVpS=±1.8V

A

25

0.5

1

v.AN

AVpS=±1.8V

A

85

0.8

3

v.AN

AVps=±1.2V

A

-40

-

0.8

3

v.AN

AVCM=±1.8V

A

25

0.8

1.2

-

MO

AVCM=±1.8V

A

85

0.5

0.8

A

-40

0.5

0.8

-

MO

AVCM=±l.2V

A

25

-

2

7.5

v.A

A

Full

5

15

v.A

B

Full

60

200

nAJOC

Input Offset Voltage

Average Input Offset Voltage Drift
Input Offset Voltage
Common-Mode Rejection Ratio

Input Offset Voltage
Power Supply Rejection Ratio

Non-Inverting Input Bias Current

Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity

Non-Inverting Input Resistance

Inverting Input Bias Current

Inverting Input Bias Current Drift

3-540

-

-

dB

MO

HFA110S
Electrical Specifications

VSUPPLY =±5V, Av = +1, RF = 5100, RL = 1000, Unless Otherwise Specified (Continued)

PARAMETER
Inverting Input Bias Current
Common-Mode Sensitivity

Inverting Input Bias Current
Power Supply Sensitivity

TEST CONDITIONS

(NOrE3)
TEST
LEVEL

TEMP,

fc)

MIN

TYP

MAX

-

3

6

IlAIV

4

8

IlAIV

4

8

IlAIV

2

5

IlAIV

4

8

IlAIV

4

a

IlAIV

60

-

0

-

pF

tNCM=±1.8V

A

25

AVCM=±1.8V

A

85

AVCM= ±1.2V

A

-40

AVps=±l.aV

A

25

AVps=±1.8V

A

85

AVps=±1.2V

A

-40

C

25

Inverting Input Resistance
Input Capacitance

C

25

-

1.6

Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN' and -laiAS CMS Tests)

A

25,85

±1.8

±2.4

A

-40

±1.2

±1.7

-

3.5

UNITS

V

-

V

Input Noise Voltage Density (Note 6)

f= 100kHz

B

25

Non-Inverting Input Noise Current Density (Note 6)

f= 100kHz

B

25

Inverting Input Noise Current Density (Note 6)

f = 100kHz

B

25

-

20

-

Av=-l

C

25

-

500

-

kQ

270

-

MHz

240

-

MHz

2.5

nVNHi
pANHZ
.J

pANHZ

TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain
AC CHARACTERISTICS

Av=+I,+Rs=5100

B

25

-

B

Full

-

AV= -I, RF = 4250

B

25

AV=+2

B

25

B

Full

B

25

B

Full

Av=+I,+Rs=5100

B

25

Av=-l

B

25

Av=+2

B

25

To 25MHz

B

25

B

Full

AV= +10, RF = 1800

Full Power Bandwidth
(Vour = 5Vp_p at Av = +21-1,
4Vp_p atAv = +1. Note 6)

Gain Flatness
(Av = +2, Your = 0.2Vp_p, Note 6)

OUTPUT CHARACTERISTICS

-

-

330

130
90
135
140
115
±D.03

To 25MHz

B

25

B

25

A

Full

A

25

±3

±3.4

A

Full

±2.8

±3

B

25

B

Full

-

±D.04
±D.l1
±D.22
±D.03
±D.09

1

MHz
MHz
MHz

260

To 75MHz

Minimum Stable gain

Output Voltage Swing (Note 6)

-

300

-

To 75MHz

Gain Flatness
(Av = +1, +RS = 5100, Your = 0.2Vp_p, Note 6)

-

-

-

MHz
MHz
MHz
MHz
MHz
dB
dB
dB
dB
dB
dB
VN

Av = +2, RF = 5100, Unless Otherwise Specified
AV = -I, RL = 1000

3-541

-

Za:
O!:!:!
-LL

!;(:J
a:c..

W:i
~C(

RF = 5100, Unless Otherwise Specified

-3dB Bandwidth
(Vour = 0.2Vp_p, Note 6)

C(Ul

V
V

HFA1105
VSUPPLY = ±5V, Av = +1, RF = 5100, RL = 1000, Unless Otherwise Specified (Continued)

Electrical Specifications

PARAMETER

TEST CONDITIONS

Output Current (Note 6)

(NOTE 3)
TEST
LEVEL

TEMP.
(DC)

MIN

TYP

MAX

UNITS

A

25,85

50

60

-

rnA

A

-40

28

B

25

Av=-1, RL= 500

Output Short Circuit Current

-

42

rnA

90

rnA

0.08

Closed Loop Output Impedance (Note 6)

DC

B

25

Second Harmonic Distortion
(VOUT = 2Vp_p, Note 6)

10MHz

B

25

20MHz

B

25

10MHz

B

25

20MHz

B

25

-

-45

30MHz

B

25

-

-55

-

1.4

Third Harmonic Distortion
(VOUT= 2Vp_p, Note 6)
Reverse Isolation (S12, Note 6)
TRANSIENT CHARACTERISTICS

-44
-50

VOUT = 0.5Vp_p

Overshoot (Note 4)
(VOUT = 0 to 0.5V, VIN tRISE = 1ns)

B

25

B

Full

1.1

-

%

+OS
-OS

B

25

Slew Rate
(VOUT= 4Vp_p, Av = +1, +Rs= 5100)

+SR

B

25

B

Full

-SR (Note 5)

B

25

B

Full

B

25

B

Full

B

25

B

Full

-

700

B

25

-

2100

B

Full

-

1900

B

25

-

·1000

B

Full

-

900

To 0.1%

B

25

To 0.05%

B

25

To 0.02%

B

25

VIN=±2V

B

25

RL = 1500

B

RL=750

B

-SR (Note 5)

+SR

-SR (Note 5)

-

ns

%

25

+SR

ns

3

B

-

-

%

Overshoot (Note 4)
(VOUT= 0.5Vp_p, VINtRISE= 1ns)

Differential Gain
(I = 3.58MHz)

dB

-

25

VIDEO CHARACTERISTICS

dBc

-

25

B

Overdrive Recovery Time

dBc
dBc

5

B

Settling Time
(VOUT = +2V to OV step, Note 6)

-

3

+OS
-OS

Slew Rate
(VOUT= 5Vp_p, Av = -1)

0
dBc

Av = +2, RF = 5100, Unless Otherwise Specified

Rise and Fall Times

Slew Rate
(VOUT = 5Vp_p, Av = +2)

-

-48

11
1000

-

%

VlJls

975

VlJlS

650

V/JlS

580
1400
1200
800

15

-

-

VlIlS
V/IlS
V/IlS
V/IlS
V/IlS
VlIlS
VlIlS

-

V/JlS

-

ns

30

-

-

8.5

-

25

-

0.02

25

-

0.03

23

VlJlS

ns
ns
ns

Av = +2, RF = 5100, Unless Otherwise Specified

3-542

-

%
%

HFA1105
Electrical Specifications VSUPPLY =±5V, Av = +1, RF = 5100, RL = 1000, Unless Otherwise Specified (Continued)
(NOTE 3)
TEST
LEVEL

TEMP,
TYP

MAX

UNITS

RL= 1500

B

25

0.03

RL=750

B

25

0.05

-

Degrees

Power Supply Range

C

25

±4.5

-

±5.5

V

Power Supply Current

A

25

5.8

6.1

mA

A

Full

-

5.9

6.3

mA

PARAMETER

TEST CONDITIONS

Differenijal Phase
(f = 3.58MHz)

fc)

MIN

Degrees

POWER SUPPLY CHARACTERISTICS

NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterizaijon; C. Design Typical for Informaijon Only.
4. Undershoot dominates for output signal swings below GND (e.g., 0.5Vp_p), yielding a higher overshoot limit compared to the VOUT = 0
to 0.5V condition. See the "Application Information" section for details.
5. Slew rates are asymmetrical if the output swings below GND (e.g. a bipolar signal). Positive unipolar output signals have symmetric
positive and negative slew rates comparable to the +SR specification. See the "Application Information" section, and the pulse response
graphs for details.
6. See Typical Performance Curves for more information.
..J

'
S.

VSUPPLY = ±5V, RF = 5100, TA = 25°C, RL = 1000, Unless Otherwise Specified

I\.

2.0

€w

\

Ay=+1
+Rs=S10n

~

1.S

!:l

g

1.0

!;

0.5

§

I
II

'I

TIME (5na/DIV.)

FIGURE 4. LARGE SIGNAL POSITIVE PULSE RESPONSE

FIGURE 3. SMALL SIGNAL PULSE RESPONSE

2.0

r

'-'

g

0

!;

-D.5

~

§

-1.0

200

Ay .. +1
+Rs .. 510n

1\
\

I

1

\

I}

>'
S.
w

100

!:l

0

g

\

rv--

I

50

~

-1.5

!; -so

§

-100

-200
TIME (Sna/DIV.)

TIME (5na/DIV.)

FIGURE 5. LARGE SIGNAL BIPOLAR PULSE RESPONSE

FIGURE 6. SMALL SIGNAL PULSE RESPONSE

3.0

2.0
Ay=+2

2.5

~

1.5

a

1.0

~

0.5

0

0

!;

Ay,,+2

1.5

~

2.0

w

1\
""""""

I

~

-150

-2.0

€

,

Ay=+2

150

I"

1.0

ell

~

-1.0
TIME (5na/DIV.)

0.5

\

-D.5

-200

€
w

\

J

0

-150

1.S

\

\

J

I

\

I

\
\

J

-D.5

€

1.0

~
g

0.5

w

'-'

0

!;

--

§

-0.5
-1.0

\

I

1.

.1
\

I

J

~

"-/

-1.5

-1.0

-2.0

TIME (Sna/DIV.)

TIME (Sna/DIV.)

FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE

FIGURE 8. LARGE SIGNAL BIPOLAR PULSE RESPONSE

3-545

....I

-ten

za:
O!!:!
-u.

!ci:J
a:c.
W::E
~-t

HFA1105

Typical Performance Curves

VSUPPLY

=:l:£V, RF =5100, TA =25°C, RL =100n, Unless Otherwise Specified

200

3.0
Ay=+10
RF,,18oo

150

>'

100

.s
...
~
~
5

,

r
I

50

0
-50

\

\

J

§

-100

I---'

-150

Ay=+10
RF= 1800

2.5

w

I
I
I
I

1.5

i

!:i

1.0

5

0.5

~

---

r~

2.0

~

/!::::I

0

0

\
\
\
.\

-1.0

TIME (5naIDIV.)

TIME (5naIDIV.)

FIGURE 9. SMALL SIGNAL PULSE RESPONSE

FIGURE 10. LARGE SIGNAL POSITIVE PULSE RESPONSE

2.0
Ay=+10
RF=190U

1.5

~

1.0

5
50

IL

z

\
\
\

I.

0

~

iD 3
:2-

/

0.5

:..I

~

-D.5

-200

~

(Continued)

I

-0.5

J

-1.0

C

1~1!+1

VOUT = 2OOmVp.p
+Rs = 510U (+1)
+RS= OCl (-1)

II tlu.
II1vTl!"?~

0

CJ -3

~w

\

,

o :Ii
iE
90 Q

.....Ayj-1

1(J

V

-1.5

;

.~

Ay=+1

"1

-2.0
0.3

TIME (SnaIDIV.)

10

100

190

~C

270

1

o

ffi

90

!§

500

FREQUENCY (MHz)

FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE

~

3

CJ

0

~

Q

FIGURE 12. FREQUENCY RESPONSE

~=~21

VO;;;~ 200mVp.p

Ay=+2

" -,

1.0::::1

~ -3

Ay =+10
I

~a:

"'" "~f

I
VOUT = 1.5Vp.p

0111\

Ay=+5 _

VOUTi5~iil

ilill \\

o
z

Ay=+2

VOUT" 200mVp.p
RF = 510U (+2)
RF = 200U (+5)
RF = 1800(+10)
0.3

Ay=+5~

~ \
p-:~

Ay=+10

10

1111111
100

"

r

190

~\

1\

\

1\

VOUT = 200mVp.p \

o iii
90

~,

~

I IT

! ..1. 11

Sl

e.w

VOUT = 1.5Vp.p

11111

270:li

iE

~f\

10

I!I
U)

VOUT = 5Vp.pl~
100

w

180 ;;;

IN

I I II

11111
0.3

500

~

270~

IL

500

FREQUENCY (MHz)

FREQUENCY (MHz)

FIGURE 13. FREQUENCY RESPONSE

FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

3-546

HFA1105

Typical Performance Curves
iii'
~

~

Cl

II
II

3
0

Q

w

N

:::;

VSUPPLY = ±5V, RF = 5100, TA = 25°C, RL = 1000, Unless Otherwise Specified (Continued)

::Ii

~

z

Rl=1k.Q

Rl = 1000

~

A~~~2

0

~U~b

'1Ir~ ~l{
Rl=500 i1T """

M.
Ay=+1

II:

IRI

I tllJllIS;~

Ay=+2

Av=-~

VOUT = 4Vp_p (+1)
VOUT = 5Vp.p (-1, +2)
+Rs = 5100 (+1)

-3

c(

VOUT = 2oomVp_p

;111

~~

'
"
"
i
Rl=J~~~
11111

Rl=500
Rl=~OO

Rl =5000

~

LI 1IJlIl

o

90

fil

180

e.w

270

1111111
10
FREQUENCY (MHz)

0.3

200

100

FIGURE 15. FULL POWER BANDWIDTH

"N

:z:

!.
:z:

i'-- r---.

Av=+1
300

b

~

z


w

~

-70

!I!
w
Ul

11.L=+11~

VOUT= 2Vp.p

Ay

g;
z~
2§

Ay=-1

"

i
!;
§

II:

0.3

10
FREQUENCY (MHz)

75

FIGURE 18. GAIN FLATNESS

FIGURE 17. -3dB BANDWIDTH vs TEMPERATURE

~

~~

Av=+1

~ -0.05

TEMPERATURE (oC)

iii'

~600V

Thermal Resistance (Typical, Note 2)

ElJA (oCIW)

PDIP Package. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
130
170
SOIC Package. . . . . . . . . . . . . . . . . . . . . • . . . . • . . • .
Maximum Junction Temperature (Die Only) ............•... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range .. . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) . . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range. . . . . . . . . . . • . . . . . . . . . . . .. -40°C to 85°C
CAUTION: Stresses above those listed In "Absolute Maximum RaUngs' may cause permanent damage to the device. This Is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability; however, continuous (100% duty cycle)
output current must not exceed 30mA for maximum reliability.
2. 8JA is measured wnh the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLy=±5V, /10;= +1, RF= 510n, CCOMP= OpF, RL = loon, Unless Otherwise SpecHied

PARAMETER

TEST CONDITIONS

(NOTE 3)
TEST LEVEL

TEMP.
('IC)

A

25

MIN

TYP

MAX

UNITS

2

5

mV

INPUT CHARACTERISTICS

A

Full

B

Full

aVCM=±1.8V

A

25

47

50

aVCM=±1.8V

A

85

45

48

aVCM=±1.2V

A

-40

45

48

aVpS=±1.8V

A

25

50

54

aVps =±1.8V

A

85

47

50

-

aVps=±1.2V

A

-40

47

50

dB

A

25

-

-

6

15

IJ.A

A

Full

10

25

IlA

B

Full

5

60

nA/oC

0.5

1

0.8

3

IJ.AIV
IJ.AIV
IJ.AIV

Average Input Offset Voltage Drift
Input Offset Voltage Common-Mode
Rejection Ratio

Input Offset Voltage Power Supply
Rejection Ratio

Non-Inverting Input Bias Current

Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity

Non-Inverting Input Resistance

-

8

mV

1

10

IlVPC

~:::i

-

dB

W:e

-

A

25

A

85

aVpS= ±1.2V

A

-40

-

0.8

3

aVCM=±1.8V

A

25

0.8

1.2

aVCM=±1.8V

A

85

0.5

0.8

aVCM=±1.2V

A

-40

0.5

0.8

-

A

25

2

7.5

A

Full

B

Full

aVCM=±1.8V

A

25

aVCM= ±1.8V

A

85

aVCM=±1.2V

A

-40

aVpS =±1.8V

A

25

aVpS= ±1.8V

A

85

aVpS=±1.2V

A

-40

3-551

dB
dB
dB

aVpS= ±1.8V

Inverting Input Bias Current Drift

Inverting Input Bias Current Power
Supply Sensitivity

-

dB

Me
Me
Me

-

5

15

IlA

60

200

nAfDC

3

6

IJ.AIV

4

8

IJ.AIV

-

4

8

IJ.AIV

2

5

IJ.AIV

4

8

IJ.AIV

4

8

IlAIV

-

CCCl)
Za:
O!!:!
-IL

3

aVpS= ±1.8V

Inverting Input Bias Current

Inverting Input Bias Current
Common-Mode Sensitivity

...I

-

Input Offset Voltage

IlA

a:c..

~CC

HFA1106
Electrical Specifications

VSUPPLY = ±5V, Av = + 1, RF = 5100, CCOMP = OpF, RL = 1000, Unless Otherwise Specified (Continued)
(NOTE 3)
TEST LEVEL

TEMP.
~C)

Inverting Input Resistance

C

25

Input Capacitance

C

Input Voltage Common Mode Range
(Implied byVIO CMRR, +RIN' and -IBIAS
CMS Tests)

PARAMETER

TEST CONDITIONS

Input Noise Voltage Density

MIN

TYP
60

0

25

-

1.6

pF

A

25,85

±1.8

±2.4

V

A

-40

±1.2

±1.7

V

-

3.5

-

nVNHz

2.5

-

pANHz

f = 100kHz

B

25

Non-Inverting Input Noise Current Density f = 100kHz

B

25

Inverting Input Noise Current Density

f = 100kHz

B

25

Av=-l

C

25

-

MAX

UNITS

20

pANHz

500

kO

TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain

AC CHARACTERISTICS Av = +2, RF = 1000, RCOMP = 510, Unless Otherwise Specified
-3dB Bandwidth
(Av = +1, RF = 1500, VOUT = 0.2Vp_p)

-3dB Bandwidth
(Av = +2, VOUT = 0.2Vp_p)

±0.1dB Flat Bandwidth
(Av= +1, RF= 1500, VOUT=0.2Vp.p)

±O.ldB Flat Bandwidth
(Av = +2, VOUT = O.2Vp_p)

MHz

65

-

25

40

-

MHz

25

13

17

B

25

60

100

CC=2pF

B

25

15

30

Cc=5pF

B

25

11

14

A

Full

1

-

Cc=OpF

B

25

250

315

CC=2pF

B

25

140

170

CC=5pF

B

25

65

80

CC=OpF

B

25

185

245

CC=2pF

B

25

110

140

Cc=5pF

B

25

55

70

Cc=OpF

B

25

45

Cc=2pF

B

25

CC=5pF

B

CC=OpF

Minimum Stable Gain
OUTPUT CHARACTERISTICS
Output Voltage Swing

Av=-l, RF=5100

A

25

±3

±3.4

A

Full

±2.8

±3
60

Av = -1, RL = 500,
RF=5100

A

25,85

50

A

-40

28

42

Closed Loop Output Impedance

DC

B

25

0.07

Output Short Circuit Current

Av=-l

B

25

-

Third Harmonic Distortion
(10MHz, VOUT = 2Vp_p)

Second Harmonic Distortion
(20MHz, VOUT = 2Vp_p)

Third Harmonic Distortion
(20MHz, VOUT = 2Vp_p)

,

MHz
MHz
MHz
MHz
MHz

MHz
MHz
MHz
MHz
VIV

Av = +2, RF = 1000, RCOMP = 510, Unless Otherwise Specified

Output Current

Second Harmonic Distortion
(10MHz, VOUT = 2Vp_p)

MHz

90

CC=OpF

B

25

-45

-53

Cc=2pF

B

25

-42

-48

Cc=5pF

B

25

-38

-44

CC=OpF

B

25

-50

-57

Cc=2pF

B

25

-48

-56

Cc=5pF

B

25

-48

-56

Cc=OpF

B

25

-42

-46

Cc=2pF

B

25

-38

-42

CC=5pF

B

25

-34

-38

CC=OpF

B

25

-46

-57

CC=2pF

B

25

-52

-57

CC=5pF

B

25

-50

-57

3-552

-

-

V
V
rnA
rnA
0
rnA

dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc

HFA1106
Electrical Specifications

VSUPPLY = ±5V, Av = + 1, RF = 510Q, CCOMP = OpF, RL = 1OOQ, Unless Otherwise SpecWied (Continued)

PARAMETER
TRANSIENT CHARACTERISTICS

TEST CONDITIONS

(NOTE 3)
TEST LEVEL

TEMP.
('IC)

MIN

TYP

MAX

UNITS

Av = +2, RF = 100Q, RCOMP = 51Q, Unless Otherwise Specified

Rise and Fall Times
(VOUT = 0.5Vp_p, Av = +1, RF = 150Q)

Rise and Fall Times
(VOUT = 0.5Vp_p, Av = +2)

B

25

CC=2pF

B

25

CC=5pF

B

25

CC=OpF

B

25

Cc=2pF

B

25

CC=5pF

B

25

B

25

B

25

VOUT = OV to 2V

B

25

VOUT = 250mVp_p

B

25

VOUT=2Vp_p

B

25

VOUT = OV to 2V

B

25

+SR, Cc=OpF

B

25

580

680

Overshoot (Note 4)
VOUT = 250mVp_p
(Av = + 1, RF = 150Q, VIN tRISE = 2.5ns)
VOUT=2Vp_p

Overshoot (Note 4)
(Av = +2, VIN tRISE = 2.5ns)

Slew Rate
(VOUT = 4Vp_p, Av = +1, RF = 150Q)

Slew Rate
(VOUT = 5Vp_p, Av = +2)

Settling Time
(VOUT = +2V to OV Step,
Cc = OpF to 5pF)
Overdrive Reoovery Time

-

Cc=OpF

-

2.6

2.9

ns

3.7

4.2

ns

5.2

6.2

ns

2.7

3.2

ns

3.9

4.4

ns

5.9

6.9

ns

1.5

4

%

6

10

%

4

7.5

%

2

5

%

6.5

12

%

2.5

7.5

-SR,Cc=OpF

B

25

400

545

+SR, CC=2pF

B

25

470

530

-SR,CC=2pF

B

25

300

410

+SR,CC=5pF

B

25

320

365

-SR, Cc=5pF

B

25

200

300

%

-

V/IlS

-

V/IlS

-

-

V/IlS

V/IlS

VlIlS
V/IlS

+SR, Cc=OpF

B

25

750

910

-SR,CC=OpF

J3

25

500

720

+SR,Cc=2pF

B

25

550

730

-SR,CC=2pF

B

25

350

520

+SR, CC=5pF

B

25

380

485

-SR, CC=5pF

B

25

250

375

-

To 0.1%

B

25

26

35

ns

To 0.05%

B

25

33

43

ns

To 0.02%

B

25

49

75

ns

VIN=±2V

B

25

8.5

-

ns

0.02

-

%

-

Degrees

-

-

-

V/IlS
V/IlS
V/IlS
VlIlS
V/IlS
V/IlS

VIDEO CHARACTERISTICS Av = +2, RF = 100Q, RCOMP = 51Q, Unless Otherwise Specified

-

CC=OpF

B

25

CC=5pF

B

25

Cc=OpF

B

25

Cc=5pF

B

25

Power Supply Range

C

25

±4.5

Power Supply Current

A

25

-

A

Full

Differential Gain
(f = 3.58MHz, RL = 150Q)
Differential Phase
(f = 3.58MHz, RL = 150Q)

0.02
0.05
0.07

%

Degrees

POWER SUPPLY CHARACTERISTICS

-

±5.5

V

5.8

6.1

mA

5.9

6.3

mA

NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. Undershoot dominates for output signal swings below GND (e.g. 2Vp_p) yielding a higher overshoot limit compared to the VOUT = OV to
2V condition.

3-553

....

-w

80

!:i

.s>-w

1

~

5
~
0

::;)

·40
·80

.-J

~
0

'--

rb

0
-40

1.2

""'=+1
Cc = 2pF, RF = 1500

0.4

FIGURE 18. SMALL SIGNAL PULSE RESPONSE

1.2

,
\

,..

0.8

E

0.8

w
~

0.4

!:i

~

~

0

5~

.0.4

o

.0.8
·1.2

\

\

r--I

'--

""'=+2
Cc = 2pF, RF = 1000

\
h

0

~

.0.4

o

.0.8

TIME (10nslOIV.)

FIGURE 19. LARGE SIGNAL PULSE RESPONSE

FIGURE 20. LARGE SIGNAL OUTPUT VOLTAGE

AV=+l

3

Cc = 2pF, RF = 1500

2

V

w 1
~

!:i

~ 0

~

·1

::;)

o

.2

I
'/

3

\
L

I

'--

...J

·1.2

TIME (10nslOIV.)

E

'-

~

TIME (10nslOlV.)

FIGURE 17. SMALL SIGNAL PULSE RESPONSE

~

\

J

-80

TIME (10nslOIV.)

w
CI

~

·120

·120

E

(Continued)

~

40

~

I-

,.

80

!:i

0

~

lOon, Unless Otherwise Specified
""'=+2
Cc = 2pF, RF = 1000

120

I

40

~

VSUPPLY '" ±5V, TA = 2SoC, RL =

,

E

2

w
~

1

~

0

~

·1

!:i

1\

\.

~

·2

""'=+2
Cc = 2pF, RF = 1000

I
'/

\,
LJ

J

\

\

-3
TIME (10nslOIV.)

TIME (10nslOIV.)

FIGURE 21. LARGE SIGNAL PULSE RESPONSE

FIGURE 22. LARGE SIGNAL PULSE RESPONSE

3·558

HFA1106

Typical Performance Curves
Cc =2pF
VOUT = 200mVp_p
I
GAIN

VSUPPLY

~ Av=+l

AV=+~~
-'

Av=+l -

1"'1

~

,

JUt
10
FREQUENCY (MHz)

90

~~

135

""

1\

13

I

W

f

U)

180

\;

225
500

100

10
100
FREQUENCY (MHz)

FIGURE 23. FREQUENCY RESPONSE

3

0.1

iii'

""'- ~

;(

10
100
FREQUENCY (MHz)

=

=

AV +1, Cc 2pF, RF = 1500
VOUT = 2OOmVp_p

500

..I

~I/)

Za:
O!!:!
-II.

........ ...

,,~

~

-0.3

!cc:;
a:c..

..

W:E

~~

I'

10
FREQUENCY (MHz)

100

500

FIGURE 26. GAIN FLATNESS (12 UNITS, 4 RUNS) ,

FIGURE 25. FREQUENCY RESPONSE (12 UNITS, 4 RUNS)

Av = +2, Cc = 2pF, RF = 1000
VOUT = 200mVp_p

Av = +2, Cc = 2pF, RF = 1000
VOUT = 200mVp_p

~

~

,

....

,

o

13

\

100

~I.,

45
w
II:
90 CI

"-

"
10
FREQUENCY (MHz)

r-

CI -0.2

~

-

0

i' -0.1
iii.

-9

PHASE

500

FIGURE 24. GAIN FLATNESS

Av = +1, Cc = 2pF, RF = 1500
VOUT = 200mVp_p

GAIN

",,-

Av=+l

Av=+~

o
45

Av=~

II

~

~

(Continued)

II

CC=2pF
Vour = 200mVp..p

11111
PHASE

=±5V, TA =25°C, RL =1000, Unless Otherwise Specified

135

~

III

~

180

f

225

500

10
FREQUENCY (MHz)

FIGURE 27. FREQUENCY RESPONSE (12 UNITS, 4 RUNS)

100

FIGURE 28. GAIN FLATNESS (12 UNITS, 4 RUNS)

3-559

500

HFA1106
Typical Performance Curves

Ay=+l
Cc = 5pF, RF = 1500

120

,

80

~

J

w 40

~

;.J

0

~

!;

-40

S

-80

0

·120

=

VSUPPLY ±5V, TA

=2S0C, RL = loon, Unless Otherwise Specified
Ay=+2
Cc = 5pF, RF = loon

120

/,

t

·40

I

\

-80

J

C!

i!i

~
~

l'
I

1\

'--

f-.I

0

!;

0

l

I

w 40

.I

~

·120

TIME (10nsIDlV.)

FIGURE 30. SMALL SIGNAL PULSE RESPONSE

Ay=+l

1.2 Cc = 5pF, RF = 1500
0.8

W 0.4
!j
~

1.2

I'

\

0

E
w

\

~

0

!;

S

-4.4

.1.2

0.4

\

J

I

S
0

\

r

-4.8

'-

.1.2

TIME (10nsIDlV.)

E

2

w

1

TIME (10nsIDlV.)

~

!;

3

1\
\.
'\

I(

;.J

~

0

I!:

·1

5

.2

FIGURE 32. LARGE SIGNAL PULSE RESPONSE

Ay=+l
Cc = 5pF, RF = 1500

/'

1

J

,\
\

.1

1

·0.4

FIGURE 31. LARGE SIGNAL PULSE 'RESPONSE

3

,

Ay=+2
Cc = 5pF, RF = 1000

0.8

C!

~

!;

0-4.8

-

TIME (10nsIDIV.)

FIGURE 29. SMALL SIGNAL PULSE RESPONSE

E

,

,.

80

~

(Continued)

E

Ay=+2
Cc = 5pF, RF = 1000

2

/

w 1

~

"'-

~

0

~

·1

o

.2

-3

\

I(

J-'

,\
"

I\-

-3

TIME (10nsIDlV.)

TIME (10nsIDlV.)

FIGURE 33. LARGE SIGNAL PULSE RESPONSE

FIGURE 34. LARGE SIGNAL PULSE RESPONSE

3·560

HFA1106
Typical Performance Curves

VSUPPLY

=±5V, TA =25°C, RL =1000, Unless Otherwise Specified

CC=5pF
VOUT = 200mVp_p

iii
:!!.
z
~

I"""~

GAIN

~=+1-

Av=+l

~
Av=:;-"

1111
1111
10
FREQUENCY (MHz)

0
~Av=+l

t:!

;;l-0.2

IIII~

r-,...

CC·5pF
VOUT = 200mVp_p

~ -0.1

Av=+2
PHASE

0.1

~ ~iii

~ ~;

~ -0.3

:.1

z

w

1/1

180 ~

225

100

Av=+2~

:IE

o

(Continued}

,\

D.

10
100
FREQUENCY (MHz)

500

FIGURE 35. FREQUENCY RESPONSE

500

FIGURE 36. GAIN FLATNESS

Av=+l
Cc = 5pF, RF = 1500
VOUT = 200mVp_p

Av=+l

0.1

..J

cr:U)

Cc = 5pF, RF .. 1500

Za::
O!!:!
-I.&.

VOUT = 2OOmVp_p

iii

- ....

Z
" -0.1

'"'" "'
.........

0

:cCI -0.2

o

-0.3

4Sm

I'

'-.,

5l

135

e.

W::::E
~cr:

,

\

~

90

ti:i
a:: a.

III

180 ~

D.

225·
10
100
FREQUENCY (MHz)

10
FREQUENCY (MHz)

500

Ay = +2, Cc = SpF, RF = 1000
VOUT = 200mVp_p

iii
:!!.

0.1

j!;

~

i'o

t-~

500

FIGURE 38. GAIN FLATNESS (12 UNITS, 4 RUNS)

FIGURE 37. FREQUENCY RESPONSE (12 UNITS, 4 RUNS)

-

100

0

~ -0.1
t:!
;

",
"'" ,~-

-0.2

~ -0.3

~

z

Ay = +2, Cc = 5pF, RF = 1000
VOUT = 200mVp_p

~

",

iIII...

l\
10
FREQUENCY (MHz)

100

10
100
FREQUENCY (MHz)

FIGURE 39. FREQUENCY RESPONSE (12 UNITS, 4 RUNS)

FIGURE 40. GAIN FLATNESS (12 UNITS, 4 RUNS)

3-561

500

HFA1106
Typical Performance Curves

1\1
\:t

~ 0.15
II:

~_

I

VSUPPLY = ±5V, TA = 2S0C, RL = 100'1, Unless Otherwise Specified (Continued)

4.0

I

Av=-l

Av=+2
RF= loon
Vour=2V

·CC=2pF

,

E

ccl~l~ -.

0.05

III

+VOUT

III

!:i

g
!:i...

i"""
RL= son

~

~ ~.o:
UI

3.5
I-VOUTI
3.0

......

-'-

+VOUT

\

...;:,

~.1

0

o

10

20

30

40

so 60
TIME (ns)

70

60

90

2.5

2
-100

100

o

-so

6.0

,/

!it 5.9
III

./

5.8

U

~

8:

~

5.7

V

;:,
UI

5.6
5.5

100

FIGURE 42. OUTPUT VOLTAGE vs TEMPERATURE

6.1

II:

so

TEMPERATURE I"C)

FIGURE 41. SETTLING RESPONSE

§

I..--

RL= loon

I-VOUTI

·~V

0.1

3.5

4.0

'/

V

io"'""

4.5

5.0

5.5

6.0

6.5

7.0

7.5

SUPPLY VOLTAGE (±V)

FIGURE 43. SUPPLY CURRENT vs SUPPLY VOLTAGE

3-562

150

HFA1106
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:
Type: Nitride
Thickness: 4kA ±O.5kA

59 mils x 58.2 mils x 19 mils
1500J.lm x 1480J.lm x 483J.lm

TRANSISTOR COUNT:

METALLIZATION:

75

Type: Metal 1: AICu(2%)fTiW
Thickness: Metal 1: 8kA ±O.4kA

SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kA ±O.8kA

Floating
(Recommend Connection to

V-I

Metallization Mask Layout
HFA1106

.:. c:: c

•

..J

«en
Za:

COMP

-IN

O!!:!
-u.,

!;:::::i
a: a..
w:=
~«

OUT

+IN

v-

3-563

NC

Hz, Low Power, Current Feedback
Operational Amplifiers
Features

Description

.• Wide - 3dB Bandwidth (Av

=+2) •••••••.•••• 550MHz

.• Gain Flatness (To 250M Hz) .................. 0.5dB
• Very Fast Slew Rate (Av

=+2) ••.•••..•.•.. 1200Vl!1s

• High Input Impedance ..................... 1.7MQ
• Differential GainlPhase .••••...• 0.02%10.02 Degrees
• Low Supply Current •••.•.•..•••••••••••••• 10mA
• Fast Output Enable/Disable (HFA1149)

Applications
• Professional Video Processing
• Video Switchers and Routers
• Medical Imaging
• PC Multimedia Systems

The HFA1109, and HFA1149 are high speed, low power,
current feedback amplifiers built with Harris' proprietary
complementary bipolar UHF-1 process. These amplifiers
feature a unique combination of power and performance
specifically tailored for video applications.
The HFA1109 is a standard pinout op amp. It is a higher
performance, drop-in replacement (no feedback resistor
change required) for the CLC409.
The HFA1149 incorporates an output disable pin which is
TTUCMOS compatible, and user programmable for polarity
(active high or low). This feature eliminates the inverter
required between amplifiers in multiplexer configurations.
The ultra-fast (10ns) enable and disable times make the
HFA1149 the obvious choice for pixel switching and other
high speed multiplexing applications. The HFA 1149 is a high
performance, pin compatible upgrade for the popular HA-5020
and HFA1145, as well as the CLC410.

Ordering Information

• Video Pixel Switching (HFA1149)

PART NUMBER
(BRAND)

TEMP.
RANGEfc)

• Flash Converter Drivers

HFA11091p, HFA11491P

-401085

8LdPDIP

E8.3

• RadarnF Processing

HFA1109IB, HFA1149IB
(H11091, H11491)

-401085

8 LdSOIC

M8.15

• Video Distribution Amplifiers

HFA11XXEVAL

PKG.
NO.

PACKAGE

DIP Evaluation Board for High Speed Op
Amps

Pinouts
HFA1109 (PDIP, SOIC)
TOP VIEW

HFA1149 PIN DESCRIPTIONS
PIN NAME

DESCRIPTION

Threshold Set

Optional Logic Thresold Sel Maintains Disable Pin
TTL Compatibility with Asymmetrical Supplies (e.g.,
+10V,OV).

Polarity Set

Defines Polarity of Disable Input. High or Aoating
Selects Active Low Disable O.e., 15iS).

15iS/DIS

TTL Compatible Disable Input. Output is Driven 10 a
True Hi-Z Slala When Active. Polarity depends on
stata of Polarity Set Pin.

OPAMP

HFA1149 (PDIP, SOIC)
TOP VIEW

HFA1149 DISABLE FUNCTIONALITY
THRESHOLD SET 1

5 POLARITY SET
OP AMP WITH DISABLE

POLARITY SET
(PIN 5)

DISABLE (PIN 8)

High or Float

H'igh or Float

Enabled

High or Float

Low

Disabled

Low

High or Aoat

Disabled

Low

Low

Enabled

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporation 1996

3-564

OUTPUT (PIN 6)

File Number

4019.1

HFA1110
750MHz, Low Distortion
Unity Gain, Closed Loop Buffer

November 1996

Features

Description

o

Wide -3dB Bandwidth •••.•••••••••.•••..• 750MHz

o

Very Fast Slew Rate ••••...••••...••.••••

o

Fast Settling Time (0.2%) .................... 7ns

o

High Output Current ....................... 60mA

o

Fixed Gain of +1

o

Gain Flatness (100MHz) •••..•••.••••.•••••• O.03dB

o

Differential Phase. • • • • • • • . . • • • • • • •. 0.025 Degrees

1300V/~

o

Differential Gain. • • • • • • • .. .. • • • • .. • • • • • • .. 0.04%

o

3rd Harmonic Distortion (50MHz) ..•••.•...• -8OdBc

o

3rd Order Intercept (100MHz) •••••••••••••• 30dBm

The HFA 1110 is a unity gain closed loop buffer that achieves
-3dB bandwidth of 750MHz, while offering excellent video
performance and low distortion. Manufactured on Harris'
proprietary complementary bipolar UHF-1 process, the
HFA 1110 also offers very fast slew rate, and high output
current. It is one more example of Harris' intent to enhance
its leadership position in products for high speed signal
processing applications.
The HFA1110's settling time of 11ns to 0.1%, low distortion
and ability to drive capacitive loads make it an ideal flash AID
driver.
The HFA1110 is an enhanced, pin compatible upgrade for
the AD9620, AD9630, CLC110, EL2072, BUF600 and
BUF601.
For buffer applications requiring a standard op amp pinout,
or selectable gain (-1, +1, +2), see the HFA1112 data sheet.
For output limiting see the HFA 1113 datasheet.

Applications

For military grade product please refer to the HFA 1110/883
data sheet.

o

Video Switching and Routing

o

RFnF Processors

o

Driving Flash AID Converters

o

High-Speed Communications

o

Impedance Transformation

HFA1110lJ

-40 to 85

8 LdCERDIP

o

Line Driving

HFA1110lP

-40 to 85

8Ld PDIP

E8.3

o

Radar Systems

HFA1110lB
(H11101)

-40 to 85

8LdSOlC

M8.15

Ordering Information
PART NUMBER
(BRAND)

HFA1110EVAL

Pinout

TEMP.
RANGE (DC)

PKG.
NO.

PACKAGE

F8.3A

High Speed Buffer DIP Evaluation Board

Pin Descriptions
HFA1110
(PDIP, CERDIP, SOIC)
TOP VIEW

'.[[~~om

II
NC II
IN E

OPTv+

_>.

~ NC
~ OPTv·
~v.

NAME

PIN
NUMBER

V+

1

Positive Supply

OptV+

2

Optional Positive Supply

NC

3

No Connection

IN

4

Input

V·

5

Negative Supply

OptV·

6

Optional Negative Supply

NC

7

No Connection

OUT

8

Output

CAUTION: These devices are sensitive to electrostatiC discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3·565

DESCRIPTION

File Number

2944.5

..J

c(1n

Za:

O!:!:!
-u..

!i::::i
a: 0..
w:s
~c(

HFA1110
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- .•.........................• 12V
DC Input Voltage .•..•.•..••......••.....•....... VSUPPLY
Output Current. • . . . . . . . . . . • • • • . • . . . . . . . . . . • . • • • • •. 60mA

Thermal Resistance (Typical, Note 1)
9JA (oclW) 9JC fclW)
CERDIP Package................
120
35
PDIP Package. . . . . . . • . . . . . . . . . . .
98
N/A
SOIC Package. . . . . . • . • • • . • • . . . . .
158
N/A
Maximum Junction Temperature (Ceramic Package) ....•.... 175°C
Maximum Junction Temperature (Plastic Package) .•...... 150°C
Maximum Storage Temperature Range • . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . .. . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .• _40°C to 85°C

CAUTION: StressBS above /hosellsteel In "Absolute Maximum RaUngs" may cause permanent damage to the device. This is 8 stress only raUng and operation
of the device at thBSe or any other conditions above those indicateel In the operational sections of this specification is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±5V, RL = 1000, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

TEMPfc)J

MIN

TYP

1

MAX

J

UNITS

INPUT CHARACTERISTICS
Output Offset Voltage (Note 2)

25

Output Offset Voltage Drift
PSRR

Input Noise Voltage (Note 2)

100kHz

Input Noise Current (Note 2)

100kHz

8

25

-

35

mV

-

JlvtDc

Full

-

10

Full

25

39

45

Full

35

25

-

14

Full

-

Input Resistance

25

25

50

Input Capacitance

25

-

2

25

Input Bias Current (Note 2)

25

-

-

51

-

10

40

-

65

-

mV

dB
dB
nVNFiZ
pANHz

JlA
JlA
kO
pF

TRANSFER CHARACTERISTICS
Gain

DC Non-Linearity (Note 2)

VOUT=2Vp_p

±2V Full Scale

25

0.980

0.990

1.02

VN

Full

0.975

1.025

VN

25

-

0.003

-

%

-

±V

OUTPUT CHARACTERISTICS
Output Voltage (Note 2)

25

3.0

3.3

Full

2.5

3.0

25,85

50

60

-40

35

50

-

Supply Voltage Range

Full

4.5

Supply Current (Note 2)

25

Output Current (Note 2)

RL=500

±V
rnA
mA

POWER SUPPLY CHARACTERISTICS

Full

-

-

5.5

±V

21

26

rnA

-

33

mA

AC CHARACTERISTICS
-3dB Bandwidth (Note 2)

VOUT = 0.2Vp_p

25

Slew Rate

VOUT= 5Vp_p

25

Full Power Bandwidth (Note 2)

VOUT= 4Vp_p

25

Gain Flatness (Note 2)

To 100MHz

25

T030MHz

25

Linear Phase Deviation (Note 2)

DC to 100MHz

25

2nd Harmonic Distortion (Note 2)

50MHz, VOUT = 2Vp_p

25

3·566

-

-

750
1300
150
±C.03
±C.Ol
±C.3

-60

-

-

MHz

V/JlS
MHz
dB
dB
Degrees
dBc

HFA1110
Electrical Specifications

VSUPPLY = ±!jV, RL = 1000, Unless Otherwise Specified (Continued)

PARAMETER

TEMP (oC)

TEST CONDITIONS

3rd Harmonic Distortion (Note 2)

50MHz, VOUT = 2Vp_p

25

3rd Order Intercept (Note 2)

100MHz

25

-1 dB Gain Compression

100MHz

Reverse Gain (S12, Note 2)

100MHz, VOUT= 1Vp_p

TYP

MIN

MAX

UNITS

-SO

dBc

30

dBm

25

14

dBm

25

-60

dB

-

TRANSIENT RESPONSE
Rise Time

VOUT = 0.5V Step

25

0.5

-

ns

Overshoot (Note 2)

VOUT = 1.0V Step, Input Signal
Rise/Fall = 1ns

25

2.5

-

%

0.2% Settling Time (Note 2)

VOUT = 1V to OV

25

0.1% Settling Time (Note 2)

VOUT = 1V to OV

25

-

ns

-

ns

-

Degrees

-

7
11

25

-

15

Differential Gain

3.5SMHz, RL = 750

25

-

0.04

Differential Phase

3.5BMHz, RL = 750

25

-

0.025

Overdrive Recovery Time

ns

%

NOTE:
2. See Typical Performance Curves for more information.

Application Information

...I

 19
U)

L'
./'

6
7
8
9
TOTAL SUPPLY VOLTAGE (V+ - V-, V)

~
II:
II:

~

9
8
7
6
5 ./'
5

)~

24

,

17
-60

""

-40

-20

0

20

40

60

80

100

TEMPERATURE (OC)

FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 18. SUPPLY CURRENT vs TEMPERATURE

3-570

120

HFA1110
Typical Performance Curves

l

!zw
a:
a:
::)
0
III

S

CD

32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
-60

VSUPPLY = ±5V, TA = 25°C, RL = 1000, Unless Otherwise SpecHied (Continued)

10

>-

~
~

S

1/

w
CJ

~

./

~

./

Iii

./

, ...
.,

If
...

./

"",.
-40

-20

0

20

40

60

80

100

9.6

"

9.4
9.2
9
8.6

...5

8.4

"

~

8.2

"

~

-40

-20

0

TEMPERATURE (oC)

FIGURE 19. BIAS CURRENT VB TEMPERATURE

3.8

w

CJ

~

If>:

3.4

~

...

3.2

5
0

3.1

20
~
60
TEMPERATURE (oc)

.....
n

100

120

200

I\.

II I I I I I
3.5 r- +YOUT (RL = lOOn)
3.3

.............

100

3.6

~

"

FIGURE 20. OFFSET VOLTAGE VB TEMPERATURE

3.7

~

..........

8
7.8

120

~

8.8

0

50

~

9.8

+YOUT (RL = Son)

I-YOUT I(RL = 100m'

r

!:l

~i""

~

I-YOUT I(RL = son)

s.
w
i
~

80

60

,""-

~

0
Z

20

2.9
~

~

0

20

~

~

n

~

~

100

TEMPERATURE (oc)

FIGURE 21. OUTPUT VOLTAGE

VB

80

--r--

IN,

~

lK

8

III

~N'I
10K

o
lOOK

FIGURE 22. INPUT NOISE VB FREQUENCY

3-571

~

~ ~

FREQUENCY (Hz)

TEMPERATURE

t
a:

o

2.8
~

120

~

r--ro

UI

!II

3

160

..J

100

2.0

Ay=-1

1.5

.A

g
~

50

!j

g

0

!;

-50

0-100
-150

-,

S

-50

0.100

~

1

!;
S

-50

!:i

IV"

~ 0.5
!j
g 0

!j

I:::l

IA

1.0

~

~IV

~ 1.0

t!l

0.5

~

0

~

~ ~.5
!:i

""

Ay=-1

0-1.0

~I\

-1.5
-2.0

-200
TIME (5nsIDIY.)

TIME (5nsIDIV.)

FIGURE 7. SMALL SIGNAL PULSE RESPONSE

FIGURE 8. LARGE SIGNAl,. PULSE RESPONSE

3-578

HFA1112
Typical Performance Curves
iii 6

VOUT = 200mVp_p

'0

i'3
~

Ay= +1

GAIN

~-6
II:

0-9

Jt--.

Ay = +2, YOUT = 2oomVp.p

l!UV

II

0

c
~ -3

VSUPPLY = ±5V, TA = 25°C, RL = 100Q, Unless Otherwise Specified (Continued)

i-'
po

Ay=-1

II 1

1111 Ay=+2

PHASE

~

z

Ay=+:?' /
Ay=-1'
Ay=+1

9

m
II:

o

~

~

-90

W

-180

...:z:

/

-270

II I I

~6

GAIN

3:: 3

~

I

~

RL =50n
RL=100n Y
RL=1kn ....

0

'11111

~

fil

-360 ~

I

II:

I

o
Z

10
FREQUENCY (MHz)

100

0.3

1000

FIGURE 9. FREQUENCY RESPONSE

6

Ay = +1, VOUT = 2oomVp.p

3

i

0

3:: -3

11111
GAIN

~-6

6

I

RL= son

11111111

I

10
100
FREQUENCY (MHz)

1,.

W

'1 RL=1kn"

:z:

-360'"

10
100
FREQUENCY (MHz)

0.3

6

1Vp_p

Ay =+1

iii 3
~ 0

~

GAIN
4.0Vp_p

-6

III 2.SVp.p'"

o ~

~

11111
4.0Vp.p
2.SVp.p

iii
;

o

~

hliili/

II
II

l§

~

-180
1000

~

VOUT ,,4Vp.p /
VOUT = 2.5Vp-p
YOUTz 1Vp.p

,,~
VOUT = 4Vp.p

V
VOUT = 2.SVp_(- V

-2701l!

ltI -360~

I ~Oilil;~P-P

11111
1000

0.3

FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

~

I I I1111 I./"

-180~
~II

-80 w

lJJ..I.UH'"

PHASE

-90 w

i-""
~

11111111

II
GAIN

CI -3

10
100
FREQUENCY (MHz)

180

90

FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

11111

PHASE

0.3

RL=500

-270~

1000

Av=+2

11111
11111

i""""I ...

W

3

o

PHASE

-180B

FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

z 6

I II
RL= 100n

·90

RL = son _

~

RL= 1oon-:::
RL=son

-6

o ~
W
l§

.......
I I R =1kn

~

GAIN

L
j;&

-9

0.3

w

-270~

rtli-360'":z:
1000

RL=1kn

11111

I

3::-3

~

RL=100n _

iii 9

Ay = -1, VOUT = 200mVp_p

~o

RL= 100n

I I I

PHASE

~

~

10
100
FREQUENCY (MHz)

3

-9

12

RL=50nRL=1kn

II!
fll

-180 B

FIGURE 10. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

RL=1~ ~
.il

-80

RL=100n ....- ~~

~

0.3

o ~

~

PHASE

1

10
100
FREQUENCY (MHz)

0

-9o

~

II!

CI

-1 80~

-270~

-360iE

100

FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

3-579

HFA1112
Typical Performance Curves
6

Ay=-1

=±5V, TA =2SoC, RL =1000, Unless Otherwise Specified

VSUPPLY

VOUT" 2.5Vp.p

J-

15

VOUTtI4~~i~ .I

GAIN

(Continued)

VoUT=5Vp.p

12

9

VOUT-1Vp.p

PHASE

rVOUT-4Vp_p
VOUT .. 2.5Vp.p . -

III

...

90

o

VOUT - 1Vp.p ........

10
100
FREQUENCY (MHz)

II!

CI

-110

~

IE

-12
-15
0.3

1000

10
FREQUENCY (MHz)

600

0.30

--

I
Ay=-1

1750

iii'

.........

~

0.15

III

0.10

Q

i

650

II:

0

600

---

Av=+2
550
500

-so

-25

~

0
25
50
75
TEMPERATURE (oC)

1/

0.25

z

~

Ay=+1 /

0.05

.,./

0

100

-D.15

125

!

-

Ay=-1

.,.,..

~

I

""-

""

Av=+1

~-3

Q

-4

-5

o

15

100

FIGURE 18. GAIN FLATNESS

Ay

~ +2, JOUT ~ 2V

0.6

-2

-6

III

10
FREQUENCY (MHz)

1

,

z-1
Q

I

Ay=:\

4

........
0

I

/

-D.10

3

1

Ay=-}

-D.05

FIGURE 17. -3dB BANDWIDTH VB TEMPERATURE

2

I

:!!. 0.20

700

1

~

1000

0.35
Ay=I+1

850

IIIII:

100

FIGURE 16. FULL POWER BANDWIDTH

900

Ii)

!-

Ay=+1

FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

~

ri

Ay=-1
Ay=+'1:

e.

-180

111111
0.3

./'

180 Ii)

30

45

l
~
II:
III

Ay=+2

CI

~

r'\.
~

1/1

"

0.4
0.2
0.1
0
-D.1
-0.2
-0.4
-0.6

-2

80 75
90 105 120 135 150
FREQUENCY (MHz)

FIGURE 19. DEVIATION FROM LINEAR PHASE

3

8

13

18

23
28
TIME (ns)

33

38

FIGURE 20. SETTLING RESPONSE

3-580

43

48

HFA1112

Typical Performance Curves

VSUPPLY = ±5V, TA = 25°C, RL = 1000, Unless Otherwise Specified (Continued)

-24

•

-36
Ay=+l_

-42

1'-...

iii'-48
:2-

z

~

-54

~-60 -

" ~"A """""

-72

-

r

o

40

-24

z-42

60

80 100 120 140
FREQUENCY (MHz)

180

f

20

... ...

~

III
If

14

~ 12

u

!

10

!it

8

1"'-

r---

I:

-

AyJ+2~

-

45 ~

o f

~

'/1

Ay=+l
I

Ay=-l

I

280 370 480 550 840 730 820 910 1000
FREQUENCY (MHz)

FIGURE 22. HIGH FREQUENCY REVERSE ISOLATION (S12)

..J
<11)

... ...

""

16

~V

100 190

FIGURE 21. LOW FREQUENCY REVERSE ISOLATION (S12)

:2- 18

-48

-60 ~

180 200

"

;~ / '

-54

I

90

GAIN

'D

""
'"

Ay=+l-

~

~~

200

W:5

~<

~f.v=+~ ;:--.....

'" .\.

\

100

Za:
O!!:!
-u..
!ci::::i
a: a.

Ay=-l

........

~

~:

"'"

300
FREQUENCY (MHz)

I'.....

400

O~--~----~--~----~--~~--~

100

500

FIGURE 23. 1dB GAIN COMPRESSION va FREQUENCY

200
300
FREQUENCY (MHz)

400

FIGURE 24. 3rd ORDER INTERMODULATION INTERCEPT va
FREQUENCY

-20
Ay=+2

-30
-40

------

i:2- -50
z

Q -60

Ir
~

-70

C

~

-- -- -

......-

-- -

r-: --r

t::tf.--i
l00MHz

50MHz -

-30r---r---r-~--~--_t---+--7f~~
-40r---r---r--4---4--~---+~-+~~

! -60r---r---r-~--~--_t--t+~~L-~
:Q~
iii

-30MHz -

-60

-70 1---1----::1000-'.::::,j~~~q__l4---+--_l

-90

-100
-6

-3

e.
CI

Ay-+l

Ay=+2 r - -

iii' -38

~

235 0
w
180\!!

I

PHASE

-30

Ay=+2

I

20

v-

Ay=-l

"

~

h

-78

-

r--

f-Ay .. -l

l'

~~+2

~ iI'I""""

Ay=-l

-66

-84

-

r==- IIIIt...

-30

o

9
3
8
OUTPUT POWER (dBm)

12

15

-3

FIGURE 25. 2nd HARMONIC DISTORTION va POUT

0

3
8
9
12
OUTPUT POWER (dBm)

15

FIGURE 26. 3rd HARMONIC DISTORTION va POUT

3-581

18

HFA1112
Typical, Performance Curves
-20

VSUPPLY = ±5V, TA = 2SoC, RL = 100Q, Unless Otherwise Specified (Continued)
-20

Ay .. ~l

-30

V

-40

i!!.-50

---

::::... -~

~ -60
~

-70

./'"

C::,i::

::::z:t::::r/

~-:50MHz
-/

l00MHz-

30MHz

-

,./

-

/

V

~

~ -so
z

~

Q-60

~

-70

-80

-80

-90

-90

o

3

9

6

12

I'

/

:::;..--

-100
-6

15

100M,!--

------:z.
- -

~
:--SOM1Hz
l00MHz

f-

i!!. -50

,/

/
30MHz

~

-60

~

-70

"....

....

-90

-90

-100

o

3

6

12

9

-8

15

..,.,......

./'"

-80

-3

......... ~ .,/
......... r-1" .-'1'V_ ~

z

-80

-6

15

Ay=-l

is

-100

12

9

-30

-r

.f-

~-80
~ -70

6

-20

~ I----

l-so
z

3

FIGURE 28. 3rd HARMONIC DISTORTION vs POUT

Ay=-l

-40

...,

30MHz

I

o

-3

-'

............:: t:::/'"

OUTPUT POWER (dBm)

FIGURE 27. 2nd HARMONIC DISTORTION VB POUT

-3~

~

~ ~£;z

OUTPUT POWER (dBm)

-20

V

..,. ",

Ii:
is

-6

/

'U'

is

-100

/

AV=+l

rr H"-

~r~HZ
I
o

-3

50MHz

3

1

30MHt

6

9

12

15

OUTPUT POWER (dBm)

OUTPUT POWER (dBm)

FIGURE 30. 3rd HARMONIC DISTORTION VS POUT

FIGURE 29. 2nd HARMONIC DISTORTION VS POUT •

60

0.D4

VOUT=0.5V

---

50

l

0.D2

IX

~

IX

w

0

!zw
U
IX
W
Go

.(J.D2

/

lL

i--'""""-

.....

-~

1\
o

-2.0

-1.0

0

1.0
INPUT VOLTAGE (V)

2.0

Ay=+l

............

~

..............

r--.

Ay=-l
10

-3.0

~ ....

-

100

3.0

I

Av=+2
300

r - :-r-I
500

700

900

1100

INPUT RISE TIME (ps)

FIGURE 31. INTEGRAL LINEARITY ERROR

FIGURE 32. OVERSHOOT vs INPUT RISE TIME

3-582

1300

HFA1112

Typical Performance Curves

v SUPPLY = ±5V, TA = 25°C, RL = '000, Unless OthelWise Specified (Continued)
60

60

- ---

VOUT=2V

VOUT=1V

50

~ 40

~
illis

50

~
............... , + 1

30

--

.......

20
10 1-.

Av=-'

100

300

-

10

--

Ay=+2
I
500
700
900
INPUT RISE TIME (ps)

o

ct

.s
!zw

II:
II:
:::I

(,)

~

......
:::I

'"

1100

1300

3.5
3.4

/

l

/
/

1100

1300

/

./

,V

18

:::I

'"

.

17
16

./

-50

FIGURE

50

~VOUT(RL=500)~~

3.2 r- I-VOUTI (RL= 1000)

~

3.1

V

3.0

.....

- - - l'---

+VOUT (RL= 1000) /'

L

...........

./

.........

V
2.8 - ~VOUTI (RL= 500)
,
I

.s
30
w
~

!:l

~ 20

6
z 10

I

o

2.6
-25

0
25
50
75
TEMPERATURE (DC)

100

125

0.1

FIGURE 37. OUTPUT VOLTAGE vs TEMPERATURE

-25

o

25
50
75
TEMPERATURE fc)

100

125

36. SUPPLY CURRENT vs TEMPERATURE

130

,

~

w

2.9

I

~>

40

/'

~

15

. 10

6
7
8
9
TOTAL SUPPLY VOLTAGE (V+ - V-, V)

\

~

-

..... r-- ...

10
FREQUENCY (kHz)

ENI
INI

30
100

FIGURE 38. INPUT NOISE CHARACTERISTICS

3-583

O!!!
-IL
!cc::i
a::D.
W:::!E

~ce

./

19

~

t

"

./

20

:::I

(,)

./

/"

ceen
Za::

21

II:
II:

./

./

..J

22

!zw

./

/

--

-SO

500
700
900
INPUT RISE TIME (ps)

23

Ay=-1

2.7

300

24

/

~

5
~
0

l"-

25

3.3

!:l

Av=-1

FIGURE 34. OVERSHOOT VB INPUT RISE TIME

/

~
w

Ay=+2

I

100

FIGURE 35. SUPPLY CURRENT vs SUPPLY VOLTAGE

3.6

~

o

FIGURE 33. OVERSHOOT VB INPUT RISE TIME

22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
./
6
5 ./
5

Ay=+1

HFA1112

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

63 mils x 44 mils x 19 mils
1600llm x 1130llm 4831lm

Type: Nitride
Thickness: 4kA ±O.skA

METALLIZATION:

TRANSISTOR COUNT:

52

Type: Metal 1: AICu (2%)/TiW
Thickness: Metal 1: 8kA ±O.4kA

SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu (2%)
Thickness: Metal 2: 16kA ±O.8kA

Floating (Recommend Connection to V-)

Metallization Mask Layout
HFA1112
NC

v-

NC

NC

OUT

3-584

HFA1113
850M Hz, Low Distortion, Output Limiting,
Programmable Gain, Buffer Amplifier

November 1996

Features

Description

• User Programmable Output Voltage Limiting

The HFA1113 is a high speed Buffer featuring user programmable gain and output limiting coupled with ultra high speed
performance. This buffer is the ideal choice for high frequency applications requiring output limiting, especially
those needing ultra fast overload recovery times. The output
limiting function allows the designer to set the maximum
positive and negative output levels, thereby protecting later
stages from damage or input saturation. The SUb-nanosecond overdrive recovery time quickly returns the amplifier to
linear operation following an overdrive condition.

• User Programmable For Closed-Loop Gains of +1, -1
or +2 Without Use of External Resistors
• Wide -3dB Bandwidth ••.•.•.•.•...•..••.• 850M Hz
• Excellent Gain Flatness (to 100MHz) •••.•••• ±O.07dB

• Low Differential Gain and Phase .••• 0.02%10.04 Degrees
• Low Distortion (HD3, 30M Hz) ••••••.•••••. , -73dBc
• Very Fast Slew Rate •••••••••••••••••.•• 2400VlIlS
• FastSeHllngTlme(0.1%) .•••••••••••.•••.•• 13ns
• High Output Current ••.••••.••.•.••••••.••• SOmA
• Excellent Gain Accuracy .••••.•••••••.•.•. 0.99VN
• Overdrive Recovery. • • • • • • • • . • • • • • • • • • • • • •• <1 ns
• Standard Operational Amplifier Pinout

A unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external
components, as described in the "Application Information"
section. Compatibility with existing op amp pinouts provides
flexibility to upgrade low gain amplifiers, while decreasing
component count. Unlike most buffers, the standard pinout
provides an upgrade path should a higher closed loop gain
be needed at a future date.
Component and composite video systems will also benefit
from this buffer's performance, as indicated by the excellent
gain flatness, and 0.020/0/0.04 Degree Differential
Gain/Phase specifications (RL = 1500).

Applications
• RFnF Processors

For Military product, refer to the HFA1113/883 data sheet.

• Driving Flash AID Converters

Ordering Information

• High-Speed Communications

PART NUMBER
(BRAND)

• Impedance Transformation
• Line Driving
• Video Switching and Routing
• Radar Systems
• Medical Imaging Systems

PKG.
NO.

PACKAGE

HFAll13MJ/883
HFAll131J

-55 to 125
-40 to 85

8 LdCERDIP
8 LdCERDIP

F8.3A
F8.3A

HFAll131P
HFAll131B
(Hll131)

·40 to 85
·40 to 85

8 Ld PDIP
8 LdSOIC

E8.3
M8.15

HFA11XXEVAL

Pinout

TEMP.
RANGE ("C)

DIP Evaluation Board For High Speed Op Amps

Pin Descriptions
HFA1113
(PDIP, CERDIP, SOIC)
TOP VIEW
NC
-IN
+IN
V-

IT ~
300
t:!l VH

[~~t:!l
II
2 -.....

[I

_

7

~

V+
OUT

NAME

PIN
NUMBER

NC

1

No Connection

·IN

2

Inverting Input

+IN

3

Non·lnverting Input

V-

4

Negative Supply

VL

5

Lower Output Limit

OUT

6

Output

V+

7

POSitive Supply

VH

8

Upper Output Limit

VL

CAUTION: These devices are sensltive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996
.

3·585

DESCRIPTION

File Number

1342.3

..J

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-u..
ti:::i
a: a..

1U:iE
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HFA1113
Absolute Maximum Ratings

Thermal Information

Thermal Resistance (Typical, Note 1)
9JA (oCIW) 9JC (,CIW)
CERDIP Package........... .•...
120
35
PDIP Package. . . . . . . . . . . . . . . . . . .
98
N/A
SOIC Package...................
158
N/A
Maximum Junction Temperature (Ceramic Package and Die) .. 175°C
Maximum Junction Temperature (Plastic Package) ..•....• 150°C
Operating Conditions
, Maximum Storage Temperature Range .•....... _65°C to 150°C
Temperature Range. . . • • . • . . . . . . . . . . . . . . . . .. -40°C to 85°C
Maximum lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Voltage Between V+ andV- .••.•.•......••..•.......•.. 12Y
DC Input Voltage ........•....•.................. VSUPPlY
Voltage at VH or Vl Terminal ....•......... (V+) + 2V to (V-) - 2V
Output Current (50% Duty Cycle) ....................... 60mA

CAUTION: Stresses above those listed in "Absolute Maximum RaUngs" may cause permanent damage to the da1lice. This Is a stress only mtlng and operetion
of the device at these or any other conditions above thosa indicated in too opemtional sactions of this specification is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air,

Electrical Specifications

VSUPPlY = :l:5V, Av = +1, Rl = 1000, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

TEMP.
(oC)

MIN

TYP

MAX

UNITS

8

25

mV

-

35

INPUT CHARACTERISTICS

Output Offset Voltage

Full

-

10

25
Full

Output Offset Voltage Drift

25

39

45

Full

35

25

Full

-

-

Non-Inverting Input Resistance

25

25

Inverting Input Resistance (Note 2)

25

Input Capacitance
Input Common Mode Range

PSRR
Input Noise Voltage (Note 3)

100kHz

+Input NoiSe Current (Note 3)

100kHz

-

mV
JlVPC
dB
dB
nVNHz

37

-

pANHz

25

40

JlA

-

65

JlA

50

-

kO

240

300

360

0

25

-

2

-

pF

Full

±2.5

±2.8

-

V

25
25

Non-Inverting Input Bias Current

9

-

TRANSFER CHARACTERISTICS

Gain

Av= +1, VIN =+2V
Av = +2, VIN = +1V

DC Non-Linearity (Note 3)

Av = +2, ±2V Full Scale

25

0.980

0.990

1.020

VN

Full

0.975

-

1.025

VN

25

1.96

1.98

2.04

VN

Full

1.95

-

2.05

VN

25

-

0.02

.

%

OUTPUT CHARACTERISTICS
Output Voltage (Note 3)

-

25

±3.0

±3.3

Full

±2.5

±3.0

25,85

50

60

-40

35

50

25

-

0.3

-

Supply Voltage Range

Full

±4.5

:1:5.5

V

25

-

-

Supply Current (Note 3)

21

26

rnA

-

33

rnA

-

MHz

Av=-l

Output Current (Note 3)

Rl=500

Closed Loop Output Impedance

DC,"-I=+2

,-

V
V
mA
rnA
0

POWER SUPPLY CHARACTERISTICS

Full
AC CHARACTERISTICS

-3dB Bandwld1h
(VOUT = 0.2Vp_p, Notes 2, 3)

Av=-l

25

450

800

Av=+l

25

500

850

Av=+2

25

350

550

3-586

MHz
MHz

HFA1113
Electrical Specifications VSUPPLY = ±5V, Av = +1, RL = 1000, Unless Otherwise Specified (Continued)
PARAMETER
Slew Rate
(Vour = 5Vp_p, Note 2)

Full Power Bandwidth
(Vour = 5Vp_p, Note 3)

TEMP.
(DC)

MIN

TYP

MAX

UNITS

Av=·1

25

1500

2400

-

V/IlS

Av=+1

25

800

1500

Av=+2

25

1100

1900

Av=-1

25

Av=+1

25

Av=+2

TEST CONDITIONS

300

-

V/IlS

-

V/IlS
MHz

150

MHz

25

220

MHz

Av=-1

25

±O.02

dB

Av=+1

25

-

±O.1

Av=+2

25

-

±0.015

Av=-1

25

Av=+1

25

Av=+2

25

Gain Flatness
(to 100MHz, Notes 2, 3)

Av=-1

25

Av=+2

25

Linear Phase Deviation
(to 100MHz, Note 3)

Av=-1

25

Av=+1

25

Av=+2

25

Av=-1

25

Av=+1

25

Av=+2

25

Av=-1

25

Av=+1

25

Av=+2

25

Av=-1

25

-47

Av=+1

25

-53

-

dBc

Av=+2

25

-47

-40

dBc

Av=-1

25

-63

Av=+1

25

-68

-

Av=+2

25

-65

-55

j

Av=-1

25

-41

-

:/

dBc

Av=+1

25

I

dBc

Av=+2

25

Av=-1

25

Av=+1

25

Av=+2

25

100MHz

25

300MHz
100MHz
300MHz

25

40MHz

25

100MHz

25

600MHz

25

Av=-1

25

Av=+1

25

Av=+2

25

Gain Flatness
(to 30M Hz, Notes 2, 3)

Gain Flatness
(to 50MHz, Notes 2, 3)

2nd Harmonic Distortion
(30MHz, Your = 2Vp_p, Notes 2, 3)

3rd Harmonic Distortion
(30MHz, Your = 2Vp_p, Notes 2, 3)

2nd Harmonic Distortion
(50MHz, Your = 2Vp_p, Notes 2, 3)

3rd Harmonic Distortion
(50MHz, Your = 2Vp_p, Notes 2, 3)

2nd Harmonic Distortion
(100MHz, Your = 2Vp_p, Notes 2,3)

3rd Harmonic Distortion
(100MHz, Your = 2Vp_p, Notes 2, 3)

3rd Order Intercept
(Av = +2, Note 3)
1dB Compression
(Ay = +2, Note 3)
Reverse Isolation
(S12, Note 3)

dB
±O.04

dB
dB

±O.05

dB

±0.2

-

-

±0.O36

±O.08

dB

±0.10

-

dB

±O.07

±O.22

dB

±O.13

-

Degrees
Degrees

-57

-

-52

-45

-71
-73

-

-72

-65

±0.83
±O.O5
-52

-

-50

25

-

13

25

-

19

Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBc

dBc
I

dBc
dBc

-42

-35

dBc

-55

dBc

-49

-

-62

-45

dBc

28

-

dBm

dBc

-32

-

500

800

ps

480

750

ps

700

1000

ps

12
-70
-60

dBm
dBm
dBm
dB
dB
dB

TRANSIENT CHARACTERISTICS
Rise Time
(Vour = 0.5V Step, Note 2)

3-587

-

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-1.1.
~::i
a: 0.
W::i

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HFA1113
Electrical Specifications

VSUPPLY = ±5V, Ay = + 1, RL = 1OOQ, Unless Otherwise Specified (Continued)
TEMP.
(oC)

MIN

TYP

Ay=·1

25

-

0.82

Ay=+1

25

Ay=+2

25

1.00

-

Overshoot
(VOUT = 0.5V Step,
Input tWtF = 200ps, Notes 2, 3, 4)

Ay=-1

25

12

30

Ay=+1

25

45

65

Ay=+2

25

6

0.1 % Settling Time (Note 3)

VOUT = 2V to OV

25

0.05% Settling TIme

VOUT = 2V to OV

Differential Gain

Po.!=+1, 3.58MHz, RL = 150Q
Po.! = +2, 3.58MHz, ~ = 150Q
Po.! = +1, 3.58MHz, ~= 1500
Po.! = +2, 3.58MHz, RL = 150Q

TEST CONDITIONS

PARAMETER
Rise Time
(VOUT = 2V Step)

Differential Phase
OUTPUT LIMITING CHARACTERISTICS
Clamp Accuracy (Note 3)

-

UNITS
ns

1.06

ns
ns

20

%
%
%

13

20

ns

25

20

33

ns

25

0.03

-

25

0.02

%
%

25
25

-

-

0.04

-

±100

±150

mV

-

±200

mV

0.05

Degrees
Degrees

Ay = +2, VH = +1V, VL = -1V, Unless Otherwise Specified
25

VIN=±1.6V,Ay=-1

Full
Clamp Overshoot

VIN = ±1V, InputtRItF = 500ps

25

Overdrive Recovery Time (Note 3)

VrN=±1V

25

-

Negative Clamp Range

25

-

Positive Clamp Range

25

-

Clamp Input Bias Current (Note 3)

25
Full

Clamp Input Bandwidth (Note 3)

MAX

25

VH or VL = 100mVp_p

-

7

-

%

0.75

1.5

ns

-

V

-

V

-5.0 to
+2.0
-2.0 to
+5.0
50

200

-

300

500

-

IJ.A
IJ.A
MHz

NOTES:
2. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.
3. See Typical Performance Curves for more information.
4. Overshoot decreases as input transition times increase, especially for Po.! = +1. Please refer to Typical Performance Curves.

Application Information

PC Board Layout

Closed Loop Gain Selection

The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low Inductance components such as chip resistors and chip capacitors is strongly recommended,
while a solid ground plane is a mustl

The HFA 1113 features a noyel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
This "buffer" operates in closed loop gains of -1, + 1, or +2, and
gain selection is accomplished via connections to the ±Inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1, while grounding -IN selects a gain of +2. A gain of·l is
obtained by applying the input signal to -IN with +IN grounded.
The table below summarizes these connections:
CONNECTIONS
GAIN

(AcrJ

+INPUT
(PIN 3)

-INPUT
(PIN 2)

-1

GND

Input

+1

Input

NC (Floating)

+2

Input

GND

Attention should be given to decoupling the power supplies.
A large value (10J.lF) tantalum in parallel with a small value
chip (0.1 J.lF) capaCitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. CapaCitance directly on the
output must be minimized, or isolated as discussed in the
next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier's
inverting input. At higher frequencies this capaCitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.

3-588

HFA1113
An example of a good high frequency layout is the Evaluation Board shown in Figure 3.

OO(~=+l)

or on (Av = +2)

Driving Capacitive Loads
Capacitive loads, such as an AID input, or an improperly terminated transmission line will degrade the amplifier's phase
margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided
by placing a resistor (RS) in series with the output prior to
the capacitance.

IN_.....--~

Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.

FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC

TOP LAYOUT

.~------------~.

RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of
850MHz. By decreasing RS as CLincreases (as illustrated in
the curves), the maximum bandwidth is obtained without
sacrificing stability. Even so, bandwidth does decrease as
you move to 'the right along the curve. For example, at
AV = +1, RS = son, CL = 30pF, the overall bandwidth is limited to 300M Hz, and bandwidth drops to 1OOMHz at AV +1,
RS = 5n, CL = 340pF.

•

=

BOTTOM LAYOUT
50

g

If

45
40
35
30
25
20
15
10
5

o

I I I I
Av=+l

]

'\.

....

"

o 0
o ~O

...

o

40

80

120

160

200 240

280 320

00

•

~=+2

o

0

•

360 400

LOAD CAPACITANCE (pF)

FIGURE 3. EVALUATION BOARD LAYOUT

FIGURE 1. RECOMMENDED SERIES RESISTOR VB LOAD
CAPACITANCE

Limiting Operation

Evaluation Board

General

The performance of the HFA1113 may be evaluated using
the HFA 11 XX Evaluation Board, slightly modified as follows:
1. Remove the soon feedback resistor (R2), and leave the
connection open.

=

2. a. For Av + 1 evaluation, remove the soon gain setting
resistor (Rl), and leave pin 2 floating.
b. For Av = +2, replace the soon gain setting resistor with
a on resistor to GND.
The modified schematic and layout of the board are shown
in Figures 2 and 3.
To order evaluation boards (part number HFA 11 XXEVAL),
please contact your local sales office.

The HFA 1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (pins 8 and
5) of the amplifier. VH sets the upper output limit, while VL
sets the lower clamp level. If the amplifier tries to drive the
output above VH, or below VL, the clamp circuitry limits the
output voltage at VH or VL (± the clamp accuracy), respectively. The low input bias currents of the clamp pins allow
them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.

Clamp Circuitry
Figure 4 shows a simplified schematic of the HFA 1113 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QXl - QX2)

3-589

...I
«0
za:

O!:!:!
-II..
~::i

a:

11.

W::E
~«

HFA1113
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V-IN - VOUT)/RF + V-IN/RG
This current is mirrored onto the high impedance node (Z) by
OXa-OX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping Is utilized,
the high impedance node may swing within the limits defined
by OP4 and 0N4. Note that when the output reaches its quiescent value, the current flowing through -IN is reduced to
only that small current (-IBIAS) required to keep the output at
the final voltage.
Tracing the path from VH to Z Illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2VBE (ONS and OPS) to set up the base voltage on 0PS'

Clamp Accuracy
The clamped output voltage will not be exactiy equal to the
voltage applied to VH or VL. Offset errors, mostly due to VBE
mismatches, necessitate a clamp accuracy parameter which
is found in the device specifications. Clamp accuracy is a
function of the clamping conditions. Referring again to Figure
4, it can be seen that one component of clamp accuracy is the
VBE mismatch between the Oxs transistors, and the OX5
transistors. If the transistors always ran at the same current
level there would be no VBE mismatch, and no contribution to
the inaccuracy. The 0XS transistors are biased at a constant
current, but as described earlier, the current through OX5 is
equivalent to ICLAMP- VBE increases as ICLAMP increases,
causing the clamped output voltage to increase as well.
ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT
CLAMPED), so clamp accuracy degrades as the overdrive
increases. As an example, the specified accuracy of ±100mV
(Av -1, VH 1V) for a 1.6X overdrive degrades to ±240mV
for a 3X (200%) overdrive, as shown in Figure 43.

=

50K
(30K

FORVL)

=

Consideration must also be given to the fact that the clamp
voltages have an affect on amplifier linearity. The "Nonlinearity Near Clamp Voltage" curve, Figure 48, illustrates the
impact of several clamp levels on linearity.

Clamp Range
Unlike some competitor devices, both VH and VL have usable
ranges that cross OV. While VH must be more positive than
VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the
HFA1113 could be limited to ECL output levels by setting
VH =-O.SV and VL = -l.SV. VH and VL may be connected to
the same voltage (GND for instance) but the result won't be in
a DC output voltage from an AC input signal. A
1SOmV - 200mV AC signal will still be present at the output.

RF=3000
(INTERNAL)

VOUT

FIGURE 4. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY
OPS begins to conduct whenever the high impedance node
reaches a voltage equal to OPs's base voltage + 2VBE (OPS
and 0N5)' Thus, OP5 clamps node Z whenever Z reaches
VH' R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp Circuitry controlled by VL.
When the output is clamped, the negative input continues to
source a slewing current (ICLAMP) in an attempt to force the
output to the quiescent voltage defined by the input. OP5 must
sink this current while clamping, because the -IN current is
always mirrored onto the high impedance node. The clamping
current is calculated as:
ICLAMP

=(V-IN - VOUT CLAMPED)I3000 + V-IN/RG'

As an example, a unity gain circuit with VIN =2V, and VH = 1V,
would have ICLAMP =(2V - 1V)I3OO0 + 2V100 =3.33mA (RG =00
because -IN is floated for unity gain applications). Note that Icc
will increase by ICLAMP when the output is clamp limited.

Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (VCLAMp/AvcLl the amplifier will
return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear
operation. The plots of "Unclamped Performance" and
"Clamped Performance" (Figures 41 and 42) highlight the
HFA1113's subnanosecond recovery time. The difference
between the unclamped and clamped propagation delays is
the overdrive recovery time. The appropriate propagation
delays are S.Ons for the unclamped pulse, and S.Sns for the
clamped (2X overdrive) pulse yielding an overdrive recovery
time of SOOps. The measurement uses the 90% point of the
output transition to ensure that linear operation has
resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the
true HFA1113 propagation delay is SOOps.
Overdrive recovery time is also a function of the overdrive
level. Figure 47 details the overdrive recovery time for various clamp and overdrive levels.

3-590

HFA1113

Typical Performance Curves
200

2.0
AV=+2

Av=+2

150

1.S

Sl00

~ 1.0

§.

1lI

1lI

50

~

g

~

-100

-150

0

5 -O.S
I!:

-50

§

-

:;)

0-1.0

J

v-

-l.S

-200

-2.0

TIME (5nsJDIV.)

TIME (SnalDIV.)

FIGURE 5. SMALL SIGNAL PULSE RESPONSE

FIGURE 6. LARGE SIGNAL PULSE RESPONSE

2.0

200
lS0

AV=+l

~

1.S

1\

Sl00

Av=+l

'\

~ 1.0

§.

1lI
~
~

1

O.S

g

0

5

:1\v-

~

so

1

O.S

!j
~

0

0

-50

5~ -O.S

-100

0_1.0

5

§

r

-lS0

.J

\L-

-l.S

-200

-2.0

TIME (SnsJDIV.)

TIME (SnsJDIV.)

FIGURE 7. SMALL SIGNAL PULSE RESPONSE

FIGURE 8. LARGE SIGNAL PULSE RESPONSE

200
150

2.0
Av=-l

1.S

S 100

~ 1.0

"

§.

w
~

1lI

50

~

0

~

0

5

-so

~

-O.S

o

-1.0

~

~

Av=-l

I

.A

:V

O.S

!j

0-100

5

"-

IA

-l.S

-150

-2.0

-200

TIME (SnsJDIV.)

TIME (SnsJDIV.)

FIGURE 9. SMALL SIGNAL PULSE RESPONSE

FIGURE 10. LARGE SIGNAL PULSE RESPONSE

3-591

-

HFA1113
Typical Performance Curves
iii' 6

:s
z
~

~

·3
·6

a:
§i!

·9

1111

Ay = +2, VOUT = 200mVp.p

Jluv'

GAIN!

0

jJ

1~1I!I+l

VOUT = 200mVp.p

3

VSUPPLY = ±5V, TA = 25°C, RL = 100n, Unless Otherwise Specified (Continued)

I

!

I+H+I+!-=G:::A:r-IN=+-I-I-+'I+H---f-+-i-fJ~I--*,,.d..I-H+Hl
~ 3 H-Hi1Ht--t+++HttI-++ RL = 500.....-F/~'ttttH

Ay=·1
Ay=+2

PHASE

6

o

Ay=~~
Ay=·1

RL = 1000 '+/-'A"''l+WH

H+ffi*-PH+AS+E~~++iIU;kn"'++~~

t+tffittt--t-tt+Httt-,...j;I;;t±tttt--t-ttttlll 0 !3

Ay=+1

1-H-HH-f-H-++HtH-RL=Q!' ""'""

~"

RL=lkO
10
100
FREQUENCY (MHz)

1000

0.3

6

1111111

~

3

lJ..WV"

GAIN

!

RL=lkn/V
RL = 1000
~
RL = 50'1

~

1111111

o

I I \ll1r"oo

·90

RL = 100'1""
·180

RL = 500

1\\11

RL = lkn
0.3

10
100
FREQUENCY (MHz)

GAIN

RL=SOO

II

Cl

RL= SOO

·270 ~

-<

RL= lkn

·360 i!:
1000

0.3

10
100
FREQUENCY (MHz)

6

Ay=+1

:So

3 H-l-H1t+1--++I-H+Hf_H-I4.0Vp.p "'F+-I::ltiHi
2.5Vp.p

~-3

GAI~

ill

H-Hi1Ht--++f+tttlt~

PHASE

i

.270

10
100
FREQUENCY (MHz)

VOUT= 1Vp.p

~
A.

......

11111111
VOUT = 4V;':~'-'

~

o
·90

·180

Vour = 2.5Vp.p -

1[w1
-<
H-tffiHt--++f+tttlt-I-tTtt111+-++++ltfflI\lliI.360 i!:
II 1111
11111
0.3

180
1000

11111111 J..
IlI..U#.r'
VOUT = 4Vp.p""-

1111I1lT""'-

f-~f:::"':Iool!I~.·I80 I!!_

2:SV:; lVp.p....

III

-90

VOUT = 2.5Vp.p'"

-6

.....::!i~++tIfI~90

~I

FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

iii'3

H-++tIt+I--++I-H+Hf-H-I-I-Htl+.......

~100'1

If

e.

11111

H-Hi1Ht--++f+tttlt~ 4 OV

III ..1..&
RL = 1000

·3
·6

GAIN
61+~H+--+~H-++I++-H+++++l.f--I-oId.lHj.jJ

PHASE

RL=lkn-+-l

PHASE

12 rT"T',.,.,.,....-r-T"TT'rrnT'-r-T"TT'lrTT
11I1Irr-, T ' " T " lIrT'
1111
I T'T1T1

~

Ay = ·1, VOUT = 200mVp.p

0

m

1i '-iH 1V~:;'
iii' 9I-t-Avttt1=...+,..2-+-t-!f+tttlt-H+ttl"1Ht-

Z

1000

a:

FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

...

10
100
FREQUENCY (MHz)

·9

1111

PHASE

~

e.

III

FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

FIGURE 11. FREQUENCY RESPONSE

Av = +1, VOUT = 200mVp.p

180

H-:~'F+""'~·270 ~
V
360i!:

H-1-H1H+--+-+++Hf+10.3

·90

'"

RL=50'1...

m
a:
~

VOUT = lVp.p';;;:;-

11111111

1000

0.3

FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

1

10
100
FREQUENCY (MHz)

1 0o

FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

3·592

HFA1113

Typical Performance Curves
6

VSUPPLY = ±5V, TA = 25°C, RL = 100n, Unless Otherwise Specified (Continued)

15
AV=·1

VOUT= 5Vp.p

VOUT = 2.5Vp.p

GAIN

VOUT = 4Vp.p - ....

III

VOUT = 1Vp.p

III

./'

PHASE
180 U)

r-..
VOUT = 4Vp.p -:--

e.
~
·180

VOUT = 1Vp.pIII

0.3

·9

II.

·12

III
III

·15
0.3

1000

10
FREQUENCY (MHz)

FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

900

800

!
Z

~

.......

Av=·1

iii'

700

600
Ay=+2
550

SOO
·50

o

·25

25

ctcn

Za:

0.20

:c

"...tilc

0.15

~

0.05

--

...

~

~

Av=+1

100

0

Ay=+2

III
10
FREQUENCY (MHz)

1

4

II

·2

Av=·1

':"'10

~

~

e. .1

~

Ay=+1

!!i

~-3

T7"
Ay=+2

~

0.4

"

0.2
0.1
0
-0.1
·0.2

a:
~
a:
w
Z

~

~

-4

o

15

30

45

60
75
90 105
FREQUENCY (MHz)

120

135

·0.4

CI)

-0.6

~

·5
-6

I
I
I
Ay = +2. VOUT = 2V

0.6

2

~
j:;

100

FIGURE 20. GAIN FLATNESS

3

0

LI'"\

-0.05

·0.15

125

f

II

1/

./

FIGURE 19• .adB BANDWIDTH vs TEMPERATURE

ffi

Av=·1

I

0.10

TEMPERATURE (OC)

...~1
a:

I

·0.10

75

50

a:
0
z

O!!:!
-II..

I

0.25

:s
z

650

..J

0.30

750

I

1000

0.35

Av= +1

N

100

FIGURE 18. FULL POWER BANDWIDTH

I

850

-"

Av=+1

·90 ...

11111

10
100
FREQUENCY (MHz)

-1:

Ay=+2

ffi

o

VOUT = 2.5Vp.p -

II

~

90

Av=·1

·2

150

3

8

13

18

23

28

33

38

TIME (ns)

FIGURE 21. DEVIATION FROM LINEAR PHASE

FIGURE 22. SETTLING RESPONSE

3·593

43

48

ti:J

a: a..

W::iE

~ct

HFA1113

Typical Performance Curves

VSUPPLY

=±5V, TA =25°C, RL =loon, Unless Otherwise Specified

-24

Av=+l

-42

\

iD-48

i'.54

~

~-60 I-- _Av=-l
-66

~

jIIII"""'"

A ~

I'

AV=+2. Av =-1

20

~-48

40

60

80 100 120 140
FREQUENCY (MHz)

160

II:

14

'll

10

~

8

-60 ~

180 200

GAIN

100 190

90~

\
~

45~
o i

I

\1

1

Av=-l

AV=-l

I

280 370 460 550 640 730 820 910 1000
FREQUENCY (MHz)

FIGURE 24. HIGH FREQUENCY REVERSE ISOLATION (S12)

30~--~----~-----r----'-----~--~

2-TONE

....

"'- ....

~

ffl

)

-54

/. , /
Y'

t§

Av=+1

Av\ 2
I =+

j

~.36

FIGURE 23. LOW FREQUENCY REVERSE ISOLATION (S12)

..,~2O18
~ 16

, ::;:;.- ,

-30

.-¥

o

1

Av = +2
\

Z -42

~ "..

-78

Av=-l
-24

.

~ f'"

-72 Av=+2

II

-

13

235
180 w

PHASE

It

-36

-84

- -±-

~

-30

(Continued)

IAv=_1 1

~ ........

j

~=~ "8 ~~
.......... ~
12

~

!:
!;

2

O

0

S

-

y
-

AV=+l

'\.
'\

~~

"

~

~

......
O~--~----~----~--~-----L--~

100

200

300
FREQUENCY (MHz)

400

100

500

.20
Av=+2

-30

-------r:::z

-- - ---

f:- -;

100MHz

50MHz

r-----r----.----,..--~--~----,r----....._~

Av=+2

-301---+---+----I----I----+---f--_.I""-*-I

~

~ ~ .--,-

400

FIGURE 26. THIRD ORDER INTERMODULATION INTERCEPT
va FREQUENCY

FIGURE 25. 1dB GAIN COMPRESSION va FREQUENCY

-20

200
300
FREQUENCY (MHz)

-401----I---+---+---+---+----h1'(....+_~

i~.50I---+---4---~---+---+--~~~~-4

If

~ -601----I---+---+---~~~~~~+_~

30MHz -

~

-70

1--+--:::;j"..oII!!!!JJ~'r:J...~-I_4-+--I

is
.90/--~~-+

-100

-100
-6

-3

o

3

6
9
OUTPUT POWER (dBm)

12

15

~

-6

__-'-__...J....__

~

___'___~___ '____'_____l

6

15

OUTPUT POWER (dBm)

RGURE 27. SECOND HARMONIC DISTORTION va POUT

FIGURE 28. THIRD HARMONIC DISTORTION va POUT

3-594

18

HFA1113

Typical Performance Curves

VSUPPLY =±5V, TA = 2SoC, RL = 1000, Unless Otherwise Specified (Continued)

·20

·20

/

AV=+1
·30

~V

·40

i~ ·50
~-60

·70

~

~

--

-'

:;;...,- :.-,..
-I
/.

- _10{-::::------

z

-

",

-

~-.----,;---.,---,---.,---,----,

-30r--~-~r--+----+---+-~-+--~

-40r---~-~r--+----+-~~--+-~

10~~Hz_50MHZ _30MHz

-

·80
-90
·100

o

-6

6

3

9

o

15

12

OUTPUT POWER (dBm)
FIGURE 29, SECOND HARMONIC DISTORTION vs POUT

·20

l

--- ::::z:.-r

z

~

-40r---~----r--~-~---~-~r---~

i~

'.../-

Q -60

Ii:

'~r---;----f----r---~--~----+---~

I-

.--

-50

~

100MHz

is

-90

-90

·100

o

-6

3

6

9

12

\-;;"-!!f--

o

15

OUTPUT POWER (dBm)

3

6

12

9

15

OUTPUT POWER (dBm)

FIGURE 31. SECOND HARMONIC DISTORTION vs POUT

FIGURE 32. THIRD HARMONIC DISTORTION vs POUT

80

0.D4

--

VOUT=0.5V

~

l

i

0.02

0

I V
...

/

" 1\

""""

~.02

10

o

~.04

-3.0

·2.0

·1.0

0

1.0

2.0

-

3.0

FIGURE 33. INTEGRAL LINEARITY ERROR

~ ....Av=+1
..........

~

........... r--

Ay=.1

A y=+2

100

INPUT VOLTAGE (V)

~O

700
900
50D
INPUT RISE TIME (pa)

1100

FIGURE 34. OVERSHOOT vs INPUT RISE TIME

3·595

..J

CCCl)

Zo:

O~
-IL

~:::i

0:0.

'~r--~--r--~-~--~~~~~--~

~ ·60 r---+----r--:::::.....""""~;__~""""::...._:I~--_i
·70 r-;__"*"'o£:'-t-,,~I""":.....r':::l;oo....."l-l----+----~

-- '7- / 30l..z
·70 r - - - - 50MHz :a0

15

Ay=·1

~

-40

12

9

~---r---r----r-----'-----r----';----,

Ay=.1

'U'

6

FIGURE 30. THIRD HARMONIC DISTORTION vs POUT

·20
-30

3

OUTPUT POWER (dBm)

1~O

W:!i

~CC

HFA1113
Typical Performance Curves

VSUPPLY = ±5V, TA = 25°C, RL = 1000, Unless Otherwise Specified (Continued)

60

60

-

VOUT= 1V

50

VOUT=2V
50

:--- ~

~40

............ Ay=+1

~

i· --Ay=+1

r--

Ay=-1

C 20

Ay=-1
I......

10

10

Ay=+2

o
100

r500
700
900
INPUT RISE TIME (pa)

300

~

!z
w
~

22
21
20
19
18
17
16
15
14

1300

100

,

I

1

10

/"
/"

9
8
7
6
5

-- --

"

----

,

!zw

I

f

II:
II:

:)

()

~

23

3.6
3.5
3.4

~

'-'

g
5

S

3.3
3.2 _

20
19

..,. " ,

a. 18
a.

:)
(II

7
6
8
9
TOTAL SUPPLY VOLTAGE (V+ - v.., V)

J....-

-

..

17

15

10

........

./

2.9

0

2.8 ; '

200

.§.

r;

c(

150

c(

a.

100

50~--~+_----_+----~._~=-;_----~

o

100

200
300
OVERDRIVE (% OF VH)

400

50

o

500

I

100

VL=2V

----

200

~:::omv

300

400

500

OVERDRIVE (% OF VLl

FIGURE 43. VH CLAMP ACCURACY vs OVERDRIVE

FIGURE 44. VL CLAMP ACCURACY vs OVERDRIVE

400r------r-----.------,-----~------,

250
AV=+2

>'

~ 300~----~----~~~--;---~~----~

r;

~

~

::) 200 I-----,A-~----l--::;,;c.--+-------+----__l

~

!

c(

1---~-bflE-----l------+-------+----_::l.

O~----~~~-L

o

100

____

200

~

______

300

~

__

150

::)

0
0

100

200

.§.

r;

a.

100

:&

~

0

50

~

400

500

OVERDRIVE (% OF VH)

FIGURE 45. VH CLAMP ACCURACY vs OVERDRIVE

0

0

200
300
OVERDRIVE (% OF VLl

400

FIGURE 46. VL CLAMP ACCURACY vs OVERDRIVE

3-597

0.

~CC

I

o

O~----. .~~~----~----~----~

a:

W:E

-'- 1//

~

0

!;;:::J

VL=lV

V/ /

II:

::)

0
0

-j!

."..--

/

500

HFA1113
Typical Performance Curves

VSUPPLY = ±5V, TA = 25°C, RL = 1000, u'nless Otherwise Specified (Continued)

3500 , . . - - - - , . . . - - - - - , - - - - - - , - - - - - - ,

20

~3000~---+----~----+--~~

15
VL=-3V

w

~

2500 1----;----+.,..--=:-::;;""""''------1

~
~

2000

:;S.

Z
'>

.

$

~ 1500~---~~~-~---_+-~~~

~

5

r:: ~--::::;;..=Ir:::::::~~+;...~;:;-~---~
~

r;

-

I{

-5

VH=1V

....

r\
VH=2V

VH=3V

-15
-20

-3

500

-2

2

3

140

130
AV = -1, VIN = ±1.6V
VH = 1V, VL = -1V

V!!.
110
100

D-

90

V

"

V

-

80

~

70
60
-75

-50

-25

--

ffi

90

£:

80

~

.., V
VL

~
CD

'/
100

125

150

70
60

"

.......

VH = 300mVp_p

/

.......

.... ~H

.........
-50

-25

..... i'o..

......~

r-- ....

0
25
50
75
TEMPERATURE fc)

100

~

z

~

r

150

11111111

0

~

-3

"J

/'

-6

~

VL = 600mVp_p/
VL=1.2Vp_p

-9

...

~J \

125

VL = 300mVp.p

3

iii'

~

-12

"-

6

III

VH = 600mVp.p ;,-:
VH =1.2Vp.p

~L

FIGURE 50. CLAMP BIAS CURRENT VB TEMPERATURE

111111

100
FREQUENCY (MHz)

..

30
20
-75

FIGURE 49. CLAMP ACCURACY VB TEMPERATURE

10

"

!:

f1'

0
25
50
75
TEMPERATURE (DC)

.e

~

~ 110
~ 100

./

~/

VH = 1V, VL = -lV

120

~

120

£:0

:50

0

FIGURE 48. NON-LINEARITY NEAR CLAMP VOLTAGE

II:

ct

\

5

FIGURE 47. OVERDRIVE RECOVERY VB OVERDRIVE

130

ct

200
300
400
OVERDRIVE LEVEL (% OF CLAMP LEVEL)

Av=-l

VL=-2V VL=-lV

,

10

I

~ -10

o t:::::~=±:::::::::t::::::J
100

,I

-12

,.r
10

1000

100
FREQUENCY (MHz)

1000

FIGURE 52. VL CLAMP INPUT BANDWIDTH

FIGURE 51. VH CLAMP INPUT BANDWIDTH

3-598

HFA1113

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:
Type: Nitride
Thickness: 4kA ±O.5kA

63 mils x 44 mils x 19 mils
1600llm x 1130llm x 4a31lm

TRANSISTOR COUNT:

METALLIZATION:

52

Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: akA ±O.4kA

SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kA ±O.akA

Floating (Recommend Connection to V-)

Metallization Mask Layout
HFA1113
NC

+IN

-IN

v+

OUT

3-599

HFA1114
850MHz Video Cable Driving Buffer

November 1996

Features

Description

• Access to Summing Node Allows Circuit Customization

The HFA1114 is a closed loop Buffer featuring user
programmable gain and ultra high speed performance.
Manufactured on Harris' proprietary complementary bipolar
UHF-1 process, the HFA1114 offers a wide -3dB bandwidth
of 850MHz, very fast slew rate, excellent gain flatness, low
distortion and high output current.

f\.

User Programmable For Clo.ed-Loop Gains of +1, -1
or +2 Without Use of External Resistors

• Wide -3dB Bandwidth •.•••.••••.••••...•. 850M Hz
• Very Fast Slew Rate ••••••••••••••••.••. 2400V/j!S
• Fast Settling Time (0.1%) ••••••••••••••••••• 11ns
• High Output Current ••.•..•.•••.•••••.•.••• 60mA
• Excellent Gain Accuracy ••.•.••..•••••.••• 0.99VN
• Overdrive Recovery. . • • . • • • • • • • • • • • • • • • • •• <10ns
• Standard Operational Amplifier Pinout

Applications
• RFnF Processors
• Driving Flash AID Converters

A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via connections
to the inputs, as described in the "Application Information"
section. The result is a more flexible product, fewer part types
in inventory, and more efficient use of board space.
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date.
For applications requiring a standard buffer pinout, please
refer to the HFA1110 datasheet.

• High Speed Communications
• Impedance Transformation

Ordering Information
PART NUMBER
(BRAND)

• Line Driving

TEMP. RANGE
(DC)

PKG.
NO.

PACKAGE

• Video Switching and Routing
• Radar Systems
• Medical Imaging Systems

HFA11141P

·40 to 85

8 Ld PDIP

E8.3

HFA11141B
(H11141)

-40 to 85

8 LdSOIC

M8.15

HFA11XXEVAL

Pinout

DIP Evaluation Board for High Speed
OpAmps

Pin Descriptions
HFA1114
(PDIP, SOIC)
TOP VIEW

NAME

PIN
NUMBER

NC

1,8

No Connection
Inverting Input

-IN

2

+IN

3

Non-Inverting Input

V-

4

Negative Supply

SN

5

Summing Node

OUT

6

Output

V+

7

Positive Supply

CAUTION: These devices are sensijlve to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © HalTls Corporation 1996

3-600

DESCRIPTION

File Number

3151.3

HFA1114
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ 12V
DC Input Voltage .......•••....•••..•....•......• VSUPPLY
Differential Input Voltage................................ 5V
Output Current. . . . .. .. .. . . . . . . . . .. . . . . . . . . . . . . .... 60mA

Thermal Resistance (Typical, Note 1)

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . • . • . . . . . .. -400 C to 85°C

9JA (lCIW)

PDIP Package.............................
130
SOIC Package.. . . . . . . .. . . . . . . . . . . . . . . . . . ..
170
Maximum Junction Temperature (Ole) ...........•........ 175°C
Maximum Junction Temperature (Plastic Package) .......• 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed In "Absolute Maximum RaUngs' may cause psrmanent damage to the device. This is a stress only tating and opstation
of the device at these or any other conditions above those indicated in the opstaffonal sections of this specification is not Implied.

NOTE:
1. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications VSUPPLY = ±5V, Av = +1, RL = 1000, Unless Otherwise Specified
TEMP_

TEST
CONDITIONS

PARAMETER

(lC)

MIN

TYP

MAX

UNITS

8

25

mV

-

35

mV

-

IlvfJc

INPUT CHARACTERISTICS

Output Offset Voltage

25

Output Offset Voltage Drift

Full

Full

PSRR

39

45

35

-

-

9

-

nVNHz

37

-

pAlVHz

25

40

/lA

Full

-

-

65

/lA

25

25

50

-

kO

25

240

300

360

0

25

-

2

-

pF

Full

±2.5

±2.8

-

V

25

0.980

0.990

1.02

VN

Full

0.975

1.025

VN

25

Non-Inverting Input Noise Current

100kHz

25
25

Inverting Input Resistance
Input Capacitance

Either Input

Input Common Mode Range

10

25

100kHz

Non-Inverting Input Resistance

/

Full
Input Noise Voltage

Non-Inverting Input Bias Current

-

dB
dB

Av = +1, VIN = +2V

Av = +2, VIN = +1V

DC Non-Linearity

Av = +2, ±2V Full Scale

25

1.96

1.98

2.04

VN

Full

1.95

-

2.05

VN

25

-

0.02

-

%

OUTPUT CHARACTERISTICS

Output Voltage

Output Current

Closed Loop Output Impedance

Av=-l

Av= -1, RL= 500

Av=+2, DC

3-601

25

±3.0

±3.3

Full

±2.5

±3.0

25,85

50

60

_40°C

35

50

25

-

0.3

-

V
V
rnA

-

~cn

Za:

O!!!
-II..

!;::::i
a: a..

w~

TRANSFER CHARACTERISTICS

Gain

...J

rnA
0

~~

HFA1114
Electrical Specifications VSUPPLY = ±5V, Av = + 1, RL = 1000, Unless Otherwise Specified (Continued)
TEMP.

TEST
CONDITIONS

PARAMETER

fc)

MIN

Full

±4.5

TYP

MAX

UNITS

±5.5

V

21

26

rnA

-

33

rnA

800

-

MHz

POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
Supply Current

25
Full

-

AC CHARACTERISTICS
-3dB Bandwidth (VOUT = 0.2Vp_p)

Ay=-1

25

Ay=+1

25

Ay=+2

25

Ay=-1

25

Ay=+1

25

Av=+2

25

-

Full PowerBW

5Vp_p, Ay = +2

25

-

220

Gain Flatness

To 30MHz, Ay = +2

25

To 100MHz, Av = +2

25

2nd Harmonic Distortion

-

±0.015

Gain Flatness

Slew Rate (VOUT = 5Vp_p)

50MHz, VOUT = 2Vp_p

25

3rd Harmonic Distortion

50MHz, VOUT = 2Vp_p

25

3rd Order Intercept

1OOMHz,

Av = +2

25

1dB Compression

100MHz, Ay = +2

25

Rise Time (VOUT = 0.5V Step)

Ay=+2

25

Overshoot

VOUT = 0.5V Step,

0.1 % Settling Time

VOUT = 2V to OV

25

0.05% Settling Time

VOUT = 2V to OV

25

25

Ay=+1

Av = +2

Overdrive Recovery Time
Differential Gain

Differential Phase

25

850
550

-

VIIlS

1500

-

VIIlS

1900

±0.07
-53
-68
28
19
700
480

11
15

25

8.5

25

0.03

Av = +2, 3.5BMHz, ~ = 1500

25

Av = +1, 3.58MHz, RL = 1500

25

Av = +2, 3.5BMHz, RL = 1500

25

-

-

-

0.04

MHz
dB
dB
dBc
dBc
dBm
dBm

ps
%

-

0.02
0.05

VIIlS

ps

6

-

MHz

2400

Av = + 1, 3.58MHz, RL = 1500

3-602

MHz

-

ns
ns
ns
%
%

-

Degrees
Degrees

HFA1114

Application Information
Closed Loop Gain Selection
The H FA 1114 features a novel design which allows Ihe user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
This "buffer" operates in closed loop gains of -1, +1, or +2, and
gain selection is accomplished via connections to the ±inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1, while grounding -IN selects a gain of +2. A gain of -1 is
obtained by applying the input signal to -IN with +IN grounded.
The table below summarizes these connections:
CONNECTIONS

GAIN
{AcLl

+INPUT (PIN 3)

-1

GND

Input

+1

Input

NC (Floating)

+2

Input

GND

-INPUT (PIN 2)

Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the Rs and CL combinations for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
Rs and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth of 850MHz. By decreasing Rs as CLincreases (as
illustrated in the curves), the maximum bandwidth is
obtained without sacrificing stability. Even so, bandwidth
does decrease as you move to the right along the curve.
For example, at Av = + 1, RS =500, CL =30pF, the overall
bandwidth is limited to 300M Hz, and bandwidth drops to
100MHz at AV =+1, RS = 50, CL =340pF.

45
40 1-1-'
35

PC Board Layout

g ~~ \
l 20

The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!

~g

For unity gain applications, care must also be taken to minimize
the capacitance to ground seen by the amplifier's inverting
input. At higher frequencies this capacitance will tend to short
the -INPUT to GND, resulting in a closed loop gain which
increases with frequency. This will cause excessive high
frequency peaking and potentially other problems as well.
An example of a good high frequency layout is the Evaluation
Board shown in Figure 2.

Driving Capacitive Loads
Capac~ive

loads, such as an NO input, or an improperly
terminated transmission line will degrade the amplifier's phase
margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a
resistor (RS) in series wRh the output prior to the capacRance.

=+1
-I

<(I)

....

I"

g111111111"1111,111111.1111111111111

50 Av=+2
o

Attention should be given to decoupling the power supplies.
A large value (10~F) tantalum in parallel with a small value
(0.1IlF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the input
and output of the device. Capacitance directly on the output must
be minimized, or isolated as discussed in the next section.

Av

40

80

120 160 200 240 280 320
LOAD CAPACITANCE (pF)

Evaluation Board
The performance of the HFA1114 may be evaluated using
the HFA 11 XX Evaluation Board, slightly modified as follows:
2. Remove the 5000 feedback resistor (R2), and leave the
connection open.

=

3. a. For AV + 1 evaluation, remove the 5000 gain setting
resistor (Rl), and leave pin 2 floating.
b. For AV +2, replace the 5000 gain setting resistor with
a 00 resistor to GND.

=

4. Isolate Pin 5 from the stray board capacitance to minimize
peaking and overshoot.
The layout and modified schematic of the board are shown in
Figure 2.
To order evaluation boards (part number HFA11 XXEVAL),
please contact your local sales office.

TOP LAYOUT

: 0

IN

•

+5V

0

~

0

-----1"31

0 -.....

0

*,-VL
GND
GNDV
5

'

'.--0

•

FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT

3-603

•

0

~::i

a::c..

W:iE

FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE

.,.-----~----~.

1----....-0

360 400

Za::

O!:!:!
-LL

0

•
0

0
0

0

•

~<

HFA1114

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

63 mils x 44 mils x 19 mils
1600llm x 1130llm x 4831lm

Type: Nitride
Thickness: 4kA ±0.5kA

METALLIZATION:

TRANSISTOR COUNT:

52

Type: Metal 1: AICu(2%)rriW
Thickness: Metal 1: 8kA ±a.4kA

SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kA ±a.8kA

Floating (Recommend Connection to V-)

Metallization Mask Layout
HFA1114

Ne

+IN

y-

-IN

Ne

Ne

SN

y+

OUT

3-604

HFA1115

HARRIS
SEMICONDUCTOR

225M Hz, Low Power, Output
Limiting, Closed Loop Buffer Amplifier

November 1996

Features

Description

• User Programmable Output Voltage Limiting

The HFA1115 is a high speed closed loop Buffer featuring both
user programmable gain and output limiting. Manufactured on
Harris' proprietary complementary bipolar UHF-l process, the
HFA 1115 also offers a wide -3dB bandwidth of 225M Hz, very
fast slew rate, excellent gain flatness and high output current.

• High Input Impedance ••...........••.•..••.. 1Mn
• Differential Gain. . • . . . . . . • . . . • . . . . • • . . • . •. 0.02%
• Differential Phase. • • . . . . • • • • • • • . • . .• 0.03 Degrees
• Wide -3dB Bandwidth (Ay = +2) •.••......•• 225MHz
'. Very Fast Slew Rate (Ay = -1) .••.••......• 1135V11lS
• Low Supply Current ....•.....•.•...•.•..•. 7.1mA
• High Output Current ...•.•••..••.•.•••.•••. 60mA
• Excellent Gain Accuracy ••.•.••••••••••••• 0.99VN
• User Programmable For Closed-Loop Gains of +1, -1
or +2 Without Use of External Resistors
• Fast Overdrive Recovery. • • • • . . • . • . • • • . • . . .. <1 ns
• Standard Operational Amplifier Pinout

Applications
• Flash AID Drivers

This buffer is the ideal choice for high frequency applications
requiring output limiting, especially those needing ultra fast
overload recovery times. The limiting function allows the
designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The HFA1115 also allows for voHage gains of +2, + 1,
and -1, without the use of external resistors. Gain selection is
accomplished via connections to the inputs, as described in
the "Application Information" text. The result is a more flexible
product, fewer part types in inventory, and more efficient use
of board space.
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path, should a higher closed loop gain be needed at
a future date. For Military product, refer to the HFA 1115/883
data sheet.

Ordering Information

• Video Cable Drivers

PART NUMBER
(BRAND)

• High Resolution Monitors

TEMP.
RANGE (DC)

PKG.
NO.

PACKAGE

• Professional Video Processing
HFA11151P

-40 to 85

8 Ld PDIP

E8.3

• Video Digitizing Boards/Systems

HFA11151B
(H11151)

-40 to 85

8 LdSOIC

M8.15

• BaHery Powered Communications

HFA11XXEYAL

• Medical Imaging

Pinout

High Speed Op Amp DIP Evaluation Board

Pin Descriptions
HFA1115
(PDIP, SOIC)
TOP VIEW

NAME

PIN NUMBER

-IN

2

Inverting Input

+IN

3

Non-Inverting Input
Negative Supply

V-

4

VL

5

Lower Output Limit

OUT

6

Output

V+

7

Positive Supply

VH

8

Upper Output Limit

CALrrION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-605

DESCRIPTION
No Connection

NC

File Number

3606.3

..J

etC/)
Za::
O!!:!
-IL.

~:::i

a::c.

W:iE

~et

HFA1115
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ..............••......•.•.•• 11 V
DC Input Voltage ...•.•.•..............•••.....•. VSUPPLY
Output Current (Note 2) ..•............. Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) •.. 600V

Thermal ReSistance (Typical, Note 1)

Operating Conditions
Temperature Range . . . . . • . . . . . . . . . . . . . . . . . .. -40°C to 85°C
Supply Voltage Range (Typical) .................... 5Vto 10V

9JA <"CIW)

PDIP Package.............................
130
SOIC Package. . . . . . . . . . • . . . • . • . • • . • • . . • . . •
170
Maximum Junction Temperature (Die) ....•.•...••.•...••. 175°C
Maximum Junction Temperature (Plastic Packages) •...... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os) ..........•. 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and opera.on
of the device at these or any other conditions above those indicated in the opera'onal sections of this specificallon Is not Implied.

NOTES:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.
2. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty
cycle) output current should not exceed 30mA for maximum reliability.

Electrical Specifications

VSUPPLY = ±5V, A.t = +1, RL = 1000, Unless Otherwise Specified

PARAMETER

(NOTE 3)
TEST
LEVEL

TEST
CONDITIONS

TEMP.
('lC)

MIN

TYP

MAX

UNITS

mV

INPUT CHARACTERISTICS
Output Offset Voltage

A

25

A

Full

B

Full

2

10

3

15

mV

-

22

70

INfDc

.1.VCM=±1.8V

A

25

42

.1.VCM= ±1.8V

A

45

85

40

44

A

-40

40

45

.1.Vps=±1.8V

A

25

45

49

.1.Vps=±1.8V

A

85

43

48

.1.Vps=±1.2V

A

-40

43

48

-

.1.VCM =±1.2V

A

25

-

1

15

A

Full

3

25

j.tA

B

Full

30

80

nAfDC

Average Output Offset Voltage Drift
Common-Mode Rejection RatiO

Power Supply Rejection Ratio

-

Non-Inverting Input Bias Current

Non-Inverting Input Bias Current Drift

-

-

dB
dB
dB
dB
dB
dB

j.tA

.1.VCM= ±1.8V

A

25

0.8

1.1

-

MO

.1.VCM= ±1.8V

A

85

0.5

1.4

-

MO

.1.VCM=±1.2V

A

-40

0.5

1.3

-

Inverting Input Resistance

C

25

280

350

420

Input Capacitance

C

25

-

1.6

Input Voltage Common Mode Range
(Implied by Via CMRR and +RIN Tests)

A

25,85

±1.8

±2.4

A

-40

±1.2

±1.7

Non-Inverting Input Resistance

-

Input Noise Voltage Density

f= 100kHz

B

25

Non-Inverting Input Noise Current Density

f= 100kHz

B

25

Av=-1

A

25

-0.98

A

Full

-0.975

A

25

A

7

MO
0
pF

-

-

V
V
nVNHz

-

pANHz

-0.996

-1.02

VN

-1.000

-1.025

VN

0.98

0.992

1.02

VN

Full

0.975

0.993

1.025

VN

A

25

1.96

1.988

2.04

VN

A

Full

1.95

1.990

2.05

VN

3.6

TRANSFER CHARACTERISTICS
Gain

A.t = +1
Av=+2

3-606

HFA1115
Electrical Specifications

VSUPPLY = ±5V, """ = + I, RL = 1000, Unless Otherwise Specified (Continued)

TEST
CONDITIONS

PARAMETER

(NOTE 3)
TEST
LEVEL

TEMP.

(OC)

MIN

TYP

MAX

UNITS

-

MHz

AC CHARACTERISTICS

Av=-1

B

25

-

225

Av = +1, +Rs = 6200

B

25

-

170

MHz

Av=+2

B

25

225

MHz

Av=-1

B

25

157

MHz

Av = +1, +RS = 6200

B

25

-

140

MHz

Av=+2

B

25

-

125

MHz

Gain Flatness
(to 25MHz, VOUT = 0.2Vp_p)

""" = +1, +RS = 6200

B

25

±!l.1

dB

Av=+2

B

25

Gain Flatness
(10 50MHz, VOUT = 0.2Vp_p)

""" = +1, +Rs = 6200

B

25

Av=+2

B

25

-

Av=-1

A

25

A

Full

A

-3dB Bandwidth
(VOUT = 0.2Vp_p)

Full Power Bandwidth
(VOUT = 5Vp_p at Av = +21-1,
4Vp_p atAv = +1)

-

-

±0.04

dB

±0.25

dB

±!l.1

dB

±3.0

±3.2

V

±2.B

±3.0

25,B5

50

55

A

-40

2B

42

B

25

-

90

-

OUTPUT CHARACTERISTICS

Output Voltage Swing

Output Current

Av=-I.RL=500

Output Short Circuit Current
Closed Loop Output Impedance

DC,Av=+2

B

25

0.07

Second Harmonic Distortion
(Av = +2, VOUT = 2Vp_p)

10MHz

B

25

-50

20MHz

B

25

10MHz

B

25

20MHz

B

Third Harmonic Distortion
(Av = +2, VOUT = 2Vp_p)
TRANSIENT RESPONSE

-

V
mA

-

mA
mA
0
dBc

-

-45
-50

-

dBc

25

-

-45

-

dBc

-

1.7

-

ns

dBc

Av = +2, Unless Otherwise Specified

Rise and Fall Times
(VOUT = 0.5Vp_p)

Rise Time

B

25

Fall Time

B

25

Overshoot
(VOUT = 0.5Vp_p, VIN 'RISE = 2.5ns)

+OS

B

25

-OS

B

25

Slew Rate
(VOUT= 5Vp_p, Av = -1)

+SR

B

25

-SR

B

25

Slew Rate
(VOUT= 4Vp_p, Av = +1, +RS = 6200)

+SR

B

25

-SR

B

25

Slew Rate
(VOUT = 5Vp_p, Av = +2)

+SR

B

25

-SR

B

25

Settling Time
(VOUT = +2V to OV step)

ToO.l%

B

25

To 0.05%

B

25

To 0.02%

B

25

-

30

Differential Gain

f = 3.58MHz, Av = +2,
RL= 1500

B

25

-

0.02

Differential Phase

f = 3.58MHz, Av = +2,
RL = 1500

B

25

-

0.03

0

-

1660

-

1.9

-

0

%
%
V/JJ.s

1125

-

BOO

-

V/JJ.s

1265

-

V/JJ.s

1135

870

-

ns

15

V/JJ.s
V/JJ.s

V/JJ.s

-

ns

-

ns

20

ns

VIDEO CHARACTERISTICS

3-607

%

-

Degrees

..J



+INPUT (PIN 3)

Another straightforward approach is to add a 6200 resistor
in series with the positive input. This resistor and the
HFA 1115 input capacitance form a low pass filter which rolls
off the signal bandwidth before gain peaking occurs. This
configuration was employed to obtain the datasheet AC and
transient parameters for a gain of + 1.

-INPUT (PIN 2)

-1

GND

Input

+1

Input

NC (Floating)

+2

Input

GND

Unity Gain Considerations

PC Board Layout

Unity gain selection is accomplished by floating the -Input of
the HFA1115. Anything that tends to short the -Input to GND,
such as stray capacitance at high frequencies, will cause the
amplifier gain to increase toward a gain of +2. The result is
excessive high frequency peaking, and possible instability.
Even the minimal amount of capacitance associated with
attaching the -Input lead to the PCB results in approximately
3dB of gain peaking. At a minimum this requires due care to
ensure the minimum capacitance at the -Input connection.

The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The

use of low inductance components such as chip resistors and chip capacitors is strongly recommended,
while a solid ground plane is a mustl
Attention should be given to decoupling the power supplies.
A large value (lOI1F) tantalum in parallel with a small value
(O.lI1F) chip capacitor works well in most cases.

3-608

HFA1115
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized. or isolated as discussed in the
next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier's
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.
An example of a good high frequency layout is the Evaluation Board shown in Figure 1.

Driving Capacitive Loads
Capacitive loads, such as an AID input, or an improperly
terminated transmission line will degrade the amplifier's
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (Rsl in series with the output
prior to the capacitance.

RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of
225M Hz. By decreasing RS as CLincreases the maximum
bandwidth is obtained without sacrificing stability.

Evaluation Board
The performance of the HFAll15 may be evaluated using
the HFA 11 XX Evaluation Board, slightly modified as follows:
4. Remove the 500n feedback resistor (R2l, and leave the
connection open.

=

5. a. For Av +1 evaluation, remove the 500n gain setting
resistor (Rll, and leave pin 2 floating.
b. For AV +2, replace the 500n gain setting resistor with
a On resistor to GND.

=

The layout and modified schematic of the board are shown
in Figure 1.
To order evaluation boards (Part Number HFA11XXEVAL),
please contact your local sales office.

.J

TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS

ctUJ

Za:

PEAKING (dB)

BW(MHz)

+SRI-SR (V/j1S)

±O.ldB GAIN FLATNESS
(MHz)

Remove Pin 2

2.5

400

1200/850

20

+RS = 6200

0.6

170

1125/800

25

0

165

1050m5

65

0

200

8751550

45

0.2

190

900/550

19

APPROACH

+Rs = 6200 and Remove Pin 2
Short Pins 2, 3
1OOpF cap. between pins 2, 3

.

(Av =+1)
or 00 (Av = +2)
00

TOP LAYOUT

.-----~----~.

.

o
o tJ.ij..

.....- - - _......-o+5V

o
4

-sv

L -__________- - ' .

5

re

VL

GND

GND'V

FIGURE 1. EVALUATION BOARD SCHEMATIC AND LAYOUT

3-609

•

0

w:e

-u..

!ci::J
a:Q.
~ct

BOTTOM LAYOUT

•

O!!:!

••
0

0
00

•

•

HFA1115

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

59 mils x 58.2 mils x 19 mils
1500lLm x 1480ILm x 483ILm

Floating (Recommend Connection to V-)
PASSIVATION:

METALLIZATION:

Type: Nitride
Thickness: 4kA ±O.5kA

Type: Metal 1: AICu(2%)mW
Thickness: Metal 1: 8kA ±O.4kA

TRANSISTOR COUNT:
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kA ±O.8kA

89

Metallization Mask Layout
HFA1115

-IN

.:. c:: c

•

v+

OUT

+IN

3-610

HARRIS
SEMICONDUCTOR

HFA1118, HFA1119

ADVANCE INFORMATION
November 1996

500MHz Programmable Gain Video Buffers
with Output Limiting and Output Disable

Features

Description

• User Programmable For Closed Loop Gains of ±1, or
+2 Without Use of External Resistors

The HFA1118, and HFA1119 are high speed, low power,
closed loop buffers built with Harris' proprietary complementary
bipolar UHF-1 process. Both buffers allow for selection of voltage gains of +2 and ±1, without the use of external gain setting resistors.

• User Programmable Output Limiting (HFA1119)
• Standard Operational Amplifier Pinout
• Excellent Gain Accuracy. • . . • • . . . . • . • . . • . •. ±O.S%
• Wide -3dB Bandwidth (Av = +2) ..•.•.••.•.• SOOMHz
• Gain Flatness (to 2S0MHz) .•.••...•••.•..•. ±O.SdB
• Very Fast Slew Rate (Av = +2) ....••.•••••• 1200V/~
• Differential Gain/Phase. • • • . • •. 0.02%/0.02 Degrees
• Fast Output EnablelDisable .....•••.•••..•.• 10ns

Applications
• Flash AID Drivers

The HFA 1119 is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra
fast overload recovery times. For added flexibility, the
HFA 1119 also features an active low, TTUCMOS compatible
disable input, which when activated forces the output to a high
impedance state, and reduces supply current.
The HFA 1118 features a TTUCMOS compatible output disable pin which is user programmable for polarity (active high
or low). This feature eliminates the inverter required between
amplifiers in multiplexer configurations. The ultra-fast (10ns)
enable and disable times make the HFA1118 and HFA1119
the obvious choices for pixel switching and other high speed
multiplexing applications.

• Video Cable Drivers

PART NUMBER

TEMP.
RANGE (oC)

• PC Multimedia Systems

HFA11181p, HFA11191P

-401085

8 Ld PDIP

E8.3

• Video Pixel Switching

HFA11181B, HFA11191B

·401085

8 LdSOIC

M8.15

• Medical Imaging

HFA11XXEVAL

• Oscilloscopes and Analyzers

PKG.
NO.

PACKAGE

DIP Evaluation Board for High Speed Op
Amps

Pinouts
HFA1118 PIN DESCRIPTIONS

HFA1118
(PDIP, SOIC)
TOP VIEW
THRESHOLD SET

PIN NAME

DESCRIPTION

Threshold Set

Optional Logic Threshold Set Main1Bins Disable
Pin TTL Compatibility with Asymmetrical Supplies
(e.g., +10V, OV)

Polarity Set

Defines Polarity of Disable Input. High or Floating
Selects Active Low Disable (i.e., DiS).

DIS/DIS

TTL Compatible Disable Input. Output is Driven
to a True Hi-Z State When Active. Polarity
depends on state of Polarity Set Pin.

1

5 POLARITY SET

HFA1119
(PDIP, SOIC)
TOP VIEW

HFA1118 DISABLE FUNCTIONALITY
POLARITY SET (PIN 5)

DISABLE (PIN 8)

High or Float

High or Float

Enabled

High or Float

Low

Disabled

Low

High or Float

Disabled

Low

Low

Enabled

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-611

O!!!
-u.

!cc:J
a: a.
W:::i

Ordering Information

• Professional Video Processing

...I


.§.

Ay=+2
1.2

~

0.6

~

30

~

0.3

~

0

...

!:i
!;
A.
!;
0

...

!:i

~

!;

-30

!l0;

-60
-90

,..

0.9

60

0
·0.3
.(I.B

-

.(I.e

I--'

·1.2

-120
TIME (SnalDIV.)

TIME (SnaIDIV.)

FIGURE 3. SMALL SIGNAL PULSE RESPONSE

r

FIGURE 4. LARGE SIGNAL PULSE RESPONSE

r

II

IN
OVTOO.5V

..J

1 1

ccrn
za:

1

IN
OVT01V

O!!!
-u.,

~:J
a: a..

1

E

1-

W:::ii

1

~cc

,I
1
1
1 1

II

OUT
OVT01V

OUT

II

OVT01V

- - --I

---- - --

--i iP--

-.,1

- -- - -

1

Ay .. +2, VH = 1V, VL = -1V, 2X OVERDRIVE
TIME (10naIDIV.)

TIME (10naIDIV.)

FIGURE 5. UN CLAMPED PERFORMANCE

FIGURE 6. CLAMPED PERFORMANCE

Vour .. 200mVp.p

iii'
0
z

:!!.

GAIN

~ ·3

Q

Aya·S

·6

~ ~

Ay .. -10

Jr :::Hi'fIt~IP~~+t\.. ~90

1-+H+1tt---t-+++tttttAy = +2
Ay=+6

HH~r-~~~

0.3

......... ~
Vi-"

Ay= +11
10
100
FREQUENCY (MHz)

-180

Ay=-5

!lI
~I_-UO~

FIGURE 7. NON-INVERTING FREQUENCY RESPONSE

IIIII

,...
'~~

PHASJ

f-e.

I J-.I 360 A.
1K

~~

I-'"

Ay=-20

~ -12

I-t1fttttt-++++ttHiAy ..

I IIIII
' 4~I-r

Ay=-10
Ay=-20
0.3

Viii'

II:

t:I

i

~~

V"

-180 A.
1K

FIGURE 8. INVERTING FREQUENCY RESPONSE

3-617

iii'

o

Vi.;'

10
100
FREQUENCY (MHz)

180

90

HFA1130

Typical Performance Curves
Av = +1, VOUT = 200mVp.p

11111

6
I

VSUPPLY= ±5V, RF = 510Q, TA = 25°C, RL = lOOn. Unless Otherwise Specified (Continued)

~lll~

11111

I II
I II

RL = 100n

~ o~~G~A'~~~r-~I~l.1~IIII~lb~~~
~ -3
L~ ~ ~lro;:±::""~HH

RL = 50n

500'

PHASE

II

RL =
RL =100n

~

0

~
CI

-10

RL = 100n .e::
RL = 1k.Q 10
100
FREQUENCY (MHz)

0.3

20

Av=+2

0.500Vp_p ' ""
0.920Vp_p
.1.63Vp-p/

0

0

w

N

~

1.00Vp-~ ....
1.84Vp_p '

::&

-20

3.26Vp.p'

0

-30

c(

a:

z

10

100

0

0.3

1K

10

::::i
c(

::&

a:
0

z

Av=+1
950
O.96Vp-p
3.89Vp-p

t""

~

'N' 900

1'-0...

i'-...

::c

!-'

!.
::c

-30

850

6
~z

800

III

750

c(

......... ........

"

700
0.3

1K

FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

Av=+6

10
-20

100

FREQUENCY (MHz)

0
-10

f

10

-10

w

FIGURE 11_ FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

~CI

lJl

III
0.32Vp_p

FREQUENCY (MHz)

10

-270
-360
1K

C

0.3

20

0
a:
-90

1

CI

-30

~

i9

I.......

RL =500-V
RL = 1k.Q

~Ht~-+~tH~--+-t+Ht~-t-+*1tfl-180 ~

iii'
~
z

I

-20

iii'

RL = 50n f-H-l'tAii

I

FIGURE 10. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

Uot!.~1

10

iii'

PHASE

1-+H+IIt---+-+-t-HttH--+-t-1t-

1K

Av=+1

~Ht~-+~tH~---t-i

1-H1-tH-H-- RL = 1000

rrI :::i

10
100
FREQUENCY (MHz)

-8

z

w

FIGURE 9. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

20

~~

-180~

1~~'~100n

I I RL=1k.Q
1

!§

-90

RL=1~1I

o.3

i9

o

" I ITTTJI"""-.
I

1111111

~ 3~~~-+~tH~--+-rRrLn=~1k.Qmr-~-+++~

RL=1k.Q_

II

Av = +2, VOUT = 200mVp_p

iii'

10
FREQUENCY (MHz)

100

1K

-SO

-25

0

25

50

75

100

125

TEMPERATURE (OC)

FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

3-618

FIGURE 14. -3dB BANDWIDTH vs TEMPERATURE

HFA1130
Typical Performance Curves vSUPPLY = ±5V, RF = 51 OQ, TA = 25°C, RL = 100Q, Unless Otherwise Specified
Ay=+2

Ay=+2

+2.0

~-----

(Continued)

+1.5

i3

0

iD -0.05
:g.

"'"

+1.0

III(.'j

+0.5

e.

l\-

0

z

-0.10

Cl

-0.15

~

-0.5

-0.20

~

-1.0

;;;:

~

II

-2.0

\

o

100

15

30

45

FREQUENCY (MHz)

;;;:

Cl 2.5

.........

0.25

.......

PHASE

~
a:

GAIN

'"'" " ....
"'-

0.1

0.01

1

105 120

~

135

150

10

100

i
~

,

180

iii'

135

III

a:

w

90

~

45

~

\

0.2
0

~

-0.4

...I

600V

Thermal Resistance (Typical, Note 2)

9JA (oclW)

PDIP Package .......................... , ..
130
170
SOIC Package.............................
Maximum Junction Temperature (Die Only) ................ 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range ........................ , -40°C to 85°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings'may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those Indicated In the operational sections of this specification Is not Implied.

NOTES:
1. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle)
output current must not exceed 30mA for maximum reliability.
2. 9JA Is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY =±5V, "'" = +1, RF = 5100 (Note 4), RL = 1000, Unless Otherwise Specified

PARAMETER

(NOTE 3)
TEST
LEVEL

TEMP.
(oC)

MIN

A

25

-

A

Full

B

Full

aVCM=±1.8V

A

aVCM=±1.8V

A

aVCM=±1.2V

A

-40

45

48

aVpS=±1.8V

A

25

50

54

aVps=±1.8V

A

85

47

50

liVpS =±1.2V

A

-40

47

50
6

15

-

10

25

/lA
/lA

TEST CONDITIONS

TYP

MAX

UNITS

mV

INPUT CHARACTERISTICS

Input Offset Voltage

Average Input Offset Voltage Drift
Input Offset Voltage
Common-Mode Rejection Ratio

Input Offset Voltage
Power Supply Rejection Ratio

Non-Inverting Input Bias Current

Non-Inverting Input Resistance

8

mV

-

1

10

/lVPC

25

47

50

85

45

48

-

A

25

A

Full

dB
dB
dB
dB
dB

-

dB

B

Full

-

5

60

nAPC

A

25

-

0.5

1

aVps=±1.8V

A

85

-

0.8

3

IlAIV
IlAIV

aVps=±1.2V

A

-40

-

0.8

3

/lAN

aVCM=±1.8V

A

25

0.8

2

aVCM=±1.8V

A

85

0.5

1.3

-

aVCM=±1.2V

A

.-40

0.5

1.3

Inverting Input Bias Current

Inverting Input Bias Current Drift
Inverting Input Bias Current
Common-Mode Sensitivity

5

aVps=±1.8V

Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current
Power Supply Sensitivity

2
3

A

25

A

Full

B

Full

aVCM=±1.8V

A

25

aVCM= ±1.8V

A

85

aVCM=±1.2V

A

-40

3-624

-

MO
MO
MO

2

7.5

5

15

/lA
/lA

60

200

nAPC

3

6

4

8

4

8

IlAIV
IlAIV
IlAIV

HFA1135
Electrical Specifications

VSUPPLY = ±5V, Ay = +1, RF = 5100 (Note 4), RL = 1000, Unless Otherwise Specilied (Continued)
(NOTE 3)
TEST
LEVEL

TEMP.
(oC)

MIN

TYP

MAX

UNITS

AVps=±1.8V

A

25

.

2

5

AVps=±1.8V

A

85

4

8

!!AN
!!AN

4

8

JlAN

40

-

TEST CONDITIONS

PARAMETER
inverting Input Bias Current
Power Supply Sensitivity

-

A

-40

Inverting Input Resistance

C

25

Input Capacitance (Either Input)

C

25

-

1.6

Input Voltage Common Mode Range
(Implied byVIO CMRR, +RIN' and -IBIAS
CMS tests)

A

25,85

±1.8

±2.4

A

-40

±1.2

±1.7

AVps=±1.2V

1= 100kHz

B

25

-

3.5

Non-Inverting Input Noise Current Density 1= 100kHz

B

25

-

2.5

Inverting Input Noise Current Density

1= 100kHz

B

25

Ay=-1

C

25

Ay = +1, RF = 1.5kO

B

25

Ay = +2, RF = 2500

B

25

Ay = +2, RF = 3300

B

25

Ay = -1, RF = 3300

B

25

Ay = +1, RF = 1.5kQ

B

25

Ay = +2, RF = 2500

B

25

Ay = -1, RF= 3300

B

25

Ay = +1, RF = 1.5kQ

B

25

±O.10

Ay = +2, RF = 2500

B

25

±O.02

Ay = +2, RF = 3300

B

25

Ay=+1, RF= 1.5kQ

B

25

Ay = +2, RF = 2500

B

25

Ay = +2, RF = 3300

B

25

A

Full

Input Noise Voltage Density

0
pF
V
V
nV/VHz
pANHz

20

-

pA/VHz

-

500

-

kO

-

660

-

MHz

-

360

TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain
AC CHARACTERISTICS

Ay = +2, RF = 2500, Unless Otherwise Specilied

-3dB Bandwidth (VOUT = 0.2Vp_p)

Full Power Bandwidth
(VOUT = 5Vp_p at Ay = +21-1,
4Vp_patAy=+1)

Gain Flatness
(to 25MHz,VOUT = 0.2Vp_p)

Gain Flatness
(to 50MHz,VOUT = 0.2Vp_p)

Minimum Stable Gain
OUTPUT CHARACTERISTICS

..J

-

MHz
MHz

a:

290

MHz

g;cr:

90

MHz

315

130

-

170

±O.02
±a.22
±a.07

-

±a.03
1

MHz
MHz

-

dB
dB
dB
dB
dB
dB
VN

RF = 5100, Unless Otherwise Specified

Output Voltage Swing

Output Current

Ay= -1, RL = 1000

Ay = -1, RL = 500

Output Short Circuit Current

A.t = +2, RF = 2500

A

25

±3

±3.4

A

Full

±2.8

±3

A

25,85

50

60

A

-40

28

42

B

25

B

25

Closed Loop Output Impedance

DC,

Second Harmonic Distortion
(Ay = +2, RF = 2500, VOUT = 2Vp_p)

10MHz

B

25

20MHz

B

25

10MHz

B

25

20MHz

B

25

Third Harmonic Distortion
(Ay = +2, RF = 2500, VOUT = 2Vp_p)

3-625

-

90
0.07
-50
-45
-50

-

cr:U)

za:

O!!!
-IL

-45

-

V
V

rnA
rnA

rnA

n
dBc
dBc
dBc
dBc

ti::i
0.
W:5

HFA1135
Electrical Specifications

VSUPPLY = ±5V, ""' = +1, RF = 5100 (Note 4), RL = 1000, Unless Otherwise Specified (Continued)

TEST CONDITIONS

PARAMETER
TRANSIENT CHARACTERISTICS

(NOTE 3)
TEST
LEVEL

TEMP.
(oC)

MIN

TYP

MAX

-

Rise and Fall Times
(VOUT = 0.5Vp_p)

Rise Time

B

25

0.81

Fall Time

B

25

1.25

Overshoot (Note 5)
(VOUT = 0 to 0.5V, VIN tRISE = 2.5ns)

+OS

B

25

3

-OS

B

25

5

Overshoot (Note 5)
(VOUT = 0.5Vp_p, VIN fAlSE = 2.5ns)

+OS

B

25

-OS

B

25

Slew Rate
(VOUT = 4Vp_p, Av = + 1, RF = 1.51<0)

+SR

B

25

-SR

B

25

Slew Rate
(VOUT = 5Vp_p, Av = +2, RF = 2500)

+SR

B

25

-SR

B

25

-

Slew Rate
(VOUT = 5Vp_p, Av= -1, RF = 3300)

+SR

B

25

-

2300

-SR

B

25

-

1200

Settling Time
(VOUT = +2V to OV step)

To 0.1%

B

25

To 0.05%

B

25

-

20

To 0.02%

B

25

-

30

VIDEO CHARACTERISTICS

UNITS

""' = +2, RF = 2500, Unless Otherwise Specified

-

2

-

875

10

510
1530
850

15

ns
ns
%
%
%
%

V/IlS
V/IlS
V/JlS
V/JlS
V/IlS
V/JlS
ns
ns
ns

Av = +2, RF = 2500,Unless Otherwise Specified

Differential Gain (f = 3.58MHz)

Differential Phase (f = 3.58MHz)

RL = 1500

B

25

0.02

RL = 750

B

25

0.03

RL= 1500

B

25

-

0.04

RL=750

B

25

-

0.06

-

%
%
Degrees
Degrees

OUTPUT UMITING CHARACTERISTICS ""' = +2, RF = 2500, VH = +1V, VL = -1V, Unless Otherwise Specified
Clamp Accuracy
Overdrive Recovery nme

VIN =±2V, Av= -1, RF= 5100

A

Full

-125

25

125

mV

-

0.8

-

ns

B

25

Negative Clamp Range

B

25

-5.0 to +2.0

Positive Clamp Range

B

25

-2.0 to +5.0

Clamp Input Bias Current

A

25

A

Full

VIN=±1V

-

V
V

50

200

80

200

JlA
JlA

POWER SUPPLY CHARACTERISTICS
Power Supply Range

C

25

±4.5

-

±5.5

V

Power Supply Current

A

25

6.6

6.8

7.1

rnA

A

Full

6.4

6.9

7.3

rnA

NOTES:
3. Test Level: A. Production Tested.; B. Typical or Guaranteed Limit Based on Characterization.; C. Design Typical for Information Only.
4. The optimum feedback resistor for the HFA1135 atAv= +1 is 1.51<0. The Production Tested parameters are tested with RF= 5100
because the HFA1135 shares test hardware with the HFA1105 amplifier.
5. Undershoot dominates for output signal swings below GND (e.g., 0.5Vp_p), yielding a higher overshoot limit compared to the
VOUT = OV to 0.5V condition.

3-626

HFA1135

Die Characteristics
PASSIVATION:

DIE DIMENSIONS:
59 mils x 58.2 mils x 19 mils
1500ILm

Type: Nitride
Thickness: 4kA ±O.5kA

x 1480ILm x 4a3ILm

METALLIZATION:

TRANSISTOR COUNT:

Type: Metal 1: AICu(2%)fTiW
Thickness: Metal 1: akA ±O.4kA

89
PROCESS:

Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kA ±O.akA

Bipolar Dielectric Isolation

SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to v-)

Metallization Mask Layout
HFA1135

.:. c:: c

•

·IN

y+

OUT

+IN

y.

3-627

HFA1145
November 1996

330M Hz, Low Power, Current Feedback Video
Operational Amplifier with Output Disable

Features

Description

• Low Supply Current ....................... 5.8mA

The HFA 1145 is a high speed, low power current feedback
amplifier built with Harris' proprietary complementary bipolar
UHF-1 process.

• High Input Impedance ••••••••..•.••••.•.••.• 1Mil
• Wide ·3dB Bandwidth ••......•....•••..•• 330MHz
• Very Fast Slew Rate .••••••••••...••••.•. 1000Vllts
• Gain Flatness (to 75MHz) ••••••...••••...• ±O.1dB
• Differential Gain. • • .. • . • • . • • • • • . . . . . • • . . •. 0.02%
• Differential Phase. • • • • • . . • . • • • • . . . .. 0.03 Degrees
• Output EnablelDisable Time .••••••....• 180n8l35ns

This amplifier features a TTUCMOS compatible disable control, pin 8, which when pulled low reduces the supply current
and forces the output into a high impedance state. This
allows easy implementation of simple, low power video
switching and routing systems. Component and composite
video systems also benefit from this op amp's excellent gain
flatness, and good differential gain and phase specifications.

• Pin Compatible Upgrade for CLC410

Multiplexed AID applications will also find the HFA1145 useful as the AID driver/multiplexer.

Applications

The HFA 1145 is a low power, high performance upgrade for
the CLC410.

• Flash AID Drivers
• Video Switching and Routing
• Professional Video Processing
• Video Digitizing Boards/Systems
• Multimedia Systems
• RGB Preamps
• Medical Imaging

For Military grade product, please refer to the HFA1145/883
data sheet.

Ordering Information
PART NUMBER
(BRAND)

TEMP. RANGE
(DC)

PKG.
NO.

PACKAGE

HFA11451P

-40 to 85

8 Ld PDIP

E8.3

HFA11451B
(H11451)

-40 to 85

8LdSOlC

M8.15

• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications

HFA11XXEVAL

DIP Evaluation Board for High Speed Op Amps

Pinout
HFA1145
(PDIP, SOIC)
TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3-628

File Number

3955.2

HFA1145
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ l1V
DC Input Voltage ................................ VSUPPLY
Differential Input Voltage ................................ 8V
Output Current (Note 1) ................ Short Circuit Protected
30mA Continuous
60mA :<> 50% Duty Cycle
ESD Rating ....................................... >600V

Thermal Resistance (Typical, Note 2)
9JA (oCIW)
PDIP Package.............. ...... ... ..... .
130
170
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Die Only) ................ 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C

CAUTION: Stresses above those /lsted in "Absolute Maximum Ratings' may cause permanent damage to the device. This Is a stress only rating and operation
of the device at these or any other condiffons above those indicated In the operational sections of this specification Is not Implied.

NOTES:
1. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle)
output current must not exceed 30mA for maximum reliability.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications VSUPPLY =±5V, Av= +1, RF= 5100, RL = 1000, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

(NOTE 3)
TEST
LEVEL

TEMP.

fC)

MIN

TYP

MAX

UNITS

INPUT CHARACTERISTICS

Input Offset Voltage

Average Input Offset Voltage Drift
Input Offset Voltage
Common-Mode Rejection Ratio

Input Offset Voltage
Power Supply Rejection Ratio

mV

B

Full

-

1

10

Jl.VPC

-

dB

-

dB

dB

Jl.A

25

47

50

85

45

48

aVCM=±1.2V

A

-40

45

48

aVpS=±1.8V

A

25

50

54

aVpS=±1.8V

A

85

47

50

dB

dB

A

-40

47

50

-

A

25

6

15

A

Full

10

25

Jl.A

B

Full

-

5

60

nAPC

0.5

1

0.8

3

i!AIV
i!AIV
i!AIV

dB

aVps=±1.8V

A

25

aVps=±1.8V

A

85

aVpS=±1.2V

A

-40

0.8

3

aVCM=±1.8V

A

25

0.8

1.2

-

aVCM=±1.8V

A

85

0.5

0.8

aVCM=±1.2V

A

-40

0.5

0.8

-

MO

A

25

2

7.5

A

Full

5

15

Jl.A
Jl.A

60

200

nAPC

3

6

4

8

4

8

i!AIV
i!AIV
i!AIV
i!AIV
i!AIV
i!AIV

Inverting Input Bias Current Drift

Inverting Input Bias Current
Power Supply Sensitivity

8

A

Inverting Input Bias Current

Inverting Input Bias Current
Common-Mode Sensitivity

5

3

A

Non-Inverting Input Bias Current Drift

Non-Inverting Input Resistance

2

Full

aVCM=±1.8V

aVps=±1.2V

Non-Inverting Input Bias Current
Power Supply Sensitivity

25

A

aVCM=±1.8V

Non-Inverting Input Bias Current

mVo'

A

B

Full

aVCM=±1.8V

A

25

aVCM=±1.8V

A

85

aVCM=±1.2V

A

-40

aVpS= ±1.8V

A

25

aVps=±1.8V

A

85

A

-40

C

25

aVpS=±1.2V
Inverting Input Resistance

3-629

-

-

-

MO
MO

2

5

4

8

4

8

60

-

0

HFA1145
Electrical Specifications

VSUPPLY = ±5V, Av= +1, RF= 5100, RL = 1000, Unless Otherwise Specified (Continued)
(NOTE 3)
TEST
LEVEL

TEMP.
~C)

MIN

TYP

MAX

UNITS

Input Capacitance

C

25

-

1.6

pF

Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN' and -I BIAS
CMS tests)

A

25,85

±1.8

±2.4

A

-40

±1.2

±1.7

-

-

3.5

-

nVNRZ

2.5

-

pAl..JHz

TEST CONDITIONS

PARAMETER

V
V

Input Noise Voltage Density (Note 6)

, = 100kHz

B

25

Non-Inverting Input Noise Current Density
(Note 6)

, = 100kHz

B

25

Inverting Input Noise Current Density
(Note 6)

, = 100kHz

B

25

-

20

-

pA/..JHz

C

25

-

500

-

kO

-

MHz

TRANSFER CHARACTERISTICS

I Av=-1

Open Loop Transimpedance Gain

I

AC CHARACTERISTICS

RF = 5100, Unless Otherwise Specified

-3dB Bandwidth
(Vour = 0.2Vp_p, Note 6)

Av = +1, +Rs = 5100

B

25

270

B

Full

240

Av= -1, RF= 4250

B

25

Av=+2

B

25

B

Full

B

25

B

Full

Av = +10, RF = 1800

Full Power Bandwidth
(Vour = 5Vp,p at Av = +21-1,
4Vp_p at Av = + 1, Note 6)

Av= +1, +Rs = 5100

B

25

Av=-1

B

25

Av=+2

B

25

Gain Flatness
(Av = +2, Vour = 0.2Vp_p, Note 6)

ro25MHz

B

25

B

Full

B

25

B

Full

To 25MHz

B

25

To 75MHz

B

25

A

Full

ro75MHz

Gain Flatness
(Av = +1, +Rs = 5100, Vour= 0.2Vp_p,
Note 6)
Minimum Stable gain

-

300
330
260
130
90

115
±O.03

-

±O.04
±O.11
±O.22
±O.03

MHz
MHz
MHz
MHz

-

MHz

-

MHz

135
140

MHz

MHz

-

MHz
dB
dB
dB
dB
dB

-

±O.09

dB

1

VN

OUTPUT CHARACTERISTICS Av = +2, RF = 5100, Unless Otherwise Specified
Output Voltage Swing
(Note 6)

Av=-1,RL=1000

Output Current
(Note 6)

Av= -1, RL = 500

Output Short Circuit Current

A

25

±3

±3.4

A

Full

±2.8

±3

A

25,85

50

60

A

-40

28

42

B

25

-

90

Closed Loop Output Impedance (Note 6)

DC

B

25

Second Harmonic Distortion
(Vour = 2Vp_p, Note 6)

10MHz

B

25

20MHz

B

25

10MHz

B

25

20MHz

B

25

30MHz

B

25

-

B

25

-

B

Full

Third Harmonic Distortion
(Vour = 2Vp_p, Note 6)
Reverse Isolation (S12, Note 6)
TRANSIENT CHARACTERISTICS
Rise and Fall Times

0.08
-48

-44

V

-

-

-

-55

-

1.1

I -

-50
-45

V
rnA

rnA
rnA
0
dBc
dBc
dBc
dBc
dB

Av = +2, RF = 5100, Unless Otherwise Specified
Your = 0.5Vp_p

3-630

-

1.4

ns
ns

HFA1145
Electrical Specifications

VSUPPLY = ±5V, Av = +1, RF = 5100, RL = 1000, Unless Otherwise Specified (Continued)

TEST CONDITIONS

(NOTE 3)
TEST
LEVEL

TEMP.

fc)

MIN

TYP

MAX

3

25

-

-

B

25

-

3

-OS

B

25

-

11

+SR

B

25

B

Full

B

25

B

Full

B

25

B

Full

B

25

B

Full

+SR

B

25

B

Full

-SR(Note5)

B

25

B

Full

PARAMETER
Overshoot (Note 4)
(VOUT = 0 to 0.5V, VIN tRISE = 1ns)

+OS

B

25

-OS

B

Overshoot (Note 4)
(Vour = 0.5Vp_p, VIN tRISE = 1ns)

+OS

Slew Rate
(VOUT = 4Vp_p, Av = +1, +RS = 5100)

-SR (Note 5)

Slew Rate
(Vour = 5Vp_p, Av = +2)

+SR

-SR (NoteS)

Slew Rate
(Vour = 5Vp_p, Av = -1)

Settling Time
(VOUT = +2V to OV step, Note 6)

Overdrive Recovery Time
VIDEO CHARACTERISTICS

To 0.1%

B

25

To 0.05%

B

25

To 0.02%

B

25

VIN=±2V

B

25

-

5

1400

-

1200

-

800
700

-

2100

-

1000
975
650

-

-

-

-

-

580

1900
1000
900
15

UNITS
%
%
%
%
V/lJ.s

V/Jls
V/lJ.s

V/Jls
V/JlS
V/lJ.s
V/lJ.s
V/JlS

V/Jls
V/Jls

-

23

V/IJ.S

..J

V/JlS

Za:

ns
ns

30

-

ns

8.5

-

ns

fly = +2, RF = 5100, Unless Otherwise Specified

Differential Gain
(f = 3.58MHz)
Differential Phase
(f = 3.58MHz)

RL= 1500

B

25

RL=750

B

25

RL = 1500

B

25

RL=750

B

25

0.02

-

%

0.03

%

0.03

Degrees

-

Degrees

3

4

rnA

-

0.8

V

100

200

0.05

DISABLE CHARACTERISTICS
A

Full

DISABLE Input Logie Low

A

Full

-

i5lSABl:E Input Logic High

A

25,85

2.0

A

-40

2.4

~=OV

A

Full

DISABLE Input Logic High Current

V~=5V

A

Full

1

15

JlA
JlA

Output Disable Time (Note 6)

VIN=±IV,

B

25

35

-

ns

B

25

-

180

-

2.5

-

pF

3

10

IJ.A

-75

-

dB

±5.5

V

Disabled Supply Current

i5lSABl:E Input Logic Low Current

VOISABLE = OV

~=2.4VtoOV

Output Enable Time (Note 6)

VIN=±tV,
~=OVt02.4V

Disabled Output capacitance

Vr5isAml: = OV

B

25

Disabled Output Leakage

V~ = OV, VIN = +2V,

A

Full

Vour= ±3V

-

Off Isolation

At5MHz

B

25

(\Ii5rsAiiI:E = OV, VIN = tVp_p, Note 6)

At 25MHz

B

25

-

C

25

±4.5

-60

-

V
V

ns

dB

POWER SUPPLY CHARACTERISTICS
Power Supply Range

3-631

~U)

O!:!:!

-u.

!;i::;
a:n.

W:aE
~~

HFA1145
Electrical Specifications VSUPPLY = ±5V, Av = +1, RF = 5100, RL = 100'0, Unless Otherwise Specified (Continued)

PARAMETER
Power Supply Current

TEST CONDITIONS

(NOTE 3)
TEST
LEVEL
A
A

TEMP.
COC)
25
Full

MIN

-

-

TYP
5.8
5.9

MAX
6.1
6.3

UNITS
rnA
rnA

NOTES:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. Undershoot dominates for oUtput signal swings below GND (e.g. 0.5Vp_p), yielding a higher overshoot limit compared to the VOUT = 0 to
0.5V condition. See the ·Application Information" section for details.
5. Slew rates are asymmetrical if the output swings below GND (e.g. a bipolar signal). Positive unipolar output signals have symmetric posItive and negative slew rates comparable to the +SR specification. See the "Application Information" section, and the pulse response
graphs for details.
6. See Typical Perfor:mance Curves for more Information.

Application Information
Optimum Feedback Resistor
Although a current feedback amplifier's bandwidth dependency on closed loop gain isn't as severe as that of a voltage
feedback amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking adVantage of the current feedback amplifier's unique
relationship between bandwidth and RF All current feedback
amplifiers require a feedback resistor, even for unity gain
applications, and Rj; in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency
response. Thus, the amplifier's bandwidth is inversely proportional to RF The HFA1145 design is optimized for RF =5100
at a gain of +2. Decreasing RF decreases stability, resulting in
excessive peaking and overshoot (Note: Capacitive feedback
will cause the same problems due to the feedback impedance
decrease at higher frequencies). At higher gains, however, the
amplifier is more stable so RF can be decreased in a trade-off
of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth. For a gain of +1, a
resistor (+RS) in series with +IN is required to reduce gain
peaking and increase stability.
GAIN

(AcLl
·1
+1
+2
+5
+10

RF(O)
425
510 (+RS =5100)
510
200
180

BANDWIDTH
(MHz)
300
270
330
300
130

Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be :<:500. This is especially important in inverting gain configurations where the non-inverting
input would normally be connected directly to GND.
DISABLE Input TTL Compatibility
The HFA1145 derives an internal GND reference for the digital circuitry as long as the power supplies are symmetrical

about GND. With symmetrical supplies the digital switching
threshold (VTH =(VIH + VILl/2 =(2.0 + 0.8)/2) is 1.4V, which
ensures the TIL compatibility of the DISABLE input. If asymmetrical supplies (e.g. +10V, OV) are utilized, the switching
threshold becomes:
VTH =

V++V-2-+ 1.4V

and the VIH and VIL levels will be VTH ± 0.6V, respectively.
Optional GND Pad (Die Use Only) for TTL Compatibility
The die version of the HFA1145 provides the user with a GND
pad for setting the disable circuitry GND reference. With symmetrical supplies the GND pad may be left unconnected, or tied
directly to GND. If asymmetrical supplies (e.g. +1O\/, OV) are utilized, and TTL compatibility is desired, die users must connect
the GND pad to GND. With an extemal GND, the 'DiSA'BlJ:
input is TTL compatible regardless of supply voltage utilized.
Pulse Undershoot and Asymmetrical Slew Rates
The HFA1145 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches
modes after crossing O\/, resulting in added distortion for signals SWinging below ground, and an increased undershoot on
the negative portion of the output waveform (See Figures 5, 8,
and 11). This undershoot isn't present for small bipolar signals,
or large positive signals. Another artifact of the composite
device is asymmetrical slew rates for output s.ignals with a negative voltage component. The slew rate degrades as the output
signal crosses through OV (See Figures 5, 8, and 11), resulting
in a slower overall negative slew rate. Positive only signals have
symmetrical slew rates as illustrated in the large signal positive
pulse response graphs (See Figures 4, 7, and 10).

PC Board Layout
This amplifier's frequency response depends greatly on the
care taken in designing the PC board. The use of low
Inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane Is a mustl

3-632

HFA1145
Attention should be given to decoupling the power supplies.
A large value (10!1F) tantalum in parallel with a small value
(0.1 !1F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
device's input and output connections. Capacitance, parasitic or planned, connected to the output must be minimized,
or isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to ground
at the amplifier's inverting input (-IN), as this capacitance
causes gain peaking, pulse overshoot, and if large enough,
instability. To reduce this capacitance, the designer should
remove the ground plane under traces connected to -IN, and
keep connections to -IN as short as possible.

Evaluation Board
The performance of the HFA 1145 may be evaluated using
the HFA 11 XX Evaluation Board.
The layout and schematic of the board are shown in Figure
2. The VH connection may be used to exercise the DISABLE
pin, but note that this connection has no SOn termination. To
order evaluation boards (part number HFA 11 XXEVAL),
please contact your local sales office.

An example of a good high frequency layout is the Evaluation
Board shown in Figure 2.

.~------------~.

Driving Capacitive Loads

+IN

Capacitive loads, such as an AID input, or an improperly
terminated transmission line will degrade the amplifier's
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (AS) in series with the output
prior to the capacitance.

v+

•

Figure 1 details starting pOints for the selection of this resistor. The points on the curve indicate the AS and CL combinations for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.

FIGURE 2A. TOP LAYOUT

•

a: a..

W:E

~cC

=

=

=

FIGURE 2B. TOP LAYOUT
50

510

510

~
~

'=

~Av .. +1

IN_.....- - - I

61-+...itllf.ro

Av=+2

5
1....._ _ _...1

ro

o

50

100

150
200
250
300
LOAD CAPACITANCE (pF)

350

rD GND VL

GND ' "

FIGURE 2C. TOP LAYOUT

400

FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE

FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT

3-633

cCU)
Za:
O!!!
-u.

!ci::::i

RS and CL form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
270M Hz (for AV +1). By decreasing AS as CL increases (as
illustrated in the curves), the maximum bandwidth is obtained
without sacrificing stability. In spite of this, the bandwidth
decreases as the load capacitance increases. For example, at
AV = +1, AS = 620, CL = 40pF, the overall bandwidth is limited to 180MHz, and bandwidth drops to 75MHz at Av +1,
AS 80, CL 4OOpF.

=

....I

HFA1145

Typical Performance Curves
200

150

>"

S.

...
!;
0

2.5

I

\

1.5

0

~
~

1.0

-50

!;

0.5

-100

I

\- ~

J

Av=+l
+RS = 5100

I\.

2.0

~
w

!:i

...:::>

3.0

Cl

50

~

=±5V, RF =510n, TA =25°C, RL =lOon, Unless Otherwise Specified

Av=+l
+RS",5100

100

w

~

VSUPPLY

I

l

\

\

J

0

-1.0

-200

TIME (5ns/DIV.)

TIME (5ns/DIV.)

FIGURE 3. SMALL SIGNAL PULSE RESPONSE

2.0

1.0

~
w
Cl 0.5

~

0

!;

-0.5

0

-1.0

~

~

FIGURE 4. LARGE SIGNAL POSITIVE PULSE RESPONSE

200

AV",+l
+RS",5100

I"
I
'/
J

.\
\

100

~w

1\

~

\

~

0

~
~

I

50

!:i

g

-50

-100

TIME (5ns/DIV.)

FIGURE 6. SMALL SIGNAL PULSE RESPONSE

FIGURE 5. LARGE SIGNAL BIPOLAR PULSE RESPONSE

2.0

3.0

Av",+2

Av=+2
1.5

2.5

~

1.0

~

0.5

!;
0

V\.

2.0
1.5

0

"""""""

-200
TIME (5ns/DIV.)

~

1\

I
~

-150

-2.0

!:i

,

Av=+2'
150

-1.5

~
w

~

-0.5

-150

1.5

\

1.0

~
w 0.5

1

J

I
I

\
\
\

,/

~

!:i

0

!;

-0.5

0

-1.0

~

I!::::>

~

-0.5

1

I

I.
I

.\
\

J

\.

'J

-1.5

-1.0

-2.0
TIME (5ns/DIV.)

TIME (5ns/DIV.)

FIGURE 8, LARGE SIGNAL BIPOLAR PULSE RESPONSE

FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE

3-634

HFA1145
Typical Performance Curves

VSUPPLY = ±5V, RF = 5100, TA = 25°C, RL = 1000, Unless Otherwise Specified {Continued}

200

3.0
Ay =+10
RF= 180n

150

!

100

~

50

0

5

-so

,

F

-100

w
CJ

~

\ """'""-

J

§

~

\

I

;!i

~

2.S

f---I

2.0
1.S

g

1.0

5

o.S

~

::>
0

Ay = +10
RF= 180n

r "'-

\
\
\

/
I
I
/

,~

0 1"'"

~

-a.S

-lS0

-1.0

-200
TIME (SnsJDIV.)

TIME (SnsIDIV.)

FIGURE 9. SMALL SIGNAL PULSE RESPONSE

FIGURE 10. LARGE SIGNAL POSITIVE PULSE RESPONSE

2.0
Ay =+10
RF= 180n

1.S

~

w
CJ

1.0

/
/,

O.S

~

g

0

5
II.

-a.S

::>

0

\
\.\.

-1.0

~

,

I
J

I-

DISABLE
800mVIDIV.
(0.4V to 2.4V)

'V

-l.S

.,.

OUT
400mVIDIV.

I..

.~

\

\

OV
Ay=+l, VIN = 1V

-2.0
TIME (SOnsIDIV.)

TIME (SnsJDIV.)
FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE

iii' 3
:!!.

z

~

VOUT = 200mVp_p
+RS = S10n (+1)
+Rs=on(-l)

0

.1~1!+1

4=1+~

I I ill.

I.r:::=

I~I!"?,~

-3

:\
o

,

Ay,,-l

1

Ay!+~
I I

0.3

10
FREQUENCY (MHz)

FIGURE 12. OUTPUT ENABLE AND DISABLE RESPONSE

100

SOO

i

j

...- r~

Ay=+10 -

,Ay=+S
'\
.....;
1111

~~

w

Ay~+2

II:

l

1\

Ay=+10

~

~

90

Q

190

!:I«

w

VOUT = 200mVp_p
RF = Sloo (+2)
RF = 2000 (+S)
RF = 180n (+10)

270::&

~
0.3

FIGURE 13. FREQUENCY RESPONSE

Ay=..s-

10
FREQUENCY (MHz)

~~

111111
100

FIGURE 14. FREQUENCY RESPONSE

3-(135

o

iii'

90

II!
!l!

180

w

e

w

270~

II:
SOO

HFA1145
Typical Performance Curves
iii'
~

VO~;'= 2OOmVp.p

~ =+2

3

VSUPPLY = tSV, RF = 5100, TA = 25°C, RL = 1000, Unless Otherwise Specified (Continued)

II

z
~ 0

r

~

I r
VOUT " 1.5Vp.p

~\

VOUT-5Vp.p

I

II
II

_t

0.3

Lift· L

.5['jj

~N

I
100

10

FIGURE 16. FULL POWER BANDWIDTH

500

RL = 1ItO

ILWlIII~.",

~"+2

RL = 500.:w

~~

400

RL"500
RL= 1000

,."....,1
RL=5OOll -

11111111

tt

"I---

~~

100

~=+10

100

o

I 111111
10

~ ...........

~=+1

11111
11111

RL = lItO ---'"

VOUT " 2OOmVp_p
RF" 1800 (+10)
+Rs = 5100 (+1) -

_1'.:2

R~ '='l'oon

0.3

200

FREQUENCY (MHz)

~ 1,,1 JoIJJJ

VOUT ,,200mVp.p

100

10

500

FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

-100

500

.so

---

o

-

:--

100

50

150

TEMPERATURE (DC)

FREQUENCY (MHz)

FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

FIGURE 18. -3dB BANDWIDTH VB TEMPERATURE

-30

VOUT = 2OOmVp.p
+Rs" 5100 (+1)
0.25

0.20

'I
~=+2
~'!.~

0.10

"

0.05

0

~=+2

l

-40

z

-SO

~ -60
-70
...I!s~ -80

j,

~ 0.15

i

~

X

VOUT = 5Vp.p

FREQUENCY (MHz)

i

~

~=+2

\

I m ~
! .!. III ..)('1\

I

~

W
~,,+1

VOUT " 2OOmVp.p'

11111

l

~=-1

VOUT = 4Vp.p (+1)
VOUT" 5Vp.p (-1, +2)
+Rs = 5100 (+1)

1\

\

I III

III

-90

VIN =lVp.p

i-'

!~

~=+1

-0.05

I 11-

-0.10
10
FREQUENCY (MHz)

75

0.3

IAN"!.
"

.'

lJ'If'"""

I<"'"

0/1

10
FREQUENCY (MHz)

FIGURE 19. GAIN FLATNESS

FIGURE 20. OFF ISOLATION

3-636

100

HFA1145
Typical Performance Curves
iii
~
z
0

§
~

-40
VOUT= 2Vp_p

~

~o

P'

-70
-80

III

-90

AV~'~2

II

'lv=+1',+2'

-50

III

til
II:

VSUPPLY = ±5V, RF = 510n, TA = 25°C, RL = loon, Unless O1herwise Specified (Continued)

£
~

Ay=-1

i'

1K

100

Q

10

5

0.1

~

iiiII:

1

~

0.3

10
FREQUENCY (MHz)

-

V~

....

0.01

100

0.3

FIGURE 21. REVERSE ISOLATION (S12)

10
100
FREQUENCY (MHz)

1000

FIGURE 22. ENABLED OUTPUT IMPEDANCE

-30

AV=+2
VOUT=2V

0.8

I--

_

....I

ettl)

za:

Ay=+2

a!!:!

0.6
0.4

II:
II:

0.2
0.1
0

0

III

"

~

til

-LL

-40

lII:

!cc:::l
a: 11.

U"
ID
~

\.

W:E

~et

Z

~

-50

~

.0.2

6

.0.4

-60

.0.6
.0.8
-70
3

8

13

18

23
28
TIME (ns)

33

38

43

-5

48

10

FIGURE 24. SECOND HARMONIC DISTORTION VB POUT

-30

3.6
Av=+2

3.5

-40

U"
ID
~

z

3.4

~
III

3.3

lil

3.2

!:i

~ 3.1

-50

5
~

Q

o

-60

3.0

Ay=-1

lr:

!-VOUTI (RL= 100m+VOUT(RL=100D)

5

10

15

OUTPUT POWER (dBm)

FIGURE 25. THIRD HARMONIC DISTORTION

--

~

~

+VOUT (RL= SOD)

2.9
2.8
I-VOUTI (RL= SOD)

2.7

o

15

OUTPUT POWER (dBm)

FIGURE 23. SETTLING RESPONSE

i

5

0

2.6
-50

""1'--,
~

-25

o

25

SO

75

100

TEMPERATURE (oC)

va POUT

FIGURE 26. OUTPUT VOLTAGE va TEMPERATURE

3-637

125

HFA1145

Typical Performance Curves

VSUPPLY;' ±S\f, RF

=5100, TA =25°C, RL =1000, Unless Otherwise Specified

,

100

100

-

~~

INI-

So

10
EN!

I

IN'j
0.1

1

10

!z
II!
a:
G

(Continued)

6.1

C

.5.

6.0

a:
a:

5.9

!zw

./

G
~
II. 5.8

./
/"
./

::;)

Ul

a:

~

5.6
3.5

100

/1'

5.7

V

V
4

4.5

5

5.5

6

6.5

7

7.5

POWER SUPPLY VOLTAGE (±V)

FREQUENCY (kHz)

FIGURE 27. INPUT NOISE CHARACTERISTICS

FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE

3-638

HFA1145

Die Characteristics
PASSIVATION:

DIE DIMENSIONS:

Type: Nitride
Thickness: 4kA ±O.5kA

59 mils x 59 mils x 19 mils
1500llm x 1500ilm x 4a31lm

TRANSISTOR COUNT:

METALLIZATION:

75

Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: akA ±O.4kA

SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kA ±O.akA

Floating (Recommend Connection to V-)

Metallization Mask Layout
HFA1145

.:. c:: c

•
DISABLE

·IN

...I

 100

.s
l!I

A

~ 1.0

I

~

~

0

5

-so

g
5

O.S

!:i

i!i

50-100

-

-lS0

0

5-G.S

~

J

-,

I

w

so

\

-

0.1.0
-1.5

-200

-2.0

TIME (SnaIDlV,)

TIME (SnaIDIV.)

FIGURE 2. SMALL SIGNAL PULSE RESPONSE

VOUT' ,200mVp.p

/I 1111

FIGURE 3. LARGE SIGNAL PULSE RESPONSE

:!!. 3

z

~'+2.1" ~~

iii'

~

a:

Ay.+l/

IIIII
I~~~

w
w

C!I

w

+180

lit

11111

+lID

./

0

~

=

~

~

~
c

:cC!I

0

~

.

C

I

~

0.3

1000

10

-40

-SO

:!!.

0.2

iii'-ss

~

0.1

~

0

a:

-G.2

;j
0

Z

RL= 100n

~

:!!.
:.= -60

Ay=+2

...

1.1

!

Ay .. +1

u

.J.~

-70

'/
b

-60

-55

100

FREQUENCY (MHz)

RL=1kn

~

-55

-7S

-G.3

10

300

II

11I111

-45

0.3

-G.l

100

FIGURE 5. FULL POWER BANDWIDTH

YOUT • 200mYp.p

...

~

FREQUENCY (MHz)

FIGURE 4. FREQUENCY RESPONSE

C

ti::J
a:: a..

~

100

FREQUENCY (MHz)

z

-LL

\\~
Ay=+:j
Ay=+2

I!!l;;

0.3

'J
10
FREQUENCY (MHz)

FIGURE 7. CROSSTALK ya FREQUENCY

FIGURE 6. GAIN FLATNESS

3-645

..J
ccrn
Za::

O!!!

~

c -3

::01

Ay=+1./
10

AY~-1

iii'

' -1

.t.

111111

iii'

=1000,

100

W:E

~cc

HFA1205

Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

69 mils x 92 mils x 19 mils
17S0~m x 2330~m x 483Jlm

Floating (Recommend Connection to V-)
PASSIVATION:

METALLIZATION:

Type: Nitride
Thickness: 4i

\

,I

w 0.5

~
!:i

.5.
w

\

J

~

\

'v

100

!:l

0
-50

~

-100

o

'I

I

J

-

-150

TIME (5naIDlV.)

TIME (5naIDIV.)

FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE

FIGURE 7. SMALL SIGNAL PULSE RESPONSE

2.0

2.0

,

Ay=+1
1.5
1.0

r

0.5

J

! 0
~
i .0.5

E
w

~

~

-

!:l

1.0
0.5

g

0

~

.0.5

o

-1.0

-1.5

J

FIGURE 8.

2.0
Ay=-1

0

-so

~

-100

!;

o

-150
-200

\

~et

V

FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE

150

'"'
g

W:E

TIME (5naIDIV.)

LARGE SIGNAL POSITIVE PULSE RESPONSE

200

!

~::::i
a:: a..

-2.0
TIME (5naIDIV.)

50

..J

etC/)
Za::
O!!:!
-IL

\,

I
I

-1.5

-2.0

w

,

Ay=+1
1.5

§ -1.0

!

1\

-200

-2.0

100

\
\

50

!;

g

-1.5

E
w

Ay:+1

150

1.5

Ay .. -1

1.5

~

-

\

1.0

E
w
~

J

~

0.5

!:l

g

0

!;

.0.5

~

-1.0

,

\

~

I

-1.5
-2.0
TIME (5naIDlV.)

TIME (5naIDIV.)

FIGURE 10. SMALL SIGNAL PULSE RESPONSE

FIGURE 11.

3-653

LARGE SIGNAL POSITIVE PULSE RESPONSE

HFA1212
Typical Performance Curves
2.0

(Continued) VSUPPLY = ±SV, TA = 2SoC, RL = lOOn, Unless Otherwise Specified

,

Ay=-l
1.5
1.0

~

0.5

w

g~
!;

I!:

is

-

I\.

,

\

0
-0.5

I

V

-1.5

I II

......

PHASE

Ay=-l

I II

IlL.
I '~

VOUT = 200mVp.p
+Rs = 6200 (+1)
+Rs = 00 (-1, +2)

TIME (5nsIDIV.)

FIGURE 12. LARGE SIGNAL BIPOLAR PULSE RESPONSE

0.6

~ 0

iii'
:s!.

~~

~-3

z

)?(
Ay=_lV~ ~

-6

0-9

z

Ay=+2
~
Ay=+l

fil

!::!

-270 ~
-360

1111

a:

o

z

600

I

0.5

VOUT = 200mVp_p
+As = 6200 (+1)
+Rs = 00 (-1. +2)

0.4

~ 0.3

~

0.2

o

0
-0.1

Q

r\
1\
\

VOUT = 4Vp_p (+1)
VOUT = 5Yp.p (-1, +2)
+RS = 6200 (+1)

z

Ay=+2

I 1111111
100

300

I

-30

II

-70

-80

./

~

-100
-110
0.3

I"

.~

r-

rr-

i,..-i--'

I III

I
10
FREQUENCY (MHz)

Ay=+2

100

1111111
1111111

-20
-30

\

AY=+~

z-4jQ

Ay=-l

-10

I

,

~

l.-iCII

I

~
Ii!U

~

Ul

)c:::;:l

-80

,.,r

.-

KI

RL= 1000

I

-100

J 1
10
FREQUENCY (MHz)

-70

-90

Ay=+2

.."".

-60

I'
~

RL=oo

iii' -40
:s!.
lo: -50
...r

11'\

iii' -50
:s!.

r-

FIGURE 15. GAIN FLATNESS

Ay=-l

-40

1\

Ay=+l -

. -0.3 1

II
IIII

-20

\. -~

1

FIGURE 14. FULL POWER BANDWIDTH

-10

J

\

0.1

-0.2

10
FREQUENCY (MHz)

-90

"

0.7

l;

~

III

.....
Ay=+2

i

-90
-180

FIGURE 13. FREQUENCY RESPONSE

iii' 6
:s!. 3

~

Ay=+l-

~w

o

10
100
FREQUENCY (MHz)

-2.0

:ii!

\

Ay=+l

II II
II

J

i

7'

I II

I

~

-1.0

A~112,

III
GAIN

100

FIGURE 16. REVERSE ISOLATION

-110
0.3

10
FREQUENCY (MHz)

100

FIGURE 17. ALL HOSTILE CROSSTALK

3-654

500

HFA1212

Typical Performance Curves

(Continued) VSUPPLY = ±5V, TA = 25°C, RL = 100D, Unless otherwise Specified

-40

-40
-45
20/

i-50

:!:!.

~

/'

-55

~

-45

~

i:!:!. -50

~
~

!!l -50

~c

/

C

-65
-70
-10

~

~ -55

/ / ~MHZ

~

20MHz

~

/'

-60

~

-65

o

-5

10

5

-70
-10

15

o
5
OUTPUT POWER (dBm)

-5

OUTPUT POWER (dBm)

FIGURE 18. 2nd HARMONIC DISTORTION vs POUT

i'--

10MHz

10

15

FIGURE 19. 3rd HARMONIC DISTORTION vs POUT

20

20

0.10

16,

11:

~ 0.05

~
~

~

~

~ "-

0

oS

12 I-

"

-0.05

Z

1&1

III

8

ENI

1>0..

1&1

!!l

1""0 ..

-0.10

0

4

i;;' 1-0
o
0.1

1
10
FREQUENCY (kHz)

TIME (ns)

FIGURE 20.

SETTLING RESPONSE

3.5

~

~
!:i

g
!5

~

3.4

Ay=-1

~

~

I-YOUTI (RL= 10on) +YOUT (RL= 1000)

3.3
3.2 f- I-YOUTI (RL= 500)
3.1
+YOUT (RL= 500)
3.0

-.....

l./"

'\.

"'-

2.9
2.8

"-~

2.7

2.6
-50

-25

o

25

50

75

100

TEMPERATURE fc)

FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE

3-655

125

o

100

FIGURE 21. INPUT NOISE CHARACTERISTICS

3.6

rr:
rr:
u

:>

z

...I

etC/)
Za::
O!!:!
-II..

!i::::i
a:: a..
W:E

~et

HFA1212

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:
Type: Nitride
Thickness: 4kA ±O.5kA

69 mils x 92 mils x 19 mils
1750llm x 2330llm x 4831lm
METALLIZATION:

TRANSISTOR COUNT:

Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kA ±O.4kA

180
SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kA ±O.8kA

Floating (Recommend Connection to V-)

Metallization Mask Layout
HFA1212
-IN1

OUT1

NC

v+
NC

3-656

HFA1245
Dual, 530MHz, Low Power, Video
Operational Amplifier with Disable

November 1996

Features

Description

• Low Supply Current .•.......•.•.••• S.8mAlOp Amp

The HFA1245 is a dual, high speed, low power current
feedback amplifier built with Harris' proprietary complementary
bipolar UHF-1 process.

• High Input Impedance •.•............•...•••• 2Mn
• Low Crosstalk (SMHz) . . . . . • . • . • • . . • . . . . • •• -73dB
• High Off Isolation (SMHz) ••••.•..•....••.•• -61dB
• Wide -3dB Bandwidth (Av

=+2) .•.••..•.••• 530MHz

• Very Fast Slew Rate ...•...••••.••...•.•. 10S0VlllS
• Gain Flatness (to SOMHz) .•.•••.•••.•••.•. ±O.11dB
• Differential Gain. . . . . • . . • • • • • • • . • . • • • • . • •• 0.02%
• Differential Phase..••.•.•..•••••.• "

0.03 Degrees

• Individual Output Enable/Disable
• Output Enable/Disable Time •.•••••••••• 160nsl20ns
• Pin Compatible Upgrade to HAS022

Applications
• Flash AID Drivers
• High Resolution Monitors
• Video Multiplexers

The HFA1245 features individual TTUCMOS compatible
disable controls. When pulled low they disable the
corresponding amplifier, which reduces the supply current and
forces the output into a high impedance state. This feature
allows easy implementation of simple,. low power video
switching and routing systems. Component and composite
video systems also benefit' from this op amp's excellent gain
flatness, and good differential gain and phase specifications.
Multiplexed AID applications will also find the HFA1245
useful as the AID driver/multiplexer.
The HFA1245 is a low power, high performance upgrade for
the popular Harris HA5022. For a dual amplifier without
disable, in a standard Blead pinout, please see the HFA1205
data sheet.

Ordering Information

• Video Switching and Routing
PART NUMBER

• Professional Video Processing
• Video Digitizing Boards/Systems
• Multimedia Systems

HFA12451P
HFA12451B

TEMP.
RANGE (DC)

• Medicallmaglng

PACKAGE

·401085

14Ld PDIP

E14.3

·401085

14 Ld sOle

M14.15

High Speed Op Amp DIP Evalualion Board

• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications
• High Speed Oscilloscopes and Analyzers

Pinout
HFA1245
(PDIP, SOIC)
TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

3·657


0

z

~

o

~

6

·3
·6

Z

·0.4
~.8

1\

-

"--

TIME (SnsJDIV.)

FIGURE 11. LARGE SIGNAL PULSE RESPONSE

VOUT = 200mVp.p
SOIC

Ay=+2
VOUT = 200mVp.p
SOIC

1111111

·1~1J~1
I i I IlL

I
GAIN

0

il !

0

FIGURE 10. SMALL SIGNAL PULSE RESPONSE

3

~

1

·1.6

TIME (5nsJDIV.)

:Eo

,
I

0.4

·1.2

·160

iii'

Av z +6
SOIC

Av =·1

~

Ittffi!IAy=+6 ..... ~

PHASE

o

I

RF=soOn
RF=683n
RF=7son

1111111
RF=lkQ
R = 1.SkQ

....
V

90

/

~

360

10
100
FREQUENCY (MHz)

0.3

0.3

iii'

1

800

0.2
0.1

iii'

Av,,·l

il ! ~.3

~.2
~.3

Rp=750n

~.4

1111

...

,

C

~

~~.4
Av=+6
I

::IE

0

z

~

10
FREQUENCY (MHz)

~.6
~.7

100

FIGURE 14. GAIN FLATNESS

X

RF=lkQ

IE: ~.5

~.7

1

11

"",'" .,(' ~RF=6S30

w

!:!

1=~Jd

FIJI IY

~
0

~

~.6

1R

0

:Eo ~.1

Av=+2

...........

·0.5

Ay=+2,SOIC
VOUT = 200mVp.p

Z

.......

~ ~.2

360'"
000

10
100
FREQUENCY (MHz)

FIGURE 13. FREQUENCY RESPONSE va FEEDBACK RESISTOR

0.1

o

z

,/

SOIC

:Eo 0
i!:
~ ~.1

w
w
270~

1809.

RF=soon

VOUT = 200mVp.p

0.2

90

"".~

~
~

FIGURE 12. FREQUENCY RESPONSE

o i[
w
!§

RF= 1.SkQ

r-.;.

Ay=·l

III

/.11

-

~ ::: ~
iiii
~~

b

~
('

)..

RF=1.5kQ

I
I

'\

\.

I

10
FREQUENCY (MHz)

1

1\

\
100

FIGURE 15. GAIN FLATNESS va FEEDBACK RESISTOR

3·670

HFA140S
Typical Performance Curves

VSUPPLY

=±5V, TA =25°C, RF =Value From the Optimum Feedback Resistor Table,

RL = 1000, Unless Otherwise Specified (Continued)

160
120

.s>

60

!i

40

g

0

5
~
0

-40

1.6

Ay=+1

PDIP

1.2

I

Ay=+1

PDIP

I'

~ 0.8

III

I

III

!:i

-80

!i 0.4
!:i
g 0

\
\..-

~

-120

,

~~A
o ~.8

v

TIME (5neIDlV.)

FIGURE 16. SMALL SIGNAL PULSE RESPONSE

FIGURE 17. LARGE SIGNAL PULSE RESPONSE

1.6

160 Ay=-1
120 PDIP

CJ

40

g

0

III

~

5
~
0

f---\

"-

1

I

-120

0.8

g

,

0

\

~.8

\1
,.

-1.2
-1.6

TIME (5nslDIY.)

TIME (5neIDIV.)

FIGURE 18. SMALL SIGNAL PULSE RESPONSE

160 Ay,,+2
PDIP
120

CJ

40

g

0

III

~

5II.
50

-.I

~

~ -0.4

o

-160

60

cC0

5

I

V

~

~
~ 0.4

,

\

-80

..J

Za:

Ay=-1

PDIP

-40

.s>

\,.

-1.6

TIME (5na/DIV.)

60

\

---1
-1.2

-160

.s>

\

FIGURE 19. LARGE SIGNAL PULSE RESPONSE

Ay=+2

PDIP

"-

1

~

~
!:i
g

0

-40

~ ~.4
o ~.8

V-

-160

1

0.4

-80

---1
-120

1\

0.8

\

--1
-1.2

\r
v

-1.6

TIME (5na/DIV.)

TIME (5na/DIY.)

FIGURE 20. SMALL SIGNAL PULSE RESPONSE

FIGURE 21. LARGE SIGNAL PULSE RESPONSE

3-671

O!!:!
-u..

~::::i
a:c..

w==
~cC

HFA1405

Typical Performance Curves

VSUPPLY = ±5V, TA = 25°C, RF = Value From the Optimum Feedback Resistor Table,
RL

160

Av=+6

PDIP

0

I

~ 0.4

!:i
~

\

~-co

RF= 1500

0.8

w

f

40

o .aD

~

II

w

PDIP

1.2

RF,"1500

~80

(Continued)

1.6

Ay=+6

120

~
'-'
§!

=1000, Unless Otherwise Specified

\

J

~

0

\
\
\/

5

~ -0.4
-0.8

V'"

.1.2

-120

-160

~

-1.8
TIME (5ns/DIV.)

TIME (5nsIDIV.)

FIGURE 23. LARGE SIGNAL PULSE RESPONSE

FIGURE 22. SMALL SIGNAL PULSE RESPONSE

1.6

160

AV=+6

AV=+6
120

~

80

CI

40

PDIP

PDIP

RF = 5000

RF=50OQ

~

~

~ 0.8

/'
IIl

w

0

~.4O

~.

~
C

0.4

~

0

!:i

!\
55
\...... o

JII

/
ill

~.

\

-0.4

J

0-80

-0.8

~
.1.2

--'
-120

-1.6

-160
TIME (5nsIDlV.)

:cCI
Q

3

0

~-3
....

::i.e

~

VOUT = 200mVp.p

111111

PDIP

~1!1~2"

II

III

Ay=.l ....
Ay = +1 (RF = +Rs = 5100)

FIGURE 25. LARGE SIGNAL PULSE RESPONSE

!z

:cCI

~

~

Q

Ay_+6
VOUT·200mVp.p

3

PDIP

0

~-3

1111111

::i.a

~

~

Ay= +2:"'~
Ay=-l
Ay=+1/

1111111
10
100
FREQUENCY (MHz)

RF=lS00 ....
RF=500Q

--

~\

l1'1'tt+ !Io..

~

IIIIII~

RF=500~/

RF=lSoo

1111111
0.3

-

TIME (SnaIDlV.)

FIGURE 24. SMALL SIGNAL PULSE RESPONSE

iz

\

11111111

II

0.3

800

FIGURE 26. FREQUENCY RESPONSE

11111
10
100
FREQUENCY (MHz)

FIGURE 27. FREQUENCY RESPONSE

3-672

o iii
w
90

II!

e.
CI

180

270~
360i:
800

HFA1405

Typical Performance Curves

VSUPPLY = ±5V, TA = 25°C, RF = Value From the Optimum Feedback Resistor Table,
RL = 100(1, Unless Otherwise Specified (Continued)

3

~

~C
w

2

VOUT= 5Vp_p

II I
Av=-1

PDIP

-

0

!l! -1

S
_ -2

i

a;
c

IAI

CJ

fil
N

=+2

I~

i

\

\

,

-3

i

r\

-4

Av = +6 (RF = 5000)
I
I

1111
1111

IAv=+6-"'
I (RF= 1500)

10
FREQUENCY (MHz)

0.3

~ 0.1

C
w

J

VOUT = 200mVp.p
I II
PDIP
Av=+1 (RF= +Rs = 51OQ)

0

-1

RF= 4220
-2

-3

..J

Av=+2

oo46
i~ -47

I:!

II)

-55
100

-

-50

3.6

-56

3.5

-57

3.4

20MHz

i-59
Z -60

-64

I

-65

10MHz

~100

E

I

!.

w so

w

~

~

!:i

!:i

0

!i!...

~ ·so

1\

-

0-100
-lS0

!i!
~

!;
o

-.

1.0

I

O.S

_\

,

I

0

\

-O.S

~

-1.0

V

-l.S

-200

-2.0
TIME (Sns/DIV.)

TIME (SnsIDlV.)

FIGURE 4. SMALL SIGNAL PULSE RESPONSE

FIGURE 5. LARGE SIGNAL PULSE RESPONSE

2.0

200

lSO

,,",=+1

Ay=+l

1.5

....

> 100

I

!.

w so
~

!:i

1.0

~

O.S

!i!

0

w

!:i

0

!i!

E

!;
A.
!;

!; -so

§

J

-100

[--

0

-1.0
-1.5

-200

-2.0

2.0
Ay=-l

>

100

"~

50

w

!i!

,

1.5

-

(

50 -50

-100

E

1.0

~

0.5

!i!

0

w

!:i

0

!;

I

\

\

l

1\

J

\r

r---

v

FIGURE 7. LARGE SIGNAL PULSE RESPONSE

200

!.

\

TIME (5nsIDlV.)

FIGURE 6. SMALL SIGNAL PULSE RESPONSE

150

I
I

-0.5

-150
TIME (SnsIDIV.)

,

I\.

I

!;

-0.5

50 -1.0

-lS0

,

""' =-1

Ir
'I
I

'\

\

J

V

-1.5

-200

-2.0

TlME(5ns/DIV.)

TIME (5nsIDIV.)

FIGURE 8. SMALL SIGNAL PULSE RESPONSE

FIGURE 9. LARGE SIGNAL PULSE RESPONSE

3-682

HFA1412

Typical Performance Curves

VSUPPLY

=±5V, TA =25°C, RL =1000, Unless Otherwise Specified

I
I

VOUT = 200mVp.p

II
II

"H+Ht;.-+2

~

"'IIII~§ ~

Av=-l
Av=+l-

o

ffi

90

II!
fil

1'\

PHASE

lo
z

'),~

10
FREQUENCY (MHz)

90
180

"

e.ww

z
~ 3

270~

if:

SOO

o

Za:

1ll1'ft

O!!:!
-u...
~::::i
a: a..

~

1\
\

.

W:iE

160

t:?~
V

ffiw

90 a:

"

10
FREQUENCY (MHz)

o

fil

e.w

-90 ~

if:

SOO

FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

Ay=+l

3

II

iii'

:2,0

1Vp.pj)fi
2.5Vp_p--1"
4Vp_p ...

II
PHASE

~

lVP.!!
2.5Vp.
4Vp_p'"

II

0.3

...

500

I ' " ' ' 100

0.3

II1I
GAIN

270~

~ ~\

RL=lkn
RL= 10011
RL=5011

Av=+2

iii'

:2,6

fil

«CI)

RL=lkn /
RL=10011 . /
RL = 5011

PHASE

!§

FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

9

e.w

...J

I 11111

o m-

100

160

:c

100

GAIN

-6

RL~~..'ri O)~
0.3

~

I II

CI

[-I II
lTI1

~L~~O,~ I

ffi

Ay= -1, VOUT = 200mV Pop

C( -3

/'~\

V

10
FREQUENCY (MHz)

~~

V

o

w
90 a:

~

FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS

3

RL = lOon

r\=rlll

0.3

500

RL=10011/ \
RL = SOil
PHASE

lmt
RL=lkn '
RL = 10011

Ay = +1, YOUTZ 200mV Pop

RL=lkn

\

1111

270~

FIGURE 10. FREQUENCY RESPONSE

GAIN

C') ~
"\

RL= lkll
RL=10011//
RL = 5011

o

if:

100

IIII

. . . . iIr

e.w

180

1111111
10
FREQUENCY (MHz)

GAIN

C( 3

Av=+l

PHASE

II

z

CI

Av=-~~~
I ~

II

iii'

:2,6

~

Jt

0.3

Ay = +2, VOUT = 200mVp_p

9

Av=+2

GAIN

(Continued)

10
FREQUENCY (MHz)

z
~-3

1\

l-J\ i\

1Vp.p
2.5Vp_p4Vp.p ~

-6

\
1\

\

\'

GAIN

PHASE

~ t\
1"'1

1ffi
lJp!~
2.5Vp.p
4Vp.p

100

0.3

FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

10
FREQUENCY (MHz)

~

1\ \

~~

\

o

ffi

90

II!
fil

180

e.w

270 ~

:c

100

so0360 ...

FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

3-683

~«

HFA1412
Typical Performance Curves
3

VSUPPLY = ±SV, TA = 25°C, RL = loon, Unless Otherwise Specified (Continued)

AV=·l

VOUT= 5Vp.p

6

IIII

iD 3

~

GAIN

:s
z

lVp_p __
..__ ~

~

2.5V~.:.-

4Vp.p

~-6

1oo..1Vp.p

l1't1

~~

4Vp.p
2.5Vp.p

180e

~ -9

90 II:

:5.12

e.

·15

o
-90

II I
10
FREQUENCY (MHz)

fil

100

~\i\

IY

w

!Ii

-18
-21
0.3

500

10
FREQUENCY (MHz)

0.5

450

400

..... ......

:z:

!.

~

z~

350

r-.........
Av=-1

300

~
250

-- -- --..........

iD

0.3

r-.........

~

0.1

~
:e

0

Ay=+Y

I,/'

o

25

50

75

100

-0.1

Ay=·1

-0.3

TEMPERATURE (oC)

FIGURE 18. -adB BANDWIDTH va TEMPERATURE

-40

III 1\
III \l\

~

-60
-65

V :;

-70
-75

-liD
-liS
-90
0.3

./

200

-10
·20

i

-55

iD
:s
z

100

o

tf- -

-50

10
FREQUENCY (MHz)

FIGURE 19. GAIN FLATNESS

h

-45

-

TtN. r\

-0.5 1

125

Ay=+2

I~

:5 -0.2

z

1\
1\

V

:E. 0.2

-0.4
-25

500

VOUT = 2OOmVp.p

Av=+l

200
-50

100

0.4

Av=+2

r-.........

1\

RGURE 17. FULL POWER BANDWIDTH

FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES

'N

~r\

KI"""

z

it

i

0.3

r\\\
AV=+2
Ay=+l
Ay=-l

C

II
PHASE

0
·3

i'Ay=+2
,- Ay =-1
Ay=+1

-30

0:': -40

...

~-50

RL=100n .-::

~-60

IA
1/

u -70
-110

./-

i"r-

~
RL=oo
~

-90
10
FREQUENCY (MHz)

100

0.3

500

FIGURE 20. REVERSE ISOLATION (S12)

10
FREQUENCY (MHz)

FIGURE 21. ALL HOSTILE CROSSTALK

3-684

100

HFA1412

Typical Performance Curves

VSUPPLY = ±SV, TA = 25°C, RL = 1Don, Unless Otherwise Specified (Continued)

""'=+2

-45

i:!!-

-50

i"'"

·55

~ ~O V

---

""'=+2

....--

-45

20MHz

·50

------

z
~ ~O

~ ~5

e!!l ~5

·70

.70

c

10MHz

...........
~

·75

·75
-80

·5

----

20MHz

i:!!- ·55

10MHz

-80

4

·2

10

7

13

-5

4

·2

OUTPUT POWER (dBm)

10

7

13

OUTPUT POWER (dBm)
FIGURE 23. 3rd HARMONIC DISTORTION va POUT

FIGURE 22. 2nd HARMONIC DISTORTION va POUT

-40

-40

""'=+1

""'=+1

-45

-45
20MHz
-50

i:!!-·55
z

"."

Q-80

Ii:

~~5

c

·70

-50

., ~

i:!!--55

~

20MHz

.........

z

10MHz

~~O
~ ~5

---

Q

·75

10MH;""-

...........

...............

·70

...........

~

"\.

"'\.

·75

-80
-5

·2

10

147

13

-80
-5

·2

-----1,65
·50

13

"'" :·1

20MHz

i:!!- -55

10

FIGURE 25. 3rd HARMONIC DISTORTION va POUT

FIGURE 24. 2nd HARMONiC DISTORTION va POUT

"",=·1

147

OUTPUT POWER (dBm)

OUTPUT POWER (dBm)

r----..
-r--

20MHz

10MHz

z
Q ~O

10MHz

"""

C .70
·75

........

·75

-80
-5

·80

·2

4

7

10

13

OUTPUT POWER (dBm)

-S

·2

4

7

10

OUTPUT POWER (dBm)

FIGURE 26. 2nd HARMONIC DISTORTION va POUT

FIGURE 27. 3rd HARMONIC DISTORTION va POUT

3·685

13

HFA1412
Typical Performance Curves

VSUPPLY

=±SV, TA =25°C, RL =1000, Unless Otherwise Specified

(Continued)

20

20

VOUT= +1V

VOUT·+O.5V
15

15

~

"-

...

~ 10

="

"'

5

--.............
o
100

I

Av=+1

Av·-1

500

"

900

...............

.......... r--....

100

2100

1700

5

~
o

Av=+2
1300

III-.

---"-......
Av=+1

Av=-1
500

INPUT TRANsmON TIME (ps)

~=+2

1300

900

~

1700

2100

INPUT TRANsmON TIME (ps)

FIGURE 28. OVERSHOOT va TRANSITION TIME

FIGURE 29. OVERSHOOT va TRANSITION TIME

r------------,------,------r-----,
VOUT = 0.5Vp..p

~

15~=_--_+~----~~~~~-----+----~

15-=~---+~Ay-=-+~1-+------+------+----~

~

~

~10r_-----+------~_.~~--~c-_p~--~

l-

I" . -__

I

..L

5

o

~-----+--~

~

____

~

100

__~~--~__~--+_----~

____

~

500

______

900

~

____- L_ _ _ _

1300

1700

5r------r----~------~--~~~~~

~

500

2100

900

1300

1700

2100

INPUT TRANsrrlON TIME (ps)

INPUT TRANSrrlON TIME (ps)

FIGURE 31. OVERSHOOT va TRANSITION TIME

FIGURE 30. OVERSHOOT va TRANSITION TIME

0.02
0.01

Ay=-1

o
~

-D.01

!§

-D.02

!w

-D.03
-0.04
-0.05

Ay=+1

~

/'
/
/

-D.06
-1.5

0.2

Ay=+2'~

""'---" ..............

~

It

............

~lr\ll

~=+2

.

""V

-0.2

-1.0

-0.5

0

0.5

1.0

1.5

INPUT VOLTAGE (V)

w

~

~

~

50

50

ro

TIME (ns)

FIGURE 32. INTEGRAL UNEARITY ERROR

FIGURE 33. SETTLING RESPONSE

3-686

50

50

HFA1412

Typical Performance Curves

VSUPPlY

=±sv, TA =2SoC, Rl =1000, Unless 01herwise Specified
3.6

6.6
~

~

~

6.5
6.4

1- :::
_

~IC
::)

6.0

5.9

u

5.8

It

5.7

iil

5.6

~

,..,

6.1

~

5.5
4.5

./
./

.,

3.5

"""

3.4

E
w

3.3

~

3.2

CI

.",

~

3.1

~
0

2.9

~ 3.0

./

!-YOUTI (RL" l000)~ ~

Ay=-l

~

+YOUT (RL" 1000)

............

I-YOUTI (RL= 500)

./'

(Continued)

'\.

+YOUT (RL= 500)

~

'\..

2.8
2.7

5.5

6.5

6

-50

7

"

~

2.6
5

o

-25

25

50

75

100

125

SUPPLY VOLTAGE (±Y)

FIGURE 34. SUPPLY CURRENT YB SUPPLY VOLTAGE

FIGURE 35. OUTPUT VOLTAGE

50

VB

TEMPERATURE

20
....I

------t

+
+

+INPUT

QN1

L-+--U--t--+

v-

v+
-INPUT

OUTPUT

Cc =33pF

>--:t-"'IYIr--"i-;::~_P-l,

v-

vv+ - ......~--<

10 SET

Application Information
Static Protection
All devices are static protected by the use of input diodes.
However, strong static fields should be avoided, as it is
possible for the strong fields to cause degraded diode
junction characteristics, which may result in increased input
leakage currents.
Latchup Avoidance
Junction-isolated CMOS circuits employ configurations
which produce a parasitic 4-layer (PNPN) structure. The 4layer structure has characteristics similar to an SCR, and
under certain circumstances may be triggered into a low
impedance state resulting in excessive supply current. To
avoid this condition, no voltage greater than 0.3V beyond the
supply rails may be applied to any pin. In general, the op
amp supplies must be established simultaneously with, or
before any input signals are applied. If this is not pOSSible,
the drive circuits must limit input current flow to 2mA to
prevent latchup.
Choosing the Proper IQ
The ICL76ll and ICL7612 have a similar 10 set-up scheme,
which allows the amplifier to be set to nominal quiescent currents of 1OjJA, 100jJA or 1mAo These current settings
change only very slightly over the entire supply voltage

range. The ICL76ll/12 have an external 10 control terminal,
permitting user selection of quiescent current. To set the 10
connect the 10 terminal as follows:

10

=10jJA -10 pin to V+
= l00jJA - 10 pin to ground.

10

=lmA - 10 pin to V-

10

If this is not pOSSible, any
voltage from V+ - 0.8 to V- +0.8 can be used.

NOTE: The output current available is a function of the quiescent
current setting. For maximum peak-to-peak output voltage swings
into low impedance loads, 10 of 1mA should be selected.

Output Stage and Load Driving Considerations
Each amplifiers' quiescent current flows primarily in the output
stage. This is approximately 70% of the 10 settings. This
allows output swings to almost the supply rails for output loads
of lMO, 100kO, and 10kO, using the output stage in a highly
linear class A mode. In this mode, crossover distortion is
avoided and the voltage gain is maximized. However, the out-'
put stage can also be operated in Class AB for higher output
currents. (See graphs under Typical Operating Characteristics). During the transition from Class A to Class B operation,
the output transfer characteristic is non-linear and the voltage
gain decreases.

3-694

ICL7611,ICL7612
Input Offset Nulling

+5

+5

Offset nulling may be achieved by connecting a 25K pot
between the SAL terminals with the wiper connected to V+. At
quiescent currents of 1mA and 100!!A the nulling range
provided is adequate for all Vas selections; however with
10 10!!A, nulling may not be possible with higher values of
Vas·

100K~---

VOUT

V+

FIGURE 7. VOS NULL CIRCUIT

30K

1&OK
6&OK

INPUT

100K

O.ll11' ...-.....--"M.......

OUTPUT

360K NOTES
NOTES

NOTES:
5. Note that small capacitors (25pF to 50pF) may be needed for stability in some cases.
6. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff.
fc= 10Hz, AvCL = 4, Passband ripple = O.ldB.
FIGURE 8. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER

3·696

ICL7611,ICL7612
Typical Performance Curves
10K

~

1K

:::)

U

-

8::::)
10

o

,

4

2

I

I

6

8
10
SUPPLY VOLTAGE (V)

II:
II:
:::)

U

12

14

i

IEw
u

~
liE

...

1000

I

-

I

0
25
50
75
FREE-AIR TEMPERATURE (DC)

-25

100

125

~

RL=1MO

~

~

.""

r---

10 = 1011A

~~

I- RL=1ookO /
I- 10 = 1OO11A
IRL=10kn
IIQ=1mA

...J

w
w

:!

100

;.J

V

....I

VSUpp=10V
VOUT=8V

~

w

/

.."

°f

1:1'-

/

1.0

-

'Q= 1

~O

I

~

10

-

FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR
TEMPERATURE

II:
II:

~ID

1o=1oo:u'

10

16

/

:::)

102

:::)

= VS=±5V

100

IQ=1mA

IL
IL

UI

FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY
VOLTAGE

1000

103

~

==.;;;

IQ= 1011A

I

!i
w

IQ = 10011A
1--1._ ~

.-r-

1

~

I

I

I

V+-V-= 10V
NO LOAD
NO SIGNAL

=~

-.l~

100

~

UI

104

I
IQ=1mA

~

!iw
II:
II:

I

TA=250C
NO LOAD
NO SIGNAL

10

II:

H:

is
0.1
-50

-25

0
25
50
75
FREE-AIR TEMPERATURE (DC)

100

FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE

~

~

1
-75

125

VSUPP = 15V

...iii'

---I----t----t---+---i

~II:

105

~

~
!j 104

~
~
..

103

IEw

102
II:

ll!
IL
is

I
z

10
1
0.1

1.0

10

100
1K
10K
FREQUENCY (Hz)

125

105
VSUpp= 10V
.~

95

90

~
.--~
_
IQ=1mA

r---... r--.....
1"""-0

-

S5
80

.....

r-......
~

.........

75
70
-75

100K

FIGURE 13. LARGE SIGNAL FREQUENCY RESPONSE

100

~1oo

w

~
...J
:!5

-25
0
25
50
75
FREE-AIR TEMPERATURE (DC)

FIGURE 12. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN vs
FREE-AIR TEMPERATURE

1~r---'----r--~----r---.---'---,
TA = 25D C
106

-50

-50

-25
0
25
50
75
FREE-AIR TEMPERATURE fC)

100

125

FIGURE 14. COMMON MODE REJECTION RATIO vs FREE-AIR
TEMPERATURE

3-697

CCCl)
Z£t:
O!!:!
-II.

~:::i

£t:1l.

W:::a:

~CC

ICL7611,ICL7612
Typical Performance Curves

(Continued)

f
:s

100

l

VSUPP= 10V

lo=lmA

~

96

II:

90 - l a = lOOIlA

~

~
L&I
~
~

I
....

85

I

L&I

1~=101lA

-

r-

-

-1-00-

80

............ .........

75

-SO

..........

--

!:i
g

-

~

11: 14

~

VSUPP
=±8V

w 12

~

!:i

g
~

8
i

I

10

~
8

V~P~

=

6

V

4
2

~

\

~

"""'-

100

i

--

\.

o

100

,

... ~ 1\

,.

\

\

'-

lK

300

125

~_

100

~

o

_

-

10

12

g

10

!;
!;

8

0
::E

:I

i

lK
FREQUENCY (Hz)

"' "-

...... ......~

10K
lOOK
FREQUENCY (Hz)

12

g

10

I-

8

1M

~
0

6

::E
:I
::E

4

0(

2

:v"'""""

-

10K

lOOK

::E

X

TA=2SoC
TA = 125°C

""

"

o

10K

10M

l.; TA = -55°C

'\ .~

;(

\

~
~~

lOOK
1M
FREQUENCY (Hz)

10M

FIGURE 18. OUTPUT VOLTAGE vs FREQUENCY

12

-IRL=l~kf.!
1
10
~

-

L&I

~

~
!;
...
!;

!j

...

100

Vsupp= 10V
10= lmA

14

w

:I

14

~

r-o....
i""""'-I-

!j

~

~
L&I

~""

FIGURE 16. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY

~

-

16

II.

'-- "-

200

FIGURE 17. OUTPUT VOLTAGE vs FREQUENCY

~

~

400

~

~\

...

~~~P

TA = 25°C
la=lmA
la=101lA
- - la = 1001lA

~I

-

16

""""\
I

::E

i

,

TA= 25°C
3V s VSUPP S 16V

L&I

FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREE-AIR
TEMPERATURE

16

,

~

500

~

I"""--

..........

-25
0
25
50
75
FREE-AIR TEMPERATURE fC)

600

6

r--

8

6

..........

RL=10kf.! I

-,........
RL=2kf.!_

0
::E

4

!

VSUPP = 10V
2 eo- la=lmA

~

:I

4

::E

2

6

10
12
8
SUPPLY VOLTAGE M

14

FIGURE 19. OUTPUT VOLTAGE vs SUPPLY VOLTAGE

o

-75

16

I

-so

I
-25
0
25
50
75
FREE-AIR TEMPERATURE fC)

100

125

FIGURE 20. OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE

3-698

ICL7611,ICL7612
Typical Performance Curves

f-

(Continued)

V
./
#

/'

V

V

V

0.01

V

10=lmA

~

12

~

10

CI

~

!5...
!5
0
::E
:)
::E

4

~

::E

I

"

6
8
10
SUPPLY VOLTAGE M

12

14

16

6
8
10
SUPPLY VOLTAGE M

4

2

10 = lmA
12

14

16

FIGURE 22. OUTPUT SINK CURRENT vs SUPPLY VOLTAGE

8

f-

I

V

/'

..J
«(I)

TA = 25°C, Vsupp = 10V
RL = 10kQ, CL = 100pF

,.- i""'"

8

2

=10vA

I

I"-

""-

TA = 25°C
V+-V-=10V
10=lmA

6

4

10

10 -l00vA

16

w

"""
.~

FIGURE 21. OUTPUT SOURCE CURRENT vs SUPPLY VOLTAGE

14

I

#

2

1
c:.

l

.I

za::

O!!:!
-IL

\

OUTPUT

/

INPUT

o

0.1

1.0
10
LOAD RESISTANCE (kn)

o

100

2

4

!;t:::;
a::

"

6

8

TIME IIts)

FIGURE 23. OUTPUT VOLTAGE vs LOAD RESISTANCE

""
10

12

FIGURE 24. VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE (Ia 1mA)

=

8

8
TA = 25°C, vsupp = 10V
RL = l00kD, CL = l00pF

~

w

6

~

4

!5

2

0

0

_. . ._. . . __
IV

-----I~

=l001lA

ICL7641 (Quad) -10 =1mA
ICL7642 (Quad) -10 =101lA

VIN

Each amplifiers' quiescent current flows primarily in the output stage. This is approximately 70% of the 10 settings. This
allows output swings to almost the supply rails for output
loads of 1MD, 100kD, and 10kD, using the output stage in a
highly linear class A mode. In this mode, crossover distortion
is avoided and the voltage gain is maximized. However, the
output stage can also be operated in Class AB for higher
output currents. (See graphs under Typical Operating Characteristics). During the transition from Class A to Class B
operation, the output transfer characteristic is non-linear and
the voltage gain decreases.

3-706

1I

VOUT

FIGURE 1. SIMPLE FOLLOWER

NOTE: The output current available is a function of the quiescent current setting. For maximum peak-to-peak output
voltage swings into low impedance loads, 10 of 1rnA should
be selected.
Output Stage and Load Driving Considerations

ICL76XX

I·

>

1001<0

4

+5

t}-ICL76XX

~--J--1~"'.

+

=.

1MCl

FIGURE 2. LEVEL DETECTOR

VOUT

~~~~g~

ICL7621, ICL7641, ICL7642

X>----<~- VOUT

680kil
WAVEFORM GENERATOR

NOTE: Since the output range swings exactly from rail to rail, fie.
quency and duty cycle are virtually independent of power supply
variations.

NOTE: Low leakage currents allow integration times up to
several hours.

FIGURE 4. TRIANGLEISQUARE WAVE GENERATOR

FIGURE 3. PHOTOCURRENT INTEGRATOR

1MCl

+BV

O.5I1F

>!I-'\I\rr-.-:----I!fo,"""""-.,

...I

VIN 10kil

c(cn

Za:

OW

-u::

ti::Ja..

a:

W::iii

~c(

-8V

FIGURE 6. BURN-IN AND UFE TEST CIRCUIT

FIGURE 5. AVERAGING AC TO DC CONVERTER FOR AID
CONVERTERS SUCH AS ICL7106, ICL7107,
ICL7109,ICL7116,ICL7117

30kCl

160kCl
680kCl

100kCl

360kil
INPUT

O.2I1F

OUTPUT
I
1MCl

I

~--il--.
NOTE 4

NOTES:
4. Small capacitors (25 - 50pF) may be needed for stability in some cases.
5. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff.
fc = 10Hz. AVCL = 4. Passband ripple = O.ldB.
FIGURE 7. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER

3-707

ICL7621,ICL7641,ICL7642
Typical Performance Curves
10K

I

TA=250C
NO LOAD
NO SIGNAL

l

lK

II:

i3

~

100

~

II.
II.

:::I

II)

1

,
o

2

I

IQ = 100JJA
-L_

I

I

IQ= lOI1A

,.

10

-t--"

1

6

8
10
SUPPLY VOLTAGE (V)

12

102

IQ = 100JJA

_

10

IQ = 101lA
I

-

~

=:=;;

II.
II.

:::I

II.

0
25
50
75
FREE-AIR TEMPERATURE (oC)

I
100

125

1000

~

/

CJ

w

!j

/

./

i!O

!iw

./'

.¥'

-

RL=lMQ
IQ = 101lA

=

i:::

RL=lookn /
IQ=l001lA
RL=10kn
la=lmA

_

~

oJ
C

1.0

100

~

./

10

VSUPPLY = 10V
VOUT=8V

~
~

1/

100

~
III
!;

-25

FIGURE 9. SUPPLY CURRENT PER AMPUFIER vs FREE-AIR
TEMPERATURE

VS=±5V

0

I

1.s0

16

1000

~

-

II:
II:
:::I
0

FIGURE 8. SUPPLY CURRENT PER AMPUFIER VB SUPPLY
VOLTAGE

!zw
i:::I

IQ = lmA

103

!zw

~

14

I

l

II)

4

I

V+ - y. = 10V
NO LOAD
NO SIGNAL

=;;;;Z

IQ=lmA

~~

i

104

I

10

II:
W

u.
u.

is
0.1
-50

-25

o

25
50
75
FREE-AIR TEMPERATURE (OC)

100

FIGURE 10. INPUT BIAS CURRENT VB TEMPERATURE

~ 106

i!O

~
w

105

~1~
~ 102

oJ

~

c 10

~

o

IiII:

~1;I::::..~;:--+-~L-4-_+~

~

~

iii"

TA = 25°C
VSUPPLY = 15V --/----+----1---+_---1

!j 104 ......----r-...rl----.",...,.../

0

~

~

::l
~

~

e

1---+-----r=;~n--3~~--+_--+----I45 CJ
90

I---+----/--

~

180 II.
1M

-L~3J

FIGURE 12. LARGE SIGNAL FREQUENCY RESPONSE

~..

~

135:::

1 L.-__...I.-__- ' -__--L____L.-__.J3>__
0.1
1.0
10
100
lK
10K
lOOK
FREQUENCY (Hz)·

-50

-25
0
25
50
75
FREE-AIR TEMPERATURE (oC)

100

125

FIGURE 11. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN VB
FREE-AIR TEMPERATURE

1~r---'----.---.----r---~---r---'
~

1
-75

125

z

0
::IE
::IE
0
0

105

-"-

VSUPPLY = 10V
100

95
90

IQ" 101lA

~
IQ=1001lA
IQ=lmA

r--.. ..........

r-- .......... .......
.......... r-....

-

85
80

~

75
70
-75

-50

-25
0
25
50
75
FREE-AIR TEMPERATURE fC)

100

125

FIGURE 13. COMMON MODE REJECTION RATIO VB FREE-AIR
TEMPERATURE

3-708

ICL7621, ICL7641, ICL7642

Typical Performance Curves
iii'
:!!.

100
10=lmA

95

I
....

I

1~=10)lA

-

-~

80
75

---- -- -VSUPPLY = 10V

90 -10=100"A
85

(Continued)

-r--

r--...

..........

70
65
·75

·50

..........

·25
0
25
50
75
FREE.AIR TEMPERATURE (oC)

100

14

~

a..

~w

10

~~

-.~

125

400

~

300

-+lr----+"------11- -

1-.....~t-...,:¥5;;;;;;;;::-1t_

1"001'00

10

100

8

~5

6

-5

4

:Eo..

io

__~~~-.J

W:E

:\.

~

10

If~

8

:ES

8

~O

TA = 25°C

~~TA=1250C

,

lOOK
1M
FREQUENCY (Hz)

10M

FIGURE 17. OUTPUT VOLTAGE VB FREQUENCY

12

-IRL=l~Okn

-

e!:j

~5

TA =-550C

'~ ~ '- .......
I'

0..

~~

~-...... OUTPUT

(R111R2l " 100kQ
FOR FULL CLAMP EFFECT

NOTE: Rl11R2 indicates the parallel combination of Rl and R2'
FIGURE 3. INVERTING AMPLIFIER WITH (OPTIONAL) CLAMP

Normal logarithmic amplifiers are limited in dynamic range in
the voltage-input mode by their input-offset wltage. The
built-in temperature compensation and convenience features
of the ICLa048 can be extended to a voltage-input dynamic
range of close to 6 decades by using the ICL7650S to offsetnull the ICLa04a, as shown in Figure 6. The same concept
can also be used with such devices as the HA2500 or
HA2600 families of op-amps to add very low offset voltage
capability to their very high slew rates and bandwidths. Note
that these circuits will also have their DC gains, CMRR, and
PSRR enhanced.

..J

 ......+-_VOUT
GROUND

15.9kn

GAIN

-I

L..-_ _ _ _

150pF

C,

I

_ _ _ _ _ _ _ of

15

7

R2

680n

lkn

I

~

(LOWT.C.)

RO
10kn
NOTE: For further Applications Assistance, see A053 and R017.
FIGURE 6. ICL8048 OFFSET NULLED BY ICL7650S

Typical Performance Curves
3
3

./

---

/

~

/'
2

----"'"'

~

o

o
4

6

10

8

12

14

·50

16

o

·25

TOTAL SUPPLY VOLTAGE (V)

FIGURE 7. SUPPLY CURRENT VB SUPPLY VOLTAGE
8
;(

g

~

UI

II:
II:

:::>

...u:::>
...
!:;
0
::I!
:::>
::I!

~

::I!

6

---

4

.... V

2

r

--

25

·20
·30
2

4

6

8

10

-

100

125

8
7

~"'"'

I

/ ~SITIVE-

4

14

-

o0

16

LIMIT

2

3

4

6

5

7

SUPPLY VOLTAGE (±V)

TOTAL SUPPLY VOLTAGE (V)

FIGURE 9. MAXIMUM OUTPUT CURRENT VB SUPPLY
VOLTAGE

/. /"

V

2

12

/ /

LlMVV

5

~

/

I

NEGATIVE

6

3

-r---... ...........

75

FIGURE 8. SUPPLY CURRENT VB AMBIENT TEMPERATURE

0
·10

50

TEMPERATURE (OC)

FIGURE 10. COMMON MODE INPUT VOLTAGE RANGE VB
SUPPLY VOLTAGE

3·718

8

ICL7650S

Typical Performance Curves

(Continued)

4

\
\,

'ii::

0.

>
.;;

100
O.lI1F
BROADBAND NOISE
(AV= 1000) \

w
CI

/1

10

1.0I1F

~

==

~

~

2

~

w

UI

0

.........

Z

1

N

:z:

~

I

0.1
25

50

I

75
100
TEMPERATURE (oC)

I

I

125

150

FIGURE 11. CLOCK RIPPLE REFERRED TO THE INPUT vs
TEMPERATURE

o

10

8

>"

.;;

-~"""

~

•

6

w
CI

~
~

4

Iii

~

o

IJ

2

o

-3
4

6

8
10
12
TOTAL SUPPLY VOLTAGE (V)

14

10

16

140

5II.
50

0

..

iii' 120
:!!.

2:2:

z
Ci

:;:-

0

~~
E E

20

CI

100

a..

9

80

a..

60

zw

0

..

RL = 10kn
CEXT= O.lI1F

""

50

20
0.01

23456789
TIME (ms)

=1000;

=10kn

0.1

W

.......

"

..

...

.. *'

"-

10
100
lK
FREQUENCY (Hz)

70

CI

90

Ii:

w

e-

:E
UI

110

"-

130

"

10K

lOOK

FIGURE 16. OPEN LOOP GAIN AND PHASE SHIFT VB
FREQUENCY

3-719

Iii
w
II:

40

FIGURE 15. OUTPUT WITH ZERO INPUT; GAIN
BALANCED SOURCE IMPEDANCE

10K

lK

FIGURE 14. INPUT OFFSET VOLTAGE vs CHOPPING
FREQUENCY

160

.§.

100

CHOPPING FREQUENCY - CLOCK OUT (Hz)

FIGURE 13. INPUT OFFSET VOLTAGE CHANGE vs SUPPLY
VOLTAGE

20

10K

FIGURE 12. 10Hz NOISE VOLTAGE vs CHOPPING
FREQUENCY

3

>"

100
lK
CHOPPING FREQUENCY - CLOCK OUT (Hz)

w

~
:z:
a..

ICL7650S
Typical Performance Curves
160
140

iii 120
:!!.

...0~

100

9

80

...0w

60

.

--

RL=10kr.l
CElIT = 0.111F

".-

"-

~
...,.,/

'"

z

-- r\.

~

0.1

10

100

""

1K

FREQUENCY (Hz)

2

i3w

50

10K

II:

70

"-

~

40
20
0.01

(Continued)

Sl

e.
t!;

90

:z:
U)
110

w

U)

«

130

...
:z:

If/

~

w 1 r-- CLOCK OUT
LOW ......

"~

g
!5

0

I

~ ·1

j'

0

·2

o

100K

~~

V

0.5

1.0

CLOCKOUT
HIGH

1.5

2.0

I---

2.5

TIMEblS)

NOTE: The two different responses correspond to the two phases of the
dock.

FIGURE 17. OPEN LOOP GAIN AND PHASE SHIFT VB
FREQUENCY

FIGURE 18. VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE (NOTE)

1001lA

2

~
w 1

~

!:l

g
~
!5
o

0

~

!zw

\

II:
II:

...::E

VE~CKOUT

j
u
w

...

\\

z
z

--

·2

o

'-"'"

11lA

;:)

u

CLOCK OUT ___~
HIGH

·1

101lA

0.5

1.0

«
:z:
9z

1.5

2.0

TIME(I1B)

100nA
1DnA
1nA

10pA
1pA

NOTE: The two different responses correspond to the two phases of
the clock.
FIGURE 19. VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE (NOTE)

I

100pA

0.8

0.6

101lA

w

II:
II:

11lA

;:)

U

...::E
j

...w
U

100nA
10nA

z
z

1nA

~

1DOpA

;!

I

10pA
1pA
-D.8

0.2

FIGURE 20. N-CHANNEL CLAMP CURRENT vs OUTPUT
VOLTAGE

1001lA

...z

0.4

OUlPUT VOLTAGE (~v.)

-D.6
-D.4
OUTPUT VOLTAGE (~v+)

-D.2

o

FIGURE 21. P-CHANNEL CLAMP CURRENT vs OUTPUT VOLTAGE

3·720

o

r----- Operational Amplifiers Glossary of Terms --~......,
AVERAGE INPUT OFFSET CURRENT DRIFT - The aver- INPUT OFFSET, ~URRENT (los) - The difference in the
age change in offset'current between room (25°C) and high currents flowing into the two input terminals when the output.
temperature (1250 C, 85°C or 75°C) or between room tem- is at zero volts.
perature and low temperature (OOC, -25°C or -55°C) divided '
INPUT OFFSET VOLTAGE (Vlo) - The differenti~1 DC ~olt.
by the temperature difference.
age required to zero the output voltage with no input signal
AVERAGE OFFSET VOLTAGE DRIFT - The average or load. Input offset voltage may also be defined for the case
change in offset voltage between room (25°C) and high tem- where two equal resistances are inserted in series with theperature (125°C,
or 75°C) or between room tempera- input leads. '
ture and low temperature (OOC, -25°C or -55°C) divided by
INPUT NOISE VOLTAGE (eN) - The input noise voltage'that
the temperature difference.
would reproduce the noise seen at the output if all the, ampli,
CHANNEL SEPARATION - The ratio of the output of a fier noise sources and source resistances were set to 'zero.
driven amplifier to the output (referred to input) of an
LARGE SIGNAL VOLTAGE GAIN (Ay) - The ratio 01 the
adjacent undriven amplifier.
peak to peak output voltage swing (over a spe-cified range) to
COMMON MODE INPUT VOLTAGE (VIe> - The average of the change in input voltage required to drive the output.
the voltages present at the differential input terminals.
OUTPUT CURRENT (loUT) - The output current available
COMMON MODE INPUT VOLTAGE RANGE (VieR) - The from the amplifier at some specified output voltage.
range of voltage that if exceeded at either input terminal will
OUTPUT RESISTANCE (Ro) - The ratio of the change in
cause the amplifier to cease operating properly.
output voltage to the change in output clirrent.
COMMON MODE REJECTION RATIO (CMRR) - The ratio
OUTPUT SHORT CIRCUIT CURRENT (Ise> - The output
of change in input offset voltage to change in input common
current available from the amplifier with the output shorted to
mode voltage, expressed in dB.
ground (or other specified potential).

asoc

CMRR

= 20XI0910[:IO]
,
CM

COMMON MODE RESISTANCE (rid - The ratio of change
in input common mode voltage to the resulting change in
input current.
DIFFERENTIAL INPUT RESISTANCE (riD) - The ratio of
change in input differential voltage (small signal, assumes
amplifier operating linearly) to the resulting change in
differential input current.
FULL, POWER BANDWIDTH (FPBW) - The maximum
frequency at which a full scale undistorted (THO < 1%) sine
wave can be obtained at the output of the amplifier.
GAIN BANDWIDTH PRODUCT (GBWP) - The open loop
gain of an op amp (in VN) at a mid-band, linear region frequency (usually between 1kHz and 10kHz) times that frequency (in Hz). GBWP = [Avou • f.
INPUT BIAS CURRENT (I BIAS) - The average of the
currents flowing into or out of the input terminals when the
output is at zero volts.
INPUT CAPACITANCE (C IN) - The equivalent capacitance
seen looking into either input terminal.
INPUT NOISE CURRENT (IN) - The input noise current that
would reproduce the noise seen at the output if all amplifier
noise sources were set to zero and the source impedances
were large compared to the optimum source impedance.

OUTPUT VOLTAGE SWING (VOUT) -The maximum output
voltage swing, referred to ground, that can be obtained
under specified loading conditions.
OVERSHOOT - Peak excursion above final value of an output step response.
POWER SUPPLY REJECTION RATIO (PSRR) - The ratio of
the change in input offset voltage to the change in power
supply voltage producing it.
RISE TIME (tR) - The time required for an output voltage
step to change from 10% to 90% of its final value, when the
input is subjected to a small signal voltage pulse.
SETTLING TIME (tSET) - The time required, aiter application
of a step input signal, for the output voltage to settle and
remain within a specified error band around the final value.
SLEW RATE (SR) - The rate of change of the output under
large signal conditions. Slew rate may be specified
separately for both positive and negative going changes.
SUPPLY CURRENT (Is) - The current required from the
power supply to operate the amplifier with no load and the
output at zero volts.
SUPPLY VOLTAGE RANGE - The range of power supply
voltage over which the amplifier may be safely operated.
UNITY GAIN BANDWIDTH - The frequency range from DC to
that frequency where the amplifier's open loop gain is unity.

3-721

...I

C(U)

Za:

O!!!
-LL
!cc::i

a:

0.

W:::E
~c(

4
COMPARATORS

PAGE
SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-2

COMPARATOR DATA SHEETS

CA139, CA139A,
CA239, CA239A,
CA339, CA339A,
LM339, LM339A,
LM2901 , LM3302

Quad Voltage Comparators for Industrial, Commercial and Military Applications. . . . . . . . . . . ..

4-3

CA3098

Programmable Schmitt Trigger with Memory, Dual Input Precision Level Detector .......... .

4-9

CA3290, CA3290A

BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output .................. .

4-10

HA-4900, HA-4902,
HA-4905

Precision Quad Comparators ................................................... .

4-18

en
a:
0

ti

a:
~

::ii:
0
0

4-1

Selection' Guide
'l

. COMPARATO~S:. Electrical Characteristics, TA = 25°C

.'
TYPE,

'VIO
MAX
(mV)

INPUT
CURRENT
MAX
(nA)

SUPPLY
CURRENT
,MAX
(mA)

SUPPLY VOLTAGE
RANGE
V+, VTYP(V)

(dB)

AoL
MIN

RESPONSE
TIME
TYP(ns)

(NOTE 1)
LEAD COUNT AND
PACKAGE TYPE

COMMENTS

.DUAL UNIT TYPES
CA3290,

20

50pA

3

+5, Oto +lB, -'lB

BB

CA3290A

10

40pA

3

+5,0 to +lB, -lB

BB

. 100

B

+2.5,0 to+1B, -lB

-

tR
tF

=1200
=200

BPDIP, BCan

Low Cost

BPDIP, 14PDIP, BCan

QUAD UNIT TYPES
CA139

5

tR
tF

=1300
=750

14PDIP,'14CERDIP,
14S0lC

Mil Temp Range

CA1,39A

2

100

B

+2.5, Oto+18, -18

94

14PDIP, 14S0lC

Mil Temp Range

CA239

5

250

2

+2.5,0 to +18, -lB

-

14PDIP, 14CERDIP,
14S0lC

Ind Temp Range

CA239A

2

250

2

+2.5, Oto+18, -lB

94

14PDIP, 14CERDIP,
14S01(:

Ir)d Temp Range

CA339

5

250

2

+2.5,0 to +18, -18

-

14PDIP, 14S0lC

CA339A

2

250

2,

+2.5,Oto+18,-18

94

14PDIP, 14S0lC

LM339

5

250

2

+2.5,0 to +18, -lB

14PDIP
14PDIP

LM339A

2

250

2

+2.5,0 to +18, -lB

LM290,l

7

250

2

+2.5,010+18, -18

, LIy13302

94

Low Cost

Low Cost

14S0lC, 14PDIP

Low Cost, Ind Temp

20

500

2

+2.5,010+18, -18

-

14S0lC, 14PDIP

Low Cost, Ind Temp

HA-4900

2

75

+20, -8, +4
(Note 2)

+5,0 to +16.5, -16.5

112

130

16CERDIP

HA-4902

2

150

+20, -8, +4
(Note 2)

+5,0 to +16.5, -16.5

112

130

16CERDIP

Single or Dual Supply.
Analog and Logic
Supplies Separated
for Easier Interface
and NOise Immunity

HA-4905

4

150

+20, -8, +4
(Note 2)

+5,

oto +16.5, -16.5

112

130

16PDIP, 16CERDIP,
16S0lC (300 mil),
20PLCC

NOTE:
,1. See Linear Package Selection Guide in Seclion 11.
2. Positive Supply Current, Negative Supply Current, Logic Supply Current.

4-2

m

CA139, CA139A, CA239, CA239A,
CA339, CA339A, LM339, LM339A,
LM2901, LM3302

HARRIS
SEMICONDUCTOR

Quad Voltage Comparators for Industrial,
Commercial and Military Applications

November 1996

Features

Description

• Operation from Single or Dual Supplies

The devices in this series consist of four independent single or dual
supply voltage comparators on a single monolithic substrate. The
common mode input voltage range includes ground even when operated from a single supply, and the low power supply current drain
makes these comparators suitable for battery operaUon. These types
were deSigned 10 directly interface with TTL and CMOS.

• Common Mode Input Voltage Range to GND
• Output Voltage Compatible with
and CMOS

TTL, DTl, ECl, MOS

• Differential Input Voltage Range Equal to the Supply
Voltage
• Maximum Input Offset Voltage (VIO)
- CA139A, CA239A, CA339A ••••••••••••••••• 2mV
- CA139, CA239, CA339 ••••••••••••••••••••• SmV
- lM2901 ..••.•••.••••••.•••••..•••••••••• 7mV

Types CA139A, CA239A, and CA339A have all the features and
characteristics of their prototype counterparts CA139, CA239, and
CA339 plus an even lower input offset voltage characteristic. All the
SOIC parts are available on tape and reel. Replace the M suffix in
the part number with M96 when ordering (e.g. CA0339AM96). The
CA339 is also available in chip form (H suffix).

- lM3302 •••••••••••••••••..•.•.•••••••.• 20mV

·

or In d ustry Types 139, 239, 3 3 9 , 139 A ,
239A, 339A, 2901, 3302

Rep Iacement

Applications
• Square Wave Generator
• Time Delay Generators
• Pulse Generators
• Multlvlbrators
• High VoHage Digital logic Gates
• AID Converters
• MOS Clock Timers

Ordering Information
TEMP.
PKG.
PART NO. (BRAND)
RANGEfC)
PACKAGE
NO.
14LdPDIP
-5510 125
IE14.3
ICA0139E
-5510 125 14 LdCERDIP E14.3
CA0139F
14LdSOlC
CA0139M,AM (139,139A)
-5510125
M14.15
CA0239E,AE
-251085
14LdPDIP
E14.3
CA0239F,AF
-251085
14 LdCERDIP E14.3
CA0239M, (239)
-251085
14LdSOlC
M14.15
E14.3
01070
14LdPDIP
CA0339E,AE
CA0339M, (339)
01070
14 Ld SOIC
M14.15
LM339N,AN
01070
14 LdPDIP
E14.3
LM2901M (2901)
14LdSOlC
401085
M14.15
14LdPDIP
E14.3
LM2901N
-401085
LM3302M (3302)
14 Ld SOIC
M14.15
-401085
14Ld PDIP
E14.3
LM3302N
-401085

Pinout

Schematic Diagram
v+

CA139, CA239, CA239A (PDIP, CERDIP, SOIC)
CA139A, CA339, CA339A, LM2901, LM3302 (PDIP, S9IC)
LM339, LM339A (PDIP)
TOP VIEW

OUTPUT2

1

OUTPUT 3
OUTPUT 4
GND

NEG. INPUT 1

4

POS.INPUT4

POS. INPUT 1

5

NEG. INPUT 4

NEG. INPUT 2

6

9

POS. INPUT 3

POS. INPUT 2

7

8

NEG. INPUT 3

COMPARATOR NO 1

~

~

~
~~

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

4-3

~

~

File Number

795.3

en
a::
o
~

a::

~

o
o==

CA139, CA139A,·CA239, CA239A, CA339, CA339A, LM339, LM339A, LM2901, LM3302
Absolute Maximum Ratings

Thermal Information

Supply Voltage ........................•...... 36V or ±18V
Differential Input Voltage............................... 36V
Input Voltage ..•.•........................... -0.3V to +S6V
Input Current (VI < -C.3V, Note I) .....•.......•......... 50mA
Output Short Circuit Duration (Single Supply, Note 2) .. Continuous

Thermal Resistance (Typical, Note 3)
9JA (oC/w) 8JC (oC/w)
90
30
CERDIP Package . . . . . . . • . . . . • . . . . .
PDIP Package. . . . . . . . . • . . . . . . . . • . .
100
N/A
SOIC Package. . . . . . . . . . . . . . . . . . . . •
175
N/A
Maximum Junction Temperature (Ceramic Package) ......• 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
CAI39, CAI39A ......................... -55°C to 125°C
CA239, CA239A . . . . . . . . . . . . . . . . . . . . . . . . .. -25°C to 80°C
CA339, CA339A, LM339, LM339A. . . . . . . . . . . . .. OoC to 70°C
LM290l, LM3302 . . • . . . . . . . . . . . . . . . . . . . . .. -40°C to 85°C

CAUTION: Stresses above those /lsted in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only tating and opetation
of the device at these or any other conditions above those Indicated in the opetational sections of this specification is not Implied.

NOTES:
I. Inputs must not go more negative than -0.3V.
2. Short circuits from the output to V + can cause excessive heating and eventual destruction. The maximum output current independent of
V+ is approximately 20mA.
3. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

V+ = 5V, Unless Otherwise Specified
CA139A

CA139
PARAMETER
Input Offset Voltage

Differential Input Voltage

Saturation Voltage

Common Mode Input
Voltage Range

Input Offset Current

Input Bias Current

SYMBOL
VIO

VIO

VSAT

VICR

110

liB

TEST
CONDITIONS

TEMP
(oC)

VREF= I.4V, Rs = 0,
Output Switch Point
V:; I.4V

TA=25

Keep All Inputs ~OV, or
V- (ff used), (Note 5)
VI- = tv, VI+ = OV,
ISINKS4mA

Note 6

11+- 11"

11+ or 11- with Output in
Linear Range

MIN

TYP

MAX

-

2

5

1+

RL=~OnAIi

Note 4

36

TA=25

250

400

Note 4

-

700

-

-

V+-l.5

0

V+-2

0

TA=25

0

Note 4

0

TA=25

-

Note 4

.

TA=25

-

TA=25

Comparators
Output Leakage
Current

Output Sink Current

Voltage Gain

AoL

-

-

Note 4

Note 4
Total Supply Current

MIN

-

3

9

25

UNITS

1

2

mV

-

4

mV

36

V

250

400

mV

-

700

mV

V+-l.5

V

V+-2

V

3

25

nA

-

100

nA

25

100

-

300

0.8

2

-

0.8

0.1

TA=25

0.1

-

-

VI+ ~ tv, VI- = OV,
Vo=30V

Note 4

-

1

-

VI- ~ tv, VI+ = OV, Vo
SI.5V

TA=25

6

16

RL~

TA=25

-

200

4-4

MAX

-

100

VI+ ~ tv, VI- = OV,
VO=5V

15kQ, V+= 15V

TYP

_.

25

100

nA

-

300

nA

2

mA

6

16

50

200

nA

1

I1A

-

mA

V/mV

CA 139, CA 139A, CA239, CA239A, CA339, CA339A, LM339, LM339A, LM2901, LM3302
Electrical Specifications

V+ = 5V, Unless Otherwise Specified (Continued)
CA139

CA139A

TEST
CONDITIONS

TEMP
(oC)

MIN

TYP

MAX

MIN

TYP

Large Signal Response
Time

VI = TTL Logic Swing,
VREF= l.4V, VRL=5V,
RL=5.11

~

~A=~Ocl- I--

~~

TA=2Soc

I""""
~

(J

8:::>

60

0.4

II)

~

0.2

TA=~o06

--

o

-

TA = 12Soc

I--

Vrc=OV
Rrc= 109n

I

I

.s

C-

so

TA=-SSoc

'W

!z

40

TA=Ooc

II:
II:

I--

r-

TA =2Soc

::>
(J

30

!5...

20

1:!:

TA = 70°C
TA = 12Soc

10

10
20
POSITIVE SUPPLY VOLTAGE (V)

o

30

10

20

40

30

POSITIVE SUPPLY VOLTAGE M

FIGURE 2. INPUT CURRENT va SUPPLY VOLTAGE

FIGURE 1. SUPPLY CURRENT vs SUPPLY VOLTAGE

100

~W

TA =2Soc
0

"~

-so

r---~--~--~--+---+-~O

g
!5...

-100

(J)

a:
o

3;

~

4

1--+--+--11--1

!:l

100mV:::.:..jI-l-l

g

3
2

~
g

0 L _ L J............._....I_ _...- - i

~

~
a:
~
:il
o
(.)

sf--+_""'If-"""

w

1

I

1---+-1-1---1--"

o

O.S

1.0
1.S
TIME(j1s)

2.0

FIGURE 4. RESPONSE TIME FOR VARIOUS INPUT .
OVERDRIVES - POSITIVE TRANSITION

FIGURE 3. RESPONSE TIME FOR VARIOUS INPUT
OVERDRIVES - NEGATIVE TRANSITION

10'
TA=2Soc

~

===

OUTOF {
SATURATION

W

~
!:l
z

tc

'-

100

g
Q

",

10-1

II:

a!5

10-2

~

0

~

r---~---+----r---~~~--~SO

~

./
10-1

100

101

OUTPUT SINK CURRENT (mA)

FIGURE 5. OUTPUT SATURATION VOLTAGE va OUTPUT SINK CURRENT

4-7

CA139, CA139A, CA239, CA239A, CA339, CA339A, LM339, LM339A, LM2901, LM3302
Metallization Mask Layout
5450-

51 -5 9
(1.295 -1.499)

-"1 •

0-

1

1__ 4 - 10 (0.102-0.254)

52 - 60 (1.321 -1.524)

•

4-8

NOTE: Dimensions in parentheses
are in mm and are derived from the
basic in. dimensions as indicated. Grid
graduations are in mils (10-3 inch).

CA3098
12 Pro ram mabie Schmitt Trigger with

ua Input Precision Level Detector
~,--

Features

Description

• Programmable Operating' Current

The CA3098 Programmable Schmitt Trigger is a monolithic
silicon integrated circuit designed to control high operating
current loads such as thyristors, lamps, relays, etc, The
CA3098 can be operated with either a single power supply
with maximum operating voltage of 16V, or a dual power
supply with maximum operating voltage of ±8V, It can
directly control currents up to 150mA and operates with
microwatt standby power dissipation when the current to be
controlled is less than 30mA The CA3098 contains the
following major circuit function features (see Block Diagram):

• Micropower Standby Dissipation
• Direct Control of Currents Up to •••.•••••••• l50mA
• Low Input On/Off Current of Less Than 1nA for
Programmable Bias Current of lilA
• Built-in Hysteresis .•....•.•.....•..•.. 20mV (Max)

Applications
• Control of Relays, Heaters, LEOs, Lamps, Photosensitive
Devices, Thyristors, Solenoids, etc.
• Signal Reconditioning
• Phase and Frequency Modulators
• On/Off Motor Switching

2, Flip-flop: the flip-flop functions as a bistable "memory" element that changes state in response to each trigger
command.

• SchmiH Triggers, Level Detectors
• Time Delays
• Overvoltage, Overcurrent, Overtemperature Protection

3, Driver and output stages: these stages permit the circuit
to "sink" maximum peak load currents up to 150mA at
terminal 3.

• BaHery-Operated Equipment
• Square and Triangular-Wave Generators

4, Programmable operating current: the circuit incorporates
access at terminal 2 to permit programming the desired
quiescent operating current and performance parameters,

Ordering Information
PART
NUMBER

TEMP
RANGE (OC)

-55 to 125

CA3098E

1. Differential amplifiers and summer: the circuit uses two
differential amplifiers, one to compare the input voltage
with the "high" reference, and the other to compare the input with the "low" reference, The resultant output of the
differential amplifiers actuates a summer circuit which delivers a trigger that initiates a change in state of a flip-flop,

PACKAGE
8Ld PDIP

Pinout

PKG. NO.
E8,3

1

Block Diagram

Os
CA3098
(PDIP)
TOP VIEW

LOW REF_
I BIAS

2

r--+---.--" -

2

7

+IN
HIGH REF.

OUT

3

6

V+

v-

4

5

CURRENT
CONTROL

I

+

PROGRAMMABLE
BIAS CURRENT
INPUT (IBIAS)

6

V+

OUTPUT
CURRENT
CONTROL

- .. - - - - - , ..---1----{

I

I

t

I

+

SUBSTRATE

CAUTION: These devices are sensilive to electrostatic discharge, Users should lollow proper IC Handling Procedures.
Copyright © Harris COIpOiation 1996

4-9

File Number

896.3

tn

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HARRIS
~

CA3290, CA3290A

SEMICONDUCTOR

BiMOS Dual Voltage Comparators
with MOSFET Input, Bipolar Output

November 1996

Features

Description

• MOSFET Input Stage
- Very High Input Impedance (ZIN) ••••••• 1.710 (Typ)
- Very Low Input Current at V+ = SV ••••• 3.SpA (Typ)
- Wide Common Mode Input Voltage Range (VICW
Can Be Swung 1.SV (Typ) Below Negative Supply
Voltage Rail
- Virtually Eliminates Errors Due to Flow of Input
Currents

The CA3290A and CA3290 types consist of a dual voltage
comparator on a single monolithic chip. The common mode
input voltage range includes ground even when operated
from a single supply. The low supply current drain makes
these comparators suitable for battery operation; their
extremely low input currents allow their use in applications
that employ sensors with extremely high source impedances. Package options are shown in the table below.

• Output Voltage Compatible with TTL, DTL, ECL, MOS,
and CMOS Logic Systems In Most Applications

Ordering Information
PART
NUMBER

Applications
• High Source Impedance Voltage Comparators
• Long Time Delay Circuits
• Square Wave Generators
• AID Converters

TEMP
RANGE (DC)

CA3290AE

-55 to 125

CA3290AE1

-55 to 125

CA3290AT

-55

to 125

PACKAGE
BLdPDIP

PKG.NO.
EB.3

14Ld PDIP

E14.3

B Pin Metal Can

TB.C

CA3290E

-55 to 125

BLd PDIP

CA3290T

-55 to 125

B Pin Metal

EB.3

can

TB.C

• Window Comparators

Pinouts

Schematic Diagram

CA32901A (PDIP)
TOP VIEW

(ONLY ONE IS SHOWN)

OUTPUT(A,)~8

Y+
7 OUTPUT (Aa)

INY.INPUT (Ad

NON~NV. INPUT (Ad

BIASING CIRcurr
FOR CURRENT
SOURCES

\NY. INPUT (Aa)

Aa

y.

COMPARATOR NO.1

NON-INY. INPUT (A2)

v+

TO
COMPo
NO.2

CA3290A (PDIP)
TOP VIEW
INY.INPUT (11,) ,
NON~NV.

4 NC(NOTE)

INPUT (11,) 2
NC(NOTE) 3

D,
D2

NC(NOTE) S
~NV.INPUT

(Aa) 8

9 NC(NOTE)

INY. INPUT (Aa) 7

8 NC(NOTE)

+VI

NOTE: Tie to GND or V+ for best Input/Output Isolation.
CA3290A, CA3290 (METAL CAN)
TOP VIEW

8 \NY. INPUT (Aa)

INY. INPUT (Ad
_____ nL.....-

NON~NY.INPUT

v-

(Aa)

CAUTION: These devices are sensitive to electrosl8tlc discharge. Users should follow proper IC Handling Procedures.
Copyright @Harns Corporation 1996

4-10

File Number

1049.2

CA3290, CA3290A
Absolute Maximum Ratings

Thermal Information

Supply Voltage
Single Supply .................................... +36V
Dual Supply .......................................... ±18V
Differential Input Voltage ................. 36V or [(V+ - V-) +5Vj
(whichever is less)
DC Input Voltage .......................... V+ +5V to V- -5V
Output to V- Short Circuit Duration (Note 1) .......... Continuous
Input Current. ....................................... 1mA

Thermal Resistance (Typical, Note 2)
8JA (OCIW) 9JC (OCIW)
14 Lead PDIP Package.. . .. . . .....
100
N/A
120
N/A
8 Lead PDIP Package. . . . . . . . . . . . .
8 Pin Metal Can Package. . . . . .....
155
67
Maximum Junction Temperature (Can) .................. 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ... . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300o

e

Operating Conditions
Temperature Range ..................... , ..... -55 to 125°C
CAUTION: Stresses above those listed in ''Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
01 the device at these or any other conditions above those indicated in the operational sections of this specification is not Implied.

NOTES:
1. Short circuits from the output to V+ can cause excessive heating and eventual destruction of the device.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

V- = OV, Unless Otherwise Specified
CA3290

CA3290A
PARAMETER
Input Offset Voltage

Temperature Coefficient
of Input Offset Voltage
Input Offset Current

Input Current

SYMBOL
VIO

TEMP
(DC)

TYP

MAX

V CM = Vo = lAV,
V+=5V

Full

4.5

-

VCM=VO=OV,
V+ = +15V, V- = -15V

Full

8.5

-

VCM =Vo =1.4V,
V+=5V

25

4.0

VCM=Vo=OV,
V+ = +15V, V- = -15V

25

TEST CONDITIONS

MIN

-

A.VldA.T

110

II

-

MIN

TYP

MAX

8.5

-

UNITS
mV

en

8.5

-

mV

10

7.5

20

mV

4.0

10

7.5

20

mV

8

-

8

-

IlVt"C

2

28

2

32

nA

7

28

-

7

32

nA

V cM =lAV,V+=5V

Full

VCM=OV, V+=+15V,
V-=-15V

Full

VCM = 1.4V,
V+=5V

25

-

2

25

-

2

30

pA

VCM=OV,
V+ = + 15V, V- = -15V

25

-

7

25

-

7

30

pA

VCM = 1.4V,
V+=5V

125

-

2.8

45

-

2.8

55

nA

VCM= OV,
V+ =+15V, V-= -15V

125

-

13

45

-

13

55

nA

VCM= lAV,
V+=5V

25

3.5

40

-

3.5

50

pA

VCM=OV,
V+ = +15V, V- = -15V

25

12

40

-

12

50

pA

4-11

-

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o
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CA3290, CA3290A
Electrical Specifications

V- = OV, Unless Otherwise Specified (Continued)
CA3290A

PARAMETER
Supply Current

Voltage Gain

SYMBOL
1+

AoL

TEST CONDITIONS

Output Leakage .Current

Common Mode Input
Voltage Range

Common Mode
Rejection Ratio
Power Supply Rejection
Ratio

V SAT

IOL

VieR

CMRR

PSRR

MIN

TYP

CA3290
MAX

MIN

TYP

-

RL=~' V+=5V

-55

0.85

1.0

RL =~, V+ = 30V

-55

1.62

3.0

RL=~' V+=5V

25

RL=~' V+=30V

25

RL = 151Ul, V+ =+15V,
V-=-15V

Full

RL = 15kn,
V+ = +15V, V- = -15V
Saturation Voltage

TEMP
(DC)

25

ISINK = 4mA, V+ = 5V,
+VI =OV, -VI = 1V

125

ISINK = 4mA, V+ = 5V,
+VI = OV, -VI = lV

-55

ISINK =4mA, V+=5V,
+VI = OV, -VI = lV

-

0.8

1.4

1.35

3.0

-

103

25

BOO

88

118

150

-

MAX

UNITS

0.85

1.6

mA

1.62

3.5

mA

0.8

1.4

mA

1.35

3.0

V/mV

103

dB

25

BOO

VlmV

8B

118

dB

0.22

0.7

0.22

0.7

V

-

0.1

-

0.1

-

V

25

-

0.12

0.4

0.12

0.4

V

V+= 15V

Full

-

V+=36V

Full

lk

nA

V+= 15V

25

65

-

130

lk

-

100

-

500

65

-

130

pA

-

500

pA

V+-3.5
V-

V+-3.1
V- -1.5

V

V+-3.B
V-

V+-3.4
V--l.6

V+=36V

25

Vo = 1.4V, V+ = 5V

25

V+-3.5
V-

V+-3.1
V--l.5

Vo=OV,
V+ = +15V, V- = -15V

25

V+-3.B
V-

V+-3.4
V--l.6
44

562

100

562

15

316

15

V+ = +15V, V- = -15V

25

V+=5V

25

V+ = +15V, V- = -15V

25

-

-

-

V

44

562

IlVN

100

562

IlVN

316

IlVN

Vo = 1.4V, V+ = 5V

25

6

30

-

6

30

t,

RL = 5.1kn, V+ = 15V

25

-

1.2

-

-

1.2

Response Time Falling
Edge

tf

RL = 5.1kn, V+ = 15V

25 .

-

200

RL = 5.1kn, V+ = 15V

25

RL = 5.1kn, V+ = 5V

25

Large Signal Response
Time

4-12

200

500

-

400

-

nA

100

Response Time Rising
Edge

Output Sink Current

mA

150

-

-

mA

IlS
ns

500

-

ns

400

-

ns

CA3290, CA3290A
Test Circuits and Waveforms

Cc =2pF
+15V
+15V

T010X

> ......... ~~g:~
WITHOUTC c

WITHCC

=

Top Trace ~ 4.5mV/DiY. VIN
Bottom Trace = 10V/Diy. = VOUT
Time Scale = 511S/Diy.

Top Trace = 4.5mV/DiY.
Bottom Trace = 10V/Diy.
Time Scale = 511S/Diy.

FIGURE 1. PARASITIC OSCILLATIONS TEST CIRCUIT AND WAVEFORMS

+15V

INPUT {
OVERDRIVE
GND _

INPUT {
OVERDRIVE
GND _

rn

a:
0

-

100mV
OVERDRIVE

/

, "-

20mV
OVERDRIVE

~
a:
~

:!i!
0
0

5mV
OVERDRIVE

5mV
OVERDRIVE

2DmV
OVERDRIVE

100mV
OVERDRIVE

FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS.

+15V

5mV
OVERDRIVE

2DmV
OVERDRIVE

100mV
OVERDRIVE

100mV
OVERDRIVE

2DmV
OVERDRIVE

FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS

4-13

5mV
OVERDRIVE

CA3290, CA3290A
Circuit Description

Operating Considerations

The Basic Comparator

Input Circuit

Figure 4 shows the basic circuit diagram for one of the two
comparators in the CA3290. It is generically similar to the
industry type "139" comparators, with PMOS transistors
replacing PNP transistors as input stage elements. Transistors
1 through 4 comprise the differential input stage, with
and
serving as a mirror connected active load and differential-to-single-ended converter. The differential input at 1 and
in accordance with the input
4 is amplified so as to toggle
signal polarity. For example, if +VIN is greater than -VIN' 1,
and Os will be turned off;
2 , and current mirror transistors
Transistors 3 , 4, and 0 7 will be turned on, causing
to be
turned off. The output is pulled positive when a load resistor is
connected between the output and V+.

a

as

a

as

a
a

as

a a

1. Ultra high input impedance (=1.7TO);

a

as

2. The availability of common mode rejection for input signals
at potentials be.low that of the negative power supply rail;

a

as

In essence, a 1 and a4 function as source followers to drive
a2 and a3, respectively, with zener diodes 0 1 through 0 4
providing gate oxide protection against input voltage
transients (e.g., static electricity). The current flow in 01 and
4 is established at approximately 50llA by constant current
sources 11 and 13, respectively. Since 0 1 and a4 are
operated with a constant current load, their gate-to-source
voltage drops will be effectively constant as long as the input
voltages are within the common-mode range.

3. Retention of the in phase relationship of the input and output signals for input signals below the negative rail.
Although the CA3290 employs rugged bipolar (zener) diodes
for protection of the input circuit, the input terminal currents
should not exceed 1mAo Appropriate series connected limiting resistors should be used in circuits where greater current
flows might exist, allowing the signal input voltage to be
greater than the supply voltage without damaging the circuit.

a

Output Circuit

As a result, the input offset voltage (VGS(Ql) + VBE (Q2)

The output of the CA3290 is the open collector of an n-p-n
transistor, a feature providing flexibility in a broad range of
comparator applications. An output ORing function can be
implemented by parallel connection of the open collectors.
An output pull-up resistor can be connected to a power
supply having a voltage range within the rating of the
particular CA3290 in use; the magnitude of this voltage may
be set at a value which is independent of that applied tothe
V+ terminal of the CA3290.

-

VBE (Q3) - VGS(C4» will not be degraded when a large
differential DC voltage is applied to the device for extended
periods of time at high temperatures.
Additional voltage gain following the first stage is provided by
transistors 0 7 and Oa. The collector of Oa is open, offering
the user a wide variety of options in applications. An
additional discrete transistor can be added if it becomes
necessary to boost the output sink current capability.

I

The use of MOS transistors in the input stage of the CA3290
series circuits provides the user with the following features
for comparator applications:

The detailed schematic diagram for one comparator and the
common current source biasing is shown on the front page.
PMOS transistors 0 9 through 0 12 are the current source elements identified in Figure 4 as 11 through 14, respectively. Their
gate source potentials (VGs) are supplied by a common bus
from the biasing circuit shown in the right hand portion of the
Schematic Diagram. The currents supplied by a10 and 012
are twice those supplied by 09 and 011' The transistor geometries are appropriately scaled to provide the requisite currents with common VGS applied to 0 9 through 0 12,

vFIGURE 4. BASIC CIRCUIT DIAGRAM FOR ONE OF THE TWO
COMPARATORS

Parasitic Oscillations
The ideal comparator has, among other features, ultra high
input impedance, high gain, and wide bandwidth. These
desirable characteristics may, however, produce parasitic
oscillations unless certain precautions are observed to
minimize the stray capacitive coupling between the input and
output terminals. Parasitic oscillations manifest themselves
during the output voltage transition intervals as the
comparator switches states. For high source impedances,
stray capacitance can induce parasitic oscillations. The
addition of a small amount (1mV to 10mV) of positive
feedback (hysteresis) produces a faster transition, thereby
reducing the likelihood of parasitic oscillations. Furthermore,
if the input Signal is a pulse waveform, with relatively rapid
rise and fall times, parasitic tendencies are reduced.
When dual comparators, like the CA3290, are packaged in
an 8 lead configuration, the output terminal of each
comparator is adjacent to an input terminal. The lead-to-Iead
capacitance is approximately 1pF, which may be sufficient to
cause undesirable feedback effects in certain applications.
Circuit factors such as impedance levels, supply voltage,
switching rate, etc., may increase the possibility of parasitic
oscillations. To minimize this potential OSCillatory condition, it
is recommended that for source impedances greater than
1kO a capacitor (~1pF - 2pF) be connected between the
appropriate input terminal and the output terminal. (See
Figure 1.)

4-14

CA3290, CA3290A
The CA3290A is also supplied in a 14 lead dual-in-line
plastic package. To minimize the possibility of parasitic
oscillations the input and Qutput ~erminals are positioned on
opposite sides of the package. In addition, there are two
leads between the output terminal of eac\:! comparator and
its corresponding inverting input terminal, reducing the
input/output coupling significantly. These leads (8, 9, 13, 14)
should be tied to either the V+ or V- supply rail. If either
comparator is unused, its input terminals should also be tied
to either the V+ or V- supply' rail.

+15V
+15V

+15V

1M1l

Typical Applications
1MO

Light Controlled One-Shot Timer

t = Period = lOs

In Figure 5 one comparator (A1) of the CA3290 is used to
sense a change i~ photo diode current. The other comparator (A2) is configured,as a one-shot timer and is triggered by
the output of A 1 . The output of the circuit will switch to a low
state for approximately 60 seconds after the light source to
the photo diode has been interrupted. The circuit operates at
normal room lighting levels. The sensitivity of the circuit may
be adjusted by changing the values of R1 and R2. The ratio
of R1 to R2 should be constant to insure constant reverse
voltage bias on the photo diode.

+15V

+15V

Rz

t = 2R 1CloQe (

2R p

R2 + 1)

1MO

FIGURE 6. LOW FREQUENCY MULTIVIBRATOR

Window Comparator
Both halves of the CA3290 can be used in a high input
impedance window comparator as shown in Figure 7. The
LED will be turned "on" whenever the input signal is above
the lower limit (Vd but below the upper limit (V u), as
determined by the R1/R2"R3 resistor divider.

+15V

en
a::

o

+15V

~

a::

~

3.3kO

LED

1.0"F
6700
INPUT

-=-

X 60s TIME

FIGURE 5. LIGHT CONTROLLED ONE-SHOT TIMER

Low-Frequency Multivibrator
In this application, one half of the CA3290 is used as a
conventional multivibrator circuit. Because of the extremely
high input impedance of this device, large values of timing
resistor (R 1) may be used for long time delays with relatively
small leakage timing capaCitors. The second half of the
CA3290 is used as an output buffer to insure that the
multivibrator frequency will not be affected by output loading.
Rp is the parallel combination of the two 1Mn resistors connected between + 15V and GND.

4-15

FIGURE 7. WINDOW COMPARATOR

::E

o
o

CA3290, CA3290A
Typical Performance Curves
4.0

RL=OO
3.5

0 TA=25"C
V+ = +30V, V- = GND

C

3.0

-5

!zw

2.5

g

IC
IC

a
~

1.5

:;)
CI)

1.0

.... ,'.... '

-- -

2.0

_25°C

l,..- I""'"

II.

po

-10

IC
IC

-15

!zw

-550C

......

i

5

10

15

20

25

.....

II.

\

-25

30

35

40

45

5

ci

;

w -1.5

4.0

.....

3.5

..... ~

3.0

~

ztil
52

..... ......
~

2.0

3.0

4.0

~

-2.5

./ ./

-3.0

--

-4.0

o

5.0

5

10

15

20

25

30

10K

~

05

r---

35

~

40

45

FIGURE 11. POSITIVE COMMON MODE INPUT VOLTAGE
RANGE VB SUPPLY VOLTAGE

1.0

0

.....I--

PosmVE SUPPLY VOLTAGE (V)

125°C

V+ = +15Y, v- = -15V
VCM=O~

IC
IC
:;)

./

/

I'"

100

./

,

/
./

lK

!zw

-0.5

V+=5V,V-=OV
VCM=IAV

U

~

-1.0

§U -1.5 I- 250C
II.
~

......... .........

u -3.5
><
w

~

1;1
!;

-SSOC

L.. L

:;)

FIGURE 10. INPUT CURRENT VB INPUT COMMON MODE
VOLTAGE

~
52

25°C

Il!

!;
1.0

125"C

-2.0

INPUT COMMON MODE VOLTAGE (V)

;

35

IC

:::

o

~

30

-1.0

II.
~

I

25

~

2.5

ci

20

I-

U

~

15

FIGURE 9. INPUT CURRENT VB INPUT COMMON MODE
VOLTAGE

4.5

!;

10

INPUT COMMON MODE VOLTAGE M

TA = 25°C
V+ = +5V, V- = GND

:;)

.....

-20

~

FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE (BOTH
AMPLIFIERS)

!z
II!IC

.....

U

!;

125"C

TOTAL SUPPLY VOLTAGE M

i

.....

:;)

0.5

o
o

.....

-2.0

~

/

10

~

---:550C
I
-2.5 0
5
10

15

20

25

30

35

40

1

45

NEGATIVE SUPPLY VOLTAGE M

FIGURE 12. NEGATIVE COMMON MODE INPUT VOLTAGE
RANGE VB SUPPLY VOLTAGE

1/

,. ,.
o

./
/

/
20

40

60
80
100
TEMPERATURE ("C)

120

FIGURE 13. INPUT CURRENT VB TEMPERATURE

4-16

140

CA3290, CA3290A
Typical Performance Curves

(Continued)

10V
125°C
25°C
-550C

w

~

!j

~

1V

; 100mV
::>

IiUl

5

§

E

f=

C::: 125 C
25°C
I- -550C' .........

~i

10mV

lmV
10J.lA

If

f::

100J.lA

..oIII!!Il

lmA

'I
fJ- f=
If

-

l-

10mA

OUTPUT SINK CURRENT

FIGURE 14. OUTPUT SATURATION VOLTAGE vs OUTPUT SINK CURRENT

Metallization Mask Layout
o

10

20

40

5053

en
o

II:

87·95
(2.210 • 2.403)

The photographs and dimensions of each chip represent a chip
when it is part of the wafer. When the wafer is cut into chips, the
cleavage angles are 57" instead of 90° with respect to the face of
the chip. Therefore, the isolated chip is actually 7mils (0.17mm)
larger in both dimensions.
Dimensions in parentheses are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in mils
(10-3 inch)
NOTE: Numbers in pads are for 8 lead DIP and TO-5 Can and
numbers outside of chip are for 14 lead DIP.

4·17

~

II:

~

:::!ii

o
o

HA-4900, HA-4902,
HA-4905
Precision Quad
Comparators
,

November 1996

,

'

Features

Description

• Fast Response Time .•.•.....•..•....•..•.• 130ns

The HA-4900 sedes are monolithk quad, preCision comparators offerihg' fast response time, low offset 'voltage, low offset current and virtually no 'channel-to-channel cross,talk for
applications requiring accurate, high speed, signal level
detection. These .comparators can sarse signals at ground
level while being operated from either a single +5V supply
(digital systems) .or from dual supplies (analog networks) up
to ±15V. The, HA-4900 series contjl.ins a, unique current
driven output stage which can be connected to logic system
supplies (VLOGIC+ and VLOGIC-) to make the output levels
directly compatible (no external components needed) with
any standard logic or special system logic levels. In
combination analog/digital systems, the design employed in
the HA-4900 series input and output 'stages prevents
troublesome ground coupling of signals betweell analog and
digital portions of the system.

• Low Offset Voltage .••.••••..•••.•...•.•••.. 2.0mV
• Low Offset Current •...•...••.••....•.•.•••. 10nA
• Single or Dual Voltage Supply Operation
• Selectable Output Logic Levels
• Active Pull-Up/Pull-Down Output Circuit. No External
Resistors Required

Applications
• Threshold Detector
• Zero Crossing Detector
• Window Detector
• Analog Interfaces for Microprocessors
• High Stability Oscillators

These comparators' combination of features, make them
ideal components for signal detection and processing in data
acquisition systems, test equipment and microprocessor/~nalog signal interface network~.

• Logic System Interfaces

Ordering Information
PART
NUMBER

TEMP RANGE
(DC)

PACKAGE

HA1·4900·2

-55 to 125

16LdCERDIP

F16.3

HA1-4902·2

·55 to 125

16 LdCERDIP

F16.3

HA1-4905·5

Oto 75

16LdCERDIP

F16.3

HA3-4905·5

Ot075

16Ld PDIP

E16.3

HA4P4905-5

Ot075

20 Ld PLCC

N20.35

HA9P4905-5

Oto 75

16 Ld SOIC

M16.3

Pinouts

PKG.NO.

For military grade procluct, refer, to the HA-4902l883 data
sheet.

HA-4900, HA-4902 (CERDIP)
HA-490S (PDIP, CERDIP, SOIC)
TOP VIEW

HA-4905
,(PLCC)
TOP VIEW

5 ~

OUT 4

0

()

z

...

if

-IN 4

CAUTION: These devices are sensilive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

4-18

File Number

2855.2'

HA-4900, HA-4902, HA-4905
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V- Terminals) ............. 33V
Differential Input Voltage............................... 15V
Voltage Between VLOGIC+ and VLOGIC- ..........•...•...• 18V
Output Current .......•........................•.... 50mA
Power Dissipation (Notes 1, 2)

Thermal Resistance (Typical, Note 3)
0JA (OCIW) 0JC (OCIW)
CERDIP Package . . . . • . . . . . . . . . . .
85
25
PDIP Package. . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package. . . . .. . . . . . . . . . . . . .
100
N/A
PLCC Package . . . . . . . . . . . . . . . . . •
75
N/A
Maximum Junction Temperature (Ceramic Package) ....... 175°C
Maximum Junction Temperature (Plastic Package) .....•.. 150°C
Maximum Storage Temperature Range •........ -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ...........•. 300°C
(PLCC and SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-4900-2, HA-4902-2 ..................... -55 0 C to 1250 C
HA-4905-5 ................................. OoC to 750 C

Die Characteristics
Back Side Potential ............•..................... VNumber of Transistors . . . . . . . . . • . . . . . . . • . . . . . . . • . . . . . 137
Die Size ............................... 95 mils x 105 miis
CAUTION: StressllS above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only mtlng and opemtlon
of the device at these or any other conditions above those Indicated in the opemtional sections of this specification is not Implied.

NOTES:
1. Maximum power dissipation, including output ioad, must be designed to maintain the junction temperature below 1750 C for ceramic
packages, and below 150°C for plastic packages.
2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and V LOG1C shown in curves of Power Dissipation vs Supply Voltages (see Performance Curves). The calculated T.P .D. is then located on the graph of Maximum Allowable Package
Dissipation vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated T.P.D. (See
Performance Curves). For instance, the combination of +15V, -15V, +5V, OV (V+, V-, V LOG1C+, VLOG1c-l gives a T.P.D. of 350mW, the
combination +15V, -15V, +15V, OV gives a T.P.D. of 450mW.
U)

3. 0JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

PARAMETER

VSUPPLY

TEMP
(OC)

a:

o
lei:

=±15V, VLOGIC+ =5V, VLOGIC- =GND
HA-4900-2
-55°C to 125°C
MIN

HA-4902-2
-55°C to 125°C

TYP

MAX

2

3

-

4

10

25

MIN

a:
~

HA-4905-S
OOC to 75°C

TYP

MAX

2

5

MIN

:::!:

TYP

MAX

UNITS

4

7.5

mV

-

10

mV

25

50

nA

INPUT CHARACTERISTICS
Offset Voltage (Note 4)

25
Full

Offset Current

-

25

-

-

35

25

50

75

Full

-

-

150

25

-

-

Full

-

-

Common Mode Range

Full

V-

Differential Input Resistance

25

Full
Bias Current (Note 5)

Input Sensitivity (Note 6)

V,O +
0.3

8

-

10

35

50

150

45

-

200
V,O +
0.5

V,O+
0.4

-

V-

-

250

-

-

250

400

-

130

200

-

180

215

-

(V+)2.6

70

nA

150

nA

-

300

nA

V,O +
0.5

mV

V 1O +
0.7

mV

(V+)2.4

V

-

V,O+
0.6

(V+)2.4

,

100

V-

-

-

250

MQ

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

25

Response Time (tpo(O»
(Note 7)

25

-

Response Time (tpo(l))
(Note 7)

25

-

4-19

400

-

130

200

180

215

-

400

-

kVN

130

200

ns

180

215

ns

o
o

HA-4900, HA-4902, HA-4905
VSUPPLY =±15V, VLOGIC+ =5V, VLOGIC- =GND (Continued)

Electrical Specifications

HA-4900-2
-550 C to 125°C

HA-4902-2
-550 C to 125°C

HA-4905-6
OOC to 75°C

TEMP
(OC)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Logic "Low State" (Vod
(Note 8)

Full

-

0.2

0.4

-

0.2

0.4

-

0.2

0.4

V

Logic "High State" (VOH )
(Note 8)

Full

3.5

4.2

-

3.5

4.2

3.5

4.2

-

V

ISINK

Full

3.0

3.0

mA

-

3.0

-

3.0

-

-

3.0

-

3.0

Full

-

-

ISOURCE

6.5

20

-

6.5

20

-

7

20

4

8

5

8

mA

-

3.5

4

-

3.5

4

mA

-

+15.0

0

V

-15.0

-

+15.0

0

0

V

PARAMETER
OUTPUT CHARACTERISTICS
Output Voltage Level

Output Current

mA

POWER SUPPLY CHARACTERISTICS
Supply Current, Ips (+)

25

Supply Current, Ips (-)

25

Supply Current, IpS (Logic)

25

-

4

8

3.5

4

mA

Supply Voltage Range
VLOGlC+ (Note 2)

Full

0

-

+15.0

0

VLOGIC- (Note 2)

Full

-15.0

-

0

-15.0

NOTES:
4. Minimum differential input voltage required to ensure a defined output state.
5. Input bias currents are essentially constant with differential input voltages up to ±9V. With differential input voltages from ±9V to ±15V,
bias current on the more negative input can rise to approximately 500"A. This will also cause higher supply currents.
6. VCM =OV. Input sensitivity is the worst case minimum differential input voltage required to guarantee a given output logic state. This
parameter includes the effects of offset voltage and voltage gain.
7. For tpo(I); 100mV input step, -1 OmV overdrive. For tpo(O); -100mV input step, 10mV overdrive. Frequency'" 1OOHz; Duty Cycle'" 50%;
Inverting input driven. See Figure 1 for Test Circuit. All unused inverting inputs tied to +5V.
8. ForVOH and VOL: ISINK =ISOURCE =3.0mA. For other values of VLOG1C ; VO H (Min) =VLOGIC+-l.5V.

Test Circuit and Waveform

..

~
OUT

G~
':,.:

......

,r-+
-15V

IpoIl)

'PolO)
OVERDRIVE

t

VOUT

•..L
•

------V1H=OV

-

Iv

t t

INPUT l00mV

•

OVERDRIVE

OUTPUT

-

IpD(O)
1=0

FIGURE 1.

4-20

tv
_

- - ____ V1H=OV

jw

_ _ lpD(1)
1=0

HA-4900, HA-4902, HA-4905
Schematic Diagram

ONE FOURTH ONLY

Applying the HA-4900 Series Comparators
Supply Connections

Power Supply Decoupling

This device is exceptionally versatile in worJ...,.._----

PROCESSOR
HIGH REF

--HH

HIGH

+5.0V

Logic Level Translators
The HA-4900 series comparators can be used as versatile
logic interface devices as shown in the circuits above.
Negative logic devices may also be interfaced with
appropriate supply connections. If separate supplies are
used for V- and VLOGIC-, these logic level translators will
tolerate several volts of ground line differential noise.

-15V

LOW REF

IN
WINDOW

--+-';--1

v+

+5.0V
+5VTO +15V

r----+

112 HA-4900

+5.ov

10110

Oscillator/Clock Generator
This self-starting fixed frequency oscillator circuit gives
excellent frequency stability. R1 and C 1 comprise the
frequency determining network while R2 provides the
regenerative feedback. Diode D1 enhances the stability by
compensating for the difference between VOH and VSUPPLY.
In applications where a precision clock generator up to
100kHz is required, such as in automatic test equipment, C 1
may be replaced by a crystal.
Rz

V+

TTL TO CMOS

150110

CMOS TO TTL
1N914

RS·232 To CMOS Line Receiver
150110

This RS-232 type line receiver to drive CMOS logic uses a
Schmit! trigger feedback network to give about 1V input hysteresis for added noise immunity. A possible problem in an
interface which connects two equipments, each plugged into
a different AC receptacle, is that the power line voltage may
appear at the receiver input when the interface connection is
made or broken. The two diodes and a 3W input resistor will
protect the inputs under these conditions.

150110

-!-

C1

4.7110

3W

Schmitt Trigger (Zero Crossing Detector With Hysteresis)
1110

51110
1N40018
1110

This circuit has a 100mV hysteresis which can be used in
applications where very fast transition times are required at
the output even though the signal input is very slow. The
hysteresis loop also reduces false triggering due to noise on
the input. The waveforms below show the trip points
developed by the hysteresis loop.

4-22

HA-4900, HA-4902, HA-490S

Ra
13kn

-

·15V

INPUT TO OUTPUT WAVEFORM SHOWING HYSTERESIS TRIP
POINTS

Typical Performance Curves

TA = 250 C, Vs = ±15V, VLOG1C+ = 5V, VLOGIC· = OV, Unless Otherwise Specified

100

C

80

.s

~

60

II:

G
~

~

C 15

.s
!z
UJ

.. ..........

II:
II:

10

i"""-...

CJ

Iii
...Ie

40
20

ii!:

o
·55

·25

o

25

50

75

100

0

·25

·55

125

TEMPERATURE (oC)

C

.s
!zUJ

60

CJ

- "-

50

['....
f"""',

40

\

~
ID

!5...

25

20

ii!:

o
·15

75

100

125

TEMPERATURE <"C)

II:
II:

::>

o

FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE

FIGURE 2. INPUT BIAS CURRENT VB TEMPERATURE

80

1\

I

!5...

ii!:

/

5

0

.........

~

::>

·12

·9

-6

-3

0

+3

+6

+9

+12 +15

COMMON MODE INPUT VOLTAGE

FIGURE 4. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE (VD1FF

4·23

=OV)

HA-4900, HA-4902, HA-4905
Typical Performance Curves

TA = 2SoC, Vs = ±1SV, VLOGIC+ = SV, VLOGIC- = OV,Uniess Otherwise Specified (Continued)

~

I

VS=±15V
VLOGIC+ =5V
VLOGIC- = GND

10

I

IpS~OUT=H

Ips+. VOUT = L _

-

8

!z:w

--

7

12

Ips+, VOUT = H

---......

Ips+, VOUT = H

I

II:
II:

6

~

Ips-. VOUT = L

-"",..-

Ips+. VOUT = L

-

IpsL. VOUT

(J

~

......

4

~

IpsL, Vour

III

Ips-. VOUT = H

=L

2

V+ =5V. V-=GND
VLOGIC+ =5V
VLOG1C'"=GND

IpsL. VOUT = H
0
-50

-25

0

25

50

75

100

o

125

~

~

FIGURE 5. SUPPLY CURRENT vs TEMPERATURE (FOR ±15V
SUPPLIES AND +5V LOGIC SUPPLy)

5

~
!;
~

~VER~RIV~ = 20~V _

~

"

3

OVERDRIVE = 5mV

_

~\, l......- OVERDRIVE = 2mV

2

n

0
~
~
TEMPERATURE (Oe)

TEMPERATURE (Oe)

4

.:L'"

m

100

FIGURE 6. SUPPLY CURRENTvs TEMPERATURE (FOR SINGLE
+5V OPERATION)

5

-

4

~
!;

3

~

\' ~

OVERDRIVE = 20mV
OVERDRIVE = 5mV ............

2

\ 1\\

I

o

u

~

~~ ~
Iff

-

OVERDRIVE = 2mV -

.~
+100mV

o

~

o

-loomV

o

100

200

300

-

o

400

200
TIME (ns)

100

TIME (ns)

300

400

FIGURE 7. RESPONSE TIME FOR VARIOUS INPUT OVERDRIVES

2.0

250

1.75

~

z

Q

Ii
e;

.E.

1.25

0

III

!II

1.0

c
w

~

0.75

~

~

~ 200

1.50

~

z

~
u;

1~

~

~

II:

w

~
...

~."

~

~

o
0

25

50
75
100
TEMPERATURE (Oe)

125

FIGURE 8. MAXIMUM PACKAGE DISSIPATION vs AMBIENT
TEMPERATURE

~

..... ......

0.25
0

~~

.....,..
I

!II 100
c

0.50

1/

V+

o

2

4

V-~

,.,.,. io"""

,.,.,. ,.,.,. i-"""

6

...... ~ P
~

I'VLOGIC+ _

I
8

10
SUPPLY VOLTAGE (V)

~

12

I I
14

FIGURE 9. POWER DISSIPATION vs SUPPLY VOLTAGE (NO
LOAD CONDITION)

4-24

5
SAMPLE AND HOLD AMPLIFIERS

PAGE
SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-2

SAMPLE AND HOLD AMPLIFIER DATA SHEETS

HA-2420, HA-2425

3.21!S Sample and Hold Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-3

HA-5320

11!S Precision Sample and Hold Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-12

HA-5330

650ns Precision Sample and Hold Amplifier. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..

5-19

HA-5340

700ns, Low Distortion, Precision Sample and Hold Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-24

HA5351

64ns Sample and Hold Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-32

c
-len
00::

:I:W

-u::
W-1-1

Il.Il.

:!E:!E

«
en

5-1

Selection Guide
SAMPLE AND HOLD AMPLIFIERS:

Typical Values at 25°C, Unless Otherwise Specified

TEMP.
RANGE
(oC)

LEAD COUNT AND
PACKAGE TYPE

ACQUISITION
TIME
(TO 0.01%)

-5510125

14 CERDIP

HA1-2425-5

01075

14CERDIP

HA3-2425-5

01075

14PDIP

HA4P2425-5

01075

20 PLCC

HA9P2425-5

Ot075

14S0lC

-55 to 125

14CERDIP

01075

14 CERDIP

-5510125

14 CERDIP

TYPE
HA1-2420-2

HA1-5320-2
HA1-5320-5
HA 1-5320/883

SAMPLElHOLD
TYPE
Extemal Hold
Cap, Low COst

High Speed,
Low Charge,
Transfer, Precision,
Includes Hold
Capacilor

HA3-5320-5

(NOTE 1)

01075

14 PDIP

-5510125

20CLCC

HA9P5320-5

01075

16 SOIC (300 mil)

HA9P5320-9

-401085

16 SOIC (300 mil)

01075

14 CERDIP

-251085

14 CERDIP

-5510125

14CERDIP

-5510125

14CERDIP

010 75

14 PDIP

-5510125

20CLCC

01075

14 CERDIP

-40 to 85

14CERDIP

-5510125

14CERDIP

HA3-5340-5

Ot075

. 14PDIP

HA3-5340-9

-401085

14PDIP

HA4-5340/883

-55 to 125

20CLCC

01075

16 SOIC (300 mil)

-401085

8PDIP

-401085

.8S01C

HA4-5320/883

HA1-5330-5
HA1-5330-4
HA1-5330-2

Very High Speed,
Precision,
Monolithic,
Includes Hold
Capacitor

HA1-5330/883
HA3-5330-5
HA4-5330/8B3
HA1-5340-5
HA1-5340-9

High Speed,
Low Distortion,
Includes Hold
capacilor

HA 1-5340/883

HA9P5340-5
HA53511P
HA53511B

Ultra High Speed
and Low Power,
Includes Hold
capacilor,
Low Pin Count

NOTE:
1. See Linear Package Selection Guide in Section 11.

5-2

HOLD STEP APERTURE

GAIN
BANDWIDTH
PRODUCT

ERROR

TIME

3.2j1S

10mV

30ns

2.5MHz
(CH = 1000pF)

lj1S
(CH = Intemal)

lmV

25ns

2.0MHz
(CH = 100pF)

650ns

0.5mV

20ns

4.5MHz

700ns

15mV

15ns

10MHz

64ns

10mV

10ns

40MHz

HA-2420, HA-2425
3.2JlS Sample and Hold Amplifiers

November 1996

Features

Description

• Maximum Acquisition Time
- 10V Step to 0.1%..•..•.......••......
- 10V Step to 0.01%.••....•............

The HA-2420 and HA-2425 is a monolithic circuit consisting
of a high performance operational amplifier with its output in
series with an ultra-low leakage analog switch and JFET
input unity gain amplifier.

• Low Droop Rate (CH

=1000pF). . • . . • ..

4~s
6~s

5~Vlms

(Max)
(Max)
(Typ)

• Gain Bandwidth Product ••••••••••••• 2.5MHz (Typ)
• Low Effective Aperture Delay Time .•...•• 30ns (Typ)
• TTL Compatible Control Input
• ±12V to ±15V Operation

Applications

Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular, and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth, and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling ampliiiers.

• 12-Bit Data Acquisition
• Digital to Analog Deglitcher
• Auto Zero Systems
• Peak Detector
• Gated Operational Amplifier

Ordering Information
PART NUMBER
HAI-2420-2

TEMP.
RANGE (oC)
-55

to 125

With an external hold capacitor connected to the switch output,
a versatile, high performance sample-and-hold or track-andhold circuit is formed. When the switch is closed, the device
behaves as an operational amplifier, and any of the standard op
amp feedback networks may be connected around the device
10 control gain, frequency response, etc. When the switch is
opened the output will remain at its last level.

PACKAGE

PKG.
NO.

14LdCERDIP

F14.3

HA1·2425-5

01075

14LdCERDIP

F14.3

HA3·2425-5

01075

14Ld PDIP

E14.3

HA4P2425·5

01075

20Ld PLCC

N20.35

HA9P2425-5

01075

14LdSOlC

M14.15

The device may also be used as a versatile operational
amplifier with a gated output for applications such as analog
switches, peak holding circuits, etc. For more information,
please see Application Note AN517.
The MIL-STD-883 data sheet for this device is available on
request.

Pinouts
HA-2420 (CERDIP)
HA-2425 (CERDIP, PDIP, SOIC)
TOP VIEW

HA-2425
(PLCC)
TOP VIEW

z
4

0

"+ ~ z 12l

SiH CONTROL

OFFSET ADJ.

3

OFFSET ADJ.

OFFSET ADJ.

4

NC

c

z

CJ

NC
NC
HOLD CAP.

OUTPUT 7

NC

NC

v-

NC

+
0
z 0t:; 0z z >

0

CAUTION: These devices are sensitive to electrostatic discharge. Users should fOllOW proper IC Handling Procedures.
Copyright

© Hams Corporation 1996

5-3

File Number

2856.2

o

..../UJ

Oa:

:z::w

w!!;
a.. a..
:E:E
ctct
..../..../

UJ

HA-2420, HA-2425
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals ................•... 40V
Differential Input Voltage............................... 24V
Digital Input Voltage (Sample and Hold Pin) .......... +8V, -15V
Output Current ....................... Short Circuit Protected

Thermal Resistance (Typical, Note 1)
BJA (oCIW) BJC (oCIW)
CERDIP Package . . . . . . . . . . . . . . . . . .
90
35
PDIP Package. . . . . . . . . . . . . . . . . . . . .
100
N/A
PLCC Package .... . . . . . . . . . . . . . . . .
75
N/A
SOIC Package. . . . . . . . . . . . . . . . . . . . .
120
N/A
Maximum Junction Temperature (Ceramic Packages) ....... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range .. . . • . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os) ............. 300°C
(PLCC and SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-2420-2 ............................. , -55°C to 125°C
HA-2425-5 ..............................•.. OoC to 75°C
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . ±12V to ±15V

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification Is not Implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Test Conditions (Unless Otherwise Specified) VSUPPLY = ±15.0V; CH = 100OpF; DigitallnpUl: VIL = +O.BV
(Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input)
TEST
CONDITIONS

PARAMETER

TEMP.
("C)

I
I

HA·2420·2
MIN

TYP

MAX

I
I

MAX

I
I UNITS

HA·2425-5
MIN

TYP

I

INPUT CHARACTERISTICS
Input Voltage Range

Full

-

-

Offset Voltage

25

2

4

Full

3

6

25

40

200

Bias Current

±10

Full
Offset Current

±10

-

-

400

25

10

Full

50
100

Input Resistance

25

5

Common Mode Range

Full

±10

10

-

-

-

·V

3

6

mV

4

8

mV

40

200

nA

-

-

400

nA

10

50

nA

5

10

±10

100

nA

-

MQ
V

TRANSFER CHARACTERISTICS

-

Large Signal Voltage Gain

RL = 2kO, Vo = 20Vp_p

Full

25

50

Common Mode Rejection

VCM= ±10V

Full

80

90

Hold Mode Feedthrough Attenuation
(Note 2)

fiN';; 100kHz

Full

-

-76

-

25

-

2.5

-

Gain Bandwidth Product (Note 2)

-

-

25

50

74

90

kVN
dB

-

-76

dB

2.5

-

MHz

-

mA

100

-

kHz

0.15

-

Q

ns

OUTPUT CHARACTERISTICS
Output Voltage Swing

RL=2kO

Output Current

Full

±10

25

±15

-

Full Power Bandwidth (Note 2)

VO=20Vp_p

25

Output Resistance

DC

25

0.15

-

100

±10
±15

V

TRANSIENT RESPONSE

-

Rise Time (Note 2)

Vo = 200mVp_p

25

75

100

Overshoot (Note 2)

Vo = 200mVp_p

25

-

25

40

Slew Rate (Note 2)

Vo= 10Vp_p

25

3.5

5

-

VIN=OV

Full

VIN=5V

Full

Low

Full

High

Full

2.0

25

I -

-

75

100

-

25

40

%

3.5

5

-

V/p.s

-0.8

mA

20

-

-

I1A

0.8

2.3

4

DIGITAL INPUT CHARACTERISTICS
Digital Input Current

Digital Input Voltage

-

-0.8
20
0.8

-

2.0

V
V

SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time (Note 2)

ToO.1% 10V Step

5·4

2.3

4

I

-

I

115

HA-2420, HA-2425
Electrical Specifications

Test Conditions (Unless Otherwise Specified) VSUPPLY = ±15.0V; CH = 1000pF; Digital Input: VIL = +0.8V
(Sample), VIH;' +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) (Continued)
TEST
CONDITIONS

PARAMETER

MIN

TYP

MAX

-

3.2

6

10

20

-

-

-

Acquisition Time (Note 2)

To 0.01% 10V Step

25

Hold Step Error

VIN =OV

25

Hold Mode Settling Time

To±1mV

25

Aperture Time (Note 3)

-

HA1-2420

Full

HA1-2425

Full

HA3-2425, HA4P2425, HA9P2425

Full

-

25
25
25

VIN=OV

TYP

MAX

3.2

6

I1S

10

20

mV

-

B60

30

-

Effective Aperture Delay Time
Aperture Uncertainty

MIN

860

25

Drift Current (Note 2)

HA-242S-S

HA-2420-2

TEMP.
(DC)

30
5

30
30
5

5

-

1.B

10

-

-

-

-

3.5
2.5
90

-

-

5

UNITS

ns
ns
ns
ns
pA
nA

0.1

1.0

nA

-

7.5

10.0

nA

5.5

-

3.5

5.5

mA

3.5

-

2.5

3.5

mA

74

90

-

dB

POWER SUPPLY CHARACTERISTICS
Supply Current (+)

25

Supply Current (-)

25

-

Power Supply Rejection

Full

BO

NOTES:
2. Av = ±1, RL = 2kU, CL = 50pF.
3. Derived from computer Simulation only; not tested.

Functional Diagram
OFFSET
ADJUST

Q

y+

.....--A---.

......!.
+INPUT o.!
-INPUT

~

14

f9

4

3

.JtJ)

o:J:W
a::

jUg;

~
J-.....
-'- ~l
+./--.-

.J.J

7

+

......~

OUT

HA-242012425

CONTROL

!13
GND

A5
y-

11
HOLD
CAPACITOR

Test Circuits and Waveforms

L

-IN

r-

OUTPUT
'-'

INPUT

+IN

.nn..
'-'

f~CONTROL
INPUT

~

CONTROL

HOLD
CAP

GND

~d

r

~

CONTROL

OUTPUT

~~
SAMPLE

~
t
YSTEP

NOTE: Set riselfaJi times of §/H Control to approximately 20ns.

FIGURE 1. HOLD STEP ERROR AND DRIFT CURRENT

FIGURE 2. HOLD STEP ERROR TEST

5-5

a.. a..
:E:E
c:t:c:t:
tJ)

HA-2420, HA-2425

Test Circuits and Waveforms

(Continued)
SINE WAVE
INPUT

HA·242012425

Vo
OUT

SiH

CONTROL

OUTPUT

.----.L-I

.----.~

----I

--.

'---

~
SAMPLE

~1ii
: ·---t·
I

___ :

I

At

~~
NOTE: Compute hold mode feedthrough attenuation from the formula:
V
Feedthrough Attenuation = 2010g

HOLD

~U~OLD

NOTE: Measure the slope olthe output during hold, !N/At,
and compute drift current from: 10 = CH AV/At.

IN
Where VOUTHOLD = Peak·ta-Peak value of output
slnewave during the hold mode.

FIGURE 3. DRIFT CURRENT TEST

FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION

Schematic Diagram
OFFSET ADJ.

v+

045 '"

t--;-----+~~~o~

J

Q.q

~

a..7

048

R7

0s9

...

.

J"JSl
L

o-,~

C3
. 15pF

R.

Rs
OUT

r--+"--

~~r
~.,

r:

GND

o~·-::t-+-D22_TI--....T 9
0

"
"

D39

a..o

0 42

D.t3

Oaa""
"041
"\044

~ R13
·IN

+IN

5·6

v·

HA-2420, HA-2425

Application Information
HOLD STEP VOLTAGE (mV)

!Itt

5
-10

-5

OUT

t-......"""1:!V

CONTROL

+10

+5

RF

+10

--~I----+I---O+-----+_--~+_-

!Itt CONTROL
o I:;;'" NOTE: GAIN _ 1 + :F

DC INPUT VOLTAGE (V)

I
CH=0.1IlF
CH = 10,OOOpF
CH= 1000pF

FIGURE 7. NON-INVERTING CONFIGURATION

Figure 8 shows a typical unity gain Circuit, with Offset Zeroing. All of the other normal op amp feedback configurations
may be used with the HA-2420/2425. The input amplifier
may be used as a gated amplifier by utilizing Pin 11 as the
output. This amplifier has excellent drive capabilities along
with exceptionally low switch leakage.

·25

-30
-35

CONTROL

FIGURE 5. HOLD STEP VB INPUT VOLTAGE

Offset Adjustment
The offset voltage of the HA-2420 and HA-2425 may be
adjusted using a 100kQ trim pot, as shown in Figure 8. The
recommended adjustment procedure is:
Apply OV to the sample-and-hold input, and a square wave
to the 81H control.
Adjust the trim pot for OV output in the hold mode.

Gain Adjustment
The linear variation in pedestal voltage with sample-and- hold
input voltage causes a -0.06% gain error (CH 1000pF). In
some applications (O/A deglitcher, AID converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain error
at the sample-and-hold.

t---+--- OUT

=

The recommended procedure for adjusting gain error is:
1. Perform oifset adjustment.

1ookO
OFFSET TRIM (±25mV RANGE)

FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)

The method used to reduce leakage paths on the PC board
and the device package is shown in Figure 9. This guard ring
is recommended to minimize the drift during hold mode.

2. Apply the nominal input voltage that should produce a
+10Voutput.

The hold capacitor should have extremely high insulation
resistance and low dielectric absorption. Polystyrene (below
85°C), Teflon, or Parlene types lire recommended.

3. Adjust the trim pot for + 1OV output in the hold mode.
4. Apply the nominal input voltage that should produce a

For more applications, consult Harris Application Note
AN517, or the factory applications group.

-10Voutput.

CONTROL

f- . .,,--.

5. Measure the output hold voltage (V- 10NOMINAU' Adjust
the trim pot for an output hold voltage of
(V-1 ONOMINAL) + (-1 OV)

2

G N••
D1\!

·IN

HOLD •
CAPACITOR ~.

~ +IN

~

•
(!)
•

_,,+-<.7 OUTPUT

·INPUT 1

OFFSET ADJUST 3

!JH

CONTROL 1

OFFSET ADJUST 4

OUTPUT 7

11

v+

10

:'1:8~~~R

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procadures.
Copyright © Harris Corporation 1996

5-12

File Number

2857.3

HA-5320
Absolute Maximum Ratings

Thermal Information

Supply Voltage ...................................... 40V
Differential Input Voltage ............................... 24V
Digital Input Voltage. . . . . . . .. .. . . . . . . . . . . . . . . . . .. +8V, -15V
Output Current, Continuous (Note 1) . . • . . . . . . • • . . . . . .. ±20mA

Thermal Resistance (Typical, Note 3)
9JA (oC/w) 9JC (oC/w)
CERDIP Package. ........ ........ .
66
16
PDIP Package. . . . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package. . . . . . . . . . . . . . . . . . . . .
95
N/A
Maximum Junction Temperature (Ceramic Package) ......... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ... . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering 105) ......•..... 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5320-2.............................. -55°C to 125°C
HA-5320-5 ................................. OoC to 75°C
HA-5320-9 ................................ -40°C to 85°C
Supply Voltage Range (Typical, Note 2) ........•. ±13.5V to ±20V

CAUnON: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those Indicated In the operational sections of this specification is not implied.

NOTES:'
1. Internal Power Dissipation may limit Output Current below 20mA.
2. Specification based on a one time characterization. This parameter is not guaranteed.
3. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPlY = ±15.0V; CH = Internal; Digital Input: Vil = +0.8V (Sample), VIH = +2.0V (Hold),
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
TEST
CONDITIONS

HA-532D-21-9

TEMP.
("C)

MIN

TYP

Input Voltage Range

Full

±10

-

Input Resistance

25

1

5

Input Capacitance

25

-

Offset Voltage

25

0.2

PARAMETER

HA-532D-5
MAX

MIN

TVP

±10

-

1

5

I

MAX

I UNITS

INPUT CHARACTERISTICS

Offset Current

Common Mode Range
CMRR

VCM=±5V

Offset Voltage Temperature Coefficient

-

Mil

25

-

70.

200

Full

-

-

200

25

30

100

-

Full

100

±10

-

72

90

-

dB

-

5

20

IlV/oC

3 x 105

2x 106

VN

-

MHz

0.18

-

mA

600

-

1,0

-

il

125

200

IlVRMS

125

200

IlVRMS

100

-

ns

Full
Bias Current

V

5

2.0

Full

±10

-

25

80

90

-

Full

-

5

15

2 x 106

-

5

pF

0.5

-

mV

1.5

mV

100

300

nA

-

300

nA

30

300

nA

-

300

nA
V

TRANSFER CHARACTERISTICS
Gain

DC, (Note 12)

25

106

Gain Bandwidth Product
(Av= +1, Note 5)

CH = 100pF

25

-

CH = 1000pF

25

2.0
0.18

2.0

MHz

OUTPUT CHARACTERISTICS
Output Voltage

Full

±10

Output Current

25

±10

Full Power Bandwidth

Note 4

25

Output Resistance

Hold Mode

25

Total Output Noise (DC to 10MHz)

Sample

25

Hold

±10

600

-

-

1.0

-

-

125

200

25

-

125

200

25

I - I

100

±10

-

V

kHz

TRANSIENT RESPONSE
Rise Time

Note 5

I

5-13

- I

-

HA-5320
Electrical Specifications

VSUPPLY = ±15.0V; CH = Internal; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold),
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued)
TEST
CONDITIONS

PARAMETER

HA-5320-21-9

HA-5320-5

TEMP.
(DC)

MIN

TYP

MAX

TYP

MAX

UNITS

-

15

-

15

45

-

45

-

V/flS

-

0.8

V

4

Overshoot

Note 5

25

Slew Rate

Note 6

25

VIH

Full

2.0

-

VIL

Full

-

0.8

VIL=OV

25

-

4

MIN

%

DIGITAL INPUT CHARACTERISTICS
Input Voltage

Input Current

Full
VIH=+5V

Full

-

-

0.1

0.8

1.2

1.0

1.5

2.0

-

10

-

V

-

10

-

0.1

ItA
ItA
ItA

0.8

1.2

,",s

1.0

1.5

,",s

25

-

ns

-25

0

ns

0.3

-

ns

SAMPLE AND HOLD CHARACTERISTICS

Aperture Time (Note 8)

25

-

Effeclive Aperture Delay Time

25

-50

Aperture Uncertainty

25

Droop Rate

25

Acquisition Time (Note 7)

ToO.1%

25

To 0.01%

25

Full
Drift Current

Note 9

25
Full

Charge Transfer

Note 9

25

Hold Step Error

Note 9

25

Hold Mode Settling Time

To 0.01%

Full

Hold Mode Feedthrough

10Vp_p, 100kHz

Full

25
-25

0

-50

0.3

-

-

-

0.08

0.5

0.08

0.5

,",VlI-lS

17

100

1.2

100

flVlI-lS

8

50

8

50

pA

1.7

10

0.12

10

nA

0.5

1.1

0.5

1.1

pC

5

11

mV

165

350

-

2

-

5

11

165

350

ns

-

2

-

mV

11

13

mA

-11

-13

mA

-

±20

V

-

dB

POWER SUPPLY CHARACTERISTICS
Positive Supply Current

Note 10

25

-

11

13

Negative Supply Current

Note 10

25

-

-11

-13

-

Supply Voltage Range

Note 2

±20

±13.5

Power Supply Rejec1ion

V+, Note 11

Full

80

V-, Note 11

Full

65

-

±13.5

-

80

.

65

-

dB

NOTES:
4. Vo = 20Vp_p; RL = 2k.Q; CL = 50pF; unattenuated output.
5. Vo = 200mVp_p; RL = 2kO; CL = 50pF.
6. Vo = 20V Step; RL = 2kO; CL = 50pF.
7. Vo = 10V Step; RL = 2k.Q; CL = 50pF.
8. Derived from computer simulation only; not tested.
9. VIN = OV, VIH = +3.5V, tR < 20ns (VIL to VIH)'
10. Specified for a zero differential input voltage between +IN and -IN. Supply current will increase with differential input (as may occur in the
Hold mode) to approximately ±46mA at 20V.
11. Based on a 1V delta in each supply, i.e. 15V ±O.5Voc.
12. RL = 1kO, CL = 30pF.

5-14

HA-5320

Test Circuits and Waveforms
-INPUT

2

OUTPUT

8

+INPUT

~

NC

11

!IHCONTROL

CONTROL
INPUT

7

NC

HA-5320
(CH

= 1OOpF)

FIGURE 1. CHARGE TRANSFER AND DRIFT CURRENT

~ CONTROL

n

-I

I

n- ---

~l

____ ...---.

HOLD (+3.5V)
SAMPLE (OV)

-

~ CONTROL ----I

vo~

Va

...---._ _ _ _ HOLD (+3.5V)

1-.1

'---

_____ J
~
'

I

- -

I

_____ :

Vp

.l
:~ I

AVO

-

I

&t

NOTES:
15. Observe the voltage "droop·, AVolA!.
16. Measure the slope 01 the output during hold, AVoIAt, and
compute drift current: 10 = CH AVoIl!.!.

NOTES:
13. Observe the "hold step· voltage Vp.
14. Compute charge transfer: Q = VpCH'
FIGURE 2. CHARGE TRANSFER TEST

FIGURE 3. DRIFT CURRENT TEST
V-

V+

V IN

-

SAMPLE (OV)

ANALOG
MUXOR
SWITCH

VOUT

10Vp.p
100kHz
SINE WAVE

OUT
REF
COM

7

INT.
COMPo

~CO~~3~o-------~------~
TO

C~:~~\

TO

NC

SIGNAL
GND

NOTE:
Feedthrough in
V
dB = 20log OUT where:
VIN
VOUT = Vp_p, Hold Mode,
VIN=Vp_P·

NC

FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION

Application Information
The HA-5320 has the uncommitted differential inputs of an op
amp, allowing the Sample and Hold function to be combined
with many conventional op amp circuits. See the Harris Application Note AN517 for a collection of circuit ideas.

Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01 mF to 0.1 mF,
ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13.
The ideal ground connections are pin 6 (SIG. Ground)
directly to the system Signal Ground, and pin 13 (Supply
Ground) directly to the system Supply Common.
Hold Capacitor
The HA-5320 includes a 100pF MOS hold capacitor,
sufficient for most high speed applications (the Electrical
Specifications section is based on this internal capacitor).

Additional capacitance may be added between pins 7 and
11. This external hold capacitance will reduce droop rate at
the expense of acquisition time, and provide other trade-offs
as shown in the Performance Curves.

If an external hold capacitor CEXT is used, then a noise
bandwidth capacitor of value 0.1 CEXT should be connected
from pin 8 to ground. Exact value and type are not critical.
The hold capacitor CEXT should have high insulation resistance and low dielectric absorption, to minimize droop
errors. Polystyrene dielectric is a good choice for operating
temperatures up to 8SoC. Teflon® and glass dielectrics offer
good performance to 1250 C and above.
The hold capacitor terminal (pin 11) remains at virtual
ground potential. Any PC connection to this terminal should
be kept short and "guarded" by the ground plane, since
nearby signal lines or power supply voltages will introduce
errors due to drift current.
®Teflon Is a registered 1l'ademark of Dupont Corporation.

5-15

c

...len
Oa:

:::z::w

iii!;!;

...1...1

a.. a..

:E:E
etet
en

HA-5320

Typical Application

Aperture Time

Figure 5 shows the HA-5320 connected as a.unity gain noninverting amplifier - its most widely used configuration. As an
input device for a fast successive -' approximation AID
. converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the HA-5320's hold step error
is adjustable to zero 'using the Offset Adjust potentiometer,
. to deliver a 12-bit accurate output from the converter.
The application may call for an external hold capacitor CEXT
as shown. As mentioned earlier, 0.1 CEXT is then recommended at pin 8 toreduce output noise in the Hold mode.
The HA-5320 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an AID conversion are absorbed
at the StH output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.

Glossary of Terms
Acquisition TI,"e
The time required following a "sample" command, for the
output to reach its final value within ±O.1 % or :i:o.01 %. This is
the minimum sample time required to obtain a given
accuracy, and includes switch delay time, slewing time and
settling time.

Charge Transfer
The small charge transferred to the holding capacitor from
the inter-electrode capacitance of the switch when the unit is
switched to the HOLD mode. Charge transfer is directly
proportional to sample-to-hold offset pedestal error, where:
Charge Transfer (pC)

=CH (pF) x Hold Step Error (V)

The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.

Hold Step Error

Hold Step (V) = Charge Tra.(lsfer (pC)
.
Hold CapacItance (pF)
See Performance Curves.

Effective Aperture Delay Time (EADT)
The difference between the digital delay time from the Hold
command to the opening of the StH switch, and the propagation time from the analog input to the switch.
EADT may be positive, negative or zero. If zero, the s/H amplifier will output a voltage equal to VIN at the instant the Hold
command was received. For negative EADT, the output in Hold
(exclusive of· pedestal and droop errorS) will correspond to a
value of VIN that occurred befo~ the Hold command.

Aperture Uncertainty
The range of variation.in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.

Drift Current
The net leakage current from the hold capaCitor during the
hold mode. Drift current can' be calculated' from the droop
rate using the formula:

= CH(pF) x ~~ (VIs)

10 (pA)

OFFSET
ADJUST
:!:15mV

10kn

,

Hold Step Error is the output error due to Charge Transfer (see
above). It may be calculated from the specified parameter,
Charge Transfer, using the following relationship:"

-15V +15V

HI-574A

I

VIN

~ CONTROL
H

7

I

13

> ....-+-------1

2-1--1

o ·_ _ _

INPUT

DIGITAL
OUTPUT

14

--t-+---i

CONVERT

~,

y--\,..

5

~----r---~~------------------___t ~
9

SYSTEM POWER

~=~~=~-------I ~~~~O<;'

GROUND

NOTE: Pin Numbers
Refer to DIP

Package

Only.

FIGURE 5. TYPICAL HA-5320 CONNECTIONS; NONINVERTING UNITY GAIN MODE

5-16

HA-5320

Typical Performance Curves
CH = lOOpF, INTERNAL

10~----------r---~~----+-~--------~

_ _ ACQUISITION TIME FOR
51-"~---------::I""'------' 10V STEP TO +0.01% (I's)

I

1.0 ~--------''''''''!------::;

...... t

1000

i

0.5 ~-"'~------t-=':---------r-----------~

100

Ii:
iE

.!?

~

10

0.1 ~----------'l"'oo~------..300r-----------~
~

....

••--------i

0.05 ~----------t--7~'~----+-"""~

SAMPLE·TO·HOLD OFFSET
(HOLD STEP) ERROR, (mV)
0.01 '--__________.L...__________..L..__________..J
100

1000

10K

o

lOOK

~.

~

.~

o

·25

25
50
75
TEMPERATURE (oC)

CH VALUE (pF)

100

125

FIGURE 7. DRIFT CURRENT va TEMPERATURE

FIGURE 6. TYPICAL SAMPLE AND HOLD PERFORMANCE AS
A FUNCTION OF HOLD CAPACITOR

120

." 't'

./

",

~

1.00

'"

"""

'" "-'" "-"-

80

0

iii'
:!!.
z 60

"

~

r--

40

-~
GAIN
(CH = lloopF)

r-- I

20

o

o

I

I

I

10

100

U;

45

I\.

"-

PHASE

~

III
III
II:

-

"SIII

90

I .........

,",CH s 100pF)~
GAIN
135

"- """- "-

lK
10K lOOK
FREQUENCY (Hz)

"

1M

,

C

...Jen

III

Oa:

:l

J:W

:r
Do

-u:
W-

...J...J

a.. a..

180

::E::E
C(C(
en

10M

FIGURE 8. OPEN LOOP GAIN AND PHASE RESPONSE

2.0

>"
oS
~

!j

TA = 25°C
1.0

g

CH = loopF

-6

-4

0.1

CH = 1000pF

0.01

CH =0.01J1f

·2

2

4

1.0

Do

III
Itil

c

..J

·8

1.5

III

HOLD STEP VOLTAGE (mV)

·10

...------------.-------r------.------,

6

0
:r

8

0.5

0.0

10

2

DC INPUT (V)

FIGURE 9A. HOLD STEP VB INPUT VOLTAGE

3
4
LOGIC LEVEL HIGH (V)

5

FIGURE 98. HOLD STEP VB LOGIC (VIH) VOLTAGE

FIGURE 9. TYPICAL SAMPLE·TO·HOLD OFFSET (HOLD STEP) ERROR

5·17

HA-5320
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

92 mils x 152 mils x 1'9 mils

Type: Nitride (SisN4) over Silox (Si02, 5% Phos)
Silox Thickness: 12kA±2kA
Nitride Thickness: 3.5kA ±1.5kA

METALLIZATION:
Type: AI, 1% Cu
Thickness: 16kA ±2kA

TRANSISTOR COUNT:
184
SUBSTRATE POTENTIAL:

vMetallization Mask Layout
HA-5320
SUPPLYGND
(13)

v+

CeXT

(9)

(11)

IIH CTRL (14)
-fNPUT(1)

(8) fNT BW

(7) OUTPUT

+fNPUT(2)

(6)SfGGND

(3)

(4)

VIO ADJ

VIO ADJ

5-18

(5)
V-

HA-5330
650ns Precision
Sample and Hold Amplifier

November 1996

Features

Description

• Very Fast Acquisition •••. 500ns (0.1%) 650ns (0.01%)

The HA-5330 is a very fast sample and hold amplifier designed
primarily for use with high speed AID converters. It utilizes the
Harris Dielectric Isolation process to achieve a 650ns acquisition
time to 12-bit accuracy and a droop rate of 0.01 ~V/~. The circuit
consists of an input transconductance amplifier capable of producing large amounts of charging current, a low leakage analog
switch, and an integrating output stage which includes a 90pF
hold capacitor.

• Low Droop Rate •..•.••••..•...•.....•.• 0.01~VI~s
• Very Low Offset ••.••......•..••...•.•..••. 0.2mV
• High Slew Rate ........................... 90Vl~s
• Wide Supply Range.................... ±10V to ±20V
• Internal Hold Capacitor
• Fully Differential Input
• TTLJCMOS Compatible

Applications
• Precision Data Acquisition Systems

The analog switch operates into a virtual ground, so charge injection on the hold capacitor is constant and independent of VIN'
Charge injection is held to a low value by compensation circuits
and, if necessary, the resulting O.SmV hold step error can be
adjusted to zero via the Offset Adjust terminals. Compensation is
also used to minimize leakage currents which cause voltage
droop in the Hold mode.
The HA-5330 will operate at reduced supply voltages (to ±10V)
with a reduced signal range. The MIL-STD-883 data sheet for
this device is available on request.

• D/A Converter Deglitching
• Auto-Zero Circuits
• Peak Detectors

Ordering Information

C

..Jcn

TEMP.
RANGE (oC)

PART NUMBER

Pinout

PKG.
NO.

PACKAGE

HA1·5330-2

·55 to 125

14LdCERDIP

F14.3

HAl-5330·4

-25 to 85

14LdCERDIP

F14.3

HAl-5330·5

Ot075

14LdCERDIP

F14.3

HA3·5330-5

Ot075

14Ld PDIP

E14.3

Functional Diagram
HA-5330
(PDIP, CERDIP)
TOP VIEW

OFFSET
ADJUST

y+

r--A--.
3

10

4

90pF

HA·5330

OFFSET ADJ. 3

2 SIGNALGND

OFFSET ADJ. 4

11 SUPPLY GND

-IN

7

+IN

SiH

OUT

8

CONTROL
OUTPUT 7

8 IiH CONTROL

5
SUPPLY
GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

5-19

y-

12
SIGNAL
GND

File Number

2858.2

O~

:t:W

-u:::
W-

..J..J
Il.Il.

::E::E
~~

en

HA-5330
Absolute Maximum Ratings

Thermal Information

Voltage between V+ and SUPPLY/SIG GND ...•.•......•• +20V
Voltage between V- and SUPPLY/SIG GND .............•.. -20V
Voltage between SUPPLY GND and SIG GND . . . . . . . . . .. ±2.0V
Voltage between 81H Control and SUPPLY/SIG GND .... +8V, -6V
Differential Input Voltage............................•.• 24V
Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . .. ±17mA

Thermal Resistance (Typical, Note 3)
0JA (oCIW) 0JC ~CIW)
CERDIP Package................
66
16
PDIP Package.. . . .. .. .. . . . . . . . . .
90
N/A
Maximum Junction Temperature (Ceramic Package, Note 2) .•. 175°C
Maximum Junction Temperature (Plastic Package) .....••. 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ..•.......•.. 300°C

Operating Conditions
Temperature Range
HA;5330-2. . . . . . . . .. . . . . . . . . . . . . . . . .. • .. -55°C to 125°C
HA-5330-4. . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. -25°C to 85°C
HA-5330-5. . . . . . . . . . . . • . • . . • • . . . . . . . . . • . . .. OoC to 75°C
Supply Voltage Range (Typical) . . . . . . . . . . . . • . . .. ±10V to ±20V
CAunON: Stresses above those listed In "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only tating and opetation
of the device at these or any other conditions above those Indicated In the opetatlonal sections of this specification is not implied.

NOTES:
1. Internal Power Dissipation may limit Output Current below ±17mA.
2. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175°C for the ceramic
package, and below 150°C for the plastic package.
3. 0JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY = ±15V; 81H Control VIL = +0.8V (Sample): VIH = +2.0V (Hold); SIG GND = SUPPLY GND,
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
HA-533D-2, -4

TEMP.
~C)

MIN

Input Voltage Range

Full

±10

Input Resistance (Note 4)

25

5

15

Input CapaCitance

25

-

3

Offset Voltage

25

PARAMETER

TEST
CONDITIONS

TYP

HA-5330-5
TYP

'MAX

MAX

MIN

UNITS

-

±10

-

-

V

5

15

-

MO

INPUT CHARACTERISTICS

Full
Offset Voltage Temperature Coefficient

Full

Bias Current

25
Full

Offset Current

-

-

25
Full

Common Mode Range

Full
VCM=±10V

Full

Gain

DC

Full

Gain Bandwidth Product

Note 12

25

CMRR

±10
86

-

0.2

-

3

-

pF

0.2

-

mV

-

2.0

1

10

-

±20

-

-

-

±500

20

500

-

-

±10

-

86

100

100

-

1.5

mV

1

10

flVJDC

±20

-

nA

-

-

±300

nA

-

20

-

nA

300

nA

-

V
dB

TRANSFER CHARACTERISTICS
2 x 106 2x 107
4.5

-

2 x 106 2x 107

-

4.5

-

VN

-

MHz

OUTPUT CHARACTERISTICS
Output Voltage

Full

±10

Output CUrrent

Full

±10

25

-

Full Power Bandwidth (Note 6)
Output Resistance

Hold Mode
Sample Mode

25
25

5-20

-

1.4

-

0.2
10-5

0.001

±10

-

-

±10

-

-

V

MHz

0.2

-

10-5

0.001

0

1.4

mA

0

HA-5330
Electrical Specifications

VSUPPLY = ±15V; S/H Control VIL = +0.8V (Sample): VIH = +2.0V (Hold); SIG GND = SUPPLY GND,
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued)
TEST
CONDITIONS

PARAMETER
Total Output Noise, DC to 4MHz

fC)

MIN

25

-

Sample Mode
Hold Mode

HA-533D-2, -4

TEMP.

HA-533D-5

TYP

MAX

MIN

TYP

230

-

-

230

190

-

MAX

UNITS
I1V RMS

-

I1V RMS

70

-

ns

10

-

V//lS

190

TRANSIENT RESPONSE
Rise Time

Note 5

25

-

70

Overshoot

Note 5

25

-

10

-

Slew Rate

Note 7

25

-

90

-

-

90

VIH

Full

2.0

2.0

-

Full

-

-

VIL

0.8

VIL=OV

Full

10

40

VIH=5V

Full

10

40

%

DIGITAL INPUT CHARACTERISTICS
Input Voltage

Input Current

-

-

V
0.8

V

10

40

10

40

J1A
J1A

500

-

ns

-

700

ns

650

-

ns

SAMPLElHOLD CHARACTERISTICS
Acquisition Time

ToO.l%,Note8

25
Full

To 0.01%, Note 8

25
Full

-

500

-

-

700

650
900

Aperture Time (Note 4)

25

Effective Aperture Oelay Time

25

-SO

-25

0

Aperture Uncertainty

25

-

0.1

-

Droop Rate (Note 9)

Hold Step Error

20

Full

-

25

0.5

Hold Mode Settling Time

To 0.01%

25

Hold Mode Feedthrough

20Vp_p, 100kHz

Full

-

900

ns

20

-

ns

-50

-25

0

ns

::t:w

-

0.1

ns

iii!!;

0.01

0.01

25

Note 10

-

-

100

100

200

-88

-

-

-

11V1/lS

-

10

I1V//lS

0.5

-

mV

100

200

-88

ns
dB

POWER SUPPLY CHARACTERISTICS
Positive Supply Current

Full

18

22

Negative Supply Current

Full

-

19

23

Full

86

100

Power Supply Rejection

Note 11

18

24

mA

-

19

25

mA

86

100

dB

NOTES:
4. Derived from computer simulation only; not tested.
5. VI = 200mV Step; RL = 2kll; CL = 50pF.
6. Full power bandwidth based on slew rate measurement using: FPBW = :Ie; Rate . Distortion of wave shape occurs beyond 100kHz
due to slew rate enhancement circuitry.
It PEAK
7. Vo = 20V Step; RL = 2kll; CL

=50pF.

8. Vo = 10V Step; RL = 2kll; CL = 50pF.
9. This parameter Is measured at ambient temperature extremes in a high speed test environment. Consequently, steady state heating
effects from intemal power dissipation are not included.
10. VIN

=OV; VIH =+3.5V; tR =22ns (VIL to VIH)' See graph.

11. Based on a 3V delta in each supply, i.e. 15V ±1.5VoC'
12. VOUT

=200mVp_p, RL =2kll, CL =50pF.

5-21

o

...Jen

Oa:

...J...J
Q,Q,

etet
====

en

HA-5330

Application Information

Output Stage

The HA-5330 has the uncommitted differential inputs of an
op amp, allowing the Sample/Hold function to be combined
with many conventional op amp circuit ideas. See the Harris
Application Note AN517 for a collection of circuit ideas.

The HA-5330 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an AID conversion are absorbed
at the ~/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output Is not
designed to tolerate a short of indefinite duration.

Layout
A printed circuit -board with ground plane is recommended
for best performance. Bypass capacitors (0.01 J.lF to 0.1 J.lF,
ceramic) should be provided from each power supply
terminal to the Supply GND Terminal on pin 11.

Typical Applications
The HA-5330 is configured as a unity gain noninverting
amplifier by simply connecting the output (pin 7) to the
inverting input (pin 14). As an input device for a fast successive - approximation AID converter, it offers an extremely
high throughput rate. Also, the HA-5330's pedestal error is
adjustable to zero by using an Offset Adjust potentiometer
(10K to SOK) center tapped to V-.

Glossary of Terms
Acquisition Time
The time required following a "sample" command, for the
output to reach its final value within ±O.1 % or ±O.01 %. This is
the minimum sample time required to obtain a given
accuracy, and includes switch delay time, slewing time and
settling time.
Aperture Time
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is that interval
between the conditions of 10% open and 90% open.
Hold Step Error
Hold step error is the output shift due to charge transfer from
the sample to the hold mode. It is also referred to as "offset
step" or "pedestal error".

FIGURE 1. HA-5330 OFFSET ADJUST

The ideal ground connections are pin 11 (Supply Ground)
directly to the system Supply Common, and pin 12 (Signal
Ground) directly to the system Signal Ground (Analog
Ground).
Hold Capacitor
The HA-5330 includes a '90pF MOS hold capacitor, sufficient
for most high speed applications (the Electrical Specifications section is based on the internal capacitor).

~
rr:

i

3.0
2.0
1.0
0.0

m -1.0

~

\

1\

\

"-.;..0

-'

-2.0

40

20

60

60

100

RISE TIME (ns) ov TO 3.5V

FIGURE 3. HOLD STEP ERROR V8 !IH CONTROL RISE TIME
MAGNrrUDE

Effective Aperture Delay Time (EADn

40

_

!

f- PHASE

1&1

~

0

~

~

The difference between the digital delay time from the Hold
command to the opening of the S!H switch, and the propagation time from the analog input to the switch.

.........

20

r""'-

-20

~f~~PLlIE~\
11111111 ~

±~JJ l~~PLI~~J

-40
1K

EADT may be -positive, negative or zero. If zero, tile ~/H
amplifier will output a voltage equal to VIN at the instant the
Hold command was received. For negative EADT, the output
in Hold (exclusive of pedestal and droop errors) will
correspond to a value of VIN that occurred before the Hold
command.

i'"

10K

111111111
II
100K
1M
FREQUENCY (Hz)

FIGURE 2. MAGNITUDE AND PHASE RESPONSE
(CLOSED LOOP GAIN = 100)

180
10M

Aperture Uncertainty
The range of variation In Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay
Uncertainty, Aperture Time Jitter, etc.) sets a limit on the
accuracy with which a waveform can be reconstructed from
sample data.

5-22

HA-5330
Die Characteristics
PASSIVATION:

DIE DIMENSIONS:
99 mils x 166 mils x 19 mils
251 O~m x 421 O~m x 483~m

Type: Nitride (Si3N4) over Silox (Si02, 5% Phos.)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±1.5kA

METALLIZATION:
SUBSTRATE POTENTIAL (Powered Up):

Type: AI, 1% Cu
Thickness: 16kA ±2kA

Signal GND
TRANSISTOR COUNT:

205
PROCESS:
Bipolar Dielectric Isolation

Metallization Mask Layout
HA-5330

c

....len
SIGNALGND

o~w
a::

SUPPLYGND

iii!!;

v+

:E:E

OFFSETADJ

OFFSET ADJ

v-

SlHCONTROL

OUTPUT

5-23

....1....1

a.. a..

«
en

HA-5340
700ns, Low Distortion, Precision
Sample and Hold Amplifier

November 1996

Features

Description

• Fast Acquisition Time (0.01%) •.••.•••••••••• 700ns

The HA-5340 combines the advantages of two sample/ hold
architectures to create a new generation of monolithic
sampleihold. High amplitude, high frequency signals can be
sampled with very low distortion being introduced. The
combination of exceptionally fast acquisition time and
specified/characterized hold mode distortion is an industry
first. Additionally, the AC performance is only minimally
affected by additional hold capacitance.

• Fast Hold Mode Settling Time (0.01 %) •••••••••• 200n
• Low Distortion (Hold Mode) •••.•••••••.•••. -72dBc
• (VIN

=200kHz, fs =450kHz, 5Vp_p)

• Bandwidth Minimally Affected By External CH
• Fully Differential Analog Inputs
• Built-In 135pF Hold Capacitor
• Pin Compatible with HA-5320

Applications
• High Bandwidth Precision Data Acquisition Systems
• Inertial Navigation and Guidance Systems
• Ultrasonics
• SONAR
• RADAR

To achieve this level of performance, the benefits of an
integrating output stage have been combined with the advantages of a buffered hold capacitor. To the user this translates
to a front-end stage that has high bandwidth due to charging
only a small capacitive load and an output stage with constant
pedestal error which can be nulled out using the offset adjust
pins. Since the performance penalty for additional hold capacitance is low, the designer can further minimize pedestal error
and droop rate without sacrificing speed.
Low distortion, fast acquisition, and low droop rate are the
result, making the HA-5340 the obvious choice for high
speed, high accuracy sampling systems.

Pinouts

For a Military temperature range version request the
HA-5340/883 data sheet.

HA-5340
(PDIP, CERDIP)
TOP VIEW

Ordering Information
4

SiH CONTROL

3 SUPPLYGND
OFFSET ADJ. 3
OFFSET ADJ. 4

PART NUMBER

TEMP.
RANGEfc)

HAI-5340-5
HAI-5340-9

Ot075
-401085

HA3-5340-5
HA3-5340-9

01075
-401085

HA9P5340-5

010 75

PACKAGE
14 LdCERDIP
14 LdCERDIP
14 Ld PDIP

PKG.
NO.
F14.3
F14.3

14 Ld PDIP

E14.3
E14.3

16 Ld SOIC

M16.3

Functional Diagram

OUTPUT 7

CHOLD EXTERNAL
(OPTIONAL)

ADJUST OFFSET
,......A--,.

HA-5340
(SOIC)
TOP VIEW

3

OFFSET ADJ. 3

-IN

OFFSET ADJ. 4

+IN
12 EXTERNAL
HOLD CAP•.

.. --11--·

4

7

2

OUT

SiH 14

CONTROL

13

SIG.GND 7
v+

v-

SUPPLY SIGNAL GND
GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporation 1996

5-24

6

File Number

2859.2

HA-5340
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 36V
Differential Input Voltage................•...•.......... 24V
Digital Input Voltage ..........••................... +8V, -6V
Output Current. Continuous. . . . . . . . . . . . . . . . . . . . . . . .. ±20mA

Thermal Resistance (Typical, Note 2)
9JA (oCIW) 9JC fc/W)
CERDIP Package................
66
16
pDlp Package. . .. . . .. . . . .. . . . . . .
90
N/A
SOIC Package. . .. .. .. .. . .. . . . . . .
95
N/A
Maximum Junction Temperature (Ceramic Package, Note 1) ... 175°C
Maximum Junction Temperature (Plastic Package) .....••. 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) .......•..... 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
HA-5340-9 ............................... -40°C to 85°C
HA-5340-5 ................................. OoC to 75°C
Supply Voltage Range (Typical) ................. ±12V to ±18V

CAUTION: Stresses above those listed In "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specificaliorlls not implied.

NOTES:
1. Maximum power dissipation must be designed to maintain the junction temperature below 175°C for the ceramic package, and below
150°C for the plastic packages.
2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = -HI.8V (Sample), VIH = +2.0V (Hold). Non-Inverting
Unity Gain Configuration (Output tied to -Input),

~ = 2k.Q, ~ =

6OpF, Unless Oiherwise Specified

HA-5340-9, HA-5340-5
PARAMETER

TEST CONDITIONS

TEMP. (DC)

MIN

TYP

MAX

UNITS

-

+10

V

-

Mil

INPUT CHARACTERISTICS
Input Voltage Range

Full

-10

Input Resistance (Note 3)

25

-

1

Input Capacitance

25

Input Offset Voltage

25

-

Offset Voltage Temperature Coefficient

Full

-

30

jJ.vtoc

Bias Current

25

±70

-

nA

...J...J

nA

:n!E
CJ)

Full

Offset Current

CMRR

±10V, Note 4

pF
mV

Q

3.0

mV

Oa:
::J:W

Full

-

-

±350

25

-

±50

-

nA
nA

-10

-

±350

Full

+10

V

25

-

83

dB

Full

72

-

-

110

140

Full
Common Mode Range

3
1.5

dB

TRANSFER CHARACTERISTICS
Gain

DC

25

Gain Bandwidth Product

CH Extemal = OpF

Full

CH Extemal = 100pF

Full

CH Extemal = 1000pF

Full

-

6.7

-

MHz
ns

10
9.6

dB

-

MHz
MHz

TRANSIENT RESPONSE
Rise Time

200mVStep

25

30

200mVStep

25

-

20

Overshoot

35

50

%

Slew Rate

10VStep

25

40

60

-

V/jJ.S

-

-

V

0.8

V

DIGITAL INPUT CHARACTERISTICS
Input Voltage
Input Current

VIH

Full

2.0

VIL

Full

-

VIL=OV

Full

VIH=5V

Full

-

5-25

7

40

jJ.A

4

40

jJ.A

...JCJ)

w!i;;

D.D.



.§.

9

II:

10

0

8

II:
II:
W

7
6
5
4
3
2
1

o

til,

> 1900

FIGURE 8. DROOP RATE VB HOLD CAPACITANCE

>

• .'~,

...

FIGURE 7. TACQ VB ADDITIONAL CH

EXTERNAL HOLD CAPACITANCE (pF)

II:

~

iii ;/

2300

1

.§.

L

,,,,,

FIGURE 6. TACQ POSOTO +10 STEP

30
28
28
24
"iii' 22
~ 20
~ 18
w 16
Ii
II: 14
12
0
10

..

r: "

...w

VIH =3V

Iii
I

...c0

I

0

:s::

VIH=4V

L I
5

10

15

-10~--'

-55

20

TRISE (n8)

__

-35

~

__

-15

~

0

__- L__- - '____
25

50

~

75

__

~

____'"

100

TEMPERATURE (DC)
FIGURE 11. HOLD STEP ERROR VB TEMPERATURE

FIGURE 10. HOLD STEP ERROR VB TRISE

5-29

125

I/)

HA-5340
Typical Performance Curves

TA = 25°C, Vs = ±15V. Unless Otherwise Specified

20~--~~-===~~---.----.----r----,

14

>'
g

12

II:

10

...
...0

Ii

Ii!II:
III

(Continued)

VIH = 4V, CH = INTERNAL
IR = 5n9, 10n9, 20n8

TRISE= 5ns
TA = 25°C

,

III

Ii;
Q

6

:z::

4

I"..

2

"

VIH=4V

I

·10~~~~--~--~----~--~----~--~

400
60a
200
800
EXTERNAL HOLD CAPACITANCE (pF)

·55

1000

11111

40

i"i"o

:!!.

0

25

50

75

100

125

FIGURE 13. HOLD STEP ERROR VB TEMPERATURE

111111

180

MAGNITUDE

iii'

!!l

E20
z
~

·15

.TEMPERATURE fC)

FIGURE 12. HOLD STEP ERROR VB HOLD CAPACITANCE

iii'

·35

""

,

o
PHASE

...... ~

III
III

90

iii'

II:

CI

:!!.

III

e.
...
CI

III

z

~

III

0

zor(

!Ii::Ii

III

·90

Av = +100, ±15V AND
±12V SUPPLIES (NOTE)

\.

~...

40

20

0

·180

111111111 111111111
lK

lOOK

10K

1M

10M

NOTE: ±15V and ±12V supplies trace the same line within
the width of the line, therefore only one line is shown.

lK

10K

lOOK

1M

10M

FIGURE 15. CLOSED LOOP PHASE/GAIN

FIGURE 14. CLOSED LOOP PHASE/GAIN

·20

·20
'SAMPLE'" 450kHz
VOUT= 5Vp..p

HA·5320
SAMPLE AND
HOLD MODES

-40

-40

r-- -

IHA'5320
SAMPLE AND HOLD MODES

I

'il'
CD

'il'
CD

:!!.

Q

i!:

:!!. -60

Q

i!:

·60

·80

-80

·100

lOOK

200K
300K
FREQUENCY (Hz)

400K

r-- -

-----

5

500K

FIGURE 16. THO VB FREQUENCY

HA.53401
HOLD MODE '-".

HA-534O
SAMPLE MODE

10
VOUTp.p at 200kHz, 'SAMPLE;: 450kHz
FIGURE 17. THO VB VOUT

5·30

- r20

HA-5340

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

84mils x 139mils x 19mils

Type: Nitride (SiaN4) over Silox (Si02, 5% Phos)
Silox Thickness: 12kA ± 2.0kA
Nitride Thickness: 3.5kA ± 1.5kA

METALLIZATION:
Type: AI, 1% Cu
Thickness: 16kA ± 2kA

SUBSTRATE POTENTIAL (Powered Up):

vTRANSISTOR COUNT:
196

Metallization Mask Layout
HA-5340

.......
c(c(

ZCJ

159
\<0

w:c

SUPPLY (13)
GND

C

5JH(14)

...II/)

CONTROL

Oa:
J:W

(9) +VSUPPLY

-IN (1)

w!!;

...1...1

(7) OUTPUT

11.11.

(7) OUTPUT

I/)

+IN(2)
(6) SIG GND

E
..,

~

c

..,c

Iii

Iii

c(

If
....
0

c(

If
....
0

5-31

ctct
====

HA5351
64ns Sample and Hold Amplifier

November 1996

Features

Description

• Fast Acquisition to 0.01% •••••••..•••••• 70ns (Max)

The HA5351 is a fast acquisition, wide bandwidth sample
and hold amplifier, built with the Harris HBC·10 BiCMOS
process. This sample and hold amplifier offers a combination
of desirable features; fast acquisition time (70ns to 0.01 %
maximum), excellent DC precision and extremely low power
dissipation, making it ideal for use in systems that sample
multiple signals and require low power. For systems with
multiple channels, consider the Dual HA5352 sample and
hold amplifier.

• Low Offset Error .•••••.••••••••••••••• ±2mY (Max)
• Low Pedestal Error ••••••.•.•••••.... HOrnY (Max)
• Low Droop Rate ••..•••••..•••..••.•• 211VlIlS (Max)
• Wide Unity Gain Bandwidth •••.••....•••••. 40MHz
• Low Power Dissipation • • • • • • • • • • • • •• 220mW (Max)
• Total Harmonic Distortion (Hold Mode) ••••••• -72dBc
(YIN 5Yp_p at 1 MHz)

=

• Synchronous Sampling

The HA5351 is in an open loop configuration with fully differential inputs providing flexibility for user defined feedback. In
unity gain the HA5351 is completely self-contained and
requires no external components. The on-chip 15pF hold
capacitor is completely isolated to minimizing droop rate and
reduce sensitivity to pedestal error. The HA5351 is available
in 8 lead PDIP and SOIC packages for minimizing board
space and ease of layout.

• Wide Bandwidth AID Conversion

Ordering Information

• Fully Differential Inputs
• On Chip Hold Capacitor

Applications

• Deglltchlng
PART NUMBER

• Peak Detection
• High Speed DC ~estore

Pinout

TEMP.
RANGECOC)

PKG.
NO.

PACKAGE

HA5351IP

-401085

8 Ld PDIP

E8.3

HA5351IB

-40 to 85

8 LdSOIC

M8.15

Functional Diagram
HA5351
(PDIP, SOIC)
TOP VIEW)

v+

v·

15pF

-IN

_.;;.8-f-l

+IN

--+-t

5 !/H

'_..--U~+t-o

CTRL

OUT

Ml __
5--1-t
HA5351

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures,
Copyright © Harris Corporation 1996

5-32

File Number

3690.5

HA5351
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals ................... +11V
Differential Input Voltage ................................ 6V
Voltage Between Sample and Hold Control and Ground ..... +5.5V
Output Current, Continuous. . . . . . . . . • . . • . . . . . . . • . . .. ±37mA

Thermal Resistance (Typical, Note 1)

Operating Conditions
Temperature Range .......................... -40°C to 85°C

9JA (oCIW)

PDIP Package .....................•.... '"
120
SOIC Package.............................
160
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............. 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = +O.OV (Sample), VIH = 4.0V
(Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF,
Unless Otherwise Specified
HA5351I

TEMP.
(oC)

MIN

Input Voltage Range

Full

Input Resistance (Note 2)

25

PARAMETER

TEST CONDITIONS

TYP

MAX

UNITS

-2.5

-

+2.5

V

100

500

-

kO

INPUT CHARACTERISTICS

Input Capacitance

25

-

5

pF

Input Offset Voltage

25

-2

2

mV

Full

-3.0

Offset Voltage Temperature Coefficient

Full

Bias Current

Full

-

Offset Current

Full

-1.5

Common Mode Range

Full

-2.5

-

Full

60

80

25

95

108

dB

Full

85
40

MHz

Common Mode Rejection

±2.5V, Note 3

-

3.0

mV

15

-

Jlvf'c

o....ItJ)

2.5

5

:I:W

+1.5

IlA
IlA

+2.5

V

-

dB

VOUT=±2·5V

Unity Gain -3dB Bandwidth

25

dB

TRANSIENT RESPONSE
Rise Time

200mVStep

25

B.5

-

Overshoot

200mVStep

25

0

-

30

%

Slew Rate

5VStep

Full

BB

105

-

V/Jls

25,B5

2.1

V

2.4

VIL

Full

0

VIL=OV

Full

-1.0

VIH=5V

Full

-1.0

-

5.0

-40

RL=5100

Full

-3.0

-

RL= 1000

25,B5

20

25

-40

15

-

ns

DIGITAL INPUT CHARACTERISTICS
Input Voltage

Input Current

VIH

5.0

V

O.B

V

1.0

IlA
IlA

1.0

OUTPUT CHARACTERISTICS
Output Voltage
Output Current

5-33

+3.0

-

-u:::
W-

....1....1

a.. a..

:?::?:
c(c(

tJ)

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

00::

V
mA
mA

HA5351
Electrical Specifications

=

=

=

=

Test Conditions: VSUPPLY ±5V; CH Internal 15pF, Digital Input: VIL +O.OV (Sample), VIH
(Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF,
Unless Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

TEMP.
(oC)

=+1, -3dB

Full

HA5351I
MIN

Output Resistance

Hold Mode

25

Total Output Noise
(DC to 10MHz)

Sample Mode

25

-

Hold Mode

25

-

VIN

=4.5Vp_p, fiN =100kHz
=5Vp_p, fiN =1MHz
VIN = 1Vp_p, fiN = 10MHz
VIN =4.5Vp_p, fiN =100kHz

25

VIN

25

Full Power Bandwidth

5Vp_p, Av

=4.0V

TYP

MAX

UNITS

13

-

MHz

n

0.02
325

-

I1V RMS

325

-

I1V RMS

-80

-76

dBc

-74

-69

dBc

-57

-52

dBc

DISTORTION CHARACTERISTICS
SAMPLE MODE
Total Harmonic Distortion

Signal to Noise Ratio
(RMS Signal to RMS Noise)

25

-

25

-

73

-

dB

25

-

-78

-74

dBc

-72

-67

dBc

HOLD MODE (50% Duty Cycle SIH)
Total Harmonic Distortion

=

VIN 4.5Vp_p, fiN
fS= 100kHz

=

=1MHz,

25

=

=10MHz,

25

-

-51

-47

dBc

25

-

70

-

dB

53

-

ns

64

70

ns

90

100

ns

VIN 5Vp_p, fiN
fS= 1MHz
VIN 1Vp_p, fiN
fS= 1MHz
Signal to Noise Ratio
(RMS Signal to RMS Noise)

=100kHz,

=

VIN 4.5Vp_p, fiN
fs= 100kHz

=100kHz,

SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time

OV to 2.0V Step to ±1mV

25

OV to 2.0V Step to 0.01%
(±2OOI1V)

25

-

-2.5V to +2.5V Step to 0.01 %
(±500I1V)

25

-

Droop Rate

0.3

25

=OV, VIH =4.0V, tR =5ns

Hold Step Error

VIL

Hold Mode Settling Time

To±1mV

Hold Mode Feedthrough

5Vp_p, 500kHz, Sine

Full

-2

Full

-10

25
25

EADT (Effective Aperture Delay Time)

25

Aperture Time (Note 2)

25

Aperture Uncertainty

25

-

-

-

-

I1V/1LS

2

I1V1ILS

+10

mV

50
72
+1

ns

-

dB
ns

10

-

ns

10

20

ps

20

22

rnA

20

22

rnA

POWER SUPPLY CHARACTERISTICS
Positive Supply Current

Full

Negative Supply Current

Full

-

Full

60

PSRR

10% Delta

NOTES:
2. Derived from Computer Simulation only, not tested.
3. +CMRR is measured from OV to +2.5V, -CMRR is measured from OV to -2.5V.

5-34

74

dB

HA5351
Typical Performance Curves

2

I
I

I

§

\\.

~
o

~

5

\

I

·2

0.1

\
\

100

200
300
TIME (n.)

400

0.0

l

·0.1

500

600

400

200

TIME (n.)

FIGURE 2. SMALL SIGNAL RESPONSE

FIGURE 1. LARGE SIGNAL RESPONSE

2
60

o

........
40.163156.~~: __

"

40

-.,

iii'
:!!.

z

....

20

~

GAIN
I'-.OdB AT 21.34MHz

-30

....

o

-

r-..

1K

100M

10M

10K

FREQUENCY (Hz)

100K

1M

""10M

:I:W

·120 ~
·150 if:
·180
100M

:i:i

FREQUENCY (Hz)

FIGURE 3. UNITY GAIN FREQUENCY RESPONSE

FIGURE 4. CLOSED LOOP GAINIPHASE

2

60

o

50

Av =+1000

200mVp.p

13.241189MHz
-3dB

iii' ·2
:!!.

~

~z

\

-4

rJ

:c

!.

~

~

z

~

4 TYPICAL UNITS

'N
40

30

I1i 20

\

III

1

;S;

}

10

·8

10K

100K

1M

10M

100M

FREQUENCY (Hz)

o

±3.5

±4

/

±4.5
±5
SUPPLY VOLTAGE (V)

±5.5

FIGURE 6. -3dB BANDWIDTH vs SUPPLY VOLTAGE

FIGURE 5. 5Vp.p FULL POWER FREQUENCY RESPONSE

5·35

o..J!/)

Oa:

~

90

PHASE'/,·119.86DEG

'III
1M

ifi

-601l!

r-...

·20

-8
lOOK

o

±6

iiig;

..J..J

a.. a..

c(c(
!/)

HA5351
Typical Performance Curves

(Continued)

O$,---------~----------_r--------_,

I----------+----------+------f---i

-

140

i

/'

UNIT.1

ii!!. 130

~ 0.3 1--------#4---------==t-"""":-1hf---i
UI
!c
a:

i

+SLEWRATE
• - . -SLEW RATE

3 TYPICAL UNITS
150

0.4

---

160

3 TYPICAL UNITS

<;.

i! 120 :;.:..:- _...\
UI

110

~lTlI2i

UNIT 113

90
-50

--

:::::::

-:~

90
OL---------~----------~--------~
-50
0
50
100
TEMPERATURE ('IC)

(

--- ----'-.- ---.- .... -----

100

0.1 1--+-~=:::=:1~---~I-------l

------- ----- ....

~

S

0.2

0

100

60

TEMPERATURE ('IC)

FIGURE 7. DROOP RATE VB TEMPERATURE

FIGURE 8. SLEW RATE VB TEMPERATURE

9,----------,----------,----------,

65

4 TYPICAL UNITS

....s.

81----------r----------+-~~~~~

!!1=

4 TYPICAL UNITS
60
55

CI

z

50

E

45

UI

I!I

!Ii

40

§!

35

Q
....

4L---------~----------~----------~

o

·50

50
TEMPERATURE ('IC)

30

100

0
50
TEMPERATURE ('IC)

-50

100

FIGURE 10. HOLD MODE SETTLING va TEMPERATURE

FIGURE 9. RISE TIME VB TEMPERATURE

3
OY TO 4Y!IH CTRL

1

ffi
....

A

~ 0

~

10

~

~
15

0.01

,)

2

OUTPUT

~

V

~

~V

-1

0.00

V

~!IH

o

CONTROL

I67i5na

~

o
-2

-0.01

o

10

20

30

40

50

!IH CONTROL RISE TIME (na)

3.0E·7
TIME (na)

FIGURE 11. PEDESTAL va SIH CONTROL RISE TIME

FIGURE 12. ACQUISITION TIME (0.01%, OV TO 2V STEP)

5-36

HA5351
Typical Performance Curves

(Continued)

OUTPUT

0.02

10

E

1\

0.00

1\

!;

§

-0.02

V

-

-0.04

o

"

51.4na

I

E
....

"
5

0
II:

!E

0

"
I~

=0

20

40

60

80

TIME (na)

FIGURE 13. HOLD MODE SETTLING nME (±2001LV)

Q
....II/)

Oa:

::J:W

-u:::
W-

....1....1

a.. a..

:E:E
c:r:c:r:
I/)

5-37

HA5351
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:
Type: Sandwich Passivation
Nitride - 4kA, Undoped Si Glass (USG) - 8kA,
Total- 12kA ±2kA

2530ILm x 1760ILm x 525ILm
100 mils x 69 mils x 19 mils
METALLIZATION:

SUBSTRATE POTENTIAL:

Type: Metal 1: AISiCufTiW
Thickness: Metal 1: 6kA ±750A

v-

Type: Metal 2: AISiCu
Thickness: Metal 2: 16kA ±1.1 kA

TRANSISTOR COUNT:
156

Metallization Mask Layout
HA5351

GND

GND

GND

y+

y+

y+

S/HCONTROL
-IN

Vour

VOUT
+IN

y-

5-38

y-

y-

6
VIDEO CROSSPOINT SWITCHES

PAGE
SELECTION GUIDE .............................................................................. .

6-2

VIDEO CROSSPOINT SWITCH DATA SHEETS
HA4201

480MHz, 1 x 1 Video Crosspoint Switch with Tally Output ............................. .

6-3

HA4244

480MHz, 1 x 1 Video Crosspoint Switch with Synchronous Enable ...................... .

6-10

HA4314B

400MHz, 4 x 1 Video Crosspoint Switch ........................................... .

6-16

HA4344B

350M Hz, 4 x 1 Video Crosspoint Switch with Synchronous Controls ..................... .

6-23

HA4404B

330M Hz, 4 x 1 Video Crosspoint Switch with Tally Outputs ............................ .

6-26

HA455

130MHz, 8 x 8 Video Crosspoint Switch ........................................... .

6-33

HA456

80M Hz, Low Power, 8

x 8 Video Crosspoint Switch .................................. .

6-34

HA457

170M Hz, Av

=+2, 8 x 8 Video Crosspoint Switch .................................... .

6-35

HA4600

480MHz, Video Buffer with Output Disable ......................................... .

6-36

th

'W

th:::t:
tho

01a:03:

Oth

wIOZ

>0
a..

6-1

Selection Guide
VIDEO CROSSPOINT SWITCHES: Typical Values at 25°C. Unless Otherwise Specified

(NOTE 2)
DEVICE

FEATURES

DIF.
GAIN
(%)

DIF.
PHASE
(DEG)

0.1dB
FLAT
GAIN
(MHz)

BW
(MHz)

SUPPLY
SLEW
10MHz
VOLTAGE
RATE CROSSTALK RANGE
(dB)
(±V)
(VIliS)

SUPPLY
CURRENT
(mA)

CROSSPOINT SWITCHES
HA4600

1x 1

0.01

0.01

250

480

1700

-85
(Note 1)

4.5 - 5.5

10.5

HA4201

1 x 1 with Tally Output

0.01

0.01

250

480

1700

-85
(Note 1)

4.5 - 5.5

10.5

HA4244

1 x 1 with Latched C;ontrol
Signal

0.01

0.01

250

480

1700

-85
(Note 1)

4.5 -5.5

10.5

HA4314B

4x1

0.01

0.01

100

400

1400

-90

4.5 - 5.5

10.5

HA4404B

4 x 1 with Tally Outputs

0.01

0.01

165

330

1250

-90

4.5 - 5.5

10.5

HA4344B

4 x 1 with Latched Control
Signals

0.01

0.01

150

350

1400

-90

4.5 - 5.5

10.5

HA455

High Performance 8 x 8, Ay

0.02

0.02

TBD

130

250

-60

4.5 - 5.5

88

HA456

Low Power 8 x 8, Ay

0.04

0.20

TBD

80

170

-60

4.5 - 5.5

56

HA457

High Performance 8 x 8, Ay

0.01

0.02

TBD

170

350

-60

4.5 - 5.5

88

=+1

=+1
=+2

NOTES:
1. Off Isolation at 100MHz.
2. Bold type indicates a new product from Harris.

6-2

HA4201
480MHz, 1 x 1 Video Crosspoint
Switch with Tally Output

November 1996

Features

Description

• Low Power Dissipation ..•................ 105mW

The HA4201 is a very wide bandwidth 1 x 1 crosspoint
switch ideal for professional video switching, HDTV, computer monitor routing, and other high performance applications. The circuit features very low power dissipation
(105mW Enabled, 1mW Disabled), excellent differential gain
and phase, and very high off isolation. When disabled, the
output is switched to a high impedance state, making the
HA4201 ideal for routing matrix equipment.

• Symmetrical Slew Rates .•..•••.......... 1700Vl!!s
• 0.1dB Gain Flatness •..................... 250M Hz
• Off Isolation (1 OOMHz). . . . . . . • . . . . . • . • . . . . .. 85dB
• Differential Gain ....•.••••.••....•........ 0.01%
• Differential Phase. . . . . • . . • • . . . . . . . •. 0.01 Degrees
• High ESD Rating ......................•. >2000V
• TTL Compatible Enable Input
• Open Collector Tally Output
• Improved Replacement for GX4201

The HA4201 requires no external current source, and features fast switching and symmetric slew rates. The tally output is an open collector PNP transistor to VCC' and is
activated whenever EN = 1 to provide an indication of crosspoint selection.
For applications which don't require a Tally output, please
refer to the HA4600 data sheet.

Applications

Ordering Information

• Professional Video Switching and Routing
PART NUMBER
(BRAND)

• Video Multiplexers

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

• HDTV

HA4201CP

Oto 70

BLdPDIP

EB.3

• Computer Graphics

HA4201CB
(4201CB)

Ot070

B LdSOIC

MB.1S

en

'w
en:J:
en O

• RF Switching and Routing
• PCM Data Routing

01a:-

Pinout

oU)
wIoz
>0
11.

0:=

Truth Table
HA4201
(PDIP, SOIC)
TOP VIEW

EN

OUT

TALLY

0

HighZ

Off

1

Active

On

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

6-3

File Number

3680.3

HA4201
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ 12V
Input Voltage ..........•......................... VSUPPLY
Digital Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . .. ±25mA
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20mA

Thermal Resistance (Typical, Note 1)

9JA (lCIW)

PDIP Package....................... ......
130
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 70°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This Is a stress only rating and operation
of the device at these or any other conditions above those Indicated In the operaOonal sections of this specification is not implied.

NOTES:
1. 9JA Is measured with the component mounted on an evaluation PC board in free air.
2. If an input signal is applied before the supplies are powered up, the Input current must be limited to this maximum value.

Electrical Specifications

VSUPPLY = ±5V, RL = 101<0, VEN = 2.0V, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

TEMP.
(oC)

MIN

TYP

MAX

UNITS

DC SUPPLY CHARACTERISTICS
Full

±4.5

±5.0

±5.5

V

25, 70

-

10.5

13

rnA

VEN=2.0V

0

14.5

rnA

25, 70

100

115

itA

VEN= 0.8V

0

-

-

VEN=0.8V

100

125

itA

25, 70

±2.7

±2.8

V

0

±2.4

±2.5

Output Current

Full

15

Input Bias Current

Full

Output Offset Voltage

25

Output Offset Voltage Drift (Note 3)

Full

Supply Voltage
Supply Current (VOUT = OV)

VEN=2.0V

ANALOG DC CHARACTERISTICS
Output Voltage Swing without Clipping

VOUT = VIN ± VIC ± 20mV

20

-

30

50

ItA

-10

-

10

mV

-

25

50

ItVPC

160

ns

V

V

rnA

SWITCHING CHARACTERISTICS
Tum-On Time

25

Tum-Off Time

25

-

320

-

Full

2

-

-

ns

DIGITAL DC CHARACTERISTICS
Input Logic High Voltage

-

0.8

V

EN Input Current

VEN=Ot04V

Full

-2

-

2

itA

Tally Output High Voltage

IOH = lmA

Full

4.7

4.8

-

V

Tally Off Leakage Current

VTALLY = OV, -5V

Full

-20

-

20

itA

Insertion Loss

tVp_p

Full

-

0.04

0.05

dB

-3dB Bandwidth

Rs = 820, CL = 10pF

480

-

MHz

380

-

MHz

Input LogiC Low Voltage

Full

AC CHARACTERISTICS

Rs = 430, CL = 15pF

25

Rs = 360, CL = 21pF

25

6-4

-

370

MHz

HA4201
Electrical Specifications VSUPPLY = ±5V, RL = 10kQ, VEN = 2.0V, Unless Otherwise Specified (Continued)

PARAMETER

TEMP.
fC)

TEST CONDITIONS

±O.ldB Flat Bandwidth

MIN

TYP

MAX

UNITS

RS = 820, CL = 10pF

25

250

MHz

RS = 430, CL = 15pF

25

175

MHz

RS = 360, CL = 21pF

25

170

MHz

400

kO
pF

Input Resistance

Full

Input Capacitance

Full

1.0

Enabled Output Resistance

Full

15

n

Disabled Output Capacitance

VEN=0.8V

Full

2.0

pF

Differential Gain

4.43MHz, Note 3

25

0.01

0.02

%

Differential Phase

4.43MHz, Note 3

25

0.01

0.02

Degrees

Off Isolation

Wp_p, l00MHz, VEN = 0.8V, RL = 100

Full

85

dB

Slew Rate
(1.5Vp_p, +SRI-SR)

RS = 820, CL = 10pF

25

1750/1770

V/IlS

Rs = 430, CL = 15pF

25

1460/1360

V1lls

Rs = 360, CL = 21pF

25

1410/1360

V/',lS

Total Harmonic Distortion (Note 3)

Full

0.01

Disabled Output Resistance

Full

12

200

0.1

%
MO

NOTE:
3. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.

AC Test Circuit

Application Information
" General

v ~o
v._ rl>
rex

4000

4;:5100

HA4201

750

RS

IN_
750

T

u

V

The HA4201 is a 1 x 1 crosspoint switch that is ideal for the
matrix element in small, high input-to-output isolation switchers and routers. It also excels as an input buffer for routers
with a large number of outputs (i.e. each input must connect
to a large number of outputs) and delivers performance
superior to most video amplifiers at a fraction of the cost. As
an input buffer, the HA4201's low input capacitance and high
input resistance provide excellent video terminations when
used with an external 75n resistor. This crosspoint contains
no feedback or gain setting reSistors, so the output is a true
high impedance load when the IC is disabled (EN = 0).

r

~""~

+~-~~

HFA11 00

10kO

u

NOTE: CL = Cx + Test Fixture Capacitance.

PC Board Layout

Frequency Response
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a mustl
Attention should" be given to decoupling the power supplies.
A large value (10~F) tantalum in parallel with a small value
(0.1 ~F) chip capacitor works well in most cases.
Keep input and output traces as short as possible, because
trace inductance and capacitance can easily become the
performance limiting items.

Most applications utilizing the HA4201 require a series output resistor, RS, to tune the response for the specific load
capacitance, CL, driven. Bandwidth and slew rate degrade
as CL increases (as shown in the Electrical Specification
table), so give careful consideration to component placement to minimize trace length. As an example, -3dB bandwidth decreases to 160MHz for CL 100pF, RS
In big
matrix configurations where CL is large, better frequency
response is obtained by cascading two levels of crosspoints
in the case of multiplexed outputs (see Figure 2), or distributing the load between two drivers if CL is due to bussing and
subsequent stage input capacitance.

6-5

=

=on.

tn
'W

tn:J:
tnO

OJa:-

0:=
otn

wJoz

>0
Il.

HA4201
Control Signals
EN - The ENABLE input is a TTUCMOS compatible, active
high input. When driven low this input forces the output to a
true high impedance state and reduces the power dissipation by two orders of magnitude. The EN input has no onchip pull-up resistor, so it must be connected to a logic high
(recommend V+) if the enable function isn't utilized.
Tally - The Tally output is an open collector PNP transistor connected to V+. When EN 1, the PNP transistor is enabled and
current is delivered to the load. When the crosspoint is dis~
abled, the Tally output presents a very high impedance to the
external circuitry. Several Tally outputs may be wire OR'd
together to generate complex control signals, as shown with the
HA4404 in the application circuits below. The Tally load may be
terminated to GND or to V- as long as the continuous output
current doesn't exceed 3mA (6mA at 50% duty cycle, etc.).

=

SwitcherlRouter Applications
Figure 1 illustrates one possible implementation of a
wideband, low power, 4 x 4 switcher/router. A 4 x 4
switcher/router allows any of the four outputs to be driven by
anyone of the four inputs (e.g. each of the four inputs may
connect to a different output, or an input may connect to
multiple outputs). This application utilizes the HA4201 for the
Input buffer, the HA4404 (4 x 1 crosspoint switch) as the
switch matrix, and the HFAll12 (programmable gain buffer)

INPUT BUFFERS

as the gain of two output driver. Figure 2 details a 16 x 1
switcher (basically a 16:1 mux) which uses the HA4201 in a
cascaded stage configuration to minimize capacitive loading
at each output node, thus increasing system bandwidth.

Power Up Considerations
No signals should be applied to the analog or digital inputs
before the power supplies are activated. Latch-up may occur
if the inputs are driven at the time of power up. To prevent
latch-up, the input currents during power up must not exceed
the values listed in the Absolute Maximum Ratings.

Harris' Crosspoint Fsmlly
Harris offers a variety of 1 x 1 and 4 x 1 crosspOint switches.
In addition to the HA4201, the 1 x 1 family includes the
HA4600 which is an essentially similar device but without the
Tally output. The 4 x 1 family is comprised of the HA4314,
HA4404, and HA4344. The HA4314 is a 14 lead basic 4 xl
crosspoint. The HA4404 is a 16 lead device with Tally outputs to indicate the selected channel. The HA4344 is ~ 6
lead crosspoint with synchronized control lines (AO, A1, CS).
With synchronization, the control information for the next
channel switch can be loaded into the crosspoint without
affecting the current state. On a subsequent clock edge the
stored control state effects the desired channel switch.

SWITCH MATRIX
10kO

SOURCEO

OUT Rs
HA4201

OUTPUT SUFFERS
(HFA1112 OR HFA1115)

75'1
OUTO

FIGURE 1. 4

OUT1

x 4 SWITCHERIROUTER APPLICATION

6-6

OUT2

OUT3

HA4201
SWITCHING MATRIX

•
••
SOURCE3

ISOLATION MUX

OUTPUT BUFFER

INO

SOURCEO

INl
IN2
-_--tIN3

TO

t-:.:---.-......-.,

•
T3r·:--.
RS

10kn

RS
SOURCE4

•••
SOURCE7

INO
INl
IN2
_

....--IIN3

••

T3~·::'--..1
HFAll12 OR HFAll15
750

>-JVt.IIr--oO OUT

HA4404
SOURCE8

INO

••
•

INl
IN2

SOURCEll -_--IIN3

TO

1-::..--__.......
lOkn

SOURCE12

-ll;N;o==;~

o-....

•••

TO t-:R~S::.--.

INl
IN2

SOURCE15 -

••

T3~.~-..1

....--IIN3

m

'W

mJ:

mo
01a:0;:

HA4404

FIGURE 2. 16 x 1 SWITCHER APPLICATION

Om
wI-

cz

Typical Performance Curves

0.75

E

,

..
1-

1.0

0.5

1.25

1.20

!:l

~

1.15

~

1.10

0.25

z

0

!

1.0

~

0.95

~

0.90

~ 1.05

5

~ ·D.25

o

~

.e.

w

i

..0.5
..0.75

>0
Q.

VSUPPLY =±5V. TA =2SoC. RL =101<0, Unless Otherwise Specified

~

J

\

'(

I

0.85
0.80

V-

0.75

·1.0

1

TIME (5nsIDIY.)

10

100

FREQUENCY (MHz)

FIGURE 3. LARGE SIGNAL PULSE RESPONSE

FIGURE 4. INPUT CAPACITANCE VB FREQUENCY

6-7

500

HA4201
Typical Performance Curves

0.4

9

0.3

6

z

~

=±5V, TA =25°C, RL = 10kn, Unless Otherwise Specified

12

0.2

RS=820 RS .. 430
CL s10PFl\'
15 F
L=

m3
~

VSUPPLY

III
III

0
-3

m 0.1

1/

~

a;

:""0 hJi\

-6

RS = 360/
CL=21p

·9

III

I

III
III

·12

10
100
FREQUENCY (MHz)

0

5 -90

~ ·100

II:
o

RS=430

~~=15pF

1\

.0.3

1111111

1\

.0.4

1111111
1111111
10

750

FREQUENCY (MHz)

FIGURE 6. GAIN FLATNESS

VIN=1Vp.p
RL= 100

_..

",

1/

"

·110

·120
·130
10
100
FREQUENCY (MHz)

FIGURE 7. OFF ISOLATION

6·8

I

RS=820
CL=10pF

-60

..aD

RS = 360
CL=21pF

.0.2

~ ·70
~

J

!"::i
I III ~_ \

FIGURE 5. FREQUENCY RESPONSE

-SO

1111
1111

I i\1.J.

(Lo.1

~

(Continued)

500

100

\
500

HA4201

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

51 mils x 36 mils x 19 mils
1290llm x 910llm x 48311m

Type: Nitride
Thickness:

4kA ±O.5kA

METALLIZATION:

TRANSISTOR COUNT:
53

Type: Metal 1: AICu (1%)/TiW
Thickness: Metal 1:

6kA ±O.akA

SUBSTRATE POTENTIAL (Powered Up):

v-

Type: Metal 2: AICu (1%}
Thickness: Metal 2: 16kA ±1. 1

kA

Metallization Mask Layout
HA4201

...
EN

GND

v·
IN

III
'W
III:J:

1110

01a:-

0:=111
OUT

...

ISA20A2IA22A 1i180'tAOI

6-9

.,.

TALLY

0
WICZ

50
0..

HA4244
480MHz,1 x 1 Video Crosspoint
Switch with Synchronous Enable

November 1996

Features

Description

• Low Power Dissipation •...• , .••.•.••.•.•. 105mW

The HA4244 is a very wide bandwidth 1 x 1 crosspoint switch
ideal for professional video switching, HDTY, computer monitor routing, and other high performance applications. The circuit features verY' low power dissipation, excellent differential
gain and phase, high off isolation, symmetric slew rates, fast
switching, and a latched enable signal. When disabled, the
output is switched to a high impedance state, making the
HA4244 ideal for routing matrix equipment.

• Symmetrical Slew Rates ...•............• 1700Vllts
• 0.1dB Gain Flatness ••.••.•••••..••..••••. 250MHz
• -3dB Bandwidth ......................... 480MHz
• Off Isolation (100MHz) ...................... 85dB

• Differential Gain and Phase .•..• 0.01 %10.01 Degrees
• High ESD Rating ...•••••.••.•••.•..••••. >2000V
• TTL Compatible Control Signals
• Latched Enable Input for Synchronous Switching
• Powers-Up in Disabled State; Avoids Bus Contention

Applications
• Professional Video Switching and Routing
• Video Multiplexers

The latched enable input allows for synchronized channel
switching. When ClK is low the master control latch loads the
next EN, while the closed slave control latch maintains the crosspoint in its current state. ClK switching high closes the master
latch, loads the now open slave latch, and enables or disables
the HA4244 according to the current state of the EN input.
This crosspoint's design ensures that it powers up in the disabled state to eliminate bus contention concerns, and to
minimize supply current draw at power up.
For applications requiring an asynchronous crosspoint
switch, please refer to the HA4201 and HA4600 data sheets.

Ordering Information

• Computer Graphics

PART NUMBER
(BRAND)

• RF Switching and Routing

TEMP.
RANGEfC)

Ot070

• PCM Data Routing

HA4244CB
(H4244C)

Pinout

Functional Diagram
HA4244
(SOIC)
TOP VIEW

PKG.
NO.

PACKAGE
8 LdSOIC

M8.15

IN ----------------------~D/O____OUT

EN

ClK

rl>PP

Timing Diagram
ClK

EN

OUT

.:::J

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper Ie Handling Procedures.
Copyright@HarrisCorpora'tlon 1996

6-10

ENABLED

\.:
File Number

4078.1

HA4244
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ 12V
Input Voltage .................................... VSUPPLY
Digital Input Current (Note 2) ....................... , ±25mA
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20mA

Thermal Resistance (Typical, Note 1)

Operating Conditions

9JA (oCIW)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C
(SOIC - lead Tips Only)

Temperature Range ............................0oC to 70°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other condiffons above those indicated in the operational sections of this specification is not implied.

NOTES:
1. IlJA is measured with the component mounted on an evaluation PC board in free air.
2. If an input signal is applied before the supplies are powered up, the input current must be limited to this maximum value.

Electrical Specifications

VSUPPLY = ±5V, RL = 10kQ, VEN = 2.0V, Unless Otherwise Specified
HA4244

PARAMETER

TEST CONDITIONS

TEMP.
(DC)

MIN

TYP

MAX

UNITS

Full

±4.5

±5.0

±5.5

V

25, 70

10.5

13

mA

-

14.5

mA

275

jl.A

DC SUPPLY CHARACTERISTICS
Supply Voltage
Supply Current
(VOUT=OV)

VEN= 2.0V

0

-

VEN= 0.8V

25, 70

-

VEN= 0.8V

0

-

-

325

jl.A

25, 70

±2.7

±2.8

-

V

VEN= 2.0V

ANALOG DC CHARACTERISTICS
Output Voltage Swing without Clipping VOUT = VtN ± VIO ± 20mV

I/)

'W
1/)0
I/):z:

0

±2.4

±2.5

Output Current

Full

15

20

-

mA

03:

Input Bias Current

Full

30

50

I1A

oz

Output Offset VoHage

25

-

10

mV

Output Offset Voltage Drift (Note 3)

Full

25

50

I1VPC

-10

V

SWITCHING CHARACTERISTICS
Tum-On Time

25

Turn-Off Time

25

-

Input logic High Voltage

Full

Input logic low Voltage

Full

160

ns

-

ns

2

-

V

-

0.8

V

320

DIGITAL DC CHARACTERISTICS

EN Input Current

VEN=Ot04V

Full

-2

2

I1A

VCLK=Ot04V

Full

-10

10

jl.A

EN Setup Time to ClK Rising Edge

Full

25

ns

EN Hold Time after ClKRising Edge

Full

-

10

ns

Full

-

0.04

ClK Input Current

AC CHARACTERISTICS
Insertion Loss

1Vp_p

6-11

0.05

dB

O~
0::-

01/)
W~

>~

HA4244
Electrical Specifications VSUPPLY = ±5V, RL = 10ka, VEN = 2.0V, Unless Otherwise Specified (Continued)
HA4244

-3dB Bandwidth

±O.ldB Flat Bandwidth

TEMP.
(oC)

TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

Rs = 820,CL = 10pF

25

480

Rs = 430, CL = 15pF

25

380

Rs = 360, CL = 21pF

25

370

MHz

RS = 820, CL = 10pF

25

250

MHz

175

MHz

170

MHz

Rs = 430, CL = 15pF

25

Rs = 360, CL = 21pF

25

200

MHz

-

-

400

MHz

Input Resistance

Full

Input Capacitance

Full

Enabled Output Resistance

Full

-

15

0.01

0.02

%

0.01

0.02

Degrees

1.0

Disabled Output Capacitance

VEN= 0.8V

Full

Differential Gain

4.43MHz, Note 3

25

Differential Phase

4.43MHz, Note 3

25

-

kO
pF

-

2.0

0
pF

Off Isolation

lVp_p, 100MHz, VEN = 0.8V, RL = 100

Full

-

85

-

dB

Slew Rate
(1.5Vp_p, +SRI-SR)

Rs = 820, CL = 10pF

25

1750/1770

-

V/IlS

Rs = 430, CL = 15pF

25

-

1460/1360

-

V/jJ.s

Rs = 360, CL = 21pF

25

1410/1360

-

V/jJ.s

Nole3

Full

0.01

0.1

%

Total Harmonic Distortion
Disabled OutpUI Resistance

-

Full

12

MO

NOTE:
3. This parameler is not tested. The limits are guaranteed based on lab characterization, and reflect 101-10-101 varialion.

AC Test Circuit
Keep input and output traces as short as possible, because
trace inductance and capacitance can easily become the
performance limiting items.

Application Information
General
NOTE: CL = Cx + Tesl Fixture Capacitance.

PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors Is strongly recommended, while a solid
ground plane is a mustl

The HA4244 is a synchronous 1 x 1 crosspoint switch that is
ideal for the matrix element in small, high input-to-output isolation switchers and routers. The HA4244's low input capacitance and high input resistance provide excellent video
terminations when used with an external 750 resistor. This
crosspoint contains no feedback or gain setting resistors, so
the output is a true high impedance load when the IC is disabled (EN 0).

=

Synchronizing Latches
Attention should be given to decoupling the power supplies.
A large value (IOj.tF) tantalum in parallel with a small value
(O.IIlF) chip capacitor works well in most cases.

The HA4244 contains two latches which gate the EN input,
thereby allowing all the crosspoints in a matrix to switch
states synchronously. The latches also allow the EN input to
be changed without affecting the current state of the

6-12

HA4244
HA4244. Thus, the next channel switch can be set up, and
isn't acted upon until the next rising ClK edge. As long as
the EN signals meet a setup and hold time relative to the rising ClK edge, all of the HA4244s will assume their new
state at the same time.
Power-Up Disable Function
The double latched EN signal, and single ClK input prevent
the user from controlling the crosspoint state at power-up. To
rectify this situation, the HA4244 incorporates power-up circuitry to ensure that the crosspoint powers up in the disabled
state. Disabling the HA4244 prevents bus contention
between multiplexed outputs, and minimizes the switching
matrix supply current during power-up. Consider, for example, a matrix of 625 crosspoints that power-up randomly. If
50% of them power-up enabled, the required matrix supply
current is 3.3A (313 x 10.5mA), neglecting output current. If
HA4244s are utilized the power-up current is reduced to
0.125A (625 x 2001lA).
Frequency Response
Most applications utilizing the HA4244 require a series output resistor, RS, to tune the response for the specific load
capacitance, CL, driven. Bandwidth and slew rate degrade
as CL increases (as shown in the Electrical Specification
table), so give careful consideration to component placement to minimize trace length. As an example, -3dB bandwidth decreases to 160MHz for CL 100pF, RS OQ. In big
matrix configurations where CL is large, better frequency
response is obtained by cascading two levels of crosspoints
in the case of multiplexed outputs, or distributing the load
between two drivers if CL is due to bussing and subsequent
stage input capacitance.

=

Typical Performance Curves

~

....

r-

0.5

EN - The ENABLE input is a TTUCMOS compatible, active
high input. When driven low this input forces the output to a
true high impedance state and reduces the power dissipation by two orders of magnitude.
ClK - An active high, TTUCMOS compatible input that controls the synchronizing latches. When ClK transistions low,
the current state of the EN input is latched in the IC. This
allows the EN input to be changed to the value correspending to the next channel switch, without affecting the
HA4244's current state. The HA4244 assumes the new state
on the next rising edge of ClK.
Power Up Considerations
No signals should be applied to the digital inputs before the
power supplies are activated. latch-up may occur if the
inputs are driven at the time of power up. To prevent latchup, the input currents during power up must not exceed the
values listed in the Absolute Maximum Ratings.
Harris' Crosspoint Family
Harris offers a variety of 1 x 1 and 4 x 1 crosspoint switches. In
addition to the HA4244, the 1 x 1 family includes the HA4600,
which is an essentially similar device but without the synchronizing latches, and the HA4201 asynchronous crosspoint with a
Tally output (enable indicator). The 4 x 1 family is comprised of
the HA4314, HA4404, and HA4344. The HA4314 is a 14 lead
basic 4 x 1 crosspoint. The HA4404 is a 16 lead device with
Tally outputs to indicate the selected channel. The HA4344 is a
16 lead crosspoint with synchronized control lines (AO, A 1, CS).
With synchronization, the control information for the next channel switch can be loaded into the crosspoint without affecting
the current state. On a subsequent clock edge the stored control state effects the desired channel switch.

01-

a:0;:

Il..

1.20

Ii:" 1.15
Q.

;;; 1.10

~ 0.25

CJ
~ 1.05

g
5

if

!:i

0

!5 -0.25

l3

1.0

t5

0.95

'(

'I

50.90

o -0.5

II.

J

(/)0

:;:0

1.25

w

-0.75

(/)

'W

(/)::t:

O(/)
wICZ

VSUPPLY = ±5V, TA = 25°C, RL = 10kn, Unless Otherwise Specified

,

1.0
0.75

=

Control Signals

a!: 0.85

\

V-

-1.0

0.80
0.75
1

TIME (5nsJDIV.)

10

100

FREQUENCY (MHz)

FIGURE 1. LARGE SIGNAL PULSE RESPONSE

FIGURE 2. INPUT CAPACITANCE VB FREQUENCY

6-13

500

HA4244
Typical Performance Curves

VSUPPLy=±5V. TA=250C, RL= 101<0, Unless otherwise Specified

12

0.4
0.3

9
6

!

0.2

RS=82Q
C = 10pF Rs = 430

3

~ ~

',r"

-~L=~?F

I" I

f""i 1\

Rs=3lUl/
CL=21pF

-6

.g

iii

0.1

:!!.
i!!i

0

·12

.0.4
10

750

:!!.

FIGURE 4. GAIN FLATNESS

VIN= 1Vp.p
RL=100

·70

Z -80
§-80
i ·100

~

100

FREQUENCY (MHz)

-60

iii

~

1111111
1111111

FIGURE 3. FREQUENCY RESPONSE

·50

RS=43O
7CLc15pF

CL = 10pF
I I 11111

.0.3

10
100
FREQUENCY (MHz)

RS=36Q
CL = 21pF

-, Js'='aJ- \

.0.2

I" ,
HlL

I
I

I iIl!.J.

iLo.1

~

1111
1111

./
~

..

"

·110
·120
·130
10
100
FREQUENCY (MHz)

FIGURE 5. OFF ISOLATION

6·14

500

\

\
500

HA4244
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

51 mils x 36 mils x 19 mils
1290l1m x 91 Ol1m x 48311m
METALLIZATION:

Type: Nitride
Thickness: 4kA ±O.5kA
TRANSISTOR COUNT:

Type: Metal 1: AICu (1%)/TiW
Thickness: Metal 1: skA ±a.8kA

53
SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu (1 %j
Thickness: Metal 2: 1SkA ±1.1 kA

v-

Metallization Mask Layout
HA4244

EN

GND

vIN
(/)

'W
(/):x:

v+

(/)0

01a:-

03:

OUT

eLK

...

..

S-15

O(/)
wICZ

;;0
a..

HA43148
400MHz, 4 x 1 Video
Crosspoint Switch

November 1996

Features

Description

• Low Power Dissipation. • • • . • • • • • • • . . • • • •• 1051,1'1W

The HA4314B is a very wide bandwidth 4 x 1 crosspoint
switch ideal for professional video switching, HDTV, computer monitor routing, and other high performance applications. The circuit features very low power dissipation
(105mW Enabled, 4mW Disabled), excellent differential gain
and phase, and very high off isolation. When disabled, the
output is switched to a high impedance state, making the
HA4314B ideal for routing matrix equipment.

• Symmetrical Slew Rates •••....••.•...••• 1400Vll1s
• 0.1dB Gain Flatness••..•.••.....•••••.••. 100MHz
• ·3dB Bandwidth ••••••••••.••.••••••••••• 400MHz

• Off Isolation (1 OOMHz). • • • • • • • • • • • • • • . • • • • •• 70dB
• Crosstalk Rejection (30MHz). • • • • • • • • • . • • • . •• BOdB
• Differential Gain and Phase •••.• 0.01 %10.01 Degrees
• High ESD Rating •••• . • • • • • • • . • • • • • . • • • •• >2000V
• TTL Compatible Control Inputs

The HA4314B requires no external current source, and features fast switching and symmetric slew rates.
For a 4 x 1 crosspoint with Tally outputs (channel indicators)
or with synchronous control signals, please refer to the
HA4404B and HA4344B data sheets, respectively.

• Improved Replacement for GX4314 and GX4314L

Ordering Information

Applications
• Professional Video Switching and Routing

PART NUMBER

TEMP.
RANGE fc)

PKG.
NO.

PACKAGE

• HDlV

HA4314BCP

0 to 70

14 Ld PDIP

E14.3

• Computer Graphics

HA4314BCB

0 to 70

14 Ld SOIC

M14.1S

• RF Switching and Routing
• PCM Data Routing

Truth Table

Pinout
HA4314B
(PDIP, SOIC)
TOP VIEW
INO
GND

IN1
GND

g:

11
~
[!

[!
[!
1N3 II
IN2

GND

..,

o
o
o
o

~ v+

~ AO
~A1

1m ~

A1

AO

OUT

o

o

INO

o
o

IN2

x

HIGH-Z

IN3

x

~OUT

IN1

~ Ne

til y.

CAUTION: These devices are sensRIva to electrostatic discharge. Users should follow proper IC Handling Procedures.
Ccpyrlght @Harris Corpcratlon 1996

6-16

File Number

3679.4

HA43148
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and v- '" ......................... 12V
Input Voltage .................................... VSUPPLY
Digital Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . .. ±25mA
Analog Input Current (Note 2) ........................ ±5mA
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20mA

Thermal Resistance (Typical, Note 1)

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .. OoC to 70°C

8JA (oCIW)

PDIP Package ................... , . ..... . ..
100
120
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) .. . . . .. 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............ 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may cause permanent damage to the device. This is 8 stress only rating and operation
o( the device at these or any other conditions above those indicated In the operational sections o( this specification is not implied.
.

NOTES:
1. 8JA is measured with the component mounted on an evaluation PC board in free air.
2. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.

Electrical Specifications VSUPPLY = ±5V. RL = 10kQ, vcs = O.BV. Unless Otherwise Specified
PARAMETER

TEST CONDITIONS

(NOTE 4)
TEMP. (DC)

MIN

TYP

MAX

Full

±4.5

±5.0

±5.5

V

10.5

13

mA

15.5

mA

UNITS

DC SUPPLY CHARACTERISTICS
Supply Voltage

Vcs=O.BV

0

VCS=2.0V

25,70

V'C'S = 2.0V

0

-

25, 70

±2.7

±2.B

0

±2.4

±2.5

Output Current

Full

15

20

-

mA

0::I:

Input Bias Current

Full

30

50

I!A

°0

Output Offset Voltage

Full

-

10

mV

Output Offset Voltage Drift (Note 3)

Full

25

50

I!VPC

Supply Current (VOUT = OV)

25,70

Vcs=O.BV

400

450

I!A

400

5BO

I!A

ANALOG DC CHARACTERISTICS
Output Voltage Swing without Clipping

VaUT = VIN ± Via ± 20mV

-10

-

V
V

SWITCHING CHARACTERISTICS
Turn-On Time

25

160

Turn-Off Time

25

320

Output Glitch During Switching

25

±10

ns
ns

-

mV

DIGITAL DC CHARACTERISTICS
Input Logic High Voltage

Full

2

-

-

V

Input Logic Low Voltage

Full

-

-

O.B

V

Full

-2

-

2

I!A

25

-

Input Current

OVt04V

AC CHARACTERISTICS
Insertion Loss

1Vp_p

Channel-to-Channellnsertion Loss
Match
..adB Bandwidth

0.055

0.063

dB

Full

0.07

O.OB

dB

Full

±0.004

±0.006

dB

Rs = son, CL = 10pF

25

Rs = 20n, CL = 20pF

25

RS = 16n, CL = 36pF

25

Rs = 13n, CL = 49pF

25

6-17

-

400
2BO
140
110

-

MHz
MHz
MHz
MHz

°

'W

01a:-

0;:
OW
wIcZ
>0
c..

HA4314B
Electrical Specifications VSUPPLY = ±5V, RL = 101<0, VC"s = 0.8V, Unless Otherwise Specified (Continued)
PARAMETER

(NOTE 4)
TEMP·fC)

TEST CONDITIONS

:!;:O.ldB Flat Bandwidth

Rs = 500, CL = 10pF

25

Rs = 200, CL = 20pF

25

Rs = 160, CL = 36pF

25

RS = 130, CL = 49pF

25

MIN

TYP

MAX

100

-

MHz

Input Resistance

Full

200

400

Input Capacitance

Full

1.5

Enabled Output Resistance

Full

-

-

15

-

V~=2.0V

Full

Differential Gain

4.43MHz. Note 3

25

Differential Phase

4.43MHz, Note 3

25

1Vp_p,100MHz,
RL= 100

Full

-

Crosstalk Rejection

1Vp_p,30MHz

Full

Slew Rate (1.5Vp_p, +SR/-SR)

RS = 500, CL = 10pF

25

Off Isolation

100
85
75

Disabled Output Capacitance

~=2.0V,

Rs = 200, CL = 20pF

25

RS = 160, CL = 36pF

25

-

RS = 130, CL = 49pF

25

-

Total Harmonic Distortion

10MHz, RL = 11<0, Note 3

Full

Disabled Output Resistance

V~=2.0V

Full

-

UNITS

MHz
MHz
MHz
kO
pF
0

2.5

-

0.01

0.02

%

0.Q1

0.02

Degrees

70
80

pF

dB

-

1425/1450

dB
V/fJS

600/650

-

0.Q1

0.1

%

12

-

MO

1010/1010

725n50

V/fJS
V/fJS
V/fJS

NOTES:
3. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.
4. Units are 100% tested at 25°C; Guaranteed but not tested at OOC and 70°C.

AC Test Circuit

Application Information
5000

........
VIN_ r f ) 4

750

~7

RS

J.

".

4000

J
~\7

General

5100

~
'l
~

10kn

The HA4314B is a 4 x 1 crosspoint switch that is ideal for the
matrix element of high performance switchers and routers.
This crosspoint's low input capacitance and high input resistance provide excellent video terminations when used with
an external 750 resistor. Nevertheless, if several HA4314B
inputs are connected together, the use of an input buffer
should be considered (see Figure 1). This crosspoint contains no feedback or gain setting resistors, so the output is a
true high impedance load when the IC is disabled (CS 1).

750
VOUT

HFA1100

=

Ground Connections

NOTE: CL = Cx + Test Fixture Capacitance.

PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in deSigning the PC board. The use of low
Inductance components such as chip resistors and chip
capacitors Is strongly recommended, while a solid
ground plane is a mustl
Attention should be given to decoupling the power supplies.
A large value (10!1F) tantalum in parallel with a small value
(0.1 !1F) chip capacitor works well in most cases.
Keep input and output traces as short as possible, because
trace inductance and capacitance can easily become the
performance limiting items.

All GND pins are connected to a common point on the die,
so anyone of them will suffice as the functional GND connection. For the best isolation and crosstalk rejection, however, all GND pins must connect to the GND plane.
Frequency Response
Most applications utilizing the HA4314B require a series output resistor, Rs, to tune the response for the specific load
capacitance, CL, driven. Bandwidth and slew rate degrade
as CL increases (as shown in the Electrical Specification
table), so give careful consideration to component placement to minimize trace length. In big matrix configurations
where CL is large, better frequency response is obtained by
cascading two levels of crosspoints in the case of multi-

6-18

HA43148
plexed outputs (see Figure 2), or distributing the load
between two drivers if CL is due to bussing and subsequent
stage input capacitance.

HA4314B in a cascaded stage configuration to minimize
capacitive loading at each output node, thus increasing system bandwidth.

Control Signals

Power Up Considerations

CS - This is a TTUCMOS compatible, active low Chip Select
input. When driven high, CS forces the output to a true high
impedance state and reduces the power dissipation by a factor of 25. The CS input has no on-chip pull-down resistor, so
it must be connected to a logic low (recommend GND) if the
enable function isn't utilized.

No signals should be applied to the analog or digital inputs
before the power supplies are activated. Latch-up may occur
if the inputs are driven at the time of power up. To prevent
latch-up, the input currents during power up must not exceed
the values listed in the Absolute Maximum Ratings.

AO, A 1 - These are binary coded, TTUCMOS compatible
address inputs that select which one of the four inputs connect to the crosspoint output.
Switcher/Router Applications
Figure 1 illustrates one possible implementation of a wideband, low power, 4 x 4 switcher/router utilizing the HA4314B
for the switch matrix. A 4 x 4 switcher/router allows any of
the four outputs to be driven by anyone of the four inputs
(e.g., each of the four inputs may connect to a different output, or an input may connect to multiple outputs). This application utilizes the HA4600 (video buffer with output disable)
for the input buffer, the HA4314B as the switch matrix, and
the HFA 1112 (programmable gain buffer) as the gain of two
output driver. Figure 2 details a 16 x 1 switcher (basically a
16: 1 mux) which uses the HA4201 (1 x 1 crosspoint) and the

Harris' Crosspoint Family
Harris offers a variety of 4 x 1 and 1 x 1 crosspoint switches.
In addition to the HA4314B, the 4 x 1 family includes the
HA4404 and HA4344. The HA4404 is a 16 lead device with
Tally outputs to indicate the selected channel. The HA4344
is a 16 lead crosspoint with synchronized control lines (AO,
A 1, CS). With synchronization, the control information for the
next channel switch can be loaded into the crosspoint without affecting the current state. On a subsequent clock edge
the stored control state effects the desired channel switch.
The 1 x 1 family is comprised of the HA4201 and HA4600.
They are essentially similar devices, but the HA4201
includes a Tally output (enable indicator). The 1 x 1s are
useful as high performance video input buffers, or in a switch
matrix requiring very high off isolation.

SWITCH MATRIX

INPUT BUFFERS
+5V

C/)

'W

C/)::x:
C/)o

01-

0:0;:
oC/)

HA4314

HA4314

wI-

HA4314

CZ

SOURCE11~

>0
I:L

•
750 •

•
SOURCE21l
750
+5V

EN
SOURCE 3

750
OUTO

OUT1

FIGURE 1. 4 x 4 SWITCHERIROUTER APPLICATION

6-19

OUT2

OUT3

HA43148
SELO:3 SE[4:7

HA4314
SOURCEO

••
•

INO
750

~7

IN1

-

IN2
IN3

SOURCE3

1/4 CD74HCTOO
~

~

750
RS

V

OUT
INO

SOURCE4

••
•

750

OUT~

RS

HA4201

RS

IN1
IN2

V

t!

~

CS

IN3

SOURCE7

HFA1112 OR HFA1115
750

750

~7
SOURCE8

••
•

V

IN1

:v-

1/4 CD74HCTOO

IN2
IN3

CS

750
RS

V

OUT

SOURCE12

SOURCE15

OUT

P'

INO
750

SOURCE11

••
•

~X2

SEI:8:IT SEJ:l2:15

HA4314

INO
750

V

~750

OUT

IN1
IN2

K

~

~

RS

HA4201

CS

IN3

HA4314
SWITCHING
MATRIX

ISOLATION
MUX

OUTPUT
BUFFER

FIGURE 2. 16 x 1 SWITCHER APPLICATION

Typical Performance Curves

VSUPPLY = ±5V, TA = 25°C, RL = 10kn, Unless Otherwise Specified

1.0
0.75

~

0.5

~

0.25

~

0

w

!:l

,

t'

\

I

-0.5
-0.75

0.8

~

0

:.J

\
~

J

1.6

!

w

~ -0.25
o

~

:c

~

5
~
0

IN1=+250mV
IN3=OV
AO=+3V

2.4

250
125
0

,

\

(

\.

·1.0
TIME (5nBIDIV.)

TIME (200nBIDIV.)

FIGURE 3. LARGE SIGNAL PULSE RESPONSE

FIGURE 4. CHANNEL-TO-CHANNEL SWITCHING RESPONSE

6-20

HA43148
Typical Performance Curves

VSUPPLY = ±SV, TA = 25°C, RL = 10kQ, Unless Otherwise Specified (Continued)

III
III

VIN _1Vp.p

f- VIN" 1Vp.p

12

0.4
0.3

9

CL= 29pF
6

iii

3

~

Z

0

~

0.2

CL = 10pF

~

-3
·6

CL=20pF·

·9

CL=36pF

·12

CL=49pF
I

f'('
~

iii

",

Z

\

" -0.1

10
FREQUENCY (MHz)

100

CL=49pF
CL =36pF •
I

-0.2
-0.3

·1 r I

500

·10

/

PDIP /"
../" /"

:'.i

~ .a0
-90

:g
II:
U

t/'-l" :~

.100
·110

-30

.r

/
/

VIN = 1Vp.p
RL= 100

-20

//

-so
~ ·70

j-40

"

t!S -so

£.

~ .ao
~

~

·70

...

SOIC

o

:!i-60

10

100

0.2

z

~
Z

3.2

0.15

~

0.1

0
::Ii

II:

C

:z: 0.05
-'
C

e

--

",.",. ~

o

200

ro

~

~

V

V

~

3.0

~

2.6

~

/ "'"
./

CH.O

2.8

~

2.4

~

2.2

!;

...

2.0

IJ
~

~

CH.1
CH.2

1.6

1.4
~
~
"
ro
FREQUENCY (MHz)

"

~

~

1

FIGURE 9. TOTAL HARMONIC DISTORTION vs FREQUENCY

I

10
FREQUENCY (MHz)

--- "

100

FIGURE 10. INPUT CAPACITANCE vs FREQUENCY

6·21

1/
J

CH.3

!: 1.8

a::u:=
0
0

wt-

OZ

>0
a..

3.4
VIN= 1Vp.p
RL= 1kn

§:

~
c

100

FIGURE 8. ALL HOSTILE OFF ISOLATION

FIGURE 7. ALL HOSTILE CROSSTALK REJECTION

~

0t-

ro
FREQUENCY (MHz)

FREQUENCY (MHz)

0

0 U

III

u

200

0::1:

oW'" SOIC

·100
1

'W

PDIP .... ~

-90

·120
0.6

200

FIGURE 6. GAIN FLATNESS

VIN =1Vp.p
RL= 10kn

iiI-60

100

10
FREQUENCY (MHz)

FIGURE 5. FREQUENCY RESPONSE

-40

1\

CL=~pF

-0.4

\I

-- :MN
"
~I

0

:c

~

I I I

0.1

~

~

.l1Y

CL = 10pF

~O

HA4314B
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

65 mils x 118 mils x 19 mils
1640/lm x 3000/lm x 483/lm

Type: Nitride
Thickness: 4kA ±0.5kA

METALLIZATION:

TRANSISTOR COUNT:

Type: Metal 1: AICu (l%)/TiW
Thickness: Metal 1: 6kA ±0.8kA

200
SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu (1%)
Thickness: Metal 2: 16kA ±1.1 kA

v-

Metallization Mask Layout
HA4314B

GND

NC

INO

v+

INl

AO

NC

Al

GND

NC

OUT

IN2

NC

GND

NC

IN3

GND

6-22

NC

v-

HA4344B
350M Hz, 4 x 1 Video Crosspoint
Switch with Synchronous Controls

November 1996

Features

Description

• Low Power Dissipation ••..•.•.•.••.•••••• 10SmW

The HA43448 is a very wide bandwidth 4 x 1 crosspoint switch
ideal for professional video switching, HDTV, computer display
routing, and other high performance applications. This circuit
features very low power dissipation, excellent differential gain
and phase, high off isolation, symmetric slew rates, fast switching, and latched control signals. When disabled, the output is
switched to a high impedance state, making the HA43448 ideal
for matrix routers.

• Symmetrical Slew Rates ••••••••..•..•••. 1400VlIJ.S
• 0.1dB Gain Flatness .••.••..••..••.•••.••. 100MHz
• -3dB Bandwidth .••.....•...•...••••..•.• 3S0MHz
• Off Isolation (100MHz) .•••..•••••••••••.•.•. 70dB
• Crosstalk Rejection (30MHz). • • • • • • . . • • • • • . •• SOdB
• Differential Gain and Phase . • • .. 0.01 %10.01 Degrees

• RGB Video Distribution Systems

The latched control signals allow for synchronized channel
switching. When CK1 is low the master control latch loads the
next switching address (AO, A1, CS), while the closed (assuming CK2 is the inverse of CK1) slave control latch maintains the
crosspoint in its current state. CK2 switching low closes the
master latch (with previous assumption), loads the now open
slave latch, and switches the crosspoint to the newty selected
channel. Channel selection is asynchronous (changes with any
control signal change) if both CK1 and CK2 are low.

• Computer Graphics

Ordering Information

• High ESD Rating . . . • . • • • . . • • • . . . . • . • • • .. >2000V
• TTL Compatible Control Signals
• Latched Control Lines for Synchronous Switching

Applications
• Professional Video Switching and Routing

• RF Switching and Routing
PART NUMBER

TEMP.
RANGE ("C)

PKG.
NO.

PACKAGE

HA4344BCP

01070

16Ld PDIP

E16.3

HA4344BCB

01070

16 Ld SOIC

M16.15
(/)

'w

(/)::1:

Pinout

(/)0

Functional Diagram

01a::03:

HA4344B
(PDIP, SOIC)
TOP VIEW

O(/)

wIOZ

>0
D..

Timing Diagram

CKf~
en~
AO,A1,CS

OUT

~z'
CHX

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright Ii:) Harris Corporation 1996

6-23

X

CHY

a

HZ

File Number

3956.1

HA43448
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ 12V
Input Voltage ..•••.••••....•....•....••••.....• , . VSUPPLY
Digital Input Current (Note 2) . • . . . . . .. . . . .. • • . .. .. ... ±25rnA
Analog Input Current(Note 2) ............••.....•••.. ±5mA
Output Current. • • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . .. 20mA

Thermal Resistance (Typical, Note 1)

Operating Conditions
Temperature Range . . . . . . . . . . . . . . • . . . . • . . . . . .. OoC to 70°C

6JA

fclW)

PDIP Package. . . . . . . . . . . . . . . . . • . . . . . . . . . . .
90
SOICPackage.............................
115
Maximum Junction Temperature (Die) ...•...•..•.......•. 1750 C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ....••... -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) .•...••..... 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Raffngs' may cause permanent damage to the device. This Is a stress only rating and operaffon
of the device at these or any other conditions above those Indicated in the operational sooffons of thIs specificatIon is not implied.

NOTES:
1. OJA is measured with the component mounted on an evaluation PC board in free air.
2. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.

Electrical Specifications

VSUPPLY = ±5V, RL = 10kO, Vcs- = O.BV, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

(NOTE 4)
TEMP. (oC)

MIN

TYP

MAX

Full

±4.5

±S.O

±S.5

V

25, 70

-

10.5

13

rnA

-

15.5

rnA

-

400

450

f!A

400

5BO

f!A

UNITS

DC SUPPLY CHARACTERISTICS
Supply Voltage
Supply Current (VOUT = OV)

VCS=O.BV
VCS=O.BV

0

VCS=2.0V

25, 70

VCS=2.0V

0

ANALOG DC CHARACTERISTICS

0

±2.4

±2.5

Output Current

Full

15

20

-

Output Voltage Swing Without Clipping

VOUT = V,N ±V,O ±20mV

25, 70

±2.7

±2.B

V
V
rnA

Input Bias Current

Full

-

30

50

!lA

Output Offset Voltage

Full

·10

-

10

mV

Output Offset Voltage Drift (Note 3)

Full

-

25

50

!lV/DC

SWITCHING CHARACTERISTICS
Tum-On Time

25

Tum·OffTime

25

Output Glitch During SWitching

25

-

160

ns

-

mV

O.B

V

50

!lA

2

!lA

0.063

dB

0.07

O.OB

dB

±D.004

±D.006

dB

320
±10

ns

DIGITAL DC CHARACTERISTICS
Input Logic High Voltage

Full

2

Input Logic Low Voltage

Full

-

CLK1, CLK2 Input Current

Ot04V,

Full

~,AO, A11nput Current

Ot04V

Full

1Vp.p

25

V

40
-2

AC CHARACTERISTICS
Insertion Loss

Full
Channel-to-Channel Insertion Loss
Match

Full

6-24

0.055

-

HA43448
Electrical Specifications

VSUPPLY = ±5V, RL = 10kO, vcs = 0.8V, Unless Otherwise Specified (Continued)
(NOTE 4)
TEMP. (DC)

MIN

TYP

MAX

UNITS

Rs = 470, CL = 10pF

25

·

350

25

300

Rs = 160, CL = 33pF

25

Rs = 90, CL = 52pF

25

·
·
·

·
·
·

MHz

Rs = 290, CL = 20pF

160

·

MHz

Rs = 470, CL = 10pF

25

150

·
·
·

MHz

TEST CONDITIONS

PARAMETER
-3dB Bandwidth

±0.1dB Flat Bandwidth

220

RS = 290, CL = 20pF

25

·

110

RS = 160, CL = 33pF

25

·

100

Input Resistance

Full

200

400

Input Capacitance

Full

·

1.5

·
·
·

70

25

RS = 90, CL = 52pF

MHz
MHz

MHz
MHz
MHz
kO
pF

Full

15

·

VOs=2.0V

Full

2.5

·

Differential Gain

4.43MHz, Note 3

25

Differential Phase

4.43MHz, Note 3

25

Off Isolation

Wp.p, 1ooMHz, Vcs = 2.0V

Full

Crosstalk Rejection

Wp_p, 30MHz

Full

·

80

Rs = 470, CL = 10pF

25

Rs = 290, CL = 20pF

25

·
·

1400/1490

Rs = 160, CL = 33pF

25

·

870/940

·

750mO

·

VlILS

0(.)

0.01

0.1

%

12

·

MO

(.):3=
0 0

Enabled Ou1put Resistance
Disabled Output Capacitance

Slew Rate (1.5Vp_p, +SRI·SR)

25

Rs = 90, CL = 52pF
Total Harmonic Distortion (Note 3)
Disabled Ou1put Resistance

·

·

Full

VOs=2.0V

0.01

0.02

%

0.01

0.02

Degrees

70

·
·

dB

·
·
·

V/ILS

120011260

Full

NOTES:
3. This parameter is not tested. The limits are guaranteed based on lab charactarization, and reflect 10t·lO-lot variation.
4. Units are 100% tested at 25°C; guaranteed, but not tested at OOC and 70°C.

AC Test Circuit

.......

5000

.1

4000

~
to'"

Rs

exl

750

U

5100

T

HA4344B
VIN

~

10ka

~7

NOTE: CL = Cx + Test Fixture Capacitance.

6·25

75n

o YOUT
HFA1100

°

pF

dB

V/ILS

VlILS

o

'W

0::t:

0 ....
a::W ....

oz
>0
a..

(m

WJ

HA4404B

HARRIS
SEMICONDUCTOR

330M Hz, 4 X 1 Video
Crosspoint Switch with Tally Outputs

November 1996

Features

Description

• Low Power Dissipation. • • • • • • • • • • • • • • • • •• 105mW

The HA4404B is a very wide bandwidth 4 x 1 crosspoint
switch ideal for professional video switching, HDTV, com·
puter monitor routing, and other high performance applica·
tions. The circuit features very low power dissipation
(105mW Enabled, 4mW Disabled), excellent differential gain
and phase, and very high off isolation. When disabled, the
output is switched to a high impedance state, making the
HA4404B ideal for routing matrix equipment.

• Symmetrical Slew Rates ••••••••••••••••• 1250Vll!s
• O.ldB Gain Flatness .••••••••..•••.•••...• 165MHz
• -3dB Bandwidth •••••••••••••.••••••••••. 330MHz
• Off Isolation (1 OOMHz). • • • • • • • . • • • • • • • • • • • •• 70dB
• Crosstalk Rejection (30M Hz). • . • • • • . • • • • • • • •• SOdB
• Differential Gain and Phase •.••• 0.01 %10.01 Degrees
• High ESD Rating ••••..••••••.••••••••••. >2000V
• TTL Compatible Control Inputs
• Open Collector Tally Outputs
• Improved Replacement tor GX4404

The HA4404B requires no external current source, and fea·
tures fast switching and symmetric slew rates. The tally out·
puts are open collector PNP transistors to V+ to provide an
indication of crosspoint selection.
For a 4 x 1 crosspoint without Tally outputs or with synchro·
nous control signals, please refer to the HA4314B and
HA4344B Data Sheets, respectively.

Ordering Information

Applications
• Professional Video Switching and Routing
• HDTV
• Computer Graphics

PART NUMBER

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

HA4404BCP

Ot070

16Ld PDIP

E16.3

HA4404BCB

Ot070

16 Ld SOIC

M16.15

• RF Switching and Routing

Functional Diagram

Pinout
HA4404B
(PDIP, SOIC)
TOP VIEW

I~ v+

ENO

IEN1

AOA1_ DECODE

r

INO J ...

EN2

TO

Jv+

T1

IN1J...
-OUT
IN2---f"

CS-

v+
r

""EN3

IN3 ........

T2

v+
T3

TRUTH TABLE

A1

AO

0

0

0

INO

TO

0

0

1

IN1

T1

0

1

0

IN2

T2

0

1

1

IN3

T3

1

X

X

High·Z

CAUTION: These devices are sensttlve to' electrostatic discharge. Users should lollow proper IC Handling Procedures.
Copyright @ Harris Corporation 1996

6-26

ACTIVE TALLY
OUTPUT

CS

OUT

None, All High· Z

File Number

3678.4

HA4404B
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- ............................ 12V
Input Voltage .................................... VSUPPLY
Digital Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . .. ±25mA
Analog Input Current (Note 2) ... . . . . . . . . . . . . . . . . . . . .. ±5mA
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20mA

Thermal Resistance (Typical, Note 1)

Operating Conditions
Temperature Range .......................... , OOC to 70°C

9JA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
115
SOIC Package ................. , . . . . . . . . . . .
Maximum Junction Temperature (Die) ........ , .......... 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ........... , 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. 8JA is measured with the component mounted on an evaluation PC board in free air.
2. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.

Electrical Specifications VSUPPLY = ±5V, RL = 10kQ, v~ = 0.8V, Unless Otherwise Specified
PARAMETER

TEST CONDITIONS

(NOTE 4)
TEMP. (DC)

MIN

TYP

MAX

Full

±4.5

±5.0

±5.5

V

10.5

13

rnA

UNITS

DC SUPPLY CHARACTERISTICS
Supply Voltage
Supply Current (VOUT = OV)

V~=0.8V

25, 70

-

-

15.5

rnA

400

450

I'A

400

580

I'A

±2.7

±2.8

-

±2.4

±2.5

Vcs= 0.8V

0

V~=2.0V

25,70

Vc:;s= 2.0V

0

-

25, 70
0

Output Current

Full

15

20

-

rnA

Input Bias Current

Full

-

30

50

I1A

Output Offset Voltage

Full

-10

-

10

mV

Output Offset Voltage Drift (Note 3)

Full

-

25

50

I'VPC

Turn-On Time

25

-

160

Turn-Off Time

25

Output Glitch During Switching

25

ANALOG DC CHARACTERISTICS
Output Voltage Swing without Clipping

VOUT = VIN ± VIO ± 20mV

V
V

SWITCHING CHARACTERISTICS

Input Current

320

-

±10

-

mV

2

-

-

V

-

0.8

V

-2

-

2

I1A

ns
ns

High

Full

Low

Full

OV to 4V

Full

Tally Output High Voltage

IOH= lmA

Full

4.7

4.8

-

V

Tally Off Leakage Current

VTALLY=OV

Full

-20

-

20

I1A

25

-

AC CHARACTERISTICS
Insertion Loss

Wp_p

Channel-to-Channel Insertion Loss Match
-3dB Bandwidth

Oen
W~

-

DIGITAL DC CHARACTERISTICS
Input Logic Voltage

en
'W
enJ:
en O
O~
a:03:

Rs = 500, CL = llpF

0.055

0.063

dB

Full

0.07

0.08

dB

Full

±0.004

±0.006

dB

25

330

-

MHz

Rs = 240, CL = 19pF

25

RS = 150, CL = 34pF

25

Rs = 110, CL = 49pF

25

6-27

-

290
210
170

-

MHz
MHz
MHz

CZ

>0
~

HA4404B
Electrical Specifications VSUPPLY = ±5V, RL = 10kn, Yes = 0.8V. Unless Otherwise Specified (Continued)
PARAMETER

(NOTE 4)
TEMP·fC)

TEST CONDiTIONS

±O.ldB Flat Bandwidth

MIN

TYP

MAX

UNITS

Rs = son, CL = llpF

25

165

MHz

Rs = 24n, CL = 19pF

25

130

MHz

Rs = 15n, CL = 34pF

25

137

MHz

Rs = lln, CL = 49pF

25

100

MHz

400

kn
pF

Input Resistance

Full

Input Capacitance

Full

1.5

Enabled Output Resistance

Full

15

n
pF

200

Disabled Output Capacitance

Vcs= 2.0V

Full

2.5

Differential Gain

4.43MHz, Note 3

25

0.01

0.02

%

Differential Phase

4.43MHz, Note 3

25

0.Q1

0.02

Degrees

Off Isolation

lVp_p, 100MHz, Ves = 2.0V,
RL=10n

Full

70

Crosstalk Rejection

lVp_p,30MHz

Full

80

dB

Slew Rate (1.5Vp_p, +SRI-SR)

Rs = son, CL = llpF

25

1280/1260

VIlIS
VIlIS

dB

Rs = 24n, CL = 19pF

25

1190/1170

Rs = 15n, CL = 34pF

25

960/930

V/IIS

Rs = lln, CL = 49pF

25

81On90

Total Harmonic Distortion

10MHz, RL = 1kn, Note 3

Full

0.Q1

VIlIS
%

Disabled Output Resistance

Ves=2.0V

Full

12

0.1

Mn

NOTES:
3. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.
4. Units are 100% tested at 25°C; guaranteed, but not tested at OOC and 70°C.

AC Test Circuit

Application Information
General

5000

.... ..t
....

5100

The HA4404B is a 4 x 1 crosspoint switch that is ideal for the
matrix element of high performance switchers and routers.
This crosspoint's low input capacitance and high input resistance provide excellent video terminations when used with
an external 750 resistor. Nevertheless, if several HA4404B
inputs are connected together, the use of an input buffer
should be considered (see Figure 1). This crosspoint contains no feedback or gain setting resistors, so the output is a
true high impedance load when the IC is disabled (CS = 1).

7

VIN_~4BRS
750 : ~
db
'\7

4000

~cx '\7

Your

10k~

HFAll00

NOTE: CL = Cx + Test Fixture Capacitance.

Ground Connections

PC Board Layout
The frequency response of this circuit depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane Is a mustl
Attention should be given to decoupling the power supplies.
A large value (10IlF) tantalum in parallel with a small value
(O.1IlF) chip capacitor works well in most cases.
Keep input and output traces as short as possible, because
trace inductance and capacitance can easily become the
performance limiting items.

All GND pins are connected to a common point on the die,
so anyone of them will suffice as the functional GND connection. For the best isolation and crosstalk rejection, however, all GND pins must connect to the GND plane.
Frequency Response
Most applications utilizing the HA4404B require a series output resistor, RS, to tune the response for the specific load
capacitance, CL, driven. Bandwidth and slew rate degrade as
CL increases (as shown in the Electrical Specification table),
so give careful consideration to component placement to minimize trace length. In big matrix configurations where CL is
large, better frequency response is obtained by cascading two
levels of crosspoints in the case of multiplexed outputs (see

6-28

HA44048
Figure 2), or distributing the load between two drivers if Cl is
due to bussing and subsequent stage input capacitance.

Control Signals
CS - This is a TTUCMOS compatible, active low Chip Select
input. When driven high, CS forces the output to a true high
impedance state and reduces the power dissipation by a factor of 25. The CS input has no on-chip pull-down resistor, so
it must be connected to a logic low (recommend GND) if the
enable function isn't utilized.
AO, A 1 - These are binary coded, TTUCMOS compatible
address inputs that select which one of the four inputs connect to the crosspoint output.
TO-T3 - The Tally outputs are open collector PNP transistors
connected to V+. When CS = 0, the PNP transistor associated with the selected input is enabled and current is delivered to the load. When the crosspoint is disabled, or the
channel is unselected, the Tally output(s) present a very high
impedance to the external circuitry. Several Tally outputs may
be wire OR'd together to generate complex control signals, as
shown in the application circuits below. The Tally load may be
terminated to GND or to V- as long as the continuous output
current doesn't exceed 3mA (6mA at 50% duty cycle, etc.).

Swltcher/Router Applications
Figure 1 illustrates one possible implementation of a wideband,
low power, 4 x 4 switcher/router utilizing the HA4404B for the
switch matrix. A 4 x 4 switcher/router allows any of the four outputs to be driven by anyone of the four inputs (e.g., each of the
four inputs may connect to a different output, or an input may
connect to multiple outputs). This application utilizes the

HA4600 (video buffer with output disable) for the input buffer,
the HA4404B as the switch matrix, and the HFA 1112 (programmable gain buffer) as the gain of two output driver. Figure 2
details a 16 x 1 switcher (basically a 16:1 mux) which uses the
HA4201 (1 x 1 crosspoint) and the HA4404B in a cascaded
stage configuration to minimize capacitive loading at each output node, thus increasing system bandwidth.

Power Up Considerations
No signals should be applied to the analog or digital inputs
before the power supplies are activated. Latch-up may occur
if the inputs are driven at the time of power up. To prevent
latch-Up, the input currents during power up must not exceed
the values listed in the Absolute Maximum Ratings.

Harris' Crosspoint Family
Harris offers a variety of 4 x 1 and 1 x 1 crosspoint switches.
In addition to the HA4404B, the 4 x 1 family includes the
HA4314 and HA4344. The HA4314Is a basic 14 lead device
without Tally outputs. The HA4344 is a 16 lead crosspoint
with synchronized control lines (AO, A1, CS). With synchronization, the control information for the next channel switch
can be loaded into the crosspoint without affecting the current state. On a subsequent clock edge the stored control
state effects the desired channel switch.
The 1 x 1 family is comprised of the HA4201 and HA4600.
They are essentially similar devices, but the HA4201
includes a Tally output. The 1 x 1s are useful as high performance video input buffers, or in a switch matrix requiring
very high off isolation.
(/)

'W
(/)x
(/)0

0 .....

a:03:

swrrcH MATRIX

INPUT BUFFERS

1DkD

O(/)

W .....

CZ

SOURCED

>0
0..

SOURCE11l
7SD

•

•
•

OUT1

OUTO

FIGURE 1. 4 X 4 SWlTCHERlROUTER APPLICATION

6-29

OUT2

OUT3

HA4404B

SWITCHING MATRIX

ISOLA11ON MUX

OUTPUT BUFFER

HA4404B
SOURCEO

••
•

INO
750 INl
IN2

SOURCE3

IN3
750

TO

•••

T3

10110

RS
RS

SOURCE4

•••
SOURCE7

INO
INl

•

••

IN2

T3
IN3

HFAll12 OR HFAll15

SOURCE8

•••
SOURCEll

750

.;

HA4404B

OUT

X2

INO
IN1

10lI0

SOURCE12

••
•
SOURCE15

INl
IN2

RS

TO

••
•

T3

IN3

HA4404B

FIGURE 2. 16 X 1 SWITCHER APPLICATION

Typical Performance Curves

VSUPPLY =±5V, TA =25°C, RL =10kel, Unless Otherwise Specified

1.0

E

I

0.5

!i!

\

,
I

~ 0.25

~

E

/"-

0.75

.0.25

o

.0.5

.0.75

J

,

~w

1\

J

IN1_+250mV
1N3.0V
AO.+3V

1.6

\

0

~

2A

i!:i
!i!

!i

--

\

·1.0
TIME (5na/DIV.)

§

0.8

0
250
125

0

~

(

I

~
TIME (200na/DIV.)

FIGURE 3. LARGE SIGNAL PULSE RESPONSE

FIGURE 4. CHANNEL-TO-CHANNEL SWITCHING RESPONSE

6-30

HA44048
Typical Performance Curves

v SUPPLY = ±5V, TA = 25°C, RL = 1Oka, Unless Otherwise Specified (Continued)

VIN = 1Vp-p

3
2

iii'

0.3

0

~

z

~

CL = 49pF

-2

0.2

,

IW

-1

~

VIN = 1Vp_p

0.4

iii'
~

z

~

1- r'
CL = 19pF
...\ ft'
CL= llpF
\
I IIIII
U

f'

0.1

.#

0

.j\

-0.1

CL = 19pF

CL = 34pF

-3
-4
-5

10
FREQUENCY (MHz)

-0.2

CL = llpF

-0.3

CL=34pF

-0.4

CL=49pF

1 J

100

500

10
FREQUENCY (MHz)

FIGURE 5. FREQUENCY RESPONSE

/

iii' -50

~

-70

,/

V

U)

~ -90
-110
-120

-50

V
~

V

~
oj

,.--"

~ -80

0-100

V
V

PD~

,~

."'V'
ll", VI

r$'OIC

V

-60

-'

-70
-80

1oi!I'~

-90

PDIP . " ~

~ -100

o -110

10

100

200

~

z

~

0.15

!:!

0.1

~

z

/

/

0

::;

a::
oC
:r:

....

0.05

~

o

--

10

I--V

20

30

"

/

03:

ou)

100

200

4.5

V

4.2

~

II

IL'

3.9

w

3.6

f

z

3.3

IJ

0

3.0

oS
0

~

ifoC

0

I:::J
Q.

I

IfJ

2.7
2.4

iii!: 2.1

-

1.8 80

90

CH.O
CH.3

./
./

CH.2

1

FIGURE 9. TOTAL HARMONIC DISTORTION vs FREQUENCY

-

IJ
I}I

~

CH.l

1.5

100

10
FREQUENCY (MHz)

100

FIGURE 10. INPUT CAPACITANCE vs FREQUENCY

6-31

WICZ

>0
D..

FIGURE 8. ALL HOSTILE OFF ISOLATION

V

40
50
60
70
FREQUENCY (MHz)

II:-

10
FREQUENCY (MHz)

FREQUENCY (MHz)

VIN = lVp_p
RL = lkn

01-

I

FIGURE 7. ALL HOSTILE CROSSTALK REJECTION

0.2

U)

'W

U):I:
U)o

~OIC

It

-120

1

0.6

500

VIN = 1Vp_p
RL=10n

-40

V/

-50

100

FIGURE 6. GAIN FLATNESS

VIN = 1Vp_p
RL=10kn

-40

1\

SOD

HA4404B
Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

65 mils x 118 mils x 19 mils
1640l!m x 3000J,lm x 4831!m

Type: Nitride
Thickness: 4kA ±a.5kA
TRANSISTOR COUNT:

METALLIZATION:

200

Type: Metal 1: AICu (1%)fTiW
Thickness: Metal 1: 6kA ±a.8kA

SUBSTRATE POTENTIAL (Powered Up):

Type: Metal 2: AICu (1%)
Thickness: Metal 2: 16kA ±1.1 kA

v-

Metallization Mask Layout
HA4404B

GND

TO

INO

v+

IN1

AO

T1

A1

NC

T2

OUT

IN2

NC

GND

NC

IN3

GND

6-32

T3

v·

HA455

HARRIS
SEMICONDUCTOR
ADVANCE INFORMATION
8

November 1996

X

130MHz,
8 Video Crosspoint Switch

Features

Description

• Fully Buffered Inputs and Outputs (Av = +1)

The HA455 is the first 8 x 8 video crosspoint switch suitable
for high performance video systems. Its high level of integration significantly reduces component count, board space,
and cost. The crosspoint switch contains a digitally controlled matrix of 64 fully buffered switches that connect eight
video input signals to any, or all, matrix outputs. Each matrix
output connects to an internal, high-speed (250V/~s), unity
gain buffer capable of driving 4000 and 20pF to ±2V.

• Routes Any Input Channel to Any Output Channel
• Switches Standard and High Resolution Video Signals
• Serial or Parallel Digital Interface
• Expandable for Larger Switch Matrices
• Wide Bandwidth ......................... 130MHz
• High Slew Rate ...•......................

250V/~s

• Low Differential Gain/Phase ..... 0.02%/0.02 Degrees
• Low Crosstalk at 10MHz ................... -SOdB

Applications

For applications requiring gain or increased drive capability,
the HA455 outputs can be connected directly to two HFA1412
quad, gain of two video buffers, which are capable of driving
750 loads. Another option which also provides gain capability
is the HA457 170MHz, gain of two 8 x 8 crosspoint.
This crosspoint's true high impedance three-state output
capability, makes it feasible to parallel multiple HA455s and
form larger switch matrices.

• Professional Video Switching and Routing
• Security and Video Editing Systems

OrderinglnfortnaHon
PART NUMBER
HA455CN

TEMP.
RANGE (oC)

Oto 70

PACKAGE
44 LdMQFP

PKG. NO.
M44.10x10
U)

'W

U)::t:
U)o

Pinout

0 ....
~­

o3!:

HA455 (MQFP)
TOP VIEW

0U)

W ....

CZ

!:i

>0
D.

i!: 0

II: II:
W

W

0

Nc(!!1~O+!:i
Q Q Z > 0

AO

OUT2

IN'
NC

OUT3

V-

IN2

AGND

DGND

OUT4
NC

NC
IN3

AGND

DGND

OUTS

IN4

AGND

EDGEILEVEL

OUT6

INS

V+

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

6-33

File Number

4264

HA456

OD HARRIS
(KJ

SEMICONDUCTOR

80M Hz, Low Power,
8 x 8 Video Crosspoint Switch

ADVANCE INFORMATION
November 1996

Features

Description

• Fully Buffered Inputs and Outputs (Av

=+1)

• Routes Any Input Channel to Any Output Channel
• Switches Standard and High Resolution Video Signals
• Serial or Parallel Digital Interface
• Expandable for Larger Switch Matrices
• Wide Bandwidth ••••••••••••••••••••.••.•. 80MHz
• High Slew Rate .•....•..••..•••..•.•..•.• 170VlllS
• Low Differential Gain/Phase •..••. 0.04%10.2 Degrees
• Low Crosstalk at 10MHz ••••.••••••.•••••••• -SOdB

Applications
• Professional Video Switching and Routing

The HA456 is the first 8 x 8 video crosspoint switch suitable
for high performance video systems. Its high level of integration significantly reduces component count, board space,
and cost. The crosspoint switch contains a digitally controlled matrix of 64 fully buffered switches that connect eight
video input signals to any, or all, matrix outputs. Each matrix
output connects to an internal, high-speed (170VlJ.lS), unity
gain buffer capable of driving 4000 and 20pF to ±2.V.
For applications requiring gain or increased drive capability,
the HA456 outputs can be connected directly to two HFA1412
quad, gain of two video buffers, which are capable of driving
750 loads. Another option which also provides gain capability
is the HA457 170MHz, gain of two 8 x 8 crosspOint.
This crosspoint's true high impedance three-state output
capability, makes it feasible to parallel multiple HA456s and
form larger switch matrices.

• Security and Video Editing Systems

Ordering Information
PART NUMBER

TEMP.
RANGE ("C)

PACKAGE

PKG. NO.

HA456CN

01070

44 LdMQFP

M44.10x10

HA456CM

01070

44 LdPLCC

N44.65

Pinouts
HA456 (MQFP)
TOP VIEW

HA456 (PLCC)
TOP VIEW

8

ii!:
a: a:

LLI UJ

I0

.....

ii!:S
a: a:

~:C~~~!il:t8S8S

LLlW

AO
IN1
NC

OUT2

IN2
DGND

AGND

NC
IN3
DGND

0

'I"'"

~~N§~O
+!5 !5 ...
_eCeC
cZ>O S OC

vOUT3
0UT4
NC
AGND
OUTS

IN4

AGND

EDGEILEVEL
INS

OUT6

•

AO
IN1
NC
IN2
DGND
NC
IN3
DGND
IN4
EDGE/LEVEL
INS

OUT2

vOUT3
AGND
OUT4
NC
AGND
OUTS
AGND
OUT6

v+

v+
+"'Ia: ....
>z""z
~-

-

III
UI

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

6-34

5 °0

:>oa::z:~1Il ~

z;;::o

File Number

4153

HA457
ADVANCE INFORMATION

170MHz, AV=+2, 8 X 8
Video Crosspoint Switch

November 1996

Description

Features
• Fully Buffered Inputs and Outputs (Av = +2)
• Routes Any Input Channel to Any Output Channel
• Switches Standard and High Resolution Video Signals
• Serial or Parallel Digital Interface
• Expandable for Larger Switch Matrices
• Wide Bandwidth ..•.••....•..•.•.•....•.• 170MHz
• High Slew Rate •..•.•.•.•.•......•....•.• 350Vll!s
• Low Differential Gain/Phase ••..• 0.01%10.02 Degrees
• Low Crosstalk at 10MHz • . . • . . . • . • • . . . . . . .. -SOdB

Applications
• Professional Video SWitching and Routing
• Video Editing

Ordering Information

HA457CN

TEMP.
RANGE (oC)
Ot070

PACKAGE
44 Ld MQFP

The HlIlOPOWER lead may be strapped to GND for power
critical applications that don't require "broadcast quality"
video performance. In this low power mode, power dissipation decreases from 880mW to 560mW.
The HA457 will directly drive a double terminated video
cable with some degradation of differential gain and phase.
Applications demanding the best composite video performance should drive the cable with a unity gain video buffer,
such as the HFA1412 quad buffer.

• Security Systems

PART NUMBER

The HA457 is the first 8 x 8 video crosspoint switch suitable
for high performance video systems. Its high level of integration significantly reduces component count, board space,
and cost. The crosspoint switch contains a digitally controlled matrix of 64 fully buffered switches that connect eight
video input signals to any, or all, matrix outputs. Each output
connects to eight internal, high-speed (350V/l!s), gain of two
buffers capable of driving 1500 and 20pF to ±2.0V.

This crosspoinfs three-state output capability, makes it feasible
to parallel multiple HA457s and form larger switch matrices.

PKG.NO.
M44.10x10

I/)

'w

I/):r;

1/)0
01-

Pinout

a::-

HA457
(MQFP)
TOP VIEW

OS:

01/)
wIOZ

5

>0
a..

iii: 0

a: a:

III

a;:(~~

III
II!
.....

0
I-

§

0 + :::l C'\I
cz>oco S

AO
IN1

OUT2

HI/LOPOWER

OUT3

IN2
DGND
NC

OUT4
NC

vAGND

IN3

AGND

DGND
IN4
EDGEJi:EIIEL

OUT5
AGND
OUT6

INS

v+

~~I~

>ua::I:~1II5
z;=uuu

5

III

0

III

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper Ie Handling Procedures.
Copyright © Harris Corporation 1996

6-35

File Number

4231

HA4600
480MHz,
Video Buffer with Output Disable

November 1996

Features

Description

• Low Power Dissipation •..••...••••••.••.• 105mW

The HA4600 is a very wide bandwidth, unity gain buffer ideal
for professional video switching, HDTV, computer monitor
routing, and other high performance applications. The circuit
features very low power dissipation (105mW Enabled. 1mW
Disabled), excellent differential gain and phase, and very
high off isolation. When disabled, the output is switched to a
high impedance state, making the HA4600 ideal for routing
matrix equipment and video multiplexers.

• Symmetrical Slew Rates ..•••••.•.•••.••• 1700VlllS
• 0.1dB Gain Flatness••••••.•.•.•..••.•••.• 250MHz

• Off Isolation (100MHz) ••••..•••••..••••••••• 85dB
• Differential Gain and Phase ••••• 0.01%10.01 Degrees
• High ESD Rating •••••..••.•••...•••••••. >2000V

• Improved Replacement for GB4600

The HA4600 also features fast switching and symmetric slew
rates. A typical application for the HA4600 is interfacing
Harris' wide range of video crosspoint switches.

Applications

For applications requiring a tally output (enable indicator),
please refer to the HA4201 data sheet.

• Professional Video Switching and Routing

Ordering Information

• TTL Compatible Enable Input

• Video Multiplexers

PART NUMBER
(BRAND)

• HDTV
• Computer Graphics
• RF Switching and Routing

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

HA4600CP

01070

8Ld PDIP

E8.3

HA4600CB
(4600CB)

01070

8Ld SOIC

M8.15

• PCM Data Routing

Pinout

Truth Table
HA4600

EN

(PDIP, SOIC)
TOP VIEW

HighZ

1

Active

CAUTION: These devices are sensitive to electrostatic discharge. Usars should follow proper Ie Handling Procedures.
Copyright © Harris Corporation 1996

6-36

OUT

0

File Number

3990.2

HA4600
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Input Voltage .................................... VSUPPLY
Digital Input Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . .. ±25mA
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20mA

Thermal Resistance (Typical, Note 1)

Operating Conditions
Temperature Range ......................... "

DoC to 70°C

6JA (oCIW)

130
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . .. 175°C
Maximum Junction Temperature (Plastic Package) ....... 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) ............ 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of /he device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.
2. If an input signal is applied before the supplies are powered up, the input current must be limited to this maximum value.

Electrical Specifications VSUPPLY = ±5V, RL = 101<0, VEN = 2.0V, Unless Otherwise Specified
TEST CONDITIONS

PARAMETER

TEMP. ("C)

MIN

TYP

MAX

Full

±4.5

±5.0

±5.5

V

25,70

-

10.5

13

rnA

UNITS

DC SUPPLY CHARACTERISTICS
Supply Voltage
Supply Current (VOUT = OV)

VEN=2V

-

14.5

rnA

VEN= O.BV

25,70

-

100

115

VEN=O.BV

0

-

100

125

IJ.A
IJ.A

25,70

±2.7

±2.B

-

V

0

±2.4

±2.5

Output Current

Full

15

20

-

mA

30

50

IJ.A

10

mV

50

IlVPC

0

VEN=2V

ANALOG DC CHARACTERISTICS
Output Voltage Swing without Clipping

VOUT = VIN ± VIO ± 20mV

Input Bias Current

Full

-

Output Offset Voltage

25

-10

Output Offset Voltage Drift (Note 3)

Full

25

25

160

25

320

V

SWITCHING CHARACTERISTICS
Tum-On Time
Tum-OIl Time

I
I

-

ns

Input Logic High Voltage

Full

2

-

V

Input Logic Low Voltage

Full

-

O.B

V

OVt04V

Full

-2

2

IJ.A

Insertion Loss

1Vp_p

Full

0.04

0.05

dB

-3dB Bandwidth

Rs = B2Q, CL = 10pF

25

4BO

-

MHz

Rs = 43Q, CL = 15pF

25

Rs = 36Q, CL = 21pF

25

370

RS = B2Q, CL = 10pF

25

250

Rs = 43Q, CL = 15pF

25

175

Rs = 36Q, CL = 21pF

25

-

170

AC CHARACTERISTICS

±0.1dB Flat Bandwidth

-

3BO

MHz

-

MHz
MHz
MHz

Input Resistance

Full

200

400

Input Capacitance

Full

-

1.0

Enabled Output Resistance

Full

-

-

15

-

Q

2.0

-

pF

0.01

0.02

%

Disabled Output Capacitance

VEN= 0.8V

Full

Differential Gain (Note 3)

4.43MHz

25

6-37

-

01a:03:

oU)

ns

DIGITAL DC CHARACTERISTICS

EN Input Current

U)

'W
U)::r:
U)o

MHz
kQ
pF

wI-

CZ

>~

HA4600
Electrical Specifications VSUPPLY = ±5V, RL = 10kQ, VEN = 2.0V. Unless Otherwise Specified (Continued)
TYP

MAX

UNITS

Differential Phase (Note 3)

4.43MHz

TEST CONDITIONS

25

0.01

0.02

Degrees

Off Isolation

1Vp_p, 100MHz,
VEN = 0.8V, RL = 100

Full

85

dB

Slew Rate (1.5Vp_p, +SR/-SR)

Rs = 820, CL = 10pF

25

1750/1770

VIlIS

Rs = 430, CL = 15pF

25

146011360

PARAMETER

TEMP. fC)

MIN

25

1410/1360

Total Harmonic Distortion (Note 3)

Full

0.D1

Disabled Output ReSistance

Full

12

Rs = 360, CL = 21pF

VlJls
0.1

%
MO

NOTE:
3. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-Iot variation.

AC Test Circuit

~
.
rl>
HA4600

VIN 0-

;:0
VRs

750

~7

I~
_;1":0

4000

=

750

.,;li"HFA11 00

T

Tex
V

I

as CL increases (as shown in the Electrical Specification
table), so give careful consideration to component placement to minimize trace length. As an example, -3dB bandwidth decreases to 160MHz for CL 100pF, RS on. In big
matrix configurations where CL is large, better frequency
response is obtained by cascading two levels of crosspoints
in the case of multiplexed outputs (see Figure 2), or distributing the load between two drivers if CL is due to bussing and
subsequent stage input capacitance.

VoUT

10110

~7

=

NOTE: CL = Cx + Test Fixture Capacitance.

Control Signals

PC Board Layout

EN - The ENABLE input is a TTUCMOS compatible, active
high input. When driven low this input forces the output to a
true high impedance state and reduces the power dissipation by two orders of magnitude. The EN input has no onchip pull-up resistor, so it must be connected to a logic high
(recommend V+) if the enable function isn't utilized.

The frequency response of this circuit depends greatly on the
care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane
isamus!1
Attention should be given to decoupling the power supplies.
A large value (10IlF) tantalum in parallel with a small value
(0.1IlF) chip capacitor works well in most cases.
Keep input and output traces as short as possible, because
trace inductance and capacitance can easily become the
performance limiting items.

ApplicaUonlnforlnaUon
General
The HA4600 is a unity gain buffer that is optimized for high per. formance video applications. The output disable function
makes it ideal for the matrix element in small, high input-to-output isolation switchers and routers. This buller contains no
feedback or gain setting resistors, so the output is a true high
impedance load when the IC is disabled (EN 0). The HA4600
also excels as an input buffer for routers with a large number of
outputs (i.e. each input must connect to a large number of outputs) and delivers performance superior to most video amplifiers at a fraction of the cost. As an input buffer, the HA4600's low
input capacitance and high input resistance provide excellent
video terminations when used with an external 75n resistor.

=

Frequency Response
Most applications utilizing the HA4600 require a series output resistor, RS, to tune the response for the specific load
capacitance, CL, driven. Bandwidth and slew rate degrade

SwitcherlRouter Applications
Figure 1 illustrates one possible implementation of a wideband, low power, 4 x 4 switcher/router. A 4 x 4
switcher/router allows any of the four outputs to be driven by
anyone of the four inputs (e.g. each of the four inputs may
connect to a different output, or an input may connect to multiple outputs). This application utilizes the HA4600 for the
input buffer, the HA4404 (4 x 1 crosspoint switch) as the
switch matrix, and the HFA1112 (programmable gain buffer)
as the gain of two output driver. Figure 2 details a 16 x 1
switcher (basically a 16:1 mux) which uses the HA4600 in a
cascaded stage configuration to minimize capacitive loading
at each output node, thus increasing system bandwidth.
Power Up Considerations
No signals should be applied to the analog or digital inputs
before the power supplies are activated. Latch-up may occur
if the inputs are driven at the time of power up. To prevent
latch-up, the input currents during power up must not exceed
the values listed in the Absolute Maximum Ratings.
Harris' Crosspoint Family
Harris offers a variety of 1 x 1 and 4 x 1 crosspoint switches. In
addition to the HA4600, the 1 x 1 family includes the HA4201
which is an essentially similar device that includes a Tally output
(enable indicator). The 4 x 1 family is comprised of the HA4314,
HA4404, and HA4344. The HA4314 is a 14 lead basic 4 x 1
crosspoint. The HA4404 is a 16 lead device with Tally outputs

6-38

HA4600
to indicate the selected channel. The HA4344 is a 16 lead
crosspoint with synchronized control lines (AO, A1, CS). With
synchronization, the control information for the next channel

switch can be loaded into the crosspoint without affecting the
current state. On a subsequent clock edge the stored control
state effects the desired channel switch.
SWITCH MATRIX

10kll

SOURCEO

OUT R
HA4600
S
OUTPUT BUFFERS
(HFAll12OR HFAll15)

750
OUTO

FIGURE 1. 4

OUTl

SWITCHING MATRIX
SOURCEO

•

••
SOURCE3

OUT3

OUT2

x 4 SWITCHERIROUTER APPLICATION
OUTPUT BUFFER

ISOLATION MUX

INO
INl
IN2
IN3

TO

•••

T3

10kll

°

'w
0:r:

Rs

o(,)

~!::
(,):=

Rs
SOURCE4

••
•
SOURCE7

INO
INl

0°
wI-

•
••

IN2

T3
IN3

CZ
So
Il.

HFAll12 OR HFAl115
750

SOURCE8

INO

••
•
SOURCE11

INl

X2

IN2
IN3

T3

SOURCE12

••
•

o--'--~I;N;O::=;~
INl

1N2

OUT

+

HA4404

TO

RS
1-:.:-=--.

•

T3t---:=.:"'---I

SOURCE15 0 -....--IIN3

HA4404

FIGURE 2. 16 x 1 SWITCHER APPLICATION

6-39

HA4600

Typical Performance Curves
1.0

,

r--

0.75

E

VSUPPLY = ±5V,TA = 25°C, RL = 10kQ, Unless Otherwise Specified

0.5

1.25
1.20

Ii:" 1.15

oS

~

0.25

~

0

~

1.05

~

1.0

...~ 0.90

1/

f: 0.85

-0.5
~.75

1.10

~ 0.95

~~.25

o

ILl

u

ILl

J

\

0.80

V-

0.75

1

-1.0

10
100
FREQUENCY (MHz)

TIME (5naIDIV.)

FIGURE 4. INPUT CAPACITANCE VB FREQUENCY

FIGURE 3. LARGE SIGNAL PULSE RESPONSE

12

0.4

9

0.3

6

RS = 8211 R - 4311
CL=10pF s·)\L = 15pF-

·1111

iii" 3
:!:!.

~ ~

1111

-9

iii"

...

~
CI

~

Rs =3611
CL=21pF

0.1

0
~.1

~.3

10

750

-SO

VIN = 1Vp.p
RL = 1011

iii" -70
:!:!.
z -80
-90

~ -100

It
o

r~

J I Lilli

100

FIGURE 6. GAIN FLATNESS

-60

~

~

I_III

FREQUENCY (MHz)

FIGURE 5. FREQUENCY REPONSE

~

V
~~

-110
·120
·130
10
100
FREQUENCY (MHz)

FIGURE 7. OFF ISOLATION

6-40

500

Rs=43ll
CL =15PF

I ~I.L

1111111

~.4

10
100
FREQUENCY (MHz)

7

Rs =8211
CL-10pF
1111111

~.2

1111
I111

-12

1111
1111

0.2

-

1"'"' i\

Rs=3611./
CL = 21pF
1111
I

-6

500

1\

\
500

HA4600
Die Characteristics
DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

51 mils x 36 mils x 19 mils
1290!!m x 910!!m x 483!!m

vPASSIVATION:

METALLIZATION:

Type: Nitride
Thickness: 4kA ±O.5kA

Type: Metal 1: AICu (l%)/TiW
Thickness: Metal 1: 6kA ±O.akA

TRANSISTOR COUNT:
Type: Metal 2: AICu (1%)
Thickness: Metal 2: 16kA ±1.1 kA

53

Metallization Mask Layout
HA4600

...
EN

GND

Yo

IN

U)

'W

U)::t:

v+

~o

a::!:::

0:=

oU)
W~

OUT

...

IIA20A21A22A 5180'tAOI

6-41

...

NC

QZ

>0
a..

7
TRANSISTOR AND DIODE ARRAYS,
AND DIFFERENTIAL AMPLIFIERS

PAGE
SELECTION GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-2

TRANSISTOR AND DIODE ARRAY, AND DIFFERENTIAL AMPLIFIER DATA SHEETS

CA3018, CA3018A

General Purpose Transistor Arrays. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-5

CA3028A, CA3028B,
CA3053

DifferentiaVCascode Amplifiers for Commercial and Industrial Equipment
from DC to 120MHz ............... " . .. . . .. . .. . .. . . . . . . . . . . . . . ... . . . . . . . .. . . ...

7-6

CA3039

Diode Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-18

CA3045, CA3046

General Purpose NPN Transistor Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-22

CA3049, CA3102

Dual High Frequency Differential Amplifiers For Low Power Applications Up to 500MHz . . . . ..

7-28

CA3054

Dual Independent Differential Amp for Low Power Applications from DC to 120MHz. . . . . . . . . . . . . . . .

7-37

CA3081, CA3082

General Purpose High Current NPN Transistor Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-45

CA3083

General Purpose High Current NPN Transistor Array. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . ..

7-48

CA3086

General Purpose NPN Transistor Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-52

CA3096, CA3096A,
CA3096C

NPN/PNP Transistor Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-57

CA3127

High Frequency NPN Transistor Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-69

CA3141

High-Voltage Diode Array For Commercial, Industrial and Military Applications. . . . . . . . . . . . ..

7-75

CA3146, CA3146A,
CA3183, CA3183A

High-Voltage Transistor Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-76

CA3227, CA3246

High-Frequency NPN Transistor Arrays For Low-Power Applications
at Frequencies Up to 1.5GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-84

HFA3046, HFA3096,
HFA3127, HFA3128

Ultra High Frequency Transistor Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-89

HFA3101

Gilbert Cell UHF Transistor Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-98

HFA3102

Dual Long-Tailed Pair Transistor Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-110

7-1

Selection Guide
DIFFERENTIAL AMPLIFIERS:

TYPE
CA3028A
CA3028B
CA3049
CA3053

CA3054
CA31 02

Typical Values, Unless Otherwise Specilied
FREO.
RANGE
DC TO
(MHz)

(NOTE 4)
FEATURES

DESCRIPTION
DifferentiaV
Cascode
Amplifiers

• Balanced Differential AmplWier Conliguration with Controlled Constant
CUrrent Source
• RF,IF and Video Frequency
Capability
Dual High
• Balanced AGC Capability
Frequency
• Operation from DC to 500MHz
Differential/Cas• CA3028B is Controlled for Input
code Amplilier
Offset Voltage, Current, and Input
Bias Current, and is Intended for ''Balance" Requirements
Dual
Independent
• Push-Pull Inputs and Outputs
• CA3028 and CA3053 are Identical
Dual High
Except for 100MHz Noise
Frequency
SpecWication

BW
(3dB
VOLTAGE
GAIN
POINT)
(MHz)
(dB)

llF
NF
(dB)

AGC
RANGE
(dB)

(NOTE 5)
LEAD.CT
ANDPKG
TYPE

120

40
(Note 1)

-

7.2

62

120

40

8

7.2

62

500

22

1.35
(Note 2)

4.6

75

120

40

120

32

550
(Note 3)

3.25

75

14PDIP,
14S0lC

500

22

1.35
(Note 2)

4.6

75

14PDIP,
14S0lC

Recommended lor IF Amplilier Applications

8 PDIP,8
SOIC,
8 Metal
Can
12 Metal
Can
BPDIP,
8 Metal
Can

NOTES:
1. Power Gain (G p) Min. at 100MHz: Cascode = 16dB; Differential Amplilier = 14dB.
2. GHz.
3. IT (MHz).
4. TA Range: -55°C to 125°C except lor type CA3054 (OOC to B50C).
5. See Linear Package Selection Guide in Section 11.

TRANSISTOR ARRAYS:

TYPE
CA3045

Electrical Characteristics TA = 25°C

DESCRIPTION
Three Transistors Plus a
Differential Pair

CA3046

(NOTE 1)
LEAD COUNT AND
PACKAGE TYPE

V(BR) CEO
(MIN) V

V(BR)CBO
(MIN) V

hFE(MIN)

Ic(MAX)
mA

15

20

40

50

14CERDIP,
14SBDIP

15

20

40

50

14 PDIP, 14 SOIC

40

100

16 PDIp, 16 CERDIP,
16 SOIC (150 mil)

40

100

16 PDIP, 16 CERDIp,
16S0IC(150mll)

100

16 PDIp, 16 CERDIp,
16S0IC(150mil)

IT > 300M Hz. 2 matched pairs ±5mV

CA3081

General-Purpose NPN
High-Current Transistors

CA3082

16

20

Seven Common-Emitter
16

20

Seven Common-Collector
15

CA3083

40

20

I

Five independent transistors. 01 and O2 matched; 110 (at
lmA) 2.5~ Max
CA3086
CA3127

Three Isolated Transistors Plus a
Differential Pair
Five Independent Transistors

15

I

20

I

40

I

50

14 PDIP, 14 CERDIp,
14S0lC

20

16PDIP,
16 SOIC (150 mil)
14 PDIP, 14 SOIC

IT> 550MHz Typ Operation lrom DC to 120MHz

15

20

I

40

I

IT> 1GHz. Operation lrom DC to 500MHz

CA3146
CA3146A

Three 1l'ansistors Plus a
Differential Pair

30

40

30

50

40

50

30

50

IT> 500MHz Typ Operation lrom DC to 120MHz

7-2

Selection Guide
TRANSISTOR ARRAYS:

DESCRIPTION

TYPE
CA3183

Electrical Characteristics TA = 25°C (Continued)

V(BR) CEO
(MIN) V

V(BR) CBO
(MIN) V

hFE(MIN)

Ic(MAX)
mA

30

40

40

75

40

50

40

75

Five High-Current Transistors

CA3183A

(NOTE 1)
LEAD COUNT AND
PACKAGE TYPE
16PDIP,
16 SOIC (150 mil)

High-Voltage Versions of CA3083 Transistors
0 1 and 02 Matched at 1rnA
CA3227

Five Independent Transistors

12

B

40

20

16PDIP,
16 SOIC (150 mil)

20

14 PDIP, 14 SOIC

fT = 3GHz Typ Operation from DC to 1.5GHz
CA3246

Three Independent Transistors
Plus a Differential Pair

TYPE
CA3096
CA3096A

DESCRIPTION

12

B

40

fT = 3GHz Typ Operation from DC to 1.5GHz
V(BR) CEO
(MIN) V
NPNIPNP

Five Independent Transistors,
3 NPN, 2 PNP

CA3096C

V(BR)CBO
(MIN) V
NPNlPNP

35/-40

45/-40

150/20

501-10

35/-40

45/-40

150/20

501-10

30/-24

100/15

24/-24

HFA3096

HFA3127

HFA312B

501-10

IVlol = 5mV Max

5mV Max

"101 = 0.61lA Max

0.251lA Max

Three 8GHz NPN Transistors
Plus an NPN Differential Pair

8

Three BGHz NPN Transistors
Plus Two 5.5GHz PNP
Transistors

B

Five Independent BGHz NPN
Transistors

8

Five Independent5.5GHz PNP
Transistors

B

(NOTE 1)
LEAD COUNT AND
PACKAGE TYPE
16 PDIP,
16 SOIC (150 mil)
16PDIP

PNP

NPN

HFA3046

Ie (MAX)
NPNIPNP

hFE(MIN)
NPNlPNP

12

40

15

14S0lC

15

16 SOIC (150 mil)

15

16 SOIC (150 mil)

IVlol = 5mV Max
12110

40/25

NF = 3.5dB atlGHz
12

40

NF = 3.5dB atlGHz
10

25

15

16 SOIC (150 mil)

NF = 3.5dB at 1GHz

u.:

II..
-en
o a::

Ow
zed!:
en~

~::!:
a:: :11

II:

i~

1-1-

- r-c-

~
:::I
Z

1

-

8
!5
~
0

921

)~

1111

IIII

10
FREQUENCY (MHz)

g

III

;i

0.5

2

~

1.5

~

,

1.0

]

If'

~ :::

./ j~
",.

1

'"

~

-D.06

o

-D.08

Is;;;;.:;:

i"'oo.

;i
Ii:
~

o

~

0

1

Z

~

10

100

CASCODE CONFIGURATION
TA = 25°C, f = 10.7MHz

I

-20

5

~ 4

f= 10.7MHz

I

CI

-Vee=+9V

~ 3

~
~

~

!5

.>

~
o

2
1

~

o
o

9876543210
DC BIAS VOLTAGE ON TERMINAL NO.7 (V)
FIGURE 36. AGC CHARACTERISTICS FOR CA3028A AND
CA3028B

"",-

vee=+l~

w

I'--ot..

100MHz
0

""
~'

FIGURE 35. OUTPUT POWER vs FREQUENCY - son INPUT
AND son OUTPUT (DIFFERENTIAL AMPLIFIER
CONFIGURATION) FOR CA3028A AND CA3028B

I I I
I I I

-

I

FREQUENCY (MHz)

DIFFERENTIAL AMPLIFIER CONFIGURATION
TA = 25°C, Vee = +9V

20

,

--

~

100

FIGURE 34. OUTPUT ADMITTANCE (Y22) vs FREQUENCY
(DIFFERENTIAL AMPLIFIER CONFIGURATION)

!

~CCI=+~2~

VCC=+9V.......

FREQUENCY (MHz)

40

"

0.5 ~

III

100

DIFFERENTIAL AMPLIFIER CONFIGURATION
TA = 25°C, CONSTANT POWER INPUT = 2~W

!!!

922

10

'"
:::I

-D.04

~

JA

8

w

(J

922

FIGURE 33. OUTPUT ADMITTANCE (Y22) vs FREQUENCY
(CASCODE CONFIGURATION)

b:!2

b 0.4
z6
0.3

~

-D.02

10

III

(J

Z

o~

10
FREQUENCY (MHz)

DIFFERENTIAL AMPLIFIER CONFIGURATION,
TA = 25°C
Ie OF EACH TRANSISTOR = 2.2mA, Vee = +9V

1
W 0.6

1 ~

11

0

~

<~

l2

100

FIGURE 32. FORWARD TRANSADMITTANCE (Y21) vs
FREQUENCY (DIFFERENTIAL AMPLIFIER
CONFIGURATION)

iii'

3

11
s

C

~

-40

g
w
Z

~

-30

CASCODE CONFIGURATION, TA = 25°C
le(STAGE) = 4.5mA, Vee = +9V

iii'

(J

~

-~ "

o

19

-

II

20

8Z~

(Continued)

I

I

J V'
0.05
0.1
INPUT VOLTAGE (V)

FIGURE 37. TRANSFER CHARACTERISTICS (CASCODE
CONFIGURATION)

7-16

0.15

CA3028A,CA3028B,CA3053
Typical Performance Curves
3.0

(Continued)

r--~--~-~--~-~----,

DIFFERENTIAL AMPLIFIER CONFIGURATION
_
TA 25°C, f 10.7MHz
_.,...-----'

~

=

=

I

I

'

~
~~

2.5

!:;

/ / Vee=+9V
1.0 1------MyL...-+--+---I---+---I

o

2.0

r--- Vee = +12V,/~-t---:::::::;~;;;_;j-__--l

/ '/...-

1.5 r--+~~I-7'~-I---1r---t---I

0.5

t/

I-,-J:F-II----+--t---t--+-----I

o

0.05
0.1
INPUT VOLTAGE (V)

0.15

FIGURE 38. TRANSFER CHARACTERISTICS (DIFFERENTIAL AMPLIFIER CONFIGURATION)

Glossary of Terms
AGC Bias Current

Input Offset Voltage

The current drawn by the device from the AGC voltage
source, at maximum AGC voltage.

The difference in the DC voltages which must be applied to
the input terminals to obtain equal quiescent operating
voltages (zero output offset voltage) at the output terminals.

AGC Range
The total change in voltage gain (from maximum gain to
complete cutoff) which may be achieved by application of the
specified range of dc voltage to the AGC input terminal of
the device.
Common Mode Rejection Ratio
The ratio of the full differential voltage gain to the common
mode voltage gain.
Power Dissipation

Noise Figure
The ratio of the total noise power of the device and a
resistive signal source to the noise power of the signal
source alone, the signal source representing a generator of
zero impedance in series with the source resistance.
Power Gain
The ratio of the signal power developed at the output of the
device to the signal power applied to the input, expressed in
dB.

The total power drain of the device with no signal applied
and no external load current.

Quiescent Operating Current

Input Bias Current

The average (DC) value of the current in either output
terminal.

The average value (one half the sum) of the currents at the
two input terminals when the quiescent operating voltages at
the two output terminals are equal.
Input Offset Current
The difference in the currents at the two input terminals
when the quiescent operating voltages at the two output terminals are equal.

Voltage Gain
The ratio of the change in output voltage at either output
terminal with respect to ground, to a change in input voltage
at either input terminal with respect to ground, with the other
input terminal at AC ground.

7-17

CA3039
Diode Array

November 1996

Description

Features

The CA3039 consists of six ultra-fast, low capacitance
diodes on a common monolithic substrate. Integrated circuit
• Excellent Reverse Recovery Time ••••••••• 1 ns (Typ)
construction assures excellent static and dynamic matching
• VF Match •••••••••••••••••••••••••••• 5mV (Max) of the diodes, making the array extremely useful for a wide
variety of applications in communication and switching
)
• Low Capacitance •••••• Co = O.65pF (Typ at VR = ·2V - systems.
• Six Matched Diodes on a Common Substrate

Five of the diodes are independently accessible, the sixth
shares a common terminal with the substrate.

Applications
• Ultra-Fast Low Capacitance Matched Diodes for
Applications In Communications and Switching
Systems
• Balanced Modulators or Demodulators
• Ring Modulators
• High Speed Diode Gates

For applications such as balanced modulators or ring
modulators where capacitive balance is important, the
substrate should be returned to a DC potential which is
significantly more negative (with respect to the active diodes)
than the peak signal applied.

Ordering Information
TEMP.
RANGEfC)

PACKAGE

CA3039

-55 to 125

12 Pin Metal Can

T12.B

CA3039M

-55 to 125

14 Ld SOIC

M14.15

CA3039M96

-55 to 125

14 Ld SOIC Tape
and Reel

M14.15

• Analog Switches
PART NUMBER

PKG.
NO.

Pinouts
CA3039
(SOIC)

CA3039
(METAL CAN)
TOP VIEW

TOP VIEW

CAUTION: These devices are sensitive to electrostatiC discharge. Users should follow proper IC Handling Procedures.
Copyright @Harrls Corporation 1998

7-18

File Number

343.3

CA3039
Absolute Maximum Ratings

Thermal Information

Inverse Voltage (PIV) lor: 01 - Os ........................ SV
De ....................... 0.5V
Diode-to-Substrate Voltage (VOl) lor 01 - Os ............ 20V, -1V
(Terminal 1, 4, 5, 8 or 12 to Terminal 10)
DC Forward Current(IF) .............................. 25mA
Recurrent Forward Current (IF) ....................... 100mA
Forward Surge Current (IF(SURGE» .................... 100mA

Thermal Resistance (Typical, Note 1)
BJA (ocfW) BJC fCfW)
Metal Can Package. . . . . . . . . . . . . . .
200
120
SOIC Package.. .................
220
N/A
Maximum Power Dissipation (Any One Diode) ........... 100mW
Maximum Junction Temperature (Metal Can Package) ....... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range ......•..•.............. -55°C to 125°C

CAUTION: Stresses above those listed in "AbsOlute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those Indicated in the operational sections of this specification Is not implied.

NOTE:
1. BJA is measured with the component mounted on an evaluation PC board in free air.

Electrical SpeCifications

TA = 25°C; Characteristics apply lor each diode unit, Unless Otherwise Specified

PARAMETER
DC Forward Voltage Drop (Figure 1)

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

0.65

0.69

V

IF=1mA

-

0.73

0.78

V

IF=3mA

-

0.76

0.80

V

IF= 10mA

-

0.81

0.90

V

IF = 501lA

VF

TYP

DC Reverse Breakdown Voltage

V(BR)R

IR = -101lA

5

7

-

V

DC Reverse Breakdown Voltage Between Any
Diode Unit and Substrate

V(BR)R

IR = -101lA

20

-

-

V

DC Reverse (Leakage) Current (Figure 2)

IR

VR=-4V

-

0.016

100

nA

DC Reverse (Leakage) Current Between Any
Diode Unit and Substrate (Figure 3)

IR

VR=-10V

-

0.022

100

nA

IV F1 -V F2 1

IF=1mA

-

0.5

5.0

mV

1.0

-

p.vfOC

Magnitude of Diode Offset Voltage (Note 2)
(Figure 1)
Temperature Coefficient of IVF1 - VF21 (Figure 4)

Temperature Coefficient of Forward Drop
(Figure 5)

DC Forward Voltage Drop for Anode-toSubstrate Diode (OS)

A!VF1- VF2 1
AT
AV F

IF= 1mA

IF= 1mA

-

-1.9

IF=1mA

-

0.65

-

V

-

1.0

-

ns

25

30

45

n

0.65

-

pF

3.2

-

pF

mVfOC

aT
VF

Reverse Recovery Time

tRR

IF = 10mA, IR = -10mA

Diode ReSistance (Figure 6)

Ro

f= 1kHz, IF = 1mA

Diode Capacitance (Figure 7)

CD

VR = -2V, IF = 0

Diode-to-Substrate CapaCitance (Figure 8)

COl

VOl = 4V, IF = 0

-

NOTE:
2. Magnitude of Diode Offset Voltage is the difference in DC Forward Voltage Drops of any two diode units.

7-19

CA3039

Typical Performance Curves
10
VR=-4V

TA=2S0 C

0.8
r-lOJARD VOLTAGE DROP (VF)

6

,,~

~

~

.... io'

r--

8

~
DIODE OFFSET QVF1-VF211

I

IJ I

0.5
0.01

li~

I

,

1
~
a:

I

0
25
50
TEMPERATURE (DC)

75

125

~

-'

l.---

IF='0mA

3

I

2

~

0.7

0.6

0.1

~

IF=lmA
0.5

./

g 0.01

100

FIGURE 2. DC REVERSE (LEAKAGE) CURRENT (D, • DS) V8
TEMPERATURE

>u.

-'!."

8

·25

.. .-

-'

10

·50

4

,

VR=·10V

---·75

10

FIGURE 1. DC FORWARD VOLTAGE DROP (ANY DIODE) AND
DIODE OFFSET VOLTAGE V8 DC FORWARD
CURRENT

100

../

0.001

o

0.1
1
DC FORWARD CURRENT (mA)

0.1

~
~
a: 0.01
g

IJ

"

/

a:

"", ioo""'"

~

/

~

./

0.4

......

-

V
./

IF = O.lmA

0.3

0.001
·75

-60

·25

0
25
50
TEMPERATURE (DC)

75

100

125

·75

·50

·25

0
25
50
TEMPERATURE (DC)

75

100

125

FIGURE 4. DIODE OFFSET VOLTAGE (ANY DIODE) V8
TEMPERATURE

FIGURE 3. DC REVERSE (LEAKAGE) CURRENT BETWEEN D,.
D2. D3. D4. D5 AND SUBSTRATE VI TEMPERATURE

1000
IF='mA

0.9

TA=250 C 'f = 1kHz

............

>' 0.8
;;j

~

..... .....

~ 0.7

i

~'00

~ ........

0.6

"'"......

~

f"".. ...........

Q

f2
g

g

m
............

III

~

"'"
r--....

10

r--.....

0.5

1
0.01

0.4
·75

-60

·25

0
25
50
TEMPERATURE (DC)

75

100

125

0.1

1

DC FORWARD CURRENT (mAl

FIGURE 5. DC FORWARD VOLTAGE DROP (ANY DIODE) V8
TEMPERATURE

FIGURE 6. DIODE RESISTANCE (ANY DIODE) V8 DC
FORWARD CURRENT

7·20

10

CA3039
Typical Performance Curves

(Continued)

6 r--------r--------~--------r_------_,
TA= 2SoC

TA =2SoC
IF=O

IF=O

~5f--------+--------+---------f--------j
~
z
~
o

~

o

~

4 f_------_+--------+_--------f_------_j
3 f_------_+--------+_--------f_------_j

I!j
~

----

2

o

2
2

3

4

3

4

DC REVERSE VOLTAGE BETWEEN TERMINALS 1, 4, 5, 8, OR 12
AND SUBSTRATE (TERMINAL 10) (V)

DC REVERSE VOLTAGE ACROSS DIODE (V)

FIGURE 8. DIODE-TO-SUBSTRATE CAPACITANCE VB
REVERSE VOLTAGE

FIGURE 7. DIODE CAPACITANCE (01 - 05) VB REVERSE
VOLTAGE

7-21

CA3045, CA3046
General Purpose NPN
Transistor Arrays

November 1996

Features

Description

• Two Matched Transistors
- VBE Match ••••.••..••••••••....•..•••••• ±5mV
- 110 Match. • . • • • • • . . • • . . . • . • • • . • • . . •• 2~A (Max)
• Low Noise Figure •...•.••••.•.. 3.2dB (Typ) at 1kHz

The CA3045 and CA3046 each consist of five general
purpose silicon NPN transistors on a common monolithic
substrate. Two of the transistors are internally connected to
form a differentially connected pair.
The transistors of the CA3045 and CA3046 are well suited to
a wide variely of applications in low power systems in the DC
through VHF range. They may be used as discrete transis·
tors in conventional circuits. However, in addition, they
provide the very significant inherent integrated circuit
advantages of close electrical and thermal matching.

• 5 General Purpose Monolithic Transistors
• Operation From DC to 120MHz
• Wide Operating Current Range
• Full Military Temperature Range

Ordering Information

Applications
• Three Isolated Transistors and One Differentially
Connected Transistor Pair for Low Power Applications
at Frequencies from DC Through the VHF Rang'e
• Custom Designed Differential Amplifiers
• Temperature Compensated Amplifiers
• See Application Note, AN5296 "Application of the
CA3018 Integrated-Circuit Transistor Array" for
Suggested Applications

PART NUMBER
(BRAND)

TEMP.
RANGEfC)

PACKAGE

PKG.
NO.

CA3045

·55 to 125

14LdSBOIP

014.3

CA3045F

·55 to 125

14 LdCEROIP

F14.3

CA3046

·55 to 125

14Ld POIP

E14.3

CA3046M
(3046)

·55 to 125

14LdSOlC

M14.15

CA3046M96
(3046)

·55 to 125

14 Ld SOIC Tape
and Reel

M14.15

Pinout
CA3045, (CERDIP, SBDIP)
CA3046 (POIP, SOIC)
TOP VIEW

DIFFERENTIAL
PAIR

11

CAUTION: These devices are sensUIve to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation t 996

7·22

File Number

341.3

CA3045, CA3046
Absolute Maximum Ratings

Thermal Information

Coliector-to-EmitterVoltage (VCEO) ...................... 15V
Collector-to-Base Voltage (VCBO) ....................... 20V
Collector-to-Substrate Voltage (VeIO, Note 1) .............. 20V
Emitter-to-Base Voltage (VEBO)' ......................... 5V
Collector Current (Ic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. SOmA

Thermal Resistance (Typical, Note 2)
BJA (oC/W) BJC (oC/W)
180
N/A
PDIP Package.......... .... .....
CERDIP Package. . . . . . . . . . . . . . . .
150
75
125
60
SBDIP Package............. .....
SOIC Package. . . . . . . . . . . . . . . . . . .
220
N/A
Maximum Power Dissipation (Any One Transistor) ........ 300mW
Maximum Junction Temperature (Hermetic Packages) ....... 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range .. . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering 1Os). . . . . . . . . . .. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range ........................ -55°C to 125°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. The collector of each transistor of the CA3045 and CA3046 is isolated from the substrate by an integral diode. The substrate (Terminal
13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal
transistor action.
2. BJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

TA = 25°C, characteristics apply for each transistor in CA3045 and CA3046 as specified

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DC CHARACTERISTICS
V(BR)CBO

Ic = lOIlA, IE = 0

20

60

Collector-to-Emitter Breakdown Voltage

V(BR)CEO

IC = lmA, IB= 0

15

24

Collector-to-Substrate Breakdown Voltage

V(BR)CIO

IC = lOIlA, ICI = 0

20

60

V(BR)EBO

IE = 101lA, Ic = 0

5

Collector Cutoff Current (Figure 1)

ICBO

VCB= 10V, IE=O

Collector Cutoff Current (Figure 2)

ICEO

VCE=10V,IB=0

Collector-to-Base Breakdown Voltage

Emitter-to-Base Breakdown Voltage

Forward Current Transfer Ratio (Static Beta)
(Note 3) (Figure 3)

hFE

VCE=3V

Base-to-Emitter Voltage (Note 3) (Figure 5)

See Fig. 2

0.5

I1A

le=10mA

100

-

le=1mA

40

100

-

54

-

-

0.3

2

I1A

0.800
0.45

5

mV

VCE = 3V, Ic = 1mA

0.45

5

mV

VeE = 3V, Ic = 1mA

-1.9

mVPC

IB= 1mA, Ic= 10mA

0.23

V

VCE = 3V. Ic = lmA

1.1

IE= 1mA

Magnitude of Input Offset Voltage for Isolated
Transistors IVBE3 - VBE41, IVBE4 - VBESI,
IVBES - VBE31 (Note 3) (Figures 5, 7)

VeES

Temperature Coefficient: Magnitude of Input
Offset Voltage (Figure 7)

IAVlol

-

0.715

V
V

AT

""'AT

7-23

-

u..:

II..

-rJ)

-

VCE=3V

IE= 10mA

Collector-to-Emitter Saturation Voltage

V
nA

VCE = 3V, Ic = lmA

AV BE

V

40

Magnitude of Input Offet Voltage for Differential
Pair IVBEl - VBE21 (Note 3) (Figures 5, 7)

Temperature Coefficient of Base-to-Emitter
Voltage (Figure 6)

7
0.002

VCE = 3V, Ic = lmA

VBE

V

-

le=101lA
Input Offset Current for Matched Pair 01 and
02' 11101 - 11021 (Note 3) (Figure 4)

V

-

IlVPC

Ca:

Cw

z-

ed!:

rJ)...I

a..
~==
a:<
a:

<

CA3045, CA3046
Electrical Specifications

TA = 25°C, characte.ristics apply for each transistor in CA3045 and CA3046 as specified (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

NF

f= 1kHz, VCE=3V,lc= 100lJA,
Source Resistance", lill

-

3.25

-

dB

Forward Current Transfer Ratio (Figure 11)

hFE

f= 1kHz, VCE=3V,lc= lmA

-

110

-

Short Circuit Input Impedance (Figure 11)

DYNAMIC CHARACTERISTICS
low Frequency Noise Figure (Figure 9)

low Frequency, Small Signal Equivalent
Circuit Characteristics

hiE

f= 1kHz, VCE=3V,lc= lmA

-

3.5

Open Circuit Output Impedance (Figure 11)

hOE

f = 1kHz, VCE = 3V, Ic = lmA

-

15.6

Open Circuit Reverse Voltage Transfer
Ratio (Agure 11)

hRE

f = 1kHz, VCE = 3V, Ic = lmA

-

1.8xl0-4

Forward Transfer Admittance (Figure 12)

VFE

f= 1kHz, VCE=3V,lc= lmA

Input Admittance (Figure 13)

VIE

f = 1kHz, VCE = 3V, Ic = lmA

Output Admittance (Figure 14)

VOE
VRE

kQ

-

!!S

-

Admittance Characteristics

Reverse Transfer Admittance (Figure 15)
Gain Bandwidth Product (Figure 16)

IT

f = 1kHz, VCE = 3V, Ic = lmA

-

0.001 + ]0.03

f= 1kHz, VCE=3V,lc= lmA

-

See Ag.14

-

-

300

550

-

MHz

-

0.6

-

pF

VCE = 3V, IC = 3mA

Emitter-to-Base Capacitance

CEe

VEe = 3V, IE = 0

Collector-to-Base Capacitance

Cce

Vce = 3V, Ic = 0

Collector-ta-Substrate Capacitance

CCI

Vcs=3V,lc=0

31 - ]1.5
0.3 + ]0.04

-

2.8

-

VCE= 10V

,.

0.58

-

pF
pF

NOTE:
3. Actual forcing current is via the emitter for this test.

Typical Performance Curves
102

.s
!Zw

103
IE=O

;(

I

10

Vcs=5V ~

u

~
U

.s
!Zw

/'/.
"It.~

.,

a::
a::
:;)

102
10

......
U

10-1

VCE=5V

12

:;)

a::

10-2

....
....

10~

§w

I

Vcs= 15V
Vcs = 10V

a::
a::
:;)

It:

IS=O

;(

if;

u
~

a::

10-1

....
....

10-2

§w

~ foo""

'"

II

0

0

u

u

10~

25

50
75
TEMPERATURE (DC)

100

125

FIGURE 1. TYPICALCOLLECTOR-TO-BASE CUTOFF CURRENT
vs TEMPERATURE FOR EACH TRANSISTOR

7-24

o

25

50
75
TEMPERATURE (DC)

100

FIGURE 2. TYPICAL COLLECTOR-TO-EMITTER CUTOFF
CURRENT vs TEMPERATURE FOR EACH
TRANSISTOR

125

CA3045, CA3046

Typical Performance Curves

(Continued)

120

...

1.1
VCE =3V
TA = 25DC

110

ffiUi
II: "-

11::5.

hFE

!i!~

90

iffi

80

U~

70

...0'"~

~

l/

100

512

10

1

".
~

--~

!zIII

1.0

'I
I

12

II:
II:

II:

u

~

IhFE110RlhFE21
hFE2
hFEl

t)

......
...::>

III

V

/

1.0
J'

".

Iiiu;

0.9 ~

0

60

,J

l..I

::>

ID

Ii ...

VCE =3V
TA = 25DC

/"""

0.1

"-

~

0.8

50
0.01

0.1
1.0
EMITTER CURRENT (mA)

1...-i"""'"
0.01
0.01

10

.....
0.1
1.0
COLLECTOR CURRENT (mA)

10

FIGURE 4. TYPICAL INPUT OFFSET CURRENT FOR
MATCHED TRANSISTOR PAIR Q1Q2 vs
COLLECTOR CURRENT

FIGURE 3. TYPICAL STATIC FORWARD CURRENT TRANSFER
RATIO AND BETA RATIO FOR Ql AND Q2 vs
EMITTER CURRENT
0.8
VCE=3V
TA = 25DC

"..

~
III

I

0.7

CJ

~

~~

3

:;E,.,.

g
II:

0.6

~

~

~""

~

'I'

g
III

0.5
INPUT OFFSET VOLTAGE

~

g

"

0.1
1.0
EMmER CURRENT (mA)

g~
~

CJ

2 ~

1

./'f"

1 I

0.4
0.01

~

~

III

I

:i

o

1.0

f--II--t--t--+--+-+-+-+--i

0.9

f--:df--t--t--+--+-+-+-+--i

0.8

f--IF""';;;S~"",",,::::--+--+-+-+-+--i

0.7

f--If--t--It-1ll.oo!""'::!Iojo.o;;::-+-+-+--i

~

~

:i

~

~

6

0.6

I-;"
UJ

~

0.5
0.4 '----''----1_--1_--'"_-'-_--'-_--'-_-'-_-"
-75
-50
-25
0
25
50
75
100 125
TEMPERATURE (DC)

10

FIGURE 6. TYPICAL BASE-TO-EMITTER VOLTAGE
CHARACTERISTIC vs TEMPERATURE FOR EACH
TRANSISTOR

FIGURE 5. TYPICAL STATIC BASE-TO-EMITTER VOLTAGE
CHARACTERISTICS AND INPUT OFFSET VOLTAGE
FOR DIFFERENTIAL PAIR AND PAIRED ISOLATED
TRANSISTORS vs EMITTER CURRENT
VCE=3V
4.00

~
III

!i
!:l
g
Iii

...0

If

5"-

IE'=10m~

-

3.00
2.00

----

20

",;
f=O.lkHz "'
I

S-

III

::>

0.75
IE=lmA

0.50
0.25

IE=O.lmA

o

I I

~

-75

-SO

-25

0
25
50
75
TEMPERATURE (DC)

!i!

~

~

III

u;

0z

100

10

5

o

125

0.01

FlGURE7. TYPICALINPUTOFFSETVDLTAGE CHARACTERISTICS
FOR DlFFEREN11AL PAIR AND PAIRED
ISOLATED TRANSISTORS vs TEMPERATURE

I = 10kHz

./

I

l=tHzI"-

II:

r--,,,,/

>

/'

~~ ~V.....

0.1
COLLECTOR CURRENT (mA)

;
;'

1.0

FIGURE 8. TYPICAL NOISE FIGURE vs COLLECTOR CURRENT

7-25

Ocr
Ow
z-

V

.(
'" 

bR~~

-0.5
-1.0

~
a.
:r
z

C
In

-1.5

CI

-2.0

1

10
FREQUENCY (MHz)

600

400

fI'

""'"

1

2

I

300

100
o

100

FIGURE 15. TYPICAL REVERSE TRANSFER ADMITTANCE vs
FREQUENCY

veE =3V
TA = 25°C

3

4 5 6 7 8 9 10 11
COLLECTOR CURRENT (mA)

12 13 14

FIGURE 16. TYPICAL GAIN BANDWIDTH PRODUCT vs
COLLECTOR CURRENT

u:
u.
-en
0a:
Ow
z«!:!:
en..J
Il.
~~

a:«
a:

«

7-27

CA3049, CA3102
Dual High Frequency Differential Amplifiers
For Low Power Applications Up to 500MHz

November 1996

Features

Description

• Power Gain 23dB (Typ) ................... 200MHz

The CA3049T and CA3102 consist of two independent
differential amplifiers with associated constant current
transistors on a common monolithic substrate. The six transistors which comprise the amplifiers are general purpose
devices which exhibit low 11f noise and a value of IT in
excess of 1GHz. These feature make the CA3049T and
CA3102 useful from DC to 500MHz. Bias and load resistors
have been omitted to provide maximum application flexibility.

• Noise Figure 4.6dB (Typ) ••••••••••••••.•.• 200MHz

• Two Differential Amplifiers on a Common Substrate
• Independently Accessible Inputs and Outputs
• Full Military Temperature Range ••••• -55°C to 125°C

Applications
• VHF AmplHiers
• VHF Mixers
• Multifunction Combinations - RFlMlxer/Oscillator;
ConverternF
• IF Amplifiers (Differential and/or Cascode)

The monolithic construction of the CA3049T and CA31 02
provides close electrical and thermal matching of ~he
amplifiers. This feature makes these devices particularly
useful in dual channel applications where matched
performance of the two channels is required.
The CA3102 is like the CA3049T except that it has a
separate substrate connection for greater design flexibility.
Formerly Developmental Type No. TA6228.

• Product Detectors
• Doubly Balanced Modulators and Demodulators

Ordering Information
PART NUMBER
(BRAND)

• Balanced Quadrature Detectors
• Cascade Limiters

TEMP.
RANGEfC)

PACKAGE

PKG.
NO.

CA3049T

-55 to 125

12 Pin Metal Can

TI2.B

• Synchronous Detectors

CA3102E

-55 to 125

14 Ld PDIP

E14.3

• Balanced Mixers

CA3102M
(3102)

-55 to 125

14 Ld SOIC

M14.15

CA3102M96
(3102)

-55 to 125

14 Ld SOIC Tape
and Reel

M14.15

• Synthesizers
• Balanced (Push-Pull) Cascode Amplifiers
• Sense AmplHiers

Pinouts
CA31 02
(PDIP, SOIC)
TOP VIEW

CA3049
(METAL CAN)
TOP VIEW

SUBSTRATE
AND CASE

CAUTION: These devices are sensitive to electrostatiC discharge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporation 1996

7-28

File Number

611.3

CA3049, CA3102
Absolute Maximum Ratings

Thermal Information

Collector-to-Emitter Voltage, V CEO ...................... 15V
Collector-te-Base Voltage, VCBO ......................•. 20V
Collector-to-Substrate Voltage, VCIO (Note 1) .............. 20V
Emltter-to-Base Voltage, VEBO .......................... 5V
Collector Current, IC' .....•.......................... 50mA

Thermal Resistance (Typical, Note 2)

Operating Conditions
Temperature Range ................•........ -55°C to 125°C

9JA (,CIW)

Metal Can Package. . . . . . • • . • . . . . . . . • . . . . . . .
225
PDIP Package...................... .....••
130
140
SOIC Package. . . . . . . . . . . . . . . . . • . . . . . . . . . . •
Maximum Power Dissipation (Any One Transistor) ..•..... 300mW
Maximum Junction Temperature (Can Package) ............ 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ..•...... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) .........•... 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the davies. This is a stress only raUng and operation
of the device at these or any other condlt/ons above those Indfcated in the oparational sections of this speclflcaffon Is not Implied.

NOTES:
1. The collector of each transistor of the CA3049T and CA31 02 is isolated from the substrate by an integral diode. The substrate (Terminal 9)
must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal
transistor action.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

PARAMETER

TA = 25°C
TEST
CONDlllONS

SYMBOL

I
I

MIN

TYP

I
I MAX I

MIN

TYP

-

0.25

5.0

-

0.25

-

CA31 02

CA3049
MAX

I
I UNIT

DC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
Input Offset Voltage
(Figures 1, 4)

VIO

Input Offset Current (Figure 1)

110

Input Bias Current (Figures 1, 5)

IB

Temperature Coefficient
Magnitude of Input Offset
Voltage

-

13=lg=2mA

-

I,Wlol

0.3

3.0

13.5

33

1.1

-

-

774

874

-

mV

0.3

-

13.5

33

IlA
IlA

1.1

-

JLVf'C

774

-

mV

~

DC CHARACTERISTICS FOR EACH TRANSISTOR
DC Forward Base-to-Emitter
Voltage (Figure 6)
Temperature Coefficient of
Base-to-Emitter Voltage
(Figure 6)
Collector Cutoff Current
(Figure 7)
Collector-to-Emitter Breakdown
Voltage

VBE

AV BE

VCE = 6V, Ic = lmA

674

-

VCE = 6V, Ic = lmA

-0.9

-

0.0013

100

-U)

-0.9

-

mVf'c

-

0.0013

100

nA

15

24

--:IT""
ICBO

VCB = 10V, IE = 0

V(BR)CEO Ic= lmA, IB=O

24

Collector-to-Base Breakdown
Voltage

V(BR)CBO IC = 101lA, IE = 0

20

60

-

20

60

Collector-te-Substrate
Breakdown Voltage

V(BR)CIO

20

60

-

20

60

Emitter-to-Base Breakdown
Voltage

V(BR)EBO Ie = 101lA, Ic = 0

5

7

5

7

-

V

V

1.5

-

dB

1.35

-

GHz

-

V
V

DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER

lit Noise Figure (For Single
Transistor) (Figure 12)

NF

f = 100kHz, RS = 5000.
Ic = lmA

Gain Bandwidth Product (For
Single Transistor) (Figure 11)

fT

Vee = 6V, Ic = 5mA

Collector-Base Capacitance
(Figure 8)

CeB

Collector-Substrate
CapaCitance (Figure B)

CCI

le=O,
Vce=5V

1.5

-

INote 3
I Note 4

1.35
0.28

-

0.15
1.65

IC = 0, VCI = 5V

7-29

-

-

-

~:i

a:c(

15

IC = 101lA, IB = Ie = 0

u::
LL

Ca:
Cw
zc(!!::
cn~

0.28
0.28
1.65

-

pF
pF
pF

!;i

CA3049, CA3102
Electrical Specifications

TA'= 25°C (Continued)

PARAMETER

SYMBOL

Common Mode Rejection Ratio

CMRR

AGC Range, One Stage
(Figure 2)

AGC

Voltage Gain, Single-Ended
Output (Figures 2, 9, 10)

A

Insertion Power Gain (Figure 3)

Gp

Noise Figure (Figure 3)

NF

Input Admittance

Yll

Reverse Transfer Admittance

Forward Transfer
Admittance

Y12

Y21

TEST
CONDlnONS

Y22

CA3049

TYP

MAX

MIN

TYP

13= Ig=2mA

100

-

-

100

Bias Voltage = -6V

75

Bias Voltage = -4.2V,
f= 10MHz
Cascode
Vcc= 12V,
ForCascode Cascode
Configuration
13=lg=2mA. Cascode (FigFor DIf!. Amp. ures 14, 16, 18)
Configuration DIff. Amp. (Fig13=lg=4mA urea 15, 17, 19)
(Each
Cascode
Collector
Ic=2mA)
f=200MHz
Diff.Amp.
Cascode (Figures 26, 28, 30)
DIf!. Amp. (Figures 27, 29, 31)

Output Admittance

CA31 02
MIN

18

22

-

4.6

23

1.5+
]2.45

-

0.878+
jl.3
0.0jO.008
0.0jO.013
17.9j30.7
-10.5+
j13

Cascode (Figures 20, 22, 24)

-

-0.503
-j15

DIf!. Amp. (Figures 21, 23, 25)

-

0.071+
jO.62

75

-

-

-

22

-

-

4.6

-

-

-

-

-

-

-

-

-

MAX

23

1.5 +
]2.45
0.878+
jl.3
0.0jO.008
0.0jO.013
17.9j30.7
-10.5+
j13
-0.503
-j15
0.071+
jO.62

dB

-

mS

-

mS

-

mS.

0

mS

-

mS

-

mS

-

mS

4. Terminals 13 and 4 or 6 and 11 (CA31 02). Terminals 10 and 11 or 4 and 5 (CA3049T).

Schematic Diagrams
CA3049T

SUBSTRATE
AND CASE

7-30

dB

mS

3. Terminals 1 and 14 or 7 and 8 (CA3102). Terminals 1 and 12 or 6 and 7 (CA3049T).

SUBSTRATE

dB

-

NOTES:

CA3102E, CA3102M

UNIT

dB
dB

CA3049, CA3102

Test Circuits
+6V
V+(+6V)

V-(.flV)

.flV

FIGURE 2. AGC RANGE AND VOLTAGE GAIN TEST CIRCUIT
FORCA3102

FIGURE 1. DC CHARACTERISTICS TEST CIRCUIT FOR CA3102

1I2CA3049T

orCA3102
p----------------------,

12(6)

....-~~":T"""-___,

u:
u.

-U)

00::

Ow
zed!:
U)~

11 (5)
[13(8)]
5.8pF
RoI~~:Q; ~I-""

~:z

_ _ _...J

o::c(

~

0::

c(

L,

O.OOl I1F NOTES:
100pF

-

1-

Fi~~--

=

470pF
10kn

+12V

100pF

1-

-

1-

5. Numbers in parentheses refer to other
half of the CA3049T or CA31 02.
6. BIacketed numbers referto CA31 02,
unbracketed numbers refer to CA3049T.
7. L1, L2· Approximately 1/2 Tum #lS
Tinned Copper Wire, 518" Diameter.
S. C1, C2 • 15pF Variable capacitors
(Hamma~und, MAC·15; or Equivalent).

O.OOll1f ~

FIGURE 3. 200M Hz CASCODE POWER GAIN AND NOISE FIGURE TEST CIRCUIT

7-31

CA3049, CA3102

Typical Performance Curves

...., ... ..

100

0.5
TA=250C

:;-

lIP'"

.§.
w
CJ

~

0.4

,

~

IiiIII

......
0

~ P""

0.3

~~

!(

::>

II.

ii!l:

.....4 JiP"'"

~

............ ""'-

I-

0.1
0.1

10

1

FIGURE 4. INPUT OFFSET VOLTAGE VB EMITTER CURRENT

~

!j

~
a:

~

0.9
0.8

I?w
III

i1i

0.7

= 25°C
TA= -40°C

zw
a:
a:

100

u

::>

==.
'~.'".
VCB=10V~

VCB=5V

......

~ !-"

......

10

I,...000o-

""'"

u

1.0

f---

~

1---

I-

r--'

t

I-

:Ii

III

~

a:

~

1---~
0.6

w

....
....

0.1

8
0.5
0.1

1.0
COLLECTOR CURRENT (mA)

0.01
-100

10

-75

·50

-

~v

-25
0
25
TEMPERATURE rC)

50

75

100

FIGURE 7. COLLECTOR CUTOFF CURRENT VB TEMPERATURE

FIGURE 6. BASE-TO-EMITTER VOLTAGE VB COLLECTOR
CURRENT

70

3
TA=250C

50

....

iii

......
I""'- '-

Ccl

-

I--

30

~

20

CJ

w

CJ

TERMINALS 14 AND 1; 7 AND 8
/ TERMINALS 13 AND 4; 6 AND 11

L

I
1

2

3

4

5
6 7 8 9
BIAS VOLTAGE (V)

I

I,t-

CCB

10 11

I--

40

:!!.

~

o

TA = 25°C
V+=6V, V-=-6V
f = 1kHz

80

\.

o

10

FIGURE 5. INPUT BIAS CURRENT VB EMITTER CURRENT

i

\".* " ---- --\

I--

1000

I I II I

1.0

TA = 85°C

1.0
EMITTER CURRENT (mA)

EMITTER CURRENT (mA)

w

I-I--

.. V

0.2
0.1

E

~ ~\.TATA=-4OoC
= 25°C

~

--...

10
.0
-10

\

-20

I

-30
·40

I--

12 13

-so
14

"'" !,

o

-1

"

-2
·3
-4
-S
-8
BIAS VOLTAGE ON TERMINALS 2 AND 10 (V)

FIGURE 9. VOLTAGE GAIN vs DC BIAS VOLTAGE

FIGURE 8. CAPACITANCE VB DC BIAS VOLTAGE

7-32

-7

CA3049, CA3102

Typical Performance Curves

(Continued)
2.0

40
TA=250C

35

"N

:cCI
1;i
!:l

1"0..

1.7

c

1.6

II:

1.5

~

1.4

II.

\.

15

~

t;

:::)

0

20

w

1.8

e.

30

iii'
E. 25
z

1.2

~

~
CI

o

0.01

0.1

1.0
FREQUENCY (MHz)

FIGURE 10. VOLTAGE GAIN

TA = 25°C
RSOURCE = 500n

30

0.9

0.8

va FREQUENCY

...... 10...

/

1.0

100

10

,

1.1

ID

5

TA = 25°C

1.3

~

1\

10

1.9

::c

o

2

3

4 5 6 7 8
9 10 11 12 13 14
COLLECTOR CURRENT (mA)

FIGURE 11. GAIN BANDWIDTH PRODUCT va COLLECTOR
CURRENT

f = 10Hz

TA = 25°C
RSOURCE=lkG -r---f--~~~~--

30

iii'
E.

i

20

w

!!!

~

o~~~
0.01

0.1
1.0
COLLECTOR CURRENT (mA)

25
CASCODE AMPLIFIER
Vcc=12V
13=lg=2mA
TA-250C

iii"

~

2.0

.§
~

1.5

"5

8
~

t-- -

1.0

0.5

I
I

20

10

0.01

0.1
1.0
COLLECTOR CURRENT (mA)

6

DIFFERENTIAL AMPLIFIER
VCC=12V
13=lg=4mA
TA = 25°C

.s

S-

~

io""""
~

911

IS ~

,

z

~

I~

10 ~
UI

:::)

UI

., ~

I

o

o~--~~--~~--~--~~~--~--~

iii"

I

~

~--+---+--r-b""~+----I-~"'I~+-::'~-I----l

FIGURE 13. 11f NOISE FIGURE va COLLECTOR CURRENT

FIGURE 12. 11f NOISE FIGURE va COLLECTOR CURRENT

2.5

10

bl1

102

~

5

~

o

o

103

10

FREQUENCY (MHz)

102

,

-

./

!:

,/

b11

III

9
." i-o' 1r1

II

FREQUENCY (MHz)

FIGURE 14. INPUT ADMITTANCE (Y11) va FREQUENCY

FIGURE 15. INPUT ADMITTANCE (Yll) va FREQUENCY

7-33

CA3049, CA3102

Typical Performance Curves

CASCODE AMPLIFIER
~ .. 1g=2rnA
t .. 200MHz
TA" 2S"C

3

o

(Continued)

,.

I""'-

bll

-

r-

911

DIFFEREN11AL AMPLIFIER
13 =IS =4rnA
t .. 200MHz
TA"ZSOC

3

,

-o

o

10
20
30
COLLECTOR SUPPLV VOLTAGE (V)

40

FIGURE 16. INPUT ADMITTANCE (V11) VB COLLECTOR SUPPLV
VOLTAGE

o

CASCODE AMPLIFIER
VCC· I2V
t=200MHz
TA=250C

b'l~ ~
.... "1
911

o

./

A'
o

V-

10
20
30
COLLECTOR SUPPLY VOLTAGE (V)

DIFFEREN11AL AMPLIFIER
Vcc=12V
f=200MHz
TA=250C

3

911

- -

~

-

I-- ~

2
4
6
EMITTER CURRENT (13 OR Is) (mA)

40

FIGURE 17. INPUT ADMmANCE (V11) vs COLLECTOR SUPPLV
VOLTAGE

7
6

b"

9"

V
f V
o

8

FIGURE 18. INPUT ADMITTANCE (V11) vs EMITTER CURRENT

- ' """"'"

""...". ~
JIll"'"

P"""'"

b'l

/
o

5
10
15
EMITTER CURRENT (13 OR Ie) (mA)

20

FIGURE 19. INPUT ADMITTANCE (V11) vs EMITTER CURRENT

3

4

CASCODE AMPLIFIER
Vcc=12V
13=ls=2mA
TA= ZSOC

2

DIFFERENTIAL AMPLIFIER
Vcc = 12V
13=ls=4mA
TA=250C

'

......

bu

""""

922

--

~

~

"\

oS
-6

10

-2

102

10

~bu

~

i"'-

102

I'"

~

ii

FREQUENCY (MHz)

FREQUENCY (MHz)
FIGURE 20. OUTPUT ADMITTANCE (V22) vs FREQUENCV

FIGURE 21. OUTPUT ADMITTANCE (V22) vs FREQUENCV

7-34

CA3049, CA3102

Typical Performance Curves

CASCODE AMPLIFIER
13=lg=2mA
f =200MHz
TA = 25°C

0

~
om

,,-

w~

(Continued)

g22

DIFFERENTIAL AMPLIFIER
13=lg=4mA
f=200MHz
TA = 25°C

0.6
1b22

zE ·1

e~

:::oz

j~

Ow

00

,/

·2

Srn

~ii:

,

b22

f---

0

·3

o

o

10
20
30
COllECTOR SUPPLY VOLTAGE (V)

40

FIGURE 22. OUTPUT ADMITTANCE (Y22) vs COL.L.ECTOR
SUPPL.Y VOL.TAGE

_g22

o

30
10
20
COLLECTOR SUPPLY VOLTAGE (V)

40

FIGURE 23. OUTPUT ADMITTANCE (Y22) VB COL.L.ECTOR
SUPPL.Y VOL.TAGE

CASCODE AMPLIFIER
Vee =12V
f=200MHz
TA = 25°C

DIFFERENTIAL AMPLIFIER
Vee=12V
f=200MHz
TA = 25°C

g22

-

\ V"
~

b22
g22

~

/

I
o

·1

2

4

6

8

o

5

10
15
EMITTER CURRENT (13 OR Ig) (mA)

EMmER CURRENT (13 OR Ig) (mA)

20

FIGURE 24. OUTPUT ADMmANCE (Y22) VB EMmER CURRENT

FIGURE 25. OUTPUT ADMITTANCE (Y22) VB EMITTER CURRENT

iii' 70

w

50

.5.

CASCODE AMPLIFIER
VCC=12V
13=lg=2mA

w 60
o
z

e

50

g21...

~

40

8

30

m20
0

i

·10

~

0-20
IL

1~11
10

e~

30
20

a: Z

10

~~

0

8~

" """

40

5'tl
z-

TA=2SoC

H!~

DIFFERENTIAL AMPLIFIER
Vee = 12V
1a=lg=4mA
TA = 25°C
~1

~!!l .10
I-rn

'-

~ 10

I!:

~

~

ca:

!i0

~

~

·20

---

~

...

III
g21

-30
-40

102
FREQUENCY (MHz)

RGURE 26. FORWARD TRANSFER ADMITTANCE (Y21) VB
FREQUENCY

10

102
FREQUENCY (MHz)

FIGURE 27. FORWARD TRANSFER ADMITTANCE (Y21) VB
FREQUENCY

7·35

CA3049, CA3102

Typical Performance Curves

0
Z

W

20

:::>111
cE

e~

10

921

L
I

i>:!1

CASCODE AMPLIFIER
13=lg=2mA
1=200MHz
TA = 25°C

0

Il!~
IIIW

ZO ·10
CIII
a::::>
~III
ca:
a:o ·20

i~

20

I

Z~

OW
00
a: Z

(Continued)

DIFFERENTIAL AMPLIFIER
13=la=4mA
1=200MHz
TA=2SoC

I

J

·30

o

-

921

b21
·15
5

10
15
20
25
COLLECTOR SUPPLY VOLTAGE (V)

30

35

40

W

30

:::>111
cE

10

e~

20

Z~

0

I

,

OW
00 ·10
a: Z
·20
IIIW
ZO -30

II!~

~~

. . . r--.

-

'"-

·70

·80

o

DIFFERENTIAL AMPLIFIER
Vcc=12V
1=200MHz
TA = 25°C

CASCODE AMPLIFIER
Vee = 12V
I =200MHz
TA = 25°C

1'0..

2

40

50

r-

J
I

",..

" "-

-40
ca: -SO
a:o
·60

i~

921 -

-

10
20
30
COLLECTOR SUPPLY VOLTAGE (V)

FIGURE 29. FORWARD TRANSFER ADMITTANCE (Y21) VB
COLLECTOR SUPPLY VOLTAGE

FIGURE 28. FORWARD TRANSFER ADMITTANCE (Y21) vs
COLLECTOR SUPPLY VOLTAGE

0
Z

o

"..,..,- ~

--- - --i>:!1

~

I
I

r-

b21 -

-

....

r-

I

4
6
8
10
EMITTER CURRENT (13 OR la) (mA)

·20
12

FIGURE 30. FORWARD TRANSFER ADMITTANCE (Y21) VB
EMITTER CURRENT

14

o

921
4

8

12

16

EMITTER CURRENT (13 OR la) (mA)

FIGURE 31. FORWARD TRANSFER ADMITTANCE (Y21) vs
EMITTER CURRENT

7·36

CA3054

HARRIS
SEMICONDUCTOR

Dual Independent Differential Amp for Low Power

Applications from DC to 120MHz

November 1996

Features

Description

• Two Differential Amplifiers on a Common Substrate

The CA3054 consists of two independent differential
amplifiers with associated constant current transistors on a
common monolithic substrate. The six NPN transistors which
comprise the amplifiers are general purpose devices which
exhibit low 1/f noise and a value of fT in excess of 300MHz.
These feature make the CA3054 useful from DC to 120MHz.
Bias and load resistors have been omitted to provide maximum application flexibility.

• Independently Accessible Inputs and Outputs
• Maximum Input Offset Voltage •••••.••••••••. ±SmV
• Temperature Range. . . . • • • • • • . . • • • . .• OoC to 8SoC

Applications

• Multifunction Combinations
- RF/Mixer/Oscillator; ConverternF

The monolithic construction of the CA3054 provides close
electrical and thermal matching of the amplifiers. This
feature makes these devices particularly useful in dual
channel applications where matched performance of the two
channels is required.

• IF Amplifiers (Differential and/or Cascode)

Ordering Information

• Dual Sense Amplifiers
• Dual Schmitt Triggers

• Product Detectors

PART NUMBER
(BRAND)

• Doubly Balanced Modulators and Demodulators
• Balanced Quadrature Detectors
• Cascade Limiters
• Synchronous Detectors

TEMP.
RANGEfC)

PACKAGE

PKG.
NO.

CA3054

01085

14LdPDIP

E14.3

CA3054M
(3054)

010 85

14LdSOlC

M14.15

CA3054M96
(3054)

01085

14 Ld SOIC Tape
and Reel

M14.15

• Pairs of Balanced Mixers
• Synthesizer Mixers

u.:
u.

-en

• Balanced (Push-Pull) Cascode Amplifiers

0a:

Ow

z-


g

0.9

3

III

0.8

CI

I::2

0.7

g

~

0.6

i

0.5

Iii
~
0

a:

I

VCB =3V

1.0

2

~

III

III
III

~

0.75

.-

-50

-25

25

0

75

50

100

~

0.50

'E=0.1mA _

1 J

o

125

-

'E=1mA -

0.25

0.4
-75

I

IE=10mA -

-75

-50

-25

0

25

50

75

100

125

u.:

TEMPERATURE (OC) (NOTE)

TEMPERATURE (OC) (NOTE)

NOTE: For CA30S4 use data from OoC to 85°C only.

Ii.

-en

Co::

NOTE: For CA3054 use data from OoC to 85°C only.

FIGURE 6. BASE-TO-EMITTER VOLTAGE FOR EACH
TRANSISTOR vs TEMPERATURE

Cw

z-

FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR
DIFFERENTIAL PAIRS


a
N

III

III

4

~i'"

VCB=3V
TA=250 C

0::<
0::

~
!:iII.
0

i!;

!:iII.

I'
0.1

1-0.01
0.01

i!;

10

FIGURE 8. STATIC BASE-TO-EMITTER VOLTAGE AND INPUT
OFFSET VOLTAGE FOR DIFFERENTIAL PAIRS vs
EMITTER CURRENT

-

l/

~

i.ooo'

0.1
1.0
COLLECTOR CURRENT (mA)

10

FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED
DIFFERENTIAL PAIRS vs COLLECTOR CURRENT

7-41

CA3054

Typical Performance Curves

(Continued)
100

VCC=12V

iii'

:!:!. 110

Q

r

~

~

VEE=-6V
I = 1kHz

100

:!:!. 75

1= 1kHz

~

SIGNAL INPUT = 10mVRMS

CI

~

/~
,.".

90

50

~

25

g

"'" ~

w

V

1.i

0

t;;

\

w

~

-'

CI -25

-so

90

o

-1

-2

-3

o

100
VCC= 12V
VEE =-6V
1=lkHz
SIGNAL INPUT = 1mVRMS

iii' 75
:!:!.
if:

1.i
!:l
g

25

~

rr;
w

10
hRE

if
~
~
rr;

\

-1

-2

-3

BIAS VOLTAGE ON TERMINALS 3 AND 11

0

Z

-6

!.

900

30

w
u
Z

~~

13

800

0

700

0 U
rr;z

iII.
:z:

b

300
200

~

:cCl

,

500

Z

1"'..-00 ~

-'

~RE
hiE
10

20

DIFFERENTIAL CONFIGURATION
IC (EACH TRANSISTOR);: 1.2SmA
VCS=3V
TA = 2SoC

:)W

800

~
Z

hFE

FIGURE 13. FORWARD CURRENT TRANSFER RATIO (hFE).
SHORT CIRCUIT INPUT IMPEDANCE (hiE). OPEN
CIRCUIT OUTPUT IMPEDANCE (hOE). AND OPEN
CIRCUIT REVERSE VOLTAGE TRANSFER RATIO
(hRE) VB COLLECTOR CURRENT FOR EACH
TRANSISTOR

1.'J'1l
0-

:)

./

0.1
1.0
COLLECTOR CURRENT (mA)

M

VCS=3V
TA=2SoC
1000

I'~

/

V

0.1
0.01

-7

FIGURE 12_ TWO STAGE VOLTAGE GAIN CHARACTERISTIC

!

.,. ,.

I

I

~

0

-' 1.0

hOE

hFE=110
}
hiE = 3.5kil
AT
hRE = 1.88 x 10-4
lmA
hOE = 15.611S

.....

J:

\...

o

-

~~IE-

Iii

~
rr;

\

-25
-50

-

"\

0

Vcs = 3V
1=lkHz
TA=2SoC

0

--...~

w

1.i
Iii

-7

M

FIGURE 11_ SINGLE STAGE VOLTAGE GAIN CHARACTERISTIC

100

50

-3

BIAS VOLTAGE ON TERMINAL 11

FIGURE 10_ COMMON MODE REJECTION RATIO
CHARACTERISTIC

Cl

-2

-1

BIAS VOLTAGE ON TERMINAL 11 (V)

'w"

'-

~

~

8

w

Cl

.".

rr;

~

VCC=12V
VEE =-6V

iii'

400

10

~e
0:)

I;"

Zo

"'z
Orr;

!Ii 0

I0

100

~

-10

921

u.

"."..

-20
1

2

3

4 S 6 7 8 9 10 11
COLLECTOR CURRENT (mA)

12 13 14

FIGURE 14. GAIN BANDWIDTH PRODUCT (for) VB COLLECTOR
CURRENT

0.1

"

~

i....o-"

0

~8

I

o

I
b21

1.0

10
FREQUENCY (MHz)

100

FIGURE 15. FORWARD TRANSFER ADMITTANCE (Y21) VB
FREQUENCY

7-42

CA3054
Typical Performance Curves

(Continued)
3

DIFFERENTIAL CONFIGURATION
IC (EACH TRANSISTOR);: 1.2SmA

5

VCB=3V
TA=25o C

II:

o~

u.s.

4

~g

3

LIJUI

~~

!!l6
Ul Z
~8

DIFFERENTIAL CONFIGURATION
IC (EACH TRANSISTOR);: 1.2SmA
0.5

I

rr

J

.s.

0.4

g

0.3

LIJ
U
Z

bl1

2

z

)

~/

I

~/

g1 1

0.1

10
FREQUENCY (MHz)

8
5
~
0

r--

II

0

10

~

0.1

LIJ

0.01

F=

~

0.001

,

m

II: 0.0001

0.1

100

1

/11

"

~

III

10
FREQUENCY (MHz)

o
100

~
z

~

i

r-

0.1

I

I- TA=2SoC

,,

VCB=3V

~

-

..

w

i'...

m

100

0.01 II:
1000

f--

",921

CASCODE CONFIGURATION
IC (STAGE) ;: 2.SmA

10
12

10
FREQUENCY (MHz)

922-

./ /

....

0.1

~

~

-

-g12

0.1

FIGURE 17. OUTPUT ADMITTANCE (Y22) vs FREQUENCY

,,-

=

b12

b 22

1000~

DIFFERENTIAL CONRGURATION
VCB=3V
Ie (EACH TRANSISTOR) 1.2SmA
TA=2SoC

g

0.2

o
100

FIGURE 16. INPUT ADMITTANCE (Y11)

I

II

Q

...

~

Ii

::l

~

~

.,

VCB=3V
TA=2SOC

Iii'

10
FREQUENCY (MHz)

~

V

100 200

Cw

FIGURE 19. FORWARD TRANSFER ADMITTANCE (Y21) vs
FREQUENCY

FIGURE 18. REVERSE TRANSFER ADMITTANCE (Y12) vs
FREQUENCY

u.:

u.
-cn

Co:

zcd!:

cn..J
D..
~:E

0: oCt
0:

oCt

9~2

CASCOOECONRGURATION
IC (STAGE);: 2.SmA

6

VCB=3V
TA=25oC

n

'I

CASCODE CONFIGURATION
Ic (STAGE) ;: 2.SmA
VCB=3V
TA=2SoC

I,tl
~

,,-~
o
0.1

"

1>,1

10
FREQUENCY (MHz)

II

J

I
~2

~

g11

r-....

I
1
I

I

/
~

1\
1\

I
1

100 200

10
FREQUENCY (MHz)

100

FIGURE 21. OUTPUT ADMITTANCE (Y22) vs FREQUENCY

FIGURE 20. INPUT ADMITTANCE (Y11) vs FREQUENCY

7-43

CA3054

Typical Performance Curves

(Continued)

I§

100

~
-

10

fi~

CASCODE CONFIGURATION
IC (STAGE) 2.6mA

=

VCB=3V
TA-250C

S~
8~

L

Zw

~~
~~

~~

W

!

g12

iI""

,

/-b12

0.1
L

IV"

0.01

..G

0.001
0.1

1

10

100 200

FREQUENCY (MHz)

FIGURE 22. REVERSE TRANSFER ADMITTANCE (Y12) VB FREQUENCY

7·44

CA3081, CA3082
General Purpose High Current
NPN Transistor Arrays

November 1996

Features

Description

• CA3081 - Common EmiHer Array

CA3081 and CA3082 consist of seven high current (to
100mA) silicon NPN transistors on a common monolithic
substrate. The CA3081 is connected in a common emitter
configuration and the CA3082 is connected in a common
collector configuration.

• CA3082 - Common Collector Array
• Directly Drive Seven Segment Incandescent Displays
and Light EmlHlng Diode (LED) Display
• 7 Transistors Permit a Wide Range of Applications In
Either a Common EmiHer (CA3081) or Common Collector (CA3082) Configuration
• High IC ....••••••••••.••••••••.•.. 100mA (Max)
• Low VCESAT (at SOmA) ••••••••••••••••• O.4V (Typ)

The CA3081 and CA3082 are capable of directly driving
seven segment displays, and light emitting diode (LED) dis·
plays. These types are also well suited for a variety of other
drive applications, including relay control and thyristor firing.

Ordering Information
PART NUMBER
(BRAND)

Applications
• Drivers for
- Incandescent Display Devices
- LED Displays
- Relay Control
• Thyristor Firing

TEMP.
RANGE (oC)

PACKAGE

PKG.
NO.

CA30B1

·5510125

16 Ld PDIP

E16.3

CA30B1F

-55 to 125

16Ld CERDIP

F16.3

CA30B1M
(30B1)

·5510125

16 Ld SOIC

M16.15

CA30B1M96
(30B1)

·5510125

16 Ld SOIC Tape
and Reel

M16.15

CA30B2

·5510125

16 Ld PDIP

E16.3

CA30B2F

-5510125

16 Ld CERDIP

F16.3

CA30B2M
(30B2)

·5510125

16 Ld SOIC

M16.15

CA30B2M96
(30B2)

·5510125

16 Ld SOIC Tape
and Reel

M16.15

Pinouts
CA3081
COMMON EMITTER CONFIGURATION
(PDIP, CERDIP, SOIC)
TOP VIEW

CA3082
COMMON COLLECTOR CONFIGURATION
(PDIP, CERDIP, SOIC)
TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

7·45

File Number

480.3

CA3081, CA3082
Absolute Maximum Ratings

Thermal Information

TA = 2SoC

Collector-to-Emitter Voltage (VCEO)' ...................... 16V
Collector-to-Base Voltage (VCBO) ....................... 20V
Collector-to-Substrate Voltage (VCIO, Note 1) .............. 20V
Emitter-to-Base Voltage (VEBO) .......................... SV
Collector Current (Ic) ............................... 100mA
Base Current (IB) .................................. 20mA

Operating Conditions
Temperature Range ........................ -SSoC to 12SoC

Thermal Resistance (Typical, Note 2)
.8JA (oCIW) 8JC (oCIW)
CERDIP Package. . . . . . . . . . . . . . . .
13S
6S
PDIP Package....... . . . . .. ..... .
13S
N/A
SOIC Package. . . . . . . . . . . . . . . . . . •
200
N/A
Maximum Power Dissipation (Any One Transistor) ........ SOOmW
Maximum Junction Temperature (Ceramic Package) ......... 17SoC
Maximum Junction Temperature (Plastic Package) ........ lS00C
Maximum Storage Temperature Range ......... -6SoC to lS00C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum RatIngs" may cause permanent damage to the device. This is a stress only rating and operation
of /he device at these or any other conditions above those Indicated in the operational sections of this specification is not implied.

NOTES:
1. The collector of each transistor of the CA3081 and CA3082 is isolated from the substrate by an integral diode. The substrate must be
connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide
normal transistor action. To avoid undesired coupling between transistors, the substrate terminal (S) should be maintained at either DC
or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

For Equipment Design at TA = 2SoC

PARAMETER

MIN

TYP

MAX

UNITS

V(BR)CBO

IC = SOOItA, IE = 0

20

60

-

V

Collector-te-Substrate Breakdown Voltage

V(BR)CIO

Ic = SOOI!A, IB = 0

20

60

Collector-to-Emitter Breakdown Voltage

V(BR)CEO

IC=lmA,IB=O

16

24

-

V

Emitter-to-Base Breakdown Voltage

V(BR)EBO

Ic=SOOItA

S.O

6.9

-

V

VCE = O.SV, Ic = 30mA

30

68

40

70

-

-

VCE = 0.8V, Ic = SOmA

0.87

1.2

V

0.27

O.S

V

0.4

0.7

V

0.4

O.B

V

10

I!A

1.0

I!A

Collector-IO-Base Breakdown Voltage

DC Forward Current Transfer Ratio

SYMBOL

hFE

Base-to-Emitter Saturation Voltage (Figure 4)

VBESAT

Collector-IO-Emitter Saturation Voltage

VCESAT

CA3081 , CA3082

TEST CONDITIONS

Ic = 30mA, IB = lmA

Ic=30mA, IB= lmA

CA3081 (Figure S)

IC = SOmA, IB = SmA

CA3082 (Figure S)

IC = SOmA, IB = SmA

Collector Cutoff Current

ICEO

VCE=10V,IB=0

Collector Cutoff Current

ICBO

VCB=10V,IE=0

7-46

-

-

V

CA3081, CA3082
Typical Read - Out Driver Applications

=rL

Vp
OV

1

i

V+

1n CA3082
(COMMON COLLECTOR)
R(NOTE)
LIGHT EMmlNG DIODE (LED)
40736R

V+

NOTE: The Resistance lor R is determined by the relationship:

1 SEGMENT OF INCANDESCENT DISPLAY
(DR2oo0 SERIES OR EQUIVALENT)

1n CA3081

FROM
DECODER

R

(COMMON EMITTER)

=

Vp-VBE-VF(LED)
I(LED)

R = OlorV p = VBE+VF(LED)
Where: Vp = Input Pulse Voltage
VF = Forward Voltage Drop Across the Diode

FIGURE 1. SCHEMATIC DIAGRAM SHOWING ONE
TRANSISTOR OF THE CA3081 DRIVING ONE
SEGMENT OF AN INCANDESCENT DISPLAY

FIGURE 2. SCHEMATIC DIAGRAM SHOWING ONE TRANSISTOR OF THE CA3082 DRIVING A LIGHT EMITTING
DIODE (LED)

Typical Performance Curves
1.0

100

TA=~SOC

VeE =3V

hFE = 10

90

!Eli!
III "a:S-

80

8~
ca:

70

i~

60

a: a:

IZ~

81=

-

c--

/ ,..... ~~
~~
~

50

'

TA=700~ ".
.II'

.......

....rrr

TA = 25°C

[.../

~

...-"TA-:tbl

~

;..-

~

~

~

/

,.".~
La:

II..

-II)

Ca::

40
0.1

1
10
COLLECTOR CURRENT (mA)

0.6

100

FIGURE 3. DC FORWARD CURRENT TRANSFER RATIO va
COLLECTOR CURRENT

1

10
COLLECTOR CURRENT (mA)

100

Q.

II

,

o

1

--

!liE

V "./

~

-

~

0.8

~~

0.6

a:z

I

~~

If

"...

I:I!l
::&~

I(

MAXIM,/

~~

UC/)

TYPICAL

10
COLLECTOR CURRENT (mA)

~::t
a::~
u O

5!~

70

14

60

;

...

50

C!I

e~

~/

80

0"

~

...~

....

1....-"'"

90

1L!l!
Uii'!

0.8

I

VCE=3V
TA = 25°C

ffiiil
a: o.

iffi

(Continued)

1/

l/

,...."'"
".,.

0.7

~

...a:

0.6

...~

0.5

~
'I'

I""

VCE=3V
TA = 25°C

~

"""

0.1
EMITTER CURRENT (mA)

0.4
0.01

10

FIGURE 4. VBE vs 'E

100

Vca=3V

~

...'"a:

Iii

0.9

:Ii

ii'!
2:
.c

0.8

~
a: 0.7

...

I::Ii

0.6

...~

0.5

10

VCE =3V
f = 1kHz
TA=250C

-

r

hFE=100
}
hiE = 3.5kn
AT
hRE = 1.88 x 10-4 lmA
hOE = 15.6i1S

~IE

!!IoJ
0(

h

I"~

-

1.0
I·

a:
0

z

#

#

-75

-SO

-25

0
25
50
75
TEMPERATURE (oC)

100

0.1
0.01

125

FIGURE 5. VBE vs TEMPERATURE

IL

L

'"""

6

hlEj

0.1
1.0
COLLECTOR CURRENT (mAl

,

bl~

I

I

I1IL

"-

......

10
FREQUENCY (MHz)

10

J
1'\

-

NRE

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25°C, VCE =3V, Ic= 1mA

I

bFE

..

hFE

FIGURE 6. NORMALIZED hFE' hiE, hRE' hOE vs IC

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25°C, VCE = 3V,Ic = 1mA

~
9FE........

LL

'i
.L

~

:Ii

0.4

hOE-

hRE

Q

'I'

i

10

0.1
1.0
EMITTER CURRENT (mA)

FIGURE 3. hFE vs 'E

!j

VaE

i

0.01

...~

,..",.

".

,

./ L.oo'

...

o
100

0.1

FIGURE 7. YFE vs FREQUENCY

1

~ ;...-""

10
FREQUENCY (MHz)

FIGURE 8. YIE vs FREQUENCY

7-55

g,E -

~

I

100

CA3086
Typical Performance Curves

6

wU>
OE

s::::w

S

e~
:>z
!il~

4

I-rn

2

(Continued)

COMMON EMITTER CIRCUIT, BASE INPUT
TA =2SoC, VCE =3V,lc= lmA

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 2SoC, VCE 3V, Ic lmA

=

III

Ze0

o

C)

b0i-

3

... rn

bRE,

-O.S

II

8~

:>:>

=

9RE IS SMALL AT FREQUENCIES
LESS THAN SOOMHz

-1.0

--

I-C

~

/

:>z
Oce

1/

./

0
0.1

10

-l.S

90E

I

-2.0

100

1

10

FREQUENCY (MHz)

FREQUENCY (MHz)

FIGURE 10. YRE vs FREQUENCY

FIGURE 9. YOE vs FREQUENCY

VCE = 3V

li
!.

TA = 25°C

1000
900
800

700
600
~

SOO

fI"

400

I

300
200

100

o

o

2

3

4

S

6

7

8

COLLECTOR CURRENT (mA)

FIGURE 11. ". vs Ic

7-56

9

10

100

CA3096, CA3096A,
CA3096C

HARRIS
SEMICONDUCTOR

NPN/PNP Transistor Arrays

August 1996

Applications

Description

• Five-Independent Transistors

The CA3096C, CA3096, and CA3096A are general purpose
high voltage silicon transistor arrays. Each array consists of
five independent transistors (two PNP and three NPN types)
on a common substrate, which has a separate connection.
Independent connections for each transistor permit maximum flexibility in circuit design.

- Three NPN and
- Two PNP
• Differential Amplifiers
• DC Amplifiers
• Sense Amplifiers

Types CA3096A, CA3096, and CA3096C are identical, except
that the CA3096A speCifications include parameter matching
and greater stringency in ICBO. ICEO. and VCE(SAT). The
CA3096C is a relaxed version of the CA3096.To type this
body text, simply triple click this paragraph and begin typing.
The paragraph tag for this area is called body.

• Level Shifters
• Timers
• Lamp and Relay Drivers
• Thyristor Firing Circuits
• Temperature Compensated Amplifiers
• Operational Amplifiers

CA309~CA3096A,CA3096C

Ordering Information

Essential Differences

PART NUMBER
(BRAND)

TEMP.
RANGE (DC)

PACKAGE

PKG.
NO.

CHARACTERISTIC

CA3096A

CA3096

CA3096C

V(BR)CEO (V) (Min)

CA3096AE

-55 to 125

16 Ld PDIP

E16.3

NPN

35

35

24

CA3096AM
(3096A)

-55 to 125

16 Ld SOIC

M16.15

PNP

-40

-40

·24

CA3096AM96
(3096A)

·55 to 125

16 Ld SOIC Tape
and Reel

M16.15

CA3096CE

·55 to 125

16 Ld PDIP

E16.3

CA3096E

·55 to 125

16 Ld PDIP

E16.3

CA3096M
(3096)

·55 to 125

16 LdSOIC

M16.15

CA3096M96
(3096)

·55 to 125

16 Ld SOIC Tape
and Reel

V(BR)CBO (V) (Min)
NPN

45

45

30

PNP

·40

·40

·24

NPN

150·500

150-500

100-670

PNP

20·200

20·200

15·200

40-250

40·250

30-300

NPN

40

100

100

PNP

-40

·100

·100

hFEatlmA

M16.15

hFE at IOOI1A
PNP
ICBO (nA) (Max)

Pinout
CA3096, CA3096A, CA3096C
(PDIP, SOIC)
TOP VIEW

ICEO (nA) (Max)
SUBSTRATE

NPN

100

1000

1000

PNP

·100

·1000

-1000

0.5

0.7

0.7

NPN

5

.

PNP

5

-

NPN

0.6

PNP

0.25

.

VCE SAT (V) (Max)
NPN
IVIOI (mV) (Max)

11101 (1lA) (Max)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

7-57

File Number

.

595.3

CA309~CA3096A.CA3096C

Absolute Maximum Ratings

Operating Conditions
NPN

Collector-to-Emitter Voltage, VCEO
CA309S, CA309SA ..................... 35V
CA309SC ............................ 24V
Collector-to-Base Voltage, VCBO
CA309S, CA309SA ..................... 45V
CA3096C ............................ 30V
Collector-to-Substrate Voltage, VCIO (Note 1)
CA309S, CA309SA ..................... 45V
CA309SC ............................ 30V
Emitter-to-Substrate Voltage, VEIO
CA309S, CA309SA . . . . . . . .. . .. .. .. .. . . .. CA309SC ............................. Emitter-to-Base Voltage, VEBO
CA309S, CA309SA ...................... SV
CA309SC ............................. SV
Collector Current, Ic (All Types) . . . . . • • . . . .• 50mA

PNP

Temperature Range ........••..............• -550C to 125°C

-40V
-24V

Thermal Information

-40V
-24V

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Pa.ckage.............. ..... .•........
170
Maximum Power Dissipation (Each Transistor, Note 3) ..... 200mW
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range .•..•.....-S50C to 150°C
Maximum Lead Temperature (Soldering 1Os) ............. 300°C
(SOIC - Lead Tips Only)

9JA (oclW)

Thermal Resistance (Typical, Note 2)

-40V
-24V
-40V
-24V
-10mA

CAUTION: Stresses above those listed In "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operaffonal sections of this specification /s not implied.

NOTES:
1. The collector of each transistor of the CA309S is isolated from the substrate by an integral diode. The substrate (Terminal 1S) must be
connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor
action.
2. 6JA is measured with the component mounted on an evaluation PC board in free air.
3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal
resistances to calculate the junction temperature.

Electrical Specifications

PARAMETER

For Equipment Design, At TA = 250 C

TEST
CONDITIONS

CA3096

I

MIN

TYP

CA3096C

CA3096A
MAX

I

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DC CHARACTERISTICS FOR EACH NPN TRANSISTOR

-

0.001

100

-

0.001

40

-

0.001

100

nA

-

O.OOS

1000

-

O.OOS

100

-

O.OOS

1000

nA

-

24

35

100

30

80

45

100

-

30

80

S

8

-

S

8

-

V

9.8

S

7.9

9.8

S

7.9

9.8

V

0.24

0.7

-

0.24

0.5

-

0.24

0.7

V
V

ICBO

VCB= 10V,
IE=O

ICEO

VCE= 10V,
IB=O

V(BR)CEO

Ic=1mA,IB=0

35

50

35

50

V(BR)CBO

Ic = 101lA,
IE=O

45

100

45

V(BR)CIO

ICI = 1011A
IB=IE=O

45

100

V(BR)EBO

IE = 101lA,
Ic=O

S

8

Vz

Iz = 101lA

S

7.9

VCESAT

IC=10mA,
IB=1mA

VBE(Note4)

IC=1mA,
VCE=5V

hFE (Note 4)
IdVBE/dTI (Note 4)

Ic=1mA,
VCE=5V

-

V
V
V

O.S

0.S9

0.78

O.S

0.S9

0.78

O.S

0.S9

0.78

150

390

500

150

390

500

100

390

S70

-

1.9

-

-

1.9

-

1.9

-

mVfJC

-100

-

-O.OOS

-40

-O.OS

-100

nA

DC CHARACTERISTICS FOR EACH PNP TRANSISTOR
ICBO

VCB= -10V,
IE=O

-O.OS

7-58

-

CA309~CA3096A,CA3096C

Electrical Specifications

PARAMETER

For Equipment Design, At TA = 25°C (Continued)

TEST
CONDITIONS

CA3096

CA3096A

CA3096C

MIN

TYP

MAX

MIN

TYP

MAX

-

-0.12

-1000

-

-0.12

-100

IC=-100J1A,
IS=O

-40

-75

-40

-75

-

V(SR)CSO

IC=-10J1A,
IE=O

-40

-80

-

-40

-80

V(SR)ESO

IE=-10J1A,
IC= 0

-40

-100

-

-40

-100

V(SR)EIO

lEI = 10J1A,
IS=IC=O

40

100

-

40

VCESAT

Ic=-1mA,
Is = -100J1A

-

-0.16

-0.4

VSE (Note 4)

Ic = -100J1A,
VCE=-5V

-0.5

-0.6

hFE (Note 4)

IC = -100J1A,
VCE=-5V

40

IC=-1mA,
VCE=-5V

ICEO

VCE=-10V,
IS=O

V(SR)CEO

IAVSE/ATI (Note 4)

TYP

MAX

UNITS

-0.12

-1000

nA

-24

-30

-

V

-24

-60

-

V

-

-24

-80

100

-

24

80

-

V

-

-0.16

-0.4

-0.16

-0.4

V

-0.7

-0.5

-0.6

-0.7

-0.5

-0.6

-0.7

V

85

250

40

85

250

30

85

300

20

47

200

20

47

200

15

47

200

-

2.2

-

2.2

-

-

2.2

-

Ic=-100J1A,
VCE=-5V

MIN

V

ICSO

COllector-Cutoff Current

Vz

Emitter-to-Base Zener Voltage

ICEO

Collector-Cutoff Current

VCE SAT

Collector-to-Emitter Saturation Voltage

V(SR)CEO Collector-to-Emltter Breakdown Voltage

VSE

Base-to-Emitter Voltage

V(SR)CBO Collector-to-Base Breakdown Voltage

hFE

DC Forward-Current Transfer Ratio

V(SR)CIO

IAVSE/ATI Magnitude of Temperature Coefficient:
(for each transistor)

Collector-to-Substrate Breakdown Voltage

V(SR)ESO Emitter-to-Base Breakdown Voltage

mVPC

u.:

II..

-rn
Co:::

NOTE:

Cw

zed!:

4. Actual forcing current is via the emitter for this test.

Electrical Specifications

rn~

~::i

For Equipment Design At TA = 25°C (CA3096A Only)

0:::<
0:::

CA3096A
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

<

MAX

UNITS

0.3

5

mV

11101

0.07

0.6

!AV IO!

1.1

FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER)
Absolute Inpu1 Offset Voltage
Absolute Input Offset Current
Absolute Input Offset Voltage
Temperature Coefficient

IVl oi

VCE = 5V, Ic = 1mA

J1A
J1VPC

---;rr-

FOR TRANSISTORS Q4 AND Qs (AS A DIFFERENTIAL AMPLIFIER)

-

0.15

5

mV

11101

-

2

250

nA

!AV IO!

-

0.54

-

J1VPC

Absolute Input Offset Voltage

IVlol

Absolute Inpu1 Offset Current
Absolute Input Offset Voltage
Temperature Coefficient

VCE = -5V, Ic = -10011A
Rs=O

---;rr-

7-59

CA309~CA3096A,CA3096C

Electrical Speci,ications

Typical Values Intended Only for Design Guidance At TA = 25°C

PARAMETER

TYPICAL
VALUES

UNITS

f= 1kHz, VCE = 5V, Ic = lrnA, Rs = lkn

2.2

dB
kg

SYMBOL

TEST CONDITIONS

DYNAMIC CHARACTERISTICS FOR EACH NPN TRANSISTOR
Noise Figure (Low Frequency)

NF

Low-Frequency, Input Resistance

RI

f = 1.0kHz, VCE = 5V Ic;' 1 mA

10

Low-Frequency Output Resistance

Ro

f = 100kHz, VCE =5V Ic = 1 mA

BO

kg

mS

Admittance Characteristics
gFE

f= lMHz, VCE = 5V, Ic = lmA

7.5

bFE

f= .1 MHz, VCE= 5V,lc= lmA

-j13

mS

glE

f= lMHz, VCE = 5V, Ic = lmA

2.2

mS

blE

f= lMHz, VCE=5V,lc= lmA

j3.1

mS

gOE

f= lMHz, VCE= 5V,lc= lmA

0.76

mS

bOE

f= lMHz, VCE= 5V,IC = lmA

j2.4

mS

VCE = 5V, Ic = 1.0mA

2BO

MHz

VCE = 5V, IC = 5mA

335

MHz
pF

Forward Transfer Admittance
YFE
Input Admittance
YIE
Output Admittance
YOE
Gain-Bandwidth Product

fr

Emitter-To-Base Capacitance

CES

VES=3V

0.75

CoIIB0
11 =12
11-12>0
FREQUENCY DEVIATION (kHz)

20

FIGURE 2. FREQUENCY COMPARATOR CHARACTERISTICS

7-60

CA309~CA3096A,CA3096C

Typical Applications

(Continued)

T2300B

1

120VAC

j
FIGURE 3. UNE'()PERATED LEVEL SWITCH USING CA3096A OR CA3096
+6V

OUTPUT

u.:

LL
-(f)
0a:

TIME DELAY CHANGES ±7%
FOR SUPPLY VOLTAGE CHANGE OF ±10%

FIGURE 4. ONE·MINUTE TIMER USING CA3096A AND A MOSFET

Ow
zCC!!:

(f)it
~:iE
a:CC
a:
CC

VT=±~

10 RL
IF 10 = 1mA AND RL .. 1kn
VT-±36mV

~----H---4Eo

+VT~~~~------~--~­

VIN ~i---~-----J'+---+"
-VT --i---t--''tr--#-+--+-

FIGURE 5. CA3096A SMALL-8IGNAL ZERO VOLTAGE DETECTOR HAVING NOISE IMMUNITY

7·61

CA3096, CA3096A, CA3096C

Typical Applications

(Continued)
1.5V

16r------.
(SUBSTRATE)

"="

FIGURE 6. TEN-SECOND TIMER OPERATED FROM 1.5V SUPPLY USING CA3096

+BV

NOTES:

5. can be operated with either dual
supply or single supply.
6. Wide-Input common mode range
+SVto -SV.

7. Low bias current: <111A.

FIGURE 7. CASCADE OF DIFFERENTIAL AMPLIFIERS USING CA3096A

70

60

~ 1'10...

!50
~
I!J
~

r--

CI 40

g

30

20

10
1

10
100
FREQUENCY (kHz)
FIGURE 8. FREQUENCY RESPONSE

7-62

1000

CA3096, CA3096A, CA3096C
Typical Performance Curves
104

10

i

Ii

II

I
I~

I-vz-I:~

VCE=10V"

kd~r
I-r-

II
"VCE=5V~-

I,-r::f::
.....

~

10-1
7.5

8.5

8

9

~

~

~

ZENER VOLTAGE (V)

",
0

~ 500

102
VCB= ISV"

u 10

......

k,

VCB = 10V

0

5u

~

7'7I'VCB" SV
~

!

'V

II:

~

::l

8

~

10-2
-75

-so

-25

o

25
TEMPERATURE (oC)

so

75

".."..

,/

",..

,

~I'"

~I'"

100

8

0
0.01

I
0.9

~

0.7

0.6

~

w

~

",I---'" ~
1",.0

10

RGURE 12. TRANSISTOR (NPN) hFE vs COLLECTOR
CURRENT

~ 0.8
w

w

~

0.1
COLLECTOR CURRENT (mA)

VCE=SV

~
:IE

......... ~~

I
I I
TA =-"

0.9

W

0.8

Iii
~

0.6

.§.

~
!:l
~

0.9

~
w

~

!:i
~

o

a:
w

;;:;

IS

12
III

-20

0

20
40
TEMPERATURE (DC)

60

~

80

~

I

Iii

V

~ 0.4
0.3

15

\

~ 0.2
;;:;

J

r'\ ,

0.1

0
0.01

~

-

io-'

W

,

14

~

8

~
z

6
4

2

o

-

0.01

~

8

~

6

~

1m~

~

'-

I....
1001lA

101lA

~ =::...

I
I

o

10

0.01

0.1

1.0
FREQUENCY (kHz)

10

100

FIGURE 24. NOISE FIGURE vs FREQUENCY FOR NPN
TRANSISTORS

RSOURCE = 1kQ

RSOURCE = 10kQ
24

iii 20
:!!.
W
16
a:
:;)

.,
"
"-

CJ

Ii:

"'-

0.1

Ic=3mA

2

Ic=3mA

-rlil

I III

28

II

""

Iii

~

4

\l
10
~ 1~

Ii:

10

z

iii
:!!. 12

~

g;
W

0.1
COLLECTOR CURRENT (mA)

16 ~

10

RSOURCE = soon

14 ~

iii
:!!. 12

FIGURE 23. MAGNITUDE OF INPUT OFFSET VOLTAGE IVIOI vs
COLLECTOR CURRENT FOR PNP TRANSISTOR
Q4- Q S
18

0.1
1.0
COLLECTOR CURRENT (mA)

16

/
I'

15

II!

0
0.01

18

0.5

w

~
~

./

FIGURE 22. MAGNITUDE OF INPUT OFFSET VOLTAGE IVIOI va
COLLECTOR CURRENT FOR NPN TRANSISTOR
Q1- Q2

FIGURE 21. VBE (PNP) vs TEMPERATURE

~

......... .........

I

E
z 0.1

C

If

0.3

/

~ 0.2

w

tn

>"

J

0.5

~ 0.4

§w

.§.

0.7

W

-

~
z

101lA

1
10
FREQUENCY (kHz)
FIGURE 25. NOISE FIGURE vs FREQUENCY FOR NPN
TRANSISTORS

~ Ic=3mA

......

i'

12

~

8 -101lA

4 ~

I\,

o

0.01

100

~

.......

1mA

r....

~01lA

I
0.1

1.0
FREQUENCY (kHz)

10

FIGURE 26. NOISE FIGURE vs FREQUENCY FOR NPN
TRANSISTORS

7-65

100

CA309~CA3096A,CA3096C

Typical Performance Curves
28
24

400

1\

RSOURCE = 1ook.QRSOURCE = 1 MO •••

20

, "~

II!::>

16

100~A

~

!l!

12

i

8

iii

~,

:2-

4

~
!.
t;

,

,

,

~O~

I~~

0.01

300

/

:c 200

5

~z

'ro .......

.... ... . ..
~

100llA

..t--.

0.1

..:

i

10

,"

....

. /~

~

~

..
.

1

/

100

/'

o

0.1

100

1.0

10

COLLECTOR CURRENT (mA)

FREQUENCY (kHz)

FIGURE 27. NOISE FIGURE
TRANSISTORS

"

Q

Ii!II.

.

I~
o

VCE = sv

::>

\::=1mA

I
,

(Continued)

vs FREQUENCY FOR NPN

FIGURE 28. GAIN-BANDWIDTH PRODUCT vs COLLECTOR
CURRENT (NPN)

4.0

1000
f= 1kHz

3.5

"-

3.0

~
w 2.5
z

u

~

I

........

"-

......

2.0

........

...

1.5

-

~ --:,EB

1.0
0.5

~
w

CCI

--

U

2

3

4

z

UI

w
a:
~

5
0

PNP

~

5

6

7

8

9

........
~

""

10

1
0.01

10

102

~

~
10

IgFEI J
Ic = 1mA

I""r---.. .........

NPN
PNP

"

0.1

FIGURE 30. INPUT RESISTANCE vs COLLECTOR CURRENT

I

"I'

........

COLLECTOR CURRENT (mA)

f=1kHz

i'o.:

i!
!II

IIIw

!:

104

103

NPN

.....

a:

RGURE 29. CAPACITANCE vs BIAS VOLTAGE (NPN)

~

I'

z

1!

BIAS VOLTAGE (V)

w

r-....

CCB

o

u

100 ~

.........
gFE

""" ....

10

.'
r- :::: "'~E 100~
...

1
0.01

-N

tijmA
0.1

1.0

"'" ""

1OO~

10

10

COLLECTOR CURRENT (mA)

-'

100

FREQUENCY (MHz)

FIGURE 31. OUTPUT RESISTANCE vs COLLECTOR CURRENT

FIGURE 32. FORWARD TRANSCONDUCTANCE vs FREQUENCY

7-66

CA309~CA3096A,CA3096C

Typical Performance Curves

(Continued)

91E ~E •••

!5~SI---r----Ir--+-++---+-

Yi1ii

'iii::::

; ~ 41---+--If--+++--+-.......~.
li!~
,cz
t) ~

3

~~

21--+---+

~w

2.S

a:1ii
o E
OW
Sa
w-

2.0

g~

1.S

OW
zO

f---+--+

~t:

OW
zO

1.0

ou!

!;!;

o

ill

!; ...

D.D.

O.S

D.~

ii!Oii!O

!;~

o~~~~~-~~~~~~~~~~~
1

10

00

0

100

1

10

FREQUENCY (MHz)

FIGURE 33. INPUT ADMITTANCE vs FREQUENCY

FIGURE 34. OUTPUT ADMITTANCE VB FREQUENCY
30

30

RSOURCE = 1 kG

RSOURCE = 5000

"~t\.. 'r--

~ i'..

",....

Ic=lmA

~

-

1""'- ..

~oJ~

o
0.01

~

"~

~

II

100~~

.....

r-

~~

0.1

1.0

10

0.01

100

....... .....

""

o
0.1

-

u.:

II..

-II)

100

10

FREQUF.NCY (kHz)

FIGURE 36. NOISE FIGURE VB FREQUENCY (PNP)

FIGURE 35. NOISE FIGURE vs FREQUENCY (PNP)

~

~

"""' ...

r-..,

a..

0:c:C
0:
c:C

100~

10

""r-.., r-.

I.... ~I1A
0.01

r-

.......

....... r-.

0.1

- .............. .....

~c=lmA

i'-

.......

.... ""

....
1.0

10

4
0.1

100

FIGURE 37. NOISE FIGURE VB FREQUENCY (PNP)

, 1\

1.0
COLLECTOR CURRENT (mA)

FREQUENCY (kHz)

FIGURE 38. GAIN-BANDWIDTH PRODUCT VB COLLECTOR
CURRENT (PNP)

7-67

Cw
zcd!::

1:i::!E
VCE = SV

RSOURCE = 10kG

Co:
II)..J

8

40

o

."" ~=lmA

~~

FREQUENCY (kHz)

30

100

FREQUENCY (MHz)

10

CA3096, CA3096A, CA3096C

Typical Performance Curves

(Continued)

6

5

i\

\

1\ .'"i'..

"

r--...

;:~ ~ CSI
~

I........

o

ICSE

o

2

3

4

5

6

7

8

9

10

BIAS VOLTAGE (V)

FIGURE 39. CAPACITANCE VB BIAS VOLTAGE (PNP)

Metallization Mask Layout
CA3096H

o
40- 1

10

20

30

..
1• •
1.. I

40

1_-.--

37-45

(0.940·1.143)

Dimensions in parentheses are in millimeters and are derived from the
basic inch dimensions as indicated. Grid graduations are in mils (10-3
inch).
The photographs and dimensions represent a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57 degrees Instead of 90 degrees with respect to the face of the chip.
Therefore, the isolated chip is actually 7mils (0.17mm) larger in both
dimensions.

7-68

CA3127
High Frequency NPN Transistor Array

August 1996

Features

Description

• Gain Bandwidth Product (fT)' ..........•...• >1GHz

The CA3127 consists of five general purpose silicon NPN
transistors on a common monolithic substrate. Each of the
completely isolated transistors exhibits low 111 noise and a
value of fT in excess of 1GHz, making the CA3127 useful
from DC to 500MHz. Access is provided to each of the termi·
nals for the individual transistors and a separate substrate
connection has been provided for maximum application flexi·
bility. The monolithic construction of the CA3127 provides
close electrical and thermal matching of the five transistors.

• Power Gain ..........••••..• 30dB (Typ) at 100MHz
• Noise Figure ..•......••....• 3.5dB (Typ) at 100MHz
• Five Independent Transistors on a Common Substrate

Applications
• VHF Amplifiers
• Multifunction Combinations - RF/Mixer/Osciliator

Ordering Information

• Sense Amplifiers

PART
NUMBER
(BRAND)

• Synchronous Detectors

TEMP.
RANGE ("C)

• VHF Mixers

PACKAGE

PKG.
NO.

CA3127E

·55

to 125

16 Ld PDIP

E16.3

CA3127M
(3127)

·55 to 125

16 Ld SOIC

M16.15

CA3127M96
(3127)

·55 to 125

16 Ld sole Tape and Reel M16.15

• IF Converter
• IF Amplifiers
• Synthesizers
• Cascade Amplifiers

Pinout

u.:
La.
-en
0a:

CA3127
(PDIP, SOIC)
TOP VIEW

Ow
zcd!:

en

it

~==
a:-,'--~f'r----""''''''''''';'''-O +12V

sents a close approximation in performance to a properly unilateralized single transistor of this type. The use of
0 3 in a current-mirror configuration facilitates simplified
biasing. The use of the cascode circuit in no way implies
that the transistors cannot be used individually.
5. E.F. Johnson number 160-104-1 or equivalent.

FIGURE 2. 100MHz POWER·GAIN AND NOISE-FIGURE TEST CIRCUIT

u:

u.
-en
Co:

Cw

z-

 0.6

b 11

7

8

9

-(/)

0a:
«!!:

FIGURE 12. INPUT ADMITTANCE (Y11 ) vs FREQUENCY

FIGURE 11. DC FORWARD-CURRENT TRANSFER RATIO (h FE )
vs COLLECTOR CURRENT

2

911/

o

40
0.1

1000

TA = 25°C, VCE = 6V, Ie = 1 rnA

TA = 25°C
_ VcE =6V

:::>

~

~

FIGURE 10. VOLTAGE GAIN vs FREQUENCY

Q 100
0:
0:

'-

10
100
FREQUENCY (MHz)

fiGURE 9. VOLTAGE GAIN vs FREQUENCY

!;;:

"" '"'',-'"'
......

TA = 25°C, VCE = 6V, RL = 1k.1l
FOR TEST CIRCUIT SEE FIGURE 19

1000

,"
......

5

-5

I""-

10
100
FREQUENCY (MHz)

.....

o

'"

....

I II

-10

--

CI

~

I

Ic=0.2mA

......

:;: 15

I .......... '"\

Ic =0.5mA

....

............. ,
""',

J"'oooo".

I
I
20 f - l =0.2mA
c

z

;;:

'1'"
Ic=1mA

15

.............

Ie -O.SmA

iii' 25
:!!.

Ic-SmA

20

~UJ

Ic-SmA

30 Ulc=1mA

I II

iii' 25
:!!.

I

35

I I I

30

z

...

40
TA = 25°C, VCE = 6V, RL = 1000
fOR TEST CIRCUIT SEE fiGURE 19

35

0.5

0.4
0.3
0.2
0.1

o

10

//
".

v:

J

-

~

~

=rg22

FIGURE 13. INPUT ADMITTANCE (Y11 ) vs COLLECTOR
CURRENT

8

l

7 ~
6 ~
5 ...
UJ

4
3
2

1

o

&l
iil
!5
~

0

1000

100

COLLECTOR CURRENT (mA)

~

1>:.2

FREQUENCY (MHz)

FIGURE 14. OUTPUT ADMITTANCE (Y22) vs FREQUENCY

7-73

CA3127
Typical Performance Curves

I
I

TA = 25°C
VCE=6V
f=200MHz

~

b22

0.400

~ 0.375
~

g

0_350
0.325
0_300

S

0.275

I

0.225

z

8

,"

0.175

2.8
2:6

922 ~

2.5

, 1..0"

2.3
2.1

1

2

ILW
IL U

i~

U

OZ

W
U

l!lE
E2!
ze

-20
-30

"- ~

I~

ILW

~~

l!lE 30

E
2!
ze

20

~!

10

I-

0
100

-40

921

" ' ....

-IY21 I

150

-so
-60
-70

-

-60

-90
-100
1000

200
FREQUENCY (MHz)

"- ...

~

~

~~

r---

9
12

0.4

Iii'

"

1

2

l!l~

E
2!
ze

oil!

wE
(1)a:: e

oe

a::w
ILU
oz

Ii

!illl)
:I ~

01
•

I!:

0

~
~
:ell)
... z

~

![

wa::
I2Cl
wl!l

~~

:::1
0~~

912

l!lE
E:I

~g

.I

z~

!il !l!
:Ie

1lI:1
(1)0
~e

1V121
0.21

-80
-90

-100
-110
-120
-140

o

1

-150
2 3 4 5 6 7 8 9 10 11 12
COLLECTOR CURRENT (mA)

FIGURE 18. REVERSE TRANSADMITIANCE (V12) vs
COLLECTOR CURRENT

Iii'

90
-95

"

~

'\

w
w
wa::
II)Cl
a::w
wo

~;;

a::
-100

N

~![

WW
... u
-105 Clz
zE
cr-110 w:l

~~

-115

FREQUENCY (MHz)

-120
1000

E!
I-

FIGURE 19. REVERSE TRANSADMITIANCE (YI2) vs FREQUENCY

7-74

~a:~
~![
~~

~;lf
III

Ii

i~

-130 ... !l!

I!:

... !l!
Ii'!
I-

~

100

~W:IE

-100
3 4 5 6 7 8 9 10 11 12
COLLECTOR CURRENT (mA)

W ~

V i Y121
0.2

i e.
12;
~;:
~~

9z1 _ -60

TA = 25°C
VCE =6V
1=200MHz

Iii'

W

~

ILU

O;lf 0.3

-40

I
I

i3

OW
a::1!i

FIGURE 16. FORWARD TRANSADMITIANCE (Y21l vs
COLLECTOR CURRENT

- .....

wE

w

-

-20
IY21 I

-60

TA =25°~
VcE =6V
Ic=1mA

12 ;; 0.5

-

~

~

20

o

FIGURE 17. FORWARD TRANSADMITIANCE (Y21) vs
FREQUENCY

Iii' 0.6

o

,

40

S

·10

.......

Iii'

80

I-

FIGURE 15. OUTPUT ADMITIANCE (Y22) vs COLLECTOR
CURRENT

is

\

1.9 0
3 4 5 6 7 8 9 10 11 12
COLLECTOR CURRENT (mA)

TA = 25°C
VCE =6V
Ic=1mA

TA = 25°C
VCE =6V
1.200MHz

80

~!

~

2.0

I
o

~W

II)
:::)
II)

2.2

J

o ~ 100
a::-

~

2.4

~

Iii'

S

2.7

~

,

0.250

0.200

(Continued)

~

CA3141
ge Diode Array For Commercial,
ustrial and Military Applications
Description
• Matched Monolithic Construction
- VF Match (Each Diode Pair) •..• O.55mV At IF

=1mA

• Low Diode Capacitance .••.••. O.3pF (Typ) at VR

=2V

• High Diode-to-Substrate Breakdown .••...... 30V (Min)
• Low Reverse (Leakage) Current •••••.. 100nA (Max)

Applications

The CA3141 E High Voltage Diode Array Consists of ten general purpose high reverse breakdown diodes. Six diodes are
internally connected to form three common cathode diode
pairs, and the remaining four diodes are internally connected
to form two common anode diode pairs. Integrated circuit
construction assures excellent static and dynamic matching
of the diodes, making the CA3141 extremely useful for a
wide variety of applications in communications and switching
systems.

• Balanced Modulators or Demodulators
• Analog Switches
• High-Voltage Diode Gates
• Current Ratio Detectors

Ordering Information
PART NUMBER
CA3141E

TEMP.
RANGEfc)
-55 to 125

PACKAGE
16Ld PDIP

PKG.
NO.
E16.3

Pinout

u.:
-en
o a::

CA3141
(PDIP)
TOP VIEW

LL.

Ow
zed!:

en...J
D.
~::il
a:: <
a::

<

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

7-75

File Number

906.3

CA3146, CA3146A,
CA3183, CA3183A
High-Voltage Transistor Arrays

August 1996

Features

Description

• Matched General Purpose Transistors
- VBE Match •••.•..•••..•••••.•.•.•.••• ±5mV (Max)
• Operation from DC to 120MHz (CA3146, CA3146A)
• low Noise Figure ••.•. " ..••• 3.2dB (CA3146, CA3146A)
• High IC.............. 75mA (Max) (CA3183, CA3183A)

Applications
• General Use in Signal Processing Systems in DC through
VHF Range
• Custom Designed Differential Amplifiers
• Temperature Compensated Amplifiers
• Lamp and Relay Drivers (CA3183, CA3183A)
• Thyristor Firing (CA3183, CA3183A)

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

PKG.
NO.

CA3146AE

·401085

14 Ld PDIP

E14.3

CA3146AM
(3146A)

·401085

14Ld SOIC

M14.15

CA3146AM96
(3146A)

·401085

14 Ld SOIC Tape and Reel M14.15

CA3146E

-401085

14 Ld PDIP

E14.3

CA3146M
(3146)

-401085

14 LdSOIC

M14.15

CA3146M96
(3146)

-401085

14 Ld SOIC Tape and Reel M14.15

CA3183AE

-401085

16 Ld PDIP

E16.3

CA3183AM
(3183A)

-401085

16 Ld SOIC

M16.15

CA3183AM96
(3183A)

-401085

16 Ld SOIC Tape and Reel M16.15

CA3183E

-401085

16 Ld PDIP

E16.3

CA3183M
(3183)

·401085

16 Ld SOIC

M16.15

CA3183M96
(3183)

·401085

16 Ld SOICTape and Reel M16.15

PACKAGE

The CA3146A, CA3146,CA3183A, and CA3183 are general
purpose high voltage silicon NPN transistor arrays on a common monolithic substrate.
Types CA3146A and CA3146 consist of five transistors with two
of the transistors connected to form a differentially connected
pair. These types are recommended for low power applications
in the DC through VHF range. (CA3146A and CA3146 are high
voltage versions of the popular predecessor type CA3046.)
Types CA3183A and CA3183 consist of five high current
transistors with independent connections for each transistor.
In addition two of these transistors (01 and 02) are matched
at low current (Le., 1mA) for applications where offset
parameters are of special importance. A special substrate
terminal is also included for greater flexibility in circuit
design. (CA3183A and CA3183 are high voltage versions of
the popular predecessor type CA3083.)
The types with an "A" suffix are premium versions of their
non-"A" counterparts and feature tighter control of breakdown voltages making them more suitable for higher voltage
applications.
For detailed application information, see companion Application
Note AN5296 "Application of the CA3018 Integrated 'CircuH
Transistor Array."

Pinouts
CA3146, CA3146A (PDIP, SOIC)
TOP VIEW

CA3183, CA3183A (PDIP, SOIC)
TOP VIEW

SUBSTRATE
DIFF.
PAIR

CAUTION: These devices are sensitive 10 eleclrostatic discharge. Users should follow proper IC Handling Procedures.
Copyrlghl

© Harris Corporation 1996

7-76

File Number

532.3

CA3146, CA3146A, CA3183, CA3183A
Absolute Maximum Ratings

Thermal Information

Collector-to-Emitter Voltage (VCEO):
CA3146A, CA3183A .................................. 40V
CA3146, CA3183 .................................... 30V
Collector-to-Base Voltage (VCBO):
CA3146A, CA3183A .................................. sov
CA3146, CA3183 .................................... 40V
Collector-to-Substrate Voltage (VCIO, Note 1)
CA3146A, CA3183A .................................. SOV
CA3146, CA3183 ................................... .40V
Emitter-ta-Base Voltage (VESO) all types ..................... SV
Collector Current
CA3146A, CA3146 ................................. SOmA
CA3183A, CA3183 ................................. 7SmA
Base Current (IB) - CA3183A, CA3183 ................... 20mA

Thermal Resistance (Typical, Note 2)

6JA(oCIW)

14 Ld PDIP Package ....................... .
100
14 Ld SOIC Package ....................... .
18S
16 Ld PDIP Package .....................•..
90
16 Ld SOIC Package ....................... .
17S
Maximum Power Dissipation (Any One Transistor, Note 3)
CA3146A, CA3146 ...........................••.. 300mW
CA3183A, CA3183 ............................... SOOmW
Maximum Junction Temperature (Die) ................... 17SoC
Maximum Junction Temperature (Plastic Package) ........ lS00C
Maximum Storage Temperature Range (all types) .. _65oC to lS00C
Maximum Lead Temperature (Soldering lOS) ............. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range .......................... -40°C to 8SoC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only fIItlng and opeflltion
of the device at these or any other conditions above those indicated in the opeflltional sections of this specification is not implied.

NOTES:
1. The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is
more negative than any collector voltage in order to maintain isolation between transisters, and to provide for normal transistor action. To
avoid undesired coupling between transistors, the substrate terminal should be maintained at either DC or signal (AC) ground. A suitable
bypass capacitor can be used to establish a signal ground.
2. 9JA is measured with the component mounted on an evaluation PC board in free air.
3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal
resistances to calculate the junction temperature.

Electrical Specifications

CA3146 Series
TEST CONDITIONS

PARAMETER

SYMBOL

TA=2SoC

TYPICAL
PERF.
CURVE
FIG. NO.

CA3146

MN

TYP

CA3146A

MAX

MIN

TYP

MAX

UNITS

Collector-to-Base
Breakdown Voltage

V(BR)CSO Ic= lOIlA,IE=O

Collector-la-Emitter
Breakdown Voltage

V(BR)CEO IC = lmA, IB=O

Collector-ta-Substrate
Breakdown Voltage

V(BR)CIO

Emitter-to-Base
Breakdown Voltage

V(BR)EBO IE = 101lA, IC = 0

ICI = lOIlA, IB = 0,
IE=O

-

40

30

S6

-

SO

40

72

56

-

V

Ow

V

cn-l
a..
a::-

3

~

2

~

0.75

.sw

/

:IE~

~~

!j

FE =10

V·

Iii
...r£

10

,.,

VCE=5V

TA=~OC

E

w 0.7

CI

~

II:

E
:IE

"".
0.6

"

~

"'"

..".

-75

B

I

W

2

)
IVSEI • VBE21

1

./r

!zw
II:
II:

·25

0255075
TEMPERATURE (DC)

I I

100

125

~

Iii
...r£

Iii
r£
II.

VCE =5V
TA = 25°C

1..1

1.0
~

:::)

U

~

!5...

10

-50

l

CI

0

II
0.1
1.0
EMmER CURRENT (mA)

!i!0(

a

IJ

w 0.5

10

.s>-

",.

'"

~

0.4
0.01

I
IE = O.lmA _

FIGURE 6. VIO VB TEMPERATURE FOR Ql AND Q2

3

w

~

IE=lmA _

0.50

40

-

....j....-1

0.25

FIGURE 5. VCE SAT VB Ic FOR ANY TRANSISTOR

~

.-

0

20
30
COLLECTOR CURRENT (mA)

I

IE=10mA -

o

o

0.8

I

VCE=5V

1.50

!:~ 1.25

1~

100

TEMPERATURE ('lC)

0

~

./'"

0.1

I-

...
:::)

~

0 ~

~

I...... I""'"
0.01
0.01

,0.1
1.0
COLLECTOR CURRENT (mA)
FIGURE 8. 110 vs IC FOR Ql AND Q2

FIGURE 7. VBE AND VIO VB IE FOR Ql AND Q2

7-80

10

CA3146, CA3146A, CA3183, CA3183A

Typical Performance Curves

VCE = 5V
Rs = soon
TA = 25°C

20

iii"
~

I

,/

1=10kHZJ>

~

W

5

o

0.01

f-

25
~

~

z

~

r--

10

r-- ' =10kHz

l=lkHz .......

I

o

0.01

"= lkHZ,,,,10
1= 10kHz " -

W

~z

P"""

I

5 ~

~

V
./

~r--.

'k" ~V

t::..~

/

o

1.0

0.01

./

""

1'1
/

-

........ "..,.

0.1
COLLECTOR CURRENT (rnA)
FIGURE 10. NFvB Ic AT Rs

1.0

=lkn

100
VCE=5V
I_1kHz
TA = 25°C

UI

:2 .,
-........

~

~

/

/

/

rr

",
~

_ -r--.V

~V ""........

5

rr
:::>

.,~

f=O.lkHz,

15

I

=soon

I

,

20

~

~

-

I
VCE=5V
Rs = l0000n
TA = 25°C

W

...£!W

~

0.1
COLLECTOR CURRENT (rnA)

30

I1= 0.1 kHz

15

W

~~. ~ /

FIGURE 9. NF VB Ic AT Rs

rr
:::>

iii"

I

z ",

rr
:::>
~ 10

iii"

~~

I=t ~"',/ / '

W

VCE = 5V
Rs = 1000n
TA = 25°C

20
1= 0.1 kHz

15

~z

Dynamic Characteristics (For Any Transistor) - CA3146 Series

,. /

~:;
0(

~

hOE= 15.6~S

if
.<:
0

.,

oJ

0(

L

1/

.....

W

!:lI

,

-hOE~ hFE=100
}
hiE = 2.7kn
AT
hRE = 1.88 x 10-4 lmA

. '"

~~

rr

1.0

:;

rr
z

1""",

.....

~

0

~~ i""""

-'

lL

hFE
~

hRE .....

1.0

-...I

'-l

~

0.1
COLLECTOR CURRENT (rnA)
FIGURE 11. NF VB Ic AT RS

10

-

u.:

LL.

hiE

0.1
0.01

0.1
1.0
COLLECTOR CURRENT (rnA)

-rJ)

0a:

10

Ow

z-

i

o.a
zOW

UU

~~

UlW

40

9FE ..........

20
10

·10

...

·20

~
0

I'.

J

,

b'Eh

1/

"-

0

!Ii °

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25°C, VCE =5V,lc = lmA

.........,.

30

ZU

~~
orr

6

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25°C, VCE = 5V,Ic = lmA
I

bFE

i""'oo...

~

.,.

./[..I'
f--

I
0.1

1.0

10
FREQUENCY (MHz)

o

0.1

100

FIGURE 13. YFE VB FREQUENCY

.....

91E
1.0

..oil!!!!!: V

10
FREQUENCY (MHz)

FIGURE 14. YIE VB FREQUENCY

7-81

100

CA3146, CA3146A, CA3183, CA3183A

Typical Performance Curves

Dynamic,Characteristics (For Any Transistor) - CA3146 Series (Continued)

I

COMMON EMITTER CIRCUIT, BASE INPUT
TA=2SoC, VCE =SV,lc= 1mA

COMMON EMmER CIRCUIT, BASE INPUT
TA = 25°C, VCE = 3V,Ie = lmA

gRE IS SMALL AT FREQUENCIES
LESS THAN 500MHz _........

o
beEt

I

Ib~~

-0.5

I
-1.0

--

1/

./

o

0.1

1.0

FIGURE

,/

-l.S

gOE

I

10
FREQUENCY (MHz)

-2.0

100

15_ FIGURE 15_ YOE vs FREQUENCY

TA=2SoC

1000
900

b

800

C

700

::;)

0

II:
A.

600

I:i
~
z

500

:r::

~

~

100

FIGURE 16_ FIGURE 16_ YRE VB FREQUENCY

VCE =SV
TA =2Soc

~
!.

10
FREQUENCY (MHz)

1

4

~

400

~

......

I

300

'3

r-.... .....

OJ

u

200

~

2

~
~

1 i'o..

u

100

o

o
1

2

3

4 5 6 7 8 9 10 11
COLLECTOR CURRENT (mA)
FIGURE

12 13 14

o

-

1

3

Cc~

CEB
4

5

6

7

8

9

10 11

12 13 14

BIAS VOLTAGE M

17. fT vSlc

Typical Performance Curves

r--.
2

,

-

FIGURE 18. CEB, CCB. CCI VB BIAS VOLTAGE

DC Characteristics - CA3183 Series

10-1

VCE=10V

,

=VCB=10V

C

So

,/
~

~

ffi

./

II.
II.

./
../

~
~

8

o

25
SO
TEMPERATURE (DC)

,/

~

U
II: 10-3

/

-25

/

II:
II: 10-2
::;)
U

75

10-4
-SO

100

FIGURE 19_ ICEO va TEMPERATURE FOR ANY TRANSISTOR

--

-25

./

./
o

25
50
TEMPERATURE (OC)

75

100

AGURE 20. ICBO VB TEMPERATURE FOR ANY TRANSISTOR

7-82

CA3146, CA3146A, CA3183, CA3183A

Typical Performance Curves

DC Characteristics - CA31 83 Series (Continued)

I II

TA = 250C

VCE=3V
100
125

ffi 1!100
11:_

!!i2
~~

!i:~

90

!!i2
u!;(

80

W.c
11:_

~

-

75

11:11:

i~ 50
OZ
I&. Ql! 25

81-

o

-50

~ II'
~

.....

ell: 70

h
II:U)

Ic=lmA

-25

I

0

25

~

11:11:

IC=O.lmA

/~

~

VCE =3V

ull:
el- 50

50

75

40

100

0.1

1.0
10
COLLECTOR CURRENT (mA)

TEMPERATURE (DC)

FIGURE 21. hFE vs TEMPERATURE FOR ANY TRANSISTOR

IIII

0.9

~
W 0.8

r- TA=700C

,

~

!:i
§!

0.7

W

0.6 ~

W

0.5 1--

II:

§
12
W

~

0.4

I

TA= 250C
-

-----

~i""

~
1.0

/

./

II:S;

w-

/

~~
12§!

./

I:~

"""""

II:Z

~~

~

:J:::>

8~

III

0.3
0.1

~

TA 250 C
hFE 10

;:::~ ~
I-~

FIGURE 22. hFE vs 'C FOR ANY TRANSISTOR

=
=

T~JOJ

-- -~ -I-

I",

.... """"

60

OZ

I&.C

.......... 'c = 10mA
(

VCE=10V

V

/

u.:

0.1
10

1.0
10
COLLECTOR CURRENT (mA)

100
COLLECTOR CURRENT (mA)

FIGURE 23. VBE vs IC FOR ANY TRANSISTOR

LL
-en
0a:

Ow

z-

«!!:
en..J
a.
~:il

FIGURE 24. V CE SAT vs Ic FOR ANY TRANSISTOR

a:«

~

VCE=3V

~A ~ OOC
TA=25 oC

I- TA =700C

C

\.

,

I\.

'\

,..

II:
II:

~-

~

8

Iii

-

~

~

~C

0.1
0.1

1.0
COLLECTOR CURRENT (mA)

~

. /~

~
;!;

10

RGURE 25. 'VIO' vs 'C FOR DIFFERENTIAL AMPUAER (Q1 AND Q:!)

V

,

~

~

".

1.0

~

~

~
;!;

I

,

VCE=3V
TA = 25 0C

!i:w

"'

"

0.1
0.1

1.0
COLLECTOR CURRENT (mA)

10

FIGURE 26. 1110' vs IC FOR DIFFERENTIAL AMPURER (Ql AND Q2)

7-83

CA3227, CA3246

~HARR.lS

\K.J

SEMICONDUCTOR

High-Frequency NPN Transistor Arrays For LowPower Applications at Frequencies Up to 1.SGHz

August 1996

Features

Description

• Gain-Bandwidth Product (fT) •••.•••.••...•• >3GHz

The CA3227 and CA3246 consist of five general purpose silicon NPN transistors on a common monolithic substrate.
Each of the transistors exhibits a value of fT in excess of
3GHz, making them useful from DC to 1.5GHz. The monolithic construction of these devices provides close electrical
and thermal matching of the five transistors.
.

• Five Transistors on a Common Substrate

Applications
• VHF Amplifiers

Ordering Information

• VHF Mixers

PART
NUMBER
(BRAND)

• Multifunction Combinations - RF/Mlxer/Oscillator
• IF Converter
• IF Amplifiers
• Sense Amplifiers
• Synthesizers
• Synchronous Detectors

TEMP.
RANGE ("C)

PACKAGE

PKG.NO.

CA3227E

·55 to 125

16 Ld PDIP

E16.3

CA3227M
(3227)

-55 to 125

16 Ld SOIC

M16.15

CA3227M96
(3227)

-55 to 125

16 Ld SOIC Tape
and Reel

M16.15

CA3246E

-55 to 125

14 Ld PDIP

E14.3

CA3246M
(3246)

·55 to 125

14 LdSOIC

M14.15

CA3246M96
(3246)

·55 to 125

14 Ld SOIC Tape
and Reel

M14.15

• Cascade Amplifiers

Pinouts
CA3246
(PDIP, SOIC)
TOP VIEW

CA3227
(PDIP, SOIC)
TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

7-84

File Number

1345.3

CA3227, CA3246
Absolute Maximum Ratings

Thermal Information

Collector-to-Emitter Voltage (V CEQ) ....................... 8V
Collector-to-Base Voltage (VCBO )' ....................... 12V
Collector-to-Substrate Voltage (VCIO, Note 1) .............. 20V
Collector Current (Iel ................................ 20mA

Thermal Resistance (Typical, Note 2)

Operating Conditions
Temperature Range ......................... -55°C to 125°C

8JA (OCIIN)
100
14 Ld PDIP Package. . . ... . . . . . . ... . ... . . . ..
14 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . .
185
16 Ld PDIP Package. . . . . . . . . . . . . . . . . . . . . . . .
90
16 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Power Dissipation (Any One Transistor) ......... 85mW
Maximum Junction Temperature (Die) .................. 175°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. The collector of each transistor of these devices is isolated from the substrate by an integral diode. The substrate (Terminal 5
(CA3227) and Terminal 13 (CA3246)) must be connected to the most negative point in the external circuit to maintain isolation be
tween transistors and to provide for normal transistor action.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

TA = 25°C

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DC CHARACTERISTICS FOR EACH TRANSISTOR
Collector-to-Base Breakdown
Voltage

V(BR)CBO

Ic= lOIlA,IE= 0

12

20

V

Collector-to-Emitter Breakdown
Voltage

V(BR)CEO

Ic = 1rnA, IB = 0

8

10

V

Collector-to-Substrate Breakdown
Voltage

V(BR)CIO

ICl = 10llA, IB = 0, IE = 0

20

-

V

Emitter-Cutofl-Current (Note 3)

lEBO

V EB = 4.5V, Ic = 0

-

-

10

IlA

Collector-Cutofl-Current

ICEO

V CE =5V,I B =0

-

1

IlA

-II)

Collector-Cutofl-Current

ICBO

V cB =8V,I E =0

-

100

nA

Ow

DC Forward-Current Transfer Ratio

hFE

VCE =6V

110

-

Ic= lOrnA
Ic=lmA

VBE

VCE =6V

Collector-to-Emitter Saturation
Voltage

VCESAT

Ic = lOrnA, IB = lmA

Base-to-Emitter Saturation Voltage

VBESAT

Ic = lOrnA, IB = lmA

Ic= lmA

«!!:
fl.

~==
a:«
a:
«

150

0.62

0.71

0.82

V

0.13

0.50

V

0.94

V

150

0.74

NOTES:
3. On small-geometry, high-frequency transistors, it is very good practice never to take the Emitter Base Junction into reverse breakdown. To do so may permanently degrade the h FE . Hence, the use of lEBO rather than V(BR)EBO' These devices are also susceptible
to damage by electrostatic discharge and transients in the circuits in which they are used. Moreover, CMOS handling procedures
should be employed.
,.,

7-85

0a:
z-

II)..J

40

Ic=O.lmA
Base-to-Emitter Voltage

u.:

LL

CA3227, CA3246
Electrical Specifications

TA = 2SoC. 200M Hz. Common Emitter. Typical Values Intended Only for Design Guidance

PARAMETER

TEST CONDITION

SYMBOL

TYPICAL
VALUES

UNITS

DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR
Input Admittance

Y11

b11

Ic= 1mA. VCE=SV

g11
Output Admittance

Y22

b22

Ic = 1mA. VCE = SV

g22
Forward Transfer Admittance

Y 21

Y21

Ic = 1mA. VCE = SV

821
Reverse Transfer Admittance

Y 12

Y 12

Y 11

b 11

Output Admittance

Y 22

b22

Forward Transfer Admittance

Y21

Y21

Reverse Transfer Admittance

Y 12

Y 12

2.7

mS

0.13

mS

29.3

mS

-33

Degrees
mS
Degrees

Ic = 10mA. VCE = SV

4.B

mS

2.BS

mS

Ic = 10mA. VCE = SV

2.7S

mS

0.9

mS

Ic = 10mA. VCE = SV

9S

mS

-62

Degrees

Ic = 10mA. VCE = SV

0.39

mS

-97

Degrees

g22

821

812
h21

mS

-97

g11

Small Signal Forward Current Transfer Ratio

mS

0.38

Ic = 1mA. VCE = SV

812
Input Admittance

4
0.7S

Ic = 1mA. VCE = SV

7.1

Ic = 10mA. VCE = SV

17

VCB=6V

0.3

TYPICAL CAPACITANCE AT 1 MHz, THREE-TERMINAL MEASUREMENT
Collector-to-Base Capacitance

CCB

pF

Collector-to-Substrate Capacitance

CCI

V cl =6V

1.6

pF

Collector-to-Emitter Capacitance

CCE

VCE=6V

0.4

pF

Emitter-to-Base Capacitance

C EB

V EB =3V

0.7S

pF

Spice Model

(Spice 2G.6)

.model NPN

+

BF = 2.610E + 02

BR = 4.401E + 00

IS = 6.930E - 16

RB = 130.0E + 00

+

RC = 1.000E + 01

RE = 7.396E - 01

VA = 6.300E + 01

VB = 2.208E + 00

+

IK = 1.000E - 01

ISE = 1.B7E - 14

NE = 1.6S3E + 00

IKR = 1.000E - 02

+

ISC = 9.25E -14

NC = 1.333E + 00

TF = 1. 77SE - 11

TR = 1.000E - 09

+

CJS = 1.800E - 12

CJE = 1.010E - 12

PE = 8.3S0E - 01

ME = 4.460E - 01

MC = 2.740E - 01

KF = O.OOOE + 00

4;.

+

CJC = 9.100E -13

PC = 3.BSOE - 01

+

AF = 1.000E + 00

EF = 1.000E + 00

FC = S.OOOE - 01

PJS = S.410E - 01

+

MJS = 3.S30E - 01

RBM=30.00

RBV= 100

IRB = 0.00

Please Note: No measurements have been made to model the reverse AC operation (tr is an estimation).

7-86

CA3227, CA3246

Typical Performance Curves
160
150
140
130 ~
120
110
100
90
80
70
60
50
40
30
VCE = 6V, TA = 25°C
20
1.0
0.1

3.5

...

II!

.c

VCE

=5V, TA =25°C ~

3.0

"

I'\.

2.5

,

'N

2.0

~
.&'

1.5

:J:

I

1.0

/

I

0.5
10

/

/

o :'
o

100

10

5

IclmA)

FIGURE 2. fT vs COLLECTOR CURRENT

FIGURE 1. hFE vs COLLECTOR CURRENT

RSOURCE
30

=5000, VCE =6V, TA =25°C
FREQUENCY

m

~

V

w

III

0

z
10

-...

~~

~

~

1kH.!,.

20

!!lz

~!;

10

io"""

......... ..... "

,

~~

-

~~

~~

0.1

=10Hz

/'

w

100kHz

I
0.01

~

I I I L

I,.oo'~

II:

1~

"

FREQUENCY

w

~

I"

I

a

w

20

=1kO, VCE =av, TA =25°C
I II111

30

=10H~

II:

~

RSOURCE

~

11111111111,/

m

a

15

IclmA)

1.0

0.01

10.0

~
'f'"

100HZ

~

~ ~'

H1'

1~ ~'

"'1ookHz
~
I
1.0

0.1

IclmA)

IclmA)

10.0

u:

II-

-(J)

0a:
Ow

zed':
(J)..J

FIGURE 3. NOISE FIGURE vs COLLECTOR CURRENT

FIGURE 4. NOISE FIGURE vs COLLECTOR CURRENT

Il.

~:E

a:

fI'

r,

I.)

a: 10

~
UI
..J
..J

I--

C

100m I- VCE=3V

1....-

Ie =12011A

c;....

./

-=
V

0

1

2

3

I

I

I

"'"

4

~

./

Ie =4O"A

I

.I~

II

Ie = 16011A..;;

le=80"A~

5

8

I

Ie =2ool1A -

1"
0.5

5

V

V

V

/'

./

/

"'"

-

-

./

0.6

0.7

0.8

0.9

1.0

BASE TO EMITTER VOLTAGE (V)

COLLECTOR TO EMITTER VOLTAGE (V)

RGURE 1. NPN COLLECTOR CURRENT vs COLLECTOR TO
EMITTER VOLTAGE

FIGURE 2. NPN COLLECTOR CURRENT AND BASE CURRENT
TO EMITTER VOLTAGE

10.0

VCE=3V

'N

:z:

~ 8.0

z

180

\j

140

co

:cCI

120

UI

80

tz

a:
a:

:::>

I.)
I.)

co

:::>

.......

100

~
A.

~

.~

\

60
40

~

100"

1m

\

:cCI

100m

10m

4.0

z
~ 2.0
Z

20
10"

6.0

u::

u.

0
0.1

1.0

COLLECTOR CURRENT (A)

10

100

COLLECTOR CURRENT (mA)

FIGURE 3. NPN DC CURRENT GAIN vs COLLECTOR CURRENT

-en

o a::

Ow

z-

FIGURE 4. NPN GAIN BANDWIDTH PRODUCT vs COLLECTOR
CURRENT (UHF 3 x 50 WITH BOND PADS)

c

11.

~:s

<

HFA3102
Electrical Specifications

SYMBOLS
ITRENCHLEAKAGE

TA = 25°C (Continued)

PARAMETER

TEST CONDITIONS

Collector-to-Collector Leakage
(Pin 6, 7,13, and 14)

,,wTEST=SV

(NOTE 2)
TEST
LEVEL

ALL GRADES
MIN

TYP

MAX

UNITS

B

-

0.D1

-

nA

NOTE:
2. Test Level: A. Production Tested; B. Typical or Guaranteed Urnit Based on Characterization; C. Design Typical for Information Only

PSPICE Model for a Single Transistor
.Model NUHFARRY NPN
+ (IS= 1.840E-16
+ VAR= 4.500E+OO

XTI= 3.000E+OO
BF= 1.036E+02

+IKF= 5.400E-02

XTB= O.OOOE+OO

+ NC= 1.800E+OO

IKR= 5.400E-02

+ MJC= 2.400E-01

VJC= 9.700E-01

EG= 1.110E+OO

VAF= 7.200E+01

ISE= 1.686E-19

NE= 1.400E+OO

BR= 1.000E+01

CJC= 3.980E-13

FC= 5.000E-01

CJE= 2.400E-13
TF= 10.51 E-12

+ MJE= 5.1 OOE-01

VJE= 8.690E-01

TR= 4.000E-09

+ ITF= 3.500E-02

XTF= 2.300E+OO

VTF= 3.500E+OO

+ XCJC= 9.000E-01
+ RE= 1.848E+OO

CJS= 1.689E-13
RB= 5.007E+01

ISC= 1.605E-14

RC= 1.140E+01

VJS= 9.982E-01
RBM= 1.974E+OO

PTF= O.OOOE+OO
MJS= O.OOOE+OO
KF= O.OOOE+OO

+ AF= 1.000E+OO)

7-112

HFA3102
Common Emitter S-Parameters
VeE

=SV and Ie =SmA

FREQ.(Hz)

ISlll

PHASE(Sll)

IS121

PHASE(S12)

IS211

PHASE(S21)

IS221

PHASE(S22)

1.0E+08
2.0E+08
3.0E+08
4.0E+08
5.0E+08
6.0E+08
7.0E+08
8.0E+08
9.0E+08
1.0E+09
1.1E+09
1.2E+09
1.3E+09
1.4E+09
1.5E+09
1.6E+09
1.7E+09
1.8E+09
1.9E+09
2.0E+09
2.1E+09
2.2E+09
2.3E+09
2.4E+09
2.5E+09
2.6E+09
2.7E+09
2.8E+09
2.9E+09
3.0E+09

0.833079
0.791776
0.734911
0.672811
0.612401
0.557126
0.508133
0.465361
0.428238
0.396034
0.368032
0.343589
0.322155
0.303268
0.286542
0.271660
0.258359
0.246420
0.235659
0.225923
0.217085
0.209034
0.201678
0.194939
0.188747
0.183044
0.177780
0.172909
0.168394
0.164200

-11.7873
-22.8290
-32.6450
-41.0871
-48.2370
-54.2780
-59.4102
-63.8123
-67.6313
-70.9834
-73.9591
-76.6285
-79.0462
-81.2548
-83.2880
-85.17.23
-86.9292
-88.5759
-90.1265
-91.5925
-92.9836
-94.3076
-95.5713
-96.7803
-97.9395
-99.0530
-100.124
-101.156
-102.152
-103.114

1.418901 E-02
2.695740E-02
3.750029E-02
4.572138E-02
5.194147E-02
5.659943E-02
6.009507E-02
6.274213E-02
6.477134E-02
6.634791 E-02
6.758932E-02
6.857937E-02
6.937837E-02
7.003020E-02
7.056718E-02
7.101343E-02
7.138717E-02
7.170231E-02
7.196964E-02
7.219757E-02
7.239274E-02
7.256046E-02
7.270498E-02
7.282977E-02
7.293764E-02
7.303093E-02
7.311157E-02
7.318117E-02
7.324107E-02
7.329243E-02

78.8805
68.6355
59.5861
51.9018
45.5043
40.2112
35.8226
32.1594
29.0743
26.4506
24.1974
22.2441
20.5358
19.0293
17.6908
16.4930
15.4143
14.4370
13.5469
12.7319
11.9824
11.2901
10.6480
10.0503
9.49212
8.96908
8.47753
8.01430
7.57661
7.16204

11.0722
10.5177
9.75379
8.91866
8.10511
7.35944
6.69712
6.11750
5.61303
5.17405
4.79104
4.45546
4.15997
3.89845
3.66577
3.45770
3.27074
3.10197
2.94897
2.80969
2.68243
2.56573
2.45837
2.35928
2.26756
2.18243
2.10322
2.02934
1.96027
1.89556

168.576
157.897
148.443
140.361
133.569
127.882
123.102
119.047
115.571
112.556
109.913
107.570
105.472
103.576
101.849
100.262
98.7956
97.4307
96.1533
94.9515
93.8156
92.7373
91.7097
90.7271
89.7844
88.8775
88.0026
87.1565
86.3366
85.5404

0.976833
0.930993
0.868128
0.799886
0.734033
0.674392
0.622181
0.577269
0.538952
0.506365
0.478663
0.455091
0.435008
0.417872
0.403238
0.390735
0.380056
0.370947
0.363195
0.356623
0.351081
0.346442
0.342599
0.339458
0.336942
0.334982
0.333518
0.332499
0.331879
0.331620

-11.0509
-21.3586
-30.4451
-38.1641
-44.5998
-49.9370
-54.3777
-58.1022
-61.2587
-63.9647
-66.3116
-68.3702
-70.1958
-71.8314
-73.3108
-74.6609
-75.9030
-77.0544
-78.1288
-79.1377
-80.0903
-80.9942
-81.8557
-82.6802
-83.4719
-84.2347
-84.9716
-85.6853
-86.3781
-87.0518

VeE

=SV and Ie =10mA

FREQ. (Hz)

ISlll

PHASE(Sll)

IS121

PHASE(S12)

IS211

PHASE(S21)

IS221

PHASE(S22)

1.0E+08
2.0E+08
3.0E+08
4.0E+08
5.0E+08
6.0E+08
7.0E+08
8.0E+08
9.0E+08
1.0E+09
1.1E+09
1.2E+09
1.3E+09
1.4E+09
1.5E+09
1.6E+09
1.7E+09
1.8E+09
1.9E+09
2.0E+09
2.1E+09
2.2E+09
2.3E+09
2.4E+09
2.5E+09
2.6E+09
2.7E+09
2.8E+09
2.9E+09
3.0E+09

0.728106
0.670836
0.600268
0.531768
0.471795
0.421506
0.379961
0.345693
0.317301
0.293608
0.273680
0.256782
0.242344
0.229918
0.219152
0.209767
0.201539
0.194288
0.187867
0.182157
0.177056
0.172484
0.168370
0.164656
0.161293
0.158239
0.155458
0.152919
0.150595
0.148463

-16.4319
-31.2669
-43.7663
-54.0028
-62.3880
-69.3569
-75.2612
-80.3608
-84.8420
-88.8381
-92.4452
-95.7336
-98.7555
-101.551
-104.150
-106.577
-108.851
-110.988
-113.001
-114.902
-116.698
-118.399
-120.D12
-121.542
-122.996
-124.378
-125.694
-126.947
-128.140
-129.279

1.273920E-02
2.342300E-02
3.132521 E-02
3.681579E-02
4.057046E-02
4.316292E-02
4.499071 E-02
4.631140E-02
4.728948E-02
4.803091 E-02
4.860515E-02
4.905871 E-02
4.942344E-02
4.972158E-02
4.996903E-02
5.017730E-02
5.035491 E-02
5.050825E-02
5.064218E-02
5.076045E-02
5.086598E-02
5.096107E-02
5.104755E-02
5.112690E-02
5.120031E-02
5.126876E-02
5.133304E-02
5.139381E-02
5.145164E-02
5. 150697E-02

75.4177
62.8941
52.5891
44.5019
38.2308
33.3405
29.4764
26.3755
23.8481
21.7581
20.0070
18.5224
17.2505
16.1506
15.1915
14.3490
13.6040
12.9411
12.3482
11.8151
11.3338
10.8974
10.5001
10.1373
9.80479
9.49919
9.21750
8.95716
8.71595
8.49194

15.1273
13.9061
12.3970
10.9257
9.62995
8.53559
7.62375
6.86423
6.22797
5.69057
5.23257
4.83873
4.49716
4.19854
3.93554
3.70234
3.49428
3.30758
3.13919
2.98658
2.84766
2.72068
2.60420
2.49697
2.39793
2.30619
2.22098
2.14162
2.06753
1.99820

165.227
152.045
141.185
132.570
125.781
120.378
116.005
112.398
109.365
106.771
104.518
102.532
100.759
99.1602
97.7028
96.3629
95.1215
93.9633
92.8761
91.8500
90.8766
89.9494
89.0626
88.2115
87.3920
86.6007
85.8348
85.0916
84.3690
83.6651

0.959692
0.886232
0.796016
0.708892
0.633146
0.570209
0.518803
0.476987
0.442915
0.415044
0.392146
0.373261
0.357640
0.344698
0.333974
0.325102
0.317789
0.311800
0.306940
0.303051
0.300003
0.297686
0.296007
0.294889
0.294266
0.294081
0.294285
0.294836
0.295696
0.296834

-14.2688
-26.9507
-37.3172
-45.4503
-51.7704
-56.7206
-60.6598
-63.8540
-66.4948
-68.7193
-70.6269
-72.2899
-73.7620
-75.0832
-76.2840
-77.3877
-78.4122
-79.3715
-80.2768
-81.1365
-81.9578
-82.7460
-83.5057
-84.2405
-84.9533
-85.6466
-86.3223
-86.9822
-87.6275
-88.2595

7-113

u.:

U.

-I/)

00::

Ow
zoCt!!:

1/)...1

D..

~==
oCt

0::
0::

oCt

HFA3102
Typical Performance Curves
140

12

\
\.

la" 15011A

120

10

la = 12011A

100

8
la =9011A

II!

6

.c

la = GOllA

4

o

I

o

60

40

Iia = 301lA1

2

""""" ~,

60

20

I

2

3

4

10-6

5

FIGURE 1. IC

VB

10-4
Ie (A)

VeE (V)

FIGURE 2. hFE VB Ic

VCE

12
VeE .. 5V

10.2

1-----1------+::...--=:::-.-1

~

10

I

~

II
4
2

0.6

VaE (V)

0.8

FIGURE 4. ". VB Ic

4.8

'"

iii' 4.4
~

'"

a:

4.2

~

4.0

::I

w

z~

,

r'\.

.""'/

3.8

V

3.4

o

----

~

0.5

"V
1.0

1.5

/

20
18
1&
14

V

12

iii'
~

"f;;

10 !II

~

3.6

3.2

-¢
~

II"

1.0

FIGURE 3. GUMMEL PLOT

4.6

v

~

2.0

8
6

I". 4

2.5

.1~"'---""'.2Oo,---"'.1"'0---0"""-~-'10

3.0

PIN. INPUT POWER (dBm)

FREQUENCY (GHz)

FIGURE 5. GAIN AND NOISE FIGURE VB FREQUENCY

FIGURE 6. P1dB AND 3RD ORDER INTERCEPT

7·114

HFA3102

Die Characteristics
PASSIVATION:

PROCESS:
UHF-1

Type: Nitride
Thickness: 4kA ±O.5kA

DIE DIMENSIONS:

SUBSTRATE POTENTIAL (Powered Up):

53 mils x 52 mils x 14 mils
1340llm x 1320llm x 355.61lm

Floating

METALIZATION:
Type: Metal 1: AICu(2°/~mW
Thickness: Metal 1: akA ±O.5kA
Type: Metal 2: AICu(2"1o)
Thickness: Metal 2: 16kA ±O.akA

Metallization Mask Layout
HFA3102
TOP VIEW

1340I'm
(53 mils)

- - - - - - - - 1320J1m
1•
(52 mils)

Pad numbers correspond to the 14 pin SOIC pinout.

7-115

-I

8
SPECIAL ANALOG CIRCUITS

PAGE
SPECIAL ANALOG CIRCUIT DATA SHEETS

CA555, CA555C,
LM555, LM555C

Timers for Timing Delays and Oscillator Application
in Commercial, Industrial and Military Equipment .................................... .

8-3

CA1391, CA1394

TV Horizontal Processors ...................................................... .

8-9

CA2111A

FM IF Amplifier-Limiter and Quadrature Detector .................................... .

8-13

CA3012

FM IF Wideband Amplifier ...................................................... .

8-18

CA3088E

AM Receiver Subsystem and General-Purpose Amplifier Array ......................... .

8-23

CA3089

FM IF System ............................................................... .

8-27

CA3126

TV Chroma Processor ......................................................... .

8-33

CA3154

TV SynC/AGC/Horizontal Signal Processor ......................................... .

8-42

CA3189

FM IF System ............................................................... .

8-48

CA3224E

Automatic Picture Tube Bias Control Circuit ........................................ .

8-56

CA3256

25MHz, BiMOS Analog Video Switch and Amplifier .................................. .

8-61

CD22402

Sync Generator for TV Applications and Video Processing Systems ..................... .

8-62

HA-2546

30M Hz, Voltage Output, Two Quadrant Analog Multiplier. ............................. .

8-73

HA-2547

100MHz, Two Quadrant, Current Output, Analog Multiplier ............................ .

8-87

HA-2556

57MHz, Wideband, Four Quadrant, Voltage Output Analog Multiplier .................... .

8-88

HA-2557

130MHz, Four Quadrant, Current Output Analog Multiplier ............................ .

8-102

00

HA7210, HA7211

10kHz to 10MHz, Low Power Crystal Oscillator ..................................... .

8-103

en

HFA5250

500MHz, Ultra High Speed Monolithic Pin Driver .................................... .

8-116

HFA5251

800M Hz Monolithic Pin Driver ................................................... .

8-117

HFA5253

800M Hz, Ultra High-Speed Monolithic Pin Driver .................................... .

8-128

ICL8013

1MHz, Four Quadrant Analog Multiplier ........................................... .

8-145

ICL8038

Precision Waveform GeneratorNoltage Controlled Oscillator........................... .

8-153

ICM7242

Long Range Fixed Timer ....................................................... .

8-163

ICM7555, ICM7556

General Purpose Timers ....................................................... .

8-170

8-1

CJ

0

.....I

«en
z!::
«:;:)
.....10
«a:

w
no

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

CA555, CA555C,
LM555, LM555C

HARRIS
SEMICONDUCTOR

Timers for Timing Delays and Oscillator Application
in Commercial, Industrial and Military Equipment

November 1996

Features

Description

•
•
•
•
•
•

The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing accurate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately controlled free running frequency and duty cycle with only two
external resistors and one capacitor.

Accurate Timing From Microseconds Through Hours
Astable and Monostable Operation
Adjustable Duty Cycle
Output Capable of Sourcing or Sinking up to 200mA
Output Capable of Driving TTL Devices
Normally ON and OFF Outputs
High Temperature Stability ..••.....•••.. O.005"1af1C
• Directly Interchangeable with SE555, NE555, MC1555,
and MC1455

Applications
• Precision Timing
• Sequential Timing
• Time Delay Generation

• Pulse Generation
• Pulse Detector
• Pulse Width and Position
Modulation

Ordering Information
PART NUMBER
(BRAND)
CA0555E
CA0555M (555)
CA0555M96 (555)
CA0555T

TEMP.
RANGE ("C)
PACKAGE
-5510125 BLd PDIP
-5510125 BLdSOIC
-5510125
-5510125
01070

PKG.
NO.
EB.3
MB.15
TB.C

B Ld PDIP

EB.3

01070

BLd SOIC

MB.15

CA0555CM96 (555C)
CA0555CT

01070
o to 70

B Ld SOIC t
B Pin Metal Can
BLd PDIP
B Ld PDIP

01070
01070
LM555CN
NOTE: t Denotes Tape and Reel
LM555N

These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.

MB.15

BLdSOICt
B Pin Metal Can

CA0555CM (555C)

CA0555CE

The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal,and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.

MB.15
TB.C
EB.3
EB.3

"o< ....

...IU)

z_
<::l
...10

..10


....

4.0

E.

/

10

:i

3.5

~

3.0

t(

,/

2.5

g

2.0

/

/

w

"~

..".

o

10

20

30

40

50

60

70

POSITIVE PULSE WIDTH AT TERMINAL 1 (JUI)

FIGURE 2. DUlYCYCLEATTHEPRE-DRIVEOUTPUT(TERMINAL
1) AS IT IS AFFECTED BY THE INPUT AT TERMINAL 8

v+

24V

0.47/lF
+150V

~
r---I----+ O.O~

2
2.7kO

t-...J15"'0"'kO
7

6

5

CA1394
22.Q

0.1~~
390kQ

-u-

1.2kO

20Vp_p

5JU1

FIGURE 3. TYPICAL CIRCUIT APPLICATION

8-12

f

3.9kO

-v60Vp.p
10JUI

CA2111A

I-I.ARRIS
SEMICONDUCTOR

FM IF Amplifier-Limiter
and Quadrature Detector

November 1996

Features

Description

• Input Limiting Voltage At 10.7MHz ........... 400llV

The CA2111 A provides a multistage wideband amplifierlimiter, a quadrature detector, and an emitter-follower output
stage. This device is designed for use in FM receivers and in
the sound IF sections of TV receivers. In addition, an output
terminal is provided which allows the use of the amplifierlimiter as a straight GOdB wideband amplifier.

• Input Limiting Voltage At 4.5, 5.5MHz ........ 250llV
• Typical AM Rejection At 10.7MHz ............. 45dB
• Provision for Output from 3-Stage IF Amplifier Section
• Low Harmonic Distortion
• Quadrature Detection Permits Simplified Single-Coil
Tuning
• Extremely Low AFC Voltage Drift Over Full Operating
Temperature Range

The amplifier-limiter features the excellent limiting characteristic of 3 cascaded differential amplifiers. The quadrature
detector requires only one coil in the associated outboard
circuit and therefore, tuning is a simple procedure.
A unique feature of the CA2111 A is its exceptionally low
AFC voltage drift over the full operating-temperature range.

• Minimum Number of External Components Required

Ordering Information
Applications
PART NUMBER

• FM IF Sound

TEMP.
RANGE (oC)
·40 to 85

CA2111AE

• TV Sound IF

Pinout

PACKAGE
14Ld PDIP

PKG.
NO.
E14.3

Block Diagram
CA2111A
(PDlP)
TOP VIEW

AUDIO OUT 1

v+
+12V

._~ ~

4 DE-EMPHASIS

__

REF BIAS 2

__ 9

Cl

o
etlz_

2 QUADRATURE INPUT

..JU)

11 QUADRATURE IN BUF

et::;)

DC FB BYPASS 5

0 HIGH IF OUTPUT

..JO

INPUT BYPASS 6

9 LOW IF OUTPUT

00
w

eta:
11.

GROUND 7

U)

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

8-13

File Number

612.1

CA2111A
Absolute Maximum Ratings

Thermal Information

TA = 25°C

Supply Voltage (V+ to V-) .............................. 16V

Thermal Resistance (Typical, Note 1)

6JA (,CfW)

PDIP Package.............. ...............
150
Maximum Junction Temperature (Plastic Package) ...•.... 150°C
Maximum Storage Temperature Range ........ , -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300°C

Operating Conditions

Temperature Range .......................... -40°C to 85°C
Supply Voltage Range (Typical) . . . . • • . • . . • . . • . . • • .. BV to 12V
CAUTION: Stresses above those listed In "Absolute Maximum RaUngs' may cause permanent damage to the device. This is a stress only tatlng and opetatlon
of the device at these or any other conditions above those Indicated In the opetational sections of this specification is not implied.
NOTES:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications
PARAMETER
Terminal 1 DC Voltage

TA = 25°C Unless Otherwise Specified
SYMBOL
Vl

TEST CONDITIONS

-

V+= 12V
V+=8V

Terminals 4,5,6,10 DC Voltage
Terminals 2,12 DC Voltage
Supply Current, Pin 13

TYP
5.4
3.7

V4, 5, 6,10

V+=8V

1.35

V2,12

V+=BV

3.5

113

V+=8V

-

V+= 12V
Amplifier Input Resistance

MIN

R4

Amplifier Input capacitance

C4

Detector Input Resistance

R12

Detector Input Capacitance

C12

fo= 10.7MHz

-

-

UNITS
V
V
V
V

14

-

rnA

16

-

rnA
kQ

2.7

-

Q

-

Q

7
11
70

-

MAX

Amplifier Output Resistance

Rl0

60

Detector Output Resistance

Rl

200

De-emphasis Resistance

R14

B.8

pF

kQ
pF

kQ

DYNAMIC CHARACTERISTICS fa = 10.7MHz, AI = ±75kHz, V+ = BV, FM Modulation Frequency = 400Hz, Source Resistance = 50Q
Input Limiting Thrashold Voltage
AM Rejection
Amplifier Voltage Gain
Detector Recovered Audio Output
Total Harmonic Distortion

VI(LlM)
AMR

VI = 10mVRMS, 100% FM, 30% AM

Av

VI= 5OIlVRMS

VO(AF)

VI= 10mVRMS

THO

VI= 10mVRMS

-

400

600

IlV RMS

37

-

dB

55

-

dB

0.3

-

VRMS

1

-

%

DYNAMIC CHARACTERISTICS fa = 10.7MHz, Af = ±75kHz, V+ = 12V, FM Modulation Frequency = 400Hz, Source ReSistance = 50Q
Input Limiting Threshold Voltage
AM Rejection
Amplifier Voltage Gain
Detector Reoovered Audio Output
Total Harmonic Distortion

VI(LIM)
AMR

VI = 10mVRMS, 100% FM, 30% AM

-

400

600

IlV RMS

45

-

dB

-

dB

Av

VI= 5OIlVRMS

55

VO(AF)

VI = 10mVRMS

0.48

THO

VI= 10mVRMS

1

-

VRMS
%

DYNAMIC CHARACTERISTICS fa = 4.5MHz, AI = ±25kHz, V+ = 12V, FM Modulation Frequency = 400Hz, Source Resistance = 50Q
Input Limiting Threshold Voltage
AM Rejection

VI(LIM)
AMR

VI = 10mVRMS, 100% FM, 30% AM

8-14

250

400

IlV RMS

36

-

dB

CA2111A
Electrical Specifications
PARAMErER

TA = 25°C Unless Otherwise Specified (Continued)
SYMBOL

Amplifier Voltage Gain
Detector Recovered Audio Output
Total Harmonic Distortion

MIN

TYP

MAX

UNITS

Av

VI = 50l1VRMS

TEST CONDITIONS

·

60

·

dB

VO(AF)

VI = 10mVRMS

·

0.72

·

VRMS

THO

VI= 10mVRMS

·

1.5

·

%

DYNAMIC CHARACTERISTICS fo = 5.5MHz,.6.f = ±50kHz, V+ = 12V, FM Modulation Frequency = 400Hz, Source Resistance = 500
Input Limiting Threshold Voltage
AM Rejection

VI(LlM)
VI = 10mVRMS, 100% FM, 30% AM

AMR

Amplifier Voltage Gain
Detector Recovered Audio Output
Total Harmonic Distortion

Test Circuit
v+

·

250

400

I1V RMS

·

40

·

dB

60

·

dB

Av

VI = 50l1VRMS

VO(AF)

VI=10mVRMS

·

1.2

·

VRMS

THO

VI= 10mVRMS

·

3

·

%

c,

DETECTOR
TRANSFER
CHARACTERISTICS

COMPONENT VALUES

1

50l'F

f

L,

C,

R,

Q

C2

C3

UPPER
PEAK

LOWER
PEAK

MHz

I1H

pF

kll

.

pF

I1F

MHz

MHz

4.5

14

120

20

30

3

0.003

4.58

4.42

5.5

8

100

20

30

3

0.003

5.63

5.37

10.7

2

120

3.9

20

4.7

0.Q1

10.9

10.5

ACVTVM

2110

NOTE: Input to the quadrature coil can be from either terminal 9 or
terminal 10. Terminal 9 Is normally used because it lessens the
possibility of overloads during tuning. The use of terminal 10
increases the limiting sensitivity significantly and has been used
successfully in these tests.

~

o

..JU)

ce~
z_
ce;:)
..JO
cea::
00
w
Q.
U)

8·15

CA2111A
Schematic Diagram

Typical Performance Curves
60
TA = 25°C

V+=12V
100% FM, 30% AM

-

50 fO .. 4.5MHz

J

'"\.

'"
/

~

~

I

I I II

I

60

I

REF. SIGNAL INPUT (TERM. 10)

"-

"' --

...

10-""'"

---...

50

~~

TA,,25"C
V+ .. 12V
100% FM, 30% AM
fO.5~MHz

~

REF. SIGNAL INPUT (TERM. 9)

~

20

10

REF. SIGNAL INPUT (TERM.

Po..
~ 1\0..

"

. /~

,/

.........

!!!L

"...

/'

./

-"

REF. SIGNAL INPUT (TERM. 9)

;/

~

0.1

"-

J

-

20

"

10

10

0.1

INPUT SIGNAL VOLTAGE (VI) (mVRMS)

1

10

INPUT VOLTAGE (VI) (mVRUS)

FIGURE 3. AM REJECTION vslNPUT VOLTAGE (AT 5.5MHz)

FIGURE 2. AM REJECTION vs INPUT VOLTAGE (AT 4.5MHz)

8-16

CA2111A
Typical Performance Curves

(Continued)

50

1.0
SUPPLY VOLTAGE

40

j

iO
:!:!.

z

12V
BV

/I

30

0

/".....

...... 1'-00

-~ ~
~

Z

;::
0

..,

w
w
a:: 20
::;

-

..

!:i

O.B

~~

0.7

iS~
~ ;U

0.5

~

0':
0-0.6

~

r.;

~ ~

0.4

$!

0.3

~

/

TA = 25°C
100% FM, 30% AM
fa =5.5MHz

/

0.2

C

)~

0.1

IJ

o

0
10

100

0.1

10

INPUT VOLTAGE (Vi) (mVRMS)

INPUT VOLTAGE (Vi) (mVRMS)

FIGURE 4. AM REJECTION vs INPUT VOLTAGE (AT 10.7MHz)

1.3
1.2

!:i
~~

1.1

TA = 25°C, V+ = 12V
10= 5.5MHz
'" =±50kHz

0.9

~

<:.

0.&

t;~
~ $!

0.7

C

0.5

iSo

fil ~

-

1

o II:
o ~

I

I

II

I

I

~

I

FIGURE 5. DETECTED AUDIO OUTPUT vs INPUT VOLTAGE
(4.5MHz)

II

INPUT CARRIER = lmV
TA = 25°C
fa = 10.7MHz
)~
" 1=±75kHz

If
I I I I"
REF. SIGNAL INPUT (TERM. 9)

I "~

"""" &V

/
IJ

I
1/

0.4

SUPPLY VOLTAGE (V+) = 12V

)

J

0.6

. REF. SIGNAL INPUT (TERM. 9)

J

CCI

..:

10

TA = 25°C, V+ = 12V
10 =4.5MHz
'" =±25kHz

0.9

~

10

/I

0.3

0.1

10

0.01

0.1

10

100

INPUT SIGNAL VOLTAGE (Vi) (mVRMS)

INPUT VOLTAGE (VI) (mVRMS)

FIGURE 6. DETECTED AUDIO OUTPUT v.,NPUT VOLTAGE
(AT5.5MHz)

C!J

o

FIGURE 7. DETECTED AUDIO OUTPUT VOLTAGE vs INPUT
VOLTAGE (AT 10.7MHz)

.J

«en

z!=
«:;)

.JO

«0::
00
w

3.&

BO

~

.;;-

iii

CI

~
$!

3.7

--

Q 60

SUPPLY VOLTAGE (V+) = 12V

Ie
a::
w

~

til

r-

is 40

P"

z

~

u.

..:

....
..: 20
z
CI

iii
·25

en

iO
:!:!.

0

3.6
-50

0..

MODULATION FREQUENCY = 1kHz
TA = 25°C
" f=±25kHz

o

25

50

75

100

~

BV

~

~ P'"

o ".
0.01

0.1

10

INPUT VOLTAGE (VI) (mVRMS)

TEMPERATURE (oC)

FIGURE 8. AFC VOLTAGE VB AMBIENT TEMPERATURE

FIGURE 9. SIGNAL-TO-NOISE RATIO vs INPUT VOLTAGE

8-17

(Il

\KJ

CA3012

HARRIS
SEMICONDUCTOR

FM IF Wideband Amplifier

November 1996

Features

Description

• Exceptionally High AmplHler Gain
• Power Gain at 4.5MHz •••••••.••••••••••••• 75dB

The CA3012 is an FM IF wideband amplifier with 3 limiter
gain stages In a bipolar monolithic technology. The pin 1
input is an open base and has a separate feedback bias.
The feedback bias pin, DC FB BYPASS, is externally
bypassed and provides the means for a tuned coil input to
the IF IN pin. The output is a high impedance open collector
which may be matched to a tuned transformer, driving an FM
detector. Internal regulation circuits provide DC bias to the
gain stages and DC feedback circuit.

• Excellent Input Limiting Characteristics
• Limiting Voltage (Knee) at 10.7MHz ...• 600I!V (Typ)
• Wide Frequency Capability:
• Bandwidth.................... 100kHz to 20MHz

Applications
• FM IF Amplifiers

The CA3012 is intended for FM limiting applications requiring
high gain.

• FM Communication Receivers

Ordering Information

• TV IF Amplifiers
PART NUMBER

-55 to 125

CA3012

Pinout

TEMP.
RANGEfC)

PKG.
NO.

PACKAGE

no.c

10 Ld Metal Can

Schematic Diagram
CA3012
(METAL CAN)

TOP VIEW

vee

.---+_5
DCFB
BYPASS

OUTPUT

t Internal connection, do not use.
2o-------~------------~~--__t
3

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Haridllng Procedures.
Copyright © Harris Corporation 1996

8-18

4

File Number

128.1

CA3012
Absolute Maximum Ratings

Thermal Information

TA = 25°C

Thermal Resistance (Typical. Note 1)
9JA (oCIW) 9JC (oCIW)
Metal Can Package. . . . . . . . . . . . . . .
175
100
Maximum Junction Temperature ..•.................... 175°C
Maximum Storage Temperature Range ......... -65°C to 150°C
Maximum lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C

Maximum Supply Voltage Vcc. Pin 10 ......•.•....••..... 10V
Maximum Output Voltage. Pin 5 ......................... 13V
Maximum Input Signal Voltage between Pin 1 and Pin 2 ..... ±3VV

Operating Conditions
Temperature Range .•..........•....•.....• -55°C to 125°C
Supply Voltage Range (Typical) .•................. 5.5V to 10V

CAUTION: Stresses above those listed In "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only raUng and operaUon
01 the device at these or any other conditions above those Indicated In the operaUonal sections of this speclflcaUon /s not Implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications
TEST CONDITIONS

PARAMETER
Total Device Dissipation (Note 2)

SYMBOL

SETUP AND
PROCEDURE
(FIGURE)

FREQUENCY
f(MHz)

DC SUPPLY
VOLTAGE
Vee (V)

TEMP
(DC)

MIN

TYP

MAX

P,-

1

-

6

-55

66

80

135

mW

25

66

90

121

mW

Voltage Gain (Note 3)

A

1

3

3

1

1

3

3

7.5

10

6

7.5

10

UNITS

125

65

70

121

mW

-55

97

130

190

mW

25

97

120

167

mW

125

95

100

167

mW

-55

150

210

275

mW

25

150

190

255

mW

125

150

160

255

mW

-55

50

55

25

60

66

125

50

61

-55

55

59

25

65

70

125

55

65

-55

55

61

25

65

71

125

55

66

4.5

7.5

25

60

67

10.7

7.5

25

55

61

-

-

dB
dB
dB
dB
dB

CJ

dB

..J(f)

dB
dB
dB

-

dB

Parallel Input Resistance

RIN

6

4.5

7.5

25

CIN

6

4.5

7.5

25

-

7

Parallel Output Resistance

ROUT

8

4.5

7.5

25

-

31.5

Parallel Output Capacitance

COUT

8

4.5

7.5

25

NF

10

4.5

7.5

25

VI(LIW

3

4.5

7.5

25

-

3

kQ
pF

Output Impedance Components

Noise Figure
Input limiting Voltage (Knee)

-

kQ

8.7

-

300

400

I1 V

4.2

NOTES:
2. The total current drain may be determined by dividing PT by Vcc.
3. Recommended minimum DC supply voltage (Vcc) is 5.5V. Nominal load currentflowing into terminalS is 1.5mA at 7.5V.

8-19

c(~
Z_

c(:;)
...1(.)
c(a:

()()
w
0.

(f)

dB

Input Impedance Components

Parallel Input Capacitance

o

pF
dB

CA3012
Typical Performance Curves and Test Setups
250

..

i'

.s

200

~

150

~

+Vcc

I

~ 100

50n

~
Q
....

~

- r-- r-- -";;r-Vcc=10

7.5

-

50

o

-

·75

·50

r-:...
·25

0

25

50

75

100

125

150

TEMPERATURE <"C)
FIGURE 1. DISSIPATION TEST SETUP

FIGURE 2. DISSIPATION

VB

TEMPERATURE

Procedures
A. Voltage Gain
1.Set input frequency at desired value, V,

=100/lVRMS

2. Record Va

3. Calculate Voltage Gain A from A =20 10910 VoN,
4. Repeat steps 1, 2 and 3 for each frequency and/or for
temperature desired

B. Input Limiting Voltage (Knee)
1.Repeat steps A1 and A2, using V,

=100mV

2. Decrease V, to the level at which Va is 3dB below its
value for V, =100mV

3. Record V, as Input Limiting Voltage (Knee)

60

75

FIGURE 3. VOLTAGE GAIN TEST SETUP

,

500

~

/

vdLTAGE'GAIN '

') ~

.......

-

:>K

....

·25

0

25

50

75

100

~

~

~
A.
100 !:
125

70

I

~

w

~
!j

~

~

66

INPUT LlMmNG VOLTAGE

V

60

0
150

0.1

500

1

~
CJ

~

~

400 CJ

E

j\

64

600

w

J

i\J
,

62

TEMPERATURE (DC)

I

f

VOLTAGE GAIN

iii'
CJ

700

TA = 25DC, vcc = 7.5, Rs = 500, RL = lItO

!!. 68

!j

~
300 CJ
z
200

55

-SO

400

~
w

E

INPUT LlMmNG

"
50
·75

72

600

vcc = 7.5, f = 11 MHz, is = 5010, RL = lItO

300

~

I::l
A.

~

200 !:

~

10

100

FREQUENCY (MHz)

FIGURE 4. VOLTAGE GAIN AND INPUT UMITING VOLTAGE
vs TEMPERATURE

FIGURE 5. VOLTAGE GAIN AND INPUT LIMITING VOLTAGE VB
FREQUENCY

8·20

CA3012
Typical Performance Curves and Test Setups

(Continued)
10
TA = 25°C, VCC = 7.5

+VCC

" '"
.......

R-XMETER

4

o

--::N

---

RIN

5

~
2
15

10

FREQUENCY (MHz)

FIGURE 7. INPUT IMPEDANCE vs FREQUENCY

FIGURE 6. INPUT IMPEDANCE TEST SETUP

6
TA = 25°C, VCC

~

= 7.5

W

o

\

Z

~
o

5

8:
~

\

5
0..

5
o

COUT
............. -.;.;;,;,

4

~

~

~

3

".

"

~OUT

II:

8:

, -

o

-----

5

10

FREQUENCY (MHz)

c:J

9


"wu::

4.5MHz
NOISE SOURCE

!!!

8.5

o

z

L1 = 8211H, CENTER TAPPED

..".

y

,,- .--

~

~

8.0

L2=2.36I1H
C1, C2 = ARCO TYPE 423 PADDER, DR EQUIVALENT

6

7

8

9

DC SUPPLY VOLTS (VCC)

FIGURE 11. NOISE FIGURE vs DC SUPPLY VOLTAGE

FIGURE 10.

8-21

10

CA3012

Typical Application

---------------+VCC

FM
10.88MHz ·108MHz
TUNER

DETECTOR

10.7MHz
SELECTIVITY

AF
AMPLIFIER
_ _ _ _ SPEAKER

FIGURE 12. BLOCK DIAGRAM OF TYPICAL FM RECEIVER USING THE CA3012 INTEGRATED CIRCUIT WIDEBAND AMPLIFIER

8·22

CA3,088E
AM Receiver Subsystem and
General-Purpose Amplifier Array·

November 1996

Features

Description

• Excellent Overload Characteristics

The CA3088E, a monolithic integrated circuit, is an AM subsystem that provides the converter, IF amplifier, detector,
and audio preamplifier stages for an AM receiver.

• AGC for IF Amplifier
• Buffered Output Signal for Tuning Meter

The CA3088E also provides internal AGC for the first IF
amplifier stage, delayed AGC for an optional external RF
amplifier, a buffer stage to drive a tuning meter, and terminals facilitating the optional use of a tone control.

• Internal Zener Diode Provides Voltage Regulation
• Two IF Amplifier Stages
• Low-Noise Converter and First IF Amplifier
• Low Harmonic Distortion (THO)
• Delayed AGC for RF Amplifier
• Terminals for Optional Inclusion of Tone Control
• Operates from Wide Range of Power Supplies:
V+ 6V to 16V

=

• Optional AC andlor DC Feedback on Wide-Band
Amplifier
• Array of Amplifiers for General-Purpose Applications
• Suitable for Use With Optional External RF Stage,
Either MOS or Bipolar
• Related at:
• Refer to AN6022 for Application Note Information

Ordering Information
PART NUMBER
CA30BBE

TEMP.
RANGE ("C)
-4010B5

PACKAGE
16Ld PDIP

Figure 2 is a functional diagram of the CA3088E. The signal
from the low-noise converter is applied to the first IF amplifier and is then coupled to the second IF amplifier. This IF
signal is then detected and externally filtered. The resultant
audio signal is applied to an audio preamplifier. Optionally, a
tone control circuit may be connected at the junction of the
detector circuit and the audio preamplifier. The gain of the
first IF amplifier stage is controlled by an internal AGC circuit. The CA3088E supplies a delayed AGC signal outpU1 for
use with an external RF amplifier. A buffered output Signal is
also available for driving a tuning meter. A DC voltage, internally regulated by a Zener diode, supplies the second IF
amplifier, the AGC and tuning meter circuits and may also be
used with any other stage.
The CA3088E features four independent transistor amplifiers, each incorporating internal biasing for temperature
traCking. These amplifiers are particularly useful in generalpurpose amplifier, oscillator, and detector applications In a
wide variety of equipment designs.

PKG.
NO.

o
"-----l-{roJ~

~-

-lH

FILTER AND AUDIO
(OPTIONAL TONE
CONTROL MAY BE
SHUNTED FROM
TERMINAL 9
TOGROUNDj

TORFSTAGE
OF ANTENNA

CJ

o
..J

en
«IZ_
«;:)

CA3088E

..J(')

«II:

UU
w

a.

en

~•
-=- 3D-l4-<
•

0.01.I.

TO~~

AMPUFIER

L - -.......-+-~E--

25
~-----oV+

NOTE: Resistance values are in n. Capacitance values in IlF. except as noted.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE CA3088E

8-25

= 9V

CA3088E

CONVERTER
INPUT BYPASS

V+

200

RZ

Re

2K

4K

t-------~--------~9 g~~~R
L----4--------~------__l7 ~~~g:fd~
V+

R,
S.aK

AUDIO
OUTPUT

ALL RESISTANCE
VALUES ARE IN
OHMS

AUDio INPUT
FROM DETECTOR FILTER

FIGURE 3. SCHEMATIC DIAGRAM OF THE CA3088E

8-26

CA3089

HARRIS
SEMICONDUCTOR

FM IF System

November 1996

Features

Description

• For FM IF Amplifier Applications in High-Fidelity,
Automotive, and Communications Receivers

Harris CA3089 is a monolithic integrated circuit that provides
all the functions of a comprehensive FM-IF system. The
block diagram shows the CA3089 features, which include a
three-stage FM-IF amplifier/limiter configuration with level
detectors for each stage, a doubly-balanced quadrature FM
detector and an audio amplifier that features the optional use
of a muting (squelch) circuit.

• Includes: IF Amplifier, Quadrature Detector, AF
Preamplifier, and Specific Circuits for AGC, AFC, Muting
(Squelch), and Tuning Meter
• Exceptional Limiting Sensitivity
at -3dS Point .......•...•.•..••.••....• 12/!V (Typ)
• Low Distortion:
(with Double-Tuned Coil) .....•...•...... 0.1% (Typ)
• Single-Coil Tuning Capability
• High Recovered Audio ...•••.•.••.•... 400mV (Typ)
• Provides Specific Signal for Control of Interchannel
Muting (Squelch)
• Provides Specific Signal for Direct Drive of a Tuning
Meter

The advanced circuit design of the IF system includes desirable deluxe features such as delayed AGC for the RF tuner,
and AFC drive circuit, and an output signal to drive a tuning
meter andlor provide stereo switching logic. In addition, internal power supply regulators maintain a nearly constant current drain over the voltage supply range of +8.SV to + 16V.
The CA3089 is ideal for high-fidelity operation. Distortion in a
CA3089 FM-IF System is primarily a function of the phase
linearity characteristic of the outboard detector coil.

• Provides Delayed AGC Voltage for RF Amplifier
• Provides a Specific Circuit for Flexible AFC
• Internal Supply-Voltage Regulators

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

PKG.
. NO.

PACKAGE

CA3089E

-401085

16 Ld PDIP

E16.3

CA3089Ml
(3089M)

-401085

20 LdSOIC

M20.3

"...o

c:(f!?
Z_
c:(::J

Pinout
CA3089
(PDIP)
TOP VIEW

... 0

CA3089
(SOIC)
TOP VIEW

c:(a::

00
w

0f/)

GND

INPUT BYPASS

2

DC FB BYPASS

3

FRAMEGND 4
MUTE CONTROL

15 DELAYED AGC
14 SUBSTRATE(GND)

1

13 TUNING METER OUT

16 TUNING METER OUT

SUBSTRATE (GND)

15 MUTE LOGIC

5

AUDIOOUT 6
AFCOUT 7

1 QUADRATURE INPUT

9 QUADRATURE INPUT

11 NC

CAUTION: These devices are sensillve to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporstion 1996

8-27

File Number

561.3

CA3089
Absolute Maximum Ratings

Thermal Information

Supply Voltage
Between V+ and Frame GND ................•........ 16V
Between V+ and Substrate GND ...................... 16V
DC Current (Out of Delayed AGC) .............•......... 2mA

Thermal Resistance (Typical, Note 1)
9JA (oCIW)
PDIP Package .............................
90
SOIC Package .............................
80
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range . . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range ......................... -40°C to 85°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only mting and opemtion
of the device at these or any other conditions above those indicated In the opemtional sections of this specification Is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

V+ = 12V (See Figures 3 and 4)

(NOTE 3)
PARAMETER

TEMP.
(oC)

TEST CONDITIONS

TYP

MIN

MAX

UNITS

DC CHARACTERISTICS
25

16

23

30

mA

Terminal 1 (IF Input)

No signal input, Non muted

25

1.2

1.9

2.4

V

Terminal 2 (AC Return to Input)

25

1.2

1.9

2.4

V

Terminal 3 (DC Bias to Input)

25

1.2

1.9

2.4

V

Terminal 6 (Audio Output)

25

5.0

5.6

6.0

V

Terminal 10 (DC Reference)

25

5.0

5.6

6.0

V

Quiescent Circuit Current
DC Voltages

DYNAMIC CHARACTERISTICS
fO = 10.7MHz,
fMOD = 400Hz,
VIN= O.1V,
AM Mod. =30% Deviation = ±75kHz

12

25

AM Rejection (Terminal 6), AMR

25

45

55

-

IlV
dB

Recovered AF Voltage (Terminal 6) Vo (AF)

VIN= 0.1V

25

300

400

500

mV

0.5

1.0

%

Input Limiting Voltage (-3dB point), V1 (lim)

Total Harmonic
Distortion, THO
(Note 2)

25

Single Tuned (Terminal 6)

25

Double Tuned (Terminal 6)

25

-

0.1

-

%

Signal Plus Noise to Noise Ratio (Terminal 6)

25

60

67

-

dB

NOTES:
2. THO characteristics are essentially a function of the phase characteristics of the network connected between Terminals 8, 9, and 10.
3. Terminal numbers refer to 16 Lead PDIP.

Application Information

...

v+ = 12V, TA 25°C
5k.Q

~
...

...
00(

~
I!!
Ie

i

!z
II!Ie

a

125
100
75
50
25
0
-25

~
~

/

/

§ m-10
::!!UI

iii'1I!

./

:Eo::!!

~

./
./

~

II"

Ie

-50
0
50
CHANGE IN FREQUENCY (kHz)

i

~i

II!

./
-100

V+ = 12V, TA = 25°C
0

ell)

V

-50

-75
-100
-125

~

8w

100

(LEFT COORDINATE)

I

8-28

I

TUNER AGC DC VOLTAGE AT'TERM. 15 (RIGHT COORDINATE)
-30 I - - - VOLTAGE AT TERMINAL 13
METER CIRCUIT (33k.Q
(RIGHT COORDINATE)
-20

-40

I;(
-50

J. ~

-60
1

FlGuAE 1. AFC CHARACTERISTICS (CURRENT AT TERMINAL
7) vs CHANGE IN FREQUENCY. (SEE TEST CIRCUIT
FlGURE3.)

f

~RECfNERED AUDIO FROM FULL OUTPUT

10

I)(

1'0,/
\
./'"
\

100
1K
INPUT SIGNAL (IlV)

10K

6

5

4£
3g
2

1
lOOK

FIGURE 2. MUTING ACTION, TUNER AGC, AND TUNING
METER OUTPUT vs INPUT SIGNAL VOLTAGE. (SEE
TEST CIRCUIT FIGURE 3.)

CA3089
Test Circuits

SIGNAL
INPUT COJ-tl-t...-{
VOLTAGE

AUDIO

}JtIY"Y1- OUT

NOTES:
4. All resistance values are in ohms.

NOTES:
7. All resistance values are in ohms.

5. L tunes with 1OOpF (C) at 10.7MHz.

6.

SIGNAL
INPUT Cg}-IH"-{
VOLTAGE

00 (unloaded) :; 75 (G.I. Automatic Mfg. Div. EX22741 or equivalent).

B. T PRI. - Qo (unloaded):; 75 (tunes with 100pF (C,) 20i 0134e on
7'32" dia. form).
9. SEC. - 00 (unloaded) :; 75 (tunes with 100pF (C2) 20i 01 34e on
7'32" dia form).
10. kQ (percent 01 critical coupling) :; 70%.
(Adjusted for coil voltage Ve) : 150mV.
Above values permit proper operation 01 mute (squelch) circuit "E"
type slugs, spacing 4mm.
FIGURE 4. TEST CIRCUIT FOR CA3089E USING A DOUBLETUNED DETECTOR COIL

FIGURE 3. TEST CIRCUIT FOR CA3089E USING A SINGLETUNED DETECTOR COIL

-

Typical Applications

p----"I

C)

o
.....
-I~

IF
INPUT

-

l

~~
l

:::t-

Q8A Q10Ql;1. R

~::Yl

RI3~"""

'--

~
R2
30K

-

Qll;;:tR13
2.7K

;;::tC4
0.2

R3
360

~

~14A

Qla)

~~
Ql
R16
2.7K
R17
360

€:a

0.2

R12
2.7K

R14
360

Ql

Q14

Rl~
2K

I/:

2K

2

INPUT
BYPASSING

v+

~

~

~

..c-

~
~

-

R!1i'
2K

~Q2
R20
2K

R28
750

'-R21
480
r--'
R22
1.5K

R15
2.7K

SEE
NEXT
PAGE

'7

*

::
3

Rl
30K

V+

R50
500

RSI
5K
C5
2

Q5

QS

---<

~.

.....

3

QSP*"

lltr~
R52

400

V

r-C7

'"""'

3

Qe

.....
c;"'

t:t-

3
Q6,*

Q6~i--J
Q6

:;:t-l

QS
Q7

R53
600

,

,>-

-t-

t:t--' i--J

W
R56
600

®~CFOR

V+

...J

ar~·""'Qn

:SJan ~Q94

r

-- ,

NOTE: Pin numbers refer to 16 lead PDIP.
LEVEL DETECTOR AND METER CIRCUIT

8-31

(!J

o

RSO
300

R59
150

~,

4K

13

RFAMPL.

'--

r.u~~:

m

cC.Z_
cC:I
...JO
cCO:

00

W
Il.

m

CA3089
Schematic Diagram

(Continued)

RE~~
BIAS
1

9 QUADRATURE
INPUT

8

~UT

~V+

DETECTOR
R33
500

-

AUDIO
AMPLIFIER

:R32
500

R37
166

-- ~24~Q3~~
'7

~

R34
10K

R25
10K

R31
390

4~

~

......~

:---

Q34.....

-

~~

~D3

~

~

~
500

:--

~
R63
300

~£

V

Q.,

51

A

~

R3S

...
...,,.!*--

.....

Q.,

Q39....

R42
166

Q53 ...

48

I

~Q3B

R44
500

R3B
500

RS4

aOci .....

'!

b48~~~9
'-

41

~~~

~

50

-7 ~

AUDIO

Qs:

~II

r Q63

~~~

TV+

~

V

R41
500

RSS

~~
10K

zl'~

Q
30
Q29VD4

~A

1~~ C~:
~

RS
4K

~,.Dl

lsod

lv+

Q2B

QS

~~

31

4811:

R64
5K

"'- ~,(Z2

RSS
13K

I~

R4
480

-:

f-l:;

~Q47

t:Q42~

~ 'DS

,.

4.2K

BIAS
SUPPLY

~4:~
1
10

u

R62

J,5OO

.,
~7

500

,~

RS7
10K

5
MUTE
CONTROL.

SDK

500
Q

....
AFC
OUTPUT
7

ja.

A48

Q55

:'6

A4a

R39
500

R~!

~

V+

r QS7
~8

,,.

500

AFC AMPLIFIER

~FRAME

On

~

SUBSTRATE

=

a73

NOTES:

RSB
SO

19. A" resistance values are in ohms.
20. All capacitance values are In pF.

12=C

21. Pin numbers refer to 16 lead PDIP.

MUTE DRIVE

8·32

CA3126

HARRIS
SEMICONDUCTOR

TV Chroma Processor

November 1996

Features

Description

• Phase Locked Subcarrier Regeneration Utilizes
Sample-and-Hold Techniques

The Harris CA3126 is a monolithic silicon integrated circuit
designed for TV chroma processing and is ideally suited for
NTSC color graphic applications that require subcarrier
regeneration of the color burst signal.

• Automatic Chrominance Control (ACC)lKilier Detector
Employs Sample-and-Hold Techniques

Ordering Information

• Supplementary ACC with an Overload Detector to
Prevent Oversaturation of this Picture Tube
• Sinusoidal Subcarrier Output

PART NUMBER

• Keyed Chroma Output
• Emitter Follower Buffered Outputs for Low Output
Impedance

TEMP.
RANGE (oC)

PKG.
NO.

PACKAGE

CA3126E

-401085

16 Ld PDIP

E16.3

CA3126M1

-401085

20 LdSOIC

M20.3

• Linear DC Saturation Control

Applications
• Tv/CATV Receiver Circuits
• NTSC ColOr Decoder/Processor
• Computer Graphics Subcarrier Regenerator
• Timing Reference for Frame Grabbers
• DSP Clock Timing Reference Source

Pinouts
CA3126
(PDIP)
TOP VIEW

CHROMA IN

1

CA3126
(SOIC)
TOP VIEW

CHROMA GAIN CONT.

AFPC FILTER +

2

CHROMA OUT

AFPC FILTER -

3

ZENER REF

4

OVERLOAD DET.

GROUND

5

V+

CHROMA IN

1

CHROMA GAIN CONT.

..10

2

CHROMA OUT

00
W

4

ZENER REF

NC

NC

RFBYPASS

D..

OVERLOAD DET.

GROUND

6

7

ACe-

VCOOUT

7

CARRIER OUT

8

HORIZ. KEY IN

V+
ACC+
ACCHORIZ. KEY IN

NC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

8-33

CARRIER OUT

File Number

«D:

I/)

ACC+
VCOIN

o
~!::
«::::;)

..II/)

AFPC FILTER +

AFPC FILTER RFBYPASS

Cl

860.4

CA3126
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage (1/+ to GND) (Note 1)................. 13.2V
OCCurrent:
Into V+ Pin ...................................... 38rnA
Into Zener Reference Pin ........................... 20rnA
DC Voltage (Horizontal Key In)
Negative Rating ................................... ·5V
Positive Rating ..................................... 3V

Thermal Resistance (Typical. Note 1)

9JA (oCIW)

100
PDIP Package.............................
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
Maximum Junction Temperature (Plastic Packages) ....... 150°C
Maximum Storage Temperature Range . . . . . . . .. ·65oC to 150°C
Maximum Lead Temperature (Soldering 10s) ............. 300°C
(SOIC • Lead Tips Only)

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .. .400 C to 85°C
CAUTION: Stresses above those listed In "Absolute Maximum Ratings" may cause permanant damage to the davies. This is a stress only tating and opetatlon
of the davies at thSSfl or any other conditions above those Indicated In the operational sections of this specification Is not Implied.

NOTES:
1. This rating does not apply when using the Intarnal zener reference in conjunction with an external pass transistor.
2. OJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

PARAMETER

=

TA 25°C. Chroma Gain Control at maximum position for all tests except as noted. Electrical
specifications referenced to test circuit.

TERMINAL,
MEASUREMENT
AND SYMBOL

SWITCHPOS.
S1

~

VCHROMA INPUT TP1

MIN

TYP

MAX

UNITS

DC ELECTRICAL SPECIFICATIONS
Voltage Regulator

V12

2

2

0

10.1

11.2

12.1

V

Supply Current

112

2

2

0

16

25

38

rnA

SWITCHING ELECTRICAL SPECIFICATIONS (Note 3)
Va

(Note 6)

2

0.5Vp.p

±250

·

.

Hz

Oscillator Output

Va

2

2

0

0.6

1.0

.

Vp.p

100% Chroma Output

V15

1

2

0.5Vp.p

1.4

2.7

Overload Detector

V15

1

1

0.5Vp.p

0.4

·

0.7

Vp.p

·

20

mVp_p

100

140
105

%of
100%
Reading

60

mVp.p

Pull·ln Range (Nota 4)

Minimum Chroma Output
(Note 5)

V15

1

2

0.5Vp.p

.

200% Chroma Output

V15

1

2

1Vp_p

70

20% Chroma Output

V15

1

·2

0.1Vp_p

40

VTP1

1

2

Vary

5

Kill Level

·

NOTES:
3. Except for pull-in range testing. tune oscillator trimmer capacitor for free running frequency of 3.579545MHz ±10Hz.
4. Set Switch 1 to Position 2. detune oscillator ±250Hz. set Switch 1 to Position 1. and check for oscillator pull-in.
5. Set Chroma Gain Control to minimum position (CCW).

8·34

Vp.p

CA3126

Test Circuit
....-_......_ _..... _ +24V

o
1Olen

2N2102
O.05p.F

~

3.91en

I

OSCILLOSCOPE

cw
471en_ _...,
1Olen s.---ItNv

I

21en

CCW
CHROMA
GAIN

CON"mOL

I

I----I~.......

+--_>---..,

COUNTER
SUB- .~_ _ _ _.....
CARRIER
OUTPUT

TPl

1__---63.5118 - - -... 1

Pin numbers refer to the PDIP package.

(A)

3.579545MHz

1__ 4118

(A) Chroma input signal
(8) Key pulse input signal

1--£"1-===

t

t

VCHROMA

O.46VCHROMA

CJ

o

.J

tn

CS: ....
Z_

(B)

CS::::::I

.JO

cs:a:
00
w
11-

tn

8-35

CA3126
Block Diagram
TV CHROMA PROCESSOR

SUPPLY
VOLTAGE
+24V

CHROMA
OUTPUT

TO
TERM. 12

cw

~~-Y~~~~~--~---+----+---~
~----~

CCW

..rt.OV
2kn

CA3126

NOTES:
6. Optional design features.
7. Pinout numbers refer to the PDIP package.

8-36

5J18WIDTH
HORIZONTAL
KEY INPUT

CA3126
Schematic Diagram
4

RF BYPASS

--------------------------------.-.----------------•

AFPC DETECTOR

A

SINGLE SAMPLE
AND HOLD

~:r--------------------------B

r--r--~r---------_,~t:~--t!.--~::::::::+=:::::::::::::g

FIRST CHROMA
AMPLIFIER

R'3
4K

•
•
·Q53

•

:. l

~

~

~,

300

300

UK.

RS
700

•
•

.----+-+.,.

r-R2
700

:

.....Jt;Vv-....i::.. Q

R20

li....:_:_

R,S

r f l 1 JVo,S"K,......_____ E
2

.

• 700

• R'6
• 12K
•• R'9
•• 12K
•
••

C,.= :
10pF

Q'3

L-__

+-~+-

________ F

L----4----~~~~~----~~--+_~--+_~·----~----~~~----------G

rftti===~;;====~r----lr--·~-~-~-f-~~~-~-~-~-f-~-:-::-:-::-:-==-:·~
SIGNAL SAMPLE

r1--,~~~~~--~--ttf11H~::::::~--~=t=t=t~::t=r!-·~--;A~N~D~H~O~L~D==::== ~
R~

RM
4K

2.5K

R57

2K

~~9r-_______

L
M

N

0
P

CHROMA
OUTPUT

J

11~~.~--+-----~--------~

CHROMA
GAIN

r ~. 5K
fo ..
•• '::
:~ n
••• ~
lK
•• R40 KILLER
AMP.
•• OJ ,
•
.
11.44

-- -R79

300

OVERLOAD
DETECTOR

- ACC·
AMP.

i~

113)-~~1'f+-i::;'
Q22

·

11. _ _ -

~;:)

-- ---.•

••
•

R49

700

5K

.~
;~

~

220

ZENER
REFERENCE

·• r-.•
•

RSI. n.
2K

••

R50
5K

~ ••
5K

.-----

•

••
•
.--_ • .1

R~~

~,

330

~II)

z!:::

...JO

------~

CONTROL

CJ

0

...J

0,

r*-:
~I"~
QI"~

"
••• RS2
• lK.
•• ••

- - - - - . : . . ___ 1

OVERLOAD DETECTOR

• • •

- - - - - - - - - - - - - - - - - - - - - - - - - _. - GROUND" - • - - ~ ~NER - - - - 5

(SUBSTRATE)

NOTE: Pin numbers refer to the PDIP Package. Resistance values are in ohms.

8-37

 REFERENCE

.-----

~a:

00
w
0..

II)

CA3126

Schematic Diagram

(Continued)

AFPC FILTER

CARRIER

XTALFILTER

¢
0'
A------.. ---------- ---.. _._--_ .. -.--------------_.- ..
PH~'EA:~~ER
••
••
•••
•
- ---_ ••
'$

lOt

@'

OU;UT

lOt

:

:

BIAS SAMPLE
AND HOLD

LIMITER AMPLIFIER

...

R38

UK
R23
8.2K

Rae

500

: ..

•

----~--

, Dz

.... :--.- ...•...... ,

..

I

------!-----_ ..• -----_ ..... _.. _-_ .....
Au

~--

.. --.- _.-

R70

1.8K

UK

KEVER
Q

r-""f"On

~------------~~--------~---~.
An
2.5K

1Ir4
lK

R

~

.- ..... -.. -.. --.--~.--.- ............ -... -.--.-- .. •

9

VOLTAGE REFERENCES

HORIZONTAL
KEYING INPUT

8-38

CA3126
Application Information
Circuit Description (Pin numbers refer to the DIP package.)
The following paragraphs briefly describe the circuit operation
of the CA3126 (shown in the Block Diagram and Schematic
Diagram). A detailed description of the operation of various
portions of the CA3126 is given in AN6247, "Application of the
CA3126 Chroma-Processing IC Using Sample-and-Hold
Techniques".
The chroma input is applied to Terminal 1 through the desired
band-shaping network. A 2,4500 resistor should be placed in
series with Terminal 1 to minimize oscillator pickup in the first
chroma amplifier. This amplifier supplies signals to the second
chroma amplifier and to the ACC and AFPC detectors. The
first chroma amplifier is gain-controlled by the ACC amplifier.
A horizontal keying pulse is applied to Terminal 9. This pulse
must be present to ensure proper operation of the oscillator circuit. The subcarrier burst is sampled during the keying interval
in the AFPC detector. The error voltage, produced at Terminal 2
and proportional to the burst phase, is compared to the quiescent bias voltage at Terminal 3 by the sample-and-hold circuitry.
This "compared' voltage controls the phase- shifting network in
the phase-locked loop. The operation of the AFPC loop is independent of any external adjustments or voltages except for an
initial capacitor adjustment to set the free-running frequency.
The regenerated oscillator signal at Terminal 8 is applied
internally to the AFPC and ACC detectors through +45 and
-45-degree phase-shifter networks to establish the proper
phase relationship for these detectors. The ACC detector,
which also samples the burst during the keying interval, produces a correction voltage proportional to the burst amplitude. The correction voltage is compared to the quiescent
bias level using sample-and-hold circuitry similar to that
used in the AFPC portion of the circuit. The "compared" voltage is applied internally to the ACC amplifier and killer
amplifier. Because the amplifier gains and killer threshold
are determined by the ratios of the internal resistors, these
functions are independent of external voltages or controls.

2. When the overload detector is used, a large resistor
(nominally 47,0000) must be placed in series with Terminal 16 to set the required RC time constant. The same
RC network series serves to set the killer time constant.
3. The setting of the free-running oscillator frequency
requires the presence of the keying pulse. The free-running frequency will be erroneous if Terminal 1 is DC
shorted during the setting operation because of the DC
offset voltage introduced to the AFPC detector.
4. Care must be taken in PC board designs to provide reasonable isolation between the oscillator portion of the circuit
(Terminals 6, 7, and 8) and the chroma input (Terminal 1).
Overload Detector
The overload detector accomplishes two purposes:
1. It prevents oversaturation due to low burst-to-chroma ratios.
2. It prevents overload conditions due to noise.
Both of these conditions are discussed in more detail in
AN6247. The extent to which the overload detector is used
depends upon the individual receiver design goals. If greater
than 0.5Vp_p output is desired, the chroma output at Terminal 15 can be tapped to yield any desired degree of overload
detector action.
Chroma Gain Control
The chroma gain control operates by varying the base bias on
current source transistor Q25. To ensure proper temperature
traCking of the chroma gain control, it is essential that the control be operated from a supply source derived from the reference voltage at Terminal 12. Because the control operates from
a current source, chroma gain is much more predictable and far
less temperature sensitive than controls that steer current by
means of a differential amplifier. The typical chroma gain characteristic for the CA3126 is shown in Figure 1.

TA

iii

:3
~
><
C

The attenuated chroma signal is fed to the second chroma
amplifier, where the burst is removed by keyer action. The
killer amplifier, the chroma gain control, and the overload
detector control the action of the second chroma amplifier,
whose gain is proportional to the dc voltage at Terminal 16.
The overload detector (Terminal 13) receives a sample of
the chroma output (Terminal 15) and detects the peak of the
signal. The detected voltage is stored in an external capacitor connected to Terminal 16. This stored voltage on Terminal 16 affects the gain of the second chroma in the same
manner as the chroma gain control.

100

:!

...0

80

C

60

t-

=25°C, CHROMA INPUT =0.5Vp..p

t0

,

II:
:I:

~ ....
z_

~;:)

~

..JO
~a:

00
w

'/

a..

!/)

~

40

~

C

:!
0

o

..J!/)

I'"

::::l
A::::l

~

20

/

0

o

i/
20

40

60

80

100

120

140

VOLTAGE AT TERMINAL 16 (% OF V12)

General Considerations
The block diagram shown is typical of the type of circuit used
in the practical application of the CA3126. Several items are
critical for proper operation of the circuit.
1. A series resistor of approximately 2,4500 (or high source
impedance) must be used at the chroma input, Terminal
1. This high impedance minimizes pickup of unbalanced
currents, particularly of the subcarrier oscillator signal.

FIGURE 1. CHROMA GAIN CONTROL

Subcarrier Regenerator Oscillator
The oscillator filter consists of a 3.579545MHz crystal, a 6800
resistor, and a 10pF capacitor connected in series across Terminals 6 and 7. A 33pF capacitor, shunt connected from Terminal 7 to ground, rolls off higher order harmonics, thereby
preventing oscillation at the crystal third-harmonic frequency. A

8-39

CA3126
curve of the typical static phase error as a function of the freerunning oscillator frequency is shown in Figure 2. It should be
noted that the slope of the curve determines the DC gain of the
phase-locked loop, i.e., 40Hz per degree.

m
l§ 4
~

2

!5W

0

~
o

-2

t;

-4

Ii

I(

/

IL

~

AMPL~

"

o

-25

./

'" ,
~

25

50

75

TEMPERATURE (DC)

FIGURE 4. AMPLITUDE AND PHASE VARIATIONS OF
. CHROMA OUTPUT VB TEMPERATURE

~

-300

PHASE

....

J

~

1
I

I
II

,

TA=250 C

6

CHROMA INPUT = 0.25Vp..p,
3.58MHz CW SIGNAL

o

-100
100
200
300
OSCILLATOR FREE-RUNNING FREQUENCY
(DEVIATION IN Hz FROM 3.579545MHz)

-200

~o

FIGURE 2. STATIC PHASE ERROR

CHROMA INPUT. OVp..p

Thermal Considerations
The Circuit of the CA3126 is thermally compensated to achieve
the optimal operating characteristics over the normal operating
temperature range of TV receivers. Figures 3 and 4 show the
oscillator and chroma-output amplitudes and phases as a function of temperature (Terminals 8 and 15),respectively.
Both the oscillator and chroma-output amplitudes and
phases are measured relative to the chroma-input phase.
The performance of the oscillator free-running frequency as
a function of temperature is shown in Figure 5. All the temperature plots are characteristic of the test circuit with the
indicated component types and values given.

~ 110

CHROMA INPUT = O.25Vp_p, 3.58MHz CW SIGNAL

~

I"-

o

25

50

75

100

FIGURE 5. VARIATION OF OSCILLATOR FREE RUNNING
FREQUENCY VB TEMPERATURE

LL ~
100 r- -JHAS~
1:'5
~
,/
~
~
~
~
IL
I!I 90

-

N

~

~ 80

/

,;{MPLITUDE

~

~

a:

70

u

8

I"-

TEMPERATURE (DC)

iii

3....

-

60
-50

-25

o

25
50
TEMPERATURE (DC)

75

FIGURE 3. AMPLITUDE AND PHASE VARIATIONS OF
OSCILLATOR OUTPUT vs TEMPERATURE

8-40

125

CA3126

82pF

"'"'" .

TYP.O.5Vp.p 1.

68pF

~I-.....n-......-

........--;'

56
pF
' - _...._

f:::

.'~ f~

=

~

•
FSC

-- -----Vee

........J 2.4kn

CA3126

=

COMPOSITE
VIDEO/CHROMA INPUT

BURST KEY PULSE

. NOTE: For Subearrler Regenerator, the second chroma
amp Is not used; Pins 13,14, and 15 are not connected and
pin 16 Is grounded.

41'S (TVP), CENTERED
ON BURST

FIGURE 6. TYPICAL APPLICATION OF THE CA3126 AS A SUBCARRIER REGENERATOR

"o m
...1

F-

--K!l41

3.4V

Q4.,

1

J

~Q33_

--·4V
VIDEO
INPUT

10.7V

.....

Rg
5S0

Q3

R7
3.4K

..Rl
R.6K

Q3S~

R47
15K

Q36

r--t::Q2

~'Ql
R2
390

,.

R3
390

VIDEO
TOAGC

SYNC
SEP.

, .. Q42
R4l
15K

SYNC
TOAGC

REF BIAS TO
AGC(4V)

A43

5K

R48
1.7K

Cl

o

~

CCIZ_
CC::l
-10
CCIl:

--i)~s
R42
15K

~

t

Q43

a..

(/)

RS4
13.5K

RS2
33

r-

SYNC
OUTPUT 3

FIGURE 4. SCHEMATIC OF SYNC SEPARATOR SECTION OF THE CA3154

00
w

I-

R4a
200

2

8-45

-I(/)

RSl
27K

R50
7.9K

,"

R39
1K

1

-=.E="

A44
2.5K

4.5V
-·7V

R46
4.24K .

SOD

SYNC

f-+ TOHOR
AFC

R53
4.17K

5

-

CA3154
VIDEO
FROM VIDEO
BUFFER AMP

REF

BIAS

(4V)

SYNC
FROM
SYNCSEP

DELAY

SET

IF
AGC

L - -.....{111

~~R
AGC

HORIZ
PULSE

IN

5

FIGURE 5. SCHEMATIC OF AGC SECTION OF THE CAA3154
HORIZ

AFCFlLTER

SYNC FROM
SYNCSEP
=O.6mA

--n

FIGURE 6. SCHEMATIC OF AFC-oSCILLATOR SEcnON OF THE CA3154

8-46

CA3154

.

AGC

I
4.7J1F

TUNER
REV

IF

t.::!::.

~
TUNER
FWD

~.3V

2200

~""

1.2kn

DE~

VON

16.5kn
lkn

33pF

+

3300
1.011Fl
0.OO6811F

1

3.Bkn

2.211F
4.5kn

500n

2.7kn
- - - - 4V

VIDEO
INPUT

2.2kn

,-rr:'fs'
-+ """"l ~
~
I

33kn

i.!.J

10kn

L~

Lf

~6!

rln

,1

~

L7~

L6J

4700

lan

620pF

6800

.:f-

3BpF

~O

"

2.4mH

>-2711H

-==

SYNC SEPARATOR
OUTPUT.posmVE
SYNC TIPS

II
32 X HORIZ.
FREQ.
(S03.5kHz)
OSC.OUTPUT

FIGURE 7. TYPICAL APPLICATION OF THE CA3154

8-47

-

470pF: :

220kn
0.OO47J1F

1.2kn

1.2kn

~ O.033I1F

180kn

O l11F
.

I.!.I"

4700

r ~

i

ri'

CA3154

0.1J1F

1.2kn

...

f1~

f1!iJ

15

HORIZ.
P.8. PULSE
(+GOV)
INPUT

".E="

2.7kn

"'-"'"

+12V
POWER
SUPP LY

CA3189
FM IF System

November 1996

Features

Description

• Includes IF Amplifier, Quadrature Detector, AF
Preal!lplifier, and SpecHlc Circuits for AGC, AFC, TUning Meter, Deviation-Nol.se Muting, and ON Channel
Detector

The Harris CA3189E is a monolithic integrated circuit that
provides all the functions of a comprehensive FM-IF system.
The block diagram of the CA3189E includes a three-stage
FM-IF amplifier/limiter configuration with level detectors for
each stage, a doubly-balanced quadrature FM detector and
an audio amplifier that features the optional use of a muting
(squelch) circuit.

• FM IF Amplifier Applications In High-Fidelity,
Automotive, and Communications Receivers
• Exceptional Limiting Sensitivity -12!lV (Typ) at -3d8
Point
• Low Distortion -0.1% (Typ) (with Double-TUned Coil)
• Single-Coil Tuning Capability
• Improved S + NlN Ratio
• Externally Programmable Recovered Audio Level
• Provides Specific Signal for Control of Interchannel
Muting (Squelch)
• Provides Specific Signal for Direct Drive of a TUning
Meter
• On Channel Step for Search Control
• Provides Programmable AGC Voltage for RF Amplifier
• Provides a Specific Circuit for Flexible Audio Output

The advanced circuit deSign of the IF system includes desirable deluxe features such as programmable delayed AGC
for the RF tuner, an AFC drive circuit, and an output signal to
drive a tuning meter and/or provide stereo switching logic. In
addition, internal power-supply regulators maintain a nearly
constant current drain over the voltage supply range of
+8.SV to +16V.
The CA3189E is ideal for high-fidelity operation. Distortion in
a CA3189E FM-IF System is primarily a function of the
phase linearity characteristic of the outboard detector coil.
The CA3189E has all the features of the CA3089E plus additions. See CA3189E features compared to the CA3089E in
Table 1.

Ordering Information

• Internal Supply Voltage Regulators
• Externally Programmable "On" Channel Step Width,
and Deviation at Which Muting Occurs

PART NUMBER
CA3189E

TEMP.
RANGE ("C)
·40 to 85

PKG.
NO.

PACKAGE
16Ld PDIP

E16.3

Pinout
CA3189
(PDIP)
TOP VIEW

DELAYEDAGC
INPUT
BYPASS

CAUTION: These devices are sensitive to eleclrostatlc discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

8-48

File Number

1046.3

CA3189
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage
(Between Terminals 11 and 4) •..•.•••.•.•...•••••.... 16V
(Between Terminals 11 and 14) ...••........•.•..•.... 16V
DC Current (Out ofTerminal15) •••...•.•.•........•.... 2mA

Thermal Resistance (Typical, Note 1)

9JA

fclW)

PDIP Package.............. ...... ..•...•..
90
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range . . . . . . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs). . . . . . . . . . .. 300°C

Operating Conditions
Temperature Range. . . . . . . . . . . . . . . • . . . . . . . .. _40°C to 85°C
CAUTION: Stresses above those listed In "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only sting and operation
of the device at these or any other conditions above those Indicated in the operational sections of this specification Is not implied.

NOTE:
1. llJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

TA = 25°C, V+ = 12V

PARAMETER

SYMBOL

TEST CONDITIONS

CIRCUIT
OR FIG.
NO.

MIN

TYP

MAX

UNITS

1,2

20

31

40

mA

DC SPECIFICATIONS
Quiescent Circuit Current

111

DC Voltages

No Signal Input, Non Muted
No Signal Input, Non Muted

Terminal 1 (IF Input)

Vl

1,2

1.2

1.9

2.4

V

Terminal 2 (AC Return to Input)

V2

1,2

1.2

1.9

2.4

V

Terminal 3 (DC Bias to Input)

V3

1,2

1.2

1.9

2.4

V

Terminal 15 (RF AGC)

V15

1,2

7.5

9.5

11

V

Terminal 10 (DC Reference)

Vl0

1,2

5

5.6

6

V

12

25

I1V

55

-

dB

650

mV

DYNAMIC SPECIFICATIONS
Input Limiting Voltage (-3dB Point)
AM Rejection (Terminal 6)
Recovered AF Voltage (Terminal 6)

VI(lim)
AMR

VIN = O.lV,
AM Mod. =30%

fO = 10.7MHz,
fMOO. = 400Hz,
Deviation ±75kHz

Vo(AF)

1,2
1,2

45

1,2

325

500

o
" ±40kHz

1

0

-

5.6

1

-

%

V
V
V

NOTE:
2. THO characteristics are essentially a function of the phase characteristics of the network connected between Terminals 8, 9, and 10.

8-49

<:::I
...JO
 70 dB

Yes

No

Meter Drive Voltage Depressed at Very Low Signal Levels

Yes

No

On-Channel Step Control Voltage

Yes

No

Test Circuits

NOTES:
6. All reSistance values are in ohms.
7. T: PRI. - 00 (unloaded);: 75 (tunes with 100pF (C1) 20t of 34e on
7'32" dia. form. SEC. - 00 (unloaded);: 75 (tunes with 100pF (0:1)
20t of 34e on 7'32" dia. form. kQ (percent of critical coupling) ;:
70% (Adjusted for coil voltage (Vel = 150mV).

NOTES:
3. All resistance values ara In ohms.
4. L tunes with 100pF (C) at1 0.7MHz. 00 (unloaded) '" 75 (TOKO No.
KAcs K586HM or equivalent).
5. C = O.01I1F for 50JlS deemphasis (Europe).
C 0.01511F for 75JlS deemphasls (USA).

=

FIGURE 1. TEST CIRCUIT FOR CA3189E USING A SINGLETUNED DETECTOR COIL

B. Above values permit proper operation of mute (squelch) circuit
"E" type slugs. spacing 4mm.
9. C = 0.01 I1F for 50JlSdeemphasis (Europe) C = 0.01511Ffor 7511S
deemphasls (USA).
FIGURE 2. TEST CIRCUIT FOR CA3189E USING A DOUBLETUNED DETECTOR COIL

8-50

CA3189
Block Diagram
I

L

I

I (NOTE 11) I

QUADRATURE
INPUT

I

-

I

TO INTERNAL
REGULATORS
CA3188E
~Wgp~ER-------------

5K

TOSTERED
1)-_ _ _- - - _ THRESHOLD
TUNING METER OUTPUT LOGIC CIRCUITS

U

ON CHANNEL
INDICATOR
47K

NOTES:
10. All resistance values are in 0.
II. L Tunes with IOOpF (C) at IO.7MHz. Qo= 75 (TaKa No. KACS K586HM or equivalent).

CJ

o

...It/)

<~
Z_
<~

...10

M,.....-B

.--------~------------------­
V+~~-----~-----_r-----~_.-------__,

.

V+

D

E

~--------~--------~~------__--~~--~F
AGCFOR
RFAMPL.

LEVEL DETECTOR AND METER CIRCUIT

8·52

TUNING
METER

CA3189

Schematic Diagrams

(Continued)
CA3189E

B

C

D .......i - -................

+-----------......

Cl

--~

E.......

o
-I



0

V+=12V,TA=250C I I
SEE FIGURE 1

J IIII I IIII
TUNER AGC DC

o·
i5~

~::e -20

-

VOLTAGE AT TERM. 15
(RIGHT COORDINATE)
(PIN 15 TO PIN 13)

ci;(

II!w OoJ -30

8II! 8~-40

f-

-50

f-

!5

III

IIf""RECOVERED AUDIO FROM FULL
OUTPUT (LEFT COORDINATE)

mu;
:!!.II! -10

~

V+ _12V, TA. 25°C

I I If

::e -60

I IIII I IIII

VOLTAGE AT TERM. 13
METER CIRCUIT (331Ul
TO GND) (RIGHT

10

100

~

200

10

too

oJ
C

150

8

~

6

(J

lK

SEE FIGURE 1

i!!O 100

~

I!! so

~

c

4

!zw

2

::>

0

a: -50
a:

(J

-100

/

-150
-100

lOOK

10K

~
51Ul !IA

::e
a:

...... 10-

COO~
-III
IJ I I

1

12

-so

INPUT SIGNAL !ltV)

FIGURE 4. MUTING ACTION, TUNER AGC, AND TUNING
METER OUTPUTvs INPUT SIGNAL VOLTAGE

V+

o

= 12V, TA = 25°C

140

-10

9

120

m -20

i=

~
z

§
~

\

100

\

80

~

20

o

......

r---

~

-60

II!

-60

SIGU~

10

15

~~

25

~~ II

.~

LOAD RESISTANCE (BEtWEEN TERM. 7 AND TERM. 10) (1Ul)

10

I III I

I I

• • • • CA3189E PRECEDED BY
2 FILTER AND GAIN STAGES

II

1

I

CA3189E ONLY
....... CA3189E PRECEDED BY
FILTER AND GAIN STAGE

\ ~

-70

20

150

lDEllllll: ±t5Ll

II

~-r:-:

-30

~

.

-80

5

0
50
100
CHANGE IN FREQUENCY (kHz)

I

§ -40

"

40

- ,I'

:!!.

,

60

V

FIGURE 5. AFC CHARACTERISTICS (CURRENT AT
TERMINAL 7 vs CHANGE IN FREQUENCy)

I
~
a:

/

/

/

V

l/

.

~

II I

• I......

JI I

•

NOISE

.'

.~

102
103
SIGNAL LEVEL (1lV)

(!'

FIGURE 6. DEVIATION MUTE THRESHOLD vs LOAD
RESISTANCE (BETWEEN TERMINAL 7 AND
TERMINAL 10)

FIGURE 7. TYPICAL LIMITING AND NOISE CHARACTERISTICS

o.....

etC/)

z!::

et::::l

..... 0

eta:

UU
w
Il..

C/)

8-55

CA3224E

HARRIS
SEMICONDUCTOR

Automatic Picture Tube Bias Control Circuit

November 1996

Features
Description

• Automatic Picture Tube Bias Cutoff Control

The CA3224E is an automatic picture tube bias control circuit used in color TV receiver CRT drive circuits. It is used to
provide dynamic bias control of the grey scale both initially
and over the CRT operating life, compensating for CRT cutoff changes.

• Automatic Background Color Balance
• Eliminates Grey Scale Adjustments
• Compensates for Cathode-to-Heater Leakage
• Electrostatic Protection on All Pins
• Servo Loop Design
• Wide Dynamic Range
• Three-Gun Control
• Minimal External Components

Ordering Information
PART NUMBER
CA3224E'

TEMP.
RANGE ("C)
-401085

PACKAGE
22 LdPDIP

PKG.
NO.

The CA3224E provides automatic continuous control of the
cutoff current in each gun of a three-gun color CRT. From an
input pulse amplitude proportional to the difference between
the desired and the actual CRT cutoff, a gated sample/hold
circuit generates a DC correction voltage which correctly
biases the CRT driver circuit. The sample/hold bias correction takes place each frame following the vertical blanking.
Figure 1 shows a block diagram of the CA3224E. The functions include three identical servo loop transconductance
amplifiers with a samplelhold switch and buffer amplifier plus
control logic, internal bias and a mode switch.

E22.4

Pinout
CA3224E

(PDIP)
TOP VIEW

GROUND

Vee

CHANNEL 1 INPUT

CHANNEL 1 HOLD CAP

CHANNEL 1 FREQ COMPENSATION

CHANNEL 1 OUTPUT

CHANNEL 2 INPUT

CHANNEL 2 HOLD CAP

CHANNEL 2 FREQ COMPENSATION

CHANNEL 2 OUTPUT

CHANNEL 3 INPUT

CHANNEL 3 HOLD CAP

CHANNEL 3 FREQ COMPENSATION

CHANNEL 3 OUTPUT

VERTICAL INPUT

VREFBYPASS

GROUND

AUTO BIAS LEVEL ADJUST

HORIZONTAL INPUT

AUTO BIAS PULSE OUTPUT

GRID PULSE OUTPUT

PROGRAM PULSE OUTPUT

CAUTION: These devices are sens~lve \0 eleclrostallc discharge. Users should Iollow proper IC Handling Procedures.
Copyright © Harris Corporallon 1996

8-56

File Number

1553.1

CA3224E
Absolute Maximum Ratings

Thermal Information

TA = 25°C

Supply Voltage (Vee) ................................. 11V
DC Input Voltage ................................ -1 to Vee
Output Current ....................... Short Circuit Protected

Operating Conditions

6JA (oCIW)

Thermal Resistance (Typical, Note 1)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Storage Temperature Range ..... . . .. -65°C to 150°C
Maximum Lead Temperature (Soldering lOs) ............. 300°C

Temperature Range .......................... -40°C to 85 0 C
Supply Voltage Range (Typical) .................... 10V ±1 0%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress only mting and opemtion
of the device at these or any other conditions above those indicated in the opemtional sections of this specification Is not implied.

NOTE:
1. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

=

=

=

At TA 250 C, Vee 10V, VBIAS 3.75V, Vv (Pin 8)
See Test Circuit and Timing Diagrams

PARAMETER

TEST PIN NO. SYMBOL

Supply Current

22

Reference Voltage

2,4,6

VREF

Input Current

2,4,6

II

Output Current

Source

17,19,21

Sink
Output Buffer

Input Current
Voltage Gain

Auto Bias Pulse

Output Low

13

High
Current Sink
Grid Pulse Output

Low

11

High
Program Pulse Output

Low

IOM+

II
AV

17,19,21

Transconductance

12

High

TEST CONDITIONS

gM

Measureat4

At pins 16, 18,20,
Measure at4, 51 B

=
Measure att6, VIN =8mVp_p
at 40kHz, 51 =B

VOL

Measure attl

VOH

Measureat4

IOM-

Measure at 4, 52

VOL

Measureat 4

VOH

Measure attl

VOL

Measure at Is

VOH

Vertical Input

8

Vv

See Figure 3

Horizontal Input

10

VH

Auto Bias Pulse Timing Start

13

Finish
Start

11

Finish
Program Pulse Timing

Start

12

Finish

5.6

=7.2V, 51 =B
VBIAS =0.5V, Measure att6, 51 =B
VBIAS =7.0V, Measure att6, 51 =B
VOUT =6.5V, VIN

TYP

MAX

UNITS

-

65

mA

6.0

VIN

Measure attl

Grid Pulse Timing

MIN

lee

IOM17,19,21

=VH (Pin 10) =6.0V, 51 =A, 52 =A,

0.8

0.97
50

6.05

=B

2.5

4.2

8.2

See Figure 3
835

10 to t7, Note 2

1270

10 to t3, Note 2

899

10 to Is, Note 2

1080

10 to ts, Note 2

1080

10 to t7, Note 2

1270

2. All time measurements are made from 50% point to 50% point.

8-57

-

V
nA

-0.8

mA

-

mA

150

nA

1.07

-

100

mS

0.3

V

-

mA

0.4

V

-

V

0.4

V

V

6.0

-

842

I1S

1275

I1S

-

CJ

o..J

«en

z!::
«~

..JO

-

6.0

10 to t2, Note 2

NOTE:

-

6.4
250

V
V
V

905

I1S

1084

I1S

1084

I1S

.1275

I1S

«IX

00
W
Il.

en

CA3224E

Device Description and Operation
(See Figures 1, 2, 4 and 5)

During the vertical retrace interval, 13 horizontal sync pulses
are counted. On the 14th sync pulse the auto-bias pulse output goes high. This is used to set the RGB drive of the companion chroma/luma circuit to black level. The auto-bias pulse
stays high for 7 horizontal periods during the auto-bias cycle.
On the 15th horizontal sync pulse, the internal logic initiates
the setup interval. During the setup interval, the cathode current is increased to a reference value (A in Figure 5) through
the action of the grid pulse. The cathode current causes a
voltage drop across RS' This voltage drop, together with the
program pulse output results in a reference voltage at Vs
(summing point) which causes capacitor C1 to charge to a
voltage proportional to the reference cathode current. The
setup interval lasts for 3 horizontal periods.
On the 18th horizontal sync pulse the grid pulse output goes
high, which through the grid pulse amplifierlinverter, causes
the cathode current to decrease. The decrease in cathode
current results in a positive recovered voltage pulse with
respect to the setup reference level at the Vs summing point.
The positive recovered voltage pulse is summed with a negative voltage pulse caused by the program pulse output going
low (cutting off Diode 01 and SWitching in resistors R1 and
R2). Any difference between the positive and negative pulses
is fed through capacitor C1 to the transconductance amplifier.
The difference signal is amplified in the transconductance
amplifier and charges the hold capacitor C2, which, through
the buffer amplHier, adjusts the bias on the driver circuit.
Components Rs, R1, and R2 must be chosen such that the
program pulse and the recovered pulse just cancel at the
desired cathode cutoff level.
CHAN FREQ
1 IN COMP

HOLD
CHAN CHAN FREQ
CAPACITOR 1 OUT 2 IN· COMP

~---------

GND

GND

MODE SWITCH

STATE

2
3

SET-UP
SENSE
OPEN

vee

_____

VREF
BYPASS

HOLD
CAPACITOR

~

CHAN CHAN FREQ
2 OUT 31N COMP

HOLD
CAPACITOR

CHAN
3 OUT

-----01---------'---

_________________ J

VERT
IN

HORIZ
IN

GRID
PULSE
OUT

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

8-58

PROG
PULSE
OUT

AUTO
BIAS
PULSE
OUT

AUTO
BIAS
LEVEL
ADJUST

CA3224E

.

I,

10

12

ta

1.4

l~-r

I

VERTICAL:

15

Ie

17

I
I

i
I

13 14 151
AUTO BIAS
PULSE OUTPUT
(PIN 13)

l2

GRID PULSE OUTPUT
(PIN 11)

II

PROGRAM PULSE
OUTPUT
(PIN 12)

~'

MODESwrrCH
(SEE FIGURE 1)

OPEN

18 171

SET-UP

19

20 21

SENSE

22

23

OPEN

FIGURE 2. FUNCTIONAL TIMING DIAGRAMS

+

VERTICAL SIGNAL OV

~l
O.5ma

HORIZONTAL SIGNAL
OV

~

-I

16.683ma

I

~

L
Iv = 59.94Hz

Itt • 15734.264Hz

CJ

FIGURE 3. VERTICAL AND HORIZONTAL INPUT SIGNALS

o
m
--...--""..~
SYNC

"1I
1M

CRYSTAL
32 TIMES
HORIZ. r:::J
503.496kHz

J1..
HOR. PROCESS
BLANKING

100PF.;.

NOTES:
5. Pin 21 high when pin 20 is high (or open).
6. Pin 1 high Inhibits clock.
FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402

8-66

CLOCK TO
COUNTERS

CD22402
Timing Waveforms
MICROSECONDS __ 0
504kHz
OSC. PIN 2 OR 6
MIXED BLANKING
PIN 13

HORIZ. DRIVE PIN 4

1.98

3.97

:.-- 3.97flS ----.J

--~

r

I

27.78

11.90

:

I

31.75

33.73

==~

I

I

--~---+~

I:

I!

I.

HORIZ. CLAMP
PIN 11

7.94flS

-r-,r-______

I

I

I

flS~

.--3.9
-H.S-YNC-;,
{

9.92

7.94

~,

MIXED BEAM
(CATHODE)
BLANKING
PIN 7

MIXED SYNC
PIN 5

5.95

:

* ' " " ' 1-

-

-

-

-

-

-

-

-

W

W:

-----'1.98flS

- - -.....
EQUALIZING
PULSE
V.SYNC

1.98flSI_

o----------25.8fl8------_-_-~---'.
I :

,'""..

I--

3.97fl8

-l

FIGURE 2. SYNC GENERATOR TIMING - 525160Hz, HORIZONTAL TIMING WAVEFORMS

TO FIRST
EQUALIZING
PULSE
LINENO_
MIXED SYNC
PIN 5

1

VERTICAL RESET
- T O FIRST
VERTICAL PULSE

I

7

456

0

8

I

VERT. DRIVE
PIN 9
VERTICAL
PROCESSING
BLANKING
PIN 17

I

;.:..~--i---......;;..--_;.---O.57mS ---;..--_;.---i----;

~~--------------------------~----------~

1

~--~~--r--r_-_T-------~--r_-~--r_-_T~
IoI..o--_....._ _

WIDE BLANKING
PIN 13

tr1~

'--_~

_ _ 1.33m. _ _ __'__ __+__

__JL..__

_ L_ _....._ __ _

____------________I

1.00--- O.19ms-'

SHORT VERTICAL
DRIVE PIN 16

+-~--~--+-~~

~'_+-~~-+_~-

~

I

MIXED BEAM
(CATHODE)
BLANKING
PIN 7

FRAME;'~~~ ---~Ur-------------------------------_I I-

(ON ALTERNATE FIELDS)

~

1.98fl8 (NOT TO SCALE)

FIGURE 3. SYNC GENERATOR TIMING - 525J60Hz, VERTICAL TIMING WAVEFORMS

8-67

CD22402
Timing Waveforms

(Continued)

MICROSECONDS - - 0
500kHz
OSC. PIN 2 OR 6
MIXED BLANKING
PIN 13

2

4

10

8

6

28

12

32

::

==~

1 1

--

~I
'--.I
1

r+--4~s

HORIZ. DRIVE PIN 4

----il

CATHODE
BLANKING
PIN 7

:

I"

1
1

t:

i

1

I

1

::

8~s

1
1

--:--p'_______

:

1---:
1

:

I

2~.

------~:----~--~~LJr--------------

HORIZ. CLAMP
PIN 11

1

I

1

-H.Sy--ilNC,

:

t - - I- - - -

r+--4~-....

MIXED SYNC
PIN 5

{

---'2~.

2~~

f
I
t----'

- - -....
EQUALIZIN;

0----------- 26~ _ _ _ _ _ _ _ _ _---<...1

PULSE 101..

---I.
~SyNCiL___________________ __ ------J~

,.

.

:,

1

1

'
! :

1--4~--I
FIGURE 4. SYNC GENERATOR TIMING - 625J50Hz, HORIZONTAL TIMING WAVEFORMS

VERTICAL RESET TO
FIRST EQUALIZING
PULSE
LlNENO_
MIXED SYNC
PIN 5

r

1

VERTICAL RESET
TO FIRST
VERTICAL PULSE

7

456

0

8

9

10

21

1

VERT. DRIVE
PIN 9
VERTICAL
PROCESSING
BLANKING
PIN 17

"':.......--i---ir---i----0.57mS ---i----i---i----<•.;I

1

~---~---~

-T---;

1~.-_T--T--~-~-------------+_--~--~----~--_T~

1
1

101.......-~_~~_~_____ l.$ms _ _r_-~--~-~--~--~.,
WIDE BLANKING
PIN 13

--.nr

in
,-"-O.l94ms -----r

SHORT VERTICAL
DRIVE PIN 16

-+--~---+--~--~~

.

~I--~--~--~--~---:---

---u-

CATHODE
BLANKING
PIN 7
FRAME SYNC
PIN 15
(ON ALTERNATE FIELDS)

u

--.j ~ 2~s (NOT TO SCALE)

FIGURE 5. SYNC GENERATOR TIMING - 625J50Hz, VERTICAL TIMING WAVEFORMS

8-68

CD22402
Timing Waveforms

(Continued)
LlN~

FIELD NO. 1

I

L
I

PINS ---i~r--

PIN 9

--:
I-l

...............

1 ClK

~

~2~

~

2 ClKS

~2~

LINE 271 (321)

~

~

·"'l-: I-'~
--I

f-

E l l..-,..., ......-

LINE 262-112 (312-112)
PINS

1

--:

.

FIELD NO. 2

u . ..
LINE 9

FIRST EQUALIZING PULSE

-: f-

,

1ClK

~ 14ClKS

~ 2ClKS

I
----I

SEE NOTES 1, 2

FIGURE 6. EXPANDED VERTICAL·TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL DRIVE - PIN 9)

FIELD NO. 1

LI'!!J

I

PINS

IL

FIRST EQUALIZING PULSE

~r--

--: I-

·""l

1 ClK

I
--I

N

---I f-

-"l-:
~

CJ

9

2 ClK.S• •

«IJ)

z!::

«:I
..... 0
«a:
00
w

,,
,

: - 2ClKS

c..
IJ)

. . . . . . . . . . . . . . . ~ ••••

--: I-

1-'''''

~

f-

liNE 283 (333) 1

LINE 262-112 (312-112)

PINS---iU

1

-.:

~ ~2~

FIELD NO.2

LINE 21

.....•......... ~ ....

_

2ClKS
SEE NOTES 1,2

2ClKS

14ClKS

I

---l

FIGURE 7. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL PROCESSING
BLANKING - PIN 17)

8·69

CD22402

Timing Waveforms
FIELD NO. 1

(Continued)

LINE 0
PINS

LINE 21

-I I--

--I

FIRST EQUAUZING PULSE

~------------------

-; r-

1 elK

lJ
I-- 2 ClKS

.......;

~~'~

,

.."l. -:--------ie~~a________-1. .J. I::I~. I

n

___....

--I :- 2 ClKS

FIELD NO. 2

1 ClK

LINE 262-112 (312-112)
PINS

•

6 ClKS-.l

LINE 283 (333)

~------------------~
- : 1--1 ClK

I--

-.;

""l~__i__________________

~'

2 ClKS

IRl______________________ ________________

~r­

: _ 14ClKS---I

: - - 2ClKS
SEE NOTES 1, 2

FIGURE 8. EXPANDED VERTICAL·TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED PROCESSING
BLANKING· PIN 13)
FIELD NO.1

LINE 3

LINE 6

... ~___________________ ~-Jl1CLK
Ar-----l

I

'-- 2 ClKS

""l :

FIELD N O . 2 liNE 265-112 (315-112)

_

tl

' - - 2 ClKS

Ii
.

LINE 268-112 (318-112)

"'~---------------------$---I

""l :
--l

N

~2~

I,

~
SEE NOTES 1, 2

FIGURE 9. EXPANDED VERTICAL·TIMING WAVEI=ORM DETAIL OF SYNC GENERATOR TIMING
(SHORT VERTICAL DRIVE· PIN 16)

8-70

I

~2~

CD22402

Timing Waveforms

(Continued)

LINE 2
PIN 5

PIN 7

LINE 3

--I

I

4

I-- --I ,-

2 ClKS

2 ClKS

--I I----i 4 ClKS

JU-- -if --

LINE 268-112 (318-112)

LINE 265-112 (315-112)

poo-------.

I

~
U

1 ClK - ;
PIN7

liNE 7

if -lf~i- ------- ------Itr -u-u-efT . hJ ----L

ClKS
liNE 265 (315)

PIN 5

liNE 6

~----------

I--- 15 ClKS - ;

1--1

- I : - 2 ClKS fa

2 ClKS

I

r:"U";

II

4 ClKS

liNE 269 (319)

I

;

;

-I ~
,16 ClKS

SEE NOTES 7, 8

NOTES:
7. Waveforms shown are for 525 line/60Hz, line number in parenthesis are for (625 line/50Hz).
8. Timing widths by clock count; for 525 line, 1 elK =1.98I1S; for 625 line, 1 elK =211S; 1 horizontal period =32 elKS.
FIGURE 10. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED BEAM BLANKING - PIN 7)

Typical Applications (Refer to Application Note AN8742, for more information)

MIXED SYNC. OR
COMPOSITE VIDEO INPUT

HORIZONTAL DRIVE
HORIZONTAL CLAMP
MIXED BEAM (CATHODE) BLANKING
MIXED PROCESSING BLANKING
HORIZONTAL PROCESSING BLANKING

L - - -..... l0

VERTICAL SYNC ~E----"""'''
(OPTIONAL)

"o cn
..I

~!::

2OpF, a 500 resistor is recom·
mended between Vour and VZ+. using VZ+ as the output (see
Figure 2). This will prevent the multiplier from going unstable.

Power Supply Decoupling
Power supply decoupling is essential for high frequency cir·
cuits. A 0.01 ~F high quality ceramic capacitor at each supply
pin in parallel with a 1~F tantalum capacitor will provide
excellent decoupling. Chip capacitors produce the best
results due to the close spacing with which they may be
placed to the supply pins minimizing lead inductance.

Adjusting Scale Factor

FIGURE 2.

Adjusting the scale factor will tailor the control signal. Vx. input
voltage range to match your needs. Referring to the simplified
schematic on the front page and looking fOr the Vx input stage.
you will notice the unusual design. The internal reference sets
up a 1.2mA current sink for the Vx differential pair. The control
signal applied to this input will be forced across the scale factor
setting resistor and set the current flowing in the Vx+ side of the
differential pair. When the current through this resistor reaches
1.2mA, all the current available is flowing in the one side and full
scale has been reached. Normally the 1.67kn internal resistor
sets the scale factor to 2V when the Gain Adjust pins Band C
are connected together, but you may set this resistor to any
convenient value using pins 16 (GA A) and 15 (GA C) (See
Figure 3).

8·78

HA-2546

VOUT

MULTIPLIER, VOUT = VXVy 12V
SCALE FACTOR

=2V

FIGURE 4. AUTOMATIC GAIN CONTROL

Voltage Controlled Amplifier
A wide range of gain adjustment is available with the Voltage
Controlled Amplifier configuration shown in Figure 5. Here
the gain of the HFA0002 is swept from 20VN at a control
voltage of O.902V to a gain of almost 1000VN with a control
voltage of O.03V.

VOUT

Video Fader
MULTIPLIER, VOUT

= VXVy 15V

SCALE FACTOR

The Video Fader circuit provides a unique function. Here Ch B
is applied to the minus Z input in addition to the minus Y input.
In this way, the function in Figure 6 is generated. VMIX will
control the percentage of Ch A and Ch B that are mixed
together to produce a resulting video image or other signal.

= 5V

FIGURE 3. SETTING THE SCALE FACTOR

Typical Applications
Automatic Gain Control
In Figure 4 the HA-2546 is configured in a true Automatic
Gain Control or AGC application. The HA-5127, low noise op
amp, provides the gain control level to the X input. This level
will set the peak output voltage of the multiplier to match the
reference level. The feedback network around the HA-5127
provides stability and a response time adjustment for the
gain control circuit.

Many other applications are possible including division,
squaring, square-root, percentage calculations, etc. Please
refer to the HA-2556 four quadrant multiplier data sheet for
additional applications.

This multiplier has the advantage over other AGC circuits, in
that the signal bandwidth is not affected by the control signal
gain adjustment.

8-79

CJ

o
'
.sw

!Il

12

900
825

1\

500

i

525
450

~

300
225
150
75

---. -

10

750
675

-!!S=RENT

-

~
i!i 375

o

"'"

OFFSET CURRENT

-2

o

-4

1

10

100

1K

10K

100K

o

-25

-55

FREQUENCY (Hz)

25

50

75

100

125

TEMPERATURE fc)

FIGURE 13. VOLTAGE NOISE DENSITY

FIGURE 14. Vy OFFSET AND BIAS CURRENT VB TEMPERATURE

10

3

8

S
.5.
w

~
!j
~

Iii
~
o

6
4

~
2

-

-

0
-2
-4
-6

---...
Vz

2

---.

Vx

--- ---

~

....

!;lIAS CURRENT

OFFSET CURRENT

o

-6

-10

o

-25

-55

25

50

75

100

-1
-55

125

-25

TEMPERATURE (DC)
FIGURE 15. OFFSET VOLTAGE

VB

TEMPERATURE

120

iii

~ r-. ......
.....
~
+Vo~

:!!.

-VOUT

"-

3
2

o

±17

±15

50

100

75

125

FIGURE 16. Vx OFFSET AND BIAS CURRENT VB TEMPERATURE

100

......,.

25

TEMPERATURE fC)

7

6

o

±12

±8

'\

±7

II:
II:

::IE
0

\..

VYcm

= 200mVRMS

,80

.....;; ~

60
40

vx~ov _

r-- ~

VX~2~~

20
0

±5

100

1K

10K

100K

1M

10M

FREQUENCY (Hz)

VSUPPLY

FIGURE 1B. Vy CMRR VB FREQUENCY

FIGURE 17. VOUT VB VSUPPLY

8-82

100M

HA-2546

Typical Performance Curves
120
100

iii' 80

I I Vx = 200mVRMS

~

i:i

40

--

20

100

···.3Y!0~

I

60 I-- Vy =';V' ~

~

Vs = ±15V, TA = 25°C, See Test Circuit For Multiplier Configuration (Continued)

+p~sJ

80

iii'

:2- 60

- r--..

~

IE:
IE:

~

I-

o

100

Vy = Vx =OV

20
0

1K

10K

1M

100K

10M

100

100M

1K

10K

FIGURE 19. Vx COMMON MODE REJECTION RATIO vs
FREQUENCY

25

14

I

I"'..

12

C

g
:>

10

I
+Icc

a:

::E

20

S:!

CJ

6

:>

4

Ul

l"-

8

~

II.
II.

"""I"-

I"" .......

"- ~

.............

CMR(+) .....

2
15
-55

·25

o

25

50

I"" 1"0 ....

1M

r-

10M

100M

FIGURE 20. PSRR vs FREQUENCY

·Icc
I-

100K

""

FREQUENCY (Hz)

FREQUENCY (Hz)

Z
UJ
IE:
IE:

"'" ......

·PSSR

40

75

100

~MR(.)

~

"

i' ......
~ ..... ........

0

125

±17

TEMPERATURE (DC)

±15

±12

±s

±7

VSUPPLY

FIGURE 21. SUPPLY CURRENT vs TEMPERATURE

FIGURE 22. CMR vs VSUPPLY

±5

Cl

o
<~
z_

...len

<::::I

100

...10



2r_----_r----~r_----_r----~~----~

I

.......-X=0.8
X=0.4,O.6

~

~

~
a:

.~ .....

-1

:E

Vs =±1SV, TA = 2SoC, See Test Circuit For Multiplier Configuration (Continued)

~

-1.5

~

-1
-1.5 '--____-'-____---J'--____- ' -____---J'--____..J

·2
-6

-2

-4

0
YINPUTM

4

2

o

6

0.5

1.5

2.5

2

X INPUT (V)

FIGURE 25.

FIGURE 26.

2.0
1.9
1.8
~ 1.7
a: 1.6
o 1.5
~ 1.4
W 1.3
Z
1.2
!2 1.1

-

~ ~:g

~_
_
!l

0.8
0.7
0.6

51 g:~

0.3
0.2
0.1

~'-------'-----~------'------~----~
2.5
0.5
o
2
1.5

0.0
-55

-25

o

25

50

75

100

125

TEMPERATURE (OC)

X INPUT (V)

FIGURE 28. WORST CASE MULTIPLICATION ERROR VB
TEMPERATURE

AGURE27.

0.5
0.6

~

a:

RL = 1 K, Vx = 2Voc, Vy " 200mVRMS

I

0.4

Ii!a:

0.4

w 0.3

I

~

~

/'

S.!
.... 0.2

V

!!:

!l
:::>

Z

I

0.2

~
0

./

:E 0.1

,

-D.2
0.0
·55

-25

o

25

50

75

100

TEMPERATURE fc)

--

If
~ i"'" CL =OpF

II

I

-

II

10K

125

I

CL=50pF

iG

z

100K

1M

10M

FREQUENCY (Hz)

FIGURE 29. MULTIPLICATION ERROR VB TEMPERATURE

FIGURE 30. GAIN VARIATION VB FREQUENCY

8-84

100M

HA-2546

Typical Performance Curves

Vs = ±15V, TA s 25°C, See Test Circuit For Multiplier Configuration (Continued)

2.010

7.0

fO = 10kHz, Vx = 2VDC, THD < 0.1%

2.008
2.006

a:

~

..."'(Jw

-

2.004
2.002
2.000
1.998

~

w

~

I'---

11111
_Vs=tI5

II-III

5.0

fVs=±12

~

4.0

,

I!:

3.0

0
II:

2.0

~
!:i

~

_!

6.0

!;

oC

1.994

W

II.

1.992
1.990

~Vs=tl0

iI""

, ""

~

en 1.996

I

Vs=±8

III

1.0
0.0

·25

·55

o

25

50

75

100

125

10

100

lK

10K

lOOK

LOAD RESISTANCE (n)

TEMPERATURE ("C)

FIGURE 31. SCALE FACTOR V8 TEMPERATURE

FIGURE 32. OUTPUT VOLTAGE SWING VB LOAD RESISTANCE

500

24
22
20

VyCHANNEL

400

r- - r-

Vx CHANNEL

r- - r-

Vy CHANNEL

18

c:.w~

300

oS 14
w

~

200

1=
w 10
!II

'OJ' 16

!ca:

...enw

::Ii

12

a:

8

VxCHANNEL

100

6
4
2

o
~O

·40

·20

0

20

40

60

80

100

o

120

~

·40

·20

0

TEMPERATURE ("C)

FIGURE 33. SLEW RATE VB TEMPERATURE

~

.§.
Izw
a:
a:
~

u

~

II.
Do.

~

en

28
26
24
22
20
18
16
14
12
10
8
6
4
2

20

40

60

80

100

120

TEMPERATURE (DC)

FIGURE 34. RISE TIME VB TEMPERATURE

"o

.Jrn
Z_

r-

-Icc,

""I""::::I

I

.JO

I""=ICC

UU

""a:
w

a..

I
I

o

2

rn

4

6

8

10

12

14

16

18

SUPPLY VOLTAGE (tV)

FIGURE 35. SUPPLY CURRENT VB SUPPLY VOLTAGE

8·85

20

HA-2546

Die Characteristics
DIE DIMENSIONS:

PASSIVATION:

79.9 mils x 119.7 mils x 19 mils

Type: Nitride (Si3N4) over Silox (Si02. 5% Phos)
Silox Thickness: 12kA ±2kA
Nitride Thickness: 3.5kA ±2kA

METALLIZATION:
Type: AI. 1% Cui
Thickness: 16kA ±2kA

TRANSISTOR COUNT:

87

Metallization Mask Layout
HA-2546

GAA GAC

VREF GND

2

16

1

15

14 GAB

13 Vx+

12 Vx-

11

7

8

V-

VOUT

.. 9

Vz+

8-86

10

Vr

V+

100MHz, Two Quadrant,
utput, Analog Multiplier

November 199

Description
• Low Multiplication Error •.•.•••••••••.•..•••• 1.6%
• Input Bias Currents .••••...•••.•••••.••••.. 1.2J.1A
• Signal Input Feedthrough at SMHz ••....•.•••• -SOdB
• Wide Signal Bandwidth ••.•••••••••••.••.• 100MHz
• Wide Control Bandwidth ..•....•.•• , •••..•• 22MHz

Applications
• Military Avionics
• Missile Guidance Systems
• Medical Imaging Displays
• Video Mixers
• Sonar AGC Processors

The single-ended current output of the HA-2547 has a
100MHz signal bandwidth (RL = 50n) and a 22MHz control
input bandwidth. High bandwidth and low distortion make this
part an ideal component in video systems. The suitability for
precision video applications is demonstrated further by low
multiplication error (1.6%), low feedthrough (-50dB), and differential inputs with low bias currents (1.2J,1A). The HA-2547 is
also well suited for mixer circuits as well as AGe applications
for sonar, radar, and medical imaging equipment.
The current output of the HA-2547 allows it to achieve higher
bandwidths than voltage output multipliers. An internal feedback resistor is provided to give an accurate current-to-voltage conversion and is trimmed to give a full scale output
voltage of ±5V. The HA-2547 is not limited to multiplication
applications only; frequency doubling and power detection
are also possible.

• Radar Signal Conditioning
• Voltage Controlled Amplifier
• Vector Generator

Ordering Information
PART NUMBER

The HA-2547 is a monolithic, high speed, two quadrant, analog multiplier constructed in Harris' Dielectrically Isolated
High Frequency Process. The high frequency performance
of the HA-2547 rivals the best analog multipliers currently
available including hybrids.

TEMP.
RANGEfc)

PACKAGE

PKG.
NO.

HA1-2547-5

010 75

16LdCERDIP

F16.3

HA1-2547-9

-40 to 85

16LdCERDIP

F16.3

Pinout

CJ

o

Schematic

-'UJ

c(~
Z_

HA-2547
(CERDIP)
TOP VIEW

c(::::I

-,0
c(a:

00
w
UJ

a..

GAA
GAC

GAB
Yx+

vxY+

RZ

CAUTION: These devices are sensitive to electrostatiC discharge. Users should follow proper IC Handling Procedures.
Copyright @ Harris Corporation 1996

8-87

File Number

2862.2

HA-2556

Im'HARRlS
\AJ' S E M I 'C 0 N D UC TOR

57MHz, Wideband, Four Quadrant,
Voltage Output Analog Multiplier

November 1996

Features

Description

• High Speed Voltage Output ....•........•.• 450VlllS

The HA-2556 is a monolithic, high speed, four quadrant,
analog multiplier constructed in the Harris Dielectrically
Isolated High Frequency Process. The voltage output
simplifies many designs by eliminating the current-to-voltage
conversion stage required for current output multipliers. The
HA-2556 provides a 450VlllS slew rate and maintains
52MHz and 57MHz bandwidths for the X and Y channels
respectively, making it an ideal part for use in video systems.

• Low Multiplication Error ••.•.•....••..•...••• 1.5%
• Input Bias Currents .•.•.......•........•..... 81lA
• 5MHz Feedthrough ...............•...•..... -50dB
• Wide Y Channel Bandwidth ....••...•...••• 57MHz
• Wide X Channel Bandwidth ....•.•......•.. 52MHz
• Vy O.1dB Gain Flatness ...................• 5.0MHz

Applications
• Military Avionics

The suitability for precision video applications is demon·
strated further by the Y Channel 0.1 dB gain flatness to
5.0MHz, 1.5% multiplication error, ·50dB feedthrough and
differential inputs with 81lA bias current. The HA·2556 also
has low differential gain (0.1 %) and phase (0.1 0 ) errors.
The HA·2556 is well suited for AGC circuits as well as mixer
applications for sonar, radar, and medical imaging equipment. The HA·2556 is not limited to multiplication applica·
tions only; frequency doubling, power detection, as well as
many other configurations are possible.

• Missile Guidance Systems
• Medical Imaging Displays
• Video Mixers
• Sonar AGC Processors
• Radar Signal Conditioning

For MIL·STD·883 compliant product consult the HA·
2556/883 datasheet.

• Voltage Controlled Amplifier

Ordering Information

• Vector Generators
PART NUMBER

Pinout

TEMP.
RANGE (DC)

PKG.
NO.

PACKAGE

HA3-2556·9

-401085

16 Ld PDIP

E16.3

HA9P2556·9

-401085

16 Ld sOle

M16.3

HAl-2556-9

·40 to 85

16 LdCERDIP

F16.3

Functional Block Diagram
HA-2556
(PDIP, CERDIP, SOIC)
TOP VIEW

HA-2556

vx+

VOUT

I Vx-

1/SF

:

---+l[XJr---t

vy+
VV"'

NOTE: The transfer equation for the HA-2556 is:
(Vx+ -Vx-) (Vy+ -Vy_) = SF 01z+ -Vz-),
where SF Scale Factor 5V; Vx. Vy. Vz

=

=

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

8·88

=Differential Inputs.

File Number

2477.4

HA-2556
Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- Terminals .................... 35V
Differential Input Voltage................................ 6V
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±60mA

Thermal Resistance (Typical, Note 1)
9JA (oclW) 9JC (oCIW)
PDIP Package...................
77
N/A
SOIC Package... ..... . ....... .. .
90
N/A
CERDIP Package . . . . . . . . . . . . . . . .
75
20
Maximum Junction Temperature (Ceramic Package) . . . . . .. 1750 e
Maximum Junction Temperature (Plastic Packages) ...... 1500 e
Maximum Storage Temperature Range ......... -650 e to 150°C
Maximum Lead Temperature (Soldering lOs) ............ 3000 e
(SOle - Lead Tips Only)

Operating Conditions
Temperature Range ......................... -40°C to 85°C

CAUTION: Stresses above those listed In "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VSUPPLY

=±15V, RF =500, RL =1ko, CL =20pF, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

TEMP.fC)

MIN

TYP

MAX

UNITS

MULTIPLIER PERFORMANCE

Transfer Function
V OUT
MuHiplication Error

Note 2

rVx+ - Vx.l x (Vy+ - Vy.)
5

Multiplication Error Drift

Full

Scale Factor

25
25
25

=±3V, Full Scale =3V
VX, Vy =±4V, Full Scale =4V
VX, Vy =±5V, Full Scale =5V
VX, Vy

(Vz+ - Vz.lJ

1.5

3

·

3.0

6

%

-

0.003

-

%flC

·

5

V

-

0.02

%

·

25
Full

Linearity Error

=A

%

0.05

0.25

%

25

0.2

0.5

%

25

57

25

52

MHz
MHz
V/jlS

AC CHARACTERISTICS

Small Signal Bandwidth (·3dB)
(;'

Vy
Vx

=200mVp.p, Vx =5V
=200mVp.p, Vy =5V

Full Power Bandwidth (·3dB)

10Vp.p

25

·

32

Slew Rate

Note 5

25

420

450

MHz

(!J

o

....I

Rise Time

Note 6

25

·

8

Overshoot

Note 6

25

·

20

Settling Time

To 0.1%, Note 5

25

-

ns

Notes 3, 8

25

-

100

Differential Gain

0.1

0.2

%

Differential Phase

Notes 3, 8

25

·

0.1

0.3

Degrees

Vy 0.1 dB Gain Flatness

200mVp_p, Vx

25

4.0

5.0

Vx 0.1 dB Gain Flatness

=5V, Note 8
200mVp_p, Vy =5V, Note 8

25

2.0

4.0

THD+N

Note 4

25

-

0.03

1MHz Feedthrough

200mVp.p, Other Ch Nulled

25

5MHz Feedthrough

200mVp.p, Other Ch Nulled

25

·65
·

·

ns
%

MHz

·

MHz

·

dB

%

·50

dB

SIGNAL INPUT (Vx, Vy, Vz)

Input Offset Voltage

25

Average Offset Voltage Drift

8-89

3

15

mV

Full

·

8

25

mV

Full

·

45

·

jlV/oC

20pF a 50Q resistor should
be connected between VOUT and Vz+, using Vz+ as the
output (see Figure 1). This will prevent the multiplier from
going unstable and reduce gain peaking at high frequencies.
The 50Q resistor will dampen the resonance formed with the
capacitive load and the inductance of the output at pin 8.
Gain accuracy will be maintained because the resistor is
inside the feedback loop.

The open loop transfer equation for the HA-2556 is:

Theory of Operation

where;

The HA-2556 creates an output voltage that is the product of
the X and Y input voltages divided by a constant scale factor of
5V. The resulting output has the correct polarity in each of the
four quadrants defined by the combinations of positive and negative X and Y inputs. The Z stage provides the means for negative feedback (in the multiplier configuration) and an input for
summation into the output. This results in the following equation, where X, Y and Z are high impedance differential inputs.

The Balance Concept
VOUT = A [

(V x+ -Vx'> x (Vy+ -Vy.l
]
SV
- (Vz+ Vzl

Output Amplifier Open Loop Gain

A
Vx, Vy, Vz
5V

= Differential Input Voltages
Fixed Scaled Factor

An understanding of the transfer function can be gained by
assuming that the open loop gain, A, of the output amplifier
is infinite. With this assumption, any value of VOUT can be
generated with an infinitesimally small value for the terms
within the brackets. Therefore we can write the equation:

0=

(Vx+ -Vx '> x (Vy+ -Vy_l
SV
- (Vz+ -Vz'>

CJ

o

which simplifies to:

.....len

(VX+ -V x '> x (Vy+ -Vy. l = SV (Vz+ -Vz'>
This form of the transfer equation provides a useful tool to
analyze multiplier application circuits and will be called the
Balance Concept.

Typical Applications
Let's first examine the Balance Concept as it applies to the
standard multiplier configuration (Figure 2).

V

20PF

FIGURE 1. DRIVING CAPACITIVE LOAD

A -

XxV
VOUT= -s--z
To accomplish this the differential input voltages are first converted into differential currents by the X and Y input transconductance stages. The currents are then scaled by a constant
reference and combined in the multiplier core. The multiplier
core is a basic Gilbert Cell that produces a differential output
current proportional to the product of X and Y input signal currents. This current becomes the output for the HA-2557.

8-91

1--""'. . .

'>--II.....-w

...

y+

B

~
..

Y

Vy-

FIGURE 2. MULTIPLIER

eClZ_
eC::::I
.....10
eCct

C3C3

w
a..
en

HA-2556
Signals A and B are input to the multiplier and the signal W
is the result. By substituting the signal values into the Balance equation you get:

Which simplifies to:
A2

W=s
(A) x (8) = 5(W)

The last basic configuration is the Square Root as shown in
Figure 5. Here feedback is provided to both X and Y inputs.

And solving for W:
W=Ax8
5

i>--........+

Notice that the output (W) enters the equation in the feedback to the Z stage. The Balance Equation does not test for
stability, so remember that you must provide negative feedback. In the multiplier configuration, the feedback path is
connected to VZ+ input, not Vz:. This is due to the inversion
that takes place at the summing node just prior to the output
amplifier. Feedback is not restricted to the Z stage, other
feedback paths are possible as in the Divider Configuration
shown in Figure 3.

W

FIGURE 5. SQUARE ROOT (FOR A > 0)

The Balance equation takes the form:
(W)x(-W)

,.>--+-+w

= 5(-A)

Which equates to:
W=

The four basic configurations (Multiply, Divide, Square and
Square Root) as well as variations of these basic circuits
have many uses.
.

FIGURE 3. DIVIDER

Inserting the Signal values A, Band W into the Balance
Equation for the divider configuration yields:
(-W) (6) = 5Vx (-A)

Solving for W yields:
6

Signals may be applied to more than one input at a time as
in the Squaring configuration in Figure 4:
Here the Balance equation will appear as:

= 5(W)
HA-2556

A _

x

(ACos(ro~»

= 5(W)

And using some trigonometric identities gives the result:

Notice that, in the divider configuration, signal B must remain
~o (positive) for the feedback to be negative. If signal B is
negative, then it will be multiplied by the Vx_ input to produce
positive feedback and the output will swing into the rail.

x (A)

Frequency Doubler
For example, if ACos(OYt) is substituted for signal A in the
Square function, then it becomes a Frequency Doubler and
the equation takes the form:
(ACos(ro~»

W=~

(A)

J5A

---11"'"

........

"~

_ _........... w

A2
W = 15(1 + Cos(2rot»

Square Root
The Square Root function can serve as a precision/wide
bandwidth compander for audio or video applications. A
compander improves the Signal to Noise Ratio for your system by amplifying low level signals while attenuating or
compressing large signals (refer to Figure 17; XO. 5 curve).
This provides for better low level signal immunity to noise
during transmission. On the receiving end the original signal
may be reconstructed with the standard Square function.

Communications
The Multiplier configuration has applications in AM Signal
Generation, Synchronous AM Detection and Phase Detection to mention a few. These circuit configurations are shown
in Figures 6, 7 and 8. The HA-2556 is particularly useful in
applications that require high speed signals on all inputs.
FIGURE 4. SQUARE

8-92

HA-2556
restricted input, so it may become necessary to modify the
scale factor. Adjusting the scale factor may also be useful
when the input signal itself is restricted to a small portion of
the full scale level. Here we can make use of the high gain
output amplifier by adding external gain resistors. Generating the maximum output possible for a given input signal will
improve the Signal to Noise Ratio and Dynamic Range of the
system. For example, let's assume that the input signals are
1VPEAK each. Then the maximum output for the HA-2556
will be 200mV. (1V x 1V)/(5V) 200mV. It would be nice to
have the output at the same full scale as our input, so let's
add a gain of 5 as shown in Figure 9.

ACOS(OlAt)
Audio

CCOS(roct)~y+
--+
Y
Carrier

_

Vy-

AC

W = lO(COS(!IlC - !IlA)t + COS(!IlC

=

+ !IlA)t)

FIGURE 6_ AM SIGNAL GENERATION

.--r.1!oo..

AM SI.:.9n
;;,.:8+1

A --+III--n-..

carrl~

B~y+
+
Y

~

>--IH_.W

vY-

250n

ExternalGain =

LIKE THE FREQUENCY DOUBLER YOU GET AUDIO CENTERED AT DC
AND2Fc_

RG

R
RF

+1

G

FIGURE 7_ SYNCHRONOUS AM DETECTION

FIGURE 9. EXTERNAL GAIN OF 5

HA-2556

One caveat is that the output bandwidth will also drop by this
factor of 5. The multiplier equation then becomes:

ACOS.;.(cot_)-+lI-_n-..

.>-.....-..- W

5AB
W=S=AxB

Current Output

DC COMPONENT IS PROPORTIONAL TO COS(I)

FIGURE 8. PHASE DETECTION

Each input X, Y and Z has similar wide bandwidth and input
characteristics. This is unlike earlier products where one
input was dedicated to a slow moving control function as is
required for Automatic Gain Control. The HA-2556 is versatile enough for both.
Although the X and Y inputs have similar AC characteristics,
they are not the same. The designer should consider input
parameters such as small signal bandwidth, AC feedthrough
and 0.1 dB gain flatness to get the most performance from
the HA-2556. The Y channel is the faster of the two inputs
with a small signal bandwidth of typically 57MHz verses
52MHz for the X channel. Therefore in AM Signal Generation, the best performance will be obtained with the Carrier
applied to the Y channel and the modulation signal (lower
frequency) applied to the X channel.

Another useful circuit for low voltage applications allows the
user to convert the voHage output of the HA2556 to an output
current. The HA-2557 is a current output version offering
100MHz of bandwidth, but its scale factor is fixed and does not
have an output amplifier for additional scaling. Fortunately the
circuit in Figure 10 provides an output current that can be
scaled with the value of RCONVERT and provides an output
impedance of typically 1MU The equation for lOUT becomes:
I

z!::

_AxBx
1
5
RCONVERT

<::l
-,0
--I~y.,.+-.IOUT

B~Y+
+
Y

-

vyFIGURE 10. CURRENT OUTPUT

c..

en

HA-2556
The Balance equation looks like:
(VMlx)x(ChA-ChB)

= S(VOUT-ChB)

Which simplifies to:
V

VOUT

M1X
= ChB+-s-(ChA-ChB)

=

When VMIX is OV the equation becomes VOUT Ch Band
Ch A is removed, conversely when VMIX is 5V the equation
becomes VOUT Ch A eliminating Ch B. For VMIX values
OV ::; VMIX ::; 5V the output is a blend of Ch A and Ch B.

.."..f-........._B
.......f-.....I--I-_A

5K

=

5K

FIGURE 14. DIFFERENCE DIVIDED BY SUM (For A + B ~ OV)S

Automatic Gain Control

VOUT

FIGURE 11. VIDEO FADER

Other Applications
As shown above, a function may contain several different
operators at the same time and use only one HA-2556.
Some other possible multi-operator functions are shown in
Figures 12, 13 and 14.

Figure 15 shows the HA-2556. configured in an Automatic
Gain Control or AGC application. The HA-5127 low noise
amplifier provides the gain control signal to the X input. This
control signal sets the peak output voltage of the multiplier to
match the preset reference level. The feedback network
around the HA-5127 provides a response time adjustment.
High frequency changes in the peak are rejected as noise or
the desired signal to be transmitted. These signals do not
indicate a change in the average peak value and therefore
no gain adjustment is needed. Lower frequency changes in
the peak value are given a gain of -1 for feedback to the control input. At DC the circuit is an integrator automatically
compensating for Offset and other constant error terms.
This multiplier has the advantage over other AGC circuits, in
that the Signal bandwidth is not affected by the control signal
gain adjustment.

Of course the HA-2556 is also well suited to standard multiplier applications such as Automatic Gain Control and Voltage Controlled Amplifier.

HA-2556

VOUT

FIGURE 12. DIFFERENCE OF SQUARES
95K

lN914

5kn

"";1f-",--oB

~ O.li1F

Rl and R2 set scale to W/%, other scale factors possible,
ForA OV
FIGURE 15. AUTOMATIC GAIN CONTROL

FIGURE 13. PERCENTAGE DEVIATION

8-94

HA-2556
A multiplier can't do nonintegral roots "exactly", but it can
yield a close approximation. We can approximate nonintegral roots with equations of the form:

HA-2556

Vo

= (1 -

Vo =

(1 -



!;

0.4

0

0.2

FIGURE 16. VOLTAGE CONTROLLED AMPLIFIER
0

Voltage Controlled Amplifier

0

0.2

0.4

0.6

0.8

INPUT (V)

A wide range of gain adjustment is available with the Voltage
Controlled Amplifier configuration shown in Figure 16. Here
the gain of the HFA0002 can be swept from 20VN to a gain
of almost 1000VN with a DC voltage from OV to 5V.

Wave Shaping Circuits
Wave shaping or curve fitting is another class of application
for the analog multiplier. For example, where a nonlinear
sensor requires corrective curve fitting to improve linearity
the HA-2556 can provide non integral powers in the range 1
to 2 or nonintegral roots in the range 0.5 to 1.0 (refer to References). This effect is displayed in Figure 17.

FIGURE 18. COMPARE APPROXIMATION TO NONINTEGRAL
ROOT

This function can be easily built using an HA-2556 and a potentiometer for easy adjustment as shown in Figures 19 and 20. If
a fixed nonintegral power is desired, the circuit shown in Figure
21 eliminates the need for the output buffer amp. These circuits
approximate the function VI~ where M is the desired nonintegral power or root.
HA-2556

Cl

o..J

en

 VIN ~ 5V

8-96

(It

VIN)

2'5

Max Theoretical Error

=0.5%FS

HA-2556
Typical Performance Curves

r---------.---------,

1.S

O.S

iF
~

a:

iF
~

a:
0
a:
a:

0

IE

...

...

a:

O.S
0
-0.5

-o.S
·1

·1

·1.5
-6

-4

·2

0
X INPUT (V)

2

4

6

2

0

·2

4

6

x INPUT (V)

FIGURE 24. X CHANNEL MULTIPLIER ERROR

1.S

·4

-6

FIGURE 25. X CHANNEL MULTIPLIER ERROR

r----------,--------..,
O.S

iF
~

(

O.S

a:

IE

a:
w

0

a:

ia:

0

...

-o.S

·1

-o.S

·1

·l.S

-6

-4

·2

0
V INPUT (V)

2

4

2

0

·2

·4

-6

6

4

6

~If)



900

II:
II:

Il.
Il.

I

I
I
~ ....... GENERATOR
(1Vp_p) (NOTE)

!zw

850

~

XTALAT 2SDC

:::>

= 1, F2

22

~

21

~

20

800

o

50

100

GENERATOR (1Vp.p) (NOTE)

--....

-

~

./

XTALAT 2SDC

18
-100

1S0

I

" '"'
.....

19

750
-100

o

-so

TEMPERATURE (DC)

SO

100

150

TEMPERATURE (DC)

FIGURE 7. SUPPLY CURRENT va'TEMPERATURE

RGURE 8. SUPPLY CURRENT va TEMPERATURE

350

7.S
EN = 0, F1

fiN = SMHz, EN = 0, F1 = 0, F2 = 0, Voo = SV
300

""'

~ 250

ffi

II: 200

8

7

.....

-

~150

Il.
Il.

iil

= 1, fIN = 100kHz, CL = 30pF, Voo = 5V

""-

23

II:
II:

G

,,~

II)

= 1, F1

~ 24

",

u

~

EN
2S

100

so

o

-so

-100

~

~ GEN~RATOR (1Vp_p)(NOTE)

'"
XTALAT25~

ffi

'-

~

6.S

"

~

6

~

S.S

8:
iil

S

= I, F2 = I, "N = 100kHz, VDD = SV

~

~

4.S

r-

50

100

ISO

""'

XTALAT2SoC

4

o

~

GENERATOR (1Vp.p) (NOTE)

-100

o

-SO

SO

"/
1S0

100

TEMPERATURE (DC)

TEMPERATURE (DC)

FIGURE 9. DISABLE SUPPLY CURRENT va TEMPERATURE

CJ

FIGURE 10. DISABLE SUPPLY CURRENT va TEMPERATURE

o

...J

<~
Z_

1400 r-----r-----r-----r-----r-----r----,

3000
EN = 1,

~ = 0, F21= 0, CL =118pF, GE~ERATO~ (1Vp.p) ~NOTE)

2500

I

~

Voo = +IV

~ 2000
w

~

II:

§
u

1S00

~

---

~

8:
iil

1000

~

500

-----

V"

EN = I, F1

1200

V

=0, F2 =1, CL = 18pF, GENERATOR (1Vp.p) (NOTE)

r-----r-----r-----r-----r---~~--~

~ 1000 I - - - + - - - \ - - _ \ - - " , , = - - - t - - - I

I

800

I-----I-----I---~~

G
6001_----I_----~~--I_~~F_----I_--_\
~

~ ---~
VDD = +5V

~

400

I_----~~--c.~--I_--~~__~r---_\

0'--_---'-_ _-'-_ _-'--_---'_ _-'-_---1

o
4

S

6

7

8

9

10

11

o

2

3

4

S

FREQUENCY (MHz)

FREQUENCY (MHz)

RGURE 12. SUPPLY CURRENT va FREQUENCY

FIGURE 11. SUPPLY CURRENT va FREQUENCY

NOTE: Refer to Test Circuit (Figure 1).

8-109

6

<:;)
...JO
=
~

!!!
II:

12

IF

11

GE~ERATOR (l~P.P) (NOTEl ~

11

10 I------r----~I_-----r~~~~----~

./

10

f-;""'"~

9

~

I.!III""'"

7

IF XTAL AT 250 C/

~
IR GENERATOR (1Vp.p) (NOTE)

6

5 f- - 4

·100

-T---'-r---.. . . .,......

r------r------r------r------,-----,
1-----+--

12

..".

:[

9

~

8 1------+------+--;;;JJ~~+_-------1__::_----_l

>=
...

7 r------t--~~~~----~~~-.--~--~

~

5 r------t------1---~~~~

~

~

r-----*'So'c.....--I-----+-----:;~~~---l

6

41------J-:::;;;_~p~--t------t------1

IR XTAL AT 25°C

I
·50

50

~10=0~----.5=0~----~0-------5LO------ll00------l~50

150

100

TEMPERATURE (oC)

TEMPERATURE (OC)

FIGURE 32. RISE/FALL TIME vs TEMPERATURE

FIGURE 31. RISEIFALL TIME vs TEMPERATURE

Voo = 5V, GENERATOR (1Vp.p) (NOTE)

CL = 18pF, GENERATOR (1Vp.p) (NOTE)

30

..

15

14 f----- IF (fiN = 5MHz)
I

13

25

S

.. 12

>=

w 11
:;
>= 10

......
~
!!!

15

!/l

a:

"'

IR (fiN = 5MHz)

~'-

IR (fiN = 100kHz)

"

9
8
7

II:

~

""""'" .........

6

20

30

40

50

60

70

80

90

4

100 110

Voo = 5V, VSS = GND

460

540
j~36.5IlAN

~ 460

g

420

c
z 380
o
~ 340

z

«

I!:

300
260

YIII

~

1000~~~r

~'

10K

son

170

lOOK
1M
FREQUENCY (Hz)

160

iii"w

g

e.

8!/l

l§

~1 50 III
«
,

1

40

380

~

300

fo""'"

100~F

~'

g

50n

i!:

10K

I

II
II
I II

3~1.61!AN

r-I--

c
z 260

10M

ilill
IIIII
TTTr

Fl=O,F2=1

420

o
~ 340

1 80

178°

loon

~
aw

I-

~-.....!

'f

HA721 0

(!)

9etl/)
z!:::

et::J
..... 0
eta:

Voo = 511 Vss = GND

500

Fl = 0, F2 = 0

o

9

FIGURE 34. RISE/FALL TIME vs VDO

620

w 500

8

Voo (+V)

FIGURE 33. RISEIFALL TIME vs CL

~
a

..........

7

4

2

CL

W

§:

(7) FREQ2

CRYSTAL (2)

(6)FREQ 1

CRYSTAL (3)

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 VLOW

Maximum Junction Temperature (Die) ...........•......•. 175°C
Maximum Storage Temperature Range ...•••....-650 C to lSOoC

CAUTION: Stresses above those listed In "Absolute Maximum RaUngs" may cause permanent damege to the daviee. This Is a stress only rating and operation
of the device at these or any other conditions above those Indicated In the operaUonal sections of this specification Is not implied.

Electrical Specifications

vcc = +10V, VEE = -5.2V, VIH = -0.9V, VIL = -1.75V, Unless Otherwise Specified

PARAMETER

TEST CONDmONS

TEMP.
(oC)

MIN

TYP

MAX

UNITS

INPUT CHARACTERISTICS (VHIGH, VLOW)
VHIGH Input Offset Voltage

VOUT=OV

25

-150

-50

+50

mV

VLOW Input Offset Voltage

VOUT=OV

25

-150

-50

+50

mV

VHIGH Input Bias Current

VHIGH = -2.25V to +7.5V

25

-50

110

300

ItA

VLOW Input Bias Current

VLOW = -2.5V to +7.25V

-110

25

-300

VHIGH Voltage Range

25

-2.25

50

ItA

7.5

V

VLOW Voltage Range

25

-2.5

7.25

V

VHIGH to VLOW Differential Voltage Range

25

0.25

10

V

VHIGHIVLOW Interaction at 500mV (Note 11)

25

-

2

4

mV

VHIGHIVLOW Interaction at 250mV (Note 11)

25

-

20

40

mV

Logic Input Voltage Range

25

-2

7

V

Logic Differential Input Voltage

25

0.4

5

V

-

LOGIC INPUT CHARACTERISTICS (DATA, DAiA. HiZ, Hil)

DATAIDAfA Logic Input High Current

VIH = OV, VIL = -2V

25

-50

110

300

ItA

DATAIDAfA Logic Inpu1 Low Current

VIH = OV, VIL = -2V

25

-700

-300

50

ItA

HIZiRiZ Logic Input High Current

VIH = OV, VIL = -2V

25

-50

70

200

ItA

HiZiRiZ Logic Input Low Current

VIH = OV, VIL = -2V

25

-300

-80

50

ItA

VHIGH Voltage Gain

VHIGH = -IV to 6.5V

25

0.95

1

VIV

VLOW Voltage Gain

VLOW = -1.5Vto 6V

25

0.95

1

VIV

VHIGHIVLOW Linearity Error (Note 7)

Fullscale = 5V

25

-0.5

0.5

%

VHIGHIVLOW Linearity Error (Note 8)

Fullscale = 8.5V

25

-0.75

0.75

%

TRANSFER CHARACTERISTICS

VHIGHIVLOW End Point Gain Deviation (Notes 10, 13)

0.5V Steps

25

-2.0

VHIGH End Point Galn Error (Notes 10 and 14)

VOUT = 6.7V to 7.0V

25

-20

VHIGHIVLOW -3dB Bandwidth

200mVp_p

25

-

8-119

100

2.0

%

20

mV

-

MHz

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HFA5251
Electrical Specifications

vee = +10V. VEE = -5.2V. VIH :. -0.9V. VIL = -1.75V. Unless Otherwise Specified - (Continued)

PARAMETER

TEST CONDITIONS

TEMP.
(DC)

MIN

25

MAX

UNITS

0.8

1.5

ns

25

-100

100

ps

Rising Edge Propagation Delay vs Duty Cycle (Notes 12, 17)

25

-120

-20

80

ps

Falling Edge Propagation Delay vs Duty Cycle (Notes 12. 17)

25

-80

20

120

ps

Active to HiZ Delay (Note 17)

25

1.2

1.7

2.2

ns

HiZ to Active Delay (Note 17)

25

2.1

2.6

3.1

ns

-

450

500

ps

890

1000

ps

1.5

1.7

ns

50

150

TYP

SWITCHING CHARACTERISTICS (ZLOAD = 16 Inches of RG-58 Terminated with 500)
Propagation Delay (Notes 2. 17)
Propagation Delay Match (Notes 2.17)

Rising to Falling Edge

TRANSIENT RESPONSE (ZLOAD = 16 inches of RG-58 Terminated with 5pF)
RisefFall Time (20%-80%)

1Vp_p

25

RlsefFall Time (10%-90%)

3Vp_p

25

RisefFall Time (10%-90%) (Note 6)

5Vp_p

25

RisefFall Time Match (Note 6)

25

Minimum Pulse Width (Note 16)

1Vp_p

25

Minimum Pulse Width (Note 16)

3Vp_p

25

Minimum Pulse Width (Note 16)

5Vp_p

25

OvershootfUndershootfPreshoot

3Vp_p

25

ps

1.0

ns

1.2

ns

2.0

ns

25

-

Vee = 10V. VEE = -5.2V

25

-2

At Other Supplies

25

VEE +3.2

-

DC Output Resistance - Active (Note 18)

-2Vto7V

25

45

Output Leakage - HiZ

-2Vt07V

25

Output Capacitance - HiZ
Output Current - Active

5

-

%

10

-

ns

7

V

Vee-3.O

V

47

49

0

-100

±10

100

nA

25

-

5

pF

25

70

100

-

mA

VHIGH

25

-

14

40

mVIV

VLOW

25

-

14

40

mVIV

Total Supply Current

25

90

94

96

mA

Supply Current (Ieel. IEE1)

25

-

74

-

mA

Supply Current (lee2, IEE2)

25

Data Settling Time to 1% (Note 3)
OUTPUT CHARACTERISTICS
Output Voltage Swing (No Load)

POWER SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio (Note 4)

20

-

mA

25

9.8

10

10.2

V

VEE

25

-5.4

-5.2

-'5.0

V

Vee - VEE

25

12

-

15.6

V

Supply Voltage Range (Note 5)

Vee

Supply Voltage Range (Note 5)
Supply Voltage Differential

8-120

HFA5251
Electrical Specifications

vee = +10V, VEE = -S.2V, VIH = -0.9V, VIL = -1.7SV, Unless Otherwise Specified (Continued)
TEMP.

PARAMETER

Power Dissipation

TEST CONDITIONS

No Load At Vee = 10V,
VEE=-S.2V

fC)

MIN

TYP

25

MAX

UNITS

1.46

W

NOTES:
1. Internal Power Dissipation may limit Output Current below 160mA.
2. 3V Step, SO% duty cycle, 200ns period.
3. 3V Step, measured from SO% of input to ±1% of reference value at SOns.
4. VHIGH = 2.6V, VLOW = 2.3V, Vee = 9V to 10V, VEE = -4.2V to -5.2V
S. Minimum/maximum output swing will vary with supply voltage.
6. SV Step, SO% duty cycle, lOOns period.
7. ForVHIGH = OV to SV, ForVLOW = OV to SV, Fullscale = SV, 0.1% = SmV.
8. For VHIGH = -l.SV to 7V, For VLOW = -2.0V to 6.SV, Fullscale = B.SV, 0.1% = B.SmV
9. Shorting the output to a voltage outside the specified range may damage the output.
10. Vee = 9.9V, VEE = -S.1V.
11. VHIGH to VLOW Interaction is measured as the change in VOUT (the active channel) due to a change in the inactive channel. VHIGH
Interaction at 2S0mV is measured as the deviation from 1V as VLOW is changed from OV to 7S0mV (Referred to VOUT)' VLow Interaction
at 2S0mV is measured as the deviation from OV as VHIGH is changed from lV to 2S0mV (Referred to VOUT).
12. OV to 3V Step, 200ns period, Pulse Width is varied from Sns to 19Sns.
13. End Point Gain Deviation is the percent deviation of Gain calculated in O.SV steps at the extremes of output voltage range. For example
in the VHIGH range S.7V to 6.7V, Gain is calculated for VHIGH = S.7V to 6.2V (Note 15) and VHIGH = 6.2V to 6.7V (Note 15) the difference
in gain is calculated and converted to a percentage. The voltage ranges tested are: VHIGH = -l.SV to -O.SV (Note lS) and S.7V to 6.7V
(Note lS), VLOW = -2.0V to -1.0V (Note lS) and S.SVto 6.SV (Note lS).
14. VHIGH End Point Gain Error is the VOUT absolute error from Ideal for a VHIGH change from 6.7V to 7.0V (Note lS).
lS. Input voltages VHIGH and VLOW are corrected for Offset Voltage and 7.SV Full Scale Gain Error.
16. Minimum Pulse Width is measured SO% to SO% of specified amplitude with pulse peak at 90% of amplitude.
17. Test is performed into a son load with a 3V step. Measurement is made from the SO% of input to SO% of output.
1B. Dynamic Output Resistance will be higher (typical 4B.Sn) than DC Output Resistance.

Application Information
The HFA5251 is a pin driver designed for use in automatic test
equipment (ATE) and high speed pulse generators. Pin drivers,
especially those with very high-speed performance, have generally been implemented with discrete transistors (sometimes
GaAs) on a circuit board or in a hybrid. Recent Ie process
improvements, specifically Harris' UHFl process [1), have
enabled the manufacturing of this 800M Hz silicon monolithic
pin driver.
The ultra high speed performance of the HFA5251 is a result
of UHFl process leverages: low parasitic collector-to-substrate capacitance of the bonded wafer, low collector-to-base
parasitic capacitance of the self-aligned base/emitter technology and ultra high fT NPN (8GHz) and PNP (5.5GHz)
poly-silicon transistors.

Functional Block Diagram
The HFA5251 functional block diagram is shown in Figure 1.

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FIGURE 1. BLOCK DIAGRAM

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II..

III

The control inputs, DATA and DATA, determine the output
level. If DATA is at logic "1" and DATA is at logic "0", the output level will be the same as VHIGH. If DATA is at logic "0"
and DATA is at logic "1", the output will be the same as
VLOW The control inputs, HiZ and HiZ, make the output
either active or high-impedance. If HiZ is at logic "1" and HiZ
is at logic "0", the output will be in high impedance mode. If
HiZ is at logic "0" and HiZ is at logic "1", the output will be
enabled. The output impedance in the enabled mode is
trimmed to 50n.

8-121

HFA5251
Circuit Schematic
The Pin Driver circuit consists of a switch, an output buffer,
and two differential control elements as shown in Figure 8.
A two stage approach, separating the switch from the output
buffer, allows the speed and accuracy requirements of the
switch to be de-coupled from the load driving capability of
the buffer.
The patent pending switch circuitry[2] uses cascaded emitter
followers as input buffers and also to switch the input VHIGH
and VLOW to node VSO. Dual differential pairs controlled by
the data timing (DATA and DATA) direct current to select
either the VHIGH or VLOW switch. Matching transistor types
and transdiodes improve linearity and lowers the voltage offset and offset drift. Stacking two emitter-base junctions
allows the VHIGH to VLOW range to be extended to two
BVebo's of the process. The speed of the pin driver is largely
determined by the current flowing through the switch stage
and the collector-base capacitance of the output stage transistors connected to the node VSO.
The output stage consists of cascaded emitter followers constructed in a typical push-pull manner as shown in Figure 2.
However, transdiodes are added to increase the voltage
breakdown characteristics of the output during high impedance mode. HiZ and HiZ control the mode of the output
stage. A trimmed, NiCr resistor is added to provide the 50n
output impedance.

Overall, a symmetry of device types and paths is constructed
to improve slew and delay symmetry. Both the VHIGH to VOUT
path and the VLOW to VOUT path contain three NPN and
three PNP transistors operating at similar collector currents.
Thus the transient response of VHIGH to VLOW and VLOW to
VHIGH are kept symmetrical. Also, a trimmable current reference (not shown) allows the AC parameters to be adjusted to
maintain unit to unit conSistency.

Speed Advantage
Harris Pin Drivers on bonded-wafer technology definitely have
a speed advantage, coming from the low collector-to-substrate capacitance and the high fT of the transistors. In addition, the patent-pending switching stage which fits uniquely to
Harris' UHFl process is another big contributor for the high
speed. This switching circuitry requires low series-resistance
NPN and PNP transdiodes available in UHF1. The rise and
fall times of the pin driver are largely determined by the slew
rate at the node VSO in Figure 2. The dominant mechanism
for the slew rate is the charging/discharging of the collectorbase capacitors of the transistors connected to the node VSO.
The charging/discharging currents are coming from the
switching stage current sources. The fast rise and fall times
are achieved because of the negligible collector-to-substrate
capacitance and the small. base-collector capacitance due to
the self-aligned recessed oxide [1].

SWITCHING STAGE

FIGURE 2. CIRCUIT SCHEMATIC

8-122

OUTPUT STAGE

VCC2

HIZ CONTROL

HFA5251

r--

I
I
2.2V/DIV.

output, the pin driver output will be in high impedance mode
(HiZ) with a logic "1" applied to the "HiZ" pin of the pin driver.
During this high impedance mode the pin driver presents a
capacitance of less than SpF to the DUT. Special care has to
be taken to match the impedance (to SOn) at the pin driver
output to minimize reflections.

7V

J

rj

L

ov

II

-2V

J

411no

sv
3V
1V

The dual level comparator detects the logic levels of the DUT
pin when it acts as an output. The comparator has two threshold level inputs, VCH and VCL. The logic level information of
DUT pin output is sent to the edge/window comparator
through the dual level comparator. The edge/window comparator interprets this information in terms of corresponding transient performance in conjunction with the timing information.
Thus it detects any possible failure transients.

I
2ns/DIV.

431 no

FIGURE 3. OUTPUT RESPONSE WITH VARIOUS VLOW AND
VHIGH CONDITIONS

The DATA/DATA differential stage is not a factor for the
speed if its current sources have enough current not to bottleneck the transient. However it should be noted that the
propagation delay mismatch is determined by this stage.
Sufficient current is allocated to the differential stage current
sources to best match the low-to-high and high-to-Iow transient propagation delays.
Figure 3 shows various output responses, OV to 1V, OV to 3V,
OV to SV, and -2V to 7V (full swing). The load condition is a 16
inch son SMA cable with a SpF capacitor at the end of the
cable. The riselfall time with SVp_p is typically 1.4Sns for the
HFAS2S1. Pin drivers, built out of the same circuit structure as
shown in Figure 2, can be made faster by trimming for a
higher power supply current. Currently the pin driver has
rise/fall times of less than 1ns (10% to 90% of SVp_p) when
ICC is trimmed to 12SmA. Further speed enhancement will be
made if there is a market demand.

Basic ATE System Application
Figure 3 shows a pin driver in a typical per-pin ATE system.
The pin driver works closely with the dual-level comparator
and the active load. When the DUT pin acts as an input waiting for a series of digital signals, the pin driver becomes
active with a logic "0" applied on the HiZ pin and provides the
DUT pin with digital signals. When the DUT pin acts as an
CLOCK,
START

The formatter sends a sequence of digital information to the
pin driver which contains logic information over time. The
active load is enabled when the DUT pin acts as an output. It
simulates the load of the DUT pin by sinking or sourcing programmed current. Finally the sequencer controls the overall
activities of the automatic testing.

Oecoupling Circuit for Oscillation-Free
Operation
To insure the oscillation-free operation in ATE or pulse generator applications, the pin driver needs an appropriate
decoupling circuit on a printed circuit board which consists of
chip capacitors and chip resistors. Figures Sand 6 refer to a
proven decoupling circuit currently working in the lab and a
1X scale film of its associated PC board (metal level).
The control pins, DATA, DATA, HiZ, and HiZ are fed ECl signals through son micro-strip lines terminated with son for
impedance matching since the input impedance at these
pins is much higher tlian SOn. At the end of the micro-strip
lines there is usually a high-speed pulse generator with an
output impedance of son A son micro-strip line is connected to each of the pins, DATA and HiZ through a son chip
resistor to monitor the pulse signals.

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ACTIVE
LOAD

TIMING

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~----------------r-o,,~
EDGE!

WINDOW

.--+-<~~:::::::::t--oVCH

COMPARATORL--+-<~~::::::::~--o

r

DUAL LEVEL COMPARATOR
SEQUENCER

FIGURE 4. TYPICAL ATE SYSTEM

8-123

VCL

HFA5251

References
1. Chris K. Davis et. aI., "UHF1: A High Speed Complementary Bipolar Analog Process on SOl: Bipolar Circuits and
Technology Meeting Proceedings, pp26Q-263, October
1992.
2. Donald K. Whitney Jr., "Symmetrical, High Speed, Voltage Switching Circuit," United States Patent Pending,
Filed November 1991.

Definition of Terms
VOHandVOL
Output High Voltage and Output Low Voltage. VOH is the
voltage at VOUT when the HiZ input is Low and the DATA
input is High. VOL is the voltage at VOUT when HiZ is Low
and DATA is Low. The VOH and VOL levels are set with the
VHIGH and VLOwinputs respectively.

9ftset Voltage
Offset Voltage is the DC error between the voltage placed on
VHIGH or VLOW and the resulting VOH and VOL' VHIGH Offset Voltage Error is obtained by measuring VOH with VHIGH
set to OV and VLOW set to -2.5V to minimize interaction
effects. VLOW Offset Voltage Error is the measurement of
VOL with VLOW set to OV and VHIGH set to +7.5V.

FIGURE 5. DECOUPLING CIRCUIT OF 28 PIN SOIC HFA5251
FOROsaLLATION~EEOPERATION

....'..ifree
.eN!.\.'
•
.~
•

Gain
Gain is defined as the ratio of output voltage change to input
voltage change for a defined range. VHIGH Gain is calculated
with the following equation with VLON fixed at -2.5V

•

VH1GHGAIN =

·~~l'~i~eee
•
..... 1:
•
••••
•

VOH(VHIGH at 6.5V) - VOH(VHIGH at .1V)
7.5

VLOW Gain is calculated in a similar manner.

•

VHIGH is held fixed at 7.5V. These Gain calculations minimize the effects of Interaction and End Point Nonlinearities.

FIGURE 6. 1X FILM OF THE EVALUATION BOARD METAL

Linearity Error
The two input voltage pins, VHIGH and VLON, need to be protected from any capacitively coupled AC noise. Normally this
protection can be achieved by having a low pass filter consisting of a
chip resistor and a 470pF chip capacitor. Without
this protection circuit the pin driver may oscillate due to signals fed back from the output through the PC board ground.

son

The power supply pins, VCC1, VCC2, VEE1, and VEE2,
require decoupling chip capacitors of 470pF, O.1I1F, lOILF.
Having decoupling capacitors close to VCC2 and VEE2 is
essential since large AC current will flow through either
VCC2 or VEE2 during transients.
The output of the pin driver Is usually connected to the
micro-strip line and
device-under-test (OUT) through
coaxial cable which carries the Signal to a high Input impedance OUT pin.

Linearity Error is a measure of output voltage worst case
deviation from a straight line that has been corrected for offset and 7.5V Gain. Linearity Error is given as a percentage
of fullscale and is done in two ranges 5V and 8.5V. Data is
measured at O.5V steps from -1.5V to 7V for VHIGH and -2V
to 6.5V for VLON' The Linearity Error equation is as follows
for 8.5V fullscale:
VOUT
VouT(IDEAL) = GAIN-OFFSET
LlNEARITYERROR = VOUT - VOUT(IDEAL)

son

8-124

B.5

HFA5251
The Linearity Error equation is as follows for 5V fullscale:

End Point Gain Error

LINEARITY ERROR = VOUT-VOUT(IDEAL)
5

End Point Gain Error (EPGE) is the VOUT absolute error in
millivolts for a VHIGH change from 6.7V to 7V. The VHIGH
input is corrected for gain and offset to provide a more accurate VOH level.

Linearity Error is calculated for every data point in the range
and the worst case value is recorded.

EPGE

=VOH (VHIGH at 7V) - VOH (VHIGH at 6.7V) - 0.3

End Point Deviation

VHIGH to VLOW Interaction

End Point Deviation is the percent change of gain in the 1V
range at the extremes of output voltage. Gain is calculated
for each 0.5V step and then compared to the adjacent step
for a percentage change. This specification is designed to
quantify the amount of curvature present at the end pOints of
output swing. VHIGH and VLOW inputs are corrected for gain
and offset to provide more accurate VOH and VOL levels. For
example VOH End Point Deviation is tested in the range 5.7V
to 6.7V as shown below:

VHIGH to VLOW Interaction is the change in VOUT (the active
channel) due to the inactive channel. VHIGH Interaction is
measured as the change in VOH from 1V as VLOW is moved
from OV to 750mV (VLOW is corrected for gain and offset
errors). VLOW Interaction is measured as the change in VOL
from OV as VHIGH is moved from 1V to 250mV (with VHIGH
corrected for gain and offset errors). The minimum recommended difference between VHIGH and VLOW for the
HFA5251 is 250mV.

VOH(VHIGH at 6.7V)- VOH(VHIGH at 6.2V)
0.5

GAIN 6.7 _ 6.2 =
GAIN 6.2 _ 5 .7

=

VOH(VHIGH at 6.2V)- VOH(VHIGH at S.7V)
0.5

END POINT DEVIATION = IGAIN6.7_6.2-GAIN6.2_d x 100

Typical Performance Curves
DISCONTINUrrv REFLECTION

1/

5

:E

~
o

1000

4

:
1

o

800

"9«en

600

400

o

z!::
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....10

200

o
ZLOAD =16 INCHES OF RG-58INTO 1lin
I
I
I ::t
I
I
I
25

o

50

00

ZLOAD = 16 INCHES OF RG-58 INTO 1lin

en

25
TIME (na)

TIME (na)

FIGURE 8. SMALL SIGNAL RESPONSE

FIGURE 7. LARGE SIGNAL RESPONSE

8-125

«Il:

?
DISCON11NUrrv REFLECTION

w

D-

50

HFA5251
Typical Performance Curves

(Continued)

3
\
2

l

1

~

0

15

.1

~

·2

Z

~~--~~--~~--~-H~-­

r-+-~-+~~~+--H

1t"nj --

~

"" VHIGH(ACTIVE)

""-

.... ~
.........

~

........

~

..... ......

" \\

VLOW(ACTIVE) .....

o

·1

5

2.5
TIME (n.)

t--

MINIMUM RECOMMENDED
VH'GH TO VLOW VOLTAGE

t'-.....

....

o

1.04
~ 1.03

S

I

1.02
1.01

-

0.99
0.98

o

0.1

0.2

0.3

3

4

5

6

7

8

1

1.1

FIGURE 10. GAIN ERROR (FULLSCALE = 8.5V)

0.01

1.06

~

2

V'NM

FIGURE 9. MINIMUM PULSE WIDTH

1.05

o

0.4 0.5 0.6
VLOW INPUT M

I

~

..0.01

!;

I

~

~,

J

·0.02

/

..0.03

0.7

0.8

..0.04

0.9

FIGURE 11. VHIGHNLOW INTERACTION, VHIGH ACTIVE
(NOMINAL 1.0V)

~

o

IJ"

-

MINIMUM RECOMMENDED

!.o ...... VHIGH TO VLOW VOLTAGE

I I I I I
0.1

0.2

0.3

0.4 0.5 0.6 0.7
VHIGH INPUT M

0.8

0.9

FIGURE 12. VHIGHNLOW INTERACTION, VLOW ACTIVE
(NOMINAL O.OV)

8·126

HFA5251

Die Characteristics
DIE DIMENSIONS:
2670~m

x

1730~m

x 525~m

METALLIZATION:
Type: Metal 1: Cu (2%) SiAlfTiW
Thickness: Metal 1: skA ±a.4kA
Backside: Gold

PASSIVATION:
Nitride, 4kA ±a.5kA
TRANSISTOR COUNT:
115
SUBSTRATE POTENTIAL:
Floating

Type: Metal 2: Cu (2%) AI
Thickness: Metal 2: 16kA ±a.skA

Metallization Mask Layout
HFA5251

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S-127

HFA5253
800M Hz, Ultra High-Speed Monolithic Pin Driver

November 1996

Features

Description

• High Digital Data Rate •.••••••••••••••.••. 800MHz

The HFAS253 is a very high speed monolithic pin driver
solution for high performance test systems. The device will
switch at high data rates between two input voltage levels
providing variable amplitude pulses. Slew Rate Control pins
provide independent control over positive and negative slew
rate allowing the customer to optimize the pin driver speed
for their application. The output impedance is trimmed to
achieve a precision 50n source for impedance matching.
Two differential ECLITTL compatible inputs control the
operation of the HFA5253, one controlling the VHIGWVLOW
switching and the other controlling the output's high-impedance state. The HFA5253's 800MHz data rate makes it compatible with today's high-speed VLSI test systems and the
+8V to -3V output swing satisfies the most stringent testing
requirements of all common logic families.

• Very Fast Rise/Fall Times ••••.•.•••••••••••• SOOps
• Wide Output Range •.......•.•..••••••. +8V to -3V
• Precise son Output Impedance
• High Impedance, Three-State Output Control
• Slew Rate Control

Applications
• IC Tester Pin Electronics
• Pattern Generators
• Pulse Generators

The HFA5253 is manufactured in Harris' proprietary complementary bipolar UHF-1 process.

• Level ComparatorlTranslator

Ordering Information
TEMP. RANGE
(DC)

PART NUMBER
HFA5253CB
HFA5253Y

Ot050

PACKAGE

PKG.
NO.

20LdPSOP

M20.3A

TJUNCTION <.175 Die Form

N/A

Pinout

Block Diagram
INPUT BUFFER

HFA5253 (PSOP)
TOP VIEW

+SRC

Vee

DATA -I~-"""
DATA -il;..oli--.,

VOUT
VOUT
NC

HIZ

VEE2

FiiZ

VEE2

VEE

~.
VLOW~':' ..

·SRC

INPUT BUFFER

POWER PSOP PACKAGE
(HEAT SLUG SURFACE IS ELECTRICALLY FLOATING)

TRUTH TABLE FOR VOUT
DATA

HIZ

0

1

I

0

VLOW

VHIGH

I

1

HIZ

HIZ

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996

8-128

File Number

4003.2

HFA5253
Pin Descriptions
NAME

FUNCTION

VCC1

Positive Supply. Nominal value is 11.2V ±O.2V. Reducing supply voltage below 11.0V will reduce positive output voltage
swing. The total supply voltage from VCC1 to VEE1 should not exceed 18.0V for normal operation or exceed 19.0V to
prevent damage. Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition,
power supply decoupling chip capacitors of 470pF, O.lI1F and a lOI1F tantalum are recommended. Do not connect the
VCC1 and VCC2 pins together immediately, rather run separate traces until they can be joined ata large by-pass capacitor
(O.lI1F IIl0.0I1F).

VEE1

Negative Supply. Nominal value is -6.4V ±0.2V. A supply voltage more positive than -6.2V will reduce negative output
voltage swing. The total supply voltage from VCC1 to VEE1 should not exceed 18.0V for normal operation or exceed 19.0V
to prevent damage. Harris recommends two wire bonds to this pad to provide the lowest possible impedance. In addition,
power supply decoupling chip capacitors of 470pF, O.lI1F and a 1OI1F tantalum are recommended. Do not connect the
VEE1 and VEE2 pins together immediately, rather run separate traces until they can be joined at a large by-pass capacitor
(O.lI1F IIl0.0I1F).

VCC2

Output Stage Positive Supply. Nominal voltage and cautions are the same as for VCC1. Having decoupling chip capacitors close to VCC2 and VEE2 is essential since large AC current will flow through this pad to the output during transients.
Harris recommends two wire bonds for this pad. Do not connect the VCC1 and VCC2 pins together immediately, rather
run separate traces until they can be joined at a large by-pass capacitor (O.lI1F " 10.0I1F).

VEE2

Output Stage Negative Supply. Nominal voltage and cautions are the same as for VEE1. Having decoupling chip capacitors close to VCC2 and VEE2 is essential since large AC current will flow through this pad to the output during transients.
Harris recommends two wire bends for this pad. Do not connectthe VEE1 and VEE2 pins together immediately, rather run
separate traces until they can be joined at a large by-pass capacitor (O.lI1F IIl0.0I1F).

VHIGH

Input Voltage High is used to setthe output high level VOH' VHIGH is sensitive to capacitively coupled AC noise. Protection
from high frequency noise can be achieved with a low pass filter consisting of a 50Q chip resistor and a 470pF chip capacitor. Without this precaution the pin driver may oscillate due to feedback from the output through the PC board ground.

VLQW

Input Voltage low is used to set the output low level VOL' VLQW is sensitive to capacitively coupled AC noise. Protection
from high frequency noise can be achieved with a low pass filter consisting of a 50Q chip resistor and a 470pF chip capacitor. Without this precaution the pin driver may oscillate due to feedback from the output through the PC board ground.

VOUT

Driver Output. The output impedance has been laser trimmed to match a 50Q transmission line ±2Q. Custom output impedance trimming is available (contact sales office for details) to provide the best match possible to your 50Q system.

DATA, DATA

Differential Digital Inputs used to switch VOUT to the VHIGH or VLQW level. Harris recommends this input pair be driven
by complementary ECl signals to provide optimal switching speeds and timing accuracy. However a large Common
Mode and Differential Voltage Range is provided to accommodate a variety of signals including single ended TTL and
CMOS. When using single ended signals the other input must be tied to an appropriate threshold voltage. .

HIZ,HIZ

Differential Digital Inputs used to switch VOUT from an Active to a High Impedance State. Harris recommends that this
input pair be driven by complementary ECl signals to provide optimal switching speeds and timing accuracy. However
a large Common Mode and Differential Voltage Range is provided to accommodate a variety of signals including single
ended TTL and CMOS. When using single ended signals the other input must be tied to an appropriate threshold voltage.

e"

9

c:t~
Z_
c:t:;)

..JO

c:tcr

00
w

c..

+SRC

The Positive Slew Rate Control Pin adjusts the rising edge slew rate with an external current ISTEAl' ISTEAl draws current
(OmA to 10mA) from an internal current source limiting the rate of change of the high impedance node. Typically an external resistor to GND is sufficient to set the slew rate at a desired level. leaving the +SRC Pin open will give the highest
speed performance. The external current ISTEAl for a resistor RSTEAl connected from +SRC to GND may be calculated
by: ISTEAl = (VCC - O.35)IRSTEAl·

-SRC

The Negative Slew Rate Control Pin adjusts the falling edge slew rate with an external current ISTEAl' ISTEAl supplies
current (OmA to 10mA) to an internal current source limiting the amount of current being drawn from the circuit and thus
limiting the rate of change of the high impedance node. Typically an external resistor to GND is sufficient to set the slew
rate at a desired level. leaving the -SRC Pin open will give the highest speed performance. The external current
ISTEAl for a resistor RSTEAl connected from -SRC to GND may be calculated by:
ISTEAl = (VEE + 0.35)/RSTEAl·

8-129

In

HFA5253
Absolute Maximum Ratings

Thermal Information

Supply Voltage . . • . . . . • • . • . • • • . • • • • • • • • • . • • . • • • . • • • • . 19V
Differential Input Voltage (DATA and HIZ) •.••••..•••••.•••• 5V
Output Current Continuous (Note 1)••.•••..•....••••••• 160mA
Input Voltage (Any pin except as specified) •••••.•••• Vee to VEE
VOUT Voltage (Nota 3) .......••••..•••.••....•••.. 9V to-4V
VHIGH Voltage .......••.....••••••.•.••••..•••• VCC to -4V

Thermal Resistance (Typical, Note 2)
9JA (0C/W) 9JC fclW)
20 Ld PSOP Package.. .. .. .. .. .. •
49
2
(9JC Measured At Copper Slug Top Center with Infinite Heat Sink)
Maximum Junction Temperature (Ole) .••...•.••••..•.••.• 175°C
Maximum Junction Temperature (Plastic Package) .•.••..• 150°C
Maximum Storage Temperature Range ..••••.•.. -S50C to 150°C
Maximum Lead Temperature (Soldering 10s) ....•.•.••..• 300°C
(PSOP - Lead Tips Only)

Operating Conditions
VLOW Voltage .... '.............................. 9V to VEE
VHIGH to VLOW Voltage .•....•••••.• 11V to OV (VHIGH > VLOW)
Slew Rate Control Current (+SRC, -SRC) •..•••..••••..•• 12mA
Temperature Range ...............•••...••.••.•0oC to 50°C

CAUTION: Stresses above those "steel In "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only fating and opefation
of the device at these or any other oondiliOns above those indicated In the opefanonal sectfons of this specification Is not Imp/led.

NOTES:
1. Intemal Power DIssipation may limit Output Current below 16OmA.
2. 9JA is measured with the component mountad on an evaluation PC board in free air.
3. Shorting the output to a voltage outside the specified range may damage the output.

Electrical Specifications

vcc = +11.2V; VEE = -S.4V; VIH = -0.9V; VIL = -1.75V; +SRC and -8RCare Not Connected Unless
Otherwise Specified

PARAMETER
INPUT CHARACTERISTICS (VHIGH, VLOW)
VHIGH Input Offset Voltage
VLOW Input Offset Voltage
VHIGH Input Bias Current
VLOW Input Bias Current
VHIGH Voltage Range
VLOW Voltage Range
VHIGH to VLOW Differential Voltage Range
VHIGWVLOW Interaction (Notas 5,17)
LOGIC INPUT CHARACTERISTICS (DATA, r
Logic Input Voltage Range
Logic Differential Input Voltage
DAT~A Logic Input High Current
DATA/DATA Logic Input Low Current
Hlzrl-lgLogic Input High Current
HIZfHIZ Logic Input Low Current
TRANSFER CHARACTERISTICS
VHIGH Voltage Gain
VLOW Voltage Gain
VHIGWVLOW Linearity Error

TEST CONDITIONS

VHIGH = -3.25V to +9.5V
VLOW = -3.5V to +8.25V

VHIGH~VLOW

At500mV
At 250mV
AlA, HIZ, HlZ)

VIH = OV, VIL = -2V
VIH = OV, VIL = -2V
VIH = OV, VIL = -2V
VIH - OV, VIL - -2V
VHIGH = -W to S.5V
VLOW=-1.5VtoSV
Fullscale = 5V, Note S
Fullscale = 10.5V, Note 7
200mVp_p

(NOTE 4)
TEST TEMP_
LEVEL
fC) MIN

8-130

MAX UNITS

-50
-50
110
-110

+50
+50
400
50
8.5
8.5
9.5
4
40

A
A
A
A
A
A
A
A
A

25
25
25
25
25
25
25
25
25

B
B
A
A
A
A

25
25
25
25
25
25

A
A
A
A
B
B
C
C

25
25
25
25
25
25
25
25

0.95
0.95
.0.2
-0.4

0.97
0.97

-

100

VHIGWVLOW -3dB Bandwidth
Typical Slew Rate Control Range
ISTEAL = OmA to 10mA, 5V Step
+SRC Pin Voltage
-SRC Pin Voltage
SWITCHING CHARACTERISTICS (lLOAD = 16 inches of RG-58 Terminated with 500)
Propagation Delay (Notes 8, 10)
B
Propagation Delay Match (Rising to FaiUng Edge,
B
Notes 8,10)
Rising Edge Propagation DelaY vs Duty Cycle
B
(Notes 9,10)

-150
-150
-50
-400
-3.5
-3.5
0

TYP

-3
0.4
-50 '
-700
-50
-400

-

2
20

110
-300
70
-80

8
5
700
50
400
50

IJ.A
IJ.A
V
V
V
mV
mV
V
V

IJ.A
IJ.A
IJ.A
IJ.A

2.8

-

Vee- O.35
VEE + 0.35

-

VN
VN
%
%
MHz
Vlns
V
V

25
25

1
-100

-

2
100

ns
ps

25

-120

-20

80

ps

1.0

-

1
1
0.2
0.4

mV
mV

-

HFA5253
Electrical Specifications

vee = +11.2V; VEE = -6.4V; VIH = -0.9V; VIL = -1.75V; +SRC and -SRC are Not Connected Unless
Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

Falling Edge Propagation Delay vs Duty Cycle
(Notes 9, 10)
Active to HIZ Delay (Note 10)
HIZ to Active Delay (Note 10)

(NOTE 4)
TEST
TEMP.
LEVEL
MIN
fC)
B
25
-BO

TYP

MAX UNITS

20

120

ps

B
B

25

1.5

2.0

2.5

ns

25

2.8

3.3

3.8

ns

B
B
B
B
B
B
B

25

350

450

500

25

700

890

1000

ps
ps

25

1.1

1.3

1.7

ns

25
25

100

-

ps
ns

25

-

-

TRANSIENT RESPONSE (ZLQAD = 16 inches of RG-58 Terminated with 5pF)

Rise/Fall Time

1Vp_p, 20% - 800k (Note 11)
3Vp_p, 100/0-90% (Note 11)
5Vp_p, 100/0 - 90% (Note 12)

Rise/Fall Time Match (Note 12)
Minimum Pulse Width (Note 13)

lVp_p
3Vp_p
5Vp_p

25
25

OvershootlUndershootlPreshoot

3Vp_p

Data Settling Time (Note 14)

Tol%

B
B

Output Voltage Swing

No Load at Vee = llV, VEE = -6.2V

A

25

-3

Output Amplitude Voltage
DC Output Resistance (Note 15)

VOH-VOL
-3Vto 8V

A
A

25
25

0.25
45

Output Leakage - HIZ

-3Vto 8V

A

25
25

-100

25

1.0
1.2
2.0
5
10

ns
ns
%
ns

OUTPUT CHARACTERISTICS

Output Capacitance - HIZ

C

-

8

V

47

9.0
49

V
0

-

100

nA
pF

-

Output Current - Active

A

25

80

5
100

-

mA

Output Short Circuit Range (Note 3)
POWER SUPPLY CHARACTERISTICS (VHIGH = 5V Active, No Load)

A

25

-4.0

-

9.0

V

VHIGH Power Supply Rejection Ratio (Note 16)

A

25

40

A

25

-

14

VLCYN Power Supply Rejection Ratio (Note 16)

14

40

mVN
mVN

Total Supply Current

A

25

90

96

98

mA

leel/IEEl Supply Current

B
B
A
A
A
A

25

-

74

-

mA

lee2/IEE2 Supply Current
Supply Voltage Range

Vee
VEE

Power Dissipation

Vee-VEE
Vee = 11.2V, VEE = -6.4V, No Load

11.0

22
11.2

11.4

V

25

-6.6

-6.4

-6.2

V

25

17.2

V

-

-

18.0

25

1.72

W

25
25

mA

NOTES:
4. Test Level: A = 100% production tested, B = Typical or limit based on lab characterization of a limited number of lots, C = Design Information, goal or condition.
5. VHIGH to VLCYN Interaction is measured as the change in Your (the active channel) due to a change in the inactive channel. VHIGH Interaction at 250mV is measured as the deviation from 1V as VLQW is changed from OV to 750mV (Referred to VOUT). VLQW Interaction
at 250mV is measured as the deviation from OV as VHIGH is changed from 1V to 250mV (Referred to VOUT).
6. ForVHIGH = OVto 5V, for VLQW = OV to 5V, Fullscale = 5V, 0.1% = 5mV. Output Amplitude (VHIGH - VLQW) = lVp_p'
7. ForVHIGH = -2.5Vto 8V, for VLQW= -3.0V to 7.5V, Fullscale = 10.5V, 0.1% = 10.5mV. Output Amplitude (VHIGH - VLQW) = 1Vp_p.
B. 3V Step, 50% duty cycle, 200ns period.
9. OV to 3V Step, 200ns period, Pulse Width is varied from 5ns to 195ns.
10. Test is performed into a 500 load with a 3V step. Measurement is made from the 50% of the input to 50% of output.
11. Limit based on calculation. Not 100% tested.
12. 5V Step, 50% duty cycle, lOOns period. 100% Tested.
13. Minimum Pulse Width is measured 50% to 50% of specified amplitude with pulse peak at 1000/0 of amplitude.
14. 3V Step, measured from 500/0 of input to ±1 % of reference value at 50ns.
15. Dynamic Output Resistance will be higher (typ 48.50) than DC Output Resistance. DC Output Resistance is measured at OV with lOUT
set from OmA to 40mA.
lS. VHIGH = 2.6V, VLQW = 2.3V, Vee = 10.2Vto 11.2V, VEE = -5.4V to -S.4V.
17. Input voltages VHIGH and VLQW are corrected for Offset Voltage and Gain Error.

8-131

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HFA5253
Functional Block Diagram
The HFA5253 functional block diagram is shown in on the first
page of this data sheet.
The control inputs, DATA and DATA, determines the output
level. If DATA is at logic "1" and DATA is at logic "0", the output
level will be the same as VHIGH. If DATA is at logic "CY' and DATA
is at logic "1", the output will be the same as VLOW The control
inputs, HIZ and HIZ, cause the output to become either active
or high-impedance. If HIZ is at logic "t" and HIZ is at logic "CY',
the output will be in high impedance mode. If HIZ is at logic "CY'
and HIZ is at logic "1", the output will be enabled. The output
impedance in the enabled mode is trimmed to 500.

Circuit Schematic
The Pin Driver circuit cQnsists of a switch, an output buffer,
and two differential control elements as shown in the circuit
Schematic Diagram.
A two stage approach, separating the switch from the output
buffer, allows the speed and accuracy requirements of the
switch to be de-coupled from the load driving capability of
the buffer.
The patented switch circuitry [3] uses cascaded emitter followers as input buffers and also to switch the input VHIGH
and VLOW to node VSO. Dual differential pairs controlled by
the data timing (DATA and DATA) direct current to select

either the VHIGH or VLOW switch. Matching transistor types
and transdiodes improve linearity and lowers the voltage offset and offset drift. Stacking two emitter-base junctions
allows the VHIGH to VLOW range to be extended to two
Emitter - Base breakdown voltages of the process. The
speed of the pin driver is largely determined by the current
flowing through the switch stage and the collector-base
capacitance of the output stage transistors connected to the
node. VSO. The Slew Rate Control. Pins, +SRC and -SRC,
allow the user to control the amount of current available in
the VHIGH and VLOtN switch, respectively and thus the slew
rate of node VSO.
The output stage consists of cascaded emitter followers constructed in a typical push-pull manner as shown in the
Schmatic Diagram. However, transdiodes are added to
increase the voltage breakdown characteristics of the output
during high impedance mode. HIZ and HIZ control the mode
of the output stage. A trimmed, NiCr resistor is added to provide the 500 output Impedance.
Overall, a symmetry of device types and paths is constructed
to improve slew and delay symmetry. Both the VHIGH to VOUT
path and the VLOW to VOUT path contain three NPN and
three PNP transistors operating at similar collector currents.
Thus the transient response of VHIGH to VLOtN and VLOW to
VHIGH are kept symmetrical. Also, a trimmable current reference (not shown) allows the AC parameters to be adjusted to
maintain unit to unit conSistency.

Schematic Diagram

8-132

HFA5253

Application Information

(IDEAL)
OUT
10.5
The Linearity Error equation is as follows for SV fullscale:
Linearity Error =

The HFAS2S3 is a pin driver designed for use in automatic
test equipment (ATE) and high speed pulse generators. Pin
drivers, especially those with very high-speed performance,
have generally been implemented with discrete transistors
(sometimes GaAs) on a circuit board or in a hybrid. Recent
IC process improvements, specifically Harris' UHFl process
[2], have enabled the manufacturing of the SOOMHz and
800M Hz silicon monolithic pin drivers, HFAS250, HFAS2S1
and now the HFAS253.

Linearity Error =

v

OUT

-v

VOUT-VOUT(lDEAL)
5

Linearity Error is calculated for every data pOint in the range
and the worst case value is recorded.

VHIGH to VLOW Interaction

Definition of Terms

VHIGH to VLON Interaction is the change in VOUT (the active
channel) due to the inactive channel. VHIGH Interaction is measured as the change in VOH from 1V as VLON is moved from
OV to 750mV (VLON is corrected for gain and offset errors).
VLON Interaction is measured as the change in VOL from OV
as VHIGH is moved from 1V to 2S0mV (with VHIGH corrected
for gain and offset errors). The minimum recommended difference between VHIGH and VLOW for the HFAS253 is 250mV.

VOH and VOL

Speed Advantage

The ultra high speed performance of the HFAS253 is a result
of UHFl process leverages: low parasitiC collector-to-substrate capacitance of the bonded wafer, low collector-to-base
parasitic capacitance of the self-aligned base/emitter technology and ultra high fT NPN (8GHz) and PNP (S.SGHz)
poly-silicon transistors.

Output High Voltage and Output Low Voltage. VOH is the
voltage at VOUT when the HIZ input is low and the DATA
input is high. VOL is the voltage at VOUT when HIZ is low
and DATA is low. The VOH and VOL levels are set with the
VHIGH and VLOW inputs respectively.

Offset Voltage
Offset Voltage is the DC error between the voltage placed on
VHIGH or VLOW and the resulting VOH and VOL· VHIGH Offset Voltage Error is obtained by measuring VOH with VHIGH
set to OV and VLOW set to -2.SV to minimize interaction
effects. VLOW Offset Voltage Error is the measurement of
VOL with VLOW set to OV and VHIGH set to +7.SV.
Gain
Gain is defined as the ratio of output voltage change to input
voltage change for a defined range. VHIGH Gain is calculated with the following equation with VLOW fixed at -2.SV:
VH1GHGAIN =

VOH(VHIGHat 6.5V)- VOH(VHIGHat -lV)
7.5

VLOW Gain is calculated in a similar manner.
VLQW GAIN

=

VOL0I LOWat 6V)- VOL0I LOWat -1.5V)
7.5

Linearity Error
Linearity Error is a measure of output voltage worst case
deviation from a straight line that has been corrected for offset and 7.SV Gain. Linearity Error is given as a percentage
of fullscale and is done in two ranges, SV and 10.SV. DATA is
measure at O.SV steps from -2.SV to 8V for VHIGH and -3V
to 7.SV for VLOW The Linearity Error equation is as follows
for 10.SV fullscale:

= V1NxGaln+Offset

The DATAIDATA differential stage is not a factor for the speed if
its current sources have enough current not to bottleneck the
transient. However it should be noted that the propagation
delay mismatch is determined by this stage. Sufficient current is
allocated to the differential stage current sources to best match
the low-to-high and high-to-Iow transient propagation delays.

son

VHIGH is held fixed at 7.SV. These Gain calculations minimize
the effects of Interaction and End Point Nonlinearities.

VOUT(IDEAL)

Harris Pin Drivers on bonded-wafer technology definitely
have a speed advantage, coming from the low collector-tosubstrate capacitance and the high fT of the transistors. In
addition, the patented SWitching stage which fits uniquely to
Harris' UHFl process is another big contributor for the high
speed. This switching circuitry requires low series-resistance
NPN and PNP transdiodes available in UHF1. The rise and
fall times of the pin driver are largely determined by the slew
rate at the node VSO in the Schematic. The dominant mechanism for the slew rate is the charging/discharging of the collector-base capacitors of the transistors connected to the
node VSO. The charging/discharging currents are coming
from the SWitching stage current sources. The fast rise and
fall times are achieved because of the negligible collector-tosubstrate capacitance and the small base-collector capacitance due to the self-aligned recessed oxide [2].

SMA cable with a
The specified load condition is a 16 inch
SpF capacitor at the end of the cable. This load simulates a typical ATE environment for a OUT (Device Under Test) with high
impedance (>1 kn) digital inputs. The risellall time for HFA5253
with SVp_p is typically 1.3ns. Pin drivers, built out of the same
circuit structure as shown in the Schematic, can be made faster
by trimming for a higher power supply current. Currently the pin
driver has risellall times of less than 1ns (10% to 90"10 of SVp_p)
when ICC is trimmed to 12SmA. Further speed enhancement
will be made if there is a market demand.

Basic ATE System Application
Figure 1 shows a pin driver in a typical per-pin ATE system. The
pin driver works closely with the Dual-Level Comparator and
the Active Load. When the OUT pin acts as an input waiting for

8-133

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HFA5253
a series of digital signals, the pin driver becomes active with a
logic "0" applied on the HIZ pin and provides the DUT pin with
digital signals. When the DUT pin acts as an output. the pin
driver output wi" be in high impedance mode (HIZ) with a logic
"1" applied to the "HIZ" pin. During this high impedance mode
the pin driver presents a capacitance of less than 5pF to the
DUT. Special care has to be taken to match the impedance (to
500) at the pin driver output to minimize reflections.

nected to each of the pins. DATA and HIZ through a 500 chip
resistor to monitor the pulse signals.
PARTS LIST

The Dual-level Comparator detects the logic levels of the
DUT pin when it acts as an output. The comparator has two
threshold level inputs. VCH and VCl' The logic level information of the DUT pin output is sent to the edgelwindow comparator through the Dual-level Comparator. The edgelwindow
comparator interprets this information in terms of corresponding transient performance in conjunction with the timing information. Thus it detects any possible failure transients.
The formatter sends a sequence of digital information to the
pin driver which contains logic information over time. The
Active Load is enabled when the DUT pin acts as an output.
It simulates the load of the DUT pin by sinking or sourcing
programmed current. Finally the sequencer controls the
overall activities of the automatic testing.

aTY

VALUE

6

470pF

COMPONENT
Chip cap: 0805

4

0.111F

Chip Cap: 0805

2

10l1F

Tant.

8

500

Chip Res: 0805

2

1000

7

SMA Jacks

Wide Body

Chip Res: 0805

HFA5253

1

20 lead PSOP

4

4-40

1" Standoff

4

4-40

1/4" Screws

2

Twisted Wire Assemblies with 4 Wires Each:
One for Vee. VHIGH. +SRC, GND; and 1 for Vee,
VLQW. -SRC, GND.

Decoupling Circuit for Oscillation-Free
Operation

The input pins. VHIGH. VlOW. +SRC. and -SRC need to be
protected from any capacitively coupled AC noise. Normally
this protection can be achieved by having a low pass filter
consisting of a 500 chip resistor and a chip capacitor. 470pF
for VHIGWVLOW and 0.11lF for +SRC/-SRC. Without this
protection circuit the pin driver may oscillate due to signals
fed back from the output through the PC board ground.

To ensure oscillation-free operation in ATE or pulse generator applications. the pin driver needs an appropriate decoupiing circuit on a printed circuit board which consists of chip
capacitors and chip resistors. Figures 2. 3. and 4 refer to a
proven decoupling circuit currently working in the lab and a
1X scale film of its associated PC board (metal level). Do not
connect the VCC1 and VCC2 pins or the VEE1 and VEE2 pins
together immediately. rather run separate traces until they can
be joined at a large by-pass capacitor (0.1IlF" 10.01lF).
The control pins. DATA. DATA, HIZ. and HiZ are fed ECl signals through 500 micro-strip lines terminated with 500 for
impedance matching since the input impedance at these
pins is much higher than 500. At the end of the micro-strip
lines there is usually a high-speed pulse generator with an
output impedance of 500. A 500 micro-strip line is con-

EDGE!

WINDOW
SEQUENCER

The power supply pins, VCC1. VCC2' VEE1. and VEE2.
require decoupling chip capacitors of 470pF, 0.11lF, 10IlF.
Having decoupling capacitors close to VCC2 and VEE2 is
essential since large AC current will flow through either
VCC2 or VEE2 during transients.
The output of the pin driver is usually connected to the deviceunder-test (DUl) through 500 micro-strip line and coaxial cable
which carries the signal to a high input impedance DUT pin.

I--~J:===t--o VCH

COMP.ARAlORL-~~:l::::::::~--o

r

D\lAL lEVEL COMP.ARATOR

FIGURE 1. TYPICAL ATE SYSTEM

8-134

VCL

HFA5253
(+1UY)

vee

VHIGH

GND

+SRC

+

VOUT

HIZ

HIZ
50

VPOPF
GND

R1Z-SCOPE

VLOW -SRC

FIGURE 2. DECOUPUNG CIRCUIT SCHEMATIC

o

o

.. ·1·· :
..• •••
. ..... --.
--.
••• • •
.~
• ••

•

DATA

•

•

••

• •

•

:! i- i!
=- 10=
.. rt:Si
•

• •
•••
• ••
•

RIZ

• +SRC

Vee

CJ

•

o

• • VOUT

.. ~ i;va

HIZ • •

•

GND

..f.:- -.......• •

I , / . &~'•.

• •

•

•

~VH

•

• ••

.~~.ril~.
,
o

~C:E

•••

•

o

HFA5253
EVAL BOARD
HARRIS SEMICONDUCTOR
•

~

• •
IF' ="_.
.~!.w::;.
- I -

m
W

0

•

- 'II.

..JI/)


...Ie)

..JO
C

The ICL8038 waveform generator is a monolithic integrated
circuit capable of producing high accuracy sine, square, triangular, sawtooth and pulse waveforms with a minimum of
external components. The frequency (or repetition rate) can
be selected externally from 0.001 Hz to more than 300kHz
using either resistors or capacitors, and frequency modulation and sweeping can be accomplished with an external
voltage. The ICL8038 is fabricated with advanced monolithic
technology, using Schottky barrier diodes and thin film resistors, and the output is stable over a wide range of temperature and supply variations. These devices may be interfaced
with phase locked loop circuitry to reduce temperature drift
to less than 250pprnPC.

• Low Distortion ...........•. 1% (Sine Wave Output)
• High Linearity ....•.... 0.1 % (Triangle Wave Output)
• Wide Frequency Range. . . . • . . • . • 0.001 Hz to 300kHz
• Variable Duty Cycle •••.••..•....•.•••.. 2% to 98%
• High Level Outputs ••••••..••.•.•.••... TTL to 28V
• Simultaneous Sine, Square, and Triangle Wave
Outputs
• Easy to Use - Just a Handful of External Components
Required

Ordering Information
STABILITY

TEMP. RANGE (DC)

ICL8038CCPD

250ppmPC (Typ)

Oto 70

14 Ld PDIP

E14.3

ICL8038CCJD

250ppmPC (Typ)

Oto 70

14Ld CERDIP

F14.3

ICL803BBCJD

1BOppmPC (Typ)

01070

14Ld CERDIP

F14.3

ICLB038ACJD

120ppmPC (Typ)

Ot070

14LdCERDIP

F14.3

ICL8038BMJD (Note)

350ppmPC (Max)

-55 to 125

14LdCERDIP

F14.3

ICL803BAMJD (Note)

250ppmPC (Max)

-55 to 125

14Ld CERDIP

F14.3

PART NUMBER

PACKAGE

PKG.NO.

NOTE: Add 1883B to part number if 883 processing IS required.

Functional Diagram

Pinout
ICL8038
(PDIP, CERDIP)
TOP VIEW

CURRENT
SOURCE

CJ

o
< ....
Z_

.J",

r------------------------------------------------------oV+
6

<::::I
 SmA), transistor betas and saturation voltages will contribute increasingly larger errors. Optimum performance will,
therefore, be obtained with charging currents of lOIlA to
1mAo If pins 7 and 8 are shorted together, the magnitude of
the charging current due to RA can be calculated from:

1= Rl x(V+ -Vol x....!.. = O.22(V+-V-)
(R 1 + R2 )
RA
RA

nn
R
8

ICLB038

3

T

FM

81K

'-----....---....---00 v-

OR GND

FIGURE SA. CONNECTIONS FOR FREQUENCY MODULATION

Rl and R2 are shown in the Detailed Schematic.

9---1----~--~~-_1--ov+

A similar calculation holds for Re.
The capacitor value should be chosen at the upper end of its
possible range.

nn

Waveform Out Level Control and Power Supplies
The waveform generator can be operated either from a single power supply (10V to 30V) or a dual power supply (±5V
to ±15V). With a single power supply the average levels of
the triangle and sine wave are at exactly one-half of the supply voltage, while the square wave alternates between V+
and ground. A split power supply has the advantage that all
waveforms move symmetrically about ground.
The square, wave output is not committed. A load resistor
can be connected to a di~erent power supply, as long as the
applied voltage remains within the breakdown capability of
the waveform generator (30V). In this way, the square wave

8-158

8

ICLB038

3

'-----""---""---00 v-

OR GND

FIGURE SB. CONNECTIONS FOR FREQUENCY SWEEP
FIGURES.

ICL8038

Typical Applications
The sine wave output has a relatively high output impedance
(1Iill Typ). The circuit of Figure 6 provides buffering, gain
and amplitude adjustment. A simple op amp follower could
also be used.
r------.------~----------~~---ov+

r---------------~~AMPLrruDE

To obtain a 1000:1 Sweep Range on the ICL8038 the voltage across external resistors RA and RS must decrease to
nearly zero. This requires that the highest voltage on control
Pin 8 exceed the voltage at the top of RA and RS by a few
hundred mV. The Circuit of Figure 8 achieves this by using a
diode to lower the effective supply voltage on the ICL8038.
The large resistor on pin 5 helps reduce duty cycle variations
with sweep.
The linearity of input sweep voltage versus output frequency
can be significantly improved by using an op amp as shown
in Figure 9.
r--.----------~--------------~~+lOV

lN457
10

11

DUTY CYCLE

c

15K

lK
4.7K

~----------~----------~----~~

4.7K

FIGURE 6. SINE WAVE OUTPUT BUFFER AMPLIFIERS
5

With a dual supply voHage the external capacitor on Pin 10 can
be shorted to ground to halt the ICL8038 oscillation. Figure 7
shows a FET switch, diode ANDed with an input strobe signal
to allow the output to always start on the same slope.

10K

FREQ.~ ...---+-t 8

ICL6038

10

r------.-----------------.------_o v+

Re

20K

4

11

6 9

nn

3

12 2
DISTORTION

lOOK
L-__.....____......____-4~----......------~

9t-----....

-lOV

GURE 8. VARIABLE AUDIO OSCILLATOR, 20Hz TO 20kHzY

lN914

"o

11

-'rJ)

lN914

c

~t=

I~-.~~~STROBE

et:l
-,0
eta:

lOOK
OFF

=

., r- +15V (+10V)
LI

-15V (-lOV)

00
w
a..

ON

rJ)

FIGURE 7. STROBE TONE BURST GENERATOR

8-159

ICL8038

~

R1

-

)

DUTY
CYCLE
FREQUENCY)
ADJUST

FMBIAS

SQUARE
WAVE
OUT

INPUT

-

VCO
IN
PHASE
DETECTOR

--

DEMODULATED
FM

AMPLIFIER

1

r
TRIANGLE

OUT
6

5

7 4

3

f-o '\Iv
SINEWAVE
OUT

ICL8038

9

2

f-o '\I\J
SINE WAVE

8 10

R2

~l

LOW PASS
FILTER

12 1

11

1

TIMING
TCAP.

)

f-o ADJ.

". SINEWAVE
ADJ.
V-/GND

FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP

HIGH FREQUENCY _~_----.
SYMMETRY
101Ul
1N753A
(6.2V)

-

1MG

11Ul

1,OOOpF

4

5

6 9

nn

+15V
1kn

>-""""'/>k-....-I8

10kn
OFFSET

1001Ul

4.71Ul

ICL8038
FUNCTION GENERATOR

10

LOW FREQUENCY
SYMMETRY
. - - - - - - - - , SINE WAVE
OUTPUT

11
100kn
3,900pF

SINE WAVE
DISTORTION

L---~~----~~-----1~----------~------------~~-o-15V

FIGURE 10. LINEAR VOLTAGE CONTROLLED OSCILLATOR

Use in Phase Locked Loops
Its high frequency stability makes the ICLB03B an ideal
building block for a phase locked loop as shown in Figure 10.
In this application the remaining functional blocks, the phase
detector and the amplifier, can be formed by a number of
available ICs (e.g., MC4344, NE562, HA2BOO, HA2B20).
In order to match these building blocks to each other, two
steps must be taken. First, two different supply voltages are
used and the square wave output is returned to the supply of
the phase detector. This assures that the VCO input voltage
will not exceed the capabilities of the phase detector. If a
smaller VCO signal is required, a simple resistive voltage
divider is connected between pin 9 of the waveform generator .and the VCO input of the phase detector.

Second, the DC output level of the amplifier must be made
compatible to the DC level required at the FM input of the
waveform generator (pin B, O.BV+). The simplest solution here
is to provide a voltage divider to V+ (R1' R2 as shown) if the
amplifier has a lower output level, or to ground if its level is
higher. The divider can be made part of the low-pass filter.
This application not only provides for a free-running frequency with very low temperature drift, but is also has the
unique feature of producing a large reconstituted sinewave
signal with a frequency identical to that at the input.
For further information, see Harris Application Note AN013,
"Everything You Always Wanted to Know About the
ICLB03B".

B-160

ICL8038
Definition of Terms
Supply Voltage (VSUPPLV). The total supply voltage from
V+ to V-.

Output Amplitude. The peak-to-peak signal amplitude
appearing at the outputs.

Supply Current. The supply current required from the
power supply to operate the device, excluding load currents
and the currents through RA and Rs.

Saturation Voltage. The output voltage at the collector of
Q23 when this transistor is turned on. It is measured for a
sink current of 2mA.

Frequency Range. The frequency range at the square wave
output through which circuit operation is guaranteed.

Rise and Fall Times. The time required for the square wave
output to change from 10% to 90%, or 90% to 10%, of its
final value.

Sweep FM Range. The ratio of maximum frequency to minimum frequency which can be obtained by applying a sweep
voltage to pin 8. For correct operation, the sweep voltage
should be within the range:
(2/3 VSUPPLV + 2V) < VSWEEP < VSUPPLV
FM Linearity. The percentage deviation from the best fit
straight line on the control voltage versus output frequency
curve.

Triangle Waveform Linearity. The percentage deviation
from the best fit straight line on the riSing and falling triangle
waveform.
Total Harmonic Distortion. The total harmonic distortion at
the sine wave output.

Typical Performance Curves
20

1.03

C

.§.
15
zw
a:
a:

-550 C

...

~

k:: ~

:::I
(.)

~

II.
II.

10

(I)

V"

tz

w

~

~~V
V

~~ ~

:::I

./ ~

V

5

10

1.01

Q

1.00

w

....
00(

25°C

:Ii

z~

15

....

1::1

~ ....
5

a:::Iw
a:
II.

1250 C -

1.02

20

30

25

0.99
0.98

5

10

SUPPLY VOLTAGE M

15

20

25

30

SUPPLY VOLTAGE (V)

CJ

FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE

o

FIGURE 12. FREQUENCYvs SUPPLY VOLTAGE

..J
ctf/)

z!:::

«::::I
«0::
00
w

1.03

..JO
~

zW
:::I

~

~a:~

c

g

1.02

~

1.01
30
1.00

20
10

c..

f/)

L.--' ~ ~

"'-

r- r;o-

10- f-""

0.9 9
0.9 8
~

·50

·25

0

25

75

125

2

FIGURE 13. FREQUENCYvs TEMPERATURE

4

6

8

LOAD RESISTANCE (1Ul)

TEMPERATURE ('Ie)

FIGURE 14. SQUARE WAVE OUTPUT RISEIFALL TIME vs
LOAD RESISTANCE

8-161

10

ICL8038

Typical Performance Curves (Continued)
2

1.0

w

~

'-'

~

~

~

1.S

g
z

~

a

12S0C

1.0

r-....

2SoC

::;)

0.5

-

~

o f/IIIIIo

~

2

4

~

I':> ~ ~ ~

·SSoC

0.9

50

......
. / 10"

i:5

II.
Q

&. ~ ~

!

"-'

0.8

cr:
z

0

6

o

10

8

2

4

6

LOAD CURRENT (rnA)

FIGURE 15. SQUARE WAVE SATURATION VOLTAGE VB LOAD
CURRENT

~'-'

i

~

0

12

14

16

18

10.0

20

~

j

1.1

~

1.0

V

l

I

1.0

II

1
.

0.9

Q

~

10

FIGURE 16. TRIANGLE WAVE OUTPUT VOLTAGE VB LOAD
CURRENT

1.2

w

8

LOAD CURRENT (rnA)

0.8

0.1

......

::Ii
cr:
0 0.7

~

z

0.6
10

100

1K

10K

100K

0.01

1M

10

100

1K

- r\.,

~

g

i

1M

12

1.1
UI

~

100K

FIGURE 18. TRIANGLE WAVE LINEARITY VB FREQUENCY

FIGURE 17. TRIANGLE WAVE OUTPUT VOLTAGE VB
FREQUENCY

~

10K

FREQUENCY (Hz)

FREQUENCY (Hz)

1.0

0.9

IIII

10

l

8

~

6

J

z

~

4
UNADJUSTED

1 '-.1

2

~~
10

100

1K

10K

100K

1M

FREQUENCY (Hz)

I

~

o

10

100

II
A'
'" I

ADJUSTED

1K

1

rj
..;t(V

100K

10K

FREQUENCY (Hz)

FIGURE 19. SINE WAVE OUTPUT VOLTAGE VB FREQUENCY

FIGURE 20. SINE WAVE DISTORTION

8·162

VB

FREQUENCY

1M

ICM7242
Long Range Fixed Timer

November 1996

Features

Description

• Replaces the 2242 in Most Applications

The ICM7242 is a CMOS timer/counter circuit consisting of
an RC oscillator followed by an 8-bit binary counter. It will
replace the 2242 in most applications, with a significant
reduction in the number of external components.

• Timing From Microseconds to Days
• Cascadable
• Monostable or Astable Operation
• Wide Supply Voltage Range •.....•...•.•. 2V to 16V

Three outputs are provided. They are the oscillator output,
and buffered outputs from the first and eighth counters.

• Low Supply Current. •................. 115J.1A at 5V

Pinout

Ordering Information
PART NUMBER
(BRAND)

TEMP.
RANGE (oC)

PACKAGE

ICM7242
(PDIP, SOIC)
TOP VIEW

PKG.
NO.

ICM72421PA

·251085

B Ld PDIP

EB.3

ICM7242CBA
(7242CBA)

01070

B LdSOIC

MB.15

vooOS

Tavo

+20UT

2

7 RC

+128/256 OUT

3

6 TRIGGER

Vss

4

5 RESET

Functional Diagram

G

o
..J

en

«IZ_

«::l
..J()

«0:
00
W
D-

en

ttivoo

~
Vss

6

S

Tavo

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. '
Copyright © Harris Corporation 1996

8·163

RESET

TRIGGER +2 OUT +128/256
OUTPUT

File Number

2866.2

ICM7242
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Voo to VSS) ........................... 18V
Input Voltage (Note 1)
Terminals (Pins 5, 6, 7, 8) ......... .(Vss -0.3V) to (Voo +0.3V)
Continuous Output Current (Each Output) ................ 50mA

Thermal Resistance (Typical, Note 2)

6JA (OCIW)

PDIP Package..... .... ..... ....•..........
100
160
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Storage Temperature Range ........ , -65°C to 150°C
Maximum Junction Temperature (Plastic Package) ........ 150°C
Maximum Lead Temperature (Soldering 1Os) ............. 300°C
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
ICM72421 ................................ -25°C to 85°C
ICM7242C ..................................0oC to 70°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than Voo or less than VSS may cause
destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same supply be
applied to the device before its supply is established and, that in multiple supply systems, the supply to the ICM7242 be turned on first.
2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

voo ~ 5V, TA ~ 25°C, R ~ 10k.Q, C ~ 0.1~F, Vss ~ OV, Unless Otherwise Specified

PARAMETER

MIN

TYP

MAX

UNITS

2

-

16

V

Reset

-

125

-

~

Operating, R ~ 10kn, C ~ 0.1 ~F

-

340

800

~A

Operating, R ~ lMQ, C ~ 0.1~F

-

220

600

~

-

225
5

-

-

250

-

pprnl"C

3.5

-

V

-

25

~

SYMBOL

Guaranteed Supply Voltage

Voo

Supply Current

100

TEST CONDITIONS

TB Inhibited, RC Connected to Vss
Timing Accuracy
RC Oscillator Frequency Temperature
Drtft

M/Ll.t

Independent of RC Components

Time Base Output Voltage

VOTB

ISOURCE ~ 100~
ISINK ~ 1.0mA

0.40

IlA
%

V

Time Base Output Leakage Current

ITBlK

RC~Ground

Trigger Input Voltage

VTRIG

Voo~5V

-

1.6

2.0

V

Voo~ 15V

-

3.5

4.5

V

1.3

2.0

V

-

2.7

4.0

Reset Input Voltage

VRST

Voo~5V
Voo~ 15V

Trigger/Reset Input Current
Max CountToggle Rate

ITRIG,IRST
IT

Voo~2V

Voo~5V

} Counter/Divider Mode

2

Voo'" 15V

V

10

IlA

1

MHz

13

-

MHz

0.22

0.4

V

300

-

~

-

-

pF

22M

Q

6

MHz

50% Duty Cycle Input with Peak to Peak
Voltages Equal to Voo and VSS
Output Saturation Voltage
Output Sourcing Current

VSAT

All Outputs Except TB Output VOO = 5V,
lOUT = 3.2mA

ISOURCE

VOO = 5V Terminals 2 and 3, VOUT '" 1V

MIN Timing Capacitor (Note 3)

CT

Timing Resistor Range (Note 3)

RT

10

Voo=2-16V

NOTE:
3. For design only, not tested.

8-164

1K

ICM7242
Test Circuit

+21 (RC/2) OUTPUT
+28 (RC/256) OUTPUT

TIME BASE PERIOD

= 1.0RC;

ls= lMQ xll'F

NOTE:

4. +21 and +28 outputs are inverters and have active pullups.

Application Information
Operating Considerations
Shorting the RC terminal or output terminals to Voo may
exceed dissipation ratings and/or maximum DC current limits
(especially at high supply voltages).
There is a limitation of 50pF maximum loading on the TB I/O
terminal if the timebase is being used to drive the counter
section. If higher value loading is used, the counter sections
may miscount.
For greatest accuracy, use timing component values shown
in Figure 8. For highest frequency operation it will be desirable to use very low values for the capacitor; accuracy will
decrease for oscillator frequencies in excess of 200kHz.
The timing capacitor should be connected between the RC
pin and the positive supply rail, VOO, as shown in Figure 1.
When system power is turned off, any charge remaining on
the capacitor will be discharged to ground through a large
internal diode between the RC node and VSS' Do NOT reference the timing capacitor to ground, since there is no high
current path in this direction to safely discharge the capacitor
when power is turned off. The discharge current from such a
configuration could potentially damage the device.

The timing diagram for the ICM7242 is shown in Figure 1.
Assuming that the device is in the RESET mode, which
occurs on power up or after a positive signal on the RESET
terminal (if TRIGGER is low), a positive edge on the trigger
input signal will initiate normal operation. The discharge
transistor turns on, discharging the timing capacitor C, and
all the flip-flops in the counter chain change states. Thus, the
outputs on terminals 2 and 3 change from high to low states.
After 128 negative timebase edges, the +28 output returns to
the high state.

. .n--el-l-----------rnlllllllill
,

When driving the counter section from an external clock, the
optimum drive waveform is a square wave with an amplitude
equal to the supply voltage. If the clock is a very slow ramp
triangular, sine wave, etc., it will be necessary to ·square up'
the waveform; this can be done by using two CMOS inverters in series, operating from the same supply voltage as the
ICM7242.

n n
a...I

n n

n r

TRIGGER INPUT
(TERMINAL6)

TlMEBASE INPUT
- - (TERMINAL 8)

~1I L.I L.I L.I L.I - -

+20UTPUT
(TERMINAL 2)
.,. 1281256 OUTPUT
(TERMINAL 3) (ASTABLE
OR "FREE RUN" MODE)

+ 1281256 OUTPUT
(TERMINAL 3)
(MONOSTABLE
OR "ONE SHOT" MODE)

FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS
FOR THE ICM7242 (COMPARE WITH FIGURE 5)

The ICM7242 is a non-programmable timer whose principal
applications will be very low frequency oscillators and long
range timers; it makes a much better low frequency oscillatorltimer than a 555 or ICM7555, because of the on-chip
8-bit counter. Also, devices can be cascaded to produce
extremely low frequency signals.
Because outputs will not be ANDed, output inverters are
used instead of open drain N-Channel transistors, and the
external resistors used for the 2242 will not be required for
the ICM7242. The ICM7242 will, however, plug into a socket
for the 2242 having these resistors.

8-165

FIGURE 2. USING THE ICM7242 AS A RIPPLE COUNTER
(DIVIDER)

Cl

o

.Jf/)

etlZ_
et:J
.JO
eta:::

00
w

0-

f/)

ICM7242
To use the B-bit counter without, the timebase, Terminal 7
(RC) should be connected to ground and the outputs taken
from Terminals 2 and 3.
The ICM7242 may be used for a very low frequency square
wave reference. For this application the timing components
are more convenient than those that would be required by a
555 timer. For very low frequencies, devices may be cascaded (see Figure 3).

Comparing the ICM7242 With the 2242
ICM7242

2242

2V -16V

4V-15V

Operating Temperature Range

-25°C to 85°C

OOC to 70°C

Supply Currant, Voo = 5V

0.7mA(Max)

7mA(Max)

Operating Voltage

Pullup Resistors
TBOulput

No

Yes

+2 Output

No

Yes

+256 Output

No

Yes

3.0MHz

0.5MHz

Resistor to Inhibit Oscillator

No

Yes

Resistor in Series with Reset for
Monostable Operation

No

Yes

Capacitor TB Terminal for HF
Operation

No

Sometimes

Toggle Rate

FIGURE 3. LOW FREQUENCY REFERENCE (OSCILLATOR)

For monostable operation the +28 output is connected to the
RESET terminal. A positive edge on TRIGGER initiates the
cycle (NOTE: TRIGGER overrides RESET).

By selection of Rand C, a wide variety of sequence timing
can be realized. A typical flow chart for a machine tool controller could be as shown in Figure 5.
ICM7242

TRIGGERING CAN BE
OBTAINED FROM A
PREVIOUS STAGE, A
LIMIT SWITCH, OPERATOR SWITCH, ETC.

ICM7242

84 EN:~LE H~g~:

OUTPIIT

ICM7242

~tl
TRIGGER

..l1..._________

TERMINAL6

TB OUTPIIT

I I I I I I ISnT

TERMINAL 8

OUTPIIT

-,

r

ICM7240

ICM7242

It~

t

Itl

t

WAIT

ENABLE

WAIT

COUNT

ENABLE

58

108

58

TO 185

58

FIGURE 5. FLOW CHART FOR MACHINE TOOL CONTROLLER

TERMINAL 3

FIGURE 4. MONOSTABLE OPERATION

The ICM7242 is superior in all respects to the 2242 except
for initial accuracy and oscillator stability. This is primarily
due to the fact that high value p- resistors have been used
on the ICM7242 to provide the comparator timing points.

By cascading devices, use of low cost CMOS AND/OR gates
and appropriate RC delays between stages, numerous
sequential control variations can be obtained. Typical applications include injection molding machine controllers, phonograph record production machines, automatic sequencers
(no metal contacts or moving parts), milling machine controllers, process timers, automatic lubrication systems, etc.
Sequence Timing
• Process Control
• Machine Automation
• Electro-Pneumatic Drivers
• Multi Operation (Serial or Parallel Controlling)

8-166

ICM7242

VDD

VDD

VDD

VDD

TRIGGE~

~- ---fo-.rt-31--+~I-.....rt--31
6

VDD
0--0 0S1

SDK

PUSH S1 TO START SEQUENCE:
--I

I-MUST BE SHORTER THAN "ON TIMEA"

TRIGGER~_________________________________________________________________

1.....o - - - - 1 2 8 R C - 1
OUTPUTA(NOTE)---,

Ir----------------------------------------------I"

128RC

-I

OUTPUT B (NOTE)

I...... 128RC-1

I

OUTPUT C (NOTE)

i---128RC-1

I

OUTPUT D (NOTE)
-oNTIMEA_"

ONTIMEB

NOTE: Select RC values for desired "ON TIME" for each ICM7242.
FIGURE 6. SEQUENCE TIMER

8-167

•

ONTIMEC

J

r

(!J

nNTIMED_1

o
..J

60
40
20

I
TA=-20~

~
!z

~

--

./

~~

/
//./

If//
'(/

o

o

"

-------

'"

V

.-

100M

./

g

~
TA=25oC
~-

~

-

~

13
a:

I
I

12

14

.I

4

2

6

8

10

100 '--__. 1 -_ _...L.._ _- ' -_ _........_ _- - '_ _ _ _<--__" -__-'
100pF 0.001 0.01
0.1
1
10
100 1000 10,000
TIMING CAPACITOR, C ("F)

16

SUPPLY VOLTAGE (V)

FIGURE 8. RECOMMENDED RANGE OF TIMING COMPONENT
VALUES FOR ACCURATE TIMING

FIGURE 7. SUPPLY CURRENT VB SUPPLY VOLTAGE

10,000"

...--..,...---.--__r--__r--_.,r--__,

~--r---

1,000" C--""oE---+--+--_+---t---+

'iii'

.s

100"~~~-3~--~---.--_+--_+--~r_~

!£
~

z

~

~
c(

f---I~'Y'IM

~

RESETMODE_

I

lOOk

~ 10k f---N~~~?-f'~"-
400
UI
a: 300
200
100

l

+10.0

z

+8.0

!;(

+6.0

~

+4.0

r;z

+2.0

TA = 25°C

Q

.s

~

o

Q

VDO=5V

,

I
VOO=2V

roc;
\..

o

/'

.....

2

:::I

UI

0.0

51a:

...

-2.0

Q

-4.0

UI
N

~

\.VDD= 16V

::Ii

~
3
4
5
6
7
RESET AMPLITUDE (V)

FIGURE 11. MINIMUM RESET PULSE WIDTH vs RESET
AMPLITUDE

9

TA=25oC
O.OOlI1F
100pF
O.l"F
O.ool 11F
O.OlI1F
O.OlI1F

~.O

a:

-8.0

z

-10.0

0

8

2

10

4

6

8
10
12
14
SUPPLY VOLTAGE (V)

16

18

FIGURE 12. NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE vs SUPPLY VOLTAGE

8-168

10

20

ICM7242

Typical Performance Curves

5V SVOO S

(Continued)

100M

l~V

N"

e.

"53
=---

~
zUI

C=O.lI1F

~

II:

0

z

·2

II:
UI

1M

==

==

~

1---

::Ii lOOK
:::>

·3

!

-4

::Ii

·5
·25

10K
0

50

25

75

o

2

4

6

8

10

12

14

20

100

§TA=250C

C

!.

Voo=15V

/L

~TA=250C

r-

!2:
UI

.......Voo=5V

II:
II:

:::>

- I--- VDD .15~

./

10

z

~II:

oJ' "VoO =2V

~~

8
0.1
DISCHARGE SATURATION VOLTAGE M

'VDD .. 2V
/'

~
5'"IL

-'
10

FIGURE 15. DISCHARGE OUTPUT CURRENT VI DISCHARGE
OUTPUT VOLTAGE

-

~VDO=5V

U

0.1
0.01

18

FIGURE 14. MAXIMUM DIVIDER FREQUENCY vs SUPPLY
VOLTAGE

FIGURE 13. NORMAUZED FREQUENCY STABILITY IN THE
ASTABLE MODE VI TEMPERATURE

"
LL

16

SUPPLY VOLTAGE M

TEMPERATURE ("C)

100

TA=250C
RC CONNECTED
TO GROUND

r

II:

IL

C=O.lI1F -

Q

-' ~

UI

~=lkll

UI

10M

:::>
CJ

,

~

./

-'

V'/

0.1
0.01

0.1
OUTPUT SATURATION VOLTAGE M

FIGURE 16. OUTPUT SATURATION CURRENT vs OUTPUT
SATURATION VOLTAGE

10
(!J

o
-'
%(V+)

>1/3(V+)

High

Low

On

<%(V+)

> 1/301+)

High

Stable

Stable

Don't Care

<1/301+)

High

High

Off

NOTE: RESET Will dominate all other Inputs:

"I'RiGGrn will dominate over THRESHOLD.

8·172

ICM7555, ICM7556

Schematic Diagram

THRE!HOLD

I

N

CONTROL
VOLTAGE

R = 100k!l ±20% (TYP)

Application Information
General

500

The ICM7555/6 devices are, in most instances, direct
replacements for the NEISE 555/6 devices. However, it is
possible to effect economies in the external component
count using the ICM7555/6. Because the bipolar 55516
devices produce large crowbar currents in the output driver,
it is necessary to decouple the power supply lines with a
good capacitor close to the device. The 7555/6 devices produce no such transients. See Figure 1.
The ICM755516 produces supply current spikes of only
2mA - 3mA instead of 300mA - 400mA and supply decoupiing is normally not necessary. Also, in most instances, the
CONTROL VOLTAGE decoupling capacitors are not
required since the input impedance of the CMOS comparators on chip are very high. Thus, for many applications 2
capacitors can be saved using an ICM7555, and 3 capacitors with an ICM7556.

TA=250C

C
.§.

!zw
II:
II:
::l
U

~
......

::l

III

8-173

400

r\

300

~

200

\

100
0

,

o

SElNE555

G

o

"'"",

--II/)

c(1-

Z_
c(~

ICM7555156

--10

c(a:

200

400

600

800

TIME (ns)

00
w
Q.

FIGURE 1. SUPPLY CURRENT TRANSIENT COMPARED WITH
A STANDARD BIPOLAR 555 DURING AN OUTPUT
TRANSITION

I/)

ICM7555, ICM7556
Power Supply Considerations

Monostable Operation

Although the supply current consumed by the ICM7555/6
devices is very low, the total system supply current can be
high unless the timing components are high impedance.
Therefore, use high values for R and low values for C in Figures 2 and 3.

In this mode of operation, the timer functions as a one-shot,
see Figure 3. Initially the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of
a negative TRIGGER pulse to pin 2, the internal flip-flop is
set which releases the short circuit across the external
capacitor and drives the OUTPUT high. The voltage across
the capacitor now increases exponentially with a time constant t ~ RAC, When the voltage across the capacitor equals
2/3 V+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the OUTPUT
to its low state. TRIGGER must return to a high state before
the OUTPUT can return to a low state.

Output Drive Capability
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of
4.5V or more the ICM7555/6 will drive at least 2 standard
TIL loads.

tOUTPUT = -In

Astable Operation

(1/3) RAC = 1.1 RAC
voo

The circuit can be connected to trigger itself and free run as
a multivibrator, see Figure 2A. The output swings from rail to
rail, and is a true 50% duty cycle square wave. (Trip points
and output swings are symmetrical). Less than a 1% frequency variation is observed, over a voltage range of +5V to
+15V.
f

~

V

TRIGGER-

JL OlITPUT
L~

1
1.4RC

voo ~18V

The timer can also be connected as shown in Figure 2B. In
this circuit, the frequency is:

FIGURE 3. MONOSTABLE OPERATION

Control Voltage
The duty cycle is controlled by the values of RA and Re, by
the equation:

voo
10K
ALTER-

RESET

OlITPUT

The RESET terminal is designed to have essentially the same
trip voltage as the standard bipolar 555/6, i.e., 0.6V to 0.7V. At
all supply voltages it represents an extremely high input
impedance. The mode of operation of the RESET function is,
however, much improved over the standard bipolar 555/6 in
that it controls only the internal flip-flop, which in turn controls
simultaneously the state of the OUTPUT and DISCHARGE
pins. This avoids the multiple threshold problems sometimes
encountered with slow falling edges in the bipolar devices.

t - - -.......~NATE
OlITPUT

CONTROL
VOLTAGE

R

The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal
comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or even
inhibition of oscillation, depending on the applied voltage. In
the monostable mode, delay times can be changed by
varying the applied voltage to the CONTROL VOLTAGE pin.

OPTIONAL

.;!;-C .;!;-CAPACITOR
FIGURE 2A. ASTABLE OPERATION

voo

OPTIONAL

.;!;- CAPACITOR
FIGURE 2B. ALTERNATE ASTABLE CONFIGURATION

8-174

ICM7555, ICM7556
Typical Performance Curves

..
.s.

~

i
w
!l
:::)

...:IE
:::)

II

I

1200

"

TA-250C

1100

I I

1000

900
800
700

..~

I

~

140

g

120

!i:w

100

'I'U

VDD-2V

300
200

.-.--

VDQ=5V

100

o

1ft'

IIJ
f).

400

400
360

L

I II

600

SOO

200
160

II:
II:

80

u
~

80

./. 109

......

~

III

f--

:::)

I

~

!i:w
~

5

100

./

:::)

U

".

lIf:

~

/

./

~

'/

,

~~

1.0

!i:w

160

II:
II:

120

U

:::)

60

......~

40

III

20

VDD=5V

".

VDD-2V

~

i

l..oo'

10.0

./

, ./ /'"

lIf:

~

~l/

~

~

o

".

1.0

./

~

W

Q.

IJ)

"..,....VDD=5V

r--

VDD=2V

./

./ /

"/

0.1
1.0
OUTPUT LOW VOLTAGE M

10.0

FIGURE 8. OUTPUT SINK CURRENT VB OUTPUT VOLTAGE

0.1
0.01

0.1
1.0
OUTPUT LOW VOLTAGE (V)

10.0

FIGURE 9. OUTPUT SINK CURRENT VB OUTPUT VOLTAGE

8-175

c:C1Z_
c:C::I
c:C1l:

00

.....
"...

-'IJ)

-,0

,
.'.VDD= 18V,
!.

B
VDD=2V

CJ

o

FIGURE 7. OUTPUT SINK CURRENT VB OUTPUT VOLTAGE

1

~

10.0

0.1
1.0
OUTPUT LOW VOLTAGE M

TA=70oC

VDD=5V

.

.JJt'

""

./

"

~

0.1
0.01

g

" 1-

./

1/
~

0.1
0.01

-0.01

,

VDD= 18V
10.0

II:
II:

5

~

./

".

S.

1.0

18

100

f- TA '-2~Ob I

C

~

16

~I

I

./

0

-1.0
-0.1
OUTPUT VOLTAGE REFERENCED 1"0 VDD M

6
8
10 12 14
SUPPLY VOLTAGE (V)

VDD-18V'/

10.0

5

FIGURE 6. OUTPUT SOURCE CURRENT VB OUTPUT VOLTAGE

!i:w

4

~

B

""" VDD-18V

-100
-10

I!!

:IE

0
2

lIf:

~

~

II:
II:

'/

III -10.0

200

TA-25oC

~
if

:::)

1

/'

./

~VDD=5V

u

"" ~""

,..... ~

240

-~ ~OJC

TA!-2~ob I

./ ./

VDD=2V

"""

TA=-2OoC

o 11

100

-1.0

,..,

260

FIGURE 5. SUPPLY CURRENT VB SUPPLY VOLTAGE

-0.1

r- TA = 25°C

,.....

320

I

20

o

o

FIGURE 4. MINIMUM PULSE WIDTH REQUIRED FOR
TRIGGERING

i
!

"."..

40

:::)

VDD-18V

~

"
I-

:::)

10
20
30
40
LOWEST VOLTAGE LEVEL OF mRmEFi PULSE (%VDD)

1

~

160

ICM7555, ICM7556
Typical Performance Curves
~
z

100

8

II

4

c

I

I- TA-250C

TA = 25°C

6

~

2

1/

o
2

I

(Continued)

«'

I"
...... \

...Z

..... ~

RA=RB=10kO
C = 0.111f

4

U
~

~

w

,

CI

I\..

II:

1.0
10.0
SUPPLY VOLTAGE (V)

I

500

.s.

~

w

-

400

~

c
z

300

I...

200 I-- TA = 70°C
f - - TA = 25°C

/

100

TA=·200C

I.

I
I

o

10

~

0.1
1.0
DISCHARGE LOW VO.LTAGE (V) .

10.0

I

~ VOO.=5V
~~\ \1
~

/

iii

30

40

LOWEST VOLTAGE LEVEL OF mRmEIi PULSE (%VOO)

I

~~ ~VOO=2V

+0.2
+0.1

...

t-- r-

~

o
-0.1

o

·20

~

VOO = 18V. L

I!,'

.../~

--.= .::,.lo

~

20

40

t--

,

""""'"

80

80

1.0
100m

1.0 ,..--.---r--,..--,..---r--"T""-"T""--'
100m
10m Ir.--t--+---t---t---t---t---t---I

10m
1m

1m h:--"-'Ir-r!£ 100" 1o;::-""'-::-""'Iooo::-t--t---b.L:.>"f:~
z 10" 1oi:::-~Ioi:::-....:::IIho::-.....:::o"""-+-~-Iy''-''''''''ir

!£
w

100"

z

10"

~

1OOn~~~~~:-""~~~~~~~-~-~

~

10n 1-~""""~t.:-~~-=::!'Ioo..A~"="Ic-+---l
1n I-~I-:-""~~~:-""~~~~~~~+---l

~

1"
100n
10n
1n
100p

u

~

1" ~~~:-""~.....:::o'looo:~~~~~~

~

1oopl-~I--r-:-""~:-""~~~~~~~~--l

10p

10p I-~I--r--+-'V'+-~t-"\r-+'k--~--l
1p ~~~_L-_~~~~~~~~~_~
0.1
10
100
1K
10K 100K 1M
10M

1"

FREQUENCY (Hz)
FIGURE 14. FREE RUNNING FREQUENCY VB RA. RB AND C

\. ~

TEMPERATURE (OC)
FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE VB TEMPERATURE

FIGURE 12. PROPAGATION DELAY VB VOLTAGE LEVEL OF
TRIGGER PULSE

~
U

~

,

rn

/

20

VOO=2V

RA=RB=10kO
I:-C = 0.1"F

I

o

i.--'"

~

FIGURE 11. DISCHARGE OUTPUT CURRENT VB DISCHARGE
OUTPUT VOLTAGE

V-

0

!i

,h
~

---

~

,

~

0.1
0.01

100.0

VOO=5V'==

-'

is

VOO-5V
"CO

"'"
V

~

U

FIGURE 10. NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE VB SUPPLY VOLTAGE
600

-'
1.0

II)

I

8
0.1

'fI'

:::)

~ i"oo..

I I II

6

./

w 10.0

II:
II:

RA= RB =10MO f-C= 100pF

"""'"

f-- -'VOO=18V./

.§.

10"

100"

1m

10m 100m

TIME DELAY (8)
FIGURE 15. TIME DELAY IN THE MONOSTABLE MODE VB
RAANDC

8·176

10

9
HARRIS QUALITY AND RELIABILITY

PAGE
Harris Quality ................................................................................... .

9-3

Introduction ................................................................................... .

9-3

The Role of the Quality Organization ................................................................ .

9-3

The Improvement Process ....................................................................... .

9-3

ISO 9000 Certification ........................................................................... .

9-3

Qualified Manufacturing List (QML) ................................................................. .

9-3

Designing for Manufacturability .................................................................... .

9-3

Special Testing ................................................................................ .

9-5

Harris Semiconductor Standard Processing Flow . .................................................... .

9-6

Controlling and Improving the Manufacturing Process - SPC/DOX ......................................... .

9-8

Average Outgoing Quality (AOQ) .................................................................. .

9-9

Training ...................................................................................... .

9-9

Incoming Materials ............................................................................. .

9-9

Calibration Laboratory ........................................................................... .

9-11

Manufacturing Science - CAM, JIT, TPM ............................................................. .

9-11

Harris Reliability . ................................................................................ .

9-12

Introduction ................................................................................... .

9-12

Reliability Engineering ........................................................................... .

9-12

Design for Reliability (Wear-Out Characterization) ..................................................... .

9-13

Process/Product/Package Qualifications ............................................................ .

9-13

Product/Package Reliability Monitors ............................................................... .

9-13

Customer Return Services ....................................................................... .

9-15

Product Analysis Lab ............................................................................ .

9-19

Analytical Services Laboratory .................................................................... .

9-20

Reliability Fundamentals and Calculation of Failure Rate ................................................ .

9-21

Failure Rate Calculations ......................................................................... .

9-21

Acceleration Factors ..........................•..................................................

9-22

Activation Energy............................................................................... .

9-22

Electrostatic Discharge Control: A Guide To Handling Integrated Circuits ................. .

9-23

Tech Brief 52

9-1

Q)-

Z ....

<::::i

)--

.... al

-<
..J<..J
;:)w

all:

Harris Quality
Introduction

The Improvement Process

Success in the integrated circu~ industry means more than
simply meeting or exceeding the demands of today's market.
It also includes anticipating and accepting the challenges of
the future. It results from a process of continuing improvement
and evolution, with periection as the constant goal.

l

STAGEIV

IMPACTON
PRODUCT
QUALITY

Harris Semiconductor's commitment to supply only top value
integrated circuits has made quality improvement a mandate
for every person in our work force - from circuit designer to
manufacturing operator, from hourly employee to corporate
executive. Price is no longer the only determinant in
marketplace competition. Quality, reliability, and periormance
enjoy significantly increased importance as measures of value
in integrated circuits.

-I

J

PRODUCT
OPTIMIZATION
STAGE III
PROCESS
OPTIMIZATION
STAGE II
PROCESS
CONTROL

STAGE I
PRODUCT
SCREENING
SOPHISTICATION OF QUALITY TECHNOLOGY

Quality in integrated circuits cannot be added or considered
after the fact. It begins with the development of capable
process technology and product design. It continues in
manufacturing, through effective controls at each process or
step. It culminates in the delivery of products which meet or
exceed the expectations of the customer.

The Role of the Quality Organization
The emphaSis on building quality into the design and
manufacturing processes of a product has resulted in a
significant refocus of the role of the Quality organization. In
addition to facilitating the development of SPC and DOX,
Quality professionals support other continuous improvement
tools such as control charts, measurement of equipment
capability, standardization of inspection equipment and
processes, procedures for chemical controls, analysis of
inspection data and feedback to the manufacturing areas,
coordination of efforts for process and product improvement,
optimization of environmental or raw materials quality, and the
development of quality improvement programs with vendors.
At critical manufacturing operations, process and product
quality is analyzed through random statistical sampling and
product monitors. The Quality organization's role is changing
from policing quality to leadership and coordination of quality
programs or procedures through auditing, sampling,
consulting, and managing Quality Improvement projects.
To support specific market requirements, or to ensure
conformance to military or customer specifications, the
Quality organization still periorms many of the conventional
quality functions (e.g., group testing for military products or
wafer lot acceptance). But, true to the philosophy that quality
is everyone's job, much of the traditional on-line measurement
and control of quality characteristics is where it belongs - with
the people who make the product. The Quality organization is
there to provide leadership and assistance in the deployment
of quality techniques, and to monitor progress.

FIGURE 1. STAGES OF STATISTICAL QUALITY TECHNOLOGY

Harris Semiconductor's quality methodology is evolving through
the stages shown in Figure 1. In 1981 we embarked on a
program to move beyond Stage I, and we are currently in the
transition from Stage III to Stage IV, as more and more of our
people become involved in quality activities. The traditional
"quality" tasks of screening, inspection, and testing are being
replaced by more effective and efficient methods, putting new
tools into the hands of all employees. Table 1 illustrates how our
quality systems are changing to meet today's needs.

ISO 9000 Certification
The manufacturing operations of Harris Semiconductor have
all received ISO certification. The ISO 9000 series of
standards were very consistent with our goals to build an even
stronger quality system foundation.

Qualified Manufacturing List (QML)
Harris Semiconductor has supplied military grade integrated
circuits for over 20 years. The government's certifying body had
audited and granted approval to ship JAN, 883 compliant, and
Source Military Drawing parts used in ground and space
applications. The discipline required to manufacture high
reliability components has been beneficial to the commercial
product lines. Harris has now taken the next evolutionary step
by transitioning into QML as defined in MIL-PRF-38535. These
guidelines incorporate the best commercial practices for
semiconductor manufacturing.

Designing for Manufacturability
Assuring quality and reliability in integrated circu~ begins with
good product and process design. This has always been a
strength in Harris Semiconductor'S quality approach. We have a
very long lineage of high reliabil~, high performance products
that have resulted from our commitment to design excellence. All
Harris products are designed to meet the stringent qual~ and
reliabil~ requirements of the most demanding end equipment
applications, from mil~ry and space to industrial and
telecommunications. The application of new tools and methods
has allowed us to continuously upgrade the design process.

9-3

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TABLE 2. HARRIS IC DESIGN TOOLS

<::J

1. Design simulation/optimization

Z~

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2. Layout verification

PRODUCTS

3. Product demonstration

DESIGN STEP

4. Reliability assessment
Harris designers have an extensive set of very powerful
Computer-Aided DeSign (CAD) tools to create and optimize
product designs (see Table 2).

Special Testing
HarriS Semiconductor offers several standard screen flows
to support a customer's need for additional testing and reliability assurance. These flows include environmental stress
testing, burn-in, and electrical testing at temperatures other
than 25°C. The flow shown in Figures 2 and 3 indicates the
Harris standard processing flow for a commercial linear part

9-5

ANALOG

DIGITAL

Functional Simulation Cds Spice

Cds Spice Verilog

Parametric Simulation Cds Spice Monte
Carlo

Cds Spice

Schematic Capture

Cadence

Cadence

Functional Checking

Cadence

Cadence

Rules Checking

Cadence

Cadence

Parasitic Extraction

Cadence

Cadence

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Harris Semiconductor Standard Processing Flow

COMMERCIAL

W

PROBE/DICE

~EPARATION

HIGH/ROOM
TEMP
PROBE TEST

--

.......

VISUAL INSPECTION
MODIFIED
MIL-STD-BB3
METHOD 2010
CONDITION B
WITH QC MONITOR

ASSEMBLY (1)
•

DIE ATTACH
CONTROL

WIRE BOND
CONTROL

POST BOND
VISUAL

••
I

•
I

*
•

OPERATION
QUALITY MONITOR
DIE MOUNT

II

LEAD FINISH
CONTROL

II

•
II

YES
YES

WIRE BOND

YES

QUALITY WIRE BOND
r * CONTROL
(SPC)

YES

•• POST BOND INSPECTION
(RTPC)

YES

r*
MOLD CONTROL

YES

n MOUNT CURE CONTROL
r* CONTROL
QUALITY DIE ATTACH
(SPC)

QUALITY POST BOND
INSPECTION

AS APPLICABLE

MOLDING

YES

MOLD CONTROL (SPC)

YES

BOTTOM CODE

YES

POST MOLD CURE

YES

TRIMIFORM/DERAIL

YES

SINGULATED SOLDER DIP

YES

100% VISUAL INSPECTION

YES

LOAD SHIPPING TUBES

YES

1-* QA LOT ACCEPTANCE
QA DOCUMENTATION
'-* INSPECTION

..........

-

(1) Example for a PDIP Package Part

FIGURE 2.

9-6

YES
YES

.......

I

Harris Semiconductor Standard Processing Flow

(Continued)

COMMERCIAL

•

TEST (2)
•

*
ACIDC SINGLE
INSERTION TEST
CAPABILITY;
HIGHILOW TEMP

OPERATION
QUALITY MONITOR

100% ELECTRICAL TEST

TOP BRAND
PRE-BURN-IN ELECTRICAL
TEST

BURN-IN

QUALITY
LOT ACCEPTANCE

PDIPLEAD
SCANNING

YES

YES
IF APPLICABLE

BURN-IN
POST BURN-IN
ELECTRICAL TESTS

IF APPLICABLE
IF APPLICABLE

APPLY BURN-IN PDA

IF APPLICABLE

*

QC PRESHIP LOT
ACCEPTANCE TEST

YES

100% LEAD SCANNING
PACKING

YES
YES

-*

QC PRESHIP LOT
ACCEPTABLE
INSPECTION

FINAL DATA REVIEW

YES

YES

~~

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FIGURE 3.

9-7

Harris Qua/ity
TABLE 3. PROCESS CONTROL APPLICATIONS
FAB

·

Diffusion
Junction Depth
Sheet Resistivities
Oxide Thickness
Implant Dose Calibration
Uniformity

.

·-

Photo Resist
Critical Dimension
Resist Thickness
Etch Rates
- Energy Monitor (Eo)

• Thin Film
Film Thickness
Uniformity
Refractive Index
Film Composition
Particles Added

-

Measurement
Equipment
Critical
Dimension
Film Thickness
Resistivity

-

ASSEMBLY
• Pre-Seal
Die Prep Visuals
Yields
Die Attach Heater Block
Die Shear
Wire Pull
Ball Bond Shear
Saw Blade Wear
Pre-Cap Visuals

-

·-

Post-Seal
Internal Package Moisture
Tin Plate Thickness
PI NO Defect Rate
Solder Thickness
Leak Tests
- Module Rm. Solder Pot Temp.
Seal
Temperature Cycle

-

• Measurement
XRF
Radiation Counter
Thermocouples
- GM-Force Measurement

-

TEST

-

Handlers/Test System
Defect Pareto Charts
Lot % Defective
ESD Failures per Month

Monitor Failures

- Lead Strengthening Quality
-

After Burn-In PDA

OTHER

·

IQC
Vendor Performance
Material Criteria
Quality Levels

-

·

• Environment
Water Quality
- Clean Room Control
Temperature
Humidity

-

IQC Measurement/Analysis
XRF
ADE
4 Point Probe
Chemical Analysis Equipment

-

ContrOlling and Improving the Manufacturing Process - SPC/DOX
Statistical process control (SPC) is the basis for quality control
and improvement at Harris Semiconductor. Harris manufacturing
people use control charts to determine the normal variabilities in
processes, materials, and products. Critical process variables
and performance characteristics are measured and control limits
are plotted on the control charts. Appropriate action is taken if the
charts show that an operation is outside the process control limits
or indicates a nonrandom pattern inside the limits. These same
control charts are powerful tools for use in reducing variations in
processing, materials, and products. Table 3 lists some typical
manufacturing applications of control charts at Harris
Semiconductor.

and visual inspection as value-added testing options. However, inspection and screening are limited in their ability to
reduce product defects to the levels expected by today's buyers. In addition, screening and inspection have an associated
expense, which raises product cost (see Table 4).

TABLE 4. APPROACH AND IMPACT OF STATISTICAL QUALITY
TECHNOLOGY
STAGE

SPC is important, but still considered only part of the solution.
Processes which operate in statistical control are not always
capable of meeting engineering requirements. The
conventional way of dealing with this in' the semiconductor
industry has been to implement 100% screening or inspection
steps to remove defects, but these techniques are insufficient
to meet today's demands for the highest reliability and perfect
quality performance.
Harris still uses screening and inspection to "grade" products
and to satisfy specific customer requirements for burn-in, multiple temperature test insertions, environmental screening,

9-8

APPROACH

IMPACT

I

Product
Screening

• Stress and Test
• Limited Quality
• Defective Prediction • Costly
• After-The-Fact

II

Process
Control

• Statistical Process
Control
• Just-In-Time
Manufacturing

III

Process
Optimization

·
·
·

Design of Experiments
Process Simulation

IV Product
• Design for ProducOptimization
ibility
Product Simulation

··

·
··
·
·

Identifies Variability
Reduces Costs
RealTime
Minimizes Variability
Before-The-Fact

Insensitive to Variability
Designed-In Quality
• Optimal Results

Harris Quality
Harris engineers are, instead, using Design of Experiments
(DOX), a scientifically disciplined mechanism for evaluating and
implementing improvements in product processes, materials,
equipment, and facil~ies. These improvements are aimed at
upgrading process performance by studying the key variables
controlling the process, and optimizing the procedures or
design to yield the best result. This approach is a more timeconsuming method of achieving quality perfection, but a better
product results from the efforts, and the basic causes of
product nonconformance can be eliminated.
SPC, DOX, and design for manufacturability, coupled with our
100% test flows, combine in a product assurance program
that delivers the quality and reliability performance demanded
for today and for the future.

manufacturing began in 1984 at Harris, with a comprehensive
development program in statistical methods. Using the
resources of Harris statisticians, private consultants, and
internally developed programs, training of engineers,
facilitators, and operatorsltechnicians has been an ongoing
activity in Harris Semiconductor.
Over the past years, Harris has also deployed a
comprehensive training program for hourly operators and
facilitators in job requirements and functional skills. All hourly
manufacturing employees participate (see Table 5).

Incoming Materials

Average Outgoing Quality (AOQ)
Average Outgoing Quality is a yardstick for our success in
quality manufacturing. The average outgoing electrical
defective is determined by randomly sampling units from each
lot and is measured in parts per million (PPM). The current
procedures and sampling plans outlined in ANSI/ASQC Z1.4,
MIL-STD-883 and MIL-PRF-38535 are used by our quality
inspectors.

Improving the quality and reducing the variability of critical
incoming materials is essential to product quality
enhancement, yield improvement, and cost control. With the
use of statistical techniques, the influence of silicon,
chemicals, gases and other materials on manufacturing is
highly measurable. Current measurements indicate that
results are best achieved when materials feeding a
statistically controlled manufacturing line have also been
produced by statistically controlled vendor processes.

Training

To assure optimum quality of all incoming materials, Harris
has initiated an aggressive program, linking key suppliers with
our manufacturing lines. This user-supplier network is the
Harris Vendor Certification process by which strategic
vendors, who have performance histories of the highest
qual~, participate with Harris in a lined network; the vendor's
factory acts as if it were a beginning of the Harris production line.

The basis of a successful transition from conventional quality
programs to more effective, total involvement is training.
Extensive training of personnel involved in product

SPC seminars, development of open working relationships,
understanding of Harris's manufacturing needs and vendor
capabilities, and continual improvement programs are all

The focus on this quality parameter has resulted in a
continuous improvement to less than 100 PPM, and the goal
is to continue improvement toward 0 PPM.

TABLE 5. SUMMARY OF TRAINING PROGRAMS
COURSE

AUDIENCE

TOPICS COVERED

SPC, Basic

Manufacturing Operators,
Non-Manufacturing
Personnel

Harris Philosophy of SPC, Stalistical Definitions, Statistical Calculations,
Problem Analysis Tools, Graphing Techniques, Control Charts

SPC, Intermediate

Manufacturing Supervisors,
Technicians

Harris Philosophy of SPC, Statistical Definitions, Statistical Calculations,
Problem Analysis Tools, Graphing Techniques, Control Charts, Distributions,
Measurement Process Evaluation, Introduction to Capability

SPC, Advanced

Manufacturing Engineers,
Manufacturing Managers

Harris Philosophy of SPC, Statistical Definitions, Statistical Calculations,
Problem Analysis Tools, Graphing Techniques, Control Charts, Distributions,
Measurement Process Evaluation, Advanced Control Charts, Variance Component Analysis, Capability Analysis

DeSign of Experiments
(DOX)

Engineers, Managers

Factorial and Fractional Designs, Blocking Designs, Nested Models, Analysis
of Variance, Normal Probability Plots, Statistical Intervals, Variance Component Analysis, Multiple Comparison Procedures, Hypothesis Testing, Model
Assumptions/Diagnostics

Regression

Engineers, Managers

Simple Linear Regression, Multiple Regression, Coefficient Interval Estimation, Diagnostic Tools, Variable Selection Techniques

Response Surface
Methods (RSM)

Engineers, Managers

Steepest Ascent Methods, Second Order Models, Central Composite
Designs, Contour Plots, Box-Behnken Designs

Capability Studies

Techs, Faciitators,
Engineers

Capability Indices (C p and CPK), Variance Components, Nested Models,
Fixed and Random Effects

9-9

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Harris Quality
part of the certification process. The sole use of engineering
limits no longer is the only quantitative requirement of incoming materials. Specified requirements include centered
means, statistical control limits, and the requirement that
vendors deliver their products from their own statistically
evaluated, in-control manufacturing processes.
.

In addition to the certification process, Harris has worked to
promote improved quality in the performance of all our qualified
vendors who must meet rigorous incoming inspection criteria
(see Table 6).

TABLE 6. INCOMING QUALITY CONTROL MATERIAL QUALITY CONFORMANCE
MATERIAL
Silicon

INCOMING INSPECTIONS

·

Equipment Capability Control Charts
- Oxygen
Resistivity
• Control Charts Related to
- Enhanced Gettering
Total Thickness Variation
Total Indicated Reading
Particulates
• Certificate of Analysis for all Critical Parameters

• Resistivity
• Crystal Orientation
• Dimensions

·

Edge Conditions

• Backside Criteria
• Oxygen

• Control Charts from On-Line Processing

• Carbon

• Certificate of Conformance

• Chemicals
Assay
- Major Contaminants
• Molding Compounds
Spiral Flow
- Thermal Characteristics
• Gases
Impurities
• Photo resists
Viscosity
Film Thickness
SolidS
Pinholes

• Certificate of Analysis on all Critical Parameters

• Assay
• Selected Contaminants

• Control Charts from On-Line Processing

• Certificate of Conformance
• Control Charts from On-Line Processing
• Control Charts
- Assay
Contaminants
Water
Selected Parameters
• Control Charts
- Assay
- Contaminants
• Control Charts on
Photospeed
Thickness
UV Absorbance
Filterability
Water
Contaminants

-

--

-

Thin Film Materials

-

• Taper
• Thickness
• Total Thickness Variation

ChemlcalsJPhotoreslsts/
Gases

VENDOR DATA REQUIREMENTS

-

• Control Charts
Assay
- Contaminants
Dimensional Characteristics.
• Certificate of Analysis for all Critical Parameters

-

• Certificate of Conformance
Assembly Materials

• Visual Inspection

• Certificate of Analysis

• Physical Dimension Checks

• Certificate of Conformance

·

• Glass Composition
• Bondability
• Intermetallic Layer Adhesion

·

Ionic Contaminants

• Thermal Characteristics
• Lead Coplanarity
• Plating Thickness
• Hermeticity

9-10

Process Control Charts on Outgoing Product Checks
and In-Line Process Controls

Harris Quality
Calibration Laboratory

Just In Time (JIT)

Another important resource in the product assurance system
is a calibration lab in each Harris Semiconductor operation
site. These labs are responsible for calibrating the electronic,
electrical, electro/mechanical, and optical equipment used in
both production and engineering areas. The accuracy of
instruments used at Harris is traceable to a national
standards. Each lab maintains a system which conforms to
the current revision of ANSI/NCSL Z540-1.

The major focus of JIT is cycle time reduction and linear
production. Significant improvements in these areas result in
large benefits to the customer. JIT is a part of the Total Quality
Management philosophy at Harris and includes Employee
Involvement, Total Quality Control, and the total elimination of
waste.

Each instrument requiring calibration is asSigned a calibration
interval based upon stability, purpose, and degree of use. The
equipment is labeled with an identification tag on which is
specified both the date of the last calibration and of the next
required calibration. The Calibration Lab reports on a regular
basis to each user department. Equipment out of calibration is
taken out of service until calibration is performed. The Quality
organization performs periodic audits to assure proper control
in the using areas. Statistical procedures are used where
applicable in the calibration process.

Some key JIT methods used for improvement are sequence
of events analysis for the elimination of non-value added
activities, demand/pull to improve production flow, TQC check
pOints and Employee Involvement Teams using root cause
analysis for problem solving.
JIT implementations at Harris Semiconductor have resulted in
significant improvements in cycle time and linearity. The
benefits from these improvements are better on time delivery,
improved yield, and a more cost effective operation.
JIT, SPC, and TPM are complementary methodologies and
used in conjunction with each other create a very powerful
force for manufacturing improvement.

Manufacturing Science - CAM, JIT, TPM

Total Productive Maintenance (TPM)

In addition to SPC and DOX as key tools to control the product
and processes, Harris is deploying other management
mechanisms in the factory. On first examination, these tools
appear to be directed more at schedules and capacity.
However, they have a significant impact on quality results.

TPM or Total Productive Maintenance is a specific
methodology which utilizes a definite set of prinCiples and
tools focusing on the improvement of equipment utilization. It
focuses on the total elimination of the six major losses which
are equipment failures, setup and adjustment, idling and
minor stoppages, reduced speed, process defects, and
reduced yield. A key measure of progress within TPM is the
overall equipment effectiveness which indicates what
percentage of the time is a particular equipment producing
good parts. The basic TPM prinCiples focus on maximum
equipment utilization, autonomous maintenance, cross
functional team involvement, and zero defects. There are
some key tools within the TPM technical set which have
proven to be very powerful to solve long standing problems.
They are initial clean, P-M analysis, condition based
maintenance, and quality maintenance.

Computer Aided Manufacturing (CAM)
CAM is a computer based inventory and productivity
management tool which allows personnel to quickly identify
production line problems and take corrective action. In
addition, CAM improves scheduling and allows Harris to more
quickly respond to changing customer requirements and aids
in managing work in process (WIP) and inventories.
The use of CAM has resulted in significant improvements in
many areas. Better wafer lot tracking has facilitated a number
of process improvements by correlating yields to process
variables. In several places CAM has greatly improved
capacity utilization through better planning and scheduling.
Queues have been reduced and cycle times have been
shortened - in some cases by as much as a factor of 2.
The most dramatic benefit has been the reduction of WIP
inventory levels, in one area by 500%. This results in fewer
lots in the area and a resulting quality improvement. In wafer
fab, defect rates are lower because wafers spend less time in
production areas awaiting processing. Lower inventory also
improves morale and brings a more orderly flow to the area.
CAM facilitates all of these advantages.

Utilization of TPM has shown significant increases in
utilization on many tools across the Sector and is rapidly
becoming widespread and recognized as a very valuable tool
to improve manufacturing competitiveness.
The major benefits of TPM are capital avoidance, reduced
costs, increased capability, and increased quality. It is also
very compatible with SPC techniques since SPC is a good
stepping stone to TPM implementation and it is in turn a good
stepping stone to JIT because a high overall equipment
effectiveness guarantees the equipment to be available and
operational at the right time as demanded by JIT.

9-11

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Harris Reliability
The reliability organization is comprised of a team that
possesses a broad cross section of expertise in these areas:

Introduction
At Harris Semiconductor, reliability is built into every product
by emphasizing quality throughout manufacturing. This starts
by ensuring the excellence of the design, layout, and
manufacturing processes. The quality of the raw materials
and workmanship is monitored using statistical process
control (SPC) to preserve the reliability of the product. The
primary and ultimate goal of these efforts is to provide full
performance to the product specification throughout its useful
life.

The Reliability Engineering department is responsible for all
aspects of reliability aSSurance at Harris Semiconductor:

• Mission
- To develop systems for assessing, enhancing, and assuring
that quality and reliability are integrated into all aspects of
our business.
• Vision
- To establish excellence and integrity through all design and
manufacturing processes as it relates to quality and reliability.
Values
• To be considered responsive and service oriented by
our customers.
• To be acknowledged by Harris as a highly qualified
resource for reliability assurance, product analysis, and
electronic materials characterization.
• To successfully utilize the organization's talents through
trained, empowered employees/employee team participation.
• To maintain an attitude of integrity, dignity and respect
for all.
Strategy
• To provide quantitative assessments of product reliability focusing on the identification and timely elimination
of design and processing deficiencies that degrade
product performance and operating life expectancy.
• To provide systems for continuous improvement of reliability and quality through the assessment of existing
processes, products, and packages.
• To perform product analysis as a means of problem
solving and feedback to our customers, both internal
and external.
• To exercise full authority over the internal qualifications
of new products, processes, and packages.

• Automotive ASICs
• Harsh Environment Plastic Packaging
• Advanced Methods for Design for Reliability (DFR)
• Strength in Power Semiconductor
• ChemicaVSurface Analysis Capabilities
• Failure Analysis Capabilities

Reliability Engineering

• Charter
- To ensure that Harris is recognized by our customers and
competitors as a company that consistently delivers products with high reliability.

• Custom Military (Radiation Hardened)

The reliability focus is customer satisfaction (external and
internal) and is accomplished through the development of
standards, performance metrics, and service systems. These
major systems are summarized below:
• A process and product development system known as
ACT PTM (Applying Concurrent Teams to Product-ToMarket) has been established. The ACT PTM philosophy
is one of new product development through a team that
pursues customer involvement. The team has the authority, responsibility, and training necessary to successfully
bring the product to market. This not only includes product
definition and design, but also all manufacturing capabilities as well.
• Standard test vehicles (over 100) have been developed for
process characterization of wear-out failure mechanisms.
These vehicles are used for conventional stresses (for
modeling failure rates) and for wafer level reliability characterization during development.
• Common qualification standards have been established
for all sites.
• A reliability monitoring system (also known as the Matrix
monitoring system) is utilized for products in production to
ensure ongoing reliability and verification of continuous
improvement.
• The field return system is designed to handle a variety of
customer issues in a timely manner. Product issues are
often handled by routing the product into the PFAST
(Product Failure Analysis Solution Team) system. Return
authorizations (RAs) are issued where an entire lot of
product needs t6 be returned to Harris. The Customer
Return Services (CRS) group is responsible for the administration of this system (see Customer Return Services.)
• The PFAST system has been established to expedite failure analysis, failure root cause determination, and corrective actions for field returns. PFAST is a team effort involving many functional'areas at all Harris sites. The purpose
of this system is to enable Harris's Field Sales and Quality
operations to properly route, track, and respond to our
customer's needs as they relate to product analysis.

9-12

Harris Reliability
Design for Reliability
(Wear-Out Characterization)
The concept of "Design for Reliability" focuses on moving
reliability assessment away from tests on sample product to a
point much earlier in the design cycle. Effort is directed at
building in and verifying the reliability of a new process well
before manufacture of the first shippable product that uses
that technology. This gives these first new products a higher
probability of success and achieves reduced product-tomarket cycle times.
In practice, a set of standardized test vehicles containing
special test structures are transferred to the new process
using the layout ground rules specified for that process. Each
test structure is designed for a specific wear-out failure
mechanism. Highly accelerated stress tests are performed on
these structures and the results can be extrapolated to
customer use conditions. Generally, log-normal statistics are
used to define wear-out distributions for the life prediction
models. The results are used to establish reliability design
ground rules and critical node lists for each process. These
ground rules and critical nodes ensure that wear-out failures
do not occur during the customer's projected use of the
product.

the package. Any failures occurring on the Matrix monitors are
fully analyzed and the failure mechanisms identified, with
containment and corrective actions obtained from
Manufacturing and Engineering. This information along with
all of the test results are routinely transmitted to a central data
base in Reliability Engineering, where failure rate trends are
analyzed and tracked on an ongoing basis. These data are
used to drive product improvements, to ensure that failure
rates are continuously being reduced over time.
Reliability data, including the Matrix Monitor results, can be
obtained by accessing our Reliability Engineering WWW
Home Page at URL: http://rel.semLharris.com or by contacting your local Harris sales office.
TABLE 7. PLASTIC PACKAGED IC MONITORING TESTS
. MATRIX I

CONDITIONS

DURATION

SAMPLE!
LTPD

Autoclave

121°C,100%RH,
15PSIG

96 Hours

45/5

Biased Life

175°C

48 Hours

45/5

125°C

48 Hours

45/5

TEST

Biased Life

Process/Product/Package Qualifications

HAST

135°C, 85% RH

48 Hours

45/5

Once the new process has successfully completed wear-out
characterization, the final qualification consists of more
conventional testing (e.g. biased life, storage life, temp cycle
etc.). These tests are performed on the first new product
designs (sampled across multiple wafer production lots).
Successful completion of the final qualification tests
concurrently qualifies the new process and the new products
that were used in the qualification. Subsequent products
designed within the now-established ground rules are
qualified individually prior to introduction. New package
configurations are also qualified individually prior to being
available for use with new products.

Thermal Shock

-65°C to 150°C

200 Cycles

45/5

CONDITIONS

DURATION

SAMPLE!
LTPD

121°C,100%RH,
15PSIG

192 Hours

45/5

85°C, 85% RH

1000 Hours

45/5

MATRIX II
TEST
Autoclave
Biased Humidity

Harris's qualification procedures are specified via controlled
documentation and the same standard is used at Harris's
sites worldwide. Figure 4 gives more information on the new
process/product development and life cycle.

Biased Life

125°C

1000 Hours

45/5

Dynamic Life

125°C

1000 Hours

45/5

Storage Life

150°C

1000 Hours

45/5

Product/Package Reliability Monitors

Temp. Cycle

-65°C to 150°C

1000 Cycles

45/5

Many of the accelerated stress-tests used during initial
reliability qualification are also employed during the routine
monitoring of standard product. Harris's continuing reliability
monitoring program consists of three groups of stress tests,
labeled Matrix I, II and III. Table 7 outlines the Matrix tests
used to monitor plastic packaged ICs in Harris's off-shore
assembly plants, where each wafer fab technology is
sampled. Matrix I consists of highly accelerated, short
duration (typically 48 hours) tests, sampled biweekly, which
provide real-time feedback on product reliability. Matrix II
consists of the more conventional, longer term stress-tests,
sampled monthly, which are similar to those used for product
qualification. Finally, Matrix III, performed monthly on each
package style, monitors the mechanical reliability aspects of

9-13

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MATRIX III
CONDITIONS

SAMPLEILTPD

MIL-STD-883/2015

15/15

Flammability

(UL-94 Vertical Burn)

11/20

Lead Fatigue

MIL-STO-883/2004

15/15

Physical Dimensions

MIL-STD-883/2016

11/20

Solderability

MIL-STO-883/2003

45/15

TEST
Brand Adhesion

Harris Reliability
RELIABILITY FOCUS

FLOW - PROCESSJPRODUCT DEVELOPMENT

I

PRODUCT DEFINmON REVIEW

I

• Assumes process development required

I

• Evaluate reliability risks factors
• Attain commitment for test vehicle development

t
I

CONCEPT REVIEW

I

DESIGN REVIEW

l-

•
•
•
•
•

I

LAYOUT REVIEW

I

•
•
•
•
•
•

I

TEST VEHICLE FABRICATION

I

• Test vehicles and/or product constructed
• Conduct wear-out characterization and/or product stress testing

I

EVALUATION REVIEW

I

• Review test vehicle stress results
• Verity wear-out mechanisms are eliminated by design and Statistical Process
Control (test vehicle + SPC)
• Review product characterization to data sheet, ESD, latch-up and Destructive
Physical Analysis (DPA) results and define corrective actions
• Review of life test data and failure mechanisms. Define corrective actions
• Utilize statistical Design Of Experiments (DOX) if required to adjust process or design
• Define necessary changes to eliminate any systematic failure mechanism
• If mature process - grant generic release

I

NEW PRODUCT TRANSFER

I

• Qualification requirements complete and presented. Meet FIT rate requirements
• Review infant mortality burn-in results
• Initiate reliability monitor plan

MANUFACTURE

I

• Reliability Monitors:
- Matrix monitor assessment
- Military quality conformance testing
• Trend analysis of reliability performance used to develop product improvements
• Yield management support

-I

I
-t

,

.1

SHIPMENT
CONTINUOUS IMPROVEMENT

I-

Review test vehicle development and stress test plan
Review package requirements and ESD requirements
Review latent random failure mechanism history and design for elimination
Review ground rules for design and elimination of wear-out mechanisms
Review process characterization, statistical control and capability and critical
node list
• Review device modeling and simulations
• Review process variability and producibility
• Define wafer level reliability vehicles
Evaluate design of chip to package risk factors
Review Design ground Rule Checks (DRCs)
Establish reliability test, stress and failure analysis capabilities
Project failure rate based on test vehicle data
Review burn-in diagrams for production and qualification
Review overall qualification plan

• High quality and reliable products shipped to Harris customers
• Failure Analysis - Determine assignable cause of failure
• Closed loop corrective action process
• Continuous improvement objectives in product reliability and quality

FIGURE 4. NEW PROCESS/PRODUCT DEVELOPMENT AND LIFE CYCLE

9-14

Harris Reliability
Customer Return Services

• Step 1 - Customer or Sales office contacts the Customer Return Services department. If a return is to be
routed into the PFAST system, then a PFAST Action
Request (see the PFAST form in this section) needs to
be completed to understand the customer's issue and
direct the analysis efforts.

Harris places a high priority on resolving customer return
issues. The Customer Return Services (CRS) department is
responsible for determining the best manner to handle a
return issue as illustrated in Figure 5.

- Phone Number: (407)-724-7400
RA
REQUEST

I I

PFAST
REQUEST

- FAX Number: (407)-724-7658
- Internet: creturn@huey.mis.semi.harris.com

1

- PROFS: CRETURN

ELECTRICAL TESTI
PROBLEM VERIFICATION

• Step 2 - The Customer Return Services department
notifies all affected sales, factory, and engineering
organizations of the issue.

1

• Step 3 - When product is received, the issue is verified
and any required analysis is performed. Where applicable, a preliminary analysis report is sent to the customer.

FAILURE
ANALYSIS

1

• Step 4 - A determination of the root cause of failure initiates the corrective actions to address the source of
the problem. A final corrective action report is sent to
the customer if requested.

CONTAINMENT ACTIONS
AND CORRECTIVE ACTIONS

• Step 5 - The Customer Return Services department
contacts the customer to confirm that all issues have
been handled properly and the customer is satisfied
that the return is completed.

FIGURE 5. GENERAL RETURN FLOW

The diversity of return reasons requires that many different
organizations be involved to test, analyze, and correct field
return issues. The CRS group coordinates the responses
from the supporting organizations to drive closure of issues
within the customer response time requirements, see Table 7.
The results from the work performed on customer returns are
used to initiate corrective actions and continuous
improvements within the factories. When the work on a return
is completed, the customer is contacted to be certain· all
issues have been satisfactorily resolved.
The two methods used to return devices are by a RA (Return
Authorization) request or by a PFAST (Product Failure
Analysis Solution Team) request. The main difference
between RA and PFAST is that the PFAST requests often
require extensive analysis and a more formal response to the
customer. All returns follow the same general procedure from
the customer's perspective as seen in steps one to five of the
customer return procedure.

The RA request is used to return and replace an entire lot of
product. The lot is returned to Harris for replacement or credit.
Once the product is received various tests and evaluations will
be performed to determine the appropriate actions that should
be taken to resolve any problems or issues.
A PFAST request is used to return a small sample for analysis
of a problem. The ultimate outcome of both types of requests
is to determine corrective actions that would preclude the
same problem occurring in the future. Where appropriate, a
containment plan is also implemented to prevent a reoccurrence of the problem in the field. The customer return
flow diagram (Figure 6) provides the typical activities and
cycle times for processing a PFAST request..

9-15

0>

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-$5k
D Failure Analysis
DOther
Impact of Failed Units on Customer's Situation:

Customer Contact with Specific Knowledge of Rejects
Name
Phone
Position

D DC Failure
D Short
DOpen
D Power Drain
D Input Level
Pin Number
D ACFailure
Power Supply Voltages = ___ V
Input Voltages VIH = _ _ _ V
Pin Number_ _ _
Failing characteristics

D Leakage
D Output Level

VIL= _ _ _ V

D RAM and ROM Failures (ROM failures must be
returned with a good master unit if failure
analysis is requested).
Address of Failing Location
Describe Pattern Used (If not standard
patterns, give very complete description
including address sequence).

Include timing diagrams and circuit schematic if available.
ROM Programmer Used (If purchased
unprogrammed)

Conformal Coating (Mfgr/Model)

Additional Comments:

FIGURE 7. PFAST ACTION REQUEST

9-17

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Harris Reliability
INSTRUCTIONS FOR COMPLETING PFAST ACTION REQUEST FORM
The purpose of this form is to help us provide you with a more accurate, complete, and timely response to failures which may occur.
Accurate and complete information is essential to ensure that the appropriate corrective action can be implemented. Due to this need for
accurate and complete information, requests without a completed PFAST Action Request form will be returned.
Source of Problem:
This section requests the product flow leading to the failure. Mark an 'X' in the appropriate boxes up to and including the step which
detected the failure. Also mark an 'X' in the appropriate box under ''ARE RESULTS REPRESENTATIVE OF PREVIOUS LOTS?" to
indicate whether this is a rare failure or a repeated problem.
Example 1. No incoming electrical test was performed; the units
were installed onto boards; the boards functioned correctly for two
hours and then 1 unit failed. The customer rarely has a failure due
to the Harris device.

1.

SOURCE OF PROBLEM

SOURCE OF PROBLEM

(Enter the. se.quence of events in the. bozu provided)

(Enter the sequence of events in the. bOXN provided)

1.

VISUAL/MECHANICAL
a

2.

Example 2. 100 out of the 500 units shipped were tested at incoming and all passed. The units were installed into boards and the
boards passed. The boards were installed into the system and the
system failed immediately when turned on. There were 3 system
failures due to this part. The customer frequently has failures of
this Harris device. The 3 units were not retested at incoming.

DESCRIBE

iii

INcOMING TEST
a

NOT PERFORMED

2. INcoMING TEST

100% TEsmo
aSAMPLETEsrEo
No. TESTED _ _ _ No. OF REJECTS _ _ _

a

ARE RESUI.lS REPRESENTATIVE OF PREVIOUS LOlS?
a

3.

YES

III
3.

a

ARE RESULlS REPRESENTATIVE OF PREVIOUS LOlS?

MIN. _ _"C

III

111m

4.

LOCATION

AVE.

__·c

NO

III

YES

III

NO

ARE RESUI.lS REPRESENTATIVE OF PREVIOUS LOlS?

FIELD FAILURE
FAILED AFTER _ _ _ HOIrnS OPERATION
ESTIMATED FAILURE RATE _ _ _ % PER _ _ _' _
END USER

a

WAS UNIT RETESTED AT INCOMING INSPECTIoN?

111m

YES

YES

IN l'ROcESsiMANuFACTURlNO FAILURE
SYSTEM TEST
How MANY UNIlS FAILED? _ _3
__
FAILED AFTER _ _0__ HOIrnS OF TESTING

WAS UNIT RETESTED AT INCOMING INSPECTION?

a

NOT PERFORMED

SAMPLE TEsrEo
~ No. OF REJECTS _0
__

III BOARD TEST

a SYSTEM TEsT
How MANY UNIlS FAILED? _ _I__
FAILED AFTER _ _2__ HOURS OF TESTING
YES

a

III

ARE RESUI.lS REPRESENTATIVE OF PRIlVIOUS LOlS?

III BOARD TEs-r

4.

100% TESTED
No. 'TESTED

am

INl'ROcESsiMANuFACTURlNG FAILURE

a

VISUAL!.MECHANICAL
aDESCffiBE _ _ _ _ _ _ _ _ _ _ _ _ __

YES

END USER

MAx._ _"C

a

NO

FIELD FAILURE
FAILED AFTER _ _ _ HOIrnS OPERATION
ESTIMAmo FAILURE RATE _ _ _% PER _ _ __

MIN. _ _·C

LocATION
AVE. _ _·C
MAx.-~-==:-:·C::--

~.01HER_~--------------

5. 01HER

Action Requested by Customer:
This section should be completed with the customer's expectations. This information is essential for an appropriate response.
Reason for Electrical Reject:
This section should be completed if the type of failure could be identified. If this information is contained in attached customer correspondence there is no need to transpose onto the PFAST Action Request form.

PFAST REQUIREMENTS
The value of returning failing products is in the corrective actions that are generated. Failure to meet the following requirements can
cause erroneous conclusion and corrective action; therefore, failure to meet these requirements will result in the request being returned.
Contact the local PFAST Coordinator if you have any questions.
Units with conformal coating should include the coating manufacturer and model. This is requested since the coating must be 'removed in
order to perform electrical and hermeticity testing.
I. Units must be returned with proper ESO protection (ESO-safe shipping tubes within shielding boxlbag or inserted into condu'ctive
foam within shielding boxlbag). No tape, paper bags, or plastic bags should be used. This requirement ensures that the devices are not
damaged during shipment back to Harris.
2. Units must be intact (lid not removed and at least part of each package lead present). This is a requirement since the parts must be intact in
order to perform electrical test. Also, opening the package can remove evidence of the cause of failure and lead to an incorrect conclusion.
3. Programmable parts (ROMs, PROMs, UVEPROMs, and EEPROMs) must include a master unit with the same pattern. This requirement is to provide the pattern so all failing locations can be identified. A master unit is required if a failure analysis is requested.
FIGURE 7. PFAST ACTION REQUEST (ContInued)

9-18

Harris Reliability
Product Analysis Lab
The Product Analysis Laboratory capabilities and charter
encompass the isolation and identification of failure modes
and mechanisms, preparing comprehensive technical reports,
and assigning appropriate corrective actions. The primary
activities of the Product Analysis Lab are electrical
verification/characterization
of the
failure,
package
inspection/analysis, die inspection/analysis, and circuit
isolation/probing. A variety of tools and techniques have been
developed to ensure the accuracy and integrity of the product
analysis. This section lists some of the tools and techniques
that are employed during a typical analysiS.
The electrical verification/characterization of devices failing
electrical parameters is essential prior to performing an
analysis. The information obtained from the electrical
verification provides a direction for the analysis efforts. The
following electrical verification/characterization equipment
may be used to obtain electrical data on a device:
• ASIC Verification System
• Analog Test System
• Curve Tracer

• Mixed SignalfTelecom
Test System

• Optical inspection microscopes
• Package opening tools and techniques

• Emission microscope
• Scanning electron microscopes - SEM
The final step of circuit isolation is ready to be performed
when an area of the circuit has been identified as the source
of the problem through one of the previous analysis efforts.
Circuit analysis is performed using the follOWing probing and
isolation tools:
• Mechanical probing
• Laser cutter and isolation
• Cross sectioning and chemical deprocessing

Prior to die level analysis, package inspection and analysis
are performed. These steps are performed routinely since
valuable data may not be obtainable once the package is
opened. The package inspection and analysiS may require the
use of some of the following lab equipment:

• C-mode Scanning Acoustic Microscope (C-SAM)

• Optical microscopes
• Liquid crystal

• E-beam probing

• Parametric Analyzer

• X-ray

Once the device has been opened, die inspection and
analysis can be performed. Depending on the type of failure,
several tools and techniques may be used to identify the
failure mechanism. Usually the faster and easier to use
operations are performed first in an attempt to expedite' the
analysis. The list of equipment and techniques for performing
die inspection and analysis is as follows:

A typical analysis flow is shown in the Figure 8 below. The
exact analysis steps and sequence are determined as the
situation dictates. For the analysis to be conclusive, it is
essential that the failure mechanism correlates to the initial
product failure conditions. Some failure mechanisms require
elemental and chemical analysis to identify the root cause
within the manufacturing process. Elemental and chemical
analysis tasks are sent to the Analytical Services Lab for
further evaluation.
The results of each analysis are entered into a computer data
base. This data base is used to search for specific types of
problems, to identify trends, and to verify that the corrective
actions were effective.

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NON-DESTRUCTIVE

DESTRUCTIVE
FIGURE 8. ANALYSIS SEQUENCE

9-19

Harris Reliability
Analytical Services Laboratory

MICROBEAM LABORATORY

Chemical and physical analysis of materials and processes is
an integral part of Harris' Total Quality/Continuous
Improvement efforts to build reliability into processes and
products. Manufacturing operations are supported with realtime analyses to help maintain robust processes. Analyses
are run in cooperation with raw material suppliers to help them
provide controlled materials in dock-ta-stock procurement
programs.

I

I

ELECTJION
BEM!

X-RAY
ANALYSIS

Harris facilities, engineering, manufacturing, and product
assurance are supported by the Analytical Services
Laboratory. Organized into chemical or microbeam analysis
methodology, staff and instrumentation from both labs
cooperate in fully integrated approaches necessary to
complete analytical studies.
The department also maintains ongoing working
arrangements with commercial laboratories, universities, and
equipment manufacturers to obtain any materials analysis in
cases where instrumental capabilities are not available in our
own facility.
FIGURE 9. MICROBEAM LABORATORY

Figures 9 and 10 show the capabilities of each area.
CHEMISTRY LABORATORY
SPECTJIOSCOPV

SEPARATION METHODS

I
EMISSION
SPECTROGRAPH

FOURIER TRANSFORM
INFRARED

SPECTJIOPH~METER

UVVISIBLE

SPECTROPH~METER

THERMAL ANALYSIS

PHYSICAL TESTING

I

I

I

GAS
CHROMATOGRAPH

DIFFERENTIAL
SCANNING
CALORIMETER

PROFILOMETERS

I

I

I

ION
CHROMATOGRAPH

THERMOGRAVIMETRIC
ANALYZER

MICROHARDNESS

I

I

I

GAS
CHROMATOGRAPH
MASSSPECTJIOMETER

THERMOMECHANICAL
ANALYZER

VISCOMETRY

I
ORGANIC CARBON
ANALYZER

I

HzO, ~ AND THC

SCANNING PROBE
MICROSCOPY

ANALVZERS

I
MASS
SPECTROMETER

SPECIALIZED ANALYSIS

MASSSPECTJIOMETER
(PACKAGE GAS
ANALYSIS)

I
ELECTROLmc METAL
ANALYSIS TOOL

ATOMIC ABSORPTlON

SPECTROPH~METER

I
FLAME
AA

I
GRAPHITE
FURNACE

FIGURE 10. CHEMISTRY LABORATORY

9-20

Harris Reliability
Reliability Fundamentals and Calculation
of Failure Rate

where,

/.. = failure rate in FITs (Number fails in t 09 device hours)
~ = number of distinct possible failure mechanisms
k = number of life tests being combined

Table 9 defines some of the more important terminology
used in describing the lifetime of integrated circuits. Of prime
importance is the concept of "failure rate" and its calculation.

xi

Failure Rate Calculations
Since reliability data can be accumulated from a number of
different life tests with several different failure mechanisms, a
comprehensive failure rate is desired. The failure rate
calculation can be complicated if there are more than one
failure mechanism in a life test, since the failure mechanisms
are thermally activated at different rates The equation below
accounts for these considerations along with a statistical
factor to obtain the upper confidence level (UCl) for the
resulting failure rate.

~

A=

Xi

I

Mx 10 9

x-~-

k

i=1

I

TDHjAFij

j=1

LXi
i=1

=

number of failures for a given failure mechanism
i; 1, 2, ... ~

TDH j

= Total device hours of test time (unaccelerated) for Life Test

AF ij

= Acceleration factor for appropriate failure mechanism i = 1,

j,j; 1, 2, 3, ... k
2, ... k

M=

x2(a,2r+2)/2

where,

X2 = chi square factor for 2r + 2 degrees of freedom
r = total number of failures (I: xi)

a; risk associated with UCL;
i.e. a = (1 OO-UCL(%))/l 00
In the failure rate calculation, Acceleration Factors (AFij ) are
used to derate the failure rate from the thermally accelerated
life test conditions to a failure rate indicative of actual use
temperature. Although no standard exists, a temperature of
55°C has been popular. Harris Semiconductor Reliability
Reports will derate to 55°C and will express failure rates at
60% UCL. Other derating temperatures and UCls are
available upon request.

TABLE 9. FAILURE RATE PRIMER
DEFINITIONS/DESCRIPTION

TERMS

Failure Rate A

Measure of failure per unit of time. The early life failure rate is typically higher, decreases slightly,
and then becomes relatively constant over time. The onset of wear-out will show an increasing failure rate, which should occur well beyond useful life. The useful life failure rate is based on the exponentiallife distribution.

FIT (Failure In Time)

Measure of failure rate in 109 device hours; e.g., 1 FIT = 1 failure in 109 device hours, 100 FITS;
100 failure in 109 device hours, etc.

Device Hours

The summation of the number of units in operation multiplied by the time of operation.

MTIF (Mean Time To Failure)

Mean of the life distribution for the population of devices under operation or expected lifetime of an
individual, MTIF =l/A, which is the time where 63.2% of the population has failed. Example: For
A = 10 FITS (or 10 E-9/Hr.), MTIF = llA. = 100 million hours.

Confidence Level (or Limit)

Acceleration Factor (AF)

Probability level at which population failure rate estimates are derived from sample life test: 10 FITs
at 95% UCL means that the population failure rate is estimated to be no more that 10 FITs with 95%
certainty. The upper limit of the confidence interval is used.
A constant derived from experimental data which relates the times to failure at two different stresses.
The AF allows extrapolation of failure rates from accelerated test conditions to use conditions.

9-21

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Harris Reliability
Acceleration Factors

Activation Energy

Acceleration factor is determined from the Arrhenius
Equation. This equation is used to describe physiochemical
reaction rates and has been found to be an appropriate model
for expressing the thermal acceleration of semiconductor
failure mechanisms.

The Activation Energy (Ea) of a failure mechanism is
determined by performing at least two tests at different levels
of stress (temperature and/or voltage). The stresses will
provide the time to failure (tf) for the two (or more) populations
thus allowing the simultaneous solution for the activation
energy as follows:

AF

~ EXP[~(_l__ ,.---,-l_)~
k T USE

T STRESS

In

~

+

Ea

~

= Acceleration Factor

=
k=

Ea

C

By subtracting the two equations and solving for the activation
energy, the following equation is obtained:

where,
AF

~

(ttl)

k[ln(t f1 ) - I n(tf2 ) 1

Ea~

Thermal Activation Energy (See Table 10)
Boltzmann's Constant (8.63 x lO-S eVf'K)

(1/T1-1/T2)

where,

Both Tuse and Tstress (in degrees Kelvin) include the internal
temperature rise of the device and therefore represent the
junction temperature.

Ea
k
T 1, T 2

= Thermal Activation Energy (See Table 10)
=

Boltzmann's Constant (8.63 x lO- S eVf'K)

= Life test temperatures in degrees Kelvin

TABLE 10. FAILURE MECHANISM
FAILURE
MECHANISM

ACTIVATION
ENERGY

SCREENING AND
TESTING METHODOLOGY

CONTROL METHODOLOGY

Oxide Defects

0.3eV . O.SeV

High temperature operating life (HTOL) and
voltage stress. Defect density test vehicles.

Statistical Process Control of oxide parameters,
defect density control, arid voltage stress testing.

Silicon Defects
(Bulk)

0.3eV - O.SeV

HTOL and voltage stress screens.

Vendor statistical Quality Control programs, and
Statistical Process Control on thermal processes.

Highly accelerated stress testing (HAST)

Passivation dopant control, hermetic seal control,
improved mold compounds, and product handling.

Temperature cycling, temperature and
mechanical shock, and environmental
stressing.

Vendor Statistical Quality Control programs,
Statistical Process Control of assembly processes, proper handling methods.

Test vehicle characterizations at highly
elevated temperatures.

Design ground rules, wafer process statistical
process steps, photoresist,
metals and
passivation.

Corrosion

0.4SeV

Assembly
Defects

O.SeV - 0.7eV

Electromigration
- AI Line
- Contact

0.6eV
0.geV

Mask Defects/Photoresist
Defects

0.7eV

Mask FAB comparator, print checks, defect
density monitor in FAB, voltage stress test
and HTOL.

Clean room control, clean mask, pellicles,
Statistical Process Control of photoresist/etch
processes.

Contamination

1.0eV

C-V stress at oxidefinterconnect, wafer FAB
device stress test and HTOL.

Statistical Process Control of C-V data, oxide!
interconnect cleans, high integrity glassivation
and clean assembly processes.

Charge Injection

1.3eV

HTOL and oxide characterization.

Design ground rules, wafer level Statistical
Process Control and critical dimensions for
oxides.

9-22

Harris Semiconductor
---------==
.
- ---- -====--- -~ -~ - -=
- -

No. TB52

Harris Digital

January 1994

Electrostatic Discharge Control:
A Guide To Handling Integrated Circuits
This paper discusses methods and materials recommended
for protection of les against ESD damage or degradation
during manufacturing operations vulnerable to ESD exposure. Areas of concern include dice prep and handling, dice
and package inspection, packing, shipping, receiving, testing, assembly and all operations where les are involved.

In addition to personnel grounding, areas where work is being
performed with les, should be equipped with an ionized air
blower. Ionized air blowers force positive and negative ions simultaneously over the work area so that any nonconductors that are
near the work surface would have their static charge neutralized
before it would cause device damage or degradation.

All integrated circuits are sensitive to electrostatic discharge
(ESD) to some degree. Since the introduction of integrated
circuits with MOS structures and high quality junctions, safe
and effective means of handling these devices have been of
primary importance.

Relative humidity in the work area should be maintained as
high as practical. When the work environment is less than 40%
RH, a static build-up condition can exist on nonconductors
allowing stored charges to remain near the les causing possible static electricity discharge to ICs.

If static discharge occurs at a sufficient magnitude, 2kV or
greater, some damage or degradation will usually occur. It has
been found that handling equipment and personnel can generate static potentials in excess of 1OkV in a low humidity environment; thus it becomes necessary for additional measures
to be implemented to eliminate or reduce static charge. Avoiding any damage or degradation by ESD when handling
devices during the manufacturing flow is therefore essential.

Integrated circuits that are being shipped or transported require
special handling and packaging materials to eliminate ESD
damage. Dice or packaged devices should be in conductive
carriers during all phases of transport and handling. Leads of
packaged devices can be shorted by tubular metallic carriers,
conductive foam or foil.

ESD Protection and Prevention Measures

Do's and Don'ts for Integrated
Circuit Handling
Do's

One method employed to protect gate oxide structures is to
incorporate input protection diodes directly on the monolithic
Chip. However, there is no completely foolproof system of
chip input protection in existence in the industry.
In areas where les are being handled, certain equipment
should be utilized to reduce the damaging effects of ESD.
Typically, equipment such as grounded work stations, conductive wrist straps, conductive floor mats, ionized air blowers and conductive packaging materials are included in the
Ie handling environment. Any time an individual intends to
handle an Ie, in any way, they must insure they have been
grounded to eliminate circuit damage.
Grounding personnel can, practically, be performed by two
methods. First, grounded wrist straps which are usually
made of a conductive material, such as Velostat or metal. A
resistor value of 1 megohm (1/2 watt) in series with the strap
to ground completes a discharge path for ESD when the
operator wears the strap in contact with the skin. Another
method is to insure direct physical contact with a grounded,
conductive work surface. .
This consists of a conductive surface like Velostat, covering
the work area. The surface is connected to a 1 megohm (1/2
watt) resistor in series with ground.

Copyright

Do keep paper, nonconductive plastic, plastic foams and
films or cardboard off the static controlled conductive bench
top. Placing devices, loaded sticks or loaded burn-in boards
on top of any of these materials effectively insulates them
from ground and defeats the purpose of the static controlled
conductive surface.
Do keep hand creams and food away from static controlled
conductive work surfaces. If spilled on the bench top, these
materials will contaminate and increase the resistivity of the
work area.
Do be especially careful when using soldering guns around
conductive work surfaces. Solder spills and heat from the gun
may melt and damage the conductive mat.
Do check the grounded wrist strap connections daily. Make certain they are snugly fitted before starting work with the product.
Do put on grounded wrist strap before touching any devices.
This drains off any static buildup from the operator.
Do know the ESD caution symbols.
Do remove devices or loaded sticks from shielding bags only
when grounded via wrist strap at grounded work station. This
also applies when loading or removing devices from the antistatic
sticks or the loading on or removing from the burn-in boards.

© Harris Corporation 1996
9-23

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Tech Brief 52
Do wear grounded wrist straps in direct contact with the bare
skin never over clothing.

Don't unload stick on a metal bench top allowing rapid discharge of charged devices.

Do use the same ESD control with empty burn-in boards as
with loaded boards if boards contain permanently mounted
ICs as part of driver circuits.

Don't touch leads. Handle devices by their package even
though grounded.

Do insure electrical tast equipment and solder irons at an
ESD control station are grounded and only uninsulated
metal hand tools be used. Ordinary plastic solder suckers
and other plastic assembly aids shall not be used.
Do use ionizing air blowers in static controlled areas when the
use of plastic (nonconductive) materials cannot be avoided.
Don'ts
Don't allow anyone not grounded to touch devices, loaded
sticks or loaded burn-in boards. To be grounded they must
be standing on a conductive floor mat with conductive heel
straps attached to footwear or must wear a grounded wrist
strap.
Don't touch the devices by the pins or leads unless
grounded since most ESD damage is done at these pOints.
Don't handle devices or loaded sticks during transport from
work station to work station unless protected by shielding
bags. These items must never be directly handled by anyone
not grounded.
Don't use freon or chlorinated cleaners at a grounded work area.
Don't wax grounded static controlled conduc::tive floor and
bench top mats. This would allow buildup of an insulating
layer and thus defeating the purpose of a conductive work
surface.

Don't allow plastiC "snow or peanut" polystyrene foam or
other high dielectric materials to come in contact with
devices or loaded sticks or loaded burn-in boards.
Don't allow rubber/plastic floor mats in front of static controlled work benches.
Don't solvent-clean devices whim loaded in antistatic sticks
since this will remove antistatic inner coating from sticks.
Don't use antistatic sticks for more than one throughput process. Used sticks should not be reused unless recoated.

Recommended Maintenance Procedures
Daily
Perform visual inspection of ground wires and terminals on
floor mats, bench tops, and grounding receptacles to ensure
that proper electrical connections via 1 megohm resistor (1/2
watt) exist.
Clean bench top mats with a soft cloth or paper towel dampened with a mild solution of detergent and water.
Weekly
Damp mop conductive floor mats to remove any accumulated dirt layer which causes high resistivity.
Annually
Replace nuclear elements for ionized air blowers.

Don't touch devices or loaded sticks or loaded burn-in
boards with clothing or textiles even though grounded wrist
strap is worn. This does not apply if conductive coats are
worn.

Review ESD protection procedures and equipment for
updating and adequacy.

Don't allow personnel to be attached to hard ground. There
must always be 1 megohm series resistance (1/2 watt
between the person and the ground).

The figure below shows an example of a work bench properly equipped to control electrostatic discharge. Note that
the wrist strap is connected to a 1 megohm resistor. This
resistor can be omitted in the setup if the wrist strap has a 1
megohm assembled on the cable attached.

Don't touch edge connectors of loaded burn-in boards or
empty burn-in boards containing permanently mounted
driver circuits when not grounded. This also applies to burnin programming cards containing ICs.

Static Controlled Work Station

R

WRIST STRAP GROUND
LEAD IS ATTACHED TO
CONDUCTIVE BENCH TOP
ESD WARNING SYMBOLS

~-rZzZZZZ:zzzj21

CONDUCTIVE WRIST
STRAP
TOP

DISSIPATIVE FLOOR MAT

GROUND, I.e. COLD WATER
PIPE OR EQUIVALENT

9-24

R=1 MEGOHM

LI NEA
~

10

~--

APPLICATION NOTES, ABSTRACTS AND SPICE MODEL LISTING

PAGE
APPLICATION NOTE ABSTRACTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-3
SPICE MODEL LISTING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-6
APPLICATION NOTES
AN013.1

Everything You Always Wanted To Know About The ICL8038 .......................... . 10-7

AN053.1

The ICL7650S: A New Era in Glitch-Free Chopper Stabilized Amplifiers .................. . 10-11

AN514.1

The HA-2400 PRAM Four Channel Operational Amplifier.............................. . 10-25

AN519.1

Operational Amplifier Noise Prediction (All Op Amps) ................................ . 10-32

AN548.1

A Designers Guide for the HA-5033 Video Buffer .................................... . 10-35

AN551.1

Recommended Test Procedures for Operational Amplifiers ............................ . 10-47

AN6668.1

Applications of the CA3080 and CA3080A High-Performance
Operational Transconductance Amplifiers ....................•...................... 10-52

AN9202

Using the HFAll00, HFAl130 Evaluation Fixture .................................... . 10-69

AN9305

HA5020 Operational Amplifier Feedback Resistor Selection ........................... . 10-71

AN9313.1

Circuit Considerations In Imaging Applications (HA-2546, HA-5020, HA-5033, HI-5700) ..... . 10-73

AN9314.1

Harris UHF Pin Drivers .......•................................................. 10-81

AN9315.1

RF Amplifier Design Using HFA3046, HFA3096, HFA3127, HFA3128 Transistor Arrays .......... . 10-85

AN9317.1

Micropower Clock Oscillator and Op Amps Provide System
Control for Battery Operated Circuits (HA7210) ..................................... . 10-89

AN9334.1

Improving Start-up Time at 32kHz for the HA7210 Low Power Crystal Oscillator ............ . 10-91

AN9415.3

Feedback, Op Amps and Compensation •........•..•.............................•. 10-93

AN9420.1

Current Feedback Amplifier Theory and Applications ................................. . 10-105

AN9502.1

Oscillator Produces Quadrature Waves (HA5025) ................................... . 10-112

AN9503.1

Low Output Impedance MUX (HA5022) ........................................... . 10-114

AN9507.1

Video Cable Drivers Save Board Space, Increase Bandwidth (HFAll12, HFAll14) ......... . 10-115

10-1

IUJ

-::::i

UJ..J
Ww

00
zO
Il.:il
Il.W

«0
a:::

UJ

Application Notes, Abstracts and Spice Model Listing

(Continued)

PAGE
AN9508.1

Video Multiplexer Delivers Lower Signal Degradation (HA5024). . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-117

AN9510.1

Basic Analog for Digital Designers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-118

AN9513

Component Video Sync Formats (HFA 1103) ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-124

AN9514

Video Amplifier with Sync Stripper and DC Restore (HFA 1103) . . . . . . . . . . . . . . . . . . . . . . . . .. 10-127

AN9515.1

Multiplier Improves the Dynamic Range of Echo Systems (HA-2556, HA-5177) ............. 10-129

AN9516.1

Adjustable Bandpass or Bandreject Filter (HA-2841) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-131

AN9523

Evaluation Programs for SPICE Op Amp Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-133

AN9524

HFA1212 Dual Video Buffer Forms Differential Line Driver/Receiver ...................... 10-143

AN9528.1

900MHz Down Converter Consumes Little Power (HFA3101) ........................... 10-144

AN9536.1

PSPICE Performs Op Amp Open Loop Stability Analysis (HA5112). . . . . . . . . . . . . . . . . . . . . .. 10-145

AN9621.1

Comparison of Current Feedback Op Amp SPICE Models (HA5013) ....................... 10-147

AN9641

High-Frequency VGA Has Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-154

AN9653

Use and Application of Output Limiting Amplifiers (HFAll15, HFAl130, HFAl135) .......... 10-156

TECH BRIEF
TB334

Guidelines for Soldering Surface Mount Components to PC Boards . . . . . . . . . . . . . . . . . . . . . . .. 10-161

10-2

. - - - - - - - Application Note Abstracts - - - - - - - - ,
AN#
007

013

040
053

TITLE
Using the 8048/8049
Monolithic Log-Anti-Log
Amplifiers
Everything You Always
Wanted to Know About the
8038
A Precision Four Quadrant
Multiplier - The 8013

ABSTRACT
Describes in detail the operation of the ICL8048 logarithmic amplifier, and its
counterpart, the ICL8049 anti-log amp.
This note includes 17 of the most asked questions regarding the use of the ICL8038.

Describes, in detail, the operation of the ICL8013 analog multiplier. Included are
multiplication, division, and square root applications.

The ICL7650 - A New Era in
Glitch-Free Chopper
Stabilizer Amplifiers
A Simple Comparator Using
The HA-2620

A brief discussion of the internal operation of the ICL7650, followed by an extensive
application section including amplifiers, comparators, log-amps, pre-amps, etc.

514

The HA-2400 PRAM
Four Channel Operational
Amplifier

HA-2400 Programmable Analog Microcircuit description, frequency compensation,
applications (analog multiplexer, non-inverting programmable gain amplifier, inverting
programmable gain amplifier, programmable attenuator, programmable addersubtractor, phase selector, phase detector, synchronous rectifier, balanced modulator,
integrator, ramp generator, track and hold, sample and hold, sine wave oscillator,
multivibrator, active filter, programmable power supply, comparator, multiplying D/A
converter).

515

Operational Amplifier
Stability: Input Capacitance
Considerations
Applications of a Monolithic
Sample and Hold Amplifier

Input capacitance and stability, capacitive feedback compensation, guidelines for
compensation requirements.

519

Operational Amplifier
Noise Prediction

Noise model and equations, procedure for computing total output noise, example,
broadband noise measurement, spot noise prediction techniques, typical spot noise
curves, popcorn noise discussion.

525

HA-5190/5195 Fast Settling
Operational Amplifier

Internal schematiC, prototyping considerations, frequency compensation, performance
enhancement methods, applications.

526

Video Applications for the

Video applications, video response tests, SIN ratio measurements, power supply
requirements temperature considerations, design hints,' prototyping tips, RF AGO
amplifier, DC gain controlled video amplifier.

509

517

HA-5190/5195

538

540

541

544

546

548

Performance characteristics,
methods.

application schematics,

output parameter control

General Sample and Hold information and fourteen specific applications, including
filtered Sample and Hold DAC de-glitcher, Integrate-Hold-Reset, gated op amp, etc.

Monolithic Sample/Hold
Combines Speed and
Precision
HA-5170 PreCision Low
Noise JFET Input Operation
Amplifier

Description and electrical specifications for the HA-5320 Sample/Hold Amplifier,
explanation of errors sources, and HA-5320 applications.

Using HA-2539 or HA-2540
Very High Slew Rate,
Wideband Operational
Amplifier

Prototyping conSiderations, output short circuit protection, offset voltage adjustment,
frequency compensation, composite amplifier scheme, DC error reduction, boosting
output current, increasing output signal swing, cascade amplifier, video gain block, high
frequency oscillator, wideband signal splitter.

zO

Micropower Op Amp Family,
HA-514X

Operation, noise performance, applications (remote sensor loop transmitter, charge
pool power supply, low power microphone preamplifier, AGO with squelch control, Wein
bridge oscillator, bar code scanner, monostable multivibrator).

c::
Ul

A Method of Calculating HA2625 Gain Bandwidth
Product vs Temperature
A Designer's Guide for the
HA-5033 Video Buffer

A method of calculating Gain Bandwidth product performance versus temperature for
the HA-2625 Op Amp.

Internal design and technology, JFET noise discussion, trimming of offset voltage,
single op amp Instrumentation Amplifier, sine wave oscillator, high impedance
transducer interface, current source/sink and current sense circuits.

Operation, video performance, video parameter specifications, Y parameters,
applications (flash converter pre-driver, coaxial line driver, video gain block, high speed
sample and hold, audio drivers, crystal oscillator).

NOTE: Bold type indicates Appnote Is included in this data book.
See pages i, Ii for information on Ordering Literature

10-3

I;;
-::J
Ul-l

Ww

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Application Note Abstracts
AN#
550

551

552

553

554

TITLE
Using the HA-2541

Recommended Test
Operational amplifier test procedures for offset voltage, bias current, offset current,
Procedures for Operational power supply rejection ratio, common mode rejection ratio, output voltage swing, output
Amplifiers
current, open loop gain, slew rate, full power bandwidth, transient response, settling
time, GBp, phase margin, noise voltage and current, and channel separation.
Using the HA-2542
Prototyping guidelines, thermal considerations and heat sinking, performance
enhancements, applications (multi-channel security system, unbalanced coaxial driver,
flash converter driver, programmable power supply, bridge load driver, high current
stage, differential line driver, DC motor speed control).
Using the HA-5147/51371
Construction and operation, low noise design applications (instrumentation amplifier
5127
bridge sensor, multiplexer, precision threshold detector, audio driver, NAB amplifier,
multivibrator, programmable gain stage, log amp, profeSSional mixer).
Low Noise Family
HA-5101/5102l5104/51121

5114
556

ABSTRACT
Prototyping guidelines, thermal considerations and heat sinking, performance
enhancements, applications (Wein bridge oscillator, high power gain stage, video stage
with clamp, multiplexer/demultiplexer, disk drive write amplifier, gain programmable
amp, composite amp).

Low noise design, operation, applications (Electronic scales, programmable attentuator,
Baxandal circuit, RIAA amplifier, NAB preamplifier, microphone amplifier, standard and
simple biquads, professional mixer.
Thermal management equations and curves indicating areas of VOUT and lOUT for safe
operation. Also, the effects of packaging and heat sinking are examined.

5290

Thermal Safe-OperatingAreas for High Current Op
Amps
General Purpose Op Amps

5296

CA3018

Transistor Array

5337

CA3028

RF amplifiers in the HF and VHF ranges.

5766

CA3020

Multipurpose wideband power amplifiers

6048

CA3094

Programmable power switch/amplifier.

6077

CA3094

OTA with power capability.

6247

CA3126

Chroma processing IC using sample and hold circuit techniques.

6257

CA3089

FM IF Subsystem

6386

CA3130

Understanding BiMOS op amps.

6459

CA3130

Why and how to use the BiMOS op amp.

6472

CA3126

A chrominance demodulator IC with dynamic flesh correction.

6668

CA30800TA

What is an Operational Transconductance Amplifier (OTA)? Circuit description plus
numerous application examples.

6669

CA3240

BiMOS op amp mates directly to system sensors.

6732

Noise Measurement

Measurement of burst noise and "popcorn" noise in ICs.

6818

CA3280 Dual OTA

OTA simplifies complex analog designs.

Discusses various uses of op amps.

7127

CA3420

BiMOS amplifier circumvents low voltage limitations.

8636

Video Devices

Discuss,es advanced video speed switches, multiplexers, cross points and buffer
amplifiers.

8707

CA3450

Single chip video line driver-high speed op amp.

8742

CD22402

Sync Generator

8811

CA5470

BiMOS-E process enhances quad op amp.

9202

Using the HFA1100,
HFA1130 Evaluation
Fixture
HA5020 Operational
Amplifier Feedback
Resistor Selection
Circuit Considerations In
Imaging Applications

Uses for the HFA 11 XX Evaluation Board, and performance examples.

Discusses the analog input section of an image processing system. Presents video
formats, analog circuit design conSiderations, etc.

Harris UHF Pin Drivers

Description, use of, and applications for the HFA5250 and HFA5251.

9305

9313
9314

Discusses a method for calculating the optimum feedback resistor value when using a
current feedback amplifier at closed loop gains grater than 1.

NOTE: Bold type indicates Appnote is included in this data book.
See pages I, Ii for information on Ordering Literature

10-4

Application Note Abstracts
AN#
9315

9317

9334

9415
9420
9502
9503
9507

9508
9510
9513
9514
9515

9516
9523

TITLE
RF Amplifier Design Using
HFA3046130961312713128
Transistor Arrays
Micropower Clock
Oscillator and OP Amps
Provide System Control for
Battery Operated Circuits
Improving Start-up Time at
32kHz for the HA721 0 Low
Power Crystal Oscillator
Feedback, Op Amps, and
Compensation
Current Feedback
Amplifier Theory
Oscillator Produces
Quadrature Waves
Low Output Impedance
MUX
Video Cable Drivers Save
Board Space, Increase
Bandwidth
Video Multiplexer Delivers
Lower Signal Degradation

ABSTRACT
Sample RF amplifier designs including layout techniques and performance results.

Using HA721 0 in a control circuit to switch a battery powered digital system from sleep
mode (ultra low power) to active when an external event (sound, pressure, etc.) is
detected.
Techniques to speed up the oscillator start-up time when operating the HA7210 at low
power settings.
Basic feedback theory and op amp fundamentals.
In depth analysis of Current feedback amplifiers.
Using a quad op amp to implement an RC oscillator producing quadrature outputs.
Amplifiers with output disable functions implement muxes to drive low impedance loads.
Limitations of long cables on video circuit performance, and use of novel video buffers
to counteract cable limitations and save board space.
Implementation of a 4:1, cable driving, video mux using quad op amps featuring an
output disable function.

Basic Analog for Digital
Designers
Component Video Sync
Formats
Video Amp with Sync
Stripper and DC Restore
Multiplier Improves the
Dynamic Range of Echo
Systems (HA-2556,
HA-5177)
Adjustable Bandpass or
Bandreject Filter (HA-2841)

Describes an active filter with easily adjusted center frequency, symmetrical skirts, and
40dB of attenuation (band reject) or gain (band pass).

Evaillation Programs for
SPICE Op Amp Models

Discussion of standard PSPICE programs for evaluating op amp models. Programs are
given to simulate AC and transient responses as well as DC performance.

Analog refresher for engineers who haven't worked with analog circuits since college.
Discussion of video sync signals and sync formats.
Use of the H FA 1103 as a component video, sync stripping, amplifier.
Implementation of a time-gain amplifier using an analog multiplier.

9524

HFA1212 Dllal Video Buffer Using a novel dual buffer to implement differential functions minimizes the number of
Forms Differential Line
external components required.
Driver/Receiver
9528
900MHz Down Converter
Using the HFA3101 transistor array to implement a battery powered 900MHz down
Consumes Little Power
converter.
(HFA3101)
PSPICE Performs Op Amp Using a simulator to perform a stability analysis makes a difficult task easier.
9536
Open Loop Stability
Analysis
9621
Comparison of Current
All op amp macro models aren't equal. This Application Note compares models from
Feedback Op Amp Spice
several vendors.
Models
9641
High-Frequency VGA Has
Utilizing the HFA3102 to implement a Variable Gain amplifier with the HI5731 providing
Digital Control
digital gain control.
Use and Application of
9653
Discussion of Input Limiting vs Output Limiting amplifiers. Description of output limiting
Output Limiting Amplifiers circuitry and resultant inaccuracies. Application examples: AID input protection, 2ns T R
(HFA1115, HFA1130,
Comparators, AM Modulator, Soft Clipping Circuit.
HFA1135)
TB334 Guidelines for Soldering
Discussion of the most common techniques for mounting SMDs to PC boards.
Surface Mount
Components to PC Boards

NOTE: Bold type indicates Appnote is included in this data book.
See pages i, ii for information on Ordering literature

10-5

ICJ)

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10-9

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-15V « -10V)

STROBE-TONE BURST GENERATOR

Application Note 013

r--!---!--~"'AMPLITUDE
8038

8038

8

2t----t.:""

8

11

10

11

10

c

c

'-----+-----....- - 0 VFIGURE3A_

FIGURE3B.
FIGURE 3_ SINEWAVE OUTPUT BUFFER AMPLIFIERS

Schematic Diagram
r-T-_-r_~CU~RRrENT~~SO~U~RCES~~_~_ _T-~_ _~r-_~-r~____~__~__T-_ _T-_V+

!.v

"32

s.a

.

II,

nIl 1I2I.:J--+-+-...,

10-10

Harris Semiconductor

----No. AN053.1

---

--

Harris Linear

November 1996

The ICL7650S: A New Era in
Glitch-Free Chopper Stabilized Amplifiers
Author: Peter Bradshaw

Introduction
OpAmps
Historically, the biggest single problem with the application of
op amps has been the input offset voltage. This is indicated
by the fact that almost all important op amps from the !1A741
and LM101 on have offered offset null adjustment pins, special screening to low offset voltage values, and/or internal
Vas trimming (laser or Zener-zap). Also consider the extensive series of specifications devoted to its variability with
temperature, time, common-mode voltage (CMRR), power
supply (PSRR), output voltage (Avad, and sometimes even
down to variation of temperature drift with offset null correction. Contrast this with the treatment afforded one other
Important (error-causing) input parameter, input bias current,
which usually gets lust a specified value under one set of
conditions, a variation over temperature, and a term relating
to its matching between the two inputs. If variation with common-mode voltage, power supply voltage, etc., is covered, it
is generally only in a ''typical curve" buried in the middle of
the data sheet.
The answers to this concern have been many and varied.
Several modules use chopper stabilization. to provide very
low offset voltages, although most of these do not provide
differential inputs and they also have problems with input
frequencies near the chopping rate (see Intermodulation
Effects). The devices are typically bulky and expensive, and
the two-path approach frequently used (Figure 1) tends to
adversely affect settling times; the high-speed path and the
IN -+-*---------------i
y+

~~+

.....--+-·U---+-+OUTPUT

Cc

33PF

y.
y+

·INPUT >-WIr-<~M------jr--;:=~--1~""

6.3Y

' - - - - - - - - -..........""-1~:::t--_-'OY.
o-t.--+-14--o y.
L....ov.;.-< IaICOMP
FIGURE 4. CMOS OP AMP SCHEMATIC (ICL7611 FAMILY)

r-----.---~----_1~----~_1~--_1~----------~-----4Y+

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THRESHOLD o---j N

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.....___-oOUTPUT

~~~g~o-------~----~
TRIGGER

o-------:t------III--~*==_+_--.....,

FIGURE 5. ICM7555n556 CMOS SINGLE AND DUAL TIMERS

10·13

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en

Application Note 053
These devices at once became the best monolithic
amplifiers available in terms of offset voltage (at 511V) and
time and temperature drift. They utilize two internal op amps,
one active while the other auto-zeroes itself into an external
capacitor. Upon commutation, the roles change and the
active op amp uses its capacitor to cancel its offset. Two
capacitors are needed, but the values and characteristics
are not critical. Although offering three orders of magnitude
improvement over the input characteristics of the IJ.A741!
LM101A type, and nearly two orders of magnitude over the
best bipolar devices in offset and drift, the CAZ principle has
some disadvantages. The input current does not exploit the
CMOS capability fully, and there is appreciable spiking at
both the input and output (Figure 8). This can be largely
removed by filtering, but that limits the available bandwidth.

+VIN -8....-1'1r--t---+------oVOUT1
L-~~~----~~Voun

~t------~OSENSE

~1---r===,:"OVSET

~~-~r--------oSHUTDOWN

_----~-....-----~oGND

FIGURE 6. FUNCTIONAL DIAGRAM OF THE ICL7663 CMOS
REGULATOR

+INPUT
OUTPUT
AZ
FIGURE 8. OUTPUT SPIKES DUE TO COMMUTATING
OPERATION

-INPUT

Synthesis
Intersil therefore decided to try to overcome all these
problems by applying the capabilities of CMOS technology
to the principle of the chopper-stabilized amplifier. The result
is the ICL7850, whose Functional Diagram is shown in
Figure 9. The use of a single full-time main amplifier avoids
any output glitches, and input switching glitches are
minimized by careful area- and charge-balancing on the
network of input switches. The chopping operation is
performed by means of a nulling amplifier, which shares one
input with the main amplifier. The other input is switched
alternately between the two main amplifier inputs (Figure
10). When the inputs are shorted, its output drives a null
point on itself, and when the inputs are across those of the
main amplifier, it drives a null point on that amplifier. The two
null points are the back-gates (often called "body
connections") on the mirror transistors of the input stage,
and by bypassing these to the equivalent point on the other
leg with external capacitors, a simple low-leakage automatic
offset null arrangement is achieved. Full differential input
capability is retained, and the impedances on the two inputs
are well balanced. The input stage legs are merged, as
shown in Figure 11, to reduce the input noise and improve
balance and high-frequency CMRR, etc.

+INPUT
OUTPUT
AZ

-INPUT-I+-f--I

~
FIGURE 7. ICL7600J1CL7601 COMMUTATING AUTO-ZERO
(CAZ) OPERATIONAL AMPLIFIER SHOWING TWOCYCLE OPERATION

10-14

Application Note 053
V+

EXTCLKIN

OUTPUT
CLAMP

W

EXT

OSC

OUT

B

A

INPUTS {

OUTPUT

INPUTS{
CEXT

V·

B

A

0----+4--++---.. .
II

..

-.-r CRE'; - Ii - -

FROM NULL AMP
2ND STAGE

CEXT

FIGURE 11. THREE-LEGGED INPUT STAGE (SIMPLIFIED)

l"V
FIGURE 9. FUNCTIONAL DIAGRAM OF ICL7650S

10"V

...........

100"V

'" "- ........
10

MAIN
AMPLIFIER
OUTPUT

100

lK

10K

FREQUENCY (Hz)

"'"

"

lOOK

CI

i

~

~

lmV

0

10mV

!§

~

100mV ~

'>

1M

Vo

FIGURE 10A. NULLING ITSELF
'----....,...TO NULL AMPLIFIER

FIGURE 12. GAIN ROLL-OFF AND INPUT VOLTAGE (MAIN
AMPLIFIER ALONE WITHOUT NULL SYSTEM) VS
FREQUENCY

FIGURE 108. NULLING MAIN AMPLIFIER
FIGURE 10. TWO PHASES OF NULLING OPERATION

The circuit automatically provides correction (at DC) for CMRR,
PSRR, and AVOL, to the same level as for VOS (typically under
1mV), and the IB remains in the low pA area, set by the leakage
of the input switches (also acting as protection diodes) and the
small net charge injection. The latter is doubly-balanced both by
careful device matching and by the excellent recovery of any
residual injection, due to the equipotential nature of the inputs.
The open-loop gainbandwidth product and the slew-rate are set
purely by the main amplifier. The null system time constant is
controlled by the effective gm to the output of the nulling amplifier and the external capacitors, and is readily controlled to be
much longer than the chopping period. In addition, the "injection" of the nulling signal into the first stage of the main amplifier
ensures that the pole-zero match at this cross-over point is no
problem.

10-15

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Application Note 053

Intermodulation Effects
Two residual problems remain with the usual chopperstabilized amplifier circuits. One of these is the
intermodulation between applied signals and the chopping
frequency, as mentioned earlier. This arises because the
main amplifier has finite gain near this frequency, and so
develops a small differential input signal to sustain the
requisite output (distinct from any DC offset voltage). This
signal is, of course, at the signal frequency, and has an
amplitude determined by the gain roll-off characteristics
(Figure 12) and the signal amplitude, and will be seen by the
nulling circuit as an error signal equivalent to an input offset
voltage. This circuit will then attempt to null out the input
signal during the active null time. If the difference in
frequency between the signal and the chopping rate is large
compared to the null circuit time constant, this attempt will
essentially fail, since the proposed direction of change will
vary between (or c!uring) each null time in such a way to lead
to little net resultant. On the other hand, if the signal and
chopping frequencies are close together (in terms of the
time constant), the null circuit will respond at the beat
frequency, leading to two undesirable results. First, the gain
and phase characteristics will be disturbed in the neighborhood of the chopping frequency, since the amplifier input
signal will be partially reduced, with some delay. Second, the
effective input will include a component at the beat
frequency, not present in the true input.
The ICl7850 minimizes this problem by the simple
expedient of introducing a compensating dynamic offset
voltage in the nulling amplifier. This is possible since, at the
frequency range of interest, the AC signal that causes the
problem is a function only of the compensation capacitor, the
input stage gms, and the output Signal amplitude. By adding
another capacitor from the output signal of the main amplifier
to the corresponding summing pOint in the nulling amplifier,
with a value which is correctly scaled to allow for the ratio of
the input stage gms, and connecting it only during the time
when the main amplifier is being nulled, the nulling amplifier
does not see the input-related signal at the main amplifier.
Thus, no nulling signal is generated, and no beat frequency
is generated. The required matching of the gm and capacitor
values is readily achieved, since they are all on a monolithic
die, and the result is a device with virtually no interference
between the normal operation of the main amplifier and the
chopping action of the nulling amplifier.

null network to remove this input signal. This effort cannot
succeed, and in fact will increase the depth of overload. If
this condition is maintained long enough (compared to the
nulling time constant), the null circuit Itself will also be driven
to its limit. Thus, when the input signal returns to an inrange
value, the input offset voltage will be skewed heavily to one
side. If the nulling range of the amplifier exceeds the input
signal range, frequently the case in the high-gain
applications common for such devices, the output will remain
stuck at the supply rail until the null circuit has almost
recovered. Since the null amplifier driving signal may be
quite small, recovery may take a long time.
Several possible methods can be used to combat this effect.
One is to detect the output limiting condition, and to stop the
chopping operation during the time that this does (or can)
occur. This has two disadvantages. It may not be possible to
predict such overrange conditions, nor easy to detect their
occurrence either. Further, even if this is done successfully,
the nulling system will be unable to correct the inevitable loss
of true null caused by leakage currents on the null points,
etc. Thus, an extended overrange interval with the chopping
stopped can leave the null badly disturbed, perhaps as much
as when the chopping is active. Nevertheless, in situations
where an overrange occurrence is predictable or readily
detectable, and lasts only for a limited time, the technique is
very useful. The ICl7650 facilitates this form of overload
effect amelioration by providing an EXT ClK IN pin (in the
14-pin versions), which can be held "low", stopping the
chopping action in a position where no capacitor charging
can occur, and by allowing judicious use of the CLAMP pin
(see below) as an overload detector.

FIGURE 13. VOLTAGES IN INVERTING AMPLIFIER WITH OVERLOAD INPUT

Overload Effects
The second traditional problem with chopper-stabilized
amplifiers relates to their behavior under overload. Once
again the problem arises through the presence of an input
signal on the main amplifier which is not due to the input
offset voltage. In this case, the presence of a large signal in
the system leads to the output running up against the supply
. rails. Under these conditions the amplifier no longer has
control, and the voltage at its input becomes only a function
of the feedback network, the input signal, and the output
swing limit of the amplifier, as shown in Figure 13. The
nulling amplifier, however, has no means of knowing that this
is the problem, and will attempt to "rectify" it by driving the

FIGURE 14. AVOIDING OVERLOAD WITH ZENER CLAMPS

The other technique for avoiding the overload problem
Involves adding a nonlinear element to the feedback
network, so that overrange inputs do not cause the output to
limit against the supply rail. One possible way of doing this is
to parallel the feedback element with a pair of Zener diodes

10-16

Application Note 053
which conduct just before the limiting would occur, as shown
in Figure 14 for the inverting configuration. The noninverting
arrangement is similar, but only reduces the gain to unity
after the Zeners conduct. One disadvantage with this circuit
is that the Zener voltage is quite critical, especially if the
supply voltage variation is significant and the maximum
allowable swing is desired. The ICL7850 avoids both of
these problems by providing a CLAMP pin which will conduct
current in the appropriate direction whenever the output
voltage gets within a few hundred mV of either supply. The
internal schematic is indicated in Figure 15A, and the output
current characteristics as a function of the voltage margin to
the supply rails in Figure 15B. The leakage currents due to
the small Nand P channel MOSFETs are negligible, and
they can only be turned on if their common sources, tied to
the output, get close to the relevant rail. If this pin is tied to
the inverting input to the amplifier, and the impedance at this
point is adequate, the desired limiting is readily achieved,
with no disturbance to the null network, and usually
negligible effect on the input bias current. The only penalties
paid for this overload protection are a slight limitation on the
output swing, and an increase in the input current on the
inverting input when the output swings close to the rail. Also,
the input circuit is not quite so easily guarded on a PC board
if the CLAMP pin is used.

v+----------__~~-------

:~~R~~~--------_~~~~-------,

~8 I i~,~~
AMy.

/'

INTERNAL
BIAS LINE

v-

VOUT

U~

-llr

r-- PIN

T

_----++----IFf1_

FIGURE 15A. OUTPUT CLAMP CIRCUIT

Device Characteristics
The net result, then, of all this technical wizardry is an op
amp with quite remarkable characteristics. The input errorrelated parameters are unprecedented in a monolithic
device, and rare indeed against all competitors, with aVos
of under 511V (typically under 111V) and an input bias current
of no more than 10pA. The Vos value is maintained over the
full range of the power supply, input common-mode, output
swing, and temperature ranges. In other words the PSRR,
CMRR, AVOL ' and dVosldT or drift are all virtually unmeasurable, and well over 120dB, 120dB, 140dB, and under
10nVJOC, respectively. The long-term drift, which we can
consider to be very low frequency noise (as indeed it is from
a device physics point of view), is also undetectable.
The other device characteristics also compare favorably with
those of the 1lA741 and LM101 type. The Gain-Bandwidth
product and slew rate are both about 3 times higher, at
2MHz and 2.5V11lS respectively, the supply current is about
the same, at 2mA (3.5mA Max), the stability margin is similar, and the output swings between the supply rails. The only
significant limitations on its use are the reduced supply voltage range (±8V Max) and the 10kn load limitation. These
are becoming less important with the growth of ±5V analog
systems, and also can be readily side-stepped, as shown in
the Applications section below.
And to cap it all, this paragon of op amp virtue is a moderate-sized monolithic die made with a high-yielding mature
low-cost process, so the device cost is quite low.

10-17

FIGURE 158. CONDUCTION CHARACTERISTICS

Application Note 053
Applications
So much has been written about op amp applications over
the last few decades that there is little point in trying to
reproduce it all, even with revised specifications and
capabilities. The most important point to be appreciated is
that in any application where the performance of the circuit
can be significantly enhanced by a reduction of input offset
voltage and/or bias current, the ICL7650S can be put right to
work. Further, any circuit using a null-trimming pot is an
immediate candidate for replacement, since the cost of
purchase, insertion, initial adjustment, and especially
periodic readjustment will generally be greater than the initial
small premium for. this device and two capacitors. Otherwise,
the finite space available here will be used to present the
particulars of this substitution as germane to the ICL7650S,
followed by the details of some circuits that utilize the specific capabilities of the part particularly well, and some combinations with other devices that concatenate their
respective features.
The normal substitution requires nothing but the
replacement of any null trim pot with two required capacitors.
In the case of the 14-pin devices, the pinout corresponds to
that of the LM108 type device, so substitution of the
ICL7650S for a (rare) 14-pin LM101/A, LM107, 1JA741 , OP05/0P-07, or any similar part, can be done most readily with
the 8-pin version. The alternative involves a minor PC board
change. If good overload recovery is a requirement for the
application, the connections to the CLAMP pin (see Overload Effects) should be made according to the basic configurations of Figure 16. The impedance at the point of
attachment needs to be high enough, at least at DC, to permit the worst case input signal to be accommodated within
the capability of the CLAMP pin output current, according to
the curve of Figure 15B. Usually this is easily managed in
the case of the inverting configuration, but in the non-inverting case,some additional input clamping may be necessary.
Some alternatives for doing this are shown in Figure 17.

INPUT

> ......_OUTPUT

R3 + (R11R21 ,,100kn
FOR FULL CLAMP EFFECT

FIGURE 16A. NON-INVERTING AMPLIFIER
R2

INPUT>-M_......

> ......_

OUTPUT

(R11R21 "l00kn FOR
FULL CLAMP EFFECT

FIGURE 16B. INVERTING AMPLIFIER
FIGURE 16. NON-INVERTING AND INVERTING
CONFIGURATIONS WITH (OPTIONAL) CLAMP
CIRCUIT CONNECTION

v+ ----------t---~-------------

10100
VIN

>---+----t---I
10100

One frequent use of an op amp is as a comparator. This
cannot be done with the usual chopper amplifiers because of
their terrible behavior under overload conditions, the normal
operating mode for an op amp so used (see Overfoad
Effects). However, the optional overload avoidance feature
built-in to the ICL7650 allows its use in many of these
applications, as shown in Figure 18. The current from the
CLAMP pin forces the inverting input to follow the signal input
(within the output swing and input common-mode ranges),
and the transfer characteristic is essentially a reflection of the
characteristic of Figure 15B. The comparison voltage must be
capable of absorbing the CLAMP pin current without distress
to itself or other parts of the system. Only one polarity of comparison is possible with a high input impedance, but if a low
impedance drive input is available, the roles can be reversed
to achieve the other polarity. The speed of the circuit is limited
to input ramp rates under 1OOVls for the most accurate performance, but above this rate the timing errors of most comparators exceed their input offset errors in any case.

>-......-VOUT

~ --------~--~--------~---

FIGURE 17. SOME OTHER CLAMPING CONFIGURATIONS FOR
NON-INVERTING AMPLIFIERS

10-18

Application Note 053
the ICL7650). This is less than the errors associated with
standard thermocouples themselves. Naturally, to realize
this performance, all the other little thermocouples between
the leads, the PC board, any IC socket, and the other components, etc., will have to be carefully handled. This topic is
discussed in Achieving the Full Benefits.

Vour

L - - -....~Wr---_~+OUT

IN

FIGURE 19. 3 OP AMP INSTRUMENTATION AMPLIFIER

r------------------------------qV+

ICIl

-::J
CIl..J
Ww

bO
zO

c..:iE
c..w
-......~~------1
,>--+OUT

IN->---------t

FIGURE 26B.
FIGURE 26. HA2500 OR HA2600 OFFSET NULLED BY

a..::E
a..w
-Wlr-+-------I

lilt

~

INPUTS

GUARD

y.
+15Y

..1...

FIGURE 29A. 14-PIN PART
2N5461

EXTERNAL
CAPACITORS

-15Y

.J...

~~,O

2N5461

FIGURE 27. NULLED HA2500 WITH DYNAMIC CORRENTION
AND OVERLOAD CLAMP

.5~
,3~jrA">

EXTERNAL_ 4
CAPACITORS,

, . - - -_ _ _-oY·
+3Y TO +IIY

y.

~ ~.

GUARD

4'

BOTTOMYIEW

FIGURE 29B. TO-99 PACKAGE
+IN

_+---.;~

FIGURE 29. BOARD LAYOUTS FOR INPUT GUARDING

·IN_+-"'-::~

t-............----oY·

-3YTO·BY

1.2MIl

Y+

FIGURE 30A. NON·INVERTING AMPLIFIER WITH CLAMP

FIGURE 28. AUTO·NULLING CIRCUIT FOR OP-Cl5lOP-Cl7

FIGURE 30B. INVERTING AMPLIFIER WITH CLAMP
FIGURE 30. INPUT GUARDING WITH CLAMP PIN

10-24

Harris Semiconductor

---No. ANS14.1

---

------

Harris Linear

November 1996

The HA-2400 PRAM Four
Channel Operational Amplifier
Author: Don Jones

Introduction

CHANNEL

Harris Semiconductor has announced a new linear device,
the HA-2400/HA-2405 Four Channel Operational Amplifier.
This combines the functions of an analog switch and a high
performance operational amplifier, and makes practical a
large number of new linear circuit applications.

I

Do ENABLE

CHANNEL CHANNEL

CHANNEL

1

2

3

4

OFF

OFF

OFF

L

L

H

ON

L

H

H

OFF

ON

OFF

OFF

H

L

H

OFF

OFF

ON

OFF

H

H

H

OFF

OFF

OFF

ON

L

OFF

OFF

OFF

OFF

L
L
orH orH

----,

v+
v- GND COMP
r----~--~-~--

0,

I

OV,;L,;+0.8V

+2V,;H,;+5V

The digital inputs can be driven with any DTL or TTL circuit
which uses a standard +5V supply.

Compensation
OUTPUT
OUTPUT
AMPLIFIER

Do D,

Frequency compensation for closed loop stability is
recommended for closed loop gains less than 10. This is
accomplished by connection of a single external capacitor
from Pin 12 to AC ground (the V+ supply is recommended).
The fOllowing table shows the minimum suggested
compensation for various closed loop gains, with the
resultant bandwidth and slew rate. Obviously, when the four
channels are connected with different feedback networks,
the channel with the lowest closed loop gain will govern the
required compensation.

I

ENABLE

DIGITAL INPUTS
FIGURE 1.

A functional diagram of the HA-2400 is shown above. There
are four preamplifier sections, one of which is selected
through the DTLlTTL compatible inputs and connected to
the output amplifier. The selected analog input terminals and
the output terminal form a high performance operational
amplifier.

NONINVERTING

In actuality, the circuit consists of four conventional op amp
input circuits connected in parallel to a conventional op amp
output circuit. The decode/control circuitry furnishes
operating current only to the selected input section.

Circuit Connections
The digital inputs control the selection of the amplifier input
channels in accordance with the fOllowing truth table:

INVERTING

CCOMP
pF

BANDWIDTH
(TYPICAL)
(-3dB),
MHz

GAIN,VN

SLEW
RATE
(TYPICAL)
VlIlS

1

-

15

8.0

15

1

7

8.0

20

zO

3

2

4

8.0

22

5

4

3

6.0

25

8

7

2

5.0

30

>10

>9

0

40+ GAIN

50

Compensation capacitors of greater value can be used to
obtain lower bandwidth, greater phase margin, and reduced
overshoot, at the expense of proportionately reduced slew
rate.

© Harris Corporation '996
10-25

en

2

External lead-lag networks could also be used to optimize
bandwidth and/or slew rate at a particular gain.

Copyright

I-

-:::i
en...J
Ww

be
a.:E
a.w

--/l--.-oOUT
IN 2

If offset adjustment is required, it can generally be
accomplished by resistive summation at either of the inputs
for each channel (see Application Number 8).
The analog input terminals of the OFF channels draw the
same bias current as the ON inputs. The maximum
differential input voltage of these terminals must be
observed and their voltage levels must never exceed the
supply voltages.

_....L......flL.;:;;.J~-,-

--'--"~

FIGURE 2. ANALOG MULTIPLEXER WITH BUFFERED INPUT
AND OUTPUT

This circuit is used for analog signal selection or time
division multiplexing. As shown, the feedback signal places
the selected amplifier channel in a voltage follower (noninverting unity gain) configuration, and provides very high
input impedance and low output impedance. The single
package replaces four input buffer amplifiers, four analog
switches with decoding, and one output buffer amplifier.
For low level input signals, gain can be added to one or more
channels by connecting the (-) inputs to a voltage divider
between output and ground. Bandwidth is approximately
8MHz, and the output will slew from one level to another at
about 15V1I1S.
Expansion to multiplex 5 to 12 channels can be accomplished by connecting the compensation pins of two or three
devices together, and using the output of only one of the
devices. The Enable input on the unselected devices must
below.
Expansion to 16 or more channels is accomplished in a
straightforward manner by connecting outputs of 4 fourchannel multiplexers to the inputs of another four-channel
multiplexer.
Differential signals can be handled by two identical multiplexers addressed in parallel.
Inverting amplifier configurations can also be used, but the
feedback resistors may cause crosstalk from the output to
unselected inputs.

10-26

Application Note 514
Application No.2
INPUT

Application No.4

(;~::::::~;;;;~~

INPUT

Z=600n

300

150

+15V

1--"",,0 OUT

75

600

Z-600n

75

OUTPUT

FIGURE 5. PROGRAMMABLE ATTENUATOR

FIGURE 3. AMPLIFIER, NON-INVERTING PROGRAMMABLE
GAIN

This is a non-inverting amplifier configuration with feedback
resistors chosen to produce a gain of 0, 1, 2, 4, or 8
depending on the Digital Control inputs.
Comparators at the output could be used for automatic gain
selection for auto-ranging meters, etc.

This circuit performs the function of dividing the input signal
by a selected constant (1. 2, 4. 8. or 00 as illustrated). To
multiply by a selected constant. see circuit NO.2. While T, 1t,
or L sections could be used in the input attenuator, this is not
necessary since the amplifier loading is negligible and a
constant input impedance is maintained. The circuit is thus
much simpler and more accurate than the usual method of
constructing a constant impedance ladder and switching
sections in and out with analog switches.
Two identical circuits may be used to attenuate a balanced
line.
Application No.5

CHALLENGE: Design a circuit using only two HA-2400s
which can be programmed to any of 16 different gains.
Application No.3

ti

-::J

en...J
Ww
FIGURE 6. ADDERISUBTRACTOR PROGRAMMABLE
FUNCTION

be

zO

1l.:E
Il.W

FIGURE 4. AMPLIFIER, INVERTING PROGRAMMABLE GAIN

The circuit above can be programmed for a gain of 0, -1, -2,
-4, or -8.
This could also have been accomplished with one input
resistor and one feedback resistor per channel in the
conventional manner, but this would require eight resistors
rather than five.

The circuit shown above can be programmed to give the
output functions -K1 X, -K2 V, -(K3X + K4 Y). or KsX - KeY.
Obviously, many other functions of one or more variables
can be constructed, including combinations with analog
multiplier or logarithmic modules.
This device opens up many new design approaches in
digitally controlled analog computation or signal manipulation.

10-27

<10.'6

7.29><10'16

(b)I,iR(i

9.9xlO·16

1.89x10·16

7.2x10· 18

72x10· 18

100Hz

3.15x10·17

(C)4KTFIQ 4.968xlO· 16 4.968x10· 16 4.968x10· 16 4.968x1 0. 16 4.968x10' 16
(d)En2

5.09x10·15

1.86x10·'5

1.31x10·15

1.23x10·15

The frequencies below the f1 point of the bandwidth selected
are filtered out by the RC network on the output of HA-2600.
The measurement of the broadband noise is observed on
the true RMS voltmeter. The measured output noise of· the
circuit is 4.7mV RMS as compared to the calculated value of
6.7mVRMS •

1.23x10·15

The totals of the selected values for each frequency is in the
form of Ei. This should be plotted on linear graph paper as
shown below:
1.5 x 10"'5.-:-:-:--,---,.---..-----,----,

Spot noise values must be generated in order to make the
output noise prediction. The effects of ·Popcorn" noise have
been excluded due to the type of measurement system.
The Quan-Tech Control Unit, Model No. 2283 and Filter Unit,
Model No. 2181 were used to acquire spot noise voltage
values expressed in (V/--JHz). The test system performs
measurements from 10Hz by orders of magnitude to 100kHz
with an effective bandwidth of 1Hz at each tested frequency.
Several source resistance (RG) values were used in the
measuring system to reveal the effects of RG on each type of
Harris' op amps and to obtain proper voltage noise values
essential for current noise calculations.

A Discussion On "Popcorn" Noise

1K

10K

20K
30K
FREQUENCY (Hz)

40K

50K

FIGURE 3. HA-2600 TOTAL EQUIVALENT INPUT NOISE

Since a noise figure is needed for the frequency of 1kHz to
24kHz, it is necessary to calculate the effective bandwidth of
the circuit. With Av = 60dB the upper 3dB point is approximately 24kHz. The product of 1.57 (24kHz) is 37.7kHz and
is the effective bandwidth of the circuit.
The shaded area under the curve is approximately
45 x 10·12 y2; the total equivalent input noise is -.fEin2 or
6.7!1V, and the total output noise for the selected bandwidth
is -.fEln2 X (closed loop gain) or 6.7mV RM S.

"Popcorn" noise was first discovered in early 709 type op
amps. Essentially it is an abrupt step-like shift in offset
voltage (or current) lasting for several milliseconds and
having amplitude from less than one microvolt to several
hundred microvolts. Occurrence of the "pops" is quite
random - an amplifier may exhibit several pops per second
during one observation period and then remain "popless" for
several minutes. Worst case conditions are usually at low
temperatures with high values of RG. Some amplifier
designs and some manufacturer's products are notoriously
bad in this respect. Although theories of the popcorn mechanism differ, it is known that devices with surface contamination of the semiconductor chip will be particularly bad
"poppers". Advertising claims not withstanding, the author
has never seen any manufacturer's op amp that was completely free of "popcorn." Some peak detector circuits have
been developed to screen devices for low amplitude "pops",
but 100% assurance is impossible because an infinite test
time would be required. Some studies have shown that spot
noise measurements at 1OHz and 100Hz, discarding units
that are much higher than typical, is an effective screen for
potentially high "popcorn" units.

10-33

t;
-:3
en..J
Ww

be

zO
c..:!:
c..w
 0.4
:!

0.2
><
oC

:!

LINE 265,
FIELD 2

45

65

'----~.

I
I

LINE 1,
FIELD 1
LINE 2 •
FIELD 1
LINE 3,
FIELD 1

I

85

105

125

TEMPERATURE (OC)

FIRST HALF

...x----_______"

LINE 262,
FIELO 1

OF LINE 263 FIGURE 7B. INTERLACED SCANNING

FIGURE 6. HA-5033 MAXIMUM POWER DISSIPATION VS
AMBIENT TEMPERATURE: FREE AIR

FIGURE 7. SCANNING SEQUENCE

The maximum power dissipation of the HA-5033/2240A
metal can/heat sink system is calculated to be,
POMAX

- _........ --___ a. - -......-t

0
25

f,..----~-

--------

175 - 25

= 34 + 27 = 2.46

Therefore, the HA-5033 used with the Thermalloy 2240A
can dissipate 2.46W at 25DC and not exceed the maximum
junction temperature of 175°C.
The power dissipation limits shown in Figure 6 and those
determined with the heat sink apply for both quiescent and
load related power. Therefore,
POMAX ~ Poc + PAC
Poc = (V+)(+I) + (V-)(-I)
PAC = (11T)ofT v(t) i(t) dt

Video Performance
The images which appear on your television picture tube are
created by a process called scanning [3]. Scanning is a
method of recreating the optical image of a scene one line at
a time. Referring to Figure 7A, an electron beam moves or
"scans" from left to right and quickly returns to a position
below its starting spot. This process continues until the
bottom of the picture is reached and the beam returns to the
original top left hand position. This method is called
sequential scanning.

Incorporated into present television broadcast standards is a
technique called interlaced scanning. Interlaced scanning
recreates the scene by providing two half scans. As shown in
Figure 7B, the first scan traces out the odd numbered lines,
the second scan fills in the even numbered lines. This
technique avoids the flicker problem and excessive
bandwidths required for similar picture definition using
sequential scanning.
The United States NTSC (National Television Systems
Committee) broadcast standard is a 525 line standard. Each
scan consists of 2621/2 lines. The first scan is known as field
one, the second, field two. Therefore, the complete picture
consists of two fields.
The first 21 lines of each field are blank. Those lines are left
open and are not used to broadcast video information.
Instead, these lines contain other important information,
such as sync pulses, data transmission, and test signals.
The test signals contained in these lines are called the
Vertical Interval Test Signals (V ITS) [4, 5], which allows
realtime monitoring of the television broadcast signal quality.
These test signals were used to evaluate the video
performance of the HA-5033.
Four test Signals are commonly used in the vertical interval.
They are the multiburst, color bar, composite and vertical
interval reference. These test signals are shown in Figures 8
through 11.

10-38

Application Note 548

IRE
100

IRE
100

...w~

80

z

z
>- U~ w

60

w

II:

40

"

20

o

~

w Qw

~

II:

:::Ii

0

THREE STEP
MODULATED
PEDESTAL

-40

-40

FIGURE 8. MULTI BURST SIGNAL (FIELD 1, LINE 17) ALLOWS
FREQUENCY RESPONSE CHECKS

w

...

1::;~~
~

...

aEjg

IRE
120

~!

100

III
:::)

w

III

Q.

t'§

l-

II:

!l
~
:::)

III

W

Q.

I;;

Q

0
:::Ii

FIGURE 9. COLOR BAR (FIELD 2, LINE 17) ENABLES MONITORING OF COLOR TRANSMISSION QUALITY

~

IRE
120

Q

~

100

:::)

Q

80

80

0
:::Ii

60

CHROMINANCE
REFERENCE
LUMINANCE
REFERENCE

60

40

40

20

20

0

o

-40

BLACK
REFERENCE

-40

~

FIGURE 10. COMPOSITE SIGNAL (FIELD 1, AND 2, LINE 18)
DESIGNED FOR GAIN AND TIME DELAY TESTS

FIGURE 11. VERTICAL INTERVAL REFERENCE SIGNAL (FIELD
1 AND 2, LINE 19) PROVIDES COLOR AND GAIN
REFERENCES

Each test signal was created to allow various distortions to
be measured without interfering with the normal video
transmission. These signal distortions which exist in
television systems are defined as linear or non-linear. Nonlinear distortion, such as differential phase and gain, vary
with the amplitude of the picture signal. Linear distortions,
usually dependent upon frequency response, are independent of signal level. For example, the multiburst test signal is
very useful for frequency response checks, whereas the
composite signal contains signals for checking gain error.
Determining the HA-5033's performance level with respect
to the NTSC standard required the definition of a measurement method. Test equipment was needed that would
produce the necessary NTSC test signals and also monitor
the device under test performance. The test configuration,
shown in Figure 12 consisted of a Tektronix 149A NTSC [6]
generator and Marconi TF 2914A video analyzer [7].

+12V

VERTICAL
INTERVAL
TEST SIGNAL
GENERATOR

VIDEO SIGNAL
ANALVZER
MARCONI
I. TF2914A
750:. INSERTION
SIGNAL
-=ANALVZER

-"11,..,....---1
50n
16.18.20
29,42

OV

Rs

Y,N

VRT

OV

TRW
TOC-l007J
-15V

-2V VRB 22
CONY

OV

30
32

411---------,
401--------,
391-------,
381------,
371-----,
361----,
35
34
33

08
(LSB)

07 06

05~

~
-'

04030201 >
(MSB);!:

Z

::Ii

Z

FIGURE 15A. ENHANCING 5033 PERFORMANCE IN FLASH CONVERTER APPLICATIONS: SERIES RESISTOR METHOD
+15V

+5V

Y,N
240pF
VRT

CONVERT

L..::c.

-=- VRM
-15V

-6V

28,4347,48 12,14
49,50 19,21
13,15,
16.18,20
29,42
11
17

-2V VRB 22

TRW
TOC-l007J

41
40
39
38
37

I-

UJ

-::J
UJ..I
Ww

be
zO

-

0.==
o.W

_--0 OUTPUT

FIGURE 18A. MODIFIED OUTPUT BUFFER

When the drive capability of the HA-S033 is insufficient,
consider adding an external output stage. Figure 19A
illustrates an example where a push-pull complementary
output stage has been added to the HA-S033. Although
unable to drive the low impedances of speakers, typically 4Q
to 8Q, the buffer can be used to drive audio output transistors. A variation of this configuration is shown in Figure 19B,
where separate buffers individually drive each transistor
base. A low noise input stage is provided by the HA-S102.
A common method of achieving an audio oscillator circuit is
to use a transistor or IC amplifier with LC or RC feedback.
An alternative technique of generating sinusoidal waveforms, using the HA-S033, is shown in Figure 20. Crystal
oscillators offer improved frequency stability over time and
temperature. This particular oscillator configuration [10] produces an 18.18MHz, 2.8V p_p sinusoidal waveform into a
1kQ load.

FIGURE 20. CRYSTAL OSCILLATOR: Vs = ±15V, C,
C2 = 39pF, 18MHz QUARTZ CRYSTAL

= 12pF,

Conclusion
The HA-S033 is a high performance integrated circuit
presently being utilized in a wide variety of applications. This
paper has provided additional information to aid designers in
applying the HA-S033 video buffer in future applications.

10-45

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Application Note 548
References

Further Reading

[1] Thermalloy Semiconductor Accessories Catalog,
Thermalloy Inc.; Dallas. Texas.

1. "TVNideo Sync Primer", Hewlett-Packard Product Note
005-1,1981.

[2] Heat Sink/Dissipator Products and Thermal Management Guide, International Electronic Research Corp.;
Burbank, California

2. Stu Rasmussen and Clifford B. Schrock "Television
Operational Measurements, Video and RF for NTSC
Systems" Tektronix, 1980.

[3] William L. Hughes, "Television Fundamentals and
Standards', Electronic Engineers Handbook
Donald G. Fink (McGraw-Hili, 1975) p. 20-3

3. "Electrical Performance Standards for Television Relay
Facilities" Electronic Industries Association Standard
'
'
RS-250-B, 1976.

ed.;

[4] "VITS Analysis for TV Screening", Tektronix Application
Note #T900, 1978

4. L. E. Weaver, Television Video Transmission Measurements, (London, Marconi Instruments, 1971).

[5] "Video Facility Testing/Technical Performance
Objectives', NTC Report No.7, Published by the Public
Broadcasting Service for the NTC, 1976.

5. F. F. Mazda, ed., Electronic Engineers Reference Book,
5th ed. (London Butterworth', 1982).

[6] Tektronix 1984 Product Catalog.

Acknowledgments

[7] Marconi Instruments 1983-84 Product Catalog.

1. Technical contributions of John Prentice and Robert
Junkins.

[8] "Monolithic Video AID Converter", TRW TOCl 007J Data
Sheet, 1978.

2. Sales and Technical Staff of Marconi Instruments.

[9] "New High Speed Switch Offers Sub-50ns Switching
Time" Harris Application Note 543,1983.

NOTE: Information contained in application notes is intended solely
for general guidance; use of the information for user's specific
application is at user's risk.

[10] Tor Hougen, "Keep Your Oscillator Simple", EON, June,
1984, p. 236-238.

10-46

Harris Semiconductor

No. AN551.1

Harris Linear

November 1996

Recommended Test Procedures for Operational Amplifiers
Authors: Wes Kilgore and Brian Mathews

Introduction
The following text describes the basic test procedures that
can be used for most Harris Op Amps. Note that all
measurement conversions have been taken into account in
the equations stated.

3. Input Offset Current
Using Test Circuit 1, the input offset current (110) of the AUT
is determined by:
1. Measuring El as in procedure 1.

1. Offset Voltage

2. Maintaining Voc at OV.

The offset voltage (V IO) of the amplifier under test (AUT) is
measured via Test Circuit 1 as follows:

3. Open SI, S2 and S3'
4. Measuring voltage at E in volts (label as E4)'

v-

1. Set V+ and
supplies to values specified in Table 1.
Column (1) and VOC to OV.

110
110

2. Close SI and S2, open S3'

4. Power Supply Rejection Ratio

3. Choose: RF = 50K for non-precision amplifiers.
RF = 5M for precision amplifiers.

Both positive and negative PSRRs are measured via Test
Circuit 1. For PSRR+:

4. Measure voltage at E in volts (label as El ).
VIO = El (mV) for RF = 50K, or

1. Close SI and S2, open S3'

VIO = El "10 (IN) for RF = 5M

2. Choose: RF

The gain of this circuit with RF = 50K (RF = 5M) requires the
output to be driven to 1000 (100,000) times the offset voHage
necessary to maintain the output of 1he AUT at Ov. Note that
the AUT output is always identical to Voc. Overall circuit stabilHy is maintained by the adjustable feed-back capacitor CA'

2. Input Bias Current

1. Measuring El as in procedure 1 (use Rs = 1OOK for JFET
input devices).

5. Change V+ to +20V.
6. Measure voltage at E in volts (label as E6)'

2. Maintain Voc at OV.

Similarly for PSRR-:
1. Follow steps 1 and 2 for PSRR+ above.

5. Measure voltage at E in volts (label as

=(El - E2) x 10 (nA) for RF =50K, Rs =100K

PSRR - = 20

The bias current flowing in or out of the negative terminal
(IB_) is found by:

2. Close SI' open S2 and S3'
IBIB-

=(El - E3) x 100 (nA) for RF =50K, Rs =10K, or
=(El - E3) x 10 (nA) for RF =50K, Rs =100K

IOg101~1
(dB) for R F= SOK
Es- E6

Eel.

I09101~I(dB)
for RF = SOK
E7- Ee

5. Common Mode Rejection Ratio
The CMRR is determined by adjusting Test Circuit 1 as
follows:
1. Close SI and S2, open S3'
2. Choose: RF

Copyright © Harris Corporation 1996

10-47

=50K

t;

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Ww

W..J

3. Measure voltage at E in volts (label as E7)'
4. Change V- to -20V.

IB+ = (El - E2) x 100 (nA) for RF = 50K, Rs = 10K, or

3. Measuring voltage at E in volts (label as E3)'

+ = 20

2. Set Voc = OV, V+ = +15V, V- = -10.

3. Close S2, open SI and S3'
4. Measuring voltage at E in volts (label as E2).

1. Following steps 1 and 2 for IB+'

=50K

3. Set Voc =0, V+ =10V, and v- =-15V.
4. Measure voltage at E in volts (label as Es).

PSRR

The bias current flowing in or out of the positive terminal of
the AUT (IB+) is obtained using Test Circuit 1 by:

IB+

=(E l • E4) x 100 (nA) for RF =50K, Rs =10K, or
=(El - E4) x 10 (nA) for RF =50K, Rs =100K

bO
zO
Q.==
Q.W

<0

a::W

Application Note 551
3. Measure voltage at E in volts (label as E15).

3. Set V+ = +SV, V- = -2SV, and Voc = -10V.
4. Measure voltage at E in volts (label as Eg).

10
AvOL- = ~(V/mV) for RF = SOK
13- 15

S. Set V+ = 2SV. V- = -SV, and Voc = 10V.

6. Measure voltage at E in volts (label as ElO)'

9. Slew Rate

CMRR = 201091012 x 104 1(dB) for RF = SOK
Eg -E 10

Test Circuit 3 is used for measurement of positive and
negative slew rate. For SR+:

6. Output Voltage Swing
o

Test Circuit 2 is adjusted to measure VOUT+ and Your the
procedure is:
1. Select appropriate V+ and V- supply values from Table 1,
Column 1.

1. Select specified RL, ACL, and CL from Table 1, Columns
4, Sand 6.
2. Apply a positive step voltage to VAC (refer to data book for
test waveform).

3. Observe eN and 8t at E. A standard approach is to use
the 10% and 90% points or else the 2S% and 7S% points
on the waveform.

2. Select specified RL from Table 1, Column 2.

3. Set VIN = O.SV.
4. Measure voltage at E in volts. VOUT + = E (V)
Similarly VOUT. is found by:
1. Selecting specified RL from Table 1, Column 1.
2. Setting VIN = -O.SV.
3. Measuring voltage at E in volts.
VOUT.= E (V)

7. Output Current

SR = IN

The output current corresponding to the output voltage of
procedure 6 is found by:

For SR- repeat above procedure with negative input pulse.

at

SR-

1. Measuring VO UT- and VOUT+ as in procedure 6.
VOUT+
.
IOUT= - R - where RL IS from Table 1, Column 2.

= AV
At

10. Full Power Bandwidth

L

Full power bandwidth is calculated by:
1. Measuring slew rate as above in procedure 9.

VOUTIOUT= -R- where RL is from Table 1, Column 2.

2. Measuring VOUT+ as in procedure 6. (Typically VOUT+ is
assumed to be the guaranteed minimum VOUT' usually
10V.)

L

8. Open Loop Gain

FPBW =

Both positive (AVOL+) and negative (Avod open loop gain
measurements are determined by adjusting Test Circuit 1.

SR+
2ltVOUT(PEAK)

For AvoL+:

11. Rise Time, Fall Time and Overshoot

1. Close 51, 52 and 53'

The small signal step response of the AUT is determined via
Test Circuit 3. The procedure requires:

2. Select specified RL from Table 1, Column 3.

3. Set RF = SOK.
4, Set Voc

=OV, V+ = +1SV, and V- =-1SV.

S. Measure voltage at E in volts (label as E13).

6. Set Voc = 10V.

1. Selecting the appropriate RL, AcL, and C L from Table 1,
Columns 4, Sand 6.
2. Applying a positive input step voltage for rise time tR and
positive overshoot 05+.
Applying a negative input step voltage for fall time tF and
negative overshoot 05-.

7. Measure voltage at E in volts (label as E14).
10
AvOL+ = ~(V/mV) for RF = SOK
14 - 13
For AVOL-:

(Refer to data book for input waveforms.)

3. Observe output of AUT noting the key points as shown.

1. Follow steps 1, 2, 3, 4, and S above.
2.SetV oc =-10V.

10-48

Application Note 551

GAIN (dB)

OVERSHOOT

OdB,O"+_ _ _;;;;::----""'t----

,

...

PI

180°-

-----}

-------------- -

FREQUENCY
PHASE MARGIN

PHASE

=

12. Settling Time
Test Circuit 6 is appropriate for settling time (ts) measurement, the procedure is:
1. Select Rl and R2 such that AUT is at the AcL stated in
Table 1, Column 5.
2. Select R3 and R4 so that R3 ~ 2Rl and R4 ~ 2R2 with the
condition that the ratio
R3

R

4

=

Rl

R

3. At a gain of OdB (if AcL 1 in Table I, column 5), record
frequency 11 and corresponding phase Pl'
Phase margin 180 degrees - PI degrees.

=

15. Input Noise Voltage
Test Circuit 5 is designed lor measuring input noise voltage.
Use of the Quantec Noise Analyzer is recommended to
obtain measurements at 1Hz bandwidth around a specific
center frequency. The procedure is:
1. SetRG=O

be maintained.

2. Set circuit card to gain of 10.

2

3. Apply step voltage as specified in data book.

3. Select measurement frequency of interest.

4. Measure the time from tl (time input step applied) to t2

4. Record noise voltage (label as En1 ). Units are nVl-#iZ:).

(the time Es settles to within a specified percentage of
VOUT - see data book). ts t2 - tl
NOTE: Clipping diodes of Test Circuit 6 prevent overdrive of oscilloscope. (Recommend fast Schottky diodes.)

=

16. Input Noise Current
Using Test Circuit 5, the input noise current is obtained by:

13. Gain Bandwidth Product

1. Measure Enl as above for the desired frequency of
interest.

Test Circuit 4 is used lor measuring GBP. The procedure is:

2. Adjust RG so that Vo > 2Enl (label Vo as En2).

1. Sweep VIN thru the required frequency range.
2. With a network analyzer view gain (dB) versus frequency
as below.

~~

Where K = 1.38 x 10-23 (Boltzmann's Constant)
T = 300°C (27°C)

17. Channel Separation (Crosstalk)
FREQUENCY (Hz)

Test Circuit 7 is used to measure channel separation (CS).
The procedure is as follows:

3. At the voltage gain of interest (Av) determine the corresponding frequency fe. Note that chosen Ay must be
greater than or equal to that stated in column 5 of Table 1.
GBP = Ay x fe (Hz) where Ay is in VN.

2. Select RL from Table 1, column 4.

14. Phase Margin (Network Analyzer Method)

3. Measure VOl'
4. Measure V02 of channel 2.

1. Apply V1N at the frequency of interest to input of
channell.

Test Circuit 4 is used to obtain phase margin measurement.
The procedure is:
1. Sweep V1N thru the required frequency range.
2. Display gain in dB and phase in degrees versus
frequency on analyzer as shown.

10-49

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10100VOI

II)

Application Note 551
TABLE ,.
PARAMETERS TO MEASURE
SLEW RATE, OS, t R, tF
(1)
SUPPLY VOLTAGE (VS)

(2)
VOUT
Rdkll)

Rdkll)

(4)
RdkO)

AcL

(6)
CdpF)

HA-2400/04l05

±15

2

2

2

1

50

HA-2500/02l05

±15

2

2

2

1

50

HA-251 0/12115

±15

2

2

2

1

50

HA-2520/02/05

±15

2

2

2

3

50

HA-2539

±15

1

1

1

10

10

HA-2540

±15

1

1

1

10

10

HA-2541

±15

2

2

2

1

10

HA-2542

±15

1

1

1

2

10

HA-2600/02l05

±15

2

2

2

1

100

HA-2620/02l05

±15

2

2

2

5

50

HA-2640/05

±40

5

5

5

1

50

HA-4741

±15

10

2

2

1

50

HA-5101

±15

2

2

2

1

50

HA-51 02104

±15

2

2

2

1

50

HA-5111

±15

2

2

2

10

50

HA-5112114

±15

2

2

2

10

50

HA-5127

±15

0.6

2

2

1

50

HA-5130/05

±15

0.6

2

2

1

100

HA-5134

±15

2

2

2

1

50

HA-5137

±15

0.6

2

2

5

50

HA-5141/12114

+5/0

50

50

50

1

50

HA-5147

±15

0.6

2

2

10

50

HA-5151/12114

±15

10

10

10

1

50

HA-5160/62

±15

2

2

2

10

50

HA-5170

±15

2

2

2

1

50

HA-5180

±15

2

2

2

1

50

HA-5190/95

±15

0.2

0.2

2

5

10

PART NUMBER

10-50

(3)

"voL

(5)

Application Note 551
Test Circuits

Rs = 10kn

10011
Rs = 10kn

5,
10011

TEST CIRCUIT 1
V+
VAC _ _- - - - I

a E
V-_ _ _..
L-_ _
RF

AcL= 1+ 111
R4EFF) = (RF + R I)IIR L

r

RI
-

TEST CIRCUIT 3

TEST CIRCUIT 2

V+

· , _"

V-

HP8601A
SWEEP GENERATOR

OREQUIV.

Vo

t;

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en..J

-

Ww

TEST CIRCUIT 4
Es
R3

R.

be
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TEST CIRCUIT 5
CHANNELl
(INPUT CHANNEL)

CHANNEL 2
(LEAKAGE CHANNEL)

100kll

l00kn

R,
V+

-

R2

V-

V+

VIN

VIN
Vo

TEST CIRCUIT 6

TEST CIRCUIT 7

10-51

V-

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c::
en

Harris Semiconductor

No. AN6668.1

------------- ---------- ----- - ---- ----- ----Harris Linear

November 1996

Applications of the CA3080 and CA3080AHigh-Performance
Operational Transconductance Amplifiers
Author: H.A. Wittlinger

Introduction
The CA3080 and CA3080A are similar in generic form to
conventional operational amplifiers, but differ sufficiently to
justify an explanation of their unique characteristics. This
new class of operational amplifier not only includes the usual
differential input terminals, but also contains an additional
control terminal which enhances the device's flexibility for
use in a broad spectrum of applications. The amplifier
incorporated in these devices is referred to as an
Operational Transconductance Amplifier (OTA), because its
output Signal is best described in terms of the output-current
that it can supply:
AiOUT

Transconductance 9M = 609 1N
The amplifier's output-current is proportional to the voltage
difference at its differential input terminals.
This Application Note describes the operation of the OTA
and features various circuits using the OTA. For example,
communications and industrial applications including modulators, multiplexers, sample-and-hold-circuits, gain control
circuits and micropower comparators are shown and discussed. In addition, circuits have been included to show the
operation of the OTA being used in conjunction with CMOS
devices as post-amplifiers.

The availability of the amplifier bias current (lABel terminal
significantly increases the flexibility of the OTA and permits
the circuit designer to exercise his creativity in the utilization
of this device in many unique applications not possible with
the conventional operational amplifier.

Circuit Description
A simplified block diagram of the OTA is shown in Figure 2.
Transistors 0 1 and O 2 comprise the differential input
amplifier found in most operational amplifiers, while the
lettered-circles (with arrows leading either into or out of the
circles) denote "current-mirrors". Figure 3A shows the basic
type of current-mirror which is comprised of two transistors,
one of which is diode-connected. In a current-mirror with
similar geometries for OA and OB' the current I' establishes a
second current I whose value is essentially equal to that of I'.
v+

Figure 1 shows the equivalent circuit for the OTA. The output
signal is a current which is proportional to the transconductance (gM) of the OTA established by the amplifier bias current (I ABC) and the differential input voltage (eIN)' The OTA
can either source or sink current at the output terminal,
depending on the polarity of the input signal.

vFIGURE 2. SIMPLIFIED DIAGRAM OF THE OTA

9M (mS) = 19.2 'ABC (mA)

flo (MO) ~ 7.5IIABC (mA)
'ABC

FIGURE 1. BASIC EQUIVALENT CIRCUIT OF THE OTA

This basic current-mirror configuration is sensitive to the
transistor beta ([3). The addition of another active transistor,
shown in Figure 38, greatly diminishes the circuit sensitivity
to transistor beta and increases the current-source output
impedance in direct proportion to the transistor beta.
Current-mirror W (Figure 2) uses the configuration shown in
Figure 3A, while mirrors X, Y, and Z are basically the version
shown in Figure 38. Mirrors Y and Z employ PNP transistors,
as depicted by the arrows pointing outward from the mirrors.
Appendix 1 describes current-mirrors in more detail.

Copyright © Harris Corporation 1996

10-52

Application Note 6668
and T is the ambient temperature in degrees Kelvin. At room
temperature, gM = 19.2 X IABC ' where gM is in mS and IABC is
in milliamperes. The temperature coefficient of gM is approximately -0.330/0f'C (at room temperature).

I

~bl:8
v-

v-

FIGURE 3A. DIODE-CONNECTED TRANSISTOR PAIRED WITH
TRANSISTOR

v-

v-

FIGURE 3B. IMPROVED VERSION: EMPLOYS AN EXTRA
TRANSISTOR

Transistor 0 3 and diode D1 (shown in Figure 4) comprise the
current mirror 'W" of Figure 2. Similarly, transistors ~, 0 8 and
0 9 and diode Ds of Figure 4 comprise the generic current mirror "Z' of Figure 2. Darlington-connected transistors are
employed in mirrors "Y" and "Z' to reduce the voltage sensitivity
of the mirror, by the increase of the mirror output impedance.
Transistors 0 1 0 11 , and diode D6 of Figure 4 comprise the
current-mirror "X" of Figure 2. Diodes D2 and D4 are connected
across the base-emitter junctions of Os and 0 8 , respectively, to
improve the circuit speed. The amplifier output signal is derived
from the collectors of the "Z' and "X' current-mirror of Figure 2,
providing a push-pull Class A output stage that produces full
differential gM' This circuit description applies to both the
CA3080 and CA3080A. The CA3080A offers tighter control of
gM and input offset voltage, less variation of input offset voltage
with variation of IABC and controlled cut-off leakage current. In
the CA3080A, both the output and the input cut-off leakage
resistances are greater than 1,000Ma.

°'

10kil

FIGURE 3. BASIC TYPES OF CURRENT MIRRORS

Figure 4 is the complete schematic diagram of the OTA. The
OTA employs only active devices (transistors and diodes).
Current applied to the amplifier-bias-current terminal, IABC '
establishes the emitter current of the input differential
amplifier 0 1 and O2 , Hence, effective control of the
differential transconductance (gM) is achieved.

CHANNEL #1
INPUT l2:J--4IIfv--c--I

v+

10kil

r---------~~~------~~-o7

MULTIPLEXED
OUTPUT

1~50PF

1.

620Q

CHANNEL #2
INPUT 19-I-J.,/I,/Ir--c--I
INVERTING
INPUT
NONINVERTING
INPUT

Iii

CLOCKr--~~-,~~~J
INPUT

Yo
~~----------------~--~--O4
FIGURE 4. SCHEMATIC DIAGRAM OF OTA TYPES CA3080
ANDCA3080A

-:::i
en .....
Ww
'---1--'- 2N4037

l:i 36kil

FIGURE 5. SCHEMATIC DIAGRAM OF OTAs IN A TWOCHANNEL LINEAR TIME-SHARED MULTIPLEXER
CIRCUIT

The gM of a differential amplifier is equal to:
qalc
2KT
(see Reference 2 for derivation) where q is the charge on an
electron, ex is the ratio of collector current to emitter current
of the differential amplifier transistors, (assumed to be 0.99
in this case), Ic is the collector current of the constantcurrent source (IABC in this case), K is Boltzman's constant,

Applications
Multiplexing
The availability of the bias current terminal, IABC ' allows the
device to be gated for multiplexer applications. Figure 5 shows
a simple two-channel multiplexer system using two CA3080

10-53

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cj~===~~r-------I

FIGURE 6. SCHEMATIC DIAGRAM OF A TWO-CHANNEL
LINEAR MULTIPLEXER SYSTEM USING A CMOS
FLIP-FLOP TO GATE TWO OTAs

Top Trace: Output; lV/Div., 1001lslDiv.
Bottom Trace: Voltage Expansion of Output; lmV/Div., 100!!s1Div.
RGURE 8. VOLTAGE WAVEFORMS FOR CIRCUIT OF FIGURE 6

A simple RC phase-compensation network is used on the
output of the OTA in the circuits shown in Figures 5 and 6.
The values of the RC-network are chosen so that:

This RC network is connected to the point shown because the
lowest-frequency pole for the system is usually found at this
point. Figure 7 shows an oscilloscope photograph of the multiplexer circun functioning with two input signals. Figure 8 shows

Sample-and-Hold Circuits
An extension of the multiplex system application is a sampleand-hold circuit (Figure 9), using the strobing characteristics
of the OTA amplifier bias-current (ABC) terminal as a means
of control. Figure 9 shows the basic system using the
CA3080A as an OTA in a simple voltage-follower configuration
with the phase-compensation capaCitor serving the additional
function of sampled-signal storage. The major consideration
for the use of this method to "hold" charge is that neither the

10-54

Application Note 6668
charging amplifier nor the signal readout device significantly
alter the charge stored on the capacitor. The CA3080A is a
particularly suitable capacitor-charging amplifier because its
output resistance is more than 1000MQ under cut-off conditions, and the loading on the storage capacitor during the
hold-mode is minimized. An effective solution to the read-out
requirement involves the use of a 3N138 insulated-gate fieldeffect transistor (MOSFET) in the feedback loop. This transistor has a maximum gate-leakage current of 10pA; its loading
on the charge "holding" capacitor is negligible. The open-loop
voltage-gain of the system (Figure 9) is approximately 100dS
if the MOSFET is used in the source-follower mode with the
CA3080A as the input amplifier. The open-loop output impedance (1/9 M) of the 3N138 is approximately 220Q because its
transconductance is about 4,600~S at an operating current of
5mA. When the CA3080A drives the 3N138, the closed loop
operational-amplifier output impedance characteristic is:
ZO(OPEN-LOOP)

sation/storage capacitor. The horizontal axis shows three
scales representing leakage currents of 50nA, 5nA, 500pA.

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IIIIIIIIi liliiii

illllllllllIIIIIIIlIIIIIIIII .IIIIIIII
._

ZOUT= A(OPEN-LOOP VOLTAGE-GAIN)
2200 2200
= 100dB =-5-=0.00220
10

Top Trace: Sampled SignallV/Div., 20IlS/Div.
Center Trace: Top Portion of Upper Signal; lV/Div., 2Ils/Div.
Bottom Trace: Sampling Signal; 20VlDiv., 20IlS/Div.

2.0kn

FIGURE 10. WAVEFORMS FOR CIRCUIT OF FIGURE 9

Figure 12 shows a dual-trace photograph of a triangular
signal being "sampled-and-held" for approximately 14ms
with a 300pF storage capacitor. The center trace (expanded
to 20mV/Div.) shows the worst-case "tilt" for all the steps
shown in the upper trace. The total equivalent leakage
current in this case is only 170pA (I = C dv/dt).
Figure 13 is an oscilloscope photograph of a ramp voltage
being sampled by the "sample-and-hold" circuit of Figure 9. The
input signal and sampled-output signal are superimposed. The
lower trace shows the sampling signal. Data shown in Figure
13 were recorded with supply voltages of ±10V and the series
input resistor at terminal 5 was 22kQ.

SAMPLE

OVU

-lSV

HOLD
v-= -lSV

1000K

FIGURE 9. SCHEMATIC DIAGRAM OF OTA IN A SAMPLEAND-HOLD CIRCUIT

f-lOOK

Figure 10 shows a "sampled" triangular signal. The lower
trace in the photograph is the sampling signal. When this
signal goes negative, the CA3080A is cutoff and the signal is
"held" on the storage capacitor, as shown by the plateaus on
the triangular waveform. The center trace is a time
expansion of the top-most transition (in the upper trace) with
a time scale of 2~s/Div.

E

_!"o"
......
c,.~~
:;0,.

.JII

~

10K

8~

...
UI

lK

9o
:I:

100

Once the signal is acquired, variation in the stored-signal level
during the hold-period is of concern. This variation is primarily a
function of the cutoff leakage current of the CA3080A (a maximum limit of 5nA), the leakage of the storage element, and
other extraneous paths. These leakage currents may be either
"positive" or "negative" and, consequently, the stored-signal
may rise or fall during the "hold" interval. The term '1i1t" is used
to describe this condition. Figure 11 shows the expected pulse
'1i1f' in microvolts versus time for various values of the compen-

10-55

.JII
.JII

,

1/

1/

.JII

1/

7'

7'

:lIl"~

"',,~~
~

~& ~

./'

.JII

~~ ~

7'

~

\)~~

~~~

~9.~

1/

""

.JII

1/

~THIS SCALE FOR
~~
500pA
Y"~ ~

[;iI

L..i"

f/[

SnA

1
10
100

10
100
lK

en
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~~~

10

I-

-::i

17~~onA
LEAKAGE

100
1~'k)~
lK
10K
lOOK
PULSE TILT (IlV)

10K
lOOK
1000K

FIGURE 11. "TILT" IN "HELD" VOLTAGE vs HOLD TIME

o..::i!:
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ii:
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Application Note 6668

Top Trace: Input and Sampled Output Superimposed:
IOOmV/Div.,IOOnS/Div.
Bottom Trace: Sampling Signal; 20V/Div.. IOOns/Div.

Top Trace: Sampled Signal; IV/Div:, 20mS/Div.
Center Trace: Worse Case Tilt; 20mVlDiv., 20mS/Div.

FIGURE 14. "TRIANGULAR-VOLTAGE" BEING SAMPLED BY
CIRCUIT OF FIGURE 9

FIGURE 12. "TRIANGULAR-VOLTAGE" BEING SAMPLED BY
CIRCUIT OF FIGURE 9

Figure 15 shows the basic circu~ of Figure 9 implemented with
a 2N4037 PNP transistor to minimize capacitive feedthrough.
Figure 16 shows oscilloscope photographs taken with the circuit of Figure 15 operating in the sampling mode at supply voltage of ±15V. The 9.1kn resistor in series with the PNP
transistor emitter establishes amplifier-bias-current (lABel conditions similar to those used in the circuit of Figure 9.
2.0k.Q

120pF

v+ = 15V

Top Trace: Input and Output Superimposed; IV/Div., 2l'5iDiv.
Bottom Trace: Sampling Signal; 20V/Div., 211S/Div.
5Vn·

FIGURE 13. "RAMP-VOLTAGE" BEING SAMPLED BY CIRCUIT
OF FIGURE 9

ov

o--JVv~.J

9.1k.Q

In Figure 14, the trace of Figure 13 has been expanded
(100mV/Div. and 100ns/Div.) to show the response of the
sample·and-hold circuit with respect to the sampling signal.
After the sampling interval, the amplifier overshoots the
signal level and settles (within the amplifier offset voltage) in
approximately 11ls. The resistor in series with the 300pF
phase-compensation capacitor was adjusted to 6an for minimum recovery time.

v- = -15V

FIGURE 15. SCHEMA11C DIAGRAM OF THE OTA IN A SAMPLEAND-HOLD CONFIGURA110N (DTL/TTL CONTROL
LOGIC)

10-56

Application Note 6668

Top Trace: Input and Sampled Output Superimposed;
100mV/Div.,100ns/Div.
Bottom Trace: Sampling Signal; 5V/Div., 100ns/Div.

Top Trace: Output; 5V/Div., 211S/Div.
Center Trace: Differential Comparsion of Input and
Output; 2mV/Div., OV thru Center; 2!1siDiv.
Bottom Trace: Input; 5V/Div., 211S/Div.

FIGURE 16. CIRCUIT OF FIGURE 15 OPERATING IN SAMPLING
MODE

Considerations of circuit stability and signal retention require
the use of the largest possible phase-compensation capacitor,
compatible with the required slew rate. In most systems the
capacitor is chosen for the maximum allowable '1i1f' in the storage mode and the resistor is chosen so that 1/21tRC;: 2M Hz,
corresponding to the first pole in the amplifier at an output current level of 5001lA. It is frequently desirable to optimize the system response by the placement of a small variable resistor in
series with the capacitor, as is shown in Figures 9 and 15. The
120pF capacitor shunting the 2k.O resistor improves the amplifier transient response.
Figure 17 shows a multi-trace oscilloscope photograph of
input and output signals for the circuit of Figure 9, operating
in the linear mode. The lower portion of the photograph
shows the input signal, and the upper portion shows the
output signal. The amplifier slew-rate is determined by the
output current and the capacitive loading: in this case the
slew rate (dv/dt) = 1.8V/~s.
The center trace in Figure 17 shows the difference between
the input and output signals as displayed on a Tektronix 7A13
differential amplifier at 2mV/Div. The output of the amplifier
system settles to within 2mV (the offset voltage specification
for the CA3080A) of the input level in 1~ after slewing.
Figure 18 is a curve of slew-rate versus amplifier-bias-current (IASel for various storage/compensation capacitors. The
magnitude of the current being supplied to the storage/compensation capacitor is equal to the amplifier-bias-current
(IASel when the OTA is supplying its maximum output current.

FIGURE 17. CIRCUIT OF FIGURE 9 OPERATING IN THE
LINEAR SAMPLE MODE

Figure 19 shows the configuration for this form of basic gain
control (a modulation system). The output signal current (10)
is equal to -gM x Vx ; the sign of the output signal is negative
because the input signal is applied to the inverting input
terminal of the OTA. The transconductance of the OTA is controlled by adjustment of the amplifier bias current, IASC. In this
circuit the level of the· unmodulated carrier output is established by a particular amplifier-bias-current (IAsel through
resistor RM. Amplitude modulation of the carrier frequency
occurs because variation of the voltage VM forces a change in
the amplifier-bias-current (lABel supplied via resistor RM.
When VM goes positive, the bias current increases which
causes a corresponding increase in the gM of the OTA. When
the VM goes in the negative direction (toward the amplifierbias-current terminal potential), the amplifier-bias-current
decreases, and reduces the gM of the OTA.

t;

100

.

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tc
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;t

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Effective gain control of a signal may be obtained by
controlled variation of the amplifier-bias-current (lASel in the
OTA because its gM is directly proportional to the amplifierbias-current (IASel. For a specified value of amplifier-bias-current, the output current (10) is equal to the product of gM and
the input signal magnitude. The output voltage swing is the
product of output current (10) and the load resistance (Rd.

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~

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0.01

~

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,.

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0.1

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Gain Control - Amplitude Modulation

150
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10

.;r

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0:i.oI"""

100

1000

AMPLIFIER BIAS CURRENT (IABC ~)

FIGURE 18. SLEW RATE vs AMPLIFIER-BIAS-CURRENT (IABC>

10-57

Application Note 6668
three remaining transistors of the transistor-array connected
as a current-source for the emitter followers.
.

CARRIER
FREQUENCY
Vx

~~~~b~JJ~~ vVM

FIGURE 19. AMPLITUDE MODULATOR CIRCUIT USING THE OTA

As discussed earlier, gM = 19.2 X IABC, where gM is in
millisiemens when IABC is in milliamperes. In this case, IABC
is approximately equal to:

+6V

FIGURE 20. AMPLITUDE MODULATOR USING OTA
CONTROLLED BY PNP TRANSISTOR

YM-(Y-)
- - - = I ABC
RM
10 =-9M Y X
9M YX = (19.2)(I ABC )(Y X)
10=

10 =

-19.2[Y M -(Y-)]Y x
RM
19.2(Yx)(Y-) 19.2(Yx)(Y M)
RM
RM

There are two terms in the modulation equation: the first
term represents the fixed carrier input, independent of YM
and the second term represents the modulation, which either
adds to or subtracts from the first term. When YM is equal to
the Y- term, the output is reduced to zero.
In the preceding modulation equations the term,
FIGURE 21. AMPLITUDE MODULATOR USING OTA
CONTROLLED BY PNP AND NPN TRANSISTORS

Y

(19.2)(Y x ) ~BC
M

involving the amplifier-bias-current terminal voltage (YABel (see
Figure 4 for YABel was neglected. This term was assumed to
be small because YABC is small compared with Y- in the equation. If the amplifier-bias-current terminal is driven by a currentsource (such as from the collector of a PNP transistor), the
effect of YABC variation is eliminated and transferred to the
involvement of the PNP transistor base-emitter junction characteristics. Figure 20 shows a method of driving the amplifierbias-current terminal to effectively remove this latter variation.
If an NPN transistor is added to the circuit of Figure 20 as an
emitter-follower to drive the PNP transistor, variations due to
base-emitter characteJistics are considerably reduced due to
the complementary nature of the NPN base-emitter junctions. Moreover, the temperature coefficients of the two
base-emitter junctions tend to cancel one another. Figure 21
shows a configuration using one transistor in the CA3018A
NPN transistor-array as an input emitter-follower, with the

The 1001<0 potentiometer shown in these schematics is used
to null the effects of amplifier input offset voltage. This potentiometer is adjusted to set the output voltage symmetrically
about zero. Figures 22A and 22B show oscilloscope photographs of the output voltages obtained when the circuit of Figure 19 is used as a modulator for both sinusoidal and triangular
modulating signals. This method of modulation permits a range
exceeding 1000:1 in the gain, and thus provides modulation of
the carrier input in excess of 99%. The photo In Figure 22C
shows the excellent isolation (>8OdB at f = 100kHz) achieved in
this modulator during the "gated-off" condition.
Four-Quadrant Multipliers
A single CA3080A is especially suited for many lowfrequency, low-power four-quadrant multiplier applications.
The basic multiplier circuit of Figure 23 is particularly useful
for waveform generation, doubly balanced modulation, and
other signal processing applications, in portable equipment,
where low-power consumption is essential and accuracy

10-58

Application Note 6668
requirements are moderate. The multiplier configuration is
basically an extension of the previously discussed gaincontrolled configuration (Figure 19).
To obtain a four-quadrant multiplier, the first term of the
modulation equation (which represents the fixed carrier)
must be reduced to zero. This term is reduced to zero by the
placement of a feedback resistor (R) between the output and
the inverting input terminal of the CA3080A, with the value of
the feedback resistor (R) equal to 1/9 M. The output current is
10 = gM (-Vx) because the input is applied to the inverting
terminal of the OTA. The output current due to the resistor
(R) is Vx/R. Hence, the two signals cancel when R = 1/9 M.
The current for this configuration is:
10 =

-19.2 VXV M
R
,andVM=V y
M

The output signal for these configurations is a current which
is best terminated by a short-circuit. This condition can be
satisfied by making the load resistance for the multiplier output very small. Alternatively, the output can be applied to a
current-to-voltage converter as shown in Figure 24.

TIME

(50~IV.)

Top Trace: Modulation Input (20V)
Bottom Trace: Amplitude Modulated Output; 500mV/Div.
FIGURE 22B. RESPONSE FOR TRIANGLE WAVE MODULATION

In Figure 23, the current "cancellation" in the resistor R is a
direct function of the OTA differential amplifier linearity. In the
following example, the signal excursion is limited to ±10mV to
preserve this linearity. Greater signal-excursions on the input
terminal will result in a significant departure from linear operation (which may be entirely satisfactory in many applications).

TIME (50~slDIV.)

Top Trace: Gated Output; W/Div.
Bottom Trace: Voltage Expansion Of Above Signal
Showing No Residual; 1mv/Div.

-rIME (50~slDIV.)

t;

FIGURE 22C. RESPONSE FOR SQUARE WAVE MODULATION

en-:J
...

FIGURE 22. AMPLITUDE MODULATOR CIRCUIT OF FIGURE 19
WITH RM = 40kn, Vs = ±1 OV

bO
zO

Ww

1l..:iE

Top Trace: Modulation Input (= 20V p.p)
Center Trace: Amplitude Modulated Output; 500mV/Div.
Bottom Trace: Expanded Output to Show
Depth of Modulation; 20mV/Div.

Il..W

<0
0::
en

vx_......_1---1

FIGURE 22A. RESPONSE FOR SINE WAVE MODULATION

>"='61)4._10

=-K Vx Vy

vy_-w\r-_....
FIGURE 23. BASIC FOUR QUADRANT ANALOG MULTIPLIER
USING AN OTA

10-59

Application Note 6668

X
y ......---..nrr"'"

V+ _ _M - _ V -

-15V +-II/ININv-+ +15V

-15V ....W\(\/V\r-+

1MQ

200kn

FIGURE 24. OTA ANALOG MULTIPLIER DRIVING A CURRENTTO-VOLTAGE CONVERTER

Figure 25 shows a schematic diagram of the basic multiplier wnh
the adjustments set-up to give the multiplier an accuracy of
approximately ±7 percent full-scale. There are only three adjustments: 1) one is on the output, to compensate for slight variations
in the current-transfer ratio of the current-mirrors (which would
otherwise result in a symmetrical output about some current level
other than zero); 2) the adjustment of the 20kn potentiometer
establishes the gM of the system equal to the value of the fixed
resistor shunting the system when the Y-input is zero; 3) compensates for error due to input offset voltage.
Procedure for adjustment of the circuit:
1. a) Set the 1Mn output-current balancing potentiometer
to the center of its range
b) Ground the
and V- inputs
c) Adjust the 100kn potentiometer until a OV reading is
obtained at the output.
2. a) Ground the V-input and apply a signal to the
input through a low source-impedance generator (it is
essential that a low impedance source be used; this
minimizes any change in the gM balance or zero-point
due to the 501lA V-input bias current).
b) Adjust the 20kn potentiometer in series with V-input
until a reading of OV is obtained at the output. This
adjustment establishes the gM of the CA3080A at the
proper level to cancel the output signal. The output
current is diverted through the 51 Okn resistor.
3. a) Ground the X-input and apply a signal to the V-input
through a low source-impedance generator.
b) Adjust the 1Mn resistor for an output voltage of Ov.

x-

x-

+15V

FIGURE 26. SCHEMATIC DIAGRAM OF ANALOG MULTIPLIER
USING OTA CONTROLLED BY A PNP TRANSISTOR

Figure 26 shows the schematic of an analog multiplier circuit
with a 2N4037 PNP transistor replacing the V-input "current"
resistor. The advantage of this system is the higher input
resistance resulting from the current-gain of the PNP
transistor. The addition of another emitter-follower preceeding the PNP transistor (shown in Figure 21) will further
increase the current gain while markedly reducing the effect
of the Vbe temperature-dependent characteristic and the
offset voltage of the two base-emitter junctions.
Figures 27A and 278 show oscilloscope photographs of the
output signals delivered by the circun of Figure 26 which is connected as a suppressed-carrier generator. Figures 28A and
288 contain photos of the outputs obtained in signal "squaring"
circuits, i.e. "squaring" sine-wave and triangular- wave inputs.
If ±15V power supplies are used (shown in Figure 26), both
inputs can accept ±10V input signals. Adjustment of this
multiplier circuit is similar to that already described above.

There will be some interaction among the adjustments and
the procedure should be repeated to optimize the circuit
performance.

SOOmV/Div.,200p.slDiv.,
Triangular Input: 700Hz; SV p•p to Vy Input
Carrier Input: 30kHz; 13.5Vp.p to Vx Input
FIGURE 27A.

FIGURE 25. SCHEMATIC DIAGRAM OF ANALOG MULTIPLIER
USINGOTA

10-60

Application Note 6668

500mVlOiv., 200llsJOiv.,
Modulating Frequency: 700Hz; 5Vp_p to Vy Input
Carrier Input: 21 kHz; 13.5Vpop to Vx Input
FIGURE 27B.
FIGURE 27. WAVEFORMS OBSERVED WITH OTA ANALOG
MULTIPLIER USED AS A SUPPRESSED CARRIER
GENERATOR

The accuracy and stability of these multipliers are a direct
function of the power supply-voltage stability because the Yinput is referred to the negative supply-voltage. Tracking of
the positive and negative supply is also important because
the balance adjustments for both the offset voltage and output current are also referenced to these supplies.

Linear Multiplexer - Decoder
A simple, but effective system for multiplexing and decoding
can be assembled with the CA3080 shown in Figure 29.
Only two channels are·· shown in this schematic, but the
number of channels may be extended as desired. Figure 30
shows oscilloscope photos taken during operation of the
multiplexer and decoder. A CA3080 is used as a 10~s delay"one-shot" multivibrator in the decoder to insure that the
sample-and-hold circuit can sample only after the input signal has settled. Thus, the trailing edge of the "one-shot" output-signal is used to sample the input at the sample-andhold circuit for approximately 1~. Figure 31 shows
oscilloscope photos of various waveforms observed during
operation of the multiplexer/decoder circuit. Either the Q or Q
output from the flip-flop may be used to trigger the 10l!s
"one-shot" to decode a signal.

Top Trace: Input to X And Y; 2V/Div., 1msJDiv. (200Hz)
Bottom Trace: Output; 500mV/Oiv., 1msJDiv. (400Hz)
FIGURE 28B.
FIGURE 28. WAVEFORMS OBSERVED WITH OTA ANALOG
MULTIPLIER USED IN SIGNAL-SQUARING
CIRCUITS

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--i~""'-\Mr---I
·5V

·5V

FIGURE 29. TWO-CHANNEL MULTIPLEXER AND DECODER USING OTAs

Top Trace: Input Signal; 1V/Div., 20mS/Div.
Center Trace: Recovered Output; 1V/Div., 20ms/Div.
Bottom Trace: Multiplexed Signals; 2V/Div., 20mS/Div.

Top Trace: Input Signal; lV/Div., 20mS/Div.
Center Trace: Recovered Output; lV/Div., 20mS/Div.
Bottom Trace: Multiplexed Signals; 1V/Div., 20ms/Div.

FIGURE 30. WAVEFORMS SHOWING OPERATION OF UNEAR MULTlPLEXERlSAMPLE·AN[)..HOLD DECODE CIRCUITRY (FIGURE 29)

10·62

Application Note 6668

Top Trace: Flip-flop Output; SVlDiv., 20llslDiv.
Center Trace: "One-shor Output; SVlDiv., 20llslDiv.
Bottom Trace: Strobe Pulse At The Collector of 01;
O.1VIDiv., 20llslDiv.

SOOllslDiv.

FIGURE 31A. WAVEFORMS CONTROWNG DECODER ENABLE

FIGURE 31C. SAME AS FIGURE 31B BUT WITH EXPANDED
TIMESCALE
FIGURE 31. VARIOUS WAVEFORMS SHOWING THE
OPERATION OF LINEAR MULTIPLEXER

High-Gain, High-Current Output Stages

Top Trace: Strobe Pulse at 01; O.SVIDiv., SmslDiv.
Center Trace: MUltir,exed Output With One
Inpu at GND; O.SV/Div., SmslDiv.
Bottom Trace: DeCoded Output; O.SVIDiv., SmslDiv.
FIGURE 31 B. WAVEFORMS SHOWING DECODER OPERATION

In the previously discussed examples, the OTA has been
buffered by a single insulated-gate field-effect-transistor
(MOSFET) shown in Figure 9. This configuration yields a
voltage gain equal to the (gM) (Ra) product of the CA30BO,
which is typically 142,000 (103dB). The output voltage and
current-swing of the operational amplifier formed by this
configuration (Figure 9) are limited by the 3N13B MOSFET
performance and its source-terminal load. In the positive
direction, the MOSFET may be driven into saturation; the
source-load resistance and the MOSFET characteristics
become the factors limiting the output-voltage swing in the
negative direction. The available negative-going load current
may be kept constant by the return of the source-terminal to
a constant-current transistor. Phase compensation is applied
at the interface of the CA30BO and the 3N13B MOSFET
shown in Figure 9.
Another variation of this generic form of amplifier utilizes the
CD4007A (CMOS) inverter as an amplifier driven by the
CA30BO. Each of the three inverter/amplifiers in the
CD4007A has a typical voltage gain of 30dB. The gain of a
single CMOS inverter/amplifier coupled with the 100dB gain
of the CA30BO yields a total forward-gain of about 130dB.
Use of a two-stage CMOS amplifier configuration will
increase the total open-loop gain of the system to about
160dB (100,000,000). Figures 32 through 3S show examples
of these configurations. Each CMOS inverter/amplifier can
sink or source a current of 6mA (Typ). In Figures 34 and 35,
two CMOS inverter/amplifiers have been connected in parallel to provide additional output current.

10-63

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Application Note 6668
and 35, for example, power-supply current drawn by the
CMOS inverter/amplifier approaches zero as the output voltage swings either positive or negative, while the CA3080
current-drain remains constant.
Figure 37 shows a variety of circuits that can be assembled
using the CA3080 to drive one inverter/amplifier in the
CD4007A. For greater output current capability, the remaining amplifiers in the CD4007A may be connected in parallel
with the single stage shown. Precise timing and thresholds
are assured by the stable characteristics of the input differential amplifier in the CA3080. Moreover, speed vs power
consumption trade-offs may be made by adjustment of the
IABC current to the CA3080. The quiescent power consumption of the circuits shown in Figure 37 is typically 6mW, but
can be made to operate in the micropower region by suitable
circuit modifications.

INVERTING
INPUT
NON-INVERTING
INPUT

FIGURE 32. OTA DRIVING CMOS INVERTER/AMPLIFIER IN
OPEN-LOOP MODE

The open-loop slew-rate of the circuit in Figure 32 is
approximately 65V/!!S. When compensated for the unity-gain
voltage-follower mode, the slew-rate is about 1V/I1S (shown
in Figure 33). Even when the three inverter/amplifiers in the
CD4007A are connected as shown in Figure 34, the openloop slew-rate remains at 65V1I1S. A slew-rate of about 1Vllts
is maintained with this circuit connected in the unity-gain
voltage-follower mode, as shown in Figure 35. Figure 36
contains oscilloscope photos of input-output waveforms
under small-signal and large-signal conditions for the circuits
of Figures 33 and 35. These photos illustrate the inherent
stability of the OTA and CMOS circuits operating in concert.

+6V

2kn

FIGURE 34. OTA DRIVING TWO-STAGE CMOS INVERTER/
AMPLIFIER IN OPEN-LOOP MODE

+6V

FIGURE 33. OTA DRIVING CMOS INVERTER/AMPLIFIER IN
UNITY-GAIN CLOSED-LOOP MODE

Precision Multistable Circuits
The micropower capabilities of the CA3080, when combined
with the characteristics of the CD4007A CMOS inverter/
amplifiers, are ideally suited for use in connection with precision multistable circuits. In the circuits of Figures 32, 33, 34,

FIGURE 35. OTA DRIVING TWO-STAGE CMOS INVERTER/
AMPLIFIER IN UNITY GAIN CLOSED-LOOP MODE

10-64

Application Note 6668

Top Trace: Input; 5V/Div.• 10011s/Div.
Bottom Trace: Output; 5VIDiv.• 1001lS/Div.

Top Trace: Input; 50mV/Div., 111s1Div.
Bottom Trace: Output; 50mVlDiv., ll1siDiv.

FIGURE 36A. LARGE SIGNAL RESPONSE FOR CIRCUIT IN
FIGURE 33

FIGURE 36B. SMALL SIGNAL RESPONSE FOR CIRCUIT IN
FIGURE 33

TOp Trace: Input; 50mV/Div., 111s1Div.
Bottom Trace: Output; 50mVlDiv., 111s1Div.

Top Trace: Input; 5VlDiv.• 10011s1Div.
Bottom Trace: Output; 5V/Div.• 10011s1Div.
FIGURE 36C. LARGE SIGNAL RESPONSE FOR CIRCUIT IN
FIGURE 35

FIGURE 36D. SMALL SIGNAL RESPONSE FOR CIRCUIT IN
FIGURE 35

l(/)

FIGURE 36. PERFORMANCE OF OTA DRIVING CMOS INVERTER/AMPLIFIER

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Micropower Comparator
The schematic diagram of a micropower comparator is
shown in Figure 38. Quiescent power consumption of this
circuit is about 10l1W (Typ). When the comparator is strobed
'ON", the CA3080A becomes active and consumes 420I1W.
Under these conditions, the circuit responds to a differential
input signal in about 8115. By suitably biasing the CA3080A,
the circuit response time can be decreased to about 150ns,
but the power consumption rises to 21 mW.

The differential amplifier input common-mode range for the
circuit of Figure 38 is -1 V to +1 0.5V. Voltage gain of the
micropower comparator is typically 130dB. For example, a
511V input signal will switch the output.

10-65

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Application Note 6668
f~---'---

R

...---V-..-.- - - - " S l V
kO""'""--..,

2RCln(2~1 .. 1)

100kO

6
V+ = 12V
V-=·2V

V·

STROBE

V·

10kO

9

FIGURE 3S. SCHEMATIC DIAGRAM OF MICROPOWE.R COMPARATOR USING THE CA30S0A AND CMOS
CD4007A

_

FIGURE 37A. ASTABLE MULTIVIBRATOR

T=RCln

[

~(v+
- v-) + V+ - Vol
R1 +R
2

V ..

V+

Appendix I
Current Mirrors
The basic current-mirror, described in the beginning of this
note, in its rudimentary form, is a transistor with a second transistor connected as a diode. Figure A shows this basic configuration of the current-mirror. O2 is a diode connected transistor.
Because this diode-connected transistor is not in saturation and
is "active", the "diode" formed by this connection may be considered as a transistor with 100% feedback. Therefore, the
base current still controls the collector current as is the case in
normal transistor action, i.e., Ic = ~ lB' If a current 11 is forced
into the diode-connected transistor, the base-to-emitter voltage
will rise until equilibrium is reached and the total current being
supplied is divided between the collector and base regions.
Thus, a base-to-emitter voltage is established in O2 such that
O2 ·sinks" the applied current 11,
11

~

~~

V+
100kO

FIGURE 39A. DIODE - TRANSISTOR CURRENT SOURCE

10kO

_

FIGURE 37C. THRESHOLD DETECTOR
FIGURE 37. MULTISTABLE CIRCUITS USING THE OTA AND
CMOS INVERTER/AMPLIFIERS

If the base of a second transistor (01) is connected to the baseto-collector junction of O2 , shown in Figure 39A, 0 1 will also be
able to "sink" a current approximately equal to that flowing in the
collector lead of the diode-connected transistor O2, This
assumes that both transistors have identical characteristics, a
prerequisite established by the Ie fabrication technique. The
diflerence in current between the input current (1 1) and the collector current (12) of transistor 0 1 , is due to the fact that the
base-current for both transistors is supplied from 11, Figure 39B
shows this current division, using a "unif' of base current (1) to
each transistor base. This base current causes a collector current to flow in direct proportion to the ~ of each transistor. The
ratio of the "sinking" current 12 to the input current 11 Is therefore:

,= .
12
1

10-66

~/(~

.

2).

Application Note 6668
Thus, as /3 increases, the output current (1 2) approaches the
input current (11)' The curves in Figure 39C show this ratio as a
function of the transistor /3. When the transistor /3 is equal to
100, for example, the difference between the two currents is
only two percent.

••

l1li !!Ei III
III IIIII II!
III
III

1111
III

IIIIlI III illII II
II III Ii

1111

1111

I
II
II1II
IIIIIi

III I!! lit

1111 1111II
IIIII!

1.5
1.4
I
1.3 1--+--11 I 112
~ 1.2 1---+-_.,.=2 _ ~ + 2~
0 1.1
11 - ~2 + 2~ + 2 -+--+-++--+---t--t-H
~
a: 1.0
io"'"
...I.
a:
0.9
w
./
"- 0.8 1-7IfC--+--b..t"'1io"'"
I
II)
./
zc( 0.7 hI"'-+-......
'I-l-l 12
~
lI'"
a: 0.6 IL--f--7I'-1--+-l-l
~ + 2 +t+-+-+-+-i-l
~
,/
0.5
w 0.4 . /
a:
a:
::> 0.3
u 0.2
0.1
0
10
100
1
1000
TRANSISTOR BETA

i1 =

!z

11111

I

I

III

1111

!!"Jj

1111

III

III

III !lI'aI

• III III II
•
• •
III

alii III

1111

FAIIIIIIIIII III.

ail

III

I

I

-- •• -••-•-•••
I

II

I I IIIII.

FIGURE 39B. DIODE - TRANSISTOR CURRENT SOURCE.
ANALYSIS OF CURRENT FLOW

• • _ ...

.. I• - •• •••
I I ••
I •• •
•
•• I I

!Jill I11III I11III

III !!iii III

Q2.A--.......-~

-..
..• ••
1IIIII.I .:ci......
il1lll _

II

11111

III

lIiIIIliiiI illlllliIIIIIII illllllliIIIIII IIIIIIIIIiI IIIIIIIIIiI iilliIIIIIII IIIIIIIIIII

III IIIIlIIIIIII!!III

I11III

!IIIIIII.

iIIIIIIIIlIillllllliIIIIIIIIlI

Scale: Horizontal = 2V/Div.
Vertical 1mNDiv.
Steps 1mNSTEP

=
=

FIGURE 390. PHOTO SHOWING RESULTS OF FIGURE 39B

This diode-connected transistor (03 in Figure 39E) may be
considered as a current-sampling diode that senses the emitter-current of 0 1 and adjusts the base current 0 1 (via O2 ) to
maintain a constant-current in 12 , Because all controlling transistors are operated at relatively fixed voltages, the previously
discussed effects due to voltage coefficients do not exist. The
curve-tracer photograph of Figure 39F shows the improved
output resistance characteristics of the circuit of Figure 39E.
(Compare Figure 390 and 39F).
11

~

FIGURE 39C. CURRENT TRANSFER RATIO lil1 VB
TRANSISTOR BETA

Figure 390 shows a curve-tracer photograph of characteristics
tor the circuit of Figure 39B. No consideration in this discussion is
given to the variation of the transistor (01) collector current as a
function of ns collector-te-emitter voRage. The output resistance
characteristic of 0 1 retains its similarny to that of a single transistor operating under similar conditions. An improvement in its output resistance characteristic can be made by the insertion of a
diode-connected transistor in series with the emitter of 0 1,

FIGURE 39E. DIODE - 2 TRANSISTOR CURRENT SOURCE

Ii;

-:::i
Ww
W..J

150
zO
c..:.E
c..w

«0

c::

W

10-67

Application Note 6668
Conclusions
The Operational Transconductance Amplifier (OTA) is a
unique device with characteristics particularly suited to
applications in multiplexing, amplitude modulation, analog
multiplication, gain control, switching circuitry, multivibrators,
comparators, and a broad spectrum of micropower circuitry.
The CA3080 is ideal for use in conjunction with CMOS ICs
being operated in the linear mode.

Acknowledgments
The author is indebted to C. F. Wheatly for many helpful
discussions. Valued contributions in circuit evaluation were
made by A. J. Visioli Jr. and J. H. Klinger.

Scale: Horizontal = 2VIDiv.
Vertical = 1mAlDiv.
Steps = 1mAlSTEP
FIGURE 39F. PHOTO SHOWING RESULTS OF FIGURE 39E

Figure 39G shows the current-division within the mirror
assuming a ·unit" (1) of current in transistors (Q2 and Q3).
The resulting current transfer ratio
I /I

2 1

2
=

P +2P .

p2+2P+2

Figure 39C shows this equation plotted as a function of beta.
It is significant that the current transfer ratio (liI1) is
Improved by the 132 term, and reduces the significance of the
213 + 2 term in the denominator.
12

p(~)
P+1

FIGURE 39G. CURRENT FLOW ANALYSIS OF FIGURE 39E

10-68

Harris Semiconductor

-------------- -- ----- --- -----

---No. AN9202

Harris Linear

January 1992

Using the HFA1100, HFA1130 Evaluation Fixture
Author: Jeff Lies

General Information

mination resistors have been incorporated. Figure 2 illustrates
the typical frequency response of an HFA11 00/30 in this fixture.

The HFA evaluation fixture is a special purpose board which
frees users from the time-consuming task of developing their
own evaluation hardware. It also serves as an example of
the type of high frequency layout required by ultra high
speed op amps. The board makes no provision for easy
modification to other configurations. Modifications are
strongly discouraged, since surface mount printed circuit
pads tend to disintegrate after only a few resolderings.

Evaluating the HFA 1100
As delivered, the fixture is ideal for evaluating the HFA1100.
The V H and V L connections have no effect, since pins 5 and
8 are not bonded out on the HFAll00. Figure 3 details a
setup for evaluating the amplifier's pulse response, while
Figure 4 illustrates the HFA 1100 performance in this setup.
The scope input trace accurately reflects the amplifier input,
but the output trace is one-half the amplifier output voltage.

The fixture is wired in a gain of +2 as shown in Figure 1. It is
intended for use in a 50n environment, so input and output ter-

5 dB/

109 MAC

CHI 521

REF -15 dB

500n

soon

~iI-

son

IT - v -

4I
r::'

IN

10~F* O.l~F*

.l.
'4
0...;.

-SV

ses

MHz

~

~-t~F+ +10~F

r-

HFA1100l30 ~

!

82

Ca~

VH

V

l.J -3. 0035 dB
•

Oil

,!.

's'
~

son

Hld

~+sv

OUT

1\

vL

V

--

*GND

r

1

\

\

GND

Iii

-:J
Ww

en..!
START

FIGURE 1. SCHEMATIC OF HFAll00/30 EVALUATION BOARD

I
PULSE
GENERATOR vG
HP8131AOR
EQUIVALENT

r--

son
POWER
SPLITTER

I

10. 000 OOQ MHz

soon

I D
v2G

r-:::z.
"i7

soon

~G

~

-

50n

vG

T

+X2

",.

son

'7

-sv

SCOPE
TEKll802OR
EQUIVALENT
w/son PLUG-IN

FIGURE 3. CONNECTION FOR EVALUATING HFA1100 PULSE RESPONSE
Copyright

STOP :3 000. 000 000 MHz

FIGURE 2. HFAll00/30 FREQUENCY RESPONSE (Ay

© Harris Corporation 1992
10-69

=+2)

60
zO
c..:!i
c..w

«0

a::en

Application Note 9202
Evaluating the HFA1120

Evaluating the HFA1130

This fixture is not recommended for evaluation of the
HFA 1120. The HFA1120 incorporates balance pins (pins 1
and 5) which are absent on the HFA1100. Pin 1 is
unconnected on this fixture, while pin 5 is connected to the
VL terminal. The unequal capacitance on these pins may
unbalance the amplifier and prevent any meaningful
evaluation.

No fixture modifications are necessary when evaluating the
HFAl130. When evaluatingunclamped performance, the V H
and V L inputs may be left floating. An unclamped HFA1130
performs like an H FAll 00/20 in that the output is clamped to
a default value of approximately ±4.2V. Even though the output swing is less than ±4.2V, the default clamp provides fast
overdrive recovery on the HFA 11 XX family.
Figure 5 illustrates the HFAl130 clamped pulse response for
a positive pulse. The set-up for evaluating the clamped overdrive recovery time is detailed in Figure 6. This'set-up uses a
slower pulse generator, since input transitions ~2ns yield the
best results.
'

INPUT AND OUTPUT: 100mVIDIV

INPUT: 200mVIDIV

OUTPUT: 100mVlDIV

II

(

I
I

IN

IN

~~~=-~

I
------------I-~N·...----+---4--I-------------

=-- -'t{---------- -----

'f-l-,"""'----+---+-it--------------

I
I
I
I
I

OUT

OUT

---- ------------- -------

I

---------

I

I

------- ----~t----I
I
I

Sns/DIV

I

tonslOlV

FIGURE 5. HFA1130 CLAMPED PULSE RESPONSE

FIGURE 4. HFA1100 PULSE RESPONSE

PULSE
GENERATOR OV - 2V
EHt38AOR
EQUIVALENT

D

tV

tV'"

SOO O.sv

SCOPE
TEKtt8020R
EQUIVALENT
w1500 PLUG-IN

FIGURE 6. CONNECTION FOR EVALUATING HFA1130 OVERDRIVE RECOVERY

10-70

Harris Semiconductor
------------ -------- - ------------ --- ----- ------ ------

--

-No. AN930S

Harris Linear

January 1995

HA5020 Operational Amplifier Feedback Resistor Selection
Author: Steve Jost

Optimum AC performance of current feedback amplifiers in
general and of the HA-5020 in particular depends upon
careful selection of the feedback resistor, RF . The benefit of
higher usable bandwidth (compared with conventional
voltage feedback amplifiers) and the ability to control the
frequency response (by choosing the value of RF) carries an
expense in that the design process becomes more complicated. This is particularly true if an intuitive knowledge of
how the device will behave in the end application is lacking.
The purpose of this App Note is to provide a conceptual
foundation on which this intuitive knowledge can be built.
The choice of the optimum resistor value depends upon
design goals for the application subject to conditions of
closed loop gain, source impedance, and load. As a point of
reference, typical curves are provided in the data sheet that
show how the frequency response is affected by closed loop
gain, 'feedback resistor value, and load resistance. Source
impedance, if it is large, becomes a factor only in conjunction
with capacitance at the inputs. The data sheet curves are all
generated with a son source impedance.
To illustrate how one might approach the problem of selecting a feedback resistor based on closed loop gain, consider
the simple model of Figure 1. Between the inputs is a unity
gain voltage buffer with non-zero output impedance
indicated by RI. The transimpedance gain, Rz, is a function
of frequency having a high DC value that forces IE to zero.
The model's behavior is influenced by external elements
consisting of a feedback network (RF and RG), source and
load impedances (Rs and RLl, and stray capacitance at the
amplifier's inputs (C s ).
RS

+IN

Derivation of the transfer function will confirm that the nonzero inverting input impedance, RI, causes the circuit's
bandwidth to degrade as the closed loop gain increases,
while stray capacitance at the negative input gives rise to
gain peaking particularly at low gains (intuitively, Cs is in
parallel with RG causing the gain as determined by the feedback network to increase with frequency).
Gain peaking due to capacitance at the inverting input is
most easily dealt with by placing a resistor in series with the
positive input. If we assume that the stray capacitance at the
positive input equals the stray at the negative input, we can
choose Rs equal to the parallel combination of RF and RG.
This introduces a pole at the positive input which cancels the
zero at the negative input, thereby eliminating the gain peak.
Note that any remaining gain peaking is a result of excessive
phase shift around the loop. Excess phase shift around the
loop can be reduced by increasing RF .
Bandwidth degradation due to non-zero inverting input
resistance is also easy to deal with as long as the product of
the closed loop gain and the inverting input resistance does
not exceed the optimum value for RF in unity gain. By solving
the transfer function for constant bandwidth, we arrive at the
following equations for RF and RG:

RF =RFO - AcL * RI
RI = RF I (AcL - 1)
Where,

(EQ.l)
(EQ.2)

RFO is the optimum value for unity gain (1000n),
RI is the inverting input impedance (75n), and
AcL is the desired closed loop gain.
A comparison between actual measured results in Figures 2
and 3 provides graphic reinforcement for the utility of these
equations. Figure 2 illustrates the failure to consider stray
input capacitance and inverting input resistance, while
Figure 3 incorporates the lessons learned from analyzing
our simple model.

V OUT

In Figure 2, a family of closed loop gain curves was obtained
on a representative unit using Rs = son and constant RF
(RF RFO
l000n). The measured stray capacitance at
either input was 2pF. The results in Figure 3 were obtained
from the same unit, except that (within the constraints of
available standard resistor values) RF and RG were chosen
according to the equations above and Rs was chosen to be
equal to the parallel combination of RF and RG'

=

Ra

FIGURE 1. SIMPLE CURRENT FEEDBACK AMPLIFIER MODEL

Copyright © Harris Corporation 1995

10-71

=

t;
-:J
Ww

CIl..J

150
zO
Il.:::!:

'11.

w

_--__ VOUT

The AGC circuit should be considered a control loop, and its
frequency and phase characteristics plotted. A slow AGC
loop could compensate for slow offset or gain changes over
temperature while a faster AGC loop could compensate for
signal overload conditions.
There are a number of opinions on where the AGC should be
applied. An easy way to do it is to vary the reference on the AID
depending on signal strength. This will work fine if the converter
has been thoroughly characterized over the range of reference
voltages it will see. Unfortunately this is usually not the case.
Most datasheets will not specify the performance of the converter versus reference voltage. Therefore, the user is taking a
significant chance that the part performance will stay the same
over the life of the system for various manufacturing lots of the
AID. The second option is to let the AGC vary the gain of the
signal conditioning circuitry while leaving the reference to the
AID at the value where the performance is guaranteed by the
datasheet. This approach will guarantee the long term success
of a circuit. The design section of this note will discuss a technique using a multiplier chip to accomplish this.

VN = 4.SnV I Viii
INN

=2SpA I v'HZ; INP =2.SpA I Viii
FIGURE 5. OP AMP NOISE MODEL

10-75

Iii

-:J
Ww

1/)...1

bO

zO
c..:5
c..w
<1:0
ii
I/)

Application Note 9313
+12V

18
10K

-12V

+12V

r--~~----~:::J~~~

____

r-ANAlOG
OUT

R7
402
-12V

-"J'IY--4J'IY--W.,..
+12V

+5V

Rl0
10

~--~~~--~ ~3~4
Rll
10

c., 10"F

t---.w,,..----¥l'--+~+ H>

C.O.l"F

....------IH>
+12V

VREF
(4.43V to 3.76V)
17

4
ANALOG OUT ________-I
U7

112R
-12V

2

VREf+

28
VIN
6
1/4R
3/4R

ClK
CEl

D7
D6 3

U6

4
05
04 5
03 10
D2 11
01 12
00 13

OVF

4

FIGURE 6. DESIGN FOR VIDEO IMAGING FRONT END

10-76

Application Note 9313
System Design

HA·2546

Figure 6 is a design for a signal conditioning and AID front end
to an image-processing system. The video input to the system
will be assumed to have a positive picture phase. That is, the
blanking and sync pulses will be the most negative portion of
the video waveform. When the video is ac coupled, the black
reference level has to be reinserted prior to the AID. If this is not
done, then, as the amplitude of the video signal is reduced, due
to a reduced contrast image, the blanking level moves more
positive. The resulting image will now appear a light shade of
gray, rather than the preferred black level. Also, the DSP
becomes more sensitive to coupled noise and may for example, during edge detect, show an edge where none exists.

VIN Vy

~

VIDEO
IN

T1f1,-,:--.. .
75

HA2546

---<1--1

r+

100k
-12V

1N914 I.

VY+

"'

~ '7

FIGURE 7. DC RESTORE CIRCUIT
The HA-2546 is a wideband two quadrant analog multiplier
which makes the implementation of AGC offset and gain
correction easy. It is configured in this design to give the
transfer function:

VOUT =

(VxxVyl
2
V

z

(EQ.B)

The Vz pin can be used to correct for system offset as long
as it does not exceed ±5V. The initial offset adjustment is set
by pot R2. The Vx pin can be used to adjust system gain.

OVF

~~

ADC

Vi

DAC

AD7545

Figure 7 is a simple circuit to DC restore the video. This circuit clamps the most negative point of the signal to -0.7V
which can now be offset by the HA-2546 to provide a stable
black level during changing contrast. Another 8-bit 20 MSPS
converter from Harris Semiconductor, the H11176, has an
internal circuit which will clamp the back porch of a video
signal to a voltage input on the reference pin.

HI-57oo

-\
H ""

I\r

FIGURE 8. SLOW AGC LOOP
The HA-5177 op amp acts as an IN converter for the DAC.
Its feedback is set so th~t at all ones to the DAC the output
voltage will be -2V which is the maximum voltage that is
allowed on the Vx pin. At the normal operating point for the
system the DAC will be at midscale and the overall system
gain will result in a full scale swing to the AID. Since the DAC
is at midscale the system has an equal amount of gain
correction range up and down.
The HA-5020 is a high-speed current feedback op amp
which provides additional gain so that a nominallVp_p signal input to the system the HI-5700 flash will see its full OV to
4V swing. If the sync has been stripped from the video
before it Is digitized [8], then the gain could be adjusted so
that the video reference black to reference white level will
span the full range of the converter.
A high-speed unity gain op amp (HA-5033) buffers the input
to the HI-5700 and provides the necessary low output
impedance over frequency required by flash converters.
Although the HA-5020 can drive the HI-5700 directly, the
HA-5033 has superior current drive, lower output
impedance, and better bandwidth.

U5 is part of a reference circuit in Figure 6 that provides the
4V reference required by the AID and the DAC. It is capable
of 8-bit performance over the industrial temperature range.
Pot R12 will set the initial overall system gain.

The pixel clock of 12.98MHz will usually determine the minimum sampling rate of the AID. In order to relax the filter
reqUirements on the front end to the system the actual
sampling rate used in this note is 15MHz. This will be more
than adequate to cover all established sampling rates
specified for the various published standards.

For the reasons outlined above, it was decided to leave the
reference to the flash at its nominal datasheet value and let
the AGC adjust the gain of the signal conditioning
components prior to the converter. A AD7545 12-bit DAC is
used as part of a slow AGC loop which uses the Vx pin of
the HA-2546 to control the gain of the system.

Additional timing circuitry might be added to gate the pixel
clock so that it is only on during the active line period thereby
conserving frame buffer memory size. If the system uses an
interlaced video format then the circuitry could also define
the even and odd fields of the image frame and update the
memory accordingly.

As illustrated in Figure 8, the feedback loop could be closed
by a microprocessor using the overflow bit on the HI-5700
and could compensate for light intensity shifts or
temperature drift. In order to avoid any glitches the DAC
should be updated during the vertical retrace period.

The clock period for the HI-5700 B-bit flash is made up of an
autozero time and sample time. It was found that the autozero time can be reduced down to as little as 15ns while the
sampling time must remain at 24ns or greater. This timing
allows the sparkle free operation of the circuit at pixel rates
up to 25MHz.

10-77

Application Note 9313
There are many considerations which have to be taken into
account when using high speed converters. These involve
board layout, choosing the right op amp to drive the input,
and designing a low drift reference. Refer to references 6
and 7 for a complete discussion of these topics and others.

OUTPUT
CODE

# REFERENCE
,

LINE

.

7,

111
110

Test Results

101

The IEEE has various standards which address the type of
tests that need to be done on a broadcast video system to
verify the performance of a video AID and D/A combination
(codec). Among them are DC linearity, Signal-To-Noise Ratio
(SNR), bandwidth, and differential phase and gain. Since
this note deals only with RS-170 monochrome video signals,
the tests that deal with the color information, such as
differential phase and gain, are not applicable. Also, adding
a DAC on the output of the converter in order to use the
IEEE test methods would tend to cloud its overall performance of the system with the errors of the DAC. Therefore,
the system will be evaluated using a set of tests that are similar to those recommended by the IEEE but are done byanalyzing the digital data out of the converter. These tests can
also be found on a datasheet for a typical flash AID. Hopefully, as a result of this approach the user will now also be
able to more intelligently read and compare converter
datasheets.
There is a great deal of information in the low frequency
(30Hz) content of video. Historically, the low frequency
performance of an AID has been evaluated by the
Differential (DNL) and Integral (INL) Nonlinearity specs.
DNL is a measure of the deviation of the code widths from
the ideal value of one Least Significant Bit (LSB). INL is the
deviation of the code edges from the ideal transfer curve of
the AID. Since the AID in this system is initially calibrated for
offset and gain, the line used as a reference will be one
drawn through the first and last transition point.

100
011
010
001
000

2

3

4

5

FIGURE 9 •. AID TRANSFER FUNCTION

The ideal probability, Pi is a constant and is equal to the
average of the number of counts per code divided by the
total number of samples. Pm is the measured probability and
is equal to the total number of counts for a particular code
divided by the total number of samples. Once the DNL error
has been determined the INL error is calculated from the
sum of the DLE errors.
A histogram was done on the design discussed in this note
by inputting a 1Vp_p 5kHz triangle wave, encoding the
HI5700 at 15MHz, and capturing the digital data. Figure 10
and Figure 11 are plots of the DNL and INL error for the total
system indicating an accuracy of better than 7 bits with no
missing codes:

The DNL and INL errors can not be calibrated out and is the
best accuracy that can be expected of the system.
Therefore, the INL error should ideally not exceed 1/2 LSB
so that when it is combined with the inherent 1/2 LSB
quantizing error of an AID the total error would not exceed 1
LSB. A DNL error of more than -1 LSB means a code is
missing from the transfer curve. An INL error of 1/2 LSB will
ensure a DNL error of at most 1 LSB.
Figure 9 shows a plot for the transfer function of a converter
with DNL and INL errors. The reference curve and the ideal
transitions are pointed out. Transition point 3 is offset in the
negative direction by 1/2 LSB therefore the ILE at this point is
-1/2 LSB. The ILE of all the other transitions is zero. The DLE
of code 2 is -1/2 LSB and the DLE of code 3 is +1/2 LSB.

+0.59 LSB

-Cl.74LSB

FIGURE 10. DIFFERENTIAL LINEARITY ERROR VB CODE

The actual linearity test was done using a histogram
approach. A triangle wave is input to the system and the
number of occurrences of each code is kept track of. DNL
error is then calculated'in LSBs from:
(Pm(i»
DNL(i) = (P.(i» -1

(Ea. 9)

I

·0.89 LSB

FIGURE 11. INTEGRAL LINEARITY ERROR VB CODE

10-78

Application Note 9313
Due to various dynamic effects such as slew rate limiting and
bandwidth rolloff the static DNL and INL will degrade as the
input frequency approaches the 4MHz bandwidth requirement
of video. DNL will show up as an increase in the quantization
noise which will tend to elevate t!"le noise floor of the ND. INL
is a bend in the transfer curve of the converter and will gener·
ate harmonics. Both result in a loss of dynamic range of the
system.These effects are usually evaluated in the frequency
domain by finding the Slgnal·to·Noise·And·Distortion (SINAD)
in dB.

The high frequency performance of the system was evalu·
ated by changing the input frequency to 4MHz and again
performing an FFT. Figure 12 is a spectrum plot of the
system output. The SINAD for this plot was determined to be
38.2dB for an ENOB of 6.0S bits.

o~========~~==~====~

The SINAD test requires performing a fourier transform on
the data obtained by sampling a continuous time input
waveform. The Discrete Fourier Transform (DFT) can be
thought of as a frequency selective filter that calculates the
RMS voltage at a particular frequency and will work for any
number of samples.
The coefficient for a particular frequency can be found from:
FREQUENCY

N -1

L

Xd(k) =

x(n)xe-j21tk(n/N)

(EQ.10)

n=O
N is the number of samples.
n is the time sample index (n = O. 1.2•...• N-1).
k is the index for the computed frequency components (k=O.
1.2•...• N-1).

FIGURE 12. HIGH FREQUENCY SPECTRAL PLOT OF SYSTEM
(fl =4MHz)

The full power bandwidth and slew rate capability of the
system was checked by inputting a fullscale sinewave at
8M Hz and sampling it at a 1SMHz rate. Figure 13 shows the
resulting reconstructed waveform. Notice the lack of
distortion and sparkle codes.

The Fast Fourier Transform (FFT) is an algorithm that will
compute all the DFT coefficients at one time; but. unlike the
DFT it will only work for sample sizes that are a power of two.
The FFT will output the coefficients for N/2 discrete
frequency bins that will have a resolution of FsamplelN.
Once the FFT has been performed SINAD can be calculated
from:
SINAD dB

=

RMSSIGNAL)
20xlog ( 'R"'M~S::":"::::':":":'=
NOISE

(EQ.11)

Where RMSSIGNAL is the measured RMS signal in the
fundamental bin and RMSNOISE is the sum of all other
spectral components below the Nyquist frequency excluding
DC. It is important that the distortion components be
included in this calculation in order to take into account all
the system errors.

FIGURE 13. RECONSTRUCTED SINEWAVE (f,

=SMHz)

Ii;

-:::i

II)...J

The Effective Number Of Bits (ENOB) of the system can be
found by:
ENOB =

SINAD dB -1.76
6.02

(EQ.12)

Ww

60
zO
n.:i:
n.w

<0
0:

ENOB is a global indication of the accuracy of the system
and. along with INL and DNL will degrade as the input
frequency is increased. The low DNL and INL errors indicate
the excellent low frequency performance of the design. This
was again verified by inputting a 1Vp.p sinewave at 20kHz.
encoding the part at 1SMHz. and performing an FFT on the
data. The SINAD was calculated to be 44.SdB for an ENOB
of 7.1 bits. An indication of the overall low noise in the
system.

10-79

II)

Application Note 9313
Time Division Multiplexed Systems
This note is mainly concerned with RS-170 type video
signals. However, it is instructive to briefly discuss the factors
to consider when dealing with other time division multiplexed
signals that might be seen from some types of CCD arrays, a
multiplexed input, or an infrared sensor array.
The output of CCD arrays many times will have the signal of
interest riding on a large DC offset. Figure 14 is an example
of an inverting buffer that can be used to remove large
offsets. Notice that since resistor R3 sees a virtual ground
Voffset can take on a value much higher than the supply
voltage.

VOFFSET

--.JI,f'.i\t------I

>_~I-

__

Once the circuits have settled then the AID must digitize the
level it sees at its input. The accuracy with which this can be
done is a function dynamic range of the system and will be
determined by the low frequency accuracy of the converter,
the noise generated in the signal conditioning circuits, and
the noise added by the converter. The INL, DNL, and low
frequency SINAD specifications can be used to predict
performance of the system with a particular converter.
The HI5800 is a low noise 12-bit 3 MSPS converter that is
perfect for the applications which require a higher dynamic
range at slower pixel rates. It is a complete sampling
converter with on board sample and hold and reference. The
low frequency (20kHz input) SINAD of typically 70dB reflects
its outstanding low noise performance. The high frequency
(lMHz input) SINAD number of 68dB illustrates how the
performance is maintained at higher input frequencies.

VOUT

Conclusion
FIGURE 14. INVERTING BUFFER

The circuit gain can be calculated from:
VOUT = (-R2/Rl)XVIN-(R2/R3)XVOFFSET

(Ea. 13)

The circuits that process large signal pulse type waveforms
must slew and settle quickly so, as depicted in Figure 15, the
AID can then accurately digitize the pixel information. Given
the ever increasing pixel rates this can become quite a
challenge.

This note has discussed the various considerations involved
in designing the analog front end to an image-processing
system. A system design was presented and proved to have
accurate sparkle free performance at typical video
frequencies. The methodology presented could be used to
analyze the system requirements for systems with higher
pixel rates.

References
(1) Joey Doernberg, Hae-Seung Lee, David A. Hodges, "Full
Speed Testing of AID Converters; IEEE Journal of Solid
State Circuits, Vol. SC-19, No.6, DEC. 1984.
(2) Fredrickson, Thomas M.:'lntuitive Operational Amplifiers,"
McGraw-Hili Inc., New York, NY, 1988.

CCD
OUTPUT

(3) Demler, Michael J., "High-Speed Analog-To-Digital
Conversion; Academic Press Inc., 1992.

AID
ENCODE
FIGURE 15. TIME DIVISION MULTIPLEXED SIGNAL

The overall system settling time is made up of two parts.
Initially the signal must slew until it enters a region where
small signal analysis takes over. Similar slew rate
requirements as discussed in the deSign considerations
section apply in this case also. For a single pole system, the
error will then decay with a time constant determined by the
small signal bandwidth of the system. The settling time in an
actual system is very much a function of the circuit parasitics
and the overall frequency response of the circuit. As such, it
is difficult to calculate an accurate number beforehand.
Reference 2 has a more thorough discussion of settling time
and the calculations involved.

(4) "IEEE Standard for Performance Measurements of AID
and D/A Converters for PCM Television Video Circuits:'
IEEE Standard 746-1984.
(5) "High Speed DeSign Seminar; Published by Analog
Devices, 1990.
(6) "High Speed Signal Processing Applications Seminar",
Published by Harris Semiconductor, 1992.
(7) "Using Harris High Speed AID Converters," Application
Note AN9214, Published by Harris Semiconductor, 1992.
(8) "Video Amplifier with Sync Stripper and DC Restore,"
Harris Semiconductor, Application Note AN9514.

Additional large signal time domain converter specifications
such as overvoltage recovery time and transient response
time become important in these types of applications. As in
the case of full power bandwidth, there are many ways to
define these tests so be aware of the method used on the
datasheet and how it applies to a particular application.

10-80

Harris Semiconductor

No. AN9314.1

------- ---- -------- ----- -- --- ----- -Harris Linear

November 1996

Harris UHF Pin Drivers
Author: Taewon Jung

Introduction
The HFA5250 [1] and HFA5251 are pin drivers designed for
use in automatic test equipment (ATE) and high speed pulse
generators. Pin drivers, especially those with very highspeed performance, have generally been implemented with
discrete transistors (sometimes GaAs) on a circuit board or
in a hybrid. Recent IC process improvements, specifically
Harris' UHF1 process [2], have enabled the manufacturing of
the 500MHz and SOOMHz silicon monolithic pin drivers,
HFA5250 and HFA5251.
The ultra-high speed performance of HFA5250 and
HFA5251 is a result of UHF1 process leverages: low parasitic collector-to-substrate capacitance of the bonded wafer,
low collector-to-base parasitic capacitance of the selfaligned base/emitter technology and ultra-high fT NPN
(SGHz) and PNP (5.5GHz) poly-silicon transistors.

Functional Block Diagram
HFA5250 and HFA5251 circuits share the
functional block diagram shown in Figure 1.

common

Circuit Schematic
The Pin Driver circuit consists of a switch, an output buffer,
and two differential control elements as shown in Figure 2.
A two stage approach, separating the switch from the output
buffer, allows the speed and accuracy requirements of the
switch to be decoupled from the load driving capability of the
buffer.
The patent pending switch Circuitry [3] uses cascaded emitter followers as input buffers and also to switch the input
VH1GH and VLQW to node VSO. Dual differential pairs controlled by the data timing (0 and 0*) direct current to select
either the VH1GH or VLQW switch. Matching transistor types
and transdiodes improve linearity and lowers the voltage offset and offset drift. Stacking two emitter-base junctions
allows the VH1GH to VLQW range to be extended to two
BVebos of the process. The speed of the pin driver is largely
determined by the current flowing through the switch stage
and the collector-base capacitance of the output stage transistors connected to the node VSO.
The output stage consists of cascaded emitter followers constructed in a typical push-pull manner as shown in Figure 2.
However, transdiodes are added to increase the voltage
breakdown characteristics of the output during high-impedance mode. HiZ and HiZ* control the mode of the output
stage. A trimmed, NiCr resistor is added to provide the 50Q
output impedance.

h.>__----1

HIZ :=:~
HIZ·...

....

FIGURE 1. BLOCK DIAGRAM

The control inputs, 0 and 0*, determine the output level. If 0
is at logiC "1" and 0* is at logic "0', the output level will be the
same as VH1GH. If 0 is at logic "0" and 0* is at logic "1", the
output will be the same as VLQw. The control inputs, HiZ and
HiZ', make the output either active or high-impedance. If HiZ
is at logic "1" and HiZ* is at logic "0", the output will be in
high-impedence mode. If HiZ is at logic "0" and HiZ* is at
logic "1", the output will be enabled. The output impedance
in the enabled mode is trimmed to 50Q.

Overall, a symmetry of device types and paths is constructed to improve slew and delay symmetry. Both the
VH1GH to VOUT path and the VLQW to VOUT path contain three
NPN and three PNP transistors operating at similar collector
currents. Thus the transient response of VH1GH to VLQW and
VLOW to VH1GH are kept symmetrical. Also, a trimmable current reference (not shown) allows the AC parameters to be
adjusted to maintain unit to unit consistency.

Copyright © Harris CorporaHon 1996

10-Sl

ti

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Ww

en . . .

be

zO
Q.:E
Q.W

 -10

~

0

Ie .. 5mA, Vee = 3V

~

·15

1 1\1
i'.; r-.....
r-.....

-20

o

From Figure 2, the noise figure of the whole circuit is mainly
controlled by the noise characteristics of the transistor Os. As
shown in Figure 3D, this high-gain amplifier demonstrates
good noise performance. For IC2 = Ics = 5mA, the measured
noise figure is 3.9dB at 900MHz, making this useful as a highgain, low-noise amplifier.
The complete microstrip board layout is shown in Figure 4. A
0.031 inch thick FR-4 (G-10) glass epoxy board is used for the
layout. The dielectric constant of the material is 4.7 at
1000MHz.

,

I~~

!5

-

I

~
=
=
Ie

10mA, Vee

~

~

sv

1
2
FREQUENCY (GHz)

3

FIGURE 3C. OUTPUT VSWR

6

iii"

!!.

5

1&1

a:
:::I
S!

...

40

1&1

I.......
30

!z

~

10

o

0

~

r-..

20

!!!

~~

Ie .. 10mA, Vee = 5V

~
~
~ ~

Ie = 5mA, Vee .. 3V

o

4

z

IIrII

3
0

--

;=::::: ::::::

-

1
2
FREQUENCY (GHz)

0.5

1
FREQUENCY (GHz)

1.5

FIGURE 3D. NOISE

r- ;;:

FIGURE 3. MEASURED CHARACTERISTICS OF THE HIGH
GAIN LOW·NOISE AMPLIFIER

3

FIGURE 3A. GAIN

10-86

2

Application Note 9315
Wideband Amplifier
A well known simple amplifier configuration which achieves
flat gain and broadband matching without losing excessive
signal power is shown in Figure 6. The simultaneous use of
both shunt and series feedback gives rise to broadband
resistive input and output impedances [2, 3].
Figure 7 shows a similar version of the double feedback
wideband amplifier circuit realized with the HFA3096. This
design takes advantage of the PNP transistors (04 and Os)
available on the HFA3096, to bias amplifying transistor O2
for good temperature stability.

FIGURE 4. MICROSTRIP BOARD LAYOUT FOR THE HIGH-GAIN
LOW-NOISE AMPLIFIER

FIGURE 6. SINGLE STAGE SHUNT AND SERIES FEEDBACK
CIRCUIT

The key rule for the circuit board layout is to make the physical length of the conductors as short as possible where the
RF signal is involved. Although it seems obvious, it is easy to
forget that the impedance looking into a microstrip line, that
has load attached at the end, can be totally different from the
attached load impedance depending on the length of the
microstrip line and frequency. Outside the RF signal path, it
does not matter.
At RF frequencies, the value of chip resistors, capacitors,
and inductors should not be taken for granted. In general,
the smaller the size of the component, the better the performance. However, it is important to evaluate the components
before use. For the RF frequencies, these components can
be evaluated easily using a network analyzer by mounting
them as shown in Figure 5. The SMA connector itself contributes about 0.7pF of capacitance between the signal and
ground terminals.

-m~

CHIP COMPONENT

cur CENTER

PINS FLUSH
TO FLANGE

-

SMA CONNECTOR

FIGURE 5. A CHIP COMPONENT MOUNTED ON AN SMA
CONNECTOR

FIGURE 7. WIDEBAND AMPLIFIER REALIZED WITH HFA3096

The frequency response of the wideband amplifier is shown
in Figure 8. As can be seen from Figure 8, the amplifier
shows 10dB of flat gain with 600MHz bandwidth.The input
and output matching is very good over the range of frequency where gains are flat. The low frequency performance
is limited by the 1OOOpF capacitor.
The microstrip board layout for the wideband amplifier is
shown in Figure 9. A 0.031 inch thick FR-4 (G-10) glass
epoxy board is used for the layout.

10-87

Iii

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Ww
Ul-J

150
zO
c..:i
c..w
<1:0

a::

Ul

Application Note 9315
or-------r-------~------~----~

15

-10
10

r--

5

o
108

107

'""

t-------t-------t-------t------::::;;;0""1

INPUTVSWR

-40~

______L __ _ _ _ _ _L __ _ _ _ _ _L __ _ _ _

~

1~

1~

FREQUENCY (Hz)

1~

FREQUENCY (Hz)

FIGURE SA_ GAIN

FIGURE SB. INPUT-OUTPUT VSWR

FIGURE S. MEASURED CHARACTERISTICS OF THE WIDEBAND AMPLIFIER

Summary
A detailed process of designing a high-gain low-noise and a
wideband amplifier using the Harris UHF transistor arrays is
summarized.

Vee

LCHOKE

A two-stage, high-gain, low-noise amplifier built with the
HFA3127 demonstrates 50Q input and output impedance
over a wide frequency range of 800M Hz to 2500MHz without
the use of external matching networks. The gain at 900MHz
is in excess of 17dB with a noise figure of 3.9dB.

THROUGH
HOLE

A wideband amplifier built with the HFA3096 demonstrates
excellent input and output matching with 10dB of constant
gain. The -3dB bandwidth of this amplifier is 600MHz. PNP
transistors available on the HFA3096 are used for temperature stable biasing of the amplifying transistor.

References
[1] C. Davis, et ai, "UHF-1: A High Speed Complementary
Bipolar Analog Process on SOl," Proceeding of BCTM
92, pp260-263, Oct. 1992.
[2] J. B. Couglin, et ai, "A Monolithic Silicon wideband
Amplifier from DC to 1 GHz:' IEEE J. Solid-State
Circuits, vol. SC-8, pp414-419, Dec. 1973.

FIGURE 9. MICROSTRIP BOARD LAYOUT FOR THE WIDEBAND
AMPLIFIER

[3] R. G. Meyer, et ai, "A wideband Ultralinear Amplifier
from 3 to 300 MHz," IEEE J. Solid-State Circuits, vol.
SC-9, pp167-175, Aug. 1974.

10-88

Harris Semiconductor

-----No. AN9317.1

-----

-------------- ------- ----- -------

Harris Linear

November 1996

Micropower Clock Oscillator and Op Amps Provide System
Control for Battery Operated Circuits (HA7210)
Author: AI Little and James Ho
The HA7210 low power oscillator is ideal for battery powered
circuits that require a precision clock. It operates well from a
single 3V to 5V supply, uses extremely low current, and
produces a clock output that is very stable over temperature
and supply voltage. In addition, it requires only an external
crystal and can operate from under 32kHz to over 1OM Hz.
This application note shows how the HA7210 can be used
with a quad CMOS op amp to make a control circuit that will
automatically switch a battery-powered digital system into
micropower "sleep mode" when not in use and trigger the
system on again when an external event (sound, pressure,
etc.) is detected. This function is extremely useful for
applications like remote metering, where a battery-powered
system may need to record occasional events yet remain in
a power down state most of the time.
This control circuit can be configured to turn on with an AC
or DC coupled event sensor and turn off using either a
preset time delay or an external digital system command.
When triggered into the power-up mode, it supplies a
precision system clock, a buffered analog ground reference
and a scaling signal amplifier for an AID converter. In the
power-down mode, it draws less than 50!!A of standby
current.

Circuit Operation
As shown in Figure 1, the control circuit operates from a single 3V to 5V battery and uses only a quad CMOS op amp
(lCL7642) and a HA7210 low power osciliatoJ chip. Two
Power-Down Reset options are available: one for a preset
time delay after turn-on, and another for external digital command as explained in the following text.
Rl and R2 create an analog signal ground reference voltage,
VREF , at 1/2 of the battery Voltage. C2 is used to filter noise
from this high impedance point. The analog reference voltage is then buffered by IC1 A and output to the other three
amplifiers.
Amplifier B is used as a high-pass filter and amplifier such
that a fast edge (like a sudden noise into a microphone) will
produce a large positive swing at the output. Diode 0 1 prevents the output from moving very much below the analog
reference voltage. Cl can be determined experimentally
depending on the application, sensor type, and sensitivity
required.

Amplifier C is used as a comparator and latch. The inverting
terminal is nominally at the analog reference, V REF , but the
non-inverting terminal is lower than V REF due to the
hysteresis of Rs. In the absence of a microphone/sensor
signal, the output of amplifier B is also at V REF , so that
VREF (Rs/(R4 + Rs)) appears at the non-inverting input of
amplifierC.
When the output of amplifier B produces a voltage at the
non-inverting terminal of amplifier C higher than VREF, the
output of C latches into the high state. This state cannot be
changed by any condition at the input of IC1 B due to the
hysteresis provided by Rs. Because the output stage of
amplifier C is CMOS, it can drive a light load nearly to the
positive supply rail.
Voltage from the output of amplifier C is provided to the supply and ENable pins of the HA7210 low power oscillator.
When this happens, the oscillator turns on and provides a
clock output to the rest of the system. C3 is used as a
bypass capacitor for the supply pin. If faster oscillator turn-on
is required, the HA7210 supply pin (pin 1) may be tied
directly to the battery and the output of amplifier C used to
enable the HA7210. In this case, the oscillator will draw
some quiescent current when not in use, but significantly
lower than when enabled. Capacitance at the output of the
HA721 0 should be minimized to keep the active supply current as low as possible.
As shown, amplifier 0 can be used as a scaling amplifier for
a system AID converter. R7 and Rs are used to scale the
gain of the amplifier (G = 1 + Rs/R7). The input of the amplifier is extremely high impedance, so that any type of high
impedance sensor may be used.

Resetting the System
To put the system back into "sleep mode", two options are
available. The digital system can send a logic high state to
the Reset input, forcing the IC1 C comparator/latch to reset
to the low state. Alternatively, if desired, an auto-reset RC
timer (shown in the dotted lines) will cause the circuit to
automatically reset after a preset time interval. This time is
determined by the time it takes for the capacitor at the inverting terminal to charge higher than the voltage at the noninverting terminal of IC1C.

Copyright © Harris Corporation 1996

10-89

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II)

Application Note 9317

1N914
R,3M

Ra1M
Cl 10nF

IC1B
7

~1M

~~~ll~~--~~~~--~~~~---.JL------~----~--~~SYSTEMENABLE

MICROPHONEI
SENSOR

1/4

ICL7642

Re1M

VBATTERY _
3V-SV

D:t

~

1N914

t-r--JYVri----'

RES~-

Cz
10nF

- -

SYSTEM CLOCK OUT

-1-!

AUTO RESET

R

13
ANALOG SIGNAL INPUT

IC1D
14

---::~+~1t;4----"'12

AMPLIFIED ANAL,OG SIGNAL TO AID

ICL7642

NOTE: Provides Sleep Mode, Power-up Trigger, Optional Auto-reset, Scaling Amp for AID, Precision System Clock Oscillator, and Analog
Ground Reference
FIGURE 1. 2-CHIP MICROPOWER CONTROL CIRCUIT OPERATES FROM 3V BATTERY

TABLE 1. HA7210 OSCILLATOR CONTROL INPUTS
ENABLE

FREQ1

FREQ2

1

1

1

10kHz to 100kHz

1

1

0

100kHz to 1MHz

OUTPUT RANGE

1

0

1

1MHz to 5MHz

1

0

0

5MHz to 10MHz+

0

X

X

High Impedance

10-90

Harris Semiconductor

-----No. AN9334.1

-----

------------ ------ ----- --

Harris Linear

October 1996

Improving Start-up Time at 32kHz for the HA7210 Low Power
Crystal Oscillator
Author: Robert Rood
The HA7210 is a very low power crystal-controlled oscillator
that can be programmed to operate between 10kHz and
10MHz. In the lowest frequency range setting (FREO 1 = 1,
FREO 2 1), at 32kHz with a 5V supply and a 40pF load, the
HA7210 will draw a mere 101JA. In this range (10kHz to
100kHz), the low power consumption may result in extended
oscillator start-up time. In higher frequency ranges, power
consumption gradually increases and start-up time is not an
issue. Several approaches to address low frequency start-up
time will be presented.

=

providing faster start-up times (32kHz crystals with ESR
greater than 50kll should be avoided). Using the circuit in Figure 1 the start-up characteristic of a 32.768kHz crystal, set in
the recommended lowest frequency range (FREO 1 = 1,
FREO 2 1) has a delay of 1.9s as shown in Figure 2.

=

VDD

Cl

The first approach is to use the Enable/Disable Mode Pin.
This pin, when pulled low, will switch the output to a high
impedance state while an internal inverter continues to drive
the crystal in normal oscillation. This will result in a power
savings because very often a majority of the power dissipation
is used to drive the output load. In the disabled mode the
HA721 0 will draw only 51JA of standby current as compared to
101JA above. This small amount of standby current gives the
benefit of instant start-up of a reliable and stable clock. The
Enable Time of the HA7210 is typically SOOns.

32.768kHz
CRYSTAL
32.768kHz
CLOCK

FIGURE 1. TYPICAL APPLICATION CIRCUIT

FREQUENCY SELECTION TRUTH TABLE

For applications where the voltage supply is removed from the
circuit or standby mode is not desired, the time from power
being applied until a stable square wave is generated can be
unexpectedly long. It should be noted that 32kHz crystal
parameters vary significantly from vendor to vendor and can
greatly affect the HA7210 (or any Pierce Oscillator) start-up
characteristic. Of particular importance is the Effective Series
Resistance (ESR) of the crystal, with lower ESR generally

ENABLE

FREQ1

FREQ2

1

1

1

OUTPUT RANGE

1

1

0

100kHz to 1MHz

1

0

1

lMHz to 5MHz

10kHz to 100kHz

1

0

0

5MHz to 10MHz

0

X

X

High-Z

I;;

-::::i

UJ.J
Ww

O.Os

1.08

2.08

00
zO
1I..:i

II..W

-.....--ovo
v,

FIGURE 5. NON-INVERTING OP AMP WITH INPUT GROUNDED
AND FEEDBACK LOOP BROKEN

FIGURE 3. NON-INVERTING CIRCUIT

The block diagram shown in Figure 4A is written by inspection of Equation 12. The block diagram shown in Figure 48 is
derived from Figure 4A by block diagram manipulations.
Equation 13 is derived from Equation 12 by algebraic manipulation, or it can be written by inspection of Figure 48
because the system is shown in standard form.

v,

~---------""'~vo

VTa

aZ 1

VTI

Z1 +Z2

-=--=A~

(EO. 14)

Referring to the inverting op amp configuration shown in
Figure 6, the analysis will be performed by working from the
amplifier circuit to the block diagram. The closed loop gain
equations are derived in references one and six as well as
most electronic text books. The closed loop gain which is
equal to 1/13 is known to be -ZiZl; thus, 13 is calculated as
Z1/Z2 with the minus sign indicating a negative input. Referring to Figure 6, if VI is set to zero and the loop is broken at
the negative input to the op amp the circuit is identical to that
shown in Figure 5.

FIGURE 4A. BLOCK DIAGRAM AS WRITTEN FROM EQUATION 12

v,

I---+--ovo
FIGURE 6. INVERTING OP AMP SCHEMATIC

FIGURE 4B. AFTER BLOCK DIAGRAM MANIPULATION
FIGURE 4. BLOCK DIAGRAM OF THE NON-INVERTING OP
AMP AS SHOWN IN EQUATION 12

(EO. 13)

An examination of Figure 5 and Figure 6 reveals that the loop
gain, AI3, is identical for both the inverting and non-inverting
circuit configurations. The loop gain is the only parameter that
determines stability, and it is not a function of the location of
the inputs. Hence the loop gain for the inverting op amp is
given to us by Equation 14. Now that AI3 and 1/13 are both
known, A can be determined by multiplication to be aZi
(Z1 + Z2)' Since the direct gain and the loop gain are both
known Figure 7 can be constructed from these quantities.

10-94

Application Note 9415
Equations 17 and Equation 18 shown below. Notice that the
percentage change in the closed loop gain is the percentage
change In the direct gain divided by the loop gain. Thus for
very high loop gains the initial accuracy and drift will be a
function of the passive components rather than of the direct
or amplifier gain. Although the feedback reduces the gain
errors, other amplifier errors such as input voltage offset are
not affected by the feedback because they occur as an input
rather than within the feedback loop.

Yo

FIGURE 7. BLOCK DIAGRAM OF THE INVERTING OP AMP

dVoNI

Equation 15, which is the closed loop gain equation for an
inverting op amp can be written directly from Figure 7. As (a)
approaches infinity in Equation 15, the closed loop gain
approaches -ZiZ1'
aZ2

z;+Z2
1+~

(EO. 15)

Z1 +Z2

The closed loop gain for the non-inverting circuit, Vd
VI (Z1 + ZiJ/Z1, is different from the closed loop gain for the
inverting circuit, VoNI = -~Z1' It will always be the case that the
loop gain, hence the stability, is independent of the location of the
inputs, but the closed loop performance is highly dependent on
the placement of the input. Many circuits take advantage of this
phenomena to gain better performance as will be shown in the
benefits section.

=

~

1
= (1

1

+A~)2 =

(1

Va

"i

(EO. 17)

+A~)-X-

(EO. 18)
All amplifiers have noise and distortion characteristics associated with them, and low noise or low distortion amplifiers
command a premium price. Very often feedback can be used
at no cost increase to reduce the effects of distortion and
noise. Both closed loop and open loop systems are shown in
Figure 8 and Figure 9; notice that both systems have the
same number of components except for the passive feedback elements.
Vo

Vo

(EO. 16)
Comparing the block diagrams of the non-inverting and
inverting circuits reveals that their direct gains are different,
and this explains why there are some slight performance differences between the configurations. The non-inverting circuit with the higher direct gain has less closed loop error; at
a closed loop gain of 2 for both circuits the non-inverting circuit has a 3.5dB more loop gain. The inverting circuit is more
stable for the same magnitude of closed loop gain; i.e., for a
closed loop gain of 2, AIJINV = O.33a and AIJNON-INV = 0.5a.
Normally these differences are minor, but they are pointed
out because they may be taken advantage of or they can
cause very subtle problems in unique situations.
There are many other op amp circuit configurations, but they
will all reduce to these two basic forms; each of which is a
variation of the basic feedback circuit shown in Figure 1. Letting Z1 and or Z2 equal various combinations of ALCs will
give different closed loop performance, but the analysis techniques remain the same. More complicated circuit configurations can all be reduced to these simple circuits through
block diagram reduction techniques and superposition.

FIGURE 8. CLOSED LOOP SYSTEM

Vo

VI
FIGURE 9. OPEN LOOP SYSTEM

Equation 19 and Equation 20 are derived from the closed
loop and open loop systems shown in Figure 8 and Figure 9.
If Equation 19 is rewritten as shown in Equation 21 it is obvious that Equation 22 results when the quantity A1A2
approaches infinity as it will in an ideal system.
A 1A2(V I +V O)
Va

=

1 +A1A2~

A2V 1

V2

+ 1 +A1A2~ + 1 +A1A2~

(EO. 19)

tIn

-:::i

1n..J

Ww

be
zO

c..:::a:
c..w

<0

c::

In

Benefits of Feedback
The tolerances and drift coefficients of passive components
are much less than those associated with active components. If the circuit transfer function can be made to be
dependent only on the passive component parameters it will
be a much more stable circuit; feedback accomplishes this
through the direct gain as shown here. Differentiating the
closed loop Equation 4, with respect to the direct gain yields

Va = A1A2(VI+VO)+A2V1 +V2
V =
VI+VO +
V1/A1
+ V2/A1A2
o
1/(A1A2)+~ 1/(A1A2)+~ 1/(A1A2)+P

10-95

(EO. 20)
(EO. 21)

(EO. 22)

Application Note 9415
Now let Vo and V 1 represent the amplifier's internal noise
referred to the input, and let V2 represent the noise from the
any other system components. Notice from Equation 22 that
in the closed loop system V 2 has disappeared, V 1 is
decreased proportional to the gain A1 and that the input
noise has only been multiplied by the closed loop gain, 1/1J.
Conversely, Equation 20 indicates that in the open loop system the input noise has been multiplied by A1A2 (which
would be equivalent to the closed loop gain), that V1 is multiplied by A2 and that V 2 is present. The feedback in the
closed loop system has dramatically reduced the noise from
the sources which follow the amplifier A1 so this can become
a big design advantage. In the closed loop system the amplifier A1 should be selected for it's excellent noise performance, but the amplifier A2 can be selected based on some
other criteria such as cost. This option is not available in the
open loop system.
Very often when driving low impedances like speakers, the
output amplifiers are driven as close to the power supply
rails as possible to obtain the maximum dynamiC range. One
result of this practice. is that some distortion of the signal
occurs.as active device parameters are driven so that they
become nonlinear. This and most other sources of distortion
usually occur in the output stages of the amplifier. Because
the distortion occurs at the output it can be represented by
V2 in Equation 19, and this quantity goes to zero as the
direct gain approaches infinity, so it is essentially eliminated
by feedback. The connection from the speaker driver output
to the preamplifier input in audio amplifiers is there to provide the feedback which reduces the amplifier's distortion
when the amplifier is driven to its iimits. Some amplifiers
such as guitar amplifiers purposely introduce distortion into
the sound, so open loop amplifiers are used in these cases,
but closed loop amplifiers are usually employed in high fidelity applications.
If the noise source, V1, is set to zero in Equation 22, then the
amplifier input noise represented by Vo is multiplied by the
closed loop gain 1/1J. There is a method to further reduce the
effects of Vo by using frequency discrimination methods. If
Vo is examined as a function of frequency, it will be noticed
that the noise is made up of many different frequency components, see Figure 10.

SIGNAL
NOISE

The input and output impedance of the closed loop circuit
can be controlled by the amount of feedback and by the circuit configuration [4]. Through the use of feedback it is possible for the same amplifier IC to appear to have an output
impedance approaching zero or approaching infinity,
depending on the circuit configuration employed.
Another interesting aspect of feedback systems is that if a
function is put in the feedback loop, in a manner similar to
the feedback factor, IJ, the inverse function will appear at the
output.
Graphical Representation of the Feedback Equation
The mathematical manipulations required to analyze a feedback circuit are complicated because they involve multiplication and division; H. W. Bode [5] developed a technique called
a Bode plot which simplifies the analysis through the use of
graphical techniques. The Bode equations are log equations
which take the form of 20LOG(F(t)) = 20LOG(1 F(t) I) + phase
angle. Since these are log equations, the terms which were
multiplied and divided can be now added and subtracted;
thus, they can easily be solved graphically as will be shown.
The transfer function for the integrator shown in Figure 11 is
given in Equation 23.
'
VI

,'M

a

R

1-----.,

-- ..,,
---

FIGURE 11. INTEGRATOR CIRCUIT

Va

1

100Hz

(EQ.23)

Wheres=jroandj=~
NOISE REMOVED

...\

-~,

OdB

Ic

avo

-I"I = (1 + RCs)

dB

IDEAL FILTER

The signal of interest has a finite bandwidth, and if the noise
bandwi¢h is larger than the signal bandwidth, the noise can
be reduced by making the loop gain a function of frequency.
Assuming that the noise bandwidth is 10KHz and that the
signal bandwidth is 100Hz, the noise beyond 100Hz can be
reduced to a minimum if 1/1J is reduced to zero beyond
100Hz. One method available to accomplish this bandwidth
reduction is through the ideal filter inserted in the closed
loop, as shown in Figure 10. This filter can be approximated
with passive components.

F

The magnitude of the transfer function is given by the equation IVoN,1 = 1N(1+(RCro)2). The approximate magnitude
orlVoN,1 =1 when ro = 0.1/RC, IVoN,1 = 0.707 when ro =11
RC and IVoN,1 = 0.1 when ro = 10/RC. These values are
plotted in Figure 12 using straight line approximations.

10KHz

FIGURE 10. INSERTING AN IDEAL FILTER IN THE TRANSFER
FUNCTION REDUCES NOISE

10-96

Application Note 9415
ro = O.lIRC
ro = 1IRC
ro = 101RC
OdB r-__;;:;;;=:--r-----........-3dB

~

O~

~

-lidB

i

-2OdB

Ii;
~

-45 DEGREES

-90 DEGREES

,
--------------------

FIGURE 12. BODE PLOT OF INTEGRATING CIRCUIT
TRANSFER FUNCTION

The downward slope of the amplitude curve in Figure 12 is 20dB/decade, and the point at which the slope changes, at ro
1/RC, is termed the breakpoint. Reading the curve, it can
be seen that gain initially is one, OdB, at very low frequencies, falling off to 0.707, -3dB, at the break frequency and
decreases at a rate of -20dB/decade for higher frequencies.
The phase shift for the integrator is given in Equation 24 and
plotted in Figure 12. Notice that the phase shift is -45
degrees at the breakpoint where ro 1IRC.

=

(1/roRC)

I!:

(Ea. 24)

The band reject circuit shown in Figure 13 has two poles,
two zeros and a DC gain. Each pole and zero is plotted separately in Figure 14. The DC gain component is plotted as a
straight line at -6dB because it is frequency independent.
The two zeros in the numerator both occur at ro 1IRC; thus
they are plotted on top of each other, and this results in a
positive sloped line rising at 40dB/decade. The two poles in
the denominator occur at ro O.44IRC and ro 4.56/RC, and
they are each plotted with a negative slope of -20dBldecade.

=

=

=

_____

LOG(ro)

•
, ,-20dB/DECADE
ro =4.56/RC ,

, • -20dB/DECADE

'.

~

(1 + RCs)(l + RCs)

iii = 2(1 + RCs/O.44)(1 + RCs/4.56)

ro = 4.56/RC

i-----r---------

OdB ...-----;-__
-6dB

I-----l

+25 DEGREES

Ii;

ili

~...

+12 DEGREES
0.0 '""""____L-~L-----..L.--------....::!I-5 DEGREES

FIGURE 15. COMPOSITE BODE PLOT FOR THE BAND REJECT
FILTER

Spacing the poles and zeros by a decade enables an accurate phase plot using approximate methods, but the circuit
performance criteria usually will not allow this lUXUry. The
amplitude plot also becomes smeared by the close proximity
of the poles and zeros, but the exact values are not usually
plotted because the approximate values usually suffice for
analysis [6]. The demand for the phase accuracy stems from
the oscillation or stability criteria which is dependent on
phase.
Applying logarithms to the system equations will enable a
quick and rather complete analysis. Equation 4 is repeated
in Equation 26 in log form; i.e., both sides of the equation
have been operated on by the function 20LOG '0 (F(t)).

FIGURE 13. BAND REJECT FILTER CIRCUIT

=jro.

,,
ro =0.44/RC,

ro = O.44/RC ro = l/RC

When the breakpoint occurs in the denominator, its slope is
negative and is called a pole. Conversely, when the breakpoint occurs in the numerator, its slope is positive and it is
called a zero.

Where s

~._,

Each of the separate Bode plots shown in Figure 14 are
combined into one composite plot in Figure 15. The phase
plots are treated much like the amplitude plots because the
separate phase responses from the poles and zeros can be
combined into one plot such as is shown in Figure 15. Now
the complete amplitude or phase response of the circuit can
be observed by looking at Figure 15. Although the phase
shift at a pole is -45 degrees, the plot indicates -5 degrees at
ro = 0.441RC because the double zero located at ro = 1/RC
has already accumulated significant positive phase shift at
the pole frequency. The non-linearity of the phase plot, a
result of the tangent function, makes it hard to approximate
accurately when several poles and zeros congregate in the
same viCinity.

=

Vo

~.,

FIGURE 14. BODE PLOT OF THE INDIVIDUAL COMPONENTS
OF THE BAND REJECT FILTER

f

til = -tangenr '

____ ____- '

- - - -1- "' - - - - - - - - - -I - ... - - - - -

-dB

ODEGREES

ili
w

+40dB/DECADE

+dB

_____ _

(Ea. 25)

20LOG(VoIV1)

=20LOG(A) - 20LOG(1 + A(3)

(Ea. 26)

As would be expected from the preceding analysis, the
shape of the plot will be determined by the breakpoints, if
any, contained in A or [3.The magnitude portion of the closed

10-97

t-

en
-:J
C/)..J
Ww

be

zO

Q..:E
Q..W

«0

a::C/)

Application Note 9415
loop system equation is plotted in Figure 16 for the case
where A and ~ are not a function of frequency. Notice that
both plots are flat lines, and there is no phase plot. Obviously this case is trivial and of no interest to the circuit
designer because it does not represent the real world since
the gain of all amplifiers is a function of frequency [7).
dB

I!!

20LOG(A)

~

t

20LOG(1 + A~)

~
20LOG(Vo/V,)
LOG(f)
FIGURE 16. PLOT OF EQUATION 4 WHEN A AND ~ ARE NOT
FREQUENCY DEPENDENT

Most high gain amplifiers such as operational amplifiers have
multiple poles, two per transistor, with the amplifier having as
many as 20 transistors leading to a potential of 40 or more
poles. Normally only a few poles are important because the
other poles occur at very high frequencies where the gain is
less than one so that they can not cause oscillation. In many
amplifiers the manufacturer compensates the amplifier with a
single pole usually called a dominant pole (fAMP), and the
amplifier's performance can be approximated by the transfer
function A =a/(1 + j (f/fAMP)). Equation 4 is plotted in Figure
17 with the assumption that A is frequency dependent and ~ is
resistive or frequency independent.

20LOG(VOIV,}

100
80

dB
20LOG(A)

occurs at fAMP = 5Hz., and the DC gain is 11 OdB. If the transfer
function shown in Figure 17 was for the CA158 then the direct
gain would be A = a/(1 + j (lIfAMP))' or A = 316,227/(1 + j (115)).
Consider for a moment the difficulty and hence the probable
error associated with measuring the DC gain and the break
point. A popular method of measuring the op amp gain and
phase is to configure the op amp in the inverting mode and then
measure the error voltage; i.e., the voltage from the inverting
input to ground. Then Equation 3, E =Vol A, is employed to calculate the op amp gain from the measured error. Assume that
the op amp is configured in a gain of -100; then the direct gain
is A = 100/101 times the op amp gain so a small offset must be
accounted for because the measurement is not a direct measurement in the inverting circuit configuration. If the output voltage, Va, is kept small to guarantee small signal accuracy, say
one volt, then for the CA158, VERROR = 1/316,217=3.16IN.
Measuring this small voltage especially considering that noise
may be present is a formidable task so designers must assume
that there may be a considerable tolerance associated with
these measurements. The numbers given in this paper are for
explanation purposes; professional test engineers will often
configure the op amp with a gain of A = -10,000 and then be
measuring errors in the nana-volt range. These measurements
require considerable skill, and even then there may be a 24dB
difference between the minimum specification point and the
typical value such as in the HA5177 data sheet.

m
~ 60

I--"lt--"'~'Io..
20LOG(1 + A~) :
~:
,/x

.... "'"

z

~

1""0 ....

40

1-0.

20

'--------"-----'-:,,---'~---1
,
,"' .. LOG(f)
f=fAMP

r--0

~

'"

II:

-45 CI

0

e.'"

....

f3dB

Ii

-90~

-135i!:

=

FIGURE 17. PLOT OF EQUATION 4 WHEN A a/(1 + j (f/lAMP»
AND ~ IS FREQUENCY INDEPENDENT

H-++++-++H+-+-HH++-H-H-+-H+H-180

The closed loop gain graphical approximation is constant until
its projection intersects the amplifier gain at point X. The actual
closed loop gain starts rolling off prior to point X, and it is down
-3dB at point X. If 20LOG(Vo lV,) -20LOG(A) = -3dB then
-20LOG(1 + A~) =-3dB, and if the magnitude of (1 + A~) is considered, then the square root of (1 + (A~)2) = 1.414 resulting in
A~ = 1. In other words, A = 1~ at the intersection of the two
curves. There is a method [8) of relating the phase shift, and
thus the stability, to the slope of the curves at the intersect point,
but this method will not be covered here in favor of the Bode A~
method.
The dominant pole causes the open loop gain to have a breakpoint at the lrequency lAMP. The internally compensated op
amp acts like a dominant pole characteristic so its AC parameters can be determined by referring to the "Open-Loop Frequency Response" curve contained in the data sheet. Although
the curve is called "Open-Loop Frequency Response", it really
is the direct gain (A). Notice that the CA158 op amp as shown
in the Harris Semiconductor catalog [9) has a breakpoint which

1K

10K

100K

1M

10M

100M

FIGURE 18. OPEN LOOP FREQUENCY RESPONSE OF THE
HA2842C

Figure 18 is a plot of the gain phase relationship for a high
frequency op amp, the HA2842C. The DC gain is 9OdB, and
since the phase shift reaches -45 degrees at 1200Hz the
first pole must occur at approximately 1200Hz. This is a high
frequency op amp so the internal compensation capacitor
has been reduced significantly to increase the bandwidth
available to the designer, and it is apparent that a second
pole exists because the phase shift approaches -135
degrees at 70MHz. Looking closely at the point where the
gain crosses the OdB axis, and then following that constant
frequency line, 120MHz, down to the phase curve indicates
that the phase shift is about -165 degrees. This op amp is
marginally stable, and the op amp is susceptible to stability
problems unless external compensation techniques are
employed. The HA2842C can be modeled with a DC gain of

10-98

Application Note 9415
31,623, the first break point at 1200Hz and the secon.d
breakpoint at 145MHz. The equation for the HA2842C IS
then A 31 ,623/(1 + j (111200»)(1 + j (1I145E6».

of phase shift between the point where the loop gain equals
OdB and -180 degrees. Equation 29 defines the phase margin mathematically.

Stability as Determined from Loop Plots

<---+--"\--

LOG(t)

FIGURE 24. DOMINANT POLE COMPENSATION PLOT

Because of the loop gain loss and the bandwidth loss dominant pole compensation is only used inside the op amp,
when the closed loop bandwidth requirements are not great,
or if noise reduction is desired. A simpler method of compensating the op amp is with gain compensation. Consider
Equation 14 which is repeated here as Equation 42; this
equation is for the loop gain and it is valid for both inverting
and non-inverting op amps. If the closed loop inverting gain
is increased to 9, then Equation 42 becomes Al10 a
decrease of 20dB in the DC intercept. Plotting these results
in Figure 25 reveals that the circuit has become stable without much of a bandwidth reduction.
V,O

-

V,I

aZ 1
Zl +Z2

= - - = A~

(EQ.42)

dB

'--_-:-_ _ _ _ _;...

r

20LOG(AP)

+
t -20dB

OdB

ORIGINAL OP AMP

,-- CURVE

en
en .....

be

«0

ii:

en

I

'---------i---A-\--

LOG(t)

FIGURE 25. GAIN COMPENSATION

The occasion always arises where the closed loop gain must
be one or less, thereby precluding the use of gain compensation; thus the designer must resort to other techniques to
achieve the circuit performance. An alternate method of

10-101

Ww

zO
c..==
c..w

'---

COMPENSATED OP
AMPCURVE

FIGURE 23. EXAMPLES OF DOMINANT POLE COMPENSATION

I-

-:i

Application Note 9415
compensation is called lead compensation, and it consists of
putting a zero in the loop transfer function to cancel out one
of the poles. The best place to locate the zero is on top of the
second pole, since this cancels the negative phase shift
caused by the second pole. The schematic of a circuit which
employs lead compensation is shown in Figure 26, and
Equation 43 is for the loop transfer function.

I.

dB

FIGURE 26. LEAD COMPENSATION

The zero in Equation 43 occurs before the pole, so it can be
used to cancel out the pole at 111:2 by placing the zero on top
of the pole. Now the 135 degree phase shift point has moved
out to 1/RFIIR,Cs yielding better phase margin. There are
always compromises to be made when designing a feedback
circuit, and the one made here is to add external components. If the op amp has additional poles close to 1/t2, and
many op amps do, then the pole placement is critical. Some
op amps have so many poles in the area of 1/t2 that this
method of compensation cannot be used.

A~

(EO. 43)

_ aRI
(RFCs + 1)
- RI + RF(RIIIRFCs + 1)

Unless specified otherwise, the amplifier gain (a) will be
assumed to have the form a K/(l + t1s)(1 + t~).

i
ca
~
~

if

dB

!. .
t£

'i:

t

I
I

ORIGINAL
TRANSFER
FUNCTION

..,

2OLOG(AP)

I..

LOG(f)
..

: --~-E~~~~~:

- - - - -

- - - -'- - - or - - - -

-

:::..::./- -

-----~---O~I~I;A~

MODIFIED

: -- ---....

NoC F:
A~

=

aRI

1

R, + RFl + R,IIRFCs

a(R,C IS+l)

A~=--'R'I--~--'R'F---

,

(EO. 44)

(EO. 45)

LOG(f)

FIGURE 27. LEAD COMPENSATION PLOT

Sometimes a good look at the problem reveals a potential
solution, so the case of stray input capacitance will be investigated. An inverting amplifier with a stray input capacitance,
CI, Is shown in Figure 28. Looking at Equation 44 for the
open loop transfer function, it is obvious that the stray capacitance adds a pole to the transfer function, and if the added
pole is close to 1i't2 the circuit will become unstable. The
capacitor, CF shown in dotted lines, is added to the circuit to
yield the transfer function shown in Equation 45. Inspection
of Equation 45 reveals that if RIC I RFC F, then the poles
and zeros in the transfer function will cancel each other, and
the transfer function will appear to be independent of frequency. This type of compensation is named after the same
idea used In the compensated attenuator, which is an old
instrument design trick. Which just proves that little in circuit
design is really new.

=

-180

:

11't2 lIRllIRFCs

I

MODIFIED
TRANSFER
FUNCTION

(R,C,s + 1) + (RFCFS + 1)

~B ~-----------r-----T~~--~~~

,

-45
-135

I
I

FIGURE 28. COMPENSATED ATTENUATOR CIRCUIT
SCHEMATIC, GAIN PLOT AND PHASE PLOT

~,~

N

OdB

r

I
I

C F in circuit:

MODIFIED
TRANSFER
FUNCTION

I

I

TRANSFER
FUNCTION

=

"it
~

ORIGINAL
TRANSFER FUNCTION

There are times when an extra degree of freedom is required
and the lead-lag, sometimes called the feed-forward, form of
compensation yields this freedom. This method of compensation puts a pole and a zero in the loop transfer function. If
the pole and zero locations must be independent of each
other, then separate compensation networks need to be
used. An example of this would be to use a lag circuit similar
to that shown in Figure 24, and a lead circuit similar to that
shown in Figure 26. The lead and lag would then be independent in the example so they could be placed conveniently for compensation purposes. The circuit shown in
Figure 29 has both a pole and a zero, but their placement is
not independent.

A~

10-102

=

aRI
(RCs + 1)
RI + RF(RR I + RFR + RFR I )
R
R
Cs+l
F+ I

(EO. 46)

Application Note 9415
Comparison of Compensation Results

c

AMPLITUDE

OdB

1-....,.-.......,---ir-~4..--

LOG(t)

FIGURE 29. LEAD-LAG COMPENSATION SCHEMATIC AND A~
AMPLITUDE PLOT

Referring to Figure 29, it can be seen that the lead-lag compensated circuit crosses OdB at a lower frequency than the
uncompensated circuit, thus the compensation has made
the circuit more stable. Also, the transfer function of the compensation has been shown in Figure 29 for clarity. There is
an additional advantage to lead-lag compensation in that it
yields higher gain at high frequencies. The closed loop gain
plots, Figure 30, show that the zero precedes the pole; the
poles and zeros interchange when the plot changes from the
loop gain to the closed loop gain. Also, the high frequency
gain is emphasized with lead-lag compensation. The high
frequency emphasis may be desirable when a high overall
gain is needed, but some unwanted effects, such as DC offset, must be minimized. The lead-lag method of compensation usually requires the precise placement of the poles and
zeros so a detailed and accurate [12] phase plot is generally
constructed for this case.

20LOG(A)

l-+-o!-oV

20LOG(RPR~ I-~""""'--""~"--CLOSED LOOP
L-+--r-r____-r__~~~U~N~COMPENSATED
I

1/(R+RI)C

FIGURE 30. LEAD-LAG CLOSED LOOP GAIN PLOTS FOR COMPENSATED AND UNCOMPENSATED CIRCUITS

Dominant pole compensation is the easiest method of
compensation to implement within an IC, but it rolls off the
closed loop gain so quickly that it is seldom used except in
op amp design. The circuit resulting from dominant pole
design is very well behaved because the phase margin is
usually about 45 degrees, but the frequency response is
very poor. If the transfer function for the HA2842C shown in
Figure 18 is compensated by dominant pole compensation,
the pole would be placed at 1200Hz; the loop gain when
moving to a lower frequency would then rise at a rate of
20dB/decade until it hit the 90dB point at 0.06Hz. This is an
effective bandwidth reduction of 4.5 decades, from 120MHz
to 1200Hz, so this method is only used when no other type
of compensation is available, noise reduction is more important than bandwidth or bandwidth is not important.
Gain compensation is always the preferred method of
compensation if the resulting higher closed loop gain meets
the performance criteria, but many times the design specifi·
cations call for a buffer or an inverter both with a gain of one,
which precludes gain compensation. Gain compensation
does not require any additional external components beyond
the gain setting resistors, it preserves the op amp bandwi,dth
and it is easy to implement. In a single pole system, increasing gain will reduce the bandwidth by the same factor.
Lead compensation offers an AC compensation which can
function for any DC gain, and it is has a much higher
frequency response than dominant pole compensation. One
deficiency with lead compensation is that the DC gain, the
zero and the pole are all tied together tightly. For example if
the HA2842C shown in Figure 18 is lead compensated for a
closed loop gain of -1 then RI = R F, This means that the pole
and zero are only separated by an octave so the compensation must be done in an area of the loop gain plot which is very
close to OdB, Observing Figure 18, it can be seen that the
best place that lead compensation can improve stability significantly is at the second pole where the phase equals -135
degrees phase shift and the frequency is 75MHz. Placing the
zero at 75MHz yields a phase margin of about 60 degrees
resulting a nice stable circuit with 10% overshoot per Figure
22, The closed loop response equation is VINF = R/RI11
(R~s + 1), and the closed loop gain is -1 until it reaches the
frequency f =1/27tRFC, 150MHz, where it is down by -3dB.
Lead compensation rolls off the closed loop frequency
response dramatically.
The compensated attenuator approach works well for negating the effects of an input capacitance because both the
open loop and closed loop transfer functions have a flat
frequency response. Also, the compensation required is very
small. When the output resistance of an op amp gets very
high, the stray capacitance seen across the resistor acts like
a lead circuit and rolls off the high frequency gain. Adding an
input capacitor, the reverse of attenuator compensation,
serves to restore the high frequency performance. Both
digital-to-analog converters and optical receiving diodes

10-103

t;

-:J
(/)..1
Ww

be

zO

a.::i!:
a.w
CS:O

a::

(/)

Application Note 9415
have large associated capacitances, so when they are put
into the input circuit of an op amp, often in an I-to-V converter configuration, the circuit oscillates. The compensated
attenuator tames these circuits, but beware, the compensation must consider the worst case especially for current
DACs which have a wide range of output capacitance.
The lead-lag compensation scheme is very similar to the
lead compensation scheme but it has two advantages. First,
setting the DC gain does not fix the pole zero separation, so
for low gains the pole and zero could be separated by more
than an octave. Second, a zero shows up in the closed loop
transfer function where it increases the gain at high frequencies. The combination of these two advantages are great
enough to outweigh the cost of the extra components added
to the circuit.
The compensation techniques demonstrated here serve as
a good foundation for feedback circuit design, but like all
foundations it is meant to be built on [13]. There are other
methods of treating compensation such as closed loop stability plots, Nichols charts, root locus plots and Nyquist analysis. Each technique offers some advantages and
disadvantages; the Bode method simply is the author's personal choice so the other techniques deserve investigation.

References
[1] Areocentric, Sol, Feedback Amplifier Principles,
Mac,millan Publishing Company, 1986.
[2] Del Toro, Vincent and Parker, Sydney, Principles of
Control Systems Engineering, McGraw-Hili Book
Company, 1960.
[3] Del Toro, Vincent and Parker, Sydney, Principles of
Control Systems Engineering, McGraw-Hili Book
Company, 1960.
[4] DiStefano, Joseph, Stubberud, Allen and Williams, Ivan,
Theory and Problems of Feedback and Control
Systems, Schaum's Outline Series, McGraw-Hili Book
Company, 1967.
[5] Bode H. W., Network Analysis and Feedback Amplifier
Design, D. Van Nostrand, Inc., 1945.
[6] D'Azzo, John and Houpis, Constantine, Feedback
Control System Analysis and Synthesis, McGraw-Hili
Book Company, 1966.
[7] Frederiksen, Thomas, Intuitive Operational Amplifiers,
McGraw-Hili Book Company, 1988.
[8] Bower, J. L. and Schultheis, P. M., Introduction to the
Design of Servomechanisms, Wiley, 1961.
[9] Harris Semiconductor, Linear and Telecom ICS for
Analog Signal Processing Applications, 1993-94.
[10] Same as above.
[11] Del Toro, Vincent and Parker Sydney, Principles of
Control Systems Engineering, McGraw-Hili Book
Company, 1960.
[12] Kuo, Benjamin, Automatic Control Systems, PrenticeHall, Inc., 1975.
[13] Bell, Ken, Conversations about feedback circuits while
at Charles Stark Draper Labs, 1971.

10-104

Harris Semiconductor

----No. AN9420.1

--------- ---- --- - - - -

--

----

- --

-

Harris Linear

April 1995

Current Feedback Amplifier
Theory and Applications
Authors: Ronald Mancini and Jeffrey Lies

Introduction
Current feedback amplifiers (CFA) have sacrificed the DC
precision of voltage feedback amplifiers (VFA) in a trade-off
for increased slew rate and a bandwidth that is relatively
independent of the closed loop gain. Although CFAs do not
have the DC precision of their VFA counterparts, they are
good enough to be DC coupled in video applications without
sacrificing too much dynamic range. The days when high frequency amplifiers had to be AC coupled are gone forever,
because some CFAs are approaching the GHz gain bandwidth region. The slew rate of CFAs is not limited by the linear rate of rise that is seen in VFAs, so it is much faster and
leads to faster riselfall times and less intermodulation
distortion.
The general feedback theory used in this paper is developed
in Harris Semiconductor Application Note Number AN9415
entilled "Feedback, Op Amps and Compensation." The
approach to the development of the circuit equations is the
same as in the referenced application note, and the
symbology/terminology is the same with one exception. The
impedance connected from the negative op amp input to
ground, or to the source driving the negative input, will be
called ZG rather than Zl or ZI, because this has become the
accepted terminology in CFA papers.

Development of the General Feedback Equation
. Referring to the block diagram shown in Figure 1, Equation 1,
Equation 2 and Equation 3 can be written by inspection if it is
assumed that there are no loading concerns between the
blocks. This assumption is implicit in all block diagram calculations, and requires that the output impedance of a block be
much less than input impedance of the block it is c;lriving. This
is usually true by one or two orders of magnitude. Algebraic
manipulation of Equation 1, Equation 2 and Equation 3 yields
Equation 4 and Equation 5 which are the defining equations
for a feedback system.
VO=EA

(EO. 1)

E = VI -I3Vo

(EO. 2)

E=VdA

(EO. 3)

VOIVI = A/(1 + AI3)

(EO. 4)

EIVI = 1/(1 + AI3)

(EO. 5)

Copyright

A

t - -......--o

Vo

FIGURE 1. FEEDBACK SYSTEM BLOCK DIAGRAM

In this analysis the parameter A, which usually Includes the
amplifier and thus contains active elements, is called the direct
gain. The parameter 13. which normally contains only pasSive
components, is called the feedback factor. Notice that in Equation 4 as the value of A approaches infinity the quantity AI3.
which is called the loop gain, becomes much larger than one;
thus, Equation 4 can be approximated by Equation 6.
VO/VI = 1/~

forA~ »1

(EO. 6)

VOIVI is called the closed loop gain. Because the direct gain,
or amplifier response, is not included in Equation 6, the closed
loop gain (for A » 1) is independent of amplifier parameter
changes. This is the major benefit of feedback circuits.
Equation 4 is adequate to describe the stability of any feedback circuit because these circuits can be reduced to this
generic form through block diagram reduction techniques [1].
The stability of the feedback circuit is determined by setting
the denominator of Equation 4 equal to zero.
1 +AI3= 0
AI3 = -1 = 111 L.:11m

(EO. 7)
(EO. 8)

Observe from Equation 4 and Equation 8, that if the magnitude of the loop gain can achieve a magnitude of one while
the phase shift equals -180 degrees, the closed loop gain
becomes undefined because of division by zero. The undefined state is unstable, causing the circuit to oscillate at the
frequency where the phase shift equals -180 degrees. If the
loop gain at the frequency of oscillation is slightly greater than
one, it will be reduced to one by the reduction in gain suffered
by the active elements as they approach the limits of saturation. If the value of AI3 is much greater than one, gross non linearities can occur and the circuit may cycle between
saturation limits. Preventing instability is the essence of feedback circuit design, so this topic will be touched lightly here
and covered in detail later in this application note.

© Harris Corporation 1995
10-105

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r are different for NPN and PNP transistors, so ZB also is a function of the polarity of the output.
Refer to Figure 12 and Figure 13 for plots of the transimpedance (Z) and ZB for the HA5020 [5]. Notice that Z starts to
level off at 20MHz which indicates that there is a zero in the
transfer function. ZB also has a zero in its transfer function
located at about 65MHz. The two curves are related, and it is
hard to determine mathematically exactly which parameter is
affecting the performance, thus considerable lab work is
required to obtain the maximum performance from the device.

=

=

=

10-108

0.01

0.1

10

100

FREQUENCY (MHz)

FIGURE 12. HA5020 TRANSIMPEDANCE vs FREQUENCY

Application Note 9420
Equation 27 yields an excellent starting point for designing a
circuit, but strays and the interaction of parameters can
make an otherwise sound design perform poorly. After the
math analysis an equal amount of time must be spent on the
circuit layout if an optimum design is going to be achieved.
Then the design must be tested in detail to verify the performance, but more importantly, the testing must determine that
unwanted anomalies have not crept into the design.

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The CFA's transimpedance, which is also a function of frequency, shows up in both the loop gain and closed loop gain
equations, Equations 18 and 22. The gain setting impedances, ZF and ZG, do not appear in the loop gain as a ratio
unless they are multiplied by a secondary quantity, lB' so IF
can be adjusted independently for maximum bandwidth. This
is why the bandwidth of CFA's are relatively independent of
closed loop gain. When ZB becomes a significant portion of
the loop gain the CFA becomes more of a constant gainbandwidth device.
Equation 5, which is rewritten here as Equation 29,
expresses the error signal as a function of the loop gain for
any feedback system. Consider a VFA non-inverting configuration where the closed loop gain is + 1; then the loop gain,
Ail, is a. It is not uncommon to have VFA amplifier gains of
50,000 in high frequency op amps, such as the HA2841 [61,
so the DC precision is then 100% (1/50,000) = 0.002%. In a
good CFA the transimpedance is Z = 6MQ, but ZF =1 k.Q so
the DC precision is 100% (1075Q/6MQ) = 0.02%. The CFA
often sacrifices DC precision for stability.

.... r-'

38
36

~
a:;

(EO. 29)
2

4

6 8 10
20
FREQUENCY (MHz)

40

60 80100

FIGURE 13. HA5020 INPUT BUFFER OUTPUT RESISTANCE VB
FREQUENCY

Performance Analysis
Table 1 shows that the closed loop equations for both the CFA
and VFA are the same, but the direct gain and loop gain equations are quite different. The VFA loop gain equation contains
the ratio ZrdZ" where Z, is equivalent to ~, which is also contained in the closed loop gain equation. Because the loop gain
and closed loop equations contain the same quantity, they are
interdependent. The amplifier gain, a, is contained in the loop
gain equation so the closed loop gain is a function of the
amplifier gain. Because the amplifier gain decreases with an
increase in frequency, the direct gain will decrease until at
some frequency it equals the closed loop gain. This
intersection always happens on a constant -20dB/
decade line in a single pole system, which is why the VFA is
considered to be a constant gain bandwidth device.
TABLE 1. SUMMARY OF OP AMP EQUATIONS
CURRENT
FEEDBACK
AMPLIFIER

VOLTAGE
FEEDBACK
AMPLIFIER

Z(l +ZrdZG)
ZF(l + ZsfZF IIZG)

a

ZlZF(l + ZsfZFIIZG)

aZQI(ZG+~)

1 +ZrdZG

1 +ZrdZG

Direct Gain

Z
ZG(l + ZsfZFIIlQ)

aZrJ(ZF + ZG)

Loop Gain

ZlZ F(l + ZsfZFIIlQ)

aZQI(ZG + ZF)

-ZrdZG

-ZrdZG

CIRCUIT
CONFIGURATION
NON-INVERTING
Direct Gain

Loop Gain
Closed Loop Gain

The VFA input structure is a differential transistor pair, and
this configuration makes it is easy to match the input bias
currents, so only the offset current generates an offset error
voltage. The time honored method of inserting a resistor,
equal to the parallel combination of the input and feedback
resistors, in series with the non-inverting input causes the
bias current to be converted to a common mode voltage.
VFAs are very good at rejecting common mode voltages, so
the bias current error is cancelled. One input of a CFA is the
base ierminal of a transistor while the other input is the output of a low impedance buffer. This explains why the input
currents don't cancel, and why the non-inverting input
impedance is high while the inverting input impedance is
low. Some CFAs, such as the HFAl120 [7], have input pins
which enable the adjustment of the offset current. Newer
CFAs are finding solutions to the DC precision problem.
Stability Calculations for Input Capacitance

INVERTING

Closed Loop Gain

The DC precision is the best accuracy that an op amp can
obtain, because as frequency increases the gain, a, or the
transimpedance, Z, decreases causing the loop gain to
decrease. As the frequency increases the constant gainbandwidth VFA starts to lose gain first, then the CFA starts
to lose gain. There is a crossover point, which is gain dependent, where the AC accuracy for both op amps is equal.
Beyond this point the CFA has better AC accuracy.

When there is a capacitance from the inverting input to
ground, the impedance ZG becomes RG/(RGCGs+l), and
Equation 14 can be written in the form of Equation 30. Then
the new values for lG are put into the equation to yield
Equation 31. Notice that the loop gain has another pole in it:
an added pole might cause an oscillation if it gets too close
to the pole(s) included in Z. Since ZB is small it will dominate
the added pole location and force the pole to be at very high
frequencies. When CG becomes large the pole will move in
towards the poles in Z, and the circuit may become unstable.

10-109

(EO. 30)

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Application Note 9420
If ZB = RB, ZF = Rf; and Za = RallCa , Equation 30 becomes:
(Ea. 31)

Notice that if the zero cancelled the pole in equation that the
circuit AC response would only depend on Z, so Equation 34
is arrived at by doing this. Equation 35 is obtained by algebraic manipulation.

Stability Calculations for Feedback Capacitance

(RFCFS + 1) = (RBIIRFIIRa(C F + Ca)S+ 1)

(Ea. 34)

When a capacitor is placed in parallel with the feedback resistor, the feedback impedance becomes ZF RP'(RFCFS + 1).
After the new value of ZF is substituted into Equation 30, and
with considerable algebraic manipulation, it becomes Equation 32.
Z(RFCFs+ 1)
AP= RF(l + (RB/RFIIRa)(RBIIRFIIRaCFs + 1)
(Ea. 32)

RFC F= CaRaRB/(Ra + RB)

(Ea. 35)

=

The new loop gain transfer function now has a zero and a
pole; thus, depending on the placement of the pole relative
to the zero oscillations can result.
2OLOGIZI - 20LOGIR F (1 + Ra/RFIIRG)I

I

; - - POLEIZERO
CURVE

\\

\1

cOMPOsrrE
CURVE

\
\
\
\

o L----....L-----'-~-....:\T""\-

LOG (I)

FIGURE 14. EFFECT OF C F ON STABILITY

The loop gain plot for a CFA with a feedback capacitor is
shown in Figure 14. The composite curve crosses the OdBn
axis with a slope of -40dBldecade, and it has more time to
accumulate phase shift, so it is more unstable than it would
be without the added poles and zeros. If the pole occurred at
a frequency much beyond the highest frequency pole in Z
then the Z pole would have a chance to roll off the gain
before any phase shift from Z could add to the phase shift
from the pole. In this case, CF would be very small and the
circuit would be stable. In practice almost any feedback
capacitance will cause ringing and eventually oscillation if
the capacitor gets large enough. There is the case where the
zero occurs just before the A~ curve goes through the OdBn
axis. In this case the positive phase shift from the zero cancels out some of the negative phase shift from the second
pole in Z: thus, it makes the circuit stable, and then the pole
occurs after the composite curve has passed through OdBn.
Calculations and Compensation for CG and CF
Za and ZF are modified as they were in the previous two sections, and the results are incorporated into Equation 30,
yielding Equation 33.
AP=

Z(RFCFs+ 1)
(Ea. 33)
RF(l + RB/RFIIRa)(RBIIRFIIRa(CF + Ca)S + 1)

Beware, RB is a frequency sensitive parameter, and the
capacitances may be hard to hold constant in production, but
the concept does work with careful tuning. As Murphy's law
predicts, any other combination of these components tends
to cause ringing and instability, so it is usually best to minimize the capacitances.
Summary
The CFA is not limited by the constant gain bandwidth phenomena of the VFA, thus the feedback resistor can be
adjusted to achieve maximum performance for any given
gain. The stability of the CFA is very dependent on the feedback resistor, and an excellent starting point is the device
data sheet which lists the optimum feedback resistor for various gains. Decreasing RF tends to cause ringing, possible
instability, and an increase in bandwidth, while increasing RF
has the opposite effect. The selection of RF is critical in a
, CFA design; start with the data sheet recommendations, test
the circuit thoroughly, modify RF as required and then test
some more. Remember, as ZF approaches zero ohms, the
stability decreases while the bandwidth increases; thus,
placing diodes or capaCitors across the feedback resistor will
cause oscillations in a CFA.
The laboratory work cannot be neglected during CFA circuit
design because so much of the performance is dependent
on the circuit layout. Much of this work can be simplified by
starting with the manufacturers recommended layout; Harris
Semiconductor appreCiates the amount of effort it takes to
complete a successfulCFA design so they have made evaluation boards available. The layout effort has already been
expended in designing the evaluation board, so use it in your
breadboard; cut it, patch it, solder to it, add or subtract components and change the layout in the search for excellence.
Remember ground planes and grounding technology! These
circuits will not function without good grounding techniques
because the oscillations will be unending. Coupled with
good grounding techniques is good decoupling. Decouple
the IC at the IC pins with surface mount parts, or be prepared to fight phantoms and ghosts.
Several excellent equations have been developed here, and
they are all good design tools, but remember the assumptions. A typical CFA has enough gain bandwidth to ridicule
most assumptions under some conditions. All of the CFA
parameters are frequency sensitive to a degree, and the art
of circuit design is to push the parameters to their limit.
Although CFAs are harder to design with than VFAs, they
offer more bandwidth, and the DC precision is getting better.
They are found in many different varieties; clamped outputs,
externally compensated, Singles, duals, quads and many
special functions so it is worth the effort to learn to design
with them.'

10-110

Application Note 9420
References
[1] Del Toro, Vincent and Parker, Sydney, "Principles of
Control Systems Engineering", McGraw-Hail Book
Company, 1960
[2] Bode H.W., "Network Analysis and Feedback Amplifier
Design", D. VanNostrand, Inc., 1945
[3] Harris Semiconductor, Application Note 9415, Author:
Ronald Mancini, 1994
[4] Jost, Steve, "Conversations About the HA5020 and CFA
Circuit Design", Harris Semiconductor, 1994
[5] Harris Semiconductor, "Linear and Telecom ICs for
Analog Signal Processing Applications", 1993 - 1994
[6] Harris Semiconductor, "Linear and Telecom ICs for
Analog Signal ProceSSing Applications", 1993 - 1994

[7] Harris Semiconductor, "Linear and Telecom ICs for
Analog Signal Processing Applications·, 1993 - 1994

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10-111

Harris Semiconductor

-----

------- --- --

-------- ----

-----

----

No. AN9502.1

- -

- --

Harris Linear

November 1996

Oscillator Produces Quadrature Waves (HA5025)
Author: Ronald Mancini
By employing a high-frequency quad current-feedback
amplifier (the HA5025) as an RC oscillator, four quadrature
sine waves can be generated, see Figure 1. The HA5025's
four separate amplifiers generate the sine waves, while the
quad NAND gate, U2, is biased at its threshold, so it acts as
a sine-wave to square-wave converter when the sine waves
are AC·coupled into its input.
The criterion for oscillation is that the open-loop gain be ~1
when the feedback phase shift is zero. In this design, there
are three noninverting phase-shifting stages and one inverting phase-shift stage (U1O); thus the phase shift of each
stage must equal 45 degrees lag. This phase shift plus the
180 degrees introduced by the phase inversion of U1D
equals 360 degrees or 0 degrees, resulting in in-phase feedback at the oscillation frequency.

Because the HA5025 features such high open-loop gainbandwidth characteristics, amplifier phase shift is negligible in
the low MHz range. Thus, each stage's phase shift is solely
determined by the passive components. At 4> 45 degrees,
R3Cl = RSC2 = 1/(27t1); the component values shown for
f = 1MHz. The rate of change of phase shift with respect to
frequency (d$ldf) is maximum at 4> 45 degrees for this type
RC circuit. Therefore, the stability is highest for the four-RC
configuration. The combination of good phase sensitivity with
no active amplifier phase shift yields a stable RC oscillator
whose temperature performance depends only on passive
compbnents.

=

=

Most RC oscillators described in the literature employ a lead
circuit as the phase-shifting element. While that practice is
fine for voltage-feedback amplifiers, it results in multiple

RIA

1100

OUT1

OUT2
OUT3

NOTES:
1. Diodes are 1N4148

OUT4

RSA-C

2. U1 • HAS025, U2 = CD74ACOO

10K

O-WH....--o

DISABLE

FIGURE 1. FOUR QUADRATURE SINE WAVES CAN BE GENERATED WITH THIS OSCILLATOR DESIGN, WHICH USES THE
HA5025 HIGH-FREQUENCY QUAD CURRENT-FEEDBACK AMPLIFIER. THE FOUR SEPARATE AMPLIFIERS
PRODUCE THE FOUR SINE WAVES.

Copyright © Harris Corporation 1996

10-112

Application Note 9502
frequency oscillations in current-feedback amplifiers
because of their ideal gain flatness performance. The voltage-feedback amplifier's gain rapidly falls off at higher frequencies, preventing oscillation beyond the design
frequency. This also is an indicator of the deleterious phase
performance associated with the voltage-feedback amplifier.
Because the voltage gain of each RC network is 0.707, the
noninverting amplifiers are arbitrarily set at gain of 1.6; the
inverting stage over all gain also is slightly above one at
1MHz. By distributing the gain over four amplifiers, the

resultant open-loop gain can be well controlled. As a result,
with the aid of Rs , D1 , and D2 , the amplitude limiting can be
limited to minimize sine-wave distortion: Rather good sinewave outputs are available across C1A, C 1B, C1e, and the
output of U1D. This RC concept can be extended to well
above 20MHz using the HA5025 with just a slight frequency
drift. The quadrature sine waves are AC-coupled to a quad
CMOS gate biased at its threshold by R7 and Rs to obtain
quadrature square waves. If these square waves aren't
exactly 45 degrees phase-shifted from each other, adjust the
bias circuit or add independent bias networks.

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10-113

Harris Semiconductor

----No. AN9503.1

-

-----

-

Harris Linear

November 1996

Low Output Impedance MUX (HA5022)
Author: Ronald Mancini
Two common problems will surface when trying to multiplex
multiple high-speed signals into a low-impedance load, such
as an analog-to-digital converter. The first is the low load
impedance, which tends to make amplifiers oscillate and
thus causes gain errors. The second problem involves the
multiplexer, which supplies no gain, introduces distortion,
and limits the frequency response.
Using op amps that have an enable/disable function, such as
the HA5022, will eliminate the multiplexer problems. That's
because the external multiplexer chip isn't needed, and the
HA5022 can drive low-impedance (large capacitance) loads
if a series isolation resistor is employed.
Looking more closely at the circuit, both inputs are terminated in their characteristic impedance; 750 is typical for
video applications, see Figure 1. Because the output cables
usually are terminated in their characteristic impedance, the
gain is 0.5. Consequently, amplifiers U2A and U2B are configured in a gain of +2 to set the circuit gain at 1. R2 and R3
determine the amplifier gain; if a different gain is desired, R2
should be changed according to the equation:
G = (1 + R~R2).

R3 sets the amplifier's frequency response, so it's best to
check the manufacturer's data sheet before changing its
value.
R5 , C1 , and D1 make up an asymmetrical charge/discharge
time circuit that configures Ul as a break-before-make
switch to prevent both .amplifiers from being active simultaneously. If this design is extended to more channels, the
drive logic must be designed to be break-before-make. Also,
the inhibit input is only functional when the channel switch
input is high. R4 is enclosed in the feedback loop of the
amplifier so that the large open-loop amplifier gain of U2 will
present the load with a small closed-loop output impedance
while keeping the amplifier stable for all values of load
capacitance.
The circuit shown was tested for the full range of capacitor
values with no oscillations observed. Thus, the problem is
solved. The circuit's frequency and gain characteristics are
now those of the amplifier independent of any multiplexing
action. This essentially solves the second problem. The multiplexer transition time is approximately 151JS with the component values shown.

INPUTB _ - - - -.....- - - - - - - ,

-sv

INPUT A _ _~-----__,,......-__,
DIA

1N4148

CHANNEL
SWITCH

----t
+5V 27

~~!5'-,.....W'-r-T----'..;!: O.Ol!1F

NOTES:
1. U2: HA5022

INHIBIT _,...,.....,

2. Ul: CD4011

FIGURE 1. THIS LOW-oUTPUT IMPEDANCE MULTIPLEXER WILL SOLVE PROBLEMS OF OSCILLATION CAUSED BY LOW LOAD
IMPEDANCE, AS WELL AS DISTORTION AND UMITED FREQUENCY RESPONSE INTRODUCED BY THE MULTIPLEXER.
THE SECOND PROBLEM IS SOLVED BECAUSE THE FREQUENCY AND GAIN CHARACTERISTICS BECOME THOSE OF
THE AMPUFIER, INDEPENDENT OF THE MULTIPLEXER.
Copyright © Harris Corporation 1996

10-114

Harris Semiconductor

--------- -- ------- --- --- ----- ---

- -

No. AN9507.1

Harris Linear

November 1996

Video Cable Drivers Save Board Space, Increase Bandwidth
(HFA1112, HFA1114)
Author: Jeff Lies
Designing video cable drivers seems to be a fairly simple
task. Just buy an amplifier with enough bandwidth, high
output current, a gain of two or greater (eliminating most
buffers) to counteract attenuation from back-terminating the
cable, and good video specifications (gain flatness if you are
designing for component video; differential gain and phase if
you are designing for composite video), and you're in
business.

Of course, picking a current feedback amplifier adds a few
additional worries such as choosing the optimum feedback
resistor, and minimizing the capacitance on both the summing node (-Input) and output. Still another problem is
achieving the desired performance at typical video loads
(~75n if driving multiple back-terminated cables).
Choosing dual or quad amplifiers and/or SOIC packaging
complicates the equation even further. How does the
engineer find a way to optimally place eight gain-setting
resistors, not to mention termination resistors, around a
quad amplifier in an SOIC package? There is no easy
solution. Compromises must be made, which usually result
in inadequate terminations or long trace lengths.

!;
!;

...

OdB

~

It's true that circuit performance changes when driving cables,
but is it really the cable driver that is at fault? Figure 1
illustrates the performance of Harris Semiconductor's
HFA1112 amplifier driving 100 feet of back-terminated cable.
It shows that the amplifier's 550MHz bandwidth decreases to
40MHz over the measured range, lending credence to the
previous hypothesis. But what's really happening?

0

r-- ....

10

C -3dB

u

Ie

A common complaint when working with long cables
involves a particular type of image degradation. The display
in question exhibits bright horizontal lines but gray vertical
lines. Since it is well known that narrow vertical lines require
higher bandwidth to be displayed properly, the bandwidth
obviously is being limited somewhere in the system. Invariably, substituting a shorter cable dramatically improves the
image quality, leading to the hypothesis that the cable
driver's performance degrades when driving long cables.
This hypothesis requires some scrutiny.

!;
...
!;

3dB

0

Specialized ICs can simplify the task of cable driver design
and board layout. However, even the best cable driver can't
solve all problems.

~

«
CJ

OdB

10

C -3dB

:"'

-IIdB

z

III

3dB

r-

....

u

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III

RESPONSE OF
CABLE ONLY

II

-6dB

~~
~~

z

«CJ

1'1..

RESPO~SE ~

~

OF
HFA1112 AND _
CABLE

11111
1MHz

10MHz
FREQUENCY

1MHz

100MHz

FIGURE 1. PERFORMANCE RESULTS INDICATE THAT THE
HFA1112 AMPLIFIER'S 550MHz BANDWIDTH
DECREASES TO 40MHz WHEN DRIVING 100 FEET
OF BACK-TERMINATED CABLE. THIS SUPPORTS
THE HYPOTHESIS THAT A CABLE DRIVER'S
PERFORMANCE DEGRADES WHEN DRIVING
LONG CABLES.

Copyright

10MHz
FREQUENCY

, , ,-

100MHz

FIGURE 2. ALTHOUGH USUALLY TAKEN FOR GRANTED,
LONG CABLES CAN LIMIT SYSTEM BANDWIDTH
TO LOW FREQUENCIES, AS IS EVIDENT IN THIS
COMPARISON BETWEEN THE FREQUENCY
RESPONSE OF THE HFA1112 DRIVING THE
CABLE AND THE RESPONSE OF THE CABLE
ALONE.

© Harris Corporation 1996
10-115

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Application Note 9507
Many engineers forget that all electrical elements have finite
bandwidth. Cables are usually taken for granted, but long
cables can limit system bandwidth to surprisingly low frequencies. For example, a comparison of the frequency
response of the HFA1112 driving the same 100 feet of cable
to the response of the cable alone shows that the problem
isn't the cable driver, but rather the cable itself (see
Figure 2).

These three .components peak the amplifier's frequency
response to counteract the cable's roll-off characteristic. By
squeezing more bandwidth out of a given cable, higher-performance cables aren't needed.
An unexpected but welcome side effect of this particular
solution is that using the on-chip gain-setting resistors frees
up board space for the compensation components.

It is abundantly clear from Figure 2 that the cable performance itself Ihnits the system performance for most of the
frequency range. Throwing a higher bandwidth driver at the
cable will, in fact, gain the engineer designing the system
nothing, because you can't get more bandwidth than the
cable allows.
Upgrading to a higher performance cable, such as a Belden
8281 or equivalent, is one solution to boosting system bandwidth. There are at least two downsides to this option, however. The first is that it introduces significantly higher cable
costs. The second is problems presented to technicians who
have to work with more rigid cables.
A better solution may be to use a cable driving buffer such as
Harris' HFA1114. The driver's frequency response is tunable
for a specific cable length via components connected to the
summing node (see Figure 3). By shunting R1 , Rc acts to
increase the amplifier's gain while C c controls the cut-in
frequency of the compensation.

FIGURE 3. INSTEAD OF UPGRADING TO A HIGHER
PERFORMANCE CABLE TO INCREASE SYSTEM
BANDWIDTH, A CABLE DRIVER LIKE THE HFA1114
CAN BE EMPLOYED. THE DRIVER'S FREQUENCY
RESPONSE IS TUNABLE FOR A SPECIFIC CABLE
LENGTH VIA THE COMPONENTS CONNECTED TO
THE SUMMING NODE.

10-116

Harris Semiconductor

No. AN950S.1

-------- --- ------ ---- --- --- - --- --Harris Linear

November 1996

Video Multiplexer Delivers Lower Signal Degradation (HA5024)
Author: Ronald Mancini
Video multiplexers pose a difficult design challenge. They
must perform several functions, such as matching the input
line impedance, signal amplification, signal switching, and
driving the output line, without degrading or adding noise
and transients to the signal. Typically, the signal flows
through the multiplexer where it's degraded by the multiplexers errors. In this design, the signal flows through the op
amp and thus isn't degraded by the multiplexer.
This circuit can multiplex several sources like VCRs, tuners, or
cameras into a single monitor, see Figure 1. The HAS0241P
quad op amp performs all of the multiplexer and amplification
functions with the aid of the TTL decoder. It exceeds the gain
flatness, differential phase, and differential gain specifications
for NTSC video, without adding the offset voltages, gain variability, or transients associated with multiplexers.
Turning our attention to op amp U 1A, Rl terminates the input
cable in its characteristic impedance, which usually is 7S0 in
video systems. R4 back terminates the output cable in its
characteristic impedance of 7S0. Because the cable termination is 7S0, it forms a voltage divider with R4, which has a
gain of O.S. The op amp is configured for a gain of two, therefore the circuit has an overall gain of one when driving a double terminated cable. The value of R3 can be changed
according to the formula G O.S (1 + RiR3)' R2 determines
the video performance of the op amp, so it should not be
changed. The circuits U1 B through U1 0, perform similarly.

In addition, the decoder can be easily extended to 3 to 8
using the same IC or 4 to 16 using a different decoder. The
circuit given here switches in less than a microsecond.
VIDEO
INPUT

R.

__

VIDEO OUTPUT

1I~1~~::!f~~~~~~r- ~T~0~7~5n~LOA~D
R1
75

VIDEO
INPUT
#2

Rs
75

YO
Y1
Y2
Y3

VIDEO
INPUT
113

-

R12
75

=

If more than one video output is needed, R4 , Rs, R12, and
R16 can be paralleled with 7S0 resistors. Each resistor is
connected from the respective op amp output to a second
video output that can drive another 7S0 cable.
U2 is configured as a two-to-four line decoder, with AO and
A 1 acting as the select inputs and E3 as the enable input. All
of the amplifiers are disabled when E3 is low, so there's no
output signal. When E3 is high, the select inputs determine
the video input that's connected to the video output. If E3 is
used to disable the outputs when the select inputs are
changed, there will be minimal bus contention transients during switching. However, if hot switching is desired, a breakbefore-make delay circuit should be placed in series with the
Yx lines. Because all of the signal switching occurs within
the HA50241p, the amplifier's differential phase and gain
parameters (0.03 degrees and 0.03%, respectively) determine the circuit's performance.

VIDEO
INPIIT

114

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be

+5VIN.

1

0.111i' ~

1+

I +5V

~1011F

-5VIN.

1

O.lI1F ~

1

-!t

I ·5V

1011i'

NOTES:
1. Ul is HAS0241P
2. All resistors in Q
3. U2 is CD74HC238
4. Use ground plane

It's easy to multiplex any number of channels with this
scheme because the single and dual versions of the op amp
help minimize the number of ICs required for a given deSign.
Copyright © Harris Corporation 1996

10-117

FIGURE 1. SEVERAL DIFFERENT SOURCES, SUCH AS VCRs,
TUNERS, OR CAMERAS, CAN BE MULTIPLEXED
INTO A SINGLE MONITOR USING THIS VIDEO
MULTIPLEXER. WITH THE AID OF TTL DECODER,
THE HA50241P QUAD OP AMP PERFORMS ALL
MULTIPLEXER AND AMPLIFICATION FUNCTIONS.

zO
Il.::i!!
Il.W

<0

c:W

Harris Semiconductor

-----------------------------------------------------------------------------------------------------No. AN951 0.1

Harris Linear

November 1996

Basic Analog for Digital Designers
Authors: Ron Mancini and Chris Henningsen

What Is This Application Note Trying To
Accomplish?
There is a long gap between engineering college and mid
career in a non-engineering position, but technology
marches on so a simple method of keeping abreast with the
latest developments is required. This application note starts
with an overview of the basic laws of physics, progresses
through circuits 1 and 2, and explains op amp operation
through the use of feedback principles. Math is the foundation of circuit design, but it is kept to the simplest level possible in this application note. For more advanced op amp
topics please refer to the technical papers listed in references 1 and 2.

Kirchoff's voltage law states that the algebraic sum of the
voltages around any closed loop equals zero. The sum
includes independent voltage sources, dependent voltage
sources and voltage drops across resistors (called IR drops).
R1

v - V Rl • VR2 =a
Basic Physics Laws, Circuit Theorems
and Analysis

Rz

v

1: voltage sources

or V =VRl + VR2
=1: voltage drops

(EO. 2)
(EO. 3)

FIGURE 2. ILLUSTRATION OF KIRCHOFF'S VOLTAGE LAW

Good news and bad news. The bad news is that it takes a
certain amount of dog work, like relearning physics and
circuit theorems, before proficiency becomes second nature.
The good news is that if you just hang in for a few pages you
will experience the joy of analyzing circuits like an expert.
You will gain ten years experience in a few hours. You will be
able to write op amp equations like a design engineer. You
might think this is a worthless eifort, but imagine the look on
the analog engineer's face, the one who thinks non-analog
engineers are as dumb as a box of rocks, when you write
your own op amp circuit equations.

Kirchoff'S current law states that the algebraic sum of all. the
currents leaving a node equals zero. The sum includes
independent current sources, dependent current sources,
and component currents.

~12
13~
(EO. 4)

Ohm's and Kirchoff's Laws
(EO. 5)

Ohm's law states that there is a relationship between the
current in a circuit and the voltage potential across a circuit.
This relationship is a function of a constant called the
resistance.

R

I

=0

(EO. 6)

FIGURE 3. ILLUSTRATION OF KIRCHOFF'S CURRENT LAW

Voltage and Current Dividers

1
V=IR

1: currents into a junction

(EO.l)

Voltage dividers are seen often. in circuit design because
they are useful for generating a reference voltage, for biasing
active devices, and acting as feedback elements. Current
dividers. are seen less often, but they are still important so
we will develop the equations for them. The voltage divider
equations, which assume that the load does not draw any
current, are developed in Figure 4.

FIGURE 1. ILLUSTRATION OF OHM'S LAW

Copyright @ Harris Corporation 1996

10-118

Application Note 9510
The open circuit voltage is calculated by looking into the
terminals X - Y, and then calculating the open circuit voltage
with the voltage divider rule.
V

R2
-V-RI + R2

(EO. 15)

Ih -

v=

(EO. 7)

IR I +IR2 =I(R I +R 2 )

I= _ _
V_
(R I + R2)

(EO.S)

V

R2
Vo = IR2 = (R I + R2 /R 2 )= V RI + R2

The impedance looking back into the terminals X - Y with the
independent source, V, shorted is given below.
RIR2
Zth = Zx_y = RI +R2 ",R I IIR2

The circuit to the left of X - Y is now replaced by the
Thevenin equivalents.

FIGURE 4. DERIVATION OFTHE VOLTAGE DIVIDER RULE

The current divider equations, assuming that the only load is
R2 , is given in Figure 5.

·....----......-T
11
II!

Rl

(EO. 16)

(EO. 9)

1

---1

R2

Vo

1

v

~~ __ J

(EO. 17)
(EO. 10)

V = IIRI = 12R2

(EO. 11)

R2
II = 12R

(EO. 12)

1=11+121=12~+12= 12(1+~)=

FIGURE 7. THE THEVENIN EQUIVALENT CIRCUIT
(EO. 13)

12CI;IR2)

RI

Then: 12 = I
R
R -

(EO. 14)

1+ 2

FIGURE 5. DERIVATION OF THE CURRENT DIVIDER RULE

Thevenin~

The loop equations are worked out below. Notice that not
only is the derivation of the equations more laborious, but
the labor will get out of hand with the addition of another
loop. This is why Thevenin's theorem is preferred over loop
equations.

and Norton's Theorems

There are situations where it is simpler to concentrate on one
component rather than write equations for the complete circuit.
When the input source is a voltage source, Thevenin's theorem
is used to isolate the component of interest, but if the input
source is a current source, Norton's theorem is used to isolate
the component of interest.
To apply Thevenin's theorem one must look back into the
terminals of the component being replaced. Now calculate the
open circuit voltage seen at these terminals, and during this
calculation consider that there is no load current so the voltage
divider rule can be used. Next short Independent voltage
sources and open independent current sources; now calculate
the impedance seen looking into the terminals. The final step is
to replace the original circuit with the Thevenin equivalent
voltage, V1h. and Thevenin equivalent impedance, Zth.

1

v

Vo

1
V = II(R 1 + R2 )-1 2 R2

(EO.1S)

12 (R2 + R3 + R4 )= II R2

(EO. 19)

II =

R2 + R3+ R4
R
12

en..J
(EO. 20)

2

(R2 +R 3 +R4 )
12
R
(RI + R2) -12R2

(EQ.21)

2

12 =

Thevenin's theorem is illustrated in Figure 6.

V
R2+R3+ R4
(R I + R2) - R2
R

(EO. 22)

2

(EQ.23)

v

R2

FIGURE 6. THE ORIGINAL CIRCUIT

t

(EQ.24)

Vo

!

FIGURE 8. LOOP EQUATION ANALYSIS OFTHE SAME
CIRCUIT

10-119

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Application Note 9510
The Norton equivalent circuit is seldom used in circuit
design, so it's derivation [3) and illustration will be left to the
serious student.
(EQ.29)

Superposition
The principle of superposition states that the equation for
each independent source can be calculated separately, and
then the equations (or results) can be added to give the total
result. When implementing superposition the equation for
each source is calculated with the other independent voltage
sources short circuited and the independent current sources
open circuited. The equations for all the sources are added
together to obtain the final answer.

j

I

Notice that the Thevenin method used twice as many
equations to describe the circuit as were required to arrive at
the same result with superposition. Also, the form of the final
equation arrived at by superposition is much easier to
analyze.

Feedback Principles
This discussion of feedback principles is simple because
they are easy to understand. The application of the principles can be very complicated for the design engineer, but we
can grasp the principles without understanding all of the
nuances. If this material creates a thirst it may be slaked by
reading references 2 and 3.

FIGURE 9. SUPERPOSITION EXAMPLE

v

I

-

Rl11R2
V
02 V1 = 0 - R3 + Rl II R2 2

(EQ.25)
FIGURE 12. FEEDBACK BLOCK DIAGRAM

= EA

(EQ.30)

E = VIN-IlVOUT

(EQ.31)

VOUT
A
V1N = 1 +AJ}

(EQ.32)

VOUT
(EQ.26)

Analysis Tools - Why Do We Need More
Than One?
Each one of the analysis tools shown has a place where it is
optimal. Later during the op amp analysis the tools wUI be
employed to relieve the burden of detailed calculation.
Figures 10 and 11 illustrate an example of the extra
calculations caused by using the less optimal tool to perform
the analysis.

"i ~. ".~I
·U

(EQ.27)

Equations 30 and 31 are written on the block diagram, and
Equation 32 is obtained by combining them to eliminate the
error, E. If ~ 1 in Equation 32 VOUT V 1N , or the feedback
circuit has turned into a unity gain buffer. If.~ 0 in Equation
AV1N, or there is no feedback. Notice that the
32 VOUT
direct gain, A, does not control the feedback circuit closed
loop gain; rather, the feedback factor,~, controls the closed
loop gain in a feedback circuit. This is the essence of a feedback circuit; now the closed loop gain is a function of the
feedback factor which is comprised of passive components.
The closed loop gain error, stability and drift are now dependent on stable, accurate, and inexpensive passive components. The closed loop gain assumption is valid as long as
A~» 1, also E ~ 0 if this assumption is valid.

=

=

=

FIGURE 10. SUPERPOSITION EXAMPLE REDRAW

(EQ.28)

=

=

=

If A~ -1 then Equation 32 becomes VOUTNIN 1/0, or it is
indeterminate. If the energy in the circuit was unlimited the
circuit would consume the world, but luckily it is limited, so
the circuit oscillates from positive to negative saturation. This
is an oscillator, thus the definition of an oscillator is that the
gain be ~1 while the phase shift equals -180 degrees. Now
we conclude that the feedback factor controls the closed
loop gain, and the direct gain/feedback factor combination
determines if the circuit will be stable or will be an oscillator.

FIGURE 11. THEVENIN EQUIVALENT CIRCUIT MODEL

10-120

Application Note 9510
The Op Amp Symbol
It is important to understand the op amp symbol shown in
Figure 13. The -input, V-, is the inverting input, and the
+input, V+, is the non-inverting input. The point of the triangle is the op amp output, and the op amp multiplies the differential voltage, (V+ - Vol, by a large gain, a.

Now superposition can be applied to the circuit; Equation 36
calculates the gain for each independent source, and
Equation 37 recombines the separate gains.

The Inverting Op Amp
Three assumptions are made in the calculation of the inverting op amp circuit equations. First, the current into the op
amp inputs, Ie in Figure 13, is assumed to be zero; this is a
valid assumption because the bias currents are usually
much lower than signal currents. The second assumption is
that the op amp gain, a, is extremely high, and this is a valid
assumption in most situations where the op amp's bandwidth is much greater than the signal bandwidth. The third
assumption, which is that the error voltage, VE, equals zero,
is a result of assuming an extremely high op amp gain.
When a is very large VOUT, can assume any value required
to drive the inverting input voltage to the non-inverting input
voltage, so VE will always be forced to zero.
11 -

RF
RF
RF
V01 = -V1R ,V02 = -V2R ,V03 = -V3R
G1
G2
G3

(EO.

36)

If RF I RGX = 1 Then;
VOUT = -(V 1 +V2 +V 3)

(EO. 38)

The Non-Inverting Op Amp

12 -

Referring to Figure 15, because VE is equal to zero the voltage at point X is equal to VIN. There is voltage divider
formed by the feedback resistor, RF , and the gain setting
resistor, RG, and the voltage divider input voltage is the output voltage of the op amp. Equation 39 is written using the
voltage divider rule, and Equation 40 is obtained through
algebraic manipulation. Notice that the ideal closed loop
gain is again independent of the op amp gain.

FIGURE 13. INVERTING OP AMP CIRCUIT

Assume Ie = 0, VE = 0, a = 00
Then:
VIN

FIGURE 14. THE INVERTING ADDER

VOUT

11 = RG = 12 = - ~

(EO.

VIN RF = - VOUT RG

(EO. 34)

VOUT
RF
VIN = - RG

(EO.3S)

33)

FIGURE 15. NON-INVERTING OP AMP

Equation 33 is written by applying Kirchoff's current law to
the inverting node. Equation 35 is obtained through algebraic manipulation of Equations 33 and 34. Note that the
ideal closed loop gain, Equation 33, does not contain the op
amp"gain, so it is independent of the op amp gain so long as
the assumptions are valid.
The inverting op amp can be configured as an inverting
adder as shown in Figure 14. The analysis is similar to that
shown for the inverting amplifier, but it is easier to
understand if the concept of a virtual ground is understood.
Virtual is defined as "existing or resulting in effect though not
in actual facf'. The inverting node acts as a real ground
because no voltage is developed across it, but the current
path is restricted to the PC traces attached to the node. The
non-inverting input of the op amp is connected to ground,
thus if the error voltage is to be zero as was assumed, the
inverting input functions as though it were tied to ground.
Considering the virtual ground, the three currents flowing
through RG1 , RG2, and RG3 can be calculated separately.

(EO. 39)

~

-...I

1Il...l

Ww

(EO. 40)

The Differential Amplifier
The differential amplifier schematic is given in Figure 16, and
the analysis will be done in two parts because we will use
superposition. Two output voltages, one corresponding to
each input voltage source, will be calculated separately and
added together. The output from V1 is calculated in
Equation 42; V+ is first calculated with the voltage divider
rule, and then it is substituted into the non-inverting gain
equation yielding Equation 43. The output from V2 is calculated from the inverting gain equation in Equation 44. The

10-121

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Application Note 9510
results of Equations 43 and 44 are added in Equation 45 to
obtain the complete circuit equation. Notice that the output is
a function of the difference between the two input voltages,
this accounts for the name differential amplifier.

equivalent voltage and resistance, then redraw the circuit as
shown in Figure 18. Now the inverting gain can be calculated
in the normal manner using the algebraic simplification
shown in Equation 48.

If a small signal is riding on a large signal, say 10mV,
0.001 Hz riding on 5Voc, the DC can be stripped off by
putting the combined signal into the non-inverting input, and
putting 5Voc into the inverting input. The 5V oc becomes a
common mode signal (a signal which is common to both
inputs), so it is rejected by the differential amplifier if R1 =R3 ,
and A2 =R4 .

'X

i>---=---....-. V

OUT

FIGURE 17. T NETWORK IN THE FEEDBACK PATH

v1

v2
FIGURE 18. THEVENIN ANALYSIS OF T NETWORKS IN THE
FEEDBACK PATH

FIGURE 16. THE DIFFERENTIAL AMPLIFIER
VOUT = VOUT1 +VOUT2

(EQ.41)
(EQ.47)
(EQ.42)

(EQ.43)
(EQ.4B)

(EQ.44)

(EQ.45)

Video Amplifiers
(EQ.46)

This effect could be accomplished through the use of a coupling capacitor, but because the frequency of the signal is so
low the capacitor value and size would be too big. The differential amplifier also rejects AC common mode signals. Data
transmission schemes often use twisted pairs for the interconnections so that any noise coupled on the lines will be
common mode. Differential amplifiers are used as receivers
in this data transmission scheme because they reject the
common mode noise while amplifying the signal.

T Networks in the Feedback Path
Putting a T network in the feedback path as shown in
Figure 17 complicates the analysis, but offers the advantage
of high closed loop gain coupled with low value feedback
resistors. This configuration is also useful for some filter
configurations. Thevenin's theorem is applied as shown in
Figure 18. Look into R4 from X, Y and calculate the Thevenin

Until now we have implicitly assumed that all op amps are
the same. This is not true, but because the ideal closed loop
equations are identical, it is a workable assumption. The two
big classifications of op amps are voltage feedback and current feedback. The type of feedback is not tlie only difference
between these op amps. The internal circuit configurations
are dramatically different, so much so that recommended
reference #1 dwells on voltage feedback while reference #2
dwells on current feedback. Whenever an op amp is used in
a high frequency circuit such as a video amp there is a
strong likelihood that it will be a current feedback op amp.
Again, because the closed loop ideal gain equations are
identical for voltage and current feedback op amps we will
not distinguish between them.
In Figure 19, RIN is usually the terminating resistance for the
input cable, and it is usually 500 or 750. AM is the matching
resistance for the cable being driven, and RT is the terminating resistance for the driven cable. RT is often shown here for
gain calculations while it is physically placed at the cable
end. Using Equation 49, we see that when AG = AF and
RM = RT , the overall circuit gain is one.

10-122

Application Note 9510
A high pass filter is shown in Figure 22. At F = 0 the gain is
(R F + RG)/R F , and at very high frequencies the gain tries to
approach the op amp gain, a. Sometimes the stray input
capacitance forms this circuit, and the result is unwanted
peaking or overshoot because the capacitor phase shift
tends to make the circuit unstable.

FIGURE 19. A TYPICAL VIDEO AMPLIFIER

(EO.49)
FIGURE 22. HIGH PASS FILTER

ACTheory
The emphasis here is on capacitors because they are
responsible for the vast majority of AC effects. The capacitor
has an impedance and a phase shift both of which are a
function of frequency. Although it is paramount in stability
calculations, we will neglect the phase shift because you can
obtain a reasonable understanding of circuit performance by
just considering the impedance. Referring to Equation 50 it
is apparent that when the frequency is very high, s = jm is
very high, so the capacitor impedance, Xc, is very low. The
converse happens when the frequency is very low.
The key to this section of AC theory is that high frequency
means low capacitive impedance, and low frequency means
high capacitive impedance. At F = 00, Xc = 0, and at F = 0,
Xc = 00. At intermediate values of frequency the capacitive
impedance must be calculated with the assistance of Equation 50.

This general method is useful for analyzing the performance
of op amp circuits which have capacitors. Depending on
where they are connected the capacitors can stabilize or
destabilize the op amp, but they always shape the transfer
function in the frequency domain.

Conclusion
Some algebra, the basic laws of physics, and the basic circuit laws are adequate to gain an understanding of op amp
circuits. By applying these tools to various circuit configurations it is possible to predict performance. Further in-depth
knowledge is required to do op amp design, and there are
many sources where this knowledge can be obtained. Don't
hesitate to try some of these tricks on your local circuit
design engineer, but be aware that it may result in a long lecture about circuit design.

References
[1) Harris Semiconductor, Application Note 9415, Author:
Ronald ManCini, 1994.
[2) Harris Semiconductor, Application Note 9420, Authors:
Ronald Mancini and Jeffrey Lies, 1995.

FIGURE 20. CAPACITOR IMPEDANCE

1
1
Xc = SC = jcoC

whereS=jwand j=./-1

(EO.50)

[3) Van Valkenberg, N.E., Network Analysis, Prentice-Hall,
1964.

Op Amp Circuits Containing Capacitors

t;

Referring to Figure 21, when F = 0, Xc = 00 so the gain,
G = -RPRG' When F = 00, Xc = 0 then G = O. The gain starts
off high and decreases to zero at very high frequencies. Very
often C F is an unwanted stray capacitor which yields an undesirable effect; namely, the circuit loses high frequency performance.

RG
i>--6--OVOUT

FIGURE 21. LOW PASS FILTER

10-123

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Harris Semiconductor

---No. AN9513

----Harris Linear

October 1996

Component Video Sync Formats (HFA 1103)
Author: Chris Henningsen

Introduction
This application note will examine a variety of sync formats
and a method for removing the sync pulse from component
video signals (see Figure 1). The HFA1103 is a Video Op
Amp with an open emitter NPN transistor output stage that is
ideal for video signal amplification and sync stripping
functions. This product was developed for video design
engineers who need to remove sync from component RGB
(red, green, blue) and monochrome RS-170 video data (see
Figure 7). Recently the term RGB has been turned around
and called GBR (green, blue, red) as video distribution
systems normally put green on channel 1, blue on channel 2
and red on channel 3. This is consistent with the hook-up of
the color difference standards.

sync signals. Sync is generally combined with the video
signal, resulting in lower system costs by minimizing the total
number of switching channels required. Certain applications,
such as some RGB monitors, can't handle sync on the video
signal and it must be stripped 011, usually by a stage on the
output of the distribution amplifier. Now that we know some
of the applications where sync removal is important, let's
look at why and where sync signals are used.

TABLE 1. RGB STANDARDS SPECIFICATIONS (BROADCAST
ENGINEERING 11/94)
SMPTEI
EBU N10

NTSC
(NO SETUP)

NTSC
(SETUP)

Max

700mV

714mV

714mV

Min

OmV

OmV

54mV

Range

700mV

714mV

660mV

Sync

-300mV

-286mV

-286mV

1V

1V

1V

COMPONENT (RGB)
VIDEO INPUT

HFA1103 OUTPUT

FIGURE 1. SYNC STRIPPER WAVEFORMS

VOUT

Peak-To-Peak

Table 1 lists standards specifications for SMPTE and NTSC
video signals. All have 1Vp.p signals with sync signals
ranging from -286mV to -300mV. A typical1Vp_p video signal
consists of up to +700mV of active video on top of a -300mV
sync pulse. The application circuit shown in Figure 2 will strip
off the sync pulse and transmit only the positive video data.
See the Harris Application Note AN9514 titled "Video
Amplifier with Sync Stripper and DC Restore" for additional
details on this circuit. This circuit is useful in a variety of
video processing applications such as; RGB video digitizing,
RGB video distribution amplifiers for workstations and PC
networks, and RGB monitor preamplifiers. When digitizing
RGB video it is not necessary to digitize the sync pulse, so
removing sync allows the full dynamic range of the AID
converter to be used on just the video data, resulting in a
30% increase in image resolution. In video distribution
amplifiers, which are driving a number of video channels, it is
undesirable to require separate switching channels for the
Copyright

FIGURE 2. HFA1103 APPLICATION CIRCUIT VIDEO AMPLIFIER
WITH SYNC STRIPPER

Transmitting two-dimensional moving pictures electronically
requires the handling of a large amount of information and
this is done by slicing the 2-D picture into horizontal strips of
video and sending them sequentially. At the receiving end, or
video monitor, the video information is recreated in scan
lines on the display screen. This process continues until all
of the scan lines needed for the picture are complete. Each
complete picture refresh is called a frame, and typical frame
refresh rates vary from 25 to 30 frames/s for broadcast video
up to 72 frames/s in high performance video systems.
Sync signals are used to ensure that the scan lines are correctly placed on the display screen. A horizontal sync pulse is
used to indicate the end of each scan line and signals the mon-

© Harris Corporation 1996
10-124

Application Note 9513
itor to return to the left edge of the screen to begin the next
scan line, below the one just completed. A vertical sync pulse is
used to tell the monitor that the bottom of the picture has been
reached, and that the next scan line will start at the top again.
This is similar to a carriage return on a typewriter, where a scan
line is equivalent to a single line of text and a frame of video is
equivalent to a complete page of text (see Figure 3).

D
[

o

~~~~ONTAL[~ ~~~~~~GE

VERTICAL
SYNC

LJ

handled. Using fewer wires is an obvious advantage in applications with long cable lengths between the computer and
monitor. Many multisync monitors accept all three formats of
RGB and sync, as they have circuits to adapt automatically
to the type of RGB signal present. Other monitors are
designed to work specifically with one of the RGB formats
and the sync must be removed from green in RGsB or from
all three channels in RsGsBs before driving the monitor. This
is one of the primary applications for the HFA 1103 video op
amp with sync stripper.
RGBHV • 5 WIRE

r--

PAGE
RETURN

FIGURE 3. HORIZONTAL AND VERTICAL SYNC IS
ANALOGOUS TO TEXT CARRIAGE RETURN
AND END OF PAGE

""'--

RED

~
BLUE
~
V SYNC

RGBS-4WIRE

r--

RED
GREEN
BLUE
COMPOSITE
SYNC

""'--

RGsB-3WIRE

r--

RED
GREEN
AND SYNC
BLUE

""'--

FIGURE 4. WIRES REQUIRED FOR RGBHV vs RGBS vs RGsB
VIDEO

The scan lines are formed by moving a spot of light, scanning left to right and top to bottom, in a pattern called a raster. As the spot traces out the raster pattern, it is modulated
by the video signal to form the picture. Monochrome (black
and white) systems require just one video signal, plus the
horizontal (H) and vertical (V) sync pulses, for a total of three
signals. Color computer systems require one signal each for
red, green and blue, plus V and H sync pulses for a total of
five signals. There are a variety of techniques used to
reduce the number of wires needed to transmit these five
signals.

Computer Systems
In computer systems the monitor is generally located close
to the CPU and separate wires can be used for Red, Green,
Blue and Horizontal and Vertical sync signals. It is common
for monitors to be hooked up using a single connector housing the five separate wires. This approach is referred to as
RGBHV. As the distance between the monitor and the computer increases, it is more convenient and less costly to use
fewer wires. Combining both the horizontal and vertical sync
into a single composite sync signal results in a four wire system, eliminating one wire. This approach is referred to as
RGBS, where S is the composite sync signal. RGBS system
monitors contain circuits to recreate the horizontal and vertical sync signals from the composite sync. Another wire can
be eliminated by combining sync with a video channel. This
is possible because sync pulses only occur between scan
lines (horizontal sync) and between frames (vertical sync),
when video signals are not present. Typically the composite
sync is carried by the green channel and this 3-wire system
is referred to as RGsB or SaG for sync-an-green. RGsB system monitors have circuits to identify composite sync from
the RGsB video and to separate it into its horizontal and vertical sync components. In some cases sync is combined with
all three color channels; red, green and blue, and is referred
to as RsGsBs. We have now discussed how to transmit
video using 5 wire RGBHV, 4 wire RGBS and 3 wire RGsB
approaches (see Figure 4), with the major differences being
the way in which the horizontal and vertical sync signals are

Now let's see if we can further reduce the number of wires
by doing something with the way we transmit video. RGB
video signals can be color space transformed into a separate black and white (monochrome) picture plus two additional pictures that describe the difference between the
monochrome picture and the full color representation. The
monochrome picture is called "luminance", and is referred to
as "Y". The pair of color difference pictures are referred to as
"U" and "V". This YUV video signal can be color space transformed back into RGB, if needed. The advantage of the YUV
signal is that it reduces the transmission and storage
requirements in video transmission and distribution systems,
as the total amount of video information is reduced. This is
due to the fact that the human eye does not need as much
color difference information as it does luminance information. Now the color difference information "U" and "V" can be
combined into a single "chrominance" signal, referred to as
"C". We have now reduced the signal total to two wires. A
new type of sync signal must be included so the video monitor can separate the two color difference signals again. This
new sync information is called color burst, and is added to
the chrominance, "C", just after each horizontal sync pulse.
The "Y" channel carries the composite sync information.
S-VHS videotape is the most popular YC format.

Television Broadcast Systems
Television Broadcast Systems must take the five original signals (R, G, B, H, and V) and transmit them through a single
transmitter. Here luminance "Y" and chrominance "C" are
combined into a single video signal called composite video.
Broadcast video systems are required to be compatible with
monochrome and color receivers, and black and white
receivers only need to process the Y portion of the signal.
The broadcast standard in North and Central America,
Korea, Taiwan and Japan is called NTSC and uses a
3.58MHz color subcarrier. Europe, Australia and the Middle
East use PAL while France and Russia use SECAM, both
4.43MHz color subcarriers (Figures 5 and 6). Note that the
application circuit for video sync stripping, shown in Figure 2,

10-125

I-

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Application Note 9513
is not useful for composite video applications, as some of the
color Information (blue) resides below the black level
(Figures 7 and 8) and would be lost by the sync stripping
function.

100 IRE

CYAN GREEN

COLOR SUBCARRIER

BLANKING LEVEL

~--~-----r~--'--+--r-~t----+I(M~)

o

3.0 3.58 4.2

2.0

1.0

SYNC LEVEL

4.5
NTSC COMPOSITE VIDEO

FIGURE 5. NTSC SYSTEM BANDWIDTH

FIGURE 8. COMPOSITE VIDEO STANDARD
COLOR SUBCARRIER

References

I

[1] Harris Semiconductor, High Speed Signal Processing
Seminar, 1994 (Publication #BR·043A)

I---r---T'"--"r---r-:-':.::-T--.r-'-t----+I (M~)

o

1.0

2.0

3.0

FIGURE 6. PAL SYSTEM BANDWIDTH

IRE LIMITS

ACTIVE LEVEL TIME

100

[2] Ues, Jeff and Henningsen, ChriS, ·Video Amplifier With
Sync Stripper and DC Restore", Harris Semiconductor
Application Note AN9514 April 1995

5.5 5.0

[3] Epstein, Steve, Component Analog Video· So Many
Standards, Broadcast Engineering, Nov. 1994

-

[4] Atwood Research Inc., Video Sync Formats, Application
Note #3, 1994

WHrrELEVEL

BLACK LEVEL

BLANK LEVEL

-

SYNC LEVEL
RS·170 VIDEO

FIGURE 7. MONOCHROME VIDEO STANDARD

10-126

Harris Semiconductor

No. AN9514

Harris Linear

June 1995

Video Amplifier with Sync Stripper and DC Restore (HFA 1103)
Authors: Jeff Lies and Chris Henningsen

Introduction
The circuit in Figure 1 transmits 200M Hz (-3dB bandwidth)
video signals while stripping off the sync pulse and performing DC restoration. It is configured for a typical video cable
driver application driving a double-terminated 75n load,
where the HFA 1103 (IC3) is configured for a gain of +2 to
ensure unity gain throughout.

Sync Stripping
In component video systems it is frequently necessary to
remove the sync pulse from an RGB signal. Sync is often
combined with one or more of the red, green, and blue video
signals in video distribution amplifiers, routers and switchers
to decrease the number of input and output channels
required in a SWitching network. In many applications, however, as the video signals exit the switching network the sync
pulse must be removed.
The HFA 1103 video op amp is specially designed to perform
sync stripping. Its open emitter NPN outPlit forms an emitterfollower with the load resistor, and passes the active video

TO SYNC
SEPARATOR

+5V

signal while virtually eliminating the negative sync pulse (see
Figure 2). Residual sync of the HFA1103, defined as the
remainder of the original -300mV sync pulse, referenced to
ground, is only SmV at the cable output. A particular advantage of sync stripping with the HFA 1103 is the resultant
larger (by 0.7V) output voltage swing, compared to simply
using a wideband video op amp with an external emitter-follower.
Because the HFA 1103 contains no active pull-down, output
linearity degrades as the Signal approaches ground. To deal
with this a 6.Skn pull-up resistor (Ra) and a 75n pull down
resistor (R 10) on the output ensure a fixed positive voltage
offset, in this case +50mV. This offset was arbitrarily chosen
as a good compromise between linearity near the DC level
and minimum residual sync. Increasing Ra decreases residual sync, at the expense of linearity. Conversely, decreasing
Ra decreases linearity error, but increases residual sync.
Other applications benefitting from sync removal are HDTV
systems and video digitizing circuits. Consider a typical
1Vp_p RGB video signal with a -300mV sync pulse and
+700mV video data. By stripping off the unwanted sync

ICla + ICl b = CA5260 DUAL AMP
IC2 = 74HC4053 SWITCH
IC3 = HFAll03 VIDEO OP AMP

Ra
6.8K
~~~--~--------~~~-----+5Voo

Ii;
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1/)...1

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R12
75

a..:ii:
a..W

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I/)

FIGURE 1. HFA1103 BASED VIDEO AMPLIFIER WITH SYNC STRIPPING AND DC RESTORE

Copyright

© Harris Corporation 1995
10-127

Application Note 9514
, pulse and digitizing only the active video, designers can use
the full dynamic range of the AID converter for the +700mV
video data. This results in a 30% increase in resolution using
the same AID converter.

DC Restore
Another common video function is DC restoration, used
when AC coupled signals have lost their DC reference and
must have it periodically reset in order to retain brightness
information.
This circuit accomplishes DC restoration using a CA5260
dual op amp (ICla, IClb) coupled with a sample-and-hold
circuit based on the 74HC4053 switch (IC2). VIN , consisting
of the input video signal and a DC offset (Vocl, is routed to
the non-inverting input of the HFA 1103 (IC3). The HFA 1103
is configured in a gain of +2 (to compensate for the attenuation resulting from double terminating the cable), which
would result in an output of 2 x VIN = (2 x Video + 2 x Vocl, if
not for the DC restore circuit.
VIN also travels through half of the dual CA5260 amplifier to
the sample-and-hold circuit, where the O.lIlF capacitor (C,)

is the hold capacitor. The sample-and-hold control is triggered by a back-porch pulse from a sync separator or by a
horizontal video blanking signal. The DC output signal (Vocl
from the sample-and-hold circuit is then amplified at a gain
of +2 by the second op amp (IC1 b); the gain is required
because Voc is input to the HFA 11 03s inverting input which
provides only a gain of -1, but as discussed earlier, the output contains a term of 2 x Voc. Thus 2 x Voc is summed into
the HFA 1103 inverting input, is subtracted from the output
signal, and yields a DC restored video signal.
Because the output impedance of IC1b is high, and would
affect the gain at the non-inverting input of the HFA1103, a
471lF capacitor (C2) is used to provide an AC ground and to
maintain good high-frequency gain accuracy.
A potentiometer (Ra) is used prior to IC1 b to null out any offset voltage contributed by the DC restore circuitry.

Conclusion
The circuit's resultant output is a 200M Hz, DC restored
video signal in which the sync pulse has been stripped to a
residual level of no more than 8mV.

-411.0

!1S

-30.0

-20.0

·10.0

0.0

I'S
FIGURE 28. ONLY VIDEO COMES OUT

FIGURE 2A. VIDEO AND SYNC GO IN

FIGURE 2. SIGNALS AT HFAll03 INPUT AND CABLE OUTPUT

10-128

10.0

Harris Semiconductor
--------- --- ------ - --- --- --- --- --

-

No. AN9515.1

Harris Linear

November 1996

Multiplier Improves the Dynamic Range of Echo Systems
(HA-2556, HA-5177)
Author: Ron Mancini

Introduction
In an echo system the returned signal amplitude is a function
of the distance to the target, and it can be expressed mathematically as function of time. An echo system with a fixed
gain preamp has poor dynamic range because close targets
(short return times) have high signal amplitudes while distant
targets (long return times) have much lower signal amplitudes. In fixed gain systems, the biggest signals establish
the upper preamp gain limit based on not saturating the system, and this gain may not be high enough to process small
returns properly.

the time it takes sound to travel approximately one foot
through air. During the first portion of the ramp, when the
returned signal is very large, the multiplier gain is small
because Vx is small. As time increases Vx also increases
providing more gain through the multiplier as the expected
echo decreases in amplitude. Thus, the output voltage swing
of the multiplier tends to stay constant for large changes in
input signal, and the dynamic range is improved to the
amount of the ramp change, which is more than 60dB with
the values shown in Figure 1.

The solution is a preamplifier which has a gain proportional
to time, such that the gain will be small for close targets and
large for distant targets. The preamp still has to meet all the
other normal preamp criteria such as bandwidth and noise
performance, and the added time dependent gain function
must not degrade the signal. The circuit shown in the figure
implements the variable gain preamp with the Harris Semiconductor HA-2556 multiplier. This IC establishes the signal
bandwidth and noise figure because it is the only component
in the signal path. The equation for the multiplier gain, as
shown in the accompanying figure, is given below:

Often the returned signal is a nonlinear function and it may
be desirable to linearize it. An inverse nonlinear ramp can be
employed to linearize the overall function. R3 , R4 and C l
generate a logarithmic ramp when Sl is in the Log position
thus yielding a logarithmic gain function adequate for
linearizing some transducers. Many other time-gain transfer
functions can be generated by employing different types of
ramps.

R8

VXVY(R7
VOUT = -5+ 1 ) = 10VXVy

The HA-5177 and its associated circuitry comprise a constant current source whose current is V ol /R2 I 51~. If
Sl is in the LIN position with Q2 's gate held high, the current
source is shorted to ground by Q2 and the multiplier gain is
set to zero. When the received signal from the closest target
can be present, Q2's gate is brought low forcing it into a very
high drain resistance state (almost an open circuit) allowing
the HA-5177 current to charge C l in a linear manner. The
voltage across C l ramps up from OV to 5V in 1ms which is

= =

It is important to eliminate the multiplier offsets with the
adjustments (1) provided because offsets will appear in the
output signal, reduce the dynamic range and contribute
errors. As the circuit is configured it will sweep from a gain of
0.01, as the ramp begins, to 10 as the ramp ends. Returned
signal amplitude is usually small but should not exceed
100mVp_p unless distortion can be tolerated. The circuit
bandwidth can be as high as 57MHz in low gain applications,
and is 5MHz as configured.

References
(1) Wideband Four Quadrant Voltage Output Analog MuHiplier
Data Sheet HA-2556, File Number 2477, Harris Semiconductor, Melbourne, Rorida

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Copyright

© Harris Corporation 1996
10-129

Application Note 9515
+15V

1

-15V

1.'

.J.

TO CIRCUITS

10llF

JO.1 1lF

+15

R.
150K

-15V

+15

!

XOFFSET
R1",20K

-15

16
8

Vx

°2

.J.

S.6V
1N752A

VOUT

13
C1
O.Ol1lF

HA-2556
U1

Vy

5

9

GAIN

Rs

CONTROLTo'
(TTL)

Rs

10K

~

20.40

O2

2N6901

-4:-

Rg.20K

-=

f YOFFSET

SIGNAL

-15V

10K

As

FIGURE 1. MULTIPLIER IMPROVES DUAL RANGE OF ECHO SYSTEMS

10-130

GAIN
CONTROLLED
OUTPUT

Harris Semiconductor

---- ------- No. AN9516.1

Harris Linear

June 1996

Adjustable Bandpass or Bandreject Filter (HA-2841)
Author: Ron Mancini

Introduction
The filter described here has an easily adjustable center frequency, symmetrical skirts and an attenuation (gain) of
-40(+40)dB at an octave either side of the center frequency
(fc). The filter Q (Q fc/BW3dB " 250) does not vary significantly when the center frequency is changed, thus, the
shape of the skirts is essentially independent of the pot setting. This feature yields filters that can be adjusted over a
much wider frequency range than "T" type filters, the only
other type of filter with such a deep notch or narrow bandpass. Now one filter type is useful in many designs. The calculation of the center frequency for the circuits shown in
Figure 1 and Figure 2 is given in Equation 1 and Equation 2.

=

fc

=

1
21tCpRIR2

Where

RI

(EO. 1)

= RIA +nRp

R2 = R2A +(1-n)Rp
(EO. 2)
A basic theorem of feedback circuits is that a function generator included in a negative feedback loop computes the
inverse function at the output. This approach has been used
to change an excellent band reject filter into an excellent
bandpass filter. The schematic of the band reject filter, which

is passive and comprised of C, RI , R2 and R3 is shown in
Figure 1. The bandpass filter, which includes the passive
network in the feedback loop, is shown in Figure 2. The
bandpass filter has the advantage of high input impedance
and low output impedance because of the location of the op
amp. With the values shown the center frequency is adjustable from 55kHz to 550kHz producing a decade of frequency
adjustment. The Harris Semiconductor HA-2841 op amp is
chosen as the amplifier because it has good DC characteristics and has the high gain bandwidth required to achieve the
bandpass gain without distorting the filter response. RI
should be split into RIA and RIB to prevent RI from becoming zero, and the split may be selected to obtain maximum
resolution over the desired center frequency range.
A PSPICETM plot of the circuit using the SPICE Model for the
HA-2841 is shown in Figure 3. The plots are the logarithmic
transfer function of both the filters (in dB). Notice that the
bandreject filter transfer function, represented by the diamonds, is the mirror image of the bandpass transfer function,
represented by the squares. These transfer functions
change very little when they are adjusted to 550kHz center
frequency. Bench test results show some deviation from the
PSPICETM simulations because of component tolerances
and layout capacitances, but generally they correlate well
with the simulations. The transfer functions change radically
and tend to degenerate at high frequencies if low gain bandwidth op amps are used.
+15

t;

O.~

VIN

VOUT

O.II1F
Ra,62K

......._
C =0.33nF

c

c

.......

O.~

l:-

Ra,62K

C

Rrr-1:--E2A
T5.IK
10

-IS

+15

C =O.33nF
-IS

C

C

Copyright © Harris Corporation 1996

10-131

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t;;

Printed copies of these programs are given here, and
electronic copies are available on the "Harris SemiconductorAnalog SPICE Macromodels" disk dated January 1996 or
later.

AC Transfer Function For An Inverting

OUT1

Rall

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FIGURE 1. SCHEMATIC OF INVERTING OP AMP

Application Note 9523
"This program simulates the AC transfer function for an inverting op amp.
"It has three op amps; each with a gain that is specified by the
"user with a .param statement. The user must specify the load RL• CL• the
"feedback resistors RF1 • RF2 • RF3 and the corresponding gains G1• G2• G3.
"The power supply voltage is set by the parameter ·vsupply". The load resistors
"are automatically split into voltage dividers to normalize the gain plot.
"and the gains can be plotted in dB by calling the macros G1• G2• and G3.
"The inputs are tied together. and the outputs are called OUT1. OUT2. and
"OUT3 corresponding to the respective gains. The op amp model is entered with
"a .lib statement. The model in the subcircuit call (x statement) must correspond to the model
"called in the .lib statement (3 times) .
.param CL=10pf
.param RL=400
.param RF1 =750
.param RF2=750
.param RF3=750
.param G1=1
.param G2=2
.param G3=3
.param vsupply=5
.lib b:ha502x.cir
x101134123ha502x

x2 0 21 3 4 22 3 ha502x
x3 0 31 3432 3 ha502x

VIN in Oac 1
Rm 11 12 {R F1 }
RF21 21 22 {R F2}
RF31 31 32 {R F31
RG11 in 11 {RF1/abs(G 1)}
RG21 in 21 {RF:labs(G 2) }
RG31 in 31 {RF~abs(G3) }
RA11 12 OUT1 {R L" (abs(G 1)-.99999) /abs(G 1)}
RA21 22 OUT2 {R L" (abs(G 2)-.99999) /abs(G 2) }
RA31 32 OUT3 (RL" (abs(G 3)-.99999) /abs(G 3)}
RB11 OOUT1 (RJabs(G 1)}
RB21 0 OUT2 {RJabs(G 2) }
RB31 0 OUT3 (RJabs(G 3)}

CL11 0 12 {CJ
CL21 022 {CJ
CL31 0 32 {CL}

Vee 3 0 {vsupply}
VEE 4 0 {-1"vsupply}
.ac dec 50 1meg 3000meg
.probe
.end
FIGURE 2. INVERTING OP AMP AC TRANSFER FUNCTION PROGRAM

10-134

Application Note 9523
6.0

.

4.0

ID

1i!: 2.0
1i!:

~

~

.-.
~

...... ~.

0

:::E -2.0
II:

i

G1
G.

-4.0

G3
-6.0
1

3

10

~'
I
30

IN ......----i~>-_ _'I,fIIV-+-0UT2

100

21t-W~"

300

RG21

FREQUENCY (MHz)

FIGURE 3. INVERTlNG OP AMP AC TRANSFER FUNCTION PLOT

AC Transfer Function for a Non-Inverting
OpAmp
The second program (see Figures 4, 5, and 6) is named
cfanig.cir, and it simulates the AC transfer function for a noninverting op amp. This program uses three op amps so it can
compute the transfer function for three different gains in one
pass. The program requires the user to supply the feedback
resistance values for each gain, the gain sellings, the load
resistance, the load capacitance, and the power supply voltage in volts. The program assumes that the op amp is run off
two power supplies of equal and opposite polarity each of
which is referenced to ground, so it applies the entered voltage to the op amp as a positive and negative supply with
equal magnitudes. If a single supply op amp needs to be
evaluated just enter half the power supply voltage, and the
analysis will be equivalent.
Unless the output is normalized the vertical scale will have to
be large enough to accommodate the difference in gains, so
small effects such as peaking may be hard to discern or
measure. The program configures the load resistor as a voltage divider, and the output is taken at the voltage divider
output. If the op amp gain is 10, the load resistor gain will be
0.1. If a load resistor is not required by the data sheet enter a
large value such as 1000Gn; the large resistor will not affect
the circuit operation while the normalization feature is
retained. Now the three curves will plot on top of each other
similar to the GBW curves shown in most data books.

FlGURE4. NON-INVERTING OP AMP SCHEMATIC

6.0

.

4.0

ID

"
./\'
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1i!: 2.0

~

C

~

0

1-

2•0

G~~

G3

-4.0

-6.0

1

3

10

30

~Gl

\

\ ,\
100

FREQUENCY (MHz)

FIGURE 5. NON-INVERTING OP AMP AC TRANSFER
FUNCTION PLOT

300

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10-135

Application Note 9523
"This program simulates the transfer function for a non-inverting op amp.

"1\ has three op amps; each with a gain that is specified by the user
"with a .param statement. The user must specify the load RL, C L, the
ofeedback resistors RF1, RF2 , RF3 and the corresponding gains G l , G2, G3.
"The power supply voltage is set by the parameter "vsupply". The load resistors
"are automatically split into voltage dividers to normalize the gain plot,
"and they can be plotted in dB by calling the macros G l , G2 and G 3.
"The inputs are tied together, and the outputs are called OUT1, OUT2, and
"OUT3 corresponding to the respective gains. The op amp model is entered with
"a .lib statement. The model in the subcircuit call (x statement) must correspond to the model
"called in the .lib statement (3 times) .
.param CL=10pf
.param RL=400
.param RF1 =1000
.param RF2=681
.param RF3=383
.param Gl =1
.param G2=2
.param G3=10
.param vsupply=5
.lib b:ha502x.cir
x1 in 11 34123 ha502x

x2 in 21 3422 3 ha502x
x3 in 31 3432 3 has02x
vininOac1

RFll 11 12 {R F1 }
RF2l 21 22 {R F2}
RF3l .31 32 {R F3l
RGll 0 11 (RF1/(G l -.99999)}
RG2l 0 21 (RF:i(G 2-.99999) }
RG3l 031 (RF:I(G 3-.99999) }
RAll 12 OUT1 {RL"(G l -.99999)/G 1}
RA2l 22 OUT2 {RL"(G 2-.99999)/G 2 }
RA3l 32 OUT3 {RL"(G3-·99999)/G3l
RBll OOUT1 (RdR L"(G l -.99999)/G 1)}
RB2l 0 OUT2 (RdR L"(G2-.99999)/G 2) }
RB3l 0 OUT3 (RdRL"(G3-.99999)/G 3) }
C Lll 012 {Cl}
Cl2l 022 {CJ
Cl3l 032 {CJ
Vee 3 0 {vsupply}
VEE 4 0 {-1"vsupply}
.ac dec 50 1meg 3000meg
.probe
.end
FIGURE 6. NON-INVERTING OP AMP AC TRANSFER FUNCTION PROGRAM

10-136

Application Note 9523
DC Parameters For a Non-Inverting
OpAmp

The input signal to the op amp is a DC sweep. The sweep
input enables a data analysis at VIN OV which is often a
data book point, and the parameters can be evaluated at
various other points of interest. The input currents can be
examined by plotting the currents through the feedback
resistor, Rfo and the input resistor, RI . The difference
between these currents is the Input offset current. When the
voltage is swept through zero the offset voltage for zero input
voltage can be calculated. Either input offset voltage can be
plotted by selecting the correct node voltage, or the differential input voltage can be plotted be selecting V(11 )-V(13).
The supply currents are plotted by selecting I(VEE) or I(Vecl
for the negative and positive power supplies respectively.

=

The third program (see Figures 7 through 11) is named
cfadc.cir, and it simulates the salient DC parameters for a
non-inverting op amp. The program requires the user to supply the feedback resistance values, the load resistance, and
the power supply voltage in volts. The program assumes that
the op amp is run off two power supplies of equal and opposite polarity each of which is referenced to ground, so it
applies the entered voltage to the op amp as a positive and
negative supply with equal magnitudes. If a single supply op
amp needs to be evaluated just enter half the power supply
voltage, and the analysis will be equivalent.

10

I(RF)-I(RI)
I(RF)
I(RI)

>4---'-- OUT
-10
-10

o

-s

5

10

V1N(mV)

FIGURE 7. NON-INVERTING OP AMP SCHEMATIC (DC)

10

FIGURE 8. NON-INVERTING OP AMP INPUT CURRENT PLOT

~~-----.-------,--------~-------,

10

!(Vee)

Iii

-~

1./) .....

Ww

bC

zO

I(Ved

-5

o

D..~

-10
5

10

-10

-s

o

5

VIN(mV)

V1N(mV)

10

D..W

--+-- O\lT1

-_......>--+--OUT2
Ru

eMMR = DB(V(IN1)-V(11))-(V(IN2)-V(21)) = DB ~VIO
(V(IN2)-V(IN1))
~VeM
FIGURE 12. SCHEMATIC AND EQUATION FOR COMMON-MODE REJECTION CIRCUIT

10-138

Application Note 9523
-This program simulates the common-mode rejection ratio for a non-inverting op
-amp. The equation recommended for the calculation is
-CMRR=d8((V(IN1)-V(11)) -(V(IN2)-V(21)))/(V(IN2)-(VIN1)) and this program uses
-two identical op amps to obtain the calculation data. The user
-must specify the feedback resistance, RF, and the load resistance, RL.
-The power supply voltage is set by the parameter ·vsupply". The op amp model
-is entered with a .lib statement. The model in the subcircuit call (x statement) must
-correspond to the model in the .lib statement (2 times) .
.param RF=l K
.param RL=400
.param vsupply=5
.lib b:ha502x.cir
xl INl 11 34 OUTl 3 ha502x
x2 iN2 21 34 OUT2 3 ha502x
VIN1 INl 0 pulse (0 1m .1ns .1ns .1ns lOOns 200ns)
V1N2 IN2 0 pulse (0 2.001 .1 ns .1 ns.l ns lOOns 200ns)
RF1 11 OUTl {R F}
RF221 OUT2 {R F}
RI1 OUTl 0 {Rd
RL2 OUT2 0 {Rd
Vee 3 0 {vsupply}
VEE 4 0 {-l-vsupply
.tran 20ns 420ns
.probe
.end
FIGURE 13. COMMON-MODE REJECTION PROGRAM

3.0
2.0

~
_1.0
w

~

~

""-

0

t;

!;

-:::i

5-1.0

0...J

o

-2.0

eMMR ..

-3.0

Ww

00
zO

to' .1.3mv/
o

50

20LOG~10-3
100

0..==
o..W

.. 63.7dB

150

200

TIME (na)

FIGURE 14. PLOT OF COMMON-MODE REJECTION PROGRAM OUTPUT

10-139



RS1 0 •01

51

'I'r

FIGURE 1. 3V DOWN CONVERTER APPLICATION

~

Harris Semiconductor

-----No. AN9536.1

------

-------------- --- --- ----- ---

Harris Linear

November 1996

PSPICE Performs Op Amp Open Loop Stability Analysis (HA5112)
Authors: Ron Mancini and Doug Youngblood
The open loop stability plot of an op amp circuit, which is commonly called a Bode [1] plot, is often difficult to observe in the
lab because most op amps saturate when the loop is opened.
Since most op amps have a very high open loop gain, one must
work with very small signals when attempting to measure the
open loop transfer function, so even if an answer is obtained it
usually contains a large error. When PSPICE is employed for
the open loop analysis an identical saturation problem occurs
because the PSPICE model is built to emulate all of the op amp
characteristics. The PSPICE saturation will manifest itself in
either of two ways: the program will not be able to calculate a
DC bias point or the results of any calculations will be in error.
A method of obtaining an accurate open loop PSPICE plot of
an op amp is to fool the circuit as shown in Figure lA. The
capacitor, CINV, is added from the inverting node to ground
where it acts like an AC short for the feedback signal. There is
still DC feedback, so the program will converge to a DC bias
point. The plot will show the op amp open loop gain characteristics if the AC output of PSPICE is configured to be a dB plot
of the ratio of the output to input voltage. Although the phase
characteristic can be plotted by PSPICE, it is simpler to
approximate it from the gain plot by noting where the slope
changes (the -3dB breakpoints), and assuming a 45 degree
phase shift resulted from the slope change. Several open loop
plots are shown in Figure 2. The curve marked with inverted
triangles is for the op amp circuit with no feedback resistance
(RFTI and CINV omitted), and it has no relation to the open
loop op amp curve shown in the HA-5112 Data Sheet [2]
because PSPICE did not calculate the correct bias point. This
illustrates the problems that occur when the circuit DC feedback path is broken in an attempt to plot the open loop transfer function. The curve marked with the non-inverted triangles
is for the op amp with RFTI included and CINV connected
from the inverting node to ground. Notice that the resulting
curve closely approximates the open loop curve shown in the
HA-5112 Data Sheet. Also, note that the slope changes to
-4OdBldecade (called a -2 slope) before the curve passes
through OdB, so the op amp will probably oscillate if it is
connected in a gain of one configuration.
Because C 1NV grounds the inverting node for AC, RFTI
appears as a small load to the op amp and has negliable
effect on the AC performance. The output of the op amp
shown in Figure lA is the op amp open loop transfer
function, so when RFI and RGI are added as shown in
Figure 1 B, the circuit calculates the open loop stability
equation A~ A(RG1)/(RF1+RG1).

=

+15V
(31)

>..:..(6..;1):.-_ _ _ OUTPUT

-15V

(21)
ROT1

20K

RFT1
20K

FIGURE IA. CIRCUIT FOR DETERMINING THE OP AMP OPEN
LOOP TRANSFER FUNCTION

cF

+15V

(61)

..I -H- ..I (OUT)

~":";";:"'-_..JoIo,.Jv-

_ _ _ OUTPUT

RF1

FIGURE I B. STABILITY ANALYSIS MODEL DESCRIBED IN THE
PSPICE LISTING

The curve marked with the diamonds is for RFI = 10K and·
RGI = 1K. The closed loop non-inverting gain would be 11,
thus it should be stable according to the data sheet. Notice
that the slope is -1 when it passes through OdB so the closed
loop circuit will be stable. The curve marked with the squares
is for a closed loop non-inverting gain of 5 with a feedback
capacitor, C F, added in parallel with RFI. Without C F the circuit is marginally stable at best because the op amp open
loop transfer function (see Figure 2) has a gain of about 9dB
when the slope changes from -1 to -2, and the attenuation per
the stability equation is -13.9dB. C F was added to the circuit to
introduce a zero into the open loop transfer function, and the
zero cancels out the pole at the second breakpoint causing
the curve to pass through OdB with a -1 slope. Thus, C F stabilizes the circuit for a closed loop gain of 5.
This analysis does not account for manufacturing tolerances
which can be as large as 2 to 1. There are two factors to keep in
mind when considering manufacturing tolerances, and they are
the OdB frequency intercept tolerance and the open loop gain
intercept tolerance.

Copyright © Harris Corporation 1996

10-145

I;;

-:J

I/).J

Ww

60
zO
a..:E
a..w
---1
50

ClK

ARTN

-5V

AGND

NOTE:

1. 0 1• O2 • 0 3 = HFA31 02.

FIGURE 1.
This variable-gain amplifier has high bandwidth ranging from 115MHz at high gain to 225MHz at low gain. and you can
update the gain at a -3MHz rate.

Iii

10ns
propagation delay (the HFA1130's normal saturation recovery time) obtained with the unrestricted output, limiting the
positive swing to 2.5V yields a 2ns response time.

Consider the HFA 1130 based inverting comparator circuit
(Figure 4). The GND at the HFA1130's non-inverting input
forces the internal buffer to output OV at the inverting input.
As soon as VIN rises above OV, the input buffer begins sinking current, and the output signal falls to its negative stop.
When VIN returns below GND, the output transitions high.

2V

I

1V

if.

ovc=t::::II

3.161<0
3.161<0
+5V _1IoN1r--_IIoN.......

'..!:-

TIME (5naiDlY.)

FIGURE 6. COMPARISON OF COMPARATOR RESPONSE
WITH AND WITHOUT OUTPUT LIMITING

AM Modulator Circuit
FIGURE 4. HFA1130 IMPLEMENTED AS AN INVERTING, 2n8,
TTL COMPATIBLE OUTPUT COMPARATOR

The fast overdrive recovery time and wide bandwidth of the
clamp inputs allows these inputs to be driven by high frequency
AC as well as DC signals. When driven at the appropriate

10-158

Application Note 9653
levels, the clamp inputs may be used to form an AM modulator.
Figure 7 shows a complete AM modulator circuit. The HFA1130
Limiting Amplifier is driven by a 4Vp_p carrier signal. The gain
of 2 through the HFA1130 insures that the carrier amplitude is
sufficient to drive the output over its ±3.3V range.
HFA1212

-6V

5100

+o-----------------~~

CARRIER

5100

AM

OUTPUT

INPUT
4Vp..p

-1

FIGURE 7. AM MODULATOR UTILIZING THE HFA1130
LIMITING CAPABIILlTY

Soft Clipping Circuit
Any amplifier stage driven to the limit of its linear range will
cause signal clipping. The circuit described here establishes a
clipping level that is a function of the input signal. The result is a
soft clamp function where the amplifier has one gain in its linear
operating range and a user programmable lower gain when the
output reaches an arbitrary threshold. The circuit may be used
in imaging applications to expand the contrast of low level signals. It can be used in audio circuits to avoid generation of
objectionable harmonics due to hard clipping. It also has application in control loops that otherwise would become unstable
when their error amplifiers saturate. This circuit can be used in
a broad range of applications that require a combination of high
sensitivity for low level Signals and wide dynamic range.
The basic soft clipping circuit, based on the HFA 1135, is
shown in Figure 9. The nominal value of R1 is 1.5kQ which is
the optimum feedback resistor for the H FA1135. Hard clamping results with R2 and R4 shorted, and R3 and Rs removed.
Figure 10 illustrates the hard clamping operation with a
100kHz input signal and clamp levels set at ±1 V. The circuit
has unity gain for inputs that fall between the clamp levels.
The addition of R2 through Rs make the clamp level a function of the input signal. The output for signals in excess of
VCH (Voltage Clamp High) is given by:
Va

The HFA1212 performs the necessary level shifting and inversion to convert the modulating signal input into a pair of antiphase signals that control the high and low clamp inputs. U1A
inverts the signal and level shifts to -1.5V. U1 B inverts that signal forming a complimentary signal centered at + 1.5V.
With a signal input of OV, U2 produces a 3V Pop output at the
carrier frequency. As the signal input varies, U2 produces a
symmetrically modulated carrier with a maximum amplitude
of 6Vp_p. The oscilloscope photograph in Figure 8 shows a
5MHz carrier AM modulated by a 100kHz signal. The
2300V/IlS slew rate of the HFA1130 limits 6Vp_p amplitude
carrier signals to a frequency of 61 MHz. If adjusted for lower
output signal levels, the carrier and modulating frequencies
can be increased to well above 100MHz.

=(VINR2 + VCHR3) I (R2 + R3)·
R2
VCH

R1
R3

6
+

HFA1135

VIN

l

+
VOUT

-f
R4

VCL

FIGURE 9. HFA1135 OUTPUT LIMITING AMPLIFIER
CONFIGURED FOR SOFT LIMITING
~

en
en..J

-::::;

Ww

be

zO
a..:E
a..w

<0
a::
en

FIGURE 8. A 5MHz CARRIER IS AM MODULATED BY A
100kHz SIGNAL

FIGURE 10. HARD CLIPPING RESULTS FROM A GAIN OF
ZERO ABOVE THE CLAMP LEVEL

10-159

Application Note 9653
Figure 11 shows the result with R~ and Ft! set to 1kQ, and
Rs and Rs set to 5kQ. The gain for signals greater than 1V is
116. In .Figure 12, R2 through Rs have been set to 1kQ, and
the gain above 1V is 1/2. Note that the high and low clamp
levels need not be symmetrical; and the attenuation factors
above and below those levels may be different.
Limiting amplifiers are frequently used at the front end of
systems to accommodate wide dynamic range signals that
may extend beyond the common mode range of the system.
While the circuit in Figure 9 performs soft clipping,' it is
restricted to signals within the ±2.4V input voltage range of
the HFA1135. The circuit in Figure 13 incorporates an additional clamp network that allows the circuit to be used with
signals that exceed the input voltage range. Using the values
shown, the circuit has unity gain for signals that range
between ±1 The gain for inputs beyond that range is 1[6.
Soft clipping works for signals up to ±9.4V which is well in
excess of the ±5V power supply. levels for the HFA 1135.

v.

FIGURE 12. SOFT CLIPPING WITH A GAIN OF 1f.O! ABOVE THE
CLAMP LEVEL

·o-'' 'vv-......- - - - - - - ,

VCH

(+1V)

lkO

~
=
VCL

(-1V)

VOUT

1kO

VIN

RS

5kO

L..-.-.---!_ _ _......

-!-:

R4

o-~~4-------~
1kO

FIGURE 13. SOFT CLIPPING CIRCUIT WITH EXTENDED INPUT
RANGE

FIGURE 11. SOFT CLIPPING WITH A GAIN OF 1/6 ABOVE THE
CLAMP LEVEL

10-160

Harris Semiconductor
------

-------~--

---

No. TB334

- ------ - -- -:::: =-~
-- -- ---

=== ==
==

::.=

= ===
==

September 1995

Guidelines for Soldering Surface Mount Components to PC Boards
Author: Maury Rosenfield
The most commonly used techniques for mounting SMDs
(Surface Mounted Devices) to PC boards are Infrared (IR) and
Vapor Phase (VP) reflow. IR and VP reflow are preferred over
wave soldering. Wave soldering typically involves increased
heating rate, higher temperatures and increased flux exposure.
The dynamics of the reflow process are imluenced by the type of
equipment used. The variables involved must be understood to
properly control the board level interconnection of SMDs.

The primary phases of the reflow process are: flux activation,
melting the solder particles in the solder paste, wetting the
surfaces to be joined, and solidifying the solder into a strong
metallurgical bond
Optimum fusing of the component leads with the solder paste
on the board is achieved when the leads attain the melting
temperature of the plated solder alloy. To avoid thermal shock of
the SMDs the maximum heating and cooling rates (i.e., ramp
rate) should be controlled.

IRRef/ow
The IR reflow technique involves thermal energy supplied via
lamps radiating at a given range of wavelength. This heating
approach in its basic form is essentially a line-of-sight surfaceheating technique. Therefore, the amount of thermal energy
absorbed varies with board size, component size, component
orientation, and materials used. The surface temperature of
the board is not uniform throughout and board edges tend to
run 10°C to 200C higher than the center. If not properly
planned, component overheating is possible.

Vapor Phase Ref/ow
The vapor phase reflow technique uses vapor from a boiling
inert fluorocarbon liquid. The heat of condensation provides a
thermal constraint dependent on the liquid selected. A typical
material in the industry has a boiling point of 21 SOC. PC board
temperature exposure should be very uniform. With essentially
no temperature gradient across the surface of the board,
component location design rules for even heating is not
significant compared to IR reflow.

temperature of the component and the PC board should be
within the range from 10SoC to 145°C.
Time above Solder Melting Point - It is recommended that the
solder at the joint be kept above its melting point for sufficient
time to flow and wet the lands and the leads. Depending on
type of equipment and component size; time above 1WC
could range from 10s to 15Os. Extended duration above the
solder melting point may damage the board and sensitive
components. This value should be minimized but sufficient to
allow for good solder joint formation.
Peak 'Reflow Temperature - The peak temperature of the
solder joint during reflow should be high enough for adequate
flux action and solder flow to obtain good wetting. The preferred
peak temperatures for IR and VP reflow are 21SoC - 2200C.
Residence time at peak temperatures should be minimized.
Cooling Rate - The cooling rate of the solder joint after reflow
is important because the faster the cooling rate, the smaller the
grain size of the solder, and the higher the fatigue resistance.
However, care should be taken to avoid an excessive
temperature gradient resulting in potential damage due to
mechanical stress.

Summary of Soldering Precautions
The soldering process can create a ·thermal stress on any
semiconductor component. The melting temperature of solder
is higher than the maximum rated temperature of the device.
The amount of time the device is heated to a high temperature
should be minimized to assure device reliability. Therefore, the
following precautions should always be observed in order to
minimize the thermal stress to which the devices are subjected.
1. Always preheat the device.
2. The delta temperature between the preheat and soldering
should always be less than 100°C. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
3. The maximum temperature gradient should be less than SoC
per second when changing from preheating to soldering.
4. The peak temperature in the soldering process should be at
least
higher th8n the melting point of the solder chosen.
S. The maximum soldering temperature and time forwave
soldering must not exceed 260°C for Ss on the leads and
case of the device.
6. After soldering is complete, forced cooling will increase
the temperature gradient and may result in latent failure
due to mechanical stress.
7. During cooling, mechanical stress or shock should be
avoided.

aooc

Solder Profile Development
Heating Rate - To avoid thermal shock to sensitive
components the maximum heating rate should be controlled. It
is desirable to hold the heating rate to less than SOC/s.
Preheat Zone - Boards should be preheated prior to the reflow
step. Over-baking the solder paste and exceeding the glass
transition temperature of the epoxy in FR-4 boards should be
avoided. Depending on the type of IR or VP equipment, the
Copy~ghl @Harrls Corporation 1995

10-161

•
Iii

-:J
Ww

en..J

150
zO
D.,:::i:
D.,W
~o

a::en

11
PACKAGING INFORMATION

PAGE
LINEAR PACKAGE SELECTION GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2
PACKAGE OUTLINES

Dual-In-Line Plastic Packages (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8
Small Outline Plastic Packages (SOl C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-14
Power Small Outline Plastic Packages (PSOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-20
Plastic Leaded Chip Carrier Packages (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-22
Metric Plastic Quad Flatpack Packages (MQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-24
Ceramic Dual-In-Line Metal Seal Packages (SBDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-25
Ceramic Dual-In-Line Frit Seal Packages (CERDIP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-28
Metal Can Packages (Can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-31

11-1

Linear Package Selection Guide
Using the Selection Guide:
The first character of each entry indicates the package type, while the number precedlng.the decimalpoint details the package lead count. Except for Can packages, the decimal point and succeeding numbers specify the package width in inches
(e.g. _.15 150 mil width). The entire entry indicates the table containing the appropriate package dimensions (e.g. B lead
PDIP dimensions are detailed in Table EB.3).

=

PDIP

SOIC,SSOP,
TSSOP,PSOP

CA124

E14.3

M14.15

-

CA1391

E8.3

-

CA1394

E8.3

-

PART NUMBER

CA139

E14.3

M14.15

CA1458

E8.3

CA155B

EB.3

-

CA15B

EB.3

MB.15

CA224

E14.3

M14.15

CA239

E14.3

M14.15

-

CAN

-

-

-

F14.3
TB.C

TB.C

-

F14.3

-

-

M14.15

-

F14.3,D14.3

-

-

-

-

-

-

-

-

-

-

-

-

EB.3

MB.15

EB.3

MB.15

CA3020

-

-

CA302B

EB.3

-

MB.15

CA3045

-

CA3046

E14.3

M14.15

CA3053

EB.3

-

CA3054

E14.3

M14.15

CA3060

E16.3

-

CA307B

EB.3

MB.15

-

CA3049

QUAD
FLATPACK

TB.C

CA25B

CA3039

CERDIP(F),
SBDIP(D)

-

CA2904
CA301B

PLCC

CA30BO

EB.3

MB.15

CA30Bl

E16.3

M16.15

CA30B2

E16.3

M16.15

CA30B3

E16.3

M16.15

CA30B6

E14.3

M14.15

CA30B9

E16.3

M20.3

CA3094

EB.3

MB.15

CA3096

E16.3

M16.15

CA309B

EB.3

-

CA31 00

EB.3

MB.15

CA31 02

E14.3

M14.15

CA3126

E16.3

M20.3

F16.3
F16.3
F16.3

-

F14.3

-

-

-

-

-

M 16 .15

EXAMPLE:

PACKAGE
TYPE

J LEAD
TL
COUNT

11-2

BODY
WIDTH

TB.C

-

T12.B
T12.B
TB.C
T12.B

-

-

T12.B
TB.C

TB.C
TB.C

-

TB.C

TB.C

Linear Package Selection Guide
CERDlP(F},
SBDIP(D)

QUAD
FLATPACK

·

·

PDIP

SOIC,SSOP,
TSSOP,PSOP

CA3l27

E16.3

M16.l5

CA3l30

EB.3

MB.15

·

CA3l40

EB.3

MB.15

CA3l4l

E16.3

·

CA3l46

E14.3

M14.l5

·
·
·

·
·
·
·

CA3l60

EB.3

·

CA31B3

E16.3

M16.l5

CA31B9

E16.3

PART NUMBER

PLCC

CA3l93

EB.3

CA3227

Elf/.3

M16.l5

CA324

E14.3

M14.l5

CA3240

EB.3, E14.3

·

·

CA3246

E14.3

M14.l5

CA3256

E1B.3

M20.3

·
·
·
·
·

CA3260

EB.3

CA32BO

E16.3

CA3290

EB.3, E14.3

·
·

CA339

E14.3

M14.l5

CA3420

EB.3

·

CA3440

EB.3

MB.15

CA3450

E16.3

CA35B

EB.3

MB.15

CA5l30

EB.3

MB.15

CA5l60

EB.3

MB.15

CA5260

EB.3

MB.15

CA5420

EB.3

MB.15

CA5470

E14.3

M14.l5

·

CA555

EB.3

MB.15

·

TB.C

·

·

·

·

·

TB.C

·
·
·

·

·

·
·

·

·

TB.C

F16.3

·

·

·

TB.C

·

TB.C

·
·
·
·
·
·

·

·

·
TB.C
TB.C

·

·
·

·
·
·

·

·

·

TB.C

·
·

·

TB.C

·

TB.C

024.6

·

F16.3

·
·

·
·
·
·
·
·
·
·

CA741

EB.3

·

·

E24.6

HA·2400

·
·

HA·2404

·
·

·
·

HA·2405

E16.3

·

HA·2406

E16.3

M16.3

·
·

F16.3
F16.3

HA·2420

·

·

·

F14.3

HA·2425

E14.3

M14.l5

N20.35

F14.3

HA·2444

E16.3

M16.3

HA·2500

·

·

HA·2502

·

·

·
·
M 16.15

TL

·

FB.3A

·
·
·

TB.C

FB.3A

·

TB.C

·

PACKAGE...J
TYPE
LEAD
COUNT

TB.C

·

F16.3

11·3

TB.C

·

·
·
·
·

·
·

CD22402

EXAMPLE:

TB.C

·
·
·

·

·
·

CAN

BODY
WIDTH

Linear Package Selection Guide

PART NUM"'ER
HA-2505

PDIP

SOIC,SSOP,
TSSOP,PSOP

PLCC

CERDIP(F),
SBDIP(D)

EB.3

-

-

FB.3A

-

-

FB.3A

-

-

FB.3A

-

-

HA-2512

-

HA-2515

EB.3

HA-2520

-

HA-2510

HA-2522

-

HA-2525

EB.3

HA-2529

-

FB.3A
FB.3A

-

FB.3A

MB.15

N20.35

FB.3A

EB.3

MB.15

-

FB.3A

HA-2539

E14.3

M14.15

HA-2540

E14.3

M14.15

HA-2541

-

HA-2542

E14.3

-

HA-2544

EB.3

MB.15

HA-2546

E16.3

M16.3

HA-2547

-

-

HA-254B

EB.3

M16.3

HA-2556

E16.3

M16.3

HA-2557

E16.3

M16.3

-

-

HA-2605

EB.3

MB.15

HA-2620

-

-

HA-2600
HA-2602

HA-2622

-

-

HA-2625

EB.3

MB.15

HA-2640

-

F14.3

-

-

F14.3
F14.3
F14.3
FB.3A

-

-

F16.3
F16.3
DB.3
F16.3
F16.3
FB.3A
FB.3A
FB.3A

-

FB.3A

-

FB.3A

-

FB.3A

HA-2645

-

HA-2B39

E14.3

-

HA-2B40

EB.3. E14.3

MB.15

HA-2B41

EB.3. E14.3

MB.15

-

-

HA-2B42

EB.3. E14.3

MB.15

-

HA-2B50

EB.3. E14.3

MB.15

-

HA4201

EB.3

MB.15

HA4244

-

M8.15

HA4314B

E14.3

M14.15

HA4344B

E16.3

M16.15

HA4404B

E16.3

M16.15

-

-

HA456
HA457

-

HA4600

EB.3

-

FB.3A
F14.3
FB.3A

-

-

-

-

N44.65

-

-

-

-

MB.15
EXAMPLE:

FB.3A

M 16 _15

TL

PACKAGE...J
TYPE
LEAD
COUNT

11-4

BODY
WIDTH

QUAD
FLATPACK

-

-

-

-

-

-

-

-

-

-

Q44.10X10
Q44.10X10

-

CAN
TB.C
TB.C
TB.C
TB.C
TB.C
TB.C
TB.C
TB.C

T12.C
T12.C
TB.C

TB.C

TB.C
TB.C
TB.C
TB.C
TB.C
TB.C
TB.C
TB.C

-

-

-

-

-

Linear Package Selection Guide

PDIP

SOIC,SSOP,
TSSOP,PSOP

PLCC

CERDIP(F),
SBDIP(D)

QUAD
FLATPACK

HA-4741

E14.3

M16.3

-

F14.3

-

HA-4900

-

-

PART NUMBER

-

F16.3

HA-4905

E16.3

M16.3

N20.35

F16.3

HA-5002

EB.3

MB.15

N20.35

FB.3A

HA-5004

-

-

-

F14.3

HA5013

E14.3

M14.15

HA-5020

EB.3

MB.15

HA5022

E16.3

M16.15

HA5023

EB.3

MB.15

HA5024

E20.3

M20.3

HA5025

E14.3

M14.15

HA-5033

EB.3

MB.15A

HA-5101

EB.3

MB.15

HA-5102

EB.3

M16.3

HA-5104

E14.3

M16.3

HA-5111

EB.3

MB.15

HA-5112

EB.3

M16.3

HA-5114

E14.3

M16.3

HA-5127

EB.3

MB.15

HA-5130

-

-

HA-5134
HA-5135

EB.3

MB.15

HA-5142

EB.3

M16.3

HA-5144

E14.3

M16.3

HA-5147

EB.3

HA-5170

-

HA-5177

EB.3

HA-5190

-

HA-5162

HA-5195

-

-

-

-

-

-

TB.C

-

-

-

-

FB.3A
F14.3
FB.3A

HA-5222

E16.3

M16.3

HA-5320

E14.3

M16.3

HA-5330

E14.3

-

HA-5340

E14.3

M16.3

HA5351

EB.3

MB.15

-

FB.3A
F14.3

-

-

-

TB.C

FB.3A

-

FB.3A

-

-

-

-

TB.C

-

TB.C

F14.3
F14.3
FB.3A
FB.3A
F14.3
F14.3
F14.3

PACKAGE
TYPE

J LEAD
TL
COUNT

11-5

BODY
WIDTH

TB.C

-

TB.C

-

T12.C

TB.C

-

FB.3A

M 16 _15

EXAMPLE:

TB.C

FB.3A

FB.3A

MB.15

T12.C

F14.3

F14.3

M14.15

-

-

FB.3A

-

EB.3

-

FB.3A

FB.3A

-

TB.C

TB.C

FB.3A

-

-

HA-5221

-

FB.3A

-

HA-5137

HA-5160

-

F16.3

-

HA-4902

CAN

T12.C
TB.C

-

Linear Package Selection Guide

PDIP

SOIC,SSOP,
TSSOP,PSOP

HA721 0

EB.3

MB.15

HA7211

-

MB.15

PART NUMBER

PLCC

CERDIP(F),
SBDIP(D)

QUAD
FLATPACK

-

-

-

HFAll00

EB.3

MB.15

FB.3A

HFAll02

EB.3

MB.15

FB.3A

HFAll03

EB.3

MB.15

HFAll05

EB.3

MB.15

HFAll06

EB.3

MB.15

HFA1109

EB.3

MB.15

HFA1110

EB.3

MB.15

HFAll12

EB.3

MB.15

HFAl113

EB.3

MB.15

HFAl114

EB.3

MB.15

HFAll15

EB.3

MB.15

HFA111B

EB.3

MB.15

HFAl119

EB.3

MB.15

HFAl120

EB.3

MB.15

HFAll30

EB.3

MB.15

HFAll35

EB.3

MB.15

HFAll45

EB.3

MB.15

HFAl149

EB.3

MB.15

HFA1205

EB.3

HFA1212

EB.3

HFA1245

E14.3

M14.15

HFAl405

E14.3

M14.15

HFA1412

E14.3

M14.15

HFA3046

-

M14.15

HFA3096

-

M16.15

HFA3101

-

MB.15

HFA3102

-

M14.15

HFA3127
HFA312B
HFA3600

-

-

-

-

FB.3A
FB.3A

-

-

FB.3A

-

-

-

-

-

-

MB.15

-

-

-

-

HFA5253

-

ICL7611

EB.3

MB.15

ICL7612

EB.3

MB.15

ICL7621

EB.3

MB.15

ICL7641

E14.3

ICL7642

E14.3

-

-

-

-

-

-

M20.3A

-

-

-

-

M 16.15

EXAMPLE:

PACKAGE
TYPE

J LEAD
TL
COUNT

11-6

-

FB.3A

MB.15

M2B.3

-

-

M14.15

-

-

-

M16.15

-

-

-

FB.3A

M16.15

-

-

-

HFA5250

-

CAN

BODY
WIDTH

-

-

-

-

-

-

-

-

TB.C
TB.C
TB.C

-

Linear Package Selection Guide

PART NUMBER
ICL7650S

PDIP

SOIC,SSOP,
TSSOP,PSOP

E8.3. E14.3

M8.15. M14.15

PLCC

CERDIP(F),
SBDIP(D)

QUAD
FLATPACK

F14.3

CAN
T8.C

ICL8013

T10.C

.

F14.3

-

-

ICL8038

E14.3

ICM7242

E8.3

M8.15

ICM7555

E8.3

M8.15

ICM7556

E14.3

-

LM1458

E8.3

LM2901

E14.3

M14.15

LM2902

E14.3

M14.15

-

M14.15

-

LM2904

E8.3

LM324

E14.3

LM3302·

E14.3

LM339

E14.3

LM358

E8.3

LM555

E8.3

LM741

E8.3

-

-

T8.C

F14.3

-

-

-

T8.C

M 16.15

EXAMPLE:

PACKAGE
TYPE

J LEAD
TL
COUNT

11-7

BODY
WIDTH

Plastic Packages for Integrated Circuits
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC M8-001·BA ISSUE D)
8 LEAD DUAL-IN-LiNE PLASTIC PACKAGE

,~-[::IJt
~..

0

INCHES

~~~Ja.'

MIN

MAX

MIN

MAX

A

-

0.210

-

5.33

4

Al

0.015

-

0.39

-

4

A2

0.115

0.195

2.93

4.95

B

0.014

0.022

0.356

0.558

-

Bl

0.045

0.070

1.15

1.77

8, 10

C

0.008

0.014

0.204

0

0.355

0.400

9.01

01

0.005

-

E

0.300

0.325

El

0.240

0.280

6.10

~E;j

_,

r+
!
£

~

d\1 ~'::'::~CI:'I';I{t:j

SEATING
PLANE

L

;

MILLIMETERS

SYMBOL

NOTES:

0.355

NOTES

-

10.16

5

0.13

-

5

7.62

8.25

6

7.11

5

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

e

0.100BSC

2.54BSC

-

eA

0.300BSC

7.62BSC

6

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

eB

-

3. Symbols are defined in the "MO Series Symbol Lisr in Section
2.2 of Publication No. 95.

L

0.115

N

4. Dimensions A, Aland L are measured with the package seated
in JEDEC seating plane gauge GS-3.

I
I
8

0.430

-

10.92

0.150

2.93

3.81
8

7
4
9
Rev. 0 12193

5. D, 01, and El dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 Inch
(0.25mm).
6. E and ~ are measured with the leads constrained to be perpendicu ar to datum ~.
7. eB and ee are measured at the lead tips with the leads unconstrained. ee must be zero or greater.
8. Bl maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.01 0 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, NI2 and Nl2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a Bl dimension of 0.030 - 0.045 Inch
(0.76 - 1.14mm).

11-8

Plastic Packages for Integrated Circuits
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LiNE PLASTIC PACKAGE

I~~~!-~Q1!JIE_1_
~

INCHES
SYMBOL

MIN

MAX

MILLIMETERS
MIN

MAX

0.210

0.115

0.195

2.93

0.014

0.022

0.356

0.045

0.070

1.15

0.008

0.014

0.204

0.735

0.775

18.66

0.300

0.325

7.62

e

0.240

0.280

6.10

0.100BSC

2.54BSC

0.300BSC

7.62 BSC

2. Dimensioning and tolerancing per ANSI YI4.5M-1982.

0.430

3. Symbols are defined in the "MO Series Symbol Lisf' in Section
2.2 of Publication No. 95.

L

4. Dimensions A, A 1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, Dl, and El dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and

leAl

are measured with the leads constrained to be per-

pendic~to datum ~.

7. ee and ee are measured at the lead tips with the leads unconstrained. ee must be zero or greater.
8. Bl maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (I, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a Bl dimension of 0.030 - 0.045 inch
(0.76-1.14mm).

11-9

N

4

0.13

0.005

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

NOTES

4

0.39

0.015

NOTES:

5.33

0.115

0.150
14

2.93
14

6

10.92

7

3.81

4
9
Rev. 0 12193

Plastic Packages for Integrated Circuits
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC M8-001·BB ISSUE D)
16 LEAD DUAL·IN·UNE PLASTIC PACKAGE
INCHES
SYMBOL

MIN

MAX

A

NOTES:
1. Controlling Dimensions: INCH. In cese of confllc1 between
English and Metric dimensions. the inch dimensions control.
2. Dimensioning and toIerancing per ANSI YI4.5M-1982.

0.210

5. D. Dl. and El dimensions do not include mold flesh or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

leAl

6. E and
are measured with the leads constrained to be perpendiCiTafto datum ~.
7. ee and ee are measured at the lead tips with the leads unconstrained. ee must be zero or greater.
8. Bl maximum dimensions do not Include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N Is the maximum number of terminal positions.
10. Comer leads (1. N. NI2 and N/2 + 1) for E8.3. EI6.3. EI8.3.
E28.3. E42.6 will have a Bl dimension of 0.030 - 0.045 inch
(0.76 -1.14mm).

11-10

NOTES
4

0.015

A2

0.115

0.195

2.93

4.95

0.39
0.558

4

B

0.014

0.022

0.356

Bl

0.045

0.070

1.15

1.77

C

0.008

0.014

0.204

0.355

0.775

18.66

19.68

8. 10

D

0.735

Dl

0.005

E

0.300

0.325

7.62

8.25

6

El

0.240

0.280

6.10

7.11

5

0.13

0.100BSC

2.54BSC

eA

0.300SSC

7.62 SSC

N

0.430
0.115

0.150
16

5
5

e

L

4. Dimensions A. Aland L are measured with the package seated
in JEDEC seating plane gauge GS-3.

MAX
5.33

AI

ee

3. Symbols are defined In the "MO Series Symbol Lisr In Sec1lon
2.2 of Publication No. 95.

MILUMETERS
MIN

10.92
2.93

3.81
16

6
7
4
9
Rev. 0 12193

Plastic Packages for Integrated Circuits
Dual-In-Line Plastic Packages (PDIP)
E18.3 (JEDEC MSoOO1·BC ISSUE D)
18 LEAD DUAL·IN-LiNE PLASTIC PACKAGE
INCHES
SYMBOL

MIN

MAX

A
Al

NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the Inch dimensions control.
2. Dimensioning and tolerancing per ANSi Y14.5M-1982.

0.115

0.195

B

0.014

0.022

Bl

0.045

0.070

C

0.008

0.014

D

0.845

0.880

Dl

0.005

E

0.300

0.325

El

0.240

5. D, Dl, and El dimensions do not inciude mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(O.25mm).

reAl

6. E and
are measured wIIh the leads constrained to be perpendic!Tafto datum ~.
7. ee and ee are measured at the lead tips with the leads unconstrained. ee must be zero or greater.
8. Bl maximum dimensions do not Include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Comer leads (1, N, NI2 and Nl2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a Bl dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

11-11

4

0.280

4.95

7.11

6.10

e

0.100BSC

2.54BSC

eA

0.300BSC

7.62 BSC

N

NOTES

4

0.015

A2

L

4. Dimensions A, Aland L are measured with the package seated
in JEDEC seating plane gauge GS-3.

MAX

5.33

0.210

10.92

0.430

ee

3. Symbols are defined in the "MO Series Symbol Lisf in Section
2.2 of Publication No. 95.

MILLIMETERS
MIN

0.115

0.150
18

2.93

3.81
18

5

6
7
4
9
Rev. 0 12193

Plastic Packages for Integrated Circuits
Dual-In-Line Plastic Packages (PDIP)
E20.3 (JEOEC MS-001·AD ISSUE 0)
20 LEAD DUAL·IN·LlNE PLASTIC PACKAGE
INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

A

-

0.210

-

5.33

4

Al

0.015

0.39

-

4

A2

0.115

0.195

2.93

4.95

-

B

0.014

0.022

0.356

0.558

Bl

0.045

0.070

1.55

1.77

C

0.008

0.014

0.204

0.355

NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the Inch dimensions control.
2. Dimensioning and tOlerancing per ANSI Y14.5M·19B2.
3. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication No. 95.
4. Dimensions A, Aland L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. 0, 01, and El dimensions do not include mold flash or protru·
sions. Mold flash or protrusions shall not exceed 0.010 Inch
(0.25mm).
6. E and re;:J are measured with the leads constrained to be perpendicU18rto datum ~.
7. ee and ee are measured at the lead tips with the leads unconstrained. ee must be zero or greater.
B. Bl maximum dimensions do not Include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal pOSitions.
10. Corner leads (1, N, N/2 and Nl2 + 1) for EB.3, E16.3, E1B.3,
E2B.3, E42.6 will have a Bl dimension of 0.030 - 0.045 inch
(0.76-1.14mm).

11-12

MAX

NOTES

B

0

0.980

1.060

01

0.005

-

0.13

E

0.300

0.325

7.62

8.25

6

El

0.240

0.280

6.10

7.11

5

e

0.100 BSC

eA

0.300BSC

24.89

26.9

5
5

2.54 BSC
7.62 BSC

6

ee

-

0.430

-

10.92

7

L

0.115

0.150

2.93

3.81

4

N

20

20

9
Rev. 0 12193

Plastic Packages for Integrated Circuits
Dual-In-Line Plastic Packages (PDIP)
E24.6 (JEDEC MS-D11-AA ISSUE B)
24 LEAD DUAL-IN-L1NE PLASTIC PACKAGE
INCHES
SYMBOL

MIN

MAX

A

NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

5. 0, 01, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and re;;l are measured with the leads constrained to be perpendic.Tafto datum ~.
7. ee and ee are measured at the lead tips with the leads unconstrained. ee must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Comer leads (1, N, NI2 and NI2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76-1.14mm).

11-13

6.35

A1

0.015

A2

0.125

0.195

3.18

4.95

0.39

0.558

NOTES
4
4

B

0.014

0.022

0.356

B1

0.030

0.070

0.77

1.77

C

0.008

0.D15

0.204

0.381

1.290

29.3

32.7

8

5

0

1.150

01

0.005

E

0.600

0.625

15.24

15.87

6

E1

0.485

0.580

12.32

14.73

5

5

0.13

e

0.100BSC

2.54 BSC

eA

0.600BSC

15.24 BSC

L

4. Dimensions A, A 1 and L are measured with the package seated
in JEDEC seating plane gauga GS-3.

MAX

0.250

0.700

ee

3. Symbols are defined in the "MO Series Symbol Lisf' in Section
2.2 of Publication No. 95.

MILLIMETERS
MIN

N

0.115

0.200
24

2.93
24

6

17.78

7

5.08

4
9
Rev. 0 12193

Plastic Packages for Integrated Circuits
Small Outline Plastic Packages (SOIC)
M8.15 (.,IEDEC M8-012·AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
. INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

NOTES

A

0.0532

0.0688

1.35

1.75

-

AI

0.0040

0.0098

0.10

0.25

-

B

0.01.3

0.020

0.33

0.51

9

C

0.0075

0.0098

0.19

0.25

-

0

0.1890

0.1968

4.80

5.00

3

E

0.1497

0.1574

3.80

4.00

4

e

0.050BSC

-

H

0.2284

0.2440

5.80

6.20

-

h

0.0099

0.0196

0.25

0.50

5

L

0.016

0.050

0.40

8

N

a

NOTES:

1.27BSC

0"

1.27

8°

0°

6
7

8
8°

Rev. 0 12193

1. Symbols are defined in the "MO Series Symbol Lisr in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI YI4.5M-1982.
3. Dimension "0" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
O.I5mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per Side.
5. The chamfer on the body Is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured O.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

11-14

Plastic Packages for Integrated Circuits
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC M8-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
MILLIMETERS

INCHES
SYMBOL

MIN

MIN

MAX

NOTES

A

0.0532

0.0688

1.35

1.75

-

Al

0.0040

0.0098

0.10

0.25

B

0.013

0.020

0.33

0.51

C

0.0075

0.0098

0.19

0.25

-

0

0.3367

0.3444

8.55

8.75

3

E

0.1497

0.1574

3.80

4.00

4

e

0.050BSC

1.27 BSC

9

-

H

0.2284

0.2440

5.80

6.20

h

0.0099

0.0196

0.25

0.50

5

L

0.016

0.050

0.40

1.27

6

8°

0°

N

a
NOTES:

MAX

14
0°

14

7
8°

Rev. 0 12193

1. Symbols are defined in the "MO Series Symbol Lisf in Section
2.2 of Publication Number 95.
2. Dimensioning and toleranclng per ANSI Y14.5M-1982.
3. Dimension "0" does not include mold flash, protrusions or gate
burrs. Mold nash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

11-15

Plastic Packages for Integrated Circuits
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC M8-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
SYMBOL

MIN

MIN

MAX

NOTES

A

0.0532

0.0688

1.35

1.75

Al

0.0040

0.0098

0.10

0.25

-

B

0.013

0.020

0.33

0.51

9

C

0.0075

0.0098

0.19

0.25

D

0.3859

0.3937

9.80

10.00

3

E

0.1497

0.1574

3.80

4.00

4

H

0.2284

0.2440

5.80

6.20

-

h

0.0099

0.Q196

0.25

0.50

5

L

0.Q16

0.050

0.40

1.27

e

0.050BSC

N
IX

NOTES:

MILLIMETERS

MAX

1.27 BSC

16

16
0°

I

8°

0°

6
7

8°

Rev. 0 12193

1. Symbols are defined in the "MO Series Symbol Lisf' in Sectic;ln
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not Include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 Inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" Is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILliMETER. Converted Inch dimensions are not necessarily exact.

11-16

Plastic Packages for Int,grated Circuits
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC M8-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
SYMBOL

I-B-D---1 ~

--11--hX45

~~~t, a{
T~-II
LA1 ~

-T

B__

--

1+1 0.25(0.010) el c IA(!)I B(!)I

1010.10(0.004)

MILLIMETERS

MAX

MIN

MIN

MAX

NOTES

-

A

0.0926

0.1043

2.35

2.65

AI

0.0040

0.0118

0.10

0.30

9

B

0.013

0.0200

0.33

0.51

C

0.0091

0.0125

0.23

0.32

-

0

0.3977

0.4133

10.10

10.50

3

E

0.2914

0.2992

7.40

7.60

4

0

e

H

I

0.050BSC
0.394

10.00

10.65

-

h

0.010

0.029

0.25

0.75

5

L

0.Q16

0.050

0.40

1.27

6

8°

00

N

a
NOTES:

0.419

1.27BSC

16
0°

16

7
8°

Rev. 0 12193

1. Symbols are defined in 1I1e "MO Series Symbol Lisr in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI YI4.5M-1982.
3. Dimension "0" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interfead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within 1I1e crosshatched area.
6. "L" is the leng1l1 of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above 1I1e seating plane, shall not exceed a maximum value of
0.61 mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

11-17

Plastic Packages for Integrated Circuits
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC M5-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

A

0.0926

0.1043

2.35

2.65

A1

0.0040

0.0118

0.10

0.30

B

0.013

0.0200

0.33

0.51

C

0.0091

0.0125

0.23

0.32

-

0

0.4961

0.5118

12.60

13.00

3

E

0.2914

0.2992

7.40

7.60

4

I-B-D_I

~~-ill.i-+- a(

e

-T T~-II

LA1 "
B__ -1010.10(0.004) I
1+10.25(0.010)$1 c IA$IB$I

0.050BSC

9

-

H

0.394

0.419

10.00

10.65

-

h

0.010

0.029

0.25

0.75

5

L

0.016

0.050

0.40

1.27

20

N

a

NOTES:

1.27BSC

NOTES

00

20
80

0°

6
7

80

Rev. 0 12193

1. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication Number 95.
2. Dimensioning and toleranclng per ANSI Y14.5M·1982.
3. Dimension "0" does not Include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Intenead flash and protrusions shall not exceed 0.25mm (0.010
Inch) per side.
5. The Chamfer on the body is optional. If it is not present, a visual
Index faature must be located within the crosshatched area.
6. "L" Is the length of terminal for soldering to a substrate.
7. "N" Is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured O.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 Inch)
10. Controlling dimension: MILLIMETER. Converted Inch dimensions are not necessarily exact.

11-18

Plastic Packages for Integrated Circuits
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES

MAX

NOTES

0.0926

0.1043

2.35

2.65

-

A1

0.0040

0.0118

0.10

0.30

MAX

MIN

MIN

B

0.013

0.0200

0.33

0.51

C

0.0091

0.0125

0.23

0.32

D

0.6969

0.7125

17.70

18.10

3

E

0.2914

0.2992

7.40

7.60

4

e

0.05 BSC

9

1.27 BSC

H

0.394

0.419

10.00

10.65

h

0.01

0.029

0.25

0.75

5

L

0.Q16

0.050

0.40

1.27

6

80

00

N
IX

NOTES:

MILLIMETERS

A

SYMBOL

28

28
00

7
80
Rev. 0 12193

1. Symbols are defined in the "MO Series Symbol Lisf' in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

11-19

Plastic Packages for Integrated Circuits
Power Small Outline Plastic Packages (PSOP)

T
E

~

!It)
j

I.£ELD_I~

~M~J,

-T T~~II

M8.15A
0.25(0.010)

®1B ®1

8 LEAD POWER SMALL OUTLINE PLASTIC PACKAGE
MILLIMETERS

INCHES
SYMBOL

--11--hX450

(/

LAI "
IQI 0.10(0.004) 1
1t)0.25{0.010)el C IA®I B(!>I

MIN

MAX

NOTES

0.0532

0.0688

1.35

1.75

Al

0.0040

0.0098

0.10

0.25

-

B

0.0130

0.0200

0.33

0.51

9

C

0.0075

0.0098

0.19

0.25

-

D

0.1890

0.1968

4.80

5.00

3

Dl

0.107

0.123

2.72

3.12

10

E

0.1497

0.1574

3.80

4.00

4

0.071

0.087

1.80

2.21

10

e

BOTTOM VIEW

MAX

A

El

B __ . - -

MIN

0.050 BSC

1.27 BSC

H

0.2284

0.2440

5.80

6.20

h

0.0099

0.0196

0.25

0.50

5

L

0.Q16

0.050

0.40

1.27

B

N
(l

8
0°

8
8°

0°

7

-

8°

Rev. 0 10/96
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
POWER SOP PACKAGE
(HEAT SLUG SURFACE IS
ELECTRICALLY FLOATING)

3. Dimension "0" does not include mold flash, protrusions or gate
burrs. Mold flash. protrusion and gate burrs shall not exceed
0.15mm (O.OOB inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
B. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.3Bmm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
O.Blmm (0.024 inch)
10. Exposed copper heat slug flush with bottom surface of package.
All other dimensions conform to JEDEC MS-012 Issue C.
11. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

11-20

Plastic Packages for Integrated Circuits
Power Small Outline Plastic Packages (PSOP)
M20.3A
20 LEAD POWER SMALL OUTLINE PLASTIC PACKAGE
INCHES

I..ELD_I~

~M~;'

- T T~~II
B__

--11--hX450

a{

LA1 \..
--

ItJ 0.25(0.010) $1 C IA $1 B (!) I

1010.10(0.004)

MAX

NOTES

0.0926

0.1043

2.35

2.65

-

Al

0.0040

O.OllB

0.10

0.30

TOP VIEW

MAX

MIN

MIN

B

0.013

0.0200

0.33

0.51

C

0.0091

0.0125

0.23

0.32

-

0

0.4961

0.5116

12.60

13.00

3

9

10

01

0.325

0.340

B.25

B.63

E

0.2914

0.2992

7.40

7.60

4

El

0.175

0.190

4.44

4.62

10

e

I

MILLIMETERS

A

SYMBOL

0.394

h
L

0.419

10.00

10.65

0.010

0.029

0.25

0.75

5

0.D16

0.050

0.40

1.27

6

BO

00

N

a

-

1.27 BSC

0.050 BSC

H

20
00

I

20

7

-

BO

Rev. 0 6/95
NOTES:
1. Symbols are defined in the "MO Series Symbol Lisr in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1962.
POWER SOP PACKAGE
(HEAT SLUG SURFACE IS ELECTRICALLY FLOATING)

3. Dimension "0" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
Index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
B. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Exposed copper heat slug flush with top surface of package. All
other dimensions conform to JEDEC MS-013AC Issue C.
11. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

11-21

Plastic Packages for Integrated Circuits
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.0n

0.048(1.22)

. . ."",'" h ....... ,
0.042 (1.07)
0.056(1.42)

~'"'''~"~
1__ \ -;-1 III

I

1

--

+

j

~!

~!~

E1E

0.045 (1.14)

'/

INCHES

:

-- -'11--'- I

MIN

MAX

MIN

MAX

A

0.165

O.IBO

4.20

4.57

At

0.090

0.120

2.29

3.04

0

0.3B5

0.395

9.7B

10.03

01

0.350

0.356

B.B9

9.04

3

02

0.141

0.169

3.59

4.29

4.5

~-

.~t VIEW "A"

r

0.020 (0.51)
. . -MIN
. . A1 ...
...A ...

..
•

~SEATING

0.020 (0.51) MAX
3PLCS

- - PLANE

0.026 (0.66)
0.032 (0.81)

0.013 (0.33)

~_+ 0.021 (0.53)
0.045 (1.14) __
MIN

__

_

MILLIMETERS

SYMBOL

£
==,
--§it

'-1

01
0

N20.35 (JEDEC M8-018AA ISSUE A)

I I 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

0.004(0.10) C

11 r~ L

\,0

I

Q

I~ MIN
0.025 (0.64)

VIEW "A" TYP.

NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
2. Dimensions and tolerancing per ANSI Yt4.5M-19B2.
3. Dimensions 01 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side.
4. To be measured at seating plane ~ contact pOint.
5. Centerline to be determined where center leads exit plastic body.
6. "N" is the number of terminal positions.

11-22

NOTES

-

E

0.3B5

0.395

9.7B

10.03

-

E1

0.350

0.356

B.B9

9.04

3

E2

0.141

0.169

3.59

4.29

4,5

N

20

20

6
Rev. 1 3/95

Plastic Packages for Integrated Circuits
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)

h"""-""

~
1-- \ --II-

r::::""T":"":":":"-::"":-::-r-::-1
~::..r---'-""":'-'-..J

o 050 (1

27) TP

INCHES

I I

t

N44.65 (JEDEC MS-018AC ISSUE A)
44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
MIN

MAX

MIN

MAX

A

0.165

0.180

4.20

4.57

A1

0.090

0.120

2.29

3.04

0

0.685

0.695

17.40

17.65

L,1 C IA -B I DI

!T;I-b1~11
_(b)
SECTION A-A

rh
'~!

-

eA

!$lcccCf!t1 C IA - B(!!)I D(!!)I

c--l_

!$laaa ~CIA- Bt!!)IDt!!)

NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's Identification shall not be used
as a pin one Identification mark.
2. The maximum limits of lead dimensions band c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

MILLIMETERS

MAX

MIN

MIN

MAX

0.225

A

NOTES

5.72

-

b

0.014

0.026

0.36

0.66

2
3

b1

0.014

0.023

0.36

0.58

b2

0.045

0.065

1.14

1.65

-

b3

0.023

0.045

0.58

1.14

4

c

0.008

0.018

0.20

0.46

2

c1

0.008

0.015

0.20

0.38

3

-

32.77

-

15.49

-

D

-

1.290

E

0.500

0.610

12.70

e

0.100BSC

2.54BSC

eA

0.600BSC

15.24BSC

eA/2

0.300 BSC

7.62 BSC

L

0.120

0.200

3.05

5.08

-

a

0.015

0.075

0.38

1.91

5

51

0.005

52

0.005

-

7

II

900

1050

aaa

-

0.015

-

0.010

3. Dimensions bl and cl apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

bbb

4. Comer leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

M

ccc

N

0.030

0.13

6

0.13

1050

900

0.38

-

0.76

0.0015
24

-

0.25
0.038
24

2
8
Rev. 04/94

a

5. Dimension shall be measured from the seating plane to the
base plane.
6. Measure dimension Sl at all four corners.
7. Measure dimension 52 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. ContrOlling dimension: INCH.

11-27

Hermetic Packages for Integrated Circuits
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F8.3A MIL-5TD-1835 GDIP1-T8 (0-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LiNE FRIT SEAL PACKAGE

c~
BASE

~(cl
N

.PI_bl_1
METAL

M

INCHES
MIN

MAX

A

-

0.200

b

0.014

0.026

bl

0.014

b2

0.045

b3
c
cl

0.008

+

M ___

__ (bl_

SECTION A-A
BASE

S~~~::\.J~I ffi1
I
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PLANE

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MILLIMETERS

SYMBOL

~

\\

eA

~-c __ __

~aaaeic A-B(!)lo(!)

NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions band c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.

11-28

0.36

0.58

3

0.065

1.14

1.65

0.023

0.045

0.58

1.14

4

0.008

0.Q18

0.20

0.46

2

0.220

0.015

0.20

0.38

3

0.405

-

10.29

5

0.310

5.59

7.87

5

0.300 BSC

7.62 BSC

0.150 BSC

3.81 BSC

L

0.125

0.200

3.18

5.08

Q

0.015

0.060

0.38

1.52

Sl

0.005

-

0.13

Cl

90°

105°

90°

0.015

-

aaa

N

8. N is the maximum number of terminal pOSitions.

0.023

eA

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

7. Measure dimension Sl at all four corners.

2

eAl2

cce

6. Dimension Q shall be measured from the seating plane to the
base plane.

-

0.66

2.54BSC

bbb

M

NOTES

0.36

0.100 BSC

e

3. Dimensions bl and cl apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

5. This dimension allows for off-center lid, meniscus, and glass
overrun.

MAX
5.08

D
E

MIN

-

105°
0.38

0.030
0.010

0.76

-

-

0.25

0.0015
8

6
7

0.038
8

2,3
8
Rev. 04/94

Hermetic Packages for Integrated Circuits
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F14.3 MIL-STD-1835 GDIP1-T14 (0-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

,j

BASE
METAL

H(e)
N

INCHES
SYMBOL

MIN

MAX

A

-

0.200

0.014

0.026

0.36

0.66

2

0.014

0.023

0.36

0.58

3

b2

0.045

0.065

1.14

1.65

b3

0.023

0.045

0.58

1.14

4

c

0.008

0.018

0.20

0.46

2

c1

0.008

0.Q15

0.20

D

-

0.785

E

0.220

0.310

eA

2. The maximum limits of lead dimensions band c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Comer leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension SI at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.

11-29

NOTES

b

eA/2

1. Index area: A notch or a pin one identification mark shall be locat·
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identification shall not be used
as a pin one identification mark.

MAX
5.08

bl

e

NOTES:

MILLIMETERS
MIN

esc
0.300 esc
0.150 esc
0.100

5.59

0.38

3

19,94

5

7.87

5

esc
7.62 esc
3.81 esc
2.54

-

L

0.125

0.200

3.18

5.08

Q

0.015

0.060

0.38

1.52

6

SI

0.005

0.13

-

7

0;

90 0

1050

1050

-

aaa

-

0.015

0.38

bbb

0.030

0.76

ccc

0.010

0.25

0.0015

M
N

14

0.038
14

2,3

B
Rev. 0 4/94

Hermetic Packages for Integrated Circuits
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

$

el,

:~:L ~(e)

+

M

-B-

S1_
b2 __

0

I I

MAX

A

-

0.200

M ___

A

--II...... ! [!]-I

c:::t:::J
A':~
~

I

t

ttL

UI

I~

+

b ..... ,

J

eAJ2

I-Tc~
......

MILLIMETERS

MIN

SECTION A-A

P~~~ N ' "-'-.fBi
---o!

tI

INCHES
SYMBOL

_(b)_

I+Ibbb(!)1 C IA -B(!)I o(!)1

SEATING,"]
PLANE

F16_3 MIL-STD-1835 GDIP1-T16 (0-2, CONFIGURATION A)
+ 16
LEAD CERAMIC DUAL-IN-LiNE FRIT SEAL PACKAGE

P •j
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A-

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See Us on the Net
http://www.semi.harris.com/

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Harris AnswerFAX Data Book Request Form - Document #199
Data Books Available Now

../

PUB •
NUMBER
7004

DATA BOOKIDESCRIPOON
Complete Set of Commercial Harris Data Books

7005

Complete Set of Commercial and Military Harris Data Books

DB223B

POWER MOSFETa (1994: 1,328pp) This data book contains detailed technical information Including standard power MOSFETs
.(the popular RF·series types, the IRF·series of industry replacement types, and JEDEC types), MegaFETs, logic-level power
MOSFETs (L2FETs), ruggedized power MOSFETs, advanced discrete, high-reliability and rediation-hardened power MOSFETs.

DB316

POWER MOSFET DATABOOK SUPPLEMENT (1996: 380pp) This data book contains the data sheets of recently introduced
products and also updates some of the datasheets in the Power MOSFET Data Book DB223B. These datasheets contain the
detailed specHication for these products.

DB235B

RADIATION HARDENED (1993: 2,232pp) The Harris radiation-hardened products include the CD4000, HCSlHCTS and ACs/
ACTS logic families, SRAMs, PROMs, op amps, analog multiplexers, the 8OC85/80C86 microprocessor family, analog switches,
gate arrays, standard cells and custom devices.

DB260.2

CDP6805 CMOS MICROCONTROLLEAS & PERIPHERALS (1995: 436pp) This data book represents the full line of Harris
Semiconductor CDP6805 products for commercial applications and supersedes previously published CDP6805 data books
under the Harris, GE, RCA or Intersil names.

DB301B

DATA ACQUISITION (1994: 1, 104pp) Product specificatiOns on AID converters (display, integrating, successive approximation,
flash); D/A converters, switches, multiplexers, and other products.

DB302B

DIGITAL SIGNAL PROCESSING (1994: 528pp) Product specifications on one-dimensional and two-dimensional filters, signal
synthesizers, multipliers, special function devices (such as address sequencers, binary correlators, histogrammer).

DB303

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DB304.1

INTELLIGENT POWER ICa (1994: 946pp) This data book includes a complete set of data sheets for product specifications,
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DB309.1

MCTnGBTlDlODES (1995: 706pp) This MCTIIGBTlDiodes Data book represents the full line of these products made by Harris
Semiconductor Discrete Power Products for commercial applications.

DB314

SIGNAL PROCESSING NEW RELEASES (1995: 690pp) This data book represents the newest products made by Harris
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commercial applications.

DB315

CROSS-REFERENCE GUIDE (1996: 554pp) This guide contains the listing of semiconductor products that are second-sourced
by Harris Semiconductor.

DB317

COMMUNICATIONS HANDBOOK (1997: approx. 7oopp) This handbook contains technical information including data sheets
and application notes for a variety of Harris Integrated Circuits targeted for the communications industry. These products include
the PRISM 2.4GHz DSSS Wireless Transceiver Chip Set, the new HC5517 Ringing SLiC as well as Standard Linear, Data
Acquisition, DSP and Power products.

DB450.4

TRANSIENT VOLTAGE SUPPRESSION DEVICES (1995: 400pp) Product specifications of Harris varistors and surgectors.
Also, general informational chapters such as: "Voltage Transients - An Overview," "Transient Suppression - Devices and
PrinCiples," "Suppression - Automotive Transients."

DB5oo.3

LINEAR ICa (1996197: 1446pp) Harris offers an extensive line of Linear components including: High Speed and General Purpose
Op Amps, Comparators, Sample/Hold Amps, Video Crosspoint Switches, Special Analog Circuits and Transistor Arrays.

Analog
Military

ANALOG MILITARY (1989: 1,264pp) This data book describes Harris' military line of Linear, Data Acquisition, and
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DB312

ANALOG MILITARY DATA BOOK SUPPLEMENT (1994: 432pp) The 1994 Military Data Book Supplement, combined with the
1989 Analog Military Product Data Book, contain detailed technical information on the extensive line of Harris Semiconductor
Linear and Data Acquisition products for Military (MIL-STD-883, DESC SMD and JAN) applications and supersedes all
previously published Linear and Data Acquisition Military data books. For applications requiring Radiation Hardened products,
please refer to the 1993 Harris Radiation Hardened Product Data Book (document #DB235B)

PSG201.23 PRODUCT SELECTION GUIDE (1996: 834pp) Key product information on all Harris Semiconductor devices. Sectioned (Linear,
Data Acquisition, Digital Signal Processing, Telecom, Intelligent Power, Discrete Power, Digital Microprocessors and Hi-Rell
Military and Rad Hard) for easy use and includes cross references and alphanumeric part number index.
SG103

CMOS LOGIC SELECTION GUIDE (1994: 288pp) This product selection guide contains technical information on Harris
Semiconductor High Speed 54174 CMOS Logic Integrated Circuits for commercial, industrial and military applications. It covers
Harris' High Speed CMOS Logic HClHCT Series, ACIACT Series, BiCMOS Interface I.Qgic FCT Series and CMOS Logic
CD4000B Series.

BR-Q57.3

Ana_rFAX CATALOG (Fall 1996: 112pp) A Complete AnswerFAX Catalog listing.

NAME: ___________________________

COMPAN~

_____________________________________

PHONE: _________________________

ADDRESS: _____________________ MAIL STOP:....._________

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12-6

ZIP:..,:_____________
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November11,1996

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

27007

BR007

7049

Complete Listing of Harris Sales
Offices, Representatives and
Authorized Distributors World
Wide (8 pages)
Harris Semiconductor Part
Number Nomenclature Guide
(16 pages)

7031

27026

DESCRIPTION

BR026

PCS03.1

Linear and Data Acquisition
Product Cross Reference
(26 pages)
PRISMTM Development Kits
(2 pages)

LINEAR ARTICLE REPRINTS
7030

7036

RFDesign
Cover Story 10/95

Four-Chip Set Supports HighSpeed DSSS PCMCIA
Applications (5 pages)

DB500,
Section 11

CA124, CA224,
CA324, LM324',
LM2902'

CA139, CA239, Quad Voltage Comparators for
CA339, LM339, Industrial, Commercial and
LM2901, LM3302 Military Applications (5 pages)

1019

CA1SS, CA158A,
CA258, CA258A,
CA358, CA358A,
CA2904, LM358,
LM2904

Dual, 1MHz, Operational
Amplifiers for Commercial
Industrial, and Military
Applications (7 pages)
FN1019.3

CA555, LM555

Timers for Timing Delays and
Oscillator Applications in
Commercial, Industrial and
Military Equipment (6 pages)

531

981
338

339

CA3020

Multipurpose Wide-Band Power
Amps Military, Industrial and
Commercial Equipment at
Frequency Up to 8MHz
(9 pages)

382

CA3028, CA3053

DifferentiaVCascode Amplifiers
for Commercial and Industrial
Equipment for DC to 120MHz
(12 pages)

343

CA3039

CA741 , CA1458, High Gain Single and Dual
CA1558, LM741', Operational Amplifiers for
LM14SS', LM1558' Military, Industrial and
Commercial Applications
(6 pages)

CA3018

611

CA3049, CA3102

Dual High Frequency
Differential Amplifiers for Low
Power Applications Up to
SOOMHz (9 pages)

388

CA3054

Transistor Array - Dual
Independent Differential Amp
for Low Power Applications for
DC to 120MHz (8 pages)

CA3059, CA3079 Zero-Voltage Switches for 5O60Hz and 400Hz Thyristor
Control Applications (12 pages)

537

CA3060

Operational Transconductance
Amplifier Arrays (12 pages)

535

CA3078

Micropower Operational
Amplifier (9 pages)

475

CA3080

Operational Transconductance
Amplifier (OTA) (13 pages)

480

CA3081, CA3082

General Purpose High Current
N-P-N Transistor Arrays
(3 pages)

481

CA3083

General Purpose High Current
NPN Transistor Array (4 pages)
FN481.3

483

CA3086

General Purpose N-P-N
Transistor Array (5 pages)

561

CA3089

FM IF System (7 pages)

598

CA3094

Programmable Power Switch!
Amplifier for Control and
General Purpose Applications
(15 pages)

CA3096, CA3096A, NPNIPNP Transistor Arrays
(12 pages) FN595.3
CA3096C

896

General Purpose TranSistor
Arrays (6 pages)

*Technical Data on LM Branded Types is Idertical to the Corresponding CA Branded Types
12-7

Diode Array (4 pages)

CA3045, CA3046 General Purpose N-P-N
Transistor Arrays (6 pages)

595

CA1391, CA1394 TV Horizontal Processors
(4 pages)

DESCRIPTION

341

490

Quad Operational Amplifiers for
Commercial, Industrial and
Military Applications (7 pages)

795

834

PART
NUMBER

Linear and Telecom Packaging
Information (19 pages)

LINEAR DATA SHEETS
796

AnswerFAX
DOCUMENT
NUMBER

Wireless Design & System Considerations in
Development
Spread-Spectrum Designs
616195
(3 pages)

LINEAR PACKAGING INFORMATION
7014

AnswerFAX Technical Support
Linear Product Listing

CA3098

Programmable Schmitt Trigger
with Memory, Dual Input
Precision Level Detector
(11 pages) FN896.3

wen

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HARRIS
S EM I CO N D UC TOR

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

625

CA31 00

860

November 11,1996

AnswerFAX Technical Support
Linear Product Listing

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

Wideband Operational Amplifier
(7 pages)

1732

CA3450

Video Line Driver, High Speed
Operational Amplifier (8 pages)

CA3126

TV Chroma Processor
(9 pages)

1923

CA5130

662

CA3127

High Frequency NPN Transistor
Array (6 pages) FN662.3

BiMOS Microprocessor
Operational Amplifier with
MOSFET InpuVCMOS Output
(17 pages)

817

CA3130

BiMOS Operational Amplifier
with MOSFET Input/CMOS
Output (15 pages)

1924

CA5160

BiMOS Microprocessor
Operational Amplifiers with
MOSFET InpuVCMOS Output
(20 pages)

957

CA3140

BiMOS Operational Amplifier
with MOSFET Input/Bipolar
Output (20 pages)

1929

CA5260

906

CA3141

High-Voltage Diode Array For
Commercial, Industrial and
Military Applications (4 pages)
FN906.3

BiMOS Microprocessor
Operational Amplifiers with
MOSFET InpuVCMOS Output
(5 pages)

1925

CA5420

Low Supply Voltage, Low Input
Current BiMOS Operational
Amplifier (7 pages)

1946

CA5470

Quad Microprocessor BiMOS-E
Operational Amplifiers with
MOSFET InpuVBipolar Output
(5 pages)

1686

CD22402

Sync Generator for TV
Applications and Video
Processing Systems (10 pages)

532

DESCRIPTION

CA3146, CA3146A, High-Voltage Transistor Arrays
CA3183, CA3183A (8 pages) FN532.3

976

CA3160

BiMOS Operational Amplifiers
with MOSFET InpuVCMOS
Output (17 pages)

1046

CA3189

FM IF System (7 pages)

1249

CA3193

BiCMOS Precision Operational
Amplifiers (11 pages)

2891

1345

CA3227, CA3246

High-Frequency NPN Transistor
Arrays For Low-Power
Applications at Frequencies Up
to 1.5GHz (5 pages) FN1345.3

3926

HA-2400/883

HA-2406

1480

CA3237

IR Remote-Control Amplifier
(5 pages)

2892

1050

CA3240

Dual BiMOS Operational
Amplifier with MOSFET Input/
Bipolar Output (16 pages)

2856

DESCRIPTION

HA-2400, HA-2404, PRAM Four Channel
HA-2405
Programmable Amplifiers
(6 pages)
PRAM Four Channel
Programmable Operational
Amplifier (11 pages)
Digitally Selectable Four
Channel Operational Amplifier
(6 pages)

HA-2420, HA-2425 Fast Sample and Hold
Amplifiers (9 pages)

1769

CA3256

BiMOS Analog Video Switch
and Amplifier (12 pages)

2490

HA-2444

Selectable, Four Channel Video
Operational Amplifier (3 pages)

1266

CA3260

BiMOS Operational Amplifier
with MOSFET InpuVCMOS
Output (4 pages)

3608

HA-2444/883

Selectable, Four Channel Video
Operational Amplifier (8 pages)

1174

CA3280

Dual Variable Operational
Amplifier (11 pages)

1049

CA3290

BiMOS Dual Voltage
Comparator with MOSFET
Input, Bipolar Output (8 pages)

3734

1320

CA3420

Low Supply Voltage, Low Input
Current BiMOS Operational
Amplifiers (5 pages)

2893

1318

CA3440

2890

3697

Nanopower BiMOS Operational
Amplifier (6 pages)

12-8

HA-2500, HA-2502, Precision High Slew Rate
HA-2505
Operational Amplifiers
(6 pages)
HA-25OO1883,
HA-2502l883

Precision High Slew Rate
Operational Amplifiers
(10 pages)

HA-2510, HA-2512, High Slew Rate Operational
HA-2515
Amplifiers (5 pages)
HA-251 0/883,
HA-25121883

High Slew Rate Operational
Amplifiers (11 pages)

November 11, 1996

AnswerFAX
DOCUMENT
NUMBER
2894

PART
NUMBER

AnswerFAX Technical Support
Linear Product Listing

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

2477

HA-2556

Uncompensated, High Slew
Rate Operational Amplifiers
(11 pages)

3619

HA-2556/883

Uncompensated, High Slew
Rate High Output Current,
Operational Amplifier (7 pages)

2478

HA-2557

Uncompensated, High Slew
Rate High Output Current,
Operational Amplifier
(12 pages)

3638

HA-2557/883

DESCRIPTION

HA-2520, HA-2522, Uncompensated High Slew
HA-2525
Rate Operational Amplifiers
(7 pages)

3735

HA-2520/883,
HA-25221883

2895

HA-2529

3736

HA-2529/883

2896

HA-2539

Very High Slew Rate Wideband
Operational Amplifier (7 pages)

3927

HA-2539/883

Very High Slew Rate Wideband
Operational Amplifier
(11 pages)

3700

2897

HA-2540

Wideband, Fast Settling
Operational Amplifier (8 pages)

2903

2898

HA-2541

Wideband, Fast Settling, Unity
Gain Stable, Operational
Amplifier (8 pages)

3698

HA-2541/883

2899

HA-2542

3928

HA-25421883

2902

3701

Wideband, Fast Settling, Unity
Gain Stable, Operational
Amplifier (11 pages)

2904

Wideband, High Slew Rate,
High Output Current
Operational Amplifier
(10 pages)

DESCRIPTION
Wideband Four Quadrant
Voltage Output Analog Multiplier
(18 pages)
Wideband Four Quadrant
Analog Multiplier (Voltage
Output) (20 pages)
Wideband Four Quadrant
Current Output Analog Multiplier
(13 pages)
Wideband Four Quadrant
Analog Multiplier (Current
Output) (14 pages)

HA-26oo, HA-2602, Wideband, High Impedance
HA-2605
Operational Amplifiers
(8 pages)

HA-2600/883,
HA-2602l883

Wideband, High Impedance
Operational Amplifiers
(11 pages)

HA-2620, HA-2622, Very Wideband,
HA-2625
Uncompensated Operational
Amplifiers (7 pages)

HA-2620/883,
HA-2622/883

Very Wideband, High Input
Impedance Uncompensated
Operational Amplifiers
(11 pages)

HA-2640, HA-2645 High Voltage Operational
Amplifiers (6 pages)

3702

HA-2640/883

High Voltage Operational
Amplifier (11 pages)

2841

HA-2839

Wideband, High Slew Rate,
High Output Current,
Operational Amplifier
(12 pages)

Very Higl:1 Slew Rate Wideband
Operational Amplifier (8 pages)

3593

HA-2839/883

Very High Slew Rate, Wideband
Operational Amplifier
(13 pages)

2900

HA-2544

Video Operational Amplifier
(10 pages)

2842

HA-2840

Very High Slew Rate Wideband
Operational Amplifier (8 pages)

3699

HA-2544/883

Video Operational Amplifier
(13 pages)

3594

HA-2840/883

2861

HA-2546

Wideband Two Quadrant
Analog Multiplier (13 pages)

Very High Slew Rate, Wideband
Operational Amplifier
(13 pages)

2843

.HA-2841

2444

HA-2546/883

Wideband Two Quadrant
Analog Multiplier (19 pages)

Wideband, Fast Settling, Unity
Gain Stable, Video Operational
Amplifier (9 pages)

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2862

HA-2547

Wideband Two Quadrant
Analog Multiplier (8 pages)

2901

HA-2548

Precision, High Slew Rate,
Wideband Operational Amplifier
(10 pages)

2472

HA-2548/883

Precision, High Slew Rate,
Wideband Operational Amplifier
(14 pages)
12-9

3621

HA-2841/883

Wideband, Fast Settling, Unity
Gain Stable, Video Operational
Amplifier (14 pages)

2766

HA-2842

Wideband, High Slew Rate,
High Output Current, Video
Operational Amplifier (9 pages)

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Novemberll,1996

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

3622

HA-2842/883

2844

HA-2850

Low Power, High Slew Rate
Wideband Operational Amplifier
(8 pages)

3595

HA-2850/883

Low Power, High Slew Rate,
Wideband Operational Amplifier
(13 pages)

3680

HA4201

Wideband, 1 x 1 Video
Crosspoint Switch with Tally
Output (7 pages) FN3680.2

4078

HA4244

Wideband, 1 x 1 Video
Crosspoint Switch with
Synchronous Enable (7 pages)
FN4078

DESCRIPTION

HA4314B

Wideband, 4 x 1 Video
Crosspoint Switch (10 pages)
FN3679.3

3956

HA4344B

Wideband, 4 x 1 Video
Crosspoint Switch with
Synchronous Controls
(3 pages) FN3956

3678

HA4404B

Wideband, 4 x 1 Video
Crosspoint Switch with Tally
Outputs (10 pages) FN3678.3

3990

HA4600

Wideband, Video Buffer with
Output Disable (7 pages)
FN3990.1

2922

HA-4741

Quad Operational Amplifier
(6 pages)

3704

HA-4741/883

Quad Operational Amplifier
(11 pages)

2855

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

2845

HA-5020

100MHz Current Feedback
Video Amplifier With Disable
(20 pages) FN2845.6

3541

HA-5020/883

100MHz Current Feedback
Video Amplifier with Disable
(19 pages) FN3541.2

3392

HA5022

Dual 125MHz Video Current
Feedback Amplifierwith Disable
(16 pages) FN3392.3

3729

HA50221883

Dual 125MHz Video Current
Feedback Amplifier with Disable
(22 pages)

3393

HA5023

Dual 125MHz Video Current
Feedback Amplifier (14 pages)
FN3393.4

3730

HA5023/883

Dual 125MHz Video Current
Feedback Amplifier (18 pages)

3550

HA5024

Quad 125MHz Video Current
Feedback Amplifierwith Disable
(16 pages) FN3550.2

3591

HA5025

Quad 125MHz Video Current
Feedback Amplifier (14 pages)
FN3591.2

2924

HA-5033

Video Buffer (10 pages)

HA-5033/883

Video Buffer (12 pages)

Wideband, High Slew Rate,
High Output Current, Video
Operational Amplifier
(14 pages)

3679

AnswerFAX Technical Support
Linear Product Listing

3930
2905

3931

2925

HA-4900, HA-4902, Precision Quad Comparator
(8 pages)
HA-4905

DESCRIPTION

HA-5101, HA-5111 Low Noise, High Performance
Operational Amplifiers
(10 pages)
HA-51 01/883

Low Noise, High Performance
Operational Amplifier
(13 pages)

HA-5102, HA-51 04, Low Noise, High Performance
HA-5112, HA-5114 Operational Amplifiers
(10 pages)

3709

HA-51 02/883

Dual, Low Noise, High
Performance Operational
Amplifier (13 pages)

Monolithic, Wideband, High
Slew Rate, High Output Current
Buffer (8 pages)

3710

HA-51 04/883

Low Noise, High Performance,
Quad Operational Amplifier
(13 pages)

Monolithic, Wideband, High
Slew Rate, High Output Current
Buffer (15 pages)

3932

HA-5111/883

Low Noise, High Performance
Uncompensated Operational
Amplifier (13 pages)

HA-5004

100MHz Current Feedback
Amplifier (9 pages)

3711

HA-5112/883

3706

HA-5004/883

100MHz Current Feedback
Amplifier (13 pages)

Dual, Low Noise, High
Performance Uncompensated
Operational Amplifier
(13 pages)

3654

HA5013

3929

HA-4902/883

2921

HA-5002

3705

HA-5002l883

2923

Precision Quad Comparator
(10 pages)

Triple 125MHz Video Amplifier
(14 pages) FN3654.2
12-10

November11,1996

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

3712

HA-51141883

Quad, Low Noise, High
Performance Uncompensated
Operational Amplifier
(13 pages)

2906

HA-5127

Ultra-Low Noise Precision
Operational Amplifier (9 pages)

3751

HA-5127/883

2907
2926

DESCRIPTION

Ultra Low Noise, Precision
Operational Amplifier
(13 pages)

HA-5130, HA-5135 Precision Operational Amplifiers
(8 pages)
HA-5134

Precision Quad Operational
Amplifier (8 pages) FN2926.2

3713

HA-5134/883

Precision Quad Operational
Amplifier (13 pages)

3731

HA-5135/883

Precision Operational Amplifier
(13 pages)

2908

HA-5137

Ultra-Low Noise Precision
Wideband Operational Amplifier
(8 pages)

3714

HA-5137/883

Ultra Low Noise, Precision
Wideband Operational Amplifier
(13 pages)

2909

HA-5142, HA-5144 DuaVQuad Ultra-Low Power
Operational Amplifiers
(7 pages)

3732

HA-5142/883

Dual, Ultra Low Power
Operational Amplifier
(12 pages)

3934

HA-5144/883

Quad, Ultra-Low Power
Operational Amplifier
(12 pages)

2910

HA-5147

Ultra-Low Noise Precision High
Slew Rate Wideband
Operational Amplifier (8 pages)

3715

HA-5147/883

Ultra Low Noise, Precision, High
Slew Rate Wideband
Operational Amplifier
(13 pages)

2911

2912

2913

HA-5160, HA-5162 Wideband, JFET Input High
Slew Rate, Uncompensated,
Operational Amplifiers
(8 pages) FN2911.2
HA-5170

HA-5177

AnswerFAX Technical Support
Linear Product Listing

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

3733

HA-5177/883

2914

HA-5190, HA-5195 Wideband, Fast Settling
Operational Amplifiers
(8 pages)

2915

HA-5221, HA-5222 Low Noise, Wideband Precision
Operational Amplifier
(11 pages)

3716

HA-5221 1883

Low Noise, Wideband,
Precision Operational Amplifier
(12 pages)

3717

HA-52221883

Dual, Low Noise, Wideband,
Precision Operational Amplifier
(13 pages) FN3717.1

2857

HA-5320

2927

HA-5320/883

2858

HA-5330

Very High Speed Precision
Monolithic Sample and Hold
Amplifier (4 pages)

3935

HA-5330/883

Very High Speed Precision
Monolithic Sample and Hold
Amplifier (9 pages)

2859

HA-5340

High Speed, Low Distortion,
Precision Monolithic Sample
and Hold Amplifier (8 pages)

2452

HA-5340/883

High Speed, Low Distortion,
Precision MonOlithic Sample
and Hold Amplifier (12 pages)

3690

HA5351

Fast Acquisition Sample and
Hold Amplifier (11 pages)
FN3690.4

3727

HA-5351 1883

Fast Acquisition, Low Power
Sample and Hold Amplifier
(1 page)

3389

HA7210, HA72t1

Low Power Crystal Oscillator
(13 pages) FN3389.5

2945

Precision JFET Input
Operational Amplifier (8 pages)
FN2912.2
Ultra-Low Offset Voltage
Operational Amplifier
(10 pages)

12-11

DESCRIPTION
Ultra Low Offset Voltage
Operational Amplifier
(14 pages)

High Speed Precision
Monolithic Sample and Hold
Amplifier (10 pages)
High Speed Precision Sample
and Hold Amplifier (12 pages)

HFA1100, HFA1120 Ultra High-Speed, Current
Feedback Amplifiers (12 pages)

3615

HFA1100/883

3597

HFA1102

850MHz Current Feedback
Amplifier (16 pages)
Ultra High-Speed Current
Feedback Amplifier with
Compensation Pin (5 pages)
FN3597.1

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mHARRIS
W SEMICONDUCTOR
AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

3547

HFAll02Y

3957

November 11, 1996

AnswerFAX TechnicalSupport
Linear Product Listing

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

Ultra High-Speed Current
Feedback Amplifier with
Compensation Pin (4 pages)

3617

HFA1120/883

HFA1103

Video Op Amp with High Speed
Sync Stripper (6 pages)
FN3957.1

3369

HFA1130

3395

HFAll05

High-Speed, Low Power,
Current Feedback Video
Operational Amplifier
(11 pages) FN3395.4

3625

HFAII30/883

3653

HFA1135

3922

HFAll06

High Speed, Low Power, Video
Operational Amplifier with
Compensation Pin (14 pages)
FN3922

High-Speed, Low Power, Video
Operational Amplifier with
Output Limiting (5 pages)
FN3653.1

3725

HFA11351883

High Speed, Low Power Current
Feedback Amplifier with
Programmable Output Limiting
(5 pages)

3955

HFA1145

High-Speed, Low Power,
Current Feedback Video
Operational Amplifier with
Output Disable (13 pages)
FN3955.1

3726

HFA1145/883

High Speed, Low Power,
Current Feedback Video
Operational Amplifier with
Output Disable (5 pages)

3605

HFA1205

Dual High-Speed, Low Power,
Video Operational Amplifier
(7 pages) FN3605.3

3607

HFA1212

Dual 350MHz, Low Power
Closed Loop Buffer Amplifier
(12 pages) FN3607.3

4019

DESCRIPTION

HFA1109, HFA1149 High-Speed, Low Power,
Current Feedback Operational
Amplifiers (1 page) FN4019

2944

HFAlll0

750MHz Low Distortion Unity
Gain, Closed Loop Buffer
(9 pages)

3620

HFAlll0/883

750MHz, Low Distortion Unity
Gain, Closed Loop Buffer
(15 pages)

DESCRIPTION
850MHz Current
Feedback Amplifier with Offset
Adjust (17 pages)
Output Clamping, Ultra HighSpeed Current Feedback
Amplifier (11 pages)
Output Clamping, 850MHz
Current Feedback Amplifier
(19 pages)

2992

HFA1112

3610

HFA1112/883

1342

HFA1113

Output Limiting, Ultra High
Speed, Programmable Gain,
Buffer Amplifier (16 pages)
FNI342.2

3742

HFA12121883

3618

HFA11131883

Output Limiting, Ultra High
Speed Programmable Gain,
Buffer Amplifier (22 pages)

Dual, High Speed, Low Power,
Video Closed Loop Buffer
(5 pages)

3682

HFA1245

Ultra High Speed
Programmable Gain Buffer
Amplifier (5 pages) FN3151.2

Dual, High-Speed, Low Power,
Video Operational Amplifier with
Disable (6 pages) FN3682.1

3743

HFA1245/883

High-Speed, Low Power, Output
Limiting, Closed Loop Buffer
Amplifier (7 pages) FN3606.2

Dual, High Speed, Low Power,
Video Operational Amplifier with
Output Disable (6 pages)

3604

HFA1405

High Speed, Low Power, Output
Limiting Closed Loop Buffer
Amplifier (5 pages)

Quad, 560MHz, Low Power,
Video Operational Amplifier
(15 pages) FN3604.3

4152

HFA1412

Quad, 350MHz, Low Power,
Programmable Gain Buffer
Amplifier (15 pages) FN4152.1

3744

HFA14121883

Quad, High Speed, Low Power,
Video Closed Loop Buffer
(4 pages)

3151

3606

3724

4020

HFA1114

HFA1115

HFA11151883

Ultra High-Speed
Programmable Gain Buffer
Amplifier (12 pages) FN2992.3
Ultra High Speed
Programmable Gain Buffer
Amplifier (18 pages)

HFA 1118, HFA1119 Programmable Gain Video
Buffers with Output Limiting and
Output Disable.(1 page)
FN4020

12-12

November 11,1996

AnswerFAX
DOCUMENT
NUMBER
3076

PART
NUMBER

HFA3046, HFA3096, Ultra High Frequency Transistor
HFA3127, HFA3128 Arrays (9 pages) FN3076.8
HFA3101

Gilbert Cell UHF Transistor
Array (12 pages) FN3663.3

3635

HFA3102

Dual Long-Tailed Pair
Transistor Array (6 pages)
FN3635.2

3967

AnswerFAX
DOCUMENT
NUMBER

DESCRIPTION

3663

HFA3127/883

Ultra High Frequency Transistor
Array (7 pages)

4131

HFA3424

2.4GHz - 2.5GHz Low Noise
Amplifier (5 pages) FN4131.1

4062

HFA3524

2.5GHzl600MHz Dual
Frequency Synthesizer
(16 pages) FN4062.3

AnswerFAX Technical Support
Linear Product Listing

2867

PART
NUMBER

DESCRIPTION

ICM7555, ICM7556 General Purpose Timers
(8 pages)

4063

PRISMTM 2.4GHz
ChipSet

Direct Sequence Spread
Spectrum Wireless Transceiver
Chip Set (2 pages) FN4063.3

4238

PRISMTM
Full Duplex Radio
Front End

For Voice and Data (1 page)
FN4238

LINEAR APPLICATION NOTES
9515

(General Op Amps) Operational Amplifier Stability:
AN515
Input Capacitance
Considerations (2 pages)

9519

(General Op Amps) Operational Amplifier Noise
Prediction (4 pages)
AN519

9551

(General Op Amps) Recommended Test
AN551
Procedures for Operational
Amplifiers (6 pages)

3655

HFA3600

Low-Noise AmplifierlMixer
(16 pages) FN3655.2

4066

HFA3624

2.4GHz Up/Down Converter
(19 pages) FN4066.5

9556

4067

HFA3724

400MHz Quadrature IF
Modulator/Demodulator
(23 pages) FN4067.3

(General Op Amps) Thermal Safe-Operating-Areas
AN556
for High Current Op Amps
(5 pages)

95290

4132

HFA3925

2.4GHz - 2.5GHz 250mW
Power Amplifier (8 pages)
FN4132.1

(General Op Amps) Integrated Circuit Operational
AN5290
Amplifiers (20 pages)

97304

(General Op Amps) SCRs As Transient-Protection
AN7304
Structure in Integrated Circuits
(3 pages) AN7304

98743

(General Logic), Micropower Crystal-Controlled
CD4007B, CD4060 Oscillator Design Using CMOS
AN8743
Inverters (8 pages)

99415

(General Op Amps) Feedback, Op Amps and
AN9415
Compensation (12 pages)
AN9415.2

99415

(General Op Amps) Feedback, Op Amps and
AN9415
Compensation (12 pages)

99420

(General Op Amps) Current Feedback Amplifier
AN9420
Theory and Applications
(7 pages) AN9420.1

99510

(General Op Amps) Basic Analog for Digital
AN951 0
Designers (6 pages) AN9510

99523

(General Op Amps) Evaluation Programs for SPICE
Op Amp Models (10 pages)
AN9523
AN9523

2943

HFA5250

Ultra High Speed, Monolithic Pin
Driver (5 pages)

3689

HFA5251

Ultra High-Speed Monolithic Pin
Driver (10 pages) FN3689.2

4003

HFA5253

Ultra High-Speed Monolithic Pin
Driver (19 pages) FN4oo3.1

2919

ICL7611,ICL7612 ICL76XX Series Low Power
CMOS Operational Amplifiers
(12 pages)

3403

ICL7621,ICL7641, ICL76XX Series Low Power
ICL7642
CMOS Operational Amplifiers
(12 pages)

2920

ICL7650S

2863

ICL8013

2864

2865
2866

ICL8038

Super Chopper-Stabilized
Operational Amplifier
(12 pages)
Four Quadrant Analog Multiplier
(8 pages)
Precision Waveform Generator/
Voltage Controlled Oscillator
(10 pages)

96182

ICL8048, ICL8049 Log/Antilog Amplifiers
(10 pages)
ICM7242

96915

Long Range Fixed Timer
(6 pages)
12-13

CA1524
AN6915

Application of the CA 1524
Series Pulse-Width Modulator
ICs (18 pages)

CA3058, CA3059, Features and Applications of
CA3079
Integrated Circuit Zero-Voltage
AN6182.
Switches (CA3059 and
CA3079) (31 pages)

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November 11,1996

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

AnswerFAX Technical Support
Linear Product Listing

AnswerFAX
DOCUMENT
NUMBER

DESCRIPTION

96048

CA3094
AN6048

Some Applications of a
Programmable Power Switch!
Amplifier (13 pages)

662520

96077

CA3094,OTA
AN6077

An IC Operational-Transconductance-Amplifier (OTA) With
Power Capability (12 pages)

662539

96459

CA3130
AN6459

Why Use the CMOS Operational
Amplifiers and How to Use it
(4 pages)

9541

96386

CA3130
AN6386

Understanding and Using the
CA3130, CA3130A and
CA3130B BiMOS Operation
Amplifiers (5 pages)

97326

CA3228
AN7326

Applications of the CA3228
Speed Control System
(16 pages)

96669

CA3240
AN6669

FET-Bipolar Monolithic Op
Amps Mate Directly to Sensitive
Sources (3 pages)

CA3280
AN6818

Dual Variable Op-Amp IC, the
CA3280, Simplifies Complex
Analog Designs (5 pages)
AN6818

98707

CA3450
AN8707

98811

PART
NUMBER

DESCRIPTION

.HA·2520, HA·2522 HA-2520/22 Spice Operational
MM2520
Amplifier Macro-Model
(4 pages)
HA·2539
MM2539

HA-2539 Spice Operational
Amplifier Macro-Model
(4 pages)

HA·2539, HA·2540 Using HA-2539 or HA-2540
AN541
Very High Slew Rate, Wideband
Operational Amplifier (4 pages)

662540

HA·2540
MM2540

HA-2540 Spice Operational
Amplifier Macro-Model
(4 pages)

662541

HA·2541
MM2541

HA-2541 Spice Operational
Amplifier Macro-Model
(5 pages)

9550

HA·2541
AN550

Using the HA-2541(6 pages)

662542

HA·2542
MM2542

HA-2542 Spice Operational
Amplifier Macro-Model
(5 pages)

9552

HA·2542
AN552

Using the HA-2542 (5 pages)

The CA3450: A Single-Chip
Video Line Driver and High
Speed Op Amp (14 pages)

662544

HA·2544
MM2544

HA-2544 Spice Operational
Amplifier Macro-Model
(5 pages)

CA5470
AN8811

BiMOS-E Process Enhances
the CA5470 Quad Op Amp
(8 pages)

99313

98742

CD22402
AN8742

Application of the CD22402
Video Sync Generator (4 pages)

662548

98823

CD54HC4046A,
CD54HC7046A,
CD54HCT4046A,
CD54HCT7046A,
CD74HC7046A,
CD74HCT4046A,
CD74HCT7046A
AN8823

CMOS Phase-Locked-Loop
Applications Using the CD54J
74HC/HCT4046A and CD541
74HC/HCT7046A (23 pages)

99515

HA·2556, HA-5177 Multiplier Improves the Dynamic
AN9515
Range of Echo Systems
(HA2556, HA-5177) (2 pages)
AN9515

662600

HA·2400
AN514

The HA-2400 PRAM Four
Channel Operational Amplifier
(7 pages)

HA·2600, HA·2602 HA-2600102 Spice Operational
MM2600
Amplifier Macro-Model
(5 pages)

96818

9514

9517

9509

HA·2420, HA·2425, Applications of Monolithic
Sample and Hold Amplifier
HA-5330
AN517
(5 pages)

662620

HA·2546, HA-5020, Circuit Considerations in
HA·5033, HA·5177, Imaging Applications (8 pages)
HI-5700
AN9313
HA·2548
MM2548

HA·2620
AN509

HA-2548 Spice Operational
Amplifier Macro-Model
(5 pages)

A Simple Comparator Using the
HA-2620 (1 page)

HA·2620, HA·2622 HA-2620122 Spice Operational
MM2620
Amplifier Macro-Model
(5 pages)

662500

HA·2500, HA·2502 HA2500/02 Spice Operational
MM2500
Amplifier Macro-Model
(5 pages) MM2500.1

9546

HA·2625
AN546

A Method of Calculating HA2625 Gain Bandwidth Product
vs. Temperature (4 pages)

662510

HA·2510, HA·2512 HA-2510/12 Spice Operational
MM2510
Amplifier Macro-Model
(4 pages)

662839

HA·2639
MM2839

HA-2839 Spice Operational
Amplifier Macro-Model
(4 pages)

12·14

November 11,1996

AnswerFAX
DOCUMENT
NUMBER

PART
NUMBER

AnswerFAX Technical Support
Linear Product Listing

AnswerFAX
DOCUMENT
NUMBER

DESCRIPTION

PART
NUMBER

DESCRIPTION

662840

HA-2840
MM2840

HA-2840 Spice Operational
Amplifier Macro-Model
(4 pages)

662841

HA-2841
MM2841

HA-2841 Spice Operational
Amplifier Macro-Model
(4 pages)

99516

HA-2841
AN9516

Adjustable Bandpass or
Bandreject Filter (HA-2841)
(2 pages) AN9516.1

662842

HA-2842
MM2842

HA-2842 Spice Operational
Amplifier Macro-Model
(4 pages)

665102

HA-5102
MM5102

HA-5102 Spice Operational
Amplifier Macro-Model
(5 pages)

662850

HA-2850
MM2850

HA-2850 Spice Operational
Amplifier Macro-Model
(4 pages)

665104

HA-5104
MM5104

HA-5104 Spice Operational
Amplifier Macro-Model
(5 pages)

665002

HA-5002
MM5002

HA-5002 Spice Buffer Amplifier
Macro-Model (4 pages)

665112

HA-5112
MM5112

665004

HA-5004
MM5004

HA-5004 Spice Current
Feedback Amplifier MacroModel (4 pages)

HA-5112 Spice Operational
Amplifier Macro-Model
(5 pages)

99536

HA-5112
AN9536

665013

HAS013
MM5013

HA5013 SPICE Macromodel
(CFA) (8 pages) MM5013.1

PSPICE Performs Op Amp
Open Loop Stability Analysis
(3 pages) AN9536

665114

99305

HA-5020
AN9305

HA-5020 Operational Amplifier
Feedback Resistor Selection
(2 pages)

HA-5114
MM5114

HA-5114 Spice Operational
Amplifier Macro-Model
(5 pages)

665127

665020

HA-5020
MM5020

HA-5020 SPICE Macromodel
(CFA) (7 pages) MM5020

HA-5127
MM5127

HA-5127 Spice Operational
Amplifier Macro-Model
(4 pages)

665022

HAS022
MM5022

HA5022 SPICE Macromodel
(CFA) (7 pages) MM5022

99503

HAS022
AN9503

Low Output Impedance MUX
(1 pages)

665023

HA5023
MM5023

HA5023 SPICE Macromodel
(CFA) (8 pages) MM5023

99508

HAS024
AN9508

Video Multiplexer Delivers
Lower Signal Degradation
(1 pages)

99637

665024

HA-5033
MM5033

HA-5033 Spice Buffer Amplifier
Macro-Model (4 pages)

665101

HA-5101
MM51 01

HA-5101 Spice Operational.
Amplifier Macro-Model
(5 pages)

9554

9553

HAS024, HFA3102 Simple Phase Meter Operates
AN9637
to 10MHz (2 pages) AN9637
HAS024
MM5024

665033

HA-5137
MM5137

HA-5137 Spice Operational
Amplifier Macro-Model
(4 pages)

665147

HA-5147
MM5147

HA-5147 Spice Operational
Amplifier Macro-Model
(4 pages)

9544

HA-514X
AN544

Micropower Op Amp Family
(6 pages)

9543

HAS02S
AN9502

Oscillator Produces Quadrature
Waves (2 pages)

665025

HAS02S
MM5025

HA5025 SPICE Macromodel
(CFA) (8 pages) MM5025.1

9548

HA-5033
AN548

A Designers Guide for the
HA-5033 Video Buffer
(12 pages)

9540

665190

9525

12-15

HA-5127, HA-5137, HA-5147/37127, Ultra Low Noise
Amplifiers (8 pages)
HA-5147
AN553

665137

HA5024 SPICE Macromodel
(CFA) (7 pages) MM5024.1

99502

HA-5101, HA-Sl02, Low Noise Family HA-5101/021
HA-Sl04, HA-5111, 04111/12114 (7 pages)
HA-S112, HA-SI14
AN554

HA-5160, HA-5170 New High Speed Switch Offers
AN543
Sub-50ns Switching TImes
(7 pages)
HA-5170
AN540

HA-5170 Precision Low Noise
JFET Input Operation Amplifier
(4 pages)

HA-5190
MM5190

HA-5190 Spice Operational
Amplifier Macro-Model
(4 pages)

HA-5190, HA-S1aS HA-5190/5195 Fast Settling
Operational Amplifier (4 pages)
AN525

wff
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m.HARR.ls
W

November 11,1996

SEM.ICONDUCTOR

AnswerFAX
DOCUMENT
NUMBER
9526

PART
NUMBER

AnswerFAX Technical Support
Linear Product Listing

AnswerFAX
DOCUMENT
NUMBER

DESCRIPTION

HA-5190, HA-5195 Video Applications for the
HA-5190/5195 (5 pages)
AN526

PART
NUMBER

99314

HFA5250
AN9314

DESCRIPTION
Harris UHF Pin Drivers
(4 pages)

9538

HA-5320
AN538

Monolithic SamplelHold
Combines Speed and Precision
(6 pages)

9053

ICL7650
AN053

The ICL7650 A New Era in
Glitch-Free Chopper Stabilized
Amplifiers (19 pages)

99334

HA721 0
AN9334

Improving Start-Up Time at
32kHz for the HA7210 Low
Power Crystal Oscillator
(2 pages)

9040

ICL8013
AN040

USing the ICL8013 Four
Quadrant Analog Multiplier
(6 pages)

9013

99317

HA721 0
AN9317

Micropower Clock Oscillator and
Op Amps Provide System
Control for Battery Operated
Circuits (2 pages)

ICL8038
AN013

Everything You Always Wanted
to Know About the ICL8038
(4 pages)

99202

9007

ICL8048, ICL8049 Using the 804818049 Log!
AN007
Antilog Amplifier (6 pages)

HFA1100, HFA1130 Using the HFA1100, HFA1130
Evaluation Fixture (4 pages)
AN9202

99614

PRISMTM Chip Set Low Data Rate Applications
(3 pages) AN9614
AN9614
PRISMTM Chip Set Using the PRISMTM HFA3724
AN9622
Evaluation Board (16 pages)
AN9622

99513

HFA1103
AN9513

Component Video Sync
Formats (HFA1103) (3 pages)
AN9513

99622

99514

HFA1103
AN9514

Video Amplifier with Sync
Stripper and DC Restore
(HFA1103) (2 pages) AN9514

99633

PRISM Chip Set
AN9633

Processing Gain for Direct
Sequence Spread Spectrum
Communication Systems and
PRISMT" (4 pages) AN9633

99639

PRISM Chip Set
AN9639

Harris PRISM Wireless LAN
Network Connectivity and Utility
SW (non IEEE802.11) For the
WLAN Evaluation Kit (3 pages)
AN9639

99507

99524

99315

663046

99528

99641

HFA1112, HFA1114 Video Cable Drivers Save Board
Space, Increase Bandwidth
AN9507
(2 pages)
HFA1212
AN9524

HFA1212 Dual Video Buffer
Forms Differential Line Driverl
Receiver (1 page) AN9524

HFA3046, HFA3096, RF Amplifier Design USing
HFA3127, HFA3128 HFA3046/3096/3127/3128
Transistor Arrays (4 pages)
AN9315

LINEAR TECHBRIEFS
82334

HFA3046, HFA3096, HFA3046/3096/3127/3128
HFA3127~ HFA3128 Transistor Array Spice Models
(4 pages)
MM3046
HFA3101
AN9528

82337

900MHz Down Converter
Consumes Little Power
(HFA3101) (1 page) AN9528

HFA3102, CA5160, High-Frequency VGA Has
HI5731
Digital Control (2 pages)
AN9641
AN9641

99627

HFA3424
AN9627

Using the HFA3424 Evaluation
Board (2 pagers) AN9627

99630

HFA3524EVAL
PRISM Chip Set
AN9630

Using The HFA3524 Evaluation
Board (13 pages) AN9630

99618

HFA3624EVAL,
PRISM Chip Set
AN9618.

Using the PRISMTM HFA3624
Evaluation Board (12 pages)
AN9618.2

99638

HFA3925EVAL,
PRISM Chip Set
AN9638

Using The HFA3925 Evaluation
Board (5 pages) AN9638

12-16

(General Linear,
Telecom)
TB334

Guidelines for Soldering Surface
Mount Components to PC
Boards (2 pages) TB334

PRISMTM Chip Set A Brief Tutorial on Spread
TB337
Spectrum and Packet Radio
(3 pages) TB337.1

13
SALES OFFICES
North American Sales Offices. Representatives and Authorized Distributors
2480 W. Ruthrauff, Suite #140
Tucson, AZ 65705
TEL: (520) 292-0222
FAX: 520 2921008

ALABAMA
Harris Semiconductor
600 Boulevard South
Sutte 103
Huntsville, AL 35602
TEL: (205) 663-2791
FAX: 205 663 2661

Alliance Electronics, Inc.
Scottsdale
TEL: (602) 483-9400

Giestlng & Associates
Sutte 15
4635 University Square
Huntsville, AL 35616
TEL: (205) 630-4554
FAX: 205 630 4699

Allied Electronics
Tempe
TEL: (602) 831-2002

Allied Electronics
Huntsville
TEL: (205) 721-3500

ArrowlSchweber
Tempe
TEL: (602) 431-0030

Mobile
TEL: (334) 476-1675

Hamilton Hallmark
Phoenix
TEL: (602) 437-1200
Wyle Electronics
Phoenix
TEL: (602) 804-7000

Hamilton Hallmark
Huntsville
TEL: (205) 637-8700

Huntsville
TEL: (205) 637-9091
Mobile
TEL: (205) 471-6500
Wyle Electronics
Huntsville
TEL: (205) 630-1119
Zeus, An Arrow Company
Huntsville
TEL: (407) 333-3055
TEL: (800) 52-HI-REL

10495 Bandley Avenue
Cupertino, CA 95014-1972
TEL: (408) 342-1220
FAX: 408 342 1221
Mesa Components, Inc.
5520 Ruffin Road
SuRe 208
San Diego, CA 92123
TEL: (619) 278-8021
FAX: (619) 576-0964

Newark Electronics
Tempe
TEL: (602) 966-6340

ArrowlSchweber
Huntsville
TEL: (205) 637-6955

Newark Electronics
Birmingham
TEL: (205) 979-7003

Ewing Foley, Inc.
165 Linden Avenue
Auburn, CA 95603
TEL: (916) 885-6591
FAX: 9168856594

Vision Technical Sales, Inc.
• 26010 Mureau Road
SuRe 140
Calabasas, CA 91302
TEL: (818) 878-7955
FAX: 818 878 7965
16257 Laguna Canyon Road
SuRe 150
Irvine, CA 92618
TEL: (714) 450-9050
FAX: (714) 450-9061

Zeus, An Arrow Company
Tempe
TEL: (408) 629-4789
TEL: (800) 52-HI-REL

Allied Electronics
Irvine
TEL: (714) 727-3010

ARKANSAS
Newark Electronics
Little Rock
TEL: (501) 225-8130

Rancho Cucamonga
TEL: (909) 980-6522

December 5, 1996

Fremont
TEL: (408) 432-7171
Irvine
TEL: (714) 587-0404
San Diego
TEL: (619) 565-4600
San Jose
TEL: (406) 441-9700
Bell Mlcroproducts
Irvine
TEL: 714-470-2900
. San Diego
TEL: 619-597-3010
San Jose
TEL: 408-451-9400
Westlake Village
TEL: 805-496-2606
Hamilton Hallmark
Costa Mesa
TEL: (714) 789-4100
Los Angeles
TEL: (818) 594-0404
Sacramento
TEL: (916) 632-4500
San Diego
TEL: (619) 571-7540
San Jose
TEL: (406) 435-3500

CALIFORNIA
Harris Semiconductor
• 1503 So. Coast Drive
SuRe 320
Costa Mesa, CA 92626
TEL: (714) 433-0600
FAX: 714 433 0682

Rocklin
TEL: (916) 632-3104

Newark Electronics
Garden Grove
TEL: (714) 693-4909

San Diego
TEL: (619) 279-2550

Riverside
TEL: (909) 784-1101

San Jose
TEL: (408) 383-0366

Santa Fe Springs
TEL: (310) 929-9722

Harris Semiconductor
• 3031 Tisch Way
SuRe 800
San Jose, CA 95128
TEL: (408) 985-7322
FAX: 406 985 7455

Torrance
TEL: (310) 540-0039

Sacramento
TEL: (916) 565-1760

Woodland Hills
TEL: (818) 598-0130

Chula Vista
TEL: (619) 691-0141

ArrowlSchweber
Calabasas
TEL: (818) 880-9686

San Diego
TEL: (619) 453-8211

ALASKA
Newark Electronics
Bellevue
TEL: 600-321-6964
ARIZONA
Compass Mktg. & Sales, Inc.
11601 N. Tatum Blvd. #101
Phoenix, AZ 85028
TEL: (602) 996-0635
FAX: 602 996 0586

HARRIS
SEMICONDUCTOR

• Field Application Assistance Available

13·1

(/)

w

o

u::
o

Palo Alto
TEL: (415) 812-6300

II..

Santa Clara
TEL: (408) 988-7300

W
...J

Thousand Oaks
TEL: (805) 499-1460

(/)

<
(/)

North American Sales Offices, Representatives and Authorized Distributors (Continued)
Wyle Electronics
Los Angelea
TEL: (818) 880-9000

Allied Electronics
Cheshire
TEL: (203) 272-7730

Nspean. Ontario
TEL: (613) 596-6980
Pointe Claire. Qusbec
TEL: (514) 697-8149
Winnipeg. Manitoba
TEL: (204) 786-2589

ArrowlSchweber
Wallingford
TEL: (203) 265-7741

San Diego
TEL: (619) 565-9171

Hamilton Hallmark
Misslssagua. Ontario
TEL: (905) 564-6060

Hamilton Hallmark
Dailbury
TEL: (203) 271-5700

Santa Clara
TEL: (408) 727-2500

Montreal
TEL: (514) 335-1000

Zeus. An Arrow Company
San Jose
TEL: (408) 829-4789
TEL: (800) 52-HI-REL

Ottawa
TEL: (613) 226-1700

Newark Electronics
Bloomfield
TEL: (203) 243-1731

irvine
TEL: (714) 581-4622
TEL: (800) 52-HI-REL

Toronto
TEL: (905) 564-6060

Irvine
TEL: (714) 78g.:9953
Sacramento
TEL: (916) 638-5282

Vancouver. B.C.
TEL: (604) 420-4101

308 Palladium Drive
Suite 200 Kanata, Ontario
Canada K2B 1A1
TEL: (613) 599-5626
FAX: 613 599 5707

FLORIDA
Harris Semiconductor
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (407) 729-4984
FAX: 407 729 5321

Newark Electronics
London, Ontario
TEL: (519) 685-4280

CANADA
Blakewood Electronic
Systems. Inc.
#201 - 7382 Winston Street
Burnaby, Be Canada VSA 2G9
TEL: (604) 444-3344
FAX: 604 444 3303
Cee-Jay Microaystems LTD.
5925 Airport Road, Suite 614
Mississauga, Ontario L4V 1W1
TEL: 905-678-3188
FAX: 905-678-3166

leus, An Arrow Compeny
TEL: (914) 937-7400
TEL: (800) 52-HI-REL

Misslssauga, OntariO
TEL: (905) 670-2888
Mount Royal, Quebec
TEL: (514) 738-4488
COLORADO
Compass Mktg. " Sales. Inc.
14142 Denver West Pkwy #200
Golden, CO 80401
TEL: (303) 277-0456
FAX: 303 277-0429

78 Donegani, Suite 200
Pointe Claire, Quebec
Canada H9R 2V4
TEL: (514) 426-0453
FAX: 5144260455
Allied Electronics
Burnaby,BC
TEL: (604) 420-9691

Sun Marketing Group
1956 Dairy Rd.
West Melbourne, FL 32904
TEL: (407) 723-0501
FAX: 407 723 3845
4175 East Bey Drive, Suite 128
Clearwater. FL 34824
TEL: (813) 536-5771
FAX: 813 536 6933

Allied Electronics
Englewood
TEL: (303) 790·1664

600 S. Federal Hwy., Suite 218
Deerfield Beach, FL 33441
TEL: (954) 429-1077
FAX: 954 429 0019

ArrowlSchweber
Englewood
TEL: (303) 799·0258

Allied Electronics
Flo Lauderdale
TEL: (954) 733-3144

Hamilton Hallmark
Denver
TEL: (303) 790-1662

Jacksonville
TEL: (904) 739-5920
Maitland
TEL: (407) 539-0055

Colorado Springs
TEL: (719) 63NI055

Miami Lakes
TEL: (305) 558-2511

Nepean,Ontario
TEL: (613) 228-1964

Newark Electronics
Denver
TEL: (303) 373-4540

SI. Petersburg
TEL: (813) 579-4860

ArrowlSchwebar
Burnaby, British Columbia
TEL: (604) 421-2333

Wyla ElectronicS
Denver
TEL: (303) 457-9953

ArrowlSchweber
Deerfield Beach
TEL: (954) 429-8200

Dorval, Quebac
TEL: (514) 421-7411

Zeus. An Arrow Company
TEL: (408) 829-4789
TEL: (800) 52-HI-REL

Lake Mary
TEL: (954) 333-9300

Nepan, Ontario
TEL: (613) 226-6903
Mlssissagua, Ontario
TEL: (905) 670-7769
Farnell Electronic Services
Burnaby, Br1Iish Columbia
TEL: (604) 608-8950
calgary, Albarta
TEL: (403) 273-2780

CONNECTICUT
Advanced Tech. Sa.... Inc.
Westview Office Park
Bldg. 2, Suite 1C
850 N. Main Street Extension
Wallingford, CT 08492
TEL: (508) 664-0888
FAX: 203 284 8232

Concord, Ontario
TEL: (416) 798-4884

Allianes Electronics. Inc.
Milford
TEL: (203) 874-2001

Bell Microproducta
Altamonte Springs
TEL: 407-682-1199
TEL: 800-542-3083
Deerfield Beach
TEL: 305-429-1001
Hamilton Hallmark
Cie&rwater
TEL: (813) 507-5000
Orlando
TEL: (407) 657:3300

• Field Applicatlcn Assistancs Available

. 13-2

Miami
TEL: (954) 484-5482
Newark Electronics
Orlando
TEL: (407) 896-8350
Flo Lauderdale
TEL: (305) 486-1151
Tampa
TEL: (813) 287-1578
Jacksonviiie
TEL: (904) 399-5041
Mobile
TEL: (205) 471-6500
Wyle Electronics
Fort Lauderdale
TEL: (954) 420-0500
SI. Petersburg
TEL: (813) 576-3004
Zeus. An Arrow Company
Lake Mary
TEL: (407) 333-3055
TEL: (800) 52-HI-REL
GEORGIA
Giestlng " AsSOCiates
• 2434 Hwy. 120. Suite 108
Duluth, GA 30136
TEL: (770) 476-0025
FAX: 7704762405
Allied Electronics
Duluth
TEL: (770) 497-9544
ArrowlSchweber
Duluth
TEL: (770) 497-1300
Hamilton Hallmsrk
Atlanta
TEL: (770) 623-4400
Newark Elect.ronics
Norcross
TEL: (770) 448-1300
Wyle Electronics
Atlanta
TEL: (770) 441-9045
Zeus. An Arrow Company
TEL: (407) 333-3055
TEL: (800) 52-HI-REL
IDAHO
Allied EleCtronlca
Boise
TEL: (208) 331-1414
Newark Electronics
Boise
TEL: (208) 342-4311
ILUNOIS
Harris Semiconductor
• 1101 Perimeter Or., Suite 600
Schaumburg, IL 80173
TEL: (847) 240-3480
FAX: 8476191511

North American Sales Offices, Representatives and Authorized Distributors (Continued)
Oasis Sales
1101 Tonne Road
Elk Grove Village, IL 60007
TEL: (847) 640-1850
FAX: 8476409432
Allied Electronics
Bensenville
TEL: (630) 860-0007
Grayslake
TEL: (847) 548-9330
Loves Park
TEL: (815) 636-1010
Oak Forest
TEL: (708) 535-0038
Arrow/Schweber
Itasca
TEL: (708) 250-0500
Bell Mlcroproducts
Schaumburg
TEL: 708-413-8530
Hamilton Hallmark
Chicago
TEL: (847) 797-7300
Newark Electronics
Rockford
TEL: (815) 229-0225
Springfield
TEL: (217) 787-9972
Schaumburg
TEL: (708) 310-8980
Willowbrook
TEL: (708) 789-4780
Wyle Electronics
Chicago
TEL: (708) 620-0969
Zeus, An Arrow Company
Itasca
TEL: (708) 250-0500
TEL: (800) 52-HI-REL
INDIANA
Harris Semiconductor
• 11590 N. Meridian SI.
Suite 100
Carmel,lN 46032
TEL: (317) 843-5180
FAX: 317 843 5191
Glestlng " Assoclstes
370 Ridgepoint Dr.
Carmel, IN 46032
TEL: (317) 844-5222
FAX: 317 844 5861
Allied Electronics
Carmel
TEL: (317) 571-1880
Arrow/Schweber
Indianapolis
TEL: (317) 299-2071
EMC
Indianapolis
TEL: (317) 484-3050

Hamilton Hallmark
Carmel
TEL: (317) 575-3500

N_ark Electronics
Louisville
TEL: (502) 423-0280

Gerber Electronics
Norwood
TEL: (617) 769-6000

N_ark Electronics
Fort Wayne
TEL: (219) 484-0766

LOUISIANA
Allied Electronics
SI. Rose
TEL: (504) 466-7575

Hamilton Hallmark
Peabody
TEL: (508) 532-9893

Indianapolis
TEL: (317) 844-0047
Zeus, An Arrow Company
TEL: (708) 250-0500
TEL: (800) 52-HI-REL
IOWA
Oasis Sales
4905 Lakeside Dr., NE
Suite 203
Cedar Rapids, IA 52402
TEL: (319) 377-8738
FAX: 319 377 8803

N_ark Electronics
Metairie
TEL: (504) 838-9771
MARYLAND
N_ Era Sales, Inc.
890 Airport Pk. Rd, SuHel03
Glen Burnie, MD 21061
TEL: (410) 761-4100
FAX: 410761-2981
Allied Electronics
Columbia
TEL: (410) 312-0810

Allied Electronics
Cedar Rapids
TEL: (319) 390-5730

Arrow/schweber
Columbia
TEL: (301) 598-7800

Hamilton Hallmark
Cedar Rapids
TEL: (319) 362-4757

Bell Mlcroproducts
Columbia
TEL: 410-720-5100

N_ark Electronics
Cedar Rapids
TEL: (319) 393-3800

Hamilton Hallmark
Columbia
TEL: (410) 720-3400

West Des Moines
TEL: (515) 222-0700
Bettendorf
TEL: (319) 359-3711

Newark Electronics
Hanover
TEL: (410) 712-6922

Zeus, An Arrow Company
TEL: (214) 380-4330
TEL: (800) 52-HI-REL

Wyle Electronics
Columbia
TEL: (410) 312-4844

KANSAS
L-TECH Marketing, Inc.
1 Kings Court, Suite 115
New Century, KS 66031
TEL: (913) 829-7884
FAX: 913-829-7611
Allied Electronics
Overland Park
TEL: (913) 338-4372

Zeus, An Arrow Company
TEL: (914) 937-7400
TEL: (800) 52-HI-REL
MASSACHUSETTS
Harris Semiconductor
• Six New England Executive Pk.
Burlington, MA 01803
TEL: (617) 221-1850
FAX: 617221 1866
Advanced Tech Ssles, Inc.
348 Park Street, Suite 102
Park Place West
N. Reading, MA01864
TEL: (508) 664-0888
FAX: 508 664 5503

Arrow/Schweber
Lenexa
TEL: (913) 541-9542
Hsmllton Hallmark
Kansas City
TEL: (913) 663-7900

Allied Electronics
Norwood
TEL: (617) 255-0361

Newark Electronics
Overland Park
TEL: (913) 677-0727
Zeus, An Arrow Company
TEL: (214) 380-4330
TEL: (800) 52-HI-REL
KENTUCKY
Glestlng " Associates
339 Arrowhead Springs Lane
Versailles, KY 40383
TEL: (606) 873-2330
FAX: 606 873 6233

13-3

Woburn
TEL: (617) 935-8350
Wyle Electronics
Bedford
(617) 271-9953
Zeus, An Arrow Company
Wilmington, MA
TEL: (508) 658-4776
TEL: (800) HI-REL

Obsolete/Discontinued
Products:
Rochester Electronics
10 Malcom Hoyt Drive
Newburyport, MA 01950
TEL: (508) 462-9332
FAX: 5084629512
MICHIGAN
Harris Semiconductor
• 27777 Franklin Rd., SuHe 460
Southfield, MI 48034
TEL: (810) 746-0800
FAX: 810746 0516
Glestlng " Associates
34441 Eight Mile Rd., Suite 113
Livonia, MI 48152
TEL: (810) 478-8106
FAX: 810477 6908
Allied Electronics
Grand Rapids
TEL: (616) 365-9960
Plymouth
TEL: (313) 416-9300
Arrow/schweber
Livonia
TEL: (313) 462-2290
Hamilton Hallmark
Plymouth
TEL: (313) 416-5800
N_ark Electronics
Grand Rapids
TEL: (616) 954-6700
Saginaw
TEL: (517) 799-0480

Peabody
TEL: (508) 538-2401

Oak Park
TEL: (810) 967-0600

Arrow/Schweber
Wilmington
TEL: (508) 658-0900

Troy
TEL: (810) 583-2899

W

Zeus, An Arrow Company
TEL: (708) 250-0500
TEL: (800) 52-HI-REL

u..

Bell Mlcroproducts
Billerica
TEL: 508-667-2400
TEL: 800-552-4305

• Field Application Assistance Available

N_ark Electronics
Marlborough
TEL: (508) 229-2200

UJ

o

ii:

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UJ

W
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UJ

North American Sales Offices, Representatives and Authorized Distributors (Continued)
MINNESOTA
OsslsSsles
7805 Telegraph Road
Sune 210
Bloomington, MN 55438
TEL: (612) 941-1917
FAX: 612 941 5701
Allied Electronics
Minnetonka
TEL: (612) 938-5633
Bell Microproducts
Eden Pralraie
TEL: 612-943-1122
Hamilton Hallmark
Minneapolis
TEL: (612) 881-2600
Newark Electronics
Minneapolis
TEL: (612) 331-6350
Sf. Paul
TEL: (612) 631-2683
Wyle Electronics
Minneapolis
TEL: (612) 853-2280

Newark Electronics
Omaha
TEL: (402) 592-2423

Allied Elsctronics
Albuquerque
TEL: (505) 266-7565

NEVADA
Allied Electronics
Las Vegas
TEL: (702) 258-1087

Hamilton Hallmark
Albuquerque
TEL: (505) 293-5119

NEWVORK
Hsrrls Semiconductor
Hampton Business Center
1611 RI. 9, Sutte U3
Wappingers Falls, NY 12590
TEL: (914) 298-0413
FAX: 914 298 0425

Hsrrls Semiconductor
• 724 Route 202
P.O. Box 591
Somerville, NJ 08876
TEL: (908) 685-6150
FAX: 908 685-6140

Harris Semiconductor
• 490 Wheeler Rd, SUite 165B
Hauppauge, NY 11788-4365
TEL: (516) 342-0291 Analog
TEL: (516) 342-0292 Digital
FAX: 516 342 0295

Trltek Sales, Inc.
One Mall Or., SuHe410
Cherry Hill, NJ 08002
TEL: (609) 667-0200
FAX: 609 667 8741

MISSISSIPPI
Newark Electronics
Ridgeland
TEL: (601) 956-3834

Foster & Wager, Inc.
300 Main Street
Vestal, NY 13850
TEL: (607) 748-5963
FAX: 607 748 5965

Allied Electronics
E. Brunswick
TEL: (908) 613-0828

MISSOURI
L-TECH Marketing, Inc.
2414 Hwy. 94 South Outer Rd.
SuneA
St. Chartes; MO 63303
TEL: (314) 936-2007
FAX: 314-936-1991

2511 Browncroft Blvd.
Rochester, NY 14625
TEL: (716) 385-7744
FAX: 716 5861359

MI. Laurel
TEL: (609) 234-7769

7696 Mountain Ash
Liverpool, NY 13090
TEL: (315) 457-7954
FAX: 315 457 7076

Parsippany
TEL: (201) 428-3350
Arrowl$chweber
MarRon
TEL: (609) 596-8000

Allied ElectroniCS
Earth City
TEL: (314) 291-7031

Pinebrook
TEL: (201) 227-7880

ArrowlSchweber
Sf. Louis
TEL: (314) 56'7-6888

Bell Microproducts
Clifton
TEL: 201-777-4100

Hamilton Hallmark
St. louis
TEL: (314) 291-5350

Hamilton Hsllmsrk
Cherry Hili
TEL: (609) 424-0110

Newark Electronics
St. louis
TEL: (314) 453-9400

Parsippany
TEL: (201) 515-1641

Parallax, Inc.
734 Walt Whitman Rd.
Melville, NY 11747
TEL: (516) 351-1000
FAX: 516-351-1608
Alliance EtactronicB, Inc.
Huntington
TEL: (516) 673-1930
Allied Electronics
Amherst
TEL: (716) 831-8101
Graat Neck
TEL: (516) 487-5211

Pine Brook
TEL: (201) 882-8358

Zeus, An Arrow Company
TEL: (214) 380-4330
TEL: (800) 52-Hi-REL

Allied Electronics
Omaha
TEL: (402) 697-0038

Zeus, An Arrow Company
TEL: (408) 629-4789
TEL: (800) 52-HI-REL

NEW JERSEY
Harris Semiconductor
• Plaza 1000 at Main Street
SUite 104
Voorhees, NJ 08043
TEL: (609) 751-3425
FAX: 609 7515911

Zeus, An Arrow Company
TEL: (214) 380-4330
TEL: (800) 52:HI-REL

NEBRASKA
Advsnced Tech. Sales, Inc.
601 North Mur-Len, Sune 8
Olathe, KS .66082
TEL: (913) 782-8702
FAX: 913 782 8641

Newark Electronics
Albuquerque
TEL: (505) 828-1878

NEW HAMPHIRE
Newark Electronics
Nashua
TEL: (603) 888-5790

Hauppauge
TEL: (516) 234-0485

Newark Electronics
East Brunswick
TEL: (908) 937-6600

Lagrangeville
TEL: (914) 452-1470

Zeus, An Arrow Company
TEL: (914) 937-7400
TEL: (800) 52-HI-REL

Rochester
TEL: (716) 292-1670

NEW MEXICO
Compass Mktg. & Salas, Inc.
4100 Osuna Rd., Nc, Suite 109
Albuquerque, NM 871 09
TEL: (505) 344-9990
FAX: 505 345 4848

• Field Application Assistance Available

13-4

Hauppauge
TEL: (516) 231-1000
Melville
TEL: (516) 391-1276
TEL: (516) 391-1300
TEL: (516) 391-1633
Rochester
TEL: (716) 427-0300
Bell Microproducts
Smnhtown
TEL: 516-543-2000
Hamilton Hallmark
Long Island
TEL: (516) 737-0600
Hauppauge
TEL: (516) 434-7470
Rochester
TEL: (716) 272-2740
Newark Electronics
Wappingers Falls
TEL: (914) 298-2810
Latham
TEL: (518) 783-0983
Bohemia
TEL: (516) 567-4200
Williamsville
TEL: (716) 631-2311
Pittsford
TEL: (716) 381-4244
Liverpool
TEL: (315) 457-4873
Wyle Electronics
Long Island.
TEL: (516) 293-8448
Rochester
TEL: (716) 334-5970
Zeus, An Arrow Company
Pt. Chester
TEL: (914) 937-7400
TEL: (800) 52-HI-REL
NORTH CAROLINA
New Era Sales
1215 Jones Franklin Road
Suite 201
Raleigh, NC 27606
TEL: (919) 859-4400
FAX: 919 859 6167
Allied Electronics
Charlotte
TEL: (704) 525-0300
Raleigh
TEL: (919) 876-5645
ArrowlSchweber
Raleigh
TEL: (919) 876-3132

Syracuse
TEL: (315) 448-7411

EMC
Charlotte
TEL: (704) 394-6195

ArrowJSchwebar
Farmingdale
TEL: (516) 293-6383

Hamilton Hallmark
Raleigh
TEL: (919) 872-0712

North American Sales Offices, Representatives and Authorized Distributors (Continued)
Newark Electronics
Charlotte
TEL: (704) 535-5650
Greensboro
TEL: (910) 294-2142
Raleigh
TEL: (919) 781-7677
Wyle Electronics
Raleigh
TEL: (919) 481-3737
TEL: 800-950-9953
Zeus, An Arrow Company
TEL: (407) 333-3055
TEL: (800) 52-HI-REL
OHIO
Glestlng .. Associates
P.O. Box 39398
2854 Blue Rook Rd.
Cincinnati, OH 45239
TEL: (513) 385-1105
FAX: 513 385 5069
6324 Tamworth Ct.
Columbus, OH 43017
TEL: (614) 792-5900
FAX: 614192 6601
6200 SOM Center Rd.
Suhe 0-20
Solon, OH 44139
TEL: (216) 498-4644
FAX: 216 498 4554
Alliance ElectronicS, Inc_
Dayton
TEL: (513) 433-7700
Allied Electronics
Beachwood
TEL: (216) 831-4900
Cincinnati
TEL: (513) 771-6990

Columbus
TEL: (614) 326-0352
Dayton
TEL: (513) 294-8980

Cleveland
TEL: (216) 391-9330
Wyle Electronics
Cleveland
TEL: (216) 248-9996

Columbus
TEL: (614) 888-3313
Dayton
TEL: (513) 439-6735
Newark Electronics
Cincinnati
TEL: (513) 772-8181

Harrisburg
TEL: (717) 540-7101

Zeus, An Arrow Company
TEL: (708) 595-9730
TEL: (800) 52-HI-REL

Pittsburg
TEL: (412) 931-2774

OKLAHOMA
Nova Marketing
8421 Easl61st Street, Suhe P
Tulsa, OK 74133-1928
TEL: (800) 826-8557
TEL: (918) 660-5105
FAX: 918 357 1091

Arrow/schweber
Pittsburgh
TEL: (412) 327-1130
800-529-0895
Hamilton Hellmark
Pittsburgh
TEL: (800) 332-8638

Allied Electronics
Tulsa
TEL: (918) 250-4505

Newark Electronics
Allentown
TEL: (610) 434-7171

Arrow/schweber
Tulsa
TEL: (918) 252-7537

Ft. Washington
TEL: (215) 654-1434
Pittsburgh
TEL: (412) 788-4790

Hamilton Hallmark
Tulsa
TEL: (918) 459-6000

Wyle Electronics
Philladelphla
TEL: (609) 439-9110

Newark Electronics
Oklahoma City
TEL: (405) 843-3301

Zeus, An Arrow Compsny
TEL: (214) 380-4330
TEL: (800) 52-HI-REL

Hamilton Hallmark
Cleveland
TEL: (216) 498-1100

Allied ElectroniCS
Chadds Ford
TEL: (610) 388-8455

Dayton
TEL: (513) 436-9935

Arrow/Schweber
Solon
TEL: (216) 248-3990

Cleveland
TEL: (216) 442-3441

PENNSYLVANIA
Glestlng .. Associates
471 Walnut Street
Pittsburgh, PA 15238
TEL: (412) 828-3553
FAX: 412 828 6160

Youngstown
TEL: (216) 793-6134

Tulsa
TEL: (918) 252-5070

EMC
Columbus
TEL: (614) 299-4161

Zeus, An Arrow Company
TEL: (408) 629-4789
TEL: (800) 52-HI-REL

Toledo
TEL: (419) 866-0404

Worthington
TEL: (614) 785-1270

Centerville
TEL: (513) 435-5563

Wyle Electronics
Portland
TEL: (503) 598-9953

Zeus, An Arrow CompallY
TEL: (914) 937-7400
TEL: (800) 52-HI-REL

OREGON
Northwest Marketing Assoc_
4905 SW Griffdh Drive Suhe 106
Beaverton, OR 97005
TEL: (503) 644-4840
FAX: 503 644-9519
Allied Electronics
Beaverton
TEL: (503) 826-9921

SOUTH CAROUNA
Allied Electronics
Greenville
TEL: (864) 288-8835
Newark Electronics
Greenville
TEL: (803) 288-9610
TENNESSEE
Newark Electronics
Knoxville
TEL: (615) 588-6493

Newark Electronics
Portland
TEL: (503) 297-1984

8350 Meadow Rd., Suhe 174
Dallas, TX 75231
TEL: (214) 265-4800
FAX: 214265 4668
Corporate Atrium II, Suite 140
10701 Corporate Dr.
Stafford, TX 77477
TEL: (713) 240-6082
FAX: 713240 6094
Allied Electronles
Austin
TEL: (512) 219-7171
Brownsville
TEL: (210) 548-1129
Dallas
TEL: (214) 341-8444
EIPaso
(915) 779-6294
Fort Worth
(817) 595-3500
Forth Worth
(817) 595-6455
Humble
(713) 446-8005
Arrow/schweber
Austin
TEL: (512) 835-4180
Dallas
TEL: (214) 380-6464
Houston
TEL: (713) 647-6868
Bell Mleroproducts
Austin
TEL: 512-258-0725
Richardson
TEL: 214-783-4191
Hamilton Hallmark
Austin
TEL: (512) 258-8848
Dallas
TEL: (214) 553-4300
Houston
TEL: (713) 781-6100

Memphis
TEL: (901) 396-7970

Newark Electronics
Austin
TEL: (512) 338-0287

Brentwood
TEL: (615) 371-1341

Corpus Christi
TEL: (512) 857-5621

TEXAS
Harrla Semiconductor
• 17000 Dallas Parkway,
Suhe205
Dallas, TX 76248
TEL: (972) 733-0800
FAX: 972 733 0819

EIPaso
TEL: (915) 772-6367

AlmacJArrow
Beaverton
TEL: (503) 629-8090
Hamilton Hallmark
Portland
TEL: (503) 526-6200

Nova Marketing
8310 Capitol of Texas Hwy.
Suhe 180
Austin, TX 78731
TEL: (512) 343-2321
FAX: 512343-2487

• Field Application Assistance Available

13-5

Houston
TEL: (713) 894-9334
San Antonio
TEL: (210) 734-7960

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