1996_Motorola_Analog_Interface_ICs_Device_Data_Volume_2 1996 Motorola Analog Interface ICs Device Data Volume 2
User Manual: 1996_Motorola_Analog_Interface_ICs_Device_Data_Volume_2
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®
I!!'0TOROLA
DL 128/D
REV 6
Analog/lnterfacelCs
Device Data
Vol. II
Volumes
I
II
I
I
I
II
II
II
II
II
II
II
I
II
I
II
a
II
Power Supply Circuits II
Power/Motor Control Circuits II
Voltage References II
Data Conversion II
Interface Circuits II
Communication Circuits II
Consumer Electronic Circuits II
Automotive Electronic Circuits IZ!I
Amplifiers and Comparators
Other Analog Circuits
II
II
Alphanumeric Index and
Cross References
III
III
Packaging Information lEI
Quality and Reliability Assurance III
Tape and Reel Options
Applications and Product Literature
III
What's Different
New Additions
,
~-
;'
CHAPTER 3
CHAPTER 7
LM2575
.MC78BCOO
MC78FCOO
MC78LCOO
MC33154
MC33264
MC33341
MC33347
MC33348
MC33363A
MC33364
MC33368
MC33463
MC33464
MC33465
MC33466
MC34065, MC33065
MC34165, MC33165
MC44604
MC44605
MC1413
MC34156
SN75175
CHAPTERS
MC13109
MC13110
MC13111
MC13144
MC13159
MC13283
MC44007
MC44030/35
MC44306
MC44353
MC44354
MC44355
MC44461
MC44462
MC44463
CHAPTER 10
CHAPTER 9
MC13022
MC13029A
MC13081X
MC13022A
MC13280AY, MC13281AIB
MC13282A
MC33143
MC33193
MC33197A
MC33293
MCCF33093
MCCF33094
MCCF33095
Deletes
LM307
LM248
MC1411
MC1412 .
MC1472
MC1748C
MC3361C
MC3371A
MC3372A
MC3430
MC3486
MC3487
MC13001 XlO7X
MC13017
MC13024
MC33292
MC33344
MC34050
MC34051
MC44301
MC44302
MC44303
MCT1413
SN75173
New Product Literature (Referenced)
AN454A
AN829
AN921
AN932
AN1044
AN1315
AN1539
AN1544
AN1548
AN1575
Not Recommended For New Designs
AM26LS31
AM26LS32
MC26S10
MC3373
MC3448A
MC3450
MC3453
MC3467
MC3481
MC3485
ULN2068
TDA1185A
3 Ways To Receive
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®
MOTOROLA
DL128/D
REV 6
Analog les
Device Data
Vol. II
This publication presents technical information for the broad line of Analog and Interface Integrated Circuit
products. Complete device specifications are provided in the form of Data Sheets which are categorized by product
type into ten chapters for easy reference. Selector Guides by product family are provided in the beginning of each
chapter to enable quick comparisons of performance characteristics. A Cross Reference chapter lists Motorola
nearest replacement and functional equivalent part numbers for other industry products.
One chapter is devoted showing all of the Tape and Reel Options. All Packaging Information, including
surface mount packages, is provided in another chapter.
Additionally, chapters are provided with information on Quality and Reliability Assurance program concepts,
high-reliability processing, and abstracts of available Applications and Product Literature.
The information in this book has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and
do vary in different applications. All operating parameters, including ''Typicals" must be validated for each customer
application by customer's technical experts. Motorola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attomey fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and ® are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Printed in U.S.A.
Series J
First Printing
© Motorola, Inc. 1996
Previous Edition © 1995
"All Rights Reserved"
Data Classification
Product PrevIew
This heading on a data sheet indicates that the device is in the formative stages or
in design (under development). The disclaimer at the bottom of the first page reads:
"This document contains information on a product under development. Motorola
reserves the right to change or discontinue this product without notice."
Advance Information
This heading on a data sheet indicates that the device is in sampling,
pre-production, or first production stages. The disclaimer at the bottom of the first
page reads: "This document contains information on a new product. Specifications
and information herein are subject to change without notice."
Fully Released
A fully released data sheet contains neither a classification heading nor a disclaimer
at the bottom of the first page. This document contains information on a product in
full production. Guaranteed limits will not be changed without written notice to your
local Motorola Semiconductor Sales Office.
C-QUAM®, Designer's, Easy Switcher, GreenLine, MDTL, MECL, MECL 10,000,
MONOMAX, MOSAIC®, MRTL, MTTL, MOSFET, SENSEFET, Sleep-Mode, SMARTMOS,
Switchmode, and ZIP-R-TRIM® are trademarks of Motorola Inc.
..
Alphanumeric Index and
Cross References
In Brief ...
Motorola Analog and Interface Integrated Circuits cover a
much broader range of products than the traditional op amps!
regulators/consumer-image associated with Analog suppliers. Analog circuit technology currently influences the design
and architecture of equipment for all major markets. As with
other integrated circuit technologies, Analog circuit design
techniques and processes have been continually refined and
updated to meet the needs of these diversified markets.
Operational amplifiers have utilized JFET inputs for
improved performance, plus innovative design and trimming
concepts have evolved for improved high performance and
precision characteristics. In analog power ICs, basic voltage
regulators have been refined to include higher current and
voltage levels, low dropout regulators, and more precise
three-terminal fixed and adjustable voltages. The power area
continues to expand into switching regulators, power supply
control and supervisory circuits, motor controllers, and battery
charging controllers.
Analog designs also offer a wide array of line drivers,
receivers and transceivers for many of the EIA, European,
IEEE and IBM interface standards. Peripheral drivers for a
variety of devices are also offered. In addition to these key
interface functions, hard disk drive read channel circuits,
10BASE-T and Ethernet circuits are also available.
In Data Conversion, a high performance video speed flash
converter is available, as well as a variety of CMOS and
Sigma-Delta converters. Analog circuit technology has also
provided precision low-voltage references for use in Data
Conversion and other low temperature drift applications.
A host of special purpose analog devices have also been
developed. These circuits find applications in telecommunications, radio, television, automotive, RF communications, and
data transmission. These products have reduced the cost of
RF communications, and have provided capabilities in telecommunications which make the telephone line convenient
for both voice and data communications. Analog developments have also reduced the many discrete components
formerly required for consumer functions to a few IC packages
and have made significant contributions to the rapidly growing
market for electronics in automotive applications.
The table of contents provides a perspective of the many
markets served by Analogllnterface ICs and of Motorola's
involvement in these areas.
MOTOROLA ANALOG IC DEVICE DATA
1-1
II
Alphanumeric Index
AM26LS30
AM26LS31#
AM26LS32#
CA3059
CA3146
LF347, B
LF351
LF353
LF411C
LF412C
LM293
LM301A
LM308A
LM311
LM317
LM317L
LM317M
LM2575
LM2900
LM2901, V
LM2902, V
LM2903, V
LM2904, V
LM2931
Dual DlfferentiaVQuad Single-Ended Line
Drtvers
Qued Line Drtver with NAND Enabled
Three-State Outputs
Quad EIA-4221423 Line Receiver with
Three-State Outputs
Zero Voltage Swhches
General Purpose Transistor Array
JFET Input Operational Amplifiers
JFET Input Operational Amplifiers
JFET Input Operational Amplifiers
Low Offset, Low Drift JFET Input Operational
AmplWiers
Low Offset, Low Drift JFET Input Operational
Amplifiers
i
Low Offset Voltage Dual Comparators
Operational Amplifiers
Precision Operational Amplifier
Highly Flexible Voltage Comparator
Three-Terminal Adjustable Output Positive
Voltage Regulator
Three-Terminal Adjustable Output Voltage
Regulator
Three-Terminal Adjustable Output Positive
Voltage Regulator
Positive
Easy SWitcher 1.0 A Stel>-Down Voltage
Regulator
Quad Single Supply Operational Amplifier
Quad Single Supply Comparator
Quad Low Power Operational Amplifier
Low Offset Voltage Dual Comparator
Duel Low Power Operational Amplifier
Low nm'nnlli' IInlt.n.
7-13
7-24
7-24
4-14
9-28
2-11
2-11
2-11
2-13
2-13
2-68
2-30
2-34
2-39
3-48
MC1488
MC14C88B
MC14C89B, AB
MCl469, A
MC1490
MC1494
MC1495
MC1496
MC1723C
Quad Line Driver
Quad Low Power Line Drtver
Quad Low Power Line Receiver
Quad Line Receivers
RFIIF Audio Amplifier
Linear Four-Quadrant Multiplier
Wldeband Linear Four-Quadrant Multiplier
Balanced Modulatosr/Demodulators
I
7-33
7-44
7-50
7-39
2-92
11-14
11-28
8-45
3-56
3-64
3-116
2-113
2-52
2-45
2-68
2-62
3-139
MC3356
MC3357
MC3358
MC3359
MC3362
MC3363
MC3371
MC3372
MC3373#
I
I
Differentially Connected Pair and Three
Isolated Transistor Arrays
Wideband FSK Reoelver
Low Power FM IF
Dual, Low Power Operational Amplifier
Dual, Low Power Operational Amplifier
Low Power Dual Conversion FM Receiver
Low Power Dual Conversion FM Receiver
Low Power Narrowband FM IF
Low Power Narrowband FM IF
Remote Control Wldeband Amplifier with
Detector
8-66
8-72
2-137
8-76
8-62
8-69
8-97
8-97
9-72
• =See Communloetlons Devioe Data (DL136).
# = Not recommended for new designs.
1-2
MOTOROLA ANALOG IC DEVICE DATA
Alphanumeric Index (continued)
MC3405
MC3418
MC3419-IL
MC3423
MC3425
MOWO/I
MC345SfI
MQM6
MC34S&
MOM?t
,MCW~
MC3479
MC3481#
MC3485#
MC348BA
MC3518
MC4558AC,C
MC4741C
MC7800
Series
MC78LOO, A
Series
MC78MOO
Series
Dual Operational Amplmer and Dual
Comparator
Continuously Variable Slope Delta
ModulatoriDemodulator
Telephone Line-Feed Circuit
Overvoltage Crowbar Sensing Circuit
Power Supply Supervisory/Over and
Undervoltage Protection Circuit
2-129
BIdI~onalllislflm!l!mtalion B\is (GPIS)
7~8
Traneoelver
Q\Jad Mm ¢omplItibIe lln$ ReoelVers
Mil1'\.. Compatible Q\Jad).l", DrtYet
7-71'
D\IaI Ttmlflg CIrouII
Dual, LOw ~ opemflonalAmpilfler
f'I-4a
2.-137
.~~WIth~
7~
G4lnCl>*~
,
3-171
3-177
'
7-64
l.Qwtelll~~AmpIliier ,
2--~
Stepper Motor Driver
Quad Single-Ended Line DrivAr
Quad Single-Ended Line Driver
Dual EIA-4231EIA-232D Line Driver
Continuously Variable Slope Delta
ModulatoriDemodulator
Dual Wide Bandwidth Operational Amplifiers
Differential Input Operational AmplWier
Three-Terminal Positive Voltage Regulators
4-19
7-81
7-81
7-86
2-149
2-156
3-t85
Three-Terminal Low Current Positive Voltage
Regulators
Three-Terminal Medium Current Positive
Voltage Regulators
3-200
'fII1et-AmPm l':oeilMl Volt!lQe FIegulat9l'S
}0;2;$
Ma76BCOO
~OO
~a_tor
M~Y_~
MOm.COO
Mic~~'
~
~
~
~
MC7IITOO
3-207
Se!1e$
~SIIIifI$
,~,A"
'u_
l'
~,
~
~f!'-'
Il-~
H~~e~~~
~
MC13~
MC'fa~
MC13022A
MC13025
MC13027
MC13028A
MCl3029A
MC13030
MC13055
MC13060
MC13077
MC13081X
MC13109
MC13110
~
, a.e
,
~~StetIIO"'~
9.1111
~~~AMSlsMo~
'~1
Advanced Medium Voltage AM Stereo Decoder
Electronically Tuned Radio Front End
AMAX Stereo Chipset
Advanced Wide Voltage IF and C-QUAM AM
Stereo Decoder
Advanced Wide Voltage IF and C-QUAM AM
Stereo Decoder with FM Amplifier and
AMlFM Internal Switch
Dual Conversion AM Receiver
Wideband FSK Receiver
Mini-Watt Audio Output
Advanced PAUNTSC Encoder
Multimode Color Monitor Horizontal, Vertical
and Video Combination Processor
Universal Cordless Telephone Subsystem IC
Universal Cordless Telephone Subsystem IC
with Scrambler
9-86
9-91
9-94
9-119
9-137
9-156
8-121
9-171
9-175
9-187
8-128
8-154
MC13111
MC13122
MC13135
MC13136
MC13141
MC13142
MC13143
MC13144
Universal Cordless Telephone Subsystem IC
AMAX Stereo Chipset
FM Communications Receiver
FM Communications Receiver
Low Power DC-l ,8 GHz LNA and Mixer
Low Power DC-l ,8 GHz LNA, Mixer and VCO
Ultra Low Power DC-2.4 GHz Linear Mixer
VHF - 2,0 GHz Low Noise Amplifier with
Programmable Bias
8-185
9-94
8-214
8-214
8-226
8-235
8-245
8-252
MC131110
Narrowband FM:CO/IIeSil Det/IOIOr IF
8458
MQ1!!155
~
Wldeband FM IF$y$tem
M()1$11)1l
WklebandFM1FSy$Ien'l
MC~1B8
WicMIland FM 1f!' SlJb$y$Iem
WRlIIband FM IF AlnpIIIIIlI
MC~l$ ,
6-275
8~
.e..oos
H30
-lnIra~~~Systl!ln
Melam
H36
.lA'I/U'WAM1'~
MCl3t15
Jl..oo;;
wm
IMP"~
Imz V1d~~$Qt
mall.' ~OI1!lO
HCa
MOiIi32a1 A. Ii
sMl.lO MH~Vldeo PrOC$$llQ/
HOO
MC13282A
MCI3283
MC26S10#
MC33023
MC33025
MC33030
MC33033
MC33035
MC33039
MC33060A
100 MHz Video Processor with OSD Interface
130 MHz Video Processor with OSD Interface
Quad Open-Collector Bus Transceiver
High Speed Single-Ended PWM Controller
High Speed Double-Ended PWM Controller
DC Servo Motor ControlieriDriver
Brushless DC Motor Controller
Brushless DC Motor Controller
Closed-Loop Brushless Motor Adapter
Precision Switch mode Pulse Width Modulator
Control Circuit
9-215
9-226
7-55
3-395
3-411
4-27
4-41
4-84
4-87
3-428
~
~ ilohvetterOOnlrolQllult
'MIm~
.
Me33064
~
Undervdltage $tin$1ng CIrcuit
,
HIgh P~lll.Ial¢hllhtllli~t,Mode
~nIrPiISt
~L
'~Dual CI\anIleI~[ll(JfMod&
~
"~Re$IlI!!IIit~~t
'MC3306!1
NlC3$Ql1.~
~A
~,A
JotIgh~~~I!'f
H!ghSlewllllte, WJu. ~ ~&ipJll\l
~~Ill\l
~!!Iew Rate, Wi!IIIanw!dih, Slngl&$uppIy
~~~
-$l$W_~~ $1ngl/l$ullPlY
:'''II'~~
~
~ tll9hJ)ul~t.QwPower,lo,w
1\IoIalI8lpo!it Qp.Alnp ,
MC33077
MC33078
MC33079
MC33091A
MC33092
MC33095
MC33102
Dual, Low Noise Operational Amplifier
DuaVQuad Low Noise Operational Amplifier
DuaVQuad Low Noise Operational Amplifier
High Side TMOS Driver
Alternator Voltage Regulator
Integral Alternator Regulator
Sleep-Mode Two-State, Micropower
Operational Amplifier
Low Voltage Compander
Low Voltage Compander with Mute and
Feedthrough
Subscriber Loop Interface Circuit
Low Voltage Subscriber loop Interface Circuit
Power Management Controller
MC33110
MC33111
MC33120
MC33121
MC33128
2-169
2-180
2-180
10-31
10-45
10-134
2-189
3-247
• = See Communications Device Data (DL 136),
# = Not recommended for new designs,
MOTOROLA ANALOG IC DEVICE DATA
1-3
•
Alphanumeric Index (continued)
MC33129
MC33143
MC33151
MC33152
MC33153
MC33154
MC33160
MC33161
MC33181
MC33182
MC33184
MC33282
MC33264
MC33293A
MC33298
MC33304
MC33340
High Performance Current Mode Controller
Dual High-Side Switch
High Speed Dual MOSFET Driver
High Speed Dual MOSFET Driver
Single IGBT Gate Driver
Single IGBT Gate Driver
Microprocessor Voltage Regulator and
Supervisory Circuit
Universal Voltaga Monitors
i
OpAmp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Mi-Bus Interface Stepper Motor Controller
Automotive Direction Indicator
Automotive Wash Wiper 11mer
Automotive ISO 9141 Serial Link Driver
Rail-te-Rall Operational Amplifier
Rall-te-Rail Operational Amplifier
Hall-te-·Rail oP"raliolonal Amplifier
i
OpAmp
Low Input Offset, High Slew Rate, Wide
Bandwidth, JFET Input Op Amp
Low Input Offset, High Slew Rate, Wide
Bandwidth, JFET Input Op Amp
Quad Low Side Switch
Octal Output Driver
Low Voltage RaIHe-Rall, Sleepmode
Operational Amplifier
Battery Fast
3-502
10-45
3-517
3-525
3-2M
3-265
3-533
3-540
MC33345
MC33346
MC33347
MC33348
Lithium Battery Protection Circuh for One to
Four Cell Battery Packs
Lithium Battery Protection Clrcuh for Three or
Four Cell Battery Packs
Lithium Banery Protection Circuit for One or
TWo Cell Banery Packs
Lithium Banery Protection Circuit for One Cell
Banery Packs
3-319
3-331
3-332
3-342
2-299
2-299
2-299
MC34004, B
MC34010
MC34011A
MC34012
MC34014
JFET Input Operational Amplifier
Electronic Telephone Circuit
Electronic Telephone Circuit
Telephone Tone Ringer
Telephone Speech Network with Dialer
Interface
Cordless Universal Telephone Interface
Telephone Tone Ringer
Voice Switched Speakerphone Circuit
High
Single-Ended PWM Controller
2-265
MC34071,A
High Slew Rate, Wide Bandwichh,
Single-Supply Operational Ampllfler
High Slew Rate, Wide Bandwidth,
Single-5upply Operational Amplifier
High Slew Rate, Wide Bandwidth,
Single-Supply Operational Amplifier
High Slew Rate, Wide Bandwlchh, JFET Input
Operational Amplifier
High Slew Rate, Wide Bandwlchh, JFET Input
Operational Ampllfler
Wide Bandwlchh, JFET Input
I Slew
I
2-272
2-246
MC34072,A
2-246
MC34074, A
1Q-94
10-109
2-254
MC34080
3-293
MC34082
MC34081
2-272
2-272
2-288
2-288
2-288
• ~ See Communications Device Data (DL136).
# ~ Not recommended for new designs.
1-4
MOTOROLA ANALOG IC DEVICE DATA
Alphanumeric Index (continued)
'/'.'
~~
MC34083
MC34084
MC34085
MC34114
MC34115
MCM1ff
eMQW1§
l'UncIkIII
High Slew Rate, Wide Bandwidth, JFET Input
Operational Amplifier
High Slew Rate, Wide Bandwidth, JFET Input
Operational Amplifier
High Slew Rate, Wide Bandwidth, JFET Input
Operational Amplifier
Telephone Speech NetworK with Dialer
Interface
Continuously Variable Slope Delta
Modulator/Demodulator
MQ$4'/ii
M(;,$41~
~6D
~$1
,MC34m
MC34164
MC34165
MC34166
MC34167
MC34181
MC34182
MC34184
MC34216A
;,
MC44603
2-288
MC44604
2-288
MC44605
__
~
~
t:,
ln1ijlltOrlve!
,~=e
'~1ll
~
iI!ld
UtMtlIIIt~~
~ SWlWIliIlg Regulatnl'
Micropower Undervoltage Sensing Circuit
Power Switching Regulator
Power Switching Regulator
Power Switching Regulator
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Programmable Telephone Line Interface Circuit
with Loudspeaker Amplifier
5.0 V, 200 M-Bit'Sec PR-/V Hard Disk Drive
Read Channel
Power Factor Controller
l::owet FaI1lor~r
~~ '11IImIna!OlReg!lIallir
U31
~~~aI/iI~W~
OI~
,
"
~J
~
,q!I~~rdVliJlll:l,~ i
~".~~lIIdlIo9r~'
S~MuIll$tantfard~~
bZ1lJ
~,
~.
~
~
~1i:H/jdeQ $lgt:la1~Wllh
;~4intl
.
~~?JItI')
IJn$
MC#144
MC44145
MC44353
MC44354
MC44355
MC44461
MC44462
MC44463
MC44602
P1Wlfr.Lboke'dLaqp
7-118
~12
~~
$-641
...
-
.~
k'l26
Pixel Clock Generator/Sync Separator
PLL Tuned UHF AudioNideo Modulator ICs for
PAL, SECAM and NTSC TV Systems
PLL Tuned UHF AudioNideo Modulator ICs for
PAL, SECAM and NTSC TV Systems
PLL Tuned UHF AudioNideo Modulator ICs for
PAL, SECAM and NTSC TV Systems
Picture-in-Picture (PIP) Controller
Y-C Picture-in-Picture (PIP) Controller
Picture-in-Picture (PIP) Controller
High Performance Current Mode Controller
MCf9Q7$
MO¢F7907il
~O
SAA1ll42
SG3525A
SG3526
SG3527A
SN75175
TCA0372
TCA3385
TCA3388
TCA5600
TCF5600
~
~
TCF6000
"YDAiOl!S¢
1T.lAtl&w'
'Wli2 '
~,
".,
1\011C,J;O
9-331
9-338
"rl..o12c, AO
9-338
~iAc
J'1.Qe4C, At;
9-338
9-341
9-354
9-360
3-651
~
~\II
~~(.Th~
Quad:£:1A-48ll LIiie Dliveh\1ll'l ~
a
-
3-667
~89
~90
9-367
9-374
9-381
9-388
9-395
9-396
9-397
~
1"i20
MIIEI
7-146
OUlpllt
MCT~
'~7'I
,~
~
~7.2l
MCC3334
MC'CFa334
MOOF33093
2-299
Mixed Frequency Mode GreenLine PWM
Controller
High Safety Standby Ladder Mode GreenLine
PWM Controller
High Safety Latched Mode GreenLine PWM
Controller for (Multi) Synchronized
Applications
PLL Tuning Circuit with 3-Wire Bus
PLL Tuning Circuit with 12C Bus
PLL Tuning Circuit with 12C Bus
PLL Tuning Circuit with 12C Bus
PLL Tuning Circuit with 3-Wire Bus
PLL Tuning Circun with 12C Bus
PLL Tuning Circun with 12C Bus
,PI.J..~~.j..sft~artd
~16\l
Ma1617i48
2-299
I'IInOIIIIII
'~~,.'
AtJgm\ent
' ,
3-564
3-570
3-584
3-598
2-299
~~!'l$plaj~~
MC34261
MC44817, B
MC44818
MC44824,25
MC44826
MC44827
MC44828
MC44829
':MC44$64
3-55l)
..
MC34250
Pm..
&ntbtl'
2-288
TelepliOtll'TO!!fII'll.
, ~~~.qJrouII,
~19
~m
~
,.
1l.O14(1; AC
TJ.081(l,AC
TL431, A, B
Series
TL494
TL594
ElecttonIc 19ni11enCol'ltRllthip
Hlghinergy Ignition CifCIdt
HIgh EnfIrgy 19n1lllJn~
1Q..l$1
111-1&
10-15
~~
,0-,32
' ~~&!br~t
~1fiitl1l1\'CoIItIolC/ijp
10-<1'34
'f&.-131
HQ
Oual WIde ~OpeIltWAmpIifier
:!-iSS
~eo,rtol~1p
1n~HtgM~
OuaI'
Al'n/lIItIiir
$IiIpper M!lIDtl»iYet
Pulse Width Modulator Control Circuit
Pulse Width Modulator Control Circuit
Pulse Width Modulator Control Circuit
Quad EIA-485 Line Receiver
Dual Power Operational AmplHier
Tel$phone Ring Signal Converter
Telephone Speech Network
Universal Microprocessor Power
Supply/Controller
Universal Microprocessor Power
Supply/Controller
Peripheral Clamping Array
'\l~MQIof~~i
~-~
but~Al\'IpII\let
1npu\~1jmpIIiier
lnpUI~~
~'IilIils9~~~AmpJlller
~m,~~
~1fJ~AmpIlfJer
JmInPul~~
,m II\Plit~ArnpI1!iet
Programmable Precision References
Switchmode Pulse Width Modulation Control
Circun
Precision Switchmode Pulse Width Modulation
Control Circuit
104$3
4-Q2 .
~91
~97
~91
7-157
2-308
3-705
3-705
HH44
IHI7
~1tl1
W1~
.....
'Wll!
~
io41t
'.H'&
,~
5-18
3-716
3-726
• = See Communications Device Data (DL136).
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
--------
1-5
•
Alphanumeric Index (continued)
UC3843A
UC3843B
UC3844
UC3844B
UC3845
UC3845B
UC3844B
UC3845
UC3845B
ULN2068#
High Performance Current Mode Controller
High Performence Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
Quad 1.5 A Sinking High Current Switch
3-745
3-758
3-n2
3-785
3-n2
3-785
3-785
3-n2
3-785
7-162
• = See Communications Device Data (DL136).
# = Not recommended for new designs.
1'-6
MOTOROLA ANALOG IC DEVICE DATA
Cross References
The following table represents a cross reference guide for all
Analog devices that are manufactured by Motorola. Where the
Motorola part number differs from the industry part
p~~~~~er
Motorola Nearest
Replacement
Motorola Similar
Replacement
number, the Motorola device is a ''form, fit and function"
replacement for the industry part number. However, some
differences in characteristics and/or specifications may exist.
P~~'W~?;er
Motorola Nearest
Replacement
75175
SN75175
CS2845D
UC2845BD1
9636AT
MC3488AP
CS3842AD
UC3842BD1
9640PC
MC26S10P#
CS3843AD
UC3843BD1
9667PC
MC1413P
CS3844D
UC3844BD1
9668PC
MC1416P
CS3845D
UC3845BD1
Motorola Similar
Replacement
AD589J
LM385Z-1.2
DM8822N
MC1489AP
AD589K
LM385Z-1.2
DS1233M
MC34064P-5
AD589L
LM385Z-1.2
DS1488N
MC1488P
AD589M
LM385BZ-1.2
DS1489AN
MC1489AP
AM201AD
LM201AN
DS1489N
MC1489P
AM201D
LM201AN
DS26LS32N
AM26LS32P#
AM26LS30P
AM26LS30PC
DS26S10CN
MC26S10P#
AM26LS31CJ
AM26LS31 PC#
DS3650N
MC3450P#
AM26LS31CN
AM26LS31 PC#
DS8834N
MC8T26AP
AM26LS32ACJ
AM26LS32D#
DS8835N
MC8T26AP
AM26LS32ACN
AM26LS32PC#
DS9636ACN
AM26LS32PC
AM26LS32PC#
ICL741CLNPA
MC1741CP1
AM723PC
MC1723CP
ICL741CLNTY
MC1741CP1
MC3488AP1
AN5150
MC34129P
ICL8008CPA
LM301 AN
CA081AE
TL081ACP
ICL8008CTY
LM301AN
CA081E
TL081CP
ICL8017CTW
LM301AN
CA082AE
TL082ACP
ICL8017MTW
LM301AN
CA082E
TL082CP
ICL8069CCZR
LM385BZ-1.2
CA084AE
TL084ACN
ICL8069DCZR
CA084E
TL084CN
IP33063N
MC33063AP1
LM385BZ-1.2
CA1391E
MC1391P
IP34060AN
MC34060AP
CA1458S
MC1458CP1
IP34063N
MC34063AP1
CA239AE
LM239AN
IP3525AN
SG3525AN
CA239E
LM239N
IP3526N
SG3526N
SG3527AN
CA3026
CA3054
IP3527AN
CA3045F
MC3346P
LM240LAZ-18
MC78L18ACP
CA3046
MC3346P
LM240LAZ-24
MC78L24ACP
CA3054
CA3054
LM240LAZ-5.0
MC78L05ACP
LM240LAZ--6.0
MC78L05ACP
CA3059
CA3059
LM240LAZ--8.0
MC78L08ACP
CA3079
CA3079
LM249N
CA3058
CA3059
MC4741CP
CA3086F
MC3346P
LM2575
LM2575
CA3136A
MC3346P
LM258D
LM258D
CA3146
MC3346P
LM258M
LM258D
CA339AE
LM339AN
LM258N
LM258N
CA339E
LM339N
LM285Z-1.2
LM285Z-1.2
CA723CE
MC1723CP
LM285Z-2.5
LM285Z-2.5
CA741CS
MC1741CP1
LM2901D
LM2901D
CS2842AD
UC2842BD1
LM2901M
LM2901D
CS2843AD
UC2843BD1
LM2901N
LM2901N
CS2844D
UC2844BD1
LM2902D
LM2902D
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-7
II
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacement
P~~'l.l'~~ber
Motorola Nearest
Replacement
IP494ACJ
TL5941N
LM2903N
LM2903N
IP494ACN
TL594CN
LM2903P
LM2903N
IR3M03A
MC34063APl
LM2904M
LM2904D
IR3M03AN
MC34063AD
LM2904N
LM2904N
ITT371 0
MC1391P
LM2905N
ITT656
L144AP
L203
LM2931AD-S,0
MC1413P
LM324N
MC1413P
L387
MC33267T
Motorola Similar
Replacement
MC1455Pl
LM2931 AD-5.0
LM2931AT-5.0
LM2931 AT-5,0
LM2931AZ-5.0
LM2931AZ-5.0
LM2931CD
LM2931CD
LF347BN
LF347BN
LM2931CM
LM2931CD
LF347N
LF347N
LM2931CT
LM2931CT
LM2931D-5.0
LM2931 D-5,0
LF351N
LF351N
LM2931D
LM2931D-5,0
LF353AN
MC34002AP
LM2931T-5.0
LM2931T-5.0
LF353BN
MC34002BP
LM2931Z-5.0
LM2931Z-5,0
LF353D
LF353D
LM2935T
LM2935T
LF353N
LF353N
LM293D
LM293D
LF411CD
LF411CD
LM301AD
LM301AD
LF412CD
LF412CD
LM301AM
LM301AD
LF441CD
LF441 CD
LM301AN
LM301AN
LF441CN
LF441CN
LM301AP
LM301AN
LF442CD
LF442CD
LM3045
MC3346P
LF442CN
LF442CN
LM3046N
MC3346P
LF444CD
LF444CD
LM3054
CA3054
LF351BN
MC34001BP
LF444CN
LF444CN
LM30BAD
LM308AD
LMllCLN
LMllCLN
LM30BAN
LM308AN
LMllCN
LMllCN
LM30BP
LM139N
MC1391P
LM311D
LM311D
LM1489AN
MC1489AP
LM311M
LM311D
LM1489N
MC1489P
LM311N
LM311N
LM1496N
MC1496P
LM311P
LM311N
LM1496M
MC1496D
LM3146A
LM1889
MC1374P
LM3146
LM1981
MC13020P
LM317KC
MC3356P
MC3346P
MC3346P
LM317T
LM201AD
LM201AD
LM317KD
LM201AN
LM201AN
LM317LD
LM317LD
LM317LZ,
LM317LZ
LM201AP
LM201AN
LM317T
LM211D
LM211D
LM317MP.
LM211M
LM211D
LM317P
LM224D
LM224D
LM317T
LM224M
LM224D
LM3189
MC3356P
LM224N
LM224N
LM320LZ-12
MC79L12ACP
LM239AN
LM239AN
LM320LZ-15
MC79L15ACP
LM239D
LM239D
LM320LZ-5.0
MC79L05ACP
LM239M
LM239D
LM320MP-12
MC7912CT
LM239N
LM239N
LM320MP-15
MC7915CT
LM317MT
LM317T
LM317T
LM240LAZ-12
MC78L12ACP
LM320MP-18
MC7918CT
LM240LAZ-15
MC78L15ACP
LM320MP-24
MC7924CT
MC78L05ACP
LM2902M
LM2902D
LM340LAZ-5.0
LM2902N
LM2902N
LM340LAZ-£.0
LM2903D
LM2903D'
LM340T-12
LM340T:"12
LM2903M
LM2903D
LM340T-15
LM340T-15
MC78L08ACP
/I = Nol recommended for new designs,
1-8
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
P~~~~~~r
Motorola Nearest
Replacement
Motorola Similar
Replacement
P~~~~~~
Motorola Nearest
Replacement
Motorola Similar
Replacement
LM320MP-5.0
MC790SCT
LM348D
LM348D
LM320MP-5.2
MC790S.2CT
LM348M
LM348D
LM320MP-6.0
MC7906CT
LM349N
LM320MP-8.0
MC7908CT
LM350T
LM320T-12
MC7912CT
LM358AN
LM320T-15
MC7915CT
LM358D
LM358D
LM320T-5.0
MC7905CT
LM358N
LM3S8N
LM320T-5.2
MC7905.2CT
LM363AN
MC3450P#
LM322N
MC145SPI
LM363N
MC34S0P#
MC4741CP
LM3S0T
LM358N
LM323AT
LM323AT
LM3858Z-1.2
LM323T
LM323T
LM385BZ-2.5
LM3858Z-2.S
LM324AD
LM324AD
LM38SD-l.2
LM38SD-l.2
LM324AN
LM324AN
LM385D-2.S
LM385D-2.5
LM324D
LM324D
LM385M-l.2
LM385D-l.2
LM324M
LM324D
LM38SM-2.S
LM38SD-2.S
LM324N
LM324N
LM385Z-1.2
LM38SZ-1.2
LM385Z-2.S
LM385Z-2.S
LM337MP
LM337MT
LM38S8Z-1.2
LM337MT
LM337MT
LM386N
MC34119P
LM337T
LM337T
LM3905N
MC14SSPI
LM339AD
LM339AD
LM393AN
LM393AN
LM339AM
LM339AD
LM393D
LM393D
LM339AN
LM339AN
LM393JG
LM339D
LM339D
LM393M
LM339N
LM339N
LM339P
LM339N
LM393N
LM393D
LM393N
LM393N
LM431ACZ
TL431 ACLP
TL431ACD
LM340AT-12
LM340AT-12
LM431ACM
LM340AT-15
LM340AT-15
LM42S0CN
LM340AT-5.0
LM340AT-S.O
LMSSSCN
MC14SSPI
LM340KC-12
LM340T-12
LMSS6CN
MC34S6P
LM340KC-15
LM340T-IS
LM703LN
LM340LAZ-12
MC78L12ACP
LM723CN
LM340LAZ-18
MC78L18ACP
LM741EN
LM340LAZ-24
MC78L24ACP
LM780SCT
MCI776CPl
MC1350P
MC1723CP
MC1741CPl
MC780SCT
LM340T-18
LM340T-18
LM7812CT
MC7812CT
LM340T-24
LM340T-24
LM781SCT
MC781SCT
LM340T-5.0
LM340T-5.0
LM78LOSACZ
MC78LOSACP
LM340T-6.0
LM340T-6.0
LM78LOSCZ
MC78LOSCP
LM340T-8.0
LM340T-8.0
LM78L08ACZ
MC78L08ACP
LM78L08CZ
MC78L08CP
LM341P-12
MC78M12CT
LM341P-15
MC78M15CT
LM78L12ACZ
MC78L12ACP
LM341P-18
MC78M18CT
LM78L12CZ
MC78L12CP
LM341P-24
MC78M24CT
LM78L1SACZ
MC78L1SACP
LM341P-5.0
MC78M05CT
LM78L1SCZ
MC78L1SCP
LM341P-6.0
MC78M06CT
LM78L18ACZ
MC78L18ACP
LM341P-8.0
MC78M08CT
LM78L18CZ
MC78L18CP
LM342P-12
MC78M12CT
LM78L24ACZ
MC78L24ACP
LM342P-15
MC78M15CT
LM78L24CZ
MC78L24CP
LM342P-18
MC78M18CT
LM78MOSCP
MC78MOSCT
LM342P-24
MC78M24CT
LM78M06CP
MC78M06CT
LM342P-5.0
MC78M05CT
LM78M12CP
MC78M12CT
LM342P-6.0
MC78M06CT
LM78M1SCP
LM342P-8.0
MC78M08CT
LM790SCT
MC78M15CT
MC790SCT
It = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-9
II
II
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacemllnt
Industry
Part Number
Motorola Nearest
Replacement
LM7912CT
MC7912CT
NE550A
LM7915CT
MC7915CT
NE555D
MC1455D
Motorola Similar
Replacement
MC1723CP
LM79L05ACZ
MC79L05ACP
NE555V
MC1455P1
LM79L12ACZ
MC79L12ACP
NE556D
NE556D
LM79L15ACZ
MC78L15ACP
NE5561N
MC34060AP
LM79M05CP
MC79M05CT
NE5234D
MC33204D
LM79M12CP
MC79M12CT
NE5234P
MC33204P
LM79M15CP
MC79M15CT
OP-01P
MC1436P1
LM833D
LM833D
RC1458DN
MC1458P1
LM833N
LM833N
RC4136DP
MC3403P
LM833P
LM833N
RC4136N
MC3403P
LM837N
MC33079P
RC4558DN
MC4558CP1
LMC6482D
MC33202D
RC4558P
MC4558CP1
LMC6482P
MC33202P
RC723DB
MC1723CP
LMC6484D
MC33204D
RC741DN
MC1741CP1
LMC6484P
MC33204P
RE5VL47A
MC34164P-5
LP2950CZ-3.0
LP2950CZ-3.0
RH5RE30AA-T1
MC78LC30HT1
LP2950CZ-3.3
LP2950CZ-3.3
RH5RE33AA-T1
MC78LC33HT1
LP2950CZ-5.0
LP2950CZ-5.0
RH5RE40AA-T1
MC78LC4OHT1
LP2950ACZ-3.0
LP2950ACZ-3.0
RH5RE50AA-T1
MC78LC50HT1
LP2950ACZ-3.3
LP2950ACZ-3.3
RN5RG30AA-TR
MC78BC30NTR
LP2950ACZ-5.0
LP2950ACZ-5.0
RN5RG33AA-TR
MC78BC33NTR
LP2951CM
LP2951CD
RN5RG40AA-TR
MC78BC40NTR
LP2951ACM
LP2951ACD
RN5RG50AA-TR
MC78BC50NTR
LP2951CM-3.0
LP2951CD-3.0
RH5RH301 A-T1
MC33466H-3OJT1
LP2951CM-3.3
LP2951CD-3.3
RH5RH302B-T1
MC33466H-30LT1
LP2951 ACM-3.0
LP2951 ACD-3.0
RH5RH331A-T1
MC33466H-33JT1
LP2951 ACM-3.3
LP2951 ACD-3.3
RH5RH332B-T1
MC33466H-33LT1
LP2951CN
LP2951CN
RH5RH501 A-T1
MC33466H-50JT1
LP2951ACN
LP2951ACN
RH5RH502B-T1
MC33466H-50LT1
LP2951CN-3.0
LP2951CN-3.0
RH5RI301 B-T1
MC33463H-30KT1
LP2951CN-3.3
LP2951CN-3.3
RH5RI302B-T1
MC33463H-30LT1
LP2951 ACN-3.0
LP2951 ACN-3.0
RH5RI331 B-T1
MC33463H-33KT1
LP2951 ACN-3.3
LP2951 ACN-3.3
RH5RI332B-T1
MC33463H-33LT1
RH5R1501B-T1
MC33463H-50KT1
RH5R1502B-T1
MC33463H-50LT1
LT1083
LT1431CZ
MC34268DT
TL431BCLP
LTC699CN8
MC34064D-5
RH5RL30AA-T1
MC78FC30HT1
LTC6991N8
MC33064D-5
RH5RL33AA-T1
MC78FC33HT1
MAX809LCPA
MC34064P-5
RH5RL40AA-T1
MC78FC4OHT1
MB3759
TL494CN
RH5RL50AA-T1
MC78FC50HT1
N5558V
MC1458P1
RH5VT09AA-T1
MC33464H-09AT1
N5723A
MC1723CP
RH5VT20AA-T1
MC33464H-20AT1
N5741 A
MC1741CP1
RH5VT27AA-Tl
MC33464H-27AT1
N5741V
MC1741CP1
RH5VT30AA-Tl
MC33464H-30ATl
N8T26AB
MC8T26AP
RH5VT45AA-Tl
MC33464H-45ATl
N8T26AN
MC8T26AP
RH5VT09CA-Tl
MC33464H-09CTl
N8T26B
MC8T26AP
RH5VT20CA-Tl
MC33464H-2OCT1
N8T26N
MC8T26AP
RH5VT27CA-T1
MC33464H-27CT1
N8T97B
MC8T97P
. RH5VT30CA-T1
MC33464H-30CTl
N8T97N
MC8T97P
RH5VT45CA-Tl
MC33464H-45CTl
N8T98B
MC8T98P
RN5RL30AA-TR
MC78FC30NTR
N8T98N
MC8T98P
RN5RL33AA-TR
MC78FC33NTR
# = Not recommended for new designs.
1-10
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacement
Industry
Part Number
Motorola Nearest
Replacement
RN5RL40AA-TR
MC78FC40NTR
SG723CN
MC1723CP
RN5RL50AA-TR
MC78FC50NTR
SG741CM
MC1741CP1
RN5VD09AA-TR
MC33465N--{)9ATR
SG777CN
RN5VD20AA-TR
MC33465N-20ATR
SG7805ACP
RN5VD27 AA-TR
MC33465N-27ATR
SG7805ACR
RN5VD30AA-TR
MC33465N-30ATR
SG7805ACT
RN5VD45AA-TR
MC33465N-45ATR
SG7805CP
MC7805CT
MC7806ACT
RN5VD09CA-TR
MC33465N--{)9CTR
SG7806ACP
RN5VD20CA-TR
MC33465N-20CTR
SG7806ACR
RN5VD27CA-TR
MC33465N-27CTR
SG7806ACT
RN5VD30CA-TR
MC33465N-30CTR
SG7806CP
RN5VD45CA-TR
MC33465N-45CTR
SG7806CR
RN5VT09AA-TR
MC33464N--{)9ATR
SG7808ACP
RN5VT20AA-TR
MC33464N-20ATR
SG7808ACT
RN5VT27 AA-T4
MC33464N-27ATR
SG7808CP
RN5VT30AA-TR
MC33464N-30ATR
SG7808CR
RN5VT45AA-TR
MC33464N-45ATR
SG7812ACP
RN5VT09CA-TR
MC33464N--{)9CTR
SG7812ACR
RN5VT20CA-TR
MC33464N-20CTR
SG7812ACT
RN5VT27CA-TR
MC33464N-27CTR
SG7812CP
RN5VT30CA-TR
MC33464N-30CTR
SG7812CR
RN5VT45CA-TR
MC33464N-45CTR
SG7815ACP
S-S0743AN
SA555N
MC34164P-3
MC1455BP1
SAA1042
SAA1042V
SG7815CP
MC1496P
SG7815CT
SG1596J
MC1496BP
SG7818ACP
SG201AM
LM201AN
SG301AM
LM201AN
SG308AM
LM201AN
MC1723CP
LM301AN
LM308AN
MC7812ACT
MC7812ACT
MC7812CT
MC7812CT
MC7815ACT
MC7815CT
MC7815CT
MC7815CT
MC7818ACT
MC7818ACT
MC7818ACT
MC7818CT
MC7818CT
MC7824ACT
SG7824ACR
MC7824ACT
SG7824ACT
MC7824ACT
SG7824CP
SG7905.2CP
SG311M
LM311N
SG7905.2CR
SG317P
LM317T
SG7905.2CT
LM317T
SG7905ACP
SG324N
LM324N
SG7905ACR
SG337P
LM337T
SG7905ACT
SG337R
MC7808CT
MC7812ACT
MC7824CT
SG7824CR
LM308AN
SG317R
MC7808ACT
MC7808CT
SG7818CR
SG7824ACP
LM301AN
SG3118AM
MC7806CT
MC7808ACT
SG7818ACT
SG7818CP
LM224N
SG301AN
MC7806ACT
MC7806CT
SG7818ACR
LM201AN
SG300N
MC7806ACT
MC7815ACT
SG1496N
SG201N
MC7805ACT
MC7815ACT
SG7815CR
SG224N
MC7805ACT
SG7815ACR
MC1458P1
SG201M
LM308AN
MC7805ACT
SG7815ACT
SG1458M
SG201AN
Motorola Similar
Replacement
LM337T
SG7905CP
MC3423P1
MC7824CT
MC7905.2CT
MC7905.2CT
MC7905.2CT
MC7905ACT
MC7905ACT
MC7905ACT
MC7905CT
SG7905CR
MC7905CT
SG3525AN
SG3525AN
SG7905CT
MC7905CT
SG3526N
SG3526N
SG7908CP
SG3527AN
SG3527AN
SG7908CR
MC7908CT
SG3561
MC34261P
SG7908CT
MC7908CT
SG3423M
SG4250CM
MC1776CP1
SG7912ACP
MC7908CT
MC7912ACT
SG555CM
MC1455P1
SG7912ACR
MC7912ACT
SG556CN
MC3456P
SG7912ACT
MC7912ACT
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-11
II
Cross References (continued)
pa~dN'~t.r
SG7912CP
Motorola Nearest
II$IIlacement
Motorola Similar
Replacement
MC7912CT
p~~~~~r
Motorola Neareat
Replacement
Motorola Similar
Replacement
TA7BLOOBAP
MC7BLOBACP
SG7912CR
MC7912CT
TA7BLOOBP
MC7BLOBCP
SG7912CT
MC7912CT
TA7BL012AP
MC7BL12ACP
TA7BL012P
MC7BL12CP
MC7915ACT
TA7BL015AP
MC7BL15ACP
MC7915ACT
TA7BL015P
MC7BL15CP
TA7BL01BAP
MC7BL1BACP
SG79015ACP
MC7915ACT
SG7915ACR "
SG7915ACT
SG7915CP
MC7915CT
SG7915CR
MC7915CT
TA7BL01BP
MC7BL1BCP
SG7915CT
MC7915CT
TA7BL024AP
MC7BL24ACP
SG791BCP
MC791BCT
SN75LBCOB6
TA7BL024P
MC7BL24CP
MC34055DW
TA7BM05P
MC7BM05CT
SN75121N
MC34B 1/5P#
TA7BM06P
MC7BM06CT
SN75126N
MC34Bl/5P#
TA7BMOBP
MC7BMOBCT
SN75150N
MC14BBP'
TA7BM12P
MC7BM12CT
SN75154N
MC14B9P
TA7BM1BP
MC7BM1BCT
SN75174N
MC75174BP
TA7BM20P
MC7BM20CT
SN75175N
SN75175N
TA7BM24P
MC7BM24CT
SN751BBN
MC14BBP
TA79005P
MC7905CT
SN751B9AN
MCl4B9AP
TA79006P
MC7906CT
SN751B9N
MCl4B9P
TA7900BP
MC790BCT
SN7546BN
MC1413P
TA79012P
MC7912CT
SN76591P
MC1391P
TA79015P
MC7915CT
SN76600P
MC1350P
TA7901BP
MC791BCT
SSS201AP
LM201AN
TA79024P
MC7924CT
"
SSS301AP
LM301AN
TA79LOO5P
TA7504P
MC1741CPl
TA79L012P
MC79L05CP
MC79L12P
TA7506P
LM301AN
TA79L015P
MC79L15P
TA75071P
MC34001P
TA79L01BP
MC79L1BP
TA75072P
MC34002P
TA79L024P
MC79L24P
TA75074F
MC34004P
TB920
MC1391P
TA75339F
LM339D
TBA920S
TA75339P
LM339N
TCF5600
MC1391P
TCF5600
TA7535BCF
LM35BD
TD62003P/AP
MC1413P
TA7535BCP
LM35BN
TD62479P
MC1374P
TDA1085C
TA75393F
LM393D
TDA10B5C
TA75393P
LM393N
TDA1085
TA7545BF
MC145BD
TDA1185A
TA7545BP
MC145BCPl
TDA4817
MC34261P
TA7555BP
MC455BCPl
TDC101B
MC10324P
TA7555F
MC1455D
TDC104B
TA7555P
MC1455Pl
TKl15
TA75902F
LM324D
TA7BOO5AP
MC10319P
MC33264
TL022CP
TL4941N
TA76494P
TDA10B5C
TDA1185A#
LM35BN
TL044CJ
LM324N
MC7B05CT
TL062ACP
TL062ACP
TA7B006AP
MC7B06CT
TL062CD
TL062CD
TA7BOOBAP
MC7BOBCT
TL062CP
TL062CP
TA7BOl2AP
MC7B12CT
TL062VP
TL062VP
TA7B015AP
MC7B15CT
TL064ACD
TL064ACD
TA7B01BAP
MC7B1BCT
TL064ACN
TL064ACN
TA7B024AP
MC7B24CT
TL064CD"
TL064CD
TA7BL005AP
MC7BL05ACP
TL064CN
TL064CN
TA7BLOO5P
MC7BL05CP
TL064VN
TL064VN
# = Not recommended for new designs,
1-12
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacement
p~~dJ~~~er
Motorola Nearest
Replacement
Motorola Similar
Replacement
TL071ACD
TL071ACD
!1A4136PC
TL071ACP
TL071ACP
!1A431AWC
MC4741CP
TL071CD
TL071CD
!1A4558TC
MC4558CP1
TL071CP
TL071CP
!1A494PC
TL494CN
TL072ACD
TL072ACD
!1A555TC
MC1455P1
TL072ACP
TL072ACP
!1A556PC
MC3456P
TL072CD
TL072CD
!1A723CN
MC1723CP
TL072CP
TL072CP
!1A723PC
MC1723CP
TL074ACN
TL074ACN
!1A741CP
MC1741CP1
TL074CN
TL074CN
I1A742DC
CA3059
TL081ACD
TL081ACD
I1A757DC
MC1350P
TL081ACP
TL081ACP
I1A757DM
TL081CD
TL081CD
I1A775PC
LM339N
TL081CP
TL081CP
I1A776TC
MC1776CP1
TL082ACP
TL082ACP
!1A7805CKC
MC7805CT
TL082CD
TL082CD
!1A7805UC
MC7805CT
TL082CP
TL082CP
!1A7805UV
MC7805BT
TL084ACN
TL084ACN
!1A7806CKC
MC7806CT
TL084CN
TL084CN
!1A7806UC
MC7806CT
TL431CD
TL431CD
!1A7806UV
MC7806BT
TL431CLP
TL431CLP
!1A7808CKC
MC7808CT
TL431CP
MC1350P
TL431CP
TL431CP
!1A7808UC
MC7808CT
TL4311LP
TL4311LP
!1A7808UV
MC7808BT
TL4311P
TL4311P
11A7812CKC
MC7812CT
TL494CN
TL494CN
I1A7812UC
MC7812CT
TL4941N
TL4941N
I1A7812UV
MC7812BT
I1A781 5CKC
MC7815CT
MC34063AP1
TL497CN
TL594CN
TL594CN
I1A7815UC
MC7815CT
TL5941N
TL5941N
I1A781 5UV
MC7815BT
TL780-05CKC
TL780-05CKC
I1A7818CKC
MC7818CT
TL780-12CKC
TL780-12CKC
!1A7818UC
MC7818CT
TL780-15CKC
TL780-15CKC
!1A7818UV
MC7818BT
TL7805ACKC
MC7805ACT
I1A7824CKC
MC7824CT
TLC2272D
MC33202D
I1A7824UC
MC7824CT
TLC2272P
MC33202P
I1A7824UV
MC7824BT
TLC2274D
MC33204D
I1A78GU1C
TLC2274P
MC33204P
I1A78GUC
!1A1391PC
MC1391P
I1A78L05ACLP
!1A1458CP
MC1458CP1
I1A78L05AWC
!1A1458CTC
MC1458CP1
I1A78L05CLP
!1A1458P
MC1458P1
I1A78L05WC
!1A1458TC
MC1458P1
11A78L08ACLP
MC1455P1
!1A2240PC
!1A301AT
LM301AN
LM317T
LM317T
MC78L05ACP
MC78L05ACP
MC78L05CP
MC78L05CP
MC78L08ACP
11A78L08AWC
MC78L08ACP
11A78L08CLP
MC78L08CP
MC78L12ACP
!1A3026HM
CA3054
11A78L12ACLP
!1A3045
MC3346P
11A78L12AWC
!1A3046DC
MC3346P
!1A78L12CLP
!1A3054DC
CA3054
!1A78L12WC
!1A311T
LM311N
!1A78L15ACLP
I1A317UC
LM317T
I1A78L15AWC
I1A3303P
MC3303P
I1A78L15CLP
I1A3403P
MC3403P
I1A78L15WC
MC78L12ACP
MC78L12CP
MC78L12CP
MC78L15ACP
MC78L15ACP
MC78L15CP
MC78L15CP
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-13
•
•
Cross References (continued)
p~~t'~~~
Motorola Naarast
Replacement
Motorola Similar
Replacament
p~~d~~~er
Motorola Nearest
Replacement
Motorola Similar
Replacement
~79M06AUC
MC79M06CT
J,lA78L24AWC
MC78L24ACP
~79M06CKC
MC79M06CT
J,lA78M05CKC
MC78M05CT
~79M06UC
MC79M06CT
~79M08AUC
MC79M08CT
MC79M08CT
J,lA78L18AWC
MC78L18ACP
J,lA78M05CKD
MC78M05CT
IlA78M05UC
MC78M05CT
~79M08CKC
J,lA78M06CKC
MC78M06CT
~79M08UC
IlA78M06CKD
MC78M06CT
MC79M08CT
~79M12AUC
MC79M12CT
MC79M12CT
IlA78M06UC
MC78M06CT
~79M12CKC
IlA78M08CKC
MC78M08CT
I1A79M18AUC
MC79M18CT
~79M18UC
MC79M18CT
MC78M08CT
IlA78M08CKD
J,lA78M08UC
MC78M08CT
~79M24AUC
MC79M24CT
J,lA78M12CKC
MC78M12CT
~79M24CKC
MC79M24CT
J,lA78M12CKD
MC78M12CT
J,lA78M12UC
MC78M12CT
J,IA78M 15CKC
MC78M15CT
~78M15CKD
MC78M15CT
~79M24UC
MC79M24CT
~9636ATC
MC3488AP1
UAA1016B
UAA1016B
UC2823DW
MC33023DW
~78M15UC
MC78M15CT
UC2823N
MC33023P
~78M18UC
MC78M18CT
UC2823Q
MC33023FN
~78M20CKC
MC78M20CT
UC2825DW
MC33025DW
~78M20CKD
MC78M20CT
~78M20UC
MC78M20CT
~78M24CKC
MC78M24CT
~78M24CKD
IlA78M24UC
UC2825N
MC33025P
UC28250
MC33025FN
UC2842AD
MC78M24CT
MC78M24CT
UC2842AD
UC2842AN
UC2842AN
UC2842BD
UC2842BD
~78MGT2C
LM317T
UC2842BN
UC2842BN
~78MGU1C
LM317T
UC2842D
UC2842AD
UC2842N
UC2842AN
~78MGUC
LM317MT
~78S40PC
~78S40PC
UC2843AD
UC2843AD
~78S40PV
~78S40PV
UC2843AN
UC2843AN
~7905.2CKC
MC7905.2CT
UC2843BD
UC2843BD
~7905CKC
MC7905CT
UC2843BN
UC2843BN
~7905UC
MC7905CT
UC2843D
UC2843AD
~7906CKC
MC7906CT
UC2843N
UC2843AN
~7906UC
MC7906CT
UC2844BD
UC2844BD
~7908CKC
MC7908CT
UC2844BN
UC2844BN
~7912CKC
MC7912CT
UC2844D
UC2844D
~7912UC
MC7912CT
UC2844N
UC2844N
~7915CKC
MC7915CT
UC2845BD
UC2845BD
~7915UC
MC7915CT
UC2845BN
UC2845BN
~7918CKC
MC7918CT
UC2845D
UC2845D
~7918UC
MC7918CT
UC2845N
UC2845N
I1A7924CKC
MC7924CT
UC317T
LM317T
I1A7924UC
MC7924CT
UC337T
LM337T
~798TC
MC3458P1
UC3525AN
SG3525AN
~79L05AWC
MC79L05ACP
UC3526N
SG3526N
~79L05WC
MC79L05CP
UC3527AN
SG3527AN
~79L12AWC
MC79L12ACP
UC3823DW
MC34023DW
~79L12WC
MC79L12CP
UC3823N
MC34023P
~79L15AWC
MC79L15ACP
UC3823Q
MC34023FN
~79L15WC
MC79L15CP
UC3825DW
MC34025DW
11A79M05AUC
MC79M05CT
UC3825N
MC34025P
11A79M05CKC
MC79M05CT
UC38250
MC34025FN
# = Not recommended for new designs.
1-14
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
P~~~~~?:er
Motorola Nearest
Replacement
Motorola Similar
Replacement
p~~~~~?:er
Motorola Nearest
Replacement
UC3842AD
UC3842AD
UC3845N
UC3842AN
UC3842AN
UC494ACN
UC3842BD
UC3842BD
UC494CN
UC3842BN
UC3842BN
UCN5816A
MC34142FN
UC3842D
UC3842AD
ULN2003A
MC1413
UC3842N
UC3842AN
ULN2004A
MC1416
UC3843AD
UC3843AD
ULN2068BB
ULN2068B#
UC3843AN
UC3843AN
ULN2068NE
ULN2068B#
UC3843BD
UC3843BD
ULN2151H
MC1741CP1
UC3843BN
UC3843BN
ULN2151M
UC3843D
UC3843AD
ULN2803A
Motorola Similar
Replacement
UC3845N
TL594CN
TL494CN
MC1741CP1
ULN2803A
UC3843N
UC3843AN
ULN2804A
ULN2804A
UC3844BD
UC3844BD
ULN8126A
SG3526N
UC3844BN
UC3844BN
ULS2151M
MC1741CP1
UC3844D
UC3844D
ULX8161M
MC34060AP
UC3844N
UC3844N
UPD6950C
MC10319P
UC3845BD
UC3845BD
UVC3101
MC10319P
UC3845BN
UC3845BN
XR082CP
TL082CP
UC3845D
UC3845D
XR084CP
TL084CN
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-15
•
1-16
MOTOROLA ANALOG IC DEVICE DATA
Voltage References
In Brief ...
Motorola's line of precIsion voltage references is
designed for applications requiring high initial accuracy, low
temperature drift, and long term stability. Initial accuracies of
±1.0%, and ±2.0% mean production line adjustments can be
eliminated. Temperature coefficients of 25 ppm/DC max
(typically 10 ppm/DC) provide excellent stability. Uses for the
references include D/A converters, AID converters,
precision power supplies, voltmeter systems, temperature
monitors, and many others.
MOTOROLA ANALOG IC DEVICE DATA
Page
Precision Low Voltage References . . . . . . . . . . . . . . . . . . 5-2
Package Overview ............................... 5-2
Device Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
5-1
•
i
i
Precision Low Voltage References
A family of precision low voltage bandgap reference devices designed for applications requiring low temperature drift.
1Precision Low Voltage References
Vout
(V)
10
Voutff
(rnA)
Typ
Max
pprnfOC
Max
1.235± 12mV
1.235±25 mV
20
80Typ
Regllne
(mV)
Regloed
(mV)
0° to +70°C
-400 to +85°C
Max
Max
Package
LM385BZ-1.2
LM385Z-1.2
LM285Z-1.2
(Note 1)
1.0
(Note 2)
Z,D
LM385BZ-2.5
LM385Z-2.5
LM285Z-2.5
25
MC1403A
-
40
MC1403
5.0±50mV
40
MC1404P5
-
6.25±60mV
40
MC1404P6
-
10±100mV
40
MC1404P10
-
50Typ
TL431C, AC, BC
TL431I, AI, BI
2.5±38mV
2.5±75mV
2.5±25mV
II
Device
2.5 to 37
10
100
2.0
(Nole3)
3.0/4.5
(Note 4)
10
(Note 5)
D
6.0
(Note 6)
P
Shunt Reference
Dynamic Impedance
(z)':;0.5a
LP, P, D, DM
Notes: 1. Mlcropower Reference DIode DynamIc Impedance (z) S 1.0 II at IR = 100 IIA.
2.10 IIA S IR S 1.0 mA.
3.20 lIAS IR S 1.0mA.
4.4.5 Vs Yin S 15 Vl15 V s Vln S 40 V.
5. OmAs ILs 10 mAo
6. (Vout + 2.5 V) s vin S 40 V.
Voltage References Package Overview
I
CASE 29
LP,ZSUFFIX
5-2
~
CASE 626
PSUFFIX
~
•
CASE 751
o SUFFIX
CASE846A
OM SUFFIX
MOTOROLA ANALOG IC DEVICE DATA
Device Listing
Voltage References
Device
Function
Page
LM285, LM385, B
MC1403, B
MC1404
TL431 , A, B Series
Micropower Voltage Reference Diodes .............................. 5-4
Low Voltage Reference ............................................ 5-9
Voltage Reference Family ........................................ 5-13
Programmable Precision References .............................. 5-18
II
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
LM285
LM385,B
Micropower Voltage
Reference Diodes
11
The LM285/LM385 series are micropower two-terminal bandgap voltage
regulator diodes. Designed to operate over a wide current range of 10 !lA to
20 mA, these devices feature exceptionally low dynamic impedance, low
noise and stable operation over time and temperature. Tight voltage
tolerances are achieved by on-chip trimming. The large dynamic operating
range enables these devices to be used in applications with widely varying
supplies with excellent regulation. Extremely low operating current make
these devices ideal for micropower circuitry like portable instrumentation,
regulators and other analog circuitry where extended battery life is required.
The LM285/LM385 series are packaged in a low cost T0-226AA plastic
case and are available in two voltage versions of 1.235 and 2.500 V as
denoted by the device suffix (see Ordering Information table). The LM285 is
specified over a -40°C to +85°C temperature range while the LM385 is rated
from O°C to +70°C.
The LM385 is also available in a surface mount plastic package in
voltages of 1.235 and 2.500 V.
• Operating Current from 10 !lA to 20 rnA
• 1.0%, 1.5%, 2.0% and 3.0% Initial Tolerance Grades
MICROPOWER VOLTAGE
REFERENCE DIODES
SEMICONDUCTOR
TECHNICAL DATA
ZSUFFIX
PLASTIC PACKAG/
CASE 29
(Bottom View)
c:w
3
~21
N.C.
Cathode
Anode
OJ
DSUFFIX
PLASTIC PACKAGE
• Low Temperature Coefficient
CASE
751
(S0-8)
• 1.0 Q Dynamic Impedance
• Surface Mount Package Available
N C. 1
8 Cathode
NC 2
7 N.C.
N.C 3
6 NC
Anode 4
5 N.C.
~
Standard Application
1.SV
Battery
i-
+
Representative Schematic Diagram
'V
~
Open
f' for 1.235 V
~
/.
j..
600k
fa.
8.45k r,.-"
~
-==
10k
ORDERING INFORMATION
~
>~
~~
r--..
~
r--<
~
Device
LM285D-1.2
LM285Z-1.2
~
v
74.3k
Open
for 2.5 V
>-I
600 k
425 k
L
LM285D-2.5
LM285Z-2.5
~
~1.235V
'] ~ lM385-1.2
Cathode
360 k
3.3 k
600k
~[ v
r 1 1
o
v
""hi.
>--
~
soon
100k
>t:
Reverse
Operating
BreakTemperature down
Range
Voltage Tolerance
TA = -40° to
+85°C
LM385BD-1.2
LM385BZ-1.2
LM385D-1.2
LM385Z-1.2
LM385BD-2.5
LM385BZ-2.5
LM385D-2.5
LM385Z-2.5
TA=OOto
+70°C
1.235 V
±1.0%
2.500 V
±1.5%
1.235 V
±1.0%
1.235 V
±2.0%
2.500 V
±1.5%
2.500 V
±3.0%
Anode
5-4
MOTOROLA ANALOG IC DEVICE DATA
LM285 LM385, B
MAXIMUM RATINGS (TA = 25'C, unless otherwise noted)
Rating
Symbol
Value
Unit
IR
30
mA
Forward Current
IF
10
mA
Operating Ambient Temperature Range
LM285
LM385
TA
Reverse Current
Operating Junction Temperature
Storage Temperature Range
'c
-40to+85
Oto +70
TJ
+ 150
'c
Tstg
- 65 to + 150
°C
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted)
LM2S5-1.2
Characteristic
Reverse Breakdown Voltage (IRmin .;; IR .;; 20 mAl
LM285-1 .2ILM385B-l.2
TA = Tlow to Thigh (Note 1)
LM385-1.2
TA = Tlowto Thigh (Note 1)
Minimum Operating Current
TA=25°C
TA = Tlowto Thigh (Note 1)
Reverse Breakdown Voltage Change with Current
IRmin .;; IR ~ 1.0 mA, TA = +25'C
TA = Tlow to Thigh (Note 1)
1.0 mA ~ IR ~ 20 rnA, TA = +25°C
TA = Tlow to Thigh (Note 1)
Reverse Dynamic Impedance
IR = 100 !lA, TA = +25°C
Average Temperature Coefficient
10 I1A ~ IR ~ 20 mA, TA = Tlow to Thigh (Note 1)
Wideband Noise (RMS)
IR=I00!lA, 10Hz ~ f
~
Symbol
LM3S5-1.21LM385B-1.2
Min
Typ
Max
Min
Typ
Max
1.223
1.200
1.235
1.247
1.270
1.235
-
1.223
1.210
1.205
1.192
1.247
1.260
1.260
1.273
-
8.0
-
V
V(BR)R
IRmin
dV(BR)R
Unit
-
-
-
-
8.0
-
-
10
20
-
-
1.0
1.5
10
20
-
-
-
-
1.0
1.5
20
25
0.6
-
-
0.6
-
W
-
Z
-
1.235
-
!lA
-
15
20
mV
dV(BR)/dT
-
80
-
-
80
-
ppm/'C
n
-
60
-
-
60
-
I1V
S
-
20
-
-
20
-
ppm!
kHR
10kHz
Long Term Stability
IR = 100 !lA, TA = +25'C ± O.I'C
MOTOROLA ANALOG IC DEVICE DATA
II
LM285 LM385, B
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
LM285-2.5
Characteristic
Reverse Breakdown Voltage (IRmin '" IR '" 20 rnA)
LM285-2.51LM385B-2.5
TA = Tlowto Thigh (Note 1)
LM385-2.5
TA = Tlow to Thigh (Note 1)
Minimum Operating Current
TA = 25°C
TA = Tlow to ThiJ;lh (Note 1)
Reverse Breakdown Voltage Change with Current
II
Symbol
Typ
Max
Min
Typ
Max
2.462
2.415
2.5
2.538
2.585
2.5
-
2.462
2.436
2.425
2.400
-
2.538
2.564
2.575
2.600
20
30
-
13
20
-
30
-
1.0
1.5
10
20
-
-
2.0
2.5
20
25
0.6
-
-
0.6
-
W
Unit
V
V(BR)R
-
-
2.5
IRmin
-
13
-
-
-
aV(BR)R
IRmin '" IR '" 1.0 mA, TA = +25°C
TA = Tlow to Thigh (Note 1)
1.0 mA '" IR '" 20 mA, TA = +25°C
TA = Tlow to Thigh (Note 1)
Reverse Dynamic Impedance
IR = 100 ItA, TA = +25°C
LM385-2.51LM385B-2.5
Min
Z
-
J!A
mV
aV(BRyaT
-
80
-
-
80
-
ppm/°C
Wideband Noise (RMS)
IR=lOOI1A, 10Hz", f '" 10kHz
n
-
120
-
-
120
-
I1V
Long Term Stability
IR = 100 I1A, TA = +25°C ± O.l°C
S
-
20
-
-
20
-
Average Temperature Coefficient
20 ItA '" IR '" 20mA, TA = Tlow to Thigh (Note 1)
NOTES: 1. TJow = - 40°C for LM285-1.2, LM285-2.5
=O°C for LM385-1.2, LM385B-1.2, LM385-2.5, LM385B-2.5
ppm/
kHR
.
Thigh = +85°C for LM285-1.2, LM285-2.5
= +70°C for LM385-1.2, LM385B-1.2, LM385-2.5, LM385B-2.5
MOTOROLA ANALOG IC DEVICE DATA
LM285 LM385, B
TYPICAL PERFORMANCE CURVES FOR LM28!i-1.2/38S-1.21385B-1.2
Figure 1. Reverse Characteristics
Figure 2. Reverse Characteristics
~
100
UJ
(!)
«
z
c(
6
:J:
I-
Z
w
a::
a::
0
10
UJ
(!)
~
::>
0
w
CJ)
a::
w
>
w
a::
10
1111111
8.0
TA = + 85'C
IIIIIII
TA=+85~
1.0
!f.
+ 25'C.I'
0.1
o
0.4
~
0.6
0.8
~40'C
~;;;i
a:@.
.I' -40'C
1'1
0.2
ViI
+25'C
>
UJ
en 4.0
a::
UJ
>
2.0
UJ
a::
ci:
~ ~
lJ
I'j I
6.0
0
1.0
1.2
-2.0
1.4
0.01
0.1
V(BR), REVERSE VOLTAGE (V)
1.0
10
100
IR, REVERSE CURRENT (rnA)
Figure 3. Forward Characteristics
Figure 4. Temperature Drift
1.250
~
w
(!)
;:!:
:..J
~
1.2
~
w 1.240
0
a::
c(
0.6
12
~~C
0.4
r--
~
u:
>
0.2
_f-
o
0.01
~
~
TA=-4~
0.8
t::::ft
~
UJ
CJ)
a::
UJ
>
UJ
a::
~'C
r--
1.230
ci: 1.220
a:-
ID
:>
1.210
0.1
1.0
10
100
-50
-25
Figure 5. Noise Voltage
-
625
1.50
1.25
.....
~
50
75
~
1.00
~
0.75
~r....
/
125
Output
o 0.50
\
0.25
!!l
~ 375
c::
100
'~
)
:::>
W 500
CD
25
Figure 6. Response Time
875
750
0
TA, AMBIENTTEMPERATURE ('C)
IF ' FORWARD CURRENT (mA)
~
IR=100f,IA
-
(!)
1.0
DUT
""'~
\
250
~
'\1'.
125
o
10
'3
"~
100
1.0K
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
10K
lOOk
10
5.0
o
0.1
0.2
0.3
0.6
0.7
0.8
0.9
1.0
1.1
t, TIME (ms)
5-7
II
LM285 LM385, B
TYPICAL PERFORMANCE CURVES FOR LM285-2,5/385-2.S/385B-2.S
Figure 7. Reverse Characteristics
Figure 8. Reverse Characteristics
:[
100
w
:z
<.!:I
«
w
10
1111111
8.0
TA = +85°C
!:j
. TA +85~
"/
f= = +25°C
40°C
o
0.5
>
w
4.0
w
>
w
cc
2.0
c:
~
~:::
0
1.0
1.5
2.0
2.5
V(SR), REVERSE VOLTAGE (V)
3.0
3.5
0.01
0.1
Figure 9. Forward Characteristics
~
w
2.520
~
w 2.510
~
0.2
o
0.01
t:t::
1-11-1-
...
~
~
w
en 2.490
cc
w
2.480
iri
cc
c: 2.470
~ 2.460
I'
'2.450
1.0
10
IF ' FORWARD CURRENT (mA)
-
1500
~1250
>:
100
-{i0
-25
0
25
50
75
TA, AMBIENTTEMPERATURE ('C)
~
.....
en
J
~
c::
500
250
10
\
t,
1.0K
FREQUENCY (Hz)
10K
.....
o
'\~
~
~
~
100
125
lOOk
');'
Output
0.50
Q)
5-8
2.00
~ 1.50
/".
51.00
750
·100
Figure 12. Response Time
3.00
2.50
~1000
o
100.
cc
+25°C
0.1
-r--
2.500
§:!
V-,I
+85°C
I-
100
IR = 100 IlA
Figure 11. Noise Voltage
~
1.0
10
IR, REVERSE CURRENT (rnA)
Figure 10. Temperature Drift
1.2
<.!:I
~-40°C
+25°C
~
:;; -2.0
I
0.1
6.0
0
en
cc
,
~
i'il
<.!:I
1.0
II
10
1111111
:t:
U
--
DUT
10
5.0
o
0.1
0.2
0.3 0.6 0.7
t,TIME(ms)
0.8
0.9
1.0
1.1
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC1403, B
Low Voltage Reference
A precision band-gap voltage reference designed for critical
instrumentation and DJA converter applications. This unit is designed to work
with DJA converters, up to 12 bits in accuracy, or as a reference for power
supply applications.
PRECISION LOW VOLTAGE
REFERENCE
SEMICONDUCTOR
TECHNICAL DATA
• Output Voltage: 2.5 V ±25 mV
• Input Voltage Range: 4.5 V to 40 V
.~
• Quiescent Current: 1.2 mA Typical
• Output Current: 10 mA
• Temperature Coefficient: 10 ppmJoC Typical
1
• Guaranteed Temperature Drift Specification
• Equivalent to AD580
8~
• Standard 8-Pin DIP, and 8-Pin SOIC Package
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
II
o SUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
1
Typical Applications
• Voltage Reference for 8 to 12 Bit DJA Converters
PIN CONNECTIONS
• Low T C Zener Replacement
• High Stability Current Reference
NC
• Voltmeter System Reference
NC
NC
MAXIMUM RATINGS (TA ~ 25°C, unless otherwise noted.)
Rating
Symbol
Value
Unit
V
Input Voltage
NC
VI
40
Storage Temperature
Tstg
-65 to 150
°C
Junction Temperature
TJ
+175
°C
Device
Operating Ambient Temperature Range
MC1403B
MC1403
TA
°C
°C
MC1403D
MC1403P1
MC1403BD
MC1403BP1
-40 to +85
Oto+70
ORDERING INFORMATION
Operating
Temperature Range
TA~00to+70°C
TA ~ -40° to +85°C
Package
S0-8
Plastic DIP
S0-8
Plastic DIP
Figure 1. A Reference for Monolithic D/A Converters
r-------------------,
Full Scale
Adjust 500 Q
+5.0V 0----'-1
I
~+_~~--~~+_~r__T_4
'----,-----'
Monolithic D/A
I
Converter
~--~~
~k
Providing the Reference Current
for Motorola Monolithic D/A Converters
The MC1403 makes an ideal reference for many monolithic D/A converters, requiring a stable current reference of
nominally 2.0 rnA. This can be easily obtained from the
MC1403 with the addition of a series resistor, R1 . A variable
resistor, R2, is recommended to provide means for fullscale adjust on the D/A converter.
MOTOROLA ANALOG IC DEVICE DATA
L __________________
I
I
I
I
I
~
• Caution: System stability may be affected if output capacitance
exceeds 1.0 ~F. Using higher capacitance values is not
recommended and should be carefully considered.
The resistor R3 improves temperature performance by
matching the impedance on both inputs olthe D/A reference
amplifier. The capacitor decouples any noise present on the
reference line. It is essential if the D/A converter is located
any appreciable distance from the reference.
A single MC1403 reference can provide the required
current input for up to five of the monolithic D/A converters.
5-9
MC1403, B
ELECTRICAL CHARACTERISTICS (Vin = 15 V, TA = 25'C, unless O1herwise noted.)
Characteristic
Output VoHage
(IO=OmA)
Temperature Coefficient of Output VoHage'
MC1403
Output Voltage Change'
(Over specified temperature range)
MC1403
Oto +70'C
MC1403B -40to+85'C
Line Regulation (10 = 0 mAl
(15V", VI'" 40 V)
Symbol
Min
Typ
Max
Unit
Vout
2.475
2.5
2.525
V
!No/AT
-
10
40
ppm/'C
-
-
7.0
12.5
1.2
0.6
4.5
3.0
Regload
-
-
10
mV
IQ
-
1.2
1.5
mA
Regline
(4.5 V '" VI '" 15V)
II
Load Regulation
(OmA<10<10mA)
Quiescent Current
(10'= 0 mA)
mV
AVO
mV
'This test is not applicable to the MC1403D or MC1403BD surface mount devices.
Figure 2. MC1403, B Schematic
32
L---+--o
Vou!
1.5 k
1.483 k
This device contains 15 active transistors.
5-10
MOTOROLA ANALOG IC DEVICE DATA
MC1403, B
Figure 4. Change in Output Voltage
versus Load Current
(Normalized to Vout @ Vin = 15 V, lout = 0 mAl
Figure 3. Typical Change in Vout versus Vin
(Normalized to Vin
:i
=15 V @ TC =25'C)
2.0
~
1.0
W 9.0
(!J
'§
> -1.0
~
~ -2.0
--
I""""
~
~
25'C
10
;5 8.0
g 7.0
I
O'C- r---
~
6.0
o~
75'C- r---
--3.0
w
~
5.0
4.0
Ji --4.0
(!J
3.0
u
2.0
~
~
>0
-6.0
o
10
20
0
± 6%
• Wide Input Voltage Range: Vref + 2.5 V to 40 V
• Low Quiescent Current: 1.25 mA Typical
• Temperature Coefficient: 10 ppm/oC Typical
• Low Output Noise: 121lV p-p Typical
• Excellent Ripple Rejection: > 80 dB Typical
.~
Typical Applications
• Voltage Reference for 8 to 12 Bit 01A Converters
1
• Low T C Zener Replacement
• High Stability Current Reference
• MPU D/A and AID Applications
PSUFFIX
PLASTIC PACKAGE
CASE 626
Figure 1. Voltage Output 8-Bit DAC Using MC1404P10
PIN CONNECTIONS
+5.0
5.0 k
6
Ref I--'VVI~-,.--.......:"-I
In
MSB
+15
2
MC1404P10
4
BBit
DAC
Digital
Inputs
75pF
5.0k
Out 1------+""-1
ORDERING INFORMATION
Oto
+10V
LSB
Device
-15
MC1404P5
MC1404P6
MC1404P10
MOTOROLA ANALOG IC DEVICE DATA
Operating
Temperature Range
Package
Plastic DIP
TA = 0° to +70°C
Plastic DIP
Plastic DIP
5-13
MC1404
MAXIMUM RATINGS
Rating
Input Voltage
Symbol
Value
Unit
V
Vin
40
Storage Temperature
Tstg
-65to+150
°C
Junction Temperature
TJ
+175
°C
Operating Ambient Temperature Range
TA
Oto+70
°C
ELECTRICAL CHARACTERISTICS (Vin = 15 V, TA = 25°C, and Trim Terminal not connected, unless otherwise noted.)
Characteristic
Output VoHage
(10=0 rnA)
II
Symbol
Min
Typ
Max
4.95
6.19
9.9
5.0
6.25
10
5.05
6.31
10.1
MC1404P5
MC1404P6
MC1404P10
Unit
V
Vo
-
-
±0.1
±1.0
%
Output Trim Range (Figure 10)
(Rp= 100kQ)
AVTRIM
±6.0
-
-
%
Output Voltage Temperature Coefficient,
Over Full Temperature Range
AVo/AT
-
10
40
ppmfOC
-
-
Output Voltage Tolerance
Maximum Output Voltage Change
Over Temperature Range
mV
AVO
-
14
17.5
28
Line Regulation (Note 1)
(Vin = Vout + 2.5 V to 40 V, lout = 0 rnA)
Regline
-
2.0
6.0
mV
Load Regulation (Note 1)
(0", 10" 10 rnA)
Regload
-
-
10
mV
Quiescent Current
(lo=omA)
IQ
-
1.2
1.5
rnA
Short Circuit Current
Isc
-
20
45
rnA
-
-
25
-
ppm/1000 hrs
Long Term Stability
MC1404P5
MC1404P6
MC1404P10
-
-
-
NOTE: 1. Includes thermal effects.
DYNAMIC CHARACTERISTICS (Vin = 15 V, TA = 25°C, all voltage ranges, unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Turn-On Settling Time
(to±0.01%)
ts
-
50
-
J.IS
Output Noise Voltage - P to P
(Bandwidth 0.1 to 10 Hz)
Vn
-
12
-
IlV
Small-Signal Output Impedance
120 Hz
500 Hz
ro
-
0.15
0.2
-
70
80
-
Characteristic
Power Supply Rejection Ratio
5-14
PSRR
n
dB
MOTOROLA ANALOG IC DEVICE DATA
MC1404
TYPICAL CHARACTERISTICS
Figure 2. Simplified Device Diagram
2
Figure 3. Line Regulation versus Temperature
2.5
Yin
:;;g 2.0
:z
~ 1.5
6
R
w
a:
w 1.0
:z
TRIM
VTEMP
3
::;
5
3.75k
Vo
5.0V
5.0k
6.25 V
8.75k
10V
Yin = Vret +2.5 V to 40 V
lout = 0 rnA
(!)
5.0 k
R
~
~
Vou!
+
5
~o 0.5
o
1.25k
o
10
20
~
40
50
70
60
TA, AMBIENT TEMPERATURE ('C)
4
Figure 4. Output Voltage versus Temperature
MC1404P10
Figure 5. Load Regulation versus Temperature
0.010
10.04
~
w
(!)
~ 0.008
10.02
~
~ 10.00
~
~
9.98
Load Change 0 to lOrnA
§ 9.96
S
>0
9.94
::]
0
o
20
~
40
50
TA, AMBIENT TEMPERATURE ('C)
10
60
o
70
Figure 6. Power Supply Rejection Ratio
versus Frequency
10
~
Ml
::;
:t
iil
ffi
70
60
~ ~
~
~
"
O.II1F
l~
rf
'V
1.0k
1.4
!z
w
1.2
a:
a:
'"
:z
(.)
I-
60
70
1.0
0.8
w
HP209A
3.0 Vons 5~~
~
«
.s
i""
40
20
30
40
50
TA, AMBIENTTEMPERATURE ('C)
1.6
80
50
10
Figure 7. Quiescent Current versus Temperature
~ 90
~
o
(.)
en
w
5
~
12
: (21.3 v Set No!e to D 4
~
20 V Average
6
i""
HP3400A
Vin= 15 V
10ut=0 rnA
0.6
0
0.4
.9
0.2
~
20
0.Q1
0.1
1.0
10
t, FREQUENCY (kHz)
MOTOROLA ANALOG IC DEVICE DATA
100
1000
o
o
10
20
30
40
50
TA, AMBIENT TEMPERATURE ('C)
60
70
5-15
II
MC1404
Figure 8. Short Circuit Current
versus Temperature
Figure 9. VTEMP Output versus Temperature
40
1.0
~
t=>
a.
t=>
1 35
~
~
30
Vin= 15V
=> 25
u
0.8
0
UI
a:
=>
!::::
0.6
~
=> 20
~
C3 IS
UI
a.
::;;;
0.4
UI
..
Ii:
f-;,
a.
~ 10
10
20
30
40
50
TA, AMBIENT TEMPERATURE (OC)
o
o
70
60
Figure 10. Output Trim Configuration
10
Va
MCI404
70
r-----------~--_oV+
330
6
Output
?
5
TRIM
Gnd
Rp
100 k
5.0,6.25,
IOV@I/2Amp
6
Va 1-"------_-0
,.----,-.=-2--, O.OIIlF
14
-1..
60
Figure 11. Precision Supply Using MC1404
+15V
j2
Yin
20
30
40
50
TA, AMBIENTTEMPERATURE (OC)
Yin
MCI404
Output Adjustment
The MCI404 trim terminal can be used to adjuslthe output vonage
over a ±6.0% range. For example, the output can be selto 10.000 V
or to 10.240 V for binary applications. For trimming, Bourns type
3059, 100 ill or 200 kO trtmpot is recommended.
Although Figure 10 illustrates a wide trim range, temperature
Output Power Boosting
Gnd
4
The addition of a power transistor, a reSistor, and a capacitor
converts the MC1404 into a preCision supply with one ampere
current capability. At V+ = 15 V, the MCI404 can carry in excess of
14 mA of load current with good regulation. nthe power transistor
current gain exceeds 75, a one ampere supply can be realized.
coefficients may become unpredictable for trim> ± 6.0%.
Figure 12. Ultra Stable Reference for MC1723 Voltage Regulator
Supply
2
MCI404P5
8(12)
7(11)
MCI723
3(5)
6
2(4)
4
-=
Io.1
_ IlF
Vout
Vout =5.0V
.I O.OOIIlF
5-16
I
omax
RO + 4.7 k)
(~
= 0.6 V
Rsc
MOTOROLA ANALOG IC DEVICE DATA
MC1404
Figure 13. 5.0 V, 6.0 Amp, 25 kHz Switching Regulator with Separate Ultra-Stable Reference
+10to+30In
120~
IO.01 /lF
50V
Ceramic
-=
+5.0 V Out
200mAto
6.0 Amps
rO.0 1 /lF
Ceramic
-=
-=
130
130
11
12
2
-=
Motorola
TL495CN
Pulse Width
Modulator
•
17
18
2.2 k
MCI404P5
100k
TRIM
(opt)
7
9
10
2.2 k
-=
-=
-=
Figure 14. Reference for a High Speed DAC
12.5 to
40V
Input
2
6
R2
MCI404Pl0
4
10 V Reference
-=
Digital
Inputs
•••
••
Analog
Oulput
Ladder
and
Switches
Rl and R2 values depend
on the current requirements
oftheDAC.
High Speed DAC
MOTOROLA ANALOG IC DEVICE DATA
5-17
®
MOTOROLA
TL431 , A, B
Series
Programmable
Precision References
•
PROGRAMMABLE
PRECISION REFERENCES
The TL431, A, B integrated circuits are three-terminal programmable
shunt regulator diodes. These monolithic IC voltage references operate as a
low temperature coefficient zener which is programmable from Vref to 36 V
with two external resistors. These devices exhibit a wide operating current
range of 1.0 rnA to 100 rnA with a typical dynamic impedance of 0.22 n. The
characteristics of these references make them excellent replacements for
zener diodes in many applications such as digital voltmeters, power
supplies, and op amp circuitry. The 2.5 V reference makes it convenient to
obtain a stable reference from 5.0 V logic supplies, and since the TL431 , A,
B operates as a shunt regulator, it can be used as either a positive or
negative voltage reference.
SEMICONDUCTOR
TECHNICAL DATA
Z, LP SUFFIX
PLASTIC PACKAGE
CASE 29
(T0-92)
I
Pin 1. Reference
2. Anode
• Programmable Output Voltage to 36 V
3. Cathode
12 3
• Voltage Reference Tolerance: ±O.4%, Typ @ 25°C (TL431B)
• Low Dynamic Output Impedance, 0.22 n Typical
• Sink Current Capability of 1.0 rnA to 100 rnA
• Equivalent Full-Range Temperature Coefficient of 50 ppml°C Typical
.~
PSUFFIX
PLASTIC PACKAGE
CASE 626
• Temperature Compensated for Operation over Full Rated Operating
Temperature Range
OM SUFFIX
PLASTIC PACKAGE
CASE 846A
(Micr0-8)
• Low Output Noise Voltage
(Top View)
o SUFFIX
PLASTIC PACKAGE
CASE 751
(SOP-8)
ORDERING INFORMATION
Device
Operating
Temperature Range
TL431CL~ACL~BCLP
Package
T0-92
TL431CP, ACP. BCP
2
7 }
Anode
Plastic
TA = 0' to +70'C
TL431CDM. ACDM. BCDM
Micr0-8
TL431CD. ACD. BCD
SOP-8
TL4311LP. AILP. BILP
T0-92
TL4311P. AlP. BIP
Plastic
TA = -40' to +85°C
TL431 10M. AIDM. BIDM
Micr0-8
TL431 10. AID. BID
SOP-8
5-18
8 Reference
Cathode
Anode {
•
8
(Top View)
80P-8 is an internally modified 80-8 package. Pins 2.
3. 6 and 7 are electrically common to the die attach ffag.
This internal lead frame modification decreases power
dissipation capability when appropriately mounted on a
printed circuit board. 80P-8 conforms to all extemal
dimensions of the standard 80-8 package.
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
Symbol
Representative Schematic Diagram
Component values are nominal
ca~~~e
Reference
(R)
i
Cathode (K)
Anode
(A)
Representative Block Diagram
Reference
(R) D-'----+----j~
II
Anode (A)
This device contains 12 active transistors.
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless
otherwise noted.)
Symbol
Rating
Cathode to Anode Voltage
Value
Unit
VKA
37
V
Cathode Current Range, Continuous
IK
-100 to +150
rnA
Reference Input Current Range, Continuous
Iref
--0.05 to + 10
rnA
Operating Junction Temperature
TJ
150
°c
Operating Ambient Temperature Range
TL431I, TL431AI, TL431BI
TL431C,TL431AC,TL431BC
TA
Storage Temperature Range
Tstg
Total Power Dissipation @ TA =25°C
Derate above 25°C Ambient Temperature
D, LP Suffix Plastic Package
P Suffix Plastic Package
DM Suffix Plastic Package
PD
Total Power Dissipation @ TC =25°C
Derate above 25°C Case Temperature
D, LP Suffix Plastic Package
P Suffix Plastic Package
PD
NOTE:
°C
-40 to +85
Oto+70
-65 to +150
°C
W
0.70
1.10
0.52
W
1.5
3.0
ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Condition
Symbol
Cathode to Anode Voltage
Min
Max
VKA
Vref
36
V
IK
1.0
100
mA
Cathode Current
Unit
THERMAL CHARACTERISTICS
Symbol
D, LP Suffix
Package
P Suffix
Package
DM Suffix
Package
Unit
Thermal Resistance, Junction-to--Ambient
RaJA
178
114
240
°CIW
Thermal Resistance, Junction-to--Case
RaJC
83
41
-
°CIW
Characteristic
MOTOROLA ANALOG IC DEVICE DATA
5-19
TL431 I A, B Series
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
TL431C
TL431 I
Symbol
Characteristic
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA = 25°C
TA = Tlowto Thigh (Note 1)
Min
Typ
Max
Min
Typ
Max
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 1, 2,4)
Unit
V
Vref
2.44
2.41
2.495
-
2.55
2.58
2.44
2.423
2.495
-
2.55
2.567
-
7.0
30
-
3.0
17
INrel
mV
VKA= Vref, IK = 10 mA
Ratio of Change in Reference Input Voltage
to Change in Cathode \0 Anode Voltage
IK = 10 mA (Figure 2), IWKA = 10 V \0 Vref
Ll.VKA=36Vtol0V
II
Reference Input Current (Figure 2)
IK = 10 mA, Rl = 10 k, R2 = ~
TA=25°C
TA = Tlowto Thigh (Note 1)
mVN
l!N ref
AV KA
-
-
-1.4
-1.0
-2.7
-2.0
-
-1.4
-1.0
-2.7
-2.0
I1A
Iref
-
1.8
-
4.0
6.5
-
1.8
-
-
-
4.0
5.2
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 1,4)
IK=10mA, Rl = 10k, R2=~
Ll.lref
-
0.8
2.5
-
0.4
1.2
I1A
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin
-
0.5
1.0
-
0.5
1.0
mA
Off-State Cathode Current (Figure 3)
VKA=36 V, Vref= OV
loff
-
2.6
1000
-
2.6
1000
nA
IZKAI
-
0.22
0.5
-
0.22
0.5
n
Dynamic Impedance (Figure 1, Note 3)
VKA = Vref, Ll.IK = 1.0 mA to 100 mA
f:s; 1.0 kHz
NOTE 1: Tlow = -40°C for TL431 AlP TL431 AILP, TL4311P, TL431ILP, TL431 BID, TL431 BIP, TL431 BILP, TL431 AIOM, TL4311DM, TL431 BIDM
= 0°ClorTL431ACP, TL431 ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431 BCD, TL431 BCP, TL431 BcLp;TL431CDM,
TL431 ACDM, TL431 BCDM
Thigh = +85°C lor TL431AIP, TL431 AILP, TL4311P, TL4311LP, TL431 BID, TL431BIP, TL431BILP, TL4311DM, TL431AIDM, TL431 BIDM
= +70°C lor TL431 ACP, TL431ACLP, TL431 CP, TL431 ACD, TL431 BCD, TL431 BCP, TL431 BCLP, TL431 CDM, TL431 ACDM, TL431 BCDM
NOTE 2: The deviation parameter AVrel is delined as the difference between the maximum and minimum values obtained over the lull operating ambient
temperature range that applies.
.
Vrffimaxl~
AVrel= Vrffi max
-Vrefmin
ATA=T2- Tl
Vrelmin(j
T1 AmbientTemperature
T2
The average temperature coefficient of the relerence input vottage, aVrel is defined as:
AVrel
( V
rel @ 25°C
V rel PfCm =
)x
6
10
Ll. TA
aVrel can be positive or negative depending on whether Vrel Min or Vrel Max occurs at the lower ambient temperature. (Reier to Figure 6.)
Example: Ll.V rei = 8.0 mV and slope is positive,
V rei
@
25°C = 2.495 V, AT A = 70°C
0.008 x 106
/0
a V ref = 70 (2.495) = 45.8 ppm C
AV
NOTE 3: The dynamic impedance ZKA is defined as IZ KA' = Ll. IKA
K
When the device is programmed with two external resistors, Rl and R2, (reler to Figure 2) the total dynamic impedance 01 the circuit is defined as:
5--20
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
ELECTRICAL CHARACTERISTICS (TA = 25'C, unless otherwise noted.)
TL431AI
Characteristic
Symbol
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA=25'C
TA = Tlow to Thigh
Min
Typ
TL431AC
Max
Min
Typ
TL431B
Min
Max
Typ
Max
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 1,2,4)
VKA= Vref, IK = lOrnA
Ratio of Change in Reference Input Voltage
to Change in Cathode to Anode Voltage
IK = 10 rnA (Figure 2), AVKA = 10 V to Vref
AVKA=36Vtol0V
Unit
V
Vref
2.47
2.44
2.495
2.52
2.55
2.47
2.453
2.495
-
-
2.52
2.537
2.483
2.475
2.495
2.495
2.507
2.515
-
7.0
30
-
3.0
17
-
3
17
AVref
mV
mVN
AV ref
AV KA
-
-1.4
-1.0
-
-2.7
-2.0
-
1.8
-
4.0
6.5
0.8
-1.4
-1.0
-2.7
-2.0
-
-
-
1.8
-
4.0
5.2
2.5
-
0.4
1.2
-
-
-1.4
-1.0
-2.7
-2.0
1.6
-
3.0
4.0
0.4
1.2
f.1A
Reference Input Current (Figure 2)
IK = lOrnA, Rl = 10k, R2 = ~
TA = 25'C
TA = Tlowto Thigh (Note 1)
Alref
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 1)
IK= lOrnA, Rl = 10k, R2=~
Alref
-
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin
-
0.5
1.0
-
0.5
1.0
-
0.5
1.0
mA
Off-State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V
loff
-
260
1000
-
260
1000
-
230
500
nA
IZKAI
-
0.22
0.5
-
0.22
0.5
-
0.14
0.3
11
Dynamic Impedance (Figure 1, Note 3)
VKA = Vref, AIK = 1.0 rnA to 100 rnA
f:;; 1.0kHz
f.1A
NOTE 1: Tlow = -40'C for TL431 AlP TL431 AILP, TL4311P. TL431ILP, TL431 BID, TL431 BIP, TL431 BILP, TL431AIDM, TL431 10M, TL431 BIDM
= O'C for TL431 ACP, TL431ACLP. TL431CP, TL431CLP, TL431 CD, TL431ACD, TL431 BCD, TL431 BCP, TL431 BCLP, TL431CDM,
TL431 ACDM, TL431 BCDM
Thigh = +85'C for TL431AIP, TL431AILP, TL4311P, TL431ILP, TL431 BID. TL431 BIP, TL431 BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70'C for TL431ACP, TL431 ACLP, TL431CP. TL431ACD, TL431 BCD, TL431 BCP, TL431 BCLP, TL431CDM, TL431ACDM, TL431 BCDM
NOTE 2: The deviation parameter tNref is defined as the difference between the maximum and minimum values obtained over the full operating ambient
temperature range that applies.
'M~I~
Vrefmin~
T1 Ambient Temperature
T2
The average temperature coefficient of the reference input voltage, aVref is defined as:
A V ref
( V
ref @ 25'C
Vref Pfcm =
)x
10
6
-'----;-;0---'---
A TA
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example: AV ref = 8.0 mV and slope is positive,
V ref @ 25'C = 2.495 V,AT A = 70'C
a V ref =
0.008 x 106
70 (2.495)
45.8 ppm/,C
AV
NOTE 3 : The dynamic impedance ZKA is defined as IZKAI =
A IKA
K
)
When the device is programmed with two external resistors, Rl and R2, (refer to Figure 2) the total dynamic impedance of the circuit is defined as:
IZKA'I
~ IZKAI
NOTE 4: This test is not applicable to surface mount (D and DM suffix) devices.
MOTOROLA ANALOG IC DEVICE DATA
( 1
+ =~
5-21
II
TL431 , A, B Series
Figure 1. Test Circuit for VKA = Vref
Figure 3. Test Circuit for lof
Figure 2. Test Circuit for VKA > Vref
Input o-.JIIIJ'V-.---o VKA
Rt
R2
VKA = Vref ( 1 +
Figure 4. Cathode Current versus
Cathode Voltage
II
a:
a:
:::>
BOO
VKA =Vref
TA = 25°C
I100
c- '"'"
!z
w
I-
50 l-
w
Cl
"K'KA
!z
ll!
a:
"'"q':"
~
-1.0
0
1.0
VKA, CATHODE VOLTAGE (V)
2600
VKA
:[ 2580 InputW
, IKVKA = Vref
Vref
'K=10mA -
~
1
I
I
I
~ 2480
2460
~
-
2440
Ii! 2420
2400
-55
I
a
0
25
50
75
TA, AMBIENT TEMPERATURE (OC)
5-22
-r--
1-""
100
~
£;
3.0
1.0
2.0
VKA, CATHODE VOLTAGE (V)
125
"""""'-
1.5
-
r--
'K=10mA
~
1.0
~~
0.5
j
.............
2.0
~
1
I
I
~=i440mv
1
-25
o
3.0
~ 2.5
a:
Vref Max = 2550 mV
I
~
Figure 7. Reference Input Current versus
Ambient Temperature
Vref Typ = 2495 mV _
>
./
0
-200
-1.0
3.0
2.0
1
~..--
~
./
!;;:
/
L
I
/
200
I
Figure 6. Reference Input Voltage versus
Ambient Temperature
a:
/
()
-50
-100
-2.0
LU
IM~ f - -
w
g
()
~
VKA = Vref
TA = 25°C
()
/'
!;;:
400
:::>
~
0
0
I
~ 600
"E!iF
I-
()
+ 'ref • Rl
Figure 5. Cathode Current versus
Cathode Voltage
150
<.s
~)
o
-55
'~~'"
!W ~ "K
10k
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (OC)
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
Figure 9. Off-State Cathode Current
versus Ambient Temperature
Figure 8. Change in Reference Input
Voltage versus Cathode Voltage
l
0
~
~--8.0
>
11.Ok
I
"'- ~
w
IK=10mA_
TA = 25°C
a: 100
a:
::>
..................
~
u::; --16
i'5
a:
'"~~VAA
Rl
+IK
a:
R2
()
tt --24
w
0
D
t'......
10
:I:
!;;:
r--.......
./
(,)
w
1.0
:Lu-
0.1
~
..............
Vref
j
10
20
30
40
o.ot
--55
--25
VKA, CATHODE VOLTAGE (V)
<5
w
~loutPut
'"
50
E
TA =25°C
A IK = 1.0 rnA to tOO rnA
==
g:
w
K
_+
-0:
D
w
~1~utPut
"",
'"
;;§
0.260
(,)
:E
-0:
-0:
:z
0.240
>D
1.0
~
~
~
~
0.1
1.0k
10k
lOOk
f, FREQUENCY (MHz)
1.0M
0.220
0.20~55
10M
Figure 12. Open-Loop Voltage Gain
versus Frequency
125
Output
+11<,
~
40
9.01!F
.~E-j
H~
230
Gnd
V
V
.-'
0
25
50
75
TA, AMBIENT TEMPERATURE (0C)
100
125
-?
<-
.§..
..... 60
)t
8.25 k
30
w
a:
a:
Gnd
(,)
t\
20
~
10 f-- IK=10mA
TA =25°C
........r-.
:z
::>
C!l
w
VKA =Vref
IK=10rnA
TA = 25°C
40
D
0
:I:
.....
!;;:
(,)
I"",~f<>_
, IK
20
]j.
I
--10
1.0k
--25
V
50
80
50
f''-'!'
100
Figure 13. Spectral Noise Density
60
~
w
75
0.280
"-
::;:
~
C!l
:z
50
VKA =Vret
A IK= 1.0 rnA to 100 rnA
t:51.0kHz
()
9
>D
25
0.300
:z
Gnd
";;§
:z
0
0.320
1.0 k
10
'"~~VAA
,Ioff
Figure 11. Dynamic Impedance
versus Ambient Temperature
100
w
()
:z
VKA =36 V
Vret = 0 V
TA, AMBIENTTEMPERATURE (5C)
Figure 10. Dynamic Impedance
versus Frequency
g:
V'
./
/'
.:
o
/'
/'
0
..P
C,.)
4.0
II
8.0
t, TIME (lJS)
12
16
Figure 16. Test Circ;uit For Curve A
of Stability Boundary Conditions
80
w
Gnd
I
c
0
60
'<
40
:x:
C,.)
~
o
A) VKA= Vref
8) VKA = 5.0 V @ IK = 10 rnA
C)VKA = 10V@ IK=10rnA
D)VKA= 15V@ IK= 10 rnA
TA=25'C
1111 II
I "Stable
Input
Mo~nor
h..
20
II
.1,Stable
:~
I.A
8
8
C
~
20
o
100pF
l000pF
O.OII1F
O.II1F
CL, LOAD CAPACITANCE
1.011F
Figure 17. Test Circuit For Curves B, C, And D
of Stability Boundary Conditions
150
V+
V+
TYPICAL APPLICATIONS
Figure 18. Shunt Regulator
V+ o--J\IV\r-_-......-
.......- - 0 Vout
Figure 19. High Current Shunt Regulator
V+ O--'W'r-_-_ _- - O Vout
R1
R2
5-24
MOTOROLA ANALOG·IC DEVICE DATA
TL431 , A, B Series
Figure 20. Output Control for a
Three-Terminal Fixed Regulator
Figure 21. Series Pass Regulator
~---.--o
~-..----o
V+
yOU!
R1
You!
R1
R2
R2
YOU! = (1
YOU! = (1
+~) Vref
yOU! min = Vref
+~) Vref
yOU! min = Vref
+ 5.0V
Figure 22. Constant Current Source
+ Vbe
•
Figure 23. Constant Current Sink
RS
Figure 24. TRIAC Crowbar
V+
1"""'<._-.__--0 you!
R1
Figure 25. SRC Crowbar
V+
»-__- _ -.......- - - 0
yOU!
R1
R2
MOTOROLA ANALOG IC DEVICE DATA
5-25
TL431 , A, B Series
Figure 26. Voltage Monitor
V+o--.--.....-
Figure 27. Single-Supply Comparator with
Temperature-Compensated Threshold
---..--o Vout
.....
V+
R3
...---0 VoU!
R2
R4
Yin
L.E.D. indicator is 'on' when V+ is between the
upper and lower limits.
II
Vre!
Lower Limit = (1
+~)
Vret
Upper Limit = (1
+~)
Vret
Figure 28. Linear Ohmmeter
Vout
V+
=2.0V
Figure 29. Simple 400 mW Phono Amplifier
T,=330t08.00
~T'
8.00
Rx = Vout •
5-26
~
Range
l)-dJ II
'Thermalloy
THM6024
Heatsinkon
LP Package
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
Figure 30. High Efficiency Step-Down Switching Converter
150"H@2.0A
Yin = 10oV_to_2~0~V_ _--..._ _,TIPI15r_-+_--..._---<_-'
4.7 k
+
Vout = 5.0 V
lout = 1.0A
lN5823
O.OIIlF
100k
2200ilF
+
51 k
10
Test
Line Regulation
Load Regulation
Oulput Ripple
Output Ripple
Efficiency
MOTOROLA ANALOG IC DEVICE DATA
Conditions
= 10 V to 20 V, 10 = 1.0 A
Vin = 15 V, 10 = 0 A to 1.0 A
Vin = 10 V, 10 = 1.0 A
Vin = 20 V, 10 = 1.0 A
Vin = 15 V, 10 = 1.0 A
Vin
II
Results
53mV (1.1%)
25mV (0.5%)
50 mVpp PAR.D.
100 mVpp PAR.D.
82%
5-27
II
5-28
MOTOROLA ANALOG IC DEVICE DATA
Data Conversion
In Brief ...
Motorola's line of digital-to-analog and analog-to--digital
converters include several varieties to suit a number of
applications.
The AID converters include an 8-bit flash converter suitable
for NTSC and PAL systems. CMOS devices include 8 to 1()-bit
converters, as well as other high speed digitizers.
The D/A converters have 6 and 8-bit devices, and video
speed (for NTSC and PAL) devices.
MOTOROLA ANALOG IC DEVICE DATA
Page
Data Conversion ................................. 6-2
A-D Converters ............................... 6-2
CMOS ..................................... 6-2
Bipolar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
Sigma-Delta ............................... 6-2
D-A Converters ............................... 6-3
CMOS ..................................... 6-3
Sigma-Delta ............................... 6-3
Package Overview ............................... 6-4
Device Listing and Related Literature ............... 6-5
6-1
III
Data Conversion
The line of data conversion products which Motorola offers
spans a wide spectrum of speed and resolution/accuracy.
Features, including bus compatibility, minimize external parts
count and provide easy interface to microprocessor systems.
Various technologies, such as Bipolar and CMOS, are utilized
to achieve functional capability, accuracy and production
repeatability. Bipolar technology generally results in higher
speed, while CMOS devices offer greatly reduced power
consumption.
Table 1. A-O Converters
Conversion
TImelRate
Input
Vonage
Range
Supplies
Device
Nonlinearity
Max
(V)
Temperature
Range
(OC)
MC145040
±1/2 LSB
10 IJS
Oto VDD
+5.0±10"lo
-40 to +125
Resolution
(Bits)
Suffix!
Package
Comments
CMOS
8
MC145041
II
MC14549BI
MC14559B
P1738,
DW1751D
Includes Inlernal
Clock, 11--Gh MUX
20 IJS
Successive Approximation
Regislers
+3.010+18
-4010 +85
P/648
Triple
8-Bil
MC44251
1 LSB
18MHz
1.6t04.6V
+5.0±10%
-4010 +85
FN17n
10
MC145050
±1 LSB
21 IJS
010 VDD
+5.0±10%
-4010+125
P1738,
DW1751D
MC145051
Requires External
Clock, 11--Gh MUX
Compalible wilh
MC1408 S.A.R.
B-bil D-A Converter
3 Separale Video
Channels
Requires Extemal
Clock, 11-Ch MUX
Includes Inlernal
Clock, 11--Gh MUX
441JS
MC145053
P/646,
D1751 A
8-10
MC144431
MC14447
±O.5%
Full Scale
300J,ls
Variable
w/Supply
+5.010+18
3-1/2 Digil
MC14433
±O.05%
±1 Counl
40ms
±2.0V
±200 mV
+5.0 to +8.0
-2.810-8.0
MC10319
±1 LSB
25 MHz
MC145073
±1 LSB
48kHz
-4010+85
Includes Inlernal
Clock, S--Ch MUX
P/648,
J,lP Compalible,
DW1751G Single Slope,
6--ch MUX
P1709,
Dual Slope
DW1751E
Bipolar
8
010 2.0 Vpp
+5.0 and
Max
-3.010-6.0
010+70
P1709,
DW1751F
Die Form
Video Speed Flash
Converter, Inlernal
Gray Code
TILOulpuls
-4010+85
DW1751E
Dual Channel,
Sigma-Delta
archilecture
Sigma-Delta
16
6-2
1.9 Vpp
4.5105.5
MOTOROLA ANALOG IC DEVICE DATA
Table 2. D-A Converters
Device
Max
Max
Settling
Time
(± 112 LSB)
MC144110
-
-
MC144111
-
-
MC144112
-
-
+2.5 to +5.5
MC44200
±1/2 LSB
30 ns
16,18,20
MC145074
See data
sheet
-
MC145076
See data
sheet
Accuracy
@,25°C
Resolution
(Bits)
Supplies
Temperature
Range
(V)
('C)
+5.0 to +15
Oto+85
Suffix!
Package
Comments
CMOS
6
Triple
8-Bit
P1707,
DWI751D
Serial input, Hex DAC,
6 outputs
P/646,
DW1751G
Serial input, Quad DAC,
4 outputs
-40 to +85
P/646,
D1751 A
Serial input, Quad DAC,
4 outputs
+5.0
±10%
-40 to +85
FU/824A
6.0 ns
4.5 to 5.5
-40 to +85
D1751B
Dual Channel,
Sigma-Delta architecture,
MC145076 FIR Filter
available
-
+5.0
-40 to +85
D1751B
Dual Channel Bit Stream,
144 tap FIR Filter
Triple Video DAC,
55 MHz, TTL
Sigma-Delta
MOTOROLA ANALOG IC DEVICE DATA
6-3
Data Conversion Package Overview
-
•
-
CASE 646.
PSUFFIX
II
CASE 648
PSUFFIX
~
CASE 707
PSUFFIX
6-4
CASE 649
PSUFFIX
CASE 709
PSUFFIX
CASE 751A
DSUFFIX
CASE 751B
DSUFFIX
CASE 751F
DWSUFFIX
CASE 751G
DWSUFFIX
•
CASE 751D
DWSUFFIX
CASE 777
FN SUFFIX
-
CASE 738
PSUFFIX
CASE 751E
DWSUFFIX
•
CASE 824A
FUSUFFIX
MOTOROLA AIliALOG IC DEVICE DATA
Device Listing and Related Literature
A-D Converters
Device
Function
MC10319
High Speed 8-Bit Analog-ta-Digital Flash Converter ................ 6-6
Page
RELATED APPLICATION NOTES
App Note
Title
Related Device
AN702
High Speed Digital-ta-Analog and Analog-ta-Digital
Techniques ............................................... General Information
AN926
Techniques for Improving the Settling Time of a DAC and
Op Amp Combination ...................................... Various
III
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC10319
High Speed a-Bit
Analog-to-Digital Converter
a
The MC10319 is an 8-bit high speed parallel flash AID converter. The
device employs an internal Grey Code structure to eliminate large output
errors on fast slewing input signals. It is fully TTL compatible, requiring a
+ 5.0 V supply and a wide tolerance negative supply of - 3.0 to - 6.0 V.
Three-state TTL outputs allow direct drive of a data bus oi; common I/O
memory.
The MC10319 contains 256 parallel comparators across a precision input
reference network. The comparator outputs are fed to latches and then to .an
encoder network, to produce an 8-bit data byte plus an overrange bit. The
data is latched and converted to 3-state L8-TTL outputs. The overrange bit
is always active to allow for either sensing olthe overrange condition or ease
of interconnecting a pair of devices to produce a 9-bit AID converter.
Applications include video display and radar processing, high speed
instrumentation and TV broadcast encoding.
HIGH SPEED
8-BIT ANALOG-TO-DIGITAL
FLASH CONVERTER
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
" , .
PLASTIC PACKAGE
CASE 709
• Internal Grey Code for Speed and Accuracy, Binary Outputs
• 8-Bit Resolution/9-Bit Typical Accuracy
• Easily Interconnected for 9-Bit Conversion
OW SUFFIX
PLASTIC PACKAGE
CASE 751F
(S0-28L)
• 3-State LS-TTL Outputs with True/Complement Enable Inputs
• 25 MHz Sampling Rate
• Wide Input Range: 1.0 to 2.0 Vpp , between ± 2.0 V
• Low Input Capacitance: 50 pF
• Low Power Dissipation: 618 mW
• No Sample/Hold Required for Video Bandwidth Signals
PIN CONNECTIONS
(Ponly)
• Single Clock Cycle Conversion
GNO 2
OVERRANGE
Representative Block Diagram
logic
Analog
Input
Vin
(14)
VAT
(24)
VEE
VCCjOj
-I - ,I
(11, 7
(13)
MC10319
GNO
(2,12,
16,22)
Bias
L ___ J
r----.,
I
I
r-----,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
r-----,
OverRange
(3)
07(4)
06(5)
05(6)
04(7)
03(8)
02(9)
ORDERING INFORMATION
01 (10)
00(21)
VRB
(23)
Device
MC10319DW
Clock
(18)
MC10319P
Operating
Temperature Range
TA = 0° to +70°C
Package
S0-28L
Plastic
MOTOROLA ANAI.,OG ICDEVICE DATA
MC10319
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC(A),(D)
VEE
+7.0
-7.0
Vdc
PosHive Supply Voltage Differential
VCC(D)VCC(A)
-0.3 to + 0.3
Vdc
Digital Input Voltage (Pins 18 to 20)
V, (D)
-0.5 to+ 7.0
Vdc
V,tA)
-2.5 to + 2.5
Vdc
Rating
Supply Voltage
Analog Input Voltage (Pins I, 14,23,24)
Reference Voltage Span (Pin 24 to Pin 23)
-
2.3
Vdc
Applied Output Voltage (Pins 4 to 10, 21 in 3-State)
-
-0.3 to + 7.0
Vdc
Junction Temperature
TJ
+ 150
°C
Storage Temperature
Tstg
-65 to + 150
°C
Devices should not be operated at these values. The "Recommended Operating Limits" table provides
guidelines for actual device operation.
RECOMMENDED OPERATING LIMITS
Characteristic
Power Supply Voltage (Pin 15)
(Pins 11,17)
VCC(D) - VCC(A)
Power Supply Voltage (Pin 13)
Digital Input Voltages (Pins 18 to 20)
Analog Input (Pin 14)
Symbol
Min
Typ
Max
Unit
VCC(A)
VCC{D)
+4.5
+5.0
+5.5
Vdc
dVCC
-0.1
0
+0.1
Vdc
VEE
-6.0
-5.0
-3.0
Vdc
V'(D)
a
-
+5.0
Vdc
V,tA)
-2.1
-
+2.1
Vdc
-
+2.1
Vdc
-
+ 1.0
Vdc
Vdc
VRT
-1.0
Voltage @ VRB (Pin 23)
VRB
-2.1
VRT-VRB
dVR
+ 1.0
-
+2.1
VRB-VEE
-
1.3
-
-
Vdc
Applied Output Voltage (Pins 4 to 10, 21 in 3-State)
Va
0
-
5.5
Vdc
Clock Pulse Width - High
Low
tCKH
tCKL
5.0
15
20
20
-
ns
Clock Frequency
fCLK
0
-
25
MHz
TA
0
-
+70
°C
Voltage @ VRT (Pin 24)
Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS (0° < TA < 70°C, VCC = 5.0 V, VEE =-5.2 V, VRT=+1.0 V, VRB =-1.0 V, unless noted.)
I
Characteristic
I
Symbol
I
Min
I
Typ
I
Max
I
Unit
TRANSFER CHARACTERISTICS (fCKL = 25 MHz)
Resolution
Monotonicity
N
-
-
8.0
Bits
LSB
Guaranteed
MON
Bits
Integral Nonlinearity
INL
-
± 1/4
± 1.0
Differential Nonlinearity
DNL
-
-
±1.0
LSB
Differential Phase (See Figure 16)
DP
-
1
-
Deg.
DG
-
1
-
Differential Gain (See Figure 16)
Power Supply Rejection Ratio
(4.5 V < VCC < 5.5 V, VEE = - 5.2 V)
(-6.0V < VEE < -3.0 V, VCC = +5.0 V)
MOTOROLA ANALOG IC DEVICE DATA
PSRR
%
LSBIV
-
0.1
-
a
-
6--7
II
MC10319
ELECTRICAL CHARACTERISTICS - continued
(0° < TA < 70°C, VCC = 5.0 V, VEE = - 5.2 V, VRT = +1.0 V, VRB = -1.0 V, unless otherwise noted.)
I
Characteristic
Symbol
Min
I
Typ
Max
Unit
ANALOG INPUTS (Pin 14)
Input Current @ Yin = VRB (See Figure 5)
IINL
-100
0
-
Input Current @ Yin = VRT (See Figure 5)
IINH
-
60
150
J.lA
J.lA
Input Capac~ance (VRT - VRB = 2.0 V, See Figure 4)
Cin
-
36
-
pF
Input Capacitance (VRT - VRB = 1.0 V, See Figure 4)
Cin
-
55
-
pF
VOS
-
0.1
-
LSB
Bipolar Offset Error
REFERENCE
Ladder Resistance (VRT to VRB, TA = 25°C)
Rret
104
130
156
Temperature Coefficient
TC
-
+0.29
Ladder CapaCitance (Pin 1 open)
Cret
-
25
-
Input Voltage - High (Pins 19 to 20)
VIHE
2.0
-
-
V
Input Voltage - Low (Pins 19 to 20)
VILE
-
0.8
V
Input Current @ 2.7 V
Q
o/oI°C
pF
ENABLE INPUTS (VCC = 5.5 V) (See Figure 6)
II
IIHE
-
0
20
Input Current @ 0.4 V @ EN (0 < EN < 5.0 V)
11L1
-400
-100
-
Input Current @ 0.4 V @ EN (EN = 0 V)
IIL2
-400
-100
-
IIL3
-20
-2.0
-
J.lA
J.lA
J.lA
J.lA
VIKE
-1.5
-1.3
-
V
Input Voltage High
VIHC
2.0
-
-
Vdc
Input Voltage Low
VILC
-
-
0.8
Vdc
Input Current @ 0.4 V (See Figure 7)
IILC
-400
-80
-
!LA
Input Current @ 2.7 V (See Figure 7)
IIHC
-100
-20
-
!LA
Input Clamp Voltage (11K = - 18 rnA)
VIKC
-1.5
-1.3
-
Vdc
VOH
2.4
3.0
-
V
-
0.35
0.4
V
35
-
mA
-50
-
+50
-
9.0
-
Input Current @ 0.4 V @ EN (EN = 2.0 V)
Input Clamp Voltage (11K = - 18 rnA)
CLOCK INPUTS (VCC = 5.5 V)
DIGITAL OUTPUTS
High Output Voltage (IOH = - 400
J.lA, VCC = 4.5 V, See Figure 8)
Low Output Voltage (IOL = 4.0 rnA, See Figure 9)
VOL
Output Short Circuit Current' (VCC = 5.5 V)
ISC
Output Leakage Current (0.4 < Vo < 2.4 V, See Figure 3,
VCC = 5.5 V, DO to 07 in 3-State Mode)
ILK
Output Capacitance (DO to 07 in 3-State Mode)
Cout
J.lA
pF
'Only one output is to be shorted at a time, not to exceed 1 second.
POWER SUPPLIES
VCC(A) Current (4.5 V < VCC(A) < 5.5 V) (Outputs unloaded)
ICC(A)
10
17
25
rnA
VCC(D) Current (4.5 V < VCC(O) < 5.5 V) (Outputs unloaded)
ICC(O)
50
90
133
rnA
VEE Current (- 6.0 < VEE < - 3.0 V)
lEE
-14
-10
-6.0
rnA
Power Dissipation (VRT - VRB = 2.0 V) (Outputs unloaded)
PD
-
618
995
mW
MOTOROLA ANALOG Ie DEVICE DATA
MC10319
TIMING CHARACTERISTICS (TA = 25°C, VCC = + 5.0 V, VEE = - 5.2 V, VRT = + 1.0 V, VRB = -1.0 V,
see System liming Diagram, Figure 1.)
Characteristic
Symbol
Min
Typ
Max
Unit
Min Clock Pulse Width - High
tCKH
-
5.0
-
ns
Min Clock Pulse Width - Low
tCKL
-
15
-
ns
Max Clock Rise, Fall Time
tR,F
-
100
-
ns
Clock Frequency
fCLK
0
30
25
MHz
tCKDV
-
19
-
ns
tAD
-
4.0
-
ns
INPUTS
OUTPUTS
New Data Valid from Clock Low
Aperture Delay
tH
-
6.0
-
ns
Data High to 3-State from Enable Low·
tEHZ
-
27
-
ns
Data Low to 3-State from Enable Low"
tELZ
-
18
-
ns
Data High to 3-State from Enable High·
tEHZ
-
32
-
ns
Data Low to 3-State from Enable High·
tELZ
-
18
-
ns
tEDV
-
15
-
ns
tEDV
-
16
-
ns
ttr
-
8.0
-
ns
Hold lime
=0 V)*
Valid Data from Enable Low (Pin 19 =5.0 V)*
Valid Data from Enable High (Pin 20
Output Transition lime" (10% to 90%)
"See Figure 2 for output loading.
PIN FUNCTION DESCRIPTION
Pin
Function
P Suffix
OW Suffix
VRM
1
1
Description
GND
2,12
16,22
2,13,17
18,25,26
OVR
3
3
D7-DO
4 to 10, 21
4to 10, 24
VCC(D)
11,17
11,12
19,20
VEE
13
14
Negative power supply. Nominally - 5.2 V, it can range from - 3.0 to - 6.0 V, and must
be more negative than VRB by > 1.3 V. Reference to analog ground.
Yin
14
15
Signal voltage input. This voltage is compared to the reference to generate a digital
equivalent. Input impedance is nominally 16 to 33K in parallel with 36 pF.
VCC(A)
15
16
Power supply for the analog section. +5.0 V, ± 10% required. Reference to analog
ground.
The midpoint of the reference resistor ladder. Bypassing can be done at this point to
improve performance at high frequencies.
Dig~al ground. The pins should be connected directly together, and through a low
impedance path to the power supply.
Overrange output. Indicates Yin is more positive than VRT 1/2 LSB. This output does
not have 3-state capability.
Dig~al Outputs. D7 (Pin 4) is the MSB. D0 (Pin 21 or 24) is the LSB. LS-TIL
compatible with 3-state capability.
Power supply for the digital section. +5.0 V, ± 10% required. Reference to digital
ground.
CLK
18
21
Clock input. TIL compatible.
EN
19
22
Enable input. TIL compatible, a logic 1 (and EN at a logic 0) enables the data outputs.
A logic 0 puts the outputs in a 3-state mode.
EN
20
23
Enable input. TIL compatible, a logic 0 (and EN at a logic 1) enables the data outputs.
A logic 1 puts the outputs in a 3-state mode.
VRB
23
27
The bottom (most negative point) of the internal reference resistor ladder.
VRT
24
28
The top (most positive point) of the internal reference resistor ladder.
MOTOROLA ANALOG IC DEVICE DATA
III
MC10319
Figure 1. System Timing Diagram
14--- 'CKH -----i*"f---- tcKL - - - - . j
Clock
tCKDV and tH measured at output levels of 0.8 and 2.4 V.
II
EN
EN
tEHZ
High Data
Output
tEll
Low Data
Output
Outputs
Active
Figure 2. Data Output Test Circuit
Figure 3. Output 3-State Leakage Current
200
VCC
~ 100
1.0kn
00-07,)--"--"-*-.
'"
~
50
§
0
~
-50
i1i
-100
a:
<..>
w
C1
i'
3.0 kn
..
...I
r.'7
Diodes = 1N914 or equivalent, C1 = 15 pF
-200
-1.0
)
(
I
O°C < TA < 70°C
Pin19=OV
o
1.0
2.0
3.0
4.0
5.0
6.0
7.0
APPLIED VOLTAGE (VOLTS)
6-10
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 5. Input Current @ Vin (Pin 14)
Figure 4. Input Capacitance @ Vin (Pin 14)
100
80
I
I
[L
80
\
S
UJ
'-'
~
t5
60
<.5
Z
UJ
I
I
ex:
ex: 40
::::J
'-'
VRT- VRS =1.0 V
::>
-
40
I
~
0-
I
I
20
-"«
(
I
0.1~
20
;;;:
-2.5
VRS
VRT
+2.5
Vin, INPUT VOLTAGE (VOLTS)
"
'/
./'
--
20
;;;:
zUJ -30
ex:
ex:
~
::> -50 I'-'
I-
E,
Pin 19 Current
2V
h_
I
-130
IZ
Pin 19 (Pin 20 = 0 V)
Pin 20 (0 < Pin 19 <5 V)
I-
-70
II
Figure 7. Clock Input Current
40
I-
0-
/
Vin, INPUT VOLTAGE (VOLTS)
E,
::>
W
/
Figure 6. Input Current @ Enable, Enable
10
0
-10
/
A~
...:...5
vRT - vRS =2.0 V
\.i
'r-J
~ '/"70°C
I-
~
1:«
~
I-
\i
C3
O°C
.2- 60
I
I
~
25°C
;;;:
I
I
~oc/ V
...-o:c
-120
1.0
2.0
o
5.5
1.0
2.0
Vin, INPUT VOLTAGE (VOLTS)
3.0
4.0
5.0
6.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 8. Output Voltage versus Output Current
Figure 9. Output Voltage versus Output Current
0.5
Ui
Ui 5.011=--+--=+--t--1---+--+--+--I
~
~
UJ
C!l
4.0
0° and 70°C-, ~
C!l
~
0.3
~
0.2
g
~
~
!3
~ 0.4
c:.
UJ
25°C-
V
§
~
.:..
;9 0.1
Q
:c
4.5 V < VCC < 5.5 V
:9
3.0
'--_.L-_...l-_-'-_--'-_-'-_--L_--'=~
o
-100
-200
-300
IOH, OUTPUT CURRENT (~A)
MOTOROLA ANALOG IC DEVICE DATA
-400
o
o
2.0
4.0
6.0
B.O
IOL, OUTPUT CURRENT (rnA)
6-11
MC10319
Figure 10. Supply Current versus Temperature
Figure 11. Supply Current versus Temperature
-12
1112
~
110
'--...
~
z
0::
...........
::;
-
a..
102
-10
'-.....
VEE=-5.2V
LiJ
E'
-8.0
20
40
60
TA. AMBIENT TEMPERATURE (OC)
70
o
20
40
60
TA. AMBIENT TEMPERATURE (OC)
Figure 12. Differential Linearity Error
70
Figure 13. Integral Linearity Error
1/2 I-+--t--+--+-+-f-I--+--+'-+-+--+-+-ff--t---I
LSB
1/2
LSB
1, ii,
o
~~ W'~'\
-1/21-+-+-+--+-+-f-1--+-+-+-+--+-+-ff--t---I
LSB
,, ~
~~
IJJ ,.A, i
~VI
-112
fJ~"'J hl~ II
I~
~~rlr'
• ~M
LSB
VRT=2.0 V. VRB = 0 V
Fs = 25 MHz
o
o
256
32
64
98
128
160
192
224
256
Figure 15. Integral Linearity Error
Figure 14. Differential Linearity Error
1/2
LSB
I--t--t--+--+-+-t-I-t-+--+--+-+-t-t-t----i
-1/2 I--+-+-+-+--+-+-ff--+-+-+-+--+-+-+-f---j
LSB
VRT= 2.0 V. VRB =0 V
Fs = 12.5 MHz
o
6-12
32
64
96
128
160
192
224
256
MOTOROLA ANALOG IC DEVICE DATA
MC10319
DESIGN GUIDELINES
Introduction
Reference
The MC1 0319 is a high speed, 8-bit, parallel (''flash'') type
analog-to-digital converter containing 256 comparators at
the front end. See Figure 17 for a block diagram. The
comparators are arranged such that one input of each is
referenced to evenly spaced voltages, derived from the
reference resistor ladder. The other input of the comparators
is connected to the input signal (Vin). Some of the
comparator's differential outputs will be ''true,'' while other
comparators will have "not true" outputs, depending on their
relative position. Their outputs are then latched, and
converted to an 8-bit Grey code by the Differential Latch
Array. The Grey code ensures that any input errors due to
cross talk, feed-thru, or timing disparities result in glitches at
the output of only a few LSBs, rather than the more traditional
1/2 scale and 1/4 scale glitches.
The Grey code is then translated to an 8-bit binary code,
and the differential levels are translated to TTL levels before
being applied to the output latches. Enable inputs at this final
stage permit the TTL outputs (except overrange) to be put
into a high impedance (3-state) condition.
The reference resistor ladder is composed of a string of
equal value resistors to provide 256 equally spaced voltages
for the comparators (see Figure 17 for the actual
configuration). The voltage difference between adjacent
comparators corresponds to 1 LSB of the input range. The
first comparator (closestto VRB) is referenced 1/2 LSB above
VRB, and 256th comparator (for the overrange) is referenced
1/2 LSB below VRT. The total resistance of the ladder is
nominally 130 n, ±20%, requiring 15.4 mA @ 2.0 V, and
7.7 mA @ 1.0 V. There is a nominal warm-up change of
~ +9.0% in the ladder resistance due to the +0.29%/OC
temperature coefficient.
The minimum recommended span [VRT - VRB] is 1.0 V. A
lower span will allow offsets and nonlinearities to become
significant. The maximum recommended span is 2.1 V due to
power limitations of the resistor ladder. The span may be
anywhere within the range of - 2.1 to + 2.1 V with respect to
ground, and VRB must be at least 1.3 V more positive than
VEE· The reference voltages must be stable and free of noise
and spikes, since the accuracy of a conversion is directly
related to the quality of the reference.
In most applications, the reference voltages will remain
fixed. In applications involving a varying reference for
modulation or signal scrambling, the modulating signal may
be applied to VRT, or VRB, or both. The output will vary
inversly with the reference signal, introducing a nonlinearity
into the transfer function. The addition of the modulating
signal and the dc level applied to the reference must be such
that the absolute voltage at VRT and VRB is maintained within
the values listed in the Recommended Operating Limits. The
RMS value of the span must be maintained .. 2.1 V.
VRM (Pin 1) is the midpoint of the resistor ladder, excluding
the Overrange comparator. The voltage at VRM is:
ANALOG SECTION
Signal Input
The signal. voltage to be digitized (Vin) is applied
simultaneously to one input of each of the 256 comparators
through Pin 14. The other inputs of the comparators are
connected to 256 evenly spaced voltages derived from the
reference ladder. The output code depends on the relative
position of the input signal and the reference voltages. The
comparators have a bandwidth of > 50 MHz, which is more
than sufficient for the allowable (Nyquist Theorem) input
frequency of 12.5 MHz.
The current into Pin 14 varies linearly from 0 (when
Yin = VRB) to ~60 jlA (when Yin =VRT). If Yin is taken below
VRB or above VRT, the input current will remain at the value
corresponding to VRB and VRT respectively (see Figure 5).
However, Yin must be maintained within the absolute range of
±2.5 V (with respect to ground) - otherwise excessive
currents will result at Pin 14, due to internal clamps.
The input capacitance at Pin 14 is typically 36 pF if
[VRT - VRB] is 2.0 V, and increases to 55 pF if [VRT - VRB]
is reduced to 1.0 V (see Figure 4). The capacitance is
constant as Yin varies from VRT down to ~0.1 V above VRB.
Taking Yin to VRB will show an increase in the capacitance of
~50%. If Yin is taken above VRT, or below VRB, the
capacitance will stay at the values corresponding to VRT
and VRB, respectively.
The source impedance of the signal voltage should be
maintained below 100 n (at the frequencies of interest) in
order to avoid sampling errors.
MOTOROLA ANALOG IC DEVICE DATA
V
RT
+V
2.0
RB _ 1/2 LSB
In most applications, bypassing this pin to ground (0.1 JlF) is
sufficient to maintain accuracy. In applications involving very
high frequencies, and where linearity is critical, it may be
necessary to trim the voltage at the midpoint. A means for
accomplishing this is indicated in Figure 18.
Power Supplies
VCC(A) is the positive power supply for the comparators,
and VCC(D) is the positive power supplyforthe digital portion.
Both are to be +5.0 V, ±10%, and the two are to be within
100 mV of each other. There is indirect internal coupling
between VCC(D) and VCC(A).lf they are powered separately,
and one supply fails, there will be current flow through the
MC10319 to the failed supply.
6-13
6
MC10319
ICC(A) is nominally 17 rnA, and does not vary with clock
frequency or with Vin. It does vary linearly with VCC(A).ICC(D)
is nominally 90 rnA, and is independent of clock frequency. It
does vary, however, by 6 to 7 rnA as Vin is changed, with the
lowest current occurring when Vin = VRT It varies linearly
with VCC(D).
VEE is the negative power supply for the comparators,
and is to be within the range - 3.0 to - 6.0 V. Additionally,
VEE must be at least 1.3 V more negative than VRS.IEE is a
nominal- 10 rnA, and is independent of clock frequency, Vin
and VEE.
'
For proper operation, the supplies must be bypassed at
the IC. A 10 J.lF tantalum, in parallel with a 0.1 J.lF ceramic is
recommended for each supply to ground.
DIGITAL SECTION
Clock
II
The Clock input is TTL compatible with a typical
frequency range of 0 to 30 MHz. There is no duty cycle
limitations, but the minimum low and high times must be
adhered to. See Figure 7 for the input current requirements.
The conversion sequence is shown in Figure 19, and is
as follows:
• On the rising edge, the data output latches are latched
with old data, and the comparator output latches are
released to follow the input signal (Vin).
• During the high time, the comparators track the input
signal. The data output latches retain the old data.
• On the falling edge, the comparator outputs are latched
with the data immediately prior to this edge. The
conversion to digital occurs within the device, and the
data output latches are released to indicate the new data
within 20 ns.
• Duringthe clock low time, the comparator outputs remain
latched, and the data output latches remain transparent.
A summary of the sequence is that data present at Vin
just prior to the Clock falling edge is digitized and
available at the data outputs immediately after that same
falling edge.
The comparator output latches provide the circuit with an
effective sample-and-hold function, eliminating the need for
an external sample-and-hold.
Enable Inputs
The two Enable inputs are TTL compatible, and are used
to change the data outputs (D7-DO) from active to 3-state.
This capability allows cascading two MC1 0319s into a 9-bit
configuration, flip-flopping two MC10319s into a 50 MHz
configuration, connecting the outputs directly to a data bus,
multiplexing multiple converters, etc. See the Applications
Information section for more details. For the outputs to be
active, Pin 19 must be a Logic "1", and Pin 20 must be a Logic
"0". Changing either input will put the outputs into the high
impedance mode. The Enable inputs affect only the state
of the outputs - they do not inhibit a conversion. The input
current into Pins 19 and 20 is shown in Figure 6, and the
input/output timing is shown in Figure 1 and 20. Leaving
either pin open is equivalent to a Logic "1", although good
design practice dictates that an input should never be
left open.
The Overrange output (Pin 3) is not affected by the Enable
inputs as it does not have 3-state capability.
Outputs
The Data outputs are TTL level outputs with high
impedance capability. Pin 4 is the MSS (D7), and Pin 21 is the
LSB (DO). The eight outputs are active as long as the Enable
inputs are true (Pin 19 =high, Pin 20 =low). The timing of the
outputs relative to the Clock input and the Enable inputs is
shown in Figures 1 and 20. Figures 8 and 9 indicate the
output voltage versus load current, while Figure 3 indicates
the leakage current when in the high impedance mode.
The output code is natural binary, depicted in the
table below.
The Overrange output (Pin 3) goes high when the input,
Vin, is more positive than VRT - 1/2 LSB. This output is
always active - it does not have high impedance capability.
Besides being used to indicate an input overrange, it is
additionally used for cascading two MC10319s to form a
9-bit AID converter (see Figure 27).
Table 1. Output Code
Input
>VRT-1/2LSB
VRT-1/2 LSB
VRT-1 LSB
VRT-1-1/2LSB
Midpoint
VRB+ 1/2 LSB
2.044V
2.044 V
2.040 V
2.036 V
1;024 V
4.0mV
0.9961 V
0.9961 V
0.992 V
0.988 V
0.000 V
-0.9961 V
<-1.0V
>0.9980 V
0.9980 V
0.9961 V
0.9941 V
0.5000 V
1.95mV
..~y----_./
Cloc!.J
.
latched.
(Valid data available after tCKOV)
Figure 22. Voltage Source for VRT Pin
+ 5.0 to
+ 40 V
O - -.....-:I::-I
n
1.25t02.00V
lM317L2 t:o~ut~-"""---- to VAT
Adj.
Data outputs latched, releases
Comparator latches.
J, 1.0 IlF
240
latches Comparator outputs,
opens data output latches.
510
200
LM317LZ
Figure 20. Enable to Output Critical Timing
. il-
00-07
' 'l,...2-1.--3-State
Line Regulation
TC (ppm/°C) max
AVout for 0 to + 70°C
Initial Accuracy
1.0mV
60
8.4mV
±4%
liming @ 07 to DO measured where waveform starts to change.
Indicated time values are typical @ 25°C, and are in ns.
6-18
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 23. Voltage Sources for VRB Pin
0.1
-5.0to
-40V
620
r
In
J.
LM337MT
10 ~F
- I
.....I
....
...... OR .......
I
I
-2.5 V L
-5.0
to
-40V
R1
R2
100
1.5
kQ
Out (- 1.25 to - 2.00 V)
...-Ad_i._ _-.
120
J.
to VRB
1.0~F
270
I
_J
R1
*0.1
2.5 V Reference
=100 Q for -5.0 V
= 620 Q for-15 V
Line Regulation
TC (ppm/'C) max
R2 = 620 Q for -5.0 V
3.0 kQ for-15 V
=
d Vout for 0 to + 70'C
Initial Accuracy
LM337MT
1.0mV
•
48
6.7mV
±4%
Figure 24. Composite Video Waveform
INPUT
OUTPUT
Figure 25. SIN2 x Waveform
INPUT-.
OUTPUT-.
MOTOROLA ANALOG IC DEVICE DATA
6-19
MC10319
Figure 26. Application Circuit for Digitizing Video
+s.OV
0-------.--.....---1__----,
14.3 MHz Clock ) - - - - - - - ,
EN VCC(A)
VCC(D)
EN
-=
-
CLK
~
VAM
OA
Ire!
MC10319
VAT
07
•
•
•
•DO
0.1
VAS
-=
II
Vin
VEE
1.5kO
GND
-S.2V
6200
1/2W
-2.5V
3.0kO
Output
Data
10flF
0.1*
-15V
-=
3.0pF
1.0kO
>10flF 250
Video Input
~I----WV--.......-I
(1.0Vpp)
500
NOTES: 1)
2)
3)
4)
5)
6-20
MC34080's powered from ± 15 V supplies. MC34083 (Dual) may be used.
Bypass capacitors required at power supply pins of alllCs.
Ground plane required over all parts of circuit board.
Care in layout around MC34080's necessary for good frequency response.
AI = MC34002.
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 27. 9-Bit AID Converter
GNO
EN
Oto25 MHz
Clock
OR
07
ClK
+2.0V
r
MC10319
VRT
0.1
VRM
VRB
••
••
00
EN
Yin VEE VCC(O) VCC(A)
0.1
500n
~
-5.2 V
ClK
VEE VCC(O) VCC(A)
0.1
r
.,..
-2.0V
VRT
VRB
EN
GNO
MOTOROLA ANALOG IC DEVICE DATA
08
07
07
••
••
00
Yin
+5.0V
OR
II
MC10319
ClK
Yin
OR
EN
VRM
00
latches
(Optional)
6-21
MC10319
Figure 28. 50 MHz 8-Bit AID Converter
SO MHz
Clock
CK
o
h
GNO
*""
Q
74F74 Q
EN
OR
EN
ClK
+1.0V
;.~
~
07
MC10319
VAT
(#1)
VRM
•••
•
DO
VRB
+S.OV
Yin VEE
VCC(O) VCC(A)
1$-"
$"
-
EN
'---
ri-
VEE
VCC(O) VCC(A)
VAT
VRM
.... 0.1
-1.0V
-S.2V
74F32
OR
OR
VRB
MC10319
ClK
(#2)
Yin
Yin
+S.OVO--- EN
r-07
07
•••
•
DO
==
== ' - - -
GNO
Latches
(Optional)
.l..
SO MHz Clock
••
•••
DO
I
I
Q~
I
I
00-07(#1) ---T-<,-:alid,9ata)
I
00-07(#2)~
--'-4~
S.SV)
7
8
MC34063A
2
0.16%
load Regulation
Yin =5.0 V. 8.0 mA <
lout < 20mA
0.4%
Output Ripple
Yin =5.0 V. lout =20 mA
2.0mVpp
Short Circuit lout
Yin
=5.0 V. R1 =0.1 0
Yin =5.0 V. lout =50 mA
140mA
Efficiency
3.0kQ
Results
4.5V < Yin < 5.5V.
lout = 10mA
2.20
6
Conditions
Test
Line Regulation
52%
1.0kQ
Vout
t-....r.,.,..,,,--++--o -5.0 VJ20 rnA
l470~F
MOTOROLA ANALOG IC DEVICE DATA
MC10319
GLOSSARY
Aperture Delay - The time difference between the sampling
signal (typically a clock edge) and the actual analog signal
converted. The actual signal converted may occur before or
after the sampling signal, depending on the internal
configuration of the converter.
Bipolar Input - A mode of operation whereby the analog
input (of an AID), or output (of a DAC), includes both
negative and positive values. Examples are - 1.0 to + 1.0 V,
- 5.0 to + 5.0 V, - 2.0 to + 8.0 V, etc.
Bipolar Offset Error - The difference between the actual
and ideal locations of the DOH to 01 H transition, where the
ideal location is 1/2 LSB above the most negative
reference voltage.
Load Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the load current is varied.
The error is typically expressed as a percent of the nominal
output voltage.
LSB - Least Significant Bit. It is the lowest order bit of a
binary code.
Monotonicity - The characteristic of the transfer function
whereby increasing the input code (of a DAC), or the input
signal (of an AID), results in the output never decreasing.
MSB - Most Significant Bit. It is the highest order bit of a
binary code.
Natural Binary Code - A binary code defined by:
N =An2n + ... + A323 + A222 + A121 + A020
Bipolar Zero Error - The error (usually expressed in LSBs)
of the input voltage location (of an AID) of the 80H to 81 H
transition. The ideal location is 1/2 LSB above zero volts in
the case of an AID setup for a symmetrical bipolar input
(e.g., - 1.0 to + 1.0 V).
where each "A" coefficient has a value of 1 or O. Typically, all
zeroes correspond to a zero input voltage of an AID, and all
ones correspond to the most positive input voltage.
Differential Nonlinearity - The maximum deviation in the
actual step size (one transition level to another) from the ideal
step size. The ideal step size is defined as the Full Scale
Range divided by 2n (n =number of bits). This error must be
within ± 1 LSB for proper operation.
Offset Binary Code - Applicable only to bipolar input (or
output) data converters, it is the same as Natural Binary,
except that all zeros correspond to the most negative input
voltage (of an AID), while all ones correspond to the most
positive input.
ECL - Emitter coupled logic.
Power Supply Sensitivity - The change in a data
converter's performance with changes in the power supply
voltage(s). This parameter is usually expressed in percent of
full scale versus tN.
Full Scale Range (Actual) - The difference between the
actual minimum and maximum end points of the analog input
(of an AID).
Full Scale Range (Ideal) - The difference between the
actual minimum and maximum end points of the analog input
(of an AID), plus one LSB.
Gain Error - The difference between the actual and
expected gain (end point to end point), with respect to the
reference, of a data converter. The gain error is usually
expressed in LSBs.
Grey Code - Also known as reflected binary code, it is a
digital code such that each code differs from adjacent codes
by only one bit. Since more than one bit is never changed at
each transition, race condition errors are eliminated.
Integral Nonlinearity - The maximum error of an AID, or
DAC, transfer function from the ideal straight line connecting
the analog end points. This parameter is sensitive to
dynamics, and test conditions must be specified in order to
be meaningful. This parameter is the best overall indicator of
the device's performance.
Line Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the input to the regulator
is varied. The error is typically expressed as a percent of the
nominal output voltage.
MOTOROLA ANALOG IC DEVICE DATA
Nyquist Theorem - See Sampling Theorem.
Quantitlzation Error - Also known as digitization error or
uncertainty. It is the inherent error involved in digitizing an
analog signal due to the finite number of steps at the digital
output versus the infinite number of values at the analog
input. This error is a minimum of ± 1/2 LSB.
Resolution - The smallest change which can be discerned
by an AID converter, or produced by a DAC. It is usually
expressed as the number of bits (n), where the converter has
2n possible states.
Sampling Theorem - Also known as the Nyquist Theorem.
It states that the sampling frequency of an AID must be no
less that 2x the highest frequency (of interest) of the analog
signal to be digitized in order to preserve the information of
that analog signal.
Unipolar Input:" A mode of operation whereby the analog
input range (of an AID), or output range (of a DAC), includes
values of a signal polarity. Examples are 0 to + 2.0 V, 0 to
- 5.0 V, 2.0 to 8.0 V, etc.
Unipolar Offset Error - The difference between the actual
and ideal locations of the DOH to 01 H tranSition, where the
ideal location is 112 LSB above the most negative
input voltage.
6-23
II
•
II
6-24
MOTOROLA ANALOG IC DEVICE DATA
Interface Circuits
In Brief ...
Described in this section is Motorola's line of interface
circuits, which provide the means for interfacing with
microprocessor or digital systems and the external world, or
to other systems.
Also included are devices which allow a microprocessor
to communicate with its own array of memory and peripheral
1/0 circuits.
The line drivers, receivers, and transceivers permit
communication between systems over cables of several
thousand feet in length, and at data rates of up to several
megahertz. The common EIA data transmission standards,
several European standards, and IEEE-488 are addressed
by these devices.
The peripheral drivers are designed to handle high
current loads such as relay coils, lamps, stepper motors, and
others. Input levels to these drivers can be TTL, CMOS, high
voltage MOS, or other user defined levels. The display
drivers are designed for LCD or LED displays, and provide
various forms of decoding.
MOTOROLA ANALOG IC DEVICE DATA
Page
Enhanced Ethernet Transceiver .................... 7-2
ISO 8802-3[IEEE 802.3110BASE-TTransceiver ..... 7-3
Hex EIA-485 Transceiver with
Three-State Outputs ............................. 7-4
5.0 V, 200 M-BiVSec PR-IV Hard Disk
Drive Read Channel ............................. 7-5
Microprocessor Bus Interface ...................... 7-7
Magnetic ReadlWrite ........................... 7-7
Single-Ended Bus Transceivers .................... 7-7
For Instrumentation Bus, Meets
GPIBIIEEE Standard 488 ...................... 7-7
For High Current Party-Line Bus for Industrial and
Data Communications ......................... 7-7
Line Receivers ................................... 7-7
General Purpose .............................. 7-7
EIA Standard .................................. 7-7
Line Drivers ..................................... 7-8
EIA Standard .................................. 7-8
Line Transceivers .............................. 7-8
EIA-232-EN.28 CMOS Drivers/Receivers ........ 7-8
Peripheral Drivers ............................. 7-9
IEEE 802.3 Transceivers ........................ 7-9
ReadlWrite Channel .............................. 7-9
Drive Read Channel ............................ 7-9
Inkjet Drivers .................................... 7-9
28-Channellnkjet Driver ........................ 7-9
CMOS Display Drivers ........................... 7-10
Package Overview .............................. 7-11
Device Listing ................................... 7-12
7-1
•
Enhanced Ethernet Transceiver
MC68160FB
TA
= 0° to +70°C, Case 848D
The MC68160 Enhanced Ethernet Interface Circuit is a
BiCMOS device which supports both IEEE 802.3 Access Unit
Interface (AUI) and 10BASE-T Twisted Pair (TP) Interface
media connections through external isolation transformers. It
encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via
10BASE-T or AUI interfaces. The MC68160 gluelessly
RX
RCLK
MFILT
interfaces tothe Ethernet controller contained in the MC68360
Quad Integrated Communications Controller (QUICC) device.
The MC68160 also interfaces easily to most other
industry-standard IEEE 802.3 LAN controllers. Prior to
twisted pair data reception, Smart Squelch circuitry qualifies
input signals for correct amplitude, pulse width, and sequence
requirements.
Manchester
Decoder
ARX+
RXLED
RENA
CLLED
ARX-
Mux
ACX+
w
ACX- c.J
w CLSN
~TXLED
~
ATX- a::
a::
II
w
....
w TENA
~
TX
~
ATX+ 2E
5
X1
Twisted
Pair
Polarity
Error
Control
X2 :
TCLK
~fJ
CS1
CS2
TPEN
APORT
TPAPCE
TPSQEL
TPFULDL
LOOP
Mode
Select
TPJABB
7-2
«
TPTX+ TPTX-
TPLIL
TPSQEL
TPRX-
TPRX+ TPPLR
MOTOROLA ANALOG IC DEVICE DATA
ISO 8802-3[IEEE 802.3] 10BASE-T Transceiver
MC34055DW
TA= 0° to +70°C, Case 751E
The Motorola 10BASE-T transceiver, designed to comply
with the ISO 8802-3[IEEE 802.3)10BASE-T specification,
will support a Medium Dependent Interface (MOl) in an
embedded Media Attachment Unit (MAU). The interface
supporting the Data Terminal Equipment (DTE) is TTL,
CMOS, and raised ECl compatible, and the interface to the
Twisted Pair (TP) media is supported through standard
10BASE-T filters and transformers. Differential data intended
for the TP media is provided a 50 ns pre-emphasis and data
at the TP receiver, is screened by Smart Squelch circuitry for
specific threshold, pulse width, and sequence requirements.
Loop Back
Test Select
Balun
TX Data A
Data Out
3 TXData B
4
TXENH
8 RXDataA
9 RXDataB
to RXENH
SIA
14
CTLH
13 JABB H
22 SQE EN L
Duplex
Mode
Select
MOTOROLA ANALOG IC DEVICE DATA
7-3
•
Hex EIA-485 Transceiver with Three-State Outputs
MC340S8IS9FTA
TA
= 0° to +70°C, Case 932
The Motorola MC34058/9 Hex Transceiver is composedof
six driver/receiver combinations designed to comply with the
EIA-485 standard. Features include three-state outputs,
thermal shutdown for each driver, and current limiting in both
directions. This device also complies with EIA-422 and
CCID Recommendations V.11 and X.27.
The devices are optimized for balanced multipoint bus
transmission at rates to 20 MBPS (MC34059). The driver
outputs/receiver inputs feature a wide common mode voltage
range, allowing for their use in noisy environments. The
current limit and thermal shutdown features protect the
devices from line fault conditions.
The MC34058/9 is available in a space saving 7.0 mm 48
lead surface mount quad package designed for optimal heat
dissipation.
• Meets EIA-485 Standard for Party Line Operation
• Meets EIA-422A and CCID Recommendations V.11 and
X.27
• Operating Ambient Temperature: O°C to +70°C
• Common Mode Driver Output/Receiver Input Range: -7.0
to +12V
• Positive and Negative Current Limiting
• Transmission Rates to 14 MBPS (MC34058) and 20
MBPS (MC34059)
• Driver Thermal Shutdown at 150°C Junction Temperature
• Thermal Shutdown Active Low Output
• Single +5.0 V Supply, ±10%
• Low Supply Current
• Compact 7.0 mm 48 Lead TQFP Plastic Package
• Skew Specified for MC34059
II
Gnd
36 Gnd
Gnd
35 OA5
OA6
3
34 065
066
4
DR4
DR1
OA4
OAl
064
061
DE4
DEl
8
29 RE4
REl
9
28 063
062
10
27 OA3
OA2
11
26 Gnd
Gnd
12
25 Gnd
Gnd
7-4
Gnd
DE2
RE2
DR2
DR3
RE3
DE3
Gnd
MOTOROLA ANALOG IC DEVICE DAT~
5.0 V, 200 M-BitiSec PR-IV Hard Disk Drive Read Channel
MC34250FTA
TA = 0° to +70°C, Case 840F
The Motorola MC34250 is a fully integrated partial
response maximum likelihood disk drive read/write channel
for use in zoned recording applications. This device integrates
the AGC, active filter, 7 tap equalizer, Viterbi detector,
frequency synthesizer, servo demodulator, 8/9 rate (0,4/4)
Encoder/Decoder with write precompensation and power
management in a single 64 pin 10 mm x 10 mm TQFP
package.
• Programmable Asymmetrical Boost of Up to ±40% of
Nominal Filter Group Delay in Both Data and Servo
Modes
FEATURES:
• Fast Acquisition Data Phase locked loop with Zero
Phase Restart
• 50 to 200 MBPS Programmable Data Rate
• 800 mW at 200 MBPS and 5.0 V
• Channel Monitor Output
• Programmable AGC Charge Pump Currents with
Different Values for Data and Servo Envelope Modes and
Gain Gradient Mode
• Programmable AGC Peak Detector Droop Currents with
Different Values for Data and Servo Envelope Modes
• Separate AGC Charge Pump Outputs for Data and Servo
Modes
• Programmable Dual Threshold Qualifier or Hysteresis
Comparator Type Pulse Detector for Servo Data
Detection.
• ERD and Polarity Outputs for Servo Timing and Raw
Encoded Data
• Integrated 7 pole 0.05° Equiripple Linear Phase Filter with
Programmable Bandwidth from 5.0 MHz to 80 MHz and
Different Values for Both Data and Servo Modes
• Programmable Symmetrical Boost from 0 to 10 dB and
Different Values for Data and Servo Modes
MOTOROLA ANALOG IC DEVICE DATA
• 7 Tap Continuous Time Transversal Equalizer with 8 Bit
Programmable Tap Weights and Integrated Decision
Directed Sign-Sign least Mean Squared Adaptation
• Internal Offset Cancellation loops
• Programmable Data Phase locked loop Charge Pump
Current
• Integrated Soft Decision Viterbi Detectors with
Programmable Merge References
• Integrated 8/9 Rate (0,4/4) Encoder and Decoder with
Code Scrambler and Descrambler
• Programmable 21418 Bit NRZ Data Interface
• Programmable Write Precompensation Delays locked to
the Frequency Synthesizer
• Differential PECl Write Data Outputs
• External Write Data Path for DC Erase or Other
Non-Encoded Data
• Integrated Write Current DAC
• Programmable Power Management
• Bi-Directional Serial Microprocessor Interface
• Various Test Modes Controlled Via the Serial
Microprocessor Interface
7-5
•
..
~I
'" '" '" '"
::0
::0
~
"'tJ
ED
:ii
:1i! :1i! ~ g ~ ~
~ :::c g -I -t --f -i
CD
!:H
--f
~ ~
UI
b
::0
:D
~~ClJcn~~~ en
(f)
~
~
<:>
<:>
.."
.."
-0
~<
-0
,....
,....
,.... -0
,....
;;::
N
0
0
s:::I
I:D
s::
~
0
Co)
Thresholds
""
CD
0
I\)
UI
Q
."
::D
CLAMPB
0
-
I
_._- --------
l.
t--I
r--1
Path Memory
I
-t-OATP1M
<
::J:
.1»
t\lr£1V1
VINP
c
VINM
HOLDB
CDATA~ Mux
CSRVO
8/9 (0.414) ENDEC
Synchronization
Byte Detect
h
CREG
:a
0
SLEEPB
Power
Manager
f f
Mode
l>
l>
r0
C>
(')
C
FREF
Fre~uency
Synt esizer
ZoneClk
WCDAC
Data
-~
I·
Write
Precompensation
WDATAP
WDATAM
en en
-< -<
~
:I: ~
.."
-0
.."
;;::
~
Z
:I:
'"
~
:E
m
m
en
Z
en
m
~
.CD
8'a
3'
SDATA
SCLK
<
il
::I
::I
MCU Interface
m
(')
::D
CD
I»
I»
SLATCH
Z
:C'
CD
::r
Coefficients
>
~
..,C
(')
Offset
Cancel
CFILT
ii'
a.
rnresnOias
RBIAS
a
SYNCDET
NRZ(7:0)
NRZCLK
READGT
WRITEGT
'-------'
SRVOGT 0
!!:
a
C
CD
.....a.
Microprocessor Bus Interface
Motorola offers a spectrum of line drivers and receivers
which provide interfaces to many industry standard
specifications. Many of the devices add key operational
features, such as hysteresis, short circuit protection, clamp
diode protection, or special control functions.
Table 1. Magnetic ReadlWrite
Device
MC3467'
Comments
Magnetic Tape Sense Amplifier. Trace independent preamplifiers with individual gain
control. Optimized for use with 9-track magnetic tape memory systems .
TA
eC)
Suffix!
Package
Oto+70
P1707
• Not recommended for new designs.
Single-Ended Bus Transceivers
Table 2. For Instrumentation Bus, Meets GPIB/IEEE Standard 488
Driver Characteristics
Receiver Characteristics
Output
Current
(rnA)
Propagation
Delay
Max (ns)
Propagation
Delay
Max (ns)
Transceivers
Per Package
Device
Suffix!
Package
48
17
25
4
MC3448A'
P/648,
Comments
Input hysteresis, open coliector,
3-state outputs with terminations
01751B
"'Not recommended for new deSigns.
Table 3. For High Current Party-Line Bus for Industrial and Data Communications
Driver Characteristics
Receiver Characteristics
Output
Current
(rnA)
Propagation
Delay
Max (ns)
Propagation
Delay
Max (ns)
Transceivers
Per Package
Device
100
15
15
4
MC26S10'
Suffix!
Package
Comments
Open collector outputs, common
enable
P/648,
0/751B
"Not recommended for new designs.
Line Receivers
Table 4. General Purpose
S= Single
Ended
0= Differ·
entlal
0
Type
of
Output
TP
OC(l)
tprop
Delay
Time
Max (ns)
Party
Line
Operation
Strobe
or
Enable
Power
Supplies
25
V
V
±5.0
(V)
Device
MC3450'
Suffix!
Package
Receivers
Per
Package
P/648
4
Receivers
Per
Package
Companion
Drivers
MC3453
Comments
Quad
(1) OC = Open Collector, TP = Totem-pole output.
.. Note recommended for new designs.
Table 5. EIA Standard
S= Single
Ended
0= Differential
Type
of
Output
tprop
Delay
Time
Max (ns)
Party
Line
Operation
Strobe
or
Enable
Power
Supplies
(V)
Device
Suffix!
Package
S
TP
4000
-
-
+5.0
MC14C89B,
AB
P/646,
01751 A
R(l)
85
-
-
TP
30
V
V
S,O
35
4
Companion
Drivers
MC1488
MC14C88B
MC1489
MC1489A
Comments
EIA-232-01
EIA-562
EIA-232-0
AM26LS32'
PC/648
AM26LS31,
EIA-422/423
SN75175
N/648,
MC75174B
EIA-4221423/
485
0/751B
(1) R = Resistor Pull-up, TP = Totem-pole output.
.. Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
7-7
•
I
I
Line Drivers
Table 6. EIA Standard
Output
Current
Capebility
(mA)
t prop
Delay
Time
Max (ns)
S= Single
Ended
0= Differential
Party
Line
Operation
Strobe
or
Enable
Power
Supplies
(V)
Device
85
35
0
V
V
+5.0
48
20
15
3500
10
350
60
300
-
S
EIA-
SlO
422
Drivers
Per
Package
MC75174B
MC75172B
P/648
4
AM26LS31*
PC/648
MC26LS31
01751B
±7.0to
±12
MC14C88B
P/646,
01751 A
±9.0to
±12
MCI488
±5.0
AM26LS30
PC/648
MC26LS30
01751B
2 (422)
4(423)
V
EIA423 -
•
Suffix!
Package
Companion
Receivers
Comments
SN75175
EIA-485
MC3486
AM26LS32*
EIA-422
with 3-state
outputs
MC14C89B
MCI4C89AB
EIA-232-0/
EIA-562
MC1489
MCI489A
EIA-232-0
AM26LS32*
EiA-422or
EIA-423
Switchabie
* Not recommended for new deSIgns .
Table 7. Line Transceivers
Driver
Prop
Delay
(Max ns)
Receiver
Prop
Delay
Max (ns)
23
23
DE =Drlver
Enable
RE =Receiver
Enable
OE,RE
Party
Line
Operation
Power
Supplies
V
+5.0
Device
Suffix!
Package
Drivers
Per
Package
Receivers
Per
Package
MC34058
FTAl932
6
6
EIA-485
to 14MBPS
MC34059
FTAl932
6
6
EIA-485
t020MBPS
(V)
EIA
Standard
Table 8. EIA-232-EN.28 CMOS Drivers/Receivers
Suffix!
Package
Pins
Drivers
Receivers
Power
Supplies (V)
MC145403
P1738,
20
3
5
±5.0 to±12
MC145404
OW1751 0
Device
MCI45405
MC145406
MC145407
P/648,
OW1751G,
SO/940B
16
P1738,
20
4
4
5
3
Features
3
+5.0
Charge Pump
OW1751D
MC145408
P1724,
OW1751E,
SO/940B
24
5
5
±5.0 to ±12
MC145583
OW1751F,
VF/940J
28
3
5
+3.3 to +5.0
MC145705
P1738,
OW1751D
20
2
3
+5.0
3
2
P1724,
OW1751E
24
MC145706
MCI45707
7-8
On-board ring monitor circuit;
charge pump, power down
Charge Pump, Power Oown
3
MOTOROLA ANALOG Ie DEVICE DATA
Table 9. Peripheral Drivers
Output
Current
Capability
(mA)
500
Input
Capability
Propagation
Delay Time
Max (Ils)
Output
Clamp
Diode
Off State
Voltage
Max (V)
TTL,CMOS
1.0
V
50
6.0Vto 15V
MOS
1500
Device
UlN2803
Drivers
Per
Package
Suffix!
Package
Logic
Function
8
M07
Invert
7
P/648,
D1751B
P/648,
D1751B
4
B/648C
UlN2804
TTl,5.0V
CMOS
MC1413, B
(UlN2003A)
8.0 Vto 18 V
MOS
MC1416, B
(UlN2004A)
V
50
10 BaseT
NRZ
IEEE
Transmit and
Receive over
4 Pins
Raised
ECl,
CMOS
802.3 Type
10BaseT
Transceiver with non-return to zero (NRZ)
interface. Intended for but not restricted to
concentrators and repeator applications .
DW1751E
TTl,CMOS
802.3 Type
10BaseTI
AUI/NRZ
Interfaces gluelessly to Motorola's MC68360
communications controller.
FB/848D
TTl,5.0V
CMOS
1.0
UlN2068*
Invert
.. Not recommended for new designs.
Table 10. IEEE 802.3 Transceivers
Device
MC34055
Power
Supply
+5.0Vdc
MC68160
Suffix!
Package
Comments
ReadlWrite Channel
Table 11. Hard Disk Drive Read Channel
Device
MC34250
Power
Supply
('C)
Suffix!
Package
Oto+70
FTAl840F
TA
('C)
Suffix!
Package
Oto +70
FNI777
TA
Comments
5.0V
200 Mbps fully integrated partial response maximum likelihood hard disk
drive read/write channel which equalizes to a PR-IV shape and uses 8/9
rate (0, 4/4) coding.
Inkjet Drivers
Table 12. 28-Channel Inkjet Driver
Device
MC34156
Power
Supply
5.0V
Comments
A 4 to 14 line decoder determines the selected output driver in each of
two 14 driver banks. Two independent output enable lines permit 1 or 2 of
28 outputs. Outputs are open collector 30 V Darlington drivers capable of
sinking 500 mAo
MOTOROLA ANALOG IC DEVICE DATA
7-9
•
CMOS Display Drivers
range of end equipment such as instruments, automotive
dashboards, home computers, appliances, radios and Clocks.
These CMOS devices include digit as well as matrix drivers
for LEDs, LCOs, and VFOs. They find applications over a wide
Table 13. Display Drivers
Display Type
LCD
(Direct Drive)
MuxedLCD
(1/4 Mux)
LED,
Incandescent,
Fluorescent(1 )
II
Muxed LED
(1/4 Mux)
MuxedLED
(1/5 Mux)
Input Format
Drive Capability
Per Package
On-Chip
Latch
Display Control
Segment Drive
Current
Device
ParalielBCD
7 Segments
V
Blank
= 1.0mA
MC14543B
Blank, Ripple Blank
Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUsj
Parallel BCD
MC14544B
33 Segments
or Dots
20pA
MC145453
48 Segments
or Dots
= 200 pA
MC145000
MC145001
44 Segments
or Dots
Blank, Lamp Test
7 Segments
25 rnA
Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUsj
4 Digits +
Decimals
-
Blank
65 rnA
MC14547B
V
Oscillator
(Scanner)
50 rnA
(Peak)
MC14499
Oscillator (Scanner),
Low Power Mode,
Dimming
Ot035rnA
(Peak)
Adjustable
MC14489
1OmA(2)
MC14495-1
-
MC14558B
5 Characters +
Decimals or 25
Lamps
LED
(Direct Drive)
Parallel Hex
7 Segments +
A thru F Indicator
(Interfaces to
Display Drivers)
Parallel BCD
7 Segments
MC14511B
MC14513B
Blank, Ripple Blank,
Lamp Test
-
Ripple Blank,
Enable
(1) Absolute maximum working vottage = 18 V.
(2) On-chip current-limtting resistor.
Table 14. Functions
Device
MC14489
Package
Function
Multi-Character LED Display/Lamp Driver
738,7510
MC14495-1
Hexadecima\-to-7 Segment Latch/Decoder ROM/Driver
648,751G
MC14499
4-Digit 7-Segment LED Display Decoder/Driver with Serial Interface
707, 7510
MC14511B
BCD-to-7-Segment Latch/DecoderlDriver
648,751G
MC1.4513B
BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking
726,707
MC14543B
BCD-to-7-Segment Latch/Decoder/Driver for Liquid Crystals
620,648
MC14544B
BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking
726,707
MC14547B
High-Current BCD-to-7-Segment Decoder/Driver
620,648
MC14558B
BCD-to-7-Segment Decoder
620,648
MC145000
48-Segment Serial Input Multiplexed LCD Driver (Master)
709,776
MC145001
44-Segment Serial Input Multiplexed LCD Driver (Slave)
707,n6
MC145453
33-8egment, Non-Multiplexed LCD Driver with Serial Interface
711,n7
7-10
MOTOROLA ANALOG IC DEVICE DATA
Interface Circuits Package Overview
-CASE 646
PSUFFIX
CASE 620
CASE 648
N, P, PC SUFFIX
CASE 709
PSUFFIX
-- CASE 724
P SUFFIX
CASE 711
P SUFFIX
CASE 751A
DSUFFIX
CASE 707
A SUFFIX
CASE 751B
DSUFFIX
CASE 751D
DWSUFFIX
• •
• •
CASE 726
CASE 751E
DWSUFFIX
CASE 751G
DWSUFFIX
CASE 776
FN SUFFIX
CASEn7
FNSUFFIX
CASE 848D
FBSUFFIX
CASE 932
FTASUFFIX
CASE 940B
SDSUFFIX
MOTOROLA ANALOG IC DEVICE DATA
•
CASE 738
PSUFFIX
CASE 751F
DWSUFFIX
•
CASE840F
FTASUFFIX
CASE 940J
VFSUFFIX
7-11
Device Listing
Interface Circuits
II
Device
Function
AM26LS30
Dual Differential (EIA-422-:-A)/Quad Single-Ended
(EIA-423-A) Line Drivers ............................. " ....... 7-13
Quad Line Driver with NAND Enabled Three-State Outputs . . . . . . . . . .. 7-24
Quad EIA-4221423 Line Receiver with Three-State Outputs .......... 7-27
High Voltage, High Current Darlington Transistor Arrays .............. 7-30
Quad Line Driver ................................................ 7-33
Quad Line Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-39
Quad Low Power Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-44
Quad Low Power Line Receivers .................................. 7-50
Ouad Open-Collector Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-55
Quad Bidirectional Instrumentation Bus (GPIB) Transceiver . . . . . . . . . .. 7-58
Quad MTTL Compatible Line Receivers ............................ 7-e4
MTTL Compatible Quad Line Driver ................................ 7-71
Triple Wideband Preamplifier with Electronic Gain Control (EGC) ...... 7-76
Quad Single-Ended Line Drivers .................................. 7-81
Dual EIA-423/EIA-232D Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-86
IEEE 802.3 1OBASE-T Transceiver ................................ 7-90
Hex EIA-485 Transceiver with Three-State Outputs ................. 7-105
28-Channellnkjet Driver ......................................... 7-116
5.0 V, 200 M-BitiSec PR-IV Hard Disk Drive Read Channel .......... 7-118
Enhanced Ethernet Transceiver ...................... '" .......... 7-120
Quad EIA-485 Line Drivers with Three-5tate Outputs ................ 7-146
Quad EIA-485 Line Receiver ..................................... 7-157
Quad 1.5 A Sinking High Current Switch ............................ 7-162
Octal High Voltage, High Current Darlington Transistor Arrays ......... 7-166
AM26LS31*
AM26LS32*
MC1413, B, MC1416, B
MC1488
MC1489,A
MC14C88B
MC14C89B, MC14C89AB
MC26S10*
MC3448A*
MC3450*
MC3453*
MC3467*
MC3481*, MC3485*
MC3488A
MC34055
MC34058, MC34059
MC34156
MC34250
MC68160
MC75172B, MC75174B
SN75175
ULN2068*
ULN2803, ULN2804
Page
NOTE: • Not recommended for new designs.
7-12
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
AM26LS30
Dual Differential (EIA-422-A)/
Quad Single-Ended
(EIA-423-A) Line Drivers
The AM26LS30 is a low power Schottky set of line drivers which can be
configured as two differential drivers which comply with EIA-422-A
standards, or as four single-ended drivers which comply with EIA-423-A
standards. A mode select pin and appropriate choice of power supplies
determine the mode. Each driver can source and sink currents in excess of
50mA.
In the differential mode (EIA-422-A), the drivers can be used up to
10 Mbaud. A disable pin for each driver permits setting the outputs into a
high impedance mode within a ±10 V common mode range.
In the single-ended mode (EIA-423-A), each driver has a slew rate
control pin which permits setting the slew rate of the output signal so as to
comply with EIA-423-A and FCC requirements and to reduce crosstalk .
When operated from symmetrical supplies (±5.0 V), the outputs exhibit zero
imbalance.
The AM26LS30 is available in a 16-pin plastic DIP and surface mount
package. Operating temperature range is -40° to +85°C.
• Operates as Two Differential EIA-422-A Drivers, or Four Single-Ended
EIA-423-A Drivers
DUAL DIFFERENTIAU
QUAD SINGLE-ENDED
LINE DRIVERS
SEMICONDUCTOR
TECHNICAL DATA
PC SUFFIX
PLASTIC PACKAGE
CASE 648
•
FN SUFFIX
PLASTIC PACKAGE
CASE 775
a
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
• High Impedance Outputs in Differential Mode
• Short Circuit Current Limit In Both Source and Sink Modes
PIN CONNECTIONS
• ± 10 V Common Mode Range on High Impedance Outputs
• ± 15 V Range on Inputs
• Low Current PNP Inputs Compatible with TTL, CMOS, and MOS
Outputs
• Individual Output Slew Rate Control in Single-Ended Mode
• Replacement for the AMD AM25LS30 and National Semiconductor
DS3691
Vee
SA-A
InpuIA
~
EnableAB
Mode
Output A
4 Output B
1
Gnd
~
Enable CD
InputD
VEE
SR-B
SR-C
OutputC
Output D
SR-D
(Top View)
Representative Block Diagrams
Single-Ended Mode
EIA-423-A
-C>==SR-A
Input A
Out A
InputB
Differential Mode
EIA-422-A
EnableAB
Input A
QutA
OutB
InputD
QutC
OutD
-c>==SA-B
OutB
InputC
-C>==SR-C
OutC
InputD
-c>==SA-D
Out D
Enable CD
MOTOROLA ANALOG IC DEVICE DATA
VCC-l
VEE-8
Gnd-5
Mode-4
In BiEnAB
OutB
Mode
SR-B
NC
NC
Gnd
SR-C
In C/En CD
OutC
ORDERING INFORMATION
Operating
Temperature Range Package
Device
AM26LS30PC
MC26LS30D
AM26LS30FN
TA = - 40° to +85°C
Plastic DIP
S0-16
PLCG-20
7-13
AM26LS30
MAXIMUM OPERATING CONDITIONS (Pin numbers refer to DIP and 90-16
packages only.) .
Rating
Power Supply Voltage
Symbol
Value
Unit
Vee
VEE
-0.5,+7.0
-7.0,+0.5
Vdc
Input Voltage (All Inputs)
Vin
-0.5, +20
Vdc
Applied Output Voltage when in High Impedance Mode
(Vee = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1)
Vza
±15
Vdc
Output VoHage with Vee, VEE = 0 V
Vzb
±15
10
Self limiting
-
TJ
--65,+150
°e
Output Current
Junction Temperature
Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides
conditions for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Rating
II
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (Differential Mode)
Vee
VEE
+4.75
-0.5
5.0
0
+5.25
+0.3
Vdc
Power Supply Voltage (Single-Ended Mode)
Vee
VEE
+4.75
-5.25
+5.0
-5.0
+5.25
-4.75
Input Voltage (All Inputs)
Applied Output Voltage (when in High Impedance Mode)
Applied Output Voltage, Vee 0
Vin
Vza
Vzb
0
-10
-10
-
+15
+10
+10
Vdc
-
10
--65
-
+65
mA
TA
-40
-
+85
°e
=
Output Current
Operating Ambient Temperature (See text)
All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (EIA-422-A differential mode, Pin 4 .. 0.8 V, -40°C 2.0 V.
7-14
MOTOROLA ANALOG IC DEVICE DATA
AM26LS30
TIMING CHARACTERISTICS (EIA-422-A differential mode, Pin 4 .. O.S V, TA = 25°C, VCC = 5.0 V, VEE = Gnd, (Notes 1 and 3)
unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Differential Output Rise Time (Figure 3)
tr
70
200
ns
Differential Output Fall Time (Figure 3)
tf
-
70
200
ns
Propagation Delay Time - Input to Differential Output
Input Low to High (Figure 3)
Input High to Low (Figure 3)
tpDH
tpDL
-
90
90
200
200
Skew Timing (Figure 3)
I tpDH to tpDL I for Each Driver
Max to Min tpDH Within a Package
Max to Min tpDL Within a Package
tSKl
tSK2
tSK3
-
9.0
2.0
2.0
-
-
Enable Timing (Figure 4)
Enable to Active High Differential Output
Enable to Active Low Differential Output
Enable to 3-State Output From Active High
Enable to 3-State Output From Active Low
tpZH
tpZL
tPHZ
tPLZ
-
150
190
SO
110
300
350
350
300
Characteristic
ns
ns
ns
-
-
ELECTRICAL CHARACTERISTICS (EIA-423-A single-ended mode, Pin 4 '" 2.0 V, -40°C < TA < S5°C, 4.75 V .. IVccl,
IVEE I .. 5.25 V, (Notes 1 and 3) unless otherwise noted).
Characteristic
Symbol
Min
Typ
Max
IVOll
IV 021
4.0
3.6
-
4.2
3.95
0.05
6.0
6.0
0.4
-
±120
-
~
10LK
-100
a
+100
~
ISC+
ISC+
ISCISC-
60
50
-150
-150
SO
150
150
-60
-50
mA
O.S
Vdc
Vdc
I~V021
Slew Control Current (Pins 16,13,12,9)
ISLEW
Output Current (Each Output)
Power Off Leakage, VCC = VEE = 0, -6.0 V .. Vo .. +6.0 V
Short Circuit Current (Output Short to Ground, Note 2)
Vin .. O.S V (TA = 25°C)
Vin .. O.S V (-40°C < TA < +S5°C)
Vln :. 2.0 V (TA = 25°C)
Vin ;;, 2.0 V (-40°C < TA < +S5°C)
Unit
Vdc
Output Voltage (VCC = IVEE I = 4.75 V)
Single-Ended Voltage, RL = 00 (Figure 2)
Single-Ended Voltage, RL = 450 n, (Figure 2)
Voltage Imbalance (Note 5), RL = 450 n
Inputs
Low Level Voltage
High Level Voltage
Current @ Vin = 2.4 V
Current @ Vln = 15 V
Current @ Vin = 0.4 V
Current, 0 .. Yin .. 15 V, VCC = 0
Clamp Voltage (lin = -12 mAl
VIL
VIH
IIH
IIHH
IlL
IIX
VIK
Power Supply Current (Outputs Open)
VCC = +5.25 V, VEE = -5.25 V, Vin = 0.4 V
ICC
lEE
-
-
-95
-
-
a
a
-200
-8.0
-1.5
a
-
-
Vdc
-
17
30
mA
-22
-S.O
-
2.0
-
40
100
~A
TIMING CHARACTERISTICS (EIA-423-Asingle-ended mode, Pin4 .. 2.0 V, TA = 25°C, VCC = 5.0 V, VEE =-5.0 V, (Notes 1 and 3)
unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Output Timing (Figure 5)
Output Rise Time, Cc = 0
Output Fall Time, Cc =
Output Rise Time, Cc = 50 pF
Output Fall Time, Cc = 50 pF
tr
tf
tr
tf
-
65
65
3.0
3.0
300
300
ns
-
Rise Time Coefficient (Figure 16)
Crt
Characteristic
a
Propagation Delay Time, Input to Single Ended Output (Figure 5)
Input Low to High, Cc =
Input High to Low, Cc =
a
a
MOTOROLA ANALOG IC DEVICE DATA
0.06
-
~s
IJSIpF
ns
tPDH
tPDL
-
-
100
100
300
300
tSK4
tSK5
tSK6
-
15
2.0
5.0
-
a
Skew Timing, Cc = (Figure 5)
I tpDH to tPDLI for Each Driver
Max to Min tpDH Within a Package
Max to Min tpDL Within a Package
-
-
ns
-
7-15
a
AM26LS30
Table 1
Inputs
Operation
Vee
Differential
(EIA-422-A)
+5.0
Single-Ended
(EIA-423-A)
Outputs
VEE
Mode
A
B
e
0
A
B
e
0
Gnd
0
0
0
0
0
0
0
1
X
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
1
1
0
1
X
0
1
1
0
Z
Z
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
1
Z
Z
+5.0
-5.0
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
X
X
X
X
X
X
Z
Z
Z
Z
X
x= Don't Care
Z = High Impedance (Off)
•
Figure 1. Differential Output Test
Figure 2. Single-Ended Output Test
Vee
r
Yin
(0.8 or 2.0 V)
Rlf2
vr
2
Rlf2
Mode=O
Yin
(0.8 or 2.0 V)
~s
T
Vo
~
Mode = 1
"::"
Figure 3. Differential Mode Rise/Fail Time and Data Propagation Delay
100
500 pF
i
r-----------~ +3.0 V
1.5V
OV
IPOL
VOD
I
90%
Ir
If
NOTES: 1. S.G. set to: f .. 1.0 MHz; duty cycle = 50%; to tf, .. IOns.
2. tSKI = itPDH""tPDLi for each driver.
3. tSK2 computed by subtracting the shortest tpDH from the longest tpDH of the 2 drivers w~hin a package.
4. tSK3 computed by subtracting the shortest tpDL from the longest tpDL of the 2 drivers within a package.
7-16
MOTOROLA ANALOG IC DEVICE DATA
AM26LS30
Figure 4. Differential Mode Enable TIming
, -_ _ _ _ _ _ _ _ _ _ _ _--,.+3.0 V
Vee
Rl
1.5 V
t
VSS
1.5 V
' - - - - OV
I
(Vin =Hi)
Output
Current
(Vin = la)
NOTES: 1. S.G. setto: f "' 1.0 MHz; duty cycle = 50"/0;10 If. "' 10 ns.
2. Above lests conducted by monitoring output current levels.
Figure 5. Single-Ended Mode Rlse/Fall Time and Data Propagation Delay
r-_ _ _ _ _ _ _ _ _ _ _
Vee
~+2.5V
1.5V
OV
tPOl
500PFT
Vo
*
tf
NOTES: 1. S.G. setto: f "' 100 kHz; duty cycle = 50%; to tf. ",10 os.
2.tSK4 = ItPDfr\pod for each driver.
3.tSK5 computed by subtracting the shortest tpOH from the 10ngesttpOH of the 4 drivers wnhin a package.
4.tSK6 computed by subtracting the shortest tpOL from the 10ngesttpOl of the 4 drivers wHhin a package.
MOTOROLA ANALOG IC DEVICE DATA
7-17
AM26LS30
Figure 6. Differential Output Voltage
versus Load Current
Figure 7. Internal Bias Current
versus Load Current
5.0
40
~ 4.0
L1J
........
~
"
r-
!j
~ 3.0
O~
r-
2.0 -
~
- -- -
Differential Mode
_ Mode =0
Supply Current = Bias Curr.ent + Load Current
Differential Mode
Mode = 0, VCC = 5.0 V
r-- r--
=o'.~T
-fv
8
::> 1.0
V C=5.25V
1D
10
20
30
40
10, OUTPUT CURRENT (rnA)
50
10
60
•
+100
-20
/
6
.!!'
I
V
{
!z -S.O
r-- r- VCC=5.0V
a -10
1/
~~
Nonnally High Ou1put
-60
./
-100
o
~
./
:J:
en
~
Normally Low Ou1put
a:
I:i:
0
o
1.0
/ Differential Mode
Mode = 0, VCC = 5.0 V
2.0
3.0
4.0
Vza , APPLIED OUTPUT VOLTAGE (V)
5.0
j
Pins2to4,6,7
-S.O V < VEE < 0 Differential or
Single-Ended Mode
-15
-20
-25
-1.0
6.0
1.0
"
~
11
~
........
L1J
L1J
..........
4.0
~
..........
~
r---.
~
!3
03.5 -
-
~
..........
r- Single-Ended Mode
f- Mode = 1
VCC = 5.0 V, VEE = -5.0 V
r- Vin= 1
I
-10
7-18
9.0
13
15
-3.25
Cl
~
7.0
Figure 11. Output Voltage versus
Output Sink Current
4.5
:J:
5.0
3.0
Yin, INPUT VOLTAGE (V)
Figure 10. Output Voltage versus
Output Source Current
;::i
120
tccl=o
/'
+60
::>
c.> +20
!::
::>
c.>
(3
100
40
60
80
TOTAL LOAD CURRENT (rnA)
+5.0
«g
a:
20
Figure 9. Input Current versus
Input Voltage
(Pin numbers refer to DIP and 80-16 packages only.)
Figure 8. Short Circuit Current
versus Output Voltage
ffia:
o
I
!3
r---.
V
~
o -4.25
.::.
~
I
-20
-30
-40
10H, OUTPUT CURRENT (rnA)
-3.75
-50
-60
/
"
/
-4.75 0
.- ......-
......- i-"'"'"
---I-'""
---
-
Single-Ended Mode
Mode=1
_
Vee = 5.0 V, VEE = -S.O V _
Vin=O
I
10
I-"""
20
30
40
10L, OUTPUT CURRENT (rnA)
I
50
60
MOTOROLA ANALOG IC DEVICE QATA
AM26LS30
Figure 12. Internal Positive Bias Current
versus Load Current
26
r- dingle kndJ Mod!
I
I
Figure 13. Internal Negative Bias Current
versus Load Current
o
I
Mode=l
f- VCC=5.0V, VEE =-5.0 V
Supply Current = Bias Current + IOH
/
~
/
1-5.0
!z
UJ
,../
a:
a:
5
- V
~
5>
/
V
-r-.
+ol~
-15
Figure 14. Short Circuit Current
versus Output Voltage
110
100
I
60
I
a:
a:
::>
0
!:::
20
j
::>
C3 -20
Ii:
0
1
Normally Low Output
+
=
...J
...J
it
i:iJ
,
;:/~~?
Output Voltage - Low Logic State
(IOL=20mA)
Output Voltage - High Logic State
(IOH = -20 mAl
':Y~;'f
, .: ~ ..
Output Short Circuit Current
(VIH = 2.0 V) Note 1
- ~u.
Output Leakage Current - Hi-Z State
,
(VOL = 0,5 V, VIL(E) = 0,8 V, VIH(~ = 2,0,'4 ,
(VOH = 2.5 V, VIL(E) = 0.8 V, VIH(E) = 2.0~;
Output Leakage Current - Power OFF""
(VOH = 6.0 V, VCC = 0 V)
.:tt,, "!i..,.
(VOL = - 0.25 V, VCC = 0 V)
::'~.~ '.:
~
:. ~.
2,·..
Output Differential Voltage, Note'2
<~~,,,
";
•
,
:.r~,
"i!:i~
......
}9S
/':~.'
"."
':,j,f,..-
:,':~(Z)
"i'
..
Output Differential Voltage Difference, NotEd!
Power Supply Current
(Output Disabled) Note 3
"
·'of
~. ~"
:,' ',;:(
;,:~~.?:>"
~;
.",
" ,"" ';,,>
.. '
:,,:~~'~ ..
,
:: ...;..... ~
::;,',.';'\tOi-t,':"" . .:(::~. ~t2.5
-
,
,
Output Offset Voltage Differ~;N9te
. .
't/':
',':,:-
+20
+100
).LA
).LA
10(0f!)
NOTES: 1. Only one output may be shorted at a time,
2, See EIA Specification EIA-422 for exact test conditions,
3. Circuit in three-state condition.
SWITCHING CHARACTERISTICS (VCC = 5,0 V, TA = 25'C unless otherwise noted.)
Characteristic
Propagation Delay Times
High to Low Output
Low to High Output
Symbol
Min
Typ
Max
tpHL
tpLH
-
-
-
-
20
20
-
-
6,0
ns
Output Skew
Propagation Delay - Control to Output
(CL = 10 pF, RL = 75 Q to Gnd)
(CL = 10 pF, RL = 180 Q to VCC)
(CL = 30 pF, RL = 75 Q to Gnd)
(CL = 30 pF, RL = 180 Q to VCC)
MOTOROLA ANALOG IC DEVICE DATA
ns
ns
tPHZ(E)
tPLZ(E)
tpZH(E)
tpZL(E)
-
-
-
-
30
35
40
45
7-25
AM26LS31
Figure 1. Three-State Enable Test Circuit and Waveforms
3.0VorGnd
Input
To Scope (Input)
To Scope
Output
Pulse generator characteristlcs
Open for tPZH(El Teet On~
Zo~50n
PRR", 1.0 MHz
~+5V
50% Duly Cycle
1nH. trill
180
Enslile
'" 6 ns
Pulse
50
Generator
Rl - See Test Table
; , . - - - - - 3.0V
- - - - - , - - - - - - - 3.0V
COntrol
Input
(Enable)
Output
II
Output
~'\t ,~
Control
Input
(Enable)
'-----VOL
OV
--1------
- lro.
IJZ~::::
_----VOH
~====----- OV
5V
Scope
(Output)
5.0 V
200
75
Zo~50n
PRR", 1.0 MHz
50% Duty Cycle
Cl Includes Probe and Jig CapacHance
lTlH. tTHl '" 6 ns
_---,-----3.0V
Input
Output
Output
:::::::~
7-26
____________~::::VOL
OV
MOTOROLA. ANALOG IC DEVICE DATA
®
MOTOROLA
QUAD EIA-422/423 Line
Receiver with Three-State
Outputs
Motorola's Quad EIA-42213 Receiver features four independent receiver
chains which comply with EIA Standards for the Electrical Characteristics of
Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs
are 74LS compatible, three-state structures which are forced to a high
impedance state when Pin 4 is a Logic "0" and Pin 12 is a Logic "1." A PNP
device buffers each output control pin to assure minimum loading for either
Logic "1" or Logic "0" inputs. In addition, each receiver chain has internal
hysteresis circuitry to improve noise margin and discourage output instability
for slowly changing input waveforms. A summary of AM26LS32 features
include:
AM26LS32
QUAD EIA-42213 LINE
RECEIVER WITH
THREE-5TATE OUTPUTS
SEMICONDUCTOR
TECHNICAL DATA
~~
• Four Independent Receiver Chains
GE
• Three-State Outputs
• High Impedance Output Control Inputs
(PIA Compatible)
• Internal Hysteresis - 30 mV (Typical) @ Zero Volts Common Mo
• Fast Propagation TImes - 25 ns (Typical)
• TTL Compatible
PC SUFFIX
PLASTIC PACKAGE
CASE 648
• Single 5.0 V Supply V o l t a g e . ; , ; ; , , '
• Fail-Safe Input-output Relationship. Output AlwaX$',>"~Whe!1lri
Are Open, Terminated or S h o r t e d "
,"fi"
• 6.0 k Minimum Input Impedance
,;~,:~~~'
PIN CONNECTIONS
Differential
Inputs
InpuisA {
1
Output
OutputsA 3
3-State 4
Control
.......~-----.13 Output8
3-State
12 Control
OutputC 5
11 OutputD
ORDERING INFORMATION
Device
• Note that the surface mount MC26LS32D device uses the same die as in the plastic DIP
AM26LS32DC device, but with an MC prefix to prevent confusion with the package suffix.
MOTOROLA ANALOG IC DEVICE DATA
AM26LS32PC
MC26LS320'
Operating
Temperature Range
TA = Oto 70°C
Package
PlasticOIP
S0-16
7-27
AM26LS32
MAXIMUM RATINGS
~atlng
Symbol
Value
Unit
VCC
7.0
Vdc
VICM
±25
Vdc
VID
±25
Vdc
Three-State Control Input Voltage
VI
7.0
Vdc
Output Sink Current
10
50
mA
Storage Temperature
Tstg
-65to+150
°c
TJ
+ 150
°c
Symbol
Value
Unit
VCC
4.75 to 5.25
Vdc
TA
Oto+70
°c
Input Common Mode Voltage Range
VICR
-7.0to + 7.0
Input Differential Voltage Range
VI DR
6.0
Power Supply Voltage
Input Common Mode Voltage
Input Differential Voltage
Operating Junction Temperature
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and max·
and power supply voltage ranges. Typical values are for TA = 25°C, VCC = 5.0 V an
•
Characteristic
Input Voltage - High Logic State (Three-State Control)
Input Voltage - Low Logic State (Three-State Control)
Differential Input Threshold Voltage (Note 2)
(-7.0 V .. VIC" 7.0 V, VIH = 2.0 V)
(10 = -0.4 mA, VOH ~ 2.7 V)
(10 = 8.0 mA, VOL" 0.45 V)
Input Bias Current
(VCC = 0 V or 5.25) (Other Inputs at -15 V ..
Vin=+15V
Yin :-15 V
6.0K
Input Resistance ( -15 V .. Yin .. + 15Y
Input Balance and Output Level
(-7.0 V .. VIC" 7.0 V, VIH : 2.1t
(10 = -0.4 mA, VID : 0.4
~.
(l0=8.0mA, V I D = - ·
VOH
VOL
2.7
~~~~------~--~~--+-~---r----~-------+----~
Output Third State Leakage
(VI(D) = + 3.0 V, VIL = 0.8 V, Vo = 0.4
(VI(D) = - 3.0 V, VIL = 0.8 V, Vo = 2.4 V)
10Z
Output Short Circuit Current
(VI(D) = 3.0 V, VIH = 2.0 V, Vo = 0 V, See Note 4)
lOS
-15
Input Current - Low Logic State (Three-State Control)
(VIL=0.4V)
Input Current - High Logic State (Three-5tate Control)
(VIH=2.7V)
(VIH = 5.5 V)
Input Clamp Diode Voltage (Three-5tate Control)
(lIC=-18mA)
Power Supply Current (VIL = 0 V) (All Inputs Grounded)
ICC
NOTES: 1. All currents into device pins are shown as pOSitive, out of device pins are negative. All voltages referenced to ground unless otherwise noted.
2. Differential input threshold voltage and guaranteed output levels are done simultaneously for worst case.
3. Refer to EIA-42213 for exact condnions. Input balance and guaranteed output levels are done simultilneously for worst case.
4. Only one output at a time should be shorted.
MOToaOLA ANALOG IC DEVICE DATA
AM26LS32
SWITCHING CHARACTERISTICS (VCC = 5.0 V and TA = 25°C, unless otherwise noted)
Characteristic
Symbol
Propagation Delay Time - Differential Inputs to Output
(Output High to Low)
(Output Low to High)
Min
Typ
Max
-
-
30
30
-
-
35
35
30
30
Unit
ns
tPHL(D)
tPLH(D)
Propagation Delay Time - Three-State Control to Output
(Output Low to Third State)
(Output High to Third State)
(Output Third State to High)
(Output Third State to Low)
ns
tPLZ
tPHZ
tpZH
tpZL
-
-
-
-
Figure 1. Switching Test Circuit and Wave for Propagation Delay Differential Input to Output
To Scope
(Input)
To Scope
(Output)
tPHL(D)
CL = 15 pF
(Includes Probe
and Stray
Capacitanoe)
51
oV
+2.0 V
3-State Control
Input Pulse Characteristics
tn.H - 'THL - 6.0 ns (10% to 90%)
PRR - 1.0 MHz, 50% Duty Cycle
SWl
2.0 k
+ 1.5Vfort
-1.5 Vfor
CL
15pF
(Includes
Probe and Stray
Capacitance)
'='
tpLZ
Input
3.0V~
1.5 V
3.0 V
Input
.. -- ,[ "\ :;g:::
= 1.3 V
Output
VOL
0.5 V
---1-- ---- ov
3 . 0 V , tpZH
Input
v::
___
~
~
; : t::! Open
l
- }
; ; -t:;2Closed
-
Oulput
1.5V
ov - - -
MOTOROLA ANALOG IC DEVICE DATA
All Diodes lN9160r
Equivalent
5.0k
,:-- *:/. . .
SWl Closed
Oulput
= 1.3V
-
- -
- -
-
-
- - OV
tpZL
3.0V
Input
-"'-:~
Oulput
SWl Closed
f
t :"""
1.5 V
VOL _ _ _ _ _ _ _ _ OV
7-29
®
MOTOROLA
MC1413, B
MC1416, B
High Voltage, High Current
Darlington Transistor Arrays
The seven NPN Darlington connected transistors in these arrays are well
suited for driving lamps, relays, or printer hammers in a variety of industrial
and consumer applications. Their high breakdown voltage and internal
suppression diodes insure freedom from problems associated with inductive
loads. Peak inrush currents to 500 rnA permit them to drive incandescent
lamps.
The MC1413, B with a 2.7 kn series input resistor is well suited for
systems utilizing a 5.0 V TTL or CMOS Logic. The MC1416, B uses a series
10.5 kn resistor and is useful in 8.0 to 18 V MOS systems.
PERIPHERAL
DRIVER ARRAYS
SEMICONDUCTOR
TECHNICAL DATA
,.
,
II
PSUFFIX
PLASTIC PACKAGE
CASE 648
ORDERING INFORMATION
Plastic DIP
sOle
Operating
Temperature Range
MC1413P (ULN2003A)
MC1416P (ULN2004A)
MC1413D
MC1416D
TA = -20° to +85°C
MC1413BP
MC1416BP
MC1413BD
MC1416BD
TA = -40° to +85°C
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
PIN CONNECTIONS
Representative Schematic Diagrams
1nMC1413,B
'--'+---t-0 Pin 9
I
I
L __
~
______ _
1nMC1416,B
+-----1~--r--O
Pin 9
I
I
L--+4I------(Top View)
7-30
MOTOROLA ANALOG IC DEVICE DATA
MC1413, B MC1416, B
MAXIMUM RATINGS (TA = 25°C, and rating apply to anyone device in the
package, unless otherwise noted.)
Symbol
Value
Unit
Output Voltage
Rating
Va
50
V
Input Voltage
VI
30
V
Collector Current - Continuous
IC
500
rnA
Base Current - Continuous
IB
25
rnA
Operating Ambient Temperature Range
MC1413-16
MC1413B-16B
TA
Storage Temperature Range
°C
-20 to +85
-40 to +85
Tstg
-55 to +150
Junction Temperature
TJ
150
Thermal Resistance, Junction-ta-Ambient
Case 648, P Suffix
Case 751 B, D Suffix
8JA
NOTE:
°C
°C
°CfW
67
100
ESD data available upon request.
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted)
Characteristic
Output Leakage Current
(Va = 50 V, TA = +85°C)
(Va = 50 V, TA = +25°C)
(Va = 50 V, TA = +85°C, VI = 1.0 V)
Collector-Emitter Saturation Voltage
(IC = 350 rnA, IB = 500 J.IA)
(IC = 200 rnA, IB = 350 J.IA)
(lc = 100 rnA, IB = 250 J.IA)
Symbol
ICEX
All Types
All Types
MC1416,B
VCE(sat)
MC1413,B
MC1416, B
MC1416, B
Input Voltage - On Condition
(VCE = 2.0 V, IC = 200 rnA)
(VCE = 2.0 V, IC = 250 rnA)
(VCE = 2.0 V, IC = 300 rnA)
(VCE = 2.0 V, IC = 125 rnA)
(VCE = 2.0 V, IC = 200 rnA)
(VCE = 2.0 V, IC = 275 rnA)
(VCE = 2.0 V, IC = 350 rnA)
MC1413, B
MC1413, B
MC1413, B
MC1416,B
MC1416, B
MC1416, B
MC1416, B
Input Current - Off Condition
(IC = 500 J.lA, TA = 85°C)
II(on)
VI(on)
All Types
DC Current Gain
(VCE = 2.0 V, IC = 350 rnA)
Typ
-
-
100
50
500
-
1.1
0.95
0.85
1.6
1.3
1.1
-
0.93
0.35
1.0
1.35
0.5
1.45
-
All Types
All Types
All Types
Input Current - On Condition
(VI = 3.85 V)
(VI = 5.0 V)
(VI=12V)
Min
-
Max
Unit
J.lA
V
rnA
-
V
-
-
2.4
2.7
3.0
5.0
6.0
7.0
8.0
II(off)
50
100
-
J.IA
hFE
1000
-
-
-
-
-
-
-
-
Input Capacitance
CI
30
pF
Ion
-
15
Turn-On Delay Time
(50% EI to 50% EO)
0.25
1.0
J.ls
Turn-Off Delay Time
(50% EI to 50% EO)
Ioff
-
0.25
1.0
J.IS
IR
-
Clamp Diode Leakage Current
(VR=50V)
Clamp Diode Forward Voltage
(IF=350mA)
MOTOROLA ANALOG IC DEVICE DATA
TA=+25°C
TA=+85°C
VF
-
-
-
50
100
J.IA
-
1.5
2.0
V
7-31
•
MC1413, B MC1416, B
TYPICAL PERFORMANCE CURVES - TA = 25°C
Figure 1. Output Current versus Input Voltage
400
Figure 2. Output Current versus Input Current
400
I
I
J
/MCI416,B
I
MC1413,B
o
o
1.0
2.0
3.0
I
I
J
4.0
5.0
8.0
9.0
10
11
o
o
12
ffi
!Ii
i3
a:
o
~
500
200
250
300
PIJ13 ~,
Plll0 __
1 Output Conducting at a Time
,.
,
l
y~
!z
w
~PINI6
i
Iff
300
- 100
=>
a.
1.0
-
0.4
0.6
0.8
1.0
1.2
1.4
V
/
/'
V/
Typical
/
/ V
/. V
0.5
/
o
o
1.6
/
V/,
~
All Types
V
Maximum
1.5
~'Y
0.2
2.0
a:
a:
=>
u
I-
~
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VCE(sat), SATURATION VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 5. Input Characteristics - MC1416, B
Figure 6. Maximum Collector Current
versus Duty Cycle
(and Number of Drivers In Use)
2.5
1000
2.0
l
a:
a:
=>
u
ffi
1.5
a:
a:
=>
u
a: 300
!5
a.
1.0
~
0.5
o ~;
o
400
v ./
2.5
o
o
350
Figure 4. Input Chsracteristlcs - MC1413, B
400
!z
w
-- -.....-
Max~
.-""" i-""'"
~
~
5.0
6.0
........
...-
7.0
8.0
9.0
10
11
700
--
W
...J
...J
8
......
............
["'-.......
500
......
........
..........
-...... -......
......
.....
............... ............
-.....:: ~
...........
~
,....-
~I
Vio INPUT VOLTAGE (V)
7-32
150
Figure 3. Typicsl Output Characteristics
6
-
100
110 INPUT CURRENT (!lA)
8200
l
50
I
I
J
VI, INPUT VOLTAGE (V)
800
II l::
AlllTypes
1
200
~
8.0
r"'o
......
......
..........
......
1
r--~
......
1""-1'-~ :::---- ~ .........
.... ......
I""- ....
......
-.........:::
...... .... ....
F=::: :::--- ......
.... ....
..... ....
'"
100
12
10
20
30
50
70
100
% DUTY CYCLE
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC1488
Quad Line Driver
The MC1488 is a monolithic quad line driver designed to interface data
terminal equipment with data communications equipment in conformance
with the specifications of EIA Standard No. EIA-232D.
QUADMDTLUNED~VER
EIA-232D
Features:
• Current Limited Output
± 10 mA typical
SEMICONDUCTOR
TECHNICAL DATA
• Power-Off Source Impedance
300 n mininum
• Simple Slew Rate Control with External Capacitor
• Flexible Operating Supply Range
P SUFFIX
PLASTIC PACKAGE
CASE 646
• Compatible with All Motorola MDTL and MTTL Logic Families
ORDERING INFORMATION
Operating
Temperature Range
Device
MC1488P
Plastic
TA = 0 to + 75°C
MC1488D
•
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
Package
S0-14
PIN CONNECTIONS
Simplified Application
Interconnecting
Una Receiver
MC1489
Cable
I
MDTLLogic Inpu1
I
I
~ Inter~:~ng~
I
MDTLLogicOtJlput
I
Circuit Schematic
(1/4 of Circuit Shown)
Vee 1 4 0 - - - - - - - - < . - - - - - - -......- - - - - < . - - - - - - .
8.2k
Pins4,9,12or2
Input
Input
70
Plns5, 10, 13
300
OUlpUt
PinsS.S, 11 or3
GND7~
10k
7.0k
70
VEElo-------~---4------~---~--~
MOTOROLA ANALOG IC DEVICE DATA
7-33
II
MC1488
MAXIMUM RATINGS (TA = +25°e, unless otherwise noted.)
Symbol
Value
Unit
Power. Supply Voltage
Vee
VEE
+15
-15
Vdc
Input Voltage Range
VIR
-15 .. VIR"
7.0
Vdc
Output Signal Voltage,
Vo
±15
Vdc
Po
1/ReJA
1000
6.7
mW
mw/oe
TA
Oto+75
°e
Tstg
-65to + 175
°e
.Ratlng .
Power Derating (Package limitation, S0-14
and Plastic Dual-ln-Llne Package)
Derate above TA = + 25°C
Operating Ambient Temperature Range
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (Vee =+ 9.0 ± 1% Vdc, VEE =-9.0 ± 1% Vdc, TA =0 to 75°C, unless otherwise noted.)
Characteristic
=0)
=5.0 V)
Input Current - Low Logic State (VIL
Min
Ty~
Max
Unit
IlL
-
1.0
1.6
mA
-
10
Input Current - High Logic State (VIH
IIH
Output Voltage - High Logic State
(VIL 0.8 Vdc, RL 3.0 kO, Vee
(VIL 0.8 Vdc, RL 3.0 kO, Vee
VOH
=+ 13.2 Vdc, VEE =- 13.2 Vdc)
Output Voltage - Low Logic State
(VIH 1.9 Vdc, RL 3.0 kO, Vee
(VIH 1.9 Vdc, RL 3.0 kO, Vee
=+ 9.0 Vdc, VEE =- 9.0 Vdc)
=+ 13.2 Vdc, VEE =-13.2 Vdc)
=
=
II
Symbol
=
=
=
=
= + 9.0 Vdc, VEE =- 9.0 Vdc)
=
=
Positive Output Short-Circuit Current, Note 1
Negative Output Short-CIrcuit Current, Note 1
=VEE =0,
Positive Supply Current (RI =00)
(VIH =1.9 Vdc, Vee =+ 9.0 Vdc)
(VIL =0.8 Vdc, Vee =+ 9.0 Vdc)
(VIH =1.9 Vdc, Vee =+ 12 Vdc)
(VIL =0.8 Vdc, Vee = + 12 Vdc)
(VIH =1.9 Vdc, Vee =+ 15 Vdc)
Output Resistance (Vee
(VIL
IVol
=± 2.0 V)
+6.0
+9.0
+7.0
+10.5
-
-6.0
-9.0
-7.0
-10.5
-
10S+
+6.0
+10
+12
10S-
-6.0
-10
-12
mA
ro
300
-
-
Ohms
-
+15
+4.5
+19
+5.5
+20
+6.0
+25
+7.0
+34
+12
-
-13
-17
-500
-23
-500
mA
-
-34
-
-2.5
mA
mA
-
-
333
VOL
ICC
-
=0.8 Vdc, Vee = + 15 Vdc)
=
Negative Supply Current (RL 00)
(VIH 1.9 Vdc, VEE
9.0 Vdc)
(VIL 0.8 Vdc, VEE
9.0 Vdc)
(VIH 1.9 Vdc, VEE
12 Vdc)
(VIL 0.8 Vdc, VEE -12 Vdc)
(VIH 1.9 Vdc, VEE
15 Vdc)
(VIL 0.8 Vdc, VEE -15 Vdc)
lEE
Power Consumption
(Vee 9.0 Vdc, VEE
(Vee 12 Vdc, VEE
Pc
=
=
=
=
=
=
=
=
====
=-
-
=
=- 9.0 Vdc)
IIA
Vdc
=-12 Vdc)
-
Vdc
mA
mA
-
-18
-
-
IIA
mA
IIA
mW
576
SWITCHING CHARACTERISTICS (Vee = +9.0 ± 1% Vdc, VEE = -9.0 ± 1% Vdc, TA = +25°c.)
Propagation Delay Time (ZI = 3.0 k and 15 pF)
Fall Time
Propagation Delay Time
Rise Time
=3.0 k and 15 pF)
(zi =3.0 k and 15 pF)
(zi =3.0 k and 15 pF)
(zi
275
350
ns
ITHL
-
45
75
ns
tPHL
-
110
175
ns
ITLH
-
55
100
ns
tPLH
NOTE: 1. Maximum Package Power Dissipation may be exceeded ff all outputs are shorted simunaneously.
7-34
MOTOROLA ANALOG IC DEVICE DATA
MC1488
CHARACTERISTIC DEFINITIONS
Figure 1. Input Current
9.0V
Figure 2. Output Voltage
-9.0V
9.0V
-9.0 V
0.8V
Figure 3. Output Short-Circuit Current
Figure 4. Output Resistance (Power Off)
Vee
1.9 V
105+
I
Va
±2.0Vdc
± 6.6 mA Max
105-
12
13
0.8V
Figure 5. Power Supply Currents
Figure 6. Switching Response
Vee
1.9V
"in
--D---I-=,..-3.0-k---1.----.
Va
115 PF
~
1.5V
0.8 V
:1;
trHL
trHL and trLH Measured 10% to 90%
MOTOROLA ANALOG IC DEVICE DATA
7-35
MC1488
TYPICAL CHARACTERISTICS
(TA =+25°C, unless otherwise noted.)
Figure 8. Short Circuit Output Current
versus Temperature
Figure 7. Transfer Characteristics
versus Power Supply Voltage
12
Vcc! VEE;+12~
9.0
vCC=VEE=±9.0V
6.0
;:'!;
3.0
,...
~
0
-
~
Vcc = VEE =±6.0 V
-~
5
-3.0 -
6
-6.0
o
>
'~
VI
-
3.0k
-
O.BV .
VEP 9.0 V
II'
::I.
o
0.2
0.4
0.6
O.B
1.0
1.2
1.4
1.6
1.B
o
2.0
en
125
Figure 9. Output Slew Rate
versus Load Cilpacitance
Figure 10; Output Voltage and
Current-Limiting Characteristics
20
16
1
12
B.O
!z
~ r--
\.
~ 4.0
a
* cL
I I I """
10
I I 1"""
100
~,
0
~
-4.0
.9
-B.O
-12
a
~~
1.0
1.0
75
T, TEMPERATURE (OC)
100
10
25
Vin, INPUT VOLTAGE (V)
~
~
II:
15
...J
-
108-
1000
..,
~
-=-
-9.0
-12
-
108+
~
w
C!l
1,000
1.9 V
•
I\.
\.
-
r-- r--...
~
'"
-
-
I'\.
3.0
.f
~~ 1 -
\.
\.
\.
lOS-
VI
-16 o.av VCC=VEE=±9.0V f,VO
-20
-16
-12
-8.0
-4.0
0
4.0
10,000
b LOA6 LINE
CAPACITANCE (pF)
\
B.O
12
16
Vo, OUTPUT VOLTAGE (V)
Figure 11. Maximum Operating Temperature
versus Power Supply Voltage
~
16
~
14
12
f- Vcc
f- Y-14
10
f-
~ 8.0
f-
~ 6.0
f-
tfl
4.0
f-
>
6 2.0
f-
;:'!;
~
~
c..
ffi
?
0
-55
I .............
I
I
I
............. ~.
...............
J. ~~k
J.. 3.0 k
~
a 3.0k
11 3.0 k
,i.?
-
61
VEE
~
o
25
75
125
T, TEMPERATURE (OC)
7-36
MOTOROLA ANALOG IC DEVICE DATA
MC1488
APPLICATIONS INFORMATION
The Electronic Industries Association EIA-232D specification
details the requirements for the interface between data processing
equipment and data communications equipment. This standard
specifies not only the number and type of interface leads, but also the
voltage levels to be used. The MCt 488 quad driver and its companion
circuit, the MCI489 quad receiver, provide a complete interface
system between DTL or TTL logic levels and the EIA-232D defined
levels. The EIA-232D requirements as applied to drivers are
discussed herein.
The required driver voltages are defined as between 5.0 and 15 V
in magnitude and are positive for a Logic "0" and negative for a Logic
"I." These voltages are so defined when the drivers are terminated
with a 3000 to 7000 n resistor. The MC1488 meets this voltage
requirement by converting a DTUTTL logic level into EIA-232D
levels with one stage of inversion.
The EIA-232D specification further requires that during transitions,
the driver output slew rate must not exceed 30 V per microsecond.
The inherent slew rate of the MC1488 is much too fast for this
requirement. The current limited output of the device can be used to
control this slew rate by connecting a capacitor to each driver output.
The required capacitor can be easily determined by using the
relationship C = lOS x I!..TII!..V from which Figure 12 is derived.
Accordingly, a 330 pF capacitor on each output will guarantee a
worst case slew rate of 30 V per microsecond.
should be placed in each power supply lead to prevent overheating in
this fault condition. These two diodes, as shown in Figure 13, could be
used to decouple all the driver packages in a system. (These same
diodes will allow the MC1488 to withstand momentary shorts to the
± 25 V limits specified in the earlier Standard EIA-232B.) The
addition of the diodes also permits the MC1488 to withstand faults
with power supplies of less than the 9.0 V stated above.
•
Figure 12. Slew Rate versus Capacitance
for ISC 10 mA
=
1000
~
The maximum short circuit current allowable under fault conditions
is more than guaranteed by the previously mentioned 10 mA output
current limiting.
10o ~3(' VlfJS.
w
~
~
(J)
0
~~:
(fllill
'1.0
10
100
1,000
10,000
C, CAPACITANCE (pF)
The interface driver is also required to withstand an accidental
short to any other conductor in an interconnecting cable. The worst
possible signal on any conductor would be another driver using a
plus or minus 15 V, 500 mA source. The MC1488 is designed to
indefinitely withstand such a short to all four outputs in a package as
long as the power supply voltages are greater than 9.0 V (i.e., VCC
'" 9.0 V; VEE';; - 9.0 V). In some power supply designs, a loss of
system power causes a low impedance on the power supply outputs.
When this occurs, a low impedance to ground would exist at the
power inputs to the MC1488 effectively shorting the 300 n output
resistors to ground. If all four outputs were then shorted to plus or
minus 15 V, the power dissipation in these resistors would be
excessive. Therefore, if the system is designed to permit low
impedances to ground at the power supplies of the drivers, a diode
MOTOROLA ANALOG IC DEVICE DATA
Other Applications
The MC1488 is an extremely versatile line driver with a myriad of
possible applications. Several features of the drivers enhance this
versatility:
1. Output Current Limiting - this enables the circuit designer to
define the output voltage levels independent of power supplies and
can be accomplished by diode clamping of the output pins. Figure 14
shows the MC148B used as a DTL to MaS translator where the high
level voltage output is clamped one diode above ground. The
resistor divider shown is used to reduce the output voltage below the
300 mV above ground MaS input level limit.
2. Power Supply Range - as can be seen from the schematic
drawing of the drivers, the positive and negative driving elements of
the device are essentially independent and do not require matching
power supplies. In fact, the positive supply can vary from a minimum
7.0 V (required for driving the negative pulldown section) to the
maximum specified 15 V. The negative supply can vary from
approximately - 2.5 V to the minimum specHied -15 V. The MC14BB
will drive the output to within 2.0 V of the positive or negative supplies
as long as the current output limits are not exceeded. The combination
of the current limiting and supply voltage features allow a wide
combination of possible outputs within the same quad package. Thus
if only a portion of the four drivers are used for driving EIA-232D
lines, the remainder could be used for DTL to MaS or even DTL to
DTL translation. Figure 15 shows one such combination.
7-37
MC1488'
Figure 15. Logic Translator Applications
Figure 14. MDTUMTTL-to-MOS Translator
12V
MOTl
Input
MOTl
MOSOutput
D--...--'\I"""-_--e (with VSS = GNO)
MTTL
1.0k
Input
10k
-12V
-12V
MOTL 4
NAND "-'"-1-....
Gate
Input
-.,..+--0__.-_--1,......_.
MOTL ......-1-...._
MHTl
Input
'"
MOTLOutput
-O,7Vto+S,7V
b-+--o--;;................;~-.
MHTL Output
-O,7Vto10V
10k
-12V
t-38
12V
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC1489, A
Quad Line Receivers
The MC1489 monolithic quad line receivers are designed to interface data
terminal equipment with data communications equipment in conformance
with the specifications of EIA Standard No. EIA-232D.
QUAD MDTL
LINE RECEIVERS
EIA-232D
• Input Resistance - 3.0 k to 7.0 kn
• Input Signal Range - ± 30 V
• Input Threshold Hysteresis Built In
• Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
PLASTIC PACKAGE
CASE 646
ORDERING INFORMATION
Operating
Temperature Range
Device
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
Package
MC1489P,AP
Plastic
TA =Oto+ 75"C
MC1489D,AD
•
S0-14
PIN CONNECTIONS
InpuiA
1
Simplified Application
Interconnecting
UneReceiver
MC1489
Cable
12 Response
COntrol 0
9 Response
controle
1
MDTL logic Input
I
I
I
I
~ 'nter~n:cting~
Ground
MDTlLoglCOutput
7
Representative Schematic Diagram
(1/4 of Circuit Shown)
14
VCC
9.0k
5.0k
1.7k
RF
RespomeCOO1ro12
30U1pu1
3.ak
1",,011
MC1489A
I
1.6 k!l
I
~
MOTOROLA ANALOG IC DEVICE DATA
10k
""
r-..
7GND
7-39
MC1489, A
MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted)
Symbol
Value
Power Supply Voltage
Rating
VCC
10
Vdc
Input Voltage Range
V,R
±30
Vdc
Output Load Current
IL
20
mA
Po
l/9JA
1000
6.7
mW
mW/oC
TA
Oto+75
°C
Tstg
-65to+175
°C
Power Dissipation (Package Limitation, SO-14
and Plastic Dual In-Line Package)
Derate above TA = + 25°C
Operating Ambient Temperature Range
Storage Temperature Range
Unit
ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC = + 5.0 Vdc ± 10%, TA = 0 to + 75°C, unless otherwise noted)
Characteristics
(V,H = + 25 Vdc)
(VIH = + 3.0 Vdc)
Positive Input Current
=-
Negative Input Current
(VIH
25 Vdc)
(V,H = - 3.0 Vdc)
Input Turn-0n Threshold Voltage
(TA + 25°C, VOL'" 0.45 V)
II
=
Min
Typ
Max
Unit
"H
3.6
0.43
-
8.3
mA
',L
-3.6
-0.43
-
-8.3
1.0
1.75
-
1.5
2.25
Vdc
MC1489
MC1489A
1.95
Vdc
V,L
=- 0.5 mAl
MC1489
MC1489A
=-
Output Voltage High
(VIH = 0.75 V, 'L
0.5 rnA)
0.5 mAl
(Input Open Circuit, 'L
Output Voltage Low
(V,L
=3.0 V, 'L =10 mAl
Power Supply Current (All Gates "on," lout = 0 mA, V,H = + 5.0 Vdc)
(V,H = + 5.0 Vdc)
Power Consumption
0.8
1.25
1.25
2.5
2.5
4.0
4.0
5.0
5.0
Vdc
-
0.2
0.45
Vdc
lOS
-3.0
-4.0
mA
ICC
-
16
26
mA
Pc
-
80
130
mW
VOL
Output Short-Circuit Current
-
0.75
0.75
VOH
=-
mA
-
V,H
=
Input Turn-Off Threshold Voltage
(TA + 25°C, VOH '" 2.5 V, 'L
Symbol
SWITCHING CHARACTERISTICS (VCC = 5.0Vdc+
- 1%, TA = + 25°C, See Figure 1.)
Propagation Delay Time
(RL = 3.9 kQ)
tpLH
-
25
85
ns
Rise Time
(RL=3.9kO)
tTLH
120
175
ns
Propagation Delay Time
(RL = 390 kQ)
tpHL
-
25
50
ns
Fall Time
(RL = 390 kQ)
trHL
-
10
20
ns
TEST CIRCUITS
Figure 1. Switching Response
Figure 2. Response Control Node
5.0 Vdc
All diodes
lN3064
or equivalent
E;n
R
P----4----~~---eEo
Cl
,.-_ _...3.0 V
)_50"1._'_ _
trHL
1/4
trLH and trHL
measured
10%-90%
1.5 V
Vin _ _-:.:M:=.C;..;148::;9;.;.A-t
Response Node
b-------_.vo
C, capaCitor is for noise filtering.
R. resistor is for threshold shifting.
CL = 15 pF = total parasitic capacitance which includes
probe and wiring capac~ances
7-40
MOTOROLA ANALOG IC DEVICE DATA
MC1489, A
TYPICAL CHARACTERISTICS
(Vee
=5.0 Vdc. TA =+25°e. unless otherwise noted)
Figure 4. MC1489 Input Threshold
Voltage Adjustment
Figure 3. Input Current
10
6.0
B.O
«
.s
I-
Z
4.0
w
2.0
:::>
0
a:
a:
U
I:::>
D~
,,;.
/'
6.0
-2.0
-4.0
-6.0
/
V
,-
VI
-8.0
-10
-25 -20
V
. / i-""
,.-
5.0
w
4.0
!:i0
3.0
~
C!l
>
I-
:::>
2.0
:::>
0
1.0
DI-
.p
:::>
Y
DI-
:::>
0
.p
-10 -5.0
0
5.0
10
4.0
Rr
S.Ok
3.0 Vth
5.0V
2.0
Rr -Rr
I - RT
1-13k
I - Vth
1-5.0V
I
I--
-11k ' - VIIl ' - -5.0V c - -
00
Y
.:.t
1.0
'-,
'-
0
,-
I-
vlLH VIHL
~
15
20
25
-3.0 -2.0 -1.0
0
1.0
2.0
3.0
Vin. INPUT VOLTAGE (V)
VI. INPUT VOLTAGE (V)
Figure 5. MC1489A Input Threshold
Voltage Adjustment
Figure 6. Input Threshold Voltage
versus Temperature
Rr r-
Rr
S.Ok
Vth
5.0V
00
r-
, - ,~
I-~
VILH - VIHL
u 2.4
~ 2.2
I
I
w
C!l
Y
RT
11 k
Vth
5.0V
!:i
§2
0
...J
0
:r:
w
a:
(f)
=Vth
F
I-
~
-
~
3.0
4.0
:::>
J
I
I
I
I
D~
".
;!;
>
-3.0 -2.0 -1.0
0
1.0
2.0
Vth
I
"" I
~
0
I-
I
-15
~
w
(!)
!:i§2
6.0
u
L
"JJ
I
J
I
5.0
2.0
1.8
1.6
1.4
1.2
1.0
O.B
0.6
0.4
0.2
-
r---
-
I
~AVIHII
I
I
I
~Cl~89VIH _
II
MC148dviL
I
I
0
-60
o
+60
r--
\
MC14B9AVIL
I
I
+120
T. TEMPERATURE (0C)
VI. INPUT VOLTAGE (V)
Figure 7. Input Threshold versus
Power Supply Voltage
2.0
VIH MC1489A
f-- VIH MC1489
VILMCI489
f - VIL MCI489A
4.0
5.0
6.0
VCC. POWER SUPPLY VOLTAGE (V)
MOTOROLA ANALOG Ie DEVICE DATA
7-41
II
MC1489, A
APPLICATIONS INFORMATION
II
General Information
The Electronic Industries Association (EIA) has released
the EIA-232D specification detailing the requirements for the
interface between data processing equipment and data
communications equipment. This standard specifies not only
the number and type of interface leads, but also the voltage
levels to be used. The MC1488 quad driver and its
companion circuit, the MC1489 quad receiver, provide a
complete interface system between DTL or TTL logic levels
and the EIA-232D defined levels. The EIA-232D
requirements as applied to receivers are discussed herein.
The required input impedance is defined as between
3000 nand 7000 n for input voltages between 3.0 and 25 V
in magnitude; and any voltage on the receiver input in an
open circuit condition must be less than 2.0 V in magnitude.
The MC1489 circuits meet these requirements with a
maximum open circuit voltage of one VSE.
The receiver shall detect a voltage between - 3.0 and
- 25 Vasa Logic "1" and inputs between 3.0 and 25 V as a
Logic "0." On some interchange leads, an open circuit of
power "OFF" condition (300 n or more to ground) shall be
decoded as an "OFF" condition or Logic "1." For this reason,
the input hysteresis thresholds of the MC1489 circuits are all
above ground. Thus an open or grounded input will cause the
same output as a negative or Logic "1" input.
Device Characteristics
The MC1489 interface receivers have internal feedback
from the second stage to the input stage providing input
hysteresis for noise rejection. The MC1489 input has typical
turn-on voltage of 1.25 V and turn-off of 1.0 V for a typical
hysteresis of 250 mY. The MC1489A has typical turn-on of
1.95 V and turn-off of 0.8 V for typically 1.15 V of hysteresis.
Each receiver section has an external response control
node in addition to the input and output pins, thereby allowing
the designer to vary the input threshold voltage levels. A
resistor can be connected between this node and an external
power supply. Figures 2, 4 and 5 illustrate the input threshold
voltage shift possible through this technique.
This response node can also be used for the filtering of
high frequency, high energy noise pulses. Figures 8 and 9
show typical noise pulse rejection for external capacitors of
various sizes.
These two operations on the response node can be
combined or used individually for many combinations of
interfacing applications. The MC1489 circuits are particularly
useful for interfacing between MOS circuits and MDTUMTTL
logic systems. In this application, the input threshold voltages
are adjusted (with the appropriate supply and resistor values)
to fall in the center of the MOS voltage logic levels (see
Figure 10).
The response node may also be used as the receiver input
as long as the designer realizes that he may not drive this
node with a low impedance source to a voltage greater than
one diode above ground or less than one diode below
ground. This feature is demonstrated in Figure 11 where two
receivers are slaved to the same line that must still meet the
EIA-232D impedance requirement.
Figure 8. Typical Turn On Threshold versus
Capacitance from Response Control Pin to GND
Figure 9. "TYpical Turn On Threshold versus
Capacitance from Response Control Pin to GND
6r-------".--r.------r--------~
6
MCI489A
MCI489
~
w
0
5
c..
..:
~
~
w
4
0
E
4
...J
c..
::;;
..:
3
.5
3
w"
w
2
1
10
2
100
1000
PW, INPUT PULSE WIDTH (ns)
7-42
10,000
1
10
100
1000
10,000
PW, INPUT PULSE WIDTH (ns)
MOTOROLA ANALOG IC DEVICE DATA
MC1489, A
Figure 10. Typical Translator ApplicationMOS to DTL or TTL
DTL or TIL
r- -,
---I
+5.0
:
Lrl
Vdc. ":"
Figure 11. Typical Paralleling of Two MC1489, A Receivers to Meet EIA-232D
Vee
Respons&-Control Pin
Input
8.0 k
r-----------------,
I
I
I
112 MC1489
Output
Vee 0--'-----------,
Input
8.0k
Respons~ntrol
Pin
MOTOROLA ANALOG IC DEVICE DATA
Output
®
MOTOROLA
MC14C88B
Quad Low Power Line Driver
The MC14C88B is a low power monolithic quad line driver, using BiMOS
technology, which conforms to EIA-232-D, EIA-562, and CCITT V.28. The
inputs feature TTL and CMOS compatibility with minimal loading. The
outputs feature internally controlled slew rate limiting, eliminating the need
for external capacitors. Power off output impedance exceeds 300 Q, and
current limiting protects the outputs in the event of short circuits.
Power supply current is less than 160 itA over the supply voltage range of
±4.5 to ±15 V. EIA-232-D performance is guaranteed with a minimum
supply voltage of ±6.5 V.
The MC14C88B is pin compatible with the MC1488, SN75188,
SN75C188, DS1488, and DS14C88. This device is available in 14 pin plastic
DIP, and surface mount packaging.
QUAD LOW POWER
LINE DRIVER
SEMICONDUCTOR
TECHNICAL DATA
Features:
• BiMOS Technology for Low Power Operation ( < 5.0 mW)
• Meets Requirements of EIA-232-D, EIA-562, and CCITT V.28
•
PSUFFIX
PLASTIC PACKAGE
CASE 646
• Quiescent Current Less Than 160 J4A
• TTUCMOS Compatible Inputs
• Minimum 300 Q Output Impedance when Powered Off
• Supply Voltage Range: ±4.5 to ±15 V
• Pin Equivalent to MC1488
• Current Limited Output: 10 mA Minimum
DSUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
• Operating Ambient Temperature: -400 to 85°C
PIN CONNECTIONS
Representative Block Diagram
OutputA
3
InputB1
4
InputB2
5
11
OutputD
(Each Driver)
Vee
Output B 6
8 Outpute
(Top View)
Output
Input2
ORDERING INFORMATION
o-+-......r
39
Device
Operating
Temperature Range
Package
MC14C88BP
Plastic DIP
1 - - - - - - 1 TA = - 40° to +85°C I--------j
MC14C88BD
S0-14
7-44
MOTOROLA ANALOG IC DEVICE DATA
MC14C88B
MAXIMUM RATINGS (TA = +25°e, unless otherwise noted.)
Rating
Power Supply Voltage
Vee(max)
VEE(min)
(Vee - VEE)max
Symbol
Value
Vee
VEE
Vee-VEE
+17
-17
34
Unit
Vdc
Input Voltage (All Inputs)
Yin
Applied Output Voltage, when Vee=VEE¢O V
Applied Output Voltage, when Vee=VEE = 0 V
Vx
Output eurrent
10
Self limiting
mA
Operating Junction Temperature
TJ
-65, + 150
°e
VEE-{)·3, VEE+39
Vdc
VEE--6.0 V, Vee+6.0 V Vdc
±15
Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides
for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
Vee
VEE
+4.5
-15
-
Vdc
-
+15
-4.5
Yin
0
-
Vec
Vdc
Applied Output Voltage (VCC=VEE=O V)
Vo
-2.0
0
+2.0
Vdc
Output De Load
RL
3.0
-
7.0
k.Q
Operating Ambient Temperature Range
TA
-40
-
+85
°C
Min
Typ
Max
Unit
-
-
160
160
-160
-160
-
-
3.7
4.0
5.0
10
3.8
4.3
6.1
10.5
13.2
-
Input Voltage (All Inputs)
Alilimtts are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (-40o e '" TA ",+85°C, unless otherwise noted.),
Characteristic
Supply Current (lout = 0, see Figure 2)
lee @ 4.75 V '" Vee, -VEE'" 15 V
Outputs High
Outputs Low
lEE
Outputs High
Outputs Low
Symbol
J.LA
ICC (OH)
lee (OL)
lEE (OH)
lEE (OL)
Output Voltage - High, Yin ",0.8 V (RL = 3.0 k.Q , see Figure 3)
Vee = +4.75 V, VEE = -4.75 V
Vee = +5.0 V, VEE = -5.0 V
Vee = +6.5 V, VEE = --6.5 V
Vee=+12V, VEE=-12V
Vee =+13.2 V, VEE =-13.2 V (RL==)
Output Voltage - Low, Yin '" 2.0 V
Vee = +4.75 V, VEE = -4.75 V
Vee = +5.0 V, VEE = -5.0 V
Vee = +6.5 V, VEE = --6.5 V
Vce=+12V, VEE=-12V
Vee =+13.2 V, VEE=-13.2V(RL==)
VOH
Output Short Circutt eurrent** (see Figure 4) (Vee = IVEEI = 15 V)
Normally High Output, shorted to ground
Normally Low Output, shorted to ground
lOS
Output Source Resistance
(Vec = VEE = 0 V, -2.0 V '" Vout ",+2.0 V)
Input Voltage
Low Level
High Level
-
-
VOL
-
Vdc
-
13.2
-3.8
-4.2
--6.0
-10.5
-13.2
-3.7
-4.0
-5.0
-10
-35
+10
-
-10
+35
RO
300
-
-
Q
VIL
VIH
0
2.0
-
-
0.8
Vce
Vdc
-
-13.2
mA
* Typicals reflect performance @ TA = 25°C
** Only one output shorted at a time, for not more than 1 second.
MOTOROLA ANALOG IC DEVICE DATA
7-45
II
MC14C88B
ELECTRICAL CHARACTERISTICS (continued) (-40°C .. TA .. +85°C, unless otherwise noted.)'
Characteristic
Input Current
Vln=OV, VCC= IVeel =4.75V
Vln=OV,VCC= IVeel =15V
Yin = 4.5 V, VCC = IVeel = 4.75 V
Vln = 4.5 V, VCC = IVeel = 15 V
Symbol
Min
Typ
Max
-10
-10
0
0
-0.1
-0.1
+0.1
+0.1
0
0
+10
+10
Min
Typ
Max
Unit
~
lin
TIMING CHARACTERISTICS (-40°C .. TA .. +85°C, unless otherwise noted.)'
Characteristic
Output Rise Time
VCC = 4.75 V, Vee = -4.75 V
-3.3 V "VO .. 3.3 V
CL=15pF
CL = 1000 pF
-3.0 V .. VO" 3.0V
CL=15pF
CL = 1000 pF
VCC = 12.0 V, Vee = -12.0 V
-3.0 V .. VO" 3.0V
CL= 15pF
CL = 2500 pF
10% .. VO" 90%
CL= 15pF
II
Output Fall Time
VCC = 4.75 V, Vee = -4.75 V
3.3 V .. VO .. -3.3 V
CL=15pF
CL= l000pF
3.0V .. VO" -3.0 V
CL=15pF
CL= l000pF
VCC = 12.0 V, Vee = -12.0 V
3.0V "VO" -3.0 V
CL= 15pF
CL= 2500 pF
90% .. VO" 10%
CL=15pF
Output Slew Rate, 3.0 kU < RL < 7.0 ill, 15 pF < CL < 2500 pF
Propagation Delay A (CL = 15 pF, see Figure 1)
VCC = 12.0 V, Vee = -12.0 V
Input to Output - Low to High
Input to Output - High to Low
Propagation Delay B (CL = 15 pF, see Figure 1)
VCC = 4.75 V, Vee = -4.75 V
Input to Output - Low to High
Input to Output - High to Low
Symbol
Unit
~s
tRl
0.22
0.22
0.66
1.52
2.1
2.1
0.20
0.20
0.51
1.16
1.5
1.5
0.20
0.20
0.62
0.82
1.5
1.5
0.53
1.41
3.2
tR2
tR3
~
tFl
0.22
0.22
0.93
1.28
2.1
2.1
0.20
0.20
0.72
1.01
1.5
1.5
0.20
0.20
0.70
0.94
1.5
1.5
0.53
1.71
3.2
4.0
-
30
tF2
tF3
SR
V/~
~s
tpLH
tPHL
-
0.9
2.3
3.0
3.5
tPLH
tpHL
-
0.4
1.5
2.0
2.5
• Typical. reflect performance @ TA = 25°C
7-46
MOTOROLA ANALOG IC DEVICE DATA
MC14C88B
Figure 1. Timing Diagram
J-
S.G.
OV
t
'---+-0
S.G.
1.SV
1-1PLH
j-1PHL
~---VOH
Your
\0---+------ 90% - - - - - - r - - - t o f
~+------ 3.3V'------+--I
NOTES: S.G. sella: f = 20 kHz for Propagation Delay A
and f = 64 kHz for Propagation Delay B; Duty
' f o o - l - - - - - - 3.0 V ' - - - - - - - / l - I
Cycle = 50%; tR, tF" 5.0 ns
Vom---1-~\--------------i~t-+-----OV
\0-----_3.0 V'------oof
~---_3.3V·---_I
-----VOL
STANDARDS COMPLIANCE
The MC14CBB is designed to comply with EIA-232-D
(formerly R8-232), the newer EIA-562 (which is a higher
speed version of the EIA-232), and CCIIT's V.2B. EIA-562
was written around modern integrated circuit technology,
whereas EIA-232 retains many of the specs written around
Parameter
the electro-mechanical circuitry in use at the time of its
creation. Yet the user will find enough similarities to allow a
certain amount of compatibility among equipment built to the
two standards. Following is a summary of the key
specifications relating to the systems and the drivers.
EIA-232-D
EIA-562
Maximum Data Rate
20kbaud
38.4 kbaud Asynchronous
64 kbaud Synchronous
Maximum Cable Length
50 feet
Based on cable capacitance/data rate
Maximum Slew Rate
.; 30 V/flS anywhere on the waveform
.; 30 V/flS anywhere on the waveform
~ 4.0 V/jlS between +3.0 and -3.0 V
Transijion Region
-3.0 to +3.0 V
-3.3 to +3.3 V
Transijion Time
For UI ;;. 25 ms, tR ';;1.0 ms
For 25 ms > UI > 125 flS, tR .;; 4% UI
For UI < 125 flS, tR .;; 5.0 flS
For UI ;;. 50 flS, 220 ns < tR .; 3.1 flS
For UI < 50 flS, 220 ns < tR .; 2.1 flS
(within the transition region)
MARK (one, off)
More negative than -3.0 V
More negative than -3.3 V
Space (zero, on)
More positive than +3.0 V
More positive than +3.3 V
Short Circuit Proof?
Yes, to any system voltage
Yes, to ground
Short Circuit Current
.;; 500 mA to any system voltage
.; 60 mA to ground
Open Circuit Voltage
IVocl .; 25V
IVocl < 13.2 V
Loaded Output Voltage
5.0 V .; IVai .;15 V for loads between
3.0 kO and 7.0 kO
Ivai ;;. 3.7 V for a load of 3.0 kO
Power Off Input Source Impedance
;;.300nlorlvol.;2.oV
'" 300 n lor Ivai.;; 2.0V
NOTE:
UI = Untt Interval, or bit time.
V.28 standard has the same specifications as EIA-232, wtth the exception of transttion time which is listed as "less than 1.0 ms, or 3% of the UI,
whichever is less".
MOTOROLA ANALOG IC DEVICE DATA
7-47
MC14C88B
Figure 2. Typical Supply Current ..
versus Supply Voltage
110
1
Figure 3. Typical Output Voltage
versus Supply Voltage
ICC(OL)
I-
i1i
a:
ICC(OH)
55
a:
:>
<.>
t::
:>
<.>
a:
0
(3
ti:
~
en
w -65
w
8
-
IE!J.OH)
IEE(OL)
-110
8.0
6.0
4.0
10
12
14
16
Vee AND-VEE, (V)
Figure 4. Typical Short Circuit Current
versus Supply Voltage
II
30
1
20
w
a:
a:
10
IZ
:>
<.>
~
t::
:>
~
0
ti:
-10
(3
0
J:
en
0-20
.!!'
-30
.
4.0
--
Ise
,..-
15
Normall~ Low 0tJlpJ1
VOH @Vee
10
I
I
~.~
----,.....
!l.0
~
~
"Ise
0
~
I
VOL @ Vee = -VEE; = 4.5 V
§ -6.0
1
Ise
r'
8.0
~
gj 5.0
(0.8 or 2.0 V)
VEE
f~VEE = 12 V
VOH @ Vcc -VEE= 4.5 V
~
Vee
vOL@veef-VEE=12V
I
-10
Normall~ High Output
10
Vcc AND -VEE, (V)
7-48
Figure 5. Typical Output Voltage
versus Temperature
i
12
'1
14
16
-15
-40
I
22
TA, AMBIENT TEMPERATURE (De)
RL =3.0kO
85
MOTOROLA ANALOG IC DEVICE DATA
MC14C888
APPLICATIONS INFORMATION
Description
The MC14C88 was designed to be a direct replacement
for the MC1488 in that it meets all EIA-232 specifications.
However, use is extended as the MC14C88 also meets the
faster EIA-562 and CCITT V.28 specifications. Slew rate
limited outputs conform to the mentioned specifications and
eliminate the need for external output capacitors. Low
power consumption is made possible by SiMOS technology.
Power supply current is limited to less than 160 f,tA, plus
load currents over the supply voltage range of ±4.5 V to
±15 V (see Figure 2).
Outputs
The output low or high voltage depends on the state of the
inputs, the load current, and the supply voltage (see Table 1
and Figure 3). The graphs apply to each driver regardless of
how many other drivers within the package are supplying
load current.
or rise above VEE by more than 39 V, excessive currents will
flow at the input pin. Open input pins are equivalent to logic
high, but good design practices dictate that inputs should
never be left open.
Operating Temperature Range
The ambient operating temperature range is listed at -40°
to +85°C and meets EIA-232-D, EIA-562 and CCITT V.28
specifications over this temperature range. The maximum
ambient temperature is listed as +85°C. However, a lower
ambient may be required depending on system use, i.e.
specifically how many drivers within a package are used, and
at what current levels they are operating. The maximum
power which may be dissipated within the package is
determined by:
P
Table 1. Function Tables
Driver 1
Input A
Output A
H
L
L
H
where: RaJA = the package thermal resistance (typically,
100°C/W for the DIP package, 125°C/W for the
SOIC package);
T Jmax = the maximum operating junction
temperature (150°C); and
TA =the ambient temperature.
Drivers 2 through 4
Input <1
Input <2
Output<
H
L
X
H
X
L
l
H
H
H = High level, L = Low level, X = Don't care.
Driver Inputs
The driver inputs determine the state of the outputs in
accordance with Table 1. The nominal threshold voltage for
the inputs is 1.4 Vdc, and for proper operation, the input
voltages should be restricted to the range Gnd to VCC.
Should the input voltage drop below VEE by more than 0.3 V
MOTOROLA ANALOG IC DEVICE DATA
TJmax-TA
- -""==:.....--'-'Dmax Ra JA
PD
={[ (VCC -
VOH) x IIOHI) or [(VOL - VEE) x
IIOLi )} each driver + (VCC x ICC) + (VEE x lEE)
where: VCC and VEE are the positive and negative
supply voltages;
VOH and VOL are measured or estimated from
Figure 3;
ICC and lEE are the quiescent supply currents
measured or estimated from Figure 2.
As indicated, the first term (in brackets) must be calculated
and summed for each of the four drivers, while the last terms
are common to the entire package.
7-49
II
®
MOTOROLA
I
Quad Low Power
Line Receivers
The MC14C89B and MC14C89AB are low monolithic quad line receivers
using bipolar technology, which conform to the EIA-232-E, EIA--562 and
CCITT V.28 Recommendations. The outputs feature LSTTL and CMOS
compatibility for easy interface to +5.0 V digital systems. Internal
time-domain filtering eliminates the need for external filter capacitors in most
cases.
The MC14C89B has an input hystereSiS of 0.35 V, while the MC14C89AB
hystereSiS is 0.95 V. The response control pins allow adjustment of the
threshold level if desired. Additionally, an external capacitor may be added
for additional noise filtering.
The MC14C89B and MC14C89AB are available in both a 14 pin
dual-in-line plastic DIP and SOIC package.
MC14C89B, AB
QUAD LOW POWER
LINE RECEIVERS
SEMICONDUCTOR
TECHNICAL DATA
Features:
•
PSUFFIX
PLASTIC PACKAGE
CASE 646
• Low Power Consumption
• Meets EIA-232-E, EIA-562, and CCITT V.28 Recommendations
• TTUCMOS Compatible Outputs
• Standard Power Supply: + 5.0 V ±1 0%
o
SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)
• Pin Equivalent to MC1489, MC1489A, Tl's SN75C189/A, SN75189/A
and National Semiconductor's DS14C89/A
• External Filtering Not Required in Most Cases
• Threshold Level Externally Adjustable
• Hysteresis: 0.35 V for MC14C89B, 0.95 V for MC14C89AB
• Available in Plastic DIP, and Surface Mount Packaging
PIN CONNECTIONS
• Operating Ambient Temperature: -40° to +85°C
VCC
Response
Control A
Input 0
Response
Control 0
Output A
Representative Block Diagram
(Each Receiver)
Response
ControlB
Inpute
OutputB
Response
ControlC
Ground
OutputC
VCC
(Top View)
Input o-t--4I~---.
Response
Control
0-+----.--..
....-t---1t-O Output
ORDERING INFORMATION
Device
Operating
Temperature Range
MC14C89BP
MC14C89ABP
MC14C89ABD
7'-50'
Package
Plastic DIP
TA = -40° to +85°C
Plastic DIP
SO-14
MOTOROLA ANALOG Ie DEVICE DATA
MC14C89B, AB
MAXIMUM RATINGS
Rating
Symbol
Value
VCC
+7.0
-0.5
Power Supply Voltage
VCC(max)
VCC(min)
Unit
Vdc
Input Voltage
Yin
±30
Output Load Current
10
Self-Limiting
Vdc
-
Junction Temperature
TJ
-65,+150
°c
Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides
for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Vonage
Symbol
Min
Typ
Max
Unit
VCC
4.5
5.0
5.5
Vdc
Input Voltage
Vin
-25
-
25
Vdc
Output Current Capability
10
-7.5
-
6.0
rnA
Operating Ambient Temperature
TA
-40
-
85
°C
Min
Typ
Max
Unit
-
330
700
All limit. are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (-40°C '" TA '" +85°C, unless otherwise noted.)'
Characteristic
Symbol
Supply Current (lout = 0)
ICC @ +4.5 V '" VCC '" +5.5 V
ICC
Output Vo~age - High, Yin '" 0.4 V (See Figures 2 and 3)
VCC=4.5V
lout = -20 !1A
VCC=5.5V
Vce=4.5V
'out = -3.2 rnA
Vce=5.5V
Output Voltage - Low, Yin ;;. 2.4 V
VCC=4.5V
'out=3.2mA
VCC=5.5V
VOH
Output Short Circuit Current·· (VCC = 5.5 V, see Figure 4)
Normally High Output shorted to ground
Normally Low Output shorted to VCC
lOS
VOL
Vdc
V,L
V,H
V,L
V,H
Input Impedance (+4.5 V < VCC < +5.5 V -25 V < Vin < +25 V)
-
3.5
3.5
2.5
2.5
3.8
4.8
3.7
4.7
-
-
0.1
0.1
0.4
0.4
-35
-
-13.9
+10.3
35
0.75
1.6
0.75
1.0
0.95
1.90
0.95
1.3
1.25
2.25
1.25
1.5
Vdc
3.0
5.5
7.0
k!l
Min
Typ
Max
Unit
-
0.08
0.30
/1S
-
3.35
2.55
6.0
6.0
/1S
1.0
1.5
-
/1S
-
Input Threshold Voltage (Vce = 5.0 V)
(MC14C89AB, see Figure 5)
Low Level
High Level
(MC14C89B, see Figure 6)
Low Level
High Level
IlA
rnA
• Typical. reflect performance @ TA = 25°C
··Only one output shorted at a time, for not more than 1.0 seconds.
TIMING CHARACTERISTICS (TA = +25°C, unless otherwise noted.)
Characteristic
Output Transition Time (10% to 90%)
Symbol
IT
4.5V '" Vce '" 5.5V
Propagation Delay Time
4.5V '" Vce '" 5.5V
Output Low-ta-High
Output High-ta-Low
Input NOise Rejection (see Figure 9)
MOTOROLA ANALOG IC DEVICE DATA
tpLH
tpHL
7-51
a
MC14C89B, AB
Figure 1. Timing Diagram
J-
S.G.
OV
Vee
sa~~~f !
':' (Open)
1.5V
~-+-----90% _ _ _ _ _-l-_r-:----VOH
Vout
':'
NOTES: S.G. set to: , = 20 kHz;
Duty Cycle = 50%;
tr,t, .. 5.On8
I ' - - - - - - ' t - - - - - t - - - - VOL
STANDARDS COMPLIANCE
II
The MC14C89B and MC14C89AB are designed to. comply
with EIA-232-E (formerly RS-232), the newer EIA-562
(which is a higher speed versian af the EIA-232), and CCITT
V.28 Recammendatians. EIA-562 was written araund
modern integrated circuit technalagy, whereas EIA-232
retains many af the specifications written around the
Parameter
Max Data Rate
electro-mechanical circuitry in use at the time of its creation.
Yet the user will find enough similarities to allow a certain
amaunt of campatibility amang equipment built to. the twa
standards. Following is a summary of the key specifications
relating to. the systems and the receivers.
EIA-562
EIA-232-E
20. kBaud
38.4 kBaud Asynchronous
64 kBaud Synchronous
Max Cable Length
SO. feet
Based on cable capacitance/data rate
Transition Region
-3.0. V to +3.0. V
-3.0. V to +3.0. V
MARK (one, off)
More negative than -3.0. V
More negative than -3.3 V
SPACE (zero, on)
More positive than +3.0. V
More positive than +;3.3 V .
Fail Safe
Output = Binary 1
Output = Binary 1
Open Circuit Input Voltage
<
Slew Rate (at the driver)
'" 3D V/flS anywhere on the waveform
'" aD. V/flS anywhere on the waveform,
;. 4.0. V/flS between +3.0. V and -3.0. V
Loaded Output Voltage (at the driver)
S.DV'" Ivai'" 1S V for loads between
3.0. kn and 7.0. kn
Ivai ;.
12.0.1 V
Not Specified
-
Figure 2. TYpical Output versus Supply Voltage
5.0
VOH(lopt -20 ~A)
~4.0
w
~
t:.i 3.0
§i!
r--
VOH(lout - -3.2 rnA)
I
MC1~C89AB
-
MC14C89B
TA = 25°C
~4.0
VOH(lout=
-ko ~)
.2 rnA)
~ 3.0
MC14C89AB
MC14C89B
Vee=5V
>
~
5 2.0
·0
6
$>
> 1.0
7-52
VOH(lout =
~
5
4.5
Figure 3. Typical Output Voltage versus Temperature
5.0
w
5o 2.0
o
3.7 V for a load of 3.0. kn
1.0
Vodlout = 3.2 rnA)
Vodlout = 3.2 rnA)
4.7
4.9
5.1
VCC, SUPPLY VOLTAGE (V)
5.3
5.5
0.
-40.
-7.5
25
57.5
TA, AMBIENT TEMPERATURE (OC)
85
MOTOROLA ANALOG IC DEVICE DATA
MC14C89B, AB
Figure 4. Typical Short Circuit Current
versus Temperature
Figure 5. Typical Threshold Voltage
versus Temperature
15
I
2.0
:g
10
!z
~
5.0
!:::
0
a:
=>
o
~
Nbrmally Low OutpJt Shorted to VCC
~
Sl
':J
MC14C89AB
MC14C89B
VCC=5.5V
~
Cl
ffi~ 1.2
.
en -10
-15
-40
MC14C89AB
4.5 V < VCC < 5.5V
1.6
5 1.4
C3 -50
~
VIH
1.8
w
f-
~
~ 1.0
Norma Iy High Output Shorted to Ground
-7.5
25
57.5
TA, AMBIENTTEMPERATURE (0C)
VIL
0.8
85
-40
-7.5
25
57.5
TA, AMBIENT TEMPERATURE (0C)
Figure 6. Typical Threshold Voltage
versus Temperature
5.0
2.0
MC14C89B
4.5V < VCC < 5.5V
:g
w
~
;:u 4.0
;5 1.6
;5
~1.8
C!l
C!l
~
~
§1.4
gfa
VIH
:x:
fa
a:
~
~ 1.2
f-
~
f-
~
~ 1.0
2.0
Figure 7. Typical Effect of Response
Control Pin Bias
\ \
\
\
-7.5
25
57.5
TA, AMBIENTTEMPERATURE (OC)
:
+ RRC
~ Vbat
""I'----.
~!.:'.bat=-3.0V - -
NominalVIL
o
o
85
~
I\.VIL@Vbat=-10V
1.0
~
VIL
0.8
-40
3.0
85
-
4.5 V < VpC < 5.5 V
10kQ
20kQ
30kQ
40kQ
SOkQ
BIAS RESISTANCE (RRC)
Figure 8. Typical Noise Pulse Rejection
S.O
~
MC14C89AB
MC14C89B
Pulse Rate = 300 kHz
RC Pin Open
4.S
w
Cl
=> 4.0
!:::
...J
a.
:::;
« 3.S
w
~
=>
a. 3.0
\
.E
w
2.5
Noise p,ulse Reje~iOn
"-J.
2.0
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
PW, INPUT PULSE WIDTH (llS)
MOTOROLA ANALOG IC DEVICE DATA
7-53
•
MC14C89B, AB
APPLICATIONS INFORMATION
Description
The MC14C89AB and MC14C89B are designed to be
direct replacements for the MC1489A and MC1489. Both
devices meet all EIA-232 specifications and also the faster
EIA-562 and CCITT V.28 specifications. Noise pulse
rejection circuitry eliminates the need for most response
control filter capacitors but does not exclude the possibility as
filtering is still possible at the Response Control (RC) pins.
Also, the Response Control pins allow for a user defined
selection of the threshold voltages. The MC14C89AB and
MC14C89B are manufactured with a bipolar technology
using low power techniques and consume at most 700 JAA,
plus load currents with a +5.0 V supply.
MC14C89B or 0.95 V for the MC14C89AB). Figure 7 plots
equation (1) for two values of Vbat and a range of RRC.
If an RC pin Is to be used for low pass filtering, the
capacitor chosen can be calculated by the equation,
C
""
RC
1
2.02 kQ 211: f _ 3dB
(2)
where L3dB represents the desired -3 dB role-off frequency
of the low pass filter.
Figure 9. Application to Adjust Thresholds
Input Pin
Outputs
The output low or high voltage depends on the state of the
inputs, the load current, the bias of the Response Control
pins, arid the supply voltage. Table 1 applies to each receiver,
regardless of how many other receivers within the package
are supplying load current.
Table 1. Function Table
Receivers
Input'
11
Output'
H
L
L
H
"The asterisk denotes A, S, C, or D.
Receiver Inputs and Response Control
The receiver inputs determine the state of the outputs in
accordance with Table 1. The nominal VIL and VIH
thresholds are 0.95 V and 1.90 V respectively for the
MC14C89AB. For the MC14C89B, the nominal VIL and VIH
thresholds are 0.95 and 1.30, respectively. The inputs are
able to withstand ±3O V referenced to ground. Should the
input voltage exceed ground by more than ± 30 V, excessive
currents will flow at the input pin. Open input pins will
generate a logic high output, but good design practices
dictate that inputs should never be left open.
The Response Control (RC) pins are coupled to the inputs
through a resistor string. The RC pins provide for adjustment
of the threshold voltages of the IC while preserving the
amount of hysteresis. Figure 10 shows a typical application
to adjust the threshold voltages. The RC pins also provide
access to an internal resistor string which permits low pass
filtering of the input signal within the IC. Like the input pins,
the RC pins should not be taken above or below ground by
more than ±30 V or excessive currents will flow at these pins.
The dependence of the low level threshold voltage (VIU upon
RRC and Vbat can be described by the following equation:
V" - {VO.09
5.32 kQ
[
~ Vbat [RRC (1':+°2.02
+ 6.67
kQ
n
(11
x 106 Q2]
RRC
505 Q
VIH can be found by calculating for VIL using equation (1)
then adding the hysteresis for each device (0.35 for the
7-54
Another feature of the MC14C89AB and MC14C89B is
input noise rejection. The inputs have the ability to ignore
pulses which exceed the VIH and VII:. thresholds but are less
than 1.0 J.ts in duration. As the duration of the pulse exceeds
1.0 J.tS, the noise pulse may still be ignored depending on its
amplitude. Figure 8 is a graph showing typical input noise
rejection as a function of pulse amplitude and pulse duration.
Figure 8 reflects data taken for an input with an unconnected
RC pin and applied to the MC14C89AB and MC14C89B.
Operating Temperature Range
The ambient operating temperature range is listed as
-40°C to +85°C, and the devices are designed to meet the
EIA-232-E, EIA-562 and CCITT V.28 specifications over
this temperature range. The timing characteristics are
guaranteed to meet the specifications at +25°C. The
maximum ambient operating temperature is listed as +85°C.
However, a lower ambient may be required depending on
system use (Le., specifically how many receivers within a
package are used), and at what current levels they are
operating. The maximum power which may be diSSipated
within the package is determined by:
Po
-
(max) -
TJ(max) - TA
RSJA
where: RSJA = thermal resistance (typ., 100°CIW for the
OIP and 125°CIW for the SOIC packages);
TJ(max) = maximum operating junction temperature
(150°C); and
TA =ambient temperature.
Po = {[(VCC- VOH) X IIOHI] or
[(YOU X IIOL I ]}each receiver + (VCC X ICC)
where: VCC = positive supply voltage;
VOH, VOL = measured or estimated from Figure 2
and 3;
ICC =measured quiescent supply current.
As indicated, the first term (in brackets) must be calculated
and summed for each of the four receivers, while the last
term is common to the entire package.
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC26S10
Quad Open-Collector
Bus Transceiver
This quad transceiver is designed to mate Schottky TTL or NMOS logic to
a low impedance bus. The Enable and Driver inputs are PNP buffered to
ensure low input loading. The Driver (Bus) output is open~ollector and can
sink up to 100 mA at 0.8 V, thus the bus can drive impedances as low as
100 Q. The receiver output is active pull-up and can drive ten Schottky TTL
loads.
An active-low Enable controls all four drivers allowing the outputs of
different device drivers to be connected together for party-line operation.
The line can be terminated at both ends and still give considerable noise
margin at the receiver. Typical receiver threshold is 2.0 V.
Advanced Schottky processing is utilized to assure fast propagation delay
times. Two ground pins are provided to improve ground current handling and
allow close decoupling between VCC and ground at the package. Both
ground pins should be tied to the ground bus external to the package.
• Driver Can Sink 100 mA at 0.8 V (Maximum)
• PNP Inputs for Low-Logic Loading
• Typical Driver Delay =10 ns
• Typical Receiver Delay =10 ns
• Schottky Processing for High Speed
QUAD OPEN-COLLECTOR
BUS TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
E#
• Inverting Driver
PIN CONNECTIONS
Device
MC26S10P
MC26S10D
Gnd
Sus A
Enable
100
5.0 V
100 100 100
Receiver
Output A
Driver
Input A
Driver
InputS
Receiver
OutputB
Enable
14 Receiver
outpule
13 Driver
Inpule
EnableE
Driver
11 InpulD
10 Receiver
OutputD
BusB
Driver
Inputs
Driver
Inputs
MC26S10
MC26S10
Receiver
Outputs
Receiver
Oulputs
Driver
Inputs
TRUTH TABLE
Driver
Inputs
MC26S10
MC26S10
Receiver
Outputs
Enable
9 BusD
Gnd
Bus
Receiver
Output
l
l
H
l
H
X
H
l
Y
l
H
Y
l =
H=
X=
y=
Receiver
Outputs
100 100 100 100
S.OV
Enable
Driver
Input
Enable
low logic State
High logic State
Irrelevant
Assumes condition controlled
by other elements on the bus
7-55
MOTOROLA ANALOG IC DEVICE DATA
,
MC26S10
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltage
Input Voltage
Input Current
Symbol
Value
VCC
-0.5 to +7.0
Unit
Vdc
VI
-0.5 to +5.5
Ydc
mA
II
-3.0 to +5.0
Vo (Hi-z)
-0.5 to VCC
V
Output Current - Bus
10(B)
200
mA
Output Current - Receiver
10(R)
30
mA
TA
oto +70
Storage Temperature
Tstg
-65 to +150
Junction Temperature
TJ
150
'c
'c
'c
Output Vo~age - High Impedance State
Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS (Unless otherwise noted VCC = 4.75 to 5.25 V and TA = 0
VCC = 5.0 V and TA = 25'C.)
Characteristic
II
+70'C. Typical values measured at
Symbol
Max
Unit
Input Voltage - Low Logic State (Driver and Enable Inputs)
VIL
0.8
V
Input voltage - High Logic State (Driver and Enable Inputs)
VIH
Input Clamp Voltage (Driver and Enable Inputs)
(1IK=-18 mAl
VIK
-1.2
V
V
rnA
Input Current - Low Logic State (VIL = 0.4 V)
(Enable Input)
(Driver Inputs)
-0.36
-0.54
Input Current - High Logic State (VIH = 2.7 V)
(Enable Input)
(Driver Inputs)
20
30
ItA
Input Current - Maximum Voltage (VIH1 = 5.5 V)
(Enable or Driver Inputs)
100
Driver Output Voltage - Low Logic State
(IOL=40mA)
(lOL=70mA)
(IOL = 100 mAl
Driver (Bus) Leakage Current
(VOH=4.5V)
(VOL = 0.8 V)
V
0.33
0.42
0.51
0.5
0.7
0.8
IIA
10(0)
100
-50
100
ItA
1.75
V
0.5
V
-60
mA
45
70
mA
Min
Typ
Max
Unit
-
10
10
15
15
ns
-
14
13
18
18
ns
Driver (Bus) Leakage Curr
Receiver Input High Threshold
2.25
Receiver Input Low Threshold (VIH E) = 2.4 V)
2.0
2.0
Receiver Output Voltage - Low Logic State (IOL = 20 mAl
Receiver Output Voltage - High Logic State (IOH = -1.0 mAl
2.7
Receiver Output Short-Circuit Current (Note.1)
-18
Power Supply Current - Output Low State (VIL(E) = 0 V)
ItA
ICC
V
3.4
V
NOTE: 1. One output shorted at a time. Duration not to exceed 1.0 second.
SWITCHING CHARACTERISTICS (VCC = 5.0 V, TA = 25'C, unless otherwise noted.)
Characteristic
Propagation Delay Time Driver Input to Output
Propagation Delay Time Enable Input to Output
Symbol
tPLH(D)
tPHL(D)
tPLH(g)
tPHL(E)
-
Propagation Delay Time Bus to Receiver Output
tPLH(R)
tPHL(R)
-
-
10
10
15
15
ns
Rise and Fall Time of Driver Output
ITLH(D)
ITHL(D)
4.0
2.0
10
4.0
-
ns
7-56
MOTOROLA ANALOG IC DEVICE DATA
MC26S10
SWITCHING WAVEFORMS AND CIRCUITS
Figure 1. Data Input to Bus Output (Driver)
Vee
To Scope
(Input)
3.0V----"""""
Oliver
Input
50
VOH------+---~~~----~~
To Scope
(Output)
50 pF
(Inctudes
probe
and jig
~_ _ _ _ _-' capacitance)
Driver
Output
VOL-----~~
Vee
II
3.0V
50
Enable
tnput
OV
To Scope
(Output)
VOH
50pF
(Includes
probe
and jig
capacitance)
Oliver
Output
VOL
t
"i Figure 3. Bus Input to Receiver Output
~,,! ~
Vee
To Scope
(Output) 1N916
VOH-----r----'
Driver
Output
(Input) VOL
1.5V
VOH ---------'"
Receiver
Output
VOL-------------'----------J
MOTOROLA ANALOG IC DEVICE DATA
Vee
or
280
Equivalent
50
:!-= 15 pF (Total)
To
Scope
(Input..,)I---+--.
<:7k:;'
=0.8 V)
Receiver Output Short Circuit Current (VI(s/R) =0.8 V, \fIIt;~ 'l;;'~'.O V)"
..... (V~~ii~r'
.·,~"F\
Dnver Input Voltage - Low Logic State ( V I ( ' ,;",:"""
';,;"
-
,,":0:-:::;
i,~T
mA
2.5
-3.2
+0.04
-
mV
V
1.6
1.0
1.8
.7
-
-
V
-
-
0.5
V
SIR)
-15
rnA
2.0
-
-75
VIH(D)
-
V
VIL(D)
-
-
0.8
• 'oX!~:~~;\;'-"
=
Driver Input Current - Data Pins (VI(S/R)
(0.5 .. VI(D) .. 2.7 V)
,,' "
(VI(D) 5.5 V ) " , ,
~( -
3.7
-1.5
~>,>
=
"""" ,'.... _ - H." _
"';,;", '",
"(,~!~:, 400,;' :,~
,,
,"
Receiver Output Voltage - Low Logic State
(VI(s/R) 0.8 V, 10L(R) 16 mA, V(BUS)
=
~.:.
(R)
Receiver Output Voltage - High Logic State
(VI(s/R) 0.8 V, 10H(R) -800~, V(BUS)
=
ri
':l~>'~
I(BUS)
=
Receiver Input Hysteresis (VI(S/R)
Typ
V
=0.8 V)
Bus Current
(5.0 V .. V(BUS~ .. 5.5 V)
(V(BUS) 0.5 V
(VCC 0 V, 0 V .. V(BUS) .. 2.75 V)
=
Symbol
V
p.A
11(0)
IIB(D)
-200
-
-
40
200
II(SIR)
IIB(s/R)
-100
-
20
100
II(E)
IIB(E)
-200
-
-
20
100
VIC(D)
-
-
-1.5
V
VOH(D)
2.5
-
-
V
Driver Output Voltage - Low Logic State (Note 1)
(VI(S/R) 2.0 V, 10L(D) 48 mAl
VOL(D)
-
-
0.5
V
Output Short Circuit Current
(VI(S/R) 2.0 V, VIH(D) 2.0 V, VIH(E)
10S(D)
-30
-
-120
mA
-
63
106
85
125
,,'
=
!';"'i'",
Input Current - Send/Receive
(0.5 .. VI(S/R) .. 2.7 V) ,':;,:::~;/>
(VI(S/R) 5.5 V ) , " " x i ( ' ,
=
,,:;,;:~~~,)';'
=2.0 V, IIC(D) =-18 rnA)
Driver Output Voltage - High Logic State
(VI(s/R) 2.0 V, VIH(D) 2.0 V, VIH(E)
=
=
=
-
p.A
=
Driver Input Clamp Voltage (VI(s/R)
-
~
.. ,
;"..'
Input Current - Enable
(0.5 .. VI(E) .. 2.7 V)
(VI (E) 5.5 V)
' ',',
=
=2.0 V, 10H =- 5.2 rnA)
=
=
=2.0 V)
Power Supply Current
(Listening Mode - All Receivers On)
(Talking Mode - All Drivers On)
MOTOROLA ANALOG IC DEVICE DATA
ICCL
ICCH
-
-
mA
7-59
MC3448A
SWITCHING CHARACTERISTICS (Vee = 5.0 V, TA = 25°C, unless otherwise noted)
Propagation Delay of Driver
(Output Low to High)
(Output High to Low)
tPLH(D)
tPHL(D)
Propagation Delay of Receiver
(Output Low to High)
(Output High 10 Low)
tPLH(R)
IPHL(R)
ns
-
-
15
17
-
-
25
23
-
ns
NOTE: 1. A modilication of the IEEE 488-1978 Bus Standard changes VOL(D) Irom 0.4 to 0.5 V maximum to permit the use of Schottky technology.
SWITCHING CHARACTERISTICS (continued)
Characteristic
Propagation Delay Time - Send/Receive to Data
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low
(Vee =5.0 V, TA =25°C, unless otherwise noted)
Symbol
Min
Typ
Max
ns
tPHZ(R)
tpZH(R)
tPLZ(R)
tPZL(R)
30
30
30
30
Propagation Delay Time - Send/Receive to Bus
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low
30
30
30
30
Turn--On Time - Enable to Bus
Pull-Up Enable to Open Collector
Open Collector to Pull-Up Enable
30
20
7-60
Unit
ns
ns
MOTOROLA ANALOG IC DEVICE DATA
MC3448A
PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
Figure 1. Bus Input to Data Output (Receiver)
Input
Ou1p~"';'
~
t>.-~~t
3.0 V
To Scope
(Input)
Send!
To Scope
(Output)
Roc Bus
Dnverlnput
or Enable "
2.3 V
3B.3
.(0::.
.. '
;""/
1.5 V
1"'2.0'
f=1.0MHz
tn.H=trHL" 5.0 ns (10%10 90%)
Duty Cycle =50%
1.:::,0\." .
Pull-Up Enable
". :::,/
,;~.~.'
':':;i tpLI'.I.ID,. ):. ,~.:;. ·~.;;jtv_<______._~;:
\~-"
O.BV~VOL
,<.~;'<:',.~ "4'~l
.. Includes Jig and
Probe Capacitance
k .
30V
~"""'15V
,~ .,
Sendlftec
Probe:~acitance
.. )
":"
,(: ~>.:~:~fr
&OV
_---3.0 V
Input
'--------·I----OV
Output
High 10 Open
Output
Low to Open
Pulse
Generator
I--;---""-ov
51
CL = 15 pF (Includes Jig and
Probe Capacitance
MOTOROLA ANALOG IC DEVICE DATA
f= 1.0 MHz
tTLH = tTHL " 5.0 ns (10% 10 90%)
DUty Cycle =50%
7--61
a
MC3448A
Figure 4. SendIReceive Input to Data Output (Receiver)
,-------"\.----3.ov
Inplll
5.0V
---OV
To Scope
(0uIput)
280
I~~----~-I-~~-~--OV
CL =15 pF (Includes Jig and
Probe capacitance
51
Figure 5. Enable Input to Bus Output (
To5cope
(0uIput)
3.0 V
_----~.--- 3.0V
•
caia
Bus
Sen0
'.'.
::>
J!l
!
-10
-12
-14
-4.0
J
I
---
Al&a f ConIormsIo
"aragillJ)h"3-5.3 of
IEEE SIandMI .
-
481H978 .
IIICcj5:0V
-2.0
I
o
2.0
VBUS. BUS VOLTAGE (V)
J
4.0
~
-
6.0
MOTOROLA ANALOG IC DEVICE DATA
MC3448A
Figure 8. Simple System Configuration
5.0 V
··•
·
Ti!!2
EOI
Ern
SAC
SRll
07
AIW
ANI
·
AS2
.f
REN
liEN
IFC
iFC
0.18
OB7
ASil
i
·
··
00
0B0
Ti!!l
.s~
~
··
··•
•
MC6802
OR
MC6800
MPU
I
A15
I
fRO
I
~
A1'N
{
NOAC
..
!!!
I
I
OAV
DlOl
0103
1-1---"''---+-1I---I
M
Dl05
1-1-----+-1I---I~
0106
I-r------t-t----1
ili5
1-1-----+-11---1
ili5
NOTE 1: AHhough the MC3448A transceivers
are non-inverting, the 488-1978 bus callouts
appear inverted wHh respect to the MC68488
pin designations. This is because the
488-1978 Standard is defined for negative
logic, while all M6800 MPU components
make use of posHive logic formal.
I-r------t-t----1~
r---L__
Trig ....
IEEE 488-1975 BUS
MOTOROLA ANALOG IC DEVICE DATA
...J
--r_ _
NOTE 2: Unless proper considerations are
provided, it is recommended that the pull-up
enable pins on the MC3448As be grounded,
selecting the open--collector mode.
7-63
®
MOTOROLA
MC3450
Quad MTTL Compatible
Line Receivers
The MC3450 features four MC751 07 type active pull up line receivers with
the addition of a common three-state strobe input. When the strobe input is
at a logic zero, each receiver outputstate is determined by the differential
voltage across its respective inputs. With the strobe high, the receiver
outputs are in the high impedance state.
The strobe input on both devices is buffered to present a strobe loading
factor of only one for all four receivers and inverted to provide best
compatability with standard decoder devices.
QUAD LINE RECEIVERS
WITH COMMON THREE-STATE
STROBE INPUT
SEMICONDUCTOR
TECHNICAL DATA
• Receiver Performance Identical to the Popular
MC751 07/MC751 08 Series
• Four Independent Receivers with Common Strobe Input
• Implied "AND" Capability with Open Collector Outputs
• Useful as a Quad 1103 type Memory Sense Amplifier
TRUTH TABLE
•
Output
Input
V,O ;;,
+25mV
-25 mV .;
V,O ';+25 mV
=
=
=
=
MC3450
L
H
H
L
z
PSUFFIX
PLASTIC PACKAGE
CASE 648
H
L
H
V,O .;
-25mV
L
H
Z
I
Strobe
Low Logic State
High Logic State
Third (High Impedance)
Indeterminate State
PIN CONNECTIONS
Figure 1. A Typical M
' Sensing Application for a
4 k Word by 4-Bit Memory
ngement Employing
1103 Type Memory Devices
Data
Bit #4
Data
Bi1#3
200
Data Bit 0
#2
Data
Brt#2
200
DataBit
ORDERING INFORMATION
ut#1
18k
5,OV ........,.-~-------~-v--
200
Only four MC3450 devices are required for
a 4 k word by 16-bit memory system.
7-64
Strobe_-o-ti
Data
Bi1#1
Device
Operating
Temperature Range
Package
MC3450P
TA = 0 to +70°C
Plastic OIP
MOTOROLA ANALOG IC DEVICE DATA
MC3450
MAXIMUM RATINGS (TA =0 to +70o e, unless otherwise noted.)
Rating
Power Supply Voltages
Symbol
Value
Unit
Vdc
VCC, VEE
±7.0
Differential Mode Input Signal Voltage Range
VI DR
±6.0
Vdc
Common Mode Input Vottage Range
VICR
±S.O
Vdc
Strobe Input Vottage
VI(S}
5.5
Vdc
1000
6.6
1000
6.6
mW
mW/"C
mW
mW/"C
Power Dissipation (Package Limitation)
Ceramic Dualln-Line Package
Derate above TA = 25°C
Plastic Dual In-Line Package
Derate above TA = 25°C
Po
Operating Temperature Range
TA
Oto+70
°C
Storage Temperature Range
Tstc
-65 to +150
°C
RECOMMENDED OPERATING CONDITIONS (TA =0 to +70oe, unless otherwise noted.)
Characteristic
Power Supply Vottages
Output Load Current
Symbol
Min
Max
Unit
VCC
VEE
+4.75
-4.75
+5.25
-5.25
Vdc
10L
16
mA
Differential Mode Input Vottage Range
VIDR
+5.0
Vdc
Common Mode Input Voltage Range
VICR
+3.0
Vdc
VIR
+3.0
Vdc
Input Voltage Range (any Input to Ground)
ELECTRICAL CHARACTERISTICS (Vee = +5.0 Vdc, VEE = -5.0 Vdc,
Max
Unit
High Level Input Current to Receiver Input
75
J.LA
Low Level Input Current to Receiver Input
-10
J.LA
High Level Input Current to Strobe Input
VIH(S} = 2.4 V
VIH S =5.25 V
40
1.0
mA
-1.6
mA
Characteristic
Low Level Input Current to Strobe Input
VILS =0.4V
High Level Output Voltage
Vdc
2.4
High Level Output Leakage Current
ICEX
Low Level Output Voltage
VOL
Short-Circuit Output Current
Output Disable Leakage Curre
lOS
J.LA
J.LA
-18
0.5
Vdc
-70
mA
f/'-=_____I-_.-...::lo:::ff_ _+ ____-I-____f-__4_0_-If---''--_--I
J.LA
High Logic Level Supply Current ,fro
ICCH
45
60
mA
High Logic Level Supply Current from VEE
IEEH
-17
-30
mA
Max
Unit
25
ns
25
ns
21
ns
18
ns
27
ns
29
ns
SWITCHING CHARACTERISTICS (Vee =+5.0 Vdc, VEE =-5.0 Vdc, TA = +25°e, unless otherwise noted.)
MC3450
Min
Typ
-
tPHL(S}
-
tPLH(S}
-
-
Characteristic
Symbol
High to Low Logic Level Propagation Delay
11me (Differential Inputs}
tPHL(D}
Low to High Logic Level Propagation Delay
11me (Differential Inputs}
tPLH(D}
Open State to High Logic Level Propagation
Delay 11me (Strobe)
tpZH(S}
High Logic Level to Open State Propagation
Delay 11me (Strobe)
tPHZ(S}
Open State to Low Logic Level Propagation
Delay 11me (Strobe)
tpZL(S}
Low Logic Level to Open State Propagation
Delay 11me (Strobe)
tPLZ(S}
High Logic to Low Logic Level Propagation
Delay 11me (Strobe)
Low Logic to High Logic Level Propagation
Delay 11me (Strobe)
MOTOROLA ANALOG IC DEVICE DATA
-
-
-
ns
ns
7-65
•
MC3450
Figure 2. Circuit Schematic
(1/4 Circuit Shown)
V~o---~--~----~----~------~--------~----~------~~
850
190
850
4.0k
1.6k
OUTPUT
·~r
GND
STROBE
4.0k
4.0k
VEE
Figure 3. ICEX. VOH. and VOL
II
V1
V2
----;:.0-1
---....:.;-o-t
0.8 v -+---;:.o-t
S.OV
V4 -+-I....-iro-l
(MC3452)
5.26V
-
MC34&O
va
vs_....._ .......o-I
--0-0
v.
S,OV
GND
GND
-S.QV
3.0 V
2.975 V
GND
S.OV
-2.976 V
-3.0V
-3.QV
GND
11
Q,4mA
-16mA
Channel A shown under test. Other channels are tested similarly.
ICEX
11.
(MC3450)
Figure 4. ICCH and IEEH
Figure 5. IIH(S) and IIL(S)
3.0V _ . - - - - - - - - - ,
mo--45.26V
5.25 V
~-~43.0V
ma-t-+4-5.25V
-5.26 V
7-66
MOTOROLA ANALOG IC DEVICE DATA
MC3450
TEST CIRCUITS (continued)
Figure 6. lOS
Figure 7. IIH
B>---. 5.25 V
8>---. 5.25 V
25mV_--+c8
8>+....... 3.0V
0.8 v -+--+C>:-l
8 > + + . -5.25 V
lOS
8 > + + . -5.25 V
Channel A shown under test, other channels are tested similarly.
Only one output shorted at a time.
Figure 8. IlL
VI-2.0V
Vl-f-~~:-t
"""1)--.... 5.25 V
B>---. 5.25 V
3.0 v-f-t--<>i-I
II
8>++.-5.25 v
Output of Channel A shown under test, other outputs are
tested similarly for VI 0.4 V and 2.4 V.
=
eceiver Propagation Delay tPLH(D) and tPHL(D)
5.0 V
l00mV ....- -...--o,;-I
Ein
200mv~--50%
OV
~~(~_~____tPHL(D)
Eo
1.5 V
VOL
EO
Output of Channel B shown under test, other channels are tested similarly.
81 at "A" for MC3452
81 at "B" for MC3450
CL = 15 pF total for MC3452
CL = 50 pF total for MC3450
MOTOROLA ANALOG IC DEVICE DATA
Eln waveform characteristics:
trLH and trHL .. IOns measured 10% to 90%
PRR= 1.0 MHz
Duly Cycle = 500 ns
7-67
MC3450
TEST CIRCUITS (continued)
Figure 11. Strobe Propagation Delay Times tPLZ(S) tPZL(S) tPHZ(S) and tPZH(S)
5.0V
Vl_--_~8
VI
V2
51
52
CL
IpLZ(S)
100mV
GND
Closed
Closed
ISpF
SOpF
IpZL(S)
100mV
GND
Closed
Open
IpHZ(S)
GND
l00mV
Closed
Closed
ISpF
IpZH(S)
GND
l00mV
Open
Closed
50pF
Output of Channel B shown under test,
other channels are tested similarly.
Ein
II
3.::---~
--:::J
tPLZ(S) {
I-- tPLZ(S)
ipHZ(S)
. - _ - - -1.5V
EO
VOH-O.5V
......_ _ _ *1.5V
Eln
tPZH(S) {
3'OV~
50%
,:
Eo
-----f.1.5 V
-OV
7-68
MOTOROLA ANALOG IC DEVICE DATA
MC3450
APPLICATIONS INFORMATION
Figure 12. Bidirectional Data Transmission
5.0V
180
~r __t-~~~~lt1-~
380
Strobe
114 (MC3450)
The thre~tate capability of lIle MC3450 permits
bidirectional data transmission as Illustrated.
Figure 13. Single-Ended Unl-Bus™ Line Receiver
Application for Minicomputer
IN914
orequiv
•
3.0k
+5.0V
S1robe
180
OataBu8
5.0
390
MC3450
180
OataBu8
390
Data
Output
Data
Lines
5.0V
f80
Addre.ssBu....- - , , -.....
5.0 V
390
-+-o.,
180
-+_--+-o-tF-l/'
Control Bu....
~H--o-.. Control
I
I
I
390
t
Strobe ....-----+-c~IH,::>O---..... : - Trademark of Olg"al
_____ .J
Equipment Corp.
L._~
To AddllionaJ
Receivers
The MC3450 can be used for slngle-ended as well as differential line
receiving. For slngle-ended line receiver applicatIons, such as are
encountered in min)computers, the configuration shown In Figure 15 can
be used. The voltage source, which generates Vref. should be designed
80thatllle Vr.fvoltagels hallway between VOH(mln)and VOL(max). The
maximum Input overdrive required to guarantee a gIven logic state Is
extremely small, 25 mV maximum. This low-lnput overdrive enhances
differential noise immunity. Also the high-Input Impedance of the line
receiver permits many receivers to be placed on a single line with
minimum load effects.
MOTOROLA ANALOG IC DEVICE DATA
S1robe
01
02
as
Q4
AI
A2
'~----'
7-69
MC3450
APPLICATIONS INFORMATION (continued)
Figure 15. Party-Line Data Transmission System
with Multiplex Decoding
~robe
Data
Inputs
stro~
MC3453
Strobe ' " - -
'"--
-L
~
~
Data
Inputs
< -
MC3453
-
~r
~~ ~
-
II
~
Data
Inputs
~
MC3453
-r
Strobe
-
Data
Inputs
Data
Outputs
MC3450
Z
~
~
"",4>
'1 f. .. ~.~
•• ;...f
~
t;
~obe
r-=
Data
Outputs
MC3450
O·
~
Y
MC7404
04
E
7-70
f-of-of-o-
112
MC4007
Data
Outputs
MC3450
Str~
r-~
01
213
Data
Outputs
~
~
'4
MC345~
~~obe
I
X
X
~
r---'LASTIC PACKAGE
"
CASE648
..>/
r"
'i-"
•
PIN CONNECTIONS
Figure 1. Party-Line Data Transmission Sy
Multiplex Decoding
Vee
InputA 1
InputB
Y{ 2
OUtputA
z
Da'
Inputs
Z{ 4
-.t--.t
e---I--o-I
OutputC
y
InputD
Da.
,,,,", e---I+--o-I
TRUTH TABLE
(positive logic)
"";+--o-I
Inpu. e---I+--o-I
00.
Da'
,,,,,IB
....,/++-0-1
Output
Current
Logic
Input
Inhibit
Input
Z
y'
H
H
On
Off
L
H
Off
On
H
L
L
Off
Off
Off
Off
L
L z Low Logic Level
H z High Logic Level
ORDERING INFORMATION
Device
At
"
MOTOROLA ANALOG IC DEVICE DATA
At
"
MC3453P
Operating
Temperature Range
TA
=0 to +70°C
Package
Plastic DIP
7-71
MC3453
MAXIMUM RATINGS (TA = 0 to +70 0 e, unless otherwise noted.)
Symbol
Value
Unit
Vec
Vee
Vin
+7.0
-7.0
5.5
V
V
Common-Mode Output Voltage Range
VOCR
-5.0 to +12
V
Power Dissipation (Package Limitation)
Plastic Dual In-Line Package
Derate above TA 25°C
Po
1000
6.6
mW
mWfC
Power Supply Voltage
Logic and Inhibitor Input Voltages
=
Operating Ambient Temperature Range
TA
Oto+70
°C
Storage Temperature Range
Plastic and Ceramic Dual In-Line Packages
Tstg
-65 to +150
°C
RECOMMENDED QPI5RATING CONDITIONS (See Notes 1 and 2.)
Characteristic
Power Supply Voltages
Symbol
VCC
Vee
Common-Mode Output Voltage Range
Positive
Negative
II
Max
Min
+4.75
-4.75
Unit
V
+5.25
-5.25
V
VOeR
0
+10
-3.0
NOTES: 1. These voltage values are in respect to the ground terminal.
2. When not using all four channels, unused outputs muat be groUnded.
DEFINITIONS OF INPUT LOGIC LEVELS·
Characteristic
High-Level Input Voltage (at any Input)
Low-Levellnput Voltage (at any input)
Min
Max
5.5
0.8
2.0
0
Unit
V
V
• The algebraic convention, where the most positlv
ooe, unless otherwise noted.)
ELECTRICAL CHARACTE
Symbol
High-Level Input Current (L
(VCC Max, Vee Max, V IH
(VCC
=
=
.4
=Max, Vee =Max, VIHL =Vec M
IIH
=
=
IlL
=
=
=
=
=
=
=
=
=
=
=
=
=
L
Low-Level Input Current (Logic Inputs)
(VCC Max, Vee Max, VIL 0.4 V)
L
High-Level Input Current (Inhibit Input)
(Vee Max, Vee Max, VIH 2.4 V)
I
(Vec Max, Vee Max, VIH Vee Max)
I
Low-Level Input Current (Inhibit Input)
(VCC Max, Vee Max, V IL 0.4 V)
I
Output Current ("ON" state)
(VCC Max, Vee Max)
(VCC Min, Vee Min)
=
Output Current ("OFF" state) (VCC
=Min, Vee =Min)
Supply Current from Vec (with driver enabled)
(V IL 0.4 V, V IH 2.0 V)
L
I
=
=
Min
Typ#
L
Max
Unit
40
j.lA
1.0
mA
-1.6
mA
40
j.lA
-1.6
mA
L
IIH ,
I
IlL
I
mA
10(on)
11
11
15
10(off)
5.0
100
j.lA
ICC(on)
35
50
rnA
6.5
#AII typical values are at Vee = 5,0 V, VEE = -5.0 V, TA = 25°e.
##For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions for the applicable device typs.
Ground unused Inputs and outputs.
7-72
MOTOROLA ANALOG IC DEVICE DATA
MC3453
ELECTRICAL CHARACTERISTICS (TA: 0 to +70°C unless otherwise noted)
Characteristic##
Supply Current from VEE (with driver enabled)
(V IL : 0.4 V, V IH : 2.0 V)
L
I
Supply Current from VCC (wHh driver inhibited)
(V IL : 0.4 V, V IL : 0.4 V)
L
I
Supply Current from VEE (with driver inhibited)
(VIL : 0.4 V, V IL : 0.4 V)
L
I
Symbol
Min
Typ#
Max
Unit
IEE(on)
-
65
90
rnA
ICC(off)
-
35
50
rnA
IEE(off)
-
25
40
rnA
#AII typical values are at Vee =5.0 V, VEE =-5.0 V, TA =25'e.
##For cond~lons shown as Min or Max, use the approprtate value specHied under recommended operating conditions for the applicable device type.
Ground unused inputs and outputs.
SWITCHING CHARACTERISTICS (VCC: 5.0 V, VEE: -5.0 V, TA: 25'C.)
Characteristic
Propagation Delay Time from Logic Input to
Output Y or Z (RL : 50 ohms, CL : 40 pF)
Propagation Delay time from Inhibit Input
to Output Y or Z (RL : 50 ohms, CL = 40 pF)
Symbol
MIl)
f,·.. ,~,.,.
.
.',
Typ
Max
Unit
9.0
9.0
17
17
ns
20
16
25
25
ns
•
MOTOROLA ANALOG IC DEVICE DATA
7-73
MC3453
Figure 2. Logic Input to Outputs Propagation
Delay Time Waveforms
.Figure 3. Inhibit Input to Outputs Propagation
Delay Time Wavefo.rms
Logic Input
3.0 V
Inhiblt
Input
OV
OV
3.0 V
50%
Output
y
OutputZ
OV
OV
50%
Output
Z
Figure 4. Logic Input to Output Propagation
Delay nme Test Circuit
II
Ein to Scope
VCC=5.0V
50.--....-->-1
Output
to
Z
Scope
50
=-5.0 V
1.0k
Channel A shown under test, the other
channels are tested similarly.
7-74
Channel A shown under test, the other
channels are tested similarly.
MOTOROLA ANALOG IC DEVICE DATA
MC3453
Figure 6. Circuit Schematic
(1/4 Circuit Shown)
Veeo----.--------~--~----_.~~----------+_--~
To Remainder
of auad
Single Driver
Oulputs
Logic O_.....=-.....:J. .J
Input
VEEo---------------------------~~--~~~--~
__
~~
To Remainder
of auad
------------------------------------~~~---~~---------- --
Vee
II
Inhibit o-_-#--=:j4.--J
Input
MOTOROLA ANALOG IC DEVICE DATA
7-75
®
MOTOROLA
MC3467
Triple Wideband Preamplifier
with Electronic Gain
Control IEGC)
The MC3467 provides three independent preamplifiers with individual
electronic gain control in a single 18-pin package. Each preamplifier has
differential inputs and outputs allowing operation in completely balanced
systems. The device is optimized for use in 9-track magnetic tape memory
systems where low noise and low distortion are paramount objectives.
The electronic gain control allows each amplifier's gain to be set
anywhere from essentially zero to a maximum of approximately 100 VN.
• Wide Bandwidth - 15 MHz (Typical)
• Individual Electronic Gain Control
• DifferentiallnputlOutput
TRIPLE MAGNETIC TAPE
ME
Y PREAMPLIFIER
II
PSUFFIX
PLASTIC PACKAGE
CASE 707
PIN CONNECTIONS
Simplified Application
High Performance 9-Track Open Reel
Tape System
VI(EGC)
NRZllcp
Select
Active
Differentiator
T
A
P
E
lSI
Formatter
MC8500
MC8S01
MC8S02
MC8S20
ORDERING INFORMATION
Device
MC3467P
7-76
Operating
TemperetureJ'!ange
TA
=0 to +70°C
Package
Plastic DIP
MOTOROLA ANALOG IC DEVICE DATA
MC3467
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltages
Positive Supply Voltage
Negative Supply Voltage
Symbol
Value
Unit
VCC
VEE
6.0
-9.0
VI(EGC)
-5.0toVCC
V
VID
±5.0
V
VIC
±5.0
V
tsc
10
s
°C
V
EGC Voltages (Pins 1, 6 and 13)
Input Differential Voltage
Input Common-Mode Voltage
Amplifier Output Short Circuij
Duration (to Ground)
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature
TA
Oto+70
Tstg
-65to+15O
°C
TJ
+150
°C
'.!
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = -6.0 V, f =100 kHz, TA = 0 to-, +7(IPd;>Ilni~ss
otherwise noted.)
.'
~
Characteristic
Symbol
Power Supply Voltage Range
Positive Supply Voltage
Negative Supply Voltage
Operating EGC Voltage
VCCR
VEER
v.:.,
:,,"y
./;L
Output Voltage Swing (Balanced) (Figure 1)
i·
:";'",:",.",
(ei = 200 mVpp)
...
c· ,,'"
Input Common-Mode Range
. ~. t.'-,
"
0'
•.
>.
Differential Output Offset Voltage
(TA= 25°C)
Common-Mode Output OffSllt.~e
(TA = 25°C)
..
Common-Mode Rejection Ratio (Figure 2),
=
VI(EGC) 0, VCM
(f = 100 kHz)
(f= 1.0 MHz)
-
0.5
2.0
VN
0.2
-
-
Vpp
VOR
6.0
B.O
-
Vpp
,.
AVO.
I',
...
"t:·
VID~'"
•••:C'"'-'
:.>
. P.r'u,
V
5.25
-7.0
VN
~,
Maximum Input Differential Voltage
(Balanced) (TA = 25°C)
Unit
120
,.";)
(VI(EGC) = VCC)
Max
VCC
>.
Differential Voltage Gain
·:',"'-6.0
~5.5,< •. ,
.~;",>.~ .:.:!
,.>i·~ . :·")"
"I',
"'.
./.,,;.';/~
,,'"
.{)
-
~.
=
TVP
100
VI(E:~
Differential Voltage Gain (Balanced)
(VI(EGC) 0, ei 25 mVpp) (See Figure 1)
=
..
<
100
lS0
VI, INPUT VOLTAGE (mVpp)
200
II 1111
-30
0.1
250
SO
SO
1 LI Ull
1
1.0
10
I, FREQUENCY (MHz)
Jill
100
Norrilllllli:llll!id Positive Power Supply
Power Supply Voltage
Figure 9. Normalized Voltage Gain
versus Ambient Temperature
~
~'OO
•
1.04 r - - , - - - , - - - , - - r - - , - - - , - - - , - - - ,
~
!1.02
z
~ 1.00
UJ
c:l
~
~
0.98
I
,' ' ",~:~~J:t~'96
>
< 0.96
o
4L.7-S-4...l..8--4.L8S-4..J..9--4..L..9S-..J.S.-0-S.L...0-S--l
S.1 -S.J...1-S --lS.L...
2 ---l
S2S
10
TA, AMBIENTTEMPERAT~11l:1' "
"",
:;.f(" j
VCC, POSITIVE POWER SUPPLY VOLTAGE (Vdc)
~~~.'~ ./fi. ~:';:~;::~~i('~
~e ~owe:-~~~y
Figure 12. Normalized Power Supply Currents
versus Ambient Temperature
Figure 11. Normalized
Current versus Negat~'~wer SuP.I>ly Voltage
I
G
:::;
'tL
l
;:>/" ~.;"
"'~'
1<,
1.02
1.041---t_-I-_-+-_;~~!~+:' ' ' :_'~;j- -.M.", . ,. '\i-,- , -,:'~>f-;_,i-+--+--l
"j,'
1.021--+--+-+--+--t--I---+--+----I1--I
0..
0..
1il til
_I
ffi~
____ -
....--~
./
3: :;;! 1.00 f---t--+-+---:;;;;¥=-I---+-+-+--t----t
~ ~
____ ~
VCc=S.OV
UJ 0
.....TA,= 2SoC
~~
n = IEE(T)
0.981--+--+-+--+--tlEE (2S°C)
:fl
_~
~
ffi
z
TeS\CircuittFigUre4
..tB
0.96
-5.0
I
I
I
-S.S
-6.0
-6.S
-7.0
VEE, NEGATIVE POWER SUPPLY VOLTAGE (Vdc)
MOTOROLA ANALOG IC DEVICE DATA
-7.S
./
V
0.99
/
0.98
o
/
,/'"'
VCc=s.O V
VEE =--M V
ICC (T)
lEE (T) n=---=--ICC (2S°C)
lEE (2S°C)
I
I FigureI 4
See
For Test Circuit
I
10
-
k--:'": ~
1-
I
20
30
40
50
60
TA, AMBIENT TEMPERATURE (0C)
70
80
7-79
MC3467
Figure 13. Differential Voltage Gain versus
Electronic Gain Control Voltage (VI(EGC»
Figure 14. Common-Mode Rejection Ratio
(CMRR) versus Frequency
~-100r---;-"-;rn~~'-'-T>"TIT---r-r.-nr~
Q
!;(
a:
5
~ -ao
lil
a:
VCC = 5.0 V
VEE = -a.0 V
TA=25°C
w
~
-ao
V
CMRR = 2010g - A
vO
V ICM
Av=100VN=40dB
~
I-_V-jIC:..cM
::,=,l-r-'0'"tV
-'!PP1tl+- Test Circuij = Figure 2 -I-I-++t+I-H
~
~O~--I-H-I-t+l~--+4-+-+++itt---I--+4-~~
8
a:
O~~~~~~~~~__~~~~
o
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VI(EGC}, ELECTRONIC GAIN CONTROL VOLTAGE (VOLTS)
::;
(,)
0.1
100
Figure 15. Phase Shift versus Frequency
•
~
ttl
ffi
o
t
:;:
en
eno. ~
~Or-~~-+~+H+-~~-++T~+-~~-r++~
~Or---r-~~rHtr--+-~++++~~~-+;-HH~
-120 1-~~-+-++I+I+--+-+-++-I+1H+--.,....+-t-++-H:
-160 r---r-H-I-t+lft---+-++-+++itt---I-~n-200
I--I-I'+-H-tttt--t-l-++++ttt--t-
-240
r-~-1-+~+H+-~--f-++++l-
5.0
03
04
Outputs
Inputs
01
EGC
Input
R1
02
VEE
7-80
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROI.A
MC3481
MC3485
Quad Single-Ended
Line Drivers
The MC3481 and MC3485 are quad single-ended line drivers specifically
designed to meet the IBM 360/370 I/O specification (GA22-6974-3).
Output levels are guaranteed over the full range of output load and fault
conditions. Compliance with the IBM requirements for fault protection,
flagging, and power up/power down protection for the bus make this an ideal
line driver for party line operations.
IBM 360/370
QUAD LINE DRIVERS
.
,
.:'.ICONDUCTOR
., 'TECHNICAL DATA
• Separate Enable and Fault Flags - MC3481
• Common Enable and Fault Flag - MC3485
• Power Up/Down Does Not Disturb Bus
• Schottky Circuitry for High-Speed - PNP Inputs
• Internal Bootstraps for Faster Rise limes
• Driver Output Current Foldback Protection
• MC3485 has LS Totem Pole Driver Output
PSUFFIX
•
PLASTIC PACKAGE
CASE 648
'.'t
.Vee
Driver Output A 1
Driver Output A 1
";;-,,=t'
Driver Output 0
Fault Flag A 2
14
Dnver Output A 2
15
taiJIfFI8gU
Enable AB 4
Driver OUlputD
14 Dnver OutputD
Enable ABCD 4
t----i>-t++-'
L...l-=::r-"'-__ II2 FaUIfl'Iag
(Open Colleclur)
Dnver Output B 6
Driver Output B 7
10
FaiiIfFI89C
9
Driver Output C
10 Driver Output C
Driver OUtput B 7
9
Driver Output C
Simplified Application
1/4 MC3481 or
1/4 MC3485
r-------,
I
I
I
Coaxial
r - - - ...,
cab~le
:
i
t
I
I
I
I
L ___ .J
ORDERING INFORMATION
Device
MC3481P
Operating
Temperature Range
Package
Plastic DIP
MC3485P
MOTOROLA ANALOG IC DEVICE DATA
7-81
MC3481 MC3485
MAXIMUM RATINGS (TA = 25°e, unless otherwise noted)
Rating
Power Supply VoHage
Input Voltage
Driver Output VoHage
Symbol
Value
Unit
Vee
+7.0
V
VI
10
V
V
Vo
5.5
Power Dissipation (Package Limitation)
Derate Above TA = 25°e
Po
1/ReJA
962
7.7
mW
mwoe
Operating Ambient Temperature Range
TA
Oto + 70
°e
Junction Temperature
TJ
+150
°e
Tstg
65 to + 150
°e
Storage Temperature Range
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
High Level Output eurrent'
Symbol
Max
Unit
Vee
Min
5.95
Vdc
10H
59.3
mA
Operating Ambient Temperature Range
•
+70
SWITCHING CHARACTERISTICS (See Note 1. Unless otherwise noted, th
range. 1/0 Driver characteristics are guaranteed for Vee = 5.0 V ± 10 % and
Vee = 5.25 to 5.95 V. Typical values measured at TA = 25 °e and Vee
over recommended temperature
Istics are guaranteed for
, Figures 1 and 2 for load conditions.)
Characteristics
Propagation Delay Time
High-to-Low-Level, Driver Output
As 1/0 Driver
As Select-Out Driver
Low-to-High-Level, Driver Output
As 1/0 Driver
As Select-Out Driver
High-to-Low-Level, "D"'ri"'ve"'r"O"'u"'tp=ut
As 1/0 Driver
As Select-Out Driver
Low-to-High-Level, ....
D"'ri'"'ve:::r""""=
As 1/0 Driver
As Select-Out Driver
Low-to-High-Level, Fault Flag - MC3481
As I/O Driver
As Select-Out Driver
Ratio of Propagation Delay Times
As 1/0 Driver
Max
Unit
ns
18
19
20
21
tPHL(D)
tPHL(DS)
25
26
tPLH(D)
tPLH(DS)
25
26
tPHL(F)
tpHL(FS)
45
47
tPLH(F)
tpLHFS
40
42
1.0
NOTES: 1. Reference IBM specffication GA22-6974-3 for test tenninology.
2. The fau~ protection Circuitry of the MC3481 and MC348S requires relatively clean input voHage wavefonns for current oparation. Noise pulses which
enter the threshold region (0.8 to 2.0 V) may cause the output to enter the fault protect mode. To exit the protect mode, ij is necessary to gate an
input of the effected driver to the low logic state.
7--82
MOTOROLA ANALOG IC DEVICE DATA
MC3481 MC3485
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, these specifications apply over recommended power supply and
temperature ratings. Typical values measured at TA = 25°e and VCC = +5.0 V)
MC3481
Characteristic
High-Level Input Voltage Note 2
Min
Typ
Max
Min
Typ
Max
Unit
-
-
2.0
-
V
0.6
-
-
0.6
V
VIH
2.0
Low-Level Input Voltage Note 2
VIL
-
High-Level Input Current
(VCC = 4.5 V, VIH = 2.7 V) - Input
Enable
(VCC = 4.5 V, VIH = 5.5 V) - Input
Enable
IIH
Low-Level Input Current
(VCC = 5.95 V, VIL = 0.4 V) - Input
Enable
IlL
Input Clamp Voltage
(IIC = -16 rnA)
MC3485
Symbol
VIC
-
-
-
-
20
40
100
200
-
20
60
100
400
-
-
-250
-500
-
-
-250
-1000
-
-
-1.5,.
-
-1.5
3.6
3.6
-
VOH(D)
VOH(DS)
3.11
3.9
Low-Level Driver Output Voltage
(VCC = 5.5 V, VIL = 0.6 V, 10L = -240 ~A)
(VCC = 5.95 V, VIL = 0.8 V, 10L = -1.0 mAl
VOL(D)
VOL(DS)
-
-
-
'f
.
+
.'
... CJA,5.f
l
V
3)~
3;8. -
OJ6
,N
.~
V
0,:
,,,+,
:1.
I$~~
.,
,
,;,.i i>,' r1 <;'.5.0
lOS (D)
10S(DS) k,r£~~'; '.
J
Driver
Short
CircuH
Operation
MOTOROLA ANALOG IC DEVICE DATA
7-85
®
MOTOROLA
MC3488A
Dual EIA-423/EIA-232D
Line Driver
The MC3488A dual is single-ended line driver has been designed to
satisfy the requirements of EIA standards EIA-423 and EIA-232D, as well
as CCITT X.26, X.28 and Federal Standard FIDS1030. It is suitable for use
where signal wave shaping is desired and the output load resistance is
greaterthan 450 ohms. Output slew rates are adjustable from 1.0 j.!s to
100 j.!S by a single external resistor. Output level and slew rate are
insensitive to power supply variations. Input undershoot diodes limit
transients below ground and output current limiting is provided in both output
states.
The MC3488A has a standard 1.5 V input logic threshold for TTL or
NMOS compatibility..
DUAL
EIA-423/EIA-232D
DRIVER
SEMICONDUCTOR
TECHNICAL DATA
• PNP Buffered Inputs to Minimize Input Loading
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
• Short Circuit Protection
• Adjustable Slew Rate Limiting
• MC3488A Equivalent to 9636A
II
• Output Levels and Slew Rates are Insensitive to Power
Supply Voltages
DSUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
• No External Blocking Diode Required for VEE Supply
• Second Source j.!A9636A
PIN CONNECTIONS
Wave
Shape
Input A
InputB
Gnd
ORDERING INFORMATION
Device
MC3488AP1
Operating
Temperature Range
TA=Oto+70°C
MC3488AD
Package
Plastic DIP
S0-8
Simplified Application
Wave Shape
Control
-4:-
MC3488A Driver
TIL Logic
7-86
:
R&-423 Interface
MC3486
Three-State Receiver
i ~
MOTOROLA ANALOG IC DEVICE DATA
MC3488A
MAXIMUM RATINGS (Note 1)
Rating
Power Supply Voltages
Output Current
Source
Sink
Symbol
Value
Unit
VCC
VEE
+15
-15
V
10+
10-
+ 150
-150
mA
Operating Ambient Temperature
TA
Oto+70
Junction Temperature Range
TJ
150
Storage Temperature Range
Tstg
-65to+ 150
°c
°c
°c
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltages
Operating Temperature Range
Wave Shaping Resistor
Symbol
Min
Typ
Max
Unit
VCC
VEE
10.8
-13.2
12
-12
13.2
-10.8
V
TA
0
25
70
°c
RWS
10
-
1000
kQ
TARGET ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply over recommended operating conditions)
Symbol
Min
Typ
Max
Unit
Input Voltage - Low Logic State
Characteristic
VIL
-
-
0.8
V
Input Voltage - High Logic State
VIH
2.0
-
-
V
IlL
-80
-
-
IlA
IIHI
IIH2
-
-
-
10
100
Input Clamp Diode Voltage
(11K = -15 rnA)
VIK
-1.5
-
-
Output Voltage (RL = 00)
(RL= 3.0 kQ)
(RL=450Q)
Low Logic State
EIA-423
EIA-232D
EIA-423
VOL
-6.0
-6.0
-6.0
-
-5.0
-5.0
-4.0
Output Voltage (RL = 00)
(RL.= 3.0 kQ)
(RL=450Q)
High Logic State
EIA-423
EIA-232D
EIA-423
VOH
5.0
5.0
4.0
-
6.0
6.0
6.0
RO
-
25
50
IOSH
IOSL
-150
+15
-
-15
+ 150
Output Leakage Current (Note 3)
(VCC =VEE = OV, -6.0V '" Vo '" 6.0 V)
lox
-100
-
100
I!A
Power Supply Currents
(RW = 100 kQ, RL = 00, VIL '" Vin '" VIH)
ICC
lEE
-
-
+18
rnA
-18
Input Current - Low Logic State
(VIL= 0.4 V)
Input Current - High Logic State
(VIH = 2.4 V)
(VIH=5.5 V)
Output Resistance
(RL'" 450Q)
Output Short-Circuit Current (Note 2)
(Vin = Vout = 0 V)
(Vin = VIH(Min), Vout = 0 V)
IlA
V
V
V
Q
mA
-
NOTES: 1. Devices should not be operated at these values. The "Electrical Characteristics" provide conditions for actual device operation.
2. One output shorted at a time.
3. No VEE diode required.
MOTOROLA ANALOG IC DEVICE DATA
7-87
II
MC3488A
TRANSITION llMES (Unless otherwise noted, eL = 30 pF, f = 1.0 kHz, Vee = - VEE = 12.0 V ± 10%, TA = 25°e, RL = 450 O.
Transition times measured 10% to 90% and 90% to 10%)
Characteristic
Symbol
Transition lime, Low-to-High State Output
(RW= 101<.0)
(RW = 100 1<.0)
(RW = 500 1<.0)
(RW = 10001<.0)
lTLH
Transition Time, High-to-Low State Output
(RW= 10kO)
(RW = 100 1<.0)
(RW = 500 1<.0)
(RW = 1000 kO)
lTHL
Min
Typ
Max
0.8
8.0
40
80
-
1.4
14
70
140
0.8
8.0
40
80
-
1.4
14
70
140
Unit
IlS
-
IlS
-
Figure 1. Test Circuit and Waveforms
for Transition Times
To
Scope
(Input)
To
Scope
(Output)
VCC
II
Pulse
Generator
CL
(Includes
Probe and Jig
Capacitance)
RWS
c
ote: Input Rise
and Fall Times
(10% to 90%) .; 10 ns
3.0V - - - - / - - , . -_ _ _ _ _ _ _ _ _ _-(
Input
OV----'
VOH ---~90~%"\o
OV-----~l.----------------r-1
Oulput
VOL--------~--~~------------------~
trHL
7-88
-I
trLH
MOTOROLA ANALOG IC DEVICE DATA
MC3488A
Figure 2. Output Transition Times versus
Wave Shape Resistor Value
Figure 3. Input/Output Characteristics
versus Temperature
1000
6.0
~
;:
4.0
~
~1oo
2.0
'-'
~
ill0:
~
!3
g:
CL-30pF
0
I
1.
is - 2.0 r-- c- VCC= 12V
UJ
~
0°
TA = 25°
70°
UJ
10
en
}-4.0
UJ
:::e
so
r-- "'VEE=-12V
r-- -RwS=1ookO
r-- '-RL=4500
-6.0
1.0
0.1
1.0
10
100
TRANSITION TIMES, trLH/trHL (~)
I
I
1000
1.0
Yin, INPUT VOLTAGE (V)
2.0
Figure 4. Output Current versus Output Voltage
Power-On
50
I
40
1
30
~
10
0:
0:
a
I,
0.08
1
'=
Yin = VIH(Min)
20
I
1/
0
TA=125oC I
VCC= 12 V
VEE=-12V
RWS=100kQ
t-
~ -10
is
Power-Off
0.10
I
I
-,
-20
I
-5-30
I
..2
-40
0.04
0.02
~
0
VCC = VEE = Yin -0 V
TA = 25°C
(No diode required
at VEE Pin.)
~ -0.02
0.
-0.04
J-0.06
I
-SO
- 10 - 8.0 - 6.0 - 4.0 - 2.0
0
2.0
4.0
Vout, OUTPUT" VOLTAGE (V)
~
ff
:::J
I
Yin = 0 V
0.06
:::J
I
I
1
- 0.08
-0.10
6.0
8.0
10
10 - 8.0 - 6.0 - 4.0 - 2.0
0
2.0 4.0
Vout, OUTPUT VOLTAGE (V)
Figure 5. Supply Current versus Temperature
12.0
10.0
8.0
6.0
~ 4.0
~
2.0
0
~ -2.0
!t - 4.0
I,
I
I
,I
1
Figure 6. Rise/Fall Time versus
I
I ..1
VCC= 12V
VEE = -12V
RWS = 100 kO, RL = 00
a
I
UJ
F
-'
-'
20
/'
en
a:
-'
:I:
TA=25°C
.
::-
lEE
30
40
SO
60
70
80
TA, AMBIENT TEMPERATURE (0C)
MOTOROLA ANALOG Ie DEVICE DATA
Rws
P'
iiI 10
~
~
:I:
~
J
10
,
I I
TA = O°C, 70°C
if
Vin-VIH
o
10
,
VCC=12V
r--- VEP 12V
r--- CL=3OpF
::;:
Vin=OV
ii -8.0
--10.0
-12.0
~
'[
ICC
I
I
~ -6.0
8.0
100
Yin = 0 V, Yin = VIH
1
6.0
90
100
".
1~
10k.
100 k
RWS, WAVE SHAPING RESISTANCE (0)
1M
7-89
®
.ItIIOTOROLA
MC34055
IEEE 802.3 10BASE-T
Transceiver
II
The Motorola 10BASE-T transceiver, designed to comply with the ISO
8802-3 [IEEE 802.3] 10BASE-T specification, will support a Medium
Dependent Interface (MDI) in an embedded Media Attachment Unit (MAU)'.
The interface supporting the Data Terminal Equipment (DTE) is TTL, CMOS,
and raised ECl compatible, and the interface to the Twisted Pair (TP) media
is supported through standard 1OBASE-T filters and transformers.
Differential data intended for the TP media is provided a 50 ns pre-emphasis
and data at the TP receiver is screened by Smart Squelch circuitry for
specific threshold, pulse Width, and sequence requirements.
Other features of the MC34055 include: Collision and Jabber detection
status outputs, select mode pins for forcing loop Back and Full-Duplex
operation, a Signal Quality Error pin for testing the collision detect circuitry
without affecting the TP output, and a lED driver for Link Integrity status. An
on-chip oscillator, capable of receiving a clock input or operating under
crystal control, is also provided for internal timing and driving a buffered
clock output.
The MC34055 is manufactured on a BiCMOS process and is packaged in
a 24 pin SOIC.
1OBASE-T TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(S0-24L)
• BiCMOS Technology for low Power Operation
• Standard 5.0 V, ± 5% Voltage Supply
• Smart Squelch Enforcement of Threshold, Pulse Width, and Sequence
Requirements
• Driver Pre-Emphasis for Output Data
• TTL, CMOS and Raised ECl Compatible
• Interfaces to TP Media with Standard 10BASE-T Filters and
Transformers
PIN CONNECTIONS
• lED Capable Status Outputs for COllision, Jabber Detection, and Link
Integrity
• Directly Driven or Crystal Controlled Clock Oscillator
ClkOut
0
• Selectable Full-Duplex Operation
TXDataB
• Signal Quality Error Test Pin
• Selectable loop Back
SQEENL
TXENH
TX+
Dig.Gnd
TX. PwrGnd
VCc{DigiAna)
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply VoHage
PwrVCC
FULLDL
Symbol
Value
Unit
VCC
-0.5 to 7.0
Vdc
RX DataB
RX+
RXENH
RX-
- 5.25 to 5.25
Vdc
-.0.5 to 5.5
Vdc
Voltage Applied to Logic Outputs and
Output Status Pins
-0.5t07.0
Vdc
ViD
CTLH
LoopL
JABBH
LNKFLH
Ambient Operating Temperature Range
TA
Ot070
°c
Junction .Temperature
TJ
-65\0150
°C
NOTE: Devices should not be operated at these limits. The "Recommended Operating
Conditions' table provides for actual device operation.
7-90
Ana. Gnd
RXDataA
Vollllge Applied to Logic and Mode/Test
Select Inputs
Differential Voltage at RX+/RX-
Clk+
Clk-
TX Data A
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC34055DW
TA = 0° to +70°C
S0-24L
MOTOROLA ANALOG IC DEVICE.DATA
MC34055
Simplified Block Diagram
PwrVcc
vee (Dig/Anal
r----------------------O----O------,
Balun
lli
Fillef
I
I
DalaOuI
Vee Hi~""''V¢~---I nveMos
SOEENL
I
L---o--o---o------Ana.
Pwr
Dig.
elk +
Goo
Gnd
*The sale and use of this product is licensed
under technology covered by one or more
Digital Equipment Corporation patents.
Goo
lOMHz
This device contains 9,875 active transistors.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Voltage Applied to logic Inputs and Status Pins
Differential Input VoHage
Operating Ambient Temperature
Symbol
Min
Typ
Max
Unit
VCC
4.75
5.0
5.25
Vdc
-
0
-
5.25
Vdc
-
0.59
-
2.8
Vpp
TA
0
-
70
°C
Unit
NOTE: AIiUmits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (oOe $ TA $ 70°C, Vce = 5.0 V, unless otherwise noted.)
Characteristic
Supply Current (4.75 V
$
VCC $ 5.25 V)
Reset Circuit Threshold
Symbol
Min
Typ
Max
ICC
-
60
180
rnA
-
4.0
-
4.4
Vdc
TWISTED PAIR TRANSMITTER
Output Differential Voltage
(See load CircuHs: Differential load Circuit)
Output Differential Voltage with Pre-Emphasis
Output Differential Voltage
Common Mode Driver Impedance
Transmitter Differential Output Impedance
Vpp
Vo
2.2
1.56
2.53
1.72
2.8
1.98
ZoCM
6.0
8.5
14
Zoo
8.0
15.5
29
VIH
0.984 VCC 0.984 VCC 0.984 VCC 0.750 VCC 0.750 VCC 0.750 VCC -
n
n
TX DATA A
Input High Voltage (IIH = + 20 I1A)
Input Low Voltage (Ill = -150!1A)
TXDATAB
Input Voltage (See load Circuits: ECl load Circuit)
High: @O°C
@25°C
@70°C
@O°C
low:
@25°C
@70o e
MOTOROLA ANALOG IC DEVICE DATA
Vdc
Vil
0.923
0.877
0.825
0.568
0.550
0.531
0.984 VCC 0.984 VCC 0.984 VCC 0.750 VCC 0.750 VCC 0.750 VCC -
0.763
0.727
0.644
0.361
0.350
0.324
7-91
•
IYIC34055
ELECTRICAL CHARACTERISTICS (O°C:O; TA:O; 70°C, VCC = 5.0 V, unless otherwise noted.)
I
I
Characteristic
Symbol
I
Min
I
Typ
Max
-
-
Unit
TXENH
Input High Voltage (IIH = 200 1lA)
Input Low Voltage (IlL = - 20 1lA)
RX DATA AlRX EN HlJABB HlCTL H
Output Vo~age (See Load Circuits: CMOS Load Circuit)
High (IOH =-12 rnA)
Low (IOL = + 16 rnA)
Vdc
VOH
VOL
3.7
VOH
0.984 VCC 0.984 VCC 0.984 VCC 0.750 VCC 0.750 VCC 0.750 VCC -
-
-
0.5
RX DATA B
Output Voltage (See Load Circuits: ECL Load Circuit)
High: @O°C
@25°C
@70°C
Low:
@O°C
@25°C
@70°C
Vdc
VOL
0.923
0.877
0.825
0.568
0.550
0.531
0.984 VCC - 0.763
0.984 VCC - 0.727
0.984 VCC - 0.644
0.750 VCC - 0.361
0.750 VCC - 0.350
0.750 VCC -·0.324
SIGNAL QUALITY ERROR TEST ENABLE CONTROL (SQE EN L)
Test Control Voltage
Test Disabled (Input High Voltage)(IIH = + 20 IlA Max.)
Test Enabled (Input Low Voltage)(- 50 IlA < IlL < -150 ~A)
Vdc
-
VIH
VIL
2.0
0
-
5.0
0.8
VIH
VIL
2.0
0
-
5.0
0.8
VIH
VIL
2.0
0
VOH
VOL
-
FULL DUPLEX MODE SELECT (FULLD L)
II
Mode Select Control Vonage
Normal Operation (Input High)(llH = + 20 1lA)
Full Duplex (Input Low)(- 50 IlA < IIH < -150 1lA)
Vdc
LOOPBACK TEST MODE FUNCTION (LOOP L)
Test Control Voltage
Test Disabled (Input High)(llH = + 20 1lA)
Test Enabled (Input Low)(IIL = - 200 1lA)
Vdc
-
5.0
0.8
-
LINK FAIL STATUS (LiNKFL H)
Status Output Vonage (See Load Circuits: CMOS Load Circuit)
Maximum VoHage for Output Low Condition (IOL = 20 rnA)
Output Low Sink Current
-
-
0.5
20
Vdc
rnA
5.0
0.8
Vdc
CLOCK OSCILLATOR
Clk+ Input Logic Threshold
High Level Input Voltage (IIH ~ +100 IlA Max.)
Logic Low Input Voltage (IlL = -100 ~A Max.)
VIH
VIL
Clk Out Output Voltage (See Load Circuits: CMOS Load Circuit)
Logic High (IOH = -12 rnA)
Logic Low (lout = + 161lA)
-
2.0
-
-
IlA
Vdc
VOH
VOL
3.7
-
3.9
0.25
-
0.5
Output Load Circuits
39(1%)
TX330!}
15pF
ECL load Circuit
7-92
20pF
6.0k!}
TIlJCMOS Load Circuit
I
I
I
TXt I
100!}
39(1%)
Differential Load Circuit
MOTOROLA ANALOG IC DEVICE DATA
MC34055
TIMING CHARACTERISTICS (O°C ~ TA ~ 70°C)
I
Characteristic
Symbol
Min
Typ
Max
Unit
TRANSMIT START TIMING
TX EN H to TX+ITX- Enable Time
trXEN
-
-
75
ns
TX Data AlB to TX+ITX- Enable Time
tFDXD
-
-
75
ns
Steady State Propagation Delay of TX Data AlB to TX+/TX- Output
trxSS
-
-
75
ns
Pre-Emphasis Pulse Widlh
IpRCM
45
-
55
ns
Transmitter Caused Edge Skew Between TX+ and TX-
ISkewT
-
-
2.0
ns
-
4.0
ns
tJitterT
-
Sleady--81ate Delay between Ihe TX Dala AlB Input to the RX Data
AlB Outpuls for Normal Operation
trXRX
-
-
50
ns
TX EN H Assert to RX EN H Assert Under Normal Operation
tDREL
-
-
50
ns
Transmitter Added Edge Jitter 10 TX+ITX- from TX Dala AlB
TRANSMIT STOP TIMING
Delay between TX EN H Low and TX+ITX- High
trXDH
-
-
75
ns
TX EN H AsserVDe-assert Delay from TX EN H 10 RX EN H
AsserVDe-assert
tXTRE
-
-
400
ns
End of Packet Hold Time from Last TX Data AlB Edge or
TX EN H De-assert
trDDC
250
-
-
ns
Delay from Loop L Deassertion to RX EN H Driven from
TX EN H Status
tLTRA
-
-
30
ns
TX EN H AsserVDe-assert to RX EN H, AsserVDe-assert when in
Loop-Back Mode and Receiver Inactive
tLTRX
-
-
50
ns
Sleady-8tate TX Dala AlB 10 RX Data AlB when in Loop-Back Mode
tLTRD
-
-
50
ns
Receiver-Added Edge Skew 10 RX Dala AlB Signal
ISkewR
-
-
1.5
ns
Receiver-Added Edge Jitter to RX Dala AlB Signal
LINK BEAT PULSES
Output Link Test Pulse Width
Minimum Link Beal Pulse Duration on RX+/RXLOOP BACK MODE TIMING
SMART SQUELCH
Interval Unit Squelch Deactivation
RECEIVE START TIMING
!Jitter R
-
-
1.5
ns
Start-Up Delay from RX+/RX- to RX Data AlB
tRXNE
-
-
50
ns
Delay from RX EN H Assertion Until RX Data AlB Valid
tRARE
-10
-
+10
ns
Steady--81ate Propagalion Delay from RX+/RX- Data AlB
IRXSS
-
-
50
ns
RECEIVE SHUTDOWN TIMING
Last received Data Edge until the RX EN H Output forces low
MOTOROLA ANALOG IC DEVICE DATA
7-93
•
MC34055
Figure 1. Start Up and Steady State Transmit Timing
TXENH
-A
BHPattem
TX Data AlB
RXENH
RXDataAIB
TX+fTX-
1
1
o
I
~~ trxRX -:
~
~
1
1
1
1
'\
LJ
1
1
1
1
1
\
/
1
1
1
1
I
:
\
I"
..
1 trxSS 1
1"tPRCM.1
trxEN
I"
II
1
1
lJlTTERT
--'·1
Figure 2. Driver Shutdown TIming
LJ
TXDataAIB~
I
Bit Pattern
1
I
585mV
0
TIMX-
~
TXENH
-
~
~~----------------I"
"I
\'----txrRE
1
RXENH
Figure 3. Link Pulse TIming
tLOCY_A
-_-_H.I"
"I
RX+_/R_X-_ _ _ _
H
-_-_'! ---[..-
TX+_fTX_-_ _ _ _
1
585mV
585mV
1
MOTOROLA ANALOG IC DEVICE DATA
MC34055
Figure 4. Loop Back Timing
TX EN H - - - - - - - - - - - ' ,
I I
I
I '---ir----"""t-=:
Bit Pattern
TX Data AlB
RXENH - - - - - - - - - - - \
I~
tlTRX ~J
1
!
I
1
I~----~
loopl
I
tlTRD
I
RXDamAIB
I
0
-------t-cr-RA~:-----~~r----~'\~----~!'
-------tj
II
Figure 5. Receive Startup Timing
o
o
RX+/RX-
I
I
I
I
IsQ
RXEN H
•
I~tRARE
"I
1
1
1
/
1
I
I..
tRXNE
·1
+
RXDataAlB------------------------tSKEWR
I
I
I
I·
tRXSS
"I
~RR
Figure 6. Receive Shutdown Timing
l~
tRXDE
"I
RXENH---------------------~\~_ _ _ _ _ _ _ __
MOTOROLA ANALOG IC DEVICE DATA
7-95
MC34055
PIN FUNCTION DESCRIPTION
II
7-96
Pin
Symbol
1
ClkOut
2
TX Data A
CMOS transmit input pin. Data input at this pin is output to the TP media. The input will source
less than 175!lA and sink less than 20 !lA.
3
TXData B
Raised ECL transmit input pin. Data input at this pin is output to the TP media. The input can
source 40 !lA for a high level input or 70 !lA for a low level input.
4
TXENH
5
Dig. Gnd
6
VCc(DiglAna)
Description
TTUCMOS buffered 10 MHz clock output. This pin will source 400 IlA and sink 16 mAo
TTUCMOS transmit enable pin. Transmit is enabled when asserted high. The input will source
less than 175!lA and sink less than 20 !lA.
Digital ground
Digital and analog VCC. With the current consumed at this pin and Pin 18, the device will
consume less than 180 mA at 5.0 Vdc.
7
Ana. Gnd
Analog ground
8
RXDataA
TTUCMOS received data output pin. Data from the TP media is output at this pin. The output
will source 12 mA and sink 16 mAo
g
RX DataB
10
RXENH
11
Loop L
TTUCMOS Loopback test select. Asserting this pin causes the transmH data to be looped to
the receive circuit while the TP transmit driver sends a link pulse. The input will source less
than 175 IlA and sink less than 20 IlA.
12
LNKFLH
This pin is driven high to indicate a link fail state. When low, the pin will sink 20 rnA to light an
LED. An usquelched condition due to valid data on the receive circuH will cause the pin to
transition high and low in 100 ms intervals.
13
JABBH
TTUCMOS Jabber status pin. This pin is asserted when a Jabber condition is detected and will
source 12 rnA and sink 16 rnA.
14
CTLH
Raised ECL received data output pin. Data from the TP media is output at this pin.
TTUCMOS received data output enable pin. This pin is asserted after the Smart Squelch
circuitry determines that there is valid data at the TP input pins and also when intemal
loop-back is occurring. The output will source 12 mA and sink 16 rnA. The receive data outputs
are forced high when this pin is low.
TTUCMOS status pin. This pin pulled high when Jabber or Collision condHions are detected.
Also high for a time interval when a Signal Quality Error test is being performed. The pin will
source 12 rnA and sink 16 rnA.
15
RX-
The inverting terminal of the TP differential receiver.
16
RX+
The noninverting terminal of the TP differential receiver.
17
FULLDL
TTUCMOS duplex mode select. When low, this pin forces the device to operate in full-duplex
mode. The input will source less than 175!lA and sink less than 20 !lA.
18
PwrVcc
Power supply pin. With the current consumed at this pin and. Pin 6, the device will consume
less than 180 mA at 5.0 Vdc.
19
PwrGnd
Power ground pin.
20
TX-
The inverting terminal of the TP differential driver.
21
TX+
The noninverting terminal of the TP differential driver.
22
SQE EN L
23
Clk-
TTUCMOS clock oscillator pin. See Pin 24.
24
Clk+
TTUCMOS clock oscillator pin. This pin is used with Pin 23 ~ the internal oscillator is to be free
run with a crystal. The oscillator can also be directly driven with a TTUCMOS clock signal at
this pin. The oscillator frequency should be 10 MHz with a duty cycle of 50 ± 20%.
TTUCMOS Signal Quality Error test enable pin. Pulling this pin low allows test of the collision
detect circuitry without affecting the twisted pair channel. The input will source less than 175 IlA
and sink less than 20 !lA.
MOTOROLA ANALOG IC DEVICE DATA
MC34055
FUNCTIONAL DESCRIPTION
Introduction
The Motorola 1OBASE-T transceiver, designed to comply
with the ISO 8802-3[IEEE 802.3) 10BASE-T specification,
will support one Medium Dependent Interface (MOl) through
standard 10BASE-T filters and transformers. Although the
device is capable of being used in embedded or external
Medium Attachment Units (MAU), it was primarily designed
for use in repeater or hub applications. For this reason a
digital interface is provided rather than an AUI interface. This
interface is TTL, CMOS, and raised ECl compatible and
allows for easy connection in hub applications.
Other features of the MC34055 include: select mode pins
of forcing loop-8ack and Full-Duplex operation; a Signal
Quality Error pin for testing the collision detect circuitry
without affecting the twisted pair output; and lED drivers for
Link Integrity status; Collision detection; and Jabber
detection. An on chip oscillator, capable of receiving a clock
input or operating under crystal control, is also provided for
internal timing and driving a buffered clock output.
The inputs were not intended to be used simultaneously in a
single application and are internally logically combined. The
unused input should be disabled by connection to VCC.
When data transmission is intended, the MC34055
detects the first falling edge of the Manchester encoded
frame at the input being used, synchronizes the on chip
oscillator (Pins 23 and 24) and asserts the twisted pair driver
output to full differential amplitude within 25 ns if the driver
enable pin (TX EN H) is previously asserted. Also, since
twisted pair attenuates a 10 MHz signal more than a 5.0 MHz
signal the 10BASE-T standard requires that data applied to
the twisted pair receive pre-equalization. To fulfill this
requirement the MC34055 provides an additional 730 mV for
approximately 50 ns to output data. This is accomplished
over the single pair of differential driver pins. TX+ and TX-,
and effectively equalizes the power of all data components at
the receiver. Figure 7 A shows a 10 MHz waveform. Figure 7B
shows the effect of pre-emphasis on a 5.0 MHz waveform.
Manchester encoded data with the pattern shown in Figure
7A would represent a repeating pattern of zeros (000000... ).
Figure 7B would represent an alternating pattern of ones and
zeros (0101010 ... ).
Data Transmission
For data intended for the twisted pair, the MC34055 has
two data inputs, TX Data A and TX Data B. TX Data A is
CMOS compatible and TX Data B is raised ECl compatible.
Figure 7A. 10 MHz Waveform on Differential Outputs
0
BitPatlem
TX+
Pin 21
0
0
0
0
1-T
25
1.
I
-+ OV
I
-1
,
1__
-t
TXPin 20
I
---L
I
1.25V
OV
Figure 7B. 5.0 MHz Waveform on Differential Outputs
o
BitPatlem
TX+
Pin 21
I
OV
TXPin20 OV
MOTOROLA ANALOG IC DEVICE DATA
----1-_...1
-,
---- ..... I
7-97
MC34055
The figures show the voltage waveforms on the differential
driver output pins. To actually meet the 10BASE-T
specification requires bandpass filtering and a pulse
transformer.
The output voltage waveform specifications of the IEEE
802.3. standard require that voltages impressed on the
twisted pair meet .a voltage template. The MC34055 can
meet the voltage template for all the 1OBASE-T applications
initiated. In this event, the transmit differential driver will
remain active for the entire frame interval and the link pulse
will not affect more than one bit interval.
The MC34055 also has Jabber circuitry to detect and
disable the twisted pair driver in the event .that a serial
controller fails constantly transmitting. Should any data
source try to transmit longer than 20 ms minimum, the Jabber
function will disable the differential driver outputs, the
Figure 8. Differential Driver Media Interface Circuitry
RS
,----,
L ____ J
.
ZF
,----,
ZF
-1 r----A/I/Ir-;
TX- RS
rI
IL
Pulse
Transfonner
I-I ':
Twisted Pair
FIZo~
_ _ -1
Where: ZOO is the transmitters differential output impedance (-20 (1),
RS is a 1% series resistor,
ZF is the filters impedance, and Zo is the characteristic
impedance of the twisted pair (100 (1).
II
by choosing the appropriate low pass filter and external
components in the driver output circuitry. When the
differential transmit driver output pins are configured to drive
the bandpass filters and pulse transformer as shown in
Figure 8, the resultant waveform is capable of meeting the
voltage template.
Following the end-of-frame activity, an internal pull-up
resistor pulls TX Data AlB high and causes the differential
driver to maintain full differential output voltage for
approximately 250 ns. The differential driver interprets the
lack of transition activity as an end of frame and starts an idle
timer. Should another frame intended for the twisted pair
arrive before the idle timer expires(-250 ns), the idle timer
will be reset, if not, the transmit driver function will begin the
decay to idle process. During idle periods the differential
driver must force the media to a minimal differential voltage
unless a link beat is being produced. The transition to
minimal voltage is subject to performance requirements in
the IEEE specification and is met by the MC34055 when the
appropriate filters and transformers are used to interface to
the media.
The MC34055 differential driver generates link pulses
(beats) during idle periods. The link pulses produced are
singular positive (TX+ positive with respect to TX-) pulses
applied to the media at 16 ms intervals and last
approximately 100 ns. The link pulses allow the receiver at
the other end of the link to verify the validity of the segment.
There is the possibility, due to the two asynchronous
sources, that one of the two input pins (TX Data A or TX Data
B) will receive frame activity immediately after a link pulse is
7-98
collision presence detector and the internal loop back
function. Also, two status indicator pins, CTL Hand JABB H
are asserted. The MC34055 will remain in the jabber state
until the TX EN H pin is pulled low or the jabbering input
ceases to toggle for a minimum of 500 ms. The status
indicator pins, CTL Hand JABB H will also sink up to 20 rnA
and can therefore support external LEOs.
The driver also works with the receiver to provide
loop-back. Under normal operating conditions (Loop L= "1"),
the data applied to the TX Data AlB pins is looped back
internally to the RX Data AlB pins. This function is disabled
when there is a collision condition or FULLD L is low.
Data Reception
Data intended for the DTE proceeds from the twisted pair
to the isolation transformer and bandpass filters before
reaching the differential receiver terminals. Figure 9 shows
the configuration of the external media receive circuitry. Once
transitions at the receiver terminals (RX+ and RX-) are
detected, the on-chip oscillator is synchronized and the
received data is screened by smart squelch circuitry for
validity. This qualification requires incoming data to meet
amplitude and sequence requirements. If the data meets the
Smart Squelch requirements, the receiver enters the
unsquelch state and the data is forwarded to the RX Data AlB
output pins provided Loop L is not low. Two data outputs are
provided to increase design flexibility, RX Data A and RX
Data B. RX Data A is CMOSfTTL compatible and RX Data B
is raised ECL compatible.
MOTOROLA ANALOG.ICDEVICE DATA
MC34055
Figure 9. Differential Receiver Media Interface Circuitry
r----,
Pulse
Transformer
Twisted Pair
L ____ .J
!r -11- 1
ZF
L _ _ .J
ZF
)<::>c><:><- Zo I ~
I
I
RT
~r:---_-W-'v---'+-+-i
16 RX+
L _ _ _ _ .J
Where: RT is a terminating resistor (1000),
ZF is the filters impedance, and Zo is the
characteristic impedance of the twisted pair (100 0).
The MC34055 powers up in a squelched and "link OK"
state, after which minimum and maximum link test and
maximum link fail timers are started. If valid data or a link
pulse is received after the link test minimum timer but before
the link fail maximum timer times out, the timers are reset and
begin counting again. In the event of missing or incorrect link
pulses, the MC34055 enters the link fail state whereby the
LNKFL H status pin is asserted until valid data or link pulse
activity appears at the receiver terminals.
Powering up in the squelched state assures that the data
path to the data output pin (RX Data AlB) is disabled, and
prevents noise at the receiver terminals (RX+/RX-), from
being interpreted as valid input data. Once transitions appear
at the receiver terminals, the smart squelch circuitry checks
for the smart squelch requirements to unsquelch; an
alternating sequence (1010 ... or 0101...) of pulses with
amplitude of at least 525 mV. This requirement is met by the
preamble of an IEEE 802.3 frame with good signal to noise
ratio.
After a pulse is received and checked for proper polarity
and amplitude, the pulse width is checked for proper
duration. If the duration is to short or too long the smart
squelch Circuitry resets and begins to look again for a proper
sequence. By requiring the differential pulses to meet
amplitude and sequence requirements, it is unlikely that
pulses due to crosstalk from coresident twisted pairs are
capable of causing the receiver to unsquelch. If a positive
pulse is received first and the differential driver is not
transmitting, the receiver should un squelch after three
alternating pulses. If a negative pulse is received first, one
additional pulse is required before unsquelch. If the
differential driver is transmitting, three additional pulses are
required to unsquelch.
After meeting the smart squelch requirements, the
MC34055 will pull high the RX EN H pin and enable the path
to the receive data pin (RX D&ta AlB) provided the MC34055
is not in the loop back test mode (Loop L low). If the receiver
unsquelches, the receive enable pin remains high and the
data path to the receive data pin remains enabled until
transitions cease to exist at the receiver terminals. Valid data
reception is also indicated by high/low transitions of the
LNKFL H pin at 100 ms intervals. When transitions at the
differential terminals cease, marking the end of frame activity,
the receiver re-enters the squelch state, pulls Iowan the RX
EN H pin, and begins accepting valid link pulses until the start
of the next 802.3 frame.
If the MC34055 is requested to begin transmitting (TX EN
H is asserted), and the receiver unsquelches simultaneously,
there is a collision. Also, if the MC34055 driver enable pin is
previously asserted and the receiver detects valid transition
activity, the receiver Smart Squelch Circuitry verifies the
possibility of collision by requiring three extra transitions at
the differential receiver before the unsquelch condition is
reached. If un squelch occurs, a collision condition exists.
During all collision conditions the MC34055 asserts the CTL
H status pin for the duration of the condition and for a time
after the end of collision.
During a collision condition the receive and transmit paths
are still both enabled allowing transparency to the media.
Either the presence of simultaneous transmit and receive
activity or the condition of the CTL H status pin can be used
by the communications controller to acknowledge and react
to the collision. In applications where a 10 MHz collision
signal is required by an SIA, the combination of this status pin
and the clock oscillator output can be logically combined to
provide a 10 MHz output. If the DTE reacts to the collision
and ceases transmitting, the MC34055 will decay to idle until
a re-transmit is attempted.
Crystal Oscillator
The MC34055 has an on-chip clock oscillator used to
provide a reliable and accurate time reference to all the
internal timers. The oscillator can be run with a crystal or
driven at Pin 24 from an external clock source. Also provided
is a buffered clock output which is useful if the MC34055 is to
be used in a repeater or concentrator application.
Table 1. The crystal used in the oscillator is subject to the following specifications.
Crystal Operating Mode
Fundamental
Crystal Cut Type
AT
Crystal External Shunt CapaCitance
7.0pFMax
Crystal Resonant Mode
Series
Crystal Accuracy
±O.OI%
Crystal Temperature Variance
0.005% from 0° to 70°C
Crystal Series Resistance
25 0 Max, 17 0 Typical
Crystal Operating Temperature Range
0° to 70°C
MOTOROLA ANALOG IC DEVICE DATA
@
25°C
7-99
7
MC34055
LOOP L Test Mode
If the Loop L pin is low, the MC34055 is in a test mode
whereby the data at the input pin (TX Data AlB) is being
looped back internally to the receive data pin(RX Data AlB).
In this mode the data path from the differential receiver
terminals to the receive data output pins (RX Data AlB) is
disconnected whiJe the Smart Squelch functionality of the
differential receiver is still operational. This test mode allows
the DTE to test the MC34055 internal loop back circuitry
since the data is looped back to the receive circuitry as close
to the twisted pair interface as possible.
minimUm, the differential driver, the collision detect, and
internal loop back circuits are disabled. To announce the
presence of a jabber condition, both the CTL H and the JABB
H status output pins are assertf3d. In order to end the jabber
condition, the TX Data AlB input must stop toggling, or the TX
EN H pin must be pulled low for a minimum of 500 ms. The
status output pins have the ability to drive an external led and
were added to facilitize network .manageability. The jabber
status outputs will not assert during power up or power down.
Signal Quality Error Test
The MC34055 can be operated in a full-duplex mode if
required. When the FULLD L pin is pulled low the device will
enter the full duplex mode. This mode allows the transmitter
and driver to operate independently. Collision will not be
announced and the internal loop back operation is disabled.
The Signal Quality Error test, however, is still operational if
enabled.
The MC34055 also provides the ability to test the collision
detect circuitry without disabling either of the data paths. By
pulling the SQE EN L pin low, a collision test is provided to
the collision detect circuitry immediately following the last
edge of a transmitted· 802.3 frame. The test verifies the
operability of the collision detect circuitry, operability is
announced by the assertion of the CTL H pin for a period
following a valid data transmission.
Jabber Detection
II
The transmit circuitry of the MC34055 has the ability to
monitor and shut down the differential driver in the event of a
jabber condition. If transmission activity ever exceeds 20 ms
Full Duplex Mode
Status Pins
The MC34055 has three status indicator pins capable of
sourcing or sinking enough current to support an external
LED. Status pin levels ("1" or "0") report the condition of the
transcei)ler. Table 2 shows the combinations and
significance.
Table 2
Status Pin
JABBH
CTLH
"0"
"1"
"1"
X
X
X
Condition
LNKFLH
cond~ion
X
Collision
or Signal Quality Error test.
"1-
X
Jabber condition
X
"0"
Link Failure. Incorrect or nonexistent link pulses, or lack of data at the
receiver terminals.
X
"1"
Link "OK". Receiving link pulses.
X
"0101.. ..
Link "OK-. Receiving valid data.
Test Select Pins
The MC34055 has three operation mode test select pins,
Loop L, SQE EN Land FULLD L. The level of the pin
determines the mode of operation. Table 3 shows the levels
and corresponding conditions of the status pins.
Table 3
Pin
Status
LoopL
"1-
Normal operating mode. Loop back occurs when the transmitter initiates and the receiver is receiving
link pulses. The RX EN H pin follows the TX EN H pin and the transmit data appears on the RX Data
AlB output pin being used.
"0"
Loop back test mode. The transmit circuit is looped back internally as close to the differential receive
circuit as possible. In this mode the RX EN H pin follows the TX EN H pin and the transmH data appears on the RX Data AlB output pin being used. Any received data other than link pulses are ignored
and the receiver will not unsquelch or announce collision.
SQE EN L
FULLDL
7-100
Condition
"0"
Normal operating mode. Concurrent transmit and receive activity results in a collision condition.
"1"
Test enabled. An intemal test is run on the collision circuitry and the CTL H pin is asserted for a time
window following the last positive packet edge. Data transmission and reception is undisturbed.
"1"
Normal operating mode. Internalloop--back is operable and collision is announced.
"0-
Internal loop-back is disabled and collision will not be announced. Signal Quality Error test is
still operable.
MOTOROLA ANALOG IC.DEVICE.DATA
MC34055
APPLICATIONS INFORMATION
The MC34055 implements the physical layer of a
10BASE-T application of IEEE 802.3. It provides the
physical connection to the media (twisted pair) and the
services required by the MAC sublayer of the Data Link
Layer. Two interfaces are defined in the IEEE 802.3
specification of the physical layer; one is the MOl providing
connection to the twisted pair; and the other is the AUI
providing connection to the encoder/decoder function of the
Data Link Layer. While the MC34055 provides the connection
to the twisted pair, a CMOS and raised ECL interface is
provided instead of an AU/.
The MC34055 implements the twisted pair interface of the
physical layer in a 802.3 10BASE-T application but circuitry
must be added if an AUI is desired, (see Figure 10 for
suggested schematic). For example, an external MAU
application requires the AUI and a twisted pair interface. A
chip capable of realizing the AUI interface is the Texas
Instruments SN75ALS085. This Ie has an AUI interface and
another interface which is compatible with the MC34055. The
differential input of the 75ALS085 can be used for the
TX+ITX- terminals of the AU/. The differential drivers of the
75ASL085 can be used as the RX+/RX- and the
COL+/COL- terminals of the AU/. The other interface of the
75ALS085 then will interface to the MC34055 by three paths
MOTOROLA ANALOG IC DEVICE DATA
shown in the application suggestion. The application
accounts for all the inputs/outputs of an external MAU.
Embedded applications do not require a full AUI and a
MC10116 can be used to interface between the raised ECL
interfaces of the MC34055 and the AUI of existing
encoder/decoder chips. The MC10116 is a MECL 10k Triple
Line Receiver with typical propagation delay and rise and fall
times (20% to 80%) of 2.0 ns. Figure 11 shows the use of the
MC10116 with the MC34055 and the AMD 7992 SIA.
In a multi-port repeater, or hub, a port is required for each
DTE connected to the IEEE 802.3 network. This port consists
of two connections, one for the TX+ITX- pair and another for
the RX+/RX- pair. The repeater unit then multiplexes these
lines so that all of the stations are capable of transmitting to
or receiving from all the other stations on the network. This
establishes the need for a transceiver without an AUI
interface. If an AUI is present with each 10BASE-T
transceiver, chip count is increased because there is a
requirement to convert from balanced to unbalanced lines
before multiplexing.
An application suggestion for the use of the MC34055
used in a multipart repeater is shown in Figure 6. Here the
receive and transmit lines for the 10BASE-T transceivers are
multiplexed by the hub hardware.
7-101
II
!I
Figure 10. External MAU Application
0
N.
+5.0
~
HII
IIH
HII
0.1
IV
Twisted Pair
cf
C'l
'il
""
.e.
TX+
TX Data B
["ill:
.~
RX+
AX DataB
AX-
~II
4.7 k
+5.0
IAXENI
b-1
AX Data A
4.7k
loop2
RXOI
4.7k
TXENH
cf
C'l
loopl
TX Data A
TX-
+5.0
cf
C'l
4.7k
cf
C'l
~
::>
~Q
+5.0
~
9
Balun
H
IV
AXil
+5.0
RX
11[==
RXI1
39.3
TX 11
AUIChlp
75ALS085
T 1
IO.
-=-
NC
TXOI
AXENHI
ITXENI
CTLHI
I TX EN2
TXOI
11[==
TX
lNKFlH
i:
0
a
+5.0
loopl
:tI
0
r-
:I>
:I>
Z
:I>
Full 0
'I f--o
SQE EN l
4.7k
r0
C)
JABBH
r-~
NC
TX021
180
TX02
TXI2
270
ClK
S!~~ OUT
+5.0
Ci)l>:tl
Ci)Ci)Ci)
(;
is.
cm
<
::>
Q.
::>
Q.
1
820
n~xm
Ci) Ci)
Ci)
Ci)
~~g~
is. is. is. is.
~
-=-
(;
m
~I
20
I I
20
NC
~II[==
COL
l,.
s::
0
Co)
a
en
en
Figure 11. Internal MAU Application
~
+5.0
~
~
~
~
8o
cm
::s
Twisted Pair
0<
0
g
Balun
om
~
.e
"
TX+
C
~
~
TClK
8 TX Data A
TX+
TX Data B ~ +5.0
4.7 k
TXENH
TX-
:Joi
TX-
s
I
A
r:"
TENA
MC34055
RX Data B
RX+
RX+
RClK
RX-
RX-
L
A
N
c
E
RXDataA~1
NC
RXENHI---
COll+
RDATA
COllRENA
+5.0
CTlH
1-1- - - - - - - ,
AM7992
JABBH
II~
NC
AM7990
ClSN
ClK
OUT
1
!
a
-
-
---------------
i:
n
Co)
0l:Io
0
en
en
..
...~
Figure 12. 10BASE-T Connecentrator Application
2
Balun
TX ENBO
RXRX+
iii:
I..
TX Data Bo
0
m
TX-
RXENBo
RX Data B 0
TX+
0
Hub
Hardware
0
Other
MC34055
-«
0
FIIC=cm
0
3:
l
(')
Co)
~
0
UI
UI
0
a~I
:0
0
'--
0
Balun
Jfffi1L,,-,
r
~
~
RX+
RX
;;:
r
0
0
8enen
C)
(')
TXEN B7
C
m
<
(')
m
TX-
TX DataB7
139.3
TX+
C
~I
gll[==
RX DataB7
Z
)Ii
TX
RX EN B7
I RX-
~
gll[==
'----'
-=-
>
AUI
®
MOTOROLA
MC34058
MC34059
Hex EIA-485 Transceiver
with Three-State Outputs
HEX EIA-485 TRANSCEIVER
with THREE-STATE OUTPUTS
The Motorola MC34058/9 Hex Transceiver is composed of six
driverlreceiver combinations designed to comply with the EIA-485 standard.
Features include three-state outputs, thermal shutdown for each driver, and
current limiting in both directions. This device also complies with EIA-422
and CCITT Recommendations V.11 and X.27.
The devices are optimized for balanced multipoint bus transmission at
rates to 20 MBPS (MC34059). The driver outputs/receiver inputs feature a
wide common mode voltage range, allowing for their use in noisy
environments. The current limit and thermal shutdown features protect the
devices from line fault conditions.
The MC34058/9 is available in a space saving 7.0 mm 48 lead surface
mount quad package designed for optimal heat dissipation.
SEMICONDUCTOR
TECHNICAL DATA
48
• Meets EIA-485 Standard for Party Line Operation
• Meets EIA-422A and CCITT Recommendations V.11 and X.27
a
FTASUFF'X
PLASTIC PACKAGE
CASE 932
(ThinQFP)
• Operating Ambient Temperature: O°C to +70°C
• Common Mode Driver Output/Receiver Input Range: -7.0 to +12 V
,. Positive and Negative Current Limiting
• Transmission Rates to 14 MBPS (MC34058) and 20 MBPS (MC34059)
• Driver Thermal Shutdown at 150°C Junction Temperature
ORDERING INFORMATION
• Thermal Shutdown Active Low Output
Device
• Single +5.0 V Supply, ±100/0
• Low Supply Current
MC34058FTA
• Compact 7.0 mm 48 Lead TQFP Plastic Package
MC34059FTA
Operating
Temperature Range
Package
TA = 0' to +70'C
TQFP-48
Representative Block Diagram
,----------------------1
I i-------i/il
,-----'---1-TTUCMOS Data DR --i--+--_<1T +
Direction {RE
Control DE --;--1---+-::1
TSD I
I
S~~~:~
f- I
Thermal
Shutdown
-L _ _ _ _ _ ...r-
OB} ToCable
~-T------------_+---OA
-L.-------i2l
-L.-------#3l
I
--r-
L
(Sameas#1)
I
:::::r=
_______ =l-
-C..-------#5l
±
TTUCMOS Data- RO
Direction {RE
Control DE
TTUCMOS Data_ 01
i
(Same as #1)
±
L _______ =T-
I
I
--r(Sameas#1)
=r=
_______-::::t-
L
.-C.-------1I4l
I
-i-
(Same as #1)
I
=r=
~
L _______-+~
i-:JJ-~t
~
JI
IL ______________________
_I
L
OB} ToCable
OA
This device contains 1,399 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
7-105
MC34058 MC34059
MA"IMUM RATINGS
Rating
Power Supply Voltage
Symbol
Value
Unit
Vdc
VCC
-0.5,7.0
Input Voltage (Driver Data, Enables)
Yin
7.0
Vdc
Applied Driver Output Voltage When in Three-State
Condition (VCC = 5.0 V)
Vz
-10,14
Vdc
Applied Driver Output Voltage When VCC = 0 V
Vx
±14
Vdc
Output Current
10
Self limiting
-
Tstg
-65,150
DC
Storage Temperature
NOTE: Devices should not be operated at these limits. The "Recommended Operating Condttions'
provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS (All limits are not necessarily functional concurrently.)
Characteristic
Power Supply Voltage
II
Symbol
Min
Typ
VCC
4.5
5.0
Input Voltage (All Inputs Except Receiver Inputs)
Yin
0
Driver Output Voltage in Three-State Condition,
Receiver Inputs, or When VCC = 0 V
VCM
-7.0
-
Driver Output Current (Normal Data Transmission)
10
-60
Operating Ambient Temperature
TA
0
ELECTRICAL CHARACTERISTICS (TA = 25 DC, Vec = 5.0 V ± 10%)
I
Characteristic
I
Max
-
Symbol
Min
Vo
IVODll
IVOD21
IAVOD21
IAVOD2AI
IVOD2AI
VOCM
IAVOCMI
0
1.5
1.5
Typ
Unit
5.5
Vdc
VCC
Vdc
12
Vdc
60
rnA
70
DC
Max
Unit
VCC
Vdc
Vdc
Vdc
mVdc
Vdc
mVdc
Vdc
mVdc
DRIVER CHARACTERISTICS
Output Voltage
Single Ended, 10 = 0
Differential, Open Circuit (10 = 0)
Differential, RL = 54 Q
Change in Differential Voltage (Note 1), RL = 54 Q
Differential, RL = 100 Q
Change in Differential Voltage (Note 1), RL = 100 Q
Common Mode Voltage, RL = 54 Q
Common Mode Voltage Change, RL = 54 Q
Output Current (Each Output)
Short Circuit Current, -7.0 V,;; VO';; 12 V
lOS
2.0
-
-
200
-
-
200
3.0
200
-250
-
250
-
0.8
rnA
Driver Data Inputs
Low Level Voltage
High Level Voltage
Clamp Voltage (lin = -18 rnA)
VILD
VIHD
VIKD
2.0
-1.5
-
Vdc
Thermal Shutdown Junction Temperature
TJTS
-
150
-
DC
-
mVdc
-
-
200
-200
-
0.36
100
1.0
VH
VOHR
VOLR
2.4
-
-
-
45
-
RECEIVER CHARACTERISTICS
Input Threshold
RO=High
RO = Low
Input Loading (Driver Disabled)
Hysteresis
Output Voltage
High (IOH = -400 1lA)
Low (IOL = 4.0 rnA)
Output Short Circuit Current
Output Leakage Current When in Three-State Mode
NOTE:
7-106
Vth
IOSR
10LKR
-
-
-
U.L.
mV
-
Vdc
0.4
85
20
rnA
IlA
1. Input swnched from low to high.
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
ELECTRICAL CHARACTERISTICS (continued) (TA
I
=25°C, VCC =5.0 V ± 10%)
I
Symbol
Min
Typ
Max
VILE
VIHE
VIKE
0
2.0
-1.5
-
0.8
VCC
ICC
-
18
28
VOHT
VOLT
2.4
0
-
-
0.8
Propagation Delay - Input to Single Ended Output
Input to Output - Low-to-High
Input to Output - Hlgh-to-Low
tpLH
tPHD
-
10
11
20
20
Propagation Delay - Input to Differential Output
Input Low-to-High
Input High-to-Low
tpLHD
tpHLD
15
15
23
23
tDR,tDF
-
9.0
10.7
tSKI
tSK2
tSK3
0
0
0
0.1
-
8.0
6.0
tSK7
tSK8
0
0.1
<4.0
-
Characterlatlc
Unit
MISCELLANEOUS
Enable Inputs
Low Level Voltage
High Level Voltage
Clamp Voltage (lin = -18 mAl
Vdc
Power Supply Current (Total Package, All Outputs Open, Enabled
or Disabled)
Thermal Shutdown Output VoHage
High
Low
-
mA
Vdc
TIMING CHARACTERISTICS - DRIVER
ns
ns
Differential Output Transition Time
Skew Timing
ItPLHD - tPHLDI for Each Driver
Maximum - Minimum tpLHD Within a Package
Maximum - Minimum tpHLD Within a Package
MC34058
Skew Timing
MC34059
ItPLHD - tPHLDI for Each Driver
Propagation Delay Difference Between Any Two Drivers (Same
Package or Different Packages at Same VCC and TA)
Enable Timing
Single Ended Outputs
Enable to Aciive High Output
Enable to Active Low Output
Active High to Disable
Active Low to Disable
Differential Outputs
Enable to Active Output
Enable to Three-State Output
ns
ns
ns
-
ns
tPZH
tPZL
tpHZ
tpLZ
-
15
25
12
10
40
40
25
25
tpZD
tPDZ
-
-
40
25
tpLHR
tpHLR
-
16
16
23
23
tSK4
tSK5
tSK6
0
0
0
1.0
-
3.0
3.0
tSK9
-
<5.0
-
TIMING CHARACTERISTICS - RECEIVER
Propagation Delay
Input to Output - Low-to-High
Input to Output - High-to-Low
Skew Timing
HpLHR - tpHLRI for Each Receiver
Maximum - Minimum tPLHR Within a Package
Maximum - Minimum tPHLR Within a Package
Skew Timing
Propagation Delay Difference Between Any Two Receivers in Different
Packages at Same V CC and TA (MC34059 Only)
Enable Timing
Single Ended Outputs
Enable to Active High Output
Enable to Active Low Output
Active High to Disable
Active Low to Disable
MOTOROLA ANALOG IC DEVICE DATA
ns
-
ns
ns
ns
tpZHR
tpZLR
tpHZR
tpLZR
-
-
15
25
12
10
22
30
25
25
7-107
MC34058 MC34059
Block DIagram and PInout
Gnd
RE6
016
Roe
DR5
RE5
DE5
Gnd
36 Gnd
Gnd
35 OA5
OA6
34 OBS
OB6
II
DE6
DR4
4
DR1
OA4
OA1
084
081
DE4
DE1
8
29 RE4
RE1
9
28 083
082
10
27 OA3
0A2
11
26 Gnd
Gnd 12
25 Gnd
Gnd
RE2
DR2
Vee
RE3
DE3
TSD
Gnd
PINOUT SUMMARY
Driver Enable, Active High (TTL)
OA
Nonlnverting Output/Input
DE
OB
Inverting Output/Input
RE
DR
Driver Input/Receiver Output (TTL)
TSD
016
#6 Driver Input (TTL)
VCC
Connect 4 Pins to 5.0 V, ± 10%
R06
#6 Receiver Output (TTL)
Gnd
Connect 12 Pins to Circuit Ground
7-108
Receiver Enable, Active Low (TTL)
Thermal Shutdown Indicator
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
Figure 1. VOD and VOS Test Circuit
Vee
Vin
(0.8 or 2.0 V)
Figure 2. VOD and VCM Test Circuit
Vee
375
Vin
(0.8 or 2.0 V)
58
375
I
veM
(+12 to ±7.0 V)
Figure 3. VOD AC Test Conditions
Vee
54
ro~
I
Vin
OV
Voo
OAl(
-=-
VOD
telr
-=-
telr
Figure 4. VOH and VOL AC Test Conditions
-
2.3 V
Vee
3.0V
Vin
OV
27
Output
I
-=-
-=-
15pF
3.0V
3.0V
3.0V
3.0V
OAX
OBX
VOL
VOH
-=-
MOTOROLA ANALOG IC DEVICE DATA
7-109
MC34058 MC34059
Figure 5. VOH versus IOH
4.6
4.4
~
4.2
:I:
-?
4.0
/
3.8
3.6
-80
V
/
Figure 6. VOL versus IOL
1.1
/
V
./
0.9
~
..J
/
0.8
V
>0
0.7
0.6
/
-60
./
1.0
-40
-20
20
/
/" "
10
20
./
30
40
50
Figure 7. VOD versus IOL
Figure 8. Input Characteristics of
OAX and OAB
0.4
II
~
0
-?
------
0.3
~
I
0.2
!z
0.1
~
0
OAXJin(mA)
~
~
-4.0
-50
o
~ -0.2
50
-0.3
100
IOO(mA)
Description
The MC34058/9 is a differential line driver designed to
comply with EIA-485 Standard for use in balanced digital
multipoint systems containing multiple drivers. The drivers
also comply with EIA-422-A and eelTT Recommendations
V.11 and X.27. Positive and negative current limiting of the
drivers meet the EIA-485 requirement for protection from
damage in the event that two or more drivers try to transmit
simultaneously on the same cable. Data rates in excess of
10 MBPS are possible, depending on the cable length and
cable characteristics. Only a single power supply, 5.0 V
± 10% is required.
Driver Inputs
The driver inputs and enable logic determine the state of
the outputs in accordance with Table 1. The driver inputs have
7-110
f
D..
~
-0.4
-10
,
~
80
1#
. / OBXJin(mA)
0
a -0.1
-2.0
-100
70
IOL(mA)
4.0
2.0
60
IOH(mA)
~
~
-5.0
"
o
5.0
10
15
INPUT VOLTAGE (V)
a nominal threshold of 1.2 V, and the voltage must be kept
within the range of 0 V to Vec for proper operation. If the
voltage is taken more than 0.5 V below ground or above Vec,
excessive currents will flow and proper operation of the
drivers will be affected. An open Pin is equivalent to a logic
high, but good design practices dictate that inputs should
never be left open. The inputs are TTL type and their
characteristics are unchanged by the state of the enable pins.
Driver Outputs
Each output (when active) will be a low or a high voltage,
depending on the input state and the load current (see
Tables 1, 2 and Figures 2 and 3). The graphs apply to each
driver, regardless of how many other drivers within the
package are supplying load current.
MOTOROLA ANALOG
IC DEVICE DATA
.
.
MC34058 MC34059
Table 1. Driver Truth Table
Enables
Outputs
Driver Data Inputs
DEX
REX
OAX
H
H
H
H
OBX
L
L
H
H
L
H
X
L
H
Z
Z
X
H
L
Not Defined
Not Defined
The outputs will be In a high impedance state when:
a) The Enable inputs are set according to Table 1;
b) The Junction temperature exceeds the trip point of the thermal shutdown circuit. When in this condition, the output's source and sink capability are shut off, and a
leakage current of less than 20 ~ will flow. Disabled outputs may be taken to any voltage between -7.0 V and 12 V without damage to Internal circuitry.
The drivers are protected from short circuits by two methods:
a) Current limiting is provided at each output, in both the source and sink direction, for shorts to any voltage w~hin the 12 Vto -7.0 V range, with respect to circuit
ground. The short circuit current will flow until the faun is removed, or until the thermal shutdown activates. The current limiting circuit has a negative temperature
ocefflcient and requires no resetting upon removal of the fauR condition.
b) A thermal shutdown circuit disables the outputs when the junction temperature reaches +150'C, ± 20'C. The thermal shutdown circuit has a hysteresis of - 12'C
to prevent oscillations. When this circuit activates, the output stage of each driver Is put into the high Impedance mode, thereby shutting ott the output currents.
However, the remainder of the internal circuitry remains biased and the outputs will become active once again as the IC cools down.
Receiver Inputs
The receiver inputs and enable logic determine the state of
the receiver outputs in accordance with Table 2. Each
receiver input pair has a nominal differential threshold of at
most 200 mV (Pin OAX with respect to OBX) and a common
mode voltage range of -7.0 V and 12 V must be maintained
for proper operation. A nominal hysteresis of 100 mV is
typical. The receiver input characteristics are shown in
Figure 8. When the inputs are in the high impedance state,
they remain capable of the common mode voltage range of
-7.0 V to 12 V.
Receiver Outputs
The receiver outputs are TTL type outputs and act in
accordance with Table 2.
Enable Logic
Each driver output is active when the Driver Enable input
is true according to Table 1. Each receiver output is active
when the Receiver Enable input is true according to Table 2.
The Enable inputs have a nominal threshold of 1.2 V and
their voltage must be kept within the range of 0 V and VCC for
proper operation. If the voltage is taken more than 0.5 V
below ground or above VCC, excessive currents will flow and
proper operation of the drivers will be affected. An open pin is
equivalent to a logic high, but good design practices dictate
that inputs should never be left open. The enable inputs are
TTL compatible. Since the same pins are used for driver input
and receiver output, care must be taken to make sure that
DEX and REX are not both enabled. This may result in
corruption of both the transmitted and received data.
Table 2. Receiver Truth Table
Receiver Data Inputs
Enables
Outputs
OAX-OBX
DEX
REX
DRX
:?:+200mV
L
L
H
S;-200mV
L
L
L
X
L
H
Z
X
H
L
Not Defined
APPLICATIONS
The MC34058/9 was designed to meet EIAlTIA-422 and
EIAlTIA-485 standards. EIAlTIA-422 specifies balanced
point-to-point transmission with the provision for multiple
receivers on the line. EIAlTIA-485 specifies balanced
point-to-point transmission and allows for multiple drivers
and receivers on the line. Refer to EIAITIA documents for
more details. Figure 9 shows a typical EIAlTIA-422 example.
Figure 10 shows a typical EIAlTIA-485 example.
Figure 9. Typical EIAlTIA-422 Application
[....""''------I--...--l-.-- - - - --I---4f'=+--l..--
MOTOROLA ANALOG IC DEVICE DATA
7-111
•
MC34058 MC34059
Figure 10. Typical EIAlTIA-485 Application
II
EIAlTIA-422 specifications require the ability to drive at
least 10 receivers of input impedance of greater than or equal
to 4.0 K(1 plus the 100 (1 termination resistor. This protocol
was intended for unidirectional transmission. EIAlTIA-485 is
capable of bidirectional transmission by allowing multiple
drivers and receivers on the same twisted pair segment. The
loading of the twisted pair segment can be up to 32 Unit
Loads (U.L.) plus the two 120 (1 terminating resistors. The
U.L. definition is shown in Figure 11.
where:
Oja package thermal resistance (see Appendix A)
TJmax =Maximum Junction Temperature. Since the
thermal shutdown feature has a trip point of 150°C ± 20°,
TJmax is selected to be +130°C.
TA Ambient Operating Temperature.
=
=
The power generated within the package is then;
PO" {[
Figure 11. TIAIEIA-485 Unit Load Definition
(vcc-
(,,,,,-dO,,"" ..
VOL' IOL }
6
Calculating Power Dissipation for the
MC3405819 Hex-Transceiver.
The operational temperature range is listed as O°C 10 70°C
to satisfy both EIAlTIA-485 and EIAlTIA-422 specifications.
However, a lower ambient temperature may be required
depending on the specific board layout and/or application.
Using a first order approximation for heat transfer, the
maximum power which may be dissipated by the package is
determined by (see Appendix A for more details);
PDmax =
7-112
TJmax-TA
Oja
6
VCH ,)' ICH,] + VOl,' lOLl} + ..
+ {[
(Vee -VOH,)' 10H,] +
+ VCC
. ICCQ
[2]
As indicated in the equation, the part of Equation 2
consisting of IOH , VOH ,IOL and VOL must be calculated for
each of the drivers and summed for the total power
dissipation estimate. The last term can be considered the
quiescent power required to keep the IC operational and is
measured with the drivers idle and unloaded. The VOH and
VOL terms can be determined from the output current
versus output voltage curves which provide driver output
characteristics.
Example 1 estimates thermal performance based on
current requirements.
[1]
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
Example 1. Balanced and Unbalanced Operation
IOL = 50 mA and IOH = ±50 mA for each driver. VCC = 5.0 V.
How many drivers can be used? (Typical power supply current ICCO
=18 mA.)
Solution:
.
ICCO 0.018 A
The quiescent power is given by: PO = ICCO' V CC ' and IS equal to PO = 0.09 W.
Balanced Operation:
Unbalanced Operation:
To determine the amount of power dissipated by each
To determine the amount of power dissipated by each
output stage we need to know the single-ended output
output stage we need to know the differential output voltage
for the output current required. Figure 7 shows that for IOH
voltage for the output current required. Figures 5 and 6
shows that for an IOH and IOL of ±50 mA,
and IOL differential of 50 mA, VOOH and VOOL are:
=
V OH = 3.9 V
VOO = 13.01, and IOL = "OHI = lOut = 0.050 A.
And the power dissipated by each driver is given by;
P OrvB = lOut' (VCC - V Oo ) and equal to
P OrvB = 0.10 W.
VOL = 0.895 V
And the power dissipated by each driver is calculated by;
)
P OrvU =
V OH . "OHI + VOL' IOL
and equal to
P OrvU = 0.10 W.
(vcc-
(For this example, balanced operation is assumed.)
Summing the quiescent and driver power for 6 transceivers operating in a package produces;
POTotal
=PO + 6·
POrvB, and equal to POTotal
=0.69 W.
For the MC34058/9, the thermal resistance is capable of a wide range. The ability of the package to dissipate power depends
on board type and temperature, layout and ambient temperature (see Appendix A). For the purposes of this example the
thermal resistance can range from 40°C/W to 100°C/W;
Sja = j, j = 40, 60, .. 100°C/W.
=
Varying the ambient operating temperature TA 25, 30, .. 85°C; specifying a maximum junction temperature to avoid
thermal shutdown TJmax 130°C; and using the first order approximation for maximum power. dissipation;
=
Pomax(Sja)' T A =
TJmax-TA
Sja
produces a set curves that can be used to determine a Safe Operating Area for the specific application. POTotal is graphed with
PO max to provide a reference.
Graph of Maximum Power Dissipation Possible
for a Particular Sja and Ambient Temperature
3.0,----,----.,,----,---,--...,----,--,
2.5f---==""""~-+--+---+--_t--+--_j
en
~
;:
2.0
1.51---+---'==-+-=--+--1-----''''''''..£--1----1
0.5 f--"'k---+----''k---t--_t=''''''"-t-oo-_j
PDTota!
30
40
70
80
90
• Safe Operating Area (SOA), is an operating power, PDTotal, less than PDmax.
So all the drivers in the package can be used if the thermal resistance and/or the ambient temperature is low enough.
MOTOROLA ANALOG IC DEVICE DATA
7-113
•
MC34058 MC34059
Appendix A. Optimizing the Thermal Performance of the MC3405819
Figure 12. Electrical Model of Package Heat Transfer
(Ieads-to-board) combination in Figure 12. This path
provides the most effective way of removing heat from the
device provided that there is a viable temperature potential
(Le. heat sinking source) to conduct towards. However, if it is
not properly considered in the system design, the other
paths, (Rjcd + Rcdb) and (Rjcu + Rca) attain greater
importance and must be more carefully considered.
So Equation 1, modified to reflect a more complete heat
transfer model becomes;
[Ria:;t.]
[2]
RJL
PDISS . Sja
ReDB
RLB
II
_
Board Temperature
An equivalent electrical circuit for the thermal model for the
MC3405819 package is shown in Figure 12. It is a simplified
model that shows the dominant means of heat transfer from
the thermally enhanced 48-ld package used for the
MC3405819. The model is a first order approximation and is
intended to emphasize the need to consider thermal issues
when designing the IC into any system. It is however
customary to use similar models and Equation 1 to estimate
device junction temperatures.
Equation 1 is the common means of using the thermal
resistance of a package to estimate junction temperature in a
particular system.
[1]
The term Sjx in Equation 1 is usually quoted as a 0ja value
in °ClWatt. However, since the 48-ld package for the
MC3405819 has been thermally enhanced to take advantage
of other heat sinking potentials, it must be modified. Sjx must
actually be considered a composite of all the heat transfer
paths from the Chip. That is, the three dominant and parallel
paths shown in Figure 12. Of those three paths, potentially
the most effective is the corner package leads. This is
because these corner leads have been attached to the flag
on which the silicon die is situated. These pins can be
connected to circuit board ground to provide a more efficient
conduction path for internal package heat. This path is
modeled as the Rjl (junction-to-Ieads) and Rib
7-114
where;
TJ= Junction Temperature
TA = Ambient Temperature
TS = Soard Temperature
PDISS = Device Power
and Sja = Total Thermal Resistance and is composed the
parallel combination of all the heat transfer paths from
the package.
While Equation 2 is still only a first order approximation of
the heat transfer paths of the MC34058/9, at least now it
includes consideration for the most effective heat transfer
path for the MC34058/9; the board to which the device is
soldered. The modified equation also better serves to
explain how external variables, namely the board and
ambient temperatur~s, affect the thermal performance of
the MC3405819.
Methods of removing heat via the flag connected pins can
be classified into two means; conduction and convection.
Radiation is omitted as the contribution is small compared to
the other means. Conduction is by far the best method to
draw heat away from the MC34058/9 package. This is best
accomplished by using a multilayer board with generous
ground plane. In this case, the flag connected pins can be
connected directly to the ground plane to maximize the heat
transfer from the package. Figure 13 shows the results of
thermal measurements of a board with an external ground
plane (the actual ground area was approximately 6 1/4 in2).
The thermal leads are connected to the board ground plane
per the recommended strategy.
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
Figure 14A. Thermal Resistance (Sja) for
Board Without Ground Plane
Figure 13. Thermal Resistance (6ja) for Board
with Large External Ground Plane
120
55
110
50
1\
100
\
-r--r--
35
30
o
100
200
300
--
400
500
~
L
.,
~
90
,
~Radiators
80
70
"'" -
" ~ .....
~
~
Masked Radiators'
~
~~
80
Exposed Radiators'
50
600
AIR SPEED (LINEAR FTIMIN)
Sjc for the package on this board is 25 ± 20% depending on the location of
the package on the board.
o
200
400
600
----
800
1000
1200
AIR SPEED (LINEAR FTlMIN)
, Masked radiators were covered by a solder mask. Exposed radiators
were bare copper.
Figure 14B. Layout Used for Thermal Resistance
Measurements in Figure 14A
Figure 15. Placement of Thermal Vias to Enhance
Heat Transfer to Ground Plane
Figure 14A on the other hand shows the result of a single
layer board without an internal ground plane. The graphs
show that even though there are radiators of substantial area
surrounding the package, substantial degredation of thermal
performance is evident (Figure 14B shows the layout used
for the measurements in Figure 14A). Comparing Figures 13
and 14A shows almost a 2:1 improvement for the strategy
involving the external ground plane.
It is clear from Figures 13, 14A and Example 1, that if an
application is to use all the device drivers, preparations to
assure adequate thermal performance of the system must
be taken.
If an extensive external ground plane is unavailable, and
only an internal ground plane is available, the thermal
performance of the device can still be improved by providing
thermal vias to connect the radiators to the internal ground
plane. Figure 15 shows a proposed scheme for thermal vias
(contact board manufactures for specifics about the thermal
performance of their products and possible enhancements).
The thermal resistance for this structure on 1.0 oz. Copper
connecting each of the four radiators to an internal ground
plane and provide an estimated thermal resistance of
approximately 5.0°CIW. The vias used in the estimate had
80 mil diameters, on 100 mil centers and a 1.0 mil copper
thickness.
MOTOROLA ANALOG IC DEVICE DATA
7-115
•
®
MOTOROLA
MC34156
Product Preview
28-Channel Inkjet Driver
The MC34156 is a 28-Channel Decoder/Driver intended to be used in
inkjet printer applications. By using sophisticated SMARTMOSTM technology, it
has been possible to combine low power CMOS inputs and logic and high
current, high voltage bipolar outputs capable of sustaining a maximum of 30 V.
A 4-t0--14 line decoder determines the selected output driver (n) in each
14-driver bank. Two independent output enable inputs (active low) then
provide the final decoding to activate 1- or 2--of-28 outputs (OUTAn and/or
OUTBn). The ac electrical characteristics of the drivers are tightly controlled
and thereby the energy of the device delivers to the inkjet print head. A Chip
Enable function is provided to lock out the drivers during system power up.
The 28 bipolar power outputs are open collector 30 V Darlington drivers
capable of sinking 500 mA at ambient temperatures up to 70°C. All driver
outputs are capable of withstanding a contact discharge of ±8.0 kV with the
IC biased.
28-CHANNEL
INKJET DRIVER
(SMARTMOSTM Technology)
SEMICONDUCTOR
TECHNICAL DATA
• ESD Output Protection with Clamping Diodes
• Addressable Data Entry
• Tightly Controlled AC and Electrical Characteristics for Inkjet Printers
II
FNSUFFIX
PLASTIC PACKAGE
CASE 777
• CMOS, TTL Compatible Inputs
• Low Power CMOS Logic
ORDERING INFORMATION
DeVice
MC34156FN
Operating
Temperature Range
Package
TA=OOto+70°C
Plastic Package
PIN ASSIGNMENTS
Pin No.
1
2
3
4
Simplified Block Diagram
«
'"
.l!!
~
:::>
a
:fJ ~
Iii
~
I
Jj e
a;U)
~
c
~
0
~
'"
~
~
a;~
«
~
7
8
!
i
9
OUTAD
OUTA1
OUTB4
10
11
12
13
14
15
16
17
18
19
20
OUTA2
21
OUTAS
23
24
OUTA4
22
25
CUTB6
OUTA5
26
27
28
OUTB?
OUlA6
29
30
OUTBB
OUTA?
31
32
OUTB9
OUTA9
NIC
Gnd
33
34
35
36
37
38
39
Q
z
Q
z
0
i!!:::>
a
7-116
i!!'" Iii5'"'
:::>
a :::>
a a
Iii
I-
'" '"
ga ga a~
:::>
i '"
a0
40
41
42
43
44
Pin Name
IND
VDD
Gnd
ENB
Chip Enable
aUTSO
aUTB1
aUTB2
aUTB3
aUTB4
aUTB5
aUTB6
aUm7
aUTB8
aum9
GOd
NlC
N/C
NlC
aUTB10
aUTB11
aUTB12
aUTB13
aUTA13
aUTA12
aUTA11
aUTA10
COM
Gnd
aUTA9
aUTA8
aUTA7
aUTA6
aUTA5
aUTA4
aUTA3
aUTA2
aUTA1
aUTAD
ENA
INA
Gnd
INB
INC
Pin Description
4th Decoder Input
Power Supply
Ground
Enable Pin for B Set Drivers
Chip Enable
B Set 1st Driver
B Set 2nd Driver
B Set 3rd Driver
B Set 4th Driver
B Set 5th Driver
B Set 6th Driver
B Set 7th Driver
B Set 8th Driver
B Set 9th Driver
B Set 10th Driver
Ground
Not Connected
Not Connected
Not Connected
B Set 11th Driver
B Set 12th Driver
B Set 13th Driver
B Set t4th Driver
A Set 14th Driver
A Set 13th Driver
A Set 12th Driver
A Set 11th Driver
Common
Ground
A Set 10th Driver
A Set 9th Driver
A Set 8th Driver
A Set 7th Driver
A Set 6th Driver
A Set 5th Driver
A Set 4th Drrver
A Set 3rd Driver
A Set 2nd Driver
A Set 1st Driver
Enable Pin for A Set Drivers
1st Decoder Input
Ground
2nd Decoder Input
3rd Decoder Input
MOTOROLA ANALOG IC DEVICE DATA
MC34156
Figure 1. Functional Block Diagram
Output Enable A
OUTAO
OUTA1
Logic Supply 0
OUTA2
Chip Enable
G--------t--t-+---.
OUTA13
INA (LSB)
OUTBO
<;;
"0
INB
8
'"c:
INC
•
'"
Cl
OUTB1
:::i
iJ
OUTB2
INO(MSB)
Output Enable B
OUTB13
Figure 2. Output Driver Configuration
Figure 3. Typical Input Circuit
VOO
l·IOCOM
L.- - - - < 0
MOTOROLA ANALOG IC DEVICE DATA
OUT
7-117
®
MOTOROLA
MC34250
Product Preview
5.0 V, 200 M-Bit/Sec PR-IV
Hard Disk Drive Read Channel
The Motorola MC34250 is a fully integrated partial response maximum
likelihood disk drive read/write channel for use in zoned recording
applications. This device integrates the AGC, active filter, 7 tap equalizer,
Viterbi detector, frequency synthesizer, servo demodulator, 8/9 rate (0,4/4)
Encoder/Decoder with write precompensation and power management in a
single 64 pin 10 mm x 10 mm TQFP package.
HARD DISK DRIVE
READ CHANNEL
SEMICONDUCTOR
TECHNICAL DATA
FEATURES:
• 50 to 200 MBPS Programmable Data Rate
• 800 mW at 200 MBPS and 5.0 V
• Channel Monitor Output
• Programmable AGC Charge Pump Currents with Different Values for
Data and Servo Envelope Modes and Gain Gradient Mode
II
• Programmable AGC Peak Detector Droop Currents with Different
Values for Data and Servo Envelope Modes
• Separate AGC Charge Pump Outputs for Data and Servo Modes
• Programmable Dual Threshold Qualifier or Hysteresis Comparator Type
Pulse Detector for Servo Data Detection.
64
• ERD and Polarity Outputs for Servo Timing and Raw Encoded Data
• Integrated 7 pole 0.05° Equiripple Linear Phase Filter with
Programmable Bandwidth from 5.0 MHz to 80 MHz and Different Values
for Both Data and Servo Modes
• Programmable Symmetrical Boost from 0 to 10 dB and Different Values
for Data and Servo Modes
FTASUFFIX
PLASTIC PACKAGE
CASE 840F
(ThinOFP)
• Programmable Asymmetrical Boost of Up to ±40% of Nominal Filter
Group Delay in Both Data and Servo Modes
• 7 Tap Continuous Time Transversal Equalizer with 8 Bit Programmable
Tap Weights and Integrated Decision Directed Sign-8ign least Mean
Squared Adaptation
• Internal Offset Cancellation loops
• Fast Acquisition Data Phase locked loop with Zero Phase Restart
ORDERING INFORMATION
Device
MC34250FTA
Operating
Temperature Range
Package
TA=OOto+70°C
TOFP-64
• Programmable Data Phase locked loop Charge Pump Current
• Integrated Soft Decision Viterbi Detectors with Programmable Merge
References
• Integrated 8/9 Rate (0,4/4) Encoder and Decoder with Code Scrambler
and Descrambler
• Programmable 214/8 Bit NRZ Data Interface
• Programmable Write Precompensation Delays locked to the Frequency
Synthesizer
• Differential PECl Write Data Outputs
• External Write Data Path for DC Erase or Other Non-Encoded Data
• Integrated Write Current DAC
• Programmable Power Management
• Bi-Directional Serial Microprocessor Interface
• Various Test Modes Controlled Via the Serial Microprocessor Interface
7-118
MOTOROLA ANALOG IC DEVICE DATA
!!:
0
'" '" '" '"
:0 :n :n
;g~CJ)cna~~
en
a
'"c
.:f
(")
:D
en en
m
Z
jJ
§3
0
C
!i:
C3
r-
~~~~cc~
Eii1il~~~~~
jJ
~
-<
~
c
c
;:::
"
"-nr-r- "-nr-r-
)0
z)0
r0
C)
(';
,--L--L,
---
C
m
<
(';
m
CLAMPS
C
~
~
0
-i
:::r
oj"
Co
~.
0
Pulse Detector
I
++
r-t
I
I
H
I
Thresholds
Viterbi Detector
Path Memory
Viterbi Margin
VINP
VINM
(/)
CD
0
0
"~
"'"
0
"80
III
g,
<
CD
:
HOLDS
819 (0,414) ENDEC
Synchronization
SyteDetect
CDATA
CSRVO
SYNCDET
NRZ(7:0)
NRZCLK
READGT
WRITEGT
WRITECLK
g
~
C
;
3
CRI4Q
!il
r"I:IIT~
0
I
"'----~I
Power
Manager
~
I-
Write
Precompensetion
T T
Mode
~WDATAP
WDATAM
Coefficients
SLATCH
~I
CD
CD
CD
"!Il.!I!"
FREFU
3i
t:I.
iii"
SRVOGT
SLEEPS U
3"
"2-
I
~I
Fr~uency
Synt esizer
en
~ -<
z
:;!
=B
~
-n
;:::
~
ZoneClk
WCDAC
Data
MCU Interface
-~
z~::t: ~
'"
~
en
iiE
~
m
I
mSDATA
SCLK
s::
0
Co)
-'N="
UI
0
®
MOTOROI.A
MC68160
Enhanced Ethernet Transceiver
The MC68160 Enhanced Ethernet Interface Circuit is a BiCMOS device
which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE-T
Twisted Pair (TP) Interface media connections through external isolation
transformers. It encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via 10BASE-T or AUI
interfaces. The MC68160 gluelessly interfaces to the Ethernet controller
contained in the MC68360 Quad Integrated Communications Controller
(QUICC) device. The MC68160 also interfaces easily to most other
industry-standard IEEE 802.3 LAN controllers. Prior to twisted pair data
reception, Smart Squelch circuitry qualifies input signals for correct
amplitude, pulse width, and sequence requirements.
• Interfaces with AMD, National, Intel and Fujitsu IEEE 802.3 LAN Controllers
ENHANCED ETHERNET
INTERFACE TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
• Automatic Twisted Pair Wiring Polarity Fault Detection and Correction
Option
• Automatic Port Selection Option with Status Output
• Driver Pre-emphasis for Twisted Pair Output Data
52
• Crystal Controlled Clock Oscillator or External Clock Generator Option
II
• Digital Phase-Locked-Loop (DPLL) Timing Recovery and Data Decoding
FBSUFFIX
PLASTIC PACKAGE
CASE 848D
(ThinOFP)
• Standby Mode with Reduced Power Consumption
• Twisted Pair Signal Quality Error (Heartbeat) Test Option
• Diagnostic Local Loop Back Option
• Transmit, Receive and Collision Detection Status Output
ORDERING INFORMATION
• Full-Duplex Operation Option on Twisted Pair Port
• Twisted Pair Jabber Detection and Status Output
Device
• Link Integrity Testing and Status Output
MC68160FB
Operating
Temperature Range
Package
TA= 0 to +70°C
TOFP-52
0
Figure 1. 1DBase-T Interface Block Diagram
RX.-----------~~~8rl
RCLK
1+-------------1
ARX+'
MFILT _ - - - - - - - - - '
ARX-
RXLED==~~~~~~JL~~~Jr~
_ _ _ _ _~
RENA_
CLLED
1&1
CLSN
~TXLED
ACX+
ACX-
-;===;----.1'""""1
ATX-
m
TENA ~===~~nBrii:heSi6rl
i;
TX
~
1&1
ATX+
~
5c(
Xl
Twisted
Pair
Polarity
Error
Control
X2_---U~.J
TCLK_----I
CSO~
CSl
CS2
TPEN
APORT
TPAPCE
TPSOEL
TPFULDL
LOOP
1&1
~
II:
Mode
Select
TPJABB
TPTX+ TPTX-
TPLiL
TPSOEL
TPRX-
TPRX+ TPPLR
This device contains 20,000 active transistors.
7-120
MOTOROLA ANALOG IC DEVICE DATA
MC68160
Enhanced Ethernet Serial Transceiver
Table 1. Pin Descriptions .............................................................................. 7-122
Controller Interface Pins ................................................................................. 7-122
AUllnterface Pins ....................................................................................... 7-122
Twisted Pair Interface Pins ............................................................................... 7-122
Oscillator and Frequency Multiplier Pins .................................................................... 7-123
Mode Select Pins ....................................................................................... 7-123
Status Indicator Pins .................................................................................... 7-124
Power Supply and Ground Pins ........................................................................... 7-124
Table 2. Controller Interface Selection ................................................................. 7-125
Table 3. Controller Independent Mode Selection ...................................................... 7-125
Electrical Characteristics .............................................................................. 7-126
Maximum Ratings ....................................................................................... 7-126
Recommended Operating Conditions ...................................................................... 7-126
ESD ................................................................................................... 7-126
DC Characteristics .................................................................................... 7-126
Power Supply DC Characteristics ......................................................................... 7-126
TTUCMOS Input and Output DC Characteristics ............................................................ 7-127
Twisted Pair Input and Output DC Characteristics ........................................................... 7-127
AUllnput and Output DC Characteristics ................................................................... 7-128
AC Characteristics .................................................................................... 7-129
External Clock Input(X1) Switching Characteristics .......................................................... 7-129
Receive Phase Locked Loop Switching Characteristics ....................................................... 7-129
Controller Transmit Switching Characteristics (Motorola Mode) ................................................ 7-129
Controller Receive Switching Characteristics (Motorola Mode) ................................................. 7-129
Controller Transmit Switching Characteristics (Intel Mode) .................................................... 7-131
Controller Receive Switching Characteristics (Intel Mode) ..................................................... 7-131
Controller Transmit Switching Characteristics (Fujitsu Mode) .................................................. 7-132
Controller Receive Switching Characteristics (Fujitsu Mode) .................................................. 7-132
Controller Transmit Switching Characteristics (National Mode) ................................................. 7-133
Controller Receive Switching Characteristics (National Mode) ................................................. 7-133
TP Transmit SWitching Characteristics ..................................................................... 7-135
TP Transmit Jabber Switching Characteristics ............................................................... 7-137
TP Transmit Signal Quality Error Test Switching Characteristics ............................................... 7-137
TP Receive Switching Characteristics ...................................................................... 7-138
TP Receive Link Integrity Switching Characteristics .......................................................... 7-138
TP Collision Switching Characteristics ..................................................................... 7-140
TP Full Duplex Switching Characteristics ................................................................... 7-140
AUlTransmit Switching Characteristics .................................................................... 7-141
AUI Receive Switching Characteristics ..................................................................... 7-141
Functional Description ................................................................................ 7-142
Data Transmission ...................................................................................... 7-142
Data Reception ......................................................................................... 7-143
Collision ............................................................................................... 7-143
Jabber ................................................................................................. 7-143
Full Duplex ............................................................................................. 7-143
Auto Port Selection ...................................................................................... 7-143
Auto Polarity Selection ................................................................................... 7-143
Loop Back Mode ........................................................................................ 7-143
Applications ........................................................................................... 7-144
Selection of Crystal and External Components .............................................................. 7-144
PLL Filter Components .................................................................................. 7-144
10BASE-T Filter and Transformer Choice .................................................................. 7-144
AUI Transformer Choice ................................................................................. 7-144
MOTOROLA ANALOG IC DEVICE DATA
7-121
•
MC68160
Table 1. Pin Function Description
Pln(s)
Symbol
Type
Name/Function
CONTROLLER INTERFACE
1
0
RENA
TTUCMO
2
0
RX
TTUCMOS
48
0
TCLK
TTUCMOS
49
TENA
50
RCLK
I
TTL
0
TTUCMOS
51
0
CLSN
TTUCMOS
II
52
Receive Enable Output: Indication of the presence of network activity, synchronous to
RCLK. In the standby mode, RENA is driven to the high impedance state.
Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation,
100 ms should be allowed before attempting to read data processed by the MC68160. This
delay is needed to insure that the receive phase locked loop is properly synchronized with
Incoming data. In the standby mode, RX is driven to the high impedance state.
Transmit Clock Output CMOSITTL Output: TCLK provides a sYl'(lmetrical clock signal at
10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to
the high impedance state.
Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission
on the active port. An internal pull-down resistor is provided so that the input is low under no
connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at
the conclusion of a reset operation, it must first be deasserted and then reasserjed before
data transmission can occur. In the standby mode, TENA is driven to the high impedance'
state.
Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high
impedance state.
Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and
ACX- terminals which meet threshold and pulse width requirements. In the TP mode,
indicates simultaneous transmit and receive activity, a heartbeat (SQI:: Test) signal was
generated, or the jabber timer has expired. In the standby mode, CLSN is driven. tq the high.
impedance state.
TX
I
TTL
Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to
be Manchester encoded. In the standby mode, TX is driven to the high impedance state.
21
22
ACXACX+
I
AUI Differential Collision Inputs: These Inputs are connected to a pair of intemally biased
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity. Signals at ACX+/- have no effect on data path functions.
23
24
ARXARX+
I
AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity, and a data receiver with no offset .for Manchester Data reception.
25
26
ATXATX+
0
AUIINTERFACE
AUI Differential Transmit Outputs: This line pair is intended to operate into terminated
transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is
previously asserted, Manchester encoded data is outputted at ATX+/-. When operating into a
78 Q terminated transmission line, signaling meets the required output levels and skew for
IEEE-802.3 drop cables. When the 10BASE-T port is automatically or manually selected,
the AUI outputs are driven to a low power standby state in which the outputs deliver a
balanced high state voltage.
TWISTED PAIR INTERFACE
31
32
TPRXTPRX+
I
Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with
Smart Squelch capability which only allows differential receive data to pass as long as the
input amplitude is greater than a minimum signal threshold level and a specific pulse
sequence is received. This assures a good signal to noise ratio while the signal pair is active
by preventing crosstalk and impulse noise conditions from activating the receive function.
36
37
TPTXTPTX+
0
TWisted Pair Differential Transmitter Outputs: These lines have pre-distortion drive
capability and are intended to drive terminated twisted pair transmission lines. When the AUI
port is manually selected, the 1OBASE-T outputs are driven to a low power standby state in
which the outputs deliver a balanced high state voltage. However, when the AUI port is
automatically selected, the 10BASE-Toutputs remain active.
NOTE:
7-122
The sense of the controiler interface pins will change, depending on the controiler selected.
MOTOROLA ANALOG IC DEVICE DATA
MC68160
Table 1. Pin Function Description (continued)
Pin(s)
Symbol
Type
Name/Function
OSCILLATOR AND FREQUENCY MULTIPLIER
12
MFILT
C
Frequency Multiplier Filter Connection Point: An extemal resistor capacitor filter must be
attached to this pin.
16
XI
I/C
CMOS
Oscillator Inverter Input and Crystal Connection Point: When connected for crystal
oscillator operation, the frequency of the clock which appears at TCLK is half that of the
crystal oscillator. As an option, instead of connecting to a crystal, XI may be driven from an
external 20 MHz CMOS compatible clock generator.
17
X2
O/C
Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the
connection of an extemal crystal and capacitor. It must be left unconnected if XI is driven by
an external CMOS Clock generator.
CMOS
MODE SELECT
3
4
5
CSO
CSI
CS2
I
TTL
Mode Select: The logic states applied to these pins select the appropriate interface for the
desired IEEE-802.3 controller or enable the standby mode. When the standby mode is
selected, the MC68160 power supply current is greatly reduced. Additionally, in the standby
mode, all of the controller inputs and outputs are driven to the high impedance state.
6
LOOP
I
TTL
Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be
Manchester encoded and then looped back through the Manchester decoder, appearing at
the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP)
or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI
port transmits data from the controller while diagnostic loopback is selected. Likewise, the
controller interface receives data neither from the TP nor the AUI receivers while in this
mode. The polarity fault detection and link integrity functions are not inhibited by the
diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair
port is selected, and TPSOEL is driven to the low logic state, a collision detect pulse is
delivered following each transmission to simulate the twisted pair SOE test.
9
APORT
I
TTL
Automatic Port Selection Enable: When high, MC68160 will automatically select the TP or
AUI port based on the presence or absence of valid link beats or frames at the TP receive
input. If the AUI port Is automatically selected, the MC68160 will continue to produce link
pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry
for the new port to resume normal operation. The power consumption is minimized in the
circuitry associated with the unselected port.
27
TPSOEL
I
TTL
Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the
internal TP collision detect circuitry after each transmit operation to the TP media. This
function provides a simulated collision to as much of the MC68160 collision detect circuitry
as possible without affecting the attached twisted pair channel. A normal SOE test results in
a high logic state at the CLSN controller interface pin which begins 6 to 16-bit times after the
last transition of a transmitted signal and continues for 5 to 15-bit times. (When the AUI port
is selected, SOE test signals are generated by the coaxial cable transceiver and delivered to
the controller via the MC68160 ACX+I- receive inputs)
28
TPFULDL
I
TTL
Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit
and receive operation on the twisted pair port without an indicated collision. This pin is not 10
be asserted with LOOP as a test mode is enabled that disrupts normal operation.
29
TPAPCE
I
TTL
Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic
polarity correction is enabled, and MC68160 will internally correct for a polarity fault on the
receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is
indicated on TPPLR.
46
TPEN
I/O
TTL
(TTUCMOS)
Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the
AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is
manually selected, the MC68160 will not produce link pulses for the TP port.
If APORT is high, TPEN is an output which will indicate which port has been automatically
selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink
10 mA in the low output state and source 10 mA in the high output state. (See Pin 9
Description.)
Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to
resume normal operation. The power consumption is minimized in the cirCUitry aSSOCiated
with the unselected port. In the standby mode, this pin is driven to the high impedance state.
MOTOROLA ANALOG Ie DEVICE DATA
7-123
•
MC68160
Table 1. Pin Function Description (continued)
Pln(s)
Symbol
Type
Name/Functlon
0
TraI'lsmH Status LED Driver Output: This pin indicates the transmit status of the currently
selected TP or AUI port. When there is no transmit activity detected, an internal pull-up takes
this pin to its normal off (high) state. When transmit activity is detected, the LED driver tums .
on. In its on state; TXLED flashes the'LED by driving low at approximately 10 Hz at a 50"k
duty cycle. In the standby mode, this output is driven to the high impedance state.
STATUS INDICATOR
40
TXLED
TTLJCMOS
"
41
RXLED
0
TTLJQMOS
42
CLLED
0
TTLJCMOS
43
TPLIL
0
TTLJCMOS
44
TPPLR
0
'TTLJCMOS
II
45
TPJABB
0
TTLJCMOS
Receive Status LED Driver Output: This pin indicates the receive status of the currently
selected TP or AUI port. When there is no receive activity detected, an internal pull-up takes
this pin to Its normal off (high) state. When receive activity is detected, the LED driver turns
on. In its on state, RXLED flashes the LED by driving low at approximately 10Hz at a 50%
duty cycle. In the standby mode, this output 'is driven til the high impedance state.
COllision Status LED Driver Output: This pin indicates the collision status of the currently
selected TP or AUI port. When there is no colliSion activity detected, an internal pull-up takes
this pin to its normal off (high) state. When collision activity is detected, the LED driver turns
on., In its on state, CLLED flashes the LED by driving low at approximately 10Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate
good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity
fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port
is selected. In the standby mode, this output is also driven to the high impedance state.
Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the
Twisted Pair Receiver Inputs (TPRX+, TPRX-) are reversed, TPPLR will be driven to the low
logic state to Indicate the fault. TPPLR remains low when the MC68160 has automatically
corrected for the reversed wires. If the twisted pair link integrity tests fail, this output will be
driven to,the high logic state. When the AUI mode is selected this output is driven to the high
Impedance state, In the standby mode, this output is also driven to the high impedance state.
Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the
TPTX+/- outputs. (Jabber condition also causes CLLED to be driven alternately to the high
and low output levels). TPJABB is driven to the low output state when no jabber condition is
present.When the AUl"mode is selected this output is driven to the high impedance state. In
the standby mode, this output is also driven to the high impedance state.
POWER SUPPLY AND GROUND
10
VDDDIV
Frequency D,lvlder Supply Pin
11
Frequency Multiplier Supply and Ground Pins
13
VDDFM
GNDFM
14
15
GNDVCO
VDDVCO
Voltage Controlled Osciliator Ground and Supply Pins
20
GNDSUB
SubStrate Ground Pin
7
8
18
19
VDDDIG'
GNDDIG
VDDDIG
GNDDIG
Digital Supply and Ground Pins
SO'
VDDANA
GNDANA
Analog Supply and ,Ground Pins
GNDPWR
VDDPWR
VDDPWR
GNDPWR
Power Supply and Ground Pins
GNDCTL
Controller Interface Ground Pin
33
34
35
38
39
47
NOTE:
7-124
Power and ground pins are not connected internally. Failure to connect externally may cause maHunction or damage to the IC.
MOTOROLA ANALOG IC DEVICE DATA
MC68160
Table 2. Controller Interface Selection
Motorola
Transceiver
MC68160
(EES'fT")
Motorola
Controller2
MC68360
(QUICCT")
Intel
Controllers
82586, 82590,
82593, 82596
CSO
CS1
CS2
1
1
0
0
FuJltau
Controllers
86950 (EtherstarT")
86960 (NICETM)
National
Controllers
8390, 83C690,
839328 (SONICTM)
0
1
1
0
0
0
0
0
Pin
Pin
Sense
Pin
Sense
Pin
Sense
Pin
Sense
TCLK
TX
TENA
RCLK
RX
RENA
CLSN
LOOp1
TCLK
TX
TENA
RCLK
RX
RENA
CLSN
N.A.
High
TXC
TXD
RTS
RXC
RXD
CRS
COT
LPBK
Low
TCKN
TXD
TEN
RCN
RXD
XCD
XCOL
LBC
Low
TXC
TXD
TXE
RXC
RXD
CRS
COL
LPBK
High
High
High
High
High
High
High
High
High
Low
Low
High
Low
Low
Low
High
High
Low
High
High
Low
High
High
High
High
High
High
High
High
NOTES: 1. Atthough LOOP input is not ordinarily classlfed as a controller pin, ~ is included in this table because Its sense varies according to the controller used.
2. The Motorola controller Interface contained In the MC68360 (QUICCT") is compatible with the AMD 7990 (LANCer") and 79C900 (ILACC™) controllers.
3. The pin sense is shown from the perspective of the ldentHied controller pin.
Table 3. Controller Independent Mode Selection
Pin
Standby Mode
Reserved
Reserved
Reserved
CSO
CS1
CS2
1
1
1
0
1
1
1
0
1
0
0
1
NOTE: In standby mode, the MC6S160 consumes less power supply current than in any other
mode. Additionally, in the standby mode, all of the controller inputs and outputs are
driven to the high impedance state. When the standby mode is deasserted, an internal
reset pulse of approximately 6.0 liS duration is generated.
Following a period of operation in the standby mode, the time required to insure stable
data reception is approximately 100 ms.
Figure 2. Applications Block Diagram
d~
"
e
,J'f"'~
w
... ' ,.
~
TENA
LAN
Controller
~
-
,...
~;
TCLK
TX
ATX+
,.
•
,
,
,
RX
,-
.-
RENA
CLSN
. . ,.
~
ATX+
ATX-
-""
ARX+
~
Pulse
Transformers
ARXACX+
.,
;
~
ACX-
-
ARX+
ARX-
D8-15
Connector
ACX+
ACX-
,
,
.
"
TPTX+ ...
TPTX+ ...
~
.*
TPTX~
i
"
"
.'
MOTOROLA ANALOG IC DEVICE DATA
ATX-
:">*
"~
RCLK
,
TPRX+
TPRX-
Filters
and
Pulse
Transformers
TPTXTPRX+
RJ-45
Connector
TPRX-
7-125
•
MC68160
ELECTRICAL CHARACTERISTl~S
MAXIMUM RATINGS
Symbol
Min
Max
Unit
Storage Temperature Range
Tstg
-65
150
°C
Power Supply Voltage Range
Analog
Digital
VDDA
VDDD
-
7.0
7.0
V
V
-0.5
VDD+0.5
V
-0.5
6.0
-6.0
6.0
Characteristic
..
Voltage on any TIL compatible Input'pin with
respect to Ground
Voltage on TPRX, ARX, or ACX input pins with
respect to Ground
Differential Voltage on TPRX, ARX, or ACX Input
Pins
VDIFF
V
NOTE: Stresses In excess 01 the Absolute Maximum Ratings can cause permanent damage to the
device. Functional operation 01 the device is not implied at these or any other conditions In
excess 01 those Indicated In the operation sections of this data sheet. Exposure to Absolute
Maximum Ratings conditions lor extended periods can adversely affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Min
Max
VDD
4.75
5.25
V
-
50
mV
Power Supply Impulse Noise (Either Polarity)
-
100
mV
Ambient Operating Temperature Range
TA
0
70
°C
ARXlACX Input Differential Rise and Fall Time (see Figure 39)
t260
2.0
10
ns
ARX Pair Idle Time after Transmission (see Figura 39)
t265
8.0
-
j.IS
Power Supply Voltage Range
•
Power Supply Ripple (20 kHz to 100 kHz)
Unit
ESD
Although protection circuitry has bean designed Into this device, proper precautions sh6uld be taken to avoid exposure to electrostatic discharge
(ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD-susceptibillty
testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance 1500 Q capacltance100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold, presented here was obtained by using
the circuit parameters contained in this speCification. ESD threshold VOltage Is designed to 1.0 kV Human Body Model.
=
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended
ambient operating temperature and power supply voltage ranges.)
Characteristic
Symbol
Teet Conditions
-
-
POWER SUPPLY
Undervoltage Shutdown Threshold
Power Supply Current
IDD
--
Standby Mode
7-126
-
-
-
4.4
V
145
200
5.0
mA
-
MOTOROLA ANALOG IC DEVICE DATA
MC68160
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum limits apply
over the recommended ambient operating temperature and power supply voltage ranges.)
I
Characteristic
I
Symbol
I
Test Conditions
Min
Max
-
0.8
Unit
TTL COMPATIBLE INPUTS
TTL Compatible Input Voltage
Low State
High State
Input Current TTL Compatible Input Pins (Note 1)
Input Current TENA TTL Compatible Input Pin:
with Pull-Down Resistor
IIH
IlL
with Pull-Down Resistor removed in Standby Mode
VIL(TTL)
VIH(TTL)
OV 25 ns.
4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair.
5. If a positive differential pulse occurs on either the AUI receive data or collision pair> 175 ns, end of frame is assumed and squelch circuitry is turned on.
Figure 39. ARXlACX Timing
ARX+/ACX+/-
Differential
Input Voltage
MOTOROLA ANALOG IC DEVICE DATA
J-f
+17SmV
- - - - -17SmV
t261/ t262
7-141
MC68160
Figure 40. ARXlACX Timing
BitolZ
I
BitU
I
BitW
BitV
I
BitX
I BitY I BitZ
ARX+/-I
ACX+/Differential
Input Voltage
1+---- t267 ---~
1.5V
1.5V
RCLK
II
\'-----
RX
I BitOlZ I
BW
I Bit V I
BitU
I BitX
BitY
I
BitZ
I
FUNCTIONAL DESCRIPTION
Introduction
The MC68160(EEST) was designed to perform the
physical connection to the Ethernet media. This is done
through two separate media dependent interfaces and aSIA
interface. The media dependent interfaces are the
Attachment Unit Interface(AUI) and the 10BASE-T Twisted
Pair(TP) port. The SIA interface is compatible with most
industry controllers and selected by three mode control pins.
Chip status is indicated by the condition of 6 status indicator
pins. All but one are open collector outputs.
If the EEST isn't receiving data, the controller may initiate
transmission. NRZ data from the communications controller
SIA interface is encoded by the MC68160 into Manchester
Code in preparation for transmission on the media. The data
is then applied to either the AUI or TP port. If the data was
transmitted using the 10BASE-T port, this data is also
looped back to the receive data interface SIA pins
connected to the controller. This allows detection of a
collision condition in the event that another station on the
media attempted transmission at the same time. After the
entire data frame has been transmitted, the EEST must
force the media idle signal. The idle signal frees the media
for other stations that have deferred transmission. If no
other transmissions are required the link enters an idle
state. During this idle state the 10BASE-T transmitter
issues idle pulses which communicates to the receiver
connected to the other side that the link is valid. If the
7-142
transmitter connected at the other end begins transmission,
the EEST will assert a receive enable signal, and forward
the received data to the controller.
Upon reception of data at the 10BASE-T port, the data is
screened for proper sequence and pulse width requirements.
If the preamble of the received frame meets the
requirements, the PLL locks onto the 64-bit preamble and
begins to decode the Manchester Code to NRZ code. This
code is then presented to the communications controller at
the receive data pins at the SIA interface. If data is received
at the AUI port, it is sent directly to the communications
controller via the SIA interface.
Data Transmission
To have properly encoded transmit data, the communications controller must be synchronized to TCLK.
Transmission to the 10BASE-T or AUI media occurs when
TENA is asserted and data is applied to the TX pin. Finally, to
signify transmission, the TXLED in will cycle on and off at a
100 ms period. Data transmission for EEST is accomplished
either over the 10BASE-T port or the AUI port. Both
connections to the media are made with industry standard
media interface components. The 10BASE-T interface
requires a filter and transformer, the AUI interface requires
only a transformer. The filter for the 1OBASE-T transmit
circuit will have to be chosen for each application.
MOTOROLA ANALOG IC DEVICE DATA
MC68160
If after approximately 40 ms after a TP or AUI transmission
has begun, the EEST is still transmitting, the TPJABB pin will
assert to signify a jabber condition. Also, the CLLED pin will
transition high and low alternately with a 100 ms period. The
transmit circuitry is, however, unaffected by the jabber
condition, so the communications controller has the
responsibility of monitoring and stopping transmission.
When transmission is complete, the transmit circuitry will
begin the end of transmit and decay to idle responses
necessary to meet requirements of the 802.3 standard for the
TP and AUI port.
Data Reception
Other than the case of being in Loop Back mode, data
reception to the RX pin of the EEST is initiated by signaling at
the RX+/- or AUI ARX+/- pins. If at the TP port, the data is
screened for validity by checking for sequence and pulse
width requirements, then passed to the decode and receive
circuitry. The RENA pin asserts and the data and
corresponding clock is passed to the communications
controller. After the frame has been transmitted, the
MC68160 detects the ending transmission and negates
RENA. If at the AUI port, the data is checked for proper pulse
width requirements before being passed to the decode
circuitry. If the data pulses are longer than at least 20 ns,
RENA gets asserted and the frame is decoded to RX with
and accompanying RCLK output.
Collision
Collision is the occurrence of simultaneous transmit
activity by two or more stations on the network. In the event of
collision, the data transfer paths are unaffected. If the
MC68160 is in the twisted pair mode, collision is detect by
simultaneous receive and transmit activity. If in the AUI
mode, collision is detected by activity on the ACX+/- pins. In
either case, if collision is detected, the CLSN pin will assert to
notify the communications controller.
MOTOROLA ANALOG IC DEVICE DATA
Jabber
The EEST has a jabber timer to detect the jabber condition.
In the event that the transmitting station continues to transmit
beyond the allowable transmit time, a jabber timer (40 ms) will
expire and assert the TPJABB pin to alert the communications
controller of the situation. The TPJABB pin can source or sink
up to 10 mA, and so, is capable of driving a status LED. In the
AUI mode, the pin is driven to high impedance since the
transceiver connected to the AUI port must alert the
communications controller of the jabber condition.
Full Duplex
A feature unique to the MC68160 is the Full Duplex mode.
In this mode the EEST is capable of transmitting and
receiving simultaneously. Collision conditions are not
announced and internal loop back is disabled. The remainder
of the EEST functionality remains unchanged from the
non-Full Duplex mode. Full Duplex mode is enabled by
asserting the TPFULDL pin.
Auto Port Selection
If the APORT pin is asserted, the MC68160 will
automatically select the TP or AUI port depending on the
presence of valid link beats or frames at the TP RX+/- pins. If
the AUI port is automatically selected by another transmitting
station or by setting TPEN low, the TP transmit port of the
EEST continues to transmit link beats to keep the link active.
Auto Polarity Selection
If the RX+ and the RX- wires happen to get reversed, the
MC68160 has the ability to automatically reverse the pins
intemally so that the received data is valid. In addition, an open
collector status pin (TPPLR) is driven low to indicate the fault.
In the AUI or reset mode this pin presents a high impedance.
Loop Back Mode
To test the transmit and receive circuitry without disturbing
the connected network, the EEST has a Loop Back mode.
Loop Back mode routes transmit data and clock to the
receive data and clock pins using as much of the transmit and
receive cirCUitry as possible. This gives a test of the
MC68160 Manchester encode and decode function.
7-143
MC68160
APPLICATIONS INFORMATION
Selection of Crystal and External Components
Accuracy of frequency and stability over temperature are
the main determinants of crystal choice. Specifications for a
.
suitable crystal are tabulated below:
·Frequency
20. > C5)
7-144
MOTOROLA ANALOG IC DEVICE DATA
Figure 41, Typical Application Diagram
3:
a
Voo
A
:u
o
~
»
z
»
TCLK . " Transmit Clock.
COMMUNICATIONS
CONTROLLER
6
MC68360
TENA :... Transmit Enable
:... Transmit Data
CLSN :.. Collision Int
RCLK
R NA
(;
~
::s
o
m
c
~
»
AM0(7990J79C900)
Intel (825" -86190193J96)
Fujitsu (869" -50160)
National (8390183C90183932B)
+S,QV
LE06
R33
330n
TX
Ii)
c
m
n~
_TPEN" TP En""lo_
l\iE05
R8
330n
l\iED4~lEo3 ~lE02 ~
Rg
330n
R11
330n
R13
330n
f
01
R14
330n
~
~
Valor (PT3877. PT3882. FU 012. FU (86)
TOKO (PM01. PM02. PMOS)
Pulse Engineenng (pE-55433. PE-65434. PE-65424)
i
~
1
!ll.
MC68160FB
RJ45
--==8...
Y=!
o
~
.....
TPFULOL
TPSOa 27
Power Supply
Bypassing
h,,,,
~
III
1O~FH
eoncraft (LAX-ET30')
Pulse Engineering (pE-64"'*)
Communications Controller Selection
h""
cso
CS1
CS2
802.3 Communication Controtler
Motorola MC68360. AMD 7990 & 79C900
Intel 8258S. 62500. 82593. 82596
Fujitsu MB86960. MB66960
O.1~F
0-
R4
39n
R5
D~ 39n
AS
National 8390, 83C690, 839328
Standby Low Current Mode
0'1~fl39n
D2
-::-
!
+12V
Valor (LT600'ILT603')
TOKO (Q3OALQ'-1AA3)
TPFULDL
TPAPCE
10~FH
s::
i"'L-----ji;>VCC
A7
39n
-::-
AUI
1. For SuilBble CryslBl (Xl) see applications text on previous page.
2. Oecoupling capacitors should be placed as close to supply pins as possible.
t;
_~JI
___________
-L
®
MOTOROLA
Quad EIA-485 Line Drivers
with Three.;.State Outputs
The Motorola MC75172B/174B Quad Line drivers are differential high
speed drivers designed to comply with the EIA-485 Standard. Features
include three-state outputs, thermal shutdown, and output current limiting in
both directions. These devices also comply with EIA-422-A, and CCITT
Recommendations V.ll and X.27.
The MC75172B/1748 are optimized for balanced multipoint bus
transmission at rates in excess of 10 MBPS. The outputs feature wide
common mode voltage range, making them suitable for party line
applications in noisy environments. The current limit and thermal shutdown
features protect the devices from line fault conditions. These devices offer
optimum performance when used with the MC75173 and MC75175 line
receivers.
Both devices are available in 16-pin plastic DIP and 20-pin wide body
surface mount packages.
• Meets EIA-485 Standard for Party Line Operation
MC75172B
MC75174B
QUAD EIA-485 LINE DRIVERS
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
PLASTIC PACKAGE
CASE 648
• Meets EIA-422-A and CCITT Recommendations V.ll and X.27
II
• Operating Ambient Temperature: -4O°C to +85°C
DWSUFFIX
PLASTIC PACKAGE
CASE751D
(SO-20L)
• High Impedance Outputs
• Common Mode Output Voltage Range: -7 to 12 V
• Positive and Negative Current Limiting
• Transmission Rates in Excess of 10 MBPS .
• Thermal Shutdown at 150°C Junction Temperature, (±20°C)
• Single 5.0 V Supply
• Pin Compatible with TI SN7517214 and NS ~9617214
• Interchangeable with MC3487 and AM26LS31 for EIA-422-A
Applications
ORDERING INFORMATION
Device
Operating
Temperature Range
MC75172BDW
MC75174BDW
Package
So-20L
TA = -40° to +85°C
MC75174BP
So-20L
Plastic DIP
PIN CONNECTIONS
MC75172B
MC75174B
OW Package
7-146
OW Package
MOTOROLA ANALOG IC DEVICE .DATA
MC75172B MC75174B
MAXIMUM RATINGS
Rating
Power Supply Voltage
Symbol
Value
VCC
-0.5, +7.0
Vdc
Yin
+7.0
Vdc
Input Voltage (Data, Enable)
Input Current (Data, Enable)
Unit
lin
-24
mA
Applied Output Voltage, when in 3-State Condition
(VCC=5.0V)
Vza
-10,+14
Vdc
Applied Output Voltage, when VCC = 0 V
Vzb
±14
10
Self-Umiting
-
Tstg
-65,+150
'c
Output Current
Storage Temperature
Devices should not be operated at these limits. The "Recommended Operating Condijions" table provides
for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
VCC
+4.75
+5.0
+5.25
Vdc
Input Voltage (All Inputs)
Yin
0
-
VCC
Vdc
Output Voltage in 3-State Condition, or when VCC = 0 V
Vcm
-7.0
-
+12
Vdc
Output Current (Normal data transmission)
10
-65
-
+65
mA
Operating Ambient Temperature (see text)
EIA-485
EIA-422
TA
-40
0
-
+85
+85
'c
Alilimijs are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (-40'C '" TA '" 85°C, 4.75 V '" VCC '" 5.25 V, unless otherwise noted.)
Characteristic
Output Voltage
Single-Ended Voltage
10=0
High @ 10 = -33 mA
Low@ 10 = +33 mA
Differential Voltage
Open Circuit (10 = 0)
RL = 54 n (Figure 1)
Change in Differential', RL = 54 n (Figure 1)
Differential Voltage, RL = 100 n (Figure 1)
Change in Differential', RL = 100 n (Figure 1)
Differential Voltage, -7.0 V'" Vcm '" 12 V (Figure 2)
Change in Differential', -7.0 V'" Vem '" 12 V (Figure 2)
Offset Voltage, RL = 54 n (Figure 1)
Change in Offset', RL = 54 n (Figure 1)
Output Current (Each Output)
Power Off Leakage, VCC = 0, -7.0 V '" Vo '" 12 V
Leakage in 3-State Mode, -7.0 V '" Vo '" 12 V
Short Circuit Current to Ground
Short Circuit Current, -7.0 V '" Vo '" 12 V
Symbol
Min
Typ
Max
Vo
VOH
VOL
0
-
-
6.0
-
4.0
1.6
-
IVODll
IVOD2 I
1.5
1.5
3.4
2.3
6.0
5.0
-
5.0
2.2
5.0
200
Unit
Vdc
-
mVdc
Vdc
mVdc
Vde
mVdc
Vdc
mVde
laVOD21
IVOD2A I
IaVOD2A I
IVOD3 I
laVOD31
VOS
lavosl
1.5
-
5.0
2.9
5.0
10(off)
10Z
-50
-50
0
0
+50
+50
jlA
10SR
lOS
-150
-250
-
+150
+250
mA
-
-
-
-
200
5.0
200
-
200
'Vin switched from 0.8 to 2.0 V.
Typical values determined at 25'C ambient and 5.0 V supply.
MOTOROLA ANALOG IC DEVICE DATA
7-147
MC75172B MC75174B
ELECTRICAL CHARACTERISTICS (-40°C " TA" 85°C, 4.75 V" VCC " 5.25 V, unless otherwise noted.)
Characteristics
Inputs
low level Voltage (Pins 4 & 12, MC75174B only)
low level Voltage (All Other Pins)
High level Voltage (All Inputs)
=2.7 V (All Inputs)
=0.5 V (All Inputs)
Clamp Voltage (All Inputs, lin =-18 mAl
Current @ Vin
Current @ Vin
Thermal Shutdown Junction Temperature
Power Supply Current (Outputs Open, VCC
Outputs Enable
Outputs Disabled
=5.25 V)
Symbol
Min
Vll(A)
Vll(B)
VIH
0
0
2.0
-
Typ
-
Max
Vdc
0.7
0.8
Vec
0.2
-15
20
IIH
III
-100
VIK
-1.5
-
-
Tjts
-
+150
-
ICC
UnH
-
ItA
Vdc
°c
mA
-
60
30
70
40
Min
Typ
Max
-
23
18
30
30
-
15
17
25
25
-
19
25
TIMING CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Characteristics
Propagation Delay - Input to Single-ended Output (Figure 3)
Output low-to-High
Output High-to-low
•
Propagation Delay -Input to Differential Output (Figure 4)
Input low-to-High
Input High-to-low
Differential Output Transition lime (Figure 4)
Skew liming
ItplHD - tPHlD I for Each Driver
Max - Min tplHD Within a Package
Max - Min tpHlD Within a Package
Enable liming
Single-ended Outputs (Figure 5)
Enable to Active High Output
Enable to Active low Output
Active High to Disable (using Enable)
Active low to Disable (using Enable)
Enable to Active High Output (MC75172B only)
Enable to Active low Output (MC75172B only)
Active High to Disable (using Enable, MC75172B only)
Active low to Disable (using Enable, MC75172B only)
Differential Outputs (Figure 6)
Enable to Active Output
Enable to Active Output (MC75172B only)
Enable to 3-Sta.te Output
Enable to 3-State Output (MC75172B only)
7-148
Symbol
tPlH
tpHl
tPlH(D)
tpHl(D)
tdr, Idf
tsK1
tSK2
tSK3
-
-
Unit
ns
ns
0.2
1.5
1.5
-
ns
ns
-
ns
tpZH(E)
tpZl(E)
tPHZ(E)
tPLZ(E)
tpZH(E)
tPZl(E)
tpHZ(E)
tPLZ(E)
tpZD(E)
tpZD(E)
tPDZ(E)
tPDZ(E)
-
-
-
-
-
-
-
48
20
35
30
58
28
38
36
60
30
45
50
70
35
50
50
47
56
32
40
-
ns
-
MOTOROLA ANALOG IC DEVICE DATA
MC75172B MC75174B
Figure 1. VDD Measurement
Figure 2. Common Mode Test
t
Vin
(0.8 or 2.0 V)
Vin
(0.8 or 2.0 V)
VOD3
375
-=-+ VCM=12to-7.0V
58
I
375
~
Figure 3. Propagation Delay, Single-Ended Outputs
3.0 V
1.5V
OV
tpHL
270
Output
:r
3.0 V
3.0V
15PF
VOL
IpLH
VOH
3.0V
3.0 V
Figure 4. Propagation Delay, Differential Outputs
3.0 V
1.SV
OV
tPHLD
1.5V
=4.6V
let!
NOTES: 1. S.G. set to: f .. 1.0 MHz; duty cycle = 50%; to tf... 5.0 ns.
2. tSK1 = ItPLHD - tpHLD I for each driver.
3. tSK2 computed by subtracting the shortest tpLHD from the longest tpLHD of the 4 drivers wKhln a package.
4. tSK3 computed by subtracting the shortest tpHLD from the longest tpHLD of the 4 drivers within a package.
MOTOROLA ANALOG IC DEVICE DATA
7-149
•
MC75172B MC75174B.
. Figure 5. Enable Timing, Single-Ended Outputs
,_.------------..3.0 V
Vee
1.SV
'----OV
r------------------,,.~--VOH
Vout
O.SV
2.3V
Vee
Vee
3.0V
1.SV
l.SV
Oor3.0V
SOPF
II
r
ov
tPZL(E)
Vout
tPLZ(E)
Vout
2.3V
O.SV
vOL
':-
Figure 6. Enable Timing, Differential Outputs
3.0V
50pF
1.SV
t
OV
tpDZE
vr
1.SV
0
':-
Active
NOTES: 1. S.G. sel 10: f " 1.0 MHz; duly cycle = 50%; If, If, " 5.0 ns.
2. Vin is inverted for 'Eila6Te measurements.
7-150
MOTOROLA ANALOG IC DEVICE DATA
MC75172B MC75174B
Figure 7. Single-Ended Output Voltage
versus Output Sink Current
Figure 8. Single-Ended Output Voltage
versus Temperature
2.0
2.0
~
w 1.5
C!l
!:i
-
V
g~
IOL =20.0mA
to; 1.5
..:.
~
0.5
o
-j
o
10
4.75
I
20
30
40
50
IOL, OUTPUT CURRENT (mA)
60
1.0
-40
70
Figure 9. Single-Ended Output Voltage
versus Output Source Current
5.0
w
~
~
4.0
IOH = -20.0 mA
~
w
C!l
;:;
3.75
~
to;
a.
to;
3.5
'-'
VCC = 4.75 V
3.0
0
±
~ 2.0
1.0
IOH - -27.8 mA
±
~
TA=25'C
o
-10
-20
-30
-40
-50
IOH, OUTPUT CURRENT (mA)
-60
VCC=4.75V
3.25
-70
-40
Figure 11. Output Differential Voltage
versus Load Current
~
S
3.
-
O~" ~
"
§ 2.OVCC = 5.0 V -./
~
a:
w
tI: 1.0
c
c
~
r0
0
20
40
60
TAo AMBIENTTEMPERATURE (OC)
85
~ 4.0
I'....
;:;
~
-20
Figure 12. Output Differential Voltage
versus Temperature
4. 0
w
C!l
85
J.
4.0
.... VCC=5.00V
g
a
20
40
60
0
TA, AMBIENT TEMPERATURE ('C)
Vee = 5.25 V
;:;
a.
-20
'" VCC '" 5.25 V
Figure 10. Single-Ended Output
Voltage versus Temperature
C!l
I::>
r--r---
1.25
4.75V '" VCC '" 5.25 V _
TA = 25'C
~
10L =21.8mA
§
§
..:.
--
I--
C!l
~
to; 1.0
~
-- :------I-
>
W 1.75
o
tll
;:;
;::::::r-r-- r-- :::--r--::: t _VCC = 5.25 V
VCC=4.75 V
I
-
~~~ ~ol Voo
I
10
I
I
20
30
40
50
10, OUTPUT CURRENT (mA)
MOTOROLA ANALOG IC DEVICE DATA
r--
~
~
3!
ic
tl:
TA = 25°C
c
~
60
70
3.0
10-20.0mA
10 = 27.8 mA
-
2.0
1.0
o
1
I-- 0.8 or ~o
2.0V 1
L
-40
-20
Voo
I
VCC=4.75V -
T
0
20
40
60
TAo AMBIENT TEMPERATURE (OC)
85
7-151
MC75172B MC75174B
Figure 13. Output Leakage Current
versus Output Voltage
Figure 14. Output Leakage Current
versus Temperature
2.0
«
~
20
«
1.0
!z
w
:E
i3
w
15
~
t-
i
10
:::>
5.0
~
0
0
~
~-1.0
Ri-l0
TA=25'e_
En = low, En = High -
I
-2.0
-7.0
I
><
(
-3.0
1.0
5.0
9.0
Vz, APPLIED OUTPUT VOLTAGE (V)
-20
-40
12
1
o
60
85
~
(
-25
-0.5
/"
Normally low Output
a:
a:
y
~ -10
<.:>
7-152
0
20
40
TA, AMBIENT TEMPERATURE ('C)
~ 90
Enable( (Driver
Pins
Inputs
!l!
-20
-20
150
~-5.0
~
r-
IrVee=o~
Figure 16. Short Circuit Current
versus Common Mode Voltage
5.0
~ -15
En = low, En = High
S? -15
r-
Figure 15. Input Current
versus Input Voltage
«::l
-
Voul=7.0V
US -5.0
-'
S?
II
-
Voul=+12 V
<.:>
w
:::::J
30
<.:>
t-
I
I
I
~
0
5-30
V
Ii::
4.75 .. vee .. 5.25 V
TA=25'e
~
I
en. -90
.J
1l
0.5
1.5
2.5
3.5
Yin, INPUT VOlTAGE (V)
4.5
5.5
-150
-7.0
-3.0
/
..I
I
r
Normally High Output
TA = 25'e
4.75 .. vee .. 5.25 V
1.0
5.0
9.0
VZ, APPLIED OUTPUT VOLTAGE (V)
12
MOTOROLA ANALOG IC DEVICE DATA
MC75172B MC75174B
APPLICATIONS INFORMATION
Description
The MC75172B and MC75174B are differential line drivers
designed to comply with EIA-485 Standard (April 1983) for
use in balanced digital multipoint systems containing multiple
drivers. The drivers also comply with EIA-422-A and CCITT
Recommendations V.ll and X.27. The drivers meet the
EIA-485 requirement for protection from damage in the event
that two or more drivers attempt to transmit data
simultaneoulsy on the same cable. Data rates in excess of 10
MBPS are possible, depending on the cable length and cable
characteristics. A single power supply, 5.0 V, ±5%, is required
at a nominal current of 60 mA, plus load currents.
Outputs
Each output (when active) will be a low or a high voltage,
which depends on the input state and the load current (see
Table 1,2 and Figures 7 to 10). The graphs apply to each
driver, regardless of how many other drivers within the
package are supplying load current.
Table 1 MC75172B Truth Table
Enables
Outputs
Data Input
EN
EN
Y
Z
H
L
H
L
X
H
H
X
X
L
X
X
L
L
H
H
L
H
L
Z
L
H
L
H
Z
Table 2 MC75174B Truth Table
Outputs
Data Input
Enable
y
Z
H
L
H
H
L
H
L
Z
L
H
Z
X
H = Logic high, L = Logic low, X = Irrelevant, Z = High impedance
The two outputs of a driver are always complementary. A
"high" output can only source current out, while a "low" output
can only sink current (except for short circuit current - see
Figure 16).
The outputs will be in the high impedance mode when:
a) the Enable inputs are set according to Table 1 or 2;
b) VCC is less than 1.5 V;
c) the junction temperature exceeds the trip point of the
thermal shutdown circuit (see below). When in this
condition, the output's source and sink capability are
shut off, and only leakage currents will flow (see
Figures 13, 14). Disabled outputs may be taken to any
voltage between -7.0 V and 12 V without damage.
MOTOROLA ANALOG IC DEVICE DATA
The drivers are protected from short circuits by two
methods:
a) Current limiting is provided at each output, in both the
source and sink direction, for shorts to any voltage
within the range of 12V to-7.0V, with respect to circuit
ground (see Figure 16). The short circuit current will flow
until the fault is removed, or until the thermal shutdown
circuit activates (see below). The current limiting circuit
has a negative temperature coefficient and requires no
resetting upon removal of the fault condition.
b) A thermal shutdown circuit disables the outputs when
the junction temperature reaches 150°C, ±20°C. The
thermal shutdown circuit has a hysteresis of ~ 12°C to
prevent oscillations. When this circuit activates, the
output stage of each driver is put into the high
impedance mode, thereby shutting off the output
currents. The remainder of the internal circuitry remains
biased. The outputs will become active once again as
the IC cools down.
Driver Inputs
The driver inputs determine the state of the outputs in
accordance with Tables 1 and 2. The driver inputs have a
nominal threshold of 1.2 V, and their voltage must be kept
within the range of 0 V to VCC for proper operation. If the
voltage is taken more than 0.5 V below ground, excessive
currents will flow, and proper operation of the drivers will be
affected. An open pin is equivalent to a logic high, but good
design practices dictate that inputs should never be left open.
The characteristics of the driver inputs are shown in Figure
15. This graph is not affected by the state of the Enable pins.
Enable Logic
Each driver's outputs are active when the Enable inputs
(Pins 4 and 12) are true according to Tables 1 and 2.
The Enable inputs have a nominal threshold of 1.2 V and
their voltage must be kept within the range of 0 V to VCC for
proper operation. If the voltage is taken more than 0.5 V
below ground, excessive currents will flow, and proper
operation of the drivers will be affected. An open pin is
equivalent to a logic high, but good design practices dictate
that inputs should never be left open. The Enable input
characteristics are shown in Figure 15.
Operating Temperature Range
The minimum ambient operating temperature is listed as
-40°C to meet EIA-485 specifications, and O°C to meet
EIA-422-A specifications. The higher VOD required by
EIA-422-A is the reason for the narrower temperature range.
7-153
•
MC75172B MC75174B
The maximum ambient operating temperature (applicable
to both EIA-485 and EIA-422-A) is listed as 85°C. However,
a lower ambient may be required depending on system use
(i.e. specifically how many drivers within a package are used)
and at what current levels they are operating. The maximum
power which may be dissipated within the package is
determined by:
.
TJmax-TA
PO max = -"'R~'--!..!
aJA
where:
reducing the load current, reducing the ambient temperature,
and/or providing a heat sink.
System Requirements
EIA-485 requires each driver to be capable of transmitting
data differentially to at least 32 unit loads, plus an equivalent
DC termination resistance of 60n, over a common mode
voltage of -7.0 to 12 V. A unit load (U.L.), as defined by
EIA-485, is shown in Figure 17.
Figure 17. Unit Load Definition
RaJA = package thermal resistance (typical
70°C/Wfor the DIP package, 85°CIW for SOIC
package);
TJmax = max. operating junction
temperature, and
TA = ambient temperature.
Since the thermal shutdown feature has a trip point of
150°C, ±20°C, TJmax is selected to be 130°C. The power
dissipated within the package is calculated from:
PO
where:
II
= {[(VCC - VOH) • IOHl + VOL • IOL)) each driver
+ (VCC·ICC)
VCC = the supply voltage;
VOH, VOL are measured or estimated from
Figures 7 to 10;
ICC = the quiescent power supply current
(typical 60 mAl.
As indicated in the equation, the first term (in brackets)
must be calculated and summed for each of the four drivers,
while the last term is common to the entire package.
Example 1: TA = 25°C, IOL = IOH = 55 mA for each driver,
VCC = 5.0 V, DIP package. How many drivers per package
can be used?
Maximum allowable power dissipation is:
Since the power supply current of 60 mA dissipates
300 mW, that leaves 1.2 W (1.5 W - 0.3 W) for the drivers.
From Figures 7 and 9, VOL = 1.75 V, and VOH =3.85 V. The
power dissipated in each driver is:
{(5.0 - 3.85) • 0.055} + (1.75 • 0.055) = 160 mW.
Since each driver dissipates 160 mW, the four drivers per
package could be used in this application
Example2:TA=85°C, IOL=27.8mA, IOH=20mAforeach
driver, Vce = 5.0 V; SOIC package. How many drivers per
package can be used?
Maximum allowable power dissipation is:
PO max =
130°C - 85°C
85 0 C/W
=
0.53 W
Since the power supply current of 60 mA dissipates
300 mW, that leaves 230 mW (530 mW - 300 mW) for the
drivers. From Figures 8 and 10 (adjusted for VCC = 5.0 V),
VOL = 1.38 V, and VOH = 4.27 V. The power dissipated in
each driver is:
{(5.0 - 4.27) • 0.020} + (1.38 • 0.0278) = 53 mW
Reprinted from EIA-485, Electronic Industries Association,
Washington,DC.
A load current within the shaded regions represents an
impedance of less than one U.L., while a load current of a
magnitude outside the shaded area is greater than one U.L.
A system's total load is the sum of the unit load equivalents
of each receiver's input current, and each disabled driver's
output leakage current. The 60n termination resistance
mentioned above allows for two 120n terminating resistors.
Using the EIA-485 requirements (worst case limits), and
the graphs of Figures 7 and 9, it can be determined that the
maximum current an MC751728 or MC751748 driver will
source or sink is =65 mAo
System Example
An example of a typical EIA-485 system is shown in
Figure 18. In this example, it is assumed each receiver's input
characteristics correspond to 1.0 U.L. as defined in Figure 17.
Each "off' driver, with a maximum leakage of ±50 ~ over the
common mode range, presents a load of =0.06 U.L. The
total load for the active driver is therefore 8.3 unit loads, plus
the parallel combination of the two terminating resistors
(60n). It is up to the system software to control the driver
Enable pins to ensure that only one driver is active at any
time.
Termination Resistors
Transmission line theory states that, in order to preserve
the shape and integrity of a waveform traveling along a cable,
the cable must be terminated in an impedance equal to its
characteristic impedance. In a system such as that depicted
in Figure 18, in which data can travel in both directions, both
physical ends of the cable must be terminated. Stubs, leading
to each receiver and driver, should be as short as possible.
Leaving off the terminations will generally result in
reflections which can have amplitudes of several volts above
VCC or below ground. These overshoots and undershoots
can disrupt the driver and/or receiver operation, create false
data, and in some cases damage components on the bus.
Since each driver dissipates 53 mW, the use of all four
drivers in a package would be marginal. Options include
7-154
MOTOROLA:ANALOG IC DEVICE DATA
MC75172B MC75174B
Figure 18. Typical EIA-485 System
m
TTL
TTL
5 "oW' drivers (@ 0.06 U.L. each),
+8 receivers (@ 1.0 U.L. each) = 8.3 Unit Loads
AT = 120 Q at each end of the cable.
120Q
Twisted
Pair
TTL
TTL
TTL
•
TTL
TTL
TTL
TTL TTL
NOTES: 1. Tenninaling resistors RT must be located at the physical ends of the cable.
2. Stubs should be as short as possible.
3. Circuit ground of all drivers and receivers must be connected via a dedicated wire within the cable.
Do not rely on chassis ground or power line ground.
MOTOROLA ANALOG IC DEVICE DATA
7-155
MC75172B MC75174B
Comparing System Requirements
Characteristic
EIA-422-A
EIA-485
V.11 and X.27
GENERATOR (DRIVER)
Output Impedance (Note 1)
Open Circuit Voltage
Differential
Single-Ended
lout
VOCD
VOCS
Loaded Differential Voltage
VOD
Differential Vo~age Balance
aVOD
Not Specified
<100 0
50101000
1.5t06.0V
<6.0V
';;6.0V
';;6.0V
.;; 6.0 V, w/3.9 ko, Load
.;; 6.0 V, w/3.9 kCl, Load
1.5 to 5.0 V, w/54 0 load
.. 2.0 V or .. 0.5
VOCD, w/l00 0 load
.. 2.0 V or .. 0.5 VOCD,
wl100 0 load
< 200 mV
.;;400mV
<400mV
Not Specified
Output Common Mode Range
VCM
-7.0to+12V
Not Specified
Offset Vo~ge
VOS
-1.0 < VOS < 3.0V
';;3.0V
';;3.0V
<200mV
.;; 400 mV
<400mV
.;; 250 rnA for-7.0 to
12 V
.;; 150 mA to ground
.;; 150 mA to ground
Offset Vo~ge Balance
Short Circuit Current
aVos
lOS
Leakage Current (VCC = 0)
10LK
Not Specified
.;; 100!1A to -0.25 V
thru 6.0 V
.;; l00!1A to ± 0.25 V
Output RiselFail Time (Note 2)
t r, tf
.;; 0.3 TB, w/54 011150 pF
load
.;; 0.1 TBor.;; 20 ns,
w/l000 load
';;0.1 TBor.;; 20ns,
w/l00oload
Vth
±300mV
RECEIVER
II
Input Sensitivity
±200mV
± 200 mV
Input Bias Voltage
Vbias
';;3.0V
';;3.0V
';;3.0V
Input Common Mode Range
Vcm
-7.0 to 12 V
-7.0 to 7.0V
-7.0t07.0V
Dynamic Input Impedance
Rin
Spec number of U.L.
.. 4kD
.. 4kD
NOTES: I. Compliance with V.II and X.27 (Blue book) output impedance requires extemal resistors in series with the outputs of the MC75172B and MC75174B.
2. T B = Bittime.
Additional Information
Copies of the EIA Recommendations (EIA-485 and EIA-422-A) can be obtained from the Electronics Industries Association,
Washington, D.C. (202-457-4966). Copies of the CCITT Recommendations (V.11 and X.27) can be obtained from the United
States Department of Commerce,Springfield, VA (703-487-4600).
7-156
MOTOROLA ANALOG Ie DEVICE DATA
®
MOTOROLA
SN75175
Quad EIA-485 Line Receiver
The Motorola SN75175 is a monolithic quad differential line receiver with
three-state outputs. It is designed specifically to meet the requirements of
EIA-485, EIA-422A123A Standards and CCITT recommendations.
The device is optimized for balanced multipoint bus transmission at rates
up to 10 megabits per second. It also features high input impedance, input
hysteresis for increased noise immunity, and input sensitivity of ±200 mV
over a common mode input voltage range of -12 V to 12 V. The SN75175 is
designed for optimum performance when used with the SN75172 or
SN75174 quad differential line drivers.
• Meets EIA Standards EIA-422A and EIA-423A, EIA-485
QUAD EIA-485
LINE RECEIVER WITH
THREE-STATE OUTPUTS
SEMICONDUCTOR
TECHNICAL DATA
• Meets CCITT Recommendations V.1 0, V.11, X.26, and X.27
• Designed for Multipoint Transmission on Long Bus Lines in Noisy
Environments
NSUFFIX
PLASTIC PACKAGE
CASE 648
• 3-State Outputs
• Common-Mode Input Voltage Range ... -12 V to 12 V
•
• Input Sensitivity ... ±200 mV
• Input Hysteresis ... 50 mV Typ
• High Input Impedance ... 1 EIA-485 Unit Load
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
• Operates from Single 5.0 V Supply
• Lower Power Requirements
• Plug-In Replacement for MC3486
This device contains 174 active transistors.
PIN CONNECTIONS
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vee
Power Supply Voltage
VCC
7.0
Vdc
Input Common Mode Voltage
VICM
±25
Vdc
VID
±25
Vdc
Three-State Control Input Voltage
VI
7.0
Vdc
Control
Output Sink Current
10
50
rnA
Output
Tstg
-65 to +150
°c
Input Differential Voltage
Storage Temperature
}
Output
In~um
A
3-State
Output
B
Ale
3-State
Control
e
BIO
Output
Operating Junction Temperature
NOTE:
TJ
+150
°c
D
ESD data available upon request.
Gnd
(Top View)
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Value
Un"
VCC
4.75 to 5.25
Vdc
TA
Oto+70
°c
Input Common Mode Voltage Range
VICM
-12to+12
Vdc
Input Differential Voltage Range
VIDR
-12 to +12
Vdc
Power Supply Voltage
Operating Ambient Temperature
MOTOROLA ANALOG IC DEVICE DATA
ORDERING INFORMATION
Device
SN75175N
SN75175D
Operating
Temperature Range
TA = 0 to +70°C
Package
Plastic DIP
S0-16
7-157
SN75175
ELECTRICAL CHARACTERISTICS (Unless otherwise noted; minimum and maximum limits apply over recommended temperature and
power supply voltage ranges. Typical values are forTA = 25°C, VCC 5.0 V, and VICM 0 V, Note 1.)
=
Characteristic
Differential Input Threshold Voltage (Note 2)
(-12 V .. VICM .. 12 V, VIH = 2.0 V)
(10 = -0.4 mA, VOH ~ 2.7 V)
(10 = 16 mA, VOL" 0.5 V)
Input Hysteresis
•
=
Symbol
Min
Typ
Max
Unit
V
VTH(D)
-
-
VT+-VT-
Input Une Current (Differential Inputs)
(Unmeasured Input at 0 V, Note 3)
(VI = 12V)
(VI =-7.0 V)
II
Input Resistance (Note 4)
ri
-
0.2
-0.2
50
-
mV
mA
-
-
1.0
-0.8
1 Unit
Load
-
-
Input Balance and Output Level (Note 3)
(-12 V .. VICM .. 12 V, VIH = 2.0 V)
(10 = -0.4 mA, VID = 0.2 V)
(10 = 8.0 mA, VID = -0.2 V)
(10 = 16 mA, VID = -0.2 V)
VOH
VOL
VOL
2.7
Input Voltage - High Logic State (Three-State Control)
VIH
2.0
Input Voltage - Low Logic State (Three-8tate Control)
VIL
-
Input Current - Higli L~gic State (Three-State Control)
(VIH=2.7V)
(VIH=5.5V)
IIH
Input Current - Low Logic State (Three-State Control)
(VIL = 0.4 V)
IlL
Input Clamp Diode Voltage (Three-State Control)
(11K = -18 rnA)
VIK
Output Third State Leakage current
(VI(D) = 3.0 V, VIL = 0.8 V, Va = 0.4 V)
(VI (D) = -3.0 V, VIL = 0.8 V, Va = 2.4 V)
10Z
Output Short-Circuit Current (Note 5)
(VI(D) = 3.0 V, VIH = 2,.0 V, Va = 0 V)
Power Supply Current (VIL = 0 V) (All Inputs Grounded)
V
-
-
-
-
0.45
0.5
-
V
ItA
-
-
V
0.8
20
100
-
-
-100
itA
-
-
-1.5
V
-
-
-20
20
lOS
-15
-
-as
mA
ICC
-
-
70
rnA
ItA
NOTES: 1. All cwrents into device pins are shown as positive, out of device pins are negative. All voltages referenced to ground unless otherwise noted.
2. Differential input threshold voltage and guaranteed output levels are done simultaneously for worst case.
3. Refer to EIA-485 for exact conditions. Input balance and guaranteed output levels are done simultaneously for worst case.
4. Input resistance should be derived from input line current specifications and is shown for reference only. See EIA-485 and input line current
specifications for more specific input resistance information.
5. Only one output at a time should be shorted.
SWITCHING CHARACTERISTICS (Unless otherwise noted, VCC = 5.0 V and TA = 25°C.)
Characteristic
Propagation Delay Time - Differential Inputs to Output
Output High to Low
OutP\lt LOVY to High
Propagation Delay Time - Three-State Control to Output
Output Low to Third State
Output High to Third State
Output Third State to High
Output Third State to Low
7-158
Symbol
Min
Typ
Max
tPHL(D)
tPLH(D)
-
25
25
35
35
-
16
19
11
11
35
35
30
30
Unit
ns
tpLZ
tpHZ
tpZH
tpZL
-
-
ns
MOTOROLA ANALOG IC DEVICE DATA
SN75175
FUNCTION TABLE (EACH RECEIVER)
Differential Inputs
3-State
Control
Output
y
VID~2.0V
'-{).2 V 1.0
2.0
1.0
o
o
-140
~O
-100
-20
0
20
60
100
1
VID =0.2 V
Load = 8.0 kn to Gnd
TA = 25°C
140
o
0.5
1.0
1.5
2.0
2.5
3.0
VI. 3-STATE CONTROL VOLTAGE (V)
VID, DIFFERENTIAL INPUT VOLTAGE (mV)
Figure 5. High Level Output Voltage
versus Output Current
~
UJ
CJ
!:i
5.0
4.0
t:":""'\
§2
I-
:::>
5
~
3.0
0
1--\~ VCC = 5.25 V
~
1
jjj 2.0
-'
:J:
1.0
-9
o
o
4.0
§2
3.5
~O
3.0
2.5
'-'
~
ffi
/
~
~.::, 0.1
-9
-10
-15
-20
-25
-30
-35
IOH, HIGH LEVEL OUTPUT CURRENT (rnA)
V
0.2
o
-40
~
o
/
Vcc = 5.0 V
f-TA = 25°C
5.0
10
15
20
25
30
35
40
IOL, LOW LEVEL OUTPUT CURRENT (rnA)
Figure 8. Low Level Output Voltage
versus Temperature
Figure 7. High Level Output VoHage
versus Temperature
5.0
~
UJ 4.5
~
UJ
/
./
0.3
0
.~ ~
-5.0
§2
-'
~'\.
:f:
,
./
~
!j 0.4
5
4.0
Figure 6. Low Level Output Voltage
versus Out I)ut Current
0.5
UJ
!5
~ ~ VCC = 5.0 V
~
VCC=4.75V~ ~
-'
UJ
~
VID=0.2V
TA = 25°C f - -
3.5
0.5
~
UJ
~ 0.4
~
~
0.3
~
0.2
~
-'
0.1
§
VCC=5.0V _
IOH = 400 IJA
2.0
r--
1.5
:E 1.0
:f:
-9 0.5
.::,
-9
o
10
20
30
40
50
60
70
80
TA, FREE AIR TEMPERATURE (0C)
MOTOROLA ANALOG IC DEVICE DATA
90
100
o
VCC=5.0V _
f--IOL= 16 rnA
o
10
20
30
40
50
60
70
80
lA, FREE AIR TEMPERATURE (0C)
90
100
7-161
®
MOTOROLA
ULN2068
Quad 1.5 A Sinking High
Current Switch
The ULN2068 is a high-voltage, high-current quad Darlington switch array
designed for high current loads, both resistive and reactive, up to 300 W.
It is intended for interfacing between low level (TTL, DTL, LS and 5.0 V
CMOS) logic families and peripheral loads such as relays, solenoids, de and
stepping motors, multiplexer LED and incandescent displays, heaters, or other
high voltage, high current loads.
The Motorola ULN2068 is specified with minimum guaranteed breakdown
of 50 V and is 100% tested for safe area using an inductive load. It includes
integral transient suppression diodes. Use of a predriver stage reduces inpl.\t
current while still allowing the device to switch 1.5 Amps.
It is supplied in an improved 1&-Pin plastic DIP package with heat sink
contact tabs (Pins 4, 5,12 and 13). A copper alloy lead frame allows maximu
power dissipation using standard cooling techniques. The use of the co
tab lead frame facilitates attachment of a DIP heat sink while permi
use of standard layout and mounting practices.
• TTL, DTL, LS, CMOS Compatible Inputs
QUAD 1.5 A
DARLINGTON SWITCH
• 1.5 A Maximum Output Current
II
BSUFFIX
PLASTIC PACKAGE
CASE 648C
• Low Input Current
• Internal Freewheeling Clamp Diodes
• 100% Inductive Load Tested
• Heat Tab Copper Alloy Lead Frame for I
=
MAXIMUM RATINGS (TA 25'C and rati
package, unless otherwise noted)
PIN CONNECTIONS
Rating
Unit
Output Voltage
V
Input Voltage (Note 1)
15
V
Supply Voltage
10
V
Collector Current (Note 2)
IC
1.75
A
Input Current (Note 3) .
II
25
mA
Oto+70
Tstg
-55 to +150
'c
'c
'c
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature
150
NOTES: 1. Input voltage referenced to ground.
2. Allowable output conditions shown in Figures 11 and 12.
3. May be limited by max input voltage.
Partial Schematic
Vs
.--.......- -......OC
.....*-+-OK
Bo-.,.....WIr--f
ORDERING INFORMATION·
Device
ULN2068B
Operating
Temperature Range
Package
Plastic DIP
'Other options of this ULN2060/2070 series are available
for volume applications. Contact your local Motorola Sales
Representative.
7-162
MOTORQLA ANALoG IC DEVICE DATA
ULN2068
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
Characteristic
Symbol
Output Leakage Current (Figure 1)
(VCE=50V)
(VCE = 50 V, TA = 70°C)
Min
Typ
Max
Unit
ICEX
100
500
Collector-Emitter Saturation Voltage (Figure 2)
V
VCE(sat)
1.13
1.25
1.40
1.60
(lC=5oomA}
(IC=750mA
V· =24V)
(lC= 1.0A
In·
(IC= 1.25A
Input Current - On Condition (Figure 4)
(VI=2.4V)
(VI = 3.75 V)
I'(on)
Input Voltage - On Condition (Figure 5)
(VCE = 2.0 V, IC = 1.5 A)
VI(on)
mA
0.25
1.0
V
2.4
Inductive Load Test (Figure 3)
(VS = 5.5 V, VCC = 24.5 V,
tPW=4.0ms)
mV
100
Supply Current (Figure 8)
(IC = 500 mA, Yin = 2.4 V, Vs = 5.5 V)
6.0
mA
Turn-On Delay Time
(50% E, to 50% EO)
1.0
Turn-Ofl Delay Time
(50% E, to 50% EO)
4.0
Clamp Diode Leakage Current (Figure 6)
(VR = 50 V)
(VR = 50 V, TA = 70°C)
100
Clamp Diode Forward Voltage (Figure 7)
(IF = 1.0A)
(IF = 1.5A)
1.75
2.0
Ils
50
V
Figure 2.
Open
Open
1
Figure 4.
Figure 3.
Vs
.....------0--0
vee
200
70MH
Open
I ,14m.
V~
1
Vout
~I--""--o Open
2
INPUT CURRENT (mA)
4.0
Figure 12. TA = 70°C wlStaver V-8
Heat Sink (37.SoCIW)
f
t
Device limit
~\
I'"
"- ""'r-....
..........
r
...........
~ r-!.
",4
L
o
o
7-164
.............
r-!.
Number of
outputs conducting
simul~aneourlY
20
40
60
DUTY CYCLE (%)
80
"-
'" ""'"
Il.cr:
Wcr:
a 1.0
;:cr:
r--- r-
r-:: t- r--
DeviceLimij
"" :s: 1.5
r--.... ~~
~
-
I---
100
~~
I
.Y~ 0.5
...
~mberof
l---"
..........
4"'-
t'.....
1
.........
r-.... 3 ~
r--..... r-- r--
.
I-outputs conducting
--r-
r-~
r---
simultaneously
o
o
20
40
80
DUTY CYCLE ('10)
80
100
MOTOROLA ANALOG.IC DEVICE DATA
ULN2068
Figure 13. TA = 70°C w/Staver V-7
Heat Sink (27.5°CIW)
•
Device Limit
"
~4
~ '"-
outputs conducting
simuitaneory
20
--- ----
"'- ....... ............ .......... 2
"'- r-.... K ....... -....-.
~mberof
Lo
o
Figure 14. TA
40
60
1
= 50°C w/o Heat Sink
'"' ~ 1.51--+....-+-~+..r--+~-+--+-+-~1-""'il
L5!z
Il. W
~~
!i¥
a 1.0 1--+--'
;;:ex:
9f2
;;!frl
!Jgu 0.5
80
80
DUTY CYCLE ('!o)
100
DUTY CYCLE ('!o)
Figure 16. TA = 50°C wlStaver V-7
Heat Sink (27.5°CIW)
'"' ~ 1.5 I--+--+--~~~~
'"' ~1.5
Il.
Il.
L5!zW
~~
!i¥
a 1.0 1--+--+-+---'
i5~
;;i@
9
g 0.5 I---+--+-+--rt-
u
°0~~-~2~0-~-4~0-~~~--'---8~0---'-~100·
DUTY CYCLE ('!o)
MOTOROLA ANALOG IC DEVICE DATA
f' Device Limtt
"
L5!zW
wex:
...Jex:
!li!
a 1.0
;;:ex:
~§
/
All Types
<.>
a: 400
J
a:
a:
=>
a: 400
~
8
/
-'
-'
200
.9
....V
a
/
All Types
<.>
:;
§w
a
1
~ 600
/
!z
w
8
Figure 9. Output Current versus
Input Current
/
/
200
.9
/
./
0.5
1.0
1.5
VCE(sat). SATURATION VOLTAGE (V)
2.0
./
V
200
,/
400
600
liN. INPUT CURRENT (1lA)
800
Input Characteristics
Figure 11. ULN28041nput Current
versus Input Voltage
Figure 10. ULN28031nput Current
versus Input Voltage
2.0
2.0
,../'
/
.......
a
2.0
/'
2.5
...- ,../'
,,/
3.0
1 1.5
V
!z
w
a:
a:
V
=>
<.> 1.0
~
~
~
3.5
4.0
4.5
VIN. INPUT VOLTAGE (V)
5.0
5.5
6.0
0.5
l..--'
V
a
5.0
6.0
7.0
--
----
8.0
9.0
10
VIN. INPUT VOLTAGE (V)
11
12
13
Figure 12. Representative Schematic Diagrams
1/8 ULN2803
1/8 ULN2804
t--...--;-o Pin 10
I
I
I
L __
* _______ _
MOTOROLA ANALOG IC DEVICE DATA
t--*--I--o
I
I
I
L ___
Pin 10
* ______ _
7-169
II
7-170
MOTOROLA ANALOG IC DEVICE DATA
Communication Circuits
In Brief ...
RF
Radio communication has greatly expanded its scope in the
past several years. Once dominated by public safety radio, the
30 to 1000 MHz spectrum is now packed with personal and low
cost business radio systems. The vast majority of this
equipment uses FM or FSK modulation and is targeted at short
range applications. From mobile phones and VHF marine
radios to garage door openers and radio controlled toys, these
new systems have become a part of our lifestyle. Motorola
Analog has focused on this technology, adding a wide array of
new products including complete receivers processed in our
exclusive 3.0 GHz MOSAIC® 1.5 process. New surface mount
packages for high density assembly are available for all of
these products, as well as a growing family of supporting
application notes and development kits.
Telephone & Voice/Data
Traditionally, an office environment has utilized two
distinctly separate wired communications systems:
telecommunications and data communications. Each had its
individual hardware components complement, and each
required its own independent transmission line system: twisted
wire pairs for Telecom and relatively high priced coaxial cable
for Datacom. But times have changed. Today, Telecom and
Datacom coexist comfortably on inexpensive twisted wire pairs
and use a significant number of components in common. This
has led to the development and enhancement of PBX (Private
Branch Exchanges) to the point where the long heralded
"office of the future," with simultaneous voice and data
communications capability at each station, is no longer of the
future at all. The capability is here today!
Motorola Semiconductor serves a wide range of
requirements for the voice/data marketplace. We offer both
CMOS and Analog technologies, each to its best advantage,
to upgrade the conventional analog voice systems and
establish new capabilities in digital communications. Early
products, such as the solid-state single-i:hip crosspoint
switch, the more recent monolithic Subscriber-LoopInterface Circuit (SLlC) , a single-i:hip Codee/Filter (MonoCircuit), the Universal Digital Loop Transceivers (UDLT),
basic rate ISDN (Integrated Services Digital NetWOrk), and
singl8-i:hip telephone circuits are just a few examples of
Motorola leadership in the voice/data area.
MOTOROLA ANALOG IC DEVICE DATA
Page
RF Communications ..................................... 8-2
RF Front End IC's .................................... 8-2
Wideband IFs ........................................ 8-2
Wideband Single Conversion Receivers ................. 8-2
Narrowband Single Conversion Receivers ............... 8-2
Narrowband Dual Conversion Receivers ................. 8-3
Universal Cordless Phone Subsystem ICs ............... 8-3
Transmitters ........... : ............................. 8-3
Balanced Modulator/Demodulator ....................... 8-4
Infrared Transceiver .................................. 8-4
Telecommunications .................................... 8-11
Subscriber Loop Interiace Circuit ...................... 8-11
PBX Archnecture (Analog Transmission) ................ 8-12
PCM Mono-Circuits .............................. 8-12
Dual Tone Multiple Frequency Receiver .............. 8-15
ISDN VOice/Data Circuits ............................. 8-15
Integrated Services Digital Network ................. 8-15
Second Generation U-Interiace Transceivers ........ 8-16
Second Generation SIT-Interiace Transceivers ....... 8-16
Dual Data Link Controller .......................... 8-17
VoicelData Communication (Digital Transmission) ........ 8-18
Universal Digital Loop Transceiver .................. 8-18
ISDN Universal Digital Loop Transceiver II ........... 8-19
Electronic Telephone Circuit ........................... 8-19
Tone Ringers ....................................... 8-20
Speech Networks ................................... 8-21
Speakerphones ..................................... 8-25
VOice Switched Speakerphone Circuit ............... 8-25
Voice Switched Speakerphone with
I!Processor Interface ............................. 8-27
Voice Switched Speakerphone Circuit ............... 8-28
Telephone Line Interface and Speakerphone Circuit ... 8-29
Family of Speakerphone ICs ....................... 8-30
Telephone Accessory Circuits ......................... 8-31
Audio Amplifier ................................... 8-31
Current Mode Switching Regulator .................. 8-31
300 Baud FSK Modems ........................... 8-32
ADPCM Transcoder .............................. 8-32
Calling Line Identification (CLIO) Receiver ........... 8-33
CVSD Modulator/Demodulator ..................... 8-34
Summary of Bipolar Telecommunications Circuits ..... 8-35
Phase-Locked Loop Components ........................ 8-38
PLL Frequency Synthesizers .......................... 8-38
Phase-Locked Loop Functions ........................ 8-39
Package Overview ..................................... 8-41
Device Listing and Related Literature ...................... 8-43
8-1
II
:
RF Communications
Table 1. RF Front End ICs
Low Noise Amplifier
Mixer
Gain
(dB)
Noise
Figura
(dB)
IIP3
(dBm)
P1dB
(dBm)
Voltage
Cant
Osc
VCC
(V)
ICC
(mA)
Suffix!
Packaga
-15
7
16
--3 to +15
-10
-
2.7 to 6.5
7.7
011751,
01751 A,
FTBl976
-15
±3
12
--3 to +21
3
Yes
2.710 6.5
13
D1751B,
FTBl976
Device
Gain
(dB)
Noise
Figura
(dB)
IIP3
(dBm)
P1dB
(dBm)
MC13141
17
1.8
-5
MC13142
17
1.8
-5
MC13143
-
-
-
-
±3
12
--3 to +21
3
-
1.8to 6.5
1
01751
MC13144
13to
19
1.4
-1
-7
-
-
-
-
-
1.8t06.5
2t09
01751
NOTES:
All devices operate over a wide range of RF input and IF frequencies, from dc to 2.0 GHz.
Typical performance shown at 900 MHz.
Table 2. Wideband (FMlFSK) IFs
IF
Mute
RSSI
Max
Data
Rate
V
2.0Mb
Wldeband Data IF, includes
datashaper
P/648,
D1751B
10Mb
Video Speed FM IF
D1751B
Devica
Vcc
ICC
Sensitivity
(Typ)
MC13055
3-12 V
25mA
20l!V
40 MHz
V
MC13155
3-6 V
7.0mA
100l!V
250 MHz
-
Notes
Suffix!
Package
Table 3. Wideband Single Conversion Receivers - VHF
Device
VCC
ICC
Sensitivity
(Typ)
RF
Input
IF
Mute
MC3356
3-9 V
25mA
30l!V
200 MHz
10.7MHz
V
MC13156
2-6 V
5.0mA
2.01!V
500 MHz
21.4MHz
-
MC1315B
2-6 V
6.0mA
MC13159
2.7-5
V
5.5mA
RSSI
Max
Data
Rata
Notes
V
500 kb
Includes front end mixer/L.O.
PI73B,
DW1751 0
CT-2 FM/Demodulator
DWI751E,
FBlB73
FM IF/Demodulator with
split IF for DECT
FTBlB73
>1.2Mb
600 MHz
FM IF for PHS
500 kb
Suffix!
Package
DTB/948F
Table 4. Narrowband Single Conversion Receivers - VHF
Device
Vec
ICC
12dB
SINAD
Sensitivity
(Typ)
MC3357
4-8 V
5.0mA
5.01!V
MC3359
4-9 V
7.0mA
2.01!V
MC3371
2-6 V
6.0mA
RF
Input
IF
Mute
RSSI
Max
Data
Rate
45 MHz
455 kHz
V
-
>4.Bkb
60 MHz
V
Notea
>4.8kb
MC3372
MC13150
Ceramic Quad
Detector/Resonator
P/648,
D1751B
Scan output option
P1707,
DW1751 0
RSSI
P/64B,
01751B,
DTB/94BF
RSSI, Ceramic Quad
Detector/Resonator
3-6 V
I.BmA
1.01!V
500 MHz
V
>9.6kb
Suffix!
Package
Coilless Detector wHh
Adjustable Bandwidth
FTBlB73,
FTAl977
110
dB
8-2
MOTOROLA ANALOG IC DEVICE DATA
RF Communications (continued)
Table 5. Narrowband Dual Conversion Receivers - FM/FSK - VHF
Device
VCC
ICC
12dB
SINAD
Sensitivity
(Typ)
MC3362
2-7 V
3.0mA
0.71lV
4.0mA
OAIlV
MC3363
MC3335
0.71lV
MC13135
1.01lV
RF
Input
IF1
180
MHz
10.7
MHz
IF2
(Limiter
In)
Mute
RSSI
455 kHz
-
V
Data
Rate
>4.8
kb
f---
V
f---
-
MC13136
Notes
Suffix!
Package
Includes buffered
VCOoutput
Pf724,
DWf751E
Includes RF
amp/mute
DWf751F
Low cost version
DWf751D,
Pf738
Voltage buffered
RSSI, LC Quad
Detector
DWf751E,
Pf724
Voltage Buffered
RSSI, Ceramic
Quad Detector
Table 6. Universal Cordless Phone Subsystem ICs
Dual
Conversion
Receiver
Universal
DualPLL
Compander
and Audio
Interface
Voice
Scrambler
Low
Battery
Detect
Programmable
Rx. T x Trim Gain
and LBO Voltage
Reference
Suffix!
Package
Device
VCC
ICC
MC13109
2.0-5.5 V
Active Mode
6.7 rnA
Inactive Mode
40llA
V
V
V
-
1
-
FB/848B,
FTN932
MC13110
2.7-5.5 V
Active Mode
8.2 rnA
Inactive Mode
60 I!A
V
V
V
V
2
V
FBl848B
MC13111
2.7-5.5 V
Active Mode
8.2 rnA
Inactive Mode
60 I!A
V
V
V
-
2
V
FBl848B
Table 7. Transmitters - AMlFM/FSK
MaxRF
Freq
Out.
Max
Mod
Freq
Device
VCC
ICC
Pout
MC2833
3-8 V
lOrnA
-30dBm
to
+10dBm
150 MHz
50kHz
MC13175
2-5 V
40mA
8.0dBm
500 MHz
5.0 MHz
MC13176
MOTOROLA ANALOG IC DEVICE DATA
1.0GHz
Notes
Suffix!
Package
FM transmitter. Includes two frequency
multiplier/amplifier transistors
P/648,
Df751B
AM/FM transmitter. Single frequency PLL
fout = 8 x fref, includes power down function
D/751B
fout = 32 x fref, includes power down function
&-3
II
Table 8. Balanced Modulator/Demodulator
Device
MC1496
vec
ICC
3-5 V
10mA
Suffix!
Package
Function
General purpose balanced modulator/demodulator for AM, SSB, FM detection
with Carrier Balance >50 dB
P/646,
Dn51A
Table 9. Infrared Transceiver
Device
Vec
ICC
12dB
SINAD
Sensitivity
(Typ)
MC13173
3-5 V
6.5mA
5.01LV
Max
IF Freq
Carr Det
RSSI
Data
Rate
V
V
200kb
10.7
MHz
Notes
Includes Single Frequency
PLL for Tx Carrier and Rx La
Suffix!
Package
FTBl873
Universal Cordless Telephohe Subsystem IC
MC13109FB, FTA
TA
=-20° to +85°C, Case 848B, 932
The MC13109 integrates several ofthe functions ryquired
for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space
reqUirements, and external adjustments. It is designed for use
in both the handset and the base.
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna1lnput
to Audio Output 80 MHz Maximum Carrier Frequency
,
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic
Discriminator
• Compander
I
- Expandor Includes Mute, Digital Volume Control and
Speaker Driver
- Compressor Includes Mute, ALC and Limiter
• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with No
External Switches
- Universal Design for Domestic and Foreign CT~ 1
Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector,
and 14-Bit Programmable Counter and 2nd LO with
12-Bit Counter
- Transmit Section Contains Phase Detector and 14-8it
Counter
- MPU Clock Output Eliminates Need for MPU Crystal
• Supply Voltage Monitor
- Externally Adjustable Trip Point
• 2.0 to 5.5 V Operation with One-Third the Power
Consumption of Competing Devices
Ir-----------------~----------~,
'
"
.
.
" I
I
Rx In ---+---1"'1
I
1
1
1
Rx
Out
Carrier __---+--<
Detect
Tx Out __--+-~==~J
Tx VCO -----+---1
________
IL _ _L::::=.J.o!--.::.......I
Low
1-'--_1__/<--_
.. Battery
~
________
~
L....";;";";;';";"'...J
___
_ ____
~
~
Indicator
MOTOROLA ANALOG IC DEVICE DATA
Universal Cordless Telephone Subsystem IC with Scrambler
MC13110FB
TA
=-40° to +85°C, Case 848B
The MC1311 0 integrates several of the functions required
for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space
requirements, and extemal adjustments. It is designed for use
in both the handset and the base.
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna In to
Audio Out 80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic
Discriminator
• Compander
- Expandor Includes Mute, Digital Volume Control,
Speaker Driver, 3.5 kHz Low Pass Filter, and
Programmable Gain Block
- Compressor Includes Mute, 3.5 kHz Low Pass Filter,
Limiter, and Programmable Gain Block
• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with New
Extemal Switches
- Universal Design for Domestic and Foreign CT-1
Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector,
and 14--Bit Programmable Counter and 2nd.LO with
12-Bit Counter
- Transmit Section Contains Phase Detector and 14--Bit
Counter
- MPU Clock Outputs Eliminates Need for MPU Crystal
• Supply Voltage Monitor
- Provides Two Levels of Monitoring with Separate
Outputs
- Separate, Adjustable Trip Points
• Frequency Inversion Scrambler/Descrambler
- Can Be Enabled/Disabled Via MPU Interface
- Programmable Carrier Modulation Frequency
• 2.7 to 5.5 V Operation with One-Third the Power
Consumption of Competing Devices
II
r-------------------------------,I
I
I
I
I
I
I
Rx In -+-----001
I
Rx PO Out
Rx PO In >-;---~""
Rx
Out
+ __-<
Carrier ...
Detect
TxOut ...t---=;~~~J
+----1
Tx VCO ...
I.
I
Low Battery
IL _ _ _ _L:::==....Jo----'
Detect.
______________________
_____
MOTOROLA ANALOG IC DEVICE DATA
I
~
I
~
I
I
Low
.. Battery
Indicator
8-5
Narrowband FM Receiver
ow
MC131351136P,
TA
=-40° to +85°C, Case 724, 751 E
The MC13135 is a full dual conversion receiver with
oscillators, mixers, Limiting IF Amplifier, Quadrature
Discriminator, and ASSI circuitry. It is designed for use in
security systems, cordless phones, and VHF mobile and
portable radios. Its wide operating supply voltage range and
low current make it ideal for battery applications. The
Aeceived Signal Strength Indicator (ASS I) has 65 dB of
dynamic range with a voltage output, and an operational
amplifier is included for a dc buffered output. Also, an
improved mixer third order intercept enables the MC13135 to
accommodate larger input signal levels.
• Complete Dual Conversion Circuitry
• Low Voltage: 2.0 to 6.0 Vdc
• ASSI with Op Amp: 65 dB Aange
• Low Drain Current: 3.5 mA Typical
• Improved First and Second Mixer 3rd Order Intercept
• Detector Output Impedance: 250 Typically
Vee
'f 0•1
24
23
0.Q1
22
I
AFin
4
21
20
360
Audio
Ol!tPut
ASSI
Output
14
13
39k
,
455 kHz
Quad Coil
Taka
7MG-B128Z
MOTOROLA ANALOG IC DEVICE DATA
Narrowband FM Coilless Detector IF Subsystem
MC13150FTA, FTB
TA
=-40° to +85°C, Case 977, 873
The MC13150 is a narrowband FM IF subsystem targeted
at cellular and other analog applications. Excellent high
frequency performance is achieved, with low cost, through
use of Motorola's MOSAIC 1.5™ RF bipolar process. The
MC13150 has an onboard Colpitts VCO for Crystal controlled
second LO in dual conversion receivers. The mixer is a double
balanced configuration with excellent third order intercept. It
is useful to beyond 200 MHz. The IF amplifier is split to
accommodate two low cost cascaded filters. RSSI output is
derived by summing the output of both IF sections. The
quadrature detector is a unique design eliminating the
conventional tunable quadrature coil.
Applications for the MC13150 include cellular, CT-1
900 MHz cordless telephone, data links and other radio
systems utilizing narrowband FM modulation.
• Linear Coilless Detector
• Adjustable Demodulator Bandwidth
• 2.5 to 6.0 Vdc Operation
• Low Drain Current: < 2.0 mA
• Typical Sensitivity of 2.0 J.lV for 12 dB SINAD
• IIP3, Input Third Order Intercept Point of 0 dBm
• RSSI Range of Greater Than 100 dB
• Internal 1.4 kO Terminations for 455 kHz Filters
• Split IF for Improved Filtering and Extended RSSI Range
...------------0 Enable
...----------0 RSSI
Mixer~220n
RSSI
II
1----0 Buffer
Out
1--_-....--0 Detector
Output
1.5 k
:~~20n-=
49.9
220n
V18-V17 = 0;
fIF=455 kHz
-=
MOTOROLA ANALOG IC DEVICE DATA
-=
8-7
Wideband FM IF System
MC13156DW, FB
TA
=-400 to +85°C, Case 751 E, 873
The MC13156 is a wideband FM IF subsystem targeted at
high performance data and analog applications. Excellent
high frequency performance is achieved, with low cost,
through use of Motorola's MOSAIC 1.5™ RF bipolar process.
The MC13156 has an onboard Colpitts VCO for PLL
controlled multichannel operation. The mixer is useful to
beyond 200 MHz and may be used in a differential, balanced,
or single--ended configuration. The IF amplifier is split to
accommodate two low cost cascaded filters. RSSI output is
derived by summing the output of both IF sections. A precision
data shaper has a hold function to preset the shaper for fast
recovery of new data.
Applications for the MC13156 include CT-2, wideband
data links, and other radio systems utilizing GMSK, FSK or FM
modulation.
• 2.0 to 6.0 Vdc Operation
• Typical Sensitivity of 6.0 /lV for 12 dB SINAD
• RSSI Dynamic Range Typically 80 dB
• High Performance Data Shaper for Enhanced CT-2
Operation
• Internal 300 Q and 1.4 kQ Terminations for 10.7 MHz and
455 kHz Filters
• Split IF for Improved Filtering and Extended RSSI Range
0.146 11
r------------.,
I
MC13156
I
I
I
144.455 MHz
RF Input
-=-
II
Carrier
Detect
Ceramic
Filter
RSSI
Output
IOn
10 n
10 n
430
Data Slicer
Hold
10k
VCC
10.7 MHz
Ceramic
Filter
Data
Output
VCC
-=-
100 n
10 n
430
Vee
8-8
MOTOROLA ANALOG IC DEVICI;: DATA
Wideband FM IF Subsystem
MC13158FTB
TA
=-40° to +85°C, Case 873
The MC13158 is a wideband IF subsystem that is designed
for high performance data and analog applications. Excellent
high frequency performance is achieved, with low cost,
through the use of Motorola's MOSAIC 1.5™ RF bipolar
process. The MC13158 has an on-board grounded collector
VCO transistor that may be used with a fundamental or
overtone crystal in single channel operation or with a PLL in
multi-channel operation. The mixer is useful to 500 MHz and
may be used in a balanced differential or single ended
configuration. The IF amplifier is split to accommodate two low
cost cascaded filters. RSSI output is derived by summing the
output of both IF sections. A precision data shaper has an Off
function to shut the output "off' to save current. An enable
control is provided to power down the IC for power
management in battery operated applications.
Mix
In2
Mix
In!
N/C
Applications include DECT, wideband wireless data links
for personal and portable laptop computers and other battery
operated radio systems which utilize GFSK, FSK or FM
modulation.
• Designed for DECT Applications
• 1.8 to 6.0 Vdc Operating Voltage
• Low Power Consumption in Active and Standby Mode
• Greater than 600 kHz Detector Bandwidth
• Data Slicer with Special Off Function
• Enable Function for Power Down of Battery Operated
Systems
• RSSI Dynamic Range of 80 dB Minimum
• Low External Component Count
Osc Osc
Emil Base NlC VEE! Enable
MixOul
VCC!
IFln
DSGnd
IF Dec!
DSOu!
IF Dec2
IFOu!
DS'off"
VCC2
DSln!
Lim In
Lim Lim
Dec! Dec2
MOTOROLA ANALOG Ie DEVICE DATA
Lim Quad N/C Del VEE2
Out
Gain
II
UHF, FMlAM Transmitter
MC131751176D
TA = 0° to +70°C, Case 751B
The MC13175 and MC13176 are one chip FM/AM
transmitter subsystems designed for AM/FM communication
systems operating in the 260 to 470 MHz band covered by
FCC TItle 47; Part 15. They include a Colpitts crystal reference
oscillator, UHF oscillator, +8 (MC13175) or +32 (MC13176)
prescaler, and phase detector forming a versatile PLL system.
Another application is as a local oscillator in a UHF or 900 MHz
receiver. MC13175/176 offer the following features:
• UHF Current Controlled Oscillator
• Use Easily Available 3rd Overtone or Fundamental
Crystals for Reference
•
•
•
•
•
•
•
•
•
Low Number of External Parts Required
Low Operating Supply Voltage (1.8-5 Vdc)
Low Supply Drain Currents
Power Output Adjustable (Up to +10 dBm)
Differential Output for Loop Antenna or Balun
Transformer Networks
Power Down Feature
ASK Modulated by Switching Output "On"f'Off'
MC13175-fo = 8xfref
MC13176-fo =32xfref
AM Modulalor
1.3k
81
II
l00p"r--;;,
MC13176
I
VCC
MC13175
T
n
----;;-,
MC13175-Mp
MC13176-180p
0.821'
"
MC13175
Crystal
3rdOvertone
o.011' MC13176..L Crystal
Fundamental
10MHz
t
1k
I=
Vee
40.0000 MHz
':'
8-10
~
MOTOROLA ANALOG IC DEVICE DATA
Telecommunications
Subscriber Loop Interface Circuit (SLlC)
MC33120/1P, FN
TA -40° to +85°C, Case 738, 776
=
With a guaranteed minimum longitudinal balance of 58 dB,
the MC33120/1 is ideally suited for Central Office applications,
as well as PBXs, and other related equipment. Protection and
sensing components on the two-wire side can be
non-precision while achieving required system performance.
Most BORSHT functions are provided while maintaining low
power consumption, and a cost effective design. Size and
weight reduction over conventional transformer designs
permit a higher density system.
• All Key Parameters Externally Programmable with
Resistors:
• Transmit and Receive Gains
• Transhybrid Loss
•
•
•
•
•
•
•
•
• Return Loss
• DC Loop Current Limit and Battery Feed Resistance
• Longitudinal Impedance
Single and Double Fault Sensing and Protection
Minimum 58 dB Longitudinal Balance (2-wire and 4-wire)
Guaranteed
Digital Hook Status and Fault Outputs
Power Down Input
Loop Start or Ground Start Operation
Size & Weight Reduction Over Conventional Approaches
Available in 20 Pin DIP and 28 Pin PLCC Packages
Battery Voltage: -42 to -58 V (for MC33120),
-21.6 to -42 V (for MC33121)
VDD
(+5.0 V)
VDG
(Dig. God
PDVST2
ST1
VAG
(Ana. Gnc
RXI
TXO
RFO
CF
VOB
________
~
__________________________ JI
(Battery)
• Indicates Trimmed Resistor
MOTOROLA ANALOG IC DEVICE DATA
8-11
II
PBX Architecture (Analog Transmission)
PCM Mono-Circuits Codec-Filters (CMOS LSI)
II
MC145500 Series
MC145554157/64f67
Case 648, 708, 751G, 776
The Mono--circuits perform the digitizing and restoration of
the analog signals. In addition to these important functions,
Motorola's family of pulse-code modulation mono-circuits
also provides the band-limiting filter functions - all on a single
monolithic CMOS chip with extremely low power dissipation.
The Mono-circuits require no external components. They
incorporate the bandpass filter required for anti aliasing and
60 Hz rejection, the A1D-O/A conversion functions for either
U.S. Mu-Law or European A-Law companding formats, the
low-pass filter required for reconstruction smoothing, an
on-board precision voltage reference, and a variety of options
that lend flexibility to circuit implementations. Unique features
of Motorola's Mono-circuit family include wide power supply
range (6.0 to 13 V), selectable on-board voltage reference
(2.5, 3.1, or 3.8 V), and TTL or CMOS 1/0 interface.
Motorola supplies three versions in this series. The
MC145503 and MC145505 are general-purpose devices in
16 pin packages designed to operate in digital telephone or
line card applications. The MC145502 is the full-feature
device that presents all of the options available on the chip.
This device is packaged in a 22 pin DIP and 28 pin chip carrier
package.
Case 648, 7510, 751G, 738
These per channel PCM Codee-Filters perform the voice
digitization and reconstruction as well as the band limiting and
smoothing required for PCM systems. They are designed to
operate in both synchronous and asynchronous applications
and contain an on-chip precision voltage reference. The
MC145554 (Mu-Law) and MC145557 (A-Law) are general
purpose devices that are offered in 16 pin packages. The
MC145564 (Mu-Law) and MC145567 (A-Law), offered in 20
pin packages, add the capability of analog loop-back and
push-pull power amplifiers with adjustable gain.
All four devices include the transmit bandpass and receive
lowpass filters on-chip, as well as active RC pre-filtering and
post-filtering. Fully differential analog circuit design assures
lowest noise. Performance is specified over the extended
temperature range of -40° to +85°C.
These PCM Codee-Filters accept both industry standard
clock formats. They also maintain compatibility with
Motorola's family of MC3419IMC33120 SLiC products.
Txl-----,
TOC
-Tx
+ Tx
TOE
TOO
CCI
VAG
MSI
RSI
Vrel
RxG---'
ROD
RxO
RCE
MC14LC5480P, OW, SO
Case 738, 7510, 940C-02
This 5.0 V, general purpose per channel PCM Codee-Filter
offers selectable Mu-Law or A-Law companding in 20 pin DIP,
SOG and SSOP packages. It performs the voice digitization
and reconstruction as well as the band limiting and smoothing
required for PCM systems. It is designed to operate in both
synchronous and asynchronous applications and contains an
on-chip precision reference voltage (1.575 V).
The transmit bandpass and receive lowpass filters, and the
active RC pre-filtering and post-filtering are incorporated, as
well as fully differential analog circuit deSign for lowest noise.
Push-pull 300 0 power drivers with external gain adjust are
also included.
The MC14LC5480 PCM Codec-Filter accepts a variety of
clock formats, including short-frame sync, long-frame sync,
10L, and GCI timing environments. This device also maintains
compatibility with Motorola'S family of Telecom products,
including
the
MC145472
U-Interface
Transceiver,
MC145532
MC145474175 SIT-Interface Transceiver,
AOPCM Transcoder, MC145422126 UOLT-I, MC145421/25
UOLT-II, and MC3419/MC33120 SLiC.
Replaces the MC145480P, OW, SO.
ROC
VSS-
VOO-
~JSiii
~
MulA
~VLS
8-12
MOTOROLA ANALOG IC DEVICE DATA
PBX Architecture (continued)
MC14LC5540P, DW, FU
Case 710, 751F,873
The MC14LC5540 ADPCM Codec is a single chip
implementation of a PCM Codec-Filter and an ADPCM
encoder/decoder, and therefore provides an efficient solution
for applications requiring the digitization and compression of
voiceband Signals. This device is designed to operate over a
wide voltage range, 2.7 V to 5.25 V, and as such is ideal for
battery powered as well as ac powered applications. The
MC14LC5540 ADPCM Codec also includes a serial control
port and internal control and status registers that permit a
microcomputer to exercise many built-in features.
The ADPCM Codec is designed to meet the 32 kbps
ADPCM
conformance
requirements
of
CCITT
Recommendation G.721 (1988) and ANSI T1.301 (1987). It
also meets ANSI T1.303 and CCITT Recommendation G.723
for 24 kbps ADPCM operation, and the 16 kbps ADPCM
standard, CCITT Recommendation G.726. This device also
meets the PCM conformance specification of the CCITT
G.714 Recommendation.
Figure 1. MC14LC5540 ADPCM Codec Block Diagram
Codec-Filter
PO+
DR
FSR
DSP
PO-
BCLKR
ADPCM
Transcoder,
Receive Gain
and
Dual Tone
Generator
PI
RO
AXO-
II
BCLKT
FST
DT
AXO+
VDSP
TG
TITI+
Sequence!
Control
VDD
SPC
VAG
VSS
C1+
C1VEXT
PDVRESET SCPEN
SCPRx
SCPCLK
MOTOROLA ANALOG IC DEVICE DATA
SCPTX
8-13
PBX Architecture (continued)
MC145537EVK
ADPCM Codec Evaluation Kit
The MC145537EVK is the primary tool for evaluation and
demonstration of the MC14LC5540 ADPCM Codec. It
provides the necessary hardware and software interface to
access the many features and operational modes of the
MC14LC5540 ADPCM Codec.
• Provides Stand Alone Evaluation on Single Board
• The kit provides Analog-to-Analog, Analog-to-Digital or
Digital-to-Analog Connections - with Digital Connections
being 64 kbps PCM, 32 or 24 kbps ADPCM, or 16 kbps
CCITI G.726 or Motorola Proprietary ADPCM
• +5.0 V Only Power Supply, or 5.0 V Plus 2.7 to 5.25 V
Supply
• Easily Interfaced to Test Equipment, Customer System,
Second MC145537EVK or MC145536EVK (5.0 V Only)
for Full Duplex Operation
• Convenient Access to Key Signals
• Piezo Loudspeaker
• EIA-232 Serial Computer Terminal Interface for Control
of the MC14LC5540 ADPCM Codec Features
• Compatible Handset Provided
• Schematics, Data Sheets, and User's Manual Included
Figure 2. MC145537EVK Block Diagram
+5.0 V
r
-
-Gnd-
I ation.
It also has an enhanced TOM interface that sUPP9rts an
on-chip timeslotassigner, GCI and IDL modes of operation.
The optional manual maintenance mode lets you choose
an inexpensive microcontroller, such as a meml;ler of
Motorola's MC68HC05 family, to control and augment the
Case 873A
MC1454BB
OOLC
TA
MC145574
SCP
IOL
MC145574DW
Case 751F
The MC145574 SfT-lnterface Transceivers provide a
CCITT 1.430 compatible interface for use in line card, network
termination, and ISDN terminal equipment applications.
Manufactured with Motorola's advanced 0.65 micron CMOS
mixed analog and digital process technology, the MC145574 is
a physical layer device capable of operating in point-to-point
or point-ta-multipoint passive bus arrangements. In addition,
the MC145574 implements the optional NT1 Star topology, NT
terminal mode and TE slave mode.
This
device
features
outstanding
transmission
performance. It reliably transmits over 1 kilometer in a
point-ta-point application. Comparable performance is
achieved in all other topologies as well. Other features include
pin selectable terminal or network operating modes, industry
standard microprocessor serial control port, full support of the
multiframing Sand Q channels, a full range of loopbacks, and
low power CMOS operation, with a maximum power
consumption of 90 mW.
The MC145574 has an enhanced TOM interface that
supports GCI, IDL and an on-chip timeslot assigner.
NT1
MC145572
MC145574
GCI
SIT
LT
MC145572
SIT
U
Chip
Chip
IOL
U
Chip
C
SCP
e
n
t
NT1ITA
a
I
SIT
Chip
MC6B302
RS232
8-16
o
S P
f
f
LT
MC145572
MC145572
IOL
U
Chip
I
c
e
SCP
MOTOROLA ANALOG ICDEVICE DATA
ISDN Voice/Data Circuits
(continued)
Dual Data Link Controller
MC145488FN
Case 779
MC14LC5494EVK
U-Interface Transceiver Evaluation Kit discontinued
The MC145488 features two full-Quplex serial HDLC
channels with an on--chip Direct Memory Access (DMA)
controller. The DMA controller minimizes the number of
microprocessor interrupts from the communications
channels, freeing the microprocessor's resources for other
tasks. The DMA controller can access up to 64 kbytes of
memory, and transfers either 8-bit bytes or 18-bit words to or
from memory. The MC145488 DDLC is compatible with
Motorola's MC68000 and other microprocessors.
In a typical ISDN terminal application, one DDLC
communications channel supports the D--channel (LAPD)
while the other supports the B--channel (LAPB). While the
DDLC is ideally suited for ISDN applications, it can support
many other HDLC protocol applications as well.
Some of the powerful extras found on the DDLC include
automatic abort and retransmit of D--channel collisions in
SIT-interface applications, address recognition, automatic
recovery mechanisms for faulty frame correction, and several
system test modes. Address recognition provides a reduction
in the host microprocessor load by filtering data frames not
addressed to the host. The DDLC can compare either SAPI or
TEl fields of LAPD frames. For LAPD (Q.921) applications,
both A and B addresses may be checked.
MC145572EVK
U-Interface Transceiver Evaluation Kit
This kit provides the hardware and software to evaluate the
many configurations under which the MC145572EVK is able
to operate. Used as a whole, it operates as both ends of the
two-wire U interface that extends from the customer premises
(NT1) to the switch line card (LT). The two halves ofthe board
can be physically and functionally separated, providing
independent NT1 and LT evaluation capability.
The kit provides the ability to interactively manipulate
status registers in the MC145572EVK U-Interface transceiver
or in the MC145474175 SIT-Interface transceiver with the aid
of an external terminal. The device can also be controlled
using the MC68302 Integrated Multiprotocol Processor
application development system to complete a total Basic
Rate ISDN evaluation solution.
II
281 Q U-Interface
NT1 Side
SIT
Interface
IDL
SIT-Interface
Transceiver
MC145474
IDL~
LTSide
t --I
I
SCP
,.IDL
U-Interface
Transceiver
MC145572FN
__ .J
SCP~~+-----4-------~~------------~------~~--.
Gated
Clocks
'------'f-------...,t-~
SCP
MC145572EVK
MOTOROLA ANALOG IC DEVICE DATA
8-17
Voice/Data Communication
(Digital Transmission)
UDLTs utilize a 256 kilobaud Modified Differential Phase
Shift Keyed (MDPSK) burst modulation technique for
transmission to minimize radio frequency, electromagnetic,
and crosstalk interference. Implementation through CMOS
technology takes advantage of
low-power operation,
increased reliability, and the proven capabilities to perform
complex telecommunications functions.
.
2-Wire Universal Digital Loop
Transceiver (UDLT)
MC145422P,
ow Master Station
Case 708, 751 E
MC145426P, OW Slave Station
Case 708, 751 E
II
The UDLT family of transceivers allows the use of existing
twisted-pair telephone lines (between conventional
telephones and a PBX) for the transmission of digital data.
With the UDLT, every voice-only telephone station in a PBX
system can be upgraded to a digital telephone station that
handles the complex voice/data communications with no
increase in cabling costs.
In implementing a UDLT-based system the AID to D/A
conversion function associated with each telset is relocated
from the PBX directly to the telsel. The SLiC (or its equivalent
circuit) is eliminated since its signaling information is
transmitted digitally between two UDLTs.
The UDLT master-slave system incorporates the
modulation/demodulation functions that permit data
communications over a distance up to 2 kilometers. It also
provides the sequence control that governs the exchange of
information between master and slave. Specifically, the master
resides on the PBX line card where it transmits and receives
data over the wire pair to the telset. The slave is located in the
telset and interfaces the mono-circuit to the wire pair. Data
transfer occurs in 1o-bit bursts (8 bits of data and 2 signaling
bits), with the master transmitting first, and the slave responding
In a synchronized half-duplex transmission formal.
Functional Features
• Provides Synchronous Duplex 64 kbitslSecond
Voice/Data Channel and Two 8 kbitslSecond Signaling
Data Channels Over One 26 AWG Wire Pair Up to 2 km.
• Compatible with Existing and Evolving Telephone Switch
Architectures and Call Signaling Schemes
• Automatic Detection Threshold Adjustment for Optimum
Performance Over Varying Signal Attenuations
• Protocol Independent
• Single 5.0 V to 8.0 V Power Supply
MC145422 Master UDLT
• 2.048 MHz Master Clock
• Pin Controlled Power-Down and Loop-Back Features
• Variable Data Clock - 64 kHz to 2.56 MHz
• Pin Controlled Insertion/Extraction of 8 kbits/Seconds
Channel into LSB of 64 kbits/Second Channel for
Simultaneous Routing of Voice and Data Through PCM
Voice Path of Telephone Switch
MC145426 Slave UDLT
• Compatible with MC145500 Series and Later PCM
Mono-Circuits
• Automatic Power-Up/Down Feature
• On-Chip Data Clock Recovery and Generation
• Pin Controlled 500 Hz D3 or CCITT Format PCM Tone
Generator for Audible Feedback Applications
...-------......:::;::::..---4- Signaling Inpull
r-----------Line
Driver
Output
Signaling Input 2
Receive Dam Input
r--L.-~_ _ _ _~
Receive Enable
er
\TaIid1Jal8
\ - - - - - - ~oop
ower own
1 - - -_ _- TIA Dam Clock
--+
1------ Conv.rtCioCk
Master Sync
~===::: Signal Insert Enable
I...§!~I.E!~___
1------ Mu Law
1------I
.~ ..
Tone Enable
XTALIn
I..........
~T~~ _ _ _ _
Master
Only
_
Slave
Only
J_
Transmit Enable
Line
Input
Transmft Daia
Signal Output 1
Signal Output 2
8-18
MOTO~OLA
ANALOG IC DEVICE.DATA
Voice/Data Communication (Digital Transmission)
(continued)
2-Wire ISDN Universal Digital Loop Transceiver II (UDLT II)
MC145421 P,
ow Master
Similar to the MC145422126 UDLT, but provide
synchronous full duplex 160 kbps voice and data
communication in a 2B + 2D format for ISDN compatibility on
a single twisted pair up to 1 km. Single 5.0 V power supply,
protocol independent.
Case 709, 751 E
MC145425P, OW Slave
Case 709, 751 E
Electronic Telephone
The Complete Electronic Telephone Circuit
MC34010P, FN
TA =-20° to +60°C, Case 711,777
The conventional transformer-driven telephone handset is
undergoing major innovations. The bulky transformer is
disappearing. So are many of its discrete components,
including the familiar telephone bell. They are being replaced
with integrated circuits that perform all the major handset
functions simply, reliably and inexpensively ... functions such
as 2-t0-4 wire conversion, DTMF dialing, tone ringing, and a
variety of related activities.
The culmination of these capabilities is the Electronic
Telephone Circuit, the MC34010. These ICs place all of the
above mentioned functions on a single monolithic chip.
These telephone circuits utilize advanced bipolar analog
(12L) technology and provide all the necessary elements of a
modern tone-dialing telephone. The MC34010 even
incorporates an MPU interface circuit for the inclusion of
automatic dialing in the final system.
• DTMF generator uses low cost ceramic resonator with
accurate frequency synthesis technique
• Tone ringer drives piezoelectric transducer and satisfies
EIA-470 requirements
• Speech network provides 2-to-4 wire conversion with
adjustable sidetone utilizing an electret transmitter
• On--chip regulator insures stable operation over wide
range of loop lengths
• 12L technology provides low 1.4 V operation and high
static discharge immunity
• Microprocessor interface port for automatic dialing features
Also Available
A broad line of additional telephone components for
customizing systems design.
• Provides all basic telephone functions, including DTMF
dialer, tone ringer, speech network and line voltage
regulator
Hook Switch
//r-~
Ceramic
Resonator
r1 2 3 A
4 5 6 8
7 8 9 C
• 0 # 0
Keypad
MPU
-----,
I
I
/
Tip
,.-'-.............., ,....--...... J
DTMF
MPU
Intertace
Receiver
Tone
Ringer
I
I
I
Ring
Speech
Network
MC34010
Electret
Microphone
MOTOROLA ANALOG IC DEVICE DATA
8-19
II
Tone Ringers
The MC34012, MC34017, and MC34117 Tone Ringers are
designed to replace the bulky bell assembly of a telephone,
while providing the same function and performance under a
variety of conditions. The operational requirements spelled
out by the FCC and EIA-470, simply stated, are that a ringer
circuit MUST function when a ringing signal is provided, and
MUST NOT ring when other signals (speech, dialing, noise)
are on the line. The tone ringers described below were
designed to meet those requirements with a minimum of
external components.
MC34012P, D
TA
=-20° to +60°C, Case 626, 751
• Complete Telephone Bell Replacement
• On-Chip Diode Bridge and Transient
Protection
• Single-Ended Output to Piezo
Transducer
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial and Hook Switch
Transients
• Adjustable Base Frequencies
• Output Frequency to Warble Ratio MC34012-1 :80
MC34012-2:160
MC34012-3:40
Aing>-----<>-:-:~~..
MC34017P, D
TA
=-20° to +60°C, Case 626, 751
AI 4 *C4
• Complete Telephone Bell Replacement
Circuit with Minimum External
Components
Aing
• On-Chip Diode Bridge and Transient
Protection
• Direct Drive for Piezoelectric
Transducers
• Push Pull Output Stage for Greater
Output Power Capability
• Base Frequency Options
- MC34017-1: 1.0 kHz
- MC34017-2: 2.0 kHz
- MC34017-3: 500 Hz
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial TranSients
8-20
r--------- ---------,t
t
t
I
TiP~ ACI DIode
Cl
1
AC2 1
•
I 2A01
MOTOROLA ANALOG IC DEVICE DATA
Tone Ringers
(continued)
MC34217P, D
TA
=-20° to +60°C, Case 626, 751
• Complete Telephone Bell Replacement
• On-Chip Diode Bridge
Internal Transient Protection
• Differential Output to Piezo Transducer
for Louder Sound
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial and Hook Switch
Transients
• Base Frequency and Warble
Frequencies are Independently
Adjustable
• Adjustable Base Frequency
• Reduced Number of Externals
r- ....... ---.--81 fl01 l.lIlId$ll!ttIgII
Tip ~If-t...........-.,
R1 C1 1
1
Ring
..----4~,....,~I~~
Speech Networks
Telephone Speech Network with Dialer Interface
MC34114P, DW
TA
=-20° to +70°C, Case 707, 751 D
• Operation Down to 1.2 V
• Adjustable Transmit, Receive, and Sidetone Gains by
External Resistors
• Differential Microphone Amplifier Input Minimizes RFI
• Transmit, Receive, and Sidetone Equalization on both
Voice and DTMF Signals
•
•
•
•
Regulated 1.7 V Output for Biasing Microphone
Regulated 3.3 V Output for Powering External Dialer
Microphone and Receive Amplifiers Muted During Dialing
Differential Receive Amplifier Output Eliminates Coupling
Capacitor
• Operates with Receiver Impedances of 150 n and Higher
Tip 0 - - - - - ,
Ring 0 - - - - - '
MOTOROLA ANALOG Ie DEVICE DATA
8-21
Speech Networks
(continued)
Cordless Universal Telephone Interface
MC34016DW, P
TA
=-20° to +70°C, Case 7510,738
The MC34016 is a telephone line interface meant for use
in cordless telephone base stations for CTO, CT1, CT2 and
DECT. The circuit forms the interface towards the telephone
line and performs all speech and line interface functions like
dc and ac line termination, 2-4 wire conversion, automatic
gain control and hookswitch control. Adjustment of
transmission parameters is accomplished by two 8 bit
registers accessible via the integrated serial bus interface and
by external components.
• DC Masks for Voltage and Current Regulation
• Supports Passive or Active AC Set Impedance
Applications
• Double Wheatstone Bridge Sidetone Architecture
• Symmetrical Inputs and Outputs with Large Signal Swing
Capability
• Gain Setting and Mute Function for Tx and Rx Amplifiers
• Very Low Noise Performance
• Serial Bus Interface SPI Compatible
• Operation from 3.0 to 5.5 V
II
FEATURES
Line Driver Architecture
• Two DC Masks for Voltage Regulation
• Two DC Masks for Current Regulation
• Passive or Active Set Impedance Adjustment
• Double Wheatstone Bridge Architecture
• Automatic Gain Control Function
Transmit Channel
• Symmetrical Inputs Capable of Handling Large Voltage
Swing
• Gain Select Option via Serial Bus Interface
• Transmit Mute Function, Programmable via Bus
• Large Voltage Swing Capability at the Telephone Line
Receive Channel
• Double Sidetone Architecture for Optimum Line Matching
• Symmetrical Outputs Capable of Producing High Voltage
Swing
• Gain Select Option via Serial Bus Interface
• Receive Mute Function, Programmable via Serial Bus
Serial Bus Interface
• 3-Wire Connection to Microcontroller
• One Programmable Output Meant for Driving a
Hookswitch
• Two Programmable Outputs Capable of Driving Low
Ohmic Loads
• Two 8-Bit Registers for Parameter Adjustment
... 1-::~
/,1
Serial Bus Interface
·1
"1
AGe'
""""""""'''''''''''''''''''''''''''''''''''''''T'C0Ui2
....",..r
''''' _
, __
AGe
HKSW
__
I
~_J
+5.0 V
Serial Bus
Inputs
8-22
A (Tip)
'----+--- B (Ring)
~
Logic
Outputs
MOTOROLA ANALOG IC DEVICE DATA
Speech Networks
(continued)
Programmable Telephone Line Interface
Circuit with Loudspeaker Amplifier
MC34216DW
TA
=0
0
to +70°C, Case 751 F
The MC34216 is developed for use in telephone
applications where besides the standard telephone functions
also the group listening-in feature is required. In cooperation
with a microcontroller, the circuit performs all basic telephone
functions including DTMF generation and pulse-dialing. The
listening-in part includes a loudspeaker amplifier, an
anti-howling circuit and a strong supply. In combination with
the TCA3385, the ringing is performed via the loudspeaker.
FEATURES
Line Driver and Supply
•
•
•
•
DC and AC Termination of the Line
Selectable Masks: France, U.K., Low Voltage
Current Protection
Adjustable Set Impedance for Resistive and Complex
Termination
• Efficient Supply Point for Loudspeaker Amplifier and
Peripherals
Handset Operation
•
•
•
•
Transmit and Receive Amplifiers
Adjustable Sidetone Network
Line Length AGC
Microphone and Earpiece Mute
• Earpiece Gain Increase Switch
• Microphone Squelch Function
• Transmit Amplifier Soft Clipping
Dialing and Ringing
•
•
•
•
•
•
Generates DTMF, Pilot Tones and Ring Signal
Interrupter Driver for Pulse-Dialing
Low Current While Pulse-Dialing
Optimized for Ringing via Loudspeaker
Programmable Ring Melodies
Uses Inexpensive 500 kHz Resonator
Loudspeaking Facility
•
•
•
•
•
Integrated Loudspeaker Amplifier
Peak-to-Peak Limiter Prevents Distortion
Programmable Volume
Anti-Howling Circuitry for Group Listening-In
Interfacing for Handsfree Conversation
8
Application Areas
•
•
•
•
Corded Telephony with Group Listening-In
Cordless Telephony Base Station with Group Listening-In
Telephones with Answering Machines
Fax, Intercom, Modem
Line +
7"~-:------"""""""'1
4
>7.'"1"
Handset
Earpiece
Supply
Stabilizer
l
Handset
Microphone
!
Base
Loudspeaker
I
I
I
1
_ _ _ _ _ _ _ _ _ _ _ _ _ JI
DTMFand
Ring
Generator
Microcontroller
Intenace
Line-
MOTOROLA ANALOG IC DEVICE DATA
8-23
Speech Networks (continued)
Telephone Line Interface
TCA3388DP, FP
TA =0° to +70°C, Case 738, 7510
The TCA3388 is a telephone line interface circuit which
performs the basic functions of a telephone set in combination
with a microcontroller and a ringer. It includes dc and ac line
termination, the hybrid function with 2 adjustable sidetone
networks, handset connections and an efficient supply point.
•
•
•
•
FEATURES
•
•
•
•
Line Driver and Supply
•
•
•
•
DC and AC Termination of the Telephone Line
Selectable DC Mask: France, U.K., Low Voltage
Current Protection
Adjustable Set Impedance for Resistive and Complex
Termination
• Efficient Supply Point for Peripherals
• Hook Status Detection
Double Anti-Sidetone Network
Line Length AGC
Microphone and Earpiece Mute
Transmit Amplifier Soft Clipping
Dialing and Ringing
Interrupter Driver for Pulse-Dialing
Reduced C~9:ent Consumption During Pulse-Dialing
DTMF Inte~~ing
Ringing vi~ Extemal Ringer
Application Areas
• Corded Telephony
• Cordless Telephony Base Station
• Answering Machines
• Fax
Handset Operation
• Intercom
• Modem
• Transmit and Receive Amplifiers
II
Line +
DC and AC
Handset
Earpiece
Handset
Microphone
_.
I
I
L.,,-'
f ___
DC Mask Generation
AC Termination
2-4 Wire Conversion
Microcontrolier
Interface
~
__ _
Une-
8-24
MOTOROLA ANALOG IC DEVICE DATA
Speakerphones
Voice Switched Speakerphone Circuit
MC34018P, DW
TA
=-20
0
to +60°C, Case 710, 751 F
The MC34018 Speakerphone integrated circuit
incorporates the necessary amplifiers, attenuators, and
control functions to produce a high quality hands-free
speakerphone system. Included are a microphone amplifier,
a power audio amplifier for the speaker, transmit and receive
attenuators, a monitoring system for background sound level,
and an attenuation control system which responds to the
relative transmit and receive levels as well as the background
level. Also included are all necessary regulated voltages for
both internal and external circuitry, allowing line-powered
operation (no additional power supplies required). A Chip
Select pin allows the chip to be powered down when not in
use. A volume control function may be implemented with an
external potentiometer. MC34018 applications include
speakerphones for household and business uses, intercom
systems, automotive telephones, and others.
• All Necessary Level Detection and Attenuation Controls
for a Hands-Free Telephone in a Single Integrated
Circuit
• Background Noise Level Monitoring with Long Time
Constant
• Wide Operating Dynamic Range Through Signal
Compression
• On-Chip Supply and Reference Voltage Regulation
• Typical 100 mW Output Power (into 25 0) with Peak
Limiting to Minimize Distortion
• Chip Select Pin for Active/Standby Operation
• Linear Volume Control Function
Electret
Microphone
II
Speaker
TelePhonr---+
Line\!
Receive Volume Control
MOTOROLA ANALOG IC DEVICE DATA
8-25
Speakerphones
(continued)
Voice Switched Speakerphone Circuit
MC34118P, DW
TA = -20° to +60°C, Case 710, 751 F
The MC34'118 Voice Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain and mute control,
Transmit and Receive attenuators which operate in a
complementary manner, level detectors at input and output of
both attElnuators,and background noise monitors for both the
transmit and receive channels. A dial tone detector prevents
the dial tone from being attenuated by the Receive
background noise monitor circuit. Also included are two line
driver amplifiers which can be used to form a hybrid network
in conjunction with an external coupling transformer. A
high-pass filter can be used to filter out 60 Hz noise in the
receive channel, or for other filtering functions. A Chip Disable
pin permits powering down the entire circuit to conserve power
on long loops where loop current is at a minimum.
The MC34118 may be operated from a power supply, or
it can be powered from the telephone line, requiring typically
5.0 mA. The MC34118 can be interfaced directly to TIp and
Ring (through a coupling transformer) for stand-alone
operation, or it can be used in conjunction with a handset
speech network and/or other features of a featurephone.
• Improved Attenuator Gain Range: 52 dB Between
Transmit and Receive
• Low Voltage Operation for Line-Po~ered Applications
(3.0 to 6.5 V)
• 4-Point Signal, Sensing for Improved Sensitivity
• Background Noise Monitors for Both Transmit and
Receive Paths
• Microphone Amplifier Gain Set by External ResistorsMute Function Included
• Chip Disable for Active/Standby Operation
• On Board Filter Pinned-out for User Defined Function
• Dial Tone Detector Inhibits Receive Idle Mode During Dial
Tone Presence
• Compatible with MC34119 Speaker Amplifier
II
(
'I
I
I
I
I
I
I
, I
Ring
~Vcc
~ChiP
I
Disable
Filter
_ _ _ _ _ ...JI
8-26
MOTOROLA ANALOG IC DEVICE DATA
Speakerphones
(continued)
Voice Switched Speakerphone with /-lProcessor Interface
MC33218AP,
TA
ow
=-40° to +85°C, Case 724, 751 E
The MC33218A, Voice Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain, and mute control,
transmit and receive attenuators which operate in a
complementary manner, and level detectors and background
noise monitors for both paths. A dial tone detector prevents
dial tone from being attenuated by the receive background
noise monitor. A Chip Disable pin permits powering down the
entire circuit to conserve power.
Also included is an 8--bit serial IlProcessor port for
controlling the receive volume, microphone mute, attenuator
gain, and operation mode (force to transmit, force to receive,
etc.). Data rate can be up to 1.0 MHz. The MC33218A can be
operated from a power supply, or from the telephone line,
requiring typically 3.8 rnA. It can also be used in intercoms and
other voice-activated applications.
•
•
•
•
Low Voltage Operation: 2.5 to 6.0 V
2-Point Sensing, Background Noise Monitor in Each Path
Chip Disable Pin for Active/Standby Operation
Microphone Amplifier Gain Set by External Resistors Mute Function Included
• Dial Tone Detector to Inhibit Receive Idle Mode During
Dial Tone Presence
• Microprocessor port for controlling:
• Receive Volume Level (16 Steps)
• Attenuator Range (26 or 52 dB, Selectable)
• Microphone Mute
• Force to Transmit, Receive, Idle or Normal Voice
Switched Operation
• Compatible with MC34119 Speaker Amplifier
r---------------,I
III
) -......--;--.... TxOutput
Rx Input
Vcc
Chip Disable
MOTOROLA ANALOG IC DEVICE DATA
8--27
Speakerphones
(continued)
Voice Switched Speakerphone Circuit
MC33219AP, ADW
TA
=-40° to +85°C, Case 724, 751 E
The MC33219A Voice Switched Speakerphone Circuit
incorporates the necessary amplifiers, attenuators" level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain, and mute control,
transmit and receive attenuators which operate in a
complementary manner, and level detectors and background
noise monitors, A dial tone detector prevents dial tone from
being attenuated by the receive background noise monitor. A
Chip Disable pin permits powering down the entire circuit to
I
conserve power.
The MC33219A may be operated from a power supply, or
it can be powered from the telephone line requiring typically
4.0 mAo The MC33219A can be interfaced directly to TIp and
Ring (through a coupling transformer for stand-alone
operation, or it can be used in conjuction with a. handset
speech network and/or other features of a featurephone.
• Low Voltage Operation: 2.7 to 6.0 V
• 2-Point Sensing, Background Noise Monitor in Each Path
• Chip Disable Pin for Active/Standby Operation
• Microphone Amplifier Gain Set by External ResistorsMute Function Included
• Dial Tone. Detector to Inhibit Receive Idle Mode During
Dial Tone Presence
• Volume Control Range: 34 dB
• Compatible with MC34119 Speaker Amplifier
Mute
>-+"'--i-....
Tx Output
II
Speaker
I
Speaker
Amp
....
, "
~
Bias"
VCC
,_
:
_
_ _ _ _ _• . _ _._ .J
VVV,
Rx Input
Chip Disable
-=-
Volum~
Control
MOTOROLA ANALOG IC DEVICE DATA
Speakerphones
(continued)
Telephone Line Interface and Speakerphone Circuit
MC33215B, FB
TA
=0° to +70°C, Case 858, 848B
The MC33215 is a combination speech network!
speakerphone developed for use in fully electronic telephone
sets with a speakerphone function. The circuit performs the ac
and dc line terminations, 2-4 wire conversion, line length AGC
and DTMF transmission. The speakerphone part includes a
half duplex controller with signal and noise monitoring, base
microphone and loudspeaker amplifiers, and an efficient
supply. The circuit is designed to operate at low line currents
down to 4.0 rnA enabling parallel operation with a classical
telephone set.
FEATURES
Line Driver and Supply
• AC and DC Termination of Telephone Line
• Adjustable Set Impedance for Real and Complex
Termination
• Efficient Supply for Speaker Amplifier and Peripherals
• Two Supplies for Handset and Base Microphones
• Separate Supply Arrangement for Handset and
Speakerphone Operation
Handset Operation
•
•
•
•
•
•
•
Transmit and Receive Amplifiers
Differential Microphone Inputs
Sidetone Cancellation Network
Line Length AGC
Microphone and Earpiece Mute
Separate Input for DTMF and Auxiliary Signals
Parallel Operation Down to 4.0 rnA of Line Current
Speakerphone Operation
• Integrated Microphone and Loudspeaker Amplifiers
• Differential Microphone Inputs
• Loudspeaker Amplifier can be Powered and Used
Separately from the Rest of the Circuit
• Integrated Switches for Smooth Switch Over from
Handset to Speakerphone Mode
• Signal and Background Noise Monitoring in Both
Channels
• Adjustable Switching Depth for Handsfree Operation
• Adjustable Switch Over and Idle Mode Timing
• Dial Tone Detector in the Receive Channel
• Handsfree Operation via Loudspeaker and Base
Microphone
r---------------~--------_.------------ 1.0 ~F)
External Required:
• 14 Resistors
• 12 Capacitors (SI.0 ~F)
• 9 Capacitors (> 1.0 ~F)
External Required:
• 12 Resistors
• 11 Capacitors (SI.0 ~F)
• 4 Capacitors (> 1.0 ~F)
External Required:
• 12 Resistors
• 11 Capacitors (SI.0 ~F)
• 4 CapaCitors (> 1.0 ~F)
Temperature Range:
-20° to +60°C
Temperature Range:
-20° to +60°C
Temperature Range:
-40° to +85°C
Temperature Range:
-40° to +85°C
8-30
MOTOROLA ANALOG IC DEVICE DATA
Telephone Accessory Circuits
Audio Amplifier
MC34119P,D
TA
=0° to +70°C, Case 626, 751
A low power audio amplifier circuit intended (primarily) for
telephone applications, such as speakerphones. Provides
differential speaker outputs to maximize output swing at low
supply voltages (2.0 V min.). Coupling capacitors to the
speaker, and snubbers, are not required. Overall gain is
externally adjustable from 0 to 46 dB. A Chip Disable pin
permits powering-down to mute the audio signal and reduce
power consumption.
Drives a Wide Range of Speaker Loads (16 to 100 0)
Output Power Exceeds 250 mW with 32 0 Speaker
Low Distortion (THD = 0.4% Typical)
Wide Operating Supply Voltage (2.0 V to 16 V) - Allows
Telephone Line Powered Applications.
• Low Quiescent Supply Current (2.5 mA Typical)
• Low Power-Down Quiescent Current (60 ~ Typical)
•
•
•
•
Current Mode Switching Regulator
MC34129P,D
High performance current mode switching regulator for
low-power digital telephones. Unique internal fault timer
provides automatic restart for overload recovery. A starVrun
comparator is included to implement bootstrapped operation
ofVCC·
Although primarily intended for digital telephone systems,
these devices can be used cost effectively in many other
applications. On-chip functions and features include:
•
•
•
•
•
•
•
Current Mode Operation to 300 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle-By-Cycle Current Limiting
Latched-Off or Continuous Retry after Fault Timeout
Soft-Start with Maximum Peak Switch Current Clamp
Internally Trimmed 2% Bandgap Reference
Input Undervoltage Lockout
MOTOROLA ANALOG IC DEVICE DATA
II
r-------------,
TA = 0° to +70°C, Case 646, 751A
I
lsi
I
Start/Run
c SofHltart 112
I
syncllnhibit~
Input
Noninverting
Input
Inverting Input
' -_ _-:.:0 Feedback!
I PWMlnput
Drive Out
Drive Gnd
I
IL _ _ _ _ _ _ _ _ _ _
~
_ _ J Ramp Input
8-31
Telephone Accessory Circuits
(continued)
300 Baud FSK Modems
The differential line driver is capable of driving 0 dBm into
a 600 n load. The transmit attenuator is programmable in
1.0 dB steps.
MC145442P, ow Modem - CCITT V.21
Case 738, 751 D
ADPCM Transcoder
MC145443P, OW Modem - 8ell103
Case 738, 751 D
MC145532DW, L
Case 751G, 620
This powerful modem combines a complete FSK
modulator/demodulator and an accompanying transmit/receive
filter system on a single silicon chip. Designed for bidirectional
transmission over the telephone network, the modem operates
at 300 baud and can be obtained for compatibility with CCITT
V.21 and Bell 103 specifications.
The modem contains an on-board carrier-detect circuit
that allows direct operation on a telephone line (through a
simple tranSformer), providing simplex, half-duplex, and
full-duplex data communications. A built-in power amplifier is
capable of driving -9.0 dBm onto a 600 n line in the transmit
mode.
CMOS processing keeps power dissipation to a very low
45 mW, with a power-down dissipation of only 1.0 mW ... from
a single 5.0 V power supply. Available in a 20 pin dual-in-line
P suffix, and a wide body surface mount DW suffix.
MC145407
+5.0 V
MC145443
+5.0 V
II
CD
3.579545 MHz
MC145444H, OW - CCITT V.21
Case 804, 7510
MC145446AFW - CCITT V.21
Case 751M
This device includes the DTMF generator and call progress
tone detector (CPTD) as well as the other circuitry needed for
full-duplex, half-duplex, or simplex 300 baud data
communication over a pair of telephone lines. It is intended for
use with telemeter system or remote control system
applications.
8-32
The MC145532 Adaptive Differential Pulse Code
Modulation (ADPCM) Transcoder provides a low cost,
full-duplex, single-channel transcoder to (from) a 64 kbps
PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
• Complies with CCITT Recommendation G.721
(1988)
• Complies with the American National Standard
(T1.301-1987)
• Full-Duplex, Single-Channel Operation
• Mu-Law or A-Law Coding is Pin Selectable
• Synchronous or Asynchronous Operation
• Easily Interfaces with any Member of Motorola's PCM
Codee-Filter Mono-Circuit Family or Other Industry
Standard Codecs
• Serial PCM and ADPCM Data Transfer Rate from
64 kbps to 5.12 Mbps
• Power Down Capability for Low Cost Consumption
• The Reset State is Automatically Initiated when the
Reset Pin is Released.
• Simple TIme Slot Assignment TIming for Transcoder
Applications
• Single 5.0 V Power Supply
• Evaluation Kit MC145536 EVK Supports the MC145532
as well as the MC14LC5480 PCM Codee-Filter. (See
PBX Architecture Pages for More Information.)
000
EDO
DOE
EOE
DOC
EDC
DDI
EDI
DIE
EIE
MODE
APD
---------0(
---------0(
Vss-
10------- Reset
·~--------s~
-VDD
MOTOROLA ANALOG IC DEVICE DATA
Telephone Accessory Circuits
(continued)
Calling Line Identification (CLIO) Receiver with Ring Detector
MC14LC5447P, DW
Case 648, 751G
The MC14LC5447 is designed to demodulate Bell 202
1200 baud FSK asynchronous data. Its primary application is
in products that will be used to receive and display the calling
number, or the message waiting indicator sent to subscribers
from participating central office facilities of the public switched
telephone network. The device also contains a carrier detect
circuit and telephone ring detector which may be used to
power up the device.
Applications include adjunct boxes, answering machines,
feature phones, fax machines, and computer interface
products.
Replaces MC145447P, OW.
•
•
•
•
•
Ring Detector On-Chip
Ring Detect Output for MCU Interrupt
Power-Down Mode Less Than 1.0 !LA
Single Supply: 3.5 V to 6.0 V
Pin Selectable Clock Frequencies: 3.68 MHz,
3.58 MHz, or 455 kHz
• Two-Stage Power-Up for Power Management Control
TIp
Ring
r---. RawData
OUt
Cooked
Data Out
ClocI---1-. +Va
Vs _ _-----.----c>-':-l1
!--O--+-- -Va
Modulating
rt-J~4"l-r-_~~12
Signallnput 10 k
51
14
5
6.8k
'L------~V
-Il.OVdc
VEE
8-48
Carrier Null
...MVdc
VEE
MOTOROLA ANALOG IC DEVICE DATA
MC1496, B
Figure 9. Common Mode Gain
.--_ _ _ _ _ _ _--+
Figure 10. Signal Gain and Output Swing
VCC
12Vdc
.--_ _ _ _ _ _ _ _-+
VCC
12Vdc
1.0k
1.0k
3.9k
3.9k
\-:0.......-+_ +Vo
-+-- +Vo
I-;;<>......
9-----·-
1--12<>--",-" - Vo
Vs
b2
&"-"'-:-14:---""5:-1
14
50
l.~~At
6.Bk
so
IVol
ACM = 20 log V
-8.0Vdc
VEE
Vo
S
6.8k
-8.0Vdc
VEE
TYPICAL CHARACTERISTICS
=
Typical characteristics were obtained with circuit shown in Figure 5, Ie 500 kHz (sine wave),
Ve = 60 mVrms, IS = 1.0 kHz, Vs = 300 mVrms, TA = 25°e, unless otherwise noted.
Figure 11. Sideband Output versus
Carrier Levels
I
Figure 12. Signal-Port Parallel-Equivalent
Input Resistance versus Frequency
~ 2.0
a
ffi
~
~ 1.6
z
o
~
....... 1'
O.B
0.4
/
~
/":
~
~
~
rn
w
a:
4OO'mv
so
0
so
200
10
I
5.0
~5.0
10
I, FREQUENCY (MHz)
~
~ 4.0
ct
~ 120
~
100
1O~
ffi
a:
BO
rn
(S 3.0
""
140
~
60
-'
40
§
~ 1.0
ct
~
~
~
ro
B.O~
6.05
cop
irl
"'-
"' I'..
a: 20
ct
2.0
5.0
10
20
I, FREQUENCY (MHz)
MOTOROLA ANALOG IC DEVICE DATA
so
100
14~
w
12~
a
(3
1.0
so
~O
Figure 14. Single-Ended Output Impedance
versus Frequency
w
o
.....
~ 1.0
1.0
Figure 13. Signal-Port Parallel-Equivalent
Input CapaCitance versus Frequency
.,,1'
II
'-
;;
D..
300mV
200·mV
0
~
\
'"
~ 100
!!2
Signal Input = 600 mV
."~
=>
§
+~
(.)
~ 1.2
~
SOO
w
LL
i
tOM
100
$-
00
1.0
10
I, FREQUENCY (MHz)
4.0::1
2.0~
o ~
100
8-49
MC1496, B
TYPICAL CHARACTERISTICS (continued)
Typical characteristics were obtained with circuit shown in Figure 5. Ie = 500 kHz (sine wave).
Ve 60 mVrms. IS 1.0 kHz. Vs 300 mVrms. TA 25°e. unless otherwise noted.
=
=
=
=
Figure 15: Sideband and Signal Port
Transadmittances versus Frequency
0'
..c::
E
.§.
w
0
Z
1.0
0.9
0
-
O.B
IS119,il ~Irt
......
r-.
11111111
0.7
~
0.6 -
0
~
0.5
(jj
Z
<
a:
0.4 -
N
0.2 -
I 11111
0.1 -
Y21
0.1
V
out
V. (Signal)
l-
o
I
= lout (Each Sideband)
y21
iD 10
~
"""'"
SideBand
iTI HI Sideband Transadmittance
0.3 -
~
Figure 16. Carrier Suppression
versus Temperature
.......
Z
a
en
w
\
=0
I
Vout
=0
IVei
-
;;:
a:
< 50
Mi9nall;o~ ~!~~il~mitt~nc~ 1111111
lout
= V.
20
a:
"- 30
"=>
en
a:
w 40
..........
en
" "-
:f;? 60
In
1.0
10
100
IC. CARRIER FREQUENCY (MHz)
70
-75 -50
1000
-25
~
(!I
w
!'I
10
II
~
0
w
0
Z
W
~
:l:
...J
(!I
Z
en
:J:Z
~ffi
RL=500Q
Re = 1.0 k
-20
< -30
0.01
II 11111 A _
RL
II 11111
+ 2re
0.1
V - Re
-
i:r;;- 20
,
- RL = 3.9 k
Re- 2.Ok
IIIIIIII I
r - IVCI = 0.5 Vdc -
g;
10
~iil
RL = 3.9 k (Standard
-10
150 175
Z
[
r- Re = 1.0 k Test Circuit)
>
0
25
50
75 100 125
TA. AMBIENT TEMPERATURE
(0C)
j:'!:
RL=3.9k
Re=500U
(!I
a'-'
-
...J
20
Z
«
/
Figure 18. Carrier Suppression
versus Frequency
Figure 17. Signal-Port Frequency Response
iD
...... r""
..........
0
= 0.5 Vdo
MC1496---r
(70°C)
II
"
;:Q
g~ 40
~~
i5~ 50
r\.
~
"-
10
--
(j)C3
II
1.0
I. FREQUENCY (MHz)
21C
30
100
g;
(J)
IC
60
70
0.05
Figure 19. Carrier Feedthrough
versus Frequency
0.1
./
~
V
...
r""
31C
"r-
0.5 1.0
5.0 10
IC. CARRIER FREQUENCY (MHz)
50
Figure 20. Sideband Harmonic Suppression
versus Input Signal Level
...J
j:'!:
o
Z
!:!il
10
<
~iD 20
,.0 _ _
=>~
"-0
i5~ 30
USffi
i51il
40
u:I ffi
50
~a:
-
--r
Q~ 60
enO
0.5 1.0
5.0
10
fC. CARRIER FREQUENCY (MHz)
8-50
50
~
ll::
=>
en
70
SO
./
fC±3IV
0
,/
I~ ......
,../
200
400
600
Vs. INPUT SIGNAL AMPLITUDE (mVrms)
800
MOTOROLA ANALOG IC DEVICE DATA
MC1496, B
Figure 21. Suppression of Carrier Harmonic
Sidebands versus Carrier Frequency
Figure 22. Carrier Suppression versus
Carrier Input Level
-'
i:!:
1111
~
10
ir;;- 20
:J:z
~ffi
;::9
0.05
a;:
=>
en
a;:
w
--
60
70
20
w
2f ±2fS
Ci)~
&
ijl
10
en
en
CL
CL
2fC±fS
~~ 40
~~ 50
:2z
0
IIII
30
0'"
f3
CD
Jfdll~
~aJ
0.1
0.5
1.0
a:
a;:
,..-
(3
en
<..>
>
5.0
10
50
30
40
50
60
70
-
fC=10MHz- 1 -
--r
",
......
./
o
- ---
"-
"100
fC, CARRIER FREQUENCY (MHz)
1 1 -f--
IC= 500kHz
f....":
200
300
400
500
VC, CARRIER INPUT LEVEL (mVrrns)
OPERATIONS INFORMATION
The MC1496, a monolithic balanced modulator circuit, is
shown in Figure 23.
This circuit consists of an upper quad differential amplifier
driven by a standard differential amplifier with dual current
sources. The output collectors are cross-coupled so that
full-wave balanced multiplication of the two input voltages
occurs. That is, the output signal is a constant times the
product of the two input signals.
Mathematical analysis of linear ac signal multiplication
indicates that the output spectrum will consist of only the sum
and difference of the two input frequencies. Thus, the device
may be used as a balanced modulator, doubly balanced mixer,
product detector, frequency doubler, and other applications
requiring these particular output signal characteristics.
The lower differential amplifier has its emitters connected
to the package pins so that an external emitter resistance
may be used. Also, external load resistors are employed at
the device output.
Signal Levels
. The upper quad differential amplifier may be operated
either in a linear or a saturated mode. The lower differential
amplifier is operated in a linear mode for most applications.
For low-level operation at both input ports, the output
signal will contain sum and difference frequency components
Figure 23. Circuit Schematic
and have an amplitude which is a function of the product of
the input signal amplitudes.
For high-level operation at the carrier input port and linear
operation at the modulating signal port, the output signal will
contain sum and difference frequency components of the
modulating signal frequency and the fundamental and odd
harmonics of the carrier frequency. The output amplitude will
be a constant times the modulating signal amplitude. Any
amplitude variations in the carrier signal will not appear in the
output.
The linear Signal handling capabilities of a differential
amplifier are well defined. With no emitter degeneration, the
maximum input voltage for linear operation is approximately
25 mV peak. Since the upper differential amplifier has its
emitters internally connected, this voltage applies to the
carrier input port for all conditions.
Since the lower differential amplifier has provisions for an
external emitter resistance, its linear signal handling range
may be adjusted by the user. The maximum input voltage for
linear operation may be approximated from the following
expression:
V =(15) (RE) volts peak.
This expression may be used to compute the minimum
value of RE for a given input voltage amplitude.
Figure 24. Typical Modulator Circuit
H 12
.--I===:::;;:::=+==:g vo,
(+) 6 Output
:t===J::===---1--J
0 :::(-::)
Carrier VCo10Input
8 (+)
- Vc 0.1l!F
Carrier ~H------O"'l
Input VS-----...,...----- -Vo
Modulating
Signal 10 k
Input
L....r----,-..J12
14
f
15
Carrier Null
6.8 k
-8.0Vdc =
VEE
8-51
MC1496, B
Figure 25. Voltage Gain and Output Frequencies
Carrier Input Signal (VC)
Approximate Voltage Gain
Output Signal Frequency(s)
RL Vc
Low-level de
2(R E
+ 2r e) (~T)
RL
High-level de
RE
fM
fM
+ 2re
RL VC(rms)
Low-level ae
2/2
High-level ae
(~T)
(R E
+ 2re)
0.637 RL
RE
fC±fM
fC±fM, 3fC±fM, 5fC±fM, . . .
+ 2re
NOTES: 1. Low-level Modulating Signal, VM, assumed in all cases. Vc is Carrier Input Voltage.
2. When the output signal contains muniple frequencies, the gain expression given is for the output amplitude of
each of the two desired outputs, fC + fM and fC - fM'
3. All gain expressions are for a single.... nded output. For a differential output connection, multiply each
expression by two.
4. RL = Load resistance.
5. RE = Emiller resistance between Pins 2 and 3.
6. re = Transistor dynamic emitter resistance, at 25°C;
26mV
re = 15 (rnA) .
7 .. K = Boltzmann's Constant, T = temperature in degrees Kelvin, q = the charge on an electron.
~T = 26 mV at room temperature
II
The gain from the modulating Signal input port to the
output is the MC1496 gain parameter which is most often of
interest to the designer. This gain has significance only when
the lower differential amplifier is operated in a linear mode,
but this includes most applications of the device.
As previously mentioned, the upper quad differential
amplifier may be operated either in a linear or a saturated
mode. Approximate gain expressions have been developed
for the MC1496 for a low-level modulating signal input and
the following carrier input conditions:
1) Low-level dc
2) High-level dc
3) Low-level ac
4) High-level ac
These gains are summarized in Figure 25, along with the
frequency components contained in the output signal.
APPLICATIONS INFORMATION
Double sideband suppressed carrier modulation is the
basic application of the MC1496. The suggested circuit for
this application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate the
MC1496 with a single dc supply voltage instead of dual
supplies. Figure 26 shows a balanced modulator designed
for operation with a Single 12 Vdc supply. Performance of this
circuit is similar to that of the dual supply modulator.
AM Modulator
The circuit shown in Figure 27 may be used as an
amplitude modulator with a minor modification.
8-52
All that is required to shift from suppressed carrier to AM
operation is to adjust the carrier null potentiometer for the
proper amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown in
Figure 27 does not have sufficient adjustment range.
Therefore, the modulator may be modified for AM operation
by changing two resistor values in the null circuit as shown in
Figure 28.
Product Detector
The MC1496 makes an excellent SSB product detector
(see Figure 29).
This product detector has a sensitivity of 3.0 microvolts
and a dynamic range of 90 dB when operating at an
intermediate frequency of 9.0 MHz.
The detector is broadband for the entire high frequency
range. For operation at very low intermediate frequencies
down to 50 kHz the 0.1 I1F capaCitors on Pins 8 and 10
should be increased to 1.0 11F. Also, the output filter at Pin 12
can be tailored to a specific intermediate frequency and audio
amplifier input impedance.
As in all applications of the MC1496, the emitter resistance
between Pins 2 and 3 may be increased or decreased to
adjust circuit gain, sensitivity, and dynamic range.
This circuit may also be used as an AM detector by
introducing carrier signal at the carrier input and an AM signal
at the SSB input.
The carrier signal may be derived from the intermediate
frequency signal or generated locally. The carrier signal may
be introduced with or without modulation, provided its level is
sufficiently high to saturate the upper quad differential
MOTOROLA ANALOG IC DEVICE DATA
MC1496,B
amplifier. If the carrier signal is modulated, a 300 mVrms
input level is recommended.
Doubly Balanced Mixer
The MC1496 may be used as a doubly balanced mixer
with either broadband or tuned narrow band input and output
networks.
The local oscillator signal is introduced at the carrier input
port with a recommended amplitude of 100 mVrms.
Figure 30 shows a mixer with a broadband input and a
tuned output.
Frequency Doubler
The MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
Figures 31 and 32 show a broadband frequency doubler
and a tuned output very high frequency (VHF) doubler,
respectively.
Phase Detection and FM Detection
The MC1496 will function as a phase detector. High-level
input signals are introduced at both inputs. When both inputs
are at the same frequency the MC1496 will deliver an output
which is a function of the phase difference between the two
input signals.
An FM detector may be constructed by using the phase
detector principle. A tuned circuit is added at one of the inputs
to cause the two input signals to vary in phase as a function
of frequency. The MC1496 will then provide an output which
is a function of the input signal frequency.
TYPICAL APPLICATIONS
Figure 26. Balanced Modulator
(12 Vdc Single Supply)
1.0k
820
0.1/iF
25/iF 1::
51
Carrier Input 15 V -=- 0.1/iF
60 mVrms
1.3k
RL
3.0k
r-4I-:-o-W-lf--+'i
6
- Vc 0.1/iF
DSB
Carrier ~1-~-----<>-'7I
0.1/iF Output Input
8
10
MC1496
Modulatin~ +
4
Signal Input 10/iF
300 mVrms 15V
25/iF 14
15V
+
Carrier
Null 50 k
Figure 27. Balanced Modulator-Demodulator
VCC
12Vdc
Vs
10 k
100
100
MC1496
1-:1-<2)--~.. -Yo
"""---"""""5
Modulating
Signal
Input
-
3.9 k
+Vo
1-;;<>-+--+..
L - _ - "_ _-+ VEE
Carrier Null
-=-
II
6.8 k
15
-B.O Vdc -=-
Figure 29. Product Detector
(12 Vdc Single Supply)
Figure 28. AM Modulator Circuit
VCC
,--.r----",8N20'r--~~:_:::-"1"'.3..,.k_-,rl...,12 Vdc
RL
1.0k
3.0 k
3.9k
- Vc 0.1/iF
Carrier ~
Input vs
+Vo Carrier Input
300 mVrrns
MC1496
4
Modulating
Signal
Input
12
5
Carrier Adjust
15 6.8 k
VEE
-B.OVdc -=-
MOTOROLA ANALOG IC DEVICE DATA
-Yo
SSB Input
0.005
/iF
AF
1.0 k 1.0 /iFOutput
L.-,-,----r~~T~"'I--it~ 10 k
10k
10.00510.005
-=-/iF
'---"'Mr--' -=- /iF
8-53
MC1496, B
Figure 30. Doubly Balanced Mixer
(Broadband Inputs, 9.0 MHz Tuned Output)
1.0k
Figure 31. Low-Frequency Doubler
1.0k
'ri
RFC
100 !IIi
001 !!F
RFlnput ,
51
"'-;--T""' 12
1.0k
9.0 MHz
l1
~~~Ol)
pF
6.8k""
Output
MC1496
9.5 F
55.o-M
3.9k
C2.-------O-"-I
12
L
9O-480pF
.".
10k
L.....:.::::::..:.=".... VEE"'"
100
10 k
100
14
-B.OVdc
6.ak
L1 = 44 Tums AWG No. 28 Enameled Wire, Wound
on Micrometals Type 44...£ Toroid Core.
15
VEE
-B.OVdc
Figure 32. 150 to 300 MHz Doubler
..
r.L.::.-....&..::~>--+~~~
0.001 !!F.
150 MHz:_~~_--c>-,;
Input
1.o-10pF
6.ak
Balance
i
I
$>
VEE
-B.OVdc
L1 =1 TumAWG
No. 18 Wire, 7/32" ID
!!'
+
I
.g
.g
U)
,.a,
.,.,
I
+
.g
300 MHz
Output
RL = 501)
g
l
Input
I
I
I
-
>rt-]-1
-::r
10k
-
Electret
(alternate)
Microphone
and biasing
11000P
47k
I
r-'VVv-.--I
I
I
I
I
I
RbI
I
L ___
f-=--t----If---....---;EJ
i
Cc2
~
C4
C5
RF output
5.DtolDdBm
(see Note 4)
____________. -____________~~~~
I-=-
VCC = 9.DVdc
I.D!'F
tantalum
NOTES:
1. Components versus output frequency:
en
2.
3.
4.
5.
6.
..en.
Output RF
X1 (MHz)
!.I..M:!l
illIl!f)
!.2.fu!:!)
B!!:L
~
Q
~
~
~
~
49.7 MHz
16.5667
3.3-4.7
0.22.
0.22
330
390 k
33 P
33 P
33 P
470 P
33 P
47 P
220 P
76 MHz
12.6000
5.1
0.22
0.22
150
300 k
68 P
10 P
68 P
470 P
12 P
20 P
120 P
12.05
5.6
0.15
0.10
150
220k
47p
10p
68p
1000p
18p
12p
33p
144.6 MHz
Crystal X1 is fundamental mode. calibrated for parallel resonance with a 32 pF load. The final output frequency is generated by frequency multiplication within
the MC2833 IC. The RF output buffer (Pin 14) and 02 transistor are used as a frequency tripler and doubler, respectively, in the 76 and 144.6 MHz transmitters.
The 01 output transistor is a linear amplifier in the 49.7 MHz and 76 MHz transmitters, and a frequency doubler in the 144.6 MHz transmitter.
All coils used are 7 mm shielded inductors, CoilCran series M1175A, M1282A-M1289A, M1312A or equivalent.
Power output is = + 10 dBm for 49.7 MHz and 76 MHz transmitters, and =+ 5.0 dBm forthe 144.6 MHz transmitter at VCC = 8.0 V. Power output drops with
10werVCC·
All capacitors in microfarads, inductors in Henries and resistors in Ohms unless otherwise specified.
Other frequency combinations may be set-up by simple scaling of the 3 examples shown.
MOTOROLA ANALOG IC DEVICE DATA
8-57
MC2833
Figure 3. BufferlMultiplier (x3, Pin 14)
(16 MHz Fundamental)
Figure 4. Input to Doubler (Pin 13)
(49.7 MHz x 3 Component)
Figure 5. Doubler Output 76 MHz (Pin 11)
Figure 6. Spectrum
Figure 7. Output Spectrum (49.7 MHz)
Figure 8. Modulation Spectrum
(1.0 kHz Showing Carrier Null)
-43dB
8-58
MOTOROLA ANALOG IC DEVICE DATA
MC2833
Figure 9. 144.6 MHzlx12 Multiplier
Figure 10. Circuit Side View
II
Figure 11. Ground Plane on Component Side
MOTOROLA ANALOG IC DEVICE DATA
8-59
MC2833
Figure 12. Component View
rn. «
f'IIl4t----------
2.0" ----.".-----~
..I
,X1 XTAL
~h
'~.~. ~
100Kl
•....
1~.
+ 1.0 R!!.e
1K-l
•
,@)
4.7K-
...
2.7K
~
Rbl--
.-
MC2833P
NOTES:
0
Positive artwork provided.
o Drtll holes must be plated to ensure making all ground (VEE) connectionsl
o Resistors labelled' are used for biasing of electret microphone if used.
o
Capacitors labelled "SM" are silver mica.
o Final board size 1.5" x 2.0".
&:-60
MOTOROLA ANALOG IC DEVICE DATA
MC2833
Figure 13. Circuit Schematic
Pin 4
rq
Pin 9
~
~O
Pin 8
Pin 11
.lI,L
~
~k
Pin10
rtr.~
.lI v----1
Y
520
Y
Y
TP~
~
Py4
10k
115k
24k
Pin 13
Pin16
L:ri,t
Pin 12
~
Pin 15
·A.lIf-
~LA
Pin 7
LJ
50
50
i,!.
T
6.8 k
570
-'III. ~.lIlL
Pin 5
LJ LJ
470
i(t
T
1
18 k
1
18k
1
18k
~,z
~11!
4.7k
Pi~1
2.2k
I
~
lr--i
Pin2
610
~
120
in3
~
~L
2.2 k
~ [L
~
4.7k
2.2k
8k
~
P
20.2k
~
2.2 k
LI
[JL
8.5k
120
710
ItT
~11!
fl
56k
,
~
n
9.7k
18k
LT
Pin 6
MOTOROLA ANALOG IC DEVICE DATA
8-61
®
MOTOROLA
MC3335
Low Power Narrowband
FM Receiver
· .. includes dual FM conversion with Oscillators, Mixers, Quadrature
Discriminator, and Meter Drive/Carrier Detect Circuitry. The MC3335 also
has a comparator circuit for FSK detection.
• Complete Dual Conversion Circuitry
• Low Voltage: VCC
= 2.0 to 6.0 Vdc
• Low Drain Current (Typical 3.6 mA with VCC
LOW POWER
DUAL CONVERSION
FM RECEIVER
= 3.0 Vdc)
SEMICONDUCTOR
TECHNICAL DATA
• Excellent Se~sitivity: - 3.0 dB Input Limiting = 0.71lV
• Externally Adjustable Carrier Detect Function
• Separate Data Shaping Output Circuitry
-
• Data Rate Up to 35000 Baud Detectable
• 60 dB RSSI Range
• Low Number of External Parts Required
• Manufactured in Motorola's MOSAIC® Process Technology
• MC13135 is Preferred for New Designs
PSUFFIX
PLASTIC PACKAGE
CASE 738
OW SUFFIX
PLASTIC PACKAGE
CASE751D
(S0-20L)
PIN CONNECTIONS
Simplified Application as a Fixed Receiver
1stMixerlnput
11--_~
_ _ O 1st Mixer Input
2nd Lo Emitter 2
2ndLoBase 3
2nd Mixer Output 4
....---.., J......,1",,7 1st Mixer Output
Vcc
Umiterlnput 6
limIter Decoupling L!7.l'T........~....
limiter Decoupling
[!8[]--v*-++
MeterDrive 9
14 Compara1or Output
13 Comparatorlnput
I TlI''Il.'--_ "l!1,,2 Detector Output
11 Quadrature eon
'----I~
---,
10 k
To Carrier
Delecllndicalor
8-62'
Data
In
L __ -'
I,p = 660l1H
Cp = 180pF
_
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC3335DW
S0-20
f-M-C3-3-3-5-P---1 TA = - 40 to +B5'C f-p-I-as-t'-c-D-Ip--I
MOTOROLA ANALOG IC DEVICE DATA
MC3335
MAXIMUM RATINGS (TA = 25°e, unless otherwise noted)
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
5
Vee(max)
7.0
Vdc
Operating Supply Voltage Range
(Recommended)
5
Vee
2.0 to 6.0
Vdc
1,20
VI-20
1.0
Vrms
-
TJ
150
°e
TA
-40to+85
°e
TstQ
-65to+150
°e
Input Voltage (Vee> 5.0 Vdc)
Junction Temperature
Operating Ambient Temperature Range
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (Vee = 5.0 Vdc, 10 = 49.7 MHz, Deviation = 3.0 kHz, TA = 25 o e, test circuit of Figure 2,
unless otherwise noted.)
Characteristic
Drain Current
Pin
Min
Typ
Max
Unit
5
4.5
7.0
mAde
0.7
2.0
J.lVrms
12
-
250
-
mVrms
mVrms
-
Input for - 3.0 dB Limiting
Recovered Audio (RF Signal Level
=1.0 mY)
12
-
250
-
Carrier Detect Threshold (below VCC)
9
0.64
-
Vdc
Meter Drive Slope
9
100
690
-
J.lAldB
Input for 20 dB (S + N/N)
-
7.2
-
Noise Output (RF Signal Level
=0 mY)
First Mixer Conversion Voltage Gain
-
Second Mixer Conversion Voltage Gain
-
Detector Output Resistance
12
First Mixer 3rd Order Intercept (Input)
First Mixer Input Resistance (Rp)
First Mixer Input Capacitance (C p )
1.3
-20
-
-
18
21
1.4
J.lVrms
dBm
n
pF
dB
dB
kG
Figure 1. Test Circuit
RF Input '-------1J2.6
49.7 MHzr---l
0.1
II
Vcc
20 k
56pF
RA
---,
10 k
To Carrier
Detect Indicator
MOTOROLA ANALOG IC DEVICE DATA
In
L __ ...l
~p
= 660 J.lH
Cp = 180pF
8-63
II
MC3335
Figure 3. Drain Current, Recovered
Audio versus Supply.
Figure 2. Imeter versus Input
12
11
10
9.0
......
VCC
~C3335
./
~
E? 6.0
S.O
4.0
ICC. Carr. Det. Low (RF in = 10 mY) "-
./
5.0
./
-
/'"
3.0
II
II
2.0
1.0
3.0
2.0
-130 -120 -110 -100 -90
-70
-60 -50
o
-40 -30
Figure 4. (S + N), N of 2nd Mixer
~ -20
20
o
-C
""-
z
;
10
S+N
~ -30
-10
i"...
-40
-SO
-60
~-20
"'"
1.0
""-..
~
N
-
2.0
3.0
4.0
5.0
6.0
7.0
o
8.0
I
S+N
l"'-.
~ 12
-50
'" """-
N
7.5k
MC3335~
0.01
-70
-60 -SO
-80
-130 -120 -110 -100 -90
-40 -30
Figure 6. 1st Mixer 3rd Order Intermodulation
/
10
3.0
1/ -,'
r
/
iii' -30
/
-SO
/
~
/3rd Order Intermod._
Products
V
/
-80 /
-100 -90 -80
u
/
Desired Products/
-40
>'"
---\
-
2.0
\
1.0
-
/
/
-70
-60
-50 -40 -30
RF INPUT (dBm)
-60 -50 -40 -30
Figure 7. Detector Output versus Frequency
",/
"'/
-20
-70
4.0
t/
o
-10
-80
RF INPUT (dBm)
20
8-64
'"
300>
Figure 5. (S + N)/N versus Input
RF INPUT (dBm)
-70
>
.E.
...........
-60
-80
-130 -120 -110 -100 -90 -80 -70
-60
400
100
~-30
z
+ -40
-70
~
~
VCC(V)
20
10
-10
>
~ Recovered Audio
200
RF INPUT (dBm)
o
f,--
~c--
JJ
o
-80
-- ---
.....-:::
600
....... >- soo I
ICC. Carr. Det. High (RF in = 0 mV) ......
~
g
4.0
./
,.--
800
700
6.0
/'
8.0
7.0
8.0
7.0
-20
-10
0
o
-40
-30
-20
-10
0
10
-20
!---
30
40
.RELATIVE INPUT FREQUENCY (kHz)
MOTOROLA ANALOG IC DEVICE DATA
MC3335
CIRCUIT DESCRIPTION
The MC3335 is a complete FM narrowband receiver from
antenna input to audio preamp output. The low voltage dual
conversion design yields low power drain, excellent
sensitivity and good image rejection in narrowband voice and
data link applications.
In the typical application diagram, the' first mixer amplifies
the signal and converts the RF input to 10.7 MHz. This IF
signal is filtered externally and fed into the second mixer,
which further amplifies the signal and converts it to a 455 kHz
IF signal. After external bandpass filtering, the low IF is fed
into the limiting amplifier and detection circuitry. The audio is
recovered using a conventional quadrature detector.
Twice-IF filtering is provided internally.
The input signal level is monitored by meter drive circuitry
which detects the amount of limiting in the limiting amplifier.
The voltage at the meter drive pin determines the state of the
carrier detect output which is active low.
APPLICATIONS INFORMATION
The first local oscillator can be run using a free running LC
tank, as a VCO using PLL synthesis, or driven from an
external crystal oscillator. At higher VCC values (6.0 to
7.0 V), it has been run to 170 MHz. The second local
oscillator is a common base Colpitts type which is typically
run at 10.245 MHz under crystal control.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 22 dB (typical), respectively. Mixer gain is
stable with respect to supply voltage. For both conversions,
the mixer impedances and pin layout are designed to allow
the user to employ low cost, readily available ceramic filters.
Overall sensitivity is shown in Figure 5. The input level for
20 dB (S + N)/N is 1.3 !LV using the two-pole post-detection
filter as demonstrated.
MOTOROLA ANALOG IC DEVICE DATA
Following the first mixer, a 10.7 MHz ceramic bandpass
filter is recommended. The 10.7 MHz filtered signal is then
fed into one second mixer input pin, the other input pin being
connected to VCC. Pin 5 (VCC) is treated as a common point
for emitter-driven signals.
The 455 kHz IF is typically filtered using a ceramic
bandpass filter, then fed into the limiter input pin. The limiter
has 10 !LV sensitivity for -3.0 dB limiting, flat to 1.0 MHz.
The output of the limiter is internally connected to the
quadrature detector, including a quadrature capacitor. A
parallel LC tank is needed externally from Pin 11 to VCC.
A 39 k.Q shunt resistance is included which determines the
peak separation of the quadrature detector; a smaller value
will increase the spacing and linearity but decrease
recovered audio and sensitivity.
A data shaping circuit is available and can be coupled to
the recovered audio output of Pin 12. The circuit is a
comparator which is designed to detect zero crossings of
FSK modulation. Data rates of up to 35000 baud are
detectable using the typical application. Hysteresis is
available by connecting a high-valued resistor from Pin 13 to
Pin 14. Values below 120 kn are not recommended as the
input signal cannot overcome the hysteresis.
The meter drive circuitry detects input Signal level by
monitoring the limiting of the limiting amplifier stages.
Figure 2 shows the unloaded current at Pin 9 versus input
power. The meter drive current can be used directly (RSSI)
or can be used to trip the carrier detect circuit at a specified
input power. To do this, pick an RF trip level in dBm. Read the
corresponding current from Figure 2 and pick a resistor such
that:
R9 =0.64 Vdc / 19
Hysteresis is available by connecting a high-valued
resistor RH between Pin 9 and 10. The formula is:
Hysteresis =VCcI(RH x 10- 7) dB
8-65
II
:
®
MOTOROLA
MC3356
Wideband FSK Receiver
The MC3356 includes Oscillator, Mixer, Limiting IF Amplifier, auadrature
Detector, Audio Buffer, Squelch, Meter Drive, Squelch Status output, and
Data Shaper comparator. The MC3356 is designed for use in digital data
communciations equipment.
• Data Rates up to 500 kilobaud
• Excellent Sensitivity: - 3 dB Limiting Sensitivity
30llVrms @ 100 MHz
• Highly Versatile, Full Function Device, yet Few External Parts are
Required
• Down Converter Can be Used Independently - Similar to NE602
WIDEBAND
FSK
RECEIVER
SEMICONDUCTOR
TECHNICAL DATA
-
PSUFFIX
PLASTIC PACKAGE
CASE 738
OW SUFFIX
PLASTIC PACKAGE
CASE 751D
(S0-20L)
Figure 1. Representative Block Diagram
RF
Vee
PIN CONNECTIONS
RF
Ground
20;..;
,..-_ _ _ _--F
19
f--o
RF
Input
RFGround
Ground
OSCEmitter
~=,-,,;;;:=:=-r""'---'-o Data
Output
Vee
ose Collector
RFVee
Mixer Output
Ceramic
Filter
15
14
*' _
Squelch
Status
Hysteresis
~
12
10
Squelch
Adjust
(Meter)
IFVce
15 Squelch Status
LimHerlnput
14 Squelch Control
LimHerBias
13 Buffered Output
Limiter Bias
12 Demodulator
Filter
Quad Bias
11 Quad Input
11
Quadrature Detector
r---,
'Ii k
I I an
ORDERING INFORMATION
Device
MC3356DW
Vec
H6
MC3356P
Operating
Temperature Range
TA = - 40 to +85°C
Package
S0-20L
Plastic DIP
MOTOROLA ANALOG IC DEVICE DATA
MC3356
MAXIMUM RATINGS
Rating
Power Supply Voltage
Operating Power Supply Voltage Range (Pins 6, 10)
Operating RF Supply Voltage Range (Pin 4)
Symbol
Value
Unit
VeC(max)
15
Vdc
Vee
3.0 to 9.0
Vdc
RFVee
3.0 to 12.0
Vdc
Junction Temperature
TJ
150
°e
Operating Ambient Temperature Range
TA
-40to+85
°e
Tstg
- 65 to + 150
°e
PD
1.25
W
Storage Temperature Range
Power Dissipation, Package Rating
=
ELECTRICAL CHARACTERISTICS (Vee 5.0 Vdc, 10
TA = 25°C, test circuit 01 Figure 2, unless otherwise noted.)
=100 MHz, losc =110.7 MHz, t.1 =±75 kHz, Imod =1.0 kHz, 50 () source,
Characteristics
Min
Typ
Max
Unit
-
20
25
mAdc
Input lor - 3 dB limiting
-
30
-
I1Vrms
" (S+N)
Input I or 50 dB
qUieting
-N-
-
60
-
I1Vrms
Mixer Voltage Gain, Pin 20 to Pin 5
-
Drain Current Total, RF Vee and Vee
2.5
-
Mixer Input Resistance, 100 MHz
-
260
-
()
Mixer Input Capacitance, 100 MHz
-
5.0
-
pF
Mixer/Oscillator Frequency Range (Note 1)
-
0.2 to 150
-
MHz
IF/Quadrature Detector Frequency Range (Note 1)
-
0.2 to 50
-
MHz
AM Rejection (30% AM, RF Vin = 1.0 mVrms)
-
50
-
dB
Demodulator Output, Pin 13
-
Vrms
Meter Drive
-
0.5
7.0
-
IlAIdB
Squelch Threshold
-
0.8
-
Vdc
NOTE: 1. Not taken in Test Circuit of Figure 2; new component values required.
Figure 2. Test Circuit
Squelch
Status
Demod
Out
Data Output
47k
100 MHz
~
51
-=
-=
11 -110.7 MHz, OAI1H
7T #22,3116 Form
w/slug & can
L2 -10.7 MHz, 1.511H
20T #30,3116 Form
w/slug & can
T1-muRata
SFEl 0.7 MA5-Z
or
KYOCERA
KBF10.7MN-MA
47k
130k
3.3k
3.0k
10k
3.3 k
20
-=
19
RF Input
Ground
RF
Gnd
OSC
EM.
Data
Output
OSC
COL.
16
Comp(-)
15
Squelch
Status
14
Squelch
Control
Domed
Out
RF
VCC
0.01
5.6 pF
15 pF
17
Comp(+)
t
MOTOROLA ANALOG IC DEVICE DATA
::f
l1
330
8-67
II
MC3356
Figure 3. Output Components of Signal,
Noise, and Distortion
10
I· I I
III II
S+N+D
![ -10 V~ -20
5
~ -30 i"""'";::
!;;r
;rl-40
a:
-50
--
-60
0.01
Figure 4. Meter Current versus Signal Input
700
V
~
1
10= 100 MHz
Im = 1.0 kHz
lif =±75kHz
r-
~ 500
z
a::
u
a: 200
I
~
N
0.1
400
~
w
a: 300
a:
::l.
N+D
~
600
:::;; 100
1.0
10
0
0.010
0.1
INPUT (mVrms)
1.0
10
PIN 20 INPUT (mVrms)
100
1000
GENERAL DESCRIPTION
This device is intended for single and double conversion
VHF receiver systems, primarily for FSK data transmission
up to 500 K baud (250 kHz). It contains an OSCillator, mixer,
limiting IF, quadrature detector, signal strength meter drive,
and data shaping amplifier.
The oscillator is a common base CCllpitis type which can
be crystal controlled, as shown in Figure 1, or L-G controlled
as shown in the other figures. At higher VCC, it" has been
operated as high as 200 MHz. A mixer/oscillator voltage gain
of 2 up to approximately 150 MHz, is readily achievable.
The mixer functions well from an input signal of
10 j.tVrms, below which the squelch is unpredictable, up to
about 10 mVrms, before any evidence of overload.
Operation up to 1.0 Vrms input is permitted, but non-linearity
of the meter output is incurred, and some oscillator pulling is
suspected. The AM rejection above 10 mVrms is degraded.
The limiting IF is a high frequency type, capable of being
operated up to 50 MHz. It is expected to be used at 10.7 MHz
in most cases, due to the availability of standard ceramic
resonators. The quadrature detector is internally coupled to
the IF, and a 5.0 pF quadrature capaCitor is internally
provided. The -3dB limiting sensitivity of the IF itself is
approximately 50 j.tV (at Pin 7), and the IF can accept signals
up to 1.0 Vrms without distortion or change of detector
quiescent dc level.
The IF is unusual in that each of the last 5 stages of the
6 state limiter contains a signal strength sensitive, current
sinking device. These are parallel connected and buffered to
produce a signal strength meter drive which is fairly linear for
IF input signals of 10 j.tV to 100 mVrms (see Figure 4).
A simple squelch arrangement is provided whereby the
meter current flowing through the meter load resistance flips
a comparator at about 0.8 Vdc above ground. The signal
strength at which this occurs can be adjusted by changing
the meter load resistor. The comparator (+) input and output
are available to permit control of hysteresis. Good positive
8-68
action can be obtained for IF input signals of above 30
j.tVrms. The 130 k.Q resistor shown in the test circuit provides
a small amount of hysteresis. Its connection between the
3.3 k resistor to ground and the 3.0 k pot, permits adjustment
of squelch level without changing the amount of hysteresis.
The squelch is internally connected to both the
quadrature detector and the data shapero The quadrature
detector output, when squelched, goes to a dc level
approximately equal to the zero signal level unsquelched.
The squelch causes the data shaper to produce a high (VCC)
output.
The data shaper is a complete "floating" comparator,
with back to back diodes across its inputs. The output of the
quadrature detector can be fed directly to either input of this
amplifier to produce an output that is either at VCC or VEE,
depending upon the received frequency. The impedance of
the biasing can be varied to produce an amplifier which
"follows" frequency detuning to some degree, to prevent data
pulse width changes.
When the data shaper is driven directly from the
demodulator output, Pin 13, there may be distortion at Pin 13
due to the diodes, but this is not important in the data
application. A useful note in relating highllow input frequency
to logic state: low IF frequency corresponds to low
demodulator output. If the oscillator is above the incoming
RF frequency, then high RF frequency will produce a logic
low (input to (+) input of Data Shaper as shown in Figures 1
and 2).
APPLICATION NOTES
The MC3356 is a high frequency/high gain receiver that
requires following certain layout techniques in designing a
stable circuit configuration. The objective is to minimize or
eliminate, if possible, any unwanted feedback.
MOTOROLA ANALOG IC DEVICE DATA
MC3356
Figure 5. Application with Fixed Bias on Data Shaper
Car. DetOut
OVor4.0V
~
-=
3.3 k
:}"& ,.
I
I
L.~_..J
20
RF Input
19
18
Ground
Data
Output
11
17
Comp(+)
Squelch
Status
Squelch
Control
Demod
Out
Demod
Fiher
Quad
Input
MC3356
RF
Gnd
OSC
EM.
OSC
COL.
Limiter
Bias
Limiter
Bias
Quad
Bias
10
S.OV
II
82
APPLICATION NOTES (continued)
Shielding, which includes the placement of input and
output components, is important in minimizing electrostatic or
electromagnetic coupling. The MC3356 has its pin
connections such that the circuit designer can place the
critical input and output circuits on opposite ends of the chip.
Shielding is normally required for inductors in tuned circuits.
The MC3356 has a separate VCC and ground for the RF
and IF sections which allows good external circuit isolation by
minimizing common ground paths.
Note that the circuits of Figures 1 and 2 have RF,
Oscillator, and IF circuits predominantly referenced to the
plus supply rails. Figure 5, on the other hand, shows a
suitable means of ground referencing. The two methods
produce identical results when carefully executed. It is
important to treat Pin 19 as a ground node for either
approach. The RF input should be "grounded" to Pin 1 and
then the input and the mixer/oscillator grounds (or RF Vce
bypasses) should be connected by a low inductance path to
Pin 19. IF and detector sections should also have their
MOTOROLA ANALOG IC DEVICE DATA
bypasses returned by a separate path to Pin 19. VCC and
RF VCC can be decoupled to minimize feedback, although
the configuration of Figure 2 shows a successful
implementation on a common 5.0 V supply. Once again, the
message is: define a supply node and a ground node and
return each section to those nodes by separate, low
impedance paths.
The test circuit of Figure 2 has a 3 dB limiting level of
30 iJ,V which can be lowered 6 db by a 1:2 untuned
transformer at the input as shown in Figures 5 and 6. For
applications that require additional sensitivity, an RF amplifier
can be added, but with no greater than 20 db gain. This will
give a 2.0 to 2.5 iJ,V sensitivity and any additional gain will
reduce receiver dynamic range without improving its
sensitivity. Although the test circuit operates at 5.0 V, the
mixer/oscillator optimum performance is at 8.0 V to 12 V. A
minimum of 8.0 V is recommended in high frequency
applications (above 150 MHz), or in PLL applications where
the oscillator drives a prescaler.
8-69
MC3356
Figure 6. Application with Self-Adjusting Bias on Data Shaper
5.0V
Data
Out
Car. Dot. Out
OVor4.0V
130k
3.3k
15 k
~_1~~ ~ ~~1~0_k~~ ~~ L1~5 ~~ ~1~3 ~~12~~~1~1~~~----------'
__
-=
RF Input
__
Ground
__
Data
Output
Comp(+)
__
__
Comp(-) Squelch
Status
__
Squelch
Control
Demod
Out
__
Demod
Fi"er
Quad
Input
f= 10.7
150 pF
APPLICATION NOTES (continued)
EI
Depending on the external circuit, inverted or
noninverted data is available at Pin 18. Inverted data makes
the higher frequency in the FSK signal a "one" when the local
oscillator is above the incoming RF. Figure 5 schematic
shows the comparator with hysteresis. In this circuit the dc
reference voltage at Pin 17 is about the same as the
demodulated output voltage (Pin 13) when no signal is
present. This type circuit is preferred for systems where the
data rates can drop to zero. Some systems have a low
frequency limit on the data rate, such as systems using the
MC3850 ACIA that has a start or stop bit. This defines the
low frequency limit that can appear in the data stream.
8-70
Figure 5 circuit can then be changed to a circuit configuration
as shown in Figure 6. In Figure 6 the reference voltage for
the comparator is derived from the demodulator output
through a low pass circuit where 't is much lower than the
lowest frequency data rate. This and similar circuits will
compensate for small tuning changes (or drift) in the
quadrature detector.
Squelch status (Pin 15) goes high (squelch off) when the
input signal becomes greater than some preset level set by
the resistance between Pin 14 and ground. Hysteresis is
added to the circuit externally by the resistance from Pin 14to
Pin 15.
MOTOROLA ANALOG Ie DEVICE DATA
!!l:
Figure 7. Internal Schematic
a
.
>
»
I
::0
o
~
~
z
»
....
oG)
(')
c
~
o
)
1.0k
i'..:
1.0k
~
ICP
'"
~
.1'-:'
r~
1.0k
5.0k
~"ro,
~
IT
1.0k
c
»~
5.0k
330
T
330
~
'"'
20k
~
'"
1
12
10k
92
...
tr.1,;;+t.
'91
"·0
r
•
1v'
1
J
W
93
86
~
r1
~r-J v.
85
~~.
,"
, 0~-r,.
20pF
'"' ~
.. ,
tl" if-
20k
10
m
5.0k
ro,
~
~~
!O
."
16
,
:s:
11
o
Co)
Co)
6
13
1.0k
1.Ok
1.0k
1.0k
1.0k
~
1.Ok
1.0k
1.Ok
~
16
17
1.0k
1.0k
1.0k
~ ~1t{
J:t~~
21
J:f
23
50k
V
~
~6
f-.::
;:
50pF
50k
il
~
K
5~
58
'-l
~
32
~~
~
r;9
r...;
" 27
64
'l~
3~
rt
2:
9
~
10k
10k
10k
10k
,
1.0k
~
~
40
43
42
1.0k
'-l
H~
28
~ ~
~
1.0k
36
25
I
0--
1.0k
{10k
1.0k
2.5k
46
, 45
48
47
,
57
,,-1
'-l
~
55 '"'"'
135
135
135
'-l
56
~
54
'-l
53"-1
~
~
,,1
135
135
34
,
5i-i 51'"'1 50
,...-1 ,,-i
49
,
...t
\
:5~ '35
135
~
135
225
,
i
II
®
MOTOROLA
MC3357
Low Power Narrowband FM IF
· .. includes Oscillator, Mixer, Limiting Amplifier, Quadrature Discriminator,
Active Filter, Squelch, Scan Control, and Mute Switch. The MC3357 is
designed for use.in FM dual conversion communications equipment.
• Low Drain Current (3.0 mA (Typical) @ VCC
=6.0 Vdc)
LOW POWER
FMIF
• Excellent Sensitivity: Input Limiting Voltage (- 3.0 dB) 5.0 flV (Typical)
=
• Low Number of Extemal Parts Required
SEMICONDUCTOR
TECHNICAL DATA
• Recommend MC3372 for ReplacemenVUpgrade
PSUFFIX
PLASTIC PACKAGE
CASE 648
o SUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
PIN CONNECTIONS
Figure 1. Representative Block Diagram
Vee
Mixer
OU1put
Umiter
Input
Umiter
OU1put
Quad
Input
ORDERING INFORMATION
Device
MC3357D
MC3357P
8-72
Operating
Temperature Range
TA = - 30 to +70°C
Package
S0-16
Plastic DIP
MOTOROLA ANALOGIC DEVICE DATA
MC3357
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted)
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
4
VCc(max)
12
Vdc
Operating Supply Voltage Range
4
VCC
4t08
Vdc
Detector Input Voltage
8
-
1.0
Vp-p
Input Voltage (VCC ~ 6.0 Volts)
16
V16
1.0
VRMS
Mute Function
14
V14
-0.5 to 5.0
Vpk
Junction Temperature
TJ
150
°c
Operating Ambient Temperature Range
-
TA
-30to+70
°C
Storage Temperature Range
-
Tsta
-65to+150
°C
ELECTRICAL CHARACTERISTICS (VCC = 6.0 Vdc, 10 = 10.7 MHz, AI = ±3.0 kHz, lmod = 1.0 kHz, TA = 25°C, unless otherwise noted.)
Characteristic
Drain Current
Squelch Off
Squelch On
Pin
Min
Typ
4
-
2.0
3.0
5.0
5.0
10
J.lV
3.0
-
Vdc
-
mVrms
-
-
400
9
200
350
Input limiting Voltage (- 3 dB limiting)
16
Detector Output Voltage
9
Detector Output Impedance
Recovered Audio Output Voltage (Vin = 10 mY)
Max
Unit
-
rnA
Q
Filter Gain (10kHz) (Vin = 5 mY)
-
40
46
-
dB
Filter Output Voltage
11
1.8
2.0
2.5
Vdc
Trigger Hysteresis
-
-
100
-
mV
Mute Function Low
14
-
15
50
Q
Mute Function High
14
1.0
10
-
MQ
Scan Function Low (Mute Off)
(V12 = 2 Vdc)
13
-
0
0.5
Vdc
Scan Function High (Mute On)
(V12 = Gnd)
13
5.0
-
-
Vdc
Mixer Conversion Gain
3
-
20
dB
16
-
-
Mixer Input Resistance
3.3
-
kQ
Mixer Input Capacitance
16
-
2.2
-
pF
MOTOROLA ANALOG IC DEVICE DATA
8-73
11
MC3357
Figure 2. Test Circuit
VCC= 6.0Vdc
14
1-------0
muRata
CFU
455D
lOOnF
2.0k
100nF
1-......- - - - - 0 OpAmpOulpul
47k
390k
1.0~F
f---+--'1,,,.O,,,k---1+
E----<> Filler In
r---'lArv-.....- o
AudioOut
~O.Ol~
Lp=1.OmH
Cp=100pF
Rp=100k.Q
CIRCUIT DESCRIPTION
The MC3357 is a low power FM IF circuit designed
primarily for use in voice communication scanning receivers.
The mixer-oscillator combination converts the input
frequency (e.g., 10.7 MHz) down to 455 kHz, where, after
external bandpass filtering, most of the amplification is done.
The audio is recovered using a conventional quadrature FM
detector. The absence of an input Signal is indicated by the
presence of noise above the desired audio frequencies. This
"noise band" is monitored by an active filter and a detector. A
squelch trigger circuit indicates the presence of a noise (or a
tone) by an output which can be used to control scanning. At
the same time, an internal switch is operated which can be
used to mute the audio.
The oscillator is an internally-biased Colpitts type with the
collector, base, and emitter connections at Pins 4, 1, and 2
respectively. A crystal can be used in place of the usual coil.
The mixer is doubly-balanced to reduce spurious
responses. The input impedance at Pin 16 is set by a 3.0 kQ
internal biasing resistor and has low capacitance, allowing
the circuit to be preceded by a crystal filter. The collector
output at Pin 3 must be dc connected to B +, below which it
can swing 0.5 V.
After suitable bandpass filtering (ceramic or LC), the signal
goes to the input of a five-stage limiter at Pin 5. The output of
the limiter at Pin 7 drives a multiplier, both internally directly,
8-74
and extemally through a quadrature coil, to detect the FM. The
output at Pin 7 is also used to supply dc feedback to Pin 5. The
other side of the first limiter stage is decoupled at Pin 6.
The recovered audio is partially filtered, then buffered,
giving an impedance of around 400 n at Pin 9. The signal still
requires de-emphasis, volume control and further
amplification before driving a loudspeaker.
A simple inverting op amp is provided with an output at Pin
11 providing dc bias (externally) to the input at Pin 10 which is
referred internally to 2.0 V. A filter can be made with external
impedance elements to discriminate between frequencies.
With an external AM detector, the filtered audio signal can be
checked for the presence of noise above the normal audio
band, or a tone signal. This information is applied to Pin 12.
An external positive bias to Pin 12 sets up the squelch
trigger circuit such that Pin 13 is low at an impedance level of
around 60 kn, and the audio mute (Pin 14) is open circuit. If
Pin 12 is pulled down to 0.7 V by the noise or tone detector,
Pin 13 will rise to approximately 0.5 Vdc below supply where
it can support a load current of around 500 I-!A and Pin 14 is
internally short-circuited to ground. There is 100 mV of
hysteresis at Pin 12 to prevent jitter. Audio muting is
accomplished by connecting Pin 14 to a high-impedance
ground-reference point in the audio path between Pin 9 and
the audio amplifier.
MOTOROLA ANALOG IC DEVICE DATA
Figure 3. Circuit Schematic
3:
~
3
o
>:
»
z
10k
10k
30k
8
<
(';
m
~
c
!:j
l>
..~~ r-lJ:-)-
r'
hi..
(';
~~
SDk
K5
50k
~
10
~
~
~6
1~
1~
f.:
17 '
K
30k
30k
5.0k
30k
220k
10k
15 k
20k
15k
lOOk
13
K20
'i
3.0k
r'8
16
L
f-
22
2CJ
15k
»
c
m
20k
4
;;
~
:Jl
15k
F
---{24
K19
14
12
K8
22k
0-
~
1L,
50k
C,
470
s::
50 k
15
4~
28 ,.
10 k
OOk
10k
10k
10 k
10k
10k
10k
10k
10k
29 ,.
30 ,
33~
5
31
6.2k
35
36
33k
37~40
33k
33k
.....
t
II
~
50 k
J.
."
'"
,,]T'-.." ~~I
J.
5= ~~
9
10k
33k
UI
~3
!
10k
10
k
120k
~
fl
r
"'l
5~
lOOk
Cl!
"'l
~
w
UI
?8
~~
o
w
."
®
ItIIOTOROLA
MC3359
Low Power Narrowband FM IF
· .. includes oscillator, mixer, limitin'g amplifier, AFC, quadrature
discriminator, op/amp, squelch, scan control, and mute switch. The MC3359
is designed to detect narrowband FM signals using a 455 kHz ceramic filter
for use in FM dual conversion communications equipment. The MC3359 is
similar to the MC3357 except that the MC3359 has an additional limiting IF
stage, an, AFC output, and an opposite polarity Broadcast Detector. The
MC3359 also requires fewer external parts. For low cost applications
requiring VCC below 6.0 V, the MC3361 BP,BD are recommended. For
. applications requiring a fixed, tuned, ceramic quadrature resonator, use the
MC3357. For applications requiring dual conversion and RSSI, refer to these
devices; MC3335, MC3362 and MC3363.
• Low Drain Current: 3.6 mA (Typical) @ Vee
=6.0 Vdc
• Excellent Sensitivity: Input Limiting Voltage - 3.0 dB 2.0 /-LV (Typical)
=
• Low Number of External Parts Required
ORDERING INFORMATION
Device
MC3359DW
MC3359P
SEMICONDUCTOR
TECHNICAL DATA
-
PSUFFIX
PLASTIC PACKAGE
CASE 707
Figure 2. Pin Connections and
Functional Block Diagram
Package
S0-20L
TA =-30 to +70°C
FMIF
DWSUFFIX
PLASTIC PACKAGE
CASE751D
(S0-20L)
• For Low Voltage and RSSI, use the MC3371
Operating
Temperature Range
HIGH GAIN
LOW POWER
C~I{
1
RF
I",.
Plastic DIP
Scan
Coni'"
limiter
Input
DecoupImg
Figure 1. Simplified Application in a Scanner Receiver
14
6
-
~:
0 ",,",
Quadral\Jl9
Input
Demodulator
Filter
Vcc=6.0Vdc
10 7 MHz
I"",
CASE 707
Vcc",SOVdc
5Ik
16
Mule
15
9canControi
MC3359
14
•
NCI
17
elchl
20NC
19
RF
Inpol
18
Gnd
17
Audio
MUle
16
Scan
CenlTol
1lI
15
14
........'"
Frequency
13
Co",",1
10
RecoveredAudKl
12
11
Squelch
Input
Filter
Output
Filter
Input
Demod
Output
I- ~~:ered
CASE751D
8-76
MOTOROLA ANALOG IC DEVICE DATA
MC3359
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted)
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
4
VCc(max)
12
Vdc
Operating Supply Voltage Range
4
VCC
6t09
Vdc
Input Voltage (VCC;;' 6.0 Volts)
18
V18
1.0
Vrms
Mute Function
16
V16
-0.7to 12
Vpk
Junction Temperature
-
TJ
150
°C
Operating Ambient Temperature Range
-
TA
-30to + 70
°C
Tsto
-65to+150
°C
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (VCC = 6.0 Vdc, 10 = 10.7 MHz, AI = ± 3.0 kHz, Imod = 1.0 kHz, 50 n source, TA = 25°C test circuit
01 Figure 3, unless otherwise noted)
Characteristics
Min
Typ
Max
Units
-
-
3.6
5.4
6.0
7.0
mA
Input lor 20 dB Quieting
-
8.0
-
I!Vrms
Input lor - 3.0 dB Limiting
-
2.0
-
I!Vrms
Mixer Voltage Gain (Pin 18 to Pin 3, Open)
-
46
-
Mixer Third Order Intercept, 50 n Input
-
-1.0
-
dBm
Mixer Input Resistance
-
3.6
-
kQ
Squelch Off
Squelch On
Drain Current (Pins 4 and 8)
Mixer Input Capacitance
Recovered Audio, Pin 10
(Input Signal 1.0 mVrms)
-
2.2
-
pF
450
700
-
mVrms
Detector Center Frequency Slope, Pin 10
-
0.3
-
V/kHz
AFC Center Slope, Pin 11, Unloaded
-
12
-
V/kHz
Filter Gain (test circuit 01 Figure 3)
40
51
-
dB
Squelch Threshold, Through 10K to Pin 14
-
0.62
-
Vdc
-
0.01
2.4
1.0
-
mA
5.0
1.5
10
n
Mn
Scan Control Current, Pin 15
Pin 14 - High
-Low
Mute Switch Impedance
Pin 16 to Ground
Pin 14 - High
-Low
2.0
-
-
I!A
Figure 3. Test Circuit
Input
10.7 MHz
17
ceramic
Filter
muRata
CFU455D
or
Kyocera
KBF455P-'2OA
2.4k
16
Audio Gen.
0.7 VPi'
15
Squelch Input
14
10k
op AJ1lp Output
13
1.0M
12
L.....~O:.-....-./
r-
-Yvv -- -......
OpAmplnput
1.0~F
AFCOulput
11
Audio Output
10
7.5k
MOTOROLA ANALOG IC DEVICE DATA
8-77
II
MC3359
Figure 4. Mixer Voltage Gain
Figure 5. Limiting IF Frequency Response
400
Input fa = 10.7 MHz Output fO = 455 kHz
Output taken at
Pin 3 wnh filter
removed (open)
VCC=9~1I1
/
V
I I IIII
-10
)1tt11J
mE
~~ -20
VCC 6.OV= F=
_
=>c:;
~ ~ -30 -
5
O~
/
20
;d '5
I
I IIIIIII
I
IIF Inpullor -3 dB Llmilin.2,
a:~
-50
-60
0.1
10
1.0
§ -40
/10'.
/
/
V
"....2:-c
=>
Q.
/
....
=>
0
5.0
0
o
V
--
o
o
III
~ ~
~-10
'5
Derived using optimum UC
-20 r- oscillator values and holding
IF frequency at 455 kHz
~ -30
~
8.0
10
~
=>
-20
o
~-30
-50
S + Nil (!;k'AM)
N
-50
100
-60
0.001
II
- - 25°C
---75°C VCC=6.0Vdc
~ ~
lli -40
-40
111111
S+N ,~~KHzFM
!i
1.0
10
FREQUENCY [MHz]
6.0
Figure 9. Overall Gain, NOise, and AM Rejection
10
8-78
.-/
V Detector Output Pin 10
-10 -8.0 -6.0 -4.0 -2.0 0
2.0 4.0
RELATIVE FREQUENCY [kHz]
10
10
-60
0.1
/'"
3.0
1.0
~ -10
lI!
. /V
4.0
Figure 8. Relative Mixer Gain
~
r
2.0
3rd Order 1M Products/
-70 -60 -50 -40 -30 -20 -10
INPUT, 50 n [dBm]
AFC Output Pin 11
6.0
II
-,,/
/V
-50
100
Vcc = 6.0 Vdc
7.0
//
./
Desired Produc!y V
V
/
5-30
-60
-90 -80
I
10
Figure 7. Detector and AFC Responses
A
10
r-
I
8.0
/
Output taken at
E
0 r-- r- Pin 3 wh filter
ID
removed
:!;!. -10
r-VCC =6.0 Vdc
-ti
1.0
FREQUENCY [MHz]
20
"'! -20
/
/
1~l1vW-IIIIL
-70
0.1
40
Figure 6. Mixer Third Order
Intermodulation Performance
I
V
§>w~ -40 -
INPUT, 50 n (mVrms)
~
1\
Terminals not
available on
standard device.
6.0
4.0
0.04
..........
~...J
/ )'
10
IFOutput
I I IIIIIII
Response Taken on
a special prototype.
0.01
II
0.1
1.0
INPUT [mVrms]
10
100
MOTOROLA ANALOG IC DEVICE DATA
MC3359
Figure 10. Output Components of Signal,
Noise, and Distortion
10
3<.
S+N+D
111111111111
-20
;::
5w
7.0
10 ~ '1'~.7 MHz
Im:l kHz
AI: ±3.0 kHz
Test circuit of
Figure 3.
~
-10
l-
=>
a.
l=>
0
w
~
-30
N+D
-40
II
l"-
a:
0.01
0.1
1.0
10
:::::r-
6.0
;::- 5.0
z
w
~ 4.0
=>
~ 3.0
:..J
a.
g, 2.0
en
1.0
II
-60
0.001
-
r- ICC, Mute On
~
ICC, Mute Off
0.7
- :::1!3
I--
0.4
0.3
5
g
o
0.2 ~
0.1
o
100
-
I
I
Audio Output
1
N
-50
0.8
8.0
111111111
0
ill
Figure 11. Audio Output and Total Current
Drain versus Supply Voltage
4.0
5.0
6.0
7.0
o
8.0
9.0
INPUT [mVrms]
VCC, SUPPLY VOLTAGE (Vdc)
Figure 12. UC Oscillator, Temperature and
Power Supply Sensitivity
Figure 13. Op Amp Gain and Phase Response
VCC, SUPPLY VOLTAGE [Vdc]
10.706
58
"'" ""
-
10.704
10.702
N
:r 10.700
~
>0
zw 10.698
=>
0
w 10.696
60
59
61
70
".
~
~
"'.......... ~
..............
Phase
![40
z
~ 30
r-......" r--...VCC
Ti~ :::--..... ~
10.694
10.692
30
40
50
60
~
o
1.0K
10K
z
i:!:
t5
C':
«
0
100
70
50
_
C5
2
1!I~c~4~t~~~I~~II!;~1.0 g~
~I-+-H--++---+-+--iI--+I"'-..~d-+-+-H-l0.3
~
0.5
'---L_--'_.....L...--'---I.-L-'-"LJO.1
20
30
70
100
50
OSCILLATOR FREQUENCY [MHz]
'--1......1~...I....L_ _
7.0
10
MOTOROLA ANALOG IC DEVICE DATA
II
I I
0.8
10M
-
Von
i:!: 5
~ 0.4
-
=>
R2
R3
3901<
SOV
-
13
Villi!
12
v.
=-.B!....
'At',I
R2=4Q2~lR~R3
\
\
0.2
i-'
1.0
18K
nloe1
Rl
o
o
Cl
"" ",1:""'"" ' '
Vrms
R3~-Q-
_
··'1.~
Cl
I I I II
GIVEN ro = CENTER FREQUENCY
A(fa) '" GAIN AT CENTER FREQUENCY
.=!, ~ 0.6
w ~
0.7
5.0
o
1.0M
lOOK
FREQUENCY [Hz]
1.0
2.0:;:_
30
r-....
20 I-H-+++--+--+--j--t---t~".rl-+--t--I0.2
10
30
Figure 15. The Op Amp as a Bandpass Filter
V~2
~H
~~
-~
1
~~
'"
VpCtI6i~X~C
10
~~VC110
I--f----=F""I-"'-L~
w
0
150
USE CIRCUIT ABOVE
FOR OPEN LOOP GAIN
AND PHASE (SOUD LINEB)
DonED
WITH CIRCUIT VALUES
OF FIGURE 3.
Figure 14. UC Oscillator Recommended
Component Values
___--+--f--_+_
300 I-HI--+--+-p.,L........
-I"~ 200
"I'.
180
13
v.
~ain
~ ::::~
AMBIENT TEMPERATURE [OC]
1000
700
500
12
cURVEs'J1N
20
70
"""-'0
1111
..........
10.690
20
:s
-
50
"M
"'~
60
a:
I.L
62
2.0
"
5.0
10
20
FREQUENCY [kHz]
50
100
8-79
II
~
Figure 16. Representative Schematic Diagram
r----------------------------------r---------r----------I
1
3
12
13
1
14
I
1
4
I
I
Y077
01
I
I
I
·1
15
v"
18
'-I
36k
O~•
¥
K063
012
33k
35k
33k
33k.(:33k
16
Y067
.
068
~013
I
If062~7k
15k
I
I
I
1
I
r'Q69
il061
"'Q14
33k
1
070
I ~11
I
01-d
09
I
I
I
50k
I
1
I
I _______________ ~~~-~~_____________ J.----~~p---l-~~~~~O~ -1---1
I
I
I
3:
1
I
:u
o
1
a
>
?Z
)00
5
o
c;)
c
~
m
c
~
)Ii
l
limning IF Amplifler
I
II
10k
10k
10k
10k
10k
10k
10k
10k
10k
I
Detector and AFC
10k
I
I
1
I 7~~~~~~===F~~====i===~~~
II
10 k
33 k
33k
33k
33k
33k
10k
~o
17
I
I
1
ask
5k
IL _________________________________
6
1______________
~
~
______
~
s::
oCo)
Co)
UI
CD
MC3359
CIRCUIT DESCRIPTION
The MC3359 is a low-power FM IF circuit designed
primarily for use in voice-communication scanning receivers.
It is also finding a place in narrowband data links.
In the typical application (Figure 1), the mixer-oscillator
combination converts the input frequency (10.7 MHz) down
to 455 kHz, where, after external bandpass filtering, most of
the amplification is done. The audio is recovered using a
conventional quadrature FM detector. The absence of an
input signal is indicated by the presence of noise above the
desired audio frequencies. This "noise band" is monitored by
an active filter and a detector. A squelch-trigger circuit
indicates the presence of noise (or a tone) by an output which
can be used to control scanning. At the same time, an
internal switch is operated which can be used to mute the
audio.
APPLICATIONS INFORMATION
The oscillator is an internally biased Colpitts type with the
collector, base, and emitter connections at Pin 4, 1 and 2,
respectively. The crystal is used in fundamental mode,
calibrated for parallel resonance at 32 pF load capacitance.
In theory this means that the two capacitors in series should
be 32 pF, but in fact much larger values do not significantly
affect the oscillator frequency, and provide higher oscillator
output.
The oscillator can also be used in the conventional UC
Colpitts configuration without loss of mixer conversion gain.
This oscillator is, of course, much more sensitive to voltage
and temperature as shown in Figure 12. Guidelines for
choosing Land C values are given in Figure 14.
The mixer is doubly balanced to reduce spurious
responses. The mixer measurements of Figure 4 and 6 were
made using an external 50 0 source and the internal 1.8 k at
Pin 3. Voltage gain curves at several VCC voltages are shown
in Figure 4. The Third Order Intercept curves of Figure 6 are
shown using the conventional dBm scales. Measured power
gain (with the 50 0 input) is approximately 18 dB but the
useful gain is much higher because the mixer input
impedance is over 3 kO. Most applications will use a 330 0
10.7 MHz crystal filter ahead of the mixer. For higher
frequencies, the relative mixer gain is given in Figure 8.
Following the mixer, a ceramic bandpass filter is
recommended. The 455 kHz types come in bandwidths from
± 2 kHz to ± 15 kHz and have input and output impedances of
1.5 k to 2.0 k. For this reason, the Pin 5 input to the 6 stage
limiting IF has an internal 1.8 k resistor. The IF has a 3 dB
MOTOROLA ANALOG IC DEVICE DATA
limiting sensitivity of approximately 100 IlV at Pin 5 and a
useful frequency range of about 5 MHz as shown in Figure 5.
The frequency limitation is due to the high resistance values
in the IF, which were necessary to meet the low power
requirement. The output of the limiter is internally connected
to the quadrature detector, including the 10 pF quadrature
capacitor. Only a parallel UC is needed externally from Pin 8
to VCC. A shunt resistance can be added to widen the peak
separation of the quadrature detector.
The detector output is amplified and buffered to the audio
output, Pin 10, which has an output impedance of
approximately 300 o. Pin 9 provides a high impedance (50 k)
point in the output amplifier for application of a filter or
de-emphasis capacitor. Pin 11 is the AFC output, with high
gain and high output impedance (1 M). If not needed, it
should be grounded, or it can be connected to Pin 9 to double
the recovered audio. The detector and AFC responses are
shown in Figure 7.
Overall performance of the MC3359 from mixer input to
audio output is shown in Figure 9 and 10. The MC3359 can
also be operated in "single conversion" equipment; i.e., the
mixer can be used as a 455 kHz amplifier. The oscillator is
disabled by connecting Pin 1 to Pin 2. In this mode, the
overall performance is identical to the 10.7 MHz results of
Figure 9.
A simple inverting op amp is provided with an output at
Pin 13 providing dc bias (externally) to the input at Pin 12,
which is referred internally to 2.0 V. A filter can be made with
external impedance elements to discriminate between
frequencies. With an external AM detector, the filtered audio
signal can be checked for the presence of either noise above
the normal audio, or a tone signal.
The open loop response of this op amp is given in
Figure13. Bandpass filter design information is provided in
Figure 15.
A low bias to Pin 14 sets up the squelch-trigger circuit so
that Pin 15 is high, a source of at least 2.0 mA, and the audio
mute (Pin 16) is open--circuit. If Pin 14 is raised to 0.7 V by
the noise or tone detector, Pin 15 becomes open circuit and
Pin 16 is internally short circuited to ground. There is no
hysteresis. Audio muting is accomplished by connecting Pin
16 to a high-impedance ground-reference point in the audio
path between Pin 10 and the audio amplifier. No dc voltage is
needed, in fact it is not desirable because audio "thump"
would result during the muting function. Signal swing greater
than 0.7 V below ground on Pin 16 should be avoided.
8-81
II
:
®
MOTOROLA
MC3362
Low-Power Narrowband
FM Receiver
... includes dual FM conversion with oscillators, mixers, quadrature
discriminator, and meter drive/carrier detect circuitry. The MC3362 also has
buffered first and second local oscillator outputs and a comparator circuit for
FSK detection.
• Complete Dual Conversion Circuitry
LOW-POWER
DUAL CONVERSION
FM RECEIVER
• Low Voltage: VCC = 2.0 to 6.0 Vdc
• Low Drain Current (3.6 mA (Typical)
@
VCC
SEMICONDUCTOR
TECHNICAL DATA
=3.0 Vdc)
• Excellent Sensitivity: Input Voltage 0.6llVrms (Typical)
for 12 dB SINAD
• Externally Adjustable Carrier Detect Function
• Low Number of External Parts Required
PSUFFIX
PLASTIC PACKAGE
CASE 724
• Manufactured Using Motorola's MOSAIC® Process Technology
• MC13135 is Preferred for New Designs
OW SUFFIX
PLASTIC PACKAGE
CASE 751E
(SO·24L)
. ,
.
Figure 2. Pin Connections and
Representative Block Diagram
Figure 1. Simplified Application in a PLL Frequency
Synthesized Receiver
RFlnpul
to 200 MHz .
1st Mixer Input 1
2nd LO Output 2
2nd LO Emitter 3
2nd LO Base 4
From PLL Phase
Detector
3
0.411lH
4
21
Ceramic Filter
455 kHz
2nd Mixer Output 5
Limiter Input 7
Umiter
Decoupling
17 2nd Mixer Input
Lim"er
Decoupling
15 Comparator Output
17
Carrier Detect 11
14 Comparator Input
9
16
Quadrature Coil 12
13 Detector Output
10
15
11
14
12
13
0.1
0.1
10k
ORDERING INFORMATION
Device
MC3362DW
MC3362P
8-82
Operating
Temperature Range
Package
SQ.--24L
TA = - 40 10 +85°C f-P-l-as-Ii-c-D-Ip--!
MOTOROLA ANALOG IC DEVICE DATA
MC3362
MAXIMUM RATING (TA = 25°C, unless otherwise noted)
Pin
Symbol
Value
Power Supply Voltage (See Figure 2)
Rating
6
VCC(max)
7.0
Vdc
Operating Supply Voltage Range (Recommended)
6
VCC
2.0to 6.0
Vdc
1,24
VI-24
1.0
Vrms
-
TJ
150
°c
TA
-40to +85
°c
TstQ
-65to+150
°c
Input Voltage (VCC '" 5.0 Vdc)
Junction Temperature
Operating Ambient Temperature Range
Storage Temperature Range
Unit
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, fo = 49.7 MHz, Deviation = 3.0 kHz, TA = 25°C, Test Circuit of Figure 3,
unless otherwise noted)
Characteristic
Pin
Min
Typ
Max
6
4.5
7.0
mA
Input for -3.0 dB Limiting
-
0.7
2.0
I1Vrms
Input for 12 dB SINAD (See Figure 9)
-
0.6
-
I1Vrms
Series Equivalent Input Impedence
-
450-j350
13
-
350
-
mVrms
Noise Output (RF signal level = 0 mV)
13
Carrier Detect Threshold (below VCe)
10
0.64
Meter Drive Slope
10
-
Drain Current (Carrier Detect Low - See Figure 5)
Recovered Audio (RF signal level = 10 mV)
First Mixer 3rd Order Intercept (Input)
First Mixer Input Capacitance (Cp)
Conversion Voltage Gain, First Mixer
Conversion Voltage Gain, Second Mixer
Dector Output Resistance
13
mVrms
nNdB
-22
-
690
-
n
pF
100
0.7
-
First Mixer Input Resistance (Rp)
n
-
250
-
Input for 20 dB (S + N)/N (See Figure 7)
Units
18
-
21
-
1.4
-
7.2
Vdc
I1Vrms
dBm
dB
kQ
Figure 3. Test Circuit
10.5 Turns
Coilcraft
UNI-l01142
FL1:
muRata CFU455D
or
Toko LFC-4551
0.1
171---+---'
16r----+-----.
10
15
11
14
12
13
0.1
Toko RMC-2A6597HM
FL2:
muRata SFE10.7MA
or
Toko SKI 07M3-AO-l 0
1.0 I1F
Vce 0-_...-----------------_--'1+ r-------Q VEE
NOTE: See AN980 for Additional Design Information.
MOTOROLA ANALOG IC DEVICE DATA
8-83
11
MC3362
Figure 5. Drain Current, Recovered Audio
versus Supply
Figure 4. IMeter versus Input
12
11 -
Vec
~C3362
10
9.0
<::I.
8.0 5.0
4.0
/"
700
ICC. Carr. Det. Low (RF in = 10 mY)
-
5.0
<-
ICC. Carr. Det.IHiQh (RJ in
.§. 4.0
(.')
/'
-
800
7.0
6.0
/"
/'
7.0
~ 6.0
/'
8.0
!:? 3.0
./V
fII
Il
/1
2.0
1.0
3.0
o
2.0
-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30
RF INPUT (dBm)
o
1.0
20
20
10
--
10
Second Mixer Output
~ -30
/"
0-40
0-
First Mixer Input
-50
/
1 1/ ........... 0
A
A V
-60
o
-10
r---
~
M
+-SO
en
I
-70
V
L
-80
-100 -90 -80
8-84
1
o
7.0
8.0
:g
S+N30%AM
"'-.,
N
10k
+;+ 0.01
-SO -40 -30
~
\
2.0
1\' -
CO)
:>
,I
-20 -10
-
~
I-.
3.0
1/3rd Order Interrnod. prjucts I
1-
-70 -60 -50 -40 -30
RF INPUT (dBm)
6.0
Figure 9. Detector Output versus Frequency
/
/'
-60
5.0
4.0
/'i
-50
4.0
-80
-130 -120 -110 -100 -90 -80 -70 -60
RF INPUT (dBm)
//'
1/ -;
./ V
Desired ProductV'
3.0
0.01
~/
./
2.0
MC3362113 10 k
-70
~ ~ RF Input to Transformer
10
!g -30
-40
100
-60
Figure 8. 1st Mixer 3rd Order Intermodulation
-20
:>
200
~
z-4O
Z
~V
~ f/
V
~V
20
~
~ -30
~
~V
~V
o
CO)
300
S+N
a:
-70
-130 -120-110 -100 -90 -80 -70 -60 -SO -40 -30
RF INPUT (dBm)
-10
.....---: ~ ~ PO""
Recovered Audio
~
~ -20
~~
First Mixer Output 'J" V
Second Mixer Input~
E
~ 400 §.
Figure 7. S + N, N, AMR versus Input
Figure 6. Signal Levels
~
-20
~
--
600
~ 500..,
VCC(V)
30
-10
~~
0
1.0
o
-40
-30
-
~~
-20
-10
0
10
20
RELATIVE INPUT FREQUENCY (kHz)
30
40
MOTOROLA ANALOG IC DEVICE DATA
MC3362
Figure 10. PC Board Test Circuit
(LC Oscillator Configuration Used in PLL Synthesized Receiver)
RFlnput
49.67 MHz
50Q
1Bp
1000p
~T-
t
Y
':'
Varactor Control
0.47 11
VCC =2.0 to 7.0 Vdc
f--......- { (keep 0.7 V .. V23 .. VCC)
':'
(This network must be tuned to exactly
10.7 MHz above or below the incoming
RFsignal.
NOTE: The IF is rolled off above 10.7
MHz to reduce L.O. feecllhrough.)
455kHz
Cer. Fitt.
=
10VCC
=
0.1
CRF2 muRata SFA10.7 MF5 or
SFE10.7 or equivalent. Rin Rout
= 330 Q. Crystal filters can be
used but impedance matching will
need to be added to ensure proper
filter characteristics are realized.
0.1
Carrier
Detee!
CRF1 muRata CFU 455X - the X
suffix denotes 6.0 dB bandwidth.
Rin = Rout = 1.5 to 2.0 kQ.
=
II
_t------....I
Recovered
Audio
455kHz
LC Resonator
Figure 10A. Crystal Oscillator Configuration for Single Channel Application
~
20k
u
::i
300
I
VCC
Crystal used is series mode resonant
(no load capacity specified), 3rd overtone.
This method has not proven adequate for
fundamental mode, 5th or 7th overtone crystals.
The inductor and capacitor will need to be
changed for other frequency crystals. See
AN980 for further information.
20 k
I
3B.97 MHz
MOTOROLA ANALOG IC DEVICE DATA
8-85
MC3362··'
Figure 11. Component Placement View'
Showing Crystal Oscillator Circuit
NOTES: 1. Reco.vered Audio. compo~ents r(1ay be deleted when using
data output.
2. Carrier Detect components must be deleted in order to obtain
linear Meter Drive output. With these components in place the
Meter Drive outputs serve only to t~ip the Carrier Detect indicator.
3. Data Output components should be deleted in applications
where only audio modulation is used. For combined audio/data
applications, the 0.047 !tF coupling capacitor will add distortion
to the audio, so a pull-down resistor at pin 13 may be required.
. Figure 11 A. LC Oscillator Component View
5. Meter Drive cannot be used simultaneously wijh Carrier Detect output.
For analog meter drive, remove components labelled "2" and measure
meter current (4-12 !tA) through ammeter to VCC.
6. Either type of oscillator circuit may be used with any output circuit
configuration.
7.LC Oscillator Coil: Coilcral! UNll014210.5turns, 0.41 !tH Crystal
Oscillator circuit: trim coil, 0.68 !tH. Coilcral! MI287-A.
8.0.47 H, Coilcral! MI286-A. Input LC network used to match first mixer
input impedance to 50 U.
4. Use Toko 7MC81282 Quadrature coil.
CIRCUIT DESCRIPTION
The MC3362 is a complete FM narrowband receiver from
antenna input to audio preamp output. The low voltage dual
conversion design yields low power drain, excellent
sensitivity and good image rejection in narrowband voice and
data link applications.
In the typical application (Figure 1), the first mixer
amplifies the signal and converts the RF input to 10.7 MHz.
This IF signal is filtered externally and fed into the second
mixer, which further amplifies the signal and converts it to a
455 kHz IF signal. After external bandpass filtering, the low IF
is fed into the limiting amplifier and detection circuitry. The
audio is recovered using a conventional quadrature detector.
Twice-IF filtering is provided internally:
The input signal level is monitored by meter drive circuitry
which detects the amount of limiting in the limiting amplifier.
The voltage at the meter drive pin determines the state of the
carrier detect output, which is active low.
APPLICATIONS INFORMATION
The first local oscillator can be run using a free-running
LC tank, as a VCO using PLL synthesis, or driven from an
external crystal oscillator. It has been run to 190 MHz: A
buffered output is available at Pin 20. The second local
'. oscillator is a common base Colpitts type which is typically
run at 10.245 MHz under crystal control. A buffered output is
available at Pin 2. Pins 2 and 3 are interchangeable.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 22 dB (typical), respectively, as seen in
Figure 6. Mixer gain is stable with respect to supply voltage.
For both conversions, the mixer impedal'\ces and pin layout
are designed to allow the user to employ low cost, readily
available ceramic filters. Overall sensitivity and AM rejection
are shown in Figure 7: The input level for 20 dB (8 + N)/N is
0.71LV using the two-pole post-detection filter pictured.
'If the first local oscillator (Pins 21 and/or 22) is driven from a
strong external source (100 mVrms). the mixer can be used to
over 450 MHz.
8-86
MOTOROLA ANALOG IC DEVICE DATA
MC3362
Following the first mixer, a 10.7 MHz ceramic band-pass
filter is recommended. The 10.7 MHz filtered signal is then
fed into one second mixer input pin, the other input pin being
connected to Vee. Pin 6 (Vee) is treated as a common point
for emitter-driven signals.
The 455 kHz IF is typically filtered using a ceramic
bandpass filter then fed into the limiter input pin. The limiter
has 10 !LV sensitivity for - 3.0 dB limiting, flat to 1.0 MHz.
The output of the limiter is internally connected to the
quadrature detector, including a quadrature capacitor. A
parallel Le tank is needed externally from Pin 12 to Vee. A 39
kQ shunt resistance is included which determines the peak
separation of the quadrature detector; a smaller value will
increase the spacing and linearity but decrease recovered
audio and sensitivity.
A data shaping circuit is available and can be coupled to
the recovered audio output of Pin 13. The circuit is a
comparator which is designed to detect zero crossings of
FSK modulation. Data rates are typically limited to 1200 baud
to ensure data integrity and avoid adjacent channel "splatter."
Hysteresis is available by connecting a high valued resistor
from Pin 15 to Pin 14. Values below 120 kn are not
recommended as the input signal cannot overcome the
hysteresis.
The meter drive circuitry detects input signal level by
monitoring the limiting amplifier stages. Figure 4 shows the
unloaded current at Pin 10 versus input power. The meter
drive current can be used directly (RSSI) or can be used to
trip the carrier detect circuit at a specified input power. To do
this, pick an RF trip level in dBm. Read the corresponding
current from Figure 4 and pick a resistor such that:
R10 "'" 0.64 Vdc / 110
Hysteresis is available by connecting a high valued resistor
RH between Pins 10 and 11. The formula is:
Hysteresis
=Vecl(RH x 10 - 7) dB
Figure 12. Circuit Side View
II
jool~----------- 4" ----------...,~~I
MOTOROLA ANALOG IC DEVICE DATA
8-87
II
~
Figure 13. Representative Schematic Diagram
23
8 1
e
lOon
210--+
~.
bias
8
e
ee
$
9 9$
e$~
8
9
10~~--------------------------------+---~~
12
11
s::
o
i
N
a
==
:II
o
~
~
§
(;
c
m
<
(;
m
c
!:i)Ii
13
14
bias
I
16
VEE
®
MOTOROLA
MC3363
Low Power Dual
Conversion FM Receiver
The MC3363 is a single chip narrowband VHF FM radio receiver. It is a dual
conversion receiver with RF amplifier transistor, oscillators, mixers,
quadrature detector, meter drive/carrier detect and mute circuitry. The
MC3363 also has a buffered first local oscillator output for use with frequency
synthesizers, and a data slicing comparator for FSK detection.
LOW POWER
DUAL CONVERSION
FM RECEIVER
• Wide Input Bandwidth - 200 MHz Using Internal Local Oscillator
- 450 MHz Using External Local Oscillator
SEMICONDUCTOR
TECHNICAL DATA
• RF Amplifier Transistor
• Muting Operational Amplifier
• Complete Dual Conversion
• Low Voltage: VCC = 2.0 V to 6.0 Vdc
• Low Drain Current: ICC = 3.6 mA (Typical) at VCC = 3.0 V,
Excluding RF Amplifier Transistor
• Excellent Sensitivity: Input 0.31lV (Typical) for 12 dB SINAD
Using Internal RF Amplifier Transistor
DWSUFFIX
PLASTIC PACKAGE
CASE 751F
(SO·2BL)
• Data Shaping Comparator
• Received Signal Strength Indicator (RSSI) with 60 dB
Dynamic Range
• Low Number of External Parts Required
ORDERING INFORMATION
• Manufactured in Motorola's MOSAIC® Process Technology
Device
Operating
Temperature Range
Package
MC3363DW
TA = - 40 10 +B5°C
S0-2BL
Figure 1. Pin Connections and Representative
Block Diagram
1st Mixer Input 11-----..., r - - - - t 2 8 1st Mixer Input
...J:;""""-,,?:1,,_, Varicap Control
Emitter
Collector
3
4 1-------'
2nd La Emiller 5
2nd LO Base
24 1st LO Output
61--~--~
2nd Mixer Output 07'1---<
23
~----t2g2j2
1st Mixer Output
2nd Mixer Input
"------121 2nd Mixer Input
Limiter Input 9 1----...,
Limiter Decoupling 10I--+--iill16 Recovered Audio
15 Mute Input
8-89
MC3363
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Pin
Symbol
Value
Power Supply Voltage
Rating
8
VCC(max)
7.0
Vdc
Operating Supply Voltage Range
(Recommended)
8
VCC
2.0 to 6.0
Vdc
1,28
Vl-28
1.0
Vrms
Vpk
Input Voltage (VCC = 5.0 Vdc)
Unit
Mute Output Voltage
19
V19
-0.7to 8.0
Junction Temperature
-
TJ
150
°c
Operating Ambient Temperature Range
-
TA
-40to +85
°c
-
Tstg
-65to +150
°c
Storage Temperature Range
'.
ELECTRICAL CHARACTERISTICS (VCC
test circun of Figure 2 unless otherwise noted)
=5.0 Vdc, fo =49.7 MHz, Deviation =±3.0 kHz, TA =25°C, Mod 1.0 kHz,
Characteristic
Pin
Min
Typ
Max
Units
-
4.5
8.0
mA
0.7
2.0
l1Vrms
Input For 12 dB SINAD
-
0.3
-
20 dB SIN Sensitivity (RF Amplifier Not Used)
-
1.0
-
-
690
-
Q
7.2
-
pF
1st Mixer Conversion Voltage Gain (Avcl, Open Circuit)
-
18
-
dB
2nd Mixer Conversion Voltage Gain )Avc2, Open Circuit)
-
21
-
-
10
-
9
100
-
RF Transistor DC Current Drain
4
1.0
1.5
2.5
mAde
=0 mY)
Recovered Audio (RF Signal Level =1.0 mY)
THO of Recovered Aduio (RF Signal =1.0 mY)
16
-
70
-
mVrms
16
120
200
-
mVrms
16
-
2%
Detector Output Impedance
16
400
Series Equivalent Input Impedance
1
-
Data (Comparator) Output Voltage - High
-Low
18
Data (Comparator) Threshold Voltage Difference
17
70
110
150
mV
Meter Drive Slope
12
70
100
135
nAldB
Carrier Detect Threshold (Below VCC)
12
0.53
0.64
0.77
Vdc
Mute Output Impedance - High
-Low
19
-
10
25
-
MQ
Drain Current (Carrier Detect Low)
8
-3.0 dB Limning Sensitivity (RF Amplifier Not Used)
1st Mixer Input Resistance (Parallel- Rp)
1,28
1st Mixer Input Capacitance (Parallel- Cp)
1,28
2nd Mixer Input Sensitivity (20 dB SIN) (10.7 MHz i/p)
Limiter Input Sensnivity (20 dB SIN) (455 kHz Vp)
Noise Output Level (RF Signal
8-90
21
450]350
-
-
0.1
0.1
-
-
l1Vrms
%
Q
VCC
-
-
Vdc
MOTOROLA ANALOG IC DEVICE DATA
iii:
a
:u
o
Figure 2. Test Circuit
VCC= 5.0 Vdc
!t:
»
z
»
g
(5
Ferronics 12-345-K Core
CRF 1: muRata SFE 10.7 rnA
or Equivalent
1000 pF
21. 6
lstMixerlnput~
1
50MHzO~------+--------
m
I
CRF 2: muRala CFU 4550
or Equivalent
o
c
I
Ll: Coilcraft UNll0/142 10-1/2 Turns
c
::5
m
LC1: Taka 7MC8128Z
~
)0
From PLL Phase Deetector
s::
120pF
To PLL Phase Detector
l
10k
10k
Mute Output
-lliI
0.1
,
0
~
Comparator Output
390k
10 k
5.0k
'VII\,
I--+---~'VII\,
5.0k
~131----'~
0
Recovered Audio
Output
14
6Sk
r:-
10k
Lcd L~. J I
~_~-..=.J-
Ll'2!~~
-VV~ ~ComparatorTestlnput
0.01
Carrier Detect Output
t...
II
Mute Input
~
~
r· I 10~F
+
MC3363
CIRCUIT DESCRIPTION
The MC3363 is a complete FM narrowband receiver from
RF amplifier to audio preamp output. The low voltage dual
conversion design yields low power drain, excellent
sensitivity and good image rejection in narrowband voice and
data link applications.
In the typical application, the input RF signal is amplified
by the RF transistor and then the first mixer amplifies the
signal and converts the RF input to 10.7 MHz. This IF signal
is filtered externally and fed into the second mixer, which
further amplifies the signal and converts it to a 455 kHz IF
signal. After external bandpass filtering, the low IF is fed into
the limiting amplifier and detection circuitry. The audio is
recovered using a conventional quadrature detector.
Twice-IF filtering is provided internally.
The input signal level is monitored by meter drive circuitry
which detects the amount of limiting in the limiting amplifier.
The voltage at the meter drive pin determines the state of the
carrier detect output, which is active low.
APPLICATIONS INFORMATION
The first local oscillator is designed to serve as the VCO in
a Pll frequency synthesized receiver. The MC3363 can
operate together with the MC145166n to provide a two-chip
ten--channel frequency synthesized receiver in the 46/49
cordless telephone band. The MC3363 can also be used with
the MC14515X series of CMOS Pll synthesizers and
MC120XX series of ECl prescalers in VHF frequency
synthesized applications to 200 MHz.
For single channel applications the first local oscillator can
be crystal controlled. The circuit of Figure 4 has been used
successfully up to 60 MHz. For higher frequencies an
external oscillator signal can be injected into Pins 25 and/or
26 - a level of approximately 100 mVrms is recommended.
The first mixer's transfer characteristic is essentially flat to
450 MHz when this approach is used (keeping a constant
10.7 MHz IF frequency). The second local oscillator is a
Colpitts type which is typically run at 10.245 MHz under
crystal control.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 21 dB (typical), respectively. Mixer gain is
stable with respect to supply voltage. For both conversions,
the mixer impedances and pin layout are designed to allow
the user to employ low cost, readily available ceramic filters.
Following the first mixer, a 10.7 MHz ceramic bandpass
filter is recommended. The 10.7 MHz filtered signal is then
fed into the second mixer input Pin 21, the other input Pin 22
being connected to VCC.
The 455 kHz IF is filtered by a ceramic narrow bandpass
filter then fed into the limiter input Pin 9. The limiter has 1011V
sensitivity for -3.0 dB limiting, flat to 1.0 MHz.
The output of the limiter is internally connected to the
quadrature detector, including a quadrature capacitor. A
parallel lC tank is needed externally from Pin 14 to VCC. A 68
kO shunt resistance is included which determines the peak
separation of the quadrature detector; a smaller value will
lower the Q and expand the deviation range and linearity, but
decrease recovered audio and sensitivity.
A data shaping circuit is available and can be coupled to
the recovered audio output of Pin 16. The circuit is a
comparator which is designed to detect zero crossings of
FSK modulation. Data rates of up to 35000 baud are
detectable using the comparator. Best sensitivity is obtained
when data rates are limited to 1200 baud maximum.
Hysteresis is available by connecting a high-valued resistor
from Pin 17 to Pin 18. Values below 120 kO are not
recommended as the input signal cannot overcome the
hysteresis.
The meter drive circuitry detects input signal level by
monitoring the limiting of the limiting amplifier stages.
Figure 5 shows the unloaded current at Pin 12 versus input
power. The meter drive current can used directly (RSSI) or
can be used to trip the carrier detect circuit at a specified
input power.
A muting op amp is provided and can be triggered by the
carrier detect output (Pin 13). This provides a carrier level
triggered squelch circuit which is activated when the RF input
at the desired input frequency falls below a present level. The
level at which this occurs is determined by the resistor placed
between the meter drive output (Pin 12) and VCC. Values
between 80-130 kO are recommended. This type of squelch
is pictured in Figures 3 and 4.
Hysteresis is available by connecting a high-valued
resistor Rh between Pins 12 and 13. The formula is:
Hyst
= VCC/ (Rh x 10- 7) dB
The meter drive can also be used directly to drive a meter
or to provide AGC. A current to voltage converter or other
linear buffer will be needed for this application.
A second possible application of the op amp would be in a
noise triggered squelch circuit, similar to that used with the
MC3357/MC3359/MC3361 B FM IFs. In this case the op amp
would serve as an active noise filter, the output of which
would be rectified and compared to a reference on a squelch
gate. The MC3363 does not have a dedicated squelch gate,
but the NPN RF input stage or data shaping comparator
might be used to provide this function if available. The op
amp is a basic type with the inverting input and the output
available. This application frees the meter drive to allow it to
be used as a linear signal strength monitor.
The circuit of Figure 4 is a complete 50 MHz receiver from
antenna input to audio preamp output. It uses few
components and has good performance. The receiver
operates on a single channel and has input sensitivity of
< 0.31lV for 12 dB SINAD.
NOTE: For further application and design information, refer to AN980.
8-92
MOTOROLA ANALOG IC DEVICE DATA
3:
g
:u
Figure 3. Typical Application in a PLL Frequency Synthesized Receiver
o
~
VCC= 5.0 Vdc
»
z
»
b
C)
n
c
~
n
m
~
~
2.0T
27pF
0.41 I1H
RFlnput
49.670 to
9.970 MHz
0.Q1
CRF 1: muRata SFE 10.7mAor Equivalent
CRF 2: muRata CFU 4550 or Equivalent
L1: Coileraft UN110/14210 112 Turns
LC1: Toko 7MCB12BZ
~rl~------------L-~
From PLL Phase Detector
To
MC14516617
Dual PLL
Frequency
Synchrsizer
CF1
10.245M
3.0k
s::
o(0)
~
(0)
10k
VCC (Regulated)
l - - - + - - - -.......-------...,~~- DataOutput
0.001
- -I
10k
200k
Mute
Control
~ Cr
t
100k
±j (
LC1
1.011 H
~
3.3kt020k
Pin 26
L=O.OB I1H
T
39k
Pull-Up
Resistor
Pin 27
L-If--------'
Pin 25
1000 200 MHz
Recovered Audio
Output
Pin 24
L=6BO I1H
C= 1BOpF
NOTE: Pull Up resistor is
used to run the oscillator above 50 MHz.
~
II
II
Figure 4. Single Channel Narrowband FM Receiver at 49.67 MHz
*
t
H~jn~~z
MC3363DW
500
0.01
39pF
1.0kpF
y~(
20 k
I
~~.OkPF
-=-
3000
o.22:H ~
20 k
.. Ii·
H
,
-=-
~
~
L.O.Out
(optional)
4.71!H
4.71!H
3.31!H
10 I!H
Squelch
Adjust
8.00 Spkr
-=-
s::
o
~
0)
(0)
0.1
Pl
lOOk
-=-
139k
-=-
50 k
!!:
m
F1 - 455 kHz ceramic filter, A in = Rout = 1.5 k!l to 2.0 kO
MuAata CFU455X or CFW455X, suffix denotes bandwidth
F2 - 10.7 MHz ceramic filter, Ain = Rout = 3300
MuAata SFE10.7MJ-A, SFA10.7MF5, orSFE10.7MS2A.
F2X - 10.7 MHz crystal filter, FOX 1OM20A or equivalent.
Crystal filters improve adjacent channel and second
image (unwanted 48.76 MHz) rejection. Sensitivity Is
degraded very slightly with this circuit.
LC1 - 455 kHz quadrature tank circuit; Toko 7MC8128Z
P1 - Volume control, miniature potentiometer, logarithmic
taper.
X11 - 10.245 MHz fundamental mode crystal,load capacity
32pF.
X2 - 38.97 MHz, 3rd overtone crystal, series mode .
0.68 IlH adjustable coil; Coilcraft M1287-A
0.22 IlH adjustable coil; Coilcraft M117~A
~
F\.ED is used to adjust LED current: I LED =
o
a
RLED
~
~
l>
Z
l>
.r-
o
Ci)
c;
+
3
~
22
21
F2
c
c;
~ Detect
Indicator
c::::=:::J
m
.<
'J'.".. Carlier
Standard 10.7 MHz Filter
VCC
-=-
fl.0l!F
-=-
c
):Ii
VCC-VLED
-c::---RLED
5:
a
Figure 5. Circuit Schematic
:0
o
>
»
27
z
»
6
8n
cm
23
7
6~
S
o
c
m
~
»
Bias
~.~.~
2T.vYV-~s
12
0
r= ["
,
3:
13
o
15
14 .
(0)
(0)
19
11
17
16
18
20
1
~
II
Q)
(0)
MC3363
Figure 6. PC Board Component View
with High Performance Crystal Filter
Figure 7. PC Board Circuit Side View
Figure 8. PC Board Component Side Ground Plane
fo..oiIlI - - - - - - - - 3.000" -------.-.11
8-96
MOTORQLA ANALOG IC DEVICE DATA
®
ItIIOTOROLA
MC3371
MC3372
Low Power
Narrowband FM IF
LOW POWER
FM IF
The MC3371 and MC3372 perform single conversion FM reception and
consist of an oscillator, mixer, limiting IF amplifier, quadrature discriminator,
active filter, squelch switch, and meter drive circuitry. These devices are
designed for use in FM dual conversion communication equipment. The
MC3371/MC3372 are similar to the MC3361/MC3357 FM IFs, except that a
signal strength indicator replaces the scan function controlling driver which is
in the MC3361/MC3357. The MC3371 is designed for the use of parallel LC
components, while the MC3372 is designed for use with either a 455 kHz
ceramic discriminator, or parallel LC components.
These devices also require fewer external parts than earlier products. The
MC3371 and MC3372 are available in dual-in-line and surface mount
packaging.
• Wide Operating Supply Voltage Range: VCC
1
PSUFFIX
PLASTIC PACKAGE
CASE 648
= 2.0 to 9.0 V
• Input Limiting Voltage Sensitivity of -3.0 dB
• Low Drain Current: ICC = 3.2 rnA, @ VCC = 4.0 V, Squelch Off
• Minimal Drain Current Increase When Squelched
DSUFFIX
PLASTIC PACKAGE
CASE 7518
(S0-16)
• Signal Strength Indicator: 60 dB Dynamic Range
• Mixer Operating Frequency Up to 100 MHz
• Fewer External Parts Required than Earlier Devices
II
MAXIMUM RATINGS
Rating
Value
Unit
4
Vcc(max)
10
Vdc
RF Input Voltage (VCC .. 4.0 Vdc)
16
V16
1.0
Vrms
Detector Input Voltage
B
VB
1.0
Vpp
Squelch Input Voltage
(VCC .. 4.0 Vdc)
12
V12
6.0
Vdc
Mute Function
14
V14
-0.7 to 10
Vpk
Mute Sink Current
14
114
50
mA
MC3371D
Junction Temperature
-
TJ
150
°c
MC3371DTB
Tstg
-65 to +150
°c
MC3371P
Storage Temperature Range
Pin
DTBSUFFIX
PLASTIC PACKAGE
CASE 948F
(TSSOP-16)
Symbol
Power Supply Voltage
ORDERING INFORMATION
Device
NOTES: 1. Devices should not be operated at these values. The "Recommended Operating
Conditions" table provides conditions for actual device operation.
2. ESO data available upon request.
Operating
Temperature Range
Package
SO-16
TSSOP-16
TA = -30° to +70°C
Plastic DIP
S0-16
MC3372D
MC3372DTB
TSSOP-16
MC3372P
Plastic DIP
PIN CONNECTIONS
Mixer Input
Crystal Osc {
Gnd
Mute
Mixer Output
VCC
Limiter Input
MC3371
(Top View)
DecouPling{
Quad Coil
MOTOROLA ANALOG IC DEVICE DATA
Meter Drive
Squelch Input
Filter Output
Filter Input
Recovered Audio
Crystal Osc {
Mute
Mixer Output
VCC
Limiter Input
Decoupling
Limiter Output
Quad Input
MC3372
(Top View)
Meter Drive
Squelch Input
Filter Output
Filter Input
Recovered Audio
8-97
MC3371 MC3372
RECOMMENDED OPERATING CONDITIONS
Rating
Pin
Symbol
Value
Unit
Supply Voltage
(@ TA =; 25°C)
(-30°C ~ TA ~'+15°C)
4
VCC
2.0 to 9.0
2.4 to 9.0
Vdc
RF Input Voltage
16
Vrf
0.0005 to 10
mVrms
RF Input Frequency
16
Irf
0.1 to 100
MHz
Oscillator Input Voltage
1
Vlceal
80 to 400
mVrms
Intermediate Frequenc:y
-
Iii
455
kHz
Limiter Amp Input VoHage
5
Vii
Ot0400
mVrms
Filter Amp Input Voltage
10
Via
0.1 to 300
mVrms
Squelch Input Voltage
12
Vsq
00r2
Vdc
14
Isq
0.1 to 30
mA
-
TA
--30 to +70
°C
>.
Mute Sink Current
Ambient Temperature Range
AC ELECTRICAL CHARACTERISTICS (VCC = 4.0 Vdc, 10 = 58.1125 MHz, df = ±3.0 kHz, Imod = 1.0 kHz, 50 n source,
Ilocal = 57.6575 MHz, Vlceal = 0 dBm, TA = 25°C, unless otherwise noted)
Characteristic
Pin
Symbol
Input lor 12 dB SINAD
Matched Input - (See Figures 11, 12 and 13)
Unmatched Input - (See Figures 1 and 2)
-
VSIN
Input lor 20 dB NOS
-
VNOS
Recovered Audio Output VoHage
Vrf =--30 dBm
-
AFO
Recovered Audio Drop Voltage Loss
Vrf = --30 dBm, VCC = 4.0 V to 2.0 V
-
Meter Drive Output Voltage (No Modulation)
Vrf=-lOOdBm
Vrf=-70dBm
Vrf=-40dBm
13
FiRer Amp Gain
Rs = 600 n , Is = 10 kHz, Via = 1.0 mVrms
-
Mixer Conversion Gain
Vrf=-40 dBm, RL = 1.8 kn
-
Signal to Noise Ratio
Vrf =-30 dBm
-
Total Harmonic Distortion
Vrf = --30 dBm, BW = 400 Hz to 30 kHz
-
Detector Output Impedance
9
Zo
Detector Output VoHage (No Modulation)
Vrf =-30 dBm
9
DVO
Meter Drive
Vrf = -100 to -40 dBm
13
Meter Drive Dynamic Range
RFln
IFln (455 kHz)
13
Mixer Third Order Input Intercept Point
11 = 58.125 MHz
12 = 58.1375 MHz
-
Mixer Input Resistance
16
Mixer Input Capacitance
16
8-98
Min
Typ
Max
-
-
1.0
5.0
15
-
3.5
-
I1Vrms
I1Vrms
mVrms
120
200
320
-8.0
-1.5
-
1.1
2.0
0.3
1.5
2.5
0.5
1.9
3.1
47
50
-
14
20
-
36
67
-
-
0.6
3.4
-
450
-
AFloss
MDrv
MVl
MV2
MV3
Unit
dB
Vdc
dB
AV(Amp)
dB
AV(Mix)
sin
THO
dB
%
n
Vdc
-
1.45
-
-
0.8
-
-
60
80
-
I1NdB
MO
MVD
dB
-
dBm
ITOMix
-
-22
Rin
-
3.3
-
kG
Cin
-
2.2
-
pF
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
DC ELECTRICAL CHARACTERISTICS (VCC = 4.0 Vdc, TA = 25'C, unless otherwise noted)
Characteristic
Pin
Drain Current (No Input Signal)
Squelch Off, Vsq = 2.0 Vdc
Squelch On, Vsq = 0 Vdc
Squelch Off, VCC = 2.0 to 9.0 V
4
Detector Output (No Input Signal)
DC Voltage, VB = VCC
9
Finer Output (No Input Signal)
DC Voltage
Voltage Change, VCC = 2.0 to 9.0 V
11
Trigger Hysteresis
-
Symbol
Min
Typ
Max
Iccl
Icc2
dlccl
-
3.2
3.6
1.0
4.2
4.B
2.0
0.9
1.6
2.3
VII
dVll
1.5
2.0
2.5
5.0
3.5
B.O
Hys
34
57
BO
Unit
mA
V9
Vdc
Vdc
mV
Figure 1. MC3371 Functional Block Diagram and Test Fixture Schematic
RSSIOutput
RFlnput
VCC=4.0Vdc
Filterln
0.1
51 k
Cl
0.01
Sqln
1
Filterout
1
51
1.o1lF
15
470
0.01
510k
Mute
16
1.o1lF
13
12
11
8.2k
10
9
51 k
53 k
1.8k
4
6
8
7
0.1
0.1
20k
muRata
CFU455D2
or
equivalent
MOTOROLA ANALOG IC DEVICE DATA
JO.l
1
AFOut
to Audio
Power Amp
II
MC3371 MC3372
Figure 2. MC3372 Functional Block Diagram and Test Fixture Schematic
RSSIOutput
RFlnput
Vcc= 4.0 Vdc
Rlterln
0.1
51 k
C1
0.01
Sqln
1
Filterout
1
51
1.OI!F
15
470
0.01
510 k
Mute
16
1.01!F
13
12
11
B.2k
10
J
AFOut
to Audio
PowerArnp
9
53k
II
R10
1.Bk
R12
4.3k
C12
0.1
o
Ceramic
Resonator
muRata
CDB455C16
muRata
CFU455D2
or
equivalent
8-100
r
C15
0.1
MOTOROLA AN!\LOG IC DEVICE DATA
MC3371 MC3372
TYPICAL CURVES
(Unmatched Input)
Figure 3. Total Harmonic Distortion
versus Temperature
~ 5.0
~
Ii:
I
VCC = 4.0 Vdc
RF Input = -30 dBm J----fo= 10.7 MHz
60
I
4.0
12
!!2
Figure 4. RSSI versus RF Input
70
«
,2,
~ 3.0
Z
~
~ 2.0
:I:
-'
~
12
\
1.0
ci
~
0
-s5
j 1\
\V
-35
-15
/"
V
'"
l-
=>
-
40
«::!.
-30dBm
en
en
30
a::
20
10 r- T A , C
105
o
125
-140 -120
t=' 36
f!:
=>
0
en
en
30
-70dBm
24
a:: 18
~_TA=-30°C
-100
-80
;[ -20
~
l-
i[ -30
-
I;
~ -40
r--
/"
-50
-80
105
-70
-70
125
T~=75jC -
27
V
-60
-50
./
~
21
t=' 18
=>
D..
5
0
en
en
T _-30°C- -
II
-40
/
-30
-20
~ "-
TA=25°C-
m
30
z
J
~
U'
RF INPUT (dBm)
I
42
TA=25 C'):
0
0
5.0
25
45
65
85
TA, AMBIENT TEMPERATURE (OC)
..
54
48
,
50
Figure 5. RSSI Output versus Temperature
60
TAI=75°C
8.0
9.0
10
o
1.0
\
\\
\\' 5.0dBm
\\ OdBm I
\\
10
100
-5.0dBm
1000
f, FREQUENCY (MHz)
8-101
II
MC3371 MC3372
MC3371 PIN FUNCTION DESCRIPTION
OPERATING CONDITIONS
Pin
The base of the Colpitts oscillator. Use
a high impedance and low capacitance
probe or a "sniffer" to view the waveform without altering the frequency.
Typical level is 450 mVpp.
Vcc
OSCI
2
OSC2
3
MXOut
-+--'l.......1".,5k~
The emitter of the Colpitts oscillator.
Typical signal level is 200 mVpp. Note
that the signal is somewhat distorted
compared to that on Pin 1.
OSC2
3
MixeroUl
II
Output of the Mixer. Riding on the
455 kHz is the RF carrier component.
The typical level is approximately
60mVpp.
4
VCC
Supply Voltage -2.0 to 9.0 Vdc is the
operating range. VCC is decoupled to
ground.
5
IFln
Input to the IF amplifier after passing
through the 455 kHz ceramic filter. The
signal is attenuated by the filter. The
typical level is approximately
50mVpp.
IFln
DECI
6
7
a
DECI
DEC2
Quad
Coil
DEC2
IF Decoupling. External 0.1 I1F
connected to VCC.
capac~ors
8
Quad Coil
VCC
Quadrature Tuning Coil. Composite
(not yet demodulated) 455 kHz IF
signal is present. The typical level is
500mVpp.
501lA
8-102
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
MC3371 PIN FUNCTION DESCRIPTION (continued)
=3.0 kHz. MC3371 at
OPERATING CONDITIONS
Internal Equivalent
Circuil
Pin
9
= 10.7 MHz (see Figure 11).
Waveform
Recovered Audio. This is a composite
FM demodulated output having signal
and carrier component. The typical
level is 1.4 Vpp.
h
VCC",
9 RAOut
100).IA
10
The filtered recovered audio has the
carrier component removed and is
typically 800 mVpp.
Filter Amplifier Input
II
11
Filter Amplifier Output. The typical
signal level is 400 mVpp.
FilOut
Vee
i;
40).IA
FilterOut
11
12
Squelch Input. See discussion in
application text.
12
Sqln~ ~
~2).IA
MOTOROLA ANALOG IC DEVICE DATA
8-103
MC3371 MC3372
MC3371 PIN FUNCTION DESCRIPTION (continued)
,
OPERATING CONDITIONS VCC = 4 0 Vdc RF'n = 100 ltV fmod = 10kHz fdev = 30kHz MC3371 at fRF = 10 7 MHz (see Figure 11)
Pin
Symbol
13
RSSI
Internal Equivalent
Circuit
Vee
Bias
14
MUTE
t
Description
Waveform
RSSI Output. Referred to as the
Received Signal Strength Indicator or
RSSI. The chip sources up to 60 ItA
over the linear 60 dB range. This pin
may be used many ways, such as:
AGC, meter drive and carrier triggered
squelch circuit.
13
RSSIOut
tf~'
Mute Output. See discussion in
application text.
40k
15
Gnd
Gnd
*
16
II
15
•
Vee
MIX'n
MixefJn
~
3.3k
Ground. The ground area should be
continuous and unbroken. In a twosided layout, the component side has
the ground plane. In a one-sided
layout, the ground plane fiJJs around
the traces on the circuit side of the
board and is not interrupted.
Mixer Input Series Input Impedance:
@ 10 MHz: 309 - j33 Q
@ 45 MHz: 200 - j13 Q
10 k
"other pins are the same as pins in MC3371.
8-104
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
MC3372 PIN FUNCTION DESCRIPTION
OPERATING CONDITIONS VCC = 4.0 Vdc, RFln = 100 ~V, fmod = 1.0 kHz, fdev = 3.0 kHz. MC3372 at 'RF = 45 MHz (see Figure 13).
Pin
Symbol
Internal Equivalent
Circuit
5
IF Amplifier Input
IFlnf.:
6
DEe
6
60 ItA
7
IFOut
7 1Foul
vee
~
53k
IF Decoupling. External 0.1 ~F
connected to Vcc.
capac~ors
IF Amplifier Output Signal level is
typically 300 mVpp.
50 ItA
.". 120 ItA
.".
8
Quadrature Detector Input. Signal
level is typically 150 mVpp.
Quadln
~
8
Quadln
II
Vee
T 10
9
501tA
RA
Recovered Audio. This is a composite
FM demodulated output having signal
and carrier components. Typical level
is800mVpp.
i=
'CC '" ,
RAOul
100 ItA
MOTOROLA ANALOG IC DEVICE DATA
The filtered recovered audio has the
carrier signal removed and is typically
500mVpp.
8-105
MC3371 MC3372
Figure 9. MC33?:1 Circuit Schematic
MixerOul
4
3
VCC
OSC1
-+-""M~
SquelchOul
OSC2
, - 15
-}
Gnd
53k
DECt~1-~~~~---~~--------t-~-+-~
. 7
51 k
DEC2~~-r-----~---~~--------------~-+~--~
Figure 10. MC3372 Circuit Schematic
MixerOut
4
3
VCC
OSC1
-+-""M~
Squelch Out
, - 15
-}
Gnd
200 9
RAout
6
DEC
7
IFOul
53k
tOO JlA
8-106
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
CIRCUIT DESCRIPTION
The MC3371 and MC3372 are low power narrowband FM
receivers with an operating frequency of up to 60 MHz. Its low
voltage design provides low power drain, excellent
sensitivity, and good image rejection in narrowband voice
and data link applications.
This part combines a mixer, an IF (intermediate frequency)
limiter with a logarithmic response signal strength indicator, a
quadrature detector, an active filter and a squelch trigger
circuit. In a typical application, the mixer amplifier converts an
RF input signal to a 455 kHz IF signal. Passing through an
external bandpass filter, the IF signal is fed into a limiting
amplifier and detection circuit where the audio signal is
recovered. A conventional quadrature detector is used.
The absence of an input signal is indicated by the
presence of noise above the desired audio frequencies. This
"noise band" is monitored by an active filter and a detector. A
squelch switch is used to mute the audio when noise or a
tone is present. The input signal level is monitored by a meter
drive circuit which detects the amount of IF signal in the
limiting amplifier.
APPLICATIONS INFORMATION
The oscillator is an internally biased Colpitts type with the
collector, base, and emitter connections at Pins 4, 1 and 2
respectively. This oscillator can be run under crystal control.
For fundamental mode crystals use crystal characterized
parallel resonant for 32 pF load. For higher frequencies, use
3rd overtone series mode type crystals. The coil (l2) and
resistor RD (R13) are needed to ensure proper and stable
operation at the LO frequency (see Figure 13, 45 MHz
application circuit).
The mixer is doubly balanced to reduce spurious radiation.
Conversion gain stated in the AC Electrical Characteristics
table is typically 20 dB. This power gain measurement was
made under stable conditions using 'a 50 0 source at the
input and an external load provided by a 455 kHz ceramic
filter at the mixer output which is connected to the VCC (Pin 4)
and IF input (Pin 5). The filter impedance closely matches the
1.8 kQ internal load resistance at Pin 3 (mixer output). Since
the input impedance at Pin 16 is strongly influenced by a
3.3 kO internal biasing resistor and has a low capaCitance,
the useful gain is actually much higher than shown by the
standard power gain measurement. The Smith Chart plot in
Figure 17 shows the measured mixer input impedance
versus input frequency with the mixer input matched to a
50 0 source impedance at the given frequencies. In order to
assure stable operation under matched conditions, it is
necessary to provide a shunt resistor to ground. Figures 11,
12 and 13 show the input networks used to derive the mixer
input impedance data.
Following the mixer, a ceramic bandpass filter is
recommended for IF filtering (I.e. 455 kHz types having a
bandwidth of ±2.0 kHz to ±15 kHz with an input and output
impedance from 1.5 kO to 2.0 kQ). The 6 stage limiting IF
MOTOROLA ANALOG IC DEVICE DATA
amplifier has approximately 92 dB of gain. The MC3371 and
MC3372 are different in the limiter and quadrature detector
circuits. The MC3371 has a 1.8 kQ and a 51 kQ resistor
providing internal dc biasing and the output of the limiter is
internally connected, both directly and through a 10 pF
capacitor to the quadrature detector; whereas, in the
MC3372 these components are not provided internally. Thus,
in the MC3371, no external components are necessary to
match the 455 kHz ceramic filter, while in the MC3372,
external 1.8 kQ and 51 kO biasing resistors are needed
between Pins 5 and 7, respectively (see Figures 12 and 13).
In the MC3371, a parallel LCR quadrature tank circuit is
connected externally from Pin 8 to VCC (similar to the
MC3361). In the MC3372, a quadrature capaCitor is needed
externally from Pin 7 to Pin 8 and a parallel LC or a ceramic
discriminator with a damping resistor is also needed from
Pin 8 to VCC (similar to the MC3357). The above external
quadrature circuitry provides 90° phase shift at the IF center
frequency and enables recovered audio.
The damping resistor determines the peak separation of
the detector and is somewhat critical. As the resistor is
decreased, the separation and the bandwidth is increased
but the recovered audio is decreased. Receiver sensitivity is
dependent on the value of this resistor and the bandwidth of
the 455 kHz ceramic filter.
On the chip the composite recovered audio, consisting of
carrier component and modulating Signal, is passed through
a low pass filter amplifier to reduce the carrier component
and then is fed to Pin 9 which has an output impedance of
450 O. The signal still requires further filtering to eliminate
the carrier component, deemphasis, volume control, and
further amplification before driving a loudspeaker. The
relative level of the composite recovered audio signal at Pin 9
should be considered for proper interaction with an audio
post amplifier and a given load element. The MC13060 is
recommended as a low power audio amplifier.
The meter output indicates the strength of the IF level and
the output current is proportional to the logarithm of the IF
input signal amplitude. A maximum source current of 60 jlA is
available and can be used to drive a meter and to detect a
carrier presence. This is referred to as a Received Strength
Signal Indicator (RSSI). The output at Pin 13 provides a
current source. Thus, a resistor to ground yields a voltage
proportional to the input carrier signal level. The value of this
resistor is estimated by (VCC(Vdc) - 1.0 V)/60 jlA; so for
VCC = 4.0 Vdc, the resistor is approximately 50 kQ and
provides a maximum voltage swing of about 3.0 V.
A simple inverting op amp has an output at Pin 11 and the
inverting input at Pin 10. The noninverting input is connected
to 2.5 V. The op amp may be used as a noise triggered
squelch or as an active noise filter. The bandpass filter is
designed with external impedance elements to discriminate
between frequencies. With an external AM detector, the
filtered audio signal is checked for a tone signal or for the
presence of noise above the normal audio band. This
information is applied to Pin 12.
8-107
8
MC3371 MC3372
An external positive bias to Pin 12 sets up the squelch
trigger circuit such that the audio mute (Pin 14) is open or
connected to ground. If Pin 12 is pulled down to 0.9 V or
below by the noise or tone detector, Pin 14 is internally
shorted to ground. There is about 57 mV of hyteresis at
Pin 12 to prevent jitter. Audio muting is accomplished by
connecting Pin 14 to the appropriate point in the audio path
between Pin 9 and an audio amplifier. The voltage at Pin 14
should not be lower than -D.7 V; this can be assured by
connecting Pin 14 to the pOint that has no dc component.
Another possible application of the squelch switch may
be as a carrier level triggered squelch circuit, similar to the
MC3362/MC3363 FM receivers . .In this case the meter
output can be used directly to trigger the squelch switch
when the RF input at the input frequency falls below the
desired level. The level at which this occurs. is determined
by the resistor placed between the meter drive output
(Pin 13) and ground (Pin 15).
Figure 11. Typical Application for MC3371 at 10.7 MHz
RSSIOutput
VCC =4.0 Vdc
R2
10k
1st IF 10.7 MHz
from Input
Front End
R3
100 k
c151
91
i :
r4~-+-f=-=-:::;'''''
8.2j.lH
L2
R11:
560 L
L1
TKANS9443HM
...J 6.B j.lH ±6%
'--~"""-_i> VR1 (Squelch Control)
10k
4.7k R6
560
II
RB
C1
0.01
3.3k
C7 :r
0.022 -=-
CB
0.22
AFOut
VR2 ~--tO--O to Audio
10 k
Ppwer Amp
16
- - - - - , T2:Toko
I 2A6597 HK (1 0 mm)
I or
t-=':...:.O--r-_-*-_-_--'...J 7MC-812BZ (7 mm)
i
L -_ _ _ _~-_*---~~---~~-~-_.
muRata
CFU455D2
or
equivalent
8-,108
C14
J O.1
MQTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
Figure 12. Typical Application for MC3372 at 10.7 MHz
VCC = 4.0Vdc
RSSIOutput
R2
10k
1st IF 10.7 MHz
from Input
Front End
c161
91
rl>---t-f:.:-:;:-. L1
R13 :
i :
560 L
TKANS9443HM
...J 6.8IlH±6%
.----"NV--i? VR1 (Squelch Control)
10k
4.7k R6
560
C1
0.01
R1
51 k
R8
C8
3.3k C7 ::r:
0.022 =
0.22
AFOut
VR2 ~_>--O to Audio
10 k
Power Amp
16
II
o
muRata
CFU455D2
or
equivalent
MOTOROLA ANALOG IC DEVICE DATA
J
muRata
CDB455C16
C15
0.1
8-109
MC3371 MC3372
Figure 13. Typical Application for MC3372 at 45 MHz
RSSIOutput
to Meter (Triplett - 100 kV)
VCC=4.0Vdc
R2
12k
RF Input
45 MHz C17
W
~20
C18..t-if--l
75
=
> VRl (Squelch Control)
.......---'\NIr-...
10k
4.7k R6
560
R7
R8
3.3k
C8
0.22
C7
0.022=J;
AFOut
VR2 ~_o---
«
30
a:
w
>
20
cw
0
~
Z
r
()
w
a:
10
V6
\
-20
"-
-30
-40
~
o
o
S+N
\
:so -10
"'~
N
-50
1.0
2.0
3.0
-60
-120 -110 -100 -90
4.0
!:s=>
:g
§.
IF
Q
J
800
~
~ 600
:..-- RL =~
(!J
:5
:; 200
=>
RL =330
1.0
2.0
J
o
1100
1060
./
/
/
~ 1040
,.:
I
-
...
-40
1120
(!J
.. :..-- RL = 990
,.:
o
~
I
g 400
-50
.........
g 1080
S3
;:!:
-60
1140
1200
~1000
-70
Figure 5. Regulated Output and Recovered
Audio versus Temperature
........
Figure 4. VREG versus Supply
>
-80
-30
INPUT (dBm)
Vcc(V)
--
/
""
'\
~
'~
V17 ........
,
...........
:; 1020
I
3.0
4.0
5.0
1000
-50
-25
0
25
50
18.0
f
17.5 §.
\
17.0 §
~
"-
-
75
16.5~
_ 1 6.0~
8
15.5~
«S
15.0 >
100
14.5
125
TA, AMBIENT TEMPERATURE ('C)
Vcc(V)
Figure 6. Buffer Amplifier Gains
versus Temperature
3.03
4.01
[
z
3.99
<
(!J
a: 3.97
w
LL
LL
=>
Cl
Q 3.95
c
=>
«
.g
>
\
~
~
/"'.. .........
'"
- 2.98 [
z
'",\Vdb
- 2.93 ~~
~~~
=>
2.88 ~
&
!;(
c
~~
3.93
.i;,
2.83 '§!
«
«
3.91
-50
-25
0
25
50
75
100
2.78
125
TA. AMBIENT TEMPERATURE ('C)
MOTOROLA ANALOG IC DEVICE DATA
8-117
II
MC3374
Figure 7. MC3374 Pager Receiver PCB Artwork
COPPER 1 LAYER
(Actuiil View of Surface Mount Side)
COPPER 2 LAYER
(Caution: Reversed View of Through-Hole Side)
2·0,,-----~1
COMPONENT 2 LAYER
COMPONENT 1 LAYER
RFVP
VCC + + GND
C::>
C20Cc,'"
+
+ fI'I Dc ... + OCB
Cl \;!;I
C2
+ + 3800P
~OeJCB
+0
CC3
+
+
+ C400 C3
...
0
+
+
+fI'I 0.1 CB
\;!;I
+ +
4.7
56K
100KD
D
+ +
O
+
V~c
+~
'!1 +
~\;!;IGND
+
+
+
+ (+l+
+
1.0fl'l 0 \;!;I
+
\;!;I 01 10
.
+ +
++
+
+ +
+
+ +
~+
L1
+
+
+FL1
xD:
0.Q1
0
L2
c::>
Q
00.Q1 +
0
+
+
+
0 +
O.33k+O.obO.~.
+
+
+ +
100 39ko lOOk + +
+ 8.2k
+ U
+
LC1'"
+
+
+
+
+ +
+ 3.3~ D8.2k
LEi£ij
+0 0.22
D
DataOIP
~
~
O
0
0
...
+
0
RL
+
+E b+1 +
+na.
+Disable
SMA
NOTE: ... = Through Hoi.
8-118
MOTOROLA ANALOG IC DEVICE DATA
MC3374
CIRCUIT DESCRIPTION
The MC3374 is an FM narrowband receiver capable of
operation to 75 MHz. The low voltage design yields low
power drain and excellent sensitivity in narrowband voice
and data link applications. In the typical application the mixer
amplifies the incoming RF or IF signal and converts this
frequency to 455 kHz. The signal is then filtered by a 455 kHz
ceramic filter and applied to the first intermediate frequency
(IF) amplifier input, before passing through a second ceramic
filter. The modulated IF signal is then applied to the limiting IF
amplifi,er and detector circuitry. Modulation is recovered by a
conventional quadrature detector. The typical modulation
bandwidth available is 3.0 to 5.0 kHz.
Features available include buffers for audio/data
amplification and active filtering, on board voltage regulator,
low battery detection circuitry with programmable level, and
receiver disable circuitry. The MC3374 is an FM utility
receiver to be used for voice and/or narrowband data
reception. It is especially suitable where extremely low power
consumption and high design flexibility are required.
APPLICATION
The MC3374 can be used as a high performance FM IF for
the use in low power dual conversion receivers. Because of
the MC3374's extremely good sensitivity (0.6 IlV for 20 dB
(S+N/N, see Figure 3)), it can also be used as a stand alone
single conversion narrowband receiver to 75 MHz for
applications not sensitive to image frequency interference.
An RF preamplifier will likely be needed to overcome
preselector losses.
The oscillator is a Colpitts type which must be run under
crystal control. For fundamental mode crystals choose
resonators, parallel resonant, for a 32 pF load. For higher
frequencies, use a 3rd overtone series mode type. The coil
l2 and RD resistor are needed to ensure proper operation.
The best adjacent channel and sensitivity response occur
when two 455 kHz ceramic filters are used, as shown in
Figure 1. Either can be replaced by a 0.1 IlF coupling
capacitor to reduce cost, but some degradation in sensitivity
and/or stabil'ity is suspected.
The detector is a quadrature type, with the connection
from the limiter output to the detector input provided
internally. A 455 kHz LC tank circuit must be provided
externally. One of the tank pins (Pin 8) must be decoupled
using a 0.1 IlF capacitor. The 56 kg damping resistor (see
Figure 1), determines the peak separation of the detector
(and thus its bandwidth). Smaller values will increase the
separation and bandwidth but decrease recovered audio and
sensitivity.
The data buffer is a noninverting amplifier with a nominal
voltage gain of 2.7 VN. This buffer needs its dc bias
(approximately 250 mV) provided externally or else
debiasing will occur. A 2nd order Sail en-Key low pass filter,
as shown in Figure 1, connecting the recovered audio output
to the data buffer input provides the necessary dc bias and
some post detection filtering: The buffer can also be used as
an active filter.
MOTOROLA ANALOG IC DEVICE DATA
The audio buffer is a non inverting amplifier with a nominal
voltage gain of 4.0 VN. This buffer is self-biasing so its input
should be ac coupled. The two buffers, when applied as
active filters, can be used together to allow simultaneous
audio and very low speed data reception. Another possible
configuration is to receive audio only and include a
noise-triggered squelch.
The comparator is a noninverting type with an open
collector output. Typically, the pull-up resistor used between
Pin 14 and VCC is 100 kU With RL =100 kg the comparator
is capable of operation up to 25 kHz. The circuit is
self-biasing, so its input should be ac coupled.
The regulator is a 1.07 V reference capable of sourcing
3.0 mAo This pin (Pin 17) needs to be decoupled using a
1.0-10 IlF capacitor to maintain stability of the MC3374.
All three VCCs on the MC3374 (VCC, VCC2, VCC3) run on
the same supply voltage. VCC is typically decoupled using
capacitors only. VCC2 and VCC3 should be bypassed using
the RC bypasses shown in Figure 1. Eliminating the resistors
on the VCC2 and VCC3 bypasses may be possible in some
applications, but a reduction in sensitivity and quieting will
likely occur.
The low battery detection circuit gives an NPN open
collector output at Pin 20 which drops low when the MC3374
supply voltage drops below 1.2 V. Typically it would be pulled
up via a 100 kn resistor to supply.
The 1.2 V Select pin, when connected to the MC3374 supply,
programs the low battery detector to trip at VCC < 1.1 V. Leaving
this pin open raises the trip voltage on the low battery detector.
Pin 15 is a receiver enable which is connected to VCC for
normal operation. Connecting this pin to ground shuts off
receiver and reduces current drain to ICC < 0.5 /lA.
APPENDIX
Design of 2nd Order Sallen-Key Low Pass Filters
is+
R1
Input
C1
~ ~
1
L-vv-,
R2
~
~
~
"~
C2
Bias
•
Low Pass Output
OtofoHz
Avo=K
The audio and data buffers can easily be configured as active
low pass filters using the circuit configuration shown above.
The circuit has a center frequency (fo) and quality factor (0)
given by the following:
f
-
1
0 - 2lt v'R1R2C1C2
0=
1
jR2C2
R1C1
+ jR1C2 + (1-K) jR1C1
R2C1
R2C2
If possible, let R1 = R2 or C1 = C2 to simplify the above
equations. Be sure to avoid a negative 0 value to prevent
instability. Setting 0
filter response.
= 1/./2 = 0.707 yields a maximally flat
8-119
II
:
MC3374,
Data Buffer Design
Audio Buffer Design
The data buffer is designed as follows:
The audio buffer is designed as follows:
fo= 200 Hz
C2 0.01 !J.F
Q 0.707 (target)
fa 3000 Hz
R1 R2 8.2 kQ
Q 0.707 (target)
C1
K
=
= =
=
= =
=
=2.7 (data buffer open loop voltage gain)
Setting C1 =C2 yields:
fa =
K
=3.9 (audio bufferopen loop voltage gain)
Setting C1 =C2 yields:
1
fa =
2n;C1JR1R2
Q =
1
/C2. + (1-K) yC2
{c1
yCf
=
Iteration yields R2 4.2 (R1) to make Q 0.707.
Substitution into the equation for fa yields:
R1 38 kQ (use 39 kQ)
R2 4.2(R1) 180 kQ
C1 C2 0.01 !J.F
=
=
8-120
= =
=
1 ,
Q =
M+(2-K)~
=
1
2:nR1JC1C2
=
=
Iteration yields C2 2.65 (C1) to make Q 0.707.
Substitution into the equation for fa yields:
C1 3900 pF
C2 2.65(C1) 0.01 !J.F
R1 = R2 = 8.2 kQ
=
=
=
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13055
Wideband FSK Receiver
The MC13055 is intended fo RF data link systems using carrier
frequencies up to 40 MHz and FSK (frequency shift keying) data rates up to
2.0 M Baud (1.0 MHz). This design is similar to the MC3356, except that it
does not include the oscillator/mixer. The IF bandwidth has been increased
and the detector output has been revised to a balanced configuration. The
received signal strength metering circuit has been retained, as has the
versatile data slicer/comparator.
WIDEBAND
FSK
RECEIVER
SEMICONDUCTOR
TECHNICAL DATA
• Input Sensitivity 20 IlV @ 40 MHz
• Signal Strength Indicator Linear Over 3 Decades
• Available in Surface Mount Package
• Easy Application, Few Peripheral Components
PSUFFIX
PLASTIC PACKAGE
CASE 648
o
SUFFIX
PLASTIC PACKAGE
CASE 7518
(50-16)
II
PIN CONNECTIONS
Figure 1. Block Diagram and Application Circuit
Comparator Gnd
1
eomparatorVcc 2
Vee
IF Ground
Squelch
Adjust
(meter)
3
IFVee
4
13
Carrier Detect
Limiter Input
5
12
Meter Drive
Limiter Bias {
6
QuadBias
B
9
Quad Input
ORDERING INFORMATION
Device
MC13055D
L2
MOTOROLA ANALOG IC DEVICE DATA
MC13055P
Operating
Temperature Range
TA = - 40 to +85°C
Package
50-16
Plastic DIP
8-121
MC13055
MAXIMUM RATINGS
Rating
Power Supply Voltage.
Operating Supply Voltage Range
Symbol
Value
Unit
VCC(max)
15
Vdc
Vdc
V2, V4
3.0 to 12
Junction Temperature
TJ
150
c.C
Operating Ambient Temperature Range
TA
-40 to +85
°c
Storage Temperature Range
Tstg
-65 to +150
°c
Power Dissipation, Package Rating
Po
1.25
W
ELECTRICAL CHARACTERISTICS (VCC =5.0 Vdc, fo = 40 MHz, fmod;' 1.0 MHz, Af =±1.0 MHz, TA = 25°C, test circuit of Figure 2.)
Characteristic'
Conditions
Min
Typ
Max
Unit
rnA
12+ 14
-
20
25
Data Comparator Pull-Down Current
116
-
10'
-
rnA
Meter Drive Slope versus Input
112
4.5
7.0
9.0
llA/dB
Carrier Detect Pull-Down Current
113
-
1.3
-
rnA
Carrier Detect Pull-Up Current
113
-
500
-
IlA
Carrier Detect Threshold Voltage
V12
690
800
1010
mV
DC Output Current
110,111
430
-
I1A
Recovered Signal
Vl0-Vll
-
350
-
mVrms
IlVrms
Total Drain Current
Sensitivity for 20 dB S + NIN, BW
S + NIN atVin
VIN
-
20
-
Vl0-Vll
-
30
-
dB
Rin
Cin
Pin 5, Ground
-
4.2
4.5
-
-
k1l
pF
Rin
Cin
Pin9t08
-
7.6
5.2
-
k1l
pF
=5.0 MHz
=50 IlV
Input Impedance
@
40 MHz
Quadrature Coil Loading
-
Figure 2. Test Circuit
VCCo---.--------*~~2
3
100pF
14
4
5
22pF r-----,
13
Carrier
--+--.-------o-=t
Detect Output
Input o-J I-l-......
12
J--C>---t-------f---O Meter Drive
6
11
0.1
7
10
J--C>--~"""--f-----O
Detector
Output
0.Q1 ~
3.9k
39pF
r
,
3.9k
Coils - Shielded
Coilcraft UNHO/142
L 1 Gray 8--1/2 Turns, nominal 300 nH
L2 Black 10-1/2 Turns, nominal 380 nH
I
I
IL _ _ _ _ _ _ _ _ .JI
8-122
MOTOROLA ANALOG IC DEVICE DATA
MC13055
Figure 3. Overall Gain, Noise, AM Rejection
o
/'
iXl-l0
~
-20
~
0-30
/
UJ
UJ
a: -SO
Out~ut tm~ = 1.0'MHz -
/
-
At= 1.0 MHz
;;(
iiJ
L
fE
~ "
"-
"'
~ AMR1.0kHz
I--
30%
ffi
t:u
""-
"' "'
J
./
)(...
'\.
400
--
./.
. /i /
300
~
..........
'-/
100
-100
Figure 5. Untuned Input: Limiting Sensitivity
versus Frequency
I_- -10 1--.
ffi
en
~
~
:::;
~
~
-SO
.-{IO
-70
V-
i -~
-20
'~1~~20k
......
10
20
-- -- - -
0.1 ~
,./
30 40
SO
60
70
t, INPUT FREQUENCY (MHz)
80
Quadrature
Coil Tuning
40 MHz
90
-
II
o
100
403
I
1\,.11
limiting
SensHivity
f-
I I I
-
39.4
39.3
39.2
I I I
3.0
5.0
7.0
9.0
11
VCC, SUPPLY VOLTAGE (Vdc)
MOTOROLA ANALOG IC DEVICE DATA
13
15
20
30
40 SO
60
70
t, INPUT FREQUENCY (MHz)
"0 1200
40.1 'N
40.0 ~
39.9 ~
39.8 Z
39.7 ~
...J
39.60
(.)
39.5 Cl
/
__~~__~~__~~__~~~
10
80
90
100
Figure 8. Detector Current and Power Supply
Current versus Supply Voltage
f - 40.2
r-
.....
'1C].J
...,........::",...;::::-I---+--+-
Figure 7. Limiting Sensitivity and Detuning
versus Supply Voltage
1.0
.-{IO
-40
INPUT SIGNAL (dBm)
-130
O~~
o
~
0.1
r-'npu1~~
51
MC13055
20k
7
8
-30 rr- 0.1~
-40
:Z -90
;> -100
12V
Figure 6. Untuned Input: Meter Current
versus Frequency
-20
-80
3.0V
800r--.--.---r--.--.---~~--------~
0
_~
---
o
-20
./V/
~
V/
,
::;; 200
/
.-{IO
-40
SIGNAL INPUT (dBm)
-100
."
(.)
"\.
.-{IO
vcc 5.0 v\o V
:::>
Noise
--
I
!
600
;!: 500
""-
/
2:
'5-40
I
.......
1/
~
Figure 4. Meter Current versus Signal
a
~
:1.
;:- 1000
:z
UJ
a:
a:
:::>
--
800
(.)
a:
~
~
Cl
:!::
+
~
-
600
....... f-"'""
400
....
- -
60 -
J..-I--:
110+111
50
L.--~
I
o
o
12+14
::;
20
J
a:
UJ
~
10 ~
o
3.0
a:
(.)
303::
:::>
en
./
1.0
!z
UJ
40 gj
/
200
1
5.0
7.0
9.0
11
Vcc, SUPPLY VOLTAGE (Vdc)
13
+
Sl!
15
8-123
MC13055
Figure 10. Carrier Detect Threshold versus
Temperature
Figure 9. Recovered Audio versus Temperature
>1000
j
S
4.0
g
~ 2.0
~
0
o
0-2.0
is
~ ......
o:z: 900
~ r-
~-~
1"-'
13
IX:
r'
~
.........
..........
800
~-4.0
..........
Cl
IX:
;;: 600
~
-40
-20
0 20
40
60 80 100
TA. AMBIENTTEMPERATURE (0C)
120
'"
:;: 500
-60
140
~ 500
400
5IX:
~ 300
:;;
~ 200
¢P
~
.,;
,,/"
,....
100
-60 -40
-40
·-50
r-
"""-.
120
140
~
I~
r--.... ~
--- -- -- .,;V·
0
20 40
60 80 100
TA. AMBIENT TEMPERATURE (OC)
~ -50
-20 ~ ~
!-30 .........
-20
E
In~utOdbm
r.. r- .........
-10
-40
Figure 12. Input Limiting versus Temperature
Figure 11. Meter Current versus Temperature
600
II
......
W
-60
!z
l:l!
IX:
,
i""---.
taw
..... 700
~-6.0
5-6.0
w
IX: -10
o
:;: -12
......
E -60
f:@
w
Cl
z
.~
" ......, l":::::~
-.... ... ,::' ...... ~.....:...;
120
/"
~
:::; -80
~
:-- ...........
.,;-"
0-
Z
......... .........:::: ........ "
" ...... ....
-20 0
20 40
60 80 100
TA. AMBIENT TEMPERATURE (0C)
-70
>=
..........
-60
1--'
(f)
-; -90
:>
140
-60 -40 -20
0 20
40 60 80 100 t20
TA. AMBIENT TEMPERATURE (OC)
140
Figure 13. Input Impedance, Pin 5
1.0
0.5
o
1.0
8-124
MOTOROLA ANALOG IC DEVICE DATA
MC13055
Figure 14. Test Fixture
(Component Layout)
II
1~"'--------4" ---------1.-'
(Circuit Side View)
4"
1
.4
.1
.-
-
-
-
MOTOROLA ANALOG IC DEVICE DATA
-
-
-
4"
----------'~I
8-125
II
!
~
Figure 15. Internal Schematic
i~
n c- ~"
74
-
~r
lr '
77
85
>-013
66
78 79
:-~
68
92
89
91
90
14
~,
'
.
94
92
~-t
69
12 0--
1
'
~~"
_~'r
8(
1
15
~
46 ,
65
5
==1
~
0
:a
6
7
':~~~x
~HHHH~'
>
5~
I""
0
"c
('j
m
:$1
0
m
C
~
):Ii
3
......,z6
'" 58
~
'1 57
~
"1 56
~
'" 55
~
'-t 54
~
52
"1'
~
Co)
en
~'36
T
......25
=i=
s:
o
.....
g
8
L
~~~~
26
0
l>
Z
l>
Q
9
. 4
tft~
38
10
27
3~
",29
'28
48
11
47
51
'-153
'-t
~
~ ~50
49
MC13055
GENERAL DESCRIPTION
The MC13055 is an extended frequency range FM IF,
quadrature detector, signal strength detector and data
shapero It is intended primarily for FSK data systems. The
design is very similar to MC3356 except that the
oscillator/mixer has been removed, and the frequency
capability of the IF has been raised about 2:1. The detector
output configuration has been changed to a balanced,
open--collector type to permit symmetrical drive of the data
shaper (comparator). Meter drive and squelch features have
been retained.
The limiting IF is a high frequency type, capable of being
operated up to 100 MHz. It is expected to be used at 40 MHz
in most cases. The quadrature detector is internally coupled
to the IF, and a 2.0 pF quadrature capacitor is internally
provided. The 20 dB quieting sensitivity is approximately
20 IlV, tuned input, and the IF can accept signals up to
220 mVrms without distortion or change of detector
quiescent DC level.
The IF is unusual in that each of the last 5 stages of the
6 stage limiter contains a signal strength sensitive, current
sinking device. These are parallel connected and buffered
to produce a signal strength meter drive which is fairly linear
for IF input signals of 20 IlV to 20 mVrms (see Figure 4).
A simple squelch arrangement is provided whereby the
meter current flowing through the meter load resistance flips
a comparator at about 0.8 Vdc above ground. The signal
strength at which this occurs can be adjusted by changing
the meter load resistor. The comparator (+) input and output
are available to permit control of hysteresis. Good positive
action can be obtained for IF input signals of above
20 IlVrms. A resistor (R) from Pin 13 to Pin 12 will provide
VCclR of feedback current. This current can be correlated to
an amount of signal strength hysteresis by using Figure 4.
The squelch is internally connected to the data shapero
Squelch causes the data shaper to produce a high (VCC)
output.
The data shaper is a complete "floating" comparator, with
diodes across its inputs. The outputs of the quadrature
detector can be fed directly to either or preferably both inputs
of the comparator to produce a squared output swinging from
VCC to ground in inverted or noninverted form.
II
MOTOROLA ANALOG IC DEVICE DATA
8-127
®
MOTOROLA
MC13109
Universal Cordless Telephone
Subsystem IC
UNIVERSAL CT-1
SUBSYSTEM
INTEGRATED CIRCUIT
The MC131 09 integrates several of the functions required for a cordless
telephone into a single integrated circuit. This significantly reduces
component count, board space requirements, and external adjustments. It is
designed for use in both the handset and the base.
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna Input to Audio Output
80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic Discriminator
52
• Compander
- Expandor Includes Mute, Digital Volume Control and Speaker Driver
- Compressor Includes Mute, ALC and limiter
II
1
FBSUFFIX
PLASTIC PACKAGE
CASE848B
(QFP-52)
•
• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with No External Switches
- Universal Design for Domestic and Foreign CT-1 Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector, and 14-Bit
Programmable Counter and 2nd LO with 12-Bit Counter
- Transmit Section Contains Phase Detector and 14-Bit Counter
- MPU Clock Output Eliminates Need for MPU Crystal
48
1
FTASUFFIX
PLASTIC PACKAGE
CASE 932
(ThinQFP)
• Supply Voltage Monitor
- Externally Adjustable Trip Point
ORDERING INFORMATION
• 2.0 to 5.5 V Operation with One-Third the Power Consumption of
Competing Devices
• AN1575: Refer to Application Note for a List of "Worldwide Cordless
Telephone Frequencies" (Chapter 8 Addendum of DL128 Data Book)
Device
Tested Operating
Temperature Range
MC13109FB
MC13109FTA
Package
QFP-52
TA = -20° to +85°C
TQFP-48
Simplified Block Diagram
Rxln ---+--~
Rx
Out
+--<
Carrier -+-_ _
Detect
Tx In -+---+------1
Tx Out -+---+--.':===~
Low
i----I----J'--- Battery
L--_ _- '
Indicator
Tx VCO -+---+----1
This device contains 6,609 active transistors.
IH28
MOTOROLA ANALOG IC DI;VICE DATA
MC13109
Figure 1. MC131 09FB Test Circuit
~-~~~~--~77------------4-----------------------------------------------,
o
ExLCJn o
Open
VCCE
A32
lOOk
~
-
o
ExCAef
C35
LOI
A31
lOOk
Open
O.OI~F
MixUn
VCC
C43
...----------'-1
O.1~F
In
330
Oul
In
~
Gnd ~
Out
~
C34
1.0~F
CF2
C5
O.1~F
R24
10
R23
1.5k
EXCjF
r-.-'o/OIIr-+-""~-'"
C33 0.1 ~F 455k
In
R23
10.2
L2
R22
12k
A12
lOOk
L--,--.....,.,~----t---O
VCCD
13 DA
12 DB
14 VCC Ls!nd
A16
49.9k
A9
1.0k
VCCA
cia
CIU.OV
1.0~F
,~! I~
'-_______
r
DeCOul
C21
C23
~
O.OOI~F
C22
O.I~F
A17
5.62k
AlB
20k
Open
Rlll.Ok
l__~====~------~~====~~ ~Om
C17
DA Ul0m
DB
A14
130
147~F
o---Q EXCSAJn
ExpJF
SA_CUI
MOTOROLA ANALOG IC DEVICE DATA
8-129
II
MC13109
Figure 2. MC13109FTA Test Circuit
AX..Audlo
o
Open
A32
lOOk
o
lC47
l,~
MIC_
Amp
Out
VCCI2 ExLRef
A2B
o Open
49,9k
A29
A31
C46
9 Tlun
ExLC)n
VCCE
49,91<
lOOk
A36 0,0047
22,lk ~F
A35
32,4k
C45
A34 O,l~F
Cl
9-35pF
1,5k
I}--'-::::-:------;;------'-j In
~
~
C5
A2
O,I~F
32,4k
AI
1,5k
I}-~
_________
AS
32,4k
8
CF2
~In
,.
~
Gnd
!!,l
3 Out
1ll
A4
lOOk
+--I--1N5"1~40--+ C1
+----l~----i 15pF
C13
0.01
A22
12k
L._-+-ICY--t~F
~
5,OV
AudloJnJn
DA..FiI
o
Open
CIU,OV
DA..ln
A16
49,9k
CIB
Rll
1,Ok
4
1,0~F
r; r'I~F
C19
C20
Ul
DA
5 DB
14 VCC
Ul
Gnd 7
DA
DB
' -_ _ _ _ _ _ _ _ _ _ _1"'-14 VCC
lS09
Out 3
Gnd 7
LS09
&-130
MOTOROLA ANALOG IC DEVICE DATA
MC13109
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
Vee
-0.5 to +5.5
Vdc
Junction Temperature
TJ
-65 to +150
°e
NOTE: 1. Devices should not be operated at these limits. The "Recommended Operating Conditions"
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Min
TYP
Max
Unit
Vee
2.0
-
5.5
Vdc
Operating Ambient Temperature
-20
-
85
°e
Characteristic
NOTE: All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (Vee =2.6 V, TA =25°C, RF In =46.61 MHz, fDEV =±3.0 kHz,
fmod = 1.0 kHz; Test Circuit Figure 1.)
Characteristic
POWER SUPPLY
Static Current
Active Mode (Vee =2.6 V)
Active Mode (Vee =3.6 V)
Receive Mode (Vee =2.6 V)
Receive Mode (Vee =3.6 V)
Standby Mode (Vee =2.6 V)
Standby Mode (Vee =3.6 V)
Inactive Mode (Vee =2.6 V)
Inactive Mode (Vee =3.6 V)
MOTOROLA ANALOG IC DEVICE DATA
Min
Typ
Max
Unit
-
6.7
7.1
4.3
4.5
300
600
40
56
12
mA
mA
mA
mA
IlA
IlA
IlA
IlA
-
7.0
600
80
-
II
8-131
MC13109
ELECTRICAL CHARACTERISTICS (continued)
FM Receiver
The FM receivers can be used with either a quad coil or a
ceramic resonator. The FM receiver and 1st LO have been
designed to work for all country channels, including 25
channel U.S., without the need for any external switching
circuitry (see Figure 29).
(Test Conditions: VCC = 2.6 V, TA = 25°C, fO = 46.61 MHz, fDEV = ±3.0 kHz, fmod = 1.0 kHz.)
Characteristic
Condition
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
VSIN
-
0.7
-
I1Vrms
Sensitivity (Input for 12
dBSINAD)
Matched Impedance
Differential Input
Mixl
Inl/2
DetOut
1st Mixer Conversion
Gain
Yin = 1.0 mVrms, with
CFl Load
Mixl
Inl/2
CFl
MXgainl
-
10
-
dB
2nd Mixer Conversion
Gain
Yin = 3.0 mVrms, with
CF2 Load
Mix21n
CF2
MXgain2
-
20
-
dB
1st and 2nd Mixer Gain
Total
Yin = 1.0 mVrms, with
CFl and CF2 Load
Mixl
Inl/2
CF2
MXgainT
24
30
-
dB
1st Mixer Input
Impedance
-
-
Mixllnl
Mixl1n2
Zinl
-
1.0
-
kO
2nd Mixer Input
Impedance
-
-
Mix21n
Zin2
-
3.0
-
kG
1st Mixer Output
Impedance
-
-
Mixl0ut
Zoutl
-
330
-
0
2nd Mixer Output
Impedance
-
-
Mix20ut
Zout2
-
1.5
-
kG
IF -3.0 dB Limiting
Sensitivity
fin =455 kHz
Lim In
DetOut
IF Sens
-
55
-
I1Vrms
Total Hannonic Distortion
(CCITT Atter)
With RC = 8.2 knI
0.01 I1F Filter at Det
Out
Mixl
Inl/2
DetOut
THD
-
0.7
-
%
Recovered Audio
With RC = 8.2 knI
0.01 I1F Filter at Det
Out
Mixl
Inl/2
DetOut
AFO
80
100
154
mVrms
-
Lim In
DetOut
BW
-
20
-
kHz
Signal to Noise Ratio
Yin = 10 mVrms,
RC = 8.2 knlO.01 I1F
Mixl
Inl/2
DetOut
SN
-
49
-
dB
AM Rejection Ratio
30% AM, Vin=
10mVrms,
RC = 8.2 knlO.001 I1F
Mix1
Inl/2
DetOut
AMR
-
37
-
dB
First Mixer 3rd Order
Intercept (Input
Referred)
Matched Impedance
Input
Mix1
Inl/2
Mix10ut
TOlmixl
-
-10
-
dBm
Second Mixer 3rd
Order Intercept (Input
Referred)
Matched Impedance
Input
Mlx21n
Mix20ut
TOlmix2
-
-27
-
dBm
-
DetOut
Zo
-
870
-
0
Demodulator Bandwidth
Detector Output
Impedance
8-132
-
MOTOROLA ANALOG IC DEVICE DATA
MC13109
ELECTRICAL CHARACTERISTICS (continued)
RSSIICarrier Detect
Connect 0.01 !LF to Gnd from "RSSI" output pin to form the
carrier detect filter. "CD Out" is an open collector output
which requires an external 100 kn pull-up resistor to Vce.
The carrier detect threshold is programmable through the
MPU interface.
(RL = 100 kn, VCC = 2.6 V, TA = 25'C.)
Characteristic
RSSI Output Current
Dynamic Range
Carrier Sense Threshold
Condition
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
-
Mix11n
RSSI
RSSI
-
65
-
dB
CO Threshold Adjust =
(10100)
Mix11n
CO Out
VT
-
22.5
-
JlVrms
-
Mix11n
CO Out
Hys
-
2.0
-
dB
Output High Voltage
Vin = 0 JlVrms, RL =
100 kn, CO = (10100)
Mix11n
CO Out
VOH
VCC-0.1
2.6
-
V
Output Low Voltage
Vin = 100 JlVrms, RL =
100 kQ, CO = (10100)
Mix11n
CO Out
VOL
-
0.01
0.4
V
Carrier Sense Threshold
Adjustment Range
Programmable through
MPU Interface
-
-
VTrange
-20
-
11
dB
Carrier Sense Threshold
- Number of Steps
Programmable through
MPU Interface
-
-
VTn
-
32
-
-
Hysteresis
Data Amp Comparator (see Figure 4)
Inverting hysteresis comparator. Open collector output
with internal 100 kQ pull-up resistor. A band pass filter is
connected between the "Det Ouf' pin and the "DA In" pin with
component values as shown in the attached block diagram.
The "DA In" input signal is ac coupled.
(VCC=26V TA=25°C)
Condition
Input
Pin
Measure
Pin
Symbol
Hysteresis
-
OAln
OAOut
Hys
Threshold Voltage
-
OAln
OAOut
VT
Input Impedance
-
-
OAln
Output Impedance
-
-
Characteristic
Min
Typ
Max
Unit
40
50
mV
VCC-0.9
VCC-0.7
VCC-O.s
V
ZI
-
11
-
kQ
OAOut
Zo
-
100
-
kQ
30·
Output High Voltage
Vin = VCC-1.0V,
IOH=OmA
OAln
OAOut
VOH
VCC-O.1
2.6
-
V
Output Low Voltage
Vin = VCC - 0.4 V,
IOL=OmA
OAln
OAOut
VOL
-
0.03
0.4
V
MOTOROLA ANALOG Ie DEVICE DATA
8-133
II
MC13109
ELECTRICAL CHARACTERISTICS (continued)
Pre-AmplifierlExpanderiRx MuteNolume Control (See Figure 4)
The Pre-Amplifier is an inverting rail-to-rail output swing
the half supply reference so the input and output swing
capability will increase as the supply voltage increases. The
operational amplifier with the non-inverting input terminal
volume control can be adjusted through the MPU interface.
connected to the internal VB half supply reference. External
resistors and capacitors can be connected to set the gain and
The "Rx Audio In" input signal is ac coupled.
frequency response. The expander analog ground is set to
(Test Conditions' VCC = 2 6 V TA = 25°C 'in = 10kHz, Set External Pre-Amplifier R's for Gain of I, Volume Control = (0111»
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
-
RxAudio
In
Pre-Amp
AVOL
-
60
-
dB
-
RxAudio
In
Pre-Amp
GBW
-
100
-
kHz
Pre-Amp Maximum
Output Swing
RL= 10k.Q
RxAudio
In
Pre-Amp
VOmax
-
VCC-0.3
-
Vpp
Expander 0 dB Gain
Level
Vin=-10dBV
RxAudio
In
EOut
G
-3.0
-0.11
3.0
dB
Expander Gain
Tracking
Vin = -20 dBV, Output
RelatlvetoG
Vin = -30 dBV, Output
RelativetoG
RxAudio
In
EOut
Gt
-21
-19.65
-19
dB
-42
-39.42
-37
Total Harmonic
Distortion
Vin = -10 dBV
RxAudio
In
EOut
THD
-
0.5
-
%
Maximum Output
Voltage
Increase input voRage
until output- voltage
THD = 5%, then
measure output
voltage. RL = 10 k.Q
RxAudio
In
EOut
VOmax
"'"
-5.0
-
dBV
Attack Time
Ecap = 1.0 IlF,
Rfilt=20kQ
(See Appendix B)
RxAudio
In
EOut
ta
-
3.0
-
ms
Release Time
Ecap = 1.0 IlF,
Rfilt=20kQ
(See Appendix B)
RxAudio
In
EOut
tr
-
13.5
-
ms
Compressor to
Expander Crosstalk
V (Rx Audio In)
= 0 Vrmli.
Vin=-10dBV
Cln
EOut
CT
-
-
-70
dB
RxMute
Vin=-10dBV
No popping
detectable during Rx
Mute transitions
RxAudio
In
EOut
Me
-
-70
-
dB
Volume Control Range
Programmable through
MPU Interface
-
-
VCrange
-14
-
16
dB
Volume Control Steps
Programmable through
MPU Interface
-
-
VCn
-
16
-
-
Characteristic
Condition
Pre-Amp Open Loop
Gain
Pre-Amp Gain
Bandwidth
8-134
MOTOROLA ANALOG IC DEVICE-DATA
MC13109
ELECTRICAL CHARACTERISTICS (continued)
Speaker AmplifierlSP Mute
The Speaker Amplifier is an inverting rail-to-rail
operational amplifier. The non-inverting input terminal is
connected to the internal VB half supply reference. External
resistors and capacitors are used to set the gain and
frequency response. The "SA In" input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.)
Characteristic
Maximum Output
Swing
SP Mute
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
VCC=2.3V,
RL=l30Q
VCC=2.3V,
RL=600Q
VCC=3.4 V,
RL=600Q
SA In
SA Out
VOmax
-
0.8
-
Vpp
-
2.0
-
-
3.0
-
Vin =-20 dBV
RL=130Q
No popping detectable
during SP Mute
transitions
SA In
-
-70
-
Condition
SA Out
Mic Amplifier (See Figure 6)
The Mic Amplifier is an inverting rail-to-rail output
operational amplifier with the non-inverting input terminal
connected to the internal VB half supply reference. External
Msp
dB
resistors and capacitors are connected to set the gain and
frequency response. The ''Tx In" input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.)
Condition
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Open Loop Gain
-
Tx In
Amp Out
AVOL
-
60
-
dB
Gain Bandwidth
-
Tx In
Amp Out
GBW
100
-
kHz
RL= 10ka
Txln
Amp Out
VOmax
-
VCC-0.3
-
Vpp
Characteristic
Maximum Output
Swing
MOTOROLA ANALOG IC DEVICE DATA
Unit
8-135
II
MC13109
ELECTRICAL CHARACTERISTICS (continued)
Compressor/ALcrrx Mute/Limiter (See Figure 5)
The compressor analog gound is set to the half supply
reference so the input and output swing capability will
increase as the supply voltage increases. The "C In" input is
ac coupled. The ALC (Automatic Level Control) provides a
soft limit to the output signal swing as the input voltage
increases slowly (Le., a sine wave is maintained). The Limiter
circuit limits rapidly changing signal levels by clipping the
signal peaks. The ALC and/or Limiter can be disabled
through the MPU serial interface.
(Test Conditions: VCC = 2.6 V, lin = 1.0 kHz, TA = 25°C.)
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
Compressor 0 dB Gain
Level
Vin=-10dBV, ALC
disabled, Limiter
disabled
Cln
Lim Out
G
-3.0
- =-12 dBV, Vout = 0.8 Vpp
-30
/
-40
",
V
.....-
V
=
-50
-80
Vin=-2.5dBV, Vout =-12 dBV
~
~
!3
§
I
-40
-30
(Rapidly Changing Limited Signals)
Yin > = -28 dBV, Vout = 2.25 Vpp
I
.L ___
Vin=-24dBV, Vout =-17 dBV
(Slowly Changing ALC Signals)
I
I
I
-50
-80
~
:8.
I
D-
S
k
=
Figure 6. Total T x Path, Mic Amp Gain 16 dB,
Splatter Amp Gain 9.0 dB
10.---.----.,---.----.----,----.----,
:> Figure 5. Typical Compressor/ALC/Limiter Response
-20
-10
o
-50
-60
-40
-30
-20
o
-10
INPUT LEVEL, Tx INPUT (dBV)
COMPRESSOR, Cin LEVEL INPUT (dBV)
Figure 7. MC13109FTA Internal I/O Block Diagram
Spl
Ref
Tx
Out
Amp
In
Lim
Out
C
Cap
Cln
Amp
Out
Gnd
Audio
L~
Mixl
In
Inl
Mixl
In2
PLL
Mix1
Vref
Out
Rx
PD
Gnd
PLL
Tx
PD
Tx
VCO
VCCRF
Clk
Out
CDOuV
Hardware
Interrupt
BD
Out
DA
Out
SA
SA
Out
In
MOTOROLA ANALOG IC DEVICE DATA
EOut
Vec
Audio
DA
In
PreAmp
Out
Rx
Audio
In
Det
Out
RSSI
8-139
II
MC13109
PIN FUNCTION DESCRIPTION
48-TQFP
Pin
52-QFP
Pin
Symbol
Type
1
2
1
2
L021n
L020ut
-
3
3
PLLVref
Supply
Description
These pins form the PLL reference oscillator when connected to an external
parallel-resonant crystal (10.24 MHz typical). The reference oscillator is also the
second Local Oscillator (L02) for the RF receiver.
Vo~age Regulator output pin. The internal voltage regulator provides a stable power
supply voltage for the Rx and T x PLL's and can also be used as a regulated supply
voltage for the other IC's.
II
4
4
RxPD
5
5
Gnd PLL
Gnd
6
6
TxPD
Output
7
7
ECap
-
8
8
Tx VCO
Input
Transmit divide counter input which is driven by an ac coupled external transmit
loop VCO. The minimum signal level is 200 mVpp @ 80.0 MHz. This pin also
functions as the test mode input for the counter tests.
9
10
11
9
10
11
Data
EN
Clk
Input
Microprocessor serial interface input pins for programming various counters and
control functions.
12
12
ClkOut
Output
Microprocesor Clock Output which is derived from the 2M LO crystal oscillator and
a programmable divider. It can be used to drive a microprocessor and thereby
reduce the number of crystals required in the system design. The driver has an
intemal resistor in series with the output whch can be combined with an extemal
capacitor to form a low pass filter to reduce radiated noise on the PCB. This output
also functions as the output for the counter test modes.
N/A
14
Status Out
Output
This pin indicates when the internal latches may have lost memory due to a power
glitch.
13
15
CD Out!
Hardware
Interrupt
Output!
Input
Dual function pin; 1) Carrier detect output (open collector w~h external 100 k.Q
pull-up resistor. 2) Hardware interrupt input which can be used to "wake-up' from
Inactive Mode.
14
16
BDOut
Output
Low battery detect output (open collector with extemal pull-up reSistor).
15
17
DAOut
Output
Data amplifier output (open collector with internal 100 kQ pull-up resistor).
16
18
SA Out
Output
Speaker amplifier output.
Output
Three state voltage output of the Rx Phase Detector. This pin is either "high", "low",
or "high impedance" depending on the phase difference of the phase detector input
signals. During lock, very narrow pulses with a frequency equal to the reference
frequency are present. This pin drives the external Rx PLL loop filter. It is important
to minimize the line length and capacnance of this pin.
Ground pin for PLL section of IC.
Three state voltage output of the T x Phase Detector. This pin is either "high", "low",
or "high impedance" depending on the phase difference of the phase detector input
signals. During lock, very narrow pulses with a frequency equal to the reference
frequency are present. This pin drives the external T x PLL loop filter. It is important
to minimize the line length and capacitance on this pin.
Expander rectHier filter capacitor pin. Connect capacitor to VCC.
17
19
SA In
Input
18
20
EOut
Output
Expander output.
VCC supply for audio section.
Speaker amplifier input (ac coupled).
19
21
VCCAudio
Supply
20
22
DAln
Input
21
23
Pre-Amp Out
Output
22
24
RxAudio In
Input
23
25
DetOut
Output
24
26
RSSI
-
N/A
27
N/A
-
Note used.
25
28
QCoil
-
A quad coil or ceramic discriminator are connected to this pin.
26
29
VCCRF
Supply
27
28
30
31
LimC2
LimC1
-
11-140
Data amplHier input (ac coupled).
Pre-amplifier output for connection of pre-amplifier feedback resistor.
Rx audio input to pre-amplifier (ac coupled).
Audio output from FM detector.
Receive signal strength indicator filter capacitor.
VCC supply for RF receiver section.
IF amplifierllimiter capacitor pins.
MOTOROLA ANALOG IC DEVICE DATA
MC13109
PIN FUNCTION DESCRIPTION (continued)
48-TQFP
Pin
52-QFP
Pin
Symbol
Type
Description
29
32
Lim In
Input
Signal input for IF amplifierllimiter.
30
33
GndRF
Gnd
Ground pin for RF section of the IC.
31
34
Mix20ut
Output
32
35
Mix21n
Input
33
36
VB
-
34
37
Mix10ut
Output
35
38
Mix11n2
Input
36
39
Mix11n1
Input
37
38
40
41
L011n
L010ut
-
Second mixer output.
Second mixer input.
Internal half supply analog ground reference.
First mixer output.
Negative polarity first mixer input.
Positive polarity first mixer input.
Tank elements for 1st LO multivibrator oscillator are connected to these pins.
39
42
VcapCtrl
-
40
43
Gnd Audio
Gnd
Ground for audio section of the IC.
T x path input to Microphone Amplifier (ac coupled).
41
44
Tx In
Input
42
45
Amp Out
Output
43
46
Cln
Input
44
47
CCap
-
45
48
Lim Out
Output
46
49
Spl Amp In
Input
47
50
Tx Out
Output
48
51
Ref
Input
N/A
52
N/A
-
1st LO varactor control pin.
Microphone amplifier output.
Compressor input (ac coupled).
Compressor rectifier filter capacitor pin. Connect capacitor to VCC.
T x path limiter output.
Splatter amplifier input (ac coupled).
T x path audio output.
Not used.
Power Supply Voltage
This circuit is used in a cordless telephone handset and
base unit. The handset is battery powered and can operate
on two ro three NiCad cells or on 5.0 V power.
PLL Frequency Synthesizer General Description
Figure 8 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL). This
dual PLL is fully programmable thorugh the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), France, Spain, Australia, Korea, New
Zealand, U.K., Netherlands and China (see channel
frequency tables in Appendix A).
The 2nd local oscillator and reference divider provide the
reference frequency for the Rx and T x PLL loops. The
MOTOROLA ANALOG IC DEVICE DATA
II
Reference voltage input for low battery detect.
programmed divider value for the reference divider is
selected based on the crystal frequency and the desired Rx
and T x reference frequency values. Additional divide by 25
and divide by 4 blocks are provided to allow for generation of
the 1.0 kHz and 6.25 kHz reference frequencies required for
the U.K. The 14-bit T x counter is programmed for the desired
transmit channel frequency. The 14-bit Rx counter is
programmed for the desired first local oscillator frequency. All
counters power up in the proper default state for USA
channel #6 and for a 10.24 MHz reference frequency crystal.
Internal fixed capacitors can be connected to the tank circuit
of the 1st LO through microprocessor control to extend the
sensitivity of the 1st LO for U.S. 25 channel operation.
8--141
MC13109
Figure 8. Dual PLL Simplified Block Diagram
Tx VCO
8,8
Tx
VCO
TxPD
LPF
6,6
12-b
+25
Programmable
+4
Reference
+1
Counter
RxPD
ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C)
Characteristic
Condition
Min
Max
VIL
-
0.3
V
VIH
'PLL Vref - 0.3
"VCCAudio"
V
IlL
-5.0
-
!lA
IIH
-
5.0
!lA
Vhys
1.0
-
V
RxPD
TxPD
10H
-
-0.7
rnA
RxPD
TxPD
10L
0.7
-
rnA
PLLPIN DC
-
Input Voltage Low
Data
Clk
EN
II
Hardware In!.
Input Voltage High
-
Data
Clk
Input Current Low
Yin = 0.3 V
Data
Clk
EN
EN
Input Current High
Yin = (VCC Audio) - 0.3
Data
Clk
EN
Hysteresis Voltage
-
Output Current High
-
Output Current Low
-
Output Voltage Low
IIL=0.7rnA
RxPD
TxPD
VOL
-
(PLL Vrefl* 0.2
V
Output Voltage High
IIH =-0. 7rnA
RxPD
TxPD
VOH
(PLL Vref)* 0.8
-
V
Tri--State Leakage Current
V= 1.2V
RxPD
TxPD
10Z
-50
50
nA
Cin
-
8.0
pF
Cout
-
8.0
pF
Data
Clk
EN
Input Capacitance
-
Data
Clk
Output Capacitance
-
RxPD
TxPD
EN
8-142
MOTOROLA ANALOG IC DEVICE DATA
MC13109
ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C)
Characteristic
Condition
Min
Max
PLL PIN INTERFACE
EN to Clk Setup Time
-
EN, Clk
Data to Clk Setup Time
-
Data, Clk
Hold Time
-
Data, Clk
tsuEC
200
-
ns
tsuDC
100
ns
th
90
Recovery Time
-
EN, Clk
tree
90
-
Input Pulse Width
-
EN,Clk
tw
100
-
ns
Input Rise and Fall Time
-
Data
Clk
EN
tr,tl
-
9.0
Ils
MPU Interface Power-Up
Delay
90% 01 PLL Vrel to
Data, Clk, EN
ns
ns
-
-
!puMPU
-
100
IlS
Measure
Pin
Symbol
Min
Max
Unit
L021n
L02°ut
lLO
-
12
MHz
TxVCO
Itxmax
-
80
MHz
PLLLOOP
Characteristic
Condition
-
2nd LO Frequency
"Tx VCO" Input Frequency
Vin = 200 mVpp
PLL I/O Pin Specifications
The 2nd LO, Rx and Tx PLL's and MPU serial interface are
normally powered by the internal voltage regulator at the
"PLL Vref' pin. The "PLL Vref' pin is the output of a voltage
regulator which is powered from the "Vee Audio" power
supply pin. Therefore, the maximum input and output levels
for most PLL 1/0 pins (L02 In, L02 Out, Rx PD, Tx PD, Tx
VeO) is the regulated voltage at the "PLL Vret" pin. The ESD
protection diodes on these pins are also connected to "PLL
Vref'. Internal level shift buffers are provided for the pins
(Data, elk, EN, elk Out) which connect directly to the
microprocessor. The maximum input and output levels for
these pins is Vee. Figure 9 shows a simplified schematic of
the PLL 1/0 pins.
Figure 9. PLL I/O Pin Simplified Schematics
PLL Vref
(2.2 V)
VCC Audio
(2.0 to 5.5 V)
PLL Vref
(2.2 V)
VCC Audio
(2.0 to 5.5 V)
OO+'"~~~~~
-=
L02 In, L02 Out,
Rx PO, Tx PO and
Tx veo Pins
-= -=
2.0 I!A -=
Data, Clk, and EN Pins
-=-=
ClkOutPin
Microprocessor Serial Interface
The "Data", "elk", and "EN" pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counter and various
control functions. The "Data" and "elk" pins are used to load
data into the shift register. Figure 10 shows "Data" and "elk"
pin timing. Data is clocked on positive clock transitions.
MOTOROLA ANALOG IC DEVICE DATA
Figure 10. Data and Clock Timing Requirement
II
II
Data,
Clk, EN
Data
Clk------'
\"----
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the "EN" pin.
This is done in two steps. First, an 8-bit address is loaded
into the shift register and latched into the 8-bit address latch
register. Then, up to 18-bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 11 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
Figure 11. Enable Timing Requirement
EN _ _ _. J
Previous Data Latched
8-143
MC13109
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 12 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when "EN" is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the "EN" high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
Figure 12. Microprocessor Interface Programming
Mode Diagrams
oata---{ MSB
ENJ
8-BH Address
Address Register Programming Mode
oata---{ MSB
16-BitOata
LSB)-____________________
-J
~
~~t~
EN __________________________
2.0_V____
~L...PU
__......;___
elk, EN
Status Out
This is a digital output which indicates whether the latch
registers have, been reset to their power-up default values.
Latch power-up default values are given in Figure 32. If there
is a power glitch or ESD event which causes the latch
registers to be reset to their default values, the "Status our
pin will indicate this to the MPU so it can reload the correct
information into the latch registers.
~
The MPU serial interface is fully operational within 100 j.1s
after the power supply has reached its minimum level during
power-up (See Figure 13). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx , and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
8-144
:-A
______
Figure 14. Status Out Operation
~I
Oata Register Programming Mode
II
Figure 13. Microprocessor Serial Interface
Power-Up Delay
Status Latch Register Bits
Status Out
Logic Level
Latch bits not at power-up default value
0
Latch bits at power-up default value
1
Data Registers
Figure 1'5 'shows the data latch'registers and addresses
which are used to select each of these registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
"Don't care" bits can be loaded into the shift register first if
8-bit bytes of data are loaded.
'
MOTOROLA ANALOG IC DEVICE DATA
MC13109
Figure 15. Microprocessor Interface Data Latch Registers
>
Latch Address
14-Bit Tx Counter
LSB
1. (00000001)
Tx Counter Latch
14-Bit Rx Counter
LSB )
2. (00000010)
Rx Counter Latch
MSB
12-Btt Reference Counter
LSB
3. (00000011)
Reference Counter Latch
4. (00000100)
l~it
Mode Control Latch
5-Bit CD Threshold Control
5. (00000101)
Threshold Control Latch
6. (00000110)
7. (00000111)
7-Bit Auxiliary Latch
Reference Frequency Selection
The "L02In" and "L02 Out" pins form a reference oscillator
when connected to an external parallel-resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 16 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries.
Figure 16. Reference Frequency and
Reference Divider Values
Crystal
Frequency
Reference
Divider
Value
U.K. Basel
Handset
Divider
Reference
Frequency
10.24 MHz
10.24 MHz
2048
1
5.0 kHz
1024
4
2.5 kHz
11.15 MHz
2230
1
5.0 kHz
12.00 MHz
2400
1
5.0 kHz
11.15 MHz
1784
1
6.25 kHz
11.15MHz
446
4
6.25 kHz
11.15MHz
446
25
1.0 kHz
MOTOROLA ANALOG IC DEVICE DATA
Reference Counter
Figure 17 shows how the reference frequencies for the Rx
and Tx loops are generated. All countries except U.K. require
that the Tx and Rx reference frequencies be identical. In this
case, set "U.K. Base Selecf' and "U.K. Handset Selecf' bits
to "0". Then the fixed divider is set to "1" and the Tx and Rx
reference frequencies will be equal to the crystal oscillator
frequency divided by the programmable reference counter
value. The U.K. is a special case which requires a different
reference frequency value fo T x and Rx.
For U.K. base operation, set "U.K. Base Select" to "1". For
U.K. handset operation, set "UK Handset Selecf' to "1". The
Netherlands is also a special case since a 2.5 kHz reference
frequency is used for both the Tx and Rx reference and the
total divider value required is 4096 which is larger than the
maximum divide value available from the 12-bit reference
divider (4095). In this case, set "U.K. Base Select" to "1" and
set "U.K. Handset Select" to "1". This will give a fixed divide
by 4 for both the Tx and Rx reference. Then set the reference.
divider to 1024 to get a total divider of 4096.
Mode Control Register
Power saving modes, mutes, disables, volume control,
and microprocessor clock output frequency are all set by the
Control Register. Operation of the Control Register is
explained in Figures 18 through 25.
8-145
MC13109
Figure 17. Reference Register Programming Mode
U.K. Base
~
12-b
Tx Reference Frequency
U.K. Handset
+ 25
Programmable + 4 I--++~.~
Reference
......U.K. Base
Counter
+1
- .......
Rx Reference Frequency
U.K. Handset
U.K. Handset
Select
U.K. Base
Select
TxDivider
Value
RxDivider
Value
Application
0
0
1
1
0
1
0
1
1
25
4
4
1
4
25
4
. All but U.K. and Nethe~ands
U.K. Base Set
U.K. HandSet
Netherlands Base and Hand Set
MSI;l
12-8it Ref Counter
LSB
14--Bit Reference Counter Latch
Figure 18. Control Register Bits
Figure 19. Mute and Disable Control Bit Descriptions
ALC Disable
1
0
Automatic Level Control Disabled
Normal Operation
Limiter Disable
1
0
Limiter Disabled
Normal Operation
Clock Disable
1
0
MPU Clock Output Disabled'
Normal Operation
Tx Mute
1
0
Transmit Channel Muted
Normal Operation
Rx Mute
1
0
Receive Channel Muted
Normal Operation
SPMute
1
0
Speaker Amp Muted
Normal Operation
Power Saving Operating Modes
When the MC13109 is used in a handset, it is important to
conserve power in order to prolong battery life. There are five
modes of operation; Active, Rx , Standby, Interrupt and
Inactive. In Active Mode, all circuit blocks are powered. In Rx
mode, all circuitry is powered down exept for those circuit
8-146
sections needed to receive a transmission from the base. In
the Standby and Interrupt Modes, all circuitry is powered
down except for the circuitry needed to provide the clock
output for the microprocessor. In Inactive Mode, all circuitry is
powered down except the MPU interface. Latch memory is
maintained in all modes. Figure 20 shows the control register
bit values for selection of each power saving mode and
Figure 21 show the circuit blocks which are powered in each
of these operating mode.
Figure 20. Power Saving Mode Selection
Stdby
Mode
Bit
Rx
Mode
Bit
"CD OutlHardware
Interrupt" Pin
Power Saving
Mode
0
0
X
Active
0
1
X
Rx
1
0
X
Standby
1
1
1 or High Impedance
Inactive
1
1
0
Inactive
MOTOROLA ANAI-OG IC DEVICE DATA
MC13109
Figure 21. Circuit Blocks Powered During Power Saving Modes
Active
Rx
Standby
Inactive
"PLL Vrel" Regulated
Voltage
X
X
Xl
Xl
MPU Interface
X
X
X
X
2nd LO Oscillator
X
X
X
MPU Clock Output
X
X
X
X
Circuit Blocks
RF Receiver
X
1st LOVCO
X
X
RxPLL
X
X
Carrier Detect
X
X
Data Amp
X
X
Low Battery Detect
X
X
TxPLL
X
Rx Audio Path
X
Tx Audio Path
X
NOTE: 1. In Standby and Inactive Modes, 'PLL Vrer remains powered but is not regulated. It will fluctuate wHh Vee.
Inactive Mode Operation and Hardware Interrupt
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the MC13109 into the Inactive mode, which turns off the
MPU Clock Output (see Figure 22), and then disable the
microprocessor. In order to give the MPU adequate time to
power down, the MPU Clock output remains active for a
minimum of one reference counter cycle (about 200 ~s) after
the command is given to switch into the "Inactive" mode. An
external timing circuit should be used to initiate the turn-on
sequence. The "CD Out" pin has a dual function. In the Active
and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is
disabled and the "CD Ouf' pin is in a "High" state due to the
external pull-up resistor. In the Inactive mode the "CD Out"
pin is the input for the hardware interrupt function. When the
"CD Out" pin is pulled "low" by the external timing circuit, the
MC13109 swtiches from the Inactive to the Interrupt mode
thereby turning on the MPU Clock Output. The MPU can then
resume control of the combo IC. The "CD Out" pin must
remain low until the MPU changes the operating mode from
Interrupt to Standby, Active or Rx modes.
Figure 22. Hardware Interrupt Operation
Mode
ActiveIR x
IV
EN
CD OuVHardware Interrupt
Inactive
CD Out Low
i.
I ,
MPU Clock Out
1
I
Delay after MPU selects Inactive Mode to when CD turns off.
MOTOROLA ANALOG IC DEVICE DATA
Interrupt
'" MPU Initiates
Inactive Mode
-I ~
--!OJ
.....,......,
r
/
CDTumsOff
"'
Standby/Rx/Active
External Timer
Pulls Pin Low
/
MPU Initiates
Mode Change
I'limeroutput
Disabled
""'- K
1
1
1_
"MPU Clock Oul' remains active for a minimum of one count of reference
counter after 'CD OuVHardware Interrupt" pin goes high
8-147
II
MC13109.·
"Clk Out" Divider Programming
The "Clk Out" pin is derived from the 2nd local oscillator
and can be used to drive a microprocessor, thereby reducing
the number of crystals required. Figure 23 shows the
relationship between the crystal frequency and the clock
output for different divider values. Figure 24 shows the "Clk
Out" register bit values.
Flgur. 23. Clock Output Valu ••
Crystal
Frequency
Clock Output Divider
2
3
5
10
10.24 MHz
5.120 MHz
3.413 MHz
2.5aOMHz
2.046 MHz
11.15 MHz
5.575 MHz
3.717 MHz
2.788 MHz
2.230 MHz
12.00 MHz
a.OOOMHz
4.000 MHz
3.000 MHz
2.400 MHz
Figure 24. Clock Output Dlvld.r
ClkOut
Bit #1
ClkOut
Bit #0
ClkOut
Divider Value
0
0
2
0
1
3
1
0
1
MPU"Clk Out" Radiated Nols. on Circuit Board
The clock line running between the MC13109 and the
microprocessor has the potential to radiate noise which can
cause problems in the system especially If the clock Is a
square wave digital signal with large high frequ.ncy
harmonics. In order to minimize radiated noise, a 1.0 kn
resistor is included on-chlp In-series with the "Clk Out" output
driver. A small capaCitor can be connected to the "Clk Ouf' line
on the PCB to form a single pole low pass filter. This filter will
significantly reduce noise radiated from the "Clk Out" line.
Volume Control
The volume control can be programmed in 2.0 dB gain
steps from -14 dB to +16 dB. The power-up default value is
OdB.
.
5
. 10
1
MPU "Clk Out" Pow.......Up Default Dlvld.r Value
The power-up default divider value Is "divide by 10". This
provld.s an MPU clock of about 1.0 MHz after initial
power-up. The reason for choosing this relatively low clock
frequency after Intlal power-up is that some microprocessors
that operate down to a 2.0 V power supply have a maximum
clock frequency fo 1.0 MHz. After initial power-up, the MPU
can change the clock divider value to set the clock to the
desired operating frequency. Special care has been taken in
the design of the clock divider to ensure that the transition
between one clock divider value and another Is "smooth"
(I.e., there will be no narrow clock pulses to disturb the MPU).
Flgur. 25. Volum. Control
Volume Control
Bit #3
Volume Control
Bit #2
Volume Control
Bit #1
Volume Control
Bit #0
Volume
Control #
Gain/Attenuation
Amount
0
0
0
0
0
-14dB
0
0
0
1
1
-12dB
0
0
1
0
2
-10dB
0
0
1
1
3
-8.0 dB
0
1
0
0
4
-6.0 dB
0
1
0
1
5
-4.0 dB
0
1
1
0
6
-2.0 dB
0
1
1
1
7
OdB
1
0
0
0
8
2.0 dB
1
0
0
1
9
4.0dB
1
0
1
0
10
a.OdB
1
0
1
1
11
8.0 dB
1
1
0
0
12
10dB
1
1
0
1
13
12dB
1
1
1
0
14
14 dB
1
1
1
1
15
16dB
Gain Control Register
The gain control register contains bits which control the
Carrier Detect threshold. Operation of these latch bits are
explained in Figures 26 and 27.
6-148
Figure 26. Gain Control Latch Bits
MBB
5-B1t CD Threshold Control
LBB
.MOTOROLA ANALOG IC DEVICE DATA
MC13109
Carrier Detect Threshold Programming
Th "CD Out" pin will give an indication to the
microprocessor if a carier signal is present on the selected
channel. The nominal value and tolerance of the carrier
detect threshold is given in the carrier detect specification
section of this document. If a different carrier detect threshold
value is desired, it can be set through the MPU interface as
shown in Figure 27 below.
Figure 27. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
Bit #1
CD
81t#O
CD
Control #
Carrier Detect
Threshold
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
-20 dB
1
1
-19dB
1
a
2
-18 dB
1
1
3
-17 dB
1
a
4
-16dB
1
a
a
1
5
-15 dB
1
1
a
6
-14 dB
1
1
1
7
-13dB
1
a
a
a
8
-12dB
1
9
-11 dB
1
a
10
-10dB
1
a
a
a
a
1
1
11
-9.0 dB
1
1
a
12
-8.0 dB
1
1
a
a
1
13
-7.0 dB
1
1
1
a
14
-6.0 dB
1
1
1
1
15
-5.0 dB
1
a
a
a
a
a
a
a
16
-4.0 dB
1
17
-3.0 dB
1
a
18
-2.0 dB
1
1
19
-1.0dB
1
a
20
OdB
1
a
a
1
21
1.0dB
1
1
a
22
2.0 dB
1
a
a
a
a
a
a
a
a
1
1
1
23
3.0 dB
1
1
0
0
0
24
4.0 dB
a
1
25
5.0 dB
1
a
26
6.0 dB
1
1
27
7.0 dB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
1
1
1
28
8.0 dB
1
1
a
a
a
1
1
29
9.0 dB
1
1
1
1
a
30
10dB
1
1
1
1
1
31
11 dB
MOTOROLA ANALOG IC DEVICE DATA
II
8-149
MC13109
schematic of the 1st LO tank circuit., Figure 30 shows the
latch control bit values.
The Internal varactor temperature coefficient Is 1800 ppm/°C
(CO =8.9 pF at 25°C, Vcap control voltage =1.2 V, Freq =
36 MHz). Customer Is sugg,ested to use a negative
temperature coefficient capacitor In 1st LO tank circuit when
the whole operating temperature range of -40 to +85°C Is
considered.
Auxiliary Reglater
The auxiliary register contains a 3-bit 1st LO Capacitor
Selection latch and a 4-bit Test Mode latch. Operation of
these latch bits are explained In Figures 28, 29 and 30.
Figure 28. Auxiliary Reglater Latch Bite
Msa
Lsa
+-BIt Test Mode
Msa 3-BH 1st LO Capacitor
Selection
LSa
Figure 29. 1st LO Schematic
--------------,
I
I VcapCtrl
Flret Local 08clllator Capacitor Selection for 25
Channel U.S. Operation
There Is a very large frequency difference between the
minimum and maximum channel frequencies in the proposed
25 Channel U.S. standard. The sensitivity of the 1st LO is not
large enough to accommodate this large frequency variation.
Fixed capacitors can be connected across the 1st LO tank
circuit to change the 1st LO sensitivity. Internal switches and
capacitors are provided to enable microprocessor control
over Internal fixed capaCitor values. Figure 29 shows the
Figure 30. 1st LO CapaCitor Select for U.S. 25 Channela
II
1st LO
Cap.
BIU
1st LO
Cap.
Bit 1
0
0
0
0
0
0
0
1
1st LO
Cap.
Selact
U.S.
U.S.
Baae
Channels
Handaet
Channela
Internal
Cap. Value
(Excluding
Varactor)
0
0
16-25
0
0
-
1
1
0
1et LO
Cap
Bit 0
Extarnal
CapaCitor
Value
External
Inductor
Valua
-
0.92 pF
10 - 6.4 pF
27pF
0.47 ~H
16-25
0.92 pF
10-6.4pF
33pF
0.47~H
1-6
-
2.61 pF
10-6.4pF
27pF
0.47~H
2
7-15
-
1.82 pF
10-6.4 pF
27pF
0.47 ~H
-
1-6
8.69 pF
10-6.4 pF
33pF
0.47~H
7-15
7.19pF
10-6.4pF
33pF
0.47~H
0
1
1
3
1
0
0
4
8-150
Varactor
Value over
0.5 to 2.2 V
Ranga
MOTOROLA ANALOG Ie DEVICE DATA
MC13109
Figure 31. Test Mode Description
Counter Under Test or
Test Mode Option
"TxVCO"
Input Signal
TM#
TM3
TM2
TM1
TMO
0
0
0
0
0
Normal Operation
"Clk Out" Output Expected
1
0
0
0
1
Rx Counter, upper 6
Ot02.2V
Input Frequency/64
2
0
0
1
0
Rx Counter, lower 8
Ot02.2V
See Note Below
3
0
0
1
1
Rx Prescaler
Ot02.2V
Input Frequency/4
4
0
1
0
0
Tx Counter, upper 6
o to 2.2 V
Input Frequency/64
5
0
1
0
1
Tx Counter, lower 8
6
0
1
1
0
Tx Prescaler
7
0
1
1
1
Reference Counter
Ot02.2 V
Input Frequency/Reference Counter Value
8
1
0
0
0
Divide by 4, 25
Ot02.2V
Input Frequency/100
9
1
0
0
1
10
1
0
1
0
=10 Option
AGC Gain =25 Option
-
>200mVpp
Oto 2.2V
See Note Below
Input Frequency/4
>200mVpp
AGC Gain
N/A
-
N/A
-
NOTE: To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value 01 the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6 bits 01 the divisor). II Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value Is Divisor (3;2) (btts 2 and 3
01 the divisor). II Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
Test Modes
Test Mode Control latch bits enable independent testing
of internal counters and set AGC Gain Options. In test
mode, the "Tx VCO" input pin is multiplexed to the input of
the counter under test and the output of the counter under
test is multiplexed to the "Clk Out" output pin so that each
counter can be individually tested. Make sure test mode bits
are set to "0" for normal operation. Test mode operation is
described in Figure 31. During normal operation and when
testing the Tx Prescaler, the "Tx VCO" input can be a
minimum of 200 mVpp at 80 MHz and should be ac coupled.
For other test modes, input signals should be standard logic
levels of 0 to 2.2 V and a maximum frequency of 16 MHz.
Power-Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The MC13109 is initially placed in
the Rx mode with all mutes active and nothing disabled. The
reference counter is set to generate a 5.0 kHz reference
frequency from a 10.24 MHz crystal. The MPU clock output
divider is set to 10 to give the minimum clock output frequency.
The Tx and Rx latch registers are set for USA Channel
Frequency #21. Figure 32 shows the initial power-up states
for all latch registers.
Figure 32. Latch Register Power-Up Defaults
MSB
LSB
Register
Count
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Tx
9966
-
-
1
0
0
1
1
0
1
1
1
0
1
1
1
0
Rx
7215
-
-
0
1
1
1
0
0
0
0
1
0
1
1
1
1
Ref
2048
-
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Mode
N/A
-
0
0
0
0
1
1
0
1
1
1
0
1
1
1
1
Gain
N/A
-
-
-
-
-
-
1
0
1
0
0
-
-
-
-
-
-
-
N/A
-
-
TM
-
-
0
0
0
0
0
0
0
MOTOROLA ANALOG IC DEVICE DATA
8-151
II
:
MC13109
Figure 34. ICC versus Vcc at Receive Mode
Figure 33. ICC versus VCC at Active Mode
8.0r---r---r---,...---,...-----,
~
i
~
6.0
B
4.0
~
~
;
6.0
~
2.0
iiil
It
:::.
tJ)
8.0r---r---;----.,----.,------,
2.0
0
2.5
3.0
3.5
4.0
Vee, SUPPLY VOLTAGE (V)
4.5
4.0
0
2.5
5.0
Figure 35. ICC versus VCC at Standby Mode
~
0:8
a:
a:
0.6
iiil
0.4
a
II
~
0.2
~
V
o2.5
3.0
V"
L ~
3.5
4.0
Vee, SUPPLY VOLTAGE (V)
60
./
----
4.5
o
2.5
5.0
~
~
"
-50
-120
J
AMRr
"-
I
/
-100
/'
-40
-20
o
Recovere AuY
~ 0.15
~
0.10
0.05
N
RFin, RF INPUT (dBm)
8-152
V
5.0
3.0
~ 0.20
N+D
4.5
R22=12kO
:ii !
\..
5.0
-----
3.5
4.0
Vee, SUPPLY VOLTAGE (V)
~
"""""'1\
-30
-40
~
3.0
~
0.25
AFoul
B -20
"........--
0.30
o
-10
4.5
Figure 38. Recovered Audlo/THD versus tDEV
Figure 37. RFln versus AFout, N+D, N, AMR
10
iB'
~
3.5
4.0
Vee, SUPPLY VOLTAGE (II)
Figure 36. ICC versus VCC at Inactive Mode
1.0
!z
w
3.0
o
o
""
V
2.0
/
/
./
/"
i
/
2.5
2.0
l
1.5~
1.0
/THD
4.0
6.0
fDEV, DEVIATION, (kHz)
8.0
MOTOROLA ANALOG IC DEVICE DATA
MC13109
Figure 40. First Mixer Third Order
Intercept Performance
Figure 39. RSSI Output versus RFin
1.4
/
1.2
~
1.0
/'
f-
::;)
a.
f-
O.B
::;)
0
c;;
0.6
lQ
0.4
0.2
~
o
-120
-100
/
/
e-+----~
Rx
Out
Carrier -+-+-_ _-<
Detect
Tx In
>-+----+1
Tx Out .....r-j.----=====~
Tx VCO -+-+------1
-=========-__________-...::====-__
Low
1----I-f---i~Baltery
L ___
...J
Indicator
This device contains 8,262 active transistors.
8-154
MOTOROLA ANALOG IC DEVICE DATA
VCC
Figure 1. Production Test Circuit
!l:
a
:0
o
RFln)
~
~
22.1 k
1)
)0
0.01
49.9
z
)0
g
(')
c
m
:so
m
c
~
)0
I-
(DAln
i:
o
....
....
....
o
Co)
VCCA ~.
Il,I'n
VCCA~'
22.1 k
Data
Out
""'loll
•
"
• BDl
Out
1.Sk
!
81
NOTE:
........._.....
'"'_.""
' -_ _ _ _ _......_ _•• Carrier
Detect Out
MPU Clock Output
,
MC13110
MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
VCC
-0.5 to +5.5
Vdc
TJ
-65 to +150
DC
Power Supply Voltage
Junction Temperature
NOTES: 1. Devices should not be operated at these limits. The "Recommended Operating Condnions"
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
VCC
2.7
3.6
5.0
Vdc
Operating Ambient Temperature
TA
-40
-
85
'c
Input Voltage Low (Data, Clk, EN)
V,L
-
-
0.3
V
Input Voltage High (Data, Clk, EN)
VIH
2.5
-
-
Characteristic
Supply Voltage
NOTE:
V
rnA
Output Current (Rx PO, Tx PO)
High
Low
-
IOH
IOL
0.7
-
-0.7
-
All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25'C, unless otherwise specHied;
Test Circuit Figure 1.)
Symbol
Characteristic
Static Current
Active Mode (2.7 V)
Active Mode
Receive Mode
Standby Mode
Inactive Mode
ACT ICC
ACT ICC
RxlCC
STDICC
INACTICC
Min
Typ
Max
-
8.1
8.6
4.3
270
35
12
5.3
500
80
-
Unit
-
rnA
rnA
rnA
!1A
!1A
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25 DC, Active or Rx Mode, unless otherwise specified;
rest CircuH Figure 1.)
Characteristic
Condition
PLL VOLTAGE REGULATOR
Regulated Output Level
IL=OmA
-
PLL Vref
Vo
2.4
2.5
2.6
V
Line Regulation
IL=OmA,
VCC = 3.6 to 5.5 V
VCC Audio
PLLVref
VReg
Line
-
'-0.6
20
mV
Load Regulation
VCC = 3.6V,IL= 1.0mA
Vce Audio
PLL Vref
VReg
Load
-
-1.1
20
mV
-
f2ext
-
12
-
MHz
L021n
L02°ut
f2ext
-
12
-
MHz
TxVCO
ftxmax
-
80
-
MHz
PLL LOOP CHARACTERISTICS
2nd LO Frequency
(No Crystal)
-
L021n
2nd LO Frequency
(With Crystal)
-
-
Tx VCO (Input Frequency)
~156
Yin = 200 mVpp
-
MOTOROLA ANALOG ,IC DEVICE DATA
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
PLL PHASE DETECTOR
Output Voltage Low
IIL=0.7 rnA
-
RxPD
TxPD
VOL
-
-
(PLL
Vref) *.2
V
Output Voltage High
IIH =-0.7 rnA
-
RxPD
TxPD
VOL
(PLL
Vref) *.8
-
-
V
3-State Leakage Current
V=1.2V
-
RxPD
TxPD
IOZ
-50
-
50
nA
-
-
RxPD
TxPD
Cout
-
8.0
-
pF
CLoad= 50pF
-
RxPD
TxPD
ClkOut
t r, tl
-
250
-
ns
Output Capacitance
Output Rise and Fall Time
MICROPROCESSOR SERIAL INTERFACE
Input Current Low
Vin=0.3V
Standby Mode
-
Data,
Clk, EN
IlL
-5.0
0.3
-
~
Input Current High
Vin=3.3V
Standby Mode
-
Data,
Clk, EN
IIH
-
1.5
5.0
~
Hysteresis Voltage
-
-
Data,
Clk, EN
Vhys
-
1.0
-
V
Maximum Clock Frequency
-
Data,
EN, Clk
-
-
-
2.0
-
MHz
Input Capacitance
-
Data,
Clk, EN
-
Cin
-
8.0
-
pF
EN to Clk Setup Time
-
-
EN,Clk
tsuEC
-
200
-
ns
tsuDC
-
100
-
ns
ttl
90
-
ns
Data to Clk Setup Time
-
-
Data, Clk
Hold Time
-
-
Data, Clk
Recovery Time
-
-
EN,Clk
trec
-
Input Pulse Width
-
-
EN,Clk
tw
-
100
Input Rise and Fall Time
-
-
Data,
Clk,EN
t r, tl
-
9.0
-
~
-
-
lpuMPU
-
100
-
~
Mixl1nl/2
DetOut
VSIN
-
2.8
-98
-
-
~Vrms
Mixl1nl/2
DetOut
-
1.0
-107
-
~Vrms
MPU Interface Power-Up
Delay
90% 01 PLL Vrel to Data,
Clk, EN
90
ns
ns
FM RECEIVER (IRF = 46 77 MHz [USA Ch 21] fdev = +3
- .0 kHz Imod = 10kHz)
Sensitivity (Input lor 12 dB
SINAD)
50 n Termination
Single-Ended, Matched Input
VSIN
-
dBm
dBm
Differential, Matched Input
Mixl Inl/2
DetOut
VSIN
-
.56
-112
-
IlVrms
dBm
1st Mixer Voltage
Conversion Gain
Yin = 1.0 mVrms, with CFl
Filter as Load
Mixl1nl/2
Mixl0ut
MXgainl
-
12
-
dB
2nd Mixer Voltage
Conversion Gain
Yin = 3.0 mVrms, with CF2
Filter as Load
Mix21n
Mix20ut
MXgain2
-
20
-
dB
1st and 2nd Mixer Voltage
Gain Total
Yin = 1.0 mVrms, with CFl
andCF2 Load
Mixlln1/2
Mix20ut
MXgainT
24
28
-
dB
1st Mixer Input Impedance
Single-Ended Input
-
Mixl Inll2
Rpl
CPl
-
-
875
2.7
-
n
pF
Zin2
-
3.0
-
kn
2nd Mixer Input Impedance
lin = 10.7 MHz
MOTOROLA ANALOG IC DEVICE DATA
-
Mix21n
8-157
II
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
FM RECEIVER (fRF = 46.77 MHz [USA Ch 211, fdev = ±3.0 kHz, fmod = 1.0 kHz)
1st Mixer Output
Impedancet
-
-
Mixl0ut
Zoutl
-
330
-
Q
2nd Mixer Output
Impedance
-
-
Mix20ut
Zout2
-
1.5
-
kQ
Lim In
DetOut
IF Sens
-
71
100
~Vrms
IF -3.0 dB Limiting
Sensitivity
fin = 455 kHz
Total Harmonic Distortion
With RC = 15 kll.0 nF Filter
at DetOut
Mixllnl
DetOut
THD
-
1.3
2.0
%
Recovered Audio
Vin = 3.16 mVrms with
RC = 15 kll000 pF Filter
at DetOut
Mixllnl
DetOut
AFO
80
105
150
mVrms
Lim In
DetOut
BW
-
20
-
kHz
Signal to Noise Ratio
Vin = 3.16 mVrms,
RC = 15 kll000 pF
Mixllnl
DetOut
SN
-
49
-
dB
AM Rejection Ratio
Vin = 3.16 mVrms,
30% AM, @ 1.0 kHz,
RC = 15 kll000 pF
Mixllnl
DetOut
AMR
30
47
-
dB
Mixl Inl/2
Mixl0ut
Vo
1.0dB
Mixl
-
15
-
mVrms
-
Demodulator Bandwidth
-
1st Mixer, 1.0 dB Voltage
Compression (Input Pin
Referred)
2nd Mixer, 1.0 dB Vol~ge .
Compression (Input Pin
Referred)
50Q Input
Mix21n
Mix20ut
Vo
1.0dB
Mix2
-
14
-
mVrms
1st Mixer 3rd Order
Intercept (Input Pin
Referred)
Vin = 3.98 mVrms
Mixllnl
Mixl0ut
TOlmixl
-
56
-
mVrms
2nd Mixer 3rd Order
Intercept (Input Pin
Referred)
Vin = 3.98 mVrms, 50 Q Input
Mix21n
Mix20ut
TOlmix2
-
53
-
mVrms
-
-
DetOut
Zo
-
870
-
Q
-
Mixlln
RSSI
RSSI
-
80
-
dB
Mixlln
CD Out
VT
-
33
-
~lirms
Detector Output Impedance
RSSIICARRIER DETECT (RL = 100 kQ)
RSSI Output Current
Dynamio Range
Carrier Sense Threshold
CD Threshold Adjust =
(10100)
-
Mixlln
CD Out
Hys
-
3.6
7.0
dB
Output High Voltage
Vin = 0 Vrms, CD = (10100)
Mixlln
CD Out
VOH
VCC0.1
3.6
-
V
Output Low Voltage
Vin = -80 dBV, CD= (10100)
Mixl"1
CD Out
VOL
-
0.02
0.4
V
Hysteresis
8-158
MOTOROLA ANALOG Ie DEVICE DATA
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Condition
Characteristic
RSSUCARRIER DETECT (RL = 100 kn)
Carrier Sense Threshold
Adjustment Range
Carrier Sense Threshold Number of Steps
-
-
VTlow
range
-
-
VThi
range
Programmable through MPU
Interface
-
-
VTn
Programmable through MPU
Interface
-20
-
-
-
-
11
-
32
-
-
dB
DATA AMP COMPARATOR
Hysteresis
-
OAln
OAOut
Hys
30
40
50
mV
Threshold Voltage
-
OAln
OAOut
VT
2.7
VCC0.7
-
V
Input Impedance
-
-
OAln
ZI
-
11
-
kQ
-
OAOut
Zo
-
100
-
kQ
Output High Voltage
Vin = VCC -1.0 V,
IOH=OmA
OAln
OAOut
VOH
VCC0.1
3.6
-
V
Output Low Voltage
Vin = VCC - 0.4 V,
IOL=OmA
OAln
OAOut
VOL
-
0.04
0.4
V
-
Output Impedance
EXPANDORJR x MUTE (fin = 1.0 kHz)
Absolute Gain
Vin=-20dBV
Eln
EOut
G
-3.0
0
3.0
dB
Gain Tracking
Vin =-30 dBV
Vin=-40dBV
E In
EOut
Gt
-21
-42
-20
-40
-19
-38
dB
Total Harmonic
~istortion
E In
EOut
THO
-
0.5
1.0
%
-
RxAudio In
-
-
-
-11.5
dBV
Increase input voltage until
output voltage THO = 5.0%,
then measure output voltage.
RL = 7.5 kl1.0 ~F
Eln
EOut
VOmax
-
0
-
-
RxAudio In
E In
-
Zin
-
600
7.5
-
kn
Vin =-20 dBV
Maximum Input Voltage
Maximum Output Voltage
Input Impedance
dBV
3.0
-
ms
AltackTime
Ecap = 0.5 ~F, Rlilt = 40 k
(See Appendix B)
Eln
EOut
ta
-
Release Time
Ecap = 0.5 ~F, Rlilt = 40 k
(See Appendix B)
E In
EOut
tr
-
13.5
-
ms
Compressor to Expandor
Crosstalk
Vin=-10dBV,
VIE In) = AC Gnd
Cln
EOut
CT
-
-90
-70
dB
Rx Data Muting (ll. Gain)
Vin = -20 dBV,
Rx Gain Adj = (01111)
RxAudio In
EOut
Me
-
--83
-60
dB
SPEAKER AMP/SP MUTE
Maximum Output Swing
Vin=OdBV,
RL=130Q
SA In
SA Out
VOmax
0.8
0.9
-
Vpp
Speaker Amp Muting
Vin=-20dBV
SA In
SA Out
Msp
-
-90
--80
dB
COMPRESSORlTx MUTE (lin = 1.0 kHz, Scrambler Bypass Mode, Tx Gain Adj = (01111), fin = 1.0 kHz)
Absolute Gain
Vin=-10dBV
Tx In
TxOut
G
-4.0
0
4.0
dB
Gain Tracking
Vin=-30dBV
Vin =-40 dBV
Txln
Tx Out
Gt
-11
-9.0
-13
dB
-17
-10
-20
Vin = -10 dBV
Txln
-
0.6
1.1
%
Total Harmonic Distortion
MOTOROLA ANALOG IC DEVICE DATA
TxOut
THO
8-159
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characterlatlc
Condition
Symbol
COMPRESSORITx MUTE (fin = 1.0 kHz , Scrambler Bypass Mode, Tx Gain Ad] = (01111) fin = 1.0 kHz)
Increase Input voltage until
Maximum Output Voltage
Cln
Tx Out
VOmax
output voltage THO = 5.0%,
then measure output voltage.
RL = 7.5 kll.0 IlF
-
Input Impedance
-
dBV
10
-
kCl
-
ms·
Ir
-
13.5
-
ms
Tx Out
CT
-
-60
-40
dB
Tx Out
Mc
-
-90
-60
dB
Tx Out
ALCout
-15
-13
-11
-10
-8.0
-6.0
dBV
Tx Out
Vllm
-10
-7.0
-
Tx Out
Ccap = 0.5 IlF, Rfllt = 40 k
(See Appendix B)
Cln
Tx Out
ta
Release TIme
Ccap = 0.5 IlF, Rfllt = 40 k
(See Appendix B)
Cln
Tx Out
Expandor to Compressor
Crosstalk
Vln = -20 dBV, Speaker Amp
No Load, V(C In) = AC Gnd
E In
Tx Muting
Vin-10 dBV
Tx In
ALC OUlput Level
Vin=-10dBV
Vln = -2.5 dBV
Limiter and Mutes disabled
Tx In
Limiter' Output Level
Yin = -2.5 dBV,
ALC disabled
Tx In
Zln
-
-5.0
3.0
Cln
Attack TIme
-
dBV
Rx ANDTx SCRAMBLER (2nd LO = 10.24 MHz, Tx Gain Ad] = (01111), Rx Gain Ad] = (01111), Volume Control =(0 dB Default Levels),
SCF Clock Divider = 31. Total is divide by 62 for SCF clock frequency of 165.16 kHz)
RxAudio In
ScrOut
Rxfch
-
3.65
-
kHz
Txln
Tx Out
Txfch
-
3.879
-
kHz
RxAudlo In
Txln
EOut
Tx Out
AV
-4.0
-4.0
0
0
4.0
4.0
dB
Cln
EOut
Ripple
-
2.0
-
dB
Rx Audio In
Cln
EOut
Tx Out
fmod
4.119
4.129
4.139
kHz
Rx + Tx Path -1.0 IlF from
Tx Out to Rx AudiO In,
fin = 1.0 kHz
Cln
EOut
GO
-
1.0
-
ms
fin = low corner frequency to
high corner frequency
Cln
EOut
GO
-
4.0
-
Carrier Breakthrough
Rx + Tx Path -1.0 IlFfrom
Tx Out to Rx Audio In
Cln
EOut
CBT
-
-60
-
dB
Baseband Breakthrough
Rx + Tx Path -1.0 IlFfrom
Tx Out to Rx Audio In,
fin = 1.0 kHz,
fmeas = 3.192 kHz
Cln
EOut
BBT
-
-50
-
dB
Rx High Frequency Corner
(Note 1)
Rx Path, f = 479 Hz,
V Rx Audio In = -20 dBV
Tx High Frequency Corner
(Note 1)
Tx Path, f = 250 Hz,
V Tx In = -10 dBV, Mic Amp
= Unity Gain
Absolute Gain
Rx: Yin = -20 dBV
Tx: Vln =-10 dBV,
Limiter disabled
Pass Band Ripple
Rx + Tx Path -1.0 IlFfrom
Tx Out to Rx Audio In,
fin = low corner frequency to
high corner frequency
Scrambler Modulation
Frequency
Rx: 100 mV (-20 dBV)
Tx: 316 mV (-10 dBY)
Group Delay
NOTE: 1. The filter specification is based on a 10.24 MHz 2nd LO, and a swltched-capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
andlor SC filter counter divider ratios are used, the filter comer frequency will be proportional to the resuHing SC filter clock frequency.
8-160
MOTOROLA ANALOG IC DEVICE DATA
MC13110
ELECTRICAL CHARACTERISTICS (continued) (Vec = 3.6 V, VB = 1.5 V. TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
MIC AMP (fin = 1.0 kHz. External resistors set to gain of 1)
Open Loop Gain
-
Gain Bandwidth
-
Txln
Amp Out
AVOL
-
100,000
GBW
100
-
kHz
VN
Txln
Amp Out
RL= 10 kn
Tx In
Amp Out
VOmax
-
2.8
-
Vpp
Average Threshold
Voltage Before Electronic
Adjustment
Vee = 3.6 V. Vref_Adj =
(0111). Take average of rising
and falling threshold
Reh
Ref2
BD10ut
BD20ut
VTi
1.36
1.5
1.64
V
Average Threshold
Voltage After Electronic
Adjustment
Vec = 3.6 V, Vref_Adj =
(adjusted value). Take
average of rising and falling
threshold
Refl
Ref2
BD10ut
BD20ut
VTf
1.475
1.5
1.525
V
-
Refl
Ref2
BD10ut
BD2°ut
Hys
-
4.0
-
mV
-
Refl
Ref2
lin
-50
-
50
nA
Maximum Output Swing
LOW BATTERY DETECT
Hysteresis
Input Current
Vin = 1.0 to 2.0 V
Output High Voltage
Vin=2.0V,
RL = 3.9 kn to Vee
Refl
Ref2
BD10ut
BD20ut
VOH
Vee0.1
3.6
-
V
Output Low Voltage
Vin= 1.0V,
RL = 3.9 kn to Vee
Refl
Ref2
BD10ut
BD2°ut
VOL
-
0.1
0.4
V
II
MOTOROLA ANALOG IC DEVICE DATA
8-161
MC13110
PIN FUNCTION DESCRIPTION
Pin
1
2
Symbol
Type
Description
L021n
L020ut
-
These pins form the PLL reference oscillator when connected to an external parallel-resonant
crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (L02) for
the AF receiver. "L02 In" may also serve as an Input for an externally generated reference signal
which is typically ac-coupljld.
3
Vag
-
4
Ax PO
Output
Three state voltage output of the Ax Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector Input signals. During lock,
very narrow pulses with a frequency equal to the reference frequency are present. This pin drives
the external Ax PLL loop filter. It Is Important to minimize the line length and parasitic capacitance
of this pin.
5
PLL Vref
-
PLL voltage regulator output pin. An internal voltage regulator provides a stable power supply
voltage for the Ax. and Tx PLL's and can also be used as a regulated supply voltage for other IC's.
6
TxPD
Output
Three state voltage output of the Tx Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector input signals. During lock,
very narrow pulses with a frequency equal to the reference frequency are present. This pin drives
the external Tx PLL loop filter. It Is Important to minimize the line length and parasitic capacitance
of this pin.
7
Gnd PLL
Gnd
Ground pin for PLL section of IC.
8
Tx VCO
Input
Transmit divide counter input which is driven by an ac-coupled externallransmit loop VCO. The
minimum signal level is 200 mVpp @ 60.0 MHz. This pin also functions as the test mode Input for
the counter tests.
9
10
11
Data
Input
Microprocessor serial interface input pins for programming various counters and control functions.
12
ClkOut
Output
Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator and a
programmable divider. It can be used to drive a microprocessor and thereby reduce the number of
crystals required In the system design. The driver has an internal resistor in series with the output
which can be combined with an external capacitor to form a low pass filter to reduce radiated noise
on the PCB. This output also functions as the output for the counter test modes.
13
CD Out
I/O
14
BD10ut
Output
Low battery detect output #1 (open collector with external pull-up resistor).
Data amplifier output (open collector with internal 100 kQ pull-up resistor).
Intemal reference voltage for switched capacitor filter section.
EN
Clk
Dual function pin; 1) Carrier detect output (open collector with external 100 kn pull-up resistor.
2) Hardware interrupt input which can be used to "wake-up" from Inactive Mode.
15
DAOut
Output
16
BD20ut
Output
Low battery detect output #2 (open collector with external pull-up reSistor).
17
Tx Out
Output
Tx path audio output.
18
CCap
-
19
C In
Input
20
Amp Out
Output
21
Txln
Input
Tx path input to microphone amplifier (Mic Amp) (ac-coupled).
22
DAln
Input
Data amplifier input (ac-coupled).
23
VCC Audio
Supply
24
Ax Audio In
Input
25
DetOut
Output
26
ASSI
Output
27
28
a Coil
-
Lim Out
29
VCCAF
Supply
30
31
LimC2
Lim Cl
-
IF amplifierilimiter capacitor pins.
32
Lim In
Input
Signal input for IF amplifierlJimiter.
8-162
Compressor rectifier filter capacitor pin. Pull pin high through a capacitor.
Compressor input (ac-coupled).
Microphone amplifier output.
VCC supply for audio section.
Ax audio Input (ac-coupled).
Audio output from FM detector.
Aeceive Signal Strength Indicator filter capacitor.
A quad coli or ceramic discriminator connected to these pins as part of the FM demodulator circuit.
VCC supply for AF receiver section.
~OTOROLA
ANALOG IC DEVICE DATA
MC13110
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
Type
33
SGNDRF
Gnd
Ground pin for RF section of the IC.
Second mixer input.
34
Mix21n
Input
35
Mix20ut
Output
36
GndRF
Gnd
37
Mix10ut
Output
38
Mix11n2
input
39
Mix11n1
Input
40
41
L011n
L010ut
-
42
VcapCtrl
-
43
GndAudio
Gnd
44
SA Out
Output
45
SAln
Input
46
EOut
Output
Description
Second mixer output.
Ground pin for RF section of the IC.
First mixer output.
Negative phase first mixer input.
Positive phase first mixer input.
Tank Elements for 1st LO Multivibrator Oscillator are connected to these pins.
1st LO Varactor Control Pin.
Ground for audio section of the IC.
Speaker amplifier output.
Speaker amplifier input (ac-<:oupled).
Expandor output.
47
Ecap
-
48
E In
Input
49
ScrOut
Output
50
Ref2
-
51
Ref1
-
Reference voltage input for Low Battery Detect #1.
52
VB
-
Internal half supply analog ground reference.
Expandor rectifier filter capacitor pin. Pull pin high through a capacitor.
Expandor Input.
Rx Scrambler Output.
Reference voltage input for Low Battery Detect #2.
II
MOTOROLA ANALOG IC DEVICE DATA
8-163
MC13110
FM Receiver
The FM receiver can be used with either a quad coil or a
ceramic resonator. The FM receiver and 1st LO have been
designed to work for all country channels, including 25
channel U.S., without the need for any external switching
circuitry (see Figure 29).
.
RSSI/Carrler Detect
Connect 0.01 ~F to Gnd from "RSSI" output pin to form the
carrier detect filter. "CD Out" is an open collector output
which requires an external 100 kQ pull-up resistor to VCC.
The carrier detect threshold is programmable through the
MPU interface.
Data Amp Comparator
The data amp comparator is an inverting hysteresis
comparator. Its open collector output has an Internal 100 kO
pull-up resistor. A band pass filter is connected between the
"Det Out" pin and the "DA In" pin with component values as
shown in Figure 1 (Test Circuit). The "DA In" Input signal is
ac-coupled.
Figure 2. Data Amp Operation
I
t
Expandor/ Compressor
In Appendix B, the EIAICCITT recommendations for
measurement of the attack and decay times are defined. The
curves in Figures 3 and 4 show the typical expandor and
compressor output versus input responses.
Figure 3. Expandor Typical Response
10
o
-10
:> -20
~
'S -30
o
w -40
-50
-60
/
-40
/
/'
-30
/'
/
/' r'-EOut=O~BV
-20
E In (deV)
8-164
Typical at THO = 5.0%
-10
o
-10
V
/
V
V
V
/
Kt
Tx Ou = -5.0 deV
Typical alTHO = 5.0%
-40
-60
-50
-40
-30
-20
-10
0
10
20
Tx In (dBV)
Rx Audio Path (LPF/Rx Gain Adjust!
Rx Mute!ExpandorNolume Control)
The Rx Audio signal path goes from "Rx Audio In" (Pin 24)
to "E Out" (Pin 46). The "Rx Audio In" input signal is ac
coupled. AC couple between "Scr Out" and "E In" (see
Figure 3).
Speaker AmplSP Mute
The Speaker Amp is an inverting rail-to-rail operational
amplifier. The noninvertlng input Is connected to the internal VB
reference. Extemal resistors and capacitors are used to set the
gain and frequency response. The "SA In" Input is ac coupled.
Oala
Signal H---l_-+l-~_-+l-~_-+_
OalaAmp
Output
Figure 4. Compressor Typical Response
o
10
MlcAmp
The Mic Amp is an inverting rail-te-rail operational amplifier
with noninverting input terminal connected to internal VB
reference. External resistors and capacitors are set to the gain
and frequency response. The ''Tx In" input is ac coupled.
Tx Audio Path (Compressor/ALCITx Mute!
Llmlter/LPFITx Gain Adjust)
The Tx Audio signal path goes from "c In" (Pin 19) to "Tx
Out" (Pin 17). The "c In" input signal is ac coupled. The ALC
(Automatic Level Control) provides a "soft" limit to the output
signal swing as the input voltage increases slowly (i.e., a sine
wave is maintained). The Limiter circuit limits rapidly
changing signal levels by clipping the signal peaks. The ALC
and/or Limiter can be disabled through the MPU serial
interface (see Figure 4).
T x and Rx Scrambler
The Tx and Rx signal paths each contain a frequency
inversion scrambler in the MC13110. Each scrambler
contains a pre-mixer low pass switched capacitor filter
(SCF), a double balanced mixer and a post-mixer low pass
switched capacitor filter. The scrambler function can be
defeated by setting the Tx or Rx Scrambler Bypass bits in the
control register to "1" through the MPU interface. In this
mode, the mixer and the post-mixer LPF are bypassed and
MOTOROLA ANALOG IC DEVICE DATA
MC13110
only the pre-mixer LPF remains in the signal path. The SCF
corner frequencies are proportional to the SCF clock. The
SCF Clock Divider is programmable through the MPU
interface, (SCF Clock) = F(2nd LO)/(SCF Divider Value*2).
The scrambler modulation frequency is (SCF Clock)/40. Four
scrambler modulation frequencies may be selected (see
Figures 28 and 29).
PLL Voltage Regulator
The "PLL Vre(' pin is the internal supply voltage for the Ax
and Tx PLL's. It is regulated to a nominal 2.5 V. The "VCC
Audio" pin is the supply voltage for the internal voltage
regulator. Two capacitors with 10 IiF and 0.1 IiF values must
be connected to the "PLL Vre( pin to filter and stabilize this
regulated voltage. The "PLL Vret" pin may be used to power
other IC's as long as the total external load current does not
exceed 1.0 mAo The tolerance of the regulated voltage is
initially ±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the "PLL Vre( pin is internally connected to the
"V CC Audio" pin (i.e., the power supply voltage is maintained
but is now unregulated).
Low Battery Detect
Two external precision resistor dividers are used to set
independent thresholds for two battery detect hysteresis
comparators. The voltages on "Aef1" and "Aef2" are
compared to an internally generated 1.5 V reference voltage.
The tolerance of the internal reference voltage is initially
±6.0%. The Low Battery Detect threshold tolerance can be
improved by adjusting a trim-pot in the external resistor
divider. Alternately, the tolerance of the internal reference
voltage can be improved to ±1.5% through MPU serial
interface programming. The internal reference can be
measured directly at the "VB" pin. During final test of the
telephone, the VB internal reference voltage is measured.
Then, the internal reference voltage value is adjusted
electronically through the MPU serial interface to achieve the
desired accuracy level. The voltage reference register value
should be stored in AOM during final test so that it can be
reloaded each time the MC13110 IC is powered up. Low
Battery Detect outputs are open collector.
Power Supply Voltage
This circuit is used in a cordless telephone handset and
base unit. The handset is battery powered and can operate
on three NiCad cells or on 5.0 V supply.
PLL Frequency Synthesizer General Description
Figure 5 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL). This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), Spain, Australia, Korea, New
Zealand, U. K., Netherlands, France, and China.
The 2nd local oscillator and reference divider provide the
reference frequency for the receive (Ax) and transmit (Tx)
PLL loops. The programmed divider value for the reference
divider is selected based on the crystal frequency and the
desired Ax and Tx reference frequency values. Additional
divide by 25 and divide by 4 blocks are provided to allow for
generation of the 1.0 kHz and 6.25 kHz reference
frequencies required for the U. K. The 14-bit Tx counter is
programmed for the desired transmit channel frequency. The
14-bit Ax counter is programmed for the desired first local
oscillator frequency. All counters power up in the proper
default state for USA channel #21 (channel #6 for FCC 10
channel band) and for a 10.24 MHz reference frequency
crystal. Internal fixed capacitors can be connected to the tank
circuit of the 1st LO through microprocessor control to extend
the sensitivity of the 1st LO for U.S. 25 channel operation.
PLL I/O Pin Specifications
The 2nd LO, Ax and Tx PLL's, and MPU serial interface are
powered by the internal voltage regulator at the "PLL Vre('
pin. The "PLL Vret" pin is the output of a voltage regulator
which is powered from the "VCC Audio" power supply pin and
is regulated by an internal bandgap voltage reference.
Therefore, the maximum input and output levels for most PLL
I/O pins (L02 In, L02 Out, Ax PD, Tx PD, Tx VCO) is the
regulated voltage at the "PLL Vret" pin. The ESD protection
diodes on these pins are also connected to "PLL Vret".
Internal level shift buffers are provided for the pins (Data, Clk,
EN, Clk Out) which connect directly to the microprocessor.
The maximum input and output levels for these pins is VCC.
Figure 6 shows a simplified schematic of the I/O pins.
Figure 5. Dual PLL Simplified Block Diagram
Tx VCO
6
12-b
o
+ 25
~ 40
Programmable
Reference ' .
Counter
+1.0 Hi-+--o '---''''----I
1
L020ut
2
~
______________________________________
MOTOROLA ANALOG IC DEVICE DATA
~41
8-165
8
MC13110
Figure 6; PLL 110 Pin Simplified Schematics
PLL Vrel
(2.5 V)
VCC Audio
(2.7 to 5.5 V)
PLL Vrel
(2.5 V)
Vee Audio
(2.7 to 5.5 V)
~+,"~~~~ru
-=-
-=- -=-
L~ In, L02 Out,
2.0 JlA
-=- .
-=- -=-
Data, Clk and EN Pins
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure '9 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when "EN" is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the "EN" high state. The convention in
these figures is that latch bits to the left are loaded into the
~hift register first.
.
ClkOutPin
Rx PO, Tx PO and
Tx VCO Pins
Figure 9. Microprocessor Interface Programming
Mode Diagrams
Microprocessor Serial Interface
The "Data", "elk", and "EN" pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counters, the switched
capacitor filter clock counter, and various control functions.
The "Data" and "elk" pins are used to load data into the shift
register. Figure 7 shows the timing required on the "Data" and
"elk" pins. Data is clocked into the shift register on positive
clock transitions.
Data--{MSB
ENJ
, 6-Bit Address
Address Register Programming Mode
rv
Data--{ MSB
16-BitData
LSB'r.......- - - - - - - - - L a t - C h - . J
Latch
EN _________________________
Figure 7. Data and Clock Timing Requirement
tl
II
Data,
elk, EN
~I
'--
Data Register Programming Mode
The MPU serial interface is·fully operational within 100 j.IS
after the power supply has reached its minimum level during
power-up (see Figure 10). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx , and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Data
Figure 10. Microprocessor Serial Interface
Power-Up Delay
Clk
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the "EN" pin.
This is done in two steps. First, an 8-bit address is loaded
into the shift register and latched into the 8-bit address latch
register. Then, up to 16-bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 5 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
Figure 8. E!1able Timing Requirement
R
50%
EN
8-166
:-A
______2_.7_V_-'~_PU
_ __
Clk, EN
Data Registers
Figure 11 shows shows the data latch registers and
addresses which are used to select each of these registers.
Latch bits to the left (MSB) are loaded into the shift register
first. The LSB bit must always be the last bit loaded into the
shift register. Bits preceeding the register must be "O's" as
shown in Figure 11.
trec
50%
Previous Data Latched
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Figure 11. Microprocessor Interface Data Latch Registers
~~M_S_B
Latch Address
l~
)
________________________T_x_Cou
__n_re_r____________________________LSB
--J
1. (00000001)
Tx Counter Latch
~~_M_S_B
l_~
_____________________ __R_x_c_o_un_re_r____________________________LSB)
--J
2. (00000010)
Rx Counter Latch
MSB
12-b Reference Counter
LSB
3. (00000011)
Reference Counter Latch
4. (00000100)
Mode Controf Latch
5-b Tx Gain Control
5-b Rx Gain Control
MSB
5-b CD Threshold Control
LSB
5. (00000101)
6-b Switched
Capacitor Filter
LSB
Clock Counter Latch
6. (00000110)
Gain Control Latch
~Voltage
MSB
MSB
Reference Adjust
SCF Clock Dividers Latch
7. (00000111)
Auxiliary Latch
Figure 12. Reference Frequency and Reference Divider Values
Crystal
Frequency
Reference
Divider
Value
10.24 MHz
2048
10.24 MHz
1024
11.15MHz
2230
12.00 MHz
U.K. Basel
Handset
Divider
Reference
Frequency
SC Filter
Clock
Divider
SC Filter
Clock
Frequency
Scrambler
Modulation
Divider
Scrambler
Modulation
Frequency
1.0
5.0 kHz
31
165.16 kHz
40
4.129 kHz
4.0
2.5 kHz
31
165.16 kHz
40
4.129 kHz
1.0
5.0 kHz
34
163.97 kHz
40
4.099 kHz
2400
1.0
5.0 kHz
36
166.67 kHz
40
4.167 kHz
11.15MHz
1784
1.0
6.25 kHz
34
163.97 kHz
40
4.099 kHz
11.15MHz
446
4.0
6.25 kHz
34
163.97 kHz
40
4.099 kHz
11.15 MHz
446
25
1.0 kHz
34
163.97 kHz
40
4.099 kHz
Reference Frequency Selection
The "L02In" and "L02 Ouf' pins form a reference oscillator
when connected to an external parallel-resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 12 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries. "L02 In"
may also serve as an input for an externally generated
reference signal which is ac-coupled. The switched
capacitor filter 6-bit programmable counter must be
programmed for the crystal frequency that is selected since
MOTOROLA ANALOG IC DEVICE DATA
this clock is derived from the crystal frequency and must be
held constant regardless of the crystal that is selected. The
actual switched capacitor clock divider ratio is twice the
programmed divider ratio since there is a fixed divide by 2.0
after the programmable counter. The scrambler mixer
modulation frequency is the switched capacitor clock divided
by 40.
Reference Counter
Figure 13 shows how the reference frequencies for the Rx
and Tx loops are generated. All countries except the U.K.
8-167
MC13110
maximum divide value available from the 12-bit reference
divider (4095). In this case, set "U.K. Base Select" to "1" and
set "U.K. Handset Select" to "1". This will give a fixed divide
by 4 for both the Tx and Rx reference. Then set the reference
divider to 1024 to get a total divider of 4096.
require that the Tx and Rx reference frequencies be identical.
In this case, set "U.K. Base Select" and "U.K. Handset
Select" bits to "0". Then the fixed divider is set to "1" and the
Tx and Rx reference frequencies will be equal to the crystal
oscillator frequency divided by the programmable reference
counter value. The U.K. is' a special case which requires a
different reference frequency value for Tx and Rx. For U.K.
base operation, set "U.K. Base Selecr to "1". For U.K.
handset operation, set "U.K. Handset Selecr to "1".The
Netherlands is also a special case since a 2.5 kHz reference
frequency is used for both the Tx and Rx reference and the
total divider value required is 4096 which is larger than the
Mode Control Register
Power saving modes, mutes, disables, volume control,
and microprocessor clock output frequency are all set by the
Mode Control Register. Operation of the Mode Control
Register is explained in Figures 14 through 21.
Figure 13. Reference Register Programming Mode
U.K. Base
~ Tx Reference Frequency
U.K. Handset
12-b
+25
Programmable
Reference + 4.0 f--+-+-+
Counter
+1.01--+......- - 0 ~--- Rx Reference Frequency
U.K. Handset
U.K. Handset
Select
U.K. Base
Select
TxDivider
Value
Rx Divider
Value
Application
(j
0
1
0
1
1.0
1.0
4.0
25
4.0
All but U.K. and Netherlands
U.K. Base Set
U.K. Hand Set
Netherlands Base and Hand Set
0
1
1
25
4.0
4.0
12-b Ref Counter
LSB
14-Bit Reference Counter Latch
8-168
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Figure 14. Mode Control Register Bits
4-b Volume
Control
Figure 15. Mute and Disable Control Bit Descriptions
ALCDisable
1
Automatic Level Control Disabled
Normal Operation
0
Limiter Disable
1
1
0
Tx Mute
1
0
RxMute
1
0
SP Mute
1
Active
Rx
Standby
Inactive
X
X
X1
X1
X
MPU Interface
X
X
X
MPU Clock Output Disabled
Normal Operation
2nd LO Oscillator
X
X
X
MPU Clock Output
X
X
X
Transmit Channel Muted
Normal Operation
RF Receiver and 1st LO
VCO
X
X
Receive Channel Muted
Normal Operation
Rx PLL
X
X
Carrier Detect
X
X
Data Amp
X
X
Low Battery Detect
X
X
Tx PLL
X
Rx and T x Audio Paths
X
Speaker Amp Muted
Normal Operation
0
"PLL Vref' Regulated
Vo~age
Limiter Disabled
Normal Operation
0
Clock Disable
Figure 17. Power Saving Modes
Circuit Blocks
Power Saving Operating Modes
When the MC1311 0 is used in a handset, it is important to
conserve power in order to prolong battery life. There are five
modes of operation; Active, Rx , Standby, Interrupt, and
Inactive. In Active mode, all circuit blocks are powered. In Rx
mode, all circuitry is powered down except for those circuit
sections needed to receive a transmission from the base. In
the Standby and Interrupt Modes, all circuitry is powered
down except for the Circuitry needed to provide the clock
output for the microprocessor. In Inactive Mode, all circuitry is
powered down except the MPU interface. Latch memory is
maintained in all modes. Figure 16 shows the control register
bit values for selection of each power saving mode and
Figure 17 shows the circuit blocks which are powered in each
of these operating modes.
Figure 16. Power Saving Mode Selection
Stdby Mode Bit
RxModeBit
"CD Out!
Hardware
Interrupt" Pin
0
0
X
Mode
Active
0
1
X
Rx
1
0
X
Standby
1
1
1 or High
Impedance
Inactive
1
1
0
interrupt
MOTOROLA ANALOG IC DEVICE DATA
NOTE: In Standby and Inactive Modes, "PLL Vrer remains powered but
is not regulated. It will fluctuate with Vee.
Inactive Mode Operation and Hardware Interrupt
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the combo IC into the Inactive mode, which turns off the
MPU Clock Output (see Figure 18), and then disable the
microprocessor. In order to give the MPU adequate time to
power down, the MPU Clock output remains active for a
minimum of one reference counter cycle (about 200 /lS) after
the command is given to switch into the "Inactive" mode. An
external timing circuit should be used to initiate the turn-on
sequence. The "CD Ouf' pin has a dual function. In the Active
and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is
disabled and the "CD Ouf' pin is in a "High" state due to the
external pull-up resistor. In the Inactive mode, the "CD Ouf'
pin is the input for the hardware interrupt function. When the
"CD Ouf' pin is pulled "low" by the external timing circuit, the
combo IC switches from the Inactive to the Interrupt mode
thereby turning on the MPU Clock Output. The MPU can then
resume control of the combo IC. The "CD Out" pin must
remain low until the MPU changes the operating mode from
Interrupt to Standby, Active or Rx modes.
8-169
8
MC13110
Figure 18. Hardware Interrupt Operation
Mode
Inactive
Active/Rx
V
fV
EN
CD OutLaw
CD OuUHardware Interrupt
MPU ClockOut
' \ CD Turns Oti
>
1
Delay after MPU selects Inactive Mode to when CD turns off.
I+-I
-I
MPU "Clk Out" Divider Programming
This pin is a clock output which is derived from the crystal
oscillator (2nd local oscillator). It can be used to drive a
microprocessor and thereby reduce the number of crystals
required. Figure 19 shows the relationship between the
crystal frequency and the clock output for different divider
values. Figure 20 shows the "Clk Out" register bit values.
/
"""""'
-".r
ExternalTimer
Pulls Pin Low
MPU Initiates
Mode Change
/ ' \ Timer Output
Disabled
K
1
1
I+-
"MPU Clock Ouf' remains active for a minimum of one count of reference
counter after "CD OuUHardware Interrupf' pin goes high
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 kQ
resistor is included on-chip in series with the "Clk Out" output
driver. A small capacitor can be connected to the "Clk Out"
line on the PCB to form a single pole low pass filter. This filter
will significantly reduce noise radiated from the "Clk Out" line.
Volume Control Programming
The volume control adjustable gain block can be
programmed in 2.0 dB gain steps from -14 dB to +16 dB. The
power-up default value is 0 dB. (See Figure 21.)
Figure 19. Clock Output Values
Clock Output .Divider
Crystal
Frequency
2
3
4
5
10.24 MHz
5.120 MHz
3.413 MHz
2.560 MHz
2.048 MHz
11.15MHz
5.575 MHz .3.717,MHz
2.788 MHz
2.230 MHz
12.00 MHz
6.000 MHz
3.000 MHz
2.400 MHz
4.000 MHz
I'
1
I
Standby/Rx/Active
/
I
1
Interrupt
MPU Initiates
Inactive Mode
MPU "Clk Out" Radiated Noise on Circuit Board
The clock line running between the MC13110 and the
microprocessor has the potential to radiate noise which can
Figure 20. Clock Output Divider
ClkOut
Bit #1
ClkOut
Bit #0
ClkOut
Divider Value
0
0
2
0
1
.3
1
0
4
1
1
5
Figure 21. Volume Control
Volume Control
Bit #3
Volume Control
Bit #2
0
0
8-170
Volume Control
Bit #1
Volume Control
BitiD
Volume
Control #
Gain/Attenuation
Amount
·0
0
0
0
-14dB
0
0
1
1
-12dB
0
0
1
0
2
-10dB
0
0
1
1
3
-8.0 dB
0
1
0
0
4
-6.0 dB
0
1
0
1
5
-4.0 dB
0
1
1
0
6
-2.0dS
0
1
1
1
7
OdB
1
0
0
0
8
2.0 dB
1
0
0
1
9
4.0 dB
1
0
1
0
10
6.0 dB
1
0
1
1
11
8.0dB
1
1
0
0
12
10dB
1
1
0
1
13
12dB
1
1
1
0
14
14dB
1
1
1
1
15
16dB
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Gain Control Register
The gain control register contains bits which control the Tx
Voltage Gain, Rx Voltage Gain, and Carrier Detect threshold.
Operation of these latch bits are explained in Figures 22, 23
and 24.
Tx and Rx Gain Programming
The T x and Rx audio signal paths each have a
programmable gain block. If a Tx or Rx voltage gain other
than the nominal power-up default is desired, it can be
programmed through the MPU interface. Alternately, these
programmable gain blocks can be used during final test of the
telephone to electronically adjust for gain tolerances in the
telephone system as shown in Figure 23. In this case, the T x
and Rx gain register values should be stored in ROM during
final test so that they can be reloaded each time the combo
IC is powered up.
Figure 22. Gain Control Latch Bits
5-b TxGain Control
5-b Rx Gain Control
Figure 23. Tx and Rx Gain Control
Gain Control
Bit #4
Gain Control
Bit #3
Gain Control
Bit #2
Gain Control
Bit #1
Gain Control
Bit #0
Gain
Control #
Gain/Attenuation
Amount
0
0
0
0
0
0
-15dB
0
0
0
0
1
1
-14dB
0
0
0
1
0
2
-13dB
0
0
0
1
1
3
-12dB
0
0
1
0
0
4
-11 dB
0
0
1
0
1
5
-10dB
0
0
1
1
0
6
-9.0 dB
0
0
1
1
1
7
-8.0 dB
0
1
0
0
0
8
-7.0 dB
0
1
0
0
1
9
-6.0 dB
0
1
0
1
0
10
-5.0 dB
0
1
0
1
1
11
-4.0 dB
0
1
1
0
0
12
-3.0 dB
0
1
1
0
1
13
-2.0 dB
0
1
1
1
0
14
-1.0dB
0
1
1
1
1
15
OdB
1
0
.0
0
0
16
1.0dB
1
0
0
0
1
17
2.0dB
1
0
0
1
0
18
3.0 dB
1
0
0
1
1
19
4.0 dB
1
0
1
0
0
20
5.0 dB
1
0
1
0
1
21
6.0 dB
1
0
1
1
0
22
7.0 dB
1
0
1
1
1
23
8.0 dB
1
1
0
0
0
24
9.0 dB
1
1
0
0
1
25
10dB
1
1
0
1
0
26
11 dB
1
1
0
1
1
27
12 dB
1
1
1
0
0
28
13dB
1
1
1
0
1
29
14dB
1
1
1
1
0
30
15dB
1
1
1
1
1
31
16dB
MOTOROLA ANALOG IC DEVICE DATA
II
&-171
MC13110
Carrier Detect Threshold Programming
The "CD Ouf' pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. The
nominal value and tolerance of the carrier detect threshold is
given in the carrier detect specification section of this
document. If a, different carrier detect threshold value is
desired, it can be programmed through the MPU interface as
shown in Figure 24. Alternately, the carrier detect threshold
can be electronically adjusted during final, test of the
telephone to reduce the tolerance of the carrier detect
threshold., This is done by measuring the threshold and then
by adjusting the threshold through the MPU interface. In this
case, it is necessary to store the carrier detect register value
in ROM so that the CD register can be reloaded each time the
combo IC is powered up.
Figure 24. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
Bit #1
CD
Bit #0
CD
Control #
Carrier Detect
Threshold
0
0
0
0
0
0
-20dB
0
0
0
0
1
1
-19dB
0
0
0
1
0
2
-18dB
0
0
0
1
1
3
-17dB
0
0
1
0
0
4
-16dB
0
0
1
0
1
5
-15dB
0
0
1
1
0
6
-14dB
0
0
1
1
1
7
-13dB
0
1
0
0
0
8
-12dB
0
1
0
0
1
9
-11 dB
0
1
0
1
0
10
-10dB
0
1
0
1
1
11
-9,0 dB
0
1
1
0
0
12
-8,OdB
0
1
1
0
1
13
-7,0 dB
0
1
1
1
0
14
-6,OdB
8-172
0
1
1
1
1
15
-5,OdB
1
0
0
0
0
16
-4,0 dB
1
0
0
0
1
17
-3,OdB
1
0
0
1
0
18
-2,0 dB
1
0
0
1
1
19
-1.0dB
1
0
1
0
0
20
OdB
1
0
1
0
1
21
1.0dB
1
0
1
1
0
22
2.0 dB
1
0
1
1
1
23
3.0 dB
1
1
0
0
0
24
4.0dB
1
1
0
0
1
25
5.0 dB
1
1
0
1
0
26
6.0 dB
1
1
0
1
1
27
7.0 dB
1
1
1
0
0
28
8.0dB
1
1
1
0
1
29
9.0 dB
1
1
1
1
0
30
10dB
1
1
1
1
1
31
11 dB
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Figure 25. Switched Capacitor Filter Clock DividerNoltage Reference Adjust Latch Bits
6-b Switched
Capacitor Filter
Clock Counter latch
4--b Voltage
Reference Adjust
SCF Clock DividerNoltage Reference Adjust Register
This register controls the scrambler bypass mode, the
divider value for the programmable switched capacitor filter
clock divider, and the voltage reference adjust. Operation is
explained in Figures 25 through 30.
The SCF divider should be set to a value which gives a
SCF Clock as close to 165.16 kHz as possible based on the
2nd LO frequency which is chosen (see Figure 12).
Figure 27. SCF Clock and Scrambler Carrier Circuit
Figure 26. Bypass Mode Bit Description
Tx Scrambler
1
Bypass
0
Rx Scrambler
1
Bypass
0
Tx Scrambler Post-Mixer LPF and Mixer
Bypassed
Normal Operation with Tx Scrambler
6-b
Programmable
SCF Clock Counter
Rx Scrambler Post-Mixer LPF and Mixer
Bypassed
Normal Operation Rx Scrambler
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter and
scrambler modulation clock dividers is shown in Figure 27.
There is a fixed divide by 2 after the programmable divider.
The switched capacitor filter clock value is given by the
following equation;
(SCF Clock) = F(2nd LO)/(SCF Divider Value * 2)
The scrambler modulation clock frequency (SMCF) is
proportional to the SCF clock and is given by the following
equation;
Scrambler Modulation Frequency Programming
Four different scrambler modulation frequencies may be
selected by programming the SCF Clock divider as shown in
Figures 28 and 29. Note that all filter corner frequencies will
change proportionately with the SCF Clock and Scrambler
Modulation Frequency. The power-up default SCF Clock
divider value is 31.
SMCF =(SCF Clock Frequency)/40
Figure 28. Scrambler Modulation Frequency Programming for a 10.240 MHz 2nd LO
SCF
Clock
Divider
Total
Divide
Value
SCF
Clock
Freq.
(kHz)
Scrambler
Modulation
Frequency
(Clkl40) (kHz)
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
Rx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
Tx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
29
30
31
32
58
60
62
64
176.55
170.67
165.16
160.00
4.414
4.267
4.129
4.000
267.2
258.3
250.0
242.2
3.902
3.772
3.650
3.536
4.147
4.008
3.879
3.758
3.955
3.823
3.700
3.584
NOTE:
All filter comer frequencies have a tolerance of ±3%.
Figure 29. Scrambler Modulation Frequency Programming for a 11.15 MHz 2nd LO
SCF
Clock
Divider
Total
Divide
Value
SCF
Clock
Freq.
(kHz)
Scrambler
Modulation
Frequency
(Clkl40) (kHz)
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
Rx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
Tx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
32
33
64
66
68
70
174.22
168.94
163.97
159.29
4.355
4.223
4.099
3.982
263.7
255.7
248.2
241.1
3.850
3.733
3.624
3.520
4.092
3.968
3.851
3.741
3.903
3.785
3.673
3.568
34
35
NOTE:
All Imer comer frequencies have a tolerance of ±3%.
MOTOROLA ANALOG IC DEVICE DATA
8-173
~
_
MC13110
Voltage Reference Adjustment
The internal 1.5 V Bandgap voltage reference provides the
voltage reference for the "B01 Out" and "B02 Ouf' low
battery detect circuits, the "PLL Vret" voltage regulator, the
"VB" reference, and all internal analog ground references.
The initial tolerance of the Bandgap voltage reference is
±6%. The tolerance of the internal reference voltage can be
improved to ±1.5% through MPU serial interface
programming.
During final test of the telephone, the battery detect
threshold is measured. Then, the internal reference voltage
value is adjusted electronically through the MPU serial
interface to achieve the desired accuracy level. The voltage
reference register value should be stored in ROM during final
test so that it can be reloaded each time the MC13110 is
powered up (see Figure 30).
Figure 30. Bandgap Voltage Reference Adjustment
VrefAdj.
Bit #3
VrefAdj.
Bit #2
VrefAdj.
Bit #1
VrefAdj.
Bit #0
VrefAdj.
#
VrefAdj.
Amount
0
0
0
0
0
-9.0%
0
0
0
1
1
-7.8%
0
0
1
0
2
-6.6%
0
0
1
1
3
-5.4%
0
1
0
0
4
-4.2%
0
1
0
1
5
-3.0%
0
1
1
0
6
-1.8%
0
1
1
1
7
-0.6%
1
0
0
0
8
+0.6%
1
0
0
1
9
+1.8%
1
0
1
0
10
+3.0%
1
0
1
1
11
+4.2%
1
1
0
0
12
+5.4%
1
1
0
1
13
+6.6%
1
1
1
0
14
+7.8%
1
1
1
1
15
+9.0%
8-174
Auxiliary Register
The auxiliary register contains a 3-bit 1st LO Capacitor
Selection latch and a 4-bit Test Mode latch. Operation of
these latch bits are explained in Figures 31, 32 and 34.
Figure 31. Auxiliary Register Latch Bits
MSB
4-b Test Mode
LSB
MSB
3-b 1st LO Capacitor
Selection
LSB
First Local Oscillator Programmable Selection (U.S.
Applications)
There is a very large frequency difference between the
minimum and maximum channel frequencies in the 25
Channel U.S. Standard.The sensitivity of the 1st LO may not
be large enough to accommodate this large frequency
variation. Fixed capacitors can be connected across the 1st
LO tank circuit to change the 1st LO sensitivity. Internal
switches and capacitors are provided to enable
microprocessor control over internal fixed capacitor values.
Figures 32 and 33 show the schematic representation of the
1st LO and the tank circuit. Figure 34 shows the latch control
bit values for microprocessor control.
Figure 32. First Local Oscillator Schematic
--------------,
I
I Vcap Ctrl
lstLO
Varactor I 41
I
I
MOTOROLA ANALOG Ie DEVICE DATA
MC13110
Figure 33. First Local Oscillator Simplified Schematic
VCCRF
VCCRF
Output
to Buffer
851lA
851lA
Control
VCCRF
t_---:__
lO Out 0--+-----,---+
1
-=-
1.0
12 k
+- -I >I1 i'1tkl- +-_~t-8.-0-k
-
5.8-8.7
6.0 k
-=-
VCCRF
...
+---..----+--0 LO In
B.Ok
-=-
-=-
-=-
-=Cp 0.8 pF
.-J
T380
.-J
T570
.-J
T320
.-J
T220
CaO.9pF
I
Cb 1.7 pF
I
Cc 6.3 pF
I
Cd 7.8 pF
I
Figure 34. First Local Oscillator Programmable Capacitor Selection for U.S. 25 Channels
1st
LO
Cap.
Bit 2
1st
LO
Cap.
Bit 1
1st
LO
Cap
Bit 0
1st
LO
Cap.
Select
U.S.
Base
Channels
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
Varactor
Value over
0.3 to 2.5 V
Equivalent
Internal
Parallel
Resistance
at 40 MHz
(ka)
Equivalent
Internal
Parallel
Resistance
at 51 MHz
(ka)
External
Capacitor
Value
External
Inductor
Value
U.S.
Handset
Channels
Internal
Capacitor
Value
1-10
-
0.8pF
5.8-8.7pF
>1000
>1000
24pF
0.47 ~H
-
1-10
0.8pF
5.8-8.7pF
>1000
>1000
33pF
0.4711H
1
11-16
2.5pF
5.8-8.7pF
35
21
24pF
0.4711H
0
2
17-25
-
1.7pF
5.8-8.7pF
100
60
24pF
0.4711H
1
3
-
11-16
8.6pF
5.8-8.7pF
6.1
3.8
33pF
0.4711H
4
-
17-25
8.0
5.0
33pF
0.4711H
0
MOTOROLA ANALOG IC DeVICE DATA
7.1 pF
5.8-8.7pF
8-175
MC13110
Figure 35. Digital Test Mode Description
Counter Under Test or
Test Mode Option
"TxVCO"
Input Signal
TM#
TM3
TM2
TM 1
TMO
"Clk Out" Output Expected
0
0
0
0
0
Normal Operation
1
0
0
0
1
Rx Counter, upper 6
Ot02,5 V
2
0
0
1
0
Rx Counter, lower 8
Oto 2,5 V
See Note Below
3
0
0
1
1
Rx Prescaler
Ot02.5 V
Input Frequency/4
Input Frequency/64
-
>200mVpp
Input Frequency/64
4
0
1
0
0
Tx Counter, upper 6
o to 2.5 V
5
0
1
0
1
Tx Counter, lower 8
Ot02.5 V
6
0
1
1
0
Tx Prescaler
7
0
1
1
1
Reference Counter
Ot02.5 V
Input Frequency/Reference Counter Value
8
1
0
0
0
Divide by 4, 25
Ot02.5 V
Input Frequencyl100
9
1
0
0
1
SCCounter
Oto 2.5 V
Input Frequency/SC Counter Value
10
1
0
1
0
Scrambler Modulation Counter
Ot02.5 V
Input Frequency/40
See Note Below
Input Frequency/4
>200mVpp
NOTE: To determine the correct output, look at the lower B-bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6-b~s of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
Figure 36. Analog Test Mode Description
II
TM#
TM3
TM2
TM1
TMO
Circuit Blocks Under Test
Input Pin
11
1
0
1
1
Compressor
Cln
Txln
12
1
1
0
0
Tx Scrambler
Txln
TxOut
13
1
1
0
1
ALC Gain
N/A
N/A
14
1
1
1
0
ALC Gain
N/A
N/A
15
1
1
1
1
N/A
N/A
=10 Option
=25 Option
Not Used
Test Modes
Digital and analog test modes can be selected through the
4-bit Test Mode Register. In digital test mode, the "Tx VCO"
input pin is multiplexed to the input of the counter under test
and the output of the counter under test is multiplexed to the
"Clk Out" output pin so that each counter can be individually
tested. Make sure test mode bits are set to "O's" for normal
operation. Digital test mode operation is described in
Figure 35. During normal operation and when testing the
T x Prescaler, the "Tx VCO" input can be a minimum of 200
mVpp at 80 MHz and should be ac-coupled. For other test
modes, input signals should be standard logic levels of 0 to
2.5 V and a maximum frequency of 16 MHz.
The analog test modes enable separate testing of the
Compressor and Tx Scrambler blocks as shown in Figure 36.
Output Pin
Also, ALC Gain options can be selected through analog test
modes.
Power-Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in the
Rx mode with all mutes active. The reference counter is set to
generate a 5.0 kHz reference frequency from a 10.24 MHz
crystal. The switched capacitor filter clock counter is set
properly for operation with a 10.24 MHz crystal. The scrambler
bypass mode control are set for normal operation of
scrambler. The Tx and Rx latch registers are set for USA
Channel Frequency 21 (Channel 6 for previous FCC 10
Channel Band). Figure 37 shows the initial power-up states
for all latch registers.
Figure 37. Latch Register Power-Up Defaults
MSB
LSB
Register
Count
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Tx
9966
-
-
1
0
0
1
1
0
1
1
1
0
1
1
1
0
Rx
7215
-
-
0
1
1
1
0
0
0
0
1
0
1
1
1
1
Ref
2048
-
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Mode
N/A
-
0
X
0
0
1
1
0
1
1
1
0
1
1
1
1
Gain
N/A
-
0
1
1
1
1
0
1
1
1
1
1
0
1
0
0
SC
31
-
-
1
1
0
0
0
1
1
1
1
1
-
-
-
1
N/A
-
0
Aux
-
-
-
-
-
0
0
0
0
0
0
0
8-176
MOTOROLA ANALOG IC DEVICE DATA
MC13110
APPLICATIONS INFORMATION
Evaluation PC Board
The PCB should be double sided with a full ground plane
on one side; any leaded components are inserted on the
ground plane side. This affords shielding and isolation from
the circuit side of the PCB. The other side is the circuit side
which has the interconnect traces and the surface mount
components. In cases where cost allows, it may be benificial
to use multi layer boards.
The placement of certain components specified in the
application circuits is very critical. These components should
be placed first and the other less critical components are
fitted in last. In general, al/ RF paths should be kept as short
as possible, ground pins should be grounded at the pins and
VCC pins should have adequate decoupling to ground at the
pins. In mixed mode systems where digital and RF/Analog
circuitry are present, the VEE and VCC busses are isolated ac
-wise from each other.
Component Selection
The evaluation PC board is designed to accommodate
specific components, while in some cases it is versatile
enough to use components from various manufacturers and
coil types. The application circuit schematics specify
particular components that were used to achieve the results
shown in the typical curves and tables, but alternate
components should give similar results.
The MC13110 IC is capable of matching the sensitivity,
IMD, adjacent channel rejection, and other performance
criteria of a multi-chip analog cordless telephone system.
For the most part, the same external components are used
as in the multi-chip solution. In the following discussion,
various parts of the system are analyzed for best peformance
and cost tradeoffs. Specific recommendations are made
where certain components or circuit designs offer superior
performance. The system analyzed is the USA "CT-1"
cordless phone.
Input Matching/Sensitivity
The sensitivity of the IC is typically 0.5611Vrms matched
with no preamp. To achieve suitable system performance, a
preamp and passive duplexer must be used. In production
final test, each section of the IC is separately tested to
guarantee its system performance in the specific
application. The preamp and duplexer yields typically -114
dBm 12 dB SINAD sensitivity performance under full duplex
operation.
The duplexer is important to achieve full duplex operation
without significant "de-sensing" of the receiver by the
transmitter. The combination of the duplexer and preamp
circuit have to attenuate the transmitter power to the receiver
by over 60 dB to be effective. They do this while improving
the receiver system noise figure and without giving up too
much IMD intermodulation performance.
The duplexer may be a single piece unit offered by
Shimida and Sansui products (designed for 10 channel CT-1
cordless phone) or a two piece solution offered by Toko
(designed for 25 channel operation). The duplexer frequency
response at the receiver port has a notch at the transmitter
MOTOROLA ANALOG IC DEVICE DATA
frequency band of about 35 to 40 dB with a 2.0 to 3.0 dB
insertion loss at the receiver frequency band.
The preamp circuit utilizes a tuned transformer at the
output side of the amplifier; this transformer is designed to
bandpass filter the receiver input frequency while rejecting
the transmitter frequency. The tuned preamp also improves
the noise performance by reducing the bandwidth of the pass
band and reducing the second stage contribution of the 1st
mixer. The preamp is biased at about 1.0 mA and 3.0 Vdc
which yields suitable noise figure and gain.
Mixers
The 1st and 2nd mixers are similar in design. Both are
double balanced to suppress the LO and the input
frequencies to give only the sum and difference frequencies
out. Typically the LO is suppressed about 40 to 60 dB. The
1st mixer may be driven either differentially or single ended.
The gain of the 1st mixer has a 3.0 dB corner at 20 MHz and
is used at a 10.7 MHz IF. It has an output impedance of
330 n and matches to a typical 10.7 MHz ceramic filter with
a source and load impedance of 330 n. A series resistor may
be used to raise the impedance for use with crystal filters
which typically have an input impedance much greater than
330 n. The 2nd mixer input impedance is typically 3.0 kn; it
requires an external 360 n parallel resistor for use with a
standard 330 n 10.7 MHz ceramic filter. The second mixer
output impedance is 1.5 kn making it suitable to match
455 kHz ceramic filters.
The following table is a list of typical input impedances
over frequency for the 1st Mixer. Rp and Cp are represented
in parallel form.
Frequency (MHz)
Rp(Q)
20
977.7
2.44
25
944.3
2.60
30
948.8
2.65
35
928
2.55
2.51
Cp (pF)
40
900
45
873.4
2.65
50
859.3
2.72
55
821
2.72
60
795
2.74
First Local Oscillator
The 1st LO is a multi-vibrator oscillator that takes an extemal
capacitance and inductance. It is voltage controlled to an
intemal varactor from an external loop filter and an on-board
phase-lock loop (PLL). The schematic in Figure 33 shows all
the basic parasitic elements of the internal circuitry. The 1st LO
internal component values have a tolerance of 15%. A typical
dc bias level on the LO Input and LO Output is 0.47 Vdc. The
curve in Figure 38 is the varactor control voltage range as it
relates to capacitance. It represents the expected capacitance
for a given control voltage of the MC13110.
II_
MC13110
Figure 38. First local Oscillator Varacter
versus Control Voltage
12
11
CL
8 10
w
\
(,)
z
~ 9.0
(,)
c::
15
8.0
\
\.
~
~ 7.0
6.0
5.0
o
0.5
.........
.........
.... "'--...
1.0
1.5
2.0
VCV, CONTROL VOLTAGE (V)
r-2.5
3.0
Second local Oscillator
The 2nd lO is a CMOS oscillator similar to that used in the
MC145162. The 2nd LO is also used as the PLL reference
oscillator. It is designed to utilize an external parallel resonant
crystal.
'
II
PllDesign
The 1st LO level is important, as well as the choice of the
crystal for the PLL cJock reference and 2nd LO. A
fundamental, parallel resonant crystal specified with 7.0 to
12 pF load calibration capacitance is recommended. With
load calibration capacitance too high, the-crystal locks up
very slowly. If the LO power is less than -10 dBm, a
pull-down resistor at the 1st LO emitter (Pin 41) will
increase its drive level. The LO level is primarily a function
of the Colpitts capacitive voltage divider formed by the
capacitors between the base to emitter and the emiller to
ground.
The VCO gain factor expressed in MHzIV is indeed critical
to the phase noise performance. If this curve is too steep or
too sensitive to changes in control voltage, it may degrade
the phase noise performance. The external VCO circuit
design needs to consider the typical swing of the control
voltage and the corresponding linearity of the transfer
function, ~fosd!Ncontrol. In general, the higher the Q of the
VCO circuit inductor, the beller phase noise performance.
Adjacent channel rejection and isolation between the 1st
and 2nd mixers may be adversely affected due to layout
problems and difficulty in getting close to the package pins
with the grounds and decoupling capacitors on the RF VCC.
These system parameters must be evaluated for sensitivity
to layout and external component placement.
Intermodulation and adjacent channel performance
problems may also result from spurs around the 1st LO'which
may be caused by harmonics from the switched capacitor
clock driver and too low 1st LO drive level. The clock driver
8-178
operates at a frequency which is f(2nd LO)/(2 • (SCF
Divider». The harmonics are n • (f(2nd LO», where n can be
any positive integer. The current spikes of the SCF on the
supply lines cause the disturbance of the 1st LO. This may be
verified by observing the spurs on a spectrum analyzer while
changing the clock divider value. The spur frequencies will
change when the divider value is changed. The spurious
sideband problem may be avoided by changing the clock
divider value via software for each channel where it is a
problem. Certain channels are worse than others.
The PLL alignment procedure for the application circuit is
detailed in Appendix C. Refer to the MC145162 data sheet
for PlL design example.
limiting IF Amplifiers
The limiting IF amplifier typically has about 110 dB of gain;
the frequency response starts rolling off at 1.0 MHz.
Decoupling capacitors should be placed close to the
decoupling Pins 31 and 32 to ensure low noise and stable
operation. The IF input impedance is 1.5 k,Q for a suitable
match to 455 kHz ceramic filters.
RSSIICarrier Dtltect
The Received Signal Strength Indicator (RSSI) indicates
the strength of the IF level and the output is proportional to
the logarithm of the IF input signal magnitude. The RSSI
dynamic range is typically 80 dB. Connect 0.01 I1F to GND
from "RSSI" output pin to form the carrier detect filter. A
resistor needed to convert the RSSI current to voltage is
included in the internal circuit. An internal temperature
compensated reference current also improves the RSSI
accuracy over temperature.
"CD Out" is an open collector output; thus, an external
100"k,Q pull-up resistor to VCC is recommended. The carrier
detect threshold is programmable through the MPU
interface.
Quadrature Detector
The quadrature detector is coupled to the IF with an
external capaCitor between Pins 27 and 28; thus, the
recovered signal level output is increased for a given
bandwidth by increasing the capacitor. The external
quadrature component may be either a LCR resonant circuit,
which may be adjustable, or a ceramic resonator which is
usually fixed tuned.
The bandwidth performance of the detector is controlled
by the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
(1) RT=QXL
wherE~
AT is the equivalent shunt resistance across the
LC
Tank. XL is the reactance of the quadrature inductor at the IF
frequency (XL = 2ItfL).
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Specific 455 kHz quadrature LC components are
manufactured by Toko in various 5 mm, 7 mm and 10 mm
shielded cans in surface mount or leaded packages.
Recommended components such as, the 7 mm Toko, is used
in the application circuit. When minaturization is a key
constraint, a surface mount inductor and capacitor may be
chosen to form a resonant LC tank with the PCB and parasitic
device capacitance. The 455 kHz IF center frequency is
calculated by
(2) fc = [21t (LC p)1/2]- 1
where L is the parallel tank inductor. Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455 kHz
and a specific loaded Q. The loaded Q of the quadrature
detector is chosen somewhat less than the Q of the IF
bandpass. For an IF frequency of 455 kHz and an IF bandpass
of 20 kHz, the IF bandpass Q is approximately 23; the loaded
Q of the quadrature tank is chosen at 15.
Example:
Let the total extemal C = 180 pF. Note: the capacitance may
be split between a 150 pF chip capaCitor and a 5.0 to 25 pF
variable capacitor; this allows for tuning to compensate for
component tolerance. Since the extemal capacitance is much
greater than the internal device and PCB parasitic
capacitance, the parasitic capacitance may be neglected.
MOTOROLA ANALOG IC DEVICE DATA
Rewrite equation (2) and solve for L:
L = (0.159)2/(C fc 2)
L = 678 IlH ; Thus, a standard value is chosen:
L = 680 IlH (surface mount inductor)
The value of the total damping resistor to obtain the
required loaded Q of 15 can be calculated from equation (1):
RT = Q(21tfL)
RT = 15 (21t)(0.455)(680) = 29.5 kg
The internal resistance, Rint at the quadrature tank Pin 27
is approximately 100 kg and is considered in determining
the external resistance, Rex! which is calculated from
Rext = ((RT)(Rint))/(Rint - AT)
Rext = 41.8 kg; Thus, choose the standard value:
Rext= 39 kg
A ceramic discriminator is' recommended for the
quadrature circuit in applications where fixed tuning is
desired. The ceramic discriminator and a 22 k resistor are
placed from Pin 27 to VCC. A 10 pF capacitor is placed from
Pin 28 to 27 to properly drive the discriminator.
MuRata Erie has designed a resonator that is compatible
with the IC. For US applications the part number is
CDBM455C48. For Europe the part number is
CDBM450C48. Contact Motorola Analog Marketing for
performance data using muRata's parts.
8-179
II
!
~
Figure 39a. Baseset RF Applications Circuit
.
TP25
R3
220
Vcc-RF
~
P35
VCC-RF ---'VI!'v--rl1
C2
0.1
~R~n------------------~
)10
"'0
"'0
R33
tOJ~
,",XI
~I
",,'
~
M
,
'"'U
\JI
..
"
~
..
,;JOt
..
~
..
'""
"'I
~
,~,o
' -__.....-::::-____...;4,1 !.OJ ru ~
SP1
TP4
C6
15G-{l()()n~7"F
r.
m
CB7
~~
'f
•
Vc:c-A ~vcc
~~1
CBB
0.15
r-------------------~N_~~~,~~
3~~
R2B
-= Gnd
ICI
R29
U.04I
~I
RSO BBOk
?7k
~o.
MC13110FB
P
, "uT
vVI'
TP19
==
o
a
o
1.0k
C
m
(')
m
C
~
:J>
(')
~
Gnd
Z
(I)
(')
Low Batt
~
Data
g
:s
!:
:0
(')
C
Car-De1ect
ClkOut
Clk
~
(5
Mlc11
( Mic
Batt Dead
RxData
,TP13
:D
)0
I
(5
-=Gnd
Vcc-A~
><
)10
)10
"'0
"'0
43
Speaker
~
+._
Z
C
C90
~10
EN
:s:
0....
....
....
Q
Co)
Figure 39a. Baseset RF Applications Circuit (continued)
3:
a
:u
o
r
i
~
gr-
V+
(')
V-
C
m
S
VTx
,.------"
+~
0.1 Y 2 . 2 11F
L6
56 I1H
VRx
C54 +
W~
~
~
00
BaHl
-=
Gnd
C53
~
VCC-RF
~
~
R94
12k
-= Gnd
~
12kL
T PWR-ON
_x___
'------RxPWR-ON
Gnd
V -A
CC
C581J.
IOI1FJ
~
CONI
~
C59
180
)1
TxAudio
~
T
l
IE-
~L4
2.0
R53
$ 68k
MODINI
C37
COO
O.II1F
-------1
.r---?
-= 6800
2
3
""'""~ "'" 15
~.::- Q
Aux
26
VBaH
25
TxData
24
g
a:.
C45
,,13
10
R51
4 .....
512
~~~
6
11
"'" - ~
Il ....
Il
R46
220 k
R49100
Gnd
23
22
W
C50
Vee
~
C40
~
10
R41
27 k
I":"
110
0.022
110
~
~I~
-=-
l"':"
C42
=e----'VVIr-- TxRF-ln
R42
91 k
See Note 1
!
NOTE 1: C42= X42= 51
a
II
R43
21
20
BaH Dead
19
Low BaH
Aux
Aux
Aux
TxPWR-ON
Gnd
VB
RSSI
Aux
R45
75k
8~
TxData~...L.
VTx
Aux
RxPWR-ON
Gnd
RxData
14
110k
7~Emtter
~
27
Gnd
R54
lOOk
28
Aux
10
11
12
13
14
18
17
16
15
s::
0
Enable
...
Clk
0
Data
ClkOut
Carrier Detect
Aux
Aux
Aux
~
Co)
~
II
!
~
Figure 39b. Handset RF Applications Circuit
TP25
R3
220
VCC-RF-"Wv-.,..-+
R21
.100k
•..
:!:P?:J Gi_u~,- - -
=.
P35
VCC-RF
47
TP26
C2
0.1
ThRF~n----------------~-
R33
C87
~h
Mllllnl
R26
LOlln
CBB
0.15
L-__~~______~41 LOl~
SP1
TP4
C6
151l-3OO0~71'F
+
Speaker
-=-Gnd
TP5
•
R8
1-
C10
0.1
"
R5
42
18k
43""'"
------."..,~~~·-IEO"
i:
R28
R29
Co)
U.U41
~,_
IC1
MC13110FB
Mic
-=-Gnd
VCC-A~
Batt Dead
!i:
a
~
§;
»
z
»
6G)
(;
c
~m
c
~
)Ii
....
....
0
44 ""'C9
"'"
T
45
16
Rx Dala
Low Batt
·TP13
1.0k
I
~TP15
i:~~
TxVT
_C7
~10
Gnd
Car-Oetec1
ClkDu1
Clk
Data
lC90
~10
EN
--
d
Figure 3gb. Handset RF Applications Circuit (continued)
!i:
a
:II
o
~
tl
03
)00
z
)00
Battt
6
V+
c;
V-
Ii)
c561
Vee
O.
C57
t y 2.2~F
VTx
L6
56I1H
VRx
-:
Gnd
VCC-RF
c
~
o
c
Gnd
-: Gnd
m
TxPWR-ON
RxPWR-ON
~
):0
C56:t
tO I1F,J
Vcc-A
CaNt
Aux
Aux
Gnd
Aux
25
Tx Data
24
Gnd
Gnd
TxAudia
TxPWR-ON
VBatt
RxPWR-ON
Gnd
23
VB
Data
Gnd
R54
tOOk
~ R53
MODINt
66k
RSSI
Enable
TxVCO
Low Batt
R5t
Aux
t10k
R37
22k
Aux
Aux
TxData~
-'-
tj~:1
27k
!g:
t3630
"01C42
'WIr--l RF I
Se.Natet x -n
NOTE1:C42=X42=5Hl
II
R43
CAl
.....
.....
0
COO
~t
s::
0
.....
Aux
MG13110
APPENDIX B - MC13110 APPLICATION BOARD BILL OF MATERIAL (USA)
Reference
Xl
Description
10.24 Crystal (Load Cap <1-2 pF)
Value
Package
Part Number
Vendor
-
HC49US
AAL 1OM240000FLEl OA
Standard Crystal
-
Sot23
MMBV2109LTl
Motorola
DUPl
Duplexer (25 Channel)
Baseset
Hybrid
DPX1035756-153B
Sumida
DUPl
Duplexer (25 Channel)
Handset
Hybrid
DPX1035756-154B
Sumida
SFE10.7MS2-A
muRata
VR2
Diode
FLl
10.7 MHz Filter (Red Dot)
-
FL2
455 kHz Filter
-
-
CFU455E2
muRata
ICl
Universal Cordless Telephone IC
-
OFP
MC13110FB
Motorola
IC2
FM Transmitter IC
-
SO-16
MC2833D
Motorola
L3
Inductor
0.47J.lH
Can
292SNS-T1370Z
Toko
L4/L5
Inductor
0.22J.lH
Can
292SN8-T1368Z
Toko
Tl/T3
Transformer
-
Can
600GCS-8519N
Toko
T2
Ouadrature Coil
-
Can
7MCS-8128Z
Toko
01
Transistor
-
T0-92
MPSH10
Motorola
03
Transistor
-
T0-92
2N3906
Motorola
04
Transistor
-
TO-92
2N3906
Motorola
NOTE:
Components for the Handset and Baseset are the same, except where noted on the Bill of Material and Schematic.
APPENDIX C - MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME
This measurement definition is based on EIAICCITT
recommendations.
Compressor Attack Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.5X of the final steady state
value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.75X of the final steady
state value.
Expandor Attack
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.57X of the final steady
state value.
Expandor Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.5X of the final steady
state value.
f
6.QdB
i
Input ______~
12dB
~
OmV------+-----------+----------Input _ _ _--'
Attack Time
~
OmV------4------------+-----------AtlackTime
Decay Time
Output
Output ______.J
--~
OmV-------------------------------OmV-----------------------------8-184
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13111
Universal Cordless Telephone
Subsystem IC
The MC13111 integrates several of the functions required for a cordless
telephone into a single integrated circuit. This significantly reduces
component count, board space requirements, external adjustments, and
lowers overall costs. It is designed for use in both the handset and the base.
UNIVERSAL CT-1
SUBSYSTEM
INTEGRATED CIRCUIT
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna In to Audio Out
80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic Discriminator
• Compander
- Expandor Includes Mute, Digital Volume Control, Speaker Driver,
3.5 kHz Low Pass Filter, and Programmable Gain Block
- Compressor Includes Mute, 3.5 kHz Low Pass Filter, Limiter, and
Programmable Gain Block
• Dual Universal Programmable PLL
SEMICONDUCTOR
TECHNICAL DATA
-
Supports New 25 Channel U.S. Standard with No Extemal Switches
Universal Design for Domestic and Foreign CT-1 Standards
Digitally Controlled Via a Serial Interface Port
Receive Side Includes 1st LO VCO, Phase Detector, and 14-Bit
Programmable Counter and 2nd LO with 12-Bit Counter
- Transmit Section Contains Phase Detector and 14-Bit Counter
- MPU Clock Outputs Eliminates Need for MPU Crystal
• Supply Voltage Monitor
- Provides Two Levels of Monitoring with Separate Outputs
- Separate, Adjustable Trip Points
• Programmable Corner Frequency Selection
52
1
II
FB SUFFIX
PLASTIC QFP PACKAGE
CASE 848B
• MC13111 is Pin-for-Pin Compatible with MC13110
ORDERING INFORMATION
• 2.7 to 5.5 V Operation with One-Third the Power Consumption of
Competing Devices
• AN1575: Refer to this Application Note for a List of the "Worldwide
Cordless Telephone Frequencies" (List can also be found in Chapter 8
Addendum of DL128 Data Book)
Device
Tested Operating
Temperature Range
Package
MC13111FB
TA =- 40° to +85°C
QFP-52
Simplified Application
Rx In -+-----;~
Rx PO Out
Rx PO In >-+----~
Rx
Out
Carrier +--+-_ _-<
Detect
TxOut+-t---~==~
Tx VCO +--+-----1
L ___~==~===~
__________
__J
Low
I----+--f---;~ Battery
~===~
Indicator
This device contains 8,262 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
8-185
II
VCC
Figure 1. Production Test Circuit
!
~
RFln)
I1
22.1 k
0.01
49.;
0.01
f-------II~
1000 -=-
~~
I:"
(OAln
3:
....
W
....
....
....
(')
!i:
a
::u
o
VCCA~
~
I~~ ~".
~
~
z
.~
~ BOI
"
g
Data
Oul
Out
(';
c
~m
22.1 k
•
c
!;
)Ii
MPU Clock Output
NOTE: This schematic is only a representation of the actual production test circuit.
• Carrier
Detect Out
MC13111
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Characteristic
VCC
-0.5 to +6.0
Vdc
Junction Temperature
TJ
-65 to +150
°c
NOTES: 1. Devices should not be operated at these Iimtls. The "Recommended Operating Condtlions"
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Min
"",p
Max
Unit
VCC
2.7
3.6
5.5
Vdc
TA
-40
-
85
°c
V
V
Supply Voltagfl
Operating Ambient Temperature
VIL
-
-
0.3
Input Voltage High (Data, Clk, EN)
VIH
2.5
-
-
Output Current (Rx PO, T x PO)
High
Low
IOH
IOL
-
-
-0.7
Input Voltage Low (Data, Clk, EN)
NOTE:
0.7
mA
-
All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25°C, unless otherwise specified;
Test Circuit Figure 1.)
Symbol
Min
"",p
Max
Unit
ACT ICC
ACT ICC
RxlCC
STDICC
INACTICC
-
8.1
8.6
4.3
270
35
12
5.3
500
80
mA
mA
mA
/lA
/lA
Characteristic
Static Current
Active Mode (2.7 V)
Active Mode
Receive Mode
Standby Mode
Inactive Mode
-
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specHied;
Test Circuit Figure 1.)
Characteristic
Condition
PLL VOLTAGE REGULATOR
-
PLLVref
Vo
IL=OmA,
VCC = 3.6 to 5.5 V
VCC Audio
PLLVref
VReg
Line
VCC = 3.6 V, IL = 1.0 mA
VCC Audio
PLLVref
VRea
Loa
-
Regulated Output Level
IL=O mA
Line Regulation
Load Regulation
2.4
2.5
2.6
V
-
-0.6
20
mV
-
-1.1
20
mV
f2ext
-
12
-
MHz
L021n
L020ut
f2ext
-
12
-
MHz
Tx VCO
ftxmax
-
80
-
MHz
PLL LOOP CHARACTERISTICS
2nd LO Frequency
(No Crystal)
-
L021n
2nd LO Frequency
(With Crystal)
-
-
T x VCO (Input Frequency)
Yin = 200 mVpp
MOTOROLA ANALOG IC DEVICE DATA
-
8-187
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
PLL PHASE DETECTOR
RxPD
TxPD
VOL
-
-
(PLL
Vref) *.2
V
RxPD
TxPD
VOL
(PLL
Vref) *.8
-
-
V
-
RxPD
TxPD
10Z
-50
-
50
nA
-
-
RxPD
TxPD
Cout
-
8.0
-
pF
CLoad= 50 pF
-
RxPD
TxPD
ClkOut
tr,tf
-
250
-
ns
Output Voltage Low
IIL=0.7mA
-
Output Voltage High
IIH = -{J.7 mA
-
3-State Leakage Current
V= 1.2V
Output Capacitance
Output Rise and Fall Time
MICROPROCESSOR SERIAL INTERFACE
Input Current Low
Yin = 0.3 V
Standby Mode
-
Data,
Clk,EN
IlL
-5.0
0.3
-
~
Input Current High
Yin = 3.3 V
Standby Mode
-
Data,
Clk, EN
IIH
-
1.5
5.0
~
Hysteresis Voltage
-
-
Data,
Clk, EN
Vhys
-
1.0
-
V
Maximum Clock Frequency
-
Data,
EN,Clk
-
-
-
2.0
-
MHz
Input Capacitance
-
Data,
Clk, EN
-
Cin
-
8.0
-
pF
EN to Clk Setup TIme
-
-
EN,Clk
tsuEC
-
200
-
ns
Data to Clk Setup TIme
-
-
Data, Clk
tsuDC
-
100
-
ns
Hold Time
-
-
Data,Clk
th
-
90
-
ns
Recovery Time
-
-
EN, Clk
trec
-
90
-
ns
Input Pulse Width
-
-
EN,Clk
tw
-
100
-
ns
Input Rise and Fall TIme
-
-
Data,
'Clk, EN
tr,tf
-
9.0
-
lJS
-
-
tpuMPU
-
100
-
Ils
-
2.8
-98
-
-
IlVrms
dBm
1.0
-107
-
IlVrms
dBm
-
.56
-112
-
IlVrms
dBm
MPU Interface Power-Up
Delay
90% of PLL Vref to Data,
Clk, EN
FM RECEIVER (fRF = 46 77 MHz [USA Ch 21] fdev = ±3 0 kHz fmod = 10kHz)
50 n Termination
Mix11n1/2
DetOut
VSIN
Single-Ended, Matched Input
Generator Referred
Mix11n1/2
DetOut
VSIN
Differential, Matched Input
Generator Referred
Mix11n1/2
1st Mixer Voltage
Conversion Gain
Yin = 1.0 mVrms, with CF1
Filter as Load
Mix1 In1/2
Mix10ut
MXgain1
-
12
-
dB
2nd Mixer Voltage
Conversion Gain
Yin = 3.0 mVrms, with CF2
Filter as Load
Mix21n
Mix20ut
MXgain2
-
20
-
dB
1st and 2nd Mixer Vo~age
Gain Total
Yin = 1.0 mVrms, with CF1
and CF2 Load
Mix11n1/2
Mix20ut
MXgainT
24
28
-
dB
1st Mixer Input Impedance
Single-Ended Input
-
Mix1 In1/2
RP1
CP1
-
875
2.7
-
pF
3.0
-
kn
Sensitivity (Input for 12 dB
SINAD)
2nd Mixer Input Impedance
8-188
fin = 10.7 MHz
-
-
DetOut
Mix21n
VSIN
Zin2
-
-
n
MOTOROLA ANALOG IC DEVICE DATA
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC
Test Circuit Figure 1.)
Condition
Characteristic
FM RECEIVER (fRF
=3.6 V, VB =1.5 V, TA =25°C, Active or Rx Mode, unless otherwise specified;
=46 77 MHz [USA Ch 21)
fdev =+
fmod
- 30kHz
.
=10kHz)
1st Mixer Output Impedance
-
-
Mixl0ut
Zoutl
-
330
-
0
2nd Mixer Output
Impedance
-
-
Mix20ut
Zout2
-
1.5
-
kO
Lim In
DetOut
IF Sens
-
71
100
j.1Vrms
=455 kHz
IF -3.0 dB Limiting
Sensitivity
~n
Total Harmonic Distortion
With RC =15 kll.0 nF Filter
at DetOut
Mixllnl
DetOut
THD
-
1.3
2.0
%
Recovered Audio
Yin =3.16 mVrms with
RC =15 kll000 pF Filter
at Det Out
Mixllnl
DetOut
AFO
80
105
150
mVrms
Lim In
DetOut
BW
-
20
-
kHz
Signal to Noise Ratio
Yin =3.16 mVrms,
RC =15 kll000 pF
-
Mixllnl
DetOut
SN
-
49
-
dB
AM Rejection Ratio
Yin =3.16 mVrms,
30% AM, @ 1.0 kHz,
RC =15 kll000 pF
Mixllnl
DetOut
AMR
30
47
-
dB
Mixl1nl/2
Mixl0ut
Vo
1.0dB
Mixl
-
15
-
mVrms
Mix21n
Mix20ut
Vo
1.0dB
Mix2
-
14
-
mVrms
Mixllnl
Mixl0ut
TOlmixl
-
56
-
mVrms
Mix21n
Mix20ut
TOlmix2
-
53
-
mVrms
-
-
DetOut
Zo
-
870
-
0
-
Mixlln
RSSI
RSSI
-
80
-
dB
Mlxlln
CD Out
VT
-
33
-
j.1Vrms
Mixlln
CD Out
Hys
-
3.6
7.0
dB
Mixlln
CD Out
VOH
VCC0.1
3.6
-
V
Mixlln
CD Out
VOL
-
0.02
0.4
V
Demodulator Bandwidth
-
1st Mixer, 1.0 dB Voltage
Compression (Input Pin
Referred)
2nd Mixer, 1.0 dB Voltage
Compression (Input Pin
Referred)
500 Input
1st Mixer 3rd Order
Intercept (Input Pin
Referred)
Yin
=3.98 mVrms
2nd Mixer 3rd Order
Intercept (Input Pin
Referred)
Yin
=3.98 mVrms, 50 0
Detector Output Impedance
Input
RSSIICARRIER DETECT (RL = 100 kO)
RSSI Output Current
Dynamic Range
Carrier Sense Threshold
CD Threshold Adjust
(10100)
Hysteresis
=
=0 Vrms, CD =(10100)
Output High Voltage
Yin
Output Low Voltage
Yin =-80 dBV, CD =(10100)
MOTOROLA ANALOG IC DEVICE DATA
8-189
II
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C"Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
.,
Characteristic
Condition
RSSIfCARRIER DETECT (RL = 100 kQ)
Carrier Sense Threshold
Adjustment Range
Carrier Sense Threshold Number of Steps
-
-
VTlow
range
-20
-
-
-
-
VThi
range
-
-
11
Programmable through MPU
Interface
-
-
VTn
-
32
-
-
Programmable through MPU
Interface
dB
DATA AMP COMPARATOR
Hysteresis
-
DAln
DAOut
Hys
30
40
50
mV
Threshold Voltage
-
DAln
DAOut
VT
2.7
VCC0.7
-
V
Input Impedance
-
-
DAln
ZI
-
11
-
kQ
DAOut
Zo
-
100
Vin = VCC -1.0 V,
IOH=OmA
DAln
DAOut
VOH
VCC0.1
3.6
-
kQ
Output High Voltage
Output Low Voltage
Vin = VCC - 0.4 V,
IOL=OmA
DAln
DAOut
VOL
-.
0.04
0.4
V
Output Impedance
V
Rx AUDIO PATH (fin = 10kHz)
II
Absolute Gain
Vin=-20dBV
Eln
EOut
G
-3.0
0
3.0
dB
Gain Tracking
Vin=-30dBV
Vin =-40 dBV
Eln
EOut
Gt
-21
-42
-20
-40
-19
-38
dB
Total Harmonic Distortion
Vin =-20dBV
Maximum Input Voltage
Maximum Output Voltage
Input Impedance
Eln
EOut
THD
-
0.5
1.0
%
-
Rx Audio In
-
-
-
-11.5
dBV
Increase input voltage until
output voltage THD = 5.0%,
then measure output voltage.
RL = 7.5 k/1.0 IlF
Eln
EOut
VOmax
-
0
-
Rx Audio In
E In
-
Zin
-
600
7.5
-
-
kQ
-
-
dBV
Attack Time
Ecap = 0.5 IlF, Rfilt = 40 k
(See Appendix B)
E In
EOut
ta
-
3.0
-
ms
Release Time
Ecap = 0.5 IlF, Rfilt = 40 k
(See Appendix B)
E In
EOut
tr
-
13.5
-
ms
Compressor to Expandor
Crosstalk
Vin = -10 dBV,
VIE In) = AC Gnd
Cln
EOut
CT
-
-90
-70
dB
Rx Data Muting (Ll Gain)
Vin = -20 dBV,
Rx Gain Adj = (01111)
RxAudio In
E Out
Me
-
-a3
-60
dB
Rx High Frequency Corner
(Note 1)
RxPath,
V Rx Audio In = -20 dBV
Rx Audio In
ScrOut
Rxfch
-
3.879
-
kHz
SPEAKER AMPISP MUTE
Maximum Output Swing
Speaker Amp Muting
Vin=-20dBV
Tx AUDIO PATH (fin = 10kHz, Tx Gain Adj = (01111) fin = 10kHz)
Absolute Gain
Vin = -10 dBV, ALC,
Lim Disabled
Txln
Tx Out
G
-4.0
0
4.0
dB
Gain Tracking
Vln=-30dBV
Vin=-40dBV
Txln
Tx Out
Gt
-11
-17
-10
-20
-9.0
-13
dB
Total Harmonic Distortion
Vln=-10dBV
Tx In
TxOut
THD
-
0.6
1.1
%
8-190
,MOTOROLA ANALOG IC DEVICE DATA
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specilied;
Test Circuit Figure 1.)
Characteristic
Condition
T x AUDIO PATH (lin = 1.0 kHz, Tx Gain Adj = (01111), lin = 1.0 kHz)
Maximum Output Voltage
Increase input voltage until
output voltage THD = 5.0%,
then measure output voltage.
RL = 7.5 kl1.0 IlF
Cln
Tx Out
VOmax
-
-
-5.0
-
dBV
Cln
Tx Out
Zin
-
10
-
kn
Attack Time
Ccap = 0.5 IlF, Rlilt = 40 k
(See Appendix B)
Cln
Tx Out
ta
-
3.0
-
ms
Release Time
Ccap = 0.5 IlF, Rlilt = 40 k
(See Appendix B)
Cln
Tx Out
tr
-
13.5
-
ms
Expandor to Compressor
Crosstalk
Vin = -20 dBV, Speaker Amp
No Load, VIC In) = AC Gnd
Eln
Tx Out
CT
-
-60
-40
dB
TxMuting
Vin-10dBV
Tx In
Tx Out
Mc
-
-90
-60
dB
ALC Output Level
Vin = -10 dBV
Vin = -2.5 dBV
Limiter and Mutes disabled
Tx In
Tx Out
ALCout
-15
-13
-11
-10
-8.0
-6.0
dBV
Limiter Output Level
Vin = -2.5 dBV,
ALC disabled
Txln
Tx Out
Vlim
-10
-7.0
-
dBV
Tx High Frequency Comer
(Note 1)
Tx Path, V Tx In = -10 dBV,
Mic Amp = Unity Gain
Tx In
TxOut
Txlch
-
3.7
-
kHz
Input Impedance
MIC AMP (lin = 1.0 kHz, External resistors set to gain 01 1)
Open Loop Gain
-
Txln
Amp Out
AVOL
-
100,000
-
VN
Gain Bandwidth
-
Tx In
Amp Out
GBW
-
100
-
kHz
RL=10kn
Tx In
Amp Out
VOmax
-
2.8
-
Vpp
Average Threshold
Voltage Belore Electronic
Adjustment
VCC = 3.6 V, Vrel_Adj =
(0111). Take average 01 rising
and lalling threshold
Relj
Ref2
BD10ut
BD20ut
VTi
1.36
1.5
1.64
V
Average Threshold
Voltage After Electronic
Adjustment
VCC = 3.6 V, Vref_Adj =
(adjusted value). Take
average of rising and falling
threshold
Ref1
Ref2
BD10ut
BD20ut
VTf
1.475
1.5
1.525
V
-
Rel1
Rel2
BD10ut
BD20ut
Hys
-
4.0
-
mV
-
Ref1
Ref2
lin
-50
-
50
nA
Maximum Output Swing
LOW BATTERY DETECT
Hysteresis
Input Current
Vin = 1.0 to 2.0 V
Output High Voltage
Vin=2.0V,
RL = 3.9 kQ to VCC
Relj
Ref2
BD10ut
BD20ut
VOH
VCC0.1
3.6
-
V
Output Low Voltage
Vin= 1.0V,
RL = 3.9 kQ to VCC
Ref1
Ref2
BD10ut
BD20ut
VOL
-
0.1
0.4
V
NOTE: 1. The filter specification is based on a 10.24 MHz 2nd LO, and a switched-capac~or (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
andlor SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MOTOROLA ANALOG IC DEVICE DATA
8-191
II
MC13111
PIN FUNCTION DESCRIPTION
Pin
Symbol
Type
Description
1
L021n
L020ut
-
These pins form the PLL reference oscillator when connected to an external parallel-resonant
crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (L02) for
the RF receiver. "L02 In" may also serve as an input for an externally generated reference signal
which is typically a!>-{!oupled. ,
2
3
Vag
-
4
RxPD
Output
Three state voltage output of the Rx Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector input signals. During lock,
very narrow pulses with a frequen~ equal to the reference frequency are present. This pin drives
the external Rx PLL loop filter. It is important to minimize the line length and parasitic capacitance
of this pin.
5
PLL Vref
-
PLL voltage regulator output pin. An internal voltage regulator provides a stable power supply
voltage for the Rx and Tx PLL:s and can also be used as a regulated supply voltage for other IC's.
6
TxPD
Output
Three state voltage output of the Tx Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector input signals. During lock,
very narrow pulses with a frequency equal to the reference frequency are present. This pin drives
the external Tx PLL loop filter. It is important to minimize the line length and parasitic capacitance
of this pin.
7
GndPLL
Gnd
Ground pin for PLL section of IC.
8
Tx VCO
Input
Transmit divide counter input which is driven by an a!>-{!oupled external transmit loop VCO. The
minimum signal level is 200 mVpp @ 60.0 MHz. This pin also functions as the test mode input for
the counter tests.
9
10
11
Data
Input
Microprocessor serial interface input pins for programming various counters and control functions.
12
ClkOut
Output
Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator and a
programmable divider. It can be used to drive a microprocessor and thereby reduce the number of
crystals required in the system design. The driver has an internal resistor in series with the output
which can be combined with an external capacitor to form a low pass filter to reduce radiated noise
on the PCB. This output also functions as the output for the counter test modes.
13
CD Out
I/O
14
BD10ut
Output
Low battery detect output #1 (open collector with external pull-up resistor).
Data amplifier output (open collector with internal 100 kn pull-up resistor).
Intemal reference voltage for switched capacitor filter section.
EN
Clk
Dual function pin; 1) Carrier detect output (open collector with external 100 kn pull-up resistor.
2) Hardware interrupt input which can be used to ''wakEHlp" from Inactive Mode.
15
DAOut
Output
16
BD20ut
Output
Low battery detect output #2 (open collector with extemal pull-up resistor).
17
Tx Out
Output
Tx path audio output.
18
CCap
-
19
Cln
Input
20
Amp Out
Output
21
Txln
Input
22
DAln
Input
23
VCCAudio
Supply
24
RxAudioln
Input
25
DetOut
Output
Compressor rectifier filter capacitor pin. Pull pin high through a capacitor.
Compressor input (ac-coupled).
Microphone amplifier output.
Tx path input to microphone amplifier (Mic Amp) (a!>-{!oupled).
Data amplifier input (a!>-{!oupled).
VCC supply for audio section.
Rx audio input (a!>-{!oupled).
Audio output from FM detector.
26
RSSI
Output
27
28
a Coil
-
Lim Out
29
VCCRF
Supply
30
31
LimC2
Lim C1
-
IF amplifierillmiter capacitor pins.
32
Lim In
Input
Signal input for IF amplifier/limiter.
8-192
Receive Signal Strength Indicator filter capacitor.
A quad coil or ceramic discriminator connected to these pins as part of the FM demodulator circuit.
VCC supply for RF receiver section.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
TYpe
33
SGNDRF
Gnd
Ground pin for RF section of the IC.
Second mixer input.
34
Mix21n
Input
35
Mix20ut
Output
36
Gnd RF
Gnd
Description
Second mixer output.
Ground pin for RF section of the IC.
First mixer output.
37
Mix10ut
Output
38
Mix11n2
Input
39
Mix11n1
Input
40
41
L011n
L010ut
-
Tank Elements for 1st LO Multivibrator Oscillator are connected to these pins.
42
Vcap Ctrl
-
1st LO Varactor Control Pin.
43
GndAudio
Gnd
44
SA Out
Output
45
SA In
Input
46
EOut
Output
47
Ecap
-
Negative phase first mixer input.
Positive phase first mixer input.
Ground for audio section of the IC.
Speaker amplifier output.
Speaker amplifier input (ac-coupled).
Expandor output.
Expandor rectifier filter capacitor pin. Pull pin high through a capacitor.
48
Eln
Input
49
ScrOut
Output
50
Ref2
-
Reference voltage input for Low Battery Detect #2.
51
Ref1
-
Reference voltage input for Low Battery Detect #1.
52
VB
-
Internal half supply analog ground reference.
Expandor Input.
Rx Audio Output.
II
MOTOROLA ANALOG IC DEVICE DATA
8-193
MC13111
FM Receiver
The FM receiver can be used with either a quad coil or a
ceramic resonator. The FM receiver and 1st LO have been
designed to work for all country channels, including 25
channel U.S., without the need for any external switching
circuitry (see Figure 32).
RSSIICarrier Detect
Connect 0.01 J.lF to Gnd from "RSSI" output pin to form the
carrier detect filter. "CD Ouf' is an open collector output
which requires an external 100 kg pull-up resistor to VCC.
The carrier detect threshold is programmable through the
MPU interface.
Data Amp Comparator
The data amp comparator is an inverting hysteresis
comparator. Its open collector output has an internal 100 kg
pull-up resistor. A band pass filter is connected between the
"Det Out" pin and the "DA In" pin with component values as
shown in Figure 1 (Test Circuit). The "DA In" input signal is
ac-coupled.
Figure 2. Data Amp Operation
OataAmp
Oata
Signal
H----"\--++---T---JIf--+--/-,
Hysteresis
~---r--+---r--+---r----
II
OataAmp
Output
I
t
Expandorl Compressor
In Appendix B, the EIAICCITT recommendations for
measurement of the attack and decay times are defined. The
curves in Figures 3 and 4 show the typical expandor and
compressor output versus input responses.
Figure 3. Expandor Typical Response
10
o
-10
:> -20
~
'5
o
-30
w -40
-50
-60
/
-40
/
/
-30
/'
V
/' ~Out=O~BV
-20
Typical at THO = 5.0%
-10
o
Figure 4. Compressor Typical Response
-10
:> -20
~
'5
o -30
02'
V
/'
V
/'
V
~
Tx Out =-5.0 dBV
Typical at THO = 5.0%
-40
-60
-50
-40
-30
-20
-10
10
20
Tx In (dBV)
Rx Audio Path (LPF/R x Gain Adjust!
Rx MutelExpandorNolume Control)
The Rx Audio signal path goes from "Rx Audio In" (Pin 24)
to "E Out" (Pin 46). The "Rx Audio In" input signal is ac
coupled. AC couple between "Scr Out" and "E In" (see
Figure 3).
Speaker Amp/SP Mute
The Speaker Amp is an inverting raiHo-;ail operational
amplifier. The noninverting input is connected to the internal VB
reference. Extemal resistors and capacitors are used to set the
gain and frequency response. The "SA In" Input is ac coupled.
MicAmp
The Mic Amp is an inverting rail-ter-rail operational amplifier
with noninverting input terminal connected to internal VB
reference. External resistors and capacitors are set to the gain
and frequency response. The ''Tx In" input is ac coupled.
Tx Audio Path (Compressor/ALCITx Mute!
Limiter/LPFITx Gain Adjust)
The Tx Audio signal path goes from "Tx In" (Pin 19) to
"Tx Out" (Pin 17). The "c In" input signal is ac coupled from
"Amp Out". The ALC (Automatic Level Control) provides a
"soft" limit to the output signal swing as the input voltage
increases slowly (i.e., a sine wave is maintained). The Limiter
circuit limits rapidly changing signal levels by clipping the
signal peaks. The ALC andlor Limiter can be disabled
through the MPU serial interface (see Figure 4).
Tx and Rx Audio
Each audio path contains a low-pass switched capacitor
filter (SCF). The control register must be set through the MPU
interface (Figure 11) for proper operation (Tx and Rx bits must
be set to"1 "). The SCF corner frequencies are proportional to
the SCF Clock. The SCF Clock Divider is programmable
through the MPU interface as follows: (SCF) F(2nd LO) I
(SCF Divider Value' 2). The LPF corner frequencies can be
=
10
E In (dBV)
8-194
MOTOROLA ANALOG IC DEVICE DATA
MC13111
selected in from the table in Figures 28 and 29 relative to the
2nd LO operating frequency.
PLL Voltage Regulator
The "PLL Vref' pin is the internal supply voltage for the Rx
and Tx PLL's. It is regulated to a nominal 2.5 V. The "VCC
Audio" pin is the supply voltage for the internal voltage
regulator. Two capacitors with 10 !!F and 0.1 !!F values must
be connected to the "PLL Vret" pin to filter and stabilize this
regulated voltage. The "PLL Vret" pin may be used to power
other IC's as long as the total external load current does not
exceed 1.0 mA. The tolerance of the regulated voltage is
initially ±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the "PLL Vref' pin is internally connected to the
"VCC Audio" pin (Le., the power supply voltage is maintained
but is now unregulated).
Low Battery Detect
Two external precision resistor dividers are used to set
independent thresholds for two battery detect hysteresis
comparators. The voltages on "Refl" and "Ref2" are
compared to an internally generated 1.5 V reference voltage.
The tolerance of the internal reference voltage is initially
±6.0%. The Low Battery Detect threshold tolerance can be
improved by adjusting a trim-pot in the external resistor
divider. Alternately, the tolerance of the internal reference
voltage can be improved to ±1.5% through MPU serial
interface programming. The internal reference can be
measured directly at the "VB" pin. During final test of the
telephone, the VB internal reference voltage is measured.
Then, the internal reference voltage value is adjusted
electronically through the MPU serial interface to achieve the
desired accuracy level. The voltage reference register value
should be stored in ROM during final test so that it can be
reloaded each time the MC13111 IC is powered up. Low
Battery Detect outputs are open collector.
Power Supply Voltage
This circuit is used in a cordless telephone handset and
base unit. The handset is battery powered and can operate
on three NiCad cells or on 5.0 V supply.
·PLL Frequency Synthesizer General Description
Figure 5 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL). This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), Spain, Australia, Korea, New
Zealand, U. K., Netherlands, France, and China.
The 2nd local oscillator and reference divider provide the
reference frequency for the receive (Rx) and transmit (Tx)
PLL loops. The programmed divider value for the reference
divider is selected based on the crystal frequency and the
desired Rx and Tx reference frequency values. Additional
divide by 25 and divide by 4 blocks are provided to allow for
generation of the 1.0 kHz and 6.25 kHz reference
frequencies required for the U. K. The 14-bit Tx counter is
programmed for the desired transmit channel frequency. The
14-bit Rx counter is programmed for the desired first local
oscillator frequency. All counters power up in the proper
default state for USA channel #21 (channel #6 for FCC 10
channel band) and for a 10.24 MHz reference frequency
crystal. Internal fixed capacitors can be connected to the tank
circuit of the 1st LO through microprocessor control to extend
the sensitivity of the 1st LO for U.S. 25 channel operation.
Figure 5. Dual PLL Simplified Block Diagram
Tx VCO
6
12-b
Programmable
Reference
Counter
MOTOROLA ANALOG IC DEVICE DATA
+ 25
~ 4 O'-rT~_
..
+1.0 f-!-*--o
"--:'=-:"::':"""
8-195
8
MC13111
PLL VO Pin Specifications
The 2nd La, Rx and Tx PLL's, and MPU serial interface are
powered by the internal voltage regulator at the "PLL Vref'
pin. The "PLL Vref' pin is the output of a voltage regulator
which is powered from the "VCC Audio" power supply pin and
is regulated by an internal bandgap voltage reference.
Therefore, the maximum input and output levels for most PLL
1/0 pins (L02 In, L02 Out, Rx PO, Tx PO, Tx VCO) is the
regulated voltage at the "PLL Vref' pin. The ESD protection
diodes on these pins are also connected to "PLL Vret".
Internal level shift buffers are provided for the pins (Data, Clk,
EN, Clk Out) which connect directly to the microprocessor.
The maximum input and output levels for these pins is Vee.
Figure 6 shows a simplified schematic ofthe 1/0 pins.
Figure 6. PLL VO Pin Simplified Schematics
PLL Vrel
VCC Audio
PLL Vrel
VCC Audio
OO~'"~~~~~
-=-
L02 In, L02 Out,
Rx PO, Tx PO and
Tx VCOPins
-=- -=-
2.0 JJA -=Data, Clk and EN Pins
-=- -=-
ClkOutPin
Figure 8. Enable Timing Requirement
PrevIous Data Latched
EN
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 9 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when "EN" is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the "EN" high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
Figure 9. Microprocessor Interface Programming
Mode Diagrams
Data - - - { MSB
ENJ
Microprocessor Serial Interface
The "Data", "elk", and "EN" pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counters, the switched
capacitor filter clock counter, and various control functions.
The "Data" and "elk" pins are used to load data into the shift
register. Figure 7 shows the timing required on the "Data" and
"Clk" pins. Data is clocked into the shift register on positive
clock transitions.
Figure 7. Data and Clock Timing Requirement
tl
Data,
Clk, EN
Data
Clk
Address Register Programming Mode
Data---{ MSB
16-BHData
LSBr
~------------------~-t-~--J ~~Wh
EN ___________________________,
~
Data Register Programming Mode
The MPU serial interface is fully operational within 100 Ils
after the power supply has reached its minimum level during
power-up (see Figure 10). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx , and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Figure 10. Microprocessor Serial Interface
Power-Up Delay
-1~
sot \
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the "EN" pin.
This is done in two steps. First, an 8-bit address is loaded
into the shift register and latched into the 8-bit address latch
register. Then, up to 18-bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 5 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
&-196
8-Bit Address
:-A
______
m'-pu____
2.7_V___
Clk, EN
Data Registers
Figure 11 shows shows the data latch registers and
addresses which are used to select each of these registers.
Latch bits to the left (MSB) are loaded into the shift register
first. The LSB bit must always be the last bit loaded into the
shift register. Bits preceeding the register must be "D's" as
shown in Figure 11.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 11. Microprocessor Interface Data Latch Registers
~
l_~_b_T_x_c_ou_n_re_r
Latch Address
LSB )
____________________________- - J
1. (00000001)
)
__
M_SB______________________ __R_x_c_o_un_te_r____________________________LSB
--J
2. (00000010)
__
M_SB______________________
Tx Counter Latch
~
l_~
Rx Counter Latch
MSB
12-b Reference Counter
3. (00000011)
LSB
Reference Counter Latch
4. (00000100)
Mode Control Latch
5-b Tx Gain Control
5-b Rx Gain Control
MSB
5-b CD Threshold Control LSB
5. (00000101)
6-b Switched
Capacitor Fitter
LSB
Clock Counter Latch
6. (00000110)
Gain Control Latch
~bVoltage
Reference Adjust
SCF Clock Dividers Latch
7. (00000111)
Auxiliary Latch
Figure 12. Reference Frequency and Reference Divider Values
Crystal
Frequency
Reference
Divider
Value
U.K. Basel
Handset
Divider
Reference
Frequency
SC Filter
Clock
Divider
SC Filter
Clock
Frequency
10.24 MHz
2048
1.0
5.0 kHz
31
165.16 kHz
10.24 MHz
1024
4.0
2.5 kHz
31
165.16 kHz
11.15MHz
2230
1.0
5.0 kHz
34
163.97 kHz
12.00 MHz
2400
1.0
5.0 kHz
36
166.67 kHz
11.15MHz
1784
1.0
6.25 kHz
34
163.97 kHz
11.15MHz
446
4.0
6.25 kHz
34
163.97 kHz
11.15 MHz
446
25
1.0 kHz
34
163.97 kHz
MOTOROLA ANALOG IC DEVICE DATA
8-197
II
MC13111
Reference Frequency Selection
The "L02In" and "L02 Ouf' pins form a reference oscillator
when connected to an external parallel-resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 12 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries. "L02 In"
may also serve as an input for an externally generated
reference signal which is ac-coupled. The switched
capacitor filter 6-bit programmable counter must be
programmed for the crystal frequency that is selected since
this clock is derived from the crystal frequency and must be
held constant regardless of the crystal that is selected. The
actual switched capacitor clock divider ratio is twice the
programmed divider ratio since there is a fixed divide by 2.0
after the programmable counter.
Selecf' bits to "0". Then the fixed divider is set to "1" and the
Tx and Rx reference frequencies will be equal to the crystal
oscillator frequency divided by the programmable reference
counter value. The U.K. is a special case which requires a
different reference frequency value for T x and Rx. For U.K.
base operation, set "U.K. Base Select" to "1". For UK
handset operation, set "U.K. Handset Selecf' to "1".The
Netherlands is also a special case since a 2.5 kHz reference
frequency is used for both the Tx and Rx reference and the
total divider value required is 4096 which is larger than the
maximum divide value available from the 12-bit reference
divider (4095). In this case, set "U.K. Base Select" to "1" and
set "U.K. Handset Select" to "1". This will give a fixed divide
by 4 for both the Tx and Rx reference. Then set the reference
divider to 1024 to get a total divider of 4096.
Mode Control Register
Power saving modes, mutes, disables, volume control,
and microprocessor clock output frequency are all set by the
Mode Control Register. Operation of the Mode Control
Register is explained in Figures 14 through 21.
Reference Counter
Figure 13 shows how the reference frequencies for the Rx
and T x loops are generated. All countries except the U.K.
require that the T x and Rx reference frequencies be identical.
In this case, set "U.K. Base Select" and "UK Handset
Figure 13. Reference Counter Register Programming Mode
U.K. Base
~ Tx Reference Frequency
U.K. Handset
12-b
+ 25
Programmable
Reference + 4.0 f-++..
Counter
+1.0 f--f-.......- o Q - - - - Rx Reference Frequency
UK Handset
U.K. Handset
Select
UK Base
Select
TxDivider
Value
RxDivider
Value
Application
0
0
1
1
0
1
0
1
1.0
25
4.0
4.0
1.0
4.0
25
4.0
All but U.K. and Netherlands
U.K. Base Set
U.K. Hand Set
Netherlands Base and Hand Set
12-b Ref Counter
LSB
III-Bit Reference Counter Latch
Figure 14. Mode Control Register Bits
4-bVolume
Control
8-198
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 15. Mute and Disable Control Bit Descriptions
ALC Disable
1
Automatic Level Control Disabled
Normal Operation
0
limiter Disable
1
1
0
1
Tx Mute
0
RxMute
1
0
SP Mute
Circuit Blocks
limiter Disabled
Normal Operation
0
Clock Disable
Figure 17. Power Saving Modes
1
0
Active
Rx
Standby
Inactive
"PLL Vre( Regulated
Voltage
X
X
Xl
Xl
MPU Interface
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MPU Clock Output Disabled
Normal Operation
2nd LO Oscillator
Transmit Channel Muted
Normal Operation
RF Receiver and 1st LO
VCO
Receive Channel Muted
Normal Operation
Carrier Detect
Speaker Amp Muted
Normal Operation
Low Battery Detect
MPU Clock Output
RxPLL
Data Amp
TxPLL
Power Saving Operating Modes
Rx and Tx Audio Paths
When the MC13111 is used in a handset, it is important to
conserve power in order to prolong battery life. There are five
modes of operation; Active, Rx , Standby, Interrupt, and
Inactive. In Active mode, all circuit blocks are powered. In Rx
mode, all circuitry is powered down except for those circuit
sections needed to receive a transmission from the base. In
the Standby and Interrupt Modes, all circuitry is powered
down except for the circuitry needed to provide the clock
output for the microprocessor. In Inactive Mode, all circuitry is
powered down except the MPU interface. Latch memory is
maintained in all modes. Figure 16 shows the control register
bit values for selection of each power saving mode and
Figure 17 shows the circuit blocks which are powered in each
of these operating modes ..
NOTE: In Standby and Inactive Modes, "PLL vref remains powered but
is not regulated. It will fluctuate w~h Vee.
Inactive Mode Operation and Hardware Interrupt
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the combo IC into the Inactive mode, which turns off the
MPU Clock Output (see Figure 18), and then disable the
microprocessor. In order to give the MPU adequate time to
power down, the MPU Clock output remains active for a
minimum of one reference counter cycle (about 200 lIS) after
the command is given to switch into the "Inactive" mode. An
external timing circuit should be used to initiate the turn-on
sequence. The "CD Ouf' pin has a dual function. In the Active
and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is
disabled and the "CD Out" pin is in a "High" state due to the
external pull-up resistor. In the Inactive mode, the "CD Out"
pin is the input for the hardware interrupt function. When the
"CD Out" pin is pulled "low" by the external timing circuit, the
combo IC switches from the Inactive to the Interrupt mode
thereby turning on the MPU Clock Output. The MPU can then
resume control of the combo IC. The "CD Out" pin must
remain low until the MPU changes the operating mode from
Interrupt to Standby, Active or Rx modes.
Figure 16. Power Saving Mode Selection
Stdby Mode Bit
Rx Mode Bit
"CDOutl
Hardware
Interrupt" Pin
0
0
X
0
1
X
Rx
1
0
X
Standby
1
1
1 or High
Impedance
Inactive
1
1
0
Interrupt
Mode
Active
Figure 18. Hardware Interrupt Operation
Mode
ActiveiR x
Inactive
V
f"V
EN
CD Out/Hardware InlerrupI
CD Oul Low
I
MPUClockOuI
MOTOROLA ANALOG IC DEVICE DATA
I+-I
-I
>
-"'....-
Standby/Rx/Active
r
/
' \ CD Turns Off
1
I
Delay after MPU selects Inactive Mode 10 when CD turns all.
....-
I
I
Interrupt
MPU Initiates
Inactive Mode
External Timer
Pulls Pin Low
/
MPU Inttiales
Mode Change
' \ limer Output
Disabled
K
1
:.- "MPU Clock Ouf' remains active for a minimum of one count of reference
counter after "CD Out/Hardware Interrupf' pin goes high
8-199
8
MC13111
MPU "Clk Out" Divider Programming
This pin is a clock output which is derived from the crystal
oscillator (2nd local oscillator). It can be used to drive a
microprocessor and thereby reduce the number of crystals
required. Figure 19 shows the relationship between the
crystal frequency and the clock output for different divider
values. Figure 20 shows the "Clk Out" register bit values.
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 kil
resistor is included on--chip in series with the "Clk Out" output
driver. A small capacitor can be connected to the "Clk Ouf'
line on the PCB to form a single pole low pass filter. This filter
will significantly reduce noise radiated from the "Clk Ouf' line.
Volume Coritrol Programming
The volume control adjustable gain block can be
programmed in 2.0 dB gain steps from -14 dB to +16 dB. The
power-up default value is 0 dB. (See Figure 21.)
Figure 19. Clock Output Values
Clock Output Divider
Crystal
Frequency
2
3
4
5
10.24 MHz
5.120 MHz
3.413 MHz
2.560 MHz
2.048 MHz
11.15 MHz
5.575 MHz
3.717 MHz
2.788 MHz
2.230 MHz
12.00 MHz
6.000 MHz
4.000 MHz
3.000 MHz
2.400 MHz
MPU "Clk Out" Radiated Noise on Circuit Board
The clock line running between the MC13111 and the
microprocessor has the potential to radiate noise which can
Figure 20. Clock Output Divider
ClkOut
Bit #1
ClkOut
Bit #0
ClkOut
Divider Value
0
0
2
0
1
3
1
0
4
1
1
5
Figure 21. Volume Control
Volume Control
Bit #3
Volume Control
BI1#2
Volume Control
Bit #1
Volume Control
Bit #0
Volume
Control #
Gain/Attenuation
Amount
0
0
0
0
0
-14dB
0
0
0
1
1
-12dB
0
0
1
0
2
-10dB
0
0
1
1
3
-8.0 dB
0
1
0
0
4
-6.0 dB
0
1
0
1
5
-4.0 dB
0
1
1
0
6
-2.0 dB
0
1
1
1
7
OdB
8-200 .
1
0
0
0
8
2.0 dB
1
0
0
1
9
4.0 dB
1
0
1
0
10
6.0 dB
1
0
1
1
11
8.0 dB
1
1
0
0
12
10dB
1
1
0
1
13
12dB
1
1
1
0
14
14dB
1
1
1
1
15
16dB
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Gain Control Register
Tx and Rx Gain Programming
The gain control register contains bits which control the Tx
Voltage Gain, Rx Voltage Gain, and Carrier Detect threshold.
Operation of these latch bits are explained in Figures 22, 23
and 24.
The T x and Rx audio signal paths each have a
programmable gain block. If a Tx or Rx voltage gain other
than the nominal power-up default is desired, it can be
programmed through the MPU interface. Alternately, these
programmable gain blocks can be used during final test of the
telephone to electronically adjust for gain tolerances in the
telephone system as shown in Figure 23. In this case, the T x
and Rx gain register values should be stored in ROM during
final test so that they can be reloaded each time the combo
Ie is powered up.
Figure 22. Gain Control Latch Bits
5-b TxGain Control
5-b Rx Gain Control
Figure 23. TX and Rx Gain Control
Gain Conlrol
Bit #4
Gain Control
Bil#3
Gain Control
Bil#2
Gain Control
Bit #1
Gain Control
Bit #0
Gain
Conlrol#
Gain/Attenuation
Amount
0
0
0
0
0
0
-15dB
0
0
0
0
1
1
-14dB
0
0
0
1
0
2
-13dB
0
0
0
1
1
3
-12dB
0
0
1
0
0
4
-11 dB
0
0
1
0
1
5
-10dB
0
0
1
1
0
6
-9.0 dB
0
0
1
1
1
7
-a.OdB
0
1
0
0
0
a
-7.0 dB
0
1
0
0
1
9
-6.0 dB
0
1
0
1
0
10
-5.0 dB
0
1
0
1
1
11
-4.0 dB
0
1
1
0
0
12
-3.0 dB
0
1
1
0
1
13
-2.0 dB
0
1
1
1
0
14
-1.0dB
0
1
1
1
1
15
OdB
1
0
0
0
0
16
1.0dB
1
0
0
0
1
17
2.0 dB
1
0
0
1
0
18
3.0 dB
1
0
0
1
1
19
4.0 dB
1
0
1
0
0
20
5.0 dB
1
0
1
0
1
21
6.0 dB
1
0
1
1
0
22
7.0 dB
0
1
1
1
23
a.OdB
1
1
0
0
0
24
9.0 dB
1
1
0
0
1
25
10dB
1
1
0
1
0
26
11 dB
1
1
0
1
1
27
12dB
1
1
1
0
0
28
13dB
1
1
1
0
1
29
14dB
1
1
1
1
0
30
15dB
1
1
1
1
1
31
16dB
1
MOTOROLA ANALOG IC DEVICE DATA
II
8-201
MC13111
Carrier Detect Threshold Programming
The ·CD Out" pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. The
nominal value and tolerance of the carrier detect threshold is
given in the carrier detect specification section of this
document. If a different carrier detect threshold value is
desired, it can be progra:mmed through the MPU interface as
shown in Figure 24. Alternately, the carrier detect threshold
can be ele9tronically adjus;ted during final test of the
telephone to reduce the tolerance of the carrier detect
threshold. This is done by measuring the threshold and then
by adjusting the threshold through the MPU interface. In this
case, it is necessary to store the carrier detect register value
in ROM so that the CD register can be reloaded each time the
combo IC is powered up.
Figure 24. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
BII#l
CD
Bit #0
CD
Control #
Carrier Detect
Threshold
0
0
0
0
0
0
-20 dB
0
0
0
0
1
1
-19dB
0
0
0
1
0
2
-18 dB
0
0
0
1
1
3
-17 dB
0
0
1
0
0
4
-16 dB
0
0
1
0
1
5
-15 dB
0
0
1
1
0
6
-14 dB
0
0
1
1
1
7
-13dB
0
1
0
0
0
8
-12 dB
0
1
0
0
1
9
-11 dB
0
1
0
1
0
10
-10dB
0
1
0
1
1
11
-9.0 dB
0
1
1
0
0
12
-8.0 dB
0
1
1
0
1
13
-7.0 dB
0
1
1
1
0
14
-6.0 dB
0
1
1
1
1
15
-5.0 dB
1
0
0
0
0
16
-4.0 dB
1
0
0
0
1
17
-3.0 dB
1
0
0
1
0
18
-2.0dB
1
0
0
1
1
19
-1.0dB
1
0
1
0
0
20
OdB
1
0
1
0
1
21
1.0dB
1
0
1
1
0
22
2.0 dB
1
0
1
1
1
23
3.0 dB
1
1
0
0
0
24
4.0 dB
1
1
0
0
1
25
5.0 dB
1
1
0
1
0
26
6.0 dB
1
1
0
1
1
27
7.0 dB
1
1
1
0
0
28
8.0 dB
II
8-202
1
1
1
0
1
29
9.0 dB
1
1
1
1
0
30
10dB
1
1
1
1
1
31
11 dB
MOTOROLA ANALOG Ie DeVice DATA
MC13111
Figure 25. SCF Clock Divider Latch Bits
6-b Switched
Capacitor Filter
Clock Counter Latch
4-bVoltage
Reference Adjust
SCF Clock Divider
This register controls the divider value for the
programmable switched capacitor filter clock divider and the
voltage reference adjust. Operation is explained in Figures
25 through 30.
The SCF divider should be set to a value which gives a
SCF Clock as close to 165.16 kHz as possible based on the
2nd LO frequency which is chosen (see Figure 12).
Figure 27. SCF Clock Circuit
Figure 26. Audio Mode Bit Description
TxMode
1
0
Normal T x Path Operation
Undefined State
RxMode
1
0
Normal Rx Path Operation
Undefined State
NOTES: Power-up brt default mode
proper operation.
IS
6-b
Programmable
SCF Clock Counter
L02 Out
"0". Must change bit to "1" for
Corner Frequency Programming
Four different corner frequencies may be selected by
programming the SCF Clock divider as shown in Figures 28
and 29. Note that all filter corner frequencies change
proportionately with the SCF Clock Frequency. The
power-up default SCF Clock divider is 31.
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter clock
dividers is shown in Figure 27. There is a fixed divide by 2
after the programmable divider. The switched capaCitor filter
clock value is given by the following equation;
(SCF Clock)
=F(2nd LO)/(SCF Divider Value' 2)
II
Figure 28 Corner Frequency Programming for a 10.240 MHz 2nd LO
SCFClock
Divider
Total
Divide Value
SCFClock
Freq. (kHz)
Rx Upper Corner
Frequency (kHz)
Tx Upper Corner
Frequency (kHz)
29
30
31
32
58
60
62
64
176.55
170.67
165.16
160.00
4.147
4.008
3.879
3.758
3.955
3.823
3.700
3.584
NOTE:
All filter corner frequencies have a tolerance of ±3%.
Figure 29 Corner Frequency Programming fora 11.15 MHz 2nd LO
SCFClock
Divider
Total
Divide Value
SCFClock
Freq. (kHz)
Rx Upper Corner
Frequency (kHz)
Tx Upper Corner
Frequency (kHz)
32
33
34
35
64
66
68
70
174.22
168.94
163.97
159.29
4.092
3.968
3.851
3.741
3.903
3.785
3.673
3.568
NOTE:
All filter corner frequencies have a tolerance of ±3%.
MOTOROLA ANALOG IC DEVICE DATA
6-203
MC13111
Voltage Reference Adjustment
The internal 1.5 V Bandgap voltage reference provides the
voltage reference for the "BD1 Ouf' and "BD2 Ouf low
battery detect circuits, the "PLL Vre(' voltage regulator, the
"VB" reference, and all internal analog ground references.
The initial tolerance of the Bandgap voltage reference is
±S%. The tolerance of the internal reference voltage can be
improved to ±1.5% through MPU serial interface
programming.
During final test of the telephone, the battery detect
threshold is measured. Then, the internal reference voltage
value is adjusted electronically through the MPU serial
interface to achieve the desired accuracy level. The voltage
reference register value should be stored in ROM during final
test so that it can be reloaded each time the MC13111 is
powered up (see Figure 30).
figure 30. Bandgap Voltage Reference Adjustment
II
VrefAdj.
Bit #3
VrefAdJ.
Bit #2
0
0
VrefAdJ.
Bit #1
VretAdj.
Bit #0
VrefAdJ.
#
VrefAdj.
Amount
0
0
0
0
-9.0%
0
0
1
1
-7.8%
0
0
1
0
2
-6.6%
0
0
1
1
3
-5.4%
0
1
0
0
4
-4.2%
0
1
0
1
5
-3.0%
0
1
1
0
6
-1.8%
0
1
1
1
7
-0.6%
1
0
0
0
8
+0.6%
1
0
0
1
9
+1.8%
1
0
1
0
10
+3.0%
1
0
1
1
11
+4.2%
1
1
0
0
12
+5.4%
1
1
0
1
13
+6.6%
1
1
1
0
14
+7.8%
1
1
1
1
15
+9.0%
8-204
Auxiliary Register
The auxiliary register contains a 3-bit 1st LO Capacitor
Selection latch and a 4-bit Test Mode latch. Operation of
these latch bits are explained in Figures 31, 32 and 34.
Figure 31. Auxiliary Register Latch Bits
MSB
4-b Test Mode
LSB
MSB
3-b 1st LO Capacitor
Selection
LSB
First Local Oscillator Programmable Selection (U.S.
Applications)
There is a very large frequency difference between the
minimum and maximum channel frequencies in the 25
Channel U.S. Standard.The sensitivity of the 1st LO may not
be large enough to accommodate this large frequency
variation. Fixed capacitors can be connected across the 1st
LO tank circuit to change the 1st LO sensitivity. Internal
switches and capacitors are provided to enable
microprocessor control over internal fixed capacitor values.
Figures 32 and 33 show the schematic representation of the
1st LO and the tank circuit. Figure 34 shows the latch control
bit values for microprocessor control.
Figure 32. First Local Oscillator Schematic
-------------,I
I Vcap Ctrt
Varactor I 41
I
I
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 33. First Local Oscillator Simplified Schematic
VCCRF
VCCRF
Output
to Buffer
85iJ.A
85iJ.A
Control
Voltage
12 k
12k
1·
VCCRF
8.0k
LOOut
VCCRF
8.0 k
LO In
5.8-8.7
6.0 k
-=-
6.0k
-=-
-=-
-=-
-=Cp 0.8pF
-L
38n
Ca 0.9 pF
57n
Cb 1.7 pF
32n
Cc 6.3 pF
22n
Cd 7.8 pF
-L
-L
-L
II
Figure 34. First Local Oscillator Programmable Capacitor Selection for U.S. 25 Channels
1st
LO
Cap.
Bit 2
1st
LO
Cap.
Bit 1
1st
LO
Cap
BitO
1st
LO
Cap.
Setect
U.S.
Base
Channels
U.S.
Handset
Channels
Internal
Capacitor
Value
Varactor
Value over
0.3 to 2.5 V
Equivalent
Internal
Parallel
Resistance
at 40 MHz
(Idl)
0
0
0
0
1-10
-
O.SpF
5.S-S.7pF
>1000
>1000
24pF
0
0
0
0
-
1-10
O.SpF
5.8-S.7pF
>1000
>1000
33pF
0.47~H
0
0
1
1
11-16
-
2.5pF
5.8-8.7 pF
35
21
24pF
0.47 ~H
0
1
0
2
17-25
-
1.7 pF
5.8-8.7pF
100
60
24pF
0.47 ~H
0
1
1
3
-
11-16
S.6pF
5.8-8.7pF
6.1
3.S
33pF
0.47 ~H
1
0
0
4
-
17-25
7.1 pF
5.8-8.7pF
S.O
5.0
33pF
0.47 ~H
MOTOROLA ANALOG IC DEVICE DATA
Equivalent
Internal
Parallel
Resistance
at 51 MHz
(Idl)
External
Capacitor
Value
External
Inductor
Value
0.47~H
8-205
MC13111
Figure 35. Digital Test Mode Description
Counter Under Test or
Test Mode Option
TM#
TM3
TM2
TM1
TMO
0
0
0
0
0
Normal Operation
"TxVCO"
Input Signal
"Clk Out" Output Expected
-
>200mVpp
1
0
0
0
1
Rx Counter, upper 6
Ot02.5 V
Input Frequency/64
2
0
0
1
0
Rx Counter, lower 8
Ot02.5 V
See Note Below
Input Frequency/4
3
0
0
1
1
Rx Prescaler
Ot02.5 V
4
0
1
0
0
Tx Counter, upper 6
Oto 2.5 V
Input Frequency/64
5
0
1
0
1
Tx Counter, lower 8
Oto 2.5 V
See Note Below
6
0
1
1
0
Tx Prescaler
Reference Counter
Oto 2.5 V
Input Frequency/Reference Counter Value
Input Frequency/100
>200mVpp
7
0
1
1
1
8
1
0
0
0
Divide by 4, 25
Oto 2.5 V
9
1
0
0
1
SCCounter
Oto 2.5 V
10
1
0
1
0
Not Used
NOTE:
Input Frequency/4
Input Frequency/SC Counter Value
-
N/A
To detenninethe correct output, look at the 10wer8--bits in the Rx orTx register (Divisor (7;0). If the value 01 the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6--bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
01 the divisor). II Divisor (7;0) < 16 and Divisor (3;2) < 2, then oulput divisor value is (Divisor (3;2) + 60).
Figure 36. Analog Test Mode Description
II
TM#
TM3
TM2
TM1
TMO
Circuit Blocks Under Test
Input Pin
Output Pin
11
1
0
1
1
Compressor
Cln
Tx In
12
1
1
0
0
Not Used
N/A
N/A
13
1
1
0
1
ALC Gain =10 Option
N/A
N/A
14
1
1
1
0
ALC Gain =25 Option
N/A
N/A
15
1
1
1
1
Not Used
N/A
N/A
Test Modes
Digital and analog test modes can be selected through the
4-bit Test Mode Register. In digital test mode, the ''Tx VCO"
input pin is multiplexed to the input of the counter under test
and the output of the counter under test is multiplexed to the
"Clk Ouf' output pin so that each counter can be individually
tested. Make sure test mode bits are set to "D's" for normal
operation. Digital test mode operation is described in
Figure 35. During normal operation and when testing the
T x Prescaler, the ''Tx VCO" input can be a minimum of 200
mVpp at 80 MHz and should be ao-coupled. For other test
modes, input signals should be standard logic levels of 0 to
2.5 V and a maximum frequency of 16 MHz.
The analog test modes enable separate testing of the
Compressor blocks as shown in Figure 36. Also, ALC Gain
options can be selected through analog test modes.
8-206
Power-Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in
the Rx mode with all mutes active. The reference counter is
set to generate a 5.0 kHz reference frequency from a 10.24
MHz crystal. The switched capacitor filter clock counter is set
properly for operation with a 10.24 MHz crystal. The audio
mode will come up in an undefined state and must be set to
a bit format shown in Figure 26 for proper operation. The T x
and Rx latch registers are set for USA Channel Frequency 21
(Channel 6 for previous FCC 10 Channel Band). Figure 37
shows the initial power-up states for all latch registers.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 37. Latch Register Power-Up Defaults
MSB
Register
Count
15
14
LSB
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Tx
9966
-
-
1
0
0
1
1
0
1
1
1
0
1
1
1
Rx
7215
-
0
1
1
1
0
0
0
0
1
0
1
1
1
1
Ref
2048
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Mode
N/A
-
0
X
0
0
1
1
0
1
1
1
0
1
1
1
1
Gain
N/A
-
0
1
1
1
1
0
1
1
1
1
1
0
1
0
0
SC
31
-
-
-
-
0
1
1
1
0
0
0
1
1
1
1
1
Aux
N/A
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
NOTE:
Bits 6 and 7 in the SC latch register must be set to "1" after power-up for proper operation.
APPLICATIONS INFORMATION
Evaluation PC Board
The PCB should be double sided with a full ground plane
on one side; any leaded components are inserted on the
ground plane side. This affords shielding and isolation from
the circuit side of the PCB. The other side is the circuit side
which has the interconnect traces and the surface mount
components. In cases where cost allows, it may be benificial
to use multi layer boards.
The placement of certain components specified in the
application circuits is very critical. These components should
be placed first and the other less critical components are
fitted in last. In general, all RF paths should be kept as short
as possible, ground pins should be grounded at the pins and
VCC pins should have adequate decoupling to ground at the
pins. In mixed mode systems where digital and RF/Analog
circuitry are present, the VEE and VCC busses are isolated ac
-wise from each other.
Component Selection
The evaluation PC board is designed to accommodate
specific components, while in some cases it is versatile
enough to use components from various manufacturers and
coil types. The application circuit schematics specify
particular components that were used to achieve the results
shown in the typical curves and tables, but alternate
components should give similar results.
The MC13111 IC is capable of matching the sensitivity,
IMD, adjacent channel rejection, and other performance
criteria of a multi-chip analog cordless telephone system.
For the most part, the same external components are used
as in the multi-chip solution. In the following discussion,
various parts of the system are analyzed for best peformance
and cost tradeoffs. Specific recommendations are made
where certain components or circuit designs offer superior
performance. The system analyzed is the USA "CT-1"
cordless phone. (CT-D is a similar cordless application in
Europe.)
Input Matching/Sensitivity
The sensitivity of the IC is typically 0.561lVrms matched
with no preamp. To achieve suitable system performance, a
preamp and passive duplexer must be used. In production
final test, each section of the IC is separately tested to
guarantee its system performance in the specific
application. The preamp and duplexer (differential, matched
MOTOROLA ANALOG IC DEVICE DATA
input) yields typically -114 dBm 12 dB SINAD sensitivity
performance under full duplex operation.
The duplexer is important to achieve full duplex operation
without significant "de-sensing" of the receiver by the
transmitter. The combination of the duplexer and preamp
circuit will attenuate the transmitter power to the receiver by
over 60 dB. This will improve the receiver system noise figure
without giving up too much IMD intermodulation
performance.
The duplexer may be a single piece unit offered by
Shimida and Sansui products (designed for 10 channel CT-1
cordless phone) or a two piece solution offered by Toko
(designed for 25 channel operation). The duplexer frequency
response at the receiver port has a notch at the transmitter
frequency band of about 35 to 40 dB with a 2.0 to 3.0 dB
insertion loss at the receiver frequency band.
The preamp circuit utilizes a tuned transformer at the
output side of the amplifier. This transformer is designed to
bandpass filter at the receiver input frequency while rejecting
the transmitter frequency. The tuned preamp also improves
the noise performance by reducing the bandwidth of the pass
band and reducing the second stage contribution of the 1st
mixer. The preamp is biased at about 1.0 mA and 3.0 Vdc
which yields suitable noise figure and gain.
Mixers
The 1st and 2nd mixers are similar in design. Both are
double balanced to suppress the LO and the input
frequencies to give only the sum and difference frequencies
out. Typically the LO is suppressed about 40 to 60 dB. The
1st mixer may be driven either differentially or single ended.
The gain of the 1st mixer has a 3.0 dB corner at 20 MHz and
is used at a 10.7 MHz IF. It has an output impedance of
330 n and matches to a typical 10.7 MHz ceramic filter with
a source and load impedance of 330 n. A series resistor may
be used to raise the impedance for use with crystal filters
which typically have an input impedance much greater than
330 n. The 2nd mixer input impedance is typically 3.0 kn; it
requires an external 360 n parallel resistor for use with a
standard 330 n 10.7 MHz ceramic filter. The second mixer
output impedance is 1.5 kn making it suitable to match
455 kHz ceramic filters.
8-207
II
:
MC13111
The following table is a list of typical input impedances
over frequency for the 1st Mixer. Rp and Cp are represented
in parallel form.
1.1
Frequency (MHz)
Rp(Q)
Cp(pF)
20
977.7
2.44
25
944.3
2.60
30
948.8
2.65
35
928
2.55
2.51
40
900
45
873.4
2.65
50
859.3
2.72
55
821
2.72
60
795
2.74
First Local Oscillator
The 1st LO is a multi-vibrator oscillator that takes an
external capacitance and inductance. It is voltage controlled
to an internal varactor from an external loop filter and an
on-board phase-lock loop (PLL). The schematic in Figure 33
shows all the basic parasitic elements of the internal circuitry.
The 1st LO internal component values have a tolerance of
15%. A typical dc bias level on the LO Input and LO Output is
0.45 Vdc. The temperature coefficient of the varactor is
+0.09%fOC. The curve in Figure 38 is the varactor control
voltage range as it relates to capacitance. It represents the
expected capacitance for a given control voltage of the
MC13111.
Figure 38. First Local Oscillator Varacter
versus Control Voltage
12
11
u::.s
w
10
1'!'
9.0
~
"-..........:-........
~ 8.0
<3
~ 7.0
6.0
5.0
limiting IF Amplifiers
The limiting IF amplifier typically has about 110 dB of gain;
the frequency response starts rolling off at 1.0 MHz.
Decoupling capacitors should be placed close to Pins 31 and
32 to ensure low noise and stable operation. The IF input
impedance is 1.5 kQ for a suitable match to 455 kHz ceramic
filters .
\.
C3
o
0.5
.....
:---"-
1.0
1.5
2.0
VCV, CONTROL VOLTAGE (V)
r-2.5
3.0
Second Local Oscillator
The 2nd LO is a CMOS oscillator Similar to that used in the
MC145162. The 2nd LO is also used as thePLL reference
oscillator. It is designed to utilize an external parallel resonant
crystal.
PLL DeSign
The 1st LO level is important, as well as the choice of the
crystal for the PLL clock reference and 2nd LO. A
fundamental, parallel resonant crystal specified with 1.0 to
8-208
12 pF load calibration capacitance is recommended. If the
load calibration capacitance is too high, the crystal locks up
very slowly. If the LO power is less than -10 dBm, a
pull-down resistor at the 1st LO emitter (Pin 41) will
increase its drive level. The LO level is primarily a function
of the Colpitts capacitive voltage divider formed by the
capacitors between the base to emitter and the emitter to
ground.
The VCO gain factor expressed in MHzIV is indeed critical
to the phase noise performance. If this curve is too steep or
too sensitive to changes in control voltage, it may degrade
the phase noise performance. The external VCO circuit
design needs to consider the typical swing of the control
voltage and the corresponding linearity of the transfer
function, Ll.fosdLl.Vcontrol. In general, the higher the Q of the
VCO circuit inductor, the better phase noise performance.
Adjacent channel rejection and isolation between the 1st
and 2nd mixers may be adversely affected due to layout
problems and difficulty in getting up close to the package pins
with the grounds and decoupling capacitors on the RF VCC.
These system parameters must be evaluated for sensitivity
to layout and external component placement.
Intermodulation' and adjacent channel performance
problems may also result from spurs around the 1st LO. This
may be caused by harmonics from the switched capacitor
clock driver and too low 1st LO drive level. The clock driver
operates at a frequency which is f(2nd LO)/(2 • (SCF
Divider)). The harmonics are n • (f(2nd LO)), where n can be
any positive integer. The current spikes of the SCF on the
supply lines cause the disturbance of the 1st LO. This may be
verified by observing the spurs on a spectrum analyzer while
changing the clock divider value. The spur frequencies will
change when the divider value is changed. The spurious
sideband problem may be avoided by changing the clock
divider value via software for each channel where it is a
problem. Certain channels are worse than others. Refer to
the MC145162 data sheet for PLL design example.
RSSIiCarrier Detect
The Received Signal Strength Indicator (RSSI) indicates
the strength of the IF level and the output is proportional to
the logarithm of the IF input signal magnitude. The RSSI
dynamic range is typically 80 dB. Connect 0.01 J.lF to GND
from "RSSI" output pin to form the carrier detect filter. A
resistor needed to convert the RSSI current to voltage is
included in the internal circuit. An internal temperature
compensated reference current also improves the RSSI
accuracy over temperature.
"CD Out" is an open collector output; thus, an external
100 kQ pull-up resistor to VCC is recommended. The carrier
detect threshold is programmable through the MPU
interface.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Quadrature Detector
The quadrature detector is coupled to the IF with an
external capacitor between Pins 27 and 28; thus, the
recovered signal level output is increased for a given
bandwidth by increasing the capacitor. The external
quadrature component may be either a LCR resonant circuit,
which may be adjustable, or a ceramic resonator which is
usually fixed tuned.
The bandwidth performance of the detector is controlled
by the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
where RT is the equivalent shunt resistance across the LC
Tank. XL is the reactance of the quadrature inductor at the IF
frequency (XL =21tfL).
Specific 455 kHz quadrature LC components are
manufactured by Toko in various 5 mm, 7 mm and 10 mm
shielded cans in surface mount or leaded packages.
Recommended components such as, the 7 mm Toko, is used
in the application circuit. When minaturization is a key
constraint, a surface mount inductor and capacitor may be
chosen to form a resonant LC tank with the PCB and parasitic
device capacitance. The 455 kHz IF center frequency is
calculated by
(2) fc
=[21t (LCp)1/2j-1
where L is the parallel tank inductor. Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455 kHz
and a specific loaded Q. The loaded Q of the quadrature
detector is chosen somewhat less than the Q of the IF
bandpass. For an IF frequency of 455 kHz and an IF bandpass
MOTOROLA ANALOG IC DEVICE DATA
of 20 kHz, the IF bandpass Q is approximately 23; the loaded
Q of the quadrature tank is chosen at 15.
Example:
Let the total external C =180 pF. Note: the capacitance may
be split between a 150 pF chip capacitor and a 5.0 to 25 pF
variable capacitor; this allows for tuning to compensate for
component tolerance. Since the external capacitance is much
greater than the internal device and PCB parasitic
capacitance, the parasitic capacitance may be neglected.
Rewrite equation (2) and solve for L:
L = (0.159)2/(C fc 2)
L =678 ~H ; Thus, a standard value is chosen:
L = 680 ~H (surface mount inductor)
The value of the total damping resistor to obtain the
required loaded Q of 15 can be calculated from equation (1):
RT = Q(21tfL)
RT =15 (21t)(0.455)(680) =29.5 kn
The internal resistance, Rint at the quadrature tank Pin 27
is approximately 100 kn and is considered in determining
the external resistance, Rext which is calculated from
Rext =((RTHRint))/(Rint - AT)
Rext = 41.8 kn; Thus, choose the standard value:
Rext =39 kn
A ceramic discriminator is recommended for the
quadrature circuit in applications where fixed tuning is
desired. The ceramic discriminator and a 22 k resistor are
placed from Pin 27 to VCC. A 10 pF capaCitor is placed from
Pin 28 to 27 to properly drive the discriminator.
MuRata Erie has designed a resonator that is compatible
with the IC. For US applications the part number is
CDBM455C48. For Europe the part number is
CDBM450C48. Contact Motorola Analog Marketing for
performance data using muRata's parts.
8-209
II
II
...t
Figure 39a. Baseset RF Applications Circuit
CI
TP25
A3
220
~g
P35
VCC-AF
VCC-RF~
l00~ I
-," ,.
47
O!:""i ~(:~v~''--_ __
C2
0.1
TxAF-ln----------'
l>
C5
24pF
SPl
15(1..0000
TP4
C6
~711F
r.
'1~41L01"
r-------------------------
AS
42
v~~
-I~
47k
MlI:llnl M
LC, In
~
"U
"U
m
C87
A33
1000
Z
C
R26
~
X
C88
:
l>
0.15
~
I
~
"U
"U
Speaker
~
Gnd
Mic
A30 680 k
ICl
MC13111FB
~Gnd
VCC-A~
•
"uT
''''
wl ,
s::
~::t1
o
~
l>
Z
l>
b
Cil
(')
C
~
o
c
m
~
loi
llh'
no.
•
$
C
Law Batt
::j
TP13
IW<
j2iM1.0 k
i'
5!~~:
~TxVT
Gnd
g~tutetect
Clk
!j
0
Z
en
0
Ax Data
TP19
EN
Co)
r
.....
n .....
.....
0
Batt Dead
s:
0.....
Figure 39a. Baseset RF Applications Circuit (continued)
i!:
o
d%I
o
~
!
8
03
I T - - V Tx
Battl
V+
V-
(;
c
0 . l Y 2 . 2 I1 F
2N3906
I
Q4
C54
lOI1F
1+
C53
0.01
J: cs/CC
c561
L6
56I1H
VRx
=
Gnd
'--~---
2N3906
VCC-RF
R95
m
:s
o
R94
12k
= Gnd
m
c
~
)Ii
12k
Gnd
TxPWR-ON
' - - - - - - R x PWR-ON
C58:t
10
l1FJ
VCC-A
CONl
Gnd
C59
180
Tx Audio------,
R54
lOOk
R53
::> 68k
MODINl
RF09ctl",S,--.:::;:::::!.-~~~~~
Daoouplr.g
---~~~-~~~~-1l3 r.:::::- c.,.,.." 14
r--;R;;:5:;-1.......
110k
4
R37
22 k
=- ill
02
""
N
5 t:,....
~
02 12
R49 100
N~~--~~~~--
6Gnd
~
8~
Tr211
Cd~19
C40
10
~
t.-.-
R46
220k
R47
75k
"cc
.--_ _--'-'7 01
27 k
VTx
CoIl9cIor
_
Tx Data
Tx
C45
13 10
Aux
26
VBatt
25
Tx Data
24
Gnd
23
Gnd
22
Gnd
21
RSSI
20
Batt Dead
19
Pl
*
00
See Note 1
NOTE 1: C42=X42=51 g
II
Low Batt
Aux
R45
'10
..L
C50JO.022
R44
=..----'VI!'r- TxRF-ln
R42
91 k
27
RxData
VCO
110
C5110.022
R43
28
Aux
Aux
Aux
10
11
12
13
14
18
17
16
15
Aux
Aux
TxPWR-ON
RxPWR-ON
Gnd
VB
Data
Enable
Clk
ClkOUt
Carrier Detect
Aux
Aux
Aux
3:
....(')
....
....
Co)
....
MCt3111
APPENDIX B - MC13111 APPLICATION BOARD BILL OF MATERIAL (USA)
Reference
Xl
Description
10.24 Crystal (Load Cap <12 pF)
Package
Part Number
Vendor
-
HC49US
AAL10M240000FLE10A
Standard Crystal
So123
MMBV2109LTl
Motorola
DUP1
Duplexer (25 Channel)
Saseset
Hybrid
DPX103575B-153B
Sumida
DUP1
Duplexer (25 Channel)
Handset
Hybrid
DPX103575B-154B
Sumida
-
SFE10.7MS2-A
muRata
CFU455E2
muRata
QFP
MC13111FB
Motorola
S0-16
MC2833D
Motorola
VR2
Diode
Value
FL1
10.7 MHz Filter (Red Dot)
-
FL2
455 kHz Filter
ICl
Universal Cordless Telephone IC
IC2
FM Transmitter IC
-
L3
Inductor
0.471J-H
Can
·292SNS-T1370Z
Toko
L4/L5
Inductor
0.221J-H
Can
292SN5-T1368Z
Toko
T11T3
Transformer
Can
6OOGC5-8519N
Toko
Can
7MC5-8128Z
Toko
T2
Quadrature Coil
-
Q1
Transistor
-
TQ-92
MPSH10
Motorola
Q3
Transistor
-
TQ-92
2N3906
Motorola
Q4
Transistor
-
TQ-92
2N3906
Motorola
NOTE:
8-212
Components for the Handset and Basese! are the same, except where noted on the Bill of Material and Schematic.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
APPENDIX C - MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME
This measurement definition is based on EIAICCITI
recommendations.
Compressor Attsck Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.SX of the final steady state
value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.7SX of the final steady
state value.
Expandor Attack
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.S7X of the final steady
state value.
Expandor Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.SX of the final steady
state value.
f
Input _ _ _-!
~
OmV---~-----+_-----
12dB
Input _ _ _-,
OmV-----+------+-------Attack Time
Attack Time
OecayTime
Output _ _ _....
Output
----'
OmV-----------------------OmV------------------
MOTOROLA ANALOG IC DEVICE DATA
8-213
II
®
MOTOROLA
MC13135
MC13136
FM Communications Receivers
The MC13135/MC13136 are the second generation of single chip, dual
conversion FM communications receivers developed by Motorola. Major
improvements in signal handling, RSSI and first oscillator operation have
been made. In addition; recovered audio distortion and audio drive have
improved. Using Motorola's MOSAICTM 1.5 process, these receivers offer
low noise, high gain and stability over a wide operating voltage range.
Both the MC13135 and MC13136 include a Colpitts oscillator, VCO tuning
diode, low noise first and second mixer and LO, high gain limiting IF, and
RSSI. The MC13135 is designed for use with an LC quadrature detector and
has an uncommitted op amp that can be used either for an RSSI buffer or as
a data comparator. The MC13136 can be used with either a ceramic
discriminator or an LC quad coil and the op amp is internally connected for a
voltage buffered RSSI output.
These devices can be used as stand-alone VHF receivers or as the lower
IF of a triple conversion system. Applications include cordless telephones,
short range data links, walkie-talkies, low cost land mobile, amateur radio
receivers, baby monitors and scanners.
DUAL CONVERSION
NARROWBAND
FM RECEIVERS
-
PSUFFIX
PLASTIC PACKAGE
CASE 724
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(S0-24L)
• Complete Dual Conversion FM Receiver - Antenna to Audio Output
• Input Frequency Range - 200 MHz
• Voltage Buffered RSSI with 70 dB of Usable Range
ORDERING INFORMATION
• Low Voltage Operation - 2.0 to 6.0 Vdc (2 Cell NiCad Supply)
• Low Current Drain - 3.5 rnA Typ
II
Device
• Low Impedance Audio Output < 25 n
Operating
Temperature Range
MC13135P
• VHF Colpitts First LO for Crystal or VCO Operation
MC13135DW
• Isolated Tuning Diode
• Buffered First LO Output to Drive CMOS PLL Synthesizer
MC13136P
S0-24L
TA = - 40° to +85°C
1st LO Base
1 1----.3f--i
151 LO Emitter 2
151 LO Out 3 1---..-..,.--'
2nd LO Emitter 5
2ndLOBese 6
2nd Mixer Oul 7 I---<~--'
PIN CONNECTIONS
MC13136
VaricapC
1st LO Base 1
VaricapA
1sl LO Emitter 2
151 Mixer In 1
1st LO Out 3
1st Mixer Out
2nd LO Emitter 5
Vcc2
2nd Mixer In
2ndLOBese 6
2nd Mixer 0IJt 7
RSSI
rm----;
Quad Coil
1st Mixer Out
VCC2
2nd Mixer In
OpAmpln-
Decouple 1
Decouple 2 11
Decouple 2 11
VaricapA
1+----l"~llsIMixerlnl
Buffered RSSI Output
OpAmpOul
OpAmp In-
VaricapC
.---II>--rr71 Audio Out
Audio Out
Decouple 1
Plastic DIP
S0-24L
MC13136DW
MC13135
Package
Plastic DIP
RSSI
Urn/ler Output
r;d---+-l'=-=-=~-"""'ilIl Quad Input
Each device contains 142 active transistors.
8-214
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
MAXIMUM RATINGS
Rating
Power Supply Voltage
Pin
Symbol
Value
4,19
Vcc(max)
6.5
Vdc
RFin
1.0
Vrms
Unit
RF Input Voltage
22
Junction Temperature
-
TJ
+150
'c
Storage Temperature Range
;;-
Tstg
- 65 to +150
'C
Unit
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Maximum 1st IF
Maximum 2nd IF
Ambient Temperature Range
Pin
Symbol
Value
4, 19
VCC
2.0 to 6.0
Vdc
flFI
21
MHz
flF2
3.0
MHz
TA
-40to+85
'C
-
ELECTRICAL CHARACTERISTICS (TA=25'C, VCC=4.0Vdc, '0=49.7MHz, 'MOD= 1.0kHz, Deviation=±3.0kHz, flstLO=39MHz, f2nd
LO = 10.245 MHz, IFI = 10.7 MHz, IF2 = 455 kHz, unless otherwise noted. All measurements performed in the test circuit of Figure 1.)
Characteristic
Condition
Symbol
Total Drain Current
No Input Signal
ICC
Sensitivity (Input for 12 dB SINAD)
Matched Input
VSIN
Recovered Audio
MC13135
MC13136
VRF = 1.0 mV
AFO
Limiter Output Level
(Pin 14, MC13136)
VLlM
1st Mixer Conversion Gain
VRF=-40dBm
MXgain1
2nd Mixer Conversion Gain
VRF=-40dBm
MXgain2
First LO Buffered Output
-
VLO
Total Harmonic Distortion
VRF=-30dBm
THO
Demodulator Bandwidth
-
RSSI Dynamic Range
First Mixer 3rd Order Intercept
(Input)
Second Mixer 3rd Order
Intercept (RF Input)
BW
RSSI
TOIMixl
Matched
Unmatched
Min
Typ
Max
Unit
-
4.0
6.0
mAdc
1.0
-
!lVrms
170
215
220
265
300
365
-
130
-
dB
100
-
mVrms
1.2
3.0
%
50
-
kHz
mVrms
mVrms
12
13
70
dB
dB
dBm
-
-17
-11
-
-27
Matched
Input
TOIMix2
First LO Buffer Output Resistance
-
RLO
-
First Mixer Parallel Input Resistance
-
R
-
722
First Mixer Parallel Input CapaCitance
-
C
-
3.3
First Mixer Output Impedance
-
ZO
-
330
-
Z,
-
4.0
-
kg
-
ZO
-
I.B
-
kn
25
-
g
Second Mixer Input Impedance
Second Mixer Output Impedance
Detector Output Impedance
MOTOROLA ANALOG IC DEVICE DATA
ZO
dBm
-
g
g
pF
g
8-215
II
MC13135 MC13136
TEST CIRCUIT INFORMATION
Although the MC13136 can be operated with a ceram.ic
discriminator, the recovered audio measurements for both
the MC13135 and MC13136 are made with an LC quadrature
detector. The typical recovered audio will depend on the
external circuit; either the Q of the quad coil, or the RC
matching network for the ceramic discriminator. On the
MC13136, an external capacitor between Pins 13 and 14can
be used with a quad coil for slightly higher recovered audio.
See Figures 10 through 13 for additional information.
Since adding a matching circuit to the RF input increases
the signal level to the mixer, the third order intercept (TOI)
point is better with an unmatched input (50 n from Pin 21 to
Pin 22). Typical values for both have been included in the
Electrical Characterization Table. TOI measurements were
taken at the pins with a high impedance probe/spectrum
analyzer system. TtJe first mixer input impedance was
measured at the pin with a network analyzer.
Figure 1a. MC13135 Test Circuit
r-----"""'-....-------,
Vee
1
241
11
Varicap~
~
*0.1
1
1.0k
221
0.001
1-----=:..;----1~ 62pF
*
~
0.211H
0.01
-=
RF
Input
-=
Caramie
Filter
10.7 MHz
360
II
39k
0.1~
0.1
*
1
1
L ___ _ _________ .J
~
Figure 1b. MC13136 Quad Detector Test Circuit
0.1 ~
8-216
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
Figure 2. Supply Current versus Supply Voltage
6.0
5.0
l
~
----
4.0
a::
a::
:::>
u
3.0
c..
c..
2.0
~
1.0
~
iil
/
o
o
~
~
~
U
25
20
15
if.
10
~
~
:!l'
RFin = 49.7 MHz
fMOD = 1.0 kHz
fDEV = ± 3.0 kHz
"I
1
--
~ 1200
VCC=4.0V
1000 f - - RFin = 49.67 MHz
fMOD= 1.0 kHz
fDEV = ±3.0 kHz
- 800
if
t
~O
-
:::> 600
~
V
J
1.0
2.0
3.0
4.0
5.0
6.0
7.0
400
~
200
-140
8.0
V
V
V
-120
-80
-100
-
V
-60
-40
Vcc, SUPPLY VOLTAGE (V)
RF INPUT (dBm)
Figure 4. Varactor Capacitance, Resistance
versus Bias Voltage
Figure 5. Oscillator Frequency
versus Varactor Bias
RJ=50MH~
--
,cp, f= 150 MHz
.......
~
.............
10
z
~ ¥ 47.0
~
~
if.
:::>
ifi
u.
...:
4.0
f-
2.0
Rp, f= 150 MHz
2.0
2.5
3.0
3.5
47.5
6.0 a::
i:d
1.5
-20
48.0
~
8.0 ~
-
5.0
1.0
Cf
w
u
cp, f= 50 MHz
~ o
Ii.
0.5
u
~~
II
if.
C3
I
...-
Figure 3. RSSI Output versus RF Input
1400
~
:!l'
~
w
~
o
00';\
II
,----------1...--5
46.0
45.5
5
4.0
-
O.61 11H
46.5
@
45.0
1.0
Ii.
a::
4.0
5.0
VB, VARACTOR BIAS VOLTAGE, VPin24 to VPin 23 (Vdc)
VB, VARACTOR BIAS VOLTAGE (Vdc)
Figure 6. Signal Levels versus RF Input
Figure 7. Signal + Noise, Noise, and
AM Rejection versus Input Power
6.0
10
S+N
10r---r---r-~r-~--~--~--~--~
I
-10r---+---~---r---+--~~~~~~"~
ffi
~ ~Or---+---~---r~~~~~~~--+---~
c..
-90
-80
-70
-60
-50
-40
RFin, RF INPUT (dBm)
MOTOROLA ANALOG IC DEVICE DATA
-30
-20
-10
~
a::
-20
~
-30
~
Z -40
..............
~
"-~
Z
VCC = 4.0 Vdc
it, -50 r- RFin = 49.67 MHz
-60 r- fMOD = 1.0 kHz
fDEV = ±3.0 kHz
-70
-130
-90
-110
S+N30%AM
""
--
"'-.N
-70
-50
-30
RFin, RF INPUT (dBm)
8-217
MC13135' MC13136
Figure 8. Op Amp Gain and Phase
versus Frequency
50
r"--r-
120
i'
Phase
ain"
~
10
~
0
z
:--...
.i -10
\
160
\
....
.... 4 ~
\
-30
-50
10k
so
....
30
100k
100M
Figure 9. First Mixer Third Order.lntermodulation
(Unmatched Input)
10M
20r---~---"r---~---"---.,
ffi
w
1£e.
~
~
240 GS
200
0-
..,.
-100
2S0
~----'-----''------'-----'-----'
-100
-so
-60
-40
-20
" FREQUENCY (Hz)
RF INPUT (dBm)
Figure 10. Recovered Audio versus
Deviation for MC13135
Figure 11. Distortion versus
Deviation for MC13135
2000,--,-------;:;------r----,.-----.,
R=6SkO
II
O~---~---~----~---~
±1.0
±3.0
±S.O
±7.0
±9.0
±3.0
±5.0
±7.0
±9.0
'DEY, DEVIATION (kHz)
'DEV, DEVIATION (kHz)
Figure 12. Recovered Audio versus
Deviation for MC13136
Figure 13. Distortion. versus
Deviation for MC13136
1000,--,----;;::-::------r----,----,--.,
C
10
z
0
i'iS:. sOO
~
~
en
Q
c
15
~
()
Z
I
0
:z;
a:
..:
:I:
~
~
~
~
ci
0L-__- l_ _ _ _
±M
±U
±M
~
_ _ _ _L __ _- L____
±M
±n
'DEV, DEVIATION (kHz)
8-218
~
±M
__
~
±9.0
:I:
I-
0
±3.0
±4.0
±5.0
±6.0
±7.0
'DEV, DEVIATION (kHz)
±S.O
±9.0
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
CIRCUIT DESCRIPTION
The MC13135/13136 are complete dual conversion
receivers. They include two local oscillators, two mixers, a
limiting IF amplifier and detector, and an op amp. Both
provide a voltage buffered RSSI with 70 dB of usable range,
isolated tuning diode and buffered LO output for PLL
operation, and a separate VCC pin for the first mixer and LO.
Improvements have been made in the temperature
performance of both the recovered audio and the RSS!.
VCC
Two separate VCC lines enable the first LO and mixer to
continue running while the rest of the circuit is powered down.
They also isolate the RF from the rest of the internal circuit.
Local Oscillators
The local oscillators are grounded collector Colpitts, which
can be easily crystal-controlled or VCO controlled with the
on-board varactor and external PLL. The first LO transistor is
internally biased, but the emitter is pinned-out and IQ can be
increased for high frequency or VCO operation. The collector
is not pinned out, so for crystal operation, the LO is generally
limited to 3rd overtone crystal frequencies; typically around
60 MHz. For higher frequency operation, the LO can be
provided externally as shown in Figure 16.
Buffer
An amplifier on the 1st LO output converts the
single-ended LO output to a differential signal to drive the
mixer. Capacitive coupling between the LO and the amplifier
minimizes the effects of the change in oscillator current on
the mixer. Buffered LO output is pinned-out at Pin 3 for use
with a PLL, with a typical output voltage of 320 mVpp at VCC
= 4.0 V and with a 5.1 k resistor from Pin 3 to ground. As seen
in Figure 14, the buffered LO output varies with the supply
voltage and a smaller external resistor may be needed for low
voltage operation. The LO buffer operates up to 60 MHz,
typically. Above 60 MHz, the output at Pin 3 rolls off at
approximately 6.0 dB per octave. Since most PLLs require
about 200 mVpp drive, an external amplifier may be required.
Figure 14. Buffered LO Output Voltage
versus Supply Voltage
600
I
RPin3 =3.0 kQ
500
~-
c..
>0.
E.. 400
~
-O
300
200
./
/'"
/"
~
..... .......
100
2.5
3.0
-----~
..- .....
3.5
4.0
~
--
Mixers
The first and second mixer are of similar design. Both are
double balanced to suppress the LO and input frequencies to
give only the sum and difference frequencies out. This
configuration typically provides 40 to 60 dB of LO
suppression. New design techniques provide improved mixer
linearity and third order intercept without increased noise.
The gain on the output of the 1st mixer starts to roll off at
about 20 MHz, so this receiver could be used with a 21 MHz
first IF. It is designed for use with a ceramic filter, with an
output impedance of 330 n. A series resistor can be used to
raise the impedance for use with a crystal filter, which
typically has an input impedance of 4.0 kn. The second mixer
input impedance is approximately 4.0 kn; it requires an
external 360 n parallel resistor for use with a standard
ceramic filter.
Limiting IF Amplifier and Detector
The limiter has approximately 110 dB of gain, which starts
rolling off at 2.0 MHz. Although not designed for wideband
operation, the bandwidth of the audio frequency amplifier has
been widened to 50 kHz, which gives less phase shift and
enables the receiver to run at higher data rates. However,
care should be taken not to exceed the bandwidth allowed by
local regulations.
The MC13135 is designed for use with an LC quadrature
detector, and does not have sufficient drive to be used with a
ceramic discriminator. The MC13136 was designed to use a
ceramic discriminator, but can also be run with an LC quad
coil, as mentioned in the Test Circuit Information section. The
data shown in Figures 12 and 13 was taken using a muRata
CDB455C34 ceramic discriminator which has been specially
matched to the MC13136. Both the choice of discriminators
and the external matching circuit will affect the distortion and
recovered audio.
RSSIIOpAmp
The Received Signal Strength Indicator (RSSI) on the
MC13135/13136 has about 70 dB of range. The resistor
needed to translate the RSSI current to a voltage output has
been included on the internal circuit, which gives it a tighter
tolerance. A temperature compensated reference current
also improves the RSSI accuracy over temperature. On the
MC13136, the op amp on board is connected to the output to
provide a voltage buffered RSS!. On the MC13135, the op
amp is not connected internally and can be used for the RSSI
or as a data slicer (see Figure 17c).
RPin3 =5.1 kQ
4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (Vdc)
MOTOROLA ANALOG IC DEVICE DATA
8-219
..
I
MC13135 MC13136
Figure 15. PLL Controlled Narrowband FM Receiver at 46149 MHz
MC13135
VCC
~0.1
lOOk
2.7k
SOOp 500p
O$~~'P
47k
1.0~
0.Q1
5.0 PI
":'
":'
22
3
":' 0.001
21
VCCl
0.1
.r
VOO
DO
01
02
03
VSS
0.2 J,lH
0.01~
4
OSC OSC
Out
In
~~~~
p~
3.0p
11so
":'
Input
":'
Ceramic
Filter
10.7 MHz
Finl
POl
P02
LO
~0.1
18
360
Fin2
MCl45166
Recovered
Audio
10
0.1
II
Limiter
10k
11
12
0.1~
RSSI
Output
14
13
Figure 16. 144 MHz Single Channel Application Circuit
1st LO External Oscillator Circuit
Preamp for MC13135 at 144.455 MHz
VCC
*
r-~--~--~--~~+
15k
L1
1.0J,lF
12p
lOOp
1.0k
8-220
470
01 - MPS5179
Xl - 44.585 MHz 3rd Overtone
Series Resonant Crystal
L1 - 0.078 J,lH Inductor
(Coilcraft Part # 141Hl2J08)
01- MPS5179
L2- 0.05J,lH
L3- 0.07J,lH
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
Figure 17a. Single Channel Narrowband FM Receiver at 49.7 MHz
MC13135
VCC
24
23
I+------'==+---I;;:n
22
Buffered LO 4---j----I1-----:.,-:--.-t-=---==----'
Output
0.001
21
0.01*
62 PF( RF Input
I 150 P 50 n Source
0.21lH
.".""
20
Ceramic
Filter
10.7 MHz
360
Recovered
10
0.1
:J
0.1
>--1--'W\-.....- - - - - - I - - _ Audio
Limiter
10k
11
'---'"'+_0---------1-_
12
0.1*
RSSI
Output
14
13
455 kHz
Quad Coil
Figure 17b. PC Board Component View
NOTES: 1. 0.2 I!H tunable (unshielded) inductor
2. 39 MHz Series mode resonant
3rd Overtone Crystal
3. 1.5 I!H tunable (shielded) inductor
4. 10.245 MHz Fundamental mode crystal,
32pF load
5. 455 kHz ceramic filter, muRata CFU 4556
or equivalent
6. Quadrature coil, Toko 7MC-8128Z (7mm)
or Toko RMG-2A6597HM (1Omm)
7. 10.7 MHz ceramic fiRer, muRataSFE10.7MJ-A
or equivalent
Figure 17c. Optional Data Slicer Circuit
(Using Internal Op Amp)
vcc
1.0M
MOTOROLA ANALOG IC DEVICE DATA
8-221
MC13135 MC13136
Figure 18. PC Board So.lder Side View
(Circuit Side View)
II
Figure 19. PC Board Component View
NOTES: 1. 0.21tH tunable (unshielded) inductor
2. 39 MHz Series mode resonant
3rd Overtone Crystal
3. 1.5 IlH tunable (shielded) inductor
4. 10.245 MHz Fundamental mode crystal,
32pF load
5. 455 kHz ceramic IiIter, muRata CFU 4556
or equivalent
6. Ceramic discriminator, muRata CDB455C34
or equivalent
7. 10.7 MHz ceramic finer, muRata SFE10.7MJ-A
or equivalent
8-222
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
Figure 20a. Single Channel Narrowband FM Receiver at 49.7 MHz
MC13136
VCC
24
+
23
1.0*
22
Buffered LO __-+---1If------,:-:-:-~-t__-----'
Output
ri!
0.001
0.01~
-=--=-
Ceramic
Filter
10.7 MHz
~Dr----4--;-~r-~
360
18
-.,...1_7+---"1"".0"'k_......_ _ _ _ _-t--l~ Recovered
/
Audio
10
0.1
62 PF ( RF Input
:c150pF 5OnSource
0.2~H
2_1+--__
L -_ _ _
Lim~er
10k
11
.--t---t-...J
1.._ _+---4~
RSSI
_ _ _ _ _ _ _---I1--_ Oulput
12
0.1~
muRata
455 kHz
Resonator
CDB455C34
Figure 20b. Optional Audio Amplifier Circuit
Speaker
Recovered
Audio
--1
!:::'""-~10~k-ji..:..--~I---'
0.22
51 k
MOTOROLA ANALOG IC DEVICE DATA
8-223
II
Figure 21. MC13135 Internal Schematic
f
18
~ IVCC1
""
'15k
6.0k
12k
2o+-l~
VEE I
I
I
I I
First LO
I I
First Mixer
SecondLO
I I
Second Mixer
Vcc 2
~-----t-$----;7;[;:---r---.--o-16
---.._--VCC2
o==
.....
Co)
.....
Co)
14
UI
3!:
o
.....
~12
.....
Co)
I
VEE
""'"
,
r r
I ,
"T
VEE
OpAmp
13
VCC2
I
I ,
,
VCC2
!I:
a
::II
o
!;
)0
z
§
9
~~~ I
I
I.
I~ J
17
,I
,I ,I
,I
II 11
c;
c
<
m
C;
m
c
~
»
VEE
II
Limiting IF Amplifier
II
Detector and Audio Amplifl8r
This device contains 142 active transistors.
I
VEE
~
iii:
L
Figure 22. MC13136lntemal Schematic
~r~1~h5k~n~I~1~1~II~I~I~1~1~1~1~1~1~1~1I
o
18
6.0k
!j;
)00
12k
~
g
c;
C
2o-t-U---1-\::.
5.0p
~
n
m
C
~
)0
VeE I
First Mixer
FlrstLO
SeconcILO
I I
I I
SeconcIIIiDr
,----~-~r----V~2
~...--
____
~
V~2
$ 'i:f--------t--o 16
3:
--o
Co)
Co)
CII
3:
o
~12
Co)
I
' - - - - - ' - - VeE
I
VeE
OpAmp
13
Vcc2
'"
,
, ,
I I
"
, ,
"
I", I
, ,
V~2
9
~~ ~ I
i
I I~ vi ,I
I
I
17
I ,I ,I II II
"I
VEE
Limiting If Amplifier
14
This device contains 142 active transistors.
II
II
DeII!cIor and Audio AmplIfier
VeE
Co)
Q)
®
MOTOROLA
MC13141
Product Preview
LOW POWER DC - 1.8 GHz
LNA AND MIXER
Low Power DC - 1.8 GHz
LNA and Mixer
SEMICONDUCTOR
TECHNICAL DATA
The MC13141 is intended to be used as a first amplifier and down
converter for RF applications. It features wide band operation, low noise,
high gain and high linearity while maintaining low current consumption. The
circuit consists of a Low Noise Amplifier (LNA), a Local Oscillator amplifier
(LO amp ), a mixer, an Intermediate Frequency amplifier (IFamp) and a dc
control section.
•
•
•
•
•
•
•
•
•
•
8~
Wide RF Bandwidth: DC-1.8 GHz
Wide Mixer Bandwidth: DC-1.8 GHz
Wide IF Bandwidth: DC-100 MHz
Low Power: 7.7 mA @ VCC 2.7-6.5 V
High Mixer Linearity: Pi1.0 dB -2.0 dBm, IP3in 3.0 dBm
Linearity Adjustment Increases IP3in (Not Available in SOIC8)
Up to +20 dBm
Single-Ended 50 n Mixer Input
Double Balanced Mixer Operation
Single-Ended 800 n Mixer Output
Single-Ended 50 n LO Input
=
=
1
01 SUFFIX
PLASTIC PACKAGE
CASE 751
(So-a)
=
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
•
ORDERING INFORMATION
Operating
Temperature Range
Device
20
Package
MC13141D1
FTBSUFFIX
PLASTIC PACKAGE
CASE 976
(ThlnQFP)
so-a
TA = -40° to +85°C
MC13141D
MC13141FTB
1
S0-14
TQFP-20
PIN CONNECTIONS
TQFP-20
S0-14
so-e
~ ~
w
8
w w
w u..
a:
>
>
RFout
Vee
RFout
Enable
RFin
Vee
RFin
VEE
LO
VEEMx
Mix Lin
eont
RFm
IF
VEE
RFm
VEE
Vee IF
VEE 7
VEE
VEELO
IF
This device contains 161 active transistors.
8-226
9
w
w
>
~
w U
~.;?
MOTOROLA ANALOG IC DEVICE DATA
MC13141
MAXIMUM RATINGS (TA
=25°C, unless otherwise noted.)
Rating
Power Supply Voltage
Operating Supply Voltage Range
Symbol
Value
Unit
VCC
7.0 (max)
Vdc
VCC
2.7-6.5
Vdc
ELECTRICAL CHARACTERISTICS (SOIC8 Package, VCC
Characteristic
=3 0 V, TA =25°C , LOin =-10 dBm @ 950 MHz, IF @ 50 MHz)
Symbol
Min
Typ
Max
Unit
100
-
pA
Supply Current (Power Up)
ICC
-
7.7
-
mA
Amplifier Gain (50 0 Insertion Gain)
S21
-
12
-
dB
Amplifier Reverse Isolation
S12
-
-33
dB
rln amp
-
-10
-
-15
-
-15
-
dBm
-5.0
-
dBm
Supply Current (Power Down)
Amplifier Input Match
Amplifier Output Match
ICC
rout amp
Amplifier 1.0 dB Gain Compression
Pin-l.0dB
Amplifier Input Third Order Intercept
IP3in
Amplifier Gain
GNF
@
N.F. (Application Circuit)
17
-
dB
-
dB
15
-
dB
-
=RL =800 0)
Mixer Power Conversion Gain (Rp =RL =800 0)
VGC
PGC
-
7.0
Mixer Input Match
rinM
-
-20
Mixer Vo~age Conversion Gain (Rp
Mixer SSB Noise Figure
NF
NFSSBM
Mixer 1.0 dB Gain Compression
P11L1.0dBM
Mixer Input Third Order Intercept
IP31nM
Mixer 3 dB RF Bandwidth
Mx-3dBBW
-
16.0
1.8
-
GHz
-10
-
dBm
-20
-
dB
-
dB
-
dB
dB
LOin
-
PRFIn-RFln
-
-13
PRFout-RFm
-
-30
PLO-IF
-
-25
dB
PLQ-RFm
-
-50
-
PRFm-IF
-
-50
dB
PRFrn-RFln
-
-
-25
-
dB
PLO-RFin
LO Feedthrough to RFm
Mixer RF Feedthrough to IF
MOTOROLA ANALOG IC DEVICE DATA
dBm
-30
LO Feedthrough to RFin
Mixer RF Feedthrough to RFln
dB
-
rinLO
LO Feedthrough to IF
dB
-3.0
LO Input Match
RFout Feedthrough to RFm
dB
dBm
-10
LO Drive Level
RFln Feedthrough to RFm
dB
1.8
-
Amplifier Noise Figure (50 0)
dB
dB
8-227
II
MC13141
CIRCUIT DESCRIPTION
figure and gain. Input and output matching may be achieved
at various frequencies using few extemal components (see
Application Circuit). Matching the LNA for maximum stable
gain (MSG) yields noise performance within a few tenths of a
dB of the minimum noise figure. Typical performance at
1.0 GHz is 17 dB gain and 1.8 dB noise figure for Vee at
3.0 to 5.0 Vdc.
General
The MC13141 Is a low power LNA, double-balanced
mixer. This device is designated for use as the front-end
section in analog and digital FM systems such as Digital
European Cordless Telephone (DECT), PHS, PCS, Cellular,
UHF and 800 MHz Special Mobile Radio (SMR), UHF
Family Radio Services and 902 to 928 MHz cordless
telephones. It features a mixer linearity control to preset or
auto preset or auto program the mixer dynamic range, an
enable function and buffered IF output for increased overall
gain. Further details are covered in the Pin Function
Description which shows the equivalent internal circuit and
external circuit requirements.
Mixer
The mixer is a double-balanced four quadrant multiplier
biased class AB allowing for programmable linearity control
via an external current source. An input third order intercept
point of 20 dBm may be achieved. All 3 ports of the mixer are
designed to work up to 1.8 GHz. The mixer has a 50 n
single-ended RF input and IF output buffer amplifier. The
linear gain of the mixer is approximately 7.0 dB with a SSE)
noise figure of 16 dB.
Current Regulation/Enable
Temperature compensating voltage independent current
regulators are controlled by the the enable function in which
"high" powers up the IC.
Local Oscillator
It requires an external local oscillator source at -10 dBm
input level to maximize the mixer gain.
Low Noise Amplifier (LNA)
The LNA is internally biased at low supply current
(approximately 2.0 mA emitter current) for optimal noise
PIN FUNCTION DESCRIPTION
II
14 Pin
20 Pin
SOIC
TQFP
Symbol
4
6
RFin
Equivalent Internal Circuit
(20 Pin TQFP)
I
I
I
I
I
6I
RFOUI
2,3
4,5
VCC
RFin
2,3,7
1,5
VEE
2,3,7
RFlnput
The input is the base of an NPN low noise amplifier.
Minimum extemal matching is required to optimize the
Input return loss and gain.
Vref1
VCC - Positive Supply Voltage
Two Vec pins are provided for the Local Oscillator and LO
Buffer Amplifier. The operating supply voltage range is
from 2.7 Vdc to 6.5 Vdc. In the PCB layout, the VCC trace
must be kept as wide as feasible to minimize inductive
reactances along the trace. VCC should be decoupled to
VEE at the IC pin as shown in the component placement
view.
I
I
I
VEE - Negative Supply
VEE pin is taken to an ample dc ground plane through a
low impedance path. The path should be kept as short as
possible. A two sided PCB Is Implemented so that ground
returns can be easily made through via holes.
andS
14
7
RFOutput
The output is from the collector of the LNA. As shown in
the 926 MHz application receiver the output is conjugately
matched with a shunt L, and series Land C network.
RFout
11
LO
I
I
I
I
I
1d
LO
8-228
Functional DeecrlptionlExternal
Circuit Requlremente
I
I
I
I
I
I
I
Vref3
Local Oscillator Input
50 (} single-ended buffered LO input.
33
1.
1.
1
33
.~
.=
MOTOROLA ANALOG IC DEVICE DATA
MC13141
PIN FUNCTION DESCRIPTION (continued)
14 Pin
SOIC
20 Pin
TQFP
5,6
9,10,
12,14
Equivalent Internal Circuit
(20 Pin TQFP)
Symbol
13
VEE - Negative Supply
These pins are VEE supply for the IF and La. In the
application PC board these pins are tied to a common
VEE trace with other VEE pins.
VEE
Vj:e
IF
2:
~~
i
13
8
Functional De.crlptlon/External
Circuit Requirement.
Vrefj!'OVbS
800
IF
IF Output
The IF Is a 800 n slngle-ended output which must be
externally matched to 50 n for optimal performance.
J~
9,10,
12,14
~ VEE
10
11
16
17
RFm
Mix Lin
Cont
I
I
I
I
I
I
I
"
"
~VEE
161
RFm I
I
"
",Ir
!
Mix Un
eont I
13
lB,19
20
I
I
I
I
I
I
I
VEE
I
I
I
EN
20
EN
!
I
I
I
I
¥4
~
171
12
Mixer RF Input
The mixer Input Impedance Is broadband 50 n for
applications up to 1.B GHz. It easily Interfaces with a RF
ceramic filter as shown In the application schematic. The
pin dc bias Is set at 1.0 Vbe.
Vee
33
~Il-
<
",~
~l
~~
'y-
n
VEE - Negative Supply
These pins are VEE supply for the mixer input.
400 I1A
~
~ee
33
~
,Ir
Mixer Linearity Control
The mixer linearity control circuit accepts approximately
oto 2.3 mA control current to set the dynamic range of the
mixer. An Input Third Order Intercept Point, IiP3 of
20 dBm may be achieved at 2.3 mA of control current
(approximately 7.0 mA of additional supply current). The
pin dc bias Is set at 2.0 Vbe.
~
Enable
The device Is enabled by pulling up to VCC or greater than
2.0Vbe.
+
2.0Vbe _
~
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The PC board accommodates ali SMT components on the
circuitside (see Circuit Side Component Placement View).
This evaluation board will be discussed and referenced in
this section.
MOTOROLA ANALOG IC DEVICE DATA
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to use
components from various manufacturers and coil types. The
circuit side placement view is illustrated for the components
specified In the application circuit. The application circuit
schematic specifies particular components that were used to
achieve the results given and specified in the tables but
alternate components of the same Q and value should give
similar results.
8-229
I
II
MC13141
Figure 1. MC13141 01 Application Circuit (881.5 MHZ)
Vee
881.5 MHz
AF
16 P
>--fi---i
I
Inpui
~
SMA
100~11~HZ
798.5 MHz
LO Input
)>--t9-+-----I) 1------1
.1
.±
r
100p
SMA
in n
10P
I
Output
':'
NOTE: '50 £1 Mlcrostrip Transmission Line; length shown in Figure 2.
Figure 2. Circuit Side Component Placement View
MC13141D1 Rev A
•
NOTES: 881.5 MHz SAW filter in the ceramic surface mount package Is available from several sources: Siemens part # B39881-84608-Z010 Is an example.
Other supplie~ include Toko and Murata.
The PCB accommodates ceramic dielectric liners for applications in Cellular. DECT, PHS and ISM bands at 902-928 and 2.4-2.5 GHz. Toko makes a
lull line-up covering th~ ,above bands.
The PCB may be used without an image flijer; ac couple the LNA to the mixer. Traces are provided on the PCB to evaluate the LNA and mixer
separately. The component placement view shows extemal circuit components used in the 881.5 MHz application circulI. It is necessary to cut a section
in the trace before placing the 0.9 pF capacitor. Capac~ors should be 0805 size; the 6.8 nH inductor is a Toko type LL2012.
8-230
MOTOROLA ANALOG IC OEVICE DATA
MC13141
Figure 3. MC13141 D Application Circuit (881.5)
Vee
881.SMHz
RFlnput
>~
16pr----,
)
SMA
798.5 MHz
LOlnput
>
1000 P
-=
470 nH SMA
83.161 MHz
~IFOUtput
~
-i
SMA
NOTE:
lOp
::t: .
·500 Microstrip Transmission Line; length shown in Figure 4.
Figure 4. Circuit Side Component Placement View
NOTES: BBI.S MHz SAW lilter in the ceramic surface mount package is available lrom several sources: Siemens part # B39BBI-B460B-ZOI 0 is an example.
Other suppliers include Taka and Murata.
The PCB accommodates ceramic dielectric lilters lor applications in Cellular, DECT, PHS and ISM bands at 902-92B and 2.4-2.5 GHz. Taka makes a
lull line-up cQvering the above bands.
The PCB may be used without an image lilter; ac couple the LNA to the mixer. Traces are provided on the PCB to evaluate the LNA and mixer
separately. The component placement view shows external circuit components used in the 881.5 MHz application circuit. It is necessary to cut a section
in the trace belore placing the 0.9 pF capacttor. Capacitors shOUld be 0805 size; the 6.B nH inductor is a Taka type LL2012.
MOTOROLA ANALOG IC DEVICE DATA
8-231
MC13141
Input Matching/Components
where:
F1 = the Noise Factor of the MC13142 LNA
G1 = the Gain of the LNA
F2 = the Noise factor of the RF Ceramic Filter
G2 = the Gain of the Ceramic Filter
F3 = the Noise factor of the Mixer
It is desirable to use a RF ceramic or SAW filter before
the mixer to provide image frequency rejection. The filter is
selected based on cost, size and performance tradeoffs.
Typical RF filters have 3.0 to 5.0 dB insertion loss. The PC
board layout accommodates both ceramic and SAW RF
filters which are offered by various suppliers such as
Siemens, Toko and Murata. Interface matching between the
LNA, RF filter and the mixer will be required. The interface
matching networks shown in the application circuit are
designed for 50 Q interfaces.
The LNA is conjugately matched to 50 g input and output
at 3.0 Vdc V CC. 17 dB gain and 1.8 dB noise figure is
typical at 881.5 MHz. The mixer measures 7.0 dB gain and
16 dB noise figure as shown in the application circuil.
Typical insertion loss of the Siemens SAW filter is 3.0 dB.
Note: the above terms are defined as linear relationships
and are related to the log form for gain and noise figure by the
following:
F = Log -1 [(NF in dB)/10] and similarly
G = Log -1 [(Gain in dB)/10]
Calculating in terms of gain and noise factor yields the
following:
F1 = 1.51 ; G1 = 50.11
F2=1.99 ; G2=0.5
F3= 39.8
System Noise Considerations
The block diagram shows the cascaded noise stages of
the MC13141 in the front-end receiver subsystem; it
represents the application circuit. In the cascaded noise
analysis the system noise equation is:
Thus, substituting in the equation for subsystem noise
factor:
Fsubsystem = 3.08 ; NFsubsystem = 4.9 dB
Overall Subsystem Gain = 21 dB
Fsystem = F1 + [{F2 -1)/G1] + [(F3-1)] / [(G1)(G2)]
Figure 5. Front-End Subsystem Block Diagram for Noise Analysis
II
fRF = 881.5 MHz
Noise
Source
G1=17dB
NF1 = 1.8dB
Seimens
Saw Filter
NF
Meter
G2=-3.0dB
NF2 =3.0 dB
IF Output
flF = 83.16 MHz
fLo = 798.339 MHz
I
G~s=21 dB
NFsys = 4:9 dB
8-232
MOTOROLA ANALOG IC DEVICE DATA
MC13141
Figure 6. Circuit Side View
MC13141D1 Rev A
LNA
Output
Mixer
Input
IF
Output
Gnd
g,
••••
LNA'"
Input'"
•
II
LO
Input
NOTES: Critical dimensions are 50 mil centers lead to lead in 80-8 footprint.
Also line widths to labeled ports excluding VCC are 50 mil (0.050 inch).
FR4 PCB, 1/32 inch.
Figure 7. MC13141D1 Rev A -Ground Side View
NOTE:
FR4 PCB, 1/32 inch.
MOTOROLA ANALOG IC DEVICE DATA
8-233
MC13141
Figure 8. Circuit Side View
IF
Output
Vee
NOTES: CrHical dimensions are 50 mil centers lead to lead in 50-14 footprint.
Also line widths to labeled ports excluding VCC are 50 mil (0.050 inch).
FR4 PCB, 1/32 inch.
Figure 9. Ground Side View
8-234
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13142
Product Preview
Low Power DC - 1.8 GHz
LNA, Mixer and VCO
The MC13142 is intended to be used as a first amplifier, voltage controlled
oscillator and down converter for RF applications. It features wide band
operation, low noise, high gain and high linearity while maintaining low
current consumption. The circuit consists of a Low Noise Amplifier (LNA), a
Voltage Controlled Oscillator (VCO), a buffered oscillator output, a mixer, an
Intermediate Frequency amplifier (IFamp) and a dc control section. The wide
mixer IF bandwidth allows this part also to be used as an up converter and
exciter amplifier.
LOW POWER DC - 1.8 GHz
LNA, MIXER and VCO
SEMICONDUCTOR
TECHNICAL DATA
• Wide RF Bandwidth: DC-1.8 GHz
• Wide LO Bandwidth: DC-1.8 GHz
• Wide IF Bandwidth: DC-1.8 GHz
• Low Power: 13 mA @ VCC
=2.7-6.5 V
• High Mixer Linearity: Pi1.0 dB = +3.0 dBm
• Linearity Adjustment Increases IP3in Up to +20 dBm
o SUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
• Single-Ended 50 n Mixer Input
• Double Balanced Mixer Operation
• Open Collector Mixer Output
• Single Transistor Oscillator with Collector, Base and Emitter Pinned Out
• Buffered Oscillator Output
•
• Mixer and Oscillator Can be Enabled Independently in TQFP-20
Package Only
20
ORDERING INFORMATION
Operating
Temperature Range
Device
FTBSUFFIX
PLASTIC PACKAGE
CASE 976
(ThinOFP)
Package
MC131420
S0-16
TA = -40° to +85°C
MC13142FTB
1
TOFP-20
PIN CONNECTIONS
TOFP-20
50-16
~
EN
RFOUI
RFin
Vcc
vEE
w
Mix Lin Coni
RFtn
OseE
RFm
VEE
OseB
vEE
-s
u...0
8
:5_
.~a
:z
w
a: > :::;;<.>
<.>
<.>
""
~
>
:0
<.>
<.>
>
w
w
>
This device contains 176 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
8-235
MC13142
MAXIMUM RATINGS (TA - 25°C unless otherwise noted)
Symbol
Value
Unit
Power Suppiy Voltage
Rating
VCC
7.0 (max)
Vdc
Operating Supply Voltage Range
VCC
2.7-6.5
Vdc
NOTE: ESO dala available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 3.0 V, TA = 25°C, LOin = -10 dBm @ 950 MHz, IF @ 50 MHz.)
Characteristic
Symbol
Supply Current (Power Down)
ICC
Supply Current (Power Up)
ICC
Amplifier Gain (50 0 Insertion Gain)
S21
Amplifier Reverse Isolation
S12
Amplifier Input Match
~in
Typ
Max
Unit
-
100
13.5
-
mA
pA
12
-
dB
-33
-
dB
rinamp
-
-10
-
dB
rout amp
-
-15
Amplifier 1 .0 dB Gain Compression
PirL1.0dB
-
-15
-
dBm
Amplifier Input Third Order Intercept
IP3in
-5.0
-
dBm
Amplifier Output Match
Amplifier Gain @ N.F.
GNF
Mixer Voltage Conversion Gain (Rp = RL = 800 0)
VGC
Mixer Power Conversion Gain (Rp = RL = 800 0)
PGC
-
rinM
-
-20
-
3.0
Amplifier Noise Figure (Application Circuit)
Mixer Input Match
Mixer SSB Noise Figure
NF
NFSSBM
Mixer 1.0 dB Gain Compression
PirL1.0dBM
Mixer Input Third Order Intercept
IP31nM
Oscillator Buffer Drive (50 0)
PVCO
Oscillator Phase Noise @ 25 kHz Offset
RFin Feedthrough to RFm
RFoul Feedthrough to RFm
LO Feedthrough to IF
N
PRFin-RFm
PRFout-RFm
PLD-IF
LO Feedthrough to RFin
PLD-RFin
LO Feedthrough to RFm
PLD-RFm
Mixer RF Feedthrough to IF
PRFm-IF
Mixer RF Feedthrough to RFin
8-236
PRFm-RFin
1.8
17
9.0
-3.0
12
-1.0
-
dB
dB
dB
dB
dB
dB
dB
-
dBm
dBm
-
-16
-90
-
dBcJHz
-
-35
dB
-
-35
-
-25
-
-25
-
-35
-35
-35
dBm
dB
dBm
dBm
dBm
dB
dB
MOTOROLA ANALOG IC DEVICE DATA
MC13142
CIRCUIT DESCRIPTION
General
The MC13142 is a low power LNA, double-balanced
Mixer, and VCO. This device is designated for use as the
frontend section in analog and digital FM systems such as
Digital European Cordless Telephone (DECT), PHS, PCS,
Cellular, UHF and 800 MHz Special Mobile Radio (SMR),
UHF Family Radio Services and 902 to 928 MHz cordless
telephones. It features a mixer linearity control to preset or
auto program the mixer dynamic range, an enable function
and a wideband IF so the IC may be used either as a down
converter or an up converter. Further details are covered in
the Pin by Pin Description which shows the equivalent
internal circuit and external circuit requirements.
Current Regulation/Enable
Temperature compensating voltage independent current
regulators are controlled by the enable function in which
"high" powers up the IC.
Low Noise Amplifier (LNA)
The LNA is internally biased at low supply current
(approximately 2.0 mA emitter current) for optimal noise
figure and gain. The LNA output is biased internally with a
600 n resistor to VCC. Input and output matching may be
achieved at various frequencies using few external
components. Matching the LNA for Maximum stable gain
MOTOROLA ANALOG IC DEVICE DATA
(MSG) yields noise performance within a few tenths of a dB
of the minimum noise figure.
Mixer
The mixer is a double-balanced four quadrant multiplier
biased class AB allowing for programmable linearity control
via an external current source. An input third order intercept
point of 20 dBm may be achieved. All 3 ports of the mixer are
designed to work up to 1.8 GHz. The mixer has a 50 n
single--ended RF input and open collector differential IF
outputs. An on-board Local Oscillator transistor has the
emitter, base and collector pinned out to implement a low
phase noise VCO in various configurations. Additionally, a
buffered LO output is provided for operation with a frequency
synthesizer. The linear gain of the mixer is approximately
o dB with a SSB noise figure of 12 dB in the IF output circuit
configuration shown in the application example.
Local Oscillator
The on-chip transistor operates with coaxial transmission
line or LC resonant elements to over 2.0 GHz. Biasing is
done with a temperature compensated current source in the
emitter and a collector to base internal resistor of 7.6 kn;
however, an RFC from VCC to base is recommended. The
application circuit shows a voltage controlled Clapp oscillator
operating at center frequency of 975 MHz.
8-237
MC13142 .
PIN FUNCTION DESCRIPTION
'Pin
16 Pin
SOIC
20 Pin
TQFP
4
5
Equivalent Internal Circuit
(20 Pin TQFP)
Symbol
Description
EN
EOsc
Enable, E Osc
In S0-16, both enables, (for the Oscillator/LO
Buffer and LNAlMixer) are bonded to Pin 1. In the
TQFP, two pins are provided, Pin S, E Osc enables
the OSCillator and buffer while Pin 4, EN enables
the lNAlMixer.
Enable by pulling up to Vec or to greater than
2.0VBE·
2
6
RFin
600
Vref2
RFOUII
3
7,8·
VEE
6
II
RF Input
The input is the base of an NPN low noise
amplifier. Minimum external matching is required to
optimize the input return loss and gain.
Vee
1
1
31
VEE - Negative Supply
VEE pin is taken to an ample dc ground plane
through a low impedance path. The path should be
kept as short as possible. A two sided PCB is
implemented so that ground returns can be easily
made through via holes.
1
1
1
RFin 1
71
16
3
RFoUI
'E~
RF Output
The output is from the collector of the lNA; it is
internally biased with a 600 Q resistor to Vcc. As
shown in the 926 MHz application receiver the
output is conjugately matched with a shunt L, and
series land C network.
81
VEE 1_
1 4
S
6
9
10
11
OscE
OscB
OscC
+rnA
1.5
11
6
8
12
14
Supply Voltage (VCC)
Two VCC pins are provided for the Local Oscillator
and LO Buffer Amplifier. The operating supply
voltage range is from 2.7 Vdc to 6.S Vdc. In the
PCB layout, the VCC trace must be kept as wide as
feasible to minimize inductive reactances along the
trace. VCC should be decoupled to VEE at the IC
pin as shown in the component placement view.
VCC
VCC
1 Vee
13
7
13
I
I
FO
LOBuff
rnA
Vee
8-238
On-Board VCO Transistor
The transistor has the emitter, base and collector +
V CC pins available. Internal biasing which is
compensated for stability over temperature is
provided. It is recommended that the base pin is
pulled up to Vec through an RFC chosen for the
particular oscillator center frequency. The
application circuit shows a modified Colpitts or
Clapp oscillator configuration and its design is
discussed in detail in the application section.
Local Oscillator Buffer
This is a buffered output providing -16 dBm
(SO Q termination) to drive the fin pin of a PLL
synthesizer. Impedance matching to the
synthesizer may be necessary to deliver the
optimal signal and to improve the phase noise
performance of the VCO.
MOTOROLA ANALOG IC DEVICE DATA
MC13142
PIN FUNCTION DESCRIPTION (continued)
Pin
16 Pin
SOIC
20 Pin
TQFP
9,12
15, 18, 19
10,11
16,17
Equivalent Internal Circuit
(20 Pin TQFP)
Symbol
VEE
I Vee
I
IA
I ~
IF-,IF+
17
IF+
13
20
Vee
~
II ~
T
IF Output
The IF is a differential open collector configuration
which designed to use over a wide frequency range
for up conversion as well as down conversion.
Differential to single-ended circuit configuration
and matching options are discussed in the
application section. 6.0 dB of additional Mixer gain
can be achieved by conjugately matching at the
desired IF frequency.
VTl
Mixer RF Input
The mixer input impedance is broadband 50 n for
applications up to 1.8 GHz. It easily interfaces with
a RF ceramic filter as shown in the application
schematic.
J
16
IF-
I
15 ~
-=-
:18~
I
I
I
I
Description
VEE, Negative Supply
These pins are VEE supply for the mixer IF output.
In the application PC board these pins are tied to a
common VEE trace wnh other VEE pins.
VEE
RFm
Vee
,
,
-=-
20
14
1
Mix Lin
Cont
+
33
VEE
RFm
1
MixLin
eont
MOTOROLA ANALOG IC DEVICE DATA
J
i
I
I
I
I
I
I
I
I
I
?
~
-=-
33
Mixer Linearity Control
The mixer linearity control circuit accepts
approximately 0 to 2.3 mA control current to set
the dynamic range of the mixer. An Input Third
Order Intercept Point, IIP3 of 20 dBm may be
achieved at 2.3 mA of control current
(approximately 7.0 mA of additional supply
current).
+
400~
8-239
MC13142
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The PC board accommodates all SMT components on the
circuit side (see Circuit Side Component Placement View).
This evaluation board will be discussell and referenced in
this section.
Component Selection
The evaluation PC board is designed to accommodate
specific components. while also being versatile enough to
use components from various manufacturers. The circuit
side placement view is illustrated for the components
specified in the application circuit. The application circuit
schematic specifies particular components that were used to
achieve the results given and specified in the tables but
alternate components of the sameC and value should give
equivalent results.
Figure 1. Application Circuit
(926.5 MHz)
Vcc
PC RotarySW
51
.-.
VControl
3.6
PI
-=-
1 0 m r--------:---tt---- 15
af'
~ ~
-6.0 ~
c3
11
20
"
RF FREQUENCY (GHz)
MOTOROLA ANALOG IC DEVICE DATA
'-..
2.0
7.0
~
Vs= 5.0Vdc
fRF = 900 MHz
fLQ = 950 MHz
10
~V
-6.0
2.5
2.0
1/
~
~
i--'
Ilmj)
10-3
rnr
0
-5.0
"'
1en
IIP3(dBm
c3 If 5.0
'"~
4.0
10
Figure 7. IIP3, Gain, Supply Current
versus Mixer Linearity Control Current
.........
6.0
o
0
Figure 6. Noise Figure and Gain
versus RF Frequency
~
o
= 5.0 Vdc
fRF= 900 MHz
fLQ =950 MHz
PLQ=OdBm
Test Circuit
V
RF INPUT POWER (dBm)
$ 13.5
11.5
'r-..
v
V"' ~/ f--
RF INPUT FREQUENCY (GHz)
-4.0
,r
8.0
-8.5
-30
2.5
2.0
15.5
10.5
~
-3.2
-10
10-5
10-4
10-2
MIXER LINEARITY CONTROL CURRENT, IMx Lin Cont (A)
8-247
MC13143
CIRCUIT DESCRIPTION
General
The MC13143 is a double-balanced Mixer. This device is
designated for use as the frontend section in analog and
digital FM systems such as Wireless Local Area Network
(LAN), Digital European Cordless Telephone (DECT), PHS,
PCS, GPS, Cellular, UHF and 800 MHz Special Mobile
Radio (SMR), UHF Family Radio Services and 902 to
928 MHz cordless telephones. It features a mixer linearity
control to preset or auto program the mixer dynamic range,
an enable function and a wideband IF so the IC may be
used either as a down converter or an up converter.
Current Regulation
Temperature compensating voltage independent current
regulators provide typical supply current at 1.0 mA with no
mixer linearity control current.
Mixer
The mixer is a unique and patented double-balanced four
quadrant multiplier biased class AB allowing for
programmable linearity control via an external current
source. An input third order intercept point of 20 dBm may be
achieved. All 3 ports of the mixer are deSigned to work up to
2.4 GHz. The mixer has a 50 n single-ended RF input and
open collector differential IF outputs (see Internal Circuit
Schematic for details). The linear gain of the mixer is
approximately -5.0 dB with a SSB noise figure of 12 dB.
Local Oscillator
The local oscillator has differential input configuration that
requires typically -10 dBm input from an external source to
achieve the optimal mixer gain.
Figure 8. MC13143 Internal Circuit·
IF-
6
5
Vee
IF+
2
4
La-
3
LO+
Vref1
Vee
33
8
Vee
MxLin
ConI
NOTE: .• The MC13143 uses a unique and patented clrcu~ topology.
8-248
MOTOROLA ANALOG IC DEVICE DATA
MC13143
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The PC board is laid out to accommodate all SMT
components on the circuit side (see Circuit Side Component
Placement View).
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to
use components from various manufacturers. The circuit side
placement view is illustrated for the components specified in
the application circuit. The Component Placement View
specifies particular components that were used to achieve
the results shown in the typical curves and tables.
Mixer Input
The mixer input impedance is broadband 50 Q for
applications up to 2.4 GHz. It easily interfaces with a RF
ceramic filter as shown in the application schematic.
Mixer Linearity Control
The mixer linearity control circuit accepts approximately
o to 2.3 mA control current. An Input Third Order Intercept
Point, IIP3 of 20 dBm may be achieved at 2.3 mA of control
current (approximately 7.0 mA of additional supply current).
Local Oscillator Inputs
The differential LO inputs are internally biased at
VCC - 1.0 VeE; this is suitable for high voltage and high gain
operation.
For low voltage operation, the inputs are taken to VCC
through 51 Q.
IF Output
The IF is a differential open collector configuration which is
designed to use over a wide frequency range for up
conversion as well as down conversion.
Input/Output Matching
It is desirable to use a RF ceramic or SAW filter before the
mixer to provide image frequency rejection. The filter is
selected based on cost, size and performance tradeoffs.
Typical RF filters have 3.0 to 5.0 dB insertion loss. The PC
board layout accommodates both ceramic and SAW RF
filters which are offered by various suppliers such as
Siemens, Toko and Murata.
MOTOROLA ANALOG IC DEVICE DATA
Interface matching between the RF input, RF filter and the
mixer will be required. The interface matching networks
shown in the application circuit are designed for 50 Q
interfaces.
Differential to single-ended circuit configuration is shown
in the test circuit. 6.0 dB of additional mixer gain can be
achieved by conjugately matching the output of the
MiniCircuits transformer to 50 Q at the desired IF frequency.
With narrowband IF output matching the mixer performance
is 3.0 dB gain and 12 dB noise figure (see Narrowband 49
and 83 MHz IF Output Matching Options). Typical insertion
loss of the Toko ceramic filter is 3.0 dB. Thus, the overall gain
of the circuit is 0 dB with a 15 dB noise figure.
Figure 9. Narrowband IF Output Matching with
16:1 Z Transformer and LC Network
SMA
I---OH......-(
I
Mixer
RFlnput
SMA
!
II
SMA
(Mixer
RF Input
83.16 MHz
E--9-< IF
10n I
Output
9.2k
8-249
MC13143
Figure 10. Circuit Side Component Placement View
MC13143D
Rev A
II
NOTES: 926.5 MHz preselect dielectric filter is Taka part # 4DFA-926A 10; the 4DFA (2 and 3 pole SMD type) filters are available
for applications in cellular and GSM, GPS, DECT, PHS, PCS and ISM bands at 902-928 MHz, 1.8-1.9 GHz at 2.4-2.5 GHz.
The PCB also accommodates a suriace mount RF SAW filter in an eight or six pin ceramic package for the cellular base and
handset frequencies. Recommended manufacturers are Siemens and Murata.
The PCB may also be used w~hout a preselector fitter; AC coupled to the mixer as shown in the test circuit schematic.
All other external circuit components shown in the PCB layout above are the same as used in the test circuit schematic.
16:1 broadband impedance transformer is mini circu~s part nX16-R3T; it is in the leadless surface mount "TX" package. For a
more selective narrowband match, a low pass filter may be used after the transformer. The PCB is designed to accommodate
lump inductors and capacitors in more selective narrowband matching of the mixer differential outputs to a single...,nded output
at a given IF frequency.
The local oscillator may also be driven in a differential configuration using a coaxial transformer. Recommended sources are the
Toko Balun transformers type B4F, B5FL and B5F (SMD component).
8-250
MOTOROLA ANALOG IC DEVICE DATA
MC13143
Figure 11. Circuit Side View
MC13143D
Rev A
NOTES: Crnical dimensions are 50 mil centers lead to lead in 80--8 footprint.
II
Also line widths to labeled ports excluding VCC are 50 mil.
Figure 12. Ground Side View
MOTOROLA ANALOG IC DEVICE DATA
8-251
®
MOTOROLA.
MC13144
Product Preview
VHF - 2.0 GHz Low
Noise Amplifier with
Programmable Bias
The MC13144 is designed in the Motorola High Frequency Bipolar
MOSIAC yrM wafer process to provide excellent.performance in analog and
digital communication systems. It inclu<;les a cascaded LNA usable up to
2.0 GHz and at 1.B Vdc, with 2 bit digital programming of the LNA bias.
Targeted applications are in the UHF Family Radio Services, UHF and
BOO MHz Special Mobile Radio, BOO MHz Cellular and GSM,. PCS, DECT
and PHS at 1.B to 2.0 GHz and Cordless Telephones in the 902 to 92B MHz
band covered by FCC Title 47; Part 15. The MC13144 offers the following
features:
VHF - 2.0 GHz LOW
NOISE AMPLIFIER WITH
PROGRAMMABLE BIAS
SEMICONDUCTOR
TECHNICAL DATA
• 17 dB Gain at 900 MHz
• 1.4 dB Noise Figure at 900 MHz
• 1.0 dB Compression Point of -7.0 dBm; Input Third Order Intercept
Point of -5.0 dBm
• Low Operating Supply Voltage (1.B to 6.0 Vdc)
• Programmable Bias with Enable 1 and Enable 2
o SUFFIX
PLASTIC PACKAGE
CASE 751
(SQ-8)
• Enable 1 and Enable 2 Programmed High for Optimal Noise Figure and
Gain Associated with NF
• Can Override Enable and Externally Program In Up to 15 rnA
Typical Application as 900 MHz Low Noise Amplifier
En1
PIN CONNECTIONS AND
FUNCTIONAL BLOCK DIAGRAM
En2
1'~RF
,.----
8.2nH
RF
Output
e1.
MOTOROLA ANALOG IC DEVICE DATA
8-255
MC13144
Figure 3. Circuit Side Component Placement View
Figure 4. Circuit Side View
NOTES: Critical dimensions are 50 Mil centers lead to lead in 50-8 footprint.
Also line widths to labeled ports excluding VCC, E1 and E2 are 50 Mil (0.050 inch).
FR4 PCB, 1/32 inch.
8-256
MOTOROLA ANALOG IC DEVICE DATA
MC13144
Figure 5. Ground Side View
LNA in
[!] VCC
[!]
El
[!]
•
•
• •••
•
•• ••• • • •
•
• •
•
[!]
•
••
• ••••
LNA Out
[!]
E2
MC13144D Rev 0
NOTES: FR4 PCB, 1/32 inch.
II
MOTOROLA ANALOG IC DEVICE DATA
8-257
®
MOTOROLA
[
MC13150
Narrowband FMeoilless
Detector IF Subsystem·
NARROWBAND FM COILLESS
DETECTOR IF SUBSYSTEM
The MC13150 is a narrowband FM IF subsystem targeted at cellular and
other analog applications. Excellent high .frequency performance is
achieved, with low cost, through use of Motorola's MOSAIC 1.5™ RF bipolar
process. The MC13150 has an onboard Colpitts VCO for Crystal controlle~
second LO in dual conversion receivers. The mixer is a double balanced
configuration with excellent third order intercept. It is useful to beyond
200 MHz. The IF amplifier is split to accommodate two low cost cascaded
filters. RSSI output is derived by summing the output of both IF sections. The
quadrature detector is a unique design eliminating the comientional tunable
quadrature coil.
Applications for the MC13150 include cellular, CT-1 900 MHz cordless
telephone, data links and other radio systems utilizing narrowband FM
modulation.
• Linear Coilless Detector
• Adjustable Demodulator Bandwidth
• 2.5 to 6.0 Vdc Operation
• Low Drain Current: < 2.0 rnA
• Typical Sensitivity of 2.0 IlV for 12 dB SINAD
• IIP3, Input Third Order Intercept Point of 0 dBm
• RSSI Range of Greater Than 100 dB
• Internal 1.4 kn Terminations for 455 kHz Filters
• Split IF for Improved Filtering and Extended RSSI Range
FOR CELLULAR AND
ANALOG APPLICATIONS
SEMICONDUCTOR
TECHNICAL DATA
24
FTASUFFIX
PLASTIC PACKAGE
CASE 977
(ThlnQFP)
ORDERING INFORMATION
Operating
Temperature Range
Device
FTBSUFFIX
PLASTIC PACKAGE
CASE 873
(ThinQFP)
Package
TQFP-24
MC13150FTA
TA = -40 ° to +85°C
MC13150FTB
TQFP-32
PIN CONNECTIONS
TQFP-24
.E
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W
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9
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8-258
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MOTOROLA ANALOG IC DEVICE DATA
MC13150
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
2,9
Vcc(max)
6.5
Vdc
Junction Temperature
-
TJmax
+150
'c
Storage Temperature Range
-
Tstg
-65to+150
'c
NOTE:
Pin
1. Devices should not be operated at or outside these values. The "Recommended Operating
Limits" provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Pin
TA = 25'C
- 40'C $ TA $ 85'C
2,9
21,31
Symbol
Value
Unit
VCC
VEE
2.5 to 6.0
0
Vdc
MHz
(See Figure 22)
Input Frequency
32
Ambient Temperature Range
Input Signal Level
32
fin
10 to 500
TA
-40to+85
'c
Vin
0
dBm
DC ELECTRICAL CHARACTERISTICS (TA = 25'C, VCC1 = VCC2 = 3.0 Vdc, No Input Signa!.)
Characteristics
Total Drain Current
(See Figure 2)
Condition
Pin
Symbol
Min
Typ
Max
Unit
Vs = 3.0Vdc
2+9
ITOTAL
-
1.7
3.0
rnA
-
2+9
-
-
40
-
nA
Supply Current, Power Down
(See Figure 3)
AC ELECTRICAL CHARACTERISTICS (TA = 25'C, Vs = 3.0 Vdc, fRF = 50 MHz, fLO = 50.455 MHz,
LO Level = -10 dBm see Figure 1 Test Circuit' unless otherwise specified.)
Condition
Pin
Symbol
Min
Typ
Max
Unit
fmod = 1.0 kHz;
fdev = ± 5.0 kHz
32
-
-
-100
-
dBm
RSSI Dynamic Range
(See Figure 7)
-
25
-
-
100
-
dB
Input 1.0 dB Compression Point
Input 3rd Order Intercept Point
(See Figure 18)
-
-
1.0dBC. Pt.
IIP3
-
-11
-1.0
-
dBm
Measured with No IF Filters
-
I:!.BWadj
-
26
-
kHzI/lA
Pin = - 30 dBm;
PLO=-10dBm
32
-
-
10
-
dB
Single-Ended
32
-
-
200
-
g
-
1
-
-
1.5
-
kg
!lA/dB
Characteristics
12 dB SINAD Sensitivity
(See Figure 15)
Coilless Detector Bandwidth
Adjust (See Figure 11)
MIXER
Conversion Voltage Gain
(See Figure 5)
Mixer Input Impedance
Mixer Output Impedance
LOCAL OSCILLATOR
LO Emitter Current
(See Figure 26)
IF & LIMITING AMPLIFIERS SECTION
IF and Limiter RSSI Slope
Figure 7
25
-
-
0.4
-
IF Gain
Figure 8
4,8
-
-
42
-
dB
IF Input & Output Impedance
-
4,8
-
-
1.5
-
kn
Limiter Input Impedance
-
10
-
-
1.5
-
kn
Limiter Gain
-
-
-
-
96
-
dB
• Figure 1 Test Circuit uses positive (VCC) Ground.
MOTOROLA ANALOG IC DEVICE DATA
8-259
II
MC13150
AC ELECTRICAL CHARACTERISTICS (continued) (TA = 25'C, Vs = 3.0 Vdc, fRF = 50 MHz, flo = 50.455 MHz,
La Level = -10 dBm, see Figure 1 Test Circuit', unless otherwise specified.)
Characteristics
Condition
Pin
Frequency Adjust Current
Figure 9,
flF = 455 kHz
16
-
41
49
56
J.LA
Frequency Adjust Voltage
Figure 10,
!IF= 455 kHz
16
-
600
650
700
mVdc
Bandwidth Adjust Voltage
Figure 12,
115= 1.0J.LA
15
-
-
570
-
mVdc
-
23
-
-
1.36
-
Vdc
!dev = ±3.0 kHz
23
-
85
122
175
mVrms
DETECTOR
Detector DC Output Voijage
(See Figure 25)
Recovered Audio Voltage
• Figure 1 Test Circuit uses positive (VCC) Ground.
Figure 1. Test Circuit
,------------QEnable
r---------QRSSI
Mixer~220n
RSSI
1-----<0 Buffer
Out
1-----<1-_-0 Detector
Output
1.5k
RL
100 k
:~~on-=49.9
220n
V1B-V17 = 0;
'IF= 455 kHz
This device contains 292 active transistors.
8-260
MOTOROLA ANALOG IC DEVICE DATA
MC13150
MC13150 CIRCUIT DESCRIPTION
General
The MC13150 is a very low power single conversion
narrowband FM receiver incorporating a split IF. This device
is designated for use as the backend in analog narrowband
FM systems such as cellular, 900 MHz cordless phones and
narrowband data links with data rates up to 9.6 k baud. It
contains a mixer, oscillator, extended range received signal
strength indicator (RSSI), RSSI buffer, IF amplifier, limiting IF,
a unique coilless quadrature detector and a device enable
function (see Package Pin Outs/Block Diagram).
Low Current Operation
The MC13150 is designed for battery and portable
applications. Supply current is typically 1.7 mAdc at 3.0 Vdc.
Figure 2 shows the supply current versus supply voltage.
Enable
The enable function is provided for battery powered
operation. The enabled pin is pulled down to enable the
regulators. Figure 3 shows the supply current versus enable
voltage, Venable (relative to VCC) needed to enable the
device. Note that the device is fully enabled at VCC -1.3 Vdc.
Figure 4 shows the relationship of enable current, lenable to
enable voltage, Venable.
Mixer
The mixer is a double-balanced four quadrant multiplier
and is designed to work up to 500 MHz. It has a single ended
input. Figure 5 shows the mixer gain and saturated output
response as a function of input signal drive and for -10 dBm
LO drive level. This is measured in the application circuit
shown in Figure 15 in which a single LC matching network is
used. Since the single-ended input impedance of the mixer is
200 Q, an alternate solution uses a 1:4 impedance
transformer to match the mixer to 50 Q input impedance. The
linear voltage gain of the mixer alone is approximately 4.0 dB
(plus an additional 6.0 dB for the transformer). Figure 6
shows the mixer gain versus the LO input level for various
mixer input levels at 50 MHz RF input.
MOTOROLA ANALOG IC DEVICE DATA
The buffered output of the mixer is internally loaded,
resulting in an output impedance of 1.5 kQ.
Local Oscillator
The on--chip transistor operates with crystal and LC
resonant elements up to 220 MHz. Series resonant, overtone
crystals are used to achieve excellent local oscillator stability.
3rd overtone crystals are used through about 65 to 70 MHz.
Operation from 70 MHz up to 200 MHz is feasible using the
on--chip transistor with a 5th or 7th overtone crystal. To
enhance operation using an overtone crystal, the intemal
transistor's bias is increased by adding an extemal resistor
from Pin 29 (in 32 pin OFP package) to VEE to keep the
oscillator on continuously or it may be taken to the enable pin
to shut it off when the receiver is disabled. -10 dBm of local
oscillator drive is needed to adequately drive the mixer
(Figure 6). The oscillator configurations specified above are
described in the application section.
RSSI
The received signal strength indicator (RSSI) output is a
current proportional to the log of the received signal
amplitude. The RSSI current output is derived by summing
the currents from the IF and limiting amplifier stages. An
external resistor at Pin 25 (in 32 pin OFP package) sets the
voltage range or swing of the RSSI output voltage. Linearity
of the RSSI is optimized by using external ceramic bandpass
filters which have an insertion loss of 4.0 dB. The RSSI circuit
is designed to provide 100+ dB of dynamic range with
temperature compensation (see Figures 7 and 23 which
show the RSSI response of the applications circuit).
RSSI Buffer
The RSSI buffer has limitations in what loads it can drive.
It can pull loads well towards the positive and negative
supplies, but has problems pulling the load away from the
supplies. The load should be biased at half supply to
overcome this limitation.
8-261
MC13150
Figure 2. Supply Current
vti!rsus Supply Voltage
2.0
«
.s
I--
.., /
1.6
w
::>
0
$ 10-3
~ 10-4
(
z
a:
a:
10-2
a
a:
1.2
D..
D..
(JJ
iil
TA=25°CI
I
I
I
:::>
!!J 10-9
a:
a:
::>
60
50
40
0
lEI
w
30
'"zw
20
-'
..:
LiJ
-'
'"
..:
z
J!.l
2.5
3.5
4.5
5.5
6.5
7.5
r--
E
'"
r-- r-..
~
\.
~
I--
0
0.8
1.2
-10
!!:
a:
-30
xw
::i" -40
\
1.6
-20
'RF = 50 MHz; fLO = 50.455 MHz
LO Input Level = -10 dBm
(100mVrms)
(Rin = 50 Q; Rout = 1.4 kQ
I
-50
-50
2.0
............
V
-40
-30
-20
I
I
-10
10
VENABLE, ENABLE VOLTAGE (Vdc)
RF INPUT LEVEL (dBm)
Figure 6. Mixer IF Output Level versus
Local Oscillator Input Level
Figure 7. RSSI Output Current
versus Input Signal Level
50
W
I-Z
~ -20
a:
a:
6
>
40
W
:::>
::>
0
I--
I--
I--
D..
::>
-40
0-
I--
30
I
I
I
I
VCC = 3.0 Vdc
f=50MHz
fLO = 50.455 MHz
455 kHz
Ceramic Filter
See Figure 15
a:
u;
(JJ
~ -60
a:
:::;;
10
0
-50
-40
-30
LO DRIVE (dBm)
-20
-10
-
-
-120
./
20
V
./
V
20
::>
0
!!:
8-262
V
V
/"
/
0-
\
0.4
VEE = -3.0 Vdc
10 I- TA = 25°C
:8-'
w
::>
0
-80
-60
1.5
20
VCC=3.0Vdc
. TA = 25°C
«
5
1.3
Figure 5. Mixer IF Output Level versus
RF Input Level
0
'"-'
1.1
Figure 4. Enable Current
versus Enable Voltage
---- -o
0.9
VENABLE, ENABLE VOLTAGE (Vdc)
RF In = 0 dBm
:8-
V
0.7
0.5
20
E
:L
VENABLE, SUPPLY VOLTAGE (Vdc)
10
-10
~~
V
10-10
1.5
70
/'
10-7
& 10-ll
o
!z
w
10-5
~
/
0.4
!!J
~
/
1
D..
0.8
~
D...
D..
:::>
I
I
I
_ VCC=3.0Vdc
TA = 25°C
- VENABLE Measured
Relative to VCC
~ 10-6
~
::>
Figure 3. Supply Current
versus Enable Voltage
,/
,/
/'
V
V
"...
-100
-80
-60
-40
-20
o
SIGNAL INPUT LEVEL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
MC13150
IF Amplifier
The first IF amplifier section is composed of three
differential stages. This section has internal dc feedback and
external input decoupling for improved symmetry and
stability. The total gain of the IF amplifier block is
approximately 42 dB at 455 kHz. Figure 8 shows the gain of
the IF amplifier as a function of the IF frequency.
The fixed internal input impedance is 1.5 kQ; it is designed
for applications where a 455 kHz ceramic filter is used and no
external output matching is necessary since the filter requires
a 1.5 kg source and load impedance.
Overall RSSI linearity is dependent on having total
midband attenuation of 10 dB (4.0 dB insertion loss plus 6.0
dB impedance matching loss) for the filter. The output of the
IF amplifier is buffered and the impedance is 1.5 kg.
Limiter
The limiter section is similar to the IF amplifier section
except that six stages are used. The fixed internal input
impedance is 1.5 kg. The total gain of the limiting amplifier
section is approximately 96 dB. This IF limiting amplifier
section internally drives the quadrature detector section.
Figure 8. IF Amplifier Gain
versus IF Frequency
Figure 9. Fadj Current
versus IF Frequency
50
120
45
ill
:Eo
z
«
(!l
............
40
\
Fadj CURRENT (1lA)
MOTOROLA ANALOG IC DEVICE DATA
100
J
V
'\ r7
0.5
rv
o
400
V
/
"-\
~ 1.0
80
T
~
ID
60
I
VCC = 3.0Vdc
BW ~ 26 kHzlllA
'5"
I'--
20
I
1000
800
t, IF FREQUENCY (kHz)
~
o
600
t, FREQUENCY (MHz)
VCC=3.0Vdc
TA = 25°C
650
800
V
V
V
3.5
(!l
~
,/"'"
40
20
800
'U' 750
,/
a
r- Rin=50Q
Rout = 1.4 kQ
25 I- BW (3.0 dB) = 2.4 MHz
V
60
=>
30
20
0.01
/
80
IZ
\
17
420
440
460
480
500
t, IF FREQUENCY (kHz)
8-263
II
MC13150
Coilless Detector
The quadrature detector is similar to a PLL. There is an
internal oscillator running at the IF frequency and two
detector outputs. One is used to deliver the audio signal and
the other one is filtered and used to tune the oscillator.
The oscillator frequency is set by an external resistor at
the Fadj pin. Figure 9 shows the control current required for a
particular frequency; Figure 10 shows the pin voltage at that
current. From this the value of RF is chosen. For example,
455 kHz would require a current of around 50 IlA. The pin
voltage (Pin 16 in the 32 pin QFP package) is around 655mV
giving a resistor of 13.1 kQ. Choosing 12 kQ as the nearest
standard value gives a current of approximately 55 !lAo The
5.0 IlA difference can be taken up by the tuning resistor, RrThe best nominal frequency for the AFTout pin (Pin 17)
would be half supply. A supply voltage of 3.0 Vdc suggests a
resistor value of (1.5 - 0.655)Vl5!lA = 169 kQ. Choosing
150 kQ would give a tuning current of 3/150 k =20 !lAo From
Figure 9 this would give a tuning range of roughly 10 kHzlllA
or ± 100 kHz which should be adequate.
The bandwidth can be adjusted with the help of Figure 11.
For example, 1.0!lA would give a bandwidth of ± 13 kHz. The
II
10-3
/1
=
So, for example, 150 k and 1.0 IlF give a 3.0 dB point of
4.5 Hz. The recovered audio is set by RL to give roughly
50mV per kHz deviation per 100 k of resistance. The dc level
can be shifted by RS from the nominal 0.68 V by the following
equation:
Detector DC Output = ((RL + RS)/RS) 0.68 Vdc
=
Thus, RS
RL sets the output at 2 x 0.68
RL 2RS sets the output at 3 x 0.68 2.0 V.
=
10
~
I:;
0
a.. -10
V
§
=
= 1.36 V;
-
II
~B=560k
~
VCC=3.0Vdc
RB=1.0M
!§ -20 _ TA=25°C
/
S
is
~c
2.5
=
RrCT = 0.681f3dB.
I.
BWadj VOLTAGE (Vdc)
8-264
=
Figure 13. Demodulator Output
versus Frequency
V
2.3
=
Figure 12. BWadj Current
versus BWadj Voltage
VCC=3.0 Vdc
TA = 25°C
10-7
voltage across the bandwidth resistor, RB from Figure 12
0.56 Vdc for VCC
3.0 Vdc., so
is VCC - 2.44 Vdc
RB 0.56V11.0 !lA 560 kn. Actually the locking range will
be ±13 kHz while the audio bandwidth will be approximately
±S.4 kHz due to an internal filter capacitor. This is verified in
Figure 13. For some applications it may be desirable that the
audio bandwidth is increased; this is done by reducing RB.
Reducing RB widens the detector bandwidth and improves
the distortion at high input levels at the expense of 12 dB
SINAD sensitivity. The low frequency 3.OdB point is set by the
tuning circuit such that the product
2.7
-30 -40 -50
0.1
fRF= 50 MHz
flO = 50.455 MHz
lOlevel=-10dBm
No IF Bandpass Filters
fdev = ±4.0 kHz
~"
T I 1111111
1.0
10
100
f, FREQUENCY (kHz)
MOTOROLA ANALOG IC DEVICE DATA
MC13150
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The center section of the board provides an area for
attaching all SMT components to the circuit side and radial
leaded components to the component ground side (see
Figures 29 and 30). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interface circuitry as a particular application dictates.
There is an area dedicated for a LNA preamp. This
evaluation board will be discussed and referenced in this
section.
shown in Figures 27 and 28 for the application circuit in
Figure 15 and for the 83.616 MHz crystal oscillator circuit in
Figure 16.
Input Matching Components
The input matching circuit shown in the application circuit
schematic (Figure 15) is a series L, shunt C single L section
which is used to match the mixer input to 50 n. An
alternative input network may use 1:4 surface mount
transformers or BALUNs. The 12 dB SINAD sensitivity
using the 1:4 impedance transformer is typically -100 dBm
forfmod= 1.0 kHz andfdev =±5.0 kHz atfin =50 MHz and fLO
=50.455 MHz (see Figure 14).
It is desirable to use a SAW filter before the mixer to
provide additional selectivity and adjacent channel rejection
and improved sensitivity. SAW filters sourced from Toko (Part
# SWS083GBWA) and Murata (Part # SAF83.16MA51 X) are
excellent choices to easily interface with the MC13150 mixer.
They are packaged in a 12 pin low profile surface mount
ceramic package. The center frequency is 83.161 MHz and
the 3.0 dB bandwidth is 30 kHz.
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to
use components from various manufacturers and coil types.
The applications circuit schematic (Figure 15) specifies
particular components that were used to achieve the results
shown in the typical curves but equivalent components
should give similar results. Component placement views are
Figure 14. S+N+D, N+D, N, 30% AMR
versus Input Signal Level
20
iIi"
:sa:
2
S+N+D
0
~ -10
g
Z -20
ci
;J;. -30
ci
;J;. -40
+
en
II
10
-50
r...
Vee =3.0Vdc
'mod = 1.0 kHz
'dev = ±5.0 kHz
'in =50MHz
I
I
I
I
"- ~iIIl;
I
~
,
N+D
I
yt
-60
-120
-100
I
30%AMR
flO = 50.455 MHz
lO level = -10 dBm
See Figure 15
-80
-60
-
-40
INPUT SIGNAL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
8-265
MC13150
Figllre 15. Application Circuit
(3)
LO Input
(4)
.-------------0 Enable
(5)
r - - -.......- - - - - Q
RSSI
82k
(2)
455 kHz
IF Ceramic
nO,
1---0
0
RSSI
Buffer
1-----<_ _>---0 Detector
Output
RL
lOOk
II
150k
R-r
12k
RF
(6)
Coilless Detector
Circutt
VCC
NOTES: 1. Altemate solution is 1:4 impedance transformer (sources include Mini Circuits, Coilcraft and Toko).
2.455 kHz ceramic IIHers (source Murata CFU455 series which are selected for various bandwidths).
3. Forextemal LO source, a 51 n pull-up resistor is usadto bias the base of the on-board transistor as shown in Figure 15.
Designer may provide local oscillator with 3rd, 5th, or 7th overtone crystal oscillator circuit. The PC board is laid out to
accommodate extemal components needed for a Butler emitter coupled crystal oscillator (see Figure 16).
4. Enable IC by switching the pin to VEE.
5. The resistor is chosen to set the range of RSSI voltage output swing.
6. Details regarding the extemal components to setup the coilless detector are provided in the application section.
8-266
MOTOROLA ANALOG IC DEVICE DATA
MC13150
local Oscillators
A series LC network to ac ground (which is VCC) is
comprised of the inductance of the base lead of the on-chip
transistor and PC board traces and tap capacitors. Parasitic
oscillations often occur in the 200 to 800 MHz range. A small
resistor is placed in series with the base (Pin 28) to cancel the
negative resistance associated with this undesired mode of
oscillation. Since the base input impedance is so large, a
small resistor in the range of 27 to 68 (1 has very little effect
on the desired Butler mode of oscillation.
The crystal parallel capacitance, Co, provides a feedback
path that is low enough in reactance at frequencies of 5th
overtones or higher to cause trouble. Co has little effect near
resonance because of the low impedance of the crystal
motional arm (Rm-Lm-Cm). As the tunable inductor, which
forms the resonant tank with the tap capacitors, is tuned off
the crystal resonant frequency, it may be difficult to tell if the
oscillation is under crystal control. Frequency jumps may
occur as the inductor is tuned. In order to eliminate this
behavior an inductor, lo, is placed in parallel with the crystal.
Lo is chosen to resonant with the crystal parallel capacitance,
Co at the desired operation frequency. The inductor provides
a feedback path at frequencies well below resonance;
however, the parallel tank network of the tap capaCitors and
tunable inductor prevent oscillation at these frequencies.
HF & VHF Applications
In the application schematic, an external sourced local
oscillator is utilized in which the base is biased via a 51 (1
resistor to VCC. However, the on-chip grounded collector
transistor may be used for HF and VHF local oscillators with
higher order overtone crystals. Figure 16 shows a 5th
overtone oscillator at 83.616 MHz. The circuit uses a Butler
overtone oscillator configuration. The amplifier is an emitter
follower. The crystal is driven from the emitter and is coupled
to the high impedance base through a capacitive tap
network. Operation at the desired overtone frequency is
ensured by the parallel resonant circuit formed by the
variable inductor and the tap capacitors and parasitic
capacitances of the on-chip transistor and PC board. The
variable inductor specified in the schematic could be
replaced with a high tolerance, high Q ceramic or air wound
surface mount component if the other components have tight
enough tolerances. A variable inductor provides an
adjustment for gain and frequency of the resonant tank
ensuring lock up and start-up of the crystal oscillator. The
overtone crystal is chosen with ESR of typically 80 (1 and
120 (1 maximum; if the resistive loss in the crystal is too high
the performance of oscillator may be impacted by lower gain
margins.
II
Figure 16. MC13150FTB Overtone Oscillator
fRF 83.16 MHz; flO 83.616 MHz
5th Overtone Crystal Oscillator
=
=
(4)
--------------,I
0.135 11H
r---,
MC13150
I
33
+
I- I
1
1.011
39p
10n
Vee
MOTOROLA ANALOG IC DEVICE DATA
8-267
MC13150
application circuit (Figure 15). the input 1.0 dB compression
point is -10 dBm and the input third order intercept (IP3)
performance of the system is approximately 0 dBm (see
Figure 18).
Receiver Design Considerations
The curves of signal levels at various portions of the
application receiver with respect to RF input level are shown
in Figure 17. This information helps determine the network
topology and gain blocks required ahead of the MC13150 to
achieve the desired sensitivity and dynamic range of the
receiver system. The PCB is laid out to accommodate a low
noise preamp followed by the 83.16 MHz SAW filter. In the
Typical Performance Over Temperature
Figures 19-26 show the device performance over
temperature.
Figure 17. Signal Levels versus
RF Input Signal Level
10
0
-10
;[
-20
~
a::
w
s:
-30
~
-40
-50
fRF=50 MHz
fLO = 50.455 MHz; LO Level = -10 dBm
See Figure 15
-60
-70
-80
-70
-60
-50
-40
-30
-20
-10
RF INPUT SIGNAL LEVEL (dBm)
8-268
MOTOROLA ANALOG IC DEVICE DATA
MC13150
Figure 18. 1.0 dB Compression Point and Input
Third Order Intercept Point versus Input Power
20
i:e
...J
w
~
~
I
I
>1
V 1 """
/' /
/'
/
IP3 = -0.5 dBm
-20
c..
~
o
V
~
a:
~ -40
::ij
-60
V-
/'
-80
V
I
I
1.0 dB Compression ~
Point =-11 dBm
_ Vcc = 3.0 Vde
fRF1 = 50 MHz
fRF2 = 50.01 MHz
o ,-- fLO = 50.455 MHz
PLO=-10dBm
'-- See figure 15
V
/
I
-60
I
I
-40
-20
20
RF INPUT POWER (dBm)
II
TYPICAL PERFORMANCE OVER TEMPERATURE
Figure 19. Supply Current, IVEEl
versus Signal Input Level
Figure 20. Supply Current, IVEE2
versus Ambient Temperature
5.0
1
I-
z
w
a:
a:
0.35
4.5 f - VCC = 3.0 Vde
fe = 50 MHz
4.0 f - fdev = ±4.0 kHz
3.5
J.
/I
/I
3.0
~
0
2.5
~
a..
a..
2.0
~
(J)
~
It
w 1.0
2?
0.5
o
A
/
1.5
-120
10
rI
/A=85"C
\
-105
-90
TA = 25"C
I
-75
-60
-45
\
TA=-40"CI
-30
-15
SIGNAL INPUT LEVEL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
I
1
!z
~
a:
VCC = 3.0 Vdc
0.3
~
o
~
a..
c..
~ 0.25
~
~
V
/'
/
r
0.2
-~
-W
0
W
~
~
80
TA, AMBIENT TEMPERATURE (0C)
8-269
MC13150
TYPICAL PERFORMANCE OVER TEMPERATURE
Figure 21. Total Supply Current
versus Ambient Temperature
1.8
«
.s
f-
ii'i
Vee = 3.0 Vdc
1.7
~ 1.65
::>
~
"-
g;
1.6
1.55
~
1.5
f-
1.45
,...
~
w
II
.=!:
!z
UJ
c:
c:
~~
~
::;:
~
1.0
o
-20
20
40
60
-40
80
-
-
--
I
I
Vin=
---"'OdBm_
-"'-20dBm
I
40dBm
I
-
60dBm
80dBm
100?Bm
120dBm
0.65
-20
0
20
40
60
80
Q
1.6
~
1.3
~
~
~
0.6
0
::>
..:
0
UJ
a:
UJ
60
0.55
80
0.5
UJ
c:
0.45
Vcc= 3.0 Vdc
r- RF In = -50 dBm
- r-
fc=50 MHz
fLO = 50.455 MHz
fdey = ±4.0 kHz
I
-40
100
I I I
-20
0
20
40
60
80
Figure 25. Demod DC Output Voltage
versus Ambient Temperature
Figure 26. LO Current versus
Ambient Temperature
I
..............
r--....
.......
I'-...
...............
100
I
Vee = 3.0Vdc RF In = -50 dBm
fc=50 MHz
fLO = 50.455 MHz
fdey = ±4.0 kHz -
I
90
-
80
;--
«
.=!:
fZ
a:
c:
..... -
::>
0
70
0
...J
60
1.0
.......-
100
I
Vee = 3.0Vdc
RF In = -50 dBm
fc=50 MHz
fLO = 50.455 MHz
fdey = ±4.0 kHz
/-
UJ
.............. r--....
1.1
..--
I-
./
V
/'
50
-20
0
20
40
60
TA, AMBIENT TEMPERATURE (Oe)
8-270
-
-- -
TA, AMBIENT TEMPERATURE (Oe)
1.2
0.9
-40
r- r- r-
TA, AMBIENTTEMPERATURE (Oe)
1.7
5o
r- !--.
0.
~
0.4
-40
1.4
60
Figure 24. Recovered Audio versus
Ambient Temperature
20
~
40
0.7
30
1.5
20
Figure 23. RSSI Current versus
Ambient Temperature and Signal Level
0
~
0
TA, AMBIENT TEMPERATURE (Oe)
Vee = 3.0 Vdc
fRF=50MHz
40
(!J
-20
TA, AMBIENT TEMPERATURE ee)
10
w
1.5
Z
c:
~
r-.
R:
::>
U)
2.0
::>
0
en
--........r-.......
~
C!>
60
«
-........
2.5
U)
1.4
50
-...........
i:'!:
/
-40
3.0
~
... V
V
/
/
U)
o
..,. ..--
1.75
Figure 22. Minimum Supply Voltage
versus Ambient Temperature
80
-40
-20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (Oe)
MOTOROLA ANALOG IC DEVICE DATA
MC13150
Figure 27. Component Placement View - Circuit Side
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GND
MOTOROLA ANALOG IC DEVICE DATA
Vee
a
8-271
MC13150
Figure 28. Component Placement View'- Ground Side
II
8-272
MOTOROLA ANALOG IC DEVICE DATA
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MC13150
Figure 30. PCB Ground Side View
II
&-274
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13155
Wideband FM IF
The MC13155 is a complete wideband FM detector designed for satellite
TV and other wideband data and analog FM applications. This device may
be cascaded for higher IF gain and extended Receive Signal Strength
Indicator (RSSI) range.
WIDEBAND FM IF
• 12 MHz Video/Baseband Demodulator
• Ideal for Wideband Data and Analog FM Systems
• Limiter Output for Cascade Operation
SEMICONDUCTOR
TECHNICAL DATA
• Low Drain Current: 7.0 rnA
• Low Supply Voltage: 3.0 to 6.0 V
• Operates to 300 MHz
MAXIMUM RATINGS
Pin
Symbol
Value
Power Supply Voltage
Rating
11,14
VEE (max)
6.5
Vdc
Input Vo~age
1,16
Vin
1.0
Vrms
Junction Temperature
-
TJ
+150
°C
Storage Temperature Range
-
Tstg
-65to+150
°C
NOTE:
Unit
DSUFFIX
PLASTIC PACKAGE
CASE 7518
(50-16)
Devices should not be operated at or outside these values. The ·'Recommended
Operating Conditions" provide for actual device operation.
II
PIN CONNECTIONS
Figure 1. Representative Block Diagram
Input
Input
Decouple
Buffered
Decouple
15
Decouple
Vcc1
RSSI
Output
13
Input
Input
Output
RSSI Buller
Output
RSSI
Limiter Out
LimHerOut
Quad Coil
Quad Coil
(Top View)
5
Decouple
Balanced
Outputs
7
Limiter
Output
NOTE: This device requires careful layout and decoupling to ensure stable operation.
MOTOROLA ANALOG IC DEVICE DATA
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC13155D
TA =- 4010 +85°C
50-16
8-275
MC13155
RECOMMENDED OPERATING CONDITIONS
Pin
Symbol
Value
Unit
Power Supply Voltage (TA= 25°C)
- 40°C::; TA::; 85°C
Rating
11,14
3,6
VEE
VCC
-3.0to-6.0
Grounded
Vdc
Maximum Input Frequency
1,16
fin
300
TJ
-40to+85
;,'
Ambient Temperature Range
-
, MHz
°c
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, no input signal.)
Characteristic
Drain Current
(VEE = - 5.0 Vdc)
(VEE = - 5.0 Vdc)
Drain Current Total (see Figure 3)
(VEE = - 5.0 Vdc)
(VEE = - 6.0 Vdc)
(VEE = - 3.0 Vdc)
Symbol
Min
Typ
Msx
Unit
11
14
14
111
114
114
2.0
3.0
3.0
2.8
4.3
4.3
4.0
6.0
6.0
rnA
11,14
ITotal
5.0
5.0
5.0
4.7
7.1
7.5
7.5
6.6
10
10.5
10.5
9.5
rnA
Pin
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, flF = 70 MHz, VEE = - 5.0 Vdc Figure 2, unless otherwise noted.)
Characteristic
•
Pin
Min
Typ
Max
Unit
-
1.0
2.0
mVrms
470
450
380
590
570
500
700
680
620
Input for - 3 dB Limiting Sensitivity
1,16
Differential Detector Output Voltage (Vin = 10 mVrms)
(fdev = ± 3.0 MHz) (VEE = - 6.0 Vdc)
(VEE = - 5.0 Vdc)
(VEE = - 3.0 Vdc)
4,5
Detector DC Offset Voltage
mVJrP
4;5
-250
-
250
mVdc
RSSISlope
13
1.4
2.1
2.8
JlAIdB
RSSI Dynamic Range
13
31
35
39
RSSIOutput
(Vin = 100 ~Vrms)
(Vin = 1.0 mVrms)
(Vin = 10 mVrms)
(Vin = 100 mVrms)
(Vin = 500 mVrms)
12
RSSI Buffer Maximum Output Current (Vin = 10 mVrms)
13
Differential Limiter Output
(Vin = 1.0 mVrms)
(Vin = 10 mVrms)
16
-
-
2.1
2.4
24
65
75
36
2.3
-
dB
!1A
-
mAdc
mVrms
7,10
100
-
140
180
-
Demodulator Video 3.0 dB Bandwidth
4,5
-
12
-
Input Impedance (Figure 14)
@70MHz Rp (VEE = - 5.0 Vdc)
Cp (C2=C15 = 100 p)
1,16
-
450
4.8
-
pF
-
46
-
dB
Differential IF Power Gain
NOTE:
8-276
1,7,10,16
MHz
n
Positive currents are out of the pins of the device.
MOTOROLA ANALOG IC DEVICE DATA
MC13155
CIRCUIT DESCRIPTION
indicator (RSSI) circuit which provides a current output
linearly proportional to the I F input signal level for
approximately 35 dB range of input level.
The MC13155 consists of a wideband three-stage limiting
amplifier, a wideband quadrature detector which may be
operated up to 200 MHz, and a received signal strength
Figure 2. Test Circuit
1.0n
INl
10n
DECl
DEC2
VCCl
VEEl
27
~
VEE
DETOl
Video
Ou1put
DET02
Limiterl~
Ou1put
VEE
VCC2
VEE2
LlMOl
LlM02
1.0n
330
VEE
Ou1put
~u"""
1.0n
330
QUADl
499
II
20p
L1 - Coileral! part number 141Hl9JOBS
260n
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB shown in Figures 19 and 20 is very
versatile and is designed to cascade two ICs. The center
section of the board provides an area for attaching all surface
mount components to the circuit side and radial leaded
components to the component ground side of the PCB (see
Figures 17 and 18). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interface circuitry as a particular application dictates.
This evaluation board will be discussed and referenced in
this section.
Limiting Amplifier
Differential input and output ports interfacing the three
stage limiting amplifier provide a differential power gain of
typically 46 dB and useable frequency range of 300 MHz.
The IF gain flatness may be controlled by decoupling of the
internal feedback network at Pins 2 and 15.
MOTOROLA ANALOG IC DEVICE DATA
Scattering parameter (8-parameter) characterization of
the IF as a two port linear amplifier is useful to implement
maximum stable power gain, input matching, and stability
over a desired bandpass response and to ensure stable
operation outside the bandpass as well. The MC13155 is
unconditionally stable over most of its useful operating
frequency range; however, it can be made unconditionally
stable over its entire operating range with the proper
decoupling of Pins 2 and 15. Relatively small decoupling
capacitors of about 100 pF have a significant effect on the
wideband response and stability. This is shown in the
scattering parameter tables where S-parameters are shown
for various values of C2 and C15 and at VEE of - 3.0 and
-5.0Vdc.
8-277
MC13155··
TYPICAL PERFORMANCE AT TEMPERATURE
(See Figure 2. Test Circuit)
Figure 4. RSSI Output versus Frequency and
Input Signal Level
Figure 3. Drain Current versus Supply Voltage
10
f
i- TA
100
J25 C
~ 8.0
ITotai = 114 + 111
~
r
II:
i3
6.0
C!.
4.0
z
~
I
I
,
-g 2.0
co
.f
0.0
0.0
1.0
II
~
en
en
4.0
5.0
6.0
6.5
;!:
:g
'"
.£'
6.0
5.5
10
5.5
u
VEE=-6.0V~
'l
/
. /~
/'
,/
5.0
-50
./
./
-30
-10
~
~-5.0VdC
. /V
",
..,
4.0
=>
0
V
gj
23.0
II:
~
22.5
22.0
21.5
-50
z
;;: 3.5
II:
.."..
~3.0
§;!:.25
30
50
70
90
2.0
-50
110
i-"""
114
V
V
..............
0
--30
!.-- ~
-10
10
-
30
~ f--
50
70
90
TA, AMBIENT TEMPERATURE (OC)
Figure 7. RSSI Output versus Ambien~
Temperature and Supply Voltage
Figure 8. RSSI Output versus Input Signal
Voltage (Vin at Temperature)
110
100
./',
/ ./
'/
/
/
/'"
/'
_
-
~.
<80
~
I; 60
"-
:::I.
>=>
VEE=-5.0Vdc -
T
0
I
en
en
~J
VIE =-3'i VdC -
/'
/
-30
VEE=~6.0Vdc
II:
40
~
20
o~~~~rrwlli-~llW~LUwm
-10
10
30
50
70
TA, AMBIENTTEMPERATURE (0C)
8-278
f=70MHz
VEE = - 5.0 Vdc
TA, AMBIENT TEMPERATURE (0C)
24.0
23.5
r--
4.5
UJ
II:
II:
"
10
I>-
5.0
z
/3.0Vdc
24.5
~
1000
Figure 6. Detector Drain Current and Limiter
Drain Current versus Ambient Temperature
25.0
<
:::I.
100
Figure 5. Total Drain Current versus Ambient
Temperature and Supply Voltage
7.5
~
f2
8.0
r--.. r-.,....
f, FREQUENCY (MHz)
8.0
7.0
-
_40IdB~
o
:--'r-.,
VEE, SUPPLY VOLTAGE (-Vdc)
9.0
~
o
--'
7.0
r--....
~ ~~
r- r-...
_30 1dBj
20
3.0
-
-201dBl
~
.1
--.... r---.
-10IdB~
40
II:
II:
i3
z
80
0
/I
11/
2.0
I,
VEE = - 5.0Vdc
oldBl
>=>
"- 60
>=>
114
j::' 8.5
z
<:::I.
If
]j
P.
f
--
0
90
110
0.1
1.0
10
100
1000
Vin, INPUT VOLTAGE (mVrms)
MOTOROLA ANALOG IC DEVICE DATA
MC13155
Figure 9. Differential Detector Output
Voltage versus Ambient Temperature
and Supply Voltage
Figure 10. Differential Limiter Output Voltage
versus Ambient Temperature
(Vin
lli
VEy_-6.0VdC
;:f
~
/' /
~V
~
./
"",.
~~
os
cc....-
..;'
180
f--~
~~
3.~ 160
<0-
ffi- 140
.....
./
ffi
it
is
-10
10
30
70
50
90
110
".,
120
-50
"",.
~
-30
~1MO~V~in-=-_~3MO~d~B~m-----------'---'---'---'---'
S
1400 VEE=-5.0Vdc
f-'c=70MHz
~ 1200 'mod = 1.0 MHz
~
(Figure 16 no external capacitors
~ 1000 between Pins 7, 8 and 9, 10)
....&C-b"""'-f-.=-""T"'''--l
f2 8001----i----j----t.-"'70-F--,;;;-F----b.,..."q....='"""T'-"'---1
6001----1----~~~c:....~~~--~~~
I5 ::I--~~~e:~t_--t-~~--t_--t_--t_--!
t--c.
~
0-
§cc
§
~
2.5
3.0
3.5
4.0
4.5
c:.
uj
(!J
;:f
:..I
§2
5.0
5.5
6.0
VEE = - 5.0 Vdc
'e = 70 MHz
Capacitively coupled
(See Figure 16) - - - interstage: no aHenuation
90
1200
1---j----t----::;.....,,~1--::..,.."F--+::::;;;;o-t ± 3.0 ~HZ
800
±2.0MHz
I
r---F:::r::t::::p;;;;t=t-1
I
± 1.0 MHz
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Figure 13. - S+N, N versus IF Input
10
siN
/'
~
-20
co
:e:.
'I'-..
z -30
-10
-2.0
-3.0
f--
Z
+
'"
f--
=> -4.0
0
'"cc
70
Q OF QUADRATURE LC TANK
=>
0-
en
50
O~~--~--~--~~--~--~--~~
Figure 12. RSSI Output Voltage versus IF Input
O.------r------.------.------,-----,
-1.0
30
Yin = 1.0 mVrms
VEP-5.0Vdc
2000 Ie = 70 MHz
lmod = 1.0 MHz
1600 (Figure 16 no extemal capacitors ...-I"'--=l"""'''-l----'----l
between Pins 7,8 and 9,10)
± 4.0 MHz
Q OF QUADRATURE LC TANK
:go
--
~~
2400 r;V"'in-=--""3;;;0"'d;;:;-Bm~--~--~--""----""--""--""--"
400
I
2.0
10
/
V
./
Figure 118. Differential Detector Output Voltage
versus Q of Quadrature LC Tank
O~--~--~--~--~--~--~--~--~~
1.5
-10
.......
TA, AMBIENTTEMPERATURE (DC)
Figure 11A. Differential Detector Output Voltage
versus Q of Quadrature LC Tank
It
./
~
TA, AMBIENT TEMPERATURE (DC)
~a
i-"""
V
wo
./
- 30
Yin = 10 mVnns
~u;- 200
V
V
I
'=70MHz
VEE = - 5.0 Vdc
g
..........: /-5.0Vdc
....0V /-3.0Vdc
=1 and 10 mVrms)
220
-50
-5.0
-80
-60
-60
-40
-20
IF INPUT, (dBm)
MOTOROLA ANALOG IC DEVICE DATA
20
'"
-40
-70
-90
Ic = 70 MHz
'mod = 1.0 MHz
'dey = ± 5.0 MHz
VEE = - 5.~ Vde
-70
't'-.,.
............ N
-50
-30
-10
10
IF INPUT (dBm)
8-279
•
MC13155
In the 8-parameters measurements, the IF is treated as a
two-port linear class A amplifier. The IF amplifier is
measured with a single-ended input and output configuration
in which the Pins 16 and 7 are terminated in the series
combination of a 47 n resistor and a 10 nF capacitor to VCC
ground (see Figure 14. 8-Parameter Test Circuit).
The 8-parameters are in polar form as the magnitude
(MAG) and angle (ANG). Also listed in the tables are the
calculated values for the stability factor (K) and the Maximum
Available Gain (MAG). These terms are related in the
followinj:l equations:
K= (1-181112,..1 82212+ I LlI2)/(21 812 8211)
where: I Lli = I 811 822 - 812 821 I.
MAG = 10 log I 8211 /1 8121 + 10 log I K-( K2_1)1/21
where: K > 1. The necessary and sufficient conditions for
unconditional stability are given as K > 1:
B1 = 1 + I 811 12 - I 822 12 - I Lll2 > 0
Figure 14. S-Parameter Test Circuit
IF
Input
SMA
)
2
IN1
DEC1
VCC1
1 - - - . - - - - - - . - - - - _ _ , - 0 VEE
DET01
DET02
r·,
II
47
8-280
VCC2
2(
SMA
IF
Output
QUAD1
MOTOROLA ANALOG IC DEVICE DATA
MC13155
S-Parameters (VEE =- 5.0 Vdc, TA =25°C, C2 and C15 =0 pF)
K
MAG
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.94
-13
8.2
143
0.001
7.0
0.87
-22
2.2
32
2.0
0.78
-23
23.5
109
0.001
-40
0.64
-31
4.2
33.5
5.0
0.48
1.0
39.2
51
0.001
-97
0.34
-17
8.7
33.7
7.0
0.59
15
40.3
34
0.001
-41
0.33
-13
10.6
34.6
10
0.75
17
40.9
19
0.001
-82
0.41
-1.0
5.7
36.7
20
0.95
7.0
42.9
-6.0
0.001
-42
0.45
0
1.05
46.4
50
0.98
-10
42.2
-48
0.001
-9.0
0.52
-3.0
0.29
-
70
0.95
-16
39.8
-68
0.001
112
0.54
-16
1.05
46.4
100
0.93
-23
44.2
-93
0.001
80
0.53
-22
0.76
-
150
0.91
-34
39.5
-139
0.001
106
0.50
-34
0.94
200
0.87
-47
34.9
-179
0.002
77
0.42
-44
0.97
-
500
0.89
-103
11.1
-58
0.022
57
0.40
-117
0.75
-
700
0.61
-156
3.5
-164
0.03
0
0.52
179
2.6
13.7
900
0.56
162
1.2
92
0.048
-44
0.47
112
4.7
4.5
1000
0.54
131
0.8
42
0.072
-48
0.44
76
5.1
0.4
K
MAG
Frequency
Input 511
Forward 521
Rev 512
Output 522
S-Parameters (VEE =- 5.0 Vdc, TA =25°C, C2 and C15 =100 pF)
Frequency
Input 511
Forward 521
Rev 512
Output 522
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.98
-15
11.7
174
0.001
-14
0.84
-27
1.2
37.4
2.0
0.50
-2.0
39.2
85.5
0.001
-108
0.62
-35
6.0
35.5
5.0
0.87
8.0
39.9
19
0.001
100
0.47
-9.0
4.2
39.2
7.0
0.90
5.0
40.4
9.0
0.001
-40
0.45
-8.0
3.1
40.3
10
0.92
3.0
41
1.0
0.001
-40
0.44
-5.0
2.4
41.8
20
0.92
-2.0
42.4
-14
0.001
-87
0.49
-6.0
2.4
41.9
50
0.91
-8.0
41.2
-45
0.001
85
0.50
-5.0
2.3
42
70
0.91
-11
39.1
-63
0.001
76
0.52
-4.0
2.2
41.6
100
0.91
-15
43.4
-84
0.001
85
0.50
-11
1.3
43.6
150
0.90
-22
38.2
-126
0.001
96
0.43
-22
1.4
41.8
200
0.86
-33
35.5
-160
0.002
78
0.43
-21
1.3
39.4
500
0.80
-66
8.3
-9.0
0.012
75
0.57
-63
1.7
23.5
700
0.62
-96
2.9
-95
0.013
50
0.49
-111
6.3
12.5
900
0.56
-120
1.0
-171
0.020
53
0.44
-150
13.3
2.8
1000
0.54
-136
0.69
154
0.034
65
0.44
-179
12.5
-0.8
MOTOROLA ANALOG IC DEVICE DATA
8-281
II
MC13155
S-Parameters (VEE = - 5.0 Vdc, TA = 25°C, C2 and C15 = 680 pF)
K
MAG
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.74
4.0
53.6
110
0.001
101
0.97
-35
0.58
-
2.0
0.90
3.0
70.8
55
0.001
60
0.68
-34
1.4
45.6
5.0
0.91
0
87.1
21
0.001
-121
0.33
-60
1.1
49
7.0
0.91
0
90.3
11
0.001
-18
0.25
-67
1.2
48.4
47.5
Frequency
Input 511
Forward 521
Rev 512
Output 522
10
0.91
-2.0
92.4
2.0
0.001
33
0.14
-67
1.5
20
0.91
-4.0
95.5
-16
0.001
63
0.12
-15
1.3
48.2
50
0.90
-8.0
89.7
-50
0.001
-43
0.24
26
1.8
46.5
70
0.90
-10
82.6
-70
0.001
92
0.33
21
1.4
47.4
100
0.91
-14
77.12
-93
0.001
23
0.42
-1.0
1.05
49
150
0.94
-20
62.0
-122
0.001
96
0.42
-22
0.54
-
200
0.95
-33
56.9
-148
0.003
146
0.33
-62
0.75
-
500
0.82
-63
12.3
-12
0.007
79
0.44
-67
1.8
26.9
14.6
700
0.66
-98
3.8
-107
0.014
84
0.40
-115
4.8
900
0.56
-122
1.3
177
0.028
78
0.39
-166
8.0
4.7
1000
0.54
-139
0.87
141
0.048
76
0.41
165
7.4
0.96
K
MAG
S-Parameters (VEE = - 3.0 Vdc, TA = 25°C, C2 and C15 = 0 pF)
Frequency
Forward 521
Input 511
Rev 512
Output 522
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.89
-14
9.3
136
0.001
2.0
0.84
-27
3.2
30.7
2.0
0.76
-22
24.2
105
0.001
-90
0.67
-37
3.5
34.3
5.0
0.52
5.0
35.7
46
0.001
-32
0.40
-13
10.6
33.3
7.0
0.59
12
38.1
34
0.001
-41
0.40
-10
9.1
34.6
10
0.78
15
37.2
16
0.001
-92
0.40
-1.0
5.7
36.3
20
0.95
5.0
38.2
-9.0
0.001
47
0.51
-4.0
0.94
-
50
0.96
-11
39.1
-50
0.001
-103
0.48
-6.0
1.4
43.7
70
0.93
-17
36.8
-71
0.001
-76
0.52
-13
2.2
41.4
39.0
100
0.91
-25
34.7
-99
0.001
-152
0.51
-19
3.0
150
0.86
-37
33.8
-143
0.001
53
0.49
-34
1.7
39.1
200
0.81
-49
27.8
86
0.003
76
0.55
-56
2.4
35.1
500
0.70
-93
6.2
-41
0.015
93
0.40
-110
2.4
19.5
700
0.62
-144
1.9
-133
0.049
56
0.40
-150
3.0
8.25
900
0.39
-176
0.72
125
0.11
-18
0.25
163
5.1
-1.9
1000
0.44
166
0.49
80
0.10
-52
0.33
127
7.5
-4.8
8-282
MOTOROLA ANALOG IC DEVICE DATA
MC13155
=- 3.0 Vdc, TA =25°C, C2 and C15 =100 pF)
S-Parameters (VEE
Frequency
Input S11
Forward S21
RevS12
OutputS22
K
MAG
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.97
-15
11.7
171
0.001
-4.0
0.84
-27
1.4
36.8
2.0
0.53
2.0
37.1
80
0.001
-91
0.57
-31
6.0
34.8
5.0
0.88
7.0
37.7
18
0.001
-9.0
0.48
-7.0
3.4
39.7
7.0
0.90
5.0
37.7
8.0
0.001
-11
0.49
-7.0
2.3
41
10
0.92
2.0
38.3
1.0
0.001
-59
0.51
-9.0
2.0
41.8
20
0.92
-2.0
39.6
-15
0.001
29
0.48
-3.0
1.9
42.5
50
0.91
-8.0
38.5
-46
0.001
-21
0.51
-7.0
2.3
41.4
70
0.91
-11
36.1
-64
0.001
49
0.50
-8.0
2.3
40.8
100
0.91
-15
39.6
-85
0.001
114
0.52
-13
1.7
37.8
150
0.89
-22
34.4
-128
0.001
120
0.48
-23
1.6
40.1
200
0.86
-33
32
-163
0.002
86
0.40
-26
1.7
37.8
500
0.78
-64
7.6
-12
0.013
94
0.46
-71
1.9
22.1
700
0.64
-98
2.3
-102
0.027
58
0.42
-109
4.1
10.1
900
0.54
-122
0.78
179
0.040
38.6
0.35
-147
10.0
-0.14
1000
0.53
-136
0.47
144
0.043
23
0.38
-171
15.4
-4.52
K
MAG
S-Parameters (VEE =- 3.0 Vdc, TA =25°C, C2 and C15 =680 pF)
Frequency
Input S11
Forward S21
Rev S12
OutputS22
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.81
3.0
37
101
0.001
-19
0.90
-32
1.1
43.5
2.0
0.90
2.0
47.8
52.7
0.001
-82
0.66
-39
0.72
-
2.3
44
5.0
0.91
0
58.9
20
0.001
104
0.37
-56
7.0
0.90
-1
60.3
11
0.001
-76
0.26
-55
2.04
44
10
0.91
-2.0
61.8
3.0
0.001
105
0.18
-52
2.2
43.9
44.1
20
0.91
-4.0
63.8
-15
0.001
59
0.11
-13
2.0
50
0.90
-8.0
60.0
-48
0.001
96
0.22
33
2.3
43.7
70
0.90
-11
56.5
-67
0.001
113
0.29
15
2.3
43.2
100
0.91
-14
52.7
-91
0.001
177
0.36
5.0
2.0
43
150
0.93
-21
44.5
-126
0.001
155
0.35
-17
1.8
42.7
200
0.90
-43
41.2
-162
0.003
144
0.17
-31
1.6
34.1
500
0.79
-65
7.3
-13
0.008
80
0.44
-75
3.0
22
700
0.65
-97
2.3
-107
0.016
86
0.38
-124
7.1
10.2
900
0.56
-122
0.80
174
0.031
73
0.38
-174
12
0.37
1000
0.55
-139
0.52
137
0.50
71
0.41
157
11.3
-3.4
MOTOROLA ANALOG IC DEVICE DATA
8-283
II
MC13155
DC Biasing Considerations
The DC biasing scheme utilizes two VCC connections
(Pins 3 and 6) and two VEE connections (Pins 14 and 11).
VEEl (Pin 14) is connected internally to the IF and RSSI
circuits' negative supply bus while VEE2 (Pin 11) is connected
internally to the quadrature detector's negative bus. Under
positive ground operation, this unique configuration offers the
ability to bias the RSSI and IF separately from the quadrature
detector. When two ICs are cascaded as shown in the 70
MHz application circuit and provided by the PCB (see
Figures 17 and 18), the first MC13155 is used without biasing
its quadrature detector, thereby saving approximately 3.0
mAo A total current of 7.0 mA is used to fully bias each IC,
thus the total current ih the application circuit is
approximately 11 mAo Both VCC pins are biased by the same
supply. VCC1 (Pin 3) is connected internally to the positive
bus of the first half of the IF limiting amplifier, while VCC2 is
internally connected to the positive bus of the RSSI, the
quadrature detector circuit, and the second half of the IF
limiting amplifier (see Figure 15). This distribution of the VCC
enhances the stability of the IC.
RSSI Circuitry
The RSSI circuitry provides typically 35 dB of linear
dynamic range and its output voltage swing is adjusted by
selection of the resistor from Pin 12 to VEE. The RSSI slope
is typically 2.1 IJAIdB ; thus, for a dynamic range of 35 dB, the
current output is approximately 74 /-lA. A 47 k resistor will
yield an RSSI output voltage swing of 3.5 Vdc. The RSSI
buffer output at Pin 13 is an emitter-follower and needs an
external emitter resistor of 10k to VEE.
In a cascaded configuration (see circuit application in
Figure 16), only one of the RSSI Buffer outputs (Pin 13) is
used; the RSSI outputs (Pin 12 of each IC) are tied together
and the one closest to the VEE supply trace is decoupled to
VCC ground. The two pins are connected to VEE through a 47
k resistor. This reSistor sources a RSSI current which is
proportional to the signal level at the IF input; typically,
1.0 mVrms (- 47 dBm) is required to place the MC13155 into
limiting. The measured RSSI output voltage response of the
application circuit is shown in Figure 12. Since the RSSI
current output is dependent upon the input signal level at the
IF input, a careful accounting of filter losses, matching and
other losses and gains must be made in the entire receiver
system. In the block diagram of the application circuit shown
below, an accounting of the signal levels at pOints throughout
the system shows how the RSSI response in Figure 12 is
justified.
Block Diagram of 70 MHz Video Receiver Application Circuit
II
Input
Level:
IF
In~ut
-45dBm
1.26 mVrms
-70dBm
71 ~Vrms
!~a
-72dBm
-32dBm
57~Vrms
57~Vrms
16
Transformer
-25dB
(I rt' L )
2.0 dB
nse Ion oss (Insertion Loss)
Cascading Stages
The limiting IF output is pinned-out differentially,
cascading is easily achieved by AC coupling stage to stage.
In the evaluation PCB, AC coupling is shown, however,
interstage filtering may be desirable in some applications. In
which case, the S-parameters provide a means to implement
a low loss interstage match and better receiver sensitivity.
Where a linear response of the RSSI output is desired
when cascading the ICs, it is necessary to provide at least
10 dB of interstage loss. Figure 12 shows the RSSI response
with and without interstage loss. A 15 dB resistive attenuator
is an inexpensive way to linearize the RSSI response. This
has its drawbacks since it is a wideband noise source that is
dependent upon the source and load impedance and the
amount of attenuation that it provides. A better, although
more costly, solution would be a bandpass filter designed to
the desired center frequency and bandpass response while
carefully selecting the insertion loss. A network topology
8-284
-47dBm
1.0mVrms
-
Minimum Input to Acquire
Limiting In MC13155
f- 16
10
MC13155
MC13155
7
f-l
-15dB
(AHenuator)
40 dB Gain
40 dB Gain
shown below may be used to provide a bandpass response
with the desired insertion loss.
Network Topology
1.0n
r
10
0.22~
7
I!
L
..,
16
I
I
I
...J
1.0n
MOTOROLA ANALOG IC DEVICE DATA
MC13155
Quadrature Detector
The quadrature detector is coupled to the IF with internal
2.0 pF capacitors between Pins 7 and 8 and Pins 9 and 10.
For wideband data applications, such as FM video and
satellite receivers, the drive to the detector can be increased
with additional external capacitors between these pins, thus,
the recovered video signal level output is increased for a
given bandwidth (see Figure 11A and Figure 11 B).
The wide band performance of the detector is controlled by
the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
(1 )
where: RT is the equivalent shunt resistance across the LC
Tank and XL is the reactance of the quadrature inductor at the
IF frequency (XL =27tfL).
The inductor and capacitor are chosen to form a resonant
LC Tank with the PCB and parasitic device capacitance at the
desired IF center frequency as predicted by:
fc = (21t "(LC p)) -1
(2)
where: L is the parallel tank inductor and Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a wideband detector
at 70 MHz and a loaded Q of 5. The loaded Q of the
quadrature detector is chosen somewhat less than the Q of
the IF bandpass. For an IF frequency of 70 MHz and an
IF bandpass of 10.9 MHz, the IF bandpass Q is
approximately 6.4.
Example:
Let the external Cext = 20 pF. (The minimum value here
should be greater than 15 pF making it greater than the
internal device and PCB parasitic capacitance, Cint ~
3.0 pF).
Cp = Cint + Cext = 23 pF
Rewrite Equation 2 and solve for L:
L = (0.159)2 /(C p fc 2)
L = 198 nH, thus, a standard value is chosen.
L =0.22 !J.H (tunable shielded inductor).
MOTOROLA ANALOG IC DEVICE DATA
The value of the total damping resistor to obtain the
required loaded Q of 5 can be calculated by rearranging
Equation 1:
RT = Q(21tfL)
RT = 5 (21t)(70)(0.22) = 483.8 Q.
The internal resistance, Rint between the quadrature tank
Pins 8 and 9 is approximately 3200 Q and is considered in
determining the external resistance, Rext which is calculated
from:
Rext = «RT)(Rint))/ (Rint - RT)
Rext
= 570, thus, choose the standard value.
Rext = 560Q.
SAW Filter
In wideband video data applications, the IF occupied
bandwidth may be several MHz wide. A good rule of thumb is
to choose the IF frequency about 10 or more times greater
than the IF occupied bandwidth. The IF bandpass filter is a
SAW filter in video data applications where a very selective
response is needed (i.e., very sharp bandpass response).
The evaluation PCB is laid out to accommodate two SAW
filter package types: 1) A five-leaded plastic SIP package.
Recommended part numbers are Siemens X6950M which
operates at 70 MHz; 10.4 MHz 3 dB passband, X6951M
(X252.8) which operates at 70 MHz; 9.2 MHz 3 dB passband;
and X6958M which operates at 70 MHz, 6.3 MHz 3 dB
passband, and 2) A four-leaded T0-39 metal can package.
Typical insertion loss in a wide bandpass SAW filter is 25 dB.
The above SAW filters require source and load
impedances of 50 Q to assure stable operation. On the PC
board layout, space is provided to add a matching network,
such as a 1:4 surface mount transformer between the SAW
filter output and the input to the MC13155. A 1:4 transformer,
made by Coilcraft and Mini Circuits, provides a suitable
interface (see Figures 16, 17 and 18). In the circuit and
layout, the SAW filter and the MC13155 are differentially
configured with interconnect traces which are equal in length
and symmetrical. This balanced feed enhances RF stability,
phase linearity, and noise performance.
8-285
II
II
t
~
Figure 15. Simplified Internal Circuit Schematic
-s=;-
2
,£
Decouple
Vcc1
~
f2l
I1sl
VCC2
LIM Out
~
10
3
131 112
Quad Coil
LIM Out
I
7
RSSI RSSI
Buffer
J
v
Y'
"
10p
tt:i1
a.Ok
5:
~
, 1~
Out
4
~4)l 1 I J
I
a.Ok
1.0k
~
a
1.0k
~
~
~
Bias
~
,~
)00
z
I
§
01
~
<
o
m
o
~
)Ii
~
Input
!e~e
,~
1
w
~
' Bias
'$~ ~e
....
....
CII
0
~e!8
~8
~$
!Q
~$
!$
!~
~e
,e
..l....
J..±
J!
Input
VEE 1
VEE 2
Co)
CII
MC13155
Figure 16. 70 MHz Video Receiver Application Circuit
If Input
>-++...,
220
SAW Riter is Siemens
Part Number X6950M
RSSI
Output
MC13155
IN2
DEC2
VEEI
10k
~ IOn
RSSI
Buffer
47k
~ lOOn
RSSI
LlM02
II
820
820
820
1.0n
MC13155
INI
Detector
Output
t
IN2
DECI
DEC2
VCCI
VEEI
DETOI
RSSI
Buffer
DET02
RSSI
VCC2
VEE2
LlMOI
LlM02
QUADI
QUAD2
lOOn
o----io----i
......---~--~
~-
lOOn
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MOTOROLA ANALOG IC DEVICE DATA
8-287
MC13155
Figure 17. Component Placement (Circuit Side)
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8-288
MOTOROLA ANALOG IC DEVICE DATA
MC13155
Figure 19. Circuit Side View
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MOTOROLA ANALOG IC DEVICE DATA
8-289
®
MOTOROLA
MC13156
Wideband FM IF System
The MC13156 is a wideband FM IF subsystem targeted at high
performance data and analog applications. Excellent high frequency
performance is achieved at low cost using Motorola's MOSAIC 1.5™ bipolar
proce~s, The MC13156 has an onboard grounded collector VCO transistor
that may be used with a fundamental or overtone crystal in single channel
operation or with a PLL in multichannel operation. The mixer is useful to
500 MHz and may be used in a balanced-differential, or single-ended
configuration. The IF amplifier is split to accommodate two low cost
cascaded filters. RSSI output is derived by summing the output of both IF
sections, A precision data shaper has a hold function to preset the shaper for
fast recovery of new data.
Applications for the MC13156 include CT-2, wideband data links and
other radio systems utilizing GMSK, FSK or FM modulation.
WIDEBAND FM IF
SYSTEM FOR DIGITAL AND
ANALOG APPLICATIONS
SEMICONDUCTOR
TECHNICAL DATA
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(SQ-24L)
• 2.0 to 6.0 Vdc Operation
• Typical Sensitivity at 200 MHz of 2.0 !LV for 12 dB SINAD
• RSSI Dynamic Range Typically 80 dB
• High Performance Data Shaper for Enhanced CT-2 Operation
• Internal 330 nand 1.4 kn Terminations for 10.7 MHz and 455 kHz Filters
FB SUFFIX
PLASTIC OFP PACKAGE
CASE 873
312 .
• Split IF for Improved Filtering and Extended RSSI Range
• 3rd Order Intercept (Input) of -25 dBm (Input Matched)
PIN CONNECTIONS
SQ-24L
Function
QFP
RF Input 1
RF Input 2
Mixer Output
VCCI
IF Amp Inpul
IF Amp Oecoupling 1
IF Amp Decoupling 2
VCC Connect (NiC Inlernal)
IF Amp Outpul
Simplified Block Diagram
LO
In
LO
Emil
VEEI
CAR
Del
RSSI
VEE2
Data
Out
OS
Gnd
31
32
1
, VCC2
Limiter IF Input
Limiter Decoupling 1
Limiter Oecoupling 2
V C Connect (N/C Internal)
Quad Coil
Demodulator Output
Data Slicer Input
VCC Connect (NiC Inlemal)
Data Slicer Ground
Data Slicer Output
Data Slicer Hold
OS
In
VEE2
RSSI OutpuVCarrier Detect In
Carrier Detect Output
VEE1 and Substrate
LO Emitter
LO Base
VCO Connect (N/C Intemal)
10
11
12
10
11
12,13,14
15
16
17
18
19
20
21
13
14
15
16
17
18
19
20
21
22
23
24
22
23
24
25
26
27
28,29.30
ORDERING INFORMATION
RF
Inl
RF
In2
Mix
Out
VCCI
IF
IF
DEC 1 DEC2
IF
Out
VCC2
LIM
In
LIM
LIM
DEC 1 DEC2
Device
NOTE: Pin Numbers shown for'SOIC pac~age only, Refer to Pin Assignments Table,
This device contains 197 active transistors.
8-290
MC13158DW
MC13156FB
Operating
Temperature Range
TA = -40 to +85°C
Package
SQ-24L
OFP
MOTOROLA ANALOG IC DEVICE DATA
MC13156
MAXIMUM RATINGS
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
16,19,22
VE~(rnaJ(>-
-6.5
Vdc
Junction Temperature
-
TJ(max)
150
°c
Storage Temperature Range
-
Tstg
-65 to +150
°c
NOTES: 1. Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" table provides for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage @ TA = 25°C
-40°C S TA S +B5°C
Input Frequency
Ambient Temperature Range
Input Signal level
Pin
Symbol
Value
Unit
VCC
VEE
o (Ground)
Vdc
4,9
16,19,22
-2.0to-6.0
1,2
fin
500
-
TA
-40to+B5
MHz
°c
1,2
Yin
200
mVrms
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCCl = VCC2 = 0, no input signal.)
Pin
Symbol
Total Drain Current (See Figure 2)
VEE = -2.0 Vdc
VEE = --3.0 Vdc
VEE = -5.0 Vdc
VEE = -6.0 Vdc
Characteristic
19,22
ITotal
Drain Current, 122 (See Figure 3)
VEE = -2.0 Vdc
VEE = --3.0 Vdc
VEE = -5.0 Vdc
VEE = -6.0 Vdc
22
Drain Current, 119 (See Figure 3)
VEE = -2.0 Vdc
VEE = --3.0 Vdc
VEE = -5.0 Vdc
VEE = -6.0 Vdc
19
Min
Typ
Max
-
4.B
5.0
5.2
5.4
-
mA
3.0
-
122
Unit
-
B.O
-
rnA
-
-
3.0
3.1
3.3
3.4
-
1.B
1.9
1.9
2.0
-
-
119
-
rnA
-
DATA SLICER (Input Voltage Referenced to VEE = --3 0 Vdc no input signal; See Figure 15 )
Input Threshold Voltage (High Yin)
15
V15
1.0
1.1
1.2
Vdc
Output Current (low Yin)
Data Slicer Enabled (No Hold)
V15> 1.1 Vdc
V1B=OVdc
17
117
-
1.7
-
rnA
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VEE = --3.0 Vdc, fRF = 130 MHz, flO = 140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
Pin
Symbol
Min
Typ
Max
Unit
1,14
-
-
-100
-
dBm
Conversion Gain
Pin = -37 dBm (Figure 4)
1,3
-
-
22
-
dB
Mixer Input Impedance
Single-Ended (Table 1)
1,2
Rp
Cp
-
1.0
4.0
-
kn
-
-
pF
Mixer Output Impedance
3
-
-
330
-
n
IF RSSI Slope (Figure 6)
20
0.4
0.6
j.tAIdB
5,B
-
0.2
IF Gain (Figure 5)
39
-
dB
Input Impedance
5
-
1.4
kn
Output Impedance
B
-
290
-
Characteristic
12 dB SINAD Sensitivity (See Figures 17, 25)
fin = 144.45 MHz; fmod = 1.0 kHz; fdev = ±75 kHz
MIXER
IF AMPLIFIER SECTION
MOTOROLA ANALOG IC DEVICE DATA
-
n
8--291
II
MC13156
AC ELECTRICAL CHARACTERISTICS (continued) (TA =25°C, VEE
=--3.0 Vdc, fRF =130 MHz, fLO =140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
.
Characteristic
LIMITING AMPLIFIER SECTION
Limiter RSSI Slope (Figure 7)
20
-
0.2
0.4
0.6
Limiter Gain
-
-
dB
10
-
55
Input Impedance
-
1.4
-
kn
Output Current - Carrier Detect (High Vin)
21
-
21
-
-
0
Output Current - Carrier Detect (Low Vin)
3.0
-
rnA
Input Threshold Voltage - Carrier Detect
Input Voltage Referenced to VEE = --3.0 Vdc
20
-
0.9
1.2
1.4
Vdc
jJAldB
CARRIER DETECT
Figure 1. Test Circuit
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130MHz
11-t~
Mixerv=
1.0n
Output
330
II
IF Input
3
MC13156
I
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50
I1A
Local
Oscillator
Input
140.7MHz
200mVnns
I
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rt-±-r Vee
-=
Bias
I
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Hold
IFOutputV
330 1.0n
8
I
rfl}vee
-=
Limiter
Input
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SMA
LIM Amp
50
I
5.0p
I
L.. _ _ _ _ _ _ _ _ _ _ _ _ J
NOTES: 1. TR 1 Coilcrafll:4 impedance transformer.
2. VCC is DC Ground.
3. 1.511H variable shielded inductor:
Taka Part # 292SNS-T1373 or Equivalent.
8-292
MOTOROI,..A ANALOG IC DEVICE DATA
MC13156
Figure 2. Total Drain Current versus Supply
Voltage and Temperature
6.5
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z
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19
Linear Amplifier
I
Quadrature Detector
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Data Slicer
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MC13156
CIRCUIT DESCRIPTION
General
The MC13156 is a low power single conversion wide band
FM receiver incorporating a split IF. This device is designated
for use as the backend in digital FM systems such as CT-2
and wideband data links with data rates up to 500 kbaud. It
contains a mixer, oscillator, signal strength meter drive, IF
amplifier, limiting IF, quadrature detector and a data slicer
with a hold function (refer to Figure 8, Simplified Internal
Circuit Schematic).
Current Regulation
Temperature compensating voltage independent current
regulators are used throughout.
Mixer
The mixer is a double-balanced four quadrant multiplier
and is designed to work up to 500 MHz. It can be used in
differential or in single--ended mode by connecting the other
input to the positive supply rail.
Figure 4 shows the mixer gain and saturated output
response as a function of input signal drive. The circuit used
to measure this is shown in Figure 1. The linear gain of the
mixer is approximately 22 dB. Figure 9 shows the mixer gain
versus the IF output frequency with the local oscillator of
150 MHz at 100 mVrms LO drive level. The RF frequency is
swept. The sensitivity of the IF output of the mixer is shown in
Figure 10 for an RF input drive of 10 mVrms at 140 MHz and
IF at 10 MHz.
The single--ended parallel equivalent input impedance of
the mixer is Rp - 1.0 kn and Cp - 4.0 pF (see Table 1 for
details). The buffered output of the mixer is internally loaded
resulting in an output impedance of 330 n.
Local Oscillator
The on--chip transistor operates with crystal and LC
resonant elements up to 220 MHz. Series resonant, overtone
crystals are used to achieve excellent local oscillator stability.
3rd overtone crystals are used through about 65 to 70 MHz.
Operation from 70 MHz up to 180 MHz is feasible using the
on--chip transistor with a 5th or 7th overtone crystal. To
enhance operation using an overtone cristal, the internal
transistor's bias is increased by adding an external resistor
from Pin 23 to VEE. -10 dBm of local oscillator drive is
needed to adequately drive the mixer (Figure 10).
The oscillator configurations specified above, and two
others using an external transistor, are described in the
application section:
1) A 133 MHz oscillator multiplier using a 3rd overtone
crystal, and
2) A 307.8 to 309.3 MHz manually tuned, varactor controlled
local oscillator.
RSSI
The Received Signal Strength Indicator (RSS!) output is a
current proportional to the log of the received signal
MOTOROLA ANALOG IC DEVICE DATA
amplitude. The RSSI current output is derived by summing
the currents from the IF and limiting amplifier stages. An
external resistor at Pin 20 sets the voltage range or swing of
the RSSI output voltage. Linearity of the RSSI is optimized by
using external ceramic or crystal bandpass filters which have
an insertion loss of 8.0 dB. The RSSI circuit is designed to
provide 70+ dB of dynamic range with temperature
compensation (see Figures 6 and 7 which show RSSI
responses of the IF and Limiter amplifiers). Variation in the
RSSI output current with supply voltage is small (see
Figure 11).
Carrier Detect
When the meter current flowing through the meter load
resistance reaches 1.2 Vdc above ground, the comparator
flips, causing the carrier detect output to go high. Hysteresis
can be accomplished by adding a very large resistor for
positive feedback between the output and the input of the
comparator.
IF Amplifier
The first IF amplifier section is composed of three
differential stages with the second and third stages
contributing to the RSSI. This section has internal dc
feedback and external input decoupling for improved
symmetry and stability. The total gain of the IF amplifier block
is approximately 39 dB at 10.7 MHz. Figure 5 shows the gain
and saturated output response of the IF amplifier over
temperature, while Figure 12 shows the IF amplifier gain as a
function of the IF frequency.
The fixed internal input impedance is 1.4 kn. It is designed
for applications where a 455 kHz ceramic filter is used and no
external output matching is necessary since the filter requires
a 1.4 kn source and load impedance.
For 10.7 MHz ceramic filter applications, an external
430 n resistor must be added in parallel to provide the
equivalent load impedance of 330 n that is required by the
filter; however, no external matching is necessary at the input
since the mixer output matches the 330 n source impedance
of the filter. For 455 kHz applications, an external 1.1 kn
resistor must be added in series with the mixer output to
obtain the required matching impedance of 1.4 kn of the filter
input resistance. Overall RSSI linearity is dependent on
having total midband attenuation of 12 dB (6.0 dB insertion
loss plus 6.0 dB impedance matching loss) for the filter. The
output of the IF amplifier is buffered and the impedance is
290n.
Limiter
The limiter section is similar to the IF amplifier section
except that four stages are used with the last three
contributing to the RSSI. The fixed internal input impedance
is 1.4 kn. The total gain of the limiting amplifier section is
approximately 55 dB. This IF limiting amplifier section
internally drives the quadrature detector section.
8--295
II
:
MC13156
Figure 10