1996_Motorola_Analog_Interface_ICs_Device_Data_Volume_2 1996 Motorola Analog Interface ICs Device Data Volume 2
User Manual: 1996_Motorola_Analog_Interface_ICs_Device_Data_Volume_2
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®
I!!'0TOROLA
DL 128/D
REV 6
Analog/lnterfacelCs
Device Data
Vol. II
Volumes
I
II
I
I
I
II
II
II
II
II
II
II
I
II
I
II
a
II
Power Supply Circuits II
Power/Motor Control Circuits II
Voltage References II
Data Conversion II
Interface Circuits II
Communication Circuits II
Consumer Electronic Circuits II
Automotive Electronic Circuits IZ!I
Amplifiers and Comparators
Other Analog Circuits
II
II
Alphanumeric Index and
Cross References
III
III
Packaging Information lEI
Quality and Reliability Assurance III
Tape and Reel Options
Applications and Product Literature
III
What's Different
New Additions
,
~-
;'
CHAPTER 3
CHAPTER 7
LM2575
.MC78BCOO
MC78FCOO
MC78LCOO
MC33154
MC33264
MC33341
MC33347
MC33348
MC33363A
MC33364
MC33368
MC33463
MC33464
MC33465
MC33466
MC34065, MC33065
MC34165, MC33165
MC44604
MC44605
MC1413
MC34156
SN75175
CHAPTERS
MC13109
MC13110
MC13111
MC13144
MC13159
MC13283
MC44007
MC44030/35
MC44306
MC44353
MC44354
MC44355
MC44461
MC44462
MC44463
CHAPTER 10
CHAPTER 9
MC13022
MC13029A
MC13081X
MC13022A
MC13280AY, MC13281AIB
MC13282A
MC33143
MC33193
MC33197A
MC33293
MCCF33093
MCCF33094
MCCF33095
Deletes
LM307
LM248
MC1411
MC1412 .
MC1472
MC1748C
MC3361C
MC3371A
MC3372A
MC3430
MC3486
MC3487
MC13001 XlO7X
MC13017
MC13024
MC33292
MC33344
MC34050
MC34051
MC44301
MC44302
MC44303
MCT1413
SN75173
New Product Literature (Referenced)
AN454A
AN829
AN921
AN932
AN1044
AN1315
AN1539
AN1544
AN1548
AN1575
Not Recommended For New Designs
AM26LS31
AM26LS32
MC26S10
MC3373
MC3448A
MC3450
MC3453
MC3467
MC3481
MC3485
ULN2068
TDA1185A
3 Ways To Receive
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®
MOTOROLA
DL128/D
REV 6
Analog les
Device Data
Vol. II
This publication presents technical information for the broad line of Analog and Interface Integrated Circuit
products. Complete device specifications are provided in the form of Data Sheets which are categorized by product
type into ten chapters for easy reference. Selector Guides by product family are provided in the beginning of each
chapter to enable quick comparisons of performance characteristics. A Cross Reference chapter lists Motorola
nearest replacement and functional equivalent part numbers for other industry products.
One chapter is devoted showing all of the Tape and Reel Options. All Packaging Information, including
surface mount packages, is provided in another chapter.
Additionally, chapters are provided with information on Quality and Reliability Assurance program concepts,
high-reliability processing, and abstracts of available Applications and Product Literature.
The information in this book has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and
do vary in different applications. All operating parameters, including ''Typicals" must be validated for each customer
application by customer's technical experts. Motorola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attomey fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and ® are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Printed in U.S.A.
Series J
First Printing
© Motorola, Inc. 1996
Previous Edition © 1995
"All Rights Reserved"
Data Classification
Product PrevIew
This heading on a data sheet indicates that the device is in the formative stages or
in design (under development). The disclaimer at the bottom of the first page reads:
"This document contains information on a product under development. Motorola
reserves the right to change or discontinue this product without notice."
Advance Information
This heading on a data sheet indicates that the device is in sampling,
pre-production, or first production stages. The disclaimer at the bottom of the first
page reads: "This document contains information on a new product. Specifications
and information herein are subject to change without notice."
Fully Released
A fully released data sheet contains neither a classification heading nor a disclaimer
at the bottom of the first page. This document contains information on a product in
full production. Guaranteed limits will not be changed without written notice to your
local Motorola Semiconductor Sales Office.
C-QUAM®, Designer's, Easy Switcher, GreenLine, MDTL, MECL, MECL 10,000,
MONOMAX, MOSAIC®, MRTL, MTTL, MOSFET, SENSEFET, Sleep-Mode, SMARTMOS,
Switchmode, and ZIP-R-TRIM® are trademarks of Motorola Inc.
..
Alphanumeric Index and
Cross References
In Brief ...
Motorola Analog and Interface Integrated Circuits cover a
much broader range of products than the traditional op amps!
regulators/consumer-image associated with Analog suppliers. Analog circuit technology currently influences the design
and architecture of equipment for all major markets. As with
other integrated circuit technologies, Analog circuit design
techniques and processes have been continually refined and
updated to meet the needs of these diversified markets.
Operational amplifiers have utilized JFET inputs for
improved performance, plus innovative design and trimming
concepts have evolved for improved high performance and
precision characteristics. In analog power ICs, basic voltage
regulators have been refined to include higher current and
voltage levels, low dropout regulators, and more precise
three-terminal fixed and adjustable voltages. The power area
continues to expand into switching regulators, power supply
control and supervisory circuits, motor controllers, and battery
charging controllers.
Analog designs also offer a wide array of line drivers,
receivers and transceivers for many of the EIA, European,
IEEE and IBM interface standards. Peripheral drivers for a
variety of devices are also offered. In addition to these key
interface functions, hard disk drive read channel circuits,
10BASE-T and Ethernet circuits are also available.
In Data Conversion, a high performance video speed flash
converter is available, as well as a variety of CMOS and
Sigma-Delta converters. Analog circuit technology has also
provided precision low-voltage references for use in Data
Conversion and other low temperature drift applications.
A host of special purpose analog devices have also been
developed. These circuits find applications in telecommunications, radio, television, automotive, RF communications, and
data transmission. These products have reduced the cost of
RF communications, and have provided capabilities in telecommunications which make the telephone line convenient
for both voice and data communications. Analog developments have also reduced the many discrete components
formerly required for consumer functions to a few IC packages
and have made significant contributions to the rapidly growing
market for electronics in automotive applications.
The table of contents provides a perspective of the many
markets served by Analogllnterface ICs and of Motorola's
involvement in these areas.
MOTOROLA ANALOG IC DEVICE DATA
1-1
II
Alphanumeric Index
AM26LS30
AM26LS31#
AM26LS32#
CA3059
CA3146
LF347, B
LF351
LF353
LF411C
LF412C
LM293
LM301A
LM308A
LM311
LM317
LM317L
LM317M
LM2575
LM2900
LM2901, V
LM2902, V
LM2903, V
LM2904, V
LM2931
Dual DlfferentiaVQuad Single-Ended Line
Drtvers
Qued Line Drtver with NAND Enabled
Three-State Outputs
Quad EIA-4221423 Line Receiver with
Three-State Outputs
Zero Voltage Swhches
General Purpose Transistor Array
JFET Input Operational Amplifiers
JFET Input Operational Amplifiers
JFET Input Operational Amplifiers
Low Offset, Low Drift JFET Input Operational
AmplWiers
Low Offset, Low Drift JFET Input Operational
Amplifiers
i
Low Offset Voltage Dual Comparators
Operational Amplifiers
Precision Operational Amplifier
Highly Flexible Voltage Comparator
Three-Terminal Adjustable Output Positive
Voltage Regulator
Three-Terminal Adjustable Output Voltage
Regulator
Three-Terminal Adjustable Output Positive
Voltage Regulator
Positive
Easy SWitcher 1.0 A Stel>-Down Voltage
Regulator
Quad Single Supply Operational Amplifier
Quad Single Supply Comparator
Quad Low Power Operational Amplifier
Low Offset Voltage Dual Comparator
Duel Low Power Operational Amplifier
Low nm'nnlli' IInlt.n.
7-13
7-24
7-24
4-14
9-28
2-11
2-11
2-11
2-13
2-13
2-68
2-30
2-34
2-39
3-48
MC1488
MC14C88B
MC14C89B, AB
MCl469, A
MC1490
MC1494
MC1495
MC1496
MC1723C
Quad Line Driver
Quad Low Power Line Drtver
Quad Low Power Line Receiver
Quad Line Receivers
RFIIF Audio Amplifier
Linear Four-Quadrant Multiplier
Wldeband Linear Four-Quadrant Multiplier
Balanced Modulatosr/Demodulators
I
7-33
7-44
7-50
7-39
2-92
11-14
11-28
8-45
3-56
3-64
3-116
2-113
2-52
2-45
2-68
2-62
3-139
MC3356
MC3357
MC3358
MC3359
MC3362
MC3363
MC3371
MC3372
MC3373#
I
I
Differentially Connected Pair and Three
Isolated Transistor Arrays
Wideband FSK Reoelver
Low Power FM IF
Dual, Low Power Operational Amplifier
Dual, Low Power Operational Amplifier
Low Power Dual Conversion FM Receiver
Low Power Dual Conversion FM Receiver
Low Power Narrowband FM IF
Low Power Narrowband FM IF
Remote Control Wldeband Amplifier with
Detector
8-66
8-72
2-137
8-76
8-62
8-69
8-97
8-97
9-72
• =See Communloetlons Devioe Data (DL136).
# = Not recommended for new designs.
1-2
MOTOROLA ANALOG IC DEVICE DATA
Alphanumeric Index (continued)
MC3405
MC3418
MC3419-IL
MC3423
MC3425
MOWO/I
MC345SfI
MQM6
MC34S&
MOM?t
,MCW~
MC3479
MC3481#
MC3485#
MC348BA
MC3518
MC4558AC,C
MC4741C
MC7800
Series
MC78LOO, A
Series
MC78MOO
Series
Dual Operational Amplmer and Dual
Comparator
Continuously Variable Slope Delta
ModulatoriDemodulator
Telephone Line-Feed Circuit
Overvoltage Crowbar Sensing Circuit
Power Supply Supervisory/Over and
Undervoltage Protection Circuit
2-129
BIdI~onalllislflm!l!mtalion B\is (GPIS)
7~8
Traneoelver
Q\Jad Mm ¢omplItibIe lln$ ReoelVers
Mil1'\.. Compatible Q\Jad).l", DrtYet
7-71'
D\IaI Ttmlflg CIrouII
Dual, LOw ~ opemflonalAmpilfler
f'I-4a
2.-137
.~~WIth~
7~
G4lnCl>*~
,
3-171
3-177
'
7-64
l.Qwtelll~~AmpIliier ,
2--~
Stepper Motor Driver
Quad Single-Ended Line DrivAr
Quad Single-Ended Line Driver
Dual EIA-4231EIA-232D Line Driver
Continuously Variable Slope Delta
ModulatoriDemodulator
Dual Wide Bandwidth Operational Amplifiers
Differential Input Operational AmplWier
Three-Terminal Positive Voltage Regulators
4-19
7-81
7-81
7-86
2-149
2-156
3-t85
Three-Terminal Low Current Positive Voltage
Regulators
Three-Terminal Medium Current Positive
Voltage Regulators
3-200
'fII1et-AmPm l':oeilMl Volt!lQe FIegulat9l'S
}0;2;$
Ma76BCOO
~OO
~a_tor
M~Y_~
MOm.COO
Mic~~'
~
~
~
~
MC7IITOO
3-207
Se!1e$
~SIIIifI$
,~,A"
'u_
l'
~,
~
~f!'-'
Il-~
H~~e~~~
~
MC13~
MC'fa~
MC13022A
MC13025
MC13027
MC13028A
MCl3029A
MC13030
MC13055
MC13060
MC13077
MC13081X
MC13109
MC13110
~
, a.e
,
~~StetIIO"'~
9.1111
~~~AMSlsMo~
'~1
Advanced Medium Voltage AM Stereo Decoder
Electronically Tuned Radio Front End
AMAX Stereo Chipset
Advanced Wide Voltage IF and C-QUAM AM
Stereo Decoder
Advanced Wide Voltage IF and C-QUAM AM
Stereo Decoder with FM Amplifier and
AMlFM Internal Switch
Dual Conversion AM Receiver
Wideband FSK Receiver
Mini-Watt Audio Output
Advanced PAUNTSC Encoder
Multimode Color Monitor Horizontal, Vertical
and Video Combination Processor
Universal Cordless Telephone Subsystem IC
Universal Cordless Telephone Subsystem IC
with Scrambler
9-86
9-91
9-94
9-119
9-137
9-156
8-121
9-171
9-175
9-187
8-128
8-154
MC13111
MC13122
MC13135
MC13136
MC13141
MC13142
MC13143
MC13144
Universal Cordless Telephone Subsystem IC
AMAX Stereo Chipset
FM Communications Receiver
FM Communications Receiver
Low Power DC-l ,8 GHz LNA and Mixer
Low Power DC-l ,8 GHz LNA, Mixer and VCO
Ultra Low Power DC-2.4 GHz Linear Mixer
VHF - 2,0 GHz Low Noise Amplifier with
Programmable Bias
8-185
9-94
8-214
8-214
8-226
8-235
8-245
8-252
MC131110
Narrowband FM:CO/IIeSil Det/IOIOr IF
8458
MQ1!!155
~
Wldeband FM IF$y$tem
M()1$11)1l
WklebandFM1FSy$Ien'l
MC~1B8
WicMIland FM 1f!' SlJb$y$Iem
WRlIIband FM IF AlnpIIIIIlI
MC~l$ ,
6-275
8~
.e..oos
H30
-lnIra~~~Systl!ln
Melam
H36
.lA'I/U'WAM1'~
MCl3t15
Jl..oo;;
wm
IMP"~
Imz V1d~~$Qt
mall.' ~OI1!lO
HCa
MOiIi32a1 A. Ii
sMl.lO MH~Vldeo PrOC$$llQ/
HOO
MC13282A
MCI3283
MC26S10#
MC33023
MC33025
MC33030
MC33033
MC33035
MC33039
MC33060A
100 MHz Video Processor with OSD Interface
130 MHz Video Processor with OSD Interface
Quad Open-Collector Bus Transceiver
High Speed Single-Ended PWM Controller
High Speed Double-Ended PWM Controller
DC Servo Motor ControlieriDriver
Brushless DC Motor Controller
Brushless DC Motor Controller
Closed-Loop Brushless Motor Adapter
Precision Switch mode Pulse Width Modulator
Control Circuit
9-215
9-226
7-55
3-395
3-411
4-27
4-41
4-84
4-87
3-428
~
~ ilohvetterOOnlrolQllult
'MIm~
.
Me33064
~
Undervdltage $tin$1ng CIrcuit
,
HIgh P~lll.Ial¢hllhtllli~t,Mode
~nIrPiISt
~L
'~Dual CI\anIleI~[ll(JfMod&
~
"~Re$IlI!!IIit~~t
'MC3306!1
NlC3$Ql1.~
~A
~,A
JotIgh~~~I!'f
H!ghSlewllllte, WJu. ~ ~&ipJll\l
~~Ill\l
~!!Iew Rate, Wi!IIIanw!dih, Slngl&$uppIy
~~~
-$l$W_~~ $1ngl/l$ullPlY
:'''II'~~
~
~ tll9hJ)ul~t.QwPower,lo,w
1\IoIalI8lpo!it Qp.Alnp ,
MC33077
MC33078
MC33079
MC33091A
MC33092
MC33095
MC33102
Dual, Low Noise Operational Amplifier
DuaVQuad Low Noise Operational Amplifier
DuaVQuad Low Noise Operational Amplifier
High Side TMOS Driver
Alternator Voltage Regulator
Integral Alternator Regulator
Sleep-Mode Two-State, Micropower
Operational Amplifier
Low Voltage Compander
Low Voltage Compander with Mute and
Feedthrough
Subscriber Loop Interface Circuit
Low Voltage Subscriber loop Interface Circuit
Power Management Controller
MC33110
MC33111
MC33120
MC33121
MC33128
2-169
2-180
2-180
10-31
10-45
10-134
2-189
3-247
• = See Communications Device Data (DL 136),
# = Not recommended for new designs,
MOTOROLA ANALOG IC DEVICE DATA
1-3
•
Alphanumeric Index (continued)
MC33129
MC33143
MC33151
MC33152
MC33153
MC33154
MC33160
MC33161
MC33181
MC33182
MC33184
MC33282
MC33264
MC33293A
MC33298
MC33304
MC33340
High Performance Current Mode Controller
Dual High-Side Switch
High Speed Dual MOSFET Driver
High Speed Dual MOSFET Driver
Single IGBT Gate Driver
Single IGBT Gate Driver
Microprocessor Voltage Regulator and
Supervisory Circuit
Universal Voltaga Monitors
i
OpAmp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Mi-Bus Interface Stepper Motor Controller
Automotive Direction Indicator
Automotive Wash Wiper 11mer
Automotive ISO 9141 Serial Link Driver
Rail-te-Rall Operational Amplifier
Rall-te-Rail Operational Amplifier
Hall-te-·Rail oP"raliolonal Amplifier
i
OpAmp
Low Input Offset, High Slew Rate, Wide
Bandwidth, JFET Input Op Amp
Low Input Offset, High Slew Rate, Wide
Bandwidth, JFET Input Op Amp
Quad Low Side Switch
Octal Output Driver
Low Voltage RaIHe-Rall, Sleepmode
Operational Amplifier
Battery Fast
3-502
10-45
3-517
3-525
3-2M
3-265
3-533
3-540
MC33345
MC33346
MC33347
MC33348
Lithium Battery Protection Circuh for One to
Four Cell Battery Packs
Lithium Battery Protection Clrcuh for Three or
Four Cell Battery Packs
Lithium Banery Protection Circuit for One or
TWo Cell Banery Packs
Lithium Banery Protection Circuit for One Cell
Banery Packs
3-319
3-331
3-332
3-342
2-299
2-299
2-299
MC34004, B
MC34010
MC34011A
MC34012
MC34014
JFET Input Operational Amplifier
Electronic Telephone Circuit
Electronic Telephone Circuit
Telephone Tone Ringer
Telephone Speech Network with Dialer
Interface
Cordless Universal Telephone Interface
Telephone Tone Ringer
Voice Switched Speakerphone Circuit
High
Single-Ended PWM Controller
2-265
MC34071,A
High Slew Rate, Wide Bandwichh,
Single-Supply Operational Ampllfler
High Slew Rate, Wide Bandwidth,
Single-5upply Operational Amplifier
High Slew Rate, Wide Bandwidth,
Single-Supply Operational Amplifier
High Slew Rate, Wide Bandwlchh, JFET Input
Operational Amplifier
High Slew Rate, Wide Bandwlchh, JFET Input
Operational Ampllfler
Wide Bandwlchh, JFET Input
I Slew
I
2-272
2-246
MC34072,A
2-246
MC34074, A
1Q-94
10-109
2-254
MC34080
3-293
MC34082
MC34081
2-272
2-272
2-288
2-288
2-288
• ~ See Communications Device Data (DL136).
# ~ Not recommended for new designs.
1-4
MOTOROLA ANALOG IC DEVICE DATA
Alphanumeric Index (continued)
'/'.'
~~
MC34083
MC34084
MC34085
MC34114
MC34115
MCM1ff
eMQW1§
l'UncIkIII
High Slew Rate, Wide Bandwidth, JFET Input
Operational Amplifier
High Slew Rate, Wide Bandwidth, JFET Input
Operational Amplifier
High Slew Rate, Wide Bandwidth, JFET Input
Operational Amplifier
Telephone Speech NetworK with Dialer
Interface
Continuously Variable Slope Delta
Modulator/Demodulator
MQ$4'/ii
M(;,$41~
~6D
~$1
,MC34m
MC34164
MC34165
MC34166
MC34167
MC34181
MC34182
MC34184
MC34216A
;,
MC44603
2-288
MC44604
2-288
MC44605
__
~
~
t:,
ln1ijlltOrlve!
,~=e
'~1ll
~
iI!ld
UtMtlIIIt~~
~ SWlWIliIlg Regulatnl'
Micropower Undervoltage Sensing Circuit
Power Switching Regulator
Power Switching Regulator
Power Switching Regulator
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Low Power, High Slew Rate, Wide Bandwidth,
JFET Input Op Amp
Programmable Telephone Line Interface Circuit
with Loudspeaker Amplifier
5.0 V, 200 M-Bit'Sec PR-/V Hard Disk Drive
Read Channel
Power Factor Controller
l::owet FaI1lor~r
~~ '11IImIna!OlReg!lIallir
U31
~~~aI/iI~W~
OI~
,
"
~J
~
,q!I~~rdVliJlll:l,~ i
~".~~lIIdlIo9r~'
S~MuIll$tantfard~~
bZ1lJ
~,
~.
~
~
~1i:H/jdeQ $lgt:la1~Wllh
;~4intl
.
~~?JItI')
IJn$
MC#144
MC44145
MC44353
MC44354
MC44355
MC44461
MC44462
MC44463
MC44602
P1Wlfr.Lboke'dLaqp
7-118
~12
~~
$-641
...
-
.~
k'l26
Pixel Clock Generator/Sync Separator
PLL Tuned UHF AudioNideo Modulator ICs for
PAL, SECAM and NTSC TV Systems
PLL Tuned UHF AudioNideo Modulator ICs for
PAL, SECAM and NTSC TV Systems
PLL Tuned UHF AudioNideo Modulator ICs for
PAL, SECAM and NTSC TV Systems
Picture-in-Picture (PIP) Controller
Y-C Picture-in-Picture (PIP) Controller
Picture-in-Picture (PIP) Controller
High Performance Current Mode Controller
MCf9Q7$
MO¢F7907il
~O
SAA1ll42
SG3525A
SG3526
SG3527A
SN75175
TCA0372
TCA3385
TCA3388
TCA5600
TCF5600
~
~
TCF6000
"YDAiOl!S¢
1T.lAtl&w'
'Wli2 '
~,
".,
1\011C,J;O
9-331
9-338
"rl..o12c, AO
9-338
~iAc
J'1.Qe4C, At;
9-338
9-341
9-354
9-360
3-651
~
~\II
~~(.Th~
Quad:£:1A-48ll LIiie Dliveh\1ll'l ~
a
-
3-667
~89
~90
9-367
9-374
9-381
9-388
9-395
9-396
9-397
~
1"i20
MIIEI
7-146
OUlpllt
MCT~
'~7'I
,~
~
~7.2l
MCC3334
MC'CFa334
MOOF33093
2-299
Mixed Frequency Mode GreenLine PWM
Controller
High Safety Standby Ladder Mode GreenLine
PWM Controller
High Safety Latched Mode GreenLine PWM
Controller for (Multi) Synchronized
Applications
PLL Tuning Circuit with 3-Wire Bus
PLL Tuning Circuit with 12C Bus
PLL Tuning Circuit with 12C Bus
PLL Tuning Circuit with 12C Bus
PLL Tuning Circuit with 3-Wire Bus
PLL Tuning Circun with 12C Bus
PLL Tuning Circun with 12C Bus
,PI.J..~~.j..sft~artd
~16\l
Ma1617i48
2-299
I'IInOIIIIII
'~~,.'
AtJgm\ent
' ,
3-564
3-570
3-584
3-598
2-299
~~!'l$plaj~~
MC34261
MC44817, B
MC44818
MC44824,25
MC44826
MC44827
MC44828
MC44829
':MC44$64
3-55l)
..
MC34250
Pm..
&ntbtl'
2-288
TelepliOtll'TO!!fII'll.
, ~~~.qJrouII,
~19
~m
~
,.
1l.O14(1; AC
TJ.081(l,AC
TL431, A, B
Series
TL494
TL594
ElecttonIc 19ni11enCol'ltRllthip
Hlghinergy Ignition CifCIdt
HIgh EnfIrgy 19n1lllJn~
1Q..l$1
111-1&
10-15
~~
,0-,32
' ~~&!br~t
~1fiitl1l1\'CoIItIolC/ijp
10-<1'34
'f&.-131
HQ
Oual WIde ~OpeIltWAmpIifier
:!-iSS
~eo,rtol~1p
1n~HtgM~
OuaI'
Al'n/lIItIiir
$IiIpper M!lIDtl»iYet
Pulse Width Modulator Control Circuit
Pulse Width Modulator Control Circuit
Pulse Width Modulator Control Circuit
Quad EIA-485 Line Receiver
Dual Power Operational AmplHier
Tel$phone Ring Signal Converter
Telephone Speech Network
Universal Microprocessor Power
Supply/Controller
Universal Microprocessor Power
Supply/Controller
Peripheral Clamping Array
'\l~MQIof~~i
~-~
but~Al\'IpII\let
1npu\~1jmpIIiier
lnpUI~~
~'IilIils9~~~AmpJlller
~m,~~
~1fJ~AmpIlfJer
JmInPul~~
,m II\Plit~ArnpI1!iet
Programmable Precision References
Switchmode Pulse Width Modulation Control
Circun
Precision Switchmode Pulse Width Modulation
Control Circuit
104$3
4-Q2 .
~91
~97
~91
7-157
2-308
3-705
3-705
HH44
IHI7
~1tl1
W1~
.....
'Wll!
~
io41t
'.H'&
,~
5-18
3-716
3-726
• = See Communications Device Data (DL136).
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
--------
1-5
•
Alphanumeric Index (continued)
UC3843A
UC3843B
UC3844
UC3844B
UC3845
UC3845B
UC3844B
UC3845
UC3845B
ULN2068#
High Performance Current Mode Controller
High Performence Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
High Performance Current Mode Controller
Quad 1.5 A Sinking High Current Switch
3-745
3-758
3-n2
3-785
3-n2
3-785
3-785
3-n2
3-785
7-162
• = See Communications Device Data (DL136).
# = Not recommended for new designs.
1'-6
MOTOROLA ANALOG IC DEVICE DATA
Cross References
The following table represents a cross reference guide for all
Analog devices that are manufactured by Motorola. Where the
Motorola part number differs from the industry part
p~~~~~er
Motorola Nearest
Replacement
Motorola Similar
Replacement
number, the Motorola device is a ''form, fit and function"
replacement for the industry part number. However, some
differences in characteristics and/or specifications may exist.
P~~'W~?;er
Motorola Nearest
Replacement
75175
SN75175
CS2845D
UC2845BD1
9636AT
MC3488AP
CS3842AD
UC3842BD1
9640PC
MC26S10P#
CS3843AD
UC3843BD1
9667PC
MC1413P
CS3844D
UC3844BD1
9668PC
MC1416P
CS3845D
UC3845BD1
Motorola Similar
Replacement
AD589J
LM385Z-1.2
DM8822N
MC1489AP
AD589K
LM385Z-1.2
DS1233M
MC34064P-5
AD589L
LM385Z-1.2
DS1488N
MC1488P
AD589M
LM385BZ-1.2
DS1489AN
MC1489AP
AM201AD
LM201AN
DS1489N
MC1489P
AM201D
LM201AN
DS26LS32N
AM26LS32P#
AM26LS30P
AM26LS30PC
DS26S10CN
MC26S10P#
AM26LS31CJ
AM26LS31 PC#
DS3650N
MC3450P#
AM26LS31CN
AM26LS31 PC#
DS8834N
MC8T26AP
AM26LS32ACJ
AM26LS32D#
DS8835N
MC8T26AP
AM26LS32ACN
AM26LS32PC#
DS9636ACN
AM26LS32PC
AM26LS32PC#
ICL741CLNPA
MC1741CP1
AM723PC
MC1723CP
ICL741CLNTY
MC1741CP1
MC3488AP1
AN5150
MC34129P
ICL8008CPA
LM301 AN
CA081AE
TL081ACP
ICL8008CTY
LM301AN
CA081E
TL081CP
ICL8017CTW
LM301AN
CA082AE
TL082ACP
ICL8017MTW
LM301AN
CA082E
TL082CP
ICL8069CCZR
LM385BZ-1.2
CA084AE
TL084ACN
ICL8069DCZR
CA084E
TL084CN
IP33063N
MC33063AP1
LM385BZ-1.2
CA1391E
MC1391P
IP34060AN
MC34060AP
CA1458S
MC1458CP1
IP34063N
MC34063AP1
CA239AE
LM239AN
IP3525AN
SG3525AN
CA239E
LM239N
IP3526N
SG3526N
SG3527AN
CA3026
CA3054
IP3527AN
CA3045F
MC3346P
LM240LAZ-18
MC78L18ACP
CA3046
MC3346P
LM240LAZ-24
MC78L24ACP
CA3054
CA3054
LM240LAZ-5.0
MC78L05ACP
LM240LAZ--6.0
MC78L05ACP
CA3059
CA3059
LM240LAZ--8.0
MC78L08ACP
CA3079
CA3079
LM249N
CA3058
CA3059
MC4741CP
CA3086F
MC3346P
LM2575
LM2575
CA3136A
MC3346P
LM258D
LM258D
CA3146
MC3346P
LM258M
LM258D
CA339AE
LM339AN
LM258N
LM258N
CA339E
LM339N
LM285Z-1.2
LM285Z-1.2
CA723CE
MC1723CP
LM285Z-2.5
LM285Z-2.5
CA741CS
MC1741CP1
LM2901D
LM2901D
CS2842AD
UC2842BD1
LM2901M
LM2901D
CS2843AD
UC2843BD1
LM2901N
LM2901N
CS2844D
UC2844BD1
LM2902D
LM2902D
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-7
II
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacement
P~~'l.l'~~ber
Motorola Nearest
Replacement
IP494ACJ
TL5941N
LM2903N
LM2903N
IP494ACN
TL594CN
LM2903P
LM2903N
IR3M03A
MC34063APl
LM2904M
LM2904D
IR3M03AN
MC34063AD
LM2904N
LM2904N
ITT371 0
MC1391P
LM2905N
ITT656
L144AP
L203
LM2931AD-S,0
MC1413P
LM324N
MC1413P
L387
MC33267T
Motorola Similar
Replacement
MC1455Pl
LM2931 AD-5.0
LM2931AT-5.0
LM2931 AT-5,0
LM2931AZ-5.0
LM2931AZ-5.0
LM2931CD
LM2931CD
LF347BN
LF347BN
LM2931CM
LM2931CD
LF347N
LF347N
LM2931CT
LM2931CT
LM2931D-5.0
LM2931 D-5,0
LF351N
LF351N
LM2931D
LM2931D-5,0
LF353AN
MC34002AP
LM2931T-5.0
LM2931T-5.0
LF353BN
MC34002BP
LM2931Z-5.0
LM2931Z-5,0
LF353D
LF353D
LM2935T
LM2935T
LF353N
LF353N
LM293D
LM293D
LF411CD
LF411CD
LM301AD
LM301AD
LF412CD
LF412CD
LM301AM
LM301AD
LF441CD
LF441 CD
LM301AN
LM301AN
LF441CN
LF441CN
LM301AP
LM301AN
LF442CD
LF442CD
LM3045
MC3346P
LF442CN
LF442CN
LM3046N
MC3346P
LF444CD
LF444CD
LM3054
CA3054
LF351BN
MC34001BP
LF444CN
LF444CN
LM30BAD
LM308AD
LMllCLN
LMllCLN
LM30BAN
LM308AN
LMllCN
LMllCN
LM30BP
LM139N
MC1391P
LM311D
LM311D
LM1489AN
MC1489AP
LM311M
LM311D
LM1489N
MC1489P
LM311N
LM311N
LM1496N
MC1496P
LM311P
LM311N
LM1496M
MC1496D
LM3146A
LM1889
MC1374P
LM3146
LM1981
MC13020P
LM317KC
MC3356P
MC3346P
MC3346P
LM317T
LM201AD
LM201AD
LM317KD
LM201AN
LM201AN
LM317LD
LM317LD
LM317LZ,
LM317LZ
LM201AP
LM201AN
LM317T
LM211D
LM211D
LM317MP.
LM211M
LM211D
LM317P
LM224D
LM224D
LM317T
LM224M
LM224D
LM3189
MC3356P
LM224N
LM224N
LM320LZ-12
MC79L12ACP
LM239AN
LM239AN
LM320LZ-15
MC79L15ACP
LM239D
LM239D
LM320LZ-5.0
MC79L05ACP
LM239M
LM239D
LM320MP-12
MC7912CT
LM239N
LM239N
LM320MP-15
MC7915CT
LM317MT
LM317T
LM317T
LM240LAZ-12
MC78L12ACP
LM320MP-18
MC7918CT
LM240LAZ-15
MC78L15ACP
LM320MP-24
MC7924CT
MC78L05ACP
LM2902M
LM2902D
LM340LAZ-5.0
LM2902N
LM2902N
LM340LAZ-£.0
LM2903D
LM2903D'
LM340T-12
LM340T:"12
LM2903M
LM2903D
LM340T-15
LM340T-15
MC78L08ACP
/I = Nol recommended for new designs,
1-8
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
P~~~~~~r
Motorola Nearest
Replacement
Motorola Similar
Replacement
P~~~~~~
Motorola Nearest
Replacement
Motorola Similar
Replacement
LM320MP-5.0
MC790SCT
LM348D
LM348D
LM320MP-5.2
MC790S.2CT
LM348M
LM348D
LM320MP-6.0
MC7906CT
LM349N
LM320MP-8.0
MC7908CT
LM350T
LM320T-12
MC7912CT
LM358AN
LM320T-15
MC7915CT
LM358D
LM358D
LM320T-5.0
MC7905CT
LM358N
LM3S8N
LM320T-5.2
MC7905.2CT
LM363AN
MC3450P#
LM322N
MC145SPI
LM363N
MC34S0P#
MC4741CP
LM3S0T
LM358N
LM323AT
LM323AT
LM3858Z-1.2
LM323T
LM323T
LM385BZ-2.5
LM3858Z-2.S
LM324AD
LM324AD
LM38SD-l.2
LM38SD-l.2
LM324AN
LM324AN
LM385D-2.S
LM385D-2.5
LM324D
LM324D
LM385M-l.2
LM385D-l.2
LM324M
LM324D
LM38SM-2.S
LM38SD-2.S
LM324N
LM324N
LM385Z-1.2
LM38SZ-1.2
LM385Z-2.S
LM385Z-2.S
LM337MP
LM337MT
LM38S8Z-1.2
LM337MT
LM337MT
LM386N
MC34119P
LM337T
LM337T
LM3905N
MC14SSPI
LM339AD
LM339AD
LM393AN
LM393AN
LM339AM
LM339AD
LM393D
LM393D
LM339AN
LM339AN
LM393JG
LM339D
LM339D
LM393M
LM339N
LM339N
LM339P
LM339N
LM393N
LM393D
LM393N
LM393N
LM431ACZ
TL431 ACLP
TL431ACD
LM340AT-12
LM340AT-12
LM431ACM
LM340AT-15
LM340AT-15
LM42S0CN
LM340AT-5.0
LM340AT-S.O
LMSSSCN
MC14SSPI
LM340KC-12
LM340T-12
LMSS6CN
MC34S6P
LM340KC-15
LM340T-IS
LM703LN
LM340LAZ-12
MC78L12ACP
LM723CN
LM340LAZ-18
MC78L18ACP
LM741EN
LM340LAZ-24
MC78L24ACP
LM780SCT
MCI776CPl
MC1350P
MC1723CP
MC1741CPl
MC780SCT
LM340T-18
LM340T-18
LM7812CT
MC7812CT
LM340T-24
LM340T-24
LM781SCT
MC781SCT
LM340T-5.0
LM340T-5.0
LM78LOSACZ
MC78LOSACP
LM340T-6.0
LM340T-6.0
LM78LOSCZ
MC78LOSCP
LM340T-8.0
LM340T-8.0
LM78L08ACZ
MC78L08ACP
LM78L08CZ
MC78L08CP
LM341P-12
MC78M12CT
LM341P-15
MC78M15CT
LM78L12ACZ
MC78L12ACP
LM341P-18
MC78M18CT
LM78L12CZ
MC78L12CP
LM341P-24
MC78M24CT
LM78L1SACZ
MC78L1SACP
LM341P-5.0
MC78M05CT
LM78L1SCZ
MC78L1SCP
LM341P-6.0
MC78M06CT
LM78L18ACZ
MC78L18ACP
LM341P-8.0
MC78M08CT
LM78L18CZ
MC78L18CP
LM342P-12
MC78M12CT
LM78L24ACZ
MC78L24ACP
LM342P-15
MC78M15CT
LM78L24CZ
MC78L24CP
LM342P-18
MC78M18CT
LM78MOSCP
MC78MOSCT
LM342P-24
MC78M24CT
LM78M06CP
MC78M06CT
LM342P-5.0
MC78M05CT
LM78M12CP
MC78M12CT
LM342P-6.0
MC78M06CT
LM78M1SCP
LM342P-8.0
MC78M08CT
LM790SCT
MC78M15CT
MC790SCT
It = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-9
II
II
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacemllnt
Industry
Part Number
Motorola Nearest
Replacement
LM7912CT
MC7912CT
NE550A
LM7915CT
MC7915CT
NE555D
MC1455D
Motorola Similar
Replacement
MC1723CP
LM79L05ACZ
MC79L05ACP
NE555V
MC1455P1
LM79L12ACZ
MC79L12ACP
NE556D
NE556D
LM79L15ACZ
MC78L15ACP
NE5561N
MC34060AP
LM79M05CP
MC79M05CT
NE5234D
MC33204D
LM79M12CP
MC79M12CT
NE5234P
MC33204P
LM79M15CP
MC79M15CT
OP-01P
MC1436P1
LM833D
LM833D
RC1458DN
MC1458P1
LM833N
LM833N
RC4136DP
MC3403P
LM833P
LM833N
RC4136N
MC3403P
LM837N
MC33079P
RC4558DN
MC4558CP1
LMC6482D
MC33202D
RC4558P
MC4558CP1
LMC6482P
MC33202P
RC723DB
MC1723CP
LMC6484D
MC33204D
RC741DN
MC1741CP1
LMC6484P
MC33204P
RE5VL47A
MC34164P-5
LP2950CZ-3.0
LP2950CZ-3.0
RH5RE30AA-T1
MC78LC30HT1
LP2950CZ-3.3
LP2950CZ-3.3
RH5RE33AA-T1
MC78LC33HT1
LP2950CZ-5.0
LP2950CZ-5.0
RH5RE40AA-T1
MC78LC4OHT1
LP2950ACZ-3.0
LP2950ACZ-3.0
RH5RE50AA-T1
MC78LC50HT1
LP2950ACZ-3.3
LP2950ACZ-3.3
RN5RG30AA-TR
MC78BC30NTR
LP2950ACZ-5.0
LP2950ACZ-5.0
RN5RG33AA-TR
MC78BC33NTR
LP2951CM
LP2951CD
RN5RG40AA-TR
MC78BC40NTR
LP2951ACM
LP2951ACD
RN5RG50AA-TR
MC78BC50NTR
LP2951CM-3.0
LP2951CD-3.0
RH5RH301 A-T1
MC33466H-3OJT1
LP2951CM-3.3
LP2951CD-3.3
RH5RH302B-T1
MC33466H-30LT1
LP2951 ACM-3.0
LP2951 ACD-3.0
RH5RH331A-T1
MC33466H-33JT1
LP2951 ACM-3.3
LP2951 ACD-3.3
RH5RH332B-T1
MC33466H-33LT1
LP2951CN
LP2951CN
RH5RH501 A-T1
MC33466H-50JT1
LP2951ACN
LP2951ACN
RH5RH502B-T1
MC33466H-50LT1
LP2951CN-3.0
LP2951CN-3.0
RH5RI301 B-T1
MC33463H-30KT1
LP2951CN-3.3
LP2951CN-3.3
RH5RI302B-T1
MC33463H-30LT1
LP2951 ACN-3.0
LP2951 ACN-3.0
RH5RI331 B-T1
MC33463H-33KT1
LP2951 ACN-3.3
LP2951 ACN-3.3
RH5RI332B-T1
MC33463H-33LT1
RH5R1501B-T1
MC33463H-50KT1
RH5R1502B-T1
MC33463H-50LT1
LT1083
LT1431CZ
MC34268DT
TL431BCLP
LTC699CN8
MC34064D-5
RH5RL30AA-T1
MC78FC30HT1
LTC6991N8
MC33064D-5
RH5RL33AA-T1
MC78FC33HT1
MAX809LCPA
MC34064P-5
RH5RL40AA-T1
MC78FC4OHT1
MB3759
TL494CN
RH5RL50AA-T1
MC78FC50HT1
N5558V
MC1458P1
RH5VT09AA-T1
MC33464H-09AT1
N5723A
MC1723CP
RH5VT20AA-T1
MC33464H-20AT1
N5741 A
MC1741CP1
RH5VT27AA-Tl
MC33464H-27AT1
N5741V
MC1741CP1
RH5VT30AA-Tl
MC33464H-30ATl
N8T26AB
MC8T26AP
RH5VT45AA-Tl
MC33464H-45ATl
N8T26AN
MC8T26AP
RH5VT09CA-Tl
MC33464H-09CTl
N8T26B
MC8T26AP
RH5VT20CA-Tl
MC33464H-2OCT1
N8T26N
MC8T26AP
RH5VT27CA-T1
MC33464H-27CT1
N8T97B
MC8T97P
. RH5VT30CA-T1
MC33464H-30CTl
N8T97N
MC8T97P
RH5VT45CA-Tl
MC33464H-45CTl
N8T98B
MC8T98P
RN5RL30AA-TR
MC78FC30NTR
N8T98N
MC8T98P
RN5RL33AA-TR
MC78FC33NTR
# = Not recommended for new designs.
1-10
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacement
Industry
Part Number
Motorola Nearest
Replacement
RN5RL40AA-TR
MC78FC40NTR
SG723CN
MC1723CP
RN5RL50AA-TR
MC78FC50NTR
SG741CM
MC1741CP1
RN5VD09AA-TR
MC33465N--{)9ATR
SG777CN
RN5VD20AA-TR
MC33465N-20ATR
SG7805ACP
RN5VD27 AA-TR
MC33465N-27ATR
SG7805ACR
RN5VD30AA-TR
MC33465N-30ATR
SG7805ACT
RN5VD45AA-TR
MC33465N-45ATR
SG7805CP
MC7805CT
MC7806ACT
RN5VD09CA-TR
MC33465N--{)9CTR
SG7806ACP
RN5VD20CA-TR
MC33465N-20CTR
SG7806ACR
RN5VD27CA-TR
MC33465N-27CTR
SG7806ACT
RN5VD30CA-TR
MC33465N-30CTR
SG7806CP
RN5VD45CA-TR
MC33465N-45CTR
SG7806CR
RN5VT09AA-TR
MC33464N--{)9ATR
SG7808ACP
RN5VT20AA-TR
MC33464N-20ATR
SG7808ACT
RN5VT27 AA-T4
MC33464N-27ATR
SG7808CP
RN5VT30AA-TR
MC33464N-30ATR
SG7808CR
RN5VT45AA-TR
MC33464N-45ATR
SG7812ACP
RN5VT09CA-TR
MC33464N--{)9CTR
SG7812ACR
RN5VT20CA-TR
MC33464N-20CTR
SG7812ACT
RN5VT27CA-TR
MC33464N-27CTR
SG7812CP
RN5VT30CA-TR
MC33464N-30CTR
SG7812CR
RN5VT45CA-TR
MC33464N-45CTR
SG7815ACP
S-S0743AN
SA555N
MC34164P-3
MC1455BP1
SAA1042
SAA1042V
SG7815CP
MC1496P
SG7815CT
SG1596J
MC1496BP
SG7818ACP
SG201AM
LM201AN
SG301AM
LM201AN
SG308AM
LM201AN
MC1723CP
LM301AN
LM308AN
MC7812ACT
MC7812ACT
MC7812CT
MC7812CT
MC7815ACT
MC7815CT
MC7815CT
MC7815CT
MC7818ACT
MC7818ACT
MC7818ACT
MC7818CT
MC7818CT
MC7824ACT
SG7824ACR
MC7824ACT
SG7824ACT
MC7824ACT
SG7824CP
SG7905.2CP
SG311M
LM311N
SG7905.2CR
SG317P
LM317T
SG7905.2CT
LM317T
SG7905ACP
SG324N
LM324N
SG7905ACR
SG337P
LM337T
SG7905ACT
SG337R
MC7808CT
MC7812ACT
MC7824CT
SG7824CR
LM308AN
SG317R
MC7808ACT
MC7808CT
SG7818CR
SG7824ACP
LM301AN
SG3118AM
MC7806CT
MC7808ACT
SG7818ACT
SG7818CP
LM224N
SG301AN
MC7806ACT
MC7806CT
SG7818ACR
LM201AN
SG300N
MC7806ACT
MC7815ACT
SG1496N
SG201N
MC7805ACT
MC7815ACT
SG7815CR
SG224N
MC7805ACT
SG7815ACR
MC1458P1
SG201M
LM308AN
MC7805ACT
SG7815ACT
SG1458M
SG201AN
Motorola Similar
Replacement
LM337T
SG7905CP
MC3423P1
MC7824CT
MC7905.2CT
MC7905.2CT
MC7905.2CT
MC7905ACT
MC7905ACT
MC7905ACT
MC7905CT
SG7905CR
MC7905CT
SG3525AN
SG3525AN
SG7905CT
MC7905CT
SG3526N
SG3526N
SG7908CP
SG3527AN
SG3527AN
SG7908CR
MC7908CT
SG3561
MC34261P
SG7908CT
MC7908CT
SG3423M
SG4250CM
MC1776CP1
SG7912ACP
MC7908CT
MC7912ACT
SG555CM
MC1455P1
SG7912ACR
MC7912ACT
SG556CN
MC3456P
SG7912ACT
MC7912ACT
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-11
II
Cross References (continued)
pa~dN'~t.r
SG7912CP
Motorola Nearest
II$IIlacement
Motorola Similar
Replacement
MC7912CT
p~~~~~r
Motorola Neareat
Replacement
Motorola Similar
Replacement
TA7BLOOBAP
MC7BLOBACP
SG7912CR
MC7912CT
TA7BLOOBP
MC7BLOBCP
SG7912CT
MC7912CT
TA7BL012AP
MC7BL12ACP
TA7BL012P
MC7BL12CP
MC7915ACT
TA7BL015AP
MC7BL15ACP
MC7915ACT
TA7BL015P
MC7BL15CP
TA7BL01BAP
MC7BL1BACP
SG79015ACP
MC7915ACT
SG7915ACR "
SG7915ACT
SG7915CP
MC7915CT
SG7915CR
MC7915CT
TA7BL01BP
MC7BL1BCP
SG7915CT
MC7915CT
TA7BL024AP
MC7BL24ACP
SG791BCP
MC791BCT
SN75LBCOB6
TA7BL024P
MC7BL24CP
MC34055DW
TA7BM05P
MC7BM05CT
SN75121N
MC34B 1/5P#
TA7BM06P
MC7BM06CT
SN75126N
MC34Bl/5P#
TA7BMOBP
MC7BMOBCT
SN75150N
MC14BBP'
TA7BM12P
MC7BM12CT
SN75154N
MC14B9P
TA7BM1BP
MC7BM1BCT
SN75174N
MC75174BP
TA7BM20P
MC7BM20CT
SN75175N
SN75175N
TA7BM24P
MC7BM24CT
SN751BBN
MC14BBP
TA79005P
MC7905CT
SN751B9AN
MCl4B9AP
TA79006P
MC7906CT
SN751B9N
MCl4B9P
TA7900BP
MC790BCT
SN7546BN
MC1413P
TA79012P
MC7912CT
SN76591P
MC1391P
TA79015P
MC7915CT
SN76600P
MC1350P
TA7901BP
MC791BCT
SSS201AP
LM201AN
TA79024P
MC7924CT
"
SSS301AP
LM301AN
TA79LOO5P
TA7504P
MC1741CPl
TA79L012P
MC79L05CP
MC79L12P
TA7506P
LM301AN
TA79L015P
MC79L15P
TA75071P
MC34001P
TA79L01BP
MC79L1BP
TA75072P
MC34002P
TA79L024P
MC79L24P
TA75074F
MC34004P
TB920
MC1391P
TA75339F
LM339D
TBA920S
TA75339P
LM339N
TCF5600
MC1391P
TCF5600
TA7535BCF
LM35BD
TD62003P/AP
MC1413P
TA7535BCP
LM35BN
TD62479P
MC1374P
TDA1085C
TA75393F
LM393D
TDA10B5C
TA75393P
LM393N
TDA1085
TA7545BF
MC145BD
TDA1185A
TA7545BP
MC145BCPl
TDA4817
MC34261P
TA7555BP
MC455BCPl
TDC101B
MC10324P
TA7555F
MC1455D
TDC104B
TA7555P
MC1455Pl
TKl15
TA75902F
LM324D
TA7BOO5AP
MC10319P
MC33264
TL022CP
TL4941N
TA76494P
TDA10B5C
TDA1185A#
LM35BN
TL044CJ
LM324N
MC7B05CT
TL062ACP
TL062ACP
TA7B006AP
MC7B06CT
TL062CD
TL062CD
TA7BOOBAP
MC7BOBCT
TL062CP
TL062CP
TA7BOl2AP
MC7B12CT
TL062VP
TL062VP
TA7B015AP
MC7B15CT
TL064ACD
TL064ACD
TA7B01BAP
MC7B1BCT
TL064ACN
TL064ACN
TA7B024AP
MC7B24CT
TL064CD"
TL064CD
TA7BL005AP
MC7BL05ACP
TL064CN
TL064CN
TA7BLOO5P
MC7BL05CP
TL064VN
TL064VN
# = Not recommended for new designs,
1-12
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
Industry
Part Number
Motorola Nearest
Replacement
Motorola Similar
Replacement
p~~dJ~~~er
Motorola Nearest
Replacement
Motorola Similar
Replacement
TL071ACD
TL071ACD
!1A4136PC
TL071ACP
TL071ACP
!1A431AWC
MC4741CP
TL071CD
TL071CD
!1A4558TC
MC4558CP1
TL071CP
TL071CP
!1A494PC
TL494CN
TL072ACD
TL072ACD
!1A555TC
MC1455P1
TL072ACP
TL072ACP
!1A556PC
MC3456P
TL072CD
TL072CD
!1A723CN
MC1723CP
TL072CP
TL072CP
!1A723PC
MC1723CP
TL074ACN
TL074ACN
!1A741CP
MC1741CP1
TL074CN
TL074CN
I1A742DC
CA3059
TL081ACD
TL081ACD
I1A757DC
MC1350P
TL081ACP
TL081ACP
I1A757DM
TL081CD
TL081CD
I1A775PC
LM339N
TL081CP
TL081CP
I1A776TC
MC1776CP1
TL082ACP
TL082ACP
!1A7805CKC
MC7805CT
TL082CD
TL082CD
!1A7805UC
MC7805CT
TL082CP
TL082CP
!1A7805UV
MC7805BT
TL084ACN
TL084ACN
!1A7806CKC
MC7806CT
TL084CN
TL084CN
!1A7806UC
MC7806CT
TL431CD
TL431CD
!1A7806UV
MC7806BT
TL431CLP
TL431CLP
!1A7808CKC
MC7808CT
TL431CP
MC1350P
TL431CP
TL431CP
!1A7808UC
MC7808CT
TL4311LP
TL4311LP
!1A7808UV
MC7808BT
TL4311P
TL4311P
11A7812CKC
MC7812CT
TL494CN
TL494CN
I1A7812UC
MC7812CT
TL4941N
TL4941N
I1A7812UV
MC7812BT
I1A781 5CKC
MC7815CT
MC34063AP1
TL497CN
TL594CN
TL594CN
I1A7815UC
MC7815CT
TL5941N
TL5941N
I1A781 5UV
MC7815BT
TL780-05CKC
TL780-05CKC
I1A7818CKC
MC7818CT
TL780-12CKC
TL780-12CKC
!1A7818UC
MC7818CT
TL780-15CKC
TL780-15CKC
!1A7818UV
MC7818BT
TL7805ACKC
MC7805ACT
I1A7824CKC
MC7824CT
TLC2272D
MC33202D
I1A7824UC
MC7824CT
TLC2272P
MC33202P
I1A7824UV
MC7824BT
TLC2274D
MC33204D
I1A78GU1C
TLC2274P
MC33204P
I1A78GUC
!1A1391PC
MC1391P
I1A78L05ACLP
!1A1458CP
MC1458CP1
I1A78L05AWC
!1A1458CTC
MC1458CP1
I1A78L05CLP
!1A1458P
MC1458P1
I1A78L05WC
!1A1458TC
MC1458P1
11A78L08ACLP
MC1455P1
!1A2240PC
!1A301AT
LM301AN
LM317T
LM317T
MC78L05ACP
MC78L05ACP
MC78L05CP
MC78L05CP
MC78L08ACP
11A78L08AWC
MC78L08ACP
11A78L08CLP
MC78L08CP
MC78L12ACP
!1A3026HM
CA3054
11A78L12ACLP
!1A3045
MC3346P
11A78L12AWC
!1A3046DC
MC3346P
!1A78L12CLP
!1A3054DC
CA3054
!1A78L12WC
!1A311T
LM311N
!1A78L15ACLP
I1A317UC
LM317T
I1A78L15AWC
I1A3303P
MC3303P
I1A78L15CLP
I1A3403P
MC3403P
I1A78L15WC
MC78L12ACP
MC78L12CP
MC78L12CP
MC78L15ACP
MC78L15ACP
MC78L15CP
MC78L15CP
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-13
•
•
Cross References (continued)
p~~t'~~~
Motorola Naarast
Replacement
Motorola Similar
Replacament
p~~d~~~er
Motorola Nearest
Replacement
Motorola Similar
Replacement
~79M06AUC
MC79M06CT
J,lA78L24AWC
MC78L24ACP
~79M06CKC
MC79M06CT
J,lA78M05CKC
MC78M05CT
~79M06UC
MC79M06CT
~79M08AUC
MC79M08CT
MC79M08CT
J,lA78L18AWC
MC78L18ACP
J,lA78M05CKD
MC78M05CT
IlA78M05UC
MC78M05CT
~79M08CKC
J,lA78M06CKC
MC78M06CT
~79M08UC
IlA78M06CKD
MC78M06CT
MC79M08CT
~79M12AUC
MC79M12CT
MC79M12CT
IlA78M06UC
MC78M06CT
~79M12CKC
IlA78M08CKC
MC78M08CT
I1A79M18AUC
MC79M18CT
~79M18UC
MC79M18CT
MC78M08CT
IlA78M08CKD
J,lA78M08UC
MC78M08CT
~79M24AUC
MC79M24CT
J,lA78M12CKC
MC78M12CT
~79M24CKC
MC79M24CT
J,lA78M12CKD
MC78M12CT
J,lA78M12UC
MC78M12CT
J,IA78M 15CKC
MC78M15CT
~78M15CKD
MC78M15CT
~79M24UC
MC79M24CT
~9636ATC
MC3488AP1
UAA1016B
UAA1016B
UC2823DW
MC33023DW
~78M15UC
MC78M15CT
UC2823N
MC33023P
~78M18UC
MC78M18CT
UC2823Q
MC33023FN
~78M20CKC
MC78M20CT
UC2825DW
MC33025DW
~78M20CKD
MC78M20CT
~78M20UC
MC78M20CT
~78M24CKC
MC78M24CT
~78M24CKD
IlA78M24UC
UC2825N
MC33025P
UC28250
MC33025FN
UC2842AD
MC78M24CT
MC78M24CT
UC2842AD
UC2842AN
UC2842AN
UC2842BD
UC2842BD
~78MGT2C
LM317T
UC2842BN
UC2842BN
~78MGU1C
LM317T
UC2842D
UC2842AD
UC2842N
UC2842AN
~78MGUC
LM317MT
~78S40PC
~78S40PC
UC2843AD
UC2843AD
~78S40PV
~78S40PV
UC2843AN
UC2843AN
~7905.2CKC
MC7905.2CT
UC2843BD
UC2843BD
~7905CKC
MC7905CT
UC2843BN
UC2843BN
~7905UC
MC7905CT
UC2843D
UC2843AD
~7906CKC
MC7906CT
UC2843N
UC2843AN
~7906UC
MC7906CT
UC2844BD
UC2844BD
~7908CKC
MC7908CT
UC2844BN
UC2844BN
~7912CKC
MC7912CT
UC2844D
UC2844D
~7912UC
MC7912CT
UC2844N
UC2844N
~7915CKC
MC7915CT
UC2845BD
UC2845BD
~7915UC
MC7915CT
UC2845BN
UC2845BN
~7918CKC
MC7918CT
UC2845D
UC2845D
~7918UC
MC7918CT
UC2845N
UC2845N
I1A7924CKC
MC7924CT
UC317T
LM317T
I1A7924UC
MC7924CT
UC337T
LM337T
~798TC
MC3458P1
UC3525AN
SG3525AN
~79L05AWC
MC79L05ACP
UC3526N
SG3526N
~79L05WC
MC79L05CP
UC3527AN
SG3527AN
~79L12AWC
MC79L12ACP
UC3823DW
MC34023DW
~79L12WC
MC79L12CP
UC3823N
MC34023P
~79L15AWC
MC79L15ACP
UC3823Q
MC34023FN
~79L15WC
MC79L15CP
UC3825DW
MC34025DW
11A79M05AUC
MC79M05CT
UC3825N
MC34025P
11A79M05CKC
MC79M05CT
UC38250
MC34025FN
# = Not recommended for new designs.
1-14
MOTOROLA ANALOG IC DEVICE DATA
Cross References (continued)
P~~~~~?:er
Motorola Nearest
Replacement
Motorola Similar
Replacement
p~~~~~?:er
Motorola Nearest
Replacement
UC3842AD
UC3842AD
UC3845N
UC3842AN
UC3842AN
UC494ACN
UC3842BD
UC3842BD
UC494CN
UC3842BN
UC3842BN
UCN5816A
MC34142FN
UC3842D
UC3842AD
ULN2003A
MC1413
UC3842N
UC3842AN
ULN2004A
MC1416
UC3843AD
UC3843AD
ULN2068BB
ULN2068B#
UC3843AN
UC3843AN
ULN2068NE
ULN2068B#
UC3843BD
UC3843BD
ULN2151H
MC1741CP1
UC3843BN
UC3843BN
ULN2151M
UC3843D
UC3843AD
ULN2803A
Motorola Similar
Replacement
UC3845N
TL594CN
TL494CN
MC1741CP1
ULN2803A
UC3843N
UC3843AN
ULN2804A
ULN2804A
UC3844BD
UC3844BD
ULN8126A
SG3526N
UC3844BN
UC3844BN
ULS2151M
MC1741CP1
UC3844D
UC3844D
ULX8161M
MC34060AP
UC3844N
UC3844N
UPD6950C
MC10319P
UC3845BD
UC3845BD
UVC3101
MC10319P
UC3845BN
UC3845BN
XR082CP
TL082CP
UC3845D
UC3845D
XR084CP
TL084CN
# = Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
1-15
•
1-16
MOTOROLA ANALOG IC DEVICE DATA
Voltage References
In Brief ...
Motorola's line of precIsion voltage references is
designed for applications requiring high initial accuracy, low
temperature drift, and long term stability. Initial accuracies of
±1.0%, and ±2.0% mean production line adjustments can be
eliminated. Temperature coefficients of 25 ppm/DC max
(typically 10 ppm/DC) provide excellent stability. Uses for the
references include D/A converters, AID converters,
precision power supplies, voltmeter systems, temperature
monitors, and many others.
MOTOROLA ANALOG IC DEVICE DATA
Page
Precision Low Voltage References . . . . . . . . . . . . . . . . . . 5-2
Package Overview ............................... 5-2
Device Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
5-1
•
i
i
Precision Low Voltage References
A family of precision low voltage bandgap reference devices designed for applications requiring low temperature drift.
1Precision Low Voltage References
Vout
(V)
10
Voutff
(rnA)
Typ
Max
pprnfOC
Max
1.235± 12mV
1.235±25 mV
20
80Typ
Regllne
(mV)
Regloed
(mV)
0° to +70°C
-400 to +85°C
Max
Max
Package
LM385BZ-1.2
LM385Z-1.2
LM285Z-1.2
(Note 1)
1.0
(Note 2)
Z,D
LM385BZ-2.5
LM385Z-2.5
LM285Z-2.5
25
MC1403A
-
40
MC1403
5.0±50mV
40
MC1404P5
-
6.25±60mV
40
MC1404P6
-
10±100mV
40
MC1404P10
-
50Typ
TL431C, AC, BC
TL431I, AI, BI
2.5±38mV
2.5±75mV
2.5±25mV
II
Device
2.5 to 37
10
100
2.0
(Nole3)
3.0/4.5
(Note 4)
10
(Note 5)
D
6.0
(Note 6)
P
Shunt Reference
Dynamic Impedance
(z)':;0.5a
LP, P, D, DM
Notes: 1. Mlcropower Reference DIode DynamIc Impedance (z) S 1.0 II at IR = 100 IIA.
2.10 IIA S IR S 1.0 mA.
3.20 lIAS IR S 1.0mA.
4.4.5 Vs Yin S 15 Vl15 V s Vln S 40 V.
5. OmAs ILs 10 mAo
6. (Vout + 2.5 V) s vin S 40 V.
Voltage References Package Overview
I
CASE 29
LP,ZSUFFIX
5-2
~
CASE 626
PSUFFIX
~
•
CASE 751
o SUFFIX
CASE846A
OM SUFFIX
MOTOROLA ANALOG IC DEVICE DATA
Device Listing
Voltage References
Device
Function
Page
LM285, LM385, B
MC1403, B
MC1404
TL431 , A, B Series
Micropower Voltage Reference Diodes .............................. 5-4
Low Voltage Reference ............................................ 5-9
Voltage Reference Family ........................................ 5-13
Programmable Precision References .............................. 5-18
II
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
LM285
LM385,B
Micropower Voltage
Reference Diodes
11
The LM285/LM385 series are micropower two-terminal bandgap voltage
regulator diodes. Designed to operate over a wide current range of 10 !lA to
20 mA, these devices feature exceptionally low dynamic impedance, low
noise and stable operation over time and temperature. Tight voltage
tolerances are achieved by on-chip trimming. The large dynamic operating
range enables these devices to be used in applications with widely varying
supplies with excellent regulation. Extremely low operating current make
these devices ideal for micropower circuitry like portable instrumentation,
regulators and other analog circuitry where extended battery life is required.
The LM285/LM385 series are packaged in a low cost T0-226AA plastic
case and are available in two voltage versions of 1.235 and 2.500 V as
denoted by the device suffix (see Ordering Information table). The LM285 is
specified over a -40°C to +85°C temperature range while the LM385 is rated
from O°C to +70°C.
The LM385 is also available in a surface mount plastic package in
voltages of 1.235 and 2.500 V.
• Operating Current from 10 !lA to 20 rnA
• 1.0%, 1.5%, 2.0% and 3.0% Initial Tolerance Grades
MICROPOWER VOLTAGE
REFERENCE DIODES
SEMICONDUCTOR
TECHNICAL DATA
ZSUFFIX
PLASTIC PACKAG/
CASE 29
(Bottom View)
c:w
3
~21
N.C.
Cathode
Anode
OJ
DSUFFIX
PLASTIC PACKAGE
• Low Temperature Coefficient
CASE
751
(S0-8)
• 1.0 Q Dynamic Impedance
• Surface Mount Package Available
N C. 1
8 Cathode
NC 2
7 N.C.
N.C 3
6 NC
Anode 4
5 N.C.
~
Standard Application
1.SV
Battery
i-
+
Representative Schematic Diagram
'V
~
Open
f' for 1.235 V
~
/.
j..
600k
fa.
8.45k r,.-"
~
-==
10k
ORDERING INFORMATION
~
>~
~~
r--..
~
r--<
~
Device
LM285D-1.2
LM285Z-1.2
~
v
74.3k
Open
for 2.5 V
>-I
600 k
425 k
L
LM285D-2.5
LM285Z-2.5
~
~1.235V
'] ~ lM385-1.2
Cathode
360 k
3.3 k
600k
~[ v
r 1 1
o
v
""hi.
>--
~
soon
100k
>t:
Reverse
Operating
BreakTemperature down
Range
Voltage Tolerance
TA = -40° to
+85°C
LM385BD-1.2
LM385BZ-1.2
LM385D-1.2
LM385Z-1.2
LM385BD-2.5
LM385BZ-2.5
LM385D-2.5
LM385Z-2.5
TA=OOto
+70°C
1.235 V
±1.0%
2.500 V
±1.5%
1.235 V
±1.0%
1.235 V
±2.0%
2.500 V
±1.5%
2.500 V
±3.0%
Anode
5-4
MOTOROLA ANALOG IC DEVICE DATA
LM285 LM385, B
MAXIMUM RATINGS (TA = 25'C, unless otherwise noted)
Rating
Symbol
Value
Unit
IR
30
mA
Forward Current
IF
10
mA
Operating Ambient Temperature Range
LM285
LM385
TA
Reverse Current
Operating Junction Temperature
Storage Temperature Range
'c
-40to+85
Oto +70
TJ
+ 150
'c
Tstg
- 65 to + 150
°C
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted)
LM2S5-1.2
Characteristic
Reverse Breakdown Voltage (IRmin .;; IR .;; 20 mAl
LM285-1 .2ILM385B-l.2
TA = Tlow to Thigh (Note 1)
LM385-1.2
TA = Tlowto Thigh (Note 1)
Minimum Operating Current
TA=25°C
TA = Tlowto Thigh (Note 1)
Reverse Breakdown Voltage Change with Current
IRmin .;; IR ~ 1.0 mA, TA = +25'C
TA = Tlow to Thigh (Note 1)
1.0 mA ~ IR ~ 20 rnA, TA = +25°C
TA = Tlow to Thigh (Note 1)
Reverse Dynamic Impedance
IR = 100 !lA, TA = +25°C
Average Temperature Coefficient
10 I1A ~ IR ~ 20 mA, TA = Tlow to Thigh (Note 1)
Wideband Noise (RMS)
IR=I00!lA, 10Hz ~ f
~
Symbol
LM3S5-1.21LM385B-1.2
Min
Typ
Max
Min
Typ
Max
1.223
1.200
1.235
1.247
1.270
1.235
-
1.223
1.210
1.205
1.192
1.247
1.260
1.260
1.273
-
8.0
-
V
V(BR)R
IRmin
dV(BR)R
Unit
-
-
-
-
8.0
-
-
10
20
-
-
1.0
1.5
10
20
-
-
-
-
1.0
1.5
20
25
0.6
-
-
0.6
-
W
-
Z
-
1.235
-
!lA
-
15
20
mV
dV(BR)/dT
-
80
-
-
80
-
ppm/'C
n
-
60
-
-
60
-
I1V
S
-
20
-
-
20
-
ppm!
kHR
10kHz
Long Term Stability
IR = 100 !lA, TA = +25'C ± O.I'C
MOTOROLA ANALOG IC DEVICE DATA
II
LM285 LM385, B
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
LM285-2.5
Characteristic
Reverse Breakdown Voltage (IRmin '" IR '" 20 rnA)
LM285-2.51LM385B-2.5
TA = Tlowto Thigh (Note 1)
LM385-2.5
TA = Tlow to Thigh (Note 1)
Minimum Operating Current
TA = 25°C
TA = Tlow to ThiJ;lh (Note 1)
Reverse Breakdown Voltage Change with Current
II
Symbol
Typ
Max
Min
Typ
Max
2.462
2.415
2.5
2.538
2.585
2.5
-
2.462
2.436
2.425
2.400
-
2.538
2.564
2.575
2.600
20
30
-
13
20
-
30
-
1.0
1.5
10
20
-
-
2.0
2.5
20
25
0.6
-
-
0.6
-
W
Unit
V
V(BR)R
-
-
2.5
IRmin
-
13
-
-
-
aV(BR)R
IRmin '" IR '" 1.0 mA, TA = +25°C
TA = Tlow to Thigh (Note 1)
1.0 mA '" IR '" 20 mA, TA = +25°C
TA = Tlow to Thigh (Note 1)
Reverse Dynamic Impedance
IR = 100 ItA, TA = +25°C
LM385-2.51LM385B-2.5
Min
Z
-
J!A
mV
aV(BRyaT
-
80
-
-
80
-
ppm/°C
Wideband Noise (RMS)
IR=lOOI1A, 10Hz", f '" 10kHz
n
-
120
-
-
120
-
I1V
Long Term Stability
IR = 100 I1A, TA = +25°C ± O.l°C
S
-
20
-
-
20
-
Average Temperature Coefficient
20 ItA '" IR '" 20mA, TA = Tlow to Thigh (Note 1)
NOTES: 1. TJow = - 40°C for LM285-1.2, LM285-2.5
=O°C for LM385-1.2, LM385B-1.2, LM385-2.5, LM385B-2.5
ppm/
kHR
.
Thigh = +85°C for LM285-1.2, LM285-2.5
= +70°C for LM385-1.2, LM385B-1.2, LM385-2.5, LM385B-2.5
MOTOROLA ANALOG IC DEVICE DATA
LM285 LM385, B
TYPICAL PERFORMANCE CURVES FOR LM28!i-1.2/38S-1.21385B-1.2
Figure 1. Reverse Characteristics
Figure 2. Reverse Characteristics
~
100
UJ
(!)
«
z
c(
6
:J:
I-
Z
w
a::
a::
0
10
UJ
(!)
~
::>
0
w
CJ)
a::
w
>
w
a::
10
1111111
8.0
TA = + 85'C
IIIIIII
TA=+85~
1.0
!f.
+ 25'C.I'
0.1
o
0.4
~
0.6
0.8
~40'C
~;;;i
a:@.
.I' -40'C
1'1
0.2
ViI
+25'C
>
UJ
en 4.0
a::
UJ
>
2.0
UJ
a::
ci:
~ ~
lJ
I'j I
6.0
0
1.0
1.2
-2.0
1.4
0.01
0.1
V(BR), REVERSE VOLTAGE (V)
1.0
10
100
IR, REVERSE CURRENT (rnA)
Figure 3. Forward Characteristics
Figure 4. Temperature Drift
1.250
~
w
(!)
;:!:
:..J
~
1.2
~
w 1.240
0
a::
c(
0.6
12
~~C
0.4
r--
~
u:
>
0.2
_f-
o
0.01
~
~
TA=-4~
0.8
t::::ft
~
UJ
CJ)
a::
UJ
>
UJ
a::
~'C
r--
1.230
ci: 1.220
a:-
ID
:>
1.210
0.1
1.0
10
100
-50
-25
Figure 5. Noise Voltage
-
625
1.50
1.25
.....
~
50
75
~
1.00
~
0.75
~r....
/
125
Output
o 0.50
\
0.25
!!l
~ 375
c::
100
'~
)
:::>
W 500
CD
25
Figure 6. Response Time
875
750
0
TA, AMBIENTTEMPERATURE ('C)
IF ' FORWARD CURRENT (mA)
~
IR=100f,IA
-
(!)
1.0
DUT
""'~
\
250
~
'\1'.
125
o
10
'3
"~
100
1.0K
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
10K
lOOk
10
5.0
o
0.1
0.2
0.3
0.6
0.7
0.8
0.9
1.0
1.1
t, TIME (ms)
5-7
II
LM285 LM385, B
TYPICAL PERFORMANCE CURVES FOR LM285-2,5/385-2.S/385B-2.S
Figure 7. Reverse Characteristics
Figure 8. Reverse Characteristics
:[
100
w
:z
<.!:I
«
w
10
1111111
8.0
TA = +85°C
!:j
. TA +85~
"/
f= = +25°C
40°C
o
0.5
>
w
4.0
w
>
w
cc
2.0
c:
~
~:::
0
1.0
1.5
2.0
2.5
V(SR), REVERSE VOLTAGE (V)
3.0
3.5
0.01
0.1
Figure 9. Forward Characteristics
~
w
2.520
~
w 2.510
~
0.2
o
0.01
t:t::
1-11-1-
...
~
~
w
en 2.490
cc
w
2.480
iri
cc
c: 2.470
~ 2.460
I'
'2.450
1.0
10
IF ' FORWARD CURRENT (mA)
-
1500
~1250
>:
100
-{i0
-25
0
25
50
75
TA, AMBIENTTEMPERATURE ('C)
~
.....
en
J
~
c::
500
250
10
\
t,
1.0K
FREQUENCY (Hz)
10K
.....
o
'\~
~
~
~
100
125
lOOk
');'
Output
0.50
Q)
5-8
2.00
~ 1.50
/".
51.00
750
·100
Figure 12. Response Time
3.00
2.50
~1000
o
100.
cc
+25°C
0.1
-r--
2.500
§:!
V-,I
+85°C
I-
100
IR = 100 IlA
Figure 11. Noise Voltage
~
1.0
10
IR, REVERSE CURRENT (rnA)
Figure 10. Temperature Drift
1.2
<.!:I
~-40°C
+25°C
~
:;; -2.0
I
0.1
6.0
0
en
cc
,
~
i'il
<.!:I
1.0
II
10
1111111
:t:
U
--
DUT
10
5.0
o
0.1
0.2
0.3 0.6 0.7
t,TIME(ms)
0.8
0.9
1.0
1.1
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC1403, B
Low Voltage Reference
A precision band-gap voltage reference designed for critical
instrumentation and DJA converter applications. This unit is designed to work
with DJA converters, up to 12 bits in accuracy, or as a reference for power
supply applications.
PRECISION LOW VOLTAGE
REFERENCE
SEMICONDUCTOR
TECHNICAL DATA
• Output Voltage: 2.5 V ±25 mV
• Input Voltage Range: 4.5 V to 40 V
.~
• Quiescent Current: 1.2 mA Typical
• Output Current: 10 mA
• Temperature Coefficient: 10 ppmJoC Typical
1
• Guaranteed Temperature Drift Specification
• Equivalent to AD580
8~
• Standard 8-Pin DIP, and 8-Pin SOIC Package
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
II
o SUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
1
Typical Applications
• Voltage Reference for 8 to 12 Bit DJA Converters
PIN CONNECTIONS
• Low T C Zener Replacement
• High Stability Current Reference
NC
• Voltmeter System Reference
NC
NC
MAXIMUM RATINGS (TA ~ 25°C, unless otherwise noted.)
Rating
Symbol
Value
Unit
V
Input Voltage
NC
VI
40
Storage Temperature
Tstg
-65 to 150
°C
Junction Temperature
TJ
+175
°C
Device
Operating Ambient Temperature Range
MC1403B
MC1403
TA
°C
°C
MC1403D
MC1403P1
MC1403BD
MC1403BP1
-40 to +85
Oto+70
ORDERING INFORMATION
Operating
Temperature Range
TA~00to+70°C
TA ~ -40° to +85°C
Package
S0-8
Plastic DIP
S0-8
Plastic DIP
Figure 1. A Reference for Monolithic D/A Converters
r-------------------,
Full Scale
Adjust 500 Q
+5.0V 0----'-1
I
~+_~~--~~+_~r__T_4
'----,-----'
Monolithic D/A
I
Converter
~--~~
~k
Providing the Reference Current
for Motorola Monolithic D/A Converters
The MC1403 makes an ideal reference for many monolithic D/A converters, requiring a stable current reference of
nominally 2.0 rnA. This can be easily obtained from the
MC1403 with the addition of a series resistor, R1 . A variable
resistor, R2, is recommended to provide means for fullscale adjust on the D/A converter.
MOTOROLA ANALOG IC DEVICE DATA
L __________________
I
I
I
I
I
~
• Caution: System stability may be affected if output capacitance
exceeds 1.0 ~F. Using higher capacitance values is not
recommended and should be carefully considered.
The resistor R3 improves temperature performance by
matching the impedance on both inputs olthe D/A reference
amplifier. The capacitor decouples any noise present on the
reference line. It is essential if the D/A converter is located
any appreciable distance from the reference.
A single MC1403 reference can provide the required
current input for up to five of the monolithic D/A converters.
5-9
MC1403, B
ELECTRICAL CHARACTERISTICS (Vin = 15 V, TA = 25'C, unless O1herwise noted.)
Characteristic
Output VoHage
(IO=OmA)
Temperature Coefficient of Output VoHage'
MC1403
Output Voltage Change'
(Over specified temperature range)
MC1403
Oto +70'C
MC1403B -40to+85'C
Line Regulation (10 = 0 mAl
(15V", VI'" 40 V)
Symbol
Min
Typ
Max
Unit
Vout
2.475
2.5
2.525
V
!No/AT
-
10
40
ppm/'C
-
-
7.0
12.5
1.2
0.6
4.5
3.0
Regload
-
-
10
mV
IQ
-
1.2
1.5
mA
Regline
(4.5 V '" VI '" 15V)
II
Load Regulation
(OmA<10<10mA)
Quiescent Current
(10'= 0 mA)
mV
AVO
mV
'This test is not applicable to the MC1403D or MC1403BD surface mount devices.
Figure 2. MC1403, B Schematic
32
L---+--o
Vou!
1.5 k
1.483 k
This device contains 15 active transistors.
5-10
MOTOROLA ANALOG IC DEVICE DATA
MC1403, B
Figure 4. Change in Output Voltage
versus Load Current
(Normalized to Vout @ Vin = 15 V, lout = 0 mAl
Figure 3. Typical Change in Vout versus Vin
(Normalized to Vin
:i
=15 V @ TC =25'C)
2.0
~
1.0
W 9.0
(!J
'§
> -1.0
~
~ -2.0
--
I""""
~
~
25'C
10
;5 8.0
g 7.0
I
O'C- r---
~
6.0
o~
75'C- r---
--3.0
w
~
5.0
4.0
Ji --4.0
(!J
3.0
u
2.0
~
~
>0
-6.0
o
10
20
0
± 6%
• Wide Input Voltage Range: Vref + 2.5 V to 40 V
• Low Quiescent Current: 1.25 mA Typical
• Temperature Coefficient: 10 ppm/oC Typical
• Low Output Noise: 121lV p-p Typical
• Excellent Ripple Rejection: > 80 dB Typical
.~
Typical Applications
• Voltage Reference for 8 to 12 Bit 01A Converters
1
• Low T C Zener Replacement
• High Stability Current Reference
• MPU D/A and AID Applications
PSUFFIX
PLASTIC PACKAGE
CASE 626
Figure 1. Voltage Output 8-Bit DAC Using MC1404P10
PIN CONNECTIONS
+5.0
5.0 k
6
Ref I--'VVI~-,.--.......:"-I
In
MSB
+15
2
MC1404P10
4
BBit
DAC
Digital
Inputs
75pF
5.0k
Out 1------+""-1
ORDERING INFORMATION
Oto
+10V
LSB
Device
-15
MC1404P5
MC1404P6
MC1404P10
MOTOROLA ANALOG IC DEVICE DATA
Operating
Temperature Range
Package
Plastic DIP
TA = 0° to +70°C
Plastic DIP
Plastic DIP
5-13
MC1404
MAXIMUM RATINGS
Rating
Input Voltage
Symbol
Value
Unit
V
Vin
40
Storage Temperature
Tstg
-65to+150
°C
Junction Temperature
TJ
+175
°C
Operating Ambient Temperature Range
TA
Oto+70
°C
ELECTRICAL CHARACTERISTICS (Vin = 15 V, TA = 25°C, and Trim Terminal not connected, unless otherwise noted.)
Characteristic
Output VoHage
(10=0 rnA)
II
Symbol
Min
Typ
Max
4.95
6.19
9.9
5.0
6.25
10
5.05
6.31
10.1
MC1404P5
MC1404P6
MC1404P10
Unit
V
Vo
-
-
±0.1
±1.0
%
Output Trim Range (Figure 10)
(Rp= 100kQ)
AVTRIM
±6.0
-
-
%
Output Voltage Temperature Coefficient,
Over Full Temperature Range
AVo/AT
-
10
40
ppmfOC
-
-
Output Voltage Tolerance
Maximum Output Voltage Change
Over Temperature Range
mV
AVO
-
14
17.5
28
Line Regulation (Note 1)
(Vin = Vout + 2.5 V to 40 V, lout = 0 rnA)
Regline
-
2.0
6.0
mV
Load Regulation (Note 1)
(0", 10" 10 rnA)
Regload
-
-
10
mV
Quiescent Current
(lo=omA)
IQ
-
1.2
1.5
rnA
Short Circuit Current
Isc
-
20
45
rnA
-
-
25
-
ppm/1000 hrs
Long Term Stability
MC1404P5
MC1404P6
MC1404P10
-
-
-
NOTE: 1. Includes thermal effects.
DYNAMIC CHARACTERISTICS (Vin = 15 V, TA = 25°C, all voltage ranges, unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Turn-On Settling Time
(to±0.01%)
ts
-
50
-
J.IS
Output Noise Voltage - P to P
(Bandwidth 0.1 to 10 Hz)
Vn
-
12
-
IlV
Small-Signal Output Impedance
120 Hz
500 Hz
ro
-
0.15
0.2
-
70
80
-
Characteristic
Power Supply Rejection Ratio
5-14
PSRR
n
dB
MOTOROLA ANALOG IC DEVICE DATA
MC1404
TYPICAL CHARACTERISTICS
Figure 2. Simplified Device Diagram
2
Figure 3. Line Regulation versus Temperature
2.5
Yin
:;;g 2.0
:z
~ 1.5
6
R
w
a:
w 1.0
:z
TRIM
VTEMP
3
::;
5
3.75k
Vo
5.0V
5.0k
6.25 V
8.75k
10V
Yin = Vret +2.5 V to 40 V
lout = 0 rnA
(!)
5.0 k
R
~
~
Vou!
+
5
~o 0.5
o
1.25k
o
10
20
~
40
50
70
60
TA, AMBIENT TEMPERATURE ('C)
4
Figure 4. Output Voltage versus Temperature
MC1404P10
Figure 5. Load Regulation versus Temperature
0.010
10.04
~
w
(!)
~ 0.008
10.02
~
~ 10.00
~
~
9.98
Load Change 0 to lOrnA
§ 9.96
S
>0
9.94
::]
0
o
20
~
40
50
TA, AMBIENT TEMPERATURE ('C)
10
60
o
70
Figure 6. Power Supply Rejection Ratio
versus Frequency
10
~
Ml
::;
:t
iil
ffi
70
60
~ ~
~
~
"
O.II1F
l~
rf
'V
1.0k
1.4
!z
w
1.2
a:
a:
'"
:z
(.)
I-
60
70
1.0
0.8
w
HP209A
3.0 Vons 5~~
~
«
.s
i""
40
20
30
40
50
TA, AMBIENTTEMPERATURE ('C)
1.6
80
50
10
Figure 7. Quiescent Current versus Temperature
~ 90
~
o
(.)
en
w
5
~
12
: (21.3 v Set No!e to D 4
~
20 V Average
6
i""
HP3400A
Vin= 15 V
10ut=0 rnA
0.6
0
0.4
.9
0.2
~
20
0.Q1
0.1
1.0
10
t, FREQUENCY (kHz)
MOTOROLA ANALOG IC DEVICE DATA
100
1000
o
o
10
20
30
40
50
TA, AMBIENT TEMPERATURE ('C)
60
70
5-15
II
MC1404
Figure 8. Short Circuit Current
versus Temperature
Figure 9. VTEMP Output versus Temperature
40
1.0
~
t=>
a.
t=>
1 35
~
~
30
Vin= 15V
=> 25
u
0.8
0
UI
a:
=>
!::::
0.6
~
=> 20
~
C3 IS
UI
a.
::;;;
0.4
UI
..
Ii:
f-;,
a.
~ 10
10
20
30
40
50
TA, AMBIENT TEMPERATURE (OC)
o
o
70
60
Figure 10. Output Trim Configuration
10
Va
MCI404
70
r-----------~--_oV+
330
6
Output
?
5
TRIM
Gnd
Rp
100 k
5.0,6.25,
IOV@I/2Amp
6
Va 1-"------_-0
,.----,-.=-2--, O.OIIlF
14
-1..
60
Figure 11. Precision Supply Using MC1404
+15V
j2
Yin
20
30
40
50
TA, AMBIENTTEMPERATURE (OC)
Yin
MCI404
Output Adjustment
The MCI404 trim terminal can be used to adjuslthe output vonage
over a ±6.0% range. For example, the output can be selto 10.000 V
or to 10.240 V for binary applications. For trimming, Bourns type
3059, 100 ill or 200 kO trtmpot is recommended.
Although Figure 10 illustrates a wide trim range, temperature
Output Power Boosting
Gnd
4
The addition of a power transistor, a reSistor, and a capacitor
converts the MC1404 into a preCision supply with one ampere
current capability. At V+ = 15 V, the MCI404 can carry in excess of
14 mA of load current with good regulation. nthe power transistor
current gain exceeds 75, a one ampere supply can be realized.
coefficients may become unpredictable for trim> ± 6.0%.
Figure 12. Ultra Stable Reference for MC1723 Voltage Regulator
Supply
2
MCI404P5
8(12)
7(11)
MCI723
3(5)
6
2(4)
4
-=
Io.1
_ IlF
Vout
Vout =5.0V
.I O.OOIIlF
5-16
I
omax
RO + 4.7 k)
(~
= 0.6 V
Rsc
MOTOROLA ANALOG IC DEVICE DATA
MC1404
Figure 13. 5.0 V, 6.0 Amp, 25 kHz Switching Regulator with Separate Ultra-Stable Reference
+10to+30In
120~
IO.01 /lF
50V
Ceramic
-=
+5.0 V Out
200mAto
6.0 Amps
rO.0 1 /lF
Ceramic
-=
-=
130
130
11
12
2
-=
Motorola
TL495CN
Pulse Width
Modulator
•
17
18
2.2 k
MCI404P5
100k
TRIM
(opt)
7
9
10
2.2 k
-=
-=
-=
Figure 14. Reference for a High Speed DAC
12.5 to
40V
Input
2
6
R2
MCI404Pl0
4
10 V Reference
-=
Digital
Inputs
•••
••
Analog
Oulput
Ladder
and
Switches
Rl and R2 values depend
on the current requirements
oftheDAC.
High Speed DAC
MOTOROLA ANALOG IC DEVICE DATA
5-17
®
MOTOROLA
TL431 , A, B
Series
Programmable
Precision References
•
PROGRAMMABLE
PRECISION REFERENCES
The TL431, A, B integrated circuits are three-terminal programmable
shunt regulator diodes. These monolithic IC voltage references operate as a
low temperature coefficient zener which is programmable from Vref to 36 V
with two external resistors. These devices exhibit a wide operating current
range of 1.0 rnA to 100 rnA with a typical dynamic impedance of 0.22 n. The
characteristics of these references make them excellent replacements for
zener diodes in many applications such as digital voltmeters, power
supplies, and op amp circuitry. The 2.5 V reference makes it convenient to
obtain a stable reference from 5.0 V logic supplies, and since the TL431 , A,
B operates as a shunt regulator, it can be used as either a positive or
negative voltage reference.
SEMICONDUCTOR
TECHNICAL DATA
Z, LP SUFFIX
PLASTIC PACKAGE
CASE 29
(T0-92)
I
Pin 1. Reference
2. Anode
• Programmable Output Voltage to 36 V
3. Cathode
12 3
• Voltage Reference Tolerance: ±O.4%, Typ @ 25°C (TL431B)
• Low Dynamic Output Impedance, 0.22 n Typical
• Sink Current Capability of 1.0 rnA to 100 rnA
• Equivalent Full-Range Temperature Coefficient of 50 ppml°C Typical
.~
PSUFFIX
PLASTIC PACKAGE
CASE 626
• Temperature Compensated for Operation over Full Rated Operating
Temperature Range
OM SUFFIX
PLASTIC PACKAGE
CASE 846A
(Micr0-8)
• Low Output Noise Voltage
(Top View)
o SUFFIX
PLASTIC PACKAGE
CASE 751
(SOP-8)
ORDERING INFORMATION
Device
Operating
Temperature Range
TL431CL~ACL~BCLP
Package
T0-92
TL431CP, ACP. BCP
2
7 }
Anode
Plastic
TA = 0' to +70'C
TL431CDM. ACDM. BCDM
Micr0-8
TL431CD. ACD. BCD
SOP-8
TL4311LP. AILP. BILP
T0-92
TL4311P. AlP. BIP
Plastic
TA = -40' to +85°C
TL431 10M. AIDM. BIDM
Micr0-8
TL431 10. AID. BID
SOP-8
5-18
8 Reference
Cathode
Anode {
•
8
(Top View)
80P-8 is an internally modified 80-8 package. Pins 2.
3. 6 and 7 are electrically common to the die attach ffag.
This internal lead frame modification decreases power
dissipation capability when appropriately mounted on a
printed circuit board. 80P-8 conforms to all extemal
dimensions of the standard 80-8 package.
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
Symbol
Representative Schematic Diagram
Component values are nominal
ca~~~e
Reference
(R)
i
Cathode (K)
Anode
(A)
Representative Block Diagram
Reference
(R) D-'----+----j~
II
Anode (A)
This device contains 12 active transistors.
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless
otherwise noted.)
Symbol
Rating
Cathode to Anode Voltage
Value
Unit
VKA
37
V
Cathode Current Range, Continuous
IK
-100 to +150
rnA
Reference Input Current Range, Continuous
Iref
--0.05 to + 10
rnA
Operating Junction Temperature
TJ
150
°c
Operating Ambient Temperature Range
TL431I, TL431AI, TL431BI
TL431C,TL431AC,TL431BC
TA
Storage Temperature Range
Tstg
Total Power Dissipation @ TA =25°C
Derate above 25°C Ambient Temperature
D, LP Suffix Plastic Package
P Suffix Plastic Package
DM Suffix Plastic Package
PD
Total Power Dissipation @ TC =25°C
Derate above 25°C Case Temperature
D, LP Suffix Plastic Package
P Suffix Plastic Package
PD
NOTE:
°C
-40 to +85
Oto+70
-65 to +150
°C
W
0.70
1.10
0.52
W
1.5
3.0
ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Condition
Symbol
Cathode to Anode Voltage
Min
Max
VKA
Vref
36
V
IK
1.0
100
mA
Cathode Current
Unit
THERMAL CHARACTERISTICS
Symbol
D, LP Suffix
Package
P Suffix
Package
DM Suffix
Package
Unit
Thermal Resistance, Junction-to--Ambient
RaJA
178
114
240
°CIW
Thermal Resistance, Junction-to--Case
RaJC
83
41
-
°CIW
Characteristic
MOTOROLA ANALOG IC DEVICE DATA
5-19
TL431 I A, B Series
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
TL431C
TL431 I
Symbol
Characteristic
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA = 25°C
TA = Tlowto Thigh (Note 1)
Min
Typ
Max
Min
Typ
Max
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 1, 2,4)
Unit
V
Vref
2.44
2.41
2.495
-
2.55
2.58
2.44
2.423
2.495
-
2.55
2.567
-
7.0
30
-
3.0
17
INrel
mV
VKA= Vref, IK = 10 mA
Ratio of Change in Reference Input Voltage
to Change in Cathode \0 Anode Voltage
IK = 10 mA (Figure 2), IWKA = 10 V \0 Vref
Ll.VKA=36Vtol0V
II
Reference Input Current (Figure 2)
IK = 10 mA, Rl = 10 k, R2 = ~
TA=25°C
TA = Tlowto Thigh (Note 1)
mVN
l!N ref
AV KA
-
-
-1.4
-1.0
-2.7
-2.0
-
-1.4
-1.0
-2.7
-2.0
I1A
Iref
-
1.8
-
4.0
6.5
-
1.8
-
-
-
4.0
5.2
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 1,4)
IK=10mA, Rl = 10k, R2=~
Ll.lref
-
0.8
2.5
-
0.4
1.2
I1A
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin
-
0.5
1.0
-
0.5
1.0
mA
Off-State Cathode Current (Figure 3)
VKA=36 V, Vref= OV
loff
-
2.6
1000
-
2.6
1000
nA
IZKAI
-
0.22
0.5
-
0.22
0.5
n
Dynamic Impedance (Figure 1, Note 3)
VKA = Vref, Ll.IK = 1.0 mA to 100 mA
f:s; 1.0 kHz
NOTE 1: Tlow = -40°C for TL431 AlP TL431 AILP, TL4311P, TL431ILP, TL431 BID, TL431 BIP, TL431 BILP, TL431 AIOM, TL4311DM, TL431 BIDM
= 0°ClorTL431ACP, TL431 ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431 BCD, TL431 BCP, TL431 BcLp;TL431CDM,
TL431 ACDM, TL431 BCDM
Thigh = +85°C lor TL431AIP, TL431 AILP, TL4311P, TL4311LP, TL431 BID, TL431BIP, TL431BILP, TL4311DM, TL431AIDM, TL431 BIDM
= +70°C lor TL431 ACP, TL431ACLP, TL431 CP, TL431 ACD, TL431 BCD, TL431 BCP, TL431 BCLP, TL431 CDM, TL431 ACDM, TL431 BCDM
NOTE 2: The deviation parameter AVrel is delined as the difference between the maximum and minimum values obtained over the lull operating ambient
temperature range that applies.
.
Vrffimaxl~
AVrel= Vrffi max
-Vrefmin
ATA=T2- Tl
Vrelmin(j
T1 AmbientTemperature
T2
The average temperature coefficient of the relerence input vottage, aVrel is defined as:
AVrel
( V
rel @ 25°C
V rel PfCm =
)x
6
10
Ll. TA
aVrel can be positive or negative depending on whether Vrel Min or Vrel Max occurs at the lower ambient temperature. (Reier to Figure 6.)
Example: Ll.V rei = 8.0 mV and slope is positive,
V rei
@
25°C = 2.495 V, AT A = 70°C
0.008 x 106
/0
a V ref = 70 (2.495) = 45.8 ppm C
AV
NOTE 3: The dynamic impedance ZKA is defined as IZ KA' = Ll. IKA
K
When the device is programmed with two external resistors, Rl and R2, (reler to Figure 2) the total dynamic impedance 01 the circuit is defined as:
5--20
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
ELECTRICAL CHARACTERISTICS (TA = 25'C, unless otherwise noted.)
TL431AI
Characteristic
Symbol
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA=25'C
TA = Tlow to Thigh
Min
Typ
TL431AC
Max
Min
Typ
TL431B
Min
Max
Typ
Max
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 1,2,4)
VKA= Vref, IK = lOrnA
Ratio of Change in Reference Input Voltage
to Change in Cathode to Anode Voltage
IK = 10 rnA (Figure 2), AVKA = 10 V to Vref
AVKA=36Vtol0V
Unit
V
Vref
2.47
2.44
2.495
2.52
2.55
2.47
2.453
2.495
-
-
2.52
2.537
2.483
2.475
2.495
2.495
2.507
2.515
-
7.0
30
-
3.0
17
-
3
17
AVref
mV
mVN
AV ref
AV KA
-
-1.4
-1.0
-
-2.7
-2.0
-
1.8
-
4.0
6.5
0.8
-1.4
-1.0
-2.7
-2.0
-
-
-
1.8
-
4.0
5.2
2.5
-
0.4
1.2
-
-
-1.4
-1.0
-2.7
-2.0
1.6
-
3.0
4.0
0.4
1.2
f.1A
Reference Input Current (Figure 2)
IK = lOrnA, Rl = 10k, R2 = ~
TA = 25'C
TA = Tlowto Thigh (Note 1)
Alref
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 1)
IK= lOrnA, Rl = 10k, R2=~
Alref
-
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin
-
0.5
1.0
-
0.5
1.0
-
0.5
1.0
mA
Off-State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V
loff
-
260
1000
-
260
1000
-
230
500
nA
IZKAI
-
0.22
0.5
-
0.22
0.5
-
0.14
0.3
11
Dynamic Impedance (Figure 1, Note 3)
VKA = Vref, AIK = 1.0 rnA to 100 rnA
f:;; 1.0kHz
f.1A
NOTE 1: Tlow = -40'C for TL431 AlP TL431 AILP, TL4311P. TL431ILP, TL431 BID, TL431 BIP, TL431 BILP, TL431AIDM, TL431 10M, TL431 BIDM
= O'C for TL431 ACP, TL431ACLP. TL431CP, TL431CLP, TL431 CD, TL431ACD, TL431 BCD, TL431 BCP, TL431 BCLP, TL431CDM,
TL431 ACDM, TL431 BCDM
Thigh = +85'C for TL431AIP, TL431AILP, TL4311P, TL431ILP, TL431 BID. TL431 BIP, TL431 BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70'C for TL431ACP, TL431 ACLP, TL431CP. TL431ACD, TL431 BCD, TL431 BCP, TL431 BCLP, TL431CDM, TL431ACDM, TL431 BCDM
NOTE 2: The deviation parameter tNref is defined as the difference between the maximum and minimum values obtained over the full operating ambient
temperature range that applies.
'M~I~
Vrefmin~
T1 Ambient Temperature
T2
The average temperature coefficient of the reference input voltage, aVref is defined as:
A V ref
( V
ref @ 25'C
Vref Pfcm =
)x
10
6
-'----;-;0---'---
A TA
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example: AV ref = 8.0 mV and slope is positive,
V ref @ 25'C = 2.495 V,AT A = 70'C
a V ref =
0.008 x 106
70 (2.495)
45.8 ppm/,C
AV
NOTE 3 : The dynamic impedance ZKA is defined as IZKAI =
A IKA
K
)
When the device is programmed with two external resistors, Rl and R2, (refer to Figure 2) the total dynamic impedance of the circuit is defined as:
IZKA'I
~ IZKAI
NOTE 4: This test is not applicable to surface mount (D and DM suffix) devices.
MOTOROLA ANALOG IC DEVICE DATA
( 1
+ =~
5-21
II
TL431 , A, B Series
Figure 1. Test Circuit for VKA = Vref
Figure 3. Test Circuit for lof
Figure 2. Test Circuit for VKA > Vref
Input o-.JIIIJ'V-.---o VKA
Rt
R2
VKA = Vref ( 1 +
Figure 4. Cathode Current versus
Cathode Voltage
II
a:
a:
:::>
BOO
VKA =Vref
TA = 25°C
I100
c- '"'"
!z
w
I-
50 l-
w
Cl
"K'KA
!z
ll!
a:
"'"q':"
~
-1.0
0
1.0
VKA, CATHODE VOLTAGE (V)
2600
VKA
:[ 2580 InputW
, IKVKA = Vref
Vref
'K=10mA -
~
1
I
I
I
~ 2480
2460
~
-
2440
Ii! 2420
2400
-55
I
a
0
25
50
75
TA, AMBIENT TEMPERATURE (OC)
5-22
-r--
1-""
100
~
£;
3.0
1.0
2.0
VKA, CATHODE VOLTAGE (V)
125
"""""'-
1.5
-
r--
'K=10mA
~
1.0
~~
0.5
j
.............
2.0
~
1
I
I
~=i440mv
1
-25
o
3.0
~ 2.5
a:
Vref Max = 2550 mV
I
~
Figure 7. Reference Input Current versus
Ambient Temperature
Vref Typ = 2495 mV _
>
./
0
-200
-1.0
3.0
2.0
1
~..--
~
./
!;;:
/
L
I
/
200
I
Figure 6. Reference Input Voltage versus
Ambient Temperature
a:
/
()
-50
-100
-2.0
LU
IM~ f - -
w
g
()
~
VKA = Vref
TA = 25°C
()
/'
!;;:
400
:::>
~
0
0
I
~ 600
"E!iF
I-
()
+ 'ref • Rl
Figure 5. Cathode Current versus
Cathode Voltage
150
<.s
~)
o
-55
'~~'"
!W ~ "K
10k
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (OC)
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
Figure 9. Off-State Cathode Current
versus Ambient Temperature
Figure 8. Change in Reference Input
Voltage versus Cathode Voltage
l
0
~
~--8.0
>
11.Ok
I
"'- ~
w
IK=10mA_
TA = 25°C
a: 100
a:
::>
..................
~
u::; --16
i'5
a:
'"~~VAA
Rl
+IK
a:
R2
()
tt --24
w
0
D
t'......
10
:I:
!;;:
r--.......
./
(,)
w
1.0
:Lu-
0.1
~
..............
Vref
j
10
20
30
40
o.ot
--55
--25
VKA, CATHODE VOLTAGE (V)
<5
w
~loutPut
'"
50
E
TA =25°C
A IK = 1.0 rnA to tOO rnA
==
g:
w
K
_+
-0:
D
w
~1~utPut
"",
'"
;;§
0.260
(,)
:E
-0:
-0:
:z
0.240
>D
1.0
~
~
~
~
0.1
1.0k
10k
lOOk
f, FREQUENCY (MHz)
1.0M
0.220
0.20~55
10M
Figure 12. Open-Loop Voltage Gain
versus Frequency
125
Output
+11<,
~
40
9.01!F
.~E-j
H~
230
Gnd
V
V
.-'
0
25
50
75
TA, AMBIENT TEMPERATURE (0C)
100
125
-?
<-
.§..
..... 60
)t
8.25 k
30
w
a:
a:
Gnd
(,)
t\
20
~
10 f-- IK=10mA
TA =25°C
........r-.
:z
::>
C!l
w
VKA =Vref
IK=10rnA
TA = 25°C
40
D
0
:I:
.....
!;;:
(,)
I"",~f<>_
, IK
20
]j.
I
--10
1.0k
--25
V
50
80
50
f''-'!'
100
Figure 13. Spectral Noise Density
60
~
w
75
0.280
"-
::;:
~
C!l
:z
50
VKA =Vret
A IK= 1.0 rnA to 100 rnA
t:51.0kHz
()
9
>D
25
0.300
:z
Gnd
";;§
:z
0
0.320
1.0 k
10
'"~~VAA
,Ioff
Figure 11. Dynamic Impedance
versus Ambient Temperature
100
w
()
:z
VKA =36 V
Vret = 0 V
TA, AMBIENTTEMPERATURE (5C)
Figure 10. Dynamic Impedance
versus Frequency
g:
V'
./
/'
.:
o
/'
/'
0
..P
C,.)
4.0
II
8.0
t, TIME (lJS)
12
16
Figure 16. Test Circ;uit For Curve A
of Stability Boundary Conditions
80
w
Gnd
I
c
0
60
'<
40
:x:
C,.)
~
o
A) VKA= Vref
8) VKA = 5.0 V @ IK = 10 rnA
C)VKA = 10V@ IK=10rnA
D)VKA= 15V@ IK= 10 rnA
TA=25'C
1111 II
I "Stable
Input
Mo~nor
h..
20
II
.1,Stable
:~
I.A
8
8
C
~
20
o
100pF
l000pF
O.OII1F
O.II1F
CL, LOAD CAPACITANCE
1.011F
Figure 17. Test Circuit For Curves B, C, And D
of Stability Boundary Conditions
150
V+
V+
TYPICAL APPLICATIONS
Figure 18. Shunt Regulator
V+ o--J\IV\r-_-......-
.......- - 0 Vout
Figure 19. High Current Shunt Regulator
V+ O--'W'r-_-_ _- - O Vout
R1
R2
5-24
MOTOROLA ANALOG·IC DEVICE DATA
TL431 , A, B Series
Figure 20. Output Control for a
Three-Terminal Fixed Regulator
Figure 21. Series Pass Regulator
~---.--o
~-..----o
V+
yOU!
R1
You!
R1
R2
R2
YOU! = (1
YOU! = (1
+~) Vref
yOU! min = Vref
+~) Vref
yOU! min = Vref
+ 5.0V
Figure 22. Constant Current Source
+ Vbe
•
Figure 23. Constant Current Sink
RS
Figure 24. TRIAC Crowbar
V+
1"""'<._-.__--0 you!
R1
Figure 25. SRC Crowbar
V+
»-__- _ -.......- - - 0
yOU!
R1
R2
MOTOROLA ANALOG IC DEVICE DATA
5-25
TL431 , A, B Series
Figure 26. Voltage Monitor
V+o--.--.....-
Figure 27. Single-Supply Comparator with
Temperature-Compensated Threshold
---..--o Vout
.....
V+
R3
...---0 VoU!
R2
R4
Yin
L.E.D. indicator is 'on' when V+ is between the
upper and lower limits.
II
Vre!
Lower Limit = (1
+~)
Vret
Upper Limit = (1
+~)
Vret
Figure 28. Linear Ohmmeter
Vout
V+
=2.0V
Figure 29. Simple 400 mW Phono Amplifier
T,=330t08.00
~T'
8.00
Rx = Vout •
5-26
~
Range
l)-dJ II
'Thermalloy
THM6024
Heatsinkon
LP Package
MOTOROLA ANALOG IC DEVICE DATA
TL431 , A, B Series
Figure 30. High Efficiency Step-Down Switching Converter
150"H@2.0A
Yin = 10oV_to_2~0~V_ _--..._ _,TIPI15r_-+_--..._---<_-'
4.7 k
+
Vout = 5.0 V
lout = 1.0A
lN5823
O.OIIlF
100k
2200ilF
+
51 k
10
Test
Line Regulation
Load Regulation
Oulput Ripple
Output Ripple
Efficiency
MOTOROLA ANALOG IC DEVICE DATA
Conditions
= 10 V to 20 V, 10 = 1.0 A
Vin = 15 V, 10 = 0 A to 1.0 A
Vin = 10 V, 10 = 1.0 A
Vin = 20 V, 10 = 1.0 A
Vin = 15 V, 10 = 1.0 A
Vin
II
Results
53mV (1.1%)
25mV (0.5%)
50 mVpp PAR.D.
100 mVpp PAR.D.
82%
5-27
II
5-28
MOTOROLA ANALOG IC DEVICE DATA
Data Conversion
In Brief ...
Motorola's line of digital-to-analog and analog-to--digital
converters include several varieties to suit a number of
applications.
The AID converters include an 8-bit flash converter suitable
for NTSC and PAL systems. CMOS devices include 8 to 1()-bit
converters, as well as other high speed digitizers.
The D/A converters have 6 and 8-bit devices, and video
speed (for NTSC and PAL) devices.
MOTOROLA ANALOG IC DEVICE DATA
Page
Data Conversion ................................. 6-2
A-D Converters ............................... 6-2
CMOS ..................................... 6-2
Bipolar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
Sigma-Delta ............................... 6-2
D-A Converters ............................... 6-3
CMOS ..................................... 6-3
Sigma-Delta ............................... 6-3
Package Overview ............................... 6-4
Device Listing and Related Literature ............... 6-5
6-1
III
Data Conversion
The line of data conversion products which Motorola offers
spans a wide spectrum of speed and resolution/accuracy.
Features, including bus compatibility, minimize external parts
count and provide easy interface to microprocessor systems.
Various technologies, such as Bipolar and CMOS, are utilized
to achieve functional capability, accuracy and production
repeatability. Bipolar technology generally results in higher
speed, while CMOS devices offer greatly reduced power
consumption.
Table 1. A-O Converters
Conversion
TImelRate
Input
Vonage
Range
Supplies
Device
Nonlinearity
Max
(V)
Temperature
Range
(OC)
MC145040
±1/2 LSB
10 IJS
Oto VDD
+5.0±10"lo
-40 to +125
Resolution
(Bits)
Suffix!
Package
Comments
CMOS
8
MC145041
II
MC14549BI
MC14559B
P1738,
DW1751D
Includes Inlernal
Clock, 11--Gh MUX
20 IJS
Successive Approximation
Regislers
+3.010+18
-4010 +85
P/648
Triple
8-Bil
MC44251
1 LSB
18MHz
1.6t04.6V
+5.0±10%
-4010 +85
FN17n
10
MC145050
±1 LSB
21 IJS
010 VDD
+5.0±10%
-4010+125
P1738,
DW1751D
MC145051
Requires External
Clock, 11--Gh MUX
Compalible wilh
MC1408 S.A.R.
B-bil D-A Converter
3 Separale Video
Channels
Requires Extemal
Clock, 11-Ch MUX
Includes Inlernal
Clock, 11--Gh MUX
441JS
MC145053
P/646,
D1751 A
8-10
MC144431
MC14447
±O.5%
Full Scale
300J,ls
Variable
w/Supply
+5.010+18
3-1/2 Digil
MC14433
±O.05%
±1 Counl
40ms
±2.0V
±200 mV
+5.0 to +8.0
-2.810-8.0
MC10319
±1 LSB
25 MHz
MC145073
±1 LSB
48kHz
-4010+85
Includes Inlernal
Clock, S--Ch MUX
P/648,
J,lP Compalible,
DW1751G Single Slope,
6--ch MUX
P1709,
Dual Slope
DW1751E
Bipolar
8
010 2.0 Vpp
+5.0 and
Max
-3.010-6.0
010+70
P1709,
DW1751F
Die Form
Video Speed Flash
Converter, Inlernal
Gray Code
TILOulpuls
-4010+85
DW1751E
Dual Channel,
Sigma-Delta
archilecture
Sigma-Delta
16
6-2
1.9 Vpp
4.5105.5
MOTOROLA ANALOG IC DEVICE DATA
Table 2. D-A Converters
Device
Max
Max
Settling
Time
(± 112 LSB)
MC144110
-
-
MC144111
-
-
MC144112
-
-
+2.5 to +5.5
MC44200
±1/2 LSB
30 ns
16,18,20
MC145074
See data
sheet
-
MC145076
See data
sheet
Accuracy
@,25°C
Resolution
(Bits)
Supplies
Temperature
Range
(V)
('C)
+5.0 to +15
Oto+85
Suffix!
Package
Comments
CMOS
6
Triple
8-Bit
P1707,
DWI751D
Serial input, Hex DAC,
6 outputs
P/646,
DW1751G
Serial input, Quad DAC,
4 outputs
-40 to +85
P/646,
D1751 A
Serial input, Quad DAC,
4 outputs
+5.0
±10%
-40 to +85
FU/824A
6.0 ns
4.5 to 5.5
-40 to +85
D1751B
Dual Channel,
Sigma-Delta architecture,
MC145076 FIR Filter
available
-
+5.0
-40 to +85
D1751B
Dual Channel Bit Stream,
144 tap FIR Filter
Triple Video DAC,
55 MHz, TTL
Sigma-Delta
MOTOROLA ANALOG IC DEVICE DATA
6-3
Data Conversion Package Overview
-
•
-
CASE 646.
PSUFFIX
II
CASE 648
PSUFFIX
~
CASE 707
PSUFFIX
6-4
CASE 649
PSUFFIX
CASE 709
PSUFFIX
CASE 751A
DSUFFIX
CASE 751B
DSUFFIX
CASE 751F
DWSUFFIX
CASE 751G
DWSUFFIX
•
CASE 751D
DWSUFFIX
CASE 777
FN SUFFIX
-
CASE 738
PSUFFIX
CASE 751E
DWSUFFIX
•
CASE 824A
FUSUFFIX
MOTOROLA AIliALOG IC DEVICE DATA
Device Listing and Related Literature
A-D Converters
Device
Function
MC10319
High Speed 8-Bit Analog-ta-Digital Flash Converter ................ 6-6
Page
RELATED APPLICATION NOTES
App Note
Title
Related Device
AN702
High Speed Digital-ta-Analog and Analog-ta-Digital
Techniques ............................................... General Information
AN926
Techniques for Improving the Settling Time of a DAC and
Op Amp Combination ...................................... Various
III
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC10319
High Speed a-Bit
Analog-to-Digital Converter
a
The MC10319 is an 8-bit high speed parallel flash AID converter. The
device employs an internal Grey Code structure to eliminate large output
errors on fast slewing input signals. It is fully TTL compatible, requiring a
+ 5.0 V supply and a wide tolerance negative supply of - 3.0 to - 6.0 V.
Three-state TTL outputs allow direct drive of a data bus oi; common I/O
memory.
The MC10319 contains 256 parallel comparators across a precision input
reference network. The comparator outputs are fed to latches and then to .an
encoder network, to produce an 8-bit data byte plus an overrange bit. The
data is latched and converted to 3-state L8-TTL outputs. The overrange bit
is always active to allow for either sensing olthe overrange condition or ease
of interconnecting a pair of devices to produce a 9-bit AID converter.
Applications include video display and radar processing, high speed
instrumentation and TV broadcast encoding.
HIGH SPEED
8-BIT ANALOG-TO-DIGITAL
FLASH CONVERTER
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
" , .
PLASTIC PACKAGE
CASE 709
• Internal Grey Code for Speed and Accuracy, Binary Outputs
• 8-Bit Resolution/9-Bit Typical Accuracy
• Easily Interconnected for 9-Bit Conversion
OW SUFFIX
PLASTIC PACKAGE
CASE 751F
(S0-28L)
• 3-State LS-TTL Outputs with True/Complement Enable Inputs
• 25 MHz Sampling Rate
• Wide Input Range: 1.0 to 2.0 Vpp , between ± 2.0 V
• Low Input Capacitance: 50 pF
• Low Power Dissipation: 618 mW
• No Sample/Hold Required for Video Bandwidth Signals
PIN CONNECTIONS
(Ponly)
• Single Clock Cycle Conversion
GNO 2
OVERRANGE
Representative Block Diagram
logic
Analog
Input
Vin
(14)
VAT
(24)
VEE
VCCjOj
-I - ,I
(11, 7
(13)
MC10319
GNO
(2,12,
16,22)
Bias
L ___ J
r----.,
I
I
r-----,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
r-----,
OverRange
(3)
07(4)
06(5)
05(6)
04(7)
03(8)
02(9)
ORDERING INFORMATION
01 (10)
00(21)
VRB
(23)
Device
MC10319DW
Clock
(18)
MC10319P
Operating
Temperature Range
TA = 0° to +70°C
Package
S0-28L
Plastic
MOTOROLA ANAI.,OG ICDEVICE DATA
MC10319
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC(A),(D)
VEE
+7.0
-7.0
Vdc
PosHive Supply Voltage Differential
VCC(D)VCC(A)
-0.3 to + 0.3
Vdc
Digital Input Voltage (Pins 18 to 20)
V, (D)
-0.5 to+ 7.0
Vdc
V,tA)
-2.5 to + 2.5
Vdc
Rating
Supply Voltage
Analog Input Voltage (Pins I, 14,23,24)
Reference Voltage Span (Pin 24 to Pin 23)
-
2.3
Vdc
Applied Output Voltage (Pins 4 to 10, 21 in 3-State)
-
-0.3 to + 7.0
Vdc
Junction Temperature
TJ
+ 150
°C
Storage Temperature
Tstg
-65 to + 150
°C
Devices should not be operated at these values. The "Recommended Operating Limits" table provides
guidelines for actual device operation.
RECOMMENDED OPERATING LIMITS
Characteristic
Power Supply Voltage (Pin 15)
(Pins 11,17)
VCC(D) - VCC(A)
Power Supply Voltage (Pin 13)
Digital Input Voltages (Pins 18 to 20)
Analog Input (Pin 14)
Symbol
Min
Typ
Max
Unit
VCC(A)
VCC{D)
+4.5
+5.0
+5.5
Vdc
dVCC
-0.1
0
+0.1
Vdc
VEE
-6.0
-5.0
-3.0
Vdc
V'(D)
a
-
+5.0
Vdc
V,tA)
-2.1
-
+2.1
Vdc
-
+2.1
Vdc
-
+ 1.0
Vdc
Vdc
VRT
-1.0
Voltage @ VRB (Pin 23)
VRB
-2.1
VRT-VRB
dVR
+ 1.0
-
+2.1
VRB-VEE
-
1.3
-
-
Vdc
Applied Output Voltage (Pins 4 to 10, 21 in 3-State)
Va
0
-
5.5
Vdc
Clock Pulse Width - High
Low
tCKH
tCKL
5.0
15
20
20
-
ns
Clock Frequency
fCLK
0
-
25
MHz
TA
0
-
+70
°C
Voltage @ VRT (Pin 24)
Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS (0° < TA < 70°C, VCC = 5.0 V, VEE =-5.2 V, VRT=+1.0 V, VRB =-1.0 V, unless noted.)
I
Characteristic
I
Symbol
I
Min
I
Typ
I
Max
I
Unit
TRANSFER CHARACTERISTICS (fCKL = 25 MHz)
Resolution
Monotonicity
N
-
-
8.0
Bits
LSB
Guaranteed
MON
Bits
Integral Nonlinearity
INL
-
± 1/4
± 1.0
Differential Nonlinearity
DNL
-
-
±1.0
LSB
Differential Phase (See Figure 16)
DP
-
1
-
Deg.
DG
-
1
-
Differential Gain (See Figure 16)
Power Supply Rejection Ratio
(4.5 V < VCC < 5.5 V, VEE = - 5.2 V)
(-6.0V < VEE < -3.0 V, VCC = +5.0 V)
MOTOROLA ANALOG IC DEVICE DATA
PSRR
%
LSBIV
-
0.1
-
a
-
6--7
II
MC10319
ELECTRICAL CHARACTERISTICS - continued
(0° < TA < 70°C, VCC = 5.0 V, VEE = - 5.2 V, VRT = +1.0 V, VRB = -1.0 V, unless otherwise noted.)
I
Characteristic
Symbol
Min
I
Typ
Max
Unit
ANALOG INPUTS (Pin 14)
Input Current @ Yin = VRB (See Figure 5)
IINL
-100
0
-
Input Current @ Yin = VRT (See Figure 5)
IINH
-
60
150
J.lA
J.lA
Input Capac~ance (VRT - VRB = 2.0 V, See Figure 4)
Cin
-
36
-
pF
Input Capacitance (VRT - VRB = 1.0 V, See Figure 4)
Cin
-
55
-
pF
VOS
-
0.1
-
LSB
Bipolar Offset Error
REFERENCE
Ladder Resistance (VRT to VRB, TA = 25°C)
Rret
104
130
156
Temperature Coefficient
TC
-
+0.29
Ladder CapaCitance (Pin 1 open)
Cret
-
25
-
Input Voltage - High (Pins 19 to 20)
VIHE
2.0
-
-
V
Input Voltage - Low (Pins 19 to 20)
VILE
-
0.8
V
Input Current @ 2.7 V
Q
o/oI°C
pF
ENABLE INPUTS (VCC = 5.5 V) (See Figure 6)
II
IIHE
-
0
20
Input Current @ 0.4 V @ EN (0 < EN < 5.0 V)
11L1
-400
-100
-
Input Current @ 0.4 V @ EN (EN = 0 V)
IIL2
-400
-100
-
IIL3
-20
-2.0
-
J.lA
J.lA
J.lA
J.lA
VIKE
-1.5
-1.3
-
V
Input Voltage High
VIHC
2.0
-
-
Vdc
Input Voltage Low
VILC
-
-
0.8
Vdc
Input Current @ 0.4 V (See Figure 7)
IILC
-400
-80
-
!LA
Input Current @ 2.7 V (See Figure 7)
IIHC
-100
-20
-
!LA
Input Clamp Voltage (11K = - 18 rnA)
VIKC
-1.5
-1.3
-
Vdc
VOH
2.4
3.0
-
V
-
0.35
0.4
V
35
-
mA
-50
-
+50
-
9.0
-
Input Current @ 0.4 V @ EN (EN = 2.0 V)
Input Clamp Voltage (11K = - 18 rnA)
CLOCK INPUTS (VCC = 5.5 V)
DIGITAL OUTPUTS
High Output Voltage (IOH = - 400
J.lA, VCC = 4.5 V, See Figure 8)
Low Output Voltage (IOL = 4.0 rnA, See Figure 9)
VOL
Output Short Circuit Current' (VCC = 5.5 V)
ISC
Output Leakage Current (0.4 < Vo < 2.4 V, See Figure 3,
VCC = 5.5 V, DO to 07 in 3-State Mode)
ILK
Output Capacitance (DO to 07 in 3-State Mode)
Cout
J.lA
pF
'Only one output is to be shorted at a time, not to exceed 1 second.
POWER SUPPLIES
VCC(A) Current (4.5 V < VCC(A) < 5.5 V) (Outputs unloaded)
ICC(A)
10
17
25
rnA
VCC(D) Current (4.5 V < VCC(O) < 5.5 V) (Outputs unloaded)
ICC(O)
50
90
133
rnA
VEE Current (- 6.0 < VEE < - 3.0 V)
lEE
-14
-10
-6.0
rnA
Power Dissipation (VRT - VRB = 2.0 V) (Outputs unloaded)
PD
-
618
995
mW
MOTOROLA ANALOG Ie DEVICE DATA
MC10319
TIMING CHARACTERISTICS (TA = 25°C, VCC = + 5.0 V, VEE = - 5.2 V, VRT = + 1.0 V, VRB = -1.0 V,
see System liming Diagram, Figure 1.)
Characteristic
Symbol
Min
Typ
Max
Unit
Min Clock Pulse Width - High
tCKH
-
5.0
-
ns
Min Clock Pulse Width - Low
tCKL
-
15
-
ns
Max Clock Rise, Fall Time
tR,F
-
100
-
ns
Clock Frequency
fCLK
0
30
25
MHz
tCKDV
-
19
-
ns
tAD
-
4.0
-
ns
INPUTS
OUTPUTS
New Data Valid from Clock Low
Aperture Delay
tH
-
6.0
-
ns
Data High to 3-State from Enable Low·
tEHZ
-
27
-
ns
Data Low to 3-State from Enable Low"
tELZ
-
18
-
ns
Data High to 3-State from Enable High·
tEHZ
-
32
-
ns
Data Low to 3-State from Enable High·
tELZ
-
18
-
ns
tEDV
-
15
-
ns
tEDV
-
16
-
ns
ttr
-
8.0
-
ns
Hold lime
=0 V)*
Valid Data from Enable Low (Pin 19 =5.0 V)*
Valid Data from Enable High (Pin 20
Output Transition lime" (10% to 90%)
"See Figure 2 for output loading.
PIN FUNCTION DESCRIPTION
Pin
Function
P Suffix
OW Suffix
VRM
1
1
Description
GND
2,12
16,22
2,13,17
18,25,26
OVR
3
3
D7-DO
4 to 10, 21
4to 10, 24
VCC(D)
11,17
11,12
19,20
VEE
13
14
Negative power supply. Nominally - 5.2 V, it can range from - 3.0 to - 6.0 V, and must
be more negative than VRB by > 1.3 V. Reference to analog ground.
Yin
14
15
Signal voltage input. This voltage is compared to the reference to generate a digital
equivalent. Input impedance is nominally 16 to 33K in parallel with 36 pF.
VCC(A)
15
16
Power supply for the analog section. +5.0 V, ± 10% required. Reference to analog
ground.
The midpoint of the reference resistor ladder. Bypassing can be done at this point to
improve performance at high frequencies.
Dig~al ground. The pins should be connected directly together, and through a low
impedance path to the power supply.
Overrange output. Indicates Yin is more positive than VRT 1/2 LSB. This output does
not have 3-state capability.
Dig~al Outputs. D7 (Pin 4) is the MSB. D0 (Pin 21 or 24) is the LSB. LS-TIL
compatible with 3-state capability.
Power supply for the digital section. +5.0 V, ± 10% required. Reference to digital
ground.
CLK
18
21
Clock input. TIL compatible.
EN
19
22
Enable input. TIL compatible, a logic 1 (and EN at a logic 0) enables the data outputs.
A logic 0 puts the outputs in a 3-state mode.
EN
20
23
Enable input. TIL compatible, a logic 0 (and EN at a logic 1) enables the data outputs.
A logic 1 puts the outputs in a 3-state mode.
VRB
23
27
The bottom (most negative point) of the internal reference resistor ladder.
VRT
24
28
The top (most positive point) of the internal reference resistor ladder.
MOTOROLA ANALOG IC DEVICE DATA
III
MC10319
Figure 1. System Timing Diagram
14--- 'CKH -----i*"f---- tcKL - - - - . j
Clock
tCKDV and tH measured at output levels of 0.8 and 2.4 V.
II
EN
EN
tEHZ
High Data
Output
tEll
Low Data
Output
Outputs
Active
Figure 2. Data Output Test Circuit
Figure 3. Output 3-State Leakage Current
200
VCC
~ 100
1.0kn
00-07,)--"--"-*-.
'"
~
50
§
0
~
-50
i1i
-100
a:
<..>
w
C1
i'
3.0 kn
..
...I
r.'7
Diodes = 1N914 or equivalent, C1 = 15 pF
-200
-1.0
)
(
I
O°C < TA < 70°C
Pin19=OV
o
1.0
2.0
3.0
4.0
5.0
6.0
7.0
APPLIED VOLTAGE (VOLTS)
6-10
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 5. Input Current @ Vin (Pin 14)
Figure 4. Input Capacitance @ Vin (Pin 14)
100
80
I
I
[L
80
\
S
UJ
'-'
~
t5
60
<.5
Z
UJ
I
I
ex:
ex: 40
::::J
'-'
VRT- VRS =1.0 V
::>
-
40
I
~
0-
I
I
20
-"«
(
I
0.1~
20
;;;:
-2.5
VRS
VRT
+2.5
Vin, INPUT VOLTAGE (VOLTS)
"
'/
./'
--
20
;;;:
zUJ -30
ex:
ex:
~
::> -50 I'-'
I-
E,
Pin 19 Current
2V
h_
I
-130
IZ
Pin 19 (Pin 20 = 0 V)
Pin 20 (0 < Pin 19 <5 V)
I-
-70
II
Figure 7. Clock Input Current
40
I-
0-
/
Vin, INPUT VOLTAGE (VOLTS)
E,
::>
W
/
Figure 6. Input Current @ Enable, Enable
10
0
-10
/
A~
...:...5
vRT - vRS =2.0 V
\.i
'r-J
~ '/"70°C
I-
~
1:«
~
I-
\i
C3
O°C
.2- 60
I
I
~
25°C
;;;:
I
I
~oc/ V
...-o:c
-120
1.0
2.0
o
5.5
1.0
2.0
Vin, INPUT VOLTAGE (VOLTS)
3.0
4.0
5.0
6.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 8. Output Voltage versus Output Current
Figure 9. Output Voltage versus Output Current
0.5
Ui
Ui 5.011=--+--=+--t--1---+--+--+--I
~
~
UJ
C!l
4.0
0° and 70°C-, ~
C!l
~
0.3
~
0.2
g
~
~
!3
~ 0.4
c:.
UJ
25°C-
V
§
~
.:..
;9 0.1
Q
:c
4.5 V < VCC < 5.5 V
:9
3.0
'--_.L-_...l-_-'-_--'-_-'-_--L_--'=~
o
-100
-200
-300
IOH, OUTPUT CURRENT (~A)
MOTOROLA ANALOG IC DEVICE DATA
-400
o
o
2.0
4.0
6.0
B.O
IOL, OUTPUT CURRENT (rnA)
6-11
MC10319
Figure 10. Supply Current versus Temperature
Figure 11. Supply Current versus Temperature
-12
1112
~
110
'--...
~
z
0::
...........
::;
-
a..
102
-10
'-.....
VEE=-5.2V
LiJ
E'
-8.0
20
40
60
TA. AMBIENT TEMPERATURE (OC)
70
o
20
40
60
TA. AMBIENT TEMPERATURE (OC)
Figure 12. Differential Linearity Error
70
Figure 13. Integral Linearity Error
1/2 I-+--t--+--+-+-f-I--+--+'-+-+--+-+-ff--t---I
LSB
1/2
LSB
1, ii,
o
~~ W'~'\
-1/21-+-+-+--+-+-f-1--+-+-+-+--+-+-ff--t---I
LSB
,, ~
~~
IJJ ,.A, i
~VI
-112
fJ~"'J hl~ II
I~
~~rlr'
• ~M
LSB
VRT=2.0 V. VRB = 0 V
Fs = 25 MHz
o
o
256
32
64
98
128
160
192
224
256
Figure 15. Integral Linearity Error
Figure 14. Differential Linearity Error
1/2
LSB
I--t--t--+--+-+-t-I-t-+--+--+-+-t-t-t----i
-1/2 I--+-+-+-+--+-+-ff--+-+-+-+--+-+-+-f---j
LSB
VRT= 2.0 V. VRB =0 V
Fs = 12.5 MHz
o
6-12
32
64
96
128
160
192
224
256
MOTOROLA ANALOG IC DEVICE DATA
MC10319
DESIGN GUIDELINES
Introduction
Reference
The MC1 0319 is a high speed, 8-bit, parallel (''flash'') type
analog-to-digital converter containing 256 comparators at
the front end. See Figure 17 for a block diagram. The
comparators are arranged such that one input of each is
referenced to evenly spaced voltages, derived from the
reference resistor ladder. The other input of the comparators
is connected to the input signal (Vin). Some of the
comparator's differential outputs will be ''true,'' while other
comparators will have "not true" outputs, depending on their
relative position. Their outputs are then latched, and
converted to an 8-bit Grey code by the Differential Latch
Array. The Grey code ensures that any input errors due to
cross talk, feed-thru, or timing disparities result in glitches at
the output of only a few LSBs, rather than the more traditional
1/2 scale and 1/4 scale glitches.
The Grey code is then translated to an 8-bit binary code,
and the differential levels are translated to TTL levels before
being applied to the output latches. Enable inputs at this final
stage permit the TTL outputs (except overrange) to be put
into a high impedance (3-state) condition.
The reference resistor ladder is composed of a string of
equal value resistors to provide 256 equally spaced voltages
for the comparators (see Figure 17 for the actual
configuration). The voltage difference between adjacent
comparators corresponds to 1 LSB of the input range. The
first comparator (closestto VRB) is referenced 1/2 LSB above
VRB, and 256th comparator (for the overrange) is referenced
1/2 LSB below VRT. The total resistance of the ladder is
nominally 130 n, ±20%, requiring 15.4 mA @ 2.0 V, and
7.7 mA @ 1.0 V. There is a nominal warm-up change of
~ +9.0% in the ladder resistance due to the +0.29%/OC
temperature coefficient.
The minimum recommended span [VRT - VRB] is 1.0 V. A
lower span will allow offsets and nonlinearities to become
significant. The maximum recommended span is 2.1 V due to
power limitations of the resistor ladder. The span may be
anywhere within the range of - 2.1 to + 2.1 V with respect to
ground, and VRB must be at least 1.3 V more positive than
VEE· The reference voltages must be stable and free of noise
and spikes, since the accuracy of a conversion is directly
related to the quality of the reference.
In most applications, the reference voltages will remain
fixed. In applications involving a varying reference for
modulation or signal scrambling, the modulating signal may
be applied to VRT, or VRB, or both. The output will vary
inversly with the reference signal, introducing a nonlinearity
into the transfer function. The addition of the modulating
signal and the dc level applied to the reference must be such
that the absolute voltage at VRT and VRB is maintained within
the values listed in the Recommended Operating Limits. The
RMS value of the span must be maintained .. 2.1 V.
VRM (Pin 1) is the midpoint of the resistor ladder, excluding
the Overrange comparator. The voltage at VRM is:
ANALOG SECTION
Signal Input
The signal. voltage to be digitized (Vin) is applied
simultaneously to one input of each of the 256 comparators
through Pin 14. The other inputs of the comparators are
connected to 256 evenly spaced voltages derived from the
reference ladder. The output code depends on the relative
position of the input signal and the reference voltages. The
comparators have a bandwidth of > 50 MHz, which is more
than sufficient for the allowable (Nyquist Theorem) input
frequency of 12.5 MHz.
The current into Pin 14 varies linearly from 0 (when
Yin = VRB) to ~60 jlA (when Yin =VRT). If Yin is taken below
VRB or above VRT, the input current will remain at the value
corresponding to VRB and VRT respectively (see Figure 5).
However, Yin must be maintained within the absolute range of
±2.5 V (with respect to ground) - otherwise excessive
currents will result at Pin 14, due to internal clamps.
The input capacitance at Pin 14 is typically 36 pF if
[VRT - VRB] is 2.0 V, and increases to 55 pF if [VRT - VRB]
is reduced to 1.0 V (see Figure 4). The capacitance is
constant as Yin varies from VRT down to ~0.1 V above VRB.
Taking Yin to VRB will show an increase in the capacitance of
~50%. If Yin is taken above VRT, or below VRB, the
capacitance will stay at the values corresponding to VRT
and VRB, respectively.
The source impedance of the signal voltage should be
maintained below 100 n (at the frequencies of interest) in
order to avoid sampling errors.
MOTOROLA ANALOG IC DEVICE DATA
V
RT
+V
2.0
RB _ 1/2 LSB
In most applications, bypassing this pin to ground (0.1 JlF) is
sufficient to maintain accuracy. In applications involving very
high frequencies, and where linearity is critical, it may be
necessary to trim the voltage at the midpoint. A means for
accomplishing this is indicated in Figure 18.
Power Supplies
VCC(A) is the positive power supply for the comparators,
and VCC(D) is the positive power supplyforthe digital portion.
Both are to be +5.0 V, ±10%, and the two are to be within
100 mV of each other. There is indirect internal coupling
between VCC(D) and VCC(A).lf they are powered separately,
and one supply fails, there will be current flow through the
MC10319 to the failed supply.
6-13
6
MC10319
ICC(A) is nominally 17 rnA, and does not vary with clock
frequency or with Vin. It does vary linearly with VCC(A).ICC(D)
is nominally 90 rnA, and is independent of clock frequency. It
does vary, however, by 6 to 7 rnA as Vin is changed, with the
lowest current occurring when Vin = VRT It varies linearly
with VCC(D).
VEE is the negative power supply for the comparators,
and is to be within the range - 3.0 to - 6.0 V. Additionally,
VEE must be at least 1.3 V more negative than VRS.IEE is a
nominal- 10 rnA, and is independent of clock frequency, Vin
and VEE.
'
For proper operation, the supplies must be bypassed at
the IC. A 10 J.lF tantalum, in parallel with a 0.1 J.lF ceramic is
recommended for each supply to ground.
DIGITAL SECTION
Clock
II
The Clock input is TTL compatible with a typical
frequency range of 0 to 30 MHz. There is no duty cycle
limitations, but the minimum low and high times must be
adhered to. See Figure 7 for the input current requirements.
The conversion sequence is shown in Figure 19, and is
as follows:
• On the rising edge, the data output latches are latched
with old data, and the comparator output latches are
released to follow the input signal (Vin).
• During the high time, the comparators track the input
signal. The data output latches retain the old data.
• On the falling edge, the comparator outputs are latched
with the data immediately prior to this edge. The
conversion to digital occurs within the device, and the
data output latches are released to indicate the new data
within 20 ns.
• Duringthe clock low time, the comparator outputs remain
latched, and the data output latches remain transparent.
A summary of the sequence is that data present at Vin
just prior to the Clock falling edge is digitized and
available at the data outputs immediately after that same
falling edge.
The comparator output latches provide the circuit with an
effective sample-and-hold function, eliminating the need for
an external sample-and-hold.
Enable Inputs
The two Enable inputs are TTL compatible, and are used
to change the data outputs (D7-DO) from active to 3-state.
This capability allows cascading two MC1 0319s into a 9-bit
configuration, flip-flopping two MC10319s into a 50 MHz
configuration, connecting the outputs directly to a data bus,
multiplexing multiple converters, etc. See the Applications
Information section for more details. For the outputs to be
active, Pin 19 must be a Logic "1", and Pin 20 must be a Logic
"0". Changing either input will put the outputs into the high
impedance mode. The Enable inputs affect only the state
of the outputs - they do not inhibit a conversion. The input
current into Pins 19 and 20 is shown in Figure 6, and the
input/output timing is shown in Figure 1 and 20. Leaving
either pin open is equivalent to a Logic "1", although good
design practice dictates that an input should never be
left open.
The Overrange output (Pin 3) is not affected by the Enable
inputs as it does not have 3-state capability.
Outputs
The Data outputs are TTL level outputs with high
impedance capability. Pin 4 is the MSS (D7), and Pin 21 is the
LSB (DO). The eight outputs are active as long as the Enable
inputs are true (Pin 19 =high, Pin 20 =low). The timing of the
outputs relative to the Clock input and the Enable inputs is
shown in Figures 1 and 20. Figures 8 and 9 indicate the
output voltage versus load current, while Figure 3 indicates
the leakage current when in the high impedance mode.
The output code is natural binary, depicted in the
table below.
The Overrange output (Pin 3) goes high when the input,
Vin, is more positive than VRT - 1/2 LSB. This output is
always active - it does not have high impedance capability.
Besides being used to indicate an input overrange, it is
additionally used for cascading two MC10319s to form a
9-bit AID converter (see Figure 27).
Table 1. Output Code
Input
>VRT-1/2LSB
VRT-1/2 LSB
VRT-1 LSB
VRT-1-1/2LSB
Midpoint
VRB+ 1/2 LSB
2.044V
2.044 V
2.040 V
2.036 V
1;024 V
4.0mV
0.9961 V
0.9961 V
0.992 V
0.988 V
0.000 V
-0.9961 V
<-1.0V
>0.9980 V
0.9980 V
0.9961 V
0.9941 V
0.5000 V
1.95mV
..~y----_./
Cloc!.J
.
latched.
(Valid data available after tCKOV)
Figure 22. Voltage Source for VRT Pin
+ 5.0 to
+ 40 V
O - -.....-:I::-I
n
1.25t02.00V
lM317L2 t:o~ut~-"""---- to VAT
Adj.
Data outputs latched, releases
Comparator latches.
J, 1.0 IlF
240
latches Comparator outputs,
opens data output latches.
510
200
LM317LZ
Figure 20. Enable to Output Critical Timing
. il-
00-07
' 'l,...2-1.--3-State
Line Regulation
TC (ppm/°C) max
AVout for 0 to + 70°C
Initial Accuracy
1.0mV
60
8.4mV
±4%
liming @ 07 to DO measured where waveform starts to change.
Indicated time values are typical @ 25°C, and are in ns.
6-18
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 23. Voltage Sources for VRB Pin
0.1
-5.0to
-40V
620
r
In
J.
LM337MT
10 ~F
- I
.....I
....
...... OR .......
I
I
-2.5 V L
-5.0
to
-40V
R1
R2
100
1.5
kQ
Out (- 1.25 to - 2.00 V)
...-Ad_i._ _-.
120
J.
to VRB
1.0~F
270
I
_J
R1
*0.1
2.5 V Reference
=100 Q for -5.0 V
= 620 Q for-15 V
Line Regulation
TC (ppm/'C) max
R2 = 620 Q for -5.0 V
3.0 kQ for-15 V
=
d Vout for 0 to + 70'C
Initial Accuracy
LM337MT
1.0mV
•
48
6.7mV
±4%
Figure 24. Composite Video Waveform
INPUT
OUTPUT
Figure 25. SIN2 x Waveform
INPUT-.
OUTPUT-.
MOTOROLA ANALOG IC DEVICE DATA
6-19
MC10319
Figure 26. Application Circuit for Digitizing Video
+s.OV
0-------.--.....---1__----,
14.3 MHz Clock ) - - - - - - - ,
EN VCC(A)
VCC(D)
EN
-=
-
CLK
~
VAM
OA
Ire!
MC10319
VAT
07
•
•
•
•DO
0.1
VAS
-=
II
Vin
VEE
1.5kO
GND
-S.2V
6200
1/2W
-2.5V
3.0kO
Output
Data
10flF
0.1*
-15V
-=
3.0pF
1.0kO
>10flF 250
Video Input
~I----WV--.......-I
(1.0Vpp)
500
NOTES: 1)
2)
3)
4)
5)
6-20
MC34080's powered from ± 15 V supplies. MC34083 (Dual) may be used.
Bypass capacitors required at power supply pins of alllCs.
Ground plane required over all parts of circuit board.
Care in layout around MC34080's necessary for good frequency response.
AI = MC34002.
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 27. 9-Bit AID Converter
GNO
EN
Oto25 MHz
Clock
OR
07
ClK
+2.0V
r
MC10319
VRT
0.1
VRM
VRB
••
••
00
EN
Yin VEE VCC(O) VCC(A)
0.1
500n
~
-5.2 V
ClK
VEE VCC(O) VCC(A)
0.1
r
.,..
-2.0V
VRT
VRB
EN
GNO
MOTOROLA ANALOG IC DEVICE DATA
08
07
07
••
••
00
Yin
+5.0V
OR
II
MC10319
ClK
Yin
OR
EN
VRM
00
latches
(Optional)
6-21
MC10319
Figure 28. 50 MHz 8-Bit AID Converter
SO MHz
Clock
CK
o
h
GNO
*""
Q
74F74 Q
EN
OR
EN
ClK
+1.0V
;.~
~
07
MC10319
VAT
(#1)
VRM
•••
•
DO
VRB
+S.OV
Yin VEE
VCC(O) VCC(A)
1$-"
$"
-
EN
'---
ri-
VEE
VCC(O) VCC(A)
VAT
VRM
.... 0.1
-1.0V
-S.2V
74F32
OR
OR
VRB
MC10319
ClK
(#2)
Yin
Yin
+S.OVO--- EN
r-07
07
•••
•
DO
==
== ' - - -
GNO
Latches
(Optional)
.l..
SO MHz Clock
••
•••
DO
I
I
Q~
I
I
00-07(#1) ---T-<,-:alid,9ata)
I
00-07(#2)~
--'-4~
S.SV)
7
8
MC34063A
2
0.16%
load Regulation
Yin =5.0 V. 8.0 mA <
lout < 20mA
0.4%
Output Ripple
Yin =5.0 V. lout =20 mA
2.0mVpp
Short Circuit lout
Yin
=5.0 V. R1 =0.1 0
Yin =5.0 V. lout =50 mA
140mA
Efficiency
3.0kQ
Results
4.5V < Yin < 5.5V.
lout = 10mA
2.20
6
Conditions
Test
Line Regulation
52%
1.0kQ
Vout
t-....r.,.,..,,,--++--o -5.0 VJ20 rnA
l470~F
MOTOROLA ANALOG IC DEVICE DATA
MC10319
GLOSSARY
Aperture Delay - The time difference between the sampling
signal (typically a clock edge) and the actual analog signal
converted. The actual signal converted may occur before or
after the sampling signal, depending on the internal
configuration of the converter.
Bipolar Input - A mode of operation whereby the analog
input (of an AID), or output (of a DAC), includes both
negative and positive values. Examples are - 1.0 to + 1.0 V,
- 5.0 to + 5.0 V, - 2.0 to + 8.0 V, etc.
Bipolar Offset Error - The difference between the actual
and ideal locations of the DOH to 01 H transition, where the
ideal location is 1/2 LSB above the most negative
reference voltage.
Load Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the load current is varied.
The error is typically expressed as a percent of the nominal
output voltage.
LSB - Least Significant Bit. It is the lowest order bit of a
binary code.
Monotonicity - The characteristic of the transfer function
whereby increasing the input code (of a DAC), or the input
signal (of an AID), results in the output never decreasing.
MSB - Most Significant Bit. It is the highest order bit of a
binary code.
Natural Binary Code - A binary code defined by:
N =An2n + ... + A323 + A222 + A121 + A020
Bipolar Zero Error - The error (usually expressed in LSBs)
of the input voltage location (of an AID) of the 80H to 81 H
transition. The ideal location is 1/2 LSB above zero volts in
the case of an AID setup for a symmetrical bipolar input
(e.g., - 1.0 to + 1.0 V).
where each "A" coefficient has a value of 1 or O. Typically, all
zeroes correspond to a zero input voltage of an AID, and all
ones correspond to the most positive input voltage.
Differential Nonlinearity - The maximum deviation in the
actual step size (one transition level to another) from the ideal
step size. The ideal step size is defined as the Full Scale
Range divided by 2n (n =number of bits). This error must be
within ± 1 LSB for proper operation.
Offset Binary Code - Applicable only to bipolar input (or
output) data converters, it is the same as Natural Binary,
except that all zeros correspond to the most negative input
voltage (of an AID), while all ones correspond to the most
positive input.
ECL - Emitter coupled logic.
Power Supply Sensitivity - The change in a data
converter's performance with changes in the power supply
voltage(s). This parameter is usually expressed in percent of
full scale versus tN.
Full Scale Range (Actual) - The difference between the
actual minimum and maximum end points of the analog input
(of an AID).
Full Scale Range (Ideal) - The difference between the
actual minimum and maximum end points of the analog input
(of an AID), plus one LSB.
Gain Error - The difference between the actual and
expected gain (end point to end point), with respect to the
reference, of a data converter. The gain error is usually
expressed in LSBs.
Grey Code - Also known as reflected binary code, it is a
digital code such that each code differs from adjacent codes
by only one bit. Since more than one bit is never changed at
each transition, race condition errors are eliminated.
Integral Nonlinearity - The maximum error of an AID, or
DAC, transfer function from the ideal straight line connecting
the analog end points. This parameter is sensitive to
dynamics, and test conditions must be specified in order to
be meaningful. This parameter is the best overall indicator of
the device's performance.
Line Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the input to the regulator
is varied. The error is typically expressed as a percent of the
nominal output voltage.
MOTOROLA ANALOG IC DEVICE DATA
Nyquist Theorem - See Sampling Theorem.
Quantitlzation Error - Also known as digitization error or
uncertainty. It is the inherent error involved in digitizing an
analog signal due to the finite number of steps at the digital
output versus the infinite number of values at the analog
input. This error is a minimum of ± 1/2 LSB.
Resolution - The smallest change which can be discerned
by an AID converter, or produced by a DAC. It is usually
expressed as the number of bits (n), where the converter has
2n possible states.
Sampling Theorem - Also known as the Nyquist Theorem.
It states that the sampling frequency of an AID must be no
less that 2x the highest frequency (of interest) of the analog
signal to be digitized in order to preserve the information of
that analog signal.
Unipolar Input:" A mode of operation whereby the analog
input range (of an AID), or output range (of a DAC), includes
values of a signal polarity. Examples are 0 to + 2.0 V, 0 to
- 5.0 V, 2.0 to 8.0 V, etc.
Unipolar Offset Error - The difference between the actual
and ideal locations of the DOH to 01 H tranSition, where the
ideal location is 112 LSB above the most negative
input voltage.
6-23
II
•
II
6-24
MOTOROLA ANALOG IC DEVICE DATA
Interface Circuits
In Brief ...
Described in this section is Motorola's line of interface
circuits, which provide the means for interfacing with
microprocessor or digital systems and the external world, or
to other systems.
Also included are devices which allow a microprocessor
to communicate with its own array of memory and peripheral
1/0 circuits.
The line drivers, receivers, and transceivers permit
communication between systems over cables of several
thousand feet in length, and at data rates of up to several
megahertz. The common EIA data transmission standards,
several European standards, and IEEE-488 are addressed
by these devices.
The peripheral drivers are designed to handle high
current loads such as relay coils, lamps, stepper motors, and
others. Input levels to these drivers can be TTL, CMOS, high
voltage MOS, or other user defined levels. The display
drivers are designed for LCD or LED displays, and provide
various forms of decoding.
MOTOROLA ANALOG IC DEVICE DATA
Page
Enhanced Ethernet Transceiver .................... 7-2
ISO 8802-3[IEEE 802.3110BASE-TTransceiver ..... 7-3
Hex EIA-485 Transceiver with
Three-State Outputs ............................. 7-4
5.0 V, 200 M-BiVSec PR-IV Hard Disk
Drive Read Channel ............................. 7-5
Microprocessor Bus Interface ...................... 7-7
Magnetic ReadlWrite ........................... 7-7
Single-Ended Bus Transceivers .................... 7-7
For Instrumentation Bus, Meets
GPIBIIEEE Standard 488 ...................... 7-7
For High Current Party-Line Bus for Industrial and
Data Communications ......................... 7-7
Line Receivers ................................... 7-7
General Purpose .............................. 7-7
EIA Standard .................................. 7-7
Line Drivers ..................................... 7-8
EIA Standard .................................. 7-8
Line Transceivers .............................. 7-8
EIA-232-EN.28 CMOS Drivers/Receivers ........ 7-8
Peripheral Drivers ............................. 7-9
IEEE 802.3 Transceivers ........................ 7-9
ReadlWrite Channel .............................. 7-9
Drive Read Channel ............................ 7-9
Inkjet Drivers .................................... 7-9
28-Channellnkjet Driver ........................ 7-9
CMOS Display Drivers ........................... 7-10
Package Overview .............................. 7-11
Device Listing ................................... 7-12
7-1
•
Enhanced Ethernet Transceiver
MC68160FB
TA
= 0° to +70°C, Case 848D
The MC68160 Enhanced Ethernet Interface Circuit is a
BiCMOS device which supports both IEEE 802.3 Access Unit
Interface (AUI) and 10BASE-T Twisted Pair (TP) Interface
media connections through external isolation transformers. It
encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via
10BASE-T or AUI interfaces. The MC68160 gluelessly
RX
RCLK
MFILT
interfaces tothe Ethernet controller contained in the MC68360
Quad Integrated Communications Controller (QUICC) device.
The MC68160 also interfaces easily to most other
industry-standard IEEE 802.3 LAN controllers. Prior to
twisted pair data reception, Smart Squelch circuitry qualifies
input signals for correct amplitude, pulse width, and sequence
requirements.
Manchester
Decoder
ARX+
RXLED
RENA
CLLED
ARX-
Mux
ACX+
w
ACX- c.J
w CLSN
~TXLED
~
ATX- a::
a::
II
w
....
w TENA
~
TX
~
ATX+ 2E
5
X1
Twisted
Pair
Polarity
Error
Control
X2 :
TCLK
~fJ
CS1
CS2
TPEN
APORT
TPAPCE
TPSQEL
TPFULDL
LOOP
Mode
Select
TPJABB
7-2
«
TPTX+ TPTX-
TPLIL
TPSQEL
TPRX-
TPRX+ TPPLR
MOTOROLA ANALOG IC DEVICE DATA
ISO 8802-3[IEEE 802.3] 10BASE-T Transceiver
MC34055DW
TA= 0° to +70°C, Case 751E
The Motorola 10BASE-T transceiver, designed to comply
with the ISO 8802-3[IEEE 802.3)10BASE-T specification,
will support a Medium Dependent Interface (MOl) in an
embedded Media Attachment Unit (MAU). The interface
supporting the Data Terminal Equipment (DTE) is TTL,
CMOS, and raised ECl compatible, and the interface to the
Twisted Pair (TP) media is supported through standard
10BASE-T filters and transformers. Differential data intended
for the TP media is provided a 50 ns pre-emphasis and data
at the TP receiver, is screened by Smart Squelch circuitry for
specific threshold, pulse width, and sequence requirements.
Loop Back
Test Select
Balun
TX Data A
Data Out
3 TXData B
4
TXENH
8 RXDataA
9 RXDataB
to RXENH
SIA
14
CTLH
13 JABB H
22 SQE EN L
Duplex
Mode
Select
MOTOROLA ANALOG IC DEVICE DATA
7-3
•
Hex EIA-485 Transceiver with Three-State Outputs
MC340S8IS9FTA
TA
= 0° to +70°C, Case 932
The Motorola MC34058/9 Hex Transceiver is composedof
six driver/receiver combinations designed to comply with the
EIA-485 standard. Features include three-state outputs,
thermal shutdown for each driver, and current limiting in both
directions. This device also complies with EIA-422 and
CCID Recommendations V.11 and X.27.
The devices are optimized for balanced multipoint bus
transmission at rates to 20 MBPS (MC34059). The driver
outputs/receiver inputs feature a wide common mode voltage
range, allowing for their use in noisy environments. The
current limit and thermal shutdown features protect the
devices from line fault conditions.
The MC34058/9 is available in a space saving 7.0 mm 48
lead surface mount quad package designed for optimal heat
dissipation.
• Meets EIA-485 Standard for Party Line Operation
• Meets EIA-422A and CCID Recommendations V.11 and
X.27
• Operating Ambient Temperature: O°C to +70°C
• Common Mode Driver Output/Receiver Input Range: -7.0
to +12V
• Positive and Negative Current Limiting
• Transmission Rates to 14 MBPS (MC34058) and 20
MBPS (MC34059)
• Driver Thermal Shutdown at 150°C Junction Temperature
• Thermal Shutdown Active Low Output
• Single +5.0 V Supply, ±10%
• Low Supply Current
• Compact 7.0 mm 48 Lead TQFP Plastic Package
• Skew Specified for MC34059
II
Gnd
36 Gnd
Gnd
35 OA5
OA6
3
34 065
066
4
DR4
DR1
OA4
OAl
064
061
DE4
DEl
8
29 RE4
REl
9
28 063
062
10
27 OA3
OA2
11
26 Gnd
Gnd
12
25 Gnd
Gnd
7-4
Gnd
DE2
RE2
DR2
DR3
RE3
DE3
Gnd
MOTOROLA ANALOG IC DEVICE DAT~
5.0 V, 200 M-BitiSec PR-IV Hard Disk Drive Read Channel
MC34250FTA
TA = 0° to +70°C, Case 840F
The Motorola MC34250 is a fully integrated partial
response maximum likelihood disk drive read/write channel
for use in zoned recording applications. This device integrates
the AGC, active filter, 7 tap equalizer, Viterbi detector,
frequency synthesizer, servo demodulator, 8/9 rate (0,4/4)
Encoder/Decoder with write precompensation and power
management in a single 64 pin 10 mm x 10 mm TQFP
package.
• Programmable Asymmetrical Boost of Up to ±40% of
Nominal Filter Group Delay in Both Data and Servo
Modes
FEATURES:
• Fast Acquisition Data Phase locked loop with Zero
Phase Restart
• 50 to 200 MBPS Programmable Data Rate
• 800 mW at 200 MBPS and 5.0 V
• Channel Monitor Output
• Programmable AGC Charge Pump Currents with
Different Values for Data and Servo Envelope Modes and
Gain Gradient Mode
• Programmable AGC Peak Detector Droop Currents with
Different Values for Data and Servo Envelope Modes
• Separate AGC Charge Pump Outputs for Data and Servo
Modes
• Programmable Dual Threshold Qualifier or Hysteresis
Comparator Type Pulse Detector for Servo Data
Detection.
• ERD and Polarity Outputs for Servo Timing and Raw
Encoded Data
• Integrated 7 pole 0.05° Equiripple Linear Phase Filter with
Programmable Bandwidth from 5.0 MHz to 80 MHz and
Different Values for Both Data and Servo Modes
• Programmable Symmetrical Boost from 0 to 10 dB and
Different Values for Data and Servo Modes
MOTOROLA ANALOG IC DEVICE DATA
• 7 Tap Continuous Time Transversal Equalizer with 8 Bit
Programmable Tap Weights and Integrated Decision
Directed Sign-Sign least Mean Squared Adaptation
• Internal Offset Cancellation loops
• Programmable Data Phase locked loop Charge Pump
Current
• Integrated Soft Decision Viterbi Detectors with
Programmable Merge References
• Integrated 8/9 Rate (0,4/4) Encoder and Decoder with
Code Scrambler and Descrambler
• Programmable 21418 Bit NRZ Data Interface
• Programmable Write Precompensation Delays locked to
the Frequency Synthesizer
• Differential PECl Write Data Outputs
• External Write Data Path for DC Erase or Other
Non-Encoded Data
• Integrated Write Current DAC
• Programmable Power Management
• Bi-Directional Serial Microprocessor Interface
• Various Test Modes Controlled Via the Serial
Microprocessor Interface
7-5
•
..
~I
'" '" '" '"
::0
::0
~
"'tJ
ED
:ii
:1i! :1i! ~ g ~ ~
~ :::c g -I -t --f -i
CD
!:H
--f
~ ~
UI
b
::0
:D
~~ClJcn~~~ en
(f)
~
~
<:>
<:>
.."
.."
-0
~<
-0
,....
,....
,.... -0
,....
;;::
N
0
0
s:::I
I:D
s::
~
0
Co)
Thresholds
""
CD
0
I\)
UI
Q
."
::D
CLAMPB
0
-
I
_._- --------
l.
t--I
r--1
Path Memory
I
-t-OATP1M
<
::J:
.1»
t\lr£1V1
VINP
c
VINM
HOLDB
CDATA~ Mux
CSRVO
8/9 (0.414) ENDEC
Synchronization
Byte Detect
h
CREG
:a
0
SLEEPB
Power
Manager
f f
Mode
l>
l>
r0
C>
(')
C
FREF
Fre~uency
Synt esizer
ZoneClk
WCDAC
Data
-~
I·
Write
Precompensation
WDATAP
WDATAM
en en
-< -<
~
:I: ~
.."
-0
.."
;;::
~
Z
:I:
'"
~
:E
m
m
en
Z
en
m
~
.CD
8'a
3'
SDATA
SCLK
<
il
::I
::I
MCU Interface
m
(')
::D
CD
I»
I»
SLATCH
Z
:C'
CD
::r
Coefficients
>
~
..,C
(')
Offset
Cancel
CFILT
ii'
a.
rnresnOias
RBIAS
a
SYNCDET
NRZ(7:0)
NRZCLK
READGT
WRITEGT
'-------'
SRVOGT 0
!!:
a
C
CD
.....a.
Microprocessor Bus Interface
Motorola offers a spectrum of line drivers and receivers
which provide interfaces to many industry standard
specifications. Many of the devices add key operational
features, such as hysteresis, short circuit protection, clamp
diode protection, or special control functions.
Table 1. Magnetic ReadlWrite
Device
MC3467'
Comments
Magnetic Tape Sense Amplifier. Trace independent preamplifiers with individual gain
control. Optimized for use with 9-track magnetic tape memory systems .
TA
eC)
Suffix!
Package
Oto+70
P1707
• Not recommended for new designs.
Single-Ended Bus Transceivers
Table 2. For Instrumentation Bus, Meets GPIB/IEEE Standard 488
Driver Characteristics
Receiver Characteristics
Output
Current
(rnA)
Propagation
Delay
Max (ns)
Propagation
Delay
Max (ns)
Transceivers
Per Package
Device
Suffix!
Package
48
17
25
4
MC3448A'
P/648,
Comments
Input hysteresis, open coliector,
3-state outputs with terminations
01751B
"'Not recommended for new deSigns.
Table 3. For High Current Party-Line Bus for Industrial and Data Communications
Driver Characteristics
Receiver Characteristics
Output
Current
(rnA)
Propagation
Delay
Max (ns)
Propagation
Delay
Max (ns)
Transceivers
Per Package
Device
100
15
15
4
MC26S10'
Suffix!
Package
Comments
Open collector outputs, common
enable
P/648,
0/751B
"Not recommended for new designs.
Line Receivers
Table 4. General Purpose
S= Single
Ended
0= Differ·
entlal
0
Type
of
Output
TP
OC(l)
tprop
Delay
Time
Max (ns)
Party
Line
Operation
Strobe
or
Enable
Power
Supplies
25
V
V
±5.0
(V)
Device
MC3450'
Suffix!
Package
Receivers
Per
Package
P/648
4
Receivers
Per
Package
Companion
Drivers
MC3453
Comments
Quad
(1) OC = Open Collector, TP = Totem-pole output.
.. Note recommended for new designs.
Table 5. EIA Standard
S= Single
Ended
0= Differential
Type
of
Output
tprop
Delay
Time
Max (ns)
Party
Line
Operation
Strobe
or
Enable
Power
Supplies
(V)
Device
Suffix!
Package
S
TP
4000
-
-
+5.0
MC14C89B,
AB
P/646,
01751 A
R(l)
85
-
-
TP
30
V
V
S,O
35
4
Companion
Drivers
MC1488
MC14C88B
MC1489
MC1489A
Comments
EIA-232-01
EIA-562
EIA-232-0
AM26LS32'
PC/648
AM26LS31,
EIA-422/423
SN75175
N/648,
MC75174B
EIA-4221423/
485
0/751B
(1) R = Resistor Pull-up, TP = Totem-pole output.
.. Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
7-7
•
I
I
Line Drivers
Table 6. EIA Standard
Output
Current
Capebility
(mA)
t prop
Delay
Time
Max (ns)
S= Single
Ended
0= Differential
Party
Line
Operation
Strobe
or
Enable
Power
Supplies
(V)
Device
85
35
0
V
V
+5.0
48
20
15
3500
10
350
60
300
-
S
EIA-
SlO
422
Drivers
Per
Package
MC75174B
MC75172B
P/648
4
AM26LS31*
PC/648
MC26LS31
01751B
±7.0to
±12
MC14C88B
P/646,
01751 A
±9.0to
±12
MCI488
±5.0
AM26LS30
PC/648
MC26LS30
01751B
2 (422)
4(423)
V
EIA423 -
•
Suffix!
Package
Companion
Receivers
Comments
SN75175
EIA-485
MC3486
AM26LS32*
EIA-422
with 3-state
outputs
MC14C89B
MCI4C89AB
EIA-232-0/
EIA-562
MC1489
MCI489A
EIA-232-0
AM26LS32*
EiA-422or
EIA-423
Switchabie
* Not recommended for new deSIgns .
Table 7. Line Transceivers
Driver
Prop
Delay
(Max ns)
Receiver
Prop
Delay
Max (ns)
23
23
DE =Drlver
Enable
RE =Receiver
Enable
OE,RE
Party
Line
Operation
Power
Supplies
V
+5.0
Device
Suffix!
Package
Drivers
Per
Package
Receivers
Per
Package
MC34058
FTAl932
6
6
EIA-485
to 14MBPS
MC34059
FTAl932
6
6
EIA-485
t020MBPS
(V)
EIA
Standard
Table 8. EIA-232-EN.28 CMOS Drivers/Receivers
Suffix!
Package
Pins
Drivers
Receivers
Power
Supplies (V)
MC145403
P1738,
20
3
5
±5.0 to±12
MC145404
OW1751 0
Device
MCI45405
MC145406
MC145407
P/648,
OW1751G,
SO/940B
16
P1738,
20
4
4
5
3
Features
3
+5.0
Charge Pump
OW1751D
MC145408
P1724,
OW1751E,
SO/940B
24
5
5
±5.0 to ±12
MC145583
OW1751F,
VF/940J
28
3
5
+3.3 to +5.0
MC145705
P1738,
OW1751D
20
2
3
+5.0
3
2
P1724,
OW1751E
24
MC145706
MCI45707
7-8
On-board ring monitor circuit;
charge pump, power down
Charge Pump, Power Oown
3
MOTOROLA ANALOG Ie DEVICE DATA
Table 9. Peripheral Drivers
Output
Current
Capability
(mA)
500
Input
Capability
Propagation
Delay Time
Max (Ils)
Output
Clamp
Diode
Off State
Voltage
Max (V)
TTL,CMOS
1.0
V
50
6.0Vto 15V
MOS
1500
Device
UlN2803
Drivers
Per
Package
Suffix!
Package
Logic
Function
8
M07
Invert
7
P/648,
D1751B
P/648,
D1751B
4
B/648C
UlN2804
TTl,5.0V
CMOS
MC1413, B
(UlN2003A)
8.0 Vto 18 V
MOS
MC1416, B
(UlN2004A)
V
50
10 BaseT
NRZ
IEEE
Transmit and
Receive over
4 Pins
Raised
ECl,
CMOS
802.3 Type
10BaseT
Transceiver with non-return to zero (NRZ)
interface. Intended for but not restricted to
concentrators and repeator applications .
DW1751E
TTl,CMOS
802.3 Type
10BaseTI
AUI/NRZ
Interfaces gluelessly to Motorola's MC68360
communications controller.
FB/848D
TTl,5.0V
CMOS
1.0
UlN2068*
Invert
.. Not recommended for new designs.
Table 10. IEEE 802.3 Transceivers
Device
MC34055
Power
Supply
+5.0Vdc
MC68160
Suffix!
Package
Comments
ReadlWrite Channel
Table 11. Hard Disk Drive Read Channel
Device
MC34250
Power
Supply
('C)
Suffix!
Package
Oto+70
FTAl840F
TA
('C)
Suffix!
Package
Oto +70
FNI777
TA
Comments
5.0V
200 Mbps fully integrated partial response maximum likelihood hard disk
drive read/write channel which equalizes to a PR-IV shape and uses 8/9
rate (0, 4/4) coding.
Inkjet Drivers
Table 12. 28-Channel Inkjet Driver
Device
MC34156
Power
Supply
5.0V
Comments
A 4 to 14 line decoder determines the selected output driver in each of
two 14 driver banks. Two independent output enable lines permit 1 or 2 of
28 outputs. Outputs are open collector 30 V Darlington drivers capable of
sinking 500 mAo
MOTOROLA ANALOG IC DEVICE DATA
7-9
•
CMOS Display Drivers
range of end equipment such as instruments, automotive
dashboards, home computers, appliances, radios and Clocks.
These CMOS devices include digit as well as matrix drivers
for LEDs, LCOs, and VFOs. They find applications over a wide
Table 13. Display Drivers
Display Type
LCD
(Direct Drive)
MuxedLCD
(1/4 Mux)
LED,
Incandescent,
Fluorescent(1 )
II
Muxed LED
(1/4 Mux)
MuxedLED
(1/5 Mux)
Input Format
Drive Capability
Per Package
On-Chip
Latch
Display Control
Segment Drive
Current
Device
ParalielBCD
7 Segments
V
Blank
= 1.0mA
MC14543B
Blank, Ripple Blank
Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUsj
Parallel BCD
MC14544B
33 Segments
or Dots
20pA
MC145453
48 Segments
or Dots
= 200 pA
MC145000
MC145001
44 Segments
or Dots
Blank, Lamp Test
7 Segments
25 rnA
Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUsj
4 Digits +
Decimals
-
Blank
65 rnA
MC14547B
V
Oscillator
(Scanner)
50 rnA
(Peak)
MC14499
Oscillator (Scanner),
Low Power Mode,
Dimming
Ot035rnA
(Peak)
Adjustable
MC14489
1OmA(2)
MC14495-1
-
MC14558B
5 Characters +
Decimals or 25
Lamps
LED
(Direct Drive)
Parallel Hex
7 Segments +
A thru F Indicator
(Interfaces to
Display Drivers)
Parallel BCD
7 Segments
MC14511B
MC14513B
Blank, Ripple Blank,
Lamp Test
-
Ripple Blank,
Enable
(1) Absolute maximum working vottage = 18 V.
(2) On-chip current-limtting resistor.
Table 14. Functions
Device
MC14489
Package
Function
Multi-Character LED Display/Lamp Driver
738,7510
MC14495-1
Hexadecima\-to-7 Segment Latch/Decoder ROM/Driver
648,751G
MC14499
4-Digit 7-Segment LED Display Decoder/Driver with Serial Interface
707, 7510
MC14511B
BCD-to-7-Segment Latch/DecoderlDriver
648,751G
MC1.4513B
BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking
726,707
MC14543B
BCD-to-7-Segment Latch/Decoder/Driver for Liquid Crystals
620,648
MC14544B
BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking
726,707
MC14547B
High-Current BCD-to-7-Segment Decoder/Driver
620,648
MC14558B
BCD-to-7-Segment Decoder
620,648
MC145000
48-Segment Serial Input Multiplexed LCD Driver (Master)
709,776
MC145001
44-Segment Serial Input Multiplexed LCD Driver (Slave)
707,n6
MC145453
33-8egment, Non-Multiplexed LCD Driver with Serial Interface
711,n7
7-10
MOTOROLA ANALOG IC DEVICE DATA
Interface Circuits Package Overview
-CASE 646
PSUFFIX
CASE 620
CASE 648
N, P, PC SUFFIX
CASE 709
PSUFFIX
-- CASE 724
P SUFFIX
CASE 711
P SUFFIX
CASE 751A
DSUFFIX
CASE 707
A SUFFIX
CASE 751B
DSUFFIX
CASE 751D
DWSUFFIX
• •
• •
CASE 726
CASE 751E
DWSUFFIX
CASE 751G
DWSUFFIX
CASE 776
FN SUFFIX
CASEn7
FNSUFFIX
CASE 848D
FBSUFFIX
CASE 932
FTASUFFIX
CASE 940B
SDSUFFIX
MOTOROLA ANALOG IC DEVICE DATA
•
CASE 738
PSUFFIX
CASE 751F
DWSUFFIX
•
CASE840F
FTASUFFIX
CASE 940J
VFSUFFIX
7-11
Device Listing
Interface Circuits
II
Device
Function
AM26LS30
Dual Differential (EIA-422-:-A)/Quad Single-Ended
(EIA-423-A) Line Drivers ............................. " ....... 7-13
Quad Line Driver with NAND Enabled Three-State Outputs . . . . . . . . . .. 7-24
Quad EIA-4221423 Line Receiver with Three-State Outputs .......... 7-27
High Voltage, High Current Darlington Transistor Arrays .............. 7-30
Quad Line Driver ................................................ 7-33
Quad Line Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-39
Quad Low Power Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-44
Quad Low Power Line Receivers .................................. 7-50
Ouad Open-Collector Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-55
Quad Bidirectional Instrumentation Bus (GPIB) Transceiver . . . . . . . . . .. 7-58
Quad MTTL Compatible Line Receivers ............................ 7-e4
MTTL Compatible Quad Line Driver ................................ 7-71
Triple Wideband Preamplifier with Electronic Gain Control (EGC) ...... 7-76
Quad Single-Ended Line Drivers .................................. 7-81
Dual EIA-423/EIA-232D Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-86
IEEE 802.3 1OBASE-T Transceiver ................................ 7-90
Hex EIA-485 Transceiver with Three-State Outputs ................. 7-105
28-Channellnkjet Driver ......................................... 7-116
5.0 V, 200 M-BitiSec PR-IV Hard Disk Drive Read Channel .......... 7-118
Enhanced Ethernet Transceiver ...................... '" .......... 7-120
Quad EIA-485 Line Drivers with Three-5tate Outputs ................ 7-146
Quad EIA-485 Line Receiver ..................................... 7-157
Quad 1.5 A Sinking High Current Switch ............................ 7-162
Octal High Voltage, High Current Darlington Transistor Arrays ......... 7-166
AM26LS31*
AM26LS32*
MC1413, B, MC1416, B
MC1488
MC1489,A
MC14C88B
MC14C89B, MC14C89AB
MC26S10*
MC3448A*
MC3450*
MC3453*
MC3467*
MC3481*, MC3485*
MC3488A
MC34055
MC34058, MC34059
MC34156
MC34250
MC68160
MC75172B, MC75174B
SN75175
ULN2068*
ULN2803, ULN2804
Page
NOTE: • Not recommended for new designs.
7-12
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
AM26LS30
Dual Differential (EIA-422-A)/
Quad Single-Ended
(EIA-423-A) Line Drivers
The AM26LS30 is a low power Schottky set of line drivers which can be
configured as two differential drivers which comply with EIA-422-A
standards, or as four single-ended drivers which comply with EIA-423-A
standards. A mode select pin and appropriate choice of power supplies
determine the mode. Each driver can source and sink currents in excess of
50mA.
In the differential mode (EIA-422-A), the drivers can be used up to
10 Mbaud. A disable pin for each driver permits setting the outputs into a
high impedance mode within a ±10 V common mode range.
In the single-ended mode (EIA-423-A), each driver has a slew rate
control pin which permits setting the slew rate of the output signal so as to
comply with EIA-423-A and FCC requirements and to reduce crosstalk .
When operated from symmetrical supplies (±5.0 V), the outputs exhibit zero
imbalance.
The AM26LS30 is available in a 16-pin plastic DIP and surface mount
package. Operating temperature range is -40° to +85°C.
• Operates as Two Differential EIA-422-A Drivers, or Four Single-Ended
EIA-423-A Drivers
DUAL DIFFERENTIAU
QUAD SINGLE-ENDED
LINE DRIVERS
SEMICONDUCTOR
TECHNICAL DATA
PC SUFFIX
PLASTIC PACKAGE
CASE 648
•
FN SUFFIX
PLASTIC PACKAGE
CASE 775
a
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
• High Impedance Outputs in Differential Mode
• Short Circuit Current Limit In Both Source and Sink Modes
PIN CONNECTIONS
• ± 10 V Common Mode Range on High Impedance Outputs
• ± 15 V Range on Inputs
• Low Current PNP Inputs Compatible with TTL, CMOS, and MOS
Outputs
• Individual Output Slew Rate Control in Single-Ended Mode
• Replacement for the AMD AM25LS30 and National Semiconductor
DS3691
Vee
SA-A
InpuIA
~
EnableAB
Mode
Output A
4 Output B
1
Gnd
~
Enable CD
InputD
VEE
SR-B
SR-C
OutputC
Output D
SR-D
(Top View)
Representative Block Diagrams
Single-Ended Mode
EIA-423-A
-C>==SR-A
Input A
Out A
InputB
Differential Mode
EIA-422-A
EnableAB
Input A
QutA
OutB
InputD
QutC
OutD
-c>==SA-B
OutB
InputC
-C>==SR-C
OutC
InputD
-c>==SA-D
Out D
Enable CD
MOTOROLA ANALOG IC DEVICE DATA
VCC-l
VEE-8
Gnd-5
Mode-4
In BiEnAB
OutB
Mode
SR-B
NC
NC
Gnd
SR-C
In C/En CD
OutC
ORDERING INFORMATION
Operating
Temperature Range Package
Device
AM26LS30PC
MC26LS30D
AM26LS30FN
TA = - 40° to +85°C
Plastic DIP
S0-16
PLCG-20
7-13
AM26LS30
MAXIMUM OPERATING CONDITIONS (Pin numbers refer to DIP and 90-16
packages only.) .
Rating
Power Supply Voltage
Symbol
Value
Unit
Vee
VEE
-0.5,+7.0
-7.0,+0.5
Vdc
Input Voltage (All Inputs)
Vin
-0.5, +20
Vdc
Applied Output Voltage when in High Impedance Mode
(Vee = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1)
Vza
±15
Vdc
Output VoHage with Vee, VEE = 0 V
Vzb
±15
10
Self limiting
-
TJ
--65,+150
°e
Output Current
Junction Temperature
Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides
conditions for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Rating
II
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (Differential Mode)
Vee
VEE
+4.75
-0.5
5.0
0
+5.25
+0.3
Vdc
Power Supply Voltage (Single-Ended Mode)
Vee
VEE
+4.75
-5.25
+5.0
-5.0
+5.25
-4.75
Input Voltage (All Inputs)
Applied Output Voltage (when in High Impedance Mode)
Applied Output Voltage, Vee 0
Vin
Vza
Vzb
0
-10
-10
-
+15
+10
+10
Vdc
-
10
--65
-
+65
mA
TA
-40
-
+85
°e
=
Output Current
Operating Ambient Temperature (See text)
All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (EIA-422-A differential mode, Pin 4 .. 0.8 V, -40°C 2.0 V.
7-14
MOTOROLA ANALOG IC DEVICE DATA
AM26LS30
TIMING CHARACTERISTICS (EIA-422-A differential mode, Pin 4 .. O.S V, TA = 25°C, VCC = 5.0 V, VEE = Gnd, (Notes 1 and 3)
unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Differential Output Rise Time (Figure 3)
tr
70
200
ns
Differential Output Fall Time (Figure 3)
tf
-
70
200
ns
Propagation Delay Time - Input to Differential Output
Input Low to High (Figure 3)
Input High to Low (Figure 3)
tpDH
tpDL
-
90
90
200
200
Skew Timing (Figure 3)
I tpDH to tpDL I for Each Driver
Max to Min tpDH Within a Package
Max to Min tpDL Within a Package
tSKl
tSK2
tSK3
-
9.0
2.0
2.0
-
-
Enable Timing (Figure 4)
Enable to Active High Differential Output
Enable to Active Low Differential Output
Enable to 3-State Output From Active High
Enable to 3-State Output From Active Low
tpZH
tpZL
tPHZ
tPLZ
-
150
190
SO
110
300
350
350
300
Characteristic
ns
ns
ns
-
-
ELECTRICAL CHARACTERISTICS (EIA-423-A single-ended mode, Pin 4 '" 2.0 V, -40°C < TA < S5°C, 4.75 V .. IVccl,
IVEE I .. 5.25 V, (Notes 1 and 3) unless otherwise noted).
Characteristic
Symbol
Min
Typ
Max
IVOll
IV 021
4.0
3.6
-
4.2
3.95
0.05
6.0
6.0
0.4
-
±120
-
~
10LK
-100
a
+100
~
ISC+
ISC+
ISCISC-
60
50
-150
-150
SO
150
150
-60
-50
mA
O.S
Vdc
Vdc
I~V021
Slew Control Current (Pins 16,13,12,9)
ISLEW
Output Current (Each Output)
Power Off Leakage, VCC = VEE = 0, -6.0 V .. Vo .. +6.0 V
Short Circuit Current (Output Short to Ground, Note 2)
Vin .. O.S V (TA = 25°C)
Vin .. O.S V (-40°C < TA < +S5°C)
Vln :. 2.0 V (TA = 25°C)
Vin ;;, 2.0 V (-40°C < TA < +S5°C)
Unit
Vdc
Output Voltage (VCC = IVEE I = 4.75 V)
Single-Ended Voltage, RL = 00 (Figure 2)
Single-Ended Voltage, RL = 450 n, (Figure 2)
Voltage Imbalance (Note 5), RL = 450 n
Inputs
Low Level Voltage
High Level Voltage
Current @ Vin = 2.4 V
Current @ Vln = 15 V
Current @ Vin = 0.4 V
Current, 0 .. Yin .. 15 V, VCC = 0
Clamp Voltage (lin = -12 mAl
VIL
VIH
IIH
IIHH
IlL
IIX
VIK
Power Supply Current (Outputs Open)
VCC = +5.25 V, VEE = -5.25 V, Vin = 0.4 V
ICC
lEE
-
-
-95
-
-
a
a
-200
-8.0
-1.5
a
-
-
Vdc
-
17
30
mA
-22
-S.O
-
2.0
-
40
100
~A
TIMING CHARACTERISTICS (EIA-423-Asingle-ended mode, Pin4 .. 2.0 V, TA = 25°C, VCC = 5.0 V, VEE =-5.0 V, (Notes 1 and 3)
unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Output Timing (Figure 5)
Output Rise Time, Cc = 0
Output Fall Time, Cc =
Output Rise Time, Cc = 50 pF
Output Fall Time, Cc = 50 pF
tr
tf
tr
tf
-
65
65
3.0
3.0
300
300
ns
-
Rise Time Coefficient (Figure 16)
Crt
Characteristic
a
Propagation Delay Time, Input to Single Ended Output (Figure 5)
Input Low to High, Cc =
Input High to Low, Cc =
a
a
MOTOROLA ANALOG IC DEVICE DATA
0.06
-
~s
IJSIpF
ns
tPDH
tPDL
-
-
100
100
300
300
tSK4
tSK5
tSK6
-
15
2.0
5.0
-
a
Skew Timing, Cc = (Figure 5)
I tpDH to tPDLI for Each Driver
Max to Min tpDH Within a Package
Max to Min tpDL Within a Package
-
-
ns
-
7-15
a
AM26LS30
Table 1
Inputs
Operation
Vee
Differential
(EIA-422-A)
+5.0
Single-Ended
(EIA-423-A)
Outputs
VEE
Mode
A
B
e
0
A
B
e
0
Gnd
0
0
0
0
0
0
0
1
X
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
1
1
0
1
X
0
1
1
0
Z
Z
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
1
Z
Z
+5.0
-5.0
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
X
X
X
X
X
X
Z
Z
Z
Z
X
x= Don't Care
Z = High Impedance (Off)
•
Figure 1. Differential Output Test
Figure 2. Single-Ended Output Test
Vee
r
Yin
(0.8 or 2.0 V)
Rlf2
vr
2
Rlf2
Mode=O
Yin
(0.8 or 2.0 V)
~s
T
Vo
~
Mode = 1
"::"
Figure 3. Differential Mode Rise/Fail Time and Data Propagation Delay
100
500 pF
i
r-----------~ +3.0 V
1.5V
OV
IPOL
VOD
I
90%
Ir
If
NOTES: 1. S.G. set to: f .. 1.0 MHz; duty cycle = 50%; to tf, .. IOns.
2. tSKI = itPDH""tPDLi for each driver.
3. tSK2 computed by subtracting the shortest tpDH from the longest tpDH of the 2 drivers w~hin a package.
4. tSK3 computed by subtracting the shortest tpDL from the longest tpDL of the 2 drivers within a package.
7-16
MOTOROLA ANALOG IC DEVICE DATA
AM26LS30
Figure 4. Differential Mode Enable TIming
, -_ _ _ _ _ _ _ _ _ _ _ _--,.+3.0 V
Vee
Rl
1.5 V
t
VSS
1.5 V
' - - - - OV
I
(Vin =Hi)
Output
Current
(Vin = la)
NOTES: 1. S.G. setto: f "' 1.0 MHz; duty cycle = 50"/0;10 If. "' 10 ns.
2. Above lests conducted by monitoring output current levels.
Figure 5. Single-Ended Mode Rlse/Fall Time and Data Propagation Delay
r-_ _ _ _ _ _ _ _ _ _ _
Vee
~+2.5V
1.5V
OV
tPOl
500PFT
Vo
*
tf
NOTES: 1. S.G. setto: f "' 100 kHz; duty cycle = 50%; to tf. ",10 os.
2.tSK4 = ItPDfr\pod for each driver.
3.tSK5 computed by subtracting the shortest tpOH from the 10ngesttpOH of the 4 drivers wnhin a package.
4.tSK6 computed by subtracting the shortest tpOL from the 10ngesttpOl of the 4 drivers wHhin a package.
MOTOROLA ANALOG IC DEVICE DATA
7-17
AM26LS30
Figure 6. Differential Output Voltage
versus Load Current
Figure 7. Internal Bias Current
versus Load Current
5.0
40
~ 4.0
L1J
........
~
"
r-
!j
~ 3.0
O~
r-
2.0 -
~
- -- -
Differential Mode
_ Mode =0
Supply Current = Bias Curr.ent + Load Current
Differential Mode
Mode = 0, VCC = 5.0 V
r-- r--
=o'.~T
-fv
8
::> 1.0
V C=5.25V
1D
10
20
30
40
10, OUTPUT CURRENT (rnA)
50
10
60
•
+100
-20
/
6
.!!'
I
V
{
!z -S.O
r-- r- VCC=5.0V
a -10
1/
~~
Nonnally High Ou1put
-60
./
-100
o
~
./
:J:
en
~
Normally Low Ou1put
a:
I:i:
0
o
1.0
/ Differential Mode
Mode = 0, VCC = 5.0 V
2.0
3.0
4.0
Vza , APPLIED OUTPUT VOLTAGE (V)
5.0
j
Pins2to4,6,7
-S.O V < VEE < 0 Differential or
Single-Ended Mode
-15
-20
-25
-1.0
6.0
1.0
"
~
11
~
........
L1J
L1J
..........
4.0
~
..........
~
r---.
~
!3
03.5 -
-
~
..........
r- Single-Ended Mode
f- Mode = 1
VCC = 5.0 V, VEE = -5.0 V
r- Vin= 1
I
-10
7-18
9.0
13
15
-3.25
Cl
~
7.0
Figure 11. Output Voltage versus
Output Sink Current
4.5
:J:
5.0
3.0
Yin, INPUT VOLTAGE (V)
Figure 10. Output Voltage versus
Output Source Current
;::i
120
tccl=o
/'
+60
::>
c.> +20
!::
::>
c.>
(3
100
40
60
80
TOTAL LOAD CURRENT (rnA)
+5.0
«g
a:
20
Figure 9. Input Current versus
Input Voltage
(Pin numbers refer to DIP and 80-16 packages only.)
Figure 8. Short Circuit Current
versus Output Voltage
ffia:
o
I
!3
r---.
V
~
o -4.25
.::.
~
I
-20
-30
-40
10H, OUTPUT CURRENT (rnA)
-3.75
-50
-60
/
"
/
-4.75 0
.- ......-
......- i-"'"'"
---I-'""
---
-
Single-Ended Mode
Mode=1
_
Vee = 5.0 V, VEE = -S.O V _
Vin=O
I
10
I-"""
20
30
40
10L, OUTPUT CURRENT (rnA)
I
50
60
MOTOROLA ANALOG IC DEVICE QATA
AM26LS30
Figure 12. Internal Positive Bias Current
versus Load Current
26
r- dingle kndJ Mod!
I
I
Figure 13. Internal Negative Bias Current
versus Load Current
o
I
Mode=l
f- VCC=5.0V, VEE =-5.0 V
Supply Current = Bias Current + IOH
/
~
/
1-5.0
!z
UJ
,../
a:
a:
5
- V
~
5>
/
V
-r-.
+ol~
-15
Figure 14. Short Circuit Current
versus Output Voltage
110
100
I
60
I
a:
a:
::>
0
!:::
20
j
::>
C3 -20
Ii:
0
1
Normally Low Output
+
=
...J
...J
it
i:iJ
,
;:/~~?
Output Voltage - Low Logic State
(IOL=20mA)
Output Voltage - High Logic State
(IOH = -20 mAl
':Y~;'f
, .: ~ ..
Output Short Circuit Current
(VIH = 2.0 V) Note 1
- ~u.
Output Leakage Current - Hi-Z State
,
(VOL = 0,5 V, VIL(E) = 0,8 V, VIH(~ = 2,0,'4 ,
(VOH = 2.5 V, VIL(E) = 0.8 V, VIH(E) = 2.0~;
Output Leakage Current - Power OFF""
(VOH = 6.0 V, VCC = 0 V)
.:tt,, "!i..,.
(VOL = - 0.25 V, VCC = 0 V)
::'~.~ '.:
~
:. ~.
2,·..
Output Differential Voltage, Note'2
<~~,,,
";
•
,
:.r~,
"i!:i~
......
}9S
/':~.'
"."
':,j,f,..-
:,':~(Z)
"i'
..
Output Differential Voltage Difference, NotEd!
Power Supply Current
(Output Disabled) Note 3
"
·'of
~. ~"
:,' ',;:(
;,:~~.?:>"
~;
.",
" ,"" ';,,>
.. '
:,,:~~'~ ..
,
:: ...;..... ~
::;,',.';'\tOi-t,':"" . .:(::~. ~t2.5
-
,
,
Output Offset Voltage Differ~;N9te
. .
't/':
',':,:-
+20
+100
).LA
).LA
10(0f!)
NOTES: 1. Only one output may be shorted at a time,
2, See EIA Specification EIA-422 for exact test conditions,
3. Circuit in three-state condition.
SWITCHING CHARACTERISTICS (VCC = 5,0 V, TA = 25'C unless otherwise noted.)
Characteristic
Propagation Delay Times
High to Low Output
Low to High Output
Symbol
Min
Typ
Max
tpHL
tpLH
-
-
-
-
20
20
-
-
6,0
ns
Output Skew
Propagation Delay - Control to Output
(CL = 10 pF, RL = 75 Q to Gnd)
(CL = 10 pF, RL = 180 Q to VCC)
(CL = 30 pF, RL = 75 Q to Gnd)
(CL = 30 pF, RL = 180 Q to VCC)
MOTOROLA ANALOG IC DEVICE DATA
ns
ns
tPHZ(E)
tPLZ(E)
tpZH(E)
tpZL(E)
-
-
-
-
30
35
40
45
7-25
AM26LS31
Figure 1. Three-State Enable Test Circuit and Waveforms
3.0VorGnd
Input
To Scope (Input)
To Scope
Output
Pulse generator characteristlcs
Open for tPZH(El Teet On~
Zo~50n
PRR", 1.0 MHz
~+5V
50% Duly Cycle
1nH. trill
180
Enslile
'" 6 ns
Pulse
50
Generator
Rl - See Test Table
; , . - - - - - 3.0V
- - - - - , - - - - - - - 3.0V
COntrol
Input
(Enable)
Output
II
Output
~'\t ,~
Control
Input
(Enable)
'-----VOL
OV
--1------
- lro.
IJZ~::::
_----VOH
~====----- OV
5V
Scope
(Output)
5.0 V
200
75
Zo~50n
PRR", 1.0 MHz
50% Duty Cycle
Cl Includes Probe and Jig CapacHance
lTlH. tTHl '" 6 ns
_---,-----3.0V
Input
Output
Output
:::::::~
7-26
____________~::::VOL
OV
MOTOROLA. ANALOG IC DEVICE DATA
®
MOTOROLA
QUAD EIA-422/423 Line
Receiver with Three-State
Outputs
Motorola's Quad EIA-42213 Receiver features four independent receiver
chains which comply with EIA Standards for the Electrical Characteristics of
Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs
are 74LS compatible, three-state structures which are forced to a high
impedance state when Pin 4 is a Logic "0" and Pin 12 is a Logic "1." A PNP
device buffers each output control pin to assure minimum loading for either
Logic "1" or Logic "0" inputs. In addition, each receiver chain has internal
hysteresis circuitry to improve noise margin and discourage output instability
for slowly changing input waveforms. A summary of AM26LS32 features
include:
AM26LS32
QUAD EIA-42213 LINE
RECEIVER WITH
THREE-5TATE OUTPUTS
SEMICONDUCTOR
TECHNICAL DATA
~~
• Four Independent Receiver Chains
GE
• Three-State Outputs
• High Impedance Output Control Inputs
(PIA Compatible)
• Internal Hysteresis - 30 mV (Typical) @ Zero Volts Common Mo
• Fast Propagation TImes - 25 ns (Typical)
• TTL Compatible
PC SUFFIX
PLASTIC PACKAGE
CASE 648
• Single 5.0 V Supply V o l t a g e . ; , ; ; , , '
• Fail-Safe Input-output Relationship. Output AlwaX$',>"~Whe!1lri
Are Open, Terminated or S h o r t e d "
,"fi"
• 6.0 k Minimum Input Impedance
,;~,:~~~'
PIN CONNECTIONS
Differential
Inputs
InpuisA {
1
Output
OutputsA 3
3-State 4
Control
.......~-----.13 Output8
3-State
12 Control
OutputC 5
11 OutputD
ORDERING INFORMATION
Device
• Note that the surface mount MC26LS32D device uses the same die as in the plastic DIP
AM26LS32DC device, but with an MC prefix to prevent confusion with the package suffix.
MOTOROLA ANALOG IC DEVICE DATA
AM26LS32PC
MC26LS320'
Operating
Temperature Range
TA = Oto 70°C
Package
PlasticOIP
S0-16
7-27
AM26LS32
MAXIMUM RATINGS
~atlng
Symbol
Value
Unit
VCC
7.0
Vdc
VICM
±25
Vdc
VID
±25
Vdc
Three-State Control Input Voltage
VI
7.0
Vdc
Output Sink Current
10
50
mA
Storage Temperature
Tstg
-65to+150
°c
TJ
+ 150
°c
Symbol
Value
Unit
VCC
4.75 to 5.25
Vdc
TA
Oto+70
°c
Input Common Mode Voltage Range
VICR
-7.0to + 7.0
Input Differential Voltage Range
VI DR
6.0
Power Supply Voltage
Input Common Mode Voltage
Input Differential Voltage
Operating Junction Temperature
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and max·
and power supply voltage ranges. Typical values are for TA = 25°C, VCC = 5.0 V an
•
Characteristic
Input Voltage - High Logic State (Three-State Control)
Input Voltage - Low Logic State (Three-State Control)
Differential Input Threshold Voltage (Note 2)
(-7.0 V .. VIC" 7.0 V, VIH = 2.0 V)
(10 = -0.4 mA, VOH ~ 2.7 V)
(10 = 8.0 mA, VOL" 0.45 V)
Input Bias Current
(VCC = 0 V or 5.25) (Other Inputs at -15 V ..
Vin=+15V
Yin :-15 V
6.0K
Input Resistance ( -15 V .. Yin .. + 15Y
Input Balance and Output Level
(-7.0 V .. VIC" 7.0 V, VIH : 2.1t
(10 = -0.4 mA, VID : 0.4
~.
(l0=8.0mA, V I D = - ·
VOH
VOL
2.7
~~~~------~--~~--+-~---r----~-------+----~
Output Third State Leakage
(VI(D) = + 3.0 V, VIL = 0.8 V, Vo = 0.4
(VI(D) = - 3.0 V, VIL = 0.8 V, Vo = 2.4 V)
10Z
Output Short Circuit Current
(VI(D) = 3.0 V, VIH = 2.0 V, Vo = 0 V, See Note 4)
lOS
-15
Input Current - Low Logic State (Three-State Control)
(VIL=0.4V)
Input Current - High Logic State (Three-5tate Control)
(VIH=2.7V)
(VIH = 5.5 V)
Input Clamp Diode Voltage (Three-5tate Control)
(lIC=-18mA)
Power Supply Current (VIL = 0 V) (All Inputs Grounded)
ICC
NOTES: 1. All currents into device pins are shown as pOSitive, out of device pins are negative. All voltages referenced to ground unless otherwise noted.
2. Differential input threshold voltage and guaranteed output levels are done simultaneously for worst case.
3. Refer to EIA-42213 for exact condnions. Input balance and guaranteed output levels are done simultilneously for worst case.
4. Only one output at a time should be shorted.
MOToaOLA ANALOG IC DEVICE DATA
AM26LS32
SWITCHING CHARACTERISTICS (VCC = 5.0 V and TA = 25°C, unless otherwise noted)
Characteristic
Symbol
Propagation Delay Time - Differential Inputs to Output
(Output High to Low)
(Output Low to High)
Min
Typ
Max
-
-
30
30
-
-
35
35
30
30
Unit
ns
tPHL(D)
tPLH(D)
Propagation Delay Time - Three-State Control to Output
(Output Low to Third State)
(Output High to Third State)
(Output Third State to High)
(Output Third State to Low)
ns
tPLZ
tPHZ
tpZH
tpZL
-
-
-
-
Figure 1. Switching Test Circuit and Wave for Propagation Delay Differential Input to Output
To Scope
(Input)
To Scope
(Output)
tPHL(D)
CL = 15 pF
(Includes Probe
and Stray
Capacitanoe)
51
oV
+2.0 V
3-State Control
Input Pulse Characteristics
tn.H - 'THL - 6.0 ns (10% to 90%)
PRR - 1.0 MHz, 50% Duty Cycle
SWl
2.0 k
+ 1.5Vfort
-1.5 Vfor
CL
15pF
(Includes
Probe and Stray
Capacitance)
'='
tpLZ
Input
3.0V~
1.5 V
3.0 V
Input
.. -- ,[ "\ :;g:::
= 1.3 V
Output
VOL
0.5 V
---1-- ---- ov
3 . 0 V , tpZH
Input
v::
___
~
~
; : t::! Open
l
- }
; ; -t:;2Closed
-
Oulput
1.5V
ov - - -
MOTOROLA ANALOG IC DEVICE DATA
All Diodes lN9160r
Equivalent
5.0k
,:-- *:/. . .
SWl Closed
Oulput
= 1.3V
-
- -
- -
-
-
- - OV
tpZL
3.0V
Input
-"'-:~
Oulput
SWl Closed
f
t :"""
1.5 V
VOL _ _ _ _ _ _ _ _ OV
7-29
®
MOTOROLA
MC1413, B
MC1416, B
High Voltage, High Current
Darlington Transistor Arrays
The seven NPN Darlington connected transistors in these arrays are well
suited for driving lamps, relays, or printer hammers in a variety of industrial
and consumer applications. Their high breakdown voltage and internal
suppression diodes insure freedom from problems associated with inductive
loads. Peak inrush currents to 500 rnA permit them to drive incandescent
lamps.
The MC1413, B with a 2.7 kn series input resistor is well suited for
systems utilizing a 5.0 V TTL or CMOS Logic. The MC1416, B uses a series
10.5 kn resistor and is useful in 8.0 to 18 V MOS systems.
PERIPHERAL
DRIVER ARRAYS
SEMICONDUCTOR
TECHNICAL DATA
,.
,
II
PSUFFIX
PLASTIC PACKAGE
CASE 648
ORDERING INFORMATION
Plastic DIP
sOle
Operating
Temperature Range
MC1413P (ULN2003A)
MC1416P (ULN2004A)
MC1413D
MC1416D
TA = -20° to +85°C
MC1413BP
MC1416BP
MC1413BD
MC1416BD
TA = -40° to +85°C
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
PIN CONNECTIONS
Representative Schematic Diagrams
1nMC1413,B
'--'+---t-0 Pin 9
I
I
L __
~
______ _
1nMC1416,B
+-----1~--r--O
Pin 9
I
I
L--+4I------(Top View)
7-30
MOTOROLA ANALOG IC DEVICE DATA
MC1413, B MC1416, B
MAXIMUM RATINGS (TA = 25°C, and rating apply to anyone device in the
package, unless otherwise noted.)
Symbol
Value
Unit
Output Voltage
Rating
Va
50
V
Input Voltage
VI
30
V
Collector Current - Continuous
IC
500
rnA
Base Current - Continuous
IB
25
rnA
Operating Ambient Temperature Range
MC1413-16
MC1413B-16B
TA
Storage Temperature Range
°C
-20 to +85
-40 to +85
Tstg
-55 to +150
Junction Temperature
TJ
150
Thermal Resistance, Junction-ta-Ambient
Case 648, P Suffix
Case 751 B, D Suffix
8JA
NOTE:
°C
°C
°CfW
67
100
ESD data available upon request.
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted)
Characteristic
Output Leakage Current
(Va = 50 V, TA = +85°C)
(Va = 50 V, TA = +25°C)
(Va = 50 V, TA = +85°C, VI = 1.0 V)
Collector-Emitter Saturation Voltage
(IC = 350 rnA, IB = 500 J.IA)
(IC = 200 rnA, IB = 350 J.IA)
(lc = 100 rnA, IB = 250 J.IA)
Symbol
ICEX
All Types
All Types
MC1416,B
VCE(sat)
MC1413,B
MC1416, B
MC1416, B
Input Voltage - On Condition
(VCE = 2.0 V, IC = 200 rnA)
(VCE = 2.0 V, IC = 250 rnA)
(VCE = 2.0 V, IC = 300 rnA)
(VCE = 2.0 V, IC = 125 rnA)
(VCE = 2.0 V, IC = 200 rnA)
(VCE = 2.0 V, IC = 275 rnA)
(VCE = 2.0 V, IC = 350 rnA)
MC1413, B
MC1413, B
MC1413, B
MC1416,B
MC1416, B
MC1416, B
MC1416, B
Input Current - Off Condition
(IC = 500 J.lA, TA = 85°C)
II(on)
VI(on)
All Types
DC Current Gain
(VCE = 2.0 V, IC = 350 rnA)
Typ
-
-
100
50
500
-
1.1
0.95
0.85
1.6
1.3
1.1
-
0.93
0.35
1.0
1.35
0.5
1.45
-
All Types
All Types
All Types
Input Current - On Condition
(VI = 3.85 V)
(VI = 5.0 V)
(VI=12V)
Min
-
Max
Unit
J.lA
V
rnA
-
V
-
-
2.4
2.7
3.0
5.0
6.0
7.0
8.0
II(off)
50
100
-
J.IA
hFE
1000
-
-
-
-
-
-
-
-
Input Capacitance
CI
30
pF
Ion
-
15
Turn-On Delay Time
(50% EI to 50% EO)
0.25
1.0
J.ls
Turn-Off Delay Time
(50% EI to 50% EO)
Ioff
-
0.25
1.0
J.IS
IR
-
Clamp Diode Leakage Current
(VR=50V)
Clamp Diode Forward Voltage
(IF=350mA)
MOTOROLA ANALOG IC DEVICE DATA
TA=+25°C
TA=+85°C
VF
-
-
-
50
100
J.IA
-
1.5
2.0
V
7-31
•
MC1413, B MC1416, B
TYPICAL PERFORMANCE CURVES - TA = 25°C
Figure 1. Output Current versus Input Voltage
400
Figure 2. Output Current versus Input Current
400
I
I
J
/MCI416,B
I
MC1413,B
o
o
1.0
2.0
3.0
I
I
J
4.0
5.0
8.0
9.0
10
11
o
o
12
ffi
!Ii
i3
a:
o
~
500
200
250
300
PIJ13 ~,
Plll0 __
1 Output Conducting at a Time
,.
,
l
y~
!z
w
~PINI6
i
Iff
300
- 100
=>
a.
1.0
-
0.4
0.6
0.8
1.0
1.2
1.4
V
/
/'
V/
Typical
/
/ V
/. V
0.5
/
o
o
1.6
/
V/,
~
All Types
V
Maximum
1.5
~'Y
0.2
2.0
a:
a:
=>
u
I-
~
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VCE(sat), SATURATION VOLTAGE (V)
VI, INPUT VOLTAGE (V)
Figure 5. Input Characteristics - MC1416, B
Figure 6. Maximum Collector Current
versus Duty Cycle
(and Number of Drivers In Use)
2.5
1000
2.0
l
a:
a:
=>
u
ffi
1.5
a:
a:
=>
u
a: 300
!5
a.
1.0
~
0.5
o ~;
o
400
v ./
2.5
o
o
350
Figure 4. Input Chsracteristlcs - MC1413, B
400
!z
w
-- -.....-
Max~
.-""" i-""'"
~
~
5.0
6.0
........
...-
7.0
8.0
9.0
10
11
700
--
W
...J
...J
8
......
............
["'-.......
500
......
........
..........
-...... -......
......
.....
............... ............
-.....:: ~
...........
~
,....-
~I
Vio INPUT VOLTAGE (V)
7-32
150
Figure 3. Typicsl Output Characteristics
6
-
100
110 INPUT CURRENT (!lA)
8200
l
50
I
I
J
VI, INPUT VOLTAGE (V)
800
II l::
AlllTypes
1
200
~
8.0
r"'o
......
......
..........
......
1
r--~
......
1""-1'-~ :::---- ~ .........
.... ......
I""- ....
......
-.........:::
...... .... ....
F=::: :::--- ......
.... ....
..... ....
'"
100
12
10
20
30
50
70
100
% DUTY CYCLE
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC1488
Quad Line Driver
The MC1488 is a monolithic quad line driver designed to interface data
terminal equipment with data communications equipment in conformance
with the specifications of EIA Standard No. EIA-232D.
QUADMDTLUNED~VER
EIA-232D
Features:
• Current Limited Output
± 10 mA typical
SEMICONDUCTOR
TECHNICAL DATA
• Power-Off Source Impedance
300 n mininum
• Simple Slew Rate Control with External Capacitor
• Flexible Operating Supply Range
P SUFFIX
PLASTIC PACKAGE
CASE 646
• Compatible with All Motorola MDTL and MTTL Logic Families
ORDERING INFORMATION
Operating
Temperature Range
Device
MC1488P
Plastic
TA = 0 to + 75°C
MC1488D
•
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
Package
S0-14
PIN CONNECTIONS
Simplified Application
Interconnecting
Una Receiver
MC1489
Cable
I
MDTLLogic Inpu1
I
I
~ Inter~:~ng~
I
MDTLLogicOtJlput
I
Circuit Schematic
(1/4 of Circuit Shown)
Vee 1 4 0 - - - - - - - - < . - - - - - - -......- - - - - < . - - - - - - .
8.2k
Pins4,9,12or2
Input
Input
70
Plns5, 10, 13
300
OUlpUt
PinsS.S, 11 or3
GND7~
10k
7.0k
70
VEElo-------~---4------~---~--~
MOTOROLA ANALOG IC DEVICE DATA
7-33
II
MC1488
MAXIMUM RATINGS (TA = +25°e, unless otherwise noted.)
Symbol
Value
Unit
Power. Supply Voltage
Vee
VEE
+15
-15
Vdc
Input Voltage Range
VIR
-15 .. VIR"
7.0
Vdc
Output Signal Voltage,
Vo
±15
Vdc
Po
1/ReJA
1000
6.7
mW
mw/oe
TA
Oto+75
°e
Tstg
-65to + 175
°e
.Ratlng .
Power Derating (Package limitation, S0-14
and Plastic Dual-ln-Llne Package)
Derate above TA = + 25°C
Operating Ambient Temperature Range
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (Vee =+ 9.0 ± 1% Vdc, VEE =-9.0 ± 1% Vdc, TA =0 to 75°C, unless otherwise noted.)
Characteristic
=0)
=5.0 V)
Input Current - Low Logic State (VIL
Min
Ty~
Max
Unit
IlL
-
1.0
1.6
mA
-
10
Input Current - High Logic State (VIH
IIH
Output Voltage - High Logic State
(VIL 0.8 Vdc, RL 3.0 kO, Vee
(VIL 0.8 Vdc, RL 3.0 kO, Vee
VOH
=+ 13.2 Vdc, VEE =- 13.2 Vdc)
Output Voltage - Low Logic State
(VIH 1.9 Vdc, RL 3.0 kO, Vee
(VIH 1.9 Vdc, RL 3.0 kO, Vee
=+ 9.0 Vdc, VEE =- 9.0 Vdc)
=+ 13.2 Vdc, VEE =-13.2 Vdc)
=
=
II
Symbol
=
=
=
=
= + 9.0 Vdc, VEE =- 9.0 Vdc)
=
=
Positive Output Short-Circuit Current, Note 1
Negative Output Short-CIrcuit Current, Note 1
=VEE =0,
Positive Supply Current (RI =00)
(VIH =1.9 Vdc, Vee =+ 9.0 Vdc)
(VIL =0.8 Vdc, Vee =+ 9.0 Vdc)
(VIH =1.9 Vdc, Vee =+ 12 Vdc)
(VIL =0.8 Vdc, Vee = + 12 Vdc)
(VIH =1.9 Vdc, Vee =+ 15 Vdc)
Output Resistance (Vee
(VIL
IVol
=± 2.0 V)
+6.0
+9.0
+7.0
+10.5
-
-6.0
-9.0
-7.0
-10.5
-
10S+
+6.0
+10
+12
10S-
-6.0
-10
-12
mA
ro
300
-
-
Ohms
-
+15
+4.5
+19
+5.5
+20
+6.0
+25
+7.0
+34
+12
-
-13
-17
-500
-23
-500
mA
-
-34
-
-2.5
mA
mA
-
-
333
VOL
ICC
-
=0.8 Vdc, Vee = + 15 Vdc)
=
Negative Supply Current (RL 00)
(VIH 1.9 Vdc, VEE
9.0 Vdc)
(VIL 0.8 Vdc, VEE
9.0 Vdc)
(VIH 1.9 Vdc, VEE
12 Vdc)
(VIL 0.8 Vdc, VEE -12 Vdc)
(VIH 1.9 Vdc, VEE
15 Vdc)
(VIL 0.8 Vdc, VEE -15 Vdc)
lEE
Power Consumption
(Vee 9.0 Vdc, VEE
(Vee 12 Vdc, VEE
Pc
=
=
=
=
=
=
=
=
====
=-
-
=
=- 9.0 Vdc)
IIA
Vdc
=-12 Vdc)
-
Vdc
mA
mA
-
-18
-
-
IIA
mA
IIA
mW
576
SWITCHING CHARACTERISTICS (Vee = +9.0 ± 1% Vdc, VEE = -9.0 ± 1% Vdc, TA = +25°c.)
Propagation Delay Time (ZI = 3.0 k and 15 pF)
Fall Time
Propagation Delay Time
Rise Time
=3.0 k and 15 pF)
(zi =3.0 k and 15 pF)
(zi =3.0 k and 15 pF)
(zi
275
350
ns
ITHL
-
45
75
ns
tPHL
-
110
175
ns
ITLH
-
55
100
ns
tPLH
NOTE: 1. Maximum Package Power Dissipation may be exceeded ff all outputs are shorted simunaneously.
7-34
MOTOROLA ANALOG IC DEVICE DATA
MC1488
CHARACTERISTIC DEFINITIONS
Figure 1. Input Current
9.0V
Figure 2. Output Voltage
-9.0V
9.0V
-9.0 V
0.8V
Figure 3. Output Short-Circuit Current
Figure 4. Output Resistance (Power Off)
Vee
1.9 V
105+
I
Va
±2.0Vdc
± 6.6 mA Max
105-
12
13
0.8V
Figure 5. Power Supply Currents
Figure 6. Switching Response
Vee
1.9V
"in
--D---I-=,..-3.0-k---1.----.
Va
115 PF
~
1.5V
0.8 V
:1;
trHL
trHL and trLH Measured 10% to 90%
MOTOROLA ANALOG IC DEVICE DATA
7-35
MC1488
TYPICAL CHARACTERISTICS
(TA =+25°C, unless otherwise noted.)
Figure 8. Short Circuit Output Current
versus Temperature
Figure 7. Transfer Characteristics
versus Power Supply Voltage
12
Vcc! VEE;+12~
9.0
vCC=VEE=±9.0V
6.0
;:'!;
3.0
,...
~
0
-
~
Vcc = VEE =±6.0 V
-~
5
-3.0 -
6
-6.0
o
>
'~
VI
-
3.0k
-
O.BV .
VEP 9.0 V
II'
::I.
o
0.2
0.4
0.6
O.B
1.0
1.2
1.4
1.6
1.B
o
2.0
en
125
Figure 9. Output Slew Rate
versus Load Cilpacitance
Figure 10; Output Voltage and
Current-Limiting Characteristics
20
16
1
12
B.O
!z
~ r--
\.
~ 4.0
a
* cL
I I I """
10
I I 1"""
100
~,
0
~
-4.0
.9
-B.O
-12
a
~~
1.0
1.0
75
T, TEMPERATURE (OC)
100
10
25
Vin, INPUT VOLTAGE (V)
~
~
II:
15
...J
-
108-
1000
..,
~
-=-
-9.0
-12
-
108+
~
w
C!l
1,000
1.9 V
•
I\.
\.
-
r-- r--...
~
'"
-
-
I'\.
3.0
.f
~~ 1 -
\.
\.
\.
lOS-
VI
-16 o.av VCC=VEE=±9.0V f,VO
-20
-16
-12
-8.0
-4.0
0
4.0
10,000
b LOA6 LINE
CAPACITANCE (pF)
\
B.O
12
16
Vo, OUTPUT VOLTAGE (V)
Figure 11. Maximum Operating Temperature
versus Power Supply Voltage
~
16
~
14
12
f- Vcc
f- Y-14
10
f-
~ 8.0
f-
~ 6.0
f-
tfl
4.0
f-
>
6 2.0
f-
;:'!;
~
~
c..
ffi
?
0
-55
I .............
I
I
I
............. ~.
...............
J. ~~k
J.. 3.0 k
~
a 3.0k
11 3.0 k
,i.?
-
61
VEE
~
o
25
75
125
T, TEMPERATURE (OC)
7-36
MOTOROLA ANALOG IC DEVICE DATA
MC1488
APPLICATIONS INFORMATION
The Electronic Industries Association EIA-232D specification
details the requirements for the interface between data processing
equipment and data communications equipment. This standard
specifies not only the number and type of interface leads, but also the
voltage levels to be used. The MCt 488 quad driver and its companion
circuit, the MCI489 quad receiver, provide a complete interface
system between DTL or TTL logic levels and the EIA-232D defined
levels. The EIA-232D requirements as applied to drivers are
discussed herein.
The required driver voltages are defined as between 5.0 and 15 V
in magnitude and are positive for a Logic "0" and negative for a Logic
"I." These voltages are so defined when the drivers are terminated
with a 3000 to 7000 n resistor. The MC1488 meets this voltage
requirement by converting a DTUTTL logic level into EIA-232D
levels with one stage of inversion.
The EIA-232D specification further requires that during transitions,
the driver output slew rate must not exceed 30 V per microsecond.
The inherent slew rate of the MC1488 is much too fast for this
requirement. The current limited output of the device can be used to
control this slew rate by connecting a capacitor to each driver output.
The required capacitor can be easily determined by using the
relationship C = lOS x I!..TII!..V from which Figure 12 is derived.
Accordingly, a 330 pF capacitor on each output will guarantee a
worst case slew rate of 30 V per microsecond.
should be placed in each power supply lead to prevent overheating in
this fault condition. These two diodes, as shown in Figure 13, could be
used to decouple all the driver packages in a system. (These same
diodes will allow the MC1488 to withstand momentary shorts to the
± 25 V limits specified in the earlier Standard EIA-232B.) The
addition of the diodes also permits the MC1488 to withstand faults
with power supplies of less than the 9.0 V stated above.
•
Figure 12. Slew Rate versus Capacitance
for ISC 10 mA
=
1000
~
The maximum short circuit current allowable under fault conditions
is more than guaranteed by the previously mentioned 10 mA output
current limiting.
10o ~3(' VlfJS.
w
~
~
(J)
0
~~:
(fllill
'1.0
10
100
1,000
10,000
C, CAPACITANCE (pF)
The interface driver is also required to withstand an accidental
short to any other conductor in an interconnecting cable. The worst
possible signal on any conductor would be another driver using a
plus or minus 15 V, 500 mA source. The MC1488 is designed to
indefinitely withstand such a short to all four outputs in a package as
long as the power supply voltages are greater than 9.0 V (i.e., VCC
'" 9.0 V; VEE';; - 9.0 V). In some power supply designs, a loss of
system power causes a low impedance on the power supply outputs.
When this occurs, a low impedance to ground would exist at the
power inputs to the MC1488 effectively shorting the 300 n output
resistors to ground. If all four outputs were then shorted to plus or
minus 15 V, the power dissipation in these resistors would be
excessive. Therefore, if the system is designed to permit low
impedances to ground at the power supplies of the drivers, a diode
MOTOROLA ANALOG IC DEVICE DATA
Other Applications
The MC1488 is an extremely versatile line driver with a myriad of
possible applications. Several features of the drivers enhance this
versatility:
1. Output Current Limiting - this enables the circuit designer to
define the output voltage levels independent of power supplies and
can be accomplished by diode clamping of the output pins. Figure 14
shows the MC148B used as a DTL to MaS translator where the high
level voltage output is clamped one diode above ground. The
resistor divider shown is used to reduce the output voltage below the
300 mV above ground MaS input level limit.
2. Power Supply Range - as can be seen from the schematic
drawing of the drivers, the positive and negative driving elements of
the device are essentially independent and do not require matching
power supplies. In fact, the positive supply can vary from a minimum
7.0 V (required for driving the negative pulldown section) to the
maximum specified 15 V. The negative supply can vary from
approximately - 2.5 V to the minimum specHied -15 V. The MC14BB
will drive the output to within 2.0 V of the positive or negative supplies
as long as the current output limits are not exceeded. The combination
of the current limiting and supply voltage features allow a wide
combination of possible outputs within the same quad package. Thus
if only a portion of the four drivers are used for driving EIA-232D
lines, the remainder could be used for DTL to MaS or even DTL to
DTL translation. Figure 15 shows one such combination.
7-37
MC1488'
Figure 15. Logic Translator Applications
Figure 14. MDTUMTTL-to-MOS Translator
12V
MOTl
Input
MOTl
MOSOutput
D--...--'\I"""-_--e (with VSS = GNO)
MTTL
1.0k
Input
10k
-12V
-12V
MOTL 4
NAND "-'"-1-....
Gate
Input
-.,..+--0__.-_--1,......_.
MOTL ......-1-...._
MHTl
Input
'"
MOTLOutput
-O,7Vto+S,7V
b-+--o--;;................;~-.
MHTL Output
-O,7Vto10V
10k
-12V
t-38
12V
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC1489, A
Quad Line Receivers
The MC1489 monolithic quad line receivers are designed to interface data
terminal equipment with data communications equipment in conformance
with the specifications of EIA Standard No. EIA-232D.
QUAD MDTL
LINE RECEIVERS
EIA-232D
• Input Resistance - 3.0 k to 7.0 kn
• Input Signal Range - ± 30 V
• Input Threshold Hysteresis Built In
• Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
PLASTIC PACKAGE
CASE 646
ORDERING INFORMATION
Operating
Temperature Range
Device
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
Package
MC1489P,AP
Plastic
TA =Oto+ 75"C
MC1489D,AD
•
S0-14
PIN CONNECTIONS
InpuiA
1
Simplified Application
Interconnecting
UneReceiver
MC1489
Cable
12 Response
COntrol 0
9 Response
controle
1
MDTL logic Input
I
I
I
I
~ 'nter~n:cting~
Ground
MDTlLoglCOutput
7
Representative Schematic Diagram
(1/4 of Circuit Shown)
14
VCC
9.0k
5.0k
1.7k
RF
RespomeCOO1ro12
30U1pu1
3.ak
1",,011
MC1489A
I
1.6 k!l
I
~
MOTOROLA ANALOG IC DEVICE DATA
10k
""
r-..
7GND
7-39
MC1489, A
MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted)
Symbol
Value
Power Supply Voltage
Rating
VCC
10
Vdc
Input Voltage Range
V,R
±30
Vdc
Output Load Current
IL
20
mA
Po
l/9JA
1000
6.7
mW
mW/oC
TA
Oto+75
°C
Tstg
-65to+175
°C
Power Dissipation (Package Limitation, SO-14
and Plastic Dual In-Line Package)
Derate above TA = + 25°C
Operating Ambient Temperature Range
Storage Temperature Range
Unit
ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC = + 5.0 Vdc ± 10%, TA = 0 to + 75°C, unless otherwise noted)
Characteristics
(V,H = + 25 Vdc)
(VIH = + 3.0 Vdc)
Positive Input Current
=-
Negative Input Current
(VIH
25 Vdc)
(V,H = - 3.0 Vdc)
Input Turn-0n Threshold Voltage
(TA + 25°C, VOL'" 0.45 V)
II
=
Min
Typ
Max
Unit
"H
3.6
0.43
-
8.3
mA
',L
-3.6
-0.43
-
-8.3
1.0
1.75
-
1.5
2.25
Vdc
MC1489
MC1489A
1.95
Vdc
V,L
=- 0.5 mAl
MC1489
MC1489A
=-
Output Voltage High
(VIH = 0.75 V, 'L
0.5 rnA)
0.5 mAl
(Input Open Circuit, 'L
Output Voltage Low
(V,L
=3.0 V, 'L =10 mAl
Power Supply Current (All Gates "on," lout = 0 mA, V,H = + 5.0 Vdc)
(V,H = + 5.0 Vdc)
Power Consumption
0.8
1.25
1.25
2.5
2.5
4.0
4.0
5.0
5.0
Vdc
-
0.2
0.45
Vdc
lOS
-3.0
-4.0
mA
ICC
-
16
26
mA
Pc
-
80
130
mW
VOL
Output Short-Circuit Current
-
0.75
0.75
VOH
=-
mA
-
V,H
=
Input Turn-Off Threshold Voltage
(TA + 25°C, VOH '" 2.5 V, 'L
Symbol
SWITCHING CHARACTERISTICS (VCC = 5.0Vdc+
- 1%, TA = + 25°C, See Figure 1.)
Propagation Delay Time
(RL = 3.9 kQ)
tpLH
-
25
85
ns
Rise Time
(RL=3.9kO)
tTLH
120
175
ns
Propagation Delay Time
(RL = 390 kQ)
tpHL
-
25
50
ns
Fall Time
(RL = 390 kQ)
trHL
-
10
20
ns
TEST CIRCUITS
Figure 1. Switching Response
Figure 2. Response Control Node
5.0 Vdc
All diodes
lN3064
or equivalent
E;n
R
P----4----~~---eEo
Cl
,.-_ _...3.0 V
)_50"1._'_ _
trHL
1/4
trLH and trHL
measured
10%-90%
1.5 V
Vin _ _-:.:M:=.C;..;148::;9;.;.A-t
Response Node
b-------_.vo
C, capaCitor is for noise filtering.
R. resistor is for threshold shifting.
CL = 15 pF = total parasitic capacitance which includes
probe and wiring capac~ances
7-40
MOTOROLA ANALOG IC DEVICE DATA
MC1489, A
TYPICAL CHARACTERISTICS
(Vee
=5.0 Vdc. TA =+25°e. unless otherwise noted)
Figure 4. MC1489 Input Threshold
Voltage Adjustment
Figure 3. Input Current
10
6.0
B.O
«
.s
I-
Z
4.0
w
2.0
:::>
0
a:
a:
U
I:::>
D~
,,;.
/'
6.0
-2.0
-4.0
-6.0
/
V
,-
VI
-8.0
-10
-25 -20
V
. / i-""
,.-
5.0
w
4.0
!:i0
3.0
~
C!l
>
I-
:::>
2.0
:::>
0
1.0
DI-
.p
:::>
Y
DI-
:::>
0
.p
-10 -5.0
0
5.0
10
4.0
Rr
S.Ok
3.0 Vth
5.0V
2.0
Rr -Rr
I - RT
1-13k
I - Vth
1-5.0V
I
I--
-11k ' - VIIl ' - -5.0V c - -
00
Y
.:.t
1.0
'-,
'-
0
,-
I-
vlLH VIHL
~
15
20
25
-3.0 -2.0 -1.0
0
1.0
2.0
3.0
Vin. INPUT VOLTAGE (V)
VI. INPUT VOLTAGE (V)
Figure 5. MC1489A Input Threshold
Voltage Adjustment
Figure 6. Input Threshold Voltage
versus Temperature
Rr r-
Rr
S.Ok
Vth
5.0V
00
r-
, - ,~
I-~
VILH - VIHL
u 2.4
~ 2.2
I
I
w
C!l
Y
RT
11 k
Vth
5.0V
!:i
§2
0
...J
0
:r:
w
a:
(f)
=Vth
F
I-
~
-
~
3.0
4.0
:::>
J
I
I
I
I
D~
".
;!;
>
-3.0 -2.0 -1.0
0
1.0
2.0
Vth
I
"" I
~
0
I-
I
-15
~
w
(!)
!:i§2
6.0
u
L
"JJ
I
J
I
5.0
2.0
1.8
1.6
1.4
1.2
1.0
O.B
0.6
0.4
0.2
-
r---
-
I
~AVIHII
I
I
I
~Cl~89VIH _
II
MC148dviL
I
I
0
-60
o
+60
r--
\
MC14B9AVIL
I
I
+120
T. TEMPERATURE (0C)
VI. INPUT VOLTAGE (V)
Figure 7. Input Threshold versus
Power Supply Voltage
2.0
VIH MC1489A
f-- VIH MC1489
VILMCI489
f - VIL MCI489A
4.0
5.0
6.0
VCC. POWER SUPPLY VOLTAGE (V)
MOTOROLA ANALOG Ie DEVICE DATA
7-41
II
MC1489, A
APPLICATIONS INFORMATION
II
General Information
The Electronic Industries Association (EIA) has released
the EIA-232D specification detailing the requirements for the
interface between data processing equipment and data
communications equipment. This standard specifies not only
the number and type of interface leads, but also the voltage
levels to be used. The MC1488 quad driver and its
companion circuit, the MC1489 quad receiver, provide a
complete interface system between DTL or TTL logic levels
and the EIA-232D defined levels. The EIA-232D
requirements as applied to receivers are discussed herein.
The required input impedance is defined as between
3000 nand 7000 n for input voltages between 3.0 and 25 V
in magnitude; and any voltage on the receiver input in an
open circuit condition must be less than 2.0 V in magnitude.
The MC1489 circuits meet these requirements with a
maximum open circuit voltage of one VSE.
The receiver shall detect a voltage between - 3.0 and
- 25 Vasa Logic "1" and inputs between 3.0 and 25 V as a
Logic "0." On some interchange leads, an open circuit of
power "OFF" condition (300 n or more to ground) shall be
decoded as an "OFF" condition or Logic "1." For this reason,
the input hysteresis thresholds of the MC1489 circuits are all
above ground. Thus an open or grounded input will cause the
same output as a negative or Logic "1" input.
Device Characteristics
The MC1489 interface receivers have internal feedback
from the second stage to the input stage providing input
hysteresis for noise rejection. The MC1489 input has typical
turn-on voltage of 1.25 V and turn-off of 1.0 V for a typical
hysteresis of 250 mY. The MC1489A has typical turn-on of
1.95 V and turn-off of 0.8 V for typically 1.15 V of hysteresis.
Each receiver section has an external response control
node in addition to the input and output pins, thereby allowing
the designer to vary the input threshold voltage levels. A
resistor can be connected between this node and an external
power supply. Figures 2, 4 and 5 illustrate the input threshold
voltage shift possible through this technique.
This response node can also be used for the filtering of
high frequency, high energy noise pulses. Figures 8 and 9
show typical noise pulse rejection for external capacitors of
various sizes.
These two operations on the response node can be
combined or used individually for many combinations of
interfacing applications. The MC1489 circuits are particularly
useful for interfacing between MOS circuits and MDTUMTTL
logic systems. In this application, the input threshold voltages
are adjusted (with the appropriate supply and resistor values)
to fall in the center of the MOS voltage logic levels (see
Figure 10).
The response node may also be used as the receiver input
as long as the designer realizes that he may not drive this
node with a low impedance source to a voltage greater than
one diode above ground or less than one diode below
ground. This feature is demonstrated in Figure 11 where two
receivers are slaved to the same line that must still meet the
EIA-232D impedance requirement.
Figure 8. Typical Turn On Threshold versus
Capacitance from Response Control Pin to GND
Figure 9. "TYpical Turn On Threshold versus
Capacitance from Response Control Pin to GND
6r-------".--r.------r--------~
6
MCI489A
MCI489
~
w
0
5
c..
..:
~
~
w
4
0
E
4
...J
c..
::;;
..:
3
.5
3
w"
w
2
1
10
2
100
1000
PW, INPUT PULSE WIDTH (ns)
7-42
10,000
1
10
100
1000
10,000
PW, INPUT PULSE WIDTH (ns)
MOTOROLA ANALOG IC DEVICE DATA
MC1489, A
Figure 10. Typical Translator ApplicationMOS to DTL or TTL
DTL or TIL
r- -,
---I
+5.0
:
Lrl
Vdc. ":"
Figure 11. Typical Paralleling of Two MC1489, A Receivers to Meet EIA-232D
Vee
Respons&-Control Pin
Input
8.0 k
r-----------------,
I
I
I
112 MC1489
Output
Vee 0--'-----------,
Input
8.0k
Respons~ntrol
Pin
MOTOROLA ANALOG IC DEVICE DATA
Output
®
MOTOROLA
MC14C88B
Quad Low Power Line Driver
The MC14C88B is a low power monolithic quad line driver, using BiMOS
technology, which conforms to EIA-232-D, EIA-562, and CCITT V.28. The
inputs feature TTL and CMOS compatibility with minimal loading. The
outputs feature internally controlled slew rate limiting, eliminating the need
for external capacitors. Power off output impedance exceeds 300 Q, and
current limiting protects the outputs in the event of short circuits.
Power supply current is less than 160 itA over the supply voltage range of
±4.5 to ±15 V. EIA-232-D performance is guaranteed with a minimum
supply voltage of ±6.5 V.
The MC14C88B is pin compatible with the MC1488, SN75188,
SN75C188, DS1488, and DS14C88. This device is available in 14 pin plastic
DIP, and surface mount packaging.
QUAD LOW POWER
LINE DRIVER
SEMICONDUCTOR
TECHNICAL DATA
Features:
• BiMOS Technology for Low Power Operation ( < 5.0 mW)
• Meets Requirements of EIA-232-D, EIA-562, and CCITT V.28
•
PSUFFIX
PLASTIC PACKAGE
CASE 646
• Quiescent Current Less Than 160 J4A
• TTUCMOS Compatible Inputs
• Minimum 300 Q Output Impedance when Powered Off
• Supply Voltage Range: ±4.5 to ±15 V
• Pin Equivalent to MC1488
• Current Limited Output: 10 mA Minimum
DSUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
• Operating Ambient Temperature: -400 to 85°C
PIN CONNECTIONS
Representative Block Diagram
OutputA
3
InputB1
4
InputB2
5
11
OutputD
(Each Driver)
Vee
Output B 6
8 Outpute
(Top View)
Output
Input2
ORDERING INFORMATION
o-+-......r
39
Device
Operating
Temperature Range
Package
MC14C88BP
Plastic DIP
1 - - - - - - 1 TA = - 40° to +85°C I--------j
MC14C88BD
S0-14
7-44
MOTOROLA ANALOG IC DEVICE DATA
MC14C88B
MAXIMUM RATINGS (TA = +25°e, unless otherwise noted.)
Rating
Power Supply Voltage
Vee(max)
VEE(min)
(Vee - VEE)max
Symbol
Value
Vee
VEE
Vee-VEE
+17
-17
34
Unit
Vdc
Input Voltage (All Inputs)
Yin
Applied Output Voltage, when Vee=VEE¢O V
Applied Output Voltage, when Vee=VEE = 0 V
Vx
Output eurrent
10
Self limiting
mA
Operating Junction Temperature
TJ
-65, + 150
°e
VEE-{)·3, VEE+39
Vdc
VEE--6.0 V, Vee+6.0 V Vdc
±15
Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides
for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
Vee
VEE
+4.5
-15
-
Vdc
-
+15
-4.5
Yin
0
-
Vec
Vdc
Applied Output Voltage (VCC=VEE=O V)
Vo
-2.0
0
+2.0
Vdc
Output De Load
RL
3.0
-
7.0
k.Q
Operating Ambient Temperature Range
TA
-40
-
+85
°C
Min
Typ
Max
Unit
-
-
160
160
-160
-160
-
-
3.7
4.0
5.0
10
3.8
4.3
6.1
10.5
13.2
-
Input Voltage (All Inputs)
Alilimtts are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (-40o e '" TA ",+85°C, unless otherwise noted.),
Characteristic
Supply Current (lout = 0, see Figure 2)
lee @ 4.75 V '" Vee, -VEE'" 15 V
Outputs High
Outputs Low
lEE
Outputs High
Outputs Low
Symbol
J.LA
ICC (OH)
lee (OL)
lEE (OH)
lEE (OL)
Output Voltage - High, Yin ",0.8 V (RL = 3.0 k.Q , see Figure 3)
Vee = +4.75 V, VEE = -4.75 V
Vee = +5.0 V, VEE = -5.0 V
Vee = +6.5 V, VEE = --6.5 V
Vee=+12V, VEE=-12V
Vee =+13.2 V, VEE =-13.2 V (RL==)
Output Voltage - Low, Yin '" 2.0 V
Vee = +4.75 V, VEE = -4.75 V
Vee = +5.0 V, VEE = -5.0 V
Vee = +6.5 V, VEE = --6.5 V
Vce=+12V, VEE=-12V
Vee =+13.2 V, VEE=-13.2V(RL==)
VOH
Output Short Circutt eurrent** (see Figure 4) (Vee = IVEEI = 15 V)
Normally High Output, shorted to ground
Normally Low Output, shorted to ground
lOS
Output Source Resistance
(Vec = VEE = 0 V, -2.0 V '" Vout ",+2.0 V)
Input Voltage
Low Level
High Level
-
-
VOL
-
Vdc
-
13.2
-3.8
-4.2
--6.0
-10.5
-13.2
-3.7
-4.0
-5.0
-10
-35
+10
-
-10
+35
RO
300
-
-
Q
VIL
VIH
0
2.0
-
-
0.8
Vce
Vdc
-
-13.2
mA
* Typicals reflect performance @ TA = 25°C
** Only one output shorted at a time, for not more than 1 second.
MOTOROLA ANALOG IC DEVICE DATA
7-45
II
MC14C88B
ELECTRICAL CHARACTERISTICS (continued) (-40°C .. TA .. +85°C, unless otherwise noted.)'
Characteristic
Input Current
Vln=OV, VCC= IVeel =4.75V
Vln=OV,VCC= IVeel =15V
Yin = 4.5 V, VCC = IVeel = 4.75 V
Vln = 4.5 V, VCC = IVeel = 15 V
Symbol
Min
Typ
Max
-10
-10
0
0
-0.1
-0.1
+0.1
+0.1
0
0
+10
+10
Min
Typ
Max
Unit
~
lin
TIMING CHARACTERISTICS (-40°C .. TA .. +85°C, unless otherwise noted.)'
Characteristic
Output Rise Time
VCC = 4.75 V, Vee = -4.75 V
-3.3 V "VO .. 3.3 V
CL=15pF
CL = 1000 pF
-3.0 V .. VO" 3.0V
CL=15pF
CL = 1000 pF
VCC = 12.0 V, Vee = -12.0 V
-3.0 V .. VO" 3.0V
CL= 15pF
CL = 2500 pF
10% .. VO" 90%
CL= 15pF
II
Output Fall Time
VCC = 4.75 V, Vee = -4.75 V
3.3 V .. VO .. -3.3 V
CL=15pF
CL= l000pF
3.0V .. VO" -3.0 V
CL=15pF
CL= l000pF
VCC = 12.0 V, Vee = -12.0 V
3.0V "VO" -3.0 V
CL= 15pF
CL= 2500 pF
90% .. VO" 10%
CL=15pF
Output Slew Rate, 3.0 kU < RL < 7.0 ill, 15 pF < CL < 2500 pF
Propagation Delay A (CL = 15 pF, see Figure 1)
VCC = 12.0 V, Vee = -12.0 V
Input to Output - Low to High
Input to Output - High to Low
Propagation Delay B (CL = 15 pF, see Figure 1)
VCC = 4.75 V, Vee = -4.75 V
Input to Output - Low to High
Input to Output - High to Low
Symbol
Unit
~s
tRl
0.22
0.22
0.66
1.52
2.1
2.1
0.20
0.20
0.51
1.16
1.5
1.5
0.20
0.20
0.62
0.82
1.5
1.5
0.53
1.41
3.2
tR2
tR3
~
tFl
0.22
0.22
0.93
1.28
2.1
2.1
0.20
0.20
0.72
1.01
1.5
1.5
0.20
0.20
0.70
0.94
1.5
1.5
0.53
1.71
3.2
4.0
-
30
tF2
tF3
SR
V/~
~s
tpLH
tPHL
-
0.9
2.3
3.0
3.5
tPLH
tpHL
-
0.4
1.5
2.0
2.5
• Typical. reflect performance @ TA = 25°C
7-46
MOTOROLA ANALOG IC DEVICE DATA
MC14C88B
Figure 1. Timing Diagram
J-
S.G.
OV
t
'---+-0
S.G.
1.SV
1-1PLH
j-1PHL
~---VOH
Your
\0---+------ 90% - - - - - - r - - - t o f
~+------ 3.3V'------+--I
NOTES: S.G. sella: f = 20 kHz for Propagation Delay A
and f = 64 kHz for Propagation Delay B; Duty
' f o o - l - - - - - - 3.0 V ' - - - - - - - / l - I
Cycle = 50%; tR, tF" 5.0 ns
Vom---1-~\--------------i~t-+-----OV
\0-----_3.0 V'------oof
~---_3.3V·---_I
-----VOL
STANDARDS COMPLIANCE
The MC14CBB is designed to comply with EIA-232-D
(formerly R8-232), the newer EIA-562 (which is a higher
speed version of the EIA-232), and CCIIT's V.2B. EIA-562
was written around modern integrated circuit technology,
whereas EIA-232 retains many of the specs written around
Parameter
the electro-mechanical circuitry in use at the time of its
creation. Yet the user will find enough similarities to allow a
certain amount of compatibility among equipment built to the
two standards. Following is a summary of the key
specifications relating to the systems and the drivers.
EIA-232-D
EIA-562
Maximum Data Rate
20kbaud
38.4 kbaud Asynchronous
64 kbaud Synchronous
Maximum Cable Length
50 feet
Based on cable capacitance/data rate
Maximum Slew Rate
.; 30 V/flS anywhere on the waveform
.; 30 V/flS anywhere on the waveform
~ 4.0 V/jlS between +3.0 and -3.0 V
Transijion Region
-3.0 to +3.0 V
-3.3 to +3.3 V
Transijion Time
For UI ;;. 25 ms, tR ';;1.0 ms
For 25 ms > UI > 125 flS, tR .;; 4% UI
For UI < 125 flS, tR .;; 5.0 flS
For UI ;;. 50 flS, 220 ns < tR .; 3.1 flS
For UI < 50 flS, 220 ns < tR .; 2.1 flS
(within the transition region)
MARK (one, off)
More negative than -3.0 V
More negative than -3.3 V
Space (zero, on)
More positive than +3.0 V
More positive than +3.3 V
Short Circuit Proof?
Yes, to any system voltage
Yes, to ground
Short Circuit Current
.;; 500 mA to any system voltage
.; 60 mA to ground
Open Circuit Voltage
IVocl .; 25V
IVocl < 13.2 V
Loaded Output Voltage
5.0 V .; IVai .;15 V for loads between
3.0 kO and 7.0 kO
Ivai ;;. 3.7 V for a load of 3.0 kO
Power Off Input Source Impedance
;;.300nlorlvol.;2.oV
'" 300 n lor Ivai.;; 2.0V
NOTE:
UI = Untt Interval, or bit time.
V.28 standard has the same specifications as EIA-232, wtth the exception of transttion time which is listed as "less than 1.0 ms, or 3% of the UI,
whichever is less".
MOTOROLA ANALOG IC DEVICE DATA
7-47
MC14C88B
Figure 2. Typical Supply Current ..
versus Supply Voltage
110
1
Figure 3. Typical Output Voltage
versus Supply Voltage
ICC(OL)
I-
i1i
a:
ICC(OH)
55
a:
:>
<.>
t::
:>
<.>
a:
0
(3
ti:
~
en
w -65
w
8
-
IE!J.OH)
IEE(OL)
-110
8.0
6.0
4.0
10
12
14
16
Vee AND-VEE, (V)
Figure 4. Typical Short Circuit Current
versus Supply Voltage
II
30
1
20
w
a:
a:
10
IZ
:>
<.>
~
t::
:>
~
0
ti:
-10
(3
0
J:
en
0-20
.!!'
-30
.
4.0
--
Ise
,..-
15
Normall~ Low 0tJlpJ1
VOH @Vee
10
I
I
~.~
----,.....
!l.0
~
~
"Ise
0
~
I
VOL @ Vee = -VEE; = 4.5 V
§ -6.0
1
Ise
r'
8.0
~
gj 5.0
(0.8 or 2.0 V)
VEE
f~VEE = 12 V
VOH @ Vcc -VEE= 4.5 V
~
Vee
vOL@veef-VEE=12V
I
-10
Normall~ High Output
10
Vcc AND -VEE, (V)
7-48
Figure 5. Typical Output Voltage
versus Temperature
i
12
'1
14
16
-15
-40
I
22
TA, AMBIENT TEMPERATURE (De)
RL =3.0kO
85
MOTOROLA ANALOG IC DEVICE DATA
MC14C888
APPLICATIONS INFORMATION
Description
The MC14C88 was designed to be a direct replacement
for the MC1488 in that it meets all EIA-232 specifications.
However, use is extended as the MC14C88 also meets the
faster EIA-562 and CCITT V.28 specifications. Slew rate
limited outputs conform to the mentioned specifications and
eliminate the need for external output capacitors. Low
power consumption is made possible by SiMOS technology.
Power supply current is limited to less than 160 f,tA, plus
load currents over the supply voltage range of ±4.5 V to
±15 V (see Figure 2).
Outputs
The output low or high voltage depends on the state of the
inputs, the load current, and the supply voltage (see Table 1
and Figure 3). The graphs apply to each driver regardless of
how many other drivers within the package are supplying
load current.
or rise above VEE by more than 39 V, excessive currents will
flow at the input pin. Open input pins are equivalent to logic
high, but good design practices dictate that inputs should
never be left open.
Operating Temperature Range
The ambient operating temperature range is listed at -40°
to +85°C and meets EIA-232-D, EIA-562 and CCITT V.28
specifications over this temperature range. The maximum
ambient temperature is listed as +85°C. However, a lower
ambient may be required depending on system use, i.e.
specifically how many drivers within a package are used, and
at what current levels they are operating. The maximum
power which may be dissipated within the package is
determined by:
P
Table 1. Function Tables
Driver 1
Input A
Output A
H
L
L
H
where: RaJA = the package thermal resistance (typically,
100°C/W for the DIP package, 125°C/W for the
SOIC package);
T Jmax = the maximum operating junction
temperature (150°C); and
TA =the ambient temperature.
Drivers 2 through 4
Input <1
Input <2
Output<
H
L
X
H
X
L
l
H
H
H = High level, L = Low level, X = Don't care.
Driver Inputs
The driver inputs determine the state of the outputs in
accordance with Table 1. The nominal threshold voltage for
the inputs is 1.4 Vdc, and for proper operation, the input
voltages should be restricted to the range Gnd to VCC.
Should the input voltage drop below VEE by more than 0.3 V
MOTOROLA ANALOG IC DEVICE DATA
TJmax-TA
- -""==:.....--'-'Dmax Ra JA
PD
={[ (VCC -
VOH) x IIOHI) or [(VOL - VEE) x
IIOLi )} each driver + (VCC x ICC) + (VEE x lEE)
where: VCC and VEE are the positive and negative
supply voltages;
VOH and VOL are measured or estimated from
Figure 3;
ICC and lEE are the quiescent supply currents
measured or estimated from Figure 2.
As indicated, the first term (in brackets) must be calculated
and summed for each of the four drivers, while the last terms
are common to the entire package.
7-49
II
®
MOTOROLA
I
Quad Low Power
Line Receivers
The MC14C89B and MC14C89AB are low monolithic quad line receivers
using bipolar technology, which conform to the EIA-232-E, EIA--562 and
CCITT V.28 Recommendations. The outputs feature LSTTL and CMOS
compatibility for easy interface to +5.0 V digital systems. Internal
time-domain filtering eliminates the need for external filter capacitors in most
cases.
The MC14C89B has an input hystereSiS of 0.35 V, while the MC14C89AB
hystereSiS is 0.95 V. The response control pins allow adjustment of the
threshold level if desired. Additionally, an external capacitor may be added
for additional noise filtering.
The MC14C89B and MC14C89AB are available in both a 14 pin
dual-in-line plastic DIP and SOIC package.
MC14C89B, AB
QUAD LOW POWER
LINE RECEIVERS
SEMICONDUCTOR
TECHNICAL DATA
Features:
•
PSUFFIX
PLASTIC PACKAGE
CASE 646
• Low Power Consumption
• Meets EIA-232-E, EIA-562, and CCITT V.28 Recommendations
• TTUCMOS Compatible Outputs
• Standard Power Supply: + 5.0 V ±1 0%
o
SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)
• Pin Equivalent to MC1489, MC1489A, Tl's SN75C189/A, SN75189/A
and National Semiconductor's DS14C89/A
• External Filtering Not Required in Most Cases
• Threshold Level Externally Adjustable
• Hysteresis: 0.35 V for MC14C89B, 0.95 V for MC14C89AB
• Available in Plastic DIP, and Surface Mount Packaging
PIN CONNECTIONS
• Operating Ambient Temperature: -40° to +85°C
VCC
Response
Control A
Input 0
Response
Control 0
Output A
Representative Block Diagram
(Each Receiver)
Response
ControlB
Inpute
OutputB
Response
ControlC
Ground
OutputC
VCC
(Top View)
Input o-t--4I~---.
Response
Control
0-+----.--..
....-t---1t-O Output
ORDERING INFORMATION
Device
Operating
Temperature Range
MC14C89BP
MC14C89ABP
MC14C89ABD
7'-50'
Package
Plastic DIP
TA = -40° to +85°C
Plastic DIP
SO-14
MOTOROLA ANALOG Ie DEVICE DATA
MC14C89B, AB
MAXIMUM RATINGS
Rating
Symbol
Value
VCC
+7.0
-0.5
Power Supply Voltage
VCC(max)
VCC(min)
Unit
Vdc
Input Voltage
Yin
±30
Output Load Current
10
Self-Limiting
Vdc
-
Junction Temperature
TJ
-65,+150
°c
Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides
for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Vonage
Symbol
Min
Typ
Max
Unit
VCC
4.5
5.0
5.5
Vdc
Input Voltage
Vin
-25
-
25
Vdc
Output Current Capability
10
-7.5
-
6.0
rnA
Operating Ambient Temperature
TA
-40
-
85
°C
Min
Typ
Max
Unit
-
330
700
All limit. are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (-40°C '" TA '" +85°C, unless otherwise noted.)'
Characteristic
Symbol
Supply Current (lout = 0)
ICC @ +4.5 V '" VCC '" +5.5 V
ICC
Output Vo~age - High, Yin '" 0.4 V (See Figures 2 and 3)
VCC=4.5V
lout = -20 !1A
VCC=5.5V
Vce=4.5V
'out = -3.2 rnA
Vce=5.5V
Output Voltage - Low, Yin ;;. 2.4 V
VCC=4.5V
'out=3.2mA
VCC=5.5V
VOH
Output Short Circuit Current·· (VCC = 5.5 V, see Figure 4)
Normally High Output shorted to ground
Normally Low Output shorted to VCC
lOS
VOL
Vdc
V,L
V,H
V,L
V,H
Input Impedance (+4.5 V < VCC < +5.5 V -25 V < Vin < +25 V)
-
3.5
3.5
2.5
2.5
3.8
4.8
3.7
4.7
-
-
0.1
0.1
0.4
0.4
-35
-
-13.9
+10.3
35
0.75
1.6
0.75
1.0
0.95
1.90
0.95
1.3
1.25
2.25
1.25
1.5
Vdc
3.0
5.5
7.0
k!l
Min
Typ
Max
Unit
-
0.08
0.30
/1S
-
3.35
2.55
6.0
6.0
/1S
1.0
1.5
-
/1S
-
Input Threshold Voltage (Vce = 5.0 V)
(MC14C89AB, see Figure 5)
Low Level
High Level
(MC14C89B, see Figure 6)
Low Level
High Level
IlA
rnA
• Typical. reflect performance @ TA = 25°C
··Only one output shorted at a time, for not more than 1.0 seconds.
TIMING CHARACTERISTICS (TA = +25°C, unless otherwise noted.)
Characteristic
Output Transition Time (10% to 90%)
Symbol
IT
4.5V '" Vce '" 5.5V
Propagation Delay Time
4.5V '" Vce '" 5.5V
Output Low-ta-High
Output High-ta-Low
Input NOise Rejection (see Figure 9)
MOTOROLA ANALOG IC DEVICE DATA
tpLH
tpHL
7-51
a
MC14C89B, AB
Figure 1. Timing Diagram
J-
S.G.
OV
Vee
sa~~~f !
':' (Open)
1.5V
~-+-----90% _ _ _ _ _-l-_r-:----VOH
Vout
':'
NOTES: S.G. set to: , = 20 kHz;
Duty Cycle = 50%;
tr,t, .. 5.On8
I ' - - - - - - ' t - - - - - t - - - - VOL
STANDARDS COMPLIANCE
II
The MC14C89B and MC14C89AB are designed to. comply
with EIA-232-E (formerly RS-232), the newer EIA-562
(which is a higher speed versian af the EIA-232), and CCITT
V.28 Recammendatians. EIA-562 was written araund
modern integrated circuit technalagy, whereas EIA-232
retains many af the specifications written around the
Parameter
Max Data Rate
electro-mechanical circuitry in use at the time of its creation.
Yet the user will find enough similarities to allow a certain
amaunt of campatibility amang equipment built to. the twa
standards. Following is a summary of the key specifications
relating to. the systems and the receivers.
EIA-562
EIA-232-E
20. kBaud
38.4 kBaud Asynchronous
64 kBaud Synchronous
Max Cable Length
SO. feet
Based on cable capacitance/data rate
Transition Region
-3.0. V to +3.0. V
-3.0. V to +3.0. V
MARK (one, off)
More negative than -3.0. V
More negative than -3.3 V
SPACE (zero, on)
More positive than +3.0. V
More positive than +;3.3 V .
Fail Safe
Output = Binary 1
Output = Binary 1
Open Circuit Input Voltage
<
Slew Rate (at the driver)
'" 3D V/flS anywhere on the waveform
'" aD. V/flS anywhere on the waveform,
;. 4.0. V/flS between +3.0. V and -3.0. V
Loaded Output Voltage (at the driver)
S.DV'" Ivai'" 1S V for loads between
3.0. kn and 7.0. kn
Ivai ;.
12.0.1 V
Not Specified
-
Figure 2. TYpical Output versus Supply Voltage
5.0
VOH(lopt -20 ~A)
~4.0
w
~
t:.i 3.0
§i!
r--
VOH(lout - -3.2 rnA)
I
MC1~C89AB
-
MC14C89B
TA = 25°C
~4.0
VOH(lout=
-ko ~)
.2 rnA)
~ 3.0
MC14C89AB
MC14C89B
Vee=5V
>
~
5 2.0
·0
6
$>
> 1.0
7-52
VOH(lout =
~
5
4.5
Figure 3. Typical Output Voltage versus Temperature
5.0
w
5o 2.0
o
3.7 V for a load of 3.0. kn
1.0
Vodlout = 3.2 rnA)
Vodlout = 3.2 rnA)
4.7
4.9
5.1
VCC, SUPPLY VOLTAGE (V)
5.3
5.5
0.
-40.
-7.5
25
57.5
TA, AMBIENT TEMPERATURE (OC)
85
MOTOROLA ANALOG IC DEVICE DATA
MC14C89B, AB
Figure 4. Typical Short Circuit Current
versus Temperature
Figure 5. Typical Threshold Voltage
versus Temperature
15
I
2.0
:g
10
!z
~
5.0
!:::
0
a:
=>
o
~
Nbrmally Low OutpJt Shorted to VCC
~
Sl
':J
MC14C89AB
MC14C89B
VCC=5.5V
~
Cl
ffi~ 1.2
.
en -10
-15
-40
MC14C89AB
4.5 V < VCC < 5.5V
1.6
5 1.4
C3 -50
~
VIH
1.8
w
f-
~
~ 1.0
Norma Iy High Output Shorted to Ground
-7.5
25
57.5
TA, AMBIENTTEMPERATURE (0C)
VIL
0.8
85
-40
-7.5
25
57.5
TA, AMBIENT TEMPERATURE (0C)
Figure 6. Typical Threshold Voltage
versus Temperature
5.0
2.0
MC14C89B
4.5V < VCC < 5.5V
:g
w
~
;:u 4.0
;5 1.6
;5
~1.8
C!l
C!l
~
~
§1.4
gfa
VIH
:x:
fa
a:
~
~ 1.2
f-
~
f-
~
~ 1.0
2.0
Figure 7. Typical Effect of Response
Control Pin Bias
\ \
\
\
-7.5
25
57.5
TA, AMBIENTTEMPERATURE (OC)
:
+ RRC
~ Vbat
""I'----.
~!.:'.bat=-3.0V - -
NominalVIL
o
o
85
~
I\.VIL@Vbat=-10V
1.0
~
VIL
0.8
-40
3.0
85
-
4.5 V < VpC < 5.5 V
10kQ
20kQ
30kQ
40kQ
SOkQ
BIAS RESISTANCE (RRC)
Figure 8. Typical Noise Pulse Rejection
S.O
~
MC14C89AB
MC14C89B
Pulse Rate = 300 kHz
RC Pin Open
4.S
w
Cl
=> 4.0
!:::
...J
a.
:::;
« 3.S
w
~
=>
a. 3.0
\
.E
w
2.5
Noise p,ulse Reje~iOn
"-J.
2.0
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
PW, INPUT PULSE WIDTH (llS)
MOTOROLA ANALOG IC DEVICE DATA
7-53
•
MC14C89B, AB
APPLICATIONS INFORMATION
Description
The MC14C89AB and MC14C89B are designed to be
direct replacements for the MC1489A and MC1489. Both
devices meet all EIA-232 specifications and also the faster
EIA-562 and CCITT V.28 specifications. Noise pulse
rejection circuitry eliminates the need for most response
control filter capacitors but does not exclude the possibility as
filtering is still possible at the Response Control (RC) pins.
Also, the Response Control pins allow for a user defined
selection of the threshold voltages. The MC14C89AB and
MC14C89B are manufactured with a bipolar technology
using low power techniques and consume at most 700 JAA,
plus load currents with a +5.0 V supply.
MC14C89B or 0.95 V for the MC14C89AB). Figure 7 plots
equation (1) for two values of Vbat and a range of RRC.
If an RC pin Is to be used for low pass filtering, the
capacitor chosen can be calculated by the equation,
C
""
RC
1
2.02 kQ 211: f _ 3dB
(2)
where L3dB represents the desired -3 dB role-off frequency
of the low pass filter.
Figure 9. Application to Adjust Thresholds
Input Pin
Outputs
The output low or high voltage depends on the state of the
inputs, the load current, the bias of the Response Control
pins, arid the supply voltage. Table 1 applies to each receiver,
regardless of how many other receivers within the package
are supplying load current.
Table 1. Function Table
Receivers
Input'
11
Output'
H
L
L
H
"The asterisk denotes A, S, C, or D.
Receiver Inputs and Response Control
The receiver inputs determine the state of the outputs in
accordance with Table 1. The nominal VIL and VIH
thresholds are 0.95 V and 1.90 V respectively for the
MC14C89AB. For the MC14C89B, the nominal VIL and VIH
thresholds are 0.95 and 1.30, respectively. The inputs are
able to withstand ±3O V referenced to ground. Should the
input voltage exceed ground by more than ± 30 V, excessive
currents will flow at the input pin. Open input pins will
generate a logic high output, but good design practices
dictate that inputs should never be left open.
The Response Control (RC) pins are coupled to the inputs
through a resistor string. The RC pins provide for adjustment
of the threshold voltages of the IC while preserving the
amount of hysteresis. Figure 10 shows a typical application
to adjust the threshold voltages. The RC pins also provide
access to an internal resistor string which permits low pass
filtering of the input signal within the IC. Like the input pins,
the RC pins should not be taken above or below ground by
more than ±30 V or excessive currents will flow at these pins.
The dependence of the low level threshold voltage (VIU upon
RRC and Vbat can be described by the following equation:
V" - {VO.09
5.32 kQ
[
~ Vbat [RRC (1':+°2.02
+ 6.67
kQ
n
(11
x 106 Q2]
RRC
505 Q
VIH can be found by calculating for VIL using equation (1)
then adding the hysteresis for each device (0.35 for the
7-54
Another feature of the MC14C89AB and MC14C89B is
input noise rejection. The inputs have the ability to ignore
pulses which exceed the VIH and VII:. thresholds but are less
than 1.0 J.ts in duration. As the duration of the pulse exceeds
1.0 J.tS, the noise pulse may still be ignored depending on its
amplitude. Figure 8 is a graph showing typical input noise
rejection as a function of pulse amplitude and pulse duration.
Figure 8 reflects data taken for an input with an unconnected
RC pin and applied to the MC14C89AB and MC14C89B.
Operating Temperature Range
The ambient operating temperature range is listed as
-40°C to +85°C, and the devices are designed to meet the
EIA-232-E, EIA-562 and CCITT V.28 specifications over
this temperature range. The timing characteristics are
guaranteed to meet the specifications at +25°C. The
maximum ambient operating temperature is listed as +85°C.
However, a lower ambient may be required depending on
system use (Le., specifically how many receivers within a
package are used), and at what current levels they are
operating. The maximum power which may be diSSipated
within the package is determined by:
Po
-
(max) -
TJ(max) - TA
RSJA
where: RSJA = thermal resistance (typ., 100°CIW for the
OIP and 125°CIW for the SOIC packages);
TJ(max) = maximum operating junction temperature
(150°C); and
TA =ambient temperature.
Po = {[(VCC- VOH) X IIOHI] or
[(YOU X IIOL I ]}each receiver + (VCC X ICC)
where: VCC = positive supply voltage;
VOH, VOL = measured or estimated from Figure 2
and 3;
ICC =measured quiescent supply current.
As indicated, the first term (in brackets) must be calculated
and summed for each of the four receivers, while the last
term is common to the entire package.
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC26S10
Quad Open-Collector
Bus Transceiver
This quad transceiver is designed to mate Schottky TTL or NMOS logic to
a low impedance bus. The Enable and Driver inputs are PNP buffered to
ensure low input loading. The Driver (Bus) output is open~ollector and can
sink up to 100 mA at 0.8 V, thus the bus can drive impedances as low as
100 Q. The receiver output is active pull-up and can drive ten Schottky TTL
loads.
An active-low Enable controls all four drivers allowing the outputs of
different device drivers to be connected together for party-line operation.
The line can be terminated at both ends and still give considerable noise
margin at the receiver. Typical receiver threshold is 2.0 V.
Advanced Schottky processing is utilized to assure fast propagation delay
times. Two ground pins are provided to improve ground current handling and
allow close decoupling between VCC and ground at the package. Both
ground pins should be tied to the ground bus external to the package.
• Driver Can Sink 100 mA at 0.8 V (Maximum)
• PNP Inputs for Low-Logic Loading
• Typical Driver Delay =10 ns
• Typical Receiver Delay =10 ns
• Schottky Processing for High Speed
QUAD OPEN-COLLECTOR
BUS TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
E#
• Inverting Driver
PIN CONNECTIONS
Device
MC26S10P
MC26S10D
Gnd
Sus A
Enable
100
5.0 V
100 100 100
Receiver
Output A
Driver
Input A
Driver
InputS
Receiver
OutputB
Enable
14 Receiver
outpule
13 Driver
Inpule
EnableE
Driver
11 InpulD
10 Receiver
OutputD
BusB
Driver
Inputs
Driver
Inputs
MC26S10
MC26S10
Receiver
Outputs
Receiver
Oulputs
Driver
Inputs
TRUTH TABLE
Driver
Inputs
MC26S10
MC26S10
Receiver
Outputs
Enable
9 BusD
Gnd
Bus
Receiver
Output
l
l
H
l
H
X
H
l
Y
l
H
Y
l =
H=
X=
y=
Receiver
Outputs
100 100 100 100
S.OV
Enable
Driver
Input
Enable
low logic State
High logic State
Irrelevant
Assumes condition controlled
by other elements on the bus
7-55
MOTOROLA ANALOG IC DEVICE DATA
,
MC26S10
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltage
Input Voltage
Input Current
Symbol
Value
VCC
-0.5 to +7.0
Unit
Vdc
VI
-0.5 to +5.5
Ydc
mA
II
-3.0 to +5.0
Vo (Hi-z)
-0.5 to VCC
V
Output Current - Bus
10(B)
200
mA
Output Current - Receiver
10(R)
30
mA
TA
oto +70
Storage Temperature
Tstg
-65 to +150
Junction Temperature
TJ
150
'c
'c
'c
Output Vo~age - High Impedance State
Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS (Unless otherwise noted VCC = 4.75 to 5.25 V and TA = 0
VCC = 5.0 V and TA = 25'C.)
Characteristic
II
+70'C. Typical values measured at
Symbol
Max
Unit
Input Voltage - Low Logic State (Driver and Enable Inputs)
VIL
0.8
V
Input voltage - High Logic State (Driver and Enable Inputs)
VIH
Input Clamp Voltage (Driver and Enable Inputs)
(1IK=-18 mAl
VIK
-1.2
V
V
rnA
Input Current - Low Logic State (VIL = 0.4 V)
(Enable Input)
(Driver Inputs)
-0.36
-0.54
Input Current - High Logic State (VIH = 2.7 V)
(Enable Input)
(Driver Inputs)
20
30
ItA
Input Current - Maximum Voltage (VIH1 = 5.5 V)
(Enable or Driver Inputs)
100
Driver Output Voltage - Low Logic State
(IOL=40mA)
(lOL=70mA)
(IOL = 100 mAl
Driver (Bus) Leakage Current
(VOH=4.5V)
(VOL = 0.8 V)
V
0.33
0.42
0.51
0.5
0.7
0.8
IIA
10(0)
100
-50
100
ItA
1.75
V
0.5
V
-60
mA
45
70
mA
Min
Typ
Max
Unit
-
10
10
15
15
ns
-
14
13
18
18
ns
Driver (Bus) Leakage Curr
Receiver Input High Threshold
2.25
Receiver Input Low Threshold (VIH E) = 2.4 V)
2.0
2.0
Receiver Output Voltage - Low Logic State (IOL = 20 mAl
Receiver Output Voltage - High Logic State (IOH = -1.0 mAl
2.7
Receiver Output Short-Circuit Current (Note.1)
-18
Power Supply Current - Output Low State (VIL(E) = 0 V)
ItA
ICC
V
3.4
V
NOTE: 1. One output shorted at a time. Duration not to exceed 1.0 second.
SWITCHING CHARACTERISTICS (VCC = 5.0 V, TA = 25'C, unless otherwise noted.)
Characteristic
Propagation Delay Time Driver Input to Output
Propagation Delay Time Enable Input to Output
Symbol
tPLH(D)
tPHL(D)
tPLH(g)
tPHL(E)
-
Propagation Delay Time Bus to Receiver Output
tPLH(R)
tPHL(R)
-
-
10
10
15
15
ns
Rise and Fall Time of Driver Output
ITLH(D)
ITHL(D)
4.0
2.0
10
4.0
-
ns
7-56
MOTOROLA ANALOG IC DEVICE DATA
MC26S10
SWITCHING WAVEFORMS AND CIRCUITS
Figure 1. Data Input to Bus Output (Driver)
Vee
To Scope
(Input)
3.0V----"""""
Oliver
Input
50
VOH------+---~~~----~~
To Scope
(Output)
50 pF
(Inctudes
probe
and jig
~_ _ _ _ _-' capacitance)
Driver
Output
VOL-----~~
Vee
II
3.0V
50
Enable
tnput
OV
To Scope
(Output)
VOH
50pF
(Includes
probe
and jig
capacitance)
Oliver
Output
VOL
t
"i Figure 3. Bus Input to Receiver Output
~,,! ~
Vee
To Scope
(Output) 1N916
VOH-----r----'
Driver
Output
(Input) VOL
1.5V
VOH ---------'"
Receiver
Output
VOL-------------'----------J
MOTOROLA ANALOG IC DEVICE DATA
Vee
or
280
Equivalent
50
:!-= 15 pF (Total)
To
Scope
(Input..,)I---+--.
<:7k:;'
=0.8 V)
Receiver Output Short Circuit Current (VI(s/R) =0.8 V, \fIIt;~ 'l;;'~'.O V)"
..... (V~~ii~r'
.·,~"F\
Dnver Input Voltage - Low Logic State ( V I ( ' ,;",:"""
';,;"
-
,,":0:-:::;
i,~T
mA
2.5
-3.2
+0.04
-
mV
V
1.6
1.0
1.8
.7
-
-
V
-
-
0.5
V
SIR)
-15
rnA
2.0
-
-75
VIH(D)
-
V
VIL(D)
-
-
0.8
• 'oX!~:~~;\;'-"
=
Driver Input Current - Data Pins (VI(S/R)
(0.5 .. VI(D) .. 2.7 V)
,,' "
(VI(D) 5.5 V ) " , ,
~( -
3.7
-1.5
~>,>
=
"""" ,'.... _ - H." _
"';,;", '",
"(,~!~:, 400,;' :,~
,,
,"
Receiver Output Voltage - Low Logic State
(VI(s/R) 0.8 V, 10L(R) 16 mA, V(BUS)
=
~.:.
(R)
Receiver Output Voltage - High Logic State
(VI(s/R) 0.8 V, 10H(R) -800~, V(BUS)
=
ri
':l~>'~
I(BUS)
=
Receiver Input Hysteresis (VI(S/R)
Typ
V
=0.8 V)
Bus Current
(5.0 V .. V(BUS~ .. 5.5 V)
(V(BUS) 0.5 V
(VCC 0 V, 0 V .. V(BUS) .. 2.75 V)
=
Symbol
V
p.A
11(0)
IIB(D)
-200
-
-
40
200
II(SIR)
IIB(s/R)
-100
-
20
100
II(E)
IIB(E)
-200
-
-
20
100
VIC(D)
-
-
-1.5
V
VOH(D)
2.5
-
-
V
Driver Output Voltage - Low Logic State (Note 1)
(VI(S/R) 2.0 V, 10L(D) 48 mAl
VOL(D)
-
-
0.5
V
Output Short Circuit Current
(VI(S/R) 2.0 V, VIH(D) 2.0 V, VIH(E)
10S(D)
-30
-
-120
mA
-
63
106
85
125
,,'
=
!';"'i'",
Input Current - Send/Receive
(0.5 .. VI(S/R) .. 2.7 V) ,':;,:::~;/>
(VI(S/R) 5.5 V ) , " " x i ( ' ,
=
,,:;,;:~~~,)';'
=2.0 V, IIC(D) =-18 rnA)
Driver Output Voltage - High Logic State
(VI(s/R) 2.0 V, VIH(D) 2.0 V, VIH(E)
=
=
=
-
p.A
=
Driver Input Clamp Voltage (VI(s/R)
-
~
.. ,
;"..'
Input Current - Enable
(0.5 .. VI(E) .. 2.7 V)
(VI (E) 5.5 V)
' ',',
=
=2.0 V, 10H =- 5.2 rnA)
=
=
=2.0 V)
Power Supply Current
(Listening Mode - All Receivers On)
(Talking Mode - All Drivers On)
MOTOROLA ANALOG IC DEVICE DATA
ICCL
ICCH
-
-
mA
7-59
MC3448A
SWITCHING CHARACTERISTICS (Vee = 5.0 V, TA = 25°C, unless otherwise noted)
Propagation Delay of Driver
(Output Low to High)
(Output High to Low)
tPLH(D)
tPHL(D)
Propagation Delay of Receiver
(Output Low to High)
(Output High 10 Low)
tPLH(R)
IPHL(R)
ns
-
-
15
17
-
-
25
23
-
ns
NOTE: 1. A modilication of the IEEE 488-1978 Bus Standard changes VOL(D) Irom 0.4 to 0.5 V maximum to permit the use of Schottky technology.
SWITCHING CHARACTERISTICS (continued)
Characteristic
Propagation Delay Time - Send/Receive to Data
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low
(Vee =5.0 V, TA =25°C, unless otherwise noted)
Symbol
Min
Typ
Max
ns
tPHZ(R)
tpZH(R)
tPLZ(R)
tPZL(R)
30
30
30
30
Propagation Delay Time - Send/Receive to Bus
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low
30
30
30
30
Turn--On Time - Enable to Bus
Pull-Up Enable to Open Collector
Open Collector to Pull-Up Enable
30
20
7-60
Unit
ns
ns
MOTOROLA ANALOG IC DEVICE DATA
MC3448A
PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
Figure 1. Bus Input to Data Output (Receiver)
Input
Ou1p~"';'
~
t>.-~~t
3.0 V
To Scope
(Input)
Send!
To Scope
(Output)
Roc Bus
Dnverlnput
or Enable "
2.3 V
3B.3
.(0::.
.. '
;""/
1.5 V
1"'2.0'
f=1.0MHz
tn.H=trHL" 5.0 ns (10%10 90%)
Duty Cycle =50%
1.:::,0\." .
Pull-Up Enable
". :::,/
,;~.~.'
':':;i tpLI'.I.ID,. ):. ,~.:;. ·~.;;jtv_<______._~;:
\~-"
O.BV~VOL
,<.~;'<:',.~ "4'~l
.. Includes Jig and
Probe Capacitance
k .
30V
~"""'15V
,~ .,
Sendlftec
Probe:~acitance
.. )
":"
,(: ~>.:~:~fr
&OV
_---3.0 V
Input
'--------·I----OV
Output
High 10 Open
Output
Low to Open
Pulse
Generator
I--;---""-ov
51
CL = 15 pF (Includes Jig and
Probe Capacitance
MOTOROLA ANALOG IC DEVICE DATA
f= 1.0 MHz
tTLH = tTHL " 5.0 ns (10% 10 90%)
DUty Cycle =50%
7--61
a
MC3448A
Figure 4. SendIReceive Input to Data Output (Receiver)
,-------"\.----3.ov
Inplll
5.0V
---OV
To Scope
(0uIput)
280
I~~----~-I-~~-~--OV
CL =15 pF (Includes Jig and
Probe capacitance
51
Figure 5. Enable Input to Bus Output (
To5cope
(0uIput)
3.0 V
_----~.--- 3.0V
•
caia
Bus
Sen0
'.'.
::>
J!l
!
-10
-12
-14
-4.0
J
I
---
Al&a f ConIormsIo
"aragillJ)h"3-5.3 of
IEEE SIandMI .
-
481H978 .
IIICcj5:0V
-2.0
I
o
2.0
VBUS. BUS VOLTAGE (V)
J
4.0
~
-
6.0
MOTOROLA ANALOG IC DEVICE DATA
MC3448A
Figure 8. Simple System Configuration
5.0 V
··•
·
Ti!!2
EOI
Ern
SAC
SRll
07
AIW
ANI
·
AS2
.f
REN
liEN
IFC
iFC
0.18
OB7
ASil
i
·
··
00
0B0
Ti!!l
.s~
~
··
··•
•
MC6802
OR
MC6800
MPU
I
A15
I
fRO
I
~
A1'N
{
NOAC
..
!!!
I
I
OAV
DlOl
0103
1-1---"''---+-1I---I
M
Dl05
1-1-----+-1I---I~
0106
I-r------t-t----1
ili5
1-1-----+-11---1
ili5
NOTE 1: AHhough the MC3448A transceivers
are non-inverting, the 488-1978 bus callouts
appear inverted wHh respect to the MC68488
pin designations. This is because the
488-1978 Standard is defined for negative
logic, while all M6800 MPU components
make use of posHive logic formal.
I-r------t-t----1~
r---L__
Trig ....
IEEE 488-1975 BUS
MOTOROLA ANALOG IC DEVICE DATA
...J
--r_ _
NOTE 2: Unless proper considerations are
provided, it is recommended that the pull-up
enable pins on the MC3448As be grounded,
selecting the open--collector mode.
7-63
®
MOTOROLA
MC3450
Quad MTTL Compatible
Line Receivers
The MC3450 features four MC751 07 type active pull up line receivers with
the addition of a common three-state strobe input. When the strobe input is
at a logic zero, each receiver outputstate is determined by the differential
voltage across its respective inputs. With the strobe high, the receiver
outputs are in the high impedance state.
The strobe input on both devices is buffered to present a strobe loading
factor of only one for all four receivers and inverted to provide best
compatability with standard decoder devices.
QUAD LINE RECEIVERS
WITH COMMON THREE-STATE
STROBE INPUT
SEMICONDUCTOR
TECHNICAL DATA
• Receiver Performance Identical to the Popular
MC751 07/MC751 08 Series
• Four Independent Receivers with Common Strobe Input
• Implied "AND" Capability with Open Collector Outputs
• Useful as a Quad 1103 type Memory Sense Amplifier
TRUTH TABLE
•
Output
Input
V,O ;;,
+25mV
-25 mV .;
V,O ';+25 mV
=
=
=
=
MC3450
L
H
H
L
z
PSUFFIX
PLASTIC PACKAGE
CASE 648
H
L
H
V,O .;
-25mV
L
H
Z
I
Strobe
Low Logic State
High Logic State
Third (High Impedance)
Indeterminate State
PIN CONNECTIONS
Figure 1. A Typical M
' Sensing Application for a
4 k Word by 4-Bit Memory
ngement Employing
1103 Type Memory Devices
Data
Bit #4
Data
Bi1#3
200
Data Bit 0
#2
Data
Brt#2
200
DataBit
ORDERING INFORMATION
ut#1
18k
5,OV ........,.-~-------~-v--
200
Only four MC3450 devices are required for
a 4 k word by 16-bit memory system.
7-64
Strobe_-o-ti
Data
Bi1#1
Device
Operating
Temperature Range
Package
MC3450P
TA = 0 to +70°C
Plastic OIP
MOTOROLA ANALOG IC DEVICE DATA
MC3450
MAXIMUM RATINGS (TA =0 to +70o e, unless otherwise noted.)
Rating
Power Supply Voltages
Symbol
Value
Unit
Vdc
VCC, VEE
±7.0
Differential Mode Input Signal Voltage Range
VI DR
±6.0
Vdc
Common Mode Input Vottage Range
VICR
±S.O
Vdc
Strobe Input Vottage
VI(S}
5.5
Vdc
1000
6.6
1000
6.6
mW
mW/"C
mW
mW/"C
Power Dissipation (Package Limitation)
Ceramic Dualln-Line Package
Derate above TA = 25°C
Plastic Dual In-Line Package
Derate above TA = 25°C
Po
Operating Temperature Range
TA
Oto+70
°C
Storage Temperature Range
Tstc
-65 to +150
°C
RECOMMENDED OPERATING CONDITIONS (TA =0 to +70oe, unless otherwise noted.)
Characteristic
Power Supply Vottages
Output Load Current
Symbol
Min
Max
Unit
VCC
VEE
+4.75
-4.75
+5.25
-5.25
Vdc
10L
16
mA
Differential Mode Input Vottage Range
VIDR
+5.0
Vdc
Common Mode Input Voltage Range
VICR
+3.0
Vdc
VIR
+3.0
Vdc
Input Voltage Range (any Input to Ground)
ELECTRICAL CHARACTERISTICS (Vee = +5.0 Vdc, VEE = -5.0 Vdc,
Max
Unit
High Level Input Current to Receiver Input
75
J.LA
Low Level Input Current to Receiver Input
-10
J.LA
High Level Input Current to Strobe Input
VIH(S} = 2.4 V
VIH S =5.25 V
40
1.0
mA
-1.6
mA
Characteristic
Low Level Input Current to Strobe Input
VILS =0.4V
High Level Output Voltage
Vdc
2.4
High Level Output Leakage Current
ICEX
Low Level Output Voltage
VOL
Short-Circuit Output Current
Output Disable Leakage Curre
lOS
J.LA
J.LA
-18
0.5
Vdc
-70
mA
f/'-=_____I-_.-...::lo:::ff_ _+ ____-I-____f-__4_0_-If---''--_--I
J.LA
High Logic Level Supply Current ,fro
ICCH
45
60
mA
High Logic Level Supply Current from VEE
IEEH
-17
-30
mA
Max
Unit
25
ns
25
ns
21
ns
18
ns
27
ns
29
ns
SWITCHING CHARACTERISTICS (Vee =+5.0 Vdc, VEE =-5.0 Vdc, TA = +25°e, unless otherwise noted.)
MC3450
Min
Typ
-
tPHL(S}
-
tPLH(S}
-
-
Characteristic
Symbol
High to Low Logic Level Propagation Delay
11me (Differential Inputs}
tPHL(D}
Low to High Logic Level Propagation Delay
11me (Differential Inputs}
tPLH(D}
Open State to High Logic Level Propagation
Delay 11me (Strobe)
tpZH(S}
High Logic Level to Open State Propagation
Delay 11me (Strobe)
tPHZ(S}
Open State to Low Logic Level Propagation
Delay 11me (Strobe)
tpZL(S}
Low Logic Level to Open State Propagation
Delay 11me (Strobe)
tPLZ(S}
High Logic to Low Logic Level Propagation
Delay 11me (Strobe)
Low Logic to High Logic Level Propagation
Delay 11me (Strobe)
MOTOROLA ANALOG IC DEVICE DATA
-
-
-
ns
ns
7-65
•
MC3450
Figure 2. Circuit Schematic
(1/4 Circuit Shown)
V~o---~--~----~----~------~--------~----~------~~
850
190
850
4.0k
1.6k
OUTPUT
·~r
GND
STROBE
4.0k
4.0k
VEE
Figure 3. ICEX. VOH. and VOL
II
V1
V2
----;:.0-1
---....:.;-o-t
0.8 v -+---;:.o-t
S.OV
V4 -+-I....-iro-l
(MC3452)
5.26V
-
MC34&O
va
vs_....._ .......o-I
--0-0
v.
S,OV
GND
GND
-S.QV
3.0 V
2.975 V
GND
S.OV
-2.976 V
-3.0V
-3.QV
GND
11
Q,4mA
-16mA
Channel A shown under test. Other channels are tested similarly.
ICEX
11.
(MC3450)
Figure 4. ICCH and IEEH
Figure 5. IIH(S) and IIL(S)
3.0V _ . - - - - - - - - - ,
mo--45.26V
5.25 V
~-~43.0V
ma-t-+4-5.25V
-5.26 V
7-66
MOTOROLA ANALOG IC DEVICE DATA
MC3450
TEST CIRCUITS (continued)
Figure 6. lOS
Figure 7. IIH
B>---. 5.25 V
8>---. 5.25 V
25mV_--+c8
8>+....... 3.0V
0.8 v -+--+C>:-l
8 > + + . -5.25 V
lOS
8 > + + . -5.25 V
Channel A shown under test, other channels are tested similarly.
Only one output shorted at a time.
Figure 8. IlL
VI-2.0V
Vl-f-~~:-t
"""1)--.... 5.25 V
B>---. 5.25 V
3.0 v-f-t--<>i-I
II
8>++.-5.25 v
Output of Channel A shown under test, other outputs are
tested similarly for VI 0.4 V and 2.4 V.
=
eceiver Propagation Delay tPLH(D) and tPHL(D)
5.0 V
l00mV ....- -...--o,;-I
Ein
200mv~--50%
OV
~~(~_~____tPHL(D)
Eo
1.5 V
VOL
EO
Output of Channel B shown under test, other channels are tested similarly.
81 at "A" for MC3452
81 at "B" for MC3450
CL = 15 pF total for MC3452
CL = 50 pF total for MC3450
MOTOROLA ANALOG IC DEVICE DATA
Eln waveform characteristics:
trLH and trHL .. IOns measured 10% to 90%
PRR= 1.0 MHz
Duly Cycle = 500 ns
7-67
MC3450
TEST CIRCUITS (continued)
Figure 11. Strobe Propagation Delay Times tPLZ(S) tPZL(S) tPHZ(S) and tPZH(S)
5.0V
Vl_--_~8
VI
V2
51
52
CL
IpLZ(S)
100mV
GND
Closed
Closed
ISpF
SOpF
IpZL(S)
100mV
GND
Closed
Open
IpHZ(S)
GND
l00mV
Closed
Closed
ISpF
IpZH(S)
GND
l00mV
Open
Closed
50pF
Output of Channel B shown under test,
other channels are tested similarly.
Ein
II
3.::---~
--:::J
tPLZ(S) {
I-- tPLZ(S)
ipHZ(S)
. - _ - - -1.5V
EO
VOH-O.5V
......_ _ _ *1.5V
Eln
tPZH(S) {
3'OV~
50%
,:
Eo
-----f.1.5 V
-OV
7-68
MOTOROLA ANALOG IC DEVICE DATA
MC3450
APPLICATIONS INFORMATION
Figure 12. Bidirectional Data Transmission
5.0V
180
~r __t-~~~~lt1-~
380
Strobe
114 (MC3450)
The thre~tate capability of lIle MC3450 permits
bidirectional data transmission as Illustrated.
Figure 13. Single-Ended Unl-Bus™ Line Receiver
Application for Minicomputer
IN914
orequiv
•
3.0k
+5.0V
S1robe
180
OataBu8
5.0
390
MC3450
180
OataBu8
390
Data
Output
Data
Lines
5.0V
f80
Addre.ssBu....- - , , -.....
5.0 V
390
-+-o.,
180
-+_--+-o-tF-l/'
Control Bu....
~H--o-.. Control
I
I
I
390
t
Strobe ....-----+-c~IH,::>O---..... : - Trademark of Olg"al
_____ .J
Equipment Corp.
L._~
To AddllionaJ
Receivers
The MC3450 can be used for slngle-ended as well as differential line
receiving. For slngle-ended line receiver applicatIons, such as are
encountered in min)computers, the configuration shown In Figure 15 can
be used. The voltage source, which generates Vref. should be designed
80thatllle Vr.fvoltagels hallway between VOH(mln)and VOL(max). The
maximum Input overdrive required to guarantee a gIven logic state Is
extremely small, 25 mV maximum. This low-lnput overdrive enhances
differential noise immunity. Also the high-Input Impedance of the line
receiver permits many receivers to be placed on a single line with
minimum load effects.
MOTOROLA ANALOG IC DEVICE DATA
S1robe
01
02
as
Q4
AI
A2
'~----'
7-69
MC3450
APPLICATIONS INFORMATION (continued)
Figure 15. Party-Line Data Transmission System
with Multiplex Decoding
~robe
Data
Inputs
stro~
MC3453
Strobe ' " - -
'"--
-L
~
~
Data
Inputs
< -
MC3453
-
~r
~~ ~
-
II
~
Data
Inputs
~
MC3453
-r
Strobe
-
Data
Inputs
Data
Outputs
MC3450
Z
~
~
"",4>
'1 f. .. ~.~
•• ;...f
~
t;
~obe
r-=
Data
Outputs
MC3450
O·
~
Y
MC7404
04
E
7-70
f-of-of-o-
112
MC4007
Data
Outputs
MC3450
Str~
r-~
01
213
Data
Outputs
~
~
'4
MC345~
~~obe
I
X
X
~
r---'LASTIC PACKAGE
"
CASE648
..>/
r"
'i-"
•
PIN CONNECTIONS
Figure 1. Party-Line Data Transmission Sy
Multiplex Decoding
Vee
InputA 1
InputB
Y{ 2
OUtputA
z
Da'
Inputs
Z{ 4
-.t--.t
e---I--o-I
OutputC
y
InputD
Da.
,,,,", e---I+--o-I
TRUTH TABLE
(positive logic)
"";+--o-I
Inpu. e---I+--o-I
00.
Da'
,,,,,IB
....,/++-0-1
Output
Current
Logic
Input
Inhibit
Input
Z
y'
H
H
On
Off
L
H
Off
On
H
L
L
Off
Off
Off
Off
L
L z Low Logic Level
H z High Logic Level
ORDERING INFORMATION
Device
At
"
MOTOROLA ANALOG IC DEVICE DATA
At
"
MC3453P
Operating
Temperature Range
TA
=0 to +70°C
Package
Plastic DIP
7-71
MC3453
MAXIMUM RATINGS (TA = 0 to +70 0 e, unless otherwise noted.)
Symbol
Value
Unit
Vec
Vee
Vin
+7.0
-7.0
5.5
V
V
Common-Mode Output Voltage Range
VOCR
-5.0 to +12
V
Power Dissipation (Package Limitation)
Plastic Dual In-Line Package
Derate above TA 25°C
Po
1000
6.6
mW
mWfC
Power Supply Voltage
Logic and Inhibitor Input Voltages
=
Operating Ambient Temperature Range
TA
Oto+70
°C
Storage Temperature Range
Plastic and Ceramic Dual In-Line Packages
Tstg
-65 to +150
°C
RECOMMENDED QPI5RATING CONDITIONS (See Notes 1 and 2.)
Characteristic
Power Supply Voltages
Symbol
VCC
Vee
Common-Mode Output Voltage Range
Positive
Negative
II
Max
Min
+4.75
-4.75
Unit
V
+5.25
-5.25
V
VOeR
0
+10
-3.0
NOTES: 1. These voltage values are in respect to the ground terminal.
2. When not using all four channels, unused outputs muat be groUnded.
DEFINITIONS OF INPUT LOGIC LEVELS·
Characteristic
High-Level Input Voltage (at any Input)
Low-Levellnput Voltage (at any input)
Min
Max
5.5
0.8
2.0
0
Unit
V
V
• The algebraic convention, where the most positlv
ooe, unless otherwise noted.)
ELECTRICAL CHARACTE
Symbol
High-Level Input Current (L
(VCC Max, Vee Max, V IH
(VCC
=
=
.4
=Max, Vee =Max, VIHL =Vec M
IIH
=
=
IlL
=
=
=
=
=
=
=
=
=
=
=
=
=
L
Low-Level Input Current (Logic Inputs)
(VCC Max, Vee Max, VIL 0.4 V)
L
High-Level Input Current (Inhibit Input)
(Vee Max, Vee Max, VIH 2.4 V)
I
(Vec Max, Vee Max, VIH Vee Max)
I
Low-Level Input Current (Inhibit Input)
(VCC Max, Vee Max, V IL 0.4 V)
I
Output Current ("ON" state)
(VCC Max, Vee Max)
(VCC Min, Vee Min)
=
Output Current ("OFF" state) (VCC
=Min, Vee =Min)
Supply Current from Vec (with driver enabled)
(V IL 0.4 V, V IH 2.0 V)
L
I
=
=
Min
Typ#
L
Max
Unit
40
j.lA
1.0
mA
-1.6
mA
40
j.lA
-1.6
mA
L
IIH ,
I
IlL
I
mA
10(on)
11
11
15
10(off)
5.0
100
j.lA
ICC(on)
35
50
rnA
6.5
#AII typical values are at Vee = 5,0 V, VEE = -5.0 V, TA = 25°e.
##For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions for the applicable device typs.
Ground unused Inputs and outputs.
7-72
MOTOROLA ANALOG IC DEVICE DATA
MC3453
ELECTRICAL CHARACTERISTICS (TA: 0 to +70°C unless otherwise noted)
Characteristic##
Supply Current from VEE (with driver enabled)
(V IL : 0.4 V, V IH : 2.0 V)
L
I
Supply Current from VCC (wHh driver inhibited)
(V IL : 0.4 V, V IL : 0.4 V)
L
I
Supply Current from VEE (with driver inhibited)
(VIL : 0.4 V, V IL : 0.4 V)
L
I
Symbol
Min
Typ#
Max
Unit
IEE(on)
-
65
90
rnA
ICC(off)
-
35
50
rnA
IEE(off)
-
25
40
rnA
#AII typical values are at Vee =5.0 V, VEE =-5.0 V, TA =25'e.
##For cond~lons shown as Min or Max, use the approprtate value specHied under recommended operating conditions for the applicable device type.
Ground unused inputs and outputs.
SWITCHING CHARACTERISTICS (VCC: 5.0 V, VEE: -5.0 V, TA: 25'C.)
Characteristic
Propagation Delay Time from Logic Input to
Output Y or Z (RL : 50 ohms, CL : 40 pF)
Propagation Delay time from Inhibit Input
to Output Y or Z (RL : 50 ohms, CL = 40 pF)
Symbol
MIl)
f,·.. ,~,.,.
.
.',
Typ
Max
Unit
9.0
9.0
17
17
ns
20
16
25
25
ns
•
MOTOROLA ANALOG IC DEVICE DATA
7-73
MC3453
Figure 2. Logic Input to Outputs Propagation
Delay Time Waveforms
.Figure 3. Inhibit Input to Outputs Propagation
Delay Time Wavefo.rms
Logic Input
3.0 V
Inhiblt
Input
OV
OV
3.0 V
50%
Output
y
OutputZ
OV
OV
50%
Output
Z
Figure 4. Logic Input to Output Propagation
Delay nme Test Circuit
II
Ein to Scope
VCC=5.0V
50.--....-->-1
Output
to
Z
Scope
50
=-5.0 V
1.0k
Channel A shown under test, the other
channels are tested similarly.
7-74
Channel A shown under test, the other
channels are tested similarly.
MOTOROLA ANALOG IC DEVICE DATA
MC3453
Figure 6. Circuit Schematic
(1/4 Circuit Shown)
Veeo----.--------~--~----_.~~----------+_--~
To Remainder
of auad
Single Driver
Oulputs
Logic O_.....=-.....:J. .J
Input
VEEo---------------------------~~--~~~--~
__
~~
To Remainder
of auad
------------------------------------~~~---~~---------- --
Vee
II
Inhibit o-_-#--=:j4.--J
Input
MOTOROLA ANALOG IC DEVICE DATA
7-75
®
MOTOROLA
MC3467
Triple Wideband Preamplifier
with Electronic Gain
Control IEGC)
The MC3467 provides three independent preamplifiers with individual
electronic gain control in a single 18-pin package. Each preamplifier has
differential inputs and outputs allowing operation in completely balanced
systems. The device is optimized for use in 9-track magnetic tape memory
systems where low noise and low distortion are paramount objectives.
The electronic gain control allows each amplifier's gain to be set
anywhere from essentially zero to a maximum of approximately 100 VN.
• Wide Bandwidth - 15 MHz (Typical)
• Individual Electronic Gain Control
• DifferentiallnputlOutput
TRIPLE MAGNETIC TAPE
ME
Y PREAMPLIFIER
II
PSUFFIX
PLASTIC PACKAGE
CASE 707
PIN CONNECTIONS
Simplified Application
High Performance 9-Track Open Reel
Tape System
VI(EGC)
NRZllcp
Select
Active
Differentiator
T
A
P
E
lSI
Formatter
MC8500
MC8S01
MC8S02
MC8S20
ORDERING INFORMATION
Device
MC3467P
7-76
Operating
TemperetureJ'!ange
TA
=0 to +70°C
Package
Plastic DIP
MOTOROLA ANALOG IC DEVICE DATA
MC3467
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltages
Positive Supply Voltage
Negative Supply Voltage
Symbol
Value
Unit
VCC
VEE
6.0
-9.0
VI(EGC)
-5.0toVCC
V
VID
±5.0
V
VIC
±5.0
V
tsc
10
s
°C
V
EGC Voltages (Pins 1, 6 and 13)
Input Differential Voltage
Input Common-Mode Voltage
Amplifier Output Short Circuij
Duration (to Ground)
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature
TA
Oto+70
Tstg
-65to+15O
°C
TJ
+150
°C
'.!
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = -6.0 V, f =100 kHz, TA = 0 to-, +7(IPd;>Ilni~ss
otherwise noted.)
.'
~
Characteristic
Symbol
Power Supply Voltage Range
Positive Supply Voltage
Negative Supply Voltage
Operating EGC Voltage
VCCR
VEER
v.:.,
:,,"y
./;L
Output Voltage Swing (Balanced) (Figure 1)
i·
:";'",:",.",
(ei = 200 mVpp)
...
c· ,,'"
Input Common-Mode Range
. ~. t.'-,
"
0'
•.
>.
Differential Output Offset Voltage
(TA= 25°C)
Common-Mode Output OffSllt.~e
(TA = 25°C)
..
Common-Mode Rejection Ratio (Figure 2),
=
VI(EGC) 0, VCM
(f = 100 kHz)
(f= 1.0 MHz)
-
0.5
2.0
VN
0.2
-
-
Vpp
VOR
6.0
B.O
-
Vpp
,.
AVO.
I',
...
"t:·
VID~'"
•••:C'"'-'
:.>
. P.r'u,
V
5.25
-7.0
VN
~,
Maximum Input Differential Voltage
(Balanced) (TA = 25°C)
Unit
120
,.";)
(VI(EGC) = VCC)
Max
VCC
>.
Differential Voltage Gain
·:',"'-6.0
~5.5,< •. ,
.~;",>.~ .:.:!
,.>i·~ . :·")"
"I',
"'.
./.,,;.';/~
,,'"
.{)
-
~.
=
TVP
100
VI(E:~
Differential Voltage Gain (Balanced)
(VI(EGC) 0, ei 25 mVpp) (See Figure 1)
=
..
<
100
lS0
VI, INPUT VOLTAGE (mVpp)
200
II 1111
-30
0.1
250
SO
SO
1 LI Ull
1
1.0
10
I, FREQUENCY (MHz)
Jill
100
Norrilllllli:llll!id Positive Power Supply
Power Supply Voltage
Figure 9. Normalized Voltage Gain
versus Ambient Temperature
~
~'OO
•
1.04 r - - , - - - , - - - , - - r - - , - - - , - - - , - - - ,
~
!1.02
z
~ 1.00
UJ
c:l
~
~
0.98
I
,' ' ",~:~~J:t~'96
>
< 0.96
o
4L.7-S-4...l..8--4.L8S-4..J..9--4..L..9S-..J.S.-0-S.L...0-S--l
S.1 -S.J...1-S --lS.L...
2 ---l
S2S
10
TA, AMBIENTTEMPERAT~11l:1' "
"",
:;.f(" j
VCC, POSITIVE POWER SUPPLY VOLTAGE (Vdc)
~~~.'~ ./fi. ~:';:~;::~~i('~
~e ~owe:-~~~y
Figure 12. Normalized Power Supply Currents
versus Ambient Temperature
Figure 11. Normalized
Current versus Negat~'~wer SuP.I>ly Voltage
I
G
:::;
'tL
l
;:>/" ~.;"
"'~'
1<,
1.02
1.041---t_-I-_-+-_;~~!~+:' ' ' :_'~;j- -.M.", . ,. '\i-,- , -,:'~>f-;_,i-+--+--l
"j,'
1.021--+--+-+--+--t--I---+--+----I1--I
0..
0..
1il til
_I
ffi~
____ -
....--~
./
3: :;;! 1.00 f---t--+-+---:;;;;¥=-I---+-+-+--t----t
~ ~
____ ~
VCc=S.OV
UJ 0
.....TA,= 2SoC
~~
n = IEE(T)
0.981--+--+-+--+--tlEE (2S°C)
:fl
_~
~
ffi
z
TeS\CircuittFigUre4
..tB
0.96
-5.0
I
I
I
-S.S
-6.0
-6.S
-7.0
VEE, NEGATIVE POWER SUPPLY VOLTAGE (Vdc)
MOTOROLA ANALOG IC DEVICE DATA
-7.S
./
V
0.99
/
0.98
o
/
,/'"'
VCc=s.O V
VEE =--M V
ICC (T)
lEE (T) n=---=--ICC (2S°C)
lEE (2S°C)
I
I FigureI 4
See
For Test Circuit
I
10
-
k--:'": ~
1-
I
20
30
40
50
60
TA, AMBIENT TEMPERATURE (0C)
70
80
7-79
MC3467
Figure 13. Differential Voltage Gain versus
Electronic Gain Control Voltage (VI(EGC»
Figure 14. Common-Mode Rejection Ratio
(CMRR) versus Frequency
~-100r---;-"-;rn~~'-'-T>"TIT---r-r.-nr~
Q
!;(
a:
5
~ -ao
lil
a:
VCC = 5.0 V
VEE = -a.0 V
TA=25°C
w
~
-ao
V
CMRR = 2010g - A
vO
V ICM
Av=100VN=40dB
~
I-_V-jIC:..cM
::,=,l-r-'0'"tV
-'!PP1tl+- Test Circuij = Figure 2 -I-I-++t+I-H
~
~O~--I-H-I-t+l~--+4-+-+++itt---I--+4-~~
8
a:
O~~~~~~~~~__~~~~
o
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VI(EGC}, ELECTRONIC GAIN CONTROL VOLTAGE (VOLTS)
::;
(,)
0.1
100
Figure 15. Phase Shift versus Frequency
•
~
ttl
ffi
o
t
:;:
en
eno. ~
~Or-~~-+~+H+-~~-++T~+-~~-r++~
~Or---r-~~rHtr--+-~++++~~~-+;-HH~
-120 1-~~-+-++I+I+--+-+-++-I+1H+--.,....+-t-++-H:
-160 r---r-H-I-t+lft---+-++-+++itt---I-~n-200
I--I-I'+-H-tttt--t-l-++++ttt--t-
-240
r-~-1-+~+H+-~--f-++++l-
5.0
03
04
Outputs
Inputs
01
EGC
Input
R1
02
VEE
7-80
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROI.A
MC3481
MC3485
Quad Single-Ended
Line Drivers
The MC3481 and MC3485 are quad single-ended line drivers specifically
designed to meet the IBM 360/370 I/O specification (GA22-6974-3).
Output levels are guaranteed over the full range of output load and fault
conditions. Compliance with the IBM requirements for fault protection,
flagging, and power up/power down protection for the bus make this an ideal
line driver for party line operations.
IBM 360/370
QUAD LINE DRIVERS
.
,
.:'.ICONDUCTOR
., 'TECHNICAL DATA
• Separate Enable and Fault Flags - MC3481
• Common Enable and Fault Flag - MC3485
• Power Up/Down Does Not Disturb Bus
• Schottky Circuitry for High-Speed - PNP Inputs
• Internal Bootstraps for Faster Rise limes
• Driver Output Current Foldback Protection
• MC3485 has LS Totem Pole Driver Output
PSUFFIX
•
PLASTIC PACKAGE
CASE 648
'.'t
.Vee
Driver Output A 1
Driver Output A 1
";;-,,=t'
Driver Output 0
Fault Flag A 2
14
Dnver Output A 2
15
taiJIfFI8gU
Enable AB 4
Driver OUlputD
14 Dnver OutputD
Enable ABCD 4
t----i>-t++-'
L...l-=::r-"'-__ II2 FaUIfl'Iag
(Open Colleclur)
Dnver Output B 6
Driver Output B 7
10
FaiiIfFI89C
9
Driver Output C
10 Driver Output C
Driver OUtput B 7
9
Driver Output C
Simplified Application
1/4 MC3481 or
1/4 MC3485
r-------,
I
I
I
Coaxial
r - - - ...,
cab~le
:
i
t
I
I
I
I
L ___ .J
ORDERING INFORMATION
Device
MC3481P
Operating
Temperature Range
Package
Plastic DIP
MC3485P
MOTOROLA ANALOG IC DEVICE DATA
7-81
MC3481 MC3485
MAXIMUM RATINGS (TA = 25°e, unless otherwise noted)
Rating
Power Supply VoHage
Input Voltage
Driver Output VoHage
Symbol
Value
Unit
Vee
+7.0
V
VI
10
V
V
Vo
5.5
Power Dissipation (Package Limitation)
Derate Above TA = 25°e
Po
1/ReJA
962
7.7
mW
mwoe
Operating Ambient Temperature Range
TA
Oto + 70
°e
Junction Temperature
TJ
+150
°e
Tstg
65 to + 150
°e
Storage Temperature Range
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
High Level Output eurrent'
Symbol
Max
Unit
Vee
Min
5.95
Vdc
10H
59.3
mA
Operating Ambient Temperature Range
•
+70
SWITCHING CHARACTERISTICS (See Note 1. Unless otherwise noted, th
range. 1/0 Driver characteristics are guaranteed for Vee = 5.0 V ± 10 % and
Vee = 5.25 to 5.95 V. Typical values measured at TA = 25 °e and Vee
over recommended temperature
Istics are guaranteed for
, Figures 1 and 2 for load conditions.)
Characteristics
Propagation Delay Time
High-to-Low-Level, Driver Output
As 1/0 Driver
As Select-Out Driver
Low-to-High-Level, Driver Output
As 1/0 Driver
As Select-Out Driver
High-to-Low-Level, "D"'ri"'ve"'r"O"'u"'tp=ut
As 1/0 Driver
As Select-Out Driver
Low-to-High-Level, ....
D"'ri'"'ve:::r""""=
As 1/0 Driver
As Select-Out Driver
Low-to-High-Level, Fault Flag - MC3481
As I/O Driver
As Select-Out Driver
Ratio of Propagation Delay Times
As 1/0 Driver
Max
Unit
ns
18
19
20
21
tPHL(D)
tPHL(DS)
25
26
tPLH(D)
tPLH(DS)
25
26
tPHL(F)
tpHL(FS)
45
47
tPLH(F)
tpLHFS
40
42
1.0
NOTES: 1. Reference IBM specffication GA22-6974-3 for test tenninology.
2. The fau~ protection Circuitry of the MC3481 and MC348S requires relatively clean input voHage wavefonns for current oparation. Noise pulses which
enter the threshold region (0.8 to 2.0 V) may cause the output to enter the fault protect mode. To exit the protect mode, ij is necessary to gate an
input of the effected driver to the low logic state.
7--82
MOTOROLA ANALOG IC DEVICE DATA
MC3481 MC3485
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, these specifications apply over recommended power supply and
temperature ratings. Typical values measured at TA = 25°e and VCC = +5.0 V)
MC3481
Characteristic
High-Level Input Voltage Note 2
Min
Typ
Max
Min
Typ
Max
Unit
-
-
2.0
-
V
0.6
-
-
0.6
V
VIH
2.0
Low-Level Input Voltage Note 2
VIL
-
High-Level Input Current
(VCC = 4.5 V, VIH = 2.7 V) - Input
Enable
(VCC = 4.5 V, VIH = 5.5 V) - Input
Enable
IIH
Low-Level Input Current
(VCC = 5.95 V, VIL = 0.4 V) - Input
Enable
IlL
Input Clamp Voltage
(IIC = -16 rnA)
MC3485
Symbol
VIC
-
-
-
-
20
40
100
200
-
20
60
100
400
-
-
-250
-500
-
-
-250
-1000
-
-
-1.5,.
-
-1.5
3.6
3.6
-
VOH(D)
VOH(DS)
3.11
3.9
Low-Level Driver Output Voltage
(VCC = 5.5 V, VIL = 0.6 V, 10L = -240 ~A)
(VCC = 5.95 V, VIL = 0.8 V, 10L = -1.0 mAl
VOL(D)
VOL(DS)
-
-
-
'f
.
+
.'
... CJA,5.f
l
V
3)~
3;8. -
OJ6
,N
.~
V
0,:
,,,+,
:1.
I$~~
.,
,
,;,.i i>,' r1 <;'.5.0
lOS (D)
10S(DS) k,r£~~'; '.
J
Driver
Short
CircuH
Operation
MOTOROLA ANALOG IC DEVICE DATA
7-85
®
MOTOROLA
MC3488A
Dual EIA-423/EIA-232D
Line Driver
The MC3488A dual is single-ended line driver has been designed to
satisfy the requirements of EIA standards EIA-423 and EIA-232D, as well
as CCITT X.26, X.28 and Federal Standard FIDS1030. It is suitable for use
where signal wave shaping is desired and the output load resistance is
greaterthan 450 ohms. Output slew rates are adjustable from 1.0 j.!s to
100 j.!S by a single external resistor. Output level and slew rate are
insensitive to power supply variations. Input undershoot diodes limit
transients below ground and output current limiting is provided in both output
states.
The MC3488A has a standard 1.5 V input logic threshold for TTL or
NMOS compatibility..
DUAL
EIA-423/EIA-232D
DRIVER
SEMICONDUCTOR
TECHNICAL DATA
• PNP Buffered Inputs to Minimize Input Loading
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
• Short Circuit Protection
• Adjustable Slew Rate Limiting
• MC3488A Equivalent to 9636A
II
• Output Levels and Slew Rates are Insensitive to Power
Supply Voltages
DSUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
• No External Blocking Diode Required for VEE Supply
• Second Source j.!A9636A
PIN CONNECTIONS
Wave
Shape
Input A
InputB
Gnd
ORDERING INFORMATION
Device
MC3488AP1
Operating
Temperature Range
TA=Oto+70°C
MC3488AD
Package
Plastic DIP
S0-8
Simplified Application
Wave Shape
Control
-4:-
MC3488A Driver
TIL Logic
7-86
:
R&-423 Interface
MC3486
Three-State Receiver
i ~
MOTOROLA ANALOG IC DEVICE DATA
MC3488A
MAXIMUM RATINGS (Note 1)
Rating
Power Supply Voltages
Output Current
Source
Sink
Symbol
Value
Unit
VCC
VEE
+15
-15
V
10+
10-
+ 150
-150
mA
Operating Ambient Temperature
TA
Oto+70
Junction Temperature Range
TJ
150
Storage Temperature Range
Tstg
-65to+ 150
°c
°c
°c
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltages
Operating Temperature Range
Wave Shaping Resistor
Symbol
Min
Typ
Max
Unit
VCC
VEE
10.8
-13.2
12
-12
13.2
-10.8
V
TA
0
25
70
°c
RWS
10
-
1000
kQ
TARGET ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply over recommended operating conditions)
Symbol
Min
Typ
Max
Unit
Input Voltage - Low Logic State
Characteristic
VIL
-
-
0.8
V
Input Voltage - High Logic State
VIH
2.0
-
-
V
IlL
-80
-
-
IlA
IIHI
IIH2
-
-
-
10
100
Input Clamp Diode Voltage
(11K = -15 rnA)
VIK
-1.5
-
-
Output Voltage (RL = 00)
(RL= 3.0 kQ)
(RL=450Q)
Low Logic State
EIA-423
EIA-232D
EIA-423
VOL
-6.0
-6.0
-6.0
-
-5.0
-5.0
-4.0
Output Voltage (RL = 00)
(RL.= 3.0 kQ)
(RL=450Q)
High Logic State
EIA-423
EIA-232D
EIA-423
VOH
5.0
5.0
4.0
-
6.0
6.0
6.0
RO
-
25
50
IOSH
IOSL
-150
+15
-
-15
+ 150
Output Leakage Current (Note 3)
(VCC =VEE = OV, -6.0V '" Vo '" 6.0 V)
lox
-100
-
100
I!A
Power Supply Currents
(RW = 100 kQ, RL = 00, VIL '" Vin '" VIH)
ICC
lEE
-
-
+18
rnA
-18
Input Current - Low Logic State
(VIL= 0.4 V)
Input Current - High Logic State
(VIH = 2.4 V)
(VIH=5.5 V)
Output Resistance
(RL'" 450Q)
Output Short-Circuit Current (Note 2)
(Vin = Vout = 0 V)
(Vin = VIH(Min), Vout = 0 V)
IlA
V
V
V
Q
mA
-
NOTES: 1. Devices should not be operated at these values. The "Electrical Characteristics" provide conditions for actual device operation.
2. One output shorted at a time.
3. No VEE diode required.
MOTOROLA ANALOG IC DEVICE DATA
7-87
II
MC3488A
TRANSITION llMES (Unless otherwise noted, eL = 30 pF, f = 1.0 kHz, Vee = - VEE = 12.0 V ± 10%, TA = 25°e, RL = 450 O.
Transition times measured 10% to 90% and 90% to 10%)
Characteristic
Symbol
Transition lime, Low-to-High State Output
(RW= 101<.0)
(RW = 100 1<.0)
(RW = 500 1<.0)
(RW = 10001<.0)
lTLH
Transition Time, High-to-Low State Output
(RW= 10kO)
(RW = 100 1<.0)
(RW = 500 1<.0)
(RW = 1000 kO)
lTHL
Min
Typ
Max
0.8
8.0
40
80
-
1.4
14
70
140
0.8
8.0
40
80
-
1.4
14
70
140
Unit
IlS
-
IlS
-
Figure 1. Test Circuit and Waveforms
for Transition Times
To
Scope
(Input)
To
Scope
(Output)
VCC
II
Pulse
Generator
CL
(Includes
Probe and Jig
Capacitance)
RWS
c
ote: Input Rise
and Fall Times
(10% to 90%) .; 10 ns
3.0V - - - - / - - , . -_ _ _ _ _ _ _ _ _ _-(
Input
OV----'
VOH ---~90~%"\o
OV-----~l.----------------r-1
Oulput
VOL--------~--~~------------------~
trHL
7-88
-I
trLH
MOTOROLA ANALOG IC DEVICE DATA
MC3488A
Figure 2. Output Transition Times versus
Wave Shape Resistor Value
Figure 3. Input/Output Characteristics
versus Temperature
1000
6.0
~
;:
4.0
~
~1oo
2.0
'-'
~
ill0:
~
!3
g:
CL-30pF
0
I
1.
is - 2.0 r-- c- VCC= 12V
UJ
~
0°
TA = 25°
70°
UJ
10
en
}-4.0
UJ
:::e
so
r-- "'VEE=-12V
r-- -RwS=1ookO
r-- '-RL=4500
-6.0
1.0
0.1
1.0
10
100
TRANSITION TIMES, trLH/trHL (~)
I
I
1000
1.0
Yin, INPUT VOLTAGE (V)
2.0
Figure 4. Output Current versus Output Voltage
Power-On
50
I
40
1
30
~
10
0:
0:
a
I,
0.08
1
'=
Yin = VIH(Min)
20
I
1/
0
TA=125oC I
VCC= 12 V
VEE=-12V
RWS=100kQ
t-
~ -10
is
Power-Off
0.10
I
I
-,
-20
I
-5-30
I
..2
-40
0.04
0.02
~
0
VCC = VEE = Yin -0 V
TA = 25°C
(No diode required
at VEE Pin.)
~ -0.02
0.
-0.04
J-0.06
I
-SO
- 10 - 8.0 - 6.0 - 4.0 - 2.0
0
2.0
4.0
Vout, OUTPUT" VOLTAGE (V)
~
ff
:::J
I
Yin = 0 V
0.06
:::J
I
I
1
- 0.08
-0.10
6.0
8.0
10
10 - 8.0 - 6.0 - 4.0 - 2.0
0
2.0 4.0
Vout, OUTPUT VOLTAGE (V)
Figure 5. Supply Current versus Temperature
12.0
10.0
8.0
6.0
~ 4.0
~
2.0
0
~ -2.0
!t - 4.0
I,
I
I
,I
1
Figure 6. Rise/Fall Time versus
I
I ..1
VCC= 12V
VEE = -12V
RWS = 100 kO, RL = 00
a
I
UJ
F
-'
-'
20
/'
en
a:
-'
:I:
TA=25°C
.
::-
lEE
30
40
SO
60
70
80
TA, AMBIENT TEMPERATURE (0C)
MOTOROLA ANALOG Ie DEVICE DATA
Rws
P'
iiI 10
~
~
:I:
~
J
10
,
I I
TA = O°C, 70°C
if
Vin-VIH
o
10
,
VCC=12V
r--- VEP 12V
r--- CL=3OpF
::;:
Vin=OV
ii -8.0
--10.0
-12.0
~
'[
ICC
I
I
~ -6.0
8.0
100
Yin = 0 V, Yin = VIH
1
6.0
90
100
".
1~
10k.
100 k
RWS, WAVE SHAPING RESISTANCE (0)
1M
7-89
®
.ItIIOTOROLA
MC34055
IEEE 802.3 10BASE-T
Transceiver
II
The Motorola 10BASE-T transceiver, designed to comply with the ISO
8802-3 [IEEE 802.3] 10BASE-T specification, will support a Medium
Dependent Interface (MDI) in an embedded Media Attachment Unit (MAU)'.
The interface supporting the Data Terminal Equipment (DTE) is TTL, CMOS,
and raised ECl compatible, and the interface to the Twisted Pair (TP) media
is supported through standard 1OBASE-T filters and transformers.
Differential data intended for the TP media is provided a 50 ns pre-emphasis
and data at the TP receiver is screened by Smart Squelch circuitry for
specific threshold, pulse Width, and sequence requirements.
Other features of the MC34055 include: Collision and Jabber detection
status outputs, select mode pins for forcing loop Back and Full-Duplex
operation, a Signal Quality Error pin for testing the collision detect circuitry
without affecting the TP output, and a lED driver for Link Integrity status. An
on-chip oscillator, capable of receiving a clock input or operating under
crystal control, is also provided for internal timing and driving a buffered
clock output.
The MC34055 is manufactured on a BiCMOS process and is packaged in
a 24 pin SOIC.
1OBASE-T TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(S0-24L)
• BiCMOS Technology for low Power Operation
• Standard 5.0 V, ± 5% Voltage Supply
• Smart Squelch Enforcement of Threshold, Pulse Width, and Sequence
Requirements
• Driver Pre-Emphasis for Output Data
• TTL, CMOS and Raised ECl Compatible
• Interfaces to TP Media with Standard 10BASE-T Filters and
Transformers
PIN CONNECTIONS
• lED Capable Status Outputs for COllision, Jabber Detection, and Link
Integrity
• Directly Driven or Crystal Controlled Clock Oscillator
ClkOut
0
• Selectable Full-Duplex Operation
TXDataB
• Signal Quality Error Test Pin
• Selectable loop Back
SQEENL
TXENH
TX+
Dig.Gnd
TX. PwrGnd
VCc{DigiAna)
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply VoHage
PwrVCC
FULLDL
Symbol
Value
Unit
VCC
-0.5 to 7.0
Vdc
RX DataB
RX+
RXENH
RX-
- 5.25 to 5.25
Vdc
-.0.5 to 5.5
Vdc
Voltage Applied to Logic Outputs and
Output Status Pins
-0.5t07.0
Vdc
ViD
CTLH
LoopL
JABBH
LNKFLH
Ambient Operating Temperature Range
TA
Ot070
°c
Junction .Temperature
TJ
-65\0150
°C
NOTE: Devices should not be operated at these limits. The "Recommended Operating
Conditions' table provides for actual device operation.
7-90
Ana. Gnd
RXDataA
Vollllge Applied to Logic and Mode/Test
Select Inputs
Differential Voltage at RX+/RX-
Clk+
Clk-
TX Data A
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC34055DW
TA = 0° to +70°C
S0-24L
MOTOROLA ANALOG IC DEVICE.DATA
MC34055
Simplified Block Diagram
PwrVcc
vee (Dig/Anal
r----------------------O----O------,
Balun
lli
Fillef
I
I
DalaOuI
Vee Hi~""''V¢~---I nveMos
SOEENL
I
L---o--o---o------Ana.
Pwr
Dig.
elk +
Goo
Gnd
*The sale and use of this product is licensed
under technology covered by one or more
Digital Equipment Corporation patents.
Goo
lOMHz
This device contains 9,875 active transistors.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Voltage Applied to logic Inputs and Status Pins
Differential Input VoHage
Operating Ambient Temperature
Symbol
Min
Typ
Max
Unit
VCC
4.75
5.0
5.25
Vdc
-
0
-
5.25
Vdc
-
0.59
-
2.8
Vpp
TA
0
-
70
°C
Unit
NOTE: AIiUmits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (oOe $ TA $ 70°C, Vce = 5.0 V, unless otherwise noted.)
Characteristic
Supply Current (4.75 V
$
VCC $ 5.25 V)
Reset Circuit Threshold
Symbol
Min
Typ
Max
ICC
-
60
180
rnA
-
4.0
-
4.4
Vdc
TWISTED PAIR TRANSMITTER
Output Differential Voltage
(See load CircuHs: Differential load Circuit)
Output Differential Voltage with Pre-Emphasis
Output Differential Voltage
Common Mode Driver Impedance
Transmitter Differential Output Impedance
Vpp
Vo
2.2
1.56
2.53
1.72
2.8
1.98
ZoCM
6.0
8.5
14
Zoo
8.0
15.5
29
VIH
0.984 VCC 0.984 VCC 0.984 VCC 0.750 VCC 0.750 VCC 0.750 VCC -
n
n
TX DATA A
Input High Voltage (IIH = + 20 I1A)
Input Low Voltage (Ill = -150!1A)
TXDATAB
Input Voltage (See load Circuits: ECl load Circuit)
High: @O°C
@25°C
@70°C
@O°C
low:
@25°C
@70o e
MOTOROLA ANALOG IC DEVICE DATA
Vdc
Vil
0.923
0.877
0.825
0.568
0.550
0.531
0.984 VCC 0.984 VCC 0.984 VCC 0.750 VCC 0.750 VCC 0.750 VCC -
0.763
0.727
0.644
0.361
0.350
0.324
7-91
•
IYIC34055
ELECTRICAL CHARACTERISTICS (O°C:O; TA:O; 70°C, VCC = 5.0 V, unless otherwise noted.)
I
I
Characteristic
Symbol
I
Min
I
Typ
Max
-
-
Unit
TXENH
Input High Voltage (IIH = 200 1lA)
Input Low Voltage (IlL = - 20 1lA)
RX DATA AlRX EN HlJABB HlCTL H
Output Vo~age (See Load Circuits: CMOS Load Circuit)
High (IOH =-12 rnA)
Low (IOL = + 16 rnA)
Vdc
VOH
VOL
3.7
VOH
0.984 VCC 0.984 VCC 0.984 VCC 0.750 VCC 0.750 VCC 0.750 VCC -
-
-
0.5
RX DATA B
Output Voltage (See Load Circuits: ECL Load Circuit)
High: @O°C
@25°C
@70°C
Low:
@O°C
@25°C
@70°C
Vdc
VOL
0.923
0.877
0.825
0.568
0.550
0.531
0.984 VCC - 0.763
0.984 VCC - 0.727
0.984 VCC - 0.644
0.750 VCC - 0.361
0.750 VCC - 0.350
0.750 VCC -·0.324
SIGNAL QUALITY ERROR TEST ENABLE CONTROL (SQE EN L)
Test Control Voltage
Test Disabled (Input High Voltage)(IIH = + 20 IlA Max.)
Test Enabled (Input Low Voltage)(- 50 IlA < IlL < -150 ~A)
Vdc
-
VIH
VIL
2.0
0
-
5.0
0.8
VIH
VIL
2.0
0
-
5.0
0.8
VIH
VIL
2.0
0
VOH
VOL
-
FULL DUPLEX MODE SELECT (FULLD L)
II
Mode Select Control Vonage
Normal Operation (Input High)(llH = + 20 1lA)
Full Duplex (Input Low)(- 50 IlA < IIH < -150 1lA)
Vdc
LOOPBACK TEST MODE FUNCTION (LOOP L)
Test Control Voltage
Test Disabled (Input High)(llH = + 20 1lA)
Test Enabled (Input Low)(IIL = - 200 1lA)
Vdc
-
5.0
0.8
-
LINK FAIL STATUS (LiNKFL H)
Status Output Vonage (See Load Circuits: CMOS Load Circuit)
Maximum VoHage for Output Low Condition (IOL = 20 rnA)
Output Low Sink Current
-
-
0.5
20
Vdc
rnA
5.0
0.8
Vdc
CLOCK OSCILLATOR
Clk+ Input Logic Threshold
High Level Input Voltage (IIH ~ +100 IlA Max.)
Logic Low Input Voltage (IlL = -100 ~A Max.)
VIH
VIL
Clk Out Output Voltage (See Load Circuits: CMOS Load Circuit)
Logic High (IOH = -12 rnA)
Logic Low (lout = + 161lA)
-
2.0
-
-
IlA
Vdc
VOH
VOL
3.7
-
3.9
0.25
-
0.5
Output Load Circuits
39(1%)
TX330!}
15pF
ECL load Circuit
7-92
20pF
6.0k!}
TIlJCMOS Load Circuit
I
I
I
TXt I
100!}
39(1%)
Differential Load Circuit
MOTOROLA ANALOG IC DEVICE DATA
MC34055
TIMING CHARACTERISTICS (O°C ~ TA ~ 70°C)
I
Characteristic
Symbol
Min
Typ
Max
Unit
TRANSMIT START TIMING
TX EN H to TX+ITX- Enable Time
trXEN
-
-
75
ns
TX Data AlB to TX+ITX- Enable Time
tFDXD
-
-
75
ns
Steady State Propagation Delay of TX Data AlB to TX+/TX- Output
trxSS
-
-
75
ns
Pre-Emphasis Pulse Widlh
IpRCM
45
-
55
ns
Transmitter Caused Edge Skew Between TX+ and TX-
ISkewT
-
-
2.0
ns
-
4.0
ns
tJitterT
-
Sleady--81ate Delay between Ihe TX Dala AlB Input to the RX Data
AlB Outpuls for Normal Operation
trXRX
-
-
50
ns
TX EN H Assert to RX EN H Assert Under Normal Operation
tDREL
-
-
50
ns
Transmitter Added Edge Jitter 10 TX+ITX- from TX Dala AlB
TRANSMIT STOP TIMING
Delay between TX EN H Low and TX+ITX- High
trXDH
-
-
75
ns
TX EN H AsserVDe-assert Delay from TX EN H 10 RX EN H
AsserVDe-assert
tXTRE
-
-
400
ns
End of Packet Hold Time from Last TX Data AlB Edge or
TX EN H De-assert
trDDC
250
-
-
ns
Delay from Loop L Deassertion to RX EN H Driven from
TX EN H Status
tLTRA
-
-
30
ns
TX EN H AsserVDe-assert to RX EN H, AsserVDe-assert when in
Loop-Back Mode and Receiver Inactive
tLTRX
-
-
50
ns
Sleady-8tate TX Dala AlB 10 RX Data AlB when in Loop-Back Mode
tLTRD
-
-
50
ns
Receiver-Added Edge Skew 10 RX Dala AlB Signal
ISkewR
-
-
1.5
ns
Receiver-Added Edge Jitter to RX Dala AlB Signal
LINK BEAT PULSES
Output Link Test Pulse Width
Minimum Link Beal Pulse Duration on RX+/RXLOOP BACK MODE TIMING
SMART SQUELCH
Interval Unit Squelch Deactivation
RECEIVE START TIMING
!Jitter R
-
-
1.5
ns
Start-Up Delay from RX+/RX- to RX Data AlB
tRXNE
-
-
50
ns
Delay from RX EN H Assertion Until RX Data AlB Valid
tRARE
-10
-
+10
ns
Steady--81ate Propagalion Delay from RX+/RX- Data AlB
IRXSS
-
-
50
ns
RECEIVE SHUTDOWN TIMING
Last received Data Edge until the RX EN H Output forces low
MOTOROLA ANALOG IC DEVICE DATA
7-93
•
MC34055
Figure 1. Start Up and Steady State Transmit Timing
TXENH
-A
BHPattem
TX Data AlB
RXENH
RXDataAIB
TX+fTX-
1
1
o
I
~~ trxRX -:
~
~
1
1
1
1
'\
LJ
1
1
1
1
1
\
/
1
1
1
1
I
:
\
I"
..
1 trxSS 1
1"tPRCM.1
trxEN
I"
II
1
1
lJlTTERT
--'·1
Figure 2. Driver Shutdown TIming
LJ
TXDataAIB~
I
Bit Pattern
1
I
585mV
0
TIMX-
~
TXENH
-
~
~~----------------I"
"I
\'----txrRE
1
RXENH
Figure 3. Link Pulse TIming
tLOCY_A
-_-_H.I"
"I
RX+_/R_X-_ _ _ _
H
-_-_'! ---[..-
TX+_fTX_-_ _ _ _
1
585mV
585mV
1
MOTOROLA ANALOG IC DEVICE DATA
MC34055
Figure 4. Loop Back Timing
TX EN H - - - - - - - - - - - ' ,
I I
I
I '---ir----"""t-=:
Bit Pattern
TX Data AlB
RXENH - - - - - - - - - - - \
I~
tlTRX ~J
1
!
I
1
I~----~
loopl
I
tlTRD
I
RXDamAIB
I
0
-------t-cr-RA~:-----~~r----~'\~----~!'
-------tj
II
Figure 5. Receive Startup Timing
o
o
RX+/RX-
I
I
I
I
IsQ
RXEN H
•
I~tRARE
"I
1
1
1
/
1
I
I..
tRXNE
·1
+
RXDataAlB------------------------tSKEWR
I
I
I
I·
tRXSS
"I
~RR
Figure 6. Receive Shutdown Timing
l~
tRXDE
"I
RXENH---------------------~\~_ _ _ _ _ _ _ __
MOTOROLA ANALOG IC DEVICE DATA
7-95
MC34055
PIN FUNCTION DESCRIPTION
II
7-96
Pin
Symbol
1
ClkOut
2
TX Data A
CMOS transmit input pin. Data input at this pin is output to the TP media. The input will source
less than 175!lA and sink less than 20 !lA.
3
TXData B
Raised ECL transmit input pin. Data input at this pin is output to the TP media. The input can
source 40 !lA for a high level input or 70 !lA for a low level input.
4
TXENH
5
Dig. Gnd
6
VCc(DiglAna)
Description
TTUCMOS buffered 10 MHz clock output. This pin will source 400 IlA and sink 16 mAo
TTUCMOS transmit enable pin. Transmit is enabled when asserted high. The input will source
less than 175!lA and sink less than 20 !lA.
Digital ground
Digital and analog VCC. With the current consumed at this pin and Pin 18, the device will
consume less than 180 mA at 5.0 Vdc.
7
Ana. Gnd
Analog ground
8
RXDataA
TTUCMOS received data output pin. Data from the TP media is output at this pin. The output
will source 12 mA and sink 16 mAo
g
RX DataB
10
RXENH
11
Loop L
TTUCMOS Loopback test select. Asserting this pin causes the transmH data to be looped to
the receive circuit while the TP transmit driver sends a link pulse. The input will source less
than 175 IlA and sink less than 20 IlA.
12
LNKFLH
This pin is driven high to indicate a link fail state. When low, the pin will sink 20 rnA to light an
LED. An usquelched condition due to valid data on the receive circuH will cause the pin to
transition high and low in 100 ms intervals.
13
JABBH
TTUCMOS Jabber status pin. This pin is asserted when a Jabber condition is detected and will
source 12 rnA and sink 16 rnA.
14
CTLH
Raised ECL received data output pin. Data from the TP media is output at this pin.
TTUCMOS received data output enable pin. This pin is asserted after the Smart Squelch
circuitry determines that there is valid data at the TP input pins and also when intemal
loop-back is occurring. The output will source 12 mA and sink 16 rnA. The receive data outputs
are forced high when this pin is low.
TTUCMOS status pin. This pin pulled high when Jabber or Collision condHions are detected.
Also high for a time interval when a Signal Quality Error test is being performed. The pin will
source 12 rnA and sink 16 rnA.
15
RX-
The inverting terminal of the TP differential receiver.
16
RX+
The noninverting terminal of the TP differential receiver.
17
FULLDL
TTUCMOS duplex mode select. When low, this pin forces the device to operate in full-duplex
mode. The input will source less than 175!lA and sink less than 20 !lA.
18
PwrVcc
Power supply pin. With the current consumed at this pin and. Pin 6, the device will consume
less than 180 mA at 5.0 Vdc.
19
PwrGnd
Power ground pin.
20
TX-
The inverting terminal of the TP differential driver.
21
TX+
The noninverting terminal of the TP differential driver.
22
SQE EN L
23
Clk-
TTUCMOS clock oscillator pin. See Pin 24.
24
Clk+
TTUCMOS clock oscillator pin. This pin is used with Pin 23 ~ the internal oscillator is to be free
run with a crystal. The oscillator can also be directly driven with a TTUCMOS clock signal at
this pin. The oscillator frequency should be 10 MHz with a duty cycle of 50 ± 20%.
TTUCMOS Signal Quality Error test enable pin. Pulling this pin low allows test of the collision
detect circuitry without affecting the twisted pair channel. The input will source less than 175 IlA
and sink less than 20 !lA.
MOTOROLA ANALOG IC DEVICE DATA
MC34055
FUNCTIONAL DESCRIPTION
Introduction
The Motorola 1OBASE-T transceiver, designed to comply
with the ISO 8802-3[IEEE 802.3) 10BASE-T specification,
will support one Medium Dependent Interface (MOl) through
standard 10BASE-T filters and transformers. Although the
device is capable of being used in embedded or external
Medium Attachment Units (MAU), it was primarily designed
for use in repeater or hub applications. For this reason a
digital interface is provided rather than an AUI interface. This
interface is TTL, CMOS, and raised ECl compatible and
allows for easy connection in hub applications.
Other features of the MC34055 include: select mode pins
of forcing loop-8ack and Full-Duplex operation; a Signal
Quality Error pin for testing the collision detect circuitry
without affecting the twisted pair output; and lED drivers for
Link Integrity status; Collision detection; and Jabber
detection. An on chip oscillator, capable of receiving a clock
input or operating under crystal control, is also provided for
internal timing and driving a buffered clock output.
The inputs were not intended to be used simultaneously in a
single application and are internally logically combined. The
unused input should be disabled by connection to VCC.
When data transmission is intended, the MC34055
detects the first falling edge of the Manchester encoded
frame at the input being used, synchronizes the on chip
oscillator (Pins 23 and 24) and asserts the twisted pair driver
output to full differential amplitude within 25 ns if the driver
enable pin (TX EN H) is previously asserted. Also, since
twisted pair attenuates a 10 MHz signal more than a 5.0 MHz
signal the 10BASE-T standard requires that data applied to
the twisted pair receive pre-equalization. To fulfill this
requirement the MC34055 provides an additional 730 mV for
approximately 50 ns to output data. This is accomplished
over the single pair of differential driver pins. TX+ and TX-,
and effectively equalizes the power of all data components at
the receiver. Figure 7 A shows a 10 MHz waveform. Figure 7B
shows the effect of pre-emphasis on a 5.0 MHz waveform.
Manchester encoded data with the pattern shown in Figure
7A would represent a repeating pattern of zeros (000000... ).
Figure 7B would represent an alternating pattern of ones and
zeros (0101010 ... ).
Data Transmission
For data intended for the twisted pair, the MC34055 has
two data inputs, TX Data A and TX Data B. TX Data A is
CMOS compatible and TX Data B is raised ECl compatible.
Figure 7A. 10 MHz Waveform on Differential Outputs
0
BitPatlem
TX+
Pin 21
0
0
0
0
1-T
25
1.
I
-+ OV
I
-1
,
1__
-t
TXPin 20
I
---L
I
1.25V
OV
Figure 7B. 5.0 MHz Waveform on Differential Outputs
o
BitPatlem
TX+
Pin 21
I
OV
TXPin20 OV
MOTOROLA ANALOG IC DEVICE DATA
----1-_...1
-,
---- ..... I
7-97
MC34055
The figures show the voltage waveforms on the differential
driver output pins. To actually meet the 10BASE-T
specification requires bandpass filtering and a pulse
transformer.
The output voltage waveform specifications of the IEEE
802.3. standard require that voltages impressed on the
twisted pair meet .a voltage template. The MC34055 can
meet the voltage template for all the 1OBASE-T applications
initiated. In this event, the transmit differential driver will
remain active for the entire frame interval and the link pulse
will not affect more than one bit interval.
The MC34055 also has Jabber circuitry to detect and
disable the twisted pair driver in the event .that a serial
controller fails constantly transmitting. Should any data
source try to transmit longer than 20 ms minimum, the Jabber
function will disable the differential driver outputs, the
Figure 8. Differential Driver Media Interface Circuitry
RS
,----,
L ____ J
.
ZF
,----,
ZF
-1 r----A/I/Ir-;
TX- RS
rI
IL
Pulse
Transfonner
I-I ':
Twisted Pair
FIZo~
_ _ -1
Where: ZOO is the transmitters differential output impedance (-20 (1),
RS is a 1% series resistor,
ZF is the filters impedance, and Zo is the characteristic
impedance of the twisted pair (100 (1).
II
by choosing the appropriate low pass filter and external
components in the driver output circuitry. When the
differential transmit driver output pins are configured to drive
the bandpass filters and pulse transformer as shown in
Figure 8, the resultant waveform is capable of meeting the
voltage template.
Following the end-of-frame activity, an internal pull-up
resistor pulls TX Data AlB high and causes the differential
driver to maintain full differential output voltage for
approximately 250 ns. The differential driver interprets the
lack of transition activity as an end of frame and starts an idle
timer. Should another frame intended for the twisted pair
arrive before the idle timer expires(-250 ns), the idle timer
will be reset, if not, the transmit driver function will begin the
decay to idle process. During idle periods the differential
driver must force the media to a minimal differential voltage
unless a link beat is being produced. The transition to
minimal voltage is subject to performance requirements in
the IEEE specification and is met by the MC34055 when the
appropriate filters and transformers are used to interface to
the media.
The MC34055 differential driver generates link pulses
(beats) during idle periods. The link pulses produced are
singular positive (TX+ positive with respect to TX-) pulses
applied to the media at 16 ms intervals and last
approximately 100 ns. The link pulses allow the receiver at
the other end of the link to verify the validity of the segment.
There is the possibility, due to the two asynchronous
sources, that one of the two input pins (TX Data A or TX Data
B) will receive frame activity immediately after a link pulse is
7-98
collision presence detector and the internal loop back
function. Also, two status indicator pins, CTL Hand JABB H
are asserted. The MC34055 will remain in the jabber state
until the TX EN H pin is pulled low or the jabbering input
ceases to toggle for a minimum of 500 ms. The status
indicator pins, CTL Hand JABB H will also sink up to 20 rnA
and can therefore support external LEOs.
The driver also works with the receiver to provide
loop-back. Under normal operating conditions (Loop L= "1"),
the data applied to the TX Data AlB pins is looped back
internally to the RX Data AlB pins. This function is disabled
when there is a collision condition or FULLD L is low.
Data Reception
Data intended for the DTE proceeds from the twisted pair
to the isolation transformer and bandpass filters before
reaching the differential receiver terminals. Figure 9 shows
the configuration of the external media receive circuitry. Once
transitions at the receiver terminals (RX+ and RX-) are
detected, the on-chip oscillator is synchronized and the
received data is screened by smart squelch circuitry for
validity. This qualification requires incoming data to meet
amplitude and sequence requirements. If the data meets the
Smart Squelch requirements, the receiver enters the
unsquelch state and the data is forwarded to the RX Data AlB
output pins provided Loop L is not low. Two data outputs are
provided to increase design flexibility, RX Data A and RX
Data B. RX Data A is CMOSfTTL compatible and RX Data B
is raised ECL compatible.
MOTOROLA ANALOG.ICDEVICE DATA
MC34055
Figure 9. Differential Receiver Media Interface Circuitry
r----,
Pulse
Transformer
Twisted Pair
L ____ .J
!r -11- 1
ZF
L _ _ .J
ZF
)<::>c><:><- Zo I ~
I
I
RT
~r:---_-W-'v---'+-+-i
16 RX+
L _ _ _ _ .J
Where: RT is a terminating resistor (1000),
ZF is the filters impedance, and Zo is the
characteristic impedance of the twisted pair (100 0).
The MC34055 powers up in a squelched and "link OK"
state, after which minimum and maximum link test and
maximum link fail timers are started. If valid data or a link
pulse is received after the link test minimum timer but before
the link fail maximum timer times out, the timers are reset and
begin counting again. In the event of missing or incorrect link
pulses, the MC34055 enters the link fail state whereby the
LNKFL H status pin is asserted until valid data or link pulse
activity appears at the receiver terminals.
Powering up in the squelched state assures that the data
path to the data output pin (RX Data AlB) is disabled, and
prevents noise at the receiver terminals (RX+/RX-), from
being interpreted as valid input data. Once transitions appear
at the receiver terminals, the smart squelch circuitry checks
for the smart squelch requirements to unsquelch; an
alternating sequence (1010 ... or 0101...) of pulses with
amplitude of at least 525 mV. This requirement is met by the
preamble of an IEEE 802.3 frame with good signal to noise
ratio.
After a pulse is received and checked for proper polarity
and amplitude, the pulse width is checked for proper
duration. If the duration is to short or too long the smart
squelch Circuitry resets and begins to look again for a proper
sequence. By requiring the differential pulses to meet
amplitude and sequence requirements, it is unlikely that
pulses due to crosstalk from coresident twisted pairs are
capable of causing the receiver to unsquelch. If a positive
pulse is received first and the differential driver is not
transmitting, the receiver should un squelch after three
alternating pulses. If a negative pulse is received first, one
additional pulse is required before unsquelch. If the
differential driver is transmitting, three additional pulses are
required to unsquelch.
After meeting the smart squelch requirements, the
MC34055 will pull high the RX EN H pin and enable the path
to the receive data pin (RX D&ta AlB) provided the MC34055
is not in the loop back test mode (Loop L low). If the receiver
unsquelches, the receive enable pin remains high and the
data path to the receive data pin remains enabled until
transitions cease to exist at the receiver terminals. Valid data
reception is also indicated by high/low transitions of the
LNKFL H pin at 100 ms intervals. When transitions at the
differential terminals cease, marking the end of frame activity,
the receiver re-enters the squelch state, pulls Iowan the RX
EN H pin, and begins accepting valid link pulses until the start
of the next 802.3 frame.
If the MC34055 is requested to begin transmitting (TX EN
H is asserted), and the receiver unsquelches simultaneously,
there is a collision. Also, if the MC34055 driver enable pin is
previously asserted and the receiver detects valid transition
activity, the receiver Smart Squelch Circuitry verifies the
possibility of collision by requiring three extra transitions at
the differential receiver before the unsquelch condition is
reached. If un squelch occurs, a collision condition exists.
During all collision conditions the MC34055 asserts the CTL
H status pin for the duration of the condition and for a time
after the end of collision.
During a collision condition the receive and transmit paths
are still both enabled allowing transparency to the media.
Either the presence of simultaneous transmit and receive
activity or the condition of the CTL H status pin can be used
by the communications controller to acknowledge and react
to the collision. In applications where a 10 MHz collision
signal is required by an SIA, the combination of this status pin
and the clock oscillator output can be logically combined to
provide a 10 MHz output. If the DTE reacts to the collision
and ceases transmitting, the MC34055 will decay to idle until
a re-transmit is attempted.
Crystal Oscillator
The MC34055 has an on-chip clock oscillator used to
provide a reliable and accurate time reference to all the
internal timers. The oscillator can be run with a crystal or
driven at Pin 24 from an external clock source. Also provided
is a buffered clock output which is useful if the MC34055 is to
be used in a repeater or concentrator application.
Table 1. The crystal used in the oscillator is subject to the following specifications.
Crystal Operating Mode
Fundamental
Crystal Cut Type
AT
Crystal External Shunt CapaCitance
7.0pFMax
Crystal Resonant Mode
Series
Crystal Accuracy
±O.OI%
Crystal Temperature Variance
0.005% from 0° to 70°C
Crystal Series Resistance
25 0 Max, 17 0 Typical
Crystal Operating Temperature Range
0° to 70°C
MOTOROLA ANALOG IC DEVICE DATA
@
25°C
7-99
7
MC34055
LOOP L Test Mode
If the Loop L pin is low, the MC34055 is in a test mode
whereby the data at the input pin (TX Data AlB) is being
looped back internally to the receive data pin(RX Data AlB).
In this mode the data path from the differential receiver
terminals to the receive data output pins (RX Data AlB) is
disconnected whiJe the Smart Squelch functionality of the
differential receiver is still operational. This test mode allows
the DTE to test the MC34055 internal loop back circuitry
since the data is looped back to the receive circuitry as close
to the twisted pair interface as possible.
minimUm, the differential driver, the collision detect, and
internal loop back circuits are disabled. To announce the
presence of a jabber condition, both the CTL H and the JABB
H status output pins are assertf3d. In order to end the jabber
condition, the TX Data AlB input must stop toggling, or the TX
EN H pin must be pulled low for a minimum of 500 ms. The
status output pins have the ability to drive an external led and
were added to facilitize network .manageability. The jabber
status outputs will not assert during power up or power down.
Signal Quality Error Test
The MC34055 can be operated in a full-duplex mode if
required. When the FULLD L pin is pulled low the device will
enter the full duplex mode. This mode allows the transmitter
and driver to operate independently. Collision will not be
announced and the internal loop back operation is disabled.
The Signal Quality Error test, however, is still operational if
enabled.
The MC34055 also provides the ability to test the collision
detect circuitry without disabling either of the data paths. By
pulling the SQE EN L pin low, a collision test is provided to
the collision detect circuitry immediately following the last
edge of a transmitted· 802.3 frame. The test verifies the
operability of the collision detect circuitry, operability is
announced by the assertion of the CTL H pin for a period
following a valid data transmission.
Jabber Detection
II
The transmit circuitry of the MC34055 has the ability to
monitor and shut down the differential driver in the event of a
jabber condition. If transmission activity ever exceeds 20 ms
Full Duplex Mode
Status Pins
The MC34055 has three status indicator pins capable of
sourcing or sinking enough current to support an external
LED. Status pin levels ("1" or "0") report the condition of the
transcei)ler. Table 2 shows the combinations and
significance.
Table 2
Status Pin
JABBH
CTLH
"0"
"1"
"1"
X
X
X
Condition
LNKFLH
cond~ion
X
Collision
or Signal Quality Error test.
"1-
X
Jabber condition
X
"0"
Link Failure. Incorrect or nonexistent link pulses, or lack of data at the
receiver terminals.
X
"1"
Link "OK". Receiving link pulses.
X
"0101.. ..
Link "OK-. Receiving valid data.
Test Select Pins
The MC34055 has three operation mode test select pins,
Loop L, SQE EN Land FULLD L. The level of the pin
determines the mode of operation. Table 3 shows the levels
and corresponding conditions of the status pins.
Table 3
Pin
Status
LoopL
"1-
Normal operating mode. Loop back occurs when the transmitter initiates and the receiver is receiving
link pulses. The RX EN H pin follows the TX EN H pin and the transmit data appears on the RX Data
AlB output pin being used.
"0"
Loop back test mode. The transmit circuit is looped back internally as close to the differential receive
circuit as possible. In this mode the RX EN H pin follows the TX EN H pin and the transmH data appears on the RX Data AlB output pin being used. Any received data other than link pulses are ignored
and the receiver will not unsquelch or announce collision.
SQE EN L
FULLDL
7-100
Condition
"0"
Normal operating mode. Concurrent transmit and receive activity results in a collision condition.
"1"
Test enabled. An intemal test is run on the collision circuitry and the CTL H pin is asserted for a time
window following the last positive packet edge. Data transmission and reception is undisturbed.
"1"
Normal operating mode. Internalloop--back is operable and collision is announced.
"0-
Internal loop-back is disabled and collision will not be announced. Signal Quality Error test is
still operable.
MOTOROLA ANALOG IC.DEVICE.DATA
MC34055
APPLICATIONS INFORMATION
The MC34055 implements the physical layer of a
10BASE-T application of IEEE 802.3. It provides the
physical connection to the media (twisted pair) and the
services required by the MAC sublayer of the Data Link
Layer. Two interfaces are defined in the IEEE 802.3
specification of the physical layer; one is the MOl providing
connection to the twisted pair; and the other is the AUI
providing connection to the encoder/decoder function of the
Data Link Layer. While the MC34055 provides the connection
to the twisted pair, a CMOS and raised ECL interface is
provided instead of an AU/.
The MC34055 implements the twisted pair interface of the
physical layer in a 802.3 10BASE-T application but circuitry
must be added if an AUI is desired, (see Figure 10 for
suggested schematic). For example, an external MAU
application requires the AUI and a twisted pair interface. A
chip capable of realizing the AUI interface is the Texas
Instruments SN75ALS085. This Ie has an AUI interface and
another interface which is compatible with the MC34055. The
differential input of the 75ALS085 can be used for the
TX+ITX- terminals of the AU/. The differential drivers of the
75ASL085 can be used as the RX+/RX- and the
COL+/COL- terminals of the AU/. The other interface of the
75ALS085 then will interface to the MC34055 by three paths
MOTOROLA ANALOG IC DEVICE DATA
shown in the application suggestion. The application
accounts for all the inputs/outputs of an external MAU.
Embedded applications do not require a full AUI and a
MC10116 can be used to interface between the raised ECL
interfaces of the MC34055 and the AUI of existing
encoder/decoder chips. The MC10116 is a MECL 10k Triple
Line Receiver with typical propagation delay and rise and fall
times (20% to 80%) of 2.0 ns. Figure 11 shows the use of the
MC10116 with the MC34055 and the AMD 7992 SIA.
In a multi-port repeater, or hub, a port is required for each
DTE connected to the IEEE 802.3 network. This port consists
of two connections, one for the TX+ITX- pair and another for
the RX+/RX- pair. The repeater unit then multiplexes these
lines so that all of the stations are capable of transmitting to
or receiving from all the other stations on the network. This
establishes the need for a transceiver without an AUI
interface. If an AUI is present with each 10BASE-T
transceiver, chip count is increased because there is a
requirement to convert from balanced to unbalanced lines
before multiplexing.
An application suggestion for the use of the MC34055
used in a multipart repeater is shown in Figure 6. Here the
receive and transmit lines for the 10BASE-T transceivers are
multiplexed by the hub hardware.
7-101
II
!I
Figure 10. External MAU Application
0
N.
+5.0
~
HII
IIH
HII
0.1
IV
Twisted Pair
cf
C'l
'il
""
.e.
TX+
TX Data B
["ill:
.~
RX+
AX DataB
AX-
~II
4.7 k
+5.0
IAXENI
b-1
AX Data A
4.7k
loop2
RXOI
4.7k
TXENH
cf
C'l
loopl
TX Data A
TX-
+5.0
cf
C'l
4.7k
cf
C'l
~
::>
~Q
+5.0
~
9
Balun
H
IV
AXil
+5.0
RX
11[==
RXI1
39.3
TX 11
AUIChlp
75ALS085
T 1
IO.
-=-
NC
TXOI
AXENHI
ITXENI
CTLHI
I TX EN2
TXOI
11[==
TX
lNKFlH
i:
0
a
+5.0
loopl
:tI
0
r-
:I>
:I>
Z
:I>
Full 0
'I f--o
SQE EN l
4.7k
r0
C)
JABBH
r-~
NC
TX021
180
TX02
TXI2
270
ClK
S!~~ OUT
+5.0
Ci)l>:tl
Ci)Ci)Ci)
(;
is.
cm
<
::>
Q.
::>
Q.
1
820
n~xm
Ci) Ci)
Ci)
Ci)
~~g~
is. is. is. is.
~
-=-
(;
m
~I
20
I I
20
NC
~II[==
COL
l,.
s::
0
Co)
a
en
en
Figure 11. Internal MAU Application
~
+5.0
~
~
~
~
8o
cm
::s
Twisted Pair
0<
0
g
Balun
om
~
.e
"
TX+
C
~
~
TClK
8 TX Data A
TX+
TX Data B ~ +5.0
4.7 k
TXENH
TX-
:Joi
TX-
s
I
A
r:"
TENA
MC34055
RX Data B
RX+
RX+
RClK
RX-
RX-
L
A
N
c
E
RXDataA~1
NC
RXENHI---
COll+
RDATA
COllRENA
+5.0
CTlH
1-1- - - - - - - ,
AM7992
JABBH
II~
NC
AM7990
ClSN
ClK
OUT
1
!
a
-
-
---------------
i:
n
Co)
0l:Io
0
en
en
..
...~
Figure 12. 10BASE-T Connecentrator Application
2
Balun
TX ENBO
RXRX+
iii:
I..
TX Data Bo
0
m
TX-
RXENBo
RX Data B 0
TX+
0
Hub
Hardware
0
Other
MC34055
-«
0
FIIC=cm
0
3:
l
(')
Co)
~
0
UI
UI
0
a~I
:0
0
'--
0
Balun
Jfffi1L,,-,
r
~
~
RX+
RX
;;:
r
0
0
8enen
C)
(')
TXEN B7
C
m
<
(')
m
TX-
TX DataB7
139.3
TX+
C
~I
gll[==
RX DataB7
Z
)Ii
TX
RX EN B7
I RX-
~
gll[==
'----'
-=-
>
AUI
®
MOTOROLA
MC34058
MC34059
Hex EIA-485 Transceiver
with Three-State Outputs
HEX EIA-485 TRANSCEIVER
with THREE-STATE OUTPUTS
The Motorola MC34058/9 Hex Transceiver is composed of six
driverlreceiver combinations designed to comply with the EIA-485 standard.
Features include three-state outputs, thermal shutdown for each driver, and
current limiting in both directions. This device also complies with EIA-422
and CCITT Recommendations V.11 and X.27.
The devices are optimized for balanced multipoint bus transmission at
rates to 20 MBPS (MC34059). The driver outputs/receiver inputs feature a
wide common mode voltage range, allowing for their use in noisy
environments. The current limit and thermal shutdown features protect the
devices from line fault conditions.
The MC34058/9 is available in a space saving 7.0 mm 48 lead surface
mount quad package designed for optimal heat dissipation.
SEMICONDUCTOR
TECHNICAL DATA
48
• Meets EIA-485 Standard for Party Line Operation
• Meets EIA-422A and CCITT Recommendations V.11 and X.27
a
FTASUFF'X
PLASTIC PACKAGE
CASE 932
(ThinQFP)
• Operating Ambient Temperature: O°C to +70°C
• Common Mode Driver Output/Receiver Input Range: -7.0 to +12 V
,. Positive and Negative Current Limiting
• Transmission Rates to 14 MBPS (MC34058) and 20 MBPS (MC34059)
• Driver Thermal Shutdown at 150°C Junction Temperature
ORDERING INFORMATION
• Thermal Shutdown Active Low Output
Device
• Single +5.0 V Supply, ±100/0
• Low Supply Current
MC34058FTA
• Compact 7.0 mm 48 Lead TQFP Plastic Package
MC34059FTA
Operating
Temperature Range
Package
TA = 0' to +70'C
TQFP-48
Representative Block Diagram
,----------------------1
I i-------i/il
,-----'---1-TTUCMOS Data DR --i--+--_<1T +
Direction {RE
Control DE --;--1---+-::1
TSD I
I
S~~~:~
f- I
Thermal
Shutdown
-L _ _ _ _ _ ...r-
OB} ToCable
~-T------------_+---OA
-L.-------i2l
-L.-------#3l
I
--r-
L
(Sameas#1)
I
:::::r=
_______ =l-
-C..-------#5l
±
TTUCMOS Data- RO
Direction {RE
Control DE
TTUCMOS Data_ 01
i
(Same as #1)
±
L _______ =T-
I
I
--r(Sameas#1)
=r=
_______-::::t-
L
.-C.-------1I4l
I
-i-
(Same as #1)
I
=r=
~
L _______-+~
i-:JJ-~t
~
JI
IL ______________________
_I
L
OB} ToCable
OA
This device contains 1,399 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
7-105
MC34058 MC34059
MA"IMUM RATINGS
Rating
Power Supply Voltage
Symbol
Value
Unit
Vdc
VCC
-0.5,7.0
Input Voltage (Driver Data, Enables)
Yin
7.0
Vdc
Applied Driver Output Voltage When in Three-State
Condition (VCC = 5.0 V)
Vz
-10,14
Vdc
Applied Driver Output Voltage When VCC = 0 V
Vx
±14
Vdc
Output Current
10
Self limiting
-
Tstg
-65,150
DC
Storage Temperature
NOTE: Devices should not be operated at these limits. The "Recommended Operating Condttions'
provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS (All limits are not necessarily functional concurrently.)
Characteristic
Power Supply Voltage
II
Symbol
Min
Typ
VCC
4.5
5.0
Input Voltage (All Inputs Except Receiver Inputs)
Yin
0
Driver Output Voltage in Three-State Condition,
Receiver Inputs, or When VCC = 0 V
VCM
-7.0
-
Driver Output Current (Normal Data Transmission)
10
-60
Operating Ambient Temperature
TA
0
ELECTRICAL CHARACTERISTICS (TA = 25 DC, Vec = 5.0 V ± 10%)
I
Characteristic
I
Max
-
Symbol
Min
Vo
IVODll
IVOD21
IAVOD21
IAVOD2AI
IVOD2AI
VOCM
IAVOCMI
0
1.5
1.5
Typ
Unit
5.5
Vdc
VCC
Vdc
12
Vdc
60
rnA
70
DC
Max
Unit
VCC
Vdc
Vdc
Vdc
mVdc
Vdc
mVdc
Vdc
mVdc
DRIVER CHARACTERISTICS
Output Voltage
Single Ended, 10 = 0
Differential, Open Circuit (10 = 0)
Differential, RL = 54 Q
Change in Differential Voltage (Note 1), RL = 54 Q
Differential, RL = 100 Q
Change in Differential Voltage (Note 1), RL = 100 Q
Common Mode Voltage, RL = 54 Q
Common Mode Voltage Change, RL = 54 Q
Output Current (Each Output)
Short Circuit Current, -7.0 V,;; VO';; 12 V
lOS
2.0
-
-
200
-
-
200
3.0
200
-250
-
250
-
0.8
rnA
Driver Data Inputs
Low Level Voltage
High Level Voltage
Clamp Voltage (lin = -18 rnA)
VILD
VIHD
VIKD
2.0
-1.5
-
Vdc
Thermal Shutdown Junction Temperature
TJTS
-
150
-
DC
-
mVdc
-
-
200
-200
-
0.36
100
1.0
VH
VOHR
VOLR
2.4
-
-
-
45
-
RECEIVER CHARACTERISTICS
Input Threshold
RO=High
RO = Low
Input Loading (Driver Disabled)
Hysteresis
Output Voltage
High (IOH = -400 1lA)
Low (IOL = 4.0 rnA)
Output Short Circuit Current
Output Leakage Current When in Three-State Mode
NOTE:
7-106
Vth
IOSR
10LKR
-
-
-
U.L.
mV
-
Vdc
0.4
85
20
rnA
IlA
1. Input swnched from low to high.
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
ELECTRICAL CHARACTERISTICS (continued) (TA
I
=25°C, VCC =5.0 V ± 10%)
I
Symbol
Min
Typ
Max
VILE
VIHE
VIKE
0
2.0
-1.5
-
0.8
VCC
ICC
-
18
28
VOHT
VOLT
2.4
0
-
-
0.8
Propagation Delay - Input to Single Ended Output
Input to Output - Low-to-High
Input to Output - Hlgh-to-Low
tpLH
tPHD
-
10
11
20
20
Propagation Delay - Input to Differential Output
Input Low-to-High
Input High-to-Low
tpLHD
tpHLD
15
15
23
23
tDR,tDF
-
9.0
10.7
tSKI
tSK2
tSK3
0
0
0
0.1
-
8.0
6.0
tSK7
tSK8
0
0.1
<4.0
-
Characterlatlc
Unit
MISCELLANEOUS
Enable Inputs
Low Level Voltage
High Level Voltage
Clamp Voltage (lin = -18 mAl
Vdc
Power Supply Current (Total Package, All Outputs Open, Enabled
or Disabled)
Thermal Shutdown Output VoHage
High
Low
-
mA
Vdc
TIMING CHARACTERISTICS - DRIVER
ns
ns
Differential Output Transition Time
Skew Timing
ItPLHD - tPHLDI for Each Driver
Maximum - Minimum tpLHD Within a Package
Maximum - Minimum tpHLD Within a Package
MC34058
Skew Timing
MC34059
ItPLHD - tPHLDI for Each Driver
Propagation Delay Difference Between Any Two Drivers (Same
Package or Different Packages at Same VCC and TA)
Enable Timing
Single Ended Outputs
Enable to Aciive High Output
Enable to Active Low Output
Active High to Disable
Active Low to Disable
Differential Outputs
Enable to Active Output
Enable to Three-State Output
ns
ns
ns
-
ns
tPZH
tPZL
tpHZ
tpLZ
-
15
25
12
10
40
40
25
25
tpZD
tPDZ
-
-
40
25
tpLHR
tpHLR
-
16
16
23
23
tSK4
tSK5
tSK6
0
0
0
1.0
-
3.0
3.0
tSK9
-
<5.0
-
TIMING CHARACTERISTICS - RECEIVER
Propagation Delay
Input to Output - Low-to-High
Input to Output - High-to-Low
Skew Timing
HpLHR - tpHLRI for Each Receiver
Maximum - Minimum tPLHR Within a Package
Maximum - Minimum tPHLR Within a Package
Skew Timing
Propagation Delay Difference Between Any Two Receivers in Different
Packages at Same V CC and TA (MC34059 Only)
Enable Timing
Single Ended Outputs
Enable to Active High Output
Enable to Active Low Output
Active High to Disable
Active Low to Disable
MOTOROLA ANALOG IC DEVICE DATA
ns
-
ns
ns
ns
tpZHR
tpZLR
tpHZR
tpLZR
-
-
15
25
12
10
22
30
25
25
7-107
MC34058 MC34059
Block DIagram and PInout
Gnd
RE6
016
Roe
DR5
RE5
DE5
Gnd
36 Gnd
Gnd
35 OA5
OA6
34 OBS
OB6
II
DE6
DR4
4
DR1
OA4
OA1
084
081
DE4
DE1
8
29 RE4
RE1
9
28 083
082
10
27 OA3
0A2
11
26 Gnd
Gnd 12
25 Gnd
Gnd
RE2
DR2
Vee
RE3
DE3
TSD
Gnd
PINOUT SUMMARY
Driver Enable, Active High (TTL)
OA
Nonlnverting Output/Input
DE
OB
Inverting Output/Input
RE
DR
Driver Input/Receiver Output (TTL)
TSD
016
#6 Driver Input (TTL)
VCC
Connect 4 Pins to 5.0 V, ± 10%
R06
#6 Receiver Output (TTL)
Gnd
Connect 12 Pins to Circuit Ground
7-108
Receiver Enable, Active Low (TTL)
Thermal Shutdown Indicator
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
Figure 1. VOD and VOS Test Circuit
Vee
Vin
(0.8 or 2.0 V)
Figure 2. VOD and VCM Test Circuit
Vee
375
Vin
(0.8 or 2.0 V)
58
375
I
veM
(+12 to ±7.0 V)
Figure 3. VOD AC Test Conditions
Vee
54
ro~
I
Vin
OV
Voo
OAl(
-=-
VOD
telr
-=-
telr
Figure 4. VOH and VOL AC Test Conditions
-
2.3 V
Vee
3.0V
Vin
OV
27
Output
I
-=-
-=-
15pF
3.0V
3.0V
3.0V
3.0V
OAX
OBX
VOL
VOH
-=-
MOTOROLA ANALOG IC DEVICE DATA
7-109
MC34058 MC34059
Figure 5. VOH versus IOH
4.6
4.4
~
4.2
:I:
-?
4.0
/
3.8
3.6
-80
V
/
Figure 6. VOL versus IOL
1.1
/
V
./
0.9
~
..J
/
0.8
V
>0
0.7
0.6
/
-60
./
1.0
-40
-20
20
/
/" "
10
20
./
30
40
50
Figure 7. VOD versus IOL
Figure 8. Input Characteristics of
OAX and OAB
0.4
II
~
0
-?
------
0.3
~
I
0.2
!z
0.1
~
0
OAXJin(mA)
~
~
-4.0
-50
o
~ -0.2
50
-0.3
100
IOO(mA)
Description
The MC34058/9 is a differential line driver designed to
comply with EIA-485 Standard for use in balanced digital
multipoint systems containing multiple drivers. The drivers
also comply with EIA-422-A and eelTT Recommendations
V.11 and X.27. Positive and negative current limiting of the
drivers meet the EIA-485 requirement for protection from
damage in the event that two or more drivers try to transmit
simultaneously on the same cable. Data rates in excess of
10 MBPS are possible, depending on the cable length and
cable characteristics. Only a single power supply, 5.0 V
± 10% is required.
Driver Inputs
The driver inputs and enable logic determine the state of
the outputs in accordance with Table 1. The driver inputs have
7-110
f
D..
~
-0.4
-10
,
~
80
1#
. / OBXJin(mA)
0
a -0.1
-2.0
-100
70
IOL(mA)
4.0
2.0
60
IOH(mA)
~
~
-5.0
"
o
5.0
10
15
INPUT VOLTAGE (V)
a nominal threshold of 1.2 V, and the voltage must be kept
within the range of 0 V to Vec for proper operation. If the
voltage is taken more than 0.5 V below ground or above Vec,
excessive currents will flow and proper operation of the
drivers will be affected. An open Pin is equivalent to a logic
high, but good design practices dictate that inputs should
never be left open. The inputs are TTL type and their
characteristics are unchanged by the state of the enable pins.
Driver Outputs
Each output (when active) will be a low or a high voltage,
depending on the input state and the load current (see
Tables 1, 2 and Figures 2 and 3). The graphs apply to each
driver, regardless of how many other drivers within the
package are supplying load current.
MOTOROLA ANALOG
IC DEVICE DATA
.
.
MC34058 MC34059
Table 1. Driver Truth Table
Enables
Outputs
Driver Data Inputs
DEX
REX
OAX
H
H
H
H
OBX
L
L
H
H
L
H
X
L
H
Z
Z
X
H
L
Not Defined
Not Defined
The outputs will be In a high impedance state when:
a) The Enable inputs are set according to Table 1;
b) The Junction temperature exceeds the trip point of the thermal shutdown circuit. When in this condition, the output's source and sink capability are shut off, and a
leakage current of less than 20 ~ will flow. Disabled outputs may be taken to any voltage between -7.0 V and 12 V without damage to Internal circuitry.
The drivers are protected from short circuits by two methods:
a) Current limiting is provided at each output, in both the source and sink direction, for shorts to any voltage w~hin the 12 Vto -7.0 V range, with respect to circuit
ground. The short circuit current will flow until the faun is removed, or until the thermal shutdown activates. The current limiting circuit has a negative temperature
ocefflcient and requires no resetting upon removal of the fauR condition.
b) A thermal shutdown circuit disables the outputs when the junction temperature reaches +150'C, ± 20'C. The thermal shutdown circuit has a hysteresis of - 12'C
to prevent oscillations. When this circuit activates, the output stage of each driver Is put into the high Impedance mode, thereby shutting ott the output currents.
However, the remainder of the internal circuitry remains biased and the outputs will become active once again as the IC cools down.
Receiver Inputs
The receiver inputs and enable logic determine the state of
the receiver outputs in accordance with Table 2. Each
receiver input pair has a nominal differential threshold of at
most 200 mV (Pin OAX with respect to OBX) and a common
mode voltage range of -7.0 V and 12 V must be maintained
for proper operation. A nominal hysteresis of 100 mV is
typical. The receiver input characteristics are shown in
Figure 8. When the inputs are in the high impedance state,
they remain capable of the common mode voltage range of
-7.0 V to 12 V.
Receiver Outputs
The receiver outputs are TTL type outputs and act in
accordance with Table 2.
Enable Logic
Each driver output is active when the Driver Enable input
is true according to Table 1. Each receiver output is active
when the Receiver Enable input is true according to Table 2.
The Enable inputs have a nominal threshold of 1.2 V and
their voltage must be kept within the range of 0 V and VCC for
proper operation. If the voltage is taken more than 0.5 V
below ground or above VCC, excessive currents will flow and
proper operation of the drivers will be affected. An open pin is
equivalent to a logic high, but good design practices dictate
that inputs should never be left open. The enable inputs are
TTL compatible. Since the same pins are used for driver input
and receiver output, care must be taken to make sure that
DEX and REX are not both enabled. This may result in
corruption of both the transmitted and received data.
Table 2. Receiver Truth Table
Receiver Data Inputs
Enables
Outputs
OAX-OBX
DEX
REX
DRX
:?:+200mV
L
L
H
S;-200mV
L
L
L
X
L
H
Z
X
H
L
Not Defined
APPLICATIONS
The MC34058/9 was designed to meet EIAlTIA-422 and
EIAlTIA-485 standards. EIAlTIA-422 specifies balanced
point-to-point transmission with the provision for multiple
receivers on the line. EIAlTIA-485 specifies balanced
point-to-point transmission and allows for multiple drivers
and receivers on the line. Refer to EIAITIA documents for
more details. Figure 9 shows a typical EIAlTIA-422 example.
Figure 10 shows a typical EIAlTIA-485 example.
Figure 9. Typical EIAlTIA-422 Application
[....""''------I--...--l-.-- - - - --I---4f'=+--l..--
MOTOROLA ANALOG IC DEVICE DATA
7-111
•
MC34058 MC34059
Figure 10. Typical EIAlTIA-485 Application
II
EIAlTIA-422 specifications require the ability to drive at
least 10 receivers of input impedance of greater than or equal
to 4.0 K(1 plus the 100 (1 termination resistor. This protocol
was intended for unidirectional transmission. EIAlTIA-485 is
capable of bidirectional transmission by allowing multiple
drivers and receivers on the same twisted pair segment. The
loading of the twisted pair segment can be up to 32 Unit
Loads (U.L.) plus the two 120 (1 terminating resistors. The
U.L. definition is shown in Figure 11.
where:
Oja package thermal resistance (see Appendix A)
TJmax =Maximum Junction Temperature. Since the
thermal shutdown feature has a trip point of 150°C ± 20°,
TJmax is selected to be +130°C.
TA Ambient Operating Temperature.
=
=
The power generated within the package is then;
PO" {[
Figure 11. TIAIEIA-485 Unit Load Definition
(vcc-
(,,,,,-dO,,"" ..
VOL' IOL }
6
Calculating Power Dissipation for the
MC3405819 Hex-Transceiver.
The operational temperature range is listed as O°C 10 70°C
to satisfy both EIAlTIA-485 and EIAlTIA-422 specifications.
However, a lower ambient temperature may be required
depending on the specific board layout and/or application.
Using a first order approximation for heat transfer, the
maximum power which may be dissipated by the package is
determined by (see Appendix A for more details);
PDmax =
7-112
TJmax-TA
Oja
6
VCH ,)' ICH,] + VOl,' lOLl} + ..
+ {[
(Vee -VOH,)' 10H,] +
+ VCC
. ICCQ
[2]
As indicated in the equation, the part of Equation 2
consisting of IOH , VOH ,IOL and VOL must be calculated for
each of the drivers and summed for the total power
dissipation estimate. The last term can be considered the
quiescent power required to keep the IC operational and is
measured with the drivers idle and unloaded. The VOH and
VOL terms can be determined from the output current
versus output voltage curves which provide driver output
characteristics.
Example 1 estimates thermal performance based on
current requirements.
[1]
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
Example 1. Balanced and Unbalanced Operation
IOL = 50 mA and IOH = ±50 mA for each driver. VCC = 5.0 V.
How many drivers can be used? (Typical power supply current ICCO
=18 mA.)
Solution:
.
ICCO 0.018 A
The quiescent power is given by: PO = ICCO' V CC ' and IS equal to PO = 0.09 W.
Balanced Operation:
Unbalanced Operation:
To determine the amount of power dissipated by each
To determine the amount of power dissipated by each
output stage we need to know the single-ended output
output stage we need to know the differential output voltage
for the output current required. Figure 7 shows that for IOH
voltage for the output current required. Figures 5 and 6
shows that for an IOH and IOL of ±50 mA,
and IOL differential of 50 mA, VOOH and VOOL are:
=
V OH = 3.9 V
VOO = 13.01, and IOL = "OHI = lOut = 0.050 A.
And the power dissipated by each driver is given by;
P OrvB = lOut' (VCC - V Oo ) and equal to
P OrvB = 0.10 W.
VOL = 0.895 V
And the power dissipated by each driver is calculated by;
)
P OrvU =
V OH . "OHI + VOL' IOL
and equal to
P OrvU = 0.10 W.
(vcc-
(For this example, balanced operation is assumed.)
Summing the quiescent and driver power for 6 transceivers operating in a package produces;
POTotal
=PO + 6·
POrvB, and equal to POTotal
=0.69 W.
For the MC34058/9, the thermal resistance is capable of a wide range. The ability of the package to dissipate power depends
on board type and temperature, layout and ambient temperature (see Appendix A). For the purposes of this example the
thermal resistance can range from 40°C/W to 100°C/W;
Sja = j, j = 40, 60, .. 100°C/W.
=
Varying the ambient operating temperature TA 25, 30, .. 85°C; specifying a maximum junction temperature to avoid
thermal shutdown TJmax 130°C; and using the first order approximation for maximum power. dissipation;
=
Pomax(Sja)' T A =
TJmax-TA
Sja
produces a set curves that can be used to determine a Safe Operating Area for the specific application. POTotal is graphed with
PO max to provide a reference.
Graph of Maximum Power Dissipation Possible
for a Particular Sja and Ambient Temperature
3.0,----,----.,,----,---,--...,----,--,
2.5f---==""""~-+--+---+--_t--+--_j
en
~
;:
2.0
1.51---+---'==-+-=--+--1-----''''''''..£--1----1
0.5 f--"'k---+----''k---t--_t=''''''"-t-oo-_j
PDTota!
30
40
70
80
90
• Safe Operating Area (SOA), is an operating power, PDTotal, less than PDmax.
So all the drivers in the package can be used if the thermal resistance and/or the ambient temperature is low enough.
MOTOROLA ANALOG IC DEVICE DATA
7-113
•
MC34058 MC34059
Appendix A. Optimizing the Thermal Performance of the MC3405819
Figure 12. Electrical Model of Package Heat Transfer
(Ieads-to-board) combination in Figure 12. This path
provides the most effective way of removing heat from the
device provided that there is a viable temperature potential
(Le. heat sinking source) to conduct towards. However, if it is
not properly considered in the system design, the other
paths, (Rjcd + Rcdb) and (Rjcu + Rca) attain greater
importance and must be more carefully considered.
So Equation 1, modified to reflect a more complete heat
transfer model becomes;
[Ria:;t.]
[2]
RJL
PDISS . Sja
ReDB
RLB
II
_
Board Temperature
An equivalent electrical circuit for the thermal model for the
MC3405819 package is shown in Figure 12. It is a simplified
model that shows the dominant means of heat transfer from
the thermally enhanced 48-ld package used for the
MC3405819. The model is a first order approximation and is
intended to emphasize the need to consider thermal issues
when designing the IC into any system. It is however
customary to use similar models and Equation 1 to estimate
device junction temperatures.
Equation 1 is the common means of using the thermal
resistance of a package to estimate junction temperature in a
particular system.
[1]
The term Sjx in Equation 1 is usually quoted as a 0ja value
in °ClWatt. However, since the 48-ld package for the
MC3405819 has been thermally enhanced to take advantage
of other heat sinking potentials, it must be modified. Sjx must
actually be considered a composite of all the heat transfer
paths from the Chip. That is, the three dominant and parallel
paths shown in Figure 12. Of those three paths, potentially
the most effective is the corner package leads. This is
because these corner leads have been attached to the flag
on which the silicon die is situated. These pins can be
connected to circuit board ground to provide a more efficient
conduction path for internal package heat. This path is
modeled as the Rjl (junction-to-Ieads) and Rib
7-114
where;
TJ= Junction Temperature
TA = Ambient Temperature
TS = Soard Temperature
PDISS = Device Power
and Sja = Total Thermal Resistance and is composed the
parallel combination of all the heat transfer paths from
the package.
While Equation 2 is still only a first order approximation of
the heat transfer paths of the MC34058/9, at least now it
includes consideration for the most effective heat transfer
path for the MC34058/9; the board to which the device is
soldered. The modified equation also better serves to
explain how external variables, namely the board and
ambient temperatur~s, affect the thermal performance of
the MC3405819.
Methods of removing heat via the flag connected pins can
be classified into two means; conduction and convection.
Radiation is omitted as the contribution is small compared to
the other means. Conduction is by far the best method to
draw heat away from the MC34058/9 package. This is best
accomplished by using a multilayer board with generous
ground plane. In this case, the flag connected pins can be
connected directly to the ground plane to maximize the heat
transfer from the package. Figure 13 shows the results of
thermal measurements of a board with an external ground
plane (the actual ground area was approximately 6 1/4 in2).
The thermal leads are connected to the board ground plane
per the recommended strategy.
MOTOROLA ANALOG IC DEVICE DATA
MC34058 MC34059
Figure 14A. Thermal Resistance (Sja) for
Board Without Ground Plane
Figure 13. Thermal Resistance (6ja) for Board
with Large External Ground Plane
120
55
110
50
1\
100
\
-r--r--
35
30
o
100
200
300
--
400
500
~
L
.,
~
90
,
~Radiators
80
70
"'" -
" ~ .....
~
~
Masked Radiators'
~
~~
80
Exposed Radiators'
50
600
AIR SPEED (LINEAR FTIMIN)
Sjc for the package on this board is 25 ± 20% depending on the location of
the package on the board.
o
200
400
600
----
800
1000
1200
AIR SPEED (LINEAR FTlMIN)
, Masked radiators were covered by a solder mask. Exposed radiators
were bare copper.
Figure 14B. Layout Used for Thermal Resistance
Measurements in Figure 14A
Figure 15. Placement of Thermal Vias to Enhance
Heat Transfer to Ground Plane
Figure 14A on the other hand shows the result of a single
layer board without an internal ground plane. The graphs
show that even though there are radiators of substantial area
surrounding the package, substantial degredation of thermal
performance is evident (Figure 14B shows the layout used
for the measurements in Figure 14A). Comparing Figures 13
and 14A shows almost a 2:1 improvement for the strategy
involving the external ground plane.
It is clear from Figures 13, 14A and Example 1, that if an
application is to use all the device drivers, preparations to
assure adequate thermal performance of the system must
be taken.
If an extensive external ground plane is unavailable, and
only an internal ground plane is available, the thermal
performance of the device can still be improved by providing
thermal vias to connect the radiators to the internal ground
plane. Figure 15 shows a proposed scheme for thermal vias
(contact board manufactures for specifics about the thermal
performance of their products and possible enhancements).
The thermal resistance for this structure on 1.0 oz. Copper
connecting each of the four radiators to an internal ground
plane and provide an estimated thermal resistance of
approximately 5.0°CIW. The vias used in the estimate had
80 mil diameters, on 100 mil centers and a 1.0 mil copper
thickness.
MOTOROLA ANALOG IC DEVICE DATA
7-115
•
®
MOTOROLA
MC34156
Product Preview
28-Channel Inkjet Driver
The MC34156 is a 28-Channel Decoder/Driver intended to be used in
inkjet printer applications. By using sophisticated SMARTMOSTM technology, it
has been possible to combine low power CMOS inputs and logic and high
current, high voltage bipolar outputs capable of sustaining a maximum of 30 V.
A 4-t0--14 line decoder determines the selected output driver (n) in each
14-driver bank. Two independent output enable inputs (active low) then
provide the final decoding to activate 1- or 2--of-28 outputs (OUTAn and/or
OUTBn). The ac electrical characteristics of the drivers are tightly controlled
and thereby the energy of the device delivers to the inkjet print head. A Chip
Enable function is provided to lock out the drivers during system power up.
The 28 bipolar power outputs are open collector 30 V Darlington drivers
capable of sinking 500 mA at ambient temperatures up to 70°C. All driver
outputs are capable of withstanding a contact discharge of ±8.0 kV with the
IC biased.
28-CHANNEL
INKJET DRIVER
(SMARTMOSTM Technology)
SEMICONDUCTOR
TECHNICAL DATA
• ESD Output Protection with Clamping Diodes
• Addressable Data Entry
• Tightly Controlled AC and Electrical Characteristics for Inkjet Printers
II
FNSUFFIX
PLASTIC PACKAGE
CASE 777
• CMOS, TTL Compatible Inputs
• Low Power CMOS Logic
ORDERING INFORMATION
DeVice
MC34156FN
Operating
Temperature Range
Package
TA=OOto+70°C
Plastic Package
PIN ASSIGNMENTS
Pin No.
1
2
3
4
Simplified Block Diagram
«
'"
.l!!
~
:::>
a
:fJ ~
Iii
~
I
Jj e
a;U)
~
c
~
0
~
'"
~
~
a;~
«
~
7
8
!
i
9
OUTAD
OUTA1
OUTB4
10
11
12
13
14
15
16
17
18
19
20
OUTA2
21
OUTAS
23
24
OUTA4
22
25
CUTB6
OUTA5
26
27
28
OUTB?
OUlA6
29
30
OUTBB
OUTA?
31
32
OUTB9
OUTA9
NIC
Gnd
33
34
35
36
37
38
39
Q
z
Q
z
0
i!!:::>
a
7-116
i!!'" Iii5'"'
:::>
a :::>
a a
Iii
I-
'" '"
ga ga a~
:::>
i '"
a0
40
41
42
43
44
Pin Name
IND
VDD
Gnd
ENB
Chip Enable
aUTSO
aUTB1
aUTB2
aUTB3
aUTB4
aUTB5
aUTB6
aUm7
aUTB8
aum9
GOd
NlC
N/C
NlC
aUTB10
aUTB11
aUTB12
aUTB13
aUTA13
aUTA12
aUTA11
aUTA10
COM
Gnd
aUTA9
aUTA8
aUTA7
aUTA6
aUTA5
aUTA4
aUTA3
aUTA2
aUTA1
aUTAD
ENA
INA
Gnd
INB
INC
Pin Description
4th Decoder Input
Power Supply
Ground
Enable Pin for B Set Drivers
Chip Enable
B Set 1st Driver
B Set 2nd Driver
B Set 3rd Driver
B Set 4th Driver
B Set 5th Driver
B Set 6th Driver
B Set 7th Driver
B Set 8th Driver
B Set 9th Driver
B Set 10th Driver
Ground
Not Connected
Not Connected
Not Connected
B Set 11th Driver
B Set 12th Driver
B Set 13th Driver
B Set t4th Driver
A Set 14th Driver
A Set 13th Driver
A Set 12th Driver
A Set 11th Driver
Common
Ground
A Set 10th Driver
A Set 9th Driver
A Set 8th Driver
A Set 7th Driver
A Set 6th Driver
A Set 5th Driver
A Set 4th Drrver
A Set 3rd Driver
A Set 2nd Driver
A Set 1st Driver
Enable Pin for A Set Drivers
1st Decoder Input
Ground
2nd Decoder Input
3rd Decoder Input
MOTOROLA ANALOG IC DEVICE DATA
MC34156
Figure 1. Functional Block Diagram
Output Enable A
OUTAO
OUTA1
Logic Supply 0
OUTA2
Chip Enable
G--------t--t-+---.
OUTA13
INA (LSB)
OUTBO
<;;
"0
INB
8
'"c:
INC
•
'"
Cl
OUTB1
:::i
iJ
OUTB2
INO(MSB)
Output Enable B
OUTB13
Figure 2. Output Driver Configuration
Figure 3. Typical Input Circuit
VOO
l·IOCOM
L.- - - - < 0
MOTOROLA ANALOG IC DEVICE DATA
OUT
7-117
®
MOTOROLA
MC34250
Product Preview
5.0 V, 200 M-Bit/Sec PR-IV
Hard Disk Drive Read Channel
The Motorola MC34250 is a fully integrated partial response maximum
likelihood disk drive read/write channel for use in zoned recording
applications. This device integrates the AGC, active filter, 7 tap equalizer,
Viterbi detector, frequency synthesizer, servo demodulator, 8/9 rate (0,4/4)
Encoder/Decoder with write precompensation and power management in a
single 64 pin 10 mm x 10 mm TQFP package.
HARD DISK DRIVE
READ CHANNEL
SEMICONDUCTOR
TECHNICAL DATA
FEATURES:
• 50 to 200 MBPS Programmable Data Rate
• 800 mW at 200 MBPS and 5.0 V
• Channel Monitor Output
• Programmable AGC Charge Pump Currents with Different Values for
Data and Servo Envelope Modes and Gain Gradient Mode
II
• Programmable AGC Peak Detector Droop Currents with Different
Values for Data and Servo Envelope Modes
• Separate AGC Charge Pump Outputs for Data and Servo Modes
• Programmable Dual Threshold Qualifier or Hysteresis Comparator Type
Pulse Detector for Servo Data Detection.
64
• ERD and Polarity Outputs for Servo Timing and Raw Encoded Data
• Integrated 7 pole 0.05° Equiripple Linear Phase Filter with
Programmable Bandwidth from 5.0 MHz to 80 MHz and Different Values
for Both Data and Servo Modes
• Programmable Symmetrical Boost from 0 to 10 dB and Different Values
for Data and Servo Modes
FTASUFFIX
PLASTIC PACKAGE
CASE 840F
(ThinOFP)
• Programmable Asymmetrical Boost of Up to ±40% of Nominal Filter
Group Delay in Both Data and Servo Modes
• 7 Tap Continuous Time Transversal Equalizer with 8 Bit Programmable
Tap Weights and Integrated Decision Directed Sign-8ign least Mean
Squared Adaptation
• Internal Offset Cancellation loops
• Fast Acquisition Data Phase locked loop with Zero Phase Restart
ORDERING INFORMATION
Device
MC34250FTA
Operating
Temperature Range
Package
TA=OOto+70°C
TOFP-64
• Programmable Data Phase locked loop Charge Pump Current
• Integrated Soft Decision Viterbi Detectors with Programmable Merge
References
• Integrated 8/9 Rate (0,4/4) Encoder and Decoder with Code Scrambler
and Descrambler
• Programmable 214/8 Bit NRZ Data Interface
• Programmable Write Precompensation Delays locked to the Frequency
Synthesizer
• Differential PECl Write Data Outputs
• External Write Data Path for DC Erase or Other Non-Encoded Data
• Integrated Write Current DAC
• Programmable Power Management
• Bi-Directional Serial Microprocessor Interface
• Various Test Modes Controlled Via the Serial Microprocessor Interface
7-118
MOTOROLA ANALOG IC DEVICE DATA
!!:
0
'" '" '" '"
:0 :n :n
;g~CJ)cna~~
en
a
'"c
.:f
(")
:D
en en
m
Z
jJ
§3
0
C
!i:
C3
r-
~~~~cc~
Eii1il~~~~~
jJ
~
-<
~
c
c
;:::
"
"-nr-r- "-nr-r-
)0
z)0
r0
C)
(';
,--L--L,
---
C
m
<
(';
m
CLAMPS
C
~
~
0
-i
:::r
oj"
Co
~.
0
Pulse Detector
I
++
r-t
I
I
H
I
Thresholds
Viterbi Detector
Path Memory
Viterbi Margin
VINP
VINM
(/)
CD
0
0
"~
"'"
0
"80
III
g,
<
CD
:
HOLDS
819 (0,414) ENDEC
Synchronization
SyteDetect
CDATA
CSRVO
SYNCDET
NRZ(7:0)
NRZCLK
READGT
WRITEGT
WRITECLK
g
~
C
;
3
CRI4Q
!il
r"I:IIT~
0
I
"'----~I
Power
Manager
~
I-
Write
Precompensetion
T T
Mode
~WDATAP
WDATAM
Coefficients
SLATCH
~I
CD
CD
CD
"!Il.!I!"
FREFU
3i
t:I.
iii"
SRVOGT
SLEEPS U
3"
"2-
I
~I
Fr~uency
Synt esizer
en
~ -<
z
:;!
=B
~
-n
;:::
~
ZoneClk
WCDAC
Data
MCU Interface
-~
z~::t: ~
'"
~
en
iiE
~
m
I
mSDATA
SCLK
s::
0
Co)
-'N="
UI
0
®
MOTOROI.A
MC68160
Enhanced Ethernet Transceiver
The MC68160 Enhanced Ethernet Interface Circuit is a BiCMOS device
which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE-T
Twisted Pair (TP) Interface media connections through external isolation
transformers. It encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via 10BASE-T or AUI
interfaces. The MC68160 gluelessly interfaces to the Ethernet controller
contained in the MC68360 Quad Integrated Communications Controller
(QUICC) device. The MC68160 also interfaces easily to most other
industry-standard IEEE 802.3 LAN controllers. Prior to twisted pair data
reception, Smart Squelch circuitry qualifies input signals for correct
amplitude, pulse width, and sequence requirements.
• Interfaces with AMD, National, Intel and Fujitsu IEEE 802.3 LAN Controllers
ENHANCED ETHERNET
INTERFACE TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
• Automatic Twisted Pair Wiring Polarity Fault Detection and Correction
Option
• Automatic Port Selection Option with Status Output
• Driver Pre-emphasis for Twisted Pair Output Data
52
• Crystal Controlled Clock Oscillator or External Clock Generator Option
II
• Digital Phase-Locked-Loop (DPLL) Timing Recovery and Data Decoding
FBSUFFIX
PLASTIC PACKAGE
CASE 848D
(ThinOFP)
• Standby Mode with Reduced Power Consumption
• Twisted Pair Signal Quality Error (Heartbeat) Test Option
• Diagnostic Local Loop Back Option
• Transmit, Receive and Collision Detection Status Output
ORDERING INFORMATION
• Full-Duplex Operation Option on Twisted Pair Port
• Twisted Pair Jabber Detection and Status Output
Device
• Link Integrity Testing and Status Output
MC68160FB
Operating
Temperature Range
Package
TA= 0 to +70°C
TOFP-52
0
Figure 1. 1DBase-T Interface Block Diagram
RX.-----------~~~8rl
RCLK
1+-------------1
ARX+'
MFILT _ - - - - - - - - - '
ARX-
RXLED==~~~~~~JL~~~Jr~
_ _ _ _ _~
RENA_
CLLED
1&1
CLSN
~TXLED
ACX+
ACX-
-;===;----.1'""""1
ATX-
m
TENA ~===~~nBrii:heSi6rl
i;
TX
~
1&1
ATX+
~
5c(
Xl
Twisted
Pair
Polarity
Error
Control
X2_---U~.J
TCLK_----I
CSO~
CSl
CS2
TPEN
APORT
TPAPCE
TPSOEL
TPFULDL
LOOP
1&1
~
II:
Mode
Select
TPJABB
TPTX+ TPTX-
TPLiL
TPSOEL
TPRX-
TPRX+ TPPLR
This device contains 20,000 active transistors.
7-120
MOTOROLA ANALOG IC DEVICE DATA
MC68160
Enhanced Ethernet Serial Transceiver
Table 1. Pin Descriptions .............................................................................. 7-122
Controller Interface Pins ................................................................................. 7-122
AUllnterface Pins ....................................................................................... 7-122
Twisted Pair Interface Pins ............................................................................... 7-122
Oscillator and Frequency Multiplier Pins .................................................................... 7-123
Mode Select Pins ....................................................................................... 7-123
Status Indicator Pins .................................................................................... 7-124
Power Supply and Ground Pins ........................................................................... 7-124
Table 2. Controller Interface Selection ................................................................. 7-125
Table 3. Controller Independent Mode Selection ...................................................... 7-125
Electrical Characteristics .............................................................................. 7-126
Maximum Ratings ....................................................................................... 7-126
Recommended Operating Conditions ...................................................................... 7-126
ESD ................................................................................................... 7-126
DC Characteristics .................................................................................... 7-126
Power Supply DC Characteristics ......................................................................... 7-126
TTUCMOS Input and Output DC Characteristics ............................................................ 7-127
Twisted Pair Input and Output DC Characteristics ........................................................... 7-127
AUllnput and Output DC Characteristics ................................................................... 7-128
AC Characteristics .................................................................................... 7-129
External Clock Input(X1) Switching Characteristics .......................................................... 7-129
Receive Phase Locked Loop Switching Characteristics ....................................................... 7-129
Controller Transmit Switching Characteristics (Motorola Mode) ................................................ 7-129
Controller Receive Switching Characteristics (Motorola Mode) ................................................. 7-129
Controller Transmit Switching Characteristics (Intel Mode) .................................................... 7-131
Controller Receive Switching Characteristics (Intel Mode) ..................................................... 7-131
Controller Transmit Switching Characteristics (Fujitsu Mode) .................................................. 7-132
Controller Receive Switching Characteristics (Fujitsu Mode) .................................................. 7-132
Controller Transmit Switching Characteristics (National Mode) ................................................. 7-133
Controller Receive Switching Characteristics (National Mode) ................................................. 7-133
TP Transmit SWitching Characteristics ..................................................................... 7-135
TP Transmit Jabber Switching Characteristics ............................................................... 7-137
TP Transmit Signal Quality Error Test Switching Characteristics ............................................... 7-137
TP Receive Switching Characteristics ...................................................................... 7-138
TP Receive Link Integrity Switching Characteristics .......................................................... 7-138
TP Collision Switching Characteristics ..................................................................... 7-140
TP Full Duplex Switching Characteristics ................................................................... 7-140
AUlTransmit Switching Characteristics .................................................................... 7-141
AUI Receive Switching Characteristics ..................................................................... 7-141
Functional Description ................................................................................ 7-142
Data Transmission ...................................................................................... 7-142
Data Reception ......................................................................................... 7-143
Collision ............................................................................................... 7-143
Jabber ................................................................................................. 7-143
Full Duplex ............................................................................................. 7-143
Auto Port Selection ...................................................................................... 7-143
Auto Polarity Selection ................................................................................... 7-143
Loop Back Mode ........................................................................................ 7-143
Applications ........................................................................................... 7-144
Selection of Crystal and External Components .............................................................. 7-144
PLL Filter Components .................................................................................. 7-144
10BASE-T Filter and Transformer Choice .................................................................. 7-144
AUI Transformer Choice ................................................................................. 7-144
MOTOROLA ANALOG IC DEVICE DATA
7-121
•
MC68160
Table 1. Pin Function Description
Pln(s)
Symbol
Type
Name/Function
CONTROLLER INTERFACE
1
0
RENA
TTUCMO
2
0
RX
TTUCMOS
48
0
TCLK
TTUCMOS
49
TENA
50
RCLK
I
TTL
0
TTUCMOS
51
0
CLSN
TTUCMOS
II
52
Receive Enable Output: Indication of the presence of network activity, synchronous to
RCLK. In the standby mode, RENA is driven to the high impedance state.
Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation,
100 ms should be allowed before attempting to read data processed by the MC68160. This
delay is needed to insure that the receive phase locked loop is properly synchronized with
Incoming data. In the standby mode, RX is driven to the high impedance state.
Transmit Clock Output CMOSITTL Output: TCLK provides a sYl'(lmetrical clock signal at
10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to
the high impedance state.
Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission
on the active port. An internal pull-down resistor is provided so that the input is low under no
connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at
the conclusion of a reset operation, it must first be deasserted and then reasserjed before
data transmission can occur. In the standby mode, TENA is driven to the high impedance'
state.
Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high
impedance state.
Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and
ACX- terminals which meet threshold and pulse width requirements. In the TP mode,
indicates simultaneous transmit and receive activity, a heartbeat (SQI:: Test) signal was
generated, or the jabber timer has expired. In the standby mode, CLSN is driven. tq the high.
impedance state.
TX
I
TTL
Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to
be Manchester encoded. In the standby mode, TX is driven to the high impedance state.
21
22
ACXACX+
I
AUI Differential Collision Inputs: These Inputs are connected to a pair of intemally biased
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity. Signals at ACX+/- have no effect on data path functions.
23
24
ARXARX+
I
AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased
line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to
detect the line activity, and a data receiver with no offset .for Manchester Data reception.
25
26
ATXATX+
0
AUIINTERFACE
AUI Differential Transmit Outputs: This line pair is intended to operate into terminated
transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is
previously asserted, Manchester encoded data is outputted at ATX+/-. When operating into a
78 Q terminated transmission line, signaling meets the required output levels and skew for
IEEE-802.3 drop cables. When the 10BASE-T port is automatically or manually selected,
the AUI outputs are driven to a low power standby state in which the outputs deliver a
balanced high state voltage.
TWISTED PAIR INTERFACE
31
32
TPRXTPRX+
I
Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with
Smart Squelch capability which only allows differential receive data to pass as long as the
input amplitude is greater than a minimum signal threshold level and a specific pulse
sequence is received. This assures a good signal to noise ratio while the signal pair is active
by preventing crosstalk and impulse noise conditions from activating the receive function.
36
37
TPTXTPTX+
0
TWisted Pair Differential Transmitter Outputs: These lines have pre-distortion drive
capability and are intended to drive terminated twisted pair transmission lines. When the AUI
port is manually selected, the 1OBASE-T outputs are driven to a low power standby state in
which the outputs deliver a balanced high state voltage. However, when the AUI port is
automatically selected, the 10BASE-Toutputs remain active.
NOTE:
7-122
The sense of the controiler interface pins will change, depending on the controiler selected.
MOTOROLA ANALOG IC DEVICE DATA
MC68160
Table 1. Pin Function Description (continued)
Pin(s)
Symbol
Type
Name/Function
OSCILLATOR AND FREQUENCY MULTIPLIER
12
MFILT
C
Frequency Multiplier Filter Connection Point: An extemal resistor capacitor filter must be
attached to this pin.
16
XI
I/C
CMOS
Oscillator Inverter Input and Crystal Connection Point: When connected for crystal
oscillator operation, the frequency of the clock which appears at TCLK is half that of the
crystal oscillator. As an option, instead of connecting to a crystal, XI may be driven from an
external 20 MHz CMOS compatible clock generator.
17
X2
O/C
Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the
connection of an extemal crystal and capacitor. It must be left unconnected if XI is driven by
an external CMOS Clock generator.
CMOS
MODE SELECT
3
4
5
CSO
CSI
CS2
I
TTL
Mode Select: The logic states applied to these pins select the appropriate interface for the
desired IEEE-802.3 controller or enable the standby mode. When the standby mode is
selected, the MC68160 power supply current is greatly reduced. Additionally, in the standby
mode, all of the controller inputs and outputs are driven to the high impedance state.
6
LOOP
I
TTL
Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be
Manchester encoded and then looped back through the Manchester decoder, appearing at
the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP)
or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI
port transmits data from the controller while diagnostic loopback is selected. Likewise, the
controller interface receives data neither from the TP nor the AUI receivers while in this
mode. The polarity fault detection and link integrity functions are not inhibited by the
diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair
port is selected, and TPSOEL is driven to the low logic state, a collision detect pulse is
delivered following each transmission to simulate the twisted pair SOE test.
9
APORT
I
TTL
Automatic Port Selection Enable: When high, MC68160 will automatically select the TP or
AUI port based on the presence or absence of valid link beats or frames at the TP receive
input. If the AUI port Is automatically selected, the MC68160 will continue to produce link
pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry
for the new port to resume normal operation. The power consumption is minimized in the
circuitry associated with the unselected port.
27
TPSOEL
I
TTL
Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the
internal TP collision detect circuitry after each transmit operation to the TP media. This
function provides a simulated collision to as much of the MC68160 collision detect circuitry
as possible without affecting the attached twisted pair channel. A normal SOE test results in
a high logic state at the CLSN controller interface pin which begins 6 to 16-bit times after the
last transition of a transmitted signal and continues for 5 to 15-bit times. (When the AUI port
is selected, SOE test signals are generated by the coaxial cable transceiver and delivered to
the controller via the MC68160 ACX+I- receive inputs)
28
TPFULDL
I
TTL
Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit
and receive operation on the twisted pair port without an indicated collision. This pin is not 10
be asserted with LOOP as a test mode is enabled that disrupts normal operation.
29
TPAPCE
I
TTL
Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic
polarity correction is enabled, and MC68160 will internally correct for a polarity fault on the
receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is
indicated on TPPLR.
46
TPEN
I/O
TTL
(TTUCMOS)
Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the
AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is
manually selected, the MC68160 will not produce link pulses for the TP port.
If APORT is high, TPEN is an output which will indicate which port has been automatically
selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink
10 mA in the low output state and source 10 mA in the high output state. (See Pin 9
Description.)
Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to
resume normal operation. The power consumption is minimized in the cirCUitry aSSOCiated
with the unselected port. In the standby mode, this pin is driven to the high impedance state.
MOTOROLA ANALOG Ie DEVICE DATA
7-123
•
MC68160
Table 1. Pin Function Description (continued)
Pln(s)
Symbol
Type
Name/Functlon
0
TraI'lsmH Status LED Driver Output: This pin indicates the transmit status of the currently
selected TP or AUI port. When there is no transmit activity detected, an internal pull-up takes
this pin to its normal off (high) state. When transmit activity is detected, the LED driver tums .
on. In its on state; TXLED flashes the'LED by driving low at approximately 10 Hz at a 50"k
duty cycle. In the standby mode, this output is driven to the high impedance state.
STATUS INDICATOR
40
TXLED
TTLJCMOS
"
41
RXLED
0
TTLJQMOS
42
CLLED
0
TTLJCMOS
43
TPLIL
0
TTLJCMOS
44
TPPLR
0
'TTLJCMOS
II
45
TPJABB
0
TTLJCMOS
Receive Status LED Driver Output: This pin indicates the receive status of the currently
selected TP or AUI port. When there is no receive activity detected, an internal pull-up takes
this pin to Its normal off (high) state. When receive activity is detected, the LED driver turns
on. In its on state, RXLED flashes the LED by driving low at approximately 10Hz at a 50%
duty cycle. In the standby mode, this output 'is driven til the high impedance state.
COllision Status LED Driver Output: This pin indicates the collision status of the currently
selected TP or AUI port. When there is no colliSion activity detected, an internal pull-up takes
this pin to its normal off (high) state. When collision activity is detected, the LED driver turns
on., In its on state, CLLED flashes the LED by driving low at approximately 10Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate
good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity
fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port
is selected. In the standby mode, this output is also driven to the high impedance state.
Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the
Twisted Pair Receiver Inputs (TPRX+, TPRX-) are reversed, TPPLR will be driven to the low
logic state to Indicate the fault. TPPLR remains low when the MC68160 has automatically
corrected for the reversed wires. If the twisted pair link integrity tests fail, this output will be
driven to,the high logic state. When the AUI mode is selected this output is driven to the high
Impedance state, In the standby mode, this output is also driven to the high impedance state.
Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the
TPTX+/- outputs. (Jabber condition also causes CLLED to be driven alternately to the high
and low output levels). TPJABB is driven to the low output state when no jabber condition is
present.When the AUl"mode is selected this output is driven to the high impedance state. In
the standby mode, this output is also driven to the high impedance state.
POWER SUPPLY AND GROUND
10
VDDDIV
Frequency D,lvlder Supply Pin
11
Frequency Multiplier Supply and Ground Pins
13
VDDFM
GNDFM
14
15
GNDVCO
VDDVCO
Voltage Controlled Osciliator Ground and Supply Pins
20
GNDSUB
SubStrate Ground Pin
7
8
18
19
VDDDIG'
GNDDIG
VDDDIG
GNDDIG
Digital Supply and Ground Pins
SO'
VDDANA
GNDANA
Analog Supply and ,Ground Pins
GNDPWR
VDDPWR
VDDPWR
GNDPWR
Power Supply and Ground Pins
GNDCTL
Controller Interface Ground Pin
33
34
35
38
39
47
NOTE:
7-124
Power and ground pins are not connected internally. Failure to connect externally may cause maHunction or damage to the IC.
MOTOROLA ANALOG IC DEVICE DATA
MC68160
Table 2. Controller Interface Selection
Motorola
Transceiver
MC68160
(EES'fT")
Motorola
Controller2
MC68360
(QUICCT")
Intel
Controllers
82586, 82590,
82593, 82596
CSO
CS1
CS2
1
1
0
0
FuJltau
Controllers
86950 (EtherstarT")
86960 (NICETM)
National
Controllers
8390, 83C690,
839328 (SONICTM)
0
1
1
0
0
0
0
0
Pin
Pin
Sense
Pin
Sense
Pin
Sense
Pin
Sense
TCLK
TX
TENA
RCLK
RX
RENA
CLSN
LOOp1
TCLK
TX
TENA
RCLK
RX
RENA
CLSN
N.A.
High
TXC
TXD
RTS
RXC
RXD
CRS
COT
LPBK
Low
TCKN
TXD
TEN
RCN
RXD
XCD
XCOL
LBC
Low
TXC
TXD
TXE
RXC
RXD
CRS
COL
LPBK
High
High
High
High
High
High
High
High
High
Low
Low
High
Low
Low
Low
High
High
Low
High
High
Low
High
High
High
High
High
High
High
High
NOTES: 1. Atthough LOOP input is not ordinarily classlfed as a controller pin, ~ is included in this table because Its sense varies according to the controller used.
2. The Motorola controller Interface contained In the MC68360 (QUICCT") is compatible with the AMD 7990 (LANCer") and 79C900 (ILACC™) controllers.
3. The pin sense is shown from the perspective of the ldentHied controller pin.
Table 3. Controller Independent Mode Selection
Pin
Standby Mode
Reserved
Reserved
Reserved
CSO
CS1
CS2
1
1
1
0
1
1
1
0
1
0
0
1
NOTE: In standby mode, the MC6S160 consumes less power supply current than in any other
mode. Additionally, in the standby mode, all of the controller inputs and outputs are
driven to the high impedance state. When the standby mode is deasserted, an internal
reset pulse of approximately 6.0 liS duration is generated.
Following a period of operation in the standby mode, the time required to insure stable
data reception is approximately 100 ms.
Figure 2. Applications Block Diagram
d~
"
e
,J'f"'~
w
... ' ,.
~
TENA
LAN
Controller
~
-
,...
~;
TCLK
TX
ATX+
,.
•
,
,
,
RX
,-
.-
RENA
CLSN
. . ,.
~
ATX+
ATX-
-""
ARX+
~
Pulse
Transformers
ARXACX+
.,
;
~
ACX-
-
ARX+
ARX-
D8-15
Connector
ACX+
ACX-
,
,
.
"
TPTX+ ...
TPTX+ ...
~
.*
TPTX~
i
"
"
.'
MOTOROLA ANALOG IC DEVICE DATA
ATX-
:">*
"~
RCLK
,
TPRX+
TPRX-
Filters
and
Pulse
Transformers
TPTXTPRX+
RJ-45
Connector
TPRX-
7-125
•
MC68160
ELECTRICAL CHARACTERISTl~S
MAXIMUM RATINGS
Symbol
Min
Max
Unit
Storage Temperature Range
Tstg
-65
150
°C
Power Supply Voltage Range
Analog
Digital
VDDA
VDDD
-
7.0
7.0
V
V
-0.5
VDD+0.5
V
-0.5
6.0
-6.0
6.0
Characteristic
..
Voltage on any TIL compatible Input'pin with
respect to Ground
Voltage on TPRX, ARX, or ACX input pins with
respect to Ground
Differential Voltage on TPRX, ARX, or ACX Input
Pins
VDIFF
V
NOTE: Stresses In excess 01 the Absolute Maximum Ratings can cause permanent damage to the
device. Functional operation 01 the device is not implied at these or any other conditions In
excess 01 those Indicated In the operation sections of this data sheet. Exposure to Absolute
Maximum Ratings conditions lor extended periods can adversely affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Min
Max
VDD
4.75
5.25
V
-
50
mV
Power Supply Impulse Noise (Either Polarity)
-
100
mV
Ambient Operating Temperature Range
TA
0
70
°C
ARXlACX Input Differential Rise and Fall Time (see Figure 39)
t260
2.0
10
ns
ARX Pair Idle Time after Transmission (see Figura 39)
t265
8.0
-
j.IS
Power Supply Voltage Range
•
Power Supply Ripple (20 kHz to 100 kHz)
Unit
ESD
Although protection circuitry has bean designed Into this device, proper precautions sh6uld be taken to avoid exposure to electrostatic discharge
(ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD-susceptibillty
testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance 1500 Q capacltance100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold, presented here was obtained by using
the circuit parameters contained in this speCification. ESD threshold VOltage Is designed to 1.0 kV Human Body Model.
=
DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended
ambient operating temperature and power supply voltage ranges.)
Characteristic
Symbol
Teet Conditions
-
-
POWER SUPPLY
Undervoltage Shutdown Threshold
Power Supply Current
IDD
--
Standby Mode
7-126
-
-
-
4.4
V
145
200
5.0
mA
-
MOTOROLA ANALOG IC DEVICE DATA
MC68160
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum limits apply
over the recommended ambient operating temperature and power supply voltage ranges.)
I
Characteristic
I
Symbol
I
Test Conditions
Min
Max
-
0.8
Unit
TTL COMPATIBLE INPUTS
TTL Compatible Input Voltage
Low State
High State
Input Current TTL Compatible Input Pins (Note 1)
Input Current TENA TTL Compatible Input Pin:
with Pull-Down Resistor
IIH
IlL
with Pull-Down Resistor removed in Standby Mode
VIL(TTL)
VIH(TTL)
OV 25 ns.
4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair.
5. If a positive differential pulse occurs on either the AUI receive data or collision pair> 175 ns, end of frame is assumed and squelch circuitry is turned on.
Figure 39. ARXlACX Timing
ARX+/ACX+/-
Differential
Input Voltage
MOTOROLA ANALOG IC DEVICE DATA
J-f
+17SmV
- - - - -17SmV
t261/ t262
7-141
MC68160
Figure 40. ARXlACX Timing
BitolZ
I
BitU
I
BitW
BitV
I
BitX
I BitY I BitZ
ARX+/-I
ACX+/Differential
Input Voltage
1+---- t267 ---~
1.5V
1.5V
RCLK
II
\'-----
RX
I BitOlZ I
BW
I Bit V I
BitU
I BitX
BitY
I
BitZ
I
FUNCTIONAL DESCRIPTION
Introduction
The MC68160(EEST) was designed to perform the
physical connection to the Ethernet media. This is done
through two separate media dependent interfaces and aSIA
interface. The media dependent interfaces are the
Attachment Unit Interface(AUI) and the 10BASE-T Twisted
Pair(TP) port. The SIA interface is compatible with most
industry controllers and selected by three mode control pins.
Chip status is indicated by the condition of 6 status indicator
pins. All but one are open collector outputs.
If the EEST isn't receiving data, the controller may initiate
transmission. NRZ data from the communications controller
SIA interface is encoded by the MC68160 into Manchester
Code in preparation for transmission on the media. The data
is then applied to either the AUI or TP port. If the data was
transmitted using the 10BASE-T port, this data is also
looped back to the receive data interface SIA pins
connected to the controller. This allows detection of a
collision condition in the event that another station on the
media attempted transmission at the same time. After the
entire data frame has been transmitted, the EEST must
force the media idle signal. The idle signal frees the media
for other stations that have deferred transmission. If no
other transmissions are required the link enters an idle
state. During this idle state the 10BASE-T transmitter
issues idle pulses which communicates to the receiver
connected to the other side that the link is valid. If the
7-142
transmitter connected at the other end begins transmission,
the EEST will assert a receive enable signal, and forward
the received data to the controller.
Upon reception of data at the 10BASE-T port, the data is
screened for proper sequence and pulse width requirements.
If the preamble of the received frame meets the
requirements, the PLL locks onto the 64-bit preamble and
begins to decode the Manchester Code to NRZ code. This
code is then presented to the communications controller at
the receive data pins at the SIA interface. If data is received
at the AUI port, it is sent directly to the communications
controller via the SIA interface.
Data Transmission
To have properly encoded transmit data, the communications controller must be synchronized to TCLK.
Transmission to the 10BASE-T or AUI media occurs when
TENA is asserted and data is applied to the TX pin. Finally, to
signify transmission, the TXLED in will cycle on and off at a
100 ms period. Data transmission for EEST is accomplished
either over the 10BASE-T port or the AUI port. Both
connections to the media are made with industry standard
media interface components. The 10BASE-T interface
requires a filter and transformer, the AUI interface requires
only a transformer. The filter for the 1OBASE-T transmit
circuit will have to be chosen for each application.
MOTOROLA ANALOG IC DEVICE DATA
MC68160
If after approximately 40 ms after a TP or AUI transmission
has begun, the EEST is still transmitting, the TPJABB pin will
assert to signify a jabber condition. Also, the CLLED pin will
transition high and low alternately with a 100 ms period. The
transmit circuitry is, however, unaffected by the jabber
condition, so the communications controller has the
responsibility of monitoring and stopping transmission.
When transmission is complete, the transmit circuitry will
begin the end of transmit and decay to idle responses
necessary to meet requirements of the 802.3 standard for the
TP and AUI port.
Data Reception
Other than the case of being in Loop Back mode, data
reception to the RX pin of the EEST is initiated by signaling at
the RX+/- or AUI ARX+/- pins. If at the TP port, the data is
screened for validity by checking for sequence and pulse
width requirements, then passed to the decode and receive
circuitry. The RENA pin asserts and the data and
corresponding clock is passed to the communications
controller. After the frame has been transmitted, the
MC68160 detects the ending transmission and negates
RENA. If at the AUI port, the data is checked for proper pulse
width requirements before being passed to the decode
circuitry. If the data pulses are longer than at least 20 ns,
RENA gets asserted and the frame is decoded to RX with
and accompanying RCLK output.
Collision
Collision is the occurrence of simultaneous transmit
activity by two or more stations on the network. In the event of
collision, the data transfer paths are unaffected. If the
MC68160 is in the twisted pair mode, collision is detect by
simultaneous receive and transmit activity. If in the AUI
mode, collision is detected by activity on the ACX+/- pins. In
either case, if collision is detected, the CLSN pin will assert to
notify the communications controller.
MOTOROLA ANALOG IC DEVICE DATA
Jabber
The EEST has a jabber timer to detect the jabber condition.
In the event that the transmitting station continues to transmit
beyond the allowable transmit time, a jabber timer (40 ms) will
expire and assert the TPJABB pin to alert the communications
controller of the situation. The TPJABB pin can source or sink
up to 10 mA, and so, is capable of driving a status LED. In the
AUI mode, the pin is driven to high impedance since the
transceiver connected to the AUI port must alert the
communications controller of the jabber condition.
Full Duplex
A feature unique to the MC68160 is the Full Duplex mode.
In this mode the EEST is capable of transmitting and
receiving simultaneously. Collision conditions are not
announced and internal loop back is disabled. The remainder
of the EEST functionality remains unchanged from the
non-Full Duplex mode. Full Duplex mode is enabled by
asserting the TPFULDL pin.
Auto Port Selection
If the APORT pin is asserted, the MC68160 will
automatically select the TP or AUI port depending on the
presence of valid link beats or frames at the TP RX+/- pins. If
the AUI port is automatically selected by another transmitting
station or by setting TPEN low, the TP transmit port of the
EEST continues to transmit link beats to keep the link active.
Auto Polarity Selection
If the RX+ and the RX- wires happen to get reversed, the
MC68160 has the ability to automatically reverse the pins
intemally so that the received data is valid. In addition, an open
collector status pin (TPPLR) is driven low to indicate the fault.
In the AUI or reset mode this pin presents a high impedance.
Loop Back Mode
To test the transmit and receive circuitry without disturbing
the connected network, the EEST has a Loop Back mode.
Loop Back mode routes transmit data and clock to the
receive data and clock pins using as much of the transmit and
receive cirCUitry as possible. This gives a test of the
MC68160 Manchester encode and decode function.
7-143
MC68160
APPLICATIONS INFORMATION
Selection of Crystal and External Components
Accuracy of frequency and stability over temperature are
the main determinants of crystal choice. Specifications for a
.
suitable crystal are tabulated below:
·Frequency
20. > C5)
7-144
MOTOROLA ANALOG IC DEVICE DATA
Figure 41, Typical Application Diagram
3:
a
Voo
A
:u
o
~
»
z
»
TCLK . " Transmit Clock.
COMMUNICATIONS
CONTROLLER
6
MC68360
TENA :... Transmit Enable
:... Transmit Data
CLSN :.. Collision Int
RCLK
R NA
(;
~
::s
o
m
c
~
»
AM0(7990J79C900)
Intel (825" -86190193J96)
Fujitsu (869" -50160)
National (8390183C90183932B)
+S,QV
LE06
R33
330n
TX
Ii)
c
m
n~
_TPEN" TP En""lo_
l\iE05
R8
330n
l\iED4~lEo3 ~lE02 ~
Rg
330n
R11
330n
R13
330n
f
01
R14
330n
~
~
Valor (PT3877. PT3882. FU 012. FU (86)
TOKO (PM01. PM02. PMOS)
Pulse Engineenng (pE-55433. PE-65434. PE-65424)
i
~
1
!ll.
MC68160FB
RJ45
--==8...
Y=!
o
~
.....
TPFULOL
TPSOa 27
Power Supply
Bypassing
h,,,,
~
III
1O~FH
eoncraft (LAX-ET30')
Pulse Engineering (pE-64"'*)
Communications Controller Selection
h""
cso
CS1
CS2
802.3 Communication Controtler
Motorola MC68360. AMD 7990 & 79C900
Intel 8258S. 62500. 82593. 82596
Fujitsu MB86960. MB66960
O.1~F
0-
R4
39n
R5
D~ 39n
AS
National 8390, 83C690, 839328
Standby Low Current Mode
0'1~fl39n
D2
-::-
!
+12V
Valor (LT600'ILT603')
TOKO (Q3OALQ'-1AA3)
TPFULDL
TPAPCE
10~FH
s::
i"'L-----ji;>VCC
A7
39n
-::-
AUI
1. For SuilBble CryslBl (Xl) see applications text on previous page.
2. Oecoupling capacitors should be placed as close to supply pins as possible.
t;
_~JI
___________
-L
®
MOTOROLA
Quad EIA-485 Line Drivers
with Three.;.State Outputs
The Motorola MC75172B/174B Quad Line drivers are differential high
speed drivers designed to comply with the EIA-485 Standard. Features
include three-state outputs, thermal shutdown, and output current limiting in
both directions. These devices also comply with EIA-422-A, and CCITT
Recommendations V.ll and X.27.
The MC75172B/1748 are optimized for balanced multipoint bus
transmission at rates in excess of 10 MBPS. The outputs feature wide
common mode voltage range, making them suitable for party line
applications in noisy environments. The current limit and thermal shutdown
features protect the devices from line fault conditions. These devices offer
optimum performance when used with the MC75173 and MC75175 line
receivers.
Both devices are available in 16-pin plastic DIP and 20-pin wide body
surface mount packages.
• Meets EIA-485 Standard for Party Line Operation
MC75172B
MC75174B
QUAD EIA-485 LINE DRIVERS
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
PLASTIC PACKAGE
CASE 648
• Meets EIA-422-A and CCITT Recommendations V.ll and X.27
II
• Operating Ambient Temperature: -4O°C to +85°C
DWSUFFIX
PLASTIC PACKAGE
CASE751D
(SO-20L)
• High Impedance Outputs
• Common Mode Output Voltage Range: -7 to 12 V
• Positive and Negative Current Limiting
• Transmission Rates in Excess of 10 MBPS .
• Thermal Shutdown at 150°C Junction Temperature, (±20°C)
• Single 5.0 V Supply
• Pin Compatible with TI SN7517214 and NS ~9617214
• Interchangeable with MC3487 and AM26LS31 for EIA-422-A
Applications
ORDERING INFORMATION
Device
Operating
Temperature Range
MC75172BDW
MC75174BDW
Package
So-20L
TA = -40° to +85°C
MC75174BP
So-20L
Plastic DIP
PIN CONNECTIONS
MC75172B
MC75174B
OW Package
7-146
OW Package
MOTOROLA ANALOG IC DEVICE .DATA
MC75172B MC75174B
MAXIMUM RATINGS
Rating
Power Supply Voltage
Symbol
Value
VCC
-0.5, +7.0
Vdc
Yin
+7.0
Vdc
Input Voltage (Data, Enable)
Input Current (Data, Enable)
Unit
lin
-24
mA
Applied Output Voltage, when in 3-State Condition
(VCC=5.0V)
Vza
-10,+14
Vdc
Applied Output Voltage, when VCC = 0 V
Vzb
±14
10
Self-Umiting
-
Tstg
-65,+150
'c
Output Current
Storage Temperature
Devices should not be operated at these limits. The "Recommended Operating Condijions" table provides
for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
VCC
+4.75
+5.0
+5.25
Vdc
Input Voltage (All Inputs)
Yin
0
-
VCC
Vdc
Output Voltage in 3-State Condition, or when VCC = 0 V
Vcm
-7.0
-
+12
Vdc
Output Current (Normal data transmission)
10
-65
-
+65
mA
Operating Ambient Temperature (see text)
EIA-485
EIA-422
TA
-40
0
-
+85
+85
'c
Alilimijs are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (-40'C '" TA '" 85°C, 4.75 V '" VCC '" 5.25 V, unless otherwise noted.)
Characteristic
Output Voltage
Single-Ended Voltage
10=0
High @ 10 = -33 mA
Low@ 10 = +33 mA
Differential Voltage
Open Circuit (10 = 0)
RL = 54 n (Figure 1)
Change in Differential', RL = 54 n (Figure 1)
Differential Voltage, RL = 100 n (Figure 1)
Change in Differential', RL = 100 n (Figure 1)
Differential Voltage, -7.0 V'" Vcm '" 12 V (Figure 2)
Change in Differential', -7.0 V'" Vem '" 12 V (Figure 2)
Offset Voltage, RL = 54 n (Figure 1)
Change in Offset', RL = 54 n (Figure 1)
Output Current (Each Output)
Power Off Leakage, VCC = 0, -7.0 V '" Vo '" 12 V
Leakage in 3-State Mode, -7.0 V '" Vo '" 12 V
Short Circuit Current to Ground
Short Circuit Current, -7.0 V '" Vo '" 12 V
Symbol
Min
Typ
Max
Vo
VOH
VOL
0
-
-
6.0
-
4.0
1.6
-
IVODll
IVOD2 I
1.5
1.5
3.4
2.3
6.0
5.0
-
5.0
2.2
5.0
200
Unit
Vdc
-
mVdc
Vdc
mVdc
Vde
mVdc
Vdc
mVde
laVOD21
IVOD2A I
IaVOD2A I
IVOD3 I
laVOD31
VOS
lavosl
1.5
-
5.0
2.9
5.0
10(off)
10Z
-50
-50
0
0
+50
+50
jlA
10SR
lOS
-150
-250
-
+150
+250
mA
-
-
-
-
200
5.0
200
-
200
'Vin switched from 0.8 to 2.0 V.
Typical values determined at 25'C ambient and 5.0 V supply.
MOTOROLA ANALOG IC DEVICE DATA
7-147
MC75172B MC75174B
ELECTRICAL CHARACTERISTICS (-40°C " TA" 85°C, 4.75 V" VCC " 5.25 V, unless otherwise noted.)
Characteristics
Inputs
low level Voltage (Pins 4 & 12, MC75174B only)
low level Voltage (All Other Pins)
High level Voltage (All Inputs)
=2.7 V (All Inputs)
=0.5 V (All Inputs)
Clamp Voltage (All Inputs, lin =-18 mAl
Current @ Vin
Current @ Vin
Thermal Shutdown Junction Temperature
Power Supply Current (Outputs Open, VCC
Outputs Enable
Outputs Disabled
=5.25 V)
Symbol
Min
Vll(A)
Vll(B)
VIH
0
0
2.0
-
Typ
-
Max
Vdc
0.7
0.8
Vec
0.2
-15
20
IIH
III
-100
VIK
-1.5
-
-
Tjts
-
+150
-
ICC
UnH
-
ItA
Vdc
°c
mA
-
60
30
70
40
Min
Typ
Max
-
23
18
30
30
-
15
17
25
25
-
19
25
TIMING CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Characteristics
Propagation Delay - Input to Single-ended Output (Figure 3)
Output low-to-High
Output High-to-low
•
Propagation Delay -Input to Differential Output (Figure 4)
Input low-to-High
Input High-to-low
Differential Output Transition lime (Figure 4)
Skew liming
ItplHD - tPHlD I for Each Driver
Max - Min tplHD Within a Package
Max - Min tpHlD Within a Package
Enable liming
Single-ended Outputs (Figure 5)
Enable to Active High Output
Enable to Active low Output
Active High to Disable (using Enable)
Active low to Disable (using Enable)
Enable to Active High Output (MC75172B only)
Enable to Active low Output (MC75172B only)
Active High to Disable (using Enable, MC75172B only)
Active low to Disable (using Enable, MC75172B only)
Differential Outputs (Figure 6)
Enable to Active Output
Enable to Active Output (MC75172B only)
Enable to 3-Sta.te Output
Enable to 3-State Output (MC75172B only)
7-148
Symbol
tPlH
tpHl
tPlH(D)
tpHl(D)
tdr, Idf
tsK1
tSK2
tSK3
-
-
Unit
ns
ns
0.2
1.5
1.5
-
ns
ns
-
ns
tpZH(E)
tpZl(E)
tPHZ(E)
tPLZ(E)
tpZH(E)
tPZl(E)
tpHZ(E)
tPLZ(E)
tpZD(E)
tpZD(E)
tPDZ(E)
tPDZ(E)
-
-
-
-
-
-
-
48
20
35
30
58
28
38
36
60
30
45
50
70
35
50
50
47
56
32
40
-
ns
-
MOTOROLA ANALOG IC DEVICE DATA
MC75172B MC75174B
Figure 1. VDD Measurement
Figure 2. Common Mode Test
t
Vin
(0.8 or 2.0 V)
Vin
(0.8 or 2.0 V)
VOD3
375
-=-+ VCM=12to-7.0V
58
I
375
~
Figure 3. Propagation Delay, Single-Ended Outputs
3.0 V
1.5V
OV
tpHL
270
Output
:r
3.0 V
3.0V
15PF
VOL
IpLH
VOH
3.0V
3.0 V
Figure 4. Propagation Delay, Differential Outputs
3.0 V
1.SV
OV
tPHLD
1.5V
=4.6V
let!
NOTES: 1. S.G. set to: f .. 1.0 MHz; duty cycle = 50%; to tf... 5.0 ns.
2. tSK1 = ItPLHD - tpHLD I for each driver.
3. tSK2 computed by subtracting the shortest tpLHD from the longest tpLHD of the 4 drivers wKhln a package.
4. tSK3 computed by subtracting the shortest tpHLD from the longest tpHLD of the 4 drivers within a package.
MOTOROLA ANALOG IC DEVICE DATA
7-149
•
MC75172B MC75174B.
. Figure 5. Enable Timing, Single-Ended Outputs
,_.------------..3.0 V
Vee
1.SV
'----OV
r------------------,,.~--VOH
Vout
O.SV
2.3V
Vee
Vee
3.0V
1.SV
l.SV
Oor3.0V
SOPF
II
r
ov
tPZL(E)
Vout
tPLZ(E)
Vout
2.3V
O.SV
vOL
':-
Figure 6. Enable Timing, Differential Outputs
3.0V
50pF
1.SV
t
OV
tpDZE
vr
1.SV
0
':-
Active
NOTES: 1. S.G. sel 10: f " 1.0 MHz; duly cycle = 50%; If, If, " 5.0 ns.
2. Vin is inverted for 'Eila6Te measurements.
7-150
MOTOROLA ANALOG IC DEVICE DATA
MC75172B MC75174B
Figure 7. Single-Ended Output Voltage
versus Output Sink Current
Figure 8. Single-Ended Output Voltage
versus Temperature
2.0
2.0
~
w 1.5
C!l
!:i
-
V
g~
IOL =20.0mA
to; 1.5
..:.
~
0.5
o
-j
o
10
4.75
I
20
30
40
50
IOL, OUTPUT CURRENT (mA)
60
1.0
-40
70
Figure 9. Single-Ended Output Voltage
versus Output Source Current
5.0
w
~
~
4.0
IOH = -20.0 mA
~
w
C!l
;:;
3.75
~
to;
a.
to;
3.5
'-'
VCC = 4.75 V
3.0
0
±
~ 2.0
1.0
IOH - -27.8 mA
±
~
TA=25'C
o
-10
-20
-30
-40
-50
IOH, OUTPUT CURRENT (mA)
-60
VCC=4.75V
3.25
-70
-40
Figure 11. Output Differential Voltage
versus Load Current
~
S
3.
-
O~" ~
"
§ 2.OVCC = 5.0 V -./
~
a:
w
tI: 1.0
c
c
~
r0
0
20
40
60
TAo AMBIENTTEMPERATURE (OC)
85
~ 4.0
I'....
;:;
~
-20
Figure 12. Output Differential Voltage
versus Temperature
4. 0
w
C!l
85
J.
4.0
.... VCC=5.00V
g
a
20
40
60
0
TA, AMBIENT TEMPERATURE ('C)
Vee = 5.25 V
;:;
a.
-20
'" VCC '" 5.25 V
Figure 10. Single-Ended Output
Voltage versus Temperature
C!l
I::>
r--r---
1.25
4.75V '" VCC '" 5.25 V _
TA = 25'C
~
10L =21.8mA
§
§
..:.
--
I--
C!l
~
to; 1.0
~
-- :------I-
>
W 1.75
o
tll
;:;
;::::::r-r-- r-- :::--r--::: t _VCC = 5.25 V
VCC=4.75 V
I
-
~~~ ~ol Voo
I
10
I
I
20
30
40
50
10, OUTPUT CURRENT (mA)
MOTOROLA ANALOG IC DEVICE DATA
r--
~
~
3!
ic
tl:
TA = 25°C
c
~
60
70
3.0
10-20.0mA
10 = 27.8 mA
-
2.0
1.0
o
1
I-- 0.8 or ~o
2.0V 1
L
-40
-20
Voo
I
VCC=4.75V -
T
0
20
40
60
TAo AMBIENT TEMPERATURE (OC)
85
7-151
MC75172B MC75174B
Figure 13. Output Leakage Current
versus Output Voltage
Figure 14. Output Leakage Current
versus Temperature
2.0
«
~
20
«
1.0
!z
w
:E
i3
w
15
~
t-
i
10
:::>
5.0
~
0
0
~
~-1.0
Ri-l0
TA=25'e_
En = low, En = High -
I
-2.0
-7.0
I
><
(
-3.0
1.0
5.0
9.0
Vz, APPLIED OUTPUT VOLTAGE (V)
-20
-40
12
1
o
60
85
~
(
-25
-0.5
/"
Normally low Output
a:
a:
y
~ -10
<.:>
7-152
0
20
40
TA, AMBIENT TEMPERATURE ('C)
~ 90
Enable( (Driver
Pins
Inputs
!l!
-20
-20
150
~-5.0
~
r-
IrVee=o~
Figure 16. Short Circuit Current
versus Common Mode Voltage
5.0
~ -15
En = low, En = High
S? -15
r-
Figure 15. Input Current
versus Input Voltage
«::l
-
Voul=7.0V
US -5.0
-'
S?
II
-
Voul=+12 V
<.:>
w
:::::J
30
<.:>
t-
I
I
I
~
0
5-30
V
Ii::
4.75 .. vee .. 5.25 V
TA=25'e
~
I
en. -90
.J
1l
0.5
1.5
2.5
3.5
Yin, INPUT VOlTAGE (V)
4.5
5.5
-150
-7.0
-3.0
/
..I
I
r
Normally High Output
TA = 25'e
4.75 .. vee .. 5.25 V
1.0
5.0
9.0
VZ, APPLIED OUTPUT VOLTAGE (V)
12
MOTOROLA ANALOG IC DEVICE DATA
MC75172B MC75174B
APPLICATIONS INFORMATION
Description
The MC75172B and MC75174B are differential line drivers
designed to comply with EIA-485 Standard (April 1983) for
use in balanced digital multipoint systems containing multiple
drivers. The drivers also comply with EIA-422-A and CCITT
Recommendations V.ll and X.27. The drivers meet the
EIA-485 requirement for protection from damage in the event
that two or more drivers attempt to transmit data
simultaneoulsy on the same cable. Data rates in excess of 10
MBPS are possible, depending on the cable length and cable
characteristics. A single power supply, 5.0 V, ±5%, is required
at a nominal current of 60 mA, plus load currents.
Outputs
Each output (when active) will be a low or a high voltage,
which depends on the input state and the load current (see
Table 1,2 and Figures 7 to 10). The graphs apply to each
driver, regardless of how many other drivers within the
package are supplying load current.
Table 1 MC75172B Truth Table
Enables
Outputs
Data Input
EN
EN
Y
Z
H
L
H
L
X
H
H
X
X
L
X
X
L
L
H
H
L
H
L
Z
L
H
L
H
Z
Table 2 MC75174B Truth Table
Outputs
Data Input
Enable
y
Z
H
L
H
H
L
H
L
Z
L
H
Z
X
H = Logic high, L = Logic low, X = Irrelevant, Z = High impedance
The two outputs of a driver are always complementary. A
"high" output can only source current out, while a "low" output
can only sink current (except for short circuit current - see
Figure 16).
The outputs will be in the high impedance mode when:
a) the Enable inputs are set according to Table 1 or 2;
b) VCC is less than 1.5 V;
c) the junction temperature exceeds the trip point of the
thermal shutdown circuit (see below). When in this
condition, the output's source and sink capability are
shut off, and only leakage currents will flow (see
Figures 13, 14). Disabled outputs may be taken to any
voltage between -7.0 V and 12 V without damage.
MOTOROLA ANALOG IC DEVICE DATA
The drivers are protected from short circuits by two
methods:
a) Current limiting is provided at each output, in both the
source and sink direction, for shorts to any voltage
within the range of 12V to-7.0V, with respect to circuit
ground (see Figure 16). The short circuit current will flow
until the fault is removed, or until the thermal shutdown
circuit activates (see below). The current limiting circuit
has a negative temperature coefficient and requires no
resetting upon removal of the fault condition.
b) A thermal shutdown circuit disables the outputs when
the junction temperature reaches 150°C, ±20°C. The
thermal shutdown circuit has a hysteresis of ~ 12°C to
prevent oscillations. When this circuit activates, the
output stage of each driver is put into the high
impedance mode, thereby shutting off the output
currents. The remainder of the internal circuitry remains
biased. The outputs will become active once again as
the IC cools down.
Driver Inputs
The driver inputs determine the state of the outputs in
accordance with Tables 1 and 2. The driver inputs have a
nominal threshold of 1.2 V, and their voltage must be kept
within the range of 0 V to VCC for proper operation. If the
voltage is taken more than 0.5 V below ground, excessive
currents will flow, and proper operation of the drivers will be
affected. An open pin is equivalent to a logic high, but good
design practices dictate that inputs should never be left open.
The characteristics of the driver inputs are shown in Figure
15. This graph is not affected by the state of the Enable pins.
Enable Logic
Each driver's outputs are active when the Enable inputs
(Pins 4 and 12) are true according to Tables 1 and 2.
The Enable inputs have a nominal threshold of 1.2 V and
their voltage must be kept within the range of 0 V to VCC for
proper operation. If the voltage is taken more than 0.5 V
below ground, excessive currents will flow, and proper
operation of the drivers will be affected. An open pin is
equivalent to a logic high, but good design practices dictate
that inputs should never be left open. The Enable input
characteristics are shown in Figure 15.
Operating Temperature Range
The minimum ambient operating temperature is listed as
-40°C to meet EIA-485 specifications, and O°C to meet
EIA-422-A specifications. The higher VOD required by
EIA-422-A is the reason for the narrower temperature range.
7-153
•
MC75172B MC75174B
The maximum ambient operating temperature (applicable
to both EIA-485 and EIA-422-A) is listed as 85°C. However,
a lower ambient may be required depending on system use
(i.e. specifically how many drivers within a package are used)
and at what current levels they are operating. The maximum
power which may be dissipated within the package is
determined by:
.
TJmax-TA
PO max = -"'R~'--!..!
aJA
where:
reducing the load current, reducing the ambient temperature,
and/or providing a heat sink.
System Requirements
EIA-485 requires each driver to be capable of transmitting
data differentially to at least 32 unit loads, plus an equivalent
DC termination resistance of 60n, over a common mode
voltage of -7.0 to 12 V. A unit load (U.L.), as defined by
EIA-485, is shown in Figure 17.
Figure 17. Unit Load Definition
RaJA = package thermal resistance (typical
70°C/Wfor the DIP package, 85°CIW for SOIC
package);
TJmax = max. operating junction
temperature, and
TA = ambient temperature.
Since the thermal shutdown feature has a trip point of
150°C, ±20°C, TJmax is selected to be 130°C. The power
dissipated within the package is calculated from:
PO
where:
II
= {[(VCC - VOH) • IOHl + VOL • IOL)) each driver
+ (VCC·ICC)
VCC = the supply voltage;
VOH, VOL are measured or estimated from
Figures 7 to 10;
ICC = the quiescent power supply current
(typical 60 mAl.
As indicated in the equation, the first term (in brackets)
must be calculated and summed for each of the four drivers,
while the last term is common to the entire package.
Example 1: TA = 25°C, IOL = IOH = 55 mA for each driver,
VCC = 5.0 V, DIP package. How many drivers per package
can be used?
Maximum allowable power dissipation is:
Since the power supply current of 60 mA dissipates
300 mW, that leaves 1.2 W (1.5 W - 0.3 W) for the drivers.
From Figures 7 and 9, VOL = 1.75 V, and VOH =3.85 V. The
power dissipated in each driver is:
{(5.0 - 3.85) • 0.055} + (1.75 • 0.055) = 160 mW.
Since each driver dissipates 160 mW, the four drivers per
package could be used in this application
Example2:TA=85°C, IOL=27.8mA, IOH=20mAforeach
driver, Vce = 5.0 V; SOIC package. How many drivers per
package can be used?
Maximum allowable power dissipation is:
PO max =
130°C - 85°C
85 0 C/W
=
0.53 W
Since the power supply current of 60 mA dissipates
300 mW, that leaves 230 mW (530 mW - 300 mW) for the
drivers. From Figures 8 and 10 (adjusted for VCC = 5.0 V),
VOL = 1.38 V, and VOH = 4.27 V. The power dissipated in
each driver is:
{(5.0 - 4.27) • 0.020} + (1.38 • 0.0278) = 53 mW
Reprinted from EIA-485, Electronic Industries Association,
Washington,DC.
A load current within the shaded regions represents an
impedance of less than one U.L., while a load current of a
magnitude outside the shaded area is greater than one U.L.
A system's total load is the sum of the unit load equivalents
of each receiver's input current, and each disabled driver's
output leakage current. The 60n termination resistance
mentioned above allows for two 120n terminating resistors.
Using the EIA-485 requirements (worst case limits), and
the graphs of Figures 7 and 9, it can be determined that the
maximum current an MC751728 or MC751748 driver will
source or sink is =65 mAo
System Example
An example of a typical EIA-485 system is shown in
Figure 18. In this example, it is assumed each receiver's input
characteristics correspond to 1.0 U.L. as defined in Figure 17.
Each "off' driver, with a maximum leakage of ±50 ~ over the
common mode range, presents a load of =0.06 U.L. The
total load for the active driver is therefore 8.3 unit loads, plus
the parallel combination of the two terminating resistors
(60n). It is up to the system software to control the driver
Enable pins to ensure that only one driver is active at any
time.
Termination Resistors
Transmission line theory states that, in order to preserve
the shape and integrity of a waveform traveling along a cable,
the cable must be terminated in an impedance equal to its
characteristic impedance. In a system such as that depicted
in Figure 18, in which data can travel in both directions, both
physical ends of the cable must be terminated. Stubs, leading
to each receiver and driver, should be as short as possible.
Leaving off the terminations will generally result in
reflections which can have amplitudes of several volts above
VCC or below ground. These overshoots and undershoots
can disrupt the driver and/or receiver operation, create false
data, and in some cases damage components on the bus.
Since each driver dissipates 53 mW, the use of all four
drivers in a package would be marginal. Options include
7-154
MOTOROLA:ANALOG IC DEVICE DATA
MC75172B MC75174B
Figure 18. Typical EIA-485 System
m
TTL
TTL
5 "oW' drivers (@ 0.06 U.L. each),
+8 receivers (@ 1.0 U.L. each) = 8.3 Unit Loads
AT = 120 Q at each end of the cable.
120Q
Twisted
Pair
TTL
TTL
TTL
•
TTL
TTL
TTL
TTL TTL
NOTES: 1. Tenninaling resistors RT must be located at the physical ends of the cable.
2. Stubs should be as short as possible.
3. Circuit ground of all drivers and receivers must be connected via a dedicated wire within the cable.
Do not rely on chassis ground or power line ground.
MOTOROLA ANALOG IC DEVICE DATA
7-155
MC75172B MC75174B
Comparing System Requirements
Characteristic
EIA-422-A
EIA-485
V.11 and X.27
GENERATOR (DRIVER)
Output Impedance (Note 1)
Open Circuit Voltage
Differential
Single-Ended
lout
VOCD
VOCS
Loaded Differential Voltage
VOD
Differential Vo~age Balance
aVOD
Not Specified
<100 0
50101000
1.5t06.0V
<6.0V
';;6.0V
';;6.0V
.;; 6.0 V, w/3.9 ko, Load
.;; 6.0 V, w/3.9 kCl, Load
1.5 to 5.0 V, w/54 0 load
.. 2.0 V or .. 0.5
VOCD, w/l00 0 load
.. 2.0 V or .. 0.5 VOCD,
wl100 0 load
< 200 mV
.;;400mV
<400mV
Not Specified
Output Common Mode Range
VCM
-7.0to+12V
Not Specified
Offset Vo~ge
VOS
-1.0 < VOS < 3.0V
';;3.0V
';;3.0V
<200mV
.;; 400 mV
<400mV
.;; 250 rnA for-7.0 to
12 V
.;; 150 mA to ground
.;; 150 mA to ground
Offset Vo~ge Balance
Short Circuit Current
aVos
lOS
Leakage Current (VCC = 0)
10LK
Not Specified
.;; 100!1A to -0.25 V
thru 6.0 V
.;; l00!1A to ± 0.25 V
Output RiselFail Time (Note 2)
t r, tf
.;; 0.3 TB, w/54 011150 pF
load
.;; 0.1 TBor.;; 20 ns,
w/l000 load
';;0.1 TBor.;; 20ns,
w/l00oload
Vth
±300mV
RECEIVER
II
Input Sensitivity
±200mV
± 200 mV
Input Bias Voltage
Vbias
';;3.0V
';;3.0V
';;3.0V
Input Common Mode Range
Vcm
-7.0 to 12 V
-7.0 to 7.0V
-7.0t07.0V
Dynamic Input Impedance
Rin
Spec number of U.L.
.. 4kD
.. 4kD
NOTES: I. Compliance with V.II and X.27 (Blue book) output impedance requires extemal resistors in series with the outputs of the MC75172B and MC75174B.
2. T B = Bittime.
Additional Information
Copies of the EIA Recommendations (EIA-485 and EIA-422-A) can be obtained from the Electronics Industries Association,
Washington, D.C. (202-457-4966). Copies of the CCITT Recommendations (V.11 and X.27) can be obtained from the United
States Department of Commerce,Springfield, VA (703-487-4600).
7-156
MOTOROLA ANALOG Ie DEVICE DATA
®
MOTOROLA
SN75175
Quad EIA-485 Line Receiver
The Motorola SN75175 is a monolithic quad differential line receiver with
three-state outputs. It is designed specifically to meet the requirements of
EIA-485, EIA-422A123A Standards and CCITT recommendations.
The device is optimized for balanced multipoint bus transmission at rates
up to 10 megabits per second. It also features high input impedance, input
hysteresis for increased noise immunity, and input sensitivity of ±200 mV
over a common mode input voltage range of -12 V to 12 V. The SN75175 is
designed for optimum performance when used with the SN75172 or
SN75174 quad differential line drivers.
• Meets EIA Standards EIA-422A and EIA-423A, EIA-485
QUAD EIA-485
LINE RECEIVER WITH
THREE-STATE OUTPUTS
SEMICONDUCTOR
TECHNICAL DATA
• Meets CCITT Recommendations V.1 0, V.11, X.26, and X.27
• Designed for Multipoint Transmission on Long Bus Lines in Noisy
Environments
NSUFFIX
PLASTIC PACKAGE
CASE 648
• 3-State Outputs
• Common-Mode Input Voltage Range ... -12 V to 12 V
•
• Input Sensitivity ... ±200 mV
• Input Hysteresis ... 50 mV Typ
• High Input Impedance ... 1 EIA-485 Unit Load
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
• Operates from Single 5.0 V Supply
• Lower Power Requirements
• Plug-In Replacement for MC3486
This device contains 174 active transistors.
PIN CONNECTIONS
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vee
Power Supply Voltage
VCC
7.0
Vdc
Input Common Mode Voltage
VICM
±25
Vdc
VID
±25
Vdc
Three-State Control Input Voltage
VI
7.0
Vdc
Control
Output Sink Current
10
50
rnA
Output
Tstg
-65 to +150
°c
Input Differential Voltage
Storage Temperature
}
Output
In~um
A
3-State
Output
B
Ale
3-State
Control
e
BIO
Output
Operating Junction Temperature
NOTE:
TJ
+150
°c
D
ESD data available upon request.
Gnd
(Top View)
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Value
Un"
VCC
4.75 to 5.25
Vdc
TA
Oto+70
°c
Input Common Mode Voltage Range
VICM
-12to+12
Vdc
Input Differential Voltage Range
VIDR
-12 to +12
Vdc
Power Supply Voltage
Operating Ambient Temperature
MOTOROLA ANALOG IC DEVICE DATA
ORDERING INFORMATION
Device
SN75175N
SN75175D
Operating
Temperature Range
TA = 0 to +70°C
Package
Plastic DIP
S0-16
7-157
SN75175
ELECTRICAL CHARACTERISTICS (Unless otherwise noted; minimum and maximum limits apply over recommended temperature and
power supply voltage ranges. Typical values are forTA = 25°C, VCC 5.0 V, and VICM 0 V, Note 1.)
=
Characteristic
Differential Input Threshold Voltage (Note 2)
(-12 V .. VICM .. 12 V, VIH = 2.0 V)
(10 = -0.4 mA, VOH ~ 2.7 V)
(10 = 16 mA, VOL" 0.5 V)
Input Hysteresis
•
=
Symbol
Min
Typ
Max
Unit
V
VTH(D)
-
-
VT+-VT-
Input Une Current (Differential Inputs)
(Unmeasured Input at 0 V, Note 3)
(VI = 12V)
(VI =-7.0 V)
II
Input Resistance (Note 4)
ri
-
0.2
-0.2
50
-
mV
mA
-
-
1.0
-0.8
1 Unit
Load
-
-
Input Balance and Output Level (Note 3)
(-12 V .. VICM .. 12 V, VIH = 2.0 V)
(10 = -0.4 mA, VID = 0.2 V)
(10 = 8.0 mA, VID = -0.2 V)
(10 = 16 mA, VID = -0.2 V)
VOH
VOL
VOL
2.7
Input Voltage - High Logic State (Three-State Control)
VIH
2.0
Input Voltage - Low Logic State (Three-8tate Control)
VIL
-
Input Current - Higli L~gic State (Three-State Control)
(VIH=2.7V)
(VIH=5.5V)
IIH
Input Current - Low Logic State (Three-State Control)
(VIL = 0.4 V)
IlL
Input Clamp Diode Voltage (Three-State Control)
(11K = -18 rnA)
VIK
Output Third State Leakage current
(VI(D) = 3.0 V, VIL = 0.8 V, Va = 0.4 V)
(VI (D) = -3.0 V, VIL = 0.8 V, Va = 2.4 V)
10Z
Output Short-Circuit Current (Note 5)
(VI(D) = 3.0 V, VIH = 2,.0 V, Va = 0 V)
Power Supply Current (VIL = 0 V) (All Inputs Grounded)
V
-
-
-
-
0.45
0.5
-
V
ItA
-
-
V
0.8
20
100
-
-
-100
itA
-
-
-1.5
V
-
-
-20
20
lOS
-15
-
-as
mA
ICC
-
-
70
rnA
ItA
NOTES: 1. All cwrents into device pins are shown as positive, out of device pins are negative. All voltages referenced to ground unless otherwise noted.
2. Differential input threshold voltage and guaranteed output levels are done simultaneously for worst case.
3. Refer to EIA-485 for exact conditions. Input balance and guaranteed output levels are done simultaneously for worst case.
4. Input resistance should be derived from input line current specifications and is shown for reference only. See EIA-485 and input line current
specifications for more specific input resistance information.
5. Only one output at a time should be shorted.
SWITCHING CHARACTERISTICS (Unless otherwise noted, VCC = 5.0 V and TA = 25°C.)
Characteristic
Propagation Delay Time - Differential Inputs to Output
Output High to Low
OutP\lt LOVY to High
Propagation Delay Time - Three-State Control to Output
Output Low to Third State
Output High to Third State
Output Third State to High
Output Third State to Low
7-158
Symbol
Min
Typ
Max
tPHL(D)
tPLH(D)
-
25
25
35
35
-
16
19
11
11
35
35
30
30
Unit
ns
tpLZ
tpHZ
tpZH
tpZL
-
-
ns
MOTOROLA ANALOG IC DEVICE DATA
SN75175
FUNCTION TABLE (EACH RECEIVER)
Differential Inputs
3-State
Control
Output
y
VID~2.0V
'-{).2 V 1.0
2.0
1.0
o
o
-140
~O
-100
-20
0
20
60
100
1
VID =0.2 V
Load = 8.0 kn to Gnd
TA = 25°C
140
o
0.5
1.0
1.5
2.0
2.5
3.0
VI. 3-STATE CONTROL VOLTAGE (V)
VID, DIFFERENTIAL INPUT VOLTAGE (mV)
Figure 5. High Level Output Voltage
versus Output Current
~
UJ
CJ
!:i
5.0
4.0
t:":""'\
§2
I-
:::>
5
~
3.0
0
1--\~ VCC = 5.25 V
~
1
jjj 2.0
-'
:J:
1.0
-9
o
o
4.0
§2
3.5
~O
3.0
2.5
'-'
~
ffi
/
~
~.::, 0.1
-9
-10
-15
-20
-25
-30
-35
IOH, HIGH LEVEL OUTPUT CURRENT (rnA)
V
0.2
o
-40
~
o
/
Vcc = 5.0 V
f-TA = 25°C
5.0
10
15
20
25
30
35
40
IOL, LOW LEVEL OUTPUT CURRENT (rnA)
Figure 8. Low Level Output Voltage
versus Temperature
Figure 7. High Level Output VoHage
versus Temperature
5.0
~
UJ 4.5
~
UJ
/
./
0.3
0
.~ ~
-5.0
§2
-'
~'\.
:f:
,
./
~
!j 0.4
5
4.0
Figure 6. Low Level Output Voltage
versus Out I)ut Current
0.5
UJ
!5
~ ~ VCC = 5.0 V
~
VCC=4.75V~ ~
-'
UJ
~
VID=0.2V
TA = 25°C f - -
3.5
0.5
~
UJ
~ 0.4
~
~
0.3
~
0.2
~
-'
0.1
§
VCC=5.0V _
IOH = 400 IJA
2.0
r--
1.5
:E 1.0
:f:
-9 0.5
.::,
-9
o
10
20
30
40
50
60
70
80
TA, FREE AIR TEMPERATURE (0C)
MOTOROLA ANALOG IC DEVICE DATA
90
100
o
VCC=5.0V _
f--IOL= 16 rnA
o
10
20
30
40
50
60
70
80
lA, FREE AIR TEMPERATURE (0C)
90
100
7-161
®
MOTOROLA
ULN2068
Quad 1.5 A Sinking High
Current Switch
The ULN2068 is a high-voltage, high-current quad Darlington switch array
designed for high current loads, both resistive and reactive, up to 300 W.
It is intended for interfacing between low level (TTL, DTL, LS and 5.0 V
CMOS) logic families and peripheral loads such as relays, solenoids, de and
stepping motors, multiplexer LED and incandescent displays, heaters, or other
high voltage, high current loads.
The Motorola ULN2068 is specified with minimum guaranteed breakdown
of 50 V and is 100% tested for safe area using an inductive load. It includes
integral transient suppression diodes. Use of a predriver stage reduces inpl.\t
current while still allowing the device to switch 1.5 Amps.
It is supplied in an improved 1&-Pin plastic DIP package with heat sink
contact tabs (Pins 4, 5,12 and 13). A copper alloy lead frame allows maximu
power dissipation using standard cooling techniques. The use of the co
tab lead frame facilitates attachment of a DIP heat sink while permi
use of standard layout and mounting practices.
• TTL, DTL, LS, CMOS Compatible Inputs
QUAD 1.5 A
DARLINGTON SWITCH
• 1.5 A Maximum Output Current
II
BSUFFIX
PLASTIC PACKAGE
CASE 648C
• Low Input Current
• Internal Freewheeling Clamp Diodes
• 100% Inductive Load Tested
• Heat Tab Copper Alloy Lead Frame for I
=
MAXIMUM RATINGS (TA 25'C and rati
package, unless otherwise noted)
PIN CONNECTIONS
Rating
Unit
Output Voltage
V
Input Voltage (Note 1)
15
V
Supply Voltage
10
V
Collector Current (Note 2)
IC
1.75
A
Input Current (Note 3) .
II
25
mA
Oto+70
Tstg
-55 to +150
'c
'c
'c
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature
150
NOTES: 1. Input voltage referenced to ground.
2. Allowable output conditions shown in Figures 11 and 12.
3. May be limited by max input voltage.
Partial Schematic
Vs
.--.......- -......OC
.....*-+-OK
Bo-.,.....WIr--f
ORDERING INFORMATION·
Device
ULN2068B
Operating
Temperature Range
Package
Plastic DIP
'Other options of this ULN2060/2070 series are available
for volume applications. Contact your local Motorola Sales
Representative.
7-162
MOTORQLA ANALoG IC DEVICE DATA
ULN2068
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
Characteristic
Symbol
Output Leakage Current (Figure 1)
(VCE=50V)
(VCE = 50 V, TA = 70°C)
Min
Typ
Max
Unit
ICEX
100
500
Collector-Emitter Saturation Voltage (Figure 2)
V
VCE(sat)
1.13
1.25
1.40
1.60
(lC=5oomA}
(IC=750mA
V· =24V)
(lC= 1.0A
In·
(IC= 1.25A
Input Current - On Condition (Figure 4)
(VI=2.4V)
(VI = 3.75 V)
I'(on)
Input Voltage - On Condition (Figure 5)
(VCE = 2.0 V, IC = 1.5 A)
VI(on)
mA
0.25
1.0
V
2.4
Inductive Load Test (Figure 3)
(VS = 5.5 V, VCC = 24.5 V,
tPW=4.0ms)
mV
100
Supply Current (Figure 8)
(IC = 500 mA, Yin = 2.4 V, Vs = 5.5 V)
6.0
mA
Turn-On Delay Time
(50% E, to 50% EO)
1.0
Turn-Ofl Delay Time
(50% E, to 50% EO)
4.0
Clamp Diode Leakage Current (Figure 6)
(VR = 50 V)
(VR = 50 V, TA = 70°C)
100
Clamp Diode Forward Voltage (Figure 7)
(IF = 1.0A)
(IF = 1.5A)
1.75
2.0
Ils
50
V
Figure 2.
Open
Open
1
Figure 4.
Figure 3.
Vs
.....------0--0
vee
200
70MH
Open
I ,14m.
V~
1
Vout
~I--""--o Open
2
INPUT CURRENT (mA)
4.0
Figure 12. TA = 70°C wlStaver V-8
Heat Sink (37.SoCIW)
f
t
Device limit
~\
I'"
"- ""'r-....
..........
r
...........
~ r-!.
",4
L
o
o
7-164
.............
r-!.
Number of
outputs conducting
simul~aneourlY
20
40
60
DUTY CYCLE (%)
80
"-
'" ""'"
Il.cr:
Wcr:
a 1.0
;:cr:
r--- r-
r-:: t- r--
DeviceLimij
"" :s: 1.5
r--.... ~~
~
-
I---
100
~~
I
.Y~ 0.5
...
~mberof
l---"
..........
4"'-
t'.....
1
.........
r-.... 3 ~
r--..... r-- r--
.
I-outputs conducting
--r-
r-~
r---
simultaneously
o
o
20
40
80
DUTY CYCLE ('10)
80
100
MOTOROLA ANALOG.IC DEVICE DATA
ULN2068
Figure 13. TA = 70°C w/Staver V-7
Heat Sink (27.5°CIW)
•
Device Limit
"
~4
~ '"-
outputs conducting
simuitaneory
20
--- ----
"'- ....... ............ .......... 2
"'- r-.... K ....... -....-.
~mberof
Lo
o
Figure 14. TA
40
60
1
= 50°C w/o Heat Sink
'"' ~ 1.51--+....-+-~+..r--+~-+--+-+-~1-""'il
L5!z
Il. W
~~
!i¥
a 1.0 1--+--'
;;:ex:
9f2
;;!frl
!Jgu 0.5
80
80
DUTY CYCLE ('!o)
100
DUTY CYCLE ('!o)
Figure 16. TA = 50°C wlStaver V-7
Heat Sink (27.5°CIW)
'"' ~ 1.5 I--+--+--~~~~
'"' ~1.5
Il.
Il.
L5!zW
~~
!i¥
a 1.0 1--+--+-+---'
i5~
;;i@
9
g 0.5 I---+--+-+--rt-
u
°0~~-~2~0-~-4~0-~~~--'---8~0---'-~100·
DUTY CYCLE ('!o)
MOTOROLA ANALOG IC DEVICE DATA
f' Device Limtt
"
L5!zW
wex:
...Jex:
!li!
a 1.0
;;:ex:
~§
/
All Types
<.>
a: 400
J
a:
a:
=>
a: 400
~
8
/
-'
-'
200
.9
....V
a
/
All Types
<.>
:;
§w
a
1
~ 600
/
!z
w
8
Figure 9. Output Current versus
Input Current
/
/
200
.9
/
./
0.5
1.0
1.5
VCE(sat). SATURATION VOLTAGE (V)
2.0
./
V
200
,/
400
600
liN. INPUT CURRENT (1lA)
800
Input Characteristics
Figure 11. ULN28041nput Current
versus Input Voltage
Figure 10. ULN28031nput Current
versus Input Voltage
2.0
2.0
,../'
/
.......
a
2.0
/'
2.5
...- ,../'
,,/
3.0
1 1.5
V
!z
w
a:
a:
V
=>
<.> 1.0
~
~
~
3.5
4.0
4.5
VIN. INPUT VOLTAGE (V)
5.0
5.5
6.0
0.5
l..--'
V
a
5.0
6.0
7.0
--
----
8.0
9.0
10
VIN. INPUT VOLTAGE (V)
11
12
13
Figure 12. Representative Schematic Diagrams
1/8 ULN2803
1/8 ULN2804
t--...--;-o Pin 10
I
I
I
L __
* _______ _
MOTOROLA ANALOG IC DEVICE DATA
t--*--I--o
I
I
I
L ___
Pin 10
* ______ _
7-169
II
7-170
MOTOROLA ANALOG IC DEVICE DATA
Communication Circuits
In Brief ...
RF
Radio communication has greatly expanded its scope in the
past several years. Once dominated by public safety radio, the
30 to 1000 MHz spectrum is now packed with personal and low
cost business radio systems. The vast majority of this
equipment uses FM or FSK modulation and is targeted at short
range applications. From mobile phones and VHF marine
radios to garage door openers and radio controlled toys, these
new systems have become a part of our lifestyle. Motorola
Analog has focused on this technology, adding a wide array of
new products including complete receivers processed in our
exclusive 3.0 GHz MOSAIC® 1.5 process. New surface mount
packages for high density assembly are available for all of
these products, as well as a growing family of supporting
application notes and development kits.
Telephone & Voice/Data
Traditionally, an office environment has utilized two
distinctly separate wired communications systems:
telecommunications and data communications. Each had its
individual hardware components complement, and each
required its own independent transmission line system: twisted
wire pairs for Telecom and relatively high priced coaxial cable
for Datacom. But times have changed. Today, Telecom and
Datacom coexist comfortably on inexpensive twisted wire pairs
and use a significant number of components in common. This
has led to the development and enhancement of PBX (Private
Branch Exchanges) to the point where the long heralded
"office of the future," with simultaneous voice and data
communications capability at each station, is no longer of the
future at all. The capability is here today!
Motorola Semiconductor serves a wide range of
requirements for the voice/data marketplace. We offer both
CMOS and Analog technologies, each to its best advantage,
to upgrade the conventional analog voice systems and
establish new capabilities in digital communications. Early
products, such as the solid-state single-i:hip crosspoint
switch, the more recent monolithic Subscriber-LoopInterface Circuit (SLlC) , a single-i:hip Codee/Filter (MonoCircuit), the Universal Digital Loop Transceivers (UDLT),
basic rate ISDN (Integrated Services Digital NetWOrk), and
singl8-i:hip telephone circuits are just a few examples of
Motorola leadership in the voice/data area.
MOTOROLA ANALOG IC DEVICE DATA
Page
RF Communications ..................................... 8-2
RF Front End IC's .................................... 8-2
Wideband IFs ........................................ 8-2
Wideband Single Conversion Receivers ................. 8-2
Narrowband Single Conversion Receivers ............... 8-2
Narrowband Dual Conversion Receivers ................. 8-3
Universal Cordless Phone Subsystem ICs ............... 8-3
Transmitters ........... : ............................. 8-3
Balanced Modulator/Demodulator ....................... 8-4
Infrared Transceiver .................................. 8-4
Telecommunications .................................... 8-11
Subscriber Loop Interiace Circuit ...................... 8-11
PBX Archnecture (Analog Transmission) ................ 8-12
PCM Mono-Circuits .............................. 8-12
Dual Tone Multiple Frequency Receiver .............. 8-15
ISDN VOice/Data Circuits ............................. 8-15
Integrated Services Digital Network ................. 8-15
Second Generation U-Interiace Transceivers ........ 8-16
Second Generation SIT-Interiace Transceivers ....... 8-16
Dual Data Link Controller .......................... 8-17
VoicelData Communication (Digital Transmission) ........ 8-18
Universal Digital Loop Transceiver .................. 8-18
ISDN Universal Digital Loop Transceiver II ........... 8-19
Electronic Telephone Circuit ........................... 8-19
Tone Ringers ....................................... 8-20
Speech Networks ................................... 8-21
Speakerphones ..................................... 8-25
VOice Switched Speakerphone Circuit ............... 8-25
Voice Switched Speakerphone with
I!Processor Interface ............................. 8-27
Voice Switched Speakerphone Circuit ............... 8-28
Telephone Line Interface and Speakerphone Circuit ... 8-29
Family of Speakerphone ICs ....................... 8-30
Telephone Accessory Circuits ......................... 8-31
Audio Amplifier ................................... 8-31
Current Mode Switching Regulator .................. 8-31
300 Baud FSK Modems ........................... 8-32
ADPCM Transcoder .............................. 8-32
Calling Line Identification (CLIO) Receiver ........... 8-33
CVSD Modulator/Demodulator ..................... 8-34
Summary of Bipolar Telecommunications Circuits ..... 8-35
Phase-Locked Loop Components ........................ 8-38
PLL Frequency Synthesizers .......................... 8-38
Phase-Locked Loop Functions ........................ 8-39
Package Overview ..................................... 8-41
Device Listing and Related Literature ...................... 8-43
8-1
II
:
RF Communications
Table 1. RF Front End ICs
Low Noise Amplifier
Mixer
Gain
(dB)
Noise
Figura
(dB)
IIP3
(dBm)
P1dB
(dBm)
Voltage
Cant
Osc
VCC
(V)
ICC
(mA)
Suffix!
Packaga
-15
7
16
--3 to +15
-10
-
2.7 to 6.5
7.7
011751,
01751 A,
FTBl976
-15
±3
12
--3 to +21
3
Yes
2.710 6.5
13
D1751B,
FTBl976
Device
Gain
(dB)
Noise
Figura
(dB)
IIP3
(dBm)
P1dB
(dBm)
MC13141
17
1.8
-5
MC13142
17
1.8
-5
MC13143
-
-
-
-
±3
12
--3 to +21
3
-
1.8to 6.5
1
01751
MC13144
13to
19
1.4
-1
-7
-
-
-
-
-
1.8t06.5
2t09
01751
NOTES:
All devices operate over a wide range of RF input and IF frequencies, from dc to 2.0 GHz.
Typical performance shown at 900 MHz.
Table 2. Wideband (FMlFSK) IFs
IF
Mute
RSSI
Max
Data
Rate
V
2.0Mb
Wldeband Data IF, includes
datashaper
P/648,
D1751B
10Mb
Video Speed FM IF
D1751B
Devica
Vcc
ICC
Sensitivity
(Typ)
MC13055
3-12 V
25mA
20l!V
40 MHz
V
MC13155
3-6 V
7.0mA
100l!V
250 MHz
-
Notes
Suffix!
Package
Table 3. Wideband Single Conversion Receivers - VHF
Device
VCC
ICC
Sensitivity
(Typ)
RF
Input
IF
Mute
MC3356
3-9 V
25mA
30l!V
200 MHz
10.7MHz
V
MC13156
2-6 V
5.0mA
2.01!V
500 MHz
21.4MHz
-
MC1315B
2-6 V
6.0mA
MC13159
2.7-5
V
5.5mA
RSSI
Max
Data
Rata
Notes
V
500 kb
Includes front end mixer/L.O.
PI73B,
DW1751 0
CT-2 FM/Demodulator
DWI751E,
FBlB73
FM IF/Demodulator with
split IF for DECT
FTBlB73
>1.2Mb
600 MHz
FM IF for PHS
500 kb
Suffix!
Package
DTB/948F
Table 4. Narrowband Single Conversion Receivers - VHF
Device
Vec
ICC
12dB
SINAD
Sensitivity
(Typ)
MC3357
4-8 V
5.0mA
5.01!V
MC3359
4-9 V
7.0mA
2.01!V
MC3371
2-6 V
6.0mA
RF
Input
IF
Mute
RSSI
Max
Data
Rate
45 MHz
455 kHz
V
-
>4.Bkb
60 MHz
V
Notea
>4.8kb
MC3372
MC13150
Ceramic Quad
Detector/Resonator
P/648,
D1751B
Scan output option
P1707,
DW1751 0
RSSI
P/64B,
01751B,
DTB/94BF
RSSI, Ceramic Quad
Detector/Resonator
3-6 V
I.BmA
1.01!V
500 MHz
V
>9.6kb
Suffix!
Package
Coilless Detector wHh
Adjustable Bandwidth
FTBlB73,
FTAl977
110
dB
8-2
MOTOROLA ANALOG IC DEVICE DATA
RF Communications (continued)
Table 5. Narrowband Dual Conversion Receivers - FM/FSK - VHF
Device
VCC
ICC
12dB
SINAD
Sensitivity
(Typ)
MC3362
2-7 V
3.0mA
0.71lV
4.0mA
OAIlV
MC3363
MC3335
0.71lV
MC13135
1.01lV
RF
Input
IF1
180
MHz
10.7
MHz
IF2
(Limiter
In)
Mute
RSSI
455 kHz
-
V
Data
Rate
>4.8
kb
f---
V
f---
-
MC13136
Notes
Suffix!
Package
Includes buffered
VCOoutput
Pf724,
DWf751E
Includes RF
amp/mute
DWf751F
Low cost version
DWf751D,
Pf738
Voltage buffered
RSSI, LC Quad
Detector
DWf751E,
Pf724
Voltage Buffered
RSSI, Ceramic
Quad Detector
Table 6. Universal Cordless Phone Subsystem ICs
Dual
Conversion
Receiver
Universal
DualPLL
Compander
and Audio
Interface
Voice
Scrambler
Low
Battery
Detect
Programmable
Rx. T x Trim Gain
and LBO Voltage
Reference
Suffix!
Package
Device
VCC
ICC
MC13109
2.0-5.5 V
Active Mode
6.7 rnA
Inactive Mode
40llA
V
V
V
-
1
-
FB/848B,
FTN932
MC13110
2.7-5.5 V
Active Mode
8.2 rnA
Inactive Mode
60 I!A
V
V
V
V
2
V
FBl848B
MC13111
2.7-5.5 V
Active Mode
8.2 rnA
Inactive Mode
60 I!A
V
V
V
-
2
V
FBl848B
Table 7. Transmitters - AMlFM/FSK
MaxRF
Freq
Out.
Max
Mod
Freq
Device
VCC
ICC
Pout
MC2833
3-8 V
lOrnA
-30dBm
to
+10dBm
150 MHz
50kHz
MC13175
2-5 V
40mA
8.0dBm
500 MHz
5.0 MHz
MC13176
MOTOROLA ANALOG IC DEVICE DATA
1.0GHz
Notes
Suffix!
Package
FM transmitter. Includes two frequency
multiplier/amplifier transistors
P/648,
Df751B
AM/FM transmitter. Single frequency PLL
fout = 8 x fref, includes power down function
D/751B
fout = 32 x fref, includes power down function
&-3
II
Table 8. Balanced Modulator/Demodulator
Device
MC1496
vec
ICC
3-5 V
10mA
Suffix!
Package
Function
General purpose balanced modulator/demodulator for AM, SSB, FM detection
with Carrier Balance >50 dB
P/646,
Dn51A
Table 9. Infrared Transceiver
Device
Vec
ICC
12dB
SINAD
Sensitivity
(Typ)
MC13173
3-5 V
6.5mA
5.01LV
Max
IF Freq
Carr Det
RSSI
Data
Rate
V
V
200kb
10.7
MHz
Notes
Includes Single Frequency
PLL for Tx Carrier and Rx La
Suffix!
Package
FTBl873
Universal Cordless Telephohe Subsystem IC
MC13109FB, FTA
TA
=-20° to +85°C, Case 848B, 932
The MC13109 integrates several ofthe functions ryquired
for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space
reqUirements, and external adjustments. It is designed for use
in both the handset and the base.
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna1lnput
to Audio Output 80 MHz Maximum Carrier Frequency
,
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic
Discriminator
• Compander
I
- Expandor Includes Mute, Digital Volume Control and
Speaker Driver
- Compressor Includes Mute, ALC and Limiter
• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with No
External Switches
- Universal Design for Domestic and Foreign CT~ 1
Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector,
and 14-Bit Programmable Counter and 2nd LO with
12-Bit Counter
- Transmit Section Contains Phase Detector and 14-8it
Counter
- MPU Clock Output Eliminates Need for MPU Crystal
• Supply Voltage Monitor
- Externally Adjustable Trip Point
• 2.0 to 5.5 V Operation with One-Third the Power
Consumption of Competing Devices
Ir-----------------~----------~,
'
"
.
.
" I
I
Rx In ---+---1"'1
I
1
1
1
Rx
Out
Carrier __---+--<
Detect
Tx Out __--+-~==~J
Tx VCO -----+---1
________
IL _ _L::::=.J.o!--.::.......I
Low
1-'--_1__/<--_
.. Battery
~
________
~
L....";;";";;';";"'...J
___
_ ____
~
~
Indicator
MOTOROLA ANALOG IC DEVICE DATA
Universal Cordless Telephone Subsystem IC with Scrambler
MC13110FB
TA
=-40° to +85°C, Case 848B
The MC1311 0 integrates several of the functions required
for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space
requirements, and extemal adjustments. It is designed for use
in both the handset and the base.
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna In to
Audio Out 80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic
Discriminator
• Compander
- Expandor Includes Mute, Digital Volume Control,
Speaker Driver, 3.5 kHz Low Pass Filter, and
Programmable Gain Block
- Compressor Includes Mute, 3.5 kHz Low Pass Filter,
Limiter, and Programmable Gain Block
• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with New
Extemal Switches
- Universal Design for Domestic and Foreign CT-1
Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector,
and 14--Bit Programmable Counter and 2nd.LO with
12-Bit Counter
- Transmit Section Contains Phase Detector and 14--Bit
Counter
- MPU Clock Outputs Eliminates Need for MPU Crystal
• Supply Voltage Monitor
- Provides Two Levels of Monitoring with Separate
Outputs
- Separate, Adjustable Trip Points
• Frequency Inversion Scrambler/Descrambler
- Can Be Enabled/Disabled Via MPU Interface
- Programmable Carrier Modulation Frequency
• 2.7 to 5.5 V Operation with One-Third the Power
Consumption of Competing Devices
II
r-------------------------------,I
I
I
I
I
I
I
Rx In -+-----001
I
Rx PO Out
Rx PO In >-;---~""
Rx
Out
+ __-<
Carrier ...
Detect
TxOut ...t---=;~~~J
+----1
Tx VCO ...
I.
I
Low Battery
IL _ _ _ _L:::==....Jo----'
Detect.
______________________
_____
MOTOROLA ANALOG IC DEVICE DATA
I
~
I
~
I
I
Low
.. Battery
Indicator
8-5
Narrowband FM Receiver
ow
MC131351136P,
TA
=-40° to +85°C, Case 724, 751 E
The MC13135 is a full dual conversion receiver with
oscillators, mixers, Limiting IF Amplifier, Quadrature
Discriminator, and ASSI circuitry. It is designed for use in
security systems, cordless phones, and VHF mobile and
portable radios. Its wide operating supply voltage range and
low current make it ideal for battery applications. The
Aeceived Signal Strength Indicator (ASS I) has 65 dB of
dynamic range with a voltage output, and an operational
amplifier is included for a dc buffered output. Also, an
improved mixer third order intercept enables the MC13135 to
accommodate larger input signal levels.
• Complete Dual Conversion Circuitry
• Low Voltage: 2.0 to 6.0 Vdc
• ASSI with Op Amp: 65 dB Aange
• Low Drain Current: 3.5 mA Typical
• Improved First and Second Mixer 3rd Order Intercept
• Detector Output Impedance: 250 Typically
Vee
'f 0•1
24
23
0.Q1
22
I
AFin
4
21
20
360
Audio
Ol!tPut
ASSI
Output
14
13
39k
,
455 kHz
Quad Coil
Taka
7MG-B128Z
MOTOROLA ANALOG IC DEVICE DATA
Narrowband FM Coilless Detector IF Subsystem
MC13150FTA, FTB
TA
=-40° to +85°C, Case 977, 873
The MC13150 is a narrowband FM IF subsystem targeted
at cellular and other analog applications. Excellent high
frequency performance is achieved, with low cost, through
use of Motorola's MOSAIC 1.5™ RF bipolar process. The
MC13150 has an onboard Colpitts VCO for Crystal controlled
second LO in dual conversion receivers. The mixer is a double
balanced configuration with excellent third order intercept. It
is useful to beyond 200 MHz. The IF amplifier is split to
accommodate two low cost cascaded filters. RSSI output is
derived by summing the output of both IF sections. The
quadrature detector is a unique design eliminating the
conventional tunable quadrature coil.
Applications for the MC13150 include cellular, CT-1
900 MHz cordless telephone, data links and other radio
systems utilizing narrowband FM modulation.
• Linear Coilless Detector
• Adjustable Demodulator Bandwidth
• 2.5 to 6.0 Vdc Operation
• Low Drain Current: < 2.0 mA
• Typical Sensitivity of 2.0 J.lV for 12 dB SINAD
• IIP3, Input Third Order Intercept Point of 0 dBm
• RSSI Range of Greater Than 100 dB
• Internal 1.4 kO Terminations for 455 kHz Filters
• Split IF for Improved Filtering and Extended RSSI Range
...------------0 Enable
...----------0 RSSI
Mixer~220n
RSSI
II
1----0 Buffer
Out
1--_-....--0 Detector
Output
1.5 k
:~~20n-=
49.9
220n
V18-V17 = 0;
fIF=455 kHz
-=
MOTOROLA ANALOG IC DEVICE DATA
-=
8-7
Wideband FM IF System
MC13156DW, FB
TA
=-400 to +85°C, Case 751 E, 873
The MC13156 is a wideband FM IF subsystem targeted at
high performance data and analog applications. Excellent
high frequency performance is achieved, with low cost,
through use of Motorola's MOSAIC 1.5™ RF bipolar process.
The MC13156 has an onboard Colpitts VCO for PLL
controlled multichannel operation. The mixer is useful to
beyond 200 MHz and may be used in a differential, balanced,
or single--ended configuration. The IF amplifier is split to
accommodate two low cost cascaded filters. RSSI output is
derived by summing the output of both IF sections. A precision
data shaper has a hold function to preset the shaper for fast
recovery of new data.
Applications for the MC13156 include CT-2, wideband
data links, and other radio systems utilizing GMSK, FSK or FM
modulation.
• 2.0 to 6.0 Vdc Operation
• Typical Sensitivity of 6.0 /lV for 12 dB SINAD
• RSSI Dynamic Range Typically 80 dB
• High Performance Data Shaper for Enhanced CT-2
Operation
• Internal 300 Q and 1.4 kQ Terminations for 10.7 MHz and
455 kHz Filters
• Split IF for Improved Filtering and Extended RSSI Range
0.146 11
r------------.,
I
MC13156
I
I
I
144.455 MHz
RF Input
-=-
II
Carrier
Detect
Ceramic
Filter
RSSI
Output
IOn
10 n
10 n
430
Data Slicer
Hold
10k
VCC
10.7 MHz
Ceramic
Filter
Data
Output
VCC
-=-
100 n
10 n
430
Vee
8-8
MOTOROLA ANALOG IC DEVICI;: DATA
Wideband FM IF Subsystem
MC13158FTB
TA
=-40° to +85°C, Case 873
The MC13158 is a wideband IF subsystem that is designed
for high performance data and analog applications. Excellent
high frequency performance is achieved, with low cost,
through the use of Motorola's MOSAIC 1.5™ RF bipolar
process. The MC13158 has an on-board grounded collector
VCO transistor that may be used with a fundamental or
overtone crystal in single channel operation or with a PLL in
multi-channel operation. The mixer is useful to 500 MHz and
may be used in a balanced differential or single ended
configuration. The IF amplifier is split to accommodate two low
cost cascaded filters. RSSI output is derived by summing the
output of both IF sections. A precision data shaper has an Off
function to shut the output "off' to save current. An enable
control is provided to power down the IC for power
management in battery operated applications.
Mix
In2
Mix
In!
N/C
Applications include DECT, wideband wireless data links
for personal and portable laptop computers and other battery
operated radio systems which utilize GFSK, FSK or FM
modulation.
• Designed for DECT Applications
• 1.8 to 6.0 Vdc Operating Voltage
• Low Power Consumption in Active and Standby Mode
• Greater than 600 kHz Detector Bandwidth
• Data Slicer with Special Off Function
• Enable Function for Power Down of Battery Operated
Systems
• RSSI Dynamic Range of 80 dB Minimum
• Low External Component Count
Osc Osc
Emil Base NlC VEE! Enable
MixOul
VCC!
IFln
DSGnd
IF Dec!
DSOu!
IF Dec2
IFOu!
DS'off"
VCC2
DSln!
Lim In
Lim Lim
Dec! Dec2
MOTOROLA ANALOG Ie DEVICE DATA
Lim Quad N/C Del VEE2
Out
Gain
II
UHF, FMlAM Transmitter
MC131751176D
TA = 0° to +70°C, Case 751B
The MC13175 and MC13176 are one chip FM/AM
transmitter subsystems designed for AM/FM communication
systems operating in the 260 to 470 MHz band covered by
FCC TItle 47; Part 15. They include a Colpitts crystal reference
oscillator, UHF oscillator, +8 (MC13175) or +32 (MC13176)
prescaler, and phase detector forming a versatile PLL system.
Another application is as a local oscillator in a UHF or 900 MHz
receiver. MC13175/176 offer the following features:
• UHF Current Controlled Oscillator
• Use Easily Available 3rd Overtone or Fundamental
Crystals for Reference
•
•
•
•
•
•
•
•
•
Low Number of External Parts Required
Low Operating Supply Voltage (1.8-5 Vdc)
Low Supply Drain Currents
Power Output Adjustable (Up to +10 dBm)
Differential Output for Loop Antenna or Balun
Transformer Networks
Power Down Feature
ASK Modulated by Switching Output "On"f'Off'
MC13175-fo = 8xfref
MC13176-fo =32xfref
AM Modulalor
1.3k
81
II
l00p"r--;;,
MC13176
I
VCC
MC13175
T
n
----;;-,
MC13175-Mp
MC13176-180p
0.821'
"
MC13175
Crystal
3rdOvertone
o.011' MC13176..L Crystal
Fundamental
10MHz
t
1k
I=
Vee
40.0000 MHz
':'
8-10
~
MOTOROLA ANALOG IC DEVICE DATA
Telecommunications
Subscriber Loop Interface Circuit (SLlC)
MC33120/1P, FN
TA -40° to +85°C, Case 738, 776
=
With a guaranteed minimum longitudinal balance of 58 dB,
the MC33120/1 is ideally suited for Central Office applications,
as well as PBXs, and other related equipment. Protection and
sensing components on the two-wire side can be
non-precision while achieving required system performance.
Most BORSHT functions are provided while maintaining low
power consumption, and a cost effective design. Size and
weight reduction over conventional transformer designs
permit a higher density system.
• All Key Parameters Externally Programmable with
Resistors:
• Transmit and Receive Gains
• Transhybrid Loss
•
•
•
•
•
•
•
•
• Return Loss
• DC Loop Current Limit and Battery Feed Resistance
• Longitudinal Impedance
Single and Double Fault Sensing and Protection
Minimum 58 dB Longitudinal Balance (2-wire and 4-wire)
Guaranteed
Digital Hook Status and Fault Outputs
Power Down Input
Loop Start or Ground Start Operation
Size & Weight Reduction Over Conventional Approaches
Available in 20 Pin DIP and 28 Pin PLCC Packages
Battery Voltage: -42 to -58 V (for MC33120),
-21.6 to -42 V (for MC33121)
VDD
(+5.0 V)
VDG
(Dig. God
PDVST2
ST1
VAG
(Ana. Gnc
RXI
TXO
RFO
CF
VOB
________
~
__________________________ JI
(Battery)
• Indicates Trimmed Resistor
MOTOROLA ANALOG IC DEVICE DATA
8-11
II
PBX Architecture (Analog Transmission)
PCM Mono-Circuits Codec-Filters (CMOS LSI)
II
MC145500 Series
MC145554157/64f67
Case 648, 708, 751G, 776
The Mono--circuits perform the digitizing and restoration of
the analog signals. In addition to these important functions,
Motorola's family of pulse-code modulation mono-circuits
also provides the band-limiting filter functions - all on a single
monolithic CMOS chip with extremely low power dissipation.
The Mono-circuits require no external components. They
incorporate the bandpass filter required for anti aliasing and
60 Hz rejection, the A1D-O/A conversion functions for either
U.S. Mu-Law or European A-Law companding formats, the
low-pass filter required for reconstruction smoothing, an
on-board precision voltage reference, and a variety of options
that lend flexibility to circuit implementations. Unique features
of Motorola's Mono-circuit family include wide power supply
range (6.0 to 13 V), selectable on-board voltage reference
(2.5, 3.1, or 3.8 V), and TTL or CMOS 1/0 interface.
Motorola supplies three versions in this series. The
MC145503 and MC145505 are general-purpose devices in
16 pin packages designed to operate in digital telephone or
line card applications. The MC145502 is the full-feature
device that presents all of the options available on the chip.
This device is packaged in a 22 pin DIP and 28 pin chip carrier
package.
Case 648, 7510, 751G, 738
These per channel PCM Codee-Filters perform the voice
digitization and reconstruction as well as the band limiting and
smoothing required for PCM systems. They are designed to
operate in both synchronous and asynchronous applications
and contain an on-chip precision voltage reference. The
MC145554 (Mu-Law) and MC145557 (A-Law) are general
purpose devices that are offered in 16 pin packages. The
MC145564 (Mu-Law) and MC145567 (A-Law), offered in 20
pin packages, add the capability of analog loop-back and
push-pull power amplifiers with adjustable gain.
All four devices include the transmit bandpass and receive
lowpass filters on-chip, as well as active RC pre-filtering and
post-filtering. Fully differential analog circuit design assures
lowest noise. Performance is specified over the extended
temperature range of -40° to +85°C.
These PCM Codee-Filters accept both industry standard
clock formats. They also maintain compatibility with
Motorola's family of MC3419IMC33120 SLiC products.
Txl-----,
TOC
-Tx
+ Tx
TOE
TOO
CCI
VAG
MSI
RSI
Vrel
RxG---'
ROD
RxO
RCE
MC14LC5480P, OW, SO
Case 738, 7510, 940C-02
This 5.0 V, general purpose per channel PCM Codee-Filter
offers selectable Mu-Law or A-Law companding in 20 pin DIP,
SOG and SSOP packages. It performs the voice digitization
and reconstruction as well as the band limiting and smoothing
required for PCM systems. It is designed to operate in both
synchronous and asynchronous applications and contains an
on-chip precision reference voltage (1.575 V).
The transmit bandpass and receive lowpass filters, and the
active RC pre-filtering and post-filtering are incorporated, as
well as fully differential analog circuit deSign for lowest noise.
Push-pull 300 0 power drivers with external gain adjust are
also included.
The MC14LC5480 PCM Codec-Filter accepts a variety of
clock formats, including short-frame sync, long-frame sync,
10L, and GCI timing environments. This device also maintains
compatibility with Motorola'S family of Telecom products,
including
the
MC145472
U-Interface
Transceiver,
MC145532
MC145474175 SIT-Interface Transceiver,
AOPCM Transcoder, MC145422126 UOLT-I, MC145421/25
UOLT-II, and MC3419/MC33120 SLiC.
Replaces the MC145480P, OW, SO.
ROC
VSS-
VOO-
~JSiii
~
MulA
~VLS
8-12
MOTOROLA ANALOG IC DEVICE DATA
PBX Architecture (continued)
MC14LC5540P, DW, FU
Case 710, 751F,873
The MC14LC5540 ADPCM Codec is a single chip
implementation of a PCM Codec-Filter and an ADPCM
encoder/decoder, and therefore provides an efficient solution
for applications requiring the digitization and compression of
voiceband Signals. This device is designed to operate over a
wide voltage range, 2.7 V to 5.25 V, and as such is ideal for
battery powered as well as ac powered applications. The
MC14LC5540 ADPCM Codec also includes a serial control
port and internal control and status registers that permit a
microcomputer to exercise many built-in features.
The ADPCM Codec is designed to meet the 32 kbps
ADPCM
conformance
requirements
of
CCITT
Recommendation G.721 (1988) and ANSI T1.301 (1987). It
also meets ANSI T1.303 and CCITT Recommendation G.723
for 24 kbps ADPCM operation, and the 16 kbps ADPCM
standard, CCITT Recommendation G.726. This device also
meets the PCM conformance specification of the CCITT
G.714 Recommendation.
Figure 1. MC14LC5540 ADPCM Codec Block Diagram
Codec-Filter
PO+
DR
FSR
DSP
PO-
BCLKR
ADPCM
Transcoder,
Receive Gain
and
Dual Tone
Generator
PI
RO
AXO-
II
BCLKT
FST
DT
AXO+
VDSP
TG
TITI+
Sequence!
Control
VDD
SPC
VAG
VSS
C1+
C1VEXT
PDVRESET SCPEN
SCPRx
SCPCLK
MOTOROLA ANALOG IC DEVICE DATA
SCPTX
8-13
PBX Architecture (continued)
MC145537EVK
ADPCM Codec Evaluation Kit
The MC145537EVK is the primary tool for evaluation and
demonstration of the MC14LC5540 ADPCM Codec. It
provides the necessary hardware and software interface to
access the many features and operational modes of the
MC14LC5540 ADPCM Codec.
• Provides Stand Alone Evaluation on Single Board
• The kit provides Analog-to-Analog, Analog-to-Digital or
Digital-to-Analog Connections - with Digital Connections
being 64 kbps PCM, 32 or 24 kbps ADPCM, or 16 kbps
CCITI G.726 or Motorola Proprietary ADPCM
• +5.0 V Only Power Supply, or 5.0 V Plus 2.7 to 5.25 V
Supply
• Easily Interfaced to Test Equipment, Customer System,
Second MC145537EVK or MC145536EVK (5.0 V Only)
for Full Duplex Operation
• Convenient Access to Key Signals
• Piezo Loudspeaker
• EIA-232 Serial Computer Terminal Interface for Control
of the MC14LC5540 ADPCM Codec Features
• Compatible Handset Provided
• Schematics, Data Sheets, and User's Manual Included
Figure 2. MC145537EVK Block Diagram
+5.0 V
r
-
-Gnd-
I ation.
It also has an enhanced TOM interface that sUPP9rts an
on-chip timeslotassigner, GCI and IDL modes of operation.
The optional manual maintenance mode lets you choose
an inexpensive microcontroller, such as a meml;ler of
Motorola's MC68HC05 family, to control and augment the
Case 873A
MC1454BB
OOLC
TA
MC145574
SCP
IOL
MC145574DW
Case 751F
The MC145574 SfT-lnterface Transceivers provide a
CCITT 1.430 compatible interface for use in line card, network
termination, and ISDN terminal equipment applications.
Manufactured with Motorola's advanced 0.65 micron CMOS
mixed analog and digital process technology, the MC145574 is
a physical layer device capable of operating in point-to-point
or point-ta-multipoint passive bus arrangements. In addition,
the MC145574 implements the optional NT1 Star topology, NT
terminal mode and TE slave mode.
This
device
features
outstanding
transmission
performance. It reliably transmits over 1 kilometer in a
point-ta-point application. Comparable performance is
achieved in all other topologies as well. Other features include
pin selectable terminal or network operating modes, industry
standard microprocessor serial control port, full support of the
multiframing Sand Q channels, a full range of loopbacks, and
low power CMOS operation, with a maximum power
consumption of 90 mW.
The MC145574 has an enhanced TOM interface that
supports GCI, IDL and an on-chip timeslot assigner.
NT1
MC145572
MC145574
GCI
SIT
LT
MC145572
SIT
U
Chip
Chip
IOL
U
Chip
C
SCP
e
n
t
NT1ITA
a
I
SIT
Chip
MC6B302
RS232
8-16
o
S P
f
f
LT
MC145572
MC145572
IOL
U
Chip
I
c
e
SCP
MOTOROLA ANALOG ICDEVICE DATA
ISDN Voice/Data Circuits
(continued)
Dual Data Link Controller
MC145488FN
Case 779
MC14LC5494EVK
U-Interface Transceiver Evaluation Kit discontinued
The MC145488 features two full-Quplex serial HDLC
channels with an on--chip Direct Memory Access (DMA)
controller. The DMA controller minimizes the number of
microprocessor interrupts from the communications
channels, freeing the microprocessor's resources for other
tasks. The DMA controller can access up to 64 kbytes of
memory, and transfers either 8-bit bytes or 18-bit words to or
from memory. The MC145488 DDLC is compatible with
Motorola's MC68000 and other microprocessors.
In a typical ISDN terminal application, one DDLC
communications channel supports the D--channel (LAPD)
while the other supports the B--channel (LAPB). While the
DDLC is ideally suited for ISDN applications, it can support
many other HDLC protocol applications as well.
Some of the powerful extras found on the DDLC include
automatic abort and retransmit of D--channel collisions in
SIT-interface applications, address recognition, automatic
recovery mechanisms for faulty frame correction, and several
system test modes. Address recognition provides a reduction
in the host microprocessor load by filtering data frames not
addressed to the host. The DDLC can compare either SAPI or
TEl fields of LAPD frames. For LAPD (Q.921) applications,
both A and B addresses may be checked.
MC145572EVK
U-Interface Transceiver Evaluation Kit
This kit provides the hardware and software to evaluate the
many configurations under which the MC145572EVK is able
to operate. Used as a whole, it operates as both ends of the
two-wire U interface that extends from the customer premises
(NT1) to the switch line card (LT). The two halves ofthe board
can be physically and functionally separated, providing
independent NT1 and LT evaluation capability.
The kit provides the ability to interactively manipulate
status registers in the MC145572EVK U-Interface transceiver
or in the MC145474175 SIT-Interface transceiver with the aid
of an external terminal. The device can also be controlled
using the MC68302 Integrated Multiprotocol Processor
application development system to complete a total Basic
Rate ISDN evaluation solution.
II
281 Q U-Interface
NT1 Side
SIT
Interface
IDL
SIT-Interface
Transceiver
MC145474
IDL~
LTSide
t --I
I
SCP
,.IDL
U-Interface
Transceiver
MC145572FN
__ .J
SCP~~+-----4-------~~------------~------~~--.
Gated
Clocks
'------'f-------...,t-~
SCP
MC145572EVK
MOTOROLA ANALOG IC DEVICE DATA
8-17
Voice/Data Communication
(Digital Transmission)
UDLTs utilize a 256 kilobaud Modified Differential Phase
Shift Keyed (MDPSK) burst modulation technique for
transmission to minimize radio frequency, electromagnetic,
and crosstalk interference. Implementation through CMOS
technology takes advantage of
low-power operation,
increased reliability, and the proven capabilities to perform
complex telecommunications functions.
.
2-Wire Universal Digital Loop
Transceiver (UDLT)
MC145422P,
ow Master Station
Case 708, 751 E
MC145426P, OW Slave Station
Case 708, 751 E
II
The UDLT family of transceivers allows the use of existing
twisted-pair telephone lines (between conventional
telephones and a PBX) for the transmission of digital data.
With the UDLT, every voice-only telephone station in a PBX
system can be upgraded to a digital telephone station that
handles the complex voice/data communications with no
increase in cabling costs.
In implementing a UDLT-based system the AID to D/A
conversion function associated with each telset is relocated
from the PBX directly to the telsel. The SLiC (or its equivalent
circuit) is eliminated since its signaling information is
transmitted digitally between two UDLTs.
The UDLT master-slave system incorporates the
modulation/demodulation functions that permit data
communications over a distance up to 2 kilometers. It also
provides the sequence control that governs the exchange of
information between master and slave. Specifically, the master
resides on the PBX line card where it transmits and receives
data over the wire pair to the telset. The slave is located in the
telset and interfaces the mono-circuit to the wire pair. Data
transfer occurs in 1o-bit bursts (8 bits of data and 2 signaling
bits), with the master transmitting first, and the slave responding
In a synchronized half-duplex transmission formal.
Functional Features
• Provides Synchronous Duplex 64 kbitslSecond
Voice/Data Channel and Two 8 kbitslSecond Signaling
Data Channels Over One 26 AWG Wire Pair Up to 2 km.
• Compatible with Existing and Evolving Telephone Switch
Architectures and Call Signaling Schemes
• Automatic Detection Threshold Adjustment for Optimum
Performance Over Varying Signal Attenuations
• Protocol Independent
• Single 5.0 V to 8.0 V Power Supply
MC145422 Master UDLT
• 2.048 MHz Master Clock
• Pin Controlled Power-Down and Loop-Back Features
• Variable Data Clock - 64 kHz to 2.56 MHz
• Pin Controlled Insertion/Extraction of 8 kbits/Seconds
Channel into LSB of 64 kbits/Second Channel for
Simultaneous Routing of Voice and Data Through PCM
Voice Path of Telephone Switch
MC145426 Slave UDLT
• Compatible with MC145500 Series and Later PCM
Mono-Circuits
• Automatic Power-Up/Down Feature
• On-Chip Data Clock Recovery and Generation
• Pin Controlled 500 Hz D3 or CCITT Format PCM Tone
Generator for Audible Feedback Applications
...-------......:::;::::..---4- Signaling Inpull
r-----------Line
Driver
Output
Signaling Input 2
Receive Dam Input
r--L.-~_ _ _ _~
Receive Enable
er
\TaIid1Jal8
\ - - - - - - ~oop
ower own
1 - - -_ _- TIA Dam Clock
--+
1------ Conv.rtCioCk
Master Sync
~===::: Signal Insert Enable
I...§!~I.E!~___
1------ Mu Law
1------I
.~ ..
Tone Enable
XTALIn
I..........
~T~~ _ _ _ _
Master
Only
_
Slave
Only
J_
Transmit Enable
Line
Input
Transmft Daia
Signal Output 1
Signal Output 2
8-18
MOTO~OLA
ANALOG IC DEVICE.DATA
Voice/Data Communication (Digital Transmission)
(continued)
2-Wire ISDN Universal Digital Loop Transceiver II (UDLT II)
MC145421 P,
ow Master
Similar to the MC145422126 UDLT, but provide
synchronous full duplex 160 kbps voice and data
communication in a 2B + 2D format for ISDN compatibility on
a single twisted pair up to 1 km. Single 5.0 V power supply,
protocol independent.
Case 709, 751 E
MC145425P, OW Slave
Case 709, 751 E
Electronic Telephone
The Complete Electronic Telephone Circuit
MC34010P, FN
TA =-20° to +60°C, Case 711,777
The conventional transformer-driven telephone handset is
undergoing major innovations. The bulky transformer is
disappearing. So are many of its discrete components,
including the familiar telephone bell. They are being replaced
with integrated circuits that perform all the major handset
functions simply, reliably and inexpensively ... functions such
as 2-t0-4 wire conversion, DTMF dialing, tone ringing, and a
variety of related activities.
The culmination of these capabilities is the Electronic
Telephone Circuit, the MC34010. These ICs place all of the
above mentioned functions on a single monolithic chip.
These telephone circuits utilize advanced bipolar analog
(12L) technology and provide all the necessary elements of a
modern tone-dialing telephone. The MC34010 even
incorporates an MPU interface circuit for the inclusion of
automatic dialing in the final system.
• DTMF generator uses low cost ceramic resonator with
accurate frequency synthesis technique
• Tone ringer drives piezoelectric transducer and satisfies
EIA-470 requirements
• Speech network provides 2-to-4 wire conversion with
adjustable sidetone utilizing an electret transmitter
• On--chip regulator insures stable operation over wide
range of loop lengths
• 12L technology provides low 1.4 V operation and high
static discharge immunity
• Microprocessor interface port for automatic dialing features
Also Available
A broad line of additional telephone components for
customizing systems design.
• Provides all basic telephone functions, including DTMF
dialer, tone ringer, speech network and line voltage
regulator
Hook Switch
//r-~
Ceramic
Resonator
r1 2 3 A
4 5 6 8
7 8 9 C
• 0 # 0
Keypad
MPU
-----,
I
I
/
Tip
,.-'-.............., ,....--...... J
DTMF
MPU
Intertace
Receiver
Tone
Ringer
I
I
I
Ring
Speech
Network
MC34010
Electret
Microphone
MOTOROLA ANALOG IC DEVICE DATA
8-19
II
Tone Ringers
The MC34012, MC34017, and MC34117 Tone Ringers are
designed to replace the bulky bell assembly of a telephone,
while providing the same function and performance under a
variety of conditions. The operational requirements spelled
out by the FCC and EIA-470, simply stated, are that a ringer
circuit MUST function when a ringing signal is provided, and
MUST NOT ring when other signals (speech, dialing, noise)
are on the line. The tone ringers described below were
designed to meet those requirements with a minimum of
external components.
MC34012P, D
TA
=-20° to +60°C, Case 626, 751
• Complete Telephone Bell Replacement
• On-Chip Diode Bridge and Transient
Protection
• Single-Ended Output to Piezo
Transducer
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial and Hook Switch
Transients
• Adjustable Base Frequencies
• Output Frequency to Warble Ratio MC34012-1 :80
MC34012-2:160
MC34012-3:40
Aing>-----<>-:-:~~..
MC34017P, D
TA
=-20° to +60°C, Case 626, 751
AI 4 *C4
• Complete Telephone Bell Replacement
Circuit with Minimum External
Components
Aing
• On-Chip Diode Bridge and Transient
Protection
• Direct Drive for Piezoelectric
Transducers
• Push Pull Output Stage for Greater
Output Power Capability
• Base Frequency Options
- MC34017-1: 1.0 kHz
- MC34017-2: 2.0 kHz
- MC34017-3: 500 Hz
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial TranSients
8-20
r--------- ---------,t
t
t
I
TiP~ ACI DIode
Cl
1
AC2 1
•
I 2A01
MOTOROLA ANALOG IC DEVICE DATA
Tone Ringers
(continued)
MC34217P, D
TA
=-20° to +60°C, Case 626, 751
• Complete Telephone Bell Replacement
• On-Chip Diode Bridge
Internal Transient Protection
• Differential Output to Piezo Transducer
for Louder Sound
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial and Hook Switch
Transients
• Base Frequency and Warble
Frequencies are Independently
Adjustable
• Adjustable Base Frequency
• Reduced Number of Externals
r- ....... ---.--81 fl01 l.lIlId$ll!ttIgII
Tip ~If-t...........-.,
R1 C1 1
1
Ring
..----4~,....,~I~~
Speech Networks
Telephone Speech Network with Dialer Interface
MC34114P, DW
TA
=-20° to +70°C, Case 707, 751 D
• Operation Down to 1.2 V
• Adjustable Transmit, Receive, and Sidetone Gains by
External Resistors
• Differential Microphone Amplifier Input Minimizes RFI
• Transmit, Receive, and Sidetone Equalization on both
Voice and DTMF Signals
•
•
•
•
Regulated 1.7 V Output for Biasing Microphone
Regulated 3.3 V Output for Powering External Dialer
Microphone and Receive Amplifiers Muted During Dialing
Differential Receive Amplifier Output Eliminates Coupling
Capacitor
• Operates with Receiver Impedances of 150 n and Higher
Tip 0 - - - - - ,
Ring 0 - - - - - '
MOTOROLA ANALOG Ie DEVICE DATA
8-21
Speech Networks
(continued)
Cordless Universal Telephone Interface
MC34016DW, P
TA
=-20° to +70°C, Case 7510,738
The MC34016 is a telephone line interface meant for use
in cordless telephone base stations for CTO, CT1, CT2 and
DECT. The circuit forms the interface towards the telephone
line and performs all speech and line interface functions like
dc and ac line termination, 2-4 wire conversion, automatic
gain control and hookswitch control. Adjustment of
transmission parameters is accomplished by two 8 bit
registers accessible via the integrated serial bus interface and
by external components.
• DC Masks for Voltage and Current Regulation
• Supports Passive or Active AC Set Impedance
Applications
• Double Wheatstone Bridge Sidetone Architecture
• Symmetrical Inputs and Outputs with Large Signal Swing
Capability
• Gain Setting and Mute Function for Tx and Rx Amplifiers
• Very Low Noise Performance
• Serial Bus Interface SPI Compatible
• Operation from 3.0 to 5.5 V
II
FEATURES
Line Driver Architecture
• Two DC Masks for Voltage Regulation
• Two DC Masks for Current Regulation
• Passive or Active Set Impedance Adjustment
• Double Wheatstone Bridge Architecture
• Automatic Gain Control Function
Transmit Channel
• Symmetrical Inputs Capable of Handling Large Voltage
Swing
• Gain Select Option via Serial Bus Interface
• Transmit Mute Function, Programmable via Bus
• Large Voltage Swing Capability at the Telephone Line
Receive Channel
• Double Sidetone Architecture for Optimum Line Matching
• Symmetrical Outputs Capable of Producing High Voltage
Swing
• Gain Select Option via Serial Bus Interface
• Receive Mute Function, Programmable via Serial Bus
Serial Bus Interface
• 3-Wire Connection to Microcontroller
• One Programmable Output Meant for Driving a
Hookswitch
• Two Programmable Outputs Capable of Driving Low
Ohmic Loads
• Two 8-Bit Registers for Parameter Adjustment
... 1-::~
/,1
Serial Bus Interface
·1
"1
AGe'
""""""""'''''''''''''''''''''''''''''''''''''''T'C0Ui2
....",..r
''''' _
, __
AGe
HKSW
__
I
~_J
+5.0 V
Serial Bus
Inputs
8-22
A (Tip)
'----+--- B (Ring)
~
Logic
Outputs
MOTOROLA ANALOG IC DEVICE DATA
Speech Networks
(continued)
Programmable Telephone Line Interface
Circuit with Loudspeaker Amplifier
MC34216DW
TA
=0
0
to +70°C, Case 751 F
The MC34216 is developed for use in telephone
applications where besides the standard telephone functions
also the group listening-in feature is required. In cooperation
with a microcontroller, the circuit performs all basic telephone
functions including DTMF generation and pulse-dialing. The
listening-in part includes a loudspeaker amplifier, an
anti-howling circuit and a strong supply. In combination with
the TCA3385, the ringing is performed via the loudspeaker.
FEATURES
Line Driver and Supply
•
•
•
•
DC and AC Termination of the Line
Selectable Masks: France, U.K., Low Voltage
Current Protection
Adjustable Set Impedance for Resistive and Complex
Termination
• Efficient Supply Point for Loudspeaker Amplifier and
Peripherals
Handset Operation
•
•
•
•
Transmit and Receive Amplifiers
Adjustable Sidetone Network
Line Length AGC
Microphone and Earpiece Mute
• Earpiece Gain Increase Switch
• Microphone Squelch Function
• Transmit Amplifier Soft Clipping
Dialing and Ringing
•
•
•
•
•
•
Generates DTMF, Pilot Tones and Ring Signal
Interrupter Driver for Pulse-Dialing
Low Current While Pulse-Dialing
Optimized for Ringing via Loudspeaker
Programmable Ring Melodies
Uses Inexpensive 500 kHz Resonator
Loudspeaking Facility
•
•
•
•
•
Integrated Loudspeaker Amplifier
Peak-to-Peak Limiter Prevents Distortion
Programmable Volume
Anti-Howling Circuitry for Group Listening-In
Interfacing for Handsfree Conversation
8
Application Areas
•
•
•
•
Corded Telephony with Group Listening-In
Cordless Telephony Base Station with Group Listening-In
Telephones with Answering Machines
Fax, Intercom, Modem
Line +
7"~-:------"""""""'1
4
>7.'"1"
Handset
Earpiece
Supply
Stabilizer
l
Handset
Microphone
!
Base
Loudspeaker
I
I
I
1
_ _ _ _ _ _ _ _ _ _ _ _ _ JI
DTMFand
Ring
Generator
Microcontroller
Intenace
Line-
MOTOROLA ANALOG IC DEVICE DATA
8-23
Speech Networks (continued)
Telephone Line Interface
TCA3388DP, FP
TA =0° to +70°C, Case 738, 7510
The TCA3388 is a telephone line interface circuit which
performs the basic functions of a telephone set in combination
with a microcontroller and a ringer. It includes dc and ac line
termination, the hybrid function with 2 adjustable sidetone
networks, handset connections and an efficient supply point.
•
•
•
•
FEATURES
•
•
•
•
Line Driver and Supply
•
•
•
•
DC and AC Termination of the Telephone Line
Selectable DC Mask: France, U.K., Low Voltage
Current Protection
Adjustable Set Impedance for Resistive and Complex
Termination
• Efficient Supply Point for Peripherals
• Hook Status Detection
Double Anti-Sidetone Network
Line Length AGC
Microphone and Earpiece Mute
Transmit Amplifier Soft Clipping
Dialing and Ringing
Interrupter Driver for Pulse-Dialing
Reduced C~9:ent Consumption During Pulse-Dialing
DTMF Inte~~ing
Ringing vi~ Extemal Ringer
Application Areas
• Corded Telephony
• Cordless Telephony Base Station
• Answering Machines
• Fax
Handset Operation
• Intercom
• Modem
• Transmit and Receive Amplifiers
II
Line +
DC and AC
Handset
Earpiece
Handset
Microphone
_.
I
I
L.,,-'
f ___
DC Mask Generation
AC Termination
2-4 Wire Conversion
Microcontrolier
Interface
~
__ _
Une-
8-24
MOTOROLA ANALOG IC DEVICE DATA
Speakerphones
Voice Switched Speakerphone Circuit
MC34018P, DW
TA
=-20
0
to +60°C, Case 710, 751 F
The MC34018 Speakerphone integrated circuit
incorporates the necessary amplifiers, attenuators, and
control functions to produce a high quality hands-free
speakerphone system. Included are a microphone amplifier,
a power audio amplifier for the speaker, transmit and receive
attenuators, a monitoring system for background sound level,
and an attenuation control system which responds to the
relative transmit and receive levels as well as the background
level. Also included are all necessary regulated voltages for
both internal and external circuitry, allowing line-powered
operation (no additional power supplies required). A Chip
Select pin allows the chip to be powered down when not in
use. A volume control function may be implemented with an
external potentiometer. MC34018 applications include
speakerphones for household and business uses, intercom
systems, automotive telephones, and others.
• All Necessary Level Detection and Attenuation Controls
for a Hands-Free Telephone in a Single Integrated
Circuit
• Background Noise Level Monitoring with Long Time
Constant
• Wide Operating Dynamic Range Through Signal
Compression
• On-Chip Supply and Reference Voltage Regulation
• Typical 100 mW Output Power (into 25 0) with Peak
Limiting to Minimize Distortion
• Chip Select Pin for Active/Standby Operation
• Linear Volume Control Function
Electret
Microphone
II
Speaker
TelePhonr---+
Line\!
Receive Volume Control
MOTOROLA ANALOG IC DEVICE DATA
8-25
Speakerphones
(continued)
Voice Switched Speakerphone Circuit
MC34118P, DW
TA = -20° to +60°C, Case 710, 751 F
The MC34'118 Voice Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain and mute control,
Transmit and Receive attenuators which operate in a
complementary manner, level detectors at input and output of
both attElnuators,and background noise monitors for both the
transmit and receive channels. A dial tone detector prevents
the dial tone from being attenuated by the Receive
background noise monitor circuit. Also included are two line
driver amplifiers which can be used to form a hybrid network
in conjunction with an external coupling transformer. A
high-pass filter can be used to filter out 60 Hz noise in the
receive channel, or for other filtering functions. A Chip Disable
pin permits powering down the entire circuit to conserve power
on long loops where loop current is at a minimum.
The MC34118 may be operated from a power supply, or
it can be powered from the telephone line, requiring typically
5.0 mA. The MC34118 can be interfaced directly to TIp and
Ring (through a coupling transformer) for stand-alone
operation, or it can be used in conjunction with a handset
speech network and/or other features of a featurephone.
• Improved Attenuator Gain Range: 52 dB Between
Transmit and Receive
• Low Voltage Operation for Line-Po~ered Applications
(3.0 to 6.5 V)
• 4-Point Signal, Sensing for Improved Sensitivity
• Background Noise Monitors for Both Transmit and
Receive Paths
• Microphone Amplifier Gain Set by External ResistorsMute Function Included
• Chip Disable for Active/Standby Operation
• On Board Filter Pinned-out for User Defined Function
• Dial Tone Detector Inhibits Receive Idle Mode During Dial
Tone Presence
• Compatible with MC34119 Speaker Amplifier
II
(
'I
I
I
I
I
I
I
, I
Ring
~Vcc
~ChiP
I
Disable
Filter
_ _ _ _ _ ...JI
8-26
MOTOROLA ANALOG IC DEVICE DATA
Speakerphones
(continued)
Voice Switched Speakerphone with /-lProcessor Interface
MC33218AP,
TA
ow
=-40° to +85°C, Case 724, 751 E
The MC33218A, Voice Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain, and mute control,
transmit and receive attenuators which operate in a
complementary manner, and level detectors and background
noise monitors for both paths. A dial tone detector prevents
dial tone from being attenuated by the receive background
noise monitor. A Chip Disable pin permits powering down the
entire circuit to conserve power.
Also included is an 8--bit serial IlProcessor port for
controlling the receive volume, microphone mute, attenuator
gain, and operation mode (force to transmit, force to receive,
etc.). Data rate can be up to 1.0 MHz. The MC33218A can be
operated from a power supply, or from the telephone line,
requiring typically 3.8 rnA. It can also be used in intercoms and
other voice-activated applications.
•
•
•
•
Low Voltage Operation: 2.5 to 6.0 V
2-Point Sensing, Background Noise Monitor in Each Path
Chip Disable Pin for Active/Standby Operation
Microphone Amplifier Gain Set by External Resistors Mute Function Included
• Dial Tone Detector to Inhibit Receive Idle Mode During
Dial Tone Presence
• Microprocessor port for controlling:
• Receive Volume Level (16 Steps)
• Attenuator Range (26 or 52 dB, Selectable)
• Microphone Mute
• Force to Transmit, Receive, Idle or Normal Voice
Switched Operation
• Compatible with MC34119 Speaker Amplifier
r---------------,I
III
) -......--;--.... TxOutput
Rx Input
Vcc
Chip Disable
MOTOROLA ANALOG IC DEVICE DATA
8--27
Speakerphones
(continued)
Voice Switched Speakerphone Circuit
MC33219AP, ADW
TA
=-40° to +85°C, Case 724, 751 E
The MC33219A Voice Switched Speakerphone Circuit
incorporates the necessary amplifiers, attenuators" level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain, and mute control,
transmit and receive attenuators which operate in a
complementary manner, and level detectors and background
noise monitors, A dial tone detector prevents dial tone from
being attenuated by the receive background noise monitor. A
Chip Disable pin permits powering down the entire circuit to
I
conserve power.
The MC33219A may be operated from a power supply, or
it can be powered from the telephone line requiring typically
4.0 mAo The MC33219A can be interfaced directly to TIp and
Ring (through a coupling transformer for stand-alone
operation, or it can be used in conjuction with a. handset
speech network and/or other features of a featurephone.
• Low Voltage Operation: 2.7 to 6.0 V
• 2-Point Sensing, Background Noise Monitor in Each Path
• Chip Disable Pin for Active/Standby Operation
• Microphone Amplifier Gain Set by External ResistorsMute Function Included
• Dial Tone. Detector to Inhibit Receive Idle Mode During
Dial Tone Presence
• Volume Control Range: 34 dB
• Compatible with MC34119 Speaker Amplifier
Mute
>-+"'--i-....
Tx Output
II
Speaker
I
Speaker
Amp
....
, "
~
Bias"
VCC
,_
:
_
_ _ _ _ _• . _ _._ .J
VVV,
Rx Input
Chip Disable
-=-
Volum~
Control
MOTOROLA ANALOG IC DEVICE DATA
Speakerphones
(continued)
Telephone Line Interface and Speakerphone Circuit
MC33215B, FB
TA
=0° to +70°C, Case 858, 848B
The MC33215 is a combination speech network!
speakerphone developed for use in fully electronic telephone
sets with a speakerphone function. The circuit performs the ac
and dc line terminations, 2-4 wire conversion, line length AGC
and DTMF transmission. The speakerphone part includes a
half duplex controller with signal and noise monitoring, base
microphone and loudspeaker amplifiers, and an efficient
supply. The circuit is designed to operate at low line currents
down to 4.0 rnA enabling parallel operation with a classical
telephone set.
FEATURES
Line Driver and Supply
• AC and DC Termination of Telephone Line
• Adjustable Set Impedance for Real and Complex
Termination
• Efficient Supply for Speaker Amplifier and Peripherals
• Two Supplies for Handset and Base Microphones
• Separate Supply Arrangement for Handset and
Speakerphone Operation
Handset Operation
•
•
•
•
•
•
•
Transmit and Receive Amplifiers
Differential Microphone Inputs
Sidetone Cancellation Network
Line Length AGC
Microphone and Earpiece Mute
Separate Input for DTMF and Auxiliary Signals
Parallel Operation Down to 4.0 rnA of Line Current
Speakerphone Operation
• Integrated Microphone and Loudspeaker Amplifiers
• Differential Microphone Inputs
• Loudspeaker Amplifier can be Powered and Used
Separately from the Rest of the Circuit
• Integrated Switches for Smooth Switch Over from
Handset to Speakerphone Mode
• Signal and Background Noise Monitoring in Both
Channels
• Adjustable Switching Depth for Handsfree Operation
• Adjustable Switch Over and Idle Mode Timing
• Dial Tone Detector in the Receive Channel
• Handsfree Operation via Loudspeaker and Base
Microphone
r---------------~--------_.------------ 1.0 ~F)
External Required:
• 14 Resistors
• 12 Capacitors (SI.0 ~F)
• 9 Capacitors (> 1.0 ~F)
External Required:
• 12 Resistors
• 11 Capacitors (SI.0 ~F)
• 4 Capacitors (> 1.0 ~F)
External Required:
• 12 Resistors
• 11 Capacitors (SI.0 ~F)
• 4 CapaCitors (> 1.0 ~F)
Temperature Range:
-20° to +60°C
Temperature Range:
-20° to +60°C
Temperature Range:
-40° to +85°C
Temperature Range:
-40° to +85°C
8-30
MOTOROLA ANALOG IC DEVICE DATA
Telephone Accessory Circuits
Audio Amplifier
MC34119P,D
TA
=0° to +70°C, Case 626, 751
A low power audio amplifier circuit intended (primarily) for
telephone applications, such as speakerphones. Provides
differential speaker outputs to maximize output swing at low
supply voltages (2.0 V min.). Coupling capacitors to the
speaker, and snubbers, are not required. Overall gain is
externally adjustable from 0 to 46 dB. A Chip Disable pin
permits powering-down to mute the audio signal and reduce
power consumption.
Drives a Wide Range of Speaker Loads (16 to 100 0)
Output Power Exceeds 250 mW with 32 0 Speaker
Low Distortion (THD = 0.4% Typical)
Wide Operating Supply Voltage (2.0 V to 16 V) - Allows
Telephone Line Powered Applications.
• Low Quiescent Supply Current (2.5 mA Typical)
• Low Power-Down Quiescent Current (60 ~ Typical)
•
•
•
•
Current Mode Switching Regulator
MC34129P,D
High performance current mode switching regulator for
low-power digital telephones. Unique internal fault timer
provides automatic restart for overload recovery. A starVrun
comparator is included to implement bootstrapped operation
ofVCC·
Although primarily intended for digital telephone systems,
these devices can be used cost effectively in many other
applications. On-chip functions and features include:
•
•
•
•
•
•
•
Current Mode Operation to 300 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle-By-Cycle Current Limiting
Latched-Off or Continuous Retry after Fault Timeout
Soft-Start with Maximum Peak Switch Current Clamp
Internally Trimmed 2% Bandgap Reference
Input Undervoltage Lockout
MOTOROLA ANALOG IC DEVICE DATA
II
r-------------,
TA = 0° to +70°C, Case 646, 751A
I
lsi
I
Start/Run
c SofHltart 112
I
syncllnhibit~
Input
Noninverting
Input
Inverting Input
' -_ _-:.:0 Feedback!
I PWMlnput
Drive Out
Drive Gnd
I
IL _ _ _ _ _ _ _ _ _ _
~
_ _ J Ramp Input
8-31
Telephone Accessory Circuits
(continued)
300 Baud FSK Modems
The differential line driver is capable of driving 0 dBm into
a 600 n load. The transmit attenuator is programmable in
1.0 dB steps.
MC145442P, ow Modem - CCITT V.21
Case 738, 751 D
ADPCM Transcoder
MC145443P, OW Modem - 8ell103
Case 738, 751 D
MC145532DW, L
Case 751G, 620
This powerful modem combines a complete FSK
modulator/demodulator and an accompanying transmit/receive
filter system on a single silicon chip. Designed for bidirectional
transmission over the telephone network, the modem operates
at 300 baud and can be obtained for compatibility with CCITT
V.21 and Bell 103 specifications.
The modem contains an on-board carrier-detect circuit
that allows direct operation on a telephone line (through a
simple tranSformer), providing simplex, half-duplex, and
full-duplex data communications. A built-in power amplifier is
capable of driving -9.0 dBm onto a 600 n line in the transmit
mode.
CMOS processing keeps power dissipation to a very low
45 mW, with a power-down dissipation of only 1.0 mW ... from
a single 5.0 V power supply. Available in a 20 pin dual-in-line
P suffix, and a wide body surface mount DW suffix.
MC145407
+5.0 V
MC145443
+5.0 V
II
CD
3.579545 MHz
MC145444H, OW - CCITT V.21
Case 804, 7510
MC145446AFW - CCITT V.21
Case 751M
This device includes the DTMF generator and call progress
tone detector (CPTD) as well as the other circuitry needed for
full-duplex, half-duplex, or simplex 300 baud data
communication over a pair of telephone lines. It is intended for
use with telemeter system or remote control system
applications.
8-32
The MC145532 Adaptive Differential Pulse Code
Modulation (ADPCM) Transcoder provides a low cost,
full-duplex, single-channel transcoder to (from) a 64 kbps
PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
• Complies with CCITT Recommendation G.721
(1988)
• Complies with the American National Standard
(T1.301-1987)
• Full-Duplex, Single-Channel Operation
• Mu-Law or A-Law Coding is Pin Selectable
• Synchronous or Asynchronous Operation
• Easily Interfaces with any Member of Motorola's PCM
Codee-Filter Mono-Circuit Family or Other Industry
Standard Codecs
• Serial PCM and ADPCM Data Transfer Rate from
64 kbps to 5.12 Mbps
• Power Down Capability for Low Cost Consumption
• The Reset State is Automatically Initiated when the
Reset Pin is Released.
• Simple TIme Slot Assignment TIming for Transcoder
Applications
• Single 5.0 V Power Supply
• Evaluation Kit MC145536 EVK Supports the MC145532
as well as the MC14LC5480 PCM Codee-Filter. (See
PBX Architecture Pages for More Information.)
000
EDO
DOE
EOE
DOC
EDC
DDI
EDI
DIE
EIE
MODE
APD
---------0(
---------0(
Vss-
10------- Reset
·~--------s~
-VDD
MOTOROLA ANALOG IC DEVICE DATA
Telephone Accessory Circuits
(continued)
Calling Line Identification (CLIO) Receiver with Ring Detector
MC14LC5447P, DW
Case 648, 751G
The MC14LC5447 is designed to demodulate Bell 202
1200 baud FSK asynchronous data. Its primary application is
in products that will be used to receive and display the calling
number, or the message waiting indicator sent to subscribers
from participating central office facilities of the public switched
telephone network. The device also contains a carrier detect
circuit and telephone ring detector which may be used to
power up the device.
Applications include adjunct boxes, answering machines,
feature phones, fax machines, and computer interface
products.
Replaces MC145447P, OW.
•
•
•
•
•
Ring Detector On-Chip
Ring Detect Output for MCU Interrupt
Power-Down Mode Less Than 1.0 !LA
Single Supply: 3.5 V to 6.0 V
Pin Selectable Clock Frequencies: 3.68 MHz,
3.58 MHz, or 455 kHz
• Two-Stage Power-Up for Power Management Control
TIp
Ring
r---. RawData
OUt
Cooked
Data Out
ClocI---1-. +Va
Vs _ _-----.----c>-':-l1
!--O--+-- -Va
Modulating
rt-J~4"l-r-_~~12
Signallnput 10 k
51
14
5
6.8k
'L------~V
-Il.OVdc
VEE
8-48
Carrier Null
...MVdc
VEE
MOTOROLA ANALOG IC DEVICE DATA
MC1496, B
Figure 9. Common Mode Gain
.--_ _ _ _ _ _ _--+
Figure 10. Signal Gain and Output Swing
VCC
12Vdc
.--_ _ _ _ _ _ _ _-+
VCC
12Vdc
1.0k
1.0k
3.9k
3.9k
\-:0.......-+_ +Vo
-+-- +Vo
I-;;<>......
9-----·-
1--12<>--",-" - Vo
Vs
b2
&"-"'-:-14:---""5:-1
14
50
l.~~At
6.Bk
so
IVol
ACM = 20 log V
-8.0Vdc
VEE
Vo
S
6.8k
-8.0Vdc
VEE
TYPICAL CHARACTERISTICS
=
Typical characteristics were obtained with circuit shown in Figure 5, Ie 500 kHz (sine wave),
Ve = 60 mVrms, IS = 1.0 kHz, Vs = 300 mVrms, TA = 25°e, unless otherwise noted.
Figure 11. Sideband Output versus
Carrier Levels
I
Figure 12. Signal-Port Parallel-Equivalent
Input Resistance versus Frequency
~ 2.0
a
ffi
~
~ 1.6
z
o
~
....... 1'
O.B
0.4
/
~
/":
~
~
~
rn
w
a:
4OO'mv
so
0
so
200
10
I
5.0
~5.0
10
I, FREQUENCY (MHz)
~
~ 4.0
ct
~ 120
~
100
1O~
ffi
a:
BO
rn
(S 3.0
""
140
~
60
-'
40
§
~ 1.0
ct
~
~
~
ro
B.O~
6.05
cop
irl
"'-
"' I'..
a: 20
ct
2.0
5.0
10
20
I, FREQUENCY (MHz)
MOTOROLA ANALOG IC DEVICE DATA
so
100
14~
w
12~
a
(3
1.0
so
~O
Figure 14. Single-Ended Output Impedance
versus Frequency
w
o
.....
~ 1.0
1.0
Figure 13. Signal-Port Parallel-Equivalent
Input CapaCitance versus Frequency
.,,1'
II
'-
;;
D..
300mV
200·mV
0
~
\
'"
~ 100
!!2
Signal Input = 600 mV
."~
=>
§
+~
(.)
~ 1.2
~
SOO
w
LL
i
tOM
100
$-
00
1.0
10
I, FREQUENCY (MHz)
4.0::1
2.0~
o ~
100
8-49
MC1496, B
TYPICAL CHARACTERISTICS (continued)
Typical characteristics were obtained with circuit shown in Figure 5. Ie = 500 kHz (sine wave).
Ve 60 mVrms. IS 1.0 kHz. Vs 300 mVrms. TA 25°e. unless otherwise noted.
=
=
=
=
Figure 15: Sideband and Signal Port
Transadmittances versus Frequency
0'
..c::
E
.§.
w
0
Z
1.0
0.9
0
-
O.B
IS119,il ~Irt
......
r-.
11111111
0.7
~
0.6 -
0
~
0.5
(jj
Z
<
a:
0.4 -
N
0.2 -
I 11111
0.1 -
Y21
0.1
V
out
V. (Signal)
l-
o
I
= lout (Each Sideband)
y21
iD 10
~
"""'"
SideBand
iTI HI Sideband Transadmittance
0.3 -
~
Figure 16. Carrier Suppression
versus Temperature
.......
Z
a
en
w
\
=0
I
Vout
=0
IVei
-
;;:
a:
< 50
Mi9nall;o~ ~!~~il~mitt~nc~ 1111111
lout
= V.
20
a:
"- 30
"=>
en
a:
w 40
..........
en
" "-
:f;? 60
In
1.0
10
100
IC. CARRIER FREQUENCY (MHz)
70
-75 -50
1000
-25
~
(!I
w
!'I
10
II
~
0
w
0
Z
W
~
:l:
...J
(!I
Z
en
:J:Z
~ffi
RL=500Q
Re = 1.0 k
-20
< -30
0.01
II 11111 A _
RL
II 11111
+ 2re
0.1
V - Re
-
i:r;;- 20
,
- RL = 3.9 k
Re- 2.Ok
IIIIIIII I
r - IVCI = 0.5 Vdc -
g;
10
~iil
RL = 3.9 k (Standard
-10
150 175
Z
[
r- Re = 1.0 k Test Circuit)
>
0
25
50
75 100 125
TA. AMBIENT TEMPERATURE
(0C)
j:'!:
RL=3.9k
Re=500U
(!I
a'-'
-
...J
20
Z
«
/
Figure 18. Carrier Suppression
versus Frequency
Figure 17. Signal-Port Frequency Response
iD
...... r""
..........
0
= 0.5 Vdo
MC1496---r
(70°C)
II
"
;:Q
g~ 40
~~
i5~ 50
r\.
~
"-
10
--
(j)C3
II
1.0
I. FREQUENCY (MHz)
21C
30
100
g;
(J)
IC
60
70
0.05
Figure 19. Carrier Feedthrough
versus Frequency
0.1
./
~
V
...
r""
31C
"r-
0.5 1.0
5.0 10
IC. CARRIER FREQUENCY (MHz)
50
Figure 20. Sideband Harmonic Suppression
versus Input Signal Level
...J
j:'!:
o
Z
!:!il
10
<
~iD 20
,.0 _ _
=>~
"-0
i5~ 30
USffi
i51il
40
u:I ffi
50
~a:
-
--r
Q~ 60
enO
0.5 1.0
5.0
10
fC. CARRIER FREQUENCY (MHz)
8-50
50
~
ll::
=>
en
70
SO
./
fC±3IV
0
,/
I~ ......
,../
200
400
600
Vs. INPUT SIGNAL AMPLITUDE (mVrms)
800
MOTOROLA ANALOG IC DEVICE DATA
MC1496, B
Figure 21. Suppression of Carrier Harmonic
Sidebands versus Carrier Frequency
Figure 22. Carrier Suppression versus
Carrier Input Level
-'
i:!:
1111
~
10
ir;;- 20
:J:z
~ffi
;::9
0.05
a;:
=>
en
a;:
w
--
60
70
20
w
2f ±2fS
Ci)~
&
ijl
10
en
en
CL
CL
2fC±fS
~~ 40
~~ 50
:2z
0
IIII
30
0'"
f3
CD
Jfdll~
~aJ
0.1
0.5
1.0
a:
a;:
,..-
(3
en
<..>
>
5.0
10
50
30
40
50
60
70
-
fC=10MHz- 1 -
--r
",
......
./
o
- ---
"-
"100
fC, CARRIER FREQUENCY (MHz)
1 1 -f--
IC= 500kHz
f....":
200
300
400
500
VC, CARRIER INPUT LEVEL (mVrrns)
OPERATIONS INFORMATION
The MC1496, a monolithic balanced modulator circuit, is
shown in Figure 23.
This circuit consists of an upper quad differential amplifier
driven by a standard differential amplifier with dual current
sources. The output collectors are cross-coupled so that
full-wave balanced multiplication of the two input voltages
occurs. That is, the output signal is a constant times the
product of the two input signals.
Mathematical analysis of linear ac signal multiplication
indicates that the output spectrum will consist of only the sum
and difference of the two input frequencies. Thus, the device
may be used as a balanced modulator, doubly balanced mixer,
product detector, frequency doubler, and other applications
requiring these particular output signal characteristics.
The lower differential amplifier has its emitters connected
to the package pins so that an external emitter resistance
may be used. Also, external load resistors are employed at
the device output.
Signal Levels
. The upper quad differential amplifier may be operated
either in a linear or a saturated mode. The lower differential
amplifier is operated in a linear mode for most applications.
For low-level operation at both input ports, the output
signal will contain sum and difference frequency components
Figure 23. Circuit Schematic
and have an amplitude which is a function of the product of
the input signal amplitudes.
For high-level operation at the carrier input port and linear
operation at the modulating signal port, the output signal will
contain sum and difference frequency components of the
modulating signal frequency and the fundamental and odd
harmonics of the carrier frequency. The output amplitude will
be a constant times the modulating signal amplitude. Any
amplitude variations in the carrier signal will not appear in the
output.
The linear Signal handling capabilities of a differential
amplifier are well defined. With no emitter degeneration, the
maximum input voltage for linear operation is approximately
25 mV peak. Since the upper differential amplifier has its
emitters internally connected, this voltage applies to the
carrier input port for all conditions.
Since the lower differential amplifier has provisions for an
external emitter resistance, its linear signal handling range
may be adjusted by the user. The maximum input voltage for
linear operation may be approximated from the following
expression:
V =(15) (RE) volts peak.
This expression may be used to compute the minimum
value of RE for a given input voltage amplitude.
Figure 24. Typical Modulator Circuit
H 12
.--I===:::;;:::=+==:g vo,
(+) 6 Output
:t===J::===---1--J
0 :::(-::)
Carrier VCo10Input
8 (+)
- Vc 0.1l!F
Carrier ~H------O"'l
Input VS-----...,...----- -Vo
Modulating
Signal 10 k
Input
L....r----,-..J12
14
f
15
Carrier Null
6.8 k
-8.0Vdc =
VEE
8-51
MC1496, B
Figure 25. Voltage Gain and Output Frequencies
Carrier Input Signal (VC)
Approximate Voltage Gain
Output Signal Frequency(s)
RL Vc
Low-level de
2(R E
+ 2r e) (~T)
RL
High-level de
RE
fM
fM
+ 2re
RL VC(rms)
Low-level ae
2/2
High-level ae
(~T)
(R E
+ 2re)
0.637 RL
RE
fC±fM
fC±fM, 3fC±fM, 5fC±fM, . . .
+ 2re
NOTES: 1. Low-level Modulating Signal, VM, assumed in all cases. Vc is Carrier Input Voltage.
2. When the output signal contains muniple frequencies, the gain expression given is for the output amplitude of
each of the two desired outputs, fC + fM and fC - fM'
3. All gain expressions are for a single.... nded output. For a differential output connection, multiply each
expression by two.
4. RL = Load resistance.
5. RE = Emiller resistance between Pins 2 and 3.
6. re = Transistor dynamic emitter resistance, at 25°C;
26mV
re = 15 (rnA) .
7 .. K = Boltzmann's Constant, T = temperature in degrees Kelvin, q = the charge on an electron.
~T = 26 mV at room temperature
II
The gain from the modulating Signal input port to the
output is the MC1496 gain parameter which is most often of
interest to the designer. This gain has significance only when
the lower differential amplifier is operated in a linear mode,
but this includes most applications of the device.
As previously mentioned, the upper quad differential
amplifier may be operated either in a linear or a saturated
mode. Approximate gain expressions have been developed
for the MC1496 for a low-level modulating signal input and
the following carrier input conditions:
1) Low-level dc
2) High-level dc
3) Low-level ac
4) High-level ac
These gains are summarized in Figure 25, along with the
frequency components contained in the output signal.
APPLICATIONS INFORMATION
Double sideband suppressed carrier modulation is the
basic application of the MC1496. The suggested circuit for
this application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate the
MC1496 with a single dc supply voltage instead of dual
supplies. Figure 26 shows a balanced modulator designed
for operation with a Single 12 Vdc supply. Performance of this
circuit is similar to that of the dual supply modulator.
AM Modulator
The circuit shown in Figure 27 may be used as an
amplitude modulator with a minor modification.
8-52
All that is required to shift from suppressed carrier to AM
operation is to adjust the carrier null potentiometer for the
proper amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown in
Figure 27 does not have sufficient adjustment range.
Therefore, the modulator may be modified for AM operation
by changing two resistor values in the null circuit as shown in
Figure 28.
Product Detector
The MC1496 makes an excellent SSB product detector
(see Figure 29).
This product detector has a sensitivity of 3.0 microvolts
and a dynamic range of 90 dB when operating at an
intermediate frequency of 9.0 MHz.
The detector is broadband for the entire high frequency
range. For operation at very low intermediate frequencies
down to 50 kHz the 0.1 I1F capaCitors on Pins 8 and 10
should be increased to 1.0 11F. Also, the output filter at Pin 12
can be tailored to a specific intermediate frequency and audio
amplifier input impedance.
As in all applications of the MC1496, the emitter resistance
between Pins 2 and 3 may be increased or decreased to
adjust circuit gain, sensitivity, and dynamic range.
This circuit may also be used as an AM detector by
introducing carrier signal at the carrier input and an AM signal
at the SSB input.
The carrier signal may be derived from the intermediate
frequency signal or generated locally. The carrier signal may
be introduced with or without modulation, provided its level is
sufficiently high to saturate the upper quad differential
MOTOROLA ANALOG IC DEVICE DATA
MC1496,B
amplifier. If the carrier signal is modulated, a 300 mVrms
input level is recommended.
Doubly Balanced Mixer
The MC1496 may be used as a doubly balanced mixer
with either broadband or tuned narrow band input and output
networks.
The local oscillator signal is introduced at the carrier input
port with a recommended amplitude of 100 mVrms.
Figure 30 shows a mixer with a broadband input and a
tuned output.
Frequency Doubler
The MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
Figures 31 and 32 show a broadband frequency doubler
and a tuned output very high frequency (VHF) doubler,
respectively.
Phase Detection and FM Detection
The MC1496 will function as a phase detector. High-level
input signals are introduced at both inputs. When both inputs
are at the same frequency the MC1496 will deliver an output
which is a function of the phase difference between the two
input signals.
An FM detector may be constructed by using the phase
detector principle. A tuned circuit is added at one of the inputs
to cause the two input signals to vary in phase as a function
of frequency. The MC1496 will then provide an output which
is a function of the input signal frequency.
TYPICAL APPLICATIONS
Figure 26. Balanced Modulator
(12 Vdc Single Supply)
1.0k
820
0.1/iF
25/iF 1::
51
Carrier Input 15 V -=- 0.1/iF
60 mVrms
1.3k
RL
3.0k
r-4I-:-o-W-lf--+'i
6
- Vc 0.1/iF
DSB
Carrier ~1-~-----<>-'7I
0.1/iF Output Input
8
10
MC1496
Modulatin~ +
4
Signal Input 10/iF
300 mVrms 15V
25/iF 14
15V
+
Carrier
Null 50 k
Figure 27. Balanced Modulator-Demodulator
VCC
12Vdc
Vs
10 k
100
100
MC1496
1-:1-<2)--~.. -Yo
"""---"""""5
Modulating
Signal
Input
-
3.9 k
+Vo
1-;;<>-+--+..
L - _ - "_ _-+ VEE
Carrier Null
-=-
II
6.8 k
15
-B.O Vdc -=-
Figure 29. Product Detector
(12 Vdc Single Supply)
Figure 28. AM Modulator Circuit
VCC
,--.r----",8N20'r--~~:_:::-"1"'.3..,.k_-,rl...,12 Vdc
RL
1.0k
3.0 k
3.9k
- Vc 0.1/iF
Carrier ~
Input vs
+Vo Carrier Input
300 mVrrns
MC1496
4
Modulating
Signal
Input
12
5
Carrier Adjust
15 6.8 k
VEE
-B.OVdc -=-
MOTOROLA ANALOG IC DEVICE DATA
-Yo
SSB Input
0.005
/iF
AF
1.0 k 1.0 /iFOutput
L.-,-,----r~~T~"'I--it~ 10 k
10k
10.00510.005
-=-/iF
'---"'Mr--' -=- /iF
8-53
MC1496, B
Figure 30. Doubly Balanced Mixer
(Broadband Inputs, 9.0 MHz Tuned Output)
1.0k
Figure 31. Low-Frequency Doubler
1.0k
'ri
RFC
100 !IIi
001 !!F
RFlnput ,
51
"'-;--T""' 12
1.0k
9.0 MHz
l1
~~~Ol)
pF
6.8k""
Output
MC1496
9.5 F
55.o-M
3.9k
C2.-------O-"-I
12
L
9O-480pF
.".
10k
L.....:.::::::..:.=".... VEE"'"
100
10 k
100
14
-B.OVdc
6.ak
L1 = 44 Tums AWG No. 28 Enameled Wire, Wound
on Micrometals Type 44...£ Toroid Core.
15
VEE
-B.OVdc
Figure 32. 150 to 300 MHz Doubler
..
r.L.::.-....&..::~>--+~~~
0.001 !!F.
150 MHz:_~~_--c>-,;
Input
1.o-10pF
6.ak
Balance
i
I
$>
VEE
-B.OVdc
L1 =1 TumAWG
No. 18 Wire, 7/32" ID
!!'
+
I
.g
.g
U)
,.a,
.,.,
I
+
.g
300 MHz
Output
RL = 501)
g
l
Input
I
I
I
-
>rt-]-1
-::r
10k
-
Electret
(alternate)
Microphone
and biasing
11000P
47k
I
r-'VVv-.--I
I
I
I
I
I
RbI
I
L ___
f-=--t----If---....---;EJ
i
Cc2
~
C4
C5
RF output
5.DtolDdBm
(see Note 4)
____________. -____________~~~~
I-=-
VCC = 9.DVdc
I.D!'F
tantalum
NOTES:
1. Components versus output frequency:
en
2.
3.
4.
5.
6.
..en.
Output RF
X1 (MHz)
!.I..M:!l
illIl!f)
!.2.fu!:!)
B!!:L
~
Q
~
~
~
~
49.7 MHz
16.5667
3.3-4.7
0.22.
0.22
330
390 k
33 P
33 P
33 P
470 P
33 P
47 P
220 P
76 MHz
12.6000
5.1
0.22
0.22
150
300 k
68 P
10 P
68 P
470 P
12 P
20 P
120 P
12.05
5.6
0.15
0.10
150
220k
47p
10p
68p
1000p
18p
12p
33p
144.6 MHz
Crystal X1 is fundamental mode. calibrated for parallel resonance with a 32 pF load. The final output frequency is generated by frequency multiplication within
the MC2833 IC. The RF output buffer (Pin 14) and 02 transistor are used as a frequency tripler and doubler, respectively, in the 76 and 144.6 MHz transmitters.
The 01 output transistor is a linear amplifier in the 49.7 MHz and 76 MHz transmitters, and a frequency doubler in the 144.6 MHz transmitter.
All coils used are 7 mm shielded inductors, CoilCran series M1175A, M1282A-M1289A, M1312A or equivalent.
Power output is = + 10 dBm for 49.7 MHz and 76 MHz transmitters, and =+ 5.0 dBm forthe 144.6 MHz transmitter at VCC = 8.0 V. Power output drops with
10werVCC·
All capacitors in microfarads, inductors in Henries and resistors in Ohms unless otherwise specified.
Other frequency combinations may be set-up by simple scaling of the 3 examples shown.
MOTOROLA ANALOG IC DEVICE DATA
8-57
MC2833
Figure 3. BufferlMultiplier (x3, Pin 14)
(16 MHz Fundamental)
Figure 4. Input to Doubler (Pin 13)
(49.7 MHz x 3 Component)
Figure 5. Doubler Output 76 MHz (Pin 11)
Figure 6. Spectrum
Figure 7. Output Spectrum (49.7 MHz)
Figure 8. Modulation Spectrum
(1.0 kHz Showing Carrier Null)
-43dB
8-58
MOTOROLA ANALOG IC DEVICE DATA
MC2833
Figure 9. 144.6 MHzlx12 Multiplier
Figure 10. Circuit Side View
II
Figure 11. Ground Plane on Component Side
MOTOROLA ANALOG IC DEVICE DATA
8-59
MC2833
Figure 12. Component View
rn. «
f'IIl4t----------
2.0" ----.".-----~
..I
,X1 XTAL
~h
'~.~. ~
100Kl
•....
1~.
+ 1.0 R!!.e
1K-l
•
,@)
4.7K-
...
2.7K
~
Rbl--
.-
MC2833P
NOTES:
0
Positive artwork provided.
o Drtll holes must be plated to ensure making all ground (VEE) connectionsl
o Resistors labelled' are used for biasing of electret microphone if used.
o
Capacitors labelled "SM" are silver mica.
o Final board size 1.5" x 2.0".
&:-60
MOTOROLA ANALOG IC DEVICE DATA
MC2833
Figure 13. Circuit Schematic
Pin 4
rq
Pin 9
~
~O
Pin 8
Pin 11
.lI,L
~
~k
Pin10
rtr.~
.lI v----1
Y
520
Y
Y
TP~
~
Py4
10k
115k
24k
Pin 13
Pin16
L:ri,t
Pin 12
~
Pin 15
·A.lIf-
~LA
Pin 7
LJ
50
50
i,!.
T
6.8 k
570
-'III. ~.lIlL
Pin 5
LJ LJ
470
i(t
T
1
18 k
1
18k
1
18k
~,z
~11!
4.7k
Pi~1
2.2k
I
~
lr--i
Pin2
610
~
120
in3
~
~L
2.2 k
~ [L
~
4.7k
2.2k
8k
~
P
20.2k
~
2.2 k
LI
[JL
8.5k
120
710
ItT
~11!
fl
56k
,
~
n
9.7k
18k
LT
Pin 6
MOTOROLA ANALOG IC DEVICE DATA
8-61
®
MOTOROLA
MC3335
Low Power Narrowband
FM Receiver
· .. includes dual FM conversion with Oscillators, Mixers, Quadrature
Discriminator, and Meter Drive/Carrier Detect Circuitry. The MC3335 also
has a comparator circuit for FSK detection.
• Complete Dual Conversion Circuitry
• Low Voltage: VCC
= 2.0 to 6.0 Vdc
• Low Drain Current (Typical 3.6 mA with VCC
LOW POWER
DUAL CONVERSION
FM RECEIVER
= 3.0 Vdc)
SEMICONDUCTOR
TECHNICAL DATA
• Excellent Se~sitivity: - 3.0 dB Input Limiting = 0.71lV
• Externally Adjustable Carrier Detect Function
• Separate Data Shaping Output Circuitry
-
• Data Rate Up to 35000 Baud Detectable
• 60 dB RSSI Range
• Low Number of External Parts Required
• Manufactured in Motorola's MOSAIC® Process Technology
• MC13135 is Preferred for New Designs
PSUFFIX
PLASTIC PACKAGE
CASE 738
OW SUFFIX
PLASTIC PACKAGE
CASE751D
(S0-20L)
PIN CONNECTIONS
Simplified Application as a Fixed Receiver
1stMixerlnput
11--_~
_ _ O 1st Mixer Input
2nd Lo Emitter 2
2ndLoBase 3
2nd Mixer Output 4
....---.., J......,1",,7 1st Mixer Output
Vcc
Umiterlnput 6
limIter Decoupling L!7.l'T........~....
limiter Decoupling
[!8[]--v*-++
MeterDrive 9
14 Compara1or Output
13 Comparatorlnput
I TlI''Il.'--_ "l!1,,2 Detector Output
11 Quadrature eon
'----I~
---,
10 k
To Carrier
Delecllndicalor
8-62'
Data
In
L __ -'
I,p = 660l1H
Cp = 180pF
_
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC3335DW
S0-20
f-M-C3-3-3-5-P---1 TA = - 40 to +B5'C f-p-I-as-t'-c-D-Ip--I
MOTOROLA ANALOG IC DEVICE DATA
MC3335
MAXIMUM RATINGS (TA = 25°e, unless otherwise noted)
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
5
Vee(max)
7.0
Vdc
Operating Supply Voltage Range
(Recommended)
5
Vee
2.0 to 6.0
Vdc
1,20
VI-20
1.0
Vrms
-
TJ
150
°e
TA
-40to+85
°e
TstQ
-65to+150
°e
Input Voltage (Vee> 5.0 Vdc)
Junction Temperature
Operating Ambient Temperature Range
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (Vee = 5.0 Vdc, 10 = 49.7 MHz, Deviation = 3.0 kHz, TA = 25 o e, test circuit of Figure 2,
unless otherwise noted.)
Characteristic
Drain Current
Pin
Min
Typ
Max
Unit
5
4.5
7.0
mAde
0.7
2.0
J.lVrms
12
-
250
-
mVrms
mVrms
-
Input for - 3.0 dB Limiting
Recovered Audio (RF Signal Level
=1.0 mY)
12
-
250
-
Carrier Detect Threshold (below VCC)
9
0.64
-
Vdc
Meter Drive Slope
9
100
690
-
J.lAldB
Input for 20 dB (S + N/N)
-
7.2
-
Noise Output (RF Signal Level
=0 mY)
First Mixer Conversion Voltage Gain
-
Second Mixer Conversion Voltage Gain
-
Detector Output Resistance
12
First Mixer 3rd Order Intercept (Input)
First Mixer Input Resistance (Rp)
First Mixer Input Capacitance (C p )
1.3
-20
-
-
18
21
1.4
J.lVrms
dBm
n
pF
dB
dB
kG
Figure 1. Test Circuit
RF Input '-------1J2.6
49.7 MHzr---l
0.1
II
Vcc
20 k
56pF
RA
---,
10 k
To Carrier
Detect Indicator
MOTOROLA ANALOG IC DEVICE DATA
In
L __ ...l
~p
= 660 J.lH
Cp = 180pF
8-63
II
MC3335
Figure 3. Drain Current, Recovered
Audio versus Supply.
Figure 2. Imeter versus Input
12
11
10
9.0
......
VCC
~C3335
./
~
E? 6.0
S.O
4.0
ICC. Carr. Det. Low (RF in = 10 mY) "-
./
5.0
./
-
/'"
3.0
II
II
2.0
1.0
3.0
2.0
-130 -120 -110 -100 -90
-70
-60 -50
o
-40 -30
Figure 4. (S + N), N of 2nd Mixer
~ -20
20
o
-C
""-
z
;
10
S+N
~ -30
-10
i"...
-40
-SO
-60
~-20
"'"
1.0
""-..
~
N
-
2.0
3.0
4.0
5.0
6.0
7.0
o
8.0
I
S+N
l"'-.
~ 12
-50
'" """-
N
7.5k
MC3335~
0.01
-70
-60 -SO
-80
-130 -120 -110 -100 -90
-40 -30
Figure 6. 1st Mixer 3rd Order Intermodulation
/
10
3.0
1/ -,'
r
/
iii' -30
/
-SO
/
~
/3rd Order Intermod._
Products
V
/
-80 /
-100 -90 -80
u
/
Desired Products/
-40
>'"
---\
-
2.0
\
1.0
-
/
/
-70
-60
-50 -40 -30
RF INPUT (dBm)
-60 -50 -40 -30
Figure 7. Detector Output versus Frequency
",/
"'/
-20
-70
4.0
t/
o
-10
-80
RF INPUT (dBm)
20
8-64
'"
300>
Figure 5. (S + N)/N versus Input
RF INPUT (dBm)
-70
>
.E.
...........
-60
-80
-130 -120 -110 -100 -90 -80 -70
-60
400
100
~-30
z
+ -40
-70
~
~
VCC(V)
20
10
-10
>
~ Recovered Audio
200
RF INPUT (dBm)
o
f,--
~c--
JJ
o
-80
-- ---
.....-:::
600
....... >- soo I
ICC. Carr. Det. High (RF in = 0 mV) ......
~
g
4.0
./
,.--
800
700
6.0
/'
8.0
7.0
8.0
7.0
-20
-10
0
o
-40
-30
-20
-10
0
10
-20
!---
30
40
.RELATIVE INPUT FREQUENCY (kHz)
MOTOROLA ANALOG IC DEVICE DATA
MC3335
CIRCUIT DESCRIPTION
The MC3335 is a complete FM narrowband receiver from
antenna input to audio preamp output. The low voltage dual
conversion design yields low power drain, excellent
sensitivity and good image rejection in narrowband voice and
data link applications.
In the typical application diagram, the' first mixer amplifies
the signal and converts the RF input to 10.7 MHz. This IF
signal is filtered externally and fed into the second mixer,
which further amplifies the signal and converts it to a 455 kHz
IF signal. After external bandpass filtering, the low IF is fed
into the limiting amplifier and detection circuitry. The audio is
recovered using a conventional quadrature detector.
Twice-IF filtering is provided internally.
The input signal level is monitored by meter drive circuitry
which detects the amount of limiting in the limiting amplifier.
The voltage at the meter drive pin determines the state of the
carrier detect output which is active low.
APPLICATIONS INFORMATION
The first local oscillator can be run using a free running LC
tank, as a VCO using PLL synthesis, or driven from an
external crystal oscillator. At higher VCC values (6.0 to
7.0 V), it has been run to 170 MHz. The second local
oscillator is a common base Colpitts type which is typically
run at 10.245 MHz under crystal control.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 22 dB (typical), respectively. Mixer gain is
stable with respect to supply voltage. For both conversions,
the mixer impedances and pin layout are designed to allow
the user to employ low cost, readily available ceramic filters.
Overall sensitivity is shown in Figure 5. The input level for
20 dB (S + N)/N is 1.3 !LV using the two-pole post-detection
filter as demonstrated.
MOTOROLA ANALOG IC DEVICE DATA
Following the first mixer, a 10.7 MHz ceramic bandpass
filter is recommended. The 10.7 MHz filtered signal is then
fed into one second mixer input pin, the other input pin being
connected to VCC. Pin 5 (VCC) is treated as a common point
for emitter-driven signals.
The 455 kHz IF is typically filtered using a ceramic
bandpass filter, then fed into the limiter input pin. The limiter
has 10 !LV sensitivity for -3.0 dB limiting, flat to 1.0 MHz.
The output of the limiter is internally connected to the
quadrature detector, including a quadrature capacitor. A
parallel LC tank is needed externally from Pin 11 to VCC.
A 39 k.Q shunt resistance is included which determines the
peak separation of the quadrature detector; a smaller value
will increase the spacing and linearity but decrease
recovered audio and sensitivity.
A data shaping circuit is available and can be coupled to
the recovered audio output of Pin 12. The circuit is a
comparator which is designed to detect zero crossings of
FSK modulation. Data rates of up to 35000 baud are
detectable using the typical application. Hysteresis is
available by connecting a high-valued resistor from Pin 13 to
Pin 14. Values below 120 kn are not recommended as the
input signal cannot overcome the hysteresis.
The meter drive circuitry detects input Signal level by
monitoring the limiting of the limiting amplifier stages.
Figure 2 shows the unloaded current at Pin 9 versus input
power. The meter drive current can be used directly (RSSI)
or can be used to trip the carrier detect circuit at a specified
input power. To do this, pick an RF trip level in dBm. Read the
corresponding current from Figure 2 and pick a resistor such
that:
R9 =0.64 Vdc / 19
Hysteresis is available by connecting a high-valued
resistor RH between Pin 9 and 10. The formula is:
Hysteresis =VCcI(RH x 10- 7) dB
8-65
II
:
®
MOTOROLA
MC3356
Wideband FSK Receiver
The MC3356 includes Oscillator, Mixer, Limiting IF Amplifier, auadrature
Detector, Audio Buffer, Squelch, Meter Drive, Squelch Status output, and
Data Shaper comparator. The MC3356 is designed for use in digital data
communciations equipment.
• Data Rates up to 500 kilobaud
• Excellent Sensitivity: - 3 dB Limiting Sensitivity
30llVrms @ 100 MHz
• Highly Versatile, Full Function Device, yet Few External Parts are
Required
• Down Converter Can be Used Independently - Similar to NE602
WIDEBAND
FSK
RECEIVER
SEMICONDUCTOR
TECHNICAL DATA
-
PSUFFIX
PLASTIC PACKAGE
CASE 738
OW SUFFIX
PLASTIC PACKAGE
CASE 751D
(S0-20L)
Figure 1. Representative Block Diagram
RF
Vee
PIN CONNECTIONS
RF
Ground
20;..;
,..-_ _ _ _--F
19
f--o
RF
Input
RFGround
Ground
OSCEmitter
~=,-,,;;;:=:=-r""'---'-o Data
Output
Vee
ose Collector
RFVee
Mixer Output
Ceramic
Filter
15
14
*' _
Squelch
Status
Hysteresis
~
12
10
Squelch
Adjust
(Meter)
IFVce
15 Squelch Status
LimHerlnput
14 Squelch Control
LimHerBias
13 Buffered Output
Limiter Bias
12 Demodulator
Filter
Quad Bias
11 Quad Input
11
Quadrature Detector
r---,
'Ii k
I I an
ORDERING INFORMATION
Device
MC3356DW
Vec
H6
MC3356P
Operating
Temperature Range
TA = - 40 to +85°C
Package
S0-20L
Plastic DIP
MOTOROLA ANALOG IC DEVICE DATA
MC3356
MAXIMUM RATINGS
Rating
Power Supply Voltage
Operating Power Supply Voltage Range (Pins 6, 10)
Operating RF Supply Voltage Range (Pin 4)
Symbol
Value
Unit
VeC(max)
15
Vdc
Vee
3.0 to 9.0
Vdc
RFVee
3.0 to 12.0
Vdc
Junction Temperature
TJ
150
°e
Operating Ambient Temperature Range
TA
-40to+85
°e
Tstg
- 65 to + 150
°e
PD
1.25
W
Storage Temperature Range
Power Dissipation, Package Rating
=
ELECTRICAL CHARACTERISTICS (Vee 5.0 Vdc, 10
TA = 25°C, test circuit 01 Figure 2, unless otherwise noted.)
=100 MHz, losc =110.7 MHz, t.1 =±75 kHz, Imod =1.0 kHz, 50 () source,
Characteristics
Min
Typ
Max
Unit
-
20
25
mAdc
Input lor - 3 dB limiting
-
30
-
I1Vrms
" (S+N)
Input I or 50 dB
qUieting
-N-
-
60
-
I1Vrms
Mixer Voltage Gain, Pin 20 to Pin 5
-
Drain Current Total, RF Vee and Vee
2.5
-
Mixer Input Resistance, 100 MHz
-
260
-
()
Mixer Input Capacitance, 100 MHz
-
5.0
-
pF
Mixer/Oscillator Frequency Range (Note 1)
-
0.2 to 150
-
MHz
IF/Quadrature Detector Frequency Range (Note 1)
-
0.2 to 50
-
MHz
AM Rejection (30% AM, RF Vin = 1.0 mVrms)
-
50
-
dB
Demodulator Output, Pin 13
-
Vrms
Meter Drive
-
0.5
7.0
-
IlAIdB
Squelch Threshold
-
0.8
-
Vdc
NOTE: 1. Not taken in Test Circuit of Figure 2; new component values required.
Figure 2. Test Circuit
Squelch
Status
Demod
Out
Data Output
47k
100 MHz
~
51
-=
-=
11 -110.7 MHz, OAI1H
7T #22,3116 Form
w/slug & can
L2 -10.7 MHz, 1.511H
20T #30,3116 Form
w/slug & can
T1-muRata
SFEl 0.7 MA5-Z
or
KYOCERA
KBF10.7MN-MA
47k
130k
3.3k
3.0k
10k
3.3 k
20
-=
19
RF Input
Ground
RF
Gnd
OSC
EM.
Data
Output
OSC
COL.
16
Comp(-)
15
Squelch
Status
14
Squelch
Control
Domed
Out
RF
VCC
0.01
5.6 pF
15 pF
17
Comp(+)
t
MOTOROLA ANALOG IC DEVICE DATA
::f
l1
330
8-67
II
MC3356
Figure 3. Output Components of Signal,
Noise, and Distortion
10
I· I I
III II
S+N+D
![ -10 V~ -20
5
~ -30 i"""'";::
!;;r
;rl-40
a:
-50
--
-60
0.01
Figure 4. Meter Current versus Signal Input
700
V
~
1
10= 100 MHz
Im = 1.0 kHz
lif =±75kHz
r-
~ 500
z
a::
u
a: 200
I
~
N
0.1
400
~
w
a: 300
a:
::l.
N+D
~
600
:::;; 100
1.0
10
0
0.010
0.1
INPUT (mVrms)
1.0
10
PIN 20 INPUT (mVrms)
100
1000
GENERAL DESCRIPTION
This device is intended for single and double conversion
VHF receiver systems, primarily for FSK data transmission
up to 500 K baud (250 kHz). It contains an OSCillator, mixer,
limiting IF, quadrature detector, signal strength meter drive,
and data shaping amplifier.
The oscillator is a common base CCllpitis type which can
be crystal controlled, as shown in Figure 1, or L-G controlled
as shown in the other figures. At higher VCC, it" has been
operated as high as 200 MHz. A mixer/oscillator voltage gain
of 2 up to approximately 150 MHz, is readily achievable.
The mixer functions well from an input signal of
10 j.tVrms, below which the squelch is unpredictable, up to
about 10 mVrms, before any evidence of overload.
Operation up to 1.0 Vrms input is permitted, but non-linearity
of the meter output is incurred, and some oscillator pulling is
suspected. The AM rejection above 10 mVrms is degraded.
The limiting IF is a high frequency type, capable of being
operated up to 50 MHz. It is expected to be used at 10.7 MHz
in most cases, due to the availability of standard ceramic
resonators. The quadrature detector is internally coupled to
the IF, and a 5.0 pF quadrature capaCitor is internally
provided. The -3dB limiting sensitivity of the IF itself is
approximately 50 j.tV (at Pin 7), and the IF can accept signals
up to 1.0 Vrms without distortion or change of detector
quiescent dc level.
The IF is unusual in that each of the last 5 stages of the
6 state limiter contains a signal strength sensitive, current
sinking device. These are parallel connected and buffered to
produce a signal strength meter drive which is fairly linear for
IF input signals of 10 j.tV to 100 mVrms (see Figure 4).
A simple squelch arrangement is provided whereby the
meter current flowing through the meter load resistance flips
a comparator at about 0.8 Vdc above ground. The signal
strength at which this occurs can be adjusted by changing
the meter load resistor. The comparator (+) input and output
are available to permit control of hysteresis. Good positive
8-68
action can be obtained for IF input signals of above 30
j.tVrms. The 130 k.Q resistor shown in the test circuit provides
a small amount of hysteresis. Its connection between the
3.3 k resistor to ground and the 3.0 k pot, permits adjustment
of squelch level without changing the amount of hysteresis.
The squelch is internally connected to both the
quadrature detector and the data shapero The quadrature
detector output, when squelched, goes to a dc level
approximately equal to the zero signal level unsquelched.
The squelch causes the data shaper to produce a high (VCC)
output.
The data shaper is a complete "floating" comparator,
with back to back diodes across its inputs. The output of the
quadrature detector can be fed directly to either input of this
amplifier to produce an output that is either at VCC or VEE,
depending upon the received frequency. The impedance of
the biasing can be varied to produce an amplifier which
"follows" frequency detuning to some degree, to prevent data
pulse width changes.
When the data shaper is driven directly from the
demodulator output, Pin 13, there may be distortion at Pin 13
due to the diodes, but this is not important in the data
application. A useful note in relating highllow input frequency
to logic state: low IF frequency corresponds to low
demodulator output. If the oscillator is above the incoming
RF frequency, then high RF frequency will produce a logic
low (input to (+) input of Data Shaper as shown in Figures 1
and 2).
APPLICATION NOTES
The MC3356 is a high frequency/high gain receiver that
requires following certain layout techniques in designing a
stable circuit configuration. The objective is to minimize or
eliminate, if possible, any unwanted feedback.
MOTOROLA ANALOG IC DEVICE DATA
MC3356
Figure 5. Application with Fixed Bias on Data Shaper
Car. DetOut
OVor4.0V
~
-=
3.3 k
:}"& ,.
I
I
L.~_..J
20
RF Input
19
18
Ground
Data
Output
11
17
Comp(+)
Squelch
Status
Squelch
Control
Demod
Out
Demod
Fiher
Quad
Input
MC3356
RF
Gnd
OSC
EM.
OSC
COL.
Limiter
Bias
Limiter
Bias
Quad
Bias
10
S.OV
II
82
APPLICATION NOTES (continued)
Shielding, which includes the placement of input and
output components, is important in minimizing electrostatic or
electromagnetic coupling. The MC3356 has its pin
connections such that the circuit designer can place the
critical input and output circuits on opposite ends of the chip.
Shielding is normally required for inductors in tuned circuits.
The MC3356 has a separate VCC and ground for the RF
and IF sections which allows good external circuit isolation by
minimizing common ground paths.
Note that the circuits of Figures 1 and 2 have RF,
Oscillator, and IF circuits predominantly referenced to the
plus supply rails. Figure 5, on the other hand, shows a
suitable means of ground referencing. The two methods
produce identical results when carefully executed. It is
important to treat Pin 19 as a ground node for either
approach. The RF input should be "grounded" to Pin 1 and
then the input and the mixer/oscillator grounds (or RF Vce
bypasses) should be connected by a low inductance path to
Pin 19. IF and detector sections should also have their
MOTOROLA ANALOG IC DEVICE DATA
bypasses returned by a separate path to Pin 19. VCC and
RF VCC can be decoupled to minimize feedback, although
the configuration of Figure 2 shows a successful
implementation on a common 5.0 V supply. Once again, the
message is: define a supply node and a ground node and
return each section to those nodes by separate, low
impedance paths.
The test circuit of Figure 2 has a 3 dB limiting level of
30 iJ,V which can be lowered 6 db by a 1:2 untuned
transformer at the input as shown in Figures 5 and 6. For
applications that require additional sensitivity, an RF amplifier
can be added, but with no greater than 20 db gain. This will
give a 2.0 to 2.5 iJ,V sensitivity and any additional gain will
reduce receiver dynamic range without improving its
sensitivity. Although the test circuit operates at 5.0 V, the
mixer/oscillator optimum performance is at 8.0 V to 12 V. A
minimum of 8.0 V is recommended in high frequency
applications (above 150 MHz), or in PLL applications where
the oscillator drives a prescaler.
8-69
MC3356
Figure 6. Application with Self-Adjusting Bias on Data Shaper
5.0V
Data
Out
Car. Dot. Out
OVor4.0V
130k
3.3k
15 k
~_1~~ ~ ~~1~0_k~~ ~~ L1~5 ~~ ~1~3 ~~12~~~1~1~~~----------'
__
-=
RF Input
__
Ground
__
Data
Output
Comp(+)
__
__
Comp(-) Squelch
Status
__
Squelch
Control
Demod
Out
__
Demod
Fi"er
Quad
Input
f= 10.7
150 pF
APPLICATION NOTES (continued)
EI
Depending on the external circuit, inverted or
noninverted data is available at Pin 18. Inverted data makes
the higher frequency in the FSK signal a "one" when the local
oscillator is above the incoming RF. Figure 5 schematic
shows the comparator with hysteresis. In this circuit the dc
reference voltage at Pin 17 is about the same as the
demodulated output voltage (Pin 13) when no signal is
present. This type circuit is preferred for systems where the
data rates can drop to zero. Some systems have a low
frequency limit on the data rate, such as systems using the
MC3850 ACIA that has a start or stop bit. This defines the
low frequency limit that can appear in the data stream.
8-70
Figure 5 circuit can then be changed to a circuit configuration
as shown in Figure 6. In Figure 6 the reference voltage for
the comparator is derived from the demodulator output
through a low pass circuit where 't is much lower than the
lowest frequency data rate. This and similar circuits will
compensate for small tuning changes (or drift) in the
quadrature detector.
Squelch status (Pin 15) goes high (squelch off) when the
input signal becomes greater than some preset level set by
the resistance between Pin 14 and ground. Hysteresis is
added to the circuit externally by the resistance from Pin 14to
Pin 15.
MOTOROLA ANALOG Ie DEVICE DATA
!!l:
Figure 7. Internal Schematic
a
.
>
»
I
::0
o
~
~
z
»
....
oG)
(')
c
~
o
)
1.0k
i'..:
1.0k
~
ICP
'"
~
.1'-:'
r~
1.0k
5.0k
~"ro,
~
IT
1.0k
c
»~
5.0k
330
T
330
~
'"'
20k
~
'"
1
12
10k
92
...
tr.1,;;+t.
'91
"·0
r
•
1v'
1
J
W
93
86
~
r1
~r-J v.
85
~~.
,"
, 0~-r,.
20pF
'"' ~
.. ,
tl" if-
20k
10
m
5.0k
ro,
~
~~
!O
."
16
,
:s:
11
o
Co)
Co)
6
13
1.0k
1.Ok
1.0k
1.0k
1.0k
~
1.Ok
1.0k
1.Ok
~
16
17
1.0k
1.0k
1.0k
~ ~1t{
J:t~~
21
J:f
23
50k
V
~
~6
f-.::
;:
50pF
50k
il
~
K
5~
58
'-l
~
32
~~
~
r;9
r...;
" 27
64
'l~
3~
rt
2:
9
~
10k
10k
10k
10k
,
1.0k
~
~
40
43
42
1.0k
'-l
H~
28
~ ~
~
1.0k
36
25
I
0--
1.0k
{10k
1.0k
2.5k
46
, 45
48
47
,
57
,,-1
'-l
~
55 '"'"'
135
135
135
'-l
56
~
54
'-l
53"-1
~
~
,,1
135
135
34
,
5i-i 51'"'1 50
,...-1 ,,-i
49
,
...t
\
:5~ '35
135
~
135
225
,
i
II
®
MOTOROLA
MC3357
Low Power Narrowband FM IF
· .. includes Oscillator, Mixer, Limiting Amplifier, Quadrature Discriminator,
Active Filter, Squelch, Scan Control, and Mute Switch. The MC3357 is
designed for use.in FM dual conversion communications equipment.
• Low Drain Current (3.0 mA (Typical) @ VCC
=6.0 Vdc)
LOW POWER
FMIF
• Excellent Sensitivity: Input Limiting Voltage (- 3.0 dB) 5.0 flV (Typical)
=
• Low Number of Extemal Parts Required
SEMICONDUCTOR
TECHNICAL DATA
• Recommend MC3372 for ReplacemenVUpgrade
PSUFFIX
PLASTIC PACKAGE
CASE 648
o SUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
PIN CONNECTIONS
Figure 1. Representative Block Diagram
Vee
Mixer
OU1put
Umiter
Input
Umiter
OU1put
Quad
Input
ORDERING INFORMATION
Device
MC3357D
MC3357P
8-72
Operating
Temperature Range
TA = - 30 to +70°C
Package
S0-16
Plastic DIP
MOTOROLA ANALOGIC DEVICE DATA
MC3357
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted)
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
4
VCc(max)
12
Vdc
Operating Supply Voltage Range
4
VCC
4t08
Vdc
Detector Input Voltage
8
-
1.0
Vp-p
Input Voltage (VCC ~ 6.0 Volts)
16
V16
1.0
VRMS
Mute Function
14
V14
-0.5 to 5.0
Vpk
Junction Temperature
TJ
150
°c
Operating Ambient Temperature Range
-
TA
-30to+70
°C
Storage Temperature Range
-
Tsta
-65to+150
°C
ELECTRICAL CHARACTERISTICS (VCC = 6.0 Vdc, 10 = 10.7 MHz, AI = ±3.0 kHz, lmod = 1.0 kHz, TA = 25°C, unless otherwise noted.)
Characteristic
Drain Current
Squelch Off
Squelch On
Pin
Min
Typ
4
-
2.0
3.0
5.0
5.0
10
J.lV
3.0
-
Vdc
-
mVrms
-
-
400
9
200
350
Input limiting Voltage (- 3 dB limiting)
16
Detector Output Voltage
9
Detector Output Impedance
Recovered Audio Output Voltage (Vin = 10 mY)
Max
Unit
-
rnA
Q
Filter Gain (10kHz) (Vin = 5 mY)
-
40
46
-
dB
Filter Output Voltage
11
1.8
2.0
2.5
Vdc
Trigger Hysteresis
-
-
100
-
mV
Mute Function Low
14
-
15
50
Q
Mute Function High
14
1.0
10
-
MQ
Scan Function Low (Mute Off)
(V12 = 2 Vdc)
13
-
0
0.5
Vdc
Scan Function High (Mute On)
(V12 = Gnd)
13
5.0
-
-
Vdc
Mixer Conversion Gain
3
-
20
dB
16
-
-
Mixer Input Resistance
3.3
-
kQ
Mixer Input Capacitance
16
-
2.2
-
pF
MOTOROLA ANALOG IC DEVICE DATA
8-73
11
MC3357
Figure 2. Test Circuit
VCC= 6.0Vdc
14
1-------0
muRata
CFU
455D
lOOnF
2.0k
100nF
1-......- - - - - 0 OpAmpOulpul
47k
390k
1.0~F
f---+--'1,,,.O,,,k---1+
E----<> Filler In
r---'lArv-.....- o
AudioOut
~O.Ol~
Lp=1.OmH
Cp=100pF
Rp=100k.Q
CIRCUIT DESCRIPTION
The MC3357 is a low power FM IF circuit designed
primarily for use in voice communication scanning receivers.
The mixer-oscillator combination converts the input
frequency (e.g., 10.7 MHz) down to 455 kHz, where, after
external bandpass filtering, most of the amplification is done.
The audio is recovered using a conventional quadrature FM
detector. The absence of an input Signal is indicated by the
presence of noise above the desired audio frequencies. This
"noise band" is monitored by an active filter and a detector. A
squelch trigger circuit indicates the presence of a noise (or a
tone) by an output which can be used to control scanning. At
the same time, an internal switch is operated which can be
used to mute the audio.
The oscillator is an internally-biased Colpitts type with the
collector, base, and emitter connections at Pins 4, 1, and 2
respectively. A crystal can be used in place of the usual coil.
The mixer is doubly-balanced to reduce spurious
responses. The input impedance at Pin 16 is set by a 3.0 kQ
internal biasing resistor and has low capacitance, allowing
the circuit to be preceded by a crystal filter. The collector
output at Pin 3 must be dc connected to B +, below which it
can swing 0.5 V.
After suitable bandpass filtering (ceramic or LC), the signal
goes to the input of a five-stage limiter at Pin 5. The output of
the limiter at Pin 7 drives a multiplier, both internally directly,
8-74
and extemally through a quadrature coil, to detect the FM. The
output at Pin 7 is also used to supply dc feedback to Pin 5. The
other side of the first limiter stage is decoupled at Pin 6.
The recovered audio is partially filtered, then buffered,
giving an impedance of around 400 n at Pin 9. The signal still
requires de-emphasis, volume control and further
amplification before driving a loudspeaker.
A simple inverting op amp is provided with an output at Pin
11 providing dc bias (externally) to the input at Pin 10 which is
referred internally to 2.0 V. A filter can be made with external
impedance elements to discriminate between frequencies.
With an external AM detector, the filtered audio signal can be
checked for the presence of noise above the normal audio
band, or a tone signal. This information is applied to Pin 12.
An external positive bias to Pin 12 sets up the squelch
trigger circuit such that Pin 13 is low at an impedance level of
around 60 kn, and the audio mute (Pin 14) is open circuit. If
Pin 12 is pulled down to 0.7 V by the noise or tone detector,
Pin 13 will rise to approximately 0.5 Vdc below supply where
it can support a load current of around 500 I-!A and Pin 14 is
internally short-circuited to ground. There is 100 mV of
hysteresis at Pin 12 to prevent jitter. Audio muting is
accomplished by connecting Pin 14 to a high-impedance
ground-reference point in the audio path between Pin 9 and
the audio amplifier.
MOTOROLA ANALOG IC DEVICE DATA
Figure 3. Circuit Schematic
3:
~
3
o
>:
»
z
10k
10k
30k
8
<
(';
m
~
c
!:j
l>
..~~ r-lJ:-)-
r'
hi..
(';
~~
SDk
K5
50k
~
10
~
~
~6
1~
1~
f.:
17 '
K
30k
30k
5.0k
30k
220k
10k
15 k
20k
15k
lOOk
13
K20
'i
3.0k
r'8
16
L
f-
22
2CJ
15k
»
c
m
20k
4
;;
~
:Jl
15k
F
---{24
K19
14
12
K8
22k
0-
~
1L,
50k
C,
470
s::
50 k
15
4~
28 ,.
10 k
OOk
10k
10k
10 k
10k
10k
10k
10k
10k
29 ,.
30 ,
33~
5
31
6.2k
35
36
33k
37~40
33k
33k
.....
t
II
~
50 k
J.
."
'"
,,]T'-.." ~~I
J.
5= ~~
9
10k
33k
UI
~3
!
10k
10
k
120k
~
fl
r
"'l
5~
lOOk
Cl!
"'l
~
w
UI
?8
~~
o
w
."
®
ItIIOTOROLA
MC3359
Low Power Narrowband FM IF
· .. includes oscillator, mixer, limitin'g amplifier, AFC, quadrature
discriminator, op/amp, squelch, scan control, and mute switch. The MC3359
is designed to detect narrowband FM signals using a 455 kHz ceramic filter
for use in FM dual conversion communications equipment. The MC3359 is
similar to the MC3357 except that the MC3359 has an additional limiting IF
stage, an, AFC output, and an opposite polarity Broadcast Detector. The
MC3359 also requires fewer external parts. For low cost applications
requiring VCC below 6.0 V, the MC3361 BP,BD are recommended. For
. applications requiring a fixed, tuned, ceramic quadrature resonator, use the
MC3357. For applications requiring dual conversion and RSSI, refer to these
devices; MC3335, MC3362 and MC3363.
• Low Drain Current: 3.6 mA (Typical) @ Vee
=6.0 Vdc
• Excellent Sensitivity: Input Limiting Voltage - 3.0 dB 2.0 /-LV (Typical)
=
• Low Number of External Parts Required
ORDERING INFORMATION
Device
MC3359DW
MC3359P
SEMICONDUCTOR
TECHNICAL DATA
-
PSUFFIX
PLASTIC PACKAGE
CASE 707
Figure 2. Pin Connections and
Functional Block Diagram
Package
S0-20L
TA =-30 to +70°C
FMIF
DWSUFFIX
PLASTIC PACKAGE
CASE751D
(S0-20L)
• For Low Voltage and RSSI, use the MC3371
Operating
Temperature Range
HIGH GAIN
LOW POWER
C~I{
1
RF
I",.
Plastic DIP
Scan
Coni'"
limiter
Input
DecoupImg
Figure 1. Simplified Application in a Scanner Receiver
14
6
-
~:
0 ",,",
Quadral\Jl9
Input
Demodulator
Filter
Vcc=6.0Vdc
10 7 MHz
I"",
CASE 707
Vcc",SOVdc
5Ik
16
Mule
15
9canControi
MC3359
14
•
NCI
17
elchl
20NC
19
RF
Inpol
18
Gnd
17
Audio
MUle
16
Scan
CenlTol
1lI
15
14
........'"
Frequency
13
Co",",1
10
RecoveredAudKl
12
11
Squelch
Input
Filter
Output
Filter
Input
Demod
Output
I- ~~:ered
CASE751D
8-76
MOTOROLA ANALOG IC DEVICE DATA
MC3359
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted)
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
4
VCc(max)
12
Vdc
Operating Supply Voltage Range
4
VCC
6t09
Vdc
Input Voltage (VCC;;' 6.0 Volts)
18
V18
1.0
Vrms
Mute Function
16
V16
-0.7to 12
Vpk
Junction Temperature
-
TJ
150
°C
Operating Ambient Temperature Range
-
TA
-30to + 70
°C
Tsto
-65to+150
°C
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (VCC = 6.0 Vdc, 10 = 10.7 MHz, AI = ± 3.0 kHz, Imod = 1.0 kHz, 50 n source, TA = 25°C test circuit
01 Figure 3, unless otherwise noted)
Characteristics
Min
Typ
Max
Units
-
-
3.6
5.4
6.0
7.0
mA
Input lor 20 dB Quieting
-
8.0
-
I!Vrms
Input lor - 3.0 dB Limiting
-
2.0
-
I!Vrms
Mixer Voltage Gain (Pin 18 to Pin 3, Open)
-
46
-
Mixer Third Order Intercept, 50 n Input
-
-1.0
-
dBm
Mixer Input Resistance
-
3.6
-
kQ
Squelch Off
Squelch On
Drain Current (Pins 4 and 8)
Mixer Input Capacitance
Recovered Audio, Pin 10
(Input Signal 1.0 mVrms)
-
2.2
-
pF
450
700
-
mVrms
Detector Center Frequency Slope, Pin 10
-
0.3
-
V/kHz
AFC Center Slope, Pin 11, Unloaded
-
12
-
V/kHz
Filter Gain (test circuit 01 Figure 3)
40
51
-
dB
Squelch Threshold, Through 10K to Pin 14
-
0.62
-
Vdc
-
0.01
2.4
1.0
-
mA
5.0
1.5
10
n
Mn
Scan Control Current, Pin 15
Pin 14 - High
-Low
Mute Switch Impedance
Pin 16 to Ground
Pin 14 - High
-Low
2.0
-
-
I!A
Figure 3. Test Circuit
Input
10.7 MHz
17
ceramic
Filter
muRata
CFU455D
or
Kyocera
KBF455P-'2OA
2.4k
16
Audio Gen.
0.7 VPi'
15
Squelch Input
14
10k
op AJ1lp Output
13
1.0M
12
L.....~O:.-....-./
r-
-Yvv -- -......
OpAmplnput
1.0~F
AFCOulput
11
Audio Output
10
7.5k
MOTOROLA ANALOG IC DEVICE DATA
8-77
II
MC3359
Figure 4. Mixer Voltage Gain
Figure 5. Limiting IF Frequency Response
400
Input fa = 10.7 MHz Output fO = 455 kHz
Output taken at
Pin 3 wnh filter
removed (open)
VCC=9~1I1
/
V
I I IIII
-10
)1tt11J
mE
~~ -20
VCC 6.OV= F=
_
=>c:;
~ ~ -30 -
5
O~
/
20
;d '5
I
I IIIIIII
I
IIF Inpullor -3 dB Llmilin.2,
a:~
-50
-60
0.1
10
1.0
§ -40
/10'.
/
/
V
"....2:-c
=>
Q.
/
....
=>
0
5.0
0
o
V
--
o
o
III
~ ~
~-10
'5
Derived using optimum UC
-20 r- oscillator values and holding
IF frequency at 455 kHz
~ -30
~
8.0
10
~
=>
-20
o
~-30
-50
S + Nil (!;k'AM)
N
-50
100
-60
0.001
II
- - 25°C
---75°C VCC=6.0Vdc
~ ~
lli -40
-40
111111
S+N ,~~KHzFM
!i
1.0
10
FREQUENCY [MHz]
6.0
Figure 9. Overall Gain, NOise, and AM Rejection
10
8-78
.-/
V Detector Output Pin 10
-10 -8.0 -6.0 -4.0 -2.0 0
2.0 4.0
RELATIVE FREQUENCY [kHz]
10
10
-60
0.1
/'"
3.0
1.0
~ -10
lI!
. /V
4.0
Figure 8. Relative Mixer Gain
~
r
2.0
3rd Order 1M Products/
-70 -60 -50 -40 -30 -20 -10
INPUT, 50 n [dBm]
AFC Output Pin 11
6.0
II
-,,/
/V
-50
100
Vcc = 6.0 Vdc
7.0
//
./
Desired Produc!y V
V
/
5-30
-60
-90 -80
I
10
Figure 7. Detector and AFC Responses
A
10
r-
I
8.0
/
Output taken at
E
0 r-- r- Pin 3 wh filter
ID
removed
:!;!. -10
r-VCC =6.0 Vdc
-ti
1.0
FREQUENCY [MHz]
20
"'! -20
/
/
1~l1vW-IIIIL
-70
0.1
40
Figure 6. Mixer Third Order
Intermodulation Performance
I
V
§>w~ -40 -
INPUT, 50 n (mVrms)
~
1\
Terminals not
available on
standard device.
6.0
4.0
0.04
..........
~...J
/ )'
10
IFOutput
I I IIIIIII
Response Taken on
a special prototype.
0.01
II
0.1
1.0
INPUT [mVrms]
10
100
MOTOROLA ANALOG IC DEVICE DATA
MC3359
Figure 10. Output Components of Signal,
Noise, and Distortion
10
3<.
S+N+D
111111111111
-20
;::
5w
7.0
10 ~ '1'~.7 MHz
Im:l kHz
AI: ±3.0 kHz
Test circuit of
Figure 3.
~
-10
l-
=>
a.
l=>
0
w
~
-30
N+D
-40
II
l"-
a:
0.01
0.1
1.0
10
:::::r-
6.0
;::- 5.0
z
w
~ 4.0
=>
~ 3.0
:..J
a.
g, 2.0
en
1.0
II
-60
0.001
-
r- ICC, Mute On
~
ICC, Mute Off
0.7
- :::1!3
I--
0.4
0.3
5
g
o
0.2 ~
0.1
o
100
-
I
I
Audio Output
1
N
-50
0.8
8.0
111111111
0
ill
Figure 11. Audio Output and Total Current
Drain versus Supply Voltage
4.0
5.0
6.0
7.0
o
8.0
9.0
INPUT [mVrms]
VCC, SUPPLY VOLTAGE (Vdc)
Figure 12. UC Oscillator, Temperature and
Power Supply Sensitivity
Figure 13. Op Amp Gain and Phase Response
VCC, SUPPLY VOLTAGE [Vdc]
10.706
58
"'" ""
-
10.704
10.702
N
:r 10.700
~
>0
zw 10.698
=>
0
w 10.696
60
59
61
70
".
~
~
"'.......... ~
..............
Phase
![40
z
~ 30
r-......" r--...VCC
Ti~ :::--..... ~
10.694
10.692
30
40
50
60
~
o
1.0K
10K
z
i:!:
t5
C':
«
0
100
70
50
_
C5
2
1!I~c~4~t~~~I~~II!;~1.0 g~
~I-+-H--++---+-+--iI--+I"'-..~d-+-+-H-l0.3
~
0.5
'---L_--'_.....L...--'---I.-L-'-"LJO.1
20
30
70
100
50
OSCILLATOR FREQUENCY [MHz]
'--1......1~...I....L_ _
7.0
10
MOTOROLA ANALOG IC DEVICE DATA
II
I I
0.8
10M
-
Von
i:!: 5
~ 0.4
-
=>
R2
R3
3901<
SOV
-
13
Villi!
12
v.
=-.B!....
'At',I
R2=4Q2~lR~R3
\
\
0.2
i-'
1.0
18K
nloe1
Rl
o
o
Cl
"" ",1:""'"" ' '
Vrms
R3~-Q-
_
··'1.~
Cl
I I I II
GIVEN ro = CENTER FREQUENCY
A(fa) '" GAIN AT CENTER FREQUENCY
.=!, ~ 0.6
w ~
0.7
5.0
o
1.0M
lOOK
FREQUENCY [Hz]
1.0
2.0:;:_
30
r-....
20 I-H-+++--+--+--j--t---t~".rl-+--t--I0.2
10
30
Figure 15. The Op Amp as a Bandpass Filter
V~2
~H
~~
-~
1
~~
'"
VpCtI6i~X~C
10
~~VC110
I--f----=F""I-"'-L~
w
0
150
USE CIRCUIT ABOVE
FOR OPEN LOOP GAIN
AND PHASE (SOUD LINEB)
DonED
WITH CIRCUIT VALUES
OF FIGURE 3.
Figure 14. UC Oscillator Recommended
Component Values
___--+--f--_+_
300 I-HI--+--+-p.,L........
-I"~ 200
"I'.
180
13
v.
~ain
~ ::::~
AMBIENT TEMPERATURE [OC]
1000
700
500
12
cURVEs'J1N
20
70
"""-'0
1111
..........
10.690
20
:s
-
50
"M
"'~
60
a:
I.L
62
2.0
"
5.0
10
20
FREQUENCY [kHz]
50
100
8-79
II
~
Figure 16. Representative Schematic Diagram
r----------------------------------r---------r----------I
1
3
12
13
1
14
I
1
4
I
I
Y077
01
I
I
I
·1
15
v"
18
'-I
36k
O~•
¥
K063
012
33k
35k
33k
33k.(:33k
16
Y067
.
068
~013
I
If062~7k
15k
I
I
I
1
I
r'Q69
il061
"'Q14
33k
1
070
I ~11
I
01-d
09
I
I
I
50k
I
1
I
I _______________ ~~~-~~_____________ J.----~~p---l-~~~~~O~ -1---1
I
I
I
3:
1
I
:u
o
1
a
>
?Z
)00
5
o
c;)
c
~
m
c
~
)Ii
l
limning IF Amplifler
I
II
10k
10k
10k
10k
10k
10k
10k
10k
10k
I
Detector and AFC
10k
I
I
1
I 7~~~~~~===F~~====i===~~~
II
10 k
33 k
33k
33k
33k
33k
10k
~o
17
I
I
1
ask
5k
IL _________________________________
6
1______________
~
~
______
~
s::
oCo)
Co)
UI
CD
MC3359
CIRCUIT DESCRIPTION
The MC3359 is a low-power FM IF circuit designed
primarily for use in voice-communication scanning receivers.
It is also finding a place in narrowband data links.
In the typical application (Figure 1), the mixer-oscillator
combination converts the input frequency (10.7 MHz) down
to 455 kHz, where, after external bandpass filtering, most of
the amplification is done. The audio is recovered using a
conventional quadrature FM detector. The absence of an
input signal is indicated by the presence of noise above the
desired audio frequencies. This "noise band" is monitored by
an active filter and a detector. A squelch-trigger circuit
indicates the presence of noise (or a tone) by an output which
can be used to control scanning. At the same time, an
internal switch is operated which can be used to mute the
audio.
APPLICATIONS INFORMATION
The oscillator is an internally biased Colpitts type with the
collector, base, and emitter connections at Pin 4, 1 and 2,
respectively. The crystal is used in fundamental mode,
calibrated for parallel resonance at 32 pF load capacitance.
In theory this means that the two capacitors in series should
be 32 pF, but in fact much larger values do not significantly
affect the oscillator frequency, and provide higher oscillator
output.
The oscillator can also be used in the conventional UC
Colpitts configuration without loss of mixer conversion gain.
This oscillator is, of course, much more sensitive to voltage
and temperature as shown in Figure 12. Guidelines for
choosing Land C values are given in Figure 14.
The mixer is doubly balanced to reduce spurious
responses. The mixer measurements of Figure 4 and 6 were
made using an external 50 0 source and the internal 1.8 k at
Pin 3. Voltage gain curves at several VCC voltages are shown
in Figure 4. The Third Order Intercept curves of Figure 6 are
shown using the conventional dBm scales. Measured power
gain (with the 50 0 input) is approximately 18 dB but the
useful gain is much higher because the mixer input
impedance is over 3 kO. Most applications will use a 330 0
10.7 MHz crystal filter ahead of the mixer. For higher
frequencies, the relative mixer gain is given in Figure 8.
Following the mixer, a ceramic bandpass filter is
recommended. The 455 kHz types come in bandwidths from
± 2 kHz to ± 15 kHz and have input and output impedances of
1.5 k to 2.0 k. For this reason, the Pin 5 input to the 6 stage
limiting IF has an internal 1.8 k resistor. The IF has a 3 dB
MOTOROLA ANALOG IC DEVICE DATA
limiting sensitivity of approximately 100 IlV at Pin 5 and a
useful frequency range of about 5 MHz as shown in Figure 5.
The frequency limitation is due to the high resistance values
in the IF, which were necessary to meet the low power
requirement. The output of the limiter is internally connected
to the quadrature detector, including the 10 pF quadrature
capacitor. Only a parallel UC is needed externally from Pin 8
to VCC. A shunt resistance can be added to widen the peak
separation of the quadrature detector.
The detector output is amplified and buffered to the audio
output, Pin 10, which has an output impedance of
approximately 300 o. Pin 9 provides a high impedance (50 k)
point in the output amplifier for application of a filter or
de-emphasis capacitor. Pin 11 is the AFC output, with high
gain and high output impedance (1 M). If not needed, it
should be grounded, or it can be connected to Pin 9 to double
the recovered audio. The detector and AFC responses are
shown in Figure 7.
Overall performance of the MC3359 from mixer input to
audio output is shown in Figure 9 and 10. The MC3359 can
also be operated in "single conversion" equipment; i.e., the
mixer can be used as a 455 kHz amplifier. The oscillator is
disabled by connecting Pin 1 to Pin 2. In this mode, the
overall performance is identical to the 10.7 MHz results of
Figure 9.
A simple inverting op amp is provided with an output at
Pin 13 providing dc bias (externally) to the input at Pin 12,
which is referred internally to 2.0 V. A filter can be made with
external impedance elements to discriminate between
frequencies. With an external AM detector, the filtered audio
signal can be checked for the presence of either noise above
the normal audio, or a tone signal.
The open loop response of this op amp is given in
Figure13. Bandpass filter design information is provided in
Figure 15.
A low bias to Pin 14 sets up the squelch-trigger circuit so
that Pin 15 is high, a source of at least 2.0 mA, and the audio
mute (Pin 16) is open--circuit. If Pin 14 is raised to 0.7 V by
the noise or tone detector, Pin 15 becomes open circuit and
Pin 16 is internally short circuited to ground. There is no
hysteresis. Audio muting is accomplished by connecting Pin
16 to a high-impedance ground-reference point in the audio
path between Pin 10 and the audio amplifier. No dc voltage is
needed, in fact it is not desirable because audio "thump"
would result during the muting function. Signal swing greater
than 0.7 V below ground on Pin 16 should be avoided.
8-81
II
:
®
MOTOROLA
MC3362
Low-Power Narrowband
FM Receiver
... includes dual FM conversion with oscillators, mixers, quadrature
discriminator, and meter drive/carrier detect circuitry. The MC3362 also has
buffered first and second local oscillator outputs and a comparator circuit for
FSK detection.
• Complete Dual Conversion Circuitry
LOW-POWER
DUAL CONVERSION
FM RECEIVER
• Low Voltage: VCC = 2.0 to 6.0 Vdc
• Low Drain Current (3.6 mA (Typical)
@
VCC
SEMICONDUCTOR
TECHNICAL DATA
=3.0 Vdc)
• Excellent Sensitivity: Input Voltage 0.6llVrms (Typical)
for 12 dB SINAD
• Externally Adjustable Carrier Detect Function
• Low Number of External Parts Required
PSUFFIX
PLASTIC PACKAGE
CASE 724
• Manufactured Using Motorola's MOSAIC® Process Technology
• MC13135 is Preferred for New Designs
OW SUFFIX
PLASTIC PACKAGE
CASE 751E
(SO·24L)
. ,
.
Figure 2. Pin Connections and
Representative Block Diagram
Figure 1. Simplified Application in a PLL Frequency
Synthesized Receiver
RFlnpul
to 200 MHz .
1st Mixer Input 1
2nd LO Output 2
2nd LO Emitter 3
2nd LO Base 4
From PLL Phase
Detector
3
0.411lH
4
21
Ceramic Filter
455 kHz
2nd Mixer Output 5
Limiter Input 7
Umiter
Decoupling
17 2nd Mixer Input
Lim"er
Decoupling
15 Comparator Output
17
Carrier Detect 11
14 Comparator Input
9
16
Quadrature Coil 12
13 Detector Output
10
15
11
14
12
13
0.1
0.1
10k
ORDERING INFORMATION
Device
MC3362DW
MC3362P
8-82
Operating
Temperature Range
Package
SQ.--24L
TA = - 40 10 +85°C f-P-l-as-Ii-c-D-Ip--!
MOTOROLA ANALOG IC DEVICE DATA
MC3362
MAXIMUM RATING (TA = 25°C, unless otherwise noted)
Pin
Symbol
Value
Power Supply Voltage (See Figure 2)
Rating
6
VCC(max)
7.0
Vdc
Operating Supply Voltage Range (Recommended)
6
VCC
2.0to 6.0
Vdc
1,24
VI-24
1.0
Vrms
-
TJ
150
°c
TA
-40to +85
°c
TstQ
-65to+150
°c
Input Voltage (VCC '" 5.0 Vdc)
Junction Temperature
Operating Ambient Temperature Range
Storage Temperature Range
Unit
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, fo = 49.7 MHz, Deviation = 3.0 kHz, TA = 25°C, Test Circuit of Figure 3,
unless otherwise noted)
Characteristic
Pin
Min
Typ
Max
6
4.5
7.0
mA
Input for -3.0 dB Limiting
-
0.7
2.0
I1Vrms
Input for 12 dB SINAD (See Figure 9)
-
0.6
-
I1Vrms
Series Equivalent Input Impedence
-
450-j350
13
-
350
-
mVrms
Noise Output (RF signal level = 0 mV)
13
Carrier Detect Threshold (below VCe)
10
0.64
Meter Drive Slope
10
-
Drain Current (Carrier Detect Low - See Figure 5)
Recovered Audio (RF signal level = 10 mV)
First Mixer 3rd Order Intercept (Input)
First Mixer Input Capacitance (Cp)
Conversion Voltage Gain, First Mixer
Conversion Voltage Gain, Second Mixer
Dector Output Resistance
13
mVrms
nNdB
-22
-
690
-
n
pF
100
0.7
-
First Mixer Input Resistance (Rp)
n
-
250
-
Input for 20 dB (S + N)/N (See Figure 7)
Units
18
-
21
-
1.4
-
7.2
Vdc
I1Vrms
dBm
dB
kQ
Figure 3. Test Circuit
10.5 Turns
Coilcraft
UNI-l01142
FL1:
muRata CFU455D
or
Toko LFC-4551
0.1
171---+---'
16r----+-----.
10
15
11
14
12
13
0.1
Toko RMC-2A6597HM
FL2:
muRata SFE10.7MA
or
Toko SKI 07M3-AO-l 0
1.0 I1F
Vce 0-_...-----------------_--'1+ r-------Q VEE
NOTE: See AN980 for Additional Design Information.
MOTOROLA ANALOG IC DEVICE DATA
8-83
11
MC3362
Figure 5. Drain Current, Recovered Audio
versus Supply
Figure 4. IMeter versus Input
12
11 -
Vec
~C3362
10
9.0
<::I.
8.0 5.0
4.0
/"
700
ICC. Carr. Det. Low (RF in = 10 mY)
-
5.0
<-
ICC. Carr. Det.IHiQh (RJ in
.§. 4.0
(.')
/'
-
800
7.0
6.0
/"
/'
7.0
~ 6.0
/'
8.0
!:? 3.0
./V
fII
Il
/1
2.0
1.0
3.0
o
2.0
-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30
RF INPUT (dBm)
o
1.0
20
20
10
--
10
Second Mixer Output
~ -30
/"
0-40
0-
First Mixer Input
-50
/
1 1/ ........... 0
A
A V
-60
o
-10
r---
~
M
+-SO
en
I
-70
V
L
-80
-100 -90 -80
8-84
1
o
7.0
8.0
:g
S+N30%AM
"'-.,
N
10k
+;+ 0.01
-SO -40 -30
~
\
2.0
1\' -
CO)
:>
,I
-20 -10
-
~
I-.
3.0
1/3rd Order Interrnod. prjucts I
1-
-70 -60 -50 -40 -30
RF INPUT (dBm)
6.0
Figure 9. Detector Output versus Frequency
/
/'
-60
5.0
4.0
/'i
-50
4.0
-80
-130 -120 -110 -100 -90 -80 -70 -60
RF INPUT (dBm)
//'
1/ -;
./ V
Desired ProductV'
3.0
0.01
~/
./
2.0
MC3362113 10 k
-70
~ ~ RF Input to Transformer
10
!g -30
-40
100
-60
Figure 8. 1st Mixer 3rd Order Intermodulation
-20
:>
200
~
z-4O
Z
~V
~ f/
V
~V
20
~
~ -30
~
~V
~V
o
CO)
300
S+N
a:
-70
-130 -120-110 -100 -90 -80 -70 -60 -SO -40 -30
RF INPUT (dBm)
-10
.....---: ~ ~ PO""
Recovered Audio
~
~ -20
~~
First Mixer Output 'J" V
Second Mixer Input~
E
~ 400 §.
Figure 7. S + N, N, AMR versus Input
Figure 6. Signal Levels
~
-20
~
--
600
~ 500..,
VCC(V)
30
-10
~~
0
1.0
o
-40
-30
-
~~
-20
-10
0
10
20
RELATIVE INPUT FREQUENCY (kHz)
30
40
MOTOROLA ANALOG IC DEVICE DATA
MC3362
Figure 10. PC Board Test Circuit
(LC Oscillator Configuration Used in PLL Synthesized Receiver)
RFlnput
49.67 MHz
50Q
1Bp
1000p
~T-
t
Y
':'
Varactor Control
0.47 11
VCC =2.0 to 7.0 Vdc
f--......- { (keep 0.7 V .. V23 .. VCC)
':'
(This network must be tuned to exactly
10.7 MHz above or below the incoming
RFsignal.
NOTE: The IF is rolled off above 10.7
MHz to reduce L.O. feecllhrough.)
455kHz
Cer. Fitt.
=
10VCC
=
0.1
CRF2 muRata SFA10.7 MF5 or
SFE10.7 or equivalent. Rin Rout
= 330 Q. Crystal filters can be
used but impedance matching will
need to be added to ensure proper
filter characteristics are realized.
0.1
Carrier
Detee!
CRF1 muRata CFU 455X - the X
suffix denotes 6.0 dB bandwidth.
Rin = Rout = 1.5 to 2.0 kQ.
=
II
_t------....I
Recovered
Audio
455kHz
LC Resonator
Figure 10A. Crystal Oscillator Configuration for Single Channel Application
~
20k
u
::i
300
I
VCC
Crystal used is series mode resonant
(no load capacity specified), 3rd overtone.
This method has not proven adequate for
fundamental mode, 5th or 7th overtone crystals.
The inductor and capacitor will need to be
changed for other frequency crystals. See
AN980 for further information.
20 k
I
3B.97 MHz
MOTOROLA ANALOG IC DEVICE DATA
8-85
MC3362··'
Figure 11. Component Placement View'
Showing Crystal Oscillator Circuit
NOTES: 1. Reco.vered Audio. compo~ents r(1ay be deleted when using
data output.
2. Carrier Detect components must be deleted in order to obtain
linear Meter Drive output. With these components in place the
Meter Drive outputs serve only to t~ip the Carrier Detect indicator.
3. Data Output components should be deleted in applications
where only audio modulation is used. For combined audio/data
applications, the 0.047 !tF coupling capacitor will add distortion
to the audio, so a pull-down resistor at pin 13 may be required.
. Figure 11 A. LC Oscillator Component View
5. Meter Drive cannot be used simultaneously wijh Carrier Detect output.
For analog meter drive, remove components labelled "2" and measure
meter current (4-12 !tA) through ammeter to VCC.
6. Either type of oscillator circuit may be used with any output circuit
configuration.
7.LC Oscillator Coil: Coilcral! UNll014210.5turns, 0.41 !tH Crystal
Oscillator circuit: trim coil, 0.68 !tH. Coilcral! MI287-A.
8.0.47 H, Coilcral! MI286-A. Input LC network used to match first mixer
input impedance to 50 U.
4. Use Toko 7MC81282 Quadrature coil.
CIRCUIT DESCRIPTION
The MC3362 is a complete FM narrowband receiver from
antenna input to audio preamp output. The low voltage dual
conversion design yields low power drain, excellent
sensitivity and good image rejection in narrowband voice and
data link applications.
In the typical application (Figure 1), the first mixer
amplifies the signal and converts the RF input to 10.7 MHz.
This IF signal is filtered externally and fed into the second
mixer, which further amplifies the signal and converts it to a
455 kHz IF signal. After external bandpass filtering, the low IF
is fed into the limiting amplifier and detection circuitry. The
audio is recovered using a conventional quadrature detector.
Twice-IF filtering is provided internally:
The input signal level is monitored by meter drive circuitry
which detects the amount of limiting in the limiting amplifier.
The voltage at the meter drive pin determines the state of the
carrier detect output, which is active low.
APPLICATIONS INFORMATION
The first local oscillator can be run using a free-running
LC tank, as a VCO using PLL synthesis, or driven from an
external crystal oscillator. It has been run to 190 MHz: A
buffered output is available at Pin 20. The second local
'. oscillator is a common base Colpitts type which is typically
run at 10.245 MHz under crystal control. A buffered output is
available at Pin 2. Pins 2 and 3 are interchangeable.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 22 dB (typical), respectively, as seen in
Figure 6. Mixer gain is stable with respect to supply voltage.
For both conversions, the mixer impedal'\ces and pin layout
are designed to allow the user to employ low cost, readily
available ceramic filters. Overall sensitivity and AM rejection
are shown in Figure 7: The input level for 20 dB (8 + N)/N is
0.71LV using the two-pole post-detection filter pictured.
'If the first local oscillator (Pins 21 and/or 22) is driven from a
strong external source (100 mVrms). the mixer can be used to
over 450 MHz.
8-86
MOTOROLA ANALOG IC DEVICE DATA
MC3362
Following the first mixer, a 10.7 MHz ceramic band-pass
filter is recommended. The 10.7 MHz filtered signal is then
fed into one second mixer input pin, the other input pin being
connected to Vee. Pin 6 (Vee) is treated as a common point
for emitter-driven signals.
The 455 kHz IF is typically filtered using a ceramic
bandpass filter then fed into the limiter input pin. The limiter
has 10 !LV sensitivity for - 3.0 dB limiting, flat to 1.0 MHz.
The output of the limiter is internally connected to the
quadrature detector, including a quadrature capacitor. A
parallel Le tank is needed externally from Pin 12 to Vee. A 39
kQ shunt resistance is included which determines the peak
separation of the quadrature detector; a smaller value will
increase the spacing and linearity but decrease recovered
audio and sensitivity.
A data shaping circuit is available and can be coupled to
the recovered audio output of Pin 13. The circuit is a
comparator which is designed to detect zero crossings of
FSK modulation. Data rates are typically limited to 1200 baud
to ensure data integrity and avoid adjacent channel "splatter."
Hysteresis is available by connecting a high valued resistor
from Pin 15 to Pin 14. Values below 120 kn are not
recommended as the input signal cannot overcome the
hysteresis.
The meter drive circuitry detects input signal level by
monitoring the limiting amplifier stages. Figure 4 shows the
unloaded current at Pin 10 versus input power. The meter
drive current can be used directly (RSSI) or can be used to
trip the carrier detect circuit at a specified input power. To do
this, pick an RF trip level in dBm. Read the corresponding
current from Figure 4 and pick a resistor such that:
R10 "'" 0.64 Vdc / 110
Hysteresis is available by connecting a high valued resistor
RH between Pins 10 and 11. The formula is:
Hysteresis
=Vecl(RH x 10 - 7) dB
Figure 12. Circuit Side View
II
jool~----------- 4" ----------...,~~I
MOTOROLA ANALOG IC DEVICE DATA
8-87
II
~
Figure 13. Representative Schematic Diagram
23
8 1
e
lOon
210--+
~.
bias
8
e
ee
$
9 9$
e$~
8
9
10~~--------------------------------+---~~
12
11
s::
o
i
N
a
==
:II
o
~
~
§
(;
c
m
<
(;
m
c
!:i)Ii
13
14
bias
I
16
VEE
®
MOTOROLA
MC3363
Low Power Dual
Conversion FM Receiver
The MC3363 is a single chip narrowband VHF FM radio receiver. It is a dual
conversion receiver with RF amplifier transistor, oscillators, mixers,
quadrature detector, meter drive/carrier detect and mute circuitry. The
MC3363 also has a buffered first local oscillator output for use with frequency
synthesizers, and a data slicing comparator for FSK detection.
LOW POWER
DUAL CONVERSION
FM RECEIVER
• Wide Input Bandwidth - 200 MHz Using Internal Local Oscillator
- 450 MHz Using External Local Oscillator
SEMICONDUCTOR
TECHNICAL DATA
• RF Amplifier Transistor
• Muting Operational Amplifier
• Complete Dual Conversion
• Low Voltage: VCC = 2.0 V to 6.0 Vdc
• Low Drain Current: ICC = 3.6 mA (Typical) at VCC = 3.0 V,
Excluding RF Amplifier Transistor
• Excellent Sensitivity: Input 0.31lV (Typical) for 12 dB SINAD
Using Internal RF Amplifier Transistor
DWSUFFIX
PLASTIC PACKAGE
CASE 751F
(SO·2BL)
• Data Shaping Comparator
• Received Signal Strength Indicator (RSSI) with 60 dB
Dynamic Range
• Low Number of External Parts Required
ORDERING INFORMATION
• Manufactured in Motorola's MOSAIC® Process Technology
Device
Operating
Temperature Range
Package
MC3363DW
TA = - 40 10 +B5°C
S0-2BL
Figure 1. Pin Connections and Representative
Block Diagram
1st Mixer Input 11-----..., r - - - - t 2 8 1st Mixer Input
...J:;""""-,,?:1,,_, Varicap Control
Emitter
Collector
3
4 1-------'
2nd La Emiller 5
2nd LO Base
24 1st LO Output
61--~--~
2nd Mixer Output 07'1---<
23
~----t2g2j2
1st Mixer Output
2nd Mixer Input
"------121 2nd Mixer Input
Limiter Input 9 1----...,
Limiter Decoupling 10I--+--iill16 Recovered Audio
15 Mute Input
8-89
MC3363
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Pin
Symbol
Value
Power Supply Voltage
Rating
8
VCC(max)
7.0
Vdc
Operating Supply Voltage Range
(Recommended)
8
VCC
2.0 to 6.0
Vdc
1,28
Vl-28
1.0
Vrms
Vpk
Input Voltage (VCC = 5.0 Vdc)
Unit
Mute Output Voltage
19
V19
-0.7to 8.0
Junction Temperature
-
TJ
150
°c
Operating Ambient Temperature Range
-
TA
-40to +85
°c
-
Tstg
-65to +150
°c
Storage Temperature Range
'.
ELECTRICAL CHARACTERISTICS (VCC
test circun of Figure 2 unless otherwise noted)
=5.0 Vdc, fo =49.7 MHz, Deviation =±3.0 kHz, TA =25°C, Mod 1.0 kHz,
Characteristic
Pin
Min
Typ
Max
Units
-
4.5
8.0
mA
0.7
2.0
l1Vrms
Input For 12 dB SINAD
-
0.3
-
20 dB SIN Sensitivity (RF Amplifier Not Used)
-
1.0
-
-
690
-
Q
7.2
-
pF
1st Mixer Conversion Voltage Gain (Avcl, Open Circuit)
-
18
-
dB
2nd Mixer Conversion Voltage Gain )Avc2, Open Circuit)
-
21
-
-
10
-
9
100
-
RF Transistor DC Current Drain
4
1.0
1.5
2.5
mAde
=0 mY)
Recovered Audio (RF Signal Level =1.0 mY)
THO of Recovered Aduio (RF Signal =1.0 mY)
16
-
70
-
mVrms
16
120
200
-
mVrms
16
-
2%
Detector Output Impedance
16
400
Series Equivalent Input Impedance
1
-
Data (Comparator) Output Voltage - High
-Low
18
Data (Comparator) Threshold Voltage Difference
17
70
110
150
mV
Meter Drive Slope
12
70
100
135
nAldB
Carrier Detect Threshold (Below VCC)
12
0.53
0.64
0.77
Vdc
Mute Output Impedance - High
-Low
19
-
10
25
-
MQ
Drain Current (Carrier Detect Low)
8
-3.0 dB Limning Sensitivity (RF Amplifier Not Used)
1st Mixer Input Resistance (Parallel- Rp)
1,28
1st Mixer Input Capacitance (Parallel- Cp)
1,28
2nd Mixer Input Sensitivity (20 dB SIN) (10.7 MHz i/p)
Limiter Input Sensnivity (20 dB SIN) (455 kHz Vp)
Noise Output Level (RF Signal
8-90
21
450]350
-
-
0.1
0.1
-
-
l1Vrms
%
Q
VCC
-
-
Vdc
MOTOROLA ANALOG IC DEVICE DATA
iii:
a
:u
o
Figure 2. Test Circuit
VCC= 5.0 Vdc
!t:
»
z
»
g
(5
Ferronics 12-345-K Core
CRF 1: muRata SFE 10.7 rnA
or Equivalent
1000 pF
21. 6
lstMixerlnput~
1
50MHzO~------+--------
m
I
CRF 2: muRala CFU 4550
or Equivalent
o
c
I
Ll: Coilcraft UNll0/142 10-1/2 Turns
c
::5
m
LC1: Taka 7MC8128Z
~
)0
From PLL Phase Deetector
s::
120pF
To PLL Phase Detector
l
10k
10k
Mute Output
-lliI
0.1
,
0
~
Comparator Output
390k
10 k
5.0k
'VII\,
I--+---~'VII\,
5.0k
~131----'~
0
Recovered Audio
Output
14
6Sk
r:-
10k
Lcd L~. J I
~_~-..=.J-
Ll'2!~~
-VV~ ~ComparatorTestlnput
0.01
Carrier Detect Output
t...
II
Mute Input
~
~
r· I 10~F
+
MC3363
CIRCUIT DESCRIPTION
The MC3363 is a complete FM narrowband receiver from
RF amplifier to audio preamp output. The low voltage dual
conversion design yields low power drain, excellent
sensitivity and good image rejection in narrowband voice and
data link applications.
In the typical application, the input RF signal is amplified
by the RF transistor and then the first mixer amplifies the
signal and converts the RF input to 10.7 MHz. This IF signal
is filtered externally and fed into the second mixer, which
further amplifies the signal and converts it to a 455 kHz IF
signal. After external bandpass filtering, the low IF is fed into
the limiting amplifier and detection circuitry. The audio is
recovered using a conventional quadrature detector.
Twice-IF filtering is provided internally.
The input signal level is monitored by meter drive circuitry
which detects the amount of limiting in the limiting amplifier.
The voltage at the meter drive pin determines the state of the
carrier detect output, which is active low.
APPLICATIONS INFORMATION
The first local oscillator is designed to serve as the VCO in
a Pll frequency synthesized receiver. The MC3363 can
operate together with the MC145166n to provide a two-chip
ten--channel frequency synthesized receiver in the 46/49
cordless telephone band. The MC3363 can also be used with
the MC14515X series of CMOS Pll synthesizers and
MC120XX series of ECl prescalers in VHF frequency
synthesized applications to 200 MHz.
For single channel applications the first local oscillator can
be crystal controlled. The circuit of Figure 4 has been used
successfully up to 60 MHz. For higher frequencies an
external oscillator signal can be injected into Pins 25 and/or
26 - a level of approximately 100 mVrms is recommended.
The first mixer's transfer characteristic is essentially flat to
450 MHz when this approach is used (keeping a constant
10.7 MHz IF frequency). The second local oscillator is a
Colpitts type which is typically run at 10.245 MHz under
crystal control.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 21 dB (typical), respectively. Mixer gain is
stable with respect to supply voltage. For both conversions,
the mixer impedances and pin layout are designed to allow
the user to employ low cost, readily available ceramic filters.
Following the first mixer, a 10.7 MHz ceramic bandpass
filter is recommended. The 10.7 MHz filtered signal is then
fed into the second mixer input Pin 21, the other input Pin 22
being connected to VCC.
The 455 kHz IF is filtered by a ceramic narrow bandpass
filter then fed into the limiter input Pin 9. The limiter has 1011V
sensitivity for -3.0 dB limiting, flat to 1.0 MHz.
The output of the limiter is internally connected to the
quadrature detector, including a quadrature capacitor. A
parallel lC tank is needed externally from Pin 14 to VCC. A 68
kO shunt resistance is included which determines the peak
separation of the quadrature detector; a smaller value will
lower the Q and expand the deviation range and linearity, but
decrease recovered audio and sensitivity.
A data shaping circuit is available and can be coupled to
the recovered audio output of Pin 16. The circuit is a
comparator which is designed to detect zero crossings of
FSK modulation. Data rates of up to 35000 baud are
detectable using the comparator. Best sensitivity is obtained
when data rates are limited to 1200 baud maximum.
Hysteresis is available by connecting a high-valued resistor
from Pin 17 to Pin 18. Values below 120 kO are not
recommended as the input signal cannot overcome the
hysteresis.
The meter drive circuitry detects input signal level by
monitoring the limiting of the limiting amplifier stages.
Figure 5 shows the unloaded current at Pin 12 versus input
power. The meter drive current can used directly (RSSI) or
can be used to trip the carrier detect circuit at a specified
input power.
A muting op amp is provided and can be triggered by the
carrier detect output (Pin 13). This provides a carrier level
triggered squelch circuit which is activated when the RF input
at the desired input frequency falls below a present level. The
level at which this occurs is determined by the resistor placed
between the meter drive output (Pin 12) and VCC. Values
between 80-130 kO are recommended. This type of squelch
is pictured in Figures 3 and 4.
Hysteresis is available by connecting a high-valued
resistor Rh between Pins 12 and 13. The formula is:
Hyst
= VCC/ (Rh x 10- 7) dB
The meter drive can also be used directly to drive a meter
or to provide AGC. A current to voltage converter or other
linear buffer will be needed for this application.
A second possible application of the op amp would be in a
noise triggered squelch circuit, similar to that used with the
MC3357/MC3359/MC3361 B FM IFs. In this case the op amp
would serve as an active noise filter, the output of which
would be rectified and compared to a reference on a squelch
gate. The MC3363 does not have a dedicated squelch gate,
but the NPN RF input stage or data shaping comparator
might be used to provide this function if available. The op
amp is a basic type with the inverting input and the output
available. This application frees the meter drive to allow it to
be used as a linear signal strength monitor.
The circuit of Figure 4 is a complete 50 MHz receiver from
antenna input to audio preamp output. It uses few
components and has good performance. The receiver
operates on a single channel and has input sensitivity of
< 0.31lV for 12 dB SINAD.
NOTE: For further application and design information, refer to AN980.
8-92
MOTOROLA ANALOG IC DEVICE DATA
3:
g
:u
Figure 3. Typical Application in a PLL Frequency Synthesized Receiver
o
~
VCC= 5.0 Vdc
»
z
»
b
C)
n
c
~
n
m
~
~
2.0T
27pF
0.41 I1H
RFlnput
49.670 to
9.970 MHz
0.Q1
CRF 1: muRata SFE 10.7mAor Equivalent
CRF 2: muRata CFU 4550 or Equivalent
L1: Coileraft UN110/14210 112 Turns
LC1: Toko 7MCB12BZ
~rl~------------L-~
From PLL Phase Detector
To
MC14516617
Dual PLL
Frequency
Synchrsizer
CF1
10.245M
3.0k
s::
o(0)
~
(0)
10k
VCC (Regulated)
l - - - + - - - -.......-------...,~~- DataOutput
0.001
- -I
10k
200k
Mute
Control
~ Cr
t
100k
±j (
LC1
1.011 H
~
3.3kt020k
Pin 26
L=O.OB I1H
T
39k
Pull-Up
Resistor
Pin 27
L-If--------'
Pin 25
1000 200 MHz
Recovered Audio
Output
Pin 24
L=6BO I1H
C= 1BOpF
NOTE: Pull Up resistor is
used to run the oscillator above 50 MHz.
~
II
II
Figure 4. Single Channel Narrowband FM Receiver at 49.67 MHz
*
t
H~jn~~z
MC3363DW
500
0.01
39pF
1.0kpF
y~(
20 k
I
~~.OkPF
-=-
3000
o.22:H ~
20 k
.. Ii·
H
,
-=-
~
~
L.O.Out
(optional)
4.71!H
4.71!H
3.31!H
10 I!H
Squelch
Adjust
8.00 Spkr
-=-
s::
o
~
0)
(0)
0.1
Pl
lOOk
-=-
139k
-=-
50 k
!!:
m
F1 - 455 kHz ceramic filter, A in = Rout = 1.5 k!l to 2.0 kO
MuAata CFU455X or CFW455X, suffix denotes bandwidth
F2 - 10.7 MHz ceramic filter, Ain = Rout = 3300
MuAata SFE10.7MJ-A, SFA10.7MF5, orSFE10.7MS2A.
F2X - 10.7 MHz crystal filter, FOX 1OM20A or equivalent.
Crystal filters improve adjacent channel and second
image (unwanted 48.76 MHz) rejection. Sensitivity Is
degraded very slightly with this circuit.
LC1 - 455 kHz quadrature tank circuit; Toko 7MC8128Z
P1 - Volume control, miniature potentiometer, logarithmic
taper.
X11 - 10.245 MHz fundamental mode crystal,load capacity
32pF.
X2 - 38.97 MHz, 3rd overtone crystal, series mode .
0.68 IlH adjustable coil; Coilcraft M1287-A
0.22 IlH adjustable coil; Coilcraft M117~A
~
F\.ED is used to adjust LED current: I LED =
o
a
RLED
~
~
l>
Z
l>
.r-
o
Ci)
c;
+
3
~
22
21
F2
c
c;
~ Detect
Indicator
c::::=:::J
m
.<
'J'.".. Carlier
Standard 10.7 MHz Filter
VCC
-=-
fl.0l!F
-=-
c
):Ii
VCC-VLED
-c::---RLED
5:
a
Figure 5. Circuit Schematic
:0
o
>
»
27
z
»
6
8n
cm
23
7
6~
S
o
c
m
~
»
Bias
~.~.~
2T.vYV-~s
12
0
r= ["
,
3:
13
o
15
14 .
(0)
(0)
19
11
17
16
18
20
1
~
II
Q)
(0)
MC3363
Figure 6. PC Board Component View
with High Performance Crystal Filter
Figure 7. PC Board Circuit Side View
Figure 8. PC Board Component Side Ground Plane
fo..oiIlI - - - - - - - - 3.000" -------.-.11
8-96
MOTORQLA ANALOG IC DEVICE DATA
®
ItIIOTOROLA
MC3371
MC3372
Low Power
Narrowband FM IF
LOW POWER
FM IF
The MC3371 and MC3372 perform single conversion FM reception and
consist of an oscillator, mixer, limiting IF amplifier, quadrature discriminator,
active filter, squelch switch, and meter drive circuitry. These devices are
designed for use in FM dual conversion communication equipment. The
MC3371/MC3372 are similar to the MC3361/MC3357 FM IFs, except that a
signal strength indicator replaces the scan function controlling driver which is
in the MC3361/MC3357. The MC3371 is designed for the use of parallel LC
components, while the MC3372 is designed for use with either a 455 kHz
ceramic discriminator, or parallel LC components.
These devices also require fewer external parts than earlier products. The
MC3371 and MC3372 are available in dual-in-line and surface mount
packaging.
• Wide Operating Supply Voltage Range: VCC
1
PSUFFIX
PLASTIC PACKAGE
CASE 648
= 2.0 to 9.0 V
• Input Limiting Voltage Sensitivity of -3.0 dB
• Low Drain Current: ICC = 3.2 rnA, @ VCC = 4.0 V, Squelch Off
• Minimal Drain Current Increase When Squelched
DSUFFIX
PLASTIC PACKAGE
CASE 7518
(S0-16)
• Signal Strength Indicator: 60 dB Dynamic Range
• Mixer Operating Frequency Up to 100 MHz
• Fewer External Parts Required than Earlier Devices
II
MAXIMUM RATINGS
Rating
Value
Unit
4
Vcc(max)
10
Vdc
RF Input Voltage (VCC .. 4.0 Vdc)
16
V16
1.0
Vrms
Detector Input Voltage
B
VB
1.0
Vpp
Squelch Input Voltage
(VCC .. 4.0 Vdc)
12
V12
6.0
Vdc
Mute Function
14
V14
-0.7 to 10
Vpk
Mute Sink Current
14
114
50
mA
MC3371D
Junction Temperature
-
TJ
150
°c
MC3371DTB
Tstg
-65 to +150
°c
MC3371P
Storage Temperature Range
Pin
DTBSUFFIX
PLASTIC PACKAGE
CASE 948F
(TSSOP-16)
Symbol
Power Supply Voltage
ORDERING INFORMATION
Device
NOTES: 1. Devices should not be operated at these values. The "Recommended Operating
Conditions" table provides conditions for actual device operation.
2. ESO data available upon request.
Operating
Temperature Range
Package
SO-16
TSSOP-16
TA = -30° to +70°C
Plastic DIP
S0-16
MC3372D
MC3372DTB
TSSOP-16
MC3372P
Plastic DIP
PIN CONNECTIONS
Mixer Input
Crystal Osc {
Gnd
Mute
Mixer Output
VCC
Limiter Input
MC3371
(Top View)
DecouPling{
Quad Coil
MOTOROLA ANALOG IC DEVICE DATA
Meter Drive
Squelch Input
Filter Output
Filter Input
Recovered Audio
Crystal Osc {
Mute
Mixer Output
VCC
Limiter Input
Decoupling
Limiter Output
Quad Input
MC3372
(Top View)
Meter Drive
Squelch Input
Filter Output
Filter Input
Recovered Audio
8-97
MC3371 MC3372
RECOMMENDED OPERATING CONDITIONS
Rating
Pin
Symbol
Value
Unit
Supply Voltage
(@ TA =; 25°C)
(-30°C ~ TA ~'+15°C)
4
VCC
2.0 to 9.0
2.4 to 9.0
Vdc
RF Input Voltage
16
Vrf
0.0005 to 10
mVrms
RF Input Frequency
16
Irf
0.1 to 100
MHz
Oscillator Input Voltage
1
Vlceal
80 to 400
mVrms
Intermediate Frequenc:y
-
Iii
455
kHz
Limiter Amp Input VoHage
5
Vii
Ot0400
mVrms
Filter Amp Input Voltage
10
Via
0.1 to 300
mVrms
Squelch Input Voltage
12
Vsq
00r2
Vdc
14
Isq
0.1 to 30
mA
-
TA
--30 to +70
°C
>.
Mute Sink Current
Ambient Temperature Range
AC ELECTRICAL CHARACTERISTICS (VCC = 4.0 Vdc, 10 = 58.1125 MHz, df = ±3.0 kHz, Imod = 1.0 kHz, 50 n source,
Ilocal = 57.6575 MHz, Vlceal = 0 dBm, TA = 25°C, unless otherwise noted)
Characteristic
Pin
Symbol
Input lor 12 dB SINAD
Matched Input - (See Figures 11, 12 and 13)
Unmatched Input - (See Figures 1 and 2)
-
VSIN
Input lor 20 dB NOS
-
VNOS
Recovered Audio Output VoHage
Vrf =--30 dBm
-
AFO
Recovered Audio Drop Voltage Loss
Vrf = --30 dBm, VCC = 4.0 V to 2.0 V
-
Meter Drive Output Voltage (No Modulation)
Vrf=-lOOdBm
Vrf=-70dBm
Vrf=-40dBm
13
FiRer Amp Gain
Rs = 600 n , Is = 10 kHz, Via = 1.0 mVrms
-
Mixer Conversion Gain
Vrf=-40 dBm, RL = 1.8 kn
-
Signal to Noise Ratio
Vrf =-30 dBm
-
Total Harmonic Distortion
Vrf = --30 dBm, BW = 400 Hz to 30 kHz
-
Detector Output Impedance
9
Zo
Detector Output VoHage (No Modulation)
Vrf =-30 dBm
9
DVO
Meter Drive
Vrf = -100 to -40 dBm
13
Meter Drive Dynamic Range
RFln
IFln (455 kHz)
13
Mixer Third Order Input Intercept Point
11 = 58.125 MHz
12 = 58.1375 MHz
-
Mixer Input Resistance
16
Mixer Input Capacitance
16
8-98
Min
Typ
Max
-
-
1.0
5.0
15
-
3.5
-
I1Vrms
I1Vrms
mVrms
120
200
320
-8.0
-1.5
-
1.1
2.0
0.3
1.5
2.5
0.5
1.9
3.1
47
50
-
14
20
-
36
67
-
-
0.6
3.4
-
450
-
AFloss
MDrv
MVl
MV2
MV3
Unit
dB
Vdc
dB
AV(Amp)
dB
AV(Mix)
sin
THO
dB
%
n
Vdc
-
1.45
-
-
0.8
-
-
60
80
-
I1NdB
MO
MVD
dB
-
dBm
ITOMix
-
-22
Rin
-
3.3
-
kG
Cin
-
2.2
-
pF
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
DC ELECTRICAL CHARACTERISTICS (VCC = 4.0 Vdc, TA = 25'C, unless otherwise noted)
Characteristic
Pin
Drain Current (No Input Signal)
Squelch Off, Vsq = 2.0 Vdc
Squelch On, Vsq = 0 Vdc
Squelch Off, VCC = 2.0 to 9.0 V
4
Detector Output (No Input Signal)
DC Voltage, VB = VCC
9
Finer Output (No Input Signal)
DC Voltage
Voltage Change, VCC = 2.0 to 9.0 V
11
Trigger Hysteresis
-
Symbol
Min
Typ
Max
Iccl
Icc2
dlccl
-
3.2
3.6
1.0
4.2
4.B
2.0
0.9
1.6
2.3
VII
dVll
1.5
2.0
2.5
5.0
3.5
B.O
Hys
34
57
BO
Unit
mA
V9
Vdc
Vdc
mV
Figure 1. MC3371 Functional Block Diagram and Test Fixture Schematic
RSSIOutput
RFlnput
VCC=4.0Vdc
Filterln
0.1
51 k
Cl
0.01
Sqln
1
Filterout
1
51
1.o1lF
15
470
0.01
510k
Mute
16
1.o1lF
13
12
11
8.2k
10
9
51 k
53 k
1.8k
4
6
8
7
0.1
0.1
20k
muRata
CFU455D2
or
equivalent
MOTOROLA ANALOG IC DEVICE DATA
JO.l
1
AFOut
to Audio
Power Amp
II
MC3371 MC3372
Figure 2. MC3372 Functional Block Diagram and Test Fixture Schematic
RSSIOutput
RFlnput
Vcc= 4.0 Vdc
Rlterln
0.1
51 k
C1
0.01
Sqln
1
Filterout
1
51
1.OI!F
15
470
0.01
510 k
Mute
16
1.01!F
13
12
11
B.2k
10
J
AFOut
to Audio
PowerArnp
9
53k
II
R10
1.Bk
R12
4.3k
C12
0.1
o
Ceramic
Resonator
muRata
CDB455C16
muRata
CFU455D2
or
equivalent
8-100
r
C15
0.1
MOTOROLA AN!\LOG IC DEVICE DATA
MC3371 MC3372
TYPICAL CURVES
(Unmatched Input)
Figure 3. Total Harmonic Distortion
versus Temperature
~ 5.0
~
Ii:
I
VCC = 4.0 Vdc
RF Input = -30 dBm J----fo= 10.7 MHz
60
I
4.0
12
!!2
Figure 4. RSSI versus RF Input
70
«
,2,
~ 3.0
Z
~
~ 2.0
:I:
-'
~
12
\
1.0
ci
~
0
-s5
j 1\
\V
-35
-15
/"
V
'"
l-
=>
-
40
«::!.
-30dBm
en
en
30
a::
20
10 r- T A , C
105
o
125
-140 -120
t=' 36
f!:
=>
0
en
en
30
-70dBm
24
a:: 18
~_TA=-30°C
-100
-80
;[ -20
~
l-
i[ -30
-
I;
~ -40
r--
/"
-50
-80
105
-70
-70
125
T~=75jC -
27
V
-60
-50
./
~
21
t=' 18
=>
D..
5
0
en
en
T _-30°C- -
II
-40
/
-30
-20
~ "-
TA=25°C-
m
30
z
J
~
U'
RF INPUT (dBm)
I
42
TA=25 C'):
0
0
5.0
25
45
65
85
TA, AMBIENT TEMPERATURE (OC)
..
54
48
,
50
Figure 5. RSSI Output versus Temperature
60
TAI=75°C
8.0
9.0
10
o
1.0
\
\\
\\' 5.0dBm
\\ OdBm I
\\
10
100
-5.0dBm
1000
f, FREQUENCY (MHz)
8-101
II
MC3371 MC3372
MC3371 PIN FUNCTION DESCRIPTION
OPERATING CONDITIONS
Pin
The base of the Colpitts oscillator. Use
a high impedance and low capacitance
probe or a "sniffer" to view the waveform without altering the frequency.
Typical level is 450 mVpp.
Vcc
OSCI
2
OSC2
3
MXOut
-+--'l.......1".,5k~
The emitter of the Colpitts oscillator.
Typical signal level is 200 mVpp. Note
that the signal is somewhat distorted
compared to that on Pin 1.
OSC2
3
MixeroUl
II
Output of the Mixer. Riding on the
455 kHz is the RF carrier component.
The typical level is approximately
60mVpp.
4
VCC
Supply Voltage -2.0 to 9.0 Vdc is the
operating range. VCC is decoupled to
ground.
5
IFln
Input to the IF amplifier after passing
through the 455 kHz ceramic filter. The
signal is attenuated by the filter. The
typical level is approximately
50mVpp.
IFln
DECI
6
7
a
DECI
DEC2
Quad
Coil
DEC2
IF Decoupling. External 0.1 I1F
connected to VCC.
capac~ors
8
Quad Coil
VCC
Quadrature Tuning Coil. Composite
(not yet demodulated) 455 kHz IF
signal is present. The typical level is
500mVpp.
501lA
8-102
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
MC3371 PIN FUNCTION DESCRIPTION (continued)
=3.0 kHz. MC3371 at
OPERATING CONDITIONS
Internal Equivalent
Circuil
Pin
9
= 10.7 MHz (see Figure 11).
Waveform
Recovered Audio. This is a composite
FM demodulated output having signal
and carrier component. The typical
level is 1.4 Vpp.
h
VCC",
9 RAOut
100).IA
10
The filtered recovered audio has the
carrier component removed and is
typically 800 mVpp.
Filter Amplifier Input
II
11
Filter Amplifier Output. The typical
signal level is 400 mVpp.
FilOut
Vee
i;
40).IA
FilterOut
11
12
Squelch Input. See discussion in
application text.
12
Sqln~ ~
~2).IA
MOTOROLA ANALOG IC DEVICE DATA
8-103
MC3371 MC3372
MC3371 PIN FUNCTION DESCRIPTION (continued)
,
OPERATING CONDITIONS VCC = 4 0 Vdc RF'n = 100 ltV fmod = 10kHz fdev = 30kHz MC3371 at fRF = 10 7 MHz (see Figure 11)
Pin
Symbol
13
RSSI
Internal Equivalent
Circuit
Vee
Bias
14
MUTE
t
Description
Waveform
RSSI Output. Referred to as the
Received Signal Strength Indicator or
RSSI. The chip sources up to 60 ItA
over the linear 60 dB range. This pin
may be used many ways, such as:
AGC, meter drive and carrier triggered
squelch circuit.
13
RSSIOut
tf~'
Mute Output. See discussion in
application text.
40k
15
Gnd
Gnd
*
16
II
15
•
Vee
MIX'n
MixefJn
~
3.3k
Ground. The ground area should be
continuous and unbroken. In a twosided layout, the component side has
the ground plane. In a one-sided
layout, the ground plane fiJJs around
the traces on the circuit side of the
board and is not interrupted.
Mixer Input Series Input Impedance:
@ 10 MHz: 309 - j33 Q
@ 45 MHz: 200 - j13 Q
10 k
"other pins are the same as pins in MC3371.
8-104
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
MC3372 PIN FUNCTION DESCRIPTION
OPERATING CONDITIONS VCC = 4.0 Vdc, RFln = 100 ~V, fmod = 1.0 kHz, fdev = 3.0 kHz. MC3372 at 'RF = 45 MHz (see Figure 13).
Pin
Symbol
Internal Equivalent
Circuit
5
IF Amplifier Input
IFlnf.:
6
DEe
6
60 ItA
7
IFOut
7 1Foul
vee
~
53k
IF Decoupling. External 0.1 ~F
connected to Vcc.
capac~ors
IF Amplifier Output Signal level is
typically 300 mVpp.
50 ItA
.". 120 ItA
.".
8
Quadrature Detector Input. Signal
level is typically 150 mVpp.
Quadln
~
8
Quadln
II
Vee
T 10
9
501tA
RA
Recovered Audio. This is a composite
FM demodulated output having signal
and carrier components. Typical level
is800mVpp.
i=
'CC '" ,
RAOul
100 ItA
MOTOROLA ANALOG IC DEVICE DATA
The filtered recovered audio has the
carrier signal removed and is typically
500mVpp.
8-105
MC3371 MC3372
Figure 9. MC33?:1 Circuit Schematic
MixerOul
4
3
VCC
OSC1
-+-""M~
SquelchOul
OSC2
, - 15
-}
Gnd
53k
DECt~1-~~~~---~~--------t-~-+-~
. 7
51 k
DEC2~~-r-----~---~~--------------~-+~--~
Figure 10. MC3372 Circuit Schematic
MixerOut
4
3
VCC
OSC1
-+-""M~
Squelch Out
, - 15
-}
Gnd
200 9
RAout
6
DEC
7
IFOul
53k
tOO JlA
8-106
MOTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
CIRCUIT DESCRIPTION
The MC3371 and MC3372 are low power narrowband FM
receivers with an operating frequency of up to 60 MHz. Its low
voltage design provides low power drain, excellent
sensitivity, and good image rejection in narrowband voice
and data link applications.
This part combines a mixer, an IF (intermediate frequency)
limiter with a logarithmic response signal strength indicator, a
quadrature detector, an active filter and a squelch trigger
circuit. In a typical application, the mixer amplifier converts an
RF input signal to a 455 kHz IF signal. Passing through an
external bandpass filter, the IF signal is fed into a limiting
amplifier and detection circuit where the audio signal is
recovered. A conventional quadrature detector is used.
The absence of an input signal is indicated by the
presence of noise above the desired audio frequencies. This
"noise band" is monitored by an active filter and a detector. A
squelch switch is used to mute the audio when noise or a
tone is present. The input signal level is monitored by a meter
drive circuit which detects the amount of IF signal in the
limiting amplifier.
APPLICATIONS INFORMATION
The oscillator is an internally biased Colpitts type with the
collector, base, and emitter connections at Pins 4, 1 and 2
respectively. This oscillator can be run under crystal control.
For fundamental mode crystals use crystal characterized
parallel resonant for 32 pF load. For higher frequencies, use
3rd overtone series mode type crystals. The coil (l2) and
resistor RD (R13) are needed to ensure proper and stable
operation at the LO frequency (see Figure 13, 45 MHz
application circuit).
The mixer is doubly balanced to reduce spurious radiation.
Conversion gain stated in the AC Electrical Characteristics
table is typically 20 dB. This power gain measurement was
made under stable conditions using 'a 50 0 source at the
input and an external load provided by a 455 kHz ceramic
filter at the mixer output which is connected to the VCC (Pin 4)
and IF input (Pin 5). The filter impedance closely matches the
1.8 kQ internal load resistance at Pin 3 (mixer output). Since
the input impedance at Pin 16 is strongly influenced by a
3.3 kO internal biasing resistor and has a low capaCitance,
the useful gain is actually much higher than shown by the
standard power gain measurement. The Smith Chart plot in
Figure 17 shows the measured mixer input impedance
versus input frequency with the mixer input matched to a
50 0 source impedance at the given frequencies. In order to
assure stable operation under matched conditions, it is
necessary to provide a shunt resistor to ground. Figures 11,
12 and 13 show the input networks used to derive the mixer
input impedance data.
Following the mixer, a ceramic bandpass filter is
recommended for IF filtering (I.e. 455 kHz types having a
bandwidth of ±2.0 kHz to ±15 kHz with an input and output
impedance from 1.5 kO to 2.0 kQ). The 6 stage limiting IF
MOTOROLA ANALOG IC DEVICE DATA
amplifier has approximately 92 dB of gain. The MC3371 and
MC3372 are different in the limiter and quadrature detector
circuits. The MC3371 has a 1.8 kQ and a 51 kQ resistor
providing internal dc biasing and the output of the limiter is
internally connected, both directly and through a 10 pF
capacitor to the quadrature detector; whereas, in the
MC3372 these components are not provided internally. Thus,
in the MC3371, no external components are necessary to
match the 455 kHz ceramic filter, while in the MC3372,
external 1.8 kQ and 51 kO biasing resistors are needed
between Pins 5 and 7, respectively (see Figures 12 and 13).
In the MC3371, a parallel LCR quadrature tank circuit is
connected externally from Pin 8 to VCC (similar to the
MC3361). In the MC3372, a quadrature capaCitor is needed
externally from Pin 7 to Pin 8 and a parallel LC or a ceramic
discriminator with a damping resistor is also needed from
Pin 8 to VCC (similar to the MC3357). The above external
quadrature circuitry provides 90° phase shift at the IF center
frequency and enables recovered audio.
The damping resistor determines the peak separation of
the detector and is somewhat critical. As the resistor is
decreased, the separation and the bandwidth is increased
but the recovered audio is decreased. Receiver sensitivity is
dependent on the value of this resistor and the bandwidth of
the 455 kHz ceramic filter.
On the chip the composite recovered audio, consisting of
carrier component and modulating Signal, is passed through
a low pass filter amplifier to reduce the carrier component
and then is fed to Pin 9 which has an output impedance of
450 O. The signal still requires further filtering to eliminate
the carrier component, deemphasis, volume control, and
further amplification before driving a loudspeaker. The
relative level of the composite recovered audio signal at Pin 9
should be considered for proper interaction with an audio
post amplifier and a given load element. The MC13060 is
recommended as a low power audio amplifier.
The meter output indicates the strength of the IF level and
the output current is proportional to the logarithm of the IF
input signal amplitude. A maximum source current of 60 jlA is
available and can be used to drive a meter and to detect a
carrier presence. This is referred to as a Received Strength
Signal Indicator (RSSI). The output at Pin 13 provides a
current source. Thus, a resistor to ground yields a voltage
proportional to the input carrier signal level. The value of this
resistor is estimated by (VCC(Vdc) - 1.0 V)/60 jlA; so for
VCC = 4.0 Vdc, the resistor is approximately 50 kQ and
provides a maximum voltage swing of about 3.0 V.
A simple inverting op amp has an output at Pin 11 and the
inverting input at Pin 10. The noninverting input is connected
to 2.5 V. The op amp may be used as a noise triggered
squelch or as an active noise filter. The bandpass filter is
designed with external impedance elements to discriminate
between frequencies. With an external AM detector, the
filtered audio signal is checked for a tone signal or for the
presence of noise above the normal audio band. This
information is applied to Pin 12.
8-107
8
MC3371 MC3372
An external positive bias to Pin 12 sets up the squelch
trigger circuit such that the audio mute (Pin 14) is open or
connected to ground. If Pin 12 is pulled down to 0.9 V or
below by the noise or tone detector, Pin 14 is internally
shorted to ground. There is about 57 mV of hyteresis at
Pin 12 to prevent jitter. Audio muting is accomplished by
connecting Pin 14 to the appropriate point in the audio path
between Pin 9 and an audio amplifier. The voltage at Pin 14
should not be lower than -D.7 V; this can be assured by
connecting Pin 14 to the pOint that has no dc component.
Another possible application of the squelch switch may
be as a carrier level triggered squelch circuit, similar to the
MC3362/MC3363 FM receivers . .In this case the meter
output can be used directly to trigger the squelch switch
when the RF input at the input frequency falls below the
desired level. The level at which this occurs. is determined
by the resistor placed between the meter drive output
(Pin 13) and ground (Pin 15).
Figure 11. Typical Application for MC3371 at 10.7 MHz
RSSIOutput
VCC =4.0 Vdc
R2
10k
1st IF 10.7 MHz
from Input
Front End
R3
100 k
c151
91
i :
r4~-+-f=-=-:::;'''''
8.2j.lH
L2
R11:
560 L
L1
TKANS9443HM
...J 6.B j.lH ±6%
'--~"""-_i> VR1 (Squelch Control)
10k
4.7k R6
560
II
RB
C1
0.01
3.3k
C7 :r
0.022 -=-
CB
0.22
AFOut
VR2 ~--tO--O to Audio
10 k
Ppwer Amp
16
- - - - - , T2:Toko
I 2A6597 HK (1 0 mm)
I or
t-=':...:.O--r-_-*-_-_--'...J 7MC-812BZ (7 mm)
i
L -_ _ _ _~-_*---~~---~~-~-_.
muRata
CFU455D2
or
equivalent
8-,108
C14
J O.1
MQTOROLA ANALOG IC DEVICE DATA
MC3371 MC3372
Figure 12. Typical Application for MC3372 at 10.7 MHz
VCC = 4.0Vdc
RSSIOutput
R2
10k
1st IF 10.7 MHz
from Input
Front End
c161
91
rl>---t-f:.:-:;:-. L1
R13 :
i :
560 L
TKANS9443HM
...J 6.8IlH±6%
.----"NV--i? VR1 (Squelch Control)
10k
4.7k R6
560
C1
0.01
R1
51 k
R8
C8
3.3k C7 ::r:
0.022 =
0.22
AFOut
VR2 ~_>--O to Audio
10 k
Power Amp
16
II
o
muRata
CFU455D2
or
equivalent
MOTOROLA ANALOG IC DEVICE DATA
J
muRata
CDB455C16
C15
0.1
8-109
MC3371 MC3372
Figure 13. Typical Application for MC3372 at 45 MHz
RSSIOutput
to Meter (Triplett - 100 kV)
VCC=4.0Vdc
R2
12k
RF Input
45 MHz C17
W
~20
C18..t-if--l
75
=
> VRl (Squelch Control)
.......---'\NIr-...
10k
4.7k R6
560
R7
R8
3.3k
C8
0.22
C7
0.022=J;
AFOut
VR2 ~_o---
«
30
a:
w
>
20
cw
0
~
Z
r
()
w
a:
10
V6
\
-20
"-
-30
-40
~
o
o
S+N
\
:so -10
"'~
N
-50
1.0
2.0
3.0
-60
-120 -110 -100 -90
4.0
!:s=>
:g
§.
IF
Q
J
800
~
~ 600
:..-- RL =~
(!J
:5
:; 200
=>
RL =330
1.0
2.0
J
o
1100
1060
./
/
/
~ 1040
,.:
I
-
...
-40
1120
(!J
.. :..-- RL = 990
,.:
o
~
I
g 400
-50
.........
g 1080
S3
;:!:
-60
1140
1200
~1000
-70
Figure 5. Regulated Output and Recovered
Audio versus Temperature
........
Figure 4. VREG versus Supply
>
-80
-30
INPUT (dBm)
Vcc(V)
--
/
""
'\
~
'~
V17 ........
,
...........
:; 1020
I
3.0
4.0
5.0
1000
-50
-25
0
25
50
18.0
f
17.5 §.
\
17.0 §
~
"-
-
75
16.5~
_ 1 6.0~
8
15.5~
«S
15.0 >
100
14.5
125
TA, AMBIENT TEMPERATURE ('C)
Vcc(V)
Figure 6. Buffer Amplifier Gains
versus Temperature
3.03
4.01
[
z
3.99
<
(!J
a: 3.97
w
LL
LL
=>
Cl
Q 3.95
c
=>
«
.g
>
\
~
~
/"'.. .........
'"
- 2.98 [
z
'",\Vdb
- 2.93 ~~
~~~
=>
2.88 ~
&
!;(
c
~~
3.93
.i;,
2.83 '§!
«
«
3.91
-50
-25
0
25
50
75
100
2.78
125
TA. AMBIENT TEMPERATURE ('C)
MOTOROLA ANALOG IC DEVICE DATA
8-117
II
MC3374
Figure 7. MC3374 Pager Receiver PCB Artwork
COPPER 1 LAYER
(Actuiil View of Surface Mount Side)
COPPER 2 LAYER
(Caution: Reversed View of Through-Hole Side)
2·0,,-----~1
COMPONENT 2 LAYER
COMPONENT 1 LAYER
RFVP
VCC + + GND
C::>
C20Cc,'"
+
+ fI'I Dc ... + OCB
Cl \;!;I
C2
+ + 3800P
~OeJCB
+0
CC3
+
+
+ C400 C3
...
0
+
+
+fI'I 0.1 CB
\;!;I
+ +
4.7
56K
100KD
D
+ +
O
+
V~c
+~
'!1 +
~\;!;IGND
+
+
+
+ (+l+
+
1.0fl'l 0 \;!;I
+
\;!;I 01 10
.
+ +
++
+
+ +
+
+ +
~+
L1
+
+
+FL1
xD:
0.Q1
0
L2
c::>
Q
00.Q1 +
0
+
+
+
0 +
O.33k+O.obO.~.
+
+
+ +
100 39ko lOOk + +
+ 8.2k
+ U
+
LC1'"
+
+
+
+
+ +
+ 3.3~ D8.2k
LEi£ij
+0 0.22
D
DataOIP
~
~
O
0
0
...
+
0
RL
+
+E b+1 +
+na.
+Disable
SMA
NOTE: ... = Through Hoi.
8-118
MOTOROLA ANALOG IC DEVICE DATA
MC3374
CIRCUIT DESCRIPTION
The MC3374 is an FM narrowband receiver capable of
operation to 75 MHz. The low voltage design yields low
power drain and excellent sensitivity in narrowband voice
and data link applications. In the typical application the mixer
amplifies the incoming RF or IF signal and converts this
frequency to 455 kHz. The signal is then filtered by a 455 kHz
ceramic filter and applied to the first intermediate frequency
(IF) amplifier input, before passing through a second ceramic
filter. The modulated IF signal is then applied to the limiting IF
amplifi,er and detector circuitry. Modulation is recovered by a
conventional quadrature detector. The typical modulation
bandwidth available is 3.0 to 5.0 kHz.
Features available include buffers for audio/data
amplification and active filtering, on board voltage regulator,
low battery detection circuitry with programmable level, and
receiver disable circuitry. The MC3374 is an FM utility
receiver to be used for voice and/or narrowband data
reception. It is especially suitable where extremely low power
consumption and high design flexibility are required.
APPLICATION
The MC3374 can be used as a high performance FM IF for
the use in low power dual conversion receivers. Because of
the MC3374's extremely good sensitivity (0.6 IlV for 20 dB
(S+N/N, see Figure 3)), it can also be used as a stand alone
single conversion narrowband receiver to 75 MHz for
applications not sensitive to image frequency interference.
An RF preamplifier will likely be needed to overcome
preselector losses.
The oscillator is a Colpitts type which must be run under
crystal control. For fundamental mode crystals choose
resonators, parallel resonant, for a 32 pF load. For higher
frequencies, use a 3rd overtone series mode type. The coil
l2 and RD resistor are needed to ensure proper operation.
The best adjacent channel and sensitivity response occur
when two 455 kHz ceramic filters are used, as shown in
Figure 1. Either can be replaced by a 0.1 IlF coupling
capacitor to reduce cost, but some degradation in sensitivity
and/or stabil'ity is suspected.
The detector is a quadrature type, with the connection
from the limiter output to the detector input provided
internally. A 455 kHz LC tank circuit must be provided
externally. One of the tank pins (Pin 8) must be decoupled
using a 0.1 IlF capacitor. The 56 kg damping resistor (see
Figure 1), determines the peak separation of the detector
(and thus its bandwidth). Smaller values will increase the
separation and bandwidth but decrease recovered audio and
sensitivity.
The data buffer is a noninverting amplifier with a nominal
voltage gain of 2.7 VN. This buffer needs its dc bias
(approximately 250 mV) provided externally or else
debiasing will occur. A 2nd order Sail en-Key low pass filter,
as shown in Figure 1, connecting the recovered audio output
to the data buffer input provides the necessary dc bias and
some post detection filtering: The buffer can also be used as
an active filter.
MOTOROLA ANALOG IC DEVICE DATA
The audio buffer is a non inverting amplifier with a nominal
voltage gain of 4.0 VN. This buffer is self-biasing so its input
should be ac coupled. The two buffers, when applied as
active filters, can be used together to allow simultaneous
audio and very low speed data reception. Another possible
configuration is to receive audio only and include a
noise-triggered squelch.
The comparator is a noninverting type with an open
collector output. Typically, the pull-up resistor used between
Pin 14 and VCC is 100 kU With RL =100 kg the comparator
is capable of operation up to 25 kHz. The circuit is
self-biasing, so its input should be ac coupled.
The regulator is a 1.07 V reference capable of sourcing
3.0 mAo This pin (Pin 17) needs to be decoupled using a
1.0-10 IlF capacitor to maintain stability of the MC3374.
All three VCCs on the MC3374 (VCC, VCC2, VCC3) run on
the same supply voltage. VCC is typically decoupled using
capacitors only. VCC2 and VCC3 should be bypassed using
the RC bypasses shown in Figure 1. Eliminating the resistors
on the VCC2 and VCC3 bypasses may be possible in some
applications, but a reduction in sensitivity and quieting will
likely occur.
The low battery detection circuit gives an NPN open
collector output at Pin 20 which drops low when the MC3374
supply voltage drops below 1.2 V. Typically it would be pulled
up via a 100 kn resistor to supply.
The 1.2 V Select pin, when connected to the MC3374 supply,
programs the low battery detector to trip at VCC < 1.1 V. Leaving
this pin open raises the trip voltage on the low battery detector.
Pin 15 is a receiver enable which is connected to VCC for
normal operation. Connecting this pin to ground shuts off
receiver and reduces current drain to ICC < 0.5 /lA.
APPENDIX
Design of 2nd Order Sallen-Key Low Pass Filters
is+
R1
Input
C1
~ ~
1
L-vv-,
R2
~
~
~
"~
C2
Bias
•
Low Pass Output
OtofoHz
Avo=K
The audio and data buffers can easily be configured as active
low pass filters using the circuit configuration shown above.
The circuit has a center frequency (fo) and quality factor (0)
given by the following:
f
-
1
0 - 2lt v'R1R2C1C2
0=
1
jR2C2
R1C1
+ jR1C2 + (1-K) jR1C1
R2C1
R2C2
If possible, let R1 = R2 or C1 = C2 to simplify the above
equations. Be sure to avoid a negative 0 value to prevent
instability. Setting 0
filter response.
= 1/./2 = 0.707 yields a maximally flat
8-119
II
:
MC3374,
Data Buffer Design
Audio Buffer Design
The data buffer is designed as follows:
The audio buffer is designed as follows:
fo= 200 Hz
C2 0.01 !J.F
Q 0.707 (target)
fa 3000 Hz
R1 R2 8.2 kQ
Q 0.707 (target)
C1
K
=
= =
=
= =
=
=2.7 (data buffer open loop voltage gain)
Setting C1 =C2 yields:
fa =
K
=3.9 (audio bufferopen loop voltage gain)
Setting C1 =C2 yields:
1
fa =
2n;C1JR1R2
Q =
1
/C2. + (1-K) yC2
{c1
yCf
=
Iteration yields R2 4.2 (R1) to make Q 0.707.
Substitution into the equation for fa yields:
R1 38 kQ (use 39 kQ)
R2 4.2(R1) 180 kQ
C1 C2 0.01 !J.F
=
=
8-120
= =
=
1 ,
Q =
M+(2-K)~
=
1
2:nR1JC1C2
=
=
Iteration yields C2 2.65 (C1) to make Q 0.707.
Substitution into the equation for fa yields:
C1 3900 pF
C2 2.65(C1) 0.01 !J.F
R1 = R2 = 8.2 kQ
=
=
=
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13055
Wideband FSK Receiver
The MC13055 is intended fo RF data link systems using carrier
frequencies up to 40 MHz and FSK (frequency shift keying) data rates up to
2.0 M Baud (1.0 MHz). This design is similar to the MC3356, except that it
does not include the oscillator/mixer. The IF bandwidth has been increased
and the detector output has been revised to a balanced configuration. The
received signal strength metering circuit has been retained, as has the
versatile data slicer/comparator.
WIDEBAND
FSK
RECEIVER
SEMICONDUCTOR
TECHNICAL DATA
• Input Sensitivity 20 IlV @ 40 MHz
• Signal Strength Indicator Linear Over 3 Decades
• Available in Surface Mount Package
• Easy Application, Few Peripheral Components
PSUFFIX
PLASTIC PACKAGE
CASE 648
o
SUFFIX
PLASTIC PACKAGE
CASE 7518
(50-16)
II
PIN CONNECTIONS
Figure 1. Block Diagram and Application Circuit
Comparator Gnd
1
eomparatorVcc 2
Vee
IF Ground
Squelch
Adjust
(meter)
3
IFVee
4
13
Carrier Detect
Limiter Input
5
12
Meter Drive
Limiter Bias {
6
QuadBias
B
9
Quad Input
ORDERING INFORMATION
Device
MC13055D
L2
MOTOROLA ANALOG IC DEVICE DATA
MC13055P
Operating
Temperature Range
TA = - 40 to +85°C
Package
50-16
Plastic DIP
8-121
MC13055
MAXIMUM RATINGS
Rating
Power Supply Voltage.
Operating Supply Voltage Range
Symbol
Value
Unit
VCC(max)
15
Vdc
Vdc
V2, V4
3.0 to 12
Junction Temperature
TJ
150
c.C
Operating Ambient Temperature Range
TA
-40 to +85
°c
Storage Temperature Range
Tstg
-65 to +150
°c
Power Dissipation, Package Rating
Po
1.25
W
ELECTRICAL CHARACTERISTICS (VCC =5.0 Vdc, fo = 40 MHz, fmod;' 1.0 MHz, Af =±1.0 MHz, TA = 25°C, test circuit of Figure 2.)
Characteristic'
Conditions
Min
Typ
Max
Unit
rnA
12+ 14
-
20
25
Data Comparator Pull-Down Current
116
-
10'
-
rnA
Meter Drive Slope versus Input
112
4.5
7.0
9.0
llA/dB
Carrier Detect Pull-Down Current
113
-
1.3
-
rnA
Carrier Detect Pull-Up Current
113
-
500
-
IlA
Carrier Detect Threshold Voltage
V12
690
800
1010
mV
DC Output Current
110,111
430
-
I1A
Recovered Signal
Vl0-Vll
-
350
-
mVrms
IlVrms
Total Drain Current
Sensitivity for 20 dB S + NIN, BW
S + NIN atVin
VIN
-
20
-
Vl0-Vll
-
30
-
dB
Rin
Cin
Pin 5, Ground
-
4.2
4.5
-
-
k1l
pF
Rin
Cin
Pin9t08
-
7.6
5.2
-
k1l
pF
=5.0 MHz
=50 IlV
Input Impedance
@
40 MHz
Quadrature Coil Loading
-
Figure 2. Test Circuit
VCCo---.--------*~~2
3
100pF
14
4
5
22pF r-----,
13
Carrier
--+--.-------o-=t
Detect Output
Input o-J I-l-......
12
J--C>---t-------f---O Meter Drive
6
11
0.1
7
10
J--C>--~"""--f-----O
Detector
Output
0.Q1 ~
3.9k
39pF
r
,
3.9k
Coils - Shielded
Coilcraft UNHO/142
L 1 Gray 8--1/2 Turns, nominal 300 nH
L2 Black 10-1/2 Turns, nominal 380 nH
I
I
IL _ _ _ _ _ _ _ _ .JI
8-122
MOTOROLA ANALOG IC DEVICE DATA
MC13055
Figure 3. Overall Gain, Noise, AM Rejection
o
/'
iXl-l0
~
-20
~
0-30
/
UJ
UJ
a: -SO
Out~ut tm~ = 1.0'MHz -
/
-
At= 1.0 MHz
;;(
iiJ
L
fE
~ "
"-
"'
~ AMR1.0kHz
I--
30%
ffi
t:u
""-
"' "'
J
./
)(...
'\.
400
--
./.
. /i /
300
~
..........
'-/
100
-100
Figure 5. Untuned Input: Limiting Sensitivity
versus Frequency
I_- -10 1--.
ffi
en
~
~
:::;
~
~
-SO
.-{IO
-70
V-
i -~
-20
'~1~~20k
......
10
20
-- -- - -
0.1 ~
,./
30 40
SO
60
70
t, INPUT FREQUENCY (MHz)
80
Quadrature
Coil Tuning
40 MHz
90
-
II
o
100
403
I
1\,.11
limiting
SensHivity
f-
I I I
-
39.4
39.3
39.2
I I I
3.0
5.0
7.0
9.0
11
VCC, SUPPLY VOLTAGE (Vdc)
MOTOROLA ANALOG IC DEVICE DATA
13
15
20
30
40 SO
60
70
t, INPUT FREQUENCY (MHz)
"0 1200
40.1 'N
40.0 ~
39.9 ~
39.8 Z
39.7 ~
...J
39.60
(.)
39.5 Cl
/
__~~__~~__~~__~~~
10
80
90
100
Figure 8. Detector Current and Power Supply
Current versus Supply Voltage
f - 40.2
r-
.....
'1C].J
...,........::",...;::::-I---+--+-
Figure 7. Limiting Sensitivity and Detuning
versus Supply Voltage
1.0
.-{IO
-40
INPUT SIGNAL (dBm)
-130
O~~
o
~
0.1
r-'npu1~~
51
MC13055
20k
7
8
-30 rr- 0.1~
-40
:Z -90
;> -100
12V
Figure 6. Untuned Input: Meter Current
versus Frequency
-20
-80
3.0V
800r--.--.---r--.--.---~~--------~
0
_~
---
o
-20
./V/
~
V/
,
::;; 200
/
.-{IO
-40
SIGNAL INPUT (dBm)
-100
."
(.)
"\.
.-{IO
vcc 5.0 v\o V
:::>
Noise
--
I
!
600
;!: 500
""-
/
2:
'5-40
I
.......
1/
~
Figure 4. Meter Current versus Signal
a
~
:1.
;:- 1000
:z
UJ
a:
a:
:::>
--
800
(.)
a:
~
~
Cl
:!::
+
~
-
600
....... f-"'""
400
....
- -
60 -
J..-I--:
110+111
50
L.--~
I
o
o
12+14
::;
20
J
a:
UJ
~
10 ~
o
3.0
a:
(.)
303::
:::>
en
./
1.0
!z
UJ
40 gj
/
200
1
5.0
7.0
9.0
11
Vcc, SUPPLY VOLTAGE (Vdc)
13
+
Sl!
15
8-123
MC13055
Figure 10. Carrier Detect Threshold versus
Temperature
Figure 9. Recovered Audio versus Temperature
>1000
j
S
4.0
g
~ 2.0
~
0
o
0-2.0
is
~ ......
o:z: 900
~ r-
~-~
1"-'
13
IX:
r'
~
.........
..........
800
~-4.0
..........
Cl
IX:
;;: 600
~
-40
-20
0 20
40
60 80 100
TA. AMBIENTTEMPERATURE (0C)
120
'"
:;: 500
-60
140
~ 500
400
5IX:
~ 300
:;;
~ 200
¢P
~
.,;
,,/"
,....
100
-60 -40
-40
·-50
r-
"""-.
120
140
~
I~
r--.... ~
--- -- -- .,;V·
0
20 40
60 80 100
TA. AMBIENT TEMPERATURE (OC)
~ -50
-20 ~ ~
!-30 .........
-20
E
In~utOdbm
r.. r- .........
-10
-40
Figure 12. Input Limiting versus Temperature
Figure 11. Meter Current versus Temperature
600
II
......
W
-60
!z
l:l!
IX:
,
i""---.
taw
..... 700
~-6.0
5-6.0
w
IX: -10
o
:;: -12
......
E -60
f:@
w
Cl
z
.~
" ......, l":::::~
-.... ... ,::' ...... ~.....:...;
120
/"
~
:::; -80
~
:-- ...........
.,;-"
0-
Z
......... .........:::: ........ "
" ...... ....
-20 0
20 40
60 80 100
TA. AMBIENT TEMPERATURE (0C)
-70
>=
..........
-60
1--'
(f)
-; -90
:>
140
-60 -40 -20
0 20
40 60 80 100 t20
TA. AMBIENT TEMPERATURE (OC)
140
Figure 13. Input Impedance, Pin 5
1.0
0.5
o
1.0
8-124
MOTOROLA ANALOG IC DEVICE DATA
MC13055
Figure 14. Test Fixture
(Component Layout)
II
1~"'--------4" ---------1.-'
(Circuit Side View)
4"
1
.4
.1
.-
-
-
-
MOTOROLA ANALOG IC DEVICE DATA
-
-
-
4"
----------'~I
8-125
II
!
~
Figure 15. Internal Schematic
i~
n c- ~"
74
-
~r
lr '
77
85
>-013
66
78 79
:-~
68
92
89
91
90
14
~,
'
.
94
92
~-t
69
12 0--
1
'
~~"
_~'r
8(
1
15
~
46 ,
65
5
==1
~
0
:a
6
7
':~~~x
~HHHH~'
>
5~
I""
0
"c
('j
m
:$1
0
m
C
~
):Ii
3
......,z6
'" 58
~
'1 57
~
"1 56
~
'" 55
~
'-t 54
~
52
"1'
~
Co)
en
~'36
T
......25
=i=
s:
o
.....
g
8
L
~~~~
26
0
l>
Z
l>
Q
9
. 4
tft~
38
10
27
3~
",29
'28
48
11
47
51
'-153
'-t
~
~ ~50
49
MC13055
GENERAL DESCRIPTION
The MC13055 is an extended frequency range FM IF,
quadrature detector, signal strength detector and data
shapero It is intended primarily for FSK data systems. The
design is very similar to MC3356 except that the
oscillator/mixer has been removed, and the frequency
capability of the IF has been raised about 2:1. The detector
output configuration has been changed to a balanced,
open--collector type to permit symmetrical drive of the data
shaper (comparator). Meter drive and squelch features have
been retained.
The limiting IF is a high frequency type, capable of being
operated up to 100 MHz. It is expected to be used at 40 MHz
in most cases. The quadrature detector is internally coupled
to the IF, and a 2.0 pF quadrature capacitor is internally
provided. The 20 dB quieting sensitivity is approximately
20 IlV, tuned input, and the IF can accept signals up to
220 mVrms without distortion or change of detector
quiescent DC level.
The IF is unusual in that each of the last 5 stages of the
6 stage limiter contains a signal strength sensitive, current
sinking device. These are parallel connected and buffered
to produce a signal strength meter drive which is fairly linear
for IF input signals of 20 IlV to 20 mVrms (see Figure 4).
A simple squelch arrangement is provided whereby the
meter current flowing through the meter load resistance flips
a comparator at about 0.8 Vdc above ground. The signal
strength at which this occurs can be adjusted by changing
the meter load resistor. The comparator (+) input and output
are available to permit control of hysteresis. Good positive
action can be obtained for IF input signals of above
20 IlVrms. A resistor (R) from Pin 13 to Pin 12 will provide
VCclR of feedback current. This current can be correlated to
an amount of signal strength hysteresis by using Figure 4.
The squelch is internally connected to the data shapero
Squelch causes the data shaper to produce a high (VCC)
output.
The data shaper is a complete "floating" comparator, with
diodes across its inputs. The outputs of the quadrature
detector can be fed directly to either or preferably both inputs
of the comparator to produce a squared output swinging from
VCC to ground in inverted or noninverted form.
II
MOTOROLA ANALOG IC DEVICE DATA
8-127
®
MOTOROLA
MC13109
Universal Cordless Telephone
Subsystem IC
UNIVERSAL CT-1
SUBSYSTEM
INTEGRATED CIRCUIT
The MC131 09 integrates several of the functions required for a cordless
telephone into a single integrated circuit. This significantly reduces
component count, board space requirements, and external adjustments. It is
designed for use in both the handset and the base.
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna Input to Audio Output
80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic Discriminator
52
• Compander
- Expandor Includes Mute, Digital Volume Control and Speaker Driver
- Compressor Includes Mute, ALC and limiter
II
1
FBSUFFIX
PLASTIC PACKAGE
CASE848B
(QFP-52)
•
• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with No External Switches
- Universal Design for Domestic and Foreign CT-1 Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector, and 14-Bit
Programmable Counter and 2nd LO with 12-Bit Counter
- Transmit Section Contains Phase Detector and 14-Bit Counter
- MPU Clock Output Eliminates Need for MPU Crystal
48
1
FTASUFFIX
PLASTIC PACKAGE
CASE 932
(ThinQFP)
• Supply Voltage Monitor
- Externally Adjustable Trip Point
ORDERING INFORMATION
• 2.0 to 5.5 V Operation with One-Third the Power Consumption of
Competing Devices
• AN1575: Refer to Application Note for a List of "Worldwide Cordless
Telephone Frequencies" (Chapter 8 Addendum of DL128 Data Book)
Device
Tested Operating
Temperature Range
MC13109FB
MC13109FTA
Package
QFP-52
TA = -20° to +85°C
TQFP-48
Simplified Block Diagram
Rxln ---+--~
Rx
Out
+--<
Carrier -+-_ _
Detect
Tx In -+---+------1
Tx Out -+---+--.':===~
Low
i----I----J'--- Battery
L--_ _- '
Indicator
Tx VCO -+---+----1
This device contains 6,609 active transistors.
IH28
MOTOROLA ANALOG IC DI;VICE DATA
MC13109
Figure 1. MC131 09FB Test Circuit
~-~~~~--~77------------4-----------------------------------------------,
o
ExLCJn o
Open
VCCE
A32
lOOk
~
-
o
ExCAef
C35
LOI
A31
lOOk
Open
O.OI~F
MixUn
VCC
C43
...----------'-1
O.1~F
In
330
Oul
In
~
Gnd ~
Out
~
C34
1.0~F
CF2
C5
O.1~F
R24
10
R23
1.5k
EXCjF
r-.-'o/OIIr-+-""~-'"
C33 0.1 ~F 455k
In
R23
10.2
L2
R22
12k
A12
lOOk
L--,--.....,.,~----t---O
VCCD
13 DA
12 DB
14 VCC Ls!nd
A16
49.9k
A9
1.0k
VCCA
cia
CIU.OV
1.0~F
,~! I~
'-_______
r
DeCOul
C21
C23
~
O.OOI~F
C22
O.I~F
A17
5.62k
AlB
20k
Open
Rlll.Ok
l__~====~------~~====~~ ~Om
C17
DA Ul0m
DB
A14
130
147~F
o---Q EXCSAJn
ExpJF
SA_CUI
MOTOROLA ANALOG IC DEVICE DATA
8-129
II
MC13109
Figure 2. MC13109FTA Test Circuit
AX..Audlo
o
Open
A32
lOOk
o
lC47
l,~
MIC_
Amp
Out
VCCI2 ExLRef
A2B
o Open
49,9k
A29
A31
C46
9 Tlun
ExLC)n
VCCE
49,91<
lOOk
A36 0,0047
22,lk ~F
A35
32,4k
C45
A34 O,l~F
Cl
9-35pF
1,5k
I}--'-::::-:------;;------'-j In
~
~
C5
A2
O,I~F
32,4k
AI
1,5k
I}-~
_________
AS
32,4k
8
CF2
~In
,.
~
Gnd
!!,l
3 Out
1ll
A4
lOOk
+--I--1N5"1~40--+ C1
+----l~----i 15pF
C13
0.01
A22
12k
L._-+-ICY--t~F
~
5,OV
AudloJnJn
DA..FiI
o
Open
CIU,OV
DA..ln
A16
49,9k
CIB
Rll
1,Ok
4
1,0~F
r; r'I~F
C19
C20
Ul
DA
5 DB
14 VCC
Ul
Gnd 7
DA
DB
' -_ _ _ _ _ _ _ _ _ _ _1"'-14 VCC
lS09
Out 3
Gnd 7
LS09
&-130
MOTOROLA ANALOG IC DEVICE DATA
MC13109
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
Vee
-0.5 to +5.5
Vdc
Junction Temperature
TJ
-65 to +150
°e
NOTE: 1. Devices should not be operated at these limits. The "Recommended Operating Conditions"
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Min
TYP
Max
Unit
Vee
2.0
-
5.5
Vdc
Operating Ambient Temperature
-20
-
85
°e
Characteristic
NOTE: All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (Vee =2.6 V, TA =25°C, RF In =46.61 MHz, fDEV =±3.0 kHz,
fmod = 1.0 kHz; Test Circuit Figure 1.)
Characteristic
POWER SUPPLY
Static Current
Active Mode (Vee =2.6 V)
Active Mode (Vee =3.6 V)
Receive Mode (Vee =2.6 V)
Receive Mode (Vee =3.6 V)
Standby Mode (Vee =2.6 V)
Standby Mode (Vee =3.6 V)
Inactive Mode (Vee =2.6 V)
Inactive Mode (Vee =3.6 V)
MOTOROLA ANALOG IC DEVICE DATA
Min
Typ
Max
Unit
-
6.7
7.1
4.3
4.5
300
600
40
56
12
mA
mA
mA
mA
IlA
IlA
IlA
IlA
-
7.0
600
80
-
II
8-131
MC13109
ELECTRICAL CHARACTERISTICS (continued)
FM Receiver
The FM receivers can be used with either a quad coil or a
ceramic resonator. The FM receiver and 1st LO have been
designed to work for all country channels, including 25
channel U.S., without the need for any external switching
circuitry (see Figure 29).
(Test Conditions: VCC = 2.6 V, TA = 25°C, fO = 46.61 MHz, fDEV = ±3.0 kHz, fmod = 1.0 kHz.)
Characteristic
Condition
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
VSIN
-
0.7
-
I1Vrms
Sensitivity (Input for 12
dBSINAD)
Matched Impedance
Differential Input
Mixl
Inl/2
DetOut
1st Mixer Conversion
Gain
Yin = 1.0 mVrms, with
CFl Load
Mixl
Inl/2
CFl
MXgainl
-
10
-
dB
2nd Mixer Conversion
Gain
Yin = 3.0 mVrms, with
CF2 Load
Mix21n
CF2
MXgain2
-
20
-
dB
1st and 2nd Mixer Gain
Total
Yin = 1.0 mVrms, with
CFl and CF2 Load
Mixl
Inl/2
CF2
MXgainT
24
30
-
dB
1st Mixer Input
Impedance
-
-
Mixllnl
Mixl1n2
Zinl
-
1.0
-
kO
2nd Mixer Input
Impedance
-
-
Mix21n
Zin2
-
3.0
-
kG
1st Mixer Output
Impedance
-
-
Mixl0ut
Zoutl
-
330
-
0
2nd Mixer Output
Impedance
-
-
Mix20ut
Zout2
-
1.5
-
kG
IF -3.0 dB Limiting
Sensitivity
fin =455 kHz
Lim In
DetOut
IF Sens
-
55
-
I1Vrms
Total Hannonic Distortion
(CCITT Atter)
With RC = 8.2 knI
0.01 I1F Filter at Det
Out
Mixl
Inl/2
DetOut
THD
-
0.7
-
%
Recovered Audio
With RC = 8.2 knI
0.01 I1F Filter at Det
Out
Mixl
Inl/2
DetOut
AFO
80
100
154
mVrms
-
Lim In
DetOut
BW
-
20
-
kHz
Signal to Noise Ratio
Yin = 10 mVrms,
RC = 8.2 knlO.01 I1F
Mixl
Inl/2
DetOut
SN
-
49
-
dB
AM Rejection Ratio
30% AM, Vin=
10mVrms,
RC = 8.2 knlO.001 I1F
Mix1
Inl/2
DetOut
AMR
-
37
-
dB
First Mixer 3rd Order
Intercept (Input
Referred)
Matched Impedance
Input
Mix1
Inl/2
Mix10ut
TOlmixl
-
-10
-
dBm
Second Mixer 3rd
Order Intercept (Input
Referred)
Matched Impedance
Input
Mlx21n
Mix20ut
TOlmix2
-
-27
-
dBm
-
DetOut
Zo
-
870
-
0
Demodulator Bandwidth
Detector Output
Impedance
8-132
-
MOTOROLA ANALOG IC DEVICE DATA
MC13109
ELECTRICAL CHARACTERISTICS (continued)
RSSIICarrier Detect
Connect 0.01 !LF to Gnd from "RSSI" output pin to form the
carrier detect filter. "CD Out" is an open collector output
which requires an external 100 kn pull-up resistor to Vce.
The carrier detect threshold is programmable through the
MPU interface.
(RL = 100 kn, VCC = 2.6 V, TA = 25'C.)
Characteristic
RSSI Output Current
Dynamic Range
Carrier Sense Threshold
Condition
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
-
Mix11n
RSSI
RSSI
-
65
-
dB
CO Threshold Adjust =
(10100)
Mix11n
CO Out
VT
-
22.5
-
JlVrms
-
Mix11n
CO Out
Hys
-
2.0
-
dB
Output High Voltage
Vin = 0 JlVrms, RL =
100 kn, CO = (10100)
Mix11n
CO Out
VOH
VCC-0.1
2.6
-
V
Output Low Voltage
Vin = 100 JlVrms, RL =
100 kQ, CO = (10100)
Mix11n
CO Out
VOL
-
0.01
0.4
V
Carrier Sense Threshold
Adjustment Range
Programmable through
MPU Interface
-
-
VTrange
-20
-
11
dB
Carrier Sense Threshold
- Number of Steps
Programmable through
MPU Interface
-
-
VTn
-
32
-
-
Hysteresis
Data Amp Comparator (see Figure 4)
Inverting hysteresis comparator. Open collector output
with internal 100 kQ pull-up resistor. A band pass filter is
connected between the "Det Ouf' pin and the "DA In" pin with
component values as shown in the attached block diagram.
The "DA In" input signal is ac coupled.
(VCC=26V TA=25°C)
Condition
Input
Pin
Measure
Pin
Symbol
Hysteresis
-
OAln
OAOut
Hys
Threshold Voltage
-
OAln
OAOut
VT
Input Impedance
-
-
OAln
Output Impedance
-
-
Characteristic
Min
Typ
Max
Unit
40
50
mV
VCC-0.9
VCC-0.7
VCC-O.s
V
ZI
-
11
-
kQ
OAOut
Zo
-
100
-
kQ
30·
Output High Voltage
Vin = VCC-1.0V,
IOH=OmA
OAln
OAOut
VOH
VCC-O.1
2.6
-
V
Output Low Voltage
Vin = VCC - 0.4 V,
IOL=OmA
OAln
OAOut
VOL
-
0.03
0.4
V
MOTOROLA ANALOG Ie DEVICE DATA
8-133
II
MC13109
ELECTRICAL CHARACTERISTICS (continued)
Pre-AmplifierlExpanderiRx MuteNolume Control (See Figure 4)
The Pre-Amplifier is an inverting rail-to-rail output swing
the half supply reference so the input and output swing
capability will increase as the supply voltage increases. The
operational amplifier with the non-inverting input terminal
volume control can be adjusted through the MPU interface.
connected to the internal VB half supply reference. External
resistors and capacitors can be connected to set the gain and
The "Rx Audio In" input signal is ac coupled.
frequency response. The expander analog ground is set to
(Test Conditions' VCC = 2 6 V TA = 25°C 'in = 10kHz, Set External Pre-Amplifier R's for Gain of I, Volume Control = (0111»
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
-
RxAudio
In
Pre-Amp
AVOL
-
60
-
dB
-
RxAudio
In
Pre-Amp
GBW
-
100
-
kHz
Pre-Amp Maximum
Output Swing
RL= 10k.Q
RxAudio
In
Pre-Amp
VOmax
-
VCC-0.3
-
Vpp
Expander 0 dB Gain
Level
Vin=-10dBV
RxAudio
In
EOut
G
-3.0
-0.11
3.0
dB
Expander Gain
Tracking
Vin = -20 dBV, Output
RelatlvetoG
Vin = -30 dBV, Output
RelativetoG
RxAudio
In
EOut
Gt
-21
-19.65
-19
dB
-42
-39.42
-37
Total Harmonic
Distortion
Vin = -10 dBV
RxAudio
In
EOut
THD
-
0.5
-
%
Maximum Output
Voltage
Increase input voRage
until output- voltage
THD = 5%, then
measure output
voltage. RL = 10 k.Q
RxAudio
In
EOut
VOmax
"'"
-5.0
-
dBV
Attack Time
Ecap = 1.0 IlF,
Rfilt=20kQ
(See Appendix B)
RxAudio
In
EOut
ta
-
3.0
-
ms
Release Time
Ecap = 1.0 IlF,
Rfilt=20kQ
(See Appendix B)
RxAudio
In
EOut
tr
-
13.5
-
ms
Compressor to
Expander Crosstalk
V (Rx Audio In)
= 0 Vrmli.
Vin=-10dBV
Cln
EOut
CT
-
-
-70
dB
RxMute
Vin=-10dBV
No popping
detectable during Rx
Mute transitions
RxAudio
In
EOut
Me
-
-70
-
dB
Volume Control Range
Programmable through
MPU Interface
-
-
VCrange
-14
-
16
dB
Volume Control Steps
Programmable through
MPU Interface
-
-
VCn
-
16
-
-
Characteristic
Condition
Pre-Amp Open Loop
Gain
Pre-Amp Gain
Bandwidth
8-134
MOTOROLA ANALOG IC DEVICE-DATA
MC13109
ELECTRICAL CHARACTERISTICS (continued)
Speaker AmplifierlSP Mute
The Speaker Amplifier is an inverting rail-to-rail
operational amplifier. The non-inverting input terminal is
connected to the internal VB half supply reference. External
resistors and capacitors are used to set the gain and
frequency response. The "SA In" input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.)
Characteristic
Maximum Output
Swing
SP Mute
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
VCC=2.3V,
RL=l30Q
VCC=2.3V,
RL=600Q
VCC=3.4 V,
RL=600Q
SA In
SA Out
VOmax
-
0.8
-
Vpp
-
2.0
-
-
3.0
-
Vin =-20 dBV
RL=130Q
No popping detectable
during SP Mute
transitions
SA In
-
-70
-
Condition
SA Out
Mic Amplifier (See Figure 6)
The Mic Amplifier is an inverting rail-to-rail output
operational amplifier with the non-inverting input terminal
connected to the internal VB half supply reference. External
Msp
dB
resistors and capacitors are connected to set the gain and
frequency response. The ''Tx In" input is ac coupled.
(Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.)
Condition
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Open Loop Gain
-
Tx In
Amp Out
AVOL
-
60
-
dB
Gain Bandwidth
-
Tx In
Amp Out
GBW
100
-
kHz
RL= 10ka
Txln
Amp Out
VOmax
-
VCC-0.3
-
Vpp
Characteristic
Maximum Output
Swing
MOTOROLA ANALOG IC DEVICE DATA
Unit
8-135
II
MC13109
ELECTRICAL CHARACTERISTICS (continued)
Compressor/ALcrrx Mute/Limiter (See Figure 5)
The compressor analog gound is set to the half supply
reference so the input and output swing capability will
increase as the supply voltage increases. The "C In" input is
ac coupled. The ALC (Automatic Level Control) provides a
soft limit to the output signal swing as the input voltage
increases slowly (Le., a sine wave is maintained). The Limiter
circuit limits rapidly changing signal levels by clipping the
signal peaks. The ALC and/or Limiter can be disabled
through the MPU serial interface.
(Test Conditions: VCC = 2.6 V, lin = 1.0 kHz, TA = 25°C.)
Input
Pin
Measure
Pin
Symbol
Min
Typ
Max
Unit
Compressor 0 dB Gain
Level
Vin=-10dBV, ALC
disabled, Limiter
disabled
Cln
Lim Out
G
-3.0
- =-12 dBV, Vout = 0.8 Vpp
-30
/
-40
",
V
.....-
V
=
-50
-80
Vin=-2.5dBV, Vout =-12 dBV
~
~
!3
§
I
-40
-30
(Rapidly Changing Limited Signals)
Yin > = -28 dBV, Vout = 2.25 Vpp
I
.L ___
Vin=-24dBV, Vout =-17 dBV
(Slowly Changing ALC Signals)
I
I
I
-50
-80
~
:8.
I
D-
S
k
=
Figure 6. Total T x Path, Mic Amp Gain 16 dB,
Splatter Amp Gain 9.0 dB
10.---.----.,---.----.----,----.----,
:> Figure 5. Typical Compressor/ALC/Limiter Response
-20
-10
o
-50
-60
-40
-30
-20
o
-10
INPUT LEVEL, Tx INPUT (dBV)
COMPRESSOR, Cin LEVEL INPUT (dBV)
Figure 7. MC13109FTA Internal I/O Block Diagram
Spl
Ref
Tx
Out
Amp
In
Lim
Out
C
Cap
Cln
Amp
Out
Gnd
Audio
L~
Mixl
In
Inl
Mixl
In2
PLL
Mix1
Vref
Out
Rx
PD
Gnd
PLL
Tx
PD
Tx
VCO
VCCRF
Clk
Out
CDOuV
Hardware
Interrupt
BD
Out
DA
Out
SA
SA
Out
In
MOTOROLA ANALOG IC DEVICE DATA
EOut
Vec
Audio
DA
In
PreAmp
Out
Rx
Audio
In
Det
Out
RSSI
8-139
II
MC13109
PIN FUNCTION DESCRIPTION
48-TQFP
Pin
52-QFP
Pin
Symbol
Type
1
2
1
2
L021n
L020ut
-
3
3
PLLVref
Supply
Description
These pins form the PLL reference oscillator when connected to an external
parallel-resonant crystal (10.24 MHz typical). The reference oscillator is also the
second Local Oscillator (L02) for the RF receiver.
Vo~age Regulator output pin. The internal voltage regulator provides a stable power
supply voltage for the Rx and T x PLL's and can also be used as a regulated supply
voltage for the other IC's.
II
4
4
RxPD
5
5
Gnd PLL
Gnd
6
6
TxPD
Output
7
7
ECap
-
8
8
Tx VCO
Input
Transmit divide counter input which is driven by an ac coupled external transmit
loop VCO. The minimum signal level is 200 mVpp @ 80.0 MHz. This pin also
functions as the test mode input for the counter tests.
9
10
11
9
10
11
Data
EN
Clk
Input
Microprocessor serial interface input pins for programming various counters and
control functions.
12
12
ClkOut
Output
Microprocesor Clock Output which is derived from the 2M LO crystal oscillator and
a programmable divider. It can be used to drive a microprocessor and thereby
reduce the number of crystals required in the system design. The driver has an
intemal resistor in series with the output whch can be combined with an extemal
capacitor to form a low pass filter to reduce radiated noise on the PCB. This output
also functions as the output for the counter test modes.
N/A
14
Status Out
Output
This pin indicates when the internal latches may have lost memory due to a power
glitch.
13
15
CD Out!
Hardware
Interrupt
Output!
Input
Dual function pin; 1) Carrier detect output (open collector w~h external 100 k.Q
pull-up resistor. 2) Hardware interrupt input which can be used to "wake-up' from
Inactive Mode.
14
16
BDOut
Output
Low battery detect output (open collector with extemal pull-up reSistor).
15
17
DAOut
Output
Data amplifier output (open collector with internal 100 kQ pull-up resistor).
16
18
SA Out
Output
Speaker amplifier output.
Output
Three state voltage output of the Rx Phase Detector. This pin is either "high", "low",
or "high impedance" depending on the phase difference of the phase detector input
signals. During lock, very narrow pulses with a frequency equal to the reference
frequency are present. This pin drives the external Rx PLL loop filter. It is important
to minimize the line length and capacnance of this pin.
Ground pin for PLL section of IC.
Three state voltage output of the T x Phase Detector. This pin is either "high", "low",
or "high impedance" depending on the phase difference of the phase detector input
signals. During lock, very narrow pulses with a frequency equal to the reference
frequency are present. This pin drives the external T x PLL loop filter. It is important
to minimize the line length and capacitance on this pin.
Expander rectHier filter capacitor pin. Connect capacitor to VCC.
17
19
SA In
Input
18
20
EOut
Output
Expander output.
VCC supply for audio section.
Speaker amplifier input (ac coupled).
19
21
VCCAudio
Supply
20
22
DAln
Input
21
23
Pre-Amp Out
Output
22
24
RxAudio In
Input
23
25
DetOut
Output
24
26
RSSI
-
N/A
27
N/A
-
Note used.
25
28
QCoil
-
A quad coil or ceramic discriminator are connected to this pin.
26
29
VCCRF
Supply
27
28
30
31
LimC2
LimC1
-
11-140
Data amplHier input (ac coupled).
Pre-amplifier output for connection of pre-amplifier feedback resistor.
Rx audio input to pre-amplifier (ac coupled).
Audio output from FM detector.
Receive signal strength indicator filter capacitor.
VCC supply for RF receiver section.
IF amplifierllimiter capacitor pins.
MOTOROLA ANALOG IC DEVICE DATA
MC13109
PIN FUNCTION DESCRIPTION (continued)
48-TQFP
Pin
52-QFP
Pin
Symbol
Type
Description
29
32
Lim In
Input
Signal input for IF amplifierllimiter.
30
33
GndRF
Gnd
Ground pin for RF section of the IC.
31
34
Mix20ut
Output
32
35
Mix21n
Input
33
36
VB
-
34
37
Mix10ut
Output
35
38
Mix11n2
Input
36
39
Mix11n1
Input
37
38
40
41
L011n
L010ut
-
Second mixer output.
Second mixer input.
Internal half supply analog ground reference.
First mixer output.
Negative polarity first mixer input.
Positive polarity first mixer input.
Tank elements for 1st LO multivibrator oscillator are connected to these pins.
39
42
VcapCtrl
-
40
43
Gnd Audio
Gnd
Ground for audio section of the IC.
T x path input to Microphone Amplifier (ac coupled).
41
44
Tx In
Input
42
45
Amp Out
Output
43
46
Cln
Input
44
47
CCap
-
45
48
Lim Out
Output
46
49
Spl Amp In
Input
47
50
Tx Out
Output
48
51
Ref
Input
N/A
52
N/A
-
1st LO varactor control pin.
Microphone amplifier output.
Compressor input (ac coupled).
Compressor rectifier filter capacitor pin. Connect capacitor to VCC.
T x path limiter output.
Splatter amplifier input (ac coupled).
T x path audio output.
Not used.
Power Supply Voltage
This circuit is used in a cordless telephone handset and
base unit. The handset is battery powered and can operate
on two ro three NiCad cells or on 5.0 V power.
PLL Frequency Synthesizer General Description
Figure 8 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL). This
dual PLL is fully programmable thorugh the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), France, Spain, Australia, Korea, New
Zealand, U.K., Netherlands and China (see channel
frequency tables in Appendix A).
The 2nd local oscillator and reference divider provide the
reference frequency for the Rx and T x PLL loops. The
MOTOROLA ANALOG IC DEVICE DATA
II
Reference voltage input for low battery detect.
programmed divider value for the reference divider is
selected based on the crystal frequency and the desired Rx
and T x reference frequency values. Additional divide by 25
and divide by 4 blocks are provided to allow for generation of
the 1.0 kHz and 6.25 kHz reference frequencies required for
the U.K. The 14-bit T x counter is programmed for the desired
transmit channel frequency. The 14-bit Rx counter is
programmed for the desired first local oscillator frequency. All
counters power up in the proper default state for USA
channel #6 and for a 10.24 MHz reference frequency crystal.
Internal fixed capacitors can be connected to the tank circuit
of the 1st LO through microprocessor control to extend the
sensitivity of the 1st LO for U.S. 25 channel operation.
8--141
MC13109
Figure 8. Dual PLL Simplified Block Diagram
Tx VCO
8,8
Tx
VCO
TxPD
LPF
6,6
12-b
+25
Programmable
+4
Reference
+1
Counter
RxPD
ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C)
Characteristic
Condition
Min
Max
VIL
-
0.3
V
VIH
'PLL Vref - 0.3
"VCCAudio"
V
IlL
-5.0
-
!lA
IIH
-
5.0
!lA
Vhys
1.0
-
V
RxPD
TxPD
10H
-
-0.7
rnA
RxPD
TxPD
10L
0.7
-
rnA
PLLPIN DC
-
Input Voltage Low
Data
Clk
EN
II
Hardware In!.
Input Voltage High
-
Data
Clk
Input Current Low
Yin = 0.3 V
Data
Clk
EN
EN
Input Current High
Yin = (VCC Audio) - 0.3
Data
Clk
EN
Hysteresis Voltage
-
Output Current High
-
Output Current Low
-
Output Voltage Low
IIL=0.7rnA
RxPD
TxPD
VOL
-
(PLL Vrefl* 0.2
V
Output Voltage High
IIH =-0. 7rnA
RxPD
TxPD
VOH
(PLL Vref)* 0.8
-
V
Tri--State Leakage Current
V= 1.2V
RxPD
TxPD
10Z
-50
50
nA
Cin
-
8.0
pF
Cout
-
8.0
pF
Data
Clk
EN
Input Capacitance
-
Data
Clk
Output Capacitance
-
RxPD
TxPD
EN
8-142
MOTOROLA ANALOG IC DEVICE DATA
MC13109
ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C)
Characteristic
Condition
Min
Max
PLL PIN INTERFACE
EN to Clk Setup Time
-
EN, Clk
Data to Clk Setup Time
-
Data, Clk
Hold Time
-
Data, Clk
tsuEC
200
-
ns
tsuDC
100
ns
th
90
Recovery Time
-
EN, Clk
tree
90
-
Input Pulse Width
-
EN,Clk
tw
100
-
ns
Input Rise and Fall Time
-
Data
Clk
EN
tr,tl
-
9.0
Ils
MPU Interface Power-Up
Delay
90% 01 PLL Vrel to
Data, Clk, EN
ns
ns
-
-
!puMPU
-
100
IlS
Measure
Pin
Symbol
Min
Max
Unit
L021n
L02°ut
lLO
-
12
MHz
TxVCO
Itxmax
-
80
MHz
PLLLOOP
Characteristic
Condition
-
2nd LO Frequency
"Tx VCO" Input Frequency
Vin = 200 mVpp
PLL I/O Pin Specifications
The 2nd LO, Rx and Tx PLL's and MPU serial interface are
normally powered by the internal voltage regulator at the
"PLL Vref' pin. The "PLL Vref' pin is the output of a voltage
regulator which is powered from the "Vee Audio" power
supply pin. Therefore, the maximum input and output levels
for most PLL 1/0 pins (L02 In, L02 Out, Rx PD, Tx PD, Tx
VeO) is the regulated voltage at the "PLL Vret" pin. The ESD
protection diodes on these pins are also connected to "PLL
Vref'. Internal level shift buffers are provided for the pins
(Data, elk, EN, elk Out) which connect directly to the
microprocessor. The maximum input and output levels for
these pins is Vee. Figure 9 shows a simplified schematic of
the PLL 1/0 pins.
Figure 9. PLL I/O Pin Simplified Schematics
PLL Vref
(2.2 V)
VCC Audio
(2.0 to 5.5 V)
PLL Vref
(2.2 V)
VCC Audio
(2.0 to 5.5 V)
OO+'"~~~~~
-=
L02 In, L02 Out,
Rx PO, Tx PO and
Tx veo Pins
-= -=
2.0 I!A -=
Data, Clk, and EN Pins
-=-=
ClkOutPin
Microprocessor Serial Interface
The "Data", "elk", and "EN" pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counter and various
control functions. The "Data" and "elk" pins are used to load
data into the shift register. Figure 10 shows "Data" and "elk"
pin timing. Data is clocked on positive clock transitions.
MOTOROLA ANALOG IC DEVICE DATA
Figure 10. Data and Clock Timing Requirement
II
II
Data,
Clk, EN
Data
Clk------'
\"----
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the "EN" pin.
This is done in two steps. First, an 8-bit address is loaded
into the shift register and latched into the 8-bit address latch
register. Then, up to 18-bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 11 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
Figure 11. Enable Timing Requirement
EN _ _ _. J
Previous Data Latched
8-143
MC13109
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 12 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when "EN" is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the "EN" high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
Figure 12. Microprocessor Interface Programming
Mode Diagrams
oata---{ MSB
ENJ
8-BH Address
Address Register Programming Mode
oata---{ MSB
16-BitOata
LSB)-____________________
-J
~
~~t~
EN __________________________
2.0_V____
~L...PU
__......;___
elk, EN
Status Out
This is a digital output which indicates whether the latch
registers have, been reset to their power-up default values.
Latch power-up default values are given in Figure 32. If there
is a power glitch or ESD event which causes the latch
registers to be reset to their default values, the "Status our
pin will indicate this to the MPU so it can reload the correct
information into the latch registers.
~
The MPU serial interface is fully operational within 100 j.1s
after the power supply has reached its minimum level during
power-up (See Figure 13). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx , and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
8-144
:-A
______
Figure 14. Status Out Operation
~I
Oata Register Programming Mode
II
Figure 13. Microprocessor Serial Interface
Power-Up Delay
Status Latch Register Bits
Status Out
Logic Level
Latch bits not at power-up default value
0
Latch bits at power-up default value
1
Data Registers
Figure 1'5 'shows the data latch'registers and addresses
which are used to select each of these registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
"Don't care" bits can be loaded into the shift register first if
8-bit bytes of data are loaded.
'
MOTOROLA ANALOG IC DEVICE DATA
MC13109
Figure 15. Microprocessor Interface Data Latch Registers
>
Latch Address
14-Bit Tx Counter
LSB
1. (00000001)
Tx Counter Latch
14-Bit Rx Counter
LSB )
2. (00000010)
Rx Counter Latch
MSB
12-Btt Reference Counter
LSB
3. (00000011)
Reference Counter Latch
4. (00000100)
l~it
Mode Control Latch
5-Bit CD Threshold Control
5. (00000101)
Threshold Control Latch
6. (00000110)
7. (00000111)
7-Bit Auxiliary Latch
Reference Frequency Selection
The "L02In" and "L02 Out" pins form a reference oscillator
when connected to an external parallel-resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 16 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries.
Figure 16. Reference Frequency and
Reference Divider Values
Crystal
Frequency
Reference
Divider
Value
U.K. Basel
Handset
Divider
Reference
Frequency
10.24 MHz
10.24 MHz
2048
1
5.0 kHz
1024
4
2.5 kHz
11.15 MHz
2230
1
5.0 kHz
12.00 MHz
2400
1
5.0 kHz
11.15 MHz
1784
1
6.25 kHz
11.15MHz
446
4
6.25 kHz
11.15MHz
446
25
1.0 kHz
MOTOROLA ANALOG IC DEVICE DATA
Reference Counter
Figure 17 shows how the reference frequencies for the Rx
and Tx loops are generated. All countries except U.K. require
that the Tx and Rx reference frequencies be identical. In this
case, set "U.K. Base Selecf' and "U.K. Handset Selecf' bits
to "0". Then the fixed divider is set to "1" and the Tx and Rx
reference frequencies will be equal to the crystal oscillator
frequency divided by the programmable reference counter
value. The U.K. is a special case which requires a different
reference frequency value fo T x and Rx.
For U.K. base operation, set "U.K. Base Select" to "1". For
U.K. handset operation, set "UK Handset Selecf' to "1". The
Netherlands is also a special case since a 2.5 kHz reference
frequency is used for both the Tx and Rx reference and the
total divider value required is 4096 which is larger than the
maximum divide value available from the 12-bit reference
divider (4095). In this case, set "U.K. Base Select" to "1" and
set "U.K. Handset Select" to "1". This will give a fixed divide
by 4 for both the Tx and Rx reference. Then set the reference.
divider to 1024 to get a total divider of 4096.
Mode Control Register
Power saving modes, mutes, disables, volume control,
and microprocessor clock output frequency are all set by the
Control Register. Operation of the Control Register is
explained in Figures 18 through 25.
8-145
MC13109
Figure 17. Reference Register Programming Mode
U.K. Base
~
12-b
Tx Reference Frequency
U.K. Handset
+ 25
Programmable + 4 I--++~.~
Reference
......U.K. Base
Counter
+1
- .......
Rx Reference Frequency
U.K. Handset
U.K. Handset
Select
U.K. Base
Select
TxDivider
Value
RxDivider
Value
Application
0
0
1
1
0
1
0
1
1
25
4
4
1
4
25
4
. All but U.K. and Nethe~ands
U.K. Base Set
U.K. HandSet
Netherlands Base and Hand Set
MSI;l
12-8it Ref Counter
LSB
14--Bit Reference Counter Latch
Figure 18. Control Register Bits
Figure 19. Mute and Disable Control Bit Descriptions
ALC Disable
1
0
Automatic Level Control Disabled
Normal Operation
Limiter Disable
1
0
Limiter Disabled
Normal Operation
Clock Disable
1
0
MPU Clock Output Disabled'
Normal Operation
Tx Mute
1
0
Transmit Channel Muted
Normal Operation
Rx Mute
1
0
Receive Channel Muted
Normal Operation
SPMute
1
0
Speaker Amp Muted
Normal Operation
Power Saving Operating Modes
When the MC13109 is used in a handset, it is important to
conserve power in order to prolong battery life. There are five
modes of operation; Active, Rx , Standby, Interrupt and
Inactive. In Active Mode, all circuit blocks are powered. In Rx
mode, all circuitry is powered down exept for those circuit
8-146
sections needed to receive a transmission from the base. In
the Standby and Interrupt Modes, all circuitry is powered
down except for the circuitry needed to provide the clock
output for the microprocessor. In Inactive Mode, all circuitry is
powered down except the MPU interface. Latch memory is
maintained in all modes. Figure 20 shows the control register
bit values for selection of each power saving mode and
Figure 21 show the circuit blocks which are powered in each
of these operating mode.
Figure 20. Power Saving Mode Selection
Stdby
Mode
Bit
Rx
Mode
Bit
"CD OutlHardware
Interrupt" Pin
Power Saving
Mode
0
0
X
Active
0
1
X
Rx
1
0
X
Standby
1
1
1 or High Impedance
Inactive
1
1
0
Inactive
MOTOROLA ANAI-OG IC DEVICE DATA
MC13109
Figure 21. Circuit Blocks Powered During Power Saving Modes
Active
Rx
Standby
Inactive
"PLL Vrel" Regulated
Voltage
X
X
Xl
Xl
MPU Interface
X
X
X
X
2nd LO Oscillator
X
X
X
MPU Clock Output
X
X
X
X
Circuit Blocks
RF Receiver
X
1st LOVCO
X
X
RxPLL
X
X
Carrier Detect
X
X
Data Amp
X
X
Low Battery Detect
X
X
TxPLL
X
Rx Audio Path
X
Tx Audio Path
X
NOTE: 1. In Standby and Inactive Modes, 'PLL Vrer remains powered but is not regulated. It will fluctuate wHh Vee.
Inactive Mode Operation and Hardware Interrupt
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the MC13109 into the Inactive mode, which turns off the
MPU Clock Output (see Figure 22), and then disable the
microprocessor. In order to give the MPU adequate time to
power down, the MPU Clock output remains active for a
minimum of one reference counter cycle (about 200 ~s) after
the command is given to switch into the "Inactive" mode. An
external timing circuit should be used to initiate the turn-on
sequence. The "CD Out" pin has a dual function. In the Active
and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is
disabled and the "CD Ouf' pin is in a "High" state due to the
external pull-up resistor. In the Inactive mode the "CD Out"
pin is the input for the hardware interrupt function. When the
"CD Out" pin is pulled "low" by the external timing circuit, the
MC13109 swtiches from the Inactive to the Interrupt mode
thereby turning on the MPU Clock Output. The MPU can then
resume control of the combo IC. The "CD Out" pin must
remain low until the MPU changes the operating mode from
Interrupt to Standby, Active or Rx modes.
Figure 22. Hardware Interrupt Operation
Mode
ActiveIR x
IV
EN
CD OuVHardware Interrupt
Inactive
CD Out Low
i.
I ,
MPU Clock Out
1
I
Delay after MPU selects Inactive Mode to when CD turns off.
MOTOROLA ANALOG IC DEVICE DATA
Interrupt
'" MPU Initiates
Inactive Mode
-I ~
--!OJ
.....,......,
r
/
CDTumsOff
"'
Standby/Rx/Active
External Timer
Pulls Pin Low
/
MPU Initiates
Mode Change
I'limeroutput
Disabled
""'- K
1
1
1_
"MPU Clock Oul' remains active for a minimum of one count of reference
counter after 'CD OuVHardware Interrupt" pin goes high
8-147
II
MC13109.·
"Clk Out" Divider Programming
The "Clk Out" pin is derived from the 2nd local oscillator
and can be used to drive a microprocessor, thereby reducing
the number of crystals required. Figure 23 shows the
relationship between the crystal frequency and the clock
output for different divider values. Figure 24 shows the "Clk
Out" register bit values.
Flgur. 23. Clock Output Valu ••
Crystal
Frequency
Clock Output Divider
2
3
5
10
10.24 MHz
5.120 MHz
3.413 MHz
2.5aOMHz
2.046 MHz
11.15 MHz
5.575 MHz
3.717 MHz
2.788 MHz
2.230 MHz
12.00 MHz
a.OOOMHz
4.000 MHz
3.000 MHz
2.400 MHz
Figure 24. Clock Output Dlvld.r
ClkOut
Bit #1
ClkOut
Bit #0
ClkOut
Divider Value
0
0
2
0
1
3
1
0
1
MPU"Clk Out" Radiated Nols. on Circuit Board
The clock line running between the MC13109 and the
microprocessor has the potential to radiate noise which can
cause problems in the system especially If the clock Is a
square wave digital signal with large high frequ.ncy
harmonics. In order to minimize radiated noise, a 1.0 kn
resistor is included on-chlp In-series with the "Clk Out" output
driver. A small capaCitor can be connected to the "Clk Ouf' line
on the PCB to form a single pole low pass filter. This filter will
significantly reduce noise radiated from the "Clk Out" line.
Volume Control
The volume control can be programmed in 2.0 dB gain
steps from -14 dB to +16 dB. The power-up default value is
OdB.
.
5
. 10
1
MPU "Clk Out" Pow.......Up Default Dlvld.r Value
The power-up default divider value Is "divide by 10". This
provld.s an MPU clock of about 1.0 MHz after initial
power-up. The reason for choosing this relatively low clock
frequency after Intlal power-up is that some microprocessors
that operate down to a 2.0 V power supply have a maximum
clock frequency fo 1.0 MHz. After initial power-up, the MPU
can change the clock divider value to set the clock to the
desired operating frequency. Special care has been taken in
the design of the clock divider to ensure that the transition
between one clock divider value and another Is "smooth"
(I.e., there will be no narrow clock pulses to disturb the MPU).
Flgur. 25. Volum. Control
Volume Control
Bit #3
Volume Control
Bit #2
Volume Control
Bit #1
Volume Control
Bit #0
Volume
Control #
Gain/Attenuation
Amount
0
0
0
0
0
-14dB
0
0
0
1
1
-12dB
0
0
1
0
2
-10dB
0
0
1
1
3
-8.0 dB
0
1
0
0
4
-6.0 dB
0
1
0
1
5
-4.0 dB
0
1
1
0
6
-2.0 dB
0
1
1
1
7
OdB
1
0
0
0
8
2.0 dB
1
0
0
1
9
4.0dB
1
0
1
0
10
a.OdB
1
0
1
1
11
8.0 dB
1
1
0
0
12
10dB
1
1
0
1
13
12dB
1
1
1
0
14
14 dB
1
1
1
1
15
16dB
Gain Control Register
The gain control register contains bits which control the
Carrier Detect threshold. Operation of these latch bits are
explained in Figures 26 and 27.
6-148
Figure 26. Gain Control Latch Bits
MBB
5-B1t CD Threshold Control
LBB
.MOTOROLA ANALOG IC DEVICE DATA
MC13109
Carrier Detect Threshold Programming
Th "CD Out" pin will give an indication to the
microprocessor if a carier signal is present on the selected
channel. The nominal value and tolerance of the carrier
detect threshold is given in the carrier detect specification
section of this document. If a different carrier detect threshold
value is desired, it can be set through the MPU interface as
shown in Figure 27 below.
Figure 27. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
Bit #1
CD
81t#O
CD
Control #
Carrier Detect
Threshold
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
-20 dB
1
1
-19dB
1
a
2
-18 dB
1
1
3
-17 dB
1
a
4
-16dB
1
a
a
1
5
-15 dB
1
1
a
6
-14 dB
1
1
1
7
-13dB
1
a
a
a
8
-12dB
1
9
-11 dB
1
a
10
-10dB
1
a
a
a
a
1
1
11
-9.0 dB
1
1
a
12
-8.0 dB
1
1
a
a
1
13
-7.0 dB
1
1
1
a
14
-6.0 dB
1
1
1
1
15
-5.0 dB
1
a
a
a
a
a
a
a
16
-4.0 dB
1
17
-3.0 dB
1
a
18
-2.0 dB
1
1
19
-1.0dB
1
a
20
OdB
1
a
a
1
21
1.0dB
1
1
a
22
2.0 dB
1
a
a
a
a
a
a
a
a
1
1
1
23
3.0 dB
1
1
0
0
0
24
4.0 dB
a
1
25
5.0 dB
1
a
26
6.0 dB
1
1
27
7.0 dB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
1
1
1
28
8.0 dB
1
1
a
a
a
1
1
29
9.0 dB
1
1
1
1
a
30
10dB
1
1
1
1
1
31
11 dB
MOTOROLA ANALOG IC DEVICE DATA
II
8-149
MC13109
schematic of the 1st LO tank circuit., Figure 30 shows the
latch control bit values.
The Internal varactor temperature coefficient Is 1800 ppm/°C
(CO =8.9 pF at 25°C, Vcap control voltage =1.2 V, Freq =
36 MHz). Customer Is sugg,ested to use a negative
temperature coefficient capacitor In 1st LO tank circuit when
the whole operating temperature range of -40 to +85°C Is
considered.
Auxiliary Reglater
The auxiliary register contains a 3-bit 1st LO Capacitor
Selection latch and a 4-bit Test Mode latch. Operation of
these latch bits are explained In Figures 28, 29 and 30.
Figure 28. Auxiliary Reglater Latch Bite
Msa
Lsa
+-BIt Test Mode
Msa 3-BH 1st LO Capacitor
Selection
LSa
Figure 29. 1st LO Schematic
--------------,
I
I VcapCtrl
Flret Local 08clllator Capacitor Selection for 25
Channel U.S. Operation
There Is a very large frequency difference between the
minimum and maximum channel frequencies in the proposed
25 Channel U.S. standard. The sensitivity of the 1st LO is not
large enough to accommodate this large frequency variation.
Fixed capacitors can be connected across the 1st LO tank
circuit to change the 1st LO sensitivity. Internal switches and
capacitors are provided to enable microprocessor control
over Internal fixed capaCitor values. Figure 29 shows the
Figure 30. 1st LO CapaCitor Select for U.S. 25 Channela
II
1st LO
Cap.
BIU
1st LO
Cap.
Bit 1
0
0
0
0
0
0
0
1
1st LO
Cap.
Selact
U.S.
U.S.
Baae
Channels
Handaet
Channela
Internal
Cap. Value
(Excluding
Varactor)
0
0
16-25
0
0
-
1
1
0
1et LO
Cap
Bit 0
Extarnal
CapaCitor
Value
External
Inductor
Valua
-
0.92 pF
10 - 6.4 pF
27pF
0.47 ~H
16-25
0.92 pF
10-6.4pF
33pF
0.47~H
1-6
-
2.61 pF
10-6.4pF
27pF
0.47~H
2
7-15
-
1.82 pF
10-6.4 pF
27pF
0.47 ~H
-
1-6
8.69 pF
10-6.4 pF
33pF
0.47~H
7-15
7.19pF
10-6.4pF
33pF
0.47~H
0
1
1
3
1
0
0
4
8-150
Varactor
Value over
0.5 to 2.2 V
Ranga
MOTOROLA ANALOG Ie DEVICE DATA
MC13109
Figure 31. Test Mode Description
Counter Under Test or
Test Mode Option
"TxVCO"
Input Signal
TM#
TM3
TM2
TM1
TMO
0
0
0
0
0
Normal Operation
"Clk Out" Output Expected
1
0
0
0
1
Rx Counter, upper 6
Ot02.2V
Input Frequency/64
2
0
0
1
0
Rx Counter, lower 8
Ot02.2V
See Note Below
3
0
0
1
1
Rx Prescaler
Ot02.2V
Input Frequency/4
4
0
1
0
0
Tx Counter, upper 6
o to 2.2 V
Input Frequency/64
5
0
1
0
1
Tx Counter, lower 8
6
0
1
1
0
Tx Prescaler
7
0
1
1
1
Reference Counter
Ot02.2 V
Input Frequency/Reference Counter Value
8
1
0
0
0
Divide by 4, 25
Ot02.2V
Input Frequency/100
9
1
0
0
1
10
1
0
1
0
=10 Option
AGC Gain =25 Option
-
>200mVpp
Oto 2.2V
See Note Below
Input Frequency/4
>200mVpp
AGC Gain
N/A
-
N/A
-
NOTE: To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value 01 the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6 bits 01 the divisor). II Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value Is Divisor (3;2) (btts 2 and 3
01 the divisor). II Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
Test Modes
Test Mode Control latch bits enable independent testing
of internal counters and set AGC Gain Options. In test
mode, the "Tx VCO" input pin is multiplexed to the input of
the counter under test and the output of the counter under
test is multiplexed to the "Clk Out" output pin so that each
counter can be individually tested. Make sure test mode bits
are set to "0" for normal operation. Test mode operation is
described in Figure 31. During normal operation and when
testing the Tx Prescaler, the "Tx VCO" input can be a
minimum of 200 mVpp at 80 MHz and should be ac coupled.
For other test modes, input signals should be standard logic
levels of 0 to 2.2 V and a maximum frequency of 16 MHz.
Power-Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The MC13109 is initially placed in
the Rx mode with all mutes active and nothing disabled. The
reference counter is set to generate a 5.0 kHz reference
frequency from a 10.24 MHz crystal. The MPU clock output
divider is set to 10 to give the minimum clock output frequency.
The Tx and Rx latch registers are set for USA Channel
Frequency #21. Figure 32 shows the initial power-up states
for all latch registers.
Figure 32. Latch Register Power-Up Defaults
MSB
LSB
Register
Count
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Tx
9966
-
-
1
0
0
1
1
0
1
1
1
0
1
1
1
0
Rx
7215
-
-
0
1
1
1
0
0
0
0
1
0
1
1
1
1
Ref
2048
-
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Mode
N/A
-
0
0
0
0
1
1
0
1
1
1
0
1
1
1
1
Gain
N/A
-
-
-
-
-
-
1
0
1
0
0
-
-
-
-
-
-
-
N/A
-
-
TM
-
-
0
0
0
0
0
0
0
MOTOROLA ANALOG IC DEVICE DATA
8-151
II
:
MC13109
Figure 34. ICC versus Vcc at Receive Mode
Figure 33. ICC versus VCC at Active Mode
8.0r---r---r---,...---,...-----,
~
i
~
6.0
B
4.0
~
~
;
6.0
~
2.0
iiil
It
:::.
tJ)
8.0r---r---;----.,----.,------,
2.0
0
2.5
3.0
3.5
4.0
Vee, SUPPLY VOLTAGE (V)
4.5
4.0
0
2.5
5.0
Figure 35. ICC versus VCC at Standby Mode
~
0:8
a:
a:
0.6
iiil
0.4
a
II
~
0.2
~
V
o2.5
3.0
V"
L ~
3.5
4.0
Vee, SUPPLY VOLTAGE (V)
60
./
----
4.5
o
2.5
5.0
~
~
"
-50
-120
J
AMRr
"-
I
/
-100
/'
-40
-20
o
Recovere AuY
~ 0.15
~
0.10
0.05
N
RFin, RF INPUT (dBm)
8-152
V
5.0
3.0
~ 0.20
N+D
4.5
R22=12kO
:ii !
\..
5.0
-----
3.5
4.0
Vee, SUPPLY VOLTAGE (V)
~
"""""'1\
-30
-40
~
3.0
~
0.25
AFoul
B -20
"........--
0.30
o
-10
4.5
Figure 38. Recovered Audlo/THD versus tDEV
Figure 37. RFln versus AFout, N+D, N, AMR
10
iB'
~
3.5
4.0
Vee, SUPPLY VOLTAGE (II)
Figure 36. ICC versus VCC at Inactive Mode
1.0
!z
w
3.0
o
o
""
V
2.0
/
/
./
/"
i
/
2.5
2.0
l
1.5~
1.0
/THD
4.0
6.0
fDEV, DEVIATION, (kHz)
8.0
MOTOROLA ANALOG IC DEVICE DATA
MC13109
Figure 40. First Mixer Third Order
Intercept Performance
Figure 39. RSSI Output versus RFin
1.4
/
1.2
~
1.0
/'
f-
::;)
a.
f-
O.B
::;)
0
c;;
0.6
lQ
0.4
0.2
~
o
-120
-100
/
/
e-+----~
Rx
Out
Carrier -+-+-_ _-<
Detect
Tx In
>-+----+1
Tx Out .....r-j.----=====~
Tx VCO -+-+------1
-=========-__________-...::====-__
Low
1----I-f---i~Baltery
L ___
...J
Indicator
This device contains 8,262 active transistors.
8-154
MOTOROLA ANALOG IC DEVICE DATA
VCC
Figure 1. Production Test Circuit
!l:
a
:0
o
RFln)
~
~
22.1 k
1)
)0
0.01
49.9
z
)0
g
(')
c
m
:so
m
c
~
)0
I-
(DAln
i:
o
....
....
....
o
Co)
VCCA ~.
Il,I'n
VCCA~'
22.1 k
Data
Out
""'loll
•
"
• BDl
Out
1.Sk
!
81
NOTE:
........._.....
'"'_.""
' -_ _ _ _ _......_ _•• Carrier
Detect Out
MPU Clock Output
,
MC13110
MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
VCC
-0.5 to +5.5
Vdc
TJ
-65 to +150
DC
Power Supply Voltage
Junction Temperature
NOTES: 1. Devices should not be operated at these limits. The "Recommended Operating Condnions"
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
VCC
2.7
3.6
5.0
Vdc
Operating Ambient Temperature
TA
-40
-
85
'c
Input Voltage Low (Data, Clk, EN)
V,L
-
-
0.3
V
Input Voltage High (Data, Clk, EN)
VIH
2.5
-
-
Characteristic
Supply Voltage
NOTE:
V
rnA
Output Current (Rx PO, Tx PO)
High
Low
-
IOH
IOL
0.7
-
-0.7
-
All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25'C, unless otherwise specHied;
Test Circuit Figure 1.)
Symbol
Characteristic
Static Current
Active Mode (2.7 V)
Active Mode
Receive Mode
Standby Mode
Inactive Mode
ACT ICC
ACT ICC
RxlCC
STDICC
INACTICC
Min
Typ
Max
-
8.1
8.6
4.3
270
35
12
5.3
500
80
-
Unit
-
rnA
rnA
rnA
!1A
!1A
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25 DC, Active or Rx Mode, unless otherwise specified;
rest CircuH Figure 1.)
Characteristic
Condition
PLL VOLTAGE REGULATOR
Regulated Output Level
IL=OmA
-
PLL Vref
Vo
2.4
2.5
2.6
V
Line Regulation
IL=OmA,
VCC = 3.6 to 5.5 V
VCC Audio
PLLVref
VReg
Line
-
'-0.6
20
mV
Load Regulation
VCC = 3.6V,IL= 1.0mA
Vce Audio
PLL Vref
VReg
Load
-
-1.1
20
mV
-
f2ext
-
12
-
MHz
L021n
L02°ut
f2ext
-
12
-
MHz
TxVCO
ftxmax
-
80
-
MHz
PLL LOOP CHARACTERISTICS
2nd LO Frequency
(No Crystal)
-
L021n
2nd LO Frequency
(With Crystal)
-
-
Tx VCO (Input Frequency)
~156
Yin = 200 mVpp
-
MOTOROLA ANALOG ,IC DEVICE DATA
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
PLL PHASE DETECTOR
Output Voltage Low
IIL=0.7 rnA
-
RxPD
TxPD
VOL
-
-
(PLL
Vref) *.2
V
Output Voltage High
IIH =-0.7 rnA
-
RxPD
TxPD
VOL
(PLL
Vref) *.8
-
-
V
3-State Leakage Current
V=1.2V
-
RxPD
TxPD
IOZ
-50
-
50
nA
-
-
RxPD
TxPD
Cout
-
8.0
-
pF
CLoad= 50pF
-
RxPD
TxPD
ClkOut
t r, tl
-
250
-
ns
Output Capacitance
Output Rise and Fall Time
MICROPROCESSOR SERIAL INTERFACE
Input Current Low
Vin=0.3V
Standby Mode
-
Data,
Clk, EN
IlL
-5.0
0.3
-
~
Input Current High
Vin=3.3V
Standby Mode
-
Data,
Clk, EN
IIH
-
1.5
5.0
~
Hysteresis Voltage
-
-
Data,
Clk, EN
Vhys
-
1.0
-
V
Maximum Clock Frequency
-
Data,
EN, Clk
-
-
-
2.0
-
MHz
Input Capacitance
-
Data,
Clk, EN
-
Cin
-
8.0
-
pF
EN to Clk Setup Time
-
-
EN,Clk
tsuEC
-
200
-
ns
tsuDC
-
100
-
ns
ttl
90
-
ns
Data to Clk Setup Time
-
-
Data, Clk
Hold Time
-
-
Data, Clk
Recovery Time
-
-
EN,Clk
trec
-
Input Pulse Width
-
-
EN,Clk
tw
-
100
Input Rise and Fall Time
-
-
Data,
Clk,EN
t r, tl
-
9.0
-
~
-
-
lpuMPU
-
100
-
~
Mixl1nl/2
DetOut
VSIN
-
2.8
-98
-
-
~Vrms
Mixl1nl/2
DetOut
-
1.0
-107
-
~Vrms
MPU Interface Power-Up
Delay
90% 01 PLL Vrel to Data,
Clk, EN
90
ns
ns
FM RECEIVER (IRF = 46 77 MHz [USA Ch 21] fdev = +3
- .0 kHz Imod = 10kHz)
Sensitivity (Input lor 12 dB
SINAD)
50 n Termination
Single-Ended, Matched Input
VSIN
-
dBm
dBm
Differential, Matched Input
Mixl Inl/2
DetOut
VSIN
-
.56
-112
-
IlVrms
dBm
1st Mixer Voltage
Conversion Gain
Yin = 1.0 mVrms, with CFl
Filter as Load
Mixl1nl/2
Mixl0ut
MXgainl
-
12
-
dB
2nd Mixer Voltage
Conversion Gain
Yin = 3.0 mVrms, with CF2
Filter as Load
Mix21n
Mix20ut
MXgain2
-
20
-
dB
1st and 2nd Mixer Voltage
Gain Total
Yin = 1.0 mVrms, with CFl
andCF2 Load
Mixlln1/2
Mix20ut
MXgainT
24
28
-
dB
1st Mixer Input Impedance
Single-Ended Input
-
Mixl Inll2
Rpl
CPl
-
-
875
2.7
-
n
pF
Zin2
-
3.0
-
kn
2nd Mixer Input Impedance
lin = 10.7 MHz
MOTOROLA ANALOG IC DEVICE DATA
-
Mix21n
8-157
II
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
FM RECEIVER (fRF = 46.77 MHz [USA Ch 211, fdev = ±3.0 kHz, fmod = 1.0 kHz)
1st Mixer Output
Impedancet
-
-
Mixl0ut
Zoutl
-
330
-
Q
2nd Mixer Output
Impedance
-
-
Mix20ut
Zout2
-
1.5
-
kQ
Lim In
DetOut
IF Sens
-
71
100
~Vrms
IF -3.0 dB Limiting
Sensitivity
fin = 455 kHz
Total Harmonic Distortion
With RC = 15 kll.0 nF Filter
at DetOut
Mixllnl
DetOut
THD
-
1.3
2.0
%
Recovered Audio
Vin = 3.16 mVrms with
RC = 15 kll000 pF Filter
at DetOut
Mixllnl
DetOut
AFO
80
105
150
mVrms
Lim In
DetOut
BW
-
20
-
kHz
Signal to Noise Ratio
Vin = 3.16 mVrms,
RC = 15 kll000 pF
Mixllnl
DetOut
SN
-
49
-
dB
AM Rejection Ratio
Vin = 3.16 mVrms,
30% AM, @ 1.0 kHz,
RC = 15 kll000 pF
Mixllnl
DetOut
AMR
30
47
-
dB
Mixl Inl/2
Mixl0ut
Vo
1.0dB
Mixl
-
15
-
mVrms
-
Demodulator Bandwidth
-
1st Mixer, 1.0 dB Voltage
Compression (Input Pin
Referred)
2nd Mixer, 1.0 dB Vol~ge .
Compression (Input Pin
Referred)
50Q Input
Mix21n
Mix20ut
Vo
1.0dB
Mix2
-
14
-
mVrms
1st Mixer 3rd Order
Intercept (Input Pin
Referred)
Vin = 3.98 mVrms
Mixllnl
Mixl0ut
TOlmixl
-
56
-
mVrms
2nd Mixer 3rd Order
Intercept (Input Pin
Referred)
Vin = 3.98 mVrms, 50 Q Input
Mix21n
Mix20ut
TOlmix2
-
53
-
mVrms
-
-
DetOut
Zo
-
870
-
Q
-
Mixlln
RSSI
RSSI
-
80
-
dB
Mixlln
CD Out
VT
-
33
-
~lirms
Detector Output Impedance
RSSIICARRIER DETECT (RL = 100 kQ)
RSSI Output Current
Dynamio Range
Carrier Sense Threshold
CD Threshold Adjust =
(10100)
-
Mixlln
CD Out
Hys
-
3.6
7.0
dB
Output High Voltage
Vin = 0 Vrms, CD = (10100)
Mixlln
CD Out
VOH
VCC0.1
3.6
-
V
Output Low Voltage
Vin = -80 dBV, CD= (10100)
Mixl"1
CD Out
VOL
-
0.02
0.4
V
Hysteresis
8-158
MOTOROLA ANALOG Ie DEVICE DATA
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Condition
Characteristic
RSSUCARRIER DETECT (RL = 100 kn)
Carrier Sense Threshold
Adjustment Range
Carrier Sense Threshold Number of Steps
-
-
VTlow
range
-
-
VThi
range
Programmable through MPU
Interface
-
-
VTn
Programmable through MPU
Interface
-20
-
-
-
-
11
-
32
-
-
dB
DATA AMP COMPARATOR
Hysteresis
-
OAln
OAOut
Hys
30
40
50
mV
Threshold Voltage
-
OAln
OAOut
VT
2.7
VCC0.7
-
V
Input Impedance
-
-
OAln
ZI
-
11
-
kQ
-
OAOut
Zo
-
100
-
kQ
Output High Voltage
Vin = VCC -1.0 V,
IOH=OmA
OAln
OAOut
VOH
VCC0.1
3.6
-
V
Output Low Voltage
Vin = VCC - 0.4 V,
IOL=OmA
OAln
OAOut
VOL
-
0.04
0.4
V
-
Output Impedance
EXPANDORJR x MUTE (fin = 1.0 kHz)
Absolute Gain
Vin=-20dBV
Eln
EOut
G
-3.0
0
3.0
dB
Gain Tracking
Vin =-30 dBV
Vin=-40dBV
E In
EOut
Gt
-21
-42
-20
-40
-19
-38
dB
Total Harmonic
~istortion
E In
EOut
THO
-
0.5
1.0
%
-
RxAudio In
-
-
-
-11.5
dBV
Increase input voltage until
output voltage THO = 5.0%,
then measure output voltage.
RL = 7.5 kl1.0 ~F
Eln
EOut
VOmax
-
0
-
-
RxAudio In
E In
-
Zin
-
600
7.5
-
kn
Vin =-20 dBV
Maximum Input Voltage
Maximum Output Voltage
Input Impedance
dBV
3.0
-
ms
AltackTime
Ecap = 0.5 ~F, Rlilt = 40 k
(See Appendix B)
Eln
EOut
ta
-
Release Time
Ecap = 0.5 ~F, Rlilt = 40 k
(See Appendix B)
E In
EOut
tr
-
13.5
-
ms
Compressor to Expandor
Crosstalk
Vin=-10dBV,
VIE In) = AC Gnd
Cln
EOut
CT
-
-90
-70
dB
Rx Data Muting (ll. Gain)
Vin = -20 dBV,
Rx Gain Adj = (01111)
RxAudio In
EOut
Me
-
--83
-60
dB
SPEAKER AMP/SP MUTE
Maximum Output Swing
Vin=OdBV,
RL=130Q
SA In
SA Out
VOmax
0.8
0.9
-
Vpp
Speaker Amp Muting
Vin=-20dBV
SA In
SA Out
Msp
-
-90
--80
dB
COMPRESSORlTx MUTE (lin = 1.0 kHz, Scrambler Bypass Mode, Tx Gain Adj = (01111), fin = 1.0 kHz)
Absolute Gain
Vin=-10dBV
Tx In
TxOut
G
-4.0
0
4.0
dB
Gain Tracking
Vin=-30dBV
Vin =-40 dBV
Txln
Tx Out
Gt
-11
-9.0
-13
dB
-17
-10
-20
Vin = -10 dBV
Txln
-
0.6
1.1
%
Total Harmonic Distortion
MOTOROLA ANALOG IC DEVICE DATA
TxOut
THO
8-159
MC13110
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characterlatlc
Condition
Symbol
COMPRESSORITx MUTE (fin = 1.0 kHz , Scrambler Bypass Mode, Tx Gain Ad] = (01111) fin = 1.0 kHz)
Increase Input voltage until
Maximum Output Voltage
Cln
Tx Out
VOmax
output voltage THO = 5.0%,
then measure output voltage.
RL = 7.5 kll.0 IlF
-
Input Impedance
-
dBV
10
-
kCl
-
ms·
Ir
-
13.5
-
ms
Tx Out
CT
-
-60
-40
dB
Tx Out
Mc
-
-90
-60
dB
Tx Out
ALCout
-15
-13
-11
-10
-8.0
-6.0
dBV
Tx Out
Vllm
-10
-7.0
-
Tx Out
Ccap = 0.5 IlF, Rfllt = 40 k
(See Appendix B)
Cln
Tx Out
ta
Release TIme
Ccap = 0.5 IlF, Rfllt = 40 k
(See Appendix B)
Cln
Tx Out
Expandor to Compressor
Crosstalk
Vln = -20 dBV, Speaker Amp
No Load, V(C In) = AC Gnd
E In
Tx Muting
Vin-10 dBV
Tx In
ALC OUlput Level
Vin=-10dBV
Vln = -2.5 dBV
Limiter and Mutes disabled
Tx In
Limiter' Output Level
Yin = -2.5 dBV,
ALC disabled
Tx In
Zln
-
-5.0
3.0
Cln
Attack TIme
-
dBV
Rx ANDTx SCRAMBLER (2nd LO = 10.24 MHz, Tx Gain Ad] = (01111), Rx Gain Ad] = (01111), Volume Control =(0 dB Default Levels),
SCF Clock Divider = 31. Total is divide by 62 for SCF clock frequency of 165.16 kHz)
RxAudio In
ScrOut
Rxfch
-
3.65
-
kHz
Txln
Tx Out
Txfch
-
3.879
-
kHz
RxAudlo In
Txln
EOut
Tx Out
AV
-4.0
-4.0
0
0
4.0
4.0
dB
Cln
EOut
Ripple
-
2.0
-
dB
Rx Audio In
Cln
EOut
Tx Out
fmod
4.119
4.129
4.139
kHz
Rx + Tx Path -1.0 IlF from
Tx Out to Rx AudiO In,
fin = 1.0 kHz
Cln
EOut
GO
-
1.0
-
ms
fin = low corner frequency to
high corner frequency
Cln
EOut
GO
-
4.0
-
Carrier Breakthrough
Rx + Tx Path -1.0 IlFfrom
Tx Out to Rx Audio In
Cln
EOut
CBT
-
-60
-
dB
Baseband Breakthrough
Rx + Tx Path -1.0 IlFfrom
Tx Out to Rx Audio In,
fin = 1.0 kHz,
fmeas = 3.192 kHz
Cln
EOut
BBT
-
-50
-
dB
Rx High Frequency Corner
(Note 1)
Rx Path, f = 479 Hz,
V Rx Audio In = -20 dBV
Tx High Frequency Corner
(Note 1)
Tx Path, f = 250 Hz,
V Tx In = -10 dBV, Mic Amp
= Unity Gain
Absolute Gain
Rx: Yin = -20 dBV
Tx: Vln =-10 dBV,
Limiter disabled
Pass Band Ripple
Rx + Tx Path -1.0 IlFfrom
Tx Out to Rx Audio In,
fin = low corner frequency to
high corner frequency
Scrambler Modulation
Frequency
Rx: 100 mV (-20 dBV)
Tx: 316 mV (-10 dBY)
Group Delay
NOTE: 1. The filter specification is based on a 10.24 MHz 2nd LO, and a swltched-capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
andlor SC filter counter divider ratios are used, the filter comer frequency will be proportional to the resuHing SC filter clock frequency.
8-160
MOTOROLA ANALOG IC DEVICE DATA
MC13110
ELECTRICAL CHARACTERISTICS (continued) (Vec = 3.6 V, VB = 1.5 V. TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
MIC AMP (fin = 1.0 kHz. External resistors set to gain of 1)
Open Loop Gain
-
Gain Bandwidth
-
Txln
Amp Out
AVOL
-
100,000
GBW
100
-
kHz
VN
Txln
Amp Out
RL= 10 kn
Tx In
Amp Out
VOmax
-
2.8
-
Vpp
Average Threshold
Voltage Before Electronic
Adjustment
Vee = 3.6 V. Vref_Adj =
(0111). Take average of rising
and falling threshold
Reh
Ref2
BD10ut
BD20ut
VTi
1.36
1.5
1.64
V
Average Threshold
Voltage After Electronic
Adjustment
Vec = 3.6 V, Vref_Adj =
(adjusted value). Take
average of rising and falling
threshold
Refl
Ref2
BD10ut
BD20ut
VTf
1.475
1.5
1.525
V
-
Refl
Ref2
BD10ut
BD2°ut
Hys
-
4.0
-
mV
-
Refl
Ref2
lin
-50
-
50
nA
Maximum Output Swing
LOW BATTERY DETECT
Hysteresis
Input Current
Vin = 1.0 to 2.0 V
Output High Voltage
Vin=2.0V,
RL = 3.9 kn to Vee
Refl
Ref2
BD10ut
BD20ut
VOH
Vee0.1
3.6
-
V
Output Low Voltage
Vin= 1.0V,
RL = 3.9 kn to Vee
Refl
Ref2
BD10ut
BD2°ut
VOL
-
0.1
0.4
V
II
MOTOROLA ANALOG IC DEVICE DATA
8-161
MC13110
PIN FUNCTION DESCRIPTION
Pin
1
2
Symbol
Type
Description
L021n
L020ut
-
These pins form the PLL reference oscillator when connected to an external parallel-resonant
crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (L02) for
the AF receiver. "L02 In" may also serve as an Input for an externally generated reference signal
which is typically ac-coupljld.
3
Vag
-
4
Ax PO
Output
Three state voltage output of the Ax Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector Input signals. During lock,
very narrow pulses with a frequency equal to the reference frequency are present. This pin drives
the external Ax PLL loop filter. It Is Important to minimize the line length and parasitic capacitance
of this pin.
5
PLL Vref
-
PLL voltage regulator output pin. An internal voltage regulator provides a stable power supply
voltage for the Ax. and Tx PLL's and can also be used as a regulated supply voltage for other IC's.
6
TxPD
Output
Three state voltage output of the Tx Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector input signals. During lock,
very narrow pulses with a frequency equal to the reference frequency are present. This pin drives
the external Tx PLL loop filter. It Is Important to minimize the line length and parasitic capacitance
of this pin.
7
Gnd PLL
Gnd
Ground pin for PLL section of IC.
8
Tx VCO
Input
Transmit divide counter input which is driven by an ac-coupled externallransmit loop VCO. The
minimum signal level is 200 mVpp @ 60.0 MHz. This pin also functions as the test mode Input for
the counter tests.
9
10
11
Data
Input
Microprocessor serial interface input pins for programming various counters and control functions.
12
ClkOut
Output
Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator and a
programmable divider. It can be used to drive a microprocessor and thereby reduce the number of
crystals required In the system design. The driver has an internal resistor in series with the output
which can be combined with an external capacitor to form a low pass filter to reduce radiated noise
on the PCB. This output also functions as the output for the counter test modes.
13
CD Out
I/O
14
BD10ut
Output
Low battery detect output #1 (open collector with external pull-up resistor).
Data amplifier output (open collector with internal 100 kQ pull-up resistor).
Intemal reference voltage for switched capacitor filter section.
EN
Clk
Dual function pin; 1) Carrier detect output (open collector with external 100 kn pull-up resistor.
2) Hardware interrupt input which can be used to "wake-up" from Inactive Mode.
15
DAOut
Output
16
BD20ut
Output
Low battery detect output #2 (open collector with external pull-up reSistor).
17
Tx Out
Output
Tx path audio output.
18
CCap
-
19
C In
Input
20
Amp Out
Output
21
Txln
Input
Tx path input to microphone amplifier (Mic Amp) (ac-coupled).
22
DAln
Input
Data amplifier input (ac-coupled).
23
VCC Audio
Supply
24
Ax Audio In
Input
25
DetOut
Output
26
ASSI
Output
27
28
a Coil
-
Lim Out
29
VCCAF
Supply
30
31
LimC2
Lim Cl
-
IF amplifierilimiter capacitor pins.
32
Lim In
Input
Signal input for IF amplifierlJimiter.
8-162
Compressor rectifier filter capacitor pin. Pull pin high through a capacitor.
Compressor input (ac-coupled).
Microphone amplifier output.
VCC supply for audio section.
Ax audio Input (ac-coupled).
Audio output from FM detector.
Aeceive Signal Strength Indicator filter capacitor.
A quad coli or ceramic discriminator connected to these pins as part of the FM demodulator circuit.
VCC supply for AF receiver section.
~OTOROLA
ANALOG IC DEVICE DATA
MC13110
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
Type
33
SGNDRF
Gnd
Ground pin for RF section of the IC.
Second mixer input.
34
Mix21n
Input
35
Mix20ut
Output
36
GndRF
Gnd
37
Mix10ut
Output
38
Mix11n2
input
39
Mix11n1
Input
40
41
L011n
L010ut
-
42
VcapCtrl
-
43
GndAudio
Gnd
44
SA Out
Output
45
SAln
Input
46
EOut
Output
Description
Second mixer output.
Ground pin for RF section of the IC.
First mixer output.
Negative phase first mixer input.
Positive phase first mixer input.
Tank Elements for 1st LO Multivibrator Oscillator are connected to these pins.
1st LO Varactor Control Pin.
Ground for audio section of the IC.
Speaker amplifier output.
Speaker amplifier input (ac-<:oupled).
Expandor output.
47
Ecap
-
48
E In
Input
49
ScrOut
Output
50
Ref2
-
51
Ref1
-
Reference voltage input for Low Battery Detect #1.
52
VB
-
Internal half supply analog ground reference.
Expandor rectifier filter capacitor pin. Pull pin high through a capacitor.
Expandor Input.
Rx Scrambler Output.
Reference voltage input for Low Battery Detect #2.
II
MOTOROLA ANALOG IC DEVICE DATA
8-163
MC13110
FM Receiver
The FM receiver can be used with either a quad coil or a
ceramic resonator. The FM receiver and 1st LO have been
designed to work for all country channels, including 25
channel U.S., without the need for any external switching
circuitry (see Figure 29).
.
RSSI/Carrler Detect
Connect 0.01 ~F to Gnd from "RSSI" output pin to form the
carrier detect filter. "CD Out" is an open collector output
which requires an external 100 kQ pull-up resistor to VCC.
The carrier detect threshold is programmable through the
MPU interface.
Data Amp Comparator
The data amp comparator is an inverting hysteresis
comparator. Its open collector output has an Internal 100 kO
pull-up resistor. A band pass filter is connected between the
"Det Out" pin and the "DA In" pin with component values as
shown in Figure 1 (Test Circuit). The "DA In" Input signal is
ac-coupled.
Figure 2. Data Amp Operation
I
t
Expandor/ Compressor
In Appendix B, the EIAICCITT recommendations for
measurement of the attack and decay times are defined. The
curves in Figures 3 and 4 show the typical expandor and
compressor output versus input responses.
Figure 3. Expandor Typical Response
10
o
-10
:> -20
~
'S -30
o
w -40
-50
-60
/
-40
/
/'
-30
/'
/
/' r'-EOut=O~BV
-20
E In (deV)
8-164
Typical at THO = 5.0%
-10
o
-10
V
/
V
V
V
/
Kt
Tx Ou = -5.0 deV
Typical alTHO = 5.0%
-40
-60
-50
-40
-30
-20
-10
0
10
20
Tx In (dBV)
Rx Audio Path (LPF/Rx Gain Adjust!
Rx Mute!ExpandorNolume Control)
The Rx Audio signal path goes from "Rx Audio In" (Pin 24)
to "E Out" (Pin 46). The "Rx Audio In" input signal is ac
coupled. AC couple between "Scr Out" and "E In" (see
Figure 3).
Speaker AmplSP Mute
The Speaker Amp is an inverting rail-to-rail operational
amplifier. The noninvertlng input Is connected to the internal VB
reference. Extemal resistors and capacitors are used to set the
gain and frequency response. The "SA In" Input is ac coupled.
Oala
Signal H---l_-+l-~_-+l-~_-+_
OalaAmp
Output
Figure 4. Compressor Typical Response
o
10
MlcAmp
The Mic Amp is an inverting rail-te-rail operational amplifier
with noninverting input terminal connected to internal VB
reference. External resistors and capacitors are set to the gain
and frequency response. The ''Tx In" input is ac coupled.
Tx Audio Path (Compressor/ALCITx Mute!
Llmlter/LPFITx Gain Adjust)
The Tx Audio signal path goes from "c In" (Pin 19) to "Tx
Out" (Pin 17). The "c In" input signal is ac coupled. The ALC
(Automatic Level Control) provides a "soft" limit to the output
signal swing as the input voltage increases slowly (i.e., a sine
wave is maintained). The Limiter circuit limits rapidly
changing signal levels by clipping the signal peaks. The ALC
and/or Limiter can be disabled through the MPU serial
interface (see Figure 4).
T x and Rx Scrambler
The Tx and Rx signal paths each contain a frequency
inversion scrambler in the MC13110. Each scrambler
contains a pre-mixer low pass switched capacitor filter
(SCF), a double balanced mixer and a post-mixer low pass
switched capacitor filter. The scrambler function can be
defeated by setting the Tx or Rx Scrambler Bypass bits in the
control register to "1" through the MPU interface. In this
mode, the mixer and the post-mixer LPF are bypassed and
MOTOROLA ANALOG IC DEVICE DATA
MC13110
only the pre-mixer LPF remains in the signal path. The SCF
corner frequencies are proportional to the SCF clock. The
SCF Clock Divider is programmable through the MPU
interface, (SCF Clock) = F(2nd LO)/(SCF Divider Value*2).
The scrambler modulation frequency is (SCF Clock)/40. Four
scrambler modulation frequencies may be selected (see
Figures 28 and 29).
PLL Voltage Regulator
The "PLL Vre(' pin is the internal supply voltage for the Ax
and Tx PLL's. It is regulated to a nominal 2.5 V. The "VCC
Audio" pin is the supply voltage for the internal voltage
regulator. Two capacitors with 10 IiF and 0.1 IiF values must
be connected to the "PLL Vre( pin to filter and stabilize this
regulated voltage. The "PLL Vret" pin may be used to power
other IC's as long as the total external load current does not
exceed 1.0 mAo The tolerance of the regulated voltage is
initially ±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the "PLL Vre( pin is internally connected to the
"V CC Audio" pin (i.e., the power supply voltage is maintained
but is now unregulated).
Low Battery Detect
Two external precision resistor dividers are used to set
independent thresholds for two battery detect hysteresis
comparators. The voltages on "Aef1" and "Aef2" are
compared to an internally generated 1.5 V reference voltage.
The tolerance of the internal reference voltage is initially
±6.0%. The Low Battery Detect threshold tolerance can be
improved by adjusting a trim-pot in the external resistor
divider. Alternately, the tolerance of the internal reference
voltage can be improved to ±1.5% through MPU serial
interface programming. The internal reference can be
measured directly at the "VB" pin. During final test of the
telephone, the VB internal reference voltage is measured.
Then, the internal reference voltage value is adjusted
electronically through the MPU serial interface to achieve the
desired accuracy level. The voltage reference register value
should be stored in AOM during final test so that it can be
reloaded each time the MC13110 IC is powered up. Low
Battery Detect outputs are open collector.
Power Supply Voltage
This circuit is used in a cordless telephone handset and
base unit. The handset is battery powered and can operate
on three NiCad cells or on 5.0 V supply.
PLL Frequency Synthesizer General Description
Figure 5 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL). This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), Spain, Australia, Korea, New
Zealand, U. K., Netherlands, France, and China.
The 2nd local oscillator and reference divider provide the
reference frequency for the receive (Ax) and transmit (Tx)
PLL loops. The programmed divider value for the reference
divider is selected based on the crystal frequency and the
desired Ax and Tx reference frequency values. Additional
divide by 25 and divide by 4 blocks are provided to allow for
generation of the 1.0 kHz and 6.25 kHz reference
frequencies required for the U. K. The 14-bit Tx counter is
programmed for the desired transmit channel frequency. The
14-bit Ax counter is programmed for the desired first local
oscillator frequency. All counters power up in the proper
default state for USA channel #21 (channel #6 for FCC 10
channel band) and for a 10.24 MHz reference frequency
crystal. Internal fixed capacitors can be connected to the tank
circuit of the 1st LO through microprocessor control to extend
the sensitivity of the 1st LO for U.S. 25 channel operation.
PLL I/O Pin Specifications
The 2nd LO, Ax and Tx PLL's, and MPU serial interface are
powered by the internal voltage regulator at the "PLL Vre('
pin. The "PLL Vret" pin is the output of a voltage regulator
which is powered from the "VCC Audio" power supply pin and
is regulated by an internal bandgap voltage reference.
Therefore, the maximum input and output levels for most PLL
I/O pins (L02 In, L02 Out, Ax PD, Tx PD, Tx VCO) is the
regulated voltage at the "PLL Vret" pin. The ESD protection
diodes on these pins are also connected to "PLL Vret".
Internal level shift buffers are provided for the pins (Data, Clk,
EN, Clk Out) which connect directly to the microprocessor.
The maximum input and output levels for these pins is VCC.
Figure 6 shows a simplified schematic of the I/O pins.
Figure 5. Dual PLL Simplified Block Diagram
Tx VCO
6
12-b
o
+ 25
~ 40
Programmable
Reference ' .
Counter
+1.0 Hi-+--o '---''''----I
1
L020ut
2
~
______________________________________
MOTOROLA ANALOG IC DEVICE DATA
~41
8-165
8
MC13110
Figure 6; PLL 110 Pin Simplified Schematics
PLL Vrel
(2.5 V)
VCC Audio
(2.7 to 5.5 V)
PLL Vrel
(2.5 V)
Vee Audio
(2.7 to 5.5 V)
~+,"~~~~ru
-=-
-=- -=-
L~ In, L02 Out,
2.0 JlA
-=- .
-=- -=-
Data, Clk and EN Pins
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure '9 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when "EN" is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the "EN" high state. The convention in
these figures is that latch bits to the left are loaded into the
~hift register first.
.
ClkOutPin
Rx PO, Tx PO and
Tx VCO Pins
Figure 9. Microprocessor Interface Programming
Mode Diagrams
Microprocessor Serial Interface
The "Data", "elk", and "EN" pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counters, the switched
capacitor filter clock counter, and various control functions.
The "Data" and "elk" pins are used to load data into the shift
register. Figure 7 shows the timing required on the "Data" and
"elk" pins. Data is clocked into the shift register on positive
clock transitions.
Data--{MSB
ENJ
, 6-Bit Address
Address Register Programming Mode
rv
Data--{ MSB
16-BitData
LSB'r.......- - - - - - - - - L a t - C h - . J
Latch
EN _________________________
Figure 7. Data and Clock Timing Requirement
tl
II
Data,
elk, EN
~I
'--
Data Register Programming Mode
The MPU serial interface is·fully operational within 100 j.IS
after the power supply has reached its minimum level during
power-up (see Figure 10). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx , and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Data
Figure 10. Microprocessor Serial Interface
Power-Up Delay
Clk
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the "EN" pin.
This is done in two steps. First, an 8-bit address is loaded
into the shift register and latched into the 8-bit address latch
register. Then, up to 16-bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 5 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
Figure 8. E!1able Timing Requirement
R
50%
EN
8-166
:-A
______2_.7_V_-'~_PU
_ __
Clk, EN
Data Registers
Figure 11 shows shows the data latch registers and
addresses which are used to select each of these registers.
Latch bits to the left (MSB) are loaded into the shift register
first. The LSB bit must always be the last bit loaded into the
shift register. Bits preceeding the register must be "O's" as
shown in Figure 11.
trec
50%
Previous Data Latched
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Figure 11. Microprocessor Interface Data Latch Registers
~~M_S_B
Latch Address
l~
)
________________________T_x_Cou
__n_re_r____________________________LSB
--J
1. (00000001)
Tx Counter Latch
~~_M_S_B
l_~
_____________________ __R_x_c_o_un_re_r____________________________LSB)
--J
2. (00000010)
Rx Counter Latch
MSB
12-b Reference Counter
LSB
3. (00000011)
Reference Counter Latch
4. (00000100)
Mode Controf Latch
5-b Tx Gain Control
5-b Rx Gain Control
MSB
5-b CD Threshold Control
LSB
5. (00000101)
6-b Switched
Capacitor Filter
LSB
Clock Counter Latch
6. (00000110)
Gain Control Latch
~Voltage
MSB
MSB
Reference Adjust
SCF Clock Dividers Latch
7. (00000111)
Auxiliary Latch
Figure 12. Reference Frequency and Reference Divider Values
Crystal
Frequency
Reference
Divider
Value
10.24 MHz
2048
10.24 MHz
1024
11.15MHz
2230
12.00 MHz
U.K. Basel
Handset
Divider
Reference
Frequency
SC Filter
Clock
Divider
SC Filter
Clock
Frequency
Scrambler
Modulation
Divider
Scrambler
Modulation
Frequency
1.0
5.0 kHz
31
165.16 kHz
40
4.129 kHz
4.0
2.5 kHz
31
165.16 kHz
40
4.129 kHz
1.0
5.0 kHz
34
163.97 kHz
40
4.099 kHz
2400
1.0
5.0 kHz
36
166.67 kHz
40
4.167 kHz
11.15MHz
1784
1.0
6.25 kHz
34
163.97 kHz
40
4.099 kHz
11.15MHz
446
4.0
6.25 kHz
34
163.97 kHz
40
4.099 kHz
11.15 MHz
446
25
1.0 kHz
34
163.97 kHz
40
4.099 kHz
Reference Frequency Selection
The "L02In" and "L02 Ouf' pins form a reference oscillator
when connected to an external parallel-resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 12 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries. "L02 In"
may also serve as an input for an externally generated
reference signal which is ac-coupled. The switched
capacitor filter 6-bit programmable counter must be
programmed for the crystal frequency that is selected since
MOTOROLA ANALOG IC DEVICE DATA
this clock is derived from the crystal frequency and must be
held constant regardless of the crystal that is selected. The
actual switched capacitor clock divider ratio is twice the
programmed divider ratio since there is a fixed divide by 2.0
after the programmable counter. The scrambler mixer
modulation frequency is the switched capacitor clock divided
by 40.
Reference Counter
Figure 13 shows how the reference frequencies for the Rx
and Tx loops are generated. All countries except the U.K.
8-167
MC13110
maximum divide value available from the 12-bit reference
divider (4095). In this case, set "U.K. Base Select" to "1" and
set "U.K. Handset Select" to "1". This will give a fixed divide
by 4 for both the Tx and Rx reference. Then set the reference
divider to 1024 to get a total divider of 4096.
require that the Tx and Rx reference frequencies be identical.
In this case, set "U.K. Base Select" and "U.K. Handset
Select" bits to "0". Then the fixed divider is set to "1" and the
Tx and Rx reference frequencies will be equal to the crystal
oscillator frequency divided by the programmable reference
counter value. The U.K. is' a special case which requires a
different reference frequency value for Tx and Rx. For U.K.
base operation, set "U.K. Base Selecr to "1". For U.K.
handset operation, set "U.K. Handset Selecr to "1".The
Netherlands is also a special case since a 2.5 kHz reference
frequency is used for both the Tx and Rx reference and the
total divider value required is 4096 which is larger than the
Mode Control Register
Power saving modes, mutes, disables, volume control,
and microprocessor clock output frequency are all set by the
Mode Control Register. Operation of the Mode Control
Register is explained in Figures 14 through 21.
Figure 13. Reference Register Programming Mode
U.K. Base
~ Tx Reference Frequency
U.K. Handset
12-b
+25
Programmable
Reference + 4.0 f--+-+-+
Counter
+1.01--+......- - 0 ~--- Rx Reference Frequency
U.K. Handset
U.K. Handset
Select
U.K. Base
Select
TxDivider
Value
Rx Divider
Value
Application
(j
0
1
0
1
1.0
1.0
4.0
25
4.0
All but U.K. and Netherlands
U.K. Base Set
U.K. Hand Set
Netherlands Base and Hand Set
0
1
1
25
4.0
4.0
12-b Ref Counter
LSB
14-Bit Reference Counter Latch
8-168
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Figure 14. Mode Control Register Bits
4-b Volume
Control
Figure 15. Mute and Disable Control Bit Descriptions
ALCDisable
1
Automatic Level Control Disabled
Normal Operation
0
Limiter Disable
1
1
0
Tx Mute
1
0
RxMute
1
0
SP Mute
1
Active
Rx
Standby
Inactive
X
X
X1
X1
X
MPU Interface
X
X
X
MPU Clock Output Disabled
Normal Operation
2nd LO Oscillator
X
X
X
MPU Clock Output
X
X
X
Transmit Channel Muted
Normal Operation
RF Receiver and 1st LO
VCO
X
X
Receive Channel Muted
Normal Operation
Rx PLL
X
X
Carrier Detect
X
X
Data Amp
X
X
Low Battery Detect
X
X
Tx PLL
X
Rx and T x Audio Paths
X
Speaker Amp Muted
Normal Operation
0
"PLL Vref' Regulated
Vo~age
Limiter Disabled
Normal Operation
0
Clock Disable
Figure 17. Power Saving Modes
Circuit Blocks
Power Saving Operating Modes
When the MC1311 0 is used in a handset, it is important to
conserve power in order to prolong battery life. There are five
modes of operation; Active, Rx , Standby, Interrupt, and
Inactive. In Active mode, all circuit blocks are powered. In Rx
mode, all circuitry is powered down except for those circuit
sections needed to receive a transmission from the base. In
the Standby and Interrupt Modes, all circuitry is powered
down except for the Circuitry needed to provide the clock
output for the microprocessor. In Inactive Mode, all circuitry is
powered down except the MPU interface. Latch memory is
maintained in all modes. Figure 16 shows the control register
bit values for selection of each power saving mode and
Figure 17 shows the circuit blocks which are powered in each
of these operating modes.
Figure 16. Power Saving Mode Selection
Stdby Mode Bit
RxModeBit
"CD Out!
Hardware
Interrupt" Pin
0
0
X
Mode
Active
0
1
X
Rx
1
0
X
Standby
1
1
1 or High
Impedance
Inactive
1
1
0
interrupt
MOTOROLA ANALOG IC DEVICE DATA
NOTE: In Standby and Inactive Modes, "PLL Vrer remains powered but
is not regulated. It will fluctuate with Vee.
Inactive Mode Operation and Hardware Interrupt
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the combo IC into the Inactive mode, which turns off the
MPU Clock Output (see Figure 18), and then disable the
microprocessor. In order to give the MPU adequate time to
power down, the MPU Clock output remains active for a
minimum of one reference counter cycle (about 200 /lS) after
the command is given to switch into the "Inactive" mode. An
external timing circuit should be used to initiate the turn-on
sequence. The "CD Ouf' pin has a dual function. In the Active
and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is
disabled and the "CD Ouf' pin is in a "High" state due to the
external pull-up resistor. In the Inactive mode, the "CD Ouf'
pin is the input for the hardware interrupt function. When the
"CD Ouf' pin is pulled "low" by the external timing circuit, the
combo IC switches from the Inactive to the Interrupt mode
thereby turning on the MPU Clock Output. The MPU can then
resume control of the combo IC. The "CD Out" pin must
remain low until the MPU changes the operating mode from
Interrupt to Standby, Active or Rx modes.
8-169
8
MC13110
Figure 18. Hardware Interrupt Operation
Mode
Inactive
Active/Rx
V
fV
EN
CD OutLaw
CD OuUHardware Interrupt
MPU ClockOut
' \ CD Turns Oti
>
1
Delay after MPU selects Inactive Mode to when CD turns off.
I+-I
-I
MPU "Clk Out" Divider Programming
This pin is a clock output which is derived from the crystal
oscillator (2nd local oscillator). It can be used to drive a
microprocessor and thereby reduce the number of crystals
required. Figure 19 shows the relationship between the
crystal frequency and the clock output for different divider
values. Figure 20 shows the "Clk Out" register bit values.
/
"""""'
-".r
ExternalTimer
Pulls Pin Low
MPU Initiates
Mode Change
/ ' \ Timer Output
Disabled
K
1
1
I+-
"MPU Clock Ouf' remains active for a minimum of one count of reference
counter after "CD OuUHardware Interrupf' pin goes high
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 kQ
resistor is included on-chip in series with the "Clk Out" output
driver. A small capacitor can be connected to the "Clk Out"
line on the PCB to form a single pole low pass filter. This filter
will significantly reduce noise radiated from the "Clk Out" line.
Volume Control Programming
The volume control adjustable gain block can be
programmed in 2.0 dB gain steps from -14 dB to +16 dB. The
power-up default value is 0 dB. (See Figure 21.)
Figure 19. Clock Output Values
Clock Output .Divider
Crystal
Frequency
2
3
4
5
10.24 MHz
5.120 MHz
3.413 MHz
2.560 MHz
2.048 MHz
11.15MHz
5.575 MHz .3.717,MHz
2.788 MHz
2.230 MHz
12.00 MHz
6.000 MHz
3.000 MHz
2.400 MHz
4.000 MHz
I'
1
I
Standby/Rx/Active
/
I
1
Interrupt
MPU Initiates
Inactive Mode
MPU "Clk Out" Radiated Noise on Circuit Board
The clock line running between the MC13110 and the
microprocessor has the potential to radiate noise which can
Figure 20. Clock Output Divider
ClkOut
Bit #1
ClkOut
Bit #0
ClkOut
Divider Value
0
0
2
0
1
.3
1
0
4
1
1
5
Figure 21. Volume Control
Volume Control
Bit #3
Volume Control
Bit #2
0
0
8-170
Volume Control
Bit #1
Volume Control
BitiD
Volume
Control #
Gain/Attenuation
Amount
·0
0
0
0
-14dB
0
0
1
1
-12dB
0
0
1
0
2
-10dB
0
0
1
1
3
-8.0 dB
0
1
0
0
4
-6.0 dB
0
1
0
1
5
-4.0 dB
0
1
1
0
6
-2.0dS
0
1
1
1
7
OdB
1
0
0
0
8
2.0 dB
1
0
0
1
9
4.0 dB
1
0
1
0
10
6.0 dB
1
0
1
1
11
8.0dB
1
1
0
0
12
10dB
1
1
0
1
13
12dB
1
1
1
0
14
14dB
1
1
1
1
15
16dB
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Gain Control Register
The gain control register contains bits which control the Tx
Voltage Gain, Rx Voltage Gain, and Carrier Detect threshold.
Operation of these latch bits are explained in Figures 22, 23
and 24.
Tx and Rx Gain Programming
The T x and Rx audio signal paths each have a
programmable gain block. If a Tx or Rx voltage gain other
than the nominal power-up default is desired, it can be
programmed through the MPU interface. Alternately, these
programmable gain blocks can be used during final test of the
telephone to electronically adjust for gain tolerances in the
telephone system as shown in Figure 23. In this case, the T x
and Rx gain register values should be stored in ROM during
final test so that they can be reloaded each time the combo
IC is powered up.
Figure 22. Gain Control Latch Bits
5-b TxGain Control
5-b Rx Gain Control
Figure 23. Tx and Rx Gain Control
Gain Control
Bit #4
Gain Control
Bit #3
Gain Control
Bit #2
Gain Control
Bit #1
Gain Control
Bit #0
Gain
Control #
Gain/Attenuation
Amount
0
0
0
0
0
0
-15dB
0
0
0
0
1
1
-14dB
0
0
0
1
0
2
-13dB
0
0
0
1
1
3
-12dB
0
0
1
0
0
4
-11 dB
0
0
1
0
1
5
-10dB
0
0
1
1
0
6
-9.0 dB
0
0
1
1
1
7
-8.0 dB
0
1
0
0
0
8
-7.0 dB
0
1
0
0
1
9
-6.0 dB
0
1
0
1
0
10
-5.0 dB
0
1
0
1
1
11
-4.0 dB
0
1
1
0
0
12
-3.0 dB
0
1
1
0
1
13
-2.0 dB
0
1
1
1
0
14
-1.0dB
0
1
1
1
1
15
OdB
1
0
.0
0
0
16
1.0dB
1
0
0
0
1
17
2.0dB
1
0
0
1
0
18
3.0 dB
1
0
0
1
1
19
4.0 dB
1
0
1
0
0
20
5.0 dB
1
0
1
0
1
21
6.0 dB
1
0
1
1
0
22
7.0 dB
1
0
1
1
1
23
8.0 dB
1
1
0
0
0
24
9.0 dB
1
1
0
0
1
25
10dB
1
1
0
1
0
26
11 dB
1
1
0
1
1
27
12 dB
1
1
1
0
0
28
13dB
1
1
1
0
1
29
14dB
1
1
1
1
0
30
15dB
1
1
1
1
1
31
16dB
MOTOROLA ANALOG IC DEVICE DATA
II
&-171
MC13110
Carrier Detect Threshold Programming
The "CD Ouf' pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. The
nominal value and tolerance of the carrier detect threshold is
given in the carrier detect specification section of this
document. If a, different carrier detect threshold value is
desired, it can be programmed through the MPU interface as
shown in Figure 24. Alternately, the carrier detect threshold
can be electronically adjusted during final, test of the
telephone to reduce the tolerance of the carrier detect
threshold., This is done by measuring the threshold and then
by adjusting the threshold through the MPU interface. In this
case, it is necessary to store the carrier detect register value
in ROM so that the CD register can be reloaded each time the
combo IC is powered up.
Figure 24. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
Bit #1
CD
Bit #0
CD
Control #
Carrier Detect
Threshold
0
0
0
0
0
0
-20dB
0
0
0
0
1
1
-19dB
0
0
0
1
0
2
-18dB
0
0
0
1
1
3
-17dB
0
0
1
0
0
4
-16dB
0
0
1
0
1
5
-15dB
0
0
1
1
0
6
-14dB
0
0
1
1
1
7
-13dB
0
1
0
0
0
8
-12dB
0
1
0
0
1
9
-11 dB
0
1
0
1
0
10
-10dB
0
1
0
1
1
11
-9,0 dB
0
1
1
0
0
12
-8,OdB
0
1
1
0
1
13
-7,0 dB
0
1
1
1
0
14
-6,OdB
8-172
0
1
1
1
1
15
-5,OdB
1
0
0
0
0
16
-4,0 dB
1
0
0
0
1
17
-3,OdB
1
0
0
1
0
18
-2,0 dB
1
0
0
1
1
19
-1.0dB
1
0
1
0
0
20
OdB
1
0
1
0
1
21
1.0dB
1
0
1
1
0
22
2.0 dB
1
0
1
1
1
23
3.0 dB
1
1
0
0
0
24
4.0dB
1
1
0
0
1
25
5.0 dB
1
1
0
1
0
26
6.0 dB
1
1
0
1
1
27
7.0 dB
1
1
1
0
0
28
8.0dB
1
1
1
0
1
29
9.0 dB
1
1
1
1
0
30
10dB
1
1
1
1
1
31
11 dB
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Figure 25. Switched Capacitor Filter Clock DividerNoltage Reference Adjust Latch Bits
6-b Switched
Capacitor Filter
Clock Counter latch
4--b Voltage
Reference Adjust
SCF Clock DividerNoltage Reference Adjust Register
This register controls the scrambler bypass mode, the
divider value for the programmable switched capacitor filter
clock divider, and the voltage reference adjust. Operation is
explained in Figures 25 through 30.
The SCF divider should be set to a value which gives a
SCF Clock as close to 165.16 kHz as possible based on the
2nd LO frequency which is chosen (see Figure 12).
Figure 27. SCF Clock and Scrambler Carrier Circuit
Figure 26. Bypass Mode Bit Description
Tx Scrambler
1
Bypass
0
Rx Scrambler
1
Bypass
0
Tx Scrambler Post-Mixer LPF and Mixer
Bypassed
Normal Operation with Tx Scrambler
6-b
Programmable
SCF Clock Counter
Rx Scrambler Post-Mixer LPF and Mixer
Bypassed
Normal Operation Rx Scrambler
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter and
scrambler modulation clock dividers is shown in Figure 27.
There is a fixed divide by 2 after the programmable divider.
The switched capacitor filter clock value is given by the
following equation;
(SCF Clock) = F(2nd LO)/(SCF Divider Value * 2)
The scrambler modulation clock frequency (SMCF) is
proportional to the SCF clock and is given by the following
equation;
Scrambler Modulation Frequency Programming
Four different scrambler modulation frequencies may be
selected by programming the SCF Clock divider as shown in
Figures 28 and 29. Note that all filter corner frequencies will
change proportionately with the SCF Clock and Scrambler
Modulation Frequency. The power-up default SCF Clock
divider value is 31.
SMCF =(SCF Clock Frequency)/40
Figure 28. Scrambler Modulation Frequency Programming for a 10.240 MHz 2nd LO
SCF
Clock
Divider
Total
Divide
Value
SCF
Clock
Freq.
(kHz)
Scrambler
Modulation
Frequency
(Clkl40) (kHz)
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
Rx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
Tx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
29
30
31
32
58
60
62
64
176.55
170.67
165.16
160.00
4.414
4.267
4.129
4.000
267.2
258.3
250.0
242.2
3.902
3.772
3.650
3.536
4.147
4.008
3.879
3.758
3.955
3.823
3.700
3.584
NOTE:
All filter comer frequencies have a tolerance of ±3%.
Figure 29. Scrambler Modulation Frequency Programming for a 11.15 MHz 2nd LO
SCF
Clock
Divider
Total
Divide
Value
SCF
Clock
Freq.
(kHz)
Scrambler
Modulation
Frequency
(Clkl40) (kHz)
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
Rx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
Tx Upper (Scrambler
Bypassed) Corner
Frequency (kHz)
32
33
64
66
68
70
174.22
168.94
163.97
159.29
4.355
4.223
4.099
3.982
263.7
255.7
248.2
241.1
3.850
3.733
3.624
3.520
4.092
3.968
3.851
3.741
3.903
3.785
3.673
3.568
34
35
NOTE:
All Imer comer frequencies have a tolerance of ±3%.
MOTOROLA ANALOG IC DEVICE DATA
8-173
~
_
MC13110
Voltage Reference Adjustment
The internal 1.5 V Bandgap voltage reference provides the
voltage reference for the "B01 Out" and "B02 Ouf' low
battery detect circuits, the "PLL Vret" voltage regulator, the
"VB" reference, and all internal analog ground references.
The initial tolerance of the Bandgap voltage reference is
±6%. The tolerance of the internal reference voltage can be
improved to ±1.5% through MPU serial interface
programming.
During final test of the telephone, the battery detect
threshold is measured. Then, the internal reference voltage
value is adjusted electronically through the MPU serial
interface to achieve the desired accuracy level. The voltage
reference register value should be stored in ROM during final
test so that it can be reloaded each time the MC13110 is
powered up (see Figure 30).
Figure 30. Bandgap Voltage Reference Adjustment
VrefAdj.
Bit #3
VrefAdj.
Bit #2
VrefAdj.
Bit #1
VrefAdj.
Bit #0
VrefAdj.
#
VrefAdj.
Amount
0
0
0
0
0
-9.0%
0
0
0
1
1
-7.8%
0
0
1
0
2
-6.6%
0
0
1
1
3
-5.4%
0
1
0
0
4
-4.2%
0
1
0
1
5
-3.0%
0
1
1
0
6
-1.8%
0
1
1
1
7
-0.6%
1
0
0
0
8
+0.6%
1
0
0
1
9
+1.8%
1
0
1
0
10
+3.0%
1
0
1
1
11
+4.2%
1
1
0
0
12
+5.4%
1
1
0
1
13
+6.6%
1
1
1
0
14
+7.8%
1
1
1
1
15
+9.0%
8-174
Auxiliary Register
The auxiliary register contains a 3-bit 1st LO Capacitor
Selection latch and a 4-bit Test Mode latch. Operation of
these latch bits are explained in Figures 31, 32 and 34.
Figure 31. Auxiliary Register Latch Bits
MSB
4-b Test Mode
LSB
MSB
3-b 1st LO Capacitor
Selection
LSB
First Local Oscillator Programmable Selection (U.S.
Applications)
There is a very large frequency difference between the
minimum and maximum channel frequencies in the 25
Channel U.S. Standard.The sensitivity of the 1st LO may not
be large enough to accommodate this large frequency
variation. Fixed capacitors can be connected across the 1st
LO tank circuit to change the 1st LO sensitivity. Internal
switches and capacitors are provided to enable
microprocessor control over internal fixed capacitor values.
Figures 32 and 33 show the schematic representation of the
1st LO and the tank circuit. Figure 34 shows the latch control
bit values for microprocessor control.
Figure 32. First Local Oscillator Schematic
--------------,
I
I Vcap Ctrl
lstLO
Varactor I 41
I
I
MOTOROLA ANALOG Ie DEVICE DATA
MC13110
Figure 33. First Local Oscillator Simplified Schematic
VCCRF
VCCRF
Output
to Buffer
851lA
851lA
Control
VCCRF
t_---:__
lO Out 0--+-----,---+
1
-=-
1.0
12 k
+- -I >I1 i'1tkl- +-_~t-8.-0-k
-
5.8-8.7
6.0 k
-=-
VCCRF
...
+---..----+--0 LO In
B.Ok
-=-
-=-
-=-
-=Cp 0.8 pF
.-J
T380
.-J
T570
.-J
T320
.-J
T220
CaO.9pF
I
Cb 1.7 pF
I
Cc 6.3 pF
I
Cd 7.8 pF
I
Figure 34. First Local Oscillator Programmable Capacitor Selection for U.S. 25 Channels
1st
LO
Cap.
Bit 2
1st
LO
Cap.
Bit 1
1st
LO
Cap
Bit 0
1st
LO
Cap.
Select
U.S.
Base
Channels
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
Varactor
Value over
0.3 to 2.5 V
Equivalent
Internal
Parallel
Resistance
at 40 MHz
(ka)
Equivalent
Internal
Parallel
Resistance
at 51 MHz
(ka)
External
Capacitor
Value
External
Inductor
Value
U.S.
Handset
Channels
Internal
Capacitor
Value
1-10
-
0.8pF
5.8-8.7pF
>1000
>1000
24pF
0.47 ~H
-
1-10
0.8pF
5.8-8.7pF
>1000
>1000
33pF
0.4711H
1
11-16
2.5pF
5.8-8.7pF
35
21
24pF
0.4711H
0
2
17-25
-
1.7pF
5.8-8.7pF
100
60
24pF
0.4711H
1
3
-
11-16
8.6pF
5.8-8.7pF
6.1
3.8
33pF
0.4711H
4
-
17-25
8.0
5.0
33pF
0.4711H
0
MOTOROLA ANALOG IC DeVICE DATA
7.1 pF
5.8-8.7pF
8-175
MC13110
Figure 35. Digital Test Mode Description
Counter Under Test or
Test Mode Option
"TxVCO"
Input Signal
TM#
TM3
TM2
TM 1
TMO
"Clk Out" Output Expected
0
0
0
0
0
Normal Operation
1
0
0
0
1
Rx Counter, upper 6
Ot02,5 V
2
0
0
1
0
Rx Counter, lower 8
Oto 2,5 V
See Note Below
3
0
0
1
1
Rx Prescaler
Ot02.5 V
Input Frequency/4
Input Frequency/64
-
>200mVpp
Input Frequency/64
4
0
1
0
0
Tx Counter, upper 6
o to 2.5 V
5
0
1
0
1
Tx Counter, lower 8
Ot02.5 V
6
0
1
1
0
Tx Prescaler
7
0
1
1
1
Reference Counter
Ot02.5 V
Input Frequency/Reference Counter Value
8
1
0
0
0
Divide by 4, 25
Ot02.5 V
Input Frequencyl100
9
1
0
0
1
SCCounter
Oto 2.5 V
Input Frequency/SC Counter Value
10
1
0
1
0
Scrambler Modulation Counter
Ot02.5 V
Input Frequency/40
See Note Below
Input Frequency/4
>200mVpp
NOTE: To determine the correct output, look at the lower B-bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6-b~s of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60).
Figure 36. Analog Test Mode Description
II
TM#
TM3
TM2
TM1
TMO
Circuit Blocks Under Test
Input Pin
11
1
0
1
1
Compressor
Cln
Txln
12
1
1
0
0
Tx Scrambler
Txln
TxOut
13
1
1
0
1
ALC Gain
N/A
N/A
14
1
1
1
0
ALC Gain
N/A
N/A
15
1
1
1
1
N/A
N/A
=10 Option
=25 Option
Not Used
Test Modes
Digital and analog test modes can be selected through the
4-bit Test Mode Register. In digital test mode, the "Tx VCO"
input pin is multiplexed to the input of the counter under test
and the output of the counter under test is multiplexed to the
"Clk Out" output pin so that each counter can be individually
tested. Make sure test mode bits are set to "O's" for normal
operation. Digital test mode operation is described in
Figure 35. During normal operation and when testing the
T x Prescaler, the "Tx VCO" input can be a minimum of 200
mVpp at 80 MHz and should be ac-coupled. For other test
modes, input signals should be standard logic levels of 0 to
2.5 V and a maximum frequency of 16 MHz.
The analog test modes enable separate testing of the
Compressor and Tx Scrambler blocks as shown in Figure 36.
Output Pin
Also, ALC Gain options can be selected through analog test
modes.
Power-Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in the
Rx mode with all mutes active. The reference counter is set to
generate a 5.0 kHz reference frequency from a 10.24 MHz
crystal. The switched capacitor filter clock counter is set
properly for operation with a 10.24 MHz crystal. The scrambler
bypass mode control are set for normal operation of
scrambler. The Tx and Rx latch registers are set for USA
Channel Frequency 21 (Channel 6 for previous FCC 10
Channel Band). Figure 37 shows the initial power-up states
for all latch registers.
Figure 37. Latch Register Power-Up Defaults
MSB
LSB
Register
Count
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Tx
9966
-
-
1
0
0
1
1
0
1
1
1
0
1
1
1
0
Rx
7215
-
-
0
1
1
1
0
0
0
0
1
0
1
1
1
1
Ref
2048
-
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Mode
N/A
-
0
X
0
0
1
1
0
1
1
1
0
1
1
1
1
Gain
N/A
-
0
1
1
1
1
0
1
1
1
1
1
0
1
0
0
SC
31
-
-
1
1
0
0
0
1
1
1
1
1
-
-
-
1
N/A
-
0
Aux
-
-
-
-
-
0
0
0
0
0
0
0
8-176
MOTOROLA ANALOG IC DEVICE DATA
MC13110
APPLICATIONS INFORMATION
Evaluation PC Board
The PCB should be double sided with a full ground plane
on one side; any leaded components are inserted on the
ground plane side. This affords shielding and isolation from
the circuit side of the PCB. The other side is the circuit side
which has the interconnect traces and the surface mount
components. In cases where cost allows, it may be benificial
to use multi layer boards.
The placement of certain components specified in the
application circuits is very critical. These components should
be placed first and the other less critical components are
fitted in last. In general, al/ RF paths should be kept as short
as possible, ground pins should be grounded at the pins and
VCC pins should have adequate decoupling to ground at the
pins. In mixed mode systems where digital and RF/Analog
circuitry are present, the VEE and VCC busses are isolated ac
-wise from each other.
Component Selection
The evaluation PC board is designed to accommodate
specific components, while in some cases it is versatile
enough to use components from various manufacturers and
coil types. The application circuit schematics specify
particular components that were used to achieve the results
shown in the typical curves and tables, but alternate
components should give similar results.
The MC13110 IC is capable of matching the sensitivity,
IMD, adjacent channel rejection, and other performance
criteria of a multi-chip analog cordless telephone system.
For the most part, the same external components are used
as in the multi-chip solution. In the following discussion,
various parts of the system are analyzed for best peformance
and cost tradeoffs. Specific recommendations are made
where certain components or circuit designs offer superior
performance. The system analyzed is the USA "CT-1"
cordless phone.
Input Matching/Sensitivity
The sensitivity of the IC is typically 0.5611Vrms matched
with no preamp. To achieve suitable system performance, a
preamp and passive duplexer must be used. In production
final test, each section of the IC is separately tested to
guarantee its system performance in the specific
application. The preamp and duplexer yields typically -114
dBm 12 dB SINAD sensitivity performance under full duplex
operation.
The duplexer is important to achieve full duplex operation
without significant "de-sensing" of the receiver by the
transmitter. The combination of the duplexer and preamp
circuit have to attenuate the transmitter power to the receiver
by over 60 dB to be effective. They do this while improving
the receiver system noise figure and without giving up too
much IMD intermodulation performance.
The duplexer may be a single piece unit offered by
Shimida and Sansui products (designed for 10 channel CT-1
cordless phone) or a two piece solution offered by Toko
(designed for 25 channel operation). The duplexer frequency
response at the receiver port has a notch at the transmitter
MOTOROLA ANALOG IC DEVICE DATA
frequency band of about 35 to 40 dB with a 2.0 to 3.0 dB
insertion loss at the receiver frequency band.
The preamp circuit utilizes a tuned transformer at the
output side of the amplifier; this transformer is designed to
bandpass filter the receiver input frequency while rejecting
the transmitter frequency. The tuned preamp also improves
the noise performance by reducing the bandwidth of the pass
band and reducing the second stage contribution of the 1st
mixer. The preamp is biased at about 1.0 mA and 3.0 Vdc
which yields suitable noise figure and gain.
Mixers
The 1st and 2nd mixers are similar in design. Both are
double balanced to suppress the LO and the input
frequencies to give only the sum and difference frequencies
out. Typically the LO is suppressed about 40 to 60 dB. The
1st mixer may be driven either differentially or single ended.
The gain of the 1st mixer has a 3.0 dB corner at 20 MHz and
is used at a 10.7 MHz IF. It has an output impedance of
330 n and matches to a typical 10.7 MHz ceramic filter with
a source and load impedance of 330 n. A series resistor may
be used to raise the impedance for use with crystal filters
which typically have an input impedance much greater than
330 n. The 2nd mixer input impedance is typically 3.0 kn; it
requires an external 360 n parallel resistor for use with a
standard 330 n 10.7 MHz ceramic filter. The second mixer
output impedance is 1.5 kn making it suitable to match
455 kHz ceramic filters.
The following table is a list of typical input impedances
over frequency for the 1st Mixer. Rp and Cp are represented
in parallel form.
Frequency (MHz)
Rp(Q)
20
977.7
2.44
25
944.3
2.60
30
948.8
2.65
35
928
2.55
2.51
Cp (pF)
40
900
45
873.4
2.65
50
859.3
2.72
55
821
2.72
60
795
2.74
First Local Oscillator
The 1st LO is a multi-vibrator oscillator that takes an extemal
capacitance and inductance. It is voltage controlled to an
intemal varactor from an external loop filter and an on-board
phase-lock loop (PLL). The schematic in Figure 33 shows all
the basic parasitic elements of the internal circuitry. The 1st LO
internal component values have a tolerance of 15%. A typical
dc bias level on the LO Input and LO Output is 0.47 Vdc. The
curve in Figure 38 is the varactor control voltage range as it
relates to capacitance. It represents the expected capacitance
for a given control voltage of the MC13110.
II_
MC13110
Figure 38. First local Oscillator Varacter
versus Control Voltage
12
11
CL
8 10
w
\
(,)
z
~ 9.0
(,)
c::
15
8.0
\
\.
~
~ 7.0
6.0
5.0
o
0.5
.........
.........
.... "'--...
1.0
1.5
2.0
VCV, CONTROL VOLTAGE (V)
r-2.5
3.0
Second local Oscillator
The 2nd lO is a CMOS oscillator similar to that used in the
MC145162. The 2nd LO is also used as the PLL reference
oscillator. It is designed to utilize an external parallel resonant
crystal.
'
II
PllDesign
The 1st LO level is important, as well as the choice of the
crystal for the PLL cJock reference and 2nd LO. A
fundamental, parallel resonant crystal specified with 7.0 to
12 pF load calibration capacitance is recommended. With
load calibration capacitance too high, the-crystal locks up
very slowly. If the LO power is less than -10 dBm, a
pull-down resistor at the 1st LO emitter (Pin 41) will
increase its drive level. The LO level is primarily a function
of the Colpitts capacitive voltage divider formed by the
capacitors between the base to emitter and the emiller to
ground.
The VCO gain factor expressed in MHzIV is indeed critical
to the phase noise performance. If this curve is too steep or
too sensitive to changes in control voltage, it may degrade
the phase noise performance. The external VCO circuit
design needs to consider the typical swing of the control
voltage and the corresponding linearity of the transfer
function, ~fosd!Ncontrol. In general, the higher the Q of the
VCO circuit inductor, the beller phase noise performance.
Adjacent channel rejection and isolation between the 1st
and 2nd mixers may be adversely affected due to layout
problems and difficulty in getting close to the package pins
with the grounds and decoupling capacitors on the RF VCC.
These system parameters must be evaluated for sensitivity
to layout and external component placement.
Intermodulation and adjacent channel performance
problems may also result from spurs around the 1st LO'which
may be caused by harmonics from the switched capacitor
clock driver and too low 1st LO drive level. The clock driver
8-178
operates at a frequency which is f(2nd LO)/(2 • (SCF
Divider». The harmonics are n • (f(2nd LO», where n can be
any positive integer. The current spikes of the SCF on the
supply lines cause the disturbance of the 1st LO. This may be
verified by observing the spurs on a spectrum analyzer while
changing the clock divider value. The spur frequencies will
change when the divider value is changed. The spurious
sideband problem may be avoided by changing the clock
divider value via software for each channel where it is a
problem. Certain channels are worse than others.
The PLL alignment procedure for the application circuit is
detailed in Appendix C. Refer to the MC145162 data sheet
for PlL design example.
limiting IF Amplifiers
The limiting IF amplifier typically has about 110 dB of gain;
the frequency response starts rolling off at 1.0 MHz.
Decoupling capacitors should be placed close to the
decoupling Pins 31 and 32 to ensure low noise and stable
operation. The IF input impedance is 1.5 k,Q for a suitable
match to 455 kHz ceramic filters.
RSSIICarrier Dtltect
The Received Signal Strength Indicator (RSSI) indicates
the strength of the IF level and the output is proportional to
the logarithm of the IF input signal magnitude. The RSSI
dynamic range is typically 80 dB. Connect 0.01 I1F to GND
from "RSSI" output pin to form the carrier detect filter. A
resistor needed to convert the RSSI current to voltage is
included in the internal circuit. An internal temperature
compensated reference current also improves the RSSI
accuracy over temperature.
"CD Out" is an open collector output; thus, an external
100"k,Q pull-up resistor to VCC is recommended. The carrier
detect threshold is programmable through the MPU
interface.
Quadrature Detector
The quadrature detector is coupled to the IF with an
external capaCitor between Pins 27 and 28; thus, the
recovered signal level output is increased for a given
bandwidth by increasing the capacitor. The external
quadrature component may be either a LCR resonant circuit,
which may be adjustable, or a ceramic resonator which is
usually fixed tuned.
The bandwidth performance of the detector is controlled
by the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
(1) RT=QXL
wherE~
AT is the equivalent shunt resistance across the
LC
Tank. XL is the reactance of the quadrature inductor at the IF
frequency (XL = 2ItfL).
MOTOROLA ANALOG IC DEVICE DATA
MC13110
Specific 455 kHz quadrature LC components are
manufactured by Toko in various 5 mm, 7 mm and 10 mm
shielded cans in surface mount or leaded packages.
Recommended components such as, the 7 mm Toko, is used
in the application circuit. When minaturization is a key
constraint, a surface mount inductor and capacitor may be
chosen to form a resonant LC tank with the PCB and parasitic
device capacitance. The 455 kHz IF center frequency is
calculated by
(2) fc = [21t (LC p)1/2]- 1
where L is the parallel tank inductor. Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455 kHz
and a specific loaded Q. The loaded Q of the quadrature
detector is chosen somewhat less than the Q of the IF
bandpass. For an IF frequency of 455 kHz and an IF bandpass
of 20 kHz, the IF bandpass Q is approximately 23; the loaded
Q of the quadrature tank is chosen at 15.
Example:
Let the total extemal C = 180 pF. Note: the capacitance may
be split between a 150 pF chip capaCitor and a 5.0 to 25 pF
variable capacitor; this allows for tuning to compensate for
component tolerance. Since the extemal capacitance is much
greater than the internal device and PCB parasitic
capacitance, the parasitic capacitance may be neglected.
MOTOROLA ANALOG IC DEVICE DATA
Rewrite equation (2) and solve for L:
L = (0.159)2/(C fc 2)
L = 678 IlH ; Thus, a standard value is chosen:
L = 680 IlH (surface mount inductor)
The value of the total damping resistor to obtain the
required loaded Q of 15 can be calculated from equation (1):
RT = Q(21tfL)
RT = 15 (21t)(0.455)(680) = 29.5 kg
The internal resistance, Rint at the quadrature tank Pin 27
is approximately 100 kg and is considered in determining
the external resistance, Rex! which is calculated from
Rext = ((RT)(Rint))/(Rint - AT)
Rext = 41.8 kg; Thus, choose the standard value:
Rext= 39 kg
A ceramic discriminator is' recommended for the
quadrature circuit in applications where fixed tuning is
desired. The ceramic discriminator and a 22 k resistor are
placed from Pin 27 to VCC. A 10 pF capacitor is placed from
Pin 28 to 27 to properly drive the discriminator.
MuRata Erie has designed a resonator that is compatible
with the IC. For US applications the part number is
CDBM455C48. For Europe the part number is
CDBM450C48. Contact Motorola Analog Marketing for
performance data using muRata's parts.
8-179
II
!
~
Figure 39a. Baseset RF Applications Circuit
.
TP25
R3
220
Vcc-RF
~
P35
VCC-RF ---'VI!'v--rl1
C2
0.1
~R~n------------------~
)10
"'0
"'0
R33
tOJ~
,",XI
~I
",,'
~
M
,
'"'U
\JI
..
"
~
..
,;JOt
..
~
..
'""
"'I
~
,~,o
' -__.....-::::-____...;4,1 !.OJ ru ~
SP1
TP4
C6
15G-{l()()n~7"F
r.
m
CB7
~~
'f
•
Vc:c-A ~vcc
~~1
CBB
0.15
r-------------------~N_~~~,~~
3~~
R2B
-= Gnd
ICI
R29
U.04I
~I
RSO BBOk
?7k
~o.
MC13110FB
P
, "uT
vVI'
TP19
==
o
a
o
1.0k
C
m
(')
m
C
~
:J>
(')
~
Gnd
Z
(I)
(')
Low Batt
~
Data
g
:s
!:
:0
(')
C
Car-De1ect
ClkOut
Clk
~
(5
Mlc11
( Mic
Batt Dead
RxData
,TP13
:D
)0
I
(5
-=Gnd
Vcc-A~
><
)10
)10
"'0
"'0
43
Speaker
~
+._
Z
C
C90
~10
EN
:s:
0....
....
....
Q
Co)
Figure 39a. Baseset RF Applications Circuit (continued)
3:
a
:u
o
r
i
~
gr-
V+
(')
V-
C
m
S
VTx
,.------"
+~
0.1 Y 2 . 2 11F
L6
56 I1H
VRx
C54 +
W~
~
~
00
BaHl
-=
Gnd
C53
~
VCC-RF
~
~
R94
12k
-= Gnd
~
12kL
T PWR-ON
_x___
'------RxPWR-ON
Gnd
V -A
CC
C581J.
IOI1FJ
~
CONI
~
C59
180
)1
TxAudio
~
T
l
IE-
~L4
2.0
R53
$ 68k
MODINI
C37
COO
O.II1F
-------1
.r---?
-= 6800
2
3
""'""~ "'" 15
~.::- Q
Aux
26
VBaH
25
TxData
24
g
a:.
C45
,,13
10
R51
4 .....
512
~~~
6
11
"'" - ~
Il ....
Il
R46
220 k
R49100
Gnd
23
22
W
C50
Vee
~
C40
~
10
R41
27 k
I":"
110
0.022
110
~
~I~
-=-
l"':"
C42
=e----'VVIr-- TxRF-ln
R42
91 k
See Note 1
!
NOTE 1: C42= X42= 51
a
II
R43
21
20
BaH Dead
19
Low BaH
Aux
Aux
Aux
TxPWR-ON
Gnd
VB
RSSI
Aux
R45
75k
8~
TxData~...L.
VTx
Aux
RxPWR-ON
Gnd
RxData
14
110k
7~Emtter
~
27
Gnd
R54
lOOk
28
Aux
10
11
12
13
14
18
17
16
15
s::
0
Enable
...
Clk
0
Data
ClkOut
Carrier Detect
Aux
Aux
Aux
~
Co)
~
II
!
~
Figure 39b. Handset RF Applications Circuit
TP25
R3
220
VCC-RF-"Wv-.,..-+
R21
.100k
•..
:!:P?:J Gi_u~,- - -
=.
P35
VCC-RF
47
TP26
C2
0.1
ThRF~n----------------~-
R33
C87
~h
Mllllnl
R26
LOlln
CBB
0.15
L-__~~______~41 LOl~
SP1
TP4
C6
151l-3OO0~71'F
+
Speaker
-=-Gnd
TP5
•
R8
1-
C10
0.1
"
R5
42
18k
43""'"
------."..,~~~·-IEO"
i:
R28
R29
Co)
U.U41
~,_
IC1
MC13110FB
Mic
-=-Gnd
VCC-A~
Batt Dead
!i:
a
~
§;
»
z
»
6G)
(;
c
~m
c
~
)Ii
....
....
0
44 ""'C9
"'"
T
45
16
Rx Dala
Low Batt
·TP13
1.0k
I
~TP15
i:~~
TxVT
_C7
~10
Gnd
Car-Oetec1
ClkDu1
Clk
Data
lC90
~10
EN
--
d
Figure 3gb. Handset RF Applications Circuit (continued)
!i:
a
:II
o
~
tl
03
)00
z
)00
Battt
6
V+
c;
V-
Ii)
c561
Vee
O.
C57
t y 2.2~F
VTx
L6
56I1H
VRx
-:
Gnd
VCC-RF
c
~
o
c
Gnd
-: Gnd
m
TxPWR-ON
RxPWR-ON
~
):0
C56:t
tO I1F,J
Vcc-A
CaNt
Aux
Aux
Gnd
Aux
25
Tx Data
24
Gnd
Gnd
TxAudia
TxPWR-ON
VBatt
RxPWR-ON
Gnd
23
VB
Data
Gnd
R54
tOOk
~ R53
MODINt
66k
RSSI
Enable
TxVCO
Low Batt
R5t
Aux
t10k
R37
22k
Aux
Aux
TxData~
-'-
tj~:1
27k
!g:
t3630
"01C42
'WIr--l RF I
Se.Natet x -n
NOTE1:C42=X42=5Hl
II
R43
CAl
.....
.....
0
COO
~t
s::
0
.....
Aux
MG13110
APPENDIX B - MC13110 APPLICATION BOARD BILL OF MATERIAL (USA)
Reference
Xl
Description
10.24 Crystal (Load Cap <1-2 pF)
Value
Package
Part Number
Vendor
-
HC49US
AAL 1OM240000FLEl OA
Standard Crystal
-
Sot23
MMBV2109LTl
Motorola
DUPl
Duplexer (25 Channel)
Baseset
Hybrid
DPX1035756-153B
Sumida
DUPl
Duplexer (25 Channel)
Handset
Hybrid
DPX1035756-154B
Sumida
SFE10.7MS2-A
muRata
VR2
Diode
FLl
10.7 MHz Filter (Red Dot)
-
FL2
455 kHz Filter
-
-
CFU455E2
muRata
ICl
Universal Cordless Telephone IC
-
OFP
MC13110FB
Motorola
IC2
FM Transmitter IC
-
SO-16
MC2833D
Motorola
L3
Inductor
0.47J.lH
Can
292SNS-T1370Z
Toko
L4/L5
Inductor
0.22J.lH
Can
292SN8-T1368Z
Toko
Tl/T3
Transformer
-
Can
600GCS-8519N
Toko
T2
Ouadrature Coil
-
Can
7MCS-8128Z
Toko
01
Transistor
-
T0-92
MPSH10
Motorola
03
Transistor
-
T0-92
2N3906
Motorola
04
Transistor
-
TO-92
2N3906
Motorola
NOTE:
Components for the Handset and Baseset are the same, except where noted on the Bill of Material and Schematic.
APPENDIX C - MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME
This measurement definition is based on EIAICCITT
recommendations.
Compressor Attack Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.5X of the final steady state
value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.75X of the final steady
state value.
Expandor Attack
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.57X of the final steady
state value.
Expandor Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.5X of the final steady
state value.
f
6.QdB
i
Input ______~
12dB
~
OmV------+-----------+----------Input _ _ _--'
Attack Time
~
OmV------4------------+-----------AtlackTime
Decay Time
Output
Output ______.J
--~
OmV-------------------------------OmV-----------------------------8-184
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13111
Universal Cordless Telephone
Subsystem IC
The MC13111 integrates several of the functions required for a cordless
telephone into a single integrated circuit. This significantly reduces
component count, board space requirements, external adjustments, and
lowers overall costs. It is designed for use in both the handset and the base.
UNIVERSAL CT-1
SUBSYSTEM
INTEGRATED CIRCUIT
• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna In to Audio Out
80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic Discriminator
• Compander
- Expandor Includes Mute, Digital Volume Control, Speaker Driver,
3.5 kHz Low Pass Filter, and Programmable Gain Block
- Compressor Includes Mute, 3.5 kHz Low Pass Filter, Limiter, and
Programmable Gain Block
• Dual Universal Programmable PLL
SEMICONDUCTOR
TECHNICAL DATA
-
Supports New 25 Channel U.S. Standard with No Extemal Switches
Universal Design for Domestic and Foreign CT-1 Standards
Digitally Controlled Via a Serial Interface Port
Receive Side Includes 1st LO VCO, Phase Detector, and 14-Bit
Programmable Counter and 2nd LO with 12-Bit Counter
- Transmit Section Contains Phase Detector and 14-Bit Counter
- MPU Clock Outputs Eliminates Need for MPU Crystal
• Supply Voltage Monitor
- Provides Two Levels of Monitoring with Separate Outputs
- Separate, Adjustable Trip Points
• Programmable Corner Frequency Selection
52
1
II
FB SUFFIX
PLASTIC QFP PACKAGE
CASE 848B
• MC13111 is Pin-for-Pin Compatible with MC13110
ORDERING INFORMATION
• 2.7 to 5.5 V Operation with One-Third the Power Consumption of
Competing Devices
• AN1575: Refer to this Application Note for a List of the "Worldwide
Cordless Telephone Frequencies" (List can also be found in Chapter 8
Addendum of DL128 Data Book)
Device
Tested Operating
Temperature Range
Package
MC13111FB
TA =- 40° to +85°C
QFP-52
Simplified Application
Rx In -+-----;~
Rx PO Out
Rx PO In >-+----~
Rx
Out
Carrier +--+-_ _-<
Detect
TxOut+-t---~==~
Tx VCO +--+-----1
L ___~==~===~
__________
__J
Low
I----+--f---;~ Battery
~===~
Indicator
This device contains 8,262 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
8-185
II
VCC
Figure 1. Production Test Circuit
!
~
RFln)
I1
22.1 k
0.01
49.;
0.01
f-------II~
1000 -=-
~~
I:"
(OAln
3:
....
W
....
....
....
(')
!i:
a
::u
o
VCCA~
~
I~~ ~".
~
~
z
.~
~ BOI
"
g
Data
Oul
Out
(';
c
~m
22.1 k
•
c
!;
)Ii
MPU Clock Output
NOTE: This schematic is only a representation of the actual production test circuit.
• Carrier
Detect Out
MC13111
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Characteristic
VCC
-0.5 to +6.0
Vdc
Junction Temperature
TJ
-65 to +150
°c
NOTES: 1. Devices should not be operated at these Iimtls. The "Recommended Operating Condtlions"
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Min
"",p
Max
Unit
VCC
2.7
3.6
5.5
Vdc
TA
-40
-
85
°c
V
V
Supply Voltagfl
Operating Ambient Temperature
VIL
-
-
0.3
Input Voltage High (Data, Clk, EN)
VIH
2.5
-
-
Output Current (Rx PO, T x PO)
High
Low
IOH
IOL
-
-
-0.7
Input Voltage Low (Data, Clk, EN)
NOTE:
0.7
mA
-
All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25°C, unless otherwise specified;
Test Circuit Figure 1.)
Symbol
Min
"",p
Max
Unit
ACT ICC
ACT ICC
RxlCC
STDICC
INACTICC
-
8.1
8.6
4.3
270
35
12
5.3
500
80
mA
mA
mA
/lA
/lA
Characteristic
Static Current
Active Mode (2.7 V)
Active Mode
Receive Mode
Standby Mode
Inactive Mode
-
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specHied;
Test Circuit Figure 1.)
Characteristic
Condition
PLL VOLTAGE REGULATOR
-
PLLVref
Vo
IL=OmA,
VCC = 3.6 to 5.5 V
VCC Audio
PLLVref
VReg
Line
VCC = 3.6 V, IL = 1.0 mA
VCC Audio
PLLVref
VRea
Loa
-
Regulated Output Level
IL=O mA
Line Regulation
Load Regulation
2.4
2.5
2.6
V
-
-0.6
20
mV
-
-1.1
20
mV
f2ext
-
12
-
MHz
L021n
L020ut
f2ext
-
12
-
MHz
Tx VCO
ftxmax
-
80
-
MHz
PLL LOOP CHARACTERISTICS
2nd LO Frequency
(No Crystal)
-
L021n
2nd LO Frequency
(With Crystal)
-
-
T x VCO (Input Frequency)
Yin = 200 mVpp
MOTOROLA ANALOG IC DEVICE DATA
-
8-187
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic
Condition
PLL PHASE DETECTOR
RxPD
TxPD
VOL
-
-
(PLL
Vref) *.2
V
RxPD
TxPD
VOL
(PLL
Vref) *.8
-
-
V
-
RxPD
TxPD
10Z
-50
-
50
nA
-
-
RxPD
TxPD
Cout
-
8.0
-
pF
CLoad= 50 pF
-
RxPD
TxPD
ClkOut
tr,tf
-
250
-
ns
Output Voltage Low
IIL=0.7mA
-
Output Voltage High
IIH = -{J.7 mA
-
3-State Leakage Current
V= 1.2V
Output Capacitance
Output Rise and Fall Time
MICROPROCESSOR SERIAL INTERFACE
Input Current Low
Yin = 0.3 V
Standby Mode
-
Data,
Clk,EN
IlL
-5.0
0.3
-
~
Input Current High
Yin = 3.3 V
Standby Mode
-
Data,
Clk, EN
IIH
-
1.5
5.0
~
Hysteresis Voltage
-
-
Data,
Clk, EN
Vhys
-
1.0
-
V
Maximum Clock Frequency
-
Data,
EN,Clk
-
-
-
2.0
-
MHz
Input Capacitance
-
Data,
Clk, EN
-
Cin
-
8.0
-
pF
EN to Clk Setup TIme
-
-
EN,Clk
tsuEC
-
200
-
ns
Data to Clk Setup TIme
-
-
Data, Clk
tsuDC
-
100
-
ns
Hold Time
-
-
Data,Clk
th
-
90
-
ns
Recovery Time
-
-
EN, Clk
trec
-
90
-
ns
Input Pulse Width
-
-
EN,Clk
tw
-
100
-
ns
Input Rise and Fall TIme
-
-
Data,
'Clk, EN
tr,tf
-
9.0
-
lJS
-
-
tpuMPU
-
100
-
Ils
-
2.8
-98
-
-
IlVrms
dBm
1.0
-107
-
IlVrms
dBm
-
.56
-112
-
IlVrms
dBm
MPU Interface Power-Up
Delay
90% of PLL Vref to Data,
Clk, EN
FM RECEIVER (fRF = 46 77 MHz [USA Ch 21] fdev = ±3 0 kHz fmod = 10kHz)
50 n Termination
Mix11n1/2
DetOut
VSIN
Single-Ended, Matched Input
Generator Referred
Mix11n1/2
DetOut
VSIN
Differential, Matched Input
Generator Referred
Mix11n1/2
1st Mixer Voltage
Conversion Gain
Yin = 1.0 mVrms, with CF1
Filter as Load
Mix1 In1/2
Mix10ut
MXgain1
-
12
-
dB
2nd Mixer Voltage
Conversion Gain
Yin = 3.0 mVrms, with CF2
Filter as Load
Mix21n
Mix20ut
MXgain2
-
20
-
dB
1st and 2nd Mixer Vo~age
Gain Total
Yin = 1.0 mVrms, with CF1
and CF2 Load
Mix11n1/2
Mix20ut
MXgainT
24
28
-
dB
1st Mixer Input Impedance
Single-Ended Input
-
Mix1 In1/2
RP1
CP1
-
875
2.7
-
pF
3.0
-
kn
Sensitivity (Input for 12 dB
SINAD)
2nd Mixer Input Impedance
8-188
fin = 10.7 MHz
-
-
DetOut
Mix21n
VSIN
Zin2
-
-
n
MOTOROLA ANALOG IC DEVICE DATA
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC
Test Circuit Figure 1.)
Condition
Characteristic
FM RECEIVER (fRF
=3.6 V, VB =1.5 V, TA =25°C, Active or Rx Mode, unless otherwise specified;
=46 77 MHz [USA Ch 21)
fdev =+
fmod
- 30kHz
.
=10kHz)
1st Mixer Output Impedance
-
-
Mixl0ut
Zoutl
-
330
-
0
2nd Mixer Output
Impedance
-
-
Mix20ut
Zout2
-
1.5
-
kO
Lim In
DetOut
IF Sens
-
71
100
j.1Vrms
=455 kHz
IF -3.0 dB Limiting
Sensitivity
~n
Total Harmonic Distortion
With RC =15 kll.0 nF Filter
at DetOut
Mixllnl
DetOut
THD
-
1.3
2.0
%
Recovered Audio
Yin =3.16 mVrms with
RC =15 kll000 pF Filter
at Det Out
Mixllnl
DetOut
AFO
80
105
150
mVrms
Lim In
DetOut
BW
-
20
-
kHz
Signal to Noise Ratio
Yin =3.16 mVrms,
RC =15 kll000 pF
-
Mixllnl
DetOut
SN
-
49
-
dB
AM Rejection Ratio
Yin =3.16 mVrms,
30% AM, @ 1.0 kHz,
RC =15 kll000 pF
Mixllnl
DetOut
AMR
30
47
-
dB
Mixl1nl/2
Mixl0ut
Vo
1.0dB
Mixl
-
15
-
mVrms
Mix21n
Mix20ut
Vo
1.0dB
Mix2
-
14
-
mVrms
Mixllnl
Mixl0ut
TOlmixl
-
56
-
mVrms
Mix21n
Mix20ut
TOlmix2
-
53
-
mVrms
-
-
DetOut
Zo
-
870
-
0
-
Mixlln
RSSI
RSSI
-
80
-
dB
Mlxlln
CD Out
VT
-
33
-
j.1Vrms
Mixlln
CD Out
Hys
-
3.6
7.0
dB
Mixlln
CD Out
VOH
VCC0.1
3.6
-
V
Mixlln
CD Out
VOL
-
0.02
0.4
V
Demodulator Bandwidth
-
1st Mixer, 1.0 dB Voltage
Compression (Input Pin
Referred)
2nd Mixer, 1.0 dB Voltage
Compression (Input Pin
Referred)
500 Input
1st Mixer 3rd Order
Intercept (Input Pin
Referred)
Yin
=3.98 mVrms
2nd Mixer 3rd Order
Intercept (Input Pin
Referred)
Yin
=3.98 mVrms, 50 0
Detector Output Impedance
Input
RSSIICARRIER DETECT (RL = 100 kO)
RSSI Output Current
Dynamic Range
Carrier Sense Threshold
CD Threshold Adjust
(10100)
Hysteresis
=
=0 Vrms, CD =(10100)
Output High Voltage
Yin
Output Low Voltage
Yin =-80 dBV, CD =(10100)
MOTOROLA ANALOG IC DEVICE DATA
8-189
II
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C"Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
.,
Characteristic
Condition
RSSIfCARRIER DETECT (RL = 100 kQ)
Carrier Sense Threshold
Adjustment Range
Carrier Sense Threshold Number of Steps
-
-
VTlow
range
-20
-
-
-
-
VThi
range
-
-
11
Programmable through MPU
Interface
-
-
VTn
-
32
-
-
Programmable through MPU
Interface
dB
DATA AMP COMPARATOR
Hysteresis
-
DAln
DAOut
Hys
30
40
50
mV
Threshold Voltage
-
DAln
DAOut
VT
2.7
VCC0.7
-
V
Input Impedance
-
-
DAln
ZI
-
11
-
kQ
DAOut
Zo
-
100
Vin = VCC -1.0 V,
IOH=OmA
DAln
DAOut
VOH
VCC0.1
3.6
-
kQ
Output High Voltage
Output Low Voltage
Vin = VCC - 0.4 V,
IOL=OmA
DAln
DAOut
VOL
-.
0.04
0.4
V
Output Impedance
V
Rx AUDIO PATH (fin = 10kHz)
II
Absolute Gain
Vin=-20dBV
Eln
EOut
G
-3.0
0
3.0
dB
Gain Tracking
Vin=-30dBV
Vin =-40 dBV
Eln
EOut
Gt
-21
-42
-20
-40
-19
-38
dB
Total Harmonic Distortion
Vin =-20dBV
Maximum Input Voltage
Maximum Output Voltage
Input Impedance
Eln
EOut
THD
-
0.5
1.0
%
-
Rx Audio In
-
-
-
-11.5
dBV
Increase input voltage until
output voltage THD = 5.0%,
then measure output voltage.
RL = 7.5 k/1.0 IlF
Eln
EOut
VOmax
-
0
-
Rx Audio In
E In
-
Zin
-
600
7.5
-
-
kQ
-
-
dBV
Attack Time
Ecap = 0.5 IlF, Rfilt = 40 k
(See Appendix B)
E In
EOut
ta
-
3.0
-
ms
Release Time
Ecap = 0.5 IlF, Rfilt = 40 k
(See Appendix B)
E In
EOut
tr
-
13.5
-
ms
Compressor to Expandor
Crosstalk
Vin = -10 dBV,
VIE In) = AC Gnd
Cln
EOut
CT
-
-90
-70
dB
Rx Data Muting (Ll Gain)
Vin = -20 dBV,
Rx Gain Adj = (01111)
RxAudio In
E Out
Me
-
-a3
-60
dB
Rx High Frequency Corner
(Note 1)
RxPath,
V Rx Audio In = -20 dBV
Rx Audio In
ScrOut
Rxfch
-
3.879
-
kHz
SPEAKER AMPISP MUTE
Maximum Output Swing
Speaker Amp Muting
Vin=-20dBV
Tx AUDIO PATH (fin = 10kHz, Tx Gain Adj = (01111) fin = 10kHz)
Absolute Gain
Vin = -10 dBV, ALC,
Lim Disabled
Txln
Tx Out
G
-4.0
0
4.0
dB
Gain Tracking
Vln=-30dBV
Vin=-40dBV
Txln
Tx Out
Gt
-11
-17
-10
-20
-9.0
-13
dB
Total Harmonic Distortion
Vln=-10dBV
Tx In
TxOut
THD
-
0.6
1.1
%
8-190
,MOTOROLA ANALOG IC DEVICE DATA
MC13111
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specilied;
Test Circuit Figure 1.)
Characteristic
Condition
T x AUDIO PATH (lin = 1.0 kHz, Tx Gain Adj = (01111), lin = 1.0 kHz)
Maximum Output Voltage
Increase input voltage until
output voltage THD = 5.0%,
then measure output voltage.
RL = 7.5 kl1.0 IlF
Cln
Tx Out
VOmax
-
-
-5.0
-
dBV
Cln
Tx Out
Zin
-
10
-
kn
Attack Time
Ccap = 0.5 IlF, Rlilt = 40 k
(See Appendix B)
Cln
Tx Out
ta
-
3.0
-
ms
Release Time
Ccap = 0.5 IlF, Rlilt = 40 k
(See Appendix B)
Cln
Tx Out
tr
-
13.5
-
ms
Expandor to Compressor
Crosstalk
Vin = -20 dBV, Speaker Amp
No Load, VIC In) = AC Gnd
Eln
Tx Out
CT
-
-60
-40
dB
TxMuting
Vin-10dBV
Tx In
Tx Out
Mc
-
-90
-60
dB
ALC Output Level
Vin = -10 dBV
Vin = -2.5 dBV
Limiter and Mutes disabled
Tx In
Tx Out
ALCout
-15
-13
-11
-10
-8.0
-6.0
dBV
Limiter Output Level
Vin = -2.5 dBV,
ALC disabled
Txln
Tx Out
Vlim
-10
-7.0
-
dBV
Tx High Frequency Comer
(Note 1)
Tx Path, V Tx In = -10 dBV,
Mic Amp = Unity Gain
Tx In
TxOut
Txlch
-
3.7
-
kHz
Input Impedance
MIC AMP (lin = 1.0 kHz, External resistors set to gain 01 1)
Open Loop Gain
-
Txln
Amp Out
AVOL
-
100,000
-
VN
Gain Bandwidth
-
Tx In
Amp Out
GBW
-
100
-
kHz
RL=10kn
Tx In
Amp Out
VOmax
-
2.8
-
Vpp
Average Threshold
Voltage Belore Electronic
Adjustment
VCC = 3.6 V, Vrel_Adj =
(0111). Take average 01 rising
and lalling threshold
Relj
Ref2
BD10ut
BD20ut
VTi
1.36
1.5
1.64
V
Average Threshold
Voltage After Electronic
Adjustment
VCC = 3.6 V, Vref_Adj =
(adjusted value). Take
average of rising and falling
threshold
Ref1
Ref2
BD10ut
BD20ut
VTf
1.475
1.5
1.525
V
-
Rel1
Rel2
BD10ut
BD20ut
Hys
-
4.0
-
mV
-
Ref1
Ref2
lin
-50
-
50
nA
Maximum Output Swing
LOW BATTERY DETECT
Hysteresis
Input Current
Vin = 1.0 to 2.0 V
Output High Voltage
Vin=2.0V,
RL = 3.9 kQ to VCC
Relj
Ref2
BD10ut
BD20ut
VOH
VCC0.1
3.6
-
V
Output Low Voltage
Vin= 1.0V,
RL = 3.9 kQ to VCC
Ref1
Ref2
BD10ut
BD20ut
VOL
-
0.1
0.4
V
NOTE: 1. The filter specification is based on a 10.24 MHz 2nd LO, and a switched-capac~or (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
andlor SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MOTOROLA ANALOG IC DEVICE DATA
8-191
II
MC13111
PIN FUNCTION DESCRIPTION
Pin
Symbol
Type
Description
1
L021n
L020ut
-
These pins form the PLL reference oscillator when connected to an external parallel-resonant
crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (L02) for
the RF receiver. "L02 In" may also serve as an input for an externally generated reference signal
which is typically a!>-{!oupled. ,
2
3
Vag
-
4
RxPD
Output
Three state voltage output of the Rx Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector input signals. During lock,
very narrow pulses with a frequen~ equal to the reference frequency are present. This pin drives
the external Rx PLL loop filter. It is important to minimize the line length and parasitic capacitance
of this pin.
5
PLL Vref
-
PLL voltage regulator output pin. An internal voltage regulator provides a stable power supply
voltage for the Rx and Tx PLL:s and can also be used as a regulated supply voltage for other IC's.
6
TxPD
Output
Three state voltage output of the Tx Phase Detector. This pin is either "high", "low", or "high
impedance" depending on the phase difference of the phase detector input signals. During lock,
very narrow pulses with a frequency equal to the reference frequency are present. This pin drives
the external Tx PLL loop filter. It is important to minimize the line length and parasitic capacitance
of this pin.
7
GndPLL
Gnd
Ground pin for PLL section of IC.
8
Tx VCO
Input
Transmit divide counter input which is driven by an a!>-{!oupled external transmit loop VCO. The
minimum signal level is 200 mVpp @ 60.0 MHz. This pin also functions as the test mode input for
the counter tests.
9
10
11
Data
Input
Microprocessor serial interface input pins for programming various counters and control functions.
12
ClkOut
Output
Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator and a
programmable divider. It can be used to drive a microprocessor and thereby reduce the number of
crystals required in the system design. The driver has an internal resistor in series with the output
which can be combined with an external capacitor to form a low pass filter to reduce radiated noise
on the PCB. This output also functions as the output for the counter test modes.
13
CD Out
I/O
14
BD10ut
Output
Low battery detect output #1 (open collector with external pull-up resistor).
Data amplifier output (open collector with internal 100 kn pull-up resistor).
Intemal reference voltage for switched capacitor filter section.
EN
Clk
Dual function pin; 1) Carrier detect output (open collector with external 100 kn pull-up resistor.
2) Hardware interrupt input which can be used to ''wakEHlp" from Inactive Mode.
15
DAOut
Output
16
BD20ut
Output
Low battery detect output #2 (open collector with extemal pull-up resistor).
17
Tx Out
Output
Tx path audio output.
18
CCap
-
19
Cln
Input
20
Amp Out
Output
21
Txln
Input
22
DAln
Input
23
VCCAudio
Supply
24
RxAudioln
Input
25
DetOut
Output
Compressor rectifier filter capacitor pin. Pull pin high through a capacitor.
Compressor input (ac-coupled).
Microphone amplifier output.
Tx path input to microphone amplifier (Mic Amp) (a!>-{!oupled).
Data amplifier input (a!>-{!oupled).
VCC supply for audio section.
Rx audio input (a!>-{!oupled).
Audio output from FM detector.
26
RSSI
Output
27
28
a Coil
-
Lim Out
29
VCCRF
Supply
30
31
LimC2
Lim C1
-
IF amplifierillmiter capacitor pins.
32
Lim In
Input
Signal input for IF amplifier/limiter.
8-192
Receive Signal Strength Indicator filter capacitor.
A quad coil or ceramic discriminator connected to these pins as part of the FM demodulator circuit.
VCC supply for RF receiver section.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
TYpe
33
SGNDRF
Gnd
Ground pin for RF section of the IC.
Second mixer input.
34
Mix21n
Input
35
Mix20ut
Output
36
Gnd RF
Gnd
Description
Second mixer output.
Ground pin for RF section of the IC.
First mixer output.
37
Mix10ut
Output
38
Mix11n2
Input
39
Mix11n1
Input
40
41
L011n
L010ut
-
Tank Elements for 1st LO Multivibrator Oscillator are connected to these pins.
42
Vcap Ctrl
-
1st LO Varactor Control Pin.
43
GndAudio
Gnd
44
SA Out
Output
45
SA In
Input
46
EOut
Output
47
Ecap
-
Negative phase first mixer input.
Positive phase first mixer input.
Ground for audio section of the IC.
Speaker amplifier output.
Speaker amplifier input (ac-coupled).
Expandor output.
Expandor rectifier filter capacitor pin. Pull pin high through a capacitor.
48
Eln
Input
49
ScrOut
Output
50
Ref2
-
Reference voltage input for Low Battery Detect #2.
51
Ref1
-
Reference voltage input for Low Battery Detect #1.
52
VB
-
Internal half supply analog ground reference.
Expandor Input.
Rx Audio Output.
II
MOTOROLA ANALOG IC DEVICE DATA
8-193
MC13111
FM Receiver
The FM receiver can be used with either a quad coil or a
ceramic resonator. The FM receiver and 1st LO have been
designed to work for all country channels, including 25
channel U.S., without the need for any external switching
circuitry (see Figure 32).
RSSIICarrier Detect
Connect 0.01 J.lF to Gnd from "RSSI" output pin to form the
carrier detect filter. "CD Ouf' is an open collector output
which requires an external 100 kg pull-up resistor to VCC.
The carrier detect threshold is programmable through the
MPU interface.
Data Amp Comparator
The data amp comparator is an inverting hysteresis
comparator. Its open collector output has an internal 100 kg
pull-up resistor. A band pass filter is connected between the
"Det Out" pin and the "DA In" pin with component values as
shown in Figure 1 (Test Circuit). The "DA In" input signal is
ac-coupled.
Figure 2. Data Amp Operation
OataAmp
Oata
Signal
H----"\--++---T---JIf--+--/-,
Hysteresis
~---r--+---r--+---r----
II
OataAmp
Output
I
t
Expandorl Compressor
In Appendix B, the EIAICCITT recommendations for
measurement of the attack and decay times are defined. The
curves in Figures 3 and 4 show the typical expandor and
compressor output versus input responses.
Figure 3. Expandor Typical Response
10
o
-10
:> -20
~
'5
o
-30
w -40
-50
-60
/
-40
/
/
-30
/'
V
/' ~Out=O~BV
-20
Typical at THO = 5.0%
-10
o
Figure 4. Compressor Typical Response
-10
:> -20
~
'5
o -30
02'
V
/'
V
/'
V
~
Tx Out =-5.0 dBV
Typical at THO = 5.0%
-40
-60
-50
-40
-30
-20
-10
10
20
Tx In (dBV)
Rx Audio Path (LPF/R x Gain Adjust!
Rx MutelExpandorNolume Control)
The Rx Audio signal path goes from "Rx Audio In" (Pin 24)
to "E Out" (Pin 46). The "Rx Audio In" input signal is ac
coupled. AC couple between "Scr Out" and "E In" (see
Figure 3).
Speaker Amp/SP Mute
The Speaker Amp is an inverting raiHo-;ail operational
amplifier. The noninverting input is connected to the internal VB
reference. Extemal resistors and capacitors are used to set the
gain and frequency response. The "SA In" Input is ac coupled.
MicAmp
The Mic Amp is an inverting rail-ter-rail operational amplifier
with noninverting input terminal connected to internal VB
reference. External resistors and capacitors are set to the gain
and frequency response. The ''Tx In" input is ac coupled.
Tx Audio Path (Compressor/ALCITx Mute!
Limiter/LPFITx Gain Adjust)
The Tx Audio signal path goes from "Tx In" (Pin 19) to
"Tx Out" (Pin 17). The "c In" input signal is ac coupled from
"Amp Out". The ALC (Automatic Level Control) provides a
"soft" limit to the output signal swing as the input voltage
increases slowly (i.e., a sine wave is maintained). The Limiter
circuit limits rapidly changing signal levels by clipping the
signal peaks. The ALC andlor Limiter can be disabled
through the MPU serial interface (see Figure 4).
Tx and Rx Audio
Each audio path contains a low-pass switched capacitor
filter (SCF). The control register must be set through the MPU
interface (Figure 11) for proper operation (Tx and Rx bits must
be set to"1 "). The SCF corner frequencies are proportional to
the SCF Clock. The SCF Clock Divider is programmable
through the MPU interface as follows: (SCF) F(2nd LO) I
(SCF Divider Value' 2). The LPF corner frequencies can be
=
10
E In (dBV)
8-194
MOTOROLA ANALOG IC DEVICE DATA
MC13111
selected in from the table in Figures 28 and 29 relative to the
2nd LO operating frequency.
PLL Voltage Regulator
The "PLL Vref' pin is the internal supply voltage for the Rx
and Tx PLL's. It is regulated to a nominal 2.5 V. The "VCC
Audio" pin is the supply voltage for the internal voltage
regulator. Two capacitors with 10 !!F and 0.1 !!F values must
be connected to the "PLL Vret" pin to filter and stabilize this
regulated voltage. The "PLL Vret" pin may be used to power
other IC's as long as the total external load current does not
exceed 1.0 mA. The tolerance of the regulated voltage is
initially ±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the "PLL Vref' pin is internally connected to the
"VCC Audio" pin (Le., the power supply voltage is maintained
but is now unregulated).
Low Battery Detect
Two external precision resistor dividers are used to set
independent thresholds for two battery detect hysteresis
comparators. The voltages on "Refl" and "Ref2" are
compared to an internally generated 1.5 V reference voltage.
The tolerance of the internal reference voltage is initially
±6.0%. The Low Battery Detect threshold tolerance can be
improved by adjusting a trim-pot in the external resistor
divider. Alternately, the tolerance of the internal reference
voltage can be improved to ±1.5% through MPU serial
interface programming. The internal reference can be
measured directly at the "VB" pin. During final test of the
telephone, the VB internal reference voltage is measured.
Then, the internal reference voltage value is adjusted
electronically through the MPU serial interface to achieve the
desired accuracy level. The voltage reference register value
should be stored in ROM during final test so that it can be
reloaded each time the MC13111 IC is powered up. Low
Battery Detect outputs are open collector.
Power Supply Voltage
This circuit is used in a cordless telephone handset and
base unit. The handset is battery powered and can operate
on three NiCad cells or on 5.0 V supply.
·PLL Frequency Synthesizer General Description
Figure 5 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL). This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), Spain, Australia, Korea, New
Zealand, U. K., Netherlands, France, and China.
The 2nd local oscillator and reference divider provide the
reference frequency for the receive (Rx) and transmit (Tx)
PLL loops. The programmed divider value for the reference
divider is selected based on the crystal frequency and the
desired Rx and Tx reference frequency values. Additional
divide by 25 and divide by 4 blocks are provided to allow for
generation of the 1.0 kHz and 6.25 kHz reference
frequencies required for the U. K. The 14-bit Tx counter is
programmed for the desired transmit channel frequency. The
14-bit Rx counter is programmed for the desired first local
oscillator frequency. All counters power up in the proper
default state for USA channel #21 (channel #6 for FCC 10
channel band) and for a 10.24 MHz reference frequency
crystal. Internal fixed capacitors can be connected to the tank
circuit of the 1st LO through microprocessor control to extend
the sensitivity of the 1st LO for U.S. 25 channel operation.
Figure 5. Dual PLL Simplified Block Diagram
Tx VCO
6
12-b
Programmable
Reference
Counter
MOTOROLA ANALOG IC DEVICE DATA
+ 25
~ 4 O'-rT~_
..
+1.0 f-!-*--o
"--:'=-:"::':"""
8-195
8
MC13111
PLL VO Pin Specifications
The 2nd La, Rx and Tx PLL's, and MPU serial interface are
powered by the internal voltage regulator at the "PLL Vref'
pin. The "PLL Vref' pin is the output of a voltage regulator
which is powered from the "VCC Audio" power supply pin and
is regulated by an internal bandgap voltage reference.
Therefore, the maximum input and output levels for most PLL
1/0 pins (L02 In, L02 Out, Rx PO, Tx PO, Tx VCO) is the
regulated voltage at the "PLL Vref' pin. The ESD protection
diodes on these pins are also connected to "PLL Vret".
Internal level shift buffers are provided for the pins (Data, Clk,
EN, Clk Out) which connect directly to the microprocessor.
The maximum input and output levels for these pins is Vee.
Figure 6 shows a simplified schematic ofthe 1/0 pins.
Figure 6. PLL VO Pin Simplified Schematics
PLL Vrel
VCC Audio
PLL Vrel
VCC Audio
OO~'"~~~~~
-=-
L02 In, L02 Out,
Rx PO, Tx PO and
Tx VCOPins
-=- -=-
2.0 JJA -=Data, Clk and EN Pins
-=- -=-
ClkOutPin
Figure 8. Enable Timing Requirement
PrevIous Data Latched
EN
The state of the EN pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 9 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when "EN" is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the "EN" high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
Figure 9. Microprocessor Interface Programming
Mode Diagrams
Data - - - { MSB
ENJ
Microprocessor Serial Interface
The "Data", "elk", and "EN" pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counters, the switched
capacitor filter clock counter, and various control functions.
The "Data" and "elk" pins are used to load data into the shift
register. Figure 7 shows the timing required on the "Data" and
"Clk" pins. Data is clocked into the shift register on positive
clock transitions.
Figure 7. Data and Clock Timing Requirement
tl
Data,
Clk, EN
Data
Clk
Address Register Programming Mode
Data---{ MSB
16-BHData
LSBr
~------------------~-t-~--J ~~Wh
EN ___________________________,
~
Data Register Programming Mode
The MPU serial interface is fully operational within 100 Ils
after the power supply has reached its minimum level during
power-up (see Figure 10). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, Rx , and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Figure 10. Microprocessor Serial Interface
Power-Up Delay
-1~
sot \
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the "EN" pin.
This is done in two steps. First, an 8-bit address is loaded
into the shift register and latched into the 8-bit address latch
register. Then, up to 18-bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 5 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
&-196
8-Bit Address
:-A
______
m'-pu____
2.7_V___
Clk, EN
Data Registers
Figure 11 shows shows the data latch registers and
addresses which are used to select each of these registers.
Latch bits to the left (MSB) are loaded into the shift register
first. The LSB bit must always be the last bit loaded into the
shift register. Bits preceeding the register must be "D's" as
shown in Figure 11.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 11. Microprocessor Interface Data Latch Registers
~
l_~_b_T_x_c_ou_n_re_r
Latch Address
LSB )
____________________________- - J
1. (00000001)
)
__
M_SB______________________ __R_x_c_o_un_te_r____________________________LSB
--J
2. (00000010)
__
M_SB______________________
Tx Counter Latch
~
l_~
Rx Counter Latch
MSB
12-b Reference Counter
3. (00000011)
LSB
Reference Counter Latch
4. (00000100)
Mode Control Latch
5-b Tx Gain Control
5-b Rx Gain Control
MSB
5-b CD Threshold Control LSB
5. (00000101)
6-b Switched
Capacitor Fitter
LSB
Clock Counter Latch
6. (00000110)
Gain Control Latch
~bVoltage
Reference Adjust
SCF Clock Dividers Latch
7. (00000111)
Auxiliary Latch
Figure 12. Reference Frequency and Reference Divider Values
Crystal
Frequency
Reference
Divider
Value
U.K. Basel
Handset
Divider
Reference
Frequency
SC Filter
Clock
Divider
SC Filter
Clock
Frequency
10.24 MHz
2048
1.0
5.0 kHz
31
165.16 kHz
10.24 MHz
1024
4.0
2.5 kHz
31
165.16 kHz
11.15MHz
2230
1.0
5.0 kHz
34
163.97 kHz
12.00 MHz
2400
1.0
5.0 kHz
36
166.67 kHz
11.15MHz
1784
1.0
6.25 kHz
34
163.97 kHz
11.15MHz
446
4.0
6.25 kHz
34
163.97 kHz
11.15 MHz
446
25
1.0 kHz
34
163.97 kHz
MOTOROLA ANALOG IC DEVICE DATA
8-197
II
MC13111
Reference Frequency Selection
The "L02In" and "L02 Ouf' pins form a reference oscillator
when connected to an external parallel-resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 12 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries. "L02 In"
may also serve as an input for an externally generated
reference signal which is ac-coupled. The switched
capacitor filter 6-bit programmable counter must be
programmed for the crystal frequency that is selected since
this clock is derived from the crystal frequency and must be
held constant regardless of the crystal that is selected. The
actual switched capacitor clock divider ratio is twice the
programmed divider ratio since there is a fixed divide by 2.0
after the programmable counter.
Selecf' bits to "0". Then the fixed divider is set to "1" and the
Tx and Rx reference frequencies will be equal to the crystal
oscillator frequency divided by the programmable reference
counter value. The U.K. is a special case which requires a
different reference frequency value for T x and Rx. For U.K.
base operation, set "U.K. Base Select" to "1". For UK
handset operation, set "U.K. Handset Selecf' to "1".The
Netherlands is also a special case since a 2.5 kHz reference
frequency is used for both the Tx and Rx reference and the
total divider value required is 4096 which is larger than the
maximum divide value available from the 12-bit reference
divider (4095). In this case, set "U.K. Base Select" to "1" and
set "U.K. Handset Select" to "1". This will give a fixed divide
by 4 for both the Tx and Rx reference. Then set the reference
divider to 1024 to get a total divider of 4096.
Mode Control Register
Power saving modes, mutes, disables, volume control,
and microprocessor clock output frequency are all set by the
Mode Control Register. Operation of the Mode Control
Register is explained in Figures 14 through 21.
Reference Counter
Figure 13 shows how the reference frequencies for the Rx
and T x loops are generated. All countries except the U.K.
require that the T x and Rx reference frequencies be identical.
In this case, set "U.K. Base Select" and "UK Handset
Figure 13. Reference Counter Register Programming Mode
U.K. Base
~ Tx Reference Frequency
U.K. Handset
12-b
+ 25
Programmable
Reference + 4.0 f-++..
Counter
+1.0 f--f-.......- o Q - - - - Rx Reference Frequency
UK Handset
U.K. Handset
Select
UK Base
Select
TxDivider
Value
RxDivider
Value
Application
0
0
1
1
0
1
0
1
1.0
25
4.0
4.0
1.0
4.0
25
4.0
All but U.K. and Netherlands
U.K. Base Set
U.K. Hand Set
Netherlands Base and Hand Set
12-b Ref Counter
LSB
III-Bit Reference Counter Latch
Figure 14. Mode Control Register Bits
4-bVolume
Control
8-198
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 15. Mute and Disable Control Bit Descriptions
ALC Disable
1
Automatic Level Control Disabled
Normal Operation
0
limiter Disable
1
1
0
1
Tx Mute
0
RxMute
1
0
SP Mute
Circuit Blocks
limiter Disabled
Normal Operation
0
Clock Disable
Figure 17. Power Saving Modes
1
0
Active
Rx
Standby
Inactive
"PLL Vre( Regulated
Voltage
X
X
Xl
Xl
MPU Interface
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MPU Clock Output Disabled
Normal Operation
2nd LO Oscillator
Transmit Channel Muted
Normal Operation
RF Receiver and 1st LO
VCO
Receive Channel Muted
Normal Operation
Carrier Detect
Speaker Amp Muted
Normal Operation
Low Battery Detect
MPU Clock Output
RxPLL
Data Amp
TxPLL
Power Saving Operating Modes
Rx and Tx Audio Paths
When the MC13111 is used in a handset, it is important to
conserve power in order to prolong battery life. There are five
modes of operation; Active, Rx , Standby, Interrupt, and
Inactive. In Active mode, all circuit blocks are powered. In Rx
mode, all circuitry is powered down except for those circuit
sections needed to receive a transmission from the base. In
the Standby and Interrupt Modes, all circuitry is powered
down except for the circuitry needed to provide the clock
output for the microprocessor. In Inactive Mode, all circuitry is
powered down except the MPU interface. Latch memory is
maintained in all modes. Figure 16 shows the control register
bit values for selection of each power saving mode and
Figure 17 shows the circuit blocks which are powered in each
of these operating modes ..
NOTE: In Standby and Inactive Modes, "PLL vref remains powered but
is not regulated. It will fluctuate w~h Vee.
Inactive Mode Operation and Hardware Interrupt
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the combo IC into the Inactive mode, which turns off the
MPU Clock Output (see Figure 18), and then disable the
microprocessor. In order to give the MPU adequate time to
power down, the MPU Clock output remains active for a
minimum of one reference counter cycle (about 200 lIS) after
the command is given to switch into the "Inactive" mode. An
external timing circuit should be used to initiate the turn-on
sequence. The "CD Ouf' pin has a dual function. In the Active
and Rx modes it performs the carrier detect function. In the
Standby and Inactive modes the carrier detect circuit is
disabled and the "CD Out" pin is in a "High" state due to the
external pull-up resistor. In the Inactive mode, the "CD Out"
pin is the input for the hardware interrupt function. When the
"CD Out" pin is pulled "low" by the external timing circuit, the
combo IC switches from the Inactive to the Interrupt mode
thereby turning on the MPU Clock Output. The MPU can then
resume control of the combo IC. The "CD Out" pin must
remain low until the MPU changes the operating mode from
Interrupt to Standby, Active or Rx modes.
Figure 16. Power Saving Mode Selection
Stdby Mode Bit
Rx Mode Bit
"CDOutl
Hardware
Interrupt" Pin
0
0
X
0
1
X
Rx
1
0
X
Standby
1
1
1 or High
Impedance
Inactive
1
1
0
Interrupt
Mode
Active
Figure 18. Hardware Interrupt Operation
Mode
ActiveiR x
Inactive
V
f"V
EN
CD Out/Hardware InlerrupI
CD Oul Low
I
MPUClockOuI
MOTOROLA ANALOG IC DEVICE DATA
I+-I
-I
>
-"'....-
Standby/Rx/Active
r
/
' \ CD Turns Off
1
I
Delay after MPU selects Inactive Mode 10 when CD turns all.
....-
I
I
Interrupt
MPU Initiates
Inactive Mode
External Timer
Pulls Pin Low
/
MPU Inttiales
Mode Change
' \ limer Output
Disabled
K
1
:.- "MPU Clock Ouf' remains active for a minimum of one count of reference
counter after "CD Out/Hardware Interrupf' pin goes high
8-199
8
MC13111
MPU "Clk Out" Divider Programming
This pin is a clock output which is derived from the crystal
oscillator (2nd local oscillator). It can be used to drive a
microprocessor and thereby reduce the number of crystals
required. Figure 19 shows the relationship between the
crystal frequency and the clock output for different divider
values. Figure 20 shows the "Clk Out" register bit values.
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 kil
resistor is included on--chip in series with the "Clk Out" output
driver. A small capacitor can be connected to the "Clk Ouf'
line on the PCB to form a single pole low pass filter. This filter
will significantly reduce noise radiated from the "Clk Ouf' line.
Volume Coritrol Programming
The volume control adjustable gain block can be
programmed in 2.0 dB gain steps from -14 dB to +16 dB. The
power-up default value is 0 dB. (See Figure 21.)
Figure 19. Clock Output Values
Clock Output Divider
Crystal
Frequency
2
3
4
5
10.24 MHz
5.120 MHz
3.413 MHz
2.560 MHz
2.048 MHz
11.15 MHz
5.575 MHz
3.717 MHz
2.788 MHz
2.230 MHz
12.00 MHz
6.000 MHz
4.000 MHz
3.000 MHz
2.400 MHz
MPU "Clk Out" Radiated Noise on Circuit Board
The clock line running between the MC13111 and the
microprocessor has the potential to radiate noise which can
Figure 20. Clock Output Divider
ClkOut
Bit #1
ClkOut
Bit #0
ClkOut
Divider Value
0
0
2
0
1
3
1
0
4
1
1
5
Figure 21. Volume Control
Volume Control
Bit #3
Volume Control
BI1#2
Volume Control
Bit #1
Volume Control
Bit #0
Volume
Control #
Gain/Attenuation
Amount
0
0
0
0
0
-14dB
0
0
0
1
1
-12dB
0
0
1
0
2
-10dB
0
0
1
1
3
-8.0 dB
0
1
0
0
4
-6.0 dB
0
1
0
1
5
-4.0 dB
0
1
1
0
6
-2.0 dB
0
1
1
1
7
OdB
8-200 .
1
0
0
0
8
2.0 dB
1
0
0
1
9
4.0 dB
1
0
1
0
10
6.0 dB
1
0
1
1
11
8.0 dB
1
1
0
0
12
10dB
1
1
0
1
13
12dB
1
1
1
0
14
14dB
1
1
1
1
15
16dB
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Gain Control Register
Tx and Rx Gain Programming
The gain control register contains bits which control the Tx
Voltage Gain, Rx Voltage Gain, and Carrier Detect threshold.
Operation of these latch bits are explained in Figures 22, 23
and 24.
The T x and Rx audio signal paths each have a
programmable gain block. If a Tx or Rx voltage gain other
than the nominal power-up default is desired, it can be
programmed through the MPU interface. Alternately, these
programmable gain blocks can be used during final test of the
telephone to electronically adjust for gain tolerances in the
telephone system as shown in Figure 23. In this case, the T x
and Rx gain register values should be stored in ROM during
final test so that they can be reloaded each time the combo
Ie is powered up.
Figure 22. Gain Control Latch Bits
5-b TxGain Control
5-b Rx Gain Control
Figure 23. TX and Rx Gain Control
Gain Conlrol
Bit #4
Gain Control
Bil#3
Gain Control
Bil#2
Gain Control
Bit #1
Gain Control
Bit #0
Gain
Conlrol#
Gain/Attenuation
Amount
0
0
0
0
0
0
-15dB
0
0
0
0
1
1
-14dB
0
0
0
1
0
2
-13dB
0
0
0
1
1
3
-12dB
0
0
1
0
0
4
-11 dB
0
0
1
0
1
5
-10dB
0
0
1
1
0
6
-9.0 dB
0
0
1
1
1
7
-a.OdB
0
1
0
0
0
a
-7.0 dB
0
1
0
0
1
9
-6.0 dB
0
1
0
1
0
10
-5.0 dB
0
1
0
1
1
11
-4.0 dB
0
1
1
0
0
12
-3.0 dB
0
1
1
0
1
13
-2.0 dB
0
1
1
1
0
14
-1.0dB
0
1
1
1
1
15
OdB
1
0
0
0
0
16
1.0dB
1
0
0
0
1
17
2.0 dB
1
0
0
1
0
18
3.0 dB
1
0
0
1
1
19
4.0 dB
1
0
1
0
0
20
5.0 dB
1
0
1
0
1
21
6.0 dB
1
0
1
1
0
22
7.0 dB
0
1
1
1
23
a.OdB
1
1
0
0
0
24
9.0 dB
1
1
0
0
1
25
10dB
1
1
0
1
0
26
11 dB
1
1
0
1
1
27
12dB
1
1
1
0
0
28
13dB
1
1
1
0
1
29
14dB
1
1
1
1
0
30
15dB
1
1
1
1
1
31
16dB
1
MOTOROLA ANALOG IC DEVICE DATA
II
8-201
MC13111
Carrier Detect Threshold Programming
The ·CD Out" pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. The
nominal value and tolerance of the carrier detect threshold is
given in the carrier detect specification section of this
document. If a different carrier detect threshold value is
desired, it can be progra:mmed through the MPU interface as
shown in Figure 24. Alternately, the carrier detect threshold
can be ele9tronically adjus;ted during final test of the
telephone to reduce the tolerance of the carrier detect
threshold. This is done by measuring the threshold and then
by adjusting the threshold through the MPU interface. In this
case, it is necessary to store the carrier detect register value
in ROM so that the CD register can be reloaded each time the
combo IC is powered up.
Figure 24. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
BII#l
CD
Bit #0
CD
Control #
Carrier Detect
Threshold
0
0
0
0
0
0
-20 dB
0
0
0
0
1
1
-19dB
0
0
0
1
0
2
-18 dB
0
0
0
1
1
3
-17 dB
0
0
1
0
0
4
-16 dB
0
0
1
0
1
5
-15 dB
0
0
1
1
0
6
-14 dB
0
0
1
1
1
7
-13dB
0
1
0
0
0
8
-12 dB
0
1
0
0
1
9
-11 dB
0
1
0
1
0
10
-10dB
0
1
0
1
1
11
-9.0 dB
0
1
1
0
0
12
-8.0 dB
0
1
1
0
1
13
-7.0 dB
0
1
1
1
0
14
-6.0 dB
0
1
1
1
1
15
-5.0 dB
1
0
0
0
0
16
-4.0 dB
1
0
0
0
1
17
-3.0 dB
1
0
0
1
0
18
-2.0dB
1
0
0
1
1
19
-1.0dB
1
0
1
0
0
20
OdB
1
0
1
0
1
21
1.0dB
1
0
1
1
0
22
2.0 dB
1
0
1
1
1
23
3.0 dB
1
1
0
0
0
24
4.0 dB
1
1
0
0
1
25
5.0 dB
1
1
0
1
0
26
6.0 dB
1
1
0
1
1
27
7.0 dB
1
1
1
0
0
28
8.0 dB
II
8-202
1
1
1
0
1
29
9.0 dB
1
1
1
1
0
30
10dB
1
1
1
1
1
31
11 dB
MOTOROLA ANALOG Ie DeVice DATA
MC13111
Figure 25. SCF Clock Divider Latch Bits
6-b Switched
Capacitor Filter
Clock Counter Latch
4-bVoltage
Reference Adjust
SCF Clock Divider
This register controls the divider value for the
programmable switched capacitor filter clock divider and the
voltage reference adjust. Operation is explained in Figures
25 through 30.
The SCF divider should be set to a value which gives a
SCF Clock as close to 165.16 kHz as possible based on the
2nd LO frequency which is chosen (see Figure 12).
Figure 27. SCF Clock Circuit
Figure 26. Audio Mode Bit Description
TxMode
1
0
Normal T x Path Operation
Undefined State
RxMode
1
0
Normal Rx Path Operation
Undefined State
NOTES: Power-up brt default mode
proper operation.
IS
6-b
Programmable
SCF Clock Counter
L02 Out
"0". Must change bit to "1" for
Corner Frequency Programming
Four different corner frequencies may be selected by
programming the SCF Clock divider as shown in Figures 28
and 29. Note that all filter corner frequencies change
proportionately with the SCF Clock Frequency. The
power-up default SCF Clock divider is 31.
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter clock
dividers is shown in Figure 27. There is a fixed divide by 2
after the programmable divider. The switched capaCitor filter
clock value is given by the following equation;
(SCF Clock)
=F(2nd LO)/(SCF Divider Value' 2)
II
Figure 28 Corner Frequency Programming for a 10.240 MHz 2nd LO
SCFClock
Divider
Total
Divide Value
SCFClock
Freq. (kHz)
Rx Upper Corner
Frequency (kHz)
Tx Upper Corner
Frequency (kHz)
29
30
31
32
58
60
62
64
176.55
170.67
165.16
160.00
4.147
4.008
3.879
3.758
3.955
3.823
3.700
3.584
NOTE:
All filter corner frequencies have a tolerance of ±3%.
Figure 29 Corner Frequency Programming fora 11.15 MHz 2nd LO
SCFClock
Divider
Total
Divide Value
SCFClock
Freq. (kHz)
Rx Upper Corner
Frequency (kHz)
Tx Upper Corner
Frequency (kHz)
32
33
34
35
64
66
68
70
174.22
168.94
163.97
159.29
4.092
3.968
3.851
3.741
3.903
3.785
3.673
3.568
NOTE:
All filter corner frequencies have a tolerance of ±3%.
MOTOROLA ANALOG IC DEVICE DATA
6-203
MC13111
Voltage Reference Adjustment
The internal 1.5 V Bandgap voltage reference provides the
voltage reference for the "BD1 Ouf' and "BD2 Ouf low
battery detect circuits, the "PLL Vre(' voltage regulator, the
"VB" reference, and all internal analog ground references.
The initial tolerance of the Bandgap voltage reference is
±S%. The tolerance of the internal reference voltage can be
improved to ±1.5% through MPU serial interface
programming.
During final test of the telephone, the battery detect
threshold is measured. Then, the internal reference voltage
value is adjusted electronically through the MPU serial
interface to achieve the desired accuracy level. The voltage
reference register value should be stored in ROM during final
test so that it can be reloaded each time the MC13111 is
powered up (see Figure 30).
figure 30. Bandgap Voltage Reference Adjustment
II
VrefAdj.
Bit #3
VrefAdJ.
Bit #2
0
0
VrefAdJ.
Bit #1
VretAdj.
Bit #0
VrefAdJ.
#
VrefAdj.
Amount
0
0
0
0
-9.0%
0
0
1
1
-7.8%
0
0
1
0
2
-6.6%
0
0
1
1
3
-5.4%
0
1
0
0
4
-4.2%
0
1
0
1
5
-3.0%
0
1
1
0
6
-1.8%
0
1
1
1
7
-0.6%
1
0
0
0
8
+0.6%
1
0
0
1
9
+1.8%
1
0
1
0
10
+3.0%
1
0
1
1
11
+4.2%
1
1
0
0
12
+5.4%
1
1
0
1
13
+6.6%
1
1
1
0
14
+7.8%
1
1
1
1
15
+9.0%
8-204
Auxiliary Register
The auxiliary register contains a 3-bit 1st LO Capacitor
Selection latch and a 4-bit Test Mode latch. Operation of
these latch bits are explained in Figures 31, 32 and 34.
Figure 31. Auxiliary Register Latch Bits
MSB
4-b Test Mode
LSB
MSB
3-b 1st LO Capacitor
Selection
LSB
First Local Oscillator Programmable Selection (U.S.
Applications)
There is a very large frequency difference between the
minimum and maximum channel frequencies in the 25
Channel U.S. Standard.The sensitivity of the 1st LO may not
be large enough to accommodate this large frequency
variation. Fixed capacitors can be connected across the 1st
LO tank circuit to change the 1st LO sensitivity. Internal
switches and capacitors are provided to enable
microprocessor control over internal fixed capacitor values.
Figures 32 and 33 show the schematic representation of the
1st LO and the tank circuit. Figure 34 shows the latch control
bit values for microprocessor control.
Figure 32. First Local Oscillator Schematic
-------------,I
I Vcap Ctrt
Varactor I 41
I
I
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 33. First Local Oscillator Simplified Schematic
VCCRF
VCCRF
Output
to Buffer
85iJ.A
85iJ.A
Control
Voltage
12 k
12k
1·
VCCRF
8.0k
LOOut
VCCRF
8.0 k
LO In
5.8-8.7
6.0 k
-=-
6.0k
-=-
-=-
-=-
-=Cp 0.8pF
-L
38n
Ca 0.9 pF
57n
Cb 1.7 pF
32n
Cc 6.3 pF
22n
Cd 7.8 pF
-L
-L
-L
II
Figure 34. First Local Oscillator Programmable Capacitor Selection for U.S. 25 Channels
1st
LO
Cap.
Bit 2
1st
LO
Cap.
Bit 1
1st
LO
Cap
BitO
1st
LO
Cap.
Setect
U.S.
Base
Channels
U.S.
Handset
Channels
Internal
Capacitor
Value
Varactor
Value over
0.3 to 2.5 V
Equivalent
Internal
Parallel
Resistance
at 40 MHz
(Idl)
0
0
0
0
1-10
-
O.SpF
5.S-S.7pF
>1000
>1000
24pF
0
0
0
0
-
1-10
O.SpF
5.8-S.7pF
>1000
>1000
33pF
0.47~H
0
0
1
1
11-16
-
2.5pF
5.8-8.7 pF
35
21
24pF
0.47 ~H
0
1
0
2
17-25
-
1.7 pF
5.8-8.7pF
100
60
24pF
0.47 ~H
0
1
1
3
-
11-16
S.6pF
5.8-8.7pF
6.1
3.S
33pF
0.47 ~H
1
0
0
4
-
17-25
7.1 pF
5.8-8.7pF
S.O
5.0
33pF
0.47 ~H
MOTOROLA ANALOG IC DEVICE DATA
Equivalent
Internal
Parallel
Resistance
at 51 MHz
(Idl)
External
Capacitor
Value
External
Inductor
Value
0.47~H
8-205
MC13111
Figure 35. Digital Test Mode Description
Counter Under Test or
Test Mode Option
TM#
TM3
TM2
TM1
TMO
0
0
0
0
0
Normal Operation
"TxVCO"
Input Signal
"Clk Out" Output Expected
-
>200mVpp
1
0
0
0
1
Rx Counter, upper 6
Ot02.5 V
Input Frequency/64
2
0
0
1
0
Rx Counter, lower 8
Ot02.5 V
See Note Below
Input Frequency/4
3
0
0
1
1
Rx Prescaler
Ot02.5 V
4
0
1
0
0
Tx Counter, upper 6
Oto 2.5 V
Input Frequency/64
5
0
1
0
1
Tx Counter, lower 8
Oto 2.5 V
See Note Below
6
0
1
1
0
Tx Prescaler
Reference Counter
Oto 2.5 V
Input Frequency/Reference Counter Value
Input Frequency/100
>200mVpp
7
0
1
1
1
8
1
0
0
0
Divide by 4, 25
Oto 2.5 V
9
1
0
0
1
SCCounter
Oto 2.5 V
10
1
0
1
0
Not Used
NOTE:
Input Frequency/4
Input Frequency/SC Counter Value
-
N/A
To detenninethe correct output, look at the 10wer8--bits in the Rx orTx register (Divisor (7;0). If the value 01 the divisor is > 16, then the output divisor
value is Divisor (7;2) (the upper 6--bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3
01 the divisor). II Divisor (7;0) < 16 and Divisor (3;2) < 2, then oulput divisor value is (Divisor (3;2) + 60).
Figure 36. Analog Test Mode Description
II
TM#
TM3
TM2
TM1
TMO
Circuit Blocks Under Test
Input Pin
Output Pin
11
1
0
1
1
Compressor
Cln
Tx In
12
1
1
0
0
Not Used
N/A
N/A
13
1
1
0
1
ALC Gain =10 Option
N/A
N/A
14
1
1
1
0
ALC Gain =25 Option
N/A
N/A
15
1
1
1
1
Not Used
N/A
N/A
Test Modes
Digital and analog test modes can be selected through the
4-bit Test Mode Register. In digital test mode, the ''Tx VCO"
input pin is multiplexed to the input of the counter under test
and the output of the counter under test is multiplexed to the
"Clk Ouf' output pin so that each counter can be individually
tested. Make sure test mode bits are set to "D's" for normal
operation. Digital test mode operation is described in
Figure 35. During normal operation and when testing the
T x Prescaler, the ''Tx VCO" input can be a minimum of 200
mVpp at 80 MHz and should be ao-coupled. For other test
modes, input signals should be standard logic levels of 0 to
2.5 V and a maximum frequency of 16 MHz.
The analog test modes enable separate testing of the
Compressor blocks as shown in Figure 36. Also, ALC Gain
options can be selected through analog test modes.
8-206
Power-Up Defaults for Control and Counter Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in
the Rx mode with all mutes active. The reference counter is
set to generate a 5.0 kHz reference frequency from a 10.24
MHz crystal. The switched capacitor filter clock counter is set
properly for operation with a 10.24 MHz crystal. The audio
mode will come up in an undefined state and must be set to
a bit format shown in Figure 26 for proper operation. The T x
and Rx latch registers are set for USA Channel Frequency 21
(Channel 6 for previous FCC 10 Channel Band). Figure 37
shows the initial power-up states for all latch registers.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Figure 37. Latch Register Power-Up Defaults
MSB
Register
Count
15
14
LSB
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Tx
9966
-
-
1
0
0
1
1
0
1
1
1
0
1
1
1
Rx
7215
-
0
1
1
1
0
0
0
0
1
0
1
1
1
1
Ref
2048
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Mode
N/A
-
0
X
0
0
1
1
0
1
1
1
0
1
1
1
1
Gain
N/A
-
0
1
1
1
1
0
1
1
1
1
1
0
1
0
0
SC
31
-
-
-
-
0
1
1
1
0
0
0
1
1
1
1
1
Aux
N/A
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
NOTE:
Bits 6 and 7 in the SC latch register must be set to "1" after power-up for proper operation.
APPLICATIONS INFORMATION
Evaluation PC Board
The PCB should be double sided with a full ground plane
on one side; any leaded components are inserted on the
ground plane side. This affords shielding and isolation from
the circuit side of the PCB. The other side is the circuit side
which has the interconnect traces and the surface mount
components. In cases where cost allows, it may be benificial
to use multi layer boards.
The placement of certain components specified in the
application circuits is very critical. These components should
be placed first and the other less critical components are
fitted in last. In general, all RF paths should be kept as short
as possible, ground pins should be grounded at the pins and
VCC pins should have adequate decoupling to ground at the
pins. In mixed mode systems where digital and RF/Analog
circuitry are present, the VEE and VCC busses are isolated ac
-wise from each other.
Component Selection
The evaluation PC board is designed to accommodate
specific components, while in some cases it is versatile
enough to use components from various manufacturers and
coil types. The application circuit schematics specify
particular components that were used to achieve the results
shown in the typical curves and tables, but alternate
components should give similar results.
The MC13111 IC is capable of matching the sensitivity,
IMD, adjacent channel rejection, and other performance
criteria of a multi-chip analog cordless telephone system.
For the most part, the same external components are used
as in the multi-chip solution. In the following discussion,
various parts of the system are analyzed for best peformance
and cost tradeoffs. Specific recommendations are made
where certain components or circuit designs offer superior
performance. The system analyzed is the USA "CT-1"
cordless phone. (CT-D is a similar cordless application in
Europe.)
Input Matching/Sensitivity
The sensitivity of the IC is typically 0.561lVrms matched
with no preamp. To achieve suitable system performance, a
preamp and passive duplexer must be used. In production
final test, each section of the IC is separately tested to
guarantee its system performance in the specific
application. The preamp and duplexer (differential, matched
MOTOROLA ANALOG IC DEVICE DATA
input) yields typically -114 dBm 12 dB SINAD sensitivity
performance under full duplex operation.
The duplexer is important to achieve full duplex operation
without significant "de-sensing" of the receiver by the
transmitter. The combination of the duplexer and preamp
circuit will attenuate the transmitter power to the receiver by
over 60 dB. This will improve the receiver system noise figure
without giving up too much IMD intermodulation
performance.
The duplexer may be a single piece unit offered by
Shimida and Sansui products (designed for 10 channel CT-1
cordless phone) or a two piece solution offered by Toko
(designed for 25 channel operation). The duplexer frequency
response at the receiver port has a notch at the transmitter
frequency band of about 35 to 40 dB with a 2.0 to 3.0 dB
insertion loss at the receiver frequency band.
The preamp circuit utilizes a tuned transformer at the
output side of the amplifier. This transformer is designed to
bandpass filter at the receiver input frequency while rejecting
the transmitter frequency. The tuned preamp also improves
the noise performance by reducing the bandwidth of the pass
band and reducing the second stage contribution of the 1st
mixer. The preamp is biased at about 1.0 mA and 3.0 Vdc
which yields suitable noise figure and gain.
Mixers
The 1st and 2nd mixers are similar in design. Both are
double balanced to suppress the LO and the input
frequencies to give only the sum and difference frequencies
out. Typically the LO is suppressed about 40 to 60 dB. The
1st mixer may be driven either differentially or single ended.
The gain of the 1st mixer has a 3.0 dB corner at 20 MHz and
is used at a 10.7 MHz IF. It has an output impedance of
330 n and matches to a typical 10.7 MHz ceramic filter with
a source and load impedance of 330 n. A series resistor may
be used to raise the impedance for use with crystal filters
which typically have an input impedance much greater than
330 n. The 2nd mixer input impedance is typically 3.0 kn; it
requires an external 360 n parallel resistor for use with a
standard 330 n 10.7 MHz ceramic filter. The second mixer
output impedance is 1.5 kn making it suitable to match
455 kHz ceramic filters.
8-207
II
:
MC13111
The following table is a list of typical input impedances
over frequency for the 1st Mixer. Rp and Cp are represented
in parallel form.
1.1
Frequency (MHz)
Rp(Q)
Cp(pF)
20
977.7
2.44
25
944.3
2.60
30
948.8
2.65
35
928
2.55
2.51
40
900
45
873.4
2.65
50
859.3
2.72
55
821
2.72
60
795
2.74
First Local Oscillator
The 1st LO is a multi-vibrator oscillator that takes an
external capacitance and inductance. It is voltage controlled
to an internal varactor from an external loop filter and an
on-board phase-lock loop (PLL). The schematic in Figure 33
shows all the basic parasitic elements of the internal circuitry.
The 1st LO internal component values have a tolerance of
15%. A typical dc bias level on the LO Input and LO Output is
0.45 Vdc. The temperature coefficient of the varactor is
+0.09%fOC. The curve in Figure 38 is the varactor control
voltage range as it relates to capacitance. It represents the
expected capacitance for a given control voltage of the
MC13111.
Figure 38. First Local Oscillator Varacter
versus Control Voltage
12
11
u::.s
w
10
1'!'
9.0
~
"-..........:-........
~ 8.0
<3
~ 7.0
6.0
5.0
limiting IF Amplifiers
The limiting IF amplifier typically has about 110 dB of gain;
the frequency response starts rolling off at 1.0 MHz.
Decoupling capacitors should be placed close to Pins 31 and
32 to ensure low noise and stable operation. The IF input
impedance is 1.5 kQ for a suitable match to 455 kHz ceramic
filters .
\.
C3
o
0.5
.....
:---"-
1.0
1.5
2.0
VCV, CONTROL VOLTAGE (V)
r-2.5
3.0
Second Local Oscillator
The 2nd LO is a CMOS oscillator Similar to that used in the
MC145162. The 2nd LO is also used as thePLL reference
oscillator. It is designed to utilize an external parallel resonant
crystal.
PLL DeSign
The 1st LO level is important, as well as the choice of the
crystal for the PLL clock reference and 2nd LO. A
fundamental, parallel resonant crystal specified with 1.0 to
8-208
12 pF load calibration capacitance is recommended. If the
load calibration capacitance is too high, the crystal locks up
very slowly. If the LO power is less than -10 dBm, a
pull-down resistor at the 1st LO emitter (Pin 41) will
increase its drive level. The LO level is primarily a function
of the Colpitts capacitive voltage divider formed by the
capacitors between the base to emitter and the emitter to
ground.
The VCO gain factor expressed in MHzIV is indeed critical
to the phase noise performance. If this curve is too steep or
too sensitive to changes in control voltage, it may degrade
the phase noise performance. The external VCO circuit
design needs to consider the typical swing of the control
voltage and the corresponding linearity of the transfer
function, Ll.fosdLl.Vcontrol. In general, the higher the Q of the
VCO circuit inductor, the better phase noise performance.
Adjacent channel rejection and isolation between the 1st
and 2nd mixers may be adversely affected due to layout
problems and difficulty in getting up close to the package pins
with the grounds and decoupling capacitors on the RF VCC.
These system parameters must be evaluated for sensitivity
to layout and external component placement.
Intermodulation' and adjacent channel performance
problems may also result from spurs around the 1st LO. This
may be caused by harmonics from the switched capacitor
clock driver and too low 1st LO drive level. The clock driver
operates at a frequency which is f(2nd LO)/(2 • (SCF
Divider)). The harmonics are n • (f(2nd LO)), where n can be
any positive integer. The current spikes of the SCF on the
supply lines cause the disturbance of the 1st LO. This may be
verified by observing the spurs on a spectrum analyzer while
changing the clock divider value. The spur frequencies will
change when the divider value is changed. The spurious
sideband problem may be avoided by changing the clock
divider value via software for each channel where it is a
problem. Certain channels are worse than others. Refer to
the MC145162 data sheet for PLL design example.
RSSIiCarrier Detect
The Received Signal Strength Indicator (RSSI) indicates
the strength of the IF level and the output is proportional to
the logarithm of the IF input signal magnitude. The RSSI
dynamic range is typically 80 dB. Connect 0.01 J.lF to GND
from "RSSI" output pin to form the carrier detect filter. A
resistor needed to convert the RSSI current to voltage is
included in the internal circuit. An internal temperature
compensated reference current also improves the RSSI
accuracy over temperature.
"CD Out" is an open collector output; thus, an external
100 kQ pull-up resistor to VCC is recommended. The carrier
detect threshold is programmable through the MPU
interface.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
Quadrature Detector
The quadrature detector is coupled to the IF with an
external capacitor between Pins 27 and 28; thus, the
recovered signal level output is increased for a given
bandwidth by increasing the capacitor. The external
quadrature component may be either a LCR resonant circuit,
which may be adjustable, or a ceramic resonator which is
usually fixed tuned.
The bandwidth performance of the detector is controlled
by the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
where RT is the equivalent shunt resistance across the LC
Tank. XL is the reactance of the quadrature inductor at the IF
frequency (XL =21tfL).
Specific 455 kHz quadrature LC components are
manufactured by Toko in various 5 mm, 7 mm and 10 mm
shielded cans in surface mount or leaded packages.
Recommended components such as, the 7 mm Toko, is used
in the application circuit. When minaturization is a key
constraint, a surface mount inductor and capacitor may be
chosen to form a resonant LC tank with the PCB and parasitic
device capacitance. The 455 kHz IF center frequency is
calculated by
(2) fc
=[21t (LCp)1/2j-1
where L is the parallel tank inductor. Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455 kHz
and a specific loaded Q. The loaded Q of the quadrature
detector is chosen somewhat less than the Q of the IF
bandpass. For an IF frequency of 455 kHz and an IF bandpass
MOTOROLA ANALOG IC DEVICE DATA
of 20 kHz, the IF bandpass Q is approximately 23; the loaded
Q of the quadrature tank is chosen at 15.
Example:
Let the total external C =180 pF. Note: the capacitance may
be split between a 150 pF chip capacitor and a 5.0 to 25 pF
variable capacitor; this allows for tuning to compensate for
component tolerance. Since the external capacitance is much
greater than the internal device and PCB parasitic
capacitance, the parasitic capacitance may be neglected.
Rewrite equation (2) and solve for L:
L = (0.159)2/(C fc 2)
L =678 ~H ; Thus, a standard value is chosen:
L = 680 ~H (surface mount inductor)
The value of the total damping resistor to obtain the
required loaded Q of 15 can be calculated from equation (1):
RT = Q(21tfL)
RT =15 (21t)(0.455)(680) =29.5 kn
The internal resistance, Rint at the quadrature tank Pin 27
is approximately 100 kn and is considered in determining
the external resistance, Rext which is calculated from
Rext =((RTHRint))/(Rint - AT)
Rext = 41.8 kn; Thus, choose the standard value:
Rext =39 kn
A ceramic discriminator is recommended for the
quadrature circuit in applications where fixed tuning is
desired. The ceramic discriminator and a 22 k resistor are
placed from Pin 27 to VCC. A 10 pF capaCitor is placed from
Pin 28 to 27 to properly drive the discriminator.
MuRata Erie has designed a resonator that is compatible
with the IC. For US applications the part number is
CDBM455C48. For Europe the part number is
CDBM450C48. Contact Motorola Analog Marketing for
performance data using muRata's parts.
8-209
II
II
...t
Figure 39a. Baseset RF Applications Circuit
CI
TP25
A3
220
~g
P35
VCC-AF
VCC-RF~
l00~ I
-," ,.
47
O!:""i ~(:~v~''--_ __
C2
0.1
TxAF-ln----------'
l>
C5
24pF
SPl
15(1..0000
TP4
C6
~711F
r.
'1~41L01"
r-------------------------
AS
42
v~~
-I~
47k
MlI:llnl M
LC, In
~
"U
"U
m
C87
A33
1000
Z
C
R26
~
X
C88
:
l>
0.15
~
I
~
"U
"U
Speaker
~
Gnd
Mic
A30 680 k
ICl
MC13111FB
~Gnd
VCC-A~
•
"uT
''''
wl ,
s::
~::t1
o
~
l>
Z
l>
b
Cil
(')
C
~
o
c
m
~
loi
llh'
no.
•
$
C
Law Batt
::j
TP13
IW<
j2iM1.0 k
i'
5!~~:
~TxVT
Gnd
g~tutetect
Clk
!j
0
Z
en
0
Ax Data
TP19
EN
Co)
r
.....
n .....
.....
0
Batt Dead
s:
0.....
Figure 39a. Baseset RF Applications Circuit (continued)
i!:
o
d%I
o
~
!
8
03
I T - - V Tx
Battl
V+
V-
(;
c
0 . l Y 2 . 2 I1 F
2N3906
I
Q4
C54
lOI1F
1+
C53
0.01
J: cs/CC
c561
L6
56I1H
VRx
=
Gnd
'--~---
2N3906
VCC-RF
R95
m
:s
o
R94
12k
= Gnd
m
c
~
)Ii
12k
Gnd
TxPWR-ON
' - - - - - - R x PWR-ON
C58:t
10
l1FJ
VCC-A
CONl
Gnd
C59
180
Tx Audio------,
R54
lOOk
R53
::> 68k
MODINl
RF09ctl",S,--.:::;:::::!.-~~~~~
Daoouplr.g
---~~~-~~~~-1l3 r.:::::- c.,.,.." 14
r--;R;;:5:;-1.......
110k
4
R37
22 k
=- ill
02
""
N
5 t:,....
~
02 12
R49 100
N~~--~~~~--
6Gnd
~
8~
Tr211
Cd~19
C40
10
~
t.-.-
R46
220k
R47
75k
"cc
.--_ _--'-'7 01
27 k
VTx
CoIl9cIor
_
Tx Data
Tx
C45
13 10
Aux
26
VBatt
25
Tx Data
24
Gnd
23
Gnd
22
Gnd
21
RSSI
20
Batt Dead
19
Pl
*
00
See Note 1
NOTE 1: C42=X42=51 g
II
Low Batt
Aux
R45
'10
..L
C50JO.022
R44
=..----'VI!'r- TxRF-ln
R42
91 k
27
RxData
VCO
110
C5110.022
R43
28
Aux
Aux
Aux
10
11
12
13
14
18
17
16
15
Aux
Aux
TxPWR-ON
RxPWR-ON
Gnd
VB
Data
Enable
Clk
ClkOUt
Carrier Detect
Aux
Aux
Aux
3:
....(')
....
....
Co)
....
MCt3111
APPENDIX B - MC13111 APPLICATION BOARD BILL OF MATERIAL (USA)
Reference
Xl
Description
10.24 Crystal (Load Cap <12 pF)
Package
Part Number
Vendor
-
HC49US
AAL10M240000FLE10A
Standard Crystal
So123
MMBV2109LTl
Motorola
DUP1
Duplexer (25 Channel)
Saseset
Hybrid
DPX103575B-153B
Sumida
DUP1
Duplexer (25 Channel)
Handset
Hybrid
DPX103575B-154B
Sumida
-
SFE10.7MS2-A
muRata
CFU455E2
muRata
QFP
MC13111FB
Motorola
S0-16
MC2833D
Motorola
VR2
Diode
Value
FL1
10.7 MHz Filter (Red Dot)
-
FL2
455 kHz Filter
ICl
Universal Cordless Telephone IC
IC2
FM Transmitter IC
-
L3
Inductor
0.471J-H
Can
·292SNS-T1370Z
Toko
L4/L5
Inductor
0.221J-H
Can
292SN5-T1368Z
Toko
T11T3
Transformer
Can
6OOGC5-8519N
Toko
Can
7MC5-8128Z
Toko
T2
Quadrature Coil
-
Q1
Transistor
-
TQ-92
MPSH10
Motorola
Q3
Transistor
-
TQ-92
2N3906
Motorola
Q4
Transistor
-
TQ-92
2N3906
Motorola
NOTE:
8-212
Components for the Handset and Basese! are the same, except where noted on the Bill of Material and Schematic.
MOTOROLA ANALOG IC DEVICE DATA
MC13111
APPENDIX C - MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME
This measurement definition is based on EIAICCITI
recommendations.
Compressor Attsck Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.SX of the final steady state
value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.7SX of the final steady
state value.
Expandor Attack
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.S7X of the final steady
state value.
Expandor Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.SX of the final steady
state value.
f
Input _ _ _-!
~
OmV---~-----+_-----
12dB
Input _ _ _-,
OmV-----+------+-------Attack Time
Attack Time
OecayTime
Output _ _ _....
Output
----'
OmV-----------------------OmV------------------
MOTOROLA ANALOG IC DEVICE DATA
8-213
II
®
MOTOROLA
MC13135
MC13136
FM Communications Receivers
The MC13135/MC13136 are the second generation of single chip, dual
conversion FM communications receivers developed by Motorola. Major
improvements in signal handling, RSSI and first oscillator operation have
been made. In addition; recovered audio distortion and audio drive have
improved. Using Motorola's MOSAICTM 1.5 process, these receivers offer
low noise, high gain and stability over a wide operating voltage range.
Both the MC13135 and MC13136 include a Colpitts oscillator, VCO tuning
diode, low noise first and second mixer and LO, high gain limiting IF, and
RSSI. The MC13135 is designed for use with an LC quadrature detector and
has an uncommitted op amp that can be used either for an RSSI buffer or as
a data comparator. The MC13136 can be used with either a ceramic
discriminator or an LC quad coil and the op amp is internally connected for a
voltage buffered RSSI output.
These devices can be used as stand-alone VHF receivers or as the lower
IF of a triple conversion system. Applications include cordless telephones,
short range data links, walkie-talkies, low cost land mobile, amateur radio
receivers, baby monitors and scanners.
DUAL CONVERSION
NARROWBAND
FM RECEIVERS
-
PSUFFIX
PLASTIC PACKAGE
CASE 724
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(S0-24L)
• Complete Dual Conversion FM Receiver - Antenna to Audio Output
• Input Frequency Range - 200 MHz
• Voltage Buffered RSSI with 70 dB of Usable Range
ORDERING INFORMATION
• Low Voltage Operation - 2.0 to 6.0 Vdc (2 Cell NiCad Supply)
• Low Current Drain - 3.5 rnA Typ
II
Device
• Low Impedance Audio Output < 25 n
Operating
Temperature Range
MC13135P
• VHF Colpitts First LO for Crystal or VCO Operation
MC13135DW
• Isolated Tuning Diode
• Buffered First LO Output to Drive CMOS PLL Synthesizer
MC13136P
S0-24L
TA = - 40° to +85°C
1st LO Base
1 1----.3f--i
151 LO Emitter 2
151 LO Out 3 1---..-..,.--'
2nd LO Emitter 5
2ndLOBese 6
2nd Mixer Oul 7 I---<~--'
PIN CONNECTIONS
MC13136
VaricapC
1st LO Base 1
VaricapA
1sl LO Emitter 2
151 Mixer In 1
1st LO Out 3
1st Mixer Out
2nd LO Emitter 5
Vcc2
2nd Mixer In
2ndLOBese 6
2nd Mixer 0IJt 7
RSSI
rm----;
Quad Coil
1st Mixer Out
VCC2
2nd Mixer In
OpAmpln-
Decouple 1
Decouple 2 11
Decouple 2 11
VaricapA
1+----l"~llsIMixerlnl
Buffered RSSI Output
OpAmpOul
OpAmp In-
VaricapC
.---II>--rr71 Audio Out
Audio Out
Decouple 1
Plastic DIP
S0-24L
MC13136DW
MC13135
Package
Plastic DIP
RSSI
Urn/ler Output
r;d---+-l'=-=-=~-"""'ilIl Quad Input
Each device contains 142 active transistors.
8-214
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
MAXIMUM RATINGS
Rating
Power Supply Voltage
Pin
Symbol
Value
4,19
Vcc(max)
6.5
Vdc
RFin
1.0
Vrms
Unit
RF Input Voltage
22
Junction Temperature
-
TJ
+150
'c
Storage Temperature Range
;;-
Tstg
- 65 to +150
'C
Unit
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Maximum 1st IF
Maximum 2nd IF
Ambient Temperature Range
Pin
Symbol
Value
4, 19
VCC
2.0 to 6.0
Vdc
flFI
21
MHz
flF2
3.0
MHz
TA
-40to+85
'C
-
ELECTRICAL CHARACTERISTICS (TA=25'C, VCC=4.0Vdc, '0=49.7MHz, 'MOD= 1.0kHz, Deviation=±3.0kHz, flstLO=39MHz, f2nd
LO = 10.245 MHz, IFI = 10.7 MHz, IF2 = 455 kHz, unless otherwise noted. All measurements performed in the test circuit of Figure 1.)
Characteristic
Condition
Symbol
Total Drain Current
No Input Signal
ICC
Sensitivity (Input for 12 dB SINAD)
Matched Input
VSIN
Recovered Audio
MC13135
MC13136
VRF = 1.0 mV
AFO
Limiter Output Level
(Pin 14, MC13136)
VLlM
1st Mixer Conversion Gain
VRF=-40dBm
MXgain1
2nd Mixer Conversion Gain
VRF=-40dBm
MXgain2
First LO Buffered Output
-
VLO
Total Harmonic Distortion
VRF=-30dBm
THO
Demodulator Bandwidth
-
RSSI Dynamic Range
First Mixer 3rd Order Intercept
(Input)
Second Mixer 3rd Order
Intercept (RF Input)
BW
RSSI
TOIMixl
Matched
Unmatched
Min
Typ
Max
Unit
-
4.0
6.0
mAdc
1.0
-
!lVrms
170
215
220
265
300
365
-
130
-
dB
100
-
mVrms
1.2
3.0
%
50
-
kHz
mVrms
mVrms
12
13
70
dB
dB
dBm
-
-17
-11
-
-27
Matched
Input
TOIMix2
First LO Buffer Output Resistance
-
RLO
-
First Mixer Parallel Input Resistance
-
R
-
722
First Mixer Parallel Input CapaCitance
-
C
-
3.3
First Mixer Output Impedance
-
ZO
-
330
-
Z,
-
4.0
-
kg
-
ZO
-
I.B
-
kn
25
-
g
Second Mixer Input Impedance
Second Mixer Output Impedance
Detector Output Impedance
MOTOROLA ANALOG IC DEVICE DATA
ZO
dBm
-
g
g
pF
g
8-215
II
MC13135 MC13136
TEST CIRCUIT INFORMATION
Although the MC13136 can be operated with a ceram.ic
discriminator, the recovered audio measurements for both
the MC13135 and MC13136 are made with an LC quadrature
detector. The typical recovered audio will depend on the
external circuit; either the Q of the quad coil, or the RC
matching network for the ceramic discriminator. On the
MC13136, an external capacitor between Pins 13 and 14can
be used with a quad coil for slightly higher recovered audio.
See Figures 10 through 13 for additional information.
Since adding a matching circuit to the RF input increases
the signal level to the mixer, the third order intercept (TOI)
point is better with an unmatched input (50 n from Pin 21 to
Pin 22). Typical values for both have been included in the
Electrical Characterization Table. TOI measurements were
taken at the pins with a high impedance probe/spectrum
analyzer system. TtJe first mixer input impedance was
measured at the pin with a network analyzer.
Figure 1a. MC13135 Test Circuit
r-----"""'-....-------,
Vee
1
241
11
Varicap~
~
*0.1
1
1.0k
221
0.001
1-----=:..;----1~ 62pF
*
~
0.211H
0.01
-=
RF
Input
-=
Caramie
Filter
10.7 MHz
360
II
39k
0.1~
0.1
*
1
1
L ___ _ _________ .J
~
Figure 1b. MC13136 Quad Detector Test Circuit
0.1 ~
8-216
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
Figure 2. Supply Current versus Supply Voltage
6.0
5.0
l
~
----
4.0
a::
a::
:::>
u
3.0
c..
c..
2.0
~
1.0
~
iil
/
o
o
~
~
~
U
25
20
15
if.
10
~
~
:!l'
RFin = 49.7 MHz
fMOD = 1.0 kHz
fDEV = ± 3.0 kHz
"I
1
--
~ 1200
VCC=4.0V
1000 f - - RFin = 49.67 MHz
fMOD= 1.0 kHz
fDEV = ±3.0 kHz
- 800
if
t
~O
-
:::> 600
~
V
J
1.0
2.0
3.0
4.0
5.0
6.0
7.0
400
~
200
-140
8.0
V
V
V
-120
-80
-100
-
V
-60
-40
Vcc, SUPPLY VOLTAGE (V)
RF INPUT (dBm)
Figure 4. Varactor Capacitance, Resistance
versus Bias Voltage
Figure 5. Oscillator Frequency
versus Varactor Bias
RJ=50MH~
--
,cp, f= 150 MHz
.......
~
.............
10
z
~ ¥ 47.0
~
~
if.
:::>
ifi
u.
...:
4.0
f-
2.0
Rp, f= 150 MHz
2.0
2.5
3.0
3.5
47.5
6.0 a::
i:d
1.5
-20
48.0
~
8.0 ~
-
5.0
1.0
Cf
w
u
cp, f= 50 MHz
~ o
Ii.
0.5
u
~~
II
if.
C3
I
...-
Figure 3. RSSI Output versus RF Input
1400
~
:!l'
~
w
~
o
00';\
II
,----------1...--5
46.0
45.5
5
4.0
-
O.61 11H
46.5
@
45.0
1.0
Ii.
a::
4.0
5.0
VB, VARACTOR BIAS VOLTAGE, VPin24 to VPin 23 (Vdc)
VB, VARACTOR BIAS VOLTAGE (Vdc)
Figure 6. Signal Levels versus RF Input
Figure 7. Signal + Noise, Noise, and
AM Rejection versus Input Power
6.0
10
S+N
10r---r---r-~r-~--~--~--~--~
I
-10r---+---~---r---+--~~~~~~"~
ffi
~ ~Or---+---~---r~~~~~~~--+---~
c..
-90
-80
-70
-60
-50
-40
RFin, RF INPUT (dBm)
MOTOROLA ANALOG IC DEVICE DATA
-30
-20
-10
~
a::
-20
~
-30
~
Z -40
..............
~
"-~
Z
VCC = 4.0 Vdc
it, -50 r- RFin = 49.67 MHz
-60 r- fMOD = 1.0 kHz
fDEV = ±3.0 kHz
-70
-130
-90
-110
S+N30%AM
""
--
"'-.N
-70
-50
-30
RFin, RF INPUT (dBm)
8-217
MC13135' MC13136
Figure 8. Op Amp Gain and Phase
versus Frequency
50
r"--r-
120
i'
Phase
ain"
~
10
~
0
z
:--...
.i -10
\
160
\
....
.... 4 ~
\
-30
-50
10k
so
....
30
100k
100M
Figure 9. First Mixer Third Order.lntermodulation
(Unmatched Input)
10M
20r---~---"r---~---"---.,
ffi
w
1£e.
~
~
240 GS
200
0-
..,.
-100
2S0
~----'-----''------'-----'-----'
-100
-so
-60
-40
-20
" FREQUENCY (Hz)
RF INPUT (dBm)
Figure 10. Recovered Audio versus
Deviation for MC13135
Figure 11. Distortion versus
Deviation for MC13135
2000,--,-------;:;------r----,.-----.,
R=6SkO
II
O~---~---~----~---~
±1.0
±3.0
±S.O
±7.0
±9.0
±3.0
±5.0
±7.0
±9.0
'DEY, DEVIATION (kHz)
'DEV, DEVIATION (kHz)
Figure 12. Recovered Audio versus
Deviation for MC13136
Figure 13. Distortion. versus
Deviation for MC13136
1000,--,----;;::-::------r----,----,--.,
C
10
z
0
i'iS:. sOO
~
~
en
Q
c
15
~
()
Z
I
0
:z;
a:
..:
:I:
~
~
~
~
ci
0L-__- l_ _ _ _
±M
±U
±M
~
_ _ _ _L __ _- L____
±M
±n
'DEV, DEVIATION (kHz)
8-218
~
±M
__
~
±9.0
:I:
I-
0
±3.0
±4.0
±5.0
±6.0
±7.0
'DEV, DEVIATION (kHz)
±S.O
±9.0
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
CIRCUIT DESCRIPTION
The MC13135/13136 are complete dual conversion
receivers. They include two local oscillators, two mixers, a
limiting IF amplifier and detector, and an op amp. Both
provide a voltage buffered RSSI with 70 dB of usable range,
isolated tuning diode and buffered LO output for PLL
operation, and a separate VCC pin for the first mixer and LO.
Improvements have been made in the temperature
performance of both the recovered audio and the RSS!.
VCC
Two separate VCC lines enable the first LO and mixer to
continue running while the rest of the circuit is powered down.
They also isolate the RF from the rest of the internal circuit.
Local Oscillators
The local oscillators are grounded collector Colpitts, which
can be easily crystal-controlled or VCO controlled with the
on-board varactor and external PLL. The first LO transistor is
internally biased, but the emitter is pinned-out and IQ can be
increased for high frequency or VCO operation. The collector
is not pinned out, so for crystal operation, the LO is generally
limited to 3rd overtone crystal frequencies; typically around
60 MHz. For higher frequency operation, the LO can be
provided externally as shown in Figure 16.
Buffer
An amplifier on the 1st LO output converts the
single-ended LO output to a differential signal to drive the
mixer. Capacitive coupling between the LO and the amplifier
minimizes the effects of the change in oscillator current on
the mixer. Buffered LO output is pinned-out at Pin 3 for use
with a PLL, with a typical output voltage of 320 mVpp at VCC
= 4.0 V and with a 5.1 k resistor from Pin 3 to ground. As seen
in Figure 14, the buffered LO output varies with the supply
voltage and a smaller external resistor may be needed for low
voltage operation. The LO buffer operates up to 60 MHz,
typically. Above 60 MHz, the output at Pin 3 rolls off at
approximately 6.0 dB per octave. Since most PLLs require
about 200 mVpp drive, an external amplifier may be required.
Figure 14. Buffered LO Output Voltage
versus Supply Voltage
600
I
RPin3 =3.0 kQ
500
~-
c..
>0.
E.. 400
~
-O
300
200
./
/'"
/"
~
..... .......
100
2.5
3.0
-----~
..- .....
3.5
4.0
~
--
Mixers
The first and second mixer are of similar design. Both are
double balanced to suppress the LO and input frequencies to
give only the sum and difference frequencies out. This
configuration typically provides 40 to 60 dB of LO
suppression. New design techniques provide improved mixer
linearity and third order intercept without increased noise.
The gain on the output of the 1st mixer starts to roll off at
about 20 MHz, so this receiver could be used with a 21 MHz
first IF. It is designed for use with a ceramic filter, with an
output impedance of 330 n. A series resistor can be used to
raise the impedance for use with a crystal filter, which
typically has an input impedance of 4.0 kn. The second mixer
input impedance is approximately 4.0 kn; it requires an
external 360 n parallel resistor for use with a standard
ceramic filter.
Limiting IF Amplifier and Detector
The limiter has approximately 110 dB of gain, which starts
rolling off at 2.0 MHz. Although not designed for wideband
operation, the bandwidth of the audio frequency amplifier has
been widened to 50 kHz, which gives less phase shift and
enables the receiver to run at higher data rates. However,
care should be taken not to exceed the bandwidth allowed by
local regulations.
The MC13135 is designed for use with an LC quadrature
detector, and does not have sufficient drive to be used with a
ceramic discriminator. The MC13136 was designed to use a
ceramic discriminator, but can also be run with an LC quad
coil, as mentioned in the Test Circuit Information section. The
data shown in Figures 12 and 13 was taken using a muRata
CDB455C34 ceramic discriminator which has been specially
matched to the MC13136. Both the choice of discriminators
and the external matching circuit will affect the distortion and
recovered audio.
RSSIIOpAmp
The Received Signal Strength Indicator (RSSI) on the
MC13135/13136 has about 70 dB of range. The resistor
needed to translate the RSSI current to a voltage output has
been included on the internal circuit, which gives it a tighter
tolerance. A temperature compensated reference current
also improves the RSSI accuracy over temperature. On the
MC13136, the op amp on board is connected to the output to
provide a voltage buffered RSS!. On the MC13135, the op
amp is not connected internally and can be used for the RSSI
or as a data slicer (see Figure 17c).
RPin3 =5.1 kQ
4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (Vdc)
MOTOROLA ANALOG IC DEVICE DATA
8-219
..
I
MC13135 MC13136
Figure 15. PLL Controlled Narrowband FM Receiver at 46149 MHz
MC13135
VCC
~0.1
lOOk
2.7k
SOOp 500p
O$~~'P
47k
1.0~
0.Q1
5.0 PI
":'
":'
22
3
":' 0.001
21
VCCl
0.1
.r
VOO
DO
01
02
03
VSS
0.2 J,lH
0.01~
4
OSC OSC
Out
In
~~~~
p~
3.0p
11so
":'
Input
":'
Ceramic
Filter
10.7 MHz
Finl
POl
P02
LO
~0.1
18
360
Fin2
MCl45166
Recovered
Audio
10
0.1
II
Limiter
10k
11
12
0.1~
RSSI
Output
14
13
Figure 16. 144 MHz Single Channel Application Circuit
1st LO External Oscillator Circuit
Preamp for MC13135 at 144.455 MHz
VCC
*
r-~--~--~--~~+
15k
L1
1.0J,lF
12p
lOOp
1.0k
8-220
470
01 - MPS5179
Xl - 44.585 MHz 3rd Overtone
Series Resonant Crystal
L1 - 0.078 J,lH Inductor
(Coilcraft Part # 141Hl2J08)
01- MPS5179
L2- 0.05J,lH
L3- 0.07J,lH
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
Figure 17a. Single Channel Narrowband FM Receiver at 49.7 MHz
MC13135
VCC
24
23
I+------'==+---I;;:n
22
Buffered LO 4---j----I1-----:.,-:--.-t-=---==----'
Output
0.001
21
0.01*
62 PF( RF Input
I 150 P 50 n Source
0.21lH
.".""
20
Ceramic
Filter
10.7 MHz
360
Recovered
10
0.1
:J
0.1
>--1--'W\-.....- - - - - - I - - _ Audio
Limiter
10k
11
'---'"'+_0---------1-_
12
0.1*
RSSI
Output
14
13
455 kHz
Quad Coil
Figure 17b. PC Board Component View
NOTES: 1. 0.2 I!H tunable (unshielded) inductor
2. 39 MHz Series mode resonant
3rd Overtone Crystal
3. 1.5 I!H tunable (shielded) inductor
4. 10.245 MHz Fundamental mode crystal,
32pF load
5. 455 kHz ceramic filter, muRata CFU 4556
or equivalent
6. Quadrature coil, Toko 7MC-8128Z (7mm)
or Toko RMG-2A6597HM (1Omm)
7. 10.7 MHz ceramic fiRer, muRataSFE10.7MJ-A
or equivalent
Figure 17c. Optional Data Slicer Circuit
(Using Internal Op Amp)
vcc
1.0M
MOTOROLA ANALOG IC DEVICE DATA
8-221
MC13135 MC13136
Figure 18. PC Board So.lder Side View
(Circuit Side View)
II
Figure 19. PC Board Component View
NOTES: 1. 0.21tH tunable (unshielded) inductor
2. 39 MHz Series mode resonant
3rd Overtone Crystal
3. 1.5 IlH tunable (shielded) inductor
4. 10.245 MHz Fundamental mode crystal,
32pF load
5. 455 kHz ceramic IiIter, muRata CFU 4556
or equivalent
6. Ceramic discriminator, muRata CDB455C34
or equivalent
7. 10.7 MHz ceramic finer, muRata SFE10.7MJ-A
or equivalent
8-222
MOTOROLA ANALOG IC DEVICE DATA
MC13135 MC13136
Figure 20a. Single Channel Narrowband FM Receiver at 49.7 MHz
MC13136
VCC
24
+
23
1.0*
22
Buffered LO __-+---1If------,:-:-:-~-t__-----'
Output
ri!
0.001
0.01~
-=--=-
Ceramic
Filter
10.7 MHz
~Dr----4--;-~r-~
360
18
-.,...1_7+---"1"".0"'k_......_ _ _ _ _-t--l~ Recovered
/
Audio
10
0.1
62 PF ( RF Input
:c150pF 5OnSource
0.2~H
2_1+--__
L -_ _ _
Lim~er
10k
11
.--t---t-...J
1.._ _+---4~
RSSI
_ _ _ _ _ _ _---I1--_ Oulput
12
0.1~
muRata
455 kHz
Resonator
CDB455C34
Figure 20b. Optional Audio Amplifier Circuit
Speaker
Recovered
Audio
--1
!:::'""-~10~k-ji..:..--~I---'
0.22
51 k
MOTOROLA ANALOG IC DEVICE DATA
8-223
II
Figure 21. MC13135 Internal Schematic
f
18
~ IVCC1
""
'15k
6.0k
12k
2o+-l~
VEE I
I
I
I I
First LO
I I
First Mixer
SecondLO
I I
Second Mixer
Vcc 2
~-----t-$----;7;[;:---r---.--o-16
---.._--VCC2
o==
.....
Co)
.....
Co)
14
UI
3!:
o
.....
~12
.....
Co)
I
VEE
""'"
,
r r
I ,
"T
VEE
OpAmp
13
VCC2
I
I ,
,
VCC2
!I:
a
::II
o
!;
)0
z
§
9
~~~ I
I
I.
I~ J
17
,I
,I ,I
,I
II 11
c;
c
<
m
C;
m
c
~
»
VEE
II
Limiting IF Amplifier
II
Detector and Audio Amplifl8r
This device contains 142 active transistors.
I
VEE
~
iii:
L
Figure 22. MC13136lntemal Schematic
~r~1~h5k~n~I~1~1~II~I~I~1~1~1~1~1~1~1~1I
o
18
6.0k
!j;
)00
12k
~
g
c;
C
2o-t-U---1-\::.
5.0p
~
n
m
C
~
)0
VeE I
First Mixer
FlrstLO
SeconcILO
I I
I I
SeconcIIIiDr
,----~-~r----V~2
~...--
____
~
V~2
$ 'i:f--------t--o 16
3:
--o
Co)
Co)
CII
3:
o
~12
Co)
I
' - - - - - ' - - VeE
I
VeE
OpAmp
13
Vcc2
'"
,
, ,
I I
"
, ,
"
I", I
, ,
V~2
9
~~ ~ I
i
I I~ vi ,I
I
I
17
I ,I ,I II II
"I
VEE
Limiting If Amplifier
14
This device contains 142 active transistors.
II
II
DeII!cIor and Audio AmplIfier
VeE
Co)
Q)
®
MOTOROLA
MC13141
Product Preview
LOW POWER DC - 1.8 GHz
LNA AND MIXER
Low Power DC - 1.8 GHz
LNA and Mixer
SEMICONDUCTOR
TECHNICAL DATA
The MC13141 is intended to be used as a first amplifier and down
converter for RF applications. It features wide band operation, low noise,
high gain and high linearity while maintaining low current consumption. The
circuit consists of a Low Noise Amplifier (LNA), a Local Oscillator amplifier
(LO amp ), a mixer, an Intermediate Frequency amplifier (IFamp) and a dc
control section.
•
•
•
•
•
•
•
•
•
•
8~
Wide RF Bandwidth: DC-1.8 GHz
Wide Mixer Bandwidth: DC-1.8 GHz
Wide IF Bandwidth: DC-100 MHz
Low Power: 7.7 mA @ VCC 2.7-6.5 V
High Mixer Linearity: Pi1.0 dB -2.0 dBm, IP3in 3.0 dBm
Linearity Adjustment Increases IP3in (Not Available in SOIC8)
Up to +20 dBm
Single-Ended 50 n Mixer Input
Double Balanced Mixer Operation
Single-Ended 800 n Mixer Output
Single-Ended 50 n LO Input
=
=
1
01 SUFFIX
PLASTIC PACKAGE
CASE 751
(So-a)
=
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
•
ORDERING INFORMATION
Operating
Temperature Range
Device
20
Package
MC13141D1
FTBSUFFIX
PLASTIC PACKAGE
CASE 976
(ThlnQFP)
so-a
TA = -40° to +85°C
MC13141D
MC13141FTB
1
S0-14
TQFP-20
PIN CONNECTIONS
TQFP-20
S0-14
so-e
~ ~
w
8
w w
w u..
a:
>
>
RFout
Vee
RFout
Enable
RFin
Vee
RFin
VEE
LO
VEEMx
Mix Lin
eont
RFm
IF
VEE
RFm
VEE
Vee IF
VEE 7
VEE
VEELO
IF
This device contains 161 active transistors.
8-226
9
w
w
>
~
w U
~.;?
MOTOROLA ANALOG IC DEVICE DATA
MC13141
MAXIMUM RATINGS (TA
=25°C, unless otherwise noted.)
Rating
Power Supply Voltage
Operating Supply Voltage Range
Symbol
Value
Unit
VCC
7.0 (max)
Vdc
VCC
2.7-6.5
Vdc
ELECTRICAL CHARACTERISTICS (SOIC8 Package, VCC
Characteristic
=3 0 V, TA =25°C , LOin =-10 dBm @ 950 MHz, IF @ 50 MHz)
Symbol
Min
Typ
Max
Unit
100
-
pA
Supply Current (Power Up)
ICC
-
7.7
-
mA
Amplifier Gain (50 0 Insertion Gain)
S21
-
12
-
dB
Amplifier Reverse Isolation
S12
-
-33
dB
rln amp
-
-10
-
-15
-
-15
-
dBm
-5.0
-
dBm
Supply Current (Power Down)
Amplifier Input Match
Amplifier Output Match
ICC
rout amp
Amplifier 1.0 dB Gain Compression
Pin-l.0dB
Amplifier Input Third Order Intercept
IP3in
Amplifier Gain
GNF
@
N.F. (Application Circuit)
17
-
dB
-
dB
15
-
dB
-
=RL =800 0)
Mixer Power Conversion Gain (Rp =RL =800 0)
VGC
PGC
-
7.0
Mixer Input Match
rinM
-
-20
Mixer Vo~age Conversion Gain (Rp
Mixer SSB Noise Figure
NF
NFSSBM
Mixer 1.0 dB Gain Compression
P11L1.0dBM
Mixer Input Third Order Intercept
IP31nM
Mixer 3 dB RF Bandwidth
Mx-3dBBW
-
16.0
1.8
-
GHz
-10
-
dBm
-20
-
dB
-
dB
-
dB
dB
LOin
-
PRFIn-RFln
-
-13
PRFout-RFm
-
-30
PLO-IF
-
-25
dB
PLQ-RFm
-
-50
-
PRFm-IF
-
-50
dB
PRFrn-RFln
-
-
-25
-
dB
PLO-RFin
LO Feedthrough to RFm
Mixer RF Feedthrough to IF
MOTOROLA ANALOG IC DEVICE DATA
dBm
-30
LO Feedthrough to RFin
Mixer RF Feedthrough to RFln
dB
-
rinLO
LO Feedthrough to IF
dB
-3.0
LO Input Match
RFout Feedthrough to RFm
dB
dBm
-10
LO Drive Level
RFln Feedthrough to RFm
dB
1.8
-
Amplifier Noise Figure (50 0)
dB
dB
8-227
II
MC13141
CIRCUIT DESCRIPTION
figure and gain. Input and output matching may be achieved
at various frequencies using few extemal components (see
Application Circuit). Matching the LNA for maximum stable
gain (MSG) yields noise performance within a few tenths of a
dB of the minimum noise figure. Typical performance at
1.0 GHz is 17 dB gain and 1.8 dB noise figure for Vee at
3.0 to 5.0 Vdc.
General
The MC13141 Is a low power LNA, double-balanced
mixer. This device is designated for use as the front-end
section in analog and digital FM systems such as Digital
European Cordless Telephone (DECT), PHS, PCS, Cellular,
UHF and 800 MHz Special Mobile Radio (SMR), UHF
Family Radio Services and 902 to 928 MHz cordless
telephones. It features a mixer linearity control to preset or
auto preset or auto program the mixer dynamic range, an
enable function and buffered IF output for increased overall
gain. Further details are covered in the Pin Function
Description which shows the equivalent internal circuit and
external circuit requirements.
Mixer
The mixer is a double-balanced four quadrant multiplier
biased class AB allowing for programmable linearity control
via an external current source. An input third order intercept
point of 20 dBm may be achieved. All 3 ports of the mixer are
designed to work up to 1.8 GHz. The mixer has a 50 n
single-ended RF input and IF output buffer amplifier. The
linear gain of the mixer is approximately 7.0 dB with a SSE)
noise figure of 16 dB.
Current Regulation/Enable
Temperature compensating voltage independent current
regulators are controlled by the the enable function in which
"high" powers up the IC.
Local Oscillator
It requires an external local oscillator source at -10 dBm
input level to maximize the mixer gain.
Low Noise Amplifier (LNA)
The LNA is internally biased at low supply current
(approximately 2.0 mA emitter current) for optimal noise
PIN FUNCTION DESCRIPTION
II
14 Pin
20 Pin
SOIC
TQFP
Symbol
4
6
RFin
Equivalent Internal Circuit
(20 Pin TQFP)
I
I
I
I
I
6I
RFOUI
2,3
4,5
VCC
RFin
2,3,7
1,5
VEE
2,3,7
RFlnput
The input is the base of an NPN low noise amplifier.
Minimum extemal matching is required to optimize the
Input return loss and gain.
Vref1
VCC - Positive Supply Voltage
Two Vec pins are provided for the Local Oscillator and LO
Buffer Amplifier. The operating supply voltage range is
from 2.7 Vdc to 6.5 Vdc. In the PCB layout, the VCC trace
must be kept as wide as feasible to minimize inductive
reactances along the trace. VCC should be decoupled to
VEE at the IC pin as shown in the component placement
view.
I
I
I
VEE - Negative Supply
VEE pin is taken to an ample dc ground plane through a
low impedance path. The path should be kept as short as
possible. A two sided PCB Is Implemented so that ground
returns can be easily made through via holes.
andS
14
7
RFOutput
The output is from the collector of the LNA. As shown in
the 926 MHz application receiver the output is conjugately
matched with a shunt L, and series Land C network.
RFout
11
LO
I
I
I
I
I
1d
LO
8-228
Functional DeecrlptionlExternal
Circuit Requlremente
I
I
I
I
I
I
I
Vref3
Local Oscillator Input
50 (} single-ended buffered LO input.
33
1.
1.
1
33
.~
.=
MOTOROLA ANALOG IC DEVICE DATA
MC13141
PIN FUNCTION DESCRIPTION (continued)
14 Pin
SOIC
20 Pin
TQFP
5,6
9,10,
12,14
Equivalent Internal Circuit
(20 Pin TQFP)
Symbol
13
VEE - Negative Supply
These pins are VEE supply for the IF and La. In the
application PC board these pins are tied to a common
VEE trace with other VEE pins.
VEE
Vj:e
IF
2:
~~
i
13
8
Functional De.crlptlon/External
Circuit Requirement.
Vrefj!'OVbS
800
IF
IF Output
The IF Is a 800 n slngle-ended output which must be
externally matched to 50 n for optimal performance.
J~
9,10,
12,14
~ VEE
10
11
16
17
RFm
Mix Lin
Cont
I
I
I
I
I
I
I
"
"
~VEE
161
RFm I
I
"
",Ir
!
Mix Un
eont I
13
lB,19
20
I
I
I
I
I
I
I
VEE
I
I
I
EN
20
EN
!
I
I
I
I
¥4
~
171
12
Mixer RF Input
The mixer Input Impedance Is broadband 50 n for
applications up to 1.B GHz. It easily Interfaces with a RF
ceramic filter as shown In the application schematic. The
pin dc bias Is set at 1.0 Vbe.
Vee
33
~Il-
<
",~
~l
~~
'y-
n
VEE - Negative Supply
These pins are VEE supply for the mixer input.
400 I1A
~
~ee
33
~
,Ir
Mixer Linearity Control
The mixer linearity control circuit accepts approximately
oto 2.3 mA control current to set the dynamic range of the
mixer. An Input Third Order Intercept Point, IiP3 of
20 dBm may be achieved at 2.3 mA of control current
(approximately 7.0 mA of additional supply current). The
pin dc bias Is set at 2.0 Vbe.
~
Enable
The device Is enabled by pulling up to VCC or greater than
2.0Vbe.
+
2.0Vbe _
~
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The PC board accommodates ali SMT components on the
circuitside (see Circuit Side Component Placement View).
This evaluation board will be discussed and referenced in
this section.
MOTOROLA ANALOG IC DEVICE DATA
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to use
components from various manufacturers and coil types. The
circuit side placement view is illustrated for the components
specified In the application circuit. The application circuit
schematic specifies particular components that were used to
achieve the results given and specified in the tables but
alternate components of the same Q and value should give
similar results.
8-229
I
II
MC13141
Figure 1. MC13141 01 Application Circuit (881.5 MHZ)
Vee
881.5 MHz
AF
16 P
>--fi---i
I
Inpui
~
SMA
100~11~HZ
798.5 MHz
LO Input
)>--t9-+-----I) 1------1
.1
.±
r
100p
SMA
in n
10P
I
Output
':'
NOTE: '50 £1 Mlcrostrip Transmission Line; length shown in Figure 2.
Figure 2. Circuit Side Component Placement View
MC13141D1 Rev A
•
NOTES: 881.5 MHz SAW filter in the ceramic surface mount package Is available from several sources: Siemens part # B39881-84608-Z010 Is an example.
Other supplie~ include Toko and Murata.
The PCB accommodates ceramic dielectric liners for applications in Cellular. DECT, PHS and ISM bands at 902-928 and 2.4-2.5 GHz. Toko makes a
lull line-up covering th~ ,above bands.
The PCB may be used without an image flijer; ac couple the LNA to the mixer. Traces are provided on the PCB to evaluate the LNA and mixer
separately. The component placement view shows extemal circuit components used in the 881.5 MHz application circulI. It is necessary to cut a section
in the trace before placing the 0.9 pF capacitor. Capac~ors should be 0805 size; the 6.8 nH inductor is a Toko type LL2012.
8-230
MOTOROLA ANALOG IC OEVICE DATA
MC13141
Figure 3. MC13141 D Application Circuit (881.5)
Vee
881.SMHz
RFlnput
>~
16pr----,
)
SMA
798.5 MHz
LOlnput
>
1000 P
-=
470 nH SMA
83.161 MHz
~IFOUtput
~
-i
SMA
NOTE:
lOp
::t: .
·500 Microstrip Transmission Line; length shown in Figure 4.
Figure 4. Circuit Side Component Placement View
NOTES: BBI.S MHz SAW lilter in the ceramic surface mount package is available lrom several sources: Siemens part # B39BBI-B460B-ZOI 0 is an example.
Other suppliers include Taka and Murata.
The PCB accommodates ceramic dielectric lilters lor applications in Cellular, DECT, PHS and ISM bands at 902-92B and 2.4-2.5 GHz. Taka makes a
lull line-up cQvering the above bands.
The PCB may be used without an image lilter; ac couple the LNA to the mixer. Traces are provided on the PCB to evaluate the LNA and mixer
separately. The component placement view shows external circuit components used in the 881.5 MHz application circuit. It is necessary to cut a section
in the trace belore placing the 0.9 pF capacttor. Capacitors shOUld be 0805 size; the 6.B nH inductor is a Taka type LL2012.
MOTOROLA ANALOG IC DEVICE DATA
8-231
MC13141
Input Matching/Components
where:
F1 = the Noise Factor of the MC13142 LNA
G1 = the Gain of the LNA
F2 = the Noise factor of the RF Ceramic Filter
G2 = the Gain of the Ceramic Filter
F3 = the Noise factor of the Mixer
It is desirable to use a RF ceramic or SAW filter before
the mixer to provide image frequency rejection. The filter is
selected based on cost, size and performance tradeoffs.
Typical RF filters have 3.0 to 5.0 dB insertion loss. The PC
board layout accommodates both ceramic and SAW RF
filters which are offered by various suppliers such as
Siemens, Toko and Murata. Interface matching between the
LNA, RF filter and the mixer will be required. The interface
matching networks shown in the application circuit are
designed for 50 Q interfaces.
The LNA is conjugately matched to 50 g input and output
at 3.0 Vdc V CC. 17 dB gain and 1.8 dB noise figure is
typical at 881.5 MHz. The mixer measures 7.0 dB gain and
16 dB noise figure as shown in the application circuil.
Typical insertion loss of the Siemens SAW filter is 3.0 dB.
Note: the above terms are defined as linear relationships
and are related to the log form for gain and noise figure by the
following:
F = Log -1 [(NF in dB)/10] and similarly
G = Log -1 [(Gain in dB)/10]
Calculating in terms of gain and noise factor yields the
following:
F1 = 1.51 ; G1 = 50.11
F2=1.99 ; G2=0.5
F3= 39.8
System Noise Considerations
The block diagram shows the cascaded noise stages of
the MC13141 in the front-end receiver subsystem; it
represents the application circuit. In the cascaded noise
analysis the system noise equation is:
Thus, substituting in the equation for subsystem noise
factor:
Fsubsystem = 3.08 ; NFsubsystem = 4.9 dB
Overall Subsystem Gain = 21 dB
Fsystem = F1 + [{F2 -1)/G1] + [(F3-1)] / [(G1)(G2)]
Figure 5. Front-End Subsystem Block Diagram for Noise Analysis
II
fRF = 881.5 MHz
Noise
Source
G1=17dB
NF1 = 1.8dB
Seimens
Saw Filter
NF
Meter
G2=-3.0dB
NF2 =3.0 dB
IF Output
flF = 83.16 MHz
fLo = 798.339 MHz
I
G~s=21 dB
NFsys = 4:9 dB
8-232
MOTOROLA ANALOG IC DEVICE DATA
MC13141
Figure 6. Circuit Side View
MC13141D1 Rev A
LNA
Output
Mixer
Input
IF
Output
Gnd
g,
••••
LNA'"
Input'"
•
II
LO
Input
NOTES: Critical dimensions are 50 mil centers lead to lead in 80-8 footprint.
Also line widths to labeled ports excluding VCC are 50 mil (0.050 inch).
FR4 PCB, 1/32 inch.
Figure 7. MC13141D1 Rev A -Ground Side View
NOTE:
FR4 PCB, 1/32 inch.
MOTOROLA ANALOG IC DEVICE DATA
8-233
MC13141
Figure 8. Circuit Side View
IF
Output
Vee
NOTES: CrHical dimensions are 50 mil centers lead to lead in 50-14 footprint.
Also line widths to labeled ports excluding VCC are 50 mil (0.050 inch).
FR4 PCB, 1/32 inch.
Figure 9. Ground Side View
8-234
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13142
Product Preview
Low Power DC - 1.8 GHz
LNA, Mixer and VCO
The MC13142 is intended to be used as a first amplifier, voltage controlled
oscillator and down converter for RF applications. It features wide band
operation, low noise, high gain and high linearity while maintaining low
current consumption. The circuit consists of a Low Noise Amplifier (LNA), a
Voltage Controlled Oscillator (VCO), a buffered oscillator output, a mixer, an
Intermediate Frequency amplifier (IFamp) and a dc control section. The wide
mixer IF bandwidth allows this part also to be used as an up converter and
exciter amplifier.
LOW POWER DC - 1.8 GHz
LNA, MIXER and VCO
SEMICONDUCTOR
TECHNICAL DATA
• Wide RF Bandwidth: DC-1.8 GHz
• Wide LO Bandwidth: DC-1.8 GHz
• Wide IF Bandwidth: DC-1.8 GHz
• Low Power: 13 mA @ VCC
=2.7-6.5 V
• High Mixer Linearity: Pi1.0 dB = +3.0 dBm
• Linearity Adjustment Increases IP3in Up to +20 dBm
o SUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
• Single-Ended 50 n Mixer Input
• Double Balanced Mixer Operation
• Open Collector Mixer Output
• Single Transistor Oscillator with Collector, Base and Emitter Pinned Out
• Buffered Oscillator Output
•
• Mixer and Oscillator Can be Enabled Independently in TQFP-20
Package Only
20
ORDERING INFORMATION
Operating
Temperature Range
Device
FTBSUFFIX
PLASTIC PACKAGE
CASE 976
(ThinOFP)
Package
MC131420
S0-16
TA = -40° to +85°C
MC13142FTB
1
TOFP-20
PIN CONNECTIONS
TOFP-20
50-16
~
EN
RFOUI
RFin
Vcc
vEE
w
Mix Lin Coni
RFtn
OseE
RFm
VEE
OseB
vEE
-s
u...0
8
:5_
.~a
:z
w
a: > :::;;<.>
<.>
<.>
""
~
>
:0
<.>
<.>
>
w
w
>
This device contains 176 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
8-235
MC13142
MAXIMUM RATINGS (TA - 25°C unless otherwise noted)
Symbol
Value
Unit
Power Suppiy Voltage
Rating
VCC
7.0 (max)
Vdc
Operating Supply Voltage Range
VCC
2.7-6.5
Vdc
NOTE: ESO dala available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 3.0 V, TA = 25°C, LOin = -10 dBm @ 950 MHz, IF @ 50 MHz.)
Characteristic
Symbol
Supply Current (Power Down)
ICC
Supply Current (Power Up)
ICC
Amplifier Gain (50 0 Insertion Gain)
S21
Amplifier Reverse Isolation
S12
Amplifier Input Match
~in
Typ
Max
Unit
-
100
13.5
-
mA
pA
12
-
dB
-33
-
dB
rinamp
-
-10
-
dB
rout amp
-
-15
Amplifier 1 .0 dB Gain Compression
PirL1.0dB
-
-15
-
dBm
Amplifier Input Third Order Intercept
IP3in
-5.0
-
dBm
Amplifier Output Match
Amplifier Gain @ N.F.
GNF
Mixer Voltage Conversion Gain (Rp = RL = 800 0)
VGC
Mixer Power Conversion Gain (Rp = RL = 800 0)
PGC
-
rinM
-
-20
-
3.0
Amplifier Noise Figure (Application Circuit)
Mixer Input Match
Mixer SSB Noise Figure
NF
NFSSBM
Mixer 1.0 dB Gain Compression
PirL1.0dBM
Mixer Input Third Order Intercept
IP31nM
Oscillator Buffer Drive (50 0)
PVCO
Oscillator Phase Noise @ 25 kHz Offset
RFin Feedthrough to RFm
RFoul Feedthrough to RFm
LO Feedthrough to IF
N
PRFin-RFm
PRFout-RFm
PLD-IF
LO Feedthrough to RFin
PLD-RFin
LO Feedthrough to RFm
PLD-RFm
Mixer RF Feedthrough to IF
PRFm-IF
Mixer RF Feedthrough to RFin
8-236
PRFm-RFin
1.8
17
9.0
-3.0
12
-1.0
-
dB
dB
dB
dB
dB
dB
dB
-
dBm
dBm
-
-16
-90
-
dBcJHz
-
-35
dB
-
-35
-
-25
-
-25
-
-35
-35
-35
dBm
dB
dBm
dBm
dBm
dB
dB
MOTOROLA ANALOG IC DEVICE DATA
MC13142
CIRCUIT DESCRIPTION
General
The MC13142 is a low power LNA, double-balanced
Mixer, and VCO. This device is designated for use as the
frontend section in analog and digital FM systems such as
Digital European Cordless Telephone (DECT), PHS, PCS,
Cellular, UHF and 800 MHz Special Mobile Radio (SMR),
UHF Family Radio Services and 902 to 928 MHz cordless
telephones. It features a mixer linearity control to preset or
auto program the mixer dynamic range, an enable function
and a wideband IF so the IC may be used either as a down
converter or an up converter. Further details are covered in
the Pin by Pin Description which shows the equivalent
internal circuit and external circuit requirements.
Current Regulation/Enable
Temperature compensating voltage independent current
regulators are controlled by the enable function in which
"high" powers up the IC.
Low Noise Amplifier (LNA)
The LNA is internally biased at low supply current
(approximately 2.0 mA emitter current) for optimal noise
figure and gain. The LNA output is biased internally with a
600 n resistor to VCC. Input and output matching may be
achieved at various frequencies using few external
components. Matching the LNA for Maximum stable gain
MOTOROLA ANALOG IC DEVICE DATA
(MSG) yields noise performance within a few tenths of a dB
of the minimum noise figure.
Mixer
The mixer is a double-balanced four quadrant multiplier
biased class AB allowing for programmable linearity control
via an external current source. An input third order intercept
point of 20 dBm may be achieved. All 3 ports of the mixer are
designed to work up to 1.8 GHz. The mixer has a 50 n
single--ended RF input and open collector differential IF
outputs. An on-board Local Oscillator transistor has the
emitter, base and collector pinned out to implement a low
phase noise VCO in various configurations. Additionally, a
buffered LO output is provided for operation with a frequency
synthesizer. The linear gain of the mixer is approximately
o dB with a SSB noise figure of 12 dB in the IF output circuit
configuration shown in the application example.
Local Oscillator
The on-chip transistor operates with coaxial transmission
line or LC resonant elements to over 2.0 GHz. Biasing is
done with a temperature compensated current source in the
emitter and a collector to base internal resistor of 7.6 kn;
however, an RFC from VCC to base is recommended. The
application circuit shows a voltage controlled Clapp oscillator
operating at center frequency of 975 MHz.
8-237
MC13142 .
PIN FUNCTION DESCRIPTION
'Pin
16 Pin
SOIC
20 Pin
TQFP
4
5
Equivalent Internal Circuit
(20 Pin TQFP)
Symbol
Description
EN
EOsc
Enable, E Osc
In S0-16, both enables, (for the Oscillator/LO
Buffer and LNAlMixer) are bonded to Pin 1. In the
TQFP, two pins are provided, Pin S, E Osc enables
the OSCillator and buffer while Pin 4, EN enables
the lNAlMixer.
Enable by pulling up to Vec or to greater than
2.0VBE·
2
6
RFin
600
Vref2
RFOUII
3
7,8·
VEE
6
II
RF Input
The input is the base of an NPN low noise
amplifier. Minimum external matching is required to
optimize the input return loss and gain.
Vee
1
1
31
VEE - Negative Supply
VEE pin is taken to an ample dc ground plane
through a low impedance path. The path should be
kept as short as possible. A two sided PCB is
implemented so that ground returns can be easily
made through via holes.
1
1
1
RFin 1
71
16
3
RFoUI
'E~
RF Output
The output is from the collector of the lNA; it is
internally biased with a 600 Q resistor to Vcc. As
shown in the 926 MHz application receiver the
output is conjugately matched with a shunt L, and
series land C network.
81
VEE 1_
1 4
S
6
9
10
11
OscE
OscB
OscC
+rnA
1.5
11
6
8
12
14
Supply Voltage (VCC)
Two VCC pins are provided for the Local Oscillator
and LO Buffer Amplifier. The operating supply
voltage range is from 2.7 Vdc to 6.S Vdc. In the
PCB layout, the VCC trace must be kept as wide as
feasible to minimize inductive reactances along the
trace. VCC should be decoupled to VEE at the IC
pin as shown in the component placement view.
VCC
VCC
1 Vee
13
7
13
I
I
FO
LOBuff
rnA
Vee
8-238
On-Board VCO Transistor
The transistor has the emitter, base and collector +
V CC pins available. Internal biasing which is
compensated for stability over temperature is
provided. It is recommended that the base pin is
pulled up to Vec through an RFC chosen for the
particular oscillator center frequency. The
application circuit shows a modified Colpitts or
Clapp oscillator configuration and its design is
discussed in detail in the application section.
Local Oscillator Buffer
This is a buffered output providing -16 dBm
(SO Q termination) to drive the fin pin of a PLL
synthesizer. Impedance matching to the
synthesizer may be necessary to deliver the
optimal signal and to improve the phase noise
performance of the VCO.
MOTOROLA ANALOG IC DEVICE DATA
MC13142
PIN FUNCTION DESCRIPTION (continued)
Pin
16 Pin
SOIC
20 Pin
TQFP
9,12
15, 18, 19
10,11
16,17
Equivalent Internal Circuit
(20 Pin TQFP)
Symbol
VEE
I Vee
I
IA
I ~
IF-,IF+
17
IF+
13
20
Vee
~
II ~
T
IF Output
The IF is a differential open collector configuration
which designed to use over a wide frequency range
for up conversion as well as down conversion.
Differential to single-ended circuit configuration
and matching options are discussed in the
application section. 6.0 dB of additional Mixer gain
can be achieved by conjugately matching at the
desired IF frequency.
VTl
Mixer RF Input
The mixer input impedance is broadband 50 n for
applications up to 1.8 GHz. It easily interfaces with
a RF ceramic filter as shown in the application
schematic.
J
16
IF-
I
15 ~
-=-
:18~
I
I
I
I
Description
VEE, Negative Supply
These pins are VEE supply for the mixer IF output.
In the application PC board these pins are tied to a
common VEE trace wnh other VEE pins.
VEE
RFm
Vee
,
,
-=-
20
14
1
Mix Lin
Cont
+
33
VEE
RFm
1
MixLin
eont
MOTOROLA ANALOG IC DEVICE DATA
J
i
I
I
I
I
I
I
I
I
I
?
~
-=-
33
Mixer Linearity Control
The mixer linearity control circuit accepts
approximately 0 to 2.3 mA control current to set
the dynamic range of the mixer. An Input Third
Order Intercept Point, IIP3 of 20 dBm may be
achieved at 2.3 mA of control current
(approximately 7.0 mA of additional supply
current).
+
400~
8-239
MC13142
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The PC board accommodates all SMT components on the
circuit side (see Circuit Side Component Placement View).
This evaluation board will be discussell and referenced in
this section.
Component Selection
The evaluation PC board is designed to accommodate
specific components. while also being versatile enough to
use components from various manufacturers. The circuit
side placement view is illustrated for the components
specified in the application circuit. The application circuit
schematic specifies particular components that were used to
achieve the results given and specified in the tables but
alternate components of the sameC and value should give
equivalent results.
Figure 1. Application Circuit
(926.5 MHz)
Vcc
PC RotarySW
51
.-.
VControl
3.6
PI
-=-
1 0 m r--------:---tt---- 15
af'
~ ~
-6.0 ~
c3
11
20
"
RF FREQUENCY (GHz)
MOTOROLA ANALOG IC DEVICE DATA
'-..
2.0
7.0
~
Vs= 5.0Vdc
fRF = 900 MHz
fLQ = 950 MHz
10
~V
-6.0
2.5
2.0
1/
~
~
i--'
Ilmj)
10-3
rnr
0
-5.0
"'
1en
IIP3(dBm
c3 If 5.0
'"~
4.0
10
Figure 7. IIP3, Gain, Supply Current
versus Mixer Linearity Control Current
.........
6.0
o
0
Figure 6. Noise Figure and Gain
versus RF Frequency
~
o
= 5.0 Vdc
fRF= 900 MHz
fLQ =950 MHz
PLQ=OdBm
Test Circuit
V
RF INPUT POWER (dBm)
$ 13.5
11.5
'r-..
v
V"' ~/ f--
RF INPUT FREQUENCY (GHz)
-4.0
,r
8.0
-8.5
-30
2.5
2.0
15.5
10.5
~
-3.2
-10
10-5
10-4
10-2
MIXER LINEARITY CONTROL CURRENT, IMx Lin Cont (A)
8-247
MC13143
CIRCUIT DESCRIPTION
General
The MC13143 is a double-balanced Mixer. This device is
designated for use as the frontend section in analog and
digital FM systems such as Wireless Local Area Network
(LAN), Digital European Cordless Telephone (DECT), PHS,
PCS, GPS, Cellular, UHF and 800 MHz Special Mobile
Radio (SMR), UHF Family Radio Services and 902 to
928 MHz cordless telephones. It features a mixer linearity
control to preset or auto program the mixer dynamic range,
an enable function and a wideband IF so the IC may be
used either as a down converter or an up converter.
Current Regulation
Temperature compensating voltage independent current
regulators provide typical supply current at 1.0 mA with no
mixer linearity control current.
Mixer
The mixer is a unique and patented double-balanced four
quadrant multiplier biased class AB allowing for
programmable linearity control via an external current
source. An input third order intercept point of 20 dBm may be
achieved. All 3 ports of the mixer are deSigned to work up to
2.4 GHz. The mixer has a 50 n single-ended RF input and
open collector differential IF outputs (see Internal Circuit
Schematic for details). The linear gain of the mixer is
approximately -5.0 dB with a SSB noise figure of 12 dB.
Local Oscillator
The local oscillator has differential input configuration that
requires typically -10 dBm input from an external source to
achieve the optimal mixer gain.
Figure 8. MC13143 Internal Circuit·
IF-
6
5
Vee
IF+
2
4
La-
3
LO+
Vref1
Vee
33
8
Vee
MxLin
ConI
NOTE: .• The MC13143 uses a unique and patented clrcu~ topology.
8-248
MOTOROLA ANALOG IC DEVICE DATA
MC13143
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The PC board is laid out to accommodate all SMT
components on the circuit side (see Circuit Side Component
Placement View).
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to
use components from various manufacturers. The circuit side
placement view is illustrated for the components specified in
the application circuit. The Component Placement View
specifies particular components that were used to achieve
the results shown in the typical curves and tables.
Mixer Input
The mixer input impedance is broadband 50 Q for
applications up to 2.4 GHz. It easily interfaces with a RF
ceramic filter as shown in the application schematic.
Mixer Linearity Control
The mixer linearity control circuit accepts approximately
o to 2.3 mA control current. An Input Third Order Intercept
Point, IIP3 of 20 dBm may be achieved at 2.3 mA of control
current (approximately 7.0 mA of additional supply current).
Local Oscillator Inputs
The differential LO inputs are internally biased at
VCC - 1.0 VeE; this is suitable for high voltage and high gain
operation.
For low voltage operation, the inputs are taken to VCC
through 51 Q.
IF Output
The IF is a differential open collector configuration which is
designed to use over a wide frequency range for up
conversion as well as down conversion.
Input/Output Matching
It is desirable to use a RF ceramic or SAW filter before the
mixer to provide image frequency rejection. The filter is
selected based on cost, size and performance tradeoffs.
Typical RF filters have 3.0 to 5.0 dB insertion loss. The PC
board layout accommodates both ceramic and SAW RF
filters which are offered by various suppliers such as
Siemens, Toko and Murata.
MOTOROLA ANALOG IC DEVICE DATA
Interface matching between the RF input, RF filter and the
mixer will be required. The interface matching networks
shown in the application circuit are designed for 50 Q
interfaces.
Differential to single-ended circuit configuration is shown
in the test circuit. 6.0 dB of additional mixer gain can be
achieved by conjugately matching the output of the
MiniCircuits transformer to 50 Q at the desired IF frequency.
With narrowband IF output matching the mixer performance
is 3.0 dB gain and 12 dB noise figure (see Narrowband 49
and 83 MHz IF Output Matching Options). Typical insertion
loss of the Toko ceramic filter is 3.0 dB. Thus, the overall gain
of the circuit is 0 dB with a 15 dB noise figure.
Figure 9. Narrowband IF Output Matching with
16:1 Z Transformer and LC Network
SMA
I---OH......-(
I
Mixer
RFlnput
SMA
!
II
SMA
(Mixer
RF Input
83.16 MHz
E--9-< IF
10n I
Output
9.2k
8-249
MC13143
Figure 10. Circuit Side Component Placement View
MC13143D
Rev A
II
NOTES: 926.5 MHz preselect dielectric filter is Taka part # 4DFA-926A 10; the 4DFA (2 and 3 pole SMD type) filters are available
for applications in cellular and GSM, GPS, DECT, PHS, PCS and ISM bands at 902-928 MHz, 1.8-1.9 GHz at 2.4-2.5 GHz.
The PCB also accommodates a suriace mount RF SAW filter in an eight or six pin ceramic package for the cellular base and
handset frequencies. Recommended manufacturers are Siemens and Murata.
The PCB may also be used w~hout a preselector fitter; AC coupled to the mixer as shown in the test circuit schematic.
All other external circuit components shown in the PCB layout above are the same as used in the test circuit schematic.
16:1 broadband impedance transformer is mini circu~s part nX16-R3T; it is in the leadless surface mount "TX" package. For a
more selective narrowband match, a low pass filter may be used after the transformer. The PCB is designed to accommodate
lump inductors and capacitors in more selective narrowband matching of the mixer differential outputs to a single...,nded output
at a given IF frequency.
The local oscillator may also be driven in a differential configuration using a coaxial transformer. Recommended sources are the
Toko Balun transformers type B4F, B5FL and B5F (SMD component).
8-250
MOTOROLA ANALOG IC DEVICE DATA
MC13143
Figure 11. Circuit Side View
MC13143D
Rev A
NOTES: Crnical dimensions are 50 mil centers lead to lead in 80--8 footprint.
II
Also line widths to labeled ports excluding VCC are 50 mil.
Figure 12. Ground Side View
MOTOROLA ANALOG IC DEVICE DATA
8-251
®
MOTOROLA.
MC13144
Product Preview
VHF - 2.0 GHz Low
Noise Amplifier with
Programmable Bias
The MC13144 is designed in the Motorola High Frequency Bipolar
MOSIAC yrM wafer process to provide excellent.performance in analog and
digital communication systems. It inclu<;les a cascaded LNA usable up to
2.0 GHz and at 1.B Vdc, with 2 bit digital programming of the LNA bias.
Targeted applications are in the UHF Family Radio Services, UHF and
BOO MHz Special Mobile Radio, BOO MHz Cellular and GSM,. PCS, DECT
and PHS at 1.B to 2.0 GHz and Cordless Telephones in the 902 to 92B MHz
band covered by FCC Title 47; Part 15. The MC13144 offers the following
features:
VHF - 2.0 GHz LOW
NOISE AMPLIFIER WITH
PROGRAMMABLE BIAS
SEMICONDUCTOR
TECHNICAL DATA
• 17 dB Gain at 900 MHz
• 1.4 dB Noise Figure at 900 MHz
• 1.0 dB Compression Point of -7.0 dBm; Input Third Order Intercept
Point of -5.0 dBm
• Low Operating Supply Voltage (1.B to 6.0 Vdc)
• Programmable Bias with Enable 1 and Enable 2
o SUFFIX
PLASTIC PACKAGE
CASE 751
(SQ-8)
• Enable 1 and Enable 2 Programmed High for Optimal Noise Figure and
Gain Associated with NF
• Can Override Enable and Externally Program In Up to 15 rnA
Typical Application as 900 MHz Low Noise Amplifier
En1
PIN CONNECTIONS AND
FUNCTIONAL BLOCK DIAGRAM
En2
1'~RF
,.----
8.2nH
RF
Output
e1.
MOTOROLA ANALOG IC DEVICE DATA
8-255
MC13144
Figure 3. Circuit Side Component Placement View
Figure 4. Circuit Side View
NOTES: Critical dimensions are 50 Mil centers lead to lead in 50-8 footprint.
Also line widths to labeled ports excluding VCC, E1 and E2 are 50 Mil (0.050 inch).
FR4 PCB, 1/32 inch.
8-256
MOTOROLA ANALOG IC DEVICE DATA
MC13144
Figure 5. Ground Side View
LNA in
[!] VCC
[!]
El
[!]
•
•
• •••
•
•• ••• • • •
•
• •
•
[!]
•
••
• ••••
LNA Out
[!]
E2
MC13144D Rev 0
NOTES: FR4 PCB, 1/32 inch.
II
MOTOROLA ANALOG IC DEVICE DATA
8-257
®
MOTOROLA
[
MC13150
Narrowband FMeoilless
Detector IF Subsystem·
NARROWBAND FM COILLESS
DETECTOR IF SUBSYSTEM
The MC13150 is a narrowband FM IF subsystem targeted at cellular and
other analog applications. Excellent high .frequency performance is
achieved, with low cost, through use of Motorola's MOSAIC 1.5™ RF bipolar
process. The MC13150 has an onboard Colpitts VCO for Crystal controlle~
second LO in dual conversion receivers. The mixer is a double balanced
configuration with excellent third order intercept. It is useful to beyond
200 MHz. The IF amplifier is split to accommodate two low cost cascaded
filters. RSSI output is derived by summing the output of both IF sections. The
quadrature detector is a unique design eliminating the comientional tunable
quadrature coil.
Applications for the MC13150 include cellular, CT-1 900 MHz cordless
telephone, data links and other radio systems utilizing narrowband FM
modulation.
• Linear Coilless Detector
• Adjustable Demodulator Bandwidth
• 2.5 to 6.0 Vdc Operation
• Low Drain Current: < 2.0 rnA
• Typical Sensitivity of 2.0 IlV for 12 dB SINAD
• IIP3, Input Third Order Intercept Point of 0 dBm
• RSSI Range of Greater Than 100 dB
• Internal 1.4 kn Terminations for 455 kHz Filters
• Split IF for Improved Filtering and Extended RSSI Range
FOR CELLULAR AND
ANALOG APPLICATIONS
SEMICONDUCTOR
TECHNICAL DATA
24
FTASUFFIX
PLASTIC PACKAGE
CASE 977
(ThlnQFP)
ORDERING INFORMATION
Operating
Temperature Range
Device
FTBSUFFIX
PLASTIC PACKAGE
CASE 873
(ThinQFP)
Package
TQFP-24
MC13150FTA
TA = -40 ° to +85°C
MC13150FTB
TQFP-32
PIN CONNECTIONS
TQFP-24
.E
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W
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9
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8-258
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MOTOROLA ANALOG IC DEVICE DATA
MC13150
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
2,9
Vcc(max)
6.5
Vdc
Junction Temperature
-
TJmax
+150
'c
Storage Temperature Range
-
Tstg
-65to+150
'c
NOTE:
Pin
1. Devices should not be operated at or outside these values. The "Recommended Operating
Limits" provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Pin
TA = 25'C
- 40'C $ TA $ 85'C
2,9
21,31
Symbol
Value
Unit
VCC
VEE
2.5 to 6.0
0
Vdc
MHz
(See Figure 22)
Input Frequency
32
Ambient Temperature Range
Input Signal Level
32
fin
10 to 500
TA
-40to+85
'c
Vin
0
dBm
DC ELECTRICAL CHARACTERISTICS (TA = 25'C, VCC1 = VCC2 = 3.0 Vdc, No Input Signa!.)
Characteristics
Total Drain Current
(See Figure 2)
Condition
Pin
Symbol
Min
Typ
Max
Unit
Vs = 3.0Vdc
2+9
ITOTAL
-
1.7
3.0
rnA
-
2+9
-
-
40
-
nA
Supply Current, Power Down
(See Figure 3)
AC ELECTRICAL CHARACTERISTICS (TA = 25'C, Vs = 3.0 Vdc, fRF = 50 MHz, fLO = 50.455 MHz,
LO Level = -10 dBm see Figure 1 Test Circuit' unless otherwise specified.)
Condition
Pin
Symbol
Min
Typ
Max
Unit
fmod = 1.0 kHz;
fdev = ± 5.0 kHz
32
-
-
-100
-
dBm
RSSI Dynamic Range
(See Figure 7)
-
25
-
-
100
-
dB
Input 1.0 dB Compression Point
Input 3rd Order Intercept Point
(See Figure 18)
-
-
1.0dBC. Pt.
IIP3
-
-11
-1.0
-
dBm
Measured with No IF Filters
-
I:!.BWadj
-
26
-
kHzI/lA
Pin = - 30 dBm;
PLO=-10dBm
32
-
-
10
-
dB
Single-Ended
32
-
-
200
-
g
-
1
-
-
1.5
-
kg
!lA/dB
Characteristics
12 dB SINAD Sensitivity
(See Figure 15)
Coilless Detector Bandwidth
Adjust (See Figure 11)
MIXER
Conversion Voltage Gain
(See Figure 5)
Mixer Input Impedance
Mixer Output Impedance
LOCAL OSCILLATOR
LO Emitter Current
(See Figure 26)
IF & LIMITING AMPLIFIERS SECTION
IF and Limiter RSSI Slope
Figure 7
25
-
-
0.4
-
IF Gain
Figure 8
4,8
-
-
42
-
dB
IF Input & Output Impedance
-
4,8
-
-
1.5
-
kn
Limiter Input Impedance
-
10
-
-
1.5
-
kn
Limiter Gain
-
-
-
-
96
-
dB
• Figure 1 Test Circuit uses positive (VCC) Ground.
MOTOROLA ANALOG IC DEVICE DATA
8-259
II
MC13150
AC ELECTRICAL CHARACTERISTICS (continued) (TA = 25'C, Vs = 3.0 Vdc, fRF = 50 MHz, flo = 50.455 MHz,
La Level = -10 dBm, see Figure 1 Test Circuit', unless otherwise specified.)
Characteristics
Condition
Pin
Frequency Adjust Current
Figure 9,
flF = 455 kHz
16
-
41
49
56
J.LA
Frequency Adjust Voltage
Figure 10,
!IF= 455 kHz
16
-
600
650
700
mVdc
Bandwidth Adjust Voltage
Figure 12,
115= 1.0J.LA
15
-
-
570
-
mVdc
-
23
-
-
1.36
-
Vdc
!dev = ±3.0 kHz
23
-
85
122
175
mVrms
DETECTOR
Detector DC Output Voijage
(See Figure 25)
Recovered Audio Voltage
• Figure 1 Test Circuit uses positive (VCC) Ground.
Figure 1. Test Circuit
,------------QEnable
r---------QRSSI
Mixer~220n
RSSI
1-----<0 Buffer
Out
1-----<1-_-0 Detector
Output
1.5k
RL
100 k
:~~on-=49.9
220n
V1B-V17 = 0;
'IF= 455 kHz
This device contains 292 active transistors.
8-260
MOTOROLA ANALOG IC DEVICE DATA
MC13150
MC13150 CIRCUIT DESCRIPTION
General
The MC13150 is a very low power single conversion
narrowband FM receiver incorporating a split IF. This device
is designated for use as the backend in analog narrowband
FM systems such as cellular, 900 MHz cordless phones and
narrowband data links with data rates up to 9.6 k baud. It
contains a mixer, oscillator, extended range received signal
strength indicator (RSSI), RSSI buffer, IF amplifier, limiting IF,
a unique coilless quadrature detector and a device enable
function (see Package Pin Outs/Block Diagram).
Low Current Operation
The MC13150 is designed for battery and portable
applications. Supply current is typically 1.7 mAdc at 3.0 Vdc.
Figure 2 shows the supply current versus supply voltage.
Enable
The enable function is provided for battery powered
operation. The enabled pin is pulled down to enable the
regulators. Figure 3 shows the supply current versus enable
voltage, Venable (relative to VCC) needed to enable the
device. Note that the device is fully enabled at VCC -1.3 Vdc.
Figure 4 shows the relationship of enable current, lenable to
enable voltage, Venable.
Mixer
The mixer is a double-balanced four quadrant multiplier
and is designed to work up to 500 MHz. It has a single ended
input. Figure 5 shows the mixer gain and saturated output
response as a function of input signal drive and for -10 dBm
LO drive level. This is measured in the application circuit
shown in Figure 15 in which a single LC matching network is
used. Since the single-ended input impedance of the mixer is
200 Q, an alternate solution uses a 1:4 impedance
transformer to match the mixer to 50 Q input impedance. The
linear voltage gain of the mixer alone is approximately 4.0 dB
(plus an additional 6.0 dB for the transformer). Figure 6
shows the mixer gain versus the LO input level for various
mixer input levels at 50 MHz RF input.
MOTOROLA ANALOG IC DEVICE DATA
The buffered output of the mixer is internally loaded,
resulting in an output impedance of 1.5 kQ.
Local Oscillator
The on--chip transistor operates with crystal and LC
resonant elements up to 220 MHz. Series resonant, overtone
crystals are used to achieve excellent local oscillator stability.
3rd overtone crystals are used through about 65 to 70 MHz.
Operation from 70 MHz up to 200 MHz is feasible using the
on--chip transistor with a 5th or 7th overtone crystal. To
enhance operation using an overtone crystal, the intemal
transistor's bias is increased by adding an extemal resistor
from Pin 29 (in 32 pin OFP package) to VEE to keep the
oscillator on continuously or it may be taken to the enable pin
to shut it off when the receiver is disabled. -10 dBm of local
oscillator drive is needed to adequately drive the mixer
(Figure 6). The oscillator configurations specified above are
described in the application section.
RSSI
The received signal strength indicator (RSSI) output is a
current proportional to the log of the received signal
amplitude. The RSSI current output is derived by summing
the currents from the IF and limiting amplifier stages. An
external resistor at Pin 25 (in 32 pin OFP package) sets the
voltage range or swing of the RSSI output voltage. Linearity
of the RSSI is optimized by using external ceramic bandpass
filters which have an insertion loss of 4.0 dB. The RSSI circuit
is designed to provide 100+ dB of dynamic range with
temperature compensation (see Figures 7 and 23 which
show the RSSI response of the applications circuit).
RSSI Buffer
The RSSI buffer has limitations in what loads it can drive.
It can pull loads well towards the positive and negative
supplies, but has problems pulling the load away from the
supplies. The load should be biased at half supply to
overcome this limitation.
8-261
MC13150
Figure 2. Supply Current
vti!rsus Supply Voltage
2.0
«
.s
I--
.., /
1.6
w
::>
0
$ 10-3
~ 10-4
(
z
a:
a:
10-2
a
a:
1.2
D..
D..
(JJ
iil
TA=25°CI
I
I
I
:::>
!!J 10-9
a:
a:
::>
60
50
40
0
lEI
w
30
'"zw
20
-'
..:
LiJ
-'
'"
..:
z
J!.l
2.5
3.5
4.5
5.5
6.5
7.5
r--
E
'"
r-- r-..
~
\.
~
I--
0
0.8
1.2
-10
!!:
a:
-30
xw
::i" -40
\
1.6
-20
'RF = 50 MHz; fLO = 50.455 MHz
LO Input Level = -10 dBm
(100mVrms)
(Rin = 50 Q; Rout = 1.4 kQ
I
-50
-50
2.0
............
V
-40
-30
-20
I
I
-10
10
VENABLE, ENABLE VOLTAGE (Vdc)
RF INPUT LEVEL (dBm)
Figure 6. Mixer IF Output Level versus
Local Oscillator Input Level
Figure 7. RSSI Output Current
versus Input Signal Level
50
W
I-Z
~ -20
a:
a:
6
>
40
W
:::>
::>
0
I--
I--
I--
D..
::>
-40
0-
I--
30
I
I
I
I
VCC = 3.0 Vdc
f=50MHz
fLO = 50.455 MHz
455 kHz
Ceramic Filter
See Figure 15
a:
u;
(JJ
~ -60
a:
:::;;
10
0
-50
-40
-30
LO DRIVE (dBm)
-20
-10
-
-
-120
./
20
V
./
V
20
::>
0
!!:
8-262
V
V
/"
/
0-
\
0.4
VEE = -3.0 Vdc
10 I- TA = 25°C
:8-'
w
::>
0
-80
-60
1.5
20
VCC=3.0Vdc
. TA = 25°C
«
5
1.3
Figure 5. Mixer IF Output Level versus
RF Input Level
0
'"-'
1.1
Figure 4. Enable Current
versus Enable Voltage
---- -o
0.9
VENABLE, ENABLE VOLTAGE (Vdc)
RF In = 0 dBm
:8-
V
0.7
0.5
20
E
:L
VENABLE, SUPPLY VOLTAGE (Vdc)
10
-10
~~
V
10-10
1.5
70
/'
10-7
& 10-ll
o
!z
w
10-5
~
/
0.4
!!J
~
/
1
D..
0.8
~
D...
D..
:::>
I
I
I
_ VCC=3.0Vdc
TA = 25°C
- VENABLE Measured
Relative to VCC
~ 10-6
~
::>
Figure 3. Supply Current
versus Enable Voltage
,/
,/
/'
V
V
"...
-100
-80
-60
-40
-20
o
SIGNAL INPUT LEVEL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
MC13150
IF Amplifier
The first IF amplifier section is composed of three
differential stages. This section has internal dc feedback and
external input decoupling for improved symmetry and
stability. The total gain of the IF amplifier block is
approximately 42 dB at 455 kHz. Figure 8 shows the gain of
the IF amplifier as a function of the IF frequency.
The fixed internal input impedance is 1.5 kQ; it is designed
for applications where a 455 kHz ceramic filter is used and no
external output matching is necessary since the filter requires
a 1.5 kg source and load impedance.
Overall RSSI linearity is dependent on having total
midband attenuation of 10 dB (4.0 dB insertion loss plus 6.0
dB impedance matching loss) for the filter. The output of the
IF amplifier is buffered and the impedance is 1.5 kg.
Limiter
The limiter section is similar to the IF amplifier section
except that six stages are used. The fixed internal input
impedance is 1.5 kg. The total gain of the limiting amplifier
section is approximately 96 dB. This IF limiting amplifier
section internally drives the quadrature detector section.
Figure 8. IF Amplifier Gain
versus IF Frequency
Figure 9. Fadj Current
versus IF Frequency
50
120
45
ill
:Eo
z
«
(!l
............
40
\
Fadj CURRENT (1lA)
MOTOROLA ANALOG IC DEVICE DATA
100
J
V
'\ r7
0.5
rv
o
400
V
/
"-\
~ 1.0
80
T
~
ID
60
I
VCC = 3.0Vdc
BW ~ 26 kHzlllA
'5"
I'--
20
I
1000
800
t, IF FREQUENCY (kHz)
~
o
600
t, FREQUENCY (MHz)
VCC=3.0Vdc
TA = 25°C
650
800
V
V
V
3.5
(!l
~
,/"'"
40
20
800
'U' 750
,/
a
r- Rin=50Q
Rout = 1.4 kQ
25 I- BW (3.0 dB) = 2.4 MHz
V
60
=>
30
20
0.01
/
80
IZ
\
17
420
440
460
480
500
t, IF FREQUENCY (kHz)
8-263
II
MC13150
Coilless Detector
The quadrature detector is similar to a PLL. There is an
internal oscillator running at the IF frequency and two
detector outputs. One is used to deliver the audio signal and
the other one is filtered and used to tune the oscillator.
The oscillator frequency is set by an external resistor at
the Fadj pin. Figure 9 shows the control current required for a
particular frequency; Figure 10 shows the pin voltage at that
current. From this the value of RF is chosen. For example,
455 kHz would require a current of around 50 IlA. The pin
voltage (Pin 16 in the 32 pin QFP package) is around 655mV
giving a resistor of 13.1 kQ. Choosing 12 kQ as the nearest
standard value gives a current of approximately 55 !lAo The
5.0 IlA difference can be taken up by the tuning resistor, RrThe best nominal frequency for the AFTout pin (Pin 17)
would be half supply. A supply voltage of 3.0 Vdc suggests a
resistor value of (1.5 - 0.655)Vl5!lA = 169 kQ. Choosing
150 kQ would give a tuning current of 3/150 k =20 !lAo From
Figure 9 this would give a tuning range of roughly 10 kHzlllA
or ± 100 kHz which should be adequate.
The bandwidth can be adjusted with the help of Figure 11.
For example, 1.0!lA would give a bandwidth of ± 13 kHz. The
II
10-3
/1
=
So, for example, 150 k and 1.0 IlF give a 3.0 dB point of
4.5 Hz. The recovered audio is set by RL to give roughly
50mV per kHz deviation per 100 k of resistance. The dc level
can be shifted by RS from the nominal 0.68 V by the following
equation:
Detector DC Output = ((RL + RS)/RS) 0.68 Vdc
=
Thus, RS
RL sets the output at 2 x 0.68
RL 2RS sets the output at 3 x 0.68 2.0 V.
=
10
~
I:;
0
a.. -10
V
§
=
= 1.36 V;
-
II
~B=560k
~
VCC=3.0Vdc
RB=1.0M
!§ -20 _ TA=25°C
/
S
is
~c
2.5
=
RrCT = 0.681f3dB.
I.
BWadj VOLTAGE (Vdc)
8-264
=
Figure 13. Demodulator Output
versus Frequency
V
2.3
=
Figure 12. BWadj Current
versus BWadj Voltage
VCC=3.0 Vdc
TA = 25°C
10-7
voltage across the bandwidth resistor, RB from Figure 12
0.56 Vdc for VCC
3.0 Vdc., so
is VCC - 2.44 Vdc
RB 0.56V11.0 !lA 560 kn. Actually the locking range will
be ±13 kHz while the audio bandwidth will be approximately
±S.4 kHz due to an internal filter capacitor. This is verified in
Figure 13. For some applications it may be desirable that the
audio bandwidth is increased; this is done by reducing RB.
Reducing RB widens the detector bandwidth and improves
the distortion at high input levels at the expense of 12 dB
SINAD sensitivity. The low frequency 3.OdB point is set by the
tuning circuit such that the product
2.7
-30 -40 -50
0.1
fRF= 50 MHz
flO = 50.455 MHz
lOlevel=-10dBm
No IF Bandpass Filters
fdev = ±4.0 kHz
~"
T I 1111111
1.0
10
100
f, FREQUENCY (kHz)
MOTOROLA ANALOG IC DEVICE DATA
MC13150
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The center section of the board provides an area for
attaching all SMT components to the circuit side and radial
leaded components to the component ground side (see
Figures 29 and 30). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interface circuitry as a particular application dictates.
There is an area dedicated for a LNA preamp. This
evaluation board will be discussed and referenced in this
section.
shown in Figures 27 and 28 for the application circuit in
Figure 15 and for the 83.616 MHz crystal oscillator circuit in
Figure 16.
Input Matching Components
The input matching circuit shown in the application circuit
schematic (Figure 15) is a series L, shunt C single L section
which is used to match the mixer input to 50 n. An
alternative input network may use 1:4 surface mount
transformers or BALUNs. The 12 dB SINAD sensitivity
using the 1:4 impedance transformer is typically -100 dBm
forfmod= 1.0 kHz andfdev =±5.0 kHz atfin =50 MHz and fLO
=50.455 MHz (see Figure 14).
It is desirable to use a SAW filter before the mixer to
provide additional selectivity and adjacent channel rejection
and improved sensitivity. SAW filters sourced from Toko (Part
# SWS083GBWA) and Murata (Part # SAF83.16MA51 X) are
excellent choices to easily interface with the MC13150 mixer.
They are packaged in a 12 pin low profile surface mount
ceramic package. The center frequency is 83.161 MHz and
the 3.0 dB bandwidth is 30 kHz.
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to
use components from various manufacturers and coil types.
The applications circuit schematic (Figure 15) specifies
particular components that were used to achieve the results
shown in the typical curves but equivalent components
should give similar results. Component placement views are
Figure 14. S+N+D, N+D, N, 30% AMR
versus Input Signal Level
20
iIi"
:sa:
2
S+N+D
0
~ -10
g
Z -20
ci
;J;. -30
ci
;J;. -40
+
en
II
10
-50
r...
Vee =3.0Vdc
'mod = 1.0 kHz
'dev = ±5.0 kHz
'in =50MHz
I
I
I
I
"- ~iIIl;
I
~
,
N+D
I
yt
-60
-120
-100
I
30%AMR
flO = 50.455 MHz
lO level = -10 dBm
See Figure 15
-80
-60
-
-40
INPUT SIGNAL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
8-265
MC13150
Figllre 15. Application Circuit
(3)
LO Input
(4)
.-------------0 Enable
(5)
r - - -.......- - - - - Q
RSSI
82k
(2)
455 kHz
IF Ceramic
nO,
1---0
0
RSSI
Buffer
1-----<_ _>---0 Detector
Output
RL
lOOk
II
150k
R-r
12k
RF
(6)
Coilless Detector
Circutt
VCC
NOTES: 1. Altemate solution is 1:4 impedance transformer (sources include Mini Circuits, Coilcraft and Toko).
2.455 kHz ceramic IIHers (source Murata CFU455 series which are selected for various bandwidths).
3. Forextemal LO source, a 51 n pull-up resistor is usadto bias the base of the on-board transistor as shown in Figure 15.
Designer may provide local oscillator with 3rd, 5th, or 7th overtone crystal oscillator circuit. The PC board is laid out to
accommodate extemal components needed for a Butler emitter coupled crystal oscillator (see Figure 16).
4. Enable IC by switching the pin to VEE.
5. The resistor is chosen to set the range of RSSI voltage output swing.
6. Details regarding the extemal components to setup the coilless detector are provided in the application section.
8-266
MOTOROLA ANALOG IC DEVICE DATA
MC13150
local Oscillators
A series LC network to ac ground (which is VCC) is
comprised of the inductance of the base lead of the on-chip
transistor and PC board traces and tap capacitors. Parasitic
oscillations often occur in the 200 to 800 MHz range. A small
resistor is placed in series with the base (Pin 28) to cancel the
negative resistance associated with this undesired mode of
oscillation. Since the base input impedance is so large, a
small resistor in the range of 27 to 68 (1 has very little effect
on the desired Butler mode of oscillation.
The crystal parallel capacitance, Co, provides a feedback
path that is low enough in reactance at frequencies of 5th
overtones or higher to cause trouble. Co has little effect near
resonance because of the low impedance of the crystal
motional arm (Rm-Lm-Cm). As the tunable inductor, which
forms the resonant tank with the tap capacitors, is tuned off
the crystal resonant frequency, it may be difficult to tell if the
oscillation is under crystal control. Frequency jumps may
occur as the inductor is tuned. In order to eliminate this
behavior an inductor, lo, is placed in parallel with the crystal.
Lo is chosen to resonant with the crystal parallel capacitance,
Co at the desired operation frequency. The inductor provides
a feedback path at frequencies well below resonance;
however, the parallel tank network of the tap capaCitors and
tunable inductor prevent oscillation at these frequencies.
HF & VHF Applications
In the application schematic, an external sourced local
oscillator is utilized in which the base is biased via a 51 (1
resistor to VCC. However, the on-chip grounded collector
transistor may be used for HF and VHF local oscillators with
higher order overtone crystals. Figure 16 shows a 5th
overtone oscillator at 83.616 MHz. The circuit uses a Butler
overtone oscillator configuration. The amplifier is an emitter
follower. The crystal is driven from the emitter and is coupled
to the high impedance base through a capacitive tap
network. Operation at the desired overtone frequency is
ensured by the parallel resonant circuit formed by the
variable inductor and the tap capacitors and parasitic
capacitances of the on-chip transistor and PC board. The
variable inductor specified in the schematic could be
replaced with a high tolerance, high Q ceramic or air wound
surface mount component if the other components have tight
enough tolerances. A variable inductor provides an
adjustment for gain and frequency of the resonant tank
ensuring lock up and start-up of the crystal oscillator. The
overtone crystal is chosen with ESR of typically 80 (1 and
120 (1 maximum; if the resistive loss in the crystal is too high
the performance of oscillator may be impacted by lower gain
margins.
II
Figure 16. MC13150FTB Overtone Oscillator
fRF 83.16 MHz; flO 83.616 MHz
5th Overtone Crystal Oscillator
=
=
(4)
--------------,I
0.135 11H
r---,
MC13150
I
33
+
I- I
1
1.011
39p
10n
Vee
MOTOROLA ANALOG IC DEVICE DATA
8-267
MC13150
application circuit (Figure 15). the input 1.0 dB compression
point is -10 dBm and the input third order intercept (IP3)
performance of the system is approximately 0 dBm (see
Figure 18).
Receiver Design Considerations
The curves of signal levels at various portions of the
application receiver with respect to RF input level are shown
in Figure 17. This information helps determine the network
topology and gain blocks required ahead of the MC13150 to
achieve the desired sensitivity and dynamic range of the
receiver system. The PCB is laid out to accommodate a low
noise preamp followed by the 83.16 MHz SAW filter. In the
Typical Performance Over Temperature
Figures 19-26 show the device performance over
temperature.
Figure 17. Signal Levels versus
RF Input Signal Level
10
0
-10
;[
-20
~
a::
w
s:
-30
~
-40
-50
fRF=50 MHz
fLO = 50.455 MHz; LO Level = -10 dBm
See Figure 15
-60
-70
-80
-70
-60
-50
-40
-30
-20
-10
RF INPUT SIGNAL LEVEL (dBm)
8-268
MOTOROLA ANALOG IC DEVICE DATA
MC13150
Figure 18. 1.0 dB Compression Point and Input
Third Order Intercept Point versus Input Power
20
i:e
...J
w
~
~
I
I
>1
V 1 """
/' /
/'
/
IP3 = -0.5 dBm
-20
c..
~
o
V
~
a:
~ -40
::ij
-60
V-
/'
-80
V
I
I
1.0 dB Compression ~
Point =-11 dBm
_ Vcc = 3.0 Vde
fRF1 = 50 MHz
fRF2 = 50.01 MHz
o ,-- fLO = 50.455 MHz
PLO=-10dBm
'-- See figure 15
V
/
I
-60
I
I
-40
-20
20
RF INPUT POWER (dBm)
II
TYPICAL PERFORMANCE OVER TEMPERATURE
Figure 19. Supply Current, IVEEl
versus Signal Input Level
Figure 20. Supply Current, IVEE2
versus Ambient Temperature
5.0
1
I-
z
w
a:
a:
0.35
4.5 f - VCC = 3.0 Vde
fe = 50 MHz
4.0 f - fdev = ±4.0 kHz
3.5
J.
/I
/I
3.0
~
0
2.5
~
a..
a..
2.0
~
(J)
~
It
w 1.0
2?
0.5
o
A
/
1.5
-120
10
rI
/A=85"C
\
-105
-90
TA = 25"C
I
-75
-60
-45
\
TA=-40"CI
-30
-15
SIGNAL INPUT LEVEL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
I
1
!z
~
a:
VCC = 3.0 Vdc
0.3
~
o
~
a..
c..
~ 0.25
~
~
V
/'
/
r
0.2
-~
-W
0
W
~
~
80
TA, AMBIENT TEMPERATURE (0C)
8-269
MC13150
TYPICAL PERFORMANCE OVER TEMPERATURE
Figure 21. Total Supply Current
versus Ambient Temperature
1.8
«
.s
f-
ii'i
Vee = 3.0 Vdc
1.7
~ 1.65
::>
~
"-
g;
1.6
1.55
~
1.5
f-
1.45
,...
~
w
II
.=!:
!z
UJ
c:
c:
~~
~
::;:
~
1.0
o
-20
20
40
60
-40
80
-
-
--
I
I
Vin=
---"'OdBm_
-"'-20dBm
I
40dBm
I
-
60dBm
80dBm
100?Bm
120dBm
0.65
-20
0
20
40
60
80
Q
1.6
~
1.3
~
~
~
0.6
0
::>
..:
0
UJ
a:
UJ
60
0.55
80
0.5
UJ
c:
0.45
Vcc= 3.0 Vdc
r- RF In = -50 dBm
- r-
fc=50 MHz
fLO = 50.455 MHz
fdey = ±4.0 kHz
I
-40
100
I I I
-20
0
20
40
60
80
Figure 25. Demod DC Output Voltage
versus Ambient Temperature
Figure 26. LO Current versus
Ambient Temperature
I
..............
r--....
.......
I'-...
...............
100
I
Vee = 3.0Vdc RF In = -50 dBm
fc=50 MHz
fLO = 50.455 MHz
fdey = ±4.0 kHz -
I
90
-
80
;--
«
.=!:
fZ
a:
c:
..... -
::>
0
70
0
...J
60
1.0
.......-
100
I
Vee = 3.0Vdc
RF In = -50 dBm
fc=50 MHz
fLO = 50.455 MHz
fdey = ±4.0 kHz
/-
UJ
.............. r--....
1.1
..--
I-
./
V
/'
50
-20
0
20
40
60
TA, AMBIENT TEMPERATURE (Oe)
8-270
-
-- -
TA, AMBIENT TEMPERATURE (Oe)
1.2
0.9
-40
r- r- r-
TA, AMBIENTTEMPERATURE (Oe)
1.7
5o
r- !--.
0.
~
0.4
-40
1.4
60
Figure 24. Recovered Audio versus
Ambient Temperature
20
~
40
0.7
30
1.5
20
Figure 23. RSSI Current versus
Ambient Temperature and Signal Level
0
~
0
TA, AMBIENT TEMPERATURE (Oe)
Vee = 3.0 Vdc
fRF=50MHz
40
(!J
-20
TA, AMBIENT TEMPERATURE ee)
10
w
1.5
Z
c:
~
r-.
R:
::>
U)
2.0
::>
0
en
--........r-.......
~
C!>
60
«
-........
2.5
U)
1.4
50
-...........
i:'!:
/
-40
3.0
~
... V
V
/
/
U)
o
..,. ..--
1.75
Figure 22. Minimum Supply Voltage
versus Ambient Temperature
80
-40
-20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (Oe)
MOTOROLA ANALOG IC DEVICE DATA
MC13150
Figure 27. Component Placement View - Circuit Side
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GND
MOTOROLA ANALOG IC DEVICE DATA
Vee
a
8-271
MC13150
Figure 28. Component Placement View'- Ground Side
II
8-272
MOTOROLA ANALOG IC DEVICE DATA
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MC13150
Figure 30. PCB Ground Side View
II
&-274
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13155
Wideband FM IF
The MC13155 is a complete wideband FM detector designed for satellite
TV and other wideband data and analog FM applications. This device may
be cascaded for higher IF gain and extended Receive Signal Strength
Indicator (RSSI) range.
WIDEBAND FM IF
• 12 MHz Video/Baseband Demodulator
• Ideal for Wideband Data and Analog FM Systems
• Limiter Output for Cascade Operation
SEMICONDUCTOR
TECHNICAL DATA
• Low Drain Current: 7.0 rnA
• Low Supply Voltage: 3.0 to 6.0 V
• Operates to 300 MHz
MAXIMUM RATINGS
Pin
Symbol
Value
Power Supply Voltage
Rating
11,14
VEE (max)
6.5
Vdc
Input Vo~age
1,16
Vin
1.0
Vrms
Junction Temperature
-
TJ
+150
°C
Storage Temperature Range
-
Tstg
-65to+150
°C
NOTE:
Unit
DSUFFIX
PLASTIC PACKAGE
CASE 7518
(50-16)
Devices should not be operated at or outside these values. The ·'Recommended
Operating Conditions" provide for actual device operation.
II
PIN CONNECTIONS
Figure 1. Representative Block Diagram
Input
Input
Decouple
Buffered
Decouple
15
Decouple
Vcc1
RSSI
Output
13
Input
Input
Output
RSSI Buller
Output
RSSI
Limiter Out
LimHerOut
Quad Coil
Quad Coil
(Top View)
5
Decouple
Balanced
Outputs
7
Limiter
Output
NOTE: This device requires careful layout and decoupling to ensure stable operation.
MOTOROLA ANALOG IC DEVICE DATA
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC13155D
TA =- 4010 +85°C
50-16
8-275
MC13155
RECOMMENDED OPERATING CONDITIONS
Pin
Symbol
Value
Unit
Power Supply Voltage (TA= 25°C)
- 40°C::; TA::; 85°C
Rating
11,14
3,6
VEE
VCC
-3.0to-6.0
Grounded
Vdc
Maximum Input Frequency
1,16
fin
300
TJ
-40to+85
;,'
Ambient Temperature Range
-
, MHz
°c
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, no input signal.)
Characteristic
Drain Current
(VEE = - 5.0 Vdc)
(VEE = - 5.0 Vdc)
Drain Current Total (see Figure 3)
(VEE = - 5.0 Vdc)
(VEE = - 6.0 Vdc)
(VEE = - 3.0 Vdc)
Symbol
Min
Typ
Msx
Unit
11
14
14
111
114
114
2.0
3.0
3.0
2.8
4.3
4.3
4.0
6.0
6.0
rnA
11,14
ITotal
5.0
5.0
5.0
4.7
7.1
7.5
7.5
6.6
10
10.5
10.5
9.5
rnA
Pin
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, flF = 70 MHz, VEE = - 5.0 Vdc Figure 2, unless otherwise noted.)
Characteristic
•
Pin
Min
Typ
Max
Unit
-
1.0
2.0
mVrms
470
450
380
590
570
500
700
680
620
Input for - 3 dB Limiting Sensitivity
1,16
Differential Detector Output Voltage (Vin = 10 mVrms)
(fdev = ± 3.0 MHz) (VEE = - 6.0 Vdc)
(VEE = - 5.0 Vdc)
(VEE = - 3.0 Vdc)
4,5
Detector DC Offset Voltage
mVJrP
4;5
-250
-
250
mVdc
RSSISlope
13
1.4
2.1
2.8
JlAIdB
RSSI Dynamic Range
13
31
35
39
RSSIOutput
(Vin = 100 ~Vrms)
(Vin = 1.0 mVrms)
(Vin = 10 mVrms)
(Vin = 100 mVrms)
(Vin = 500 mVrms)
12
RSSI Buffer Maximum Output Current (Vin = 10 mVrms)
13
Differential Limiter Output
(Vin = 1.0 mVrms)
(Vin = 10 mVrms)
16
-
-
2.1
2.4
24
65
75
36
2.3
-
dB
!1A
-
mAdc
mVrms
7,10
100
-
140
180
-
Demodulator Video 3.0 dB Bandwidth
4,5
-
12
-
Input Impedance (Figure 14)
@70MHz Rp (VEE = - 5.0 Vdc)
Cp (C2=C15 = 100 p)
1,16
-
450
4.8
-
pF
-
46
-
dB
Differential IF Power Gain
NOTE:
8-276
1,7,10,16
MHz
n
Positive currents are out of the pins of the device.
MOTOROLA ANALOG IC DEVICE DATA
MC13155
CIRCUIT DESCRIPTION
indicator (RSSI) circuit which provides a current output
linearly proportional to the I F input signal level for
approximately 35 dB range of input level.
The MC13155 consists of a wideband three-stage limiting
amplifier, a wideband quadrature detector which may be
operated up to 200 MHz, and a received signal strength
Figure 2. Test Circuit
1.0n
INl
10n
DECl
DEC2
VCCl
VEEl
27
~
VEE
DETOl
Video
Ou1put
DET02
Limiterl~
Ou1put
VEE
VCC2
VEE2
LlMOl
LlM02
1.0n
330
VEE
Ou1put
~u"""
1.0n
330
QUADl
499
II
20p
L1 - Coileral! part number 141Hl9JOBS
260n
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB shown in Figures 19 and 20 is very
versatile and is designed to cascade two ICs. The center
section of the board provides an area for attaching all surface
mount components to the circuit side and radial leaded
components to the component ground side of the PCB (see
Figures 17 and 18). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interface circuitry as a particular application dictates.
This evaluation board will be discussed and referenced in
this section.
Limiting Amplifier
Differential input and output ports interfacing the three
stage limiting amplifier provide a differential power gain of
typically 46 dB and useable frequency range of 300 MHz.
The IF gain flatness may be controlled by decoupling of the
internal feedback network at Pins 2 and 15.
MOTOROLA ANALOG IC DEVICE DATA
Scattering parameter (8-parameter) characterization of
the IF as a two port linear amplifier is useful to implement
maximum stable power gain, input matching, and stability
over a desired bandpass response and to ensure stable
operation outside the bandpass as well. The MC13155 is
unconditionally stable over most of its useful operating
frequency range; however, it can be made unconditionally
stable over its entire operating range with the proper
decoupling of Pins 2 and 15. Relatively small decoupling
capacitors of about 100 pF have a significant effect on the
wideband response and stability. This is shown in the
scattering parameter tables where S-parameters are shown
for various values of C2 and C15 and at VEE of - 3.0 and
-5.0Vdc.
8-277
MC13155··
TYPICAL PERFORMANCE AT TEMPERATURE
(See Figure 2. Test Circuit)
Figure 4. RSSI Output versus Frequency and
Input Signal Level
Figure 3. Drain Current versus Supply Voltage
10
f
i- TA
100
J25 C
~ 8.0
ITotai = 114 + 111
~
r
II:
i3
6.0
C!.
4.0
z
~
I
I
,
-g 2.0
co
.f
0.0
0.0
1.0
II
~
en
en
4.0
5.0
6.0
6.5
;!:
:g
'"
.£'
6.0
5.5
10
5.5
u
VEE=-6.0V~
'l
/
. /~
/'
,/
5.0
-50
./
./
-30
-10
~
~-5.0VdC
. /V
",
..,
4.0
=>
0
V
gj
23.0
II:
~
22.5
22.0
21.5
-50
z
;;: 3.5
II:
.."..
~3.0
§;!:.25
30
50
70
90
2.0
-50
110
i-"""
114
V
V
..............
0
--30
!.-- ~
-10
10
-
30
~ f--
50
70
90
TA, AMBIENT TEMPERATURE (OC)
Figure 7. RSSI Output versus Ambien~
Temperature and Supply Voltage
Figure 8. RSSI Output versus Input Signal
Voltage (Vin at Temperature)
110
100
./',
/ ./
'/
/
/
/'"
/'
_
-
~.
<80
~
I; 60
"-
:::I.
>=>
VEE=-5.0Vdc -
T
0
I
en
en
~J
VIE =-3'i VdC -
/'
/
-30
VEE=~6.0Vdc
II:
40
~
20
o~~~~rrwlli-~llW~LUwm
-10
10
30
50
70
TA, AMBIENTTEMPERATURE (0C)
8-278
f=70MHz
VEE = - 5.0 Vdc
TA, AMBIENT TEMPERATURE (0C)
24.0
23.5
r--
4.5
UJ
II:
II:
"
10
I>-
5.0
z
/3.0Vdc
24.5
~
1000
Figure 6. Detector Drain Current and Limiter
Drain Current versus Ambient Temperature
25.0
<
:::I.
100
Figure 5. Total Drain Current versus Ambient
Temperature and Supply Voltage
7.5
~
f2
8.0
r--.. r-.,....
f, FREQUENCY (MHz)
8.0
7.0
-
_40IdB~
o
:--'r-.,
VEE, SUPPLY VOLTAGE (-Vdc)
9.0
~
o
--'
7.0
r--....
~ ~~
r- r-...
_30 1dBj
20
3.0
-
-201dBl
~
.1
--.... r---.
-10IdB~
40
II:
II:
i3
z
80
0
/I
11/
2.0
I,
VEE = - 5.0Vdc
oldBl
>=>
"- 60
>=>
114
j::' 8.5
z
<:::I.
If
]j
P.
f
--
0
90
110
0.1
1.0
10
100
1000
Vin, INPUT VOLTAGE (mVrms)
MOTOROLA ANALOG IC DEVICE DATA
MC13155
Figure 9. Differential Detector Output
Voltage versus Ambient Temperature
and Supply Voltage
Figure 10. Differential Limiter Output Voltage
versus Ambient Temperature
(Vin
lli
VEy_-6.0VdC
;:f
~
/' /
~V
~
./
"",.
~~
os
cc....-
..;'
180
f--~
~~
3.~ 160
<0-
ffi- 140
.....
./
ffi
it
is
-10
10
30
70
50
90
110
".,
120
-50
"",.
~
-30
~1MO~V~in-=-_~3MO~d~B~m-----------'---'---'---'---'
S
1400 VEE=-5.0Vdc
f-'c=70MHz
~ 1200 'mod = 1.0 MHz
~
(Figure 16 no external capacitors
~ 1000 between Pins 7, 8 and 9, 10)
....&C-b"""'-f-.=-""T"'''--l
f2 8001----i----j----t.-"'70-F--,;;;-F----b.,..."q....='"""T'-"'---1
6001----1----~~~c:....~~~--~~~
I5 ::I--~~~e:~t_--t-~~--t_--t_--t_--!
t--c.
~
0-
§cc
§
~
2.5
3.0
3.5
4.0
4.5
c:.
uj
(!J
;:f
:..I
§2
5.0
5.5
6.0
VEE = - 5.0 Vdc
'e = 70 MHz
Capacitively coupled
(See Figure 16) - - - interstage: no aHenuation
90
1200
1---j----t----::;.....,,~1--::..,.."F--+::::;;;;o-t ± 3.0 ~HZ
800
±2.0MHz
I
r---F:::r::t::::p;;;;t=t-1
I
± 1.0 MHz
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Figure 13. - S+N, N versus IF Input
10
siN
/'
~
-20
co
:e:.
'I'-..
z -30
-10
-2.0
-3.0
f--
Z
+
'"
f--
=> -4.0
0
'"cc
70
Q OF QUADRATURE LC TANK
=>
0-
en
50
O~~--~--~--~~--~--~--~~
Figure 12. RSSI Output Voltage versus IF Input
O.------r------.------.------,-----,
-1.0
30
Yin = 1.0 mVrms
VEP-5.0Vdc
2000 Ie = 70 MHz
lmod = 1.0 MHz
1600 (Figure 16 no extemal capacitors ...-I"'--=l"""'''-l----'----l
between Pins 7,8 and 9,10)
± 4.0 MHz
Q OF QUADRATURE LC TANK
:go
--
~~
2400 r;V"'in-=--""3;;;0"'d;;:;-Bm~--~--~--""----""--""--""--"
400
I
2.0
10
/
V
./
Figure 118. Differential Detector Output Voltage
versus Q of Quadrature LC Tank
O~--~--~--~--~--~--~--~--~~
1.5
-10
.......
TA, AMBIENTTEMPERATURE (DC)
Figure 11A. Differential Detector Output Voltage
versus Q of Quadrature LC Tank
It
./
~
TA, AMBIENT TEMPERATURE (DC)
~a
i-"""
V
wo
./
- 30
Yin = 10 mVnns
~u;- 200
V
V
I
'=70MHz
VEE = - 5.0 Vdc
g
..........: /-5.0Vdc
....0V /-3.0Vdc
=1 and 10 mVrms)
220
-50
-5.0
-80
-60
-60
-40
-20
IF INPUT, (dBm)
MOTOROLA ANALOG IC DEVICE DATA
20
'"
-40
-70
-90
Ic = 70 MHz
'mod = 1.0 MHz
'dey = ± 5.0 MHz
VEE = - 5.~ Vde
-70
't'-.,.
............ N
-50
-30
-10
10
IF INPUT (dBm)
8-279
•
MC13155
In the 8-parameters measurements, the IF is treated as a
two-port linear class A amplifier. The IF amplifier is
measured with a single-ended input and output configuration
in which the Pins 16 and 7 are terminated in the series
combination of a 47 n resistor and a 10 nF capacitor to VCC
ground (see Figure 14. 8-Parameter Test Circuit).
The 8-parameters are in polar form as the magnitude
(MAG) and angle (ANG). Also listed in the tables are the
calculated values for the stability factor (K) and the Maximum
Available Gain (MAG). These terms are related in the
followinj:l equations:
K= (1-181112,..1 82212+ I LlI2)/(21 812 8211)
where: I Lli = I 811 822 - 812 821 I.
MAG = 10 log I 8211 /1 8121 + 10 log I K-( K2_1)1/21
where: K > 1. The necessary and sufficient conditions for
unconditional stability are given as K > 1:
B1 = 1 + I 811 12 - I 822 12 - I Lll2 > 0
Figure 14. S-Parameter Test Circuit
IF
Input
SMA
)
2
IN1
DEC1
VCC1
1 - - - . - - - - - - . - - - - _ _ , - 0 VEE
DET01
DET02
r·,
II
47
8-280
VCC2
2(
SMA
IF
Output
QUAD1
MOTOROLA ANALOG IC DEVICE DATA
MC13155
S-Parameters (VEE =- 5.0 Vdc, TA =25°C, C2 and C15 =0 pF)
K
MAG
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.94
-13
8.2
143
0.001
7.0
0.87
-22
2.2
32
2.0
0.78
-23
23.5
109
0.001
-40
0.64
-31
4.2
33.5
5.0
0.48
1.0
39.2
51
0.001
-97
0.34
-17
8.7
33.7
7.0
0.59
15
40.3
34
0.001
-41
0.33
-13
10.6
34.6
10
0.75
17
40.9
19
0.001
-82
0.41
-1.0
5.7
36.7
20
0.95
7.0
42.9
-6.0
0.001
-42
0.45
0
1.05
46.4
50
0.98
-10
42.2
-48
0.001
-9.0
0.52
-3.0
0.29
-
70
0.95
-16
39.8
-68
0.001
112
0.54
-16
1.05
46.4
100
0.93
-23
44.2
-93
0.001
80
0.53
-22
0.76
-
150
0.91
-34
39.5
-139
0.001
106
0.50
-34
0.94
200
0.87
-47
34.9
-179
0.002
77
0.42
-44
0.97
-
500
0.89
-103
11.1
-58
0.022
57
0.40
-117
0.75
-
700
0.61
-156
3.5
-164
0.03
0
0.52
179
2.6
13.7
900
0.56
162
1.2
92
0.048
-44
0.47
112
4.7
4.5
1000
0.54
131
0.8
42
0.072
-48
0.44
76
5.1
0.4
K
MAG
Frequency
Input 511
Forward 521
Rev 512
Output 522
S-Parameters (VEE =- 5.0 Vdc, TA =25°C, C2 and C15 =100 pF)
Frequency
Input 511
Forward 521
Rev 512
Output 522
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.98
-15
11.7
174
0.001
-14
0.84
-27
1.2
37.4
2.0
0.50
-2.0
39.2
85.5
0.001
-108
0.62
-35
6.0
35.5
5.0
0.87
8.0
39.9
19
0.001
100
0.47
-9.0
4.2
39.2
7.0
0.90
5.0
40.4
9.0
0.001
-40
0.45
-8.0
3.1
40.3
10
0.92
3.0
41
1.0
0.001
-40
0.44
-5.0
2.4
41.8
20
0.92
-2.0
42.4
-14
0.001
-87
0.49
-6.0
2.4
41.9
50
0.91
-8.0
41.2
-45
0.001
85
0.50
-5.0
2.3
42
70
0.91
-11
39.1
-63
0.001
76
0.52
-4.0
2.2
41.6
100
0.91
-15
43.4
-84
0.001
85
0.50
-11
1.3
43.6
150
0.90
-22
38.2
-126
0.001
96
0.43
-22
1.4
41.8
200
0.86
-33
35.5
-160
0.002
78
0.43
-21
1.3
39.4
500
0.80
-66
8.3
-9.0
0.012
75
0.57
-63
1.7
23.5
700
0.62
-96
2.9
-95
0.013
50
0.49
-111
6.3
12.5
900
0.56
-120
1.0
-171
0.020
53
0.44
-150
13.3
2.8
1000
0.54
-136
0.69
154
0.034
65
0.44
-179
12.5
-0.8
MOTOROLA ANALOG IC DEVICE DATA
8-281
II
MC13155
S-Parameters (VEE = - 5.0 Vdc, TA = 25°C, C2 and C15 = 680 pF)
K
MAG
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.74
4.0
53.6
110
0.001
101
0.97
-35
0.58
-
2.0
0.90
3.0
70.8
55
0.001
60
0.68
-34
1.4
45.6
5.0
0.91
0
87.1
21
0.001
-121
0.33
-60
1.1
49
7.0
0.91
0
90.3
11
0.001
-18
0.25
-67
1.2
48.4
47.5
Frequency
Input 511
Forward 521
Rev 512
Output 522
10
0.91
-2.0
92.4
2.0
0.001
33
0.14
-67
1.5
20
0.91
-4.0
95.5
-16
0.001
63
0.12
-15
1.3
48.2
50
0.90
-8.0
89.7
-50
0.001
-43
0.24
26
1.8
46.5
70
0.90
-10
82.6
-70
0.001
92
0.33
21
1.4
47.4
100
0.91
-14
77.12
-93
0.001
23
0.42
-1.0
1.05
49
150
0.94
-20
62.0
-122
0.001
96
0.42
-22
0.54
-
200
0.95
-33
56.9
-148
0.003
146
0.33
-62
0.75
-
500
0.82
-63
12.3
-12
0.007
79
0.44
-67
1.8
26.9
14.6
700
0.66
-98
3.8
-107
0.014
84
0.40
-115
4.8
900
0.56
-122
1.3
177
0.028
78
0.39
-166
8.0
4.7
1000
0.54
-139
0.87
141
0.048
76
0.41
165
7.4
0.96
K
MAG
S-Parameters (VEE = - 3.0 Vdc, TA = 25°C, C2 and C15 = 0 pF)
Frequency
Forward 521
Input 511
Rev 512
Output 522
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.89
-14
9.3
136
0.001
2.0
0.84
-27
3.2
30.7
2.0
0.76
-22
24.2
105
0.001
-90
0.67
-37
3.5
34.3
5.0
0.52
5.0
35.7
46
0.001
-32
0.40
-13
10.6
33.3
7.0
0.59
12
38.1
34
0.001
-41
0.40
-10
9.1
34.6
10
0.78
15
37.2
16
0.001
-92
0.40
-1.0
5.7
36.3
20
0.95
5.0
38.2
-9.0
0.001
47
0.51
-4.0
0.94
-
50
0.96
-11
39.1
-50
0.001
-103
0.48
-6.0
1.4
43.7
70
0.93
-17
36.8
-71
0.001
-76
0.52
-13
2.2
41.4
39.0
100
0.91
-25
34.7
-99
0.001
-152
0.51
-19
3.0
150
0.86
-37
33.8
-143
0.001
53
0.49
-34
1.7
39.1
200
0.81
-49
27.8
86
0.003
76
0.55
-56
2.4
35.1
500
0.70
-93
6.2
-41
0.015
93
0.40
-110
2.4
19.5
700
0.62
-144
1.9
-133
0.049
56
0.40
-150
3.0
8.25
900
0.39
-176
0.72
125
0.11
-18
0.25
163
5.1
-1.9
1000
0.44
166
0.49
80
0.10
-52
0.33
127
7.5
-4.8
8-282
MOTOROLA ANALOG IC DEVICE DATA
MC13155
=- 3.0 Vdc, TA =25°C, C2 and C15 =100 pF)
S-Parameters (VEE
Frequency
Input S11
Forward S21
RevS12
OutputS22
K
MAG
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.97
-15
11.7
171
0.001
-4.0
0.84
-27
1.4
36.8
2.0
0.53
2.0
37.1
80
0.001
-91
0.57
-31
6.0
34.8
5.0
0.88
7.0
37.7
18
0.001
-9.0
0.48
-7.0
3.4
39.7
7.0
0.90
5.0
37.7
8.0
0.001
-11
0.49
-7.0
2.3
41
10
0.92
2.0
38.3
1.0
0.001
-59
0.51
-9.0
2.0
41.8
20
0.92
-2.0
39.6
-15
0.001
29
0.48
-3.0
1.9
42.5
50
0.91
-8.0
38.5
-46
0.001
-21
0.51
-7.0
2.3
41.4
70
0.91
-11
36.1
-64
0.001
49
0.50
-8.0
2.3
40.8
100
0.91
-15
39.6
-85
0.001
114
0.52
-13
1.7
37.8
150
0.89
-22
34.4
-128
0.001
120
0.48
-23
1.6
40.1
200
0.86
-33
32
-163
0.002
86
0.40
-26
1.7
37.8
500
0.78
-64
7.6
-12
0.013
94
0.46
-71
1.9
22.1
700
0.64
-98
2.3
-102
0.027
58
0.42
-109
4.1
10.1
900
0.54
-122
0.78
179
0.040
38.6
0.35
-147
10.0
-0.14
1000
0.53
-136
0.47
144
0.043
23
0.38
-171
15.4
-4.52
K
MAG
S-Parameters (VEE =- 3.0 Vdc, TA =25°C, C2 and C15 =680 pF)
Frequency
Input S11
Forward S21
Rev S12
OutputS22
MHz
MAG
ANG
MAG
ANG
MAG
ANG
MAG
ANG
MAG
dB
1.0
0.81
3.0
37
101
0.001
-19
0.90
-32
1.1
43.5
2.0
0.90
2.0
47.8
52.7
0.001
-82
0.66
-39
0.72
-
2.3
44
5.0
0.91
0
58.9
20
0.001
104
0.37
-56
7.0
0.90
-1
60.3
11
0.001
-76
0.26
-55
2.04
44
10
0.91
-2.0
61.8
3.0
0.001
105
0.18
-52
2.2
43.9
44.1
20
0.91
-4.0
63.8
-15
0.001
59
0.11
-13
2.0
50
0.90
-8.0
60.0
-48
0.001
96
0.22
33
2.3
43.7
70
0.90
-11
56.5
-67
0.001
113
0.29
15
2.3
43.2
100
0.91
-14
52.7
-91
0.001
177
0.36
5.0
2.0
43
150
0.93
-21
44.5
-126
0.001
155
0.35
-17
1.8
42.7
200
0.90
-43
41.2
-162
0.003
144
0.17
-31
1.6
34.1
500
0.79
-65
7.3
-13
0.008
80
0.44
-75
3.0
22
700
0.65
-97
2.3
-107
0.016
86
0.38
-124
7.1
10.2
900
0.56
-122
0.80
174
0.031
73
0.38
-174
12
0.37
1000
0.55
-139
0.52
137
0.50
71
0.41
157
11.3
-3.4
MOTOROLA ANALOG IC DEVICE DATA
8-283
II
MC13155
DC Biasing Considerations
The DC biasing scheme utilizes two VCC connections
(Pins 3 and 6) and two VEE connections (Pins 14 and 11).
VEEl (Pin 14) is connected internally to the IF and RSSI
circuits' negative supply bus while VEE2 (Pin 11) is connected
internally to the quadrature detector's negative bus. Under
positive ground operation, this unique configuration offers the
ability to bias the RSSI and IF separately from the quadrature
detector. When two ICs are cascaded as shown in the 70
MHz application circuit and provided by the PCB (see
Figures 17 and 18), the first MC13155 is used without biasing
its quadrature detector, thereby saving approximately 3.0
mAo A total current of 7.0 mA is used to fully bias each IC,
thus the total current ih the application circuit is
approximately 11 mAo Both VCC pins are biased by the same
supply. VCC1 (Pin 3) is connected internally to the positive
bus of the first half of the IF limiting amplifier, while VCC2 is
internally connected to the positive bus of the RSSI, the
quadrature detector circuit, and the second half of the IF
limiting amplifier (see Figure 15). This distribution of the VCC
enhances the stability of the IC.
RSSI Circuitry
The RSSI circuitry provides typically 35 dB of linear
dynamic range and its output voltage swing is adjusted by
selection of the resistor from Pin 12 to VEE. The RSSI slope
is typically 2.1 IJAIdB ; thus, for a dynamic range of 35 dB, the
current output is approximately 74 /-lA. A 47 k resistor will
yield an RSSI output voltage swing of 3.5 Vdc. The RSSI
buffer output at Pin 13 is an emitter-follower and needs an
external emitter resistor of 10k to VEE.
In a cascaded configuration (see circuit application in
Figure 16), only one of the RSSI Buffer outputs (Pin 13) is
used; the RSSI outputs (Pin 12 of each IC) are tied together
and the one closest to the VEE supply trace is decoupled to
VCC ground. The two pins are connected to VEE through a 47
k resistor. This reSistor sources a RSSI current which is
proportional to the signal level at the IF input; typically,
1.0 mVrms (- 47 dBm) is required to place the MC13155 into
limiting. The measured RSSI output voltage response of the
application circuit is shown in Figure 12. Since the RSSI
current output is dependent upon the input signal level at the
IF input, a careful accounting of filter losses, matching and
other losses and gains must be made in the entire receiver
system. In the block diagram of the application circuit shown
below, an accounting of the signal levels at pOints throughout
the system shows how the RSSI response in Figure 12 is
justified.
Block Diagram of 70 MHz Video Receiver Application Circuit
II
Input
Level:
IF
In~ut
-45dBm
1.26 mVrms
-70dBm
71 ~Vrms
!~a
-72dBm
-32dBm
57~Vrms
57~Vrms
16
Transformer
-25dB
(I rt' L )
2.0 dB
nse Ion oss (Insertion Loss)
Cascading Stages
The limiting IF output is pinned-out differentially,
cascading is easily achieved by AC coupling stage to stage.
In the evaluation PCB, AC coupling is shown, however,
interstage filtering may be desirable in some applications. In
which case, the S-parameters provide a means to implement
a low loss interstage match and better receiver sensitivity.
Where a linear response of the RSSI output is desired
when cascading the ICs, it is necessary to provide at least
10 dB of interstage loss. Figure 12 shows the RSSI response
with and without interstage loss. A 15 dB resistive attenuator
is an inexpensive way to linearize the RSSI response. This
has its drawbacks since it is a wideband noise source that is
dependent upon the source and load impedance and the
amount of attenuation that it provides. A better, although
more costly, solution would be a bandpass filter designed to
the desired center frequency and bandpass response while
carefully selecting the insertion loss. A network topology
8-284
-47dBm
1.0mVrms
-
Minimum Input to Acquire
Limiting In MC13155
f- 16
10
MC13155
MC13155
7
f-l
-15dB
(AHenuator)
40 dB Gain
40 dB Gain
shown below may be used to provide a bandpass response
with the desired insertion loss.
Network Topology
1.0n
r
10
0.22~
7
I!
L
..,
16
I
I
I
...J
1.0n
MOTOROLA ANALOG IC DEVICE DATA
MC13155
Quadrature Detector
The quadrature detector is coupled to the IF with internal
2.0 pF capacitors between Pins 7 and 8 and Pins 9 and 10.
For wideband data applications, such as FM video and
satellite receivers, the drive to the detector can be increased
with additional external capacitors between these pins, thus,
the recovered video signal level output is increased for a
given bandwidth (see Figure 11A and Figure 11 B).
The wide band performance of the detector is controlled by
the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
(1 )
where: RT is the equivalent shunt resistance across the LC
Tank and XL is the reactance of the quadrature inductor at the
IF frequency (XL =27tfL).
The inductor and capacitor are chosen to form a resonant
LC Tank with the PCB and parasitic device capacitance at the
desired IF center frequency as predicted by:
fc = (21t "(LC p)) -1
(2)
where: L is the parallel tank inductor and Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a wideband detector
at 70 MHz and a loaded Q of 5. The loaded Q of the
quadrature detector is chosen somewhat less than the Q of
the IF bandpass. For an IF frequency of 70 MHz and an
IF bandpass of 10.9 MHz, the IF bandpass Q is
approximately 6.4.
Example:
Let the external Cext = 20 pF. (The minimum value here
should be greater than 15 pF making it greater than the
internal device and PCB parasitic capacitance, Cint ~
3.0 pF).
Cp = Cint + Cext = 23 pF
Rewrite Equation 2 and solve for L:
L = (0.159)2 /(C p fc 2)
L = 198 nH, thus, a standard value is chosen.
L =0.22 !J.H (tunable shielded inductor).
MOTOROLA ANALOG IC DEVICE DATA
The value of the total damping resistor to obtain the
required loaded Q of 5 can be calculated by rearranging
Equation 1:
RT = Q(21tfL)
RT = 5 (21t)(70)(0.22) = 483.8 Q.
The internal resistance, Rint between the quadrature tank
Pins 8 and 9 is approximately 3200 Q and is considered in
determining the external resistance, Rext which is calculated
from:
Rext = «RT)(Rint))/ (Rint - RT)
Rext
= 570, thus, choose the standard value.
Rext = 560Q.
SAW Filter
In wideband video data applications, the IF occupied
bandwidth may be several MHz wide. A good rule of thumb is
to choose the IF frequency about 10 or more times greater
than the IF occupied bandwidth. The IF bandpass filter is a
SAW filter in video data applications where a very selective
response is needed (i.e., very sharp bandpass response).
The evaluation PCB is laid out to accommodate two SAW
filter package types: 1) A five-leaded plastic SIP package.
Recommended part numbers are Siemens X6950M which
operates at 70 MHz; 10.4 MHz 3 dB passband, X6951M
(X252.8) which operates at 70 MHz; 9.2 MHz 3 dB passband;
and X6958M which operates at 70 MHz, 6.3 MHz 3 dB
passband, and 2) A four-leaded T0-39 metal can package.
Typical insertion loss in a wide bandpass SAW filter is 25 dB.
The above SAW filters require source and load
impedances of 50 Q to assure stable operation. On the PC
board layout, space is provided to add a matching network,
such as a 1:4 surface mount transformer between the SAW
filter output and the input to the MC13155. A 1:4 transformer,
made by Coilcraft and Mini Circuits, provides a suitable
interface (see Figures 16, 17 and 18). In the circuit and
layout, the SAW filter and the MC13155 are differentially
configured with interconnect traces which are equal in length
and symmetrical. This balanced feed enhances RF stability,
phase linearity, and noise performance.
8-285
II
II
t
~
Figure 15. Simplified Internal Circuit Schematic
-s=;-
2
,£
Decouple
Vcc1
~
f2l
I1sl
VCC2
LIM Out
~
10
3
131 112
Quad Coil
LIM Out
I
7
RSSI RSSI
Buffer
J
v
Y'
"
10p
tt:i1
a.Ok
5:
~
, 1~
Out
4
~4)l 1 I J
I
a.Ok
1.0k
~
a
1.0k
~
~
~
Bias
~
,~
)00
z
I
§
01
~
<
o
m
o
~
)Ii
~
Input
!e~e
,~
1
w
~
' Bias
'$~ ~e
....
....
CII
0
~e!8
~8
~$
!Q
~$
!$
!~
~e
,e
..l....
J..±
J!
Input
VEE 1
VEE 2
Co)
CII
MC13155
Figure 16. 70 MHz Video Receiver Application Circuit
If Input
>-++...,
220
SAW Riter is Siemens
Part Number X6950M
RSSI
Output
MC13155
IN2
DEC2
VEEI
10k
~ IOn
RSSI
Buffer
47k
~ lOOn
RSSI
LlM02
II
820
820
820
1.0n
MC13155
INI
Detector
Output
t
IN2
DECI
DEC2
VCCI
VEEI
DETOI
RSSI
Buffer
DET02
RSSI
VCC2
VEE2
LlMOI
LlM02
QUADI
QUAD2
lOOn
o----io----i
......---~--~
~-
lOOn
r - _ - - - - - - - - - - -......--OVEE2
10~
=¥
560
20p
r----,
-
L
I
I
L ___ .J
L- Coilcraft part number I 46-08J08S
0.22~
MOTOROLA ANALOG IC DEVICE DATA
8-287
MC13155
Figure 17. Component Placement (Circuit Side)
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8-288
MOTOROLA ANALOG IC DEVICE DATA
MC13155
Figure 19. Circuit Side View
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Figure 20. Ground Side View
MOTOROLA ANALOG IC DEVICE DATA
8-289
®
MOTOROLA
MC13156
Wideband FM IF System
The MC13156 is a wideband FM IF subsystem targeted at high
performance data and analog applications. Excellent high frequency
performance is achieved at low cost using Motorola's MOSAIC 1.5™ bipolar
proce~s, The MC13156 has an onboard grounded collector VCO transistor
that may be used with a fundamental or overtone crystal in single channel
operation or with a PLL in multichannel operation. The mixer is useful to
500 MHz and may be used in a balanced-differential, or single-ended
configuration. The IF amplifier is split to accommodate two low cost
cascaded filters. RSSI output is derived by summing the output of both IF
sections, A precision data shaper has a hold function to preset the shaper for
fast recovery of new data.
Applications for the MC13156 include CT-2, wideband data links and
other radio systems utilizing GMSK, FSK or FM modulation.
WIDEBAND FM IF
SYSTEM FOR DIGITAL AND
ANALOG APPLICATIONS
SEMICONDUCTOR
TECHNICAL DATA
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(SQ-24L)
• 2.0 to 6.0 Vdc Operation
• Typical Sensitivity at 200 MHz of 2.0 !LV for 12 dB SINAD
• RSSI Dynamic Range Typically 80 dB
• High Performance Data Shaper for Enhanced CT-2 Operation
• Internal 330 nand 1.4 kn Terminations for 10.7 MHz and 455 kHz Filters
FB SUFFIX
PLASTIC OFP PACKAGE
CASE 873
312 .
• Split IF for Improved Filtering and Extended RSSI Range
• 3rd Order Intercept (Input) of -25 dBm (Input Matched)
PIN CONNECTIONS
SQ-24L
Function
QFP
RF Input 1
RF Input 2
Mixer Output
VCCI
IF Amp Inpul
IF Amp Oecoupling 1
IF Amp Decoupling 2
VCC Connect (NiC Inlernal)
IF Amp Outpul
Simplified Block Diagram
LO
In
LO
Emil
VEEI
CAR
Del
RSSI
VEE2
Data
Out
OS
Gnd
31
32
1
, VCC2
Limiter IF Input
Limiter Decoupling 1
Limiter Oecoupling 2
V C Connect (N/C Internal)
Quad Coil
Demodulator Output
Data Slicer Input
VCC Connect (NiC Inlemal)
Data Slicer Ground
Data Slicer Output
Data Slicer Hold
OS
In
VEE2
RSSI OutpuVCarrier Detect In
Carrier Detect Output
VEE1 and Substrate
LO Emitter
LO Base
VCO Connect (N/C Intemal)
10
11
12
10
11
12,13,14
15
16
17
18
19
20
21
13
14
15
16
17
18
19
20
21
22
23
24
22
23
24
25
26
27
28,29.30
ORDERING INFORMATION
RF
Inl
RF
In2
Mix
Out
VCCI
IF
IF
DEC 1 DEC2
IF
Out
VCC2
LIM
In
LIM
LIM
DEC 1 DEC2
Device
NOTE: Pin Numbers shown for'SOIC pac~age only, Refer to Pin Assignments Table,
This device contains 197 active transistors.
8-290
MC13158DW
MC13156FB
Operating
Temperature Range
TA = -40 to +85°C
Package
SQ-24L
OFP
MOTOROLA ANALOG IC DEVICE DATA
MC13156
MAXIMUM RATINGS
Pin
Symbol
Value
Unit
Power Supply Voltage
Rating
16,19,22
VE~(rnaJ(>-
-6.5
Vdc
Junction Temperature
-
TJ(max)
150
°c
Storage Temperature Range
-
Tstg
-65 to +150
°c
NOTES: 1. Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" table provides for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage @ TA = 25°C
-40°C S TA S +B5°C
Input Frequency
Ambient Temperature Range
Input Signal level
Pin
Symbol
Value
Unit
VCC
VEE
o (Ground)
Vdc
4,9
16,19,22
-2.0to-6.0
1,2
fin
500
-
TA
-40to+B5
MHz
°c
1,2
Yin
200
mVrms
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCCl = VCC2 = 0, no input signal.)
Pin
Symbol
Total Drain Current (See Figure 2)
VEE = -2.0 Vdc
VEE = --3.0 Vdc
VEE = -5.0 Vdc
VEE = -6.0 Vdc
Characteristic
19,22
ITotal
Drain Current, 122 (See Figure 3)
VEE = -2.0 Vdc
VEE = --3.0 Vdc
VEE = -5.0 Vdc
VEE = -6.0 Vdc
22
Drain Current, 119 (See Figure 3)
VEE = -2.0 Vdc
VEE = --3.0 Vdc
VEE = -5.0 Vdc
VEE = -6.0 Vdc
19
Min
Typ
Max
-
4.B
5.0
5.2
5.4
-
mA
3.0
-
122
Unit
-
B.O
-
rnA
-
-
3.0
3.1
3.3
3.4
-
1.B
1.9
1.9
2.0
-
-
119
-
rnA
-
DATA SLICER (Input Voltage Referenced to VEE = --3 0 Vdc no input signal; See Figure 15 )
Input Threshold Voltage (High Yin)
15
V15
1.0
1.1
1.2
Vdc
Output Current (low Yin)
Data Slicer Enabled (No Hold)
V15> 1.1 Vdc
V1B=OVdc
17
117
-
1.7
-
rnA
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VEE = --3.0 Vdc, fRF = 130 MHz, flO = 140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
Pin
Symbol
Min
Typ
Max
Unit
1,14
-
-
-100
-
dBm
Conversion Gain
Pin = -37 dBm (Figure 4)
1,3
-
-
22
-
dB
Mixer Input Impedance
Single-Ended (Table 1)
1,2
Rp
Cp
-
1.0
4.0
-
kn
-
-
pF
Mixer Output Impedance
3
-
-
330
-
n
IF RSSI Slope (Figure 6)
20
0.4
0.6
j.tAIdB
5,B
-
0.2
IF Gain (Figure 5)
39
-
dB
Input Impedance
5
-
1.4
kn
Output Impedance
B
-
290
-
Characteristic
12 dB SINAD Sensitivity (See Figures 17, 25)
fin = 144.45 MHz; fmod = 1.0 kHz; fdev = ±75 kHz
MIXER
IF AMPLIFIER SECTION
MOTOROLA ANALOG IC DEVICE DATA
-
n
8--291
II
MC13156
AC ELECTRICAL CHARACTERISTICS (continued) (TA =25°C, VEE
=--3.0 Vdc, fRF =130 MHz, fLO =140.7 MHz, Figure 1 test
circuit, unless otherwise specified.)
.
Characteristic
LIMITING AMPLIFIER SECTION
Limiter RSSI Slope (Figure 7)
20
-
0.2
0.4
0.6
Limiter Gain
-
-
dB
10
-
55
Input Impedance
-
1.4
-
kn
Output Current - Carrier Detect (High Vin)
21
-
21
-
-
0
Output Current - Carrier Detect (Low Vin)
3.0
-
rnA
Input Threshold Voltage - Carrier Detect
Input Voltage Referenced to VEE = --3.0 Vdc
20
-
0.9
1.2
1.4
Vdc
jJAldB
CARRIER DETECT
Figure 1. Test Circuit
r------------,
I
I
1:4
RFlnput
130MHz
11-t~
Mixerv=
1.0n
Output
330
II
IF Input
3
MC13156
I
I
50
I1A
Local
Oscillator
Input
140.7MHz
200mVnns
I
r.-1
rt-±-r Vee
-=
Bias
I
>-++-......- - - - - - 1
r-----------+-O DataSlicer
Hold
IFOutputV
330 1.0n
8
I
rfl}vee
-=
Limiter
Input
-=
I
>-f-r--t"----j
SMA
LIM Amp
50
I
5.0p
I
L.. _ _ _ _ _ _ _ _ _ _ _ _ J
NOTES: 1. TR 1 Coilcrafll:4 impedance transformer.
2. VCC is DC Ground.
3. 1.511H variable shielded inductor:
Taka Part # 292SNS-T1373 or Equivalent.
8-292
MOTOROI,..A ANALOG IC DEVICE DATA
MC13156
Figure 2. Total Drain Current versus Supply
Voltage and Temperature
6.5
<-
.s
.._J
-----
6.0
z>-'"
w
a:.
II:
:::J
U
z
5.5
5.0
--
4.5
z
:r>
g
(')
c
~
om
C
~
:I>
I
VEE2
I
0
19
Linear Amplifier
I
Quadrature Detector
(""' '")
(""'1(""'
t (""' '")
'")
L - - - - - - - - - - -.....-'VItI.
Data Slicer
64k
I
~
0
18
DSHold
MC13156
CIRCUIT DESCRIPTION
General
The MC13156 is a low power single conversion wide band
FM receiver incorporating a split IF. This device is designated
for use as the backend in digital FM systems such as CT-2
and wideband data links with data rates up to 500 kbaud. It
contains a mixer, oscillator, signal strength meter drive, IF
amplifier, limiting IF, quadrature detector and a data slicer
with a hold function (refer to Figure 8, Simplified Internal
Circuit Schematic).
Current Regulation
Temperature compensating voltage independent current
regulators are used throughout.
Mixer
The mixer is a double-balanced four quadrant multiplier
and is designed to work up to 500 MHz. It can be used in
differential or in single--ended mode by connecting the other
input to the positive supply rail.
Figure 4 shows the mixer gain and saturated output
response as a function of input signal drive. The circuit used
to measure this is shown in Figure 1. The linear gain of the
mixer is approximately 22 dB. Figure 9 shows the mixer gain
versus the IF output frequency with the local oscillator of
150 MHz at 100 mVrms LO drive level. The RF frequency is
swept. The sensitivity of the IF output of the mixer is shown in
Figure 10 for an RF input drive of 10 mVrms at 140 MHz and
IF at 10 MHz.
The single--ended parallel equivalent input impedance of
the mixer is Rp - 1.0 kn and Cp - 4.0 pF (see Table 1 for
details). The buffered output of the mixer is internally loaded
resulting in an output impedance of 330 n.
Local Oscillator
The on--chip transistor operates with crystal and LC
resonant elements up to 220 MHz. Series resonant, overtone
crystals are used to achieve excellent local oscillator stability.
3rd overtone crystals are used through about 65 to 70 MHz.
Operation from 70 MHz up to 180 MHz is feasible using the
on--chip transistor with a 5th or 7th overtone crystal. To
enhance operation using an overtone cristal, the internal
transistor's bias is increased by adding an external resistor
from Pin 23 to VEE. -10 dBm of local oscillator drive is
needed to adequately drive the mixer (Figure 10).
The oscillator configurations specified above, and two
others using an external transistor, are described in the
application section:
1) A 133 MHz oscillator multiplier using a 3rd overtone
crystal, and
2) A 307.8 to 309.3 MHz manually tuned, varactor controlled
local oscillator.
RSSI
The Received Signal Strength Indicator (RSS!) output is a
current proportional to the log of the received signal
MOTOROLA ANALOG IC DEVICE DATA
amplitude. The RSSI current output is derived by summing
the currents from the IF and limiting amplifier stages. An
external resistor at Pin 20 sets the voltage range or swing of
the RSSI output voltage. Linearity of the RSSI is optimized by
using external ceramic or crystal bandpass filters which have
an insertion loss of 8.0 dB. The RSSI circuit is designed to
provide 70+ dB of dynamic range with temperature
compensation (see Figures 6 and 7 which show RSSI
responses of the IF and Limiter amplifiers). Variation in the
RSSI output current with supply voltage is small (see
Figure 11).
Carrier Detect
When the meter current flowing through the meter load
resistance reaches 1.2 Vdc above ground, the comparator
flips, causing the carrier detect output to go high. Hysteresis
can be accomplished by adding a very large resistor for
positive feedback between the output and the input of the
comparator.
IF Amplifier
The first IF amplifier section is composed of three
differential stages with the second and third stages
contributing to the RSSI. This section has internal dc
feedback and external input decoupling for improved
symmetry and stability. The total gain of the IF amplifier block
is approximately 39 dB at 10.7 MHz. Figure 5 shows the gain
and saturated output response of the IF amplifier over
temperature, while Figure 12 shows the IF amplifier gain as a
function of the IF frequency.
The fixed internal input impedance is 1.4 kn. It is designed
for applications where a 455 kHz ceramic filter is used and no
external output matching is necessary since the filter requires
a 1.4 kn source and load impedance.
For 10.7 MHz ceramic filter applications, an external
430 n resistor must be added in parallel to provide the
equivalent load impedance of 330 n that is required by the
filter; however, no external matching is necessary at the input
since the mixer output matches the 330 n source impedance
of the filter. For 455 kHz applications, an external 1.1 kn
resistor must be added in series with the mixer output to
obtain the required matching impedance of 1.4 kn of the filter
input resistance. Overall RSSI linearity is dependent on
having total midband attenuation of 12 dB (6.0 dB insertion
loss plus 6.0 dB impedance matching loss) for the filter. The
output of the IF amplifier is buffered and the impedance is
290n.
Limiter
The limiter section is similar to the IF amplifier section
except that four stages are used with the last three
contributing to the RSSI. The fixed internal input impedance
is 1.4 kn. The total gain of the limiting amplifier section is
approximately 55 dB. This IF limiting amplifier section
internally drives the quadrature detector section.
8--295
II
:
MC13156
Figure 10. Mixer IF Output Level versus
Local Oscillator Input Level
Figure 9. Mixer Gain versus IF Frequency
20
15
I I IIIIIII
I
I
I
I 111I111
......
VEE =-{3.0 Vdc
i'il
Vin = 1.0 mVrms (-47 dBm)
:!2- 10 r- Ro=330n
z
Rin=50n
«(!)
BW(3.0 dB) = 21.7 MHz
ex:
w 5.0 f- flF = fLO - fRF
~
fLO = 150 MHz
::;:
VLO = 100 mVrms
-5.0
,
1
i\
iLl
~ -20
'3
~O
-25
-{30
~
ex: -{35
~
I
1.0
10
,/
-45
100
-50
V
V
/
-{30
-40
~
25
'3
20
~
15
en
10
o
~
~
50
i'il
:!2-
-40dBm
z
«
40
.....
I,;""
(!)
-WdBm
ex:
w
Vin = 100 I1V
Rin=50n
Ro=330n
BW(3.0 dB) = 26.8 MHz
TA = 25°C
::J
a..
::;:
..:
1.0
2.0
20
~
100dBm
10
5.0
3.0
4.0
5.0
6.0
I I IIIIIII
o
0.1
7.0
~r-.
30
u:
-80dBm
o
10
TA = 25°C
20dBm
<.>
I
o
60
Vin=
30
I
-10
Figure 12.IF Amplifier Gain versus IF Frequency
40
~
I
-20
LO DRIVE (dBm)
Figure 11. RSSI Output Current versus
Supply Voltage and RF Input Signal Level
35
/
fRF= 140 MHz; flO = 150 MHz
RF Input level = -27 dBm
(10mVrms)
Rin = 50 n; RO = 330 n
flF, IF FREQUENCY (MHz)
«::t
/
TA = 25°C
en
:!2- -15
:E -40
I 11111111
-5.0
0.1
.1
E -10 r- VEE = -{3.0 Vdc
1.0
10
100
f, FREQUENCY (MHz)
VEE, SUPPLY VOLTAGE (-Vdc)
Figure 13. Recovered Audio Output Voltage
versus Supply Voltage
' [ 400
i
'3
a.. 300
§
I
9
Cl
~ 200
fil
a::
fmod = 1.0 kHz
fdev = ±75 kHz
fRF= 140 MHz
RF Input level = 1.0 mVrms
TA = 25°C
w
§
100
ex:
...
-> o
1.0
J
2.0
3.0
4.0
I
I
5.0
6.0
7.0
VEE, SUPPLY VOLTAGE (-Vdc)
8-296
MOTOROLA ANALOG IC DEVICE DATA
MC13156
Quadrature Detector
The quadrature detector is a doubly balanced four
quadrant multiplier with an internal 5.0 pF quadrature
capacitor to couple the IF signal to the external parallel RLC
resonant circuit that provides the 90 degree phase shift and
drives the quadrature detector. A single pin (Pin 13) provides
for the external LC parallel resonant network and the internal
connection to the quadrature detector.
The bandwidth of the detector allows for recovery of
relatively high data rate modulation. The recovered Signal is
converted from differential to single ended through a
push-pull NPN/PNP output stage. Variation in recovered
audio output voltage with supply voltage is very small (see
Figure 13). The output drive capability is approximately
±9.0 IlA for a frequency deviation of ±75 kHz and 1.0 kHz
modulating frequency (see Application Circuit).
Data Slicer
The data slicer input (Pin 15) is self centering around 1.1 V
with clamping occurring at 1.1 ± 0.5 Vbe Vdc. It is designed to
square up the data signal. Figure 14 shows a detailed
schematic of the data slicer.
The Voltage Regulator sets up 1.1 Vdc on the base of
012, the Differential Input Amplifier. There is a potential of
1 .0 Vbe on the base--collector of transistor diode 011 and
2.0 Vbe on the base--collector of 01 O. This sets up a 1.5 Vbe
(- 1.1 Vdc) on the node between the 36 kn resistors which is
connected to the base of 012. The differential output of the
data slicer 012 and 013 is converted to a single-ended
output by the Driver Circuit. Additional circuitry, not shown in
Figure 14, tends to keep the data slicer input centered at
1.1 Vdc as input signal levels vary.
The Input Diode Clamp Circuit provides the clamping at
1.0 Vbe (0.75 Vdc) and 2.0 Vbe (1.45 Vdc). Transistor diodes
07 and 08 are on, thus, providing a 2.0 Vbe potential at the
base of 01. Also, the voltage regulator circuit provides a
potential of 2.0 Vbe on the base of 03 and 1.0 Vbe on the
emitter of 03 and 02. When the data slicer input (Pin 15) is
MOTOROLA ANALOG IC DEVICE DATA
pulled up, 01 turns off; 02 turns on, thereby clamping the
input at 2.0 Vbe. On the other hand, when Pin 15 is pulled
down, 01 turns on; 02 turns off, thereby clamping the input at
1.0 Vbe.
The recovered data signal from the quadrature detector is
ac coupled to the data slicer via an input coupling capacitor.
The size of this capacitor and the nature of the data signal
determine how faithfully the data slicer shapes up the
recovered signal. The time constant is short for large peak to
peak voltage swings or when there is a change in dc level at
the detector output. For small Signal or for continuous bits of
the same polarity which drift close to the threshold voltage,
the time constant is longer. When centered there is no input
current allowed, which is to say, that the input looks high in
impedance.
Another unique feature of the data slicer is that it responds
to various logic levels applied to the Data Slicer Hold Control
pin (Pin 18). Figure 15 illustrates how the input and output
currents under "no hold" condition relate to the input voltage.
Figure 16 shows how the input current and input voltage
relate for both the "no hold" and "hold" condition.
The hold control (Pin18) does three separate tasks:
1) With Pin 18 at 1.0 Vbe or greater, the output is shut off
(sets high). 019 turns on which shunts the base drive
from 020, thereby turning the output off.
2) With Pin 18 at 2.0 Vbe or greater, internal clamping diodes
are open circuited and the comparator input is shut off and
effectively open circuited. This is accomplished by turning
off the current source to emitters of the input differential
amplifier, thus, the input differential amplifier is shut off.
3) When the input is shut off, it allows the input capaCitor to
hold its charge during transmit to improve recovery at the
beginning of the next receive period. When it is turned on,
it allows for very fast charging of the input capacitor for
quick recovery of new tuning or data average. The above
features are very desirable in a TOO digital FM system.
8-297
MC13156
Figure 14. Data Slicer Circuit
15
DSln
B.Ok
B.O k
Data Out
17
014
020
/
/
/
(
I
I
64 k
64k
Input Diode
Clamp Circuit
(01 to 09)
Voltage
Regulator
(010,011)
Differential
Input Amplifier
(012,013)
Driver and
Output Circuit
(014,020)
Figure 15. Data Slicer Input/Output Currents
versus Input Voltage
0.5
1
0.3
I-
z
w
a:
a:
r-- Output Current
r-- (117)
I
0.1
::>
0..
~
: : -0.3
H
-0.5
0.6
2.5
1.5
150
1 1 100
!z
w
a: !z
w
a: a:
a:
::>
(.)
/
-0.5
(.)
0..
::>
I-
I
O.B
1~
12
1A
1
1.6
1.B
2.5
I
Hold
V1B",10
No Hold
V1B=OVdc
/
iJ
50
I0..
0
~
.;,
VEP -3.0 Vdc _
-1.5 . : ..:: -50
V1B = 0 Vdc
(No Hold)
-
Input Current
(115)
~I
I
VEE =-J,O Vdc
::>
I-
::>
::>
0
V15,INPUTVOLTAGE (Vdc)
8-298
Figure 16. Data Slicer Input Current
versus Input Voltage
0.5
./
(.)
~ -0.1
1
I
I
lB
DSHold
-100
-1.0
,
(~
I
(
No Hold
Hold
J
-0.5
o
0.5
J
1.0
1.5
2.0
2.5
3.0
V15, INPUT VOLTAGE (Vdc)
MOTOROLA ANALOG IC DEVICE DATA
MC13156
Figure 17. MC13156DW Application Circuit
(6)
0. 146 11
r------------,
144.455 MHz
RF Input
I
I
MC13156
I
I
-::-
Carrier
Detect
Vee
Bias
RSSI
Output
10n
10n
Data Slicer
Hold
10k
II
Data
Output
Vee
Vee
NOTES: 1.0.1 JLH Variable Shielded Inductor: Coilcraft part # M1283-A or equivalent.
2.10.7 MHz Ceramic Filter. Toko part # SK107M5-A0-1OX or Murata Erie part # SFE10.7MHY-A.
3. 1.5 JLH Variable Shielded Inductor: Toko part # 292SNS-T1373.
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.585 MHz.
5.0.814 JLH Variable Shielded Inductor: Coilcraft part 1/ 143-18J12S.
6. 0.146 JLH Variable Inductor: Coilcraft part # 146-D4J08.
MOTOROLA ANALOG IC DEVICE DATA
8-299
MC,13156
Figure 18. MC13156DW Circuit Side Component Placement
...
r;.D
.....
•••
D.I
••• ••
...
.w.
•••
......
&.=J..
•••••••••••••••••••••••
•••••••••
• •••••••
••••
•••
•••
••
••
••
LocalOSC
.•
••
.
• ••••
II
•• ••
••
•••
•••
•••
•••
•••
•••
••
•••
•••
••
••••
•••••
•••
•• ••••
•••
••••
••••••
•
••••••
•••••••••••••••••••••••
II
Figure 19. MC13156DW Ground Side Component Placement
8-300
MOTOROLA ANALpG IC DEVICE DATA
MC13156
APPLICATIONS INFORMATION
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to
use components from various manufacturers and coil types.
Figures 18 and 19 show the placement for the components
specified in the application circuit (Figure 17). The
applications circuit schematic specifies particular
components that were used to achieve the results shown in
the typical curves and tables but equivalent components
should give similar results.
Input Matching Networks/Components
The input matching circuit shown in the application circuit
schematic is passive high pass network which offers effective
image rejection when the local oscillator is below the RF input
frequency. Silver mica capacitors are used for their high Q
and tight tolerance. The PC board is not dedicated to any
particular input matching network topology; space is provided
for the designer to breadboard as desired.
Alternate matching networks using 4:1 surface mount
transformers or BALUNs provide satisfactory performance.
The 12 dB SINAD sensitivity using the above matching
networks is typically -100 dBm for fmod = 1.0 kHz and
fdev =±75 kHz at fiN =144.45 MHz and fose =133.75 MHz
(see Figure 25).
It is desirable to use a SAW filter before the mixer to
provide additional selectivity and adjacent channel rejection
and improved sensitivity. The SAW filter should be designed
to interface with the mixer input impedance of approximately
1.0 kQ. Table 1 displays the series equivalent single-ended
mixer input impedance.
Local Oscillators
VHF Applications - The local oscillator circuit shown in the
application schematic utilizes a third overtone crystal and an
RF transistor. Selecting a transistor having good phase noise
performance is important; a mandatory criteria is for the
device to have good linearity of beta over several decades of
collector current. In other words, if the low current beta is
suppressed, it will not offer good 11f noise performance. A
third overtone series resonant crystal having at least 25 ppm
tolerance over the operating temperature is recommended.
The local oscillator is an impedance inversion third overtone
Colpitts network and harmonic generator. In this circuit a 560
to 1.0 kQ resistor shunts the crystal to ensure that it operates
in its overtone mode; thus, a blocking capacitor is needed to
eliminate the dc path to ground. The resulting parallel LC
network should "free-run" near the crystal frequency if a
short to ground is placed across the crystal. To provide
sufficient output loading at the collector, a high Q variable
inductor is used that is tuned to self resonate at the 3rd
harmonic of the overtone crystal frequency.
The on--chip grounded collector transistor may be used for
HF and VHF local oscillator with higher order overtone
crystals. Figure 20 shows a 5th overtone oscillator at
93.3 MHz and Figure 21 shows a 7th overtone oscillator at
148:3 MHz. Both circuits use a Butler overtone oscillator
configuration. The amplifier is an emitter follower. The crystal
is driven from the emitter and is coupled to the high
impedance base through a capacitive tap network. Operation
at the desired overtone frequency is ensured by the parallel
resonant circuit formed by the variable inductor and the tap
capacitors and parasitic capacitances of the on-chip
transistor and PC board. The variable inductor specified in
the schematic could be replaced with a high tolerance, high Q
ceramic or air wound surface mount component if the other
components have good tolerances. A variable inductor
provides an adjustment for gain and frequency of the
resonant tank ensuring lock up and startup of the crystal
oscillator. The overtone crystal is chosen with ESR of
typically 80 Q and 120 Q maximum; if the resistive loss in the
crystal is too high, the performance of the oscillator may be
impacted by lower gain margins.
Table 1. Mixer Input Impedance Data
(Single-ended configuration, VCC = 3.0 Vdc, local oscillator drive = 100 mVrms)
Frequency
(MHz)
Series Equivalent
Complex Impedance
(R+jX)
(n)
Parallel
Resistance
Rp
(n)
Parallel
Capacitance
Cp
(pF)
90
190- j380
950
4.7
100
160-j360
970
4.4
110
130- j340
1020
4.2
120
110-j320
1040
4.2
130
97-j300
1030
4.0
140
82-j280
1040
4.0
150
71- j270
1100
4.0
160
59-j260
1200
3.9
170
52-j240
1160
3.9
180
44-j230
1250
3.8
190
38- j220
1300
3.8
MOTOROLA ANALOG IC DEVICE DATA
8--301
II
MC13156
A series LC network to ground (which is VCC) is comprised
of the inductance of the base lead of the on-chip transistor
and PC board traces and tap capacitors. Parasitic
oscillations often occur in the 200 to 800 MHz range. A small
resistor is placed in series with the base (Pin 24) to cancel the
negative resistance associated with this undesired mode of
oscillation. Since the base input impedance is so large a
small resistor in the range of 27 to 68 n has very little effect
on the desired Butler mode of oscillation.
The crystal parallel capacitance, Co, provides a feedback
path that is low enough in reactance at frequencies of 5th
overtone or higher to cause trouble. Co has little effect near
resonance because of the low impedance of the crystal
motional arm (Rm-Lm-Cm). As the tunable inductor which
forms the resonant tank with the tap capacitors is tuned off
the crystal resonant frequency, it may be difficult to tell if the
oscillation is under crystal control. Frequency jumps may
occur as the inductor is tuned. In order to eliminate this
behavior an inductor (Lo) is placed in parallel with the crystal.
Lo is chosen to resonant with the crystal parallel capacitance
(Co) at the desired operation frequency. The inductor
provides a feedback path at frequencies well below
resonance; however, the parallel tank network of the tap
capacitors and tunable inductor prevent oscillation at these
frequencies.
II
UHF Application
Figure 22 shows a 318.5 to 320 MHz receiver which drives
the mixer with an external varactor controlled (307.8 to
309.3 MHz) LC oscillator using an MPS901 (RF low power
transistor in a T0-92 plastic package; also MMBR901 is
available in a SOT-23 surface mount package). With the
50 kn 10 turn· potentiometer this oscillator is tunable over a
range of approximately 1.5 MHz. The MMBV909L is a low
voltage varactor suitable for UHF applications; it is a dual
back-to-back varactor in a SOT-23 package. The input
matching network uses a 1:4 impedance matching
transformer (Recommended sources are Mini-Circuits and
COilcraft).
Using the same IF ceramic filters and quadrature detector
circuit as specified in the applications circuit in Figure 17, the
12 dB SINAD performance is -95 dBm for a fmod = 1.0 kHz
sinusoidal waveform and fdev ±40 kHz.
This circuit is breadboarded using the evaluation PC board
shown in Figures 32 and 33. The RF ground is VCC and path
lengths are minimized. High quality surface mount
components were used except where specified. The
absolute values of the components used will vary with layout
placement and component parasitics.
RSSI Response
Figure 26 shows the full RSSI response in the application
circuit. The 10.7 MHz, 110kHz wide bandpass ceramic filters
(recommended sources are TaKa part # SK107M5-A0-10X
or Murata Erie SFE10.7MHY-A) provide the correct
bandpass insertion loss to linearize the curve between the
limiter and IF portions of RSSI. Figure 25 shows that limiting
occurs at an input of -100 dBm. As shown in Figure 26, the
RSSI output linear from -100 dBm to -30 dBm.
The RSSI rise and fall times for various RF input signal
levels and R20 values are measured at Pin 20 without 10 nF
filter capacitor. A 10 kHz square wave pulses the RF input
signal on and off. Figure 27 shows that the rise and fall times
are short enough to recover greater than 10kHz ASK data;
with a wider IF bandpass filters data rates up to 50 kHz may
be achieved. The circuit used is the application circuit in
Figure 17 with no RSSI output filter capacitor.
Figure 20. MC13156DW Application Circuit
=
=
fRF 104 MHz; flO 93.30 MHz
5th Overtone Crystal Oscillator
r------------,
104 MHz
I
I
I
I
I
I
I
IIL
_ _ _ / ".. ...---_ --"""",,--II
33
RF Input
To Filter
Vee
NOTES: 1.0.1 I1H Variable Shielded Inductor: Coileral! part # M1283-A or equivalent.
2. Capacitors are Silver Mica.
3. 5th Overtone. Series Resonant, 25 PPM Crystal at 93.300 MHz.
4. 0.13511H Variable Shielded Inductor: Coileral! part # 146-05J08S or equivalent.
8-302
MOTOROLA ANALOG IC DEVICE DATA
MC13156
Figure 21. MC13156DW Application Circuit
fRF
=159 MHz; flO =148.30 MHz
7th Overtol)e Crystal Oscillator
(4)
76nH
r------------,
I
I
159 MHz
33
r:--'
I
I
RFlnput
To IF Filter
I
I
I
_--_
I
I
"'/'
""'-. -I
L _ _ _-
VCC
NOTES: 1. O.OSI1H Variable Shielded Inductor: Taka part # 292SN8-T1365Z or equivalent.
2. Capacitors are Silver Mica.
3. 7th Overtone, Series Resonant, 25 PPM Crystal at 14B.300 MHz.
4. 76 nH Variable Shielded Inductor. Coilcra" part # 15!Hl3JOSS or equivalent.
Figure 22. MC13156DW Varactor Controlled LC Oscillator
50k
(6)
~g~~~ul:4T~~rmer
RFlnput
SMA
I
I
I
I
I
I
47k
::c+1.011
r------------,
(1)
II
(2)
1.0M
I
I
I
I
I
22 1--+--.......- - - - ' 1
VEE
I
I
I
L _ _ _-
""
""---_
I
307.8-J09.3 MHz
LC Varactor
Controlled Oscillator
Vec = 3.3 Vdc (Reg)
""'-.-1
NOTES: 1. 1:4 Impedance Transformer: Mini-<:irouits.
2. 50 k PotenUometer, 10 turns.
3. Spring Coil; Coilcra" A05T.
4. Dual Varactor in 80T-23 Package.
5. All other components are surface mount components.
6. Ferrite beads through loop of 24 AWG wire.
MOTOROLA ANALOG IC DEVICE DATA
8-303
MC13156
45 MHz Narrowband Receiver
The above application examples utilize a.10.7 MHz IF. In
this section a narrowband receiver with a 455 kHz IF will be
described. Figure 23 shows a full schematic of a 45 MHz
receiver that uses a 3rd overtone crystal with the on-chip
oscillator transistor. The oscillator configuration is similar to
the one used in Figure 17; it is called an impedance inversion
Colpitts. A 44.545 MHz 3rd overtone, series resonant crystal
is used to achieve an IF frequency at 455 kHz. The ceramic
IF filters selected are Murata Erie part # SFG455A3. 1.2 kn
chip resistors are used in series with the filters to achieve the
terminating resistance of 1.4 kn to the filter. The IF
decoupling is very important; 0.1 IlF chip capacitors are used
at Pins 6, 7, 11 and 12. The quadrature detector tank circuit
uses a 455 kHz quadrature tank from Toko.
The 12 dB SINAD performance is -109 dBm for a fmod =
1.0 kHz and a fdev =±4.0 kHz. The RSSI dynamic range is
approximately 80 dB of linear range (see Figure 24).
Receiver Design Considerations
The curves of signal levels at various portions of the
application receiver with respect to RF input level are shown
in Figure 28. This information helps determine the network
topology and gain blocks required ahead of the MC13156 to
achieve the desired sensitivity and dynamic range of the
receiver system. In the application circuit the input third order
intercept (IP3) performance of the system is approximately
-25 dBm (see Figure 29).
Figure 23. MC13156DW Application Circuit at 45 MHz
r-------------,
~~>~rMP~-[-+--...J
I
I
I
I
10 n
,-_______+-_-{)
a
Carrier
Detect
f----.---.-----l----(") RSSI
Output
10 n
IOn
t----------+--.()
Data Slicer
Hold
10k
Data
L - - - - - - - - + - - O Output
Vcc
-=
100 n
,-_______+_--(">
lOOk
Audio To
G-Message
Filter and
Amp.
Vcc = 2.0 to 5.0 Vdc
NOTES: 1. 0.33 !1H Variable Shielded Inductor. Coilcrait part # 7M3-331 or equivalent.
2. 455 kHz Ceramic Filter: Murata Erie part # SFG455A3.
3.455 kHz Quadrature Tank: Toko part # 7MC8128Z.
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.540 MHz.
5. 0.416 !1H Variable Shielded Inductor: Coilcrait part # 143-1 OJI2S.
6. 1.8 !1H Molded Inductor.
8-304
MOTOROLA ANALOG IC DEVICE DATA
MC13156
Figure 24. RSSI Output Voltage
versus Input Signal Level
Figure 25. S + NIN versus RF Input Signal Level
10
1.8
:g
~
w
1.4
0
~
1.2
::>
1.0
(!)
>
r-
0..
50
en
en
/
~
./
1/
0.8
a: 0.6
0.4
-120
J
V
/
fRF = 45.00 MHz
VCC =2.0Vdc
12 dB SINAD @-109 dBm
(0.8IlVnns)
(See Figure 23)
(!)
~
§?
r-
-100
-80
-80
-40
o
-20
-90
-80
-70
/
0.8
/
0.6
V
"'
en
-30
w
:;;;
;::
=l
i'f
-20
0
25
20
-40
-130
w
15
en
en
10
-
5.0
en
;;:
-
I
I
Ir
If
0 Ir
0 If
lSI Ir
121 If
@22k
@22k
@47k
@47k
@100k
@100k
••
30
«
Vcc = 5.0 Vdc
fc = 144.455 MHz
fLO = 133.755 MHz
Low Loss 10.7 MHz
Ceramic Rller
(See Figure 17)
-80
35
-
-
-20
-20
-40
iill
-80
-80
SIGNAL INPUT LEVEL (dBm)
RF INPUT SIGNAL LEVEL (dBm)
Figure 28. Signal Levels versus
RF Input Signal Level
Figure 29. 1.0 dB Compression Pt. and Input
Third Order Intercept Pt. versus Input Power
10
--t~:::::j::=~~==t:;;:;~
(See Figure 17)
~0~--~----~~~--~~--4-~~~~~
E
~ -~~-~~~+--~--~~~~~~~~~
E
In
~ -10
.....
w
>
w -20
.....
r-
::>
II:
W
0..
-30
::>
0
-40
r-
~
w
-130~--~~~~~~~~~--~--~~--~
__
~
-80
__
~
-70
____L-__- L_ _
-130
-50
RF INPUT SIGNAL LEVEL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
~L-
-40
__"'"
-30
x
~
-50
-80
-70
-100
J
J,
Vcc= 5.0Vdc
fRF1 = 144.4 MHz fRF2 = 144.5 MHz
fLO = 133.75 MHz
PLO = -2.0 dBm
(See Figure 17)
1.0 dB Compo PI.
=-37dBm
/'
=-25dBm
i
.I
..... /
./V
/
./"
-80
I~
~
I
..... V
./V
!!:
II:
_roL-~-L~
II
II:
LO Level = -2.0 dBm
-90
-50
2,
z
.-/
-100
!--
/
/
0.4
-100
-80
Figure 27. RSSI Output Rise and Fall Times
versus RF Input Signal Level
1.0
-10
-40
" ........... N
-50
-110 -100
20
"" r\.
Figure 26. RSSI Output Voltage
versus Input Signal Level
1.2
0.2
-120
"
........
+
en -30
I
RF INPUT SIGNAL (dBm)
0..
II:
"-
~ -20
I
Vcc =5.0 Vdc
fdev = ±75 kHz
fmod = 1.0 kHz
fin = 144.45 MHz
(See Figure 17)
SIGNAL INPUT LEVEL (dBm)
::>
50
en
en
(
~ -10
-40
1.4
~
w
S~N
/'
1.6
-130
.'
-40
-20
o
RF INPUT POWER (dBm)
8-305
MC13156
BER TESTING AND PERFORMANCE
Description
The test setup shown in Figure 30 is configured so that the
function generator supplies a 100 kHz clock source to the bit
error rate· tester. This device generates and receives a
repeating data pattern and drives a 5 pole baseband data
filter. The filter effectively reduces harmonic content of the
baseband data which is used to modulate the RF generator
which is running at 144.45 MHz. Following processing of the
signal by the receiver (MC13156), the recovered baseband
sinewave (data) is AC coupled to the data slicer. The data
slicer is essentially an auto-threshold comparator which
tracks the zero crossing of the incoming sinewave and
provides logic level data at its ouput. Data errors associated
with the recovered data are collected by the bit error rate
receiver and displayed.
Bit error rate versus RF signal input level and IF filter
bandwidth are shown in Figure 31. The bit error rate data was
taken under the following test conditions:
• Data rate
=100 kbps
• Filter cutoff frequency set to 39% of the data rate or 39 kHz.
• Filter type is a 5 pole equal-ripple with 0.5 0 phase error.
• VCC =4.0 Vdc
• Frequency deviation =±32 kHz.
II
Figure 31. Bit Error Rate versus RF
Input Signal Level and IF Bandpass Filter
10-1
==
, .......
w
!<
a:
a:
0
a:
a:
10-8
~ IFFitterBW
VCC-4.0Vde
•
Data Pattern = 2E09 Prbs NRZ ~
Baseband Filter 'e - 50 kHz _
'dev - ±32 kHz
-
110kHz
w
IFFilterBW~
!::
m
a:
w
230kHz
10-5
~
m
'\
10-7
-110
-85
-75
-80
-70
RF INPUT SIGNAL LEVEL (dBm)
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The center section of the board provides an area for
attaching all SMT components to the circuit side and radial
leaded components to the component ground side (see
Figures 32 and 33). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interface circuitry as a particular application dictates.
Figure 30. Bit Error Rate Test Setup
Function Generator
Bit Error Rate Tester
RF Generator
Wavetek Model No. 164
HP3760A or Equivalent
HP8640B
Clock
Out
I
Gen
Clock
Input
1
Rer
Clock
Input
Rer
Data
Input
Generator
Input
Modulation
Input
RF
Output
I
I
SPoie
Bandpass
Filter
-
I
Data Slicer
Output
Mixer
Input
MC13156
UUT
8-306
MOTOROLA ANALOG IC DEVICE DATA
MC13156
Figure 32. Circuit Side View
••••••••••••••••••••••••••••••••••••••
MC13156DW
::::::::::::::::::::::::::
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
:
............
•••.••••.••• ra·
a.1
••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••a
•••••••••••••••
•••••••••••••
•••••••••••.
••
.............
............ ..F
••••••••••••
•••••••••••• a.
••••••••••••
••••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
DSC •••••••
•••••••
• ••••••
-'1-•••••••••••
•••••••
•• ••••••••
••••••••
_.. .......
.lILDC~!
•• ••••••••
••••••••
•• •••••••••
•••••••
• ••••••••
••••••••
•
••••••••••
•• ••••••••
••••••••
••••••••••
••••••••••
•
••••••••
••••••••••
••••••••••••
••••••••••••
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••••••••••••
• ••••••••••
•••••••••••••
•• ••••••••••••
•••••••••••••
••••••••••••
••••••••••••••••••••••••••••••••••••••
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••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
4.0"
Figure 33. Ground Side View
4.0"
MOTOROLA ANALOG IC DEVICE DATA
8-307
®
MOTOROLA
MC13158
Wideband FM IF Subsystem
The MC13158 is a wideband IF subsystem that is designed for high
performance data and analog applications. Excellent high frequency
performance is achieved, with low cost, through the use of Motorola's
MOSAIC 1.5™ RF bipolar process. The MC13158 has .an on-board
grounded collector VCO transistor that may be used with a fundamental or
overtone crystal in single channel operation or with a PLL in multi-channel
operation. The mixer is useful to 500 MHz and may be used in a balanced
differential or single ended configuration. The IF amplifier is split to
accommodate two low cost cascaded filters. RSSI output is derived by
summing the output of both IF sections. A precision data shaper has an Off
function to shut the output off to save current. An enable control is provided
to power down the IC for power management in battery operated
applications.
Applications include DECT, wide band wireless data links for personal and
portable laptop computers and other battery operated radio systems which
utilize GFSK, FSK or FM modulation.
WIDEBAND FM IF
SUBSYSTEM FOR DECT
AND DIGITAL APPLICATIONS
SEMICONDUCTOR
TECHNICAL DATA
• Designed for DECT Applications
• 1.8 to 6.0 Vdc Operating Voltage
FTBSUFFIX
PLASTIC PACKAGE
CASE 873
(Thin QFP)
• Low Power Consumption in Active and Standby Mode
• Greater than 600 kHz Detector Bandwidth
• Data Slicer with Special Off Function
• Enable Function for Power Down ofSattery Operated Systems
ORDERING INFORMATION
• RSSI Dynamic Range of 80 dB Minimum
Device
Operating
Temperature Range
Package
MC13158FTB
TA = - 40 to +85Q C
TQFP-32
• Low External Component Count
Representative Block Diagram
Mix
In2
Mix
In1
NlC
Osc Osc
Emit Base N/C
Mix Out
VCC1
IFln
IF Dec1
IF Dec2
IF Out
VCC2
Lim In
Urn Lim
Dec! Dec2
Urn Quad
Out
Det VEE2
Gain
This device contains 234 active transistors.
8-308
MOTOROLA ANALOG IC DEVICE DATA
MC13158
MAXIMUM RATINGS
Rating
Pin
Power Supply Voltage
16,26
Junction Temperature
Storage Temperature Range
NOTE:
Symbol
Value
Unit
VS(max)
6.5
Vdc
TJMAX
+150
°c
Tstg
-65 to +150
°c
1. Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" provide for actual device operation.
RECOMMENDED OPERATING CONDITIONS (VCC = V2 = V7; VEE = V16 = V22 = V26; Vs = VCC - VEE)
Rating
Pin
Symbol
Value
Unit
2,7
Vs
2.0 to 6.0
Vdc
31,32
Fin
10t0500
MHz
TA
-40 to +85
°c
31,32
Yin
200
mVrms
Power Supply Voltage
TA=25°C
-40°C ~ TA ~ 85°C
16,26
Input Frequency
Ambient Temperature Range
Input Signal Level
DC ELECTRICAL CHARACTERISTICS (TA = 25°C; Vs = 3.0 Vdc; No Input Signal; See Figure 1.)
Characteristic
Total Drain Current
Condition
Pin
Vs = 2.0 Vdc
Vs =3.0Vdc
Vs = 6.0Vdc
See Figure 2
16,26
Symbol
Min
Typ
Max
Unit
ITOTAL
2.5
3.5
3.5
5.5
5.7
6.0
8.5
8.5
9.5
mA
DATA SLICER (Input Voltage Referenced to VEE; Vs = 3.0 Vdc; No Input Signal)
Output Current; V18 LO;
Data Slicer Enabled (OS "on")
V19=VEE
V18 V20
V20 = VSf2
See Figure 4
21
121
-
0.1
1.0
~A
Output Current;
Data Slicer Disabled (OS "off")
V19 = VCC
V20 = VsJ2
21
121
-
0.1
1.0
~
AC ELECTRICAL CHARACTERISTICS (TA = 25°C; Vs = 3.0 Vdc; fRF = 110.7 MHz; fLO = 100 MHz; See Figure 1.)
Characteristic
Condition
MIXER
Yin = 1.0 mVrms
See Figure 5
31,32,1
-
-
Noise Figure
Input Matched
31,32,1
NF
-
Mixer Input Impedance
Single-Ended
See Figure 15
31,32
Rp
Cp
-
Mixer Conversion Gain
Mixer Output Impedance
MOTOROLA ANALOG IC DEVICE DATA
1
-
-
dB
14
-
dB
865
1.6
-
Q
-
pF
22
330
Q
8--309
II
MC13158
AC ELECTRICAL CHARACTERISTICS (continued) (TA = 25'C; Vs = 3.0 Vdc; fRF = 110.7 MHz; fLO = 100 MHz; See Figure 1.)
Characteristic
Condition
IF AMPLIFIER SECTION
IF RSSI Slope
See Figure 8
23
-
0.15
0.3
0.4
/lA/dB
IF Gain
f= 10.7 MHz
See Figure 7
3,6
-
-
36
-
dB
Input Impedance
3
-
-
330
-
(.l
Output Impedance
6
-
-
330
-
(.l
LIMITING AMPLIFIER SECTION
Limiter RSSI Slope
See Figure 9
23
-
0.15
0.3
0.4
IlAIdB
Limiter Gain
f= 10.7 MHz
8,12
-
-
70
-
dB
B
-
-
330
-
(.l
Input Impedance
Figure 1. Test Circuit
e
RFlnput)
110.7MHz >--lI'-4--r-~-_""
LO Input
100 MHz
200 mVrms
1=1_1
1
1:~ 1
MiXer)
OUlput
tJ
330
-3.0Vdc
Inp~~oon
1.0n
50
lOOn
tJ.., .
1.0n
,..:;>
0---0
-3.0Vdc
LimHerv
Input
100 n
50
8-310
MOTOROLA ANALOG IC DEVICE DATA
MC13158
Typical Performance Over Temperature
(per Figure 1)
--
Figure 3. Data Slicer On Output Current
versus Ambient Temperature
Figure 2. Total Supply Current versus
Ambient Temperature, Supply Voltage
<'
g
I-
zw
a:
a:
=>
C,)
~
"-
6.4
6.2
6.0
5.B
"-
5.6
...J
j::!:
5.4
f2..:.
5.2
=>
en
j::!:
..?
5.0
..,.,...,
V . /...V V V
... V V V
",
".
V /'
".
=>
7.0
0
5
6.5
w
C,)
::;
6.0
~
5.5
=>
C,)
20
40
60
BO
100
120
V1B»
Data Slicer "On"
O.OB
0.06
V
~
::;
V
~
/
~
ffi
zw
a:
a:
6.0
C,)
5.0
I-
0
4.0
a:
a:
3.0
en
en
w
~
::;:
40
60
BO
100
-20
0
./'
40
/
~
60
BO
100
-0.6
-40
120
II
,II'
-0.1
~ -0.4
a:
~
20
120
/
/
I
Yin = 1.0 mVrms
Vs =3.0Vdc
fc = 110.7 MHz
fLO = 100 MHz
,I
-20
0
20
40
60
T
l
BO
100
TA, AMBIENTTEMPERATURE (0C)
TA, AMBIENTTEMPERATURE (OC)
Figure 6. Mixer RSSI Output Current versus
Ambient Temperature, Mixer Input Level
Figure 7. Normalized IF Amp Gain
versus Ambient Temperature
-
....-
Yin = 10 mVrms
~ 0.4
z
~
"-
~
Vs =3.0 Vdc
fc = tl0.7 MHz
fLO = 100 MHz
VS=3.0Vdc
f = 10.7 MHz
Yin = 1.0 mVrms
/V
@ -0.2
/
N
~
a:
o
z -0.6
-20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (OC)
MOTOROLA ANALOG IC DEVICE DATA
100
120
...-
/
0
'=
Yin = 1.0 mVrms
./
0.2
120
-
0.6
::;: -0.4
2.0
-40
20
0.1
-0.5
~
0
::;: -0.2
c
w
!:j -0.3
7.0
=>
"=>
-20
z
~
<'
/
0.2
~
".
Figure 5. Normalized Mixer Gain
versus Ambient Temperature
en 0.04
l-
/1'
Figure 4. Data Slicer On Output Current
versus Ambient Temperature
C,)
I-
/
a:
5.0
VIB < V20
V
/
"-
~
TA, AMBIENTTEMPERATURE (OC)
0.12
0.03 40
/'
TA, AMBIENT TEMPERATURE (OC)
=>
0
I-
2.0V
a:
a:
Z
./
-20
Data Slicer "On"
VI9=VEE
V20=VsJ2
B.O
en
a:
a:
l-
B.5
I-
/ ' ./
~
VI9=VCC
Iz 0.10 V20 = VsJ2
w
=>
C,)
<'
g
3.0V
".
4.B
<'
Vs = 6.0 V
-O.B
-40
~
/
-20
0
20
40
60
80
100
120
TA, AMBIENTTEMPERATURE (OC)
8-311
MC13158
tTypical Performance Over Temperature
(per Figure 1)
Figure 8. IF Amp RSSI Output Current versus
Ambient Temperature, IF Input Level
10
- --
~
I-
9.0
UJ
8.0
::>
7.0
I-
VS=3.0Vdc
6.0 f = 10.7 MHz
5.0
Z
a:
a:
(,)
::>
D-
I-
::>
0
(i5
en
a:
4.0
D-
:::;:
«
3.0
~
2.0
-40
«
II
-20
«
-
Yin = 10 mVrms
(,)
~
~
~
Vi~ = 100 ~Vrms
I
2.0 -
I
Yin = 10 mVrms
"I
Vs = 3.0 Vdc
f=10.7MHz
I
I
!.
Yin = 1.0 mVrms
D-
Yin = 1.0 mVrms
~
ffi
I
0
Vi, = 100 ivrms
t:::
:::;:
o
20
40
60
80
100
120
-2.0
-40
::i
o
-20
20
40
60
80
100
TA. AMBIENTTEMPERATURE ('C)
TA. AMBIENT TEMPERATURE ('C)
Figure 10. Total RSSI Output Current versus
Ambient Temperature (No Signal)
Figure 11. Demodulator DC Voltage versus
Ambient Temperature
/
0.55
~
~
~ 1.15
g
D-
~ 0.45
0
(i5
en
....... ./'
-20
/
/
o
/
V
g
1.10
~
o
1.05
gj
1.00
3::>
8:::;:
UJ
o
20
40
60
80
100
120
120
1.20
UJ
/V
0.50
12
-
4.0
§
VS=3.0Vdc
No Input Signal
a:
--' 0.40
j:'S
6.0
::>
a:
a:
::>
8.0
..:::
~~
(,)
0.60
..:::
!z
UJ
-
~
Figure 9. Limiter.Amp RSSI Output Current
ver$US Ambient Temperature, Input Signal Level
Vs = 3.0 Vdc
R17= 51 k _
R15=100k
.....
~r-..
"- r-....
0.95
0.9 0
-40
'""
........
r-..........
I"o
-20
TA. AMBIENT TEMPERATURE ('C)
20
40
60
80
100
120
TA. AMBIENT TEMPERATURE ('C)
SYSTEM LEVEL AC ELECTRICAL CHARACTERISTICS (TA = 25'C; VS = 3.0 Vdc; fRF = 112 MHz; fLO = 122.7 MHz)
Characteristic
12 dB SINAD Sensitivity:
Narrowband Application
Without Preamp
With Preamp
Third Order Intercept Point
1.0 dB Compo Point
Condition
Notes
Symbol
fRF= 112MHz
fmod = 1.0 kHz
fdev = ±125 kHz
SINAD Curve
Figure 25
Figure 26
1
-
fRF1 = 112 MHz
fRF2 = 112.1 MHz
VS= 3.5Vdc
Figure 28
2
Typ
'.Unit
dBm
-101
-113
IIP3
-32
1.0 dB C.Pt.
-39
dBm
NOTES: 1. Test Circuit & Test Set per Figure 24.
2. Test Circuit & Test Set per Figure 27.
8-312
MOTOROLA ANALOG IC DEVICE DATA
MC13158
CIRCUIT DESCRIPTION
General
The MC13158 is a low power single conversion wideband
FM receiver incorporating a split IF. This device is designated
for use as the backend in digital FM systems such as Digital
European Cordless Telephone (DECT) and wide band data
links with data rates up to 2.0 Mbps. It contains a mixer,
oscillator, Received Signal Strength Indicator (RSSI), IF
amplifier, limiting IF, quadrature detector, power down or
enable function, and a data slicer with output off function.
Further details are covered in the Pin Function Description
which shows the equivalent internal circuit and external
circuit requirements.
Current Regulation/Enable
Temperature compensating voltage independent current
regulators which are controlled by the enable pin (Pin 25)
where "low" powers up and "high" powers down the entire
circuit.
Mixer
The mixer is a double-balanced four quadrant multiplier
and is designed to work up to 500 MHz. It can be used in
differential or in single ended mode by connecting the other
input to the positive supply rail. The linear gain of the mixer is
approximately 22 dB at 100 mVrms LO drive level. The mixer
gain and noise figure have been emphasized at the expense
of intermodulation performance. RSSI measurements are
added in the mixer to extend the range to higher signal levels.
The single-ended parallel equivalent input impedance of the
mixer is Rp - 1.0 kn and Cp - 2.0 pF. The buffered output of
the mixer is internally loaded resulting in an output
impedance of 330 n.
Local Oscillator
The on--chip transistor operates with crystal and LC
resonant elements up to 220 MHz. Series resonant, overtone
crystals are used to achieve excellent local oscillator stability.
Third overtone crystals are used through about 65 to 70 MHz.
Operation from 70 MHz up to 180 MHz is feasible using the
on--chip transistor with a 5th or 7th overtone crystal. To
enhance operation using an overtone crystal, the internal
transistor bias is increased by adding an external resistor
from Pin 29 to VEE; however, with an external resistor the
oscillator stays on during power down. Typically, -10 dBm of
local oscillator drive is needed to adequately drive the mixer.
With an external oscillator source, the IC can be operated up
to 500 MHz.
RSSI
The received signal strength indicator (RSSI) output is a
current proportional to the log of the received signal
amplitude. The RSSI current output is derived by summing
the currents from the mixer, IF and limiting amplifier stages.
An increase in RSSI dynamic range, particularly at higher
input signal levels is achieved. The RSSI circuit is designed
to provide typically 85 dB of dynamic range with temperature
compensation.
Linearity of the RSSI is optimized by using external
ceramic bandpass filters which have an insertion loss of
4.0 dB and 330 n source and load impedance. For higher
data rates used in DECT and related applications, LC
bandpass filtering is necessary to acquire the desired
MOTOROLA ANALOG Ie DEVICE DATA
bandpass response; however, the RSSI linearity will require
the same insertion loss.
RSSI Buffer
The RSSI output current creates a voltage across an
external resistor. A unity voltage-gain amplifier is used to
buffer this voltage. The output of this buffer has an active
pull-up but no pull-down, so it can also be used as a peak
detector. The negative slew rate is determined by external
capacitance and resistance to the negative supply.
IF Amplifier
The first IF amplifier section is composed of three
differential stages with the second and third stages
contributing to the RSSI. This section has internal DC
feedback and external input decoupling for improved
symmetry and stability. The total gain of the IF amplifier block
is approximately 40 dB at 10.7 MHz.
The fixed internal input impedance is 330 n. When using
ceramic filters requiring source and loss impedances of
330 n, no external matching is necessary. Overall RSSI
linearity is dependent on having total midband attenuation of
10 dB (4.0 dB insertion loss plus 6.0 dB impedance matching
loss) for the filter. The output of the IF amplifier is buffered
and the impedance is 330 n.
Limiter
The limiter section is similar to the IF amplifier section
except that five differential stages are used. The fixed internal
input impedance is 330 n. The total gain of the limiting
amplifier section is approximately 70 dB. This IF limiting
amplifier section internally drives the quadrature detector
section and it is also brought out on Pin 12.
Quadrature Detector
The quadrature detector is a doubly balanced four
quadrant multiplier with an internal 5.0 pF quadrature
capaCitor between Pins 12 and 13. An external capacitor may
be added between these pins to increase the IF signal to the
external parallel RLC resonant circuit that provides the
90 degree phase shift and drives the quadrature detector. A
single pin (Pin 13) provides for the external LC parallel
resonant network and the internal connection to the
quadrature detector.
Internal low pass filter capacitors have been selected to
control the bandwidth of the detector. The recovered signal is
brought out by the inverting amplifier buffer. An external
feedback resistor from the output (Pin 17) to the input of the
inverting amplifier (Pin 15) controls the output amplitude; it is
combined with another external resistor from the input to the
negative supply (Pin 16) to set the output dc level. For a
resistor ratio of 1, the DC level at the detector output is
2.0 VBE (see Figure 12). A small capacitor C17 across the
first resistor (from Pin 17 to 15) can be used to reduce the
bandwidth.
Data Slicer
The data slicer is a comparator that is designed to square
up the data signal. Across the data slicer inputs (Pins 18
and 20) are back to back diodes.
8-313
II
:
MC13158
A unique feature of the data slicer is that the inverting
switching stages in the comparator are supplied through the
emitter pin of the output transistor (Pin 22 - OS Gnd) to VEE
rather than internally to VEE. This is provided in order to
reduce switching feedback to the front end. A control pin is
provided to shut the data slicer output off (OS "ofF - Pin 19).
With OS "off' pin at VCC the data slicer output is shut off by
shutting down the base drive to the output transistor. When a
channel is being monitored to make an RSSI measurement,
but not to collect data, the data output may be shut off to save
current.
The recovered data signal from the quadrature detector
can be DC coupled to the data slicer DS INl (Pin 18). In the
application circuit shown in Figur~ 1 it will be centered at
2.0 VBE and allowed to swing ± VBE. A capacitor is placed
from DS IN2 (Pin 20) to VEE. The size of this capacitor and
the nature of the data signal determine how faithfully the data
slicer shapes up the recovered signal. The time constant is
short for large peak to peak voltage swings or when there is
a change in DC level at the detector output. For small signal
or for continuous bits of the same polarity which drift close to
the threshold voltage, the time constant is longer.
PIN FUNCTION DESCRIPTION
Pin
Symbol
1
Mix
Out
2
Internal Equivalent Circuit
2
VCCl
~
VCCl
3
IF
In
Mixer Output
The mixer output impedance is 330 n; it
matches to 10.7 MHz ceramic filters with
330 n input impedance.
f--o 1
Mix
Out
-S
26
VEEl
Description/External Circuit Requirements
2
VCCl
64k
50-IFDec2
4
IF
Oecl
5
IF
Oec2
6
IF
Out
I
26
VEEI
~+
4
IFDecl
3
IF In
2
VCCl
26
VEEl
8-314
:::t-~
~
~
-S
Supply Voltage (VCC1)
This pin is the VCC pin for the Mixer, Local
OSCillator, and IF Amplifer. The operating
supply voltage range ,sfrom 1.8 Vdc to
5.0 Vdc. In the PCB layout, the VCC trace
must be kept as wide as possible to minimize
inductive reactances along the trace; it is best
to have it completely fill around the surface
mount components and traces on the circuit
side of the PCB.
IF Input
The input impedance at Pin 3 is 330 n. It
matches the 330 n load impedance of a
10.7 MHz ceramic filter. Thus, no external
matching is required.
IF DEC1 & DEC2
IF decoupling pins. Oecoupling capacitors
should be placed directly at the pins to enhance
stability. Two capacitors are decoupled to the
RF ground VCC1; one is placed between DECl
&OEC2.
IF Output
The output impedance is 330 n; it matches
the 330 input resistance of a 10.7 MHz
ceramic filter.
>----{)
5
IF
Out
MOTOROLA ANALOG IC DEVICE DATA
MC13158
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
7
VCC2
Descrlption/Extemal Circuit Requirements
Internal Equivalent Circuit
Supply Voltage (VCC2)
7o-~--~~----~------~
VCC2
64k
8
Lim
In
9
10
Lim
Dec2
64k
330
Limiter Input
The limiter input impedance is 330 n.
Lim
Dec1
Limiter Decoupling
16o-+--r------~----+_----+
10
Lim
Dec2
11,14,
27 &28
N/C
12
Lim
Out
13
This pin is VCC supply for the Limiter,
Quadrature Detector, data slicer and RSSI
buffer circuits. In the application PC board this
pin is tied to a common VCC trace with VCC1.
VEE2
8
Lim In
9
LimDec1
Decoupling capacitors are placed directly at
these pins and to VCC (RF ground). Use the
same procedure as in the IF decoupling.
No Connects
There is no internal connection to these pins;
however it is recommended that these pins be
connected externally to VCC (RF ground).
Limiter Output
The output impedance is low. The limiter
drives a quadrature detector circuit with inphase and quadrature phase signals.
Quadrature Detector Circuit
Quad
The quadrature detector is a doubly balanced
four-quadrant multiplier with an internal 5.0 pF
capacitor between Pins 12 and 13. An external
capacitor may be added to increase the IF
signal to Pin 13. The quadrature detector pin is
provided to connect the external RLC parallel
resonant network which provides the 90 degree
phase shift and drives the quadrature detector.
15
17
16
Det
Gain
Det
Out
Detector Buffer Amplifier
7~~~--~~r_~
VCC2
15 ()-<~---11----'"
Det
Gain
16 o------~--__+------4_
VEE2
MOTOROLA ANALOG IC DEVICE DATA
This is an inverting amplifier. An external feedback resistor from Pin 17to 15, (the inverting
input) controls the output amplitude; another
resistor from Pin 15 to the negative supply
(Pin 16) sets the DC output level. A 1:1 resistor
ratio sets the output DC level at two VBE with
respectto VEE. A small capacitor from Pin 17 to
15 can be used to setthe bandwidth.
Supply Ground (VEE2)
In the PCB layout, the ground pins (also applies
to Pin 26) should be connected directly to
chassis ground. Decoupling capacitors to V CC
should be placed directly at the ground pins.
8-315
II
MC13158
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
19
OS
"off'
21
OS
Out
Internal Equivalent Circuit
Descrlption/External Circuit Requirements
Data Slicer Off
The data output may be shut off to save current by placing OS "off" (Pin 19) at VCC.
OS Out
21
+--1--022
OSGnd
22
OS
Gnd
18
OS
In1
20
OS
In2
64k
7
VCC2
OSlnl
18
II
19
OS "olr
OS In2
20
16
VEE2
23
ASSI
Buf
24
ASSI
Data Slicer Output
In the application example a 10 k.Q pull-up
resistor is connected to the collector of the
output transistor at Pin 21.
Data Slicer Ground
All the inverting switching stages in the
comparator are supplied through the emitter
pin of the output transistor (Pin 22) to ground
rather than internally to VEE in order to reduce
switching feedback to the front end.
Data Slicer Inputs
The data slicer has differential inputs with
back to back diodes across them. The
recovered signal is DC coupled to OS IN1
(Pin 18) at nominally V18 with respect to VEE;
thus, it will maintain V 18 ± VBE at Pin 18. OS
IN2 (Pin 20) is AC coupled to VEE. The chOice
of coupling capacitor is dependent on the
nature of the data signal. For small signal or
continuous bits of the same polarity, the
response time is relatively large. On the other
hand, for large peak to peak voltage swings or
when the DC level at the detector output
changes, the response time is short. See the
discussion in the application section for
external circuit design details.
RSSI Buffer
A unity gain amplifier is used to buffer the
voltage at Pin 24 to 23. The output of the unity
gain buffer (Pin 23) has an active pull up but no
pull down. An external resistor is placed from
Pin 23 to VEE to provide the pull down.
RSSI
The RSSI output current creates a voltage
drop across an external resistor from Pin 24 to
VEE. The maximum ASSI current is 26 j.tA;
thus, the maximum ASSI voltage using a
100 k.Q resistor is approximately 2.6 Vdc. Figure 22 shows the ASSI Output Voltage versus
Input Signal Level in the application circuit.
160-4..----4---'
VEE2
8-316
23
RSSI
Bul
The negative slew rate is determined by an
external capacitor and resistor to VEE
(negative supply). The ASSI rise and fall times
for various AF input signal levels and A24
values without the capacitor, C24 are displayed
in Figure 24. This is the maximum response
time of the ASSI.
MOTOROLA ANALOG IC DEVICE DATA
MC13158
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
25
Enable
Internal Equivalent Circuit
DescriptionlExternal Circuit Requirements
e~'l}
Enable
The IC regulators are enabled by placing this
pin at VEE.
25crEnable
26
26
VEE1
VEE1
28
Osc
Base
29
Osc
Emitter
20VCC1
7
VCC2
26
VEE1
016
VEE2
2
VCC1
280-Ose
Base
290-Osc
Emitter
26
VEE1
31
32
Mix
In1
Mix
In2
Oscillator Base
This pin is connected to the base lead of the
common collector transistor. Since there is no
internal bias resistor to the base, VCC is
applied through an external choke or coil.
J
[~~~
Oscillator Emitter
This pin is connected to the emitter lead; the
emitter is connected internally to a current
source of about 200 !lA. Additional emitter
current may be obtained by connecting an
external resistor to VEE; IE V2g1R29.
$. ~.
=
Details of circuits using overtone crystal and
LC varactor controlled oscillators are
discussed in the application section.
2
VCC1
,,~~~M pYt --"'~
-2
~~
VCC and VEE ESD Protection
ESD protection diodes exist between the VCC
and VEE pins. It is important to note that
significant differences in potential (> 0.5 VB E)
between the two VCC pins or between the VEE
pins can cause these structures to start to
conduct, thus compromising isolation between
the supply busses. VCC1 & VCC2 should be
maintained at the same DC potential, as
should VEE1 & VEE2·
26
VEE1
MOTOROLA ANALOG IC DEVICE DATA
~
+
~~
Mixer Inputs
The parallel equivalent differential input
impedance of the mixer is approximately 2.0
kn in parallel with 1.0 pF. This equates to a
single ended input impedance of 1.0 kn in
parallel with 2.0 pF.
The application circuit utilizes a SAW filter
having a differential output that requires a
2.0 kn 112.0 pF load. Therefore, little matching
is required between the SAW filter and the
mixer inputs. This and alternative circuits are
discussed in more detail in the application
section.
8-317
II
MC13158
APPLICATIONS INFORMATION
Evaluation PC Board
The evaluation PCB is very versatile and is intended to be
used across the entire useful frequency range of this device.
The center section of the board provides an area for
attaching all SMT components to the circuit side and radial
leaded components to the component ground side (see
Figures 29 and 30). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interlace circuitry as a particular application dictates.
This evaluation board will be discussed and referenced in
this section.
8-318
Component Selection
The evaluation PC board is designed to accommodate
specific components, while also being versatile enough to
use components from various manufacturers and coil types.
Figures 13 and 14 show the placement for the components
specified in the application circuit (Figure 12). The application
circuit schematic specifies particular components that were
used to achieve the results shown in the typical curves and
tables but alternate components should give similar results.
MOTOROLA ANALOG IC DEVICE DATA'
MC13158
Figure 12. Application Circuit
(4) 122.7 MHz
33 p
r5t_h_O~T~C~~S_m~I~__~~
~------------------~~,+
(1)
RF Input
.T 1.011
>--t=:l----t-'----f
112MHz
150
100 n.T
1.0 n
MC1315B
OS Out
OSln2
OS'off"
150
(2)
II
6BOp
Vcc=
2.0 to 5.0 Vdc
2.2 k
NOTES: 1. Saw Filter - Siemens part number Y6970M(5 pin SIP plastic package).
2. An LCR filter reduces the broadband noise in the IF; ceramic filters may be used for data rates under 500 kHz. 4.0 dB insertion loss filters
optimize the linearity of RSSI.
3. The quadrature tank components are chosen to optimize linearity of the recovered signal while maintaining adequate recovered
signal level. 1.5 !lH 7.0 mm variable shielded inductor: Taka part # 292SN8-T1373Z. The shunt resistor is approximately equal to
Q(21tfL), where Q - 18 (3.0 dB BW = 600 kHz).
4. The local oscillator circuit utilizes a 122.7 MHz, 5th overtone, series resonant crystal specified with a frequency tolerance of 25 PPM, ESR
of 120 n max. The oscillator configuration is an emitter coupled butler.
5. The 95 NH (Nominal) inductor is a 7.0 mm variable shielded inductor: Coilcraft part # 15~4J08S or equivalent.
6. 0.68 !lH axial lead chokes (molded inductor): Coilcral! part # 90-11.
7. To enable the Ie, Pin 25 is taken to VEE. The external pull down resistor at Pin 29 CQuid be linked to the enable function; otherwise if it is
taken to VEE as shown, it will keep the oscillator biased at about 500!lA depending on the VCC level.
B. The other resistors and capacitors are surface mount components.
MOTOROLA ANALOG IC DEVICE DATA
8-319
MC13158
Figure 13. Circuit Side Component Placement
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MOTOROLA ANALOG IC DEVICE DATA
MC13158
Figure 14. Ground Side Component Placement
II
MOTOROLA ANALOG IC DEVICE DATA
8-321
MC13158
Input Matching/Components
It is desirable to use a SAW filter before the mixer to
provide additional selectivity and adjac;ent channel rejection.
In a wideband sy~tem the primary sensitivity of the receiver
backend may be achieved before the last mixer. Bandpass
filtering in th~ rimiting IF is costly and difficult to achieve for
bandwidths9reater than 280 kHz.
The SAW filter:should be selected'to easily interface with
the mixer differential. input imped!!r:)ce of approximately
2.0 kg in parallel with 1.0 pF. The PC board is dedicated to·
the Siemens SAW filter (part number Y6970M); the part is
designed for DECT at 112 MHz 1st IF frequency. It is
deSigned for a load impedance of 2.0 ill in parallel with
2.0 pF; thus, no or little input matching is required between
the SAW filter and the mixer.
The Siemens SAW filter has an insertion loss of typically
10 dB and a 3.0 dB bandwidth of 1.0 MHz. The relatively high
insertion loss significantly contributes to the system noise
and a filter having lower insertion loss would be desirable. In
existing low loss SAW filters, the required load impedance is
50 g; thus, interface matching between the filter and the
mixer will be required. Figure 15 is a table of the
. single-ended mixer input impedance. A careful noise
analysis is necessary to determine the secondary
contribution to system noise.
Figure 15. Mixer Input Impedance
(Single-ended)
f
Rs
XS
Rp
Xp
(MHz)
(a)
(a)
(a)
(a)
Cp
(pF)
50
930
-350
1060
-2820
1.1
100
480
-430
865
-966
1.6
1.8
150
270
-400
860
-580
200
170
-320
770
-410
1.9
250
130
-270
690
-330
1.85
300
110
-250
680
-300
1.8
'400
71
-190
580
-220
1.8
500
63
-140
370
-170,
1.9
600
49
-110
300
-130
2.0
System Noise Considerations
The system block diagram in Figure 16 shows the
cascaded noise stages contributing to the system noise; it
represents the application circuit in Figure 12 and a low noise
preamp using a MRF941 transistor (see Figure 17). The
pre!!mp is designed for a conjugately matched input and
output at 2.0 Vdc VCE and 3.0 mAdc Ic. S-parameters at
2.0 V, 3.0 rnA and 100 MHz are:
511 =.0.86, -20
521=9.0, 164 '
512 = 0.02,79
522 =0.96, -12
The bias network sets VeE at 2.0 V and Ic at 3.0 rnA for
VCC = 3.0 to 3.5 Vdc. The preamp operates with 18 dB gain
and 2.7 dB noise figure.
In the cascaded noise analysis the system noise equation
is:
Fsystem = F1
+ [(F2-1)/G1] + [(F3-1)]f[(G1)(G2)]
Note: the proceeding terms are defined as linear
relationships and are related to the log 'form for gain and
noise figure by the following:
F = log-1[(NF in dB)/10] and similarly
G = log-1[(Gain in dB)/10]
The noise figure and gain measured in dB are shown in the
system block diagram. The mixer noise figure is typically
14 dB and the SAW filter adds typically 10 dB insertion. loss.
Addition of a low noise preamp having a 18 dB gain and
2.7 dB noise figure not only improves the system noise figure
but it increases the reverse isolation from the local oscillator
to the antenna input at the receiver. Calculating in terms of
gain and noise factor yields the following:
F1 = 1.86; G1 = 63.1
F2 = 10; G2 = 0.1
F3 = 25.12
Thus, substituting in the equation for system noise factor:
where:
F1 = the Noise Factor of the Preamp
G1 =the Gain of the Preamp
F2 =the Noise factor of the 5AW Filter
G2 =the Gain of the 5AW Filter
F3 the Noise factor of the Mixer
Fsystem = 5.82; NFsystem = 7.7 dB
=
8-322
MOTOROLA ANALOG IC DI;VICE DATA
MC13158
Figure 16. System Block Diagram tor Noise Analysis
Mixer
G1 = 18dB
NF1 =2.7dB
fLo = 122.7 MHz
Figure 17. 112 MHz LNA
. . . - - - - _ - { ) 3.5 Vdc
1000.T
II
LOCAL OSCILLATORS
VHF Applications
The on--<:hip grounded collector transistor may be used for
HF and VHF local oscillator with higher order overtone
crystals. The local oscillator in the application circuit
(Figure 12) shows a 5th overtone oscillator at 122.7 MHz.
This circuit uses a Butler overtone oscillator configuration.
The amplifier is an emitter follower. The crystal is driven from
the emitter and is coupled to the high impedance base
through a capacitive tap network. Operation at the desired
overtone frequency is ensured by the parallel resonant circuit
formed by the variable inductor and the tap capacitors and
parasitic capacitances of the on--<:hip transistor and PC
board. The variable inductor specified in the schematic could
be replaced with a high tolerance, high Q ceramic or air
wound surface mount component if the other components
have tight enough tolerances. A variable inductor provides an
adjustment for gain and frequency of the resonant tank
ensuring lock up and start-up of the crystal oscillator. The
overtone crystal is chosen with ESR of typically 80 nand
120 n maximum; if the resistive loss in the crystal is too high
the performance of oscillator may be impacted by lower gain
margins.
A series LC network to ground (which is VCC) is comprised
of the inductance of the base lead of the on--<:hip transistor
and PC board traces and tap capacitors. Parasitic
oscillations often occur in the 200 to 800 MHz range. A small
resistor is placed in series with the base (Pin 28) to cancel the
MOTOROLA ANALOG IC DEVICE DATA
negative resistance associated with this undesired mode of
OSCillation. Since the base input impedance is so large a
small resistor in the range of 27 to 68 n has very little effect
on the desired Butler mode of oscillation.
The crystal parallel capacitance, Co, provides a feedback
path that is low enough in reactance at frequencies of 5th
overtones or higher to cause trouble. Co has little effect near
resonance because of the low impedance of the crystal
motional arm (Rm-Lm-Cm). As the tunable inductor which
forms the resonant tank with the tap capacitors is tuned "off'
the crystal resonant frequency it may be difficult to tell if the
oscillation is under crystal control. Frequency jumps may
occur as the inductor is tuned. In order to eliminate this
behavior an inductor, La, is placed in parallel with the crystal.
La is chosen to be resonant with the crystal parallel
capacitance, Co, at the desired operation frequency. The
inductor provides a feedback path at frequencies well below
resonance; however, the parallel tank network of the tap
capacitors and tunable inductor prevent oscillation at these
frequencies.
IF Filtering/Matching
In wideband data systems the IF bandpass needed is
greater than can be found in low cost ceramic filters operating
at 10.7 MHz. It is necessary to bandpass limit with LC
networks or series-parallel ceramic filter networks. Murata
offers a series-parallel resonator pair (part number
8-323
MC13158
KMFC545) with a 3.0 dB bandwidth of ± 325 kHz and a
maximum insertion loss of 5.0 dB. The application PC board
is laid out to accommodate this filter pair (a filter pair is used
at both locations of the split IF). However, even using a series
parallel ceramic filter network yields only a maximum
bandpass of 650 kHz. In some applications a wider band IF
bandpass is necessary.
A simple LC network yields a bandpass wider than the
SAW filter but it does reduce an appreciable amount of
wideband IF noise. In the application circuit an LC network is
specified using surface mount components. The parallel LC
components are placed from the outputs of the mixer and IF
amplifier to the VCC trace; internal 330 loads are connected
from the mixer and IF amplifier outputs to DEC2 (Pin 5 and 10
respectively).This loads the outputs with the optimal load
impedance but creates a low insertion loss filter. An external
shunt resistor may be used to widen the bandpass and to
acquire the 10 dB composite loss necessary to linearize the
RSSI output. The equivalent circuit is shown in Figure 18.
Computation of the loaded Q of this LeR network is
Q = Requivalent/X L
where: XL =21tfL and Requivalent is 103 Q
Thus, Q = 4.65
The total system loss is
20 log (103/433) = -12.5 dB
Quadrature Detector
The quadrature detector is coupled to the IF with an
internal 5.0 pF capacitor between Pins 12 and 13. For
wide band data applications, the drive to the detector can be
increased with an additional external capacitor between
these pins; thus, the recovered signal level output is
increased for a given bandwidth
The wideband performance of the detector is controlled by
the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
Figure 18. IF LCR Filter
[1]
Rout
330
Vee
where RT is the equivalent shunt resistance across the LC
Tank
XL is the reactance of the quadrature inductor at the IF
frequency (XL = 21tfL).
The inductor and capacitor are chosen to forrn a resonant
LC tank with the PCB and parasitic device capaCitance at the
desired IF center frequency as predicted by
fc = [2n: (LC p)1/2r1
Rin
330
Vee
The following equations satisfy the 12 dB loss
(1:4 resistive ratio):
(Rext)(330)/(Rext + 330) = Requivalent
Requivalentj (Requivalent + 330) = 1/4
Solve for Requivalenl:
4(Requhialent) := Requivalent
3(Requivalent) = 330
Requivalent = 110
+ 330
.Substitute for Requivalent and solve for Rext: .
330(Rext) = 110(Rext) + (330)(110)
Rext = (330)(110)/220
Rext = 165 Q
The IF is 10.7 MHz although any IF between 10 to 20 MHz
could be used. The value of the coil is lowered from that used
in the quadrature circuit because the unloaded Q must be
maintained in a surface mount component. A standard value
component having an unloaded Q = 100 at 10.7 MHz is
330 nH; therefore the capacitor is 669 pF. Standard values
have been chosen for these components;
[2]
where L is the parallel tank inductor Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a deSign example for a wideband detector
at 10.7 MHz and a loaded Q of 18. The loaded Q of the
quadrature detector is chosen somewhat less than the Q of
the IF bandpass. For an IF frequency of 10.7 MHz and an IF
bandpass of 600 kHz, the IF bandpass Q is approximately
6.4.
Example:
Let the external Cext = 139 pF. (The minimum value here
should be much greater than the internal device and PCB
parasitic capacitance, Cint ~ 3.0 pF). Thus, Cp = Cint +
Cext = 142 pF.
Rewrite equation (2) and solve for L:
L = (0.159)2/(C pfc 2)
.
L = 1.56 ~H; Thus, a standard value is
choosen:
L = 1.56 ~H (tunable shielded inductor)
The value of the total damping resistor to obtain the
required loaded Q of 18 can be calculated by rearranging
equation (1):
RT = Q(2n:fL)
RT = 18(2n:)(10.7)(1.5) = 1815 Q
Rext = 150 Q
C = 680 pF
L
8-324
= 330
nH
MOTOROLA ANALOG IC DEVICE DATA
MC13158
The internal resistance, Rint at the quadrature tank Pin 13
is approximately 13 kn and is considered in determining the
external resistance, Rext which is calculated from
Rext '" ((RTHRint))/(Rint - RT )
Rext '" 2110; Thus, choose the standard value:
Rext '" 2.2 kQ
It is important to set the DC level of the detector output at
Pin 17 to center the peak to peak swing of the recovered
signal. In the equivalent internal circuit shown in the Pin
Function Description, the reference voltage at the positive
terminal of the inverting op amp buffer amplifier is set at
1.0 VBE. The detector DC level, V17 is determined by the
following equation:
V 17 '" [((R 15/R 17)
+ 1)/(R 15/R 17)]
V BE
Thus, for a 1:1 ratio of R15/R17, V17 = 2.0 VBE = 1.4 Vdc.
Similarly for a 2:1, V17 = 1.5 VSE = 1.05 Vdc; and for 3:1,
V17 = 1.33 VSE = 0.93 Vdc.
Figure 19 shows the detector "S-Curves", in which the
resistor ratio is varied while maintaining a constant gain (R17
is held at 62 k). R15 is 62 k for a 1:1 ratio; while R15 = 120 k
and 180 kto produce the 2:1 and 3:1 ratios. The IF signal into
the detector is swept ± 500 kHz about the 10.7 MHz IF center
frequency. The resulting curve show how the resistor ratio
and the supply voltage effects the symmetry of the "S-curve"
(Figure 21 Test Setup). For the 3:1 and 2:1 ratio, symmetry is
maintained with Vs from 2.0 to 5.0 Vdc; however, for the 1:1
ratio, symmetry is lost at 2.0 Vdc.
Figure 19. Detector Output Voltage versus
Frequency Deviation
Data Slicer Circuit
C20 at the input of the data slicer is chosen to maintain a
time constant long enough to hold the charge on the
capacitor for the longest strings of bits at the same polarity.
For a data rate at 576 kHz a bit stream of 15 bits at the same
polarity would equate to an apparent data rate of
approximately 77 kbps or 38 kHz. The time constant would
be approximately 26 J.1s. The following expression equates
the time constant, t, to the external components:
t = 211: (R 18HC 20 )
Solve for C20:
C 20 = 1/211: (R 18)
where the effective resistance R18 is a complex function of
the demodulator feedback resistance and the data slicer
input circuit. In the data input network the back to back diodes
form a charge and discharge path for the capacitor at Pin 20;
however, the diodes create a non-linear response. This
resistance is loaded by the B, beta of the detector output
transistor; beta =100 is a typical value (see Figure 21). Thus,
the apparent value of the resistance at Pin 18 (DS IN1) is
approximately equal to:
R 18 - R17/ 100
where R17 is 82 kn, the feedback resistor from Pin 17 to 15.
Therefore, substituting for R18 and solving for C20:
C 20
= 15.9 (t)/R 17 = 5.04
nF
The closest standard value is 4.7 nF.
Figure 21. Data Slicer Equivalent Input Circuit
!6~00~---~4~00~---~20~0~--~0----~2~00~---40~0----6~00
Vce
FREQUENCY DEVIATION (kHz)
Figure 20. Demodulator uS-Curve" Test Setup
EXT
MOD In
Wavetek Signal
Generator
Model 134
50n
Output
Signal Generator
Fluke 6082A
tc= 10.7 MHz
at =± 500 kHz
RFOut
Sweep Out
Urn In
X Input
Oscilloscope
TEK475
Y
Input
DET
Out
MC13158
MOTOROLA ANALOG IC DEVICE DATA
8-325
II
MC13158
SYSTEM PERFORMANCE DATA
RSSI
In Figure 22, the RSSI versus RF Input Level shows the
linear response of RSSI over a 65 dB range but it has
extended capability over 80 dB from -80 dBm to +10 dBm.
The RSSI is measured in the application circuit (Figure 12) in
which a SAW filter is used before the mixer; thus, the overall
sensitivity is compromised for the sake of selectivity. The
curves are shown for three filters having different
bandwidths:
1) LCR Filter with 2.3 MHz 3.0 dB BW (Circuit and
Component Placement is shown in Figure 12)
2) Series-Parallel Ceramic Filter with 650 kHz 3.0 dB BW
(Murata Part # KMFG-545)
3) Ceramic Filter with 280 kHz 3.0 dB BW.
Figure 22. RSSI Output Voltage versus
Signal Input Level
<3'
~
LU
Cl
!:i§Z
~
13
o
Ci.i
~
3.0
VCC =4.0Vdc
2.7 fRF= 112MHz
2.4 fLO = 122.7 MHz
flF = 10.7 MHz
2. I See Figure 12 for LCR filler
I.B
1.5 Sertes-Parallel
Ceramic Fi~er "1.2
0.9
0.6
,
0.3
......
o
•
.::- 30
~~
en
III!iI
0
0
25
LU
:;
;:::
...J
...J
if
0
~
w
en
0
20
~
Ir@22k
If@22k
Ir@47k
If@47k
Ir @lOOk
If@ lOOk
IS
10
cc
~ 5.0
a:
-40
-60
.rn
-80
SINAD Performance
Figure 24 shows a test setup for a narrowband
demodulator output response in which a C-message filter
and an active de-emphasis filter is used following the
demodulator. The input is matched using a 1:4 impedance
transformer. The SINAD performance is shown in Figure 25
with no preamp and in Figure 26 with preamp (Preamp Figure 16). The 12 dB SINAD sensitivity is -101 dBm withho
preamp and -113 dBm with the preamp .
t#'
/. ~
~~
a
Ceramic Filler
./ A
. / Aer
35
RF INPUT SIGNAL LEVEL (dBm)
. /~
Y Q
U>
::t
-20
J
~
Figure 23. RSSI Output Rise and Fall Times
versus RF Input Signal Level
LCR; Rex! = 150 Q
"/
-90 -BO -70 -60 -50 -40 -30 -20 -10
10
20
SIGNAL INPUT LEVEL (dBm)
Figure 24. Test Setup for Narrowband SINAD
Input
HP8657B
fc = 112 MHz
fmod= 1.0 kHz
df = ±125 kHz
HP8657B
fc= 122.7 MHz
PLO = -6.0 dBm
8-326
Malch
MCI315B
IF 3.0 dB BW = 280 kHz
LO
Outpul
MOTOROLA ANALOG IC DEVICE DATA
MC13158
Figure 25. S+N+D, N+D, N
versus Input Signal Level (without preamp)
Figure 26. S+N+D, N+D, N versus
Input Signal Level (with preamp)
10
10
S+N+D
o
~ -10
~ -20
~
i ~:
-50
-60
-70
-120
I
V""
VS=3.0Vdc
'dey = ±125 kHz
'mod = 1.0 kHz
'RF= 112 MHz
IF 3.0 dB BW = 280 kHz
./
,
""\ \.
o
I
N+D_ _
-
-10
~
z -20
z~ -30
~
z -40
J;
1\
\
-100
'-
/
,,"
\
\
\
-so
-60
N
-80
S+N+D
-60
-40
-70
-120
o
-20
N+D
"-
VS=3.0Vdc
'dey =±125 k H z 'mod = 100kHz
'RF=112MHz IF 3.0 dB BW =280 kHz
N
-80-60
-100
RF INPUT SIGNAL (dBm)
-40
-20
o
RF INPUT SIGNAL (dBm)
Figure 27. Input IP3, 1.0 dB Compression pt. Test Setup
MIXER
(
FETProbe
TEKP6201
270
~--~~--~-------'Th
50
Spectrum
Analyzer
Mini-Circuits ZSFG-4
4 Way Zero Degree
Combiner
Local
Oscillator
HP8657B
iLO-122.7 MHz @-6.0dBm
Figure 28. -1.0 dB Compression Pt. and Input
Third Order Intercept
-10
1.0 dB Compo Pt. =-39 dBm
-20
iii' -30
z
ci -40
+
z
ci -50
:
.........
~/
-80
/
-60
Vs =3.5 Vdc
fRF1 = 112 kHz
'RF2 = 112.1 kHz
'LO =122.7 MHz
PLO =-6.0 dBm
See Figure 27
/'
-60
-70
/ ' / ' IP3 =-32 dBm
/'
~
+
~
w
..".
. /V
:Eo
A . . .'
V
-so
-40
-30
-20
RF INPUT SIGNAL LEVEL (dBm)
MOTOROLA ANALOG IC DEVICE DATA
8-327
II
MC13158
Figure 29. Circuit Side View
II
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------:----3.8"
8-328
----------I~I
MOTOROLA ANALOG IC DEVICE DATA
MC13158
Figure 30. Ground Side View
II
MOTOROLA ANALOG IC DEVICE DATA
8-329
®
ItIIOTOROLA
MC13159
Advance Information
Wideband. FM IF Amp
WIDEBANO FM IF
SUBSYSTEM FOR PHS
AND DIGITAL
APPLICATIONS
The MC13159.is a wideband FMIF subsystem that is designed for high
performance data and digital applications. Excellent high frequency
performance is achieved, with .low cost, through the use of Motorola's RF
bipolar process. The MC13159 includes a mixer, Local Oscillator Buffer
amplifier, IF amplifier, Limiter amplifier and RSSI functions. ThE;! mixer is
useful for 240 MHz input used In a single-endedlbalanced differential
configuration. The IF and Limiter amplifier are separated for using the
external filler'in series or connecting directly by an external capacitor. RSSI
output is derived by summing the output of both IF and Limiter sections. An
enable control is provided to power down the IC for power management in
battery operated applications.
Applications are suitable for PHS, DECT, PDC, GSM, PCS, wideband
wireless data links arid other battery operated radio systems.
SEMICONDUCTOR
TECHNICAL DATA
• Designed for ~HS Applications
• 2. 7to 5.5 V Operating Voltage
DTBSUFFIX
PLASTIC PACKAGE
CASE948F
(TSSOP-16L)
• Low Drain Current: 5.5 mA (Typ)
• Wide Input Dynamic Range of Mixer (Maximum -16 dBm Input)
• Enable Function for Power Down Mode
• Over 80 dB of RSSI Dynamic Range (AC Coupi'ing BetWeen IF Amplifier
and Limiter Amplifier)
ORDERING INFORMATION
• Low External Component Count
Device
Operating
Temperature Range
Package
MC13159DTB
TA = -300 to +85°C
TSSOP-16L
, Simplified Application
Mix
Oecoup
Vee
RSSI
LlMOec2
LlMout
LlMOec1
LlMin
This device contains 164 active transistors.
8-330
MOTOROLA ANALOG IC DEVICE DATA
MC13159
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
VS(max)
6.0
Vdc
Junction Temperature
TJmax
150
°C
Tstg
-65 to +150
°C
Unit
Storage Temperature Range
NOTE:
ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Symbol
Value
Power Supply Voltage
Rating
Vs
2.7 to 5.5
Vdc
Input Frequency
fin
10 to 600
MHz
Ambient Temperature Range
TA
-30 to +85
°C
Input Signal Level at Local Input
Yin
-10
dBm
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, Vs = 3.0 V; No Input Signal)
Conditions
Symbol
Min
Typ
Max
Unit
Total Drain Current 1
Characteristics
Active Mode
ICCl
4.5
5.5
7.5
mA
Total Drain Current 2
Disable Mode
ICC2
-
0.1
10
IlA
50 Q Termination
Input Matched
-
11
14
21
17
dB
Noise Figure
Input Matched
NF
14
-
dB
Mixer Input Impedance
Single-Ended
Rp
Cp
-
400
4.0
-
pF
AC ELECTRICAL CHARACTERISTICS
Characteristics
Conditions
MIXER (TA = 25°C; Vs = 3.0; fRF = 240 MHz, fLO = 229.3 MHz)
Mixer Conversion Gain
-
-
Q
Mixer Output Impendance
-
-
-
330
-
Q
1.0 dB Gain Compression
@Mixin
Vicp
-16
-
dBm
3rd Order Input Intercept
50 Q Termination
IIP3
-
-B.O
-
dBm
32
36
45
dB
-
330
-
Q
-
330
-
Q
dB
IF AMPLIFIER SECTION (TA = 25°C; Vs = 3.0 V; flF = 10.7 MHz)
IF Gain
!= 10.7 MHz
Input Impedance
-
Output Impedance
-
-
LIMITING AMPLIFIER SECTION (TA = 25°C; Vs = 3.0 V; !IF = 10.7 MHz)
!=10.7MHz
-
-
70
-
Input Impedance
-
-
-
330
-
Q
Output Swing
-
-
400
500
600
mVpp
Output Rise TIme
-
-
-
10
-
ns
Output Fall TIme
-
-
-
20
-
ns
Limiter Gain
RSSI SECTION (TA= 25°C; Vs = 3.0 V; flF = 10.7 MHz)
-
-
10
14
18
mY/dB
RSSI Output DC Voltage 1
No Input Signal
-
0.8
0.9
1.0
V
RSSI Output DC Voltage 2
VIF=-85 dBm
-
0.82
0.95
1.02
V
RSSI Output DC Voltage 3
VIF=-80 dBm
-
0.85
1.0
1.15
V
RSSI Output DC Voltage 4
VIF=-40 dBm
-
1.4
1.5
1.6
V
RSSI Output DC Voltage 5
Vin=OdBm
-
1.95
2.1
2.25
V
RSSISlope
MOTOROLA ANALOG IC DEVICE DATA
8-331
II
MC13159
Figure 1. Test Circuit
10 n
RFin~
240MHZ~
501
39p
II
5
0n
Vee
-
'U
50
_
-
Local
esc Input
229.3 MHz
-10dBm
8-332
MOTOROLA ANALOG IC D.EVICE DATA
MC13159
Figure 2. Test Circuit for Evaluation
Vmixo
10 n
10n
VIF
~l1lFin
10.8 MHz
10.8Mixoutt:r~
MHz
~
~
50
330
RFin
248.5 MHz
HOOP
39 P
r
100 P
:;r:
-
iF1
I
1 0n
100 p
-=-
T.P
10k
I
39P
10P
LlMout
10.8 MHz
0.5 Vpp
-=-
RF Input Matching Circuit
(To
Pin 16)
1
Local Osc Input
237.7 MHz
NOTES: 1. CF1: Murata CFEC10.8MK1
(single filter application) or Murata
CFEC10.8MG1 (dual filters application)
2. CF2: Murata CFEC10.8ME1 (dual
filters application)
@:
o:
BNC (unless otherwise specified)
Banana Jack
NOTE:
All resistors and capacitors are the chip components
except coupling at CF2.
Text boards are for the TSSOP package and socket.
MOTOROLA ANALOG IC DEVICE DATA
8-333
MC13159
PIN FUNCnON DESCRIPTION
1
1 Vee
MixOecoup
16
MiXjn
2
VCC
3
LOin
16
1
Vee 1
~ sift'
1
1
1 -=1
.
-=- 1
1
Mixer Decoupling
Mixer decoupling pin. 220 pF is decoupled to the RF
ground. This pin also can be used for differential input
with Mixin.
Mixer Input
Input impedance is about 400 Q at 240 MHz.
Single-ended matching section at 240 MHz is
referenced at !!pplication circuit.
Supply Vohage
Supply voltage range range is from 2.7 Vdc to
5.5 Vdc. 1.0 nF of decoupling capacitor is placed
directly at this pin to reduce the floor noise.
Local Oscillator Input
Connected to extemallocal oscillator. Input
impedance is about 900 Q at 230 MHz.
3
-=4
RSSI
RSSI
The RSSI current creates a· voltage drop across an
internal 15 k11 resistor.
II
4
-=5
7
-=1
1
Vee 1
1
1
LlMOec2
LlMOec1
8
8
LlMin
6
LlMout
7
1
1
1
-=-1
1
1
Limiter Decoupllng
Limiter decoupling pins. Oecoupling capacitors are
connected to the RF ground, and one is placed
between Oec1 and Oec2.
5
Limiter Input
The input impedance is 330 Q; it matches the
330 input resistance of a 10.7/10.8 MHz ceramicfiiter.
Limiter Output
The output level is about 0.5 Vpp.
MOTOROLA ANALOG IC DEVICE DATA
MC13159
PIN FUNCTION DESCRIPTION (continued)
Pin
9
Symbol
Internal Equivalent Circuit
~ ~o
f
10
11
~
12
12
IFin
10
13
300flA
,, Vee
,,,Vee Vee
,,
IFOec2
IFOecl
A
la, .
Enable
"-..j
~
14
Mixout
t-L!,
,
Vee
Enable
The Ie regulators are enabled by placing this pin at
VEE·
,,
,
Vee
MOTOROLA ANALOG IC DEVICE DATA
I
I
I
I
I
I
I
220
-
VEE
IF Input
The input impedance is 330 Q; it matches the
330 input resistance of a 10.7/10.8 MHz ceramic filter.
-=,
'----
~700flA
15
IF Decoupling
IF decoupling pins. Oecoupling capacitor is connected
from Oecl to the RF groun.... and one is placed
between Oecl and Oec2.
11
Vee
M~
9
'~
~
13
IF Output
The output impedance is 330 Q; it matches the
330 input resistance of a 10.7/10.8 MHz ceramic filter.
,,
Vee,
,,
~3~,
,,-= -=
,, Vee
,, .
,,
,, -=
Description
,,
,
Vee ,
,,
,,
,
-= ,
Vee
IFout
-,
~
-=
....._".
",
,';~
Mixer Output
The mixer output impedance is 330 Q; it matches the
330 input resistance of a 10.7/10.8 MHz ceramic filter.
14
f"
'
.
"
Supply Ground
8-335
®
MOTOROLA
MC13173
Infrared Integrated
Transceiver IC
The MC13173 is a low power infrared integrated system (IRIS). It is a
unique blend of a split IF wideband FM receiver and a specialized infrared
LED transmitter. This device was designed to provide communications
between portable computers via a half duplex infrared link at data rates up to
200kbps.
The receiver includes a mixer, IF amplifier and limiter and data slicer. The
IF amplifier is split to accommodate two low cost cascaded filters. The RSSI
output is derived by summing the output of both IF sections.
The transmitter section includes a frequency synthesizer, FSK modulator,
harmonic low pass filter and an IR LED driver.
INFRARED
TRANSCEIVER
SEMICONDUCTOR
TECHNICAL DATA
• Transmitter Operates in Two Modes:
- OnlOff Pulsing for Remote Control
- FSK Modulation at 1.4 MHz for Data Communications
• Over 70 dB of RSSI Range
FTBSUFFIX
PLASTIC PACKAGE
CASE 873
(ThinQFP)
• Split IF for Improved Filtering and Extended RSSI Range
• Digitally controlled Via a Six Line Interface Bus
• Individual Circuit Blocks Can Be Powered Down When Not In Use for
Power Conservation
•
ORDERING INFORMATION
Device
MC13173FTB
Operating
Temperature Range
Package
TA = - 40° to +85°C
TQFP-32
Simplified Block Diagram
Ma
PLL
Tx
PLL
T
Data
In
E
IRLED
Driver
24
12M
VEE1
LED Driver
Feedback
VEE3
Data Out
R
RFln1
VEE2
RFln2
Data
Slicer In
Mixer
Out
Demod
Quad Coil
Carrier
Detect
IF In
IF
Dec1
IF
Dec2
IF
Out
VCC2
Lim
In
Lim
Dec1
Urn
Dec2
This device contains 914 active transistors.
8-336
MOTOROLA ANALOG IC DEVICE DATA
MC13173
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC-VEE
6.0
Vdc
Junction Temperature
TJ
150
Storage Temperature
Tstg
-55 \0 +150
'c
'c
Power Supply Voltage
NOTE: Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" table provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Symbol
Value
Unit
VCC-VEE
2.7 to 5.5
Vdc
TA
-40 to +85
'c
Ambient Temperature Range
DC ELECTRICAL CHARACTERISTICS (TA
unless otherwise noted.)
Characteristic
Supply Current (See Table 2)
Receive Mode
Communications Mode
AN Mode
Standby Mode
I
=+25'C, VCC =3.3 Vdc, fREF =32.768 kHz. Measured using test circuit in Figure 1,
Control Pin
Logic State
T
0
1
1
0
Master PLL Charge Current
R
1
0
0
0
Pin
Symbol
7,12
ICC
E
0
0
1
0
31
IMA
Min
Typ
Max
Unit
-
9.0
8.0
rnA
-
6.5
4.75
1.5
<10
-
nA
-
±25
-
~
-
DATA SLICER
Data Slicer Threshold Voltage
Maximum Pull-Down Current
CARRIER DETECT
Carrier Detect Threshold Voltage
Maximum Pull-Down Current
TRANSMITTER
Maximum Pull-Up Current
25
IOH
5.8
7.0
-
Maximum Pull-Down Current
25
IOL
150
700
~
DC Output Voltage
24
Vo
200
30
ITX
-
mV
Transmit PLL Charge Current
-
±25
rnA
~
AC ELECTRICAL CHARACTERISTICS (TA = +25'C, VCC = 3.3 Vdc, fREF = 32.768 kHz. Measured using test circuit in
Figure 1, unless otherwise noted.)
Characteristic
TRANSMITTER
Upper Sideband Frequency (Mark)
24
Lower Sideband Frequency (Space)
24
Upper and Lower Sideband Amplitude
24
fHI
-
1.427
-
fLO
-
1.317
-
MHz
VSB
40
54
70
mVrrns
MHz
RECEIVER
Receiver Sensitivity - 12 dB SINAD
MIXER
Mixer Conversion Gain
Mixer Output Impedance
MOTOROLA ANALOG IC DEVICE DATA
8-337
•
MC13173
AC ELECTRICAL CHARACTERISTICS (continued) (TA = +25°C, VCC = 3.3 Vdc, fREF = 32.768 kHz. Measured using test circuit in
Figure I, unless otherwise noted.)
I
Characteristic
Pin
Symbol
Min
Max
Typ
Unit
IF AMPLIFIER
IF Amplifier Gain
8,11
-
-
54
16
-
-
275
IF Amplifier RSSI Slope
-
dB
nAldB
330
Zo
-
-
20
-
!LA
16
-
-
70
-
dB
Input Impedance
13
ZIN
Limiter RSSI Slope
16
-
RSSI Current Range
16
RSSI Dynamic Range
16
Input Impedance
8
ZIN
Output Impedance
11
RSSI Current Range
16
RSSI Dynamic Range
330
n
n
LIMITING AMPLIFIER
-
-
330
-
n
360
-
nAldB
-
20
-
58
!LA
dB
Figure 1. Test Circuit
10k
10k
II
36k
MV209
Vee
~iOk
~'-o...._-+--1----L.1-'
~~ Fl Vee .
~ o-ra.l~F~8~
1
9
33011f 5011
Vee
8-338
lOOn
Vee
MOTOROLA ANALOG IC DEVICE DATA
MC13173
CIRCUIT DESCRIPTION
General
The MC13173 infrared transceiver integrates a split IF
wideband FM receiver and an IR LED transmitter into a single
IC. The transmitter is comprised of an FSK modulator,
harmonic low pass filter, and IR LED driver. The receiver
consists of a mixer, IF amplifier and limiting IF, detector, and
data slicer. It includes RSSI and carrier detect functions.
The transmitter is capable of two modes of operation. It
was primarily designed for use in the Communications Mode,
which enables pOint-to-point data links, such as the
communication from keyboard to computer, or for the
exchange of data between portable computers. In this mode
it is capable of 200 kbps half duplex FSK operation.
The transmitter can also operate in an "AN" Mode, which
pulses the LED on and off with no carrier. (See Figure 11).
Digital Interface Bus
The MC13173 is controlled via a six line 3.3 V digital
interface bus. That includes three control pins, data in and
out pins, and a carrier detect pin. Listed below is a brief
description of each pin and its function.
Table 1. Digital Interface Pin Descriptions
Symbol
110
28
Transmit Enable
T
I
High - Transmitter is enabled
Low - Transmitter is disabled
27
Data In
01
I
Data Input - 38.2 kbps
Communication Mode
3
Receive Enable
R
I
High - Receiver is enabled
Low - Receiver is disabled
22
Data Out
DO
Carrier Detect
CD
a
a
Demodulated Output Signal
17
26
Transmit Modulation Enable
E
I
High - Transmitter is in AN Mode
Low - Transmitter is in
Communications Mode
Pin
Pin Name
This transceiver was designed for use in battery powered,
hand-held consumer products. To minimize power
consumption, the digital interface enables individual system
Description
High - Carrier is present
Low - Carrier is not present
blocks to be powered down while not in use. The following
diagram shows the mode of the IC and the power state of
each circuit block for a given set of control levels.
Table 2. Power State Table
Control
Pins'
Circuit Block Power States
(See Figures 2 and 3)
Master
VCO
FSK
Modulator
Off
Off
Receiver
LED
Driver
Supply
Current
(Typical)
Off
Off
10nA
T
R
E
0
0
0
OFF
0
0
1
OFF
Off
Off
Off
Off
701lA
0
1
X
Receive
On
Off
On
Off
6.5mA
1
1
1
Receive
On
Off
On
On
7.5mA
1
1
0
Transmit - Comm Mode
On
On
On
On
9.0mA
1
0
0
Transmit - Comm Mode
On
On
Off
On
4.75mA
1
0
1
Transmit - AN Mode
Off
Off
Off
On
1.5mA
Mode
• With Data In Pin Low
MOTOROLA ANALOG IC DEVICE DATA
8-339
II
MC1317.3
Master VCO/PLL
The master VCO provides the reference frequency for the
FSK modulator and the LO frequency for the receiver
downconverter. With a 32.768 kHz input frequency to the
master VCO on Pin 1, the LO frequency for the receiver will
be at 12.075 MHz. The reference frequency for the FSK
modulator will be at approximately 1.1 MHz. The master VCO
and FSK modulator are not used when the transmitter is used
in AN mode, and both are powered down.
Receiver Description
The single conversion receiver portion of the MC13173 is
low power and wideband, and incorporates a split IF. This
section includes a mixer, IF amplifier, limiting IF, quadrature
detector and data slicer.
Mixer
The mixer is a double balanced four quadrant multiplier. It
can be driven either differentially or single-ended by
connecting the unused input to the positive supply rail.
The buffered output is internally loaded for an output
impedance of 330 Q for use with a standard ceramic filter.
IF Amplifier
The first IF. amplifier section is composed of three
differential stages with the second and third stages
contributing to the RSS!. This section has internal DC
feedback and external input decoupling for improved
symmetry and stability. The total gain of the IF amplifier block
is approximately 40 dB. The fixed internal input impedance is
330 Q for use with a 10.7 MHz ceramic filter. The output of the
IF amplifier is buffered and the impedance is 330 Q.
Limiter
The limiter section is similar to the IF amplifier section,
except that four stages are used with the last three
contributing to the RSS!. This IF limiting amplifier section
drives the quadrature detector internally.
RSSIICarrier Detect
The received signal strength indicator (RSSI) outputs a
current proportional to the log of the received signal
amplitude. The RSSI current output is derived by summing
the currents from the IF and limiting amplifier stages. An
external resistor sets the output voltage range.
The carrier detect threshold is set at approximately
1.2 Vdc. When the RSSI level exceeds that threshold, the
carrier detect output will go high. A large resistor may be
added externally between the comparator output and the
positive input for hysteresis.
Quadrature Detector
The demodulator is a conventional quadrature type with
an external LC tank driven through an internal 5 pF capacitor.
The output is buffered to give an output impedance of less
than 1.0 kQ at an average DC level of around 1.1 V.
Data Slicer
The data slicer is designed to square up the data signal. It
is self centering at about 1.1 V, and clips at about 0.75 V and
1.45 V. There is a short time constant for large peak-to--peak
voltage swings or when there is a change in DC level at the
detector output. The time constant is longer for small signals
or for continuous bits of the same polarity which drift close to
the threshold voltage.
Transmission Description
The MC13173 uses a dual modulus PLL to frequency shift
key (FSK) modulate the baseband digital input signal,
producing the necessary logic high and low frequencies for
transmission. The transmit frequency for a logic high is
1.427 MHz, and the frequency for a low is 1.317 MHz with a
32.768 kHz reference frequency.
FSK Modulator
In the communications mode, the FSK modulator uses the
reference frequency from the Master VCO to produce the two
frequencies required for a logic high and a logic low. In the
AN mode, the FSK modulator is not used and is powered
down.
LED Driver Stage
A low pass filter following the FSK modulator removes the
undesired harmonic frequencies from the square-wave
output of the divider circuits in PLLs. The resulting sinusoidal
waveforms are fed into a unity gain difference amplifier,
which drives the base of an external transistor, modulating
the IR LED.
In AN mode, the data is input directly into the inverting
input of the op amp, and the low pass filter is not used.
MOTORO,LA ANALOG IC DEVICE DATA
MC13173
Figure 2. Transmitter Block Diagram
Vcc
Vcc
-, r---------I
II
II
II
I
I
I
LED Driver
Stage
IILL-,
Harmonic
l , LPF
14--1--4---+---1 + 10
LED
Driver
~
II
I
>!-+----f
I,
"
___ --I L
Data In
(CommMode)
Data In
(AN Mode)
fR = 32.768 kHz
flo = 67~11 fA
Data High: fM1 = 11 ~1O fLO
Data Low: fM2 =
II
rriho fLO
Figure 3. Receiver Block Diagram
Carrier
Detect
RSSI
Data
Output
Vcc
MOTOROLA ANALOG IC DEVICE DATA
8-341
MC13173
Table 3. PIN FUNCTION DESCRIPTION (TA = 25°C, VCC = 5.0 Vdc, fREF = 32.768 kHz, fMOD = 32.768 kHz)
Pin
Symbol
Description
12M
VCO for Master PLL.
Internal Equivalent
Circuit
Waveform
(Measured using a
low capacitance FET
probe. Standard
oscilloscope probes
can pull oscillator off
frequency. See
Figure 14.)
2,
21,
23
VEE
DC ground. Should be
connected to a
continuous ground
plane on the PCB.
3
R
Receive Enable Pin.
See Tables 1 & 2.
4,5
RF In1
RFln2
RF Input to the mixer.
1.375 MHz average
carrier frequency with
± 50 kHz deviation.
"
Vee
4
5
II
VEE
6
Mixer
Out
10.7 MHz IF
ZO=3300
RFln=-20dBm
Modulation =
32.768 kHz
6
VEE
7,
12
VCC
Supply voltage and
RF ground, should be
decoupled to VEE.
8
IFln
IF input impedance is
3300.
RF In = - 20 dBm
Modulation =
32.768 kHz
8-342
Vee
10
MOTOROLA ANALOG IC DEVICE DATA
MC13173
Table 3. PIN FUNCTION DESCRIPTION (continued) (TA = 25°C, VCC = 5.0 Vdc, fREF = 32.768 kHz, fMOD = 32.768 kHz)
Pin
Symbol
9,
IF Dec
10
11
IF Out
Internal Equivalent
Circuit
Description
IF decoupling as
shown in Figure 15.
Waveform
See Circuit for Pin 8.
IF Output.
Vee
Zo=330Q.
-20 dBm RF input
level. Output is
sinusoidal with lower
drive levels.
t--~VV'v~t--D
11
VEE
13
Lim In
Limiter input.
lin = 330 Q.
15
13
14,
15
Lim Dec
External limiter
decoupling as shown
in application circuit.
16
RSSI
Received Signal
Strength Indicator
Output. (See
Figure 13)
17
Carrier
Detect
Logic output of the
carrier detect
comparator.
18
Quad
Coil
Quadrature tuning
circuit.
14
VEE
II
~17
VEE
Modulated 10.7 MHz
IF.
Measured with a low
capacitance FET
probe.
19
Demod
Demodulated signal
output measured at
. the pin (before
filtering).
Modulation =
32.768 kHz
sine wave.
MOTOROLA ANALOG IC DEVICE DATA
MC13173
Table 3. PIN FUNCTION DESCRIPTION (continued) (TA = 25°C, VCC = 5.0 Vdc, fREF '= 32.768 kHz, fMOD = 32.768 kHz)
Internal Equivalent
Circuit
Pin
Symbol
Description
20
Data
Slicer In
Input from the
receiver demodulated
output.
22
Data
Out
Waveform
Output from the
receiver data slicer.
Modulation =
32.768 kHz
sine wave.
RF input driven by
frequency generator.
See also Figure 10.
.<)
24
LED
Driver
Feedback
Feedback for the LED
driver op amp.
25
IRLED
Driver
Output of the unity
gain output buffer in
Communications
Mode. See Figure 11
for transmit output in
NVmode.
Vee
24
Modulation =
32.768 kHz
square wave.
II
25
25k
VEE
26
E
Transmit Modulation
Enable.
See Tables 1 & 2.
27
Data In
Modulation input for
transmit data.
28
T
Transmit Enable pin.
. See Tabl~ 1 & 2.
29
14MHz
Ref
VCOforFSK
Modulator phase:
locked loop.
..,,:
"
.-"
'"
i
(Measured using a
low capacitance FET
probe. Standard
oscilloscope probes
can pull oscillator off
frequency. See
Figure 14.)
29
No modulation
(Data In low).
8-344
MOTOROLA ANALOG IC DEVICE DATA
MC13173
Table 3. PIN FUNCTION DESCRIPTION (continued) (TA =25°e, Vee =5.0 Vdc, fREF =32.768 kHz, fMOD
Pin
Symbol
Description
30
Tx PLL
Phase detector output
for the FSK Modulator.
Internal Equivalent
Circuit
=32.768 kHz)
Waveform
(With loop closed and
locked.)
No modulation
(Data In low).
Vee
30
With 32.768 kHz
square wave
modulation.
Note: Probing the
output of the phase
detectors directly may
disturb the loop. It is
best to probe the
output of the op amp
when evaluating loop
response.
31
MaPLL
Output of the phase
detector charge pump
for the Master PLL.
VEE
Vee
(With loop closed and
locked.)
31
3232kHz
Ref
Input to 32.768 kHz
reference. Filtered
from TTL oscillator
using application
circuit in Figure 15.
Approximately
1.0 Vp-p triangle
wave at 32.768 kHz.
MOTOROLA ANALOG IC DEVICE DATA
8-345
MC13173
Typical Performance Over Temperature
(Measured using test circuit in Figure 1) ,
Figure 5. Normalized IF Amp Gain
versus Temperature
Figure 4. Normalized Mixer Gain
versus Temperature
1.0
1.0
"
z
<.
(!)
z
<
(!)
0.5
cr
w
~
::;
c
w
~
~
:i
a::
2
-0.5
.
~1.0
. /"
1
II
!!:
--......
cW
a:: -0.5
2
50
-1.0
<6
=>
D..
5.5
-50
o
130
a::
a:: 120
=>
u
/
z
t5
/
,~
110
::;
=>
::;
80
..:
::;
70
.9
60
x
o
50
-5.01~-~_:_r__:=~.....;;;;;;;;t:::=======1
Ti'ansmit Communications Mode
~
w
(!)
~ 1.25
~
~
:t
-6.0t-----~1o::::------+------;
ffl
a::
.B-6.5t------I------'''''''''...r-------i
-7.0L-_ _ _ _-I.._ _ _ _ _.L....._ _ _ _...J
-50
100
50
TA. AMBIENT TEMPERATURE (0C)
100
50
1.5
-5.51------"--.....-.1r--'----4------l
~
'" -----
Figure 9. Data Slicer and Carrier Detect
Threshold Voltages versus Temperature
~
8-346
100
TA. AMBIENT TEMPERATURE (0C)
-4.5 .., - - - - - - ; - - - - - - - r - - - - - - - ,
a
~
o
-50
100
Figure II. Supply Current
versus Temperature
15
........
c 100
...!,
....
=>
90
D..
TA. AMBIENTTEMPERATURE (0C)
I
50
140
!z
w
/
-
/
Figure 7. Maximum Pull-Down Current
versus Temperature (Pin 25)
...!,
....
=>
.9
/
Figure 6. Maximum Pull-Up Current
versus Temperature (Pin 25)
6.5
~
./
-50
100
' 7.0
6.0
0
N
::::;
..:
::;
./"'" ~
TA. AMBIENT TEMPERATURE (0C)
D..
::;
=>
::;
..:
TA. AMBIENT TEMPERATURE (0C)
!z
w
a::
a::
=>
u
-o
, -50
0.5
D..
::;
~
f!'
1.0
--
Carrier Detect
~ t-------
j.
0.75
-50
o
50
100
TA. AMBIENT TEMPERATURE (0C)
MOTOROLA ANALOG IC DEVICE DATA
MC13173
APPLICATIONS INFORMATION
The MC13173 transceiver is specially designed to operate
from a 32.768 kHz reference which is readily available in
most computer applications. The frequency synthesizer on
chip generates a receiver local oscillator frequency and the
transmit mark and space frequencies from this fixed
reference frequency, eliminating the need for additional
crystals or manual tuning.
Large divide ratios are needed to generate these
frequencies, however. For example, the receiver La
frequency is 368.5 times the 32.768 kHz reference
frequency. This requires that the reference frequency be both
accurate and stable. A two percent error in the reference
frequency would pull the La off frequency by over 240 kHz,
putting the IF frequency out of the usable bandwidth of the
filters and discriminator. For this reason, a 32.768 kHz
oscillator circuit has been included on the demonstration
board design. Although TTL crystal oscillators are available,
this oscillator circuit uses an inexpensive tuning fork crystal
and a hex inverter to generate a square wave reference
frequency, which is then filtered and level adjusted to a
1.0 Vp-p triangle wave to drive pin 32. A TTL Clock Oscillator
could also be used with the filter circuit as shown.
Frequency Synthesizer
The recommended op amp for the extemalloop filter is the
MC33202. For low voltage operation, (VCC ~ 3.3 V) an op
amp that is rail-ta-rail on both the input and output is
advisable to obtain the widest possible output voltage range
without distortion. Sufficient distortion from the op amp such
as phase reversal on the output caused by overdriving the
inputs could prevent the loop from locking to the reference.
In debugging the loop filter, it is important to note that the
FSK Modulator phase locked loop will not lock until the
Master VCO is locked to the reference. If the application
circuit in Figure 15 is used, both loops should lock without the
need for any additional tweaking. Since the VCO has
±2.0 MHz of range using the MV209 varactor diode (see
Figure 11), neither preciSion components nor tuning should
be required. To ensure both loops are operating properly, first
evaluate each VCO with the loop open and a voltage equal to
VCct2 applied to the resistor in series with the varactor. Since
there is a relatively small capacitance «40 pF) in series with
the LC tank circuit, the VCO pin is sensitive to any parasitic
capacitance. Thus when using a standard oscilloscope probe
having 10 to 20 pF capacitance it is difficult to measure the
VCO frequency without shifting its frequency. A low
capacitance FET probe used with a frequency counter will
enable you to accurately measure the VCO frequency
without altering it in the process.
The free running frequency of the VCO should be
approximately on frequency when the loop is open and the
varactor is biased at mid-supply. The VCO for the Master
PLL should run at 12.05 MHz. The free running frequency of
the FSK Modulator should be at 13.72 MHz, midway between
the two VCO frequencies needed to generate the transmit
mark and space frequencies. The FSK Modulator loop is only
active when the transmitter is enabled and the device is in the
communications mode (see Tables 1 & 2). If either the "T"
pin is low or the "E" pin is high, the VCO will be off and
you will see no oscillation on Pin 29.
Once the loops are closed, the veo frequencies should
track the reference frequency within the hold-in range of the
MOTOROLA ANALOG IC DEVICE DATA
loop. Although the FSK Modulator loop is dependent on the
Master veo, the Master VCO is completely independent of
the FSK Modulator. In fact, the FSK Modulator can be
powered down (see Table 2) without affecting the Master
veo operation. In the application circuit in Figure 15 a single
reference voltage for both op amps in the loop filters is
provided by two diodes to VCC. If the Master veo is affected
by the FSK Modulator loop, this generally indicates a problem
with the common reference voltage to the op amp, and may
mean the diodes are in backwards.
Once the loops are closed you should see a phase
detector output such as is shown in the Pin Function
Description in Table 3. If the veo was on frequency when the
loop was open, the phase detector outputs should swing
around mid supply and not hit against either the positive or
negative rail. Latching to Vee or VEE may indicate the loop
filter circuitry is not implemented correctly.
Due to the digital design of the phase detectors, the
transmitter can only transition between mark and space
frequencies on a clock edge. On the receive side this may be
seen as a double image on the detector output, with a
discrete time delay which does not vary with the frequency of
the data input (see Figure 10). This is a normal consequence
of using a digital phase detector and should not be confused
with jitter from the data slicer.
Figure 10. Receive Data Output
(Data Transmitted from Companion MC13173)
II
Transmitter
The light emitting diode (LED) driver in the transmitter is
capable of 6.0 to 10 mA of pull-up current. Selection of the
extemal transistor and biaSing resistor will depend on the
LEOs used. Typical infrared LEOs require 50 to 100 mA of
current and have a forward voltage of 1.5V. Sufficient current
is needed to obtain the maximum power output without
distorting the output by overdriving the LEO. Key
specifications include rise and fall time, wavelength, beam
width (generally given in half-angle), maximum power output
and efficiency. Choice of wavelengths is generally
determined by cost and power efficiency, which may vary
between vendors. The LEOs used in this application are at
880 nm and were chosen for best efficiency. However LEOs
in general are very inefficient, converting only 1 or 2 percent
of the electrical power into optical power. Multiple LEOs can
be used to increase transceiver range.
8--347
MC13173
Disabling the transmitter via the data bus turns off the
output of the LED driver, removing the base current from the
external transistor and thereby turning off the IR LED.
Because of the high current drawn by the LED, this offers
considerable power savings when the transmitter is not in
use and can be easily controlled by a microcontroller with no
additional circuitry.
In the "AN" transmit mode, the data output is on/off keyed,
with the LED on for a data high, and off for a data low. It is a
baseband signal, with no carrier present (see Figure 11).
harmonics. In the application circuit in Figure 15, Toko filters
with a bandwidth of 330 kHz or 360 kHz are recommended to
accommodate higher data rates. If the IF filters are too
narrow, the recovered signal may have noise on the peaks
(see Figure 12).
Figure 12. Receive Data Output
Figure 11. LED Driver Output in AN Mode
II
Receiver
The receiver portion of the MC13173 is similar to the
design of Motorola's MC13156 Wideband FM Receiver.
Instead of using the mixer to downconvert from a higher RF
frequency, this application is designed to upconvert the
1.372 MHl input to a 10.7 MHz IF. The wide deviation,
relative to the RF input frequency, requires a low Q tuned
circuit to recover this bandwidth:
Q =
fc
~,
where fc = 1.372 MHz
.3dB
By Carson's Rule, the BW " 2(fdev + fmod). Since for
mark/space frequencies of 1.317 MHz and 1.427 MHz the
deviation is fixed at ±50 kHz, the bandwidth for· a 50 kHz
square wave (100 i
"-
15
a:
10
!3
0
gj
:I:
/
20
:::>
0
f-
~ r--....
14
~
/
>'
0
zw
13
:::>
0
w
12
0
11
a:
u..
V
/
....
15
N'
-r-.....
~
~
............
MasterPLL'
0
FSK Modulator
.............
-120
-100
-80
-60
-40
-20
9.0
-0.5
20
'"
"- ......
>
10
5.0
-140
r.....
0
0.5
RF INPUT LEVEL (dBm)
1.0
1.5
2.0
2.5
3.00
3.5
VARACTOR VOLTAGE (V)
Figure 15. Application Circuit
rr:---[}e
r------nl
XI
220k
220k
~
~
.1rL---~
24k
24k
II
~C74HCU04
L-+-____~o~----,L-----~
MV209
r l - - _.........
J
Vee
36k
33n
Vee
2.2n
NOTES:
1) F1 & F2 -10.7 MHzceramicfi~er, Toko 107MA-AE-10
(360kHz), Taka 107MOAE-10 (330kHz) or equivalent.
2) Tunable shielded inductors:
561'H Toko A119AN8-T1042Z
1.0 I'H Toko292KN8-T1372Z
82 I'H Taka A 119AN8-T1044Z
1.5 I'H Taka 292KN8-T1373Z
3) Crystal- 32.768 kHz C - Type tuning fork crystal. Digikey
part number SE3201 or equivalent.
4) LEOs and Detectors SFH484-2, SFH485-2 and SFH206K
are made by Siemens.
5) Optimum bias resistor depends on the LEOs used.
6) May be fixed or tunable.
MOTOROLA ANALOG IC DEVICE DATA
I
=F2
1.0nT 1 LOn
1.0n1
L---4->--l'---+---<->-.J
Vee
8-349
MC13173
Figure 16. Component Placement
O
o
TX
Data
In
Ref
Ose
Rx
Data
Out
o
Carrier
Detect
o
8-350
RSSI
VEE
VCC
000
MOTOROLA ANALOG IC DEVICE DATA
MC13173
Figure 17. Solder Side View
Carrier
VCC
o
ASSI
VEE
00
Detect
II
Figure 18. Component Side View
MOTOROLA ANALOG IC DEVICE DATA
8-351
MC13173
Figure 19. Detailed Internal Block Diagram
32K
32
12M
1
0
27
E
26
---L
<:)
,~
2
~
'--
MaPLL31
)-
t9 r
."
e
~
r
n
"'"'
..... ~
-
r-
.....
,e
CD
"
r-
~J-
2VEE1
r--;
~75b
4RFin1
5 RFin2
-
.....
~
3R
6MIXout
~
r-
7VCC1
81Fin
-
91Fdec1
,m
CD
"
10lFdec2
I-
."
t9 ITxPLL30
.....
'--
II
.....
'-'-'7
:;;
e
<:
t" l~
w
n
,l-l
.....
e
~ r-
<>
111Fout
12 VCC2
u
13L1Min
14 LlMdec1
0
-~ r-
15 LlMdec2
-
,
r-
.....
."
,"e
C
0::
r-
~ I-
LED Feedback 24
LED Driver 25
T28
14M 29
!l
16 RSSI
17
.~\
.~
en
17 Carrier Detect
18 Quad Coil
19 Demoo
20 DSin
21 VEE2
22DATAout
23VEE3
8-352
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13175
MC13176
UHF FM/AM Transmitter
The MC13175 and MC13176 are one chip FM/AM transmitter
subsystems designed for AM/FM communication systems. They include a
Colpitts crystal reference oscillator, UHF oscillator, + 8 (MC13175) or + 32
(MC13176) prescaler and phase detector forming a versatile PLL system.
Targeted applications are in the 260 to 470 MHz band and 902 to 928 MHz
band covered by FCC Title 47; Part 15. Other applications include local
oscillator sources in UHF and 900 MHz receivers, UHF and 900 MHz video
transmitters, RF Local Area Networks (LANs), and high frequency clock
drivers. The MC13175176 offer the following features:
UHFFM/AM
TRANSMITTER
SEMICONDUCTOR
TECHNICAL DATA
• UHF Current Controlled Oscillator
• Uses Easily Available 3rd Overtone or Fundamental Crystals for
Reference
• Fewer External Parts Required
• Low Operating Supply Voltage (1.8 to 5.0 Vdc)
• Low Supply Drain Currents
• Power Output Adjustable (Up to +10 dBm)
• Differential Output for Loop Antenna or Balun Transformer Networks
• Power Down Feature
• ASK Modulated by Switching Output On and Off
• (MC13175) fo
o
SUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
=8 x fref; (MC13176) fo =32 x fref
Figure 1. Typical Application as 320 MHz AM Transmitter
AM Moclulator
PIN CONNECTIONS
l~k
Coilcraft
l5O-05J08
Osc1
NC
NC
Osc4
VEE
ICont
PDout
Xtale
.17 1oop
I
Vcc
(MC13l76)
30p
:::c
(MC13l75)
=
~t
MC13l75-30p
MC13l76-lOOp
MC13175
CIys1aI
3rdOvertone
40.0000 MHz
0.B2~
1.0k =
:I:
O';;;--I
(3)
MC13l76
Cryslal
I
...L
Functamental_
10MHz·
vcc
NOTES: 1. 50 n coaxial balun, 111 0 wavelength at 320 MHz equals 1.5 inches.
2. Pins 5,10 & 15 are ground and connected to VEE which is the component/DC ground plane
side of PCB. These pins must be decoupJed to Vee; decoupling capacitors should be placed
as close as possible to the pins.
3. The crystal oscillator circuit may be adjusted for frequency with the variable inductor
(MC13175); recommended source is Coilcraft "slot seven- 7mm tuneable inductor, Part
#7M3-821. 1.Ok resistor. Shunting the crystal prevents it from OSCillating in the fundamental
ORDERING INFORMATION
Device
MC13175D
MC13176D
Operating
Temperature Range
TA = - 40° to +85°C
Package
S0-16
S0-16
mode.
MOTOROLA ANALOG IC DEVICE DATA
8-353
MC13175 MC13176
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Symbol
Value
Un"
Power Supply Voltage
VCC
7.0 (max)
Vdc
Operating Supply Voltage Range
VCC
1.8 to 5.0
Vdc
Junction Temperature
TJ
+150
°c
Operating Ambient Temperature
TA
-40to+85
°c
Tstg
-65to+150
°c
Storage Temperature
ELECTRICAL CHARACTERISTICS (Figure 2; VEE = - 3.0 Vdc, TA = 25°C, unless otherwise noted.)'
Characteristic
Pin
Supply Current (Power down: 111 & 116 = 0)
Supply Current (Enable [Pin 11) to VCC thru 30 k, 116 = 0)
Total Supply Current (Transmit Mode)
(Imod = 2.0 mA; 10 = 320 MHz)
Symbol
Min
'iYP
Max
Unit
IEEl
-0.5
-
IEE2
-18
'7'14
mA
IEE3
-39
-34
-
-
Differential Output Power (10 = 320 MHz; Vrel [Pin 9)
= 500 mVp-p; 10 = N x Irell
Imod 2.0 mA (see Figure 7, 8)
Imod=OmA
13& 14
Hold-in Range (± "'Irel x N)
MC13175 (see Figure 7)
MC13176 (see Figure 8)
13& 14
Oscillator Enable TIme (see Figure 22b)
7
2.0
-
+4.7
-45
-
3.5
4.0
6.5
8.0
-
20
22
25
27
-
-
4.0
-
ms
25
-
MHz
-50
-50
-
dBc
-
MHz
±!ifH
lerror
11 &8
!enable
16
BWAM
Spurious Outputs (Imod = 2.0 mAl
Spurious Outputs (Imod = 0 mAl
13& 14
13& 14
Pson
Psoll
Maximum Divider Input Frequency
Maximum Output Frequency
-
Idiv
13 & 14
10
AmplHude Modulation Bandwidth (see Figure 24)
mA
dBm
Pout
=
Phase Detector Output Error Current
MC13175
MC13176
IlA
-
-
950
950
MHz
I1A
-
-
• For testing purposes, Vee is ground (see Figure 2).
Figure 2. 320 MHz Test Circuit
RFoUI1
VEE
(1)
RFouI2
1---"-'--k->IIr<:J lreg. enable
MC13175-30p
MC13176-33p
Mg~~5
0.0111----1-
~I+
0.8211
(3)
1.0k =
MC13176 I
Cryslal
V=
Fundamental CC
10 MHz .
3rdOvertone
NOTES: 1. Vee is ground; while VEE is negative with respect to ground.
40 MHz
2. Pins 5, 10 and 15 are brought to the circuit side of the PCB via plated through holes.
They are connected together with a trace on the PCB and each Pin is decoupled to Vee (ground).
3. Recommended source Is Collcral! 'slot seven" Inductor, part number 7M3-821.
MOTOROLA ANALOG IC DEVICE DATA
MC13175 MC13176
PIN FUNCTION DESCRIPTIONS
Pin
Symbol
1&4
Osc 1,
Osc4
Internal Equivalent
Circuit
Vee
-r-
J"' l
10k
1
Ose 1
10k
4
III
A
A
~
VEE
Osc4
~
n
5
Description/External
Circuit Requirements
~
VEE
5
,J- ~
CCOlnputs
The oscillator is a current controlled type. An external oscillator
coil is connected to Pins 1 and 4 which forms a parallel
resonance LC tank circuit with the internal capac~ance of the
IC and with parasitic capacitance of the PC board. Three
base-ilmitter capacitances in series configuration form the
capacitance for the parallel tank. These are the base-emitters
at Pins 1 and 4 and the base-emitter of the differential amplifier.
The equivalent series capacitance in the differential amplifier is
varied by the modulating current from the frequency control
circuit (see Pin 6, internal circuit). A more thorough discussion
is found in the Applications Information section.
Supply Ground (VEE)
In the PCB layout, the ground pins (also applies to Pins 10 and
15) should be connected directly to chassis ground. Decoupling
capacitors to VCC should be placed directly at
the ground retums.
VEE ~
6
ICont
Frequency Control
For VCC = 3.0 Vdc, the voltage at Pin 6 is approximately 1.55
Vdc. The oscillator is current controlled by the error current from
the phase detector. This current is amplified to drive the current
source in the oscillator section which controls the frequency of
the oscillator. Figures 9 and 10 show the b.fosc versus ICont,
Figure 5 shows the Mosc versus ICont at - 40°C, + 25°C and
+ 85°C for 320 MHz. The CCO may be FM modulated as shown
in Figure 17, MC13176 320 MHz FM Transmitter. A detailed
discussion is found in the Applications Information section.
Vee
I
~
Rag
6
-- R
leont
~
7
PDout
Vee
4.0k
r
ceo
4.0k
~~
~
t---
~
PDout
7
~
~
MOTOROLA ANALOG IC DEVICE DATA
Phase Detector Output
The phase detector provides ± 30 I!A to keep the
locked at
the desired carrier frequency. The output impedance of the
phase detector is approximately 53 kn. Under closed loop
conditions there is a DC voltage which is dependent upon the
free running oscillator and the reference oscillator frequencies.
The circuitry between Pins 7 and 6 should be selected for
adequate loop filtering necessary to stabilize and filter the loop
response. Low pass filtering between Pin 7 and 6 is needed so
that the corner frequency is well below the sum of the divider
and the reference oscillator frequencies, but high enough to
allow for fast response to keep the loop locked. Refer to the
Applications Information section regarding loop filtering and FM
modulation.
~
8-355
MC13175 MC13176
PIN FUNCTION DESCRIPTIONS
Pin
Symbol
8
Xtale
9
Xtalb
10
Reg. Gnd
11
Enable
Internal Equivalent
Circuit
Description/External
Circuit Requirements
Vee
Crystsl Oscillator Inputs
The internal reference oscillator is configured as a common
emitter Colpitts. It may be operated with either a fundamental
or overtone crystal depending on the carrier frequency and the
internal prescaler. Crystal oscillator circuits and specifications
of crystals are discussed in detail in the applications section.
With VCC = 3.0 Vdc, the voltage at Pin 8 is approximately 1.8
Vdc and at Pin 9 is approximately 2.3 Vdc. 500 to 1000 mVp-p
should be present at Pin 9. The Colpitts is biased at 200 /-lA;
additional drive may be acquired by increasing the bias to
approximately 500 /-lA. Use 6.2 k from Pin 8 to ground.
Vee
Regulator Ground
An additional ground pin is provided to enhance the stability of
the system. Decoupling to the VCC (RF ground) Is essential; it
should be done at the ground return for Pin 10.
Reg
Device Enable
The potential at Pin 11 is approximately 1.25 Vdc. When Pin 11
is open, the transmitter is disabled in a power down mode and
draws less than 1.0 /-lA ICC if the MOD at Pin 16 is also open
(i.e., it has no current driving it). To enable the transmitter a
current source of 10 /-lA to 90 !-1A is provided. Figures 3 and 4
show the relationship between ICC, VCC and Ireg . enable. Note
that ICC is flat at approximately lOrnA for Ireg . enable 5.0 to
100 /-lA (lmod = 0).
=
II
12
VCC
Supply Voltage (VCC)
The operating supply voltage range is from 1.8 Vdc to 5.0 Vdc.
In the PCB layout, the VCC trace must be kept as wide as
possible to minimize inductive reactances along the trace; it is
best to have it completely fill around the surface mount
components and traces on the circuit side of the PCB.
Vee
r
12
Vee
13& 14
Out 1 and
Out 2
Vee
Differential Output
The output is configured differentially to easily drive a loop
antenna. By using a transformer or balun, as shown in the
application schematic, the device may then drive an unbalanced
low impedance load. Figure 6 shows how much the Output
Power and Free-Running Oscillator Frequency change with
temperature at 3.0 Vdc; Imod = 2.0 rnA.
15
OuCGnd
Output Ground
This additional ground pin provides direct access for the output
ground to the circuit board VEE.
16
Imod
AM Modulation/Power Output Level
The DC voltage at this pin is 0.8 Vdc with the current source
active. An external resistor is chosen to provide a source
current of 1.0 to 3.0 rnA, depending on the desired output power
level at a given VCC. Figure 23 shows the relationship of Power
Output to Modulation Current, Imod. At VCC =3.0 Vdc, 3.5 dBm
power output can be acquired with about 35 rnA ICC.
For FM modulation, Pin 16 is used to set the desired output
power level as described above.
For AM modulation, the modulation signal must ride on a
positive DC bias offset which sets a static (modulation off)
modulation current. External circuitry for various schemes is
further discussed in the Applications Information section.
8-356
MOTOROLA ANALOG IC DEVICE DATA
MC13175 MC13176
Figure 3. Supply Current
versus Supply Voltage
,...
10
l
8.0
I-
z
w
-
a:
a:
=> 6.0
u
Figure 4. Supply Current versus
Regulator Enable Current
-
100
C>
::;
10
::;
a.
a. 4.0
=>
en
a.
a.
=>
en
c:,
u
.5? 2.0
.5?
J
./
o
o
1.0
2.0
3.0
Vcc. SUPPLY VOLTAGE (Vdc)
4.0
5.0
Figure 5. Change Oscillator Frequency
versus Oscillator Control Current
~
~
~
W
§
I
1.0
0.1
1.0
10
100
Ireg . enable. REGULATOR ENABLE CURRENT (1lA)
~
4.0
~
3.0
til
2.0
~
=>
~
fE
1.0
u..
a:
g~ - 5.0 I-----t-----+-''''=--+__---'''o.t:-----''''''I---'''---'-j
-40°C
a:
o
~
::J
(3
o
~ -2.0
25°C
6-10r-----t-----+-----+---~~----+---~
~
_15~
-40
~
;:- 41.0
~
:::;;
~ 40.8
@
fE
40.6
a:
o
:s 40.4
____~____~____~____~____~8~5~oC~
-20
0
20
40
60
ICont. OSCILLATOR CONTROL CURRENT (~A)
\\
'\
"...
...J
~ 40.2
o
w
~ 40.0
~
-....;::
W
a:
~
Imod=2.0 mA
ICC=36mA
Po = 5.4 dBm
39.8
~
-i;39.6
-30
_~
-20
Po
"""'
... ~
,/
"
-50
-.....-
5.0
"-
4.0
VCC= 3.0Vdc
Imod=2.0mA
f = 320 MHz (ICont = 0; TA = 25°C)
Free-Running Oscillator
50
TA. AMBIENT TEMPERATURE eC)
E
~
a:
4.5 ~
~
.,.,~'
./
~ -4.0
!3
5
o
3.5
"-
,p
3.0
100
Figure 8. MC13176 Reference Oscillator
Frequency versus Phase Detector Current
¥
Closed Loop Response:
VCC = 3.0 Vdc
fo = 8.0 x fref
Vr j = 500 mVp-p
\\
.96 -3.0
80
Figure 7. MC13175 Reference Oscillator
Frequency versus Phase Detector Current
5.5
LlfOSC
-1.0
(3
.9
1000
Figure 6. Change in Oscillator Frequency and
Output Power versus Ambient Temperature
10.-----,-----,-----,-----.-----.-----,
VCC = 3.0 Vdc
Imod =2.0 mA
5.01---""+-"'"-""--+__--- f = 320 MHz (ICont = 0; TA = 25°C)
Free-Running Oscillator
en
V
~ 10.3 ,-----.-----,-----,----------------..,
~
Closed Loop Response:
VCC = 3.0 Vdc
6 10.2 I--r~-t------t-----+__--- fo = 32 x fref
~
Vref = 500 mVp-p
w
ga: 10.1 I-----'k-..,."".--t-----+__-----t-----+-----I
~
Imod= 1.0 mA
ICC=25mA -
~ ~o=-0.2dBm
~
-10
0
10
20
17. PHASE DETECTOR CURRENT (~A)
MOTOROLA ANALOG IC DEVICE DATA
(3
~
~ 99 r-----j----+
~
UJ
~
30
10 I------t---~~--~~----+-
UJ
u
Y
=--"""'__
Imod = 2.0 mA """'.....
---1
ICC = 35.5 mA
Po
=
4.7
dBm
98~____~__~____~____~_____ L_ _ _ _~
·-30
-20
-10
0
10
20
17. PHASE DETECTOR CURRENT (1lA)
30
8--357
II
MC13175 MC13176
~
£>-
20
10
ffi
~
0
II:
-10
~
-20
g
§
6-30
~
-
\
Vcc= 3.0 Vdc
Imod =2.0 mA
I--TA=25DC
lose (ICont @ 0) 320 MHz
"- ~~
o
ffi
@
IE
gII:
~
~
--r--r--
-10
,
\
Vcc = 3.0 Vdc
Imod=2.0mA
TA =25 DC
lose (IConI @ 0) 450 MHz
~
'I'....
-20
6-30
r-- r--
~
--71
_\- k::
1.1
1
~ 0.9
VI//.o K ~ IF~
1// ~.5Y£/ I
[I v~o\
/V
II
~:::
o
\
~
/,--+--+-+--+==-+-+-+-+-+-+--1
0.4 1---IW1,/.It+--+--+--f--+--+-+--t-I--+--+--I
0.3 I--.+,/++--+-I--+--+--j---jf--+--I---l---j--l
0.1
H(s) = KvF(s)/s + KvF(s)
From control theory, if the loop filter characteristic has F(O)
1, the DC gain of the closed loop, Kv is defined as,
J
If
Kv = KpKoKn
and the transfer function has a natural frequency,
ron = (Kv/tl + t2)1/2
a = (ron/2) (t2 + 1/Kv)
Rewriting the above equations and solving for the MC13176
with = 0.707 and ron = 5.0 k rad/sec:
a
Kv = KpKoKn = (30) (0.91 x 106) (1/32) = 0.853 x 106
tl + t2 = Kv/ron2 = 0.853 x 106/(25 X 106) = 34.1 ms
t2 = 2a/ron = (2) (0.707)/(5 X 103) = 0.283 ms
tl (Kv/ron2) - t2= (34.1 - 0.283) = 33.8 ms
=
OL-~~~~~-L~_L-~~_L-~-L~
o 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
COnt
MOTOROLA ANALOG IC DEVICE DATA
=
and a damping factor,
:00.6
0.51--~H,
0.2
The closed loop transfer function takes the form of a 2nd
order low pass filter given by,
10
11
12 13
8-359
II
MC13175 MC13176
For C =0.47 f.1;
then, R1 =t1/C =33.8 x 10-3/0.47 X 10-6 =72 k
dthus, R2 =t2/C =0.283 x 10-3/0.47 X 10-6 =0.60 k
In the above example, the following standard value
components are used,
C =0.47 f.1; R2
=620 and R'1 =72 k -
measurement of the hold-in range (Le. t.fref x N =MfH X
21t). Since sin 8e cannot exceed ±1.0, as 8e approaches ±:rtI2
the hold-in range is equal to the DC loop gain, Kv x N.
MOOH
53 k - 18 k
(R'1 is defined as R1 - 53 k, the output impedance of the
phase detector.)
Since the output of the phase detector is high impedance
(-50 k) and serves as a current source, and the input to the
frequency control, Pin 6 is low impedance (impedance of the
two diode to ground is approximately 500 0), it is imperative
that the second order low pass filter design above be
modified. In order to minimize loading of the R2C shunt
network, a higher impedance must be established to Pin 6. A
simple solution is achieved by adding a low pass network
between the passive second order network and the input to
Pin 6. This helps to minimize the loading effects on the
second order low pass while further suppressing the
sideband spurs of the crystal oscillator. A low pass filter with
R3 = 1.0 k and C2 = 1500 P has a corner frequency (fel of
106 kHz; the reference sideband spurs are down greater
than - 60 dBc.
MooH =± 27.3 Mrad/sec
MfH =± 4.35 MHz
Extended Hold-in Range
The hold-in range of about 3.4% could cause problems
over temperature in cases where the free-running oscillator
drifts more than 2 to 3% because of relatively high
temperature coefficients of the ferrite tuned CCO inductor.
This problem might worsen for lower frequency applications
where the external tuning coil is large compared to internal
capacitance at Pins 1 and 4. To improve hold-in range
performance, it is apparent that the gain factors involved
must be carefully considered.
Kn
18k
I
1.0k
~-6-2-oI-R-2~%
0.47~
C
C3
= is either 1/8 in the MC13175 or 1/32 in the
MC13176.
Kp = is fixed internally and cannot be altered.
Ko = Figures 9 and 10 suggest that there is capability
of greater control range with more current swing.
However, this swing must be symmetrical about
the center of the dynamic response. The
suggested zero current operating point for
±100 f.1A swing of the CCO is at about + 70 f.1A
offset point.
Ka = External loop amplification will be necessary
since the phase detector only supplies ± 30 1iA.
Figure 14. Modified Low Pass Loop Filter
Pin 7
=± Kv X N
where, Kv =KpKoKn.
In the above example,
Pin 6
0
1500P
T
_
'---'--l-vc-c-'
In the design example in Figure 15, an external resistor
(R5) of 15 k to VCC (3.0 Vdc) provides approximately 100 f.1A
of current boost to supplement the existing 50 f.1A internal
source current. R4 (1.0 k) is selected for approximately
0.1 Vdcacross it with 100 f.1A. R1, R2 and R3 are selected to
set the potential at Pin 7 and the base of 2N4402 at
approximately 0.9 Vdc and the emitter at 1.55 Vdc when error
current to Pin 6 is approximately zero f.1A. C1 is chosen to
reduce the level of the crystal sidebands.
Hold-In Range
The hold-in range, also called the lock range, tracking
range and synchronization range, is the ability of the CCO
frequency, fo to track the input reference signal, fref • N as it
gradually shifted away from the free running frequency, ff.
Assuming that the CCO is capable of sufficient frequency
deviation and that the intemalloop amplifier and filter are not
overdriven, the CCO will track until the phase error, 8e
approaches ±:rtI2 radians. Figures 5 through 8 are a direct
Figure 15. External Loop Amplifier
VCC=3.0Vdc
30J,JA
Phase
Detector
17
I
30J,JA
I
I
______ .JI
Oscillator
Control
Circuitry
1.Ok
2N4402
Output
8-360
I
I
-=-
L _____ _
MOTOROLA ANALOGIC DEVICE DATA
MC13175 MC13176
Figure 16 shows the improved hold-in range of the loop.
The ,.,fref is moved 950 kHz with over 200 IlA swing of control
current for an improved hold-in range of ±15.2 MHz or
± 95.46 Mrad/sec.
Figure 16. MC13176 Reference Oscillator
Frequency versus Oscillator Control Current
"N
:r:
~10.6
(.)
ifi
@10A
a:
~10.2
g
~
10
§w 9.8
I\.
1\
Closed Loop Response:
fa = 32 x fref
VCC = 3.0 Vdc
ICC=38 rnA
Pout = 4.8 dB
Irnod =2.0 rnA
Vref = 500 rnVp-p
,
............
r-. ....
I'
(.)
1'",
z
w
ffi
9.6
~.;..9.4
_P2 -150
-100
-50
0
50
16, OSCILLATOR CONTROL CURRENT (!LA)
100
Lock-in Range/Capture Range
If a signal is applied to the loop not equal to free running
frequency, ff, then the loop will capture or lock-in the
signal by making fs = fo (i.e. if the initial frequency
difference is not too great). The lock-in range can be
expressed as "'coL - ± 2ilcon
FM Modulation
Noise external to the loop (phase detector input) is
minimized by narrowing the bandwidth. This noise is minimal
in a PLL system since the reference frequency is usually
derived from a crystal oscillator. FM can be achieved by
applying a modulation current superimposed on the control
current of the CCO. The loop bandwidth must be narrow
enough to prevent the loop from responding to the
modulation frequency components, thus, allowing the CCO
to deviate in frequency. The loop bandwidth is related to the
natural frequency con. In the lag-lead design example where
the natural frequency, con = 5.0 krad/sec and a damping
factor, il = 0.707, the loop bandwidth = 1.64 kHz.
Characterization data of the closed loop responses for both
the MC13175 and MC13176 at 320 MHz (Figures 7 and 8,
respectively) show satisfactory performance using only a
simple low-pass loop filter network. The loop filter response
is strongly influenced by the high output impedance of the
push-pull current output of the phase detector.
MOTOROLA ANALOG IC DEVICE DATA
fc = 0.159/RC;
For R = 1.0 k + R7 (R7 =53 k) and C =390 pF
fc = 7.55 kHz or roc =47 krad/sec
The application example in Figure 17a of a 320 MHz FM
transmitter demonstrates the FM capabilities of the IC. A high
value series resistor (100 k) to Pin 6 sets up the current
source to drive the modulation section of the chip. Its value is
dependent on the peak to peak level of the encoding data
and the maximum desired frequency deviation. The data
input is AC coupled with a large coupling capacitor which is
selected for the modulating frequency. The component
placements on the circuit side and ground side of the PC
board are shown in Figures 28 and 29, respectively.
Figure 18a illustrates the input data of a 10kHz modulating
signal at 1.6 Vp-p. Figures 18b and 18c depict the deviation
and resulting modulation spectrum showing the carrier null at
- 40 dBc. Figure 18d shows the unmodulated carrier power
output at 3.5 dBm for VCC =3.0 Vdc.
For voice applications using a dynamic or an electret
microphone, an op amp is used to amplify the microphone's
low level output. The microphone amplifier circuit is shown in
Figure 19. Figure 17b shows an application example for
NBFM audio or direct FSK in which the reference crystal
oscillator is modulated.
Figure 19. Microphone Amplifier
II
Voice>
Input
10k
Electret
Microphone
Data or
Audio
Output
Local Oscillator Application
To reduce internal loop noise, a relatively wide loop
bandwidth is needed so that the' loop tracks out or cancels
the noise. This is emphasized to reduce inherent CCO and
divider noise or noise produced by mechanical shock and
environmental vibrations. In a local oscillator application the
CCO and divider noise should be reduced by proper
selection of the natural frequency of the loop. Additional low
pass filtering of the output will likely be necessary to reduce
the crystal sideband spurs to a minimal level.
8-361
MC13175 MC13176
Figure 17a. 320 MHz MC13176D.FM Transmitter
RF Level Adjust
SMA
ty<
SlOp -=
R'"--------1
RF OUIput
to Antenna
/----vv'v----1 Vee
1301<
33k
Data tnput
(1.6Vp-p)
~51P
51p
Crystal
Fundamental
10MHz
NOTES: 1. 50 11 coaxial balun, 2 inches long.
2. Pins 5, 10 and 15 are grounds and connnected to VEE which is the component's side ground plane.
These pins must be decoupled to Vcc; decoupling capacitors should be placed as close as possible to the pins.
3. RFCl is 180 nH Coilcrat! surface mount inductor or 190 nH Coilcraft 146-05J08.
4. Recommended source is a Coilcrat! "slot seven" 7.0 mm tuneable inductor, part 117M3--682.
5. The crystal is a parallel. resonant, fundamental mode calibrated with 32 pF load capacitance.
Figure 17b. 320 MHz NBFM Transmitter
RF Level Adjust
SMA
~
rq.L-_ _ _...; 470p -=
f+---~_I
RFOutput
toAntema
VCC (3.6 Vdc- Litllium Battery)
i-----vv'v--I Vee
13011
I
33k
O.47~
Vee
Extemal
l.oopAmp
RFC2
l(~Il'~
- 110~
F;Z'"~6) l' 1
O.Q1~
~-------;~-------~~
lOOp "J;
180p
Vee
RFC3
10MHz
*
(5) MMBV432L
NOTES: 1. 50 11 coaxial balun, 2 inches long.
AudIo or
Datatnput
2. Pins 5,10 and 15 are grounds and connnected to VEE which is the component's side ground plane. These
pins must be decoupled to VCC; decoupling capacttors should be placed as close as possible to the pins.
3. RFCI is 180 nH Coilcrat! surface mount inductor.
4. RF~ and RFC3 are high impedance crystal frequency of 10 MHz; 8.21'H molded inductor gives XL > 100011..
5. A single varactor like the MV21 05 may be used whereby RFC2 is not needed.
6. The crystal is a parallel resonant, fundamental mode calibrated with 32 pF load capacitance.
8-362
MOTOROLA ANALOG IC DEVICE DATA
MC13175 MC13176
Figure 18a. Input Data Waveform
Figure 18b. Frequency Deviation
Figure 18c. Modulation Spectrum
Figure 18d. Unmodulated Carrier
II
Reference Crystal Oscillator (Pins 8 and 9)
Selection of Proper Crystal: A crystal can operate in a
number of mechanical modes. The lowest resonant
frequency mode is its fundamental while higher order modes
are called overtones. At each mechanical resonance, a
crystal behaves like a RLC series-tuned circuit having a
large inductor and a high Q. The inductor Ls is series
resonance with a dynamic capacitor, Cs determined by the
elasticity of the crystal lattice and a series resistance Rs ,
which accounts for the power dissipated in heating the
crystal. This series RLC circuit is in parallel with a static
capacitance, Cp which is created by the crystal block and by
the metal plates and leads that make contact with it.
Figure 20 is the equivalent circuit for a crystal in a single
resonant mode. It is assumed that other modes of resonance
are 50 far off frequency that their effects are negligible.
Series resonant frequency, 15 is given by;
fs
=1/21t(LsCs )1/2
and parallel resonant frequency, Ip is given by;
fp
=fs(1
+ CslCp)1/2
MOTOROLA ANALOG IC DEVICE DATA
Figure 20. Crystal Equivalent Circuit
the frequency separation at resonance is given by;
Ilf =fp-fs =fs[1 - (1 + CslCp)1/2]
Usually fp is less than 1% higher than fs, and a crystal exhibits
an extremely wide variation of the reactance with frequency
between fp and 15' A crystal oscillator circuit is very stable
with frequency. This high rate 01 change of impedance with
frequency stabilizes the oscillator, because any significant
change in oscillator Irequency will cause a large phase shift
in the feedback loop keeping the oscillator on frequency.
8-363
MC13175 MC13176'
Manufacturers specify crystal for either series or parallel
resonant operation. The frequency for the parallel mode is
calibrated with a specified shunt capacitance called a "load
capacitance." The most common value is 30 to 32 pF. If the
load qapacitance is placed in series with the crystal, the
equivalent circuit will be series resonance at the specified
parallel-resonant frequency. Frequencies up to 20 MHz use
parallel resonant crystal operating in the fundamental mode,
while above 20 MHz to about 60 MHz, a series resonant
crystal specified and calibrated for operation in the overtone
mode is used.
II
Application Examples
Two types of crystal oscillator circuits are used in the
applications circuits: 1) fundamental mode common emitter
Colpitts (Figures 1, 17a, 17b, and 21), and 2) third overtone
impedance inversion Colpitts (also Figures 1 and 21).
The fundamental mode common emitter Colpitts uses a
parallel resonant crystal calibrated with a 32 pf load
capaCitance. The capaCitance values are chosen to provide
excellent frequency stability and output power
of > 500 mVp-p at Pin 9. In Figures 1 and 21, the
fundamental mode reference oscillator is fixed tuned relying
on the repeatability of the crystal and passive network to
maintain the' frequency, while in the circuit shown in Figure
17, the oscillator frequency can be adjusted with the variable
inductor for the precise operating frequency.
The third overtone impedance inversion Colpitts uses a
series resonance crystal with a 25 ppm tolerance. In the
application examples (Figures 1 and 21), the reference
oscillator operates with the third overtone crystal at
40.0000 MHz. Thus, the MC13175 is operated at 320 MHz
(f0l8 = crystal; 320/8 = 40.0000 MHz. The resistor across the
crystal ensures that the crystal will operate in the series
resonant mode. A tuneable inductor is used to adjust the
oscillation frequency; it forms a parallel resonant circuit with
the series and parallel combination of the external capaCitors
forming the divider and feedback network and the
base-emitter capacitance of the device. If the crystal is
shorted, the reference oscillator should free-run at the
frequency dictated by the parallel resonant LC network.
The reference oscillator can be operated as high as
60 MHz with a third overtone crystal. Therefore, it is
possible to use the MC13175 up to at least 480 MHz and the
MC13176 up to 950 MHz (based on the maximum capability
of the divider network).
Enable (Pin 11)
The enabling resistor at Pin 11 is calculated by:
Reg. enable =VCC - 1.0 Vdcllreg. enable
8-364
From Figure 4, Ireg. enable is chosen to be 75 !-lA. So, for a
VCC =3.0 Vdc Rreg . enable = 26.6 1<0, a standard value
27 1<0 resistor is adequate.
Layout Considerations
Supply (Pin 12): Inthe PCB layout, the Vcctrace must be
kept as wide as possible to minimize inductive reactance
along the trace; it is best that VCC (RF ground) completely fills
around the surface, mounted components and interconnect
traces on the circuit side of the board. This technique is
demonstrated in the evaluation PC board.
Battery/Selection/Lithium Types
The device may be operated from a 3.0 V lithium battery.
Selection of a suitable battery is important. Because one of
the major problems for long life battery powered equipment is
oxidation of the battery terminals, a battery mounted in a
clip-in socket is not advised. The battery leads or contact
post should be isolated from the air to eliminate oxide
build-up. The battery should have PC board mounting tabs
which can be soldered to the PCB. Consideration should be
given for the peak current capability of the battery. Lithium
batteries have current handling capabilities based on the
composition of the lithium compound, construction and the
battery size. A 1300 mAlhr rating can be achieved in the
cylindrical cell battery. The Rayovac CR2/3A
lithium-manganese dioxide battery is a crimp sealed, spiral
wound 3.0 Vdc, 1300 mAlhr cylindrical cell with PC board
mounting tabs. It is an excellent choice based on capacity
and size (1.358" long by 0.665" in diameter).
Differential Output (Pins 13, 14)
The availability of micro-coaxial cable and small baluns in
surface mount and radial-leaded components allows for
simple interface to the output ports. A loop antenna may be
directly connected with bias via RFC or 50 g resistors.
Antenna configuration will vary depending on the space
available and the frequency of operation.
AM Modulation (Pin 16)
Amplitude Shift Key: The MC13175 and MC13176 are
designed to accommodate Amplitude Shift Keying (ASK).
ASK modulation is a form of digital modulation corresponding
to AM. The amplitude of the carrier is switched between two
or more values in response to the PCM code. For the binary
case, the usual choice is On-Off Keying (often abbreviated
OaK). The resultant amplitude modulated waveform
consists of RF pulses called marks, representing binary 1
and spaces representing binary O.
MOTOROLA ANALOG IC DEVICE DATA
MC13175 MC13176
Figure 21. ASK 320 MHz Application Circuit
Rmod
3.311
(4)
On-OII Keyed Input
TTL Levell 0 kHz
Coilcraft
l5Q-05J08
RFOut
(2) 0----+---1
VEE
I----'\Mr-~ (5)
100p
(MC13l76)
:I:
VCC
30p
::r:
(MC13l75) -=
MC13l75-30p
MC13l76-l80p
~t
0.8211
(3) MC13l76
I
C
MC13175
rysta
Crystal
1.0k
_
Fundamental
3rd Overtone
10 MHz
40.0000 MHz
--
_:r:
NOTES: 1. 50 n coaxial balun. 1/10 wavelength line (1.5") provides the best
match to a 50 n load.
2. Pins 5, 10 and 15 are ground and connnected to VEE which is
the componenVDC ground plane side of PCB. These pins must
be decoupled to VCC; decoupling capacitors should be placed
as close as possible to the pins.
3. The crystal oscillator circuit may be adjusted for frequency with
the variable inductor (MCI3175); 1.0 k resistor shunting the
crystal prevents it from oscillating in the fundamental mode.
Recommended source is Coilcraft "slot seven" 7.0 mm tuneable
inductor, part #7M3-821.
Figure 21 shows a typical application in which the output
power has been reduced for linearity and current drain. The
current draw on the device is 16 mA ICC (average) and
- 22.5 dBm (average power output) using a 10kHz
modulating rate for the on-off keying. This equates to 20 mA
and - 2.3 dBm "On", 13 mA and - 41 dBm "Off". In Figure
22a, the device's modulating waveform and encoded carrier
MOTOROLA ANALOG IC DEVICE DATA
o~~---l
.!.
-. VCC
I
...
4. The On-OIl keyed signal turns the output of the transmitter off and on with
TTL level pulses through Rmod at Pin 16. The "On" power and ICC is set
by the resistor which sels.lmod = VTTL - 0.8/ Rmod. (see Figure 23).
5. SI simulates an enable gate pulse from a microprocessor which will
enable the transmitter. (see Figure 4 to determine precise value of the
enabling resistor based on the potential of the gate pulse and the
desired enable.)
are displayed. The crystal oscillator enable time is needed to
set the acquisition timing. It takes typically 4.0 msec to reach
full magnitude of the oscillator waveform (see Figure 22b,
Oscillator Waveform, at Pin 8). A square waveform of 3.0 V
peak with a period that is greater than the oscillator enable
time is applied to the Enable (Pin 11).
8-365
II
MC13175 MC13176
Figure 22a. ASK Input Waveform and Modulated Carrier
Pin 16
00t< Input Modulation
10kHz TTL Waveform
OrKlff Keying Encoded
Carrier Envelope
Figure 22b. Oscillator Enable Time, Tenable
PinS
Oscillator Waveform
Figure 23. Power Output versus Modulation Current
10
. /!-
5.0
E
~
./
0
!3
5.0
13o
;
~ -10
...,..V'
f( -15
rP
-20
VCC = 3.0 Vdc
f=320MHz
,/
",.
-25
0.1
8-366
1.0
Imod, MODULATION CURRENT (rnA)
10
Analog AM
In analog AM applications, the output amplifier's linearity
must be carefully considered. Figure 23 is a plot of Power
Output versus Modulation Current at 320 MHz, 3.0 Vdc. In
order to achieve a linear encoding of the modulating
sinusoidal waveform on the carrier, the modulating signal
must amplitude modulate the carrier in the linear portion of its
power output response. When using a sinewave modulating
signal, the signal rides on a positive DC offset called Vmod
which sets a static (modulation off) modulation current, Imod.
Imod controls the power output of the IC. As the modulating
signal moves around this static bias point the modulating
current varies causing power output to vary or to be AM
modulated. When the IC is operated at modulation current
levels greater than 2.0 mAdc the differential output stage
starts to saturate.
MOTOROLA ANALOG IC DEVICE DATA
MC13175 MC13176
In the design example, shown in Figure 24, the operating
point is selected as a tradeoff between average power output
and quality of the AM.
ForVCC=3.0Vdc; ICC= 18.5 mAand Imod =0.5 mAdcand
a static DC offset of 1.04 Vdc, the circuit shown in Figure 24
completes the design. Figures 25a, 25b and 25c show the
results of - 6.9 dBm output power and 100% modulation by
the 10kHz and 1.0 MHz modulating sinewave signals. The
amplitude of the input signals is approximately 800 mVp--p.
Where Rmod = (VCC - 1.04 Vdc)/0.5 mA = 3.92 k, use a
standard value resistor of 3.9 k.
Figure 24. Analog AM Transmitter
1---3.9k
1.04Vdc 560
~
Vee 1---'>Atv--..---'lNv--116
3.0Vdc Rmod
0--------1
Data
Input
800mVp-p
0.8Vdc
+
6.8~
I
I
I
Figure 25a. Power Output of Unmodulated Carrier
11
Figure 25b. Input Signal and AM Modulated
Carrier for fmod = 10kHz
MOTOROLA ANALOG IC DEVICE DATA
Figure 25c. Input Signal and AM Modulated
Carrier for fmod = 1.0 MHz
8-367
MC13175 MC13176
Figure 26. Circuit Side View of MC1317XD
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••• a •• a •••••
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••••••••••••••••• a.a •••••• a •••••••••••
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a.......
••••• a.a.
........ .
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a •••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
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••••••••••••••••••••••••••••••••••••••
.a.......
4"
.......
Figure 27. Ground Side View
4"
~I.---4"---~·1
8-368
MOTOROLA ANALOG IC DEVICE DATA
MC13175 MC13176
Figure 28. Surface Mounted Components Placement
(on Circuit Side)
Figure 29. Radial Leaded Components Placement
(on Ground Side)
MOTOROLA ANALOG IC DEVICE DATA
II
Addendum
An Introduction to Motorola
RF Communications IC Applications
In Brief ...
Page
II
The RF devices described. in Chapter 8 are targeted
for the consumer communications market. In addition,
most of these parts are capable of superior perfottnance
in professional and industrial applicationS. These devices
represent the latest technology in cost effective RF and
audio subsystems for cordless telephones (CT-1), RF :
LANs, land mobile radio, scanners, cellular telephones,
remote control spread spectrum, and amateur radio. The
purpose of this addendum is to help the user explore all
the opportunities presented by this growing family of
wireless communications ICs from Motorola Analog.
8-370
Regulatory Issues ............................. 8-371
Industry Standards ............................ 8-371
Communications Systems ...................... 8-371
Passive Components ... : ...................... 8-371
Component Suppliers .. ,o ••••••••••••••••••••••• 8-372
Breadboarding ................................ 8-372
Test Equipment ............................... 8-372
Worldwide Cordless Telephone Frequencies ...... 8-373
MOTOROLA ANALOG IC DEVICE DATA
REGULATORY ISSUES
COMMUNICATIONS SYSTEMS
Each country has its own specific set of regulations
regarding radio frequency systems and equipment built and
sold within its jurisdiction. These regulations are strongly
applicable to transmitting devices. The rules are based on
both local needs and international treaties. The regulations
are established to provide maximum utilization of the limited
available radio spectrum. Motorola strongly recommends that
you, the user of these communication ICs, obtain the
applicable regulations and abide by them.
In the United States, the regulations of the Federal
Communications Commission (F.C.C.) are published in the
Code of Federal Regulations (CFR), Title 47, Parts 0 through
99. In the U.S. most of the consumer applications fall under
CFR 47, Part 15, covering nonlicensed intentional radiators,
or Part 68 which covers public network interconnections.
CFR 47 may be obtained at most libraries (in the reference
section), or from the U.S. Government Printing Office. You
may call their office at (213) 894-5841 , or (202) 274-2054 for
price and availability. In addition, private contractors such as
the Rules Service Company, (301) 424-9402 can provide
both the CFR data and an automatic update service. In the
U.S., further information is available from the FCC field
organization.
For the address and telephone number of the nearest
office, contact:
For the most part, the devices described in Chapter 8 use
frequency modulation (FM) for both analog voice and data.
FM is generally considered the simplest and most cost
efficient type of modulation today. FM offers excellent: noise
rejection; good sensitivity; reduction of interference due to the
FM capture effect; simple circuitry; and an array of test
equipment, most of which has spun-off the land mobile
market. Direct digital transmission may also be accomplished
using Frequency Shift Keying (FSK) or Amplitude Shih
Keying (ASK).
The devices shown in Chapter 8 are designed to operate at
frequencies below 1.0 GHz (1000 MHz). Today, that frequency
range offers the best compromise among performance,
complexity and cost. Over the next decade there will be an
increasing movement to 1.0 to 3.0 GHz, as the demand for
more complex personal communications systems comes
on-line. Motorola will add products to its portfolio as these
microwave applications become better defined.
Several reference books on Communications Theory and
Design are listed below. These books are generally available
at major public and university libraries.
FCC CONSUMER OFFICE AND
SMALL BUSINESS DIVISION
1919 M STREET WEST
WASHINGTON, D.C. 20554
(202) 632-7000
SOLID STATE RADIO ENGINEERING, Herbert l. Krauss,
Charles W. Bosdan, F.H. Raab, Wiley 1980.R
In other countries, the Ministry of Posts or
Telecommunications should be contacted. Motorola
Semiconductor does not warrant that the applications shown
in this data book meet all the conditions prescribed by
government regulations.
INDUSTRY STANDARDS
Throughout the world the telecommunications industry
has established working standards committees to ensure
equipment compatibility by setting minimum standards.
These standards also help make the best use of the available
radio spectrum. In the U.S., the Electronic Industries
Association (E.I.A.) has developed a series of these
recommended standards which have become the defacto
global guidelines.
The following EIA Standards apply to Frequency
Modulation (FM) systems.
EIAlTIA-204C
EIAlTIA-152B
EIAlTIA-316B
FM/PM RECEIVER STANDARDS
FM/PM TRANSMITTER STANDARDS
TEST CONDITIONS, PORTABLE
PERSONAL RADIO
For additional information and priCing, contact the E.I.A. at
the following address:
ELECTRONIC INDUSTRIES ASSOCIATION
ENGINEERING DEPARTMENT
2001 EYE STREET NW.
WASHINGTON, D.C. 20006
(202) 457-4900
MOTOROLA ANALOG IC DEVICE DATA
THE RADIO AMATEUR'S HANDBOOK, American Radio
Relay League, Newington, CT.
MICROWAVE THEORY AND APPLICATIONS, Steven F.
Adam, Hewlett Packard, Prentice Hall.
F CIRCUIT DESIGN, Chris Bowick, Howard Sams & Co.,
1982.
INTRODUCTION TO COMMUNICATIONS SYSTEMS,
Ferrel Stremler, Addison Wesley.
ARRL ANTENNA HANDBOOK, American Radio Relay
League, Newington, CT.
STANDARD RADIO COMMUNICATIONS MANUAL, R.H.
Kinley, CET, Prentice Hall, 1985.
In addition, you may find very timely design and
component information in the following magazines:
R.F. DESIGN, Cardiff Publishing (708) 647-0756.
MICROWAVES AND RF, Penton Publishing (216) 696-7000.
PASSIVE COMPONENTS
The availability of passive components; coils, filters,
crystals, capaCitors, resonators, resistors, etc., is often a
larger problem than finding the RF or analog IC to meet a
designer's needs. The Motorola applications engineering
team considers this a key issue when developing the circuits
shown in our data sheets. Analog Applications has worked
with many suppliers to develop practical and reasonably
priced passive component selections. Suppliers who have a
global support structure and can supply both prototype and
production quantities are listed. The following table lists a
number of suppliers which have been used in recent
applications. The design engineer will also need information
on the performance of the components as a function of
temperature, frequency, solderability and reliability. Most of
these suppliers have applications-engineering support with a
wealth of specific technical information. Motorola, however,
cannot warrant the suppliers' quality, availability, or prices.
8--371
II
Motorola suggests contacting the suppliers directly to obtain
technical information and competitive quotes.
In many cases, recommendations have been made to use
readily available sources such as "Radio Shack" for small
parts and construction material. The user is encouraged to
develop a core of dependable and local, if possible, suppliers
for his or her passive components. Please note that many
data sheets have specific passive components which have
been used to develop and characterize the integrated circuit.
Constructing a benchmark circuit with these components is
an excellent starting point in the development of a new
design.
COMPONENT SUPPLIERS
QUARTZ CRYSTALS - FREQUENCY CONTROL:
California Crystal Laboratories
(800) 333-9825
(813) 693-0099
Fox Electronics
International Crystals
(405) 236-3741
(818) 443-2121
Standard Crystal Corporation
GENERAL COMPONENTS - PROTOTYPE
QUANTITIES - ASSEMBLY MATERIAL - PC BOARD
MATERIAL:
(800) 344-4539
Digi-Key Corporation
(See local telephone directory)
Radio Shack Division,
Tandy Corporation
INDUCTORS, COILS, RF TRANSFORMERS, FIXED AND
VARIABLE:
(800) 322-COIL
Coilcraft
(708) 639-6400
(708) 297-0070
Toko America, Inc.
CERAMIC FILTERS AND RESONATORS, IF FILTERSAM & FM TYPES:
muRata Erie
(404) 436-1300 (Todd
Brown, Harry Moore)
(708) 803-6100
TDK Corporation of America
(708) 297-0070
Toko America, Inc.
The RF designer will find recommended PC board layouts
for most of the communications circuits in Chapter 8. These
layouts are strongly recommended as starting pOints for new
designs. They will allow you to develop your own benchmark
standard circuit to be' used as a standard of comparison
during further design iterations. Many Motorola
communications ICs have supporting development kits which
include a PC board. These boards are meant to provide
performance equivalent to the data sheet specifications, and
are easy to modify for other ljses however, these boards are
not optimized or intended for production applications.
Contact your Motorola sales office ,or Motorola distributor for
information on the availability of these development kits.
In addition, there are many PC and Macintosh-based CAD
programs available today. In general, these programs work
well for digital and low frequency analog circuits, but are of
very limited value in RF applications. SPICE models are not
currently available for the communications circuits. Several
circuits do show S-Parameter data or admittance plane
information which may be used to optimize input or output
matching for gain or noise. The most useful method of
utilizing the applications circuits at different frequencies is
simple linear scaling of the tuning and reactive elements. This
method is generally applicable over a 2:1 frequency range
lower than the documented application.
Many communication applications include some digital
signaling, data conversion, or microcontroller interface. The
RF Designer must take great caution to avoid interference
with the low level analog circuits in these mixed-mode
systems. The receivers are particularly susceptible to
interference as they respond to signals of only a few
microvolts. Make sure the clock frequency is not a
submultiple of the receiver input or IF frequencies. Be sure to
keep the dc supply lines for the digital and analog portions
separate. Avoid ground paths carrying common digital and
analog currents. Common sense as well as analytical skill is
required for a successful RF design. A good consultant may
well save many times their fee in material, lost time, and
rework expenses.
TEST EQUIPMENT
BREADBOARDING
Breadboarding RF or other high speed analog circuits can
be a very frustrating process for the newcomer or even an
experienced digital designer. Most of these circuits deal with
very high gain (100+ dB), very small ~ignals of less than a few
microvolts, or with very high frequencies with wavelengths
that are a fraction of a meter. Once "friendly" 0.1 I1F
capaCitors may act as inductors, due to their parasitic
inductance, while conventional construction methods may
yield only circuits that oscillate.
What to avoid (never use these):
- Wire wrap for RF or high frequency breadboards.
- Conventional push-in prototype boards.
- Digital printed protoboards with ground and power
supply bus lines.
What to use:
- Carefully laid-out double-sided groundplane PC
boards.
- Grid boards with a backside ground plane.
- Single-sided PC layouts with continuous full ground fill.
- High frequency qualified components.
- Adequate decoupling.
8-372
Establishing a new RF/Communications lab can be a wiry
costly investment. The normal DVMs and regulated power
supplies are generally acceptable, if they do not generate
spurious RF, and are not sensitive to RF voltages. The
Designer should choose an oscilloscope with a frequency
response three or more times higher than the operating
frequency. In addition, a low capacitance probe, a FET probe,
would be useful. Remember, while conventional probes have
very high input resistance, their capacitive reactance
decreases with frequency and becomes a limiting factor
above 30 MHz. For most transmitter work, a basic spectrum
analyzer is a must to help confirm power output, spurious
output levels, stability, and modulation characteristics.
Rental and used equipment are often a good source of test
equipment. Communications System Analysers have
recently become available at very moderate prices. The
Motorola R2600, for example, combines 16 different
instruments into one portable package. The signal generator,
receiver, counter, oscilloscope and a "best-in-class"
modulation meter make this instrument a very attractive
design and production test tool. Further information, including
a demonstration, are available from your local Motorola
Communications and Electronics sales office.
MOTOROLA ANALOG IC DEVICE DATA
WORLDWIDE CORDLESS
TELEPHONE FREQUENCIES
The following tables contain CT-1 USA and Asia Pacific
(CT-o Europe) frequencies for cordless telephone. These
tables reference application information provided in
MC13109, MC13110, and MC13111 Universal Cordless
Telephone Subsystem Integrated Circuit Technical Data
Sheets. Channel number, T x channel frequency, 1st LO
frequency, and T x and Rx divider values are listed in this
addendum. The device data sheets can be found in Chapter
8 of this Data Book (DL128).
Note: USA cordless frequency band listed herein is
specified in the Code of Federal Regulations (CFR), Title 47
(FCC Rules), Part 15, paragraph 15.233, dated June 5,1995
(25 channel band).
CHANNEL FREQUENCIES
USA CT-1 BASESET CHANNEL FREQUENCIES (2nd LO =10.240 MHz, Ref Divider =2048)
Channel
Tx Channel
Tx Divider
Number
Frequency (MHz)
(5.0 kHz Ref)
1.1 LO Frequency (MHz)
101 IF = 10.695 MHz
RxDlvlder
(5.0 kHz Ro1)
7613
1
43.720
8744
38.065
2
43.740
8748
38.145
7629
3
43.820
8764
38.165
7633
4
43.840
8768
38.225
7645
5
43.920
8784
38.325
7685
6
43.960
8792
38.385
7677
7
44.120
8824
38.405
7681
8
44.160
8832
38.465
7693
9
44.180
8836
38.505
7701
10
44.200
8840
38.545
7709
11
44.320
8864
38.585
7717
12
44,360
8872
38.665
7733
13
44.400
8880
38.705
7741
14
44.460
8892
38.765
7753
15
44.480
8896
38.805
7761
16
46.610
9322
38.975
7795
17
46.630
9326
39.150
7830
18
46.670
9334
39.165
7833
19
46.710
9342
39.075
7815
20
46.730
9346
39.180
7836
21
46.770
9354
39.135
7827
22
46.830
9366
39.195
7639
23
46.870
9374
39.235
7847
24
46.930
9386
39.295
7859
25
46.970
9394
39.275
7855
MOTOROLA ANALOG IC DEVICE DATA
8-373
USA CT-1 HANDSET CHANNEL FREQUENCIES (2nd LO = 10.240 MHz, Ref Divider = 2048)
Channel
Number
II
Tx Channel
TxDlvider
Frequency (MHz)
(5.0 kHz Rei)
1.1 LO Frequency (MHz)
1.1 IF =10.695 MHz
Rx Divider
(5.0 kHz Rei)
1
48.760
9752
33.025
6605
2
48.840
9768
33.045
6609
3
49.860
9772
33.125
6625
4
49.920
9784
33.145
6629
5
49.020
9804
33.225
6645
6
49.080
9816
33.265
6653
7
49.100
9820
33.425
6685
8
49.160
9832
33.495
6693
9
49.200
9840
33.485
6697
10
49.240
9848
33.505
6701
11
49.280
9856
33.625
6725
12
49.360
9872
33.665
6733
13
49.400
9880
33.705
6741
14
49.460
9892
33.765
6753
15
49.500
9900
33.785
6757
16
49.670
9934
35.915
7183
17
49.845
9969
35.935
7187
18
49.860
9972
35.975
7195
19
49.770
9954
36.015
7203
20
49.875
9975
36.035
7207
21
49.830
9966
36.075
7215
22
49.890
9978
36.135
7227
23
49.930
9986
36.175
7235
24
49.990
9998
36.235
7247
25
49.970
9994
36.275
7255
SPAIN CT-1 BASESET CHANNEL FREQUENCIES (2nd LO = 10.240 MHz, Ref Divider = 2048)
Channel
Number
Frequency (MHz)
1
31.025
6205
29.230
5846
2
31.050
6210
29.255
5851
3
31.075
6215
29.280
5856
4
31.100
6220
29.305
5861
TxChannei
Tx Divider
(5.0 kHz ReI)
1st LO Frequency (MHz)
1sliF = 10.695 MHz
Rx Divider
(5.0 kHz ReI)
5
31.125
6225
29.330
5868
6
31.150
6230
29.355
5871
7
31.175
6235
29.380
5876
8
31.200
6240
29.405
5881
9
31.250
6250
29.455
5891
10
31.275
6255
29.480
5896
11
31.300
6260
29.505
5901
12
31.325
6265
29.530
5906
8-374
MOTOROLA ANALOG IC DEVICE DATA
SPAIN CT-1 HANDSET CHANNEL FREQUENCIES (2nd LO = 10.240 MHz, Ref Divider = 2048)
Channel
Number
Tx Channel
Frequency (MHz)
Tx Divider
(5.0 kHz Ref)
1st LO Frequency (MHz)
1st IF = 10.695 MHz
Rx Divider
(5.0 kHz ReI)
4066
1
39.925
7985
20.330
2
39.950
7990
20.355
4071
3
39.975
7995
20.380
4076
4
40.000
8000
20.405
4081
5
40.025
8005
20.430
4086
6
40.050
6010
20.455
4091
7
40.075
6015
20.460
4096
6
40.100
6020
20.505
4101
9
40.150
6030
20.555
4111
10
40.175
6035
20.560
4116
11
40.200
6040
20.605
4121
12
40.225
6045
20.630
4126
AUSTRALIA CT-1 BASESET CHANNEL FREQUENCIES (2nd LO =10.240 MHz, Ref Divider = 2048)
Channel
Number
Tx Channel
Frequency (MHz)
Tx Divider
(5.0 kHz Rei)
1st LO Frequency (MHz)
1st IF = 10.695 MHz
RxDivider
(5.0 kHz ReI)
1
30.075
6015
29.060
5616
2
30.125
6025
29.130
5626
3
30.175
6035
29.180
5836
4
30.225
6045
29.230
5646
5
30.275
6055
29.280
5856
6
30.100
6020
29.105
5821
7
30.150
6030
29.155
5831
8
30.200
6040
29.205
5841
9
30.250
6050
29.255
5851
10
30.300
6060
29.305
5861
II
AUSTRALIA CT-1 HANDSET CHANNEL FREQUENCIES (2nd LO = 10.240 MHz, Ref Divider = 2048)
Channel
Number
Tx Channel
Frequency (MHz)
Tx Divider
(5.0 kHz Ref)
1st LO Frequency (MHz)
1st IF = 10.695 MHz
RxDivider
(5.0 kHz Rei)
1
39.775
7955
19.380
3876
2
39.625
7965
19.430
3866
3
39.675
7975
19.460
3696
4
39.925
7965
19.530
3906
5
39.975
7995
19.560
3916
6
39.600
7960
19.405
3881
7
39.850
7970
19.455
3691
6
39.900
7960
19.505
3901
9
39.950
7990
19.555
3911
10
40.000
6000
19.605
3921
MOTOROLA ANALOG IC DEVICE DATA
8-375
KOREA CT-1 BASESET CHANNEL FREQUENCIES (2nd LO =10.240 MHz, Ref Divider =2048)
Channel
Number
TxChannei
TxDivider
Frequency (MHz)
(5.0 kHz Ref)
1.1 LO Frequency (MHz)
1stlF = 10.&95 MHz
Rx Divider
(5.0 kHz Ref)
7795
1
46.610
9322
38.975
2
46.630
9326
39.150
7830
3
46.670
9334
39.165
7633
4
46.710
9342
39.075
7815
5
46.730
9346
39.180
7836
6
46.770
9354
39.135
7827
7
46.830
9356
39.195
7839
8
46.870
9374
39.235
7847
9
46.930
9386
39.295
7859
10
46.970
9394
39.275
7855
11
46.510
9302
39.000
7800
12
46.530
9306
39.015
7803
13
46.550
9310
39.030
7806
14
46.570
9314
39.045
7809
15
46.590
9318
39.060
7812
KOREA CT-1 HANDSET CHANNEL FREQUENCIES (2nd LO =10.240 MHz, Ref Divider =2048)
II
Channel
Tx Channel
Number
Frequency (MHz)
TxDlvlder
(5.0 kHz Ref)
1st LO Frequency (MHz)
1st IF = 10.&95 MHz
Rx Divider
(5.0 kHz Ref)
1
49.670
9934
35.915
7183
2
49.845
9969
35.935
7187
3
49.860
9972
35.975
7195
4
49.770
9954
36.015
7203
5
49.875
9975
36.035
7207
6
49.830
9966
36.075
7215
7
49.890
9978
36.135
7227
8
49.930
9986
36.175
7235
9
49.990
9998
36.235
7247
10
49.970
9994
36.275
7255
11
49.695
9939
35.815
7163
12
49.710
9942
35.835
7167
13
49.725
9945
35.855
7171
14
49.740
9948
35.875
7175
15
49.755
9951
36.895
7179
8-376
MOTOROLA ANALOG IC DEVICE DATA
NEW ZEALAND CT-1 BASESET CHANNEL FREQUENCIES (2nd LO =10.240 MHz, Ref Divider =2048)
Channel Number
Tx Channel
Frequency (MHz)
Tx Divider
(5.0 kHz Ref)
1st LO Frequency (MHz)
1st IF = 10.695 MHz
RxDfvlder
(5.0 kHz ReI)
5911
11
34.250
6850
29.555
12
34.275
6855
29.580
5916
13
34.300
6860
29.605
5921
14
34.325
6865
29.630
5926
15
34.350
6870
29.655
5931
16
34.375
6875
29.680
5936
17
34.400
6880
29.705
5941
18
34.425
6885
29.730
5946
19
34.450
6890
29.755
5951
20
34.475
6895
29.780
5956
NEW ZEALAND CT-1 HANDSET CHANNEL FREQUENCIES (2nd LO = 10.240 MHz, Ref Divider =2048)
Channel
Number
Tx Divider
(5.0 kHz Ref)
1st LO Frequency (MHz)
Frequency (MHz)
Tx Channel
1st IF =10.695 MHz
RxDlvider
(5.0 kHz ReI)
11
40.250
8050
23.555
4711
12
40.275
8055
23.580
4716
13
40.300
8060
23.605
4721
14
40.325
8065
23.630
4726
15
40.350
8070
23.655
4731
16
40.375
8075
23.680
4736
17
40.400
8080
23.705
4741
18
40.425
8085
23.730
4746
19
40.450
8090
23.755
4751
20
40.475
8095
23.780
4756
U.K. BASESET CHANNEL FREQUENCIES (2nd LO = 11.150 MHz, Ref Divider = 446 + divide by 4/25)
Channel Number
Tx Channel
Frequency (MHz)
Tx Divider
(1.0 kHz Ref)
1 st LO Frequency (MHz)
lstiF = 10.7 MHz
RxDlvider
(6.25 kHz Ref)
1
1.642
1642
36.75625
5881
2
1.662
1662
36.76875
5883
3
1.682
1682
36.78125
5885
4
1.702
1702
36.79375
5887
5
1.722
1722
36.80625
5889
6
1.742
1742
36.81875
5891
7
1.762
1762
36.83125
5893
8
1.782
1782
36.94375
5895
U.K. HANDSET CHANNEL FREQUENCIES (2nd LO = 11.150 MHz, Ref Divider = 446 + divide by 4/25)
Channel Number
Tx Divider
(6.25 kHz Ref)
1st LO Frequency (MHz)
Frequency (MHz)
Tx Channel
1st IF = 10.7 MHz
RxDlvlder
(1.0 kHz ReI)
1
47.45625
7593
12.342
12342
2
47.46875
7595
12.362
12362
3
47.48125
7597
12.382
12382
4
47.49375
7599
12.402
12402
5
47.50625
7601
12.422
12422
6
47.51875
7603
12.442
12442
7
47.53125
7605
12.462
12462
8
47.54375
7607
12.482
12482
MOTOROLA ANALOG IC DEVICE DATA
&-377
FRANCE BASESET CHANNEL FREQUENCIES (2nd LO = 11.150 MHz, Ref Divider = 1784)
Channel
Number
TxChannel
Frequency (MHz)
TxDlvider
(6.25 kHz Ref)
1st LO Frequency (MHz)
1st IF = 10.7 MHz
1
26.3125
4210
30.6125
4898
2
26.3250
4212
30.6250
4900
4902
RxDivlder
(6.25 kHz ReI)
3
26.3375
4214
30.6375
4
26.3500
4216
30.6500
4904
5
26.3625
4218
30.6625
4906
6
26.3750
4220
30.6750
4908
7
26.3875
4222
30.6875
4910
8
26.4000
4224
30.7000
4912
9
26.4125
4226
30.7125
4914
10
26.4250
4228
30.7250
4916
11
26.4375
4230
30.7375
4918
12
26.4500
4232
30.7500
4920
13
26.4625
4234
30.7625
4922
14
26.4750
4236
30.7750
4924
15
26.4875
4238
30.7875
4926
FRANCE HANDSET CHANNEL FREQUENCIES (2nd LO =11.150 MHz, Ref Divider =1784)
Channel
Number
Tx Channal
Frequency (MHz)
(6.25 kHz Rei)
1st LO Frequency (MHz)
1st IF = 10.7 MHz
Rx Divider
(6.25 kHz ReI)
8-378
Tx Divider
1
41.3125
6610
37.0125
5922
2
41.3250
6612
37.0250
5924
3
41.3375
6614
37.0375
5926
4
41.3500
6616
37.0500
5928
5
41.3625
6618
37.0625
5930
6
41.3750
6620
37.0750
5932
7
41.3875
6622
37.0875
5934
8
41.4000
6624
37.1000
5936
9
41.4125
6626
37.1125
5938
10
41.4250
6628
37.1250
5940
11
41.4375
6630
37.1375
5942
12
41.4500
6632
37.1500
5944
13
41.4625
6634
37.1625
5946
14
41.4750
6636
37.1750
5948
15
41.4875
6638
37.1875
5950
MOTOROLA ANALOG IC DEV.!fx
MC4446t
MC444Il2.'
MC44463
I I~· I
I I DelayLme I
I I MC44140 I
I L_
__...I
Set-TopBpx
IDVEl
~
,------,
I1~1Qek
Genemtor
II
IL
MC44145
I
_ _ _ _ _ ...J
...I
Comb Filter
/'
MC141620
MC141621A
MC141622A
MCi41624
M¢141627
V Sync
HSync
IF
MC44aOl"
MC~·
Antenna
II
• In Development
** Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
Digitally Controlled Video Processor for Multimedia Applications
MC44011FN, FB
Case 777, 824E
The MC44011, a member of the MC44000 Chroma 4
family, is designed to provide RGB or YUV outputs from a
variety of inputs. The inputs may be either PAL or NTSC
composite video (two inputs), S-VHS, RGB, and color
difference (R-Y, B-Y).
The MC44011 provides a sampling clock output for use
by a subsequent analog to digital converter. The sampling
clock (6.0 to 40 MHz) is phase-locked to the horizontal
frequency. Additional outputs include composite sync,
vertical sync, field identification, luminance, burst gate, and
horizontal frequency.
Control of the MC44011, and reading of status flags is
accomplished via an 12C bus.
• Multistandard Decoder, Accepts NTSC and PAL
Composite Video
• Dual Composite Video or S-VHS Inputs
• All Chroma and Luma Channel Filtering, and Luma Delay
Line are Integrated Using Sampled Data Filters Requiring
no External components
• Digitally Controlled via 12C Bus
•
•
•
•
•
•
Auxiliary Y, R-Y, B-Y Inputs
Switched RGB Inputs with Separate Saturation Control
Line-Locked Sampling Clock for Digitizing Video Signals
Burst Gate Pulse Output for External Clamping
Vertical Sync and Field Ident Outputs
Software Selectable YUV or RGB Outputs Able to Drive
AID Converters
_ _ _In....~~ts_ __
Outputs
VCC1 Gnd1
~
r-------r-~----
R-Y B-Y Y2
CompVideo 1
~}
Comp Video 2
Outputs
BlU
II
VCC2
t-----OVCC3
Burst
Gate
16Fhl Filter
CSYNC Switch
H
Filter
Quiet
Gnd
Fh
Ref.
15k
Ret.
PLL
Filter
Clock
To NO Converters
....n...
Frequency
Divider
MOTOROLA ANALOG IC DEVICE DATA
9-7
Video Circuits
(continued)
Triple a-Bit D/A Converter
MC44200FB
Case 824A
The MC44200 is a monolithic digital to analog converter for
three independent channels fabricated in CMOS technology.
The part is specifically designed for video applications.
Differential outputs are provided, allowing for a large output
voltage range.
• B-Bit Resolution
• Differential Outputs
•
•
•
•
•
•
55 msps Conversion Speed
Large Output Voltage Range
Low Current Mode
Single 5.0 V Power Supply
TTL Compatible Inputs
Integrated Reference Voltage
r-------------..,
r-~_J'\
vooo
Gin
r--+----~
Rln
r-""7\o--.rl vOOR
~-+--~~
OR
I<.....,,,,,,-,,-'V OR
8 In
r+-+--~~
OG
I<.....,~--'V OG
r::-"""7\o--.rl VODB
I<.....,~-'V
08
08
t----+-<)--~f____o
Clk o----<~-'
VOO
CCAS
?-t
VSS~
Rlrel
l----"eIJ--O----lf-----l
I
Vss R 0--------------------'
L.. _ _ _ _ _ _ _ _ _ _ _ _ JI
VDD R 0------------------'"
CVref
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
Triple 8-Bit AID Converter
MC44251FN
Case 777
The MC44251 contains three independent parallel analog
to digital converters. Each ADC consists of 256 latching
comparators and an encoder. Input clamps allow for AC
coupling of the input signals, and dc coupling is also allowed.
For video processing performance enhancements, a dither
generator with subsequent digital correction is provided to
each ADC. The outputs of the MC44251 can be set to a high
impedance state.
These AIDs are especially suitable as front end converters
in TV picture processing.
• 18 MHz Maximum Conversion Speed (MC44251)
• Input Clamps Suitable for RGB and YUV Applications
• Built-in Dither Generator with Subsequent
Digital Correction
• Single 5.0 V Power Supply
Simplified Diagram of One of the ADCs
Rtop
Rmid
II
8
Data
Outputs
Clock
Analog Input
HZ
VTN
Mode
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
Color TV Block Diagram
r------,
I PbHn-P1x I
I MC44461 I
I ; MC444fl2' I
IL _MC44483
_ _ _ _ .JI
<
TunerPlL
r-----,
MC44e17
I
MC448HI
MC44824
MC44825
MC44826
IF
MC44301"
MC44827
MC44828
MC44829
MC44864
Comb Filler
I
Mc14~ I-'-_Y-,--_~
MC141621A I
R
G
B
I MC141622
C
I MC141624 I+-~-~
I MCt4t627 I
L _ _ _ _ .J
MC443IJ2'
aSD
r--------,
L:..:AM=M:::.on::.o_ _ _-..!1
FM Mono
Stereo
$tereoOeooder
I-tl-+------I>
Sound PIOOeSSQI'
n
MC44131
L _ _ _ _ _ _ _ ...J
SMPS
MC44603'
MC44605
MJF18OO4(61P)
MTP3N60E(TMOS)
II
+200 V
+12V
MCU
+5.0 V
r-----,
II
Op1fonai
II
L _ _ _ _ .J
• In Development
". Not recommended for new designs.
9-10
MOTOROLA ANALOG IC DEVIC'E DATA
Video Circuits
(continued)
Multistandard VideolTimebase Processor
MC44002P, MC44007P
Case 711
The MC4400217 is a highly advanced circuit which
performs most of the basic functions required for a color TV.
All of its advanced features are under processor control via an
12C bus, enabling potentiometer controls to be removed
completely. In this way the component count may be reduced
dramatically to allow significant cost savings and the
possibility of implementing sophisticated automatic test
routines. Using the MC44002l7, TV manufacturers will be able
to build a standard chassis for anywhere in the world.
• Operation from a Single 5.0 V Supply; Typical Current
Consumption Only 120 rnA
• Full PAUSECAM/NTSC Capability (MC44002 Only)
• MC44007 Decodes PAUNTSC Only
• Dual CompOSite Video or S-VHS Inputs
• All ChromalLuma Channel Filtering, and Luma Delay
Line are Integrated Using Sampled Data Filters Requiring
No External Components
• Filters Automatically Commutate with Change
of Standard
• Chroma Delay Line is Realized with Companion
Device (MC44140)
• RGB Drives Incorporate Contrast and Brightness
Controls and Auto Gray Scale
• Switched RGB Inputs with Saturation Control
• Auxiliary V, R-V, B-V Inputs
• Line Timebase Featuring H-Phase Control and
Switchable Phase Detector Gain and Time Constant
• Vertical Timebase Incorporating the Vertical
Geometry Corrections
• E-W Parabola Drive Incorporating the Horizontal
Geometry Corrections
• Beam Current Monitor with Breathing Compensation
• 16:9 Display Mode Capability
II
MOTOROLA ANALOG Ie DEVICE DATA
9-11
Video Circuits
(continued)
Advanced NTSC Comb Filter
MC141621FB
Case 898
The MC141621 is an advanced NTSC comb filter for VCR
and TV applications. It separates the luminance(Y) and
chrominance (C) signals from the NTSC composite video
signal by using digital signal processing techniques. This filter
allows a video signal input of an extended frequency
bandwidth by using a 4.0 FSC clock. In addition, the filter
minimizes dot crawl and cross color effects. The built-in AID
and D/A converters allow easy connections to analog video
circuits.
Co C1
C:1 C3
•
•
•
•
•
•
•
Built-in High Speed 8-Bit AID Converter
Two Line Memories (1820 Bytes)
Advanced Combing Process
Two 8-Bit D/A Converters
Built-in Clamp Circuit
On-Chip Reference Voltage Regulator for ADC
Digital Interface Mode
RTP
C4 Cs C6 C7
28
RTPS
27
Self
Bias
23
22
ADC
IBias
RBTS
RBT
21
Yin
20
Yout
Clout
Ref(OA)
II
Cout
Clamp
18
17
16
CLC
TE1
TEo
Mode 1
VCC(AO) = Pin 25
VCC(O) = Pin 11
VCC(OA~ = Pin 42
GNO(AO = Pin 26
GNO(O) = Pins 9,19
GNO(OA) = Pin 43
9-12
Mode 0
DO 01 02 03 04 05 06
OJ
13
BW
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
Advanced Comb Filter-II (ACF-II)
MC141622AFU
Case 898
The Advanced Comb Filter-II is a video signal processor
for VCRs and TVs. II's function is to separate the Luminance
Y and Chrominance C signals from the NTSC composite video
signal. The ACF-II minimizes dot-<:rawl and cross-<:olor. A
built-in PLL provides a 4xfsc clock from either an NTSC
subcarrier signal or a 4xfsc input. This allows a video signal
input of an extended frequency bandwidth. The built-in
vertical enhancer circuit improves the quality of the
Luminance Y signal. The built-in AID and D/A converters
allow easy connection to analog video circuits.
•
•
•
•
•
•
•
•
•
Built-in High Speed 8-Bit AID Converter
Two Line Memories (1820 Bytes)
Advanced Comb-II Process
Vertical Enhancer Circuit
Two High Speed 8-Bit D/A Converters
4xfsc PLL Circuit
Built-in Clamp Circuit
Digital Interface Mode
On-Ghip Reference Voltage Regulator for AID Converter
03
TE1
02
TEO
01
MODE1
DO
MODEO
BK
II
ClK(AD)
ACF-II
PROCESSING
VH
GND(D)
GNO(O)
VCC(D)
VCC(O)
CLC
FSC
NC
NC
RBT
NC
RTP
:z
::J
u:::
MOTOROLA ANALOG IC DEVICE DATA
9-13
Video Circuits
(continued)
Closed-Caption Decoder
MC144143P
Case 707
The MC144143 is a Line 21 closed-caption decoder for
use in television receivers or set top decoders conforming to
the NTSC broadcast standard. Capability for processing and
displaying all of the latest standard Line 21 closed-caption
format transmissions is included. The device requires a
closed-caption encoded composite video signal, a horizontal
sync signal, and an external keyerto produce captioned video.
RGB outputs are provided, along with a luminance and a box
signal, allowing simple interface to both color and black and
white receivers.
• Conforms to the FCC Report and Order as Amended by
the Petition for Reconsideration on Gen. Doc. 91-1
• Supports Four Different Data Channels, Time Multiplexed
within the Line 21 Data Stream: Captions Utilizing
Languages 1 & 2, Plus Text Utilizing Languages 1 & 2
• Output Logic Provides Hardware Underline Control and
Italics Slant Generation
• Single Supply Operating Voltage Range: 4.75 to 5.25 V
• Composite Video Input Range: 0.7 to 1.4 Vpp
• Horizontal Sync Input Polarity can be either Positive
or Negative
• Internal Timing/Sync Signals Derived from
On-ChipVCO
Data Modulator &
Transfer Buffer
Video
In
Slice
12
Level - - - / - - - - - 1
Command
Processor
Lock
R
6
Output
Logic
4
3
Hsync
Fi~er
Reset
Config
CT/SData
LanglSClk
B
Luma
Box
2
16
Decoder
Control
Enable
9-14
7
G
17
18
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
Enhanced Closed-Caption Decoder
MC144144P
Case 707
The MC144144 is a Line 21 closed-caption decoder for
use in television receivers or set-top decoders conforming to
the NTSC standard. Capability for processing and displaying
all of the latest standard Line 21 closed-caption format
transmissions is included. The device requires a closedcaption encoded composite video signal, a horizontal sync
signal, and an external keyer to produce captioned video.
RGB and box signal outputs are provided, which along with
the mode select, allow simple interfacing to either color or
black-and-white TV receivers.
Display storage is accomplished with an on-chip RAM. A
modified ASCII character set, which includes several
non-English characters, is decoded by an on-chip ROM. An
on-screen character appears as a white or colored dot matrix
on a black background.
Captions (video-related information) can be up to four rows
appearing anywhere on the screen and can be displayed in two
modes: roll-up, paint-on, or pop-on. With rollup captions, the
row scrolls up and new information appears at the bottom row
each time a carriage retum is received. Pop-on captions work
with two memories. One memory is displayed while the other
is used to accumulate new data. A special command causes
the information to be exchanged in the two memories, thus
causing the entire caption to appear at once.
When text (non-video related information) is displayed, the
rows contain a maximum of 32 characters over a black box
which overwrites the screen. Fifteen rows of characters are
displayed in the text mode.
MOTOROLA ANALOG IC DEVICE DATA
An on-chip processor controls the manipulation of data for
storage and display. Also controlled are the loading,
addressing, and clearing of the display RAM. The processor
transfers the data received to the RAM during scan lines 21
through 42. The operation of the display RAM, character ROM,
and output logic circuits are controlled during scan lines 43
through 237. The functions olthe MC144144 are controlled via
a serial port which may be configured to be either 12C or SPI.
• Conforms to FCC Report and Order as Amended by the
Petition for
Reconsideration on Gen. Doc. 91-1
• Conforms to EIA-608 for XDS Data Structure
• Supports Four Different Data Channels for Field 1 and
Five Different Data Channels for Field 2, Time
Multiplexed within the Line 21 Data Stream: Captions
Utilizing Languages 1 and 2, Text Utilizing Languages 1
and 2 and XDS Support
• Output Logic Provides Hardware Underline Control and
Italics Slant Generation
• Single Supply, Operating Voltage Range: 4.75 to 5.25 V
• Supply Current: 20 mA (Preliminary)
• Operating Temperature Range: 0 to 70°C
• Composite Video Input Range: 0.7 to 1.4 Vpp
• Horizontal Input Polarity: Either Positive or Negative
• Internal Timing and Sync Signals Derived from On-Chip
VCO
9-15
II
II
sc.
!m
~~~~-----------------,
VIDEO~.
::;:
-I
til
~
~
CSYNCI
CGlINES
~
a..
8
FLD
i!l:
~
SFLP
????
!;
l>
Z
l>
"c
(')
~
(')
m
c
~
~
-
I
',< I
ADDR
DECODER
FlD
Ls"
o
5
~
o
~r
c
1
LINE & FLD
CTR
LINE AND FLO
DECODERS
11
-------~~-lr~;--~;;
Td:
-=
LOOP
~ FILTER
-=
r;;l
~
---
17 3 2 18
g
a3'
1
Video Circuits
(continued)
Set-Top Block Diagram
TunerPLL
MC44817
MC44818
MC44824
MC44825
, -----,I
I PiX-ln-PIx I
I MC44461
I MC44462' I
I MC44463 I
MC44826
MC44827
MC44828
MC44829
MC44864
L___
...J
• R
• G
• B
Tuner
MC44361 ,
MC44362'
MC44365'
IF
MC44301'"
MC443Ol!'
,,:±::t::::t:=,"
I RGBto
I VIdeo
Encoder
I MC13077
IL'-_-_-_-_~...J
,----,
I1~~Channel
Modulator
~ 314
I
r
MC1374
I
L _ _ _ _ ...J
Power PC
Embedded Controller
II
Digital Sound Section
• In Development
** Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
9-17
Video Circuits (continued)
PLL Tuning Circuits with 3-Wire Bus
MC44817BD, D
Case 751B
The MC44817/17B are tuning circuits for TV and VCR
tuner applications. They contain on one chip all the functions
required for PLL control of a VCO. The integrated circuits also
contain a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44817 has programmable 51211024 reference
dividers while the MC44817B has a fixed reference divider of
1024.
The MC44817/17B are manufactured on a single silicon
chip using Motorola's high density bipolar process, MOSAICTM
(Motorola Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (3-Wire
Bus). Data and Clock Inputs are IIC Bus Compatible
• Divide-by--8 Prescaler Accepts Frequencies up to
1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies
up to 165 MHz
• Reference Divider: Programmable for Division Ratios 512
and 1024. The MC44817B has a Fixed 1024 Reference
Divider
• 3-State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output
(30 V)
• Four Integrated PNP Band Buffers for 40 mA (VCC1 to .
14.4 V)
• Output Options for the Reference Frequency and the
Programmable Divider
• Bus Protocol for 18 or 19 Bit Transmission
• Extra Protocol for 34 Bit for Test and Further Features
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
• Fully ESD Protected
Bands Out 30 rnA
(40 rnA at 0° to BO°C)
VTUN
VCC3
13
B3
12 11
10
6
4
~ B1 Bo
Arnpln
Buffers
-=
Lock
XTAL
9-18
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
PLL Tuning Circuit with 12C Bus
MC44818D
Case 751B
The MC44818 is a tuning circuit for TV and VCR tuner
applications. It contains, on one chip, all the functions required
for PLL control of a VCO. This integrated circuit also contains
a high frequency prescaler and thus can handle frequencies
up to 1.3 GHz. The MC44818 is a pin compatible drop-in
replacementforthe MC44817, where the only difference is the
MC44818 has a fixed divide-by-8 prescaler (cannot be
bypassed) and the MC44817 uses the three wire bus.
The MC44818 has programmable 512/1024 reference
dividers and is manufactured on a single silicon chip using
Motorola's high density bipolar process, MOSAICTM (Motorola
Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (12C Bus).
Data and Clock Inputs are 3-Wire Bus Compatible
• Divide-by-8 Prescaler Accepts Frequencies up to
1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies
up to 165 MHz
• Reference Divider: Programmable for Division Ratios 512
and 1024.
• 3-State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output
(30 V)
• Four Integrated PNP Band Buffers for 40 mA (VCC1 to
14.4 V)
• Output Options for the Reference Frequency and the
Programmable Divider
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
• Fully ESD Protected
Bands Out 30 rnA
(40 rnA at 0° to BO°C)
VrUN
VCC3
13
B3
12 11
10
6
4
B2 Bl BO
Amp In
Buffers
II
-=Lock
XTAL
MOTOROLA ANALOG IC DEVICE DATA
9-19
Video Circuits
(continued)
PLL Tuning Circuits with 12C Bus
MC44824/25D
Case 751A, 751B
The MC44824/25 are tuning circuits for TV and VCR tuner
applications. They contain on one chip all the functions
required for PLL control of a VCO. The integrated circuits also
contain a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44824/25 are manufactured on a single silicon chip
using Motorola's high density bipolar process, MOSAICTM
(Motorola Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (12C Bus).
Data and Clock Inputs are 3-Wire Bus Compatible
• Divide-by-8 Prescaler Accepts Frequencies up to
1.3 GHz
• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512
and 1024
• 3-8tate Phase/Frequency Comparator
• 4 Programmable Chip Addresses
• 3 Output Buffers (MC44824) respectively; 5 Output
Buffers (MC44825) for 10 mAl15 V
• Operational Amplifier for use with Extemal NPN Transistor
• SO-14 Package for MC44824 and SO-16 for MC44825
• High Sensitivity Preamplifier
• Fully ESD Protected
UD
Vcc
5.0V
10 (12)
6(6)
B7
- (7)
B4
8(9)
~
Buffers
9(10)
Bl
-(11)
14(16)
1(1
Bo
PO
2.7 V
Gnd
XTALl
XTAL2
HF Inputl n.....-'--'w ' .....
HFlnput2..,--........
MC44825 Pin Numbers ( )
9-20
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
PLL Tuning Circuit with 3-Wire Bus
MC44827DTB
Case 948F
The MC44827 is a tuning circuit for TV and VCR tuner
applications. This device contains on one chip all the functions
required for PLL control of a VCO. This integrated circuit also
contains a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44827 is controlled by a 3-wire bus. It has the
same function as the MC44828 which is 12C bus controlled.
The MC44827 and MC44828 can replace each other to allow
conversion between 3-wire bus and 12C bus control.
The MC44827 is manufactured on a single silicon chip
using Motorola's high density bipolar process, MOSAICTM
(Motorola Oxide Self Aligned Implanted Circuits).
The MC44827 has the same features as MC44817 with the
following differences:
• Lower Power Consumption, 200 mW Typical
• Improved Prescaler with Higher Margins for Sensitivity
and Temperature Range. (A typical device is functional in
a temperature range greater than -40 to 100°C.)
• Lock Detector with Push-Pull Output
• No Bypass of Divide-by-8 Prescaler
• TSSOP Package
PLL Tuning Circuit with 12C Bus
MC44828DTB
Case 948F
The MC44828 is a tuning circuit for TV and VCR tuner
applications. This device contains on one chip all the functions
required for PLL control of a VCO. This integrated circuit also
contains a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44828 is controlled by an 12C bus. It has the same
function as the MC44827 which is 3-wire bus controlled. The
MC44827 and MC44828 can replace each other to allow
conversion between 3-wire bus and 12C bus control.
The MC44828 is manufactured on a single silicon chip
using Motorola's high density bipolar process, MOSAICTM
(Motorola Oxide Self Aligned Implanted Circuits).
MOTOROLA ANALOG IC DEVICE DATA
The MC44828 has the same features as MC44818 with the
following differences:
• Lower Power Consumption, 200 mW Typical
• Improved Prescaler with Higher Margins for Sensitivity
and Temperature Range. (A typical device is functional in
a temperature range greater than -40 to 100°C.)
• Lock Detector with Push-Pull Output
• TSSOP Package
9-21
II
•
Video Circuits
(continued)
PLL Tuning Circuit with 12C Bus
MC44829D
Case 751A
The MC44829 is a tuning circuit for TV and VCR tuner
applications. It contains, on one chip, all the functions required
for PLL control of a VCO. This integrated circuit also contains
a high frequency prescaler and thus can handle frequencies
up to 1.3 GHz. The circuit has a band decoder that provides
the band switching signal for the mixer/oscillator circuit. The
decoder is controlled by the buffer bits.
The MC44829 has programmable 512/1024 reference
dividers and is manufactured on a single silicon chip using
Motorola's high density bipolar process, MOSAICTM (Motorola
Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (12C Bus)
• Divide--by-8 Prescaler Accepts Frequencies up to
1.3 GHz
• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512
and 1024
• 3-8tate Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output
(30 V)
• Four Programmable Chip Addresses
• Integrated Band Decoder for the Mixer/Oscillator Circuit
• Band Buffers with Low "On" Voltage (0,4 V Maximum at
5.0mA)
• Fully ESD Protected to MIL-STD-883C, Method 3015.7
(2000 V, 1.5 kQ, 150 pF)
VTUN
r-=-
Bands Out
VCCI
5.0 V 5
8
7
VCC2
CL
6
14
2.7 V
DTBI
Gnd
PHO
-=-
2
DTB2
POR
CA
SDA
SCL
9
11
10
CL
Data
RL
DTF
T12pF
CJ 3.214.0
MHz
.l
DTS, EN
9-22
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits
(continued)
Advanced PAUNTSC Encoder
MC13077P,
ow
Case 738, 7510
The MC13077 is an economical, high quality, RGB encoder
for PAL or NTSC applications. It accepts red, green, blue and
composite sync inputs and delivers either composite PAL or
NTSC video, and S-Video Chroma and Luma outputs. The
MC13077 is manufactured using Motorola'S high density,
bipolar MOSAIC® process.
• Single 5.0 V Supply
• CompOSite Output
•
•
•
•
•
•
•
•
S-Video Outputs
PAUNTSC Switchable
PAL Squarewave Output
PAL Sequence Resettable
InternaVExternal Burst Flag
Modulator Angles Accurate to 90°
Burst Position/Duration Determined Digitally
Subcarrier Reference from a Crystal or External Source
Vcc
Gnd
I----~----------------------~-----l
Divide By Four Ring
H
16
~
MOTOROLA ANALOG IC DEVICE DATA
3.581
4.43 MHz
Divide By 256
Counter
latch
I
I
I
I
I
I
I
II
PAL
F/F
R-Y
Clamp
9-23
Consumer Electronic Circuits Package Overview
•
CASE 626
PSUFFIX
-
CASE 707
PSUFFIX
CASE 711
PSUFFIX
II
•
CASE 751
o SUFFIX
CASE 751E
OW SUFFIX
9-24
CASE 646
PSUFFIX
CASE 648
PSUFFIX
CASE 709
PSUFFIX
CASE 710
PSUFFIX
-
-
CASE 724
PSUFFIX
CASE 751A
o SUFFIX
CASE 738
H, PSUFFIX
CASE751D
OW SUFFIX
CASE 751B
o SUFFIX
CASE 751F
OW SUFFIX
•
CASE 751G
OW SUFFIX
~OTOROLA ANALOG IC DEVICE DATA
Consumer Electronic Circuits Package Overview
•
CASE 777
FNSUFFIX
CASE 824, 824A
FBSUFFIX
CASE 859
BSUFFIX
• •
CASE 904
FSUFFIX
CASE948E
DTB SUFFIX
•
CASE 873
FUSUFFIX
•
CASE948F
DTBSUFFIX
(continued)
• •
CASE 824D
FTB SUFFIX
CASE 824E
FB SUFFIX
CASE 898
FB, FU, P SUFFIX
CASE948J
DTBSUFFIX
CASE 967
MSUFFIX
II
MOTOROLA ANALOG IC DEVICE DATA
9-25
Device Listing and Related Literature
Entertainment Radio Receiver Circuits
Page
Device
Function
MC3340
MC13020
MC13022
MC13022A
MC13025
MC13027, MC13122
MC13028A
MC13029A
Electronic Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-66
Motorola C-QUAM AM Stereo Decoder . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-76
Advanced Medium Voltage AM Stereo Decoder ............................ 9-81
Advanced Medium Voltage AM Stereo Decoder ............................ 9-86
Electronically Tuned Radio Front End ..................................... 9-91
AMAX Stereo Chipset .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-94
Advanced Wide Voltage IF and C-QUAM AM Stereo Decoder ................ 9-119
Advanced Medium Voltage IF and C-QUAM AM Stereo Decoder with
FM Amplifier and AM/FM Internal Switch ................................ 9-137
Dual Conversion AM Receiver ............................................ 9-156
Mini-Watt Audio Output .................................................. 9-171
Low Power Audio Amplifier ............................................... 9-227
MC13030
MC13060
MC34119
Video Circuits
II
Page
Device
Function
CA3146
MC1350
MC1374
MC1377
MC1378
MC1391
MC3346
General Purpose Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-28
Monolithic IF Amplifier ................................................... 9-30
TV Modulator Circuit .................................................... 9-34
Color Television RGB to PAUNTSC Encoder ..... . . . . . . . . . . . . . . . . . . . . . . . . .. 9-42
Color Television Composite Video Overlay Synchronizer . . . . . . . . . . . . . . . . . . . .. 9-58
TV Horizontal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-62
General Purpose Transistor Array Cine Differentially Connected Pair
and Three Isolated Transistor Arrays .................................... 9-69
Advanced PAUNTSC Encoder ........................................... 9-175
Multimode Color Monitor Horizontal, Vertical, and
Video Combination Processor .......................................... 9-187
MC13077
MC13081X
MC13280AY,
MC13281AlB
MC13282A
MC13283
MC44002, MC44007
MC44011
MC44030, MC44035
MC44144
MC44145
MC44353, MC44354,
MC44355
MC44461
MC44462
MC44463
9-26
80/100 MHz Video Processor ............................................ 9-205
100 MHz Video Processor with OSD Interface .............................. 9-215
130 MHz Video Processor with OSD Interface .............................. 9-226
Chroma 4 Multistandard Video Processor .................................. 9-236
Bus Controlled Multistandard Video Processor ............................. 9-275
Multistandard Video Signal Processor with Integrated Delay Line ............. 9-324
Subcarrier Phase-Locked Loop .......................................... 9-326
Pixel Clock Generator/Sync Separator ..................................... 9-331
PLL Tuned UHF AudioNideo Modulator ICs for
PAL, SECAM and NTSC TV Systems ................................... 9-338
Picture-in-Picture (PIP) Controller ........................................ 9-341
Y-C Picture-in-Picture (PIP) Controller ................................... 9-354
Replay and Multiple Picture-in-Picture (PIP) Controller ...................... 9-360
MOTOROLA ANALOG IC DEVICE DATA
Video Circuits (continued)
Device
Function
Page
MC44817, MC44817B PLL Tuning Circuits with 3-Wire Bus ...................................... 9-367
MC44818
PLL Tuning Circuit with 12C Bus .......................................... 9-374
MC44824, MC44825
PLL Tuning Circuits with 12C Bus ......................................... 9-381
MC44826
PLL Tuning Circuit with 12C Bus .......................................... 9-388
PLL Tuning Circuit with 3-Wire Bus ....................................... 9-395
MC44827
MC44828
PLL Tuning Circuit with 12C Bus .......................................... 9-396
MC44829
PLL Tuning Circuit with 12C Bus .......................................... 9-397
PLL Tuning Circuit with 1.3 GHz Prescaler and D/A Converters for
MC44864
Automatic Tuner Alignment ............................................ 9-405
Remote Control Circuit
Device
Function
Page
MC3373*
Remote Control Amplifier/Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-72
RELATED APPLICATION NOTES
App Note
Title
Related Device
AN545A
Television IF Amplifiers ........................................ MC1350
AN829
Application of the MC1374 TV Modulator ......................... MC1374
AN921
Horizontal APC/AFC Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. MC1391
AN932
Application of the MC 1377 Color Encoder ....... . . . . . . . . . . . . . . . .. MC1377
AN1044
A Monolithic Composite Video Synchronizer ...................... MC1378
AN1548
Guidelines for Debugging the MC44011 Video Decoder ............ MC44011
II
NOTE: • Not recommended for new designs.
MOTOROLA ANALOG IC DEVICE DATA
9-27
®
MOTOROLA
CA3146
General Purpose
Transistor Array
One Differentially Connected Pair and
Three Isolated Transistor Arrays
GENERAL PURPOSE
TRANSISTOR ARRAY
The CA3146 is designed for general purpose, low power applications in
the dc through VHF range.
SEMICONDUCTOR
TECHNICAL DATA
• Guaranteed Base-Emitter Voltage Matching
• Operating Current Range Specified: 10 j.IA to 10 rnA
• Five General Purpose Transistors in One Package
DSUFFIX
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector-Emitter Voltage
VCEO
130
Vdc
Collector-Base Voltage
VCBO
20
Vdc
Collector-Substrate Voltage
VCIO
20
Vde
Emitter-Base Voltage
VEBO
5.0
Vde
Collector Current
IC
50
mAde
Operating Temperature Range
TA
-40 to +85
°C
Tstg
-65 to +150
°C
Storage Temperature Range
PLASTIC PACKAGE
CASE 751A
(SQ-14)
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
CA3146D
TA =- 40° to +85°C
SQ-14
PIN CONNECTIONS
Pin 13 is connected to substrate and must remain at the lowest circuit potential.
9-28
MOTOROLA ANALOG IC DEVICE DATA
CA3146
ELECTRICAL CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Collector-Base Breakdown Voltage
(lc = 10 !JAde)
V(BR)CBO
40
89
-
Vdc
Collector-Emitter Breakdown Voltage
(lc = 1.0 mAde)
V(BR)CEO
35
45
-
Vdc
Collector-Substrate Breakdown Voltage
(lCI= 10/olA)
V(BR)CIO
40
85
-
Vdc
Emitter-Base Breakdown Voltage
(IE = 10/olA)
V(BR)EBO
5.0
-
-
Vdc
ICBO
-
0.68
40
nAdc
171
188
-
0.7
-
Vdc
Characteristics
STATIC CHARACTERISTICS
Collector-Base Cutoff Current
(VCB = 10 Vdc, IE = 0)
-
DC Current Gain
(lc = 10 mAde, VCE = 5.0 Vdc)
(lC = 1.0 mAde, VCE = 5.0 Vdc)
hFE
Base-Emitter Voltage
(VCE = 5.0 Vdc, 'E = 1.0 mAde)
VBE
-
VCE(sat)
-
0.28
0.5
Vdc
',0
-
0.03
2.0
/olAdc
,V,O'
-
0.13
2.0
mVdc
Low Frequency Noise Figure
(VCE = 5.0 Vdc, IC = 100 /olAdc, RS = 1.0 kQ, f = 1.0 kHz)
NF
-
3.25
-
dB
Forward Current Transfer Ratio
(VCE = 5.0 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
hfe
-
201.5
-
-
Short Circuit Input Impedance
(VCE = 5.0 Vdc, IC = 1.0 mAde, f = 1.0 kHz)
hie
-
6.7
-
kQ
Open Circuit Output Impedance
(VCE = 5.0 Vdc, IC = 1.0 mAde, f = 1.0 kHz)
hoe
-
15.6
-
/olmho
Reverse Voltage Transfer Ratio
(VCE = 5.0 Vdc, IC = 1.0 mAdc, f = 1.0 kHz)
h re
-
3.5
-
Xl0- 4
Input Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAde, f = 1.0 kHz)
Vie
-
0.14+
jO.16
-
mmho
Forward Transfer Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAde, f = 1.0 kHz)
Vfe
-
34.6jO.63
-
mmho
Reverse Transfer Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAde, f = 1.0 kHz)
V re
-
62.0j59.4
-
/olmho
Output Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAde, f = 1.0 kHz)
Voe
-
0.16+
jO.14
-
mmho
tr
300
500
-
MHz
Emitter-Base Capacitance
(VEB = 5.0 Vdc, IE = 0 mAde)
CEB
-
1.17
-
pF
Collector-Base Capacitance
(VCB = 5.0 Vdc, 'E = 0 mAde)
CCB
-
0.68
-
pF
Collector-Substrate Capacitance
(VCS = 5.0 Vdc, IC = 0 mAde)
CCI
-
1.92
-
pF
Collector-Emitter Saturation Voltage
(IC = 10 mA, IB = 0.4 mAl
Magnitude of Input Offset Current 11,01 - ',02'
(VCE = 5.0 Vdc, ICI = IC2 = 1.0 mAde)
Magnitude of Input Offset Voltage IVBEI = VBE2'
(VCE = 5.0 Vdc, 'E = 1.0 mAdc)
DYNAMIC CHARACTERISTICS
Current-Gain - Bandwidth Product
(VCE = 5.0 Vdc, IC = 3.0 mAde)
MOTOROLA ANALOG IC DEVICE DATA
9-29
II
®
MOTOROLA
MC1350
Monolithic IF Amplifier
The MC1350 is an integrated circuit featuring wide range AGC for use as
an IF amplifier in radio and TV over an operating temperature range of 0° to
+75°C.
IF AMPLIFIER
• Power Gain: 50 dB Typ at 45 MHZ
50 dB Typ at 58 MHZ
SEMICONDUCTOR
TECHNICAL DATA
• AGC Range: 60 dB Min, DC to 45 MHz
• Nearly Constant Input & Output Admittance over the Entire AGC Range
• Y21 Constant ( -3.0 dB) to gO MHz
• Low Reverse Transfer Admittance: < < 1.0 j!mho Typ
.~
• 12 V Operation, Single-Polarity Power Supply
PSUFFIX
PLASTIC PACKAGE
CASE 626
1
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating
Symbol
Value
Unit
Power Supply Voltage
V+
+18
Vdc
Output Supply Voltage
VI. V8
+18
Vdc
AGC Supply Voltage
VAGC
V+
Vdc
Differential Input Voltage
Vin
5.0
Vdc
Power Dissipation (Package Limitation)
Plastic Package
Derate above 25°C
Po
625
5.0
mW
mW/oC
Operating Temperature Range
TA
Oto +75
°C
II
DSUFFIX
PLASTIC PACKAGE
CASE 751
(SCHl)
ORDERING INFORMATION
Device
MC1350P
Operating
Temperature Range
TA = 0° to +75°C
MC1350D
Package
Plastic DIP
SCHl
Figure 1. Typical MC1350 Video IF Amplifier and MC1330 Low-Level Video Detector Circuit
+18Vdc
-A-l
J
Auxiliary Video 18V [
Output
-J Iv.Nv
10V
--Primary Video
and Sound Output
3.3k
6
u.
::l.
~
o
3.9:·~[~
MC1330AP
MCI3S0
7
3.9k
+---f--e AFT Output
u.
::l.
g
ci
T1
-= AGC
qdfJ·p~,.
Tum~ums
'4
All windings #30 AWG tinned nylon acetate
wire tuned with Carbonyl E or J slugs.
9-30
3"
M-,rrrrl~
I 10 I
Turns
3"
-
16
L1 wound with #26 AWG tinned nylon
acetate wire tuned by distorting winding.
MOTOROLA ANALOG IC DEVICE DATA
MC1350
ELECTRICAL CHARACTERISTICS (V+ = +12 Vdc, TA = +25°C, unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
60
68
-
dB
-
48
50
58
62
-
20
8.0
AGC Range, 45 MHz (5.0 V to 7.0 V) (Figure 1)
Power Gain (Pin 5 grounded via a 5.1
f = 58 MHz, BW = 4.5 MHz
f = 45 MHz, BW = 4.5 MHz
f = 10.7 MHz, BW = 350 kHz
f = 455 kHz, BW = 20 kHz
kn resistor)
dB
Ap
See Figure 6(a)
See Figure 6(a), (b)
See Figure 7
46
Maximum Differential VoHage Swing
OdBAGC
-30 dB AGC
Vo
Output Stage Current (Pins 1 and 8)
-
-
Vpp
-
11 +18
-
5.6
-
mA
Total Supply Current (Pins 1, 2 and 8)
IS
-
14
17
mAdc
Power Dissipation
PD
-
168
204
mW
DESIGN PARAMETERS, Typical Values (V+ = +12 Vdc, TA = +25°C, unless otherwise noted.)
Frequency
Parameter
Single-Ended Input Admittance
Input Admittance Variations with AGC
(0 dB to 60 dB)
Differential Output Admittance
Symbol
455 kHz
10.7 MHz
45 MHz
58 MHz
Unit
911
b11
0.31
0.022
0.36
O.SO
0.39
2.30
0.5
2.75
mmho
!l.911
!l.bll
-
-
60
0
-
Ilmho
-
922
b22
4.0
3.0
4.4
110
30
390
60
510
Ilmho
-
-
4.0
90
-
Ilmho
«1.0
Ilmho
Output Admittance Variations with AGC
(0 dB to 60 dB)
!l.922
!l.b22
Reverse Transfer Admittance (Magnitude)
IY121
Forward Transfer Admittance
Magnitude
Angle (0 dB AGC)
Angle (-30 dB AGC)
IY21 i
< Y21
'\I
-160
30
-200
100
SO
r\
-'
922
30
8.0
iiJ7.0
I-
1.,...;'
~
:;;-
~
!j 6.0
§;
1/
"'- 0.4
'"
/
Sl
Figure ". Differential Output Voltage
L
admittance exhibits
0.8 - twice th se valu .)
-80 a::
Y21
o
100
70
m
~
~
100
o
-40
'I'
1300
Figure 10. Differential Output Admittance
_
~
LY21 (max gain) ...... ~
f, FREQUENCY (MHz)
1.0
LY21 (-30 dB gain)
~ 200
gll
20
/
V
I II
I
/
V++ =14V
V++ =12V
~ 2.0
w
!t
c
1.0
o
100
o
10
20
30
40
SO
GAIN REDUCTION (dB)
60
70
80
9-33
®
MOTOROLA
MC1374
TV Modulator Circuit
The MC1374 includes an FM audio modulator,. sound carrier oscillator, RF
oscillator, and RF dual input modulator. It is designed to generate a TV signal
from audio and video inputs. The MC1374's wide dynamic range and low
distortion audio make it particularly well suited for applications such as video
tape recorders, video disc players, TV games and subscription decoders.
TV MODULATOR CIRCUIT
SEMICONDUCTOR
TECHNICAL DATA
• Single Supply, 5.0 V to 12 V
• Channel 3 or 4 Operation
• Variable Gain RF Modulator
-
• Wide Dynamic Range
• Low Intermodulation Distortion
• Positive or Negative Sync
.
• Low Audio Distortion
• Few External Components
PSUFFIX
PLASTIC PACKAGE
CASE 646
ORDERING INFORMATION
Device
Operating
Temperature Range
Paclqlge
MC1374P
TA = 0° to +70°C
Plastic DIP
Figure 1. Simplified Application
v
+Vcc = 12V
C9
0.001
T-=
4
- - - - - - - - - - VPinl
~_~inll
3
T
7
.. t
C15
0.001
6
4
+
+
~I
f-----o Output
R9
560
Ul
MC1374
Rll
220
3
C4
50
2
6.ak
R12
' - - - - - - - . 0 Video In
18ak
14
,.
h - - - - - - - - - ' - + - - - - " l + 1-(---~O Audio In
R5
3.3k
R6
2.2k
'--------'
Shaded Parts Optional
R13
C6
30k
I~F
L1 - 4 Turns #22,1/4" Dia.
L2 - 40 Turns, #36, 3116" Dia.
MOTOROLA ANALOG IC DEVICE DATA
MC1374
MAXIMUM RATINGS (TA = 25'C, unless otherwise noted.)
Rating
Value
Unit
14
Vdc
Oto+70
'c
Supply Voltage
Operating Ambient Temperature Range
Storage Temperature Range
-65 to +150
'C
150
'c
1.25
10mW/'C
W
Junction Temperature
Power Dissipation Package
Derate above 25'C
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, TA = 25'C, fc = 67.25 MHz, Figure 4 circuit, unless otherwise noted.)
I
Characteristics
I
Min
I
Typ
I
Max
I
Unit
AM OSCILLATOR/MODULATOR
Operating Supply Voltage
5.0
12
12
V
Supply Current (Figure 1)
-
13
-
rnA
Video Input Dynamic Range (Sync Amplitude)
0.25
1.0
1.0
VPk
RF Output (Pin 9, R7 = 75 n, No Extemal Load)
-
170
-
mVpp
Carrier Suppression
36
40
-
dB
Linearity (75% to 12.5% Carrier, 15 kHz to 3.58 MHz)
-
-
2.0
%
5.0
7.0
10
%
2.0
Degrees
Differential Gain Distortion (IRE Test Signal)
-
1.5
920 kHz Beat (3.58 MHz @ 30%,4.5 MHz @ 25%)
-
-57
-
dB
Video Bandwidth (75 n Input Source)
30
-
-
MHz
Oscillator Frequency Range
-
105
-
MHz
Internal Resistance across Tank (Pin 6 to Pin 7)
Internal CapaCitance across Tank (Pin 6 to Pin 7)
-
1.8
4.0
-
kU
pF
Differential Phase Distortion (3.58 MHz IRE Test Signal)
-
ELECTRICAL CHARACTERISTICS (TA = 25'C, VCC = 12 Vdc, 4.5 MHz, Test circuit of Figure 11, unless otherwise noted.)
I
Characteristics
I
Min
I
Typ
I
Max
I
Unit
FM OSCILLATOR/MODULATOR
Frequency Range of Modulator
Frequency Shift versus Temperature (Pin 14 open)
Frequency Shift versus VCC (Pin 14 open)
Output Amplitude (Pin 3 not loaded)
Output Harmonics, Unmodulated
14
4.5
0.2
-
900
-
-
-40
MHz
kHzI'C
kHzIV
mVpp
dB
-
MHzIV
-
-
-
14
0.3
4.0
1.7 MHz
4.5 MHz
10.7 MHz
-
-
0.20
0.24
0.80
Audio Distortion (±25 kHz Deviation, Optimized Bias Pin 14)
Audio Distortion (±25 kHz Deviation, Pin 14 self biased)
Incidental AM (±25 kHz FM)
-
0.6
1.4
2.0
1.0
Audio Input Resistance (Pin 14 to ground)
Audio Input Capacitance (Pin 14 to ground)
-
6.0
5.0
-
Stray Tuning Capacitance (Pin 3 to ground)
Effective Oscillator Source Impedance (Pin 3 to load)
-
5.0
2.0
-
Modulation Sensitivity
MOTOROLA ANALOG IC DEVICE DATA
-
-
%
-
-
kn
pF
pF
kn
9-35
II
MC1374
Figure 2. TV Modulator
Bias
Section
RIO
FM Oscillator/Modulator
Sound Carrier
Audio In
OSC B+
4
14 ~
Rl1
R12
R13
325
02~
-r-",,022
~~1r~tl ~~
c~
T
CO~~
R14
03
~4
R15
~Q26
o23
V
ht.
ht.
027
11- -t
Dl
Rl
R2
R3
50
Gnd
R4
r-""
08
r.,.
~
R5
1
Sound Carrier
In
016
h.
r-""
017
h.
represents one diode drop, or about 0.75 V. The oscillator
Pins6 and7 must be biased to alevelofVcc _I\> - 211 RL(or
lower) and the input Pins 1 and 11 must always be at least 21\>
below that. It is permissible to operate down to 1.6 V,
saturating the current sources, but whenever possible, the
minimum should be 31\> above ground.
The oscillator will operate dependably up to about
105 MHz with a broad range of tank circuit component
values. It is desirable to use a small L and a large C to
minimize the dependence on IC internal capacitance. An
operating 0 between 10 and 20 is recommended. The values
of R1, R2 and R3 are chosen to produce the desired 0 and to
set the Pin 6 and 7 dc voltage as discussed above.
Unbalanced operation, i.e., Pin 6 or 7 bypassed to ground, is
not recommended. Although the oscillator will still run, and
the modulator will produce a useable signal, this mode
causes substantial base-band video feedthrough.
Bandswitching, as Figure 1 shows, can still be accomplished
economically without using the unbalanced method.
The oscillator frequency with respect to temperature in the
test circuit shows less than ±20 kHz total shift from 0° to 50°C
as shown in Figure 7. At higher temperatures the slope
approaches 2.0 kHzl°C. Improvement in this region would
require a temperature compensating tuning capacitor of the
N75family.
Crystal control is feasible using the circuit shown in Figure
21. The crystal is a 3rd overtone series type, used in series
resonance. The L1, C2 resonance is adjusted well below the
crystal frequency and is sufficiently tolerant to permit fixed
values. A frequency shift versus temperature of less than
1.0 Hzl°C can be expected from this approach. The resistors
Ra and Rb are to suppress parasitic resonances.
Coupling of output RF to wiring and components on Pins 1
and 11 can cause as much as 300 kHz shift in carrier (at
67 MHz) over the video input range. A careful layout can
keep this shift below 10kHz. Oscillator may also be
inadvertently coupled to the RF output, with the undesired
effect of preventing a good null when V 11 =V1. Reasonable
care will yield carrier rejection ratios of 36 to 40 dB below sync
tip level carrier.
MOTOROLA ANALOG IC DEVICE DATA
In television, one of the most serious concerns is the
prevention of the intermodulation of color (3.58 MHz) and
sound (4.5 MHz) frequencies, which causes a 920 kHz signal
to appear in the spectrum. Very little (3rd order) nonlinearity is
needed to cause this problem. The results in Figure 6 are
unsatisfactory, and demonstrate that too much of the
available dynamic range of the MC1374 has been used.
Figures 8 and 10 show that by either reducing standard
signal level, or reducing gain, acceptable results may be
obtained.
At VHF frequencies, small imbalances within the device
introduce substantial amounts of 2nd harmonic in the RF
output. At 67 MHz, the 2nd harmonic is only 6 to 8 dB below
the maximum fundamental. For this reason, a double pi low
pass filter is shown in the test circuit of Figure 3 and works
well for Channel 3 and 4 lab work. For a fully commercial
application, a vestigial sideband filter will be required. The
general form and approximate values are shown in Figure 19.
It must be exactly aligned to the particular channel.
Figure 3. AM Modulator Transfer Function
II
Differential Input, Vll-Vl (V)
Figure 4. AM Test Circuit
R2
470
L1
Rl
470
7
Vl
Vee
RL
75
lO!LF
o-j~
RF
11
Video
Input
22
1.0k
Vll
I
9-37
MC1374
Figure 5. The Operating Window
Figure 6. 920 kHz Beat
o
Inilial Video = 1.0 Vdc
-10 r-Chroma (3.58 MHz) = 300 mVpp
Sound (4.5 MHz) a) = 250 mVpp
w&
-20 rb) = 500 mVpp
o
Gain Resistor R = 1.0 kO
w -30
CD
E
-'
0
!ilE => -40
?1.2
!z
-
4.9
4.8
fil
a:
a:
4.5
f2
~
:s
4.4
13
en
4.3
j
4.2
A
~
1.0
~
N'
4.53
~
4.52
::>
w
0
a:
u.
.,.:
"
L
Pin 14Vt02!6
~
4.50
4.49
6.0
4.47
7.0
N'
~
r-
TA=25°e
(10.7 MHz)
>- 11.2
'-'
z
a:
u.
a: 10.6
0
3
-'
10.4
0
10.0
IJ
,-
8
9.8
9.6
~~
o
2.0
3.0
4.0
5.0
De INPUT VOLTAGE. PIN 14 (V)
o
.-
- .. --
1
25
50
75
TA. AMBIENT TEMPERATURE (Oe)
Pin 14 to 2·.6 V Source
4.49
¥
~
4.48
4.47
~
z
w
4.48
@
4.45
a:
u.
4.44
4.43
6.0
r--
100
Figure 18. FM System Frequency versus Vcc
i\ .I, ~
~ If'
1.0
180· k130 k Divider
Pin 14 0 pen
4.50
12V
9.0VVCC
5.0V
A
13 10.2
en
.Jl
,
~
w
::> 11.0
0
w 10.8
b::::::;; ;;
/'
~.
./
---
4.51
Figure 17. Modulator Transfer Function
11.6
:t: 11.4
",......
I
4.48
2.0
3.0
4.0
5.0
De INPUT VOLTAGE. PIN 14 (V)
100
75
4.54 f- Vee=12V
~
zw
.4~
o
4.55
:t:
J
0
4.1
I
Vee = 5.0 V. 9.0 V
,.J
-'
II
~
50
DEVIATION (kHz)
-- -
Figure 16. FM System Frequency
versus Temperature
1 1 1
Vee = 12V_
TA=25°e
(4.5 MHz)
4.7
4.6
u.
-
./
/'
~
25
Figure 15. Modulator Transfer Function
N'
:t:
~
/'
V
/'O~timum
Bias (2.6-2.7 V)
'1.
1
1 __
--
1.0
o
Self B:as (2'9-f'0 V)""
2.0
is
1.4
1.3
,r
7.0
~
-
~
Pin140 en
./
."
V
~
... V
. /.....Pin14-180 k130 k Divider
V
4.42
4.0
./
TA = 25°e
5.0
6.0
7.0
8.0
9.0
10
Vee. SUPPLY VOLTAGE (Vdc)
11
12
MOTOROLA ANALOG IC DEVICE DATA
MC1374
Figure 19. A Channel 4 Vestigial Sideband Filter
VCC
Both transformer windings
4H23AWG
close wound on 1/4" ID
on common axis, 3/8" spacing.
8.2pF
I
I
I
I
I
I
I
I
-.l
ij
240
3pF
2.~
Z
~
§-40
~ -50
~~O~~t
L..J.'
i
33pF
8T#23AWG
~
close wound on 1/8" ID,
knife luned to trap Channel 3
61.25 MHz.
o
-10
-20
Q -30
'"~
33pF
~
ig
~-60
-70 +-_-.---'--,-.-J'-,.-_ _
61
65
69
73
f, FREQUENCY (MHz)
loon
~
Figure 20. Audio Pre-Emphasis Circuit
iD 25
2ltRC
::2I::J
c..
z
C=0.0012j.1F
CC=O.~
'Flat"
Audio
Input
0=1
r = 56kO
;:::
15
c..
10
w
5
~
0
::J
--
Audio
Input
':i
a
R
6.0kn
20
;;::
w
5 >Gnd
a: -5
21
210
2100
21k
f, FREQUENCY (MHz)
PrHlmphasis = 75 j.1S = rC = 2 It (2: 00 Hz)
II
Figure 21. Crystal Controlled RF Oscillator
for Channel 3, 61.25 MHz
470
Cl
0. 001
1
R2
0.15j.1H
Rb
6
18
7
MC1374
I
I
NOTE: See Application Note AN829 for further information.
MOTOROLA ANALOG IC DEVICE DATA
9-41
®
MOTOROLA
MC1377
Color Television RGB to
PAL/NTSC Encoder
COLOR TELEVISION
RGB to PAUNTSC ENCODER
The MC1377 will generate a composite video from baseband red, green,
blue, and sync inputs. On board features include: a color subcarrier
oscillator; voltage controlled 90° phase shifter; two double sideband
suppressed carrier (DSBSC) chroma modulators; and RGB input matrices
with blanking level clamps. Such features permit system design with few
external components and accordingly, system performance comparable to
studio eqUipment with external components common in receiver systems.
SEMICONDUCTOR
TECHNICAL DATA
• Self-contained or Externally Driven Reference Oscillator
• Chroma Axes, Nominally 90° (±5°), are Optionally Trimable
PSUFFIX
PLASTIC PACKAGE
CASE 738
• PAUNTSC Compatible
• Internal 8.2 V Regulator
20~
DWSUFFIX
PLASTIC PACKAGE
CASE 7510
(SD-20L)
ORDERING INFORMATION
Operating
Temperature Range
Device
MC13770W
TA = 0° to +70°C
MC1377P
Package
SD-20L
PlaslicOIP
Figure 1. Representative Block Diagram
Quad
19Decoup
I()
OSCout1 ~
OSCin1
...
t
Oscillator
Buffer
~-
~
Voltage
Controlled
goo
PAUNTSC
Control
r---
1
~
~
u 1
Trise
Burst
Pulse
Driver
1
Latching
Ramp
Generator
1
! I
...
X·
r-A
Airl
~ , r
PAL
Switch
0/180°
8.2V
Regulator
f
900 t
H/2
Gnd
I
VB
16
()
'----,
I
2
NTSC/PAL ~~
Select
VCC
()l14
r-
Dual
Comparator
I
+
u 2
Composite
Sync Input
OOt
I
~~~
r--pl oChroma In
I
I B-Y
Color Difference and
Luminance Matrix
, ,
,
u 3
v
I
u 4
R
I
G
B
"'---- v - - - "
~-Y
~
B-Y
Clamp
I
11
R-Y
Clamp
I
12
Output Amp/
Clamp
I
9 Composite
Video Output
Video Clamp
7
,
H
t
5
6
-Yout
Chroma Out
T
t
I R-Y
3
Amp
I
I
B-YClamp
R-YClamp
v
8
-Yin
Inputs
MOTOROLA ANALOG IC DEVICE DATA
MC1377
MAXIMUM OPERATING CONDITIONS
Symbol
Value
Unit
Supply Voltage
Rating
VCC
15
Vdc
Storage Temperature
Tstg
-65 to +150
°C
Power Dissipation Package
Derate above 25'C
Po
1.25
10
W
mW/"C
Operating Temperature
TA
Oto+70
'c
RECOMMENDED OPERATING CONDITIONS
Min
Typ
Max
Unit
Supply Voltage
Characteristics
10
12
14
Vdc
IB Current (Pin 16)
0
-
-10
mA
1.7
-
Sync, Blanking Level (DC level between pulses, see Figure ge)
Sync Tip Level (see Figure ge)
Sync Pulse Width (see Figure ge)
2.5
-
B.2
0.9
5.2
-
1.0
-
--{).s
0
Vdc
IJ.S
R, G, B Input (Amplitude)
R, G, B Peak Levels for DC Coupled Inputs, with Respect to Ground
2.2
-
4.4
Vpp
V
Chrominance Bandwidth (Non--<:omb Filtered Applications), (6 dB)
0.5
1.5
2.0
MHz
Ext. Subscarrier Input (to Pin 17) if On--Chip Oscillator is not used.
0.5
0.7
1.0
Vpp
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, TA = 25°C, circuit of Figure 7, unless otherwise noted.)
Characteristics
Typ
SUPPLY CURRENT
Supply Current into VCC, No Load, on Pin 9.
Circuit Figure 7
VCC=10V
VCC=11 V
VCC=12V
VCC=13V
VCC=14V
14
ICC
-
20
-
33
34
35
36
37
-
-
mA
40
-
-
VOLTAGE REGULATOR
VB Voltage (IB =-10 mA, VCC = 12 V, Figure 7)
Load Regulation (0 < IB'; 10 mA, VCC = 12 V)
Line Regulation (IB = 0 mA, 10 V < VCC < 14 V)
16
VB
Regload
Regline
7.7
-20
B.7
+30
-
B.2
120
4.5
-
Vdc
mV
mVN
OSCILLATOR AND MODULATION
Oscillator Amplitude with 3.5B MHzJ4.43 MHz crystal
17
Osc
-
0.6
-
Vpp
Subcarrier Input: Resistance at 3.5B MHz
4.43 MHz
17
Rosc
-
-
5.0
4.0
-
kQ
-
Cosc
-
2.0
-
pF
19
19
0m
L\0m
V19
-
±5
0.25
6.4
-
Deg
Deg/I1A
Vdc
10
Yin
-
-
4.0
0.7
-
-
Vdc
Vpp
Rin
Cin
-
10
2.0
-
kQ
pF
Vout
B.9
-
10
1.0
10.9
-
Vdc
Vpp
Rout
-
50
-
n
BWLuma
-
B.O
-
MHz
Capacitance
Modulation Angle (R-V) to (B-V)
Angle Adjustment (R-V)
DC Bias VoHage
-
-
CHROMINANCE AND LUMINANCE
Chroma Input DC Level
Chroma Input Level for 100% Saturation
Chroma Input: Resistance
CapaCitance
Chroma DC Output Level
Chroma Output Level at 100% Saturation
13
Chroma Output Resistance
Luminance Bandwidth (-3.0 dB), Less Delay Line
MOTOROLA ANALOG IC DEVICE DATA
9
II
MC1377
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, TA = 25°C, circuit of Figure 7, unless otherwise noted.)
Characteristics
Typ
VIDEO INPUT
R, G, B Input DC Levels
3,4,5
RGB
2.8
3.3
3.B
Vdc
-
1.0
-
Vpp
RRGB
CRGB
8.0
10
2.0
17
-
kg
pF
2
Sync
-
10
9
CVout
-
-
-
-
0.6
1.4
1.7
0.6
Rvideo
-
50
-
g
Vlk
-
20
-
mVpp
R, G, B Input for 100% Color Saturation
R, G, B Input: Resistance
Capacitance
Sync Input Resistance (1.7 V < Input < 8.2)
-
kQ
COMPOSITE VIDEO OUTPUT
}{
Composite Output,
100% Saturation
(see Figure Bd)
Sync
Luminance
Chroma
Burst
Output Impedance (Note 1)
Subcarrier Leakage in Output (Note 2)
Vpp
-
-
NOTES: 1. OUlput Impedance can be reduced to less than 10 n by using a 150 n output load from Pin 9to ground. Power supply current will
increase to about 60 rnA.
2. Subcarrier leakage can be reduced to less than 10 mV with optional ci!Cunry (see Figure 12).
PIN FUNCTION DESCRIPTIONS
Symbol
Pin
Description
tr
1
External components at this pin set the rise time of the internal ramp function generator (see Figure 10).
Sync
2
Composite sync input. Presents 10 kQ resistance to input.
R
3
Red signal input. Presents 10 kQ impedance to input. 1.0 Vpp required for 100% saturation.
G
4
Green signal input. Presents 10 kQ impedance to input. 1.0 Vpp required for 100"", saturation.
B
5
Blue signal Input. Presents 10 kQ impedance to input. 1.0 Vpp required for 100% saturation.
-Yout
6
Luma (-Y) output. Allows external setting of luma delay time.
Vclamp
7
Video Clamp pin. Typical connection is a 0.01 IlF capacitor to ground.
-Yin
8
Luma (-Y) input. Presents 10 kQ input impedance.
CVout
9
Composite Video output. 50 0 output impedance.
Chromaln
10
Chroma input. Presents 10 kQ input impedance.
B-Yclamp
11
B-Y clamp. Clamps B-Y during blanking with a 0.1 IlF capacitor to ground.
Also used with R-Y clamp to null residual color subcarrier in output.
R-Yclamp
12
R-Y clamp. Clamps R-Y during blanking with a 0.1 IlF capacitor to ground.
Also used with B-Y clamp to null residual color subcarrier in output.
ChromaOut
13
Chroma output. 50 g output impedance.
VCC
14
Power supply pin for the IC; +12, ± 2.0 V, required at 35 rnA (typical).
Gnd
15
Ground pin.
VB
16
B.2 V reference from an internal regulator capable of delivering lOrnA to external circuitry.
Oscin
17
Oscillator input. A transistor base presents 5.0 kQ to an external subcarrier input, or is available for
constructing a Colpitts oscillator (see Figure 4).
OSCout
18
Oscillator output. The emitter of the transistor, with base access at Pin 17, is accessible for completing the
Colpitts oscillator. See Figure 4.
0m
19
Quad decoupler. With external circuitry, R-Y to B-Y relative angle errors can be corrected. Typically,
requires a 0.01 IlF capacitor to ground.
NTSC/PAL
, Select
20
NTSC/PAL switch. When grounded, the MC1377 is in the NTSC mode; if unconnected, in the PAL mode.
9-44'
MOTOROLA ANALOG IC DEVICE DATA
MC1377
FUNCTIONAL DESCRIPTION
Power Supply and VB (8.2 V Regulator)
Figure 2. Power Supply and VB
The MC1377 pin for power supply connection is Pin 14.
From the supply voltage applied to this pin, the IC biases
internal output stages and is used to power the 8.2 V internal
regulator (VB at Pin 1S) which biases the majority of internal
circuitry. The regulator will provide a nominal 8.2 V and is
capable of 10 mA before degradation of performance. An
equivalent circuit of the supply and regulator is shown in
Figure 2.
R, G, B Inputs
The RGB inputs are internally biased to 3.3 V and provide
10 kO of input impedance. Figure 3 shows representative
input circuitry at Pins 3, 4, and 5.
The input coupling capaCitors of 15 !iF are used to prevent
tilt during the 50/S0 Hz vertical period. However, if it is desired
to avoid the use of the capaCitors, then inputs to Pins 3, 4,
and 5 can be de coupled provided that the signal levels are
always between 2.2 V and 4.4 V.
After input, the separate RGB information is introduced to
the matrix Circuitry which outputs the R-Y, B-Y, and -Y
signals. The -Y information is routed out at Pin S to an
external delay line (typically 400 ns).
9
Figure 3. RGB Input Circuitry
R-V
-v
B-V
DSBSC Modulators and 3.58 MHz Oscillator
27k
18k
3
T 15J.lF
4
6
T 15J.lF
-v
G
R
Figure 4. Chroma Section
-
OscHlator
17
Quad
Oecoup
19
Burst
Rag -
B-V
MOTOROLA ANALOG IC DEVICE DATA
The R-Y and B-Y outputs (see (B-Y)/(R-Y) Axes versus
I/Q Axes, Figure 22) from the matrix circuitry are amplitude
modulated onto the 3.58/4.43 MHz subcarrier. These signals
are added and color burst is included to produce compOSite
chroma available at Pin 13. These functions plus others,
depending on whether NTSC or PAL operation is chosen, are
performed in the chroma section. Figure 4 shows a block
diagram of the chroma section.
The MC1377 has two double balanced mixers, and
regardless of which mode is chosen (NTSC or PAL), the
mixers always perform the same operation. The B-Y mixer
modulates the color subcarrier directly, the R-Y mixer
receives a 90° phase shifted color subcarrier before being
modulated by the R-Y baseband information. Additional
operations are then performed on these two signals to make
them NTSC or PAL compatible.
In the NTSC mode, the NTSC/PAL control circuitry allows
an inverted burst of 3.58 MHz to be added only to the B-Y
signal. A gating pulse or "burst flag" from the timing section
permits color burst to be added to the B-Y signal. This color
burst is 1800 from the B-Y signal and 90° away from the R-Y
signal (see Figure 22) and permits decoding of the color
information. These Signals are then added and amplified
before being output, at Pin 13, to be bandpassed and then
reintroduced to the IC at Pin 10.
In the PAL mode, NTSC/PAL control circuitry allows an
inverted 4.43 MHz burst to be added to both R-Y and B-Y
equally to produce the characteristic PAL 225°/135 burst
phase. Also, the R-Y information is switched alternately from
1800 to 0 0 of its original position and added to the B-Y
information to be amplified and output.
R-V
9-45
II
MC1377
Timing Circuitry
Figure 5. Timing Circuitry
The composite sync input at Pin 2 performs three
important functions: it provides the timing (but not the
amplitude) for the sync in the final output; it drives the black
level clamps in the modulators and output amplifier; and it
triggers the ramp generator at Pin 1, which produces burst
envelope and PAL switching. A representative block diagram
of the timing circuitry is shown in Figure 5.
In order to produce a color burst, a burst envelope must be
generated which "gates" a color subcarrier into the R-V and
8-V modulators. This is done with the ramp generator at
Pin 1.
The ramp generator at Pin 1 is an R-C type in which the
pin is held low until the arrival of the leading edge of sync. The
rising ramp function, with time constant R-G, passes through
two level sensors - the first one starts the gating pulse and
the second stops it (see Figure 10). Since the "early" part of
the exponential is used, the timing provided is relatively
accurate from chip-to-chip and assembly-to-assembly.
Fixed components are usually adequate. The ramp
continues to rise for more than half of the line interval, thereby
inhibiting burst generation on "half- interval" pulses on vertical
front and back pdrches. The ramp method will produce burst
on the vertical front and back "porches" at full line intervals.
PAU
NTSC
Figure 6. R-V, B-V and Output Amplifier Clamps
, Chroma
10
B-Y
R-V, B-V Clamps and Output Clamp/Amplifier
R-Y
The sync Signal, shown in the block diagram of Figure 6,
drives the R-V and B-V clamps which clamp the R-V and
B-V signals to reference black during the blanking periods.
The output amplifier/clamp provides this same function plus
combines and a,mplifies the chroma and luma components
for composite video output.
a
11
O.~
12
O.~
1-_-\:>9.-...,....Composite
7
Video
Sync
~-''-~~~~O.~
Application Circuit
Figure 7 illustrates the block diagram of the MC1377 and
the external circuitry required for typical operation.
Figure 7. Block Diagram and Application Circuit
~ O.OIVce o-~:-----;~------------,
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MOTOROLA ANALOG Ie DEVICE DATA
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9-47
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MC1377
Figure 8. Internal Schematic
Chroma Out
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MOTOROLA ANALOG IC DEVICE DATA
MC1377
APPLICATION INFORMATION
R, G, B Input Levels
Figure 8. Signal Voltages
(Circuit Values of Figure 7)
(a)
4.4V
Limits
tor DC
Coupled
Inputs
1.0Vpp
100%
Green
Input
(Pin 4)
2.2V
(b)
1.0Vpp
100%
Red
Input
(Pin 3)
1.0Vpp
100%
Blue
Input
(PinS)
(c)
(d)
5.0
Composite
Output
(Pin 9)
4.0
3.0
S.2Max
(e)
1.7 Min
0.9 Max
0
-0.5 Min
(~
Sync
Input
(Pin 2)
II
II
LJ
11LJ
10.5
10.0
Chroma
Output
(Pin 13)
9.5
(9)
4.35
4.0
Chroma
Input
(Pin 10)
3.65
(h)
5.2
Luminance
Output
(Pin 6)
4.3
(i)
M~
2.1
MOTOROLA ANALOG IC DEVICE DATA
Luminance
Input
(PinS)
The signal levels into Pins 3, 4, 5 should be 1.0 Vpp for fully
saturated, standard composite video output levels as shown
in Figure 9(d). The inputs require 1.0 Vpp since the internally
generated sync pulse and color burst are at fixed and
predetermined amplitudes.
Further, it is essential that the portion of each input which
occurs during the sync interval represent black for that input
since that level will be clamped to reference black in the color
modulators and output stage. This implies that a refinement,
such as a difference between black and blanking levels, must
be incorporated in the RGB input signals.
If Y, R-Y, 8-Y and burst flag components are available and
the MC1377 is operating in NTSC, inputs may be as follows:
the Y component can be coupled through a 15 pF capacitor
to Pins 3, 4 and 5 tied together; the (-[R-Y]) component can
be coupled to Pin 12 through a 0.1 J.lF capacitor, and the
(-[8-V]) and burst flag components can be coupled to Pin 11
in a similar manner.
Sync Input
As shown in Figure 9(e), the sync input amplitude can be
varied over a wide latitude, but will require bias pull-up from
most sync sources. The important requirements are:
1) The voltage level between sync pulses must be between
1.7 V and 8.2 V, see Figure 9(e).
2) The voltage level for the sync tips must be between
+0.9 V and - 0.5 V, to prevent substrate leakage in the IC,
see Figure 9(e).
3) The width of the sync pulse should be no longer than
5.2 J.IS and no shorter than 2.5 Ils.
For PAL operation, correctly serrated vertical sync is
necessary to properly trigger the PAL divider. In NTSC mode,
simplified "block" vertical sync can be used but the loss of
proper horizontal timing may cause '1op hook" or "flag
waving" in some monitors. An interesting note is that
composite video can be used directly as a sync Signal,
provided that it meets the sync input criteria.
Latching Ramp (Burst Flag) Generator
The recommended application is to connect a close
tolerance (5%) O.OOIIlF capacitor from Pin 1 to ground and a
resistor of 51 kQ or 56 kQ from Pin 1 to VB (Pin 16). This will
produce a burst pulse of 2.5 Ils to 3.5 Ils in duration, as
shown in Figure 10. As the ramp on Pin 1 rises toward the
charging voltage of 8.2 V, it passes first through a burst "start
threshold" at 1.0 V, then a "stop threshold" at 1.3 V, and finally
a ramp reset threshold at 5.0 V. If the resistor is reduced to
43 kQ, the ramp will rise more quickly, producing a narrower
and earlier burst pulse (starting approx. 0.4 J.ls after sync and
about 0.6 J.ls wide). The burst will be wider and later if the
resistor is raised to 62 kQ, but more importantly, the 5.0 V
reset point may not be reached in one full line interval,
resulting in loss of alternate burst pulses.
As mentioned earlier, the ramp method does produce
burst at full line intervals on the "vertical porches." If this is not
desired, and the MC1377 is operating in the NTSC mode,
burst flag may be applied to Pin 1 provided that the tip of the
9-49
MC1377
pulse is between 1.0 Vdc and 1.3 Vdc. In PAL mode· this
method is not suitable, since the ramp isn't available to drive
the PAL flip-flop. Another means of inhibiting the burst pulse
is to set Pin 1 either above 1.3 Vdc or below 1.0 Vdc for the
duration that burst is not desired.
. Also, it is possible to do both; i.e., let the oscillator ''free run"
on its own crystal and override with an external source. An
extra coupling capacitor of 50 pF from the external source to
Pin 17 was adequate with the experimentation attempted.
Voltage Controlled 90°
Color Reference Oscillator/Buffer
The oscillator drives the (B-V) modulator and a voltage
controlled phase shifter which produces an oscillator phase
As stated earlier in the general description, there is an
on-board common collector Colpitts color reference
of 90° ±·5° at the (R-V) modulator. In most situations, the
oscillator with the transistor base at Pin 17 and the emitter at
result of an error of 5° is very subtle to all but the most expert
Pin 18. When used with a common low-cost TV crystal and
eye. However, if it is necessary to adjust the angle to better
capacitive divider, about 0.6 Vpp will be developed at Pin 17.
accuracy, the circuit shown in Figure 11 can be used.
The frequency adjustment can be done with a series 30 pF
Pulling Pin 19 up will increase the (R-V) to (B-V) angle by
trimmer capacitor over a total range of about 1.0 kHz.
about 0.25°jlJA. Pulling Pin 19 down reduces the angle by the
Oscillator frequency should be adjusted for each unit,
same sensitivity. The nominal Pin 19 voltage is about 6.3 V,
keeping in mind that most monitors and receivers can pull in
so even though it is unregulated, the 12 V supply is best for
1200 Hz.
good control. For effective adjustment, the simplest approach
If an external color reference is to be used eXClusively, it
is to apply RGB color bar inputs and use a vectorscope. A
must be continuous. The components on Pins 17 and 18 can
simple bar generator giving R, G, and B outputs is shown in
be removed·, and the external source capacitively coupled
Figure 26.
into Pin 17. The input at Pin 17 should be a sine wave with
amplitude between 0.5 Vpp and 1.0 Vpp.
Figure 9. RamplBurst Gate Generator
·5.0
1.3
1.0
~u~_S!.0~
___ ,
Burst Start,
O~--~~~,--------------------~~====~
~II-~
U: : - - - L
(Pin 2)
5.58.5
Residual Feedthrough Components
As shown in Figure 9(d), the composite output at Pin 9
for fully saturated color bars is about 2.6 Vpp, output with full
chroma on the largest bars (cyan and red) being 1.7 Vpp.
The typical device, due to imperfections in gain, matrixing,
and modulator balance, will exhibit about 20 mVpp·residual
color subcarrier in both white and black. Both rElsiduals can
be reduced to less than 10 mVpp for the more· exacting
applications.
The subcarrier feedthrough in black is due primarily to
imbalance in the modulators and can be nulled by sinking or
sourcing small currents into clamp Pins 11 and 12 as shown
in Figure 12. The nominal voltage on these pins is about
4.0 Vdc, so the 8.2 V regulator is capable of supplying a pull
up source. Pulling Pin 11 down is in the 0° direction, pulling it
up is towards 180°. i='ulling Pin 12 down is in the 90° direction,
pulling it up is towards 270°. Any direction of correction may
be required from part to part.
White carrier imbalance at the output can only be
corrected by juggling the relative levels of R, G, and B inputs
9-50
Time(lJ.S)
50
63.5
for perfect balance. Standard devices are tested to be within
5% of balance at full saturation. Black balance should be
adjusted first, because it affects all levels of gray scale
equally. There is also usually SOme residual baseband video
at the chroma output (Pin 13), which is most easily observed
by disabling the color oscillator. Typical devices show 0.4 Vpp
of residual luminance for saturated color bar inputs. This is
not a major problem since Pin 13 is always coupled to Pin 10
through a bandpass or a high pass filter, but it serves as a
warning to pay proper attention to the coupling network.
Figure 10. Adjusting Modulator Angle
12Vdc
19
220k
P---_~Wlr---::
10k
MOTOROLA ANALOG IC DEV!CE DATA
MC1377
Figure 11. Nulling Residual Color in Black
VB
12
470k
11
p-......J\I\,.......-~10k
470k
Figure 14(a) shows the output of the MC1377 with low
resolution RGB inputs. If no bandwidth reduction is employed
then a monitor or receiver with frequency response shown in
Figure 14(b), which is fairly typical of non.;:omb filtered
monitors and receivers, will detect an incorrect luma
sideband at X'. This will result in cross-talk in the form of
chroma information in the luma channel. To avoid this
situation, a simpler bandpass circuit as shown in Figure
15(a), can be used.
Figure 13. MC13n Output with
Low Resolution RGB Inputs
X
X
X
X
Figure 12. Delay of Chroma Information
Lum~
II
I
I
~~
3.0 3.584.0
1.0
5.0
(a) Encoder Output with Low Resolution Inputs
and No Bandpass Transformer
The Chroma Coupling Circuits
With the exception of S-VHS equipped monitors and
receivers, it is generally true that most monitors and receivers
have color IF 6.0 dB bandwidths limited to approximately
±O.5 MHz. It is therefore recommended that the encoder
circuit should also limit the chroma bandwidth to
approximately ±0.5 MHz through insertion of a bandpass
circuit between Pin 13 and Pin 10. However, if S-VHS
operation is desired, a coupling circuit which outputs the
composite chroma directly for connection to a S-VHS
terminal is given in the S-VHS application (see Figure 19).
For proper color level in the video output, a ±O.5 MHz
bandwidth and a midband insertion loss of 3.0 dB is desired.
The bandpass circuit shown in Figure 7, using the TaKa
fixed tuned transformer, couples Pin 10 to Pin 13 and gives
this result. However, this circuit introduces about 350 ns of
delay to the chroma information (see Figure 13). This must be
accounted for in the luminance path.
A 350 ns delay results in a viSible displacement of the color
and black and white information on the final display. The
solution is to place a delay line in the luminance path from
Pins 6 to 8, to realign the two components. A normal TV
receiver delay line can be used. These delay lines are usually
of 1.0 kQ to 1.5 kQ characteristic impedance, and the
resistors at Pins 6 and 8 should be selected accordingly. A
very compact, lumped constant delay line is available from
TDK (see Figure 25 for specifications). Some types of delay
lines have very low impedances (approx. 100 n) and should
not be used, due to drive and power dissipation
requirements.
In the event of very low resolution RGB, the transformer
and the delay line may be omitted from the circuit. Very low
resolution for the MC1377 can be considered RGB
information of less than 1.5 MHz. However, in this situation, a
bandwidth reduction scheme is still recommended due to the
response of most receivers.
MOTOROLA ANALOG IC DEVICE DATA
1.0
2.0
3.0 3.58 4.0
5.0
(b) Standard Receiver Response
A final option is shown in Figure 15(b). This circuit provides
very little bandwidth reduction, but enough to remove the
chroma to luma feedthrough, with essentially no delay. There
is, however, about a 9 dB insertion loss from this network.
It will be left to the designer to decide which, if any,
compromises are acceptable. Color bars viewed on a good
monitor can be used to judge acceptability of step
luminance/chrominance alignment and step edge transients,
but signals containing the finest detail to be encountered in
the system must also be examined before settling on a
compromise.
The Output Stage
The output amplifier normally produces about 2.0 Vpp and
is intended to be loaded with 150 n as shown in Figure 16.
This provides about 1.0 Vpp into 75 n, an industry standard
level (R8-343). In some cases, the input to the monitor may
be through a large coupling capacitor. If so, it is necessary to
connect a 150 n resistor from Pin 9 to ground to provide a low
impedance path to discharge the capacitor. The nominal
average voltage at Pin 9 is over 4.0 V. The 150 Q dc load
causes the current supply to rise another 30 mA (to
approximately 60 mA total into Pin 14). Under this (normal)
condition the total device dissipation is about 600 mW. The
calculated worst case die temperature rise is 60°C, but the
typical device in a test socket is only slightly warm to the
touch at room temperature. The solid copper 2Q-pin lead
frame in a printed circuit board will be even more
effectively cooled.
9-51
MC1377
Figure 14. Optional Chroma Coupling Circuits
0.001
1.0k
0.001
~I~--~~--~--~--~;r--o
13
10
22!1H
with an effective source impedance of less than 1.0 n. This
regulator is convenient for a tracking dc reference for dc
coupling the output to an RF modulator. Typical tum-on drift
for the regulator is approximately -30 mV over 1 to 2 minutes
in otherwise stable ambient conditions.
39pF
Figure 15. Output Termination
a) Insertion Loss: 3.0 dB
Bandwidth: ± 1.0 MHz
Delay: ~ 100 ns
56pF
1.0k
0.001
~I~----~----'---~--~~
__ J
~~~
27pF
4.7k
I
I
I
b) Insertion Loss: 9.0 dB
Bandwidth: ± 2.0 MHz
Delay: a
SUMMARY
Power Supplies
The MC1377 is designed to operate from an unregulated
10 V to 14 Vdc power supply. Device current into Pin 14 with
open output is typically 35 rnA. To provide a stable reference
for the'ramp generator and the video output, a high quality
8.2 V regulator can supply up to 10 rnA for external uses,
The preceding information was intended to detail the
application and basis of circuit choices for the MC1377. A
complete MC1377 application with the MC1374 VHF
modulator is illustrated in Figure 17. The internal schematic
diagram of the MC1377 is provided in Figure 8.
Figure 16. Application with VHF Modulator
470
471<
470
PAL
II
,...--_--+-f 17
3'58M~Hz
c:=I
220
5-25
10
o NTSC
-~
20
18
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13
12k
t--+----t14
11 12 19 15 7
0.1
.01
.Q1
+12Vdc
9-52
MOTOROLA ANALOG IC. DEVICE DATA
MC1377
APPLICATIONS INFORMATION
S-VHS
In full RGB systems (Figure 18), three information
channels are provided from the signal source to the display to
permit unimpaired image resolution. The detail reproduction
of the system is limited only by the signal bandwidth and the
capability of the color display device. Also, higher than
normal sweep rates may be employed to add more lines
within a vertical period and three separate projection picture
tubes can be used to eliminate the "shadow mask" limitations
of a conventional color CRT.
Figure 21 shows the "baseband" components of a studio
NTSC signal. As in the previous example, energy is
concentrated at multiples of the horizontal sweep frequency.
The system is further refined by precisely locating the color
subcarrier midway between luminance spectral components.
This places all color spectra between luminance spectra and
can be accomplished in the MC1377 only if "full interlaced"
external color r!lference and sync are applied. The individual
Figure 17. Spectra of a Full RGB System
components of luminance and color can then be separated
by the use of a comb filter in the monitor or receiver. This
technique has not been widely used in consumer products,
due to cost, but it is rapidly becoming less expensive and
more common. Another technique which is gaining popularity
is S-VHS (Super VHS).
In S-VHS, the chroma and luma information are contained
on separate channels. This allows the bandwidth of both the
chroma and luma channels to be as wide as the monitors
ability to reproduce the extra high frequency information. An
output coupling circuit for the compOSite chroma using the
TaKa transformer is shown in Figure 19. It is composed of
the bandpass transformer and an output buffer and has the
frequency performance shown in Figure 20. The composite
output (Pin 9) then produces the luma information as well as
composite sync and blanking.
Figure 19. Frequency Response of
Chroma Coupling Circuit
Red
G_
'~I IPl l l r'"
I
I
I
I
I
Blue
01
'11111 1111
:PI
1.0
:
:
I
~
§
II
I
§
2.0
3.0
f, FREQUENCY (MHz)
t"\
4-1l
Figure 18. S-VHS Output Buffer
+12Vdc
100l62pP
__
':,~~I --+-~_--'
Composite
Chroma
Out
f,MHz
2.7
3.66
4.5
0.1~F
*Refers to different component values used for NTSCIPAL (3.58 MHz/4.43 MHz).
"'Toko 166NNF-l026AG
MOTOROLA ANALOG IC DEVICE DATA
9-53
MC1377
I/Q System versus (R-V)/(B-Y) System
The NTSC standard calls for unequal bandwidths for I and
Q (Figure 21). The MC1377 has no means of processing the
unequal bandwidths because the I and Q axes are not used
(Figure 22) and because the outputs of the (R-V) and the
(B-V) modulators are added before being output at Pin 13.
Therefore, any bandwidth reduction intended for the chroma
information must be performed on the composite chroma
information. This is generally not a problem, however, since
most monitors compromise the standard quite a bit.
Figure 20. NTSC Standard Spectral Content
Figure 23 shows the typical response of most monitors
and receivers. This figure shows that some crosstalk
between luma and chroma information is always present.
The acceptability of the situation is enhanced by the limited
ability of the CRT to display information above 2.5 MHz. If the
signal from the MC1377 is to be used primarily to drive
conventional no~omb filtered, monitors or receivers, it
would be best to reduce the bandwidth at the MC1377 to that
of Figure 23 to lessen crosstalk.
Figure 21. Color Vector Relationship
(Showing Standard Colors)
Red (R-Y)
(1040) (90°)
1.0
2.0
3.0
f, FREQUENCY (MHz)
4.0
Green
(241°)
II
Purple
(61°)
Cyan
(284°)
Figure 22. Frequency Response of
Typical Monitornv
Chroma
Channel
Gain / - - - - - - ,
Luminance
Channel
1.0
9-54
MOTOROLA ANALOG IC DEVICE DATA
MC1377
Figure 23. A Prototype Chroma Bandpass Transformer
Toko Sample Number 166NNF-10264AG
(Drawing Provided By:
Toko America, Skokie, IL)
Unloaded Q (Pins 1-3): 15 @ 2.5 MHz
Inductance: 30 I1H ± 10% @ 2.5 MHz
Turns: 60 (each winding)
Wire: #38 AWG (0.1 m/m)
Connection Diagram
Bottom View
Figure 24. A Prototype Delay Line
TDK Sample Number DL1223010-1533
I'Markin
1.26 Max
32.0
'-.../
'-.../
'-.../
·1
'-.../
H
T
0.35 Max
9:0
0.93 Max
23.5
~
[
1
~I-
0.2 ± 0.04
5.0±1.0
0.026 ± 0.002
0.65±O.33
0.788 ±O.OB
20.0±2.0
0.8 Radius Max
2.0
Item
'Marking: Part Number, Manufacturer's Identification,
Date Code and Lead Number.
Skokie, IL (TDK Corporation of America)
Time Delay
Specifications
400ns±10%
Impedance
1200n±10%
Resistance
Less Than 15 n
Transient Response with 20 ns
Rise Time Input Pulse
Overshoot: 10% Max
Attenuation
3 dB Max at 6.0 MHz
Preshoot: 10% Max
Rise Time: 120 ns Max
MOTOROLA ANALOG IC DEVICE DATA
9-55
MC1377
Figure 25.RGB Pulse Generator
BNC
4.711f
1S ~1-...1MOk"'-_--{~N4403
Composite
Blanking
2.21<
10k
-5.OV
Reg
10k
112 MC74LSll2A
MC74LS112A
3.3k
MCl455
3.3k
~:
~__~r--l~5S~16'
a5
3J
T"
lc:!:5S'-+':16'
....... llJ 148
- - 12k
~
••
07
'----130
~
'---- lC
5
0.1
10k
I ~-+--......----i----------+......
8
-_--~------+..J
Adl
H
:1,-@
r
2N4401
-
Rl0
'::-Freq
__
1.8k
~
R4
R4
~~lNOk~~----.~
750pF
~
t--.......-!2k
154kHz
31---+-+-----~--~__{lC
1
~1
asl----+-_
L-I:-- ~~~
~~
--
>---- 7
1.~
BNC
Blue
Output
~
:J-@
•
2N4401
-
BNC
Red
Oulput
1.8k
-----t
~-@
•
2N4401
BNC
Green
Oulput
0.1
470
470
r~
470
II
RGB Pulse Generator Timing Diagram for NTSC
LJ
U-
1
...•. . . . - - - - - - - - - - 64J!S - - - - - - - - - - + 1
.. 1
Composite
Blanking
Input
154 kHz
Clock
Black
Blue
Output
Red
Output _______...
Green
Output _____...
9-56
MOTOROLA ANALOG IC DEVICE DATA
MC1377
Figure 26. Printed Circuit Boards for the MC13n
(CIRCUIT SIDE)
(COMPONENT SIZE)
Figure 27. Color TV Encoder - Modulator
470
47k
470
Vee
'-~:
s~+
~
17
20
18
16
8.2Vdc
75
0.33!LH
47
G~
MC1377
15~F
t
10.001
mica
10~
MC1374
12
~
3.3kB~+
RF
122
120
15~j!
0.001
E--<>0tJI
54k
R~
O.33~H
0.001
15~F
11
5.1k
10
13
75k
40011,
0.1
13
0
1.2k
14
11 12 19 15 7
ct,·
14
+
<0
VIdeo
Oul
Audio
In
.01
vee
(+12V)
MOTOROLA ANALOG IC DEVICE DATA
9-57
®
MOTOROLA
MC1378
Color Television Composite
Video Overlay Synchronizer
The MC1378 is a bipolar composite video overlay encoder .and·
microcomputer synchronizer. The MC1378 contains the complete encoder
function of the MC1377, i.e., quadrature color modulators, RGB matrix, and
blanking level clamps, plus a complete complement of synchronizers to lock
a microcomputer-based video source to any remote video source. The
MC1378 can be used as a local system timing and encoding source, but it is
most valuable when used to lock the microcomputer source to a remotely
originated video signal.
• Contains All Needed Reference Oscillators
COLOR TELEVISION
COMPOSITE VIDEO OVERLAY
SYNCHRONIZER
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
PLASTIC PACKAGE
.
CASE 711
• Can Be Operated in PAL or NTSC Mode, 625 or 525 Line
~
.
40
.
• Wideband, Full-Fidelity Color Encoding
• Local or Remote Modes of Operation
FNSUFFIX
PLASTIC PACKAGE
CASE 777
(PLCC-44)
• Minimal External Components
• DeSigned to Operate from 5.0 V supply
• Will Work with non standard Video
PIN CONNECTIONS
LocaVRem.
H. PLLFiher
H. Sync In
Camp. Sync Out
V. OuUSync In
H.VCO {
Clock PLL Filter
Burst Gate Out
II
Clock Output
Ground
Clock Ground
3.58/4.43 In
Chroma PLL Filter
Figure 1. Simplified Application
HSync
3.58/4.43MHz
Vert/Comp ~ync
Video
System
Red
MC1378
Green
Blue
Video Enable
---
Quad. Loop Filter
R-YClamp
PAL Indent. Cap
B-YClamp
VCC
Remote
Video
R Input
Comp. Vid. Out
Glnput
Ground
Blnput
Overlay Enable
-YOutput
Chroma Out
Composite
Overplayed
Video
}CIOCkVCO
Killer Fitter
ChromaVCO {
36MHz Master Clock
ClockVCC
PAUNTSC Mode
Loc. Vid. Clamp
Chroma In
Rem. Vid.ln
ACC Fiher
-Ylnput
Rem. Vid. Clamp
• ( ) PLCC Pin Assignments
LocaVRemote
ORDERING INFORMATION
i
525160
625150
9-58
i
PAU
NTSC
Device
MC1378P
MC1378FN
Operating
Temperature Range
TA = 0° to +70°C
Package
Plastic 01 P.
PLCC-44
MOTOROLA ANALOG IC DEVICE DATA
MC1378
MAXIMUM RATINGS
Rating
Supply Voltage
Operating Temperature
Storage Temperature
Junction Temperature
Power Dissipation, Package
Derate above 25°C
Symbol
Value
Unit
VCC
6.0
Vdc
TA
Oto +70
°C
Tstg
-65 to +150
°C
TJ(max)
150
°C
PD
1.25
10
W
mW/oC
RECOMMENDED OPERATING CONDITIONS
Condition
Pin
Value
28,36
5.4 ±0.25
Vdc
14,15,16
1.0
Vpp
8
0.5
Vpp
24
1.0
Vpp
Supply Voltage
RGB Input for 100% Saturation
Color Oscillator Input Level
Video Input, Positive
Unit
ELECTRICAL CHARACTERISTICS (VCC =5.0 V, TA =25°C, circuit of Figure 4 or 5)
Characteristics
Supply Current
Pin
Min
Typ
Max
Unit
28,36
-
100
-
mAdc
Video Output, Open Circuit, Positive
27
-
2.0
9.4
Vpp
Modulation Angle (R - Y) to (B - Y)
-
87
90
93
Degrees
14, 15, 16
-
10
-
kQ
1
-
Remote
Local
-
-
RGB Input Impedance
LocaVRemote Switch (TTL)
High
Low
Horizontal Sync Input, Negative Going
(TTL)
40
-
4.3
-
Vpp
38
-
4.3
-
Vpp
(TTL)
39
-
4.3
(TTL)
5
-
4.3
Vertical Sync Output, Negative Going,
Remote Mode
(TTL)
Composite Sync Output, Negative Going
Burst Gate Output, Positive Going
-
Vpp
Vpp
Description of Operation - Refer to Figures 3, 4
Remote Mode
Local Mode
The incoming remote video signal (Pin 24) supplies all
synchronizing information. A discussion of the function of the
phase detectors helps to clarify the lockup method:
The MC1378 and a video system combine to provide a fully
synchronized standard signal source. In this case, composite sync
must be supplied by the video system or other time base system.
In the MC1378 the phase detectors operate as follows:
PD1 -
locks the internally counted-down 4 MHz horizontal VCO
to the incoming horizontal sync. It is fast acting, to follow
VCR source fluctuations.
PD1 -
locks the internally counted-down 4 MHz horizontal VCO
to a Horizontal Sync signal (at Pin 40) from the video
system (counted down from 36 MHz)
PD2 -
locks the 36 MHz clock VCO, which is divided down by
the video system, to the divided down horizontal VCO.
PD2 PD3 -
not used in LOCAL MODE.
not used in LOCAL MODE.
PD3 -
is a gated phase detector which locks the 14 MHz crystal
oscillator, divided by 4, to the incoming color burst.
PD4 -
active, but providing an arbitrary phase shift setting
between the color oscillator and the output burst phase.
PD4 -
controls an internal phase shifter to assure that the
outgoing color burst is the same phase as incoming burst
atPD3.
not used in REMOTE MODE
PD5 -
locks the 36 MHz clock VCO (which is divided down by
the video system) to the 14 MHz (crystal) color oscillator.
The 14 MHz is, therefore, the system standard in LOCAL
MODE, and is not DC controlled.
PD5 -
Vertical lock is obtained by continuously resetting the sync
generator in the video system with separated vertical sync from the
MC1378, Pin 38. This signal is TTL level vertical block sync,
negative going. The horizontal sync from the video system to Pin 40
is also TTL level with sync negative going. The locaVremote switch,
Pin 1, is in local mode when grounded, remote mode when taken
to 5.0 V. The overlay control, Pin 25, has an analog characteristic,
centered about 1.0 V, which allows fading from local to remote.
MOTOROLA ANALOG IC DEVICE DATA
COMPOSITE VIDEO GENERATION
The color encoding at the RGB signals is done exactly as in
the MC1377. Composite chroma is looped out at Pins 18 and 20
to allow the designer to choose band shaping. Luminance is
similarly brought out (Pins 17 and 22) to permit installation of
the appropriate delay.
Composite sync output, Pin 39, and burst gate output, Pin 5,
are provided for convenience only.
9-59
..
~
Figure 2. Representative Block Diagram
e~cl<
Burst Gate Out
Out
~~~
.i
Vee
+5.0 V
~
5------------------------
36-
~ '--<;>34
Gnd~
""",
i
I
1-,
28
~
4 MHz
35.8/
35.5
veo
MHz
o:I6------I ~
..
I
~
i:
....
(')
PW
NTSC~
I Comp
I SyncOut
~
I
I. locaIIRemolB
I
I
LocIRem
==
a
L
SWItcIIos
38
I Vert.Out
I Comp. Sync In
:u
o
!;
~
J:o
8
(5
c
~
om
c
~
)i
I
I
I
I
I
IL _ _ _ _ _ ..!!
-29
rr
____
25
Overtey
Remo1eII
Enab~
Vee
Video In
.".
7/26
I
I
I
I
I
--~I-J
~
MC1378
Figure 3. Remote Mode
OVerlay Enable
Remote
Master Clock 35.8135.5MHz
+5
Video
Vee
Out
Video
In
75
0.1
36pF
33
32
31
30
29
28
27
26
25
TDK
Local
Video
Source
SOL-4301
Figure 4. Local Mode
+
1.0)1F
+
1·000F
TDK
SOL-4301
+8
Local
Video
Source
MOTOROLA ANALOG IC DEVICE DATA
9-61
®
MOTOROLA
MC1391
TV Horizontal Processor
The MC1391 provides low-level horizontal sections including phase
detector, oscillator and pre-driver. This device was designed for use in all
types of television receivers.
TV HORIZONTAL.
PRQCESSOR
• Internal Shunt Regulator
• Preset Hold Control Capability
SEMICONDUCTOR
TECHNICAL DATA
• ±300 Hz Typical Pull-In
• Linear Balanced Phase Detector
• Variiible Output Duty Cycle for Driving Tube or Transistor
• Low Thermal Frequency Drift
• Small Static Phase Error
• Adjustable DC Loop Gain
• Positive Flyback Inputs
PSUFFIX
PLASTIC PACKAGE
CASE 626
ORDERING INFORMATION
II
470
Operating
Temperature Range
Package
MC1391P
TA =0° to +70°C
Plastic DIP
Figure 1. Simplified Application
Vnonreg
+30V
RA
Device
1.
RS
470
CA
+ RD
100~F r
2.7k
~(,
+IS0V
~.3k
Hold
r-'
RE
2.4k
IIQb.
High
4k
lOW
Rx
3.3k
12k
0.0068
Ry
~1
IS0k
O.ooS
~F
rCS
V~ltage
Tnpler
J. Cc..}
J
J
JL
ll1F
~
8
2.2k
7
6
S
~I
ISk
MCl391P
1
2~
Rzt
82k
3 ~
41
39k
.".
T
~
-20VSync
f?
~
Y
0
0.001 ~
~F
O.I~F
K
E
~S.3:1
MRD
1140 A
S.OIlF
I-0.003
I1F
MJ10S or Equiv
1.S
or
Equiv
r-.O.Ol
~F
r:;
0.2
~F
1"'~
or Equiv
fO.l 11F
t
RZ -- 6.8 k per 100 V of flyback amplitude .
This circuit has an oscillator pull-in range of ±300 Hz, a noise bandwidth of 320 Hz, and a damping factor of 0.8 .
9-62
..MOTOROLA ANALOG IC D.EVICE DATA
MC1391
MAXIMUM RATINGS (TA = +25'C, unless otherwise noted.)
Rating
Supply Current
Value
Unit
40
mAdc
Output Voltage
40
Vdc
Output Current
30
mAdc
Sync Input Voltage (Pin 3)
5.0
Vpp
Flyback Input Vo~age (Pin 4)
5.0
Vpp
Power Dissipation (Package Limitation)
Plastic Package
Derate above TA = +25'C
625
5.0
mW
mW/'C
Oto+70
'c
--e5 to +150
'C
Operating Temperature Range (Ambient)
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (TA = +25'C, unless otherwise noted. See Test CircuH 01 Figure 2, all switches in position 1.)
Characteristics
Min
Typ
Max
8.0
B.6
9.4
Vdc
Supply Current (Pin 6)
-
20
-
mAdc
Collector-Emitter Saturation Voltage (Output Transistor 01 in Figure 6)
(IC = 20 mA, Pin 1 ) Vdc
-
0.15
0.25
Regulated Voltage (Pin 6)
Unit
Vdc
Voltage (Pin 4)
-
2.0
-
Vdc
Oscillator Pull-in Range (Adjust RH in Figure 2)
-
±300
-
Hz
Oscillator Hold-in Range (Adjust RH in Figure 2)
-
±900
-
Hz
Static Phase Error
(M=300Hz)
-
0.5
-
Free-running Frequency Supply Dependance
(Sl in position 2)
-
±3.0
-
Phase Detector Leakage (Pin 5)
(All switches in position 2)
-
-
±1.0
Sync Input Voltage (Pin 3)
2.0
-
5.0
Vpp
Sawtooth Input Voltage (Pin 4)
1.0
-
3.0
Vpp
r' .
-=
Ji
MCl391P
150k
8
•
1.0k
,VM
Vee +30V (See Figure 5)
-=
2.0k
MOTOROLA ANALOG IC DEVICE DATA
Output
Pulse
+30V
1
1:'
":"
39k
2
7
6800pF ~j:;
L
3
6
'"3.0k
1.0k
~~S2
5
O.l~F
+4.0V
12k
~
2
1
~~lS1
RH
HzlVdc
Figure 2. Test Circuit
33k
_ 2
JJ
~s
2
I·
S3
E-f-.:e:-
0.003
~F
Pulse Generator
Output = +50 V
12~
Pulse Generator
Sync Pulse =
-20 V, 5.0 ~s,
10 = 15.750 Hz
II
MC1391
Figure 3. Frequency versus Temperature
Figure 4. Frequency Drift versus Warm-Up TIme
40
30
- --
20
10
N'
0
- -10
(.)
zw -20
::>
0
w
--30
U.
-40
II:
r--...
Reference Frequency
= 15.750 Hz
,
z 20
(.)
::>
f".....
S3 in PasHion 2
10
/
w
............
o
./
a:Cl
-50
-60
-70
N'
20
30
40
50
60
TA, AMBIENT TEMPERATURE (0C)
@
u.
70
---
10k
3.9k
RolHlff
Output
5.1k
Il-c~
~.J--
-=
-=
2
5.1k
5.1k
-=
-=
5.1k
6
1
750
4.7k
6.2k
S.1k
Input
1
1
...
....
20k
510
MOTOROLA ANALOG IC DEVICE DATA
-=
1.3k
1.5k
510
9-67
MC3340
Figure 3. Attenuation versus
DC Control Voltage
o
20
"-
vee!'
8.0Vdc _
"- r\
,
\.
,~
,"\:
~~
"
2.5
"-
-
. , "',l'\"
','
lz
r--...
~
40
~
~
,
l..........
:J
z
~
,,,\:
"
"
5.5
60
o dB Reference = 13 dB Gain
f= to kHz-
80
6.0
z
~
w
8:
2:.
~
"
Input voltage (ein) = 10 mV
Pin 6 uncompensated
~w
~
~ 6.0
~
II
15
20
30
....
40
-
-
I"""
6.0
>!i
..",.. I--
/'
~ 4.0
~
2.0
100
8.0
C!l
.jJ 4.0
o
10
.........
"-
Figure 6. Output Voltage Swing
10
8.0 f-
8.0
""
",
10
12
C!l
"
1"'.....
Re. CONTROL RESISTOR (kn)
Figure 5. Frequency Response
~
"'" ,"........
RC. is from Pin 2 to ground
100
4.0
6.5
14
iii'
,
0
",.
3.5
4.5
V2. CONTROL VOLTAGE (V)
r-...
20
VCc=
'\. 16Vdc
r, ......, ~', "
I',,'Y,,"
~,
100
1.5
'\.
~12Vdc
,
-
0
vee=
Figure 4. Attenuation versus
Control Resistor
2.0
o
1.0k
10k
100k
tOM
f. FREQUENCY (Hz)
10M
8.0
100M
9.0
10
11
12
13
14
15
VCC. SUPPLY VOLTAGE (V)
16
17
18
Figure 7. Total Harmonic Distortion
_ 4.0
C
~
~
a(,,)
3.0
/
1
/
20
.
/
~ 1.0
i2
I
9-68
o dB Reference = 13 dB Gain
f=1.0kHz
eo=2.5Vnns
_ _ r""
ci
~
/
"
~
0
o
10
20
30
40
50
ATIENUATION (dB)
60
70
80
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC3346
General Purpose Transistor
Array One Differentially
Connected Pair and Three
Isolated Transistor Arrays
GENERAL PURPOSE
TRANSISTOR ARRAY
The MC3346 is designed for general purpose, low power applications for
consumer and industrial designs.
SEMICONDUCTOR
TECHNICAL DATA
• Guaranteed Base-Emitter Voltage Matching
• Operating Current Range Specified: 10 IlA to 10 mA
• Five General Purpose Transistors in One Package
PSUFFIX
PLASTIC PACKAGE
CASE 646
MAXIMUM RATINGS
Symbol
Value
Collector-Emitter Voltage
Rating
VCEO
15
Vde
Collector-Base Voltage
VCBO
20
Vde
Emitter-Base Voltage
VEB
5.0
Vde
Collector-Substrate Voltage
VCIO
20
Vde
IC
50
mAde
Po
1.2
10
W
mW/oC
TA
-40 to +85
°C
Tstg
-65 to +150
°C
Collector Current - Continuous
Total Power Dissipation
Derate above 25°C
@
TA = 25°C
Operating Temperature Range
Storage Temperature Range
Unit
DSUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
ORDERING INFORMATION
Device
Operating
Temperature Range
MC3346D
MC3356P
TA = -40° to +85°C
Package
S0-14
Plastic DIP
PIN CONNECTIONS
Pin 13 is connected to substrate and must remain at the lowest circuit potential.
MOTOROLA ANALOG IC DEVICE DATA
9-69
MC3346
ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted.)
I
I
Symbol
Min
Typ
Max
Unit
Collector-Base Breakdown Voltage
(IC = 10 jJAdc)
V(BR)CBO
20
60
-
Vde
Collector-Emitter Breakdown Voltage
(lc = 1.0 mAde)
V(BR)CEO
15
-
-
Vde
Colleetor-8ubstrate Breakdown Voltage
(lc = 1OI1A)
V(BR)CIO
20
60
-
Vde
Emitter-Base Breakdown Voltage
(IE = 10 jJAdc)
V(BR)EBO
5.0
7.0
-
Vde
Collector-Base Cutoff Current
(VCB = 10 Vde, IE = 0)
ICBO
-
-
40
nAdc
DC Current Gain
(IC = 10 mAde, VCE = 3.0 Vde)
(IC = 1.0 mAdc, VCE = 3.0 Vdc)
(IC = 10 jJAde, VCE = 3.0 Vdc)
hFE
-
140
130
60
-
Base-Emitter Voltage
(VCE = 3.0 Vdc, IE = 1.0 mAde)
(VCE = 3.0 Vdc, IE = 10 mAdc)
VBE
-
0.72
0.8
11101- 11021
-
0.3
2.0
jJAdc
-
-
0.5
5.0
mVde
Ll.VBE
-
-1.9
-
mV/oC
ILl.Vlol
-
1.0
-
I1V/oC
ICEO
-
-
0.5
I1Ade
Low Frequency Noise Figure
(VCE = 3.0 Vdc, IC = 100 jJAdc, RS = 1.0 kn, I = 1.0 kHz)
NF
-
3.25
-
dB
Forward Current Transler Ratio
(VCE = 3.0 Vde, IC = 1.0 mAdc, I;: 1.0 kHz)
hFE
-
110
-
-
Short Circuit Input Impedance
(VCE = 3.0 Vdc, IC = 1.0 mAde)
hie
-
3.5
-
kQ
Open Circu~ Output Impedance
(VCE = 3.0 Vdc, IC = 1.0 mAdc)
hoe
-
15.6
-
I1mhos
Reverse Voltage Transfer Ratio
(VCE = 3.0 Vde, IC = 1.0 mAdc)
h re
-
1.8
-
x10-4
Forward Transler Admittance
(VCE = 3.0 Vdc, IC = 1.0 mAdc, I = 1.0 MHz)
Yle
-
31-j1.5
-
-
Input Admittance
(VCE = 3.0 Vdc, IC = 1.0 mAde, I = 1.0 MHz)
Yie
-
0.3+ jO.04
-
-
Output Admittance
(VCE = 3.0 Vdc, IC = 1.0 mAdc, 1= 1.0 MHz)
Yoe
-
0.001 + jO.03
-
-
IT
300
550
-
MHz
Emitter-Base Capacitance
(VEB = 3.0 Vdc, IE = 0)
Ceb
-
0.6
-
pF
Collector-Base Capacitance
(VCB = 3.0 Vdc, IC = 0)
Ccb
-
0.58
-
pF
Collector-Substrate Capacitance
(VCS = 3.0 Vdc, IC = 0)
CCI
-
2.8
-
pF
Characteristics
STATIC CHARACTERISTICS
Input Offset Current for Matched Pair 01 and 02
(VCE = 3.0 Vdc, IC = 1.0 mAde)
Magnitude of Input Offset Voltage
(VCE = 3.0 Vde, IC = 1.0 mAdc)
Temperature Coefficient of Base-Emitter Voltage
(VCE = 3.0 Vde, IC = 1.0 mAdc)
Temperature Coefficient
Collector-Emitter Cutoff Current
(VCE = 10 Vde, IB = 0)
II
40
or
---o:r
-
Vde
-
DYNAMIC CHARACTERISTICS
Current-Gain - Bandwidth Product
(VCE = 3.0 Vdc, IC = 3.0 mAde)
9-70
MOTOROLA ANALOG IC DEVICE DATA
MC3346
Figure 1. Collector Cutoff Current
versus Temperature (Each Transistor)
/
-IB=O
/
......
-
/
./. ~
./
CE = 10V
,.,
Figure 2. Collector Cutoff Current
versus Temperature (Each Transistor)
/.0
/
/
vr. = 15
VCE=5.0V
.........
25
~~
50
75
100
125
25
Figure 3. Input Offset Characteristics
forQ1 and Q2
<>
1,
I-
z
UJ
a:
a:
:::>
'-'
tu
en
u.
u.
0
I-
:::>
0..
;;!;
~
125
0.9
5.0
0.8
4.0
~
UJ
C!>
!:§
./
0.3
0.2
0.03
0.02
50
75
100
TA. AMBIENT TEMPERATURE (ec)
Figure 4. Base-Emitter and Input Offset
Voltage Characteristics
1.0
0.7
0.5
0.1
0.07
0.05
VCB=5.0V
V B = 10V
~
TA. AMBIENTTEMPERATURE (ec)
"C
~/
~
......
1/
'"
0.01
0.01
a:
VB
0.7
UJ
!=::;;
~
....
0.6
0
3.0 >
tu
en
2.0
-""
w 0.5
u.
>
0.1
0.2
0.3
0.5 0.7 1.0
. ,VIF,-
0.01
0.05
IC. COLLECTOR CURRENT (mAde)
0.1
0.5
1.0
5.0
0
10
IE. EMITTER CURRENT (mAde)
Figure 5. DC Current Gain
140
3.5
3.0
",
V
z 130
I-
hFE
Z
UJ
a: 110
a:
:::>
'-'
'-'
90
D
2.0
I-"
1.5
1.0
/
W
u.
70
./
50
0.01
0.95
I,.oof-'
".
.<:
0.9
11m Ior! hFE21
FE2
F
,
,EI,-
0.05
0.1
0.5
"'I t
1.0
5.0
0.85
0.8
0.75
10
o
~
z
!z
UJ
a:
a:
ag
i.~
~
.<:
IE. EMITTER CURRENT (mAde)
MOTOROLA ANALOG IC DEVICE DATA
u.
u.
0
50..
1.0
0.4
0.05
UJ
!:§
V
........
~
0.02 0.03
g
C!>
§2
....-
:g
9-71
;;!;
Q
>
II
®
MOTOROLA
MC3373
Remote Control
Amplifier/Detector
The MC3373 is intended for application in infrared remote controls. It
provides the high gain and pulse shaping needed to couple the signal from
an IR receiver diode to the tuning control system logic.
REMOTE CONTROL WIDEBAND
AMPLIFIER WITH
DETECTOR
• High Gain Pre-Amp
SEMICONDUCTOR
TECHNICAL DATA
• Envelope Detector for PCM Demodulation
• Simple Interface to Microcomputer Remote Control Decoder
• Use with Tuned Circuit for Narrow Bandwidth, Lower Noise Operation
• Minimum External Components
• Wide Operating Supply Voltage Range
• Low Current Drain
• Improved Retrofit for NEC Part NO.IlPC1373
o SUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
• MC14497 Recommended IR Transmitter
• MLED81 Complementary Emitter
• MRD821 Complementary Detector Diode
Vee
Input
Filter
Ground
ORDERING INFORMATION
Device
MC3373P
MC3373D
Operating
Temperature Range
TA=Oto+75°C
Package
Plastic DIP
S0-8
(2)
1N914
150k
To
Keyboard
+5.0Vdc
-+-+++-117
-+-+++-12
-1--+-+-+--1 16
-1--+-+-+--1 14
-1---+-+-+--1 11
18
MC14497
(3)
MLED71
Infrared
Emitting
Diodes
4
5
6
LfTRONIX
SFH206
Receiver
Dioda
1N914
9-72
MOTOROLA ANALOG IC DEVICE DATA
MC3373
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Power Supply Voltage (25°C)
VCC
4.75
Power Supply Voltage (DOC)
VCC
5.0
fin
30
Characteristics
Input Frequency
Max
Unit
-
15
Vdc
-
15
Vdc
40
80
kHz
ELECTRICAL CHARACTERISTICS (TA = 25'C, VCC = 5.0 V, fin = 40 kHz, Test circuit of Figure 2)
Symbol
Min
Typ
Max
Unit
Power Supply Current
ICC
1.5
2.5
3.5
mAdc
Input Terminal Voltage
V(Pin7)
2.4
2.8
3.0
Vdc
50
100
Characteristics
Input Voltage Threshold
Input Amplifier Voltage Gain
(V[Pin 3] = 500 mVpp)
60
AV
60
Input Impedance
dB
80
Output Voltage, Vin = 1.0 mVpp
0.5
Output Leakage, VCC = VOH = 15 Vdc
2.0
:~ .... ~'
Output Voltage, Input Open
,
5.0
V
Vdc
/;~~:~~;::i:i'
,,";; 'y:
Figure 2.
Teli!('~~i~
+
.*'~\t~.::'f"
VCC= 5.0Vdc
lOOk
Output
COIL:
TOKOINC.
CANS-4612Z
II
3
4 1--.---11-------'
(Bottom View)
Figure 3. Representative Block Diagram
Tuned
Circuit and VCC
VCC
3
Detector
Threshold (Fig. 5)
4
Output
Output
Inputfrom
Decoupling
7
Detector
Gain Adjust
(Fig. 4)
MOTOROLA ANALOG IC DEVICE DATA
Ground
9-73
MC3373
Figure 4. Input Amplifier Gain
i
Figure 5. Detector Threshold
1.0
100
~
z
~
w
w
c
:::>
80
(!)
60
w
~
40
""
~
20
:;;
'"""w
~
ffi
z
r- Vee = 8.5 Vdc
r-.
.........
<">
~
.£
'\
0-
:;;
i'-
a:
u::
~
..........
1:5
§2
12Vdc
r--- rr Ve
f= ~~ed::
z
a:
I
0
1.0
10
100
RPin6, Pin 6 RESISTOR (0)
1000
100
50
"""'-..."
-.....
I'""--.
150
--
200
250
APPLICATIONS INFORMATION
II
The MC3373 is a specialized high gain amplifier/signal
processor bipolar analog IC designed to be the core of
infrared carrier signaling systems. The amplifier section has
an Automatic Bias Level Control (ABLC) for simplified direct
connection to an IR detector diode. Generally, it is operated
ac .coupled, utilizing an input high-pass filter to eliminat
power line related noise, particularly that from f10re
gas vapor lamps. The use of a high frequency
strongly recommended as opposed to simply d
bursts of IR energy. In the carrier mode setup
acts like an AM receiver subsystem, am
signal, demodulating it, and providing'
shaping of the demodulated envelo
Tti
Pin 3 provides the main system
noise interference and permittin
n in
the same physical area wit
.Itichannel
case the carriers must
elated. The
bandwidth is determined
of the coil.
Bandwidth may be increased
shunting, the coil
with a resistor.
Since this is a very high gain system operating at relatively
high frequencies, care must be taken in the circuit layout and
construction. Do not use wire wrap or non-ground plane
. protoboard. A simple single sided PCB with ground fill or a
two-sided board with a solid groundplane and top side
point-to-point will provide consistent high performance.
There is a wide array of IR emitter/detectors available. The
Motorola MLED81 and MRD821 are an excellent low cost
combination to use with the MC3373. Multiple emitters are
recommended for extended range.
9-74
~
"''---~'''''''~--
2.8 V
r----I_ _
r-__
Vee
0.5V
~
o
The input amplifier gain is approximately equal to the load
impedance at Pin 3, divided by the resistor from Pin 6
to ground. Again, the low frequency gain can be reduced
by using a small coupling capacitor in series with the
Pin 6 resistor.
The load may be resistive, with only, or tuned, as in the test
circuit. The amplifier output is limited by back-ta-back
clamping diodes, level shifted, buffered and fed to a negative
peak detector. The detector threshold is set by the external
resistor on Pin 4, and an internal 6.8 kQ resistor and diode to
VCC. The capacitor from VCC to Pin 4 quickly charges during
the negative peaks and then settles toward the set-up
voltage between signal bursts at a rate roughly determined
by the value of the capacitor and the 6.8 k resistor. The
external capacitor at Pin 2 filters the ultrasonic carrier from
the pulses.
MOTOROLA ANALOG Ie DEVICE DATA
MC3373
CIRCUIT DESCRIPTION
01 to 04 set the bias on the amplifier input at
approximately 2.8 V. 06 to 01 0 form the input amplifier, which
has a gain of about 80 dB when R(Pin 6) =0, 05 sinks input
current from the photo diode and keeps the amplifier properly
biased. 018 to 020 level shift and buffer the signal to the
negative peak detector, 022 and 023. Output devices 026
and 027 conduct during peaks and pull the output (Pin 1) low.
The capacitor on Pin 2 filters out the carrier.
Figure 7. Representative Schematic Diagram
Vee
8
A23
A1
56k
15k
Input
Output
A7
6.8k
1
1
06
A2
68k
A6
300
+----1----1-4
Rtter
026
A19
10k
A22
200
A13
3.3k
A10
10k
MOTOROLA ANALOG IC DEVICE DATA
A20
7.Sk
+----vvv---LQ27
A21
2.2k
A15
2.2k
II
A24
2.2k
9-75
®
MOTOROLA
MC13020
Motorola' C-QUAM®
AM Stereo Decoder
MOTOROLA c-aUAM®
AM STEREO DECODER
This circuit is a complete one ship, full feature AM stereo decoding and
pilot detection system. It employs full-wave envelope signal detection at all
times for the L + R signal, and decodes L - R signals only in the presence of
valid stereo transmission.
SEMICONDUCTOR
TECHNICAL DATA
• No Adjustments, No Coils
• Few Peripheral Components
• True Full-Wave Envelope Detection for L + R
• PLL Detection for L - R
• 25 Hz Pilot Presence Required to Receive L - R
J'fff"f'fn
• Pilot Acquisition Time 300 ms for Strong Signals, Time Extended for
Noise Conditions to Prevent "Falsing"
• Internal Level Detector can be used as AGC Source
1
.
PSUFFIX
PLASTIC PACKAGE
CASE 738
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC13020P
TA = - 40 10 +85°C
PlaslicDIP
Figure 1. Simplified Application
+8.0Vdc
II
0.0033
0.0033
0.0033.
2
3
IF Input o-----j
0.01
4
Optional Tuner
AGCSource
+
10ILF l
I Detector
o Detector
Envelope
Detector
Phase Detector
IF Input
Level
Detector
Error
Amplifier
0.001
6
l
7
Audio {
Outputs
8
VCC
19
47ILF
T
Osc.lnput
LED
Stereo
Indicator
Ground
15
Stereo Lamp
Pilot Detector
Input
14
Pilot Filter
Input
13
+
0.47
220k
+
0.47
lOOk
Auto Monaural
)
9
10
+
2. 21LF l
Forced
Monaural
Lock
~
Osc. Feedback
Left Output
Right Output
220
910
1.5k
Co-Channel
Input
AGC'dO
Output
4.7k
+
l2.21LF
11
430
+
4.71LF l
'muRata Ceramic Resonator - CSA3.60MGF10l
The purchase of the Motorola C-QUAM® AM Stereo Decoder does not carry wtth such purchase any license by implication, estoppel or otherwise,
under any patent rights of Motorola or others covering any combination of this decoder wtth other elements including use in a radio receiver. Upon
application by an interested party, licenses are available from Motorola on ITS patents applicable to AM Stereo radio receivers.
S"-76
MOTOROLA ANALOG IC DEVICE DATA
MC13020
MAXIMUM RATINGS
Rating
Symbol
Supply Voltage
VCC
Pilot Lamp Current, Pin 15
Operating Temperature
Value
Unit
14
Vdc
50
mAdc
°C
TA
-40 to +65
Storage Temperature
Tstg
-65 to +150
°C
Junction Temperature
TJ(max)
150
°C
Power Dissipation
Derate above 25°C
Po
1.25
10
mwrc
W
ELECTRICAL CHARACTERISTICS (VCC: 6.0 Vdc, TA : 25°C, Input qignal : 200 mVrms. Unmodulated carrier, circuit of Figure 1,
unless otherwise noted.)
Characteristics
Supply Line Current Drain, Pin 6
Input Signal Level, Unmodulated, Pin 3, for Full Operation
Audio Output Level, 50% Modulation
L only or R only
Monaural
Channel Balance, 50% Modulation, Monaural
Output THO, 50% Modulation
Monaural
Stereo
Monaural
Output THO, 90% Modulation
Channel Separation, L only or R only, 50% Modulation
Input Impedance
Rin
Cin
Qutput Impedance
Pilot Acquisition Time
VCO locked (after release of forced monaural)
Bad Signal Condition
Lock Detector Filter Voltage, Pin 10
In Lock
Qut of Lock
Max
Unit
30
40
mAdc
112
200
357
mVrms
160
60
220
110
260
140
mVrms
-
-
±1.0
dB
-
-
0.5
1.0
1.0
%
-
-
23
30
-
dB
20
-
27
6.0
-
kQ
pF
-
100
150
Q
-
260
300
-
ms
sec
-
Vdc
-
7.7
6.0
0.6
1.0
2.5
0.15
-
Vdc
-
1.0
p.A
-
3.5
<0.001
3.7
1.0
Vdc
2.0
Pull-Up for Automatic Mode
Figure 2. Basic Quadrature AM (QUAM)
Average
Carrier
Typ
20
1.46
Force to Monaural, Pin 9
Pull-Down for Monaural Mode
l+L+~
Min
V (1+L+A)2 + (L-A)2: Envelope
Envelope amplitude
is not a correct
sum signal for
envelope detection.
p.A
Figure 3. Motorola C-QUAM®
(l+L+A)cos6 l+L+A
.is
8
Average
Carrier
Envelope is
compatible
with existing
monaural
receivers.
I (L-A)cos8
MOTOROLA ANALOG IC DEVICE DATA
9-77
II
MC13020
Figure 4. Representative Block Diagram
V~o-------~~r-----------~~~----.
~~------------------o
Optional
AGC
To Tuner
I~-:-f--<>-~~L:o Audio
Outputs
'----r__J--Q-'''---'-'O (Note 1)
Vee
0.01
IF Input o-II---"3'(')--,l-l
Force to
L~~,-t---------?-,'-----OMonaural
-,
18
CJ
See Text
and Figures
5,6and7
17
I
I
I
I
I
Cs I
16
11
430
_.J
r-~~-1----~~r-----------~r---+---~-J
NOTE 1. Output polarny is defined
for receiver fmnt end with LO above
signal frequency.
MOTOROLA C-QUAM® - COMPATIBLE QUADRATURE AM STEREO
Introduction
In C-QUAM®, conventional quadrature amplitude
modulation has been modified by multiplying each axis by
cose as shown in Figures 2 and 3. The resulting carrier
envelope is 1 + L + R, I.e., a correct sum signal for monaural
receivers and for stereo receivers operating in monaural
mode. A 25 Hz pilot signal is added to the L - R information at
a 4% modulation level.
90° relative demodulation angles by reference Signals from
the phase-locked, divided-down VCO. The output of the
I DET is 1 + L + R, with the added benefit (over the Env DET)
of being able to produce a negative output on strong
co-channel or noise interference. This is used to tell the Lock
circuit to go to monaural operation. The output of the Q DET
is the L - R and pilot information.
Decoder
The MC13020P takes the output of the AM IF amplifier and
performs the complete C-QUAM® decoding function. In the
absence of a good stereo signal, it produces an undegraded
monaural output. Note in Figure 4 that the L + R information
delivered to the output always comes from the envelope
detector (Env DET).
. The MC13020P decodes the stereo information by first
converting the C-QUAM® signal to QUAM, and then
detecting QUAM. The conversion is accomplished by
comparing the output of the Env DET and the I DET in the Err
AMP. This provides 1/cose correction factor, which is then
multiplied by the c-aUAM® incoming signal in the Var Gain
block. Thus, the output of the Var Gain block is a QUAM
signal, which can then be synchronously detected by
conventional means. The I and Q detectors are held at 0° and
VCO
The VCO operates at8 times the IF input frequency, which
ensures that it is out-of-band, even when a 260 kHz IF
frequency is used. Typically, a 450 kHz IF frequency is used
with synthesized front ends. This places the VCO at 3.6 MHz,
which permits economic crystal and ceramic resonators. A
crystal VCO is very stable, but cannot be pulled very far to
follow front-end mis-tuning. Pull-in capability of ±1oo Hz at
450 kHz is typical, and de--Q-ing with a resistor (see Figure
7) can increase the range only slightly. Therefore, the crystal
approach can only be used with very accurate, stable
front-ends. By comparison, ceramic and L - C VCO circuits
offer pull-in range in the order of ±2.5 kHz (at 450 kHz).
Ceramic devices accurate enough to avoid trimming .
adjustment can be obtained with a matched capacitor for Cs
(see Figure 1 and 5).
9-78
MOTOROLA ANALOG IC DEViCE DATA
MC13020
In the PLL filter circuit on Pin 19, C1 is the primary factor in
setting a loop corner frequency of 8.0 to 10Hz, in-lock. An
internally controlled fast pull-in is provided. R2 is selected to
slightly overdamp the control loop, and C2 prevents high
frequency instability.
The Level DET block senses carrier level and provides an
optional tuner AGC source. It also operates on the Q AGC
block to provide a constant amplitude of 25 Hz pilot at Pin 11 ,
and it delivers information to the pilot decoder regarding
signal strength.
Pilot and Co-Channel Filters
The Q AGC output drives a low pass filter, made up of
400 n internal and 430 nand 5 (IF external. From this point,
an active 25 Hz band-pass filter is coupled to the Pilot
Decoder, Pin 14, and another low-pass filter is connected to
the Co-channellnput, Pin 12. A 2:1 reduction of 25 Hz pilot
level to the Pilot Decode circuit will cause the system to go
monaural, with the components shown. Refer to Figure 8 for
the formulas governing the active band-pass filter. The
co-channel input signal contains any low frequency
intercarrier beat notes, and, at the selected level, prevents
the Pilot Decode circuit from going into stereo. The
co--channel input, Pin 12, gain can be adjusted by changing
the external 1.5 k resistor. The values shown set the "trip"
level at about 7% modulation. The 25 Hz pilot signal at the
output of the active filter is opposite in phase to the pilot signal
coming from the second low-pass filter. The 56 k resistor
from Pin 14 to Pin 12 causes the pilot to be cancelled at the
co--channel input. This allows a more sensitive setting of the
co-channel trip level.
Pilot Decoder
The Pilot Decoder has two modes of operation. When
signal conditions are good, the decoder will switch to stereo
after 7 consecutive cycles of the 25 Hz pilot tone. When
signal conditions are bad, the detected interference changes
the pilot counter so as to require 37 consecutive cycles of
pilot to go to stereo. In a frequency synthesized radio. the
logic that mutes the audio when tuning can be connected to
Pin 9. When this pin is held low it holds the decoder in
monaural mode and switches it to the short count. This pin
should be held low until the synthesizer and decoder have
both locked onto a new station. A 300 ms delay should be
sufficient. " the synthesizer logic does not provide sufficient
delay, the circuit shown in Figure 9 may be added. Once Pil'1
9 goes high, the Pilot Decoder starts counting. " no pilot is
detected for seven consecutive counts, it is assumed to be a
good monaural station and the decoder is switched to the
long count. This reduces the possibility of false stereo
triggering due to signal level fluctuation or noise. " the PLL
goes out of lock, or interference is detected by the
co-channel protection circuit before seven cycles are
counted, the decoder goes into the long count mode. Each
disturbance will reset the counter to zero. The Level Detector
will keep the decoder from going into stereo if the IF input
level drops 10 dB, but will not change the operation of the
pilot counter.
Once the decoder has gone into the stereo mode, it will go
instantly back to monaural if either the lock detector on Pin 10
goes low, or if the carrier level drops below the present
threshold. Seven consecutive counts of no pilot will also put
the decoder in monaural. In stereo, the co-channel input is
MOTOROLA ANALOG IC DEVICE DATA
disabled, and co-channel or other noise is detected by
negative excursions of the I DET, as mentioned earlier. When
these excursions reach a level caused by approximately 20%
modulation of co-channel, the lock detector puts the system
in monaural, even though the PLL may still actually be
locked. This higher level of co-channel tolerance provides
the hysteresis to prevent chattering in and out of stereo on a
marginal signal.
When all inputs to the Pilot Decode block are correct, and
it has completed its count, it turns on the Switch, sending the
L - R to the Matrix, and switches the pilot lamp pin to a low
impedance to ground.
Summary
It should be noted that in C-QUAM®, with both channels
AM modulated, the noise increase in stereo is a maximum of
3.0 dB, less on program material. Therefore, this is not the
major concern in the choice of monaural to stereo switc!'ling
point as it was in FM, and blend is not needed.
PIN FUNCTION DESCRIPTION
Pin
Description
1,2
Detector Filters, Rout 4.3 k, recommend 0.0033 IlF
to VCC to filter 450 kHz components.
=
3
IF Signal Input
4
Level Detector filter pin, Rout 8.2 k, 10 IlF to ground
sets the AGC time constant. High impedance output,
needs buffer.
5
Error Amp compensation to stabilize the Var Gain
feedback loop
6
VCC, 6.0 to 10 Vdc, suitable for low Vbat automotive
operation, but must be protected from "high line"
condition.
7,8
=
Left and Right Outputs, NPN emitter-followers
9
Forced Monaural, MOS or TTL controllable
10
Lock detector filter, Rout
to ground
11
AGC'd Q output, NPN emitter-follower with 400 g
from emitter to Pin 11
=27 k, recommend 2.2 IlF
12
C~hannel
13
Pilot Filter input to op amp, see Figure 8.
14
Pilot Decode Input (op amp output) emitter-follower,
Rout 100 g
15
Stereo Lamp, open-collector of an NPN common
emitter stage, can sink 50 rnA, Vsat 0.3 V at
5.0 rnA.
input, 2.0 k series in and 47 k feedback
=
=
16
Ground
17
Oscillator input, Rin
Pin 18 or ground.
18
Oscillator feedback, NPN emitter, Rout
19
Phase Detector output, current source to filter.
20
Detector Filter, Rout 4.3 k, recommend 0.0033 IlF
to VCC to filter 450 kHz.
=10k, do not DC connect to
=100 g
=
9-79
MC13020
Figure 5. Ceramic VCO
Figure 6. L-C VCO
5.5
~
~
z
~ 4.5
a:
ttl
.1'20
5.0
Cl
~
~
4.0
~f}i~~
4.5 580
0.0033 30
:::l
Q.
4.0
;;:;
3.51--.....'--:01"'~'+--+-----11---+--+---1
~
/'"
3.5
I
3.0
447
448
449
450
451
452
453
454
446
447
~
5.0
u.i
4.5
~ 4.0
~
F
r
-:-
:::l
Q.
;;:;
II
./
TIL
9
Bus O-....--4i(;---...........=.O
MCl3020
./
".
1.2k
~
~
L
3.5
3.0
454
V
c
O.1"F
24
453
/
17
MHz
~
~
18
+~
I
22"F
z
a:
Cl
19
20
448 449 450 451 452
VCO 7- 8 FREQUENCY (kHz)
Figure 8. Forced Monaural
Optional Delay Circuit
Figure 7. Crystal VCO
1
./
/
./
/
VCO 7- 8 FREQUENCY (kHz)
~
220
~
~
5.5
J
I
I
17
18
100
u.i
>!i
19
I
449.90
449.95
450.00
450.05
450.10
VCO 7- 8 FREQUENCY (kHz)
Figure 9. Active Bandpass Filter
~~
.
Rb
Re--~
7t lo C
Rc
Ra-~
C
+
VRel
2Ao
RaRe
Rb = 4Q2Ra-Re
Rc ±1%
C±5%
Ra±S%
Rb±1%
0.471lF
4.7k
910
220 k
8.2.k
1.3 k
330k
O.33IlF
NOTE: Capacitor C should be a good grade. low ESR.
Where in this application: fO = center Irequency = 25 Hz
Ao = gain at 10 ~ 25
Q~10
Choose values lor '0.
9-80
Ao. Q. and convenient C. solve lor resistors.
MOTOROLA ANALOG IC. DEVICE DATA
®
MOTOROLA
MC13022
Advanced Medium Voltage
AM Stereo Decoder
The MC13022 is designed for home, portable and automotive AM stereo
radio applications. The circuits and functions included in the design allow
implementation of a full-featured C-QUAM® AM stereo radio with relatively
few, inexpensive external parts. It is available in either 28-lead DIP or EIAJ
compatible wide-bodied 28-lead SOIC.
C-QUAM ADVANCED
MEDIUM VOLTAGE
AM STEREO DECODER
SEMICONDUCTOR
TECHNICAL DATA
• Operation from 4.0 V to 10 V Supply with Current Drain of 18 mA Typ
• IF Amplifier with Two Speed AGC
• Post Detection Filters that Allow Manual or Automatic Adjustable Audio
Bandwidth Control and 9.0 or 10 kHz Notch Filtering
• Signal Quality Controlled Stereo Blend and Noise Reduction
• Noise and Co-Channel Discriminating Stop-On-Station
PSUFFIX
PLASTIC PACKAGE
CASE 710
• Signal Strength Indicator Output for RF AGC and/or Meter Drive
• Signal Strength Controlled IF and Audio Bandwidth
• Noise Immune Pilot Detector Needs no Precision Filter Components
• MC13023 Complementary Tuning System IC
DWSUFFIX
PLASTIC PACKAGE
CASE 751F
(S0-28L)
PIN CONNECTIONS
IDet
EnvDet
Decoder Input
L-R Det
Ref
QOut
AGC
Simplified Application
VCC
Loop Riter
IF Input
SSRFAGC
Left Audio
Right Audio
Blend
GND
Filtered Left Out
Left Notch In
Stereo Lamp
Feedback
Osc Feedback
Oscln
Unfiltered Lout
Pilot Lamp
Unfiltered Rout
Pilot Det In
Feedback
Right Notch In
I Pilot
QPilot
Filtered Right Out
Filter Control
(Top View)
ORDERING INFORMATION
Fast AGC Control
I--_ _ _ _ _~Stop Sensei
RFAGCI
Meter DRive
Device
MC13022P
MC13022DW
MOTOROLA ANALOG IC DEVICE DATA
Operating
Temperature Range
TA
=- 40° to +85°C
Package
Plastic Power
S0-28L
9-81
MC13022
MAXIMUM RATINGS
Rating
Symbol
Value
VCC
12
Vdc
Stereo Indicator Lamp Current (Pin 21)
-
30
mAdc
Operating Ambient Temperature
TA
-40 to +85
°c
Tstg
-65 to +.150
°c
TJ(max)
150
°C
Po
1.25
10
W
mWrC
Power Supply Input Voltage
Storage Temperature Range
Operating Junction Temperature
Power Dissipation
Derate above 25°C
NOTE:
Unit
ESO data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 8.0 V, TA = 25°C, Test Circuit 01 Figure 1, unless otherwise noted.)
Min
Typ
Max
Power Supply Operating Range
Characteristic
4.0
8.0
10
Vdc
Supply Line Current Drain (Pin 25)
11·
16
22
mAde
Minimum Input Signal Level, Unmodulated lor Full Operation (Pin 5)
-
5.0
-
mVrms
Audio Output Level, 50% Modulation, L only or R only (Pins 10, 11)
Stereo
100
140
180
mVrms
Audio Output Level, 50% Modulation (Pins 10, 11)
Monaural
50
70
90
mVrrns
-
0.3
0.5
0.5
2.0
Channel Separation, L only or R only, 50% Modulation
Stereo
22
35
-
dB
Pilot Acquisition Time Following Blend Reset to 0.3 Vdc
-
-
600
ms
300
-
n
-
200
mVdc
-
-
1.0
IlAde
Output THO, 50% Modulation
Monaural
Stereo
II
Unit
%
..
.
Audio Output Impedance at 1.0 kHz (Pins 7,14)
Stereo Indicator Lamp Pin
Saturation Voltage at 3.0 rnA Load Current (Vsat Pin 21)
Stereo Indicator Lamp Pin
Leakage Current (Pin 21)
Notch Filter Control (Pin 15), Response versus Voltage
9-82
(See Figure 2)
MOTOROLA ANALOG IC DEVICE DATA
MC13022
Figure 1. Test Circuit
VCC
2.2k
2.2k
~.001
0.0011 0.001 1
J:
J
L-R
Det
27
IDet
28
Q
Out
loop +
BlenJ+
Rh
24
23
Vcc
25
26
J20 llF
47"F
~
~
f-LED
Stereo
lamp
21
Gnd
22
,. ...........
i\OllF
10"F~t
Pilot
I
17
M~P
Pilot
Q
16
Pilot
Detector
Rher
Control
15
I
VCO
Geir>-Controiled L-R
Envelope L+R
IF Out
T
PilotDet
Input
18
-I
r-
0.001
Osc
In
19
J
Decoder
2
Decoder
Input
-ja'~~~
Osc
Fbk
20
Signal
Quality
Detector
~
1
Env
Det
~
0.22
~
3
Ret
~
+
7
1
8
10
L
9
~out
43k
0 01
.
10k
:r
40
Buffer
11
R
Out
12
43k
13
1~4043k
21.5k
21.5k
Fihered
Left
Output
lOOk
~t-~~o
~t-~t-
+
0',1
0.1
I
~
MOTOROLA ANALOG IC DEVICE DATA
14
43k
IF
Input
1.0mH
120
6
I
Filte~~
Buffer
5
~
Yf--<
~r05AmP
~
10 llFJ
Matrix
I
~~
4
AGC
~I
RFAGC,
Stop Sense,
SSMeter
Tl - Ceramic Resonator muRata
CSA 3.60 MGF103
L2 - Miller 923()""92
Fihered
Right
Output
II
MC13022
EXPLANATION OF FEATURES
Blend and Noise Reduction
Although AM stereo does not have the extreme difference
in SIN between mono and stereo that FM does (typically less
than 3.0 dB versus greater than 20 dB for FM), sudden
switching between mono and stereo is quite apparent. Some
forms of interference such as co-channel have a large L-R
component that makes them more annoying than would
ordinarily be expected for the measured level. The MC13022
measures the interference level and reduces L-R as
interference increases, blending smoothly to monaural. The
pilot indicator remains on as long as a pilot signal is detected,
even when interference is severe, to minimize annoying pilot
light flickering.
RF AGClMeter Drive
A dc voltage proportional to the log of signal strength is
provided at Pin 6. This can be used for RF AGC, signal
strength indication, and/or control of the post detection filter.
Normal operation is above 2.2 V as shown is Figure 4.
Stop Sense
Multiplexed with the signal strength information is the stop
sense signal. The stop sense is activated when scanning by
externally pulling the blend capacitor on Pin 23 below 0.5 V.
This would typically be done from the mute line in a frequency
synthesizer.
If at any time Pin 23 is low and there is either no signal in
the IF or a noisy signal of a predetermined interference level,
Pin 6 will go low. This low can be used to tell the frequency
synthesizer to immediately scan to the next channel. The
interference detection prevents stopping on many
unlistenable stations, a feature particularly useful at night
when many frequencies may have strong signals from
multiple co-channel stations.
IF Bandwidth Control
IF AGC attenuates the signal by shunting the signal at the
IF input. This widens the IF bandwidth by decreasing the
loaded Q of the input coupling coil as signal strength
increases.
Post Detection Filtering
With weak, noisy signals, high frequency rolloff greatly
improves the sound. Conventional tone controls do not
attenuate the highs sufficiently to control noise without also
significantly affecting the mid-range. Also, notch filters are
necessary with any wide-band AM radio to eliminate the
10 kHz whistle from adjacent stations.
By using a twin-T filter with variable feedback to the
normally grounded center leg, a variable Q notch filter is
formed that provides both the 10 kHz notch and variable high
frequency rolloff functions. Typical range of response is
shown in Figure 3. Response is controlled by the dc voltage
on Pin 15.
Pin 15 could interface with a dc operated tone control such
as the TDA1524, or could be tied to Pin 6 for automatic audio
bandwidth control as a function of signal strength.
II
MOTOROLA ANALOG IC. DEVICE QATA
MC13022
Figure 2. High Performance Home Type AM Stereo Receiver
VCC
TOKOPartNo.
MF292BC--1349Z
0.001
20
Osc
Feedbk
MC13022
IF
Input
5
SS
RFAGC
6
Out
Left Notch
In
FBK
7
Unfi"ered
Rout
11
Lout
10
9
8
Right Notch
In
OUt
13
14
FBK
12
r
I
I
I
I
I
IL
To
Signal
Strength
See
MCl3025
Data Sheet
for
Alternate
Approach
Meter
I
I
I
I
I
I
_ _ _ _ _ _ _ _ _ _ _ _ .JI
TOKOPartNo.
THB-122
Tuning Line
From Synthesizer
I
I
~II
,!II..,.
. ..,.
I
-. .-
T1 - Ceramic Resonator muRata
CSA 3.60 MGF1 03
-. .
- .- I
L ____~e:.. _______ ~sc~~ __1
Figure 3. Overall Selectivity of a Typical Receiver
versus Filter Control Voltage
J l
o
iD -10
:!;!.
lli
-20
~
-30
z
l!!-40
~ -50
~ -eo
0 _70
-eo
j.= ~
Vat in 15 = 3~5 Vdcr:7'- ~
,#
d,5VcJd/
I
1.5Vdc
I
esponselat
Pins 10 and 11 Due
to IF Selectivity
_ Total Response at
Output Pins 7 and 14
1.5
--
I
2.0
3.0
Figure 4. RF AGClSignal Strength Output
versus Input Signal
....
Signal
_ 5.0
......
,:\
,:,
:,
"-
'I
~
,
a:
~
:~
::;;
' ....
F
.c::::-'
MOTOROLA ANALOG IC DEVICE DATA
5
10k 0.Q1
2
rt-
3
n.
I
6
RF AGC
..,. 0.Q1
Y
Zo = 13 k
r£ 4.0
~
u
II:
20
/'
~ 3.0
2.0
30
-
1.0
i;"~
L~l00ki SSMeter
L_:J
<0
Z
I
4.0 5.0 6.0 8.0 10
15
AUDIO FREQUENCY (kHz)
I
I~
,/
""
.....
3.0
10
30
100 300
SIGNAL INPUT, 10 kQ TO PIN 5 (mVnms)
1.0 k
9-85
®
MOTOROLA
MC13022A
Advance Information
Advanced Medium Voltage
AM Stereo Decoder
The MC13022A is designed for home and automotive AM stereo radio
applications. The circuits and functions included in the design allow
implementation of a full-featured G-QUAM® AM stereo radio with relatively
few, inexpensive external parts. It is available in either 28-lead DIP or EIAJ
compatible wide-bodied 28-lead SOIC. Functionally, the MC13022A and
MC13022 are very similar. The MC13022A has 10 dB more audio output and
a CMOS compatible logic level output (Pin 15) for stop sense. The SlOP
sense/AGC function has been internally connected to the output notch filter
'
control.
C-QUAM ADVANCED
MEDIUM VOLTAGE
AM STEREO DECODER
SEMICONDUCTOR
TECHNICAL DATA
• Operation from 6.0 V to 10 V Supply with Current Drain of 20 rnA Typ
• IF Amplifier with Two Speed AGC
• Post Detection Filters that Allow Automatic Adjustable Audio Bandwidth
Control and Notch Filtering (9.0 or 10 kHz)
PSUFFIX
PLASTIC PACKAGE
CASE 710
• Signal Quality Controlled Stereo Blend and Noise Reduction
• Noise and Co-Ghannel Discriminating Stop-On-8tation
• Signal Strength Indicator Output for Stop Sense and/or Meter Drive
• Signal Strength Controlled IF and Audio Bandwidth
DWSUFFIX
PLASTIC PACKAGE
CASE 751F
(S0-28L)
• Noise Immune Pilot Detector Needs no Precision Filter Components
• MC13025 Complementary Electronically Tuned Radio Front End
• CMOS Compatible Driver for Stop Sense
II
PIN CONNECTIONS
IDet
EnvDet
Decoder Input
Re!
L-R Det
QOut
Vee
AGC
IF Input
Simplified Application
Loop Fiijer
SS
Blend
GND
Filtered Left Out
Left Notch In
Feedback
Pilot Lamp
Stereo Lamp
Osc Feedback
Oscln
UnfiRered Lout
Unfiltered Rout
Feedback
Right Notch In
Filtered Right Out
PiiotOetln
I Pilot
QPilot
CMOSSSOut
(Top View)
Signal
Strength
Controlo!
Audio Filters
~
Fast AGC Control
9-86
__________~CMOS
(Logic)
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
Plastic Power
MC13022AP
MC13022ADW TA = - 40° to +85°C
S0-28L
MOTOROLA ANALOG IC DEVICE DATA
MC13022A
MAXIMUM RATINGS
Rating
Power Supply Input Voltage
Symbol
Value
VCC
12
Vdc
-
30
mAde
TA
-40 to +85
°C
Tstg
--65 to +150
°C
TJ(max)
150
°C
Po
1.25
10
W
mW/oC
Stereo Indicator Lamp Current (Pin 21)
Operating Ambient Temperature
Storage Temperature Range
Operating Junction Temperature
Power Dissipation
Derate above 25°C
Unit
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 8.0 V, TA = 25°C, Test Circuit of Figure 1, unless otherwise noted.)
Min
Typ
Max
Power Supply Operating Range
6.0
8.0
10
Vdc
Supply Line Current Drain (Pin 25)
10
20
25
mAde
Characteristic
Unit
-
5.0
-
mVrms
Audio Output Level, 50% Modulation, L only or R only (Pins 10, 11)
Stereo
290
400
530
mVrms
Audio Output Level, 50% Modulation (Pins 10, 11)
Monaural
140
200
265
mVrms
-
0.8
1.6
Minimum Input Signal Level, Unmodulated for Full Operation (Pin 5)
Output THO, 50% Modulation
Monaural
Stereo
%
-
0.3
0.5
Channel Separation, L only or R only, 50% Modulation
Stereo
22
35
-
dB
Pilot Acquisition Time Following Blend Reset to 0.3 Vdc
-
-
600
ms
Audio Output Impedance at 1.0 kHz (Pins 7,14)
-
300
-
Q
Stereo Indicator Lamp Pin
Saturation Voltage at 3.0 rnA Load Current (Vsat Pin 21)
-
-
200
mVdc
Stereo Indicator Lamp Pin
Leakage Current (Pin 21)
-
-
1.0
J1Adc
Oscillator Capture Range
-
±3.0
-
kHz
I
II
I
MOTOROLA ANALOG Ie DEVICE DATA
9-87
MC13022A
Figure 1. Test Circuit
From
Tuning System
LogicVCC
(5.0 V)
vCC
3.0k
2.2k
0.001
~.OOI
0.001
3.9k
J
L-R
Del
27
IDet
28
Q
Out
26
471lF~
~ 20llF
Loop + ~+
Blend
Filt
24
23
Vee
25
LED
Stereo
Lsmp
21
22
IF Out
~~
Det
0.001
2
Decoder
Input
3
Ref
~
4
AGC
5
+
10 llFJ
~
II
1.0mH
Yf-;
120
+
10 F
Signal
Strength
Output
I'---
3.0V
1
47k
J
I
"I
6
Envelope L+R
J
Pilot
Detector
Matrix
8
9
43k
0 01
.
10k
10
-=-
J
370
riM
12
11
rf.740
43k
13
14
4O
r f :43k
21.5k
~~O
370
LOutput
I
15
Buffer
21.5k
Filtered
Left
Output
lOOk
O.Q1J
I
43k
IF
Input
Stop
Sense
".c<}~
Buffer
1
1
0.4;f
Pilot
Q
·161
Pilot
I
171
To CMOS
Logic
veo
~~~
7
~
10~:j
Gain-Controlled L-R
'I
Env
PiiotDet
InDut
18
L
Decoder
r-
Osc
In
19
Osc
Fbi<
20
±+0.68
'OOu
, .......... ~D~+~1
*
Signal
Quality
Detector
JI
-
Gnd
W
0.33
r
~;O
Fiftered
Right
Output
R Output
Stop Sense,
SSMeter
Tl - Ceramic Resonator muRata
CSA 3.60 MGF103
L2 - Miller 9230-92
NOTES: 1. 01 is switched on when Ihe Blend Pin 23 is extemally held low and the signal is weak or has 110%
negative modulalion. In Ihis condijion 01 pulls Pin 6 low (0.25 to 1.3 V). At all other limes, Pin 6 follows
the curve in Figure 4.
2. 02 (Pin 15) is swilched on when Pin 6 vonage is below 1.7 V. Q2 could Ihen be used as a logic output
10 I~e luning syslem, lelling the luning system to conlinue searching for a good signal.
3. User is c~utioned not 10 require more than 1.0 mA from Pin 6.
9-88
MOTOROLA ANALOG IC DEVICE DATA
MC13022A
EXPLANATION OF FEATURES
Blend and Noise Reduction
Although AM stereo does not have the extreme difference
in SIN between mono and stereo that FM does (typically less
than 3.0 dB versus greater than 20 dB for FM), sudden
switching between mono and stereo is quite apparent. Some
forms of interference such as co-channel have a large L-R
component that makes them more annoying than would
ordinarily be expected for the measured level. The
MC13022A measures the interference level and reduces
L-R as interference increases, blending smoothly to
monaural. The pilot indicator remains on as long as a pilot
signal is detected, even when interference is severe to
minimize annoying pilot light flickering.
'
Signal Strength
A dc voltage proportional to the log of signal strength is
provided at Pin 6. This can be used for signal strength
indication, and it directly controls the post detection filter.
Normal operation is above 2.2 V as shown is Figure 4.
Stop Sense
The signal strength information is multiplexed with the stop
sense signal. The stop sense is activated when scanning by
externally pulling the blend, Pin 23, below 0.3 V. This would
typically be done from the mute line in a frequency
synthesizer.
If at any time Pin 23 is low and there is either no signal in
the IF or a noisy signal of a predetermined interference
level, Pins 6 and 15 will go low. This low can be used to tell
the frequency synthesizer to immediately scan to the next
channel. The interference detection prevents stopping on
many unlistenable stations, a feature particularly useful at
night when many frequencies may have strong signals from
multiple co-channel stations. Pin 6 drives a comparator
which has a 1.7 V reference. Therefore the comparator
output, Pin 15, is low if Pin 6 is <1.7 V and high if Pin 6 is
>1.7 V.
IF Bandwidth Control
IF AGC attenuates the signal by shunting the signal at the
IF input. This widens the IF bandwidth by decreasing the
loaded Q of the input coupling coil as signal strength
increases.
Post Detection Filtering
With weak, noisy signals, high frequency rolloff greatly
improves the sound. Conventional tone controls do not
attenuate the highs sufficiently to control noise without also
significantly affecting the mid-range. Also, notch filters are
necessary with any wide-band AM radio to eliminate the
10kHz whistle from adjacent stations.
By using a twin-T filter with variable feedback to the
normally grounded center leg, a variable Q notch filter is
formed that provides both the 10kHz notch and variable high
frequency rolloff functions. Typical range of response is
shown in Figure 3. Response is controlled by Pin 6 for
automatic audio bandwidth control as a function of signal
strength.
II
MOTOROLA ANALOG IC DEVICE DATA
9-89
MC13022A
Figure 2. High Performance Home Type AM Stereo Receiver
From
Mute Line
LogiCVCC
(5.0 V)
Vee
TOKO Part No.
MF292SC-1349Z
To
Tuning
System
15
CMOS
SSOut
MC13022A
Out
7
Left Notch
In
FBK
B
9
Unfiltered
Rout
lout
10
11
FBK
12
Righi Notch
In
Out
13
14
r
To
Signal
Strength
Meter
See
MC13025
DataShee1
for
Alternate
Approach
,
I
I
I
I
I
I
I
I
I
IL
1
I
_ _ _ _ _ _ _ _ _ _ _ _ ...l
TOKO Part No.
THB-122
Tuning Line
From Synthesizer
1
1
g.11
1
.3 . . .
_____ I
..
... 1
L ____~e~ _ _ _ _ _ _ _ ~~~ _ _1
ill
T1 - Ceramic Resonator muRata
CSA 3.60 MGF1 03
T2 - Broad Resonance @ 450 kHz
Effective Rp of 8.0 k to 12 k
(TOKO 7NRES-T13704)
Figure 3. Overall Selectivity of a Typical Receiver
versus Filter Control Voltage
Figure 4. Strength Output versus Input Signal
J l
t),: tor--.
Pin 6 = 31.5 Vdc~ )l: ~r-.
rg -10
W-20
CI)
~=:
~ -50
~ -60
d.5Vdd//
I
1.5Vdc
I
esponse1at
Pins 10 and 11 Due
to IF Selectivity
Total Response at
Output Pins 7 and 14
--
0-70 _
-80
I
1.5
9-90
2.0
3.0
,;r [".,[\
-~ 5.0
~.
Signal
.... ,
I
10k 0.Q1
1i:
\1\ .c::::.
3
6
en
en
uj
"
~
CI)
./
3.0
ter
SSMe
,/
~ 4.0
"
I
~ 0.Q1
Zo = 13 k
~
~
'"
~
Do
f2
CI)
1
4.0 5.0 6.0 8.0 10
15
AUDIO FREQUENCY (kHz)
2
r+.1l.
L~100kj,_
L_:J
a:
I' , 1'1""'
5
I~!::!
z'"
20
2.0
30
~
1.0
.....
3.0
10
30
100 300
SIGNAL INPUT, 10 k.Q TO PIN 5 (mVnns)
1.0k
MOTOROLA ~NALOG IC DEVICE DATA
®
MOTOROLA
MC13025
Electronically Tuned Radio
Front End
ETR® FRONT END for
C-QUAM® AM STEREO
The MC13025 is the complementary ETR® Electronically Tuned Radio
front-end for the second generation MC13022 C-QUAM® AM stereo IF and
decoder. The MC13025 provides a high dynamic range mixer, voltage
controlled oscillator, and first IF that with the MC13022 and synthesizer form
a complete digitally controlled AM stereo tuner system. This system in turn
may drive a dual channel audio processor and high power amplifiers for car
radio or home stereo applications. Other applications include portable radio
"boom boxes", table radios and component stereo systems.
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
PLASTIC PACKAGE
CASE 648
• Operates Over a Wide Range of Supply Voltages: 6.0 VCC to 10 VCC
• Wideband AGC Voltage to RF Amp for Extended Dynamic Range
~
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0--16)
• Buffered VCO Output to Frequency Synthesizer
• No External RF Amp Needed for Most Home Stereo and
Portable Radios
.
16~-
• IF Drive Output Matches the MC13022 for Optimum Performance
PIN CONNECTIONS
.'. VCO Operates at Four Times Local Oscillator Injection Frequency
Vce 1
Wi~~~~
ORDERING INFORMATION
Device
MC13025D
Operating
Temperature Range
TA = _40° to + 85°C
2
I
Package
II
S0--16
Plastic DIP
MC13025P
!
(Top View)
Simplified Block Diagram
I
I
I
I
I
I
I
I
I
I
I
I
MC13025
L--------r-====;
Right Channel
MC13022
Variable Bandwidth IF
Amplifier with Notch Filter
and C-QUAM® AM
Stereo Decoder
Audio Out
Left Channel
__ -1
Varactor
Tuned
Circuit
Stereo Indicator
This device contains 93 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
9-91
MC13025
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
12
Vde
TA
-40 to +85
°C
Storage Temperature
Tstg
-65to+15Q
°C
Junction Temperature
TJ
150
°C
Power Dissipation
Derate above 25°C
PD
1.25
10
W
mW/oC
Supply Voltage
Ambient Operating Temperature
ELECTRICAL CHARACTERISTICS (TA = 25°C, 8.0 VCC test circuit as shown in Figure 2.)
Pin
Min
Typ
Max
Unit
Supply Current
1
7.0
8.2
10
mAde
3.0 V Ref, Current In
7
-SO
7.0
90
!lAde
1.2
mAde
Characteristics
IF Out DC Current
8
0.9
1.05
Mixer DC Current Output
4
0.70
0.77
0.82
mAde
IF Output Amplitude, RF Input
@1.7MHz,31.6mV
8
270
330
390
mVrms
Local Oscillator Output
10
160
181
220
mVrms
Wideband AGC Pull-Down Current
16
0.5
1.0
1.5
mAde
1000
2500
-
0
z
UJ
--'
m
1
1
:1
1[
(!)
.......
32
3.0
-
1.0
'"
".V
24
!;(
a:
ct
UJ
I
16
/
en
II
8.0
20
30
NOTE:
::9z
Q
40
50
60
ANTENNA INPUT (dBIo1V)
70
80
II
20
The graphs on this page were made using the t 5160 pF
dummy antenna and the Application Circuit 01 Figure 6.
30
NOTE:
70
40
50
60
ANTENNA INPUT (dBIo1V)
80
The radio stays in mono until the stereo signal is
sufficiently large and then maKes a smooth transition to
stereo. This is similar to FM receivers with variable
blend.
Figure 13. 5.0 kHz Attentuation
versus RF Input Level
Figure 12. Signal to Noise versus RF Input Level
50
.,., , /
42
m
::9-
34
ijj
N
:I:
<:>
/
26
~
!;( -10
:::>
z
UJ
~
20
".,
C!
'"
30
NOTE:
-15
N
:I:
V
10
/
Q
/
18
II
/.
/
~ -5.0
z
V
40
50
60
ANTENNA INPUT (dBIo1V)
70
".
-20
.,.,V "
V
V
-25
80
20
The slightly abrupt change at around 25 dB~V is due
to the decoder switching into stereo.
30
NOTE:
Figure 14. Audio Output Level
versus RF Input Level
70
40
50
60
ANTENNA INPUT (dBIo1V)
This curve shows the effect 01 the variable audio
bandwidth control 01 the MCt3122. It is due to the
variable loading 01 the IF coil and the variable 10kHz
notch Iliter in the output.
Figure 15. Stop-Sense Voltage
versus RF Input Level
500
4.0
.",
400
.§.. 300
I
t--
:::>
"-
'3
0
u..
""
~
v-
:>
200
co
z
uI
en
z
UJ
:f
NOTE:
u)
en
30
40
50
60
ANTENNA INPUT (dBIo1V)
70
80
All the curves 01 performance versus RF input level
were generated using the car radio receiver circuit
shown in Figure 6. Using a 15160 pF dummy antenna
input and a 50% L only stereo signal.
9-114
2.0
12
en
I
20
3.0
Pin23=( pen
1[
I
1
100
80
1.0
~
~
---
~
~
l/
".
--
~
fin 23 = Grounded
II
60
NOTE:
70
80
90
RF INPUT LEVEL (dBIo1V)
100
110
This measurement was made on the MC13122 alone
with a 10k series input resistor. It will enable the
designer to determine the stop-sense level the gain
01 receiver RF section is known. Note that il Pin 23 is
held low. the 88 voltage on Pin 6 rises lrom about 0.3
to 2.2 V over a small change in RF level. This can be
used to generate a very reliable stop signal. II Pin 23 is
not held low. the 88 voltage starts out at 2.2 V and
rises slowly to a maximum 01 around 4.0 V.
n
MOTOROLA ANALOG IC DEVICE DATA
MC13027 MC13122
Figure 16. Audio Blanking Delay versus R17
1000
'" -
U>
.:;
S
w
100
o
(!)
z
,.,..
52
z
~
U>
.=;,
w
::i!
100
;::
z
z
52
~
w
10
[.,.00'
Figure 19. WB AGC Oulpul Voltage (Pin 20)
versus RF Input Level
Figure 18. Audio Blanking Time versus R19
::i!
--
(!)
./"
10
Figure 17. RF Blanking Time versus R15
1000
10
33
100
R19 (kO)
330
1000
0
1.0
2.0
3.0
4.0
"'" '"
5.0
6.0
RF LEVEL INTO PIN 1 (mV)
NOTE: This was measured by applying an RF signal through
a capacitor directly to Pin 1. The input resistanoe is
15 k. so the desired threshold can be increased by
adding a resistor in series wnh the input.
MOTOROLA ANALOG IC DEVICE DATA
9-115
II
MC13027 MC13122.
AMAX STEREO CHIPSET
power supply connections. This modification is described
below. Motorola will work with TOKO to develop a new part
number incorporating this change. In the meantime, it is
necessary that the user perform these simple changes,
because the radio circuits throughout this data sheet assume
this modified design.
The RF Module
In the early development phase of this AMAX Stereo
Chipset, Motorola worked with TOKO America Inc. to
develop an RF tuning module. Part number TMG522E was
assigned and is available from TOKO now. This module
provides the "tracked" tuning elements for the RF (T1 and T2
and associated capacitors and varicaps) and the VCO (T3 et
al). Some radio designers may prefer to develop their own
tuning system using discrete coils and components, but the
TOKO approach offers good performance, compactness and
ease of application. Motorola recommends that every
designer use this approach at least for initial system
development and evaluation.
As refinement of the application progressed, it was found
that a modification of the TMG522E was needed which would
reduce the amount of VCO leakage into the Mixer through the
Modifying the TMG522E
Referring to Figures 20 and 21, there are three simple
steps to the modification:
1. Cut the thin copper trace from Pin 2 to Pin 5 as shown.
2. Cut the thin copper trace from Pin 8 to the bottom of the
120 g resistor. Removal of the resistor is optional.
3. Connect a wire from Pin 5 to the top of the 120 g resistor
(or the upper pad for the resistor).
Figure 20. TMG522E Schematic
Add
Cut
race (2)
Wire (3)
4
5
RFOut
3.9k
i
[
120
3.0 V 80sc
Low
7
Osc
High
T3~----.J
I
=/
CutTrace (1)
+B
5
Figure 21. TMG522E Physical Modifications
TMG522E
Add Wire (3)
Cut (2)
Cut (1)
87654321
9-116
MOTOROLA ANALOG IC DEVICE DATA
MC13027 MC13122
Figure 22. AMAX Chipset Printed Circuit Board
(Top View)
Figure 23. AMAX Chipset Printed Circuit Board
(Bottom View)
II
MOTOROLA ANALOG IC DEVICE DATA
9-117
MC13027 MC13122
Figure 24. AMAXCh·Ipset Printed C·
(Copper View)
Ircuit Board
9-118.
.
MOTOROLAANALOGIC DEVICE
DATA
®
MOTOROLA
MC13028A
Advanced Wide Voltage
IF and C-QUAM® AM
Stereo Decoder
The MC13028A is a third generation C-QUAM stereo decoder targeted
for use in low voltage, low cost AM/FM E.T.R. radio applications. Advanced
features include a signal quality detector that analyzes signal strength,
signal to noise ratio, and stereo pilot tone before switching to the stereo
mode. A "blend function" much like FM stereo has been added to improve
the transition from mono to stereo. The audio output level is adjustable to
allow easy interface with a variety of AM/FM tuner chips. The external
components have been minimized to keep the total system cost low.
C-QUAM AM STEREO
ADVANCED WIDE VOLTAGE
IF and DECODER
for E.T.R. RADIOS
SEMICONDUCTOR
TECHNICAL DATA
• Adjustable Audio Output Level
• Stereo Blend Function
• Stereo Threshold Adjustment
PSUFFIX
PLASTIC PACKAGE
CASE 648
• Operation from 2.2 V to 12 V Supply
• Precision Pilot Tone Detector
• Forced Mono Function
• Single Pinout VCO
• IF Amplifier with IF AGC Circuit
• VCO Shutdown Mode at Weak Signal Condition
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
The purchase of the Motorola C-QUAM® AM Stereo Decoder does not carry with such purchase any license by implication, estoppel or otherwise, under any patent rights of Motorola
or others covering any combination of this decoder with other elements including use in a
radio receiver. Upon application by an interested party, licenses are available from Motorola
on its patents applicable to AM Stereo radio receivers.
II
PIN CONNECTIONS
Representative Block Diagram
16
12
15
o
11
10
0
9
o
Stereo
Threshold Adjust
AGCBypass
Riter
IF Feedback
Bypass
Right Channel
Output
Left Channel
Output
Loop Riter
VCOOutput
IF Signal Input
Gnd
VCC
Stereo
Indicator Drive
Input
Pilot Signal
Pilot Q Detector
Output
Pilot I Detector
Output
1.0V
Reference
Blend
--;---if~ --~
2
4
5
6
7
ORDERING INFORMATION
Device
MC13028AD
MC13028AP
Operating
Temperature Range
TA = -25° to +70°C
Package
S0-16
DIP-16
This device contains 679 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
9-119
MC13028A
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Input Voltage
Symbol
Value
Unit
VCC
14
Vdc
°c
Operating Junction Temperature
TJ
150
Operating Ambient Temperature
TA
-25 to +70
°C
Storage Temperature Range
Tstg
-55 to +150
°C
LED Indicator Current
ILED
10
mA
ELECTRICAL CHARACTERISTICS (VCC = 8.0 Vdc, TA = 25°C, Input Signal Level = 74 dBItV, Modulation = 1.0 kHz
@ 50% Modulation, unless otherwise noted.)
Characteristic
Max
-
9.0
11
11
22
150
80
44
250
180
-
33
200
130
50
35
340
80
460
106
580
THD1
THD2
THD3
-
0.6
0.3
-
1.8
0.6
1.5
LorR
23
35
-
dB
Yin
-
33
-
dBItV
-
0.25
0.3
-
Audio Output Level, L+R, Mono Modulation
RO = 1.8 k, VCC = 2.2 V, Input 55 dBItV
RO = 10k, VCC = 8.0 V, Input 50 dBItV
Input 40 dBItV
Input 31 dBItV
Vout
Audio Output Level, L or R Only, Stereo Modulation
RO = 1.8 k, VCC = 2.2 V, 55 dBItV Input
RO= 10 k, VCC = 8.0 V
Vout
Channel Separation
50% Lor R Only
Decoder Input Sensitivity
Vout=-10dB
Force to Mono Mode, (Pin 10)
I'
Typ
ICC
OutputTHD
50% Stereo, L or R Only
50% Mono, L+R
90% Mono, L+R, Input 86 dBItV
II
Min
Symbol
Supply Current Drain
VCC=2.2V
VCC=8.0V
Unit
rnA
mVrms
mVrms
%
Stereo Threshold Adjust (Pin 1)
Pin 1 Open
R1 = 15 k (Gnd)
R1 = 680 k (VCC)
STA
Signal to Noise Ratio, RO = 10 k
50% Stereo, L or R Only
50% Mono, L+R
SIN
Input Impedance
(Reference Specification)
Rin
Cin
-
Maximum Input Signal Level for THD :s; 1.5%
-
Blend Voltage
Mono Mode
Stereo Mode
Out of Lock
BI
Vdc
dBItV
55
-
50
55
48
40
40
62
59
-
-
10
8.0
-
kQ
pF
-
-
86
dBItV
0.7
1.20
-
-
dB
-
Vdc
-
1.30
0.12
0.9
1.35
0.2
VCO Lock Range
OSCtun
-
±2.5
-
kHz
AGC Range
AGC mg
-
44
-
dB
C-B
-1.0
-
1.0
dB
-
-
2.5
4.0
%
Channel Balance
Pilot Sensitivity
9-120
MOTOROLA ANALOG IC DEVICE DATA
MC13028A
Standard Test Circuit
Vee
R1
o
R
~-~----~~-oL
~AUdiO
7
OU~~
2.2k
IFin ~---"I------f
0.01 ~F
~----~--------~~~_oVee
Gndo------,.--\
47~F 1:+
Pilot Ind o--..~--------__I
+
0.22~F1:
1------.+
LED
0.47~F
2.2 k
1:
Blend 0--+-------......---1
PIN FUNCTION DESCRIPTION
Pin
Symbol
Internal Equivalent Circuit
DescriptionlExternal Circuit Requirements
Stereo Threshold Adjustment Pin
The function ofthis circuit is to provide the freedom
to achieve a desired value of incoming IF signal level
which will cause full stereo operation of the decoder.
The level can be detemnined by the value of R1 , a
resistor from Pin 1 that can be connected to either
VCC orto ground. This resistor may also be omitted
in some designs (Pin 1 left open). The approximate
dc level with the pin left open is 0.6 Vdc.
2
AGCcap
3
IFFBcap
AGC Filter Bypass Capacitor
An electrolytic capacitor is used as a bypass filter
and it sets the time constant for the AGC circuit
action. The recommended capacitor value is 10 ~F
from Pin 2 to ground. The dc level at this pin varies
as shown in the curve in Figure 13, AGC Voltage
versus Input Level.
Vee
IF Amplifier Feedback Capacitor
A capacitor which is specified to have a low ESR
at 450 kHz is normally used at Pin 3. The value
recommended for this capacitor is 0.47 ~F from
Pin 3 to ground. This component forms a low pass
filter which has a corner frequency around 30 kHz .
.......-+---03
MOTOROLA ANALOG IC DEVICE DATA
9-121
II
MC13028A
PIN FUNCTION DESCRIPTION
Pin
Symbol
4
IFin
Internal Equivalent Circuit
Descriptlon/Extemal CircuH Requirements
IF Amplifier Input
Pin 4 is the IF input pin. The typical input impedance
at this pin is 10k. The input should be ac coupled
through a 0.01 I1F capacitor.
4
10k
t
Vref
5
-::-
Gnd
I
5
Gndl
~
J.
rh
Supply Ground
In the PCB layout, the ground pin should be
connected to the «hassis ground directly. This pin
is the internal circuit ground and the silicon
substrate ground.
Substrate
6
Stereo Indicator Driver
This driver circuit is intended to light an LED or
other indicator when the decoder receives the
proper input signals and switches into the stereo
mode. The maximum amount of current that the
circuit can sink is 10 mAo
SIND
VCC
'r
A current limiting resistor is applied externally to
control LED brightness versus total power supply
current.
30k
-::-
7
VAef
7
Reference
Voltage
1.0V
I
Regulated Voltage. 1.0 V
An electrolytic capacitor used as a bypass fi~er is
recommended from Pin 7 to ground. The capacitor
value should be 10 I1F.
-:!:8
CAPBlend
Blend Cap
Charging
Circutt
VCC
Pilot Indicator
Driver Circuit
8
t
-=Blend
. Algorithm
Circutt
9
Ipilot
I
VCC
Vreg
Blend Capacitor
The value of the capacitor on this pin will effect the
time constant of the decoder blend function. The
recommended value is 10 I1F from Pin 8 to ground.
The de level at Pin 8 is internally generated in
response to input signal level and signal quality. This
pin is a key indicator of the operational state of the Ie
(see text Functional Description). It is recommended
to discharge the blend capacitor externally when
changing stations.
.~
Pilot I Detector Output
The Pilot r Detector output requires a 10 I1F
electrolytic capacitor to ground. The value of this
capacitor sets the pilot acquisition time. The de
level at Pin 9 is approximately 1.0 Vdc, unlocked,
and 1.1 to 2.4 Vdc in the locked condition.
t
-::-
9-122
MOTOROLA ANALOG IC DEVICE DATA
MC13028A
PIN FUNCTION DESCRIPTION
Pin
10
Symbol
Internal Equivalent Circuit
QPilot
Vee 10
11
12
PILOTfil
Vee
Vee
-=-
-=-
Description/External Circuit Requirements
Pilot Q Detector Output
This pin is connected to the Pilot Q detector and
requires a 0.47 IlF capacitor to ground to filter the
error line voltage at the PLL pilot tone detector. If the
value of this capacitor is made too large, the
decoder may be prevented from coming back into
stereo after a signal drop out has been experienced
in the field. The force to mono function is also
accomplished at this pin by pulling the dc voltage
level at the pin below 1.0 V.
Pilot Signal Input
A capacitor to ground forms a filter for the pilot input
, signal. The recommended value of the capacitor is
0,221lF. The dc level at Pin 11 is approximately
1,0Vdc,
Supply Voltage (VCC)
The operating supply voltage range is from 1,8 Vdc
to 12 Vdc.
Vee
Vee
I
12
Vee
13
OSe in
13
Vreg
Oscillator Input
The oscillator pin requires a ceramic resonator and
parallel capacitor connected to ground, The
recommended source for the ceramic resonator is
Murata, part number eSA 3,60MGFI 08,
A 43 pF NPO capacitor is in parallel with the
resonator, The dc level at Pin 13 is approximately
1.1 Vdc.
Vreg
2.2 k
3.0 k
6.3pF
MOTOROLA ANALOG IC DEVICE DATA
15 k
9-123
II
MC13028A
PIN FUNCTION DESCRIPTION
Pin
Symbol
14
lOOPFilter
Internal Equivalent Circuit
Vee
Descrlption/External Circuit Requirements
loop Filter
A capacitor which forms the loop fiRer is connected
from Pin 14 to ground. The recommended value is
471lF in series with 47 n. This capacitor should be of
good construction quality so it will have a very low
spec~ication for leakage current in orderto prevent
stereo distortion. The 47 n resistor in series with the
capacitor controls the Pll corner frequency
response, keeping the response shape critically
damped and not peaked up. The dc level at Pin 14 is
approximately 0.6 Vdc in the locked condition.
Vee
390
Vee
-=-=15
-=left Channel Audio Output
This is the left channel audio output pin from Which
the IC can provide 1.3 !lApp drive current for each
percent of mono modulation. A resistor to ground
sets the level of the audio output.
lEFTout
Vee
Vee
15
a
16
RIGHTout
Vee
For example, 100% (mono mod) x 1.3 !lApp (IC
drive per % mod) ': 130 !lApp flowing through the
load resistor. (For a 2.2 k load, 286 mVpp is then
the output sighal voltage.) When dealing with
stereo signals, multiply the mod level by 2; i.e. 50%
(left only mod) x 2 (stereo factor) x 1.3 !lApp (IC
drive per % mod) = 130 !lApp flowing through the
load resistor.
Right Channel Audio Output
This is the right channel audio output pin. A resistor
to ground sets the level of the audio output. See the
explanation under the left Channel Audio Output
description above.
Vee
16
~124
MOTOROLA ANALOG Ie DEVICE; DATA
MC13028A
Figure 1. Typical Circuit for E.T.R. Applications
NRSC Rol~ff Filter
VCC
~
0.221lF
(Note 4)
15
+~ +~
-:-
Right Output
47 IlF+
Left Output ----_-+--... (Note 1) 47
16
10llF
0.471lF
14
12
-:-
-:Pilot I
Input
9
Pilot 0
Input
10
Pilot
Input
11
I + 471lF
--,
I
Optional
I--'V'o/V-- Force to
Mono
RF AGC'd IF Signal from
Mixer (450 kHz from
Tuner IC Section)
~
Stereo
Threshold Adjust
c:::=:J
T
-:-
L_
III
+
Rl
10
-:-
2
AGe
Bypass
3
IF
Bypass
-I'
0.471l[ O.OlIlF
(Note 5)
-:-
--r-
4
IF
Input
5
Gnd
~
Reg
_...J
6
Stereo
Indicator
+
7
Ref
8
Blend
1
+
-:-
-:-
Scan
Mute
(Note 6)
10 llFI 10 11
-:-
II
-:-
NOTES: 1. The 47 ~F capacitor is recommended to be a low leakage type capacitor. Leakage current due to this capac~or causes
increase in stereo distortion and decreased separation pertormance.
2. The recommended source for this part is Murata Products. CSA3.60MGF10B. The location of this part should be carefully
considered during the layout of the decoder circu~. This part should not be near the audio signal paths, the 25 Hz pilot filter
lines, or the VCC high current lines, and the ceramic element ground line should be direct to the chassis ground lead in order
to avoid any oscillator inter-modulation.
3. The 43 pF capacitor is recommended to be a NPO type ceramic part. Changing the value of this capacHor alters the lock
range of the decoder PLL.
4. The tolerance on the value of the 0.22 ~F capacitor should be w~hin ±20% for the full design temperature range of operation.
Any reduction in the value of this capacitor due to temperature excursions will reduce the pilot tone circuit sensitiv~y.
5. The 0.47 ~F capacitor is recommended to be a low ESR type capacHor, (less than 1.5 &.I) in order to avoid increased audio
output distortions under weak input signal conditions with higher modulation levels.
6. The scan/mute function is located on the Blend pin at Pin B. To provide this function, Pin B should be pulled down below 0.3 V
until the decoder and the synthesizer have both locked to'a new station.
MOTOROLA ANALOG IC DEVICE DATA
9-125
MC13028A
FUNCTIONAL DESCRIPTION
II
Introduction
The MC13028A is designed as a low voltage, low cost
decoder for the C-QUAM AM Stereo technology and is
completely compatible with existing monaural AM
transmissions. The IC requires relatively few, inexpensive
external parts to produce a full featured C-QUAM AM Stereo
implementation. The layout is straightforward and should
produce excellent stereo performance. This device performs
the function of IF amplification, AGC, modulation detection,
pilot tone detection, signal quality inspection, and left and
right audio output matrix operation. The IC is targeted for use
in portable and home AM Stereo radio applications.
A simple overview follows which traces the path of the
input signal information to the MC13028A all the way to the
audio output pins of the decoder IC.
From the appropriate pin of an AM IC, the IF amplifier
circuit of the MC13028A receives its input at Pin 4 as a
450 kHz, typically modulated C-QUAM signal. The input
signal level for stereo operation can vary from 47 dB/lV to
about 90 dB/lV. A specific threshold level between these
limits can be designed into a receiver by the choice of the
resistor value for R1 connected to Pin 1. This IC design
incorporates feedback in the IF circuit section which provides
excellent dc balance in the IF amplifier. This balanced
condition also guarantees excellent monophonic
performance from the decoder. An IF feedback filter at Pin 3
is formed by a 0.47 /IF low leakage capacitor. It is used to
filter out the unwanted audio which is present on the IF
amplifier feedback line at higher modulation levels under
weak input RF signal conditions. Elimination of the unwanted
signal helps to decrease the amount of distortion in the audio
output of the stereo decoder under these particular input
conditions. An AGC circuit controls the level of IF signal
which is subsequently fed to the detector circuits. An AGC
bypass capaCitor is connected to Pin 2 and forms a single
pole low pass filter. The value of this part also sets the time
constant for the AGC circuit action.
The amplified C-QUAM IF Signal is fed simultaneously to
the envelope detector circuit, and to a C-QUAM converter
circuit. The envelope detector provides the L+R (mono)
signal output which is fed to the stereo matrix. In the
converter circuit, the C-QUAM signal is restored to a Quam
signal. This is accomplished by dividing the C-QUAM IF
signal by the demodulated cos term. The cos term is
derived from the phase modulated IF Signal in an active
feedback loop. Cosine is detected by comparing the
envelope detector and the in-phase detector outputs in the
high speed comparator/feedback loop. Cosine is extracted
from the I detector output and is actively transferred through
feedback to the output of the comparator. The output of the
comparator is in turn fed to the control inpu! of the divider,
thus closing the feedback loop of the converter circuit. In this
process, the cos term is removed from the divider IF output,
thus allowing direct detection of the L-R by the quadrature
detector. The audio outputs from both the envelope and the
L-R detectors are first filtered to minimize the second
harmonic of the IF signal. Then they are fed into a matrix
9-126
circuit where the Left channel and the Right channel outputs
can be extracted at Pins 15 and 16. (The outputs from the I
and Q detectors are also filtered similarly.) At this time, a
stereo indicator driver circuit, which can sink up to 10 mA, is
also enabled. The stereo output will occur if the input IF
signal is: larger than the stereo threshold level, not too noisy,
and if a proper pilot tone is present. If these three conditions
are not met, the blend circuit will begin to force monaural
operation at that time.
A blend circuit is included in this design because
conditions occur during field use that can cause input signal
strength fluctuation, strong unwanted co--channel or power
line interference, and/or multi-path or re-radiation. When
these aberrant conditions occur, rapid switching between
stereo and mono might occur, or the stereo quality might be
degraded enough to sound displeasing. Since these
conditions could be annoying to the normal listener, the
stereo information is blended towards a monaural output.
This circuit action creates a condition for listening where
these aberrant effects are better tolerated by the consumer.
Intentional mono operation is a feature sometimes
required in receiver designs. There are several ways in which
to accomplish this feat. First, a resistor from Pin 10 to ground
can be switched into the circuit. A value of 1.0 k is adequate
as is shown in the schematic in Figure 18. A second method
to force the decoder into mono is simply to shunt Pin 10 to
ground through an NPN transistor (collector to Pin 10, emitter
to ground), where the base lead is held electrically "high" to
initiate the action.
A third method to force a mono condition upon the
decoder is to shunt Pin 8 of the decoder to ground through
an NPN transistor as described above. Effectively, this
operation discharges the blend capacitor (10 /IF), and the
blend function takes over internally forcing the decoder into
mono. This third method does not necessarily require extra
specific parts for the forced mono function as the first two
examples do. The reason for this is that most electronically
tuned receiver designs require an audio muting function
during turn onlturn off, tuning/scanning, or band switching
(FM to AM). When the muting function is designed into an
AM Stereo receiver, it also should include a blend capaCitor
reset (discharge) function which is accomplished in this case
by the use of an NPN transistor shunting Pin 8 to ground,
(thus making the addition of a forced mono function almost
"free"). The purpose of the blend reset during muting is to
re-initialize the decoder back into the "fast lock" mode from
which stereo operation can be attained much quicker after
any of the interruptive activities mentioned earlier, (i.e. turn
on, tuning, etc.).
The VCO in this,IC is a phase shift oscillator type design
that operates with a ceramic resonator at eight times the IF
frequency, or 3.60 MHz. With IF input levels below the
stereo threshold level, the oscillator is not operational. This
feature helps to eliminate audio tweets under low level,
noisy input conditions.
MOTOROLA ANALOGIC DEVICE DATA
MC13028A
The phase locked loop (PLL) in the MC13028A is locked to
the L-R signal. This insures good stereo distortion
performance at the higher levels of left only or right only
modulations. Under normal operating conditions, the PLL
remains locked because of the current flow capability of the
loop driver circuit. This high gain, high impedance circuit
performs optimally when the current flow is balanced. The
balanced condition is enhanced by the loop driver filter circuit
connected between Pin 14 and ground. The filter circuit
consists of a 47 a resistor in series with a 47 IlF capacitor. The
47 a resistor is to set the Fast Lock rate. It is recommended
that the capacitor be a very low leakage type electrolytic, or a
tantalum composition part because any significant amount of
leakage current flowing through the capacitor will unbalance
the loop driver circuit and result in less than optimum stereo
performance, see Figures 10 and 11.
The pilot tone detector circuit is fed internally from the Q
detector output signal. The circuit input employs a low pass
filter at Pin 11 that is designed to prevent the pilot tone
detector input from being overloaded by higher levels of L-R
modulation. The filter is formed by a 0.22 IlF capacitor and
the input impedance of the first amplifier. A pilot I detector
circuit employs a capacitor to ground at Pin 9 to operate in
conjunction with an internal resistor to create an RC
integration time. The value of the capacitor determines the
amount of time required to produce a stereo indication. This
amount must include the time it takes to check for the
presence of detector falsing due to noise or interference,
station retuning by the customer, and pilot dropout in the
presence of heavy interference. The pilot Q detector utilizes
a filter on its pilot tone PLL error line at Pin 10. This capaCitor
to ground (usually 0.47 IlF) is present to filter any low
frequency L-R information that may be present on the error
line. If the value of this capacitor is allowed to be too small,
L-R modulation ripple on the error line may get large enough
to cause stereo dropout. If the capaCitor value is made too
large, the pilot tone may be prevented from being reacquired
if it is somehow lost due to fluctuating field conditions.
A 1.0 V reference level is created internally from the VCC
source to the IC. This regulated line is used extensively by
circuits throughout the MC13028A design. An electrolytic'
capaCitor from Pin 7 to ground is used as a filter for the
reference voltage.
DISCUSSION OF GRAPHS AND FIGURES
If the general recommendations put forth in this application
guide are followed, excellent stereo performance should
result.
The curves in Figures 2 through 7 depict the separation
and the distortion performance in stereo for 30%, 50%, and
65% single channel modulations respectively. The data for
these figures were collected under the conditions of
Vce =8.0 V and RO = 10 k in both the left and the right
channels as applied to the application circuit of Figure 1. A
very precise laboratory generator was used to produce the
AM Stereo test signal of 450 kHz at 70 dBIlV fed to Pin 4. An
NRSe post detection filter was not present at the time of
these measurements. The audio separation shows an
average performance at 30% and 50% modulations of
-45 dB in the frequency range of 2.0 kHz to 5.0 kHz. The
corresponding audio distortions under these conditions are
about 0.28% at 30% modulation, and about 0.41 % at 50%
modulation.
Figure 6 shows that the typical separation at 65%
modulation in the 2.0 kHz to 5.0 kHz region is about -37 dB,
and the corresponding audio distortion shown in Figure 7 is
about 1.0%. The performance level of these sinusoidal
Signals is somewhat less than those discussed in the
MOTOROLA ANALOG IC DEVICE DATA
previous paragraph due to the internal operation of the
clamping circuits. In the field, the transmitters at AM Stereo
radio stations are not usually permitted to modulate single
channel levels past 70%. Therefore these conditions do not
occur very often during normal broadcast material.
The roll-off at both the low and high frequencies of the
30% single channel driven responses is due to the fact that a
post detection bandpass filter of 60 Hz to 10kHz was used in
the measurement of the data, while a post detection filter of
2.0 Hz to 20 kHz was used for the collection of data in the
50% and 65% modulation examples. The tighter bandwidth
was used while collecting the performance data at 30%
modulation levels in order to assure that the distortion
measurement was indicative of the true distortion products
measured near the noise floor and thus not encumbered by
residual noise and hum levels which would erroneously add
to the magnitude of the harmonic distortion data. Note in
Figure 8 the traces of noise response for the four different
bandwidths of post detection filtering. It can be seen that the
noise floors improve steadily with increasing levels of
incoming 450 kHz as the value of the lower corner frequency
of the filter is increased. Data for the stereo noise floors was
collected with the decoder in the forced stereo mode.
9-127
MC13028A
o
Figure 2. Single Channel Separation
at 300/0 Modulation
Figure 3; Single Channel Distortion
at 300/0 Modulation
10
Desired Channel
-10
~
-
~
!;;:
II:
~
-20
-30
I"SeeText
~ r-\Lndesired Channel
\.
r--.. 1'0 ....
gj
-40
......
~~
-50
100
1.0k
0.1
10k
100
1.0k
10k
t, FREQUENCY (Hz)
t, FREQUENCY (Hz)
Figure 4. Single Channel Separation
at 50% Modulation
Figure 5. Single Channel Distortion
at 50% Modulation
10
Desired Channel
-10
"
10
:s
z
o
~
~
w
-20
-30
~ I'....Undesired Channel
......
en
-50
o
~ 1.0
i5
............
1.0 k
100
10k
o. 1
100
t, FREQUENCY (Hz)
Figure 6. Single Channel Separation
at 65% Modulation
.
Figure 7. Single Channel Distortion
at 65% Modulation
10 k
10
Desired Channel
-10
......
10
I'-....
:s
z -20
!;!
1.0k
t, FREQUENCY (Hz)
0
0
" I'r--..
f2en
1'0 ....
-40
II
cz
.....
roo
............... Kndesired Channel
II:
~ -30
w
..... 1'0
en
-40
-50
100
1.0k
t, FREQUENCY (Hz)
9-128
10k
0.1
100
1.0k
10k
t, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
MC13028A
Figure 8. Stereo Noise and Stereo Composite
Distortion when Mono Transmitted
iz
10
~
o
o·
§
Stereo Audio Level
...-
"--l
Stereo Composite Distortion
-10
N
lV-
~ -20
~
,
Noise
5.0 Hz \.0 kHz
-30 -
a:
12
-40
w
en
-50
~
400 Hz to 3.0 kHz
50 Hz to 3.0 kHz
I
\
tOO Hz to
kHZ\
3~
-
[3 -60
a:
40
50
60
70
80
"
~
en
30
Cf.
w
4.0
~
w
~
/
gs
"-
o
1.0~
~
o ~
1046
"-1""-
/
~
/
~
i l\.
I"
48
i'..
52
50
q:r
54
56
58
60
\
2.0
\
W
...J
C)
Z
\
CiS
....
..............
15 1.0
Z
o
~
~
o
-600
-400
-200
Loop Filter 15
\
M
//
I' /
I
10
-400
~V
- 200
0
200
400
Figure 13. AGC Voltage versus
Input Signal Level
\
If
-600
600
Figure 12. Low Frequency Corner
of PLL Response
Loop Filter 47 ~F
§
ii! -8.0
400
/
LEAKAGE CURRENT (10-9)
II
I I
[3
::: -4.0
200
\
/
/
LEAKAGE CURRENT (10-9)
0
-12
3.0~
~
ae 100
8::;;
g1
25
20
4.0~
Figure 11. Decoder Distortion versus Filter
Capacitor (Pin 14) Leakage Current
0
35
oz
Figure 10. Decoder Separation versus Filter
Capacitor (Pin 14) Leakage Current
40
~
,
5.0 ::;;
STEREO THRESHOLD (dB~V)
45
10
Rl toVcC
SIGNAL STRENGTH (dB~V)
50
z
1000
2.0~
\/
\.
Figure 9. R1 versus Stereo Threshold Point
~
7.0g
;:;
6.0§
/
~F
I
'\0 .J.
7
500
I
.-
Loop FiHer 4.7 ~F
~
"""'--
r"
>
S
400
...J
W
/
>
w
...J 300
~ 200
§?
L
~ 100
100
MODULATION FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
~
J
(.')
1/
----
II
600
I
W
C)
I
~
V
./
o
40
50
60
70
80
90
INPUT SIGNAL STRENGTH (dB~V)
9-129
MC13028A
Figure 9 presents more detailed information with respect
to the value of resistor R1 at Pin 1 versus the desired
incoming signal level for stereo threshold.
Figures 10 and 11, discussed briefly in the Pin Function
Description Section, show the importance of using a quality
component at Pin 14 to ground. It can be seen that an
electrolytic capacitor leakage current of 600 nA can
unbalance the. PLL to the point where stereo performance
may degrade to only 25 dB of separation with a
corresponding 2.0% distortion at 50% modulation levels.
The value of the capacitor connected to Pin 14 (47 JlF) is
also a factor in the determination of the low frequency corner
of the PLL circuit response. Three traces of PLL response
appear in Figure 12 where they have been plotted for three
different values of loop filter capacitor. The recommended
value of 47 JlF provides the best response shape in this
particular circuit set-up where a Murata Products
CSA3.60MGF108 part is used.
Figure 13 presents the response of the AGC voltage
versus decoder input signal level. This is a typical response
when the Ie is used as shown in the application schematic of
Figure 1. The tra«El begins approximately at the point of
decoder sensitivity, and rises rapidly until reaching the area
of stereo sensitivity, approximately 50 dBJlV. Thereafter, the
circuit responds in a linear fashion for the next 30 dB of input
signal increase.
Figures 14 through 17 inclusively depict the VCC ripple
rejection performance for the MC13028A under mono and
stereo conditions for nominal and for low values of VCC. It
should be noted that this data was collected without any VCC
filtering. As one might expect, the ripple rejection is better in
mono than in stereo. When the decoder operates in stereo,
the VCO is functional, thus the decoder becomes more
susceptible to audio ripple on the VCC line. Under normal
operating conditions, with the recommended value of 47 JlF
at Pin 12 and 10 JlF at Pin 7, a VCC ripple reading will be
virtually the same as measuring the noise floor of the IC.
AM STEREO TUNER I FM STEREO IF
Description of Application
Special Parts
This application combines a Sanyo LA1832M with the
Motorola MC13028A AM Stereo decoder IC. The LA1832
provides an FM IF, FM multiplex detection, AM tuning, and
the AM IF functions. The MC13028A provides the AM Stereo
detection as well as Left and Right audio outputs. An
MC145151 synthesizer provides the frequency control of the
local oscillator contained within the LA 1832. Frequency
selection is by means of a switch array attached to the
synthesizer. The application circuit is shown in Figure 18.
The following information provides circuit function, part
number, and the manufacturer's name for special parts
identified by their schematic symbol. Where the part is not
limited to a single source, a description sufficient to select a
part is given.
U1
IC - AM Stereo Decoder
MC13028AD by Motorola
U2
IC - AM/FM IF and Multiplex Tuner
LA 1832M by Sanyo
U3
IC - Frequency Synthesizer
MC145151DW2 by Motorola
T1.
AM IF Coil
A7NRE5-11148N by TaKa
F1
AM IF Ceramic Filter
SFG450F by Murata
F2
FM IF Detector Resonator
CDA10.7MG46A by Murata
F3
FM Multiplex Decoder Resonator
CSB456F15 by Murata
F4
AM Tuner Block
.BL-70 by Korin Giken
X1
10.24 MHz Crystal, Fundamental Mode,
AT Cut, 18 pF Load Cap, 35 n maximum series R.
HC-18/U Holder
X2
3.6 MHz AM Stereo Decoder Resonator
CSA3.60MGF108 by Murata
S5
8 SPST DIP Switch
Circuit Board Description
The copper side layout and the component locations are
shown in Figure 19. The view is from the plating side of the
board, with the components shown in hidden view. Several
jumper wires are placed on the component side of the board
to complete the circuit. Posts are provided for electrical
connections to the circuit. The circuit board has been scaled
to fit the page, however, the dimensions provide the true size.
Circuit Description
The Sanyo data sheet for the LA 1832 should be
consulted for an understanding of the FM detection and
multiplex decoding.
9-130
MOTOROLA ANALOG Ie DEVICE DATA
MC13028A
Figure 15. Mono Low Voltage
VCC Ripple Rejection
Figure 14. Mono VCC Ripple Rejection
-30
10
:E-'
c -40
Ci5
W
II:
-50
1.0k
100
RIPPLE FREQUENCY (Hz)
RIPPLE FREQUENCY (Hz)
Figure 16. Stereo VCC Ripple Rejection
Figure 17. Stereo Low Voltage
VCC Ripple Rejection
-20rr-"rrrr----~--_._,r_,,_.TT._----,
-10
r-r--
10 -20
I J
~ r--...,VCC=2.0V
-........ r-...
:E-
~
ffi
II:
-30
-40
I-
~
VCC= 3.0V..---x
-50
100
1.0k
RIPPLE FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
-60
I I VCC
= 4.0 v""'"
1-'
100
.........
"\.
~ ...........
V
~CI2'151
II
~
m
I.Ok
RIPPLE FREQUENCY (Hz)
9-131
I
Figure 18. MC13028A Decoder IC Application
1:
C20
10JlF
Co)
I\)
s::
o....
Co)
oI\)
;
i!:
g
:u
o
~
l>
~.
8o
c
m
<
o
m
c
:=J:Ii
Gnd~
-=-
-=-=-
--=-
•
-=-
f~4148
MC13028A
Figure 19. MC13028A Decoder IC Application Circuit Board
11.50
em
12.50
em
II
0.50cm
0.50em
I~
+
MOTOROLA ANALOG IC DEVICE DATA
S.Oem
9.0em
"I .
- - - - - - - - - - - - - - - + 1I
9-133
MC13028A
The LA 1832 tuner IC (U2) is set for AM operation by
switch S2 connecting Pin 12 to ground. An AM Stereo signal
source is applied to Pin 2 of the RF coil contained within the
BL-70 tuning block. That coil applies the signal to Pin 21 of
U2. The L.O. coil is connected from Pin 23 to VCC. The
secondary is tuned by a varactor which is controlled by a dc
voltage output from the synthesizer circuit. The reactance of
this oscillator tank is coupled back to Pin 23. It is through this
reactance that the frequency of the L.O. is determined. A
buffered output from the L.O. emerges at Pin 24. This signal
is routed to Pin 1 of the synthesizer (U3), thus completing the
frequency control loop.
The mixer output at Pin 2 is applied to the IF coil T1. Coil
T1 provides the correct impedance to drive the ceramic
bandpass filter F1. The IF signal returns to U2 through
Pin 4, and also to the input, Pin 4 of the AM Stereo decoder
(U1). The ceramic filter F1 is designed to operate into a
load resistance of 2.0 kO. This load is provided at Pin 4 of
U2.
The stereo outputs exit from Pins 15 and 16 of U1. The
design amplitudes of the audio outputs will vary according to
the values used for the resistors to ground at Pins 15 and 16
of the decoder, (labeled RO in the Electrical Characteristics
Table and the ,Test Circuit on page 2 and 3, and in Figure 1,
and called R2 and R3 in Figure 18). While the values chosen
for RO are left to the discretion of the designer, the numbers
chosen in this data sheet are reflective of those required to
set the general industry standard levels of audio outputs in
receiver designs.
Pins 15 and 16 are also good locations for the insertion of
simple RC filters that are used to comply with. the United
States NRSC requirement for the shape of the overall
receiver audio response. The following curve, Figure 20,
shows the response of this U.S. standard.
Figure 20. NRSC De-Emphasis Curve
for the United States
o
~
10-2.0
r\
:Eo
is -4. 0
~
~ -6.0
~
«:
1\
-8.0
-1 0
100
200
500
1.0k
2.0k
5.0k
10k
f, FREQUENCY (Hz)
There are many design factors that affect the shape of the
receiver response, and they must all be considered when
trying to approximate the NRSC de-emphasis response. The
mixer output transformer (IF coil, T1), and ceramic filter
probably have the greatest contribution to the frequency
response. The ceramic filter can be tailored from its rated
response by the choice of transformer impedance and
bandwidth. When designing an overall audio response
shape, the response of the speakers or earphones should
also be considered.
9-134
Component Values.
The Pin Function Description table gives specific
information on the choice of components to be used at
each pin of U 1. A similar section in the Sanyo LA 1832 data
sheet should be consulted as to the components to be used
with U2.
Tuning
The frequency to which the test circuit will tune is set by
the eight binary switches contained in the 55 assembly,
numbered' from 1 to. 8. Number 1 connects to Pin 11 of U3
and number 8 connects to Pin 18. The other switches
connect to the pins in between and in order. Each individual
switch is a SPST type.
To tune to a specific RF frequency, a computation must be
made in order to ascertain the divide ratio to input to the
synthesizer via the switch array. The divide ratio is simply the
eight digit binary equivalent number for the local oscillator
frequency divided by 10kHz. The local oscillator frequency is
the desired RF frequency plus 450 kHz, the IF frequency. Any
local oscillator value within the AM band can be represented
by a binary number. Each binary bit represents a switch
setting where a "1" is an open switch and a "0" is a closed
switch. The most significant bit represents switch 8 which is
connected to Pin 18.
To illustrate, consider the setting for an input frequency of
1010 kHz. (This frequency was used to test the circuit board
as described further on.) The local oscillator frequency is
1070 kHz plus 450 kHz which equals 1520 kHz. Dividing by
10kHz yields the number 152. The binary number for 152 is
10011000. Thus the switches are set to:
Switch
Position
8
Open
NUmber
1
7
Closed
0
6
Closed
0
5
Open
1
4
Open
1
3
Closed
0
2
Closed
0
1
Closed
0
Circuit Adjustments
The FM circuit requires no adjustment. The AM L.O. must
be able to tune from 980 to 2150 kHz to cover the broadcast
range. Adjust the core of the L.O. coil if needed in order to be
able to cover this range. The AM RF coil and trimmer can be
adjusted for best signal after connection to the loop antenna.
The coil is adjusted near the low end of the band, and the
trimmer is adjusted at the top of the band. The IF coil, T1, is
first adjusted for maximum signal out of the filter, F1. This is
a "coarse" adjustment. The final ''fine tune" adjustment
occurs after the following conditions are met. From an AM
Stereo generator with the pilot tone off, feed the decoder an
input signal of approximately 70 dBj.lV that is modulated with
an 80% L-R audio signal at 3.0 kHz. While monitoring either
the left or the right output from the decoder on an
oscilloscope, precisely fine tune the IF coil for a minimum
residual signal, see the following diagram. If there is no
sideband tilt in the system, this adjustment should hold for
both channels. Otherwise, the best compromise adjustment
for both channels should be used.
MOTOROLA 'ANALOG IC DEVICE DATA
MC13028A
AM Circuit Test
The connections for test are as shown in Figure 22. A 50 n
resistor is placed on the AM antenna input. The AM Stereo
generator is connected to the AM antenna input.
Measurements of audio level in mono mode are made with
an audio voltmeter connected through a FET probe (pilot
signal "off"). Measurements of audio level and distortion in
stereo mode (pilot signal "on") are made using a pilot
rejection filter ahead of the distortion analyzer or the audio
meter. The pilot rejection filter has a rejection ratio that should
exceed 20 to 25 dB. Typical data is shown in Figures 23-26.
Figures 23 and 24 were read on the left channel in mono
mode. Figures 25-26 were in stereo mode.
Figure 21. Decoder Signal Output for Mistuned
and Tuned Condition with Input Signal of 80%
L-R at 3.0 kHz
Mistuned
Tuned
Figure 22. MC13028A/LA1832 Application Circuit Board Test Setup
1-------------,
, 110-01
r:---------I'
son'
10-011'
,
• AmStereo
Generator
1070 kHz
50 n Output
AM Ant. Input
1--__._--1-+0-+1-0
o
,
01
10
II
,
IlQ _~_______
LQ_QlI'
1.::_...1 I
...L
,
Ant. Tuning Block
,
.1 I'II
1 I,
Pilot Filter
and
Buffer Amp
Right
!----O- -.J ,
U1
MC13028A1LA1832 Application
Circuit Board Test
-=
L ___ ~~e!!,~~~~ ___ ..J
Distortion
Analyzer
and
Audio Voltmeter
For Stereo Measurements, Pilot On
MOTOROLA ANALOG IC DEVICE DATA
II
~
9-135
MC13028A
,
Figure 23. Left·AM Output at 30% Modulation
10
o
-10
5o
!l3
)"
-30
-40
-50
o
20
6.0
1000 kHz
Noise
60
80
-
100
z 5.0
0
~ ~
1f'.
~
40
0
4.0
~
3.0 15
l\.
\~
Distortion
-60
6.0
5.0 z
odB =90 mVnns
1\
7.0
1000kHz
Out
,/
-20
Figure 24. Left AM Output at 80% Modulation
7.0
~
4.0
CI)
15 3.0
1f'.
2.0
2.0
1.0
1.0
o
120
"
\
20
.".
40
--
..---r- /
60
Figure 25. AM Output Right Channel Only
Modulated at 50%
Figure 26. AM Output Left Channel Only
Modulated at 50%
Out
Out
z
0
odB = 150 mVnns
3.0~
~
~
CI)
2.015
2.015
1f'.
1f'.
1.0
TONE (Hz)
0
10 k
z
0
3.0 ~
1.0k
120
5.0
4.0
odB = 150 mVrms
9-136
100
PEAK (dBI!V)
5.0
a
80
INPUT (dBI!V)
1.0
1.0k
0
10k
TONE (Hz)
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROI.A
MC13029A
Advance Information
Advanced Medium Voltage IF
and C-QUAM® AM Stereo
Decoder with FM Amplifier and
AM/FM Internal Switch
C-QUAM AM STEREO
ADVANCED MEDIUM VOLTAGE
IF AND DECODER
FOR E.T.R. RADIOS
The MC13029A is a third generation C-QUAM stereo decoder targeted
for use in medium voltage, CD/Cassette, Mini-Component, and Hi-Fi
AM/FM Electronically Tuned radio applications. Advanced features include a
signal quality detector that analyzes signal strength, signal to noise ratio, and
stereo pilot tone before switching to the stereo mode. A "blend function" has
been added to improve the transition from both mono to stereo and stereo to
mono. The audio output level is adjustable to allow easy interface with a
variety of AM/FM tuner chips. The IC further includes an AM/FM switch, an
audio mute and internal high pass filtering on AM. The external components
have been minimized to keep the total system cost low.
DWSUFFIX
PLASTIC PACKAGE
CASE 7510
(S0-20)
H SUFFIX
PLASTIC PACKAGE
CASE73B
• Operation From 4.0 to 12 V Supply
• IF Amplifier with IF AGC Circuit
• Single Pin-Out, Temperature Compensated VCO
• VCO Shut Down Mode at Weak Signal Condition
• Precision Pilot Tone Detector
• Stereo Blend Function
• Forced Mono Function
PIN CONNECTIONS
• Adjustable Audio Output Level
• AM/FM Switch
FM Left Input
AM/FM Switch
AGCBypass
Filter
IF Feedback
Bypass
IF Signal Input
• Separate AM De-Emphasis
• Mute Function
• Internal AM High Pass Filters
FM Right Input
To Radio Mute
Right Audio
Output
Left Audio
Output
VCC
AM Right Chan
De-Emphasis
AM Left Chan
De-Emphasis
Loop Filter
Gnd
Stereo Indicator
Drive
Blend
Simplified Block Diagram
20
19
18
17
13
12
11
1.0 V Reference
Pilot I Detector
Output
Pilot Q Detector
Outpu1
VCOOutput
(Top View)
ORDERING INFORMATION
Device
MC13029ADW
MC13029AH
L.._
-6-2
3
4
5
6
-!T----
7
8
9
10
Operating
Temperature Range
TA = - 25° to +70°C
Package
S0-20
DIP-20
The purchase of the Motorola C-QUAM® AM Stereo Decoder does not carry with such purchase any license by im·
plication, estoppel or otherwise, under any patent rights of
Motorola or others covering any combination of this decod·
er with other elements including use in a radio receiver.
Upon application by an interested party. licenses are available from Motorola on its patents applicable to AM Stereo
radio receivers.
This device contains 909 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
9-137
II
MC13029A
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Symbol
Value
Unit
VCC
14
Vdc
Power Supply Input Voltage
Operating Junction Temperature
TJ
150
°C
Operating Ambient Temperature
TA
-25 to +70
°C
Storage Temperature REinge '
Tslg
-55 to +150
°C'
LED Indicator Current
ILED
10
mA
NOTE:
ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, TA = 25°C, Input Signal Level = 74 dBIlV, Modulating
Signal = 1.0 kHz
@
50% Modulation, Test Circuit of Figure 1, unless otherwise noted.)
Min
Typ
Max
-
-
9.0
12
11
13
50
80
110
mVrms
Vout
110
170
260
mVrms
OutputTHD
Stereo, L or R Only
Mono, L+R
THO 1
THD2
-
0.6
0.1
1.8
0.6
Channel Separation, L or R Only
RorL
23
35
-
dB
Yin
-
33
-
dB/lV
-
0.25
0.3
-
Vdc
40
40
59
62
-
-
10
8.0
-
Characteristic
Symbol
Supply Current Drain
VCC=12V
VCC=5.0V
ICC
Audio Output Level, L+R, Mono Modulation
RO=3.9k
Vout
Audio Output Level, L only or R Only, Stereo Modulation
RO = 3.9 k
Unit
mA
%
Decoder Input Sensitivity, Vout = -10 dB
Force to Mono Mode, at Pin 10
Signal to Noise Ratio
Stereo, 50%, L or R Only, 1.0 kHz
Mono, 50%, L+R, 1.0 kHz
SIN
Input Impedance
(Reference Specification)
Rin
Cin
dB
-
BI
Blend Voltage
Mono Mode
Stereo Mode
Out at Lock
0.7
1.2
-
-
1.30
0.12
kO
pF
Vdc
0.9
1.4
0.2
VCO Lock Range
OSCtun
-
±2.5
-
kH7
AGC Range
AGC rng
-
44
-
dB
G-B
-1.2
-
1.2
dB
-
-
-
4.0
%
Channel Balance
Pilot Sensitivity
FM AUDIO SWITCH ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, TA = 25°C, Signal = 1.0 kHz.)
Characteristic
FM Switch Nominal Audio Input
VCC=5.0V
Symbol
Min
Typ
Max
Unit
Yin
200
-
500
mVpp
SIN
-
80
-
dB
Channel Separation, Lor R Only
RorL
-
>60
-
dB
Output THO
FM Audio Input = 200 mVrms
FM Audio Input = 500 mVrms
THDI
THD2
-
0.01
-
-
2.0
-
-
0.5
2.6
-
-
2.6
-
-
Signal to Noise Ratio (FM Audio Input = 200 mVrms)
%
AM/FM Switch Input (Pin I)
AM Mode
FM Mode
-
Mute Threshold (Pin 18)
Mute On
Mute Off
-
9-138
Vdc
Vdc
-
0.5
MOTOROLA ANALOG IC DEVICE DATA
MC13029A
Figure 1. Test Circuit
Vee Input for Ripple Rejection Tests
1 AUdi~
51
+
FMln
Left Right
Input for Ripple Rejection Tests
300~F
VCC=5.0V
10~F
Stereo
I;
6.8k
+
FM
1O~FI
+
2.2~FI
18
5
-=
+
I
10~Fr-__________~
Ul
15
7
14
8
13
+
12
10~F
Out
16
6
Right
47k
17
4
-=
0.01
~
19
3
IF In
0
-=
-=
Mute
20
-=
1.0k
6.8k
MC13029A
:p:q
0.001
3.9k
-=
Left
Out
10
0.001
3.9k
47
Enable Stereo wlo Pilot
Forced
Stereo
047
.J
-
43I3.60-=
-=MHZ..I..
-=
-
II
Normal
1.2SVNom
1.2to 1.SV
MOTOROLA ANALOG IC DEVICE DATA
1
Force
Mono
1.0k
9-139
MC13029A
PIN FUNCTION DESCRIPTION
Pin
Symbol
Internal Equivalent Circuit
AMlFM
1.9V
2
Description/External Circuit Requirements
AMIFM Mode Switch
The dc level applied to this pin will determine
whether the AM or FM audio is switched to output
Pins 16 and 17. A voltage greater than 1.2 V will
cause the FM audio to be output.
AGC Filter Bypass Capacitor
AGCcap
An electrolytic capacitor is used as a bypass filter
and it sets the time constant for the AGC circuit
action. The recommended capacitor value is 10 \!F
from Pin 2 to ground. The dc level at this pin varies
as shown in the curve in Figure 13. AGC Voltage
versus Input Level.
Vee
IF Amplifier Feedback Capacitor
A capacitor which is specified to have a low ESR
at 450 kHz is normally used at Pin 3. The value
recommended for this capacitor is 0.47 \!F from
Pin 3 to ground. This component forms a low pass
filter which has a comer frequency around 30 kHz.
3
IFFBcap
4
IFin
IF Amplifier Input
Pin 4 is the IF input pin. The typical input
impedance at this pin is 10k. The input should be
ac coupled through a 0.01 \!F capacitor.
5
Gnd
Supply Ground
In the PCB layout. the ground pin should be
connected to the chassis ground directly. This pin
is the internal circuit ground and the silicon
substrate ground.
Substra1e
6
Vee
SIND
6
Stereo Indicator Driver
This driver circuit is intended to light an LED or
other indicator when the decoder receives the
proper input signals and switches into the stereo
mode. The maximum amount of current that the
circuit can sink is 10 rnA.
A current limiting resistor is applied externally to
control LED brightness versus total power supply
current.
9-140
MOTOROLA ANALOG IC DEVICE
P~TA
MC13029A
PIN FUNCTION DESCRIPTION (continued)
Pin
7
Symbol
Internal Equivalent Circuit
CAPBlend
Pilot Indicator
Driver Circuit
70-+-.....-[
Description/External Circuit Requirements
Blend Capacitor
The value of the capacitor on this pin will effect the
time constant of the decoder blend function. The
recommended value is 10 l1F from Pin 7 to ground.
The dc level at Pin 7 is intemally generated in
response to input signal level and signal quality.
This pin is a key indicator of the operational state of
the IC (see text Functional Description). It is
recommended to discharge the Blend Capacitor
extemally when changing stations.
8
Vref
Regulated Voltage, 1.0 V
An electrolytic capacitor used as a bypass filter is
recommended from Pin 8 to ground. The capacitor
value should be 10 l1F.
9
IPilot
Pilot I Detector Output
The Pilot I Detector Output requires a 10 l1F
electrolytic capacitor to ground. The value of this
capac~or sets the pilot acquisition time. The dc
level at Pin 9 is approximately 1.0 Vdc, unlocked,
and 1.1 to 2.4 Vdc in the locked condition.
10
°Pilot
+
+
-=-
-=-
10
-=11
OSCin
+
+
+
Pilot Q Detector Output
This pin is connected to the Pilot 0 Detector and
requires a 0.47 l1F capacitor to ground to filter the
error line voltage at the PLL pilot tone detector. If the
value of this capacitor is made too large, the
decoder may be prevented from coming back into
stereo after a signal dropout has been experienced
in the field. The force to mono function is also
accomplished at this pin by pulling the dc voltage
.
level at the pin below 1.0 V.
Oscillator Input
The Oscillator pin requires a ceramic resonator and
parallel capaCitor connected to ground. The
recommended source for the ceramic resonator is
Murata, part number CSA 3.60MGFI 08. A 43 pF
NPO capac~or is in parallel with the resonator. The
dc level at Pin 11 is approximately 1.1 Vdc.
1100---+--.--{
12
LOOPFilter
+
+
120-....--'V1I1r--F-----;
MOTOROLA ANALOG IC DEVICE DATA
Loop Filter
A capac~or which forms the Loop Filter is connected
from Pin 12 to ground. The recommended value is
47 l1F in series w~ 47 n. This capacitor should be
of good construction quality so ~ will have a very low
specification for leakage current in order to prevent
stereo distortion. The 47 Q resistor in series wHh the
capacitor controls fast lock rate. The dc level at
Pin 12 is approximately 0.6 Vdc in the locked
condition.
9-141
MC13029A
PIN FUNCTION DESCRIPTION (c!)ntlnued)
Pin
Symbol
13
14
DE-L
DE-R
Internal Equivalent Circuit
Vee
Vee
13,140-<_--+----f
15
Vee
Vcc
DescrlptlonlExternal Circuit Requirements
AM De-Emphasis, Left Channel/Right Channel
An RC network attached at this pin can be used to
add de-emphasis to the AM. tone response. The
AM tone response is primarily shaped by the IF
filler. Additional roll-off may be applied here.
Supply Voltage (VCC)
The operating supply voltage range is from 4.0 Vdc
to 12 Vdc.
I
15
Vee
16
17
LEFTout
RIGHTout
18
Mute
Vee
Audio Output
. Output is approximately 1.31lApp drive current for
each percent of mono modulation. A resistor to
ground sets the voltage level of the audio output.
Mute Input
A dc voltage exceeding 1.5 V applied to this pin will
cause a shutting down of the left and right channel
outputs at Pins 16 and 17.
18
II
19
-=-
FM Audio Right Channel Input
The audio output from the FM detector is input at
this pin. The dc level applied at Pin 1, the AM/FM
Mode SWitch, then determines whether this audio,
or that from the AM channel will be output at
Pin 17. An external series resistor between this pin
and the FM detector is used to set the FM audio
levels at the output Pin 17.
-=-
FM Audio Left Channel Input
The audio output from the FM detector is input at
this pin. The dc level applied at Pin 1, the AM/FM
Mode Switch, then determines whether this audio
or that from the AM channel will be output at
Pin 16. An external series resistor, between this pin
and the FM detector, is used to set the FM audio
levels at the output Pin 16.
FM-R
19
-=20
FM-L
20
-=-
9-142
MOTOROLA ANALOG IC DEVICE DATA
MC13029A
Figure 2. Typical Circuit For HI-Fi AMlFM E.T.R. Applications
Stereo Audio Output
Ri ht
Left
FM Input
3.9k
"J"J
+
Vee
On
+
Mute
6.2k
47k
6.2 k
'1..._
2
3
+
+
10j.lF
0.47
Note 4
+
0.01
10j.lF
10
+
+
10j.lF
0.47
II
To AM Mono
Stereo Switch
33k
FM~
9
4
AM
33k
450 kHz
IF Input Signal
0----,1
c:=::J
T
NOTES: 1. This part is recommended to be a low leakage type capacnor. Leakage current due to this capacitor causes increase in stereo distortion and poor
separation perfonnance.
2. The recommended source for this part is Murata Products, CSA3.60MGF108. The location of this part should be carefully considered during the
layout of the decoder circuit. This part should not be near the audio signal paths, the 25 Hz pilot filter lines, or the VCC high current lines, and the
ceramic element ground line should be direct to the chassis ground lead in order to avoid any oscillator inter-modulation.
3. This capacitor is recommended to be an NPO type ceramic part. Changing the value of this capacnor aHers the lock range of the decoder PLL.
4. This part is recommended to be a low ESR type capacitor, (less than 1.5 il) in order to avoid increased audio output distortions under weak input
signal conditions wnh higher modulation levels.
5. Component values for this stage of the NRSC fiHer will vary from receiver manufacturer to manufacturer due to the additive nature of the particular
response slopes of the frequency selective parts, (RF and IF coils, and the ceramic IF filter) within a radio design. Since these responses may vary
somewhat in each custom deSign, the filters at Pins 13 and 14 are included to provide any remaining response roll-off that might be necessary to
comply with the overall NRSC frequency standard.
MOTOROLA ANALOG IC DEVICE DATA
9-143
MC13029A
FUNCTIONAL PESCRIPTION
Introduction
II
The MC13029A is designed as a medium voltage decoder
for the G-QUAM AM Stereo technology and is completely
compatible with existing monaural AM transmissions. The IC
requires relatively few, inexpensive external parts to produce
a multi-featured C-QUAM AM Stereo implementation. The
layout is straightforward and should produce excellent stereo
performance results. This device performs the function of IF
amplification, AGC, modulation detection, pilot tone
detection, signal quality inspection, blend, left and right
channel FM input amplification, muting, AM and FM
switching function, and amplified left and right audio output
levels which are adjustable. The IC is targeted for use in
CD/Radio/Cassette, Mini-Component, and Hi-Fi AM/FM
E.T.R. AM Stereo radio applications.
From the output of a ceramic IF filter and through a
coupling capacitor, the IF amplifier circuit of the MC13029A
receives its input at Pin 4 as a 450 kHz, typically modulated
C-QUAM signal. The input signal level for stereo operation
can vary from 50 dBl-tV to about 90 dBJ.lV. This IC design
incorporates feedback in the IF circuit section 'which
provides excellent dc balance in the IF amplifier. This
balanced condition also guarantees excellent monophonic
performance from the decoder. An IF feedback filter at Pin 3
is formed by a 0.47 J.lF, low leakage, low ESR capacitor. It is
used to filter out the 450 kHz Signal which is present on the
IF amplifier feedback line. An AGC circuit controls the level
of IF signal which is subsequently fed to the detector
circuits. An AGC bypass capacitor is connected to Pin 2 and
forms a single pole, low pass filter. The value of this part
also sets the time constant for the AGC circuit action.
The amplified C-QUAM IF signal is fed simultaneously to
the envelope detector circuit, and to a C-QUAM converter
circuit. The envelope detector provides the L+R (mono)
signal output which is fed to the stereo matrix. In the
converter circuit, the C-QUAM signal is changed into a
Quam signal when it is divided by the cos term. The Quam
IF signal is then fed into the I detector, the L-R detector, and
the Q detector circuits. The outputs of the Envelope detector
and the I detector circuits feed back into a comparator circuit
which looks at both signals and uses the differences to
create the cos signal. The Quam IF signal fed to the L-R
and the Q detectors is multiplied by a 450 kHz signal that is
phased 90 0 from the one in the I detector circuit. This
quadrature relationship is necessary in order to detect the
L-R (or stereo) audio information from the Quam signal. The
audio outputs from both the Envelope and the L-R detectors
are first filtered to minimize the harmonics of the IF signal
that are created in the mixing process. (The outputs from the
I and Q detectors are also filtered similarly.) Then they are
fed into a matrix circuit where the Left channel and the Right
channel outputs are extracted and fed into a high pass filter
block. Here the audio signals are conditioned so they can be
fed to an output amplifier which, if left unmuted, delivers the
left and the right output at Pins 16 and 17. At this time, a
stereo output will occur if the input IF signal is: a.) larger
than the stereo threshold level, b.) not too noisy, and c.) a
proper pilot tone is present. At Pin 6, the stereo indicator
driver circuit, which can sink up to 10·mA, is also enabled.
After turn on or tune in, if the input signal level threshold for
stereo operation is not exceeded, or if the incoming signal is
too noisy, the blend circuit, at Pin 7, (even in the presence of
9-144
a pilot signal) will hold the decoder in the monaural mode. A
blend circuit is included in this design because of the effects
of conditions which occur during field use that can cause
input signal strength fluctuation, strong unwanted
co-channel or power line interference, and/or multi-path or
re-radiation. When these aberrant conditions occur, rapid
switching between stereo and mono might occur, or the
stereo quality might be degraded. Since these effects could
be annoying to the listener, the stereo information is blended
towards a monaural output. This creates a condition for
listening where the aberrant effects are more tolerable.
Intentional mono operation is a feature sometimes
required in receiver designs. There are several ways in which
to accomplish this. First, a 10k resistor from Pin 10 to ground
can be switched into the circuit, as is shown in Figure 18. A
second method is to shunt Pin 10 to ground through an NPN
transistor as shown in Figure 2.
A third method to force a mono condition on the decoder is
to shunt Pin 7 of the decoder to ground through an NPN
transistor. This discharges the blend capacitor (10 J.lF), and
the blend function internally forces the decoder into mono.
This third method does not necessarily require extra parts as
most electronically tuned receiver designs require an audio
muting function during turn onlturn off, tuning/scanning, or
band switching (FM to AM). When the muting function is
designed into an AM Stereo receiver, it also should include a
blend capacitor reset (discharge) function. The purpose of
the blend reset during muting is to re-initialize the decoder
back into the "fast lock" mode from which stereo operation
can be attained much quicker after any of the interruptive
activities mentioned earlier, (Le. turn on, tuning, etc.).
The VCO in this IC is a phase shift oscillator type that
operates with a ceramic resonator at eight times the IF
frequency, or 3.60 MHz. With IF input levels below the
stereo threshold level, the oscillator is not operational. This
feature helps to eliminate audio tweets under low level,
noisy input conditions.
The phase locked loop (PLL) in the MC13029A is locked
to the L-R signal. This insures good stereo distortion
performance at the higher levels of Left only or Right only
modulations. Under normal operating conditions, the PLL
remains locked because of the current capability of the loop
driver circuit. This high gain, high impedance circuit is
filtered by a 47 n resistor in series with a 47 J.lF capaCitor
from Pin 12 to ground. It is recommended that the capaCitor
be a very low leakage type electrolytic (less than 200 J.lA),
or a tantalum part. Any significant leakage through the
capaCitor will unbalance the loop driver circuit and result in
less than optimum stereo performance, see Figures 10
and 11.
The pilot tone detector circuit is fed internally by a signal
from the Q detector output and is filtered by an internal, 50 Hz
low pass pilot pre-filter. This filter is designed to prevent the
pilot tone detector input from being overloaded by higher
levels of L-R audio modulation. A pilot I detector circuit
employs a capacitor to ground at Pin 9 to operate in
conjunction with an internal resistor to create an RC
integration time. The value of the capaCitor affects the
amount of time required to produce a stereo indication. The
minimal time period must be long enough to include the time
it takes for the circuit to check for detector falsing due to noise
MOTOROLA ANALOG IC DEVICE DATA
MC13029A
or interference, station re-tuning by the customer, and pilot
drop-out in the presence of heavy interference. The pilot Q
detector incorporates a filter on its pilot tone PLL error line at
Pin 10. This capacitor to ground (usually 0.47 /IF) is utilized
to filter any low frequency information that may be present on
the error line. If the value of this capacitor is allowed to be too
small, the level of interference near the pilot tone frequency
of 25 Hz may become large enough to cause stereo
drop-out. If the capacitor value is made too large, the pilot
tone may be prevented from being re-acquired if it is
somehow lost due to fluctuating field conditions.
A 1.0 V reference level is created within the IC. This
regulated line is used extensively by circuits throughout the
MC13029A design. An electrolytic capacitor from Pin 8 to
ground is used as a filter for the reference voltage.
At Pin 1, the MC13029A provides a function which allows
the user to switch between AM and FM audio signals. The
actual switching is controlled by dc level with a low for AM
and a high for FM audio output.
The level of the audio output at Pins 16 and 17 can be set
by the value of a resistor to ground at these pins. The output
pins are connected to the collectors of PNP audio output
amplifiers. At strong signal, these amplifiers can supply
about 1.3 /lApp of drive current for each percentage of mono
modulation present. In other words, for a 100% LTR signal,
130 /lApp will flow through the load. Thus, the value of
resistor to ground will determine the peak-to-peak output.
The MC13029A IC provides a true mute function,
controlled at Pin 18. A dc level of about 2.6 Vdc is sufficient to
ensure muting of the audio outputs at Pins 16 and 17. This
feature is useful when tuning in a different radio station, and
the designer may also choose to utilize muting when
switching between AM and FM.
The FM input audio signals are fed through series external
resistors to Pins 19 and 20. Since AM broadcasters normally
use heavy audio processing, the value of these resistors is
chosen so that the audio output levels of FM are
approximately 2.0 dB higher than the audio output levels of
AM for the same modulation levels. Under these conditions,
there will be only minimal volume differences perceived by
the consumer when the MC13029A is switched between AM
and FM outputs.
In order to comply with the FCC ruling on the NRSC AM
audio response, a connection for de-emphasis circuitry in
the MC13029A is provided at Pins 13 and 14 for left and
right AM channels respectively. Typically, a series R-G
network to ground will provide sufficient additional response
shaping to the overall AM response so that the NRSC
standard shape can be achieved. The values of these
de-emphasis components will vary from design to design.
The AM RF and IF coil responses, ceramic filter response
and NRSC circuit response all contribute in an additiive
manner to the shape of the overall AM audio responses at
the IC output pins.
II
MOTOROLA ANALOG Ie DEVICE DATA
9-145
MC13029A
DISCUSSION OF GRAPHS AND FIGURES
II
The curves in Figures 3 through 8 depict the separation and
the distortion performance in stereo for 30,,/0, 50% and 65%
single channel modulations respectively. The data for these
figures was collected under the conditions of VCC =8.0 V and
RO = 3.9 k in both the left and the right channels as
recommended in the application circuit of Figure 2. A very
precise laboratory generator was used to produce the AM
Stereo test signal of 450 kHz at 75 dBJ.1V fed to Pin 4. An NRSC
post detection filter was not used. The audio separation shows
an average performance at 30% and 50% modulations of
-38 dB in the frequency range of 1.0 to 5.0 kHz. The
corresponding audio distortions are about 0.3% at 30%
modulation and about 0.4% or better at 50% modulation.
Figure 7 shows that the typical separation performance at
65% modulation in the 1.0 to 5.0 kHz region is about -35 dB,
and the corresponding audio distortion shown in Figure 8 is
about 0.9% or better. The performance level of. these
sinusoidal signals is somewhat less than those discussed in
the previous paragraph due to the internal operation of the
clamping circuits. In the field, the transmitters at AM Stereo
radio stations are not usually permitted to modulate single
channel levels past 70%.
Note the -3.0 dB of roll-off at 80 Hz in the output
responses of this decoder. These are the top traces (Desired
Channel) in Figures 3, 5 and 7. That roll-off appears by
design as a feature to help minimize switching transients
present when between AM and FM. This roll-off also
provides additional attenuation of pilot tone residuals in the
detected audio.
The graphs in Figure 9 show the traces of noise response
for four different bandwidths of post detection filtering,
measured with respect to 30% mono modulation. It can be
seen that the noise floors improve steadily with increasing
levels of incoming 450 kHz as the value of the lower corner
frequency of the filter is increased. Data for the stereo noise
floors was collected with the decoder in the forced stereo
mode. The upper trace in Figure 9, labeled Audio Level,
shows the response, of the 30% mono signal transmitted, as
9-146
it appears at the decoder output. The change in response
level around 55 dBmV shows the characteristic of the total
decoder gain at lower signal inputs.
Figures 10 and 11, discussed briefly in the Function
Description Section, show the importance of using a quality
component at Pin 12. to ground. It can be seen that an
electrolytic capacitor leakage current of 600 nA can
unbalance the PLL to the point where stereo performance
may degrade to only 25 dB of separation with a
corresponding 2.0% distortion at 50% modulation levels.
The value of the capacitor connected to Pin 12 (47 IlF) is
also a factor in the determination of the low frequency corner
of the PLL circuit response. PLL responses appear in
Figure 12, plotted for three different values of loop filter
capacitor. The recommended value of 47 J.1F provides the
best response shape in this circuit where a Murata Products
CSA3.60MGF108 part is used.
Figure 13 presents the response of the AGC voltage
versus decoder input signal level in the application schematic
of Figure 2. The trace begins approximately at the point of
decoder sensitivity, and rises until reaching the area of stereo
sensitivity. Thereafter, the circuit responds in a near linear
fashion for the next 35 dB of input signal increase.
Figures 14 through 17 depict the VCC ripple rejection
performance for the MC13029A under mono and stereo
conditions for maximum and for no NRSC filtering. It should
be noted that this data was collected without any VCC
filtering. As one might expect, the ripple rejection is excellent
during mono conditions with approximately 45 dB of 50 Hz to
100 Hz ripple rejection at the high level of NRSC filtering.
Under stereo operation, the rejection is the same or better in
the 6.0 to 12 V range of operation, as can be seen in
Figure 16. When the decoder operates in stereo, the VCO is
functional, thus the decoder becomes more susceptible to
audio ripple on the VCC line. Under normal operating
conditions, with the recommended value of 47 J.1F at Pin 15
and 10 J.1F at Pin 8, a VCC ripple reading will be virtually the
same as measuring the noise floor of the IC.
MOTOROLA ANALOG IC DEVICE DATA
MC13029A
Figure 4. Single Channel Distortion
at 30% Modulation
Figure 3. Single Channel Separation
at 30% Modulation
10
0
-10
iD
E
z
-20
Desired
Channel
"'"
See Text
z
0
~
a: -30
..........
it
w
en
~
r- :-
1.0
r-....
f2en
.....
i5
Undesired
-40
Cjnnrl
-50
100
1000
10000
0.1
100
1000
f, FREQUENCY (Hz)
Figure 5. Signal Channel Separation
at 50% Modulation
-10
~ II
10000
f, FREQUENCY (Hz)
Figure 6. Single Channel Distortion
at 50% Modulation
Desired
Channel
See Texl
iD
E
z
-20
Q
!;;c
a:
it
w
-30
en
"-
-40
" i'~r-
Undesired
?hannel
0.1
-50
100
-40
-50
"
100
;-......,
10000
10
" ~LU
-20
-30
1000
Figure 8. Single Channel Distortion
at 65% Modulation
E
en
100
Figure 7. Single Channel Separation
at 65% Modulation
-10
-'
U-J...'-1..1-'-_--'---'---'--'-J...Wu...L_ _'---'--'--'--'.J...J..l..J
f, FREQUENCY (Hz)
iD
iii
-'
10000
f, FREQUENCY (Hz)
0
-'
w
1000
Desired
Channel
,
"
Undesired
Channel
:1000
f, FREQUENCY (Hz)
MOTOROLA ANALOG IC DEVICE DATA
10000
0.1
100
1000
10000
f, FREQUENCY (Hz)
9-147
MC13029A
1D
:E.
z
Q
5
::J
c
~
Figure 10. Decoder Separation versus Filter
Capacito~.(Pin 12) Leakage Current
Figure 9. Stereo Noise In Various
Bandwidths when Mono Transmitted
0
50
/~
-10
/"
-20
Audio Level
45
V
1D
~
·Noise
5.0 Hz to 3.0 kHz
....
1i'l
a: -40
5O/Z to, 3.0 kHz
.I
),
f2
~
40
~
35
en
30
j \.
/
0
0
:::; -30
w
:E.
z
~
w
1od J'iz to 3.0 kHz
-50
~
en
w -60
a:
25
400 Hz to 3.0 Hz
40
50
60
70
20
90
80
/
V
"
~
/
"
-600
-400
-200
0
200
~
400
SIGNAL STRENGTH (dB!1V)
LEAKAGE CURRENT (nA)
Figure 11. Decoder Distortion versus Filter
Capacitor (Pin 12) Leakage Current
Figure 12. Low Frequency Corner
of PLL Response
4.0
\
\
1\
\
-600
-400
"'-V
-200
0
/
200
/
V
400
/
-12
600
II
II
V
I
Loop Rtter 15 !1F
\ I
\. 1..1Loop Fitter 47 !1F
,.,....
\
600
1'01
~
Loop Fitter 4.7!1F
I'---
YI J
// I
1/ /
I
l II
I
10
100
MODULATION FREQUENCY (Hz)
LEAKAGE CURRENT (nA)
Figure 13. AGC Voltage versus
Input Signal Level
400
:[
..,........ ~
300
--'
w
iii
--'
w
(!)
200
~
§?
C,.)
~
100
o
I
~
40
50
V
./
60
f'
70
80
90
INPUT SIGNAL STRENGTH (dB!1V)
9-148
MOTOROLA ANALOG Ie DEVICE DATA
MC13029A
AM STEREO TUNERlFM STEREO IF
Description of Application
The MC13029A AM Stereo Decoder is combined with a
Sanyo LA1832 Tuner. The combination results in an AM
stereo tuner, along with an FM IF and FM stereo detector.
The MC13029A provides the means to switch the left and
right channel audio between the AM and FM. A MC145151
synthesizer controls the L.a. contained within the LA1832.
The circuit schematic is shown in Figure 18.
Circuit Board Description
The copper side layout and component locations are
shown in Figure 19. The dimensions in the figure give the true
size of the circuit board. With the exception of U2 and U3, all
components and jumpers are mounted on the side of the
board, away from the viewer.
Special Parts
Table 1 provides the Circuit function, part number, and the
manufacturer's name for special parts. The parts are
identified by their schematic symbol. Where the part is not
limited to a single source, a description sufficient to select a
part is given.
Table 1
U1
Ie-AM Stereo Decoder, MC13029A, Motorola
U2
Ie-AM/FM IF and Multiplex Decoder, LA 1832M, Sanyo
U3
Ie-Frequency Synthesizer, MC145151 DW2, Motorola
T1
AM IF Coil, A7NRE8-11148N, TaKa
F1
AM IF Ceramic Filter, SFG450F, Murata
F2
FM Detector Resonator, CDA10.7MG43, Murata
F3
FM Multiplex Decoder Resonator, CSB456F15, Murata
F4
AM Tuner Block, BL-70, Korin Giken
X1
10.24 MHz Crystal, Fundamental Mode, AT Cut, 18 pF
Load Cap, 35 n Max Series R, HC18/U Holder
X2
3.6 MHz AM Stereo Decoder Resonator,
CSA3.60F103, Murata
S5
8 Section SPST DIP Switch
Figure 15. Mono VCC Ripple Rejection
with Maximum NRSC Filter
Figure 14. Mono VCC Ripple Rejection
with No NRSC Filter
-20
300~F
'·~·f
-30
-v"
l
10k
10k
:§: Vee
iii"
:!2.
...J
-40
«
::>
c
Cii
w
a:
VCC=4.0V
I
it ICC=6.0V
j
-50
ICf
nt;--
-ji0
-:
VCC = 10 V
I
~
=
II
\
VCc= 12 V
T I I
100
100
1000
1000
RIPPLE FREQUENCY (Hz)
RIPPLE FREQUENCY (Hz)
Figure 16. Stereo VCC Ripple Rejection
with No NRSC Filter
Figure 17. Stereo VCC Ripple Rejection
with Maximum NRSC Filter
300~F
VCC=4.0V
-30
H-H-t-~---+-
100 mVpp
VCC=5.0V
C:
1~
Decoder
Vee
VCC=10V
100
RIPPLE FREQUENCY (Hz)
MOTOROLA ANALOG Ie DEVICE DATA
RIPPLE FREQUENCY (Hz)
9-149
II
Figure 18. MC13029A Decoder IC Application
!g
C421
. 10l1F +
.lC41
+ 10l1F
6~4:
~6k
Stereo a
FM
C10
10l!F
S ... 03 r
cnN;JI
...J.:t
~r~CIt ~
.T
3
-=
9 ~--..
8
~.T
U2
~---~19
~-~~~=-----~21
BL·70 ~tTu~ing Block
22
Konn Glken
~-t=:t===t===:;-----11-123
O
AMAnt'
Inpui..
2
U1
15
14
13
12
11
6
71---H-1f--J
6
5
4
3
'-=-------1 20
5
7
7
J±
.T J±
C54 0.01
7
7
9
C22;!;
,------{ 10
10l1F - .T
C23 - C1
10l1F -101!F
R41 M. ute Mute R17
OnOfi
47k·
18
17
16
4
..Ii
J f'(~~
7
CJ
7.l
+
10 k
C26.T
10l1F7
~
7
R2.
6.8 k
1~~F Left
+ f--o
AM
C13
0.001
Audio
Co)
2
;
R40
47 IR42
62k
7
~-~-~---~-----,
R39
3.3 k
!!:
o
a:u
C29
0.01
7
,..----4H
.T
+
o
!;
~
7
7
.T.T
§
c;
C
~
m
c
~
~
VCC
8.0V
Gnd1..
-
~
-C53
100l1F
-
R
...3!:
(')
X2
3.6 MHz
43.T
Mono
H
0 Right
C110l!FQ
0.001 ~
R3
6'8k
h
C3_
7
I4711F
~S6 f'1.
.
4.56 kHz Res Murata CS8456F15
C40 + CJ F3
.0I1 F T . l
~C6
c51
0.1I
.~
FMAudio
7::-
MC13029A
Figure 19. MC13029A Application Circuit Board
Shown 1112 Times Actual Size
II
1 4 - - - - - - - - - - - - 9.0cm - - - - - - - - - - - - - - - - 1
MOTOROLA ANALOG IC DEVICE DATA
9-151
MC13029A
CIRCUIT DESCRIPTION
To set the circuit to AM mode, Pin 12 of U2 must be pulled
to ground, as is Pin 1 of U1. This operation is shown in
Figure 20. Pin 12 of U2 must be isolated by a high impedance
when in FM mode. To allow switch S2 to accomplish the
switching of both ICs, the transistor 05 performs the
switching of Pin 12 of U2.
Figure 20. AMlFM Switch
LA1832
U2
MC13029A
U1
and R47 provide for the desired balance in audio levels
between AM and FM modes. FM de-emphasis is provided by
the capacitors C43 and C44. The output impedance of the
tuner at Pins 14 and 15 is 5.0 k. The series resistance R46
and R47 in combination with the input resistance at Pins 19
and 20 of U1 bring the effective resistance down to
approximately 4.0 k. For a 50 Ils de-emphasis, a capacitance
value of 0.012 IlF would be used for C43 and C44.
Figure 22. FM Audio Connection
Tuner to Decoder
LA1832
U2
MC13029A
U1
R45
AM when Low
II
The AM local oscillator is contained in U2 with the L.a. coil
located within the tuning block F4, and the coil connected to
Pin 23 of U2. See Figure 18. The secondary of the coil .is
tuned by a varacter contained in F4, and controlled by the
synthesizer IC U3. A buffer amplifier outputs the L.a.
frequency from U2 Pin 24, This sample of the L.a. frequency
is input to Pin 1 of the synthesizer IC U3.
The station signal is applied from a loop antenna (not
shown in Figure 18) to the primary of the RF coil contained
within the tuning block F4. The primary is tuned by a varactor
located within F4, and controlled by the synthesizer U3. The
coil secondary applies the signal to Pin 21 of U2 along with a
bias voltage from Pin 22 of U2.
The 450 kHz IF signal from the mixer is output from Pin 2
of U2. Refer to Figure 21. The IF signal is applied through the
IF coil T1 to the ceramic band pass filter F1. The signal is
then applied to Pin 4 of the tuner IC, U2 and to Pin 4 of the
decoder, U1. C54 is necessary to provide dc isolation
between Pin 4 of U2 and Pin 4 of U1.
-=
Provision for the application of AM de-emphasis is at
Pins 13 (left) and 14 (right) of the decoder U1. This is shown
in Figure 23. The tone response in AM mode is primarily set
by the IF bandpass filter F1. This response is shown in
Figure 28.
Figure 23. AM De-Emphasis
Left Channel Shown
VCC
MC13029A
Figure 21. IF Connection
MC13029A
U1
LA1832
U2
4
VCC
C54
Switching of the audio between AM and FM modes takes
place in the decoder IC, U1. The FM audio is conducted from
the tuner IC, U2 to the decoder as shown in Figure 22. R46
9-152
The NRSC recommended tone response is as shown in
Figure 24. The tones falling within the IF filter bandpass can
be contoured to this response by RC networks at Pins 13 and
14 ofthe decoder, U1.
MOTOROLA ANALOG IC DEVICE DATA
MC13029A
Figure 24. NRSC De-Emphasis
Curve for the United States
"'"
10 -2.0
E
z
Q -4.0
!;;:
z -6.0
w
::>
~
closed. This process is continued for all eight bits of the binary
number. Table 2 summarizes the switch settings for
1070 kHz.
Table 2
~
Switch
Number
Position
8
1
Open
\
\
-6.0
-10
100
200
500
1.0 k
2.0 k
5.0k
10k
f, FREQUENCY (Hz)
For muting, Pin 10 of U2 and Pin 18 of U1 must be pulled
high. This is done by switch 56 as is shown in Figure 25.
Figure 25. Mute SWitching
LA1832
U2
MC13029A
U1
VCC
Mu1eOn
R17
10
I
~
-=-
R41
7
0
Closed
6
0
Closed
5
1
Open
4
1
Open
3
0
Closed
2
0
Closed
1
0
Closed
Circuit Adjustments
The FM circuit requires no adjustments. The AM L.O. must
be able to tune from 990 to 2050 kHz to cover the broadcast
range. Adjust the core of the L.O. coil, if needed, to be able to
cover this range. The AM RF coil and trimmer can be
adjusted for best signal after connection to the loop antenna.
The coil is adjusted near the low end of the band, and the
trimmer is adjusted at the top of the band. The IF coil T1 is
first adjusted for maximum signal out of the filter F1. Final
adjustment is shown in Figure 26.
Figure 26. Decoder Signal Output for
Mistuned and Tuned Condition with Input
Signal of 80% L-R and 3.0 kHz
18
C30
A
The AM can be forced to mono by pulling Pin 10 of U1 to
ground. This is done by switch 54. Refer to Figure 18. The
FM can be forced to mono by pulling Pin 13 of U2 to ground.
This is accomplished by switch 53.
Component Choice
The pin function section of this data sheet gives the
information to select the proper components to be used with
the MC13029A decoder. A similar section in the LA 1832 data
sheet provides the information to choose the components for
the tuner.
Tuning
The frequency to which the AM tuner will tune is set by the
eight switches contained in the 55 assembly. 55 consists of
eight SPST switches. The switches are numbered from 1 to
8. Switch 8 connects to Pin 18 of the synthesizer, U3.
To tune each frequency, the switches are set to a pattern
corresponding to that frequency. The pattern is derived from
a binary number, equal to the local oscillator frequency
divided by 10kHz.
As an example, consider tuning to 1070 kHz. The local
oscillator is 1070 kHz + 450 kHz or 1520 kHz.
1520 kHzl10 kHz is 152. The binary equivalent of 152 is
10011000. The 1 represents an open switch. The 0
represents a closed switch. The left most bit of the binary
number is switch 8. Switch 8 is set open. Switch 7 is set
MOTOROLA ANALOG IC DEVICE DATA
Mistuned
B
Tuned
Apply an AM Stereo signal modulated with a 3.0 kHz tone
at 80% L-R. Set the pilot tone off. Observe either the left or
right channel audio. When T1 is properly adjusted, the
waveform should appear as waveform B shown in Figure 26.
Adjust T1 as required. If the waveform can only be adjusted
to appear as waveform A, then adjust for least amplitude and
equal amplitudes on both the left and right channels.
AM Circuit Test
The connections for test are as shown in Figure 27. A 50 a
resistor is placed on the AM antenna input. The AM Stereo
generator is connected to the AM antenna input.
Measurements of audio level are made with an audio
voltmeter with a high input impedance (1.0 MO).
Measurements of distortion in stereo mode are made using a
400 Hz high pass filter ahead of the distortion analyzer.
Typical data is shown in Figures 28 through 34.
9-153
MC13029A
Figure 27. Test Circuit
I
(""\
FM Generator
-!- 8.0 VSupply
T
I--
~
-=
Le
0-
Distortion Analyzer
400 Hz HP FiRer
D
D
I
Do-
10
0
Right Output
0
-b
(""\
50g
Shunting ?'
AM input
-'-
-i
Figure 28. Tone Response without
De-Emphasis Set by IF Bypass
II
FEr Probe
Left Output
MCl3029A1LAl832
Circun Board
c-aUAM
AM Stereo
Modulated
Generator
I
Audio Meter with
High Impedance Input
Figure 29. Tone Response with D.-Emphasis
5.0
5.0
0
0
r- ........
~
-5.0
~
........ r-..
10-
-5.0
~
.....
iC
:5!. -10
-10
-15
-15
-20
100
9-154
-20
1000
TONE (Hz)
10000
-25
100
1000
10000
TONE (Hz)
MOTOROLA ANALOG IC DEVICE DATA
MC13029A
Figure 31. Single Channel Distortion
at 50% Modulation
Figure 30. Single Channel Separation
at 50% Modulation
1.8
-5.0
1.6
-10
1.4
_ -15
~
5
5
-20
L
0 _25
-30
i--
-
-35
./
i'
100
o
~ 1.0
V
/
5
-20
5o -30
-40
-50
o
/
1
II
1\
0.6
./
0.4
1000
0.2
100
10000
10000
1000
TONE (Hz)
TONE (Hz)
Figure 32. Mono Characteristics
at 30% Modulation
Figure 33. Mono Characteristics
at 80% Modulation
Output
\
12
10
10
0
6.0
~
,
l iiI-1O
:z
o :s!I6.0 ~ ir -20
I~ 0~
4.0 ~
-30
5.0
Output
8.0
\
\
SIN
~
20
"-
-
Distortion
40
60
100
80
INPUT (dB~V)
2.0
-40
o
-50
4.0
g
~
3.0~
\
'.\
SIN\\
/
Distortion
\.'-.
o
120
~
I
\
~
o
!:!l 0.8
10
~-10
,
~1.2
I
I
I--\.
20
60
40
80
J
!a
2.0 0
1.0
100
o
120
INPUT (dB~V)
Figure 34. AMIFM Audio Switch Performance
of Left FM Channel with 1.0 kHz Audio Tone
0.05
20
\
0
iii
:s!UJ
en
:z
-20
0
0-
en -40
UJ
a:
-60
-80
-
l
0.03 :z
...........
.......
-
NOise_~/S+~L---
o
0.04
AU~O Output from MC13029A
100
""
-
200
~istortion
.¥'
V
0
~
0.02
~
!:!l
0
--
V
300
separaliln -
400
0.01
o
500
INPUT AUDIO (mV)
MOTOROLA ANALOG IC DEVICE DATA
9-155
II
®
MOTOROLA
MC13030
Advance Information
Dual Conversion
AM Receiver
DUAL CONVERSION
AM RECEIVER
The MC13030 is a dual conversion AM receiver designed for car radio
applications. It includes a high dynamic range first mixer, local oscillator,
second mixer and second oscillator, and a high gain AGC'd IF and
detector. Also included is a signal strength output, two delayed RF AGC
outputs for a cascode FET/bipolar RF amplifier and diode attenuator, a
buffered IF output stage and a first local oscillator output buffer for driving
a synthesizer. Frequency range of the first mixer and oscillator is 100 kHz
to 50 MHz.
Applications include single band and multi-band car radio receivers, and
shortwave receivers.
SEMICONDUCTOR
TECHNICAL DATA
• Operation from 7.5 to 9.0 Vdc
• First Mixer, 3rd Order Intercept = 20 dBm
• Buffered First Oscillator Output .
DWSUFFIX
PLASTIC PACKAGE
CASE 751F
• Second Mixer, 3rd Order Intercept =' +5.0 dBm
• No Internal Beats Between 1st and 2nd Oscillator Harmonics
• Signal Strength Output
• Limited 2nd IF Output for Frequency Counter Station Detector
PIN CONNECTIONS
• Adjustable IF Output Station Detector Level
• Adjustable RF AGC Threshold for Both Mixer Inputs
• Two Delayed AGC Outputs for Cascode RF Stage and Diode Attenuator
RFGnd
FETRFAGC
RFAGC2
RFAGCAdj
7
Representative Block Diagram
Mix! RF AGC Adj
IFGnd
SO IF Out
S Level Out
IF AGC In
AFOul
VCC
(Top View)
ORDERING INFORMATION
Device
This device contains 335 active transistors.
9-156
MC13030DW
Operating
Temperatura Range
TA
=-40° 10 +85'C
Package
SOlC-28
MOTOROLA ANALOG IC DEVICE DATA
MC13030
MAXIMUM RATINGS (TA = 25'C, unless otherwise noted.)
Rating
Symbol
Value
VCC
to
V
Operating Temperature
TA
-40 to +85
Storage Temperature
Tstg
-£5 to +150
Junction Temperature
TJ
150
'c
'c
'c
Power Supply
Unit
NOTE: ESO data available upon request.
ELECTRICAL CHARACTERISTICS (TA = 25'C, VCC = 8.0 V, unless otherwise noted.)
Condition/Pin
Symbol
Min
TyP
Max
Power Supply Voltage
Characteristic
-
VCC
7.5
8.0
9.0
V
Power Supply Current
VCC=8.0V
ICC
26
32
44
rnA
Unit
Detector Output Level
Yin = 1.0 mY, 30% Mod.
V13
160
200
240
mVrms
Audio SIN Ratio
Vin = 1.0 mY, 30% Mod.
SIN
48
52
-
dB
Audio THO
Vin = 1.0 mY, 30% Mod.
Vin = 1.0 mY, 80% Mod.
Yin = 2.0 mY, 80% Mod.
THO
-
0.3
0.3
0.4
1.0
1.0
1.5
%
Yin = Oto 2.0 V
Vll
0
-
5.2
V
-
V28
178
224
282
mV
Yin = 1.0 mY, Vll > V8
Vl0
2.3
2.7
3.3
Vpp
10r2toGnd
-
-
10
-
kQ
dBIlV
Signal Strength Output
VCO Buffer Output
SO Output Level
-
MIXERl
Input Resistance
Third Order Intercept Point
Conversion Transconductance
Total Collector Current
Input IF Rejection
10r2
IP3
-
127
-
1 or 2 to 24 + 25
gc
-
2.2
-
mS
24+25
IC
-
4.6
-
rnA
10r2
-
-
45
-
dB
MIXER2
Input Resistance
22
-
-
2.4
-
kn
Third Order Intercept Point
22
IP3
-
112
-
dBrN
22 to 20 + 21
gc
-
4.6
-
mS
20+21
IC
-
3.0
-
rnA
27 to 26
Rp
-
3.0
-
kQ
Buffer Output Level
28
Vo
-
224
Stray Capacitance
27
Cs
-
7.0
-
Conversion Transconductance
Total Collector Current
VCO
Minimum Oscillator Coil Parallel Impedance
mVrms
pF
IF AMPLIFIER
Input Resistance
Transconductance
Maximum Input Level
Minimum Detector Coil Parallel Impedance
RF Output Level
Audio Output Impedance
Audio Output Level
MOTOROLA ANALOG IC DEVICE DATA
17
Rin
-
2.0
-
kQ
17to 15
gm
-
28
-
mS
17
mVrms
Yin
-
125
-
17to 15
RL
-
15
-
kQ
15, Yin = 1.0 mV
-
-
2.0
-
Vpp
13
Rout
-
120
-
n
13@30%Mod.
Vout
-
200
-
mVrms
9-157
MC13030 '
Figure 1. Test Circuit
a.ov
47
Mixer2ln
1
1.0 l1F
0.1
IF
Input
0.1
I
IF Output!
Oetlnput
FET
Mixl
In
Mixerl Input
FO=I.0MHz
Mixl
In
RF
Gnd
RF
AGC
RF
AGC2
RF
Mixl
AGC RFAGC so
Adj
Adj Level
IF
Gnd
so IF
Out
S Level
IF
AF
Out AGC In Out
......j
0.1
-=10k
FET RF AGC Voltage - - - - '
+
10k
+
RF AGC Current +-_ _ _ _ _..J
II
Audio Out
Pi~
6 Current + - - - - - - - - - - '
SO Adjust
S Output Current
IF Signal Out
NOTES: 1. The transformers used for at the output of the mixers are wideband 1:4 impedance ratio. The secondary load is the 50 II input of the spectrum
analyzer, so the impedance across the collectors of the mixer output is 200 n.
2. Since the VCO frequency is not critical forthis measurement, a fixed tuned oscillator tuned to 11.7 MHz is used. This gives an input frequency
of 1.0 MHz.
3. The detector coil is loaded with a 10k resistor to reduce the tuned circuit Q and to present a 10 kll load to the IF output for detennination of IF
transconductance.
.
4. The RF AGC current, S output current and Pin 6 current are measured by connecting a current measuring meter to these pins, so they are effectively
shorted to ground.
5. SD adjust is adjusted by connecting a power supply or potentiometer and voltmeter to Pin 8.
FUNCTIONAL DESCRIPTION
The MC13030 contains all the necessary active circuits for
an AM car radio or shortwave receiver.
The first mixer is a multiplier with emitter resistors in the
lower, signal input transistors to give a high dynamic range. It
is internally connected to the first oscillator (VCO). The input
pins are 1 and 2. The input can be to either Pins 1 or 2, or
balanced. These pins are internally biased, so a de path
between them is allowable but not necessary. The mixer
outputs are open collectors on Pins 25 and 26. They are
normally connected to a tuned transformer.
The first oscillator on Pin 27 is a negative resistance type
with automatic level control. The level is low so the Signal
does not modulate the tuning diode capacitance and cause
9-158
distortion. Pin 26 is the reference voltage for the oscillator
coil. This reference is also the supply for the mixer circuits.
The upper bases of the mixer are 0.7 V below this reference.
The second mixer is similar to the first, but it is singleended input on Pin 22. Its outputs are open collectors on
Pins 20 and 21 which are connected to a tuned transformer.
The dynamic range of this mixer is less than the first. It is also
connected internally to an oscillator which 'is normally crystal
controlled. The oscillator is a standard Colpitts type with the
emitter on Pin 19 and the base on Pin 18.
The IF amplifier input is Pin 17. The AGC operates on the
input stage to obtain maximum dynamic range and minimum
distortion. The IF output, Pin 15, is a current source.
MOTOROLA ANALOG IC DEVICE DATA
MC13030
Therefore, its gain is determined by the load impedance
connected between Pins 15 and 16. Pin 16 is a voltage
reference for the output. The output is internally connected to
the AM detector, and Pin 13 is the detector output. This
detector also provides the AGC signal for the IF amplifier. An
RC filter from Pin 13 to 12 removes the audio, leaving a dc
level proportional to the carrier level for AGC.
Pin 11 provides a current proportional to signal strength.
I! is a current source so a resistor must be connected from
Pin 11 to ground to select the desired dc voltage range. The
current is proportional to the signal level at Pin 17, the IF
amplifier input.
A high--gain limiting amplifier is used to derive the station
detect (SO) signal output on Pin 10; this output is present only if
it is turned on by the voltage on Pin 8. If the voltage on
Pin 8 is less than the voltage on Pin 11, the output on Pin 10 is
"on". The station detector IF output on Pin 10 is used with
synthesizers which have a frequency counting signal detector.
The RF AGC outputs on Pins 4 and 5 are controlled by the
signal levels at Mixer1 or Mixer2. Bypass capacitors are
required on Pins 6 and 4 to remove audio signals from the
AGC outputs. Pin 4 is designed to control the NPN transistor
in series with the RF amplifier FET. The voltage on Pin 4 is
5.1 V with no input signal and decreases with increasing input
signal. Pin 5 is designed to control an additional AGC circllit
at the antenna input. The voltage on Pin 5 is at 0 V with no
input Signal and increases with increasing input signals. The
voltage on Pin 5 does not increase until the voltage on Pin 4
has decreased to about 1.3 V. In most cases, Pin 5 is used to
drive a diode shunt. Maximum output current is about 850 /IA.
The RF AGC sensitivity is about 40 mVrms input to Mixer1
or about 2.0 mVrms input to Mixer2 at 1.0 MHz. The AGC
sensitivity for both mixers can be decreased by adding a
resistor from Pin 6 to ground. There is also an additional
amplifier between Mixer1 and its AGC rectifier. The gain of
this amplifier and AGC sensitivity for Mixer1 can be increased
by adding a resistor from Pin 7 to ground. Therefore, the
desired AGC sensitivity for both mixers can be achieved by
changing the resistors on Pins 6 and 7.
S Out versus IF Input:
The S output current at Pin 11 is provided by two
collectors, one a PNP source and the other a sink to ground.
The desired S output voltage can be selected using the curve
of Figure 3 and calculating the value of the required resistor.
Figure 3. S Output Current versus IF Input Level
70
~
60
V
~
IZ
w
cc
cc
=>
u
40
z
;s:
V
/
./
;::
20
o
L
V '"
I--
30
40
50
60
70
BO
IF INPUT LEVEL (dBILV)
RF FET AGC versus Mixer1 and Mixer2 input Level:
Figures 4 and 5 are generated with no external resistance
on Pins 4 or 6, so they represent the minimum RF AGC
sensitivity of Mixer1 and Mixer2.
Figure 4. RF AGC Voltage versus Mixer1 Input
5.0
--- .~
-....
~
4.0
~
w
(!J
~
3.0
z
2.0
~
..,.
;s:
\
Mixlln
5.1 V
3.3 V
Mixlln
5.1 V
OV
RFGnd
5.1 V
FETRFAGC
7.BV
RFAGC2
7.BV
RFAGCAdj
6.5V
5.1 toOV
Oto B50 IJA
Ot02.BV
200mV
43mV
Ot04.BV
OV
6.5V
Oto4.BV
3.6 to 4.5 V
3.6 to 4.5 V
B.OV
4
1.0
\
3.7V
SD Level
Mix20ut
7.9V
IFGnd
Mix20ut
7.9V
SDIFOut
XlalOscE
4.4 V
S Level Out
XlalOscB
5.0V
IFAGCln
AFOut
VCC
o
90
85
IFln
DetVref
Detln
MOTOROLA ANALOG IC DEVICE DATA
4.BV
95
100
105
MIXER 1 INPUT LEVEL (dBILV)
Figure 5. RF AGC Voltage versus Mlxer2 Input
5.0
Mix2ln
Mixl RF AGC Adj
II
l\
Figure 2. Pin Connections and DC Voltages
3.3V
100
90
-r-..
4.0
~
w
(!J
~
3.0
0
>
..,.
z 2.0
;s:
~
1,\
~
1.0
o
65
~
70
75
BO
MIXER21NPUT LEVEL (dBILV)
4.1 V .
4.1 V
&-159
MC13030
Pin 6 Current versus Mixer1 and Mlxer2 Input. Level:
The· internal resistance from Pin 6 to ground is 39 k.
The RF AGC voltage on Pin 4 is 2.0 V when the voltage on
Pin 6 is 1.2. V. Therefore, the desired AGC thresholds for
either mixer can be set with these curves. The design steps
are described in the design notes.
Mixer1 AGC Gain Increase versus R7:
Adding a resistor from Pin 7 to ground increases the AGC
sensitivity of Mixer1. The range of increase in dB can be
found from this curve. This is useful after setting up th.e AGC
threshold of Mixer2.
FiSiure 8. Mlxer1 AGC Gain Increase versus R7
-
Figure 6. Pin 6 Current versus Mixer1 Input Level
250
<.2,
/
200
/
I-
z 150
w
IX:
IX:
::>
(.)
'"a::z
~
100
50
~
V
~
/
::>
II
(.)
'"a::z
100
/
50
L
V
~
w
~
IX:
110
80
'"
1'1'
r--...
4.0
2.0
1.0
0
100
",
.... 1'1-0
1.0k
120
10k
R7
Pin 5 Current versus Pin 4 Voltage:
All the curves give Pin 4 AGC voltage versus some other
input level. This curve can be used to determine the auxiliary
AGC current from Pin 5 at a given Pin 4 voltage.
./
Figure 9. Pin 5 Current versus Pin 4 Voltage
5.0
4.0
w
(!)
ti
g
3.0
.".
2.0
z
a::
o
....
~ 3.0
Figure 7. Pin 6 Current versus Mixer2 Input Level
150
'-
:ij
250
IX:
IX:
i5
~
a:
MIXERl INPUT LEVEL (dBI1V)
'Z
w
7.0
6.0
~ 5.0
/
100
90
1
~
U)
~
o
200
~ 8.0
90
100
110
120
i'-....
1.0
MIXER2INPUT LEVEL (dBI1V)
o
o
...............
"-----
0.4
-
~
0.8
1.2
PIN 5 CURRENT (rnA)
9-160
MOTOROLA ANALOG IC DEVICE DATA
MC13030
PIN FUNCTION DESCRIPTION
Pin No.
Internal Equivalent Circuit
Description
2
3~
3
RFGround
This should be connected to the ground used for the RF circuits.
4
FET RF AGC Output
This is the AGe for the cascode transistor connected to the RF amplifier
FET. The no--signal voltage is 5.1 V. The voltage decreases with
increasing input signals. A bypass capacitor and electrolytic capacitor
must be added to filter out RF signals on the transistor and audio signals
in the AGC signal. See Figures 4 and 5.
10k
4 0--*-----,
5
Mixer1 Input
Pins 1 and 2 are equivalent. In the application circuit, 2 is grounded
with a capacitor and 1 is the input. If a load resistor is needed for the
input filter, it can be placed across Pins 1 and 2. Input impedance for
each pin is 10k. IP3 (third order intercept) at the input is 20 dBm
(127 dB~). To guarantee -50 dB 1M3, the input level should not be
greater than 3.5 dBm (1 03 dB~) (150 mVrms).
RF AGC2 Output
The voltage on this pin starts at 0 and increases with increasing input
signals. It is normally used to tum on diodes or a transistor connected
across the antenna input and is AGe delayed until Pin 6 reaches 2.7 V.
If the voltage on Pin 5 decreases below 2.0 V, the voltage on this pin will
decrease from 3.1 down to about 1.5 V. The maximum output current is
about 850 ~A.
100
6
RF AGC Adjust
An electrolytic capacitor of 1.0 ~F must be connected to prevent audio
modulation of the AGC circuits. If there is no resistor on this pin, the RF
AGC starts at an input level to Mixer1 = 40 mVrms or Mixer2 = 2.0 mVrms.
Connecting a resistor from Pin 6 to ground increases RF levels required
for AGC to start. It should be used to set the desired AGC level of Mixer2.
If a resistor is not connected to Pin 6, unwanted RF signals will cause the
AGe to start at a very low level, and desired signals may be suppressed.
6 o----+-------"N\,---j
7
Mixer1 RF Level Adjust
A resistor from Pin 7 to ground will increase the gain of an amplifier from
the input of Mixer1 to the AGC circuit. It can be used to set the RF AGC
level of Mixer1. The minimum value of R7 is about 680 Q.
8
Station Detector Signal Level Adjust
A voHage on Pin 8 will set the desired Signal strength at which the SD IF
Out on Pin 10 appears. The other input to this comparator is the S (signal
strength) signal. If Pin 8 is grounded, a square wave 01 the 2nd IF (usually
450 of 455 kHz) is present with very small input levels. This output could
also be used to drive an FM detector if desired.
s
9
9~
MOTOROLA ANALOG IC DEVICE DATA
IF Ground
Pin 9 is the ground lor the IF section.
9-161
II
MC13030
PIN FUNCTION DESCRIPTION (continued)
Pin No.
Description
Internal Equivarent Circuit
10
Station Detector IF Output
This output is "on" when VII> VB. The output is an amplified and limited
2nd IF signal. The signal level is ~ 250 mVpp when it is 100% "on".
IF
10
so
Vee
11
S Level Output
This is a de current proportional to IF input level. With a load resistor of
75 k, the dc voltage is 0 to 5.1 V.
11
510
r>---"/V\~"
Vee
12
12
Vee
13
II
13
14
~
+
oo
140------ Vee
IFAGCln
The IF gain is controlled by the dc voltage on this pin. It is normally
connected to Pin 13 through an RC network to filter out the audio signal
on Pin 13. The IF gain is maximum when V13 ~ 3.6 V. When V13
increases, the IF gain decreases.
Audio Output
The dc voltage on Pin 13 is ~ 3.6 V with no input signal and increases to
~ 4.5 V at minimum IF gain. A nonpolarized electrolytic capacitor may be
required to couple to the audio circuits if the audio amplifier dc bias
voltage is between these voltages.
Supply Voltage
The nominal operating voltage is B.O V.
15
IF Amplifier Output and Detector Input
The detector coil must be connected between Pin 15 and 16. The IF
amplifier output is a current source, the IF amplifier is a transconductance
amplifier; the gain is determined by the impedance between Pins 15 and
16. The IF amplifier gm ~ 0.028 mho. If a wide bandwidth IF is desired, the
detector coil can be connected between Pins 15 and 16 without a tap and
then loaded with a resistor across the coil.
16
Detector Reference Voltage
One side of the detector coil is connected to this pin. It should be
bypassed with a 0.1 I!F capacitor.
9-162
MOTOROLA ANALOG IC DEVICE DATA
MC13030
PIN FUNCTION DESCRIPTION (continued)
Pin No.
Internal Equivalent Circuit
Description
17
IF Input
The IF input impedance is 2.0 k to match most ceramic 455 or 450 kHz
filters. For a ceramic filter requiring a 1.5 k load, a 5.6 k resistor in
series with a 0.01 ~F capacitor should be connected from Pin 17 to
ground.
170-_---[
18
Crystal Oscillator Base
The crystal oscillator is a simple Colpitts type, operating at a low
current. The crystal should operate at 10.250 MHz for 450 kHz IF or
10.245 MHz for 455 kHz IF with a 20 pF load capacitance. The
oscillator signal to the second mixer is coupled from Pin 18 through an
emitter follower. If a synthesizer such as the Motorola MC145170 with
a 15 bit programmable R counter is used, the 10.245 MHz crystal can
be connected to the synthesizer, and a 200 mVpp oscillator signal
from the synthesizer can be capacitively coupled to Pin 18, so only
one crystal is needed.
19
19
Crystel Oscillator Emitter
The capacitive divider from Pin 18 is connected as shown in the
application circuits of Figures 10, II, 12.
20,21
20
21
22
Mixer2 Output
The maximum AC collector voltage is about 5.8 Vpp or 2.0 Vrms. The
mixer conversion transconductance gc = 0.0046 mho. The load
impedance should be selected so the mixer output does not overload
before the input.
Mixer2 Input
The input impedance is 2.4 k. A series R-G network from Pin 22 to
ground or a resistor from the fillerto Pin 22 can be used to properly
match the filter. In most cases, a 10.7 MHz crystal filter can be connected
to Pin 22 directly without any additional components. IP3 (third order
intercept) at the input is 5.0 dBm (112 dB~). To guarantee -50 dB 1M3, the
input level should not be greater than -20 dBm (87 dB~) (22.7 mVrms).
23~
+ 6.5V
23
-
Vref
24,25
Vref
This is the main reference voltage for most of the circuits in the IC and
should be bypassed with a 1.0 ~F capacitor.
Mixer1 Output
The maximum collector voltage is about 5.8 Vpp or 2.0 Vrms. The mixer
conversion transconductance gc = 0.0022. The load impedance should
be selected so the mixer output does not overload before the input.
veo
MOTOROLA ANALOG IC DEVICE DATA
9-163
MC13030
PIN FUNCTION DESCRIPTION (continued)
PinNa.
Description
Internlill Equivlillent Circuit
Vee
26
VCO Reference
The first oscillator coil is connected from Pin 26 to 27. Pin 26 must be
bypassed to ground with a capacitor which has a low impedance at the
.oscillator frequency. This capacitor also will reduce the phase noise of
theVCO.
260---<1>--27
VCO
27
to Mixert
The VCO is a negative resistance type and has an Internal level control
circuit so a tapped coil or one with a secondary is not needed. The level
is fixed at 0,8 Vpp so the oscillator signal does not modulate the tuning
diode, thus keeping the distortion low. The oscillator stray capacitance is
= 12 pF and the tuned circuit impedance should be greater than 3,0 k to
guarantee oscillation, Oscillator range is up to 45 MHz so it can be used
for SW receivers.
VCOOut
28
The output level is 240 mVrms (108 dBf1), high enough to drive any
CMOS synthesizer.
..
28o---~,~-
AM CAR RADIO DESIGN NOTES
The MC13030 AM Radio IC is intended for dual
conversion AM radios. In most cases, the 1st IF frequency
(F,F1) is upconverted above the highest input frequency. The
first oscillator (VCO) is tuned by a synthesizer and operates
at Fin + F,F1. For the 530 to 1700 kHz AM band with a
10.7 MHz first IF, the VCO goes from 11.23 to 12.40 MHz.
Therefore, Fmax/Fmin for VCO is only 1.104, so one low-cost
tuning diode can be used. Since the required tuning voltage
range can be made less than 5.0 V, it may also be possible to
drive the tuning diode directly or from the phase detector of
the synthesizer IC, such as the Motorola MC145170,
operating from 5.0 V, without using a buffer amplifier or
transistor.
If the veo is above the incoming frequency, the image
frequency of the first mixer is at fOSC + FIF1. For the AM
broadcast receiver, it is around 22 MHz, so a simple LPF
can be used between the RF stage and Mixer1 input.
However, if a LPF is used, an additional coil is still needed
to supply the collector voltage of the RF amplifier. For this
reason, a BPF filter was used in the application circuit
instead, since it uses the same number of coils and gives
better performance. It is simply a lowpass to bandpass
conversion. The lowpass filter is designed to have a cutoff
frequency equal to the desired bandwidth. In this case, it
would be 1700 - 530 kHz = 1170 kHz. Then, it is
transformed to be resonant at 949 kHz, the geometric
mean of the end frequencies: '11'1700 x 530 949 kHz.
A balanced-ta-unbalanced transformer is required at the
output of both mixers. The first one is designed so that Mixer1
has enough gain to overcome the loss of the 10.7 MHz filter
and so that the output of the mixer will not overload before the
input. The primary impedance of the transformer is relatively
low, and it may be difficult to control with commonly available
7.0 mm transformers because the number of primary turns is
=
9-164
quite small. It would also require a large tuning capacitance.
A better solution is to tune the secondary with a small
capacitance and then use a capacitive divider to match the
tuned circuit to the filter. This allows one transformer to be
used for either a ceramic or crystal filter. The capaCitors can
be adjusted to match the filter. The recommended coil is
made this way.
If the formula: Pin IP3 - DRl2 is used, the maximum input
level to the mixer can be calculated for a desired dynamic
range.
IP3 3rd order intercept level in dB (dBm or dB!!)
DR dynamic range in dB between the desired signals
and 3rd order intermodulation products
Pin input level in dBm or dB!!
The RF AGC level can then be adjusted so that Pin does
not exceed this level.
Whether or not a narrow bandwidth crystal or wide
bandwidth ceramic filter is used between the first and second
mixers depends on the receiver requirements. It is possible to
achieve about 50 dB adjacent channel and 1M rejection with
a ceramic filter because of the wide dynamic range of the
mixers. If more than this is required, a crystal filter should be
used. If a crystal filter is used, a lower cost CFU type of
455 kHz second IF filter can be used. If a ceramic filter is
used, a CFW type filter should be used because there is no
RF section selectivity in this type of radio.
Since the wideband AGC system is quite sensitive, it can
be set to eliminate all spurious responses present at the
receiver output. However, the RF AGC will sometimes
eliminate or reduce the level of desired signals if there is a
strong signal somewhere in the bandpass of the RF circuit.
The second mixer is designed like the first and requires a
balanced output. Since its load impedance is higher, the
transformer can be designed to be tuned on the primary or
=
=
=
=
MOTOROLA ANALOG IC DEVICE DATA
MC13030
secondary, but, like with the one for the first mixer, if the
secondary is tuned, the tap can be adjusted for the
impedance of the 455 kHz filter. Wideband filters usually have
a higher terminating resistance than the narrowband ones.
The recommended coil is made this way.
The IF amplifier is basically a transconductance amplifier
because the output is a current source. The output is also
internally connected to a high impedance AM detector. gm for
the IF amplifier is ~ 0.028 mho. The voltage gain will be the
detector coil impedance x 0.028. This can be designed to
give the desired audio output level for a given RF input level.
If it is set too high, the receiver may oscillate with no input
signal. The application circuit was designed for a relatively
narrow bandwidth, so a tapped detector coil is used to get the
desired gain. If a wide bandwidth receiver is desired, the
detector coil can be untapped, and a resistor can be added
across the coil to get the desired Q.
The detector output on Pin 13 is a low impedance. It
supplies the IF AGe signal to Pin 12, so the audio must be
filtered out. The time constant of this filter is up to the
designer. The main requirement is usually the allowable
audio distortion at 100 Hz, 80% modulation. If the time
constant is made too long, the audio level will be slow to
correct when changing stations.
The Signal Strength (S) output is dependent only on the
IF amplifier input level. Its maximum voltage is about 5.0 V
with a 75 k load resistor. The range can be reduced by
using a lower value for the resistor on Pin 11. The S signal
will stop increasing when the RF AGe circuits become
active, so if the RF AGe threshold is set too low, or there is
too much loss from the Mixer2 output to the IF input, the
maximum S signal will be reduced. The desired load
resistor on Pin 11 (R11) can be determined using the curve
of Pin 11 current versus IF input.
MOTOROLA ANALOG IC DEVICE DATA
Setting the RF AGe threshold is probably the most difficult
because a tradEH>ff between allowable interference and
suppression of desired signals must be made.
First select the values for both mixers:
d. Using the formula Pin =IP3 - DRl2
Select the desired dynamic range and calculate the
maximum input levels for both mixers. Remember that all
levels must be in dB, dBIlV or dBm. Let DR =50 dB. IP3
for Mixer2 =112 dBIlV. Therefore, Pinmax =87 dBIlV. IP3
for Mixer1 =127 dBIlV. Therefore, Pinmax = 102 dBIlV.
e. First, adjust the resistor from Pin 6 to ground to give
the desired maximum input level to Mixer2. From the
curve of Pin 6 current versus Mixer2 input level,
R6 =1.21110 IlA = 11 k. Rint =39 k, so R6ext =15 k.
f. From the curve of Pin 6 current versus Mixer1 input level,
determine how much more gain would be required in the
Mixer1 AGe circuit to achieve the desired dynamiC range
for Mixer1. From the curve of Relative Sensitivity versus
R7 determine the value of R7. Alternatively, R7 can be
adjusted to give the desired maximum input level to
Mixer1.
The resulting R7 may be too small to set the AGe
threshold of Mixer1 as low as desired. Also, if R7 is less than
680 n, the AGe sensitivity for the Mixer1 input falls off at
higher frequencies, so in these cases, the resistor from Pin 6
to ground must be reduced to achieve the desired level
because the overload of Mixer1 provides the most important
spurious response rejection. However, if the AGe level is set
too high, the IF in signal may become too large and the IF
amplifier can overload with strong signals. The values used in
the application are more conservative.
The gain from the antenna input to the point being
measured are shown on the AM radio application. These are
helpful when calculating audio sensitivity and troubleshooting
a new radio.
9-165
II
Figure 10. AM Radio Application
Ceramic Fitter
8.0 V
!g:
RFln
2200pF
.
R18
11213
1.5 k
1 2 3
I 10.5X
C25
~0.Q1
I
C19
22pF
R13
R5
47
33k
.".
I
Fl2 CFU455H2
CFW455H
-01
MV209
~
C20
0.1~
C4
--l
0.01
C2
1°·1
R3
loOk
SKl 07MfrAE-l OA
lOM7A
.-11-
Tuning Voltage
1.0-7.0 V
FL1
~F~iII ~,.~~
C27
C30
330pF
Al
I
88X
Gnd Gnd Gnd In
_I
120pF
_I
.1
3:
....
281 271 261 25
(')
WEQc::a:c:
8~g;88g;~88
~
~i~~~~~
C16
130X
51 Out
C13
~ ~ !!; ~ ~
(0)
C17
R17
120pF
180k
~
4.5X
~
~
~
~
ii~
~~
8.0 V
s:
a
.".
e
~
6
Ii)
(';
8.0V
L3
220¢i
~m
c
02
lN4148
~
)Ii
.".
or R6~
1
R
11i=1 33k 11.0k
RVl
lOOk
.".
C22
0.1
:t
C7Jt
C15
0.11
_
03
- lN4148
r·711F
56k
120pF
c
C9c!;
R14
C18
Rl
loOk
R9
IF Output 10Signal Detector
.
Rl0
68k
*
~
C23
0.Q1
r·=
711F
AFOul.
O104.8V
Signal Strength
S
o
MC13030
SW RADIO DESIGN NOTES
CB RADIO DESIGN NOTES
The shortwave receiver was designed to cover from 5.0 to
10 MHz. This MC13030 radio has better performance than
most receivers because of the high dynamic range and
spurious rejection of the mixers.
The RF stage bandpass filter for this radio is the same type
as the one used for the car radio, but the series tuned section
was scaled down in impedance to reduce the inductance of
the coil.
Since most SW receivers include an SSB and CW mode,
the detector coil could have a secondary winding to supply
the second IF signal to this section.
The capacitors C10 and C23 have been reduced from
those in the AM radio so that the AGC system can follow
variations in signal level due to fading.
The RF stage bandpass filter for this radio consists of a
tuned input and a double tuned interstage filter. For lower cost
radios, a single tuned interstage filter could be used.
The schematic also shows a crystal 10.7 MHz 1st IF filter, but
a ceramic or coil filter could also be used. An intermodulation
rejection of 50 dB can be obtained with a ceramic 1st IF filter.
A bipolar transistor is shown for the RF stage. A dual gate
CMOS FET could also be used with G2 connected to the
AGC voltage on Pin 4. A PIN diode is recommended for 02.
COIL DATA
T1 - Taka A119ANS-19335UH
T2 - Taka A7MNS-12704UH
T3 - Taka A7MCS-12705Y
II
MOTOROLA ANALOG IC DEVICE DATA
9-167
II
Figure 11. 5 to 10 MHz Radio Application
8.0V
!
.,-
aI
CD
C28
C26
11~T~
"""
f'
"
I
Tuning
Voltage
A1
RFln
C19
100pF
R14
RS
47
-=-
L6
33k
I
56 pF
~
"@
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Figure 12. CB Radio Application
B.OV
-,.-
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~
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e
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Voltage
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16.265 to 16.705 MHz·
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ffiJ-8
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1.5 k
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56 PFTR12
R7
Crystal Finer
C28
2200pF
C26
0104.8V
Signal Strength
MC13030
Figure 13. Printed Circuit Board
4.0"
~I
(Top View)
NOTE: J ~ Jumper
II
3.0"
4.0"
(Bottom View)
9-170
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13060
Mini-Watt Audio Output
This device is a rugged and versatile power amplifier in a remarkable
plastic power package.
MINI-WATT
AUDIO OUTPUT
• Supply Voltages from 6.0 Vdc to 35 Vdc
• 2.0 W Output @ 70°C Ambient on PC Board with Good
Copper Ground Plane
SEMICONDUCTOR
TECHNICAL DATA
• Self Protecting Thermal Shutdown
• Easy to Apply, Few Components
• Gain Extemally Determined
• Output is Independent of Supply Voltage Over a Wide Range
DSUFFIX
PLASTIC PACKAGE
CASE 751
(SOP-8)
PIN CONNECTIONS
Power Type
Lead Frame
Figure 1. Simplified Application
Vee = 6.0V to 35V
1.0f.lF
Audio o---i + 5
Input
Output
1
Gnd {
2
Speaker
16J32Q
Vee
4
(Top View)
6.8
+
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC13060D
TA =-40 to +85°C
SOP-8
Figure 2. Thermal Resistance & Maximum Power Dissipation
versus PC Board Copper
160
~
I
I
140
a:
I'...
::>
rP>
[
a:
r---
o
~ 40
I
r--l
20
30
40
50
L, LENGTH OF COPPER
MOTOROLA ANALOG IC DEVICE DATA
9-171
MC13060
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
35
V
1.0
Vpp
Thermal Aesistance, Junction to Air
AaJA
160
°CIW
Thermal Aesistance, Junction to Case
°CIW
,RatIng,
Power Supply Voltage
Audio Input, Pin 5
AaJC
25
Junction Temperature
TJ
150
°C
Operating Ambient Temperature Aange
TA
-40 to +85
°C
Tstg
-65 to +150
°C
Storage Temperature Aange
ELECTRICAL CHARACTERISTICS (TA = 25°C, circuit of Figure 3, unless otherwise noted.)
I
I
Characteristics
I
Symbol
Min
Typ
Max
Unit
AUDIO SECTION
Power Supply Current, No Signal
ICC
-
mAde
Ao
-
13
Gain
50
-
VN
Distortion at 62.5 mW Output, 1.0 kHz
THD
-
0.2
1.0
%
Distortion at 900 mW Output, 1.0 kHz
THD
-
0.5
3.0
%
Quiescent Output Voltage, No Signal
VPin 1
-
8.4
Vdc
-
0.7
-
28
-
kn
0.5
4.0
mVrms
Input Bias
VPin 5, VPin 8
Input Aesistance
Ain, Pin 5
Output Noise (50 Hz to 15 kHz) Input 50 D
Vout
Vdc
GENERAL DESCRIPTION
II
The MC13060 is a quasi-<:omplementary audio power
amplifier, mounted in the SOP 8 (power SOIC package). It is
well suited to a variety 01 1.0 Wand 2.0 W applications in
radio, TV, intercom, and other speaker driving tasks. It
requires the usual external components for high frequency
stability and for gain adjustment.
The output signal voltage and the power supply drain
current are very linearly related, as shown in Figure 5. Both
are quite constant over wide variation of the power supply
voltage (above minimum VCC for clipping, of course). The
amplifier can best be described as a voltage source with
about 1.0 App capability. On a good heatsink, it can deliver
over 2.0 W at 70°C ambient.
The MC13060 will automatically go into shutdown at a die
temperature of about 150°C, effectively protecting itself, even
on fairly stiff power supplies. This eliminates the need for
decoupling the power supply, which degrades performance
and requires extra components.
Input Pins 5 and 8 are internally biased at 0.7 Vdc and
should not be driven below ground.
Figure 3. Test Circuit
1.011F
Audiolnput
~ +
50
1
100l1F
+
6,7
3.0
16D
330
Load
::t. 0.1
6.8
9-172
MOTOROLA ANALOG IC DEVICE~DATA
MC13060
All Curves Taken in the Test Circuit of Figure 3, Unless Otherwise Noted.
Figure 4. Quiescent Supply Current and
Output Voltage versus Supply Voltage
Figure 5. Supply Current versus Output
20
,,:g
18
~~
16
-/
Signal = 0
gj ~ 14
13
i:!!
oa:
12
"0
=> 10
z
w
a:
a:
=>
1/
./' Vo(OC)
~ ~ 6.0
~
200
180
Q
120 I - - 100 I - 80
=>
6
60
.9
10
20
30
Vcc, SUPPLY VOLTAGE (Vdc)
2.0
~
~
f?
!a
01111
1.8
1.6
1.4
I I
I I
1.0
"-
0
Q
~ 1.0
a: 0.8
1.0
1\
~
f?
0.4
ci 0.2
:x:
J...I.-II
0
t-
100
10
1.0k
t, FREQUENCY (Hz)
" ....- -
w
~ 1.0
:E-
z
32 0 Load
~
z
0
~
en
a
(f)
/
1.0
a:
w
~
"-
I
I...---'"
Cl
>
-4.0
f?
0.4
-5.0
j:!: 0.2
w
a:
V
V
v.... ""
I/h V
~~
6
"-
I
,,'
",."
---
20~
24 V
1'="
",'
;>
,
a
V
~
/
gj
0 1.0
!
16V
~
MOTOROLA ANALOG IC DEVICE DATA
1/1
H'
160 Load
Q
......
1.0
32 Vl320
1.0
2.0
Po, POWER OUTPUT eN)
0.1
~
z
....
1%
THO
Po, POWER OUTPUT (W)
I
r-I
10
Figure 9. Dissipation versus Output Power
V
0
I!
IJ-. 24 Vl16 0
-
I-
ci
I
28V
8.0
!J
~ 0.6
2.0
Vcy=32V
7.0
I I \I
Figure 8. Dissipation versus Output Power
2.0
II
I
«
iil
-£.0
10k
2.0
3.0
4.0
5.0
6.0
SINE WAVE OUTPUT VOLTAGE (Vrms)
1.6 f-- 400 Hz- _.16V1160
f?
!a 1.4 r-- Signal_
- 24V132 0
o
~ 1.2
0.8
~.O
THO
I
~
~ ~
2.0
~
3 0.6
g
3.0
1.0
Gain
RL =~, VCC=32V
Figure 7. Distortion versus Power Output
2.0
II
1.2
o
I I 11111111
.,......
.......,
...... ~
20
~2.0
1.8
4.0
VCC=116IV' RL = 160, 0.5 W
V
RL=320,_
VCC=32'!,... ~
./
./' ........ i/'"
40
o
o
40
/"
V
Figure 6. Distortion and Gain versus Frequency
_
RL=160
VCC=24V
(f)
/'
o
o
V
140
::;
""-
./
84.0
2.0
160
2.0
V
-
VCC=24V17
~
20V
~
j/
/,
1//. ......
rtl
r
....
7"
~%~HO-
~.
16V
1.0
2.0
Po, POWER OUTPUT (W)
9-173
II
MC13060
Figure 10. Representative Schematic Diagram
r-_---__;~-__.__---.-__;~.._-<>
Audio Vee
4
01
.-~_<>
Audio
1 Output
Audio 0---,..-----'
Input 5
Audio 0--.._-----'
Feedback 8
rtf' Ground
15,6
Pins
II
9-174
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13077
Advanced PAL/NTSC Encoder
The MC13077 is a high quality RGBIYUV to NTSC/PAL encoder with
Composite Video and S-Video outputs. The IC integrates the color
difference and luma matrix circuitry, chroma modulators, subcarrier
oscillator, and logic circuitry to encode component video into a composite
video signal compatible with the NTSC/PAL standards. The IC operates off a
standard +5.0 V supply and typically requires less than 75 mA, making it
useful in PC environments. The high degree of integration saves board
space and cost, as only passive external components are required for
operation. The IC is manufactured using Motorola's MOSAIOM process and
is available in a 20 pin DIP or SOIC package.
ADVANCED
PAUNTSC ENCODER
SEMICONDUCTOR
TECHNICAL DATA
• Single 5.0 V Supply
•J!II!IIIIIIIIIf
~~ ~ ~
• Composite Output
• S-Video Outputs
P SUFFUC
UUPLASTIC PACKAGE
• PAUNTSC Switchable
CASE 738
• PAL Squarewave Output
• PAL Sequence Resettable
DWSUFFIX
PLASTIC PACKAGE
CASE 7510
(S0-20L)
• Internal/External Burst Flag
• Digitally Determined Modulator Axes
• Subcarrier Reference Drive Selectable
~
20
ORDERING INFORMATION
Device
MC13077DW
MC13077P
Vcc
4xfsc Xtall
4. fso Input
Simplified Block Diagram
Operating
Temperature Range
TA =0° to +70°C
Package
S0-20L
Plastic DIP
II
Gnd
r----~-----------------~----,
I
I
4. fsc
Divide by Four
3.581
I
B
Oscillator
Ring Counter
4.43
I
Latch
I
I
I
1.1 k
MOTOROLA ANALOG IC DEVICE DATA
9-175
MC13077
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
6.0
V
'c
Supply Voltage
Storage Temperature
Tstg
-65 to +150
Operating Junction Temperature
TJ
+150
'c
Operating Ambient Temperature
TA
Oto+70
°c
RECOMMENDED OPERATING CONDITIONS
Characteristic
Supply Voltage
Min
Typ
Max
Unit
4.5
5.0
5.5
Vdc
Sync Input Threshold Equivalent (See Figure 2)
Pulse Width
-
1.4
4.5-5.5
-
Vdc
R, G, B Input (Amplitude for 100% Saturated Video)
-
0.7
-
Vpp
R-V Input Amplitude at"Pin 16 (for 100% Saturated Video)
B-V Input Amplitude at Pin 15 (for 100% Saturated Video)
V Input Amplitude (without sync) at Pins 12, 13, 14 (for 100% Saturated Video)
V Input Amplitude (with sync) at Delay Line
-
490
350
700
1.0
-
mVpp
External 4x Subcarrier Input to Pin 8 (If crystal is not used)
-
External Subcarrier Input to Pin 9
Lock Range (with 4x Subcarrier Crystal specified) at Subcarrier Frequency
-
!IS
-
Vpp
300
-
mVpp
-
0.10to 3.0
±400
Vpp
Hz
2.5
-
-
4.0
1.1
0.4
-
Pin
Min
Typ
Max
Unit
1
55
70
85
mA
250
350
25
mVpp
mV
-
!!s
125
215
170
300
7.0
5.0 to 5.3
5.4 to 5.6
9
10
135
225
180
145
235
190
Degrees
-
-
25
65
mV
240
281
7.0
320
-
10
Burst Flag Input Threshold (Pin 18)
NTSC/PAL Select (Pin 19)
PAL Switching Amplitude: High
Low
NTSC Select Threshold
Vdc
Vdc
-
ELECTRICAL CHARACTERISTICS (TA =25°C, VCC =5.0 Vdc, test circuit of Figure 1.)
II
Characteristic
Supply Current (150 Q Load on Output Pins)
Color Burst Amplitude
Line-to-Line Burst Amplitude Deviation
Start after leading edge of Sync: NTSC (3.579 MHz)
PAL (4.43 MHz)
Duration: NTSC (3.579 MHz)
PAL (4.43 MHz)
PAL Burst Phase: Line n
Line n+l
NTSC Burst Phase
Subcarrier Leakage in Black
White (100% white)
Composite Video Output (100% saturated output)
Sync Amplitude
Line-to-Line Sync Amplitude Deviation (PAL)
Luminance Amplitude Error
Line-to-Line Luminance Amplitude Deviation (PAL)
Chrominance Amplitude Error
Line-to-Line Chroma Amplitude Deviation (PAL)
Chrominance Phase Error
Line-to-Line Chrominance Phase Error (PAL)
Black Level (RGB at Black during Blanking Intervals)
Sync Tip Clamp Level above Ground
9-176
2&4
(@75Q
load)
2&4
(@75Q
load)
2
(@75Q
load)
-
120
Cycles
<14
-
-
10
mVpp
mV
%
mVpp
%
mVpp
Degrees
<5.0
500
200
-
mV
-
3.0
-
-
10
280
MOTO.ROLA ANALOGIG DEVICE DATA
MC13077
ELECTRICAL CHARACTERISTICS (continued) (TA =25°C, VCC =5.0 Vdc)
Characteristic
Luma S-Video Output
Sync Amplitude
Line-ta-Line Sync Amplitude Deviation (PAL)
Luminance Amplitude Error
Line-ta-Line Luminance Amplitude Deviation (PAL)
Black Level
Sync Tip Clamp Level above Ground
Chroma S-Video Output
Chrominance Amplitude Error
Line-ta-Line Chrominance Amplitude Deviation (PAL)
Chrominance Phase Error
Black Level
Pin
3
(@750
load)
Min
Typ
Max
Unit
240
281
7.0
320
mVpp
mV
%
mVpp
mV
-
120
4
(@750
load)
-
-
-
10
3.0
500
200
280
-
10
<14
-
-
10
500
-
%
mVpp
Degrees
mV
Figure 1. Test Circuit
r----~~~-------------,-------------------,
I
Divide by Four
Ring Counter
Divide by512
3.58/4.43
Latch
I
I
I
I
I
I
I
II
MOTOROLA ANALOG IC DEVICE DATA
MC13077
PIN DESCRIPTIONS
Pin
Internal Equivalent
Schematic
Symbol
Description
Expected Waveforms
1
VCC
Supply Voltage
+ 5.0 Vdc ±1 0%
2
Comp
Video
Composite Video output. The external
75 0 series resistor determines the
impedance of the output. The output will
drive a 75 0 load through a 75 0 coax.
1.0 Vpp (75% Color Saturation),
1.23 Vpp (100% Color Saturation) at
the 75 0 load.
Luminance S-Video output. The external
75 0 series resistor determines the
impedance of the output. The output will
drive a 75 0 load through a 75 0 coax.
1.0 Vpp with sync (100% output) at the
750 load.
Chrominance S-Video output. The
external 75 0 series resistor determines
the impedance of the output. The output
will drive a 75 0 load through a 75 0
coax.
885 mVpp (100% output) when at the
75 0 load.
Luminance Output Clamp storage
capacitor. A 0.01 I1F capacitor should be
connected from this pin to ground.
3.4 Vdc.
Luminance input from the delay line. The
delayed Luma from Pin lOis applied at
this pin.
500 mVpp of Composite Luma when
100% saturated RGB inputs are applied.
CompOSite Sync input. Negative going
sync should be applied at this pin. The
input has a threshold of 1.4 V.
The peak vo~age may not exceed VCC.
Minimum voltage should not be less than
o V. See Figure 2 for input requirements.
Four times Subcarrier Frequency Crystal
Oscillator pin. This pin provides for the
connection of the oscillator resonant
element. Pin may also be driven directly
with a 4x subcarrier signal. <
300 to 600 mVpp 4x subcarrier input if
the pin is being externally driven.
Approximately 40 mVpp, if a crystal is
being used.
75
3
J
Zo=750
of
750
Luma
S-Video
Zo=750
1-
750
750
4
Chroma
S-Video
Luma
Clamp
6
Vln
I>
11~
1-::-
I~
Zo=750
750
750f
5
11~
1-::-
I
11~
1-::-
K
+
~
I
1
II
-
-::-
1.4V +
I
7
Sync Ini
Sync Sep
1(:'"
110 k
I
II
8
<4xfsc Xtal
14xfsc In
~
i~;~
1
::r:
1400
1
+
-=-Vref
~
2.Ok
9
3.58/
4.43 MHz
InlPLLOff
I
fP>
I
9-178
_
External Subcarrier Input. This pin
0.10 to 3.0 Vpp (AC coupled) of
provides an input to a Phase Detector and subcarrier to phase-lock 4x oscillator or
PLL and allows phase-lock of the 4x
grounded to disable the PLL.
oscillator to an external subcarrier
reference. To disable the PLL, this pin
should be grounded. 400 Hz of pull-in and
lock-in range is possible with a crystal.
MOTOROLA ANALOG IC DEVICE DATA
MC13077
PIN DESCRIPTIONS (continued)
Pin
10
Internal Equivalent
Schematic
Symbol
YOut
I
Description
10k
~
I
I
+
Expected Waveforms
Luminance Delay Line Drive Output. A
delay should be inserted between this
pin and Pin 6 to match the delay incurred
by the Chroma.
1.0 Vpp with sync
(100% saturated Color Bar output).
lAV
11
Gnd
Ground
Ground
12
Redl n
Red Video input.
0.7 Vpp AC coupled (100% Color Bars).
I
1
~
I
~
20k
Yv
I
ref
13
Greenln
See Pin 12
Green Video input.
0.7 Vpp AC coupled (100% Color Bars).
14
Blueln
See Pin 12
Blue Video input.
0.7 Vpp AC coupled (100% Color Bars).
15
B-Y
Clamp
B-Y Clamp storage capacitor. A 0.01 ILF
capacitor should be connected from this
pin to ground, unless the pin is used as
an input.
If not used as an input the pin is clamped
during sync to 2.4 Vdc. Can be used as a
B-Y input (AC coupled, 350 mVpp, 100%
color saturation). Burst Flag, if disabled
at Pin 18, must be inserted here with the
following signal levels; -170 mV (NTSC),
-121 mV (PAL).
16
R-Y
Clamp
R-Y Clamp storage capacitor. A 0.01 ILF
capacitor should be connected from this
pin to ground, unless the pin is used as
an input.
If not used as an input the pin is clamped
during sync to 2.4 Vdc. Can be used as a
R-Y input (AC coupled, 490 mVpp, 100%
color saturation). Burst Flag, if disabled
at Pin 18, must be inserted here with the
following signal level; +121 mV for PAL.
17
Chroma
Out
Chroma Bandpass Drive Output.
2.8 Vpp (100% Color Bars)
18
Burst Flag
OuVForce
Burst Flag
Burst Flag Output Disable and Force pin.
If left unconnected, internally generated
color burst will appear at Pins 2 and 4.
Burst Flag will appear at this pin (18). If
grounded, the Burst Flag will be
disabled. If externally driven from
another source of burst flag, the internal
flags will be overriden.
1.8 Vpp burst flag pulses if unconnected.
PAUNTSC system switch. If grounded,
the MC13077 will encode NTSC, and if
left open, PAL.
In PAL mode, a PAL squarewave
appears at this pin, the phase of which
can be reset by momentarily forcing the
pin to ground during the high state of
the squarewave.
Chroma Bandpass input. Output from
chroma bandpass filter should be
applied at this pin.
1.4 Vpp (100% Color Bars) with
bandpass filter and 1.0 kQ matching
resistors.
K
K
K
J
Iinternal
Burst
Flag
I
I
19
PAL
Squarewave
OuVForce
NTSC
20
Chroma
In
+
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MOTOROLA ANALOG IC DEVICE DATA
9-179
MC13077
FUNCTIONAL DESCRIPTION
Composite Sync Input
Other than the component video inputs to be encoded,
only Composite Sync is required for encoding the
components into a composite signal compatible with either
the NTSC or PAL standard. The Composite Sync input is
used internally for determining which standard to encode to,
for driving the black level clamps, and to set the timing of the
composite sync in the outputs.
The Composite Sync/Sync Separator input was designed
to accept AC or DC coupled inputs making it possible to drive
the sync input from a variety of sources. An interesting note is
that composite video can also be used for sync input. The
threshold of the sync input is 1.4 Vdc. Figure 2 shows the
requirements for sync input.
Figure 2. Sync Input Amplltude Requirements
The clamp capaCitors at Pins 5,15 and 16 are used to store
the reference voltage during the line period.
RGB Inputs
To encode RGB, the component video inputs (Pins 12,13,
14) are applied to the Luma (Y) and color difference (R-Y,
B-Y) matrix. The color difference signals are then
conditioned by Sallen-key low pass filters (f-3dB = 4.0 MHz).
The inputs are designed so that 700 mVpp RGB provides
100% color saturation.
The first color difference component (R-Y) is created by
matrixing the RGB components with the following weights:
R-Y=0.70R-0.59G-0.11B
B-Y = 0.89B - 0.59G - 0.30R
-r------ Vee
Baseline Voltage
i
LV___ :'""
Sync Tip VOlta91
-......- - - - - - Gnd
Figure 3. TTL Sync Input Circuit
1
5.1 k
0.111
71
nLSynC_~f---C1
240
1
1
Luma and Color Difference Clamps
Clamping for the MC13077 occurs once every horizontal
line during sync. The absence of color creates a color
difference component voltage of zero, this null is used to
generate a reference voltage for black in the video outputs.
9-180
(2)
These two components then receive burst flag before being
modulated by the color subcarrier to create composite
chroma.
The luma is also the result of a weighted matrixing of the
RGB components. The components and corresponding
weights are:
Y = 0.30R + 0.59G + 0.11B
Both serrated and block vertical sync can be used for
NTSC applications. PAL applications require a serrated
vertical sync. The serrations at the horizontal rate trigger the
PAL flip-flop to generate the swinging burst.
Even though the sync input of the MC13077 is well suited
for TTL interface, some functions of the IC are susceptible to
the high energy present in such signals and may be
disturbed. This disturbance may take the form of a noise
spike in the video outputs and/or a disturbance of the 4x
oscillator resulting in an incorrect encoding of the chroma
information. Therefore, it is recommended that if TTL or other
fast-edged inputs are going to be used for the sync input,
then either the amplitude and/or the edge speed of the sync
input pulse should be reduced. 300 mVpp of sync without a
reduction of edge speed has to be shown to produce
disturbance free operation. Also, a sync input of 4.0 Vpp and
edge rates of 225 ns have been shown to produce similar
results. Figure 3 shows a recommended coupling circuit for
TTL type composite sync.
(1)
The second color difference Signal (B-Y) is created in a
similar fashion by the equation:
(3)
Composite sync is then added to the result of Equation 3 to
create composite luma.
The luma information thus created must be eventually
recombined with the chroma information. However, since the
chroma information created by Equations 1 and 2 is filtered
internally before being modulated then bandlimited
externally, the resultant encoded chroma experiences a
group delay that is the sum of the delay imposed by the
internal and external filtering. So, the composite luma is
output at Pin 10 so that an external delay can be inserted in
the path to match the delay incurred by the composite
chroma. The delayed composite luma is then input back into
the MC13077 at Pin 6.
Color Difference Inputs
If the MC13077 is intended to encode color difference
signals (YUV or Y, R-Y, B-Y), it becomes necessary to
bypass the color difference and luma matrix circuitry. This
can be accomplished by inputing directly to the color
modulators the color difference signals. 491 mVpp and
349 mVpp should be input to the R-Y and B-Y Clamp pins
(Pin 16 and Pin 15) respectively, to achieve 100% color
saturation in the composite video output. The luma
information can be input in two ways. The luma can be input
directly into the RGB inputs (700 mVpp without sync), or
through the delay line (1.0 Vpp with sync, sync tip-to-peak
white) in which case the RGB inputs should be cap-coupled
to ground. In either case, composite sync still needs to be
input to the MC13077 at Pin 7 (see Figures 11, 12 and 13).
If the R-Y and B-Y inputs also have burst flag, it can also
be input along with the color difference signals at these pins.
Of course, now since the color difference modulator
pre-filtering is circumvented, the delay for the luma
information should be matched only to the delay of the
bandpass filter.
MOTOROLA ANALOG IC DEVICE DATA
MC13077
Figure 4. Versatility of the 4x fsc Oscillator
4x fse
~~tal
-=8
5-25 pF
MCI3017
Oscillator Free
Run wtth Crystal
4x fse Drive
220
(150 mV to 3.0 Vpp) -----11--'\/\/'v-_--18
1000 pF
MC13017
9
Direct Drive of
Oscillator with
4x fse Source
4xfse
Crystal
..L
A~I
8
5-25 pF 1000 pF
fse
.)
9
Subcarrier Reference
Input (Pull-in Range
of~±400 Hz)
MCI3077
Oscillator Phase Lock
with Crystal to
Subcarrier Reference
4X Subcarrier Oscillator
To encode the color difference components. an accurate
and reliable subcarrier source is required. The MC13077 has
an on-chip single pin oscillator that will free-run with a 4x fsc
crystal. phase-lock to an external subcarrier reference with a
4x fsc crystal or resonator. or be driven externally from a 4x fsc
source. If the 4x fsc oscillator is going to be free run. the
subcarrier input (Pin 9) should be grounded. If the 4x fsc
oscillator is going to be phase-locked to an external
subcarrier source. the external reference should be
capacitor-coupled to Pin 9. If the 4x fsc oscillator is going to
be driven externally. Pin 8 should be driven from a network
that increases the impedance of the source at frequencies
capable of producing off-frequency oscillations. The 4x fsc
subcarrier source. thus being defined. makes it possible to
produce accurate quadrature subcarriers for the modulators.
The 4x source is internally divided by a ring counter to
produce the quadrature subcarrier signals. These signals in
turn are provided to the color difference rnodulators to
produce the modulated chrorna. The oscillator was designed
so that if a crystal is chosen as the resonant element of the 4x
oscillator. the crystal specifications would be common.
Crystal specifications for an adequate crystal are shown in 1
Table 1. Crystal Specifications
Frequency: 14.31818 MHz (NTSC)
17.734475 MHz (PAL)
Mode: Fundamental
Frequency Tolerance (@25'C). 40 ppm
Frequency Tolerance df/dfo (0' - 70'C). 40 ppm
Load Capacitance: 20pF
ESR:
son
Cl(lntemal Series Capacitance). 15 mpF
This crystal is a common variety and is specnied as a parallel resonant.
Burst Flag Decoding
In order to encode to either NTSC or PAL compatibility. the
MC13077 must first determine which is the intended
standard. The MC13077 accomplishes this with an internal
decode using the sync input and the output of the divide by 4
ring counter. Internally. the Sync separator circuitry provides
an output that is sampled by the subcarrier signal from the
MOTOROLA ANALOG IC DEVICE DATA
MCI3017
Oscillator Phase Lock
with Resonator to
Subearrier Reference
ring counter. The result is an internal sync representative of
externally input sync but synchronized to the internal
subcarrier signal. This signal provides a reset for an internal
9-bit counter that provides divisions of the subcarrier signal
frorn the ring counter at powers of 2 (I.e. 21. 22. 23 ....2 9 =
512). The eighth bit of the counter gives the output. fsc + 256.
The decision to provide burst gate timing for PAL or NTSC is
based upon the state of this output after one period of the
horizontal sync. Figure 5 shows the relationship between the
clock and the eighth bit of the counter.
Triggering of the burst PAL flip-flop due to equalizing
pulses is also inhibited by the decode circuitry. This is done
by counting out beyond a half line interval before generating
burst flag.
If the MC13077 is encoding 525/60 component video to
NTSC and the MC13077 is generating the burst flag. the start
of burst will occur 18 counts after the leading edge of sync
has been sampled. and will continue until nine cycles of burst
have occurred. Since the reset pulse of the 9-bit counter has
a resolution of 1.0/fsc • this implies that the start of burst will
occur 5.17 ± 0.1397 I1s after the leading edge of sync and
also that the start (and end) of burst may differ by as much as
279.4 ns from line-to-line. If the MC13077 is encoding
625/50 to PAL. the subcarrier frequency will be
4.43361875 MHz and that irnplies a resolution of 225.5 ns
for the burst position. For PAL encoding. 24 counts of the
subcarrier are necessary before burst is initiated. So ten
cycles of subcarrier will occur 5.53 ± 0.1128 I1s after the
leading edge of sync. After the timing of the burst gate is
selected. the burst gate envelope is added to the color
difference components.
Another alternative to the internal deterrnination of burst
flag is the external input of burst flag. This allows the user to
externally define the exact timing and duration of color burst.
If external burst flag is available. it can be inserted at Pin 18.
The threshold level is nominally VCC/2 and the input should
not exceed VCC. Burst will begin when the leading edge of
the burst flag input exceeds VCC/2 and will stop when it falls
below VCC/2. If it is desired to disable the burst flag. Pin 18
can be pulled low. It is also possible to insert burst flag with
the R-V and B-V components. This is done at the clamp pins
with the respective color difference inputs with the internal
burst flag generation disabled (Pin 18 grounded).
9-181
II
•
MC13077
Figure 5. Relationship Showing the Counts of a 3.58 MHz Clock
versus a 4.43 MHz Clock at the End of a Horizontal Period
fsc - - - - -
rr t
L---------~t----~r)~r--------~r----I
256
NTSC: (3.58 MHz) (63.56 J.ls) = 227.5 counts
512
PAL: (4.43 MHz) (64 J.ls) = 283.75 counts
Chroma Band Limiting and Luma Delay
Once the color difference and burst flag envelopes have
been modulated, the two components are internally summed
and applied to an output buffer that will drive the external
bandpass circuitry before entering the chip again at Pin 20.
The sum of the color difference modulators produces 'an
output that is high in harmonic content. For this reason, and
to reduce the possibility of cross color, a chroma bandpass
transformer is used to band-limit the chroma. Suggested
bandpass filters and specifications for NTSC and PAL are
shown in Figure 7a and 7b. For each of these filters,
approximately 300 ns of group delay is experienced by the
filtered chroma. There is also an internal delay on the order of
100 ns due to internal filtering that must be considered. Thus
a 400 ns luma delay line is used to equalize the timing of the
luma and the chroma. Suitable 400 ns delay lines are the
TaKa H321 LNP-1436PBAB and the TOK
OL1224010-1533. The delay of the luma channel is inserted
between Pins 10 and 6. Pin lOis the buffered output of the
luma from the RGB matrix. This output is capable of driving
the external passive delay line with no external gain or
buffering required.
Figure 7a. Group Delay and Magnitude
Response of the TOKO Bandpass Filter
Intended for NTSC Applications
o
II
liLA-IN
Attenuatioiyf'
Figure 7b. Group Delay and Magnitude
Response of the TOKO Bandpass Filter
Intended for PAL Applications
~ 10
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Q 20 II NTSC Bandpass Filter
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FREQUENCY (MHz)
9-182
Attenuation (dB)
20
10k
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I I I I I I
3.0
4.0
5.0
6.0
7.0
8.0
I
0.2
r
9.0
FREQUENCY (MHz)
Characteristics of TOKO Bandpass Filter
(H286BAIS - 6276DAD)
Frequency (MHz)
1 3
I
I
5
I
PAL Bandpass FiRer
~!'.lII
~
60
VI 1.,.......11 I
YI I I I N I
Characteristics of TOKO Bandpass Filter
(H286BAIS - 4963DAD)
Group Delay (J.lS)
Frequency (MHz)
Attenuation (dB)
Group Delay (J.ls)
2.0
. 8.0 (min)
0.12
2.50
10 (min)
0.075
2.8
3.0±3.0
0.25
3.73
3.0±3.0
0.24
3.58
Ins. Loss 3.5 (max)
0.290 ± 0.030
4.43
Ins Loss 2.0 (max)
0.295 ± 0.035
4.3
3.0±3.0
0.24
5.13
3.0±3.0
0.24
6.2
15 (min)
0.05
6.50
12 (min)
0.05
MOTOROLA ANALOG IC DEVICE DATA
MC13077
Chroma Encoding
Modulation of the color difference components is
performed by two double-balanced mixers that are driven
from quadrature signals provided by an internal ring counter.
The quadrature signals are derived from a ring counter that is
driven by the 4x oscillator, and which makes highly accurate
quadrature angles possible.
If PAL encoding is selected, negative burst flag envelope
is provided to both B-V and R-V components equally, then
the R-V envelope phase is switched positive and negative
from line-lo-line to provide the PAL alternating burst phase
characteristic. An internal flip-flop that provides the internal
fH/2 switching is enabled by opening the connection at
Pin 19. If enabled, the pin will exhibit the internally generated
half line frequency squarewave. If it is desired to reverse the
sense of the PAL swinging burst, it can be done at this pin by
pulling Pin 19 low when the squarewave is high. The
component envelopes with the proper PAL burst phase are
then modulated to produce the composite chroma.
If the MC13077 is encoding to NTSC, only the B-V color
difference component is provided a negative burst flag. This
envelope when modulated results in the characteristic -180 0
phase difference between the color burst and the subcarrier
for the B-V component. Pin 19 should be grounded for NTSC
operation to disable the PAL flip-flop.
Video Outputs
After being filtered, the composite chroma is recombined
with the composite luma information for the Composite Video
output. The composite chroma and composite luma
components are also kept separate and buffered for the
chroma S-Video and luma S-Video outputs. The video
outputs are provided with low impedance emitter-follower
stages and, therefore, require an external 75 n impedance
determining series resistor (see Figure 7). The outputs are
designed to drive a 75 n load through the external 75 n
series resistor.
The Composite Video output will provide 1.23 Vpp of video
(sync tip-to-peak chroma) for 100% saturated video at the
75 n load. Luma S-Video will be 1.0 Vpp (sync tip-to-peak
white) at the 75 n load and the Chroma S-Video output will
provide 885 mVpp at the 75 n load.
Figure 7. Composite S-Luma and
S-Chroma Video Outputs
--;c-;;;l
I
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I
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___::.....JI
APPLICATIONS INFORMATION
Figures 8 through 13 are application examples showing
the versatility of the MC13077.
Figure 8. Standard Encoder Application with RGB Inputs and Phase-Locked Subcarrler
II
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3
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MOTOROLA ANALOG IC DEVICE DATA
9-183
MC13077
Flgur~ 9. Encoder with RGB Inputs and Unlocked Subcllrrler
.'
Uk
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Figure 10. Encoder with RGB Inputs and 4x Subcarrier Drive
~~ ~J;
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Figure 12. Encoder with Composite Luma and Color Difference Inputs
Using Phase-Locked Subcarrier
II
R-Y, B-Y Source
Impedance
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MOTOROLA ANALOG IC DEVICE DATA
1.2 k CompoSite
Y-Input
!H85
MC13077
Figure 13. Encoder with Composite Luma and Color Difference Inputs
Using the Sync Separator and Having Phase-Locked Subcarrier
R-Y, B-Y Source
Impedance
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Recommended Vendors
Bandpass Filters
and Delay Lines
TOKO America Inc.
1250 Feehanville Drive
Mt. Prospect, IL 60056
Crystals
Fox Electronics
5570 Enterprise Pkwy
Ft. Myers, FL 33905
(813) 693-0099
(708) 297-0070
(708)699-7864 (fax)
Delay Lines
TDK Corp. of America
1600 Feehanville Drive
Mt. Prospect, IL 60056
Standard Crystal Corporation
9940 E. Baldwin Place
EI Monte, CA 91731
(818) 443-2121
(708) 803-6100
9-186
MOTOROLA ANALOG ICDEVICE DATA
®
MOTOROLA
MC13081X
Advance Information
MULTIMODE COLOR
MONITOR PROCESSOR
Multimode Color Monitor
Horizontal, Vertical, and Video
Combination Processor
SEMICONDUCTOR
TECHNICAL DATA
The MC13081X includes all the signal processing functions for a scan
frequency agile and multiple sync system analog RGB monitor and includes
the following functions:
• Automatic Horizontal Frequency Tracking of All Commonly Used
Personal Computers, Continuously Adaptable from 30 kHz to 64 kHz
• Sync-on-Green Detection
• Vertical Timebase Operates from 45 to 100 Hz
• Vertical and Horizontal Sync Polarity Detection with Outputs for
Mode Switching
BSUFFIX
PLASTIC SDIP PACKAGE
CASE 859
• Video Pre-Amplifiers Typical Rise/Fall Time of 5.0 ns at 3.0 Vpp Output
Voltage Swing
• Overall Contrast Control and Independent RGB Gain Controls
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC13081XB
TA = 0° to +70°C
Plastic SDIP
II
PIN CONNECTIONS
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MOTOROLA ANALOG IC DEVICE DATA
9-187
MC13081X
Figure 1. Block Diagram
m
TTL
V-Sync H-8ync CVS
r--I
I
Vert Integrator Cap
3
!
10
AFC
11
I
12
Hon Freq Control
Timebase VCC
+5.0 V Output
Timebase Gnd
FHA Switch
FHA Threshold
FHBSwitch
FHB Threshold
Channelt Video In
Channel 3 Video In
Contrast
Brightness
r
Vertical
Oscillator
J
5 Count Latch
l~Kn
Vertical Ramp
Generator
1
I
!
25
!
27
I
I
I
18
!I
19
I
!
Vcci
64H
Xl
Up
Digital Honzontal
Loci< Control
~
64 Divider and
Clamp Pulse Decoder
~
~
I
Ramp 2
'I
64xOsciliator
-----;:= ~
I
5 V Regulator
1
f
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J
1
SDG Detector
II
143
I
H-Dnve
Timebase Gnd
I
141
X-Ray
X-Ray Shutdown
I
!
44
Channell
H-Drive Width Adjust
1 40 Collector Out
!
139
EmlnerOut
1 20
!
Channel 2
~ Channel3
v>
!
PD2F
142
138
1
H-Ryback
I
I
1
~
Brlghtnass and
Contrast Procassor
145
129 VideoVCC
V
c
'I
~
/>
~
~
Clamp
Pulse Position
!
I
I
'--
146
¥ -t
Generator
Hori Position Adjust
!
Honzontal
Dnver
1"-
~
155
Ramp 1
l/BUne
Shift
Blanking
!
Phase
Detector
1=
II
cl.-)
23
I
I
I
I
1
;r-~
I
riB_ _ _ .,
I
Phase Detector
Down
I
151
h
Vert
Ramp
V-sync
I
I
I
gJ
I
14 I
Vert
Size
2.!.._ 52
rJ.-
Blanking
l
I
I
Channel 2 Video In
H
!
56 I
9
~--
Vert
Vase Vert Hold Ramp Gap
2_ _ _
147
H-Sync
!
I
I
I
I
.i. __
1 Sync Source Decoder
1 and Polanty Control
I
I
I
I
I
I
I
I
I
PD1F
'--r-
V-Sync H-8ync
Polar Det Polar Det
54
137
Clamp
Subcontrast
Collector Out
I
134
133
124
I
!
32
EmlnerOut
Clamp
Subcontrast
Collector Out
I
I~ Emitter Out
lao Clamp
!
26
Subcontrast
I
~-----------------------o--------_J
28
Video Gnd
This device contains 1074 active transistors.
9-188
MOTOROLA ANALOG IC DEVICE DATA
MC13081X
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Pin
Value
Power Supply Voltage
Video Section VCCI
Timebase Section VCC2
29
56
-0.5,+10
-0.5, +10
19,18,46,
14,16
OtoVCC
Vdc
Vdc
Unit
Vdc
Brightness, Contrast, Horizontal Flyback
Input, Frequency Switch when Off
41
-{).5, +0.9
20,24,26
Oto+2.0
Vdc
44,55
o to +5.0
Vdc
43,4,5,6,
32,37,40
-0.5 to
VCC+0.5
Vdc
X-Ray Shutdown
Subcontrast RGB Controls
Horizontal Drive Width, Horizontal Position
Voltage on Horizontal Drive when Off, Vertical
TTL Sync Input, Horizontal TTL Sync Input,
Composite Video Sync Input, Video Ampl~ier
Output Collectors
Current into Horizontal Drive when On
43
100
rnA
14,16
30
rnA
Video Amplifier Inputs
23,25,27
-0.5, + 5.0
Vdc
Video Amplifier Output Current (Total for the
Three Channels)
40,39,37,
34,32,31
120
rnA
Storage Temperature
-
-65 to +150
°c
Junction Temperature
-
+150
°e
Current into Frequency Switch when On
NOTE:
ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Pin
Min
Typ
Max
Power Supply Voltage
Video Section VCCI
Tlmebase Section VCC2
29
56
7.6
7.6
8.0
8.0
8.4
8.4
Power Supply Voltage Difference, VCC2 - VCCI
-
-0.3
0
0.8
Internal 5.0 V Regulator Output Current
9
-20
-
0
mA
Contrast Control
18
0
-
5.0
Vdc
Vdc
Characteristic
Unit
Vdc
Vdc
19
0
-
5.0
20,24,26
0
2.0
Vdc
Horizontal Drive Width Adjust
44
0
-
5.0
Vdc
Horizontal Position Adjust
55
1.0
-
4.0
Vdc
Horizontal Flyback Signal Amplitude
46
0.7
5.0
8.0
V'
Vdc
Brightness Control
Subcontrast Control
Horizontal Flyback Signal DC Input Voltage Level
46
-0.2
0
-
Voltage on Horizontal Drive Collector when "Off'
43
0
Vce
V
Current into Horizontal Drive Collector when "On"
43
0
-
40
rnA
Voltage on Horizontal Drive Emitter W.R.T. Circuit Ground
42
-0.3
0
2.0
Vdc
Blanking Input Signal Amplitude
47
1.5
-
4.0
V
Voltage on FH Switches when "Off'
14,16
0
-
8.0
Vdc
Current into each FH Switch when "On"
14,16
0
-
20
rnA
41
0
-
0.7
Vdc
Composite Video Sync Input
6
1.0
-
2.0
Vpp
Vertical Sync Frequency
-
45
-
100
Hz
Horizontal Sync Frequency
-
30
-
64
kHz
Vertical Sync Pulse Width
-
-
70
-
~
Horizontal Sync Pulse Width
-
-
1.0
-
~
X-Ray Shutdown
MOTOROLA ANALOG IC DEVICE DATA
9-189
II
MC13081X
RECOMMENDED OPERATING CONDITIONS (continued)
Pin
Min
Typ
Max
Unit
Video Signal AmplHude (with 75 n Termination)
23,25,27
0.5
0.7
1.2
Vpp
Voltage on Video Amplifier Collector
32,37,40
4.5
-
VCC
Vdc
Current Through Video Collector-Emitter
40,39,37
34,32,31
0
-
40
mA
Vertical Hold Set Resistance, R9 + VR2 (Figure 2)
2
-
10
-
kn
Vertical Size Set Resistance, R10 + VR3 (Figure 2)
52
-
220
-
kn
Vertical Linearity Set Resistance, R12 + VR4 (Figure 2)
51
-
1000
-
kn
Operating Ambient Temperature
-
0
25
70
°C
Characteristic
15,17
See Application Section 5
-
Vertical TTL Sync Input
4
TTL Voltage Level
Vdc
Horizontal TTL Sync Input
5
TTL Voltage Level
Vdc
FH Switches Set Resistance
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 8.0 Vdc)
Characteristic
Condition
POWER SUPPLIES
Supply Current
Total Consumption
5.0 V Regulator
Output Voltage
Une Regulation
Load Regulation
Temperature Coefficient
Thermal Resistance, Junction-to-Ambient
-
29,56
70
85
110
mA
4.75
5.25
-
5.0
25
100
-(l.3
-
Vdc
mV
mV
mV/oC
59
-
°CIW
9
Load Current (lB) = 0 mA
7.6 V < VCC < 8.4 V, IB = 0 mA
-10 mA< IB 500 ms
-
30
-
64
kHz
Current Flowing Out of Pin 12
12
115
122
129
HzlliA
Pin 11 is Opened
-
-
300
-
ppm/DC
-
15,17
11212
5.0
-
Tlme<5.0ms
0
-
200
itA
V
mV
-
-
200
mVdc
-
1=10mA
14,16
±5.0
MOTOROLA ANAL9G IC DEVICE DATA
MC13081X
ELECTRICAL CHARACTERISTICS (continued) (TA = 25°C, VCC = 8.0 Vdc)
Characteristic
Condition
HORIZONTAL DRIVE
o < V55 < 5.0 V,
FH=30k-56kHz
See Application Section 7
55
FH = 35 kHz, 0 < V44 < 5.0 V
44
Horizontal Position Adjust
Range
Input Impedance
Horizontal Drive Width Adjust
Range
Input Impedance
Horizontal Flyback
Threshold
Input Amplitude
Input Impedance
Horizontal Drive
Output Low
Output High
See Application Section 4
Input Signal Should Not Fall
Below-O.2V
-
10
31
-
%
kfl
2:1
-
1:2
-
30
-
%
kfl
-
0.7
0
-
8.0
-
10
-
V
V
kfl
0
46
43
Isink= 40 rnA
V43 = VCC
-
0.3
100
Vdc
IlA
250
-
ns
Time Delay from Flyback to Video Output
Blanking
See Application Section 7
-
-
Time Delay from Blanking to Video Output .
Blanking
See Application Section 7
-
-
400
-
ns
X-Ray Shutdown
Activate Voltage
See Application Section 11
41
0.4
0.58
0.7
Vdc
-
41
-
-2.3
-
mVloC
30 kHz < FH < 56 kHz
43
-
3.0
-
ns
-
48
45
-
100
Hz
FV= 50 Hz,
R12 + VR4 = 820 kfl
R10 + VR3 =120 kfl,
C6 = C7 = 1.0 IlF
48
-
3.0
1.9
3.4
2.0
0.45
-
1.0
Vpp
V
V
rnA
%
0.01
-
HZ/oC
Temperature Coefficient of X-Ray
Threshold Voltage
Horizontal Jitter
VERTICAL PROCESSING
Vertical Ramp Frequency
Vertical Ramp
Amplitude
Minimum Peak
Maximum Peak
Output Current
Non-Linearity
-
-
-
Vertical Ramp Free Running Temperature
Drift
FV=50Hz
48
-
Vertical Ramp Free Running Drift with VCC
FV=50Hz
48
-
0.5
-
HzIV
Vertical Ramp Discharge Rate (Retrace)
FV=50Hz
48
-
9.5
-
Vlms
Vertical Sync Detector Output/+VE Sync
53
-
0
-
Vdc
Vertical Sync Detector Output/-VE Sync
53
-
3.6
-
Vdc
-
22
-
kn
0
2.4
-
0.8
5.0
Vdc
Vdc
100
-
-
2.4
-
Vdc
Vertical Sync Input
Input Impedance
Input Level - Low
Input Level - High
-
4
VIDEO AMPLIFIERS
Input Impedance
Internal DC Bias Voltage
Output Signal Amplitude
Vo~ageGain
Contrast Control
Subcontrast Control
Brightness Control
MOTOROLA ANALOG IC DEVICE DATA
-
23,25,27
kfl
Yin = 0.7 Vpp, V18 = 5.0 V
V20 =V24 = V26=OV
39,34,31
-
3.6
5.1
-
Vpp
VN
V18 = 0 to 5.0 V;
V20, 24, 26 = 0 V
18
-
20
-
dB
V20, 24, 26 = 2.0 to 0 V;
V18=5.0V
20,24,26
1:2.5
-
-
-
V19 = 0 to 5.0 V; Measure
Pin 39, 34, 31 DC Level
19
-
±D.5
-
Vdc
9-191
MC13081X
ELECTRICAL CHARACTERISTICS (continued) (TA = 25'C, VCC = B.O Vdc)
Characteristic
Condition
VIDEO AMPLIFIERS
Emitter DC Level
Minimum Brightness
Nominal Brightness
Maximum Brightness
39,34,31
Crosstalk, Amplifier to Amplifier
Output Rise Time
Output Fall Time
Vdc
-
V19=OV
V19=2.5V
V19=5.0V
1.25
Frequency = 10 MHz
39,34,31
Yin = 0.7 Vpp; Vout = 3.0 Vpp
39,34,31
-
1.0
1.5
2.0
1.75
34
-
5.0
5.0
-
dB
ns
PIN FUNCTION DESCRIPTION
Vertical
Oscillator
Capacitor
2
This capacitor should be 100 nF film type to give good
temperature stability.
2.Sk
Vertical Hold
Control
--------R2
3
Vertical
Integrator
Capacitor
The potentiometer at Pin 2 adjusts the free running
frequency of the oscillator. It should normally be set
for about 55 Hz with no vertical signal input such that
it will lock to 60 Hz.
The capacitor on this pin integrates the sync pulses
with a long time constant. C3 is typically 0.01 jlF.
VCC
Swttching
Control
ISIO
II
4
Vertical TIL
Sync
To Logic
Sync
Input
5
Horizontal TIL
Sync
Composite or Horizontal TIL Sync input. The input
threshold voltage at this pin is 2.0 V.
2.DV
To Logic
Sync
Input
6
Vertical TIL Sync input. The input threshold voltage
at this pin is 2.0 V.
2.DV
Compos~e
5.0V
Video Input
Comp
InpLrt
>--l
} To Sync
Separator
This pin requires a coupling of min 100 nF. The
composite sync input should consist of -VE sync
signal only with amplitude> 500 mVpp.
The source impedance of the sync signal should be
<1.0 kO.
0.1
Sync information at Pin 5 will override this pin, but
signals at Pin 4 will not.
Minimum pulse width is 2.0 jls.
7,8
N/C
These two pins are internally connected to each other,
and nothing else.
MOTOROLA ANALOG IC DEVICE DATA
MC13081X
PIN FUNCTION DESCRIPTION (continued)
Pin
9
Name
Equivalent Internal Circuit
Description
5.0V
Regulator
Output
5.0 V (±5%) regulator. Minimum 10 IlF capacitor is
required for noise filtering and compensation. Up to
20 mA can be supplied to external circuitry. It can
source but not sink current. Output impedance Is
=10Q.
5.0 V+-~-<>-+--f<'
This 5.0 V regulator is recommended for use as a
reference only.
10
Phase
Detector 1
Filter
External components at this pin will determine the
PLL gain and phase characteristics. The capacitors
should be non-polarized.
The voltage at this pin nominally ranges from 1.5 V to
5.0 V with corresponding horizontal frequency from
25 kHz to 68 kHz.
11
Automatic
Frequency
Control
1,...--f-<>--+--'VIf'v- vee
RllA
Pin 11 is a buffered equivalent of Pin 10, and ranges
from a minimum of 1.5 V at horizontal high frequency
to near 5.0 V at low frequency. Pin 11 can sink a
maximum of 1.0 mA, but cannot source current.
R11B
12
Horizontal
Frequency
Range
The current out of Pin 12 determines the horizontal
frequency by a current transfer constant of
= 122 HZ/ItA.
Rlle
Pin 12 is intemally maintained at 5.0 V.
13
14,16
Timebase
Ground
Ground for the timebase section. Connect to a clean,
low impedance ground.
FH SwHch A, B
Pin 14 (Switch A), and Pin 16 (Switch B) are open
collector NPN switches to ground. Each switch is
"on" when the horizontal frequency is higher than the
set points set by resistors at Pins 15 and 17,
respectively.
Maximum voltage is 8.0 V, and maximum sink
current is 20 mAo
15, 17
FH Switch A, B
Threshold
Setting
Pin 15 and Pin 17 are current mirror at 1/2 of Pin 12
current. External resistors at these pins set the
horizontal frequency at which Pins 14 and 16 will
switch, respectively. The threshold voltage is 5.0 V.
To Output
Switches
R15
(R17)
18
Contrast
Control
19
Brightness
Control
The input control range is from 0 to 5.0 V. An increase
of voltage increases contrast.
Rle ~_-'<>+_-{
(R19)
MOTOROLA ANALOG IC DEVICE DATA
The input control range is from 0 to 5.0 V. An increase
of voltage increases brightness.
9-193
II
MC13081X,
PIN FUNCTION DESCRIPTION (continued)
20
24
26
Vee
Subcontrast
Control
Channell
Channel 2
Channel 3
Subcontrast controls the gain of each video channel.
o V for maximum gain, and 2.0 V for minimum gain.
N/C
These two pins are internally connected to each other,
and nothing else.
23
25
27
Video Inputs
Channell
Channel 2
Channel 3
The input coupling capacitor is used for input clamp
storage. The maximum source impedance is 100 n.
Polarity of the input video signal is positive. Amplitude
should be nominally 0.7 Vpp.
28
Video Ground
Ground for the video section (video amplifiers,
contrast and brightness controls, subcontrast, and
video reference voltage).
21,22
Noise from the timebase section, and other digital
should not be allowed to produce ground
bounce at this pin.
circu~s,
II
29
Video VCCI
38
33
30
Video Clamp
Channell
Channel 2'
Channel 3
39
34
31
Video Emitter
Output
Channell
Channel 2
Channel 3
40
37
32
Video Collector
Output
Channell
Channel 2
Channel 3
35,36
9-194
N/C
Connected to a 8.0, V ±S%, dc supply. Decoupling is
required at this pin.
Clamp Pulse
I
L5V~J
VideoOut
Normally a 100 nF capacitor is connected to each of
these pins,
-
Vee
Pins 39, 34, and 31 are the emitter outputs of the
three video amplifier, and have an internal 33 n
resistor.
The emitter dc voltage is controlled by the brightness
control.
The curren! through each collector and emitter should
not exceed 40 rnA.
These two pins are internally connected to each other,
'and nothing else.
MOTOROLA ANALOG IC DEVICE DATA
MC13081X
PIN FUNCTION DESCRIPTION (continued)
Pin
41
Name
Equival nt Internal Circuit
X-Ray
Shu1down
Description
~rC'"
If the vottage at this pin is > 0.58 V, the horizontal driver
device (Pins 42 and 43) will be "on" until power is
removed, or the votlage on this pin is taken below 0.4 V.
47k
41
X-Ray
V
Shutdown
=
42
Horizontal
Drive Ground
I
I
I
vee
2.7k
This emitter pin must be connected externally to a low
impedance ground.
vee
43
I
Horizontal
Drive
I
I
I
Horizontal
Drive Width
s.ov
~.
45
Secondary
Phase
Detector Filter
I Detector
Phase
T
Horizontal
Flyback
Video Blanking
Input
I
Circuit
As the voltage of this pin is increased, the "on" time at
Pin 43 is decreased.
24k
22k
Ramp 2
13.5k
~250~
I
I
I
I
4250~A I
i
-
Horiz
ose
Typically a 10 to 100 nF decoupling capacitor is
connected to this pin.
I
I
I
-
47
+
II
45
-f4+>-I
I
I
Inpu1 impedance is ~ 30 kU.
=
=
#2
Maximum current through Pins 42 and 43 must be
less than 40 rnA.
Varying the votlage at this pin will change the
horizontal drive duty cycle.
+
s.ov
IC45
I
Signal
47
i
I
I
I
I
Pin 43 is an open collector pin and normally is pulled
up by a resistor to Vee.
To Horizontal
Deflection
=
vee
Sync
46
I
44
'r
R44
42
I
I
I
=
44
T
R43
1 43
To Phase
Detector #2
The flyback signal should be a +VE pulse of peak
voltage 8.0 V. The internal switching voltage is 0.7 V
and it controls the secondary PLL
Input impedance is ~ 10 kQ
0.7 V
I
I ~
I
2.0k
20k
....
The video blanking signal should be positive pulse in
the range of 1.5 to 4.0 V.
I
I
I =
MOTOROLA ANALOG IC DEVICE DATA
9-195
MC13081X
PIN FUNCTION DESCRIPTION (continued)
48
Vertical Ramp
Output
This ramp signal drives the external vertical output
devices.
To Vertical
H>-----+-l-<;-,~Deflection
Circuit
Voltage ramps from 2.0 V to less than 5.0 V,
depending on frequency and components at Pins 51
and 52.
Loading on this pin must tie > 30 kO to avoid
distorting or clipping the ramp.
49,50
51
NlC
These two pins are intemally connected to each other,
and nothing else.
Vertical Ramp
Capacitor
The slope of the output ramp is determined by the
components at Pins 51 and 52.
The resistor at Pin 52 sets the charging current of the
capacitor, and therfore the vertical height of the
picture.
200
52
The linearity of the ramp can be modified by external
feedback.
Vertical Size
Control
52
51
C51
53
Vertical Sync
Polarity
Detector
The output goes low when the vertical sync input
polarity is positive. It goes high when the vertical sync
input' polarity is negative.
54
Horizontal
Sync Polarity
Detector
The output goes low when the horizontal sync input
polarity is positive. It'goes high when the horizontal
sync input polarity is negative.
55
Horizontal
Position
Control
Varying the voltage at this pin will change the
horizontal position of the picture.
II
Input impedance is ~ 31 kO.
R55 ~-o--+JVV\r--+-l
56
9-196
Timebase
VCC2
Ramp 1
Connected to a 8.0 V, ±5%, dc supply. Decoupling is
required at this pin.
MOTOROLA ANALOG 10 DEVICE DATA
MC13081X
APPLICATION INFORMATION
The MC13081X is an integrated multisync color monitor
processor. It combines horizontal/vertical deflection processing
circuitry and video pre-amplifiers into a single device.
The overall timebase section consists of two parts:
horizontal and vertical. The horizontal timebase can be
operated from 30 kHz to 64 kHz, and can be driven from TTL
separate sync, composite sync, or a composite video signal.
There are two PLLs which ensure proper timing throughout
the whole system. The first PLL provides line locking of the
horizontal sync signal with the built-in oscillator, while the
second one maintains fixed timing with the horizontal flyback
signal such that a stable display can be achieved.
The vertical timebase section operates from 45 Hz to
100 Hz, and can receive various sync signals as the
horizontal one does. This section consists of an oscillator and
a ramp generator. Adjustments include linearity, ramp
amplitude, and minimum free running frequency in the
absence of sync signal.
The video section has three 70 MHz bandwidth
pre-amplifiers. The outputs of these amplifiers are
uncommitted collector/emitter facilitating cascode
configuration with subsequent stages. Controls include
brightness and contrast. In addition, the voltage gain of each
amplifier can be adjusted individually which provides
flexibility in adjusting color correctness. Blanking and
clamping signals are provided to the amplifiers internally from
the timebase section. Additionally, a blanking signal can also
be supplied externally.
Separate power supply and ground pins are provided to
the timebase and video section in order to minimize the cross
interference between these two sections.
Figure 2. Application Circuit
VR2
VR3
C6
Rl0
C7
m
§
C4
1
R9
C5
52
V-Sync>------<>-t
~~i~nc
H-Sync
Horizontal m Sync
Cl
R>----......-l
C2
Gi>----<>--+-l
81>--..._+--+C=:3'j
MC13081X
Rl
R2
R3
28
VideoGnd
Vd
11
12
AFC
!
i I
j
Horizontal Freq Control
~
N
l>
I I l J
~
24
26
19
6
S. VlSf S.O V,af
VR1I
R7
~4---~~~~+4~~~~
~y~
va:T:1' ~~~
I '~~"tr
C25
1
C26
-=-
R18
C19
Vd
1
1
C27
C281 c29
-=-
-=-
Vd
Rl-R3,R17
R4-R8
R7
R8
R9
Rl0
R12
R13
R14
R15
R18
R18
Rl9-R21
MOTOROLA ANALOG IC DEVICE DATA
75U
15 kn
3.eMU
a.8MU
8.2kn
220kn
220kn
2.2kU
4700
5.8kn
5.1 kn
10kn
3300
-:;-
R17
Cl-C3
C4,C6-C9,Cl3-C19,C22-024,C29
C5,C20
Cl0
Cll
C12
C21
C27
C28,C28
C30,C31
2.2~F
100nF
10 nF
1.0nF
100nF
22~F
10 nF
Ll
L2
50 ~H
50 ~H
VR1,VRS-VRll
VR2
VR3
VR4
10kO
5.0kU
200kn
1.0Mn
100~
47~F
1.0~F
9-197
MC13081X
The following describes a step-by-step procedure in
using the MC13801 for a typical multisync color monitor
chassis; component notations refer to Figure 2.
1. Horizontal Frequency Range Resistor
Network (Pins 11, 12)
FHm = Minimum Horizontal Frequency
FHx = Maximum Horizontal Frequency
Oscillator Transfer Constant =122 Hzlj.1A
The threshold voltage for Pin 46 is 0.7 V. The blanking
period depends on the amplitude, as shown in Figure 3 (X and
Y, respectively). A larger amplitude provides better
consistency and control of the blanking period.
Figure 3. Voltage for Flyback
RS = 6.3Sx 108
FHx - FHm
R6 = _;:---'S"--_ _
FHx
3.S
122 x 106 - RS
R4 s
v CC -
6.0
l.S
x RS and
For most applications, R4 = RS provides the
required results.
NOTE:
0.7V
V CC - 1.S
R4
< 1.0 mA
In order to compensate device/component tolerance, a
potentiometer is recommended in series with R6, as VR1.
2. Horizontal Frequency Range Phase Detector Filter
5. Frequency Switch (Pin 14 to 17)
There are two frequency switches available for screen
size compensation for different timing standards. Each
switch will turn on at the switch frequency set with its external
resistor. See Figure 4.
Network (Pin 10)
Figure 4. FH Switches
Typical values are:
C10 = 1.0 nF
C11 = 100 nF
R1S = S.6 k
C11 <: 100 x C10
Vee
NOTE: C10 and C11 should have less than 1.0 itA leakage.
3. Horizontal Free Running Frequency
The voltage at Pin 10 will be buffered to Pin 11, and
hence control the internal oscillator. In the absence of
horizontal sync signal, the free running horizontal frequency
will vary between preset minimum and maximum horizontal
frequency values.
If an undetermined free running frequency value is not
desired, a large impedance resistor can be used to pull
Pin 10 to VCC or Gnd, and the free running frequency will be
equal to FHm or FHx, respectively.
The free running frequency can also be set to any value
within the horizontal frequency range by using a voltage
divider, as R7 and R8 indicate.
R7
V11 = V D x R7 + R8
112 .
= R6
V11
V11 - S
+ VR1 - - - S -
Free Running Frequency = 112 j.1A x 12~AHZ
The above formula provides the ratio of R7 and R8. The
values chosen should be similar to those shown in Figure 2.
4. Horizontal Flyback Input (Pin 46)
The horizontal flyback signal not only provides proper
timing reference for the horizontal drive output, but also
supplies the necessary blanking for the video outputs.
There are two precautions for the flyback input. First, the
signal should have a zero volt reference, and second, the
peak value should be as near to VCC as possible.
9-198
1.0k
3.0k
5.0 V0---+---<>---1
The switch frequency is calculated as follow:
SF = Switch Frequency
S F = S x 2 x 122 x 10 6
Ra + Rb
In considering the ratio of Ra to Rb, the following
parameters, and their tolerances, need to be clarified:
1.losc
±10%
2. S.O Vref
±S%
3. Vhys
±S%
4. Ra, Rb
±?%
Internally, the lock-in horizontal frequency will build up a
current reference, and half of this current reference is used
for setting up a voltage and then compared with the internal
S.O Vref. Looking at the four parameters above, the first three
are IC related, while the last item depends on the external
component tolerance.
By adding up the first three items, the value of Ra and Rb
should be chosen to compensate for about 20% of system
tolerance.
Therefore, if Ra is chosen to be 70% of the calculated
value (Ra + Rb), Rb should be 60% of (Ra + Rb). That
MOTOROLA ANALOG IC.DEVICE DATA
MC13081X
means, the overall adjustment is about 70% to 130%, which
provides additional ±10% margin.
During normal operation, the frequency switch will switch
"off' when the pin voltage falls 60 mV below the 5.0 V
reference voltage (~4.94 V), and will switch "on" when the pin
voltage rises to 40 mV above the 5.0 V reference (~ 5.04 V).
An Example: Require Trip Point @ 35 kHz
+
Rb =
12~ xk2
jJA
5.0 V
35k
122x2 IlA
= 34857
n
Hysteresis @ 35 kHz = 5.04 - 4.94 V x 122 Hz
IlA
34857 n
= 350 Hz
=34857 n
Select Ra =24 k, and Rb =20 k Trim Pot
From above, Ra + Rb
The Temperature Coefficient of the potentiometer can also
be considered. If the value of the potentiometer and Ra vary
by 1% (for example) over temperature, the error would be:
5 x {
I
nil'---____~n'---
I
I
I
I
-
___
1
_
1
} x 122 Hz
34857 x 0.99
34857 x 1.01
IlA
= 350 Hz
6. Horizontal Position Compensation for Selected Scan
Frequency in Using FHA Switch
Refering to Figure1 (block diagram), tliere is an output
from the FHA switch to the horizontal drive output. When the
FHA switch is switched on, at a specified horizontal
frequency, there is a 1/Bth horizontal line shift of H-Ramp1.
Referring to Figures 5 and 9, a shift of H-Ramp1 will result in
a shift of the H-Drive output timing with respect to flyback
input.
The exact H-Drive output shift will be determined by the
PD2 voltage (Pin 45), which is generated by the flyback input
and the internal Comp1 output. That is related to the H-Drive
output transistor storage time.
MOTOROLA ANALOG IC DEVICE DATA
H-8ync
L- Wrthout
H-Drive
~r-----'L---_ _~
Trip Point Reference Current = 112
Ra
I
I
~I L
112 = 35 x 10 3 jJA
122
=
This function is particularly useful for high frequency scan
rates. The higher the frequency, the more significant the
storage time becomes, compared to the horizontal scan time.
Figure 5.
Shift
H-Drive
' - - - - - - WHh FHA
On
I
_I x I+- To Be Determined
By Application
7. Proper Horizontal Phase Control
The horizontal adjustment range depends on the phase
angle between the H-Sync signal and the horizontal flyback
input. In reality, the actual adjustment range is a
combination of horizontal frequency, front porchlback porch
timing, flyback pulse width, and horizontal output transistor
storage time. The following paragraph conveys the concept
for normal operation.
There are two clamping situations for video signals. In
case 1, separate VTTL and HTTL sync are provided, the
video signal is clamped at sync tip, and the dc voltage built up
is used for black level reference. In this instance, the clamp
pulse has the same pulse width as H-Sync, and nearly the
same position. This clamp pulse is blanked out internally. In
order to allow the video output to complete the blanking
action during horizontal retrace, the horizontal phase should
not be over-adjusted. See Figure 6 for a pictorial perception.
Accordingly, the total horizontal position adjustment range is
calculated as the sum of At1 and tl.t2.
Should the phase of horizontal flybacklH-Sync move
further left or rightfrom the normal adjustment range, the black
level reference voltage will be restored, and consequently a
slightly brighter than screen dark region will be observed
on-screen. See Figure 7 for pictorial explanation.
Horizontal Blanking Time = FPtime
+
Sync Width
+ BPtime =THB
Criterion for Normal Operation:
THB
IAt11 < -2-
THB
ltl.t21 < - -
2
In other words, the left/right 0.7 V threshold flyback
reference should be within the H-Sync pulse (shaded area
of Figure 6).
9-199
II
MC13081X
Figure 6. Horizontal Position Adjustment at Normal Operation
=w=
Ll12
HTTLSync
H-5yncWidth
I
- - - - - - - - - - -
Flyback Threshold = 0.7 V
Video Output
II
t - - - - - - . ; OV
9-200
Black Level Ref
f
MOTOROLA ANALOG IC DEVICE DATA
MC13081X
Figure 7. Horizontal Position Adjustment at Overscan Operation
HTILSync
Flyback Threshold = 0.7 V
I
I
I
I
I
I
I
A
I
I
Video Output
i Blanking Width
I
I
I
I
I
I
---t ----t ;---------------I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Ftyback Threshold = 0.7 V
II
Video Output
Black Level Ref
t
NOTE:
Region X will appear as bright vertical stripe.
MOTOROLA ANALOG IC DEVICE DATA
9-201
MC13081X
FigureS.
Video Input
I
I
I
I I
:nr--~---------
I I
I
I
I
I
I
I
-----------1-1
I
I
- - - - - - - - -
Clamp Pulse Position
Flyback Threshold = 0.7 V
I
Blanking Width
In case 2, composite sync is used instead of VTTL and
HTTL sync, the clamp pulse is located at the backporch of
the video signal, and the width of the clamp pulse is
calculated as follows:
Clamp Pulse Width = 64 x Line 1FreqUency x 3
Blanking Width =Sync Width + Clamp Pulse Width
+ Flyback Threshold (0.7 V) (See Figure 8)
From the above diagram, it can be seen that the horizontal
position adjustment is basically the same as case 1 except
slightly wider with the addition of clamp pulse blanking.
S. Horizontal Timing Relationship for Phase Detector 2
The following paragraphs explain the PLL2 mechanism.
Figure 9 portrays the timing signals of various parts of the IC.
In using the H-Sync pulse, which is generated from PLL1 ,
a horizontal ramp 1 signal is created. H-Ramp1 starts at
9-202
1/4th line before H-Sync and the ramping slope is directly
proportional to horizontal frequency. The lower tip of this
ramp is at approximately 1.2 V, and the amplitude is about
4.2 V. By adjusting the dc bias to the H-Phase control, a
pulse waveform is derived from this H-Ramp1.
A phase detector is used to compare the phase between
the pulse generated above, and the incoming flyback pulse.
An integrating capacitor is applied to generate a dc voltage.
This dc voltage, PD2F output, is used to slice the H-Ramp1
signal in order to generate Comp2 output pulse.
A second ramp signal, H-Ramp2, is triggered from this
Comp2 output. By applying a dc voltage (H-Width control) to
H-Ramp2, the Comp3 output pulses are generated.
The H-Drive output is formed by the rising edge of Comp2
output and the rising edge of Comp3 output.
It can be seen from Figure 9, if the H-Phase control is over
or under driven, it will reach the upperllower tip of H-Ramp1,
and thus PLL2 will be disturbed.
MOTOROLA ANALOG IC DEVICE DATA
MC13081X
Figure 9. Horizontal Timing for PLL2 Internal Sections
I_
1/4H
1
_I..
_I
1/2H
1
1
~~____~!______~Il~____________~Il~_________
H-5ync
1
1
I
.
1
I
1 ~
~
1
~
~_
1
. c " " ' : \ 4.2V
~
Z~:Z
12 V
.
1
\.......-;
t
'----"""""
1
~
\
(i\
--------' 1
~~
I
1'----"""""
I
I
I
I
!1
n
I
1
:z
£L
H-Phase
PD20utput
H-Aamp1
!I
H-Flyback
1
I
L
------JI
Comp1 Output
I
I
Comp2 Output
1
1
1
1
--f~+-----::::::::i"'''''~=----+----::===-''''~=----4----
il---:
~
1
I
1
1
I
I
i
I
1
~----~
c:::
H Pulse Width
H-Aamp2
Comp3 Output
1
1
J
MOTOROLA ANALOG IC DEVICE DATA
H-Drlve
9-203
11
MC13081X
Figure 10. Vertical Section
Free Running V-Ramp
Jl~----!
I
I
Vert Sync Pulse
I
1/4 V 1~_ _31=-4,-,V_ _ _..
I~"
I
I
I
Vert Oscillator
Vert Ramp Output
9. Vertical Frequency Range (Pins 48, 51, 52)
The MC13081X vertical oscillator is an injection-lock
type. The device can handle vertical frequency from 45 Hz
to 100 Hz.
The internal ramp generator will generate a ramp output in
the absence of a V-Sync signal. Upon receiving an external
vertical sync pulse, the ramp up portion is forced to retrace,
and therefore, the vertical ramp output is synchronized with
incoming V-Sync.
The slope of the Vertical Ramp output is directly
proportional to the current flowing out of Pin 52. Half of this
current is used to charge up the Vertical Ramp Capacitor. As
the charging current is increased, so does the ramp slope.
External feedback can be provided from Pin 48 to Pins 51
and 52 for linearity adjustment.
10. Vertical Free Running Frequency (Pins 1, 2)
The purpose of the vertical oscillator is to maintain a
vertical ramp to the deflection circuitry in the event the
vertical sync is not present. Because of the injection-lock
type, the free running frequency must be lower than the
system's lowest vertical frequency.
While various combinations of C4 and R9 can produce a
given frequency, it is recommended C4 be 0.1 f.1F in order to
obtain practical values for R9. The free running frequency
should be set at about 10% lower than the minimum
operating vertical frequency (54 Hz for a 60 Hz system).
R9 is then calculated from:
V CC -1.4
R9 = 96 x C4 x FV - 2.5 k
Connecting a potentiometer, (VR2) provides "Vertical
Hold" adjustment.
9-204
11. X-Ray Shutdown Protection (Pin 41)
The X-Ray input (Pin 41) permits shutting off the
horizontal drive, usually by external circuitry which monitors
faults within the high voltage supply, such as excess anode
current. This input is activated by taking it above = 0.6 V
which causes the drive transistor at Pin 43 to be turned on
(low) permanently by an internal latch.
An external resistor must be connected to Pin 41 to limit
the input current, and to assist with the latching action (see
Figure 11). 10 kn is a typical value, but the value can be
chosen based on the specifies of the driving circuit. The
external resistor reduces the sensitivity of Pin 41 to noise and
transients which may otherwise result in false latches.
To resume normal operation (after correction of the fault),
lower Pin 41 below 0.4 V. If the external circuit's normal
operation does not take it below 0.4 V, but does take it below
0.6 V, then recycle Vec "off'-"on". If the pin is not used, it
must be connected to ground.
The minimum holding current to keep the latch on is
=70 f,1A, while the minimum turn-on current is =0.4 f.1A.
Figure 11. X-Ray Shutdown Circuit
r----_-l4--5.0 V
H-Orive
Shutdown
X~~>-~IAO~k-c41~~~
Shutdown
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC13280AY
MC13281A/B
Advance Information
80/100 MHz Video Processor
MHz VIDEO
PROCESSOR
80/100
The MC13280AY and MC13281 AlB are three channel wideband amplifiers
designed for use as a video pre-amplifier in high resolution RGB color
monitors.
Features:
• 4.0 Vpp Output Swing
• 3.5 ns Rise/Fall Time, 100 MHz Bandwidth (MC13281 AlB)
• 4.3 ns Rise/Fall Time, 80 MHz Bandwidth (MC13280AY)
• Main Contrast Control
• Blanking and Clamping Inputs
• Packages: NOIP-24 and NOIP-20
• A Single PC Board Pattern Can Accept the MC13281 A and the
MC13282A (Video Amplifier with OSO)
PIN CONNECTIONS
Operating
Temperature Range
Package
TA: 0' to +70'C
Plastic DIP
MC13281BP
Blank
R Subcontrast
Rlnput
G Subcontrast
Glnput
B Subcontrast
Plastic DIP
MC13281AP
PLASTIC PACKAGE
CASE 738
1
ORDERING INFORMATION
MC13280AYP
PLASTIC PACKAGE
CASE 724
1
• Subcontrast Controls for Each Channel
Device
_,sum,
_ 'su~
Plastic DIP
Clamp
GEmitter
Blnput
ABSOLUTE MAXIMUM RATINGS
Rating
Power Supply Voltage
Pin
Value
Unit
VCC
VideoVcc
-0.5,10
-0.5,10
Vdc
Voltage at Video Amplifier Inputs
2,4,6
-0.5, +5.0
Vdc
VideoVcc
120
mA
Storage Temperature
-
-65 to +150
°c
Junction Temperature
-
150
°c
Collector-Emitter Current (Three Channels)
NOTES: 1. Devices should not be operated at these limits. Refer to "Recommended
Operating Conditions" section for actual device operation.
2. ESD data available upon request.
II
REmitter
RClamp
V5
Gnd
GClamp
N/C
VCC
VideoVCC
BClamp
BEmiller
Fast Commutate
N/C
NlC
NlC
Contrast
(Top View)
R Subcontrast
Rlnput
G Subcontrast
Blank
Clamp
Glnput
B Subcontrast
Blnput
RClamp
V5
REmitter
GEmitter
GClamp
Gnd
VideoVCC
BClamp
VCC
Contrast
BEmitter
Fast Commutate
(Top View)
MOTOROLA ANALOG IC DEVICE DATA
9-205
MC13280AV MC13281AlB
RECOMMENDED OPERATING CONDITIONS
. Characteristic
Power Supply Voltage
Pin
Min
Typ
Max
Unit
VCC,
Video VCC
7.6
8.0
8.4
Vdc
Contrast
0
-
5.0
Vdc
Subconlrast Control
1,3,5
0
-
5.0
Vdc
Blanking Input Signal Amplitude
Blank
0
-
5.0
V
Clamping Input Signal Amplitude
Clamp
0
-
5.0
V
Video Signal Amplitude
(with 75 0 Tennination)
2,4,6
-
0.7
1.0
Vpp
VideoVcc
0
-
50
mA
Clamp
500
-
-
ns
0
-
70
°c
Contrast Control
Collector-Emitter Current (Total for Three
Channels)
Clamp Pulse Width
Operating Ambient Temperature
-
ELECTRICAL CHARACTERISTICS (Refer to Test Circuit Figure 1, TA = 25°C, VCC = 8.0 Vdc.)
Characteristic
Input Impedance
Condition
Pin
Min
Typ
Max
-
2,4,6
100
-
-
kD
-
2.4
-
Vdc
3.6
4.0
-
Vpp
-
5.6
-
VN
Internal DC Bias Voltage
=
=
=
Output Signal Amplitude
Unit
V2, V4, V6 0.7 Vpp
Vl, V3, V5 5.0 V
Contrast 5.0 V
R,G,B
Emitters
=
Contrast
-
-26
-
dB
Vl, V3, V5 5.0 to 0 V
Contrast 5.0 V
1,3,5
-
-26
-
dB
Emitter DC level
-
-
1.0
1.2
1.4
Vdc
Blanking Input Threshold
-
Blank
-
1.25
-
V
Clamping Input Threshold
-
Clamp
-
3.75
-
Voltage Gain
Contrast Control
Contrast 5.0 to 0 V
Vl, V3, V5 5.0 V
=
=
Subcontrast Control
Video Rise Time
MC13280AY
MC13281A1B
MC13280AY
MC13281AlB
V2, V4, V6 0.7 Vpp
Vout 4.0 Vpp
Rl > 300 n, Cl < 5.0 pF
MC13280AY
MC13281AlB
V2, V4, V6 0.7 Vpp
Vl, V3, V5, Contrast 5.0 V
Rl > 300 D, Cl < 5.0 pF
9-206
=
=
=
=
Video Bandwidth
NOTE:
=
V2, V4, V6 0.7 Vpp
Vout 4.0 Vpp
Rl> 300 D, Cl < 5.0 pF
Video Fall Time
Power Supply Current
=
VCC, Video VCC
=
=8.0 V
R,G,B
Emitters
R,G,B
Emitters
R,G,B
Emitters
-
V
ns
-
4.3
3.5
-
-
4.3
3.5
-
-
80
100
-
-
70
-
ns
MHz
mA
It is recommended to use a double sided PCB layout for high frequency measurement (e.g., riseffall time, bandwidth).
MOTOROLA ANALOG IC DEVICE DATA
MC13280AY MC13281AIB
Figure 1. Internal Block Diagram
r--------------------------------·
Fast commutat~
I RClamp
I
I
I
I
I
I
Rlnput
I
I
I
I VideoVCC
I
I
I REmitter
I
I
I
I
I
I
I
I
I
I
I
I
I
RSubcontrast I
Q-l----I---I
Contrast and Subcontrast
Control Processor
RChannel
r -_ _ _ _ _ _ _4-~__j-_+oIGC~mp
I
I
I
I
I
I
I
I
I
I
I
I
Glnput I
o-!---__ji--+--1
IGEmitter
I
I
I
I
I
I
GSubcontrast I
0+---1---1
'--__j-+-~---tO
I
-+----+-l__lkiBlank
r - - - t -_ _
II
L-=:::==--->----t-t---+-/<51Clamp
Contrast and Subcontrast
Control Processor
GChannel
I
I
I BClamp
r-------------+-4-~~~
I
I
I
I
I
I
I
I
I BEmitter
I
I
I
,_I
I
""""'""-
.....
Control Processor
B;:~
I Gnd
I
.--------------------------------~
This device contains 272 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
9-207
MC13280AY MC13281AIB
PIN FUNCTION DESCRIPTION
MC13280AY
MC13281B
Pin
MC13281A
Pin
Name
Equivalent Internal Circuit
R
Subcontrast
Control
3
3
G
Subcontrast
Control
5
5
B
Subcontrast
Control
2
2
R Input
4
4
G Input
6
6
Blnput
Description
These pins provides a maximum of
26 dB attenuation to vary the gain of
each video amplifier separately.
Vee
SOk
S.OV
Input voltage is from 0 to 5.0 V.
Increasing the voltage will increase
the contrast level.
-=
The input coupling capacitor is used
for input clamping storage. The
maximum source impedance is 100 Q.
to
Input polarity of the video signal is
positive.
0.1
Nominal 0.7 Vpp input signal is
recommended (maximum 1.0 Vpp).
-=
7
N/A
II
7
Ground
Ground pin. Connect to a clean, solid
ground.
Connected to ground.
8
N/C
10
N/C
11
N/C
12
N/C
8
9
VCC
9
13
Contrast
Connect to 8.0 Vdc supply, ±5%.
Oecoupling is required at this pin.
S.OV
2.SV
Overall Contrast Control for the three
channels.
The input range is 0 V to 5.0 V. An
increase of voltage increases the
contrast.
-=
10
14
Fast
Commutate
11
15
BEmitter
Output
15
19
GEmitter
Output
18
22
REmitter
Output
Must be connected to ground.
The video outputs are configured as
emitter-followers with a driving
capability of about 15 mA each.
Vee
Video
Signal
The dc voltage at these three emitters
is set to 1.2 V (black level).
Contrast
RE=330
Typical
The dc current through the output
stage is determined by the emitter
resistors (typically 330 Q).
-=
9-208
MOTOROLA AN~LOG IC DEVICE DATA
MC13280AY MC13281A1B
PIN FUNCTION DESCRIPTION (continued)
MC13280AY
MC13281B
Pin
MC13281A
Pin
12
16
BClamp
Capacitor
14
18
GClamp
Capacitor
17
21
R Clamp
Capacitor
13
17
VideoVcc
16
20
5.0 Vref (V5)
Name
Equivalent Internal Circuit
Description
A 100 nF capacitor is connected to
.
each of these pins.
The capacitor is used for video output
dc restoration.
,'
Connect to 8.0 V dc supply, ±5%. The
VCC is for the video output stage. It is
internally connected to the collectors
of the output transistors.
5.0 V regulator. Minimum 10 jJ.F
capacitor is required for noise filtering
and compensation. It can source up
to 20 mA but not sink current. Output
impedance is = 10 Q. Recommended
for use as a voltage reference only.
5.0V
19
23
This pin is used for video clamping.
Clamp
The threshold clamping level is 3.75 V.
3.75 V
20
24
Blank
This pin is used for video blanking.
The threshold blanking level is 1.25 V.
1.25V
MOTOROLA ANALOG IC DEVICE DATA
9-209
MC13280AY MC13281AIB
FUNCTIONAL DESCRIPTI.ON
The MC13280AY and MC13281A1B are composed of
three video amplifiers, clamping and blanking circuitry with
contrast and subcontrast controls. Each video amplifier is
designed to have a -3.0 dB bandwidth of 100 MHz
(MC13281, 80 MHz for the MC13280) with a gain of up to
about 5.6 VN, or 15 dB.
Video Input
The video input stages are high impedance and designed
to accept a maximum signal of 1.0 Vpp with 75 0 termination
(typically) provided externally. During the clamping period, a
current is provided to the input capacitor by the clamping
circuit which brings the input to a proper dc level (nominal
2.0 V). The blanking and clamping signals are to be provided
externally, with their thresholds at 1.25 V and 3.75 V,
respectively.
Video Output
The video output stages are configured as emitterfollowers, with a driving capability of about 15 mA for each
channel. The dc voltage at these three emitters is set to 1.2 V
(black level). The dc current through each output stage is
determined by the emitter resistor (typically 330 0).
Contrast Control
The contrast control varies the gain of three video
amplifiers from a minimum of 0.3 VN to a maximum of
5.6 VN when all subcontrast levels are set to 5.0 V.
Subcontrast Control
Each subcontrast control provides a maximum of 26 dB
attenuation on each video amplifier separately.
Clamp Pulse Input
The clamping pulse is provided externally, and the pulse
width must be no less than 500 ns.
Blank Pulse Input
The blanking pulse is used to blank the video signal during
the horizontal sync period, or used as a control pin for video
mute function.
Fast Commutate
This pin should be connected to ground.
Power Supplies
VCC and Video VCC supplies are to be 8.0 V ±5%.
Figure 2. Test Circuit
Fast
Commutate
II
C1
0.1
Rlnput
G Input
C2
0.1
B Input
C3
0.1
R1
75
R2
75
Rlnput
R Output
REmitter t-O----_~..
G Input
G Emitter
I-O----<~--t-..
Blnput
B Emitter
I-O---<~-t----t-. .
GOutput
BOutput
R4
330
R3
75
MC13280AY
MC13281AIB
R Clamp 1-0--------,
G Clamp 1-0----"-1
C12
Gnd
BClamp
C13
0.11
C11T 0.11
0.1
-=-
-=-
-=-
Clamp Capacitor
R
Subcontrast Control
G
B
+C5
C4
0.1p10 1lF
C10
TO.1
-=-
-=-
5.0V
-=-
9-210
Contrast
-=-
-=-
MOTOROLA ANALOG IC DEVICE DATA
MC13280AV MC13281A1B
APPLICATION INFORMATION
PCB Layout
Care should be taken in the PCB layout to minimize the
noise effects. The most sensitive pins are VCC, Video VCC,
V5 and Clamp. It is strongly recommended to make a ground
plane and connect VccNideo VCC and ground traces, to the
power supply directly. Separate power supply traces should
be used for VCC and Video VCC and decoupling capacitors
should be connected as close as possible to the device.
Multi-layer ceramic and tantalum capacitors are
recommended. V5 is designed as a 5.0 V voltage reference
for contrast, and RGB subcontrast controls, so the same
precautions for VCC should also be applied at this pin. The
Clamp capacitors should be connected to ground close to
IC's ground pin, or power supply ground. The copper trace of
video signal inputs and outputs should be as short as
possible and separated by ground traces to avoid any RGB
cross-interference. A double sided PCB should be used to
optimize the device's performance.
RGB Input and Output
The RGB output stages are designed as emitter-followers
to drive the CRT driver circuitry directly. The emitter reSistors
used are 330 n (typically) and the driving current is 15 mA
maximum for each channel. The loading impedance
connected to the output stages should be greater than 330 n
and less than 5.0 pF for optimum performance (e.g., riselfall
time, bandwidth, etc.). Decreasing the resistive load will
reduce the rise/fall time by increasing the driving current, but
the output stage may be damaged due to increasing power
dissipation at the same time. The frequency response is
affected by the loading capacitance. The typical value is 3.0
to 5.0 pF. Figure 3 shows a typical interface with a video
output driver. For high resolution color monitor application, it
is recommended to use coaxial cable or shielded cable for
input signal connections.
Clamp and Blank Input
The clamp input is normally (except for Sync-on-Green)
connected to a positive horizontal sync pulse and has a
threshold level of 3.75 V. It is used as a timing reference for
the dc restoration process, so it cannot be an open circuit. If
Sync-on-Green timing mode is used, the clamping pulse
should be located at the horizontal back porch period instead
of horizontal sync. Otherwise, the black level will be clamped
at the wrong dc level.
The blank input is used as a video mute, or horizontal
blanking control pin, and is normally connected to a blanking
pulse generated from the flyback or MCU. The threshold level
is 1.25 V. The blanking pulse width should be equal to the
flyback retrace period to make sure that the video signal is
blanked properly during retrace. It is necessary to limit the
amplitude and avoid any negative undershoot if the flyback
pulse is used. The blanking input pin cannot accept a
negative voltage. This pin should be grounded if it is not used.
II
MOTOROLA ANALOG IC DEVICE DATA
9-211
MC13280AY MC13281 ~
Figure 3. Interfacing with Video Output Drivers
CRT Driver VCC
Reference Voltage o--+¥.."v--1 Clamp
RGBOutput
MC13280AY
MC13281AlB
B Emitlerl-O..........:-:-:,-----R Clamp 1-0--------,
Video Processor
G Clamp 1-0------.
Blank
Fast
Commutate Contrast
-=
Clamp
Input
Blank
Input
s.ov
i
:':1 ~I ~~T
-::-
SOk
VRS
-=
9--212
MOTOROLA ANALOG IC DEVICE DATA
MC13280AY MC13281A1B
Figure 4. RGB In/Out Linearity
Figure 5. Contrast Control
4.5
4.0
Q:
::':
=>
2.0
c
1.5
w
:>
L/
2.5
0
0
1.0
0.5
4.0
v
3.5
~ 3.0
5
./
./
Q:
Q.
3.5
3.0
G
=>
D-
2.5
=>
2.0
l-
./
w
c
:>
./
1.5
1.0
0.5
0.2
/
l-
0
0
L
o1/
o
0.4
0.6
---
o
o
0.8
VIDEO INPUT (Vpp)
-
4.5
4.0
/
3.5
~ 3.0
l-
=>
D-
50
2.5
2.0
@ 1.5
c
:>
1.0
0.5
o~
o
/
V
/
/
/
/
/
2.0
4.0
-20
iii
~
z
Q
..JO
1
!;;: -40
=>
z
w
~
-50
4.0
MOTOROLA ANALOG IC DEVICE DATA
6.0
BlueChann~
-60
-70
SUBCONTRAST VOLTAGE (V)
6.0
CONTRAST CONTROL VOLTAGE (V)
-10
/
2.0
/
/
/
/"
Figure 7. Crosstalk From Green to Red
and Blue Channels
Figure 6. Subcontrast Control
Q:
-
4.5
-80
I'...
~
1.0
.......
f::::.
10
"'
V
I
rid,crmnel
100
1000
f, FREQUENCY (MHz)
9-213
II
MC13280AY MC13281AIB
Figure 9. Fall Time for MC13281B
Figure 8. Rise Time for MC13281B
100mVlDIV
5.0 nslDIV
100mVlDIV
5.0 nslDIV
10xPROBE
10xPROBE
NOTE: Recommend to use a double sided PCB without any socket for risellall time measurements, using an input pulse with
1.5 ns risellall time and an active probe with 1.7 pF capacitance loading.
Figure 10. Single Sided PCB Layout
(Component Side) for MC13280AY, MC13281B
II
NOTE: J = Jumper
9-:-214
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROL.A
MC13282A
Advance Information
100 MHz Video Processor
with OSD Interface
The MC13282A is a three channel wideband amplifier designed for use as
a video pre-amp in high resolution RGB color monitors.
100 MHz VIDEO PROCESSOR
WITH OSD INTERFACE
Features:
SEMICONDUCTOR
TECHNICAL DATA
• 4.0 Vpp Output with 100 MHz Bandwidth
• 3.5 ns Rise/Fall Time
• Subcontrast Control for Each Channel
• Blanking and Clamping Inputs
• Contrast Control
• OSD Interface with 50 MHz Bandwidth
• OSD Contrast Control
• Package: NDIP-24
ABSOLUTE MAXIMUM RATINGS
Rating
Power Supply Voltage - VCC
Value
Unit
9
-0.5,10
Vdc
17
-0.5,10
Vdc
2,4,6,8,
10,12
-0.5, +5.0
Vdc
Power Supply Voltage - Video VCC
Voltage at Video Amplifier Inputs
Pin
Collector-Emitter Current (Three Channels)
17
120
mA
Storage Temperature
-
-6510+150
°c
Junction Temperature
-
150
°c
..
NOTES: 1. Devices should not be operated at these limits. Refer to "Recommended
Operating Conditions" section for actual device operation.
2. ESD data available upon request.
Characteristic
II
PIN CONNECTIONS
R Subcontrast
Blank
R Input
Clamp
G Subcontrast
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage
PSUFFIX
PLASTIC PACKAGE
CASE 724
G Input
B Subcontrast
REmitter
RClamp
V5
GEmiller
Pin
Min
Typ
Max
Unit
B Input
9,17
7.6
8.0
8.4
Vdc
Gnd
RoSD
VCC
GClamp
Video VCC
BClamp
BEmiller
13
0
-
5.0
Vdc
1,3,5
0
5.0
Vdc
Blanking Input Signal Amplitude
24
0
-
5.0
V
GOSD
OSD Contrast
Clamping Input Signal Amplitude
23
0
-
5.0
V
BOSD
2,4,6
-
0.7
1.0
Vpp
8,10,12
-
TTL
-
V
Collector-Emitter Current
(Total for Three Channels)
17
0
-
50
mA
Clamping Pulse Wiclth
23
500
-
-
ns
Device
Operating
Temperature Range
Package
Operating Ambient Temperature
-
0
-
70
°C
MC13282AP
TA = 0° to +70°C
Plastic DIP
Contrast Control
Subcontrast Control
Video Signal Amplitude
(with 75 Q Termination)
OSD Signal Input
MOTOROLA ANALOG IC DEVICE DATA
Fast Commutate
Contrast
(Top View)
ORDERING INFORMATION
9-215
MC13282A
ELECTRICAL CHARACTERISTICS (Refer to Test Circuit Figure 1, TA = 25°C, VCC = B.O Vdc.)
Characteristic
Input Impedance
Condition
Pin
Min
Typ
Max
-
2,4,6
100
-
-
kQ
Unit
-
2.4
-
Vdc
3.6
4.0
-
Vpp
-
5.6
VN
13
-
-26
-
V1, V3, V5 = 5.0toO V'
VI3=5.0V
1,3,5
-
-26
-
dB
-
15,19,22
1.0
1.2
1.4
Vdc
Blanking Input Threshold
24
1.25
Clamping Input Threshold
-
-
V
Internal DC Bias Voltage
Output Signal Amplitude
Voltage Gain
Contrast Control
Subcontrast Control
Emitter DC Level
V2, V4, V6 = 0.7 Vpp
V1, V3, V5, V13 = 5.0 V
V14=OV
15,19,22
V13=5.0100V
V1, V3, V5 = 5.0 V
dB
V2, V4, V6 = 0.7 Vpp
Vout = 4.0 Vpp
RL > 300 Q, CL < 5.0 pF
15,19,22
-
3.5
-
Video Bandwidth
V2, V4, V6 = 0.7 Vpp
V1, V3, V5, V13 = 5.0 V
V14 = 0 V
RL > 300 Q, CL < 5.0 pF
15,19,22
-.
100
-
MHz
OSD Rise lime
VB, V10, V12 = TTL Level
V11 = 5.0 V, V14 = 5.0 V
15,19,22
-
7.0
-
ns
-
7.0
-
VB, V10, V12 = TTL Level
V11 = 5.0 V, V14 = 5.0 V
15,19,22
-
50
-
MHz
-
-
-
17
VCC, Video VCC = B.O V
9,17
-
70
-
mA
Video Rise lime
Video Fall lime
OSDFaliTime
OSD Bandwidth
OSD Propagation Delay
Power Supply Current
NOTE:
23
3.75
3.5
V
ns
ns
It is recommended to use a double sided PCB layout for high frequency measurement (e.g., riseJfaU time, bandwidth).
II
9-216
MOTOROLA ANALOG IC DEVICE DATA
MC13282A
Figure 1. Internal Block Diagram
,--------------------------------.
Fast Commutate
,
' RClamp
, 21
,,
,
,,
,,
14,
.---t_ _......_-;'-ovideo VCC
,
R Input
,
,17
O
2 -!-,--t--+---I
,
, REmitter
'---+---+-+0
o-t---t------j
8,
,
R Subcontrast '
,,
,,
,
,22
ROSO'
RChannel
.--_ _ _ _ _ _ _+--+--t__'roG Clamp
,,
,,
,,
,18
,,
,,
13'
Glnput'
o-t--HH-+---i
4,
,
GOSO'
OT--HH---1
3',
,
, GEmitter
'----t-t---t--+O
'19
,-----,.---1--1--1--1-<3'Blank
G Channel
OSO Centrast ,
,,
111
B Input'
6,,
O+---+-HI----<~
BOSO
102-!-'--1-+-+---1
,
BChannel
This device contains 272 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
9-217
MC13282A
PIN FUNCTION DESCRIPTION
R Subcontrast
Control
3
G Subcontrast
Control
5
B Subcontrast
Control
2
R Input
4
G Input
These pin provides a maximum of 26 dB attenuation
to vary the gain of each video amplifier separately.
Vee
Input voltage is from 0 to 5.0 V. Increasing the voltage
will increase the contrast level.
5.0V
10----0+-----[
The input coupling capacitor is used for input
clamping storage. The maximum source impedance
is100Q.
Input polarHy of the video signal is positive.
Nominal 0.7 Vpp input signal is recommended
(maximum 1.0 Vpp).
6
Blnput
8
ROSD Input
10
Vee
GOSD Input
SOk
II
12
BOSD Input
9
VCC
Connect to 8.0 Vdc supply, ±5%. Decoupling is
required at this pin.
11
OSD Contrast
On Screen Display contrast control.
60k
-=-
Input voltage is from 0 to 5.0 V. Increasing the voltage
will increase the contrast of the OSD signal.
13
Contrast
Overall Contrast Control for the three channels.
The input range is 0 V to 5.0 V. An increase of voltage
increases the contrast.
9-218
MOTOROLA ANALOG IC DEVICE DATA
MC13282A
PIN FUNCTION DESCRIPTION (continued)
14
Fast Commutate
This pin is used in conjunction with the RGB OSD
inputs. It is a high speed switch used for overlaying
text on picture. A logic low selects Pins 2, 4, 6. A logic
high selects Pins 6, 10, 12.
Vee
-=15
B Emitter Output
19
G Emitter Output
22
R Emitter Output
16
BClamp
Capacitor
The video outputs are configured as emitter-followers
with a driving capability of about 15 mA each.
The dc voltage at these three emitters is set to 1.2 V
(black level).
Video
Signal
Conlrast
RE= 330
Typical
The dc current through the output stage is determined
by the emitter resistors (typically 330 0).
-=A 100 nF capacitor is connected to each of these pins.
1.2V
VideoOul
The capacitor is used for video output dc restoration.
I-=-
16
GClamp
Capacitor
21
RClamp
Capacitor
17
VideoVcc
Connect to 6.0 V de supply, ±50/0. This VCC is for the
video output stage. It is internally connected to the
collectors of the output transistors.
20
5.0 Vref (V5)
5.0 V regulator. Minimum 10 I-lF capacitor is required
for noise filtering and compensation. It can source
up to 20 mA but not sink current. Output impedance
is ~ IOn. Recommended for use as a voltage
reference only.
5.0 V
R
MOTOROLA ANALOG IC DEVICE DATA
O.SR
9-219
II
MC13282A.
PIN FUNCTION DESCRIPTION (continued)
Pin
23
Name
Clamp
Equivalent Internal Circuit
Description
I
I
I
I Vref2
I
I
This pin is used for video clamping.
The threshold clamping level is 3.75 V.
3.75 V
24
Blank
This pin is used for video blanking.
Vee
Vref1
The threshold blanking level is 1.25 V.
Vref2
1.25V
FUNCTIONAL DESCRIPTION
The MC13282A is composed of three video amplifiers,
clamping and blanking circuitry with contrast and subcontrast
controls and OSD interface. Each video amplifier is designed
to have a -3.0 dB bandwidth of 100 MHz with a gain of up to
about 5.6 VN, or 15 dB.
II
Video Input
The video input· stages are high impedance and designed
to accept a maximum signal of 1.0 Vpp with 75 0 termination
(typically) provided externally. During the clamping period, a
current is provided to the input capacitor by the clamping
circuit which brings the input to a proper dc level (nominal
2.0 V). The blanking and clamping signals are to be provided
extemally, with their thresholds sitting at 1.25 V and 3.75 V,
respectively.
Video Output
The video output stages are configured as
emitter-followers, with a driving capability of about 15 mA for
each channel. The dc voltage at these three emitters is set to
1.2 V (black level). The dc current through each output stage
is determined by the emitter resistor (typically 330 0).
Subcontrast Control
Each subcontrast control provides a maximum of 26 dB
attenuation on each video amplifier separately.
OSD Interface
The three OSD inputs are TIL compatible and have a
typical bandwidth of 50 MHz. A fast commutate pin is
provided to select either the video or the OSD inputs as the
source for the outputs. OSD contrast control is also
provided to set the amount of gain required when OSD
inputs are selected.
Clamp Pulse Input
The clamping pulse is provided externally, and the pulse
width must be no less than 500 ns.
Blank Pulse Input
The blanking pulse is used to blank the video signal during
the horizontal sync period, or used as a control pin for video
mute function.
Power Supplies
VCC and Video VCC supplies are to be 8.0 V ±5%.
Contrast Control
The contrast control varies the gain of three video
amplifiers from a minimum of 0.3 VN to a maximum of
5.6 VN when all subcontrast levels are set to 5.0 V.
9-220
MOTOROLA ANALOG IC DEVICE DATA
MC13282A
Figure 2. Test Circuit
24
Blank
Video
Inputs
C1
0.1
r~
C2
0.1
G Input
Fast
Commutate
Video
VCC
VCC
Rlnput
REmitter
Glnput
GEmitter
B Input
BEmitter
B Input
22
ROutput
19
G Output
15
B Output
R4
330
ROSD
={
10
Inputs
12
-=
MC13282A
GOSD
RClamp
BOSD
GClamp
7
R2
75
-=
C13
C12
0.1
-=
R3
75
-=
18
C11,T
0.1
20
R6
330
21
BClamp 16
Gnd
R1
75
R5
330
I-=
0.11
-=
Clamp Capacitor
R
Subcontrast Control
G
B
OSD
Contrast
Contrast
11
13
3
+ C5
C p 1 0 llF
0.1
-=
-=
-=
-=
II
-=
APPLICATION INFORMATION
PCB Layout
Care should be taken in the PCB layout to minimize the
noise effects. The most sensitive pins are VCC (9), Video VCC
(17), V5 (20), Clamp (16, 18,21). It is strongly recommended
to make a ground plane and connect VccNideo VCC and
ground traces to the power supply directly. Separate power
supply traces, should be used for VCC and Video VCC and
decoupling capacitors should be connected as close as
possible to the device. Multi-layer ceramic and tantalum
capacitors are recommended. Pin 20 (V5) is designed as a
5.0 V voltage reference for contrast, RGB subcontrast and
OSD contrast controls, so the same precaution for VCC
should be also applied at this pin. The Clamp capacitors at
Pins 16,18 and 21 should be connected to ground close to
IC's ground Pin 7 or power supply ground. The copper trace
of the video signal inputs and outputs should be as short as
possible and separated by ground traces to avoid any RGB
cross-interference. A double sided PCB should be used to
optimize the device's performance.
RGB Input and Output
The RGB output stages are designed as emitter-followers
to drive the CRT driver circuitry directly. The emitter resistors
used is 330 n (typically) and the driving current is 15 mA
MOTOROLA ANALOG IC DEVICE DATA
maximum for each channel. The loading impedance
connected to the output stages should be greater than 330 n
and less than 5.0 pF for optimum performance (e.g., rise/fall
time, bandwidth, etc.). Decreasing the resistive load will
reduce the riselfall time by increasing the driving current, but
the output stage may be damaged due to increasing power
dissipation at the same time. The frequency response is
affected by the loading capacitance. The typical value is 3.0
to 5.0 pF. Figure 4 shows a typical interface with a video output
driver. For a high resolution color monitor application, it is
recommended to use coaxial cable or shielded cable for input
signal connections.
Clamp and Blank Input
The clamp input is normally (except for Sync-on-Green)
connected to a positive horizontal sync pulse, and has a
threshold level of 3.75 V. It is used as a timing reference for
the dc restoration process, so it cannot be left open. If
Sync-on-Green timing mode is used, the clamping pulse
should be located at horizontal back porch period instead of
horizontal sync tip. Otherwise, the black level will be clamped
at an incorrect voltage.
The blank input is used as a video mute, or horizontal
blanking control, and is normally connected to a blanking
9-221
MC13282A
pulse generated from the flyback or from an MCU. The
threshold level of 1.25 V. The blanking pulse width should be
equal to the flyback retrace period to make sure that the
video signal is blanked properly during retrace. It is
necessary to limit the amplitude, and avoid any negative
undershoots if the flyback pulse is used. This Blanking input
pin cannot accept a negative voltage. This. pin should be
grounded if it is not used.
OSD interface
Figure 3 show a typical application with an aso device
(MC141540). The MC141540 aso and FC outputs are TTL
compatible, and therefore interface directly with MC13282A.
Level shifting circuitry is not needed. The MC141540 is a
digital device, controlled by an MCU. Therefore, separate
power supply runs to the MC141540 and to the MC13282A
are recommended. Care should be taken in the PC board
layout to prevent digital noise from entering the analog
portions of MC13282A.
Normally the aso switching is done during the active
video time. It is recommended that the Fast Commutate pin
not be activated during the horizontal sync time.
Figure 3. Interfacing with OSD Device
5.0V
B.OV
CB
~----,TO.l
R
G
B
Contrast Contrast Contrast
Cl 0.1
R Input 0----.------1
R Input
G Input 0---t--._---1
Glnput
B Input o---t---!-_--J
B Input
Rl
75
R2
75
II
Gnd
VCC
Video
VCC
::::::::::~~~~~~~:.}
:
RGB Output
B Emitterl-O...-,....,..,---..
MC13282A
Video Processor
with OSD Interface
R3
75
.....
'--
VS
R Clamp 1-0------....,
,----(>-1 Clamp
G Clampl-O~--.........,
---'
Blank
Fast
OSD
ROSoGOSD BoSD Commutate Contrast
s.OV
Clamp
Input
Blank
Input
VR4
50k
RoSD GOSD BOSD
o----{)-/
S.OV
Fast
HTone
Commutate
ss
~VR5
l
VDD
s0k
5.0V
1-0..----.
VSS 1-0*-""':""'---"
MC141540
On Screen Display
Processor
MCU Interface o----{)-/ MOSI
VDDA 1-0......--....---'
o----{)-ISCK
9-222
HF/B
VFIB
. Hsyn
Input
Vsyn
Input
Rll
7.Sk
MOTOROLA ANALOG IC DEVICE DATA
MC13282A
Figure 4. Interfacing with Video Output Drivers
CRT DriverVcc
Reference Voltage D--.....-AAfIr<'-+-l
5.0V
B.OV
+------,T
R
G
B
Contrast Contrast Contrast
Cl
V5
Gnd
VCC
0.1
CB
0.1
Video
VCC
II
R Emilterl-O......,....,..,....---l--"t---'
Rlnput
R Input
C2 0.1
G Emilterl-O......,....,..,....--.
Glnput
Glnput
C3 0.1
B Input
B Input
R1
75
R2
75
R3
75
MC13282A
Video Processor
with OSD Interface
Clamp
RGBOutput
B Emilterl-O......,....,..,....--.
R Clamp 1-0>---------,
G Clamp 1-0-------,
Blank
Fast
OSD
ROSD GOSD BOSD Commutate Contrast
Contrast
5.0V
Clamp
Input
Blank
Input
v
OSD Input and Control
MOTOROLA ANALOG IC DEVICE DATA
i
-=50k
VR5
-=-
9-223
MC13282A
Figure 6. Color Contrast
Figure 5. RGB In/Out Linearity
4.5
4.0
~
....
3.0
2.5
0
2.0
D..
....
:::>
4.0
v
3.5
:::>
/"
@
c 1.5
:>
/"
/'
/'
~
~
0.5
oL
!3
3.0
1.5
c
:>
1.0
0.5
0.2
0.4
0.6
/
2.0
w
/'
o
3.5
2.5
0
0
./
1.0
---
-
Figure 7. Subcontrast Control
4.5
4.0
5D..
50
@
~
3.0
2.5
2.0
1.5
1.0
0.5
II
/
3.5
---
o
o
/
./
V
/
/
/
2.0
4.0
6.0
Figure 8. OSD Contrast Control
4.5
4.0
8:
~
....
:::>
D..
....:::>
0
3.5
V
3.0
2.0
/'
0.5
o L
o
6.0
L
L
2.5
1.0
4.0
/
CONTRAST CONTROL VOLTAGE (V)
@
c 1.5
:>
2.0
L
/
/
/
./
o
o
O.B
VIDEO INPUT (Vpp)
~
-
4.5
SUBCONTRAST VOLTAGE (V)
/'
/'
/'
2.0
4.0
6.0
OSD CONTRAST CONTROL VOLTAGE (V)
Figure 9. Crosstalk From Green to Red
and Blue Channels
0
-10
:z
w
~
BlueChann';!.
-50
-00
-70
-80
~
1.0
-.....; ~~
~
10
"'V
r~lcnil"el
100
1000
f, FREQUENCY (MHz)
9-224
MOTOROLA ANALOG IC DEVICE DATA
MC13282A
Figure 10. Rise Time
Figure 11. Fall Time
100 mVlDlV
5.0 nslDIV
10xPROBE
NOTE:
Recommended to use a double sided PCB without any socket for rise/fall time measurements, using an input pulse with
1.5 ns riselfall time and an active probe wfth 1.7 pF capacitance loading.
Figure 12. Single Sided PCB Layout
(Component Side)
.:.,
,
NOTE:
J = Jumper
MOTOROLA ANALOG IC DEVICE DATA
9-225
®
MOTOROLA
MC13283
Product Preview
130 MHz Video Processor
with OSD Interface
The MC13283 is a three channel wideband amplifier designed for use as
a video pre-amp in high resolution RGB color monitors.
130 MHz VIDEO
PROCESSOR WITH
OSDINTERFACE
SEMICONDUCTOR
TECHNICAL DATA
Features:
• 4.0 Vpp Output with 130 MHz Bandwidth
• 2.6 ns Rise and 3.2 ns Fall Time
• Subcontrast Control for Each Channel
• Blanking and Clamping Inputs
• Contrast Control
• OSD Interlace with 85 MHz Bandwidth
• OSD Contrast Control
• Package: NDIP-24
II
PSUFFIX
PLASTIC PACKAGE
CASE 724
(NDIP-24)
ORDERING INFORMATION
Device
MC13283P
Operating
Temperature Range
Package
TA=OOto+70°C
Plastic DIP
PIN CONNECTIONS
R Subconlrasl
Blank
R Inpul 2
Clamp
G Subcontrast 3
REmitter
G Input 4
RClamp
V5
B Subcontrast
Blnput
GEmitter
GClamp
Ground
ROSD
Vee
GOSD
OSD Contrast 11
BOSD
BEmitter
Fast Commutate
Contrast
(Top View)
9-226
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC34119
Low Power Audio Amplifier
The MC34119 is a low power audio amplifier intergrated circuit intended
(primarily) for telephone applications, such as in speakerphones. It provides
differential speaker outputs to maximize output swing at low supply voltages
(2.0 V minimum). Coupling capacitors to the speaker are not required. Open
loop gain is 80 dB, and the closed loop gain is set with two extemal resistors.
A Chip Disable pin permits powering down and/or muting the input signal.
The MC34119 is available in standard 8-pin DIP, SOIC package, and
TSSOP package.
LOW POWER
AUDIO AMPLIFIER
SEMICONDUCTOR
TECHNICAL DATA
• Wide Operating Supply Voltage Range (2.0 V to 16 V), Allows
Telephone
Line Powered Applications
• Low Quiescent Supply Current (2.7 mA Typ) for Battery
Powered Applications
• Chip Disable Input to Power Down the IC
• Low Power-Down Quiescent Current (6511A Typ)
• Drives a Wide Range of Speaker Loads (8.0 n and Up)
PSUFFIX
PLASTIC PACKAGE
CASE 626
• Output Power Exceeds 250 mW with 32 n Speaker
• Low Total Harmonic Distortion (0.5% Typ)
• Gain Adjustable from <0 dB to >46 dB for Voice Band
8~
• Requires Few Extemal Components
1
DSUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
MAXIMUM RATINGS
Rating
Supply Voltage
Maximum Output Current at VOl, V02
Maximum Voltage @ Vin, FC1, FC2, CD
Applied Output Voltage to VOl, V02 when disabled
Junction Temperature
NOTE:
Value
Unit
-1.0to +18
Vdc
±250
mA
-1.0,VCC+1.0
-1.0, VCC + 1.0
Vdc
-55,+140
°C
8~
1
DTBSUFFIX
PLASTIC PACKAGE
CASE946J
(TSSOP)
ESO data available upon request.
PIN CONNECTIONS
Block Diagram and Simplified Application
Rt
75k
-----,
6
Ci
Audio
~.t
VCC
I
Ri
3.0 k
51
Input ,/II--"""---{>-'--+---l
VOt
,---"""0-"'-+.......-1
1.0~~f2' II
5.01lF
=
(TopViaw)
2
ORDERING INFORMATION
FC2 1
I
IL _=_ _MC34119
___
• = Optional
Differential Gian = 2 x
_ _ _ _ _ .1I
7
Gnd
~:
This device contains 45 active transistors.
MOTOROLA ANALOGIC DEVICE DATA
Device
Operating
Temperature Range
MC34119P
MC34119D
MC34119DTB
Package
PlastiC DIP
TA =-20° to +70°C
S0-8
TSSOP
9-227
MC34119
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Max
Unit
VCC
VCD
+2.0
0
+16
VCC
Vdc
Vdc
Load Impedance
RL
8.0
-
n
Peak Load Current
IL
-
±200
rnA
AVO
0
46
dB
TA
-20
+70
°C
Supply Voltage
Voltage @ CD (pin 1)
Differential Gain (5.0 kHz Bandwidth)
Ambient Temperature.
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
I
I
Characteristics
Symbol
Min
Max
Unit
Mn
AMPLIFIERS (AC CHARACTERISTICS)
AC Input Resistance (@ Vln)
Open Loop Gain (Amplifier #1 , I < 100 Hz)
Closed Loop Gain (Amplifier #2, VCC = 6.0 V, I = 1.0 kHz, RL = 32 n)
Gain Bandwidth Product
Output Power;
VCC = 3.0 V, RL = 16 n, THO s 10%
VCC = 6.0 V, RL = 32 n, THO s 10%
VCC = 12 V, RL = 100 n, THO s 10%
Total Harmonic Distortion (I = 1.0 kHz)
(VCC = 6.0 V, RL = 32
Pout = 125 mW)
(VCC 30
-
80
-
-
dB
AV2
-0.35
0
+0.35
dB
GBW
-
1.5
-
MHz
POut3
POut6
POut12
55
250
400
-
-
-
1.0
-
0.5
0.5
0.6
50
-
-
-
12
52
-
GMT
-
>70
-
dB
VO(3)
VO(6)
VO(12)
1.0
1.15
2.65
5.65
1.25
Vdc
-
-
vcc-Hi
0.16
-
-30
0
+30
-
-100
-200
THO
=
Power Supply Rejection (VCC = 6.0 V, AVCC
(Cl 00, C2 0.01 J.LF)
(Cl 0.1 llF, C2 0, I 1.0 kHz)
(Cl 1.0 llF, C2 5.0 llF, I 1.0 kHz)
=
=
=
ri
AVOL1
=3.0 V)
=6.0 V, 1.0 kHz sIs 20 kHz, CD = 2.0 V)
%
PSRR
=
mW
-
dB
AMPLIFIERS (DC CHARACTERISTICS)
Output DC Level @ VOl, V02, VCC
VCC=6.0V
VCC=12V
=3.0 V, RL =16 (RI =75 k)
Output Level
High (lout = -75 rnA, 2.0 V s VCC s 16 V)
Low (lout = 75 rnA, 2.0 V s VCC s 16 V)
Vdc
VOH
VOL
Output DC Offset Vo~age (V01-V02)
(VCC 6.0 V, RI = 75 kn, RL = 32 0)
AVO
Input Bias Current @ Yin (VCC = 6.0 V)
liB
=
Equivalent Resistance
@ FCI (VCC 6.0 V)
@ FC2 (VCC 6.0 V)
=
=
-
-
mV
nA
kn
RFCI
RFC2
100
18
150
25
220
-
0.8
40
CHIP DISABLE (Pin 1)
Input Voltage
Low
High
VIL
VIH
2.0
-
Input Resistance (VCC = VCD = 16 V)
RCD
50
90
175
kn
-
2.7
3.3
65
4.0
5.0
100
rnA
mA
Vdc
-
POWER SUPPLY
Power Supply Current
(VCC = 3.0 V, RL =00, CD = 0.8 V)
(VCC= 16 V, RL = 00, CD = 0.8 V)
(VCC = 3.0 V, RL = 00, CD = 2.0 V)
ICC3
leC16
ICCD
-
ItA
NOTE: Currents into a pin are positive, currents out of a pin are negative.
9-228
MOTOROLA ANALOG Ie DEVICE DATA
MC34119
PIN FUNCTION DESCRIPTION
Symbol
Pin
Description
CD
1
Chip Disable - Digital input. A Logic "0" «0.8 V) sets normal operation. A logic "1" (~.O V) sets the power down
mode. Inpul impedance is nominally 90 kQ .
FC2
2
A capacitor at this pin increases power supply rejection, and affects turn--on time. This pin can be left open if the
capacitor at FCl is sufficient.
FCl
3
Analog ground for the amplifiers. A 1.0 j.1F capacitor at this pin (with a 5.0 j.1F capacitor at Pin 2) provides
(typically) 52 dB of power supply rejection. Tum-on time of the circuit is affected by the capacitor on this pin. This
pin can be used as an altemate input.
Vin
4
Amplifier input. The input capacitor and resistor set low frequency rolloff and input impedance. The feedback
resistor is connected to this pin and VOl'
Amplifier Output #1. The dc level is = (VCC - 0.7 V)/2.
VOl
5
VCC
6
DC supply voltage (+2.0 V to +16 V) is applied to this pin.
GND
7
Ground pin for the entire Circuit.
V02
8
Amplifier Output #2. This signal is equal in amplitude, but 180' out-of-phase with that at VOl.
The dc level is = (VCC - 0.7 V)/2.
TYPICAL TEMPERATURE PERFORMANCE (-20' C < TA < +70'C)
Function
Input Bias Current (@ Vin)
Total Harmonic Distortion
(VCC 6.0 V, RL 32 Q. Pout
=
=
=125 mW, f =1.0 kHz)
Power Supply Current
(VCC 3.0 V, RL
(VCC 3.0 V, RL
=
=
="', CD =0 V)
="', CD =2.0 V)
MOTOROLA ANALOG IC DEVICE DATA
Typical Change
Units
±40
pAioC
+0.003
%/'C
j.tA/'C
-2.5
-0.03
9-229
MC34119
DESIGN GUIDELINES
General
The MC34119 is a low power audio amplifier capable of
low voltage operation (VCC = 2.0 V minimum) such as that
encountered in line-powered speakerphones. The circuit
provides a differential output (V01-V02) to the speaker to
maximize the available voltage swing at low voltages. The
differential gain is set by two external resistors. Pins FC1 and
FC2 allow controlling the amount of power supply and noise
rejection, as well as providing alternate inputs to the
amplifiers. The CD pin permits powering down the IC for
muting purposes and to conserve power.
Amplifiers
Referring to the block diagram, the internal configuration
consists of two identical operational amplifiers. Amplifier #1
has an open loop gain of ~80 dB (at f S 100 Hz), and the
closed loop gain is set by external resistor Rf and Ri. The
amplifier is unity gain stable. and has a unity gain frequency
of approximately 1.5 MHz. In order to adequately cover the
telephone voice band (300 Hz to 3400 Hz), a maximum
closed loop gain of 46 is recommended. Amplifier #2 is
internally set to a gain of - 1.0 (0 dB).
The outputs of both amplifiers are capable of sourcing and
sinking a peak current of 200 mA. The outputs can typically
swing to within =0.4 V above ground, and to within =1.3 V
below VCC, at the maximum current. See Figures 18 and 19
for VOH and VOL curves.
The output dc offset voltage (V01-V02) is primarily a
function of the feedback resistor (Rf), and secondarily due to
the amplifiers' input offset voltages. The input offset voltage
of the two amplifiers will generally be similar for a particular
IC, and therefore nearly cancel each other at the outputs.
Amplifier #1's bias current, however, flows out of Vin (Pin 4)
and through Rf, forcing V01 to shift negative by an amount
equal to [Rf x IIBI. V02 is shifted positive an equal amount.
The output offset voltage, specified in the Electrical
Characteristics, is measured with the feedback resistor
shown in the Typical Application Circuit, and therefore takes
into account the bias current as well as internal offset
voltages of the amplifiers. The bias current is constant with
respect to VCC.
FC1 and FC2
Power supply rejection is provided by the capacitors (C1
and C2 in the Typical Application Circuit) at FC1 and FC2. C2
is somewhat dominant at low frequencies, while C1 is
dominant at high frequencies, as shown in the graphs of
Figures 4 to 7. The required values of C1 and C2 depend on
the conditions of each application. A line powered
speakerphone, for example, will require more filtering than a
circuit powered by a well regulated power supply. The
amount of rejection is a function of the capacitors, and the
equivalent impedance looking into FC1 and FC2 (listed in the
Electrical Characteristics as RFC1 and RFC2).
In addition to providing filtering, C1 and C2 also affect the
turn-on time of the circuit at power-up, since the two
capaCitors must charge up through the internal 50 k and
125 ill resistors. The graph of Figure 1 indicates the
turn-on time upon application of VCC of +6.0 V. The turn-on
time is =60% longer for VCC = 3.0 V, and =20% less for
VCC =9.0 V. Turn-off time is <10 I1s upon removal of VCC.
9-230
Figure 1. Turn-On Time versus C1, C2 at Power-On
360
l....-
300
I
.~
l....-
240 t--- t- C1 = 5.0 f.l,/- V
~ 180
~
I....-
120
60
/
-..... --
o
o
.,;'
/
~
",
C1 =1.0f.lF
1
~
4.0
2.0
VCC switching from
OVto6.0V
6.0
C2, CAPACITANCE (f.lF)
8.0
10
Chip Disable
The Chip Disable (Pin 1) can be used to power down the
IC to conserve power, or for muting, or both. When at a Logic
"0" (0 V to 0.8 V), the MC34119 is enabled for normal
operation. When Pin 1 is at a Logic "1" (2.0 V to VCC V), the
IC is disabled. If Pin 1 is open, that is equivalent to a Logic
"0," although good design practice dictates that an input
should never be left open. Input impedance at Pin 1 is a
nominal 90 kn. The power supply current (when disabled) is
shown in Figure 15.
Muting, defined as the change in differential gain from
normal operation to muted operation, is in excess of 70 dB.
The turn-off time of the audio output, from the application of
the CD signal, is <2.0 I1s, and turn on-time is 12 ms-15 ms.
Both times are independent of C1, C2, and VCC.
When the MC34119 is disabled, the voltages at FC1 and
FC2 do not change as they are powered from VCC. The
outputs, V01 and V02, change to a high impedance condition,
removing the signal from the speaker. If signals from other
sources are to be applied to the outputs (while disabled), they
must be within the range of VCC and Ground.
Power Dissipation
Figures 8 to 10 indicate the device dissipation (within the
IC) for various combinations of VCC, RL, and load power. The
maximum power which can safely be dissipated within the
MC34119 is found from the following equation:
Po
=(140°C -
TA)/SJA
where TA is the ambient temperature; and SJA is the package
thermal resistance (100°CIW for the standard DIP package,
and 180°CIW for the surface mount package.)
The power dissipated within the MC34119, in a given
application, is found from the following equation:
Po =(VCC x ICC) + (IRMS x VCC) - (RL x IRMS2)
where ICC is obtained from Figure 15; and IRMS is the RMS
current at the load; and RL is the load resistance.
Figures 8 to 10, along with Figures 11 to 13 (distortion
curves), and a peak working load current of ±200 mA, define
the operating range for the MC34119. The operating range is
further defined in terms of allowable load power in Figure 14
for loads of 8.0 n, 16 nand 32 n. The left (ascending) portion
MOTOROLA ANALOG IC DEVICE DATA
MC34119
Layout ConSiderations
of each of the three curves is defined by the power level at
which 10% distortion occurs. The center flat portion of each
curve is defined by the maximum output current capability of
the MC34119. The right (descending) portion of each curve is
defined by the maximum internal power disSipation of the IC
at 25°C. At higher ambient temperatures, the maximum load
power must be reduced according to the above equations.
Operating the device beyond the current and junction
temperature limits will degrade long term reliability.
Normally a snubber is not needed at the output of the
MC34119, unlike many other audio amplifiers. However, the
PC board layout, stray capacitances, and the manner in
which the speaker wires are configured, may dictate
otherwise. Generally, the speaker wires should be twisted
tightly, and not more than a few inches in length.
Figure 2. Amplifier #1 Open Loop Gain and Phase
100
80
-
~o
- ...
I
1 1
Phase
..........
60
108
144
........ r-.
Gain
~ 40
0
36
72
"
1.0k
10 32
ffi
:!2.
z
rJ)
-'
«
a:
~
w
~
-e=
r-.
10k
I, FREQUENCY (Hz)
100k
1.0M
t-
w
Q.
rJ)
rJ)
20
100
en
w
180 ~
.....
o
Figure 3. Differential Gain versus Frequency
36
~
24
!iw
KJ111111
Rt= 75 k, Ri = 3.0 k
~ 7'F-~""""
IL
a: 16
~
LL
15
~ -'15~ ~ 'R' ~'~ 0 ~
I-I I I' 1 .
8
o
100
o~
Input>-1
R
-#1
V01}
'~vo
~ liilill
1 ~ 1-.llW
1.0k
10k
I, FREQUENCY (Hz)
20k
II
MOTOROLA ANALOG IC DEVICE DATA
9-231
MC34119
Figure 4. Power Supply Rejection versus Frequency
(C2 .. 10 IJ,F)
C1 ~1.0IJ,F
~1.01J,F-
C1
-
Figure 5. Power Supply Rejection versus Frequency
(C2= 5.01J,F)
-
C1 =0.1 F
50
40
-
-
~;I/1~
-
30
r--
C1=O
o
200
---
1.0k
10k
20
,
-
C1 =0
10
o
2.0k
200
1.0k
t, FREQUENCY (Hz)
t, FREQUENCY (Hz)
~
Figure 6. Power Supply Rejection versus Frequency
(C2= 1.0 IJ,F)
60
_ C1=5:0IJ,F
50
~
40
~
30 I-C1 =0.1 IJ,F
ffi
20
a::
~
~-
II
~
_C11=1'1~
~
...........
~U3
a::
1/1
....
f-"'"
a::
w
20
C1 = 1.0 IJ,F
I I 1
c£
10
C1io.1L~
a::
~f1=10
-~
(J)
D-
200
1.Ok
t, FREQUENCY (Hz)
10 k
20k
~
200
.§.
~
600
I
en
I
~ 400
w
~
c
f...-
1 /'
I
200
f...III
V
o
o
--
30
VC~~
en
(J)
600
is
Vc =3.0V_
w
~
w
c
400
200
/"
1/
.§.
z
Q 800
~
~
I
/
II
I
'/
'L
/
90
120
150
.....I
~VCC=12V
/
J
/
..........
--
-
VCC=6.0V_
-
V£C=3Y
.......
60
LOAD POWER (mW)
9-232
L
3; 1000
--
20 k
Figure 9. Device DisSipation, 16 n Load
VCC=16V
/
10 k
1.Ok
1200
~\=1Jv
z
Q
--
~
t, FREQUENCY (Hz)
v
800
I-"""
......
nl
o
Figure 8. Device Dissipation, 8.0 n Load
1000
20k
=-..---
~
.- i-""'"
30
~
.............
---
!5.rilJ,~
C1
40
DD-
1il
.....
........
10k
Figure 7. Power Supply Rejection versus Frequency
(C2=0)
60
1
1
50
::::;
~
10
o
:5!.
z
~
§
1C
..............
1
100
200
300
400
LOAD POWER (mW)
MOTOROLA ,ANALOG IC D~VICE DATA
MC34119
Figure 11. Distortion versus Power
Figure 10. Device Dissipation, 32 n Load
1200
r-
~ 1000
.§.
z
0
~
1ii
:g
w
400
~
a
......
V
V
T-:-i - r-I
I
200
/
2.0
12
F
2.0
/
=3.0 kHz, AVO =34 dB)
~
~
I
I.
L Vee=6.0V.
RL=320
/
Vee =3.0 V,
RL=8.00
1
Vee = 16 V,
RL =320 Limit
Ii
RL=320
I
II
I J.
300
400
500
B.O
Vee = 3.0 V,
RL=B.OO
Vee=6.0 V,
RL=320
~
:: 4.0
~
12
I
I
2.0
F
1/
,,/
I 1/
200
I
RL=B.OO
~cc
cc
::>
n
100
I
I
I
"
......
'\.
..........
TA = 25°e-Derate at higher temperatures
2.0
4.0
6.0
8.0
10
Vee, SUPPLY VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
~
'\.
~
12
I
~~ee=\2V'
~L=3tO
'1..)
~
100
1
\
\
VCC=6.0V, RL= 160 Limit-
I"
200
300
POut, OUTPUT POWER (mW)
500
400
Figure 15. Power Supply Current
\
I
\
[
4.0
3.0
~
14
2.0
::>
--
eD=O
en
cc
w
~
D..
............
-
D..
D..
-
RL =00
U
300
\
0
a
I[
Vee = 16V,
RL =320 Limit
I
I
/
a"
\
I
I
RL= 16 0
I
a
I
Vee=3.0V."
RL= 160
~ 6.0
Vr.r. = 6.0 V, FtL=160
VJ:e_= 12 V, RL = 32 0
100
200
300
400
500
POut, OUTPUT POWER (mW)
400
a
I
Vee=12V,RL=320 _
10
Figure 14. Maximum Allowable Load Power
9
200
tn
/
500
~
V
I \
100
If
(f = 1, 3.0 kHz, AVO = 12 dB)
~
I
I
I I
II
a
a
RL=160
Figure 13. Distortion versus Power
oi/
~
cc
RL=320
'rr
oLo
SOO
400
I II
Figure 12. Distortion versus Power
6.0
--'
;'!'!:
a"
300
I I I I
I /Vee=16V,_ Vee=6.0V,_
4.0
--'
POut, OUTPUT POWER (mW)
I"
;'!'!:
I
I RL=32Q
I I I
LOAD POWER (mW)
Vee =3.0V,
RL = 160
12
r--
Vee=6.0V -
Vee=6.0 v,
Vee = 3.0 V,
RL=B.OO
\,2
100
4.0
~
B.O Vee = 3.0 V,
RL=IHl
C 6.0
10
i
~
i::i
Ii:
=1.0 kHz, AVO =34 dB)
10
z
(f
\,2
~
Vee=3.0V
/" ~
...0
-
Vee=!.~
V
LL
I
/
200
0
Vee=16V
/
(f
~
I
./
BOO
600
I
1.0
U
!:?
16
eD = Vee
o
o
2.0
4.0
6.0
B.O
10
12
14
16
Vee, SUPPLY VOLTAGE (V)
9-233
II
MC34119
Figure 16. ·Small Signal Response
Figure 17. Large Signal Response
201J,SlDIV
20~DIV
Figure 19. VOL @ V01, V02 versus Load Current
Figure 18. VCC-VOH @ V01, V02 versus Load Current
1.5
1.4
~
J:
1.2
0
1.1
~
I
~
L
..."
./
"2.0SVCCS16V -
r--
40
0.6
0
0.4
~
TA = 25°C -
./
0.8 . /
0
::>
:=::>
..::.
..."
80
120
160
200
/
./
./
0.8
I-
..."
0.9
~ 1.0
9
./
./
J
w
...J
s:
..."
1.0
0.2
./
VCC=3.0V
--r
./
--:-r
~
...-
o
o
VCC>6.0V
I
I
I
40
80
120
160
200
ILOAD. LOAD CURRENT (rnA)
ILOAD. LOAD CURRENT (rnA)
II
L
I
I • ...,
VCC=2.0V;
1.2 -TA=25°C
...J
1.3
~
1.4
Figure 20. Input Characteristics @ CD (Pin 1)
Figure 21. Audio Amplifier with High Input Impedance
200
75 k
./
160
./
~
.." V'
120
V
C
.9 80
40
o L...---"
o
0.1
Input>--l
,/'
/'
V
./
4.0
I
5.0~F21
8.0
ValidforVCDsVcC
I
'1
12
16
PI
'::'
I
IL. _ _ _MC34119
__ _
VCD. CHIP DISABLE VOLTAGE (V)
7
Differential Gain = 34 dB
Frequency Response: See Figure 3
Input Impedance = 125 kn
PSRR = 50 dB
9-234
MOTOROLA ANALO~ IC DEVICE DATA
MC34119
Figure 22. Audio Amplifier with Bass Suppression
Figure 23. Frequency Response of Figure 22
75k
36
1[32
, '"
z
i§
....J
24
~
16
~
1
5.01lF 21
1
1 -
""
i5
rl
'"
);"
ci
~
a
MC34119
I.. _ _ _ _ _
B.O
1.0k
10k
I, FREQUENCY (Hz)
100
...!
Figure 24. Audio Amplifier with Bandpass
20k
Figure 25. Frequency Response of Figure 24
l000pF
lOOk
, '"
lOOk
....
"
0.1
Input>--J
1
5.01lF 21
a
rl
'"
100
1.0k
10k
I, FREQUENCY (Hz)
1
MC34119
1I.. _
- __
_ _ ...! ____ .J
20k
II
Gnd
I
I
Figure 26. Split Supply Operation
RI75k
Ci Ri
0.1 3.0k
Audio Input >--J f---'W'v'.......-"'-C-+--l
20k
H--w\r-.~Chip
Disable
20k
NOTE: If Vee and VEE are not symmetrical about ground then Fel must be
connected through a capacnor to ground as shown on the front page.
MOTOROLA ANALOG IC DEVICE DATA
VEE
9-235
®
MOTOROLA
MC44002
MC44007
Advance Information
Chroma 4 Multistandard
,Video Processor
CHROMA 4
VIDEO PROCESSOR
The MC4400217 is a highly advanced circuit which performs most of the
basic functions required for a color TV. All of its advanced features are under
processor control via an 12C bus, enabling potentiometer controls to be
removed completely. In this way the component count may be reduced
dramatically, allowing significant cost savings together with the possibility of
implementing sophisticated automatic test routines. Using the MC44002l7,
TV manufacturers will be able to build a standard chassis for anywhere in the
world. Additional features include 4 selectable matrix modes (primarily for
NTSC), fast beam current limiting and 16:9 display.
• Operation from a Single 5.0 V Supply; Typical Current Consumption
Only 120mA
• Full PAUSECAMINTSC Capability (4 Matrix Modes)
• Dual Composite Video or S-VHS Inputs
• All ChromalLuma Channel Filtering, and Luma Delay Line Are
Integrated Using Sampled Data Filters Requiring No External
Components
• Filters Automatically Commutate with Change of Standard
• Chroma Delay Line is Realized with a 16 Pin Companion Device, the
MC44140
• RGB Drives Incorporate Contrast and Brightness Controls and Auto
Gray Scale
• Switched RGB Inputs with Separate Saturation Control
II
• Auxiliary V, R-V, B-V Inputs
• Line TImebase Featuring H-Phase Control, TIme Constant and
Switchable Phase Detector Gain
• Vertical TImebase Incorporating Vertical Geometry Corrections
•
•
•
•
•
SEMICONDUCTOR
TECHNICAL DATA
PSUFFIX
PLASTIC PACKAGE
CASE 711
PIN CONNECTIONS
ACC
Video lin
Osc Loop Filter
Video 2
12C
t
ldent
lref
Clock
Data
36
V-Ramp
35 Vee
V-Drive
Gnd
(17.7 MHz)
(14,3 MHz) Crystals
E-WDrive
16:9 Display Mode Capability
E-W Parabola Drive Incorporating Horizontal Geometry Corrections
Beam Current Monitor with Breathing Compensation
Analog Contrast Control, Allowing Fast Beam Current Limitation
MC44007 Decoders PAUNTSC Only
} R-Y Out uts
B-Y
P
IAnode
Analog Contrast
SandcasHe
System Select
SECAM Cal loop
Yl0utput
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Pin
Symbol
Value
Unit
VCC
6.0
Vdc
TA
O,to + 70
°c
Tstg
- 65 to +150
°C
Supply Voltage
35
Operating Ambient Temperature
-
Storage Temperature
-
Junction Temperature
-
TJ
+150
°C
Drive Output Sink Current
12
112
2.0
mA
20
V20
Vg
Vi
Oto+8.0
-2.0toVCC
OtoVCC
Applied Voltage Range:
Feedback
Anode Current
All Other Pins
ESD
NOTE: ESO data available upon request.
9-236
(Top View)
Vdc
9
-
ORDERING INFORMATION
Device
V
Operating
Temperature Range
MC44002P
MC44007P
Package
Plastic DIP
TA=OOto+70°C
Plastic DIP
MOTOROLA ANALOG I,C DEVICE DATA
MC44002 MC44007
MAXIMUM RATINGS (TA =25°C, unless otherwise noted.)
Rating
Pin
Symbol
Value
-
-
:±2000
:±200
Human Body Model
Machine Model
NOTE:
-
-
Unit
ESD data available upon request.
Simplified Block Diagram
R-Y
B-Y
Yl
Red
Green
Blue
II
II
~I~~
I
H Drive
s.ov
H Flyback
Pulse
s.ov
This device contains 6,245 active transistors.
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, 13 = 70 !lA, TA = 25°C, unless otherwise noted.)
Pin
Min
Typ
Max
Supply Voltage
35
4.75
5.0
5.25
V
Operating Current
35
90
120
180
mA
Reference Current, Input Voltage
3
1.0
1.3
1.6
V
Thermal Resistance, Junction-ta-Ambient
-
-
56
-
°cm
Characteristic
NOTES:
Composite Video Input Signal level = 1.0 Vpp
Black-to-White = 0.Vpp7 , Syn-to-Black = 0.3 Vpp
PAUNTSC = 75% color bars; Burst = 300 mVpp
SECAM = 75% color bars
MOTOROLA ANALOG IC DEVICE DATA
Unit
Horizontallimebase started (subaddress 00)
Vertical Breathing control set to 00; V9 = 0 V
All other analog controls set to midrange 32
Video Peaking "PI, P2, P3" bUs high
9-237
MC44002 MC44007
TEST CONDITIONS (unless otherwise noted.)
VCC=5.0V
Iref=70~
TA = 25°C
Video Composite Input = 1.0 Vpp
- Black-to-White = 0.7 Vpp
- Black-to-Sync= 0.3 Vpp
HorizontalTImebase Started (Reg. 00)
Vertical Breathing Control Set to 00
Pin9=OV
Pin 10= 5.0 V
PAUNTSC = 75% Color Bars
-Burst = 300 mVpp
SECAM = 75% Color Bars (MC44002 only)
All Analog Controls Set to Midpoint (32)
Luma Peaking at Min. (P1 - P3 = 111)
Control Bits Setup
Name
Value
V1N2
1
Function Status
Video Input 1 Selected
HEN
0
Horizontal Drive Enabled
BRIEN
1
"Brighf' Sample "On"
HGAIN1
0
Horizontal Phase Detector Gain Reduced by 3 Enabled
YXEN
0
Luma Matrix Disabled
Y1 EN
1
Luma from Filters "On"
DEN
0
RGB Inputs Enabled
XS
0
Pin 33 Crystal Enabled
TEST
1
Outputs Sampled Once/Field
FSI
0
50 Hz Field Rate
T3
1
Low Pass Filter Enabled
VD1
1
4:3 Display Mode
2xFh
0
Horizontal Drive at 1xFh
NORM
0
Horizontal Reference Divider for 17.7 MHz
HGAIN2
1
Horizontal Phase Detector Gain Reduced by 2 Enabled
INTSEL
1
Long Vertical Time Constant
Y2EN
0
External Luma Input "Off'
SSD
0
SECAM Mode Select Enabled
CALKIL
1
Horizontal Calibration Loop Enabled
BAI
1
Vertical Blanking for 625 Lines
S-VHS
1
Composite Video Input
9-238
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
ELECTRJCAL CHARACTERISTICS
Symbol
Pin
Min
Typ
Max
Unit
Maximum Output Low Voltage
Isink = 1.0 rnA, Device in "Read" Mode
VOL(max)
5
-
0.7
-
V
Maximum Sink Current
VOL = 0.7 V, Device in "Read" Mode
Isink(max)
5
-
1.0
-
mA
Minimum Input High Voltage
VIH(min)
5
-
3.0
-
V
VIL(max)
5
-
1.5
-
V
tr(max)
4,5
-
1.0
-
IJ.S
fSCL
4
-
-
100
kHz
Free-Running Frequency (Calibration Mode)
17.734475 MHz Crystal. "NORM" Bit = 0;
"H EN" Bit = 1 (Horizontal Drive Disabled)
14.31818 MHz Crystal. "NORM" Bit = 1;
"H EN" Bit = 1 (Horizontal Drive Disabled)
-
31
15.39
15.625
15.85
15.42
15.75
15.98
H-Loop 1 (Pin 15 Current Forced to ± 20 1lA)
Minimum Frequency
Maximum Frequency
Frequency Range
-
13.85
16.05
-
14.25
16.55
2.3
14.65
17.05
VCO Control Gain
-
12,15
1.9
2.4
2.9
kHzIV
Phase Detector Gain
"HGAIN1" Bit = 1; "HGAIN2" Bit = 0
-
15
18
27
39
11A1I1S
Phase Detector Gain Reduction Factor
"HGAIN1" Bit Switched from 1 to 0
"HGAIN2" Bit Switched from 0 to 1
-
15
2.5
1.75
3.0
2.0
3.5
2.25
Parameter
BUS REQUIREMENTS
Maximum Input Low Voltage
Maximum Rise Time
Between VIH and VIL Levels
SCL Clock Frequency
HORIZONTAL TIMEBASE
kHz
12
kHz
-
-
-
12
-
0.25
0.5
V
Horizontal Drive Pulse Low
Defined by Internal Counter, Deflection Transistor
"Off', Period is 64 IJ.S
-
12
-
27
-
I1s
Horizontal Flyback Input Resistance
V13=2.0V
-
13
-
50
-
kO
-
13
-
5.7
-0.5
-
-
Line Drive Output Saturation Voltage
112=1.0mA
Horizontal Flyback Clamping Voltages
113 = 500 IlA
113 = -50 IlA
V
Horizontal Flyback Threshold Current
Should be Externally Limited to 500 IlA Peak by an
External Resistor
-
13
30
-
-
IlA
Horizontal Phase Control Range
Flyback Duration: 121J.S
-
12
8.0
-
12
IJ.S
External Delay Compensation
From Horizontal Drive to Center of Flyback Pulse.
Flyback Duration: 12 IJ.S
-
12,13
6.0
-
18
IJ.S
1.15
1.55
1.95
1.33
1.75
2.18
1.5
1.95
2.4
0.75
0.85
1.0
VERTICAL TIMEBASE (All Values are Related to Pin 3 Reference Current)
Vertical Drive Amplitude (4:3 Display)
(00)
(32)
(63)
C6 = 82 nF, Assuming Zero Tolerance
Capacitance, "VOl" Set to "1"
Vertical Drive Amplitude Control Range (4:3 Display)
C6 = 82 nF, Assuming Zero Tolerance Capacitance,
"VOl" Set to "1", Vertical Amplitude Varied from
(00) to (63)
MOTOROLA ANALOG IC DEVICE DATA
-
-
7
7
V
V
9-239
II
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
I
Parameter.
I
Symbol
Pin
Min
Typ
Max
Unit
VERTICAL TIMEBASE (All Values are Related to Pin 3 Reference Current)
Ramp Amplitude Ratio Between 4:3 and 16:9 Display
Modes
Vertical Amplitude = (32)
-
7
0.7
0.8
0.9
-
Maximum Ramp Amplitude Change With 5251625
Mode Change
-
7
-
2.0
-
%
Vertical Ramp Low Voltage (4:3 Display)
Pin 6 Voltage Set to 0 V, ''VDI" Set to "1", Vertical
Position = (00)
-
7
-
0.65
-
V
Vertical Ramp Low Voltage (16:9 Display)
Pin 6 Voltage Set to 0 V, ''VDI" Set to "0", Vertical
Position = (00), Measured After 16:9 Holding
Period
-
7
-
0.85
-
V
Vertical Ramp High Voltage
Pin 6 Open, "VOl" Set to "0" or "1", Vertical
Position = (63)
-
7
-
4.15
-
V
Vertical Ramp Position Control Range
Versus Vertical Ramp Voltage at Vertical Position
(32). Measured at Vm , "VOl" Set to "0" or "1",
Vertical Position Varied from (00) to (63)
-
7
±D.5
±D.75
±1.0
V
-
7
-
512
-
115
Maximum Output Source Current
-
7
1.0
-
-
mA
Maximum Output Sink Current
-
7
200
-
-
IlA
Vertical Linearity
(00)
(63)
-
7
-
0.8
1.1
-
Change in Ramp current as Pin 9 Current Varied from
to 6.41lA
Vertical Breathing Correction = (63)
Vertical Breathing Correction = (00)
-
GainV7N6
-
Vertical Ramp Clamping Duration (tel
Defined by Intemal Counter
o
-
-
IlA
6
0.15
6,7
0.75
0
1.3
0.9
0.95
1.0
0
150
0.2
300
20
0
100
0.2
250
10
0
10
-
0.2
-150
-
1.9
-1.9
1.0
-
-
VN
E-W CORRECTION (V6(b) = 0.2 V, V6(m) = 1.1 V, V6(e) = 2.0 V)
Horizontal Amplitude
(00)
(63)
Corner Correction = (00), Tilt = (32), Parabola
Amplitude = (00), Measured at Tm.
-
Parabola Amplitude
(00)
(63)
Corner Correction = (00), Horizontal Amplitude =
(32), Tilt = (32), Measured at Tb, T m and Te .
-
Corner Correction
(00)
(63)
HOrizontal Amplitude = (63), Parabola Amplitude =
(00). Tilt = (32), Measured at Tb, Tm and Te.
-
Parabola Tilt
(00)
(63)
Corner Correction = (00). Horizontal Amplitude =
(32), Parabola Amplitude = (32), Measured at Tb,
Tm and Te.
-
E-W Drive Output Voltage
-
9-240
IlA
8
-
IlA
8
-
8
8
8
J.lA
-30
-
-
-
VCC
V
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
I
Parameter
E-W CORRECTION (V6(b)
I
Symbol
Pin
Min
Typ
Max
Unit
-1.0
-
1.0
-2.0
-
1.0
100
-
-
160
-
-
36
68
-
448
-
740
Half
Lines
=0.2 V, V6(m) =1.1 V, V6(e) =2.0 V)
E-W DACs Differential Non-Linearity Error
At Minor Transitions: Steps 0-1: 1-2; 3-4; 7-8;
15-16.
At Major Transition: Step 31-32
-
8
LSB
SYNC SEPARATOR
Sync Amplitude to Operate the Device
From Black to Sync, Black Picture, Standard Timing
Specifications on Sync Signal
-
Vertical Sync Separator Delay Time: td
"INTSEL"= 0
"INTSEL" = 1
From Vertical Sync Pulse to Vertical Ramp Reset
-
Vertical Sync Window
-
2,40
22,23,
24,25
2,40
2,40,
22,23,
24,25
mV
liS
COMPOSITE VIDEO PROCESSING (All measurements in NORMAL mode, unless otherwise noted.)
Composite Video Input Amplitude
Load Impedance 75 Q, Less than 5% Distortion
-
2,40
0.7
1.0
1.4
Vpp
Video lNideo 2 Input Crosstalk
@ f = (2.0 MHz), Measured on Yl Output
-
29
-
-
-40
dB
Variable Input LPF Cut-Off Frequency
17.7 MHz Crystal Selected
14.3 MHz Crystal Selected
-
29
-
6.0
4.85
-
Chroma Subcarrier Rejection
PAL 4.43 MHz (17.7 MHz Crystal Selected)
NTSC 3.58 MHz (14.3 MHz Crystal Selected)
SECAM (FoR and FoB) (17.7 MHz Crystal Selected)
-
25
25
18
30
-
20
-
Yl Output Resistance
-
29
-
-
300
Yl Bandwidth (-3.0 dB)
PAL
Minimum Peaking, "T3" Set to 1 (Input LPF "On")
SECAM
Minimum Peaking, "T3" Set to 0 (Input LPF "011")
-
29
2.5
3.0
-
2.5
3.0
-
Luma Peaking Range
Measured at 3.0 MHz, 17.7 MHz Crystal Selected
-
29
6.0
8.5
-
dB
MHz
29
dB
30
Q
MHz
Luma Gain (@ 100 kHz)
-
2,40,29
0.9
1.1
1.3
VN
Overshoot
Peaking at Step 3 (100)
-
29
-
5.0
-
%
0
-
1.5
kQ
-
280
350
-
Source Impedance
-
2,40
Luma Delay Range
PAVSECAM (17.7 MHz Crystal Selected)
NTSC 3.58 (14.3 MHz Crystal Selected)
-
29
Video In to Luma Out Delay Difference Between PAL
and SECAM (MC44002 only)
Luma Delay Minimum: (01 02 03) = (0 0 D), Green
to Magenta Transition, ''T3" Set to 1 in PAL, to 0 in
SECAM
-
29,40
-
260
-
ns
Chroma Output Variation
For a Burst Input Varied from 60 mV to 600 mV
-
36,37
-
-
3.0
dB
Color Kill Attenuation
Referred to Standard Color Video Input,
Monochrome Mode Selected
-
36,37
40
-
-
dB
ns
PAUNTSC DECODER
MOTOROLA ANALOG IC DEVICE DATA
9-241
II
MC44002MC44007
ELECTRICAL CHARACTERISTICS (continued)
I
I
Symbol
Pin
Min
Typ
Max
Unit
Color Difference Output Distortion
@ 1.5 V Output Signal
-
36,37
-
-
5.0
%
Residual Chroma Subcarrier Rejection
PAL
NTSC
Referred to Video Input
-
36,37
40
40
-
-
-
-
Parameter
PAUNTSC DECODER
Oscillator Pull-ln Range
PAL
NTSC
Referred to Nominal Subcarrier Frequency, with
Ideal Xtal
-
dB
32,33
±350
±400
-
Hz
-
-
36,37
30
-
-
dB
-
36,37
-
1.3
-
VN
-
36,37
-2.0
-
2.0
dB
-
2,40
-
10
20
Minimum Burst Level for "PAL IdentHied" Flag "On"
Standard Set to PAL or NTSC, Increasing Burst
Level Steps
-
2,40
-
5.0
20
mVpp
Maximum Burst Level for "ACC Active" Flag "Off"
Standard Set to PAL or NTSC, Decreasing Burst
Level Steps
-
2,40
-
5.0
-
mVpp
-
2,40
-
1.0
-
mVpp
-
36
0.7
1.1
1.5
V
-
36,37
±20
-
-
Oeg
-
29,36
-
80
100
-
75
1.65.
3.0
4.0
400
1.9
3.25
4.3
mV
V
V
V
-
4.0
2.95
1.55
75
4.3
3.15
1.8
V
V
V
mV
5.0
4.0
6.0
5.0
7.0
6.0
R-Y, B-Y Channel Separation
B-Y/R-Y Amplitude Ratio
At Standard Color Bars Signal
B-Y/R-Y Amplitude Ratio Spread
At Standard Color Bars Signal
Minimum Burst Level for "ACC Active" Flag "On"
Standard Set to PAL or NTSC, Increasing Burst
Level Steps
Maximum Burst Level for "PAL Identified" Flag "Off'
Standard Set to PAL or NTSC, Decreasing Burst
Level Steps
(B-Y) Color Difference Output Levels
Relative to 75% Color Bars
Hue DAC Control Range
Hue Control Register Varying from (00) to (63)
Chroma to Luma Delay
PAL
NTSC
Measured on (B-Y) Output, Luma Delay Set to
Minimum: (01 02 03) = (0 0 0), Green to Magenta
Transition, ''T3'' Set to 1
.'
mVpp
ns
-
DELAY LINE CONTROL SIGNALS
System Select
PAL
NTSC
SECAM (MC44002 only)
EXTERNAL
Sandcastle
Levell
Level 2
Level 3
Level 4
See Figure 4
Sandcastle
tl
t2
See Figure 4, Values Defined by Internal Counter
9-242
-
30
1.4
2.75
3.7
-
31
3.7
2.75
1..3
-
-
31
itS
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
I
Parameter
I
Symbol
Pin
Min
Typ
Max
Unit
S-VHS VIDEO PROCESSING (S-VHS Set to 0, "T3" Set to 0)
Yl Bandwidth
Luma Peaking Set to Minimum
-
29
3.2
3.5
-
MHz
Minimum Burst Level for "ACC Active" Flag "On"
Standard Set to PAL or NTSC, Increasing Burst
Level Steps
-
2,40
-
10
20
mVpp
Minimum Burst Level for "PAL Identified" Flag "On"
Standard Set to PAL or NTSC, Increasing Burst
Level Steps
-
2,40
-
5.0
20
mVpp
Maximum Burst Level for "ACC Active" Flag "Off"
Standard Set to PAL or NTSC, Decreasing Burst
Level Steps
-
2,40
-
5.0
-
mVpp
Maximum Burst Level for "PAL Identified" Flag "Off'
Standard Set to PAL or NTSC, Decreasing Burst
Level Steps
-
2,40
-
1.0
-
mVpp
Video In to Luma Out Delay Difference Between
S-VHS and Normal Mode
Luma Delay Minimum in Normal Mode, Set to Step
6 in S-VHS Mode, Green to Magenta Transition,
"T3" Set to 1 in Normal Mode, to 0 in S-VHS Mode
-
2,40,29
-
310
-
ns
Chroma to Luma Delay Difference Between S-VHS
and Normal Mode
Measured on (B-Y) Output, Luma Delay Minimum
in Normal Mode, Set to Step 6 in S-VHS Mode,
Green to Magenta Transition, "T3" Set to 1 in
Normal Mode, to 0 in S-VHS Mode
-
29,36,
2,40
-
60
-
ns
Minimum Subcarrier Level for "SECAM Identified"
Flag
Measured at foR
-
2,40
-
10
20
mVpp
Color Kill Attenuation
Monochrome Mode Selected Referred to Color
Difference Output Signal with SECAM Selected
and Identified
-
36,37
40
50
-
dB
Color Difference Zero Level Error
Relative to 75% Color Bars, Difference Between
Signal Measured at tl and Active Black Level
(Black Bar)
-
36,37
-
±1.0
±3.0
%
Color Difference Output Distortion
Subcarrier Level at foR = 20-400 mV @ 1.5 V
Output Signal
-
36,37
-
-
5.0
%
Transient Response
(B-Y)
(R-Y)
Generator Rise Time - 600 ns (B-Y), Green to
Magenta TranSition, Measured Between 10% and
90% Levels
36
37
-
650
750
800
900
B-Y/R-Y Amplitude
Ratio
Ratio Spread
Relative to 75% Color Bars
-
Residual Carrier and Harmonics (4.0 to 13.5 MHz)
At Standard Color Bars Signal
-
(B-Y) Color Difference Output Levels
Relative to 75% Color Bars
PAUSECAM Color Difference Ratio
Nominal Input Signals
SECAM DECODER (MC44002 ONLY)
MOTOROLA ANALOG IC DEVICE DATA
ns
36,37
-
1.3
-
-2.0
-
2.0
VN
dB
36,37
-
-
1.0
%
-
36
-
1.1
-
V
-
36
0.8
1.0
1.2
9-243
II
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
I
I
Parameter
Symbol
Pin
Min
Typ
Max
Unit
-
29,36
-
420
-
ns
-
36
-
-
5.0
%
-
29
-
-
1.5
%
-
29,36
-
340
-
ns
500
700
1000
mVpp
-
0.5
SECAM DECODER (MC44002 ONLY)
Chroma to Luma Delay
Luma Delay Set to Minimum: (01 02 03) = (00 0),
Green to Magenta Transition, ''T3" Set tei 0
Patteming
Full Screen 75% Color Frequency, 500 kHz Low
Pass Finer, Relative to Black to Color Output Signal
Line to Line Luma Levels Difference
Full Screen 75% Yellow Color Frequency, Relative
to Black to Yellow Output Signal
Chroma to Luma Delay Difference Between PAL and
SECAM
Measured on (B-Y) Output, Luma Delay Set to
Minimum: (01 02 03) = (0 0 0), Green to Magenta
Transition, ''T3" Set to 0 in SECAM, to 1 in PAl
COLOR DIFFERENCE STAGES
II
RGB Input Amplttude
Black to Peak (Less than 5% Distortion at RGB
Outputs)
-
Fast Commutate
Low Level
High Level
-
1.0
-
Y2 Input Amplitude
(Less than 5% Distortion at RGB Outputs)
-
25
0.7
1.0
1.4
Vpp
Color Difference Input Amplitude
(Less than 5% Distortion at RGB Outputs)
-
26,27
-
-
1.8
Vpp
Y21Y1 Crosstalk
Measured at RGB Outputs, Measured at f
-
25,29
-
--40
-30
dB
RGB to Y Crosstalk
Measured at RGB Outputs, M~red at f = (2.0 MHz)
-
22,23,
24,25,
29
-
--40
-30
dB
RGB Transconductance Bandwidth (@ -1.0 dB)
-
24,17,
23,18,
22,19
6.5
-
-
MHz
Gain Reduction in ACL Mode
Pin 10 Voltage Varying from 0 to 5.0 v
-
10,17,
18,19
-
12.5
-
dB
Gain Reduction Sensitivity in ACL Mode
Pin 10 Voltage Varying from 2.0 to 2.5 V
-
10,17,
18,19
-
20
-
dBN
Demodulation Angles and Amplttudes
Mode A
Rm
Ra
Gm
Ga
ModeB
Rm
Ra
Gm
Ga
ModeC
Rm
Ra
Gm
Ga
Mode 0
Rm
Ra
Gm
Ga
Definitions: RmlGm Module, RalGa = Argument
-
-
-
0.562
90
0.344
237
0.9
100
0.3
236
0.9
106
0.3
240
0.91
106
0.31
246
=
9--244
=(2.0 MHz)
22,23,
24
21
V
-
-
-
-
-
-
Deg
-
-
-
-
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
ELECTRICAL CHARACTERISTICS (continued)
I
Parameter
I
Symbol
Pin
-
17,18,
19
Min
Typ
Max
-
-
3.15
3.15
3.15
3.95
3.95
3.95
-
-
-
-
Unit
RGB OUTPUT STAGES
Low Dark Sample Output Current
Red
Green
Blue
Dark Sample Cathode Current 5.0 to 15 !lA, DC
DAC Set to Full Scale, See Figure 1
-
High Dark Sample Output Current
Red
Green
Blue
Dark Sample Cathode Current 5.0 to 15 !lA, DC
DAC Set to Zero, See Figure 1
17,18,
19
mA
-
-
mA
-
-
17,18,
19
6.0
-
-
rnA
Maximum Y to RGB Output Transconductance
Gain DAC Set to Full Scale
-
17,18,
19
6.0
7.0
B.O
mAN
Brightness
-
-
-
30
-20
-
Blanking Output Current
(00)
(63)
Wrt Dark Sample Cathode Voltage,
V
High Voltage Output Stage Transimpedance
39 kn, Dark Sample Cathode Current 15 !lA, Dark
Sample Cathode Voltage 140 V
-
20
15
20
-
Bright to Dark Sample Current Ratio
-
20
8.0
9.5
11
Leakage Loop
Sink Current
Source Current
-
20
20
5.0
-
-
0.9
-1.3
1.0
-1.2
1.1
-1.1
6.5
6.B
7.1
RGB Dark Sample Current Intensity Range
RGB Intensity DACs Varying from (00) to (63)
-
Average Beam Current Detection Level
Excess Flag
Overload Flag
!1AI!lA
!lA
9
-
Peak Beam Current Detection Level
-
dB
20
V
V
Figure 1. Example of Output Circuitry
Vp
RFDBK
Rp
Pins 17, 18, 19
>-_....._.
MC44002I7P
Vref
+
Picture Tube
Cathode
vp' Vref, RFDBK and Rp values will determine the exact operating point.
For example, let us take:
Vp = 5.0 V
RFDBK = 39 kG
Vref= 3.6 V
Rp= 6.8 kG
The formula giving the Dark Cathode Voltage with above circuit is:
Vdk = Vref + RFDBK"(Vref - Vp + 10dk"Rp) I Rp
With above application, component values and lodk specifications, all 3 cathodes on all devices will always have a range of at least 120 V to 150 V.
By changing the values of Vp ' V,ef and Rp' the cathode voltage range may be shifted up or down as required.
MOTOROLA ANALOG IC DEVICE DATA
9-245
II
MC44002 MC44007·
Figure 2. Vertical Waveforms
I~
I
18.4 ms
1.6ms
I
Video Signal
Vertical Ramp Waveform
Parabola Waveform
II
Figure 3. Vertical Ramp Positions (V7 versus V6)
Pin 7 Voltage (V)
4
3
2
(XX) = Values of (80) Register
V Ramp Low Voltage
Pin 6 Vottage (V)
2
9-246
3
4
MOTOROLA ANALOG Ie DEVICE DATA
MC44002 MC44007
Definitions
(ib + ie) .
Parabola Amplitude = --2--lm
Vertical Amplitude = Ve - Vb
.
(ie-i b)
Parabola Tilt = Parabola Amplitude
Vertical Linearity =
(V -V )
ve vm
m- b
Horizontal Amplitude = im
Corner correction is calculated in the same way as Parabola Amplitude.
Figure 4. Sandcastle Output (Pin 31)
2
I
I
I
I
I
I
I
1_11-1
n
I
I
I
12
H
4
I
I
1
1
I..
1
1
641JS
II
GENERAL DESCRIPTION OF THE CHROMA 4 SYSTEM
Figure 5 shows a simplified block diagram representation
of the basic system using the MC4400217 and its companion
device the MC44140 chroma delay line. The MC4400217 has
been designed to carry out all the processing of video
signals, display controls and timebase functions. There are
two video inputs which can be used for normal composite
video or separate Y and C inputs. In either case, the inputs
are interchangeable and selection is made via the 12C bus.
The video is decoded within the MC4400217 and involves
MOTOROLA ANALOG IC DEVICE DATA
separation, filtering, delay of the luminance part of the signal
and demodulation of the chroma into color difference signals.
The luminance (called Y1) together with the demodulated
R-Y and B-Y are all then brought out from the IC. The color
difference signals then enter the MC44140 which performs
color correction in PAL and the delay line function in SECAM.
Corrected color difference signals then re-enter the
MC44002l7.
9-247
MC44002 MC44007
Figure 5. Connection to TV Chassis
H.T.
5.0V
. . -t." "
or
S·VHS
Video 2
<>-1
EHT
Focus
H-Flyback
<>-1
Yl0ut
R·YOut
ExtR·Y
ExtB·Y
H·Sean
Coils
B·YOut
0-1
~
:;
....
0-1
Analog
Contrast
R·Yln
<.>
::;;;
Linearity
B-Yln
T
E·W
Amplifier ':'
MC4400217
26V
V·Drive
EHT
R-OIP
Fast Commutate
0----1
G-Q/P
II
17.7 MHz
14.3 MHz
B-Q/P
Feedback
?~
I"'-Bus
Clock
Data
OV
The next stage is caUed the color difference stage where a
number of control functions are carried out together with
matrixing of the components to derive RGB signals. At this
point a number of auxiliary signals may also be switched in,
again all under MCU control. External RGB (text) and Fast
Commutate enter here; also an external luminance (Y2) may
be used instead of Yl. External R-Y and B·Y are switched in
via the delay line circuit to save pins on the main device. The
Y2 and External R-Y, B-Y will obviously be of considerable
benefit from the system point of view for use with external
decoders.
The final stage of video processing is the RGB outputs which
drive the high voltage amplifiers connected to the tube
cathodes. These outputs are controlled by a sophisticated
digital servo-loop which is maintained and stabilized by a
sequentially sampled beam current feedback system.
Automatic gray scale control is featured as a part of this system.
Both horizontal and vertical timebases are incorporated
into the MC44002J7 and control is via the 12C bus. The
9-248
horizontal timebase employs a dual loop system of a PLL and
variable phase shifter, and the vertical uses a countdown
system. For the vertical, a field rate sawtooth is available
which is used to drive an external power amplifier with
flyback generator (usually a single IC). The line output
consists of a pulse which drives a conventional line output
stage in the normal way. The line flyback pulse is sensed and
used by the second loop for horizontal phase shift.
Where E-W correction is required, a parabola waveform is
available for this which, with the addition of a power amplifier,
can be used with a diode modulator type line output stage for
dynamic width and E-W control. The bottom of the EHT
overwinding is returned to the MC44002J7 and is used for
anode current monitoring.
Fast beam current limitation is also made possible by the
use of an analog contrast control.
A much more detailed description of each stage of the
MC44002J7 will be found in the next section. Information on
the delay line is to be found in its own data sheet.
MOTOROLA ANALOG
IC DEVICE DATA
MC44002 MC44007
Introduction
The following information describes the basic operation of
the MC4400217 IC together with the MC44140 chroma delay
line. The MC4400217 is a highly advanced circuit which
performs all the video processing, timebase and display
functions needed for a modern color TV. The device employs
analog circuitry but with the difference that all its advanced
features are under processor control, enabling external
filtering and potentiometer adjustments to be removed
completely. Sophisticated feedback control techniques have
been used throughout the design to ensure stable operating
conditions and the absence of drift with age.
The IC described herein is one of a new generation of TV
circuits, which make use of a serial data bus to carry out
control functions. Its revolutionary design concept permits a
level of integration and degree of flexibility never achieved
before. The MC4400217 consists of a single bipolar VlSI chip
which uses a high density, high frequency, low voltage
process called MOSAIC 1.5. Contained within this single 40
pin package is all the circuitry needed for the video signal
processing, horizontal and vertical timebases and CRT
display control for today's color TV. Furthermore, all the user
controls and manufacturer's set-up adjustments are under
the control of the processor 12C bus, eliminating the need for
potentiometer controls. The MC4400217 offers an enormous
variety of different options configurable in software, to cater
to virtually any video standard or circumstance commonly
met. The decoder section offers full multistandard capability,
able to handle PAL, SECAM (MC44002 only) and NTSC
standards with 4 matrix modes available. Practically all the
filtering is carried out onboard the IC by means of sampled
data filters, and requires no external components or
adjustment.
Digital Interface
One of the most important features of MC4400217 is the
use of processor control to replace external potentiometer
and filter adjustments. Great flexibility is possible using
processor control, as each user can configure the software to
suit their individual application. The circuit operates on a
bidirectional serial data bus, based on the well known 12C
bus. This system is rapidly becoming a world standard for the
control of consumer equipment.
12C Bus
It is not within the scope of this data sheet to describe in
detail the functioning of the 12C bus. Basically, the 12C bus is
a two-wire bidirectional system conSisting of a clock and a
serial data stream. The write cycle consists of 3 bytes of data
and 3 acknowledge bits. The first byte is the Chip Address,
the second the Sub-address to identify the location in the
memory, and the third byte is the data. When the address'
ReadlWrite bit is high, the second and third bytes are used to
transmit status flags back to the MCU.
Figure 6 shows a block diagram of the MC4400217 Bus
Interface/Decoder. To begin with, the start bit is recognized
by means of the data going low during ClK high. This causes
the Counter and all the latches to be reset. For a write
operation, the Write address ($88) is read into the Shift
Register. If the correct address is identified, the Chip Address
latch is set and at ClK 9 an acknowledge is sent.
The second byte is now read into the Shift Register and is
used to select the Sub-address. At ClK 18 a Sub-address
Enable is sent to the memory to allow the Data in the register
to be changed. Also, at ClK 18 another acknowledge is sent.
The third byte is now read into the Shift Register and the
Data bussed into the memory. The Data in the Sub-address
location already selected is then altered. A third acknowledge
is sent at ClK 27 to complete the cycle.
A Read address ($89) indicates that the MCU wants to
read the MC4400217 status flags. In this instance, the
ReadlWrite latch is set, causing the Memory Enable and
Subaddress Enable to be inhibited, and the flags to be written
onto the data line. Two of the status flags are permanently
wired one-high and one-low (O.K. and Fault), to provide a
check on the communication medium between the
MC4400217 and the MCU.
At start-up the Counter is automatically reset and the Data
for each Sub-address is read in from the MCU. Only after the
entire memory contents have been transmitted, is Data 00
sent to register 00 to start the Horizontal Drive.
The MC4400217 needs the full 27 clock cycles, or a stop
condition, to properly release the 12C bus.
Figure 6. 12C Bus Interface and Decoder
Reset
4
Clock
ReadlWrite
Latch
Data
Chip·Address
Latch
Memory &
Sub·Address
Decoding
MOTOROLA ANALOG IC DEVICE DATA
9-249
9
MC44002 .MC44007
Figure 7. MC44002/7 Memory Map
Bits 6,7
Bits 6,7
~~
~u;>
:g~
:g.:
C.$
.g "5
!
.~
l~
liP
rt,
:I
rna:
.. <=
::IiC
ii
------~:g
i~~-
-------
r:-o>
-------
:g
rn£
l.~
~l
~1ii
::!!~
~~
~!f
r:-g>
-------
Memory
Figure 7 shows a diagram of the MC4400217 Memory
Map. It has 18 bytes of memory which are located at hex
sub-addresses 77 to 88. Sub-address 77 is used to set up the
vertical timebase mode of the IC and for S-VHS switching,
and consists of 8 separate data bits. The remaining 17 bytes
use the least significant 6-bits as an analog control register.
The contents of each are D/A converted, providing an analog
control current which is distributed to the appropriate part of
the circuit. Bits 6 and 7 are used singularly for switching
control functions.
Chroma Decoder
The mairi function of this section is to decode the incoming
composite video, which may be in any of the PAL, NTSC or
SECAM (MC44002 only) Standards, and to retrieve the
luminance and color difference Signals. In addition, the signal
filtering and luma delay line functions are carried out in this
section by means of sampled data filters.
The entire decoder section operates in sampled data
mode using clocks generated by external crystals. The
oscillator, which is phase-locked in the usual way for
PAUNTSC modes, provides the clock function for the whole
circuit. The crystals are selected by the MCU by means of a
control bit (XS). Only crystals appropriate to the standards
which are going to be received need to be fifted. A 17.7 MHz
crystal (4x PAL subcarrier) is used for PAL and SECAM
systems (50 Hz, 625 lines); and 14.3 MHz (4x NTSC
subcarrier) for the NTSC system (60 Hz, 525 lines). Nearly all
the filters, together with the luma delay line and peaking,
have been integrated, requiring no external components or
any adjustment. The filter characteristics are entirely
determined by the clocks and by capacitor ratios, and are
thus completely independent of variations in the
manufacturing process. The PAUNTSC subcarrier PLL and
ACC loop filters have not been integrated in order to facilitate
testing. These filters consist of fixed external components.
Figure 8 is a block diagram of the main features of the
chroma decoder. Selection is first made between the Video 1
and Video 2 inputs. These may be either normal composite
video or separate luma and chroma which may enter the IC at
either pin. Commands from the MCU are used to route the
signals through the appropriate delay and filter sections.
9-250
In PAUNTSC, a variable low pass filter, which can be
software bypassed (control bit T3), is then used to
compensate for IF filtering and the Q of the external sound
traps. Filter response is controlled by means of control bits
T1 and T2. It is not recommended to use this filter in SECAM
or in S-VHS, as luma-chroma delays will not be optimized.
Next, the video enters the luma path. The PAUNTSC or
SECAM chroma signals are separated out by transversal
high pass filters. In SECAM mode, the chroma trap frequency
is dynamically steered to follow the instantaneous frequency
of the chroma.
Then, another transversal filter provides luma peaking,
which is also active in S-VHS mode. The high frequency
luma may be peaked (at about 3.0 MHz with the 17.7 MHz
crystal, and 2.4 MHz with the 14.3 MHz crystal) in 7 steps up
to a maximum of 8.5 dB, by a control word from the MCU.
Another control word is used to trim the delay in the luma
channel. Five steps of 56 ns (70 ns with the 14.3 MHz crystal)
are pOSSible, giving a total programmable delay of 280 ns.
Steps 6 and 7 are used in S-VHS mode. The resulting
processed luma signal then proceeds to the color difference
section aiter being low-pass filtered by an active filter to
remove components of the crystal frequency, and twice that
frequency. The luma component (Y1) is made available at
Pin 29 for use with auxiliary external functions, as well as
testing.
When in the S-VHS mode, the S-VHS control bit controls
the signal paths. The luma signal bypasses the first section of
the luma channel, which contains the chroma trap. The
S-VHS chroma is passed directly to the PAUNTSC decoder
without further filtering.
As all the delay and filter responses are determined by the
crystal, they automatically commute to the new standard
when the crystal is changed over. Thus, when the 14.3 MHz
(flock is being used, the chroma trap moves to 3.58 MHz.
The filtered PAUNTSC and SECAM chroma signals are
decoded by their respective circuits. The PAUNTSC decoder
employs a conventional design, using ACC action for gain
control and the common double balanced multipliers to
retrieve the color difference signals. The SECAM decoder is
discussed in a separate subsection.
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
Figure 8. Chroma Decoder
~2
Th~
Difference
Stage
4.41B.BMHz
Crystal
Select
NOTES: SECAM decoding
available in the MC44002 only.
The actual decision as to a signal's identity is made by the
MCU based on data provided by 3 flags returned to it,
namely: ACC Active, PAL Identified, and SECAM Identified.
Control bits SSA-SSD must be sent to set the decoder to
the correct standard.
This allows a maximum of flexibility, since the software
may be written to accommodate many different sets of
circumstances. For example, channel information could be
taken into account if certain channels always carry signals in
the same standard. Alternatively, if one standard is never
going to be received, the software can be adapted to this
circumstance. If none of the flags are on, color killing can be
implemented by the MCU. This occurs if the net Ident Signal
is too low, or if the ACC circuit is inactive due to too Iowa
signal level.
The demodulated color difference signals now enter the
Hue control section, where selection is made between
PAUNTSC and SECAM outputs. The Hue control is simply
realized by altering the amplitudes of both color difference
signals together. Hue control is only a requirement in NTSC
mode and would not normally be used for other standards.
The function is usually carried out prior to demodulation of
the chroma by shifting the phase of the subcarrier reference,
causing decoding to take place along different axes. In the
MC44002/7, Hue control is performed on the already
demodulated color difference signals. A proportion of the R-Y
signal is added 9r subtracted to the B-Y signal and
vice-versa. This has the same effect as altering the reference
phase. If desired, the MC4400217 can apply the Hue control
to simple PAL signals.
After manipulation by the Saturation and Hue controls, the
color difference signals are finally filtered to reduce any
remaining subcarrier and multiplier products. Before leaving
the chip at Pins 36 and 37, the signals are blanked during line
MOTOROLA ANALOG IC DEVICE DATA
f-:L
SECAM
Cal
= loop
and frame intervals. The 64 j..ls chroma delay line is carried
out by a companion device, the MC44140.
SECAM Decoder (MC44002 only)
The SECAM signal from the high-pass filter enters tightly
controlled AGC amplifiers wrapped around a cloche filter
which is a sampled recursive type, with the AGC derived from
a Signal squarer. Next, the Signal is blanked during the
calibration gate period and a reference 4.43 MHz is inserted
during this time. The SECAM signal is then passed through a
limiter.
The frequency demodulator function is carried out by a
frequency-locked-loop (F.L.L.). This consists of three
components: a tracking filter, a phase detector and a loop
filter. The center frequency of the tracking filter depends on
three factors: internal R-C product, ADJUST voltage, and
TUNING voltage. The tracking filter is dynamically tuned by
the TUNING feedback from the loop-filter forming the F.L.L.
The ADJUST control calibrates the F.L.L. and compensates
for variations in the R-C product. After the F.L.L., the color
difference signals are passed to another block where several
functions are carried out. The signals are de-emphasized
and outputs are provided to the Ident section. Another
function of this section is to generate the ICOMP signal used
for calibrating the F.L.L. This signal is blanked during the
H-IG period to ensure that (R-Y) and (B-Y) output signals
have a clean dc level for clamping purposes.
In addition, components are added to compensate for the
R-C product, and tuning offsets are introduced during the
active lines for FORfFOB.
Calibration of the F.L.L. takes place during every field
blanking interval, starting from field retrace and ending just
before the SECAM vertical Ident sequence (bottles). The
calibration current ICAl is derived from ICOMP during the
9-251
II
MC44002 MC44007
calibration gate (CAL) and integrated by an external
capacitor on Pin 11. The resulting voltage VEXT is then
transformed to generate the ADJUST control voltage
removing from the loop range most of the variations due to
internal RC products and temperature.
From here the selected luma signal goes to the RGB matrix.
The two color difference signals pass through the saturation
control. From here they go to a matrix in which G-Y is
generated from the R-Y and B-Y, and lastly, to another matrix
where Y is added to the three color difference signals to
derive R,G,B.
Control bits (via the 12C bus) allow the matrix coefficients
to be adjusted in order to suit different requirements,
particularly in NTSC. Table 1 shows the theoretical
demodulation angles and amplitudes and the corresponding
matrix coefficient values for each of the 4 selectable modes.
(The A mode corresponds to the standard PAUSECAMINTSC
mode). Although primarily intended for NTSC, this feature can
also act on PAUSECAM or extemal RGB signals.
The R,G,B inputs may take one of two different paths.
They may ei!her go straight to the output without further
processing, or via a separate matrix and the saturation
control. The path taken is controlled in software. When the
latter route is selected, the R,G,B signals undergo a matrix
operation to derive Y. From this, R-Y and B-Y are easily
derived by subtraction from Rand B; the derived color
difference signals are then subjected to saturation control.
This extra circuitry allows another feature to be added to the
TV set, namely the ability to adjust the color saturation of the
RGB inputs. After the saturation control the derived signals
are processed as before.
Color Difference Stages
This stage accepts luminance and color difference
signals, together with external R,G,B and Fast Commutation
inputs and carries out various functions on them, including
clamping, blanking, switching and matrixing. The outputs,
consisting of processed R,G,B signals, are then passed to
the Auto Gray Scale section.
A block diagram of this stage is shown in Figure 10. The
Y2, R-Y, B-Y together with R, G and B are all external inputs
to the chip. The Yl signal comes from the decoder section.
Each of the signals is back-porch clamped and then blanked.
The Y2 and R,G,B inputs have their own simple sync
separators, the output from which may be used as the
primary synchronization for the chip by means of commands
from the MCU.
The Fast Commutation is an active high input used to drive
a high speed switch; for switching between the Y and Golor
difference inputs and the R,G,B (text) inputs.
After blanking, the Yl and Y2 channels go to the Luma
Selector which is controlled by means of 2 bits from the MCU.
Table 1 Matrix Modes Coefficients
RR
RS
GR
GS
SS
SR
Rm
Gm
Ra
Ga
II
A
B
C
C
1.0
1.577
1.539
1.556
-0.251
0
-0.156
-0.248
-0.513
-0.443
-0.462
-0.504
-0.187
-0.168
-0.150
-0.125
1.0
1.0
1.0
1.0
0
0
0
0
0.562
0.9
0.9
0.91
0.31
0.344
0.3
0.3
90
100
106
106
237
236
240
246
NOTE: BB = Gain of (BouV(B--Y)in) = 1 (reference). BR = Gain of (BouV(R-Y)in) = 0 (theoretically).
Figure 9. SECAM Decoder (MC44002 only)
FLL Demodulator
Squarer
AGC
r--~-------------,
I
I
CAL
";j\
I
4.43MHz Calibration
SWitch
•
I
r---~I
L________ ____ _
~
VAl Adjust!
I
I
I
I
FLL Tracking
Filter
Ident
Out
RC·T
Compensation
ICOMP
PHIG
De·emphasis
Tuning Offsets
Output Interiace
SECAM Out
Timing Signals
(R·Y/B·Y Sequen.)
9-252
MOTORQJ-A ANALQG I.C DEVICE DATA
MC44002 MC44007
Figure 10. Color Difference Stages
__- - - - ,
r----_~A.
FIC
R
G
B
21
24
23
22
Inputs
Fast
Commutation
Sync
Separator
YXEN
Blanking
B
G
Bypass
R
Burst Gate
YMatrix
Blanking
BlankinglFast
Commutation I-Logic
6n-
R~~
~
Gate
R·Y 27
Inputs
Y2
25
§~
H--+-l+{ 18
G
r-
Outputs
T
Blanking
Gate
~
-,,-
BCL
I
10
Analog
Contrast
Y2
Luma
Selector
~
1
28
eg
.a g
R
1-+-*1 19 B
Separator
Y1
-. § _
H-++-J..I 17
JJ o
--B
=B
B·Y 26
r-
+---I-'~-'
Y1
I
Y1, Y2 Select
Y1 Clamp
I
MOTOROLA ANALOG IC DEVICE DATA
9-253
II
MC44002 MC44007
In order to implement automatic beam current limiting
(BCl), the possibility of fast contrast reduction has been
added. For normal operation, the Contrast control is
achieved by auto grey scale output loops and is 12C bus
controlled (see Section 4). In the case of excess beam
current, this control is not fast enough to protect the tube and
power supply stages. It is now possible, by acting on the
Pin 10 voltage, to reduce the contrast about 12 dB by
reducing the luma gain and saturation. In the case of direct
RGB mode, the RGB gains are also reduced.
Figure 11. Typical Contrast Reduction
1.0
I
~-1.0
g!
'=l
J
-3.0
I
I
I;;
~ -5.0
!z
8
-7.0
/
w
~ -9.0
~
a: -11
-13
II
./'
o
1.0
J
Figure 13. BrightJDark Current Control
2.0
3.0
PIN 10 VOLTAGE (V)
4.0
S.O
Figure 11 is showing the typical analog CONTRAST
reduction possible as a function of the voltage on Pin 10. Two
solutions are possible for obtaining the BCl function:
1st solution: A measure of the average and/or peak beam
current is applied to Pin 10, which causes a reduction of the
RGB drive levels to the high voltage video amplifiers. In this
case, no software control is required, but variations in color
balance and saturation may be observed. A typical
application is shown in Figure 12.
2nd solution: The beam current flags are read and acted
on by the MCU, which reduces the 12C bus CONTRAST
control to maintain the average beam current below the
desired level. In the case of rapid and extreme beam current
changes (black to white picture at high contrast level), the
circuit of Figure 12 may be used as a fast aging protection
while the MCU is reducing the CONTRAST through 12C bus.
The average of this method is to make any color
balance/saturation variation only transient.
Figure 12. Automatic Beam
Current limiter Application
EHT
I
I
I
I
1.0M
R4
10k
JI '-----1~-R-1
*-",33f1P.k.--'lM.:";
J
2.2M
CS
470n
9-254
Auto Gray Scale Control loops
. This section supplies current drives to the RGB cathode
amplifiers and receives a signal feedback from them,
proportional to the combined cathode currents. The current
feedback is used to establish a set of feedback loops to
control the dc level of the cathode voltage (cut-off), and gain
of the signal at the cathode (white balance). There are three
loops to control the dark currents dark loops and another
three to control the gains bright loops. The system uses 3
lines at the end of the vertical suppression period and just
before the beginning of the picture for sampling the cathode
current (Le., one line for red, one for green and one for blue).
The first half of reach line is used for adjusting the gain of the
channel and is usually called the "bright" adjustment period.
The second half of the line is used for adjusting the dc level of
the channel and is called the "dark" adjustment.
The theoretical circuit diagram for one channel is shown in
Figure 13 along with the basic equations. The dc level (Idc)
and gain (G) are both controlled by 7 bit DACs which receive
data directly from latches in which the required values are
stored between sampling periods.
9
10
Dart<
Bright
tPic!
Picture Output Current: 10(Pict) = A x [ IOC = G x ((B x ICont) + Ipial]
Dark Sample Output Current: IO(dk) = A x IOC
Bright Sample Output Current: 10(br) = IO(dk) - A x G X ICont
Black Level Output Current: IO(bk) = IO(dk) - B x A x G x ICont
= IO(dk) x B x [IO(dk) -IO(br~
A block diagram of the complete system is illustrated in
Figure 16. Data words from the MCU which represent the
RGB color temperatures selected at the factory, are stored in
latches 1,2,3 and D/A converted by DAC1,2,3 to reference
currents. During the bright adjustment period, a reference
current pulse, whose amplitude depends on the Contrast
setting, is output to the cathode of the tube. The gain control
is adjusted to bring the feedback current to the same value as
the bright reference current, which is defined by the color
intensity setting of the output considered. The currents must
match each other. If not, a current will flow in resistor R
producing an error voltage. This is then buffered into
comparators Comp1, 2 and is compared with voltage
references Vref1 and Vre f2. If the error voltage is greater than
Vref1, Comp1 causes the counter to count up. If the error
voltage is less than Vre f2, Comp2 sends a count-down
command. In this way, a "deadband" is set up to prevent the
outputs from continuously changing. With the color intenSity
DAC set to about 32d, the bright cathode current is 100 !lA
(10 times the dark current).
During load the contents of the counter are loaded into
latch 6 (for red dc) and then D/A converted. The resulting dc
current is then applied as an offset to the red output amplifier,
completing the loop. During the dark adjustment period, the
same intensity data is used but divided by a common factor
(typically 10). A black level reference pulse is applied and the
feedback loop adjusts the dc levels of the cathode to obtain a
set of cathode currents equal to the dark reference currents
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
(10 f.IA). Therefore, the image color will always be adjusted to
match the dark level color, i.e. grey scale tracking is ensured.
The Load/Backload sequencer is used to control which
latch is being addressed at any given time by means of the
timing signals input to it. The backload command sends the
data from the appropriate latch to the Up/Down Counter,
ready to be modified if necessary.
The Brightness control is affected by simply changing the
dc pedestal of all three drives by the same amount, and does
not form part of the feedback loop. The Contrast is adjusted
to a set of values dependent on the level of the bright pulse
applied during the set-up period. This level is set by a control
word from the MCU. Once the loops have stabilized under
normal working conditions, they may be deactivated by
means of a control bit from the MCU. When, however, any
change is made to either contrast or ROB intensity, the loops
must be reactivated. For normal operation, it is not necessary
to deactivate the bright loops.
Increasing the ROB intensity values will cause the
Black-to-White cathode voltage amplitude to increase for a
given Contrast setting. The White balance can therefore be
set by adjusting the relative values of R, 0 and B intensity. An
extra loop has been included via Latch 4 and DAC 4, which
operates during the field flyback time to compensate for
offsets within the loop. This has the effect of counteracting
any input offset from the Buffer/Amp and will also
compensate for cathode leakage should this be needed.
A second output of the reference currents from the ROB
DACs are used to compare with preset limits, to ensure that
the loops are working within their range of control. Should the
limits be exceeded in either direction, flags are returned to
the MCU to request that the 02 control be adjusted up or
down as appropriate. Once set-up, the servo loops maintain
the same conditions throughout the life of the TV.
Horizontal Timebase
The horizontal timebase consists of a PLL which locks up
to the incoming horizontal sync, and a phase detector and
shifter whose purpose is to maintain the H-Drive in phase
with the line flyback pulse.
Because of on-Chip component tolerances, the
free-running oscillator frequency cannot be set more
accurately than ± 40%; this range would be too much for the
line output stage to cope with. For this reason the
free-running frequency is calibrated periodically by other
means. During startup and whenever there is a channel
change, the phase detector is disconnected from the VCO for
2 lines during the blanking interval. A block diagram of the
line timebase is given in Figure 14. The calibration loop
consists of a frequency comparator driving an Up/Down
Counter. The count is D/A converted to give a dc bias which
is used to correct a 1.0 MHz VCO. The 1.0 MHz is divided by
64 to give line frequency and this is returned to the frequency
comparator. This compares Fh from the VCO with a
reference derived from dividing down the subcarrier
frequency. Any difference in frequency will result in an output
from the comparator, causing the counter to count up or
down; and thus closing the loop. Since the horizontal
oscillator is quite stable, this calibration does not need to be
carried out very often. After switch-on, the calibration loop
need only be enabled when the timebase goes out of lock.
A Coincidence Detector looks at the PLL Fh and compares
it with the incoming H-sync. If they are not in lock, a flag is
returned to the MCU. To allow for use with VCRs, the gain of
MOTOROLA ANALOG IC DEVICE DATA
the phase detector may be switched by means of commands
from the MCU (bits HOAIN1 and HOAIN2). The gain of the
phase detector is switched to the maximum value at the end
of the vertical sync pulse and then reduced to the selected
value after about 11 lines. This allows the horizontal timebase
to rapidly compensate any horizontal phase jump (e.g. with a
VCR) during the vertical blanking period, thus avoiding
bending at the top of the picture.
Twice line frequency is output from the PLL which may be
divided by either 1 or 2 depending on the command of the
MCU. The x2 Fh will be used with Feature Boxes. The phase
of the Fh and flyback pulses are compared in a phase
detector, whose output drives a phase shifter. A 6-bit control
word and D/A converter are used to apply an offset to the
phase detector giving a horizontal phase shift control.
The presence of the horizontal flyback pulse is detected; if
it is missing a warning flag is sent back to the MCU which can
take appropriate action.
Vertical Timebase
The vertical timebase consists of two sections; a digital
section which includes a vertical sync separator and
standard recognition; and an analog section which generates
a vertical ramp which may be modified under MCU control to
allow for geometrical adjustments. A parabola is also
generated and may be used for pin-cushion (E-W) correction
and width control (see FigUre 15).
In the digital section, the MC4400217 uses a video sync
separator which works using feedback, such that the
threshold level of a comparator (slice level) is always
maintained at the center of the sync pulse. Sync from any of
the auxiliary inputs may also be used. The composite sync is
fed to a vertical sync separator, where vertical sync is
derived. This consists of a comparator, up/down counter and
decoder. The counter counts up when sync is high, and down
when sync is low. The output of the decoder is compared with
a threshold level, the threshold only being reached with a
high count during the broad pulses in the field interval.
When "Auto Countdown" is selected, the vertical timebase
in fact starts off in the "Injection Lock" mode. This means that
the timebase locks immediately to the first signal received, in
exactly the same way as an old type injection locked
timebase. A coincidence detector looks for counts of the right
number (525 e.g.), and causes a 4 bit counter to count up.
When there are 8 consecutive COincidences, the vertical
countdown is engaged, and the MSB of the counter is
brought out to set the flag. Similarly, non~oincidence, which
will occur if synchronizing pulses are missing or in the wrong
place, or if there is noise on the signals, causes the counter to
count down. When the count goes back to zero, after 8
noncoincidences, the timebase automatically reverts to
"Injection Lock" mode.
If it is known that lock will be lost (e.g., channel change), it
is possible to jump straight into Injection Lock mode and not
have to wait for the 8 consecutive non-coincidences. In this
way the new channel will be captured rapidly. Once locked on
to the new channel, "auto countdown" is then reselected by
the MCU.
Under some conditions such as some VCRs in Search
mode, it is possible to get signals having an incorrect number
of lines, meaning that the countdown flag will go off because
of successive non-coincidences. In these circumstances, if
"auto countdown" is selected, the time base will automatically
lock to the signal in the Injection Lock mode. The fact that the
9-255
II
•
MC44002MC44007
flag is effectively saying that the vertical timebase is out of
lock' need not· be a cause for major concern, since the
horizontal timebase will still be locked to the signal, and has
its own flag - "Horizontal out of lock". The vertical countdown
and horizontal lock flags both perform an independent test for
the presence of a valid signal. A logical OR function can be
performed on the two flags, such that if either are present
then by definition a valid signal is present.
The vertical oscillator,has end-stops set at two line-count
decodes as given below:
50 x 625/740 = 42.2 Hz (min)
50 x 625/448 69.8 Hz (max)
These figures assume that the horizontal timebase is
running at 15,625 Hz. When the vertical timebase is in
Injection Lock mode, the line counter reset is inhibited so that
it ignores any sync pulses before a count of 448 is reached.
This prevents any possible attempted synchronization in the
middle of the picture. If the count reaches 740 lines, then
there is an automatic reset which effectively sets the lower
frequency limit. The choice of these limits is a compromise
between a wide window for rapid signal capture and a narrow
window for good noise immunity.
It is also possible to run the timebase in 2.0 V mode as
there are decodes for 100 Hz (2 x 50 Hz) operation with
upper and lower limits in proportion. This is, of course,
intended to be used in conjunction with field and frame
memory stores. The similar decodes which would be
ne,cessary to allow 120 Hz (2 x 60 Hz) operation have not, for
the present, been implemented. Finally, the timebase can be
forced into a count of either 625 or 525 by commands from
the MCU; in this mode the input Signal, if present, is ignored
completely. If there is no signal present save for noise, then
this feature can be used to obtain a stable raster.
In the analog section, an adjustable current source is used
to charge an external capacitor at Pin 6 to generate a vertical
ramp. The amplitude of the ramp is varied according to the
current source (Height), and is automatically' adapted when
the 525 standard is recognized by multiplying by 1.2. The
Linearity control is achieved by squaring the ramp and either
adding or subtracting a portion of it to the main linear current.
In addition, a correction current, depending on the level of
anode current, is applied in the sense of oppose a change of
picture height with EHT (Breathing).
=
9-256
The final ramp with corrections added is then passed to a
driver/amplifier and is output at Pin 7. The vertical ramp can
be used to drive a separate vertical deflection power circuit
with local feedback control. Vertical "S" Correction will then
be made using fixed components within the feedback loop of
the power op amp. The vertical position can be adjusted
under MCU control- this is achieved by varying the dc output
level at Pin 7. The vertical amplitude can be reduced to 75%
of its original value (bit VOl) to make possible the display of a
16:9 picture on a 4:3 screen.
The reference ramp is squared to provide a pin-cushion
correction parabola, developed across an external resistor'at
Pin 8. The parabola itself is squared, giving an independent
fourth order term (Corner Correction) whose level can also
be varied; this is then added as a further modifying term to
the E-W output. This latter correction is used for obtaining
good corner geometry with flat-square tubes. A variable dc
current is added to the parabola to effect a width control.
Using a suitable power amplifier and a diode-modulator in the
line output stage, the parabola may be used for E-W
correction and dynamic width control. A further control is
provided to shift the center point of the parabola up and down
the screen (Parabola Tilt).
All of the vertical and horizontal signals are adjustable via
6-bit words from the MCU, and stored in latches. The
adjustment controls available are:
Vertical Amplitude/Linearity/Breathing Correction/Position
Parabola (E-W) Amplitude/Horizontal Amplitude/
Corner Correction, and Parabola Tilt
The Anode Current Sense at Pin 9 is also used as a beam
current monitor. Two thresholds may be set, by the
manufacturer, using extemal components. The first threshold
sets a flag to the processor if beam current becomes
excessive. The MCU could, e.g., reduce brightness and/or
contrast to alleviate the condition. The second threshold sets
a flag warning of an overload condition where the CRT
phosphor could be damaged. If such a condition were to
arise, the processor would be programmed to shut down
the PSU.
The vertical blanking lines may be selected by means of a
bit from the MCU for either the 525 or 625 standard. The
interlace may also be suppressed again under the control of
the processor (bits ICI, IFI).
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
Figure 14. Horizontal Timebase
Horizontal Out of Lock
(MPU)
f - - - - - + - - - - - - - - - - - - - - - -....-~12
Drive Out
Flyback In
L - - - - - - - - + -_ _ _ _ _ _ _--.J~L__
___114
~
Figure 15. Vertical TImebase
Vertical
Amplitude
(MCU)
2Fh
Clock
Vertical
Linearity
(MCU)
Vertical Breathing
Correction
(MCU)
Vertical
Position
(MCU)
Reset
Composite
Sync
Horizontal
Amplitude
(MCU)
Parabola
Amplitude
(MCU)
8
E-WDrive
Overload and
Excess Average
Beam Current
(MCU)
V Countdown
Engaged (MCU)
7
Corner
Correction
(MCU)
Vertical
Ramp
Vertical
Drive
Anode Current
Sense
Parabola TI~ (MCU)
MOTOROLA ANALOG IC DeViCe DATA
9-257
II
MC44002 MC44007
Figure 16.·Auto Gray Scale Control Loops
EPBCReset
(MCU)
Excess Peak
Beam Current
(MCU)
Cathode
Current
Feedback
R Intensity
(MCU)
G Intensity
(MCU)
ToMPU
r---A---.
G2Up G2 Down
Request Request
B Intensity
(MCU)
RDC
G DC G2 UpIDown
BDC
Request
Offset
Compensation
UpJDown
Counter
Clock Debounce
1 - - - - Vertical
Clock
Vertical
II
RED Line
GREEN Line
CD
<>
<=
Q)
BLUE Line
"g
en
Timing
Signals
al
:§
~
Backload
..J
Load
21
Bright
Dark
PIN FUNCTION AND EXTERNAL CIRCUIT REQUIREMENTS
The following section describes the purpose and function
of each of the 40 pins on the MC44002l7. There is also an
explanation of the external circuit component requirements
for a practical application; a diagram of the small signal circuit
will be found in Figure 17. One of the primary design aims for
the MC4400217 was to use the minimum number of external
components, and where these are necessary, to employ low
9-258
cost and easily obtainable standard types. Thus for example,
as all the video Signal filtering is carried out on the IC, there
are no coils required whatsoever. The most common
requirement is for ac coupling capacitors which are far too big
to be integrated onto the chip. The time constants on certain
pins are deliberately determined by external components to
facilitate testing and for fine tuning the performance.
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
PIN FUNCTION DESCRIPTION
Pin
Equivalent Internal Circuit
r ----------Vee
I
I
I
JO.llr-~--~--+_~--~
Description
ACC
External Filter used by ACC section. A single capacitor, that does not
have a critical value, typically 0.01 IIF, filters the feedback loop of the
chroma automatic gain control amplifier.
I
I
IL __________
Gnd _
r------------
2
40
I
I
I
1.0k
~~~r-~--~--~N+~
100nF
I
I
I
IL _________ ~n~_
V
Supply
3
r-VCc-------
I
I
I
I
I
ILGnd
--+--.........- -.........- _
_________
! 41
r-------
4
T.~U-
r
4--AAA..-J...
.n
150 k
IL ______
....Gn....d - -..................
_-
r---------
5
I
Video Input 1 (Pin 40) and 2 (Pin 2)
Video inputs (Pin 2 Video 2; Pin 40 Videol); Intended for a
nominal 1.0 Vpp input level of composite video. Separate luma and
chroma components may also be used with these input pins for
S-VHS. The external circuit requirement is for a coupling capacitor of
0.01 IIF and a series resistance not exceeding 1.0 kn. The input
selec1ion and adaptation for Y and C is carried out in software.
=
=
Reference Current
Master reference current used throughout the IC. This is programmed
by means of an external pull-up resistor, as on-board resistors are
not sufficiently accurate. The designated current is 70 !lA. This pin
should be very well de-coupled to ground to avoid picking up
interference from the nearby 12C bus inputs. Nominal voltage at the
pin is 1.3 V.
l2cclock
12C bus clock input. This input can be taken straight into the IC, but in
a real TV application it may be prudent to fit a series current limiting
resistor near the pin in case of flash-over. A single pull-up resistor to
5.0 V is required. Although its value is associated with the liP, taking
into account system capacitance at high data rates, a value of 4.7 kn,
giving optimal performance, is recommended.
12C Data
12C data input. Comments above for Pin 4 also apply to this pin.
To MeU _+_..JVI.IIr--o--_ __.----\'Vv-..-t.
I
I
I
IL Gnd
.........--<1>----01--' _
_________
r--vcc------
6
r
O.082 I1F
I
I
I
Vertical Ramp
A current is used to charge an external capacitor connected to this
pin, developing a voltage sawtooth with a field period. The capacitor
value determines the ramp amplitude. 82 nF is the more convenient
value for symmetrical, linearity and parabola tilt adjustments.
I
I
IL _________ _
MOTOROLA ANALOG IC DEVICE DATA
9-259
II
MC44002 MC44007
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
Description
Vertical Drive
7
The sawtooth derived on Pin 6 is used to drive an extemal power
amplifier vertical output stage. The amplitude, linearity and pOSition of
the output ramp are adjustable via the MCU.
T o V e r t i C VCC
8lfui
I
Deflec~ion
Amplifier
300 " •
I'"
IL ______
Gnd
_
~ [-------...:-
8
ToE-W
T
Amplifier
~
!L
500r
r.
Gnd __
Anode Current
9
r------
Anode
Current
560 k
~
1
50k
T
I
I
L===~~_
r
1
10
1
Vec
~
Vec
Analog
Contrast o-~T:>--+---L.r
II
I
t--I
2.0k
I
Gnd
L _________ _
r
11
I
200k
t,OkJ1Ok
ffi
II
I
200 k
Above 2.5 V on the pin, the contrast remains maximum. Below 2.5,
the contrast is reduced by about 12 dB, which is reached at about
1.0V.
This pin is used for the storage capacitor of the analog SECAM
calibration loop (typically 100 nF). The capacitor is required
regardless of whether or not SECAM will be decoded.
___ ~n!.. ___ _
5.0V
r--
1.0k
To Line OIP "'-Driver Stage ~-
Anode Contrast
This pin is used as an Analog Contrast monitor, allowing fast Beam
Current limiting (BCL). The fast BCL is controlled by Pin 10 voltage,
which decreases with the contrast reduction (see typical curve).
10k
L_~~
12
The pin is connected via about 560 k.Q series resistor to the bottom of
the E.H.T. overwinding. Therefore, increasing beam current will pull
the voltage on this pin more negative. This change Is sensed within
the chip and used to apply a correction to the ramp and parabola
amplitudes. With large beam currents, thresholds at +Vbe and
-2.0 Vbe set off warning flags to the MCU, which then has to take the
appropriate action. The anode current levels at which these
thresholds are reached are set up using fixed external resistors.
f
100nFl
.,r-1
Used as an anode current monitor whose purpose is to: (1) Provide
E.H.T. compensation (antt-breathing) for the vertical ramp; and (2)
provide warning of excessive and overload beam current conditions.
SECAM Calibration Loop
Vec
I
47k
0.0if.!7
9-260
Parabola (E-W) Drive
An inverted parabolic waveform derived by squaring the vertical ramp
is used to drive an external power amplifier. In sets fitted with a diode
modulator type line output stage, this provides width control and
pilH:ushion correction. The parabola Is squared again to give a fourth
order correction term required for flat square tubes. The E-W
amplitude, dc level, tilt and corner correction are all adjustable by
means of the MCU. This is a current output and may be used, for
example, to drive the virtual ground of an extemal power amplifier
r-----I
VCC
I
I
I
Horizontal Drive Output
Horizontal drive pulses having an approximately even mark-to-space
ratio emerge from this pin. This is an open-collector output which can
sink up to 10 rnA. However, taking this much current is not
recommended since there is no separate ground pin available which
may be connected near the line output stage; noise could be injected
into the signal ground on the IC. Therefore, with a transformer driven
line output stage, this output has been designed to be used with an
extra external transistor inverter between the IC and the line driver.
The transistor is open during the period when the line deflection
transistor should be conducting.
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
PIN FUNCTION DESCRIPTION (continued)
Equivalent Internal Circuit
Pin
13
n
rl
Line
Flyback
VCC
~
Pulse 11
'"'-
120k
T
J
Flyback sensing input taken from the line output transformer. These
pulses are used by the 2nd horizontal loop for H-Phase control. A
positive going pulse from 0 to 5.0 V amplitude is needed for correct
operation. The intemal impedance of the pin is about 50 kn and an
extemal attenuating series resistor of around 120 kn will also be
needed.
180 k
'"
I
I
L~~~_=-
____ _
r
14
Description
Horizontal Flyback Input
Horizontal Loop 2 Filter
.Jj1}
,r-i' i Wfl
Components at this pin filter the output of the phase detector in the
2nd horizontal loop. A simple extemal filter consisting of a 0.1 IlF
capacitor is required.
L _____ _
r
15
100kD~~
0.1
VCC
I ~v ~
t
470 I
pFI
_
-
Horizontal Loop 1 Filter
't-~
('
Gnd
r
Horizontal PLL loop time constant. Components at this pin filter the
output of the phase detector is in the 1st horizontal loop. The value of
RC time constant is selected with external components to give a
smooth recovery after the field interval disturbance and to ensure
optimum performances in the presence of noise.
L ______ _
r
17
18
I
19
1
RGBOutputs
~cc
To R, G, B _---<:)--+----,
T
Amplifiers
II
(,.
The R, G and B drives are current rather than voltage due to the
limited headroom available with the 5.0 V supply line. The outputs
themselves consist of open-collector transistors and these are used
to drive the virtual ground point of the high voltage cathode amplifiers
100
L_______ _
20
S.OV
390
Gnd
r--------
!~
I
I
220
J6
,~
J IL _______
Gnd
~ _
Feedback
21
Fast-Commutate
Input
Feedback
Current feedback sense derived from the video output amplifiers. The
currents from all three guns are summed together as each is driven
sequentially with know current pulses during the field interval. This
feedback is then compared with internally set-up references. A low
value ceramic capacitor to ground may be fitted close to this pin to
help stabilize the control loops.
A secondary function of this pin is for peak beam current limiting.
When the feedback vonage during picture time becomes too great (i.e.
too high beam current), a threshold at VCC + 3.0 Vbe is exceeded at
which time a flag is sent to the MCU. The MCU then has to carry out
the function of peak beam IimHer by e.g. reducing contrast until the
flag goes off. The threshold current is set externally with a fixed
resistor value.
rl ~~
Fast Commutate
A very fast active high switch (transition time IOns) used with text on
I
the RGB inputs, for overlaying text on picture. This hardware swHch
may be enabled and disabled in software.
T
I
IL_______
Gnd
_
MOTOROLA ANALOG IC DEVICE DATA
9-261
II
MC44002 MC44007
PIN FUNCTION DESCRIPTION (continued)
Pin
Equivalent Internal Circuit
,--------1
22
23
24
25
VCC
vr~ ~
1
1
l
o. 1lLF
0-1
1'>1_
1
1
100k
1
1
L _________
Gnd
26
27
,
V~y
l
o. 1lLF
0-1
28
V21nput
Auxiliary external input to MC4400217 which can be used in
conjunction with auxiliary color difference inputs and/or as a sync
input. The pin should be driven from a source of less than 1.0 kn
output impedance with 700 mVpp luminance signal. The signal must
be ac coupled via an external 0.1 ILF coupling capacitor. Internal
clamp and sync separator are provided.
B-V and R-V Inputs
Corrected color difference inputs from the MC44140. The signals are
ac coupled via 0.1 ILF capacitors and are clamped internally. The
Inputs should be driven from a source of less than 1.0 kO output
impedance.
VCC
1
1
1
Description
RGB Inputs
These external Input signals to the color difference stages are ac
coupled into the IC via 0.1 ILF capacitors. They have a clamp and
sync separator. The inputs should be driven from a source of less
than 1.0 kn output impedance with 700 mVpp signal levels.
""_
1
1
100 k
1
1
L _______Gnd
VI Clamp
External capacitor used by the circuit which clamps the Y1 signal
output on Pin 29. A typical value is 4.7ILF.
'VCC
1
1
>-~
1
1
4.71=
ILF ... T
1
L______ ~~
II
29
r
VI Output
The luminance, after passing through the filter and delay line/peaking
sections, is made available on this pin. It is also routed internally to
the color difference stages.
VCC
1
1
1
1
1
1
- Gnd
L___
-.. ____
,
30
1
1
ToMC44140 1
VCC
11-
1
System Select
A multilevel de output controlled in software, which is used by the
MC44140 for system selection .. Please refer to separate functional
description of the MC44140 chroma delay line.
I
30k
I ________
L
Gnd
r
31
1
1
ToMC44140
I
I
I
Vee
11-
Sandcastle
A special multilevel timing pulse derived in the MC4400217 for use by
the MC44140. Please refer to separate function description of the
MC44140 chroma delay line.
~ 200~
1
L________
Gnd
9-262
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
PIN FUNCTION DESCRIPTION (continued)
Pin
32
33
Equivalent Internal Circuit
r---------
14.3M~
TOPin~2~D
MC44140
22 P
:32
VCC
1 33
~ 0 1-0''''----+--1---''''''''''''--
120 PI 17.7 MHzl
':'
1
L ________
_
Gnd
1
34
35
Description
Crystals (Respectively 14.3 MHz and 17.7 MHz)
Drive for externally filted crystal clock reference for PAL, SECAM or
NTSC. Four times Fsc is used. If the NTSC system is not going to be
received, the 14.3 MHz crystal may be omilted. The crystal is parallel
driven from a single pin and it requires a series load capacitance of
appropriate value (usually 20 to 30 pF). Only crystals intended for
VCO use should be filted. The reference frequency is divided down in
a capacitor chain to provide about 50 mV of clock reference for the
MC44140.
Positions for Pins 32 and 33 are selected by software.
5.0 V Supply (35) and Ground (34)
Supply line, nominally 5.0 V, requiring about 120 mAo The actual
voltage should be in the range of 4.75 to 5.25 V for usable results. It is
recommended to decouple the supply line using a small ceramic
capacitor mounted close to the supply and ground pins.
~-------
36
37
1 VCC
1
1
B-V and R-V Outputs
Demodulated color difference outputs. These signals are ac coupled
to the MC44140 for correction and delay with PAL and SECAM
respectively. Signal level of about 1.4 Vpp may be expected on 8-V
output when using a standard 75% color bars input video signal.
1
1
To MC44140
L
_
1 ______
Gnd
r----------
38
1
VCC
1
1
0.047 1
Identification
External filter used by R-V identification circuit. The filter normally
consists of a single capacitor whose value is a compromise between
rapid identification and noise rejection. Experience has shown that
0.047 IlF is a suitable value.
-P
r-----------
39
1
VCC
1
1
0.0471
-P
50k
50k
1
1
1
1
L __________Gnd
_
MOTOROLA ANALOG IC DEVICE DATA
II
Oscillator Loop Filter
External time constant for chroma PLL. The crystal reference
oscillator is phase locked to the incoming burst in PAL and NTSC. A
low value ceramic capacitor, for good noise immunity, is normally
placed in parallel with a much longer RC time constant. The PLL
pull-in range is reduced when the time constant on the pin is made
bigger. allowing this function to be optimized by the user.
9-263
II
t
01
-I'>
I
S.OV
Video 2
Video 1
f
f
. . 0.1
S.OV
Gnd
~~
. . 0.1
Clk
Data
S.OV
"TI
-WDMve
~
Vertical
DMve
.......a;
0
~
0
c
Anode
Current
"0
n-
I
Analog 0
Contrast
O
N
)0
"0
"0
0
~
0
::J
0
ac
;::;
~I
a
:D
o
.0047
H-DMve
BC337
120k
.~
)0
z
r-
)0
8
(';
c
~
(';
m
c
~
)Ii
H-F1yback Gnd
R G
(Outputs)
B
FIB
F/C
B
G
R
Y2 R-Y B-Y
(Inputs)
R-Y B-Y Y1
(Outputs)
.Ilo
.Ilo
!!!.
5'
S.OV
s:
s:
.Ilo
.Ilo
0
0
.....
MC44002 MC44007
SOFTWARE CONTROL FUNCTIONS
General Description
As already related in the circuit description, the
MC44002/7 has a memory of 18 bytes. All, except
Sub-address 77 and 7F, use the 6 least significant bits as an
analog control register with D/A converters (64 steps) within
the memory section. The remaining bits are controlled
individually for switching numerous functions. Table 2 gives a
listing of all the memory registers and control bits. An
explanation of the function of the 16 DACs is given below.
Vertical Amplitude - Changes the amplitude of the
vertical ramp available on Pin 7.
Vertical Breathing Correction - A correction is applied to
the vertical ramp amplitude in a sense opposite to the picture
expansion and contraction produced by changes in beam
current. This register alters the sensitivity of the beam current
sensing and hence the size of correction applied for a given
change in beam current.
Parabola Amplitude - Changes the amplitude of the E-W
output parabola developed across an external pull-up
resistor at Pin 8.
Parabola Tilt - Shifts the point of inflection of the E-W
parabola from side to side along the time axis. Also known as
keystone correction.
Vertical Linearity - The vertical ramp is multiplied by itself
to give a squared term, a part of which is either added or
subtracted to the linear ramp as determined by this register.
Corner Correction - An independent 4th order term
which is subtracted from the E-W parabola to achieve correct
geometry with flat square tubes.
Horizontal Amplitude - A variable dc offset applied to the
E-W output parabola on Pin 8.
Vertical Position - Adjust the dc level of the vertical ramp
on Pin 7, allowing vertical centering control.
Horizontal Phase Control - Applies a variable phase
offset to the horizontal drive pulse at Pin 15 providing for a
picture centering control.
B, G, R Intensity - These controls set up the current
reference pulses used when sampling the beam current
during field interval. The data is fixed by the TV manufacturer
when setting up the White balance and the CRT for correct
Gray Scale tracking.
(All the above registers are for use during the test and
setting up procedures; the remaining 4 registers are also
user controls.)
MOTOROLA ANALOG IC DEVICE DATA
Contrast - During bright sample time during t:',e field
interval, this control varies the level of the current pulses
injected into the R,G,B channels, so altering the picture
contrast.
Brightness - A variable current pedestal which is added
to the three drives during active picture time.
Saturation - A variable gain control for the two color
difference signals.
Hue - Achieved by mixing a portion of one color difference
signal into the other.
Individually Adjustable Control Bits - These consist of
bits 7 and 6 of registers 77 through 88, as well as bits 0 to 5
of register 77 and bits 0 to 3 of register 7F. Some of these are
used individually to control single functions requiring just
on/off switching; and some are arranged into 2 or 3-bit words
(e.g., luma peaking). A list of control words and truth tables
for these may be found in Table 3.
CA 1, CBl - Used to change the mode of operation of the
vertical timebase to either injection lock or auto countdown,
or to force it into 525 or 625 lines. Just prior to changing
channel, the vertical timebase can be switched to injection
lock mode and when a new channel is captured, the
timebase is switched back to auto mode. In this way there is
no delay in locking onto the new channel and hence no
picture roll. If there is no valid signal being received, the
display can be stabilized by forcing the timebase into 525 or
625 lines.
IC1, IF1 - These bits are used to suppress the field
interlace, which can be scanned in the nearest even or odd
half line.
HI, VI - Selects the type of SECAM ident when operating
in this mode. Either vertical ident bursts or horizontal ident
can be selected individually, or ident can be taken from a
combination of the two. In certain transmissions the vertical
SECAM identification is not present (and sometimes
replaced by other signals), so it is strongly recommended
that only the horizontal identification be used. These bits
must both be set to 1 when SECAM is not decoded
(MC44002 and MC44007).
SSA, SSB, SSC - Used to set the color decoder and the
dc level of the System Select output from the MC44002I7,
Pin 30. This output is used by the MC44140 delay line in turn
for changing between PAL, NTSC, SECAM and external
modes of operation. In effect, the MC44140 is being
controlled by the 12C bus via the MC44002l7.
9-265
II
•
MC44002 MC44007
Table 2a. Register Memory Map
9-266
HEX Sub-address
MSB
77
T3
S-VHS
Data Byte
78
INTSEL
CALKILL
Vertical Amplitude
FSI
I
SAl
I
LSB
ICI
I
IFI
I
CSI
79
HI
VI
Vertical Breathing Correction
7A
XS
SSD
Parabola Amplitude
7B
T1
T2
Parabola Tilt
7C
SSC
SSA
Vertical Linearity
7D
P1
SSB
Comer Correction
7E
P3
P2
7F
D3
D1
80
DEN
D2
Vertical Position
Horizontal Phase Control
I
CAl
Horizontal Amplitude
Reserved
I
VDI
I
NT2
81
Y2EN
Y1 EN
82
TEST
YXEN
Blue Intensity
83
Not Used
HGAIN1
Green Intensity
84
HGAIN2
NORM
Red Intensity
85
BRIEN
2x Fh
Contrast
86
SSE
HEN
Brightness
87
SSl
Not Used
Sal\Jration
88
V1N2
SS2
I
NT1
INTO
Hue
00
Dummy -If H EN, then starts H timebase
FF
Dummy - Resets peak beam limit flag
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
Table 2b. Register Memory Map
~ I
Variable Low Pass Filter
(0 - By-Passed; 1 = Enabled)
Comp Video/5-VHS Swtlching
(0 = S-VHS; 1 = Compostle
50 Hzl100 Hz Field Rate
(O-SOHz; 1 =100Hz
Vertical Blanking
(0 =for 525 lines, 1 =for 625 lines)
o
I
D3
I
T3 5-VHS
FSI BAI
~
D1
II
ICI
IA
L~
ICI IA
0 X
1 0
1 1
I
~
CBI CAl
Field Scan
Interlaced
Even 112 Line
Odd 112 Line
Reserved
VI
0
1
0
1
T1 T2
SECAMldent
H+V
Honly
Vonlv
None
lPF Response
0
0
1
0
1
0
LP1
LP2
LP3
1
1
LP4
I
Rr,;~~~~:: _
XtalSelect -
Luma Peaking
INTSEL
CALKILl -
HI
VI
Force 625
Force 525
I"ect. Lock
Auto Count.
XS
SSD
T1
T2
SSC
SSA
P1
SSB
-
Matrix Mode
C
0
B
A
A
C
0
B
Disable Calibration Loop
Force PAL Mode
Select in Delay Line
P3
P2
03
01
Disable RGB Inpuf -
DEN
02
Enable Y21nput -
Y2EN
Y1 EN
-
Enable Luma from Decoder
For Production Test -
TEST
YXEN
-
Enable Luma Matrix
Notused
HGAIN1
-
Phase Detector Gain Reduction by 3
Phase Detector Gain Redution by 2 -
HGAIN2
NORM
-
Select 625150Hz
Enable "Bright' Sample -
BRIEN
2xFh
-
DoubleFh
SSE
HEN
-
Enable H-Drive
SS1
NoIUsed
V1N2
SS2
Select Video Input -
Sync Mode
SSA NT2 NT1 NTO
X
X
X
X
0
X
X X
0
X 1
1
X 0
1 0
X 1
0
0
Vertical Display Mode;
(0 = 16:9; 1 = 4:3)
Hf
0
0
1
1
CAl CBI
0
0
0
1
1
0
1
1
sse
SSA
SSB
Decoder
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
SECAM
PAL
NTSC
None
External
SS1
0
0
1
1
SS2
0
1
0
1
X
X
Sync Source
None
RGB
Y2
Not Used
Comp. Video
Luma Delay in Multiples of 56 ns or 70 ns
SSE
0
0
0
0
1
NOTES: SECAM decoding is selectable in the MC44002 only. HI and
VI must be set to 1,1 in non--SECAM applications.
MOTOROLA ANALOG IC DEVICE DATA
9-267
II
MC44002 MC44007·
Table 3. Control Bit Truth Tables
CAl
CBI
Sync Mode
ICI
IFI
0
0
Force 625
0
X
Interlaced
0
1
Force 525
1
0
Even Up 1/2 Line
1
1
Odd Up 1/2 Line
LPF Response
1
0
Injection Lock
1
1
Auto Countdown
HI
VI
SECAMldent
T1
T2
0
0
H+V
0
0
LP1
0
1
H only
0
1
LP2
1
0
V only
1
0
LP3
1
1
None
1
1
LP4
SSC
SSA
SSB
Color Dlff. Source
SSE
SS1
SS2
Sync Source
0
0
0
SECAM
0
0
0
None
0
.0
1
PAL
0
0
1
RGB
0
1
0
NTSC
0
1
0
Y2
0
1
1
None
0
1
1
Not Used
1
X
X
External
1
X
X
Compo Video
P2
P1
P3
Luma Peak (dB)
@3.0MHz·
SSA
NT2
NT1
NTO
Matrix Mode
0
0
0
8.5
0
0
0
X
A
0
0
1
8.0
0
0
1
0
D
0
1
0
7.2
0
0
1
1
A
0
1
1
6.3
1
B
0
a
5.4
1
a
a
a
1
1
A
1
0
1
3.8
1
1
a
C
1
1
a
2.3
a
a
a
a
1
1
1
0.0
1
• Value shown for 17.7 MHz crystal.
Peak Frequency is = 2.2 MHz when using 14.3 MHz crystal.
9-268
Field Scan
1
1
1
A
a
X
A
1
a
a
1
X
D
1
1
a
X
B
1
1
1
X
C
HGAIN1
HGAIN2
H-Phase Detector Gain
a
a
a
Divide by 3 (Sync Window Enabled)
1
Divide by 6 (Sync Window Enabled)
1
a
High (Sync Window Disabled)
1
1
Divide by 2 (Sync Window Disabled)
01
02
03
PAL (T3 = 1)
NTSC(T3= 1)
SECAM (T3 = 0)
S-VHS (T3 = 0)
a
a
a
a
a
a
780ns
940n5
1050 ns
N/A
1
836ns
1010 ns
1106 ns
N/A
1
a
892 ns
1080 ns
1162 ns
N/A
0
1
1
948 ns
1150 ns
1218 ns
N/A
1
0
a
1004 ns
1220 ns
1274 ns
N/A
1
a
1
1060 ns
1290 n5
1330 ns
N/A
1
1
a
N/A
N/A
N/A
480ns
1
1
1
N/A
N/A
N/A
480ns
MOTOROLA ANALOGICDEVICE DATA
MC44002 MC44007
SSE, SS1, SS2 - These 3 bits select the signal input from
which the timebase synchronization is taken. The composite
video input has a high quality sync separator which has been
designed to cope with noise and interference on the video;
the RGB and Y2 inputs have simple single sync separators
which may also be used for synchronization.
T1, T2 - The bits are used to modify the response of the
variable Low Pass Filter placed at the composite video inputs
(for PAUNTSC signals) in order to compensate for IF filtering
and the Q of external sound traps.
P1, P2, P3 - These 3 bits are used to adjust the Luma
peaking value. The amount of peaking indicated is with
respect to the gain at the minimum peaking value (P1, P2,
P3=111).
01, 02, 03 - These 3 bits are used to adjust the Luma
delay. The indicated delay is that from the video inputs (Pins
2 and 40) to the Y1 output. The amount of delay depends on
the composite video standard used if S-VHS is selected.
NTO, NT1, NT2 - These 3 bits are used in conjunction with
SSA for the selection of the matrix coefficients mode.
HGAIN1, HGAIN2 - These 2 bits are used to set the gain
of the horizontal phase detector. The high gain pOSition is
used to acquire lock and for operation with a VCR. Setting
HGAIN1 to 0 also enables a horizontal sync window. The low
gain position is used for off-the-air signals.
The remaining control bits are used singularly and are
listed as follows:
T3 - When high, this bit enables the variable Low Pass
Filter at the video inputs. For optimum performance, T3 must
be set to 0 in S-VHS and SECAM modes, and to 1 in PAL
and NTSC. The filter response is set with bits T1, T2.
S-VHS - Set to 1 for normal composite video input to
Pin 2 or 40. In this mode, the luma-chroma separator is
active. Set to 0 for S-VHS (Y/C) operation at those pins. In
this mode, luma is to be applied to the selected video input
(with bit V1N2), and chroma is to be applied to the other
input. The luma-chroma separator is bypassed.
FSI- Selects either 50 Hz or 100 Hz field rate. When bit is
low, 50 Hz operation is selected. No usable with NTSC.
BAI - This bit selects the number of blanked lines for
either 525 or 625 line standards.
INTSEL - The vertical sync separator operates by starting
a counter counting up at the beginning of each sync pulse, a
field pulse being recognized only if the counter counts up to a
sufficiently high value. The control bit INTSEL is used in
taking the decision as to when a vertical sync pulse has been
MOTOROLA ANALOG IC DEVICE DATA
detected. When low, the pulse is detected after 36 Its; when
high after 68 its. This may find application with anti-copy
techniques used with some VCRs, which rely on a modified
or corrupted field sync to allow a TV with a short time
constant to display a stable picture. However, a VCR having
a longer time constant will be unable to lock to the vertical.
CALKILL - Enables or disables the horizontal calibration
loop. The loop is normally enabled only during startup for
some seconds and when there is no signal present. The loop
may be disabled so long as the horizontal timebase is locked
to an incoming signal.
XS - Is used to change between the two external crystal
positions (Pins 32 and 33).
SSO - Forces system select to PAL level. Can be used to
override SECAM mode in the delay line. When low, SECAM
mode is enabled (MC44002 only).
VOI- Either 4:3 or 16:9 display mode can be chosen using
this bit. When low, the 16:9 mode is enabled.
o EN - Enables or disables the RGB Fast Commutation
switch for the RGB inputs. When low, RGB inputs are
enabled.
Y1 EN - Switches Y1 through to the color difference stage.
Y2 EN - Switches Y2 through to the color difference stage.
Test - When bit is low, enables continuous sampling by
the RGB output control loops throughout the entire field
period. Used only for testing the IC.
YX EN - Enables the luma matrix allowing saturation
control in the color difference stage.
Norm - Alters the division ratio for the reference
frequency used by the horizontal calibration loop. Always
used when changing between 14.3 MHz and 17.7 MHz
crystals.
BRI EN - Used to switch on or off the "bright" sampling
pulses used by the RGB output loops. This feature was
originally introduced to prevent any backscatter from these
three bright lines in the field interval from getting into the
picture. Must be enabled when adjusting intensity Contrast or
Red, Green and Blue.
2x Fh - Line drive output is either standard 15.625 kHz
(15.750 kHz) or at double this rate.
H EN - Control bit enables horizontal drive pulse. This is
normally done automatically after the values stored in the
MCU nonvolatile memory have been read into the
MC4400217 memory.
V1N2 - To select between Video Inputs 1 and 2.
9-269
II
•
MC44002 MC44007
Table 4. Control Bit Functions
Bits
T3
S-VHS
BilLoW
Bit High
Variable Input LPF By-Passed
Variable Input LPF Enabled
S-VHS Mode Enabled
Composite Video Mode Enabled
FSI.
50 Hz Field Rate Selected
100 Hz Field Rate Selected
BAI
Vertical Blanking for 525 Lines
Vertical Blanking for 625 Lines
INTSEL
Short Vertical Time-Constant
Long Vertical Time-Constant
CALKILL
H Calibration Loop Enabled
H Calibration Loop Disabled
17.7 MHz Crystal (Pin 33) Selected
14.3 MHz Crystal (Pin 32) Selected
SSD
XS
System Select Active
System Select Forced to PAL
DEN
RGB Inputs Enabled
RGB Inputs Disabled
Y2EN
External Luma Input Switched "Off"
External Luma Input Switched "On"
Y1 EN
Luma from Filters Switched "Off"
Luma from Filters Switched "On"
TEST
Video Outputs Sampled Continuously
Video Outputs Sampled Once per Field
YXEN
Disable Luma Matrix (RGB Saturation Control)
Enable Luma Matrix (RGB Saturation Control)
HGAIN1
H-Phase Detector Gain Division by 3 Enabled
H-Phase Detector Gain Division by 3 Disabled
HGAIN2
H-Phase Detector Gain Division by 2 Disabled
H-Phase Detector Gain Division by 2 Enabled
NORM
H-Reference Divider Ratio for 17.7 MHz Crystal
H-Reference Divider RatiO for 14.3 MHz Crystal
BRIEN
"Bright" Sample Switched "Off"
"Bright" Sample Switched "On"
2xfH
H-Drive : 1 x fH
H-Drive : 2 x fH
HEN
H-Drive Enabled
H-Drive Disabled
16:9 Display Mode Enabled
4:3 Display Mode Enabled
Video Input 2 (Pin 2) Selected
Video Input 1 (Pin 40) Selected
VOl
V1N2
II
9-270
MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
FLAGS RETURNED BY THE MC4400217
When the Address ReadlWrite bit is high the last two bytes
of 12C data are read by the MCU as status flags; a listing of
these may be found in Table 5. The MC4400217 is designed
to be part of a closed-loop system with the MCU; these flags
are the feedback mechanism which allow the MCU to interact
with the MC44002l7.
A brief description of each of the flags, its significance and
possible uses are given below.
Table 5. Flags Returned
Clock #
Flag (Bit High)
10
Horizontal Flyback Present
11
Horizontal Drive Enabled
12
Horizontal Out Of lock
13
Excess Average Beam Current
14
less Than 576 lines
15
Vertical Countdown Engaged
16
Overload Average Beam Current
17
Reserved
18
(Acknowledge)
19
Grid 2 Voltage Up Request
20
Grid 2 Voltage Down Request
21
OK
22
Fault
23
ACCActive
24
PAL Identified
25
SECAM Identified (MC44002 only)
26
Excess Peak Beam Current
27
(Acknowledge)
Horizontal Flyback Present - A sense of the horizontal
flyback is taken via a current limiting series resistor from one
of the flyback transformer secondaries to Pin 13. This is used
for the H-phase shift control, but the presence of the pulse is
also flagged to the MCU. Should the flag be missing after the
chassis has been started up, then the MCU would have to
shut down the set immediately.
Horizontal Drive Enabled - Indicates that the horizontal
drive pulse output at Pin 15 has been enabled. This occurs
after the stored values in the nonvolatile memory have been
transferred to the MC4400217 memory.
Horizontal Out of Lock - This flag is high when no valid
signal is being received by the MC4400217. Possible action in
this case would be to change the phase detector gain and
time constant bits to ensure rapid capture and locking to a
new Signal.
Excess Average Beam Current - This is one of two
threshold levels which are determined by an external
component network connected to the beam current sensing
at Pin 9. This flag indicates an excess of beam current. A
typical application of this flag in conjunction with "Overload
Average Beam Current" flag is for the software controlled
Automatic Beam Current Limiting. When this flag is "on", it is
recommended that the software prevent increases to the
Contrast setting.
Less Than 576 Lines - Output from the line counter in the
vertical timebase. If there is a count of less than 576 this is
indicative of a 525 line system being received. If the flag is
low then a 625 line system is being received. This information
can be used as part of an automatic system selection
software.
Vertical Countdown Engaged - The vertical timebase is
based on a countdown system. The timebase starts in
Injection Lock mode and when vertical retrace is initiated a
4-bit counter is set to zero. A coincidence detector looks for
counts of 625 lines. In Auto mode each coincidence causes
the counter to count up. When eight consecutive
coincidences are detected, the countdown is engaged. The
MSB of the counter is used to set this flag to the processor.
Overload Average Beam Current - This is the second
threshold level which is set by the external component
network on Pin 9. The flag warns of an overload in anode
current which should be lowered by reducing the Contrast.
Grid 2 Voltage Up/Down Requests - These flags
indicate when the RGB output loops are about to go out of the
control range necessary for correct gray scale tracking.
These 2 flags are used during factory adjustment.
OK and Fault - These two flags are included as a check
on the communication line between the MCU and
MC44002l7. The OK flag is permanently wired high and Fault
is permanently wired low. The MCU can use these flags to
verify that the data received is valid.
ACC Active - This flag is high when there is a sufficient
level of burst present in PAL and NTSC modes during the
video back porch period. The flag goes low when the level of
burst falls below a set threshold or if the signal becomes too
noisy. The flag is used to implement a software color killer in
PAL and NTSC and is also available for system identification
purposes. Since in SECAM there is line carrier present
during the gating period, it is quite likely that the ACC will be
on, or will flicker on and off in this mode .
• PAL Identified - Recognizes the line-by-line swinging
phase characteristic of the PAL burst. When this flag is on
together with the ACC flag, this is positive identification for a
PAL signal.
• SECAM Identified - Senses the changing line-by-line
reference frequencies (F01 and F02) present during the back
porch period of the SECAM signal. This flag alone provides
identification that SECAM is being received (MC44002 only).
Excess Peak Beam Current - A voltage threshold is set
on the beam current feedback on Pin 20, which is also used
for the RGB output loops for current sampling. When the
threshold is reached, the flag is set, indicating too high a peak
beam current which may be in only a part of the screen. The
response of the MCU might be to reduce the contrast of the
picture. This flag, together with the Excess Average Beam
Current flag, performs the function of beam limiting. The
exact way in which this is handled is left to the discretion of
the user who will have their own requirements, which may be
incorporated by the way in which the software is written.
* These two flags are set in opposition to one another such that they can never both be on at the same time. This has been done to try to prevent misidentification from occurring. Often It is
very difficult to distinguish between PAL and SECAM especially when broadcast material has been transcoded, sometimes badly, leaving e.g. large amounts of SECAM carrier in a
transcoded PAL signal (also often with noise). With this method the strongest influence will win out making a misidentification much less likely.
MOTOROLA ANALOG IC DEVICE DATA
9-271
9
MC44002 MC44007
APPENDIX A - SYSTEM IDENTIFICATION TABLE
The table below can be used for color standard selection
between the normal PAL (I, BG), SECAM (L, BG) and NTSC
(3.58 MHz - M) standards. Detecting the hybrid VCR
standard (525 lines with 4.4 MHz chrominance) would entail
switching back to the 17.7 MHz crystal in the event of there
being no flag present with the 14.3 MHz crystal. The
MC4400217 could also be used for the PAL M and N
standards that are used in some parts of South America, but
because the subcarrier frequencies differ by some kHz from
the normal, crystals with a different center frequency would
be required.
Table 6. System Identification
Flags from the MC4400217
<576
II
9-272
Lines
ACCOn
0
0
Crystal
(MHz)
Standard Selected
ByMCU
PAL
SECAM
0
0
0
17.7
0
0
1
17.7
SECAM
0
0
1
0
17.7
Kill
0
0
1
1
17.7
12C Bus Error
0
1
0
0
17.7
Kill
0
1
0
1
17.7
SECAM
0
1
1
0
17.7
PAL
0
1
1
1
17.7
12C Bus Error
1
0
0
0
14.3
NTSC Kill
1
0
0
1
14.3
NTSCKili
1
0
1
0
14.3
NTSC Kill
1
0
1
1
14.3
12C Bus Error
1
1
0
0
14.3
NTSC
1
1
0
1
14.3
NTSC
1
1
1
0
14.3
NTSC
1
1
1
1
14.3
12C Bus Error
Kill
,MOTOROLA ANALOG IC DEVICE DATA
MC44002 MC44007
APPENDIX B - 12C BUS AND RGB CONTROL LOOPS WITH MC4400217
The RGB drive DACs cannot be buffered on account of the
chip area that this would take up. This factor has
considerable implications on the way that the 12C data is
written into the MC44002/7 memory. If the data for
Brightness, Contrast, Saturation and Hue are transmitted at
just any time, a disturbance will be visible on the screen.
To overcome this difficulty, a method synchronizing the
MCU to write data only during the field interval has been
developed. This represents something of a limitation, but has
to be used only for the 4 user controls.
Another characteristic of the MC4400217 is that the
Contrast control function is carried out within the RGB
sampling loops. If data is written into the registers during the
time when the RGB loops are taking their samples, then the
situation arises where data is being sampled and changed at
A
the same time. Hence, the loops will inevitably go unstable.
When this happens, the brightness is seen to vary
uncontrollably while the Contrast is changed. The effect has
been described as "loop bounce".
The timing diagram below show the exact situation.
From the start of the field flyback pulse to the beginning of
the RGB sampling, approximately 1.2 ms is available to write
the 12C data. Therefore, with a reasonable safety margin, the
write time should be limited to only about 1.0 ms. This should
not present any serious difficulty since only the data byte has
to be transmitted during this time, and then only for the 4 user
controls.
M
Video Field Interval
o 00 00 0 III 0 0 0 011 IOr-Tl"O""""'O-n-100rr-T0.-----rT""0---'Orr----n-O-""-0--riO
ITTT
Field Flyback
Synchronizing
Pulse
~1.2ms~·1
II
Loop Sampling
Waveform (Pin 20)
R
MOTOROLA ANALOG IC DEVICE DATA
G
B
9-273
MC44002 MC44007
APPENDIX C - A SUGGESTED METHOD FOR OUTPUT LOOPS ADJUSTMENT
II
As described in section 4, the MC44002f7 output loops
stage automatically adjust the dc level of the cathode voltage
(cut-off) and the gain of the signal at the cathode (white
balance). These automatic adjustments replace the
conventional manual adjustments. The only adjustment that
must be carried out, either by hand or automatically using an
"intelligent screwdriver", is for the G2 voltage.
As the G2 voltage is varied, the automatic output loops of
the MC44002f7 will adjust the cathode voltage of the dark
sample level to always obtain the correct dark cathode
current. However, if the G2 voltage is adjusted-too high or too
low, one or more of the DAC's controlling the dc level will
reach the end of their range and the cathode voltage on the
channel will not be correctly adjusted. In order to inform the
operator or machine adjusting the G2 voltage that the control
range has been exceeded, the G2-Up Request or G2-Down
Request flags will be set. These flags are set when anyone
of the dc-DAC's approaches the end of its range. The
threshold for setting the flags lies typically between 15 and
20% of the range from the actual end. Therefore, when a flag
is set, the output loops can still operate correctly. As the gain
of the picture tube varies very little with the G2 voltage, flags
are not provided for the gain-DAC's.
In order to fix a procedure for setting the G2 voltage it is
necessary to consider several points:
- On a given sample, the output currents from the three
channels corresponding to the dark level are all different. The
range of each DAC is about 2.4 mA and varies little from one
channel to another and from one device tQ another. For
reasons of stability and control range we recommend that the
feedback resistor of the high-voltage video amplifier be
39 kQ. this means that the dark cathode voltage range of
each channel is about 94 V (Le. 39 kQ x 2.4 mAl, but the
absolute value of the cathode voltage can vary.
- In a typical application the actual cut-off voltage (Le.
zero cathode current) lies about 10-15 V higher than the dark
cathode current (10 j.1A).
- When the beam--current in the picture tube increases,
the G2 voltage tends to decrease. With the output loops of
the MC44002f7, the cathode voltage is lowered automatically
to compensate, but this effect would normally cause the
values in the dc-DAC's to fall, using up their useful control
range. as high beam current is associated to high contrast, in
the MC4400217 the dc output current (and therefore the
cathode voltage) is reduced directly as the contrast setting is
9-274
increased. In this way as contrast is increased, leading to
higher beam current and lower G2 voltage, the dc-DAC's do
not move much, thus saving range.
- A picture tube can have a difference in cut-off voltage
between guns of up to about 30 V and it is not generally
possible to identify in a particular type and make of tube
which gun has the lowest and which gun has the highest
cut-off voltage. Also, it is generally recommended by the
tube manufacturer to set the cut-off voltage of the highest
gun to a certain value which gives optimum focus
performance.
- As the picture .tube ages, the cathode cut-off voltage
falls. It is therefore best to set the G2 voltage when the tube
is new to give the highest possible cathode cut-off voltage.
Taking into account the above pOints, it is recommended
that the G2 voltage be set up in the following way:
1) Display a black picture with the brightness control to
minimum. (This give minimum beam current and no drop in
G2 voltage.)
2) Set he contrast to maximum. (This causes the dc output
current to be forced',to Ii lower level and the output loops to
compensate by moving towards the top of their range.)
3) Now adjust the G2 voltage so that the G2 Down
Request flag is just turned off. (All the dc-DAC's are towards
the top of their range and the highest one is just at the level to
switch on the flag. Lowering the contrast setting, increasing
the beam current or aging of the tube will cause the output
loops to reduce the values in the dc-DAC's, but the available
range will be a maximum.)
4) With a white picture and contrast set to give the
maximum allowable beam current, check that the G2 Up
Request flag is still off. (This is just to check that the G2
voltage is not falling too much at high beam current, but this
step is not absolutely necessary.)
It is not recommended adjusting the G2 voltage to reach a
specific value of cathode cut-off or dark voltage. The reason
for this is that tolerances of the picture tube, high voltage
video amplifier and the MC44002f7 itself will cause the
, dc-DACs to be set anywhere in their range and perhaps near
the bottom end, leaving no margin for aging and G2 voltage
drop.
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44011
Advance Information
Bus Controlled Multistandard
Video Processor
BUS CONTROLLED
MULTISTANDARD
VIDEO PROCESSOR
The Motorola MC44011, a member of the MC44000 Chroma 4 family, is
designed to provide RGB or YUV outputs from a variety of inputs. The inputs
can be composite video (two inputs), S-VHS, RGB, and color difference
(R-Y, B-Y). The composite video can be PAL and/or NTSC as the MC44011
is capable of decoding both systems. Additionally, R-Y and B-Y outputs and
inputs are provided for use with a delay line where needed. Sync separators
are provided at all video inputs.
In addition, the MC44011 provides a sampling clock output for use by a
subsequent triple AID converter system which digitizes the RGBIYUV
outputs. The sampling clock (6.0 to 40 MHz) is phase-locked to the
horizontal frequency.
Additional outputs include composite sync, vertical sync, field
identification, luma, burst gate, and horizontal frequency.
Control of the MC44011, and reading of status flags, is via an 12C bus.
SEMICONDUCTOR
TECHNICAL DATA
FNSUFFIX
PLASTIC PACKAGE
CASE 777
(PLCC)
44
FBSUFFIX
PLASTIC PACKAGE
CASE 824E
(OFP)
• Accepts NTSC and PAL CompOSite Video, S-VHS, RGB, and R-Y, B-Y
• Includes Luma and Chroma Filters, Luma Delay Lines, and Sound Traps
• Digitally Controlled via 12C Bus
•
441
• R-Y, B-Y Inputs for Alternate Signal Source
• Line-Locked Sampling Clock for AID Converters
ORDERING INFORMATION
• Burst Gate, Composite Sync, Vertical Sync and Field Identification Outputs
• RGBIYUV Outputs can Provide 3.0 Vpp for AID Inputs
Operating
Temperature Range
Device
• Overlay Capability
MC44011FN
• Single Power Supply: 5.0 V, ±5%, 550 mW (Typical)
MC44011FB
TA = 0' to +70°C
Package
PLCC-44
OFP
II
• 44 Pin PLCC and QFP Packages
Representative Block Diagram
Outputs
VCC1
~
Y1
R-Y B-Y
Gnd1
r------1--~----
I
"., , .. ,,""'"''
. '.'
Inputs
-'
R-Y
A.
B-Y
"
Y2
R G 8
Fast
Comm
I
I
:}OU1Puts
1v-1r~~L. . . .--~--,,~~~~u
~r-----------------~
I
r--;;;;;;-'l.-+-f--I
SDLlTo P
scLf
Il
1+----------<;lVCC3
---r__---;r----rS-r---oi.----.!~~--,J-----oGnd3
'-r-__
.....,,=-. To AID Converters
MOTOROLA ANALOG IC DEVICE DATA
9-275
II
Figure 1. Representative Block Diagram
~
~
Inputs
PALINTSCIS-VHS Decoder
r------------------r----------,
. .
.
I
I
I
I
Cj
I
L _ _ _ _ _ _ ..I
Adaptive Sync
Separalor&
Selector
From}
RGB&Y2
Inputs
3:
o
t
Saturation
Conlras!
,\.Blue Gain
,\.RedGain
Brighlness
,\.Red DC f--I----'
,\.BlueDC
o....
....
--------~~~!!~Bus Control & Flag Status Read
s:
a
::u
o
~
:J>
Z
:J>
r-
oI:)
(';
c
m
::so
m
c
~
J>
SCl}
SDl
ToJlP
MC44011
ELECTRICAL CHARACTERISTICS (The tested electrical characteristics are based on the conditions shown in Table 1 and 2.
Composite Video input signal = 1.0 Vpp, composed of: 0.7 Vpp Black-to-White; 0.3 Vpp Sync-to-Black; 0.3 Vpp Color Burst. VCCl = VCC2
= VCC3 = 5.0 V, Iref = 32 itA (Pin 9), unless otherwise noted.)
Table 1. Control Bit Test Settings
Name
Value
$77-7
S-VHS-Y
Control Bit
Function
$77-2
Ll GATE
a
a
a
a
a
a
$77-1,0
CB1,CAl
1,1
$78-7
36168 itS
$78-6
CalKili
a
a
$79-7,6
HI, VI
1,1
Xtal
-
0= 17.7 MHz crystal selected, 1 = 14.3 MHz crystal selected.
Normal
$77-6
S-VHS-C
$77-5
FSI
$77-4
L2GATE
$77-3
BLCP
$7A-7
$7A-6
$7B-7,6
$7C-7
SSD
a
Tl, T2
1,1
SSC
a
Composite Video input selected.
Composite Video input selected.
50 Hz Field Rate selected.
PLL #2 Gating enabled.
Clamp Pulse Gating enabled.
Vertical Gating enabled.
Vertical section Auto-Countdown mode
Time from beginning of Line 4 to Vertical Sync is 36 its.
Horizontal Calibration Loop enabled.
Normal
Sound Trap Notch filter set to 5.5 MHz (with 17.7 MHz crystal).
Permits PAL and NTSC selection.
$7C-6, $70-6
SSA, SSB
-
$70-7, $7E-7, 6
Pl,P3,P2
1,1,1
Sets Luma Peaking at
$7F-7,6,$8D-6
03,01,02
0,0,0
Set Luma Delay to minimum
$8D-7
RGBEN
$81-7
Y2EN
a
a
Y2 input (Pin 29) deselected
0, 1 = PAL decoding, 1,0 = NTSC decoding
a dB.
Fast Commutate input can enable RGB inputs.
$81-6
Yl EN
1
Yl luma path from PAUNTSC decoder selected.
$82-7
YUVEN
RGB output mode selected
$82-6
YXEN
$83-7
L2 Gain
a
a
a
Set PLL #2 Phase/Frequency detector gain high.
$83-6
L1 Gain
1
Set PLL #1 Phase Detector gain high.
$84-7
H Switch
a
Set Horizontal Phase Detector filter switch open.
$84-6
525/625
-
a = 625 lines (PAL), 1 = 525 lines (NTSC)
$85-7
Fosc + 2
CSync
a
a
Select direct VCO output from PLL #2.
$85-6
$86-7
Vin Sync
1
Composite Video inputs (Pin 1 or 3) Sync Source selected.
$86-6
HEN
$87-7
Y2 Sync
a
a
Y2 sync source not selected.
Disable luma matrix from RGB inputs.
II
16 Fh output selected at Pin 13.
Enabled Horizontal Timebase.
$88-7
V2IVl
1
Select Video 1 input (Pin 1).
$88-6
RGB Sync
a
RGB inputs Sync Source not selected.
Table 2. DAC Test Settings
DAC
Value
Function
DAC
Value
$78
32
R-Y/B-Y Gain
$82
32
Red Contrast Trim
Function
$79
32
Sub Carrier Phase
$83
32
Blue Brightness Trim
$70
00
Blue Output DC Bias
$84
32
Main Brightness
$7E
00
Red Output DC Bias
$85
32
Red Brightness Trim
$7F
63
Pixel Clock VCO Gain
$86
32
Saturation (Color Dill.)
$80
32
Blue Contrast Trim
$87
16
Saturation (Decoder)
$81
32
Main Contrast
$88
32
Hue
NOTE:
Currents out of a pin are designated -, and those into a pin are designated +.
MOTOROLA ANALOG IC DEVICE DATA
9-2n
MC44011
MAXIMUM RATINGS
Symbol
Value
Unit
VCCl
VCC2
VCC3
-0.5 to +6.0
-0.5 to +6.0
-0.5 to +6.0
Vdc
-
±D.5
Vdc
Input Voltage: Video 1, 2, SCL, SDL
15 kHz Return
R-Y, B-Y, Y2, RGB, FC
Yin
-0.5, VCCl +0.5
-0.5, VCC3 +0.5
-0.5, VCC2 +0.5
Vdc
Junction Temperature (Storage and Operating)
TJ
-65.to+150
°c
Rating
Power Supply Voltage
Power Supply Difference
(Between any two VCC pins)
NOTES: 1. Devices should nol be operated at these IimHs. The "Recommended Operating Conditions"
table provides for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Power Supply Voltage
Power Supply Difference (Between any two VCC pins)
Input Voltage: Video 1,2 (Sync-White)
Chroma (S-VHS Mode)
Y2
RGB
R-Y, B-Y (Pins 30,31)
15 kHz Retum
SCL, SDL
FC
Burst Signal
Sync Amplitude
Output Load Impedance to Ground: RGB (Pull-Up
B-Y,R-Y
II
=390 0)
Yl
. Pull-Up Resistance at Vertical Sync (Pin 4)
Source Impedance: Video 1, 2
Pins 26 to 31
Min
Typ
Max
Unit
VCC1, 2, 3
4.75
5.0
5.25
Vdc
tNCC
-0.5
O.
0.5
Vdc
Vin
0.7
1.0
1.4
1.2
1.4
1.0
1.8
Vpp
VCC3
VCCl
VCC2
560
Vdc
-
-
0.7
0.5
0
0
0
0
30
60
1.0
0.7
280
300
RLRGB
RLCD
RLYl
1.0
10
-
1.0
-
RVS
1.0
10
-
kn
-
0
0
-
1.0
1.0
kn
MHz
-
-
VCCl
mVpp
mVpp
00
kn
00
00
fpx
-
2.0 to 45
-
PW15k
0.2
-
45
its
12C Clock Frequency
fl2C
-
-
100
kHz
Reference Current (Pin 9)
Iref
-
32
-
ItA
TA
0
-
70
°C
Typ
Max
Unit
95
9.0
6.0
110
115
12
8:0
135
mA
Pixel Clock Frequency (Pin 18, see PLL #2 Electrical Characteristic)
15 kHz Return Pulse Width (Low lime)
Operating Ambient Temperature
NOTE:
AlllimHs are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCCl = VCC2 = VCC3 = 5.0 V, unless otherwise noted.)
I
Characteristics
I·
Min
I
POWER SUPPLIES
Power Supply Current (VCC
9-278
=5.0 V)
Pin 40
Pin 23
Pin 19
Total
75
6.0
3.5
85
MOTOROLA ANALOG IC DEVICE DATA
MC44011
ELECTRICAL CHARACTERISTICS (continued) (TA
I
=25°C, VCCl =VCC2 =VCC3 =5.0 V, unless otherwise noted.)
Characteristics
I
Min
I
Typ
I
Max
Unit
-
dB
-
Vdc
-10
I1A
-
dB
PAUNTSC/S-VHS DECODER
Video 1, 2 Inputs
Crosstalk Rejection, f 1.0 MHz
(Measured at Yl output, Luma Peaking 0 dB,
DC Level: @ Selected Input
@ Unselected Input
Clamp Current
Sound Trap Rejection (See Figures 14 to 23)
With 17.7 MHz Crystal: @ 6.5 MHz (n, T2
@ 6.0 MHz (n, T2
@ 5.5 MHz (Tl, T2
@ 5.74 MHz (n, T2
With 14.3 MHz Crystal: @ 4.44 MHz (n, T2
=
=
$77-7
=1)
=00)
=10)
=11)
=01)
=11)
R-Y, B-Y Outputs (Pins
Output Amplitude (with
Saturation (DAC 87)
Saturation (DAC 87)
Saturation (DAC 87)
41,42)
100% Saturated Color Bars)
00
16
63
=
=
=
DC Level During Blanking
Hue Control- Minimum Phase (DAC 88
- Maximum Phase (DAC 88
=00)
=63)
Nominal Saturation (with respect to Yl Output, Note 1)
R-Y/B-Y Ratio: Balance (DAC 78)
Balance (DAC 78)
Balance (DAC 78)
=63
=32
=00
Output Amplitude Variation as Burst is varied from 80 mVpp to 600 mVpp
=
Color Kill Attenuation ($7C-7, 6 and $7D-6 011)
Crosstalk with respect to Yl Output (@ 1.0 MHz)
Chroma Subcarrier Residual
(Measured at Yl Output, with 17.7 MHz Crystal)
f Subcarrier
2nd Harmonic Residual
4th Harmonic Residual
(Measured at R-Y, B-Y Outputs, with 17.7 or 14.3 MHz Crystal)
f Subcarrier
2nd Harmonic Residual
4th Harmonic Residual
=
=
Yl Luma Output (Pin 33)
Clamp Level
Output Impedance
20
40
-
2.8
0.7
-20
-30
15
15
10
15
-
-
30
30
43
26
35
-
-
-
1.8
<1.0
1.6
3.0
-
2.4
-
-
-30
30
-
100
-
%
1.35
0.98
0.60
1.69
1.27
0.77
2.06
1.58
0.96
VN
-
3.0
-
dB
-
-
-
mVpp
Vpp
Vdc
Deg
-27
40
-20
-
-
25
4.0
12
60
12
30
5.0
5.0
15
20
20
50
1.1
300
1.8
Vdc
-
g
1.1
1.1
1.2
VN
-
2.8
-
MHz
5.0
8.0
10
dB
-
0
2.0
-
-
690
1040
594
876
-
-
0.4
-
dB
mVpp
=
Composite Video Mode ($77-6, 7 00)
Output Level versus Input Level
Delay 000, Peaking 111, f 100 kHz
Delay Min-to-Max, Peaking Min-to-Max
=
=
=
=
=
-3.0 dB Bandwidth (17.7 MHz Crystal, PAL Decoding selected,
Sound trap at 6.5 MHz, Peaking off)
Peaking Range ($70-7, $7E-6/7
Sound trap at 6.5 MHz)
=000 to 111, @ 3.0 MHz, with 17.7 MHz Crystal,
Overshoot with Minimum Peaking
Differential Non-linearity (Measured with Staircase)
Delay (Pin 1 or 3 to 33)
With 14.3 MHz Crystal: Minimum
Maximum
With 17.7 MHz Crystal: Minimum
Maximum
1.0
-
-
-
-
%
%
ns
-
NOTE: 1. This spec indicates a correct output ampltlude at Pins 41 and 42, with respect to Y1 output. For standard color bar inputs, the output ampltlude is
between 1.5 and 1.7Vpp. wtththe settings in Tables 1 and 2.
MOTOROLA ANALOG IC DI:VICE DATA
9-279
II
MC44011
ELECTRICAL CHARACTERISTICS (continued) (TA = 25°C, VCC1 = VCC2 = VCC3 = 5.0 V, unless otherwise noted.)
I
Characteristics
I
Min
I
Typ
I
Max
Unit
1.2
-
VN
MHz
-
dB
PAUNTSC/s-VHS DECODER
S-VHS Mode ($77-6, 7 = 11)
Output Level versus Input Level (Delay = Min-to-Max)
-3.0 dB Bandwidth (17.7 MHz crystal, PAL Decoding selected,
Sound trap at 6.5 MHz)
YIC Crosstalk Rejection
Delay (Luma input to Pin 33)
14.3 MHz Crystal: Minimum
Maximum
17.7 MHz Crystal: Minimum
Maximum
Crystal Oscillator
PLL Pull-in range with respect to Subcarrier Frequency
(Burst Level 2: 30 mVpp): with 17.7 MHz Crystal
with 14.3 MHz Crystal
4fsc Filter (Pin 44) DC Voltage
@ 14.3 MHz
@ 17.7 MHz
No Burst present
II
DC Voltages
System Select (Pin 34)
NTSCMode
(SSA = 1, SSB = 0, SSC = 0, SSD = 0)
PAL Mode
(SSA=O, SSB = 1, SSC= 0, SSD=O)
Color Kill Mode
(SSA = 1, SSB = 1, SSC = 0, SSD = 0)
External Mode
(SSA = X, SSB = X, SSC = 1, SSD = 0)
Ident Filter (Pin 43)
NTSC Mode
PAL Mode
No Burst present
ACC Filter (Pin 2)
No Burst present
Threshold for ACC Flag on
Burst = 50 mVpp
Burst = 280 mVpp
System Select Output Impedance
1.0
-
1.1
4.5
20
40
-
-
395
745
350
632
-
±350
±300
-
2.4
3.5
1.3
-
-
ns
-
Hz
-
-
Vdc
Vdc
1.5
0
3.7
1.2
-
1.75
0.075
0.075
4.0
1.6
1.5
0.2
2.0
0.4
4.3
1.8
-
-
0.25
1.2
1.4
1.7
-
40
100
kQ
2.0
3.0
0.5
6.0
2.0
-
Vpp
.%
MHz
-
Vdc
0.8
1.6
-
COLOR DIFFERENCE SECTION
RGBNUV Outputs
Output Swing, Black-to-White (DAC $81 = 63)
THO (RGB Inputs to RGB Outputs @ 1.0 MHz, 0.7 Vpp)
-3.0 dB Bandwidth
Clamp Level
RGB Outputs ($70, 7E = 00)
UV Outputs ($70, 7E = 32)
Red, Blue Clamp Level Change (DACs $70, 7E varied from 00 to 63)
0.85
1.4
2.3
1.8
Crosstalk Rejection
Among RGB Outputs @ 1.0 MHz
Y1 toY2
From RGB Outputs to Y1 or Y2
20
20
20
40
40
40
-
Input Black Clamp Voltage at Y2, B-Y, R-Y, and RGB
2.4
3.0
3.6
Vdc
-
0.5
-7.5
0
50
90
-
Vdc
-
IlA
Fast Commutate Input (Pin 25)
Switching Threshold Voltage
Input Current @ Yin = 0 V
Input Current @ Yin = 5.0 V
Timing: Input Low-to-High (RGB Enable)
Input High-to-Low (RGB Disable)
9-280
-
-
2.4
dB
ns
-
MOTOROLA ANALOG IC DEVICE DATA
MC44011
ELECTRICAL CHARACTERISTICS (continued) (TA =25°C, VCC1
I
=VCC2 =VCC3 =5.0 V, unless otherwise noted.)
Characteristics
I
Min
I
Typ
I
Max
Unit
COLOR DIFFERENCE SECTION
Contrast (Gain)
Y1 to RGB (DAC $81 =32, DAC $86 =00)
Y2 to RGB (DAC $81 = 32, DAC $86 =00)
Green In (Pin 27) to Green Out (Pin 21) with YX Enabled
($82-6 = 1, DAC $81 and DAC $86 =32)
Red-to-Green and Blue-ta-Green Gain Ratio
RGB Inpul to RGB Output with YX Not Enabled
($82-6 =0, DAC $81 and DAC $86 =32)
Ratio (DAC $81 = 00 versus 32)
Ratio (DAC $81 =63 versus 32)
Red and Blue Trim Control (DACs $80, 82 varied from 00 to 63)
Saturation (Average of R, G, B saturation levels with respect to Luma)
Inputs at Pins 29 to 31 (DAC $86 = 32)
Ratio (DAC $86 =00 versus 32)
Ratio (DAC $86 =63 versus 32)
Inputs at Pins 26 to 28 (DAC $86 =32, $82-6 = 1)
VN
1.9
1.8
1.8
2.4
2.3
2.3
3.0
2.8
2.4
0.8
2.0
1.0
2.6
1.2
3.2
1.5
±5.0
0.2
2.0
±30
0.4
2.5
50
90
±SO
%
%
Vdc
-
-
150
70
170
125
130
5
190
180
±D.3
±D.05
±D.5
±0.3
±D.7
±D.6
-0.21
-0.56
-0.19
-0.51
-0.17
-0.46
0.28
0.57
0.09
0.30
0.59
0.11
0.32
0.61
0.13
62.5
62.5
64.0
63.5
65.5
65.5
~s
VCO minimum period (Pin 11 Voltage at 1.2 V)
VCO maximum period (Pin 11 Voltage at 2.8 V)
56
66
59.5
69.5
62
72
~
VCO Control Gain factor
5.0
8.5
12
~
15
0.32
50
0.38
85
0.44
I!AI~
-
16
-
~
-
10
<5.0
1.0
100
mV
Brightness
Black Level Range (Brightness = 00 to 63 with respect to Brightness setting of 32)
Red and Blue Trim Control (DACs $83, 85 varied from 00 to 63)
Color Coefficients
G-Y Matrix Coefficient versus B-Y
G-Y Matrix Coefficient versus R-Y
YX Matrix (Inputs at Pins 26 to 28, $82-6 = 1):
Yversus R
Yversus G
Yversus B
HORIZONTAL TIME BASE SECTION (PLL #1)
Free-Running Period (Calibration mode in effect, Bit $86-6 = 1)
17.7 MHz Crystal selected ($84-6 = 0)
14.3 MHz Crystal selected ($64-6 = 1)
Phase Detector Current
High Gain ($83-6 = 1)
Low Gain-to-High Gain Current Ratio
Noise Gate Width ($77-2
=0, Low Gain, see Figure 26)
Horizontal Filter Switch (Pin 12)
Saturation Voltage (112 =20 ~)
Dynamic Impendance ($84-7 = 1)
Parallel Resistance ($84-7 =0)
Pins 8, 13, 14 Output Level
High (10 =-40 ~A)
Low (10 =800 ~)
Burst Gate (Pin 8) Timing (See Figures 25, 27)
Rising edge from Sync leading edge (Pins 1, 3)
Rising edge from Sync center (Pins 26 to 29)
Pulse Width
16Fh Output (Pin 13) Timing (Bit $85-6 =0) (See Figures 25, 27)
Rising edge from Fh rising edge
Duty Cycle
Composije Sync Output (Pin 13) Timing (Bit $85-6 = 1)
Input Sync center to Output Sync center (Pins 1, 3)
Input Sync center to Output Sync center (Pins 26 to 29)
MOTOROLA ANALOG IC DEVICE DATA
-
0.6
2.4
-
4.5
0.1
-
~A
kn
-
Mn
-
Vdc
0.8
~s
4.4
3.0
-
-
5.6
2.5
3.5
1.3
50
0.95
0.4
6.8
4.0
-
-
~
%
~
9-281
II
MC44011
ELECTRICAL CHARACTERISTICS (continued) (TA = 25'C, VCCl = VCC2 = VCC3 = 5.0 V, unless otherwise noted.)
I
Characteristics
I
Min
I
Typ
I
Max
Unit
-
itS
ns
HORIZONTAL TIME BASE SECTION (PLL #1)
Fh Reference (Pin 14) Timing (See Figures 25, 27)
Rising edge from Sync center (Pins " 3)
Rising edge from Sync center (Pins 26 to 29)
Duty cycle
Sandcastle Output (Pin 35, see Figures 25, 27)
Output Vo~age - Levell
Output Voltage - Level 2
Output Voltage - Level 3
Output Voltage - Level 4
Rising edge from Sync center (Pins " 3)
Rising edge from Sync center (Pins 26 to 29)
High Time
Level 2 Time
Reference Voltage @ Pin 9 (Iref = 32
ItA)
-
-
1.3
650
50
-
%
Vdc
3.7
2.8
4.3
3.2
-
I1S
-
4.0
3.0
1.55
0.07
-2.6
-3.3
6.0
5.0
1.0
1.2
1.4
VdC
-
2.0
4.0
-
-
-
-
PHASE-LOCKED PIXEL CLOCK SECTION (PLL #2)
VCO Frequency @ Pin 18
Minimum (Pin 16 = 1.6 V, $85-7 = 1)
Maximum (Pin 16 = 4.0 V, $85-7= 0)
30
45
60
VCO Up (Flag 19) Threshold Voltage @ Pin 16
VCO Down (Flag 20) Threshold Voltage @ Pin 16
1.5
3.1
1.7
3.3
1.9
3.5
Vdc
VCO Control Voltage Range @ Pin 16
VCO Control Gain factor ($7FDAC = 00, $85-7 = 0)
1.2
4.0
8.0
3.8
12
Vdc
MHzIV
Charge Pump Cu~rent (Pin 16)
High Gain ($83-7 = 0)
Current Ratio
Low Gain-to-High Gain
25
50
75
ItA
0.3
0.4
0.5
I!AlItA
-
3.9
0.15
7.0
17
5.0
8.0
-
Vdc
1.5
Vdc
ns
Pixel Clock Output (Pin 18) (Load = 3 FAST TTL loads + 10 pF)
Output Voltage - High
Output Voltage - Low
Rise Time @ 50 MHz
Rise Time @ 9.0 MHz
Fall Time @ 50 MHz
Fall Time @ 9.0 MHz
15 kHz Return (Pin 15)
Input Threshold Voltage
Falling edge from Fh rising edge
Minimum Input Low Time
-
-
-
MHz
-
200
-
-
60
ns
VERTICAL DECODER
43.3
-
122
Hz
Vertical Sync Output
Saturation Voltage (10 = 800 ItA)
Leakage Current @ 5.0 V (Output high)
-
0.1
-
0.8
40
ItA
Timing from Sync polarity reversal to Pin 4 falling edge (See Figures 33, 34)
($78-7=0)
($78-7 = 1)
"
32
62
36
68
40
74
490
500
510
I1S
2.4
4.5
0.1
Fig. 33, 34
-
Vdc
Vertical Frequency Range
Vertical Sync Pulse Width (Pin 4, NTSC or PAL)
Field Ident (Pin 7)
Output Voltage - High (10 = -40 itA)
Output Voltage - Low (10 = 800 ItA)
Timing
V
I1S
-
0.8
-
HORIZONTAL SYNC SEPARATOR
Sync Slicing Levels
From Black Level
9-282
(Pins " 3)
(Pins 2610 29)
MOTOROLA ANALOG IC DEVICE DATA
MC44011
PIN FUNCTION DESCRIPTION
FB
FN
QFP
PLCC
Representative Circuitry
(Pin numbers refer to PLCC package)
Pin
39,41
i-.-->-.:J-
1,3
Video
Inpul
0.47
~I--:l"""""""
1.-1
47 PFI
OMI
f
~~
40
r
2
~
IL ________
· ~-- _
r'-~
I
I
I
0.1
20k
Description
(Pin numbers refer to PLCC package)
Video Input 1 & 2 - Video 1 (Pin 1) and Video 2
(Pin 3) are composite video inputs. Either can be
NTSC or PAl. Input impedance is high, termination
must be external. Also used for the luma and chroma
components of an S-VHS signal. Selection of these
inputs is done by software. External components
protect against ESD and noise.
ACC Filter - A 0.1 IlF capacitor at this pin filters the
feedback loop of the chroma automatic gain control
amplifier. Input chroma burst amplitude can be
between 30 and 600 mVpp.
h-- -
2
!
L _________ _
42
4
5.0~~--
i
Vertical Sync
?----
I
_
L_':"' __ _
43
5
F~MCU~----
Vertical Sync Output - An open collector output
requiring an external pull-up. Output is an active low
pulse, 500 Ils wide, occurring each field. liming of this
pulse depends on Bit $78-7.
SCL - Clock for the 12C bus interface. See Appendix C
for specifications. Maximum frequency is 100kHz.
L-2'"_____ _
44
r
6
ToiFromMCU
180k
~--
i
~---
SOL - Bidirectional data line for the 12C bus interface.
As an output, it is an open collector. (Wr~e Address
$8A, Read Address $8B)
_____ _
L_~
i~OOk
7
I
II-
Fieldlo4
Field 10 - TTL level output indicating Field 1 or Field 2.
Polarity depends on state of Bit $78-7 (Vertical Sync
Delay). See Table 11 and Figure 33 and 34.
--
I
12k
IL ________
II_
2
8
(Same as Pin 7)
3
5.0
9
r=-~------
110k
2.21lF /I
0.01
4
10
J
9
1
I
I
(' 20k '1
IL ________
~8.0k
_~
(See power distribution diagram at the end of this section.)
MOTOROLA ANALOG IC DEVICE DATA
Burst Gate - TTL level output used for external
clamps, as well as internally. Pulse is active high,
~ 3.5 !lS wide, w~h the rising edge ~ 3.0 !lS after
center of selected incoming sync pulse.
Reference Current Input - Current supplied to this
pin, typically 32 IlA from 5.0 V through a 110 k!l
resistor, is the reference current for the calibration
circu~. Noise filtering should be done at the pin.
Voltage at this pin is typically 1.2 V.
Quiet Ground - Ground for the horizontal PLL filter
(PLL#1) at Pin 11.
9-283
II
MC44011
PIN FUNCTION DESCRIPTION (continued)
FB
FN
QFP
PLCC
Representative Circuitry
(Pin numbers refer to PLCC package)
Pin
5
r----------
11
I
I
Description
(Pin numbers refer to PLCC package)
H Filter - Components at this pin filter the output of
the phase detector of PLL #1. This PLL becomes
phase-locked to the selected incoming horizontal
sync. External component values are valid for NTSC
and PAL systems.
100 k
0.1
6
H Filter Switch - An internal switch-to-ground which
permits altering the filtering action of the components
at Pin 11.
12
12 t--..............--,
rL
470p F T
L--.[J1J
L_~
7
8
9
_____ _
(Same as Pin 7)
16 FhlCSync - A TTL level output from PLL #1. This
pin provides either a square wave equal to Fh x 16
(~250 kHz), or composite sync, depending on the
setting of Bit $85-6.
(Same as Pin 7)
Fh Reference - A TTL square wave output which is
phase-locked to the selected incoming horizontal sync.
The rising edge occurs ~ 1.3 ~ after sync center.
13
14
r---------
15
I
I
15 kHz
Return
11
10k
20k
15
I
I
I
15 kHz Return - This TIL input receives the output of
an external frequency divider which is part of PLL #2
(Pixel Clock PLL). This signal will be phase and
frequency-locked to the Fh signal at Pin 14. If PLL #2
is not used, this pin should be connected to a 5.0 V
supply.
6.Ok
L ...... _______ _
10
r:-------------
16
I
I
I
11
12
17
(See power distribution diagram at the end of this section.)
r---------
18
I
I
Pixel
Clock
Output
9-284
200
I
PLL #2 Filter - Components at this pin filter the output
of the phase detector of PLL 2. This PLL becomes
phase-locked to the Fh signal at Pin 14.
Recommended values for filter components are
shown. External components should be connected to
ground et Pin 17. If PLL #2 Is not used, this pin should
be grounded.
Gnd3 - Ground for the high frequency PLL #2. Signals
at Pins 15 to 19 should be referenced to this ground.
Pixel Clock Output - Sampling clock output (TTL) for
external AID converters, and for the external frequency
divider. Frequency range at this pin is 6.0 to 40 MHz.
18
I
I
IL ________ _
MOTOROLA ANALOG IC DEVICE DATA
MC44011
PIN FUNCTION DESCRIPTION (continued)
FB
FN
QFP
PLCC
Representative Circuitry
(Pin numbers reter to PLCC psckage)
Description
(Pin numbers reter to PLCC psckage)
(See power distribution diagram at the end of this section.)
VCC3 - A 5.0 V supply (±5%), for the high frequency
PLL #2. Decoupling must be provided from this pin to
Pin 17. Ripple on this pin will affect pixel clock jitter.
Pin
13
14
19
20
Color
5.0 V
-,
&Gain~6k
I
390
Brighlness
+
20
-
I
__________
15
OUlput
~..J
G/Y Output - Green (in RGB mode), or Y (in YUV
mode), output from the color difference stage (same
as Pin 20).
21
(Same as Pin 20)
16
Btu Output - Blue (in RGB mode), or B-Y (in YUV
22
mode), output from the color difference stage (same
as Pin 20).
(Same as Pin 20)
17
(See power distribution diagram at the end of this section.)
VCC2 - A 5.0 V supply (±5%), for the color difference
stage. Decoupling must be provided from this pin to
Pin 24.
(See power distribution diagram at the end of this section.)
Gnd2 - Ground for the color difference stage. Signals
at Pins 20 to 31 should be referenced to this pin.
23
18
24
19
25
~
IL ____ _
r
FC - Fast Commutate swttch. Taking this pin high
(TTL level) connects the RGB inputs (Pins 26 to 28)
to the RGB outputs (Pins 20 to 22), permitting an
overlay function. The switch can be disabled in
software (Bit $80-7).
__
25
20,21,
22
26,27,
28
R,G, B
Inputs
23
>--1
r-r----....--
30,31
>--1
I i-+--+-~_\~~f__[J
IL __________
1~~0-k _
r
32
__
~
I
0.47
Blue (26), Green (27). Red (28) Inputs - Inputs to
the color difference stage. Designed to accept
standard analog video levels, these input pins have a
clamp and sync separator. They are selected with
Pin 25 or in software (Bit $80-7).
V2 Input - Luma #2/Composite sync input. This
luma input to the color difference stage is used in
conjunction with auxiliary color difference inputs,
and/or as a sync input. Clamp and sync separator
are provided.
>--1
R-Y, B-Y
Inputs
26
IL __________
4;"-- 1~~~;_
29
Y2
Input
24,25
RN Output - Red (in RGB mode), or R-Y (in YUV
mode), output from the color difference stage. A
pull-up (3900) to 5.0 V is required. Blank level is
~ 1.4 Vdc. Maximum amplitude is ~ 3.0 Vpp,
black-to-white.
~
--
B-V (30). R-V (3t) Inputs -Inputs to the color
difference stage. Designed for standard color
difference levels, these inputs can be capacitor
coupled from the color difference outputs, from a delay
line, or an auxiliary signal source. Input clamp is
provided.
VI Clamp - A 0.47 IlF capacitor at this pin provides
clamping for the Luma #1 output.
32
IL ______
-- _
MOTOROLA ANALOG IC DEVICE DATA
9-285
II
MC44011
PIN FUNCTION DESCRIPTION (continued)
FB
FN
QFP
PLCC
Pin
27
Representative Circuitry
(Pin numbers refer to PLCC package)
33
~
~
~
r-------I
V1
Output
28
34
35
__
34
+
L ______
I
I
Sandcastle
Pulse
30,32
---
36,38
*
__
35
+
L ______
14.3MHz 1
¢20j.lA
>_
L ________
--
17.7 MHz I
I
---
R
R = 400 a at Pin 38
R = 300 a at Pin 36
II
31
37
39
34
40
35
41
System Select - A multi-level dc output which
indicates the color decoding system to which the
PAUNTSC detector is set by the software. This output
is used by the MC44140 chroma delay line.
Sandcastle Pulse - A multi-level timing pulse output
used by the MC44140 chroma delay line. This pulse
encompasses the horizontal sync and burst time.
I
dl
33
Y1 Output - Luma #1 output. This output from the
PAUNTSC/S-VHS decoder is the luma component of
the decoded composite video at Pin 1 or 3. It is
intemally directed to the color difference stage.
L _____
I
System
Select
29
33
.I
Description
(Pin numbers refer to PLCC package)
Xtal 2 (36), Xtal 1 (38) - Designed for connection of 4x
subcarrier color crystals. Selection is done in software.
The selected frequency is used by the PAUNTSC
detector; system identifier; all notches and traps; delay
lines; and the horizontal calibration circuit.
The crystal frequency should be:
14.3 MHz at Pin 36 for NTSC,
17.7 MHz at Pin 38 for PAL.
(See Table 17 for crystal specifications)
No Connect - This pin is to be left open.
(See power distribution diagram at the end of this section.)
Ground 1 - Ground for all sections except PLL #2
and the color difference stage.
(See power distribution diagram at the end of this section.)
VCC1 - A 5.0 V (±5%), supply to all sections except
PLL #2 and the color difference stage.
r
~
--
I
B-V
---I
r
41
!
B-Y Output - Output from the PAUNTSC decoder, it
Is typically capacltor-coupled to a delay line or to the
B-Y input. This pin Is clamped, and filtered at the
color subcarrler frequency, 2x, and 8x that frequency.
L _______
36
42
37
43
(Same as Pin 41)
r
I
0.1
.,p
9-286
I
I
43
~
~
R-Y Output - Output from the PAUNTSC decoder.
Ident Filter - A 0.1 j.LF capacitor filters the system
Identification circuit In the NTSC/PAL decoder.
---
• --
h---'
!L _________
MOTOROLA ANALOG IC DEVICE DATA
MC44011
PIN FUNCTION DESCRIPTION (continued)
FB
FN
QFP
PLCC
Representative Circuitry
(Pin numbers refer to PLCC package)
Pin
38
r
44
R·
I
I
I
1
2200 pF
4,11,
13,17,
18,33,
34
10,17,
19,23,
24,39,
40
44
~
Description
(Pin numbers refer to PLCC package)
Crystal PLL Filter - Components at this pin filter the
PLL for the crystal chroma oscillator circuit.
---
5
rr
~
--
!L _________
rr__ ~~tf__ ~o~rr
VCCI
VCC2
7.0 V
VCC3
Power Distribution - The three VCC pins must be
externally connected to 5.0 V (±5%) supply. The four
grounds must be externally tied together, preferably to
a ground plane.
(Dashed lines indicate substrate connection.)
II
MOTOROLA ANALOG IC DEVICE DATA
9-287
MC44011
Luma Frequency Response (14.3 MHz) Crystal, (4.5 MHz) Sound Trap
Figure 2. Composite Video Mode
aw
10
.....
I
L
.!.
,
........
0
:>
~
w -10
I",
I.
;;;:
!5w
a:
-20
OOU
010
0
111
~
w -10
>
~
w -20
-40
Sound Trap = 1,1 I - -
"C
5.0
\
\I
!;( -30
z
«
Peaking- I - -
a:
!Xl
-50
0.1
~
aw
.VI
;:::
«
1-
~1.
!;;: -30
z
~ -10
w
aw
0
~,
'\
l!:!
;:::
-20
~
!B
t,
I'
-20
I
z
Sound Trap = 1,1 r--3.0
a:
«
~
w -10
-
;;;:
!5
Figure 5. S-VHS Mode
10
5.0
7.0
FREQUENCY (MHz)
"C
-50
0.1 "
10
Sound Trap = 1,1
~II pea~ing Se1tings
"
-40
!Xl
1.0
3.0
t,
I
5.0
7.0
FREQUENCY (MHz)
10
Luma Frequency Response (17.7 MHz) Crystal, (5.515.75 MHz) Sound Trap
Figure 6. Composite Video Mode
@
.......
0
;;
~ -10
~
l!:!
;:::
10
~
"\.'
~.
~\ r,...
,\\.'. / - ~ 010
-20
111
\V.
v
1- -
i 1,1
1.0
3.0
5.0
7.0
JL
;;
~ -10
~
a:
""" \
~
......
0
"
~\JI
~\\IIJ "'\
-20
\\"/1
'"/
\I
1
>=
!;( -30
z
«
'\ l\ {
2:
~
w
aw
1'..'\
~ -10
w
a:
Figure 9. S-VHS Mode
10
/I
1
"
"
-40
r-- ooU
010 Peaking
'r- ~
" 111 1-r---=-I--
~
w
a:
3.0
5.0
«=
m
Sound Trap = 1,0 _
Ali peakiig setttgs _
-40
-50
0.1
10
r--.
r
/
1
I
"C
1
1.0
\
!;( -30
z
1
"C
-50
0.1
....
0
~
w -10
>
1.0
3.0
t, FREQUENCY (MHz)
5.0
7.0
10
t, FREQUENCY (MHz)
Luma Frequency Response (17.7 MHz) Crystal, (6.5 MHz) Sound Trap
Figure 10. Composite Video Mode
-,
10
fa0
....
0
:>
~ -10
w
~
w
!;(
~
-30
ooU-1-Peaking
I- 010
1\"/
W
11 11 - 1 - -
-40
3.0
5.0
~
w -20
\ I'
>=
\1
\I
'"
7.0
,
-40
"C
10
I
1.0
0.1
3.0
~
~ -20
w
>
~
~
>=
!;(
1
"
-15
-25
-
-30
z
~
lei
-35
-40
3.0
I,
/.
'- Gainal
'- Peaking = 000
001
100
101
010
on
110
1111
""\. 'l/.:
/ 1(//
/~ Wr
'i'//': 1/'\
~L/
'/
'/
I
7.0
10
Figure 13. (4.43 MHz) Chroma Notch
1
Sound Trap =1,1 14.3 MHz Crystal -
..........
I
t, FREQUENCY (MHz)
Figure 12. (3.58 MHz) Chroma Notch
fa
5.0
II
Sound Trap =0,0
All Peaking Settings
-50
t, FREQUENCY (MHz)
-10
\
a:
~
-50
1.0
-10
z
SOUid Trap, = 0,0
0.1
~
-"
1'--
!;( -30
,I
\I
z
~
lei
:>
~
~\"J
-20
a:
>=
fa0
."'\1
A
, l\
~
1\\ HA'
2:
Figure 11. S-VHS Mode
10
/
"
-
f0a
-10
-15
::;:
~ -20
~
~w
a:
/
-25
>=
!;( -30
L
~
-35
lei
3.5
t, FREQUENCY (MHz)
MOTOROLA ANALOG IC DEVICE DATA
4.0
1
1
I
Sound Trap 1,1 17.7 MHz Crystal -
=
~
-40
4.0
'""'-
i""'...
\.
Galnal
Peaking = 000
~
~
./
~ '%:""
/
7..-1
r001
100 ~ -j/L
101
010.J
011 .J / , /
110
\.
' / '\.
/
"'-
", -
4.5
5.0
t, FREQUENCY (MHz)
9-289
MC44011
(4.5 MHz) Sound Trap
Figure 14. Composite Video Mode
-15
@
9
i--""
-20 ~
.......
>
f2LU
-25
~
-30
".
.....
/
'\
\
O!:
LU
>=
!;;: -35
z
r- Sound Trap = 1,1
«
LU
I
II
>=
!;;: -30
~
III
-35
'0
V
-45
4.0
........
"
V
'\.
\
cr
1 I
\I
r- 14'13 MHzlCrysta:
'0
aLU
O!:
\
cr
III
-
Figure 15. S-VHS Mode
-10
4.5
r- Sound Trap = 1,1
r- Peaking = 111
r- 14.~ MHz ~rystall
-40
4.0
5.0
/'
/
\ II
\
\ I
JL
v
4.5
I, FREQUENCY (MHz)
I, FREQUENCY (MHz)
-
5.0
(5.5 MHz) Sound Trap
Figure 16. Composite Video Mode
-15
-
@ -20
>
f2LU
-25
~UJ
-30
>=
-35
r-....
@ -10
........
0
./
...........
>
I"
II
~
III
'0
/'
"
~
cr
!;;:
z
Figure 17. S-VHS Mode
-5.0
\
- Sound Trap =1,1
-40 - Peaking =111
MHZ1Crysta:
-45
5.0
I
\
V
0
>
f2LU
-20
~
-25
>
L
w
cr
............ t-..
-15
""' \
>=
-30
«
f2
-20
~
LU
-25
>=
-30
~
-35
~
-5.0
-
cr
!;;:
z
@ -10
0
>
i"'-...
io"'"
"'
'0
J
I
\
I
I
J
5.4
-25
>=
-30
5.8
6.2
"
.,-
\
!;;:
z -35
Sound Trap = 0,1 Peaking = 111
17.7 ~HZ Crytal -
I, FREQUENCY (MHz)
9-290
~
LU
cr
.\
-15
O!: -20
/
'\
\
III
-40
5.0
f2UJ
Figure 19. S-VHS Mode
«
~ -20 ............
w
>
g
-25
w
I..........
~
!;;:
-30
/
\.
:z
«C!l
./
" "'
a:
;;::
-35
/
/
V
-40
5.5
:> -15
...........
~
..........
w
> -20
gw -25
~
\
a:
;;::
-30
:z -35
«
6.0
t, FREQUENCY (MHz)
C!l
to
I"
1/
\
-45
5.5
6.5
--
Sound Trap =1,0
Peaking =111
17.7 MHz Crystal
1\ J
-40
"0
V
\.
!;;:
Sound Trap =1,0
Peaking =111
17.7 MHz Crystal
\..
to
"0
0
6.0
6.5
t, FREQUENCY (MHz)
(6.5 MHz) Sound Trap
Figure 23. S-VHS Mode
Figure 22. Composite Video Mode
-15
-15
0
-20
w
0
..........
:>
~ -25
w
2:
~
w
-30
;;::
-35
a:
!;;:
:z
~
¥l
-40
-45
6.0
"-
\.
../
./
~
~
\
\
\.
--
.............
@ -20
0
:>
~ -25
"-
I\,
\.
g>w -30
'z<
6.5
~
/
\
;;:: -35
Sound Trap =0,0
Peaking = 111
17.7 MHz Crystal
/"
\
I
Sound Trap = 0,0
Peaking = 111
17.7 MHz Crystal
-40
c:c
"0
-45
6.0
7.0
-
I
a:
I
I
1
,.,.....
",
w
6.5
7.0
t, FREQUENCY (MHz)
t, FREQUENCY (MHz)
Figure 24. FC Input Current
~
<-20
~ -40
./'
B
~ -60
-100
v
./
.:!:
~
j; -80
",
r"'"
V
./
"
VCC=5.0V
o
1.0
2.0
3.0
4.0
5.0
PIN 25 VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
9-291
II
MC44011
Figure 25. Horizontal PLL1 TIming/Composite Video Inputs
Video Input
(@Pinsl or 3)
r-3"I1S+-3.5J.1S-!
Burst Gate
(PinS)
____-+!__~I
I
I
FhRef
(Pin 14)
1.3J.1S
__
4_.5_V___________________________
~1·------1I2Fh -------~·I-
--l
4.5 V
'--------
I~
I
I
I
I
I
16FhOut
(Pin 13)
Comp Sync Out
(Pin 13)
~I
1---+1
1I16Fh
.
r-------'---- 4.5V
~I-- ~
0.711S
3.3 J.IS
(1.4 J.IS during vertical Interval)
I
~
Sandeasde OUt
(Pin 35)
J -l-
I
1- 4.0V
I.
I
I
I--- 5.9.115
5.0 J.IS
•
-
3.0V
1----------------------I
---------------------
1.55V
OV
I
NOTE: In above waveforms, all timing is referenced to the center of the incoming Sync Pulse at Pin 1 or 3.
Above timings based on a 4.611s wide sync pulse.
Lower two levels of Sandcastle output aHernate, based on video system in effect.
All timings are nominal, and apply to both PAL and NTSC signals.
Figure 26. Horizontal PLL1 Noise Gate and Filter Pin
Video Input
(@ Pins 1 or 3)
NdlseGate
Charge Pump Current
(Pin 11)
Voltage Waveform
(Pin 11)
9-292
----~~---------_____r
-""'" - - - - - - - ---. {7oo mVpp with High Gain
. ""'"
.
=---1 250 mVpp with Low Gain
MOTOROLA ANALOG IC DEV.ICE DATA
MC44011
Figure 27. Horizontal PLL1 Timing/R, G, Band Y2 Inputs
Video Input
(@ Pins 26 to 29)
'-2.5 ~+-a.5I1S-l
I
Burst Gate
(Pin 8)
:
1
1
-----+I--~·
I
I
FhRef
(Pin 14)
4.5V
650 ns
--l
~------------------------------
"'1·>-------
4.5V
"'1'--___________
1/2Fh - - - - - - - - - - 1..
:--i
16Fh Out
(Pin 13)
I
I
I
I
I
Comp Sync Out
(Pin 13)
,..----------------------ld~4.72:~~,.. =:l
~
1----1
1/16Fh
4.5V
(1.4 ~ during vertical interval)
I
~
Sandcastle Out
(Pin 35)
R, G, B OUtputl
(@ Pins 20 to 22)
J --i1-'"
II
I
I
I-- 5.9,I1S
5.011s
-
--I
II
3.0V
!=--------------------
1.55V
--------------------OV
I
I
I
I
I
I
I
NOTE: In above waveforms, all timing is referenced to the center of the incoming Sync Pulse at Pin 26 to 28, or 29.
Above timings based on a 4.6 I1s wide sync pulse.
Lower two levels of Sandcastle output alternate, based on video system in effect.
MOTOROLA ANALOG IC DEVICE DATA
9-293
MC44011
Figure 28. System TimingNldeo Inputs to RGB Outputs
Video Input
(@ Pins 1 or3)
R-V, B-V Outputs
(@ Pins 41, 42)
R, G, B Outputs
(@ Pins 20 to 22)
II
Figure 29. Fast Commutate Timing
+0.5V
Input @ Pin 25
R, G, BOutputs
(@ Pins 20 to 22)
Color Difference
Inputs Enabled
9-294
RGB Inputs
Enabled
Color Difference
Inputs Enabled
MOTOROLA ANALOG IC DEVICE DATA
MC44011
Figure 30. Horizontal Outputs versus Fields (NTSC System)
Composite Input
(@ Pins 1, 3, 2610 29)
FhRef
(Pin 14)
Burst Gate
(PinS)
Composite Sync
(Pin 13)
I
I
I
____________ LI ______________________________ _
Field 1 I Field 2
•
Composite Input
(@ Pins 1, 3, 2610 29)
Fh Ref
(Pin 14)
II
Burst Gate
(PinS)
Composite Sync
(Pin 13)
MOTOROLA ANALOG IC DEVICE DATA
9-295
MC44011
Figure 31. Horizontal Outputs versus Fields (PAL System)
Line 1
..
Composite Input
(@Pins1,3,26to29)
Field 214
I
I
I
I
Field 113
..
FhRef
(Pin 14)
Burst Gate
(PinS)
Composite Sync
(Pin 13)
I
I
I
---------------~---------------------..
Field 113
i
Field 214 ..
I
Composite Input
(@ Pins 1, 3, 26 to 29)
FhRef
(Pin 14)
II
Burst Gate
(PinS)
Composite Sync
(Pin 13)
Figure 32. Horizontal PLL2 Timing
FhRef
(Pin 14)
15 kHz Retum
(Pin 15)
9-296
~ 60 ns--j
I. .
.
rl
Detennined by
External Circuit
(Must be > 200 ns)
~--
MOTOROLA ANALOG IC DEVICE DATA
MC44011
Figure 33. Vertical Timing (NTSC System)
A) Bh $78-7 = 0
Line 1
Video Input
~36l1si--
I
Vert Sync Out
(Pin 4)
I
I
:
I
I
I
I
I
Field ldent Out
(Pin 7)
I
I
Field 2
Field 1
~4~-----1-------..
I
I--- 500 I1S -----.j
I
----------,----------------------I
Video Input
I
Vert Sync Out
(Pin 4)
Field 1
I
~..>--------I
--'36 1lSi-Field 2
I
Field ldent Out
(Pin 7)
I.
:
•
:
I.
i--- 500 I1s----I
I
I
:
I
I-===========~=======================:
--I
I
68 118
Line 1
B) Bit $78-7 = 1
Video Input
Vert Sync Out
(Pin 4)
~..----Fi-eld-2-:-F-iel-d-l---.~
:
Field ldent Out
(Pin 7)
I
I
I
I
I
:
II
~
I
I
I
f - - 500 1lS----I
I
I+-l00~
----------,----------------------I
Video Input
Vert Sync Out
(Pin 4)
Field 1
Field 2
~4------- -----~.~
Field ldent Out
(Pin 7)
I
I
I
If--500IlS~I
:t-- 144 I1 --!~I-----------S
MOTOROLA ANALOG IC DEVICE DATA
9-297
MC44011.
Figure 34. Vertical Timing (PAL System)
Line 1
A) Bit $78-7 = 0
I
I
I
Video Input
--j 36l1sl--
Vert Sync Out
(Pin 4)
I
I
•
Field 214
Field Ident Out
(Pin 7)
I
---!
~500I1s~
1 - 1_ _ _ _ _ _
Field 1/3
..
I
I
1-110~-I
I
--------------------~--------------
I
Video Input
- - ' 36~1--
Vert Sync Out
(Pin 4)
I
1
Field 1/3
Field Ident Out
(Pin 7)
""
I Field 214
..
I
I
Line 1
B) Bit $78-7 = 1
II
1
~500~~
I
Video Input
Vert Sync Out
(Pin 4)
I
1
""
Field ldent Out
(Pin 7)
Field 214
I
r-
I--- 500~--I
I
..
Field 1/3
------------------~I----~I-----------J+-100~
I
--------------------~--------------
Video Input
Vert Sync Out
(Pin 4)
Field Ident Out
(Pin 7)
9-298
I
1-68~-J
I
I
Field 1/3 I
...""1----1
1
r-
I--- 500~--l
Field 2/4
..
I1--144l1s--lI~---------
MOTOROLA ANALOG IC DEVICE DATA
MC44011
FUNCTIONAL DESCRIPTION
Introduction
The MC44011, a member of the MC44000 Chroma 4
family, is a composite video decoder which has been tailored
for applications involving multimedia, picture-in-picture, and
frame storage (although not limited to those applications).
The first stage of the MC44011 provides color difference
signals (R-V, B-V, and V) from one of two (selectable)
composite video inputs, which are designed to receive PAL,
NTSC, and S-VHS (V,C) signals. The second stage provides
either RGB or VUV outputs from the first stage's Signals, or
from a separate (internally selectable) set of RGB inputs,
permitting an overlay function to be performed. Adjustments
can be made to saturation; hue; brightness; contrast;
brightness balance; contrast balance; U and V bias;
subcarrier phase; and color difference gain ratio.
The above mentioned video decoding sections provide the
necessary lumaldelay function, as well as all necessary
filters for sound traps, lumalchroma separation, luma
peaking, and subcarrier rejection. External tank circuits and
luma delay lines are not needed. For PAL applications, the
MC44140 chroma delay line provides the necessary
line-by-line corrections to the color difference signals
required by that system.
The MC44011 provides a pixel clock to set the sampling
rate of external AID converters. This pixel clock, and other
horizontal frequency related output signals, are
phase-locked to the incoming sync. The VCO's gain is
adjustable for optimum performance. The MC44011 also
provides vertical sync and field identification (Field 1, Field 2)
outputs.
Selection of the various inputs, outputs, and functions, as
well as the adjustments, is done by means of a two-wire 12C
interface. The basic procedure requires the microprocessor
system to read the internal flags of the MC44011, and then
set the internal registers appropriately. This 12C interface
eliminates the need for manual controls (potentiometers) and
external switches. All of the external components for the
MC44011, except for the two crystals, are standard value
resistors and capacitors, and can be non-precision.
(The DACs mentioned in the fol/owingdescriptionare6-bits wide. The
settings mentioned for them are given in decimal values of 00 to 63.
These are not hex values.)
PAUNTSC/S-VHS Decoder
A block diagram of this decoder section is shown in
Figure 35. This section's function is to take the incoming
composite video (at Pins 1 or 3), separate it into luma and
chroma information, determine if the signal is PAL or NTSC
(for the flags), and then provide color difference and luma
signals at the outputs. If the input is S-VHS, the lumalchroma
separation is bypassed, but the other functions are still
in effect.
Figure 35. PAUNTSC/s-VHS Decoder Block Diagram
To Color
Select
($88-7)
r -_ _ _ _D-,iff Stage
I
II
I
Adjustable
LumaDelay
($7F-7,6; $80...j)
R-YOU!
Crystal Select
($7A-7)
Saturation ($87-510)
Hue ($88-5/0)
Color Balance ($78-510)
Blanking
B-YOut
Switches shown with control bits = o.
MOTOROLA ANALOG IC DEVICE DATA
9-299
MC44011
Inputs
The inputs at Pins 1 and 3 are high impedance inputs
designed to accept standard 1.0 Vpp positive video signals
(with negative going sync). The inputs are to be
capacitor--coupled so as not to upset the internal dc bias.
When normal composite video is applied, the desired input is
selected by Bit $88-7. Bits $77-6 and $77-7 must be set to
o so that their switches are as shown in Figure 35. The
selected signal passes through the sound trap, and is then
separated by the chroma trap and the chroma (high
pass) filter.
When S-VHS signals (Y,C) are applied to the two inputs,
Bit $88-7 is used to direct the luma information to the sound
trap, and the chroma information to the ACC circuit
(Bit $77-6 must be set to a Logic 1). Bit $77-7 is normally
set to a Logic 1 in this mode to bypass the first luma delay
line and the chroma trap, but it can be left 0 if the additional
delay is desired.
Sound Trap
The sound trap will filter out any residual sound subcarrier
at the frequency selected by control bits T1 and T2 according
to Table 3. The accuracy of the notch frequency is directly
related to the selected crystal frequency.
Table 3. Sound Trap Frequency
Crystal
Frequency
17.73 MHZ
II
T1
($7B-7)
T1
($7B-6)
Notch
Frequency
0
0
6.5 MHz
0
1
5.5 + 5.75 MHz
1
0
6.0 MHz
1
1
5.5 MHz
0
0
5.25 MHz
0
1
4.44 + 4.64 MHz
1
0
4.B4MHz
1
1
4.44 MHz
14.32 MHz
Code 01 (for T1, T2) is used to widen the band rejection
where stereo is in use. Typical rejection is 30 dB.
ACC and PAUNTSC Decoder
The chroma filter bandpass characteristics (3.58 or
4.43 MHz) is determined by the selected crystal. The output
of the chroma filter is sent to the ACC circuit which detects
the burst signal, and provides automatic gain control once
the crystal oscillator has achieved phase lock-up to the
burst. The dc voltage at Pin 2 is ~ 1.5 to 2.0 V. This will occur
if the burst amplitude exceeds 30 mVpp, and if the correct
crystal is selected (Bit $7A-7). A 17.734472 MHz crystal is
required for PAL, and a 14.31818 MHz crystal is required for
NTSC. When Flag 23 is high, it indicates that the crystal's
PLL has locked up, and the ACC circuit is active, providing
automatic gain control. A small amount of phase adjustment
(~±5°) of the crystal PLL, for color correction, can be made
with control DAC $79-5/0. Pin 2 is the filter for the ACC loop,
and Pin 44 is the filter for the crystal oscillator PLL.
9-300
The PAUNTSC decoder then determines if the signal is
PAL or NTSC by looking for the alternating phase
characteristic of the PAL burst. When Flag 24 is high, PAL
has been detected. Bits SSA, SSB, SSC, and SSD (Table 4)
must then be sent to the decoder to set the appropriate
decoding method.
Table 4. Color System Select
SSA
($7C-6)
. SSB
($7D-6)
SSC
($7C-7)
SSD
($7A-6)
Color
System
0
0
0
0
Not Used
0
1
0
0
PAL
1
0
0
0
NTSC
1
1
0
0
Color Kill
X
X
1
0
Extemal
Upon receiving the SSA to SSD bits, the decoder provides
the correct color difference Signals, and with the Identification
circuit, provides the correct level at the System Select output
(Pin 34). This output is used by the MC44140 delay line.
The color kill setting (SSA = SSB = 1) should be used
when the ACC flag is 0, when the color system cannot be
properly determined, or when· it is desired to have a
black-and-white output (the ACC circuit and flag will still
function if the input signal has a burst signal). The "External"
setting (SSC =1) is used when an external (alternate) source
of color difference signals are applied to the MC44140 delay
line. (See Miscellaneous Applications Information for more
details.)
Color Difference Controls and Outputs
The color difference signals (R-Y, B-Y) from the
PAUNTSC decoder are directed to the saturation, hue and
color balance controls, and then through a series of notch
filters before being output at Pins 41 and 42. Blanking and
clamping are applied to these outputs.
The saturation control DAC($87-5/0) varies the amplitude
of the two signals from 0 Vpp (DAC setting = 00), to a
maximum of ~ 1.8 Vpp (at a DAC setting of 63). The
maximum amplitude (without clipping) is ~ 1.5 Vpp, but a
nominal setting is ~ 1.3 Vpp at a DAC setting of 15.
The hue control ($88-5/0) varies the relative amplitude of
the two signals to provide a hue adjustment. The nominal
setting for this DAC is 32.
The color balance control ($78-510) provides a fine
adjustment of the relative amplitude of the two outputs. This
provides for a more accurate color setting, particularly when
NTSC signals are decoded. The nominal setting for this DAC
is 32, and should be adjusted before the hue control is
adjusted.
The notch filters provide filtering at the color burst
frequency, and at 2x and 8x that frequency. Additionally,
blanking and clamping (derived from the horizontal PLL) are
applied to the signals at this stage. The nominal output dc
level is ~ 2.0 to 2.5 Vdc, and the load applied to these outputs
should be > 10 kn. Sync is not present on these outputs.
MOTOROLA ANALOG IC DEVICE DATA
MC44011
Luma Peaking, Delay Line, and Y1 Output
When composite video is applied, the luma information
extracted in the chroma trap is then applied to a stage which
allows peaking at ~ 3.0 MHz with the 17.7 MHz crystal
(~2.2 MHz with the 14.3 MHz crystal). The amount of
peaking at Y1 is with respect to the gain at the minimum
peaking value (P1, P2, P3 = 111), and is adjustable with
Bits $70-7, and $7E-7,6 according to Table 5.
The luma delay lines allow for adjustment of that delay so
as to correspond to the chroma delay through this section.
Table 6 indicates the amount of delay using the D1-D3 bits
($7F-7,6, and $80-6). The delay indicated is the total delay
from Pin 1 or 3 to the Y1 output at Pin 33. The amount of
delay depends on whether Composite Video is applied, or YC
signals (S-VHS) are applied.
The output impedance at Y1 is ~ 300 n, and the black level
clamp is at ~ 1.1 V. Sync is present on this output. Y1 is also
internally routed to the color difference stage.
Table 5. Luma Peaking
P1
($7D-7)
P2
($7E-6)
P3
($7E-7)
VI
Peaking
0
0
0
9.5 dB
0
0
1
8.5
1
0
0
7.7
1
0
1
6.5
0
1
0
5.3
0
1
1
3.8
1
1
0
2.2
1
1
1
0
17.7 MHz Crystal, 6.5 MHz Sound Trap, Composite Video Mode
Table 6. Luma Delay
14.3 MHz Crystal
17.7 MHz Crystal
01
($7F-6)
02
($80-6)
03
($7F-7)
Camp. Video
($77-7=0)
S-VHS
($77-7 = 1)
Composite Video
($77-7= 0)
S-VHS
($77-7= 1)
0
0
0
690 ns
395 ns
594 ns
350n5
0
0
1
760
465
650
406
0
1
0
830
535
707
463
0
1
1
900
605
763
519
1
0
0
970
675
819
575
1
0
1
1040
745
876
632
1
1
0
970
675
819
575
1
1
1
1040
745
876
632
Color Difference Stage and RGBNUV Outputs
A block diagram of this section is shown in Figure 36. This
section's function is to take the color difference input signals
(Pins 30, 31), or the RGB inputs (Pins 26 to 28), and output
the information at Pins 20 to 22 as either RGB or YUV.
The inputs (on the left side of Figure 36) are analog RGB,
or color difference signals (R-Y and B-Y) with Yl or Y2 as
the luma component. Pin 25 (Fast Commutate) is a logic level
II
input, used in conjunction with RGB EN (Bit $80-7), to select
the RGB inputs or the color difference inputs. The outputs
(Pins 20 to 22) are either RGB or YUV, selected with
Bit $82-7. The bit numbers adjacent to the various switches
and gates indicate the bits used to control those functions.
Table 7 indicates the modes of operation.
Table 7. Color Difference Input/Output Selection
FC
RGBEN
$80-7
VXEN
$82-6
VUVEN
$82-7
1
0
0
0
RGB inputs, RGB outputs, no saturation control
Function
1
0
1
0
RGB inputs, RGB outputs, with saturation control
1
0
1
1
RGB inputs, VUV outputs, with saturation control
1
0
0
1
Not usable
FC Low and/or
RGB EN Hi
X
0
R-V, B-V inputs, RGB outputs. V1 or V2 must be selected
FC Low and/or
RGBENHi
X
1
R-V, B-V inputs, YUV outputs. V1 or V2 must be selected
MOTOROLA ANALOG IC DEVICE DATA
9-301
MC44011
In addition to Table 7, the following guidelines apply:
a. To select the RGB inputs, both FC must be high and
RGB EN.must be low. Therefore, thEl RGB inputs can
be selected either by the 12C bus by leaving FC
permanently high, or by the FC input by leaving
Bit $80-7 permanently low. For overlay functions,
where high speed, well controlled switching is
necessary, the FC pin must be the controlling input.
b. When the R-Y, B-Y inputs are selected, either Y1 or Y2
must be selected, and the other must be deselected.
The YX input is automatically disabled in this mode.
c. In applications where the color difference inputs are
obtained from the NTSC/PAL decoder (from a
composite video signal), Y1 is used. The Y2 input is
nor.mally used where alternately sourced color
difference Signals are applied, either through the
MC44140 delay line, or through other external switching
to Pins 30 and 31.
In Figure 36, the bit numbers followed by "-- 200 ns. The phase comparator will
phase-lock the falling edge of the returned signal with the
rising edge of the fH signal at Pin 14 (see Figure 32).
Vertical Decoder
The vertical decoder section, depicted in Figure 40,
provides a vertical sync pulse and a field identification signal,
as well as flags which indicate if vertical lockup has occurred,
and if the number of horizontal lines per frame is greater or
less than 576.
Inputs to this section consists of the composite sync from
the sync separator, and horizontal related signals from the
horizontal PLL (PLL1).
Figure 40. Vertical Decoder
' - - - - - 2Fh
r~=::-,-_Comp
Sync
L-...::2="-__-16Fh
MOTOROLA ANALOG IC DEVICE DATA
The sync output (Pin 4) is an active low Signal which starts
after the horizontal half-line sync pulses change polarity (see
Figures 33 and 34). The pulse width is nominally 500 its for
both PAL and NTSC signals. The pOSition of this sync pulse's
leading edge can be altered slightly with Bit $78-7, but this
does not change the pulse width. Since the pulse width is
generated digitally by counters, it will not vary with
temperature, supply voltage, or manufacturing distribution.
The sync output is an operl-1:ollector NPN output, requiring
an external pull-up resistor. Minimum value for the pull-up is
1.0 kn, with 10 kn recommended for most applications.
Flag 14 « 576 lines) is derived from the counter which
compares the number of horizontal lines in each frame with a
preset value of 576. This flag can be used externally to help
determine whether PAL or NTSC signals are being provided
to the MC44011. Flag 15 (Vertical countdown engaged)
indicates that the vertical decoder has locked-up to the
incoming composite sync information for eight consecutive
fields (CB1, CA1 = 11).
The operation of the vertical decoder is controlled by Bits
$77--0 and $77-1, according to Table 10.
Table 10. Vertical Decoder Mode
CBl ($77-1)
CAl ($77-0)
Vertical Sync Mode
0
0
Force 625
1
0
Force 525
0
1
Injection Lock
1
1
Auto-Count
The Injection Lock mode has a quicker response time, but
less noise immunity, than the Auto-Count mode, and is
normally used when attempting to lock-up to a new Signal
(such as when changing video input selection). Flag 15 will
not switch high when in this mode. The Auto-Count mode,
having a higher noise immunity, should be set once the
horizontal PLL is locked-up (by reading Flag 12), and then
Flag 15 should be checked after 8 fields for vertical lock-up.
The modes deSignated Force 525 and Force 625 can be
used for those cases where it is desired to force the vertical
sync pulse to occur twice every 525 or 625 lines, regardless
of the incoming signal. In either of these modes, the
MC44011's vertical section will not lock-up to the vertical
sync information contained in the incoming composite video
signal. If there is no incoming video signal, the vertical sync
will still occur every 525 or 625 lines generated by the
horizontal PLL Flag 14 will indicate the number of lines
selected, and Flag 15 will be a steady high.
Bit $77-5 (FSI) is used only in the PAL mode to select the
vertical sync output rate. With this bit set to 0, the vertical
sync pulses will be synchronized with the composite vertical
sync input (every 20 ms). With this bit set to 1, the MC44011
will add a second vertical output sync pulse 10 ms after the
one occurring at the vertical interval, giving a vertical sync
rate of 100 Hz.
9-305
II
MC44011
The Field 10 output (Pin 7) indicates which field is being
processed when interlaced signals are applied, but the
polarity depends on Bit $78-7. Table 11 indicates Pin 7
output. When non-interlaced signals are being processed,
Pin 7 will be a constant high level when $78-7 is set to 1, and
will be a constant low level when $78-7 is set to a O. Loading
on Pin 7 should not be less than 2.0 kf.I to either ground or
5.0 V. Figures 33 and 34 indicate the timing.
Table 12. Sync Source
VlnSync
($88-7)
Y2Sync
($87-7)
RGBSync
($88-6)
0
0
0
None
0
0
1
RGB (Pins 26-28)
Sync Source
0
1
0
Y2 (Pin 29)
1
X
X
Compo Video (Pins 1, 3)
Table 11. Field 10 Output
Field
FieldlD
(Pin 7)
1
1
High
1
2
Low
0
1
Low
0
2
High
36/68118
($78-7)
Sync Separator
The sync separator block provides composite sync
information to the horizontal PLL, and to various other blocks
within the MC44011 from one of several sources. It also
provides composite sync output at Pin 13 when Bit $85-{:! 1.
The sync source is selectable via the 12C bus according to
Table 12.
=
Setting Bit $86-7 to a 1 overrides the other bits, thereby
deriving the sync from the composite video input (either Pin 1
or 3) selected by Bit $88-7.
.
When RGB is selected, sync information on Pins 26 to 28
is used. Sync may be applied to all three inputs, or to anyone
with the other two ac grounded. If RGB signals are applied to
these pins, sync may be present on anyone or all three.
When Y2 is selected, sync information on Pin 29 is used.
The sync amplitude applied to any of the above pins must be
greater than 100 mV, and it must be capacitor coupled.
This system allows a certain amount of flexibility in using
the MC44011, in that if the sync information is not present as
part of the applied video Signals, sync may be applied to
another input. In other words, the input selected for the sync
information need not be the same as the input selected for
the video information.
.
SOFTWARE CONTROL OF THE MC44011
II
12C Interface
Communication to and from the MC44011 follows the 12C
interface arrangement and protocol defined by Philips
Corporation. In simple terms,I2C is a two line, multimaster
bidirectional bus for data transfer. See Appendix C for a
description of the 12C requirements and operation. Although
an 12C system can be multimaster, the MC44011 never
functions as a master.
The MC44011 has a write address of $8A, and a flag read
address of $8B. It requires that an external microprocessor
read the internal flags, and then set the appropriate registers.
The MC44011 does not do any automatic internal switching
when applied video signals are changed. A block diagram of
the 12C interface is shown in Figure 41. Since writing to the
MC44011's registers can momentarily create jitter and other
undesirable artifacts on the screen, writing should be done
only during vertical retrace (before line 20). Reading of flags,
however, can be done anytime.
Figure 41. 12C Bus Interface and Decoder
Start Bit
Recognition
Clock
Clock Counter
Read!
Write
Latch
Data
19 Registers
---------iG,?""1,
Flag Data
9-306
Sub-Address
Latches
MOTOROLA ANALOG IC DEVICE DATA
MC44011
Write to Control Registers
Writing should be done only during vertical retrace. A write
cycle consists of three bytes (with three acknowledge bits):
1) The first byte is always the write address for the
MC44011 ($8A).
2) The second byte defines the sub-address register
(within the MC44011) to be operated on ($77 through
$88, and $00).
3) The third byte is the data for that register.
generated by the MC44011, which tells the master to
continue the communication. The second byte is then
entered, followed by an acknowledge. The third byte is the
operative data which is directed to the designated register,
followed by a third acknowledge.
Sub-Address Registers
The sub-addresses of the 19 registers are at $77
through $88, and $00. Fourteen of the registers use Bits
0-5 to operate DACs which provide the analog
adjustments. Most of the other bits are used to set/reset
functions, and to select appropriate inputs/outputs. Table 13
indicates the assignments of the registers.
Communication begins when a start bit (data taken low
while clock is high), initiated by the master, is detected,
generating an internal reset. The first byte is then entered,
and if the address is correct ($8A), an acknowledge is
Table 13. Sub-Address Register Assignments
SubAddress
7
6
5
$77
S-VHSY
S-VHSC
FSI
$78
36/381ls
Cal Kill
(R-Y)/(B-Y) adjust DAC
Subcarrier balance DAC
$79
HI
VI
$7A
Xtal
SSD
$7B
T1
T2
I
I
4
L2GATE
I
I
$7C
SSC
SSA
$70
PI
SSB
Blue bias for YUV operation DAC
$7E
P3
P2
Red bias for YUV operation DAC
$7F
03
01
Pixel Clock VCO Gain adjust DAC
$80
RGBEN
02
Blue Contrast trim DAC
$81
Y2EN
Yl EN
$82
YUVEN
YXEN
Red Contrast trim DAC
$83
L2Gain
Ll Gain
Blue Brightness trim DAC
$84
HSwitch
525/625
Main Brightness DAC
$85
PClkf2
C Sync
Red Brightness trim DAC
$86
Vin Sync
PLL1 En
$87
Y2 Sync
0
$88
V2IVI
RGBSync
3
BLCP
I
I
2
L1 GATE
I
I
1
CBI
I
I
0
CAl
Main Contrast DAC
II
Main Saturation DAC (Color Difference section)
(R-Y)/(B-Y) Saturation balance DAC (Decoder section)
Hue DAC
$00
Set to $00 to start Horizontal Loop if $88--6 = 0
Table 14 is a brief explanation of the individual control bits.
A more detailed explanation of the functions is found in the
block diagram description of the text (within the Functional
Description section). Table 15 provides an explanation olthe
MOTOROLA ANALOG IC DEVICE DATA
DACs. Each DAC is 6 bits wide, allowing 64 adjustment
steps. The proper sequence and control of the bits and
DACs, to achieve various system functions, is described in
the Applications Information section.
9-307
MC44011
Table 14. Control Bit Description
II
Control Bit
Name
Description
$77-7
S-VHS-Y
Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1, 3). Set to 1 for S-VHS (YC)
operation. When 1, the Y-input at the selected video input (V1 or V2, selected by Bit $88-7)
bypasses the initialluma delay line, and associated luma/chroma filters and peaking. The signal
passes through the second luma delay, adjustable with Bits D1-D3. Luma is output at Pin 33.
$77-6
S-VH5-C
Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1, 3). Set to 1 for S-VHS (YC)
operation. When 1, the chroma input at the non-selected video input (V1 or V2 by Bit $88-7) is
directed to the ACC loop and PAUNTSC detector. Color difference signals are then output at
Pins 41 and 42.
$77-5
FSI
$77-4
L2GATE
Set to 0 for a Vertical Sync output rate of 50 Hz. Set to 1 for 100 Hz. Useable in PAL systems only.
When set to 0, the pixel clock charge pump (PLL2) operation is inhibited during the Vertical
Retrace to minimize momentary instabilities. When set to 1, PLL2 operation is not inhibited.
$77-3
BLCPGATE
When 0, Vertical Gating of the black level clamp pulse during the Vertical Retrace occurs to
minimize momentary instabilities. The Vertical Gating can be inhibited by setting this bit to 1.
$77-2
L1 GATE
$77-1,0
CB1,CA1
$78-7
361681J.S
When 0, the time delay from the sync polarity reversal within the Composite Sync to the leading
edge of the Vertical Sync output (Pin 4) is 361J.S. When 1, the time delay is 68 Ils.
(See Figure 33 and 34).
$78-6
CalKili
When 0, the Horizontal Calibration Loop is enabled for two lines (lines 4 and 5) in each field.
When 1, the Calibration Loop is not engaged. Upon power-up, this bit is ineffective (Calibration
Loop is enabled) until bit $86-6 is set to 0, and register $00 is set to $00.
$79-7
HI
This bit is not used in the MC44011, and must be set to 1.
$79-6
VI
This bit is not used in the MC44011, and must be set to 1.
$7A-7
Xtal
When 0, the crystal at Pin 38 (17.7 MHz) is selected. When 1, the crystal at Pin 36 (14.3 MHz)
is selected.
This bit is not used in the MC44011, and must be set to O.
When set to 0, the horizontal PLL's phase detector (PLL 1) operation is inhiMed during the Vertical
Retrace to minimize momentary instabilities. When set to 1, the phase detector is not inhibited. If
PLL 1 gain is high (Bit $83-6 = 1), gating cannot be enabled.
Sets the Verticallimebase operating method according to Table 10.
$7A-6
SSD
$78-7,6
n, T2
Used to set the Sound Trap Notch filter frequency according to Table 3.
$7C-7, 6 $70-6
SSC,SSA,SSB
Sets the NTSC/PAL decoder to the correct system according to Table 4.
$70-7 $7E-7, 6
P1,P2,P3
Sets the Luma Peaking in the decoder section according to Table 5. (See text).
$7F-7, 6 $80-6
D3, D1, D2
Sets the Luma Delay in the decoder section according to Table 6. (See text).
$80-7
RGBEN
$81-7
Y2EN
When 1, the Y2 Luma input (Pin 29) is selected. When 0, it is deselected.
$81-6
Y1 EN
When 1, the Y1 Luma Signal (provided by the decoder section to the color difference section) is
selected. When 0, it Is deselected.
$82-7
YUVEN
$82-6
YXEN
Effective only when the RGB inputs are selected. When 0, the RGB inputs (Pins 26 to 28) are
directed to the RGB outputs (Pins 20 to 22) via the Contrast and Brightness controls. When 1, the
RGB inputs are directed through the Color Difference Matrix, allowing Saturation control in
addition to the Brightness and Contrast controls. See Figure 36.
$83-7
L2Gain
When 0, the gain of the pixel clock VCO (PLL2) is high (50 1lA). When 1, the gain is low (20 1lA).
$83-6
L1 Gain
When 0, the Horizontal Phase Detector Gain (PLL 1) is low. When 1, the gain is high.
$84-7
H Switch
When 0, Pin 12 is open. When 1, Pin 12 is internally switched to ground, allowing the PLL1 filter
operation to be adjusted for noisy signals.
$85-7
PClkl2
9-308
When 0, permits the RGB inputs (Pins 26 to 28) to be selected with the Fast Commutate (FC)
input (Pin 25). When 1, the FC input is disabled, preventing the RGB inputs from being selected.
When the RGB inputs are selected, the Color Difference inputs (Pins 30, 31) are deselected.
When 0, Pins 20 to 22 provide RGB output signals. When 1, those pins provide YUV
output signals.
When 0, the PLL2 VCO provides the Pixel Clock at Pin 18 directly. When 1, the veo output is
directed through a + 2 stage, and then to Pin 18.
MOTOROLA ANALOG IC DEVICE DATA
MC44011
Table 14. Control Bit Description (continued)
Control Bit
Name
$84-6
525/625
This bit sets the division ratio from the crystal for the reference frequency for the Horizontal
Calibration Loop. For NTSC systems, set to 1. For PAL systems, set to O.
$85-6
CSync
When 0, Pin 13 will provide a square wave of ~ 250 kHz (16 x Fh). When 1, Pin 13 provides a
negative composite sync signal. See Figures 25, 27, 30, 31.
$86-7
Vin Sync
When 1, Composite Sync at the selected Video input (Pin 1 or 3) is used for all internal timing.
When 0, the Sync source is selected by Bits $87-7 and $88-6. See Table 12.
$86-6
PLL1 Enable
$87-7
Y2 Sync
Description
After power up, this bit must be set to 0, and then register $00 set to $00, to enable the Horizontal
Loop (PLL 1). Setting this bit to a 1 will disable the Horizontal Loop, and engages the Calibration
Loop.
When 1, and $86-7 = $88-6 = 0, Composite Sync at the Y2 input (Pin 29) is used for all internal
timing. When 0, the Sync source is selected by Bits $86-7 or $88-6. See Table 12.
This bit must always be set to O.
$87-6
0
$88-7
V2IV1
When CompOSite Video is applied, and this bit is 0, the Video 2 input (Pin 3) is directed to the
Sound Trap. When 1, the Video 1 input (Pin 1) is selected. In S-VHS applications, when 0, Pin 3
is the Y (Iuma) input, and Pin 1 is the chroma input. When this bit is 1, Pin 1 is the luma input, and
Pin 3 is the chroma input.
$88-6
RGBSync
When 1, and $86-7 = $87-7 = 0, Composite Sync at any or all of the RGB inputs (Pin 26 to 28) is
used for all internal timing. When 0, the sync source is selected by Bits $86-7 or $87-7.
See Table 12.
Table 15. Control DAC Description
Control Bits
Description
$78-5/0
This DAC allows for a relative gain adjustment of the R-Y and B-Y outputs (Pins 41,42) as a means of adjusting the
color decoding accuracy. Nominal setting is 32.
$79-5/0
Used to balance out reference errors of the color subcarrier, primarily for NTSC. Nominal setting is 32.
Adjustment range is = ±5'.
$70-5/0
Used to set the U (Pin 22) dc bias level. When in the YUV mode ($82-7
When in RGB mode, set to 00.
=1), this setting should nominally be 32.
$7E-5/0
Used to set the V (Pin 22) dc bias level. When in the YUV mode ($82-7
When in RGB mode, set to 00.
=1), this setting should nominally be 32.
$7F-5/0
Used to fine tune the gain of the Pixel Clock VCO to obtain optimum performance without instabilities. A setting of 63
will shut off the VCO. Setting 50 to 62 provide non-square wave outputs, and can be unstable. As the setting is
increased from 00 to 49, the gain is increased. Changing this register does not change the Pixel Clock frequency.
$80-5/0
Used to fine tune the contrast of the Blue output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$81-510
Used to adjust the gain of the three outputs. In RGB mode this is the Contrast control.
$82-5/0
Used to fine tune the contrast of the Red output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$83-5/0
Used to fine tune the brightness of the Blue output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$84-510
Used to adjust the brightness of the three RGB outputs. In YUV mode this DAC affects only Y output (Pin 21).
$85-5/0
Used to fine tune the brightness of the Red output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.
$86-510
Used to adjust the saturation of the RGBIYUV outputs of the Color Difference section.
$87-5/0
Used to adjustthe saturation of the R-Y, B-Y outputs (Pins 41,42) of the Decoder section.
$88-510
Used to adjust the hue of the R-Y, B-Y outputs (Pins 41, 42). Nominal setting is 32.
$00-7/0
This register must be set to 00, after Bit $86-6 is set to 0, to enable the Horizontal Loop (PLL 1) after power up, or
anytime when Bit $86-6 is set to 0 after having been a 1.
NOTE: The above DACs are 6-bits wide. The settings mentioned above, and in subsequent paragraphs are given in decimal values of 00 to 63. These are not
hex values.
MOTOROLA ANALOG IC DEVICE DATA
9-309
II
MC44011
Reading Flags
A read cycle need not be restricted to the vertical interval,
but may be done anytime. A flag read cycle consists of three
bytes (with three acknowledge bits):
• The first byte is always the Read address for the MC44011
($86).
• The second and third bytes are the flag data.
Communication begins when a start bit (data taken low
while clock is high), initiated by the master (not the
MC44011), is detected, generating an internal reset. The first
byte (address) is then entered, and if correct, an
acknowledge is generated by the MC44011. The flag bits will
then exit the MC44011 as two 8 bit bytes at clock cycles
10-17 and 19-26. The master (receiving the data) is
expected to generate the acknowledge bits at clocks 18 and
27. The master must then generate the stop bit.
The MC44011 flags must be read on a regular basis to
determine the. status of the various circuit blocks. The
MC44011 does not generate interrupts. It is recommended
the flags be read once per field or frame. See Table 16 for a
description of the flags.
Table 16. Flag Description
Clock No.
II
Description (When Flag
=1)
10
Internally set to a Logic 1 .
11
Horizontal Loop (PLL 1) enabled, indicating the loop can be driven by the incoming sync. This bit will be low upon
power up, and will change to a 1 aiter initialization of control Bit $86-6 and register $00.
12
Horizontal Loop (PLL 1) not locked. Lack of incoming sync, or wrong sync source selecfion, or the wrong horizontal
frequency, will cause the Coincidence Detector to indicate a "not locked" condition.
13
Internally set to Logic O.
14
Less than 576 horizontal lines counted per frame. This flag helps determine the applied video system. When high, a
525 line system (NTSC) is indicated. When low, a 625 line system (PAL) is indicated.
15
Vertical Countdown engaged. When high, this flag indicates the Vertical Countdown secfion has successfully
maintained lock for 8 consecutive fields, indicating therefor a successful vertical lock-up. This flag is low in the
Injecfion Lock mode.
16
Internally set to a Logic 1 .
17
Internally set to a Logic 1 .
18
(Acknowledge pulse).
19
Pixel clock VCO control voltage too low « 1.7 V at Pin 16). This indicates the VCO may not funcfion correctly as the
control voltage is near one end of its range. The DAC setting at register $7F-5/0 must be increased, and/or the + 2
block must be selected (set $85-7 1), to clear this flag.
20
Pixel clock VCO control voltage too high (> 3.3 V at Pin 16). This indicates the VCO may not funcfion correctly as the
control voltage is near one end of ~s range. The DAC setting at register $7F-5/0 must be reduced, and/or the + 2 block
must be deselected (set $85-7 = 0) to clear this flag. This flag will be high if the VCO is off (DAC $7F = 63).
=
9-310
21
Internally set to a Logic 1.
22
Internally set to a Logic O.
23
ACC Loop is active, indicating it is locked up to the color burst signal. The Color Burst amplitude must exceed
30 mVpp, and the correcf crystal selected, for lock-up.to·occur.
24
PAL system identified by the decoder, indicating the decoder recognizes the line-by-line change in the burst phase.
When NTSC is applied, this flag is O.
25
Not used.
26
Internally set to a Logic O.
27
(Acknowledge pulse).
MOTOROLA ANALOG Ie DEVICE DATA
MC44011
APPLICATIONS INFORMATION
Design Procedure and PC Board Layout
The external components required by the MC44011 are
shown in Figure 42. Except for the crystals, all the
components are standard value resistors and capacitors, and
can be non-precIsion. Table 18 describes the external
components for each pin.
Figure 42. Basic Functional Circuit
Video 2 ___-'V47>A0~
Input
VSync Out ....- - - - - ,
(If necessary - see text)
12C {SCL
"'---'0:~~======~11
Bus SOL
Field 10 Out
Burst Gate Out ....- - - - - - - . . ,
Gnd
Xtal1
N/C
Xtal2
SANOCI-""'-----------....J
Sys Sell-'!''---------....l
Y1 Outl-""------~
Y 1 Clmp
I 0.47 ~
R-Y liP ~-----''---_+_------l
B-Y liP ~------__l_----.J
Y2 In
Y1 Luma Out
'-----'VVIr--j f---_-..... Y2 Luma Input
0.1
~
-,.--=.!"----.I------'-'-I
PLL 1 Filt
124 PLL 1 Filt SW
'-JV\tv---::---:::-H--,,
F_-"'-I 16FhlCSync
16FhlCSync __---'1-".2.'!.k_...:.47:..::0,-!:pc:...
Out
MC44011
FH Ref
.-------...:.::-115 k Ref
1-".....""';':::-1 PLLFilt
Gnd
Pixel ...._ ......_ _ _ _ _ _ _--,
Clock
5.0
Red Out ---H...+----,
Green Out __--j- 1.5 kn. If it is desired to drive a 75 n load
(e.g., a monitor) from these outputs, a simple buffer (see
Figure 43) can be added.
Figure 43. Output Buffer
The Y1 output (Pin 33) has an output impedance of
= 300 n, and can be used as a monitoring point, or to drive
the input of the MC44145 sync separator, or other high
impedance loads (minimum load for Y1 is 1.0 kn). If it is to be
used to drive a 75 n load, the buffer shown in Figure 43 can
be used, except the 390 n resistor must be deleted.
The Vertical Sync output (Pin 4) is an open-collector logic
level output, and requires a pull-up resistor to 5.0 V. 10 kn is
recommended, but it can be as low as 1.0 kn. The 12C data
line (SOL, Pin 6) is also open--collector when it is an output,
and can sink a maximum of 3.0 mAo Only one pull-up resistor
is required on the SOL line (regardless of the number of
devices on that line), and it is typically near the master
device. The Field 10, Burst Gate, 16Fh/CSync , Fh Ref, and
Pixel Clock outputs are logic level totem-pole outputs.
PC Board
The PC board layout should be neat and compact, and
should preferably have a ground plane. If feasible, a second
plane should be provided for the 5.0 V supply, but this is not
mandatory. The components at Pins 9 and 11 should be
connected to the same ground track which goes to Pin 10.
The VCC and ground should be connected as directly as
possible to the power supply, and not routed through a maze
of digital circuitry before arriving at the MC44011. Since the
MC44011 is intended to be used with AID converters and
high speed digital Signals, it is expected digital circuitry will be
on the same board. Care should be taken in the layout to
prevent digital noise from entering the analog portions of the
MC44011. The most sensitive pins are Pins 1,2,3,9,10,11,
12, 16, and 44, and should be protected from noise.
Initialization and Programming Information
Upon powering up the MC44011, initialization consists of
first filling the registers with initial values to set a known
condition. Table 19 provides recommended values for the
initial settings, although these may be tailored for each
application (with the exception of Bits $79-6,7, $7A-6,
$86-6, and $87-6). Table 19 settings will set up the
MC44011 to the following conditions:
• Composite video input at Video 1 (Pin 1), NTSC, using the
crystal at Xtal 2 (Pin 36).
• Y1 enabled, RGB outputs enabled, and Composite
Sync at Pin 13
• RGB inputs not enabled (R-Y, B-Y inputs are enabled)
• The Sound Trap at 4.5 MHz
• The Luma Peaking at 0 dB
• The Luma Delay at minimum
• High gain and high noise rejection for the horizontal PLL
• Vertical decoder set to Injection Lock mode
• The Pixel Clock VCO is off
R,G,B,
orYl0ut
To Monitor
MOTOROLA ANALOG IC DEVICE DATA
After the registers are initialized, then set Bit $86-6 to 0,
and load register $00 with $00. This will enable the horizontal
PLL, permitting normal operation.
9-313
MC44011
Table 19. Recommended Initial Settings
SubAddress
7
6
5
4
3
2
1
·0
$77
S-VHSY=O
S-VHSC=O
FSI=O
L2 Gain =0
BLCP=O
L1 Gain=O
CBI=O
CAI=1
$78
36168jlS = 0
. Calkill = 0
(R-Y)/(8-Y) Adjust DAC = 32
$79
HI = 1
VI=1
Subcarrier Balance DAC = 32
$7A
Xtal;=1
SSD=O
$7B
T1 = 1
T2= 1
-
$7C
SSC=O
SSA= 1
-
$7D
P1" 1
SSB=O
Blue Bias = 00
$7E
P3= 1
P2= 1
Red Bias = 00
$7F
03=0
01 =0
Pixel Clock VCO Gain Adjust = 63
$80
RGB EN= 1
02=0
$81
Y2EN=0
Y1 EN = 1
Main Contrast = 47
$82
YUVEN=O
YXEN=O
Red Contrast Trim = 32
$83
L2 Gain = 1
L1Gain=1
Blue Brightness Trim = 32
$84
H Switch = 1
525/625 = 1
Main Brightness = 30
$85
PClkl2= 1
CSync = 1
$86
Yin Sync = 1
$87
Y2 Sync = 0
0
$88
V2IV1=1
RGBSync = 0
PLL1 EN=1
Blue Contrast Trim = 32
Red Brightness Trim = 32
Main Saturation (Color Difference section) = 32
(R-Y)/(B-Y) Saturation Balance (Decoder section) = 15
Hue =32
..
NOTE: These settings are for power-up initialization only. Refer to the text, and Appendix B, for subsequent modifications based on the application .
II
Then, after selecting the desired input(s) (from Pins 1, 3,
or 26 to 31), and based on the applied signals at those
inputs, and by reading the flags, the registers are adjusted
for the desired and proper mode of operation. A suggested
routine for selting modes is given in Appendix B. The "initial
values" in the Control DACs table of Appendix B are those
in Table 19. The remainder of the flow chart is a
recommendation only, and should be tailored for each
application.
The monitoring of flags should be done on a regular basis,
and it is recommended it be done once per field. See Table 16
(in the Functional Description section) for a summary of the
flags. Should any flags change, the following procedures are
recommended:
Flag 11 (Horizontal Enabled) - Once enabled by setting Bit
$86-6 = 0, this flag should always remain a 1. Should it
change to 0, reset $86-6 to 0, and write $00 to register $00
again. If the flag does not return to a 1, this indicates a
possible device malfunction.
Flag 12 (Horizontal Out-of-Lock) - When 1, this indicates:
a. the wrong input is selected (Bits $88-7, $81-7,
$80-7, and $77-7,6), or;
b. the wrong sync source is selected (Bits $86-7, $87-7,
and $88-6), or;
c. the incoming signal is somewhat unstable, as from a
VCR tape (change Bit $83-6), and/or;
d. the incoming signal is noisy (change Bit $84-7), or;
e. a loss of the incoming signal with sync.
(It is possible for this flag to flicker when the video signal is
from a poor quality tape, or other poor quality source.)
9-314
Flag 14 (Less than 576 lines) - This flag, from the vertical
decoder, is used to help determine if the signal is PAL or
NTSC. Should it change, this indicates the incoming signal
has changed format, or possibly one of the items listed under
Flag 12 above.
Flag 15 (Vertical Countdown Engaged) - Bits 77-0 and 1
must be set to 1 (after Flag 12 reads 0) for this flag to indicate
correctly. Then this flag will change to a 1 after 8 fields of
successful synchronization of the internal counters with the
incoming signal. To change to a 0 requires 8 consecutive
fields of non-synchronization. If this flag changes to 0, this
indicates a loss of signal, a change of signal format, or
instability in the horizontal PLL.
Flags 19, 20 (VCO Control Voltage LowlHigh) - These
flags are meaningful only if.the Pixel Clock Generator is used.
If Flag 19 is a 1, the gain of the pixel clock VCO needs to be
increased by increasing the value of register $7F, and/or set
Bit $85-7 = 1. If Flag 20 is a 1, the value of the register must
be decreased, and/or set Bit $85-7 = O. If the VCO is turned
off ($7F 63), Flag 19 will be 0, and Flag 20 will be 1.
=
Flag 23 (ACC Active) -If this flag is a 0, it indicates the ACC
loop is not active. This will happen if the burst signal is less
than 30 mVpp, if the incorrect crystal is selected ($7A-7), if
the crystal PLL is not locked, or if the horizontal PLL is not
locked.
Flag 24 (PAL Identified) - This flag is a 1 when PAL signals
are applied, and a 0 when NTSC signals are applied, or when
no burst is present.
It is recommended that the Color Decoder section, and
crystal, should be set according to the state of Flags 14, 23,
and 24 according to Table 20.
MOTOROLA ANALOG IC DEVICE DATA
MC44011
Table 20. Color Standard Selection Table
Flags
Bit Settings
#14
#23
#24
<576 Lines
ACCActive
PAL Signal
X
0
X
0
1
0
1
1
1
Crystal
SSA
($7C-6)
SSB
($70-6)
SSC
($7C-7)
System
Either
1
1
0
Color Kill
0
Either
1
1
0
Color Kill
1
17.7 MHz
0
1
0
PAL
1
0
14.3 MHz
1
0
0
NTSC
1
1
(Note 1)
0
1
0
PAL-M
NOTES: 1. PAL-M, used in Brazil and olher South American countries, can be decoded bylhe MC44011, bul requires a 14.3024 MHz cryslal.
2. SSO ($7A-6) is always sella O.
MISCELLANEOUS APPLICATIONS INFORMATION
Use of the MC44140 Delay Line
The MC44140 delay line is generally required if PAL
signals are to be decoded, so as to average out the
line-by-line color information associated with PAL color
decoding. If the same single PAL video source is always used
in a particular application, the delay line can be eliminated,
and any slight phase errors can be corrected with the DAC of
register $79-5/0. If, however, various video sources can be
used, and/or if the video signal is less than broadcast quality,
it is recommended the MC44140 delay line be included.
The MC44140 acts on the color difference signals before
they enter the color difference stage of the MC4401'. It will,
however, pass NTSC signals through without modifications.
The MC44011 uses the System Select output (Pin 34) to
indicate to the delay line which signals are being processed.
The System Select voltage is set when the color decoder is
set with Bits SSA, SSB, SSC, SSD. The Sandcastle output
(Pin 35) provides the horizontal timing signals to the delay
line. In addition, the MC44140 uses the crystal frequency for
the internal counters.
The MC44140 is inserted into the circuit between the Color
Difference outputs and inputs of the MC440". In addition,
the MC44140 provides pins (Pins 8,9) for inserting an
alternate source of color difference signals to the MC44011
by setting the System Select to external (Bit $7C-7 1). See
Figure 44 for a suggested circuit.
If only NTSC signals are to be processed by the MC44011 ,
the MC44140 is not needed. In this case, connect Pin 42 to
Pin 31 with a 9.1 J.1F capacitor, and similarly connect Pin 41 to
Pin 30.
=
Figure 44. Incorporating the MC44140 Delay Line
-MC44011l
Gnd
Xtal1
Xtal2
5.0
12?PF
~I__---.
10
1.0
I -=22 pF
,...--If-_+---_-_-_-_-_-_----+-,
~11----11---+1-----+--I
I 17.7MHz
I
22 pF
r36H11----1
5.0
47
114.3 MHz
I
Sande
Sys Sal
R-YOul
B-Y) Alternate
Inputs
B-YOut 411-----0-.1----11----, L-.-----------1If--+-+O R-Y
R-Yln []j]""'.---IIf-----'
..1-,
0.. '
L- __ ~Y~~~------------------~
MOTOROLA ANALOG IC DEVICE DATA
9-315
MC44011
Figure 45. Typical Waveforms
.~
~
~
~
!
sc:::
5i
j
I!!
C!l
T
Video Input
@Plnslor3
(Standard Color Bar
PaHem, 100% Saturation)
R-YOutput
Pin 42
Pin 41
(DAC $87 = 15)
!Il ~
1i5 co
i
f
950
700
~
----,
"" 2.8Vdc
400
----------y
"" 2.4 Vdc _ _ _ _ _ _.J
(DAC $87 = 15)
B-YOutput
~
1200
____________ -.l
-------,
"" 2.4 Vdc
1460
--------------~
T
770
Yl0utput
Pin 33
___ -L
"" 1.1 Vdc
----T 440
---------r
II
Red Output
Pin 20
Vo
--L
"" l.4Vdc
Vs
-------------,
Green Output
Pin 21
"" 1.4 Vdc-Ur---...J
I
U
*
T
~
Vs
--------,
Vo
--.-L
BtueOutput
Pin 22
"" 1.4Vdc
DACs set per Table 19. All amplnudes In milliVolts.
Voltages are nominal, and do not represent guaranteed limita.
DAC8l
Vo
Vs
32
1725
2360
3160
220
340
440
47
63
9-316
MOTOROLA ANALOG IC DEVICE DATA
MC44011
Use of the MC44145 Pixel Clock Generator
For most applications the Pixel Clock Generator (PLL2)
within the MC44011 will be suitable. In those cases, however,
where the pixel clock frequency is set to within ±1.0 MHz of
the selected crystal frequency (14.3 MHz or 17.7 MHz), or to
within ±1.0 MHz of double the selected crystal frequencies,
undesirable noise artifacts may be present on the RGB
outputs. In these cases the MC44145 should be used to
generate the Pixel Clock. The circuitry within the MC44145
duplicates that of the MC44011, but since it is physically
removed from the circuitry within the MC44011, the
interfering noise is not generated. If the MC44145 is used,
the Pixel Clock Generator within the MC44011 should be shut
off by setting the DAC of register $7F to 63, eliminating the
components at Pin 16, and grounding Pin 16.
If the desired pixel clock frequency is close to the limits
mentioned above, then experimentation may be used to
determine the need for the MC44145.
that it equals the horizontal frequency. The PLL within the
MC44011 (or the MC44145) compares the horizontal
frequency with the returned frequency, and adjusts the
internal VCO accordingly, to achieve the proper relationship
between the two. The PLL will phase-lock the
negative-going edge of the returned signal with the
positive-going edge of the Fh signal (Pin 14 of the
MC44011). The returned signal must be TTL logic level
amplitudes, and have a minimum low time of 200 ns. A
suggested circuit for the divider, shown in Figure 46, uses
74F161 programmable binary counters. The 12 switches at
the bottom are used to set the division ratio, and hence the
Pixel Clock frequency.
The division ratio is determined by dividing the desired
clock frequency by the horizontal frequency, and then using
the closest whole number. After determining the binary
equivalent of that number, close each switch corresponding
to a 1, and leave open each switch corresponding to a O.
Alternately, the switches could be deleted, and Pins 3, 4, 5
and 6 of each 74F161 hard-wired to 5.0 V or ground, or
controlled by a microprocessor where different pixel clock
frequencies are required.
Frequency Divider
The frequency of the Pixel Clock is determined by the
horizontal frequency and an external frequency divider. The
divider simply divides down the Pixel Clock Frequency so
Figure 46. Suggested Frequency Divider
r----
I
Return
I
I Clock Out
I MC44011
I
or
I
IL ____
MC44145 I
.J
To AID Converters
(MC44250 or MC44251)
74FOO
ENP
ENT
2
Clk
9
LD
6
0
C
B
12
(MSB)
u;
~
14
OA
13
OB
12
OC
11
00
15
RCO
16
VCC
1
ClR
Gnd a
** * *
MOTOROLA ANALOG IC DEVICE DATA
9
5.0
7 ENP
10
ENT
2
Clk
lO
0
C
B
5.0
1,0
3
OA 14
5.0
OB 13
OC 12
u;
00 11
Ii: RCO 15
~
VCC 16
ClR 1
Gnd a
5.0
1,0
14
7 ENP
OA
13
10 ENT
OB
2
12
Clk
OC
9
lO u; 00 11
6 0 Ii: RCO 15
....
16
5 C
VCC
1
4
B
ClR
Gnd a
II
....
4
5,0
1,0
* ***
1
(lSB)
9-317
MC44011
Connecting the MC44011 to the MC44250 or
MC44251 AID Converter
The MC44250 and MC44251 triple AJD converters are
designed to accept RGB or YUV inputs, and provide 8-bit
equivalents of each. Additionally, the inputs have black level
clamps, allowing the input signals to be capacitor-coupled.
The simplified schematic of Figure 47 shows the connections
between the MC44011 and the MC44250/1, including
anti-aliasing filters between the devices. Connection to other
AID converters would be done in a similar manner. Refer to
the appropriate data sheet for details.
a Triple AID Converter
Figure 47. Connecting to
i-7s~;
I
I
I
I
I
I
I
I
I---~f::~:f---{O R7
Pixel Clock
23 Clk
Burst Gate
29Hz
I
RNOut
T
Green
orY
RNln
35 GIY In
GfYOut
BlU Out
Red, •
orV ~.
RO
-
22
DigilalOutputs
GO
BJiJ In
37
{YQ" ~7
{Q
~7
r
Blue
I
orU
~.
L __________
BO
L~~~12...J
Connecting the MC44011 to the MC141621 or
MC141625 NTSC Comb Filter
A comb filter can be used ahead of the MC44011 to
enhance picture quality by providing a more accurate
separation of the luma and chroma components from the
composite video, without sacrificing bandwidth. The usual
benefits are reduced dot crawl, and increased color purity.
II
Figure 48 (a simplified schematic) shows the normal mode of
implementing the MC141621 (NTSC) or MC141625
(PAUNTSC) comb filter with the MC44011. The two comb
filters can also provide the Y and C signals in digital format.
Refer to their data sheets for details. The MC14576A
operational amplifiers have an internally set gain of 2.
Figure 48. Implementing the Comb Filter
n
Comp
Video o-.o---~~-~
Output 75
0.47
I
I
f-D
1.Ok
Video
II
I
I
I
I
I
I Clk
Inpui
_ -
,r--.c.
1 -V-d-1---'
tL.;U I eo
I
-
75
YOut~75
I
MC14576A
I
MC44011
I
I
I
Set Bits:
$n-7 = 1
CO~5
I
ut
~
~Vide02
I -=-
MC141621
MC141625
Comb Filter
75
..--l-,
~
-=-
$n~=1
I
II
I
I
I
I
I
II
I 22 F
17.7 ~Hz.-L $88-7 = 1
I
p f----I.~ Xlal1
I
50
22pFI ___ ~.' - ' -1.'-------'
~ Xtal2
-----750k 120PF~4.3MHZ L ____ -1
t
0.1
9-318
5_O
r--U----,
5.0 ___.--------.
3 7
+2
+ 5
_6
MOTOROLA ANALOG IC DEVICE DATA
MC44011
APPENDIX A
Control Bit Summary
I
$77
Btt7
6
5
S-VHSY
S-VHSC
FSI
I
0=50Hz
1= 100 Hz
I
I
I
I
I
I
I
$78
$79
$7A
I $78
I
I
I
o = Camp. Video
1=S-VHS
I
I
36/68
HI
Xtal
T1
'II
I
"
SSO
I
SSC
SSA
I
$70
I
PI
SSB
I
$7E
$82
$83
I
I
I
I
3
BlCP
I
0= Clamp
Gating
P3
P2
03
01
RGBEN
02
I
I
T1
0
0
1
1
1 = Cal Loop Oisabled
~Settol,1
~settoo
2
1
Ll Gate
I
0= PLL1
Gating
CBI
CBI
0
1
0
1
<;
YUVEN
<;
12Gain
<;
$84
H Swttch
$85
PClkl2
$86
Vin Sync
<;
<;
<;
I
I
I
I
I
I
0
1
0
1
$87
Y2Sync
I
$88
V'2IVI
I
~ 1 = Yl Enabled
YXEN
~ 1 = RGB Matnx Enabled
Ll Gain
~ 1= PLL1 Gain High
SSB
SSC
Color System
0
1
0
1
X
0
0
0
0
1
Not Used
PAL
NTSC
Color Kill
Extemal
PI
P2
P3
VI Peak
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
9.5 dB
8.5
7.7
6.5
5.3
3.8
2.2
0
1 = YUV Outputs
LumaOelay
01 02 03
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Camp Video Mode
1 = PLL2 Gain Low
~1=NTSC
CSync
f- 1= Camp Sync
PLL1 EN
r--- 0 = PLL1 Enabled
1 = Switch Closed
1 = ... 2 Enabled
1 = Camp Video Sync Source
~ Set to 0
'--'--......L---'---~'c=====_ 1 = Y2 Sync Source
RGB Sync
Sync Mode
Force 625
Force 525
Inj Lock
Auto Count
CAl
0
0
1
1
0
0
1
1
X
1 = Y2 Enabled
5251625
I
SSA
I
V1 EN
0
CAl
Sound Trap Notch Frequency
PAL
NTSC
6.5 MHz
5.25 MHz
5.5+5.75 MHz
4.44 + 4.64 MHz
6.0 MHz
4.84 MHz
5.5 MHz
4.44 MHz
o = RGB Inputs Enabled
Y2EN
I
T2
/
1 = Pin 36 Crystal
$7C
$81
I
12 Gate
I
0= PLL2
Gating
12
I
I $7F I
I $80
I
4
I
I
I
I
~VertiCal1ime Constant
CalKiIi
VI
I
14.3 MHz
690ns
760
830
900
970
1040
970
1040
17.7 MHz
594ns
650
707
763
819
876
819
876
r--- 1= RGB Sync Source
'--'--......L----~'c=====_ 1 = Pin 1 Input
Control DACs
$78
R-YIB-Y Gain Adjustment
$82
Red Contrast Trim
$79
Subcarrier Phase
$83
Blue Brightness Trim
$70
Blue DC Bias
Red DC Bias
$84
$85
Main Brightness
$7E
$7F
Pixel Clock VCO Gain
$86
Saluration (Color Diff Section)
$80
Blue Contrast Trim
$87
Saluralion (Decoder)
$81
Main Contrast
$88
Hue
Red Brightness Trim
Flags
10
Intemally Set to 1
19
11
Horizontal Loop (PLL1) Enabled
20
Pixel Clock VCO Gain too high
12
Horizontal Loop not Locked
21
Internally Set to 1
13
Internally Set to 0
22
Internally Set to 0
14
Less than 576 lines
23
ACC Loop Active
15
Vertical Decoder Engaged
24
PAL Signals Detected
16
Internally Set to 1
25
Not Used
17
Internally Set to 1
26
Internally Set to 0
MOTOROLA ANALOG IC DEVICE DATA
Pixel Clock VCO Gain too low
9-319
MC44011
APPENDIXB
Suggested Mode Setting Routine (Simplified)
Set PAL Mode with
Bits $7C-7, 6 $7D--6
Enable Horizontallimebase
Set $86-6 = 0
Set Register $00 to $00
Select Honzontal Calibration
Frequency Bit $8oH!
Check Hon.. Out-of-Lock
(Aag12)
Select Sound Trap
Set$71Hl,7
Select Luma Peak
Set$7D--7, $7E-6, 7
Select loma Delay
Set $7F-6, 7, $80-6
Select Sync Source with
Bits $86-7, $87-7, $8B-6
Check Aags 19 & 20.
Adjust $7F Register
as required
Adjust Contrast, Brightnass, Trim,
Hue, Saturation and other DACs
as necessary
Monitor Flags on a
continuing basis
9-320
MOTOROLA ANALOG IC DEVICE DATA
MC44011
APPENDIXC
12C Description
Introduction
The 12C system, a patented and proprietary system
developed by Philips Corporation, defines a two-wire
communication system. The number of devices in a system is
limited only by the system capacitance and data rate. Each
device is assigned two unique addresses - one for writing to it,
and one for reading from it. Any device may act as a master by
initiating a data transfer with any other device (the slave). Data
R2
Vp
R1
Hardware Aspects
The system bus consists of two wires, Clock and Data. All
devices must have open-collector (or open-drain) outputs. A
single pull-up resistor is required on each line, as shown in
Figure C1.
Figure C1. Basic 12C System
Device 2
Devices such as the MC44011, which never act as a
master, need not have the output drive transistor at the Clock
pin. Nominal value for R1 and R2 is 10 kQ, but can be
different to account for system capacitance at high data
rates. VR is a switching threshold for input signals.
The significant electrical characteristics are as follows:
- Maximum data rate (Clock frequency) is 100 kHz;
- VOL max is 0.4 V when sinking 3.0 mA;
- VIL max is 0.3 x Vp, but at least 1.5 V;
- VIH min is 3.0 V for a 5.0 V system, or 0.7 x Vp for other
supply voltages.
- The maximum input current at Clock and Data at VOL
max (when they are inputs) is -10 f.1A;
- The maximum input current at Clock and Data at 0.9 x Vp
(when they are inputs) is 10 f.1A;
- The maximum pin capacitance is 10 pF;
- Maximum bus capacitance is 400 pF.
Data Transfer
Prior to initiating a data transfer, both lines must be high
(all drive transistors off). A device which initiates a data
transfer assumes the role of the master, and generates a
START condition by taking the Data line low while Clock is
still high. At this time, all other devices become listeners. The
master will supply the clock for the entire sequence.
The master then sends the 8-bit address by operating
both the clock and data lines. Data must be stable during the
clock's high time, and can change during the clock's low time.
The MSB is sent first. The address must end in a 0 if it is a
Write operation (data transfer from master-te-slave), and it
must end in a 1 if it is a Read operation.
At the 9th Clock Pulse, the master must release the Data
line high, and the slave must provide an acknowledge bit by
pulling Data low during this clock time. If the master does not
receive a proper acknowledge, it can terminate the operation.
MOTOROLA ANALOG IC DEVICE DATA
transfer is in 8-bit bytes, and can be in either direction, but not
in both directions in one data transfer operation.
DeviceN
After the first acknowledge, the role of the two devices
depends on whether it is a Write or a Read operation, but the
master always supplies the clock.
- In a Write operation the master is the transmitter, and the
slave is the receiver.
- In a Read operation the slave is the transmitter, and the
master is the receiver.
The transmitter then sends the next 8-bit byte. At the 18th
Clock Pulse (and every 9th clock pulse thereafter), the
transmitter releases the Data line, and the receiver
acknowledges by pulling Data low. There is no limit to how
many bytes may be sent after the address.
When all data is transferred, the Data line must be
released by the transmitter so that the master can set the
STOP condition. This is done by first pulling Data low (during
clock low), then releasing Data high while clock is high. After
this, the bus is free for any other device to initiate a new data
transfer.
Definitions
Master - The device which initiates a data transfer
(regardless of the data direction), generates the clock, and
terminates the transfer.
Slave - The device addressed by the master.
Transmitter - The device which supplies data to the bus.
Receiver - The device which receives data from the bus.
Notice that the master is not necessarily the transmitter,
andthe slave is not necessarily the receiver.
Other
For additional information on the 12C bus specifications;
modes of operation; arbitration; and synchronization, contact
Philips Corporation.
9-321
9
MC44011
APPENDIXD
PLL Loop Theory
High Frequency Line-Locked Clock Generator
This section is not intended as a complete loop theory, its
aim is merely to point out the idiosyncrasies of the loop, and
provide the user with enough information for the selection of
filter components. For a more in depth explanation, the
references at the end of this section may be consulted.
always in the correct direction, whereas the higher gain will
come into action as soon as the error reaches 21t.
The following values are selected and defined:
C2 C1/10 or less, to satisfy the requirement that the effect
of C2 on the low frequency response of the loop be minimal,
and similar to a 2nd order loop.
=
S
Figure 01. PLL2 Basic Configuration
= 0.707 (damping factor).
roi = 15750 x 2p = 98960 rad/sec (input frequency).
~
RC as the loop filter
Ko x Ip x R/(21tN) - the loop gain
K
K'
K x 1: 4S2 (the normalized loop gain)
Ko
70 x 106 radN
=
=
=
=
=
=
Stability analysis with C2 = C1/10 and K' = 2 (S 0.707)
gives a minimum value of 7.5 for the ratio roi/K. To have some
margin, a reasonable value can be 15 to 20 or higher.
Selecting roi/K = 20 yields,
K roi/20 = 5000.
=
Using the following items:
K'=2,
1: 21K
400 j.!s,
K Ko x Ip x R/(21tN)
Ip = 20 J.LA
N = 2000 (average value)
= =
=
The following general remarks apply to the loop (PLL2):
- The loop frequency is = 15.7 kHz.
- In spite of the samples nature of the loop, a continuous
time approximation is possible if the loop bandwidth is
sufficiently small.
- Ripple on Vc (filter pin) is a function of loop bandwidth.
- The loop is a type II, 3rd order. However, since C2 is
small, the pole it creates is far removed from the low
frequency dominant poles, and the loop can be analyzed
as a 2nd order loop.
The following remarks apply to the Phase and Frequency
Comparator:
- Phase and frequency sensitive.
- Independent of duty cycle.
- It has 3 allowed states: up, down, and off (high
impedance).
- The VCO is always pulled in the right direction during
acquisition.
- The Comparator's gain is higher at or near lock.
The last two remarks imply that only the higher value need
be taken into account, as acquisition will be slower but
yields a value of 22 kn for R. Using a value of 400 j.!s for~, C1
calculates to 18 nF, and C2 calculates to 1.8 nF.
With the above values, the loop's natural frequency (ron),
and loop bandwidth (r03dB) can be calculated:
ron ((Ko/N) x Ip/(21tC) }0.5 3520 rad/sec.
fn = 3520/21t 560 Hz.
ro3dB = 2 x ron 1120 Hz (valid if S 0.707).
=
=
=
=
=
The circuit designer should be cautioned at this point that
the above calculated values are not necessarily optimum for
every application. Besides the fact that several assumptions
were made in the discussion, the equations cannot account
for items such as the PC board layout, characteristics of the
external divider, and noise from various sources. The above
calculated values provide for a functional circuit, which
should then be tweaked to obtain minimum jitter at the pixel
clock output.
When initially adjusting the filter component values, it
is advisable to maintain the same general time constant
(400 j.!s in this example), and the same x10 relationship
between C1 and C2.
References:
(1) Charge-Pump Phase-Lock-Loops by Floyd M. Gardner, IEEE Transactions on Communications, Vol. com-28, no. 11, Nov. 1980.
(2) Phaselock Techniques by Floyd M. Gardner, J. Wiley & Sons, 1979.
(3) Phase-Locked-Loopsby Roland E. Best, McGraw Hill, 1984.
(4) AN-535, Phase-Locked-Loop Design Fundamentals, Motorola.
9-322
MOTOROLA ANALOG IC DEVICE DATA
MC44011
GLOSSARY
Aspect Ratio - The ratio of the width of a TV screen to the
height. In standard TVs, it is 4:3. In HDVT it will likely be 16:9.
Front Porch - The blanking time immediately before the
sync signal.
Back Porch - The blanking time after the sync signal during
which the color burst is inserted.
Horizontal Sync - The negative going sync pulses at the
beginning of each line. The pulses indicate to the circuit to
begin sweeping the dot across the screen.
Blank, Pedestal- The signal level which is either at black, or
slightly more negative than black ("blacker-than-black"), and
is used to turn off the screen dot during retrace. Also referred
to as the pedestal.
Brightness - A measure of the dc levels of the luma
component. Changing brightness will change the minimum
and maximum luma levels together.
Burst - The 8 to 10 cycle sine wave which is inserted in the
back porch. It's frequency is the color subcarrier (3.58 MHz
or 4.43 MHz), and is used as a phase reference for the color
decoder.
Burst Gate - A signal identifying the time during which the
burst signal occurs.
C, Chrominance - The color component of the video signal.
The color is determined by the phase of the chrominance
component relative to the burst signal.
Clamping - A process which establishes a fixed dc voltage
level, usually during the back porch time.
Color Difference Signals - B-Y, R-Y, also designated as
U and V.
Color Decoder - A circuit which separates composite video
into Red, Blue, and Green, luminance, and sync signals.
Color Encoder - A circuit which combines Red, Blue, and
Green, luminance, and sync signals into composite video.
Comb Filter - A multi-bandpass filter which separates the
luma and chrominance components from the video signal,
without sacrificing bandwidth.
Component Video, VUV - A format whereby the video
information is kept as separate luma, R-Y, and B-Y signals
(YUV). U is the same as B-Y, and V is the same as R-Y.
Composite Sync - A sync signal which combines horizontal
and vertical sync information. The waveform is made up of
regularly spaced negative going pulses for the horizontal
sync, and then half-line pulses and polarity reversal to
indicate the vertical sync and retrace time.
CompOSite Video - The video signal which consists of sync,
back porch, color burst, video information (Iuma and
chroma), and front porch. This is the signal normally
broadcast by TV stations.
Contrast - A measure of the difference between minimum
and maximum luma amplitudes. Increasing contrast
produces a "blacker" black and a "whiter" white.
dB - A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:
10 x log (Pl/P2) for power measurements, and
20 x log (V1N2) for voltage measurements.
Field - One of the two or more equal parts into which a frame
is divided in an interlaced system.
Frame - The information which makes up one complete
picture. It consists of 525 lines in NTSC systems, and
625 lines in PAL systems. An interlaced system is typically
composed of two fields.
MOTOROLA ANALOG IC DEVICE DATA
Hue - A measure of the correctness of the colors on a
screen.
Interlaced System - A method of generating a picture on the
screen whereby the even number lines are processed, and
then the odd number lines are processed, thereby
completing a full picture.
IRE - Abbreviation for International Radio Engineers, it is the
amplitude unit used to define video levels. In standard NTSC
signals, blank-to-white is 100 IRE units, and blank-to-sync
tip is 40 IRE units. In a 1.0 Vpp signal, one IRE unit is
7.14mV.
Luma, V - The brightness component of the video signal.
Usually abbreviated "Y", it defines the shade of gray in a
black-and-white TV set. In color systems, it is composed of
0.30 red, 0.59 green and 0.11 blue.
NTSC - National Television System Committee. This
committee set the color encoding standards and format for
television broadcast in the United States.
PAL - Phase Alternating Line. A color encoding system in
which the burst is alternated 90 0 each line to help
compensate for color errors which may occur during
transmission. This system is popular mainly in Europe.
Pixel- The smallest picture element, or dot, on a screen. It is
determined by the design of the CRT, as well as the system
bandwidth.
R-V, B-V - Referred to as color difference signals. These
are two of the three signals of component video. When
combined with Y, the full color and luminance information is
available.
Retrace - The rapid movement of the blanked dot from the
screen's right edge to the left edge so it can start scanning a
new line. It is also the rapid movement from the lower right
corner to the upper left corner during vertical blanking.
RGB - The three main colors (red, blue, green) used in the
acquiring, and subsequent display of a video signal.
S-VHS - A format whereby the video information is kept as
separate luma and chroma signals (Y and C).
Sandcastle - A signal which indicates the horizontal
blanking time. It encompasses the front porch, sync, and
back porch. Two amplitudes distinguish the front porch +
sync time from the back porch.
Saturation - A measure of the intensity of the color on a
screen. Also related to its purity.
Sync Separator - A circuit which will detect, and output, the
sync signal from a composite video waveform.
Vertical Sync - The synchronizing signal which indicates to
the circuitry to drive the dot to the upper left corner of the
screen, thereby starting a new field. This signal is derived
from the composite sync.
9-323
II
•
®
MOTOROLA
MC44030
MC44035
Product Preview
Multistandard Video Signal
Processor with Integrated
Chroma Delay Line
The MC44030/35 is a highly advanced circuit which performs most of the
basic functions required for a color TV. All its advanced features are under
processor control via 12C bus, enabling potentiometer controls to be
removed completely and allowing significant cost savings together with the
possibility of implementing sophisticated automatic test routines.
MULTISTANDARD
VIDEO SIGNAL PROCESSOR
WITH INTEGRATED
CHROMA DELAY LINE
SEMICONDUCTOR
TECHNICAL DATA
A summary of the features available on the device is given below:
• Operation from a Single 5.0 V Supply; Low Current Consumption
(Typically 150 mAl
• PAUSECAM/NTSC Decoding Capability (4 Matrix Modes Available)
• Integrated Chroma Delay Line
• Dl1al Composite Video or S-VHS Inputs
• Integrated Luma and Chroma Filters (Including SECAM Cloche Filter)
• Programmable Luma Delay and Peaking
• RGB Drives Including CONTRAST/BRIGHTNESS Controls and Auto
Grey-Scale
PSUFFIX
PLASTIC PACKAGE
CASE 711
• External RGB and Fast Commutate Inputs with SATURATION Control
Possibility
• Auxiliary y, R-Y, B-Y Inputs
• Line Timebase Featuring H-PHASE Control and Switchable Phase
Detector Gain
• Countdown Type Vertical Timebase Including the Vertical Geometry
Corrections
FTSSUFFIX
PLASTIC PACKAGE
CASE 824D
(TQFP--44)
• 16:9 Display Mode Capability
• E-W Parabola .Drive Including the Horizontal Geometry Corrections
• Anode Current Monitor with Vertical Breathing Compensation
• Analog Contrast Control, Allowing Fast Beam Current Limitation
• Pin to Pin Compatible with MC44002/7
• MC44035 is the PAUNTSC Only Version of the MC44030
• Available in DIP and TQFP Packages
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
Plastic DIP
MC44030P
TQFP--44
MC44030FTB
TA = 0' to +70'C
MC44035P
MC44035FTB
9-324
Plastic DIP
TQFP--44
MOTOROLA ANALOG IC DEVICE DATA
MC44030 MC44035
Simplified Block Diagram
R-V
Video I
(S-VHS)
Video 2
B-V
VI
~
Red
Green
I
J
Blue
II
~ I~~
I
5.0V
Analog
Output
12
H-Orive
H-Flyback
Pulse
5.0V
NOTE: Pin numbers shown are for the DIP package.
This device contains 6360 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
9-325
®
MOTOROLA
MC44144
Subcarrier Phase-Locked Loop
The MC44144 is a gated phase-locked loop intended for, but not
restricted to, video applications. The integrated circuit contains a gated
phase detector, voltage controlied crystal osciliator, divide-by-4 circuitry,
and a video clamp. This device provides a 4X reference frequency output,
and a 1X reference frequency output.
The MC44144 is manufactured using Motorola's high density, bipolar
MOSAICTM process.
SUBCARRIER
PHASE-LOCKED LOOP
SEMICONDUCTOR
TECHNICAL DATA
• 8-Pin DIP or Surface Mount Package
• Gated-Phase Detector
• Single Pin Voltage Controlied Crystal Osciliator
• 1X and 4X Subcarrier Output
• Operates
Off of a Standard 5.0 V Supply
PSUFFIX
PLASTIC PACKAGE
CASE 626
DSUFFIX
PLASTIC PACKAGE
CASEl51
(S0-8)
II
Representative Block Diagram
PIN CONNECTIONS
+ 5.0
Voltage
Reference
2.6V
Subcarrter
Output
Vcc 8
Gnd
Burst
Gate
7
3
Phase
Detector
Output
Comp
Video
Input
6
4
4XSub
Xtal
Video Clamp
4XRef
Out
4X
Subcarrier
Output
Divideby4
(Top View)
ORDERING INFORMATION
Device
Subcarrier
Output
Package
MC44144D
MC44144P
9-326
Operating
Temperature Range
Plastic
MOTOROLA ANALOG IC DEVICE DATA
MC44144
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
6.0
Vdc
0° to +70
°c
Supply Voltage
Operating Ambient Temperature
TA
Storage Temperature Range
Tstg
-65to+150
°c
TJ
+150
°c
Operating Junction Temperature
RECOMMENDED OPERATING CONDITIONS
Pin
Symbol
Min
TyP
Max
Supply Voltage
Characteristic
8
VCC
4.5
5.0
5.5
Composite Video Input (Note 1)
Burst Amplitude to Acquire Lock
6
Unit
Vdc
mVpp
-
50
300
1000
Pin
Min
Typ
Max
8
8.0
10
12
mA
7
3.0
-
-
Vdc
1.5
20
-0.5
IJ.A
mVpp
NOTE: 1. Total peak-to-peak voltage of video should not exceed ground or VCC.
ELECTRICAL CHARACTERISTICS (VCC =5.0 Vdc, TA =25°C)
Characteristic
Operating Current
Burst Gate Threshold VoHage:
VIH
VIL
IIH (Vin = 5.0 V)
IlL (Vin = 0 V)
Burst Gate Input Current:
-
4X Subcarrier
Output Voltage: (14.32 MHz)
(17.73 MHz)
Output Impedance: (14.3 MHz and 17.73 MHz)
Unit
-
-
400
610
450
25
650
-
n
300
200
-60
3.0
400
mVpp
-
3
-
±350
±500
-
-
5
-
Subcarrier Output
Output Voltage: (3.58 MHz and 4.43 MHz)
Output Impedance: (3.58 MHz and 4.43 MHz)
Phase Angle (Note 1)
Phase Sensitivity (Notes 1 & 2)
200
1
Static Phase Error (Note 2)
1,2
Phase-Locked Loop PuU-ln Range
Phase-Locked Loop Hold-In Range
-
-
n
deg
Note 2
-
deg/l00 Hz
Hz
NOTES: 1. Referenced to composite video input color burst.
2. See paragraph 1 of the Functional Description text.
Figure 1. Typical VCXO Gain
14.322
17.745 N
:I:
KOPAl
~
/""
14.320
~V
=>
@o
!~ 14.318
"'a:
~-~
14.314
14.312
-1.0
17.740
#
o
KONTSC
gain must be estimated from the
operating point. KOPAL is the gain for
PAL applications and KONTSC is the
gain for NTSC applications.
2.0
@
17.735 !~
'"
;5;~
17.730 e,.u..
~e
1.0
~w
3.0
Frequency
=>
/I ~
14.316
Table 1. Crystal Specifications
5
~
4.0
5.0
~
~
17.7255
j
17.719 ~
6.0
Mode
Frequency Tolerance
@25°C
df/dfo O°C - 70°C
Load Capacitance
ESR
Cl (Intemal Series Capacitance)
14.31818 MHz (NTSC)
17.734475 MHz (PAL)
Fundamental
40 ppm
20pF
500
15mpF
VCO CONTROL VOLTAGE (PIN 3 VOLTAGE) (V)
MOTOROLA ANALOG IC DEVICE DATA
9-327
MC44144
Figure 2. Representative Schematic Diagram
+5.0
Voltage
Reference
2.6V
Video Clamp
4XRef
Out
Dlvldeby4
Subcarrier
Output
FUNCTIONAL DESCRIPTION
II
The MC44144 is designed to implement the color sync
function in a video system. When provided NTSC/PAL
composite video or composite chroma and burst gate inputs,
the IC will phase-lock a Voltage Controlled Crystal Oscillator
(VCXO) to the color burst. Both 4X and 1X subcarrier
frequency outputs are provided by the IC. The VCXO
operates off of a 4X subcarrier crystal and The VCXO
operates off a 4X subcarrier crystal and is capable of at least
± 600 Hz of pull-in. The tradeoff for such a wide pull-in range
is a resultant "soft" lock, or a 3° phase shift per 100 Hz
change in oscillator free-run or input reference frequency.
In addition to providing the gate pulse for the MC44144
phase detector, the Burst Gate input also initiates a clamp
pulse that sets up the level of the composite video at the input
to the Phase Detector. The start and duration of the Gate
Pulse should be timed so that the pulse envelopes the color
burst of the video signal, but not so wide as to gate sync or
video into the Phase Detector.
.
The Phase Detector is enabled when the voltage at the
Burst Gate input (Pin 7) is above the nominal 2.2 V threshold.
While this makes possible the ability to lock to a color burst,
it does not exclude the possibility of lock to a constant
reference. If a constant source is to be the reference, the
Phase Detector can be permanently enabled by holding the
voltage on the Phase Detector input pin higher than the
threshold voltage.
The phase detector gain must be specified in two ways, for
a constant reference and for a burst-locked application. The
gain in a constant reference application is specified by the
maximum current output with the maximum phase error. For
9-328
a maximum phase error of 7tl2 radians the maximum current
available is approximately' 200 flA. So the phase detector
gain is defined as,
KPD
=200/(7tl2)(f1AIrad • sec)
For a burst-locked application, the Phase Detector is
active for only the duration of the color burst. Therefore the
phase detector gain must be specified as an average gain
over a line period. In this case the phase detector gain for
NTSC and for PAL applications is,
KPDNTSC
=(8/(7tl2))(flAlrad • sec) and,
KPDpAL =(7/(7tl2))(flAlrad • sec)
A suitable filter for both types of applications is shown in
the test schematic F~gure 2. This same filter also works for
both NTSC and PAL applications.
The 4X subcarrier Voltage Controlled Crystal Oscillator
(VCXO) uses a design that enables the use of series or
parallel resonant types of crystals. Still, layout and crystal
positioning are critical as the oscillator frequency is sensitive
to shunt capacitance. Care should be taken to keep the
crystal close to the IC and crystal switching should be
avoided. A suitable parallel type crystal would meet the
specifications in Table 1.
A plot showing the VCXO gain is shown in Figure 1. From
this plot the gain must be estimated from the operating point.
KOPAL is the gain for PAL applications and KONTSC is the
gain for NTSC applications.
MOTOROLA ANALOG IC DEVICE DATA
MC44144
PIN FUNCTION DESCRIPTION
Name
Subcarrier
Output
Pin
Representative Circuitry
1
Vee
200
I
I
Description
Expected Waveforms
Subcarrier Output. A
phase-locked reference of the
PAL or NTSC color burst is
output at this pin.
A 300 mVpp square wave is output.
Some high frequency content is
present.
I
I
5.0k
-=
.
Ground
2
Circuit Ground
Phase
Detector
Output
3
The error current from the
phase detector is output at this
pin. A filter circuit should be
connected at this pin.
.~ 1 J,;~
1.0k
31k
33k
,,-1/2 Subcarrier Period ~
I
\\\\\\\.
I
4X Sub Xtal
4
~
,~
'm·i·.~
-
CompOSite
Video Input
(Black Burst,
Continuous
Wave, or
CompOSite
r.hroma
can also be
applied)
6
~
Vref
i
I
5
,\\\\\\\
I--- Line Period-----!
1400
I
4X Subcarrier
Output (or
Black Burst)
A beat waveform, showing both
horizontal period and half the
subcarrier period, is present.
2.Ok
Vee
*+
I
I
,...l
Y
I
I
I
~)
Vee
j
Vlock
Crystal Oscillator Pin. A 4X
subcarrier parallel resonant
crystal, in series with a 5.0 to
25 pF trimmer capacitor
provides the resonant element
for the Voltage Controlled
Crystal Oscillator (VCXO).
Approximately 40 mVpp. A scope
probe will disturb the frequency of
oscillation.
Buffered output from the 4X
voltage controlled oscillator.
The sinusoidal 4Xfsc oscillator output
is available at this pin.
The output is nominally:
525 mVpp for NTSC,
425 mVpp for PAL.
CompOSite Video Input. Color
burst from the video present at
this pin is used as a reference
to phase lock the VCXO.
Positive or negative video may
be used.
Composite video should be applied
at this pin. The color burst
amplitude of the input video should
be at least 50 mY, but no more than
1000 mY. The waveform at this pin
should not exceed ground or V CC.
-J[lJi::
~~
- - - - - - - - GND
Burst Gate
Input
7
I
I
I
I
I
I
VCC
Vee
Input for the phase detector
gate pulse. TTL compatible.
The threshold is nominally
2.6V.
22k
"",J1DJ-
r-22k
~
8
. MOTOROLA ANALOGIC DEVICE DATA
A positive going gate pulse should
be applied at this pin. The Burst Gate
input should envelope the color
burst.
Pin7-=.R----- 2.2V
Power Supply Pin. 5.0 Vdc
should be applied at this pin.
9-329
II
MC44144
Linear and TTL Output Buffers
The output buffers of the MC44144 are not designed to
any specific logic family. If it is desired, Linear or TIL buffers
can be added externally. Figure 3 shows an example of a
Linear buffer using an MC3346 Transistor array; virtually any
utility transistor can be used. Figure 4 shows a TIL type
buffer using an MC74LS04 buffer.
Figure 3. Linear Buffer
14
2
13
MC3346
+S.OV
3
12
4
11
R1
S
Cin
3.3k
4X Subcarrier
lOOOIlF
Output or 1X '--------11--+-----1
Subcarrier ,-------,
Output
+s.OV
10
9
Co
1000IlF
8 1------<----1
E---7 Linear Output
Rs
56
C2
I100PF
Figure 4. TIL Buffer
MC74LS04
C1
4X Subcarrier
O.OlI1F
Output or 1X '--------11---._-1
Subcarrier ,-------,
Output
TTL Output '
9-330
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44145
Pixel Clock Generatorl
Sync Separator
The MC44145, Pixel Clock Generator, is a component of the MC44000
family.
The MC44145 contains a sync separator with composite sync and vertical
outputs, and clock generation circuitry for the digitization of any video signal
along with the necessary circuitry for clock generation, such as a phase
comparator and a divide-by-2 to provide a 50% duty cycle.
The MC44145 is available in a S0-14 package and is fabricated in the
Motorola high denSity, high speed, low voltage, process called MOSAIC 1.5®.
PIXEL CLOCK GENERATOR!
SYNC SEPARATOR
SEMICONDUCTOR
TECHNICAL DATA
DSUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
Representative Block Diagram
Sync Out
VCC
,--J'---..
Div2
f--t~~--~~Aj "-t-ta,1-1EN-1
~~
I
I
I
I
I
I
I
I
I
L"6t---13 -1
VCC
NBACK
!
I
r--
Vc
Charge
Pump
II
Sync Amp
~
i
VCO
2FO
I
II
I
I
I
I
PIN CONNECTIONS
NPD~~: ~
"""...
PLLLoop
Filter
R
CT
r
Clock Out
MOTOROLA ANALOG IC DEVICE DATA
t.~~.A.'.::·~
SyncAmpln 4
Sync Amp Out
Div2 EN
Clock Out 7
(Top View)
Gnd
C2
This device contains 214 active transistors.
~:
Ii::
Video In
14 --~~~---7 ____~J
NPD
Gain
~ PLL Loop Filter
0
1
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC44145D
TA = 0° to +70°C
50-14
9-331
MC44145
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
VCC2
6.0
6.0
V
Tstg
-65 to +150
°c
TJ
+150
°C
Supply Voltage,
Storage Temperature Range
Operating Junction Temperature
NOTE:
ESD data available upon request
RECOMMENDED OPERATING CONDITIONS
Characteristic
Supply Voltage
Video Input Amplitude (Note 2)
Symbol
Pin
Min
Typ
Max
Unit
VCC
VCC2
6
11
4.75
4.75
5.0
5.0
5,5
5.5
Vdc
Vpp
Yin
12
0.4
1.0
2.5
NBACK
13
100
500
-
ns
Fret Pulse Width
Fret
9
100
500
-
ns
Operating Ambient Temperature
TA
-
0
-
+70
°C
NBACK Pulse Width
ELECTRICAL CHARACTERISTICS
I
Characteristic
Symbol
Typ
Max
Unit
-
5.0 to 0
V
-
Ot03.3
-
12
-
VCC/2
Note
Pin
Min
3
3
4
5
POWER SUPPLY
Supply Current (Note 1)
Supply Current
SYNC SEPARATOR (VCC
= 5 0 V· TA = 25°C unless otherwise specified)
II
-
Video Input Sink Current
-
VPin 12< SL
12
-
18
-
Video Input Source Current
-
,VPin 12> SL
12
-
1.2
-
Sync B Output
Sync C Output (1.0 rnA Source)
Slicing Level (SL)
V
V
f!A
f!A
NOTES: 1, Operating currerll for Pin 6 is dependent on the clock frequency (Pin 7), Values given are specified for Pin 14 ~ 4.0 V,
2, Positive Video,
3, High impedance output
4. Low impedance output
9-332
MOTOROLA ANALOG IC DEVICE DATA
MC44145
ELECTRICAL CHARACTERISTICS (continued)
I
Characteristic
Note
Pin
Min
l'iP
Max
Unit
SYNC SEPARATOR (VCC = 5.0 V; TA = 25°C, unless otherwise specified.)
VCO (VCC = 5.0 V; TA = 25°C, unless otherwise specified, divider disabled.)
Fmin
1,5
7,8,14
-
-
10
MHz
Fmax
1,4
7,8,14
39
42
-
MHz
Control Range
2
14
1.0
-
4.0
V
Transfer Function
1
7,8,14
-
14
-
MHzIV
Input Resistance
9
14
0.5
-
-
MQ
Charge Pump
6
7
1,14
-
40
80
-
-
I1A
B
7,9
-
-
3.0
ns
2.4
3.0
-
V
Phase Jitter
INPUT BUFFERS (Fret AND NBACK) (TA = 25°C, unless otherwise specified.)
Threshold (TTL Compatible)
Input Current
OUTPUT BUFFER CLOCK (TA = 25°C, unless otherwise specified.)
Sync Amplifier Output High Level
1.0mA
Source
10
Sync Amplifier Output Low Level
1.0mASink
10
-
0.2
0.4
V
11
10
-
-
6.0
ns
Fall Time
11
10
-
-
6.0
ns
Load Capacitance
10
10
-
15
-
pF
Rise Time
NOTES: 1. Internal divider disabled.
2. 0 V stops the oscillator.
3. Divider +2 active.
4. Ve =4.0V.
II
5. Ve = 1.0V.
6. PFD gain low.
7. PFD gain high.
B. veo alone.
9. Ve = 4.0 V, charge pumps off.
10.2 LSTIL loads.
11. WHh cap load 15 pF and between 10 and 90% of 0.4 and 2.4 V.
MOTOROLA ANALOG IC DEVICE DATA
9-333
MC44145
CIRCUIT DESCRIPTION
Composite Sync Separator
The composite sync separation section is comprised of
two blocks, a sync slicer and a sync amplifier, which can be
used to extract the vertical sync and composite sync
information from a video signal.
The sync separator is an adaptive slicer in which the
video signal is slightly integrated and then sliced at a ratio of
4.7 to 64 which corresponds to the sync to horizontal ratio.
Two outputs are given, one of high impedance and the other
low impedance.
A slicing sync inverting amplifier is also on-chip, allowing
one output to be used for composite sync and the other
output to be integrated and then sliced using the slicing
amplifier to extract the vertical sync information.
Clock Generation
The clock generation is made up of a wide ranging
emitter-coupled VCO followed by a switchable +2 to provide
a 50% duty cycle wherever required, or twice the set
frequency if an external divider is used. The clock generator
is a PLL subsection; its function is the generation of a high
frequency, line locked clock that is used for video sampling
and digitizing.
.
The clock output is a LSTTL-like buffer which has a limited
drive capability of two LSTTL loads.
The VCO is driven from a charge pump with selectable
current. The charge pump is driven by the phase comparator.
The phase comparator is a type IV "phase and frequency
comparator" sequential circuit.
The clock generator, the heart of a PLL, is to be closed by
means of an external divider, thus setting the synthesized
frequency. This divider could be implemented in discrete
logic or be a part of an ASIC subsystem.
Phase and Frequency Comparator
The phase comparator is fed from two input buffers, Fref
which expects a reference frequency at line rate and that is
rising edge sensitive, and NBACK which comes from the
external divider and is falling edge sensitive.
Charge pump current and output divider action are
controlled by applying suitable voltage on the appropriate
pins (respectively, NPD Gain and Div 2 EN).
PIN FUNCTION DESCRIPTION
. Pin
II
Description
Function
1
NPDGain
This pin sets the gain of the phase frequency detector by changing the current of the charge pump
output (40 !LA or 80 !LA). Low current with this pin> 2.0 V, high current for < 0.5 V.
2
Ground
Ground connection common to the PLL and sync separator sections.
3
SyncB
High impedance sync output.
4
Sync Amp In
Sync amplifier input.
5
SyncC
Low impedance sync output.
6
VCC
Power connection to the PLL section.
7
Clock Out
VCO clock output. Capable of limited LSTTL drive. It should not be used to drive high capacitive
loads, such as long PCB traces or coaxial lines.
8
Div2EN
The divider is switched in with this pin> 2.0 V; switched out for < 0.5 V.
9
Fref
Reference frequency input to the phase and frequency comparator. Typically this will be a 15625
(15750) Hz signal. It is rising edge sensitive. Due to the nature of the phase and frequency
comparator, no missing pulses are tolerable on this input. In a typical setup, this signal can be
provided by the MC44011.
10
Sync Amp Out
Sync amplifier output.
11
VCC2
Power connection to the sync separator and amplifier.
12
Video In
Video signal input to the sync separator.
13
NBACK
Fed by the external clock divider. Sets the multiplication ratio of the loop in multiples of the Fref
frequency. Negative edge sensitive.
14
PLL Loop Filter
See loop filter calculations at the end of this document.
NOTE:
9-334
The two Vee pins are not independent, as they are internally connected by means of the input protection diodes; they must always be both connected
to a suitable vee line.
MOTOROLA ANALOG IC DEVICE DATA'
MC44145
CIRCUIT OPERATION
which does not tolerate mlssmg pulses. The dual loop
structure makes up a noise insensitive frequency (and
phase) locked loop.
The phase and frequency comparator provides two logical
outputs. mutually exclusive - up or down - that are used to
source or sink current to and from the loop filter. This current
can be user-selected to be 40 !IA or 80 !IA (typical), thus
providing some degree of loop gain control.
The VCO is an emitter-coupled multivibrator type, with an
on-chip timing capacitor, and has been designed for low
phase noise.
The divide-by-2 is included at the output of the VCO, thus
allowing for a precise 50% duty cycle, hence the VCO is
operating at twice the required frequency. The divider can be
bypassed, bringing the VCO output directly to the output
buffer.
The external divider must provide a feedback pulse to
close the loop; the falling edge of this pulse will be aligned
(when the loop is in lock) with the rising edge of the pulse
applied to the Fref input. Operation of the phase comparator
is insensitive to the duty cycle of both its inputs. The feedback
pulse should have a minimum width of 500 ns. This can be
guaranteed if it has a length of at least 16 output clock cycles
(highest output frequency with the divider disabled).
Composite Sync Separator
The sync separator is an adaptive slicer. It will output
"raw" sync data. Two outputs are given, thus allowing one
output to be used for composite sync and the other output to
be integrated and then sliced using the inverting slicing
amplifier provided. As the input of the slicing amplifier is
external, the amplifier may be driven from either sync output,
although normally the high impedance output (Sync B)
would be recommended.
The positive video input signal required is nominally 1.0 V
sync-ta-white, but the circuit supports signals above and
below this level and also is resistant to a degree of reflections
on the signal. Coupling to the sync separator may be
achieved by a simple capacitor of 100 nF, but better results
may be obtained with a higher value in series with a
resistance of 1.0 kn.
Clock Generator
The system is best put to use in a dual loop configuration;
a first loop locks to line frequency by means of a type I phase
detector (multiplier type) which is insensitive to missing
pulses. This PLL is then followed by a second loop using the
MC44145, performing frequency multiplication. The phase
comparator of the MC44145 is frequency and phase
sensitive. It is a type IV (sequential type) phase detector,
APPLICATION INFORMATION
Analog video signals out of the MC44011 are sampled and
converted to 8-bits digital in the AID converter (MC44250
series) by means of the clock provided by the MC44145,
pixel clock generator (see Figure 1).
The frame store contains the memory, the necessary logic
for the memory addressing, as well as the counter to set the
frequency multiplication ratio of the line locked clock
generator (H. Count).
II
Figure 1. Application Block Diagram
R(Y)
Digital
Multistandard
Decoder
Video
--t~
G(U)
R(Y)
NO
Frame Store
Converter
8 (V)
MC44011
G(U)
8 (V)
MC44250
Pixel Clock
Pixel Clock
Generator
H. Count
Vertical Sync
MC44145
MOTOROLA ANALOG IC DEVICE DATA
9-335
MC44145
Figure 2.
H Sync Out
Video In
C=1S0pF,R=120kQ
Figure 3. Typical VCO Transfer Characteristics
60
N
:c
6
.....
z
50
40
,.....,....
a::
!;;:
>-
,.....,....
30
(.)
Z
au
=>
@
a:
u.
20
10
~
,."
..,....
./"
PinS/LOW -
~
I
o
2.0
1.0
3.0
4.0
PIN 14 VOLTAGE (V)
Figure 4. Sync Separator Timing
Video Input
(Pin 12)
-II-SyncCOut
(PinS)
~
J
0.21J.S
I-
I
k-- ~ 5.0 IlS
1.0 IJ.S
Composite Sync
Input (Pin 12)
--'I--'I--'I--rl--'I I 1 1 1 II
D1 = 9.SIlS--!!--
--'1
Vertical Sync _ _ _ _
Out(Pin 10)
I
--I
1 1 1 1 II
!-- D2= 9.51ls
1. . _______ ::sVv
Note: D1 and D2 depend on the value ofR and C connected 10 Pin 3. They are specified here for the values: R = 120k!l, and C = 180 pF.
9-336
MOTOROLA ANALOG IC DEVICE DATA
MC44145
LOOP FILTER CALCULATION
This section is not intended as a complete loop theory; its
aim is merely to point out the peculiarities of the loop, and
provide the user with enough information for the filter
components selection. For a more in-depth covering, the
cited reference should be consulted, especially [1].
The following remarks apply to the loop:
• The loop frequency is 15 kHz.
• In spite of the sampled nature of the loop, a continuous
time approximation is possible if the loop bandwidth is
sufficiently small.
• Ripple on Vc is a function of the loop bandwidth
• The loop is a type II, 3rd order; however, since C2 is
small, the pole it creates is far removed from the low
frequency dominant poles, and the loop can be analyzed
as a 2nd order loop.
These remarks apply to the PFD:
• Phase and frequency sensitive.
• Independent of duty cycle.
• PFD has 3 allowed states: up, down, hi-Z
• The VCO is always pulled in the right direction (during
acquisition).
• PFD gain is higher near lock.
The last two remarks imply that only the higher value need
be taken into account, as acquisition will be slower, but
always in the proper direction, whereas the higher gain will
enter the action as soon as the error reaches ±2lt.
The following values are selected and defined (see Block
Diagram):
C2 = C/1 0 or less, to satisfy the requirement that the effect
of C2 on the low frequency response of the loop be minimal,
and similar to a second order loop.
MOTOROLA ANALOG IC DEVICE DATA
I; =0.707 for the damping factor.
roi =15625 x 2lt the input pulsation.
1: =RC as the loop filter.
K =Ko x Ip x R/(2 x It x N) the loop gain.
K' =K x 1: =41;2 is the "normalized" loop gain.
Ko =57 x 106 [radlVs] (9.0 MHzIV).
Stability analysis, with C2 =C/10 and K' =2 (I; =0.707)
gives a minimum value of 7.5 for the ratio roilK and to have
some margin, a reasonable value can be 15 to 20 or higher [1].
Selecting roilK =20, gives: K =roi/20 ~ 5000.
With K' =2, 1: =21K =400 I1s.
Using K =Ko x Ip x R/(2 x It x N) and setting Ip =60 pA,
and N an average value of 1000, we get R =9.1 kn.
Then for 1: =400 I1s, C becomes 47 nF and C2, 4.7 nF.
With these values, the loop natural frequency (ron) and the
loop bandwidth (r03dB) can be calculated:
ron =[(Ko/N) x Ip/(2ltC)1/2 =3400 and
fn =3400/2lt = 540 Hz.
ro3dB =2 x ron =1080 Hz (valid if I; is close to 0.707).
References:
[4] Charge-Pump Phase-Lock Loops, Floyd M. Gardner,
IEEE transactions on communications, vol. com-28
no. 11 November 1980
[5] Phaselock Techniques, Floyd M. Gardner, J. Wiley &
Sons, 1979
[6] Phase-Locked Loops, Roland E. Best, McGraw-Hili,
1984
[7] Phase-Locked Loop Systems, Motorola
9-337
Ij
®
MOTOROLA
MC44353
MC44354
MC44355
Product Preview
PLL Tuned UHF Audio/Video
Modulator ICs for.PAL, SECAM
and NTSC TViSystems
MC44353 - Multi-5tandard Modulator IC
MC44354 - PAUNTSC Modulator IC
MC44355 - PAUNTSC Modulator IC with
Fixed Video Modulation Index
MULTI-STANDARD
ANDPAUNTSC
MODULATOR ICs
SEMICONDUCTOR
TECHNICAL DATA
These modulator circuits are intendEid for use in VCRs, satellite receivers,
set-top boxes, video games, etc. An on-chip high speed 12C compatible bus
receiver is included and is used to set the channel, tuned by a PLL over the
full range in the UHF bands. The modulator incorporates a sound subcarrier
oscillator, using a second PLL to derive 4.5, 5.5, 6.0 and 6.5 MHz carrier
frequencies, selectable by the bus.
For the sound, either frequency modulation with pre--emphasis or
amplitude modulation (MC44353 only) is possible. A control bit (MC44353
only) i~ used to select AM sound with positive RF modulation (system L). The
level of the sound carrier with respect to the vision carrier and the modulation
depth of both sound and vision may be adjusted by means of the bus. In
addition, an on-chip video test pattern generator may be switched in with a
1.0 kHz audio test signal.
DTBSUFFIX
PLASTIC PACKAGE
CASE 948E
(TSSOP-20)
• UHF Operation (471 MHz to 855 MHz)
II
• On-Ghip Low Power Operational Amplifier for Direct Tuning Voltage
Output
• Single-Ended Output for Low Cost and Ease of Interface
• Low External Component Count
DWSUFFIX
PLASTIC PACKAGE
CASE751D
(S0-20L)
• High Speed 12C Bus Compatible (Min 500 kHz)
• Programmable Video Modulation Depth (8 Steps of 2.5%)
• Programmable Picture/Sound Carriers Ratio and Audio Sensitivity
(8 Steps of 1.0 dB)
• Programmable Sound Subcarrier Oscillator (4.5 MHz to 6.5 MHz)
• Video Test Pattern Generator with Sound Test Signal (1.0 kHz)
• VCC Standby Mode (Typ 500 IJA)
PIN CONNECTIONS
• Transient Output Inhibit During PLL Lock-Up at Power-0n
Xtal
PHD
OpOut
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
SDA
SCL
VCCD
OscGnd
GndMod
Osc1
VCC Mod
MC44353DTB
TSSOP-20
OscGnd
GndMod
MC44353DW
S0-20L
SndFill
Video In
MC44354DTB
TSSOP-20
SndTun
MC44354DW
S0-20L
Pre-Em
VCCA
Audio In
MC44355DTB
TSSOP-20
MC44355DW
S0-20L
9-338
TA = -20° to +80°C
(Top View)
MOTOROLA ANALOG IC DEVICE.DATA
MC44353 MC44354 MC44355
Typical Application
VCC2 (30 V)
0.1
I
560k
OpOut
SDA} High
Speed
I--C>--------o SCL Bus
3
5.0V
47k
VCCD
4
Gnd
-=-
5
1-0--+-0'-'-------0 5.0 V
Oscl
HVU202APOOO
(Note2)
6
r-~-----01
r-----O TV Out
0sc2
7
47 k
-=-
33 k
-=-
75Q±1%
13
8
SndFilt
Video
Clln
12
9
SndTun
10
0.01
VCCA I-O---~---o 5.0 V
I 0.1
11
~Audioln
0.1
1
1.Ok
5.0 V o-.......~ I4H>--I~
II
220
NOTES: 1. Cx depends on Crystal Load Capacitance, Crystal resistance < 200 n
2. Tubular 0603 1000 pF capacttors.
3. UHF Coil is a surface mount 0605 Chip Inductor, REF: AVXlKYOCERA - LOB05 6RB DEW ±D.S nH
(@ 450 MHz Q = 43, @ 900 MHz Q = 62 and L = 7.0 nH)
MOTOROLA' ANALOG IC DEVICE DATA
9-339
MC44353 MC44354 MC44355
MODULATOR FUNCTIONAL DESCRIPTION
General
The device has two main sections; a PLL section to
synthesize the channel frequency of the UHF output and a
modulator section which accepts audio and video inputs and
modulates the UHF carrier with them.
The channel frequency, sound and picture modulation
index and sound/picture carrier ratio are all programmable by
means of a high speed 12C compatible bus. An on-chip video
test pattern generator with an audio test signal is also
included.
The MC44353 is designed to operate as a multi-standard
modulator and can handle the systems B/G, D/K, H, I, Land
N with the same external circuit components.
Figure 1. MC44353 Simplified Block Diagram
GndMod
SOO Fill
Snd Tun
8
9
16
Vee Mod Standby f'1-1--.....".A"~
Gnd.Mod
17
II
3
VeeD
9-340
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44461
Advance Information
Picture-in-Picture
(PIP) Controller
PICTURE-IN-PICTURE
(PIP) CONTROLLER
The MC44461 Picture-in-Picture (PIP) controller is a member of
Motorola's low cost PIP family. It is NTSC compatible and contains all the
analog signal processing, control logic and memory necessary to provide for
the overlay of a small picture from a second non synchronized source onto
the main picture of a television. All control and setup of the MC44461 is via a
standard two pin 12C bus interface. The device is fabricated using BICMOS
technology. It is available in a 56-pin shrink dip (SDIP) package.
SEMICONDUCTOR
TECHNICAL DATA
The main features of the MC44461 are:
• Two NTSC CVBS Inputs
• Switchable Main and PIP Video Signals
• Single NTSC CVBS Output Allows Simple TV Chassis Integration
• Two PIP Sizes; 1/16 and 1/9 Screen Area
• Freeze Field Feature
• Variable PIP Position in 64-X by 64-V Steps
• PIP Border with Programmable Color
• Programmable PIP Tint and Saturation Control
BSUFFIX
PLASTIC PACKAGE
CASE 859
(SDIP)
• Automatic Main to PIP Contrast Balance
• Vertical Filter
• Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI
• Minimal RFI Allows Simple Low Cost Application into TV
ORDERING INFORMATION
• 12C Bus Control - No External Variable Adjustments Needed
• Operates from a Single 5.0 V Supply
• Economical 56-Pin Shrink DIP Package
Device
Operating
Temperature Range
Package
MC44461B
TJ = -65' to +150'C
SDIP
For surface mount package availability, contact your local
Motorola sales office or authorized distributor.
CompOSite Video Simplified System Diagram
L
CV
'.'
Till1f:lrnF
-
...
CVin
VkW>
Processor
'--------- CV1
Back Panel (i}
Composite •
Video Input
r-----
f-R
C+G
!-8
PIP
MC44461
CV2
~
MOTOROLA ANALOG IC DEVICE DATA
~41
MC44461
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
VDD
-0.5 to +6.0
V
Power Supply Vo~age
VCC
-0.5 to +6.0
V
Input Voltage Range
VIR
-0.5,
VDD+0.5
V
10
160
mA
Po
RaJA
1.3
59
W
°CIW
TJ
-65 to +150
°C
Output Current
Power Dissipation
Maximum Power Dissipation @ 70°C
Thermal Resistance, Junction-ta-Air
Junction Temperature (Storage and Operating)
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = VDD = 5.0 V, TA = 25°C, unless otherwise noted.)
I
I
Characteristic
POWER SUPPLY
Total Supply (Pins 8, 15, 43 and 50)
I
Symbol
I
I
Total ISupply
I
Min
Typ
Max
Unit
100
160
rnA
VIDEO
CVi
-
1.0
-
Vpp
Composite Video Output (Pin 49, ynterminated)
-
-
2.0
-
Vpp
Video Output DC Level (Sync Tip)'
-
-
Video Gain
-
Video Frequency Response (Main Video to -1.0 dB)
-
-
Composite Video Input (Pin 34 or 36)
II
-
Vdc
10
-
MHz
-
±4.0
-
deg
-
55
55
-
1.0
6.0
dB
Color Bar Accuracy
-
Video Crosstalk (@ 75% Color Bars)
Main to PIP
PIP to Main
-
Output Impedance
-
-
5.0
-
n
dB
HORIZONTAL TIMEBASE
Free Run HPLL Frequency (Pin 16)
-
-
15734
-
Hz
HPLL Pull-In Range
-
-
±400
-
Hz
HPLLJitter
-
-
±4.0
-
ns
Burst Gate Timing (from Trailing Edge Hsync, Pin 24)
-
-
1.0
-
I1S
Burst Gate Width
-
-
4.0
-
I1S
Resolution
-
-
6
-
Bits
Integral Non-Linearity
-
-
±1
-
LSB
VERTICAL TIMEBASE
Vertical Countdown Window
Vertical Sync Integration Time
ANALOG TO DIGITAL CONVERTER
Differential Non-Linearity
-
-
+21-1
-
LSB
ADC - Y Frequency Response @ -5.0 dB
-
-
1.0
-
MHz
ADC - U, V Frequency Response @ -5.0 dB
-
-
200
-
kHz
Sample Clock Frequency (4/3 FSC)
-
-
4.773
-
MHz
9-342
MOTOROLA ANALOG IC DEVICE DATA
MC44461
ELECTRICAL CHARACTERISTICS (continued) (VCC = VDD = 5.0 V, TA = 25°C, unless otherwise noted.)
I
I
Characteristic
I
Symbol
Min
I
Max
Typ
Unit
DIGITAL TO ANALOG CONVERTER
-
Resolution
Differential Non-Linearity
-
Tint DAC Control Range (in 64 Steps)
-
Saturation DAC Control Range (in 64 steps)
-
Integral Non-Linearity
-
-
6
Bits
±1
-
LSB
+21-1
-
LSB
±10
-
Deg
±B.O
dB
NTSC DECODER
Color Kill Threshold
-
-
-241-16
Threshold Hysteresis
-
3.0±1.0
ACC (Chroma Amplitude Change, +3.0 dB to -12 dB)
-
-
-
114
71
-
84
-
±D.5
dB
dB
dB
PIP CHARACTERISTICS
PIP Size
1/9 Screen Horizontal
1/9 Screen Vertical
1/16 Screen Horizontal
1116 Screen Vertical
-
53
-
Border Size Horizontal
-
-
3
-
pels
Border Size Vertical
2
-
lines
-
-
pels
lines
pels
lines
-
-
Output PEL Clock (4 FSC)
-
-
MHz
-
-
14.318
Position Control Range Horizontal (% of Main Picture), 64 Steps
100
-
%
Position Control Range Vertical (% of Main Picture), 64 Steps
-
-
100
-
%
Figure 1. Representative Block Diagram
De~PS
r-------------
1
41
J.g
ADCMid-Ref
---------,1
51
28
I----r''o Sync Sep
31'O H Pll
1-_-t",
Video 1036""-!-_-+I
341
Vidoo2~T_-_L~~~
DecoderACC
Hin
Vin
SCl
SDA
Reset
10
Vid 112Sel
30
Multi Test
MainOut
Decoder Xlal
Decoder Pll
16 FSC Pll
Encoder Phase
EncoderACC
52
Encoder
PLL
~:Oder En~aps
This device contains approximately 500,000 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
9-343
MC44461
Figure 2. Application Circuit
5.0V 5.0 V
Honzln
Vert In
12C Ser CI
12C Ser Data
_ _-'VIi'r'!'1.0""k'--t--;
_ _-'VIi'v7'1.0..,kc--"
_~'W'.,...cl',:-O!!.,k---,
_ _-'l/lJ'v-"'1.0~k'--1
0.D1
MC44461
0.01
5.0 V _-JIN'...--,
Encoder V Cap
54
0.01
Encoder U Cap
Endoder YCap
N/C
~~----~~--~
":'
1000
100
5.0 V - -......---2.5 Vpp @ 4.5 V VCC) is used to avoid potential
noise problems.
Figure 5. NTSC Decoder
U
v
In
Byte 1: YO(5:0), V(1 :0)
Byte 2: Y1(5:0), V(3:2)
Byte 3: Y2(5:0), V(5:4)
Byte 4: Y3(5:0), U(1:0)
Byte 5: Y4(5:0), U(3:2)
Byte 6: Y5(5:0), U(5:4)
Refer to the block diagram. Both the video inputs are
applied to an input switch which is controlled by the 12C bus
interface. Either of the inputs is applied to the PIP processing
circuitry and either to the main video signal path of the output
switch. The signal applied to the PIP processor also provides
the vertical sync reference to the PIP processor.
The PIP output from the switch is applied to a 1.0 MHz
cutoff low pass GmC biquad filter to extract the luminance
Signal and a similar bandpass filter to pass chroma to the
9-352
The NTSC Decoder (Figure 5) consists of two multipliers,
a voltage controlled 4 X SIC crystal oscillator/divider,
Automatic Color Control (ACC) block, Color Kill circuit and
necessary switching. During Burst Gate time, the ACC block
in the NTSC Decoder is calibrated with respect to burst
magnitude by applying the output of multiplier 1 to the
reference input of the ACC block. The result is U and V
outputs which are 0.6 V ± 0.5 dB for burst amplitudes varying
from -12 dB to 3.0 dB. The second multiplier serves as a
phase detector during color burst to match the 90 degree
output from the XVCO to the 180 degree color burst and feed
MOTOROLA ANALOG IC DEVICE DATA
MC44461
a correction current to the PLL filter. The phase is correct
when the two signals are 90 degrees out of phase.
During the H drive time, the output of the multipliers is fed
to the YUV clamp, filtered to 200 KHz and input along with the
Y signal to the multiplexer.
The YUV samples are fed through a multiplexer to a single
six bit AID converter. The AID is a flash type architecture and
is capable of digitizing at a 20 MHz sample rate. It is
comprised of an internal bandgap source voltage reference,
a 64 tap resistor ladder comparator array, a binary encoder
and output latches. Once the multiplexer has switched,
sufficient time is provided to allow the AID converter to settle
before the reading is latched. The encoder code is
determined from the values of any comparators which are not
metastable.
The multiplexer and AID converter receive and convert the
YUV data at a 4FSC/3 rate for a 1/9th size picture or FSC for
a 1/16th size picture. The samples are taken in the following
way to simplify the control logic:
Y,V,Y,U,Y,V,Y,U
To provide a 6:1:1 format, one of three U and V samples is
saved to memory giving a luminance sample rate of 2FSC/3
for a 1/9th picture and Fscl2 for a 1/16 picture. In the vertical
direction, one line of every 3 (1/9th picture) or 4 (1/16th
picture) are saved. In order to avoid objectionable artifacts, a
piece-wise vertical filter is used to take a weighted average
on the luminance samples. For three lines (1/9th size) the
weight is 1/4 + 1/2 + 1/4 and for four lines (1/16 size) it is
1/4 + 1/4 + 1/4 + 1/4. This filter also delays the luma samples
correcting for the longer chroma signal path through the
decoder.
Finally the logic incorporates a field generator to
determine the current field in order to correct interlace
disorders arising from a Single field memory.
A separate process runs in the logic section to create the
PIP window on the main picture. Control signals are
generated and sent to the memory controller to read data
from the field memory. Data from the eight bit memory are
then de-multiplexed into a six bit YUV format, borders are
added, blanking is generated for the video clamps and sent to
the Y, U and V DACs. Since the PIP display is based on a
data clock, it is important to minimize the main display clock
skew on a line by line basis. Skew is minimized in the
MC44461 by reclocking the display timebase to the nearest
rising or falling edge of a 16FSC clock. This produces a
maximum line to line skew of approximately 8.0 ns which is
not perceptible to the viewer. The PIP write logic also
incorporates a field generator for use by the memory
controller for interlace disorder correction. Interlace disorder
can occur when the line order of the two fields of the PIP
image is swapped due to a mismatch with the main picture
field or due to an incomplete field being displayed from
memory. The main and PIP field generators, along with
monitoring, when the PIP read address passes the PIP write
address, allows the read address to the memory to be
modified to correct for interlace disorder.
The read logic can provide various border colors: black,
75% white (light gray), 50% white (medium gray), red, green,
MOTOROLA ANALOG Ie DEVICE DATA
blue or transparent (no border). In a system without an
adaptive comb filter, borders which contain no chroma give
the best results. Also built into the read logic is a PIP fill mode
which allows the PIP window to be filled with either a solid
green, blue or red color as an aid in aligning the PIP analog
color circuitry.
Because the DAC output video will be referenced during
back porch time, the read processor zeroes the luminance
value and sets the bipolar U and V values to mid-range
during periods outside the PIP window to ensure clamping at
correct levels. Since the PIP window is positioned relative to
the main picture's vertical and horizontal sync, a safety
feature turns off the window if the window encroaches upon
the sync period, thus preventing erroneous clamping.
The Y, U and V DACs are all three of the same design. A
binary weighted current source is used, split into two, three
bit levels. In the three most significant bits, the current
sources are cascaded to improve the matching to the three
least significant current sources. Analog transmission gates,
switched by the bi-phase outputs of the data latches, feed
the binary currents to the single ended current mirror. The
output current is subsequently clamped and filtered for
processing buy the NTSC Encoder.
The outputs of the U and V DACS are buffered and burst
flag pulses added to both signals. The U burst flag is fixed to
generate a -180 0 color burst at the modulator output. The V
burst flag is variable under the control of an internal register
set through the 12C bus to provide a variable tint. Saturation is
controlled by varying a register which sets the reference
voltage to the U and V DACs. This is also under 12C bus
control. By oversampling the U and V DACs, it was possible
to use identical post-DAC filtering for Y, U and V, thereby
reducing the delay inequalities between Y and UV and also
simplifying the design. After filtering, the U and V signals are
clamped to an internal reference voltage during horizontal
blanking periods and fed to the U and V modulators. In the
NTSC Decoder, the Y, U and V signals were scaled to use the
entire AID range. Gain through the NTSC Encoder is set to
properly match these amplitudes.
The phase of the re-encoded chrominance must match
that of the incoming main video signal at the input to the PIP
switch, so a separate first order PLL is placed within the loop
of the main video signal burst PLL. The first order PLL
compares the phase of the main burst with that of the
encoded burst and moves the oscillator phase so that they
match. A special phase shift circuit allowing a continuous
range of 1800 was developed to do this.
The amplitude of the re-encoded chrominance Signal
must also match that of the main video signal. To do this, a
synchronous amplitude comparator looks at both burst
signals and adjusts the chrominance amplitude in the
modulator section of the NTSC encoder. The Y signal from
the YDAC is compared to the main video Signal at black level
during back porch time and clamped to this same black level
voltage. The PIP chrominance and luminance are then
added together and fed to the PIP output switch through a
buffered output.
9-353
®
MOTOROLA
MC44462
Product Preview
Y -C Picture-in-Picture
(PIP) Controller
V-C PICTURE-IN-PICTURE
(PIP) CONTROLLER
The MC44462 V-C PIP controller is a low cost member of a family of high
performance PIP controllers and video signal processors for television, It is a
follow-up to the MC44461 PIP and has a modified input selection to allow
higher performance in TV systems which have S-Video inputs on the back
panel. The S-Video input is separate luma (luminance) and chroma
components. It is NTSC compatible and contains all the analog signal
processing, control logic and memory necessary to provide for the overlay of
a small picture from a second non synchronized source onto the main picture
of a television. All control and setup of the MC44462 is via a standard two pin
12C bus interface. The device is fabricated using BICMOS technology. It is
available in a 56-pin shrink dip (SDIP) package.
SEMICONDUCTOR
TECHNICAL DATA
The main features of the MC44462 are:
• Switchable PIP CompOSite Video Signals - Video 1 and Video 2
• S-Video Output Allows High Performance in TV
• Two PIP Sizes; 1/16 and 1/9 Screen Area
• Freeze Field Feature
• Variable PIP Position in 64-X by 64-V Steps
• PIP Border with Programmable Color
BSUFFIX
PLASTIC PACKAGE
CASE 859
(SDIP)
• Programmable PIP Tint and Saturation Control
• Automatic Main to PIP Contrast Balance
• Vertical Filter
• Integrated 64 k Bit DRAM Memqry Resulting in Minimal, RFI
ORDERING INFORMATION
• Minimal RFI Allows Simple Low Cost Application into TV
Device
Operating
Temperature Range
Package
'MC44462B
TJ = -65° to +150°C
SDIP
• 12C, Bus Control - No External Variable Adjustments Needed
• Operates from a Single 5.0 V Supply
• Economical 56-Pin Shrink DIP Package
YC-PIP System Diagram
-
cv
~
Tuner/If
Comb
Filier
(MC14i625)
s
~ w'
r--4
M
T
R
X
=Y
Back Panel ,!.
S--VHS Inputs f!!)'C
Back Panel
'i'CV
Composite
Video Input
~
9-354
cv
~
Main
(unused)
VIdeo
-+ R
Processor '-+ G
Ymain in
Cmainin
YCPIP
MC44462
Ymainoul
Cmainout
Yln
-+ B
em
CVl
CV2
MOTOROLA ANALOG IC DEVICE DATA
MC44462
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
VDD
- 0
Register 05h': 00-07 -> 01 h
Replay PIP (RPIP) Operation
In sequence, the Capture Ready mode must be first
activated, allowing up to 8 seconds of fill memory wi1h the
desired video stream. Then the Capture mode must be set,
disabling further write to memory. The Capture data may be
re-displayed at any time afterword.
Multiple PIP (MPIP) Operation
Capture Ready
Register 05h : 00-03 -> 0
Register 05h : 00-03 -> 07h or OFh
Register OBh : 06 -> 0, 02 -> 1, 00-01 -> 0 to 3
Register 04h : 00-01 -> 0 to 3
Capture
Register OBh : 06 -> 0
Register OBh : 06 -> 1, 02 -> 0, 04-05 -> 0 to 3
Register OCh : 05 -> 1, 02 -> 0 or 1 (Optional)
Register 05h: DO -> 1
9-366
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44817/17B
PLL Tuning Circuits
with 3-Wire Bus
The MC44817/17B are tuning circuits for TV and VCR tuner applications.
They contain on one chip all the functions required for PLL control of a VCO.
The integrated circuits also contain a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz.
The MC44817 has programmable 51211024 reference divider while the
MC44817B has a fixed reference divider of 1024.
The MC44817/17B are manufactured on a single silicon chip using
Motorola's high density bipolar process, MOSAICTM (Motorola Oxide Self
Aligned Implanted Circuits).
TV AND VCR
PLL TUNING CIRCUITS
WITH 1.3 GHz PRESCALER
AND 3-WIRE BUS
SEMICONDUCTOR
TECHNICAL DATA
• Complete Single Chip System for MPU Control (3-Wire Bus). Data and
Clock Inputs are IIC Bus Compatible
• Divide-by-B Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
• Reference Divider: Programmable for Division Ratios 512 and 1024.
The MC44817B has a Fixed 1024 Reference Divider
• Tri-State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output (30 V)
DSUFFIX
• Four Integrated PNP Band Buffers for 40 rnA (VCC1 to 14.4 V)
PLASTIC PACKAGE
CASE 751B
(S0-16)
• Output Options for the Reference Frequency and the
Programmable Divider
• Bus Protocol for 18 or 19 Bit Transmission
• Extra Protocol for 34 Bit for Test and Further Features
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
PIN CONNECTIONS
• Fully ESD Protected
0
DA
16
EN
MOSAIC is a trademark of Motorola, Inc.
ORDERING INFORMATION
Device
2
15
Lock
XTAL
3
14
VCC3 12V
Amp In
4
13
B3
VTUN
5
12
B2
6
11
B1
Operating
Temperature Range
Package
VCC233 V
TA = -20° to + 80°C
S0-16
VCC1 5.OV
MC44817D
MC44817BD
CL
BO
HFln
Gnd
(Top View)
MOTOROLA ANALOG IC DEVICE DATA
9-367
MC44817/17B
Representative Block Diagram
Bands Out 30 mA
(40 rnA at 0° to BO°C)
VCCl
5.0V
VTUN
VCC3
7
13
12 11
10
14
12V
6
/+f-_ _ _40 Amp In
Gnd
9
Lock
16
D!t~o-:l---+--~
2 -I-~~;::::;:':::""~
CIOCkcr-
XTAL
II
Preamp 2
This device contains 3,204 active transistors.
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Pin
Value
Unit
7
6.0
V
Band Buffer "Off' Voltage
10-13
14.4
V
Band Buffer "On" Current
10-13
50
mA
Band Buffer - Short Circuit Duration (0 to VCC3) (Note 2)
10-13
Continuous
-
6
40
V
Operational Amplifier Short Circuit Duration (0 to VCC2)
5
Continuous
-
Power Supply Voltage (VCC3)
14
14.4
V
Storage Temperature
-
-65 to +150
°C
-20 to +80
°C
10-13
10
sec
Operational Amplifier Output Voltage
5
VCC2
V
RF Input Level (10 MHz to 1.3 GHz)
-
1.5
Vrms
Rating
Power Supply Voltage (VCC1)
Operational Amplifier Power Supply Voltage (VCC2)
Operating Temperature Range
Band Buffer Operation (Note 1) at 50 mA each Buffer
All Buffers "On" Simultaneously
NOTES: 1, At VCC3 = VCC1 to 14.4 V and TA=-20° to + 80°C.
2: At VCC3 = VCC1 to 14.4 V and TA = -20° to +80°C one buffer ·On" only.
MOTOROLA ANALOG IC DEVICE DATA
MC44817117B
ELECTRICAL CHARACTERISTICS (VCCI = 5.0 V, VCC2 = 33 V, VCC3 = 12 V, TA = 25°C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
Unit
VCCI Supply Voltage Range
7
4.5
5.0
5.5
V
VCCI Supply Current (VCCI = 5.0 V)
7
-
37
50
mA
VCC2 Supply Voltage Range
6
25
-
37
V
VCC2 Supply Current (Output Open)
6
1.5
3.5
mA
j.lA
Band Buffer Leakage Current when "Off' at 12 V
10-13
-
0.01
1.0
Band Buffer Saturation Voltage when "On" at 30 mA
10-13
-
0.15
0.3
V
Band Buffer Saturation Voltage when "On" at 40 mA
only for 0° to BO°C
10-13
-
0.2
0.5
V
Data/Clock/Enable Current at 0 V
1,2,16
-10
-
0
~A
Data/Clock/Enable Current at 5.0 V
1,2,16
0
-
1.0
~A
Data/Clock/Enable Input Voltage Low
1,2,16
-
-
1.5
V
Data/Clock/Enable Input Voltage High
1,2,16
3.0
-
V
2
-
-
100
kHz
MHz
Clock Frequency Range
Oscillator Frequency Range
3
3.15
3.2
4.05
Operational Amplifier Internal Reference Voltage
-
2.0
2.75
3.2
V
Operational Ampmier Input Current
4
-15
0
15
nA
DC Open Loop Voltage Gain
-
100
250
-
VN
Gain Bandwidth Product (CL = 1.0 nF)
-
0.3
-
-
MHz
Vout Low, Sinking 50 j.lA
5
-
0.2
0.4
V
Vout High, Sourcing 10 j.lA, VCC2 - Vout
5
-
0.2
0.5
V
Phase Comparator Tri-8tate Current
4
-15
0
15
nA
Charge Pump High Current of Phase Comparator
4
30
50
85
j.lA
Charge Pump Low Current of Phase Comparator
4
10
15
30
~A
VCC3 Supply Voltage Range
14
VCCI
-
14.4
VCC3 Supply Current
All Buffers "OIl"
One Buffer "On" when Open
One Buffer "On" at 40 mA
14
Data Format and Bus Receiver
The circuit is controlled by a 3-wire bus via Data (DA),
Clock (Cl), and Enable (EN) inputs. The Data and Clock
inputs may be shared with other inputs on the lie-Bus while
the Enable is a separate signal. The circuit is compatible with
18 and 19 bit data transmission and also has a mode for
34 bit transmission for test and additional features.
The 3-wire bus receiver receives data for the intemal shift
register after the positive going edge of the EN-signal. The
data is transmitted to the band buffers on the negative going
edge of the clock pulse 4 (signal DTB1).
18 and 19 Bit Data Transmission
The programmable divider may receive 14 bit (18 bit
transmission) or 15 bit (19 bit transmission). The data is
transmitted to the programmable divider (latches A) on the
negative going edge of clock pulse 19 or on the negative
edge of the EN-signal if EN goes down after the 18th clock
pulse (signal DTF). If the programmable divider receives
14 bit, its MSB (bit N14) is internally reset. The reset pulse is
generated only if EN goes negative after the 18th clock pulse
(signal Rl).
MOTOROLA ANALOG IC DEVICE DATA
V
mA
-
-
0.2
8.0
48
0.5
13
53
34 Bit Data Transmission
(For Test and Additional Features)
In the test mode, the programmable divider receives 15 bit
and the data is transferred to latches A on the negative edge
of clock pulse 19 (signal DTF). The information for test is
received on clock pulses 20 to 26 and transmitted to the
latches .on the negative edge of pulse 34 (signal DTB2).
These latches have a power--on reset. The power-on reset
sets the programmable divider to a counting ratio of 256 or
higher and resets the corresponding latches to the test bits
TO to T6 (signal POR). The bus receiver is not disturbed if the
data format is wrong. Useless bits are ignored. If for example
the Enable signal goes low after the clock pulse 9, bits one to
four are accepted as valid buffer information and the other
bits are ignored. If more than 34 bits are received, bit 35 and
the following are ignored.
Lock Detector
The lock-detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
9-369
MC44817/17B
Figure 1. HF Sensitivity Test Circuit
Bus Controller
r---_-40mA
MC44817117B
Gnd
9
BO
B3
13
10
Counter
4.7k
4.7k
390g.-_ _--i tn
390g
50g
Device is in test mode. B2. B3 are "On" and BO. Bl are "Off'.
Sensitivity is level of HF generator on 50 l'lload (without Pin B loading).
HF CHARACTERISTICS (See Figure 1)
Characteristic
DC Bias
Input Voltage Range
10-80 MHz. Prescaler "Off', T6 = 1.0
80--150 MHz
150-600 MHz
600--950 MHz
950--1300 MHz
Pin
Min
Typ
Max
8
-
1.6
-
Unit
V
mVrms
20
10
5.0
10
50
8
8
8
8
8
-
315
3.15
315
315
315
Figure 2. Typical HF Input Impedance
II
-j
+j
_ 0 __
9-370
MOTOROLA ANALOG IC DEVICE DATA
MOTOROLA ANALOG IC DEVICE DATA
9-371
MC44817117B
Bus Timing Diagram
. Standard Bus Protocol 18 or 19 Bit
Data
18 19
4 5
Clock
I
Enable
1
Bl
Frequency
~
4
Sa II:!
Buffers
5
BO N14 N13 N12 Nll NlO Ng Ne
Buffers
'?
Ne N5 N4 N3 N2
1. Bus Protocol for 18 Bit
B3 B2 B1 BO N13 N12 N11 N10 Ng N8 N7 N6 NS N4 N3
N2 N1 NO
Max Counting Ratio 16363
N14 is Reset Internally
2. Bus Protocol for 19 Bit
B3 B2 B1 BO N14 N13 N12 N11 N10 Ng N8 N7 N6 NS N4
N3 N2 N1 NO
Max Counting Ratio 32767
- BO to B3: Control of Band Buffers
- NO to N14: Control of Programmable Dividers
=
N14 MSB; NO LSB
Minimum Counting Ratio Always 17
B3 = First Shifted Bit
NO = Last Shifted Bit
3. Bus Protocol for Test and Further Features (34 Bit)
B3 B2 B1 BO N14 .. ·NO T6 TS T4 T3 T2 T1 TO X7
X6 .. ·X1 Xo
- TO to T3: Control the Phase Comparator
- T4: Switches Test Signals to the Buffer Outputs
- TS: Division Ratio ofthe Reference Divider
B Version TS "X"
- T 6: Bypasses the Prescaler (Note 1)
- Xo to X7: Are Random
=
B3
Xo
=First Shifted Bit
=Last Shifted Bit
Definition of the Bits for Test and Features
Bit TO: Defines the Charge Pump Current of the
Phase Comparator
TO = 0
= 1
9-372
Nl NO T6 T5
Frequency
Definition of Permissible Bus Protocols
=
Pump Current 50 I1A Typical
Pump Current 15 I1A Typical
II
Bus Protocol for Test and Features
19 20
33 34
26 27
T4
T3 T2
Tl
To X7
XsX5~X3
Test & Features
X2 Xl
Xo
Random
Bits T 1 and T2: Define the Digital Function of the Phase
Comparator
Output Function of Phase Comparator
T2
T1
State
0
0
1
NOl:fllal Operation
0
1
2
High Impedance (Tri-State)
1
0
3
Upper Source "On", Lower Source "Off'
1
1
4
Lower Source ''On", Upper Source ''Off'
NOTE: 1. The phase comparator pulls high If the Input frequency IS too
high and it pulls low when the input frequency is too low.
(Inversion by Operational Amplifier) The phase comparator
generates a fixed duration offset pulse for each compariscn
pulse (similar to the MC44802A). This guarantees operation in
the linear region. The offset pulse is a positive current pulse
(upper source).
Bit T3: Defines the Offset Pulse of the Phase
Comparator
T3=0
=1
Offset Pulse Short (200 ns)
Normal Mode
Offset Pulse Long (350 ns)
Bit T 4: Switches the Internal Frequencies Fref and
FBY2 to the Buffer Outputs (B2. B3)
Normal Operation
Fre! Sw~ched to Buffer Output B2
FBY2 Switched to Buffer Output B3
NOTE: Bits B2 and B3 have to be one in this case.
Fref is the reference frequency.
FBY2 is the output frequency of the programmable divider,
divided by two.
Bit T5: Defines the Division Ratio of the Reference
Divider
Division Ratio 512
Division Ratio 1024
NOTE: The division ratio of the reference divider cen only be
programmed in the 34 bit bus protocol.
In the standard bus protocol the division,. ratio is 512.
(The power-up reset POR sets the division ratio to 512).
On "S-version", T5 =·X". Division ratio 1024 fixed.
MOTOROLA ANALOG ICDEVICE DATA
MC44817/17B
At power~n the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N =256 or
higher.
Bit T6: Switches the Prescaler
T6=0
=1
Normal Operation, 1.3 GHz
Low Frequency Operation
Preamp. 2 Switched Off, 165 MHz maximum
The prescaler is bypassed and the power supply of
the prescaler is switched off. Input: 10 MHz
minimum, 20 mVrms minimum
Figure 4. Equivalent Circuit of the Integrated
Band Buffers
VCC3 12V
- _ - . . - _ - - - - -.......- 0 (MinVCC1,Max14.4V)
25V
0.15 V Typical
Protection
0.3 V Max
Out
NOTE: IB + ISUB = B.O rnA Typical, 13 rnA Max
IB = Base Current
ISUB = Substrate Current of PNP
30 rnA (40 rnA
at 0 to 80°C)
BO .. ·B3
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TOI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N =16384 x N14 + 8132 x N13 + ... + 4 x N2 + 2 x Nl + NO
Maximum Ratio 32767
(16363 in case of 18 bit bus protocol)
Minimum Ratio 17
NO ... N14 are the different bits for frequency information.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
needs 28.5 V supply (VCC2) as minimum voltage for a
guaranteed maximum tuning voltage of 28 V.
Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
The Oscillator
The oscillator uses a 3.2 to 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 3 has low amplitude and low harmonic
distortion.
Figure 5. Equivalent Circuit of the Lock Output
,-----.._---0 VCCI 5.0 V
Lock
II
Figure 6. Typical Tuner Application
IF
External Switching
Bill
5.0V 7
f-------7O+-CL
f------i;O+-DA
f----~O+-EN
T 12pF
o
3.214.0 MHz
l
VTUN
AGC
NOTES: 1. On some layouts the 100 !l resistor will not be required.
2. C2 = 330 pF minimum is required for stability.
MOTOROLA ANALOG IC DEVICE DATA
22nF
9-373
®
MOTOROLA
MC44818
PLL Tuning Circuit
with 12C Bus
The MC44818 is a tuning circuit for TV and VCR tuner applications. It
contains, on one chip, all the functions required for PLL control of a VCO.
This integrated circuit also contains a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz. The MC44818 is a pin compatible drop in
replacement for the MC44817, where the only difference is the MC44818
has a fixed divide-by-8 prescaler (cannot be bypassed) and the MC44817
uses the three wire bus.
' ,.'
The MC44818 has a programmable 51211024 reference divider and is
manufactured on a single silicon chip using Motorola's high density bipolar
process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits).
TV AND VCR
PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND 12C BUS
SEMICONDUCTOR
TECHNICAL DATA
• Complete Single Chip System for MPU Control (12C Bus). Data and
Clock Inputs are 3-Wire 'Bus Compatible
• Divide-by-8 Prescaler Accepts Freqoencies up to 1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
• Reference Divider: Programmable for Division Ratios 512 and 1024.
• 3-State Phase/Frequency CQmparator
• Operational Amplifier for Direct Tuning Voltage Output (30 V)
• Four Integrated PNP Band Buffers for 40 mA (VCC1 to 14.4 V)
• Output Options for the Reference, Frequency and the
Programmable Divider
DSUFFIX
PLASTIC PACKAGE
CASE 7516
(S0-16)
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
• Fully ESD Protected
MOSAIC is a trademark of Motorola, Inc.
PIN CONNECTIONS
SDA
o
SCl
AS
lock
VCC3 12V
83
ORDERING INFORMATION
Device
MC44818D
Operating
Temperature Range
Package
TA =-20° to +80°C
S0-16
80
Gnd
(Top View)
9-374
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Representative Block Diagram
Bands Out 30 rnA
(40 rnA at 00 to 80°C)
VCCI
5.0V
VTUN
VCC3
13
7
12 11
10
14
12V
6
~+-
___4-o Amp In
Lock
AS~_ _-rL...-..-L...J.~
I---'~--I
Data
Clock?",,"---4..-';:::::=--~
XTAL
II
DTS, EN
This device contains 3,204 active transistors.
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Pin
Value
7
6.0
V
Band Buffer "Off' Voltage
10-13
14.4
V
Band Buffer "On" Current
10-13
50
mA
Band Buffer - Short Circuit Duration (0 to VCC3) (Note 2)
10-13
Continuous
-
6
40
V
Operational AmplHier Short Circuit Duration (0 to VCC2)
5
Continuous
-
Power Supply Voltage (VCC3)
14
14.4
V
Storage Temperature
-
-65 to +150
DC
Rating
Power Supply Voltage (VCC1)
Operational Amplifier Power Supply Voltage (VCC2)
Un"
-
-20 to +80
DC
10-13
10
sec
Operational Amplifier Output Voltage
5
VCC2
V
RF Input Level (10 MHz to 1.3 GHz)
-
1.5
Vrms
Operating Temperature Range
Band Buffer Operation (Note 1) at 50 mA each Buffer All
Buffers "On" Simultaneously
NOTES: 1. AtVCC3= VCCI to 14.4 VandTA =-2O"lo+80°C.
2. AI VCC3 = VCCI 1014.4 V and TA =-20"10 +80"C one buffer "On" only.
MOTOROLA ANALOG IC DEVICE DATA
9-375
MC44818
ELECTRICAL CHARACTERISTICS (VCC1 = 5.0 V, VCC2 = 33 V,VCC3 = 12 V,
Characteristic
Min
Typ
Max
VCC1 Supply Voltage Range
7
4.5
5.0
5.5
V
VCC1 Supply Current (VCCf:" S.O V)
7
-
37
50
rnA
VCC2 Supply Voltage Range
6
25
-
37
V
VCC2 Supply Current (Output Open)
6
-
1.5
2.3
rnA
Unit
Band Buffer Leakage Current when "Off" at 12 V
10-13
-
0.01
1.0
IlA
Band Buffer Saturation Voltage when "On" at 30 rnA
10-13
-
0.15
0.3
V
Band Buffer Saturation Voltage when "On" at 40 rnA
only for 0° to 80°C
10-13
-
0.2
0.5
V
1,2
-10
-
0
Clock Current at,5.0 V
2
0
-
1.0
IlA
IlA
Data Current at 5.0 V Acknowledge "Off"
1
0
IlA
1
-
-
1.0
Data Saturation Voltage at 15 rnA Acknowledge "On"
1.0
V
Data/Clock Input Voltage Low
1,2
-
-
1.5
V
Data/Clock Input Voltage High
1,2
3.0
-
Clock Frequency Range
2
-
-
100
kHz
Oscillator Frequency Range
3
3.15
3.2
4.05
MHz
Operational Amplifier Internal Reference Voltage
-
2.0
2.75
3.2
V
Operational Amplifier Input Current
4
-15
0
15
nA
DC Open Loop Voltage Gain
-
100
250
-
VN
Gain Bandwidth Product (CL = 1.0 nF)
-
0.3
-
-
MHz
Vout Low, Sinking 50 IlA
5
0.4
V
5,
-
0.2
VOU! High, Sourcing 10 1lA, VCC2 - Vout
0.2
0.5
V
Phase Detector Current in the High Impedance State
4
-15
0
15
nA
IlA
IlA
Data/Clock Current at 0 V
II
iA = 25°C, unless otherwise noted.)
Pin
-
Charge Pump High Current of Phase Comparator
4
30
50
85
Charge Pump Lo~ Current of Phase Comparator
4
10
15
30
VCC3 Supply Voltage Range
14
VCC1
-
14.4
VCC3 Supply Current
All Buffers "Off"
One Buffer "On" when Open
One Buffer "On" at 40 rnA
14
1_STA
2_STA
3_STA
CA
CA
CA
CO
FM
CO
BA
FL
BA
-
0.2
8.0
48
-
STO
STO
FM
FL
V
rnA
-
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the 12C bus. The incoming information, consisting of a
chip address byte followed by two or four data bytes, is
treated in the 12C bus receiver. The definition of the
permissible bus protocol is shown below:
V
0.5
13
53
4_STA CA
FM
FL
CO BA
STO
STA Start Condition
STO Stop Condition
CA Chip Address Byte
CO Data Byte for Control Information
BA Band Information
FM Data Byte for Frequency Information
FL Data Byte for Frequency Information
=
=
=
=
=
=
=
STO
Figure 1. Complete Data Transfer Process
r,
r,
SDA:V--~~~-_~
tT-
SCL!Vl~;\
1;\ Q.
r;_~I~;'rV?'
r;'
8 V
9 Vll
I I
,voLJ·L.J
L
S...1
STA
I~~
I
ADDRESS
RIW
ACK
I
IL---.,J
DATA
. ACK
I
I
DATA
L:.-.J
L
P...1
STO
CA
9-376
MOTOROLA ANALOG ICDEVICE DATA
MC44818
The first and the third data bytes contain a function bit
which allows the Ie to distinguish between frequency
information and control plus band information.
Frequency information is preceeded by a Logic "0". If the
function bit is Logic "1" the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
The two permissible bus protocols with five bytes are
shown in Figure 2.
Figure 2 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received: if three data bytes are received the third data byte
is ignored.
If five or more data bytes are received the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
Figure 2. Definition of Bytes
CA_Chip Address
BA_Band Information
FM_Frequency Information
FL_Frequency Information
CA_Chip Address
FM_Frequency Information
FL_Frequency Information
x
BA_Band Information
x
Chip Address
The chip address is programmable by Pin 16 (AS Address Select).
AS-Pin16
Address (HEX.)
Gnd to 0.1 VCC1
CO
.
x
BO
T8=0
=1
Normal Operation
Operational Amplifier Active
Output State of Operational Amplifier Switched "Off",
Output Pulls High Through 20 k Internal Pull-Up
Resistor
Bits Tg, T12: Control the Phase Comparator
C2
0.4 VCC1 to 0.7 VCC1
C4
Tg
T12
0.8 VCC1 to 1.1 VCC1
C6
1
1
0
0
0
1
0
1
Bo, B1, B2, B3 :: 01
I
Function
Normal Operation
High Impedance
Upper Source "On" Only
Lower Source "On" Only
Bits T10, T 11: Control the Reference Ratio
Buffer "Off"
. Buffer"On"
Figure 3. Equivalent Circuit of the Integrated
Band Buffers
- - . . -.......- . - - - - - -.....-0 VCC312 V
25V
Pro1ection
T10
T11
0
0
1
1
0
1
0
1
Division Ratio
512
1024
1024
512
Bit T13: SWitches the Internal Signals Fref and FBY2 to
the Band Buffer Outputs (Test)
T 13 = 0
: 1
Out
NOTE: IB + ISUB = S.O rnA Typical, 13 rnA Max
IB = Base Current
ISUB = Substrate Current of PNP
ACK
Bit TS: Controls the Output of the Operational Amplifier
Open or 0.2 VCC1 to 0.3 VCC1
Bits BO, B1, B2, B3: Control the Band Buffers
l
x
Bo···B3
MOTOROLA ANALOG IC DEVICE DATA
30 mA (40 mA
at 0 to SO°G)
Normal Operation
Test Mode
Fref Output at B2 (Pin 12)
FBY2 Output at B3 (Pin 13)
Bits B2 and B3 have to be "On", B2 = B3 = 1 in the test mode.
Fref is the reference frequency.
FSY2 is the output frequency of the programmable divider, divided by two.
9-377
MC44818
Bit T 14: Controls the Charge Pump Current of the
Phase Comparator
T 14 = 0
Lock Detector
The lock detector output is low in lock. The output gpes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
Pump Current 15 j.IA Typical
Pump Current 50 j.IA Typical
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TOI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N =16384 x N14+8192x N13+ ... +4x N2+2x N1 + NO
Maximum Ratio 32767
Minimum Ratio 17
NO ... N14 are the different bits for frequency information.
At power "on" the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N =256 or
higher.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
.
impedance s t a t e . '
Figure 4. Equivalent Circuit of the Lock Output
VCC1 5.OV
200 !iA Typical
2.0k
_I\AA_....," Lock
100 k
25 V ProteCiion
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
needs 28.5 V supply (VCC2) as minimum voltage for a
guaranteed maximum tuning voltage of 28 V.
Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
The Oscillator
The oscillator uses a 3.2 to 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 3 has low amplitude and low harmonic
distortion.
Figure 5. Typical Tuner Application
IF
II
External Switching
Bill
5.0V 7
I-----~o--SCL
I------,-=c.o--SDA
I------.!.!!()..o--As
T
12pF
o
3.214.0 MHz
l
VTUN
AGC
NOTES: 1. On some layouts the loon resistor will not be required.
2. C2 = 330 pF minimum is required for stability.
9-378
22 nF
MOTOROLA ANALOG IC DEVICE DATA
MC44818
Figure 6. HF Sensitivity Test Circuit
Bus Controller
MC44818
Gnd
9
BO
10
4.7k
4.7k
3900.-_ _- ; In
Frequency
Counter
3900
500
Device is in test mode. B2. B3 are "On" and BO. Bl are "Off".
Sensitivny is level of HF generator on 50 0 load (without Pin 6 loading).
HF CHARACTERISTICS (See Figure 1)
Pin
Min
Typ
Max
Unit
DC Bias
8
-
1.6
-
V
Input Voltage Range
80-150 MHz
150-600 MHz
600-950 MHz
950-1300 MHz
8
8
8
8
10
5.0
10
50
-
315
315
315
315
Characteristic
mVrms
-
-
_0_
Figure 7. Typical HF Input Impedance
-j
MOTOROLA ANALOG IC DEVICE DATA
+j
9-379
9-380
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44824/25
TV AND VCR
PLL Tuning Circuits
with 12C Bus
The MC44824125 are tuning circuits for TV and VCR tuner applications.
They contain on one chip all the functions required for PLL control of a VCO.
The integrated circuits also contain a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz.
The MC44824/25 are manufactured on a single silicon chip using
Motorola's high density bipolar process, MOSAICTM (Motorola Oxide Self
Aligned Implanted Circuits).
PLL TUNING CIRCUITS
WITH 1.3 GHz PRESCALER
ANDI2C BUS
• Complete Single Chip System for MPU Control (12C Bus). Data and
Clock Inputs are 3-Wire Bus Compatible
• Divide-by-8 Prescaler Accepts Frequencies up to 1.3 GHz
DSUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512 and 1024
• 3-State Phase/Frequency Comparator
• 4 Programmable Chip Addresses
• 3 Output Buffers (MC44824) respectively 5 Output Buffers (MC44825)
for 10 mAl15 V
DSUFFIX
PLASTIC PACKAGE
CASE 751B
(S0-16)
• Operational Amplifier for use with External NPN Transistor
• S0-14 Package for MC44824 and S0-16 for MC44825
• High Sensitivity Preamplifier
II
• Fully ESD Protected
PIN CONNECTIONS
I
I
MOSAIC is a trademark of Motorola, Inc.
UD
GND
XTAL2
HF2
SDA
HF1
I
I
I
Vee
61
62
(Top View)
ORDERING INFORMATION
Device
Operating
Temperature Range
MC44824D
MC44825D
UD
GND
XTAL2
HF2
HF1
Vee
Package
S0-14
TA=-20° to + 80°C
XTAL1
S0-16
67
64
60
61
eA
62
(Top View)
MOTOROLA ANALOG IC DEVICE DATA
9-381
MC44824/25
Representative Block Diagram
Vee
5.0V
UO
10
(12)
6
(6)
(7)
8
(9)
9
(10)
14
(16)
(11)
/ . t -_ _ _....1>'-(1-o PO
BO
2.iv
XTAU
XTAL2
HF Input1
HF Input2 v---, ___
II
MC44825 Pin Numbers ( )
This device contains 3,204 active transistors.
PIN FUNCTION DESCRIPTION
Pin
MC44824
MC44825
1
1
PO
Input of tuning
2
2
XTAL1
First crystal input is the active pin at the oscillators
Second crystal input is the internal ground
Symbol
Description
vo~age
amplifier
3
3
XTAL2
4
4
SOA
Data input
5
5
SCl
Clock input of the 12C bus
6,8,9
-
B7,B2,B1
Band buffer (open collector) outputs for up to 10 mA
-
6,7,9,10,11
B7,B4,B2,B1,BO
Band buffer (open collector) outputs for up to 10 mA
7
8
CA
Chip address selection pin
10
12
VCC
Supply voltage, typical 5.0 V
11,12
13,14
HF1/HF2
Symmetric HF inputs from local oscillator
13
15
GNO
Ground
14
16
UO
Output of the tuning voltage amplifier. Needs an external NPN with pull-up
resistor to drive the varicaps
9-382
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
MAXIMUM RATINGS (TA =25°C, unless otherwise noted.)
Pin
MC44824
MC44825
Value
Unit
10
12
6.0
V
Band Buffer "Off' Voltage
6,8,9
6,7,9,10,11
15
V
Band Buffer "On" Current
6,8,9
6,7,9,10,11
15
mA
Rating
Power Supply Voltage
(VCC)
Storage Temperature
-
-
-65 to +150
°C
Operating Temperature
Range
-
-
-20 to +80
°C
RF Input Level (10 MHz
to 1.3 GHz)
11,12
13,14
1.5
Vrms
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C, unless otherwise noted.)
Pin
Characteristic
MC44824
MC44825
Min
Typ
Max
VCC Supply Voltage Range
10
12
4.5
5.0
5.5
V
VCC Supply Current (VCC = 5.0 V)
10
12
-
40
55
mA
Band Buffer Leakage Current when "Off' at 12 V
6,8,9
6,7,9, 10, 11
-
0.01
1.0
I1A
Band Buffer Saturation Voltage when "On" at 10 mA
6,8,9
6,7,9,10,11
-
1.6
1.8
V
Data Saturation Voltage at 15 mA Acknowledge "On"
4
4
-
-
1.0
V
Data/Clock/Enable Current at 0 V
4,5
4,5
-10
-
0
Data/Clock/Enable Current at 5.0 V
4,5
4,5
0
-
1.0
I1A
I1A
Data/Clock/Enable Input Voltage Low
4,5
4,5
-
-
1.5
V
Data/Clock/Enable Input Voltage High
4,5
4,5
3.0
-
-
V
5
5
-
-
100
kHz
Clock Frequency Range
Unit
2,3
2,3
3.15
3.2
4.05
MHz
Operational Amplifier Input Current
1
1
-15
0
15
nA
Phase Detector Current in High Impedance State
1
1
-15
0
15
nA
Oscillator Frequency Range
Charge Pump Current of Phase Comparator, T 14 = 0
1
1
30
40
60
I1A
Charge Pump Current of Phase Comparator, T 14 = 1
1
1
100
125
200
I1A
MC44824
MC44825
Min
Typ
Max
Unit
11,12
13,14
-
1.6
-
HF CHARACTERISTICS (See Figure 1)
Pin
Characteristic
DC Bias
Input Voltage Range
80-150 MHz
150-600 MHz
600-950 MHz
950-1300 MHz
MOTOROLA ANALOG IC DEVICE DATA
V
mVrms
11,12
11,12
11,12
11,12
13,14
13,14
13,14
13,14
10
5.0
10
50
-
-
-
315
315
315
315
9-383
MC44824125
Figure 1. HF Sensitivity Test Circuit
Bus Controller
SDA,SCL
S.OV VCC
MC44824125
HF
HF
Gnd
"'----1 In
470
470
Frequency
Counter
VCC
Device is in test mode. B2 and 67 are ·On".
Sensitivity is level of HF generator on 50 n load.
Figure 2. Typical HF Input Impedance
-j
+j
_0---.
II
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the 12C bus. The incoming information, consisting of a
chip address byte followed by two or four data bytes, is
treated in the 12C bus receiver. The definition of the
permissible bus protocol is shown below:
1_STA CA
2_STA CA
3_STA CA
CO
FM
CO
BA
FL
BA
STO
STO
FM FL
4_STA CA FM FL CO BA STO
STA =Start Condition
STO =Stop Condition
CA =Chip Address Byte
CO =Data Byte for Control Information
BA =Band Information
FM Data Byte for Frequency Information (MSB's)
FL = Data Byte for Frequency Information (LSB's)
=
STO
MOTOROLA ANALOG IC DEVICE DATA
MC44824/25
Figure 3. Complete Data Transfer Process
r,
r,
SDA-W--~~-rlJC-_~
SCL!!\.i1~;\
I I
' V
,--S...J
STA
I
f;,\U Q• '---1r1--~1~:;'
?
rV 8V
0
I~L--.J
ADDRESS
RIW
ACK
CA
I
IL--J
DATA
I
I
ACK
DATA
r-t-
79 Vi :
~
ACK
,--P...J
STO
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.
Frequency information is preceded by a Logic "0". If the
function bit is Logic "1" the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
The two permissible bus protocols with five bytes are
shown in Figure 4.
Figure 4 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received: if three data bytes are received, the third data byte
is ignored.
If five or more data bytes are received, the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
Figure 4. Definition of Bytes
CA_Chip Address
BA_Band Information
FM_Frequency Information
FL_Frequency Information
II
FM_Frequency Information
FL_Frequency Information
BA_Band Information
B7
x
x
x
BO'
ACK
• 60 and 64 are only available on MC44825. On MC44824 this data is random.
Chip Address
The chip address is programmable by Pin 7 (8), CA.
CA-Pin7(8)
Address (HEX.)
GndtoO.1 VCC1
CO
Open or 0.2 VCC1 to 0.3 VCC1
C2
0.4 VCC1 to 0.7 VCC1
C4
0.8 VCC1 to 1.1 VCC1
C6
Bits BO, B1. B2. B4. B7: Control the Band Buffers
l
.
BO, B1, B2, B4, B7 == 0
1
Buffer "Off'
Buffer "On"
MOTOROLA ANALOG IC DEVICE DATA
Bit T8: Controls the Output of the Operational Amplifier
T8
=0
Normal Operation
Operational Amplifier Active
=1
Output State of Operational Amplifier Switched "Off",
Output Pulls High Through an External Pull-Up
Resistor
Bits Tg. T12: Control the Phase Comparator
T9
T'2
1
1
0
0
0
1
0
1
Function
Normal Operation
High Impedance
Upper Source "On" Only
Lower Source "On" Only
9-385
MC44824125 .
Bits T 10. T 11: Control the Reference Ratio
T10
T11
0
0
1
1
0
1
0
1
512
1024
1024
512
Bit T 13: Switches the Internal Signals Fref and FBY2 to
the Band Buffer Outputs (Test)
Normal Operation
Test Mode
, Fre! Output at B7
FBY2 Output at B2
=
Bits B:2 and B7 have to be "Off. B2 = B7 = 0 in the test mode.
Fref is the reference frequency.
FBY2 is the out~ut frequency of t~e programmable divider. divided by two.
Bit T 14: Controls the Charge Pump Current of the
Phase Comparator
T14 = 0
=1
BA_Band Information
MC4482414 Pin version
x
X
X
X
B2
B1
X
ACK
X
B2
B1
Bo
ACK
MC4482516 Pin version
B7
X
X
B4
The band buffers are open collector buffers and are active
"low" at Bn 1. They are designed for 10 mA with a typical
"On" resistance of 160 n. These buffers are designed to
withstand relative high output voltage in the "Off' state ..
B2 and B7 buffers may also be used to output internal IC
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.
The bit B2 andlor B7 have to be zero if the buffers are used
for these additional functions.
=
II
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division
ratio out of the latches B. Latches B are loaded from latches
A by means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
9-386.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
Pump Current 40 itA Typical
Pump Current 1251!A Typical
The Band Buffers
B7
The division ratio definition is given by:
N 16;381J.xN14 +S192 x N13 + ... + 4x N2 + 2 x N1 + NO
Maximum Ratio 32761.
Minimum Ratio 17
Where NO ... N14 are the different bits for frequency
information.
The cOl!nter may be used for any ratio between 17 and
32767 and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.
The data transfer between latches A and B (Signal TDI) is
also initiated by any start condition on the 12C bus.
At power-on, the whole bus 'receiver is reset and the
programmable divider is set to a counting ration of N 256 or
higher.
The first 12C message must be sent only when the
POWER ON RESET is completed.
=
Division Ratio
The Tuning Voltage Amplifier
The amplifier is designed for very low noise, low input bias
current and high power supply rejection. The positive input is
biased internally. The tuning voltage amplifier needs an
external NPN with a pull-up resistor to generate the tuning
voltage.
The amplifier can be switched "Off' through bit TS. When
bit TS is "One", the amplifier is "Off'. The tuning voltage is
then pulled high by the external pull-up resistor.
Figure 5 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 5 may be used for 7.S125 kHz reference frequency
in a multiband TV tuner.
The .Oscillator
The oscillator uses a 4.0 MHz crystal tied to ground "or
between Pins 2 and 3" through a series capacitor. The crystal
oscillates in its series resonance mode.
The voltage at Pin 13 XTAL1, has low amplitude and low
harmonic distortion.
Pin XTAL2 is the internal ground of the oscillator; it is
connected internally to ground Pin 13 (15).
MOTOROLA ANALOG Ie DEVICE DATA
MC44824/25
Figure 5. Typical Tuner Applications
\----"O-SCL
I----:(').-SDA
\ - - - - - ' - 0 _ CA
22 nF
Extemal Switching
Bill
7
\----"O-SCL
I----:(').-SDA
\----"O-CA
22nF
NOTE: C2 = 330 pF minimum is required for stability.
MOTOROLA ANALOG IC DEVICE DATA
9-387
II
®
MOTOROLA
MC44826
PLL Tuning Circuit
with 12C Bus
The MC44826 is a tuning circuit for TV and VCR tuner applications. It
contains, on one chip, all the functions required for PLL control of a VCO. This
integrated circuit also contains a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz. The circuit has a band decoder that
provides the band switching signal for the mixer/oscillator circuit. The decoder
is controlled by the buffer bits or independently by extra bits T6 and T7.
The MC44826 has a programmable 51211024 reference divider and is
manufactured on a single silicon chip using Motorola's high density bipolar
process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits).
TV AND VCR
12C PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND Mlx/OSC DECODER
SEMICONDUCTOR
TECHNICAL DATA
• Complete Single Chip System for MPU Control (12C Bus)
• Divide-by--8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512 and 1024
• 3-State Phase/Frequency Comparator
• Operational Amplifier'for Direct Tuning Voltage Output (30 V)
• Four Programmable Chip Addresses
14
• Integrated Band Decoder for the Mixer/Oscillator Circuit
• Band Buffers with Low "On" Voltage (0.4 V Maximum at 15 mAl
• Fully ESD Protected to MIL-STD--883C, Method 3015.7
(2000 V, 1.5 1<0, 150 pF)
II
o SUFFIX
PLASTIC PACKAGE
CA8E751A
(80-14)
MOSAIC is a trademark of Motorola, Inc.
PIN CONNECTIONS
ORDERING INFORMATION
Device
MC44826D
Operating
Temperature Range
Package
TA = -20° to +80°C
S0-14
0
14
PHO
Gnd
13
Xtal
HF1
12
DEC
HF2
11
SDA
VTUN
SCL
VCC1
81
8
83
85
(Top View)
9-388
MOTOROLA ANALOG IC DEVICE D~TA
MC44826
Representative Block Diagram
VTUN
VCC2
RL
CL
Bands Out
r'
VCCI
S.OV
5
7
14
2.7V
PHO
Gnd
-=DTB2
POR
CA
SDA
SCL
9
CL
11
10
Data
RL
DTF
T12pF
CJ 3.214.0
l
MHz
DTS, EN
This device contains 3,204 active transistors.
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Pin
Value
5
6.0
V
Band Buffer "Off" Voltage
6,7,8
15
V
Band Buffer "On" Current
6,7,8
20
rnA
1
40
V
3,4
1.5
Vrms
Storage Temperature
-
-65 to +150
°e
Operating Temperature Range
-
-20 to +80
°e
Bus Input Voltage (Positive)
10,11
7
V
Bus Input Voltage (Negative)
10,11
-0.5
V
Rating
Power Supply Voltage (Veel)
Operational Amplifier Power Supply (VCC2)
RF Input Level 10 MHz to 1.3 GHz
MOTOROLA ANALOG IC DEVICE DATA
Unit
9-389
II
MC44826
ELECTRICAL CHARACTERISTICS (VCCl
=5.0 V, VCC2 =33 V, TA =25°C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
VCCl Supply Voltage Range
5
4.5
5.0
5.5
Unit
V
VCCl Supply Current (VCCl .; 5.0 V)
5
25
35
50
rnA
ItA
Band Buffer Leakage Current when ''Off' at 12 V
1;>,7,8
-
0.Q1
1.0
Band Buffer Saturation Voltage when "On" at 15 rnA
6,7,8
-
0.2
0.4
V
Data/Clock Current at 0 V (Acknowledge "Off')
10,11
-10
-
0
Data/Clock Current at 5.0 V (Acknowledge "011")
10,11
0
-
1.0
ItA
ItA
Data/Clock Input Voltage Low
10,11
-
-
1.5
V
Data/Clock Input Voltage High
10,11
3.0
-
-
V
Data Saturation Voltage at 3.0 rnA (Acknowledge ''On")
11
-
0.25
0.4
V
Decoder "High" Level Sourcing 100 ItA
12
3.4
-
VCCl
V
Decoder "Medium" Level Sourcing 15 !LA
12
1.7
-
2.3
V
Decoder "Low" Level Sinking 20 ItA
12
0
-
0.8
V
Clock Frequency Range
10
-
-
100
kHz
Oscillator Frequency Range
13
3.15
3.2
4.05
MHz
Operational Amplifier Internal Reference Voltage
-
2.0
2.75
3.2
V
Operational Amplifier Input Current
14
-15
0
15
nA
14,1
100
250
1000
VN
14,1
0.3
-
-
MHz
DC Open Loop Gain (RL
=22 kn)
=0.5 nF)
Gain Bandwidth Product (CL
Vout Low (RL
=22 kQ)
Phase Detector Current in High Impedance State
Charge Pump Current of Phase Comparator (T 14
Charge Pump Current of Phase Comparator (T 14
=0)
=1)
VCC2 Supply Voltage Range
1
-
0.25
0.4
V
14
-15
0
15
nA
14
30
40
50
!LA
14
90
125
150
!LA
1
25
33
36
V
PIN FUNCTION DESCRIPTION
Pin
Function
1
VTUNNCC2
Description
Output of the tuning voltage amplifier. Needs an external pull-up resistor to drive the varicaps
2
Gnd
3,4
HF1/HF2
5
VCCl
6,7,8
Bl, B3, B5
9
CA
Chip address selection pin
10
SCL
Clock input of the 12C bus
11
SDA
Data input
12
DEC
Band decoder output for the mixer/oscillator circuit
13
Xtal
Crystal input
14
PHO
Input of tuning voltage amplifier
9-390
Ground
Symmetric HF inputs from local oscillator
Supply voltage. Typical 5.0 V
Band buffer outputs
MOTOROLA ANALOG IC DEVICE DATA
MC44826
Figure 1. Typical Prescaler Input Sensitivity
o
200
400
600
600
1000
1200
1400
RFln (MHz)
NOTE: Vee = 4.5 to 5.5 V, TA = - 20° to +800 e
HF CHARACTERISTICS (See Figure 1)
Characteristic
DC Bias
Input Voltage Range
50-950 MHz
950-1300 MHz
Pin
Min
'iYP
Max
3,4
-
1.6
-
UnH
V
mVrms
3,4
3,4
-
10
50
315
315
Figure 2. RF Sensitivity Test Circuit
II
12C Bus Controller
+5.0 V 0----1 5
MC44826
VCCI
'--_....,3r--_-r4_ _ _ _ _
7 B3
r-__....
4,0 k
B5
HFln
+---~'V'v\r---""'o
RF Generator
(SOU)
+12 V
4.0kQ
sOU
Frequency Counter
Device is in test mode, B5 and B3 are "On", Bl is "Off".
SensHivity is the level of the HF generator on 50 a load.
MOTOROLA ANALOG iC DEVICE DATA
9-391
MC44826
Figure 3. 1\tpical HF Input Impedance
+j _
_-j0 _
Figure 4. Complete Data Transfer Process
"
"
SDA1V-'----IC~~-_~
SCl
tt-
!!\J1~;\
t;\ t;\
r 1--~1~:;"
I I
,voV'\-f
7V?8 V r;'9 Vi I·
L..S-.J
STA
I
Il....-....JL........J
ADDRESS
CA
AIW
I
ACK
IL.......J
DATA
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the 12C bus. The incoming information, consisting of a
chip address byte followed by two or four data bytes, is
treated in the 12C bus receiver. The definition of the
permissible bus protocol is shown below:
1_STA
2_STA
3_STA
4_STA
CA
CA
CA
CA
CO
FM
CO
FM
BA
FL
BA
FL
STO
STO
FM FL
CO BA
STO
STO
STA =Start Condition
STO = Stop Condition
CA Chip Address Byte
CO =Data Byte for Control Information
BA = Band Information
FM =Data Byte for Frequency Information (MSB's)
FL =Data Byte for Frequency Information (LSB's)
=
Figure 5 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two
9-392
ACK
I
I L........J
DATA
ACK
L..P-.J
STO
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received: if three data bytes are received the third data byte
is ignored.
If five or more data bytes are received the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.
Frequency information is preceded by a Logic "0". If the
function bit is Logic "1" the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
The two permissible bus protocols with five bytes are
shown in Figure 5.
The Data and Clock inputs (Pins 10 and 11) are high
impedance when the supply voltage VCC1 is between 0 and
5.5V.
MOTOROLA ANALOG IC DEVICE DATA
MC44826
Chip Address
The chip address is programmable by Pin 9 (CA - Address
Select).
CA- Pin 9
Address (HEX.)
-0.04 VCCl to 0.1 VCCl
C6
Open or 0.2 VCCl to 0.3 VCCl
C4
0.42 VCCl to 0.75 VCCl
C2
0.9 VCCl 10 1.2 VCC1
CO
Figure 5. Definition of Bytes
o
o
o
011
011
o
ACK
BA_Band Information
FM_Frequency Information
FL_Frequency Information
FM_Frequency Information
FL_Frequency Information
a
BA_Band Information
Figure 6. Typical Tuner Application
IF
6
L--,----'
L....:--'T-j=7---r---l!Jb.o--SDA
f----~:>---SCL
L-~~------~Q4--CA
T
12pF
o
3.214.0 MHz
l
VTUN
AGC
NOTES: 1. On some layouts the 100 II resistor will not be required.
2. C2 = 330 pF minimum is required for stability.
MOTOROLA ANALOG IC DEVICE DATA
22nF
9-393
MC44826
Bits B1. B3. B5: Control the Band Buffers
I Buffer
"Off"
Buffer "On"
Bit T8: Controls the Output of the Operational Amplifier
T8 = a
=1
Normal Operation
Operational Amplifier Active
Output State of Operational Amplifier Switched "Off",
Output Pulls High Through the External Pull-Up
Resistor RL
Bits T9. T12: Control the Phase Comparator
T9
T12
1
1
a
Function
Normal Operation
High Impedance
Upper Source "On" Only
Lower Source "On" Only
1
a
a
a
1
Bits T10. T11: Control the Reference Divider
T10
T11
a
a
a
Division Ratio
512
1024
1024
512
1
a
1
1
1
Bit T 13: Switches the Internal Signals Fref and FBY2 to
the Band Buffer Outputs (Test)
T 13
=a
Normal Operation
=1
Test Mode
Fref Output at B3 (Pin 7)
FBY2 Output at B5 (Pin 8)
II
Bits B3 and B5 have to be "On", B3 = B5 = 1 In the test mode.
Frel is the reference frequency.
FBY2 is the output frequency of the programmable divider, divided by two.
Bit T 14: Controls the Charge Pump Current of the
Phase Comparator
Pump Current 40 ~ Typical
Normal Operation. Pump Current 125 ~ Typical
Bits T6. T7: Mixer/Oscillator Band Decoder
The band decoder provides the band switching signal for
the mixer/oscillator circuit. The buffer bits control the decoder
output. The decoder can be controlled by the buffer bits or
independently by the control bits T6 and T7 as per the tables
below.
T7
T6
a
a
a
1
Decoder Output DEC
Decoder Output Controlled by Buffer Bits
Bl, B3, Bs
OtoO.8V
1.8t02.1 V
3.4 V to VCC1 (VCC1 = 4.5 to 5.5 V)
1
1
a
8S
83
81
a
a
x
x
a
1
X
a
1
X
1
1
1
Decoder Output DEC
1.8t02.1 V
OtoO.BV
3.4V to VCC1
(VCC1 = 4.5 to 5.5 V)
Undefined
BA_Band Information
B3
9-394
X
ACK
The band buffers are open collector buffers and are active
"low". at Bn = 1. They are designed for 15 mA with a typical
"On" voltage of 200 mY. These buffers are designed to
withstand relative high output voltage in the "Off' state.
B3 and B5 buffers may also be used to output internal IC
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.
The bit B3 and/or B5 have to be one if the buffers are used
for these additional functions.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TOI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N =16384xN14 + 8192 x N13 + ... + 4x N2 + 2x N1 + NO
Maximum Ratio 32767
Minimum Ratio 256
Where NO ... N14 are the different bits for frequency
information.
The counter may be used for any ratio between 256 and
32767, and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.
The data transfer between latches A and B (signal TOI) is
also initiated by any start condition on the 12C bus.
At power-on the whole bus receiver is reset and the bit N8
of the programmable divider is set to Na = 1. Thus the
programmable divider starts with a division ratio of 256 or
higher.
The first 12C message must be sent only when the
POWER ON RESET is completed. Division ratios of N < 256
are not allowed.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Tuning Voltage Amplifier
The amplifier is designed for very low noise, low input bias
current and high power supply rejection. The positive input is
biased internally. The tuning voltage amplifier· needs an
external pull-up resistor to generate the tuning voltage.
The amplifier can be switched "Off' through bit TB. When
bit T8 is "One", the amplifier is "Off". The tuning voltage is
then pulled high by the external pull-up resistor.
Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
The Oscillator
The oscillator uses a 3.2 or 4.0 MHz crystal tied to ground in
series with a capaCitor. The crystal operates in its series
resonance mode.
The voltage at Pin 13, has low amplitude and low
harmonic distortion.
The negative impedance of the crystal input (Pin 13) is
about 3.0 kn.
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44827
Product Preview
PLL Tuning Circuit
with 3-Wire Bus
The MC44827 is a tuning circuit for TV and VCR tuner applications. This
device contains on one chip all the functions required for PLL control of a
VCO. This integrated circuit also contains a high frequency prescaler and
thus can handle frequencies up to 1.3 GHz.
The MC44827 is controlled by a 3-wire bus. It has the same function as
the MC44828 which is 12C bus controlled. The MC44827 and MC44828 can
replace each other to allow conversion between 3-wire bus and 12C bus
control.
The MC44827 is manufactured on a single silicon chip using Motorola's
high density bipolar process, MOSAICTM (Motorola Oxide Self Aligned
Implanted Circuits).
The MC44827 has the same features as MC44817 with the following
differences:
PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND 3-WIRE BUS
SEMICONDUCTOR
TECHNICAL DATA
16
• Lower Power Consumption, 200 mW Typical
• Improved Prescaler with Higher Margins for Sensitivity and Temperature
Range. (A typical device is functional in a temperature range greater
than -40 to 100°C.)
• Lock Detector with Push-Pull Output
DTBSUFFIX
PLASTIC PACKAGE
CASE 948F
(TSSOP-16)
• No Bypass of Divide-by-8 Prescaler
• TSSOP Package
II
PIN CONNECTIONS
16 Pin TSSOP
DA
MOSAIC is a trademark of Motorola, Inc.
0
CL
XTAL
Amp In
VTUN
VCC2 33V
ORDERING INFORMATION
Device
MC44827DTB
VCC1 5.OV
Operating
Temperature Range
Package
TJ = -20 ° to +80°C
16 Pin TSSOP
(Top View)
MOTOROLA ANALOG IC DEVICE DATA
9-395
®
MOTOROLA
MC44828
Product Preview
PLL Tuning Circuit
with 12C Bus
The MC44828 is a tuning circuit for TV and VCR tuner applications. This
device contains on one chip all the functions required for PLL control of a
VCO. This integrated circuit also contains a high frequency prescaler and
thus can handle frequencies up to 1.3 GHz.
The MC44828 is controlled by an 12C bus. It has the same function as the
MC44827 which is 3-wire bus controlled. The MC44827 and MC44828 can
replace each other to allow conversion between 3--wire bus and 12C bus
control.
The MC44828 is manufactured on a single silicon chip using Motorola's
high density bipolar process, MOSAICTM (Motorola Oxide Self Aligned
Implanted Circuits).
The MC44828 has the same features as MC44818 with the following
differences:
PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER .
AND 12C BUS
SEMICONDUCTOR
TECHNICAL DATA
16
• Lower Power Consumption, 200 mW Typical
• Improved Prescaler with Higher Margins for Sensitivity and Temperature
Range. (A typical device is functional in a temperature range greater
than -40 to 100°C.)
• Lock Detector with Push-Pull Output
DTBSUFFIX
PLASTIC PACKAGE
CASE948F
(TSSOP-16)
• TSSOP Package
PIN CONNECTIONS
16 Pin TSSOP
MOSAIC is a trademark of Motorola, Inc.
DA
0
XTAl
VTUN
ORDERING INFORMATION
Device
MC44828DTB
VCC233 V
Operating
Temperature Range
Package
TJ =-20 ° to +80°C
16 Pin TSSOP
VCC15.OV 7
HFln
(Top View)
9-396
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44829
PLL Tuning Circuit
with 12C Bus
The MC44829 is a tuning circuit for TV and VCR tuner applications. It
contains, on one chip, all the functions required for PLL control of a VCO.
This integrated circuit also contains a high frequency prescaler and thus
can handle frequencies up to 1.3 GHz. The circuit has a band decoder that
provides the band switching signal for the mixer/oscillator circuit. The
decoder is controlled by the buffer bits.
The MC44829 has programmable 51211024 reference dividers and is
manufactured on a single silicon chip using Motorola's high density bipolar
process, MOSAICTM (Motorola Oxide Self Aligned Implanted Circuits).
TV AND VCR
12C PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND Mlx/OSC DECODER
SEMICONDUCTOR
TECHNICAL DATA
• Complete Single Chip System for MPU Control (l2C Bus)
• Divide-by-8 Prescaler Accepts Frequencies up to 1.3 GHz
.#
• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512 and 1024
• 3-State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output (30 V)
• Four Programmable Chip Addresses
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
• Integrated Band Decoder for the Mixer/Oscillator Circuit
• Band Buffers with Low "On" Voltage (0.4 V Maximum at 5.0 mAl
• Fully ESD Protected to MIL-STD-883C, Method 3015.7
(2000 V, 1.5 kg, 150 pF)
II
PIN CONNECTIONS
MOSAIC is a trademark of Motorola, Inc.
0
VTUN
MAXIMUM RATINGS (TA = 25'C, unless otherwise noted.)
Rating
Pin
Value
Unit
5
6.0
V
Band Buffer "Off' Voltage
6,7,8
15
V
Band Buffer "On" Current
6,7,8
10
mA
1
40
V
Power Supply Voltage (VCC1)
Operational Amplifier Power Supply (VCC2)
3,4
1.5
Vrms
Storage Temperature
RF Input Level 10 MHz to 1.3 GHz
-
-65 to +150
'C
Operating Temperature Range
-
-20 to +80
'C
Bus Input Voltage (Posijive)
10,11
7.0
V
Bus Input Voltage (Negative)
10,11
-0.5
V
14
PHD
Gnd
2
13
Xtal
HF1
3
12
DEC
HF2
4
11
SDA
VCC1
5
10
SCL
84
6
9
CA
B5
7
8
B6
(Top View)
ORDERING INFORMATION
MOTOROLA ANALOG IC DEVICE DATA
Device
Operating
Temperature Range
Package
MC44829D
TA = -20' to +80'C
S0-14
9-397
MC44829
Representative Block Diagram
VTUN
VCC2
Rl
Cl
Bands Out
5.0V
5
7
6
14
2.7V
PHO
DTB1
Gnd
2
DTB2
POR
--<.I-::-.L...Li
CA6=-9_ _
SDA
11
SCl
10
Cl
f-----'=---.j
II
T 12pF
0
l
3.214.0
MHz
HF1,",-,-3_-",
HF2v--.......
DTS, EN
This device contains 3,204 active transistors.
9--398
MOTOROLA ANALOG IC DEVICE DATA
MC44829
ELECTRICAL CHARACTERISTICS (VCCI
= 5.0 V, VCC2 =33 V, TA =25°C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
5
4.5
5.0
5.5
V
5
25
35
50
mA
Band Buffer Leakage Current when "Off" at 12 V
6,7,8
-
0.01
1.0
itA
Band Buffer Saturation Voltage when "On" at 5.0 mA
6,7,8
-
0.16
0.4
V
Data/Clock Current at 0 V (Acknowledge "Off')
10,11
-10
-
0
itA
VCCI Supply Voltage Range
VCCI Supply Current (VCCI
=5.0 V)
Unit
Data/Clock Current at 5.0 V (Acknowledge "Off')
10,11
0
-
1.0
itA
Data/Clock Input Voltage Low
10,11
-
-
1.5
V
Data/Clock Input Voltage High
10,11
3.0
-
-
V
Data Saturation Voltage at 3.0 mA (Acknowledge "On")
11
-
0.25
0.4
V
Decoder "High" Level Sourcing 100 itA
12
3.4
VCCI
V
Decoder "Medium" Level Sourcing 15 ItA
12
1.8
Decoder "Low" Level Sinking 20 itA
12
-
2.1
V
0.8
V
Clock Frequency Range
10
a
-
100
kHz
Oscillator Frequency Range
13
3.15
3.2
4.05
MHz
Operational Amplifier Internal Reference Voltage
-
2.0
2.75
3.2
V
Operational Amplifier Input Current
14
-15
a
15
nA
DC Open Loop Gain (RL = 22 kQ)
14,1
100
250
1000
VN
Gain Bandwidth Product (CL = 0.5 nF)
14,1
0.3
-
-
MHz
1
-
0.45
0.65
V
Phase Detector Tri-State Current
14
-15
a
15
nA
Charge Pump Current of Phase Comparator (T 14 =0)
14
30
40
50
Charge Pump Current of Phase Comparator (T 14 = 1)
14
90
125
150
ItA
ItA
1
25
33
36
V
Vout Low (RL = 22 kQ)
VCC2 Supply Voltage Range
II
PIN FUNCTION DESCRIPTION
Pin
Function
1
VTUNNCC2
2
Gnd
3,4
HF1/HF2
Description
Output of the tuning voltage amplifier. Needs an external pull-up resistor to drive the varicaps
Ground
Symmetric HF inputs from local oscillator
5
VCCI
6,7,8
B4,B5,%
9
CA
Chip address selection pin
10
SCL
Clock input of the 12C bus
11
SDA
Data input
12
DEC
Band decoder output for the mixer/oscillator circuit
13
Xtal
Crystal input
14
PHO
Input of tuning voltage amplifier
Supply voltage. Typical 5.0 V
Band buffer outputs
MOTOROLA ANALOG IC DEVICE DATA
9-399
MC44829
Figure 1. Typical Prescaler Input Sensitivity
o
200
400
600
800
1000
1200
1400
RF In (MHz)
NOTE:
Vee = 4.5 to 5.5 V, TA = - 20° to +80 0 e
HF CHARACTERISTICS (See Figure 1)
Pin
Min
TyP
Max
Unit
DC Bias
3,4
-
1.6
-
V
Input Voltage Range
50-950 MHz
950-1300 MHz
3,4
3,4
10
50
-
315
315
Characteristic
mVrms
Figure 2. RF Sensitivity Test Circuit
II
12C Bus Controller
10,11
+5.0 V
5
2
-=-
MC44829
VCC1
7
8
B5
4.0k
B6
RF Generator
(500)
+12V
4.0kQ
Frequency Counter
Device is in test mode, B5 and B6 are "On", B4 is "Off'.
Sensitivity is the level of the HF generator of 50 Q load.
9-400
MOTOROI;J. ANALOG IC DEVICE DATA
MC44829
Figure 3. Typical HF Input Impedance
+j
_-j0 _
_
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the 12C bus. The incoming information, consisting of a
chip address byte followed by two or four data bytes, is
treated in the 12C bus receiver. The definition of the
permissible bus protocol is shown below:
1_STA
2_STA
3_STA
4_STA
CA
CA
CA
CA
CO
FM
CO
FM
BA
FL
BA
FL
STO
STO
FM
FL
CO
BA
STA = Start Condition
STO = Stop Condition
CA =Chip Address Byte
CO = Data Byte for Control Information
BA = Band Information
FM =Data Byte for Frequency Information (MSB's)
FL = Data Byte for Frequency Information (LSB's)
II
STO
STO
Figure 4. Complete Data Transfer Process
r,
r,
SDA:V--'---JC~~-_~
SCLi!\J1~;\
f;,\. f0
r1-"'~1~:;'rVr;'8 V
I I
,voU'LJ
LS-.J
STA
I
I
ADDRESS
CA
L-.......J L - - J
R!W
ACK
MOTOROLA ANALOG IC DEVICE DATA
I
IL-......J
DATA
ACK
I
I
DATA
V:H:
r;"
9
L-.......J
LP-.J
ACK
STO
9-401
MC44829
Figure 5 shows the five bytes of information that are
needed for circuit operation: there is the chip address,'two
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received: if three data bytes are received the third data byte
is ignored.
If five or more data bytes are received the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.
Frequency information is preceded by a Logic "0". If the
function bit is Logic "1" the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
The two permissible bus protocols with five bytes are
shown in Figure 5.
The Data and Clock inputs (Pins 10 and 11) are high
impedance when the supply voltage VCC1 is between 0 and
5.5V.
Chip Address
The chip address is programmable by Pin 9 (CA - Address
Select).
CA- Pin 9
Address (HEX.)
-0.04VCC1 toO.1 VCC1
Co
Open or 0.2 VCC1 to 0.3 VCC1
C2
0.42 VCC1 to 0,75 VCC1
C4
0.9 VCC1 to 1.2 VCC1
C6
Figure 5. Definition of Bytes
CA_Chip Address
BA_Band Information
FM_Frequency Information
FL_Frequency Information
CA_Chip Address
II
FM_Frequency Information
FL_Frequency Information
BA_Band Information
9-402
x
x
x
x
x
ACK
MOTOROLA ANALOG IC DEVICE DATA
MC44829
Figure 6. Typical Tuner Application
IF
UHF
VHF
6
L-_-----I
~~-T___i=~---.--~~_ SDA
1---.!¥6_ SCL
L~-,"-----2it"l.-
CA
T 12pF
o
3.214.0 MHz
l
VTUN
AGC
NOTE: C2 = 330 pF minimum is required for stability.
Bits B4. BS. B6: Control the Band Buffers
I Buffer
"Off"
Buffer "On"
B4, B5, B6 = 0
=1
Bit T14: Controls the Charge Pump Current of the
Phase Comparator
Pump Current 40 !IA Typical
Normal Operation. Pump Current 12511A Typical
Bit Ta: Controls the Output of the Operational Amplifier
T8 = 0
=1
Normal Operation
Operational Amplifier Active
Output State of Operational Amplifier Switched "Off",
Output Pulls High Through the External Pull-Up
ResistorRl
Bits Tg. T12: Control the Phase Comparator
Tg
T12
1
1
0
0
0
1
0
1
Function
Normal Operation
High Impedance (Tri-State)
Upper Source "On" Only
lower Source 'On" Only
Bits T10. T11: Control the Reference Divider
T10
T11
0
0
1
1
0
1
0
1
Mixer/Oscillator Band Decoder
The band decoder provides the band switching signal for
the mixer/oscillator circuit. The buffer bits B4 and B6 control
the decoder output. BS is not decoded. The decoder is
controlled by the buffer bits as per the table below
86
85
84
0
0
X
X
0
1
1
1
X
X
0
1
Decoder Output DEC
Undefined
3.4 Vto VCC1
(VCC1 = 4.5 to 5.5 V)
Oto 0.8 V
1.8t02.1 V
BA_Band Information
X
X
X
X
ACK
Division Ratio
512
1024
1024
512
Bit T13: Switches the Internal Signals Fref and FBY2 to
the Band Buffer Outputs (Test)
Normal Operation
Test Mode
Fref Output at B5 (Pin 7)
FBY2 Output at B6 (Pin 8)
Bits BS and Be have to be "On", BS = Be = 1 in the test mode.
Fref is the reference frequency.
FBY2 is the output frequency of the programmable divider, divided by two.
MOTOROLA ANALOG IC DEVICE DATA
The band buffers are open collector buffers and are active
"low" at Bn = 1. They are designed for S.O mA with a typical
"on" voltage of 160 mY. These buffers are designed to
withstand relative high output voltage in the "off" state.
BS and B6 buffers may also be used to output internal Ie
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.
The bit BS andlor B6 have to be one if the buffers are used
for these additional functions.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TOI which is synchronous to the
programmable divider output signal.
II
•
MC44829
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N =16384 x N14+ 8132x N13+ ... +4x N2+2xN1 + NO
Maximum Ratio 32767
Minimum Ratio 256
Where NO .. , N14. are the different bits for frequency
information.
The counter may be used for any ratio between 256 and
32767 and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.
The data transfer between latches A and B (signal TDI) is
also initiated by any start condition on the 12C bus.
At power "on" the whole bus receiver is reset and the bit N8
of the programmable divider is set to N8 = 1. Thus the
programmable divider starts with a division ratio of 256 or
higher.
The first 12C message must be sent only when the
POWER ON RESET is completed. Division ratios of N < 256
are not allowed.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The tuning Voltage Amplifier
The amplifier is designed for very low noise, low input bias
current and high power supply rejection. The positive input is
biased internally. The tuning voltage amplifier needs an
external pull-up resistor to generate the tuning voltage.
The amplifier can be switched "off" through bit T 8. When bit
T8 is "One", the amplifier is "Off". The tuning voltage is then
pulled high by the external pull-up resistor.
Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
The Oscillator
The oscillator uses a 3.2 or 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in its series
resonance mode.
The voltage at Pin 13, has low amplitude and low
harmonic distortion.
The negative impedance of the crystal input (Pin 13) is
about 3.0 kil.
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC44864
Advance Information
PLL Tuning Circuit with
1.3 GHz Prescaler and D/A
Converters for Automatic
Tuner Alignment
The MC44864 is a tuning circuit for TV applications. This device contains
a PLL section and a DAC section and is MCU controlled through an 12C Bus.
The PLL section contains all the functions required to control the VCO of a
TV tuner. The IC generates the tuning voltage and the additional control
signals, such as band switching voltages.
The D/A section generates three additional varactor voltages to feed all of
the varactors of the tuner with individually optimized control voltages
(automatic tuner adjustment). The MC44864 is manufactured on a single
silicon chip using Motorola's high density bipolar process, MOSIACTM
(Motorola Oxide Self-Aligned Implanted Circuits).
PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND D/A CONVERTERS
SEMICONDUCTOR
TECHNICAL DATA
• Complete Single Chip System for MPU Control
• Selectable +8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
• Programmable Reference Divider
• 3-State Phase/Frequency Comparator
MSUFFIX
PLASTIC PACKAGE
CASE 967
(EIAJ-20)
• Operational Amplifier for Direct Varactor Control with Low Saturation
Voltage
• Four Output Buffers (15 mAl
• Output Options for 62.5 kHz, Reference Frequency and the
Programmable Divider
II
• The HF Input is Symmetrical
• Three 6 Bit DACs for Automatic Tuner Adjustment Allowing Use of
Non-Matched Varactors
PIN CONNECTIONS
• Better Tuner Performances Through Optimum Filter Response
• 12C Bus Controlled
XTAL
Gnd
• Four ChiP. Addresses for the PLL Section
PHO
SDA
• Four Chip Addresses for the D/A Section
Amp In
SCL
VCC2
B7
VTUN
DAI
Sa
• ESD Protected to MIL-STD-883C, Method 3015.7
(2,000 V, 1.5 kil, 150 pF)
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltage (VCC1)
Pin
Value
Unit
9
6.0
V
Band Buffer "Off' Voltage
14-17
15
V
Band Buffer "On" Current
14-17
20
mA
4
36
V
5-8
Continuous
S
Storage Temperature
-
-65 to +150
°C
Operating Temperature Range
-
Oto+70
°C
Operational Amplifier Power Supply
Voltage (VCC2)
Operational Amplifier Short Circuit Duration
(OtoVCC2)
NOTE: ESD data available upon request.
B5
DA2
Bl
DA3
CA
VCCI
Gnd
HFI
HF2
(Top View)
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
EIAJ-20
MOTOROLA ANALOG IC DEVICE DATA
9-405
MC44864
Representative Block Diagram
DA3
DA2
DAI
f-~--"OAmp
In
DIAl
6 Bit
Ref
Voltage
Latches
r - - - - - " " 20 PHD
VCCI
9
5.0V
DTC
CA
SCL
SDA
Gnd
Shift Register
8Bn
13
18
19
1----'0 XTAL
,--_---2"'0'0 Gnd
12
-=-
II
HFI
HF2
10
11
Preamp 2
This device contains 3,551 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
MC44864
ELECTRICAL CHARACTERISTICS (VCCl
=5.0 V, VCC2 =32 V, TA =25°C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
9
4.5
5.0
5.5
V
9
-
50
70
mA
VCC2 Supply Voltage Range
4
25
30
35
V
VCC2 Supply Current (Output Open)
4
1.3
2.5(4)
mA
0.01
1.0
I1A
1.8
2.0
V
VCCl Supply Voltage Range
VCCl Supply Current (VCCl
=5.0 V)(1)(2)
Band Buffer Leakage Current when "Off' at 12 V
14-17
Band Buffer Saturation Voltage when "On" at 15 mA
14-17
-
18,19
-10
-
0
Clock Current at 5.0 V
18
0
19
0
-
1.0
Data Current at 5.0 V Acknowledge "Off'
Data Saturation Voltage at 15 mA Acknowledge "On"
19
Data/Clock Current at 0 V
Unit
1.0
I1A
I1A
I1A
1.2
-
V
-
1.5
V
Data/Clock Input Voltage Low
18,19
-
Data/Clock Input Voltage High
18,19
3.0
-
-
V
18
-
100
kHz
Clock Frequency Range
Phase Detector Current in High Impedance State
Oscillator Frequency Range
2
-15
-
15
nA
1,2
3.5
4.0
4.1
MHz
Phase Detector High-State Source Current (@ 1.5 V)
2
-2.5
-
-{l.5
mA
Phase Detector Low-State Sink Current (@ 4.0 V)
2
0.5
-
2.5
mA
Operational Amplifier Internal Reference Voltage
-
2.0
2.5
3.0
V
Operational Amplifier Input Current
3
-15
-
15
nA
DC Open Loop Gain
-
2000
-
-
VN
Gain Bandwidth Product
-
-
0.2
-
MHz
Deg.
-
-
50
-
Vout Low, Sinking 50 I1A
6-8
-
0.2
0.5
V
Vout High, Sourcing 50 I1A (VCC2 - Vout High)
6-8
-
-
1.5
V
Phase Margin
Tuning Voltage (DC)
5-8
-
-
30
V
D/A Converters Step Size(3)
6-8
0.5
-
1.5
LSB
D/A Converters Temperature Drift
6-8
-
1.0
-
LSB
-
-50
-
50
mV
-
-700
-
700
mV
6-8
-
-
33
V
DAC Offset at VTUN
DAC Offset at VTUN
=2.5 V
=25 V
DAC Voltages (DC)
NOTES: 1. When prescaler "Off"', typical supply current is decreased by 10 rnA.
2. Band Buffers "Off', 2.4 rnA more when one buffer is on.
3. For definttion of the LSB, see Figure 9 in the D/A section.
4.2.5 rnA as long as the analog outputs are not in saturation high, which means VTUN, VDAC (Pins 5, 6, 7, 8) lower than VCC2 - 1.5 V. When all
outputs are in saturation high the maximum VCC2 current is 5.0 rnA.
MOTOROLA ANALOG IC DEVICE DATA
9-407
II
MC44864
HF CHARACTERISTICS (See Figure 1)
Characteristic
DC Bias
Input Voltage Range
10-150 MHz (Prescaler "Off')
80-1000 MHz
1000-1300 MHz
Pin
Min
Typ
Max
10,11
-
1.55
-
Unit
V
mVrms
10,11
10,11
10,11
20
20
50
-
315
315
315
-
Figure 1. HF Sensitivity Test Circuit
12V
Bus Controller
18,19
+S.OV VCCI 9
MC44864
11
10
Frequency
Counter
1.0nF
son Cable
son
Device is in test mode: B7 is "On", R2 = 1 and R3 = 0 (see Bus section).
Sensijivily is the level of the HF generator on 50 Q load (without MC44864 load).
_0_
Figure 2. 'TYpical HF Input Impedance
II
-j
9-408
+j
MOTOROLA ANALOG IC DEVICE DATA
MC44864
PIN FUNCTION DESCRIPTION
Pin
6.7.8
9
Symbol
DA1. DA2. DA3
Description
DIA output control voltages
VCCl
Positive supply of the circuit (except DACs)
10.11
HF1. HF2
HF input from local oscillator
12.20
Gnd
Ground
13
CA
Chip Address
Bl. B3. B5. B7
Band buffer output can drive 15 rnA
18
SCL
Clock input (supplied by the microprocessor via Bus)
19
SDA
Data input (bus)
1
XTAL
Crystal oscillator (typically 4.0 MHz)
2
PHO
Phase comparator output
3
Amp In
Negative operational amplifier input
4
VCC2
Operational amplifier positive supply
5
VTUN
Operational
14.15.16.17
ampl~ier
output which provides the tuning voltage
II
MOTOROLA ANALOG IC DEVICE DATA
9-409
MC44864
Figure 3. Pin Circuit Schematic
r--------
I
I
I
I
I
I
I
I
I
I
DA1
6
DA2
7
DA3
r----- J
---,
20V
20V
vrUN
5
20V
<> VCC2
L--_ _ _ _ _
4
20V
600k
I
I
20V
I
I
~V
I
I _______
-= _ _ _ _ _ _ _ _-_ _ _ JI
8o--~----~
Amp
}-..---+--.JWI..---.----O In
3
&-~Afu--~~~--
~
VCC1
9
. -_ _ _ _ _~-o~HO
S.SV
~V
5.5V
HF1
10
II
HF2
11
XTAL
1
5.5 V
Gnd
20
5.5V
SDA
Gnd
12
l---.--JVl."v-........-o 19
CA
l---ilNlr--........--o SCL
13O---~-~~-~-~
18
20V
------------l
~l o - - - - - - - - - - - i - - r - -..-----.......
2.5k
f-_ _ _-<>B7
17
VCC1!
I
I
I
I
On/Off
I
_ _ _ _ _ _ _ JI
r-~--~NY--~
B30-_ _ _--1
15
I
Buffer
______ _
~_~
9-410
~
1 - - - - - - - 0 B5
16
MOTOROLA ANALOG IC DEVICE DATA
MC44864
FUNCTIONAL DESCRIPTION
optimum value of the other varactor voltages. The digital
word for each voltage value is stored in a nonvolatile memory
(NVM). Hence, for each frequency pOint to be adjusted, three
times 6 bits of information have to be stored (plus 2 bits for
the DAC range).
The information stored in the NVM reflects the
characteristic of the individual tuner. For this reason, the
NVM is preferably situated inside the tuner and is also
controlled by the 12C Bus.
A representative block diagram and a typical system
application are shown in Figures 4 and 5. A discussion of the
features and function of the internal blocks is given below.
Automatic Tuner Alignment
The circuit generates the tuning voltage through the PLL.
The output voltages of the D/A converters are equal to the
tuning voltage plus a positive or negative offset of up to 31
steps. During the automatic alignment one first lets the PLL
lock to the. appropriate frequency and then searches for the
Figure 4. Block Diagram
DA3
DA2
DAl
390
1.00
1.00
I
I
18k
Amp
10
VCC1
5.0V
9
DIC
II
Shift Register
8Sn
10k
(1)
15k
-=-
CA
13
SCl
18
SDA
God
19
12
-=HFI
HF2
10
11
Preamp 2
NOTES: 1. Pin 13: Short to VCC
Resistors±10%
Open or 1.0 nF to Gnd
Short to Gnd
for addresses CC, CE
for addresses ca, CA (values 10 k and 15 k) for test only
for addresses C4, C6
for addresses CO, C2
2. The crystal may be connected to Pin 20 with no connection to extemal Gnd.
MOTOROLA ANALOG IC DEVICE DATA
9-411
MC44864.
Figure 5. TV Tuner for Automatic Alignment
IF
12V
Band Buffers
VCC2
VCC1
HF Input
MC44864
PLL-D/A IC
Clock
Data
Local
Oscillator
DA2
DA3
33V
S.OV
SCL
SDA
D-to-A
Converters
DA1
Figure 6. Definition of Bytes
CO_Control Information
BA-Band Information
FM_Frequency Information (with MSB)
FL_Frequency Information (with LSB)
Chip Addresses
The chip address is programmable by Pin CA.
The PLL addresses CO, C2, C4, C6 are officially allocated
to PLL-IC's.
The addresses ca, CA, CC, CE are not officially allocated.
Care has to be taken in the application that no conflict occurs
with other devices on the same 12C Bus when using the
addresses ca to CEo
CA Pin (13)
A3
A2
Al
AO
Address
Function
-Q.04 VCCI 10
0.1 VCCI
0
0
0
0
0
1
0
0
CO
C2
lsi PLL
lslDAC
Open or 0.2
VCC1100.3VCCI
0
0
1
1
0
1
0
0
C4
C6
2nd PLL
2nd DAC
0.42VCC1 10
0.75VCCI
1
1
0
0
0
1
0
0
C8
CA
3rd PLL
3rd DAC
0.9 VCCI 10 1.2
VCCI
1
1
1
1
0
0
0
CC
CE
41h PLL
41h DAC
9-412
1
PLLSECTION
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via 12C Bus. The incoming information is treated in the bus
receiver. The definition of the permissible bus protocol is
shown in the four examples below:
Ex. 1 STA CAl
CO
BA STO
Ex.2 STA CAl
FM
FL
STO
Ex.3 STA CAl
CO
BA FM
FL
STO
Ex.4 STA CAl
FM
FL
BA
CO
STO
STA = Start Condition
STO =Stop Condition
CA 1 Chip Address Byte of the PLL Section
CO =Data Byte for Control Information
BA =Band Information
FM =Data Byte for Frequency Information (MSB's)
FL = Data Byte for Frequency Information (LSB's)
Figure 6 shows the five bytes of information that are
needed for circuit operation: there is a chip address, two
bytes of control and band information and two bytes of
frequency information.
=
MOTOROLA ANALOG IC DEVICE DATA
MC44864
After the chip address, two or four data bytes may be
received: if three data bytes are received, the third data byte
is ignored. If five or more data bytes are received, the fifth
and following data bytes are ignored and the last
acknowledge pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit F. If
the function bit F= 0, frequency information is acknowledged
and if F = 1, control/band information is acknowledged.
If the address is correct (signal A01) the information is
loaded into latches.
A function bit in the first and third data byte is used to pass
this data either into the latches of the programmable divider
(signal OTF) or into the latches for band and control information
(signal OTB). The data transfer to the latches (signals OTF and
OTB) is initiated after the 2nd and 4th data bytes.
A second string of latches is used for the data transfer into
the programmable divider to inhibit the transfer during the
preset operation (signal TOI, signal AVA is an internal
"address valid" command).
The switching levels of clock and data (Pins 18 and 19) are
0.5 XVCC1.
The control and band information bits have the following
functions.
Bits RO, R1: Controls Reference Divider Division Ratio
RO
Rl
Division Ratio
0
1
0
1
0
0
1
1
2048
1024
512
256
Bits R2, R3: Switches Internal Signals to the Buffer
Outputs
R2
R3
Pin 16
Pin 17
0
0
0
1
0
1
62.5 kHz
Fret
-
1
1
-
FBY2
-
Bit B5 has to be "one" when Pin 16 is used to output 62.5
kHz. Bits 85 and 87 have to be "one" to output Fref and FBY2.
FBY2 is the programmable divider output frequency divided
by two.
Bits R2, RS, T: Controls the Phase Comparator Output
Stage
R2
R6
T
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Output State
Normal Operation
"Off" (High Impedance)
High
Low
Normal Operation
"Off"
Normal Operation
"Off'
The Band Buffers
The band buffers are open collector transistors and are
active "low" at 8n = 1. They are designed for 15 mA with
typical on-voltage of 1.8 V. These buffers are designed to
withstand relative high output voltage in the off-state (15 V).
85 and 87 buffers (Pins 16 and 17) may also be used to
output internal IC signals (reference frequency and
programmable divider output frequency divided by 2) for test
purposes.
MOTOROLA ANALOG IC DEVICE DATA
8uffer 85 may also be used to output a 62.5 kHz frequency
from an intermediate stage of the reference divider. The bits
85 and 87 have to be "one" if the buffers are used for these
additional functions.
The Programmable Divider
The programmable divider is a preseltable down counter.
When it has counted to zero it takes its required division ratio
out of the latches 8. Latches B are loaded from latches A by
means of Signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384x N14+ 8192x N13+ ... +4x N2+ 2 x N1 + NO
Maximum Ratio 32767
Minimum Ratio 256
where NO ... N 14 are the different bits for frequency
information.
The counter reloads correctly as long as its output
frequency does not exceed 1.0 MHz.
Division ratios of < 256 are not allowed. At power-up the
counter bit N8 is preset to"1 ". AII.other bits are undetermined.
In this way, the counter always starts with a division ratio of
256 or higher.
The data transfer between latches A and 8 (signal TDI) is
also initiated by any start condition on the bus.
At power-on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The prescaler has a preamplifier and may be bypassed
(Bit Pl. The signal then passes through preamplifier 2.
The table on the following page shows the frequency
ranges which may be synthesized with and without prescaler.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Operational Amplifier
The operational amplifier for the tuning voltage is designed
for low noise, low input bias current and high power supply
rejection. The positive input is biased internally. The
operational amplifier needs 30 V supply (VCC2) as minimum
voltage for a guaranteed maximum tuning voltage of 28.5 V.
Figure 4 shows the usual filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 4 may be used for 7.8125 kHz reference frequency
in a multi band TV tuner.
The Oscillator
The oscillator uses a 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The crystal is driven through a 1.6 kQ resistor on Chip.
The voltage at Pin 16 "crystal", has low amplitude and low
harmonic distortion.
The negative resistance of the oscillator at Pin 1 (XTAL) is
about 3.0 kQ.
9-413
II
MC44864
With Int. Prescaler
Without Prescaler
P 1
p=o
Input Data
RO
R1
Ref. Divider
Div. Ratio
0
1
0
1
0
0
1
1
2048
1024
512
256
=
Ref. Freq.
Hz(1)
Frequency,
Steps kHz
Max. Input
Freq. MHz
Frequency
Steps kHz
Max.lmput
Freq. MHz
1,953.125
3906.25
7812.5
15625.0
15.625
31.25
62.5
125.0
512
1024
1300(2)
1300(2)
1.953125
3.90625
7.8125
15.625
64
128
165(3)
165(3)
NOTES: 1. Wnh 4.0 MHz Crystal
2. Limit of Prescaler
3. Limit of Programmable Divider
For satellite tuner applications the circun may be used with an external 14 prescaler and a reference divider ration of 1024 (RO = 1, Rl = 0). In this way,
frequencies up to 4.0 GHz can be synthesized with 125 kHz resolution (4.0 MHz crystal).
The same resutt can be achieved with an extemal/32 prescaler when the internal prescaler is bypassed (P = 1).
The Reference Divider
The reference divider of the MC44864 is programmable
(Bits RO and R1) for ratios of 2048,1024,512 and 256. This
feature makes the circuit versatile.
C3 contain the address for the individual converter and the 6
bits to be converted. Bit D5 is the sign (log "1" for positive
offset, log "0" for negative offset) and the bits DO to D4
determine the number of steps to be made as an offset from
the tuning voltage. The bits So and S1 in the data byte RA
define the step size (Vstep) and the range of the converters
(see Figures 8 and 9). The range is the same for all
converters.
After the chip address (CA2) is acknowledged, up to four
data bytes may be received by the IC. If more than four bytes
are received, the fifth and following bytes are ignored and the
last acknowledge pulse is sent after the fourth data byte. The
data transfer to the converters (signal DTC) is initiated each
time a complete data byte is received.
The following shows some examples of the permissible
bus protocols of the D-to-A section. The data bytes may be
sent to the IC in random order with up to four in one
sequence. The same converter may be loaded up to four
times as Shown in example 6. Below are 6 examples of
permissible bus protocols.
Bit P: Controls the Prescaler
P
0
1
Prescaler Function
Prescaler Active
Prescaler Bypassed
Prescaler Power Supply "Off"
Bits B1. B3. BS. B7: Controls the Band Buffers
B1, B3, B5, B7 = 0
=1
I
Buffer "Off"
Buffer "On"
D/ASECTION
Basic Function
The D/A section has four separate chip addresses from
the PLL section. Three D-to-A converters that have a
resolution of 6 bits (5 bits plus sign) are on chip. The analog
output voltages are dc. The converters are buffered to the
analog outputs DA1, DA2 and DA3 by operational amplifiers
with an output voltage range that is equal to the tuning
voltage range (about 0 to 30 V). The operational amplifiers
are arranged such that a positive or negative offset can be
generated from the tuning voltage.
Ex. 1
Ex. 2
Ex. 3
Ex. 4
Ex.5
Ex. 6
STA
STA
STA
STA
STA
STA
CA2
CA2
CA2
CA2
CA2
CA2
C1
C1
C1
C1
RA
C1
STO
C2
C2
C2
C1
C1
STO
C3
C3
C2
C1
STO
RA
STO
STO
C3
STO
C1
STA =Start Condition
STO =Stop Condition
CA2 = Chip Address Byte for D/A Section
C1, C2, C3 = Data Bytes for D/A Converters
RA =Data Byte for Range
Data Format and Bus Protocols
The D-to-A information consists of the D/A chip address
(CA2) and four data bytes. The first two bits of the data bytes
are used as the function address. Thus the bytes C1, C2 and
Figure 7. Definition of Bytes
CA2_D/A Chip Address
o
ACK
0
CCConverter 1
C3_Conv,erter 3
RA_Range Selection
9--414
So
MOTOROLA ANALOG IC DEVICE DATA
MC44864
Figure 8. Output Voltage (D/A Converters)
Os =1 positive sign; Os =0 negative sign
VTUN: Tuning Voltage set by Pll
Vstep: Voltage Step (lSB) of the OIA Converters
Figure 9. Range Selection of the D/A Converters
Input Data
So
S1
Typ. Step Size
Vstep
0
1
0
1
0
0
1
1
22SmV
12SmV
70mV
40mV
Guaranteed
Range 31
Steps
6.2SV
3.40 V
1.90V
1.0SV
The D/A Converters
The D/A converters convert 5 bit into analog current of
which the polarity is switched by the sixth bit. The reference
voltage of the converters is programmed by two bits (SO, S1
of the RA-byte) to determine the scaling factor. The analog
OACOffsel
(VOAC - VTUN)
currents are then converted into voltages and added to their
respective operational amplifier nominal bias. The resulting
voltages at Pins 6, 7 and 8 are the tuning voltages (VTUN, see
Figure 4) at Pin 5 plus any offset provided by information in
the D/A converters.
If the data bits DO to D4 are all ·0", the three DIA output
voltages on Pins 6, 7 and 8 are equal to the tuning voltage
(Pin 5) within the DAC offset voltages.
The four amplifiers have the same output characteristics
with the maximum output voHage being 1.5 V lower than
VCC2 in the worst case. The four analog outputs are
short-circuit protected. At power-up, the D/A outputs are
undetermined.
The D/A converters are guaranteed to be monotonic with a
voltage step variation of ±O.5 LSB.
The D/A converters work correctly as long as the PLlloop
is active. VTUN is then between 0.3 V and VCC2-1.5 V.lfthe
loop saturates, the DACs do not work.
The DAC-OFFSET is defined as the difference between
the DAC output voltage (with bits DO to D4 0) and the tuning
voltage (PLL active). The DAC operation is guaranteed from
0.3 V to VCC2 - 1.5 V. On typical samples, the DACs will
operate down to 0.2 V.
=
Figure 10. Definition of DAC Offset
±700mVmax
II
10
MOTOROLA ANALOG IC DEVICE DATA
20
30V
9-415
II
9-416
MOTOROLA ANALOG IC DEVICE DATA
Automotive Electronic Circuits
In Brief ...
Motorola Analog has established itself as a global leader
in custom integrated circuits for the automotive market. With
multiple design centers located on four continents, global
process and assembly sites, and strategically located
. supply centers, Motorola serves the global automotive
. market needs. These products are key elements in the
rapidly' growing engine control, body, navigation,
entertainment, and communication electronics portions of
modern automobiles. Though Motorola is most active in
supplying automotive custom deSigns, many of yesterday's
proprietary custom devices have become standard products
of today, available to the broad base manufacturers who
support this industry. Today, based on new technologies,
Motorola offers a wide array of standard products ranging
from rugged high current "smart" fuel injector drivers which
control and protectthe fuel management system through the
rigors of the underhood environment, to the latest
SMARTMOSTM switches and series transient protectors.
Several devices are targeted to support microprocessor
housekeeping and data line protection. A wide range of
packaging is available including die, flip-chip, and SOICs for
high density layouts, to low thermal resistance multi-pin,
single-in-line types for high power controllCs.
MOTOROLA ANALOG Ie DEVICE DATA
Page
Voltage Regulators .............................. 10-2
Electronic Ignition ............................... 10-2
Special Functions ............................... 10-3
Package Overview ............................. 10-13
Device Listing .................................. 10-14
10-1
Automotive Electronic Circuits
Table 1. Voltage Regulators
Function
Suffixl
Package
Features
Device
Low Dropout Voltage
Regulator
Positive fixed and adjustable output voltage regulators which
maintain regulation with very low input to output vo~age differential.
Zl29, T/221 A,
T/314D, TH/314A,
TV/314B, DT/369A,
DT-1/369, D2T/936,
D2T/936A, D1751
LM2931, C
Low Dropout Dual
Regulator
Positive low voltage differential regulator which features dual 5.0 V
outputs, with currents in excess of 750 rnA (switched) and 10 rnA
standby, and quiescent current less than 3.0 rnA.
T/314D, TH/314A,
TV/314B, D2T/936A
LM2935
Automotive Voltage
Regulator
Provides load response control, duty cycle limiting, under/overvoltage
and phase detection, high side MOSFET field control, vo~age
regulatlon in 12 V alternator systems.
DW1751D
MC33092
Low Dropout Voltage
Regulator
Positive 5.0 V, 500 rnA regulator having on-chip power-up-reset
circuit with programmable delay, current limit, and thennal shutdown.
T/314D, TV/314B
MC33267
Low Dropout Voltage
Regulator
Positive 3.3 V, 5.0 V, 12 V, 800 rnA regulator.
D1751 , DT/369A
MC33269
Table 2. Electronic Ignition
Function
Features
Sufflxl
Package
Device
P/626, D1751 ,
Flip-Chlp
MC3334,
MCCF3334
Electronic Ignition
Circuit
Used in high energy variable dwell electronic ignition systems with
variable reluctance sensors. Dwell and spark energy are externally
adjustable. "Bumped" die for inverted mounting to substrate.
Electronic Ignition
Circuit
Used in high energy electronic ignition systems requiring differential
Hall Sensor control. "Bumped" die for inverted mounting to substrate.
DW1751G,
Fllp-Chlp
MC33093,
MCCF33093
Electronic Ignition
Circuit
Used in high energy electronic ignition systems requiring single Hall
Sensor control. "Bumped" die for inverted mounting to substrate.
DW1751G,
Flip-Chip
MC33094,
MCCF33094
Electronic Ignition
Circuit
Used in high energy electronic ignition systems requiring single Hall
Sensor control. Dwell feedback for coil variation. "Bumped" die for
inverted mounting to substrate.
DW1751G,
Flip-Chip
MC79076,
MCCF79076
10-2
MOTOROLA At.lALOG IC DEVICE DATA
Table 3. Special Functions
Function
Features
Suffixl
Package
Device
Low Side Protected
Switch
Single automotive low side switch having CMOS compatible input,
1.0 A maximum rating, with overcurrent, overvoHage and thermal
protection.
T/221 A, T-1/314D,
DWn51G
MC3392
Low Current High-Side
Switch
Drives loads from pos~ive side of power supply and protects against
high-voltage transients.
T/314D, DWn51G
MC3399
High-Side TMOS Driver
Designed to drive and protect N-channel power MOSFETs used in
high side switching applications. Has internal charge pump, externally
programmed timer and fauH reporting.
P/626, Dn51
MC33091A
MI-Bus Interface
Stepper Motor
Controller
High noise immunity serial communication using MI-Bus protocol to
control relay drivers and motors in harsh environments. Four phase
signals drive two phase motors in either half or full-step modes.
DWn51G
MC33192
Quad Fuel Injector
Driver
Four low side switches with paraliel CMOS compatible input control,
,;; 7.0 mA quiescent current, 0.25 n rDS(on) at 25'C independent
outputs with 3.0 A current limiting and internal 65 V clamps.
T/821D, TV/821C
MC33293A
Octal Serial Output
Switch
Eight low side switches having 8-bit serial CMOS compatible input
control, serial fault reporting, ,;; 4.0 mA quiescent current, independent
0.45 n rDS(on) at 25'C outputs with 3.0 A minimum current limiting and
internal 55 V clamps.
pn38, DWn51E
MC33298
Integral Alternator
Regulator
Control device used in conjunction with a Darlington device to monitor
and control the field current in alternator charging systems. "Bumped"
die for inverted mounting to substrate.
Dn51A, Flip-Chip
MC33095
MCCF33095
Peripheral Clamping
Array
Protects up to six MPU I/O lines against voltage transients.
"/626, Dn51
TCF6000
Automotive Direction
Indicator
Detects defective lamps and protects against overvoltage in
automotive turn-signal applications. Replaces UAA1041 B in most
applications.
Dn51 , P/626
MC33193
Automotive Wash Wiper
Timer
Standard wiper timer control device that drives a wiper motor relay and
can perform the intermittent, afterwash and continuous wiper timer
functions.
Dn51 , P/626
MC33197A
Automotive ISO 9141
Serial Link Driver
Interface between the two-wire asynchronous serial communication
interface (SCI) of a microcontrolier and a special one-wire care
diagnosis system (DIA).
Dn51 A
MC33199
"No Suffix
MOTOROLA ANALOG IC DEVICE DATA
10-3
Quad Fuel Injector Driver
MC33293AT, MC33293ATV
TJ
=-40° to +150°C, Case 8210, C
The MC33293AT is a monolithic quad low-side switching
device having CMOS logic, bipolar! CMOS analog circuitry,
and OMOS power FETs. All inputs are CMOS compatible.
Each independent output is internally clamped to 65 V, current
limited to ~ 3.0 A, and has an rOS(on) of S 0.25 n with VPWR
~ 9.0 V and may be paralleled to lower rOS(on). Fault output
reports existence of open loads (outputs "On" or "Off"),
shorted loads, and over temperature condition of outputs. A
shorted load condition will shut off only the specific output
involved while allowing other outputs to operate normally. An
overvoHage condition will shut off all outputs for the
overvoHage duration. A single/dual mode select pin allows
either independent input/output operation or paired output
operation.
3 (Input 1) Q-i--'-H
4 (Input 2) D-l.........-I
I-"-,.-t.......-t-'-O 2 (Outpull)
I
,l
I
I
13(lnput3) O-;.......~
ro 1
I
{-o 14
12 (Input 4) D-l---1t-1
(Output 2)
I
I
ro 15
5 (Input 1 + 2) (}-J'--t-!
.
(Output 3)
(Output 4)
6 (Single/Dual Select) D-lf--t-!
11 (Input 3 + 4) ~II--t-l
I
I
8 (Ground)
10 (Fault) o - r - - - - - - q
L.;-",""""±",,,!-<~
I
I
Fmm~~;a,41
L
___."':" ___ ~ ___"':":":' __ ":"_':":,"-_,-,-..:.. _________
..;.._J
EIICQder,'
10-4
.
".
<,
MOTOROLA ANALOG IC DEVICE DATA
Octal Serial Switch
MC33298P, MC33298DW
TJ= -40° to +150°C. Case 738. 751E
The MC33298 is a monolithic eight output low-side switch
with 8-bit serial input control. Incorporates CMOS logic.
bipolar/CMOS analog circuitry. and OMOS power FETs. All
inputs are CMOS compatible. It is designed to interface to a
microcontroller and switch inductive or incandescent loads.
Each independent output is internally clamped to 55 V. current
limited to <;: 3.0 A. and has an rOS(on) of s 0.45 n with VPWR
<;: 9.0 V. This device has low standby current. cascadable fault
status reporting. output diagnostics. and shutdown for each
output.
17 (VPWR)
Ir"""'-~'-----~-'-""""--~~--~
I
14 (VOO)
0-1-'---'"
-r:-_-oo!
l.._ _ _
;:;;:;;~::~=:jj' "j-O 10 (Output 4)
18(SFPO)~~~-h~1i
~,
+-0 9 (Output 5)
2 (Output 6)
1 (Output 7)
8(CSB)o-r~1t_~
3 (SCLK)o-MIi'--~""'"!""
4 (SI)
...~--o
5 (Ground)
6 (Ground)
15 (Ground)
16 (Ground)
7 (SO)o-If--"....,;;;~
MOTOROLA ANALOG Ie DEVICE DATA
10-5
Dual High-Side Switch
MC33143DW
TA= -400 to+125°C, Case 751E
The MC33143 is a dual high-side switch designed for
solenoid control in harsh automotive applications, but is well
suited for other environmeri!s. The device can also be used to
control small motors and relays ~s well as solenoids. The
MC33143 incorporates SMARTMOSTM technology, with
CMOS logic, bipolar/MOS analog circuitry, and DMOS power
outputs. An internal charge pump is incorporated for efficient
gate enhancement of the internal high-side power output
devices. The outputs are designed to provide current to low
impedance solenoids. The MC33143 provides individual
output fault status reporting along with internal Overcurrent
and Over Temperature protection. The device also has
Overvoltage protection, with automatic recovery, which
"globally" disables both outputs for the duration of an
Overvoltage condition. Each output has individual
Overcurrent and Over Temperature shutdown with automatic
retry recovery. Outputs are enabled with a CMOS logic high
signal applied to an input to providing true logic control. The
outputs, when turned on, provide full supply (battery) voltage
across the solenoid coil.
The MC33143 is packaged in an economical 24 pin surface
mount power package and specified over an operating voltage.
of 5.5 V ~ VPwr < 26 V for-40°C ~ TA ~ 125°C.
• Designed to Operate Over Wide Supply Voltages of 5.5 V
t026V
.
• Dual High-8ide Outputs Clamped to -10 V for Driving
Inductive Loads
• Internal Charge Pump fbr Enhanced Gate Drive
• Interfaces Directly to a Microcontroller with Parallel Input
Control
• Outputs Current Limited to 3.0 A to 6.0 A for Driving
Incandescent Loads
• Chip Enable "Sleep Mode" for Power Conservation
• Individual Output Status Reporting
• Fault Interrupt Output for System Interrupt Use
• Output ON or OFF Open Load Detection
• Overvoltage Detection and Shutdown
• Output Over Temperature Detection and Shutdown with
Automatic Retry
• Sustained Current Limit or Immediate Overcurrent
Shutdown Output Modes
• Output Short to Ground Detection and Shutdown with
Automatic Retry
• Output Short to VPwr Detection
Simplified Internal Block Diagram
VPwT(9,16)
SFPO(14)
INl (1)
Ourl (24)
I----.. . . --.. . .
~--+O STAT1 (3)
VOO(ll)
GTST (15) O+-~+;I!---~Iof;
CEN(2)
IN2(12)
Gnd (5) (500 Noto)
I
f
INT(23)
f .
cfi
f' • <
f _ •
l -,
L_~
NOTE:
10-6
'--....
-!j-oO......+-o OUT2 (13)
'".
___
__
• OvorTomperature
~
1-_ _ _ _- - -...............-0
«
VPwTOvorvoltago
____
_ _' _ _ _ _• _
____________
~
~
__
I
STAT2 (10)
~
Pins 5, 6, 7, 8, 17, 18, 19 and 20 should all be grounded so as to provide electrical as well as thermal heatsinking olthe device.
MOTOROLA ANALOG IC DEVICE DATA
Low Side Protected Switch
MC3392T, T-1,
ow
TJ = -40° to +150°C,
Case 221A, 314D, 751G
Single low side protected switch with fault reporting
capability. Input is CMOS compatible. Output is short circuit
protected to 1.0 A minimum with a unique current fold-back
feature. Device has internal output clamp for driving inductive
loads with overcurrent, overvoltage, and thermal protection.
When driving a moderate load, the MC3392 performs as an
extremely high gain, low saturation Darlington transistor
having a CMOS input characteristic with added protection
features. In some applications, the three terminal version can
replace industry standard TIP100/101 NPN power Darlington
transistors.
Ir------------------------------------~
..
.
I
I
--
~
·1
Turnoff
Vou!
1
Overvoltage
Detect
I
'j
~
I
1
~
: 550 V is used.
MOTOROLA ANALOG IC DEVICE DATA
10-15
MC3334 MCC3334 MCCF3334
ELECTRICAL CHARACTERISTICS (TA = -40° to +125°C, Vbat = 13.2 Vdc, circuit 01 Figure 1, unless otherwise noted.)
Symbol
Characteristics
Internal Supply VoHage, Pin 6
Vbat = 4.0 Vdc
8.0Vdc
12.0
14.0
VCC
Ignition Coil Current Peak, Cranking RPM 2.0 Hz to 27 Hz
Vbat = 4.0 Vdc
6.0
8.0
10.0
lo(pk)
Ignition Coil Current Peak, Normal RPM
Frequency = 33 Hz
133Hz
200Hz
267Hz
333Hz
lo(pk)
Ignition Coil On-Tlme, Normal RPM Range
Frequency = 33 Hz
133Hz
200Hz
267Hz
333Hz
Typ
-
-
3.5
7.2
10.4
11.8
3.0
4.0
4.6
5.1
3.4
5.2
5.3
5.4
-
5.1
5.1
4.2
3.4
2.7
5.5
5.5
5.4
4.4
3.4
-
-
-
-
7.5
5.0
4.0
3.0
2.3
14.0
5.9
4.6
3.6
2.8
25
30
35
Max
Vbat
VS~VS1
-
-
Apk
Input Threshold Hysteresis
VS~VS1
Vdc
mVdc
-
360
90
-
75
-
-
-
1.8
1.5
-
Total Circuit Lag from ts (Figure 1) until Ignition Coil Current Falls to 10%
-
60
120
Ignition Coil Current Fall Tlme (90% to 10%)
-
4.0
-
mVdc
Vdc
VS2
Saturation Voltage IC Output (Pin 7) (RDRIVE = 100 0)
Vbat= 10 Vdc
30Vdc
50Vdc
Vdc
-
ms
Input Threshold (Static Test)
Turn-on
Turn-off
Input Threshold (Active Operation)
Turn-on
Turn-off
Unit
Apk
ton
Shutdown VoHage
Min
~s
~s
mVdc
VCE(sat)
Current Limit Reference, Pin 8
Vrel
-
-
120
280
540
-
-
120
160
190
mVdc
Figure 2. Ignition Coil Current versus Frequency/Period
Vb.t = 13.2 Vile
6.0
Vbat- 1.5V
Slope =-a:Diiiii
5.5
g
5.0
4.0
_°3.0
2.0
1.0
I
I
33
50
I
15
f, FREQUENCY (Hz)
10-16
I
20
I
I I
25
30
ms
MOTOROLA ANALOG IC DEVICE DATA
MC3334 MCC3334 MCCF3334
CIRCUIT DESCRIPTION
The MC3334 high energy ignition circuit was designed to
serve aftermarket Delco five-terminal ignition applications.
This device, driving a high voltage Darlington transistor, offers
an ignition system which optimizes spark energy at minimum
power dissipation. The IC is pinned-out to permit thick film or
printed circuit module design without any crossovers.
The basic function of an ignition circuit is to permit build-up
of current in the primary of a spark coil, and then to interrupt
the flow at the proper firing time. The resulting flyback action
in the ignition coil induces the required high secondary
voltage needed for the spark. In the Simplest systems, fixed
dwell angle produces a fixed duty cycle, which can result in
too little stored energy at high RPM, and/or wasted power at
low RPM. The MC3334 uses a variable DC voltage
reference, stored on CDwell, and buffered to the bottom end of
the reluctor pickup (S 1) to vary the duty cycle at the spark
coil. At high RPM, the MC3334 holds the output "off' for
approximately 1.0 ms to permit full energy discharge from the
previous spark; then it switches the output Darlington
transistor into full saturation. The current ramps up at a slope
dictated by Vbat and the coil L. At very high RPM the peak
current may be less than desired, but it is limited by the
coil itself.
As the RPM decreases, the ignition coil current builds up
and would be limited only by series resistance losses. The
MC3334 provides adjustable peak current regulation sensed
by RS and set by RD1, in this case at 5.5 A, as shown in
Figure 2. As the RPM decreases further, the coil current is
held at 5.5 A for a short period. This provides a reserve for
sudden acceleration, when discharge may suddenly occur
earlier than expected. The peak hold period is about 20% at
medium RPM, decreaSing to about 10% at very low RPM.
(Note: 333 Hz = 5000 RPM for an eight cylinder four stroke
engine.) At lower Vbat, the "on" period automatically stretches
to accommodate the slower current build-up. At very low Vbat
and low RPM, a common condition during cold starting, the
"on" period is nearly the full cycle to permit as much coil
current as possible.
The output stage of the IC is deSigned with an OVP circuit
which turns it on at Vbat ~ 30 V (VCC ~ 22 V), holding the
output Darlington off. This protects the IC and the Darlington
from damage due to load dump or other causes of
excessive Vbat.
Component Values
Pickup
series resistance = 800 Q ± 10% @ 25°C
inductance = 1.35 H @ 1.0 kHz @ 15 Vrms
Coil
leakage L = 0.6 mH
primary R = 0.43 Q ± 5% @ 25°C
primary L = 7.5 mH to 8.5 mH @ 5.0 A
RL
RA, RB
load resistor for pickup = 10 kQ ± 20%
-
input buffer resistors provide additional
transient protection to the already clamped
inputs = 20 k ± 20%
MOTOROLA ANALOG IC DEVICE DATA
C1, C2
-
for reduction of high frequency noise and
spark transients induced in pick-up and
leads; optional and non-critical
-
provides load dump protection (but small
enough to allow operation at Vbat = 4.0 V)
=300Q± 20%
transient filter on VCC, non--critical
CFilter
-
CDwell
-
stores reference, circuit designed for 0.1 IlF
±20%
RGain/RD1 sets the DC gain of the current
regulator = 5.0 k ± 20%
RGain
-
RD2/RD1 set up voltage feedback from RS
sense resistor (PdAg in thick film techniques)
= 0.075 Q ± 30%
low enough to supply drive to the output
Darlington, high enough to keep VCE(sat) of
the IC below Darlington turn-on during load
dump = 100 Q ± 20%, 5.0 W
RDrive
-
starting with 35 Q assures less than 5.5 A,
increasing as required to set 5.5 A
RD1 = IO(pk) RS-Vref - (~100 Q)
Vref_~
RD2
RGain
General Layout Notes
The major concern in the substrate design should be to
reduce ground resistance problems. The first area of concern
is the metallization resistance in the power ground to module
ground and the output to the Rdrive resistor. This resistance
directly adds to the VCE(sat) of the IC power device and if not
minimized could cause failure in load dump. The second
concern is to reference the sense ground as close to the
ground end of the sense resistor as possible in order to
further remove the sensitivity of ignition coil current to ground
I.A. drops.
All versions were deSigned to provide the same pin-out
order viewed from the top (component side) of the board or
substrate. This was done to eliminate conductor
cross-overs. The standard MC3334 plastic device is
numbered in the industry convention, counter--clockwise
viewed from the top, or bonding pad side. The MCCF3334
"flip" or "bump" chip is made from reversed artwork, so it is
numbered clockwise viewed from its bump side. Since this
chip is mounted face down, the resulting assembly still has
the same counter--clockwise order viewed from above the
component surface. All chips have the same size and
bonding pad spacing. See Figure 4 for dimensions.
10-17
MC3334 MCC3334 MCCF3334
Figure 3. Internal Schematic
6
r-----------~--'r
5
Vee
--------'r------------,
I
I
I
I
I
I
II
II
II
II
II
82 1
I
I
I
I
I
I
I
I
I
I
I
I
I
4vI
I
I
I
I
I
I
I
I
I
r+--+--HM
Input
::,parator
Hysteresis .
Output
Stage
with OVP
and
Current
Umiting
r----------,
Vee
I
I
I
S1
I---<___~
e
I
L~
Dwell
Reference
Buffer
II
;.,:':::: - - - -"J--;;.; J
Ground
Ground
I
I
I
I
I
I
I
I
I
I
I
_ _ _ ~L _ _ ~ _ _ _ ~_ _ _ ~
Figure 4. MCCF3334 Ignition Circuit Bump Side View
T
66
12
Mils 50
Mils
'I
I
.
1
, 1
(8) Bumps 7 ± 1 Mil Dia.
raised minimum 0.5 Mils
above pass~atad chip surface
1
10-18
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC3392
Low Side Protected Switch
The MC3392 is a low side protected switch designed for use in harsh
automotive applications which require the capability of handling high
voltages attributed to load and field dump transients, in addition to reverse
and double battery conditions. The three terminal TQ-220 is intended to
replace power Darlington transistors in new and existing switching
applications when taking into account the CMOS input levels required by the
MC3392. It offers improved functionality and ruggedness over power
Darlingtons while retaining the same package and pin configuration, and can
be used as a replacement in many applications using the industry standard
TIP100/101 NPN power Darlington transistor.
The five-terminal TQ-220 has the added feature of having a Fault output
(active low) which will indicate the existence of an over temperature,
over-voltage or current limit condition, including an output short to ground.
When driving a moderate load, the MC3392 performs as an extremely
high gain,low saturation Darlington transistor having CMOS input levels. The
primary advantage of the MC3392 over a Darlington transistor is the
additional protection afforded the device and load when driving difficult or
faulty loads. This device incorporates unique internal current limit and
thermal protection circuitry to safeguard itself and the associated load from
catastrophic failure.
The MC3392 is available in a three and five-lead TQ-220 package; the
five-lead having the added diagnostic feature. The full featured MC3392 is
also available in a 16 pin wide body SOIC plastic power package.
• DeSigned for Automotive Applications
LOW SIDE
PROTECTED SWITCH
SEMICONDUCTOR
TECHNICAL DATA
Pin 1. Input
2. Output
3. Ground
(Heatsink surface
connected to Pin 3)
TSUFFIX
PLASTIC PACKAGE
CASE 221A
(T0-220)
• Can Be Used as a Replacement for TIP100/101 NPN Power Darlingtons
• Drives Inductive Loads without External Clamp Circuitry
• Withstands Negative and Positive Transient Voltages
• Low ON Voltage
• CMOS Logic Compatible Input
• Over Current, Overvoltage, and Thermal Protection
T-1 SUFFIX
PLASTIC PACKAGE
CASE 3140
(T0-220)
• Extended Operating Temperature Range
• Fault Output
Pin 1.
2.
3.
4.
5.
Pin 1.
2.
3.
4.
Simplified Block Diagram
5.
I---t--..------
250
I.....~--_
.. I...--.~I__!
g>
~.~
g:::i
-g(ij
E
::::;
'E
.3Q. ~
~ ~
:;;E
.s~
'E
§
"C
<:
0
)en
::I
~
200
li~
150
z
0
0
t::>
0~
c
100
o
o
10-22
If/I
0
2.0
3.0
Vin, INPUT VOLTAGE (V)
3.0
2.5
w
2.0
«
w
1.5
t::>
0t::>
0
1.0
~
...J
~V
1.0
3.5
::>
VI
50
t-
w
a:
a:
lin
TA=-40°C
...J
«::l.
Z
~
0
~
t-
Figure 4. Output Leakage Current
versus Temperature
.--
TA = 1~5°C
lin
TA = 25°C
I
I
E
Figure 3. Input Control Current
versus Input Voltage
~
I
I
Irl--~In:I
lrTU
I I
I I I
..I • .. I--J
"C
~j ...J~
C,.)
!:::
1.4
(3
1.3
~
en
1.2
~
~
1.1
.Ql
1.0
-50
~
Ii:
o
~
./
/
(!)
~
/
~
1.2
~
1.1
~
V
./
~
+VS= 14V
RL=O
o
50
100
TA, OPERATING AMBIENT TEMPERATURE (0G)
1.3
w
~
1.0
~
0.9
0.8
-50
150
- ---
4.0
~
~
3.0
[l.
::;;
(!)
:5
C,.)
VIH ' "
2.0
l-
VIL .JF
~
~
0
-50
~ -93
w
~ -94
~
~ -95
W
cc
'"~
-96
-97
~
cc -98
~
> -99
-50
,
/
72
71
/'
=>
~ 70
~
C,.)
69
50
100
68
-50
150
"
10= 100 mA
/
/
~
1
(!)
",«8
+VS =5.0V-
o
/
73
[l.
[l.
1.0
150
~
(!)
::t:
~
--'
:>
10=400 mA
~
w 74
\2
~
Vin 1'4.0 V
75
~
~
10 = 800 mA
Figure 8. Output Clamp Voltage
versus Temperature
~ 5.0
~
/
o
50
100
TA, OPERATING AMBIENT TEMPERATURE (OC)
Figure 7. Input Voltage
versus Temperature
~
~.
o
50
100
150
TA, OPERATING AMBIENT TEMPERATURE (0G)
TA, OPERATING AMBIENT TEMPERATURE (OC)
Figure 9. Reverse Breakdown Voltage
versus Temperature
Figure 10. Fault Output Saturation
versus Sink Current
2.5
Transient Breakdown
Pulse Width = 1.0 ms
Vin = 5.0 V Vin = 5.0 V Vin = 5.0 V
TA=125°C TA=25°C TA=-40°C
~
z 2.0
~
Q
~
'\
=>
!;;: 1.5
"
'--
en
=>
l[l.
l-
1.0
=>
o.
10=20mA
o
50
100
TA, OPERATING AMBIENT TEMPERATURE (0G)
MOTOROLA ANALOG IC DEVICE DATA
j 0.51---~~"'-;&"'""'-+---1----+---I
~
>
150
O~~__~____~____~____~____~____~
o
2.0
4.0
6.0
8.0
ISink, SINK CURRENT (mA)
10
12
10-23
MC3392
Figure 11. Turn-On Waveform
Figure 12. Turn-Off Waveform
10
Vout
Figure 13. Output Current versus
Supply Voltage
1.5
5: 1.25
!z
~
gs
1.0
(,)
~ 0.75
o
2
7
I
0.5
o
o
0.5
~
~
10
Vin= 4.0V
RL=O
TA=25°C -
\
;g
l'z::
0.4
~Heatsink
~
0.3
~'
9
i::!:
'"
Infintte
0.25
Figure 14. Maximum Load Inductance
versus Output Current
Heatsi~
"\.
20
30
40
+Vs, SUPPLY VOLTAGE (V)
~
''-....,.
50
60
~
~
'1
\
I
External Clamp Needed
0.2
~ 0.1 -
Emax =60 mJ
"'" -- --
Safj operatin, Region
0
0.2
0.4
0.6
....
r--
0.8
1.0
1.2
10, OUTPUT CURRENT (A)
1.4
1.6
TECHNICAL DISCUSSION
Introduction
The MC3392 is a low side protected switch incorporating
many features making it ideal for use in harsh automotive
applications. The protection circuitry of the MC3392 protects
not only itself but also the associated load from destructive
voltage transients attributed to load and field dump, as well as
reverse and double battery conditions found in automotive
applications. The MC3392 is unique in that the protection
circuitry is Internal and does not require additional external
protection components for its operation. This makes the
device very cost effective because its application utilizes few
external components, thus reducing cost and space
requirements needed for the system. The MC3392 is
extremely effective when used to drive solenoids, as well as
incandescent lamp loads. The following description of the
device's operation is in reference to the functional blocks of
the Representative Block Diagram shown in Figure 1.
10-24
CMOS Input
The input of the MC3392 is CMOS compatible. Input
control performs as true logic. When the input (Vin) is less
than 1.0 V the MC3392 switch is in a high impedance or OFF
state. When Yin is greater than 4.0 V, is in a low impedance or
ON state. The switching threshold of the input is
approximately 2.0 Vand is graphed in Figure 7. With the input
at 4.0 V, the input sink current will be approximately 250 !lA.
In the ON state, the internal protection circuitry is activated
and all of the protection features are available for use. In the
OFF state, however, it is important to note that none of the
protection features are available, with the exception of the
internal inductive load clamp. The input pin is afforded a
minimum of 2000 V ESD protection (Human Body Model) by
virtue of the 7.2 V zener diode.
MOTOROLA ANALOG IC DEVICE DATA
MC3392
Over Temperature Shutdown
Internal Thermal Shutdown Circuitry is provided to protect
the MC3392 in the event the Operating Junction Temperature
(TJ) exceeds 150°C. Typically, Thermal Shutdown will occur
at 160° to 170°C. The thermal shutdown sense element is
embedded within the output PNP (04) in order to afford very
fast thermal coupling of 04 to the sense element. Any rise in
temperature due to the ambient is translated directly to 04
and the sense element. If the junction temperature rises
excessively above 150°C, the Thermal Shutdown circuit will
turn ON, quickly pulling the gate of 02 to ground, which pulls
the base of Q4 to ground, turning it OFF. In addition, the
Thermal Shutdown circuit simultaneously turns 05 ON and
with a suitable pull-up resistor at the Fault pin reports the
presence of a fault (logic low). The output PNP will remain
OFF until the junction temperature decreases to within the
operating range at which time Thermal Shutdown turns OFF,
ceasing to hold the gate of 02 low, turning 04 back ON. This
process will repeat as long as the thermal over load exists.
This mode of operation is a nondestructive safety feature of
the device and will correct itself real time when the cause of
over temperature is removed. A continued over temperature
condition will thermally Pulse Width Modulate (PWM) the
output and Fault and may be incorrectly interpreted as an
oscillating load if one does not consider the simultaneous
performance of the Fault pin.
Current Limit
The MC3392 protects itself against Vout to +VS hard
shorts as well as any over current conditions by reducing the
magnitude of output current (10) to that of the short circuit
current limit value (ISC). When the output current monitored
by 03 tries to exceed ISC, the Current Limit circuit lowers the
gate voltage of 02, lowering the base of 04, causing the load
current through 04 to diminish. Simultaneously, when the
load current exceeds ISC, 05 will turn ON reporting a fault
condition. If the output current is allowed to remain
excessively high for the degree of heatsinking incorporated,
and the junction temperature of the device is allowed to heat
beyond 150°C, the Thermal Shutdown circuit will activate and
the output will thermally PWM. Again, these modes of
operation are safety features of the MC3392 and are not
destructive.
Overvoltage Detect
This circuitry protects the MC3392 from Vout voltages in
excess of 16 V by lowering the output current to a
nondestructive value. With increasing Vout voltage (16 V <
Vout < 45 V) the load current is reduced to below that of ISC
and produces a fold back current effect. As Vout increases in
excess of 16 V, the output current decreases linearly until
Vout exceeds 45 V. With an infinite heatsink and YOu! > 45 V,
10 will be less than 100 mAo For the other extreme, no
heatsink and Vout > 45 V, 10 can be expected to be less than
about 400 mAo This behavior of 10 in relation to Vout is shown
in Figure 13.
MOTOROLA ANALOG IC DEVICE DATA
For the infinite heatsink case, the output current initially
increases with increased voltage until Vout exceeds 16 V,
thereafter the behavior is expressed as,
10
=ISC [1-(Vout -16 V) 130 Vj
Beyond 45 V, 10 is limited to less than 100 mA. Anytime the
Overvoltage Detect circuit is activated, the gate of 05 is
pulled low causing 05 to turn ON to report the fault at the
Fault pin.
Inductive Load Clamp
The MC3392 has an internal inductive load clamp for
protection against flyback voltages imposed on the output pin
in excess of 70 V. The incorporated zener clamp can quickly
dissipate up to 60 milli-Joules of inductive flyback energy.
Figure 14 shows the maximum inductive load versus load
current that the clamp can handle safely. As an example
(using Figure 14), if operating the MC3392 to drive a 0.33 H
inductor, the maximum load current should be adjusted to
600 mA or less. If the load current is too high for the inductor
used, some series resistance can be added to the load to limit
the current. If this is not pOSSible, an external clamp must be
used to facilitate handling the higher energy. When using an
external clamp, the external clamp voltage must be less than
60 V so as to override the internal clamp. The output clamp
offers protection for the output when the MC3392 is in the
OFF state. During the ON state, other protection features
(Overvollage, Current, and Temperature) are available to
protect the output.
Fault Logic
The Fault is comprised of an internal open drain FET
requiring an external pull-up resistor. Typically, a 5.0 k
pull-up resistor to a +5.0 V supply is satisfactory. The Fault
pin is afforded a minimum of 2000 V ESD protection (Human
Body Model) by virtue of the 7.2 V zener diode. The Fault will
report a fault (logic low state) whenever the MC3392
experiences a fault condition. Conditions producing a fault
are: 10 > 1.3 A (over current/shorted load); TJ > 150°C (over
temperature); and Vout > 16 V (overvoltage).
If the device goes into Thermal Shutdown, caused by
environmental overheating (not resulting from another fault
condition), the Fault and Vout will thermally PWM as the
MC3392 repeatedly heats to shut off, cools, and again turns
on. If a current limit fault causes the device to go into Thermal
Shutdown, the output will oscillate while the Fault remains
pulled low. There is no thermal hysteresis designed in to
control the PWM effect and this fault mode of operation is not
destructive.
Fast Turn-Off
This circuitry enhances the MC3392 turn-off performance.
Whenever Vin goes to a logic low state, Vout is held in an OFF
state for approximately 15 liS. During fast turn-off, less than
30 mA of current is allowed 10 flow producing an abrupt
turn-off. This turn-off characteristic can be seen in Figure 12,
a photograph of the typical turn-off waveform.
10-25
MC3392
APPLICATIONS INFORMATION
Solenoid Driver
The MC3392 can be used to drive a variety of solenoid
applications similar to that of Figure 15. For example; driving
a solenoid having an inductance of 73.8 mH and a resistance
of 95 from a 12 V supply will cause 240 mA of sink current
to flow with the MC3392 in the ON state. The resulting current
value is within the normal load current operating region and
will not produce a fault. Load current is paramount in any
design using the MC3392 and must be less than ISC for
acceptable operation. If the load current is greater than ISC, a
current limit fault state will exist. Operation in this state is not
destructive as the device will turn off if the Junction
Temperature (TJ) rises above 150°C. When the Junction
Temperature cools below 150°C the device will again
turn-on, with a repeat of the cycle. Careful design to
acceptable load current limits should be insured for
satisfactory operation of an application.
n
Figure 15. Solenoid Driver
Oft
1-
VinIcM;:p;- -
I - -=
II
I
II MC3392
..L
+
5.0V
-=
-F:- -
-
-
-
-
-
-
-,
Turnoff
Vout
Solenoid
Over
Voltage
Detect
IFault
L_J1 _________ ~...::.__.J
+
-=- 5.0V
-t
Gnd~-
10-26
MOTOROLA ANALOG IC DEVICE DATA
MC3392
Instrument Panel Lamp Dimmer Control
The MC3392 can be used to control the dimming function
associated with instrument panel lamps. The brightness of
incandescent lamps can be varied by pulse width modulating
the input of the MC3392. The modulating signal for the
MC3392 can be obtained directly from a microprocessor or,
as in Figure 16, from an MC1455 timer. The MC1455 timer is
configured as a free-running clock having both frequency
and duty cycle control. The typical timer frequency is
approximately 80 Hz when the frequency potentiometer is
adjusted to 1.0 k. This frequency was chosen so as to avoid
any perceptible lamp flicker. The duty cycle potentiometer
controls the duty cycle over a range of approximately 3.0% to
97%; When at 3.0% duty cycle, the lamps are essentially off;
When at 97% duty cycle, the lamps are essentially full lit. Six
incandescent lamps are shown in this application drawing
720 mA total current. Similar applications can be used to
drive a variety of lamp loads. The total load current is the
primary factor of consideration when driving lamp loads. The
total value of 10 must be less than ISC.
Another convenient aspect of this application is the LED.
The LED can be used to denote the existence of a system
fault (overvoltage, current limiting, or thermal shutdown).
Figure 16. Instrument Panel Lamp Dimmer Control
+
-=-
J
MC1455
5.0V
Frequency
I
I
I
I
I
I
I
Instrument
Panel Lamps
+
-=-
L_I1-_
Gnd
r
MOTOROLA ANALOG IC DEVICE DATA
1
5.0V
10-27
®
ItIIOTOROLA
MC3399
Automotive Half-Amp
High-Side Switch
The MC3399 is a High-Side Switch designed to drive loads from the
positive side of the power supply. The output is controlled by a TIL
compatible input Enable pin. In the "on" state, the device exhibits very low
saturation voltages for load currents in excess of 750 mAo The device
isolates the load from positive or negative going high voltage transients by
abruptly "opening" thus protecting the load from the transient voltage for the
duration of the transient. The device automatically re-establishes its original
operating state following the transient condition.
The MC3399 is fabricated on a power BIMOS process which combines
the best features of Bipolar and MOS technologies. The mixed technology
provides higher gain PNP output devices and results in Power Integrated
Circuits having substantially reduced quiescent currents.
The device operates over a wide power supply voltage range and can
withstand voltage transients (positive or negative) of ±1 00 V. A rugged PNP
output stage along with active clamp circuitry, output current limit and
thermal shutdown permit the driving of all types of loads, including inductive.
The MC3399 is offered in 5-lead T0-220 and 16-lead SOIC plastic
packages to facilitate either "thru-hole" or surface mount use. In addition, it
is specified over a wide ambient operating temperature of -40°C to +125°C
and is ideally suited for industrial and automotive applications where harsh
environments exist.
AUTOMOTIVE
HALF-AMP HIGH-SIDE
SWITCH
SEMICONDUCTOR
TECHNICAL DATA
TSUFFIX
PLASTIC PACKAGE
CASE 3140
Pin I.
2.
3.
4.
5.
Ignition
Output
Output
Ground
Input
• Low Switch Voltage Drop
• Load Currents in Excess of 750 mA
• Low Quiescent Current
Pins 2 and 3 connected to package tab.
• Transient Protection Up to ± 100 V
• TIL Compatible Enable Input
• On-Chip Current Limit and Thermal Shutdown Circuitry
Pin I. Ignition
2. N.C.
3. N.C.
4. N.C.
Representative Block Diagram
OW SUFFIX
PLASTIC PACKAGE
CASE 751G
SOP(8+8)L
MC3399T
5. Ground
6. N.C.
7. Input
8. N.C.
9. Output
IO.Output
II. Output
12.0utput
13.0utput
14.0utput
15.0utput
16.0utput
ORDERING INFORMATION
Device
MC33990W
This device contains 52 active transistors.
10-28
MC3399T
Operating
Temperature Range
Package
SOP(8+8)L
TA = - 40° to +125°C
Plastic Power
MOTOROLA ANALOG IC DEVICE DATA
MC3399
MAXIMUM RATINGS
Rating
Symbol
Ignition Input Voltage (Continuous)
Forward
Reverse
VIGN
Ignition Input Voltage (Transient)
VIGN
Value
Unit
Vdc
25
-16
V
±60
±100
Input Voltage
Yin
-0.3 to +7.0
V
Output Current
10
Internally
Limited
A
°CIW
Thermal Resistance
Plastic Power Package (Case 314D)
Junction-te-Ambient
Junction-te-Tab
SOP(8+8)L Plastic Package (Case 751G)
Junction-to--Ambient
Junction-to-Lead 12
RWAl
ReJT
65
5.0
ReJA2
RWL
138
52
Soldering Temperature (for 10 Seconds)
Tsolder
260
°C
Junction Temperature
TJ
-40 to +150
°C
Storage Temperature
Tstg
-65 to +150
°C
ELECTRICAL CHARACTERISTICS (VIGN = 12 V, IL = 150 mA, -4Q°C '" TA = +125°C, V Input = "1", unless otherwise noted.)(l)
Symbol
Min
Typ
Max
Unit
Operating Voltage
VIGN(min)
4.5
-
-
V
Switch Voltage Drop (Saturation)
VIGN = 4.5 V 10 = 150 mA, TA = 25°C
10 = 200 mA, TA = -40°C
10 = 125 mA, TA = 125°C
VIGN = 12 V 10 = 425 mA, TA = 25°C
10 = 550 mA, TA = -40°C
VIGN = 16 V 10 = 375 mA, TA = 125°C
VIGN-VO
-
-
0.2
0.3
0.3
0.3
0.3
0.4
0.5
0.5
0.5
0.7
0.7
0.7
Quiescent Current
VIGN= 12V 10= 150 mA,TA= 25°C
10 = 550 mA, TA = -40°C
10 = 300 mA, TA = 125°C
IGND
-
12
25
10
50
100
50
Characteristic
V
mA
ISC
-
1.6
2.5
A
ILeak
-
10
150
llA
Input Voltage
High Logic State
Low Logic State
-
V
VIH
VIL
2.0
-
Input Current
High Logic State (VIH = 5.5 V)
Low Logic State (VIL = 0.4 V)
IIH
IlL
Output Current Limit (VO = 0 V)
Output Leakage Current (VIGN = 12 V, Input = "0")
-
-
0.8
!1A
120
20
-
50
-
!1S
5.0
-
!1S
-
Output Turn-On Delay Time
Input = "0" - "1", TA = +25°C (Figures 1 and 3)
tDLY(on)
-
Output Turn-Off Delay Time
Input = "1" - "0", TA = +25°C (Figures 1 and 3)
tDLY(off)
-
Overvoltage Shutdown Threshold
Vin(OV)
26
31
36
V
tDLY
-
2.0
-
lls
tRCVY
-
5.0
-
!1S
Output Turn-Off Delay Time (TA = + 25°C) to Overvoltage Condition,
Yin stepped from 12 V to 40 V, V", 0.9 Vo (Figures 1 and 3)
Output Recovery Delay Time (TA = + 25°C)
VIGN stepped from 40 V to 12 V, V", 0.9 Vo (Figures 1 and 3)
NOTES: 1. Typical values represent characteristics of operation at TA = 25°C.
MOTOROLA ANALOG IC DEVICE DATA
10-29
MC3399
Figure 1. Transient Response Test Circuit
50Q
NOTE:
• Depending on load current and transient duration, an oulput capacitor
(Col of sufficient value may be used to hold up output voltage during the
transient, and absorb tum-off delay vonage overshoot.
Figure 2. Timing Diagram
100V -
Figure 3. Response Time Diagram
Line Transient
n
4OV-
31 VIgnition
12V -
12V-
I
ov -.......J
-100 V -
Input
I
5.0V-
1.0ms
OV31V-
•
5.0V~
1
OV-
Output
Vo 12V-
Input
a
OV-
-.j
tDLY(OV)
Figure 4. Switch Voltage Drop
versus Load Current
800
I
Zw
0'"
~ ~
400
..,/
(!)C
-. w
o~
!j 200
./
::rzo
£1>
>
V
o
o
,
I>-
II
VIGN=24V _ I - TA = 25°C
Vin="I'
r--
-
60
40
~
U
--
en
w
5
...".. ~
20
0
_0
~
200
400
600
800
tDLY(onl
z
w
'"u'":::>
/~
",
IL' LOAD CURRENT (rnA)
lo:-aO
80
I
t:::;
f2~
toLT(off)
Figure 5. Quiescent Current
versus Load Current
VIGN=24V _ I--TA = 25°C
Vin="I'
-
!5c..>
!5
5- 600
0«
tRCVY
1000
o
o
200
400
600
IL, LOAD CURRENT (rnA)
800
V
1000
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC33091A
High-Side TMOS Driver
The MC33091A is a High-Side TMOS Driver designed for use in harsh
automotive switching applications requiring the capability of handling high
voltages attributed to load and field dump transients, as well as reverse and
double battery conditions. Few external components are required to drive a
wide variety of N-Channel TMOS devices. The MC33091A, driving an
appropriate TMOS device, offers economical system solutions for high-side
switching large currents. The MC33091A has CMOS compatible input
control, charge pump to drive the TMOS power transistor, basic fault
detection circuit, VDS monitoring circuit used to detect a shorted TMOS load,
and overcurrent protection timer with associated current squaring circuitry.
Short circuit protection is made possible by having a unique VDS voltage
to current converter drive an externally programmable integrator circuit. This
circuit affords fast detection of a shorted load while allowing difficult loads,
such as lamps having high in-rush currents, additional time to turn on.
The Fault output is comprised of an open collector NPN transistor
requiring a single pull-up resistor for operation. A fault is reported whenever
the MOSFET on-current exceeds an externally programmed set level.
The MC33091A is available in the plastic 8-Pin DIP package as well as
the plastic a-Pin surface mount package.
HIGH-5IDE
TMOS DRIVER
SEMICONDUCTOR
TECHNICAL DATA
.~
1
PSUFFIX
PLASTIC PACKAGE
CASE 626
• Designed for Automotive High-Side Driver Applications
• Works with a Wide Variety of N-Channel Power MOSFETs
• Drives Inductive Loads with No External Clamp Circuitry Required
8~
• CMOS Logic Compatible Input Control
• On-Board Charge Pump with No External Components Required
• Shorted Load Detection and Protection
o SUFFIX
PLASTIC PACKAGE
CASE 751
(S0--8)
• Forward Overvoltage and Reverse Battery Protection
• Load and Field Dump Protection
• Extended Operating Temperature Range
• Fault Output to Report a MOSFET Overcurrent Condition
Simplified Block Diagram
RS
RX
1MC33091A--Input
2
DRN
1m
PIN CONNECTIONS
......--------_----+O+vs
cs~
---------
I
SRC
VT
DRN
Input
Gnd
Fault
Gate
VCC
(Top View)
6
I
I
ORDERING INFORMATION
Lsj:t-;;;j----a
-
R-r
This device contains 54 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
Device
MC33091AD
MC33091AP
Operating
Temperature Range
TA = - 40° to +125°C
Package
S0--8
Plastic DIP
11l-31
MC33091A
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage (PinS) (Note 1)
Continuous (Without Activating Clamp)
VCC
-0.7 to 28
7.0 to 28
V
Continuous Supply Clamp Current (Pin 5)
DIP Package (Case 626)
So-a Package (Case 751)
IC
Input Control Voltage Range (Pin 7)
Continuous
Vin
Fault Pull-Up Voltage Range (Pin 6)
Continuous
Vout
Minimum ESD Voltage Capability (Note 2)
ESD
2000
V
TJ
150
Tstg
-65 to +150
TA
-40 to +125
°c
°c
°c
Rating
mA
10
1.0
V
-0.7 to 28
V
-0.7 to 28
Operating Junction Temperature
Storage Temperature
Operating Ambient Temperature Range
Thermal Resistance, Junction-to-Ambient
DIP Package (Case 626)
So-a Package (Case 751)
°elW
RaJA
100
145
NOTES: 1. An internal zener diode is incorporated to protect the device from overvoltage transients in excess
of30V.
2. ESD testing performed in accordance with Human Body Model (C" 100 pF, R ~ 15000).
Figure 1. Typical Application
r-----------------~------------~+vs
RX=75k
RS=200
0.1:::r::
r--------2
DRN
-=- 5
I MC33091 A
I
,-----+-1
Input
'--------'
+5.0 V
9.1 k
10-32
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
ELECTRICAL CHARACTERISTICS (Values are noted under conditions of 7.0 V ,;; VCC ,;; 24 V, -40°C ,;; TA ,;; +125°C, unless otherwise
noted. Typical values reflect approximate mean at TA = 25°C at time of device characterization.)
Characteristics
Symbol
Min
Typ
Max
Unit
-
160
2.5
300
6.0
I1A
mA
Vz
29
-
35
V
VGS
8.0
12
15
Supply Current (Note 1)
Vin=OV
Vin = 5.0 V (RX = 100 k)
ICC
Supply Clamp Voltage (Note 2)
Gate-te-Source Voltage Range (Pin 4)
Gate Current (Pin 4)
VG=VCC
IG
V
ItA
30
-
VG(sat)
0
1.2
1.4
V
IGC
6.4
7.0
7.7
V
VIL
VIH
-
1.5
3.5
2.7
2.7
Input Control Current (Pin 7) (Vin = 5.0 V)
lin
-
100
250
limer Current Constant (Pin 8)
(RX = 100 k, VT = 0, VDS = 1.0 V) (Note 3)
K
Gate Saturation Voltage (lG = 10 ItA)
Short Circuit Gate Voltage (Note 4)
400
Input Control Threshold Voltage (Pin 7)
V
-
ItA
I1NV2
0.7
1.1
1.5
VTL
VTH
0.4
4.3
0.95
4.6
1.2
5.2
Fault Sink Current (Pin 6)
VF=5.0V
VF=O
IOL
IOH
500
-
-
-
2.0
100
I1A
nA
FauH Saturation Voltage (Pin 6) (IF = 500 ItA)
VOL
-
0.2
0.8
V
limer (Pin 8)
Lower Threshold Voltage
Upper Threshold VoHage
V
NOTES: 1. The total supply current into Pin 2 and Pin 5 with RX = lOOk (from Pin 2 to supply) and 45 k pull-up resistor from Pin 6 to supply.
2. An internal zener clamp is provided to protect the device from overvoltage transients on the supply line.
3. The timer current constant is the proportionality constant of the voltage to current converter used to monitor the VOS voltage developed across the
FET (from Pin 1 to the supply).
4. The gate vonage will be clamped at approximately 7.0 V above the source voltage whenever the source vonage is less than approximately 1.0 V
above ground.
Figure 2. Supply Current versus Supply Voltage
Figure 3. Operating Current versus Supply Voltage
600
<" 500
.=;.
i
6.0
Vin = 0 V (Gale "off')
VOS=2.0V
400
::J
(.) 300
~
"-
~ 200
6
.Y 100
o
6.0
-
---
./
-::;::::::::.
12
/
//
----
24
Vee, SUPPLY VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
::J
4.0
f------+---:;;;£...+-----t---::;.....=---i
(!)
z
~
a:
3.01----~~~f__----~~~------_I_--~~--_I
w
"-
°6
TA = 125°e
18
5.0 I-________~--------+-----~~~~~--~
(.)
/ ' TA=25°C
~
J[
-
i
TA=I-40oe /
2.0
I--=--'--~f__-----=_"""F'--------_I_--------_I
.9
30
1.0 L.::_ _ _-'---_ _ _...L.._ _ _- ' -_ _ _--1
6.0
12
18
24
30
Vee, SUPPLY VOLTAGE (V)
10-33
MC33091A
Figure 4. Input Control Current
versus Input Control Voltage
160
<" 140 _ Vcc:114V
~
TA : 25°C
!z
w
120
::>
100
a:
a:
(.')
-'
~
/'
I-
40
::>
a.
;;!!;
~ 180
a: 160
a:
::>
(.')
140
-'
0
~
a:
!z 120 I-- TA : 25°C
/
~5 20
o
o
8
/
a.
;;!!;
....:..5
/'
1.0
2.0
-
~ 100
4.0
3.0
5.0
6.0
12
Vin.INPUT CONTROL VOLTAGE (V)
1.2
~
5~
>
l!;l
18
24
30
Vee. SUPPLY VOLTAGE (V)
Figure 6. Fault Voltage versus
Fault Sink Current
1.4 ,---,------.,.----.--::;.----,----,
~
-
80 t- TA: 125°C
60
6.0
--------
Vin: 5.0 V
TA:-4~
!z
w
/'
60
0
<"
/',1"
80
(.')
V
-
200
/
Figure 5. Input Control Current
versus Supply Voltage
Figure 7. Squaring Constant uK"
versus Supply Voltage
1.30 , - - - - - - , , - - - - - - , - - - - - , - - = . . - - - ,
::t
RX: 100k
j::' 1.25 VDS: 2.0 V +------'-+--:::;;~'--__t---__i
1
z
1.0
f_--+---I-7'~-+---f_--_I
g 1.20 f_---+-~~_+----t__---__j
0.8
\_---+---7''--\_---+-7''~-\_--_j
8 1.15 t---7'l---i---:::::;;;;;;;;;:t:::===--i
0.6
f_---J.-~--h~"-+----:f_--_I
if
(!)
z
~ 1.10 f_-,.£--+---:;;;;;.....,:;.....=.-:-::-t-----__j
§
~ 0.4 f_....,,~+"7"''''"''--f__=-'''F-
I-
If
> 0.2 r:.~'--::::.....~'---f_--+---t__--_I
iii
lE
1.05 \ _ - - - - 7 " 7 " ' ' ' - - - + - - - - t - - - - - - j
1.00 f_"'7'''S-c--+---_+----t__---__j
::>
(.')
1.0
2.0
3.0
4.0
5.0
,;: 0.95 ' - - - - - - ' - - - - - - ' - - - - - ' - - - - - - '
6.0
12
18
24
30
Vee. SUPPLY VOLTAGE (V)
IFaull. FAULT SINK CURRENT (mA)
Figure 8. Timer Current versus
Drain-to-Source Voltage Squared
Figure 9. Timer Current versus
Drain-to-Source Voltage Squared
600,----,-----,-----,----,
~o,----,-----,-----,----,
Vee: 14 V
Yin : 5.0 V
RX: 75 k
300
<"
TA: 25°C
6 25of_---1I--~~~~::::+=::::::~
ffi
lE
B
a:
w
:;
I
200 \_----+---.,"7"'-J;,.e::---
I-
z
f_-----b>~"7"'---+----+_---_I
(.')
0.1 w::..._ _ _-'-_ _ _-'--_ _ _.....L._ _ _---'
0.1
50
100
150
200
VDS2. DRAIN-TO-SOUReE VOLTAGE SQUARED (y2)
10-34
Vee:
14VV
Yin = 5.0
TA = 25°C
+'-----+--.,.,...~h;;;;"sO"k=
RX = 50 k
400
300
FlX=75k
a:
w
:;
;::: 200
0
50f_~~-+_---~---_r---_1
500
w
a:
a:
::>
150
;::: 100 \_----"fY.ioII"-----t----+----_j
-g
~
_00
RX: 1OOk
100
0.1 ......
o
~
_ _.l..-_ _ _--'--_ _ __'__ _ __ '
50
100
150
200
VDS2. DRAIN-TO-SOUReE VOLTAGE SQUARED (V2)
MOTOROLA ANALOG IC DEVICE"DATA
MC33091A
~ 4.64
Figure 10. Timer Upper Threshold Voltage
versus Temperature
w
"'-
VCC=7.0V
(!)
i:]
4.62
~
9
4.60
~
~ 4.58
a:
~ 4.56
a:
4.54
-
----....
i!:
;:5 4.62 1--'...-''''''111''''''"--1------1-----+-----1
~9
~
~
~
50
4.60
1-----""+--",,.,._;::--+------+-----1
4.58 f - - - - - j - - " '...--+---"'.....2"""-...io::--------j
a:
Yin =5.0V
VTH = Increasing VT causing Gate turn-{)ff
a:
~ 4.52
F
4.50
>
-50
(!)
"
VCC=14V
VCC=28V
w
gs
Figure 11. Timer Upper Threshold Voltage
versus Supply Voltage
~ 4.64 , - - - - - - - , - - - - - , - - - - - - - , - - - - - ,
~ 4.56
a:
w
~ 4.54 f-----j-----+--...".",~-+-------j
a:
~
100
!:lI 4.521-----+----+------+""',.,-----j
F
150
i!: 4.50 ' - - - - - - - - - ' - - - - - - ' - - - - - - ' - - - - - - '
>
6.0
12
18
TA, AMBIENT TEMPERATUE (OC)
~ 1.10
w
(!)
;:5 1.05
~
1.00
• Cl
--'
a
m
0.95
a:
F
a:
0.90
~
Figure 12. Timer Lower Threshold Voltage
versus Temperature
"
ffi
:2 0.80
F
F 0.75
>
o
-50
~ 1.2
w
Jcc "
"
0.85
i:]
~
Cl
~~
a:
""
50
i!:
a:
~
TA =-40°C
1.1
1.0
TA = 25°C
0.9
O.B
TA = 125°C
0.7
Yin = 5.0 V
VTL = Decreasing VT causing Gate turrt-{)n
a:
"
100
TA, AMBIENTTEMPERATUE (OC)
~
0.6
F
150
.j
0.5
6.0
12
-
~
w
20
(!)
i:]
15
>
w
!;;(
10
a
~
40
I
t
I
~
w
VCC=14V _
TA = 25°C
(!)
r-
~
35
(!)
(!)
>6 5.0
>6
30
25
20
-5.0
2.0
2.2
/
'-2.4
2.6
Yin, INPUT CONTROL VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
2.8
15
3.0
./
/"
....
..,./
w
!;;(
-
TA~
-40°C"
125°C
Yin = 5.0 V (Gate "on")
IG,,5.01JA
i:]
I
t
30
24
Figure 15. Gate Voltage versus
Supply Voltage
45
-
25
18
Vcc, SUPPLY VOLTAGE (V)
Figure 14. Gate Voltage versus
Input Control Voltage
30
30
Figure 13. Timer Lower Threshold Voltage
versus Supply Voltage
(!)
7.0 V"
28 V Yin = 5.0 V
VTl = Decreasing VT causing Gate turn-{)n
" ."'"
24
Vcc, SUPPLY VOLTAGE (V)
6.0
/'
/
12
18
24
30
Vcc, SUPPLY VOLTAGE (V)
10-35
MC33091A
Figure 16. Gate Voltage versus Supply Voltage
Figure 17. Gate Voltage verus Gate Current
50.----,-----,----,-----.----,----,
1.15
TA =-40°C
1.10
:;;-
TA = 25°C
W 1.05
C!l
!:§
1.00
§2
Yin = 0 V(Gate "off')
~ 0.95
C!l
C!J 0.90
>
0.85
TA= 125°C
0.80
6.0
12
18
24
30
-50
-100
VCC. SUPPLY VOLTAGE (V)
Figure 18. Gate-to-Source Voltage
versus Source Voltage
14
I
C!l
~
12
w
10
~.1..
II
8.0
!;(
II
C!l
II
ih
-?
1m
1.0
2.5
~
§2
I
1.5
z
0
~
:::l
1 300 f-------+--------+------~/"":;;__=_;::___1
~ 250f-------+--------+~~----~~~--_1
a!E
_0100f-~~~~---=~~~------r-------_1
VCC='14 V
Load sr0rted
50r=~~~+_------+------~------~
1.5
2.0
2.5
T~ = 25
0
w
~
t
~
~
:::l
55
0.90
w
0.45
j
>C!J
><5
0.2
.",. ~
1.80
~
30
0.4
0.6
'G. GATE CURRENT (rnA)
0.8
1.0
TA =-40°C
£V'
z
Q 1.35
C!l_
10-36
______
24
~2.25
C!l
T~ = 12~oC
o
~
Figure 21. Gate Saturation Voltage
versus Gate Current (Expanded Scale)
0.5
o
______
18
Figure 20. Gate Saturation Voltage
versus Gate Current
W
C!l
~
VCC. SUPPLY VOLTAGE (V)
!;(
!;(
~
6.0
VSRC. SOURCE VOLTAGE (V)
"
4.0
(.)
~
3.0
't
z
1\
\
"'"
~ 2.0
ll.0
~
.........
~
0
i1i
>0
VOS(min~ = [(VTHRX2IQ)lRrJll2
VTH=4. V
IQ100J.tA
RX= lOOk
1\ ".........
Figure 23. Timer Response versus
VDS(minyS Ratio
..",..,..
~
~
r--....
/'
r--
./
.......- ~-
:E
200
300
400
500
600
700
800
900
1000
S10-6
-
0.05 0.10
0.15
0.20
10r-~~~~~~~~---r--+-~r--T--~
;:s
~
0.50
20r-~"-I-~tt-~~-+
15 f-+H.--7I"''-
w
!;;:
(!)
?
5.0 ffh"'-t----r--,='--r-'--r---r-
200
300
400
500
600
700
800
10~~~~~4---~~---r--+---t-~--~
Input = 5.0 VStep
5.0 I+-+---'=r----'r----+--+---I-- VCC = 14 V
TA = 25°C
900 1000
100
200
300
t,nME(~)
Figure 26. FET Comparison Gate Response
4Or-~t-~~~-r--~~
~
w
w
(!)
T~ = 25
40
!:ia
20H+~~~~~~---+---4~--+---4---~
!;;: 20
30
(
>
w
(!)
10
l1li---+---4----1----+---+
100
200
300
400
500
Input = 5.0 VStep
VCC = 28 V
TA = 25°C
600
t,nME(lls)
MOTOROLA ANALOG IC DEVICE DATA
700
700
800
900 1000
?
800
0
t/ /
Vee =28 V
V"
(!)
30 1-+-+<:1---7""-
?
400 500 600
t,nME(lls)
Figure 27. MTP25N06 Gate Response
50
(!)
0.45
~
100
!;;:
0.40
Figure 25. FET Comparison Gate Response
~
>(!)
52
w
0.35
Figure 24. FET Comparison Gate Response
(!)
!:i
0.30
VOS(minVVS, ORAIN-TO-SOURCE VOLTAGE
to SUPPLY VOLTAGE RATIO
!;;:
~
0.25
AT, EXTERNAL TIMER RESISTOR (kn)
15
w
RrCT=O.Ol
t(jn) =-iT In[1 - (Vormin1s2J -
0
100
w
52
RrCr=°·l
.,/'
Rx-SO;- ~
(!)
!:i
-
/'" L,...---- ,..-:" ~
RX = 75 k
r-- Z
--
~
RrCr= 1.0
V
10
o
V
V
~ ....VCy=14,
VCC = 7.0 V _ MTP25N06
Ciss = 1000 pF
:nput = ~.O V~tep
V
o
100
200
300
I
'I
k-- ~
400
500
I
600
700
800
900 1000
t, TIME (Ils)
10-37
MC33091A
Figure 28. Descriptive Waveform Diagram
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
I
vz-j-
1
1
[
<30V
(;~c~ 1L_11__ J--l---I---1--J-------I--1-------1-.
ov
1
1
1
1
1
1
1
1
1
Input
(Pin7)
r--i
I
-+--r---1--+---I---+--~-·
1
1
--"""1
1
----,
Gate
(Pin 4)
I
1
1
5.0V
--{---------I-· ov
1
--j---T--,
-~
-
VSRC+14V
~c-wv
1
1
1
1
1
ov
VT
(Pin 8)
SRC
(Pin 1)
-+--------1-. OV
DRN
--
(Pin2) - -
--
1 VDS
--+---11 --+---1---Il--T--j
--j---I---f--
1
1
1
1Q-38
1
1
1
1
Noilnal Oper~tion
1
1
1
--+--------1-·
----------1--
1---1 - - 1---1 ------1-1
1
1
1
1
1
Shorted FET LJad
1
Normal Operati
5
0
6.0
4.0
<.>"
0
2.0
o
2.0
VTH=4.6V
VTL =0.95 V
'= voros min)
.i
\
\
\
,
I
1\
\.
"- r--.....L
4.0
I
1
In(VTtJVTH)
1 + (VTH - J32 VTH)
In (VTL - /32 VTH)
oc=
~
6.0
I
B.O
-
f--
-
f--
f--
I
10
12
VOsiVOS(min)
As previously discussed, ISO is externally dependant on
the sensed VDS voltage developed across the TMOS device
and RX in accordance with Equations 1 and 2. At the onset of
an overload condition, the voltage across CT will be less than
the VTH threshold voltage of the upper comparator with the
TMOS device in an "on" state. ISO current will increase
dramatically and the timing capacitor CT charges toward VTH.
When the voltage on CT reaches the VTH threshold voltage of
the upper comparator, the upper comparator output goes
high setting the latch output (a) high, tuming on the open
collector NPN transistor and pulling the Fault output low. At
MOTOROLA ANALOG IC DEVICE DATA
=-RTCT In[1-(VTH-VTLl/(ISORT-VTLll
(10)
The discharge time (td) of CT can be shown as:
!d = -RTCT In(VTLNTH}
(11)
The duty cycle is defined as charge time divided by the
charge plus discharge time and represented by:
DC
(9)
As long as the average power, in Equation 9, is less than
the maximum power dissipation of the TMOS device under
normal conditions, the short circuit protection scheme of the
MC33091A will adequately protect the TMOS device. The
duty cycle at which the MC33091 A controls the gate can be
determined by using Figure 30.
10
tc
(8)
The average power is equal to the peak power dissipation
multiplied by the duty cycle (DC):
PD(avg)
the same time, ISO is switched off, allowing CT to discharge
through resistor RT to VTL, at which time the TMOS device is
again switched on. This action is repeated so long as the
overload condition exists. The VTL and VTH thresholds are
internally set to approximately 0.95 V and 4.6 V respectively.
The charge time (tc> of CT can be shown as:
=td(tc+td}
(12)
Substituting Equations 10 and 11 into 12:
DC
= 111+ln(VTIlVTH}/ln{(VTH-~VTH}f(VTL-132VTH}} (13)
where: 13 = VOsNOS(min}
Notice the duty cycle is dependent only on the ratio of the
drain to source voltage, VOS, of the TMOS device to the
minimum drain to source voltage, VOS(min}, allowing
uninterrupted continuous TMOS operation as calculated in
Equation 5. A graph of Equation 13 is shown in Figure 30 and
is valid for any ratio of VOS to VOS(min}. Knowing this ratio, the
duty cycle can be determined by using Figure 30 or Equation
13 and knowing the duty cycle, the average power
dissipation can be calculated by using Equation 9.
If the TMOS device experiences a hard load short to
ground a minimum duty cycle will be experienced which can
be calculated. When this condition exists, the TMOS device
experiences a VOS voltage of Vs which is sensed by the
MC33091A. The MC33091A very rapidly charges the timing
capaCitor CT to VTH shutting down the TMOS device. This
condition produces the minimum duty cycle for the specific
system conditions. The minimum duty cycle ,can be
calculated for any valid Vs voltage by substituting the value of
Vs used for VOS in Equation 13 and solving forthe duty cycle.
Knowing the duty cycle and peak power allows
determination of the average power as was pointed out in
Equation 9. TMOS data sheets specify the maximum
allowable junction temperature and thermal resistance,
junction-to-case, at which the device may be operated.
Knowing the average power and the device thermal
information, proper heatsinking of the TMOS device can
be determined.
The duty cycle graph (Figure 30) reveals lower values of
VOS(min} produce shorter duty cycles, forgiven VOS voltages.
The minimum duty cycle, being limited to the case where
VOS VS, increases as higher values of Vs are used.
=
1G-41
1m
•
MC33091A
APPLICATION
The following design approach will simplify application of
the MC33091 A and will insure the components chosen to be
optimal for a specific application.
1. Characterize the load impedance and determine
the maximum load current possible for the load supply
voltage used:
2. Select a TMOS device capable of handling the
maximum load current. Though the MC33091A will equally
drive our competitors products, it is hoped you will select one
of the many TMOS devices listed in Motorola's Power
MOSFET Transistor Data Book.
3. Oetermine the maximum steady state VOS voltage the
TMOS device will experience under normal operating
conditions. Typically, this is the maximum load current
multiplied by the specified ROS(on) of the TMOS device.
Junction temperature considerations should be taken into
account for the ROS(on) value since it is significantly
temperature dependent. Normally, TMOS data sheets depict
the effect of junction temperature on ROS(on) and an ROS(on)
value at some considered maximum junction temperature
should. be used. Various graphs relating to ROS(on) are
depicted in Motorola TMOS data sheets. Though Motorola
TMOS devices typically specify' a maximum allowable
junction temperature of 150°C, in practical sense, the user
should strive to keep junction temperature as low as possible
so as to enhance the applications long term reliability. The
maximum steady state VOS voltage the TMOS device will
experience under normal operating conditions is thus:
a
.
VOS(norm)
=ll(max)ROS(on)
(14)
4. Calculate the maximum power dissipation of the TMOS
device under normal operating conditions:
PO(max)
=VOS(on)IL(max)
(15)
5. The calculated maximum power. dissipation of the
TMOS device dictates the required thermal impedance for
the application. Knowing this, the selection of an appropriate
heatsink to maintain the junction temperature below the
maximum specified by the TMOS manufacture for operation
can be made. The required overall thermal impedance is:
TRJA =' (TJ(max) ~ TA(max»/PD(max)
(16)
Where TJ(max), the maximum allowable junctiqn
temperature, is found on the TMOS data sheet and TA(max),
the maximum ambient temperature, is dictated by the
application itself.
6. The thermal resistance, TRJA, represents the maximum
overall or total thermal resistance, from junction to the
surrounding ambient, allowable to insure the TMOS
manufactures maximum junction temperature will not be
exceeded. In general, this overall thermal resistance can be
considered as being made up of several separate minor
thermal resistance interfaces comprised of TAJC, TRCS and
TRSA such that:
TRJA
=TRJC + TRCS + TRSA
(17)
Where TAJC, TRCS and TRSA represent the junction-tocase, case-to-heatsink and heatsink-to-ambient thermal
resistances respectively. TRCS and TRSA are the only
parameters the device user can influence.
10-42
The case-to-heatsink thermal resistance, TRCS, is
material dependent and can be expressed as:
TRCS
=P x
tlA
(18)
Where Up" is the thermal resistivity of the heatsink material
(expressed in °ClWattlUnit Thickness), "I" is the thickness of
heatsink material, and "A"' is the contact area of the
case-to-heatsink. Heatsink manufactures specify the value
of TRCS for standard heatsinks. For nonstandard heatsinks,
the user is required to calculate TRCS using some form of the
basic Equation 18.
The required heatsink-to-ambient thermal resistance,
TRSA, can easily be calculated once the terms of Equation 17
are known. Substituting TAJA of Equation 16 into Equation 17
and solving for TRSA produces:
TRSA
=(TJ(max)-TA(max»/PO(max)-(TRJC+TRCS)
(19)
Consulting the heatsink manufactures catalog will provide
TRCS information for various heatsinks under various
mounting conditions so as to allow easy calculation of TRSA
in units of °CIW (or when multiplied by the power dissipation
produces the heatsink mounting surface temperature rise).
Furthermore, heatsink rnanufactures typically sPl:ICify for
various heatsinks, heatsink efficiency in the form of mounting
surface temperature rise above the ambient conditions for
various power dissipation levels. The user should insure that
the heatsink selected will provide a surface temperature rise
somewhat less than the maximum capability of the heatsink
so that the device junction temperature will not be exceeded.
The user should consult the heatsink manufacturers catalog
for this information.
7. Set the value of VOS(min) to something greater than the
normal operating drain to source voltage, VOS(norm), the
TMOS device will experience as calculated in Step 3 above
(Equation 14). From a practical standpoint, a value two or
three times VOS(norm) expected under normal operation will
prove to be a good starting point for VOS(min).
8. Select a value of RT less than 1.0 Mn for minimal timing
error whose value is compatible with RX (RX will be selected
in Step 9 below). A recommended starting value to use for AT
would be 470 k. The consideration here is that the input
impedance of the threshold comparators are approximately
10 Mn and if RT values greater than 1.0 Mn are used,
significant timing errors may be experienced as a result of
input bias current variations of the threshold comparators.
9. Select a value of RX which is compatible with AT. The
value of RX should be between 50 k and 100 k. Recall in
Equation 5 that VOS(min) was determined by the combined
selection of RX and RT. Low values of RX will give large
values for K (K 4.0 1J.AIV2 for RX 50 k) causing ISO to be
very sensitive to VOS variations (see Equation 1). This is
desirable if a minimum VOS trip pOint is needed in the 1.0 V
range since small VOS values will generate measurable
currents. However, at high VOS values, TMOS device
currents become excessively large and the current squaring
function begins to deviate slightly from the predicted value
due to high level injection effects occurring in the output PNP
of the current squaring circuit. These effects can be seen
when ISO exceeds several hundred microamps. See
Figure 22 for graphical aid in the selection of RT and RX. .
=
=
MOTOROLA ANALOG IC DEVICE DATA
MC33091A
10. Calculate the shorted load average power dissipation
for the application using Equations 8 and 9. This involves
determining the peak shorted load power dissipation of the
TMOS device and gate duty cycle. The duty cycle is based
on VDS(min), the value of VDS under shorted conditions (Le.
VS(max».
11. The calculated shorted load average power dissipation
of Step 10 should be less than the maximum power
dissipation under normal operating conditions calculated in
Step 4. If this is not the case, there are two options.
Option one is to reduce the thermal resistance of the
TMOS device heatsink, in other words, use a larger or better
heatsink. This though, is not always practical to do
particularly if restricted by size.
Option two is to set VDS(min) to the lowest practical value.
If for instance VDS(min) is set to 4.0 V when only 2.0 V are
needed, the short circuit duty cycle will be over twice as large,
resulting in double the TMOS device power dissipated.
Keeping VDS(min) to a minimum, reduces the shorted load
average power.
12. Choose a value of Cr- The value of CT can be
determined either by trial and error or by characterizing the
VDS waveform for the load and selecting a capacitor value
that generates a minimum fault time curve (see Equation 4)
that encompasses the VDS versus time waveform. The value
of CT has no effect on the duty cycle itself as was pointed out
earlier. See Figure 23 for a graphical selection of CT.
Inductive Loads
The TMOS device is turned off by pulling the gate to near
ground potential. Turning off an inductive load will cause
the source of the TMOS device to go below ground due to
flyback voltage to the point where the TMOS device may
become biased on again allowing the inductive energy to be
dissipated through the load. An internal 14 V zener diode
clamp from the gate to source pin limits how far the source pin
can be pulled below ground. For high inductive loads, it may
be necessary to have an external 10 k current limiting resistor
in series with the source pin to limit the clamp current in the
event the source pin is pulled more than 14 V below ground.
Transient Faults
The MC33091A is not able to withstand automotive
voltage transients directly. By correctly sizing resistor RS and
capacitor CS, the MC33091A can withstand load dump and
other automotive type transients. The VCC voltage is clamped
at approximately 30 V through the use of an internal zener
diode.
Under reverse battery conditions, the load will be
energized in reverse due to the parasitic body diode inherent
in the TMOS device. Under this condition, the drain is
grounded and the MC33091 A clamps the gate at 0.7 V below
the battery potential. This turns the TMOS device on in
reverse and minimizes the voltage across the TMOS device
resulting in minimal power dissipation. Neither the
MC33091 A nor the TMOS device will be damaged under
such a condition. In addition, if the load can tolerate a reverse
MOTOROLA ANALOG IC DEVICE DATA
polarity, the load will not be damaged. Caution; some
sensitive applications may not tolerate a reverse polarity load
condition with reverse battery polarity.
There is no protection of the TMOS device during a
reverse battery condition if the load itself is already shorted to
ground. The MC33091A will not incur damage under this
specialized reverse battery condition but the TMOS
device may be damaged since there could be significant
energy available from the battery to be disSipated in the
TMOS device.
The MC33091 A will withstand a maximum VCC voltage of
28 V and with the proper TMOS device used, the system can
withstand a double battery condition.
Figure 36 depicts a method of protecting the FET from
positive transient voltages in excess of the rated FET
breakdown voltage. The zener voltage, in this case, should
be less than the FET breakdown voltage. The diode, D, is
necessary where reverse battery protection of the gate of the
FET is required.
EMIConcern
The gate capacitance and thus the size of the TMOS
device used will determine the turn-on and turn-off times
experienced. In a practical sense, smaller TMOS devices
have smaller gate capacitances and give rise to higher slew
rates. By way of example, the turn-on of an MPT50N06
TMOS device might be of the order of 80 J.lS while that of an
MPT8N10 might be 10 ~s (see Figure 25). The speed of
turn-on or turn-off can be calculated by assuming the charge
pump to supply approximately 100 ~ over the time the gate
capacitance will transition a VGS voltage of 0 V to 10 V. In
reality, the VGS voltage will be greater than 10 V, but the
additional increase in TMOS drain current will be minimal for
VGS voltages greater than 10 V.
The charge pump current is sized so that turn-on time
need not be of concem in all but the most critical of
applications. Where limiting of EMI is of concern, the charge
pump of the MC33091A may be slew rate limited by adding
an external feedback capacitor from the gate-to-source of
the TMOS device for slow down adjustment of both turn-on
and turn-off times (see Figure 33). Figures 31 through 35
depict various methods of modifying the turn-on or turn-off
times.
Figure 35 depicts a method of using only six external
components to decrease turn-off time and clamp the flyback
voltage associated with switching inductive loads. VGS(th)
used in the critical component selection criteria refers to the
gate-ta-source threshold voltage of the FET used in the
application.
Caution should be exercised when slowing down the
switching transition time since doing so can greatly increase
the average power dissipation of the TMOS device. The
resulting increase in power dissipation should be taken into
account when selecting the RTCT time constant values
in order to protect the TMOS device from any overcurrent
condition.
10-43
MC33091A
Figure 31. Slow Down FET Turn-On
Figure 32. Slow Down FET Turn-Off
Figure 33. Slow Down Turn-On and Turn-Off of FET
Figure 34. Independent Slow Down Adjustment
of FET Turn-On and Turn-Off
Figure 35. Decreased FETTurn-Off Time with
Inductive Flyback Voltlige Clamp
Figure 36. Overvoltage Protection of FET
Rp
1~4
~
+vs
vz-vs
MOTOROLA ANALOGIC DEVICE DATA
®
MOTOROLA
MC33092
Alternator Voltage Regulator
The MC33092 is specifically designed for voltage regulation and Load
Response Control (LRC) of diode rectified alternator charging systems, as
commonly found in automotive applications. The MC33092 provides load
response control of the alternator output current to eliminate engine speed
hunting and vibration due to sudden electrical loads which cause abrupt
torque loading of the engine at low RPM. Two load response rates are
selectable using Pin 11. The timing of the response rates is dependent on
the oscillator frequency.
In maintaining system voltage, the MC33092 monitors and compares the
system battery voltage to an externally programmed set point value and
pulse width modulates an N-channel MOSFET transistor to control the
average alternator field current.
ALTERNATOR VOLTAGE
REGULATOR
SEMICONDUCTOR
TECHNICAL DATA
• Forced Load Response Control (LRC) with Heavy Load Transitions
at Low RPM
• Capable of Regulating Voltage to ± 0.1 V @ 25°C
• Operating Frequency Selectable with One External Resistor
• < 0.1 V Variation over Speed Range of 2000 to 10,000 RPM
• < 0.4 V Variation over 10% to 95% of Maximum Alternator Output
• Maintains Regulation with External Loads as Low as 1.0 A
DWSUFFIX
PLASTIC PACKAGE
CASE 751D
(So-20L)
• Load Dump Protection of Lamp, Field Control Devices, and Loads
• Duty Cycle Limit Protection
• Provides High Side MOSFET Control of a Ground Referenced Field
Winding
• Controlled MOSFET and Flyback Diode Recovery Characteristics for
Minimum RFI
• < 2.0 mA Standby Current from Battery @ 25°C
• < 3.0 mA Standby Current from Battery Over Temperature Range
• Optional 2.5 or 10 sec. LRC Rate Control (Osc. Freq.
=280 kHz)
PIN CONNECTIONS
• Undervoltage, Overvoltage and Phase Fault (Broken Belt) Detection
Filter Buffer
0
Remote Sense
Simplified Block Diagram
Fa uv
Vref
r-------- -1
19
2{)
1
1
1
1
21
lamp Collector
lamp Base
Gnd {
Oscillator
Adjust
Vre f0
Oscillator
Phase
(Top View)
ORDERING INFORMATION
Device
MC33092DW
MOTOROLA ANALOG IC DEVICE DATA
Operating
Temperature Range
Package
TA = - 40° to +125°C
So-20L
10-45
MC33092
MAXIMUM RATINGS
Rating
Power Supply Voltag~
Load Dump Transient Voltage (Note 1)
Negative Voltage (Note 2)
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA = 125°C
Thermal Resistance, Junction-te-Ambient
Symbol
Value
Unit
Vbat
+V max
-Vmin
24
40
-2.5
V
V
V
PD
RaJA
867
75
°CfW
TJ
+150
°C
TA
- 40 to +125
°C
Tstg
-45to+150
°C
Operating Junction Temperature
Operating Ambient Temperature Range
Storage Temperature Range
mW
ELECTRICAL CHARACTERISTICS (External components per Figure 1, TA = 25°C, unless otherwise noted).
Characteristic
Symbol
Min
Typ
Max
Unit
Regulation Voltage
(Determined by external resistor divider)
VReg
-
14.85
-
V
Regulation Voltage Temperature Coefficient
TC
-13
-11
-9.0
mVrC
Vbat
11.5
14.85
16.5
V
VPwr
0.5
1.2
2.0
V
101
102
-
1.3
2.0
3.0
mA
mA
V
DC CHARACTERISTICS
Suggested Battery Voltage Operating Range
Power Up/Down Threshold Voltage (Pin 3)
Standby Current,
Vbat 12.8 V, Ignition off, TA 25°C
Vbat 12.8 V, Ignition off, - 40°C"TA,,125°C
=
=
=
Zero Temperature Coefficient Reference Voltage, (Pin 8)
-
Vref0
1.1
1.25
1.4
Band Gap Reference Voltage (Pin 20)
Vref
1.7
2.0
2.3
V
Band Gap Reference Temperature Coefficient
TC
-13
-11
-9.0
mV/oC
SLoss(th)
-
0.6
1.0
V
Phase Detection Threshold Voltage (Pin 10)
PTh
1.0
1.25
1.5
V
Phase Rotation Detection Frequency (Pin 10)
PRot
-
36
-
Hz
Sense Loss Threshold (Pin 2)
Undervoltage Threshold (Pin 19)
VUV
1.0
1.25
1.5
V
Overvoltage Threshold (Pin 2, or Pin 12 if Pin 2 is not used)
VOV
1.09(Vref)
1.12(Vre f)
1.16(Vref)
V
Load Dump Threshold (Pin 2, or Pin 12 if Pin 2 is not used)
VLD
1.33(Vre f)
l.4(Vre f)
1.48(Vref)
V
f
-
68
-
Hz
losc
205
280
350
kHz
SWITCHING CHARACTERISTICS
Fundamental Regulation Output Frequency, (Pin 17)
(Clock oscillator frequency divided by 4096)
Suggested Clock Oscillator Frequency Range, (Pin 9)
(Determined by external resistor, RT, see Figure 6)
'.
Duty Cycle (Pin 17)
At Start-up
During Overvoltage Condition
StartDC
OVDC
27
3.5
29
4.7
31
5.5
%
%
Low/High RPM Transition Frequency (Pin 10)
LRCFreq
247
273
309
Hz
LRCS
8.5
9.5
10.5
%/sec
LRCF
34
38
42
%/sec
LRCH
409
455
501
"Io1sec
LRC Duty Cycle Increase Rate
Low RPM Mode (LRCFreq < 247 Hz),
Pin 11 Open (Slow Rate)
Low RPM Mode (LRCFreq < 247 Hz),
Pin 11 Grounded (Fast Rate)
High RPM Mode (LRCFreq > 309 Hz),
=
=
Pin 11
=Don't Care (LRC Mode is disabled)
NOTES: 1. 125 ms wide square wave pulse.
2. Maximum time = 2 minutes.
10-46
MOTOROLA ANALOG IC DEVICE DATA
Figure 1. Simplified Application
iii:
a
Sense
21
o
~
:roo
28k
~
(;
C
I
J
5G')
1.0k
r-------------I
I
MC33092
I
I
I
I
2I
m
<
(;
m
c
~
)0
oHx~j
+ I
01----+----,
B+ Supply
250
45k
28k
Phase
Undervoltage
2.0k
Field
2.0k
Lamp
3:
II, ?l1
o
Co)
g
I\)
10
MR850
RT
NOTES: R1 = R2 = 3.0 k 10 5.0 k
R3=10kl015k
RT=50kl0100k
...
~
Ground
Battery
-=-
MC33092
Figure 2. Standby Current versus Temperature
0.8
<"
.s
0.7
I-
z
w
II:
II:
0.6
::>
U
ii:i
0
z
~
0.5
'"
ISB : Current from VCC Supply
VCC: 12.8 V (see Figure 8)
VCl : 0.5 V (Ignnion OFF)
VPin2: VPin 12: 1.5 V
VPin 10 = VPin 11 = VPin 19: 0 V
"'- ~
.............
0.4
...............
0.3
0.2
-55
-~
w
~
0
1.7
~
w
1.6
i:!:
'-'
g
1.5
z
1.4
Cl
~
II:
...........
(J)
............. joo."
.........
1.2
1.1
-~
w
~
0
"
"~
~
100
TA, AMBIENT TEMPERATURE (0C)
TA, AMBIENT TEMPERATURE (OC)
Figure 4. Reference Voltage versus Temperature
Figure 5. OTC Reference Voltage
versus Temperature
13g
.........
Vref : Voltage at Pin 20
VCC = 12.8 V (see Figure 8)
VCl : 0.5 V (Ignition OFF)
VPin 2: VPin 12: 1.5 V
VPin 10: VPin 11 : VPin 19: 0 V
'"
b.....
2.0
1.9
i'-.
"'-... ......
~
.......
>
1.8
-55
-25
25
50
75
"
100
TA, AMBIENTTEMPERATURE (0C)
rr-
S
~
" ,
1.20
-55
125
60
~
~
2.5
.....
1-.1
~
w
2.0
I
13
g
1.96
I
~
~
-
I-
"
B
f, FREQUENCY (kHz)
10-48
o
-25
25
50
1 Lo~d DU~P
Protection
-t
Cl
::>
a.
, ,
VCC: 14.8 V (see Figure 8)
VC2: 6.0 V (Sl Closed)
VPin2 :VPin 10: VPin 12: VPin 19: 1.5V
VPinl1: 0V
~
,.,./
~
~
-&-
"'"1-. I--L
1.95
100
125
Vin: Voltage at Pin 2 or 12 Duty Cycle taken at Pin 17
VCC: 14.8 V (see Figure 8) :
VC2 : 6.0 V (Sl Closed)
:::
VPin 10: 1.5 V@ >309 Hz
VPin 11: OV;VPin 19: 1.5V-
--, -&-
-5'
a.
i"- ""--
c:
->
.........
~
75
Figure 7. Input Voltage versus Output Duty Cycle
R : Resistance from Pin 7 to Ground _
f: Frequency at Pin 9
r-...
./
"......,.
TA, AMBIENT TEMPERATURE (OC)
.........
70
----
1.21
3.0
~
Vref '" : Voltage at Pin 8
VCC: 12.8 V (see Figure 8)
VC2 = 6.0 V (Sl Closed)
VPin 2: VPin 12: 1.5 V
VPin 10: VPin 11: VPin 19: 0 V
>
Figure 6. Oscillator Frequency
versus Timing Resistor
110
125
1.26
~
w 2.1 joo."
Cl
W
II:
............
1.3
1.0
-55
125
2.2
w
u
z
w
II:
w
u..
" '"
VON: Voltage at Pin 3
VCC: 12.8 V (see Figure 8)
VPin 2: VPin 12: 1.5 V
VPin 10: VPin 11 : VPin 19: 0 V
~
~
1.94
1.93
o
10
20
30
40
50
60
70
80
90
100
DC, DUTY CYCLE (%)
MOTOROLA ANALOG IC DEVICE DATA
s::
a
:rJ
o
Figure 8. Typical Test Circuit
>
VCC
)00
z)00
8
250
(')
c
m
<
r--------------
m
1
1
1
(')
c
~
l>
MC33092
1
1
1
21
Sense
(Remote)
01
1
1
2.0k
~
IIU
s::
o
121
II
Supply Reg ot-i~±
(Local) •
~
~
II
I
===n
~
OVC1
~
o
~
MC33092
PIN FUNCTION DESCRIPTION
Pin No.
Function
Description
1
FB
This pin provides a filtered resu~ of the Sense input (if the Sense input is used) or the Supply
Regulation input (if the Sense input is not used).
2
Sense
The Sense input is a remote (Kelvin), low current battery voltage reference input used to give an
accurate representation of the true battery voltage. This input is also used to monitor overvoltage or
load dump conditions.
3
Lamp Collector and
Power-UplDown
This pin connects to the collector of the transistor (02) used to drive the fault lamp. It is also used to
sense a closed ignition switch (voltage sense) which then turns power on to the IC.
4
Lamp Base
The Lamp Base pin provides base current to the fau~ lamp drive transistor (02).
5
Ground
Grounded to provide a ground retum for the fau~ lamp control logic circuH.
6,15
Ground
IC ground reference pins.
7
Oscillator Adjust
A resistor to ground on this pin adjusts the internal oscillator frequency (see Figure 6).
8
' V rei0
This is a test point for the 1.1 V to 1.4 V reference voltage. It has a zero temperature coefficient. The
reference is used internally for phase signal and undervoltage detection.
9
' OSCillator
Test point for checking the operation of the internal oscillator.
10
Phase
The Phase input detects the existence of a magnetic field rotating within the alternator.
11
Rate
The Rate pin is used to select a slow mode (floating) or fast mode (ground) Load
Response Control recovery rate.
12
Supply Regulation
The voltage on the Supply Regulation pin is used as a representation of the alternator output
voltage. This input also used to monitor overvoltage or load dump conditions.
13
VCC3
Positive supply forthe internal Charge Pump.
14
VCC1
Positive supply for the entire IC except for the Charge Pump.
Ground
Ground reference for the IC.
15,6
,
16
N/C
No connection.
17
Gate
Controls the Gate of the MOSFET used to energize the field winding.
18
Source
Field winding control MOSFET source reference.
19
Undervoltage
If the voltage at this pin goes below 1.0 V, the fau~ lamp is guaranteed to turn on. The IC will
continue to function, but with IimHed perfonnance.
20
'Vref
Test point for the 1.7 V to 2.3 V Bandgap reference voltage. This voltage has a negative
temperature coefficient of approximately-11 mV/aC.
'NOTE: Pins 8, 9 and 20 are test paints only.
10-50
MOTOROLA ANALOG IC DEVICE DATA
MC33092
APPLICATION CIRCUIT DESCRIPTION
Introduction
The MC33092, designed to operate in a 12 V system, is
intended to control the voltage in an automotive s~'stem that
uses a 3 phase alternator with a rotating field winding. The
system shown in Figure 1 includes an alternator with its
associated field coil, stator coils and rectifiers, a battery, a
lamp and an ignition switch. A tap is connected to one corner
of the stator windings and provides an AC signal for rotation
(phase) detection.
A unique feature of the MC33092 is the Load Response
Control (LRC) circuitry. The LRC circuitry is active when the
stator winding AC signal frequency (phase buffer input
signal, Pin 10) is lower than the Low/High RPM transition
frequency. When active, the LRC circuitry dominates the
basic analog control circuitry and slows the alternator
response time to sudden increases in load current. This
prevents the alternator from placing a sudden, high torque
load on the automobile engine when a high current
accessory is switched on.
The LRC circuitry is inactive when the stator winding AC
signal frequency is higher than the Low/High RPM transition
frequency. When the LRC circuitry is inactive, the basic
analog control circuitry controls the alternator so it will supply
a constant voltage that is independent of the load current.
Both the LRC and analog control circuits control the
system voltage by switching ON and OFF the alternator field
current using Pulse Width Modulation (PWM). The PWM
approach controls the duty cycle and therefore the average
field current. The field current is switched ON and OFF at a
fixed frequency by a MOSFET (01) which is driven directly
by the IC. The MC33092 uses a charge pump to drive the
MOSFET in a high side configuration for alternators having a
grounded field winding.
A fault detector is featured which detects overvoltage,
undervoltage, slow rotation or non-rotation (broken
alternator belt) conditions and indicates them through a fault
lamp drive output (Pin 4).
A Load Dump protection circuit is included. During a load
dump condition, the MOSFET gate drive (Pin 17) and the
fault lamp drive output are disabled to protect the MOSFET,
field winding and lamp.
Power-Up/Down
Power is continuously applied to the MC33092 through
VCC1 and VCC3. A power-up/down condition is determined
by the voltage on the Lamp Collector pin (Pin 3). When this
voltage is below 0.5 V the IC is guaranteed to be in a low
current standby mode. When the voltage at Pin 3 is above 2.0
V, the IC is guaranteed to be fully operational. The power-up
voltage is applied to Pin 3 via the ignition switch and fault
lamp. In case the fault lamp opens, a 500 n bypass resistor
should be used to ensure regulator IC power-up.
A power-up reset circuit provides a reset or set condition
for all digital counter circuitry. There is also a built-in
power-up delay circuit that protects against erratic power-up
signals.
Battery and Alternator Output Voltage Sensing
The battery and the alternator output voltage are sensed
by the remote (Sense, Pin 2), and the local (Supply
Regulator, Pin 12) input buffer pins, respectively, by way of
MOTOROLA ANALOG IC DEVICE DATA
external voltage dividers. The regulated system voltage is
determined by the voltage divider resistor values.
Normally the remote pin voltage determines the value at
which the battery voltage is regulated. In some cases the
remote pin is not used. When this condition (VPin 2 < 0.6 V
typically) exists, a sense loss function allows the local pin
voltage to determine the regulated battery voltage with no
attenuation of signal. If, however, when the remote pin is
used, and the voltage at this pin is approximately 25% less
than the voltage at the local sense pin (but greater than 0.6 V,
typically), the value at which the battery voltage is regulated
is switched to the local sense pin voltage (minus the 25%).
The signal combiner/switch controls this transfer function.
Low Pass Filter, DAC & Regulator Comparator
The output of the combiner/switch buffer feeds a low pass
filter block to remove high frequency system noise. The filter
output is buffered and compared by the regulator comparator
to a descending ramp waveform generated by an internal
DAC. When the two voltages are approximately equal, the
output of the regulator comparator changes state and the
gate of the MOSFET is pulled low (turned OFF) by the output
control logic for the duration of the output frequency clock
cycle. At the beginning of the next output clock cycle, the
DAC begins its descending ramp waveform and the
MOSFET is turned ON until the regulator comparator output
again changes state. This ongoing cycle constitutes the
PWM technique used to control the system voltage.
Oscillator
The oscillator block provides the clock pulses for the
prescaler-counter chain and the charge control for the
charge pump circuit. The oscillator frequency is set by an
external resistor from Pin 7 to ground as presented in
Figure 6.
The prescaler-counter divides the oscillator frequency by
212 (4096) and feeds it to the output control logic and
divider-up/down counter chain. The output control logic uses
it as the fundamental regulation output frequency (Pin 17).
Load Response Control
The Load Response Control (LRC) circuit generates a
digital control of the regulation function and is active when the
stator output AC signal (Pin 10) frequency is lower than the
Low/High RPM transition frequency. The LRC circuit takes
the output signal of the prescaler-counter chain and with a
subsequent divider and up/down counter to provide delay,
controls the alternator response time to load increases on the
system. The response time is pin programmable to two rates.
Pin 11 programs the divider to divide by 12 or divide by 48. If
Pin 11 is grounded, the signal fed to the up/down counter is
divided by 12 and the response time is 12 times slower than
the basic analog response time. If Pin 11 is left floating, the
Signal to the up/down counter is divided by 48 and the
response time is 48 times slower.
The basic analog (LRC not active) and digital duty cycle
control (LRC active) are OR'd such that either function will
terminate drive to the gate of the MOSFET device with the
shortest ON-time, I.e., lower duty cycle dominating.
10-51
MC33092
The digital ON-time is determined by comparing the
output of the up/down counter to a continuous counter and
decoding when they are equal. This event will terminate drive
to the MOSFET. A count direction shift register requires three
consecutive clock pulses with a state change on the data
input of the register to result in an up/down count direction
change. The count will increase for increasing system load
up to 100% duty cycle and count down for decreased loading
to a minimum of 29% duty cycle. The analog control can
provide a minimum duty cycle of 4 to 5%. The initial
power-up duty cycle is 29% until the phase comparator input
exceeds its input threshold voltage. Also, the IC powers up
with the LRC circuit active, i.~., when the Lamp Collector pin
exceeds the power-up threshold voltage.
Fault Lamp Indicator
Pins 3 and 4 control the external Darlington transistor (Q2)
that drives the fault indicator lamp. A 10 Q resistor should be
placed in series with the transistor's emitter for current
limiting purposes. The fault lamp is energized during any of
the following fault conditions: 1) No Phase buffer (Pin 10)
input due to slow or no alternator rotation, shorted phase
winding, etc.; 2) Phase buffer input AC voltage less tlian the
phase detect threshold; 3) Overvoltage on Pin 2, or Pin 12 if
Pin 2 is not used, or4) Undervoltage on Pin 19 with the phase
buffer input signal higher than the Low/High RPM transition
frequency.
Phase Buffer Input
A tap is normally connected to one corner of the
alternator's stator winding to provide an AC voltage for
rotation detection. This AC signal is fed into the phase buffer
input (Pin 10) through a voltage divider. If the frequency of
this signal is less than the phase rotation detect frequency
(36 Hz, typically), the fault lamp is lit indicating an insufficient
10-52
alternator rotation and the MOSFET drive (Pin 17) output
duty cycle is restricted to approximately 29% maximum. Also,
if the peak voltage of the AC signal is less than the phase
detect threshold, the fault lamp is lit indicating an insufficient
amount of field current and again the MOSFET drive (Pin 17)
output duty cycle is restricted to approximately 29%
maximum.
Undervoltage, Overvoltage and Load Dump
The low pass filter output feeds an undervoltage
comparator through an external voltage divider. The voltage
divider can be used to adjust the undervoltage detection
level. During an undervoltage condition, the fault lamp will
light only if the phase buffer input signal frequency is higher
than the Low/High RPM transition frequency. This is to
ensure that the undervoltage condition is caused by a true
fault and not just by low alternator rotation. To help maintain
system voltage regulation during an undervoltage condition,
the output duty cycle is automatically increased to 100%.
Even though the fault lamp may be energized for an
undervoltage condition, the MC33092 will continue to
operate but with limited performance.
Through an internal voltage divider, the low pass filter
feeds an overvoltage comparator which monitors this output
for an overvoltage condition. If the overvoltage threshold is
exceeded, the fault lamp is lit and the MOSFET drive (Pin 17)
output duty cycle is restricted to approximately 4% maximum.
The internal voltage divider on the input to the load dump
comparator has a different ratio than the divider used on the
overvoltage comparator. This allows the load dump detect
threshold to be higher than the overvoltage threshold even
though both comparators are monitoring the same low pass
filter output. If the load dump detect threshold is exceeded,
the fault lamp and MOSFET drive outputs are disabled to
protect the MOSFET, field winding and lamp.
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC33143
Advance Information
Dual High-Side Switch
The MC33143 is a dual high-side switch designed for solenoid control in
harsh automotive applications, but is well suited for other environments. The
device can also be used to control small motors and relays as well as
solenoids. The MC33143 incorporates SMARTMOSTM technology, with
CMOS logic, bipolar/MOS analog circuitry, and DMOS power outputs. An
internal charge pump is incorporated for efficient gate enhancement of the
internal high-side power output devices. The outputs are designed to
provide current to low impedance solenoids. The MC33143 provides
individual output fault status reporting along with internal Overcurrent and
Over Temperature protection. The device also has Overvoltage protection,
with automatic recovery, which "globally" disables both outputs for the
duration of an Overvoltage condition. Each output has individual Overcurrent
and Over Temperature shutdown with automatic retry recovery. Outputs are
enabled with a CMOS logic high Signal applied to an input to providing true
logic control. The outputs, when tumed on, provide full supply (battery)
voltage across the solenoid coil.
The MC33143 is packaged in an economical 24 pin surface mount power
package and specified over an operating voltage of 5.5 V :S VPwr < 26 V for
-40°C:s TA:S 125°C.
• Designed to Operate Over Wide Supply Voltages of 5.5 V to 26 V
DUAL HIGH-5IDE
SWITCH
SEMICONDUCTOR
TECHNICAL DATA
• Dual High-Side Outputs Clamped to -10 V for Driving Inductive Loads
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(SOP (16+4+4)L)
• Internal Charge Pump for Enhanced Gate Drive
• Interfaces Directly to a Microcontroller with Parallel Input Control
• Outputs Current Limited to 3.0 A to 6.0 A for Driving Incandescent Loads
• Chip Enable "Sleep Mode" for Power Conservation
• Individual Output Status Reporting
PIN CONNECTIONS
• Fault Interrupt Output for System Interrupt Use
• Output ON or OFF Open Load Detection
• Output Over Temperature Detection and Shutdown with Automatic Retry
• Sustained Current Limit or Immediate Overcurrent Shutdown Output Modes
• Output Short to Ground Detection and Shutdown with Automatic Retry
• Output Short to VPwr Detection
Simplified Application
VDD
~
~_
I+VPwr~
In.
2)
>G
(!l' " OUT1(24);J
IN1 (1)
1N2 (12)
OUT2
STAT1 (13)
MC33143
-,0
(13)~
STAT2 (10)
INT (23)
NOTE:
Gnd (Nole)
This device contains 889 active transistors.
CEN
tNT
STAT1
N/C
VPwr
VPwr
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
VPwr
VPwr
STAT2
GTST
VDD
SFPD
IN2
OUT2
(Top View)
I
i
Pins 5.6,7, B, 17, 1B, 19 and 20 provide electrical ground and healsinking.
MOTOROLA ANALOG IC DEVICE DATA
OUT1
IN1
• Overvoltage Detection and Shutdown
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
=_40° to +125°C
SOP-24L
MC33143DW TA
10-53
MC33143
Figure 1. Simplified Internal Block Diagram
r-----------------------------------,
.
I
VPwr(9,16)
I
I
I
I
I
I
SFPO(14)
INI (1)
L-~--i-_I------11-<>
01JT1 (24)
t---------+--1>-----!!-O STAT1 (3)
VOO(II)
GTST (15) ot----HI-----+H-+
CEN(2)
INT(23)
1N2 (12)
Faun Oetection
• ON/OFF Open Load
: g~~~~~"S'~oS:°rt
I
NOTE:
01JT2 (13)
• Over Temperature
VPwr Overvoltage
•
I
STAT2 (10)
~---~------------------------------~~
Pins 5, 6,.7, 8,17; 18, 19 and 20 should all be grounded so as to provide electrical as well as thermal heatsinking o!the device.
MAXIMUM RATINGS (All voltages are with respect to ground, unless otherwise noted.)
Rating
Symbol
Power Supply Voltage
Steady State Continuous Operation
Negative Transient (Note 1)
Positive Load Dump Transient (Note 2)
VPwr
Logic Supply Voltage Range
Value
Unit
V
26
-1.5
60
VOO
-0.3 to 7.0
V
Logic Supply Current
100
5.0
mA
Input Voltage (Note 3)
Vin
-0.3 to 7.0
V
Output Clamp Voltage
10=-20mA
10=-200mA
VClamp
Output Current Umit (Note 4)
10(Um)
Output Clamp Energy (10 = -1.0 A)
TJ = 25°0
TJ = 125°C
EClamp
ESO (Minimum)
Human Body Model (Note 5)
Machine Model (Note 6)
V
-3.0to-20
-5.5to-20
-3.0to-6.0
A
mJ
300
100
V
HBM
MM
2000
200
Power Dissipation (TA = 25°C) (Note 7)
Po
4.2
W
Operating Temperature (Note 8)
TA
-40 to +125
°C
Operating Junction Temperature
TJ
-40 to +150
°C
Tstg
-5510+150
°C
Tsolder
270
Storage Temperature
Soldering Temperature (for 10 Seconds)
Thermal Resistance
Junction-to-Lead
Junction-to-Ambient
10-54
°C
°C/W
RaJL
RaJA
15
30
NOTES: 1. Negative transient survival capability
for lOOms time duration.
2. Positive transient survival capability
with typical automotive load dump
condHion; 400 ms time constant
decay.
3. All input pins (INI-2, CEN and
SFPD).
. 4. Each output has independent
current IimHing.
5. Perfonned In accordance to HBM;
CZap 100 pF, RZap 1500 06. Perfonned in accordance to MM;
CZap = 100 pF, RZap = a 07. Derate Power Dissipation 33 mWf"C
for temperatures above 25°C.
=
=
8. Ambient temperature is given as a
practical reference; Maximum
junction temperature is the limiting
factor.
9. ESD data available upon request.
MOTOROLA ANALOG IC DEVICE DATA
MC33143
DC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions 9.0 V ,;; VPwr ,;; t 7 V, 4.5 V ,;; VDD 5.5 V,
-40°C';; TL';; 125°C, unless otherwise noted, typical values represent approximate mean at TL = 25°C.)
Characteristic
Symbol
POWER INPUT
VPwr
9.0
-
17
V
IPwr
IPwr(sby)
IPwr(sleep)
0.1
-
7.0
7.0
300
mA
mA
-
4.2
3.9
0.2
Logic Supply Voltage Range
VDD
4.5
-
5.5
V
Logic Supply Current
Both Outputs ON (INl = IN2 = 0.7 x VDD, 101 = 102 = -1.0 A)
IDD
-
0.43
5.0
VPwr(ovsd)
30
33.2
38
V
VPwr(hys)
0.3
0.5
1.5
V
Supply Voltage Range (Operational)
Supply Current (Note 1)
Both Outputs ON
(CEN = INl = IN2 = 0.7 x VDD, 101 = 102 = -1.0 A)
Standby (CEN = 0.7 x VDD, INl = IN2 = 0.3 x VDD, RL = 12 il)
"Sleep State" (CEN = INl = IN2 = 0.3 x VDD, RL = 12 il)
Overvoltage Shutdown (Note 2)
Overvoltage Shutdown Hysteresis
I!A
mA
NOTES: 1. Supply current when both outputs are ON and during standby are measured in the Ground pin while during ·sleep state" is measured In the VPwr pin.
2. Overvoltage Shutdown causes enabled outputs to be forced OFF; Overvoltage fault is immediately reported.
DC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions 9.0 V,;; VPwr ,;; 17 V, 4.5 V ,;; VDD 5.5 V,
-40°C ,;; T L ,;; 125°C, unless otherwise noted, typical values represent approximate mean at T L = 25°C.)
Characteristic
Symbol
Drain-to-Source ON Resistance (Note 1)
(TJ = 25°C, CEN = INl = IN2 = 0.7 x VDD)
10 = -{l.5 A. VPwr = 5.5 V
10 = -1.0 A. VPwr = 14 V
10 = -2.0 A. VPwr = 24 V
RDS(on)
Drain-to-Source ON Resistance (Note 1)
(TJ = 125°C, CEN = INl = IN2 = 0.7 x VDD)
10 = -{l.5 A. VPwr = 5.5 V
10=-1.0 A. VPwr= 14 V
10 = -2.0 A. VPwr = 24 V
RDS(on)
-
1.0
0.38
0.38
Output Self-Limiting Current (Note 2)
(CEN = INl = IN2 = SFPD = 0.7 x VDD, RL = 0 il)
10(Lim)
-3.0
-4.1
-6.0
A
Output OFF Leakage Current
(CEN = 0.7 x VDD, INl = IN2 = 0.3 x VDD)
10(Lkg)
-5.0
-45
-150
I1A
Output OFF Open Load Sense Current
(CEN = 0.7 x VDD, INl = IN2 = 0.3 x VDD)
10(Sense)
-5.0
-45
-150
I!A
POWER OUTPUT
-
-
-
10(On)
Output Clamp Voltage (Note 4)
(CEN = 0.7 x VDD, INl = IN2 = 0.3 x VDD)
10 =-20 mA
10 =-200 mA
VClamp
Over Temperature Shutdown Range (Note 5)
(CEN = INl = IN2 = SFPD = 0.7 x VDD)
0.2
0.14
0.14
0.5
0.2
0.2
il
-
Output ON Open Load Detection Current (Note 3)
(CEN = INl = IN2 = 0.7 x VDD)
TL = -40°C
TL = 125°C
Over Temperature Shutdown Hysteresis (Note 6)
il
-
mA
-2.0
-2.0
-145
-181
-200
-200
V
-9.0
-9.0
-13.2
-13.5
-20
-20
TLim
155
-
185
°C
TLim(hys)
-
-
15
°C
NOTES: 1. ROS(on) applies to OUT!, OUT2 and is independent of output current.
2. Applies to each output; each output has independent self-limiting source current feature; Over Current and Short-to-Ground defined as condition
when output source current exceeds 10(L1m); Oevice ignores Over Current and Short-to-Ground faults from 0 to tss.
3. Applies to each output; tested for by ramping 10 from 0 until STAT S 0.7 x VOO; defined as the condition when 10 is outside of 10(on) current window.
4. Applies to each output; each output has independent dynamic output voltage clamping feature.
S. Applies to each output; each output has independent thermal shutdown; parameter is measured by ramping temperature until enabled output is
disabled; parameter is established by design but is not production tested; thermal fault is immediately reported.
6. Parameter is established by design but is not production tested.
MOTOROLA ANALOG IC DEVICE DATA
10-55
MC33143
DC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions 9.0 V ~ VPwr ~ 17 V, 4.5 V ~ VOO 5.5 V,
-40°C ~ TL ~ 125°C, unless otherwise noted, typical values represent approximate mean at TL 25°C.)
I
Characteristic
I
Symbol
I
=
Min
I
Typ
Max
0.3
Unit
CONTROL INTERFACE
Input Control
Logic High (10 = -0.1 A) (Note 1)
Logic Low (10 = 0) (Note 2)
VIH
V,L
0.7
-
0.56
0.52
Input Logic Voltage Hysteresis (VIH - VIU
Vhys
50
250
500
20
44
100
VOO
Input Pull-Oown Current (0.3 x VOO ~ Yin < 0.7 x VOO) (Nota 3)
lin(pd)
mV
/LA
Chip-Enable Threshold
Logic Low (Note 4)
Lo9!c High (Note 5)
VCEN(IL)
VCEN(lH)
0.5
0.5
0.3
0.7
Chip-Enable Hysteresis (VCEN(IH) - VCEN(IL»
VCEN(hys)
50
150
500
ICEN(pu)
-2.0
-16.8
-40
/LA
VSTAT(low)
-
0.07
0.2
VOO
ISTAT(pu)
-20
-44
-100
Chip-Enable Pull-Up Current (CEN = 0.7 x VOO)
Status Low Voltage (lin = 600 /LA) (Note 6)
Status Pull-Up Current (Note 7)
Interrupt (Note 8)
Logic High
1,.0gicLow
VOO
-
-
0.7
INTh
INTI
-
-
-
-
mV
/LA
VOO
0.3
NOTES: 1. Upper logic threshold voltage applies to IN1, IN2, and SFPO and expressed in VOO units
2. Lower logic threshold vonage applies to IN1, IN2, and SFPO and expressed in VOO untts.
3. Applies to IN1, IN2, and SFPO.
4. Initially have CEN = 0.7 x VOO, Ramp CEN down from VOO until 10 = 0 and note disabling pOint.
5.lnitially h~ve Yin =0.7 x VOO, Ramp CEN up from ground until 10 =0.1 A and note enabling pOint.
6. Applies equalljt..la..SJ1\Tk2-and INT outputs; Measured threshold vonage by applying an 'open' fault to OUT1 or OUT2 while forcing 600 jJA of
current into STAT1-2 or INT.
7. Measured with no faults on OUT1-2. VSTAT = VINT = 0.8 x VOO·
8. The Interrupt output has an intemal active current pull-up.
DC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions 9.0 V ~ VPwr ~ 17 V, 4.5 V ~ VOO 5.5 V,
-40°C ~ TL ~ 125°C, unless otherwise noted, typical values represent approximate mean at TL = 25°C.)
I
Characteristic
I
Symbol
I
Min
I
Typ
Max
Unit
OUTPUT DYNAMICS
Output Short Sense Time (Note 1)
tss
30
54
100
!tS
Output Short Refresh .TIme (Note 2)
tref
3.0
4.1
6.0
ms
Ios(on)
3.0
6.4
12·
ms
-
7.2
40
50
75
0.2
0.2
11
2.6
10
10
Output Open Sense ON TIme (Note 3)
Output Propagation Oelay
Turn-On (Output Low to High) (Note 4)
Turn-Off (Output High to Low) (Note 5)
tdlh
idhl
Output Slew Rate
Output Rising (Note 6)
Output Falling (Note 7)
SR r
SRf
Ils
V/IlS
NOTES: 1. CEN =0.7 x Voo. SFPO = 0.3 x Voo, RL =0, Step Y'n from 0.3 x VDDlo 0.7 x VOO; Sense lime measured from step until STAT = 0.2 x VOO.
2. CEN =INI =IN2 =0.7 x VOO, RL =0; Refresh lime measured from output disable until output is re-enabled.
3. RL = "open', Step Yin from ground to 0.7 x VOO, Open sense time measured from step unlil VSTAT'; 0.2 x VOO.
4. RL =12 n. CL =0.01 ILF. slep Yin from V,L 10 V,H; Turn-On propagation measured from Yin
=0.5 x VOO until Vout =2.0 V (see Figure 2).
5. RL =12 f.l, CL =0.01 ILF, step Yin from VIH to V,L; Turn-Oll propagation measured from Vout =VPwr -3.0 V until Vout = 2.0 V (see Figure 2).
6. RL = 12 f.l, CL = 0.01 ILF, slep Yin from VIL to V,H; Output Slew Rate measured from 2.0 V to VPwr - 3.0 V (see Figure 2).
7. RL = 12 f.l, .CL;= O.OIILF, slep Yin from V,H to VIL; Output Slew Rate measured from VPwr- 3.0 V to 2.0 V (see Figure 2).
10-56
MOTOROLA ANALOG IC DEVICE DATA
MC33143
Figure 2. Output Response Waveform
INl-2
OV
VPwr
OUTl-2
r--
I
VPwr- 3.OV"
"
oV_....::.2;::...OV:.....7j,tSRr - :
,
k-Idhl
,----""'"
,,
-t-----t:--
-1
r-
tsRf
PIN FUNCTION DESCRIPTION
Pin
1,12
Symbol
Description
IN1,IN2
INput 1 and INput 2 (INI and IN2) respectively determine the state of the corresponding output drivers
(OUTI and OUT2) under normal operating conditions. When an input is high, it's corresponding output
is active ON, and when low is disabled OFF. INI and IN2 have internal active pull-downs which allow a
floating input pin to be conservatively interpreted as a logic low, turning Off the output. An unused input
should be connected to ground.
CEN
Chip Enable (CEN) input pin, when low, disables both outputs (OUTI and OUT2) and places the device
in a "sleep mode" reducing the bias current required from VDD and VPwr. A falling edge of CEN causes
OUTI and OUT2 to rapidly turn OFF. A falling edge of CEN should precede any VDD shutdown to allow
time OUTI and OUT2 to be disabled. When CEN is low, INTerrupt (INT) and STATus 1 and 2 (STATI-2)
will be tri-stated (high impedance). The CEN pin can also be used for power-on reset and under
voltage lockout to disable the outputs for power supply vo~ages less than 4.5 V. CEN is a dependent
input from the system microcontroller unit (MCU) or some other integrated circuit. It has an internal
pull-up resistor to VDD affording a floating pin to be interpreted as a logic high. Rpull-up is greater than
50 kn. " used externally, this pin should be connected to VDD.
STAT1. STAT2
The STATus pins (STATI-2) respectively indicate the presence of faults on OUTI-2. STATI-2 will be
logic high during normal operation. A logic low will occur whenever an Open Load, Short-to-Ground,
Short-to-Supply (Battery), Thermal Limit, or Overvoltage Shutdown fau~ condition is experienced on a
corresponding output. STATI-2 are both active low digital drivers. A 10 kQ resistor between STATI-2
and the system CPU may improve a Failure Mode Evaluation Analysis (FMEA) score if STATI-2 are
externally shorted to VPwr. " unused, this pin should be left connected.
4,9,16,
21
VPwr
These pins are connected to the supply and provide load current to the DMOS outputs, are used
pumping the DMOS gates, and for Overvoitage shutdown detection of the DMOS. The DMOS outputs
will turn ON with 5.5 to 24 V applied to VPwr. VPwr is limited to -1.5 V for a maximum duration of
250 ms. A 10 nF de-coupling cap is recommended to be used from VPwr to Ground.
5,6,7,8,
17,18,
19,20
Gnd
These eight pins constitute the circuits ground (Gnd) and also provide heatsinking for the DMOS output
transistors. Ground continuity is required for the outputs2 to tum ON.
11
VDD
This pin is to be connected to the 5.0 V logic supply of the system. A 10 nF de-coupling capacitor is
recommended from VDD to Gnd.
OUT1,OUT2
These pins are connected internally to the DMOS output transistors which source current into the
corresponding load. Each output incorporates dynamic clamping to accommodate inductive loads. In
addition, each output has independent short to ground detection and protection, current limit detection
and protection, thermal limit detection and protection, ON open load and or short to supply (battery)
detection. Neither output will turn ON if CEN is logic low. An unused output should be connected to a
10 kQ load to prevent false fault reporting. A 1.0 nF filter capacitor may be used from OUT to Gnd to
provide dVldt noise filtering.
2
3, 10
13,24
MOTOROLA ANALOG IC DEVICE DATA
10-57
MC33143
PIN FUNCTION DESCRIPTION (continued)
Pin
Symbol
Description
14
SFPD
This is a Short Fault Protect Disable (SFPD) input; which when logic high disables the internal current
limit timer preventing OUTl-2 from latching OFF when confronted with an overcurrent condition. The
condition of SFPD does not affect fault reporting. Current and thermallimil remain active when the
SFPD pin is logic high. Having the SFPD pin logic high facilitates the device to drive incandescent lamp
loads with peak, in-rush currents in excess of three amperes. When SFPD is logic low, an overcurrent
demand will latch OFF only the output affected. The device will then automatically begin active
re-enabling of the corresponding output affected for the duration of the overcurrent condition. SFPD has
an internal active pull-down which affords a floating input pin condition to be conservatively interpreted
as a logic low. A 10 k.Q resistor between SFPD and the system CPU may improve the FMEA score if
SFPD is externally shorted to OUT2. SFPD should be connected to Gnd or VDD for the desired
operating mode and not be left '110ating".
15
GTST
The Gate TeST (GTST) pin is used to str~ss the devices DMOS gates during testing operations. This pin
should normally be connected to ground in the application.
23
INT
The INTerrupt pin INT is active logic low and indicates the presence of a fault on either the output. INT
can be paralleled with additional fault pins and used as a system CPU interrupt to indicate the presence
of a fault. The system CPU can then read STATl-2 to determine the specific type of fault occurring. INT
will be logic high during normal operation. A logic low will result if a fault occurs on either OUT1 or
OUT2. INT has an internal active pull-up and requires no external pull-up resistor to be used. The INT
output has sufficient current drive capability to afford paralleling of up to five INT pins. A 10 kQ resistor
between INT and the system CPU may improve the FMEA score if INT is extern~IIy shorted to OUT1.
This pin should be left unconnected if the feature is not used.
Figure 3. Function Table
Device Condition
Normal
Output to Gnd Short
Open Load
Output to VPwr
Short
Over Temperature
VPwr Overvoltage
"Sleep"/Under
Voltage Mode,
CENLow
10-58
In
Out
STAT
Low
High
Low
High
High
High
Output Condition
STAT Condition
Normal OFF
Normal ON
Normal
Normal
Low
Low
High
Normal OFF
Normal
High
HighlLow
Low
Output in active retry mode.
Normal ON when short is
removed.
Short fault reported. Fault
clears when short is removed.
Low
High
LoV'(
Normal OFF
"OFF" open fault reported. Fault
clears when load is connected.
High
High
Low
Normal ON
"ON" open fault reported. Fault
clears when load is connected.
Low
High
Low
Normal OFF
"OFF" open fault reported. Fault
clears when short is removed.
High
High
Low
Normal ON
"ON" open fault reported. Fault
clears when short is removed.
Low
Low
Low
Normal OFF
Thermal fault reported. Fault
clears with no thermal limit.
High
Low
Low
Output disabled. Output Retries
with no thermal limit.
Thermal fault reported. IN low
and no thermal limit required to
clear the fault.
Low
Low
Low
Normal OFF
Overvoltage fault reported.
Fault clears with no
overvoltage.
High
Low
Low
Output disabled. Will reset with
no overvoltage.
Overvoltage fault reported.
Fault clears with no
overvoltage.
Low
Low
High-Z
Output disabled.
STAT tri-stated, no faults
reported.
High
Low
High-Z
Output disabled.
STAT tri-stated, no faults
reported.
MOTOROLA ANALOG IC DEVICE DATA
MC33143
FUNCTIONAL DESCRIPTION
General
The MC33143 is designed as an interface device;
between system's electronic control unit and the actuators. It
is designed to withstand several abnormal operating
conditions, with the capability of reporting it's operating status
back to the control unit. The MC33143 will resume normal
operation aiter having experienced 60 V transients on the
VPwr line, output shorts to VPwr, open loads, output shorts to
ground, over current, over temperature, or overvoltage
conditions. Status information is available when ever a load
experiences any of the faults. In addition, the MC33143
device incorporates intemal output transient clamps allowing
it to control inductive loads and survive negative voltage
spikes without the need of external components.
Power Supply Voltage Requirements
The MC33143 is designed to operate with 5.5 V to 26 V
applied to the power supply pin (VPwr) and 4.5 V to 5.5 V
applied to the logic supply pin (VDD). If VPwr is above the
specified Overvoltage Shutdown voltage limit (VPwr(ovsd»
the outputs will be disabled and the status line voltage will
transition to a low logic state indicating a fault.
When the CEN voltage is at a low logic state, OUTl and
OUT2 will turn OFF. This provides an under voltage
shutdown for VPwr in the 0 to 4.5 V range. The active low
under voltage must be externally provided to the CEN pin.
The MC33143 is designed to survive the loss of VPwr.
Normal Operations
The MC33143 is considered to be operating normal when
the following conditions are met:
8) 5.5 V :5 VPwr :5 26 V.
9) -40°C :5 TJ :5 150°C.
10) When load currents (10) exceed the Output Open
"ON" detection current (IO(on» and occur within the
Open Sense "ON" time (tos(on» window.
11) When load currents (10) are less than the Output Limit
Current (IO(Lim» for durations in excess of the Short
Sense time (ts s).
12) So long as the output of the device is able to clamp
negative voltages produced when switching inductive
loads to the specified clamp voltage (VClamp).
Fault Conditions
Anytime the MC33143 is not operating normal it is said to
be operating in a "faulted condition". Fault conditions will
result in level changes of the status outputs (STATl-2) and
disable the affected faulted output.
Output Over Current/Short to Ground Faults
For an enabled input, the status line voltage will transition
to a low logic level if the output current equals or exceeds the
Output Limit current (lO(Lim» for a period of time in excess of
the Short Sense time (tss ). Only the affected output will turn
off; independent of the corresponding input's condition. The
device incorporates an internal short duration Refresh timer
MOTOROLA ANALOG IC DEVICE DATA
(tref) to mask edge transients due to switching noise. The
output will remain off for the short tref duration and then
attempt to re-energize the shorted load. The internal
protection circuitry continues to be active during this
process. If the short is not removed; the circuitry will
sequence and the output will remain off for a another tref
time. This process will continue so long as the output
remains shorted and the input remains in a logic high state. If
the short is removed from the output, while the input is ON,
the MC33143 will return to normal operation and the status
line will go to a logic high state aiter the tref time--~
~._.__4o__~~
Ground
Ceramic
Resonator
MI-8us
From MCU
- - - - - - - - - - - - - - - - - MI-8us
ORDERING INFORMATION·
Operating
Temperature Range
Package
MC33192DW TA = - 40' to +1OO'C
SO-t6l
Device
This device contains 1,528 active transistors.
10-60
MOTOROLA ANALO(3 IC DEVICE DATA
MC33192
MAXIMUM RATINGS (All voltages are with respect to ground, unless otherwise noted.)
Rating
Symbol
Value
VCC
VLD
25
40
Power Supply Voltage
Continuous Operation
Transient Survival (Note 1)
Limit
V
Vi
0.3 to VCC + 0.3
V
Output Current (TA = - 40°C)
10LT
260
mA
Output Current (TA = 100°C)
10HT
150
mA
Tstg
-40to+150
°C
TA
-40to+125
°C
Junction Temperature
TJ
-40to+150
°C
Power Dissipation (TA = 100°C)
PD
0.5
W
VLD
40
V
Digital Input Voltage
Storage Temperature
Operating Temperature (Note 2)
Load Dump Transient (Note 3)
DC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions 9.0 V S VCC S 15.5 V, - 40°C S TA S 100°C,
unless otherwise noted.)
Characteristic
Standby Current (VCC = 15.5 V) (Note 4)
Symbol
Min
Typ
Max
Un"
10
-
-
12
rnA
10
-
120
-
rnA
H-Bridge Saturation Voltage (10 = 150 mAl (Note 5)
TA=-40°C
TA=25°C
TA = 100°C
VO(sat)
-
-
V
-
-
1.3
1.2
1.1
1.6
1.6
1.6
Address Programming Current (TA = 25°C) (Note 6)
Ipc
-
1.2
-
Output Current (VCC '" 15.5 V)
A
CONTROL LOGIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions 9.0 V S VCC S 15.5 V, - 40°C S TA S
100°C, unless otherwise noted.)
Typ
Max
Unit
640
-
kHz
24.8
25
25.2
IlS
too
9xts
-
-
IlS
Internal MI Bus Pull Up Resistor
Rpu
6.0
20
kQ
Internal MI-Bus Zener Diode Clamp Voltage
Vel
-
18
-
V
Vp
10
12
14
V
Program Energize lime
Ippw
200
MI-Bus Slew Rate
flY!At
1.0
Characteristic
Symbol
Oscillator (Note 7)
fel
Message lime Slot (VCC = 12 V) (Note 8)
ts
Urgent Output Disable (VCC = 12 V) (Note 9)
Address Programming Voltage (Note 10)
Min
MI-Bus "0" Level Input Voltage Threshold
Vii
-
MI-Bus "1" Level Input Voltage Threshold
Vih
2.4
MI-Bus "0" Level Output Voltage (10 = 30 mAl
VOL
Power-On Reset Time (VCC;'" 7.5 V)
tpor
1000
IlS
1.5
2.0
V!1lS
V
-
1.3
-
V
-
-
1.0
V
-
250
-
fls
NOTES: 1. Transient capability is defined as the positive overvoltage transient wnh 250 ms decay time constant. The detection on an overvoltage condition causes all
H-Bridges to be latched ·olr'.
2. Ambient temperature is given as a convience; Maximum junction temperature is the limiting factor.
3. Load Dump is the inductive transient voltage imposed on an automotive battery line as a result of opening the battery connection while the alternator
system is producing charge current. The detection on an overvoHage condition causes all H-Bridges to be latched ·olr'.
4. Standby Current is with both H-Brtdges ·off' (Inh1 = Inh2 = 0).
5. H-Brtdge Saturation VeHage is referenced to the positive supply or ground respective of the H-Brtdge output being High or Low.
Saturation voHage is the 'voltage drop from the output to the positive supply (with output High) and the voltage drop to ground (wnh output LOW).
6. Address Programming Current is the current encountered when the bus is at 12 V during address programming.
7. A typical application uses an external ceramic resonator crystal having a frequency of 644 kHz. An internal capacitor in parallel with ceramic resonator is
used to shift the frequency to the working frequency of 640 kHz. The frequency accuracy of the oscillator is dependant on the capaCitor and ceramic
resonator tolerance (usually ±1.0%).
8. The Message Time Slot is the time required for one complete device message transfer. The message time is equivalent to a total of 16 pertods of the
oscillator frequency used.
9. If the MI-Bus becomes shorted to ground, all MC33192 outputs will be disabled after a period of nine time slots (9ts)'
10. MI-Bus voltage required for address programming.
MOTOROLA ANALOG IC DEVICE DATA
1G-61
I~
MC33192
GENERAL DESCRIPTION
The MC33192 is a serial stepper motor controller for use in
harsh automotive applications using multiplex wiring. The
MC33192 provides all the necessary four phase drive signals
to control two phase bipolar stepper motors operated in either
half or full step modes. Multiple stepper motor controllers can
be operated on a real time basis at step frequencies up to
200 Hz using a single microcontroller (MCU). A primary
attribute of operation is the utilization of the MI-Bus message
media to provide high noise immunity communication
ensuring very high operating reliability of motor stepping.
The MC33192 is designed to drive bipolar stepper motors
having a winding resistance of 80 Q at 20°C with a supply
voltage of 12 V. It is supplied in a S0-16L plastiC package
having eight pins, on one side, connected directly to the lead
frame thus enhancing the thermal performance to allow a
power diSSipation of 0.5 W at 120°C ambient temperature.
Multiple Simultaneous Motor Operation
Several motors can be controlled in a serial fashion, one
after the other, using the same software time base. The time
base determines the step frequency of the motors. A single
motor can be operated at a maximum speed of 200 Hz
pull-in with a duration of 5.0 ms per step. Three motors can
be operated simultaneously using a 68HC05B6 MCU at the
same time base (200 Hz) with about 1.7 ms per step. A
68HC11 MCU can control 4 stepper motors with adequate
program step time. The step frequency must be decreased to
control additional motors. To control eight motors
simultaneously would require the motor speed to be
decreased to 100 Hz produCing about 2.0 ms time duration
per step with adequate program time.
MI-Bus General Description
The Motorola Interconnect Bus (MI-Bus) is a serial
push-pull communications protocol which efficiently
supports distributed real time control while exhibiting a high
level of noise immunity.
Under the SAE Vehicle Network categories, the MI-Bus is
a Class A bus with a data stream transfer bit rate in excess of
20 kHz and thus inaudible to the human ear. It requires a
single wire to carry the control data between the master MCU
and its slave devices. The bus can be operated at lengths up
to 15 meters.
At 20 kHz the time slot used to construct the message
(25 (.1s) can be handled by software using many MCUs
available on the market.
The MI-Bus is suitable for medium speed networks
requiring very low cost multiplex wiring. Aside from ground,
the MI-Bus requires only one signal wire connecting the
MCU to multiple slave MC33192 devices with individual
control.
A single MI-Bus can accomplish simultaneous automotive
system control of Air Conditioning, Head Lamp Levellers,
Window Lifts, Sensors, Intelligent Coil Drivers, etc. The
MI-Bus has been fpund to be cost effective in vehicle body
electronics by replacing the conventional wiring harness.
Figure 1 shows the internal block diagram of the MC33192
Stepper Motor Controller.
Figure 1. MC33192 Stepper Motor Con roller Block Diagram
r-------------------------------------,1
Xtal (8)0+--..--1
1
5.0V
1
1
1
Noise Detector
Bi-Phase
Bi-Phase Program
,----,1
10k
Programming
Level Detection
5.0 V
+VCC(7)
Control
Logic
-=
Latch
All (3)
AI2(4)
Dual Bridge Driver and
Motor Diagnostics
Bll (5)
BI2(6)
1
1
1
1
1
1
1
1
~
- Encoder
1
_____________________________________ J1
NOTE: (0) Pins 2, 9, 1D, II, 12, 13, 14, 15 and 16 are common electrical and heatsink ground pins for the device.
10-&2
MOTOROLA ANALOG IC DEVICE DATA
MC33192
MI-Bus Access Method
The information on the MI-Bus is sent in a fixed message
frame format (See Figure 4). The system MCU can take
control of the MI-Bus at any time with a start bit which
violates the law of Manchester Bi-Phase code by having
three consecutive Time Slots (3ts) held constantly at a Logic
"0" state.
Push-Pull Communication Sequence
Communication between the system MCU and slave
MC33192 devices always use the same message frame
organization. The MCU first sends eight serial data bits over
the MI-Bus comprised of five control bits followed by three
address bits. This communication sequence is called a "Push
Field" since it represents command information sent from the
MCU. The sequence of the five control data bits follow the
order DO, D1, D2, D3 and D4. The three address bits are sent
in sequential order AO, A1 and A2 defining a binary address
code. The condition of MI-Bus during any of the control bit
time windows defines a specific control function as shown in
Figure 2. A "Pull Sync" bit is sent at the end of the Push Field,
the positive edge of which causes all data sent to the
selected device to be latched into the output circuit.
Figure 2. Push Field Data Bits
Bit
Name
04
Inh2
Inhibits H-Bridge 2
Control Function
03
Dir2
Establishes Direction of H-Bridge 2 Current
02
E
Energizes Bridge Coils 1 and 2
D1
Dir1
Establishes Direction of H-Bridge 1 Current
DO
Inh1
Inhibits H-Bridge 1
After the Pull Sync bit is sent, following the Push Field, the
MCU listens on the MI-Bus for serial data bits sent back from
the previously addressed MC33192 device. This portion of
the communication sequence starts the "Pull Field Data"
since it represents information pulled from the addressed
MC33192 and received by the MCU.
The address selected MC33192 device sends data, in
the form of status bits, back to the MCU reporting the
devices condition. At the end of the Push Field the MCU
outputs a Pull Sync bit which signals the start of the Pull
Field. In the Pull Field are three bits (S2, S1 and SO) which
report the status of the previously addressed MC331 92
according to Figure 3.
Figure 3. Pull Field Status Bits
S2
S1
SO
0
0
0
Status
Comments
0
0
1
Free
0
1
0
No Back EMF
0
1
1
Free
1
0
0
Normal/OK
1
0
1
Thermal
1
1
0
Programming
PROM energized
1
1
1
Selection failed
Noise on MI-Bus, failed or
disconnected module
Not used
Drivers and/or coils failed
Chip temperature> 150'C
The positive edge of the Pull Sync pulse (set by the MCU)
causes all Push Field Data sent to the selected MC33192 to
be stored in the output latch circuit in time with the strobe
pulse. This means the data bits are emitted in real time
synchronization with the MCU's machine cycle. The strobe
pulse occurs only after the Push Field sequence is validated
by the address selected device.
Message Validation
The communication between the MCU and the selected
MC33192 device is valid only when the MCU reads
(receives) the Pull Field Data having the correct codes
(excluding the code "1-1-1" and "0-0-0") followed by an
End-af-Frame signal. The frequency of the End-of-Frame
signal may be a sub-multiple of the selected devices local
oscillator or related to an internal or external analog
parameter using a Voltage to Frequency Converter.
Error Detection
An error is detected when the Pull Field contains the code
"1-1-1" followed by the End-ai-Frame permanently tied to a
logic "1" state (internally from 5.0 V through a pull-up
resistor). This means the communication between the MCU
and the selected device was not obtained.
Figure 4. MI-Bus Timing Diagram
Frame
I"
1
I"
Push Field
1
~I
I
-I
..
3ts
1
1 Start
1
1
1
1 75/ls
I"
Pull Field
Push Sync
Data
Address:
Data
End-ol-Frame
""f--••+-I..f----------*"I------~.I 1 I"
.1"
.1
I
I
1
1
1
I
1
1
MI-BusWire
-I
1
• ..
1i-v-v-v-v-v-IT""'I7"""1:T'"1n~~,.-,:Xr"'llXr"'llX~\ I UXJ \..F.\..F~
11 1
1
1 112 1 31 41
'\
1
1
1
1
1
1
1"1""0'
A1 A2 1"0"'1,ls2 Sl sol
Start 1
1
1
1 NRZ 1
1
1
1
1 Coded ,
Oscillator
,
1
Pull Sync - , - - - ,
1
Frequency
,
1
100j.lS'
+32=20kHz
1
C\
-I"
1
Push/Pull Function - - - - . . ,
-'"
1
-,
,
r-1-------pu-II-..,;~~'''-----iL
n
Strobe Pulse
Strobe - - - - - - - - - - - - - - - - - - - - - - -....I~-------...,.",.~
MOTOROLA ANALOG IC DEVICE DATA
..., ______
10-63
MC33192
There are four types of system error detections which are
not mutually exclusive; These are:
1) Noise Detection
The system MC33192 slave devices receive the Push
Field message from the MCU twice for each lime Slot (ts)
of the Bi-Phase Code. A receive error occurs when the two
message samples fail to "logic wise" match. Noise and
Bi-Phase detection are discussed further under Message
Coding.
2) Bi-Phase Detection
The system slave devices receiving the Push Field
message from the MCU detect the Bi-Phase Code. A
detector error occurs when the two time slots of the Bi-Phase
Code do not contain an Exclusive-OR logic function.
3) Field Check
A field error is detected when a fixed-form bit field
contains an improper number of bits. A bit error can also be
detected by the MCU during the Push Field. The MCU can
simultaneously monitor the MI-Bus at the time it is sending
data. A bit error is detected if the sent bit value does not
match the value which was monitored.
4) Urgent Output Disable
If the MI-Bus becomes shorted to ground, the slave
device outputs will be disabled after a period of 9ts. The MCU
itself can take advantage of this feature to "globally" disable
the outputs of all system slave devices by keeping the
MI-Bus at a logic "0" level for a duration of 9ts or more.
Normal operation is resumed when the MCU sends a
"standard" instruction over the MI-Bus.
Basic Stepper Motor Construction and Operation
Stepper motors are constructed with a permanent magnet
rotor magnetized with the same number of pole pairs as
contained in one stator coil section. Operationally, stepper
motors rotate at constant incremental angles by stepping one
step every time the current switches discretely in one stator
field coil causing the North-South stator field to rotate either
clockwise or counter-elockwise causing the permanent
magnet rotor to follow (see Figure 5). For simplicity, assume
the starting condition of the A 1 to A2 stator field to be top to
bottom polarized N to S and the B1 to B2 stator field to be left
to right polarized N to S. The resulting stator field will produce
a vector which points in the direction of position 3. The rotor
will, in this case, be in the pOSition shown in Figure 5 (pointing
to position 1). This initial condition corresponds to that of
step 1 in Figure 6. As the direction of current flow in the B1 to
B2 stator field is reversed, the field polarity of the B1 to B2
also reverses and is left to right polarized S to N. This causes
the resulting stator field vector to point in the direction of
position 4. This in turn causes the N-S rotor to follow and
rotate 90° in a clockwise direction and point in the direction of
pOSition 2. This condition corresponds to step 2 of Figure 6.
Continued clockwise rotor steps will be experienced as the
stator field continues to be incrementally rotated as shown in
steps 3, 4, 5, etc. of Figure 6. The 90° steps in this simplistic
example constitute "full steps". It is to be noticed that both
coils, in the foregoing full step example, were simultaneously
energized in one of two directions. It is possible to increment
the rotor in 45° "intermediate steps" or "half steps· by
alternately energizing only one stator coil at a time in the
appropriate direction while turning the other stator coil off.
The drive signals for Half Step operation are shown in
11H14
Figure 7. The Power output stages of the MC33192 consist
of two H-Bridges capable of driving two--phase bi-polar
permanent magnet motors in either half or full step
increment.
Figure 5. Permanent Magnet Stepper Motor
AI
B1D--+---i
H+--oB2
A2
Figure 6. 4-Step "Full Step" Operation
Step
2
1
5
4
3
6
CoilA +
(AI toA2)
CoilB +
(Bl toB2)
~
~
Stator
Field
/
/
/
/
/
/
" " "
" " "
Rotor
Position
Rotor
Direction
CCW·
.. CW
Figure 7. 8-Step "Half Step" Operation
Step
CoilA
(AI toA2)
CoilB
(Bl toB2)
Stator
Field
Rotor
POSition
Rotor
Direction
1
2
3
4
5
6
7
8
1
r-
+
+- r -
-
/ " / "t/ -"
"
t/
"
+
CCW·
+
I-
"
• CW
MOTOROLA ANALOG IC DEVICE DATA
MC33192
Permanent magnetic stepping motors exhibit the
characteristic ability to hold a shaft rotor position with or
without a stator coil being energized. Normally the shaft
holding ability of the motor with a stator coil energized is
referred to as "Holding Torque" while "Residual Torque" or
"Detent Torque" refers to the shaft holding ability when a
stator coil is not energized. The Holding Torque value is
dependent on the interactive magnetic force created by the
resulting energized stator fields with that of the permanent
magnet rotor. The Residual Torque is a function of the
physical size and composition of the permanent magnet rotor
material coupled with its intrinsic magnetic attraction for the
un-energized stator core material and as a result, the weaker
of the two torques.
It is to be noted when using half step operation, only one
coil is energized during alternate step periods which
produces a somewhat weaker Holding Torque. Holding
Torque is maximized when both coils are simultaneously
energized. In addition, since each winding and resulting flux
conditions are not perfectly matched for each half step,
incremental accuracy is not as good as when full stepping.
Two Phase Drive Signals
The DIR1 and DIR2 bits in the Data Frame of the Push
Field determine the direction of H-Bridge current flow, and
thus the magnetic field polarization of the stator coils, for
H-Bridge outputs "A" and "B" respectively. The directional
signals DIR1 and DIR2, generated by the MCU,
communicate over the MI-Bus to control the two H-Bridge
power output stages of the MC33192 to drive two phase
bipolar permanent magnet motors. Figure 8 shows the
MC33192 truth table to accomplish incremental stepping of
the motor in a clockwise or counter-clockwise direction in
either half or full step modes. The stator field polarization and
rotor position are also shown for reference relative to the
basic stepper motor of Figure 5.
Figure 8. Truth Table and Serial Push Field Data Bits For Sequential Stepping
Push Field Bits
Step
DO
Dl
D2
D3
D4
H-Bridge Outputs
Full
Half
Inhl
DIRl
E
DIR2
Inh2
Al
A2
Bl
B2
1
1
1
0
1
0
1
1
0
1
0
-
2
1
0
1
X
0
1
0
Z
Z
2
3
1
0
1
1
1
1
0
0
1
-
4
0
X
1
1
1
Z
Z
0
1
3
5
1
1
1
1
1
0
1
0
1
-
6
1
1
1
X
0
0
1
0
0
4
7
1
1
1
0
1
0
1
1
0
-
8
0
X
1
0
1
Z
Z
1
0
0
X
X
X
0
Z
Z
Z
Z
1
1
0
1
1
Z
1
Z
1
1
0
0
0
1
1
Z
1
Z
1
1
0
0
0
Z
1
Z
Z
0
0
0
1
1
Z
Z
Z
1
Stator
Field
(Note 2)
Rotor
PosRion
(Note 2)
"-
""~
/
/
t
Direction
of Shaft
Rotation
-- """/~ /t
- --
ccw
cw
NOTES: 1. X = Don't care; Z = High impedance; 1 = High (active 'on") state; 0 = Low (Inactive 'off") state.
2. The stator field direction and position of the rotor are shown for explanation purposes and relative to the basic
stepper motor shown in Figure 3.
3. DIR1 establishes the direction of current flow in H-Bridge "A".
4. DIR2 establishes the direction of current flow in H-Bridge 'B".
MOTOROLA ANALOG IC DEVICE DATA
10-65
MC33192.·
MI-Bus Interface Description
The MI-Bus Interface shown in Figure 9 is made up of a
single NPN transistor (01). The two main functions of this
NPN transistor are:
1) To drive the MI-Bus during the Push Field with
approximately 20 mA of current while also exhibiting low
saturation characteristics (VCE(sat».
2) To protect the Input/Output (I/O) pin of the MCU against
any: Electro-Magnetic Interference (EMI) captured on the
bus wire.
Without the NPN transistor, the MCU could be destroyed
as a result of receiving excessive EMI energy present on the
bus. In addition, the transistor blocks the MCU from receiving
EMI signals which could erroneously change the data
direction register of the MCU I/O.
The MCU input pin (Pin), used to read the Pull Field of the
MI-Bus, is protected by two diodes (D2 and D3) and two
resistors (R5 and R6). Any transient EMI generated voltage
present on the bus is clamped by the two diodes to a
windowed voltage value not to be greater than the VDD or
less than the VSS supply voltages of ttie MCU.
MI-Bus Levels
The MI-Bus can have one of two valid logic states,
recessive or dominant. The recessive state corresponds io a
Logic "1" and is obtained through use of a 10 kQ pull-up
resistor (R9) to 5.0 V. The dominant state corresponds to a
Logic "0" which represents a voltage less than 0.3 V and
created by the VCE(s/it) of 01.
MI-Bus Overvoltage Protection
An external zener diode (Z1) is incorporated in the
interface circuit so as to protect the MCU output pin (Pout>
from overvoltages commonly encountered in automotive
applications as a result of "Load Dump" and "Jump Start"
conditions. Load Dump is defined as the inductive transient
generated on the battery line as a result of opening the
battery connection while the alternator system is producing
charge current. Jump Start overvoltages are the result of
paralleling the installed automotive battery, through the use
of "jumper cables", to an external voltage source in excess
of the· vehicles nominal system voltage. For 12 V
automotive systems, it is common for 24 V "jump start"
voltages to be used.
When an overvoltage situation (>18 V) exists, due to a
load dump or jump start condition, the zener diode (Z1) is
activated and supplies base current to turn on the NPN
transistor 01 causing the bus to be pulled to less than 0.3 V
producing a Logic "0" on the MI-Bus. After a duration
corresponding to 8ts (200 I!s) of continuous Logic "0" on the
bus all MC33192 devices will disable their outputs. Normal
operation is resumed, following the overvoltage, by the MCU
sending out a "standard" message instruction.
MI-Bus Termination Network
The MI-Bus is resistively loaded according to the number
of MC33192 devices installed on the bus. Each MC33192
has an internal 10 kQ pull-up resistor to 5.0 V. An external
pull-up resistor (R7) is recommended to be used to optimally
adjust termination of the bus for a load resistance of 600 Q.
Figure 9. MI-Bus MCU Interface
12V
Program
7
r ----------MC33192
VCC
S.OV
s.OV
r-
--,
Run
Z1
(18V)
I VDD I
R1
(4.7K)
I
I
R3
I
I
(3.9k)
I
Pout !-O---*.....+-......~W'v-~
I
I
D1
R4
(10 k)
I MCU I
VDD
I
I
I
I
D2
I
I
IL. _VSS
Pin k>---AN\,.--t---'V'V'v-----'
_ _ .J
D3
R6
(22k)
lin
-f
TR7
(1.2k)
1
1
1
1
S.OV
Programming
11
MI-Bus
Data In
#2
#3
#4
#5
#6
#7
#8
Additional MC33192 Devices
OV
10-66
MOTOROLA ANALOG IC DEVICE PATA
MC33192
MESSAGE CODING
Bi-Phase Coding and Detection
The Manchester Bi-Phase code shown in Figure 10
requires two time slots (2ts) to encode a single data bil. This
allows detection of a single error at the time slot level. The
logic levels "1" or "0" are determined by the organization of
the two time slots. These always have complementary logic
levels of either zero volts or plus five volts, which are
detected using an Exclusive OR detection circuit during the
Push Field sequence. A "1" bit is detected when the first time
slot is set to a zero logic state (0 V) followed by the second
time slot set to a logic state one (5.0 V). Conversely, a "0" bit
is detected when the first time slot is set to the logic state
"one" (5.0 V) followed by a second time slot set to a "zero"
logic state (0 V). For these two bits are Exclusive-0Rs of
each other.
The addressed devices receiving the Push Field detect
the Bi-Phase code. Bi-Phase detection involves the
sampling of the Push Field Bi-Phase code twice (a and b) for
each time slol. A code error occurs when the two time slots of
the Bi-Phase do not follow a logical Exclusive-QR function
(see Figure 10).
Noise monitoring is accomplished by sampling the Push
Field Bi-Phase code twice (a and a') and (b and b') during
each time sial. A noise error is detected if the two sample
values do not have the same logical level.
Figure 10. NoiselBi-Phase Detection
2ts
---
5.0 V
Push Field
Bi-Phase
Coded Bits
(L09:~ "O"~
I
ts
_
(Logic "1")
I
I
-o1 2 3 4 5 6
a
t
I
7
b
t
o1
'-
__ t
2 345 6 7
a
b
t
t
VV U
Bi-Phase
Detection
Noise
Detection
Each message frame consists of two fields: The Push
Field, in which data and addresses are transferred by the
MCU to the slave device; and the Pull Field, in which serial
data is transferred back to the MCU from the address
selected slave device. The message frame is broken down
into seven individual field segments as indicated in Figure 4
(Start, Push Field Sync, Push Field Data, Push Field
Address, Pull Field Sync, Pull Field Data, and
End-of-Frame). The following lists the bit size and function
of each of these segments:
1) Start is the start of message and consists of three time
slots (3ts) having the dominant Logic "0" state of less than
0.3 V. Holding the MI-Bus at ground for three time slots (3ts)
marks the beginning of the message frame by violating the
law of the Manchester Code.
MOTOROLA ANALOG Ie DEVICE DATA
2) Push Field Sync is a single bit which establishes initial
timing for the Push Field Data to follow.
3) Push Field Data is comprised of five serial data bit
fields (DO, 01, 02, 03 and 04) which comprise the instruction
set defining the configuration and condition of the two
H-Bridge output stages.
4) Push Field Address is comprised of three serial data
bit fields (AO, A 1 and A2) which define the address or name
of a MC33192 on the MI-Bus.
5) Pull Field Sync is a single bit which establishes the end
of the Push Field and the initial start timing for the Pull Field
Data to follow.
6) Pull Field Data is made up of three serial data bit fields
(S2, S1 and SO) which contain the existing status information
of an addressed MC33192.
7) End-ot-Frame field is a Signal which communicates
to the MCU that the status information sent by the MC33192
is complete.
The Push Field Sync bit, Push Field Data bits, Push Field
Address bits, Pull Field Sync bit are all coded by the
Manchester Bi-Phase L Code. The Pull Field Data bits are
Non-Return to Zero (NRZ) coded. The End-of Frame field is
a square wave signal with a frequency of 20 kHz or higher so
as to avoid a condition which causes a bus violation.
The Manchester Bi-Phase L code requires two time slots
(2ts) to encode a single bil. This allows a single error to be
detected during the time slol.
Address Programming involves the use of three
instructions. Refer to Figure10.
First Instruction Set the MI-Bus continuously at 12 V.
This places the MC33192 in the programming mode.
Programming is possible only when the MI-Bus is at 12 V.
Next, the MCU serially enters "Logic Zeros" in all five Push
Field Data bit positions (DO, D1, D2, D3 and D4) followed by
the designated address value in the Push Field Address
positions (AO, A 1, & A2).
The MCU now waits 275 /ls before starting the second
instruction. The total of the Pull time, Delay time, and Bus
Violation time (V) of the second instruction (150 /ls, 275 /ls
and 75 /ls respectively) will cause the memory cell to be
energized for 500 /ls. During the first 150 /ls of this time, the
MCU is checking the Pull Field Data Bits S2, S1 and SO
looking for the programming code "110" to indicate
complete activation of the memory cell.
Second Instruction (MI-Bus voltage remaining at 12 V)
The MCU repeats the same Push Field instruction as
previously sent in the First Instruction; entering all "Logic
Zeros" in the Push Field Data positions followed by the
designated Push Field Address value in the address
positions.
Again, the MCU waits for the Pull, Delay, and Bus violation
time while checking the Pull Field Data bits looking for the
programming code "110" code. The MCU must repeat the
initial Push Field Address instruction until a "110" code is
received before advancing to the Third Instruction.
Third Instruction The MI-Bus voltage is lowered to 5.0 V.
The MCU serially loads "Logic Zeros" in all five Push Field
Data bit positions followed by the programmed address in the
Push Field Address positions. The MCU then checks the Pull
Field Address status bits looking this time for the
10--67
1m
I
MC33192
programming OK code "100" indicating the address
programming to be executed.
The First and Second Instructions must be repeated until
the MCU successfully receives the programming code
"100'. Address programming is not complete until a "100"
OK status is received by the MCU with the MI-Bus voltage
at5.0V.
Overwrite-Bit Programming involves the use of two
instructions. See Figure 11.
First Instruction Have the MI-Bus continuously set at
12 V so as to have the MC33192 in the programming mode.
Programming can only be accomplished with the MI-Bus at
12 V.
The MCU serially enters "Logic Zeros" for the Push Field
Data bits ~O, 01, 02 and 03 and a Logic "1" for 04 bit
followed by the programmed address bits AD, A 1 and A2.
The MCU now waits 275 fls before starting the second
instruction. The total of the Pull time, Delay time, and Bus
Violation time (V) of the second instruction (150 fls, 275 fls
and 75 fls respectively) will cause the memory cell to be
energized for 500 fls. During the first 150 fls of this time, the
MCU is checking the Pull Field Data Bits for the status of bits
S2, S1 and SO looking for the programming code "110" to
indicate complete activation of the memory cell.
Second Instruction (MI-Bus remaining at 12 V)
The MCU repeats the first instruction outlined above until
the programming OK code "100" is sent back to theMCU
from the selected MC33192 indicating the overwrite-bit
protection to be programmed. If after eight repeat
instructions, the programming code "110" or the OK code
"100" is not generated four times in succession,
programming of the MC33192 has failed. If this occurs, the
Overwrite-Bit Programming sequence should be reviewed
and re-started from the beginning.
H-Bridge Output
The H-Bridge output drive circuit and associated
diagnostic encoder are shown in Figure 12. The H-Bridge
output uses internal diode clamps (01, 02, 03, 04) to provide
transient protection of the output transistors necessary when
switching inductive loads associated with stepper motor's.
Back EMF Detection
Three different Back EMF currents can occur depending
on whether the motor is running or manner in which it is being
stopped. Referring to Figure 12; When the Oir1 bit is set to
logic 0, the direction of current flow will be from V CC through
transistor 02, Coil A (A 1 to A2),. and transistor 04 to ground.
1) Fast Decay (when transistors 01, Q2, 03 and 04 are
switched off).
When the current flowing in the coil is stopped by setting
the Inh1 bit to logic 0, the back EMF current will .circulate
through the voltage supply (VCC) and di.odes 01 and 03. At
that time, the voltage developed across the diode 01 is
detected by transistor 06. The generated voltage pulse of 06
is then encoded and sent, in the Pull-Field, to the
microprocessor.
2) Slow Decay (03 and 04 are switched off)
When the current flowing in the coil is stopped by setting
the E bit to logic 0, the back EMF current will circulate through
the diode 01 and transistor 02 which is already switched on.
3) When Motor is Running
The rotational direction of the motor changes whenever
the Oir bit state is changed. When the Oir bit is changed from
a logic to a logic 1, transistors 02 and 04 are switched off
and transistors 01 and 03 are switched on. At this time, the
back EMF current will circulate from ground through diodes
01 and 03 to the voltage supply (VCC). In all cases, the back
EMF currents will be detected by transistors 05 and 06.
°
Figure 11. Address Programming Diagram
Programming
MI-Bus Voltage
I
Active
Finished
Finished
I 12V
12V
5.0V
Instruction Number
-I
1
2
Address
Status Code
Overwrite-Bit
Status Code
Strobe Pulse
Energy in
Memory Cell
10-68
vi
1
Push
1 PUlli
Delay
Ivi
Push
550~
,150~
275~
75~
550 ItS
I
1 "110'
1
1
i
I
500~
\
I
ivi
275~
75~
I
I
I
I
I
I
1 '110'
I
I
I
I
l
150~
Delay
I
1
1'110"
\ Pull i
I
I
"100'
I
475~
\
I
500 Its
1
3
"'I
1
MI-Bus Field
1
1
5.0V
\
I
Push
"'I
I PUllil1
I
1
I
1 '100'
1
I
1
1
'100"
I
OK
1
II
I
I
t
MOTOROLA ANALOG IC DEVICE DATA
MC33192
Figure 12. H-Bridge Output Drive Circuit and Diagnostic Encoder
r-~I---_--_-"""~I------o
Inh1O-'--~~---~-~--1--~~-~~----'
Vec
A1
~il~O
Dir1
Inh2
DB1
Coil 2
B2
Dir2
E
Ground
E
S2
S1
0
SO
BF1
BF2
ST
Programming
Thermal
S1
S2
0
SO
Status
Not Used
Free
0
No Back EMF
0
Free
1
NormaVOK
Thermal
Programming
Selection Failed
MOTOROLA ANALOG IC DEVICE DATA
10-69
MC33192
Figure 13. Single Wire MI-Bus Control of 8 Stepper Motors
Mi-Bus
Program
MC331920W
Run
Micorcontroller
Rl
MC331920W
ZI
R3
Pout
01
MC68HCOSB6
MC68HCllKA
RS
02
-=-
R6
MC331920W
Pin
03
Gnd
-=-
MC331920W
MC331920W
MC331920W
MC331920W
MC331920W
10-70
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC33193
Advance Information
Automotive Direction
Indicator
AUTOMOTIVE
DIRECTION INDICATOR
The MC33193 is a new generation industry standard UAA 1041 "Flasher".
It has been developed for enhanced EMI sensitivity, system reliability, and
improved wiring simplification. The MC33193 is pin compatible with the
UAA1041 and UAA1041B in the standard application configuration as
shown in Figure 9, without lamp short circuit detection and using a 20 mn
shunt resistor. The MC33193 has a standby mode of operation requiring very
low standby supply current and can be directly connected to the vehicle's
battery. It includes an RF filter on the Fault detection pin (Pin 7) for EMI
purposes. Fault detection thresholds are reduced relative to those of the
UAA1041 , allowing a lower shunt resistance value (20 mn) to be used.
SEMICONDUCTOR
TECHNICAL DATA
8~
1
o SUFFIX
PLASTIC PACKAGE
CASEl51
(SQ-a)
• Pin Compatible with the UAA1041
• Defective Lamp Detection Threshold
• RF Filter for EMI Purposes
• Load Dump Protection
• Double Battery Capability for Jump Start Protection
• Internal Free Wheeling Diode Protection
• Low Standby Current Mode
PSUFFIX
PLASTIC PACKAGE
CASE 626
Simplified Block Diagram
PIN CONNECTIONS
Vss
Vee
Oscillator
Enable
FauH Detector
Relay
Oscillator
(Top View)
-Iffl
r--~--=--:,--L---,
'-------,----'
I
Oscillator
L
I6
I
-::- 15
I
~------------------------~
This device contains 60 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
Slarter
ORDERING INFORMATION
Device
MC33193D
MC33193P
Operating
Temperature Range
TA = -40' to +125'C
Package
SQ.-8
DIP-8
10-71
MC33193
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Pin 1 Positive Current (ContinuouS/Pulse)
11+
150 to 500
mA
Pin 1 Negative Current (ContinuouS/Pulse)
11-
-35to-500
mA
Pin 2 Current (ContinuouS/Pulse)
12
±350to±1900
mA
Pin 3 Current (ContinuouS/Pulse)
13
±300 to ±1400
mA
Pin 8 Current (Continuous/Pulse)
18
±25to±50
mA
VESD
±2000
V
V
°C
ESD (All Pins Except Pin 4 for Negative Pulse)
ESD (Pin 4 Negative Pulse)
VESD4-
-1000
Junction Temperature
TJ
150
Operation Ambient Temperature Range
TA
-40 to +125
°C
Tstg
-65 to +150
°C
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (-40°C S; TA:S: +125°<:;, 8.0 V:S: VCC:S: 18 V, unless otherwise noted. Typical values
reflect approximate mean at TA;" 25°C, VCC = 14 V at the time of initial device characterization.)
Symbol
Min
Typ
Max
Unit
Battery Voltage Range (Normal Operation)
Characteristic
Vb
8.0
-
18
V
Overvoltage Detector Threshold (VPin2 - VPin1)
Vih
19
20.2
22
V
Clamping Voltage (R2 = 220 0)
Vcl
27
29.2
34
V
Output Voltage [I = -250 mA (VPin2 - VPin3)]
Vsat
-
1.5
V
3.3
3.6
k.Q
1.75
X
Starter Resistance (Rst = R2 + RLamp)
Rst
-
OSCillator Constant (Normal Operation, TA = 25°C)
Kn
1.3
1.5
Temperature Coefficient of Kn
TCKn
-
0.001
-
1rC
Duty Cycle (Normal Operation)
-
45
50
55
%
Oscillator Constant (One 21 W Lamp Defect, TA = 25°C)
Kf
0.63
0.68
0.73
X
Duty Cycle (One 21 W Lamp Defect)
-
35
40
45
%
Oscillator Constant (TA = 25°C)
K1
K2
0.167
0.250
0.180
0.270
0.193
0.290
-
-
2.0
100
Standby Current (Ignition "Off')
ICC
Current Consumption (Relay "Off," Enable Pin 6 High)
Vbat = 8.0 V, R3 = 220 ll, TA = 25°C
Vbat = 13.5 V, R3 = 220 0
Vbat = 18 V, R3 = 220 0, TA = 25°C
ICC
Current Consumption (Relay "On")
Vbat = 8.0 V, R3 = 220 ll, TA = 25°C
Vbat = 13.5 V, R3 = 220 0
Vbat = 18 V, R3 = 220 0, TA = 25°C
ICC
Defect Lamp Detector Threshold [R3 = 220 ll, (VPin2 - VPin7)]
Vbat = 8.0 V, TA = 25°C
Vbat= 13.5V
Vbat = 18 V, TA = 25°C
Vs
Temperature Coefficient of Vs
10-72
TCVs
-
-
-
1.40
2.16
2.64
-
1.62
2.06
3.30
46.5
-
43.6
51.0
57.0
56
-
0.3 x 10-3
-
J.lA
mA
3.5
mA
6.0
-
mV
11°C
MOTOROLA ANALOG IC DEVICE DATA
MC33193
Figure 1. Normal Operation Oscillator
Timing Diagram
Figure 2. One Defective Lamp Oscillator
Timing Diagram
0
0
-1.0
-1.0
..
_ -2.0
]i -2.0
.Q
>
>
1
-3.0
--+-1-
-4.0
1 1
1 1
1 1
11
T
--i
r-
1
-3.0
-1-
-4.0
1
1
1
-1I
1"*1
1 1
1 1
1
1
Fn = llt n
I
..
TIME
TIME
INTRODUCTION
The MC33193 is designed to drive the direction indicator
flasher relay. It is a new generation industry standard
UAA1041 "Flasher". It consists of the following functions:
•
•
•
•
•
•
Supply and Protections
On-Chip Relay Driver
Oscillator
Starter Functions
Lamp Fault Detector with Internal RF Filter
Standby Mode
Supply and Protection Systems
Pin 1 is connected to ground via resistor R3 which limits
the current in the event of any high voltage transients. Pin 2
(VCC) is the positive supply and may be connected directly to
the vehicle's battery voltage.
Overvoltage and Double Battery Protection: When the
applied VCC to VSS voltage is greater than 22 V, the
overvoltage detector circuit turns the relay driver off. Both the
device and the lamps are protected if two 12 V batteries are
connected in series and used to jump start the vehicle.
Load Dump Overvoltage Protection: A 29 V overvoltage
detector protects the circuits against high voltage transients
due to load dumps and other low energy spikes. The relay
driver is automatically turned on whenever the VCC to VSS
voltage is greater than 34 V.
Overvo/tage Protection, High Voltage Transients: The
Enable and the Starter pins are protected against positive
and negative transients by internal on--chip diodes.
On-Chip Relay Driver
The device directly drives the flasher relay. The output
structure is an Emitter of an NPN transistor. It contains the
free wheeling diode circuitry necessary to protect the device
whenever the relay is switched off.
MOTOROLA ANALOG'IC DEVICE DATA
Oscillator
The device uses a sawtooth oscillator (Figure 1).
The frequency is determined by the external components
C1 and R1. In the normal operating mode, the flashing
frequency is: Fn =1/R1*C1*Kn. With a defective (open) 21 W
lamp (Figure 2), the flashing frequency changes to: Fn =
2.2*Fn·
The typical first flash delay (the time between the moment
when the indicator switch is closed and the first lamp flash
occurs) is: t1 =K1*R1*C1
The fault detection delay is from the time relay R1 is on and
fault detection is enabled. Where a 21 W lamp opens, the
delay is expressed as: t2 =K2*R1*C1
Starter
Pin 8 is connected through a 3.3 kn resistor to the flashing
lamp. Pin 8 is the input to the Starter function and senses the
use of S1 by sensing ground through the lamp (Figures 9 and
10).
Lamp Fault Detector with Internal RF Filter
A Lamp defect is sensed by the lamp fault detector's
monitoring of the voltage developed across the external
shunt resistor RS via the RF filter. The RS voltage drop is
compared to a Vbat dependent internal reference voltage
(Vref) to validate the comparison over the full battery voltage
range. A detected fault causes the oscillator to change
frequency (Figure 2).
Standby Mode
When the ignition key and warning switches are open;
Enable is in a low state and the internal switches, SW1 and
SW2, are open and no current passes through the circuit. In
this condition, the device's current consumption is zero
(ICC = 0). When ignition key and warning switches are
closed; Enable is in a high state with SW1 and SW2 being
closed and the circuit is powered on.
10-73
MC33193
MAIN DIFFERENCES BETWEEN
UAA1041B & MC33193
The MC33193 is pin compatible with the UAA 1041.
Supply Current
Supply current is more stable on the MC33193 when the
device is in "on" or "off' state. In "on" state the supply current
is only 40% higher than when in the "off" state, as compared
to a ratio of 3 times for the UAA 1041. This results in a lower
voltage drop across the ground resistor R3 (see On-Chip
Relay Driver).
Short Circuit Detection
The MC33193 has no short circuit detection.
Standby Mode (Pin 6)
The UAA1041 has no standby mode. Pin 6 is used as an
Enable/Disable for the short circuit detection.
The MC33193 uses Pin 6 to set the device in standby
mode. If Pin 6 is connected to ground, the MC33193 is in the
standby mode. In this mode, standby current is very low and
Pin 8's starter resistor R2 and a 2.0 kn internal resistor are
switched off. As soon as Pin 6 is at a high level (typical
thre.shold
2Vbe) the device becomes active. In the
application, the MC33193 can be connected directly to the
battery and awakened whenever Pin 6 is connected to the
vehicle's battery by way of a protection resistor and the
ignition key switch.
=
The MC33193 is designed to operate with 20 mn shunt
resistor and at a reduced threshold of 50 mV. This reduces
power generation in the flasher module. In addition, the
MC33193 incorporates an RF filter to enhance RFI immunity.
Load Dump and Overvoltage Behavior
The UAA1041 and MC33193 both behave the same in this
regard. Both have double battery detection and lamp turn-off
protection in the event of a jump start. During load dump, both
devices are protected by an internal 30 V zener diode with the
relay activated during a load dump.
Relay Driver
Drive capability of both devices is the same. Free wheeling
diode protection is internal to both devices. The free wheeling
voltage is 2Vbe for the UAA 1041 and 3Vbe for the MC33193.
This results in a higher clamp voltage across the relay and
thus in a faster turn-off. In addition, the lower "on" state
supply current is lower on the MC33193 and thus the voltage
drop across the ground resistor R3 is reduced. This results in
an even higher clamp voltage across the relay.
Oscillator Phase
The oscillator phase is opposite on the MC33193 as
compared to the UAA1041. The Oscillator voltage is falling
during ~on· state and rising during "off' state for the MC33193.
Lamp Defect Detection (Pin 7)
The UAA 1041 operates with a 30 mn shunt resistor to
sense the lamp current. It's lamp defect detection threshold of
Pin 7 is typically 85 mV.
10-74
MOTOROLA ANALOG IC DEVICE DATA
MC33193
Figure 3. Clamping Voltage versus Temperature
0
29.5
~
~
21.5
ffi
29.0
-
28.5
d 28.0
~
a:: 21.0
-
~
a::
::;;;
Figure 4. Overvoltage Detection
versus Temperature
~
~
lli
s-
F
~
o
w
~
~
~
20.0
~
.j
27.5
-50
o
50
100
150
19.5
-50
o
TA, AMBIENTTEMPERATURE (0C)
Figure 5. Supply Current versus Temperature
1
a::
a::
=>
<..>
3.0
!z
w
~
0
~
>
0
50
100
o
io-
50
100
Figure 7. Defect Lamp Detection
versus Temperature
Figure 8. Oscillator Constant
versus Temperature
150
1.7
W
w
Vbat= 13.5V
R2=220Q
::;;;
51
50
o
e..
49
-50
E
""""
~
./
52
o
~
~
TA, AMBIENTTEMPERATURE (oG)
z
~w
'"
TA, AMBIENTTEMPERATURE (0C)
F
~
1.24
1.22
-50
150
53
~
1.26
....e..=>
2.0
Vbat= 13.5V
1=250mA
~
w 1.28
Cl
0
-50
a::
150
Figure 6. Output Voltage versus Temperature
!:§
§Z
....
=>
0
.9 1.0
i
roo
1.30
Vbat= 13.5 V
R2=22on
4.0
50
TA, AMBIENT TEMPERATURE (0C)
5.0
e..
e..
=>
CI)
i-""'"
""""
Cl
~
~
"..
20.5
......-
/"
!z
~
z
<..>
/'
1.6
CI)
0
a::
V
1.5
g
:s-'
(3
CI)
/'
1.4
0
~
/
/'
V
./'
1.3
o
50
100
TA, AMBIENT TEMPERATURE (oG)
MOTOROLA ANALOG IC DEVICE DATA
150
-50
o
50
100
150
TA, AMBIENT TEMPERATURE (0C)
10-75
MC33193
Figure 9. MC33193 Typical Application
80---+---,
RS
70---+---+--+
2
MC33193
C1
6
R2
4
R3
Re~ _ _ _ _ .!~
_______ _
S1
16
L2
l3
L4
l5
RS=20mn
R1 =75kn
C1 =5.6 IlF
R2=3.3kn
R3=200Q
L2, L3, L4, l5 = 21 W Turn Signal Lamps
Application Information
NOTES: 1. In the above application, the MC33193 is compatible wfth the UAA1041 and UAA1041 B except
for the shunt resistor value (RS = 20 rna).
2. The flashing cycle Is started by the closing of swHch 81.
3. The position of switch 81 is sensed across resistor R2 and RLamp by the input, Pin 8.
1~76
MOTOROLA ANALOG IC DEVICE DATA
MC33193
Figure 10. Typical MC33193 Application
RS
CI
R2
Relayl _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
_____ _
EXTERNAL COMPONENTS
Rs=20mQ
RI =75kQ
CI =5.6~F
R2=2.2kQ
R3=220Q
10 kQ:;; R4:;;47 kQ
IOkQ:;;R5:;;47kQ
Relay I
L1, L2, L3, L4=21 W
LD = Dashboard Indicator
Application Information
NOTES: 1. The flashing cycle is started by the closing of switch 81.
2. The 81 switch position is sensed across the resistor R2 and RLamp by the input (Pin al.
3. If the logic state at Pin 6 is [0], the current through R2 is off.
MOTOROLA ANALOG IC DEVICE DATA
10-77
®
MOTOROLA
MC33197A
Advance Information
Automotive Wash Wiper Timer
The MC33197A is a standard wiper timer control device designed for
harsh automotive applications. The device can perform the intermittent, after
wash, and continuous wiper timer functions. It is deSigned to directly drive a
wiper motor relay. The MC33197A requires very few external components
for full system implementation. The intermittent control pin can be switched
to ground or Vbat to meet a large variety of possible applications. The
intermittent timing can be fixed or adjustable via an external resistor. The
MC33197A is built using bipolar technology and parametrically specified
over the automotive ambient temperature range and 8.0 to 16 V supply
voltage. The MC33197A can operate in both front and rear wiper
applications.
AUTOMOTIVE WASH
WIPER TIMER
SEMICONDUCTOR
TECHNICAL DATA
• Adjustable lime Interval of Less Than 500 ms to More Than 30 s
• Intermittent Control Pin Can Be Switched to Ground or Vbat
• Adjustable After Wipe lime
P SUFFIX
PLASTIC PACKAGE
CASE 626
• Priority to Continuous Wipe
• Minimum Number of Timing Components
• Integrated Relay Driver With Free Wheeling Protection Diode
• Operating Voltage Range From 8.0 to 16 V
8~
• For Front Wiper and Rear Wiper Window Applications
1
DSUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
ORDERING INFORMATION
Operating
Temperature Range
Device
Package
MC33197AD
TA = - 40° to +105°C
S0-8
MC33197AP
TA = - 40° to +125°C
DIP-8
PIN CONNECTIONS
MAXIMUM RATINGS
Rating
Continuous Supply Voltage (VPin 6)
Symbol
Value
VCC
16
Storage Temperature
Tstg
-55 to +150
ThermalHesistance (Junction-to-Ambient)
DIP-8 Package
S0-8 Package
RaJA
Operating Ambient Temperature Range
DIP-8 Package
S0-8 Package
Operating Junction Temperature Range
Maximum Junction Temperature
NOTE: ESD data available upon request.
10-78
Unit
V
INT
Out
0sc2
Gnd
Osc1
Vee
eONT
WIW
°c
(Top View)
°CIW
100
145
(50-8)
°C
TA
-40 to +125
-40 to +105
TJ
-40 to +150
°C
TJ(max)
150
°C
Osc2
Oscl
eONT
INT
WIW
Out
Vee
Gnd
(Top View)
MOTOROLA ANALOG IC DEVICE. DATA
MC33197A
Representative Block Diagram
CI
r------------
I
I
I
I
I
Vbb
I~
Switch
Variable Current Sources
I
I
I
I
-=- w/WI
Ref I
I
I
liNT
1
-=-
Rl =2200
R2=22kO
R3 = 1.5t022 kn
R4=4.7kn
R5 =4.7 kO
Cl =4711F
C2=100nF
Rl
I
Gnd
Water Pump Motor
R4
11- __ ~~~~~ ___ ~~j ~--J\jVv-~
L______ ~~~
I Oscl
R2
."
Input Comparator II I-_R-,-e,-f-01
This device contains 390 active transistors.
ELECTRICAL CHARACTERISTICS (-40°C $ TA $ +125°C, 8.0 V $ VCC $16 V, unless otherwise noted. Typical values reflect
approximate mean atTA
=25°C with VCC =14 V at the time of initial device characterization.)
Characteristic
Functional Supply Vo~age Range
Operating Supply Voltage Range
= 16 V, R2 = 68 k)
Supply Current INT Active (R3 = 2.5 k)
Supply Current Relay "On" (R2 = 68 k)
Supply Current INT and Relay "On" (R2 = 68 k, R3 = 2.5 k)
Standby Supply Current (VCC
Oscillator Variations with Supply Voltage and Temperature (excluding
external component tolerances, C2 = 100 nF polyester capacitor)
(Notes 1 &2)
Symbol
Min
Typ
Max
Unit
VCCF
8.0
-
18
V
VCCOP
8.0
-
16
V
ICC
-
4.0
5.2
rnA
ICC
-
7.0
8.4
rnA
ICC
-
7.5
11.2
rnA
ICC
-
10
14.5
rnA
%
Kosc
RL
60
-
-
0.9
1.5
V
V
10V$Vbb$16V
8.0 V $ Vbb $ 16 V
-
Relay Resistance
Output Voltage (lout = 200 rnA)
10
15
Q
Vout
-
Output Clamp Voltage (lout = 20 rnA)
Vcl
19.5
-
22
Oscillator Period Coefficient (TA = 25°C)
Vbb = 13 V (Note 3)
Vbb = 13 V (INT Connected to Gnd) (Note 4)
Vbb = 13 V (INT Connected to Vbat, Rl = 220 0) (Note 4)
tbl
tb2g
tb2v
0.98
15.1
11.5
1.0
15.5
12.1
1.03
15.9
12.7
Vih
6.0
-
8.5
V
Vih
-
VCC/2
-
V
CONT Threshold (VCC
CONT Threshold (VCC
= 13 V)
= 16 V)
-
NOTES: 1. The oscillator frequency is defined by the current flowing through the external resistor R2. The vo~age at the INT pin is (Vccl2 - Vbe) and hence the
current flowing through R3 is different if R3 is connected to Vbb or to Gnd because of the voltage drop across resistor R1. This voltage drop causes
the oscillator coefficient for tb2 to be different for the two cases of INT tenninated to Gnd or to Vbb. Because of this, the oscillator coefficient is specified with a specnic value of Rl whenever INT is connected to Vbb. If Rl is changed, the coefficient will change. Also, any extra current through the
resistor R1 other than the current used by the device will cause timing deviations in tb2 timings (as in the case where two devices are sharing a
common Rl resistor).
2. The oscillator stability with temperature is dependent on the temperature coefficients of the external components. If the capacitance value of the
external capacitor varies more than 5% over the parametric temperature range, the figures quoted for oscillator variation are not valid.
3. The tbl duration is given by coefficient 4 x R2 x C2 (tbl duration = tbl x 4 x R2 x C2).
4. The tb2 duration is given by coefficient x R3 x C2 (tb2 duration = tb2 x R3 x C2).
MOTOROLA ANALOG IC DEVICE DATA
10--79
MC33197A
Figure 1. Intermittent Wash Wiper Typical Application
+ Battery Line
,
Vbb
r-----------I
r----'I Washer
I
I
I
I
I Intermittent
Low Speed
o---t-I....:.H""ig""hSpeed
I
Wash Wipe
Switch
r--R3
I
---,
I
I
VCC
INT
R4
I
t-----o~\I\r_O
I
I
R1
I
I
MC33197A
WIW
Out
Wiper Motor
Ll~-OSIc1-G5nd-J
r
I
C2
R2
I
1--
Low Speed
1...___________ __
-=-
r-
Water
Pump
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
High Speed
I
I
I
II
,
_
I
I
I
II
L. _ _ _ _ _ _ _ _ .J
This application shows the MC33197A with the extemal wirings and two speed
wiper motor. This application has the Intermittent and Wash Wiper functions.
INTRODUCTION
The MC33197A is a wiper timer control device designed
for use in harsh automotive applications. The device can
perform the intermittent, after wash, and continuous wiper
timer functions.
The MC33197A is designed to directly drive a wiper motor
relay. The MC33197A is suitable for both front and rear wiper
applications. The MC33197A connects directly to the
vehicle's battery voltage (Vbat) through a 220 Q resistor used
with a 47 I1F de--coupling filter capacitor. The device has an
internal oscillator controlled by one of two external resistors
(R2 and R3) in addition to one external capacitor (C2),
dependent on the application function required. The values of
C2 and R2 determine the tb1 time base. Tb1 is used to
generate the relay wiper activation during the INT function
(T3) and the after wash timing (T2) during the wash wipe
mode. The values C2 and R3 determine the tb2 time base.
The tb2 time base is used to generate the pause or
intermittent time (T4).
The intermittent wiper function can generate intermittent
timing (T4) from less than 500 ms to more than 30 seconds.
The intermittent function of the device can be activated by the
INT input connected to either ground or Vbat. The intermittent
timing is externally adjustable by changing the value of
resistor R3.
10-80
The wash wiper timer function detects the water pump
motor's operation. When the pump motor activation is
detected, the MC33197A turns the wiper on for the entire
duration of the pump motor's activation. When the motor is
turned off, it generates an after wash timing (T2) to maintain
the wiping action. The W/W pin is connected to the water
pump motor through a protection resistor (R4).
The MC33197A also has a continuous function, which
activates the wiper relay whenever the CaNT input is
activated. The CaNT input is connected to a switch through
a protection resistor (R5). The CaNT input comparator has
an input threshold of Vbbl2 with hysteresis.
The device has internal debounce circuitry, based on the
oscillator period. This provides filtering of the intermittent
(INT) and wash wipe (W/w) input Signals (see T1 Debounce
TIming paragraph that follows). The device directly drives the
wiper motor relay. It internally incorporates a 20 V free
wheeling zener diode to protect the device against
overvoltage spikes produced when relay is switched off.
Intermittent Operation
Conditions:
• W/W not connected or connected to ground.
• CaNT not connected or connected to ground.
• INT connected to Vbb or to ground.
MOTOROLA ANALOG IC DEVICE DATA
MC33197A
In this configuration, the circuit will respond to the
switching of INT to either Vbb or ground after a time Tl (see
Tl Debounce Timing). If INT is disconnected before the end
of Tl; no action will be taken. After a time Tl, the output will
be switched on for a duration, T3 = 16 x 4 x tbl and then
switched off for a duration, T4 = 144 x 4 x tb2. This sequence
will continue to repeat so long as INT is disconnected from
Vbb or ground for a time duration greater than Tl. If INT is
disconnected during the time T3; the output will remain on for
the remainder of T3. This is illustrated in the diagram on
Figure 2.
Figure 2. Switching Waveform INT Timing
Out
U
U
T1~j--L
L
Wash Wiper and Intermittent Operation
If WIW is activated during the time INT is also activated,
the circuit will respond to WIW after a time Tl (see T1
Debounce Timing). The output will turn on after T1, and stay
on for a time T2 + T3 after WIW is deactivated. Following this,
normal operation of INT will occur. This is shown on Figure 4.
Figure 4. Switching Waveform W/W and INT Active
INT
WIW
Out
LJ
~T4--1
Wash Wipe Operation
Conditions:
• INT disconnected.
• CONT disconnected or connected to ground.
In this condition, the circuit will respond to the switching of
WIW to Vbb after a time T1 (see T1 Debounce Timing). If
WIW is disconnected or connected to ground before the end
of Tl; no action will be taken. After a time Tl; the circuit will
perform as shown on Figure 3. The output will turn on and
remain on for the duration of WIW. When WIW becomes
inactive, the output will remain on for T2 = 96 x 4 x tbl.
T1 Debounce Timing
The criteria for an input signal to be detected is that it
should be active at two successive negative internal clock
edges. The inputs are sampled on the negative edge of the
internal clock. If two consecutive samples are the same, the
input is detected as being in that state. Hence the time T1 from
a signal becoming active to the time that the circuit responds
can be anytime from 4 xtbl to 2 x 4 xtbl (due to synchronizing
the input to the oscillator period) when the oscillator is
oscillating with atime base oftbl and4xtb2t02x4xtb2, when
the oscillator is oscillating with a time base of tb2.
The following table summarizes all Tl debounce timings:
Condition
Figure 3. Switching Waveform W/w Timing
Out
-1T11--
I---T2--1
Continuous Operation
In this condition, the circuit responds to the switching of
CONT to Vbb. If CONT is connected to Vbb, the output will
turn on regardless of the state of any other input and remain
on so long as CO NT is active. This command operates
directly on the relay output and does not interfere with any
other timing. Therefore, the circuit will not be reset to a
defined state.
MOTOROLA ANALOG IC DEVICE DATA
Debounce Time
INT Active
4 x tb1 to 2 x 4 x tb1
INT Inactive
4 x tb1 to 2 x 4 x tb1
WfW Active When INT Inactive
4 x tb1 to 2 x 4 x tb1
WfW Active When INT Active During T3
4 x tb1 to 2 x 4 x tb1
WfW Active When INT Active During T4
4xtb2t02x4xtb2
Two MC33197A Devices Using One Decoupling
Resistor and CapaCitor
Two devices may be connected to the power source using
a common Rl resistor for protection against overvoltages. If
this is done it should be noted that the current flowing
through R1 is increased and hence the voltage drop across
Rl is increased.
1~1
MC33197A
Overvoltage Protection
In reference to the Block Diagram and Typical Application,
all of the foregoing operational cases require:
R1 ~ 100 n, Cl ~ 47 IlF
R3~ 1.0 kn, R4~4.7kn, R5~4.7kn
The circuit will not operate during the transient conditions.
By using the above component values, the circuit will be able
to sustain the following overvoltages on Vbb without
permanent damage:
1. +28 V for 5 minutes
2. -15 V for 5 minutes
3. -16 V cycled off for 1.0 minute
4. +80 V pulse decaying exponentially to 8.0 V in 400 ms
repeated 3 times at 1.0 minute intervals.
5. ± 300 V pulse decaying exponentially to 30 V in 300 ms
with a maximum energy of 1.0 Joule.
6. ±100 V pulse decaying exponentially to 10 V in 2 ms.
Recommended External Component Values
Below are the recommended component values to ensure
the device will operate properly, and that all specified
parameters will stay within their tolerances.
Rl should be greater than 100 n; recommended value of
220 n. Rl can be up to 500 n, but in this case the tli2v
parameter could be out of it's specified value (see Electrical
Characleristicsand Note 1). Also, the minimum operating
voltage range should be greater than 8.0 V. The following
values should be adhered to:
10 kn ~ R2 ~ 68 kn
1.5 kg ~ R3 ~ 47 kn
R4~4.7kn
R5~4.7kn
Cl ~47 uF
47 nF ~ C2
10-82
~
Application Information
The following is an example of timing calculations using
the following external components values:
R2 = 22 kn, R3 = 2.2 kn, C2 = 100 nF (Referring to Block
Diagram and Typical Application).
Oscillator TIme Base Calculation:
tbl duration =tbl x4 x R2 x C2 = 1 x 4 x 27e3 x 100e-9 =
10.8 ms
tb2 duration_g (INTto Gnd) = tb2g x R3 x C2 = 15.5 x 2.2e3
x 100e-9 = 3.41 ms
tb2 duration3 (INTto Vbb) = tb2v x R3 x C2 = 12.1 x 2.2e3
x 100e-9 = 2.66 ms
Intermittent timing calculation:
T3 = 16 x 4 x tbl duration = 16 x 4 x 10.8 ms = 691 ms
T4 = 144 x 4 x tb2 duration_g = 144 x 4 x 3.41 ms = 1.96 s
(INT connected to Gnd)
T4 = 144 x 4 x tb2 duration_v = 144 x 4 x 2.66 ms = 1.53 s
(INT connected to Vbb)
Wash wipe timing calculation:
T2 = 96 x 4 x tbl = 96 x 4 x 10.8 ms = 4.15 s
Tl Debounce TIme Calculation (see Tl Debounce TIming)
When oscillator is oscillating at tbl:
Tl minimum = 4 x tb1 = 4 x 10.8 ms = 43.2 ms
Tl maximum = 2 x 4 x tb1 = 2 x 4 x 10.8 ms = 86.4 ms
When oscillator is oscillating at tb2:
Tl minimum (I NT connected to Gnd, tb2g) = 4 x tb2 = 4 x
3.41 ms = 13.6 ms
Tl maximum (INT connected to Gnd, tb2g) = 2 x 4 x tb2 =
2 x 4 x 3.41 ms = 27.3 ms
470 nF
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC33199
Automotive ISO 9141
Serial Link Driver
The MC33199D is a serial interface circuit used in diagnostic
applications. It is the interface between the microcontroller and the special
K and L Lines of the ISO diagnostic port. The MC33199D has been
designed to meet the "Diagnosis System ISO 9141" specification.
The device has a bi-directional bus K Line driver, fully protected against
short circuits and over temperature. It also includes the L Line receiver,
used during the wake up sequence in the ISO transmission.
The MC33199 has a unique feature which allows transmission baud rate
up to 200 k baud.
• Electrically Compatible with Specification
"Diagnosi~
1509141
SERIAL LINK DRIVER
SEMICONDUCTOR
TECHNICAL DATA
System ISO 9141"
• Transmission Speed Up to 200 k Baud
• Internal Voltage Reference Generator for Line Comparator Thresholds
• TXD, RXD and LO Pins are 5.0 V CMOS Compatible
• High Current Capability of DIA Pin (K Line)
• Short Circuit Protection for the K Line Input
• Over Temperature Shutdown with Hysteresis
• Large Operating Range of Driver Supply Voltage
• Full Operating Temperature Range
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(So-14)
• ESD Protected Pins
Simplified Application
Vs
PIN CONNECTIONS
--,
I
I
I
I
REF-QUT cro---j
LO
~----1-------~--oL
I
I
I
I
REF-IN-L 0 - - - - - - - - - '
REF-IN-K 0 - - - - - - - ,
Vee
REF-QUT
REF-IN-!.
Vs
REF-IN-K
L
LO
L-------o11
11
RXD
Gnd
TXD
DIA
NC
NC
1---11----.....----4_-0 DIA
I
I
I
I
(Top View)
Gnd
-.L1
-=I
ORDERING INFORMATION
I
This device contains 94 active transistors.
MOTOROLA ANALOG IC DEVICE DATA
Device
Operating
Temperature Range
Package
MC33199D
TA = - 40° to +125°C
S0-14
10-83
MC33199
MAXIMUM RATINGS (Note 1)
Rating
Vs Supply Pin
DC Voltage Range
Transient Pulse (Note 2)
Symbol
Value
Unit
Vs
Vpulse
-0.5 to +40
-2.0 to +40
VCC
-0.3 to +6.0
V
-0.5 to +40
-2.0
-50
Int. Limit
V
V
mA
rnA
-0.3 to
VCC+0.3
V
V
VCC Supply DC Voltage Range
DlA and L Pins (Note 2)
DC Voltage Range
Transient Pulse (Clamped by Internal Diode)
DC Source Current
DIA Low Level Sink Current
-
TXD DC Voltage Range
-
REF-IN DC Voltage Range
VSVCC
-
V
-0.3 to VCC
-0.3 to Vs
ESD Voltage Capability (Note 3)
±2000
V(ESD)
V
NOTES: 1. The device is compatible with Specification: "Diagnosis System ISO 9141".
2. See the test circuit (Figure 23). Transient test pulse according to ISO 76371 and DIN 40839;
highest test levels.
3. Human Body Model; e 100 pF, R 1500 ll.
=
=
THERMAL RATINGS
Rating
Storage Temperature
Operating Junction Temperature
Thermal Resistance, Junction-te-Ambient
Maximum Power Dissipation (@ TA = 105°C)
Symbol
Value
Unit
Tstg
-55 to +150
°c
TJ
-40 to +150
°c
RaJA
180
°cm
PD
250
mW
ELECTRICAL CHARACTERISTICS (- 40°C,;; TA';; 125°C, 4.5 V,;; VCC';; 5.5 V, 4.5 V,;; VS';; 20 V, unless otherwise
noted. Typical values reflect approximate mean at 25°C, nominal VCC and VS, at time of device characterization.)
I
Characteristic
I
Symbol
I
Min
I
Typ
I
Max
Unit
VCC PIN 1
VCC Supply Voltage Range
5.5
VCC Supply Current (Note 1)
1.0
1.5
-
VCC-2.0V
VS-l.0V
REF-IN-L PIN 2 AND REF-IN-K PIN 3
REF-IN-L and REF-IN-K Input Voltage Range
For 0 < Vs < VCC
For VCC 2.7 V)
Rise Time
Hold Time
10-8&
ns
tllR
tllF
-
1.5
-
-
J!S
ns
I1S
MOTOROLA ANALOG IC DEVICE DATA
MC33199
Figure 1. TXD to DIA AC Characteristic
+ 5.0 V +12 V
r-L-l-,
Input
Signal
§'~§r'h~
DIA
!
TXD
IL
~~-~---~~i~t----~.IL_
n~ ~i9~ ~ lu_t
i
__
OV
!
I tDDR
~
I
I
I
I-
___
tDDF
T 1.0nF
v---:l.
-=
Gnd
_ _ _ _ _ ..J
Figure 2. DIA to TXD and L to LO AC Characteristics
12 V , - - - - - - - - ,
+ 5.0 V +12 V
..-----r----I
I
2.0K
-1-,I
Vcc
Vbat
REF-OUT
REF-IN-L
REF-IN-K
nD
DIAand L
Input Signal
I
I
L~nput
Signal
DIA
h
Testo--I------OLO
Gnd.
Points 0
1: 1: '6RXD
I L _ _ _ _ _ .J
2X30pF
-=-
I
Figure 3. Current Source 11 AC Characteristics
.
L
Figure 4. Current Source 11 and DIA Discharge
Current Test Schematic
11 Pulse
Current
+ 5.0 V +12 V
r-L-l-,I ~
ov
.l VCC Vbat
'( REF-OUT
Current Source
11 Maximum Limit
Input
Signal
9 REF-IN-L
6 REF-IN-K
~nD
JU
LO
I
11
DIA
~
h
9
Gnd
6L RXD
_ _ _ _ _ .J
.
DIA Discharge
Current
33nF To
FOscilioscope
100
At static "High" or "Low" level TXD, the current source 11 delivers a
current of 3.0 mA (typ). Only during "Low" to "High" transHion, does this
current increase to a higher value in order to charge the Kline
capacitor (CI < 4.0 nF) in a short time.
MOTOROLA ANALOG IC DEVICE DATA
10-87
MC33199
Figure 5. Logic Diali/ram and Application Schematic
r-----------,
r-----------------------------,
Vbat
VCC=5.0V
I
I
I
I
-+ -
REF-OUT
LO
I
I
I
L
1----1----_+-0-- - -
I
I
LUne
___
- --1001--+--0
I
I
I RpU
I
I
I
REF-IN-L
REF-IN-K
11
RXD
TXD
RXD
MCU
TXD
car Electronic Control Unit
~-----------------------------j
Figure 6. Typical Application with Several ECUs
+Vbat
r- ------------ -,
r - - -------------,
I
I
I
~
ECUil1
r
~
r
r
ECUil2
Car
Other
ECUs
r-
I
I
I
I
I
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
\
RpU
LUne
KUne
Service Tester or
EndofLIne
Manufacturer
Programmation or
Checking System
IL. _ _ _ _ _ _ _ _ _ _ _ _ _
Car ISO Diagnostic
Connector
---------------j
1D-88
MOTOROLA ANALOG IC DEVICE DATA
MC33199
Figure 8. IS Supply Current
versus Vs Supply Voltage
Figure 7. ICC Supply Current
versus Temperature
2.5
1.4
I
1.2
!z
w
a:
a:
1.0
:::>
()
~
a..
a..
0.8
:::>
en
6
()
-r--- --- --
I
t--
w
a:
a:
t--
o
-25
25
50
75
:::>
a..
a..
00 0.5
I-Z
w
a:
a:
:::>
()
~
a..
a..
:::>
en
.i>
5.0
Figure 9. IS Supply Current
versus Vs Supply Voltage
Figure 10. Vs Voltage
versus IS Current
-40°C
-"
25°C
15
./
/.
10
~
5.0
I~
~
7: "/
~ ",,°C
~
w
(!l
30
~
:...I
0
"':
25
;ff'
20
15L-----~-----L----~L-----~----~
10
15
20
25
30
-5.0
35
-1.0
3.0
7.0
11
Vs, SUPPLY VOLTAGE (V)
IS, CURRENT (mA)
Figure 11. REF-OUT Voltage
versus Vs Supply Voltage
Figure 12. REF-OUT Voltage
versus REF-OUT Current
15
0
~
/
8.0
w
/
~
(!l
VS-18V
8. 0
~
/
6.0
~
I--
6. 0
:::>
a..
§
4.0
t-=
:::>
:r
a:
20
~r-----~----'------.-----.----~
~
w
15
VS, SUPPLY VOLTAGE (V)
10
~
10
TA, AMBIENT TEMPERATURE (OC)
20
5.0
~
125°C
25
o
tll
~
o
125
30
0.6
0.4
-50
2.0
I-Z
V
a..
/
I--
:::>
0
:r
2.0
w
a:
5.0
4. 0
t-=
:::>
10
15
20
25
VS, VOLTAGE (V)
MOTOROLA ANALOG IC DEVICE DATA
30
35
VS=6.0V
2. 0
0
-50 -40 -30 -20 -10
0
10
20
30
~
50
REF-()UT, OUTPUT CURRENT (~)
10-89
MC33199
Figure 13. Land DIA Hysteresis
versus Ambient Temperature
Figure 14. Land DIACurrent
versus Land DIA Voltage
500
12
:>
.s
!!2
480
en
w
a:
w
~ 460
V
>
/
--'
8.0
25°C
..:. 6.0
1Te
Q
Q
.;;:
420
is
0
25
50
75
100
125
z
Q 450
!;;:
a:
::>
!;;: 400
en
:;!;
Q
~350
~
Q
> 300
-50
30
35
40
70
1
!::
----~
-25
o
25
::::;
.....
z
f..--
75
62
w
a:
a:
::>
(.)
~
50
66
:::;:
58
:;!;
Q
:$
54
Q
100
50
-50
125
.-- ...-25
~
2.5
2.4
~ 2.3
~ 2.2
2.1
2.0
1.9
~ 1.8
~ 1.7
a: 1.6
1.5
-50
Z
Q
----- ---25
0
25
50
75
TA. AMBIENT TEMPERATURE (OC)
1()'-90
...-o
~
25
50
---
I--"'"
75
i.-"""'"
100
125
TA. AMBIENT TEMPERATURE (0C)
Figure 17. RXD Pull-Up Resistor
versus Temperature
~
25
Figure 16. DIA Current Limit
versus Temperature
TA. AMBIENT TEMPERATURE ('C)
~
--'
20
Figure 15. DIA Saturation Voltage
versus Temperature
!:i soo
a:
15
VOlA. VL. DlA ANO L VOLTAGE (V)
lOlA =40 rnA
§2
a
10
5.0
TA. AMBIENT TEMPERATURE ('C)
550
0
~
-
Z
:;!;
-25
I--
«
:I:
400
-50
f/
(.)
>
:>
.s
w
10
a:
a:
./
:I:
is
./
<"
~
.....
z
Figure 18. TXD and LO Saturation Voltage
versus Temperature
600
!;;:
~
!;;:
500
en
i-""'"'
100
9
>
Q
~
400
300
~;... 200
..
9
>
125
~
-;:::::. f::-- i"'""
::::::: :::RXO
----
100
J~50
-25
o
25
50
75
100
125
TA. AMBIENTTEMPERATURE (Oe)
MOTOROLA ANALOG IC DEVICE DATA
MC33199
Figure 19.11 Saturation Voltage
versus Temperature
Figure 20. 11 Output DC Current
versus Temperature
3.50
1.0
~
w
C!l
i:!:
'-'
ij::' 3.00
~
z
Q
w
~ 2.75
c::
!;;:
=>
(.)
0.7
~
CI)
i
~
z
0.8
!;;:
=>
-
3.25
0.9
2.50
0.6f--+---+--+--t---f---/----j
2.25
0~LO---_-2L5--~0L---~25L---~50L---~75L---~10-0---1~25
2.00
L
/'
/
V
:>
-50
0
25
50
75
Figure 21. 11 Output Pulse Current
versus Vs Supply Voltage
Figure 22. 11 Pulse Current Width
versus Temperature
g-
90~--_j----_+----_+-----+----~~~~
~
80~--_j----_+~~~~~~----~----~
c::
a
.,.:;
4.2
~
0
§:
4.0
~
I
--- -......
-
=>
0-
3.B
i'-..
~
:!:
w~~~~--_j----_+----_+----_+----~
40L---L--~-~-
7.5
10
12.5
_
_ L_ _L__~
15
17.5
20
125
4.4
w
5.0
100
TA. AMBIENT TEMPERATURE (0C)
100 r - - - - - , - - - - , - - - - , - - - , - - - - - , - - - - - ,
~
-25
TA. AMBIENT TEMPERATURE (OC)
-
3.6
3.4
-50
-25
0
25
50
75
.......
~
100
125
TA. AMBIENT TEMPERATURE (0C)
Vs. SUPPLY VOLTAGE (V)
Figure 23. Transient Test Circuit Using Schaffner Generator
+12V
D2
Schaffner
Generator
Test pulses are directly applied to Vs and via a capacitor of 1.0 nF to
DlA and L. The voltage Vs is limited to - 2.0 V/tUJ V by the transient
suppressor diode Dl. Pulses can occur simultaneously or separately.
MOTOROLA ANALOG IC DEVICE DATA
10-91
MC33199
INTRODUCTION
The MC33199 is a serial interface circuit used in
diagnostic applications. It is the interface between the
microcontroller and the special K and L Lines of the ISO
diagnostic port. The MC33199 has been designed to meet
the "Diagnosis System ISO 9141" specification.
This product description will detail the functionality of the
device (see simplified application). The power supply and
reference voltage generator will be discussed followed by the
path functions between MCU, K and L Lines. A dedicated
paragraph will discuss the special functionality of the 11 pin in
it's ability to accommodiate high baud rate transmissions.
Power Supplies and Reference Voltage
The device requires two power supplies to be used; a
5.0 V supply, VCC, which is normally connected to the MCU
supply. The device VCC pin is capable of sinking typically
1.0 mA during normal operation. A Vbat supply voltage, VS, is
normally tied to the car's battery voltage. The Vbat pin can
sustain up to 40 V dc. Care should be taken to provide any
additional reverse battery and transient voltage protection in
excess of 40 V.
The voltage reference generator is supplied from both VCC
and Vbat pins. The voltage reference generator provides a
reference voltage for the K and L Line comparator
thresholds. The reference voltage is dependant on the Vbat
voltage; it is linear in relation to the Vbat voltage for all Vbat
voltages between 5.6 V and 18 V. Below 5.6 V and over 18 V
the reference voltage is clamped (see Figure 11). The
REF-OUT pin connects the reference voltage out externally
making it available for other application needs. The
REF-OUT pin is capable of supplying a current of 50 ~ (see
Figure 12).
Path Functions Between MCU, K and L Lines
The path function from the MCU to the K Line uses a driver
to interface directly with the MCU through the TXD pin. The
TXD pin is CMOS compatible. This driver controls the On-Off
conduction of the power transistor. When the power
transistor is On, it pulls the DIA pin low. This pin is known as
K Line in the ISO 9141 specification. The DIA pin structure is
open collector and requires an external pull-up resistor for
use. Having an open collector without an internal pull-up
resistor allows several MC33199 to be connected to the K
Line while using a single pull-up resistor for the system (see
Figure 6). In order to protect the DIA pin against short circuits
to Vbat, the MC33199 incorporates an internal current limit
(see Figure 16) and thermal shutdown circuit. The current
limit feature makes it possible for the device to drive a Kline
bus having a large parasitic capacitor value (see Special
Functionality of 11 pin below).
The path from the DIA pin, or K Line, to the MCU is done
through a comparator. The comparator threshold voltage is
connected to REF-IN-K pin. It can be tied to the REF-OUT
voltage if a Vbat dependant threshold is required in the
application. The second input of this comparator is
connected intemally to DIA pin. The output of this comparator
is available at the RXD output pin and normally connects to
an MCU I/O port. RXD pin has a 2.0 kn internal pull-up
resistor.
10-92
The path from the L Line, used during a wake-up
sequence of the transmission, to the MCU is done through a
second comparator. The comparator threshold voltage is
connected to REF-IN-L pin. The REF-IN-K pin can be tied
to the REF-OUT voltage if a Vbat dependant threshold is
required in the application. The second input of this
comparator is internally connected to L pin. The output of this
comparator is available on LO output pin, which is also an
open collector structure. The LO pin is normally connected to
an MCU I/O port.
The DIA and L pins can sustain up to 40 V dc. Care should
be taken to protect these pins from reverse battery and
transient voltages exceeding 40 V.
The DIA and L pins both have internal pull-down current
sources of typically 7.5 ~A (see Figure 14). The L Line
exhibits a 10 ~A pull-down current. The DIA pin has the
same behavior when it is in "off" state, that is when TXD is at
logic high level.
Special Functionality of 11 Pin
The MC33199 has a unique feature which accommodates
transmission baud rates of up to 200 k baud. In practice, the
K Line can be several meters long and have a large parasitic
capacitance value. Large parasitic capacitance values will
slow down the low to high transition of the K Line and limit the
baud rate transmission. For the K Line to go from low to high
level, the parasitic capacitor must first be charged, and can
only be charged through the pull-up resistor. A low pull-up
resistor value would result in fast charge time of the capacitor
but also large output currents to be supplied causing a high
power dissipation in the driver.
To avoid this problem, the MC33199 incorporates a
dynamic current source which is temporarily activated at the
low to high transition of the TXD pin when the DIA pin or K
Line switches from a low to high level (see Figures 3 and 4).
This current source is available at the 11 pin. The 11 pin has
a typical current capability of 80 mAo It is activated for 4.0 ~
(see Figures 21 and 22) and is automatically disabled after
this time. During this time it will charge the K Line parasitic
capacitor. This extra current will quickly increase the Kline
voltage up to Vbat, resulting in a reduced rise time of the K
Line. With this feature, the MC33199 ensures baud rate
transmission of up to 200 k baud.
During high to low transitions of the K Line, the parasitic
capacitor of the line will be discharged by the output
transistor of the DIA pin. In this case, the total current may
exceed the internal current limitation of the DIA pin. If so, the
current limit circuit will activate, limiting the discharge current
to typically 60 mA (see Figures 4 and 16).
If a high baud rate is necessary, the 11 pin should be
connected to the DIA as shown in the typical application
circuit shown in Figure 5. The 11 pin can be left open, if the 11
functionality and high baud rate are not required for the
application.
MOTOROLA ANALOG IC DEVICE DATA
MC33199
PIN DESCRIPTION
Pin 1: VCC
Power Supply pin; typically 5.0 V and requiring less than
1.5 mAo
Pin 2: REF-IN-L
Input reference for C2 comparator. This input can be
connected directly to REF-OUT with or without a resistor
network or to an external reference.
Pin 3: REF-IN-K
Input reference for C1 comparator. This input can be
connected directly to REF-OUT with or without a resistor
network or to an external reference.
Pin 4: LO
Output of C2 comparator and normally connected to a
microcontroller 1/0. If L input> (REF-IN-L + Hystl2); output
LO is in high state. If L< (REF-IN-L - Hystl2); output LO is in
low state and the output transistor is "on". This pin is an open
collector structure and requires a pull-up resistor to be
connected to VCc. Output drive capability of this output is
5.0mA.
Pin 5: RXD
Receive output normally connected to a microcontroller
1/0. If DIA input> (REF-IN-L + Hystl2); output LO is in high
state. If DIA < (REF-IN-L - Hystl2); output LO is in low state
and the output transistor is "on". This pin has an internal
pull-up resistor (typically 2.0 kQ) connected to VCC. Drive
capability of this output is 5.0 mAo
Pin 6: TXD
Transmission input normally connected to a
microcontroller 1/0. This pin controls the DIA output. If TXD is
high, the output DIA transistor is in the "off" state. If TXD is
low, the DIA output transistor is "on".
Pin 9: DIA
InputlOutput Diagnosis Bus line pin. This pin is an open
collector structure and is protected against overcurrent and
MOTOROLA ANALOG IC DEVICE DATA
circuit shorts to Vbat and VS. Whenever the open collector
transistor turns "on" (TXD low), the Bus line is pulled to
ground and the DIA pin current is internally limited to nominal
value of 60 mAo The internal power transistor incorporates a
thermal shutdown circuit which forces the DIA output "off" in
the event of an over temperature condition. The DIA pin is
also the C1 comparator input. It is protected against both
positive and negative overvoltages by an internal 40 V zener
diode. This pin exhibits a constant input current of 7.5 flA.
Pin 10: Gnd
Ground reference for the entire device.
Pin 11: 11
Bus source current pin. It is normally tied to DIA pin and to
the Bus line. The current source 11 delivers a nominal current
of 3.0 mA at static "High" or "Low" levels of TXD. Only during
"Low" to "High" transitions, does this current increase to
a higher value so as to charge the key line capacitor
(CI < 4.0 nF) in a short time (see Figures 3 and 4).
Pin 12: L
Input for C2 comparator. This pin is protected against both
positive and negative overvoltage by a 40 V zener diode. This
L Line is a second independent input. It can be used for wake
up sequence in ISO diagnosis or as an additional input bus
line. This pin exhibits a constant input current of 7.5 flA.
Pin 13: Vs
12 V typical, or Vbat supply pin for the device. This pin is
protected against overvoltage transients.
Pin 14: REF-OUT
Internal reference voltage generator output pin. Its value
depends on Vs (Vbat) values. This output can be directly
connected to REF-IN-L and REF-IN-K, or through a
resistor network. Maximum current capability is 50 flA.
10-93
®
MOTOROLA
MC33293A
Advance Information
Quad Low Side Switch
The MC33293A is a single monolithic integrated circuit designed for quad
low side switching applications. This device was initially conceived as a quad
injector driver for use in the harsh automotive environment but is well suited
for many other applications. The MC33293A incorporates SMARTMOS'M
technology having CMOS logic, bipolar and CMOS analog circuitry and
DMOS power MOSFETs. All of the device inputs are CMOS compatible. The
four output devices are N-channel power MOSFETs. A Fault detect output is
provided to flag the existence of open loads (outputs ON or OFF) or shorted
loads. If a short circuit is detected, the fault detect circuitry turns off the
shorted output, but allows the others to function normally. An overvoltage
(VPWR) condition will turn off all outputs for the overvoltage duration. Each
output functions independently and has a drain-to-gate diode clamp for
inductive flyback voltage protection. A Single/Dual select pin is incorporated
to allow either individual output control or control of a pair of outputs from one
input.
The MC33293A is parametrically specified over - 40°C $; TA $; 125°C
ambient temperature and a 9.0 V $; VPWR $; 14.5 V supply.
• Designed to Operate with Supply Voltages of 5.5 V to 30 V
• CMOS Compatible Inputs with Active Pull-Downs
QUAD LOW SIDE SWITCH
= 0.25 Q Max per Output)
(ROS(on)
SEMICONDUCTOR
TECHNICAL DATA
TSUFFIX
PLASTIC PACKAGE
CASE821D
• Maximum 5.0 mA Quiescent Current
• RDS(on) of 0.25 Q Maximum at 25°C, with VPWR ;?: 9.0 V
• Each Output Clamped to 65 V for Driving Inductive Loads
• Each Output Current Limited at 3.0 A to handle Incandescent
Lamp Loads
• Active Low Output Fault Status with Interrogation Capability
• Open Load Detection (Output ON or OFF)
TV SUFFIX
PLASTIC PACKAGE
CASE 821C
• Capable of Withstanding Reverse Battery
• Overvoltage Shutdown
• Short Circuit Detection and Shutdown with Automatic Retry
PIN CONNECTIONS
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
TJ =-40° to +150°C
15 Pin SIP
MC33293AT
MC33293ATV
Pin 1.
2.
3.
4.
5.
6.
7.
8.
Output 2
Output1
Input 1
Input2
Input 1 &2
Single/Dual
VPWR
Gnd
9. N/C
10.Fault
11.lnput3&4
12. Input 4
13.lnput 3
14. Output 3
15.0utput4
10-94
MOTOROLA ANALOG IC DEVICE DATA
MC33293A
Simplified Block Diagram
7
+VPWA
----------,I
~~~
I
I
~OulpUI2
I-!
OuIpUI3
115
t-o Oulpul4
5
Input 1 &2
I
I
I
I
I
I8
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _
From
Detectors
2,3,4
_ _ _ _ _ _ _ _ _ JI
Groond
MAXIMUM RATINGS
Rating
VCC
Steady-State
Transient Conditions
Input Pin Voltage
ESD Capability
Human Body Model (R = 1.5 kn, C = 200 pI)
Lead Current (per Output)
Symbol
Value
VpWR
VPWR(pk)
-13 to 30
-13to60
Vin
-0.5t07.5
Unit
V
V
V
VESD
2000
Intemally
Limited
A
Eclamp
100
mJ
Tstg
- 55 to +150
'C
TJ
-40to+150
'c
Tsolder
260
°c
PD
11.25
6.25
0.25
W
wrc
Thermal Resistance Junction-to-Ambient
RaJA
35
°CIW
Thermal Resistance Junction-to-Case.
Any one O/P
R9JC
4.0
°CIW
Single Pulse Clamp Energy @ 25'C, 1.5 A
Storage Temperature
Operating Temperature
Lead Temperature (Wave Solder, 10 s)
Power Dissipation @ TA = 105°C
Power Dissipation @ TA = 125°C
Derate lor every °c above 25°C
MOTOROLA ANALOG IC DEVICE DATA
lOut
10-95
MC33293A
STATIC ELECTRICAL CHARACTERISTICS (9.0 V ~ VpWR $ 14.5 V and - 40°C ~ TC ~ + 125°C, unless otherwise
noted. Typical values are at 25°C, unless otherwise noted.)
I
Characteristic
Symbol
Min
TYP
Max
Unit
Von(th)
-
3.4
5.5
V
VPWR
5.5
-
30
V
INPUT
Turn ON Threshold
Operating Voltage Range
IpWR
-
2.2
5.0
mA
Overvoltage Shutdown Range
VPWR(ov)
30
35
38
V
Overvoltage Reset Hysteresis
VPWR(hys)
2.0
5.0
7.0
V
VIH
VIL
3.0
-
2.3
1.6
0.8
VIH(hys)
0.4
0.7
-
-
-
11
11
50
50
-
0.18
0.28
0.20
0.22
0.25
0.50
0.40
0.50
55
64
80
10
-
23
0.06
80
2.0
rnA
-
0.62
1.4
V
Quiescent Power Supply Current (All Inputs 011)
Input Voltage
High (lOS 1.0 A)
Low (lOS 80 !LA)
=
=
Input High Hysteresis (lOS
=1.0 A)
Input Current
High (VIH 3.0 V)
Low (VIL 0.8 V)
=
=
IIH
IlL
V
V
!LA
OUTPUT
Static Drain-Source On-Resistance
(lOS 1.0 A, VPWR 13 V, TC
(lOS 1.0 A, VPWR 13 V, TC
(lOS 0.7 A, VPWR 8.0 V, TC
(lOS 0.4 A, VpWR 5.5 V, TC
ROS(on)
Drain-Source Clamp Vottage
(los 20 rnA, Vin 0 V,lclarnp
BVOSS
=
=
=
=
=
=
=
=
=
=
=-40°C to + 25°C)
=+125°C)
=+ 25°C)
=+ 25°C)
=100 !1S)
Zero Input Voltage Drain Current
(VOS 25 V, VpWR 14.5 V)
(VOS 58 V, VPWR 14.5 V)
=
=
10-96
V
lOS (011)
=
=
Source Drain Diode Forward Voltage (ISO
g
=1.0 A)
VSO
!LA
MOTOROLA ANALOG IC DEVICE DATA
MC33293A
STATIC ELECTRICAL CHARACTERISTICS (continued) (9.0 v
noted. Typical values are at 25°C, unless otherwise noted.)
I
Characteristic
,,; VPWR ,,; 14.5 V and - 40°C,,; TC ,,; + 125°C, unless otherwise
Symbol
Min
Typ
Max
Unit
FAULT STATUS OUTPUTT
Fault Status Pin
Low Voltage (VpWR = 14.5 V, Isli = 1.0 rnA, open-load on
Output I, 2, 3 or 4. All inputs = 0 V)
High Voltage, (VPWR
= 14.5 V, Isth =- 30~, Note 1)
V
VsII
-
0.1
0.4
Vsth
3.0
4.7
5.5
IDS(limit)
3.0
4.0
6.0
A
VOC(limit)
VOoff(thl
2.4
2.4
3.7
3.7
5.0
5.0
V
20
20
80
75
190
130
20
65
100
Min
Typ
Max
FAULT DETECTION
Output Limiting Current (VPWR
= 13 V)
Over-Current Detect Voltage Threshold and
Output-Off Open-Load Detect Threshold Voltage
output-on open-load Detect Current
(VpWR = 13 V, Yin =5.0 V, TC =- 40°C)
(VPWR = 13 V, Yin = 5.0 V, TC =+ 25°C)
(VPWR
rnA
IOon(th)
= 13 V, Yin =5.0 V, TC =+125°C)
DYNAMIC ELECTRIC CHARACTERISTICS
I
Characteristic
Symbol
Unit
OUTPUT TIMING
Output Driver Rise Time (VCC = 13 V, RL = 13 n,
tr =Output Voltage change from 90% to 10%, see Figure 2)
tr
-
2.3
10
Output Driver Fall Time (VCC = 13 V, RL = 13 n,
tf = Output Voltage change from 10% to 90%, see Figure 2)
tf
-
1.5
10
-
3.2
5.9
10
15
10
55
250
1.5
3.6
7.0
Output Delay Time (VCC = 13 V, RL = 13 n,
ton(dly) = Yin at 3.0 V to Vo at 90%, see Figure 2)
Ioff(dly) =Yin at 1.0 V to Vo at 10%, see Figure 2)
ton(dly)
Ioff(dly)
-
j.lS
j.IS
j.IS
FAULT TIMING
Over-Current Sense Time (See Figure 5 or 6)
(Vin = 5.0 V, RL = 0.05 n, VPWR = 14.5 V,
over-current duty cycle,,; 10%
lac
j.IS
toc =time that VStatus is > 1.0 V)
Over-Current Refresh Time (See Figures 5 or 6)
(Vin =5.0 V, RL =0.05 n, VPWR = 14.5 V,
over-current duty cycle,,; 10%
ms
tref
tref =time that VStatus is < 1.0 V)
Output Open-Load Fault Status Delay Time
(VPWR = 13 V, Yin =5.0 V, open-load on Output,
tos(on) =time from Yin = 3.0 V to VStatus = 1.0 V, see Figure 3)
(VPWR = 13 V, Yin
=0 V, open-load on Output,
tos(off) =time from Yin = 2.5 V to VStatus = 1.0 V, see Figure 4)
Fault Status Reset Delay Time
(VPWR = 13 V, Yin =0 V, see Figure 4)
ms
Ios(on)
1.0
2.2
4.0
1.0
19
40
-
2.0
10
j.IS
tos(oll)
ts(reset)
j.lS
NOTE: 1. Negative current signifies current flowing out of device.
MOTOROLA ANALOG IC DEVICE DATA
10--97
MC33293A
Figure 1. Fuel Injector Application Block Diagram
VLoad
(Battery)
MC68HC11A1
+14V
-=-
J-
I
7
r-------------~----~~
II
OC2b-__I~np_ut_l~~~~~
OC3b-__I~np_ut_2~~~~~
Input 3
OC4
Input 4
OC5
Input 1 & 2
Open
Load
Detect
PD~
POl
II
Select
Short
CircuH
Detect
Input 3&4
PD2
Open
Load
Detect
IRQ
Short
CircuH
Detect
II
Fault
Open
Load
Detect
Short
CircuH
Detect
II
115
1
1
Open
Load
Detect
1
1NOTE: 1. The MC33293A
1is also designed to drive
1the 194 type incandescent
1instrument lamp.
Short
Circuit
Detect
1
1
L
1 ____________________________
10-98
~_
J8
MOTOROLA ANALOG IC DEVICE DATA
MC33293A
Figure 2. Switching Speed Test CircuH and Response Times
J:
13V
13V
load
Test Circuit
13n
VPWR
Input n.
10V---
-"v
50n
Yin
Input
7
Oull ~
Out 2 1
Oul3 -'-'-Oul4 JL
~ Inpull
4 Input 2
---"'- Inpul3
--R Inpul4
-"it
Vo
M
--.1Q. Stalus
50n
MC33293A
OV
I
--1
I
100115
5 Inpull &2
11 Inpul3& 4
6
Selecl
I
I--
Gnd 8
I
2% Duty Cycle
Gnd
L
Response Times
'Y:---~f- ,~
~i·
OV
\-,~
11...·-----
1
1
1
1
1
'".."'I~--Ion - -.......~I
1
-1
I
Ion(dly)
J-- Ir ---:
1
1
1
I..
.1
loll
1
: - - - Ioll(dly)
I
.1..
1
1
1
I
:
1
1
1
1
1
1
1
1
1
1
1
1
I
If
---I
1
1
1
%---_: ___ l ______________ J___ :~----
1 3 V - - - - -g0
Vo
1
1
1
1
10%
OV - - - - - - - - - - - - - - '--_ _ _ _ _ _ _ _ _ _--.J
MOTOROLA ANALOG IC DEVICE DATA
16-99
MC33293A
Figure 3. Fault Status Operation with an Output-On, Open-Load Fault
3.0V
I
I
S.OV _ _ _...JI' - - _ - - - . .
',,: _____L___~'-=----1-.0-V---------J/
:---------------------1----------_-~";"
I-- Ios(on) '---1
I
I
~-
OpenReported
Load
Fault
-
-
1.0A
' " Open Load
Fault Ends
" If the open occurs after the output has been on,
the delay time is much less than tos(on)'
NOTE: Rise and fall times are exaggerated for emphasis.
Figure 4. Fault Status Operation with an Output-Off, Open-Load Fault
S.OV~
~-- 2.SV
Vln
ov-----L '-.- - - - - - - - - - - - - - - - - - - - - - - - - - I
I
I
---+-I-----..~
S.OV
VStatus
(All Outputs Off)
I
I
r-
_
I
r- Is(reset)--J
I
;/1
_ _
1'-.
I
- ------
3.0V
1.0V
ov ----T-------+-''-------+I----'
Ios(off)
"--1
Open Load
Fauh Reported
I
I
_ j f r - - - - - - - - - - - - - - - Vload
:: _______________--'7------------• If the open occurs after the output has been all, the
delay time is much less than Ios(oll)'
VOoff(th)
' " Open Load
FauhEnds
NOTE: Rise and fall times are exaggerated for emphasis.
10-100
MOTOROLA ANALOG Ie DEVICE DATA
MC33293A
Figure 5. Fault Status Operation with TUrn On Into an Over-Current Load
~
l _____
I
5.0V
VFault
Statu
ov, ____
I
I.-- lac
I
I
I
I
10
:
OA - - - - (
I
/
----1·9X-----X--
_=_
I
-I-
.N
I
':5-- tref -----1
Output
Shutdown
I
I
I
I
I
IOS(limit)
'---___.---1.0A
(Normal load)
Over-Current
condition at Tum On
NOTE: Rise and fall times are exaggerated for emphasis.
Figure 6. Fault Status Operation with Over-Current Load after Turn On
5.0V - - - - - - ,----------~J;~-------------~
_
""Vln
- -
3.0V
""
OV
5.0V
'------
------l---___.
I
VFault Status
OV - - -
-1-____
...=--+,_-_-_-....,lfJ·O;;..V_-_-_-.,
I
I
I
I
I
10
I
I
1.0A----iOA - - - - ¥
I
r-------:r.f- tref ---~- toe-----1
I
\
lOver-Current
Refresh
(Turn on and test load)
condition occurs
NOTE: Rise and fall times are exaggerated for emphasis.
MOTOROLA ANALOG IC DEVICE DATA
10-101
MC33293A
Figure 7. Turn On-Threshold Voltage
versus Temperature
~
6.0
w
Cl
!:i
§2 5.0
VPWR=V~th)
VOS= 14.5
Vin =5.0V
Figure 8. Output On Resistance
versus Temperature
§
~
,
~
Cl
...J
4.0
0
:I:
in
a:
W
3.0
j!:
~
z
0
0.18
§
0.16
-20.14
-E.
-~
0
~
W
~
TA, AMBIENT TEMPERATURE (Oe)
100
125
Figure 9. Drain Source Clamp Voltage
versus Temperature
~
~
Bor----,----,---,----,----r---.----,
r- Vos = BVoss
~
VPWR=14.5V
76 I- Vin = Open
+---+--+--+--1----1
~
0-
~ nl__-~--+_-_+--+_-~---I__--~
w
1f
~
6BI-----1--+---+--+--+--I----1
@
z
~ 64~~~----+=--~----+----t----r---1
~
~
~~~----~25----~---2~5----5~0----7~5----10~0--~125
Figure 11. Current Limit
versus Temperature
6.0 r - - - - , - - , - - - , - - r - - - , . . . - - - - , , - - . . . ,
VOS=2.BV
5.5 VPWR=13V
Vin = 5.0 V
!:::
::;;
::J
!z
~
a
5.01----+--+---+--+--+---11----1
1f
~
4.51----t--+---+--+--~----I1---~
w
@
~ 4,oE=1::j:=j=j::~==~~
w
3.51__-~--+_--+--+_-~--1__-~
:::J
if 3.0 1-..__
....J____..l-__-1.____.l.-__-'-..:.-__L -__~
-55
10-102
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (Oe)
100
125
../
-----
8 0.12
a: 0.10
-55
!z
~
-25
./
./
/"
./
./
0
25
50
75
TA, AMBIENT TEMPERATURE (Oe)
100
125
Figure 10. Zero Input Voltage Drain Current
versus Temperature
BOr-----,,---,---,--,---,--r--,
VDS=2~V
w
~
70
60
w
501-----11----j---t--+---+--1---~
~
!:i
Cl
~
~
VpWR = 14.5 V
Vin=OV
401-----11----j---t--+---+--1---~
30~--~--_+--_+--_1--~r_--r____l
~ 20~~~~==~==~====~~:t:=:=~::~
~
i:!:l
~
8
TA, AMBIENTTEMPERATURE (Oe)
g
",
0.22
~ 0.20
(f)
a:
0.30
0.2B _IO=1.0A
VpwR= 13 V
0.26 - Vin=5.0V
0.24
~
101------I1---~--t--+---+--r--~
O~--~--~----~--~--~--~--~
-55
-25
25
75
50
TA, AMBIENTTEMPERATURE (Oe)
100
125
Figure 12. Open-Load Threshold
versus Temperature
g
5.0
ill
a:
4.5 f- VPWR = 13 V -+----+----I-----j----+----I
Vin = 0 v
b
tii
4.0
~
3.5
O~
3.0 1------1----+----+----t----I----j---I
j!:
1.
I-VOS=13V
t=:;;;~~*==l=~t:::t==t:=~
1~
>
~
~
2.5
__ ____-'-__.....L____..L__ __ ' __ _ _ _
-55
-25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (Oe)
_ _....I
125
MOTOROLA ANALOG IC DI;VICE DATA
MC33293A
PIN DESCRIPTION
Pin
Function
Description
1
Output 2
This is one of four open drain power MOSFET output connections. The load is connected from
this pin to the positive voltage supply.
2
Output 1
This is one of four open drain power MOSFET output connections. The load is connected from
this pin to the positive voltage supply.
3
Input 1
This input controls the turn ON and turn OFF of Output 1 when the Single/Dual pin is at a logic
low level. It is a CMOS input with an internal active pull-down employed for noise immunity.
4
Input 2
This input controls the turn ON and turn OFF of Output 2 when the Single/Dual pin is at a logic
low level. It is a CMOS input with an internal active pull-down employed for noise immunity.
5
Input 1 & 2
This input controls the turn ON and turn OFF of Output 1 and Output 2 when the Single/Dual
select pin is at a logic high level. It is a CMOS input with an internal active pull-down employed
for noise immunity.
6
Single/Dual
Select
This input selects between the single (one input controls one output) mode and the dual
(one input controls two outputs) mode of operation.
7
VpWR
The pO'Ner (voltage and current) to operate the IC is supplied through this pin. The MC33293A
is designed to operate over a voltage range of 5.5 V to 30 V.
8
Ground
IC ground reference pin.
9
N/C
No connection.
10
Fault
One of three fault conditions, Output-On Open-Load, Output-Off Open-Load or Over-Current are
reported at this outP'Jt. A logic low state signals the existence of a fault condition. This output
has an internal active pull-up and does not require an external pull-up resistor.
11
Input 3 & 4
This input controls the turn ON and turn OFF of Output 3 and Output 4 when the Single/Dual
select pin is at a logic high level. It is a CMOS input with an internal active pull-down employed
for noise immunity.
12
Input 4
This input controls the turn ON and turn OFF of Output 4 when the Single/Dual pin is at a logic
low level. It is a CMOS input with an internal active pull-down employed for noise immunity.
13
Input 3
This input controls the turn ON and turn OFF of Output 3 when the Single/Dual pin is at a logic
low level. It is a CMOS input with an internal active pull-down employed for noise immunity.
14
Output 3
This is one of four open-drain power MOSFET output connections. The load is connected from
this pin to the positive voltage supply.
15
Output 4
This is one of four open-drain power MOSFET output connections. The load is connected from
this pin to the positive voltage supply.
CIRCUIT DESCRIPTION
Introduction
The MC33293A is a four output low side switch originally
intended for use in automotive applications as a fuel injection
driver. This circuit can be used in a variety of applications. It
is parametrically specified over a battery voltage range of
9.0 V to 14.5 V, but is designed to operate over a
considerably wider range of 5.5 V to 30 V. The design
incorporates the use of logic level MOSFETs as output
devices which are fully enhanced at a gate voltage of 5.0 V,
eliminating the need for internal charge pumps. Each output
is identically sized and is independent in operation. The
efficiency of each output device is such that with as little as
9.0VofVPWRapplied,the RDS(on) isO.18ntypically, at room
temperature and increases to only 0.22 n as VPWR
decreases to 5.5 V.
All inputs of the MC33293A are CMOS and have individual
11 J.lA internal active pull-downs. This eliminates the need for
external pull-down resistors to prevent false switching due to
noise on the input control lines. This also ensures that at
MOTOROLA ANALOG IC DEVICE DATA
power-up, no load is turned on before a logic high appears on
an input pin. Fault reporting is through the use of an
open-drain MOSFET having a 100 J.lA internal active pUll-Up.
All inputs incorporate true logic (or positive logic). This
means that whenever an input is in a logic low state « 0.8 V)
the corresponding output will be in an OFF state. Conversely,
whenever an input is in a logic high state (> 3.0 V), the
corresponding output will be in an ON state.
Single/Dual Select
The Single/Dual Select pin can be used to switch between
completely independent control and control of the outputs in
pairs. Whenever the Single/Dual Select pin is in a logic low
state, Inputs 1, 2, 3 and 4 control Outputs 1, 2, 3 and 4,
respectively. In this mode, only Inputs 1, 2, 3 and 4 can
exercise individual control over their respective output.
Hence the term "single select" mode of operation. Input 1 & 2
(Pin 5) and Input 3 & 4 (Pin 11) have no control whenever the
Single/Dual Select pin is in a logic low state.
10-103
MC33293A
When the Single/Dual Select pin is held at a logic high
state, Control Inputs 1,2, 3 and 4 are turned OFF and can not
exercise any control over the outputs. In this mode, input
control transfers from a single to a dual mode of operation,
wherein only Input 1 & 2 and Input 3 & 4 have control of
Output 1 plus Output 2, and Output 3 plus Output 4,
respectively. Hence the term "Dual Select" mode of
operation.
Paralleling Outputs
Paralleling outputs may be desirable in the event the
application requires a lower RDS(on) or higher current
switching capability than a single output. The MC33293A can
be operated with all outputs (and therefore all Inputs) tied
together but modified operation is to be expected. With all
inputs tied together and depending on the dual or single
select mode used, the paralleled input control current will
either be twice (with the dual mode selected) or four times
(with the single mode selected) that of any single Input. Other
expected differences are: RDS(on) will decrease by a factor of
four while the Output-On Open-Load Detect current and the
Output Limiting current will Increase by a factor of four. There
will be no change In the Over-Voltage Shutdown Range or
the Output-Off Output-On Open-Load Detect Threshold
Voltage Range. As always, system level thermal design and
verification are important when outputs are paralleled.
FAULT LOGIC OPERATION
General
The Fault Status output (Pin 10) on the MC33293A reports
anyone of three possible faults from anyone of the four
outputs. The three possible faults are output-on open-load
Fault, output-off open-load Fault and over-current Fault. All
faults from any of the four outputs are OR'd together and
reported by the single Fault Status output-on Pin 10
(Figure 13).
Figure 13. MC33293A Fault Logic Diagram
Output·Off open·load Fault Report 1
Output-Off open·load Fault Report 2
Output·Off open·load Fault Report 3
Output·Off open·load Fault Report 4
+
1001lA
Input 1 >-----r--."
,-------"
Input 2 >----+--r--."
,-----,-,
Input 3 >---t--r--...,L------'---"--'
Input 4 :>---+--r--...,L------'---"--'
Single/Dual Select
Inputt &2
>----+l~~
Input 3 & 4 >-----1_
output-on open·load Fault Report 1
output-on open-load Fault Report 2
:>--+H+-i
output-on open-load Fault Report 3 >--t-f-tt-i
output·on open·load Fault Report 4 >--t-f-tt-L~
output-on Over-Current Fault Report 1 >--+t+---1
output-on Over-Current Fault Report 2 >--+t----1
10-104
output-on Over-Current Fault Report 3
>--+----1
output-on Over-Current Fault Report 4
>-----L~
MOTOROLA ANALOG IC DEVICE DATA
MC33293A
Output-On open-load Fault
The MC33293A always checks for an open-load on the
outputs whether the outputs are ON or OFF. An output-on
open-load Fault is detected if an open-load exists when the
output is ON (corresponding input at a logic high state). The
output-on open-load Fault detection occurs when the load
current is less than the minimum Output-On Open-Load
Detect current (lOon(th», specified in this data sheet. The
value of IOon(th) is, typically, 75 mA at room temperature.
See Figure 3.
The minimum load resistance value that the MC33293A
will i~terpret as an output-on open-load (Ropen(on» is a
function of; the Output-On Open-Load Oetect current
(iOon(th»; the load supply voltage (Vload); and the resistance
of the output (ROS(on», as shown below.
Ropen(on) =[Vload IIOon(th)l(1)
ROS(on) ~ Vload IIOon(th)
Using Equation 1 for the steady state case,
when: Vload = 14 V
ROS(on) =0.3 n
IOon(th) =75 mA
an output-on open-load Fault will be detected and reported
whenever Rload 2: 187 n.
Each output has an output-on open-load fault detect circuit
that performs real time load current monitoring. Load current
is monitored immediately after any output is turned ON.
Since it takes a finite amount of time for load current to begin,
the MC33293A detects an output-on open-load Fault from
the time the output is turned ON until the load current
e~c~eds the Output-On Open-Load Oetect current (lOon(th».
It IS Important to note that a fault will not be reported at the
Fault Status output during this short period of time. This is
due to the built-in output-on open-load Fault Status Delay
Time (toson), see Figure 3. This delay time is incorporated in
the MC33293A to mask the reporting of a false output-on
open-load Fault at the Fault Status output. The delay is
typically 2.2 ms.
The purpose for the tos(on) delay is to prevent false fault
reporting, especially when driving inductive loads. The load
inductance causes a current lag when the load is turned ON.
The normal current lag of an inductive load could be
misinterpreted as an open-load if it weren't for the bUilt-in
delay. This delay or masking is accomplished internally with
a single timer which resets every time any input switches from
a low-to-high logic state. An output-on open-load Fault will be
reported by the Fault Status output as a result of turning ON
an output having an open-load Fault and the most recent
tos(on) is allowed to lapse after switching ON any input.
T~e time it takes the load current to reach IOon(th) is a
function of the load resistance (Rload); load inductance
(Lload); output on resistance (ROS(on»; load supply voltage
(Vload); and the turn-on time (ton) as shown below. The value
of ton is comprised of the low-to-high Yin propagation delay
time (ton(dly», and the output voltage rise time (t r).
See Figure 2.
ton (false fault) =- 't In [(I00n(th)- Iload)1
(2)
(- Iload)] + ton
",here:
=Lload I Rload =time constant
(3)
Iload =Vload I [Rload + ROS(on)l
(4)
't
ton
=ton(dIV) + tr
MOTOROLA ANALOG Ie DEVICE DATA
Using Equation 2 for the transient case,
when: Vload =14 V
ROS(on) =0.3 n
Lload =10 mH
Rload =14n
IOon(th) =75 mA
an output-on open-load Fault will be detected, but not
reported after initial turn ON for a duration of 57 I.ls + ton.
Output-Off open-load Fault
The MC33293A checks for open-loads on the outputs
regardless of an output being on or off. An output-off
open-load Fault is detected if an open-load exists when the
output is turned OFF (corresponding input at a logic low
state). When anyone of the four outputs are turned OFF, an
independent internal current source tied to each output tries
to pull a small amount of zero input voltage drain current
(lOS(off), typically 23I.lA), through the load. If, while this zero
input voltage drain current is being pulled through the load,
the output voltage is less than the output-off open-load
Oetect Threshold Voltage (VOoff(th), typically 3.7 V), an
output-off open-load Fault will be detected.
The zero input voltage drain current could be provided by
a large external resistor connected from the output to ground.
However, if an external resistor were used to provide this
zero input voltage drain current, only "opens" resulting from
open-loads or output to ground shorts could be detected. The
external resistor could not guarantee detection of an open
resulting from an output wire bond failure internal to the
MC33293A. Because the current source is provided
internally, open loads, output to ground shorts, and loss of
output wire bonds will all be detected.
The value of load resistance that will be detected as an
output-off open-load (Ropen(off), is a function olthe zero input
voltage drain current (lOS(off»; the load supply voltage (Vload);
and the output-off open-load Detect Threshold Voltage
(VOoff(th», as shown next by:
(6)
R
( ff) _ [Vload - VOoff(th)l
10S(off)
open 0 USing Equation 6 for the steady state case,
when: Vload =14 V
IDS(off) =23 I.lA
VOoff(th) =3.7 V
an output-off open-load Fault will be detected and reported
whenever RL 2: 448 kn.
.
Each output has an output-off open-load fault detect circuit
that performs real time output voltage monitoring. Output
voltage is monitored immediately after any output is turned
off. A finite amount of time is required for output voltage to
rise. The MC33293A detects an output-off open-load Fault
from when an output is turned off until the output voltage
exceeds the output-off open-load Oetect Threshold Voltage
(VOoff(th». It is important to note a fault will not be reported at
the Fault Status output during this rise time. This is due to the
built-in.output-off open-load Fault Status Delay Time, tos(off),
see Figure 4. This delay time is incorporated in the
MC33293A to delay the reporting of an output-Off open-load
Fault at the Fault Status Output. The delay is typically 19 I.ls.
(5)
10-105
.,..
IIiiI
MC33293A·
The purpose for the tos(off) delay is to prevent false fault
reporting experienced with capacitance type loads. The load
capacitance causes the rise in output voltage to lag even
after the load has been turned OFF. The normal voltage lag
caused by load capacitance could be misinterpreted as an
open-load if it weren't for the built-in delay. This delay, or
masking, is accomplished with four separate timers that reset
independent of each other when the corresponding input is
switched from a high to a low logic state. Internal logic
prevents an output-off open-load Fault from being reported at
the Fault pin when any input is high. An output-off open-load
Fault will be reported at the Fault Status pin after an open
load occurs, all inputs not corresponding to the faulted output
are low and a time in excess of tos(off) is exceeded after
switching OFF the input corresponding to the faulted output.
An important note that bears repeating is that an output-off
open-load Fault will not be reported at the Fault Status pin
unless all input pins are at a logic low state (Figure 13). This
is a Fault Status interrogation feature. It helps in
distinguishing between an output-on open-load Fault and an
output-on over-current Fault. (Fault Status interrogation is
explained in greater detail in a later section).
The time the output voltage takes to reach VOoff(th) after
being turned OFF is toff false fault. It is a function of the load
resistance (Rload); load inductance (Lload); load current
(lload); output-on resistance (ROS(on», output capacitance
(CO); load supply voltage (Vload); and the turn OFF time (Ioff).
The value of toff is comprised of the Yin high-to-Iow
propagation delay time (Ioff(dly», and the output voltage fall
time (tf).
For the case when:
1/2 Lload (1Ioad):'::» 1/2 Co (VOoff(th»:'::
(7)
Ioff false fault =[(CO flV) / Iload] + toff
where: Iload =Vload / [Rload + ROS(on)]
flV = VOoff(th) - [I load ROS(on)]
(8)
(9)
(10)
toff =toff(dlv) + tf
(11)
Using Equation 7 for the transient case,
when: Vload =14 V
ROS(on) =0.3 n
Lload =10 mH
Rload = 14 n
Co =0.001 /!F
VOoff(th) =3.7 V
an Output-Off open-load Fault will be detected but not
reported after initial turn OFF for a duration of 3.5 ns + toff.
From Equation 7, the energy stored in the load inductor will
be 4.8 mJ. This is much greater than the 68 nJ needed to
charge the output capacitance. This allows the use of
Equation 8 in determining the false output-off open-load Fault
duration following turn OFF because it assures that the
output capacitance will be charged by the energy stored in
the load inductance.
Over-Current Fault
An over-current (short circuit or current limit) Fault is the
detection and reporting of any output over-current condition.
An over-current condition is defined as a condition where
10--106
load current exceeds the internal current limit value (typically
4.0 A). An over-current condition activates the current limit
circuit. This circuit then sends an analog signal to the gate
control circuit, lowering the voltage on the output transistor's
gate. Lowering the gate voltage forces the output transistor to
transition from the resistive (fully enhanced) mode of
operation to the current limit (between fully enhanced and
fully OFF) mode.
The actual detection of an over-current condition does not
occur at the initial onset of current limit. The onset of current
limit causes the voltage on the affected output to increase.
The actual Over-Current detection occurs when the output
voltage increases and exceeds the over-current Oetect
Voltage Threshold (VOC(limit), typically 3.7 V), while the
corresponding input signal is in a logic high state.
After detection, the reporting of an over-current Fault at
the Fault Status output is delayed by a time equal to the
over-current Sense lime (Ioe>, see Figures 5 and 6. This
delay time is typically 55 /!S. If the over-current condition no
longer exists after the over-current Sense lime has passed,
then no fault is reported. The purpose of the Fault reporting
delay is to blank any false faults that might be reported due to
high inrush current loads such as incandescent lamps. If the
over-current condition still exists after the delay time has
passed, then a fault will be reported at the Fault Status output
and the affected output is turned OFF.
The Over-Current Sense Time is accomplished internally
with four separate timers that reset and start independent of
each other whenever a corresponding output is turned ON,
either due to the corresponding input turning ON or the
completion of the over-current Refresh Time (tretl explained
in the next paragraph, (see Figures 5 and 6). An over-current
Fault will be reported at the Fault Status output when an
over-current condition is detected and a lapse time in excess
of toc is exceeded after turning ON the affected output.
At the same time the over-current Fault is reported, a
single internal over-current refresh timer resets, causing any
over-current outputs to be turned OFF for a duration of tref,
typically 3.6 ms. After a time tref, the faulted output(s) will be
turned ON again to check if the over-current condition still
exists. If the over-current condition still exists, the output(s)
will be turned OFF again after a time toc. This periodic retry
continues turning ON and OFF over-current loads at a duty
cycle of Ioc /(Ioc + tref) with a period of toc + tref until either the
input is turned OFF or the over-current condition is removed.
Any subsequent over-current conditions will reset and restart
the tref timer.
Oetection of an over-current condition coincides with, but
does not occur until after the onset of current limit. This
allows a specific but small current limit range to go
undetected. The factors that determine the value of load
resistance causing an over-current condition to be detected
are: the output-Load Current Limit [lOS (limit)]; load voltage
(Vload); and the Over-Current Oetect Threshold Voltage
[VOC(limit)] as shown below:
Rload(detect) [Vload - VOC(limit)]
(12)
IOS(limit)
MOTOROLA ANALOG IC DEVICE DATA
MC33293A
The factors that determine the value of load resistance
that will cause the onset of current limit are: IOS(limit), Vload,
and RoS(on), as shown below.
Rload(limit) = [Vload IIOS(limit)l- ROS(on)
(13)
For the case when: Vload =14 V
VOC(limit) =3.7 V
ROS(on) =0.3 n
IOS(limit) 4.0 A
an over-current condition will be detected for any load
resistance such that Rload ::; 2.6 n. An undetected current
limit condition will occur any time 2.6 n ::; Rload ::; 3.2 n. Notice
that the undetected current limit range is quite small.
=
Fault Interrogation
Even though the MC33293A incorporates a single Fault
Status Output pin for reporting three different fault conditions,
a real time interrogation routine can be used to determine
which one of the three Fault conditions is being reported and
which single output is affected.
An important pOint to note about Fault interrogation is that
only one fault on a single output can be interpreted. In other
woRDS, if more than one over-current or open-load Fault
exists among the four outputs, it is not possible to distinguish
which outputs have a fault and which do not. It is very
unlikely, however, that more than one output will be faulted at
the same time.
When a Fault is reported, the first step is to determine if it
is an over-current or open-load Fault (Rload ~ 447 kn,
typical). This is done by taking all the inputs (single or dual) to
a logic low state. If the Fault Status resets (changes to a
logic high state) after the Fault Status Reset Delay Time
(ts(reset), see Figure 4) has lapsed, then an over-current Fault
is being reported. If the Fault Status does not reset (remains
MOTOROLA ANALOG Ie DEVICE DATA
at a logic low state) after ts(reset) has lapsed, then an
open-load Fault (Rload ~ 447 kil, typical) is being reported.
This type of interrogation is possible because an output-off
open-load Fault can only be reported when all the inputs are
in a logic low state.
For an over-current Fault, the next step is to determine
which single output is affected. After all inputs are turned
OFF and the fault status resets, each input is then turned ON
then OFF sequentially. A Fault will again be reported when
the input to the corresponding Over-Current output is turned
ON and Ios(on) has lapsed. If the dual input mode is being
used, an over-current Fault can only be interrogated down to
the two outputs being driven together.
For an open-load Fault (Rload ~ 447 kil, typical)
interrogation, all inputs are turned OFF and the fault status
remains set. Each input is then turned ON and OFF
sequentially. The Fault status will remain set when the input
to the corresponding faulted output is turned ON and tos(on)
has lapsed. Ifthe dual input mode is used, an open-load Fault
can only be interrogated down to the two outputs driven
together.
From the example following Equation 1, the typical value
of Ropen(on) is 187 n. From the example following Equation
6, the typical value of Ropen(off) is 447 kn. Therefore, if the
load resistance is between 187 nand 447 kil typically, an
output-on open-load Fault will be reported at the Fault Status
output but an output-off open-load Fault will not. This
condition is referred to as a soft open fault. If a soft open fault
exists, it is reported at the Fault Status output the same as an
over-current Fault except for the reporting delay time. A soft
open fault has a reporting delay time of 2.2 ms typically, and
an over-current Fault has a reporting delay time of only 55 Jis
typically, after the input to the faulted output is turned ON.
10-107
MC33293A
Figure 14. Truth Table
Inputs
Conditions of Outputs
Non-Faulted Operation
2
3
4
SID
1&2
3&4
1
·2
3
4
Fault
l
l
l
l
l
H
H
l
l
H
H
l
l
H
H
l
l
H
H
X
X
X
X
l
H
l
H
l
H
l
H
l
H
l
H
l
H
l
H
X
X
X
X
l
l
l
l
l
l
l
l
l
.l
l
l
l
l
l
l
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
l
H
l
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
l
l
H
H
H
H
H
H
H
H
H
H
l
l
l
l
l
l
l
l
H
l
H
l
H
H
H
·H
l
l
l
l
H
H
H
H
H
H
H
H
X
X
X
X
l
l
l
l
H
H
H
H
l
l
l
l
H
H
H
H
X
X
X
X
l
l
l
l
H
l
H
l
H·
H
l
l
H
H
l
l
H
H
l
l
H
H
l
l
H
H
l
l
H
l
H
l
H
l
H
l
H
l
H
l
H
l
H
l
H
H
l
l
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
l
H
l
H
X
X
X
X
l
l
H
H
X
X
X
X
l
l
H
H
X
X
X
X
l
l
H
H
X
X
X
X
l
l
l
l
H
H
H
H
X
X
X
X
H
l
H
X
X
X
X
l
l
H
H
l
l
l
l
l
l
l
l
H
H
l
l
H
l
H
l
H
H
l
l
H
H
l
l
H
H
l
l
H
H
l
l
l
l
H"
l
l
l
H"
l
l
H
l
H
X
X
X
X
l
l
H
H
X
X
X
X
l
l
H
H
X
X
X
X
l
l
H
H
X
X
X
X
l
l
l
l
H
H
H
H
X
X
X
X
l
H
l
H
X
X
X
X
l
l
H
H
H
H
H
H
H
H
H
H
H
H
l
l
H
l
H
l
H
H
l
l
H
H
l
l
H
H
l
l
H
H
l
l
H
l
H
l
H
l
H
l
L
open-load Fault On Output 1
Over-Current Fault On Output 1
Outputs
1
L
l
l
l
l
H
H
H
H
"NOTE: All inputs must be a logic low state for an Output-Off open-load Fault to be reported.
10-108
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC33298
Octal Serial Switch with
Serial Peripheral Interface I/O
The MC33298 is an eight output low side power switch with 8 bit serial input
control. The MC33298 is a versatile circuit designed for automotive
applications, but is well suited for other environments. The MC33298
incorporates SMARTMOSTM technology, with CMOS logic, bipolarlMOS
analog circuitry, and DMOS power MOSFETs. The MC33298 interfaces
directly with a microcontroller to control various inductive or incandescent
loads. The circuit's innovative monitoring and protection features are: very low
standby current, cascadable fault reporting, internal 65 V clamp on each
output, output specific diagnostics, and independent shutdown of outputs. The
MC33298 is parametrically specified over a temperature range of - 40°C ~ TA
~ +125°C ambient temperature and 9.0 V ~ VPWR ~ 16 V supply. The
economical 20 pin DIP and S0-24 wide body surface mount plastic packages
make the MC33298 very cost effective.
• Designed to Operate Over Wide Supply Voltages of 5.5 V to 26.5 V
• Interfaces Directly to Microprocessor Using SPI Protocol
OCTAL SERIAL SWITCH
(SPI Input/Output)
SEMICONDUCTOR
TECHNICAL DATA
1
• SPI Communication for Control and Fault Reporting
• 8-Bit Serial 1/0 is CMOS Compatible
• 3.0 A Peak Current Outputs with Maximum RDS(on) of 0.45
n at 25°C
PSUFFIX
PLASTIC PACKAGE
CASE 738
DIP (16+2+2)
• Outputs are Current Limited to 3.0 A to 6.0 A for Driving Incandescent
Lamp Loads
• Output Voltages Clamped to 65 V During Inductive Switching
24
#
DWSUFFIX
PLASTIC PACKAGE
CASE 751E
SOP (16+4+4)L
• Maximum Sleep Current (IPWR) of 50 f,IA with VDD ~ 2.0 V
PIN CONNECTIONS
• Maximum of 4.0 mA IDD During Operation
• Maximum of 2.0 mA IPWR During Operation with All Outputs "On"
DIP
• Open Load Detection (Outputs "Off')
• Overvoltage Detection and Shutdown
• Each Output has Independent Over Temperature Detection and Shutdown
• Output Mode Programmable for Sustained Current Limit or Shutdown
• Short Circuit Detect and Shutdown with Automatic Retry for Every
Write Cycle
• Serial Operation Guaranteed to 2.0 MHz
Simplified Application
SFPD
L.
CSB
Micrcr
controller
with Bus
SClK
SI
VDD
+Vbat
VPWR
-:1
CMOS
Input
logic
Updrain
DMOS
Output
Switches
and
Sense
Circuits
CMOS
SerialShiit
Registers
and
latches
Reset
Yo
Yl
Y2
Y3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
This device contains
1.200 active transistors. =
Device
MC33298P
Gnd
MOTOROLA ANALOG IC DEVICE DATA
SOP-24L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ORDERING INFORMATION
SO 01--1---'
IL ____ _
Function
Output 7
Output 6
SCLK
SI
Ground
Ground
Ground
Ground
SO
CSB
Output 5
Output 4
Output 3
Output 2
SFPD
VDD
Ground
Ground
Ground
Ground
VPWR
Reset
Output 1
Output 0
MC33298DW
Tested Operating
Temperature Range
TC = - 40° to +125°C
Package
DIP
SOP-24L
10-109
II
MC33298
Figure 1. Simplified Block Diagram
VPWR
r----------~-----
------~-----~-------I
I
Bias
65V
VOOo+----..,
SFPD 0+....,..,.--+---,
Gate
Control
1..0
1+---+ I
to
Gates
l ___J-t---- To1-7
Fau~
TImers
CSB
SPI
Interface
Logic
k
I
1-0
I
ro
Open
Output 0
Outputs
1-7
1..0
I
to
I
I
Load
Detect
SCLK 0+-....,..,.---...,----'
Short
Circuit
Detect
Slo+-t:--------'
Serial 0/0
Over
Temperature
Detect
SOot-----1 UneDriver
~I
I
I
IL _____________ _______________________
From Detectors 1 to 7
I
~
~
FAULT OPERATION
SERIAL OUTPUT (SO) PIN REPORTS
Overvoltage
Overvoltage condition reported.
Over Temperature
Fault reported by Serial Output (SO) pin.
Over Current
SO pin reports short to battery/supply or over current condition.
Output "On," Open Load Fault
Not reported.
Output "Off," Open Load Fault
SO pin reports output "off' open load condition.
DEVICE SHUTDOWNS
Overvoltage
Total device shutdown at VpWR = 28-36 V. Re-operates when overvoltage is removed with
all outputs assuming an off state upon recovery from overvoltage. All device registers are
automatically reset (cleared) during shutdown.
Over Temperature
Only the output experiencing an over temperature shuts down.
Over Current
Only the output experiencing an over current condition shuts down at 3.0 A to 6.0 A after a
251JS to 100 I1S delay, with SFPD pin grounded. All outputs will continue to operate in a current
limit mode, with no shutdown, if the SPFD pin is at 5.0 V.
10-110
MOTOROLA ANALOG IC DEVICE DATA
MC33298
MAXIMUM RATINGS (All voltages are with respect to ground, unless otherwise noted.)
Rating
Symbol
Value
Unit
Power Supply Voltage
Steady-State
Transient Conditions (Notel)
VPWR(sus)
VpWR(pk)
-1.5 to 26.5
-13 to 60
V
V
Logic Supply Voltage (Note 2)
VDD
- 0.3 to 7.0
V
VIN
-0.3t07.0
V
Input Pin Voltage (Note 3)
Output Clamp Voltage (Note 4)
50 to 75
(2.0 mA S; lout S; 0.5 A)
Output Self-Limit Current
Continuous Per Output Current (Note 5)
ESDVoitage
Human Body Model (Note 6)
Machine Model (Note 7)
Output Clamp Energy (Note 8)
Repetitive:
TJ = 25°C
TJ = 125'C
Non-Repetitive:
10UT(lim)
3.0 to 6.0
A
10UT(cont)
1.0
A
VESDl
VESD2
2000
200
V
V
Eclamp
TJ = 25°C
TJ= 125°C
Recommended Frequency of SPI Operation (Note 9)
V
VOUT(off)
100
mJ
30
mJ
2.0
0.5
J
J
fSPI
2.0
MHz
Storage Temperature
Tstg
-55to+15O
Operating Case Temperature
TC
-40to+125
Operating Junction Temperature
TJ
-40to+150
'c
'c
'c
Power Dissipation (TA = 25'C) (Note 10)
Po
3.0
W
Soldering Temperature (for 10 seconds)
Tsolder
260
'c
Thermal Resistance, Junction--to--Ambient (Note 11)
Plastic Package, Case 738:
All Outputs "On" (Note 12)
Single Output "On" (Note 13)
SOP-24 Package, Case 751 E:
All Outputs "On" (Note 12)
Single Output (Note 13)
NOTES:
'C/W
RaJA
31
37
34
40
1. Transient capability with extemall 00 Il resistor connected in series with VPWR pin and supply.
2. Exceeding these IimRs may cause a maKunction or pennanent damage to the device.
3. Exceeding voltage limRs on SCLI<. SI, CSB, SFPD, or Reset pins may cause pennanent damage to
the device.
4. WRh output ·off."
5. Continuous output rating so long as maximum junction temperature is not exceeded. (See Figure 21 and
22 for more details).
6. ESDl testing is perfonned in accordance wRh the Human Body Model (CZap = 100 pF, RZap = 1500 Il).
7. ESD2 testing is perfonned in accordance wRh the Machine Model (CZap = 100 pF, RZap = 0 Il).
B. Maximum output clamp energy capability at indicated Junction Temperature using single pulse method.
See Figure 19 for more details.
9. Guaranteed and production tested for 2.0 MHz SPI operation but has been demonstrated to operate to
8.5 MHz @ 25"C.
10. Maximum power dissipation at indicated junction temperature with no heat sink used. See Figures 20,
21, and 22 for more details.
11. See Figure 20 for Thermal Model.
12. Thennal resistance from Junction-to-Ambient wRh all outputs 'on" and dissipating equal power.
13. Thennal resistance from Junction-to-Ambient with a single output ·on."
MOTOROLA ANALOG IC DEVICE DATA
10-111
MC33298
STATIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V :s; Voo :s; 5.5 V, 9.0 V :S;VPWR :s; t 6 V,
- 40°C :s; TC :s; 125°C, unless otherwise noted.)
Characteristic
Symbol
Min
lYP
Max
Supply Voltage Range
Quasi-Functional (Note 1)
Full Operational
VPWR(qf)
VPWR(fO)
5.5
9.0
-
9.0
26.5
Supply Current (all Outputs "On," lout = 0.5 A) (Note 2)
IPWR(on)
-
1.0
2.0
Un"
POWER INPUT
V
Sleep State Supply Current (Voo = 0.5 V)
IPWR(ss)
Sleep State Output Leakage Current (per Output, Voo = 0.5 V)
10UT(ss)
mA
1.0
50
ItA
-
50
I1A
VOV
28
-
36
V
VOV(hys)
0.2
1.5
V
Logic Supply Voltage
Voo
4.5
5.5
V
Logic Supply Current (with any combination of Outputs "On")
100
-
-
4.0
mA
Voo(uvlo)
2.0
-
4.5
V
-
-
-
-
0.4
0.35
1.0
0.5
0.45
-
-
Overvoltage Shutdown
Overvoltage Shutdown Hysteresis
Logic Supply Undervoltage Lockout Threshold (Note 3)
POWER OUTPUT
orain-to--Source "On" Resistance (lout = 0.5 A, TJ = 25°C)
VPWR=5.5V
VpWR=9.0V
VpWR=13V
RoS(on)
orain-to--Source "On" Resistance (lout = 0.5 A, TJ = 150°C)
VpWR=5.5V
VPWR=9.0V
VPWR= 13V
RoS(on)
Output SeH-Limiting Current
Outputs Programmed "On", Vout = 0.6 Voo
10UT(lim)
Output Fault Detect Threshold (Note 4)
Output Programmed "Off'
lOCO
Output Clamp Voltage
2.0 mA:S; lout :s; 200 mA
VOK
Over Temperature Shutdown (Outputs "Off') (Note 7)
Over Temperature Shutdown Hysteresis (Note 7)
Q
-
.0.75
0.65
1.8
0.9
0.8
3.0
4.0
6.0
0.6
0.7
0.8
30
50
100
50
60
75
-50
0
50
ItA
A
Voo
VOUTth(F)
Output "orr Open Load Detect Current (Note 5)
Output Programmed "Off," Vout = 0.6 Voo
Output Leakage Current (Voo :s; 2.0 V) (Note 6)
Q
10UT(lkg)
ItA
V
TLiM
155
170
185
°C
TLlM(hys)
-
10
20
°C
NOTES: 1. SPI inputs and outputs operational; Fault reporting may not be fully operational within this voltage rangs.
2. Value reflects nonnal operation (no faults) with all outputs "on." Each 'on" output contributes approximately 20 IlA to IpwR. Each output experiencing
a 'soft short" condition contributes approximately 0.5 mA to IpWR. A 'soft short" Is defined as any load current causing the output source current to
seH-limit. A "hard" output short is a very low impedance short to supply.
3. For VDD less than the Undervoltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled.
4. Output fault detect threshold with outputs programmed "off." Output fault detect thresholds are the same for output opens and shorts.
5. Output "011" Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open condition
when the specific output is commanded to be ·off."
6. Output leakage current measured with output "off" and at 16 V.
7. This parameter is guaranteed by design but is not production tested.
10-112
MOTOROLA ANALOG IC DEVICE DATA
MC33298
STATIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V 5 VOO 5 5.5 V, 9.0 V 5 VPWR 5 16 V,
-40°C STC 5 125°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
VIH
0.7
Vil
0.0
VI(hys)
50
Max
Unit
-
1.0
VOO
-
0.2
VOO
100
500
mV
DIGITAL INTERFACE
Input logic High Voltage (Note 1)
Input logic low Voltage (Note 2)
Input logic Voltage Hysteresis (Note 3)
liN
-10
0
10
Reset Pull-Up Current (Reset = 0.7 VOO)
IRSTB
10
22
50
SFPO Pull-Down Current (SFPO = 0.2 VOO)
ISFPO
10
22
50
ItA
ItA
ItA
SO High State Output Voltage (lOH = 1.0 rnA)
VSOH
VOO-1.0V
VOO-0.6V
-
V
SO low State Output Voltage (IOl = -1.6 rnA)
VSOl
-
0.2
0.4
V
ISOT
-10
0
10
ItA
CIN
-
-
12
pF
CSOT
-
-
20
pF
Input logic Current (Note 4)
SO Tn-8tate leakage Current (CSB = 0.7 VOO, 0 V 5 VSO 5 VOO)
Input Capacitance (0 V 5 VOO 5 5.5 V) (Note 5)
SO Tn-State Capacitance (0 V 5 VOO 5 5.5 V) (Note 6)
NOTES: 1. Upper logic threshold voltage range applies to SI. CSB. SCLK. Reset, and SFPD input signals.
2. Lower logic threshold vonage range applies to SI, CSB, SCLK, Reset, and SFPD input signals.
3. Only the SFPD and Reset inputs have hysteresis. This parameter is guaranteed by design but is not production tested.
4. Input current of SCLK, SI, and CSB logic control inputs.
5. Input capacitance of SI, CSB, SCLK, Reset, and SFPD for 0 V,; VDD'; 5.5 V. This parameter is guaranteed by design, but is not production tested.
6. Tri-state capacitance of SO for 0 V ,;; VDD ,;; 5.5 V. This parameter is guaranteed by design but is not production tested.
Figure 2. Input Timing Switch Characteristics
~
O.2VDD
/
-----------------------------------------------------------VIH
~ ____________________________________
Vil
~
I twRSTB I
------------.
O.2V~DD--
CSB
VIH
rl
tlead l
O.7VDD
~_
I
SCLK
r------- VIl
-----------------------/
I~WSClK~1
I
I
I
~
-}---------I
VIH
" - - - - - - - - - - Vil
.,---------- VIH
SI
Don't Care
Don't Care
' - - - - - - - - - - Vil
MOTOROLA ANALOG IC DEVICE DATA
10-113
MC33298
DYNAMIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V ", VDD ", 5.5 V,
9.0 V", VpWR'" 16 V, -40°C ",TC'" 125°C, unless otherwise noted.)
Characteristic
Typ
Max
Unit
0.4
1.5
20
liS
tf
0.4
2.5
20
!1S
Idly(on)
1.0
5.0
15
!1S
Idly(off)
1.0
5.0
15
!1S
25
50
100
25
50
Hio
Symbol
Min
tr
POWER OUTPUT TIMING
=13 V, RL =26 0) (Note 1)
Output Fall Time (VpWR =13 V, RL =26 0) (Note 1)
Output Tum 'On" Delay Time (VPWR =13 V, RL =26 0) (Note 2)
Output Tum "Off" Delay Time (VPWR = 13 V, RL =26 0) (Note 3)
Output Rise Time (VPWR
Output Short Fault Disable Report Delay (Note 4}
SFPD 0.2 x VDD
tdly(sf)
Output "Off" Fault Report Delay (Note 5)
SFPD 0.2 x VDD
tdly(off)
=
=
!1S
!1S
NOTES: 1. Output Rise and Fall time respectively measured across a 26 Q resistive load at 10% to 90% and 90% to 10% voHage points.
2. Output Tum "On" Delay time measured from rising edge of CSB to 50% of output "off' Vout voHage wHh Rl = 26 Q resistive load
(see Figure 7 and 9).
3. Output Tum "Off' Delay time measured from rising edge (If CSB to 50% of output "off' Vout voltage wHh Rl ,. 26 Q resistive load
(see Figure 7 and 9).
4. Output Short FauH Disable Report Delay measured from rising edge of CSB to lout = 2.0 A point wHh output "on; Vout = 5.0 V,
and SFPD = 0.2 x VDD (see Figure 8 and 10).
5. Output "Off' Fault Report Delay measured from 50% pOints of rising edge of CSB to rising edge of output (see Figure 9).
DYNAMIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.5 V ", VDD ", 5.5 V,
9.0 V", VpWR'" 16 V, - 40°C", TC'" 125°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING
tpSCLK
500
-
-
ns
SCLK Clock High Time
twSCLKH
175
-
-
ns
SCLK Clock Low Time
twSCLKL
175
-
-
ns
Required Low State Duration for Reset (VIL ", 0.2 VDD) (Note 1)
twRSTB
250
50
-
ns
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)
tlead
250
50
-
ns
Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)
tlag
250
50
-
ns
tSISU
125
25
-
ns
tSI(hold)
125
25
-
ns
trSO
-
25
75
ns
SCLK Clock Period (Note 6)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Hold Time)
=200 pF)
SO Fall Time (CL =200 pF)
SO Rise Time (CL
tfSO
-
25
75
ns
SI, CSB, SCLK Incoming Signal Rise Time (Note 2)
trSI
-
200
ns
SI, CSB, SCLK Incoming Signal Fall Time (Note 2)
tfSI
-
-
200
ns
tSO(en)
tSOldi!!}
-
-
200
200
-
50
125
Time from Falling Edge of CSB to SO
Low Impedance (Note 3)
High Impedance (Note 4)
Time from Rising Edge of SCLK to SO Data Valid (Note 5)
0.2 VDD ", SO '" 0.8 VDD, CL
=200 pF
ns
tvaiid
ns
NOTES: 1. Reset low duration measured with outputs enabled and going to "off' or disabled condition.
2. Rise and Fall time of incoming SI, CSB, and SCU< signals suggested for design consideration to prevent the occurrence of double pulsing.
3. lime required for output status data to be available for use at SO.
4. lime required for output status data to be terminated at SO.
5. lime required to obtain valid data out from SO following the rise of SClK.
6. Clock period includes 75 ns rise plus 75 ns fall transition time in addition to clock high and low time.
10-114
MOTOROLA ANALOG IC DEVICE DATA
MC33298
Figure 3. Valid Data Delay Time and
Valid Time Test Circuit
Figure 4. Enable and Disable Time Test Circuit
Voo = 5.0 V
MC33298
Under
Test
SCLK
1 - - - . - 0 SO
I
tlSl1
~ ,;;10ns
t-l
~l-~-=-.-:~ - - - - - ~
';;10ns
:r----
CSB
5.0V
0.2 Voo
..;;S..:.;CL..:.;K'--_ _ _ _
SO
(High-ta-Low) .
0.7 Voo
T-
I
I
I
Idly(hl)
I--t
-0. 2Voo
1'-----=--- VOL
SO (Iow-ta-high) is for an output with internal conditions such that
the 10w-to-l1igh transition of CSB causes the SO output to switch
from high-ta-Iow.
MOTOROLA ANALOG IC DEVICE DATA
VOH
I
I
I
:4tso(en~ I
trS~ 1
.:S.:::.O_ _ _ _~~_+_--.,.I"'I<-tfS--io~I_ _ _ _ _ _ _ _ VOH
(High-tHaw)
5.0V
0
I
I
Idly(lh) j----+!
1/------- VOH
I
I
SO
0.2voo.j..._1
-=--------+--;.-.-;-- - - - - - - VOL
1
RL = 2.0 k.Q
I----+--{) SO
Figure 6. Enable and Disable Time Waveforms
0.7VOO(2.5V)
(Low-to-High)
MC33298
CL represents the total capacitance of the test fixture and probe.
Figure 5. Vaild Data Delay Time and
Valid Time Waveforms
I
I
r--'
VPull-Up = 2.5 V
Under
Test
CSB
CL represents the total capacitance of the test fixture and probe.
trSI
VOO=5.0V
I
I
----
: ~O(di~1
L--
;Y-- 50%--~
..;;SO~_ _ _ _ _ _J.
VOL
VOH
~VOL
(Low-ta-High)
NOTES: 1. SO (high-ta-Iow) waveform is for SO output w~h internal
cond~ions such that SO output is low except when an output is
disabled as a resuR of detecting a circuit fauR with CSB in a
High Logic state (e.g., open load).
2. SO (Iow-ta-high) waveform is for SO output w~h internal
cond~ions such that SO output is high except when an output
is disabled as a result of detecting a circuit fauR with CSB in
a High Logic state (e.g., shorted load).
10-115
MC33298·
Figure 7. Switching Time.Test Circuit
Voo=li.OV
Figure 8. Output Fault Unlatch Disable
Delay TestCircuit
VOO=5.0V
VpWR=14V
RL=26Q
CSB
MC33298
1---"-.0 Output
CSB
Under
VpWR=ll V
IL=2.0A
(Output 'On")
I---+-.o
Output
Test
CL represents the total capacitance of the test fixture and probe.
CL represents the total capacitance of the test fixture and probe.
Figure 9. Turn-On/Off Waveforms
~
I
CSB
10%
Figure 10. Output Fault Unlatch Disable
Delay Waveforms
~ ,,10ns
-.J ___ _
,,10ns
11_ - - -.....+-1
I
90%
50%
90%
50%
I
~
5.0 V
10%
-------"'- ~ - - - - - - - + -"----- 0
tdIY(O~1
I
...".--,..,...,...--_--L.~- 1- _________
Output Voltage
Waveform 2
I
I
I 50%
~
I Idly(on) I
_
14V
' - - - - - - - - - VOL
NOTES: 1. tdly(on) and tdly(off) are turn-<>n and tum- 3.0 V), the output being
controlled will be high and turned "off."
Figure 12. MC33298 SPI System Daisy Chain
SCLK
T
Ir
CSB
SCLK
Parallel Port
MC68XX
Microcontroller
SPI
g
MISO
MOSI
so
SI~
MC33298
Y
8 Outputs
MOTOROLA ANALOG IC DEVICE DATA
I,
I
CSB
SCLK
so
SI ~
MC33298
J,
8 Outputs
1
-,
T
CSB
SCLK
so
SII--MC33298
Y
8 Outputs
I
l
CSB
SCLK
so
SI
MC33298
-
J,
8 Outputs
10-117
MC33298
One main advantage of the MC33298 is the serial port
which when coupled to an MCU, receives "on"/"off"
commands from the MCU and in return transmits the drain
status of the device's output switches. Many devices can be
"daisy--chained" together to form a larger system (see
Figure 12). Note in this example that only one dedicated
MCU parallel port (aside from the required SPI) is needed for
chip select to control 32 possible loads.
Multiple MC33298 devices can also be controlled in a
parallel input fashion using SPI (see Figure 13). This figure
shows a possible 24 loads being controlled by only three
dedicated parallel MCU ports used for chip select.
Figure 13. Parallel Input SPI Control
MC33298
MOSI
SI
SCLK
SCLK
~ 8 Outputs
SGLK
' - - - A D t----I Parallel A1
I
Ports
~ 8 Outputs
GSB
.~ t-----
The only drawbacks to SPI are that an MCU is required for
efficient operational control and, in contrast to parallel input
control, is slower at performing pulse width modulating
(PWM) functions.
Figure 14. Multiple MCU SPI Control
MC33298
~
SI
SCLK
MC68XX
Microcontroller
SPI
(Master)
f---'- 8 Outputs
CSB
Figure 14 shows a basic method of controlling multiple
MC33298 devices using two MCUs. A system can have only
one master MCU at any given instant of time and one or more
slave MCUs. The master MCU supplies the system clock
signal (top MCU designated the master); the lower MCU
being the slave. It is possible to have a system with more
than one master but not at the same time. Only when the
master is not communicating can a slave communicate. MCU
master control is switched through the use of the slave select
(SS) pin of the MCUs. A master will become a slave when it
detects a logic low state on its SS pin.
These basic examples make the MC33298 very attractive
for applications where a large number of loads need be
controlled efficiently. The popular Synchronous Serial
Peripheral Interface (SPI) protocol is incorporated, to this
end, to communicate efficiently with the MCU.
10-118
• Each Microcontroller can be a Master or a Slave
• Provides Write Collision Flag Protection
• Four II0s associated with SPI (MOSI, MISO, SCLK, SS)
MC33298
~ SI
L
The SPI system is flexible enough to communicate directly
with numerous standard peripherals and MCUs available
from Motorola and other semiconductor manufacturers.· SPI
reduces the number of pins necessary for input/output (1/0)
on the MC33298. It also offers an easy means of expanding
the I/O function using few MCU pins. The SPI system of
communication consists of the MCU transmitting, and in
return, receiving one databit of information per clock cycle.
Databits of information are simultaneously transmitted by
one pin, Microcontroller Out Serial In (MOSI), and received
by another pin, Microcontroller In Serial Out (MISO), of
the MCU.
Some features of SPI are:
• Full Duplex, Three-Wire Synchronous Data Transfer
• Provides End of Message Interrupt Flag
CSB
MC68XX
Microcontloller
SPI
SPI System Attributes
,.--- ~o- - - -iii f + - - - - + I CS:C33298
; - - Bl Parallel Al
I- _
~~ _A~
B-Bit
VDD
.:r-
rITJIIlll
~
~
f-'-. 8 Outputs
,-----.. SGLK B-Bit
~ ~~~
SCLK
MISO
MOSI H-H-1~
L SS
MC33298
+++++-":CSB
MC68XX
Microcontroller
SPI
(Alternate
Master)
SCLK -8.
I-"'- 8 Outputs
8 It
r----- SO OIIIIIIJ+,
f.--I
_
' - - SI
I
L-"BO---AO
L---
Bl Parallel A1 fMC33298
Ports A2 f-.......+l-+--+I CSB
r-----'=B-Bit SCLK f--e.++--+I SCLK B-Bit
VDD rITJIIlll MISO
T L-MOSI
L SS
f--'-. 8 Outputs
SO ~
SI'------'
MOTOROLA ANALOG IC DEVICE DATA
MC33298
PIN FUNCTION DESCRIPTION
CSB Pin
The system MCU selects the MC33298 to be
communicated with through the use of the CSB pin.
Whenever the pin is in a logic low state, data can be
transferred from the MCU to the MC33298 and vise versa.
Clocked-in data from the MCU is transferred from the
MC33298 shift register and latched into the power outputs on
the rising edge of the CSB signal. On the falling edge of the
CSB signal, drain status information is transferred from the
power outputs and loaded into the device's shift register. The
CSB pin also controls the output driver of the serial output
pin. Whenever the CSB pin goes to a logic low state, the SO
pin output driver is enabled allowing information to be
transferred from the MC33298 to the MCU. To avoid any
spurious data, it is essential that the high-to-Iow transition of
the CSB signal occur only when SCLK is in a logic low state.
SCLKPin
The system clock pin (SCLK) clocks the internal shift
registers of the MC33298. The serial input pin (SI) accepts
data into the input shift register on the falling edge of the
SCLK signal while the serial output pin (SO) shifts data
information out of the shift register on the riSing edge of the
SCLK signal. False clocking of the shift register must be
avoided to guarantee validity of data. It is essential that the
SCLK pin be in a logic low state whenever chip select bar pin
(CSB) makes any transition. For this reason, it is
recommended though not necessary, that the SCLK pin be
kept in a low logic state as long as the device is not accessed
(CSB in logic high state). When CSB is in a logic high state,
any signal at the SCLK and SI pin is ignored and SO is
tristated (high impedance). See the Data Transfer Timing
diagram of Figure 16.
SI Pin
This pin is for the input of serial instruction data. SI
information is read in on the falling edge of SCLK. A logic high
state present on this pin when the SCLK signal rises will
program a specific output "off," and in turn, turns "off" the
specific output on the rising edge of the CSB signal.
Conversely, a logic low state present on the SI pin will
program the output "on," and in turn, turns "on" the specific
output on the rising edge of the CSB signal. To program the
eight outputs of the MC33298 "on" or "off," an eight bit serial
stream of data is required to be entered into the SI pin
starting with Output 7, followed by Output 6, Output 5, etc., to
Output O. For each rise of the SCLK signal, with CSB held in
a logic low state, a databit instruction ("on" or "off') is loaded
into the shift register per the databit SI state. The shift register
is full after eight bits of information have been entered. To
preserve data integrity, care should be taken to not transition
SI as SCLK transitions from a low to high logic state.
SO Pin
The serial output (SO) pin is the tri-stateable output from
the shift register. The SO pin remains in a high impedance
state until the CSB pin goes to a logic low state. The SO data
reports the drain status, either high or low. The SO pin
changes state on the rising edge of SCLK and reads out on
the falling edge of SCLK. When an output is "off' and not
faulted, the corresponding SO databit is a high state. When
an output is "on," and there is no fault, the corresponding
databit on the SO pin will be a low logic state. The SI/SO
shifting of data follows a first-in-first-out protocol with both
MOTOROLA ANALOG IC DEVICE DATA
input and output words transferring the Most Significant Bit
(MSB) first. The SO pin is not affected by the status of the
Reset pin.
Reset Pin
The MC33298 Reset pin is active low and used to clear the
SPI shift register and in doing so sets all output switches "off."
With the device in a system with an MCU; upon initial system
power up, the MCU holds the Reset pin of the device in a
logic low state ensuring all outputs to be "off' until both the
VDD and VPWR pin voltages are adequate for predictable
operation. After the MC33298 is reset, the MCU is ready to
assert system control with all output switches initially "off." If
the VPWR pin of the MC33298 experiences a low voltage,
following normal operation, the MCU should pull the Reset
pin low so as to shutdown the outputs and clear the input data
register. The Reset pin is active low and has an internal
pull-up incorporated to ensure operational predictability
should the external pull-up of the MCU open circuit. The
internal pull-up is only 20 IlA to afford safe and easy
interfacing to the MCU. The Reset pin of the MC33298
should be pulled to a logic low state for a duration of at least
250 ns to ensure reliable reset.
A simple power "on" reset delay of the system can be
programmed through the use of an RC network comprised of
a shunt capacitor from the Reset pin to Ground and a resistor
to VDD (See Figure 15). Care should be exercised to ensure
proper discharge of the capaCitor so as to not adversely
delay the reset nor damage the MCU should the MCU pull the
Reset line low and yet accomplish initialization for turn "on"
delay. It may be easier to incorporate delay into the software
program and use a parallel port pin of the MCU to control the
MC33298 Reset pin.
Figure 15. Power "On" Reset
r------,
VOO
r---,
ROLY
I MCU I Reset
I
I
L __ -1
I
I
I
I
I
+
2Ol1A
Reset
.T
-=
COLY
I
I
I
I
I
I
I
I
I
I
I
I
L _ .!c::a~8_..J
SFPD Pin
The Short Fault Protect Disable (SFPD) pin is used to
disable the over current latch-Qff. This feature allows control
of incandescent loads where in-rush currents exceed the
device's analog current limits. Essentially the SFPD pin
determines whether the MC33298 output(s) will instantly shut
down upon sensing an output short or remain "on" in a
current limiting mode of operation until the output short is
removed or thermal shutdown is reached. If the SFPD pin is
tied to VDD 5.0 V the MC33298 output(s) will remain "on" in
a current limited mode of operation upon encountering a load
short to supply. If the SFPD pin is grounded, a short circuit
will immediately shut down only the output affected. Other
outputs not having a fault condition will operate normally. The
short circuit operation is addressed in more detail later.
=
10-119
1m
it
...
~
Figure 16. Data Transfer Timing
~
CSB '
SCLK'
SI
s:
Oulpul7
C')
Old Data
New Data 007 '
(0)
(0)
I\)
CD
OulpulO.
Q)
Old Data
I
5:
0
a:u
New Data 000 ,
NOTES: 1. Reset pin is in a logic high state during the above operation.
2.
3.
4.
5.
00,01, 02, ... , and 015 relate to the ordered entry of program data into the MC33298 wijh 00108 bits (MSB) corresponding to Output 7 and 07/015 corresponding to Output O.
00", 01", 02", ... , and 07" relate to the ordered data out of the MC33298 with 00" bit (MSB) corresponding to Output 7.
00" corresponds to Old Oatabits.
For brevity, only 007 and 000 are shown which respectively correspond to Output 7 and Output O.
0
~
)0
z
)0
....
0
Data Transfer Timing (General)
G)
0
c
m
:S
0
m
c
~
)Ii
GSB High-ta-Low
SO pin is enabled. Output Status information transferred to Output Shift Register.
GSB Low-ta-High
Data from the Shift Register is transferred to the Output Power Switches.
SO
Will change state on the rising edge of the SGLK pin signal.
SI
Will accept data on the falling edge of the SGLK pin signal.
MC33298
Power Consumption
The MC33298P has extremely low power consumption in
both the operating and standby modes. In the standby or
"sleep' mode, with VDD ~ 2.0 V, the current consumed by the
VpWR pin is less than 50 I1A. In the operating mode, the
current drawn by the VDD pin is less than 4.0 mA (1.0 mA
typical) while the current drawn at the VPWR pin is 2.0 mA
maximum (1.0 mA typical). During normal operation, turning
outputs "on" increases IPWR by only 20 I1A per output. Each
output experiencing a "soft short" (overcurrent conditions just
under the current limit), adds 0.5 mA to the IpWR current.
Paralleling of Outputs
Using MOSFETs as output switches allows the connection
of any combination of outputs together. MOSFETs have an
inherent positive temperature coefficient thermal feedback
which modulates RDS(on) providing balanced current sharing
between outputs without destructive operation (bipolar
outputs could not be paralleled in this fashion as thermal
run-away would likely occur). The device can even be
operated with all outputs tied together. This mode of
operation may be desirable in the event the application
requires lower power dissipation or the added capability of
switching higher currents. Performance of parallel operation
results in a corresponding decrease in RDS(on) while the
Output Off Open Load Detect Currents and the Output
Current Limits increase correspondingly (by a factor of eight
if all outputs are paralleled). Less than 56 mn RDS(on) with
current limiting of 24 to 48 A will result if all outputs are
paralleled together. There will be no change in the
Overvoltage detect or the "Off' Output Threshold Voltage
Range. The advantage of paralleling outputs within the same
MC33298 affords the existence of minimal RDS(on) and
output clamp voltage variation between outputs. Typically,
the variation of RDS(on) between outputs of the same device
is less than is 0.5%. The variation in clamp voltages (which
could affect dynamic current sharing) is less than 5%.
Paralleling outputs from two or more devices is possible but
not recommended. This is because there is no guarantee
that the RDS(on) and clamp voltage of the two devices will
match. System level thermal design analysis and verification
should be conducted whenever paralleling outputs.
FAULT LOGIC OPERATION
General
The MCU can perform a parity check of the fault logic
operation by comparing the command 8-bit word to the
status 8-bit word. Assume that after system reset, the MCU
first sends an 8-bit command word, Command Word 1, to the
MC33298. Each output that is to be turned "on" will have its
corresponding databit low. Refer to the Data Transfer Timing
diagram of Figure 16. As this word, Command Word 1, is
being written into the shift register of the MC33298, a status
word is being simultaneously written out and received by the
MCU. However, the word being received by the MCU is the
status of the previous write word to the MC33298, Status
Word O. If the command word of the MCU is written a second
time (Command Word 2 = Command Word 1), the word
received by the MCU, Status Word 2, is the status of
Command Word 1. The timing diagram shown in Figure 16
depicts this operation. Status Word 2 is then compared with
Command Word 1. The MCU will Exclusive OR Status Word
2 with Command Word 1 to determine if the two words are
identical. If the two words are identical, no faults exist. The
timing between the two write words must be greater than
100 I1s to receive proper drain status. The system databus
integrity may be tested by writing two like words to the
MC33298 within a few microseconds of each other.
Initial System Setup Timing
The MCU can monitor two kinds of faults:
(1) Communication errors on the data bus and
(2) Actual faults of the output loads.
After initial system start up or reset, the MCU will write one
word to the MC33298. If the word is repeated within a few
microseconds (say 5) of the first word, the word received by
the MCU, at the end of the repeated word, serves as a
confirmation of data bus integrity (1). At startup, the
MC33298 will take 25 to 100 I1s before a repeat of the first
word can give the actual status of the outputs. Therefore, the
first word should be repeated at least 100 I1s later to verify the
status of the outputs.
MOTOROLA ANALOG IC DEVICE DATA
The SO of the MC33298 will indicate anyone of four faults.
The four possible faults are Over Temperature, Output Off
Open Fault, Short Fault (overcurrent), and VPWR
Overvoltage Fault. All of these faults, with the exception of
the Overvoltage Fault, are output specific. Over Temperature
Detect, Output Off Open Detect, and Output Short Detect are
dedicated to each output separately such that the outputs are
independent in operation. A VPWR Overvoltage Detect is of a
"global" nature causing all outputs to be turned "off."
Over Temperature Fault
Patent pending Over Temperature Detect and shutdown
circuits are specifically incorporated for each individual
output. The shutdown that follows an Over Temperature
condition is independent of the system clock or any other
logic signal. Each independent output shuts down at 155°C
to 185°C. When an output shuts down due to an Over
Temperature Fault, no other outputs are affected. The MCU
recognizes the fault since the output was commanded to be
"on" and the status word indicates that it is "off." A maximum
hysteresis of 20°C ensures an adequate time delay between
output tum "off' and recovery. This avoids a very rapid turn
"on" and turn "off' of the device around the Over Temperature
threshold. When the temperature falls below the recovery
level for the Over Temperature Fault, the device will turn "on"
only if the Command Word during the next write cycle
indicates the output should be turned "on."
Overvoltage Fault
An Overvoltage condition on the VPWR pin will cause the
MC33298 to shut down all outputs until the overvoltage
condition is removed and the device is re-programmed by
the SPI. The overvoltage threshold on the VPWR pin is
specified as 28 V to 36 V with 1.0 V typical hysteresis.
Following the overvoltage condition, the next write cycle
sends the SO pin the hexadecimal word $FF (all ones)
indicating all outputs are turned "off." In this way, potentially
dangerous timing problems are avoided and the MCU reset
10-121
m
MC33298
routine ensures an orderly startup of the loads. The
MC33298 does not detect an overvoltagfil on the VDD pin.
Other extE!rnal circuitry, such as the Motorola ,MC33161
Universal Voltage Monitor, is necessary to accomplish this
function.
Output Off Open Load Fault
An Output Off Open Load Fault is the detection and
reporting of an "open" load when the corr,esppnding output is
disabled (input in a logic high state).' To understand the
operation of the Open Loa!l Fault detect circuit, see
Figure 17. The Output Off Opel] Load Fault is detected by
comparing the drain voltage of the specific MOSFET output
to an internally generated reference. Each output has one
dedicated comparator for this purpose.
Figure 17. Output "Off" Open Load Detect
r----- Mc3s298------,
Low = Fault
"
I
50 j.1/I
VThres
0,6 to 0,8 x Voo
L ____________
RL
I
I
I
I
I
I
I
I
Output
~._I
An Output Off Open Load Faull is indicated when the
output voltage is less than the Output Threshold Voltage
(VThres) of 0.6 to 0.8 x VDD. Since the MC33298 outputs
function as switches, during normal operation, each
MOSFET output should either be completely turned "on" or
':off." By design the threshold voltage was selected to be
between the "on" and "off" voltage of the M,OSFET. During
normal operation, the "on" state VDS voltage of the MOSFET
is less than the threshold voltage and the "off' state VDS
voltage is greater than the threshold voltage. This design
approach affords using the same threshold comparator for
Output Open Load Detect in the "off' state and Short Circuit
Detect.in the "on" state. See Figure 18 for an understanding
of the Short Circuit Detect circuit With VDD =5.0 V, an "off'
state output voltage of less than 3.0 V will be detected as an
Output Off Open Load Fault while voltages greater than 4.0 V
will not be detected as a fault
The MC33298 has an internal pull-down current source of
50 11A, as shown in Figure 17, between the MOSFET drain
and ground. This prevents the output from floating up to
VPWR if there is an open load or internal wirebond failure. The
internal comparator compares the drain voltage with a
reference voltage, VThres (0.6 to 0.8 x VDD). If the output
voltage is less than this reference voltage, the MC33298 will
declare the condition to be an open load fault.
During steady-state operation, the minimum load
resistance (RL) needed to prevent false fault reporting during
normal operation can be found as follows:
VPWR =9.0 V (min)
ILCO =50 I1A
VThres (max) =(0.8 x 5.5)V = 4.4 V
10-122
Therefore, the load resistance necessary to prevent false
open load fault reporting is (using Ohm's Law) equal to 92 kn
or less.
During output switching, especially with capacitive loads,
a false Output Off Open Load Fault may be triggered. To
prevent this false fault from being reported an internal fault
filter of 25 to 100 /ls is incorporated. The duration for which a
false fault may be reported is a function of the load
impedance (RL, CL, LL), RDS( on), and Cout ofthe MOSFET as
well as the supply voltage, VPWR. The rising edge of C~B
triggers a built in fault delay timer which must time out (25
to 100 /ls) before the fault comparator is enabled to detect a
faulted threshold. The circuit automatically returns to normal
operation once the, condition causing the Open Load Fault
is removed.,
Shorted Load Fault
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply, or an output
experiencing a current greater than the current limit
There are three safety circuits progressively in operation
during load short conditions which afford system protection:
1) The device's output current is monitored in an analog
fashion using a SENSEFET'M approach and limited; 2) The
device's output current limit threshold is sensed by
monitoring the MOSFET drain voltage; and 3) The device's
output the'rmallimit is sensed and when attained causes only
the specific faulted output to be latched "off," allowing
remaining outputs to operate normally. All three protection
mechanisms are incorporated in each output affording robust
independent output operation.
'
The analog current limit circuit is always active and
monitors the output drain current. An overcurrent condition
causes the gate control circuitry to reduce the gate to source
voltage imposed on the output MOSFET which
re-establishes the load current in compliance with current
limit (3.0 to 6.0 A) range. The time required for the current
limit circuitry to act is less than 20 /ls. Therefore, currents
higher than 3.0 to 6.0 A will never be seen for more than 20 flS
(a typical duration is 10 /ls). If the current of an output
attempts to exceed the predetermined limit of 3.0 to 6.0 A
(4.0 A nominal), the VDS voltage will exceed the VThres
voltage and the overcurrent comparator will be tripped as
shown in Figure 18.
Figure 18. Short Circuit Detect and Analog
, Current Limiting Circuit
r------- Mcm;------,
I
VpWR
High = Fault
I
I
I
I
I
I
I
I
Vref
I
I
I
, VThres
I
0,6 to 0,8 x Voo
IL _________________
Output
~
MOToROLA ANALOG IC DEVICE DATA
MC33298
The status of SFPD will determine whether the MC33298
will shut down or continue to operate in an analog current
limited mode until either the short circuit is removed or
thermal shutdown is reached.
Grounding the SFPD pin will enable the short fault
protection shutdown circuitry. Consider a load short (output
short to supply) occurring on an output before, during, and
alter output tum "on." When the CSB signal rises to the high
logic state, the corresponding output is turned "on" and a
delay timer activated. The duration of the delay timer is
25 to 100 ~s. If the short circuit takes place before the output
is turned "on," the delay experienced is the entire
25 to 100 ~s followed by shutdown. If the short occurs
during the delay time, the shutdown still occurs alter the
delay time has elapsed. If the short circuit occurs alter the
delay time, shut- down is immediate (within 20 ~s alter
sensing). The purpose of the delay timer is to prevent false
faults from being reported when switching capacitive loads.
If the SFPD pin is at 5.0 V (or VDD), an output will not be
disabled when overcurrent is detected. The specific output
will, within 5.0 to 10 ~s of encountering the short circuit, go
into an analog current limited mode. This feature is especially
useful when switching incandescent lamp loads, where high
in-rush currents experienced during startup last for
10to 20 ms.
Each output of the MC33298 has its own overcurrent
shutdown circuitry. Over temperature faults and the
overvoltage faults are not affected by the SFPD pin.
Both load current sensing and output voltage sensing are
incorporated for Short Fault detection with actual detection
occurring slightly alter the onset of current limit. The current
limit circuitry incorporates a SENSEFETTM approach to
measure the total drain current. This calls for the current
through a small number of cells in the power MOSFET to be
measured and the result multiplied by a constant to give the
total current. Whereas output shutdown circuitry measures
the drain to source voltage and shuts down if a threshold
(VThres) is exceeded.
Short Fault detection is accomplished by sensing the
output voltage and comparing it to VThres. The lowest VThres
requires a voltage of 0.6 times 4.5 V (the minimum VDD
voltage) or 2.7 V to be sensed. For an enabled output, with
VDD 5.0 ± 0.5 V, an output voltage in excess of 4.4 V will be
detected as a "shorf' while voltages less than 2.7 V will not be
detected as "shorts."
=
Over Current Recovery
If the SFPD pin is in a high logic state, the circuit returns to
normal operation automatically alter the short circuit is
removed (unless thermal shutdown has occurred).
If the SFPD pin is grounded and overcurrent shutdown
occurs; removal of the short circuit will result in the output
remaining "off" until the next write cycle. If the short circuit is
not removed, the output will turn "on" for the delay time
(25 to 100 ~s) and then turn "off" for every write cycle
commanding a turn "on."
SFPD Pin Voltage Selection
Since the voltage condition of the SFPD pin controls the
activation of the short fault protection (Le. shutdown) mode
equally for all eight outputs, the load having the longest
duration of in-rush current determines what voltage (state)
MOTOROLA ANALOG IC DEVICE DATA
the SFPD pin should be at. Usually if at least one load is, say
an incandescent lamp, the in-rush current on that input will
be milliseconds in duration. Therefore, setting SFPD at 5.0 V
will prevent shutdown of the output due to the in-rush
current. The system relies only on the Over Temperature
Shutdown to protect the outputs and the loads. The
MC33298 was designed to switch GE194 incandescent
lamps with the SFPD pin in a grounded state. Considerably
larger lamps can be switched with the SFPD pin held in a
high logic state.
Sometimes both a delay period greater than 25 to 100 ~s
(current limiting of the output) followed by an immediate over
current shutdown is necessary. This can be accomplished by
programming the SFPD pin to 5.0 V for the extended delay
period to afford the outputs to remain "on" in a current limited
mode and then grounding it to accomplish the immediate
shutdown alter some period of time. Additional external
circuitry is required to implement this type of function. An
MCU parallel output port can be devoted to controlling the
SFPD voltage during and alter the delay period, is often a
much better method. In either case, care should be taken to
execute the SFPD start-up routine every time start-up or
reset occurs.
Undervoltage Shutdown
An undervoltage VDD condition will result in the global
shutdown of all outputs. The undervoltage threshold is
between 2.5 V and 4.5 V. When VDD goes below the
threshold, all outputs are turned "off' and the SO register is
reset to indicate the same.
An undervoltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5 V
and 9.0 V, the outputs will operate per the command word.
However, the status as reported by the serial output (SO) pin
may not be accurate. Proper operation at VPWR voltages
below 5.5 V cannot be guaranteed.
Deciphering Fault Type
The MC33298 SO pin can be used to understand what
kind of system fault has occurred. With eight outputs having
open load, over current and over temperature faults, a total of
25 different faults are possible. The SO status word received
by the MCU will be compared with the word sent to the
MC33298 during the previous write cycle. If the two words
are not the same, then the MCU should be programmed to
determine which output or outputs are indicating faults. If the
command bit for any of the output switches indicating a fault
is high, the fault is an open load.
The eight open load faults are therefore the ones most
easily detected. Over current and over temperature faults are
often related. Turning the affected output switches "off" and
waiting for some time should make these faults go away.
Over current and over temperature faults can not be
differentiated in normal application usage.
One advantage of the synchronous serial output is that
multiple faults can be detected with only one pin (SO) being
used for fault status indication.
If VpWR experiences an overvoltage condition, all outputs
will immediately be turned "off' and remain latched "off."
A new command word is required to turn the outputs back
"on" following an overvoltage condition.
10-123
1
I
MC33298
Output Voltage Clamping
Each output of the MC33298 incorporates an internal
voltage clamp to provide fast turn-off and transient protection
of the output. Each clamp independently limits the drain to
source voltage to 65 V at drain currents of 0.5 A and keeps
the output transistors from avalanching by causing the
transient energy to be disSipated in the linear mode (see
Figure 19). The total energy (EJ) can be calculated by
multiplying the current area under the current curve (lA)
during the time the clamp is active and the clamp
voltage (VcLl.
Characterization of the output clamps, using a single pulse
repetitive method at 0.5 A, indicate the maximum energy to
be 100 mJ at 25°C and 25 mJ at 125°C per output. Using a
single pulse non-repetitive method at 0.5 A the clamps are
capable of 2.0 Joules at 25°C and 0.5 Joules at 125°C.
Figure 19. Output Voltage Clamping
Drain-to-Source Clamp ,
Voltage (VCl = 65 V)
_ _ _ _--,
Drain Voltage
Drain Current
(10 = 0.5 A) - - - f , \
'----VpWR
Drain-ta-Source "On"
Voltage (VDS(ON))
Gnd ==~'-------'~---- Time
THERMAL CHARACTERIZATION
Thermal Model
Logic functions take up a very small area of the die and
generate negligible power. In contrast, the output transistors
take up most of the die area and are the primary contributors
of power ge.neration. The thermal model shown in Figure 20
was developed for the MC33298 mounted on a typical PC
board. The model is accurate for both steady .state and
transient thermal conditions. The components RdO, Rd1,
Rd2, ... , and Rd7 represent the steady state thermal
resistance of the silicon die for transistor outputs 0, 1, 2, ... ,
and 7, while CdO, Cd1, Cd2, ... , and Cd7 represent
the corresponding thermal capacitance of the silicon
die transistor outputs and plastic. The device area and
die thickness determine the values of these specific
components.
The thermal impedance of the package from the internal
mounting flag to the outside environment is represented by
the terms Rpkg and Cpkg. The steady state thermal resistance
of leads and the PC board make up the steady state package
thermal resistance, Rpkg. The thermal capaCitance of the
package is made up of the combined capacitance of the flag
and the PC board. The mold compound was not modeled as
a specific component but is factored into the other overall
component values.
The battery voltage in the thermal model represents the
ambient temperature the device and PC board are subjected
to. The IPWR current source represents the total power
dissipation and is calculated by adding up the power
dissipation of each individual output transistor. This is easily
done by knowing RDS(on) and load current of the
individual outputs.
Very satisfactory steady state and transient results have
been experienced with this thermal model. Tests indicate the
model accuracy to have less than· 10% error. Output
interaction with an adjacent output is thought to be the main
contributor to the thermal inaccuracy. Tests indicate little or
no detectabie thermal affects caused by distant output
transistors which are isolated by one or more other outputs.
Tests were conducted with the device mounted on a typical
PC board placed horizontally in a 33 cubic inch still air
enclosure. .The PC board was made of FR4 material
measuring 2.5" by 2.5", having double-sided circuit traces of
1.0 oz. copper soldered to each device pin. The board
temperature was measured with thermal couple soldered to
the board surface one inch away from the center of the
10-124
device. The ambient temperature of the enclosure was
measured with a second thermal couple located over the
center and one inch distant from device.
Thermal Performance
Figure 20 shows the worst case thermal component
parameters values for the MC33298 in the 20 pin plastic
power DIP and the SOP-24 wide body surface mount
package. The power DIP package has Pins 5,6,15, and 16
connected directly to the lead frame flag. The parameter
values indicated take ·into account adjacent output cell thermal
pulling effects as well as different output combinations. The
characterization was conducted over power dissipation levels
of 0.7 to 17 W. The junction-to-ambient temperature thermal
resistance was found to be 3YOCIW with a single output
active (31 °CIW with all outputs dissipating equal power) and
in conjunction with this, the thermal resistance from junction
to PC board (Rjunction-board) was found to be 27°CIW (board
temperature, measured 1" from device center). In addition,
the thermal resistance from junction-to-heatsink lead was
found to approximate 10°CIW. Devoting additional PC board
metal around the heatsinking pins improved Rpkg from 30° to
28°CIW.
The SOP-24 package has Pins 5,6,7,8, 17, 18, 19, and
20 of the package connected directly to the lead frame flag.
Characterization was conducted in the same manner as for
the DIP package. The junction-to-ambient temperature
resistance was found to be 40°CIW with a single output
active (34°CIW with all outputs dissipating equal power) and
the thermal resistance from junction-to.,..PC board
(Rjunction-board) to be 30°C/W (board temperature,
measured 1" from ·device center). The junction-to-heatsink
lead resistance.· was found again to approximate 10°CIW.
Devoting additional PC board metal· around the heatsinking
pins for this package improved the Rpkg from 33° to 31 °CIW.
The total power dissipation available is dependent on the
number of outputs enabled at anyone time. At 25°C the
RDS(on) is 450 mQ with a coefficient of 6500 ppm/DC. For the
junction temperature to remain below 150°C, the maximum
available power dissipation must decrease as the ambient
temperature increases. Figures 21 and 22 depict the per
output limit of current at ambient temperatures necessary for
the plastic DIP and SOP packages respectively when one,
four, or eight outputs are enabled "on." Figure 23 depicts how
the RDS(on) output value is affected by junction temperature.
MOTOROLA ANALOG IC DEVICE DATA
MC33298
Figure 20. Thermal Model (Electrical Equivalent)
Junction Temperature Node
VD=TD(OC)
(Volts represent Die Surface Temperature)
Output 0
Output 1
Output 2
Output 6
Cd2 - - - - - - - - -
+
IpWR (Steady State or Transient)
(1.0 A = 1.0 W of Device Power Dissipation)
Rpkg = Rleads + RpC Board
Rpkjl
(0)
Package
Cp k,,9
Cpkg = Cnag + Cpc Board
±
Ambient Temperature Node
VA =TA(OC)
(f.O V = 1°C Ambient Temperature)
(F)
20 Pin DIP
7.0
0.002
30
0.2
SOP-24L
7.0
0.002
33
0.15
*Q
Cd?
=°CIW, F =W sl°C, IpWR =W, and VA =°C
MOTOROLA ANALOGIC DEVICE DATA
10-125
MC33298
5:
Figure 21. Maximum DIP Package Steady State.
Output Current versus Ambient Temperature
5:
~O
3.0,---,.----,.----,---r--...,.-...,.---,--,
!3
2.5 f-""",+---+---I---+-
§
I-
2.0 f--+---+--~...:::::--+--t--f--+---i
~
~
~-
I
2.0 f--+---+---=="'Io..,---+--t--f--+---i
ffi
1.5
0-
II:
II:
i3
U
~
1.0
2.5 ro::--,--,----,---,----,--,---,---,
w
II:
=>
:2
Figure 22. Maximum SOP Package Steady State
Ouput Current versus Ambient Temperature
1-T-;;;;;:+:::t:::t....~:::=-I~'t-1
~
1.0 t--o;;;;±:::--+-+=-....,.=-t--I-~d----l
~
0.5 f-:"':":F'--'-1--"'-'--"-t'-'---I---F""""""",,"~""""--'I..-l
:2
0.5 f---!..t-~:r-~+---I--+==="'I--~"""":4..-l
1
0 '----'----'---'-----'----'--'----'---..1
-50 -25
0
25
50
75
100
125
150
OL-__
-50
L-~
__
~
o
-25
TA, AMBIENT TEMPERATURE (0C)
__
25
~
__
50
~
__
75
~
__
100
~
__
125
~
150
TA, AMBIENT TEMPERATURE (0C)
Figure 23. Maximum Output "On" Resistance
versus Junction Temperature
9:w
0.9
u
z
0.8 -
1i)
0.7
f'!:
en
VPWR= 13 V
VOO=5.0V
lour=0.5A
V
./
w
II:
Z
0.6
!3
0.5
OJ
0.4
9
~
0
./
/"
. / V"
'2
[}; 0.3
0
II:
0.2
-50
;'
/
-25
o
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (OC)
10-126
MOTOROLA ANALOG IC DEVICE DATA
MC33298
Latch-Up Immunity
Device latch-up caused by substrate injection has been
characterized. Latch-up immunity has both a dc and a
transient immunity component. DC latch-up immunity results
indicate the device to be capable of withstanding in excess of
four amps of reverse current out of any of the output
transistors while the control logic continues to function
normally. The logic control current (100) was found to
increase by only 0.6 mA with four amps of current being
pulled out of an output. Additionally, the IpWR current was
found to increase by only 0.15 mA under the same condition.
These increases are a result of minority carriers being
injected into substrate and subsequently being collected.
The following procedure has been developed to test for
transient latch-up immunity and has been applied to this
automotive circuit design. Results of transient testing indicate
the device to operate properly at output currents greater than
1.5 A. The procedure tests for the device's immunity to
intermittent load to battery current connection with the device
controlling an inductive load. Appropriately termed '1he file
test," the battery is connected to a shop file while the lead to
the inductive load is dragged across the files surface causing
intermittent load opens producing lots of arcs, sparks, and
smoke, plus severe transients (see Figure 24). It is during
these severe transients that latch-Up most likely could occur.
The battery voltage used for this test was 18 V and the
inductive load was 2.0 mHo These values were found to
produce severe transient stresses of the device outputs. All
outputs must maintain operation and input control during
transient generation to pass "the file test."
The device's input control currents were found to remain
stable and were not affected by dc or transient latch-up
immunity testing.
Figure 24. Transient Latch-Up Immunity File Test
II
Output 0
~!. -
1-0
1-0
1-7
l.o
I
I
APPLICATIONS INFORMATION
SlOP Communication
Two common communication protocols used in Motorola's
microprocessors are the Serial Peripheral Interface (SPI) and
Synchronous Input Output Port (SlOP). SlOP is a subset of
the more flexible SPI and the simpler of the two protocols.
SlOP is used on many of the MC68HC05 family of
microcontrollers. Restrictions of the SlOP protocol include:
1) the SCLK frequency is fixed at one-fourth the internal
clock rate and 2) the polarity of the SCLK signal is fixed.
By way of example, the MC68HC05P9 utilizes SlOP
protocol and is not directly compatible with the serial input
requirements of the MC33298. Specifically, the MG33298
accepts data on the falling edge of SCLK whereas its rising
edge triggers data transfer in the SlOP protocol. SCLK is high
during SlOP transmissions, which is the opposite of what the
MC33298 requires.
Though designed specifically for SPI communication
protocol, the MC33298 can easily be adapted to
communicate with SlOP protocol through the use of
software. The amount of code required to implement SPI in
software is relatively small, so the only major drawback is a
slower transfer of data. The software routine shown in
Table 1 completes a transfer in about 100 Ils.
MOTOROLA ANALOG IC DEVICE DATA
Cost
The bottom line relates to cost. The MC33298 is a very
cost effective octal output serial switch for applications
typically encountered in the automotive and industrial market
segments. To accomplish only the most basic serial switch
function the MC33298 offers, using a discrete semiconductor
approach, would require the use of at least eight logic level
power MOSFETs for the outputs and two shift registers for
the 1/0 plus other miscellaneous "glue" components.
Additional circuitry would have to be incorporated to
accomplish the protection features offered by the MC33298.
Other noteworthy advantages the MC33298 offers are
conservation of power and board space, requirement of
fewer application components, and enhanced application
reliability. The MC33298 is available at a fraction of the cost
required for discrete component implementation and
represents true value.
The MC33298 represents a cost effective device having
advanced performance and features and worthy of
consideration.
10-127
MC33298
Table 1. Program to Exercise the MC33298 Using SPI (Having Only SlOP) Protocol
SET LABELS FOR OUTPUT REGISTERS
PORTA
EClU
$0000
;SPI Port
;DO (Data Out), SCLK, CS, RESET, X, FLTOUT, DI (Data In)
PORTB
EQU
$0001
;Normally the SlOP Port. SlOP will be disabled
PORTC
EQU
$0002
;A-D Converter Port
PORTD
EQU
$0003
;Tlmer Capture Port
DORA
EQU
$0004
;Data Direction Register for SPI Port
DDRB
EQU
$0005
;Data Direction Register for SClK, SOl, SDO, 11111
DDRC
EQU
$0006
;Data Direction Register for A-D Converter Port
DDRD
EQU
$0007
;Data Direction Register for PORTO, Timer Capture
DTOUT
EQU
$0080
;Register for the SPI output data. This register will be used for a Seriai-to-Paralleltransformation.
DATAIN
EQU
$0081
;Input Register for SPI. Also used for a Serial-to-Parallel transformation.
VALUE
EQU
$0082
;Register to store the SPI. Also used for a Seriai-to-Paralleltransformation.
DATAl
EQU
$0083
;Miscellaneous data register
SCR
EQU
$OOOA
;label for SlOP control register, 0 SPE 0 MSTR 0 0 0 O.
SSR
EQU
$ooOB
;label for SlOP status register, SPIF DCOl 0 0 0 0 0 0, Read Only Register.
SDR
EQU
$OOOC
;label for SlOP data register.
;Program starts at first byte of User ROM.
;Reset Stack Pointerto $FF.
;Configuration PortA as the SPI Port.
;AII but Bit 0 will be outputs.
lOA
#$FF
STA
DDRB
STA
DDRC
;Configure Register C as an output
STA
DDRD
;Configure Register D as an output
;Configure Register B as an output. SlOP is not used for the MC33298, but is available for
another peripheral.
;Initialize the SlOP Control Register.
;Disable SlOP by clearing Bit 6.
SELECT THE DESIRED OUTPUTS
TOP
lOA
STA
#$55
VALUE
Select outputs of MC33298 to be turned "on." This instruction is left inside the loop to include
changes while running the program. A set bit will cause the associated MC33298 output to be
"off." The value register is uncorrupted by the serial-to-parallel conversion.
BSET
4,PORTA
;Reset the MC33298.
BClR
4,PORTA
;Also establishes a + or - trigger source
BSET
4,PORTA
;The MC33298 is reset with a logic low.
;Enable MC33298 by pulling CSB (chip select bar) low. Within the MC33298 the Fault Status is
transferred to the MC33298 Serial Register at a falling edge of CSB.
;Select outputs to be turned "on."
;Save Output Word (Value) to check for fault.
10-128
MOTOROLA ANALOG IC DEVICE DATA
MC33298,
SPI TRANSFER LOOP
;Set the number of Read/Shift cycles,
LDX
#$07
ASL
DATAIN
ASL
DTOUT
;Test value currently in MSB of DTOUT,
BCS
DOONE
;
BCLR
7,PORTA
;MSB was Zero, so clear DATA OUT bit
JMP
GOON
DOONE
BSET
7,PORTA
;MSB was One, so set the DATA OUT bit
GOON
BSET
6,PORTA
;Set the SCLK. Serial Output pin of the MC33298 changes state on the rising edge of the SCLK.
Read the next bit coming from the MC33298,
BRCLR
O,PORTA,
WZZERO
;Read the bit and branch if Zero, LSB of DATAIN is already cleared due to the ASL above,
BSET
O,DATAIN
;Bit was One, Set the next bit in DATAIN,
BCLR
6,PORTA
;Clear SCLK. Falling edge causes the MC33298 to read the next bit from the MCU,
LOOP
WZZERO
;Shift a Zero into LSB of DATAIN and ASL other bits,
DECX
BPL
LOOP
;Continue to loop eight times until the SPI transfer is complete,
;Transfer control signal to output transistors,
ESTABLISH A BRIEF DELAY
LOA
PAUSE
#16
DECA
;3 Clock cycles
BNE
PAUSE
;3 Clock cycles
BCLR
5,PORTA
;Transfer output status to Serial Register,
JSR
FLTCHK
;Jump to Fault Check subroutine,
JSR
DLY
;Delay 1fT msec
;Deselect the MC33298.
;Return to top of loop,
SUBROUTINE TO CHECK FOR FAULTS
FLTCHK
NOFLT
BCLR
1,PORTA
LDA
DATAIN
CMP
VALUE
BEQ
NOFLT
BSET
1,PORTA
;CLR the Fault pin,
;Check for Faults.
;11 there is no Fault, continue,
;Activate Fault LED,
RTS
MOTOROLA ANALOG IC DEVICE DATA
10-129
MC33298
DELAY SUBROUTINE
OLY
STA
OATA1
LOA
#$04
OUTLP
CLRX
INNRLP
OECX
BNE
;X used as Inner Loop Count
;O-FF, FF-FE, ... 1-{) 256 loops.
INNRLP
;6CYC* 256* 1.0 !!SICYC = 1.53 ms
;4-3. 3-2, 2-1, 1-{)
OECA
BNE
OUTLP
;1545CYC* 4*1.0 IlsfCYC = 6.18 ms
LOA
OATA1
;Recover Accumulator value.
;Retum from subroutine.
RTS
10-130
;Save Accumulator in RAM.
;00 outer loop 4 times, roughly 4.0 ms.
ORG
$1FF
FOB
INIT
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC79076
MCCF79076
Product Preview
Electronic Ignition
Control Circuit
The MCCF79076, in conjunction with an appropriate Motorola Power
Darlington Transistor, provides an economical solution for automotive
ignition applications. The MCCF79076 offers optimum performance by
providing closed loop operation of the Power Darlington in controlling the
ignition coil current.
The MCCF79076 incorporates Flip-Chip Technology which involves the
formation of solder bumps, rather than traditional wire bonds, to establish
mechanical and electrical contact to the semiconductor chip. This process
affords a unique device having improved reliability at elevated operating
temperatures.
ELECTRONIC IGNITION
CONTROL CIRCUIT
SEMICONDUCTOR
TECHNICAL DATA
•
• Solder Bumped for Flip-Chip Assembly
• Ignition Coil Voltage Internally Limited to 375 V
DWSUFFIX
PLASTIC PACKAGE
CASE 751G
(So-16L)
• Coil Current Limiting to 7.5 A
• Output On-Time (Dwell) Control
• Dwell Feedback Control to Sense Coil Variation
• Hall Sensor Input
• - 30°C :5 TA :5 +140°C Ambient Operating Temperature
FLIP-CHIP CONFIGURATION
0
0
4 0
.L
5 ',r
2
0
0
0
0
0
3
.L
6 "'\,r
00 0
7
Simplified Block Diagram
and Application Circuit
13
12
11
10
9
8
Top View
(Bump Side)
BUMP CONNECTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Hall
Sensor
input
I-= IL
ORDERING INFORMATION
L -_ _ _- - - '
____________ _
1
Device
MCCF79076
MC79076DW
MOTOROLA ANALOG IC DEVICE DATA
High Ground
Oulpul Current Limij
Dwell Output
Supply
Low Ground
Reference Dwell Input
Advance Input
Bias Voltage
Est Input
Reference Output
Bypass Input
900 RPM Detector
Dwell Control
Operating
Temperature Range
TA = - 30° to +125°C
Package
Flip-Chip
So-16L
10-131
®
MOTOROLA
MCCF33093
Product Preview
Ignition Control Flip-Chip
Designed for automotive ignition applications. The MCCF33093 provides
outstanding control of the ignition coil when used with an appropriate
Motorola Power Darlington Transistor. Engine control systems utilizing the
MCCF33093 exhibit exceptional fuel efficiency and low exhaust emissions.
The MCCF33093 requires a differential Hall Sensor input for proper
operation.
The MCCF33093 utilizes Flip-Chip Technology in which solder bumps,
rather than traditional wire bonds, are created to establish mechanical and
electrical contact to the chip. This process affords a unique device having
improved reliability at elevated operating temperatures.
• Solder Bumped for Flip-Chip Assembly
• External Capacitors to Set Device TIming
IGNITION CONTROL
FLIP-CHIP
SEMICONDUCTOR
TECHNICAL DATA
FLIP-CHIP CONFIGURATION
• Overvoltage Shutdown Protection
14
• Auto Start-Up Capability Once Overvoltage Condition Ceases
• Allows for Push Start-Up in Automotive Applications
13
0
12
0
11
0>
• Ignition Coil Current Limiting
• Ignition Coil Voltage Limiting
0
• Bandgap Reference for Enhanced Stability Over Temperature
• Negative Edge Filter for Hall Sensor Input Transient Protection
• Hall Sensor Inputs for RPM and Position Sensing
• - 30°C ~ TA ~ +140°C Ambient Operating Temperature
.J
9
.J
2
0
3
0
4
0
5
0
6
1
1
10
0
0
\..
't'
1
\..
'I'
0
0
8
7
(Backside View)
0.116 inch x 0.091 Inch
Backside orientation marking
indicated by arrow oriented as shown
Simplified Block Diagram
and Application Circuit
Vee
o
BUMP CONNECTIONS
1. Ground
Master Bias
Adaptive Capacijor
Ramp Capacitor
Positive Hall Input
Negative Hall Input
7. Start
B. Supply
9. Distributor Signal
10. Coil
11. Output
12. Process Test
13. Emitter of Dariington
14. Stall Capacitor
2.
3.
4.
5.
6.
In (+) -'VV'v-V,...,
In (-) -'VV'v-U...,
SW~~~~----~~~~
l.Ok
ORDERING INFORMATION
Operating
Temperature Range
Package
MCCF33093 TA ~ -30° to +140°C
Flip-Chip
Device
10-132
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MCCF33094
Product Preview
Ignition Control Flip-Chip
Designed for automotive ignition applications. The MCCF33094 provides
outstanding control of the ignition coil when used with an appropriate
Motorola Power Darlington Transistor. Engine control systems utilizing the
MCCF33094 exhibit exceptional fuel efficiency and low exhaust emissions.
For proper operation, the MCCF33094 requires a single Hall Sensor input
signal, which is compared to an accurate internal reference.
The MCCF33094 utilizes Flip-Chip Technology in which solder bumps,
rather than traditional wire bonds, are created to establish mechanical and
electrical contact to the chip. This process affords a unique device having
improved reliability at elevated operating temperatures.
• Solder Bumped for Flip-Chip Assembly
IGNITION CONTROL
FLIP-CHIP
SEMICONDUCTOR
TECHNICAL DATA
FLIP-CHIP CONFIGURATION
• External Capacitors to Set Device Timing
14
• Overvoltage Shutdown Protection
• Auto Start-Up Capability Once Overvoltage Condition Ceases
13
0
12
0
11
0
0
0
2
0
3
0
4
0
5
0
6
• Allows for Push Start-Up in Automotive Applications
• Ignition Coil Current Limiting
• Ignition Coil Voltage Limiting
• Bandgap Reference for Enhanced Stability Over Temperature
• Negative Edge Filter for Hall Sensor Input Transient Protection
• Hall Sensor Inputs for RPM and Position Sensing
>
!
10
.J
9
.J
• - 30°C::; TA::; +140°C Ambient Operating Temperature
L
',"
!
0
L
',"
1
0
0
7
(Backside View)
0.116 inch x 0.091 inch
Backside orientation marking
indicated by arrow oriented as shown
Simplified Block Diagram
and Application Circuit
o
Vee
330
55
BUMP CONNECTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
In (+1 -'VV'v--<::>-i--,
SW~~~ot----~~~~
1.Ok
Ground
Master Bias
Adaptive Capacitor
Ramp Capacitor
Positive Hall Input
N.C.
Start
Supply
Distributor Signal
Coil
Output
Process Test
Emitter of Darlington
Stall Capacitor
ORDERING INFORMATION
Operating
Temperature Range
Package
MCCF33094 TA = -30' to +l40°C
Flip-Chip
Device
MOTOROLA ANALOG IC DEVICE DATA
10--133
®
MOTOROLA
MCCF33095
MC33095
Advance Information
Integral Alternator Regulator
The MCCF33095 (Flip-Chip) and MC33095 (Surface Mount) are
regulator control integrated circuits designed for use in automotive 12 V
alternator charging systems. Few external components are required for full
system implementation. These devices provide control for a broad range of
12 V alternator charging systems when used in conjunction with the
appropriate Motorola Power Darlington transistor to control the field current
of the specific alternator.
Both versions have internal detection and protection features to withstand
extreme electrical variations encountered in harsh automotive environments.
Flip-Chip Technology allows the MCCF33095 to operate at higher ambient
temperatures than the surface mount version in addition to withstanding
severe vibration and thermal shock with a high degree of reliability.
INTEGRAL
ALTERNATOR
REGULATOR
SEMICONDUCTOR
TECHNICAL DATA
3
2
• Constant Frequency with Variable Duty Cycle Operation
• Adjusts System Charging to Compensate for Changes
in Ambient Temperature
A
$. 9
....
. .t- . .$~ . . $~ . .~
• Slew Rate Control to Reduce EMI
5
• Lamp Pin to Indicate Abnormal Operating Conditions
• Shorted Field Protection
• Resumes Normal Operation Once Fault Condition Ceases
• Operation from -40°C to 170°C for Flip-Chip and -40°C to 125°C
forSO-14
6
7
8
FLiP-CHIP CONFIGURATION
(Backside View)
Back marking is oriented as shown
• Surface Mount or Solder Bump Processed Flip-Chip Assembly Versions
Simplified Block Diagram
1m
4(8)
Ignition
+
Load Dump
Detection and
Protection
DSUFFIX
PLASTIC PACKAGE
CASE 751A
(S0-14)
+
6(4)
Oscillator
,t-~=tj;~~gL~-l--~tW9(')
Darlington
Drive
2(11)
Sense
Function
So-14 (Note 1)
I
2
VCC
Sense
Stator
Ignition
Lamp
Oscillator
Roll-Off
Ground
Darlington Drive
Short Circuit
(12)
(11)
(10)
3
4
5
6
7
8
9
10
10(14)
Short
Circuit
3(10)
Stator
Bump
(4)
(3)(Note 2)
(2)
(1)
(14)
7(3)
Rotl-Off
-=-
NOTES: 1. No connections to Pins 3, 6, 7, 9 and 13.
2. Connected to ground internal to package.,
ORDERING INFORMATION
Operating
Temperature Range
Package
MCCF33095 TA =-40° to +170°C
Flip-Chip
Device
This device contains 145 active transistors.
10-134
(8)
(5)
MC33095D
TA =-40° to +125°C
S0-14
MOTOROLA ANALOG IC DEVICE DATA
MCCF33095 MC33095
MAXIMUM RATINGS (Notes 1 and 3)
Symbol
Value
Unit
Steady State VCC, VIGN, VSTA
Rating
-
9.0 to 24
V
VCC and VIGN Transient
-
80
V
8.0
GramslBump
RSJS
RaJA
29
145
Bump Shear Strength (Flip-Chip)
Thermal Characteristics (Thermal Resistance)
Junction-to-Substrate (Flip-Chip)
Junctlon-ta-Ambient (So-14)
°CIW
Junction Temperature
Flip-Chip
So-14
TJ
Operating Ambient Temperature Range
Flip-Chip
So-14
TA
°C
170
150
°C
-40 to +170
-40 to +125
ELECTRICAL CHARACTERISTICS (Limit values are given for -40°C :5 TA :5 150°C (Flip-Chip), -40°C :5 TA :5 125°C
=
(So-14) and typical values represent approximate mean value at TA 25°C. Oscillator, Roll-Off, Ground, Short Circuit
and 12 V:5 VCC, Sense, Stator, Ignition:5 16 V, unless otherwise specified.)
=0 V,
Characteristic
SUPPLY (VCC)
Supply Current
Disabled (Ignition = 0.5 V, Stator 5.0 V)
Enabled (VCC, Sense = 17 V, Ignition = 1.4 V)
ICC
=
Dariington Drive Overvoltage
Disable Threshold (VCC, Ignition, Short Circuit = 19 V to 29 V Ramp, Stator = 10 V)
Hysteresis (VCC, Stator, Ignition, Short Circuit = 29 V to 19 V Ramp)
Lamp Overvoltage
Disable Threshold (VCC, Stator, Ignnion, Short Circuit = 19 V to 29 V Ramp)
Hysteresis
-50
0
0.2
3.9
300
25
VCODD
VCODDH
19
26
4.2
28.5
VCOl
VCOLH
19
22.3
0.3
29.5
~
mA
V
-
V
-
-
SENSE
Sense Current (Oscillator = 2.0 V)
Calibration Voltage (50% Duty Cycle) (Note 5)
Lamp Comparator Detect Threshold
Proportional Control Range
Lamp Comparator Reset Threshold
Lamp Hysteresis
ISNS
-10
0.6
10
~
VR
12.25
14.6
17.5
V
VSCD
-
16.3
-
V
MV
50
187.4
350
mV
VHV
15.4
15.9
16.4
V
VHYS
20
416.6
600
mV
ms
STATOR
Propagation Delay (Lamp-ta-High, Stator = 15 V to 6.0 V)
tSTA
6.0
59.4
600
Reset Threshold Voltage (Lamp-to-Low, Stator = 5.0 V to 11 V)
VIH
6.0
8.8
11
V
Input Current (Sense = 18 V, Oscillator = 2.0 V)
ISTA
-10
1.5
10
~
mV
LAMP
Saturation Voltage (Lamp = 14 mAl
VOLL
0
111.8
350
Leakage Current (Sense = 1.0 V, Lamp = 2.5 V)
IOHL
-50
0.8
50
~
VOOLL
0
147.4
350
mV
Saturation Voltage (VCC, Sense, Stator, Ignition = 30 V, Lamp
=20 mAl
NOTES: 1. vee applied through a 250 !l resistor.
2. Sense input applied through a 100 k!l and 50 k!l resistor divider to generate one-third Vbat.
3. Stator and Ign~ion inputs applied through a 20 k!l resistor.
4. Short Circu~ input applied through a 30 k!l resistor.
5. Oscillator pin connected in series with 0.0221'F capacitor to ground.
MOTOROLA ANALOG IC DEVICE DATA
10-135
MCCF~3095 MC33095
ELECTRICAL CHARACTERISTICS (continued) (Limit values are given for -40°C :S TA :S 150°C (Flip-Chip), -4Q°C :S TA :S 1. 25°C
=
(SO-14) and typical values represent approximate mean value at TA 25°C. Oscillator, Roll-Off, Ground, Short Circuit
and 12 V:s VCC, Sense, Stator, Ignition:S 16 V, unless otherwise specified.)
=0 V,
DARLINGTON DRIVE
Source Current (Pins VCC, Sense, Ignition = 9.0 V, Darlington Drive = V across
Power Darlington)
10HDD
Saturation Voltage (Sense = 18 V, Oscillator = 2.0 V, Darlington Drive = -100 !LA)
VOLDD
0
174.7
Minimum ·On" Time (Sense = 18 V) (Note 5)
4.0
too
200
Frequency (Note 5)
FOSC
75
Minimum Duty Cycle (Sense = 18 V) (Note 5)
7.6
20
mA
300.1
350
mV
697.8
700
!1S
325
Hz
DCDD
4.0
12.2
13
%
Rise Time (10% to 90%) (Note 5)
tr
10
21.4
50
!1S
Fall Time (90% to 10%) (Note 5)
tf
10
23.7
50
!1S
SHORT CIRCUIT
Duty Cycle (Note 5)
"On" Time (Short Circuit High, Short Circuit = 8.0 V) (Note 5)
NOTES: 1. Vee applied through a 250 Q resistor.
2. Sense input applied through a 100 kQ and 50 kQ resistor divider to generate on&-thlrd Vbat.
3. Stator and Ignition inputs applied through a 20 kQ resistor.
4. Short eircu~ input applied through a 30 kQ resistor.
5. Oscillator pin connected In series with 0.022 "F capacitor to ground.
Figure 1. Flip-Chip Mechanical Dimensions
""'1"-3----
0.025R oITrue Position
0
,L
o----~~:r:-------~~--~
+--<:+_ :-
4
f--__....:.
'[
+;'[
J
10
9
~:--f:-
5
6
-.-__,-__1--,
;+:
+;-
,L
7
8
I
-B0
r,."""0.140
2.032
2
,..-::.-.------=:...----+-.....",
0.185 - - -
0.216 O' 10 PI
0.127 Ia.
aces
'"ci~
L-Y ~
t
0559
0'483
.
0.029
.
Maximum taper either
direction allowed, 4 edges.
Die sawed through.
NOTES: 1. All dimensions shown indicated in millimeters.
2 ' 1 1 Denotes basic dimension having zero
~ tolerance and describes the theoretical
exact location (true position) or contour.
10-136
MOTOROLA ANALOG IC DEVICE DATA
MCCF33095 MC33095
Figure 2. Pins 1, 3 and 4 Field Transient Decay
~
UJ
(!)
13
g
VFT =14.5 V for 02:12: 0.38 sec
VFT =- 75 ell0.038 for 0 SIS 0.38 sec
20 I--Refer 10 Noles 1 10 5 01 Eleclrical Table
14 .5V for Circuit Hook-Up
0
1
0
~
-'
UJ
u::
!z
UJ
enz
«
....a:
ti::
Figure 3. Pins 1 and 4 Load Dump Transient Decay
40
-20
/
-40
y
---
~
J
UJ
(!)
0
60
!z
UJ
40
~
~
16.5
16.0
(;
5~
~
a:
f2
.:, 20
-'
20
14.5
UJ
(!)
14.0
13g
13.5
E
r---_ -,..
to-..
-......
1"'--
40
60
80
I, TIME (ms)
100
380
400
o
o
420
--
100
Figure 5. Vbat (50% Duty Cycle) versus
Vbat (Lamp "On")
---r--_ -
-... -----r--..
-- -----Minimum
- - ---..
40
80
120
160
13
TA, TEMPERATURE ('C)
0
0
-'
UJ
u::
0.050
Ii.
0.025
~ 1.5
!z
w
'" "
1.4
14.5
15
15.5
16
16.5
Figure 7. Field Current versus Time
Vbat= 14.4 V
Duty Cycle = 6.0% _
TA = 25'C
/\
14
2.0
II
A
13.5
Vbal FOR A 50% DUTY CYCLE (V)
Figure 6. Field Current versus Cycle Time
1.025
::>
400
Maximum
~ical
o
a: 0.075
a:
300
1'-__
>
!z
UJ
"
200
t, TIME(ms)
...
13.0
~ 1.000
"-
>
15.5
15.0
.........
....
Figure 4. Temperature versus
Vbat for 50% Duty Cycle
~
o
"'- "-
en
z
«
a:
V
-75
-20
~
g
I
-60
>
80
VLD = 80 e- 51 for 0 SIS 0.342 sec
VLD = 14.5 Vlorl 2: 0.342 sec
ReIer 10 Noles 1 10 5 of Electrical
Table lor Circuit Hook-Up
a:
a:
::>
0
0
---
'"'"
1.0
-'
w
u::
~ 0.5
............
Vbal= 14.4 V
Duty Cycle = 86%
TA = 25'C
r--
2.8
SC, CYCLE TIME (ms)
MOTOROLA ANALOG IC DEVICE DATA
4.2
5.6
o
o
1.4
2.8
4.2
5.6
SC, CYCLE TIME (ms)
10-137
MCCF33095 MC33095
Figure S. Integral Alternator Regulator System
r---~--------~~------------------------------~A
250Q
r-----~--------~~S~~------~------~~,
1.0k
100 k
18k
r - 1 (gL-=- ____ 3l!.°L _ _ ,
I Vee
2 ",,11"-1I SENSE
.--__-+-____=.c
I
SOk
0.022
STATOR
II
MCCF33095
~ose
I1
30k
se t--1....;0('-'4)...J\fIII.-__-+---,
DD t-=9..>.:1:L.-__-r...
I
I
I
L IGN - - - - 5 ( 5 )lMP-7ii[8if
RO
GND J
4(s)
Power Ground
20k
10Q
10-138
1.0k
2.4 k
Battery
=
I
MOTOROLA ANALOG IC DEVICE DATA
MCCF33095 MC33095
FUNCTIONAL DESCRIPTION
Introduction
This ignition control circuit was originally designed and
offered as an MCCF33095 Flip-Chip for use in 12 V
automotive altemator charging systems. The MCCF33095
consists of many protection features which are entailed in a
ten pin flip-chip package. The device was subsequently
made available in a 14 pin surface mount version
(MC33095D). Both versions perform in a similar manner. The
Flip-Chip version has an advantage over the surface mount
version where minimized space and higher operating
ambient temperatures are of major concern. Device
operation and application suggestions for both versions are
given below.
Oscillator
The oscillator frequency is determined by the value of an
external capacitor from the Oscillator pin to ground (see
applications circuit). The oscillator frequency in a typical
application is approximately 175 Hz, but a range of 50 Hz to
500 Hz can reasonably be used. The waveform generated
consists of a positive linear slope followed by relatively fast
negative fall (sawtooth). The flip-flops are reset by the falling
edge of the sawtooth signal as shown on the logic diagram.
The oscillator signal peaks at approximately 3.0 V and
provides the timing required for the device.
Ignition
The Ignition input signal enables the device turn-on when
the Ignition pin voltage is greater than 1.4 V. This signal
normally originates from the ignition switch of automotive
systems.
Sense
The Sense pin functions as a voltage sensor. It
proportionally senses the battery voltage and determines the
amount of time the Darlington transistor is high over the next
cycle. A low voltage at the Sense pin will result in a long duty
cycle for the Darlington while a high voltage produces a short
duty cycle. In the application, proportional control is used to
determine the duty cycle. Proportional control is defined as
the sense ratio of battery voltage, present on the Sense pin,
required to obtain a 20% to 95% duty cycle range in the
application. The·20% duty cycle value will correlate to the
maximum battery in the application. Normally the sense ratio
of battery voltage is an end product trim adjustment.
MOTOROLA ANALOG IC DEVICE DATA
Lamp
The Lamp output pin functions as a warning indicator for
overvoltage and stopped engine or broken belt conditions
existing in the system.
Stator
The Stator pin senses the voltage from the stator in the
application circuit, and keeps the device powered up while
the stator voltage is high. Furthermore, it acts as a sense for
a stopped engine or broken belt condition. If this condition is
detected, the Stator turns "on" the Lamp.
Power Supply, VCC
The VCC pin powers the entire device and disables all
outputs during any overvoltage condition.
Roll-Off
The Roll-Ofl pin provides thermal protection for the circuit.
This capability exists, but has not been characterized and is
not tested for at this time. Therefore, it is recommended that
this pin be connected to ground. The surface mount version
has this pin internally connected to ground.
Darlington Drive
The purpose of the Darlington Drive output pin is to turn on
an external power Darlington transistor. The Sense pin
voltage determines the duty cycle of the Darlington. The
oscillator is set to maintain a minimum duty cycle, except
during overvoltage and short circuit conditions.
Short Circuit
The Short Circuit pin monitors the field Voltage. When the
Darlington Drive and Short Circuit pins are simultaneously
high for a duration greater than the slew rate period, a short
circuit condition is noted. The detection time required
prevents the device from reacting to false shorts. As a result
of short circuit detection, the output is disabled. During a short
circuit condition, the device automatically retries with a 2%
duty cycle (Darlington "on" time). Once the short circuit
condition ceases, normal device operation resumes.
Application Notes
A capacitor should be used in parallel with the VCC pin to
filter out noise transients on the supply or battery line.
Likewise, a capacitor should be used in parallel with the
Sense pin to create a dominant closed loop pole. Resistors
connected to inputs, as mentioned in Notes 1 through 5 of the
Electrical Characteristic table, should be used.
10-139
MCCF33095 MC33095'
FLIP-CHIP AP'PLICATION INFORMATION
Introduction
Although the'packaging technology known as "flip-chip"
has been ',available for some time, it has seen few
applications outside the automotive and computer industries.
Present microelectronic trends are demanding smaller chip
sizes, reduced manufacturing costs, and improved reliability.
Flip-chip technology satisfies all of these needs.
Conventional assembly techniques involve bonding wires
to metal pads to make electrical contact to the integrated
circuit. Flip--chip assembly requires further processing of the
integrated circuit after final nitride deposition to establish
robust solder bumps with which to make electrical contact to
the circuit. A spatially identical solderabl,e solder bump
pattern, normally formed on ceramic material, serves as a
substrate host for the flip--chip. The "bumped" flip--chip is
aligned to, and temporarily held in place through the use of
soldering paste. The aligned flip-chip and substrate host are
placed into an oven and the solder reflowed to establish both
electrical and mechanical bonding of the flip--chip to the
substrate circuit. Use of solder paste not only holds the chip
in temporary placement for reflow but also enhances the
reflow process to produce highly reliable bonds.
Flip-Chip Benefits
Some of the benefits of flip-chip assembly are:
1) Higher circuit density resulting in approximately
one-tenth the footprint required of a conventional
plastic encapsulated device.
2) Improved reliability, especially in high temperature
applications. This is due, in part, to the absence
of wires to corrode or fatigue from extensive
thermal cycling.
3) No bond wires are required that might possibly
become damaged during assembly.
4) Adaptable for simultaneous assembly of multiple
flip-chips, in a hybrid fashion, onto a single
'ceramic substrate.
The following discussion covers the flip-chip process
steps performed by Motorola, and the assembly processing
required by the customer, in order to attach the flip-chip onto
a ceramic substrate.
The diagram below depicts the various layers involved in
the bump process.
Figure 9. Plated Bump Structure
and Process Flow
Solder Bump Before Reflow
Plated Copper
Solder Bump After Reflow
Plated Copper
MOTOROLA'S FLIP-CHIP PROCESS
Initially, photoresist techniques are used to create
openings in the nitride passivation layer exposing the metal
pad bias. TiIW, followed by Cu, are sputtered across the
entire wafer surface. The surface is then photo patterned to
define the bump areas. The sputtered metals together
constitute a base metal for the next two metal depositions.
The TiIW layer provides excellent intermetallic adhesion
between the metal pads and the sputtered copper. In
addition, the TilW provides a highly reliable interface to
absorb mechanical shock and vibrations frequently
encountered in automotive applications. The sputtered
copper layer creates a platform onto which an electroplated
copper layer can be built-up. Layers of Cu, Pb, and Sn are
applied by plating onto the void areas of the photoresist
material. The photoresist is then removed and the earlier
sputtered materials are etched away. The flip-chip wafer is
then put into an oven exposing it to a specific ambient
temperature which causes the lead and tin to ball-up and
form a solder alloy.
Overview
The process steps to develop an integrated circuit
flip-chip are identical to that of conventional integrated
circuits up to and including the deposition of the final nitride
passivation layer on the front surface (circuit side). At this
stage all device metal interconnects are present.
The process sequence is as follows:
1) Passivation-nitride photoresist and etch
2) Bimetal sputter (titanium (Ti) and tungsten (W)
followed by copper (Cu»
3) Photo mask to define the bump area
4) Copper plate
5) Lead plate
6) Tin plate
7) Photoresist clean to remove all photoresist material
8) Bimetal etch back
9) Reflow for bump formation
10) Final inspection
IC Solder Bumps
The solder consists of approximately 93% lead and 7% tin.
The alloying of lead with tin provides a bump with good
ductility and joint adhesion properties. Precise amounts of tin
are used in conjunction with lead. Too much tin in relation to
lead can cause the solder joints to become brittle and subject
to fatigue failure. Motorola has established what it believes to
be the optimum material composition necessary in order to
achieve high bump reliability.
In the make-up of the flip-chip design, bumps are ideally
spaced evenly and symmetrically along each edge of the
chip allowing for stress experienced during thermal
expansion and vibration to be distributed evenly from bump
to bump. The bump dimensions and center-to--center
spacing (pitch) are specified by the chip layout and the
specific application. The nominal diameter of the bumps is
6.5 mils and the minimum center-to--center pitch is roughly
8.0 mils.
10-140
MOTOROLA ANALOG IC DEVICE DATA
MCCF33095 MC33095
Reflow
The reflow process creates a thermally induced amalgam
of the lead and tin. In the melting process, the surface tension
is equalized causing the melted solder to uniformly ball up as
mentioned earlier.
The ideal reflow oven profile gradually ramps up in
temperature to an initial plateau. The purpose of the plateau
is to establish a near equilibrium temperature just below that
of the solder's melting temperature. Following the preheat, a
short time and higher temperature excursion is necessary.
This is to ensure adequate melting of the solder materials.
The temperature is then ramped down to room temperature.
An atmosphere of hydrogen is used during the reflow heat
cycle. The hydrogen provides a reducing atmosphere for the
removal of any surface oxides present. The formation or
presence of oxides can cause degradation in the bond
reliability of the product.
During the flip-chip attachment reflow onto the ceramic
substrate host, the created surface tension of the molten
solder aids in the alignment of the chip onto the ceramic
substrate.
substrate from external moisture. A commonly used gel for
this purpose is Dow Corning 562. As a final module assembly
step, a cover is recommended to be placed over the ceramic
assembly for further protection of the circuit.
It should be pOinted out that the commonly used ceramic
substrate material, though more expensive than other
substrate materials, offers significantly superior thermal
properties. By comparison, the use of ceramic material offers
33 times the thermal advantage of the second best material,
Ceracom. The common FR-4 epoxy material is 100 times
less thermally conductive than ceramic. For applications
where dielectric constants are important and/or heat
dissipation is not of real importance, other less costly
materials can be used. The basic concept of the process is
identical for all flip-chip substrates used.
Figure 10. Process Flow Diagram
Reliability
Motorola is determined to bring high quality and reliable
products to its customers. This is being brought about by
increased automation, in-line Statistical Process Control
(SPC), bump shear strength testing, thermocycling from
- 40° to +140°C, process improvements such as backside
laser marking of the silicon chip, and improved copper
plating techniques.
ATTACHING FLIP-CHIPS ONTO
CERAMIC SUBSTRATES
Overview
The assembly or process of attaching the flip-chip onto a
ceramic substrate is performed by the module fabricator.
Prior to actual assembly, the ceramic substrate should
undergo several process steps. Care should be exercised to
properly orient the flip-chip onto the substrate host in order to
accommodate the appropriate solder bumps. Ideally, the
flip-chip should be removed from the waffle pack with a pick
and place machine utilizing a vacuum pick-up to move the
die onto the ceramic substrate. Any other components to be
reflow soldered onto the substrate can be placed onto the
substrate in a similar manner. Flip-chip assembly onto a
ceramic substrate allows for some passive components,
such as resistors, to be formed directly into the ceramic
substrate circuit pattern itself. With all surface components to
be mounted in place on the ceramic substrate, the assembly
is moved into the furnace where it undergoes a specified
temperature variation to solder all the components onto the
ceramic substrate. This is accomplished by melting
(reflowing) the substrate solder bumps. The resulting
assembly should, after being cooled, be cleaned to remove
any flux residues. If the substrate assembly is to be mounted
into a module, it is recommended that the cavity of the
module be filled with an appropriate silicon gel. The use of a
gel coating helps to seal the individual components on the
MOTOROLA ANALOG IC DEVICE DATA
Ceramic Substrate Preparation
The recommended ceramic substrate is aluminum oxide.
These substrates come connected in what is referred to as a
card. This is identical to the concept of die or chips on a wafer.
Each card usually contains 8 to 16 substrates.
Initially, the ceramic should be precleaned with isopropyl
alcohol, followed by freon. The bump pattern is then
transferred onto the substrate using a metal stencil technique
using a palladium silver conducting paste, such as DuPont
9476, through a #325 mesh. Once the pattern is applied, the
substrate is dried for ten minutes at 150°C and then fired for
60 minutes at a temperature increasing to a peak of 850°C for
ten additional minutes. Solder paste is then stenciled onto
the pads.
A metal etched stencil defining the contact areas is
recommended. The use of an etched stencil affords better
solder paste control than does a silk screen. The metal stencil
affords a deposition of a known amount of solder paste,
thereby preventing bridging caused by excess solder usage.
10-141
1m
•
MCCF33095 MC33095
Solder Paste Content
It is recommended that the solder paste consist of 10% tin,
88% lead, and 2% silver alloy. However, 95/3/2 compositions
have had successful results.
A rosin based flux, such a,s RMA (Rosin Mildly Activated)
manufactured by Dupont and having,spherical particles of 45
to 75 microns, should be,used. Th.e tackiness of the solder
paste at room temperature helps to hold the flip-chip in place
during. the pick and place operation. The use of flux:
1) Prevents excess oxidation during reflow.
2) Optimizes the flow of liquid solder through the stencil.
3) Smooths the surface by reducing surface tension, and
4) Enhances the normalization of surface tension upon
reflow causing the flip-chip bumps to effectively
auto-align themselves to substrate bump pads.
A solder mask can be used for applications requiring high
precision as shown in Figures 11a and 11b.
Figure 11a. Before Reflow
IC
Flip-Chip Bump
~~~~~Ss..'S:r- Solder Mask
Ceramic
Figure 11b. After Reflow
IC
Flip-Chip Bump
Pb/Sn
Reflow
~;S:~~~!i:"S~~- Solder Mask
Ceramic
Oven Profile
After the flip-chip is placed onto the bumped substrate, the
substrate and flip-chip are ready for reflow. Initially, the
flip-chip is heated to a peak temperature of around 300° to
350°C for five minutes. It is to be noted that the flip-chip
bumps have a higher melting temperature than the bumps on
the substrate. During assembly reflow, the substrate bumps
melt and create a substrate to flip-chip bump bond. After
reflow, the assembled part is cooled to room temperature or
10-142
to some intermediate temperature point for annealing
purposes.
Figure 12. Reflow Oven Profile
p-
350
UJ
a:
::>
!;(
.a:
UJ
"::;:
W
I-
~
'----'---'----'---':-----
The oven temperature profile is established primarily to
melt the solder while minimizing the alloying of the materials
and keeping the flux from boiling away. It should be noted that
when the flip-chip is placed onto the substrate, the material is
stressed in one direction or another. The use of flux helps to
reduce any surface stresses present. A reduction in the
surface stress enhances solder wetting which in turn aids in
the alignment of the flip-chip to the substrate. Poor solder
wetting will produce misalignment as well as inferior bond
strengths and reliability.
It is recommended that an inert atmosphere such as
nitrogen be used during the reflow process to prevent
oxidation.
Final Cleaning
The final cleaning involves removing the remaining flux
from the flip-chip assembly. Three possible methods of
removing flux are: ultrasonic cleaner, Terpene solvent and DI
water, or vapor degreaser. The flux manufacturer should be
able to recommend the proper type of vapor degreaser to be
used.
Test and Reliability
Both visual inspection and shear strength testing should
be performed on packaged flip-chip assemblies.
Solder reflow results that exhibit a grainy and dull
appearance produce inferior bond shear strengths. Inferior
bond shear strengths are visually recognizable by:
1) The presence of old or badly oxidized solder paste.
2) Insufficient amount of solderable material.
3) The contamination of bond pads with grease, oil, etc.
It should be mentioned that many contaminants are
transparent and not easily detectable by visual means.
MOTOROLA ANALOG IC DEVICE DATA
MCCF33095 MC33095
Shear strength testing should meet a 0.8 Newtons/Bump
criteria. Shear strength testing should follow thermocycling of
the chip from - 40° to +140°C to insure the stability of shear
strength over temperature. Figure 13 depicts a test set-up
which might possibly be used.
Figure 13. Shear Test Fixture
Aside from physical contamination, flip-chips, like any
other chips, should not be handled directly due to the fact that
electrostatic discharges can cause permanent damage to the
electronic circuit. Flip-chips which do survive an electrostatic
discharge can be left in a weakened condition resulting in
reduced reliability of the end product. To avoid electrostatic
damage of the circuit, assembly personnel should make use
of a wrist strap or some other device to provide electrostatic
grounding of their body. For the same reason, machinery
used to assemble semiconductor circuits should be
electrostaticly grounded.
Flip-chips rely primarily on the thermal path established by
the bumps to remove heat from the chip as a result of internal
circuit operation. Standard Motorola flip-chips have a thermal
resistance of approximately 290°CIW/Bump. This figure can
be used to estimate the allowed maximum power dissipation
of the chip.
Cost and Equipment Manufacturers
The cost of implementing a flip-chip assembly process
depends on the specific production requirements and as a
result will vary over a broad range. It is possible to implement
a small volume laboratory set-up for a few hundred dollars
using manual operations. At the other end of the scale one
could spend millions setting up a fully automated line
incorporating pattern recognization, chip and substrate
MOTOROLA ANALOG IC DEVICE DATA
orientation, reflow, cleaning, and test. The module fabricator
will have to make this assessment.
An assembly operator can manually accomplish the pick
and place operation using a vacuum probe to pick-up and
orient the flip-chip onto the substrate. Furthermore, it is
possible to perform the reflow assembly operation using a
simple batch process oven fabricated from a laboratory hot
plate. However, the use of such process techniques will have
questionable impact on the final product's reliability and
quality. For this reason, it is highly recommended that the
module fabricator seriously consider two major pieces of
eqUipment; a pick and place machine and an infrared solder
reflow oven. Both pieces of eqUipment can vary over a wide
cost range depending on the production requirements. A
partial list of manufacturers for this equipment is given below.
Pick and Place Machine:
Universal Instruments Corp.
Dover Technologies, Inc.
Binghamton, NY 13902
(607) 772-7522
Seiko
Torrance, CA 90505
(310) 517-7850
Laurier Inc.
Hudson, NH 03051
(603) 889-8800
Infrared Reflow Oven:
BTU
Bellerica, MA 01862
(508) 667-4111
Vitronics
Newmarket, NH 03857
(603) 659--6550
Additional Applications
Completed ceramic flip-chip sub-assemblies can be
stacked one on top of another to produce an overall
assembly by making contact connections through bumps.
This technology is beginning to emerge in the computer
industry where physical module size is of significant
importance. Furthermore, this assembly technology, though
more complex, is undergoing serious consideration within the
automotive industry as well.
Applications requiring small size and high reliability at high
ambient temperatures can benefit considerably through the
implementation of flip-chip assembly techniques.
10-143
®
MOTOROLA
TCF6000
Peripheral Clamping Array
The TCF6000 was designed to protect input/output lines of
microprocessor systems against voltage transients.
PERIPHERAL CLAMPING
ARRAY
• Optimized for HMOS System
• Minimal Component Count
SEMICONDUCTOR
TECHNICAL DATA
• Low Board Space Requirement
• No P.C.B. Track Crossovers Required
• Applications Areas Include Automotive, Industrial,
Telecommunications and Consumer Goods
o SUFFIX
PLASTIC PACKAGE
CASE 751
(SO-8)
NO SUFFIX
PLASTIC PACKAGE
CASE 626
PIN CONNECTIONS
Figure 1. Representative Block Diagram and
Simplified Application
Gnd
VCC
Clamp
Clamp
Clamp
Clamp
Clamp
Each Cell
Digital
Inputs
{~VV'v--l-+-------t+*-j
Micro
Computer
Analog
Inputs
{~vv\~-+"""_---t--;
ORDERING INFORMATION
Device
TCF6000D
Gnd
10-144
TCF6000
Operating
Temperature Range
TA = - 40° 10 +85°C
Package
S0-8
PlaslicDIP
MOTOROLA ANALOG IC DEVICE DATA
TCF6000
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted, Note 1.)
Rating
Symbol
Value
Unit
VCC
6.0
V
Supply Voltage
Supply Current
Ii
300
mA
Clamping Current
11K
±50
mA
Junction Temperature
TJ
150
'c
Power Dissipation (TA = + 85'C)
Po
400
mfW
Thermal Resistance (Junction-Ambient)
8JA
100
°CfW
Operating Ambient Temperature Range
TA
-40 to +85
Tstg
-55 to + 150
'c
'c
Storage Temperature Range
NOTE: I. Values beyond which damage may occur.
ELECTRICAL CHARACTERISTICS (TA = 25°C, 4.5 '" VCC '" 5.5 V, unless otherwise noted.)
Symbol
Min
Max
Unit
Positive Clamping Voltage (Note 2)
(11K = 10 rnA, -40°C '" TA '" + 85°C)
V(IK)
-
VCC+ 1.0
V
Characteristics
Positive Peak Clamping Current
IIK(P)
-
20
rnA
Negative Peak Clamping VoHage
(11K =-10 mA, -40°C '" TA '" + 85'C)
V(IK)
-0.3
-
V
Negative Peak Clamping Current
IIK(P)
-20
-
rnA
IL
ILT
-
-
1.0
5.0
AcT
100
-
dB
IB
-
2.0
rnA
Output Leakage Current
(OV ",Vin ",VCC)
(0 V '" Yin '" VCC, -40°C '" TA '" + 85'C)
Channel Crosstalk (AcT = 20 log 1t!IIK)
Quiescent Current (Package)
IlA
NOTE: 2. The device might not give 100% protection in CMOS applications.
CIRCUIT DESCRIPTION
To ensure the reliable operation of any integrated circuit
based electronics system, care has been taken that voltage
transients do not reach the device I/O pins. Most NMOS,
HMOS and Bipolar integrated circuits are particularly
sensitive to negative voltage peaks which can provoke
latch-up or otherwise disturb the normal functioning of the
circuit, and in extreme cases may destroy the device.
Generally the maximum rating for a negative voltage
transients on integral circuits is -0.3 V over the whole
temperature range. Classical protection units have consisted
of diode/resistor networks as shown in Figures 2a and 2b.
The arrangement in Figure 2a does not, in general, meet
the specification and is therefore inadequate.
The problem with the solution shown if Figure 2b lies
mainly with the high current drain through the biassing
devices Rl and 03. A second problem exists if the input line
carries an analog signal. When Vin is close to the ground
potential, currents arising from leakage and mismatch
between 03 and 02 can be sourced into the input line, thus
disturbing the reading.
MOTOROLA ANALOG IC DEVICE DATA
Figure 2. Classical Protection Circuits
(a)
(b)
vcc
Vee
RI
Vin
~
IiC
Rin
~n ~
01
Vin Rin
01
i
C·In!
-'-
02
I
I
1
Gnd
IiC
C=>
02
~
03
Gnd
Figure 3 shows the clamping characteristics which
are common to each of the six cells in the Peripheral
Clamping Array.
As with the classical protection circuits, positive voltage
tranSients are clamped by means of a fast diode to the V CC
supply line.
10-145
TCF6000
Figure 3. Clamping Characteristics
APPLICATIONS INFORMATION
Figure 4 depicts a typical application in a microcomputer
based automotive ignition system.
The TCF6000 is being used not only to protect the
system's normal inputs but also the (bidirectional) serial
diagnostics port.
The value of the input resistors, Rin, is determined by the
clamping current and the anticipated value of the spikes.
11K
+10mA
Thus:
Vcc
V
11K
Rin= -
Vcc+
0.75VTyp
n
where:
V = Peak Volts (V)
11K = Clamping current (A)
So, taking, V = 300 V typically (SAE J1211)
11K = 10 mA (recommended)
gives,
Rin= 30 k
--It---t- -10 rnA
Low
Impedance
Hi h
Low
Impedance
Impedance
Resistors of this value will not usually cause any problems
in MOS systems, but their presence needs to be taken into
account by the designer. Their effect will normally need to be
compensated for Bipolar systems.
Figure 4. Typical Automotive Application
Vcc
=
Gnd
<=>
<=>
<=>
:f
Ie
~
Gnd
Vbat
VCC
RHall
INT1
MC6805S2
:f
DO
B1
D2
B2
'J'
Gnd
6X
Rin
:f
VSS
3X
Cin
Gnd
~
Gnd
..
Coil Drive
Coil Feedback
D1
Vbat
10-146
BO
Car
Serial Diagnostics
Ignition Module
.
MOTOROLA ANALOG IC DEVICE DATA
TCF6000
The use of Cin is not mandatory, and is not recommended
where the lines to be protected are used for output or for both
input and output. For digital input lines, the use of a small
capacitor in the range of 50 pF to 220 pF is recommended as
this will reduce the rate of rise of voltage seen by the
TCF6000 and hence the possibility of overshoot.
In the case of the analog inputs, such as that from the
pressure sensor, the capacitor Cin is necessary for devices
such as the MC6805S2 shown, which present a low
impedance during the sampling period. The maximum value
for Cin is determined by the accuracy required, the time taken
to sample the input and the input impedance during that time,
while the maximum value is determined by the required
frequency response and the value of Rin.
Thus for a resistive input AID connector where:
Ts = Sample time (seconds)
RO= Device input resistance (0)
Vin= Input voltage (V)
k = Required accuracy (%)
01 = Charge on capacitor before sampling
02 = Charge on capacitor after sampling
10 = Device input current (A)
Thus:
but,
and,
01=Cin Yin
01-02= 10 - Ts
so that,
lOTs =
10-Ts
and,
Cin (min) = - Vk. Farad
so,
.
100-Ts
Cin (min) = k _ RD Farad
m-
The calculation for a sample and hold type converter is
even simpler:
k = Required accuracy (%)
CH= Hold capacitor (Farad)
100- CH
Cin (min) = - - k - - Farad
For the MC6805S2 this comes out at:
Cin (min) =
MOTOROLA ANALOG IC DEVICE DATA
k- Cin-Vin
100
100.25 pF
0.25
= 10 nF for 1/4% accuracy
10-147
®
MOTOROLA
'UAA1041B
Automotive Direction
Indicator
This device was designed for use in conjunction with a relay in automotive
applications. It is also applicable for other warning lamps such as "handbrake
ON," etc.
AUTOMOTIVE DIRECTION
INDICATOR
• Defective Lilmp Detection
SEMICONDUCTOR
TECHNICAL DATA
• Overvoltage Protection
• Short Circuit Detection and Relay Shutdown to Prevent Risk of Fire
• Reverse Battery Connection Protection
• Integrated Suppression Clamp Diode
.~
1
NO SUFFIX
PLASTIC PACKAGE
CASE 626
Figure 1. Typical Automotive System
o SUFFIX
PLASTIC PACKAGE
CASE 751
C2
-Vcc
RS
UAA1041
Cl
+
+V
T
7r---+-" . l
(S0-8)
-v
3
PIN CONNECTIONS
R2
Rl
R3
1Relay 1--------
-vccOastart
+Vbat 2
7 Fault Det
RLY Out 3
Oscillator
4
6
FauH Det On/Off
5
Oscillator
(Top View)
L2
L3
L4
L5
ORDERING INFORMATION
L1: 1.2 W, waming light handbrake ON
L2, L3, L4, L5: 21 W, turn signals
Rl =75 k
R2=3.3k
R3=220n
RS=30mn
Cl =5.6IlF
C2 = 0.047 IlF
Oevice
UAA1041BD
UAA1041B
10-148
Operating
Temperature Range
Package
S0-8
TA = - 40° to +100°C I-P-Ia-s-tic-O-I-P--i
MOTOROLA ANALOG IC DEVICE DATA
UAA1041B
MAXIMUM RATINGS
Rating
Current: Continuous/Pulse"
Pin
Value
Unit
1
+150/+500
--35/-500
±350/1900
±300/1400
±25/50
mA
TJ
150
°c
°c
2
3
8
Junction Temperature
Operating Ambient Temperature Range
TA
-40 to + 100
Storage Temperature Range
Tstg
--{j5to+150
°c
Thermal Resistance, Junction-to-Ambient
RSJA
100
°CIW (Typ)
" One pulse with an exponential decay and with a time constant of 500 ms.
ELECTRICAL CHARACTERISTICS (T 1 = 25°C)
Characteristics
Battery Voltage Range (normal operation)
Symbol
Min
Typ
Max
Unit
VB
8.0
-
18
V
Overvoltage Detector Threshold
(VPinlOVPinl )
Dth(OV)
19
20.2
21.5
V
Clamping Voltage
(VPin2-VPinl )
VIK
29
31.5
34
V
Short Circuit Detector Threshold
(VPinlOVPin7)
Dth(SC)
0.63
0.7
0.77
V
Output Voltage (Jrelay = -250 mAl
(VPin2-VPin3)
Vo
-
-
1.5
V
Starter Resistance Rst = R2 + RLamp
Rst
-
-
3.6
knt
Oscillator Constant (normal operation)
Kn
1.4
1.5
1.6
-
Temperature Coefficient of Kn
Kn
-
-1.5xl0-3
-
l/oC
%
-
45
50
55
KF
0.63
0.68
0.73
-
-
35
40
45
%
Oscillator Constant
Kl
K2
K3
0.167
0.25
0.126
0.18
0.27
0.13
0.193
0.29
0.14
-
Current Consumption (relay off)
Pin 1; at VPin2 - VPinl = 8.0 V
= 13.5V
= 18V
ICC
-
-1.0
-
--0.9
-1.6
-2.2
Current Consumption (relay on)
Pin 1; at VPin2 - VPinl = 8.0 V
= 13.5 V
= 18 V
-
-
--3.8
-5.6
--{j.9
-
-
68
85.3
100
91
Duty Cycle (normal operation)
Oscillator Constant - (1 lamp defect of 21 W)
Duty Cycle (1 lamp defect of 21 W)
Defect Lamp Detector Threshold at VPin2 to VB = 8.0 V
and R3=220n
=13.5V
=18V
mA
-2.5
VPinlOVPin7
VPinlOVPin7
VPinlOVPin7
mA
79
-
-
mV
-
t See Note 1 of Application Information
MOTOROLA ANALOG IC DEVICE DATA
10--149
UAA1041B
CIRCUIT DESCRIPTION
The circuit is designed to drive the direction indicator
flasher relay. Figure 2 shows the typical system configuration
with the extemal components. It consists of a network (R1,
C1) to determine the oscillator frequency, shunt resistor (RS)
to detect defective bulbs and short circuits in the system, and
two current limiting resistors (R2fR3) to protect the IC against
load dump transients. The circuit can be used either with or
without short circuit detection, and features overvoltage,
defective lamp and short circuit detection.
The lightbulbs L2, L3, L4, L5 are the tum signal indicators
with the dashboard-light L6. When switch S1 is closed, after
a time delay of t1 (in our example t1 = 75 ms), the relay will be
actuated. The corresponding lightbulbs (L2, L3 or L4, L5) will
flash at the oscillator frequency, independent of the battery
voltage of 8.0 V to 18 V. The flashing cycle stops and the
circuit is reset to the initial position when switch S1 is open.
Pin 6 has to be connected to Pin 2, and the use of capacitor
C2 is not necessary. The circuit can also be used for other
waming flashers. In this example, when the handbrake is
engaged, it is signaled by the light (L 1).
Figure 2. Typical System Configuration
C2
JU-1
-Vcc
2
7~1--r~
UAA1041B
3
C1
6
4
R2
R1
R3
Overvoltage Detection
Relay
Senses the battery voltage. When this voltage exceeds
20.2 V (this is the case when two batteries are connected in
series), the relay will be tumed off to protect the lightbulbs.
Lightbulb Defect Detector
Senses the current through the shunt resistor RS. When one
of the lightbulbs is defective, the failure is indicated by
doubling the flashing frequency.
L2
Short Circuit Detector
Detects excessive current (Ish > 25 A) flowing in the shunt
resistor RS. The detection takes place after a time delay of t3
(t3 55 ms). In this case, the relay will be tumed off. The
circuit is reset by switching S1 to the off position.
=
Operation with Short Circuit Detection
Pin 6 has to be left open and a capacitor C2 has to be
connected between Pin 1 and Pin 2.
L3
L4
L5
PARTS LIST
R1 = 75 kO
Relay-Coil Resistance
R2 = 3.3 kO
Range 60 0 to 800 0
R3=2200
Note: Per text connect
RS=30mO
jumper JU-1 bypass
Wire Resistor
short circuit detector
C1 =5.6J.lF
C2 may be deleted also.
C2=0.047J.lF
Operation without Short Circuit Detection
APPLICATION INFORMATION
1. The flashing cycle is started by closing S1. The switch
position issensed across resistorR2and RLamp by Input 8.
Rst = R2 + RLamp.
The condition for the start is: Rst < 3.6 kn.
For correct operation, leakage resistance from Pin 8 to
ground must be greater than 5.6 kn.
2.
Flashing frequency: fn ___1_
- R1 C1Kn
3. Flashing frequency in the case of one defective lightbulb
of 21 W:
fF
10-150
1
= R1 C1 KF
Kn
=2,2KF
4. t1: delay at the moment when S1 is closed and first flash
=
t1 K1R1C
5. t2: defective lightbulb detection delay t2 K2R1 C1
6. t3: short circuit detection delay t3 K1 R1C1
In the case of short circuit - it is assumed thatthe voltage
(VPin2-VPin1):<:8.0V.Therelaywilibetumedoffafterdelay
t3. The circuit is reset by switching S1 to the off position.
The capacitor C2 is not obligatory when the short circuit
7. detector is not used. In this case Pin 6 has to be connected
to Pin 2.
When overvoltage is sensed (VPin2 - VPin1) the relay is
8. tumed off to protect the relay and the lightbulbs against
excessive currents.
=
=
MOTOROLA ANALOG IC DEVICE DATA
Other Analog Circuits
In Brief ...
Other analog circuits are provided for special applications
with both bipolar and CMOS technologies. These circuits
range from the industry standard analog timing circuits and
multipliers to specialized CMOS smoke detectors. These
products provide key functions in a wide range of
applications, including data transmission, commercial
smoke detectors, and various industrial controls.
Page
Timing Circuits ..................................
Singles ......................................
Duals .......................................
Multipliers ............... , ......................
Linear Four-Quadrant Multipliers ................
Smoke Detectors (CMOS) ........................
Package Overview ..............................
Device Listing ...................................
11-2
11-2
11-2
11-2
11-2
11-3
11-4
11-5
III
MOTOROLA ANALOG Ie DEVICE DATA
11-1
Timing Circuits
Multipliers
These highly stable timers are capable of producing
accurate time delays or oscillation. In the time delay mode of
operation, the time is precisely controlled by one external
resistor and capacitor. For a stable operation as an oscillator,
the free-running frequency and the duty cycle are both
accurately controlled with two external resistors and one
capacitor. The output structure can source or sink up to 200 rnA
or drive TIL circuits. liming intervals from microseconds
through hours can be obtained. Additional terminals are
provided for triggering or resetting if desired.
Linear Four-Quadrant Multipliers
Multipliers are designed for use where the output voltage is
a linear product of two input voltages. Typical applications
include: multiply, divide, square, root-mean-square, phase
detector, frequency doubler, balanced modulator/demodulator,
electronic gain control.
Multiplier Transfer Characteristics
Singles
MC1455P1, D
TA 0° to +70°C, Case 626, 751
=
MC1455BP1, D
TA = -40° to +85°C, Case 626, 751
Vee
----------...,I
Flip
Flop
7
Q
I
13
L--l':>-b Output
I
Trigger
_ _ _ _ .JI
1
Gnd
-6.0 -4.0 -2.0 0
2.0 4.0
VX, INPUT VOLTAGE (V)
Discharge
10
MC1494P
TA
= 0° to +70°C, Case 648
This device has all the necessary internal regulation and
references. The Single-ended output is referenced to ground.
4
Reset
MC1495D, P
Duals
TA
MC3456P
TA 0° to +70°C, Case 646
Maximum versatility is assured by allowing the user to
select the level shift method.
=
NE556N, D
TA = 0° to +70°C, Case 646, 751A
MC1495BP
TA
III
= 0° to +70°C, Case 751A, 646
=-400 to +125°C, Case 646
Linearity and offset are actually tested over temperature.
This is an improved specification over previous versions.
11-2
MOTOROLA ANALOG IC DEVICE DATA
Smoke Detectors (CMOS) .
These smoke detector les require a minimum number of
external components. When smoke is sensed, or a low battery
voltage is detected, an alarm is sounded via an extemal
piezoelectric transducer. All devices are designed to comply
with UL specifications.
Table 1. Smoke Detectors (CMOS)
Low
Battery
Detector
Piezoelectric
Horn Driver
I/'
I/'
Device
Number
Suffix!
Package
MC14467-1
P1/646
MC1457B
P/648
I/'
I/'
I/'
I/'
-
I/'
I/'
MC14470
I/'
I/'
I/'
MC145010
(1)
I/'
I/'
MC145011
Recommended
Power Source
Unique
Feature
Ionization-Type
Smoke Detector
Battery
High Input Impedance
FET Comparator
-
-
Ionization-Type
Smoke Detector
with Interconnect
Battery
I/'
Line
Photoelectric-Type
Smoke Detector
with Interconnect
Battery
Function
Line
Photo Amplifier
Line
Complies
with
UL217
and UL268
MC14468
P/648,
DW1751G
(1) Low-supply detector.
MOTOROLA ANALOG IC DEVICE DATA
11-3
Other Analog Circuits Package Overview
CASE 626
P1 SUFFIX
CASE 646
N, P, P1 SUFFIX
CASE 751
DSUFFIX
CASE 751A
DSUFFIX
CASE 648
PSUFFIX
•
CASE 751G
DWSUFFIX
II
11-4
MOTOROLA ANALOG IC DEVICE DATA
· Device Listing
Timing Circuits
Page
Device
Function
MC1455, B
MC3456
liming Circuit ................................................................ 11-6
Dual liming Circuit .......................................................... 11-43
Multipliers
Page
Device
Function
MC1494
MC1495
MC1496
Linear Four-Quadrant Multiplier ............................................... 11-14
Wideband Linear Four-Quadrant Multiplier ..................................... 11-28
Balanced Modulator/Demodulator Four-Quadrant Multiplier .............. (See Chapter 8)
II
MOTOROLA ANALOG IC DEVICE DATA
11-5
®
MOTOROLA
MC1455, B
Timing Circuit
The MC1455 monolithic timing circuit is a highly stable controller capable
of producing accurate time delays or oscillation. Additional terminals are
provided for triggering or resetting if desired. In the time delay mode, time is
precisely controlled by one external resistor and capacitor. For astable
operation as an oscillator, the free-running frequency and the duty cycle are
both accurately controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms, and the output
structure can source or sink up to 200 mA or drive MTTL circuits.
TIMING CIRCUIT
SEMICONDUCTOR
TECHNICAL DATA
• Direct Replacement for NE555 Timers
• . Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Current Output Can Source or Sink 200 mA
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
• Output Can Drive MTTL
• Temperature Stability of 0.005% per °C
• Normally ON or Normally OFF Output
o SUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)
Figure 1. 22 Second Solid State Time Delay Relay Circuit
ORDERING INFORMATION
Device
MC1455P1
10k
MC1455D
MC1455BD
MC1455BP1
III
t=I.I; Rande=22sec
lime delay (t) is variable by
changing Rand e (see Figure 16).
lN4740
Operating
Temperature Range
TA = 0° to +70°C
TA = - 40° to +85°C
Package
Plastic DIP
S0-8
S0-8
Plastic DIP
Figure 3. General Test Circuit
Figure 2. Representative Block Diagram
vee
B
-----------,
I
7
,..,--..,--- Discharge
Threshold --<:l--f--l
Control Voltage
--<:l-+-l
output
I
_ _ _ _ _ .1I
Trigger -<:I--+~
L
4
Gnd
11-6
Reset
Test circun for measuring DC parameters (to set output and
measure parameters):
a) When Vs '" 213 Vee, Vo is low.
b) When Vs s 1/3 Vee, Vo is high.
c) When Vo is low, Pin 7 sinks current. To test for Reset, set Vo
high, apply Reset voltage, and test for current flowing into Pin 7.
When Reset is not in use, it should be tied to Vee.
MOTOROLA ANALOG IC DEVICE DATA
MC1455, B
MAXIMUM RATINGS (TA: +25°e, unless otherwise noted.)
Rating
Power Supply Voltage
Discharge Current (Pin 7)
Power Dissipation (Package Limitation)
PI Suffix, Plastic Package
Derate above TA: +25°e
D Suffix, Plastic Package
Derate above TA: +25°e
Operating Temperature Range (Ambient)
Me1455B
Me1455
Storage Temperature Range
Symbol
Value
Unit
Vee
+18
Vdc
17
200
rnA
PD
625
5.0
625
160
mW
mW/oe
mW
PD
°elW
°e
TA
-40 to +85
Oto+70
Tstg
-65 to +150
°e
ELECTRICAL CHARACTERISTICS (TA: +25°e, Vee: +5.0 V to +15 V, unless otherwise noted.)
Symbol
Min
TYP
Max
Operating Supply Voltage Range
Vee
4.5
-
16
Supply Current
Vee: 5.0 V, RL: 00
Vee: 15 V, RL: 00, Low State (Note 1)
ICC
Characteristics
Timing Error (R = 1.0 kil to 100 kO) (Note 2)
Initial Accuracy e: 0.1 I1F
Drift with Temperature
Drift with Supply Voltage
Threshold Voltage/Supply Voltage
Trigger Voltage
Vee: 15V
Vee: 5.OV
VthNee
Unit
V
mA
-
3.0
10
-
1.0
50
0.1
-
213
-
5.0
1.67
VT
6.0
15
-
-
%
PPM/oC
%N
V
-
Trigger Current
IT
-
0.5
-
Reset Voltage
VR
0.4
0.7
1.0
V
Reset Current
IR
-
0.1
-
rnA
Ith
-
0.1
0.25
l1A
Idischg
-
-
100
nA
9.0
2.6
10
3.33
11
4.0
-
0.1
0.4
2.0
2.5
0.25
0.75
2.5
-
-
0.25
0.35
12.75
2.75
12.5
13.3
3.3
-
Threshold Current (Note 3)
Discharge Leakage Current (Pin 7)
Control Voltage Level
Vee: 15V
Vee: 5.OV
VeL
Output Voltage Low
ISink: 10 rnA (Vee: 15 V)
ISink: 50 rnA (Vee: 15 V)
ISink: 100 rnA (Vee: 15 V)
ISink: 200 rnA (Vee: 15 V)
ISink: 8.0 rnA (Vee: 5.0 V)
ISink: 5.0 rnA (Vee: 5.0 V)
VOL
Output Voltage High
Vee: 15 V (lSource = 200 rnA)
Vee: 15 V (lSource: 100 rnA)
Vee: 5.0 V (ISource: 100 rnA)
VOH
l1A
V
V
-
-
V
-
Rise Time Differential Output
tr
-
100
Fall Time Differential Output
If
-
100
-
ns
ns
NOTES: 1. Supply current when output is high is typically 1.0 rnA less.
2. Tested at Vee: 5.0 V and Vee: 15 V Monostable mode.
3. This will determine the maximum value 01 AA + AS lor 15 V operation. The maximum total A = 20 mO.
MOTOROLA ANALOG IC DEVICE DATA
11-7
ID
MC1455, B
Figure 4. trigger Pulse Width
Figure 5. Supply Current
150
10
'2 125
l
'E
~ 100
----
:J:
b
~
w
~
~
a.
~
75
50
o
o
0.1
(.)
::;
0.3
~
2.0
I
10.- I-""
-
o
5.0
10
15
10
:If
w
!:i
25°C
1.0
/
S
1.0
~
15
0.6
?
J J-'
2.0
5.0
10
50
20
~
.....
.-
..:.
5.0VSVee S15V
-
0.1
...J
0.2
-
~
C)
§2
1.2
0.4
.L
0.01
100
1.0
2.0
5.0
10
20
50
ISource (mA)
ISink(mA)
Figure 8. Low Output Voltage
@ VCC = 10Vdc
Figure 9. Low Output Voltage
@ VCC= 15 Vdc
10
100
10
~
!:i0
w
C)
C)
25°eC
1.0
'/
I-
~
1=
~
0
~
5
>
/
Figure 7. Low Output Voltage
@ VCC = 5.0 Vdc
25°C
1.0
, / 'V
Figure 6. High Output Voltage
(.)
.j? 0.8
~
w
!:i
§2
./
~
V".
Vee, SUPPLY VOLTAGE (Vdc)
1.6
1.4
o
. /~
VT (min), MINIMUM TRIGGER VOLTAGE (x Vee = Vdc)
1.8
III
4.0
0.4
2.0
~:J:
f
a.
a.
~
en
i--
70°C
0.2
6.0
~
ooe
~-
~
8.0
w
-:::::: r--
~ t-"
25
~
a:
a:
25~V
0.1
-
~
......
~
...--
>
J
1.0
./
S
a.
S
0
.....
~..:.
......
25°C
0.1
~
~
?
0.01
0.Q1
1.0
2.0
5.0
10
ISink(mA)
11-8
20
50
100
1.0
2.0
5.0
10
20
50
100
ISink(mA)
MOTOROLA ANALOG IC DEVICE DATA
MC1455, B
Figure 10. Delay Time versus Supply Voltage
Figure 11. Delay Time versus Temperature
1.015
c
~
1.015
c
1.010
1\
Cf 1.005
oz
~
\
1.000
~
~
.~
~
--
-
Cf 1.005
~-~
w
::;;
1.000
~
0.995
-
~
0.995
w
~
;SI 0.990
0.985
1.010
c
;SI 0.990
o
5.0
10
15
0.985
-75
20
-so
Vee. SUPPLY VOLTAGE (Vdc)
-25
0
25
50
75
100
125
TA. AMBIENT TEMPERATURE ('C)
Figure 12. Propagation Delay
versus Trigger Voltage
300
~
w
::;;
2SO
~
~
w
200
0
z
150
-o'e
~
100
a..
so
-;;;;
c
~
~
j.
o
o
MOTOROLA ANALOG IC DEVICE DATA
...i""~
.,~
v
~
-:::::
, 25'e
~
I
0.1
0.2
0.3
VT (min). MINIMUM TRIGGER VOLTAGE (x Vee = Vdc)
0.4
11-9
MC1455, B
Figure 13. Representative Circuit Schematic
Control Voltage
,------1,---1
I
Flip-flop
II
Output
Vee
Threshold
7.0k
I
I
I
I
I
I
I
I
I
I
I
Output
Trigger 0------+--1---1
Reset
4.7k
Discharge
100
GENERAL OPERATION
II
The MC1455 is a monolithic timing circuit which uses an
external resistor - capacitor network as its timing element. It
can be used in both the monostable (one-shot) and astable
modes with frequency and duty cycle controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input
signal and the other for capacitor voltage; also a flip-flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit in Figure 14). When the input
voltage to the trigger comparator falls below 1/3 VCC, the
comparator output triggers the flip-flop so that its output sets
low. This turns the capacitor discharge transistor "off" and
drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which is
set by the RC time constant. When the capacitor voltage
reaches 213 VCC, the threshold comparator resets the
flip-flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip-flop
has been triggered by an input signal, it cannot be retriggered
11-10
until the present timing period has been completed. The time
that the output is high is given by the equation t 1.1 RA C.
Various combinations of Rand C and their associated times
are shown in Figure 16. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor, thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned "on" and prevents
the capaCitor from charging. While the reset voltage is
applied the digital output will remain the same. The reset pin
should be tied to the supply voltage when not in use.
=
Figure 14. Monostable Circuit
+Vee (5.0 V to 15 V)
Reset
Vee
,--'-'--_--1...::8--, Discharge
Output
7
3
~ RL
2
Trigger
MOTOROLA ANALOG IC DEVICE DATA
MC1455, B
Figure 15. Monostable Waveforms
Figure 16. Time Delay
100
10
/
Ii:'
::1.
~
C---"V
0.1
C3
c.5 0.01
/
/
/
/
,,~ ~~J
V
/
:/
./
/
./
./
~q,,,L ~q,./
./
1/
./
./
l/ '/ 1/ 1/
0.001 ./
10 JJ.S 100 JJ.S 1.0 ms
t = 50 Ils/cm
(AA =to kil, C =O.OlIlF, RL =1.0 kil, Vcc =15 V)
/
,,0/
,,~/
/
/
/
/
L
q,,L' ~
-
(3
i't.
/
/
/
~
/
1/
1.0
;:!:
/
1/
/
./
10 ms
100 ms
1.0
10
100
ld, TIME DELAY (s)
Figure 17. Astable Circuit
Figure 18. Astable Waveforms
+Vcc (5.0 V to 15 V)
~
AA
Vcc
B
AL
Output
7 Discharge
3
RS
~ RL
C
t = 20 Ils/cm
(RA =5.1 kil, C =O.OlIlF, RL =1.0 kil; AS =3.9 kil, Vcc =15 V)
-
Astable Mode
In the astable mode the timer is connected so that it will
retrigger itself and cause the capacitor voltage to oscillate
between 1/3 Vee and 213 Vee. See Figure 17.
The external capacitor changes to 213 Vee through RA and
RS and discharges to 1/3 Vee through RS. Sy varying the ratio
of these resistors the duty cycle can be varied. The charge and
discharge times are independent of the supply voltage.
discharge current (Pin 7 current) within the maximum rating
of the discharge transistor (200 mAl.
The minimum value of RA is given by:
RA
The charge time (output high) is given by:
tl 0.695 (RA + RS) e
=
~
Vee (Vdc)
17 (A)
~
Vee (Vdc)
--=--=--'-----'-
II
0.2
Figure 19. Free Running Frequency
The discharge time (output low) is given by:
t2 = 0.695 (RS) e
Thus the total period is given by:
T = tl + t2 = 0.695 (RA +2RS) e
The frequency of oscillation is then: f
=..1.- =
T
1.44
(RA +2RS) e
Ii:'
::1.
w
§;1
;:!:
(3
and may be easily found as shown in Figure 19.
The duty cycle is given by: De =
RS
RA+2RS
To obtain the maximum duty cycle RA must be as small as
possible; but it must also be large enough to limit the
MOTOROLA ANALOG IC DEVICE DATA
i't.
C3
c.5
O.Oll---+----f"...,----f'o,.----.po...;:---f~-_I
1.0
10
100
1.0k
10k
f, FREE RUNNING FREQUENCY (Hz)
lOOk
11-11
MC1455, B
APPLICATIONS INFORMATION
Linear Voltage Ramp
In the monostable mode, the resistor can be replaced by a
constant current source to provide a linear ramp voltage. The
capacitor still charges from 0 Vee to 213 Vee. The linear ramp
time is given by:
t= ~ Vee wherel= Vee-VB-VBE
3
1 '
RE
Missing Pulse Detector
The timer can be used to produce an ,output when an input
pulse fails to occur within the delay of the· timer. To
accomplish this, set the time delay to .be slightly longer than
the time between successive input pulses. The timing cycle is
then continuously reset by the input pulse train until a change
in frequency or a missing pulse allows completion of the
timing cycle, causing a change in the output level.
If VB is much larger than VBE, then t can be made
independent of Vee.
Figure 21. Missing Pulse Detector
Figure 20. Linear Voltage Sweep Circuit
+Vcc (5.0 Vto 15V)
Vcc
Vcc
Digital 3
Outpu1
VCC
Reset
4
RL
Rl
8
Discharge
3
VB
7
Output
MCI455
R2
Input
2
Threshold
6 Control
5 Voltage
Trigger
2N4403
or Equiv
Figure 22. Linear Voltage Ramp Waveforms
Figure 23. Missing Pulse Detector Waveforms
II
11-12
t = 100 llSicm
t= 500 I!Sicm
(RE= 10kn, R2 = 100 kO, Rl =39 kn,C =O.OII!F, Vcc= 15 V)
(RA = 2.0 kn, RL = 1.0 kn, C =O.OII!F, VCC = 15 V)
MOTOROLA ANALOG IC DEVICE DATA
MC1455, B
Pulse Width Modulation
If the timer is triggered with a continuous pulse train in the
monstable mode of ,operation, the charge time of the
capacitor can be varied by changing the control voltage at
Pin 5. In this manntflr, the output pulse width can be
modulated by applying a modulating signal that controls the
threshold voltage.
Figure 25. Pulse Width Modulation Waveforms
Figure 24. Pulse Width Modulator
+Vee (5.0 V to 15 V)
RA
RL
4
t=0.5ms/cm
(RA = 10 kQ, e = 0.02 ~F, Vee = 15 V)
7
3
~e
Output
6
MC1455
2
Test Sequences
Several timers can be connected to drive each other for
sequential timing. An example is shown in Figure 26 where
the sequence is started by triggering the first timer which runs
for 10 ms. The output then switches low momentarily and
starts the second timer which runs for 50 ms and so forth.
5
Clock
Input
Modulation
Input
Figure 26. Sequential Timer
Vee (5.0 V to 15 V)
9.1 k
9.1 k
27k
4
8
5 0.01
~
,
MC1455
~F
~1
3
r--&-
4
If
MC1455
2
2
1
S.OIlFI
OIlF
I '·
-=
Load
MOTOROLA ANALOG IC DEVICE DATA
--0--11
0.OO1 1lF
1
-=
r62
1
S.01lF
Load
5 0.011lF
~
3
"
0.OO1 1lF
4
8
5 O.o1IlF
~
~
18.2k
27k
8
MCI455
~1
+
1
-=
Load
11-13
®
MOT0f!l0LA
MC1494
Linear Fo,~r-Q:~ad.rant
MUltiiJlier
'
The MC1494 is designed for. use where the output voltage is a linear
product of two input voltages. Typical appli~tions include: multiply, divide,
square root,. me,E!,nsquare; phase detector, frequency doubler, balanced
modulator! demodulator, electronic gain control.
The MC1494 is' a variable' transconductance multiplier with internal
level-shift circuitry and voltage regulator. Scale factor, input offsets and output
offset are completely adjustable with the use of four external potentiometers.
Two complementary regulated voltages are provided to simplify offset
adjustment and improve power supply rejection.
LINEAR FOUR-QUADRANT
MULTIPLIER INTEGRATED
CIRCUIT
SEMICONDUCTOR
TECHNICAL DATA
• Operates with ±15 V Supplies
• Excellent Linearity: Maximum Error (X or Y) ±1.0 %
• Wide Input Voltage Range: ±10 V
• Adjustable Scale Factor, K (0.1 nominal)
• Single-Ended Output Referenced to Ground
• Simplified Offset Adjust Circuitry
• Frequency Response (3.0 dB Small-8ignal):.1.0 MHz
• Power Supply Sensitivity: 30 mVN typical
PSUFFIX
PLASTIC PACKAGE
CASE 648C
ORDERING INFORMATION
II
Figure 1. Multiplier Transfer Characteristic
Device
Tested Operating
Temperature Range
Package
MC1494P
TA=OOto + 70°C
Plastic DIP
Figure 2. Linearity Error versus Temperature
a:
!Ea:
0.751-----+-----11----+----+----1---+-----1
w
~
US O,W f-----I-----+---+--+--I--I----l
z
~
~----i_--_+----~--4_--_+----r_--1
~ 0.25 f----+----t--+---+-----1I---+----;
~
w
o~
-8.0 -6.0 -4,0 -2,0
0
2.0
4.0
VX, INPUT VOLTAGE (V)
11-14
6.0
8.0
10
-50
__
~
-25
__- L__
o
~L-
25
__L -__
W
~
__- L__
~
100
~
125
TA, AMBIENT TEMPERATURE (OC)
MOTOROLA ANALOG IC D.EVICE DATA
MC1494
MAXIMUM RATINGS (TA = + 25°C. unless otherwise noted.)
Symbol
Value
Unit
Power Supply Voltages
±V
±18
Vdc
Differential Input Signal
VS-V6
V1O....V13
±16 + 11 RyI<30
±16 + 11 RXI<30
Vdc
Common Mode Input Voltage
VCMY = V9=V6
VCMX =V1O=V13
VCMY
VCMX
±11.5
±11.5
Power Dissipation (Package Limitation)
TA=+25°C
Derate above TA = + 25°C
PD
1/8JA
1.25
20
Rating
Vdc
W
mW/oC
Operating Temperature Range
TA
Oto+70
°C
Storage Temperature Range
Tstg
.... 65 to +150
°c
ELECTRICAL CHARACTERISTICS (±V = ±15 V. TA = + 25°C. R1 = 16 kQ. RX = 30 kQ. Ry = 62 kQ. RL = 47 kQ.
unless otherwise noted.)
Characteristics
Linearity
Output error in percent of full scale
....10 V
to
....
....
....
....
....
CMV
ACM
±10.5
....
.... 65
....
....
Vpk
dB
Id+
IaPD
S+
S-
....
12
12
350
100
200
mAde
VR+. VR....
TCVR
SR+.SR....
5.0
Vdc
mVrC
mVN
BW3dB(X)
BW3dB(Y)
PBW
....
....
....
....
....
O.Og
7
kHz
8
(XorY)
(X or Y)
9
Quiescent Power Dissipation
Sensitivity
Regulated Offset Adjust Voltages
Positive/Negative
Temperature Coefficient (VR+ or VR....)
Power Supply Sensitivity (VFi+ or VA-)
±10
....
5.6
Power Bandwidth (47 k)
3° Relative Phase Shift
1% Absolute Error
Power Supply
Current
Vin
Rin
IVioxl
IVioyl
Ib
lIiol
11001
Typ
%
....
X Input Offset (Y = 0)
Y Input Offset (X = 0)
Scale Factor
Total DC Accurac'l Drift LX -10 Y -10)
Dynamic Response
Small Signal (3.0 dB)
Common Mode
Input Swing
Gain
Min
....
Output
Voltage Swing Capability
Impedance
Offset Voltage (Note 1)
Offset Current (Note 1)
Temperature Stability (Drift)
TA = Thigh to Tlow
Output Offset (X = o. Y = 0)
Figure
....
6.0
6.5
185
13
....
30
3.5
4.3
0.03
0.6
....
....
mW
mVN
9
....
....
....
....
NOTE: 1. Offsets can be adlustedto zero With external potentlomers. THigh = +7DoC. TLow = DOC
MOTOROLA ANALOG IC DEVICE DATA
11 ....15
MC1494
Figure 3. Linearity
Figure 4. Input Resistance
B.2k
10k
R;n x
Uneari1y. Error
=[ ~~-2]Mn
= Eo(peak)
Es(peak)
Figure 5. Offset Voltages, Gain
Figure 6. Input Bias CurrentJInput Offset
Current, Output Resistance
Vy---'!---b-!
III
Figure 7. Frequency Response
Figure 8. Common Mode
Vo
47k
11-16
MOTOROLA ANALOGIC DEVICE DATA
MC1494
Figure 9. Power Supply Sensitivity
Figure 10. Burn-ln
t-O--.......- _ Vo
-15V
Figure 11. Frequency Response of V Input
versus Load Resistance
15
~
~
II~~
5.0
OI".!
0
-15
~
~
Rl=47~
w
w
-20
104
Figure 13. Linearity versus RX or Ry with K
la:
0.4
0
a:
a:
w
~
0.3
Rl Adjusted for K = 1 __
Vin=2.0Vpp
"- ~
f"'.... ........
r-....
~ 0.2
z
~
>-
,jf 0.1
5
x
,jf
=1
---
f.It.=47kll
r-~~~~I~I~r=rm II
104
II
105
f, FREQUENCY (Hz)
I
106
Figure 14. Linearity versus RX or Ry with K = 1NO
e:.a:
0.6
0
a:
a:
w
~
a:
0.5
;;::;
....
0.4
<
w
r\
\
Rl Adjusted for K = 1/10
Vin=20Vpp
-
\
\.
" "-
~
5 0.3
x
a:
w
0
-m-
'-1J
Vx = 1.0 Vrms, Vy = 10 Vdc
103
106
~I~I
~j~JIl
-10
-20
105
f, FREQUENCY (Hz)
(1t.
0
-15
--RX=3°~lrY=i2rrlll
CO= 6.0pF
103
5.0
~ -5.0
Vy = 1.0Vrms, Vx = 10 Vdc
11111
Rl = 1.0 kll
>
a:
-10
II 11111
10
z
l~l=33kll
~-5.0
~
15
Rl~I~I·Ok~ II:
10
!z
Figure 12. Frequency Response of X Input
versus Load Resistance
......... r-.
0.2
2.0
4.0
6.0
8.0
10 RX (kll)
20
30
40
4.0
8.0
12
16
20 Ry(kll)
40
60
80
MOTOROLA ANALOG IC DEVICE DATA
50
100
RX(kll)
Ry (kll)
11-17
II
MC1494
Figure 15. Large Signal Voltage versus Frequency
Figure 16. Scale Factor (K) versus Temperature
0.108
~
Q.
~
K Factor Adjusted for 1110 at 25'C)
.......
W
t5 0.104""2~
Cl
~
0
>
....
::>
a..
50
0.106
CD
20
10
--<>-_.... Vo
P1 20k
1
0.11'F
P2
+15V
P3 SDk
Vo= -VXVy
-10-
'R is not necessary ninputs are DC coupled.
-=
-10V,;VX,;+10V
-10V,;Vy,;+10V
It should be pointed out that there is nothing magic about
setting the scale factor to 1/10. This is merely a convenient
factor to use if the Vx and Vy input voltages are expected to
be large, say ±10 V. Obviously with Vx Vy 10 V and a
scale factor of unity, the device could not hope to provide a
100 V output, so the scale factor is set to 1/10 and provides
an output scaled down by a factor of ten. For many
applications it may be desirable to set K 1/2 or K 1 or even
K = 100. This can be accomplished by adjusting RX, Ry and
RL appropriately.
The selection of RL is arbitrary and can be chosen after
resistors RX and Ry are found. Note in Figure 18 that Ry is
62 kil while RX is 30 kU The reason for this is that the "Y"
side of the multiplier exhibits a second order nonlinearity
whereas the "X" side exhibits a simple nonlinearity. By
making the Ry resistor approximately twice the value of the
RX resistor, the linearity on both the "X· and "YO sides are
made equal. The selection ofthe RX and Ry resistor values is
dependent upon the expected amplitude of Vx and Vy inputs.
To maintain a specified linearity, resistors RX and Ry should
be selected according to the following equations:
RX ;:: 3 Vx (max) in kil when Vx is in Volts,
Ry ;:: 6 Vy (max) in kO when Vy is in Volts.
currents of the op amp will cause errors in the output voltage,
particularly with temperature, one with very low bias and
offset currents is recommended. The MC1456 or MC1741
are excellent choices for this application.
Since the MC1494 is capable of operation at much higher
frequencies than the op amp, the frequency characteristics of
the circuit in Figure 18 will be primarily dependent upon the
operational amplifier.
For example, if the maximum input on the "X' side is ±1.0 V, .
resistor RX can be selected to be 3.0 kil. If the maximum
input on the "yo side is also ±1.0 V, then resistor Ry can be
selected to be 6.0 kil (6.2 kO nominal value). If a scale factor
of K =10 is desired, the load resistor is found to be 47 kil. In
this example, the multiplier provides a gain of 20 dB.
Offset Adjustment
The noninverting input of the op amp provides a
convenient point to adjust the output offset voltage. By
connecting this point to the wiper arm of a potentiometer
(P3), the output offset voltage can be adjusted to zero (see
Offset and Scale Factor Adjustment Procedure).
The input offset adjustment potentiometers, P1 and P2 will
be necessary for most applications where it is desirable to
take advantage of the multiplier's excellent linearity
characteristics. Depending upon the particular application,
some of the potentiometers can be omitted (see Figures 19,
21, 24, 26 and 27).
= =
=
II
-15V
=
Operational Amplifier Selection
The operational amplifier connection in Figure 18 is a
simple but extremely accurate current-ta-voltage converter.
The output current of the muHiplier flows through the
feedback resistor RL to provide a low impedance output
voltage from the op amp. Since the offset current and bias
11-20
Stability
The current-ta-voltage converter mode is a most
demanding application for an operational amplifier. Loop gain
is at its maximum and the feedback resistor in conjunction
with stray or input capacitance at the muHiplier output adds
additional phase shift. It may therefore be necessary to add
(particularly in the case of internally compensated op amps)
a small feedback capacitor to reduce loop gain at the higher
frequencies. A value of 10 pF in parallel with RL should be
adequate to insure stability over production and temperature
variations, etc.
An externally compensated op amp might be employed
using slightly heavier compensation than that recommended
for unity-gain operation.
MOTOROLA ANAJ.OG IC DEVICE .DATA
MC1494
Offset and Scale Factor Adjustment Procedure
The adjustment procedure for the circuit of Figure 18 is:
A. X Input Offset
1. Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)
to the "Y" input (Pin 9).
2. Connect "X" input (Pin 10) to ground.
3. Adjust X-offset potentiometer, P2 for an AC null
at the output.
B. Y Input Offset
1. Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)
to the "X" input (Pin 10).
2. Connect "Y" input (Pin 9) to ground.
3. Adjust Y-offset potentiometer, P1 for an AC null
at the output.
C. Output Offset
1. Connect both "X" and "Y" inputs to ground.
2. Adjust output offset potentiometer, P3 until the
output voltage Vo is 0 Vdc.
D. Scale Factor
1. Apply +10 Vdc to both the "X" and "Y" inputs.
2. Adjust P4 to achieve -10 V at the output.
3. Apply -10 Vdc to both "X" and "Y" inputs and
check for Vo =-10 V.
E. Repeat steps A through D as necessary.
The ability to accurately adjust the MC1494 is dependent on
the offset adjust potentiometers. Potentiometers should be of
the "infinite" resolution type rather than wirewound. Fine
adjustments in balanced-modulator applications may require
two potentiometers to provide ·coarse" and "fine" adjustment.
Potentiometers should have low temperature coefficients
and be free from backlash.
Temperature Stability
While the MC1494 provides excellent performance in
itself, overall performance depends to a large degree on the
quality of the external components. Previous discussion
shows the direct dependence on RX, Ry and RL and indirect
dependence on R1 (through 11). Any circuit subjected to
temperature variations should be evaluated with these
effects in mind.
Bias Currents
The MC1494 multiplier, like most linear ICs, requires a
DC bias current into its input terminals. The device cannot
be capacitively coupled at the input without regard for this
bias current. If inputs Vx and Vy are able to supply the
small bias current (= 0.5 /lA) resistors R can be omitted
(see Figure 18). If the MC1494 is used in an AC mode of
operation and capacitive coupling is used the value of
resistor R can be any reasonable value up to 100 kQ. For
minimum noise and optimum temperature performance, the
value of resistor R should be as low as practical.
Parasitic Oscillation
When long leads are used on the inputs, oscillation may
occur. In this event, an RC parasitic suppression network
similar to the ones shown in Figure 18 should be connected
directly to each input using short leads. The purpose of the
network is to reduce the "Q" of the source-tuned circuits
which cause the oscillation.
Inability to adjust the circuit to within the specified
accuracy may be an indication of oscillation.
MOTOROLA ANALOG IC DEVICE DATA
AC OPERATION
General
For AC operation, such as balanced modulation,
frequency doubler, AGC, etc., the op amp will usually be
omitted as well as the output offset adjust potentiometer. The
output offset adjust potentiometer is omitted since the output
will normally be AC coupled and the DC voltage at the output
is of no concern providing it is close enough to zero volts that
it will not cause clipping in the output waveform. Figure 19
shows a typical AC multiplier circuit with a scale factor K = 1.
Again, resistor RX and Ry are chosen as outlined in the
previous section, with RL chosen to provide the required
scale factor.
Figure 19. Wideband Multiplier
3.0k
6.2k
t-<:>--_ _-
.......eo
,
Rl -'- c
4.7k';"' 0
K=l
ex (max) = ey 0 the transfer
function through the multiplier is noninverting. Its output is fed
to the inverting input of the op amp Thus, operation is in the
negative feedback mode and the circuit is DC stable.
Figure 22. Basic Divide Circuit Using Multiplier
Vx
+
KVXVy
+
MC1494
Vy
Vz=-¥NXVy
or
-VZ
vO= KVX
Vz
>------VO
+
Should Vx change polarity, the transfer function through
the multiplier becomes inverting. the amplifier has positive
feedback and latch-up results. The problem resulting from
Vx being near zero is a result of the transfer through the
multiplier being near zero. The op amp is then operating with
a very high closed-loop gain and error voltages can thus
become effective in causing latch-Up.
The other mode of latch-up results from the output voltage
of the op amp exceeding the rated common mode input
voltage of the multiplier. The input stage of the multiplier
becomes saturated, phase reversal results, and the circuit is
latched up. The circuit of Figure 23 protects against this
happening by clamping the output swing of the op amp to
approximately ± 10.7 V. Five percent tolerance. 10 V zeners
are used to assure adequate output swing but still limit the
output voltage of the op amp from exceeding the common
mode input range of the MC1494.
Setting up the divide circuit for reasonably accurate
operation is somewhat different from the procedure for the
multiplier itself. One approach, however, is to break the
feedback loop. null out the multiplier circuit, and then close
the loop.
11-23
II
MC1494
Figure 23. Practical Divide Circuit
30k
Vz
62k
2
14
1N5240A'
(10V)
or
Equivalent
MC1741CP1
16k
MC1494
3
,..---Q-i
4
+
7
Vx
-IOVZ
15 13
10PFl
VO=VX
2
4
1
510
+15V
-15V
0< Vx < +10 V
-10V<;,VZ<;,+10V
-1SV+ISV
A simpler approach, since it does not involve breaking the
loop (thus making it more practical on a production basis), is:
1. Set Vz 0 V and adjust the output offset potentiometer
(P3) until the output voltage (VO) remains at some (not
necessarily zero) constant value as Vx is varied
between +1.0 V and +10 V.
2. Maintain Vz at 0 V, set Vx at + 10 V and adjust the
Y input offset potentiometer (P1) until Vo = 0 V.
3. With Vx VZ, adjust the X input offset potentiometer
(P2) until the output voltage remains at some (not
necessarily -10 V) constant value as Vz Vx is varied
between +1.0 V and +10 V.
=
=
=
=
4.
Maintain Vx Vz and adjust the scale factor
potentiometer (RL) until the average value of Vo is
-10 V as Vz Vx is varied between +1.0 V and +10 V.
5. Repeat steps 1 through 4 as necessary to achieve
optimum performance.
Users of the divide circuit should be aware that the
accuracy to be· expected decreases in direct proportion to the
denominator voltage. As a result, if Vx is set to 10 V and
0.5% accuracy is available, then 5% accuracy can be
expected when Vx is only 1.0 V.
In accordance with an earlier statement, Vx may have only
one polarity (positive) while Vz may be either polarity.
=
Figure 24. Basic Square Root Circuit
x
IW0 2=-VZ
or
Vo=fIYi
K
Vz <;,0 V
Vz
>--......-Vo
Square Root
A special case of the divide circuit in which the two inputs
to the multiplier are connected together results in the square
root function as indicated in Figure 24. This circuit too may
11-24
suffer from latch-up problems similar to those of the divide
circuit. Note that only one polarity of input is allowed and
diode clamping (see Figure 25) protects against accidental
latch-up.
This circuit too, may be adjusted in the closed-loop mode:
1. Set Vz -0.01 Vdc and adjust P3 (output offset) for
Vo 0.316 Vdc.
2. Set Vz to -0.9 Vdc and adjust P2 ("X" adjust) for'
Vo +3.0 Vdc.
3. Set Vz to -10 Vdc and adjust P4 (gain adjust) for
Vo = +10 Vdc.
4. Steps 1 through 3 may be repeated as necessary to
achieve desired accuracy.
=
=
=
NOTE: Operation near 0 V input may prove very inaccurate,
hence, it may not be possible to adjust Vo to zero but rather
only to within 100 mV to 400 mV of zero.
AC APPLICATIONS
Wideband Amplifier with Linear AGC
If one input to the MC1494 is a DC voltage and a signal
voltage is applied to the other input, the amplitude of the
output signal can be controlled in a linear fashion by varying
the DC voltage. Hence, the multiplier can function as a DC
coupled, wideband amplifier with linear AGC control.
In addition to the advantage of linear AGC control, the
multiplier has three other distinct advantages over most other
types of AGC systems. First, the AGC dynamic range is
theoretically infinite. This stems from the basic fact that with
o Vdc applied to the AGC, the output will be zero regardless
of the input. In practice, the dynamic range is limited by the
ability to adjust the input offset adjust potentiometers. By
using cermet multi-turn potentiometers, a dynamic range of
80 dB can be obtained. The second advantage of the
multiplier is that variation of the AGC voltage has no effect on
the signal handling capability of the signal port, nor does it
alter the input impedance of the signal port. This feature is
particularly important in AGC systems which are phase
sensitive. A third advantage of the multiplier is that the output
voltage swing capability and output impedance are
unchanged with variations in AGC voltage.
MOTOROLA ANALOG Ie DEVICE DATA
MC1494
Figure 25. Square Root Circuit
Vz
FI
10 P
510
4
lN962B
(1 N5241 B)
(llV)
or
Equivalent
VO)10IVZI
+15V -15V
-10V + cos(20Jct + ----......
X-V
Plotter
L __~
- . . . L . - -.....
5.0k
Scale
Factor
Adjust
-15V
Figure 6. Input and Output Current
Figure 7. Input Resistance
+32V
Ry=15k RX=15k
Ry=15k Rx= 15k
"t=1.0Vrms
20Hz
1.0M
+32V
111 9.1 k
1.0M
2 11k
MCI495
14 11 k
.:J:. O.II'F
7 13
12k
l
13.75k
J.
5.0k
+
O'II'F
O.lI'F
-15V
Figure 8. Output Resistance
Ry= 15k Rx=15k
Figure 9. Bandwidth (RL
+32V
111
Ry=15k RX=15k
9.1 k
"2
RL= 11 k
2 11 k
MC1495
11 k
13
5.0k
~
O.II'F
-15V
14
11 k
13
'V
"I
1.0Vrms ~O.II'F
20Hz
12k
+32V
9.1 k
MC1495
14
=11 kn)
R13
13.7k
~o.II'F
13.7k
Ro=RLI
:~
MOTOROLA ANALOG IC DEVICE DATA
-21
-15V
11-31
ID
MC1495
Figure 11. Common Mode Gain and
Common Mode Input Swing
Figure 10. Bandwidth (RL"; 50 0)
+15V
+32V
15k
1.0k
9.1 k
50
MC1495
14
+ 11 k
50
11 k
13
R13
13.71<
K=40
~O.II1F
f
=:=
Io.
10.I
l11F
I1F
·0
Vo
CL < 3.0 pF
AcM = 20 log CMVy
-15V
+32V
'V+
+32V(V+)
15k
or 20 log CMVX
Figure 13. Offset Adjust Circuit
Figure 12. Power Supply Sensitivity
15k
Vo
-15V
R
2.0k
Pol #2 To Pin 12
ToPinS Pol'l
yOffset_ 10k 10k _XOffset
6.2 V
Adjust
Adjust
2.0k
4.3k
2.0k
10k
-15V
2N2905A
or Equivalent
-=
22 k
-15V
-15V
(V-)
Figure 14. Offset Adjust Circuit (AHernate)
II
V+
R
5.1 V
To PinS Pot'l
YOffset
Pol#2
10k
10k
Adjust
~
To Pin 12
XOffset
Adjust
5.1V
2.0k
-15V
11-32
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 15. Linearity versus Temperature
2.0
~
1.B
~
1.6
;
1.4
1.2
~
"'
~
a: 0.105
~
'-'
',,-
=;.. 1.0
.If
Figure 16. Scale Factor versus Temperature
0.110
'"
.............
O.B
~
............
EF~
~
~ 0.6
w
0.4
0.2
-"
"
i1
--
w 0.100
...J
«
'-'
en
-:.<:
0.095
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (0C)
100
-25
-55
125
Figure 17. Error Contributed by Input
Differential Amplifier
1.0
g O.B
0.6
!z
~
0.4
«
'-'
en
O.B
:J
0.6
u..
u..
~
g 0.2
a:
o
12
10
!z
w
\
----
~
w
0.4
\
r£
0
a:
a:
0.2
~
~ .......
"-
w
14
16
RxorRy(kO)
125
Vx: Vy:±5.0 VMax
13: 113: 1.0 mAde
0
ffi
a.
w
1.0
W
...J
...J
...J
\
o
"
r--
0
25
50
75
100
TA, AMBIENTTEMPERATURE (0C)
C
\
:::l
u..
r--
Figure 18. Error Contributed by
Input Differential Amplifier
Vx: Vy = ± 10 VMax
13 = 113 = 1.0 mAde
~
i'r
.......
[
o
~
K Adjusted to 0.100 at 25°C
18
20
o
6.0
4.0
I"--I--
B.O
10
RxorRy(kQ)
14
12
Figure 19. Maximum Allowable Input Voltage versus Voltage at Pin 1 or Pin 7
14
"'c."
~
::;;
::;;
.,.,""
12
.,.,
10
8.0
Minimum I
::;;
~
6.0
IS
4.0
~
2.0
o
",..
.,.,""
.......... .,., ~
.,.,"" .,., ~
:J
~
.,.,- ~
......,.,.,.,.,.,.,.,V
.,.,.,.,.,.,~
,.~
o
2.0
.,.,""
.,.,""
"....
.,.,"" / " "
..".
Redommended
V
4.0
6.0
B.O
10
12
14
16
18
IV 11 or IV71 (V)
MOTOROLA ANALOG IC DEVICE DATA
11-33
MC1495
OPERATION AND APPLICATIONS INFORMATION
Theory of Operation
The MC1495 is a monolithic, four-quadrant multiplier
which operates on the principle of variable
transconductance. A detailed theory of operation is covered
in Application Note AN489, Analysis and Basic Operation of
the MC1595. The result of this analysis is that the differential
output current of the multiplier is given by:
IA - IB = Lli = 2VXVy
RXRyl3
where, IA and IB are the currents into Pins 14 and 2,
respectively, and Vx and Vy are the X and Y input voltages at
the multiplier input terminals.
DESIGN CONSIDERATIONS
General
The MC1495 permits the designer to tailor the multiplier to
a specific application by proper selection of external
components. External components may be selected to
optimize a given parameter (e.g. bandwidth) which may in
turn restrict another parameter (e.g. maximum output voltage
swing). Each important parameter is discussed in detail in the
following paragraphs.
Linearity, Output Error, ERX or ERY
Linearity error is defined as the maximum deviation of
output voltage from a straight line transfer function. It is
expressed as error in percent of full scale (see figure below).
~~v
*
~
f'
~"
For example, if the maximum deviation, VE(max), is
±100 mV and the full scale output is 10 V, then the
percentage error is:
ER =VE(max) x 100 =100 x 10-3 x 100 =±1.0%.
Vo(max)
10
II
Linearity error may be measured by either of the following
methods:
1. Using an X-Y plotter with the circuit shown in Figure 5,
obtain plots for X and Y similar to the one shown above.
2. Use the circuit of Figure 4. This method nulls the level
shifted output of the multiplier with the original input.The
peak output of the null operational amplifier will be equal
to the error voltage, VE (max).
One source of linearity error can arise from large signal
nonlinearity in the X and Y input differential amplifiers. To
avoid introducing error from this source, the emitter
degeneration resistors RX and Ry must be chosen large
enough so that nonlinear base-emitter voltage variation can
be ignored. Figures 17 and 18 show the error expected from
this source as a function of the values of RX and Ry with an
operating current of 1.0 mA in each side of the differential
amplifiers (i.e., 13 =113 = 1.0 mAl.
11-34
Exceeding this value will drive one side of the input amplifier
to "cutoff and cause nonlinear operation.
Current 13 and 113 are chosen at a convenient value
(observing power dissipation limitation) between 0.5 mA and
2.0 mA, approximately 1.0 mAo Then RX and Ry can be
determined by considering the input signal handling
requirements.
For VX(max) = VY(max) = 10 V;
~ tVE(maX)
+10V
VxorVy
~
f'
---.l.
3 dB Bandwidth and Phase Shift
Bandwidth is primarily determined by the load resistors
and the stray multiplier output capacitance and/or the
operational amplifier used to level shift the output. If
wideband operation is desired, low· value load resistors
and/or a wideband operational amplifier should be used.
Stray output capacitance will depend to a large extent on
circuit layout.
Phase shift in the multiplier circuit results from two
sources: phase shift common to both X and Y channels (due
to the load resistor-output capacitance pole mentioned
above) and relative phase shift between X and Y channels
(due to differences in transadmittance in the X and Y
channels). If the input to output phase shift is only 0.6°, the
output product of two sine waves will exhibit a vector error of
1%. A 3° relative phase shift between Vx and Vy results in a
vector error of 5%.
Maximum Input Voltage
VX(max), VY(max) input voltages must be such that:
VX(max) <113 Ry
Vy(max) <13 Ry
RX
10V
=Ry >1.0
mA =10 kQ.
2VXVy
The equation IA -IB
= RX Ry 13
is derived from IA - IB =
2VX Vy
(RX + 2kT ) (Ry + 2kT ) 13
ql13
q l3
with the assumption RX» 2kT and Ry» 2k,T.
qlt3
q3
At TA
=+25°C and 113 =13 =1.0 mA,
2kT = 2kT = 52
ql13 ql3
n.
Therefore, with RX =Ry =10 kQ the above assumption is
valid. Reference to Figure 19 will indicate limitations of
VX(max) or VY(max) due to VIand V7. Exceeding these limits
will cause saturation or "cutoff" of the input transistors. See
Step 4 of General Design Procedure for further details.
Maximum Output Voltage Swing
The maximum output voltage swing is dependent upon the
factors mentioned below and upon the particular circuit being
considered.
For Figure 20 the maximum output swing is dependent
upon V+ for positive swing and upon the voltage at Pin 1 for
negative swing. The potential at Pin 1 determines the
quiescent level for transistors 05, 06, 07 and 08. This
potential should be related so that negative swing at Pins 2 or
14 does not saturate those transistors. See General Design
Procedure for further information regarding selection of
these potentials.
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 20. Basic Multiplier
GENERAL DESIGN PROCEDURE
V+
RI
10
vx{
+
12
4
RL
2
+
Selection of component values is best demonstrated by
the following example. Assume resistive dividers are used at
the X and V-inputs to limit the maximum multiplier input to ±
5.0 V [VX = VY(max)l for a ± 10 V input [VX' = VY'(max)l
(see Figure 21). If an overall scale factor of 1/10 is desired,
RL
} Va
14
MC1495
+
then Vo = VX' Vy' = (2VX) (2Vy)= 4/10 Vx Vy
,
10
10
VY{
Therefore, K = 4/10 for the multiplier (excluding the divider
network).
Step 1. The fist step is to select current 13 and current 113.
There are no restrictions on the selection of either of these
currents except the power dissipation of the device. 13 and 113
will normally be 1.0 mA or 2.0 mAo Further, 13 does not have
to be equal to 113, and there is normally no need to make
them different. For this example, let
VO=KVXVy
2RL
K--- RXRy l3
13
3
R13
R3!
vIf an operational amplifier is used for level shift, as shown
in Figure 21, the output swing (of the multiplier) is greatly
reduced. See Section 3 for further details.
13 = 113 = 1.0 mAo
Figure 21. Multiplier with Operational Amplifier Level Shift
-15V
-15V
Rl
3.0 k
VY'
6
10 k
RO
3.0k
O.ll!F
RO
3.0k
~
7
7
+
2
3
+
10 k
10 k
9
+
Vx 3
-VXVy
VO= -10-
14
t
h
13
113
8
R13
12 k
5.0 k
P4
R3!
-10V:;; VX:;; +10V
-10V:;;Vy:;;+10V
5
Scale
Factor
Adjust -=
y Offset
Adjust
2.0 k
+15V
Pl
10 k
20k
18k
" RL !
~O.ll!F
4
MC1741C
VX'
+15V
RL
Output
Offset
Adjust
X Offset-=
Adjust
II
P2
-15V
5.1 V
MOTOROLA ANALOG IC DEVICE DATA
11-35
MC1495
To set currents 13 and 113 to \he desired value, it is only
necessary to connect a resistor between Pin 13 and ground,
and between Pin 3 and ground. From the schematic shown in
Figure 3, it can be seen that the resistor values necessary are
given by:
IV-I-Q.7V
R13 + 500 Q = - - : 1 - 13
R3+500Q-
IV-I-Q.7V
13
Let V- = -15 V, then R13 + 500 = 14.3 V or R13 = 13.8 kQ
1.0mA
V+-V1
R1=-21 3
Let R13 = 12 kQ. Similarly, R3 = 13.8 kQ, let R3 = 15 kn
15V th
R _15V-9.0V
L tV
e +=
,en 1 - (2) (1.0 rnA)
However, for applications which require an accurate scale
factor, the adjustment of R3 and consequently, 13, offers a
convenient method of making a final trim of the scale factor.
For this reason, as shown in Figure 21, resistor R3 is shown
as a fixed resistor in series with a potentiometer.
For applications not requiring an exact scale factor
(balanced modulator, frequency doubler, AGC amplifier, etc.)
Pins 3 and 13 can be connected together and a single
resistor from Pin 3 to ground can be used. Inthis case, the
single resistor would have a value of 1/2 the above calculated
value for R13.
Step 2. The next step is to select RX and Ry. To insure that
the input transistors will always be active, the following
conditions should be met:
Note that the voltage at the base of transistors 05, 06, 07
and 08 is one diode-drop below the voltage at Pin 1. Thus, in
order that these transistors stay active, the voltage at Pins 2
and 14 should be approximately halfway between the voltage
at Pin 1 and the positive supply voltage. For this example, the
voltage at Pins 2 and 14 should be approximately 11 V.
Step 5. For dc applications, such as the multiply, divide
and square-root functions, it is usually desirable to convert
the differential output to a single-ended output voltage
referenced to ground. The circuit shown in Figure 22
performs this function. It can be shown that the output voltage
of this circuit is given by:
Vx < 113,
RX
Let RX = Ry
then 13Ry
113RX
(2)(RL)
=~
2RL
= ~ or
RX Ry 13
10'
(10k)(10 k) (1.0 rnA) 10
Thus RL = 20 kQ.
Step 4. To determine what power supply voltage is
necessary for this application, attention must be given to the
circuit schematic shown in Figure 3. From the circuit
schematic it can be seen that in order to maintain transistors
01, 02, 03 and 04 in an active region when the maximum
input voltages are applied (VX' = VY' = 10 V or Vx = 5.0 V,
Vy = 5.0 V), their respective collector voltage should be at
least a few tenths of a volt higher than the maximum input
11-36
Va
And since IA -18
=(12 -114) RL
21Xly
=12 -114 =-13- =
2VXVy
13 RXRy
2R V 'V '
L X Y where, VX' Vy' is the voltage at
4RX RX 13
the input to the voltage dividers.
then Va =
= 10 kn,
= 10 V
= 10V
sinceVX(max)=VY(max)=5.0V,thevalueofRx= Ry = 10 kQ
is sufficient.
Step 3. Now that RX, Ryand 13 have been chosen, RL can
be determined:
K=
R1 =3.0 kn.
Vy <13
Ry
A good rule of thumb is to make 13Ry;:: 1.5 VY(max) and
113 RX;:: 1.5 VX(max). Thelargerthe 13Ryand 113RX product in
relation to Vy and Vx respectively, the more accurate the
multiplier will be (see Figures 17 and 18).
II
voltage. It should also be noticed that the collector voltage of
transistors 03 and 04 is at a potential which is two
diode-drops below the voltage at Pin 1. Thus, the voltage at
Pin 1 should be about 2.0 V higher than the maximum input
voltage. Therefore, to handle +5.0 V at the inputs, the voltage
at Pin 1 must be at least +7.0 V. Let V1 =' 9.0 Vdc.
Since the current flowing into Pin 1 is always equal to 213,
the voltage at Pin 1 can be set by placing a resistor (R1) from
Pin 1 to the positive supply:
Figure 22. Level Shift Circuit
v+
-'2
RO
V2
RO
+
Vo
V14
'14
RL
RL
The choice of an operational amplifier for this application
should have low bias currents, low offset current, and a high
common mode input voltage range as well as a high common
mode rejection ratio. The MC1456, and MC1741C
operational amplifiers meet these requirements.
MOTOROLA ANALOG IC DEVICE DATA
MC1495
The versatility of the MC1495 allows the user to to
optimize its performance for various input and output signal
levels.
Referring to Figure 21, the level shift components will be
determined. When Vx = Vv =0, the currents 12 and 114 will be
equal to 113. In Step 3, RL was found to be 20 kQ and in Step
4, V2 and V14 were found to be approximately 11 V. From this
information RO can be found easily from the following
equation (neglecting the operational amplifiers bias current):
OFFSET AND SCALE FACTOR ADJUSTMENT
Offset Voltages
Within the monolithic multiplier (Figure 3) transistor base·
emitter junctions are typically matched within 1.0 mV and
resistors are typically matched within 2%. Even with this
careful matching, an output error can occur. This output error
is comprised of X·input offset voltage, V·input offset voltage,
and output offset voltage. These errors can be adjusted to
zero with the techniques shown in Figure 21. Offset terms
can be shown analytically by the transfer function:
V2 I _ V+-V2
RL + 13-~
Andforthisexample
llV 10mA_15V-llV
'20kO+·
RO
Solving for RO: RO = 2.6 kn, thus, select RO = 3.0 kO
For RO
to be:
=3.0 kO, the voltage at Pins 2 and 14 is calculated
V2
=V14 =10.4 V.
Vo = K[Vx ± Viox ± Vx(off)J [Vy ± Vioy ± Vy(off)J ± VOO
Where:
The linearity of this circuit (Figure 21) is likely to be as
good or better than the circuit of Figure 5. Further
improvements are possible as shown in Figure 23 where RV
has been increased substantially to improve the V linearity,
and RX decreased somewhat so as not to materially affect
the X linearity. This avoids increasing RL significantly in order
to maintain a K of 0.1.
K
Vx
Vy
Viox
Vioy
Vx(off)
Vy(off)
VOO
(1)
= scale factor
"x" input voltage
= "y" input voltage
= "x" input offset voltage
= ''y'' input offset voltage
= "x" input offset adjust voltage
= "y" input offset adjust voltage
= output offset voltage.
=
Figure 23. Multiplier with Improved Linearity
-15V
-15V
r--~~-.---~---+---.+15V
3.0k
3.0k
7
14
3
+
10k
±10V
-VXVy
VO=-10-
MC1741C
10k
9
Vx'
+
10k
3
8
13
12
13k
40k
33k
12k
5.0k
Scale
Factor
Adjust
2
2
+
10k
YOllset
Adjust
+15V
15k
II
Output
Offset
Adjust
-=XOllset
Adjust
20 k
15 k
-15V
20k
2.0 k
MOTOROLA ANALOG IC DEVICE DATA
2.0 k
11-37
iff
~
MC1495
x, Y and Output Offset Voltages
o
Output
Offsat
Vx
X Offset
0
DC APPLICATIONS
Output
Offsat
Vy
Y Offset
For most dc applications, all three offset adjust
potentiometers (P1, P2, P4) will be necessary. One or more
offset adjust potentiometers can be eliminated for ac
applications (see Figures 28,29,30,31).
If well regulated supply voltages are available, the offset
adjust circuit of Figure 13 is recommended. Otherwise, the
circuit of Figure 14 will greatly reduce the sensitivity to power
supply changes.
Scale Factor
The scale factor K is set by Ps (Figure 21). Ps varies 13
which inversely controls the scale factor K. It should be noted
that current 13 is one-half the current through R1. R1 sets the
bias level for 05, 06, 07, and 08 (see Figure 3). Therefore, to
be sure that these devices remain active under all conditions
of input and output swing, care should be exercised in
adjusting P3 over wide voltage ranges (see General Design
Procedure).
Adjustment Procedures
The following adjustment procedure should be used to null
the offsets and set the scale factor for the multiply mode of
operation, (see Figure 21).
III
1. X-Input Offset
(a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)
to the V-input (Pin 4).
(b) Connect X-input (Pin 9) to ground.
(c) Adjust X offset potentiometer (P2) for an ac
null at the output.
2. Y-Input Offset
(a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)
to the X-input (Pin 9).
(b) Connect V-input (Pin 4) to ground.
(c) Adjust Y offset potentiometer (P1) for an ac null
at the output.
3. Output Offset
(a) Connect both X and V-inputs to ground.
(b) Adjust output offset potentiometer (P 4) until
the output voltage (VO) is 0 Vdc.
4. Scale Factor
(a) Apply +10 Vdc to both the X and V-inputs.
(b) Adjust P3 to achieve + 10 V at the output.
5. Repeat steps 1 through 4 as necessary.
Multiply
The circuit shown in Figure 21 may be used to multiply
signals frOm dc to 100 kHz. Input levels to the actual
multiplier are 5.0 V (max). With resistive voltage dividers the
maximum could be very large however, for this application
two-to-one dividers have been used so that the maximum
input level is 10 V. The maximum output level has also been
designed for 10 V (max).
Squaring Circuit
If the two inputs are tied together, the resultant function is
squaring; that is Vo =KV2 where K is the scale factor. Note
that all error terms can be eliminated with only three
adjustment potentiometers, thus eliminating one of the input
offset adjustments. Procedures for nulling with adjustments
are given as follows:
A. AC Procedure:
1.
2.
3.
4.
5.
Connect oscillator (1.0 kHz, 15 Vpp) to input.
Monitor output at 2.0 kHz with tuned voltmeter
and adjust Ps for desired gain. (Be sure to peak
response of the voltmeter.)
Tune voltmeter to 1.0 kHz and adjust P1 for a
minimum output voltage.
Ground input and adjust P4 (output offset) for
o Vdc output.
Repeat steps 1 through 4 as necessary.
B. DC Procedure:
1. Set Vx = Vy = 0 V and adjust P4 (output offset
potentiometer) such that Vo = 0 Vdc
2. Set Vx =Vy =1.0 V and adjust P1 (Y-input offset
potentiometer) such that the output voltage is
+0.100V.
3. Set Vx = Vy = 10 Vdc and adjust P3 such that
the output voltage is + 10 V.
4. Set Vx =Vy =-10 Vdc. Repeat steps 1 through
3 as necessary.
Figure 24. Basic Divide Circuit
~
Vz _--'lIVV--4I---<>--1
R2
>---o-........ VY
+
The ability to accurately adjust the MC1495 depends upon
the characteristics of potentiometers P1 through P4.
Multi-turn, infinite resolution potentiometers with low
temperature coefficients are recommended.
11-38
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Divide Circuit
Consider the circuit shown in Figure 24 in which the
multiplier is placed in the feedback path of an operational
amplifier. For this configuration, the operational amplifier will
maintain a "virtual ground" at the inverting (-) input.
Assuming that the bias current of the operational amplifier is
negligible, then 11 = 12 and,
KVXVy
-VZ
--=
Rl
R2
Percentage error = error x 100%
actual
or from Equation (5),
~
KVX
PED=[~]
(2)
If Rl=R2,
-VZ
Vy=KVX
(3)
If Rl= KR2,
-VZ
Vy= Vx
(4)
A suggested adjustment procedure for the divide circuit.
(5)
1. Set Vz = 0 V and adjust the output offset potentiometer
(P4) until the output voltage (VO) remains at some (not
necessarily zero) constant value as VX' is varied
between +1.0 V and +10 V.
2. Keep Vz at 0 V, set VX' at + 10 V and adjust the y input
offset potentiometer (Pl) until Vo = 0 V.
3. Let VX' = Vz and adjust the X-input offset potentiometer
(P2) until the output voltage remains at so~e (~ot
necessarily -1 0 V) constant value as Vz = VX' IS vaned
between +1.0 and +10 V.
4. Keep VX' = Vz and adjust the scale factor potentiometer
(P3) until the average value of Vo is -1 0 V as Vz = VX' is
varied between +1.0 V and +10 V.
5. Repeat steps 1 through 4 as necessary to achieve
optimum performance.
10~E
=-vx + ----vx
-10VZ
(7)
Two things should be emphasized concerning Figure 25.
1. The input voltage (VX') must be greater than zero and
must be positive. This insures that the current out of
Pin 2 of the multiplier will always be in a direction
compatible with the polarity of VZ.
2. Pin 2 and 14 of the multiplier have been interchanged in
respect to the operational amplifiers input terminals. In
this instance, Figure 25 differs from the circuit
connection shown in Figure 21; necessitated to insure
negative feedback around the loop.
where ~E is the error voltage at the output of the multiplier.
From this equation, it is seen that divide accuracy is strongly
dependent upon the accuracy at which the multiplier can be
set, particularly at small values of Vy. For example, assume
that Rl = R2, and K = 1/10. For these conditions the output of
the divide circuit is given by:
Vy
[R2] ~E
.R1. Vz
From Equation 7, the percentage error is inversely related
to voltage Vz (i.e., for increasing values of VZ, the percentage
error decreases).
A circuit that performs the divide function is shown in
Figure 25.
Hence, the output voltage is the ratio of Vz to Vx and
provides a divide function. This analysis is, of course, the
ideal condition. If the multiplier error is taken into account, the
output voltage is found to be:
~E
[ Rl ] Vz
VY=-.R2K. VX+ KVX
Vz =
.R2 K. Vx
(1)
-Rl Vz
Vy= R2KV)(
Solving for Vy,
In terms of percentage error,
(6)
From Equation 6, it is seen that only when Vx = 10 V is the
error voltage of the divide circuit as low as the error of the
multiply circuit. For example, when Vx is small, (0.1 V) the
error voltage of the divide circuit can be expected to be a
hundred times the error of the basic multiplier circuit.
m
Figure 25. Divide Circuit
-15V
-15V
r---~~--~----~-----t----~---1--~+15V
3.0 k
O.IIJ-F
3.0 k
*
7
H>~t----+---63-1 +
4
10 k
MC1741C
VX'
10 k
9
*O.IIJ-F
>--c6.-.._____.... Vo
-10VZ
VO=---yx
2
+
+ I-O---l----..-----+-VO
KV0 2=-VZ
or
VO=~
Square Root
A special case of the divide circuit in which the two inputs
to the multiplier are connected together is the square root
function as indicated in Figure 26. This circuit may suffer from
latch-up problems similar to those of the divide circuit. Note
that only one polarity of input is allowed and diode clamping
(see Figure 27) protects against accidental latch-up.
This circuit also may be adjusted in the closed-loop mode
as follows:
1. Set Vz to -0.01 V and adjust P4 (output offset) for
Va = +0.316 V, being careful to approach the output
from the positive side to preclude the effect of the output
diode clamping.
2. Set Vz to -0.9 V and adjust P2 (X adjust) for
Va =+3.0V.
3. Set Vz to -10 V and adjust P3 (scale factor adjust)
for Va = +10 V.
4. Steps 1 through 3 may be repeated as necessary to
achieve desired accuracy.
The applications that follOW demonstrate the versatility of
the monolithic multiplier. If a potted multiplier is used for these
cases, the rel!ults generally would not be as good because
the potted units have circuits that, although they optimize dc
multiplication operation, can hinder ac applications.
Frequency doubling often is done with a diode where
the fundamental plus a series of harmonics are
generated. However, extensive filtering is required to obtain
the desired harmonic, and the second harmonic obtained
under this technique usually is small in magnitude and
requires amplification.
When a multiplier is used to double frequency the second
harmonic is obtained direclly, except for a dc term, which can
be removed with ac coupling.
eo =KE2 cos2 rot
KE2
eo =2 (1 + cos 200t).
A potted multiplier can be used to obtain the double
frequency component, but frequency would be limited by its
internal level-shift amplififer. In the monolithic units, the
amplifier is omitted.
In a typical doubler Circuit, conventional ± 15 V supplies
are used. An input dynamic range of 5.0 V peak-to-peak is
allowed. The circuit generates wave-forms that are double
frequency; less than 1% distortion is encountered without
filtering. The configuration has been successfully used in
excess of 200 kHz; reducing ihe scale factor by decreasing
the load resistors can further expand the bandwidth.
Figure 29 represents an application for the monolithic
multiplier as a balanced modulator. Here, the audio input
signal is 1.6 kHz and the carrier is 40 kHz.
Figure 27. Square Root Circuit
-15V
-15V
II
10k
13k
13k
12k
5.0k
Scale P3
Factor
Adjust -=
11-40
To Offset
Adjust
(See Figure 13)
Vz
20k
RL
S.Ok
P4
Output
Offset
Adjust
-10,;;VZ';;+OV
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 28. Frequency Doubler
Ry
RX
8.2 k
8.2 k
The defining equation for balanced modulation is
K(Emcos Olmt) (Ec cos Olet)
Vee +15 V
=
KEc Em [cos (Ole + Olm)t + cos (Ole - Olm) t 1
2
where Ole is the carrier frequency. Olm is the modulator
frequency and K is the multiplier gain constant.
AC coupling at the output eliminates the need for level
translation or an operational amplifier; a higher operating
frequency results.
A problem common to communications is to extract the
intelligence from single-sideband received signal. The ssb
signal is of the form:
essb =A cos (Ole + Olm) t
E cos rot
«
5.0 Vppl
Offset
Adjust
...-:----o-j
6.8k
and if multiplied by the appropriate carrier waveform. cos Olet.
-15V
When two equal cosine waves are applied to X and y, the result
is a wave shape of twice the input frequency. For this example
the input was a 10 kHz signal, output was 20 kHz.
Figure 29. Balanced Modulator
(A)
essbecarrier = ~ [cos (20le + Olm)t + cos (Ole) t 1·
If the frequency of the band~limited carrier signal (Ole) is
ascertained in advance, the designer can insert a low pass
filter and obtain the (AKl2) (cosOlet) term with ease. He/she
also can use an operational amplifier for a combination level
shift-active filter, as an extemal component. But in potted
multipliers, even if the frequency range can be covered, the
operational amplifier is inside and not accessible, so the user
must accept the level shifting provided, and still add a low
pass filter.
Amplitude Modulation
The multiplier performs amplitude modulation, similar to
balanced modulation, when a dc term is added to the
modulating signal with the V-offset adjust potentiometer (see
Figure 30).
ey = E cos Olmt
eX = E cos OlCt
Here, the identity is:
Offset y
Adjust X
Em(1 + m cos Olmt) Ec cos Olet = KEmEccos Olet +
KEmEcm
- - 2 - - [COS(Ole + Olm)t + cos (Ole - Olm) t 1
6.8k
-15V
(B)
MOTOROLA ANALOG
Ie DEVICE DATA
where m indicates the degrees of modulation. Since m is
adjustable, via potentiometer P1, 100% modulation is
possible. Without extensive tweaking, 96% modulation may
be obtained where Ole and Olm are the same as in the
balanced modulator example.
Linear Gain Control
To obtain linear gain control, the designer can feed to one
of the two MC1495 inputs a signal that will vary the unit's
gain. The following example demonstrates the feasibility of
this application. Suppose a 200 kHz sinewave, 1.0 V
peak-to-peak, is the signal to which a gain control will be
added. The dynamic range of the control voltage Vc is 0 V to
+1.0 V. These must be ascertained and the proper values of
RX and Ry can be selected for optimum performance. For the
200 kHz operating frequency, load resistors of 100 n were
chosen to broaden the operating bandwidth of the multiplier,
but gain was sacrificed. It may be made up with an amplifier
operating at the appropriate frequency (see Figure 31).
11-41
II
MC1495
Figure 30. Amplitude Modulation
Ry
8.2 k
VCC=+15V
RX
8.2 k
ey = Ecos romt
ex = E cos IOmt
RL1
3.3k
% Modutation Adjust
Offset Adjust
'Select
ex, ey < 5.0 Vpp
6.8k
-15V
The signal is applied to the unit's V-input. Since the total
input range is limited to 1.0 Vpp , a 2.0 V swing, a current
source of 2.0 rnA and an RV value of 1.0 kQ is chosen. This
takes best advantage of the dynamic range and insures
linear operation in the V-channel.
Since the X-input varies between 0 and +1.0 V, the current
source selected was 1.0 rnA, and the RX value chosen
was 2.0 kQ. This also insures linear operation over the
X-input dynamic range. Choosing RL = 100 assures wide
bandwidth operation.
Hence, the scale factor for this configuration is:
RL
K= RX RV 13
=
100
(2 k) (1 k) (2 x 103) V-1
= _1_ V-1
40
The 2 in the numerator of the equation is missing in this scale
factor expression because the output is single-ended and ac
coupled.
Figure 31. Linear Gain Control
2.0k
+12V
1.0k
1.25
Yin = 1.0Vpp
200kHz
10
6
Y F'---'.:...L...L.:--'':'-' 1 1.5 k
Vinlot--_-o-r +
1.0
4
Q.
II
Vc
Offset
Adjust
MC1495
1
k= 40
X
1.0k
0.1IlF~
2
+
9
y
(5
>
0.5
100
0.25
8
X
12
0.75
>0..
100
14
O~~_~~L--L_~~~
3
13
o
7
2.0mA+
0.2
0.4
0.6 0.8
VAGC(V)
1.0
1.2
3.0 k
11 k
5.0k
P3
J'"1.0 Il F
NOTE:
Linear gain control of a 1.0 Vpp signal is perfonned with a a v
to 1.0 V control vo~age. If Vc IS 0.5 V the output will be 0.5 Vpp.
-12V
11-42
MOTOROLA ANALOG IC DEVICE DATA
®
MOTOROLA
MC3456
Dual Timing Circuit
The MC3456 dual timing circuit is a highly stable controller capable of
producing accurate time delays, or oscillation. Additional terminals are
provided for triggering or resetting if desired. In the time delay mode of
operation, the time is precisely controlled by one external resistor and
capacitor per timer. For astable operation as an oscillator, the free running
frequency and the duty cycle are both accurately controlled with two external
resistors and one capacitor per timer. The circuit may be triggered and reset
on falling waveforms, and the output structure can source or sink up to
200 mA or drive MTTL circuits.
DUAL TIMING CIRCUIT
SEMICONDUCTOR
TECHNICAL DATA
• Direct Replacement for NE556/SE556 Timers
PSUFFIX
PLASTIC PACKAGE
CASE 646
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
DSUFFIX
PLASTIC PACKAGE
CASE 751
(So-14)
• Adjustable Duty Cycle
.#
• High Current Output can Source or Sink 200 mA
• Output can Drive MTTL
1
• Temperature Stability of 0.005% per °C
• Normally "On" or Normally "Off" Output
• Dual Version of the Popular MC1455 Timer
PIN CONNECTIONS
Discharge A 1
Threshold A 2
13
Discharge B
ControlA 3
12
Threshold B
ResstA 4
11
Control B
Figure 1. 22 Second Solid State Time Delay Relay Circuit
OutputA 5
TriggerA 6
9 OutputB
Gnd 7
8 TriggerB
10k
(Top View)
t=1.1;RaOOC=22sec
lime delay (t) is variable by
changing Rand C (see Figure 16).
ORDERING INFORMATION
lN4740
Device
MC3456P
Figure 3. General Test Circuit
Operating
Temperature Range
0° to +70°C
Package
Plastic DIP
So-14
NE556D
r~t-
Figure 2. Block Diagram (1/2 Shown)
vee
r2 (12
I
------------,
14
I
5k
1 ~(13)Discharge
. ./"_-0-
.!:.:{:I--+..,
Control Voitage3",(I,(1:1--+..,
Threshold
I
I
5"'-'(9) Output
'-----'''_..:n..
Test circuit for measuring De parameters (to set output and measure parameters):
a) When Vs '" 213 Vee, Vo is low.
b) When Vs '" 113 Vee, Vo is high.
c) When Vo is low, Pin 7 sinks current. To test for Reset, set Vo high,
apply Reset voltage. and test for current flowing into Pin 7. When Reset
is not in use, n should be tied to Vee.
MOTOROLA ANALOG IC DEVICE DATA
_ _ _ _ _ ...J
L
4(10)
Goo
Reset
11-43
m
MC3456
MAXIMUM RATINGS (TA =+25°e, unless otherwise noted.)
Symbol
Value
Unit
Power Supply VoHage
VCC
+lB
Vdc
Discharge Current
Idis
200
rnA
Power Dissipation (Package limitation)
P Suffix, Plestic Package. Case 646
Derate above TA = +25°C
D Suffix, Plastic Package, Case 751
Derate above TA = ';'25°C
PD
625
5.0
1.0
B.O
mW
mWFC
W
mWFC
TA
Oto +70
°C
Tstg
-65 to +150
~C
!'Iatlng
Operating Ambient Temperature Aange
Storage Temperature Aange
ELECTRICAL CHARACTERISTICS (TA = +25°e, Vee = +15 V, unless otherwise noted.)
Symbol
Min
Typ
Max
Supply Voltage
VCC
4.5
-
16
Supply Current
VCC =5.0 V, Al =~
VCC = 15V, AL=~LowState, (Note 1)
ICC
Characteristics
Timing Error (Note 2)
Monostable Mode (AA = 2.0 kQ; C = 0.1 I1F)
InHial Aocuracy
Drift wHh Temperature
Drift wHh Supply Voltage
Astable Mode (AA = AB = 2.0 kQ to 100 kQ; C = 0.01 I1F)
InHial Aocuracy
Drift wHh Temperature
Drift wHh Supply Voltage
-
Threshold Voltage
Vth
Trigger Voltage
VCC=15V
VCC=5.0V,
VT
V
rnA
6.0
20
12
30
-
-
0.75
50
0.1
-
2.25
150
0.3
-
213
-
5.0
1.67
-
-
%
PPMFC
%N
%
PPMFC
%N
xVCC
V
Trigger Current
IT
-
0.5
-
AesetVoltage
VA
0.4
0.7
1.0
V
Aeset Current
IA
-
0.1
-
rnA
0.03
0.1
ItA
9.0
2.6
10
3.33
11
4.0
-
-
0.1
0.4
2.0
2.5
0.25
0.75
2.75
-
0.25
0.35
-
12.5
-
12.75
2.75
13.3
3.3
-
Threshold Current (Note 3)
DI
-
Unit
Ith
Control Voltage level
VCC=15V
VCC=5.0V
VCl
Output VoHage low
(VCC=15V)
ISink= lOrnA
ISink=50mA
ISink = 100 rnA
ISlnk = 200 rnA
(VCC= 5.0 V)
ISink = 5.0 rnA
VOL
Output Voltage High
(ISource = 200 rnA)
VCC=15V
(lSource = 100 rnA)
VCC=15V
VCC=5.0V
VOH
Toggle Aate AA = 3.3 kO, AB = 6.B kO, C = 0.00311F (Figure 17, 19)
Discharge leakage Current
Idis
Rise Time of Output
tolH
Fall Time of Output
toHl
Matching Characteristics Between Sections
Monostable Mode
Initial Timing Aocuracy
Timing Drift with Temperatura
Drift wHh Supply Voltage
ItA
V
V
-
V
-
-
100
-
kHz
20
100
nA
100
100
1.0
±10
0.2
2.0
-
0.5
ns
ns
%
ppmFC
%N .
NOTES: 1. Supply current is typically 1.0 rnA less for each output which is high.
2. Tested at VCC = 5.0 V and VCC = 15 V.
3. This will detennlne the maximum value of AA + AB for 15 V operation. The maximum total A = 20 mOo
11-44
MOTOROLA ANALOG IC DEVICE DATA
MC3456
Figure 4. Trigger Pulse Width
Figure 5. Supply Current
150
10
Z 125
~
g
:c
....
e
100
~
75
~
a.
50
w
::>
~
I
25'y ~
<.s
....
z
8.0
a:
a:
6.0
.."
w
I---
~
---
::>
o'e
~
25'e
~
a.
a.
4.0
::>
en
f--::: :::..-:~
70'e
.:>
~ i:--
25
V
()
-
/'
V
/
,.,..,
./
./
.9 2.0
~
o
o
0.1
0.2
0.3
o
0.4
5.0
10
15
Vee. SUPPLY VOLTAGE (Vile)
VT (min). MINIMUM TRIGGER VOLTAGE (X Vee = Vdc)
Figure 7. Low Output Voltage
Figure 6. High Output Voltage
(@ Vee = 5.0 Vdc)
2.0
10
1.8
-
1.6
~:c
f
()
:f?
~~
25'e
1.4
1.2
"..:.
1.0
~
0.8
~
5}V~lVe~~!5V -
0.4
0.2
o
1.0
2.0
5.0
/
--
0.1
0.6
-
25'e/
1.0
.-/
0.01
10
20
50
100
1.0
2.0
5.0
10
20
ISource (mA)
ISink(mA)
Figure 8. Low Output Voltage
Figure 9. Low Output Voltage
(@ Vee =15 Vdc)
(@ Vee = 10 Vdc)
10
50
II
10
r
:g
100
1.0
~
..:.
~
k ~
---
./
"~..:.
25'e ........
0.1
I
1.0
I)
~
0.1
.....
0.01
--
;;:£..
0.01
1.0
2.0
5.0
10
20
ISink(mA)
MOTOROLA ANALOG IC DEVICE DATA
50
100
1.0
2.0
5.0
10
20
50
100
ISink(mA)
11-45
MC3456
Figure 10. Delay Time versus Supply Voltage
Figure 11. Delay Time versus Temperature
1.015
fa
1.010
~
1.005
~
1.015
\
1.000
5
w
0.995
;::
- --
\"\
Sl
~
c
\
[-
~
a:~
~--
1.005
~
~
1.000
5
0.995
;::
~- I -
-
UJ
c
;9 0.990
0.985
1.010
c
;9 0.990
o
5.0
10
15
0.985
-75
20
-50
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (0C)
Vee, SUPPLY VOLTAGE (Vdc)
Figure 12. Propagation Delay
versus Trigger Voltage
300
~
I
250
;::
5
200
5
150
~
100
~
~
~
a..
j.
-
=ooe
~70~e
.I
..r::::::; .,
~
25°e
50
o
o
11-46
-
~
0.1
0.2
0.3
VT (min), MINIMUM TRIGGER VOLTAGE (x Vee = Vdc)
0.4
MOTOROLA ANALOG IC DEVICE DATA
MC3456
Figure 13. 112 Representative Circuit Schematic
Control Voltage
Threshold
Output
Trigger o-------t---j-j
Reset
100
GENERAL OPERATION
The MC3456 is a dual timing circuit which uses as its
timing elements an external resistor/capacitor network. It can
be used in both the monostable (one shot) and astable
modes with frequency and duty cycle, controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input
signal and the other for capacitor voltage; also a flip-flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit Figure 15). When the input
voltage to the trigger comparator falls below 1/3 VCC the
comparator output triggers the flip-flop so that it's output sets
low. This turns the capacitor discharge transistor "off' and
drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which is
set by the RC time constant. When the capacitor voltage
reaches 213 VCC the threshold comparator resets the
flip-flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip-flop
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
MOTOROLA ANALOG IC DEVICE DATA
=
that the output is high is given by the equation t 1.1 RA C.
Various combinations of Rand C and their associated times
are shown in Figure 14. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned "on" and prevents
the capacitor from charging. While the reset voltage is
applied the digital output will remain the same. The reset pin
should be tied to the supply voltage when not in use.
Figure 14. Time Delay
100
u::
:;.
/
w
0
z
~
1.0
it
0.1
V
I-
(3
('§
c.5
0.01 i/
0.001 /
101LS
/
~9~/~~ ~~
/
/
/
/
1/
V
V
V
100llS 1.0ms
/
/
/
1/
~~Q
/
./
/
/
/
/
,,9,/ ~<)~
/
L
/
1/
/
/
/
/
/
/
/
/
10
/
/
10ms 100ms
td, TIME DELAY (s)
1.0
10
100
11-47
II
MC3456
Figure 15. Monostable Circuit
Figure 16. Monostable Waveforms
+Vcc (5.0Vto t5V)
Reset
Vcc
4 (to)
14
5 (9)
Output
2(12)
1~
6(8)
Discharge
1 (13)
Threshold
MC3456
3(11)
Trigge,
Gnd
Control
Voltage
O.Ol Il
F,J
1= 50 Ils/em
(RA =10k.Q, C=O.OIIlF, RL = 1.0k.Q, VCC= 15V)
Pin numbers in parenthesis ( ) indicate B-Channel
Figure 18. Astable Waveforms
t=2°llsicm
(RA=5.1 k!l, C =0.0 IIlF, RL = 1.0 k!l, Ra=3.9 k.Q, VCC= 15V)
II
Astable Mode
In the astable mode the timer is connected so that it will
retrigger itself and cause the capacitor voltage to oscillate
between 1/3 VCC and 2/3 Vee (see Figure 17).
The external capacitor charges to 2/3 Vee through RA and
RS and discharges to 1/3 Vee through RS. Sy varying the
ratio of these resistors the duty cycle can be varied. The
charge and discharge times are independent of the supply
voltage.
discharge current (Pin 7 current) within the maximum rating
of the discharge transistor (200 mAl.
The minimum value of RA is given by:
RA ~ Vee (Vdc) ~ Vee (Vdc)
17 (A)
0.2
Figure 19. Free Running Frequency
The charge time (output high) is given by:
t1 = 0.695 (RA+RS) e
The discharge time (output low) by:
t2 0.695 (RS) e
=
10
CL
Thus the total period is given by:
T = t1 + t2 = 0.695 (RA + 2RS) e
The frequency of oscillation is then: f
+
= = (RA ;;~S) e
and may be easily found as shown in Figure 19.
The duty cycle is given by: De
= R:~2RS
To obtain the maximum duty cycle, RA must be as small as
possible; but it must also be large enough to limit the
11-48
:l.
w
(,)
z
;:!:
13
Cf.
c:§
c.5
0.1
0.01
0.001
0.1
1.0
10'
100
1.0 k
10 k
f, FREE RUNNING FREQUENCY (Hz)
lOOk
MOTOROLA ANALOG IC DEVICE DATA
MC3456
APPLICATIONS INFORMATION
Tone Burst Generator
For a tone burst generator, the first timer is used as a
monostable and determines the tone duration when triggered
by a positive pulse at Pin 6. The second timer is enabled by
the high output of the monostable. It is connected as an
astable and determines the frequency of the tone.
Dual Astable Multivibrator
This dual astable multivibrator provides versatility not
available with single timer circuits. The duty cycle can be
adjusted from 5% to 95%. The two outputs provide two phase
clock signals often required in digital systems. It can also be
inhibited by use of either reset terminal.
Figure 20. Tone Burst Generator
Rese:
A,-
~
14
~
6
Trigger
VCC
14
Output
112
MC3456
Discharge
2
Threshold
t
7
Cl-
3
~
Gnd
0.01
Vcc
RA
13 Discharge
10
5
Trigge{
I
+15V
Reset
,-J.OUtput
Re
12 Threshold
112
MC3456
B Trigger
::I
rol
~F
71
Gnd
o.otmFT
T
C2
Gnd
1.44
Figure 21. Dual Astable Multivibrator
+15V
Rl
Reset
10k
14
lN914
10k
lN914
10
Reset
R2
12
Output
Output
112
MC3456
Discharge
Cl
7
Discharge
Trigger
Trigger
Control
Voltage
112
MC3456
0.001
Control
Voltage
11
Gnd
Output
T
m
C2
T
I
I
Gnd
0.91
f= (Rl+R2)C torCl=C2
MOTOROLA ANALOG IC DEVICE DATA
R2
DulyCycle Fii+R2
11-49
MC3456
Pulse Width Modulation
If the timer is triggered with a continuous pulse train in the
monostable mode of operation, the charge time of the
capacitor can be varied by changing the control voltage at
Pin 3. In this manner, the output pulse width can be
modulated by applying a modulating signal that controls the
threshold voltage.
Test .Sequences
Several timers can be connected to drive each other for
sequential timing. An example is shown in Figure 24 where
the sequence is started by triggering the first timer which runs
for 10 ms. The output then switches low momentarily and
starts the second timer which runs for 50 ms and so forth.
Figure 23. Pulse Width Modulation Circuit
Figure 22. Pulse Width Modulation Waveforms
+VCC(SOVtolSV)
4(1~1~
RL
RA
Reset
Output
Output
14
Vee
Discharge
112
MC3456
2 (12)
C.Qntrol
Trigger
Clock
Input
i
1 (13)
Threshold
S (9)
3(11)
6 (8)
Gnd
C
Modulatio
Input
7
t=0.5 ms/cm
(RA = 10 kW, e = 0.02 mF, Vee = 15 V)
Figure 24. Sequential Timing Circuit
VcciS.OVtoI5V)
27k
9.1k
Threshold
Threshold
~
~f-l
Discharge
MC3456
II
Tngger
Output
0.001
Trigger
~J
SOk
Reset
VCC
~
,Discha~
112
MC3456
Trigger
~F
-=
Output
Gnd
Load
0.01
--:o--jl
Control
Threshold
0.001 ~F
~F
I
-=
0.01 ~F
Output
Gnd
1.0~F
11-50
1/2
MC3456
Discharge
I
Reset
VCC
0.01 ~F
112
27k
9.H
Reset
VCC
Gnd
S.O~F
Is.o~F
-=
Load
-=
Load
MOTOROLA ANALOG IC DEVICE DATA
Tape and Reel Options
In Brief ...
Motorola offers the convenience of Tape and Reel
packaging for our growing family of standard integrated circuit
products. Reels are available to support the requirements of
both first and second generation pick-ancl-place equipment.
The packaging fully conforms to the latest EIA-481A
specification. The antistatic embossed tape provides a
secure cavity, sealed with a peel-back cover tape.
Page
Tape and Reel Configurations ..................... 12-2
Tape and Reel Information Table ................... 12-4
Analog MPQ Table .............................. 12-5
II
MOTOROLA ANALOG IC DEVICE DATA
12-1
Tape and Reel Configurations
Mechanical Polarization
SOIC and MicrH
DEVICES
PLCC DEVICES
Typical
Typical
$$$$$$$$$
u][[ZJ]
User Direction of Feed
User Direction of Feed
DPAK and I)2PAK
DEVICES
User Direction of Feed
SOT-23 (5 Pin)
DEVICES
SOT4I9 (3 Pin)
DEVICES
SOT4I9 (5 Pin)
DEVICES
Typical
Typical
Typical
~
)l~ l~)
)~~o)
~
User Direction of Feed
12-2
~
User Direction of Feed
~
User Direction of Feed
MOTOROLA ANALOG IC DEVICE DATA
Tape and Reel Configurations
(continued)
To-92 Reel Styles
STYLE A
(Preferred)
Feed
STYLE E
~_."...,,..-_ _ _ _ _ _ _-'
Feed
Rounded side of transistor and adhesive tape visible.
Flat side of transistor and adhesive tape visible.
T0-92 Ammo Pack Styles
STYLE P
(Preferred)
STYLEM
Adhesive Tape On
TopSide
Adhesive Tape On
TopSide
Rounded Side
Flat Side
Carrier
Strip
Carrier
Strip
Flat side of transistor and
adhesive tape visible.
Rounded side of transistor and
adhesive tape visible.
Style P ammo pack is equivalent to Styles A and B of reel pack
dependent on feed orientation from box.
Style M ammo pack is equivalent to Style E of reel
pack dependent on feed orientation from box.
To-92 EIA Radial Tape in Fan Fold Box or On Reel
H2A
MOTOROLA ANALOG IC DEVICE DATA
12-3
Tape and Reel Information Table
Tape Width
(mm)
Devlces!lJ
per Reel
Reel Size
(Inch)
Device
Suffix
SD-a, SOP--8
SO-14
SO-16
12
16
16
2,500
2,500
2,500
13
13
13
R2
R2
R2
SO-16L, SD-a+8L WIDE
S0-20LWIDE
S0-24LWIDE
S0-28LWIDE
S0-28LWIDE
16
24
24
24
32
1,000
1,000
1,000
1,000
1,000
13
13
13
13
13
R2
R2
R2
R2
R3
Package
Micr0-8
12
2,500
13
R2
PLCC-20
PLCC-28
PLCC-44
16
24
32
1,000
500
500
13
13
13
R2
R2
R2
PLCC-52
PLCC--88
PLCC--84
32
44
44
500
250
250
13
13
13
R2
R2
R2
T0-226AA (T0-92)(2)
18
2,000
13
RA, RE, RP, or RM
(Ammo Pack) only
DPAK
16
2,500
13
RK
D2pAK
24
800
13
R4
SOT-23 (5 Pin)
8
3,000
7
TR
SOT--89 (3/5 Pin)
..
12
1,000
7
T1
(1) Minimum order quantity IS 1 reel. Distributors/OEM customers may break lots or reels at the" option, however broken reels may not be returned .
(2) Integrated circuits in TO-226AA packages are available in Styes A and E only, with optional "Ammo Pack" (Suffix RP or RM). The RA and RP configurations
are preferred. For ordering information please contact your local Motorola Semiconductor Sales Office.
12-4
MOTOROLA ANALOG IC DEVICE DATA
Analog MPQ Table
Tape/Reel and Ammo Pack
I
Package Type
Package Code
MPQ
Case 775
Case 776
Case 777
0802
0804
0801
lOOO/reel
500/reel
500/reel
Case 751
Case 751A
Case 751B
Case 751G
Case 751D
Case 751E
Case 751F
0095
0096
0097
2003
2005
2008
2009
2500lreel
2500/reel
2500/reel
1000/reel
1000/reel
1000/reel
1000lreel
PLCC
SOIC
Micr0-8
Case 846A
2500/reel
To-92
Case 29
Case 29
0031
0031
2000/reel
20001Ammo Pack
DPAK
Case 369A
2500/reel
D2PAK
I
SOT-23 (5 Pin)
I
Case 936
800/reel
Case 1212
3000/reel
SOT-89 (3 Pin)
I
Case 1213
looo/reel
SOT-89 (5 Pin)
I
Case 1214
MOTOROLA ANALOGIC DEVICE DATA
1000/reel
12-6
12-6
MOTOROLA ANALOG IC DEVICE DATA
Packaging Information
In Brief . ..
The packaging availability for each device type is indicated
on the individual data sheets and the Selector Guide. All of the
outline dimensions for the packages are given in this section.
The maximum power consumption an integrated circuit
can tolerate at a given operating ambient temperature can be
found from the equation:
TJ(max)-TA
PD(TA) = - - - RSJA(Typ)
where:
PD(TA) = Power Dissipation allowable at a given
operating ambient temperature. This must
be greater than the sum of the products of
the supply voltages and supply currents at
the worst case operating condition.
TJ(max) = Maximum operating Junction Temperature
as listed in the Maximum Ratings Section.
See individual data sheets for TJ(max)
information.
TA = Maximum desired operating Ambient
Temperature
RSJA(Typ)
Typical Thermal Resistance Junction-toAmbient
=
lEI
MOTOROLA ANALOG IC DEVICE DATA
13-1
Case Outline Dimensions
LP, P, Z SU~FIX
CASE 29-04
Plastic Package
(TO-226AAfTO-92)
ISSUE AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLUNG DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. DIMENSION FAPPUES BETWEEN P AND L.
DIMENSION DANDJ APPLY BETWEEN L AND K
MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
MIN
A
B
C
D
F
0.175
0.170
0.125
0.016
0.016'
0.045
0.095
0.015
.500
.250
G
H
J
K
L
N
P
R
V
--j~vr C
N
1,
INCHES
MAX
0.205
0.210
0.165
0.Q22
0.019
0.055
0.105
0.020
DIM
.105
0.100
0.115
0.135
IIILUIiETERS
MIN
MAX
4.45
5.20
422
5.33
3.18
4.19"
0.41
0.55
0.41
0.48
1.15
1.39
2.42
2.86
0.39
0.50
12.70
6.35
2.04
2.66
2.54
2.93
3.43
N
KC, TSUFFIX
CASE 221 A-06
Plastic Package
ISSUEY
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1962.
2. CONTROLUNG DIMENSION: INCH.
DIM
A
Q
B
C
D
F
G
H
J
K
L
N
Q
G
-I
13-2
D 3PL
N ~.J$\ 0.25 (0.010)®\ B ®\v\
R
S
T
U
INCHES
MIN
MAX
0.560 0.625
0J6Q 0A2Q
0.140 0190
0.020 0.045
0.13~
0.155
O.l00BSC
0260
0.012 0.045
0.500 0.560
0.045 0.070
0.200BSC
0.100 0.135
0.080
0.115
0.020 0.055
0.235 0.255
0.000 0.050
IIILUMETERS
MIN
MAX
14.23 15.87
9.86 10.66
3.56
4.82
0.51
1.14
353
3.93
2.54BSC
7.11
0.31
1.14
12.70 14.73
1.15
1.n
5.08BSC
2.54
3.42
2.92
2.04
0.51
1.39
5.97
6.47
0.00
1.27
MOTOROLA ANALOG IC DEVICE DATA
TH SUFFIX
CASE 314A-G3
Plastic Package
ISSUED
0Q
NOTES:
1. DIMENSIONING AND TOLEAANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHAll
NOT EXCEED 0.043 (1.092) MAXIMUM.
OPTIONAL
CHAMFER
,
Dill
A
B
C
D
5
E
F
G
J
K
L
G
Q
1$1 O,014(o.356)@lrl p @I
S
INCHES
MIN
MAX
0.572 0.613
0.390 0.415
0.170 0.180
0.025 0.038
0.048 0.055
0.570 0.585
0.067 BSC
0.015 0.025
0.730 0.745
0.320 0.385
0.140 0.153
0.210 0.260
8 0.605
MIWMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318 4.572
0.635 0.965
1.219 1.397
14.478 14.859
1.702BSC
0.381
0.635
18.542 18.923
8.128
9.271
3.556 3.886
5.334 6.604
11.888 12.827
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROlUNG DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCWDlNG PROTRUSION SHAll
NOT EXCEED 0.043 (1.092) MAXIMUM.
T, TV SUFFIX
CASE 3148-05
Plastic Package
ISSUEJ
DIM
A
B
K
C
D
E
F
G
1~
H
J
K
5
L
N
G
5X
0
S
U
1$IO.10(O.254)@lrlp@1
-T- ~~~G
TSUFFIX
CASE 314c-{)1
Plastic Package
l-1
ISSUE A
1 2 3 4 5
n
L
V
W
~-I~
E
NOTES:
1. DIMENSIONING AND TOlERANCING PER ANSI
Y14~M, 1982.
2. CONTROlliNG DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
DIM
A
B
C
D
E
G
J
K
L
Q
MOTOROLA ANALOG IC DEVICE DATA
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.572
0.613 14.529 15.570
0.390 0.415 9.906 10.541
0.170 0.180 4.318 4.572
0.025
0.038 0.635 0.965
0.048 0.055 1.219 1.397
0.850 0.935 21.590 23.749
O.067BSC
1.702BSC
0.166 BSC
4216BSC
0.015 0.025 0.381
0.635
0.900
1.100 22880 27.940
0.320 0.385 8.128
9.271
0.320 BSC
8.128BSC
0.140 0.153 3.556 3.886
0.620
1 .7
0.466 0.505 11.888 12.827
0.735
18.669
0.090 0.110 2.286 2.794
INCHES
MIN
MAX
0.610 0.625
0.360 0.420
0.160 0.190
0.020 0.040
0.035 0.055
0.067BSC
0.015 0.025
0.500
0.355 0.370
0.139 0.147
MILLIMETERS
MIN
MAX
15.59 15.88
9.65
10.67
4.06
4.83
0.51
1.02
0.89
1.40
1.702BSC
0.64
0.38
12.70
9.02
9.40
3.53
3.73
13-3
lEI
T, T1 SUFFIX
CASE 314D-03
Plastic Package
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANS1
Y14.5M.1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAM BAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHAU.
NOT EXCEED 10.92 (0.043) MAXIMUM.
DIM
A
B
C
D
E
G
H
J
K
L
Q
G
U
S
INCHES
MIN
MAX
0.572
0.613
0.390
0.415
0.170
0.180
0.025
0.038
0.048
0.055
0.067BSC
0.087
0.112
0.Q15
0.025
1.020
1.065
0.320 0.365
0.140
0.153
0.105
0.117
0.543
0.582
MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.5414.318
4.572
0.635
0.965
1.219
1.397
1.702BSC
2.210
2.845
0.381
0.635
25.908 27.051
8.128
9.271
3.556
3.886
2.657
2.972
13.782 14.763
1*1 0.356 (0.014)®1 TI Q ® 1
OT-1 SUFFIX
CASE 369-G7
Plastic Package
(DPAK)
ISSUEK
V
t
L1
S
".2 3
l±l
SEATING
PLANE
f
:3T
A
3i
K
-.l
F
11~'
,jlH
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.090 BSC
0.034
0.040
0.Q18
0.023
0.350
0.380
0.175
0.215
0.050 0.090
0.050
0.030
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
2.19
2.38
0.69
O.BB
0.84
1.01
0.84
1.19
2.29BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.46
1.27
2.26
0.77
1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
DIM
A
B
C
0
E
F
G
H
J
K
L
R
S
U
V
Z
13-4
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.088
0.084
0.035 .
0.027
0.033
0.040
0.037
0.047
0.180BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090BSC
0.175
0.215
0.020
0.050
0.020
0.030
0.050
0.138
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.84
1.19
4.58BSC
0.87
1.01
0.46
0.58
2.60
299
2.29BSC
4.45
5.46
0.51
1.27
0.51
0.77
1.27
3.51
MOTOROLA ANALOG IC DEVICE DATA
DP1, N, P, P1 SUFFIX
CASE 626-QS
Plastic Package
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARAllEl.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SOUARE CORNERS).
3. DIMENSIONING AND TOlERANCING PER ANSI
Y14.5M,1982.
ISSUE K
.~
DIM
A
B
C
D
F
NOTE 2
G
H
J
1
K
L
M
N
MILLIMETERS
MIN
MAX
10.16
~
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.6288C
10°
0.76
1.01
INCHES
MIN
MAX
0.400
0.240 0.260
0.155 0.175
0.015
0.020
0.040 0.070
O.IOOBSC
0.030 0.05
0.008 0.012
~3~
O.~
O.~
0.300BSC
10°
0.030 0.040
N, P, N-14, P2 SUFFIX
CASE 646-06
Plastic Package
ISSUEL
t
8
".
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAl.
B
t-n""'t"T"'t"T"t"T"1:7"""t'T"l:':7r,-.L
.1
DIM
A
B
D
1
F
G
H
K
K
L
N
DP2, N, P, PC SUFFIX
CASE 64S-08
Plastic Package
~
QJ!Z!l
0IOO88C
0.005
0.008
0.01
0.115
0.135
30 asc
0°
1°
0.05 0.039
O.O~
MILUMETERS
/,1J1l
lB.16
6.10
3.69
0.38
~
MA
19.56
6.60
4.69
0.53
J!l.
2.54BSC
2.4
1.32
0.20
0.38
2.92
3.43
62 SC
0°
10°
0.39
1.0
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,I982.
2. CONTROlliNG DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARAllEL
4. DIMENSION a DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAl.
ISSUER
I~I O.25(O.010)®lrIA ®I
MOTOROLA ANALOG IC DEVICE DATA
INCHES
MIN . MAX
0.715 0.770
0.240 0.260
0.145
0.185
0.015
0.021
INCHES
MILLIMETERS
DIM .l!!I!l ..MAl
MIl! MA
9.5
A 0.:M!L ~J1L ~
B 0.250 0.20
B.
S.B
C 0.145 0.175
1.44
3.'
.015
1
o.
F o.
0.0
1.
1.
G
1
S
1 7asc
0 0
o.o~
0.1
038
~
K .0.1111. ~1~11.
2£ ~
L 0.295 0.305
.50
7.74
M
0°
10°
0°
10°
0.020 0.04
0.51
1.01
13-5
B, P, P2, V SUFFIX
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1962.
2. CONTROLUNG DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. INTERNAL LEAD CONNECTION BETWEEN 4 AND
5. 12 AND 13.
CASE 648C-03
Plastic Package
(DIP-16)
ISSUEC
DIM
A
B
C
D
E
F
J
K
M
L
M
N
INCHES
MIN
MAX
0.740 0.640
0.240 0.280
0.145 0.165
0015 0.021
O. sse
0.040
0.70
0.100 BSC
O.ooe 0.D15
0.115 0.135
0.300 BSC
O·
10·
~.015
0.040
MILLIMETERS
MIN
MAX
16.60 21.34
6.10
6.60
3.69
4.69
0.53
M8
1. 7B C
1.02
1.76
2.54B C
0.20
0.38
2.92
3.43
7.62 BS
O·
10·
_0.39
1.01
1$1 0.13(0.005)@lrIA ®I
PSUFFIX
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M. 1962.
2. CONTROLUNG DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION A AND B DOES NOT INCLUDE MOLD
PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 (0.010).
6. ROUNDED CORNER OPTIONAL.
CASE 648E-Q1
Plastic Package
(DIP-16)
ISSUE 0
I DIM
A
B
C
D
F
G
11
INCHES
MIlL
MIWMETERS
MIIi --"!A
la.80 1l!.30
B.
6.80
44
....MAl[
0.740 ~76!t
0.245 0.260
4
O. 15 0.021
~
0.39
O.
~
1.JZ.
0.100BSC
2.54 BSC
W~C
~IU!lK
J
o.ooe
K
0.20
0.015
0.40
o 1
~~
M
5
O·
O·
5
6S
R
S
.
B
.6
0.1!l§.
0.210.
8
7
1·
0.8
Mi
1$10.25 (0.010)@lrl B ®I A ®I
PSUFFIX
CASE 649-03
Plastic Package
P
NOTES:
1. LEADB WITHIN 0.13 (0.005) RADIUS OFTRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
ISSUE D
Q
MILLIMETERS
-.W
5
~6
05
BS
S
16
24
0
K
£
-.l.4.ii.
.1L
--'I _Ml
P
0
1
13-6
1~
JlJ
2
47
C
INCHES
1
..1U2..
0
1
110..
.Jl.!1l.Q.
1 •
~ JlJ
~
L02.~~ ~I~
o1
O.
MOTOROLA ANALOG IC DEVICE DATA
A, e, N, P SUFFIX
CASE 707-02
Plastic Package
ISSUEC
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FOAMED PARAllEL
3. DIMENSION B DOES NOT INCLUDE MOLD
FlASH.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
PSUFFIX
CASE 710-02
Plastic Package
ISSUE B
MILLIMETERS
MIN
MAX
22.22
23.24
6.10
6.80
3.58
4.57
036
0.56
127
1.78
2.54 BSC
1.02
1.52
0.20
0.30
2~2
3.43
7.62 esc
15°
0°
0$1
1.2
INCHES
MIN
MAX
0.875 0.915
0.240 0.280
0.140 0.180
0.014 0.022
0.05Jl 0.070
0.100 BSC
0.040 0.060
0.008 0.012
0.115
0.135
0.300BSC
0°
15°
0.040
0.02
NOTES:
1. POSITIONAL TOLERANCE Of LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
DIM
A
S
C
0
F
G
H
J
K
L
Pol
N
MILUMETERS
MIN
MAX
36.45 37.21
13.72 14.22
.94
5.08
.56
.36
1.
2.5
.65
2.16
0.20
0.38
2.92
3.43
1 .24B
1°
°
0.51
1.02
esc
INCHES
MIN
MAX
1.435 1.465
0.540 0.580
0.155 0.200
O. 4 0.022
0.1 BSC
0.065 0.065
0.008 0.Q15
0.115
.135
O.
B
15°
°
0.020 0.040
PSUFFIX
CASE 711-D3
Plastic Package
ISSUE C
NOTES:
1, POSITIONAL TOLERANCE OF LEADS (0), SHALL
BE WITHIN 0,25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION S DOES NOT INCLUDE MOLD FlASH.
DIM
A
S
C
F
J
L
MOTOROLA ANALOG IC DEVICE DATA
MIWMETERS
MIN
MAX
51.69 52.45
13.72 14.22
5.08
O.
0.56
2
1.
2.8
0.20
0.8
2,92
.43
1 ,24 SC
°
°
0, 1
1,0
INCHES
MIN MAlt
2.035 2,065
0.540 0.560
155
'.200
.014
.022
O.
.1
0.085
.08
0.008
.015.
0: 15 0,135
O,BOOBSC
15°
0°
02
lEI
13-7
M_
F, P, P-3 SUFFIX
CASE 724-03
Plastic Package
(NDIP-24)
ISSUE 0
I"
NOTES:
1. CHAMFERED CONTOUR OPTIONAL.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARAllEL.
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.SM, 1982.
4. CONTROLLING DIMENSION: INCH.
1
lJ
. r±l
1~:::::::::::loo
t
~
~~,
C
INCHES
MIN
MAX
1.230 1.26
0.: 50 0.270
0.145 0.175
0.015 0.020
0.050BS(
0.040 O.MIl
A
B
C
D
E
F
2!i4e.qc
O~Mii""
G
O. 7
.012
0.110 0.140
0.300BSC
0°
15°
0.020 0.040
K
-LJ 24~ '~M
MILUMmRS
IN
MAX
1
2.1
6.35
B.85
3.89
4.44
038
0.51
1.27 BSC
1.02
1,;'
M
N
0.1
.3
2.80
3.55
7.62BSC
O·
15°
0.51
1.01
1-$1 O.25(O.010)@ITI B @j
D 24PL
j-$j O.25(O,010)@jTjA @j
H, P, DP SUFFIX
CASE 73S-03
Plastic Package
ISSUE E
I-
~1
L::.T;J
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
-I
r±l
f~:::::::::1J
INCHES
I I]JU . "Iii -Ii
A
j
G
LE- ~t
~J!
F
K
L
O,M'I1!SC
C
-1fB1
,C
OIQIQQQlmQQQR~~ J
II UU tm~.u II ! •
1. 0 1.
0.240 0.2
O. 0 0.1
0.015 0.0
0.050BS(
0.050 0.070
0.10e BSC
0.008 0.015
0.110 0140
0
E
F
\
G
J
---.I V"
0°
15°
MILLIMmRS
IN
5.
27.1
6.10
B.BO
0.5
1.2: esc
1.27
n
2.5 esc
0.21
0.3"
2.80 -(55
62--..r
0°
1°
1
O.
J2DPL
l-$jO,25(o.o10)@jTjB@j
D 2DPL
j-$IO,25(O,010)@ITIA @j
D, D1, D2 SUFFIX
CASE 751-05
PlastiC Package
(SO-B, SOP-8)
ISSUE R
B~
1
Dili
W
E" .~tl"51i11"~1 ~
00 "
f8
~c
5
t~~
h, ••
A
hErboodA1D"~B"
[SEATING
PLANE
~
I-$j 0.25 @jcl B ®j A® 1
13-8
r:~
NOTES:
1, DIMENSIONING AND TOLEAANCING PEA ASME
Y14,SM,19i4.
2. DIMENSIONS ARE IN MilliMETERS.
3. DIMENSION DAND E DO NOT INCLUDE MOLD
PROTRUSION,
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6, DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION, ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EKCESS
OF THE BDIMENSION AT MAXIMUM MATERIAL
CONDITION,
DIM
01
&51
. A1
MILUMmAS
MIN
MAX
1.35
1.75
10
0.25
~
0
4
5.
7
It-
o
h
•
0.40
°
0
0.80
1.2'
°
MOTOROLA ANALOG IC DEVICE DATA
DSUFFIX
CASE 751A-Q3
Plastic Package
p=fi--n--ul
(SO-14)
ISSUE F
"
1T
1
,~IO,,(o."O)@IB@1
m,
-8-
I@
~ --I '--
U--ILULL1L[
-I G I-
14#
1
P7PL
C
RX.5.'
F
!t
t
rn- &CJCJCJCJCJCJ9
--J-I.-- - - - - K
SEATING
r
, ...
M
D 14 PL
CASE 751 B-05
Plastic Package
18
(SO-16)
9
ISSUEJ
I-B-I P 8PL
__
:rt~JU lLu~IO~(MlO}@IB~
1S#
1
l±l Sfp'(l~~
;r
t , . . !f:
~CJ
CJ~~
:JC ----Tt
R(4;~!
CJ CJ CJ CJCJ
M
D 18PL
.JFl
(SO-20L, S0-20)
.IA
RRR
J
~ AHA ;liCfl
ISSUE E
1
~8~¥1'[1:I1:I1:I1:I
20X D
1
1'~P
~$lo.010(o.25)@1 sewl
1$
20.",
K
M
P
R
l
1$IO.010(O.25)@l r A ® IB®I
[did
.!J
MOTOROLA ANALOG IC DEVICE DATA
-T-
K
~E:~rG
DIM
A
B
C
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
'.00
1.75
1.'"
O.
0.49
0.40
1.25
1.27BS
0.25
0.19
0.10
0.25
o·
7·
5.80
6.20
0.25
0.50
J
INCHES
MIN
MAX
0"" 0.39
0.150
0.157
~ 0.068
O. 1. 0,019
0.Q16 0.049
0.050BSC
0.008
onll9
0.004
0.009
O·
7·
0:'29 0.244
0.010 0.019
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Yl'.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
S. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
•. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
6. DIMENSION D DOES NOT INCLUDE
DAM BAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXDESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
DIM
A
...........
M
INCHES
MIN
MAX
0.337
0.344
0.150 0:157
0.054 0.068
0.01. 0.019
0.016
0Ji4e
0.050 BSC
0.008 0.009
0.004
0.009
O·
7·
0.228 0.244
0.010 0,019
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE 0 DIMENSION AT
MAXIMUM MATERIAL CONDITION.
Fl-
&
mmtm~1 I ~fr
-I !--,8X G
MILLIMETERS
MIN
AX
8.75
8.56
.80
4.00
1.35
1.75
0.49
0.35
0.40
1.25
1.27 ESC
.19
0.25
0.10
0.25
o·
7·
5.80
6.20
0.25
0.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Yl'.5M,1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. ~~I~~~. MOLD PROTRUSION 0.15 (0.006)
F
1$IO.25(O.010)@lrIS®IA®1
CASE 751 D-04
J
J
I~OlT~--n';l~
f
DSUFFIX
Plastic Package
DIM
A
B
C
0
F
G
1$lo.25(O.010)@lrIB®IA®1
PLANE
DW, FP SUFFIX
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
C
0
F
G
) 11.
K
M
P
R
MILUMETERS
MIN
MAX
12.8
12.
INCHES
MAl
MIN
0
0.51
2.35
2.85
O.
O.
0.90
0.50
1.27 BSC
0.25
0::"
0.10 n,?i<
O·
7·
10.
10
.25
0.7
0.093
0.01.
0.020
0.051
0.Q10
).004
O·
O. 5
.1
0.1
0.019
0.035
sse
0.012
0.009
7·
a 15
13-9
lEI
DWSUFFIX
CASE 751 E-04
Plastic Package
NOTES:
1. DIMENSIONING AND TOlERANCING PER ANSI
YI4.5M,I982.
2. CONTROlliNG DIMENSION: MilliMETER.
3. DIMENSIONS A AND BDO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF 0 DIMENSION AT MAXIMUM
MATERIAL CONDITION.
(SO-24L,
SOP (16+4+4)L)
ISSUE E
DIM
A
B
C
0
F
G
J
K
M
P
R
DWSUFFIX
CASE 751F-04
MILLIMETERS
MIN
MAX
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.29
0.13
O'
B'
10.05 10.65
025
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009
0,013
0.005
0.011
O'
8'
0.395 0.415
0.010
0.029
lW
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 19B2.
2. CONTROlliNG DIMENSION: MILLIMETER.
3. DIMENSION AAND B DO NOT INCLUDE
MOlD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
DAM BAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF 0 DIMENSION
AT MAXIMUM MATERIAL CONDITION.
PlastiC Package
(SO-28L, S010-28)
ISSUE E
ll!!
MILLIMETERS
JoI!N
1780
A
B
M
lB.05
.60
7~
2,35
2,65
0,4
,41
0,9
1,27 SC
0,23
032
,13 ~
B'
i'
P
MJ
c
F
G
J
0
DWSUFFIX
CASE 7510-02
INCHES
...MM ....M!!i ...MAX.
=
0.01
0,2!i
0, 93
,0
0,01
0.711
om
0,104
0019
,035
C
0,09
M13
@§.
0.Qll
,
i'
~ ~m
o 29
0, 0
NOTES:
1, DIMENSIONING AND TOLERANCING PER ANSI
YI4,5M,19B2,
2, CONTROLLING DIMENBION: MILLIMETER,
3, DIMENSIONS AAND B DO NOT INCLUDE MOLD
PROTRUSION,
4, MAXIMUM MOLD PROTRUSION 0,15 (0.006) PER
SIDE,
5, DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION, ALLOWABLE OAMBAR
PROTRUSION SHALL BE 0,13 (0.006) TOTAL IN
EXCESS 01' 0 DIMENSION AT MAXIMUM
MATERIAL CONDITION,
Plastic Package
(SO-16L, SOP-16L,
SOP-8+8L)
ISSUE A
MILLIMm~
1,11,45~
93
,04
5
--.l
~iji;:;;ori;t~;;;;;;n~~L +L±J
~ ~14X 0
13-10
[ K
SEATING
PLANE
,7
...Q;
0
0, 9
060
~
, o 5,
~10
...11!
:1.!.
0004
iL'
o 09,
5
R
0,25
0,5
,0
1
0,
MOTOROLA ANALOG IC DEVICE DATA
o SUFFIX
CASE 751 K-01
Plastic Package
(So-16)
ISSUE 0
t
I-B-I
L
lS#
1
~
B
~'--III~lInlnll-mll m
Ci
e.
'"
"!
C>
p
~~~_~_~~~_~_~_~~
1
& .
'®s
I
r.---+-----t
--I Gi--
"
-I
~
'-'--
L
C~~
fJ J~
----1
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1962.
2 CONTROWNG DIMENSION: MILLlMffiR.
3 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4 MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5 DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE 0 DIMENSION AT MAXIMUM
MATERIAL CONDITION.
i-f
F
DIM
A
B
C
D
F
R'ti'1r-\,
G
t=.6t$.,y
..........
l±J~f:~~G
J
K
P
R
J
14XO
1$1 Q,25(O,010)@ITIA ®I B®I
OW SUFFIX
CASE 751 N-01
Plastic Package
(SOP-16L)
ISSUE 0
16.
1
"~'1l
~f'
1: ~~~~~~Ll
JL
1$lo.010(O.25)@IB @I
13XO
1$1 O,010(O,25)@ITIA ®I B®I
~
B!rt,~
K
PLANE
[d/8
~Fl)j r-
B
b..lifTJlb
M-
INCHES
MIN
MAX
0.368 0.3
0.150 0.157
0.054 0.OS8
0.014
0.019
0.D16 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0'
7'
0.29 0.244
0.010 0.019
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1962.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS AAND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION 0 DOES NOT INCLUDE DAM BAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF 0 DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM
RX45 '
MILLIMffiRS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27BSC
0.19
0.25
0.10
0.25
7'
0'
5.80
6.20
0.25
O.SO
D
F
G
K
M
P
T
MILLIMETERS
MIN
MAX
10.15
0.45
7.
.60
.35
.85
0.35
.49
.50
O.
1. Bse
0.25
0.32
0.0
0,25
0'
7'
10.5 10.55
0.25
0.75
3.81 Bse
INCHES
MIN
MAX
0.400
0.411
O.
299
0.093
O. 4
0.01
019
O.
O.
0.050SSC .
0.,)10 0.012
0.004 0.009
0'
7'
0.395
0.415
0.010
0.029
1
0.150BSC
ex G
MOTOROLA ANALOG IC DEVICE DATA
13-11
CASE 762-01
Plastic Medium Power Package
(SIP-9)
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5,1982.
2. CONTROLLING DIMENSION: MILLIMETER.
Q
1$10 0.25 (0.010)®1 TI A ®I
DIM
A
B
C
0
E
F
G
H
J
K
M
N
Q
JL
J 1$10 0.25 (0.010)®ITI
o 9PL
c @I
H
X
1$10 0.25(0.010)@ITIA @I
FN SUFFIX
CASE 77S·02
Plastic Package
(PLCC-20)
ISSUE C
•
Y
BI$~·007 (0.1809ITIL-M@IN@1
UI$p·007(0.18~ITIL-M@IN@1
G~$9.010 (0.25aDlITIL-M@IN@1
20
R
S
U
V
W
VIEWD-O
~--+f--AI$9·007(0.1809ITIL-M@IN@1
Z
E
~
H 1$~.007(0.1809ITIL-M@IN@1
t
K1
.---:J
VIEWS
F
G
H
K
R
i-FIM·007(0.1809I TIL-M@IN@1
V
W
X
INCHES
MI
MAX
O.
O.
.15 0.180
0.0
0.11
0.013 0.019
0,051 IBSC
0.028 0.032
0.020
0.025
0.360 0.58
0.04
0.042,
0.042
Y
Gl
1
13-12
INCHES
MIN
MAX
0.873 0.897
0.252 0.260
0.135 1.143
0,015 0.021
0.368 0.377
0.055 0.062
0.100BSC
0.059 0.067
0.014 0.015
0.155 0.165
30 Q BSC
0.099 0.1
0.124 0.135
0.535
0.547
0.064 0.076
0.866 0.874
0.021
0.029
0.113 BSC
0.025 0.029
0.110
0106
NOTES:
1 DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION Gl, TRUE POSITION TO BE
MEASURED AT DATIUM - T-, SEATING PLANE.
3. DIMENSIONS RAND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0,010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
YI4,5M,1962.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS RAND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION HDOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAM BAR INTRUSION(S) SHALL NOT CAUSE
THE HDIMENSION TO BE SMALLER THAN 0.025
(0.836).
1M
A
B
ilil-----<...r-R 1$9·007 (0.1809ITIL-M@IN@1
MiLLIMETERS
MIN
MAX
2240 23.00
6.40
6.60
3.45
3.65
0.55
0.40
9.35
9.60
1.40
1.60
2.54BSC
1.51
1.71
0.360 0.400
3.95
4.20
3QoBSC
2.50
2.70
.15
3.45
13.60 13.90
1.85
.95
22.00 22.20
0.55
0.75
2.89BSC
0.65
0.7
.70
2°
0.31
O.
0
0.048
0.066
0.00
10°
0.330
~
~~
4,
2.
7
.79
.48
0.88
'.51
.84
7BSI
0.81
,04
1. 7
2°
.21
.21
1.42
0.60
10°
.38
MOTOROLA. ANALOG IC DEVICE DATA
FNSUFFIX
CASE 776-02
Plastic Package
(PLCG-28)
ISSUE D
•
BI$-I 0.007 (0.180)@ITI L-M® 1N®I
YBRK
~
1"
-r----=----irL.i
~pD
VIEWD-D
~----~ A 1$-1 0.007 (0.180)@ITI L-M® 1N®I
1Io-------oof+-- R 1$-1 0.007(0.180)@ITI
rtE~~.-.-l
L-M®I N®I
i- F 1$-1 0.007(0.180)@ITI L-M®I N®I
VIEWS
1$-1 0.010(0.250)®ITI L-M®I N®I
NOTES:
1. DATUMS -l-, 411-, AND -N- DETeRMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC SCDY AT MOLD PARTING LINE.
2. DIMENSION Gl, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS RAND UDO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.
8. CONTROLLING DIMENSION: INCH.
8. THE PACKAGE TOP MAY BE SMALLER THAN
THe PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS RAND UARe
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTER LEAD
FLASH, BUT INCUUDING ANY MISMATCH
BETWEEN THe TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMeNSION HDOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE HDIMeNSION TO BE
SMALLER THAN 0.025 (0.835).
MOTOROLA ANALOG IC DEVICE DATA
VIEWS
INCHes
MILUMETeRS
I
DIM
A
B
C
e
F
O.~
O.~
12~
12.5L
0.485
0.1
0.1
1
J.495
0.180
12.S2
4.20
12.57
4.57
2.79
04
.032
.88
0.81
B
143
1.43
1.07
1.
11.5
I1.B8
1.21
H
1
J
Jl
R
V
W
_O~
0.·
0.,
0 2
0.042
Y
Z01
1
~.
0.,110
0.040
O.
0.020
ilL·
J.430
.
10.42
.02
1.42
.50
~
10.S!
13-13
FN SUFFIX
CASE777-D2
B 1$lo.007(O.180l®1 TI
Plastic Package
L-M® IN ®I
ul$lo.007(O.180l®1 TI L-M® IN ®I
(PLCC)
ISSUEC
G1
VIEWD-D
1$lo.010(O.25)®ITI L-M®IN®I
~I-F
""'$"I-O.O--07--(O-.18--ol
I
®::::-r:1T"I-L---M"®"I--N®~SI
VIEWS
1$lo.010(O.25)®ITI L-M® I N®I
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION Gl, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS RAND U DO NOT INCWDE MOUD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,19B2.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BonOM BY UP TO 0.012
(0.300). DIMENSIONS RAND UARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTIOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAM BAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.835).
DIM
A
8
C
E
F
G
H
J
K
R
INCHES
MIN
M
.6
O.
0.685 0.895
0.1
0.1
0.090 0.110
0.013 0.019
>.051 BSC
0.026 0.032
0.020
0.025
0.6
0
V
0.042~
W
X
0.042
0.042
Y
Z
Gl
Kl
2'
0.610
.04
0.048
0.048
0.056
0.020
10'
0.630
MILLIMETERS
MIN
MAX
1740
.65
17.40 17.65
42
4.
2.29
2.79
0.48
033
I.27BSC
0.66
O.Bl
051
0.64
161
1.
.51
1~
107
121
1.07
1.21
.07
1.42
050
10'
2'
1550 1.
1.02
NOTES:
6 DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,19B2.
7 CONTROLLING DIMENSION: MILLIMETER.
B DIMENSIONS A AND B DO NOT INCLUDE MOUD
PROTRUSION.
9 MAXIMUM MOLD PROTRUSION 0.15 (0.008) PER
SIDE.
10 DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.006) TOTAL IN
EXCESS OF THE 0 DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MSUFFIX
CASE803C
PRELIMINARY
Plastic Package
20
S
10PL
1$1 0.13 (0.005)®1 B @I
DIM
A
MILLIMETERS
MIN
MAX
12.35 12.BO
5.10
5.45
O.
M
N
S
0
12.40'
I.llt
1~
0.59
O.Bl
0.1
0.: 7
1.10
1.50
0.05
0.20
0'
0
7.40
B.20
,
INCHES
MIN
MAX
0.4BB 0.504
0.201
>.215
n .OBI
0
0
O.
0.00
023
0.007
0.043
0.01
,
.02
0291
~O55
0.032
011
0.059
0.008
10'
0.323
'APPROXIMATE
13-14
MOTOROLA ANALOG IC DEVICE DATA
TV SUFFIX
CASE 821 C-04
Plastic Package
(15-Pin ZIP)
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1962.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION RDOES NOT INCLUDE MOLD FLASH
OR PROTRUSIONS.
4. DIMENSION BDOES NOT INCLUDE MOLD FLASH
OR PROTRUSIONS.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.010 (0.250).
6. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.003 (0.076) TOTAL IN EXCESS OF THE 0
DIMENSION. AT MAXIMUM MATERIAL CONDITION.
15
DIM
A
B
C
0
E
G
H
J
1$10.010(0.254)@ITI plo®1
1$1 0.024 (0.610) @I TI
TSUFFIX
CASE 821 D-03
K
L
M
R
S
U
V
Y
INCHES
MIN
MAX
0.664 0.694
0.7B4 0.792
0.173 0.181
0.024 0.031
0.058 0.062
.050 BSC
0.169 BSC
0.018 0.024
0.700 0.710
0.200 BSC
0.148 0.151
0.416 0.426
0.157 0.167
0.105
0.115
0.868 REF
Q.625
0.639
MILLIMETERS
MIN
MAX
17.374 17.627
19.914 20.116
4.395
4.597
0.610 0.787
1.473 1.574
1.270B C
4.293 BSC
0.458 0.609
17.780 18.034
5.080 BSC
3.760 3.835
10.567 10.820
3.988 4.242
2.67 2.921
22.047 REF
15.75 16.231
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION RDOES NOT INCLUDE MOLD FLASH
OR PROTRUSIONS.
4. DIMENSION BDOES NOT INCLUDE MOLD FLASH
OR PROTRUSIONS.
5. MOUD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.Q10 (0.250).
6. DELETED
7. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.003 (0.078) TOTAL IN EXCESS OF THE 0
DIMENSION. AT MAXIMUM MATERIAL OCNDITION.
Plastic Package
ISSUEC
15
Q
I-L-I
C
0
INCHES
MIN
MA
0.881
0.694
0.7
0.792
0.1
81
4
.03
F
00
01
A
B
G
H
J
Q
V
MILLIMETERS
MIN ~AX
.298 17.627
19.914 20.18
:97
439
0
.7
1.47
4
0.40
0 4
.270
23
.050 C
0 B
2
0.018
024 0.418 0.B09
1.08B 127.38
7.584
J78
0.1 8 0.151
3.760 3.835
8
0 B
2 94B
.50 EF
.77 EF
1$10.024(0.610)@ITI
MOTOROLA ANALOG IC DEVICE DATA
13-15
FTBSUFFIX
CASE 8240-01
Plastic Package
(TQFP--44)
ISSUE 0
34
OETAILAA
> @
~
;
~
PLATlN~ASE METAL
t~=N
tLo--Jt
!$! O.20(O.OO8)@!AC!T-U®!Z®!
SECTION AE-AE
!$! O.20(O.008)@!AC!T-U®!Z®!
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,198.2.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB-IS LOCATED AT 9OTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC 90DY AT THE
9OTTOM OF THE PARTING LINE.
4. DATUMS - T-, -U- AND -Z- TO BE DETERMINED AT
DATUM PLANE -AB-.
5. DIMENSIONS SAND V TO BE DETERMINED AT
SEATING PLANE -AG-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE D DIMENSION TO EXCEED 0.530
(0.021).
MIL
HE!
1m
0.1
0.1
1.40
1.30
0.,
".
~o
,"7
12'REF
0.160
REF
0.004 I 0.006
. 5'
- 5'
100-
VIEWAO
O.
REF
13-16
.
,
12'REF
MOTOROLA ANALOG IC DEVICE DATA
FBSUFFIX
CASE 824E-02
Plastic Package
(QFP)
ISSUE A
44
S--------I
G~
1$1 0.20 (O.OOB)® 1TIL-M®I N®1
J1
!
G
f
VIEWY
@)
@)
z
z
@)
::;:
...'..
I-
>®
3PL
~-.~
J
<0
0
0
eo
"!
0
$
B1
tLD-It
1$1 0.20(0.00B)®lriL-M®1 N®I
SECTION J1-J1
44PL
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -IHS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OFTHE PARTlNG LINE.
4. DATUMS -l-, -M- AND -N- TO BE DETERMINED
AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE-T-.
6. DIMENSIONS A AND B DO NOTiNCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE-H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.530 (0.021).
DIM
A
B
C
D
E
F
G
J
VIEWP
MOTOROLA ANALOG IC DEVICE DATA
K
M
S
V
W
Y
A1
81
C1
R1
R2
81
82
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
9.90 10.10 0.390 0.398
9.90 10.10 0.390 0.398
2.00
2.21
0.079 0.087
0.30
0.45 0.0118 0.0177
2.00
2.10 0.079 0.083
0.30
0.40 0.012 0.D16
O.BOBSC
0.031 BSC
0.13
0.23 O.
0.009
0.65
0.95 0.026 0.037
10'
5'
10'
5'
12.95 13.45 0.510 0.530
12.95 13.45 0.510 0.530
0.000 0.210 0.000 0.006
10'
5'
10'
5'
0.450 REF
0.018 REF
0.130 0.170 0.005 0.007
1.BOOREF
0.063 REF
0.130 0.300 0.005 0.012
0.130 0.300 0.005
0.012
10'
10'
5'
5'
0'
7'
0'
7'
III
13-17
FBSUFFIX
CASE 840F-Q1
Plastic Package
ISSUE 0
64
1
e
tT-·t-·-Z-
1
~
~
- ::-r-
e
N
(.)
V
-
s,
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M. 1982.
2. CONTROLLING DIMENSION: M1LUMETER.
3. DIMENSION A DOES NOT INCWDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROmUSION.INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
DIll
A
B
C
0
G
H
J
K
L
MILLIMETERS
MIN
IIAX
2.90
3.10
2.90
3.10
1.10
0.25
0.40
O. BSC
0.05
0.15
0.13
0.23
4.75
5.05
0.40
0.70
INCHES
IIJN
IIAX
0.114
0.114
0.122
0.122
0.043
0.016
-
0.010
.026
0.002
0.005
0.187
0016
0.006
0.009
0.199
0.028
lEI
MOTOROLA ANALOG IC DEVICE DATA
13-19
FBSUFFIX
CASE848B-G4
Plastic Package
(TQFP-52)
ISSUEC
52
L-----+I
~
L_
®
®
®
®
c
c
'"
.l:
'"
.l:
0
® ~ >®
00:I:
~ §'
e. e.
~ '"
ci
e.
-$- ~
-$-
0
0
0
0
0
~1
A-, -B-,
-0-1
DETAIL A
0
C\I
ci
/-$-/ 0.20 (O.008)®/C/ A-B® Io®/
C
SECTIONB-B
~.10(0.OO4)/
-C-
DETAILC
SEATING
PlANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,I982.
2. CONTRCLLiNG DIMENSION: MIIl.IMETER.
3. DATUM PLANE -I+-IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -II- AND --D- TO BE DETERMINED AT
DATUM PLANE-I+-.
5. DIMENSIONS S AND VTO BE DETERMINED AT
SEATING PLANE-C-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PRCTRUSION. ALLOWABLE PRCTRUSION IS 025
(0.010) PER SIDE. DIMENSIONS AAND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -Ii-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PRCTRUSION. AIl.OWABL£ DAMBAR PRCTRUSION
SHAll. BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
DIM
A
B
D
E
F
G
H
J
K
L
II
N
Q
R
S
T
U
V
W
X
13-20
MILUIIIETERS
MIN
MAX
9.90
10.10
9.90 10.10
2.10
2.45
0.22
0.38
2.00
2.10
0.22
0.33
0.65 BSG
0.25
0.13
0.23
0.65
0.95
7.80 REF
5°
10°
0.13
0.17
7°
0°
0.13
0.30
12.95 13A5
0.13
0°
12.95 13.45
0.45
0.35
1.6 REF
INCHES
MIN
MAX
0.390 0.398
0.390 0~98
0.053 0.096
0.009 0.015
0.079 0.053
0.009 0.013
0.026BSG
0.010
0.005 0.009
0.037
0.0
0.307 REF
5°
10°
0.005 0.007
0°
7°
0.005 0.012
0$ 0 0.530
0.005
0°
0$10 0.530
0.014 0.018
0.053 REF
.MOTOROLA ANALOG IC DEVICE DATA
FBSUFFIX
CASE 8480-03
Plastic Package
ISSUEC
52
VIEWY
PLATING~ BASE METAL,
~~j
tl- o-lf
1$1 O.13(O.005)®lrl L-M®I N®I
14----00---_..
SECTION AB-AB
14-----~------..
ROTATED 90· CLOCKWISE
~
4X9~1tF' lolo.10(O,OO4)l r l
RR
:tf1nnnnnonn~Ji~ f
4X93 . . . (
PLANE
\.-
VIEWAA
NOTES:
VIEWAA
MOTOROLA ANALOG IC DEVICE DATA
1, DIMENSIONING AND TOLEflANCING PER ANSI
YI45M.I982.
2. CONTROLLING DIMENSION: MILLIMffiR.
3, DATUM PLANE -ll-IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OFTHE PARTING LINE.
4, DATUMS -1.-, -M- AND -N- TO BE DffiRMINED
AT DATUM PLANE-II-,
5, DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE-T-,
6, DIMENSIONS A AND B DO NOTiNCLUDE MOLD
PROTRUSION, ALLOWABLE PRCITRUSION IS
025 (0,010) PEfl SIDE. DIMENSIONS A AND B 00
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE .H-,
7, DIMENSION 0 OOES NOT INCLUDE DAMBAR
PROTRUSION, DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0,46
(0,018), MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0,07 (0,003),
DIM
A
AI
8
81
C
Cl
C2
0
E
F
G
J
K
Rl
S
$1
U
V
VI
W
Z
9
91
92
9
MILUMETEIIS
MIN
MAX
10,ooBSC
5,00 C
10,00BSC
5,00 BSC
170
0,05
0,20
1,50
1.30
0,40
020
0,45
0,75
0,22
0,35
O,65BSC
0,07
020
0,50 REF
0,06
020
12,00 BSC
6,ooBSC
0.16
0.09
12.00 BSC
6,00BSC
020 REF
LooREF
0°
7°
0°
12Q REF
5°
13°
INCHES
MIN
MAX
O,3S4BSC
,ffT
0,394BSC
0, ffTBSC
0,087
0,002 0,008
0,051
0,059
0,006 0,016
0,01
0,030
0,009 0.014
0,
BSC
0,003 0,006
0,020 REF
0,003 0,008
0,472BSC
O,236BSC
0.004 0.005
M72BSC
O,236BSC
0,008 REF
0,039 REF
0°
7°
0°
12° REF
5°
13°
13-21
lEI
BSUFFIX
CASE 858-01
Plastic Package
ISSUE 0
NOTOS:
1. DIMENSIONING AND TOlERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
t:::::::::::::::::lJ
INCHES
IIIN
MAX
lASS
1.455
0.540 0.560
0.155 0.200
0.014 0.022
0.032 0.048
0.070BSC
0.300BSC
0.008 0.Q15
0.115
0.135
O.600BSC
0°
15°
O.
DIM
A
B
C
D
F
G
H
J
J 42PL
K
L
II
N
MIWIIETERS
MIN
MAX
36.45 37.21
13.72
1422
5.08
3.94
0.36
0.56
1.17
0.81
l.778BSC
7.82BSC
0.38
0.20
2.92
3.43
15.24BSC
0°
15°
0.51
1.
BSUFFIX
CASE 859-01
Plastic Package
(SDIP)
ISSUE 0
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCWDE MOlD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010)
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
2.0352.065
0.540
0.560
0.155
0.200
0.014 0.022
0.035 BSC
0.032 0.046
0.070BSC
0.300 ssc
0.008
0.D15
0.115
0.135
O.600BSC
0°
15°
0.020
0.040
MILLIMETERS
MIN
MAX
51.69 6245
13.72
1422
3.94
5.08
0.36
0.56
O.69BSC
0.81'
1.17
1.778BSC
7.62BSC
0.20
0.38
2.92
3.43
1524BSC
0°
0.51
15°
1.02
1$lo.25(O.010)®lrl B ®I
13-22
MOTOROL~
ANALOG IC DEVICE DATA
FB, FTB SUFFIX
CASE 873-01
Plastic Package
(TQFP-32)
ISSUE A
L---~
17
@>
c
@>
'"J:
~
V@
c;;-
oo
0
2-
2-
0
0
0
C'J
:r
on
0
ci ci
-$ -l
0
0
C'J
ci
-$
).05
'63
).00
).05
).007 0.009
0.020 lASlC
0.002
0.006
12' REF
0.090 0.160
0.250 3ASIC
5'
I'
l.150 0.250
9.00( sc
M28
12' REF
1.004 0.006
0.010 lASlC
I'
0.006 0.010
0.3, ISC
1.50<
0.200 EF
1.000 REF
O.
l.00B IEF
0.039 REF
1.40
O.
X
MOTOROLA ANALOG IC DEVICE DATA
MILLIMETERS
MIN
MAl
7.000 BSC
13-25
lEI
D2TSUFFIX
CASE 936-Q3
Plastic Package
ISSUE B
NOTES:
1. DIMENSIONING AND TOLEAANCING ~ER ANSI
Y14.5M.1982.
2. CONTROlliNG DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
A AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 4.
5. DIMENSIONS A AND B 00 NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAXIMUM.
TERMINAL 4
OPTIONAL
CHAMFER
M
L
t
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
U
v
INCHES
MIN
MAX
0.386 0.403
0.356 0.368
0.170 0.180
0.026
0.036
0.045
0.055
0.051 REF
0.1ooBSG
0.539 0.579
0.125 MAX
0.050 REF
0.000 0.010
0.088 0.102
0.018 0.026
0.058 0.078
5°REF
0.116 REF
0.200 MIN
0.250 MIN
MILLIMETERS
MIN
MAX
9.804 10.236
9.042
9.347
4.318 4.572
0.680
0.914
1.143
1.397
1.295 REF
2.540BSG
13.691 14.707
3.175 MAX
1.270 REF
0.000
0.254
2.235
2.591
0.457
0.660
1.473
1.981
5°REF
2.946 REF
5.080 MIN
6.350 MIN
D2TSUFFIX
CASE 936A-Q2
Plastic Package
(D2PAK)
ISSUE A
TERMINAL &
-¢-
B
L
12345~
~=I--'T1~ ~
r:1
$"1-0.0-10-(0-.2-54-::)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROlliNG DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
AANDK.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 6.
5. DIMENSIONS A AND B 00 NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAXIMUM.
DIM
A
B
C
D
E
G
H
K
L
M
N
P
R
G
OPTIONAL
CHAMFER
S
U
M
v
INCHES
MILLIMETERS
MIN
MIN
M
MAX
0.386 0.403 9.804 10.236
0.356 0.368 9.042
9.347
0.170 0.180 4.318 4.572
0.026 0.036 0.660 0.914
0.045 0.055 1.143
1.397
0.067BSC
1.702 BSC
0.539 0.579 13.691 14.707
1.270 REF
0.050 REF
0.000 0.010 0.000
0.254
0.068 0.102 2.235
2.591
0.Q18 0.026 0.457
0.660
0.058 0.078 1.473 1.981
5°REF
5° REF
0.116 REF
2.946 REF
0.200 MIN
5.080 MIN
0.250 MIN
6.350 MIN
N~
13-26
MOTOROLA ANALOG IC DEVICE DATA
DT. DTB SUFFIX
CASE 948E4l2
Plastic Package
(TSSOP-20)
ISSUE A
SECTIONN-N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROlliNG DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOlD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHAll NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FlASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDfTlON.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DIM
A
B
C
D
F
G
H
L.--_ _ _ _--,
Cl~L
o
--I k-- G
r-,-----,
DTBSUFFIX
CASE 948F4l1
Plastic Package
(TSSOP-16, TSSOP-16L)
ISSUE 0
r-r---,--.--:",-,
J
Jl
DETAILE
K
K1
L
M
H--I
I f1$1
16XKREF
O.10(O.004)®ITI u ®I V®I
1
K
i~7"Til
PIN 1
IDENT.
~¥='"
DETAILE
MILLIMETERS
MIN
MAX
6.60
6AO
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40BSC
8°
0°
INCHES
MIN
MAX
0.252
0.260
0.169
o.m
0.047
0.002
0.006
0.020
0.030
0.026BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.012
0.007
0.007
0.010
0.252BSC
0°
8°
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONffiOLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FlASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FlASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHAlL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MAX
MIN
4.90
5.10
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40Bse
0°
8°
INCHES
MIN
MAX
0.193
0.200
0.169 0,177
0.047
0.002
0.006
0.020
0.030
0.026BSC
0.007
0.011
0.004 0.008
0.004
0.006
0.007 0.012
0,007
0.010
0.252 Bse
0°
8°
,d)1,-_ _--IKc)H'H
DETAILE~'MOTOROLA ANALOG IC DEVICE DATA
13-27
DTBSUFFIX
CASE 948G-01
Plastic Package
(TSSOP-14)
ISSUE 0
14.
14XK REF
PIN 1
IDENT.
:~~l
DETAILE
L;f
J J1
1£j.10(O.004)
-T- SEATING
I
It
--SECTION N-N
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DIMENSION A DOES NOT INCLUDE MOLD FlASH.
PROTRUSIONS OR GATE BURRS. MOLD FlASH
OR GATE BURRS SHAll NOT EXCEED 0.15
(0.006) PER SIDE.
4 DIMENSION BDOES NOT INCLUDE INTERLEAD
FlASH OR PROTRUSION. INTERLEAD FlASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. AlLOWABLE DAMBAR
PROTRUSION SHALL BE 0.06 (0.003) TOTAL IN
EXCESS OF THE KDIMENSION AT MAXIMUM
MATERiAl CONDITION.
6 TERMINAl NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DIM
A
B
C
D
F
G
H
J
Jl
K
Kl
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
1.20
0.05
.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.16
0.09
0.19
0.30
0.19
0.25
6.40BSC
0°
8°
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
0.047
0.002 0.006
0.020 0.030
0.026BSC
0.020 0.024
0.004 0.006
0.004 0.006
0.007 0.012
0.007 0.010
0.252BSC
0°
8°
PLANE
13-28
MOTOROLA ANALOG IC DEVICE DATA
DTBSUFFIX
CASE 948H-{)1
Plastic Package
ISSUE 0
24
24X KREF
-,
~~~~L-~.--.
~$I
0.10 (0.004)@ITI
u ® I V®1
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,1982.
2. CONTROLLING DIMENSION: MIlliMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHAll NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAA
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
PIN 1
IDENT.
1010.10 (0.004)1
mSEATING
PLANE
____----,
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MilliMETERS
MIN
MAX
7.70
4.30
7.90
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0°
aO
INCHES
MIN
MAX
0.303
0.311
0.169
0.1n
0.047
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Figure 4. Portion of a Process Flow Chart From Wafer Fab, Showing Documentation Control and SPC
Process Control Plan
FLOW
OPERATION
SPC
DOCUMENTATION &
REFERENCE #
IMPLEMENTATION
BURIED LAYER OXIDE
PREDIFFUSION CLEAN
WAFER INSPECTION AFTER CLEAN
12MSM 45640A
12MSM 53692A
BURIED LAYER OXIDE
NANOSPEC/AFTER DEP.
CV PLOTTING
CV EVALUATION
BURIED LAYER OXIDE
12MSM
12MSM
12MSM
12MSM
WAFERTRACPROCESS
(SCRUBlBAKEICOAT/BAKE)
12MSM 51416A REF. #10
35443A REF. #1
51418A
53805A
45486A
CONTROL PLAN, OXIDE THICKNESS
X BAR & R. RESIST THICKNESS
12MSM 35093A
416A
P·CHART, A.D.1. REDO
Figure 5. Part of a Wafer Fab Control Plan, Showing Statistical Process Control Details
Characteristics:
Process
Location
Code
A
B
C
D
Ref.
No.
Description
VISUAL DEFECTS
VISUAL DEFECTS ... MICROSCOPE
PARTICLE ... MONITOR
FILM THICKNESS
Code
E
F
G
H
Description
FILM SHEET RESISTANCE
REFRACTIVE INDEX
CRITICAL DIMENSION
CVPLOT
Measurements
Method
Analysis
Methods
D
OXIDE
THICKNESS
NANOMETRIC
CONTROL
GRAPH
EVERY RUN
3WFRlRUN
IMPOUND LOT (1)
ADJUST TIME TO
CENTER PROCESS
PER SPEC
EPI
D
THICKNESS
DIGILAB
XRCHART
EVERY RUN
5SITESIWFR
IMPOUND LOT (1)
NOTIFY ENGR.
QA
D
THICKNESS
DIGILAB
X RCHART
1WFRISHIFT
5SITESIWFR
IMPOUND LOT (2)
NOTIFY ENGR.
E
FILM
RESISTIVITY
4PTPROBE
XRCHART
EVERY RUN
5SITESIWFR
IMPOUND LOT (1)
NOTIFY ENGR.
E
FILM
RESISTIVITY
4PTPROBE
XRCHART
1WFRlSHIFT
5SITESIWFR
IMPOUND LOT (2)
NOTIFY ENGR.
MOVINGR
EVERY LOT
1 CTRLWFR
PER LOT
IMPOUND LOT
NOTIFY ENGR.
B.L.OXIDE
Frequency
Sample Size
Reaction Plan:
Point out of
PartiProcess
Detail
Characteristic
Affected
Limit (3)(4)
2
QA
lEI
DEEP
14-4
MOTOROLA ANALOG IC DEVICE DATA
Figure 6. Portion of Six Sigma (60') Roadmap Showing Steps to Six Sigma Capability
±6cr Summary
STEP
1. Identify critical characteristics
•
•
•
•
•
Product Description
Marketing
Industrial Design
R&D/Developmental Engineering
Actual or Potential Customers
2. Determine specified product elements
contributing to critical characteristics
•
•
•
•
•
Critical Characteristics Matrix
Cause·and·Effect and Ishikawa Diagrams
Success Tree/Fault Tree Analysis
Component Search or Other Forms of Planned Experimentation
FMECA (Failure Mode Effects and Critical Analysis)
3. For each product element, determine
the process step or process choice
that affects or controls required performance
•
•
•
•
•
Planned Experiments
Computer·Aided Simulation
TOP/Process Engineering Studies
Multi·Vari Analysis
Comparative Experiments
4. Determine maximum (real) allowable
tolerance for each and process
•
•
•
•
Graphing Techniques
Engineering Handbooks
Planned Experiments
Optimization, Especially Response Surface Methodology
~-
V
/
Reliability Concepts
Reliability is the probability that an analog integrated circuit
will succesfully perform its specified function in a given
environment for a specified period of time. This is the classical
definition of reliability applied to analog integrated circuits.
Another way of thinking about reliability is in relationship to
quality. While quality is a measure of variability (extending to
potential nonconformances-rejects) in the population domain,
reliability is a measure of variability (extending to potential
nonconformances-failures) in the population, time and
environmental conditions domain. In brief, reliability can
be thought of as quality over time and environmental conditions.
Ultimately, product reliability is a function of proper
understanding
of
customer
requirements
and
communicating them throughout design, product/process
development, manufacturing and final product use. Quality
Function
Deployment (QFD) is a technique which may be used to
facilitate identification of customer quality and reliability
requirements and communicating them throughout an
organization.
The most frequently used reliability measure for integrated
circuits is the failure rate expressed in percent per thousand
device hours (%/1000 hrs.). If the time interval is small
the failure rate is called Instantaneous Failure Rate
[A (t)] or "Hazard Rate." If the time interval is long (for example
total operational time) the failure rate is called Cumulative
Failure Rate.
MOTOROLA ANALOG IC DEVICE DATA
The number of failures observed, taken over the number of
device hours accumulated at the end of the observation period
and expressed as a percent is called the pOint estimate failure
rate. This however, is a number obtained from observations
from a sample of all integrated circuits. If we are to use this
number to estimate the failure rate of all integrated circuits
(total population), we need to say something about the risk we
are taking by using this estimate. A risk statement is provided
by the confidence level expressed together with the failure
rate. Mathematically, the failure rate at a given confidence
level is obtained from the point estimate and the CHI square
(X2) distribution. (The X2 is a statistical distribution used to
relate the observed and expected frequencies of an event.) In
practice, a reliability calculator rule is used which gives the
failure rate at the confidence level desired for the number of
failures and device hours under question.
As the number of device hours increases, our confidence in
the estimate increases. In integrated circuits, it is preferred to
make estimates on the basis of failures per 1,000,000,000
(10 9) device hours (FITS) or more. If such large numbers of
device hours are not available for a particular device, then the
point estimate is obtained by pooling the data from devices
that are similar in process, voltage, construction, design, etc.,
and for which we expect to see the same failure modes in
the field.
14-5
III
The environment is specified in terms of the temperature,
electric field, relative humidity, etc., by an Eyring type equation
of the form:
B
C
I..=Ae- KT ... e- RH ... e-
Figure 7. Example of a Failure Rate versus
Junction Temperature Curve
100
E
where A, B, C, & K are constants, T is temperature, RH is
relative humidity, E is the electric field, etc.
The most familiar form of this equation deals with the first
exponential which shows an Arrhenius type relationship of
the failure rate versus the junction temperature of integrated
circuits, while the causes of failure generally remain the same.
Thus we can test devices near their maximum junction
temperatures, analyze the failures to assure that they are the
types that are accelerated by temperature and then applying
known acceleration factors, estimate the failure rates for lower
junction temperatures. The Eyring or Arrhenius relationships
should be used for failure rate projections in conjunction with
proper understanding of failure modes, mechanisms and
patterns such as infant mortality, constant failure rate (useful
region) and wearout. For example if by design and proper
process control infant mortality and useful period failures have
been brought to zero and wearout failures do not start until, let
us say, 30,000 hours at 125°C then failure rate projections at
lower temperatures must account for these facts and whether
the observed wearout failures occur at lower temperatures.
Figure 7 shows an example of a curve which gives
estimates of failure rates versus temperature for an integrated
circuit case study.
Arrhenius type of equation:
where:
I..
A
e
K
T
I.. = Ae -
-..!
KT
Failure Rate
Constant
2.72
Activation Energy
Botzman's Constant
Temperature in Degrees Kelvin
10
~m
,
Non-Bumed·ln Product
iii
0....1
:I:
Ow
~e..>
1.0
~~
!¥~
trO
1\
0.1
we..>
\.
\
3~
-'"
i1@
0.01
\.
\
0.001
500 400 300 200 150 100
50 25
TJ, JUNCTION TEMPERATURE ('C)
Figure 8. A Model for Failure Distribution
in Time Domain Bathtub Curve Model
- - - Parts/Equipment
- - - Integrated Circuits (Past)
- •Inlegrated Circuits (PresenVFuture)
A
B
C
w
!;;:
tr
W
tr
:3
" ......
~
-
--
I
~~
---'te-_
-
11
----
-
I
/1'
-:/
./
LIFETIME
TJ = TA + 8JA PD or TJ = TC + 8JC PD
where:
III
TJ
Junction Temperature
TA = Ambient Temperature
TC = Case Temperature
8JA = Junction to Ambient Thermal
Resistance
8JC = Junction to Case Thermal
Resistance
PD = Power Dissipation
Life patterns (failure rate curves) for equipment and
devices can be represented by an idealized graph called the
Bathtub Curve (Figure 8).
There are three important regions identified on this curve. In
Region A, the failure rate decreases with time and it is
generally called infant mortality or early life failure region. In
Region B, the failure rate has reached a relatively constant
level and it is called constant failure rate or useful life region.
In the third region, the failure rate increases again and it is
called wearout region. Modern integrated circuits generally
do not reach the wearout portion of the curve when operating
under normal use conditions.
Decreasing Failure Rate
Constant Failure Rate
Increasing Failure Rate
Infant Mortality
Bum·ln
Manufacturing Variations
Workmanship Defects
Useful L~e
Waarout
Random (Chance) Defects
(No Pattern; Occur
Material, Design,
Precess limitations
Regula~y)
Weibull
Log Normal
Gamma Distribution
Weibull
Exponential for Equipment
Log Normal for ICs
Weibull
Normal (Gaussian)
The wearout portion ofthe curve can usually be identified by
using highly accelerated test conditions. For modern
integrated circuits, even the useful life portion cif the curve may
be characterized by few or no failures. As a result the bathtub
curve looks like continuously declining (few failures, Figure 8,
Curve B) or zero infant and useful period failures (constant
failure rate until wearout, Curve C).
The infant mortality portion of the curve is of most interest
to equipment manufacturers because of its impact on
customer perception and potential warranty costs. In recent
years the infant mortality portion of the curve for integrated
circuits, and even equipment, has been drastically reduced
MOTOROLA ANALOG IC DEVICE DATA
(Figure 8, Curve C). The reduction was accomplished by
improvements in technology, emphasis on statistical process
control, reliability modeling in design and reliability in
manufacturing (wafer level reliability, assembly level reliability,
etc.). In this respect many integrated circuit families have zero
or near zero failure patterns until wearout starts.
Does a user still need to consider burn-in? For this question
to be answered properly the IC user must consider the target
failure rate ofthe equipment, apportioned to the components
used, application environment, maturity of equipment and
components (new versus mature technology), the impact of a
failure (Le. safety versus casual loss of entertainment),
maintenance costs, etc. Therefore, if the IC user is going
through these considerations for the first time, the question of
burn-in at the component level should be discussed during a
user-vendor interface meeting.
A frequently asked question is about the reliability
differences between plastic and hermetic packaged
integrated circuits. In general, for all integrated circuits
including analog, the field removal rates are the same for
normal use environments, with many claims of plastic being
better because of its "solid block" structure.
The tremendous decrease of failure rates of plastic
packages has been accomplished by continuous
improvements in piece parts, materials and processes.
Nevertheless, differences can still be observed under highly
accelerated environmental stress conditions. For example, if
a bimetallic (gold wire and aluminum metallization) system is
used in plastic packages and they are placed on a high
temperature operating life test (125°C) then failures in the form
of opens, at the gold to aluminum interface, may not be
observed until 30,000 hours of continuous operating life.
Packages, whether plastic or hermetic, with a monometallic
system (aluminum wire to aluminum metallization) will have no
opens because of the absence of the gold to aluminum
interface. As a result, a difference in failure rates will
be observable.
Differences in failure rates between plastics and hermetics
may also be observed if devices from both packaging systems
are placed in a moist environment such as 85°C, 85% RH with
bias applied. At some point in time plastic encapsulated ICs
should fail since they are considered pervious by moisture,
(the failure mechanism being corrosion of the aluminum
metallization) while hermetic packages should not fail since
they are considered impervious by moisture. The reason the
word "should" was used is because advances in plastic
compounds, package piece parts, encapsulation processes
and final chip passivation have made plastic integrated
circuits capable of operating more than 5000 hours without
failures in an 85°C, 85% RH environment. Differences in
failure rates due to internal corrosion between plastic and
hermetic packages may not be observable until well after 5000
operating hours.
The aforementioned two examples had environments
substantially more accelerated than normal life so the two
issues discussed are not even a factor under normal use
conditions. In addition, mechanisms inherent in hermetic
packages but absent in plastics were not even considered
here. Improved reliability of plastic encapsulated ICs has
decreased demand of hermetic packages to the point where
many devices are offered only in plastic packages. The user
then should feel comfortable in using the present plastic
packaging systems.
MOTOROLA ANALOG IC DEVICE DATA
A final question that is asked by the IC user is, how can one
be assured that the reliability of standard product does not
degrade over time? This is accomplished by our emphasis on
statistical process control, in-line reliability assessment
and reliability auditing by periodic and strategiC sampling
and accelerated testing of the various integrated circuit
device packaging systems. A description of these audit
programs follows.
Analog Reliability Audit Program
The reliability of a product is a function of proper
understanding of the application and environmental
conditions that the product will encounter during its life as well
as design, manufacturing process and final use conditions.
Inherent reliability is the reliability which a product would
have if there were no imperfections in the materials, piece
parts and manufacturing processes of the product. The
presence of imperfections gives rise to reliability risks. Failure
Mode and Effects Analysis (FMEA) is a technique for
identifying, controlling and eliminating potential failures from
the design and manufacture of the product.
Motorola uses on-line and off-line reliability monitoring in
an attempt to prevent situations which could degrade
reliability. On-line reliability monitoring is at the wafer and
assembly levels while off-line reliability monitoring involves
reliability assessment ofthe finished product through the use
of accelerated environmental tests.
Continuous monitoring of the reliability of analog integrated
circuits is accomplished by the Analog Reliability Audit
Program, which is designed to compare the actual reliability
to that specified. This objective is accomplished by periodiC
and strategic sampling of the various integrated circuit device
packaging systems. The samples are tested by subjecting
them to accelerated environmental conditions and the results
are reviewed for unfavorable trends that would indicate a
degradation of the reliability or quality of a particular packaging
system. This provides the trigger mechanism for initiating an
investigation for root cause and corrective action.
Concurrently, in order to provide a minimum of interruption of
product flow and assure that the product is fit for use, a lot by
lot sampling or a non-destructive type 100% screen may be
used to assure that a particular packaging system released for
shipment does have the expected reliability. This rigorous
surveillance is continued until there is sufficient proof (many
consecutive lots) that the problem has been corrected.
The Logic and Analog Technologies Group has used
reliability audits since the late sixties. Such programs have
been identified by acronyms such as CRP (Consumer
Reliability Program), EPIIC (Environmental Package
Indicators for Integrated Circuits), LAPP (Linear Accelerated
Punishment Program), and RAP (Reliability Audit Program).
Currently, the Analog Reliability Audit Program consists of
a Weekly Reliability Audit and a Quarterly Reliability Audit.
The Weekly Reliability Audit consists of rapid (short time)
types of tests used to monitor the production lines on a real
time basis. This type of testing 'is performed at the
assembly/test sites worldwide. It provides data for use as an
early warning system for identifying negative trends and
triggering investigations for root cause and corrective actions.
14-7
III
•
The Quarterly Reliability Audit consists of long term types of
tests and is performed at th U.S. Bipolar Analog Division
Center. The data obtained from the Quarterly Reliability Audit
is used to assure that the correlation between the short term
weekly tests and long term quarterly tests has not changed
and a new failure mechanism \:las not appeared.
A large data base is established by combining the results
from the Weekly Reliability Audit with the results from the
Quarterly Reliability Audit. Such a data base is necessary for
estimating long term failure rates and evaluating potential
process improvement changes. Also, after a process
improvement change has been implemented, .the Analog
Reliability Audit Program provides a system for monitoring the
change and the past history data base for evaluating the affect
of the change.
Weekly Reliability Audit
The Weekly Reliability Audit is performed by each
assemblyltest site worldwide. The site must have capability for
final electrical and quality assurance testing, reliability testing
and first level of failure analysis. The results are reviewed on
a continuous basis and corrective action is taken when
appropriate. The results are accumulated on a monthly basis
and published.
The Reliability Audit test plan is as follows:
Electrical Measurements: Performed initially and after
each reliability test, consist of critical parameters and
functional testing at 25°C on a go-no-go basis.
High Temperature Operating Life: Performed to detect
failure mechanisms that are accelerated by a combination of
temperature and electric fields. Procedure and conditions are
per MIL-STD-883, Method 1015 with an ambient temperature
of 145°C for 40 hours or equivalent based on a 1.0 eV
activation energy and the Arrhenius equation.
Approximate Accelerated Factors
145°C
125°C
12SoC
SO°C
4
4000
1000
Temperature CyclinglThermal Shock: Performed to
detect mechanisms related to thermal expansion and
contraction of dissimilar materials, etc. Procedures and
conditions are per MIL-STD-883, Methods 1010 or 1011, with
ambient temperatures of -65° to +150°C or -40° to +125°C
(JEDEC-STD-22-A104), for a minimum of 100 cycles.
Pressure Temperature Humidity (Autoclave): Perfonned
to measure the moisture resistance of plastic encapsulated
packages. It detects corrosion type failure mechanisms due to
free ionic contaminants that may have entered the package
during the manufacturing processes. Conditions are per
JEDEC-STD-22, Method 102, a temperature of 121°C, steam
environment and 15 psig. The duration of the test is 96 hours
(minimum).
AnalysiS Procedure: Devices failing to meet the electrical
criteria after being subjected to an accelerated environment
type test are verified and characterized electrically, then
submitted for failure analysis.
14-8
Quarterly Reliability Audit
The Quarterly Analog Reliability Audit Program is performed
at the U.S. Bipolar Analog Division Center. This testing is
designed to assure that the correlation between the short term
weekly tests and the longer quarterly tests has not changed
and that no new failure mechanisms have appeared. It also
provides additional long term information for a data base for
estimating failure rates and evaluation of potential process
improvement changes.
Electrical Measurements: Performed initially and at
interim readouts, consist of all standard DC and functional
parameters at 25°C, measured on a go-no-go basis.
High Temperature Operating Life Test: Performed to
detect failure mechanisms that are accelerated by a
combination of temperature and electric fields. Procedure and
conditions are per MIL-STD-883, Method 1015, with an
ambient temperature of 145°C for 40 and 250 hours or
equivalent, based on 1.0 eV activation energy and the
Arrhenius equation.
Approximate Accelerated Factors
145°C
125°C
12SoC
SO°C
-4-
4000
1000
Temperature CyclinglThermal Shock: Performed to
detect mechanisms related to thermal expansion and
contraction, mismatch effects, etc. Procedure and conditions
are per MIL-STD-883, Methods 1010 or 1011, with ambient
temperatures of -65° to + 150°C or -40° to + 125°C
(JEDEC-STD-22-A104) for 100, 500 and 1000 or more cycles,
depending on the temperature range used. Temperature
Cycling is used more frequently than Thermal Shock.
Pressure Temperature Humidity (Autoclave): Performed
to measure the moisture resistance of plastic encapsulated
packages. It detects corrosion type failure mechanisms due to
free ionic contaminants that may have entered the package
during the manufacturing processes. Conditions are per
JEDEC-STD-22, Method 102, a temperature of 121°C, steam
environment and 15 psig. The duration of the test is for 96
hours (minimum), with a 48 hour interim readout.
Pressure Temperature Humidity Bias (PTHB; Biased
Autoclaved): This test measures the moisture resistance of
plastic encapsulated packages. It detects corrosion type
failure mechanisms due to free and bounded ionic
contaminants that may have entered the package during the
manufacturing processes, or they may be bound in the
materials of the integrated circuit packaging system and
activated by the moisture and the applied electrical fields.
Conditions are per JEDEC-STD-22, Method 102, with .bias
applied, a temperature of 121°C, steam environment and
15 psig. This test detects the same type of failures as the
Temperature Humidity Bias (85°C, 85% RH, with bias) test,
only faster. The acceleration factor between PTHB and THB
is between 20 and 40 times, depending on the type of
corrosion mechanism, electrical field and packaging system.
Highly Accelerated Stress Test {HASn is increasingly
replacing the aforementioned PTHB test. The reason is that
the HAST test allows control of pressure, temperature and
MOTOROLA ANALOG IC DEVICE DATA
humidity independently of each other, thus we are able to set
different combinations of temperature and relative humidity.
The most frequently used combination is 130°C wHh 85% RH.
This has been related to THB (85°C, 85% RH) by an
acceleration factor of 20 (minimum). The ability to keep the
relative humidity variable constant for different temperatures
is the most appealing factor of the HAST test because it
reduces the determination of the acceleration factor to a single
Arrhenius type of relationship. Motorola has been phasing
over to HAST testing since 1985.
Temperature, Humidity and Bias (THB): This test
measures the moisture resistance of plastic encapsulated
packages. It detects corrosion type failure mechanisms due to
free and bounded ionic contaminants that may have entered
the package during the manufacturing processes, or they may
be bound in the materials of the integrated circuit packaging
system and activated by moisture and the applied electrical
fields. Conditions are per JEDEC-STD-22, Method 102 (85°C,
85% RH), with bias applied. The duration is for 1008 hours,
with a 504 hour interim readout. The acceleration factor
between THB (85°C, 85% RH with bias) and the 30°C, 90%
RH is typically 40 to 50 times, depending on the type of
corrosion mechanism, electrical field and packaging system.
AnalYSis Procedure: Devices failing to meet the electrical
criteria after being subjected to an accelerated environment
type test(s) are verified and characterized electrically, then
they are submitted for root cause failure analysis and
corrective action for continuous improvement.
III
MOTOROLA ANALOG IC DEVICE DATA
14-9
14-10
MOTOROLA ANALOG IC DEVICE DATA
Applications and Product Literature
In Brief ...
Motorola's Applications Literature provides guidance to
the effective use of its semiconductor families across a
broad range ofpractical applications. Many different topics
are discussed - in a way that is not possible in a device
data sheet - froni detailed circuit designs complete with
PCB layouts, through matters to consider when embarking
on a design, to complete overviews of product families and
their design philosophies.
Information is presented in the form of Application
Notes, Article Reprints and detailed Engineering Bulletins.
Abstracts of all the applications documents are provided
as a guide to their content; each abstract also shows the
number of pages in the document, plus the origin of the
article in the case of Article Reprints. Documents new to
this issue are highlighted throughout.
MOTOROLA ANALOG IC DEVICE DATA
15-1
Applications and Product Literature
The application literature listed in this section has been
prepared to acquaint the circuits and systems engineer with
Motorola Linear integrated circuits and their applications. To
obtain copies of the notes, simply list the publications number
or numbers and send your request on your company
letterhead to: Literature Distribution Center, Motorola
Semiconductor Products Inc., P.O. Box 20912, Phoenix,
Arizona 85036.
'Indicates New Document
AN559
AN569
Application Note Abstracts
ANOO4E
Semiconductor Consideration for DC Power
Supply Voltage Protector Circuits
..
This paper addresses the requirements for the
semiconductor sensing circuitry and SCR crowbar devices
used in DC power supply over/under voltage protection
schemes. (8pp)
Automotive Direction Indicator with Short
Circuit Detection Using the UAA 1041
Cold lamps and faulty wiring can cause false operation
when using the UAA1041 Automotive Direction Indicator IC.
This note provides simple solutions. (3pp)
AN531
MC1596 Balanced Modulator
The MC1596 Monolithic Balanced Modulator is a versatile
HF communications building block. It functions as a
broadband, double-sideband suppressed-carrier balanced
modulator without the need for transformers or tuned circuits.
This article describes device operation and biasing, and gives
circuit details for typical modulator/demodulator applications
in AM, SSB and suppressed-carrier AM. Additional uses as an
SSB Product Detector, AM Modulator/Detector, Mixer,
Frequency Doubler, Phase Detector and others are also
illustrated. An appendix gives detailed AC and DC analysis.
(13pp)
AN535
Phase-Locked-Loop Design Fundamentals
The fundamental design concepts for phase-locked-loops
implemented with integrated circuits are outlined. The
necessary equations required to evaluate the basic loop
performance are given in conjunction with a brief design
example. (12pp)
AN545A
Television Video IF Amplifier Using
Integrated Circuits
This applications note considers the requirements of the
video IF amplifier section of a television receiver, and gives
working circuit schematics using integrated circuits which
have been specifically designed for consumer oriented
products. The integrated circuits used are the MC1350,
MC1352, and the MC1330. (12pp)
15-2
Transient Thermal Resistance -.General
Data and its Use
Data illustrating the thermal response of a number of
semiconductor die and package combinations are given. Its
use, employing the concepts of transient thermal resistance
and superposition, permit the circuit designer to predict
semiconductor junction temperature at any point in time during
application of a complex power pulse train. (16pp)
AN587
AN428
A Single Ramp Analog-to-Digital Converter
A simple single ramp AID converter which incorporates a
calibration cycle to ensure an accuracy of 12 bits is discussed.
The circuit uses standard ICs and requires only one precision
part - the reference voltage used in the calibration. This
converter is useful in a number of instrumentation and
measurement applications. (10pp)
Analysis and Design of the Op Amp
Current Source
Voltage-controlled current sources based on operational
amplifiers are both versatile and accurate, yet the quality of op
amps required· is unimportant. This note develops general
expressions for basic transfer function and output impedance,
and shows that simplified equations give a very accurate
description of actual circuit performance. Includes a section on
analysis of the errors that result from changes in circuit
parameters and temperature. (7pp)
AN703
Designing Digitally-Controlled Power
Supplies
This application note shows two design approaches; a
basic low voltage supply using an inexpensive MC1723
voltage regulator and a high current, high voltage, supply
using the MC1466 floating regulator with optoelectronic
isolation. Various circuit options are shown to allow the
deSigner maximum flexibility in an application. (9pp)
AN708A
Line Driver and Receiver Considerations
This report discusses many line driver and receiver design
considerations such as system description, definition ofterms,
important parameter measurements, design procedures and
application examples. An extensive line of devices is available
from Motorola to provide the designer with the tools to
implement the data transmission requirements necessary for
almost every type of transmission system. (18pp)
AN719
A New Approach To Switching Regulators
This article describes a 24 V, 3.0 A switching mode supply.
It operates at 20 kHz from a 120 V AC line with an overall
efficiency of 70%. New techniques are used to shape the load
line. The control circuit uses a quad comparator and an
opto-coupler and features short circuit protection. (12pp)
MOTOROLA ANALOG IC DEVICE DATA
Applications and Product Literature (continued)
AN740
The Design of an N·Channel16k x 16 Bit
Memory System for the PDp·11
This application note describes the design and construction
of a mainframe memory system with MCM6605 N·channel
MOS memories. Topics included are: the interface to the
PDp·11, refresh control and bookkeeping, timing control logic
for the memories, memory system considerations and
organization. The memory also features new integrated
circuits that reduce package count and enhance memory
system performance. (16pp)
AN781A
Revised Data Interface Standards
Revised data interface standards allow higher data rates
and longer cables. This note provides an overview and
comparison of the electrical and performance characteristics
of RS232-C, RS422, RS423, RS449 and RS485. Includes a
list of appropriate Motorola drivers and receivers with
performance summaries. (6pp)
AN829
Application of the MC1374 TV Modulator
The MC1374 was designed for use in applications where
separate audio and composite video signals are available,
which need converting to a high quality VHF television signal.
It's ideally suited as an output device for subscription TV
decoders, video disk and video tape players. (12pp)
Monomax: Application of the MC13001
Monochrome Television Integrated Circuit
This application note presents a complete 12" black and
white line-operated television receiver, including artwork for
the printed circuit board. It is intended to provide a good
starting point forthe first-time user. Some of the most common
pitfalls are overcome, and the significance of component
selections and locations are discussed. (12pp)
AN879
AN917
Reading and Writing in Floppy Disk
Systems Using Motorola Integrated
Circuits
The floppy disk system has become a widely used means
for storing and retrieving both programs and data. A floppy disk
drive requires precision controls to position and load the head
as will as defined read/write signals in order to be a viable
system. This application note describes the use of the
MC3469 and MC3471 Write Control ICs and the MC3470
Read Amplifier which provide the necessary head and erase
control, timing functions, and filtering. (16pp)
AN920
Theory and Applications of the MC34063
and IlA78S40 Switching Regular Control
Circuits
This paper describes in detail the principle of operation of
the MC34063 and IlA78S40 switching regulator subsystems.
Several converter design examples and numerous
applications circuits with test data are included. (38pp)
MOTOROLA ANALOG IC DEVICE DATA
AN921
'Indicates New Document
Horizontal APClAFC Loops
The most popular method used In modern television
receivers to synchronize the line frequency oscillator is the
phase locked loop. The operating characteristics and
parameters of the loops are discussed. (19pp)
AN932
Application of the MC1377 Color Encoder
The MC1377 is an economical, high quality, RGB encoder
for NTSC or PAL applications. It accepts RGB and composite
sync inputs, and delivers a 1.0 Vp-p composite NTSC or PAL
video output into a 75 n load. It can provide its own color
oscillator and burst gating, or it can easily be driven from
external sources. Performance virtually equal to high-cost
studio equipment is possible with common color receiver
components. (12pp)
A Unique Converter Configuration
Provides Step-Up/Down Functions
The use of switching regulators in new portable equipment
designs is becoming more pronounced over that of linear
regulators. This is primarily due to the need for reductions in
size and weight which dictate an ever increasing demand for
higher power conversion efficiency from a battery pack. When
designing at the board level it sometimes becomes necessary
to generate a constant output voltage that is less than that of
the battery. The step-down circuit is presented that will
perform this function efficiently. However, as the battery
discharges, its terminal voltage will eventually fall down below
the desired output, and in order to utilize the remaining battery
energy a step-up circuit is also presented.
*AN954
Interfacing the Speakerphone to the
MC34010111113 Speech Networks
InterfaCing the MC34018 speakerphone circuit to the
MC34010 series of telephone circuits is described in this
application note. The series includes the MC34010,
MC34011, MC34013, and the new "/1\' version of each of
those. The interface is applicable to existing designs, as well
as to new designs. (12pp)
AN957
Transmit Gain Adjustments for the
MC34014 Speech Network
The MC34014 telephone speech network provides for
direct connection to an electret microphone and to Tip and
Ring. In between, the circuit provides gain, drive capability,
and determination of the ac impedance for compatibility with
the telephone lines. Since different microphones have
different sensitivity levels, different gain levels are required
from the microphone to the Tip and Ring lines. This application
note will discuss how to change the gain level to suit a
particular microphone while not affecting the other circuit
parameters. (2pp)
AN958
15-3
Applications and Product Literature (continued)
AN959
A Speakerphone with Receive Idle Mode ."
The MC34018 speakerphone system operates on the
principle of comparing the transmit and receive signals to
determine which is stronger, and then switching the circuit into
that mode. (2pp)
AN960
Equalization of DTMF Signals Using
the MC34014
This application note will describe how to obtain
equalization (line length compensation) of the DTMF dialing
tones using the MC34014 speech network. (2pp)
AN968
A Digital Voice/Data Telephone Set
This design provides standard analog telephone functions
while simultaneously transmitting 9600 baud asynchronous
data. It is based on Motorola's MC145422/26 UDLTfamily of
voice/data ICs which provide 80 kbps full-duplex synchronous
communication over distances up to 2 km. The circuit includes
a Codec/filter, Data Set Interface and pulseltone dialer. (7pp)
AN976
A New High Performance Current Mode
Controller Teams Up with Current
Sensing Power MOSFETs
A new current mode control IC that interfaces directly with
current sensing power MOSFETs is described. Its second
generation architecture is shown to provide a variety of
advantages in current mode power supplies. The most
notable of these advaritages is a "Iossless" current sensing
capability that is provided when used with current sensing
MOSFETs. The discussion includes subtle factors to watch
outlor in practical designs, and an applications example. (8pp)
AN980
VHF Narrowband FM Receiver Design
Using the MC3362 and the MC3363 Dual
Conversion Receivers
The MC3362 and MC3363 narrowband FM dual conversion
receivers feature excellent VHF performance with low power
drain, making them ideal for cordless telephones, narrowband
voice and data receivers and RF security devices. This note
provides a detailed description of the operation of the two
devices, plus circuits and descriptions for four applications: a
Single Channel VHF FM Narrowband Receiver; a Ten
Channel Frequency Synthesized Cordless Telephone
Receiver; a 256 Channel Frequency Synthesized Two-Meter
Amateur Band Receiver; and a Single Chip Weather Band
Receiver. (14pp)
AN983
A Simplified Power Supply Design Using
the TL494 Control Circuit
This application note describes the operation and
characteristics of the TL494 Switchmode™ Voltage Regulator
and shows its application of a 400 W offline power supply.
The TL494 is a fixed-frequency pulse width modulation
control circuit, incorporating the primary building blocks
required for the control of a switching power supply. (5pp)
15-4
AN1002
'Indicates New Document
A Handsfree Featurephone Design
Using the MC34114 Speech Network
and the MC34018 Speakerphone ICs
A comprehensive application note which develops a full
featurephone circuit using the MC34114 Speech Network, the
MC34018 Speakerphone IC and the MC145412 Dialer.
Functions include 10 number memory pulseltone dialer, tone
ringer, mike mute and line length compensation for both
handset and speakerphone operation. Options include
line-powered circuit, line-powered circuit with booster for long
lines, and external supply-powered. Includes glossary of
telephone terms. (18pp)
AN1003
A Featurephone Design, with Tone
Ringer and Dialer, Using the MC34118
Speakerphone IC
This application note describes how to add a handset, dialer
and tone ringer to the MC34118 speakerphone circuit.
Although anyone of several speech networks could be used
as an interface between the MC34118 and the phone line this
application note covers the case where simplicity and low cost
are paramount. Two circuits are developed in this discussion:
line-powered and supply-powered versions. (13pp)
AN1004
A Handsfree Featurephone Design
Using the MC34114 Speech Network
and the MC34118 Speakerphone ICs
Complete designs for a featurephone providing 10 number
memory, pulse or tone dialling, tone ringer, microphone
muting, and line length compensation for both handset and
speakerphone operation. Includes line-powered, linepowered plus long-line booster, and supply-powered
versions. The MC34114 interfaces with tip and ring and
provides 2-to-4 wire conversion. (18pp)
AN1006
Linearize the Volume Control of the
MC34118 Speakerphone
A single resistor added to the volume control potentiometer
in an MC34118 speakerphone application will almost perfectly
linearize the control law. (lpp)
AN1016
Infrared Sensing and Data Transmission
Fundamentals
Many applications need electrical isolation, remote control
or pOSition sensing. Infrared light provides an excellent
solution due to its low cost, ease of use, availability of
components, and freedom from the licensing and interference
concerns of RF techniques. This note is a brief but informative
reference on the design principles for IR systems, including a
selection of receiver circuits. (6pp)
MOTOROLA ANALOG IC DEVICE DATA
Applications and Product Literature (continued)
NTSC Decoding Using the TDA3330, with
Emphasis on Cable In/Cable Out Operation
The TDA3330 is a Composite Video to RGB Color Decoder
originally intended for PAL and NTSC color TV receivers and
monitors - so its data sheet concentrates on picture tube
drive. This practical application note supplements the data
sheet by providing circuits for video cable drive as used in
video processing, frame store and other specialized
applications, and expands on TDA3330 functional details.
Includes PCB artwork and layout of an evaluation board. (8pp)
AN1019
Mounting Considerations for Power
Semiconductors
The operating environment is a vital factor in setting current
and power ratings of a semiconductor device. Reliability is
increased considerably for relatively small reductions in
junction temperature. Faulty mounting not only increases the
thermal gradient between the device and its heatsink, but can
also cause mechanical damage. This comprehensive note
shows correct and incorrect methods of mounting all types of
discrete packages, and discusses methods of thermal system
evaluation. (20pp)
AN1040
AN1044
The MC137B-A Monolithic Composite
Video Synchronizer
The MC1378 provides an interface between a remote
composite color video source and local RGB. On-chip circuitry
can lock a local computer to the remote source, switching
between local and remote signals to generate composite
video overlays. This detailed note describes local and remote
operation; picture-in-picture applications and the design of
test fixtures to help system development. Printed circuit
artwork for an evaluation board is provided. The NTSC/PAL
color encoder is similar to the MC1377, discussed in detail in
AN932. (13pp)
'Indicates New Document
Circuit and the MC34164 Undervoltage Sensing Circuit. The
MC34160 provides a regulated 5.0 V supply, plus power
warning and reset outputs to the MCU. The MC34164 assures
that the MCU is held in reset when the supply voltage is too low
for the MC34160 to operate correctly.
Adding Digital Volume Control To
Speakerphone Circuits
Describes how to control speakerphone volume from UP
and DOWN switches in place ofthe more usual potentiometer.
Includes a fully annotated circuit using only three standard
CMOS ICs and no critical components. (4pp)
AN10n
New Components Simplify Brush DC
Motor Drives
A variety of new components simplify the design of brush
motor drives. One is a brushless motor control IC which is
easily adapted to brush motors. Others include multiple Power
MOSFETs in H-Bridge configuration, a new MOS turn-off
device, and gain-stable opto level shifters. Several circuits
illustrate how the new devices can be used in practical motor
drives, in particular to control speed in both directions and
operate from a single power supply. (6pp)
AN1078
External-Sync Power Supply with Universal
Input Voltage Range for Monitors
As the resolution of color monitors increases, the
performance and features of their power supplies becomes
more critical. EMI/RFI generated by switching power supplies
can adversely affect resolution if switching frequency is not
synchronized to horizontal scanning frequency. This 90 W
flyback switching supply demonstrates the use of new high
performance devices in a low cost design, and includes a new
universal input voltage adapter. (20pp)
AN1080
Minimize the "pop" in the MC34119
Low Power Audio Amplifier
Sometimes a "pop" is heard in the loudspeaker when the
MC34119 audio amplifier is re-enabled. There are several
possible causes, but this note offers a simple and low cost
remedy to satiSfy the most demanding user. (3pp)
AN1081
AN1046
Three Piece Solution for Brush/ess Motor
Control Design (Rev. 1)
Until recently, the design of compact but comprehensive
circuits taking full advantage of the unique attributes of
brushless DC motors has been difficult, while available power
transistors have not always performed as well as is necessary
for the application. This high-performance three-chip solution
couples the rugged MPM3003 three phase MOSFET bridge
(in a 12-pin power package) with the MC33035 Brushless DC
Motor Adapter. DeSign is simplified, board area reduced. Full
circuit, parts list, and discussion of practical considerations.
(10pp)
Use of the MC6BHC6BT1 Real-Time
Clock with Multiple Time Bases
While this Application Note is primarily about the
MC68HC68T1 clock/calendar device, it also provides an
example of the application of two Motorola Analog ICs: the
MC34160 Microporcessor Voltage Regulator and Supervisory
• AN1 065
One-Horsepower O"-Line Brushless
Permanent Magnet Motor Drive
Brushless Permanent Magnet (BPM) motors (brushless DC
motors) using MOSFET inverters are common in low voltage,
variable speed applications such as disk drives. Higher
voltage off-line applications can also use the same
technology, but there have been problems in deSigning a
reliable, low cost high side driver and understanding the more
subtle effects of diode snap and PCB layout. This
one-horsepower off-line BPM motor drive board uses
opto-isolators and a special MOSFET turn-off IC for level
translation. Includes PCB artwork and parts list, and a
discussion of the theory. (10pp)
AN1101
III
MOTOROLA ANALOG IC DEVICE DATA
15-5
Applications and Product Literature (continued)
AN1108
Design Considerations for a TWo Transistor,
Current Mode Forward Converter
This design for a 150 W, 150 kHz, two transistor, current
mode forward converter illustrates solutions for noise control,
feedback circuit analysis and magnetic component design topics that often create the most problems for designers.
Improved Schottky rectifiers, power MOSFETs and
optocouplers - and their effects on switch mode power supply
design - are also considered. Includes circuit, analysis, parts
list and theoretical discussion. (11pp)
AN1122
Running the MC44802A PLL Circuit
The MC44802A provides the Phase-Locked-Loop (PLL)
portion of a tuning circuit intended for TV, FM radio and set-top
converter applications up to 1.3 GHz; a complete tuning circuit
is formed by adding a Voltage Controlled Oscillator (VCO) and
mixer. The data sheet recommends use of an MCU for sending
the control bytes that set the tuning frequency. This note
describes a serial (12C) interface with an MC68HC11 E9 in a
tuner design - the information is sufficiently general to allow
almost any MCU to be used. Includes M68HC11 program
listing. (12pp)
AN1126
Evaluation Systems for Remote Control
Devices on an Infrared Link
The availability at low cost of remote control devices and
infrared communication links provides opportunities in many
application areas. This note gives information for constructing
the basic building blocks to evaluate both IR links and the most
popular remote control devices. Schematics and single-side
PCB layouts are presented that should enable the designer
quickly to put together a basic control link and evaluate its
suitability for a given application in terms of data rate, effective
distance, error rate and cost. Sources for special parts are also
given. (10pp)
AN1203
A Software Method for Decoding the Output
from the MC144971MC3373 Combination
Infrared communication is now widely used as a simple and
effective means of remote control over short distances. A
variety of encoding methods is used, including the biphase
scheme implemented by the MC14497, a complete building
block for IR data transmission. The MC3373 is a companion
receiver chip to the MC14497, providing front-end processing
to interface a photo detector to a TTL level. This note
describes the decoding of the data at the output of the
MC3373, along with software listings for the MC68HC11 and
the MC68HC05. (5pp)
AN1300
Interfacing Microcomputers to Fractional
Horsepower Motors
In fractional horsepower motion control systems, command
signals are usually now generated by a microprocessor or
digital signal processor, while power is applied with MOSFETs.
The interface between the two can still present difficulties; for
small motors it will be, typically, 5.0 V logic to complementary
P-ChanneI/N-Channel MOSFET H-bridges. A number of
factors need to be conSidered, including diode snap, group
15-6
·Indicates New Document
bounce, noise suppression and locking out invalid inputs. The
design discussed here is embodied in evaluation board
DEVB103. (8pp)
AN1301
Interfacing Analog Inputs to Fractional
Horsepower Motors
In many types of systems it is desirable to control motor
speed with an analog signal. Even in digital systems, it is often
cost effective to generate an analog Signal from static speed
control bits or a lower frequency PWM signal than to use a
more expensive MCU capable of generating a 20 kHz+ PWM
signal directly. Although recent developments have simplified
analog input conversion and power MOSFET outputs, the
interface between Signal processing circuits and power
outputs is still far from simple. This note discusses the issues
using the DEVB118 evaluation board as an example design.
(9pp)
AN1306
Thermal Distortion in Video Amplifiers
Thermal distortion is a problem in many high resolution
video amplifiers. It occurs when there are instantaneous
power changes in the transistor stages, and if the problem
remains uncompensated, this leads to the visual effect known
as smearing. This note discusses what smearing is, what
causes thermal distortion, how to measure it, and how to
compensate for it. (5pp)
AN1307
A Simple Pressure Regulator Using
Semiconductor Pressure Transducers
Semiconductor pressure transducers offer an economical
means of achieving high reliability and performance in
pressure sensing applications. The completely integrated
MPX5100 (0 psi to 15 psi) series provides a temperature
compensated, high level linear output suitable for interfacing
directly with many linear control systems. This Circuit
illustrates how the MPX5100 can be used with a simple
pressure feedback system based on the MC33033 Brushless
Motor Controller to establish pressure regulation. Includes
circuit diagram and PCB artwork. (7pp)
*AN1315
An Evaluation System Interfacing
the MPX2000 Series Pressure Sensors
to a Microprocessor
Outputs from compensated and calibrated semiconductor
pressure sensors such as the MPX2000 series devices are
easily amplified and interfaced to a microprocessor. Design
considerations and the description of an evaluation board
using a simple analog interface connected to a
microprocessor is presented here. (21 pp)
AN1510
A Mode Indicator for the MC34118
Speakerphone Circuit
Within the MC34118 are two comparators driven by the level
detectors which are sensing the speech signals (see
MC34118/D Data Sheet, Figure 24). The comparators'
outputs drive the attenuator control block which sets the
operating mode. (2pp)
MOTOROLA ANALOG IC DEVICE; DATA
Applications and Product Literature (continued)
*AN1539
An IF Communication Circuit Tutorial
This article is intended to be a tutorial on the use of IF
communication integrated circuits. The ISM band channel
bandwidths and the Motorola MC13156 are used within this
article as a platform for discussion. An examination of the
devices topology is provided along with a discussion of the
classical parameters critical to the proper operation of any
typical IF device. The parameters reviewed are impedance
matching the mixer, selecting the quad tank and filters and
concluding with a overview of bit error rate testing for digital
applications. Upon completion, the reader will have a better
understanding of IF communications basics and will be able
to specify the support components necessary for proper
operation of these devices. (8pp)
*AN1544
Design of Continuously Variable Slope
Delta Modulation Communication Systems
Delta modulation is a simple and robust method of AID
conversion in systems requiring serial digital communications
of analog signals. Delta modulation is limited by the anlaog
input frequency and amplitude processed with any given
circuit configuration; i.e., the higher the clock frequency, the
better the modulation quality (the clock frequency should be
typically 9.6 kHz to 64 kHz for voice applications). Delta
modulaton has the advantage that signal to noise ratios do not
vary with distance in digital transmission and multiplexing, and
the switching and repeating hardware is more economical
than with purely analog systems. This paper is intended to give
practical guidance in designing an optimum deltamod
configuration for the most common voice applications using a
Continuously Variable Slope Delta Modulator/Demodulator,
MC34115 or MC3418, and provide some useful SNR
performance information. (20pp)
*AN1548
Guidelines for Debugging the MC44011
Video Decoder
Normally, the implementation of the MC44011
Multistandard video decoder is fairly simple in that there are no
external adjustments, or critical components, to deal with.
However, since this IC contains several interrelated functions
and a substantial amount of programmability, debugging an
improperly working circuit can sometimes be daunting. The
purpose of this document is to provide a procedure for
debugging and checking the operation of this IC, and an
indication of what to expect at some of the various pins. (8pp)
*AN1575
Worldwide Cordless Telephone Frequencies
This application note contains a listing of the worldwide
cordless telephone frequencies by country. These tables
reference application information provided in the MC13109,
'Indicates New Document
MC13110, and MC13111 Universal Cordless Telephone
Subsystem Integrated Circuit Technical Data Sheets. Channel
number, Tx channel frequency, 1st LO frequency, and Tx and
Rx divider values are listed in this application note. (8pp)
ANE424
50 W Current Mode Controlled Offline
Switch Mode Power Supply Working
over 50% Duty Cycle using the UC3842A
Switch mode power supplies based on flyback architecture
and voltage-controlled PWM techniques are well established.
This note describes a way of improving their dynamic
characteristics using a Current Controlled PWM technique. A
dedicated bipolar IC, the UC3842A Off-Line Current Mode
PWM Controller, performs the current control, regulation and
safety features. Full analYSis of transformer and other
components, plus discussion of the instability inherent in the
current control mode. (27pp)
ANHK02
Low Power FM Transmitter System
MC2831A
This application note provides information concerning the
MC2831A, a one-chip low-power FM transmitter system
designed for FM communication equipment such as FM
transceivers, cordless telephones, remote control and RF
data link. (16pp)
Article Reprint Abstracts
AR301
Solid State Devices Ease Task of DeSigning
Brushless DC Motors
Brushless fractional-horsepower DC motors are gaining in
popularity over brush type motors. Their characteristics are
similar but they avoid the practical problems associated with
brushes. In the past control complexity has made them less
attractive, but dedicated control ICs like the MC33034, plus
current-sensing power MOSFETs, mean that much of the
control and protection electronics is available off the shelf.
(EDN, 3 September 1987) (7pp)
AR323
Managing Heat DiSSipation in DPAK
Surface Mount Power Packages
Physically smaller than a lead-formed TO-220, the DPAK
was introduced to accommodate larger die than in previously
available SM packages like the SOT-89. But larger die implies
increased heat dissipation. New board materials and good
circuit deSign ensure that DPAK Power MOSFETs can readily
switch at their full pulse current ratings.
(Powertechnics, December 1988) (4pp)
III
MOTOROLA ANALOG IC DEVICE DATA
15-7
Applications and Product Literature (continued)
AR340
The Low Forward Voltage Schottky
As feature sizes are scaled down in very high density
circuits, it will be necessary for the standard power supply
voltage to be reduced from 5.0 V to 3.3 V within the next few
years to avoid degrading performance in the new devices.
Also, greater power supply efficiency will be required if the
power supply is not to occupy a disproportionate amount of the
total system volume. Since the major power loss in switching
power supplies is in the output rectification circuits, more
efficient rectifiers are needed. Schottky rectifier technology
shows the greatest potential. (Powerlechnics, May 1990)
(3pp)
advantages and disadvantages, illustrated with typical 100 W
MOSFET and Bipolar deSigns. (2pp)
EB126
Get 300 Watts EPE Linear Across 2 to
30 MHz from this Push-Pull Amplifier
Includes circuit, PCB artwork and layout for a 300 W
push-pull linear amplifier based on two MRF422s, designed to
operateoverthe 2.0 MHz to 30 MHz band. An MC1723 voltage
regulator is used as a bias supply. (4pp)
EB27A
EB85A
Full-Bridge Switching Power Supplies
A useful selection chart presenting preferred Bipolar,
power MOSFET, Rectifier and Control devices for various
areas of typical 500 W to 1000 W full-bridge switching power
supplies. (1 p)
EB112
The Application of a Telephone Tone
Ringer as a Ring Detector
Telephone ringers are driven by high voltage, low frequency
AC signals which are superimposed on the 48 V DC Tip-Ring
feed voltage. An electronic ring detector must sense the
presence of an AC signal on the line and produce a
dielectrically isolated logic level to the system processor. (2pp)
Ultra-Rapid Nickel-Cadmium Battery
Charger
Charging NiCad batteries is a particular problem when their
voltage exceeds the voltage of the available charging source.
The ultra-fast charger presented here is capable of charging
eight to twelve 1.5 V batteries at 1.2 A to 1.8 A in 30 to 45
minutes from a 10 V to 14 V source - a feat made possible by
the use of new sintered electrode technology by battery
manufacturers. Includes PC artwork and layout. (3pp)
EB128
Engineering Bulletin Abstracts
'Indicates New Document
Simple, Low-Cost Motor Controller
This low cost DC motor controller uses the cost effective
MPM3002 SENSEFET-based H-Bridge, plus the MC34060
PWM IC. It is capable of driving a 1/3 HP, permanent magnet
90 V DC motor, and includes dynamic braking and Soft-Start.
(2pp)
EB142
The MOSFET Turn-Off Device Circuit Building Block
A New
Technical developments have lead to a variety of discrete
devices using circuit integration to reduce system cost and
board space, while offering some performance improvement
over conventional solutions. The first of these new
components - dubbed SMALLBLOCK'M - is' a building block
that simplifies and reduces the component cost of an active
gate-tum-off network for current-source driven MOSFETs. It is
available in TO-92, SOT-23 and SOT-223 packages. (8pp)
Product Literature
DL136/D
HB206
Telecommunications Device Data
Linear & Switchmode Voltage Regulator
Handbook (See Back of Chapter 3)
(Out of Print)
EB123
A Simple Brush Type DC Motor Controller
A Simple and cost effective way to drive brush type DC
motors is to use power MOSFETs with a Brushless DC Motor
Control IC. The low cost MC33033 controller and integrated
8.0 Al1 00 V MPM3002 H-bridge combine to give a minimum
parts count brush motor drive. (2pp)
SG56/D
SG73/D
SG79/D
SG96/D
EB124
MOSFETs Compete with Bipolars in Flyback
Power Supplies
Power MOSFETs with 400 V to 500 V breakdown ratings are
widely used in multiple-transistor off-line power supplies. Now
they can be used in flyback supplies as well, as breakdown
voltages are extended to 1000 V. A discussion of the
1!i-8
SG98/D
SG127/D
SG368/D
TMOS Power MOSFET Selector Guide /
Cross Reference
Master Selection Guide
SWITCHMODE - A DeSigner's Guide for
Switching Power Supply Circuits and
Components
Linear/Interface ICs Selector Guide
Selector Guide and Cross Reference
Linear Telecom Cross Reference
Surface Mount Products Selector Guide
Video Capture Chip Sets Selector Guide
(See Front of Chapter 9)
SG410/D
Applications & Product Literature Selector
Guide / Cross Reference
MOTOROLA ANALOG IC DEVICE DATA
D
Alphanumeric Index
and Cross References
Volumes
I
II
a
Amplifiers and Comparators
I
II
Power Supply Circuits
I
II
Power/Motor Control Circuits
I
II
Voltage References
II
a
Data Conversion
II
II
Interface Circuits
II
Communication Circuits
II
a
II Consumer Electronic Circuits
1m Automotive Electronic Circuits
III Other Analog Circuits
II Tape and Reel Options
lEI Packaging Information
II Quality and Reliability Assurance
II
Applications and Product Literature
1PHX16946-15 Prtnted in USA 12/96 BANTA CO. MOTO#41 30,000 LITLINIF
II
II
II
I
II
I
II
II
II
®
MOTOROLA
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1--800--441-2447 or 602- 303-5454
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DL128/D
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Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:06:13 22:07:26-08:00 Modify Date : 2017:06:13 22:57:34-07:00 Metadata Date : 2017:06:13 22:57:34-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:7589d9e1-5d03-6349-ac42-b03f440b23b2 Instance ID : uuid:2e105ce1-3951-754e-a1d0-4f8e547ac508 Page Layout : SinglePage Page Mode : UseNone Page Count : 1302EXIF Metadata provided by EXIF.tools