1996_Motorola_High Performance_ECL 1996 Motorola High Performance ECL

User Manual: 1996_Motorola_High-Performance_ECL

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MOTOROLA

OL 140/0
REV 4

Hig,h.Performance Eel Data

ECLinPS and ECLinPS Lite

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High Performance EeL Data
ECLinPS and ECLinPS Lite

General Information

ECLinlPS Family Specifications &
Device Data Sheets
IECLinPS Lite Family Specifications
& Device Data Sheets
Low-Voltage ECLinPS &·E-lite
Device Data Sheets
Design Guide &
Application Notes

ECLinPS, ECLinPS Lile, MOSAIC, MECL 10K and MECL 10H are Irademarks of Motorola Inc.
The brands or product names mentioned are trademarks or registered trademarks of their respective holders.

Suggested References:

Low Voltage ECLinPS SPICE Modeling Kit, Motorola Inc., 1996. Stock code AN1560/D.
Motorola MECL Device Data Book, Motorola Inc., 1993. Stock code DL122/D.
F100K ECL Data Book, Fairchild Camera and Instrument Corp.
Motorola MECL System Design Handbook, second edition. Motorola Inc., 1983. Stock code HB205/D.
Signetics ECL 10K/100K Data Manual.

MOTOROLA

High Performance Eel Data
ECLinPS and ECLinPS Lite
This databook contains device specifications for Motorola's advanced ECl logic families, ECLinPS and
ECLinPS Lite.
ECLinPS' (ECl in picoseconds) was dev,eloped in response to the need for an even higher
performance ECl family of standard logic functions, particularly in the Computer, Automated Test,
Instrumentation and Communications indusiries. Family general features as well as specific functions
were developed in close consultation with ECl systems deSign engineers.
ECLinPS offers the user a Single gate delay of SOOps max., including package delay, and a flip-flop
toggle frequency of 11 OOMHz.
ECLinPS is compatible with two different ECl standards. Each function is available with either MECl
10H compatibility (MC10Exxx series) or lOOK compatibility (MC100Exxx series).
ECLinPS Lite is Motorola's family of Single, essential logic primitives, (gates, muxes, flops etc.) along
with translators, low voltage ECl logic devices and Pll support products.
ECLinPS is offered in the 28-lead plastic leaded chip carrier (PlCC), a J-Iead surface mount IC
package. ECLinPS Lite is offered in either 8, 16 or 20-Iead industry standard SOIC packaging. These
packages were selected for high performance, reduced parasitics and good thermal handling in low
cost, standard packages, and reflect the industry trend towards surface mount assembly.
• Any reference to ECLinPS in the General Information or Applications Information sections of this book,
unless otherwise noted, will Include the ECLinPS Lite and Low Voltage ECLinPS families.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes
no warranty, represenlation or guarantee regarding the suilability of its products for any particular purpose,
nor does Motorola assume any liability arising out olthe application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical"
parameters which may be provided in Motorola data sheets andlor specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including 'Typicals" must
be validated for each customer application by customer's technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products
for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part. Motorola and@ are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Printed in U.S.A.

iii

CONTENTS
Ch 1. General Information

MC10E411 ...........................
MC10E416/MC100E416 ...............
MC10E431/MC100E431 ...............
MC10E445/MC100E445 ...............
MC10E446/MC100E446 ...............
MC10E451/MC100E451 ...............
MC10E452/MC100E452 ...............
MC10E457/MC100E457 ...............
MC10E1651 ..........................
MC10E1652 ..........................

Numeric Index ............................. 1-2
Device Nomenclature ...................... 1-3
Selection Guide ........................... 1-3
Family Overview ........................... 1-5
Electrical Characteristics ................... 1-10
Engineering Evaluation Board .............. 1-15

.Ch 2. ECLinPS Data Sheets
Family Specifications. . . . . . . . . . . . . . . . . . . . . .. 2-2
MC10E016/MC100E016 ................. 2-3
MC10El0l/MC100El0l ................. 2-9
MC10El04/MC100El04 ................ 2-11
MC10El07/MC100El07 ................ 2-13
MC10Elll/MC100Elll ................. 2-15
MC10Ell21MC100El12 ................. 2-18
MC10El16/MC100El16 ................. 2-20
MC10E1221MC100E122 ................ 2-22
MC10E131/MC100E131 ................ 2-24
MC10E136/MC100E136 ................ 2-26
MC10E137/MC100E137 ................ 2-33
MC10E141/MC100E141 ................ 2-36
MC10E142/MC100E142 ................ 2-38
MC10E143/MC100E143 ................ 2-40
MC10E150/MC100E150 ................ 2-42
MC10E151/MC100E151 ................ 2-44
MC10E154/MC100E154 ................ 2-46
MC10E155/MC100E155 ................ 2-48
MC10E156/MC100E156 ................ 2-50
MC10E157/MC100E157 ................ 2-52
MC10E158/MC100E158 ................ 2-54
MC10E160/MC100E160 ................ 2-56
MC10E163/MC100E163 ................ 2-58
MC10E164/MC100E164 ................ 2-60
MC10E166/MC100E166 ................ 2-62
MC10E167/MC100E167 ................ 2-64
MC10E171/MC100E171 ................ 2-66
MC10E175/MC100E175 ................ 2-68
MC10E193/MC100E193 ................ 2-70
MC10E195/MC100E195 ................ 2-72
MC10E196/MC100E196 ................ 2-75
MC10E197 ............................ 2-80
MC100E210/MC100LVE210 .............. 4-7
MC10E211/MC100E211 ................. 2-95
MC10E212/MC100E212 ............... 2-100
MC10E241/MC100E241 ............... 2-102
MC10E256/MC100E256 ............... 2-104
MC100E310/MC100LVE310 ............. 4-14
MC10E336/MC100E336 ............... 2-108
MC10E337/MC100E337 ............... 2-110
MC10E404/MC100E404 ............... 2-113

2-115
2-119
2-121
2-123
2-129
2-133
2-135
2-137
2-140
2-144

Ch 3. ECLinPS Lite Datasheets
Family Specifications. . . . . . . . . . . . . . . . . . . . . .. 3-3
Applications Information .................... 3-4
MC10EL01/MC100ELOl ................. 3-7
MC10EL04/MC100EL04 ................. 3-8
MC10EL05/MC100EL05 ................. 3-9
MC10EL07/MC100EL07 ................ 3-11
MC10EL11/MC100EL11 ................. 3-12
MC10EL12/MC100EL12 ................ 3-14
MC100EL13/MC100LVEL13 ............. 4-20
MC100EL14/MC100LVEL14 ............. 4-22
MC10EL 15/MC100EL 15 ................ 3-17
MC10EL 16/MC100EL16 ................ 3-20
MC100EL17/MC100LVEL 17 ............. 4-27
MC100EL29/MC100LVEL29 ............. 4-29
MCl 00EL30/MCl 00LVEL30 ............. 4-31
MC10EL31/MC100EL31 ................ 3-25
MC10EL32/MC100EL32 ................ 3-27
MC10EL33/MC100EL33 ................ 3-29
MC10EL34/MC100EL34 ................ 3-31
MC10EL35/MC100EL35 ................ 3-33
MC100EL38/MC100LVEL38 ............. 4-35
MC100EL39/MC100LVEL39 ............. 4-39
MC10EL51/MC100EL51 ................ 3-37
MC10EL521MC100EL52 ................ 3-39
MCl 00EL56/MCl 00LVEL56 ............. 4-44
MC10EL57/MC100EL57 ................ 3-42
MCl OEL58/MCl 00EL58 ................ 3-44
MCl 00EL59/MCl 00LVEL59 ............. 4-47
MC10EL89 ............................ 3-46
MC100EL90/MC100LVEL90 ............. 4-49
MC100EL91/MC100LVEL91 ............. 4-52
MC10ELT20/MC100ELT20 .............. 3-51
MC10ELT21/MC100ELT21 .............. 3-53
MC10ELT22/MC100ELT22 .............. 3-55
MC100ELT23 .......................... 3-57
MC10ELT24/MC100ELT24 .............. 3-59
MC10ELT25/MC100ELT25 .............. 3-61
MC10ELT26/MC100ELT26 .............. 3-63
MC10ELT28/MC100ELT28 .............. 3-64

CONTENTS
Ch 4. Low Voltage ECLinPS Data Sheets

Ch 5. Design Guide & Application Notes
Design Guide:
System ................................ 5-2
Transmission Line Theory . . . . . . . . . . . . . . .. 5-8
System Interconnect .................... 5-18
Interfacing With ECLinPS ............... 5-29
Packaging and Thermal Information ...... 5-32

MC100LVE111 .......................... 4-2
MC100LVE164 ......................... 4-5
MC100LVE210/MC10E210 ............... 4-7
MC100LVE222 ........................ 4-11
MC100LVE310/MC10E310 .............. 4-14
MC100LVEL11 ......................... 4-18
MC100LVEL13/MC100EL13 ............. 4-20
MC100LVEL14/MC100EL14 ............. 4-22
MC100LVEL16 ........................ 4-25
MC100LVEL17/MC100EL17 ............. 4-27
MC100LVEL29/MC100EL29 ............. 4-29
MC100LVEL30/MC100EL30 ............. 4-31
MC100LVEL32 ........................ 4-33
MC100LVEL38/MC100EL38 ............. 4-35
MC100LVEL39/MC100EL39 ............. 4-39
MC100LVEL51 ........................ 4-42
MC100LVEL56/MC100EL56 ............. 4-44
MC100LVEL59/MC100EL59 ............. 4-47
MC100LVEL90/MC100EL90 ............. 4-49
MC100LVEL91/MC100EL91 ............. 4-52
MC100LVEL92 ........................ 4-55

Case Outlines . ......................... 5-37
Quality and Reliability. . . . . . . . . . . . . . . . . .. 5-43
Application Notes:
ECLinPS Circuit Performance at
Standard VIH Levels (AN1404) ........
ECL Clock Distribution
Techniques (AN1405) ................
Designing With PECL (AN1406) ..........
ECLinPS I/O SPICE Kit (AN1503) ........
Metastability and the ECLinPS
Family (AN1504) ....................
Interfacing Between LVDS and
ECL (AN1568) ......................
Distributor and Worldwide Sales Offices .....

5-45
5-53
5-60
5-69
5-79
5-87
5-93

High Performanl;e Eel Data
ECLinPS and ECLinPS Lite

General Information
This section contains a numerical listing of
ECLinPS and ECLinPS Lite family functions, a
technical overview of the ECLinPS amd ECLinPS
Lite families and an outline of their electrical
characteristics. In addition, this section outlines the
procedures and philosophies used to AC test the
families. (MC10ElEL series devices are compatible
with the MECL 10H family. MC100ElEL series are
compatible with 100K ECL.)

CONTENTS
Numeric Index ............................. 1-2
Device Nomenclature ....................... 1-3
Selection Guide ............................ 1-3
Family Overview ........................... 1-5
Electrical Characteristics ................... 1-10
Engineering Evaluation Board ............... 1-15

ECLinPS and ECLinPS Lite
DL140-Rev4

1-1

MOTOROLA

MOTOROLA
SEMICONDUCTOR GENERAL INFORMATION

SECTION 1
Numeric Index
ECLinPS Devices
MC1D1
MC100

E016
E101
E104
EI07
EI11
EI12
EI16
EI22
EI31
EI36
EI37
EI41
EI42
EI43
EI50
EI51
E154
EI55
EI56
EI57
EI58
EI60
EI63
EI64
EI66
EI67

Function
8-Bit Synch Binary Counter
Quad 4-lnput OR/NOR Gate
Quint 2-lnput AND/NAND Gate
Quint 2-lnput XORIXNOR Gate
I :9 Differential Clock Driver
Quad Drive, Common Enable
Quint Diff Line Receiver
9-Bit Buffer
4-Bit D Flip-Flop
6-Bit Universal Counter
8-Bit Ripple Counter
8-Bit Universal Shift Register
9-Bit Shift Register
9-Bit Hold Register
6-Bit D latch
6-Bit D Register
5-Bit 2:1 Mux Latch
6-Bit 2:1 Mux latch
3-Bit 4:1 Mux Latch
Quad 2: I Mux, Separate Selects
5-Bit 2:1 Multiplexer
12-Bit Parity GenlChecker
2-Bit 8:1 Multiplexer
16:1 Multiplexer
9-Bit Magnitude Comparator
6-Bit 2:1 Mux Register

Page
2-{3
2-9
2-11
2-13
2-15
2-18
2-20
2-22
2-24
2-26
2-{33
2-{36
2-{38
2-40
2-42
2-44
2-46
'2-48
2-50
2-52
2-54
2-56
2-58
2~0
2~2
2~4

MC101
MCIOO

Function

Page

EI71
EI75
EI93
EI95
EI96
EI97'
EllVE210t
E211
E212
E241
E256
EllVE310t
E336
E337
E404
E411'
E416
E431
E445
E446
E451
E452
E457
EI651'
EI652'

3-Bit 4:1 Multiplexer
9-Bit latch wI Parity GenlChecker
8-Bit EDAC/Parity
Programmable Delay Chip
Programmable Delay Chip
High Speed Data Separator
Dual I :4, 1:5 Differential Fanout Buffer
1:6 Differential Clock Distribution
3-Bit Scannable ECl Driver
8-Bit Scannable Register
3-Bit 4:1 Mux latch
2:8 Differential Fanout Buffer
3-Bit Registered Bus Transceiver
3-Bit Scannable Bus Tracnsceiver
Quad High Freq Diff AND
1:9 Diff ECUPECl RAMBus Clk Buffer
Quint High Freq Line Receiver
3-Bit Diff Set/Reset Flip-Flop
I :4 SeriaVParaliel Converter
4: I Parallel/Serial Converter
6-Bit DReg Diff D and Clk
5-Bit DReg Diff D Clk and Q
Triple High Freq Diff 2:1 Mux
Dual Analog Comparator
Dual Analog Comparator

2-66
2-68
2-70
2-72
2-75
2-80
4-7
2-95
2-100
2-102
2-104
4-14
2-108
2-110
2-113
2-115
2-119
2-121
2-123
2-129
2-133
2-135
2-137
2-140
2-144

'IOE version only
t Available in lOOElIOOlVE versions only.

ECLinPS Lite Devices
MC1D1
MC100
ElOI
El04
El05
El07
ELII
ELl2
Ell3"
ELI 4"
EllS
Ell6
El17"
EL29"
El30"
El31
El32
El33
El34
El35
El38"
El39"

MOTOROLA

Function
4-lnput OR/NOR
2-lnput AND/NAND
2-lnput Differential AND/NAND
2-lnput XORIXNOR
1:2 Differential Fanout Buffer
low Impedance Driver
Dual 1:3 Fanout Buffer
1:5 Clock Distribution Chip
I :4 Clock Distribution Chip
Differential Line Receiver
Quad Differential Receiver
Dual Diff Data/Clock D Flip-Flop SR
Triple D Flip-Flop With Set & Reset
D Flip-Flop With Set and Reset
Integrated +2 Divider, Diff Input
Integrated ->4 Divider, Diff Input
+2, ->4, +8 Clock Generation Chip
JK Flip-Flop
+2, ->4/6 Clock Generation Chip
+214, ->4/6 Clock Generation Chip

MCIDI
MC10D

Page
3-7

ELSI
El52
ELS6*'
El57
ELS8
ELS9*'
El89'
El90
El91
ElT20
ElT21
ELT22
ElT23t
ElT24
ElT25
ElT26
ElT28

3-8
3-9
3-11
3-12
3-14
4-20
4-22
3-17
3-20
4-27
4-29
4-{31
3-25
3-27
3-29
3-{31
3-{33
4-{35
4-{39

Function
D Flip-Flop wI Reset and Diff Clock
D Flip-Flop wI Diff Data and Clock
Dual Differential 2:1 Multiplexer
4:1 Differential Multiplexer
2:1 Multiplexer
Triple 2:1 Multiplexer
Coaxial Cable Driver
Triple ECl to PECl Translator
Triple PECl to ECl Translator
TTL to Differential PECl Translator
Differential PECl to Tll Translator
Dual TTL to Diff PECl Translator
Dual Diff PECl to TTL Translator
Dual TTL to Diff ECl Translator
Dual Diff ECl to TTL Translator
I :2 Fanout Diff PECl to TTL Trans
TTL to Diff PECUDiff PECl to TTL

Page
3-37
3-{39
4-44
3-42

3-44
4-47
3-46
4-49
4-52
3-51
3-53
3-55
3-57
3-59
3-81
3-83
3-64

, Available in I OEl version only. t Available in I OOElT version only.
*' Available in I OOEl version only.

1-2

ECLinPS and ECLinPS Lite
Dl140- Rev 4

Device Nomenclature
Low Voltage ECLinPS and ECLinPS Lite Devices
MC100

Function

lVElll
LVE164
lVE210
LVE222
LVE310
LVELII
lVEL13
LVEL14
LVEL16
LVEL17
LVEL29

Page

1:9 Differential Clock Driver
16:1 Multiplexer
Dual 1:4, 1:5 Diff Fanout Buffer
1:15 Diff ECUPECL Clock Driver
2:8 Differential Fanout Buffer
1:2 Differential Fanout Buffer
Dual 1:3 Fanout Buffer
1:5 Clock Distribution Chip
Differential Receiver
Quad Differential Receiver
Dual Diff Data/Clock D Flip-Flop SR

MC100

4-2
4-5
4-7
4-11
4-14
4-18
4-20
4-22
4-25
4-27
4-29

Function

Page

Triple D Flip-Flop With Set & Reset
+2 Divider
+2, +4/6 Clock Generation Chip
+214, +4/6 Clock Generation Chip
Differential Clock D Flip-Flop
Dual Differential 2:1 Multiplexer
Triple 2:1 Multiplexer
Triple ECl to PECL Translator
Triple PECl to ECL Translator
Triple PECl to LVPECL Translator

LVEL30
LVEL32
LVEL38
LVEL39
LVEL51
LVEL56
LVEL59
LVEL90
LVEL91
lVEl92

4-31
4-33
4-35
4-39
4-42

4-44
4-47
4-49
4-52
4-55

SECTION 2

Device Nomenclature
ECLinPS, ECLinPS Lite
MC
Motorola
Circuit Identifier

=
=

WWW

xxx

1:
VVV

ZZ
1

T
~

• MC Fully Qualified Circuit
• XC Non Reliability Qualified

Package Type
•
•
•
•

=
=

FN PLCC
D Plastic SOIC
l = Ceramic DIP
P = Plastic DIP

Function Type
• YYY 3-Digits for ECLinPS
• YY= 2-Digits for ECLinPS Lite

Compatibility Identifier _ _ _ _ _ _--1
• 10 = 10H Compatible (0 to +85'C)
• 100 lOOK Compatible (0 to +85'C)

1.-_ _ _ _ _ _ _ _ _ ECLlnPS Family Identifier

•
•
•
•
•

=
=

E ECLinPS
EL ECLinPS Lite
ELT = ECLinPS Lite Translator
LYE = Low Voltage ECLinPS
lVEL = Low Voltage ECLinPS Lite

SECTION 3
Selection Guide
Gates

Buffers
E122

Single 4-lnput ORiNOR

EL01

9-Bit Buffer

Quad 4-lnput ORiNOR

El01

1:2 Differential Fanout Buffer

Single 2-lnput AND/NAND

El04

1:4 Clock Distribution Chip

EllS

Quint 2-lnput AND/NAND

El04

1:9 Differential Clock Driver

ElLVElll:j:

Single 2-lnput Differential AND/NAND

El05

1:9 Diff ECUPECL RAMBus Clock Buffer

Single 2-lnput XORIXNOR

El07

Dau11:3 Fanout Buffer

Quint 2-input XORIXNOR

E107

Single Driver With Enable

Quad 2-lnput AND/NAND, Differential

E404

Dual 1:4, 1:5 Differential Fanout Buffer

EllVE210t

• Available In lOx Version Only.

2:8 Differential Fanout Buffer

EllVE310t

Quad Driver with Enable

E112

3-Bit Scannable Driver

E212

:\:

Available in 100x Version Only.
ECLinPS/Lite Versions is 1Oxll OOx. low-Voltage in l00x Only.

ECLinPS and ECLinPS Lite
DL140-Rev4

1-,3

EULVEL11:\:

E4W
EUlVEL13t
E112

MOTOROLA

Selection Guide

Selection Guide (continued)
Parity Generator/Comparator

Flip-Flops/Registers
Single 0 (Set & Reset)
Dual Differential 0
4-Bit 0 (Async Set & Reset)

12-Bit Parity Generator/Checker

El31
EUlVEL29t
E131

TripleD

EUlVEl30t

Single 0 (Reset & Differential Clock)

EUlVEl51:j:

E160

9-Bit Magnitude Comparator

E166

B-Bit Error DetectionlCorrection (EDAC)

E193

9-Bit Latch w/Parity GenlChecker

E175

Line Receivers

6-Bit 0 (Async Reset)

E151

Quint Differential Line Receiver

6-Bit 0 (Differential Data & Clock Inputs)

E451

Differential Line Receiver

EUlVEL16:j:
EUlVEL17t

E116

9-Bit Hold Register

E143

Quad Differential Line Receiver

3-Bit 0 (Edge Triggered Set & Reset)

E431

6-Bit DReg., Diff Data & ClK Inputs

E451

SingleJK

El35

Quint High Freq. Differential Line Receiver

E416

Single 0 (Differential Data & Clock)

El52

5-Bit Differential 0 Register

E452

Bus Transceivers
3-Bit Registered Bus Transceiver

latches

3-Bit Scannable Register Bus Transceiver

6-Bit 0 (Async Reset)

Translators

9-Bit latch w/Parity Gen/Checker
Multiplexers

Triple ECl to PECl Translator

EUlVEl90t

Triple PECl to ECl Translator

EUlVEl91t

Single 4:1 Differential Multiplexer

ELS7

Triple PECl to lVPECl Translator

lVEl92t

Single 2:1 Multiplexer

ELSB

Tll to Differential PECl Translator

ElT20

Dual Differential 2:1 Multiplexer

EUlVEl56t

Differential PECl to TTL Translator

ElT21

Triple 2:1 Multiplexer

EUlVEl59t

Dual TTL to Differential PECl Translator

ElT22

5-Bit 2:1 Multiplexer

E15B

Dual Differential PECl to TTL Translator

ElT23t

3-Bit 4:1 Multiplexer

E171

Dual TTL to Differential ECl Translator

ELT24

2-Bit B:l Multiplexer

E163

Dual Differential ECl to TTL Translator

ElT25

Single 16:1 Multiplexer

E164

1:2 Fanout Differential PECl to TTL Translator

ElT26

Quad 2:1 Mux, Individual Select

E157

TTL to Diff PECUDiff PECl to TTL Translator

ElT2B

Triple 2:1 Mux, Differential

E457

Miscellaneous

Mux-latches

Integrated +2 Divider, Differential Input

EUlVEL32:j:

5-Bit 2:1 Mux-latch

E154

Integrated +4 Divider, Differential Input

EL33

6-Bit 2:1 Mux-latch

E155

+2, +4, +B Clock Generation Chip

3-Bit 4:1 Mux-Latch

E156

+2, +4/6 Clock Generation Chip

EUlVEl3Bt

3-Bit 4:1 Mux-Latch

E256

+214, +416 Clock Generation Chip

EUlVEL39t

Mux-Registers

I 6-Bit 2:1 Mux-Register

E167

Counters

EL34

Coaxial Cable Driver

ElB9'

Programmable Delay Chip, Digital

E195

Programmable Delay Chip, Digital & Analog

E196

Hard Disk Data Separator

E197"

B-Bit Synchronous Binary Counter

E016

1:4 Serial/Parallel Converter

E445

6-Bit Synchronous Universal Counter

E136

4: 1 Parallel/Serial Converter

E446

B-Bit Ripple Counter

E137

Dual Analog Comparator with latch

EI651"

Dual Analog Comparator wI latch & Hysteresis

E1652"

Shift Registers
B-Bit Shift Register (bidirectional)
B-Bit Scannable Register (unidirectional)

E241

9-Bit Shift Register (unidirectional)

E142

9-Bit Hold Register

E143

3-Bit Scannable Driver

E212

MOTOROLA

• Available in 1Ox Version Only.
t Available in 100x Version Only.
:j: ECLinPS/Lite Versions is lOx/I OOx. Low-Voltage in 100x Only.

E141

1-4

ECLinPS and ECLinPS Lite
Dl140-Rev4

MOTOROLA
SEMICONDUCTOR GENERAL INFORMATION

SECTION 4
Family Overview
Transmission Line Drive Capability
The low output impedance, high input impedance and
high current drive capability of ECl makes it an ideal
technology for driving transmission lines. Regardless of the
technology, as system speeds increase, interconnect
becomes more of a transmission line phenomenon. With
ECl no special line driving devices are necessary, as all
ECl devices are line drivers.

Introduction
Advances in bipolar processes led to a proliferation of very
high speed lSI and VlSI gate arrays in high end computer
applications. The advent of these high speed arrays created
a need for a high speed logic family to tie or "glue" them
together. Because arrays have a finite amount of circuitry and
I/O pins, glue functions which are sensitive to either of these
parameters may be better performed off of the array. In
addition glue functions which require very tight skew control
may be difficultto perform on an array due to the inherent skew
of the large packages associated with large gate arrays.
Therefore although the trend is to push more and more of the
logic onto the array, there are design constraints which make
performing some of the logic, such as clock distribution,
multiplexing, decoding, latching, memory addreSSing and
translating, in glue an attractive altemative.
The high end computer segment is not the only market
segment pushing for higher performance logic parts. ATE,
instrumentation and communication designs can have data
rate requirements ranging from 300MHz to as high as 2.5GHz.
Because large high speed arrays do not always lend
themselves to passing high frequency signals on and off chip,
portions of the designs must be realized with discrete logic.
The current bipolar logic families are not capable of operating
at these high frequencies.
To answer the call for a very high speed bipolar logic family
Motorola designed and produced the ECLinPS· (ECl in Pica
Seconds) logic family. The family is designed to meetthe most
stringent of system requirements in speed, skew and board
density as well as maintaining compatibility to existing ECl
families.

Constant Power Supply Current Drain
Because of the differential amplifier design used for ECl
circuits, the current is not switched on and off but rather simply
steered between two paths. Thus the current drain of an ECl
device is independent of the logic state and the frequency of
operation. This current stability greatly simplifies system
power supply design.
Input Pulldown Resistors
ECl inputs have 50KQ - 75Kn internal pulldown resistors
which pull the input to VEE (logic lOW) when left open. This
allows unused inputs to be left open and greatly simplifies
logic design.
Differential Drive Capability
Because of the presence of high current drive
complimentary outputs, ECl circuits are ideally suited for
driving twisted pair lines or cables over long distances. With
common mode noise rejection of 1V or more, ECl line
receivers are less susceptible to common mode noise. In
addition, their differential inputs need only a few hundred
millivolt voltage differences to correctly interpret the logic.

High Speed Design Philosophy

Eel Design Benefits
Today a truly high speed logic family needs more than
simply short propagation delays. The minimization of all types
of skew, as well as a level of logic density which affords a
smaller amount of board space for an equivalent function, are
also necessities of a high speed family. The following
summary will outline the steps taken by Motorola to achieve
these goals in the development of the ECLinPS logic family.

The speed benefits of an ECl design over those of
alternative logic technologies are well documented, however
there are a number of other important features that make
ECl an attractive technology for system designs. The
ECLinPS logic family, as with other ECl families, affords the
following advantages:

Fast Propagation Delays
The ECLinPS family boasts 500ps maximum packaged
gate delays and typical flip-flop toggle frequencies of 1.4GHz.
Simple gate functions show typical propagation delays of
360ps at 25mW of power for a speed power product of only
9pJ. For higher density devices internal gates run at 100ps
with 5mW of power for a speed power product of only O.5pJ.

Complimentary Outputs
Complimentary outputs are available on many functions
with equal propagation delays between the two paths. This
alleviates the need for external inverters and saves system
power and board space while maintaining exceptional
system timing .

• Any reference to ECLinPS in this section includes the ECLinPS Lite and Low Voltage ECLinPS families.

ECLinPS and ECLinPS Lite
DL140-Rev4

1-5

MOTOROLA

Family Overview
Advanced Bipolar Processing

Internal Differential Interconnect
The propagation delay window size, skew between rising
and falling inputs and susceptibility to noise are all
phenomenon which are exacerbated by VBB switching
reference variation. By extensively using differential
interconnects internal to the chip, the ECLinPS family has
been able to achieve superior performance in these areas.
Propagation Delay Temperature Insensitivity
The variation of propagation delay through an ECLinPS
device across temperature is typically less than 50ps. This
stability allows for faster designs due to tighter delay windows
across temperature.

Input Impedance and Loading Capacitance
The input structures of the ECLinPS family show a positive
real impedance across the applicable input frequency range.
This ensures that the system will remain stable and operate
as designed over a wide range of input frequencies. The input
loading capacitance typically measures only 1.5pF and is
virtually independent of input fanout as the device capacitance
is less than 5% of the total. Because the propagation delay of
a signal down a transmission line is adversely affected by
loading capacitance, the overall system speed is enhanced.

The ECLinPS logic family is fabricated using Motorola's
MOSAIC III process, a process which is two generations
ahead of the process used in the development of the 10H
family. The small geometries and feature sizes of the MOSAIC
III process enable the ECLinPS logic family to boast of a nearly
three-fold improvement in speed at less than half the power of
existing ECl logic families.
The MOSAIC III process is a double polysilicon process
which uses a unique self-alignment scheme for device
electrode and isolation definition. The process features self
aligned submicron emitters as well as polysilicon base,
collector and emitter electrodes. In addition, polysilicon
resistors, diodes and capacitors are available to minimize
the parasitic capacitance of an ECl gate. Figure 1.1
shows a cross section for an NPN device using the
MOSAIC III process.

Input Buffers
To minimize propagation delays in a system environment,
inputs with a large internal fanout are buffered to minimize the
loading capacitance on the transmission line.

Figure 1.1. MOSAIC III Cross Section

High Level of Integration

By incorporating the use of polysilicon contacts and
resistors through the MOSAIC III process, the parasitic
capacitances of an ECLinPS gate are minimized, thus
minimizing the time constants which comprise the switching
delays of the gate. The resultant gates show delays of 1OOps
for internal gates and 200ps for output gates capable of
driving 500 loads. The small geometries of the process,
nearly 350% reduction in device area compared to a 10H
device, allow these internal gate delays to be achieved at
only 800fl,A of current.

28-pin designs allow for the design of 9-bit functions for
implementation in byte plus parity applications. Full byte plus
parity implementation reduces total package count and saves
expensive board space.
Space Efficient Package
Surface mount PlCC package affords a high level of
integration with a minimum amount of required board space.
Quad layout of the package equalizes pin lengths thus
minimizing the skew between similar internal paths.

Universal Compatibility

Flow Through Pin Assignment

Each member of the ECLinPS family is available in both of
the existing ECl standards: 10E series devices are
compatible with the MECl 10H family; 100E series devices
are compatible with ECl 100K. In addition, to maintain
compatibility with temperature-compensated, three-level
series-gated gate arrays, the 1OOE devices are guaranteed to
operate without degradation to a VEE of - 5.46V.
The section below presents a comparison between the two
standards in the new context of the ECLinPS family. The user
is also referred to the Electrical Characteristics section of this
book as well as appropriate family data books and other
literature for descriptive information on the earlier ECl
families.

Input and output pins have been laid out in a flow through
pattern with the inputs on one side of the package and the
outputs on the other. This flow through pattern helps to simplify
the PC board layout operation.
Multiple VCCO pins
To minimize the noise generated in simultaneous
switching situations, a minimum of three single-ended
outputs per VCCO has been employed in the family.
Optimum placement of these VCCOs also results in superior
output-to-output skew.

MOTOROLA

1-6

ECLlnPS and ECLinPS Lite

DL140-Rev4

Family Overview
Because no supplier previous to Motorola has offered both
ECl standards on an identical process, comparison of
existing 10H and 100K style devices has some limitations.
Comparison of the two standards fabricated with two different
processes has sometimes led to the erroneous conclusion
that there are inherent AC performance differences between
them. In reality this is not the case. The only inherent
difference between the two standards is the difference in the
behavior of the DC characteristics with temperature.

The 28-pin PlCC package emerged as the clear favorite
both internally and with the high speed market in general. The
package offers a quad layout to minimize both lead lengths
and lead length differences. As a result, the parasitics and
delays of the package are very well suited for a high speed
logic family. In addition, the nearly matched lead lengths allow
for tighter skew among similar paths through the chip.
The board density potential of the PlCC is also attractive in
that it allows for a nearly 100% reduction in board space when
compared to the DIP alternative. The package is
approximately a half inch square with 50 mil spaced J-bend
leads. More detailed measurements can be found in the
package section of this data book. The J-bend leads provide
a srnallerfootprint than a gull wing package and propose fewer
temperature expansion coefficient mismatch problems than
the leadless alternative.
Thermally, the standard PlCC exhibits a ElJA of 43.soC per
watt at 500lfpm air flow. With this thermal resistance most
28-pin functions can be implemented with the MOSAIC III
process without encountering any severe thermal problems.
For more details on thermal Issues of the ECLinPS family refer
to the thermal section of this data book.

AC Performance
From an IC design standpoint the only differences between
a 10E device and a 100E device in the ECLinPS family is a
small temperature compensation network in the 100E output
gate, and very minimal differences in the two bias generator
networks. Therefore one would expect that from an AC
stand-point the performance of the two standards in the
ECLinPS family should be nearly identical; measurements
prove this to be the case. There is no significant measurable
difference in the riselfall times, propagation delays or toggle
frequencies when comparing a 10E and 100E device. The
minor difference between previous 10H and lOOK designs is
due to the fact that the two are fabricated on different
processes, and in some cases are designed for operation at
different power levels.

Abbreviation Definitions
The following is a list of abbreviations found in this data book
and a brief definition of each.

Summary
Summarizing the above information, in general, the two
ECl design standards, although differing somewhat in DC
parameters, are nearly identical when one compares the AC
performance for a given device. There may be very small
differences in the AC measurements due to the slightly
smaller output swing of the 100E device. However, these
differences are negligible when compared to the absolute
value of the measurements. Therefore, from an AC
stand-point, there is no real advantage in using one standard
over the other, thus removing AC performance as a decision
variable in high-speed system design.

Current
ICC

Total power supply current drawn from the positive
supply by an ECLinPS unit under test.

lEE

Total power supply current drawn from an ECLinPS
device under test by the negative supply.

IlL

Current drawn by the input of an ECLinPS device with a
specified low level (VIL min) forced on the input.

IINH

Current drawn by the input of an ECLinPS device with a
specified high level (VIH max) forced on the input.

lOUT

The current sourced by an output under specified load
conditions.

Packaging
During the definition phase of the ECLinPS family, much
attention was placed on the identification of a suitable
package for the family. The package had to meet the criteria
of minimum parasitics and propagation delays along with an
attractive 1/0 vs board space relationship. Although the DIP
package offered a level of familiarity and convenience, the
performance of the package with a very high speed logic
family was inadequate. In addition to the obvious parasitics
and board space problems, the propagation delays through
the DIP package were nearly twice as long as the delay
through the silicon.

ECLinPS and ECLinPS Lite
DL140-Rev4

Voltage
VBB

The switching reference voltage.
Base-to-emittervoltage drop of a transistor at specified
collector and base currents.

VCB

1-7

Collector-to-base voltage drop of a transistor at
specified collector and base currents.

MOTOROLA

Family Overview

VCC

The most positive supply voltage to an ECLinPS
device.

VCUT

The logic LOW voltage level for ECL BUS outputs
which attain cutoff of the output emitter follower.

VCCO

Power supply connection to the output emitter follower
of an ECLinPS gate. For the ECLinPS logic family V CC
and VCCO are common nodes.

VSUP

The maximum voltage difference between VEE and
Vccforthe E1651 comparator.

Timing Parameters
The most negative supply voltage to an ECLinPS
device.

[]]

VIH

Nominal input logic HIGH voltage level.

VIH max

Maximum (most positive) logic HIGH voltage level for
which all parametric specifications hold.

VIHmin

Minimum (least positive) logic HIGH voltage level for
which all parametric specifications hold.

VIL

Nominal input logic LOW Voltage.

VILmax

VILmin

VOH

VOHA

VOHmax

VOHmin

VOL

Waveform rise time of an output signal measured from
the 20% to 80% levels of the signal.
tF

Waveform fall time of an output signal measured from
the 20% to 80% levels of the signal.

TpD:l±

Propagation delay of a signal measured for a
rising/falling input to a risinglfalling output.

xpt

The crossing point of a differential input or output
Signal. The reference point for which differential delays
are measured.

Maximum (most positive) logic LOW voltage level for
which all parametric specifications hold.

TpLH

The propagation delay for an output transitioning from
a logic LOW level to a logiC HIGH level.

Minimum (least positive) logic HIGH voltage level for
which all parametric specifications hold.

TpHL

The propagation delay for an output transitioning from
a logic HIGH level to a logic LOW level.

Output logic HIGH voltage level for the specified load
condition.

fMAX

Maximum input frequency for which an ECLinPS flip
flop will function correctly.

Output logic HIGH voltage level with the inputs biased
at VIH min or VOL max.

fCOUNT

Maximum input frequency for which an ECLinPS
counter will function properly.

Maximum (most positive) logic HIGH output voltage
level.

fSHIFT

Maximum input frequency for which an ECLinPS shift
register will function properly.

Minimum (least positive) logic HIGH output voltage
level.

tSKEW

The maximum delay difference between similar paths
on a single ECLinPS device.

Output logic LOW voltage level for the specified load
condition.

Setup time: the minimum amount of time an input must
transition before a clock transition to ensure proper
function of the device.

Hold time: the minimum amount of time an input must
remain asserted after a clock transition to ensure
proper operation of the device.

VOLA

Output logic LOW voltage level with the inputs biased
at VIH min or VOL max.

VOL max

Maximum (most positive) logic LOW output voltage
level.

VOL min

Minimum (least positive) logic LOW output voltage
level.

Output termination voltage for ECLinPS open emitter
follower outputs.

Vpp

Minimum peak-to-peak input voltage for differential
input devices.

VCMR

The voltage range in which the logic HIGH voltage level
of a differential input signal must fall for a differential
input device.

Release time or Reset Recovery Time: the minimum
amount of time after a signal is de-asserted that a
different input must wait before assertion to ensure
proper functionality of the device.
tw min

MOTOROLA

1--8

Minimum pulse width of a Signal necessary to ensure
proper functionality of a device.

ECLinPS and ECLinPS Lite
DL140-Rev4

Family Overview
Temperature
TSTG

Miscellaneous

The maximum temperature at which a device may be
stored without damage or performance degradation.

DUT

Device under test.

GIN

Input capacitance of a device.

Junction (or die) temperature of an integrated circuit
device.

Input impedance of a device.

Ambient (environment) temperature existing in the
immediate vicinity of an integrated circuit package.

0JA

Thermal resistance of an integrated circuit package
between the junction and the ambient.

GOUT

Output capacitance of a device.

ZOUT

Output impedance of a device.

The total dc power applied to a device, not including
any power delivered from the device to the load.

Thermal resistance of an integrated circuit package
between the junction and the case.

Load resistance.

Thermal resistance of an integrated circuit package
between the case and the ambient.
Ifpm

Transmission line termination resistor.
Rp

An input pull-down resistor.

PUT

Pin under test.

SMA

Industry standard PGB connector.

Linear feet per minute.

EGLinPS and EGLinPS Lite
DL140-Rev4

1-9

MOTOROLA

MOTOROLA
SEMICONDUCTOR GENERAL INFORMATION

SECTION 5
Electrical Characteristics
DC Characteristics

EClinPS' Transfer Curves
As mentioned in the previous section, exceptforthe E1651,
E1652and E197 all ECLinPS devices are offered in either10E
or 1OOE versions to be compatible with 1OH or 1OaK ECl logic
respectively. The following information will overview the DC
characteristics of the two versions of ECLinPS devices, for
more detailed discussions the reader is referred to the MECl
and F100K data books.
Both 10E and 100E devices produce ~ 800mV output
swings into a specified 50'1 to - 2.0V load. However, because
of the low output impedance (Figure 2.1) of both standards,
neither is limited to 50'1 loads. Larger load resistances can be
used to reduce the system power without sacrificing the speed
of the device. Of course the overall system speed will be
reduced due to the increased delays of the interconnect
traces. In addition, to better drive high capacitive lines, smaller
resistances, down to 250, can be used without violating the
50mA max output current specification. It is however
recommended that for lines of less than 35'1, specialized 25'1
driver circuits or "ganged" output schemes should be used to
ensure optimum long term reliability of the device.

The 10E devices are voltage compensated but not
temperature compensated, therefore, although the output
voltage levels are insensitive to variations in VEE, they do vary
with temperature. The transfer curves in Figure 2.2 pictorially
illustrate the behavior of the 1OE outputs. In order to maintain
noise margins over temperature, it is important that the VBB
switching reference tracks with temperature in such a way as
to remain centered between the VOH and VOL levels. As
shown in Table 2.1 , the temperature tracking rates of the VOH
and VOL for a 10E device are not equal. Therefore, it is
necessary to design the VBB reference such that it tracks at a
rate equal to the average rate of the difference between the

-O.B

~
w

-1.2

::::>

-1.6

::::>

-1.8

1-1.48, -1.63 1'-

-1.13, - 0.98

II-

1\ /

-1.4

1---1 1.48, - 0.98

(!l

-1.0

-1.13,-1.63

=-®
1
I IVEE

= - 4.94V TO - 5.46V

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0 -0.8

INPUT VOLTAGE (V)
-0.8

.s
I-

25°C r\0C
0;"'\

-1.0

a:
a:

::::>

~
w
(!l

-1.2

-1.4

0
I-

::::>

I-

::::>

I-

::::>

-1.6
-1.8

-1.75 -1.5

-1.25 -1.0 -0.75 -0.5 -0.25

-2.0

OUTPUT VOLTAGE (V)

,/ /

II~

\\ \.

~
-1.8

~
-1.6

-1.4

-1.2

-1.0 -0.8

INPUT VOLTAGE (V)
Figure 2.2. ECllnPS 1DE Transfer Curves

Figure 2.1. Output Characteristics vs load

• Any reference to EClinPS in this section Includes the ECllnPS lite and Low Voltage EClinPS families.

MOTOROLA

1-10

ECLinPS and ECLinPS Lite

DL140-Rev4

Electrical Characteristics

high and low output level tracking rates. Table 2.1 also
outlines the temperature tracking behavior of a 10E VBB
switching reference.
min

typ

~VOH/~T

(mV/'C)

1.1

1.2

1.4

~VOL/~T

(mV/'C)

0.4

0.6

~VBslAT

(mVl'C)

1.0

10E

max

0.6

0.8

~VOH/~VEE

(mVN)

~VOl!~VEE

(mVN)

min

typ

max

AVBB/AVEE (mVN)
100E
~VOH/~T

(mV/'C)

-0.15

0.15

~VOL/~T

(mV/'C)

-0.30

0.30

~VBB/AT

(mVl'C)

-0.20

0.20

20
30
20

~VOH/~VEE

(mVN)

~VOl!~VEE

(mVN)

~VBsI~VEE

(mVN)

Table 2.1. ECLinPS Voltage Level Tracking Rates
The 1OOE devices, on the other hand, are temperature and
voltage compensated, therefore, the output levels remain
fairly constant over variations in both VEE and temperature.
Figure 2.3 shows the transfer characteristics for a 100E
device. The associated tracking rates are illustrated in Table
2.1. Notice that in this case the VBB switching reference is
designed to remain constant over temperature to maintain an
optimum position within the output swing of the device. This
flat temperature tracking of the internal reference levels leads
to a phenomena particular to the 100E devices.
-0.8
-1.0
~
w

'"~
§?

....
=>

D..
....
=>

-1.2

1-1.475,-1.6101

10E

X
/

-1.8 ~OR

NORr

-1.4

-1.2

-1.0 -O.B

INPUT VOLTAGE (V)
Figure 2.3. ECLinPS tODE Transfer Characteristics

ECLinPS and ECLinPS Lite
DL140-Rev4

min

typ

150
150

240
280

140
145

210
230

Table 2.2. DC Noise Margins

II VEE=-4.20VTO-5.46V 1
-1.6

typ

\-1.165,-1.610

-1.B

tOOE

min

-1.165,-1.035

-2.0

The noise margin of a device is a measure of a device's
resistance to undesirable switching. For ECLinPS, as well as
all ECL devices, noise margin is a DC specification. The noise
margin is defined as the difference between the voltage level
of an output of the sending device and the required voltage
level of the input of the receiving device. Therefore a worst
case noise margin can be calculated from the ECLinPS data
sheets by simply subtracting the VIL max or VIH min from the
VOL min or VOH max respectively. Table 2.2 below illustrates
the worst case and typical noise margins for both 10E and
100E ECLinPS devices. Notice that the typical noise margins
are approximately 100mV larger than the worst case.

I
1-1.475,-1.0351
1
O'Cto 85'C

-1.6

Noise Margin

NMHIGH(mV)
NMLQW(mV)

-1.4

Since the VBES of the current source transistor reduce with
temperature, if the current source reference remains
constant, as is the case for 100E devices, the lEE of the
device will vary with temperature. Careful scrutiny of the data
sheets will reveal that the worst case lEE for a function is
higher for the 100E version than the 10E version of that
device. As a result, from a power standpoint a 100E device
operating at 85'C with a - 4.5V VEE will be nearly identical to
a 10E device operating with a - 5.2V VEE under identical
temperature conditions.
Although differing somewhat in many DC parameters, 10E
and 100E devices do share a couple of the same DC
characteristics. Both designs show superior lEE vs VEE
tracking rates due to the design of the voltage regulator. With
a tracking rate of <3%N, this variation can effectively be
ignored during system design. The output level and reference
level variation with VEE are also outstanding as can be seen
in Table 2.1.

As mentioned above, the noise margins of a device are a
DC measurement and thus can lead to some false
impressions of the noise immunity of a system. For instance,
from the chart the worst case noise margin is 140mV for a high
level of a 1OOE device. This would suggest that an undershoot
on this line of greater than 140mV could cause an error in the
system. This however is not necessarily the case as the
determination as to whether or not an AC noise Signal is
propagated is dependent on line impedances, output
impedances and propagation delays as well as noise margins.

1-11

MOTOROLA

Electrical Characteristics

AC Characteristics
Parameter Definitions
The device data sheets in Section 3 contain specifications
for the propagation delays and riselfall times for each of the
devices in the ECLinPS family. In addition, where applicable,
skew, setup/hold, maximum toggle frequencies (fMAX), reset
recovery and minimum pulse width specifications are
included. The waveforms and terminologies used in
describing the propagation delays and riselfall times of the
ECLinPS family are depicted in Figure 2.4 below.

You!

RISE AND FALL TIMES

Propagation delays and riselfall times are generally well
understood parameters, however, there is sometimes
confusion surrounding the definitions of more specialized AC
parameters such as skew, setup/hold times, release times,
and maximum frequency. The following few paragraphs will
outline the ways in which Motorola defines these parameters.

Skew Times
In the design of high speed systems skew plays nearly as
important a role as propagation delay. The majority of the
devices in the ECLinPS family have the skew between outputs
specified. This skew specification represents the typical
difference between the delays of similar paths on a single chip.
No maximum value for skew is specified due to the difficulty
in the production testing of this parameter. The user is
encouraged to contact an ECLinPS application engineer to
obtain actual evaluation data if this parameter is critical in their
designs.

Set-Up and Hold Times
Motorola defines the setup time of a device as the minimum
time, prior to the transition of the clock, that an input must be
stable to ensure that the device operates properly. The hold
time, on the other hand, is defined as the minimum time that
an input must remain stable after the transition of the clock to
ensure that the device operates properly. Figure 2.5 illustrates
the way in which Motorola defines setup and hold times.

Data

You!
50%

SINGLE·ENDED PROPAGATION DELAY

Clock
Tpd

yOU!

Tpd __

Figure 2.5. Set-Up and Hold Waveforms

Release Times
YOU!
Vou!

DIFFERENTIAL PROPAGATION DELAY

Figure 2.4. ECLlnPS TpD Measurement Waveforms

MOTOROLA

Release times are defined as the minimum amount of time
an input must wait to be clocked after an enable, master reset
or set signal is deactivated to ensure proper operation.
Because more times than not this specification is in reference
to a master reset operation, this parameter is often called reset
recovery time. Figure 2.6 illustrates the definition of release
time in the Motorola data sheets.

1-12

ECLinPS and ECLinPS Lite

DL140- Rev 4

Electrical Characteristics

Master Reset

SO%

Clock

Figure 2.6. ECLinPS Release Time Waveforms

'MAX Measurement
In general fMAX is measured in the manner shown in Figure
2.7 with the fail criterion being either a swing of 600mV or less,
or a miscount. However, in some cases, the feedback method
of testing can lead to a pessimistic value of fMAX because the
feedback path delay is such that the setup times of the device
are violated. If this is the case, it is necessary to have two free
running signal generators to ensure that the setup times are
observed. This parameter, along with fSHIFT and fCOUNT,
represents the maximum frequency at which a particular flip
flop, shift register or counter can be clocked with the divide,
shift or count operation guaranteed. This number is generated
from worst case operating conditions, thus, under nominal
operating conditions, the maximum toggle frequency is higher.
AC Testing ECLinPS Devices
The introduction of the ECLinPS family raised the
performance of silicon to a new domain. As the propagation
delays of logic devices become ever faster the task of

Data

Clock

Figure 2.7. fMAX Measurement
correlating between test setups becomes increasingly
challenging. To obtain test results which correlate with
Motorola, various testing techniques must be adhered to. A
typical schematic for an ECLinPS test setup is illustrated in
Figure 2.8.
.
A solid ground plane is a must in the test setup, as the two
power supplies are bypassed to this ground plane. A 20J.lF
capacitor from the two power supplies to ground is used to
dampen any supply variations. An RF quality 0.01 J.lF capacitor
from each power pin to ground is used to decouple the fixture.
These 0.01 J.lF capacitors should be located as close to the
power pins of the package as possible. In addition, in order to
minimize the inductance of the power pins, all of the power
leads should be kept as short as possible. The power supplies
are shifted by +2.0V so that the load comprises only the
precision 50n input impedance of the oscilloscope. Use of this
technique will assure that the customer and Motorola are
terminating devices into equivalent loads and will improve test
correlation.

CHANNEL A

son COAX

PULSE
GENERATOR

son COAX
VCCO"
(+2.0V) - - - - - - t - - . j

OSCILLOSCOPE

VCC
(+2.0V)

CHANNELB
SOW COAX

son
-3.2V·
• VEE=-3.2V FOR 10Exxx, -2.SV FOR 100Exxx
.. MULTIPLE Vccos EXIST ON MOST PARTS

Figure 2.8. Typical ECLinPS Test Setup

ECLinPS and ECLinPS Lite

DL140-Rev4

1-13

MOTOROLA

Electrical Characteristics
To further standardize testing, any unused outputs should
be loaded with son to ground.
Because the power supplies are shifted, the input levels
must also be shifted by an equal amount. Table 2.3 gives the
typical input levels for the ECLinPS family and their
corresponding +2.0V shifted levels.

10Exxx

Typical

Shifted

VIL

-1.7SV

+ O.2SV

VIH

-O.90V

+1.10V

100Exxx

Typical

Shifted

VIL

-1.70V

+ O.30V

VIH

-O.9SV

+1.0SV

Table 2.3. ECl levels after Translating by +2.0V

The test fix1ure should be in a controlled impedance son
environment, with any non-SOn interconnects, or stubs,
kept as short as possible «1/4"). This controlled impedance
environment will help to minimize overshoot and ringing,
two phenomena which can lead to inaccuracies in AC
measurements. To minimize degradation of the input and
output edge rates, a son coaxial cable with a teflon
dielectric is recommended, however any other cable with a
bandwidth of >5.0GHz is adequate. In addition, the cables
from the device under test (OUT) to the inputs of the scope

should be matched in length to prevent any errors due to
different path lengths from the OUT to the scope. The
interconnect fittings should be son SMA straight or SMA
launchers to minimize impedance mismatches at the
interface of the coax and test PC board. Although a teflon
laminate board is preferable, an FR4 laminate board is
acceptable as long as the signal traces are kept to five
inches or less. Longer traces will result in significant edge
rate degradation of the input and output signals.
To make the board useful for incoming inspection or other
volume testing, the board needs to be fitted with a socket.
Although not suitable for AC testing due to different pin lengths
and large parasitics, there are through hole sockets which are
adequate for DC testing of ECLinPS devices. For AC testing
purposes a 28-pin PLCC surface mount socket is
recommended.
To ease the correlation issue, Motorola has developed a
universal AC test board which is now available to customers.
The board is fitted with a PLCC socket and comes with
instructions on how it can be configured forthe different device
types in the family. For ordering information see the
description on the following page.
Finally, to ensure correlation between Motorola and the
customer, high-performance, state-of-the-art measuring
equipment should be used. The pulse generator must be
capable of producing the required input levels with rise and fall
times of 500ps. In addition, if fMAX is going to be tested, a
frequency of up to 1.5GHz may be needed. The oscilloscope
should also be of the utmost in performance with a minimum
bandwidth of 5.0 GHz.

Figure 2.9. EClinPS AC Test Board

MOTOROLA

1-14

ECLinPS and ECLinPS Lite

DL140-Rev4

MOTOROLA
SEMICONDUCTOR GENERAL INFORMATION

SECTION 6
Engineering Evaluation Board
for 28-Pin ECl Devices in the PlCC Package
Part # ECLPSBD28

DESCRIPTION
This board is designed to provide a low cost characterization tool for evaluating ECl devices in the ECLinPS Product Family.
The board provides a high bandwidth 50n controlled impedance environment. The board is universal and can be configured by
the user for any of the 28-pin PlCC devices in the family depending on the input, output, and power pinout layout of the device.
The table below indicates common input/output/power devices.
Group

Base Device

Pin Compatible Devices

CONF1
CONF2
CONF3
CONF4
CONF5
CONF6
CONF7
CONF8
CONF9
CONF10
CONF11
CONF12
CONF13
CONF14
CONF15

E196
E142
E337
E212
E156
E158
E154
E101
E112
E431
E111
E164
E451
E163
E193

E195
E016,E141,E143,E241
E336
E104,E107,E150,E151
E155,E167,E171,E256
E116,E122,E175,E416
E452
E131,E157,E404
E457
E160
E166

Table 1_ Cross Reference of Board Configurations

The board is designed to test devices using the fly-by (Kelvin contact) test method, therefore one input force trace and one
input sense trace exist for each input pin. This allows termination of the input and output signals into the highly accurate 50 ohm
impedance of an oscilloscope. The layout is engineered to have equal length traces from the device under test (DUT) socket to
the sense outputs which simplifies the calibration requirements for accurate AC measurements.
The kit provides a printed circuit board with an attached surface mount socket as well as assembly instructions. For superior
impedance control from the cable to the board, Motorola recommends the use of SMA coaxial connectors.

ECLinPS and ECLinPS Lite
DL140-Rev4

1-15

MOTOROLA

Engineering Evaluation Board

MOTOROLA

rn
o

A. LOCATION OF
SENSE RING
FOR8MAs

B. VIAS TO THE
POWER PLANES

Figure 1. Front View of ECLlnPS Evaluation Board

MOTOROLA

1-16

ECLinPS and ECLinPS Lite

DL140-Rev4

Engineering Evaluation Board
Table 2. Pin Cross Reference

Group

Parl(s)

P10

P11

P12

P13

eONF1

E196

VEE

Vee

eONF2

E142

VEE

Vee

eONF3

E337

VEE

eONF4

E2l2

VEE

eONF5

E156

VEE

eONF6

E158

VEE

INB

eONF7

E154

VEE

INB

eONF8

El01

VEE

eONF9

E112

VEE

eONF10

E431

eONFll

P14

Vee

VEE

INB

Vee

Elll

Vee

eONF12

El64

VEE

Vee

eONF13

E45l

VEE

Vee

eONF14
eONF15

E163
EW3

VEE
VEE

I
I

I
Vee

I
0

0
0

Vee
Vee

Table 2. Pin Cross Reference (continued)
#01

Parl(s)
(cont'd)

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

Connectors

E196

Vee

El42

Vee

E337

Vee

E212

Vee

E1S6

Vee

Elsa

Vee

Vce

E154

Vee

Vec

E10l

Vee

E112

Vee

E431

Vee

INB

El11

Vce

Vee

VEE

El64

Vee

E45l

Vee

El63
E193

Ne
0

Vee
Vee

0
0

Vee
0

I
I

42
38

KEY:

Vec

I designates an input
o designates an output
VEE designates the lower voltage rail
Vee designates the upper voltage rail
Ne designates a no connect
VB designates VBB output which should
not be terminated into 50 ohms

ECLinPS and EeLinPS Lite
DL140-Rev4

1-17

MOTOROLA

Engineering Evaluation Board

ASSEMBLING THE ECLinPS EVALUATION BOARD
The evaluation board is designed for characterizing devices in a laboratory environment using high bandwidth sampling
oscilloscopes such as the Hewlett Packard 54120T, the Tektronix 11800 Series, or the Tektronix 7854. The board is designed using
Kelvin contact (fly-by) techniques to present the input signals to the DUT. Each pin on the board has two traces, one force and one
sense. Input pins use one force and one sense line, while outputs need only a sense line. This means that input signals are
terminated through the sense line into the 50 ohm input of a sampling oscilloscope instead of atthe inpulto the DUT. Please refer to
the AC Testing section of the ECLinPS Data Book for further information and a simplified figure of the test setup.
The first step in building a board is determining which inpuVoutpuVpower configuration is necessary forthe device of interest. Table
1 on the first page olthe Applications Information shows all the board configurations. For example, if the devices of interest were the
E104 and the Et51, then CONF2 would be selected. Table 2 is a pin cross reference for each configuration.

I. Installing the SMA Connectors
Table 2 indicates the number of SMA connectors needed to populate an evaluation board for a given configuration. Depending on
the device and the parameters of interest, it may not be necessary to install the full complement of SMA connectors. For example,
some devices have two clock inputs or common clocks and individual clocks. Figure 1 is the frontview of the ECLinPS evaluation
board. Item A pOints to the inner ring which connects to the sense traces of the DUT. The outer ring connects to the force traces. An
input requires one SMA connector for the force and one SMA connector for the sense, while an output only requires a connection to
the sense trace. Insert all the SMA connectors into the board and solder to the board. A simple assembly technique is to place a stiff
piece of cardboard (8" x 7" or larger) on top of all the connectors and hold the board and cardboard together. Invert the board, place
on a level surface, and all the connectors will be seated properly and can be soldered in place.
II. Connecting Power Planes to DUT Socket

There are four voltage planes on the ECLPSBD28. One is dedicated to ground and the other three, B1, B2, B3, are uncommitted.
These planes are accessible through a power connection and sets of four vias that are adjacent to each sense trace. This is
identified as Item B in Figure 1. For standard parts, B1 can be assigned VCC, B2 can be assigned to VEE, and B3 can be assigned to
ground. Table 2 indicates which pins need to be connected to the various supply voltages. On the front side of the board, solder a
jumper wire from the closest VEE or Vee via to the sense trace for each Vce, Veeo, and VEE pin. Near the DUT there are sets of
ground/bias plane vias that accommodate power supply decoupling capacitors. These are identified as Item C. On the front side of
the board install 10 IlF capacitors and on the back side install a 0.01 IlF high frequency capacitor in parallel to decouple the VEE and
Vee planes.
III. Cutting Force Traces for Outputs

Because of the design of the board, all force traces for output pins will appear as transmission line stubs connected to the output
pin. On the back side of the board, cut the force traces associated with the outputs using a razor blade knife. It is important to cut
the trace very close to the DUT area to minimize the stub length. Also cut the force traces that are connected to Vee, Veeo, and
VEE pins.
IV. Installing the Chip Capacitors for the VccNcco Pins
In the kit are 0.011lF chip capacitors for use in decoupling the Vee and Veeo pins to the ground plane. This is critical because the
power pins are not directly connected to the Vec plane as in an actual board layout. On the back side of the board beneath the DUT
socket are pads for each pin which allow connection of chip capacitors to the center island (GND) for each VCC andVcco pin. Stand
the chip capacitors on edge when soldering them in place so that adjacent pins are not shorted together.

MOTOROLA

1-18

ECLinPS and ECLinPS Lite
DL140-Rev4

Engineering Evaluation Board

v. Final Assembly
The board power plane interface is designed to accommodate a 15·pin right angle 0 connector. This can be used directly, or wires
can be inserted into the vias to connect to the power planes that were connected to the OUT in part II. Attach standoffs into the four
0.25 inch holes at the corners of the board. This completes the assembly of the evaluation board and it should be ready to test.

VI. SMA Connector Suppliers
Below are two suppliers who manufacture PC Mount SMA connectors which interface to the evaluation board. Motorola has used
these two connectors before, but there are other vendors who manufacture similar products.

EF Johnson
299 Johnson Ave. P.O. Box 1249
Waseca, Minnesota 56093
(800) 247·8343 or (507) 835·6222

0.200" PC Mount SMA
Jack Receptacle
142·0701·201

MACOM Omni Spectra
140 Fourth Avenue
Waltham, Massachusetts 02254
(617) 890·4750

0.200" PC Mount SMA
Straight Jack
2062·0000·00

ECLinPS and ECLinPS Lite
DL140-Rev4

1-19

MOTOROLA

1-20

ECLinPS and ECLinPS Lite
DLl40-Rev4

High Performance Eel Data
ECLinPS and ECLinPS Lite

This section contains AC & DC specifications
for each 20, 28-lead PLCC and 16-/ead SOIC
ECLinPS device type. Specifications common to
aI/ device types can be found in the first part of
this section. While specifications unique to a
particular device can be found in the individual
data sheets fol/owing the family specifications.

ECLinPS Family Specifications &
Device Data Sheets

Data Sheet Classification

Advance Information - product in the sampling or
pre-production stage at the time of publication.

Product Preview- product in the design stage at
the time of publicatioA.

ECLinPS and ECLinPS Lite
DL140-Rev4

2-1

MOTOROLA

ECLinPS Family Specifications
Absolute Maximum Ratings
Beyond which device life maybe Impaired.1
Characteristic

Symbol

Rating

Unit

VEE

-8toO

Vdc

Oto-6V

Vdc

Output Current - Continuous
-Surge

lout

50
100

Operating Temperature Range
10E Series
100ESeries

=OV)
Input Voltage (VCC =OV)
Power Supply (VCC

°C
o to+ 85
Oto + 85

Operating Range2

-5.7to-4.2

VEE

1. Unless specified otherwise on individual data sheet.
2. Parametric values specified at: 1DOE series: - 4.2V to - 5.46V
10E series: - 4.94V to - 5.46V

10E Series DC Characteristics
VEE

=- 5.2V ± 5%; Vee =Veeo =GN01
O°C

Symbol

Characteristic

25°C

75°C

85°C

Min

Max

Min

Max

Min

Max

Min

Max

Unit

VOH

Output HIGH Voltage

-1020

-840

-980

-810

-920

-735

-910

-720

VOL

Output LOW Voltage

-1950

-1630

-1950

-1630

-1950

-1600

-1950

-1595

VIH

Input HIGH Voltage

-1170

-840

-1130

-810

-1070

-735

-1060

-720

VIL

Input LOW Voltage

-1950

-1480

-1950

-1480

-1950

-1450

-1950

-1445

IlL

Input LOW Current

0.5

0.3

I1A

0.3

1. 10E series circuits are designed to meet Ihe dc speCifications shown in the table, after thermal equilibrium has been established. The circuit is
in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through
a 50Q resistor to -2.0 volts, except bus outputs which, where specified, are terminated into 25Q.

100E Series DC Characteristics
VEE

=- 4.2V to - 5.46V; Vee =Veeo =GNO; TA =ooe to + 85°e

Symbol

Min

Typ

Max

Unit

VOH

Output HIGH Voltage

Characteristic

-1025

-955

-880

Conditions

VOL

Output LOW Voltage

-1810

-1705

-1620

orVIL(min)

Loading with

VOHA

Output HIGH Voltage

-1035

VIN = VIH(min)

50Qto-2.0V

VOLA

Output LOW Voltage

-1610

VIH

Input HIGH Voltage

-1165

-880

VIL

Input LOW Voltage

-1810

-1475

Guaranteed LOW Signal for All Inputs

IlL

Input LOW Current

0.5

I1A

VIN = VIL07

00->07

Eot6
LSB

EOt6

EOt6
MSB

PO-> P7

CLOCKo--4--------------~--------------------~~------------------~

Figure 1. 32·Blt Cascaded E016 Counter

MOTOROLA

2-6

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E016 MC100E016
Applications Information (continued)
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not
the case estimates of these delays need to be added to
the calculations.

where:
PO = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 2 will
result in the waveforms of Figure 3. Note that the TC output is
used as the divide output and the pulse duration is equal to a

Programmable Divider

Table 1_ Preset Values for Various Divide Ratios
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all Is state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 2
below illustrates the input conditions necessary for utilizing the
E016 as a programmable divider set up to divide by 113.
H

CE
H

TClD

Figure 2. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply subtracts
the binary equivalent of the desired divide ratio from the binary
value for 256. As an example for a divide ratio of 113:
Pn's

=256 -113 =8F16 =1000 1111
load

10010000

10010001

2
3
4
5

H
H
H
H

H
H
H

l
H

112
113
114

H
H
H

L
L
L

L
L

H
H

254
255
256

L
L
L

··
··

·· ·· ··
·· ·· ··

L
L

·· ·· ··
·· ·· ··
L
L

L
H

··
··
L

full clock period. For even divide ratios, twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2 to
256 inclusive. If divide ratios of greater than 256 are needed
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.

ClK

Rallo

··
··

Preset Dala Inpuls

Divide

11111100

11111101

11111110

11111111

load

Clock

-----+-./

TC-----f_/

DIVIDE BY 113

Figure 3. Divide by 113 E016 Programmable Divider Waveforms

ECLinPS and ECLinPS Lite

DL140-Rev4

2-7

MOTOROLA

MC10E016 MC100E016
Applications Information (continued)

00->07

E016

E016
MSB

LO
E016
LSB

PO->P7
CLOCK

Figure 4. 32-Bit Cascaded E016 Programmable Divider

Figure 4 on the following page shows a typical block
diagram of a 32·bit divider chain. Once again to maximize the
frequency of operation EL01 OR gates were used. For lower
frequency applications a slower OR gate could replace the
EL01. Note that for a 16-bit divider the OR function feeding the
PE (program enable) input CANNOT be replaced by a wire OR
tie as the TC output of the least significant E016 must also feed
the CE input o!the most significant E016. l!the two TC outputs
were OR tied the cascaded count operation would not operate
properly. Because in the cascaded form the PE feedback is
external and requires external gating, the maximum frequency
of operation will be significantly less than the same operation
in a single device.

MOTOROLA

Maximizing E016 Count Frequency
The E016 device produces 9 fast transitioning single ended
outputs, thus VCC noise can become significant in situations
where all of the outputs switch simultaneously in the same
direction. This VCC noise can negatively impact the maximum
frequency of operation of the device. Since the device does
not need to have the Q outputs terminated to count properly,
it is recommended that if the outputs are not going to be used
in the rest of the system they should be left unterminated. In
addition, if only a subset of the Q outputs are used in the
system only those outputs should be terminated. Not
terminating the unused outputs will not only cut down the VCC
noise generated but will also save in total system power
disSipation. Following these guidelines will allow designers to
either be more aggressive in their deSigns or provide them
with an extra margin to the published data book specifications.

2-8

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad 4-lnput OR/NOR Gate

MC10E1011
MC100E101

The Mel0E/l00El0l is a quad 4-input ORiNOR gate.
o 500ps Max. Propagation Delay
o Extended 100E VEE Range of - 4.2V to - 5.46V

• 75k!:! Input Pulldown Resistors

QUAD 4-INPUT
OR/NOR GATE'

Pinout: 28-Lead PLCC (Top View)

D2d

D2c

D2b

Vee

VEE

FN SUFFIX
PLASTIC PACKAGE
CASE 776-02

Dlb

Dla

Dad

DOc

Dab

DOa

Veeo

• All VCC and VCCO pins are tied together on the die.

LOGIC DIAGRAM

Doa~

Dab

DOc
Dad

PIN NAMES

Function

Pin
DOa- D3d

Data Inputs

00- 03

True Outputs

00- 0 3

Inverting Outputs

12193

2-9

REV 2

MOTOROLA

[2J

MC1 OE1 01 MC1 00E1 01
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =veea = GND)
Q'C

Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

min

typ

25'C
max

min

150

tpLH
tpHL

Propagation Delay to Output
DtoO

tSKEW
tSKEW

Within-Device Skew
Within-Gate Skew

tr
tf

Rise/Fall Time
20- BO%

min

typ

max

Unit

150

IlA

Condition

mA
30
30

36
36

30
30

min

typ

36
36

30
35

25'C
max

36
42

=Veea = GND)

O'C
Characteristic

85'C
max
150

AC CHARACTERISTICS (VEE =VEE(min) to VEE(max); Vee

Symbol

typ

min

typ

85'C
max

min

typ

max

Unit

Condition

ps
200

350

500

200

50
25

350

500

200

50
25

350

500
ps

50
25

1
2

ps
300

3BO

575

300

3BO

575

300

3BO

575

1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Within-gate skew is defined as the variation in propagation delays of a gate when driven from its different inputs.

MOTOROLA

2-10

ECLinPS and ECLinPS Lite
.
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quint 2-lnput AND/NAND Gate

MC10E104
MC100E104

The Mel DEll OOEl 04 is a quint 2-input ANDINAND gate. The function
output F is the OR of all five AND gate outputs, while F is the NOR. The Q
outputs need not be terminated if only the F outputs are to be used.
• 600ps Max. Propagation Delay
• ORINOR Function Outputs

QUINT 2-INPUT
AND/NAND GATE

• Extended lODE VEE Range of - 4.2V to - 5.46V
• 75kn Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)

Vee
FNSUFAX

PLASTIC PACKAGE
CASE 776-02

LOGIC DIAGRAM
Dab

Veea 00

00 01

01 Veea

• All VCC and VCCO pins are tied together on the die.

DOa

Dab

PIN NAMES
Pin
DOa -D4b
00- 0 4
00- 0 4
F

Function
Data Inputs
AND Outputs
NAND Outputs
OR Output
NOR Output

D3a

FUNCTION OUTPUTS
F=

(Doa • Dab) + (Dla· D1b) + (D2a· D2b) +
(D3a • D3b) + (D4a • D4b)

t2l93

2-11

REV2

MOTOROLA

MC10E104 MC100E104
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea =GND)
DOC

Characteristic

Symbol
IIH

Input HIGH Current

lEE

Power Supply Current
10E
lODE

AC CHARACTERISTICS (VEE

min

typ

25°C
max

min

typ

200

max

Unit

200

I1A

Characteristic
Propagation Delay to Output
DtoO
DtoF

tSKEW

Within-Device Skew
DtoO

mA
38
38

46
46

38
38

46
46

38
44

46
53

min

typ

25'C
max

min

typ

85°C
max

min

typ

max

Unit

Condition

ps
225
500

385
725

600
1000

225
500

385
725

600
1000

225
500

385
725

600
1000
ps

Rise/Fall Times
20-80%

Condition

=VEE(min) to VEE(max); Vee =Veea =GND)

tpLH
tpHL

tr
tf

85°C
max

200

D'C
Symbol

typ

ps
275
300

425
475

700
700

275
300

425
475

700
700

275
300

425
475

700
700

1. Within-device skew is defined as identical transitions on similar paths through a device.

MOTOROLA

2-12

ECLinPS and ECLinPS Lite
DL140-Rev4

Ii\IilC"IT(O)!R(O)IL.A
SEMICONDUCTOR TECHNICAL DATA

The MC1 0E/1 00E1 07 is a quint 2-input XORlXNOR gate. The function
output F is the OR of all five XOR outputs, while F is the NOR. The Q
outputs need not be terminated if only the F outputs are to be used.

MC10E107
MCiJOOEi07

• 600ps Max. Propagation Delay
o ORINOR Function Outputs

QUINT 2-INPUT
XORIXNOR GATE

o Extended 1OOE VEE Range of - 4.2V to - 5.46V

o 75kn Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)
D3a

D4b

D4a

Ne Veea

D3b

D2a

D2b

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

VEE

LOGIC DIAGRAM

DOb

Veea 00

Oi' Veea

""-OHHt---- 0 0

• All VCC and VCCO pins are tied 10gether on the die.

---<>-+H+--- 00
"-OIrH---- 0 1

PIN NAMES
Pin

A>--Ht--- Oi'

Function

DOa- D4b

Data Inputs

0 0- 0 4

XOROutputs

""~tH--- 0 2

0 0- 0 4

XNOR Outputs

---<>---+1--- 02

OR Output

NOR Output

'..---d!---- 03

FUNCTION OUTPUTS
F

A>---+--- 03

= (DOa E9 Dab) + (D1 a E9 D1 b) (D2a E9 D2b) +
(D3a E9 D3b) + (D4a E9 D4b)

""--6---

---<>----- 04

12193

2-13

REV2

MOTOROILA

MC10E107 MC100E107
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max);

Vee = Veea = GND)

D'C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current

min

typ

min

42
42

ISKEW

Within-Device Skew
DtoO

tr
tl

typ

max
200

min

typ

42
48

50
50

Condition

!1A

50
58

25'C
max

min

typ

85°C
max

min

typ

max

Unit

Condition

ps
250
500

410
725

600
1000

250
500

410
725

600
100

250
500

410
725

600
1000
ps

Rise/Fall Times
20-80%

Unit

Vee = Veea = GND)

O'C

Propagation Delay to Output
DloO
DloF

min

200

50
50

AC CHARACTERISTICS (VEE =VEE(min) to VEE(max);

tpLH
tpHL

max

mA
42
42

Characteristic

typ

200

10E
100E

Symbol

85'C

25'C
max

ps
275
300

450
475

700
700

275
300

450
475

700
700

275
300

450
475

700
700

1. Within-device skew IS dellned as Idenllcal transitions on similar paths through a device.

MOTOROLA

2-14

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

1:9 Differential Clock Driver

MC10E111
MC100E111

The MC10El100E111 is a low skew 1-10-9 differential driver, designed
with clock distribution in mind. It accepts one signal input, which can be
either differential or else single-ended if the Vee output is used. The
signal is fanned out to 9 identical differential outputs. An enable input is
also provided. A HIGH disables the device by forcing all Q outputs LOW
and all Q outputs HIGH.
• LowSkew
• Guarateed Skew Spec
• Differential Design
•
•
•
•

1:9 DIFFERENTIAL
CLOCK DRIVER

Vee Output
Enable
Extended 100E VEE Range of -4.2 to -5.46V
75/ill Input Pulldown Resistors

The device is specifically designed, modeled and produced with low
skew as the key goa/. Optimal design and layout serve to minimize gate to
gate skew within-device, and empirical modeling is used to determine
process control limits that ensure consistent tpd distributions from lot to
lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into son, even if only
one side is being used. In most applications, all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used, it is necessary to terminate at least the output pairs on the
same package side (Le. sharing the same VCCO) as the pair(s) being
used on that side, in order to maintain minimum skew. Failure to do this
will result in small degradations of propagation delay (on the order of
10-20ps) of the output(s) being used which, while not being catastrophic
to most designs, will mean a loss of skew margin.

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

LOGIC SYMBOL

PIN NAMES
Pin

Function

IN,IN
EN
00, 00-08, 08
VSS

~-"'---

r-t.~-

_-1-"",,_- Q1

Differential Input Pair
Enable
Differential Outputs
VssOutput

_1/"1>---

11>--1-"'--- Q2

_1/"1>---

b--I-r-..-- Q3
00

01 Veeo

VEE

_1/"1>---

Veeo

Vss

Pinout: 28-Lead PLCC
(Top View)

Vee

Veeo Q7

2-15

_-I-r-..-- QS
_1/"1>--- Os
_-I-r-..__ Q6
_1/"1>---

_-I-r-..-- Q7

_1/"IJ--07
'---1-"'--- QS

'""""1.~-0s

5195

IN --f""'..:---....-f-.f'.o.,.--- Q4

REV 3

MOTOROLA

MC10E111 MC100E111

=VEE (min) to VEE (max); Vee =veea =GND)

DC CHARACTERISTICS (VEE

-40'C
Symbol
VBB

Characteristic
Output Reference
Voltage
tOE
100E

IIH

Input HIGH
Current

lEE

Power Supply
Current
10E
100E

Min

Typ

O'C
Max

Min

25'C

Typ

Max

Min

85'C

Typ

Max

Min

Typ

Max

Unit

Cond

V
-1.43
-1.38

-1.30
-1.26

-t.38
-1.38

-1.27
-1.26

ISO

-1.35
-1.38

-1.25
-1.26

150

-1.31
-1.38

-1.19
-1.26
ISO

ISO

)!A
mA

48
48

Vpp(DC)

Input Sensitivity

VCMR

CommomMode
Range

-1.6

60
60

48
48

60
60

48
48

50
-0.4

-1.6

60
69

-1.6

-0.4

48
55

-0.4

-1.6

-0.4

I. Differential Input voltage reqUired to obtain a full ECl sWing on the outputs.
2. VCMR is defined as the range within which the VIH level mayvaJY. with the device still meeting the propagation delay specification. The Vil level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

AC CHARACTERISTICS (VEE

=VEE (min) to VEE (max); Vee =Veca =GND)
-40'C

Symbol

Characteristic

Min

tplH
tpHl

Propagation Delay to
Output
IN (Diff)
IN (SE)
Enable
Disable

380
280
400
400

Typ

O'C
Max

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

Cond

ps
680
780
900
900

460
410
450
450

560
610
850
850

480
430
450
450

580
630
850
850

510
460
450
450

610
660
850
850

I
2
3
3

Setup lime

EN to IN

250

200

Hold lime

INtoEN

-200

Release lime ENtolN

350

100

300

100

300

100

300

100

tskew

Within-Device Skew

Vpp(AC)

Minimum Input Swing

250

tr.tf

Rise/Fall lime

250

450

650

375

600

250
275

375

600

375

600

250

250
275

275

I. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter I (page 1-12).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter I (page 1-12).
3. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition on Q
(or a negative transition on 0). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the 50% point
of a negative transition on Q (or a positive transition on 0).
4. The within-device skew is defined as the worst case difference between any two similar delay ~ths within a single device.
5. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/iN transition (see Figure I).
6. The hold time is the minimum time that EN must remain asserted aiter a negative going IN or a positive going iN to prevent an output response
greater than ±75 mV to that IN/iN transition (see Figure 2).
7. The release time is the minimum time that EN must be deasserted prior to the next IN/iN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times (see Figure 3).
8. Vpp(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The Vpp(min) is AC limited
for the EIII as a differential input as low as 50 mV will still produce full ECl levels at the output.

MOTOROLA

2-16

ECLinPS and ECLinPS Lite
Dl140-Rev4

MC10E111 MC100E111

~j_t.~,__
EN

,;75mV

TT
,;?5mV

Figure 1. Setup Time

IN~

50%

,;?5mV

Figure 2. Hold Time

Q ____
Q

Figure 3. Release Time

ECLinPS and ECLinPS Lite
DL140-Rev4

2-17

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad Driver

MC10E112
MC100E112

The MC10El100E112 is a quad driver with two pairs of ORINOR
outputs from each gate, and a common, buffered enable input. Using the
data inputs the device can serve as an ECl memory address fan-out
driver. Using just the enable input, the device serves as a clock driver,
although the MC1 OEl1 00E111 is designed specifically for this purpose,
and offers lower skew than the E112. For memory address driver
applications where scan capabilities are required, please refer to the
E212 device.
•
•
•
•

QUAD DRIVER

600ps Max. Propagation Delay
Common Enable Input
Extended 100E VEE Range of - 4.2V to - 5.46V
75kQ Input Pulldown Resistors

[2J

Pinout: 28-Lead PLCC (Top View)
FN SUFFIX

Q3b

Q3a

Q3b

Q3a

Veea

Q2b

PLASTIC PACKAGE
CASE 776·02

Q2a

Veea

Q2b

Q2a

Vce

VEE

Qlb

Qla

LOGIC DIAGRAM
QOa
00

QOb
QOa
QOb

Qlb

Qla

Qla
01

Qlb
Qla

Veco

QOa

QOb

QOa QOb

Qlb

Veea

• All VCC and VCCO pins are tied together on the die.

Q2a
02

Q2b
Q2a

PIN NAMES
Pin

Q2b

Function

Do-D3
EN

Data Inputs

Qna,Qnb

True Outputs

Q3a

Qna. Qnb

Inverting Outputs

Q3b

Q3a
03

Enable Input

Q3b

12/93

2-18

REV2

MOTOROLA

MC10E112 MC100E112
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
D'C
Symbol
IIH

lEE

Characteristic

min

typ

25'C
max

min

200
200

Propagation Delay to Output
D
EN

tSKEW

Within-Device Skew
Dnto an, an
anatoanb

47
47

56
56

47
47

max

Unit

Condition

200
200

min

typ

56
56

47
54

25'C
max

min

56
65

=GND)
typ

85'C
max

min

typ

max

Unit

Condition

ps
200
275

400
450

600
675

200
275

400
450

600
675

200
275

400
450

600
675
ps

80
40

Rise/Fall Times
tr
20-80%
275
425
700
275
425
700
tl
..
1. Within-deVice skew IS dell ned as Identical transitions on similar paths through a device.
2. Skew delined between common OR or common NOR outputs 01 a single gate.

ECUnPS and ECUnPS Lite
DL140-Rev4

typ

200
200

D'C

tpLH
tpHL

min

rnA

Power Supply Current
10E
100E

Characteristic

85'C
max

Input HIGH Current
D
EN

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea

Symbol

typ

2-19

80
40

I
2
ps

275

425

700

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quint Differential Line
Receiver

MC10E116
MC100E116

The MC10E/100E116 is a quint differential line receiver with
emitter-follower outputs. An internally generated reference supply (VSS)
is available for single-ended reception.
• 500ps Max. Propagation Delay

QUINT DIFFERENTIAL
LINE RECEIVER

• VSS Supply Output
• Dedicated VCCO Pin for Each Receiver
• Extended 100E VEE Range of - 4.2V to - 5.46V
• 751<0 Input Pulldown Resistors
Active current sources plus a deep collector feature of the MOSAIC III
process provide the receivers with excellent common-mode noise
rejection. Each receiver has a dedicated VCCO supply lead, providing
optimum symmetry and stability.
The receiver design features clamp circuitry to cause a defined state if
both the inverting and non-inverting inputs are left open; in this case the Q
output goes lOW, while the Q output goes HIGH. This feature makes the
device ideal for twisted pair applications.

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

If both inverting and non-inverting inputs are at an equal potential of
> -2.5V, the receiver does not go to a defined state, but rather
current-shares in normal differential amplifier fashion, producing output
voltage levels midway between HIGH and lOW, or the device may even
oscillate.

The device VSS output is intended for use as a reference voltage for single-ended reception of ECl signals to that device only.
When using for this purpose, it is recommended that VSS is decoupled to VCC via a O.o1ILF capacitor. Please refer to the interface
section of the design guide for information on using the E116 in specialized applications.
The E116 features input pull-down resistors, as does the rest of the ECLinPS family. For applications which require
bandwidths greater than that of the E116, the E416 device may be of interest.

Pinout: 28-lead PLCC (Top View)
03

Veea

04 04

Veea

PIN NAMES
Pin
DO, DO - D4, D4
00, 00 - 04, 04
VBB

Function
Differential Input Pairs
Differential Output Pairs
Reference Voltage Output.

Veea

• All VCC and VCCO pins are tied together on the die.

5/95

2-20

REV 3

MOTOROLA

MC10E116 MC100E116
LOGIC DIAGRAM

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
-40°C
Symbol
VBB

Characteristic
Output Reference
Voltage
10E
100E

'IH

Input HIGH
Current

lEE

Power Supply
Current
10E
100E

Min

Typ

O°C
Max

Min

Typ

25°C
Max

Min

Typ

05°C
Max

Min

Typ

Max

Unit

Cond

V
-1.43
-1.38

-1.30
-1.26

-1.38
-1.38

-1.27
-1.26

-1.35
-1.38

-1.25
-1.26

200

-1.31
-1.38

-1.19
-1.26
200

200

rnA
29
29

Vpp(DC)

Input Sensitivity

150

VCMR

CommomMode
Range

-2.0

35
35

29
29

35
35

150
-{J.6

-2.0

29
29

35
35

29
29

150
-{J.6

35
40

150
-{J.6

-2.0

-0.6

1. Dlfferenliallnput voltage reqUired to obtain a full ECl sWing on the outputs.
2. VCMR is defined as the range within which the V,H level may vary, with the device still meeting the propagation delay specification. The V,l level
must be such that the peak to peak voltage Is less than 1.0 V and greater than or equal to Vpp(min).

AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); Vee = Veea = GND)
-40°C
Symbol

Characteristic

Min

tPlH
tpHl

Propagation Delay to Output
o (Differential)
o (Single-Ended)

tskew

Within-Device Skew

tskew

Duty Cycle Skew

Typ

O°Cto 05°C
Max

Min

Typ

Max

Unit

Condition

ps
150
150

tPlH-tPHl

Vpp(AC)

Minimum Input Swing

150

trltf

Rise/Fall Time

250

300
300

500
550

200
150

300
300

450
500

±10

150
375

625

275

375

575

2o-BO%

1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
3. Minimum input swing for which AC parameters are guaranteed.

ECLinPS and ECLinPS Lite
Dl140-Rev4

2-21

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

9·Bit Buffer
The MC10E/100E122 is a 9-bit buffer. The device contains nine
non-inverting buffer gates.

MC10E122
MC100E122'

• SOOps Max. Propagation Delay
• Extended 100E VEE Range of - 4.2V to - 5.46 V
• 7Skn Input Pulldown Resistors

9·BIT BUFFER

Pinout: 28-Lead PLCC (Top View)
08

Vcca

[2J

Vce

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

VEE

LOGIC DIAGRAM

• All VCC and VCCO pins are tied together on the die.

PIN NAMES
Pin

Function

Do-Da

Data Inputs

Oo-Oa

Data Outputs

12/93

2-22

REV 2

MOTOROL.A

MC10E122 MC100E122
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea =GND)
D'C

Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

AC CHARACTERISTICS (VEE

min

typ

25'C
max

min

typ

200

max

Unit

200

/1A

Condition

49
49

4t
41

49
49

41
47

49
57

=VEE(min) to VEE(max); Vee =Veea =GND)

Characteristic
Propagation Delay to Output
DtoO

tSKEW

Within-Device Skew
DtoO
Rise/Fall Times
20-80%

min

rnA
41
41

tpLH
tpHL

tr
tf

max

200

D'C
Symbol

85'C

typ

min

typ

25'C
max

min

typ

85'C
max

min

typ

max

Unit

Condition

ps
t50

350

500

150

350

500

150

350

500
ps

1
ps

300

425

800

300

425

800

300

425

800

1. Within-device skew IS defined as Identical tranSItions on similar paths through a device .

ECLinPS and ECLinPS Lite
DL140- Rev 4

2-23

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

4-Bit D Flip-Flop

MC10E131
MC100E131

The MC10El100E131 is a quad master-slave D-type flip-flop with
differential outputs. Each flip-flop may be clocked separately by holding
Common Clock (CC) LOW and using the Clock Enable (CE) inputs for
clocking. Common clocking is achieved by holding the CE inputs LOW
and using Cc to clock all four flip-flops. In this case, the CE inputs perform
the function of controlling the common clock, to each flip-flop.

4·BIT
D FLlp·FLOP

Individual asynchronous resets are provided (R). Asynchronous set
controls (S) are ganged together in pairs, with the pairing chosen to
reflect physical chip symmetry.
Data enters the master when both Cc and CE are LOW, and transfers
to the slave when either Cc or CE (or both) go HIGH.
• 1100MHz Min. Toggle Frequency
• Differential Outputs
• Individual and Common Clocks
• Individual Resets (asynchronous)
• Paired Sets (asynchronous)

FNSUFFIX
PLASTIC PACKAGE
CA8E776-02

• Extended 100E VEE Range of - 4.2V to - 5.46V
• 751<0 Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)

R2
22

Veeo OJ
21

LOGIC DIAGRAM

8
D

GEs

Vee

GE2

80S

R2
00

80a
812

Rl
• All VCC and VCCO pins are tied together on the die.

PIN NAMES
Pin
DO-D3
CEO-CE3
RO-R3
Cc
803,812
00- 0 3
00- 0 3

Function
Data Inputs
Clock Enables (Individual)
Resets
Common Clock
8ets (paired)
True Outputs
Inverting Outputs

2-24

GEo
D

7196

GEl

REV 3

MOTOROLA

MC10E131 MC100E131
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
-40'C
Symbol
IIH

IIEE

Characteristic
Input HIGH
Current

Min

Typ

O'C
Max

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

Cond

IJA
350
450
300
150

Cc
S
R,CE
D

Power Supply
Current
10E
100E

350
450
300
150

350
450
300
150
mA

58
58

70
70

58
58

70
70

58
58

70
70

58
67

70
81

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
O'Cto85'C

-40'C
Symbol

Characteristic

Min

Typ

IMAX

Maximum Toggle Frequency

1000

1400

IplH
IpHl

Propagation Delay to Output

CE
Cc
R
S

310
275
300
300

600
600
625
550

Max

750
725
775
775

Min

Typ

1100

1400

360
325
350
350

500
500
550
550

Max

Unit

Condition

MHz

700
675
725
725

Setup TIme

200

150

Hold TIme

225

-20

175

-20

1RR

Reset Recovery TIme

450

150

400

150

tpw

Minimum Pulse Width

tSKEW

Within-Device Skew

trltl

Rise/Fall TIme

ClK
R,S

400
400

400
400
60

60
275

460

725

300

480

675

2CHlO%

1. Setup/hold times guaranteed lor both Cc and CEo
2. Within-device skew is delined as identical transitions on similar paths through a device.

ECLinPS and ECLinPS Lite
Dl140-Rev4

2-25

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

6·Bit Universal Up/Down Counter

MC10E136
MC100E136

The MC1 OEl1 00E136 is a 6-bit synchronous, presettable, cascadable
universal counter. The device generates a look-ahead-carry output and
accepts a look-ahead-carry input. These two features allow for the
cacading of multiple E136's for wider bit width counters that operate at
very nearly the same frequency as the stand alone counter.
• 550 MHz Count Frequency

6-81T UNIVERSAL
UP/DOWN COUNTER

• Fully Synchronous Up and Down Counting
• Internal 75 fill Input Pulldown Resistors
• Look-Ahead-Carry Input and Output
• Asynchronous Master Reset
• Extended 100E VEE Range of -4.2 V to -5.46 V
The CLOUT output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT output will pulse
LOW for one clock cycle when the counter reaches terminal count. For
more information on utilizing the look-ahead-carry features of the device
please refer to the applications section of this data sheet. The differential
COUT output facilitates the E136's use in programmable divider and
self-stopping counter applications.

FN5UFFIX
PLA5TIC PACKAGE
CA5E776-02

Unlike the H136 and other similar universal counter designs the E136
carry out and look-ahead-carry out signals are registered on chip. This
design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet carefully. Note specifically (see logiC diagram) the operation of the carry out
outputs and the look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input pulldown resistor. The master reset is an asynchronous
signal which when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136to function properly, in fact if these outputs will not be used in a system itis
recommended to save power and minimize noise that they be left' open. This practice will minimize switching noise which can
reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system.
03

PIN NAMES
Pin

Function

Do-Os
00- 0 5
51,52
MR
CLK
COUT, COUT
CLOUT
CIN
CLiN

Preset Data Inputs
Data Inputs
Mode Control Pins
Master Reset
Clock Input
Carry-Out Output (Active LOW)
Look-Ahead-Carry Out (Active LOW)
Carry-In Input (Active LOW)
Look-Ahead-Carry In Input (Active LOW)

FUNCTION TABLE (Expanded truth table on page 2-29)
51

CIN

eLK

Function

L
L
L
H
H
H

L
H
H
L
L
H

L
L
L
L
L
L
H

Z
Z
Z
Z
Z
Z
X

Preset Parallel Data
Increment (Count Up)
Hold Count
Decrement (Count Down)
Hold Count
Hold Count
Reset (an = LOW)

L
H
L
H
X
X

2-26

Veea

81
VEE

Vee

Pinout: 28-lead PLCC
(Top View)

Veea

elK

eaUT

elN

eaUT

eLiN

CLOUT

MR 01
00 Veea 00
01 Veea
• All VCC and VCCO pins are tied together on the die.

5195

Veea

REV 2

MOTOROLA

!:p
~ 5·

,CJl
;JJ0l

CD ::l

5CJl

Sl
S2

Co>

c:
::::I
~.

CIN1~

I'll II~Ds~~ ~~~~

!!!.

l!.

CLiN

~
n
0

, ,

::::I

, ,

"'----f).j D Qf--- CLOUT

f\
"

ir0

;:;.

MR
CLK

iii

OODI

D2-D4

02-04 D5

Nole Ihallhis diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions
are achieved intemally without incurring a full gate delay.

s::
o
-'-

-'-

s::
o-'-

;;::

o
o
m
......
w

;JJ

MC10E136 MC100E136
DC CHARACTERISTICS

(VEE

=VEE(min) to VEE(max); VCC =VCCO =GND)
25'C

D'C
Characteristic

85'C

Symbol

Min

Typ

Max

Min

Typ

Max

Typ

Max

Unit

Input HIGH Current

IIH

150

ItA

Power Supply Current
10E
100E

lEE

125
125

150
150

125
125

150
150

125
140

150
170

AC CHARACTERISTICS

(VEE

25'C

Min

Typ

Max

Min

Typ

Maximum Count Frequency

fCOUNT

550

650

550

650

Propagation Delay to Output
CLKtoO
MRtoO
CLKtoCOUT
CLKtoCLOUT

tpLH
tpHL

850
850
800
825

1150
1150
1150
1150

1450
1450
1300
1400

850
850
800
825

1150
1150
1150
1150

1000
800
150
800

650
400
0
400

1000
800
150
800

650
400
0
400

150
150
300
150

-200
-250
0
-250

150
150
300
150

-200
-250
0
-250

1000

700

1000

700

400

700

400

275
300

600
700

275
300

Hold lime
Sl,S2
D
CLiN
CIN

Reset Recovery TIme

tRR

Minimum Pulse Width
CLK,MR

tpw

Rise/FaliTImes
COUT
Other

MOTOROLA

tr
tf

85'C

Symbol

Setup lime
Sl,S2
D
CLiN
CIN

Condition

=VEE(min) to VEE(max); VCC =VCCO =GND)
D'C

Characteristic

Min

Max

Min

Typ

Max

Unit

550

650

MHz

850
850
800
825

1150
1150
1150
1150

1450
1450
1300
1400

1000
800
150
800

650
400
0
400

150
150
300
150

-200
-250
0
-250

1000

700

400

275
300

600
700

Condition

2-28

1450
1450
1300
1400

600
700

ps
ps
ps
20%-80%

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E136 MC100E136
EXPANDED TRUTH TABLE
Function

CIN

CLIN

CLK

COUT

Preset

Down

H
H
H
H

L
L
L
L

Z
Z
Z
Z

X
X
X
X

X
X

X
X
X
X

X
X

X
X
X
X

L
L
L
H

H
L
L
H

L
H
L
H

H
H
L
H

H
L
H
H

Preset

L
L
L
L
L
L

H
H
H
H
H
H

L
L
L
L
L
L

Z
Z
Z
Z
Z
Z

X
X
X
X
X
X

X
X
X
X

X
X
X
X
X
X

X
X

H
H
H
L
L
L

L
H
H
L
L
H

H
L
H
L
H
L

H
H
L
H
H
H

H
L
H
H
H
H

Hold

H
H

L
L

X
X

Z
Z

X
X

L
L

H
H

L
L

H
H

Oown
Hold
Down
Hold

H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L

L
H
L
H
H
H
L
L

L
L
L
L
L
H
H
L

Z
Z
Z
Z
Z
Z
Z
Z

X
X
X
X
X
X
X
X

L
L
L
L
L
L
L
L

H
H
L
L
L
L
L
L

H
H
L
H
H
H
L
L

L
H
H
H
H
H
H
H

H
L
L
L
L
L
L
L
L

H
L
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L
L

L
L
H
L
H
H
L

L
L
L
L
L
H
L

Z
Z
Z
Z
Z
Z
Z
Z
Z

X
X
X
X
X
X
X

X
X
X
X

X
X
X
X
X
X
X

L
H
H
H
H
H
H
H
H

L
L
L
H
H
H
H
H
H

L
L
H
L
L
H
H
H
H

L
H
H
H
H
L
H
H
L

H
H
H
L
H
H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

Z
Z
Z
Z

X
X
X
X

X
X
X

X
X
X
X

X
X
X

X
X
X
X

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

Hold
Hold
Preset
Up
Hold
Up
Hold
Hold
Up

Reset

X
X

CLOUT

Z = Low to High Transition

ECLinPS and ECLinPS Lite
DL140-Rev4

2-29

MOTOROLA

MC1 OE136 MC100E136
APPLICATIONS INFORMATION
Overview
The MCI OEll 00E136 is a 6-bit synchronous, presettable,
cascadable universal counter. Using the 81 and 82 control
pins the user can select between preset, count up, count
down and hold count. The master reset pin will reset the
internal counter, and set the COUT, CLOUT, and CUN
flip-flops. Unlike previous 136 type counters the carry out
outputs will go to a high state during the preset operation. In
addition since the carry out outputs are registered they will
not go low if terminal count is loaded into the register. The
look-ahead-carry out output functions similarly.

result of the terminal count signal of the lower order counters
having to ripple through the entire counter chain. As a result
past counters of this type were not widely used in large bit
counter applications.
An alternative counter architecture similar to the E016
binary counter was implemented to alleviate the need to
ripple propagate the terminal count signal. Unfortunately
these types of counters require external gating for cascading
deSigns of more than two devices. In addition to requiring
additional components, these external gates limit the
cascaded count frequency to a value less than the free
running count frequency of a single counter. Although there is
a performance impact with this type of architecture it is minor
compared to the impact of the ripple propagate designs. As a
result the E016 type counters have been used extensively in
applications requiring very high speed, wide bit width
synchronous counters.

Note from the schematic the use of the master information
from the least significant bits for control of the two carry out
functions. This architecture not only reduces the carry out
delay, but is essential to incorporate the registered carry out
functions. In addition to being faster, because these functions
are registered the resulting carry out signals are stable and
glitch free.

Motorola has incorporated several improvements to past
universal counter designs in the E136 universal counter.
These enhancements make the E136 the unparalleled leader
in its class. With the addition of look-ahead-carry features on
the terminal count Signal, very large counter chains can be
designed which function at very nearly the same clock
frequency as a single free running device. More importantly
these counter chains require no external gating. Figure 1
below illustrates the interconnect scheme for using the
look-ahead-carry features of the E136 counter.

Cascading Multiple E136 Devices
Many applications require counters significantly larger
than the 6 bits available with the E136. For these applications
several E136 devices can be cascaded to increase the bit
width of the counter to meet the needs of the application.
In the past cascading several 136 type universal counters
necessarily impacted the maximum count frequency of the
resulting counter chain. This performance impact was the

00-> 05

CLOCK

00->05

ClK

00->05

ClK

00->05

ClK

lSB

MSB

'lO"

CIN

COUT

'LD"

CUN

CLOUT

"lO'

CIN
CUN

00->05

111101

CUN

00->05

111110

COUT 1----1 CIN

COUT I----ICIN
CLOUT

CLOUT

00-> 05

111111

000000

CUN

00->05

000001

ClK

CLDUT------------~,,~____~~

COUT------------------------~,,~______~~

Figure 1. 24-bit Cascaded E136 Counter

MOTOROLA

2-30

ECLinPS and ECLinPS Lite
DL140-Rev4

MC1 OE136 MC100E136

CIN---------------4

ACTIVE
lOW

ClK

Figure 2. Look-Ahead-Carry Input Structure
Note from the waveforms that the look-ahead-carry output
(CLOUT) pulses low one clock pulse before the counter
reaches terminal count. Also note that both CLOUT and the
carry out pin (COUT) of the device pulse low for only one
clock period. The input structure for look-ahead-carry in
(CUN) and carry in (CIN) is pictured in Figure 2.
The CUN input is registered and then ORed with the CIN
input. From the truth table one can see that both the CIN and
the CUN inputs must be in a LOW state for the E136 to be
enabled to count (either count up or count down). The CUN
inputs are driven by the CLOUT output of the lowest order
E136 and therefore are only asserted for a single clock
period. Since the CUN input is registered it must be asserted
one clock period prior to the CIN input.
If the counter previous to a given counter is at terminal
count its COUT output and thus the CIN input of the given
counter will be in the "LOW" state. This Signals the given
counter that it will need to count one upon the next terminal
count of the least significant counter (LSC). The CLOUT
output of the LSC will pulse low one clock period before it
reaches terminal count. This CLOUT signal will be clocked
into the CUN input of the higher order counters on the
following positive clock transition. Since both CIN and CUN
are in the LOW state the next clock pulse will cause the least
significant counter to roll over and all higher order counters if
signaled by their CIN inputs, to count by one.
'
00->

During the clock pulse in which the higher order counter is
counting by one the CUN is clocking in the high signal
presented by the CLOUT of the LSC. The CIN's in the higher
order counter will ripple propagate through the chain to
update the count status for the next occurrence of terminal
count on the LSC. This ripple propagation will not affect the
count frequency as it has 2 6-1 or 63 clock pulses to ripple
through without affecting the count operation of the chain.
The only limiting factor which could reduce the count
frequency of the chain as compared to a free running single
device will be the setup time of the CUN input. This limit will
consist of the CLK to CLOUT delay of the E136 plus the CUN
setup time plus any path length differences between the
CLOUT output and the clock.
Programmable Divider
Using external feedback of the COUT pin, the E136 can be
configured as a programmable divider. Figure 3 illustrates the
configuration for a 6-bit count down programmable divider. If
for some reason a count up divider is preferred the COUT
signal is simply fed back to S2 rather than SI. Examination of
the truth table for the E136 shows that when both SI and S2
are LOW the counter will parallel load on the next positive
transition of the clock. If the S2 input is low and the SI input is
high the counter will be in the count down mode and will
count towards an all zero state upon successive clock
pulses. Knowing this and the operation of the COUT output it
becomes a trivial matter to build programmable dividers.
For a programmable divider one wants to load a
predesignated number into the counter and count to terminal
count. Upon terminal count the counter should automatically
reload the divide number. With the architecture shown in
Figure 3 when the counter reaches terminal count the COUT
output and thus the SI input will go LOW, this combined with
the Iowan S2 will cause the counter to load the inputs
present on 00-05. Upon loading the divide value into the
counter COUT will go HIGH as the counter is no longer at
terminal count thereby placing the counter back into the
count mode.

as
Table 1. Preset Inputs Versus Divide Ratio
SO

ClK

"La'

Divide

'2
3

L
L
L
L

L
L
L
l

L
L
L
H

l
H
H
l

H
L
H
L

36
37
38

H
H
H

L
L
L

L
H
H

H
L
L

H
L
H

62
63
64

H
H
H

L
H
H

H
L
H

··

DO-> DS

Figure 3. 6-bit Programmable Divider

OL140-Rev4

··

COUT

ECLinPS and ECLinPS Lite

4
5

COUT

2-31

Preset Data Inputs

Ratio

·· ·· ··
·· ·· ··

MOTOROLA

MC10E136 MC100E136
lOAD
100100

100011

100010

000011

000010

000001

000000

lOAO

CLOCK

81------------~J

COUT------------~

0lVIOEBY37

Figure 4. Programmable Divider Waveforms

The exercise of building a programmable divider then
becomes simply determining what value to load into the
counter to accomplish the desired division. Since the load
operation requires a clock pulse, to divide by N, N-l must be
loaded into the counter. A single E136 device is capable of
divide ratios of 2 to 64 inclusive, Table 1 outlines the load
values for the various divide ratios. Figure 4 presents the
waveforms resulting from a divide by 37 operation. Note that
the availability of the COUT complimentary output COUT
allows the user to choose the polarity of the divide by output.
For single device programmable counters the E016
counter is probably a better choice than the E136. The E016
has an internal feedback to control the reloading of the
counter, this not only simplifies board design but also will
result in a faster maximum count frequency.
For programmable dividers of larger than a bits the

CLOCK 0 - -

superiority of the E016 diminishes, and in fact for very wide
dividers the El36 will provide the capability of a faster count
frequency. This potential is a result of the cascading features
mentioned previously in this document. Figure 5 shows the
architecture of a 24-bit programmable divider implemented
using E136 counters. Note the need for one external gate to
control the loading of the entire counter chain. An ideal
device for the external gating of this architecture would be the
4-input OR function in the a-lead SOIC ECLinPS Lite™ family.
However the final decision as to what device to use for the
external gating requires a balancing of performance needs,
cost and available board space. Note that because of the
need for external gating the maximum count frequency of a
given sized programmable divider will be less than that of a
single cascaded counter.

00->Q5

00->05

111111

I II II I

111111

I II II I

ClK

'----

ClK

!> ClK

ClK

l8B

M8B

lO"- CIN

COUT

LO"- CUN

CLOUT

"lO"- CIN

COUT

CUN

CLOUT

CIN

COUT

CUN

CLOUT

CIN

COUT

r - - CUN

CLOUT

111111

II I I II

111111

00->05

~
Figure 5. 24-bit Programmable Divider Architecture

MOTOROLA

2-32

ECLinPS and ECLinPS Lite
Dl140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

a-Bit Ripple Counter

MC10E137
MC100E137

The MC1 OEl1 00E137 is a very high speed binary ripple counter. The
two least significant bits were designed with very fast edge rates while the
more significant bits maintain standard ECLinPSTM output edge rates.
This allows the counter to operate at very high frequencies while
maintaining a moderate power dissipation level.
• 1.8GHz Minimum Count Frequency

8-BIT RIPPLE
COUNTER

• Differential Clock Input and Data Output Pins
• VBB Output for Single-Ended Use
• Internal 75kn Input Pull down Resistors
• Synchronous and Asynchronous Enable Pins
• Asynchronous Master Reset
o Extended 100E VEE Range of -4.2V to -5.46V

The device is ideally suited for multiple frequency clock generation as
well as a counter in a high performance ATE time measurement board.
Both asynchronous and synchronous enables are available to
maximize the device's flexibility for various applications. The
asynchronous enable input, A_Start, when asserted enables the counter
while overriding any synchronous enable signals. The E137 features
XORed enable inputs, EN1 and EN2, which are synchronous to the ClK
input. When only one synchronous enable is asserted the counter
becomes disabled on the next ClK transition; all outputs remain in the
previous state pOised for the other synchronous enable or A_Start to be
asserted to re-enable the counter. Asserting both synchronous enables
causes the counter to become enabled on the next transition of the ClK.
If EN1 (or EN2) and ClK edges are coincident, sufficient delay has been
inserted in the ClK path (to compensate for the XOR gate delay and the
internal D-flip flop setup time) to insure that the synchronous enable
signal is clocked correctly, hence, the counter is disabled.
The E137 can also be driven single-endedly utilizing the VBB output
supply as the voltage reference for the ClK input signal. If a single-ended
signal is to be used the VBB pin should be connected to the ClK input and
bypassed to ground via a 0.01 flF capacitor. VBB can only source/sink
0.5mA, therefore it should be used as a switching reference for the E137
only.

FN SUFFIX
PLASTIC PACKAGE
CASE 776-02

PIN NAMES
PIN

FUNCTION

ClK,ClK
00-07, 00-07
A_Start
EN1, EN2
MR

Differential Clock Inputs
Differential Outputs
Asynchronous Enable Input
Synchronous Enable Inputs
Asynchronous Master Reset
Switching Refernce Output

VBB

All input pins left open will be pulled lOW via an input pulldown resistor. Therefore, do not leave the differential ClK inputs
open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias
regulators and jeopardizing the stability of the device.
The asynchronous Master Reset resets the counter to an all zero state upon assertion.

LOGIC DIAGRAM
00

B
B>A
A=B

Function
A Data Inputs
B Data Inputs
A Greater than B Output
B Greater than A Output
A Equal to B Output
(active-LOW)

7/96

A=B
B>A

Bo-Ba

PIN NAMES

A>B

2-62

REV3

MOTOROI.A

MC10E166 MC100E166
DC CHARACTERISTICS (VEE = VEE (min) to VEE(max); Vee = Veea = GND)
D'C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

min

typ

25'C
max

min

typ

150

85'C
max

min

typ

150

max

Unit

150

I'A

Condition

mA
113
113

156
156

113
113

156
156

113
130

156
156

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
25'C

D'C
Symbol

Characteristic

min

typ

max

min

typ

85'C
max

min

typ

max

tpLH
tpHL

Propagation Delay to Output
DtoA=B
DtoAB

500
500

750
850

1100
1400

500
500

750
850

1100
1400

500
500

750
850

1100
1400

tr
tf

Rise/Fall TIme
20-80%

300

450

800

300

450

800

300

450

800

ECLinPS and ECLinPS Lite
DL140-Rev4

Unit

Condition

2-63

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

6-Bit 2: 1 Mux-Register

MC10E167
MC100E167

The MC10E/100E167 contains six 2:1 multiplexers followed by D
flip-flops with single-ended outputs. Input data are selected by the Select
control, SEL. The selected data are transferred to the flip-flop outputs by
a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset
(MR) pin asynchronously forces all Q outputs LOW.

6-BIT 2:1
MUX-REGISTER

• 1000MHz Min. Operating Frequency
• 800ps Max. Clock to Output
• Single-Ended Outputs
• Asynchronous Master Resets
• Dual Clocks
• Extended 100E VEE Range of - 4.2V to - 5.46V
• 75k.Q Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
Dsa

D4b

D4a

D3b

D3a

NC Vcco
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

LOGIC DIAGRAM
00

Dab

Dla

Dtb

D2a

D2b Vcca

• All VCC and VCCO pins are tied together on the die.

PIN NAMES
Pin

Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs

DOa- DSa
DOb-DSb
SEL
CLK1,CLK2
MR

00- 0 5

FUNCTIONS

SEL

Data

SEl

ClKl
CLK2
MR

12/93

2-64

REV2

MOTOROLA

MC10E167 MC100E167
DC CHARACTERISTICS (VEE

=VEE (min) to VEE(max); Vee =Veea =GND)
25'C

G'C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

AC CHARACTERISTICS (VEE

min

typ

max

min

typ

113
113

94
94

typ

'MAX

Max. Toggle Frequency

1000

1400

1000

1400

tpLH
tpHL

Propagation Delay to Output
Clk
MR

450
450

650
650

450
450

650
650

Setup Time
D
SEL

100
275

-50
125

100
275

Hold Time
D
SEL

300
75

50
-125

tRR
tpw

Reset Recovery Time

750

550

Minimum Pulse Width
Clk, MR

400

Within-Device Skew
Rise/Fall Times
20- 80%

113
113

94
108

25'C
min

tSKEW

typ

max

Unit

150

J1A

Condition

113
130

=VEE(min) to VEE(max); Vee =Veea =GND)

Characteristic

tr
t,

min

mA
94
94

min

85'C
max
150

150

G'C
Symbol

typ

max

85'C
max

min

typ

1000

1400

450
450

650
650

-50
125

100
275

-50
125

300
75

50
-125

300
75

50
-125

750

550

750

550

max

Unit

Condition

MHz
ps

800
850

800
850
ps

ps
ps

400

400
75

300

450

. .

800

300

450

800

300

450

800

1. Within-device skew IS de'lned as Identical transitions on similar paths through a deVice .

ECLinPS and ECLinPS Lite
DL140-Rev4

2-65

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

3·Bit 4: 1 Multiplexer

MC10E171
MC100E171

The MC10E/100E171 contains three 4:1 multiplexers with differential
outputs. Separate Select controls are provided for the leading 2: 1 mux
pairs (see logic symbol). The three Select inputs control which one of the
four data inputs in each case is propagated to the corresponding output.

3-BIT 4:1
MULTIPLEXER

• 725ps Max. D to Output
• Split Select
• Differential Outputs
• Extended 100E VEE Range of - 4.2V to - 5.46V
• 75kn Input Pulldown Resistors

Pinout: 28-Lead PlCC (Top View)
Dlb

Dla

D2d

D2c

D2b

D2a

Vcca
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02

SELlA
SEL1B

Vcc

SEL2

LOGIC DIAGRAM
DOa

2:1

MUX
NC

DOb

Vcco

SEL

DOC

DOd
Dl a

• All VCC and VCCO pins are tied together on the die.

PIN NAMES
Pin

Function
Data Inputs
First-stage Select Inputs
Second-stage Select Input
True Output
Inverted Output

Dox-D2X
SEL1A, SEL1B
SEL2
00- 0 2

00- 0 2
FUNCTION TABLE
Pin
SEL2
SEL1A
SEL1B

State

H
H
H

Dlb

Dl c

Old
D2a
D2b

D2c

Operation
Output c/d data
Inputd data
Input bdata

D2d
SELlA
SEL1B
SEL2

12193

2-66

REV 2

MOTOROI.A

MC10E171 MC100E171
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee

=Veea =GND)
25'C

O'C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

min

typ

max

min

typ

150

85'C
max

min

typ

150

max

Unit

150

iJ.A

Condition

rnA
56
56

67
67

56
56

67
67

56
65

67
77

AC CHARACTERISTICS (VEE = VEE (min) to VEE(max); Vee = Veea = GND)
O'C
Symbol
tpLH
tpHL

Propagation Delay to Oulput
0
SEL1
SEL2

tSKEW

Within-Device Skew
Dnm, Dnm to Qn
Da, Db, Dc, Dd 10 Q

tr
tf
1.

Characteristic

Rise/Fall TIme
20-80%

min

typ

25'C
max

min

typ

85'C
max

min

typ

Unit

Condition

ps
275
450
350

480
650
550

650
850
700

275
450
350

480
650
550

650
850
700

275
450
350

480
650
550

650
850
700
ps

60
40

60
40
ps

300

475

650

300

475

650

300

475

..
Within-device skew IS defined as Identical transllIOns on similar paths through a deVice; n =0,1,2 m =a,b,c,d .

ECLinPS and ECLinPS Lite
DL140-Rev4

max

2--67

650

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

9·Bit Latch With Parity
The MC10El100E175 is a 9-bit latch. It also features a tenth latched
output, ODDPAR, which is formed as the odd parity of the nine data
inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).

MC10E175
MC100E175

The E175 can also be used to generate byte parity by using D8 as the
parity-type select (L even parity, H odd parity), and using ODDPAR as
the byte parity output.

The LEN pin latches the data when asserted with a logical high and
makes the latch transparent when placed at a logic low level.

9-81T LATCH
WITH PARITY

• 9-Bit Latch
• Parity Detection/Generation
• BOOps Max. D to Output
• Reset
• Extended 1OOE VEE Range of - 4.2V to - 5.46V
• Internal75kn Input Pulldown Resistors

Pinout: 2B-Lead PLCC (Top View)
D6

Veeo

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

Veeo
06

as
Vee
LOGIC DIAGRAM

04 .
03

Veea
02

Veea

: BITS:
• 1-7 •
D

• All VCC and VCGO pins are tied together on the die.

PIN NAMES
Pin
Do-Ds
LEN
MR
Oo-Os
ODD PAR

Function

Data Inputs
Latch Enable
Master Reset
Data Outputs
Parity Output

aDDPAR

lEN----------'

MR-----------~

12193

2-6S

REV2

MOTOROLA

MC10E175 MC100E175
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea
DOC
Symbol

min

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current

typ

max

min

typ

max

Unit

150

flA

132
132

110
110

132
132

110
127

132
152

min

typ

25°C
max

min

typ

85°C
max

min

typ

max

Propagation Delay to Output
DtoO
DtoODDPAR

450

600

800
1450

450

600

1150

850

1150

800
1450

450

600

850
525

1150

525

700

900

525
525
525

700
700
700

900

525
525

700

LEN to ODDPAR

900
900

525
525

700
700
700

900
900
900

275
900

100
700

275
900

700

900

525

700
700
700

900

175
-300

-100
-70

175
-300

850

600

850

525
525

900
900
ps

0(0)
(ODDPAR)

Hold Time

0(0)
(ODDPAR)

o
tRR

Reset Recovery Time

tSKEW

Within-Device Skew

850

600

LEN, MR

DtoO
DtoODDPAR

75
200

Rise/Fall Times
20 - 80%

tr
tf

Cond

800
1450

Setup Time

Unit
ps

850

MR to O(tpHU
MR to ODDPAR(tpHU
ts

Cond

=VEE(min) to VEE(max); Vee = Veea =GND)

Characteristic

LEN to

min

150

DOC

tpHL

85°C
max

mA
110
110

AC CHARACTERISTICS (VEE

tpLH

typ

150

10E
100E

Symbol

=GND)
25°C

ps
300

500

800

300

500

..
..
Within-device skew IS dellned as Identical tranSItions on similar paths through a device .

800

300

500

800

FUNCTION TABLE
D

H
L

L
L
H

L
L
L
H

X
X

ECLinPS and ECLinPS Lite
DL140-Rev4

L
00

ODDPAR
H if odd no. of On HIGH
H if odd no. of On HIGH
00
L

2-69

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Error Detection/Correction
Circuit

MC10E193
MC100E193

The MC10El100E193 is an error detection and correction (EDAC)
circuit. Modified Hamming parity codes are generated on an 8-bit word
according to the pattern shown in the logic symbol. The P5 output gives
the parity of the whole word. The word parity is also provided at the PGEN
pin, after Odd/Even parity control and gating with the BPAR input. This
output also feeds to a 1-bit shiftable register, for use as part of a scan ring.

ERROR DETECTIONI
CORRECTION CIRCUIT

Used in conjunction with 12-bit parity generators such as the E160, a
SECDED (single error correction, double error detection) error system
can be designed for a multiple of an 8-bit word.
• Hamming Code Generation
• 8-Bit Word, Expandable
• Provides Parity of Whole Word
• Scannable Parity Register
• Extended 1OOE VEE Range of - 4.2V to - 5.46V

FN SUFFIX
PLASTIC PACKAGE
CASE 776-02

• 75kQ Input Pulldown Resistors

B INPUTS
036S7421

LOGIC DIAGRAM

Pinout: 28-Lead PLCC (Top View)
EN

HOLD S·IN

SHIFT elK Veeo PGEN
PARERR
PARERR
Vee
Ps

vEE

veeo

--------==1
~~Dr=====~~~~~~~~~~

PGEN

BPAR

P3
PARERR
PARERR

7196
Molorola. Inc. 1996

veeo

• All VCC and VCCO pins are tied together on the die.

HOlD-------I
S·IN--------I
SHIFT-------....J
elK-----------I

2-70

REV 3

MOTOROLA

MC10E193 MC100E193
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
D'C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

min

typ

25'C
max

min

85'C

typ

max

150

min

typ

150

max

Unit

150

!lA

Condition

mA
112
112

134
134

112
112

134
134

112
129

134
155

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
O'C
Symbol
tpLH
tpHL

Characteristic
Propagation Delay to Output
B to Pl, P2, P3, P4
Bto P5
EV/OD, BPAR to PGEN
Bto PGEN
CLK to PAR ERR
Setup TIme
SHIFT
S-IN
HOLD
EN
EV/OD
BPAR
B

Hold TIme
SHIFT
S-IN
HOLD
EN
EViOD
BPAR
B

Ir
If

Rise/Fall TImes
20-80%

ECLinPS and ECLinPS Lile
DL140-Rev4

min

typ

25'C
max

min

typ

85'C
max

min

typ

max

Unit

Condition

350
600
300

700
775
650
1000
550

400
300
750
500
1300
1300
1700

150
50
350
250
850
850
1100

400
300
750
500
1300
1300
1700

150
50
350
250
850
850
1100

200

-150
-50
-350
-250

200

-150
-50
-350
-250

350
400

1000
1150

350
400

850
1450
850

350
600
300

700
775
650
1000
550

1000
1150
850
1450
850

350
400
350
600
300

700
775
650
1000
550

1000
1150
850
1450
850
ps

400
300
750
500
1300
1300
1700

150
50
350
250
850
850
1100
ps

300
100
100
-200 -850
-200 -850
-300 -1100

300
100
100
-200
-200
-300

-850
-850
-1100

300

700

-150
200
300
-50
100 -350
100 -250
-200 -850
-200 -850
-300 -1100
ps

300

700

1100

2-71

1100

300

700

1100

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC10E195
MC100E195

Programmable Delay Chip
The MC10El100E195 is a programmable delay chip (PDC) designed
primarily for clock de-skewing and timing adjustment. It provides variable
delay of a differential ECl input transition.
The delay section consists of a chain of gates organized as shown in
the logic symbol. The first two delay elements feature gates that have
been modified to have delays 1.25 and 1.5 times the basic gate delay of
approximately 80 ps. These two elements provide the E195 with a
digitally-selectable resolution of approximately 20 ps. The required
device delay is selected by the seven address inputs D[0:6], which are
latched on chip by a high signal on the latch enable (lEN) control.

PROGRAMMABLE
DELAY CHIP

Because the delay programmability of the E195 is achieved by purely
differential ECl gate delays the device will operate at frequencies of >1.0
GHz while maintaining over 600 mV of output swing.
The E195 thus offers very fine resolution, at very high frequencies, that
is selectable entirely from a digital input allowing for very accurate system
clock timing.

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

An eighth latched input, D7, is provided for cascading multiple PDC's
for increased programmable range. The cascade logic allows full control
of multiple PDC's, at the expense of only a single added line to the data
bus for each additional PDC, without the need for any external gating.
•
•
•
•
•
•

2.0ns Worst Case Delay Range
~20psJDelay Step Resolution
> 1.0GHz Bandwidth
On Chip Cascade Circuitry
Extended 100E VEE Range of -4.2 to -5.46V
75Kn Input Pulldown Resistors

LEN
SET MIN
SET MAX
CASCADE

LEN

Pinout:
28-lead PLCC
(Top View)

VEE

Q/Q

25
D1
DO

PIN NAMES

IN/IN
EN
0[0:7]

Function

Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal

VBB

I:ii
en

::;;

....
w

w
c

I~(3

(3
en

«
u

LOGIC DIAGf'lAM - SIMPLIFIED

!!:!
IN
Q

LEN------1
SETMIN - - - - - - 1

SETMAA------~ri--r_--._---.--._--_r-_,r_--._J
DO
• DELAYS ARE 25% OR 50% LONGER THAN
STANDARD (STANDARD ~ BO PSI

CASCADE
CASCADE
D7

12193

2-72

REV 2

MOTOROLA

MC10E195 MC100E195
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
25'C

O'C
Symbol

Characteristic

IIH

Inpul HIGH Current

lEE

Power Supply Current
10E
100E

Min

Typ

Max

Min

Typ

150

85'C
Max

Min

Typ

150

Max

Unit

150

!lA

Condition

rnA
130
130

156
156

130
130

156
156

130
150

156
179

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
O'C
Symbol

Characteristic

Min

Typ

tpLH
tpHL

Propagation Delay
IN to Q; Tap=O
IN to Q; Tap = 127
EN to Q; Tap = 0
D7 to CASCADE

1210
3320
1250
300

1360
3570
1450
450

tRANGE

Programmable Range
tpD (max) - tpD (min)

2000

2175

55
115
250
505
1000

17
34
68
136
272
544
1088

Step Delay
DO High
Dl High
D2 High
D3 High
D4 High
D5High
D6 High

Duty Cycle Skew
tpHL-tpLH

Setup TIme
DtoLEN
Dto IN
ENtolN

200
800
200

Hold TIme
LEN to D
IN to EN

500
0

250

tjit

Jitter

tr
tf

Output Rise/Fall TIme
20-80%(Q)
20--£0% (CASCADE)

85'C
Max

Min

Typ

Max

Unit

1510
3820
1650
700

1240
3380
1275
300

1390
3630
1475
450

2050

2240

1540
3880
1675
700

1440
3920
1350
300

1590
4270
1650
450

Notes

2375

2580

65
140
305
620
1240

21
42
84
168
336
672
1344

1765
4720
1950
700

Linearity

Typ

Lin

Release TIme
ENtolN
SET MAX to LEN
SET MIN to LEN

Min

tSKEW

25'C
Max

17.5

35
105
180
325
620
1190

55
115
250
515
1030

70
140
280
560
1120

105
180
325
620
1220

120
205
380
740
1450
7
ps

±30

1
ps

200
800
200

500
0

250

200
800
200

500
0

250

2
3
ps
4
ps

300
800
800

300
800
800
<5.0

<5.0

ps
125
300

225
450

325
650

125
300

225
450

325
650

125
300

225
450

325
650

1. Duty cycle skew guaranteed only for differential operation measured from the cross pOint of the Input to the cross pOint of the output.
2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
3. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/iN to prevent an output response greater than
±75 mV to that IN/iN transition.
4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going iN to prevent an output response
greater than ±75 mV to that IN/IN transition.
5. This release time is the minimum time that EN must be deasserted prior to the next IN/iN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of
asserted delay control inputs will typically realize DO resolution steps across the specified programmable range.
7. The linearity specification guarantees to which delay control Input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the DO input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the DO input is the LSB. With the Dl input as the LSB
the device is guaranteed to be monotonic over all specified environmental conditions and process variation.
8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.

ECLinPS and ECLinPS Lite
DL140-Rev4

2-73

MOTOROLA

MC10E195 MC100E195

ADDRESS BUS (AD-AS)

~--~----+-+-+-+-+-~

DO
LEN

E195
Chip #1

E195
Chip #2

Vee
veeo

a(]-----{]
INPUT

OUTPUT

z :::;
Q
C3 « veeo
:E
Ii:; Ii:;
00

liii

en en

Figure 1. Cascading Interconnect Architecture

Cascading Multiple E195's
To increase the programmable range of the E195 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E195's without the need for any
external gating. Furthermore this capability requires only one
more address line per added E195. Obviously cascading
multiple PDC's will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay.
Figure 1 illustrates the interconnect scheme for cascading
two E195's. As can be seen, this scheme can easily be
expanded for larger E195 chains. The D7 input of the E195 is
the cascade control pin. With the interconnect scheme of
Figure 1 when 07 is asserted it Signals the need for a larger
programmable range than is achievable with a single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D7 of
chip #1 above is low the cascade output will also be low while
the cascade bar output will be a logical high. In this condition
the SET MIN pin of chip #2 will be asserted and thus all of the
latches of chip #2 will be reset and the device will be set at its
minimum delay. Since the RESET and SET inputs of the
latches are overriding any changes on the AD-AS address bus
will not affect the operation of chip #2.

Chip #1 on the other hand will have both SET MIN and SET
MAX de-asserted so that its delay will be controlled entirely by
the address bus AD-AS. If the delay needed is greater than
can be achieved with 31.75 gate delays (1111111 on the
AD-AS address bus) D7 will be asserted to signal the need to
cascade the delay to the next E195 device. When D7 is
asserted the SET MIN pin of chip #2 will be de-asserted and
the delay will be controlled by the AD-AS address bus. Chip #1
on the other hand will have its SET MAX pin asserted resulting
in the device delay to be independent of the AD-AS address
bus.
When the SET MAX pin of chip #1 is asserted the DO and D1
latches will be reset while the rest of the latches will be set. In
addition, to maintain monotonicity an additional gate delay is
selected in the cascade circuitry. As a result when 07 of chip
#1 is asserted the delay increases from 31.75 gates to 32
gates. A 32 gate delay is the maximum delay setting for the
E195.
To expand this cascading scheme to more devices one
simply needs to connect the 07 input and CASCADE outputs
of the current most significant E195 to the new most significant
E195 in the same manner as pictured in Figure 1. The only
addition to the logic is the increase of one line to the address
bus for cascade control of the second PDC.

TO SELECT MULTIPLEXERS

CASCADE
~

SET MIN-,-j---'------+--'------I---''-------I--L------+---'-------f--'------If-..J
______' _________''_________ L_ _ _ _ _ _ _ ___'__ _ _ _ _ _ _ _

SET~---'---------..1---

Figure 2. Expansion of the Latch Section of the E195 Block Diagram

MOTOROLA

2-74

ECLinPS and ECLinPS Lile
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Programmable Delay Chip

MC10E196
MC100E196

The MC10El100E196 is a programmable delay chip (PDC) designed
primarily for very accurate differential ECl input edge placement
applications.
The delay section consists of a chain of gates and a linear ramp delay
adjust organized as shown in the logic symbol. The first two delay
elements feature gates that have been modified to have delays 1.25 and
1.5 times the basic gate delay of approximately 80 ps. These two
elements provide the E196 with a digitally-selectable resolution of
approximately 20 ps. The required device delay is selected by the seven
address inputs D[0:6], which are latched on chip by a high signal on the
latch enable (lEN) control.
The FTUNE input takes an analog voltage and applies it to an internal
linear ramp for reducing the 20 ps resolution still further. The FTUNE input
is what differentiates the E196 from the E195.
An eighth latched input, D7, is provided for cascading multiple PDC's
for increased programmable range. The cascade logic allows full control
of multiple PDC's, at the expense of only a single added line to the data
bus for each additional PDC, without the need for any external gating.

PROGRAMMABLE
DELAY CHIP

•
•
•
•

2.0ns Worst Case Delay Range
~20ps/Delay Step Resolution
Linear Input for lighter Resolution
>1.0GHz Bandwidth
o On Chip Cascade Circuitry
• Extended 100E VEE Range of -4.2 to -5.46V
o 75Kn Input Pulldown Resistors

FN SUFFIX
PLASTIC PACKAGE
CASE 776-02

PIN NAMES
Pin
IN/IN
EN
D[0:7)

Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE

Function
Signal Input
Input Enable
Mux Selecl Inpuls
Signal Output
Latch Enable
Min Delay Set
Max Delay Sel
Cascade Signal
Linear Voltage Input

LOGIC DIAGRAM - SIMPLIFIED

!!:!
IN

LEN

-------1

SET MIN -------1

SETMAA----~ri-r_-,_--.--~-_r-_,r_-,_J
DO

• DELAYS ARE 25% OR 50% LONGER THAN
STANDARD (STANDARD ~ 80 PS)

12193

2-75

REV2

MOTOROLA

MC1 OE196 MC100E196

Pinout: 28-Lead PLCC (Top View)
D2

NC
FTUNE

LEN

Vcc

VEE

Vcca

VBB

Vcca
10
NC

::;;

t:u

''""'

'" '" ~

l~a

[2J
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea = GND)
DOC

Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

Min

Typ

25°C
Max

Min

150

Min

Typ

Propagation Delay
IN to Q; Tap 0
IN to Q; Tap 127
EN to Q; Tap 0
D7 to CASCADE

1210
3320
1250
300

1360
3570
1450
450

tRANGE

Programmable Range
tpD (max) - tpD (min)

2000

2175

55
115
250
505
1000

17
34
68
136
272
544
1088

Step Delay
DO High
Dl High
D2 High
D3 High
D4High
D5High
D6 High

Lin

Linearity

tSKEW

Duty Cycle Skew
tpHL-tpLH

MOTOROLA

Typ

Max

Unit

150

IlA

Condition

156
156

130
130

156
156

130
150

=Veea =GND)
25°C

Max

156
179

Min

Typ

85°C
Max

Min

Typ

Max

Unit

Notes

tpLH
tpHL

=
=
=

Min

mA
130
130

DOC
Characteristic

85°C
Max
150

AC CHARACTERISTICS (VEE =VEE(min) to VEE(max); Vee

Symbol

Typ

1510
3820
1650
700

1240
3380
1275
300

1390
3630
1475
450

2050

2240

55
115
250
515
1030

17.5
35
70
140
280
560
1120

1540
3880
1675
700

1440
3920
1350
300

1590
4270
1650
450

2375

2580

65
140
305
620
1240

21
42
B4
168
336
672
1344

1765
4720
1950
700
ps
ps

105
180
325
620
1190

105
180
325
620
1220

120
205
380
740
1450
7
ps

±30

2-76

±30

ECLinPS and ECLinPS Lite
DLI40-Rev4

MC10E196 MC100E196
AC CHARACTERISTICS (continued) (VEE = VEE(min) to VEE(max); Vee = Veeo = GND)
DOC
Symbol
ts

Characteristic

Min

25°C
Max

Min

05°C

Typ

Max

Min

Typ

Max

Unit

Notes

Setup lime
Dto LEN
DtolN
ENtolN

200
800
200

Hold lime
LENto D
INtoEN

500
0

250

200
800
200

500
0

250

200
800
200

500
0

250

2
3
ps

tjit

Jitter

tr
tf

Output Rise/Fall Time
2Q-80%(Q)
2Q-80% (CASCADE)

4
ps

Release lime
EN to IN
SET MAX to LEN
SET MIN to LEN

Typ

300
800
800

300
800
800
<5.0

<5.0

ps
125
300

225
450

325
650

125
300

225
450

325
650

125
300

225
450

325
650

1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross pOint of the output.
2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
3. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/TN to prevent an output response greater than
±75 mV to that IN/TN transition.
4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going TN to prevent an output response
greater than ±75 mV to that INIIN transition.
5. This release time is the minimum time that EN must be deasserted prior to the next IN/TN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
6. Specification limits represent the amount 01 delay added with the assertion of each individual delay control pin. The various combinations of
asserted delay control inputs will typically realize DO resolution steps across the specified programmable range.
7. The linearity specilication guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs On). Typically the device will be monotonic to the DO input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the DO input is the LSB. With the 01 input as the LSB
the device Is guaranteed to be monotonic over all specilied environmental conditions and process variation.
8. The jitter 01 the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.

ANALOG INPUT CHARACTERISTICS
Ftune =Vee to VEE

140

100
90

120
u;-

w
c

100

'"
if
~
D..

I\,

'"
II:

\
\

D..

'""

-4.5

if
c

.....

!;(

I\,

-3.5

r-.

-2.5
-1.5
FTUNE VOLTAGE (V)

-5

-4

-3

-2

r--1

FTUNE VOLTAGE (V)

Propagation Delay versus Ftune Voltage
(100E196)

ECLinPS and ECLinPS Lite
DL140-Rev4

10
-0.5

r--

Propagation Delay versus Ftune Voltage
(10E196)

2-77

MOTOROLA

MC10E196 MC100E196
USING THE FTUNE ANALOG INPUT
The analog FTUNE pin on the E196 device is intended to
enhance the 20 ps resolution capabilities of the fully digital
E195. The level of resolution obtained is dependent on the
number of increments applied to the appropriate range on the
FTUNE pin.
To provide another level of resolution the FTUNE pin must
be capable of adjusting the delay by greater than the 20 ps
digital resolution. From the provided graphs one sees that this
requirement is easily achieved as over the entire FTUNE
voltage range a 100 ps delay can be achieved. This extra
analog range ensures thatthe FTUNE pin will be capable even
under worst case conditions of covering the digital
resolution.Typically the analog input will be driven by an
external OAC to provide a digital control with very fine analog
output steps. The final resolution of the device will be
dependent on the width of the OAC chosen.
To determine the voltage range necessary for the FTUNE
input, the graphs provided should be used. As an example if a
range of 40 ps is selected to cover worst case conditions and
ensure coverage of the digital range, from the 100E196 graph
a voltage range of-3.25 V to-4.0 V would be necessary on the
FTUNE pin. Obviously there are numerous voltage ranges
which can be used to cover a given delay range, users are
given the flexibility to determine which one best fits their
designs.
Cascading Multiple E196's
To increase the programmable range of the E196 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E196's without the need for any
external gating. Furthermore this capability requires only one
more address line per added E196. Obviously cascading
multiple POC's will result in a larger programmable range,
however, this increase is at the expense of a longer minimum
delay.
Figure 1 illustrates the interconnect scheme for cascading
two EI96's. As can be seen, this scheme can easily be

expanded for larger E196 chains. The 07 input of the E196 is
the cascade control pin. With the interconnect scheme of
Figure 1 when 07 is asserted it signals the need for a larger
programmable range than is achievable with a single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When 07 of
chip #1 above is low the cascade output will also be low while
the cascade bar output will be a logical high. In this condition
the SET MIN pin of chip #2 will be asserted and thus all of the
latches of chip #2 will be reset and the device will be set at its
minimum delay. Since the RESET and SET inputs of the
latches are overriding any changes on the AO-A6 address bus
will not affect the operation of chip #2.
Chip #1 on the other hand will have both SET MIN and SET
MAX de-asserted so that its delay will be controlled entirely by
the address bus AQ-A6. If the delay needed is greater than
can be achieved with 31.75 gate delays (1111111 on the
AQ-A6 address bus) 07 will be asserted to signal the need to
cascade the delay to the next E196 device. When 07 is
asserted the SET MIN pin of chip #2 will be de-asserted and
the delay will be controlled by the AO-A6 address bus. Chip #1
on the other hand will have its SET MAX pin asserted
resulting in the device delay to be independent of ttie AQ-A6
address bus.
When the SET MAX pin of chip #1 is asserted the 00 and 01
latches will be reset while the rest of the latches will be set. In
addition, to maintain monotonicity an additional gate delay is
selected in the cascade circuitry. As a result when 07 of chip
#1 is asserted the delay increases from 31.75 gates to 32
gates. A 32 gate delay is the maximum delay setting for
the E196.
When cascading multiple POC's it will prove more cost
effective to use a single E196 for the MSB of the chain while
using E195 for the lower order bits. This is due to the fact that
only one fine tune input is needed to further reduce the delay
step resolution.

ADDRESS BUS (AO-A6)

~--r+----+-+-+-+-~

FTUNE

Dl
DO

E196
Chip #1

LEN
VEE

Vee
veeo

INPUT

~ ~ 5! veeoQ
ffi Iii Iii ~
z
:E

E196
Chip #2

vss

WI veco

;;:: ~ ~
:; :;

OUTPUT

Fw Iii Iii ~~
U)

Figure 1. Cascading Interconnect Architecture

MOTOROLA

2-78

ECLinPS and ECLinPS Lite

DL140-Rev4

MC10E196 MC100E196
TO SELECT MULTIPLEXERS

CASCADE
CASCADE

SET MIN--+-----'---+---'----+---'----1f--'-----f--'----+-'-----+--'
S8MAX---'-------'-----~-----'-----L------'----~

Figure 2. Expansion of the Latch Section of the E196 Block Diagram

ECLinPS and ECLinPS Lite
DL140- Rev 4

2-79

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Advance Information

MC10E197

Data Separator
The MC10E197 is an integrated data separator designed for use in
high speed hard disk drive applications. With data rate capabilities of up
to 50Mb/s the device is ideally suited for today's and future
state-of-the-art hard disk designs.
The E197 is typically driven by a pulse detector which reads the
magnetic information from the storage disk and changes it into ECL
pulses. The device is capable of operating on both 2:7 and 1:7 RLL
coding schemes. Note that the E197 does not do any decoding but rather
prepares the disk data for decoding by another device.
For applications with higher data rate needs, such as tape drive
systems, the device accepts an external VCO. The frequency capability
of the integrated VCO is the factor which limits the device to 50Mb/s.
A special anti-equivocation circuit has been employed to ensure timely
lock-up when the arriving data and VCO edges are coincident.
Unlike the majority of the devices in the ECLinPS family, the E197 is
available in only 10H compatible ECL. The device is available in the
standard 28-lead PLCC.
Since the E197 contains both analog and digital circuitry, separate
supply and ground pins have been provided to minimize noise coupling
inside the device. The device can operate on either standard negative
ECL supplies or, as is more common, on positive voltage supplies.
•
•
•
•

DATA SEPARATOR

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

2:7 and 1:7 RLL Format Compatible
Fully Integrated VCO for 50Mb/s Operation
External VCO Input for Higher Operating Frequency
Anti-equivocation Circuitry to Ensure PLL Lock
LOGIC DIAGRAM
RDEN----------------------------------~

REFCLK

---------IPiiAsE:FREru~

CAP1
PUMPUP

VCOIN _":""''=:::r---'

PUMPDN

EXNCO------~

RSETUP

ENVCO --------------'
RAWD -------~~~

' - - - - - - - RSETDN

ACQ---------1~~~

RDATA

TYPE-------i..J~!!:illY.J

RDCLK

This document contains information on a new product. Specifications and information herein are subject to
change without notice.

12/93

2-80

REV 2

MOTOROLA

MC10E197
Pinout: 2B-Lead PLCC (Top View)
0

u
>
U
>u

;;;;
0

u
D'"

0::
«
u

()

.J:'

TEST

RDCLK

EXTVCO

RDCLK

ENVCO

VCC
RSDATA

VEE
ACO

RSDATA

TYPE

PUMPUP

RDEN

RSETDN

~
u

""0:

~
0:

:z
c
D::;;
::::>

D-

::::>

Iii
en
0:

.J:'

[]]

PIN DESCRIPTIONS
REFClK

Reference clock equivalent to one clock cycle per decoding window.

RDEN

Enable data synchronizer when HIGH. When lOW enable the phase/frequency detector steered by REFClK.

RAWD

Data Input to Synchronizer logic.

VCOIN

VCO control voltage input

CAPI/CAP2

VCO frequency controlling capacitor inputs

ENVCO

VCO select pin. lOW selects the internal VCO and HIGH selects the external VCO input. Pin floats lOW when left open.

EXTVCO

External VCO pin selected when ENVCO is HIGH

ACO

Acquisition circuitry select pin. This pin must be driven HIGH at the end of the data sync field for some sync field types.

TYPE

Selects between the two types of commonly used sync fields. When lOW it selects a sync field interspersed with 3 zeroes
(2:7 Rll code). When HIGH it selects a sync field interspersed with 2 zeroes (1:7 Rll code).

TEST

Input included to initialize the clock flip-flop for test purposes only. Pin should be left open (lOW) in actual application.

PUMP UP

Open collector charge pump output for the signal pump

PUMPDN

Open collector charge pump output for the reference pump

RSETUP

Current setting resistor for the signal pump

RSETDN

Current setting resistor for the reference pump

RDATA

Synchronized data output

RDClK

Synchronized clock output

VCC, VCCO,
VCCVCO

Most positive supply rails. Digital and analog supplies are independent on chip

VEE, VEEVCO

Most negative supply rails. Digital and analog supplies are independent on chip

EClinPS and EClinPS lite
D1140-Rev4

2-81

MOTOROLA

MC10E197
DC CHARACTERISTICS (VEE =VEE(min) to VEE (max); Vee

=GND or Vee =4.75V to 5.25V; VEE =GND)

DOC
Characteristic

Symbol

min

IIH

Input HIGH Current

IlL

Input LOW Current

0.5

lEE

Power Supply Current

ISET

Charge Pump Bias Current

0.5

lOUT

Charge Pump Output
Leakage Current

VACT

PUMPUP/PUMPDN
Active Voltage Range

10H LOGIC LEVELS
DC CHARACTERISTICS (VEE

25°C
max

typ

min

max

0.5
150

180

0.5

max

Unit

Condition

150

IJA
IJA

180

VCC

0.5
150

180

150

0.5

1
VCC-2.5

typ

150

VCC-2.5

VCC

VCC-2.5

VCC

Characteristic

min

25°C

typ

max

min

max

Unit

-1020

-840

-980

-810

-910

-720

VOL

Output LOW Voltage

-1950

-1630

-1950

-1630

-1950

-1595

ViH

input HIGH Voltage

-1170

-840

-1130

-810

-1060

-720

VIL

Input LOW Voltage

-1950

-1480

-1950

-1480

-1950

-1445

POSITIVE EMITTER COUPLED LOGIC LEVELS
DC CHARACTERISTICS (VEE =VEEVea =GND; Vee

typ

85°C

Output HiGH Voltage

VOH

Characteristic

min

max

min

typ

Condition

=Veea1 =Veevea =+5 volts')

DOC
Symbol

=VEE (min) to VEE(max); Vee =Veea + Vee01 =Veevea =GND)
DOC

Symbol

85°C

typ

25°C
max

min

max

Unit

VOH

3980

4160

4020

4190

4090

4280

VOL

Output LOW Voltage

3050

3370

3050

3370

3050

3405

VIH

Input HIGH Voltage

3830

4160

3870

4190

3940

4280

Input LOW Voltage
3050
VIL
,
1. VOH and VOL levels Will vary 1.1 With VCC

3520

3050

3555

AC CHARACTERISTICS (VEE =VEE(min) to VEE(max); Vee

typ

85°C

Output HIGH Voltage

typ

max

min

typ

Condition

=GND or Vee =4.75V to 5.25V; VEE =GND)

O°C

25°C
min

85°C
Unit

Condition

TIme from RDATA Valid to
Rising Edge of RDCLK

TVCO-550

TVCO-500

4,7

TIme from Rising Edge of
RDCLK to RDATA invalid

TVCO

4,7

tSKEW

Skew Between RDATA and
RDATA

Symbol

tvco

Characteristic

min

max

300

Frequency of the VCO

150

Tuning Ratio

1.53

max

300
150

1.87

min

1.53

max

300
150

1.87

1.53

ps
MHz

1.87

·5
6

1. Applies to the Input current for each Input except VCOIN
2. For a nominal set current of 3.72mA, the resistor values for RSETUP and RSETDN should be 130Q(0.1 %). Assuming no variation between
these two reSistors, the current match between the PUMPUP and PUMPDN output Signals should be within ±3%. ISET is calculated as (VEE+
1.3v - VBE)/R; where R is RSETUP or RSETDN and a nominal value lor VBE is 0.85 volts.
3. Output leakage current of the PUMPUP or PUMPDN output Signals when at a LOW level.
4. TVCO is the period of the VCO.
5. The VCO frequency determined with VCOIN = VEE + 0.5 volts and using a 10pF tuning capacitor.
6. Thetuning ratioisdefinedastheratiooftvCOMAXto FVCOMINwheretvCOMAX ismeasuredatVCOIN= 1.3V+ VEE andtvCOMAXismeasured
at VCOIN = 2.6V + VEE.

MOTOROLA

2-82

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E197

x x
x x X

, . . - - - - - RDATA

' - - - - - - RDATA

, . - - - - - RDCLK

-IS

.1.

' - - - - - - RDCLK

IH-

SETUP AND HOLD TIMING DIAGRAMS

APPLICATIONS INFORMATION

General Operation
Operation
The E197 is a phase-locked loop circuit consisting of an
internal vee, a Data Phase detector with associated
acquisition circuitry, and a Phase/Frequency detector (Figure
1). In addition, an enable pin(ENVee) is provided to disable
the internal vee and enable the external vee input. Hence,
the user has the option of supplying the vee signal.
The E197 contains two phase detectors: a data phase
detector for synchronizing to the non-periodic pulses in the
read data stream during the data read mode of operation, and
aphase/frequencydetectorforfrequency (and phase) locking
to an external reference clock during the "idle" mode of
operation. The read enable (RDEN) pin muxes between these
two detectors.
Data Read Mode
The data pins (RAWD) are enabled when the RDEN pin is
placed at a logic high level, thus enabling the Data Phase
detector (Figurel) and initiating the data read mode. In this
mode, the loop is servoed by the timing information taken from
the positive edges of the input data pulses. This phase
detector samples positive edges from the RAWD signal and
generates both a pump up and pump down pulse from any
edge of the input data pulse. The leading edge of the pump up
pulse is time modulated by the leading edge of the data Signal,
whereas the rising edge of the pump up pulse is generated
synchronous to the vee clock. The falling edge of the pump
down pulse is synchronous to the falling edge of the vee
clock and the rising edge of the pump down signal is
synchronous to the rising edge of the vee clock. Since both
edges of the vee are used the internal clock a duty cycle of
50%. This pulse width modulation technique is used to
generate the servoing signal which drives the vee. The pump
down signal is a reference pulse which is included to provide
an evenly balanced differential system, thereby allowing the
synthesis of a vee input control signal after appropriate signal
processing by the loop filter.

ECLinPS and ECLinPS Lite
DL140-Rev4

By using suitable external filter circuitry, a control signal for
input into the vee can be generated by inverting the pump
down signal, summing the inverted signal with the pump up
Signal and averaging the result. The polarity of this control
signal is defined as zero when the data edges lead the clock
by a hal! clock cycle. I! the data edges are advanced with
respect to the zero polarity dataIVCe edge relationship, the
control signal is defined to have a negative polarity; whereas
if the vee is advanced with respect to the zero polarity
datalVee edge relationship, the control signal is defined to
have a positive polarity. I! there is no data edge present at the
RAWD input, the corresponding pump up and pump down
outputs are not generated and the resulting control output is
zero.
Acquisition Circuitry
The acquisition circuitry is provided to assist the data phase
detector in phase locking to the sync field that precedes the
data. For the case in which lock-up is attempted when the data
edges are coincident with the veo edges, the pump down
signal may enter an indeterminate state for an unacceptably
long period due to the violation of internal set up and hold
times. After an initial pump down pulse, the circuit blocks
successive pump down pulses, and inserts extra pump up
pulses, during portions of the sync field that are known to
contain zeros. Thus, the data phase detector is forced to have
a nonzero output during the lock-up period, and the restoring
force ensures correction of the loop within an acceptable time.
Hence, this circuitry provides a quasi-deterministic pump
down output signal, under the condition of coincident data and
vee edges, allowing lock-up to occur with excessive delays.
The AeO line is provided to disable (disable = HIGH) the
acquisition circuit during the data portion of a sector block.
Typically, this circuit is enabled at the beginning of the sync
field by a one-shot timer to ensure a timely lock-up.
The TYPE line allows the choice between two sync field
preamble types; transitions interspersed with two zeros
between transitions. These types of sync fields are used with
the 1:7 and 2:7 coding schemes, respectively.

2-83

MOTOROLA

MC10E197
Idle Mode
In the absence of data or when the drive is writing to the disk,
PLL servoing is accomplished by pulling the read enable line
(RDEN) low and providing a reference clock via the REFeLK
pins. The condition whereby RDEN is low selects the
Phase/Frequency detector (Figure 1) and the 10E197 is said
to be operating in the "idle mode". In order to function as a
frequency detector the input waveform must be periodic. The
pump up and pump down pulses from the Phase/Frequency
detector will have the same frequency, phase and pulse width
only when the two clocks that are being compared have their
positive edges aligned and are of the same frequency.
As with the data phase detector, by using suitable external
filter Circuitry, a veo input control signal can be generated by
inverting the pump down Signal, summing the inverted signal
with the pump up signal and averaging the result. The polarity

of this control signal is defined as zero when all positive edges
of both clocks are coincident. For the case in which the
frequencies of the two clocks are the same but the clock edges
olthe reference clock are slightly advanced with respectto the
veo clock, the control clock is defined to have a positive
polarity. A control signal with negative polarity occurs when
the edges of the reference clock are delayed with respect to
those of the veo. If the frequencies of the two clocks are
different, the clock with the most edges per unit time will initiate
the most pulses and the polarity of the detector will reflect the
frequency error. Thus, when the reference clock is high in
frequency than the veo clock the polarity of the control signal
is positive; whereas a control signal with negative polarity
occurs when the frequency of the reference clock is lowerthan
the veo clock.

Phase-Lock Loop Theory
Introduction
Fa
Phase lock loop (PLL) circuits are fundamentally feedback
systems used to synchronize the frequency of an oscillator to
an incoming signal. In addition to frequency synchronization,
the PLL circuitry is designed to minimize the phase difference
between the system input and output signals. A block diagram
of a feedback control system is shown in Figure 1.

Figure 2. Phase Lock Loop Block Diagram
The closed loop transfer function is:

where:
A(s) is the product of the feed-forward transfer functions.

Xi(S)
Xi(S)o----t~

/--....---0 Xo(s)

K$ ~ F(s)

Xo(s)

. 1+

~ ~o F(s)

where:
~=

the phase detector gain.
the veo gain. Since the veo introduces a
pole at the origin of the s-plane, Ko is divided
bys.
F(s) = the transfer function of the loop filter.

1<0=

Figure 1. Feedback System
~(s) is the product of the feedback transfer functions.

The 10E197 is designed to implement the phase detector
and veo functions in a unity feedback loop, while allowing the
user to select the desired filter function.

Gain Constants
The transfer function for this closed loop system is
A(s)
1 + A(s)~(s)
Typically, phase lock loops are modeled as feedback
systems connected in a unity feedback configuration (~(s)=1)
with a phase detector, a veo (voltage controlled oscillator),
and a loop filter in the feed-forward path, A(s). Figure 2
illustrates a phase lock loop as a feedback control system in
block diagram form.

MOTOROLA

As mentioned, each of the three sections in the phase lock
loop block diagram has an associated open loop gain
constant. Further, the gain constant of the filter Circuitry is
composed of the product of three gain constants, one for each
filter subsection. The open loop gain constant of the
feed-forward path is given by
Kol = ~ • Ko • K1 • KI •

eqt. 1

and obtained by performing a root locus analysis.
Phase Detector Gain Constant
The gain of the phase detector is a function of the operating
mode and the data pattern. The 10E197 provides data

2-84

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E197
separation for signals encoded in 2:7 or 1:7 RLL encoding
schemes; hence, Tables 1 and 2 are coding tables for these
schemes. Table 3 lists nominal phase detector gains for both
2:7 and 1:7 sync fields.
NRZ Data Sequence

Code Sequence

00
01

1000
0100

100

001000

101
111

100100
000100

1100
1101

00001000
00100100

Table 1. 2:7 RLL Encoding Table
NRZ Data Sequence

Code Sequence

XOI

01
10

010

1100

010001

1101
1110
1111

XOOOOO
XOOOOI

XOO

eqt.2
The individual gain constants are defined in the appropriate
subsections of this document.

Loop Filter
The two major functions of the loop filter are to remove any
noise or high frequency components present in the phase
detector output signal and, more importantly, to control the
characteristics which determine the dynamic response of the
phase lock loop; i.e. capture range, loop bandwidth, capture
time, and transient response.
Although a variety of loop filter configurations exist, this
section will only describe a filter capable of performing the
signal processing as described in the Data Read Mode and
the Idle Mode sections. The loop filter consists of a differential
summing amplifier cascaded with an augmenting integrator
which drives the VeOIN input to the 1OE197 through a resistor
divider network (Figure 3).
The transfer function and the element values for the loop
filter are derived by dividing the filter into three cascaded
subsections: filter input, augmenting integrator, and the
voltage divider network (Figure 4).

Loop Filter Transfer Function

010000

An X In the leading bit of a code sequence IS assigned the
complement of the bit
Table 2. 1:7 RLL Encoding Table
Sync Pattern

Read Mode

Idle Mode

2:7

121 mY/radian

484 mViradian

1:7

161 mY/radian

483 mY/radian

The open loop transfer function of the phase lock loop is the
product of each individual filter subsection, as well as the
phase detector and veo. Thus, the open loop filter transfer
function is:
Fo(s) = K$ *

* F1 (s) * FI(S) * Fd(S)

where:
F1 (s) = K1 *(s +1 P1) *

Table 3. Phase Detector Gain Constants

[s2 +

(2~ro:1) s + ~11

VCO Gain Constant
The gain of the veo is a function of the tuning capacitor.
For a value of 10pF a nominal value of the gain, Ko, is
20MHz per volt.
Filter Circuitry Gain Constant(s)

Fd(S) = Kd * _ _
1_
(S+P2)

The open loop gain constant of the filter circuitry is given by:

PUMPUPO-----~~~~-.----~~------~~~_1--~~~

PUMPDN o-----_~'VV~_'I

Veeveo
elN

VEEVCO

VCCVCO

Figure 3. Loop Filter Circuitry

ECLinPS and ECLinPS Lite
DL140-Rev4

2-85

MOTOROLA

MC10E197
a circuit configuration capable of providing this dual
bandwidth function. Analysis of the filter input circuitry yields
the transfer function:
Fj(s)

Figure 4. Loop Filter Block Diagram

The gain constant is defined as:

A root locus analysis is performed on the open loop transfer
function to determine the final pole-zero locations and the
open loop gain constant for the phase lock loop. Note that the
open loop gain constant impacts the crossover frequency and
that a lower frequency crossover point means a much more
efficient filter. Once these positions and constants are
determined the component values may be calculated.

eqt. 3
where:
A1= op-amp gain constant for the
selected pole positions.
GIN = phase detector shunt capacitor.
The real pole is a function of the input resistance to the
op-amp and the shunt capacitors connected to the phase
detector output. For stability the real pole must be placed
beyond the unity gain frequency; hence, this pole is typically
placed midway between the unity crossover and phase
detector sampling frequency, which should be about ten
times greater.

IPUMPUP

RSETDN

RSETUPo-_----,

IpUMPDN
VCCVCO

4640

VEEVCO

Figure 5. Filter Input Sunsection

ELECTRONIC SWITCH

Filter Input
VEEVCO

The primary function of the filter input subsection is to
convert the output of the phase detector into a single ended
signal for subsequent processing by the integrator circuitry.
This subsection consists of the 1OE197 charge pump current
sinks, two shunt capacitors, and a differential summing
amplifier (Figure 5).
Hence, this portion of the filter circuit contributes a real pole
and two complex poles to the overall loop transfer function
F(s). Before these pole locations are selected, appropriate
values for the current setting resistors (RSETUP and
RSETDN) must be ascertained. The goal in choosing these
resistor values is to maximize the gain of the filter input
subsection while ensuring the charge pump output transistors
operate in the active mode. The filter input gain is maximized
for a charge pump current of 1.1 mA; a value of 464Q for both
RSETUP and RSETDN yields a nominal charge pump current
of 1.1mA.
It should be noted that a dual bandwidth implementation
of the phase lock loop may be achieved by modifying the
current setting resistors such that an electronic switch
enables one of two resistor configurations. Figure 6 shows

MOTOROLA

Figure 6. Dual Bandwidth Current
Source Implementation
The second order pole set arises from the two pole model
for an op-amp. The open loop gain and the first open loop pole
for the op-amp are obtained from the data sheets. Typically,
op-amp manufacturers do not provide information on the
location of the second open loop pole; however, it can be
approximated by measuring the roll off of the op-amp in the
open loop configuration. The second pole is located where the
gain begins to decrease at a rate of 40dB per decade. The
inclusion of both poles in the differential summing amplifier
transfer function becomes important when closing the
feedback path around the op-amp because the poles migrate;
and this migration must be accounted for to accurately
determine the phase lock loop transient performance.
Typically the op-amp poles can be approximated by a pole
pair occurring as a complex conjugate pair making an angle
of 45° to the real axis of the complex frequency plane. Two
constraints on the selection of the op-amp pole pair are that

2-86

ECLinPS and ECLinPS Lite
DL140- Rev 4

MC10E197
the poles lie beyond the crossover frequency and they are
positioned for near unity gain operation. Performing a root
locus analysis on the op-amp open loop configuration and
adhering to the two constraints yields the pole positions
contributed by the op-amp.
Determination of Element Values
Since the difference amplifier is configured to operate as a
differential summer the resistor values associated with the
amplifier are of equal value. Further, the typical input
resistance to the summing amplifier is 1kQ; thus, the op-amp
resistors are set at 1 kQ. Having set the input resistance to the
op-amp and selected the position of the real pole, the value of
the shunt capacitors is determined using the following
relationship:
eqt. 4

a complex conjugate pair making an angle of 45 0 to the real
axis of the complex frequency plane; are positioned for near
unity gain operation; and are located beyond the crossover
frequency. Since both the summing and integrating op-amps
are realized by the same type of op-amp (MC34182D), the
open loop pole positions for both amplifiers will be the same.
Further, the loop transfer function contains two poles
located at the origin, one introduced by the integrator and the
other by the VCO; hence a zero is necessary to compensate
for the phase shift produced by these poles and ensure loop
stability. The op-amp will be stable if the crossover point
occurs before the transfer function phase angle becomes
1800 • The zero should be positioned much less than one
decade before the unity gain frequency.
As in the case of the filter input circuitry, the poles and zero
from this analysis will be used as open loop poles and a zero
when performing the root locus analysis for the complete
system.
Determination of Element Values

Augmenting Integrator
The augmenting integrator consists of an active filter with a
lag-lead network in the feedback path (Figure 7).
AlA

The location of the zero is used to determine the element
values for the augmenting integrator. The value of the
capacitor, CA, is selected to provide adequate charge storage
when the loop is not sampling data. A value of 0.1!!F is
sufficient for most applications; this value may be increased
when the RDCLK frequency is much lower than 4 MHz. The
value of RA is governed by:
eqt. 6

MC34182

For unity gain operation of the integrating op-amp the value of
RIA is selected such that:

Vccvco
Figure 7. Integrator Subsection

Analysis of this portion of the filter circuit yields the transfer
function:

It should be noted that although the zero can be tuned by
varying either RA or CA, caution must be exercised when
adjusting the zero by varying CA because the integrator gain is
also a function of CA. Further, the gain of the loop filter can be
adjusted by changing the integrator input resistor RIA.

Voltage Divider
The input range to the VCOIN input is from 1.3V + VEE to
2.6V + VEE; hence, the output from the augmenting amplifier
section must be attenuated to meet the VCOIN constraints. A
simple voltage divider network provides the necessary
attenuation (Figure 8).

The gain constant is defined as:
RA
KI=AI* RIA

eqt. 7

eqt.5
AV

VIN

where:
AI =

op-amp gain constant for selected pole positions.

RA = integrator feedback resistor.

RIA = integrator input resistor.
The integrator circuit introduces a zero, a pole at the origin,
and a second order pole set as described by the two pole
model for an op-amp. As in the case of the differential
summing amplifier, we assume the op-amp pole pair occur as

EClinPS and EClinPS lite
DL140- Rev 4

o-----V'vv-_..----_..----o
Vo

Figure 8. Voltage Divider Subsection

2-87

MOTOROLA

MC10E197
In addition, a shunt filter capacitor connected between the
VCOIN input pin and VEE provides the voltage divider
subsection with a single time constant transfer function that
adds a pole to the overall loop filter. The transfer function for
the voltage divider network is:

The pole for the voltage divider network should be positioned
an octave beyond that for the filter input.

Determination of Element Values
Once the pole location and the gain constant Kd are
established the resistor values for the voltage divider network
are determined using the design guidelines mentioned above
and from the following relationship:

The gain constant,

I Ro and:

where f is the RDCLK frequency in MHz.

Example for an 11 Mbitlsec Data Rate
As an example of scaling, assume the given filter and a 2:7
code are used but the data rate is 11 Mbitlsec. The dynamic
pole positions, and therefore the bandwidth of the loop filter,
are a function of the data rate. Thus a slower data rate will
force the dynamic poles and the bandwidth to move to a lower
frequency. From Equation 11 the value of CIN is:
CIN = 581pF
and from Equation 12 the value of Cd is:
Cd =205pF
Thus the element values for the filter are:
Filter Input Subsection:
CIN =581pF
R1 = 1kO
Integrator Subsection:
CA=0.1JlF

are fulfilled. The pole position P2 is determined from the root
locus analysis to be:

RA = 5.11kO

P2 = - 3.0BMHz
Hence, Rv is selected to be:

RIA = 5.11kO
Voltage Divider Subsection:

Rv =2.15kO

Cd = 205pF

and Ro is calculated to be:

Rv = 2.15k.Q
Ro =700k.Q

Ro=7000

MOTOROLA

2-90

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E197
Note, the poles P1 and P2 are now located at:
P1 =-274kHz
P2 = -1.47MHz

And, the open loop filter unity crossover point is at 300kHz.
The gain can be adjusted by changing the value of RIA and the
value of Cd. Varying the gain by changing Cd is not
recommended because this will also move the poles, hence
affect the dynamic 2 performance of the filter.

Calculations For a 1:7 Coding Scheme
Introduction

Dynamic Zero

The circuit component values are calculated for a 1:7
coding scheme employing a data rate of 20MbiVsec. Since the
number of bits increases from two to three when the data is
encoded, the data clock is at two-thirds the frequency of the
RDCLK signal. Thus, the operating frequency for these
calculations is 30M Hz. As in the case of the 2:7 coding
scheme the pole and zero positions are a function of the data
rate, hence the component values derived by these
calculations must be scaled if a different operating frequency
is used.
Again, the analysis is divided into three parts: static pole
positioning, dynamic pole positioning, and dynamic zero
positioning.

Finally, the zero is positioned much less than one decade
before the crossover frequency; for this design the zero is
placed at:
z=-311Hz
Once the dynamic pole and zero positions have been
determined, the phase margin is determined using a Bode
plot; if the phase margin is not sufficient, the dynamic poles
may be moved to improve the phase margin. Finally, a root
locus analysis is performed to obtain the optimum closed loop
pole positions for the dynamic characteristics of interest.

Component Values
Having determined the closed loop pole and zero positions
the component values are calculated. From the root locus
analysis the dynamic pole and zero positions are:

Static Poles
As in the 2:7 coding example, an MC34182D op-amp is
employed, hence the pole set is:

P1 = - 541kHz
P2 = - 2.73MHz

P1 a = - 5.65 + j5.65MHz

z=-311Hz

P1 b = - 5.65 - j5.65MHz
and the open loop gain is:

Filter Input Subsection
Rearranging Equation 4

___
1_
IN -2" R1ip1i

Since the op-amps introduce a set of complex conjugate
poles, a total of four poles are introduced by the op-amp. In
addition, the integrator and the VCO each contribute a pole at
the origin for a total of six static poles.

Dynamic Poles

and substituting 541 kHz for the pole position and 1.0kn for
the resistor value yields:
CIN = 294 pF

Augmenting Integrator Subsection

The filter input and the voltage divider sections each
contribute a dynamic pole. As stated previously, the filter input
pole should be positioned midway between the unity
crossover point and the phase detector sampling frequency.
Hence, the open loop filter input pole position is selected as:

Rearranging Equation 6
1
RA=21t IzicA

P*1 =-1.1MHz

and substituting 311Hz for the zero position and O.1I1F for the
capacitor value yields:

The voltage divider pole is set approximately one octave
higher than the filter input pole. Thus, the open loop voltage
divider pole position is selected as:

From Equation 7 the value for the other resistors associated
with the integrator op-amp are set equal to RA:

P*2 = - 2.28MHz

RIA = RA= 5.11kn

ECLinPS and ECLinPS Lite
DL140-Rev4

RA=5.11kQ

2-91

MOTOROLA

MC10E197
Voltage Divider Subsection

Finally, using Equation 8a:

The element values for the voltage divider network are
calculated using the relationships presented in Equations 8,
9, and 10 with the constraint that this divider network must
produce a voltage that lies within the range 1.3V + VEE to 2.6V
+ VEE·
Restating Equation 9,

1
Rv Kd

eqt. 8a

the capacitor value, Cd is calculated to be:
Cd = 156pF
Again, note the voltage divider section can be used to set the
gain, butthe designer is cautioned to be sure the input value to
VCOIN is within the correct range.

From the root locus analysis Kol is determined to be:
Kol = 1.258 e51--V- MA
SEC3
From Equation 3:

Component Scaling
As mentioned, these design equations were developed for
a data rate of 20Mbitlsec. If the data rate is different from the
nominal design value the reactive elements must be scaled
accordingly. The following equations provided are to facilitate
scaling and were derived with the assumptions that a 1:7
coding scheme is used and that the RDCLK signal is twice the
frequency of the data clock:
30

(pF)

eqt. 13

Cd=156*~

(pF)

eqt.14

CIN =294
and the gain constant K1:

K1 = 8.42 e21 mA sec

where f is the RDGLK frequency in MHz.
From Equation 5:

Example for an 10 Mbitlsec Data Rate

and the gain constant KI is:

KI = 2.48 e15-v

As an example of scaling, assume the given filter and a 1:7
code are used but the data rate is 10Mbitlsec. The dynamic
pole pOSitions and, therefore, the bandwidth of the loop filter,
are a function of the data rate. Thus, a slower data rate will
force the dynamic poles and the bandwidth to move to a lower
frequency. From Equation 13 the value of GIN is:
GIN = 588pF

Kd = 2.98 e6 sec-1
Having determined the gain constant Kd , the value of Rv, is
selected such that the constraints Rv > Ro and:

~-~
21tlp21

and from Equation 14 the value of Gd is:
Cd=312pF
Thus, the element values for the filter are:
Filter Input Subsection:

Ro+Rv

CIN = 588pF

are fulfilled. The pole position P2 is determined from the root
locus analysis to be:

R1 = 1.0kn

P2 = - 2.73MHz
Hence, Rv is selected to be:

Integrator Subsection:

Rv = 2.15kn

GA= 0.111F

and Ro is calculated to be:

RA = 5.11kn

Ro=453n

MOTOROLA

RIA = 5.11 kn

2-92

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E197
P1 =-271kHz

Voltage Divider Subsection:

P2 = -1.36MHz
Cd=312pF
Rv = 2.15kQ
Ro=453kQ
Note, the poles P1 and P2 are now located at:

ECLinPS and ECLinPS Lite
DL140-Rev4

And, the open loop filter unity crossover point is at 300kHz.
As in the case of the 2:7 coding scheme, the gain can be
adjusted by changing the value of RIA and the value of Cd.
Varying the gain by changing Cd is not recommended
because this will also move the poles, hence affect the
dynamic performance of the filter.

2-93

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low Voltage Dual 1 :4, 1:5
Differential Fanout Buffer

MC100E210

ECL/PECL Compatible

For information on the MC100E210
please refer to the MC100LVE210
datasheet on page 4-7 in
Chapter 4 of this book.

LOW VOLTAGE
DUAL 1 :4, 1:5 DIFFERENTIAL
FANOUT BUFFER

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

MOTOROLA

2-94

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

1:6 Differential Clock
Distribution Chip

MC10E211
MC100E211

The MC10E/100E211 is a low skew 1:6 fanout device designed
explicitly for low skew clock distribution applications. The device can be
driven by either a differential or single-ended ECl or, if positive power
supplies are used, PECl input signal (PECl is an acronym for Positive
ECl, PECl levels are ECl levels referenced to +5V rather than ground).
If a single-ended input is to be used the VBB pin should be connected to
the ClK input and bypassed to ground via a 0.01 ~F capacitor. The VBB
supply is designed to act as the switching reference for the input of the
E211 under single-ended input conditions, as a result this pin can only
source/sink up to 0.5mA of current.

1:6 DIFFERENTIAL
CLOCK DISTRIBUTION CHIP

• Guaranteed low Skew Specification
• Synchronous Enabling/Disabling
• Multiplexed Clock Inputs
• VBB Output for Single-Ended Use
• Internal 75kO Input Pulldown Resistors
• Common and Individual Enable/Disable Control
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

• High Bandwidth Output Transistors
• Extended 100E VEE Range of -4.2V to -5.46V
The E211 features a multiplexed clock input to allow for the distribution
of a lower speed scan or test clock along with the high speed system
clock. When lOW (or left open in which case it will be pulled LOW by the
input pulldown resistor) the SEl pin will select the differential clock input.

Both a common enable and individual output enables are provided. When asserted the positive output will go lOW on the next
negative transition of the ClK (or SClK) input. The enabling function is synchronous so that the outputs will only be
enabled/disabled when the outputs are already in the lOW state. In this way the problem of runt pulse generation during the
disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all
associated specifications are referenced to the negative edge of the ClK input.
The output transitions of the E211 are faster than the standard ECLinPSTM edge rates. This feature provides a means of
distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits
guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the
recommended termination schemes please refer to the applications information section of this data sheet.
FUNCTION TABLE
ClK

SClK

SEl

H/l
X

X
l
H/l
H
z·
Z"
X
..
• Z = NegatIVe transition of ClK or SClK

ENx

l
l
H

ClK
SClK
l

ECLinPS is a trademark of Motorola Inc.
5/95

2-95

REV 3

MOTOROLA

CLK

01-4

CLK

01-4

SCLK
SEL
EN1-4
CEN

Q5
ENS

VBB _ ..
__- - - -

Logic Diagram

MOTOROLA

2-96

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E211 MC100E211
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea =GND)
D'C

Characteristic
Output Reference Voltage
10E
lODE

Symbol

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

Max

-1.38
-1.38

Input High Current

IIH

Power Supply Current
10E
lODE

lEE

Unit

Condition

VBB
-1.27
-1.26

-1.35
-1.38

-1.25
-1.26

150

-1.31
-1.38

-1.19
-1.26
150

150

I1A
mA

119
119

160
160

119
119

160
160

119
137

160
164

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
D'C
Characteristic
Propagation Delay to Output
ClK to 0 (Dilf)
ClKtoO(SE)
SClKtoO
SEl toO

tplH
tpHl

Disable TIme
ClK or SClK to 0

IpHl

Part-Io-Part Skew
ClK (Dilf) 10 0
ClK (SE), SClK 10 0
Within-Device Skew

tskew

Hold TIme
ClK 10 ENx, CEN

Com. Mode Range (ClK)
Rise/Fall TImes
20-80%

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

Condition

ps
795
745
650
745

930
930
900
970

1065
1115
1085
1195

600

800

805
755
650
755

940
940
910
980

1075
1125
1095
1205

600

800

825
775
650
775

960
960
930
1000

1095
1145
1115
1225

600

800

ps
2
ps

Setup TIme
ENxtoClK
CEN toClK

Minimum Inpul Swing (ClK)

1.
2.
3.
4.

Symbol

270
370
75

1
ps

200
200

-100
0

200
200

-100
0

200
200

-100
0

2
ps

900

600

900

160

900

600

Vpp

0.25

1.0

0.25

1.0

0.25

1.0

VCMR

--{).4

Nole

-0.4

Nole

--{).4

Nole

tr
If

150
400
150
150
400
400
..
..
Wllhln-Devlce skew IS defined for Identical transitions on similar paths through a device.
Setup, Hold and Disable times are all relative to a falling edge on ClK or SClK.
Minimum input swing for which AC parameters are guaranteed. Full DC ECl output swings will be generated with only 50mV input swings.
The range in which Ihe high level of the input swing must fall while meeting the Vpp spec. The lower end of the range is VEE dependent and
can be calculaled as VEE + 2.4V.

ECLinPS and ECLinPS Lite
Dl140-Rev4

2-97

MOTOROLA

MC10E211 MC100E211
APPLICATIONS INFORMATION
General Description
The Me1 OEl1 00E211 is a 1:6 fanout tree designed
explicitly for low skew high speed clock distribution. The
device was targeted to work in conjunction with the E111
device to provide another level of flexibility in the design and
implementation of clock distribution trees. The individual
synchronous enable controls and multiplexed clock Inputs
make the device ideal as the first level distribution unit in a
distribution tree. The device provides the ability to distribute a
lower speed scan or test clock along with the high speed
system clock to ease the design of system diagnostics and
self test procedures. The individual enables could be used to
allow for the disabling of individual cards on a backplane in
fault tolerant designs.
Because of lower fanout and larger skews the E211 will
not likely be used as an alternative to the E111 for the bulk of
the clock fanout generation. Figure 1 shows a typical
application combining the two devices to take advantage of
the strengths of each.

r---------,
I
I
I

E211

Figure 1. Standard E211 Application

Using the E211 in PEel Designs
The E211 device can be utilized very effectively in designs
utilizing only a +SV power supply. Since the internal switching
reference levels are biased off of the Vce supply the input
thresholds for the single-ended inputs will vary with Vcc. As a
result the single-ended inputs should be driven by a device
on the same board as the E211. Driving these inputs across a
backplane where significant differences between the Vce's of
the transmitter and receiver can occur can lead to AC
performance and/or significant noise margin degradations.
Because the differential 1/0 does not use a switching
reference, and due to the CMR range of the E211, even

MOTOROLA

under worst case VCC situations between cards there will be
no AC performance or noise margin loss for the differential
ClK inputs.
For situations where TTL clocks are required the E211 can
be interfaced with the H641 or H643 ECl to TTL Clock
Distribution Chips from Motorola. The H641 is a single supply
1:9 PECl to TTL device while the H643 is a 1:8 dual supply
standard ECl to TTL device. By combining the superior skew
performance of the E211, or E111, with the low skew
translating capabilities of the H641 and H643 very low skew
TTL clock distribution networks can be realized.
Handling Open Inputs and Outputs
All of the input pins of the E211 have a SOkf.l to 7Skn
pulldown resistor to pull the input to VEE when left open. This
feature can cause a problem if the differential clock inputs are
left open as the input gate current source transistor will
become saturated. Under these conditions the outputs of the
ClK input buffer will go to an undefined state. It is
recommended, if possible,that the SClK input should be
selected any time the differential ClK inputs are allowed to
float. The SClK buffer, under open input conditions, will
maintain a defined output state and thus the 0 outputs of the
device will be in a defined state (0 lOW). Note that if all of
the inputs are left open the differential ClK input will be
selected and the state of the 0 outputs will be undefined.

With the simultaneous switching characteristics and the
tight skew speCifications of the E211 the handling of the
unused outputs becomes critical. To minimize the noise
generated on the die all outputs should be terminated in
pairs, ie. both the true and compliment outputs should be
terminated even if only one of the outputs will be used in the
system. With both complimentary pairs terminated the
current in the VCC pins will remain essentially constant and
thus inductance induced voltage glitches on VCC will not
occur. VCC glitches will result in distorted output waveforms
and degradations in the skew performance of the device.
The package parasitics of the 28-lead PlCC cause the
signals on a given pin to be influenced by signals on adjacent
pins. The E211 is characterized and tested with all of the
outputs switching, therefore the numbers in the data book are
guaranteed only for this situation. If all of the outputs of the
E211 are not needed and there is a desire to save power the
unused output pairs can be left unterminated. Unterminated
outputs can influence the propagation delay on adjacent pins
by 1Sps - 20ps. Therefore under these conditions this 1Sps 20ps needs to be added to the overall skew of the device.
Pins which are separated by a package corner are not
considered adjacent pins in the context of propagation delay
influence. Therefore as long as all of the outputs on a single
side of the package are terminated the specification limits in
the data sheet will apply.

2-98

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E211 MC100E211
APPLICATIONS INFORMATION
Differential versus Single-Ended Use
As can be seen from the data sheet, to minimize the skew
of the E211 the device must be used in the differential mode.
In the single-ended mode the propagation delays are
dependent on the relative position of the VSB switching
reference. Any VBB offset from the center of the input swing
will add delay to either the TplH or TpHl and subtract delay
from the other. This increase and decrease in delay will lead
to an increase in the duty cycle skew and thus part-to-part
skew. The within-device skew will be independent of the VBB
and therefore will be the same regardless of whether the
device is driven differentially or single-endedly.

pulse. On initial power up the enable flip flops will randomly
attain a stable state, therefore precautions should be taken
on initial power up to ensure the E211 is in the desired state.

For applications where part-to-part skew or duty cycle
skew are not important the advantages of single-ended clock
distribution may lead to its use. Using single-ended
interconnect will reduce the number of signal traces to be
routed, but remember that all of the complimentary outputs
still need to be terminated therefore there will be no reduction
in the termination components required. To use the E211 with
a single-ended input the arrangement pictured in Figure 2b
should be used. If the input to the differential ClK inputs are
AC coupled as pictured in Figure 2a the dependence on a
centered VBS reference is removed. The situation pictured
will ensure that the input is centered around the bias set by
the VSS. As a result when AC coupled the AC specification
limits for a differential input can be used. For more
information on AC coupling please refer to the interfacing
section of the deSign guide in the ECLinPS data book.

VBB

Figure 2a. AC Coupled Input

~}-----.,
iNO---r----I

Using the Enable Pins
Both the common enable (CEN) and the individual
enables (ENx) are synchronous to the ClK or SClK input
depending on which is selected. The active low signals are
clocked into the enable flip flops on the negative edges of the
E211 clock inputs. In this way the devices will only be
disabled when the outputs are already in the lOW state. The
internal propagation delays are such that the delay to the
output through the distribution buffers is less than that
through the enable flip flops. This will ensure that the
disabling of the device will not slice any time off the clock

ECLinPS and ECLinPS Lite
DL140-Rev4

O.OIJlF

~
VBB

Figure 2b. Single-Ended Input

2-99

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

3·Bit Scannable Registered
Address Driver

MC10E212
MC100E212

The MC1 OEl1 OOE212 is a scannable registered ECL driver typically
used as a fan-out memory address driver for ECL cache driving. In a VLSI
array based CPU design, use of the E212 allows the user to conserve
array output cell functionality and also output pins.
The input shift register is designed with control logic which greatly
facilitates its use in boundary scan applications.

3-BIT SCANNABLE
REGISTERED
ADDRESS DRIVER

• Scannable Version E112 Driver
• 1025ps Max. CLK to Output
• Dual Differential Outputs
• Master Reset
• Extended 100E VEE Range of - 4.2V to - 5.46V
• Internal75kn Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)
SHIFT MR

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

NC S-OUTVCCO 02b 02a

LOAD

02b

CLK

02a

VCC

VEE

01 b

LOGIC DIAGRAM

02b
02a

01 a
01 b

S-OUT

02a
02b

01 a

NC Veeo OOa QOb OOa a(jii VCCO
• All VCC and VCCO pins are tied together on the die.

PIN NAMES

Pin
DO-D2
S-IN
lOAD
SHIFT
ClK
MR
S-OUT
Q[O:2]a, Q[O:2]b
O[0:2]a,O[0:2]b

Function
Data Inputs
Scan Input
lOAD/HOLD Control
Scan Control
Clock
Reset
Scan Output
True Outputs
Inverting Outputs

Oob
Ooa
DO
S-IN ---t----'
LOAD - - - - - '
SHIFT - - - - - - - - '
CLK - - - - - - - - - '
MR----------------'

12193

2-100

REV 2

MOTOROLA

MC10E212 MC100E212
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea = GND)
Q'C

Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

min

typ

25'C
max

min

150

min

typ

150
80
80

96
96

max

Unit

150

J.lA

Condition

Characteristic

min

typ

tpLH
tpHL

Propagation Delay to Output
CLK
MR
CLKtoS-OUT

575
575
575

800
800
800

Setup TIme
D
SHIFT
LOAD
S-IN

175
150
225
150

25
-50

Hold TIme
D
SHIFT
LOAD
S-IN

80
92

96
96

96
110

=Veea =GND)

Q'C

85'C
max

rnA
80
80

AC CHARACTERISTICS (VEE =VEE(min) to VEE(max); Vee

Symbol

typ

25'C
max

min

typ

85'C
max

min

typ

max

Unit

Condition

ps
575
575
575

800
800
800
25
-50

50
-50

175
150
225
150

250
300
225
300

25
100
0
100

250
300
225
300

25
100

600

350

600

1025
1025
1025

575
575
575

800
800
800

175
150
225
150

25
-50

0
100

250
300
225
300

25
100
0
100

350

600

1025
1025
1025
ps

50
-50

50
-50
ps

tRR

Reset Recovery

350

tSKEW

Within-Device Skew

100

tSKEW

Within-Gate Skew

ps
Rise/Fall TImes
tr
20 -80%
275
425
275
425
650
650
425
650
275
tf
.
.
..
..
1. Within-device skew IS defined as Identical transitions on similar paths through a deVice.
2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input.

FUNCTION TABLE
LOAD

SHIFT

MODE

L
H

L
L
H

L
L
L
H

Load
Hold
Shift
Reset

X
X

ECLinPS and ECLinPS Lite
DL140-Rev4

2-101

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

a-Bit Scannable Register

MC10E241
MC100E241

The MC10El100E241 is an 8-bit shiftable register. Unlike a standard
universal shift register such as the E141, the E241 features internal data
feedback organized so that the SHIFT control overrides the HOLD/LOAD
control. This enables the normal operations of HOLD and LOAD to be
toggled with a single control line without the need for external gating. It
also enables switching to scan mode with the single SHIFT control line.
The eight inputs DO - 07 accept parallel input data, while S-IN accepts
serial input data when in shift mode. Data is accepted a set-up time
before the positive-going edge of CLK; shifting is also accomplished on
the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.

8-BIT SCANNABLE
REGISTER

• SHIFT overrides HOLD/LOAD Control
• 1000ps Max. CLK to Q
• Asynchronous Master Reset
• Pin-Compatible with E141
• Extended 1OOE VEE Range of - 4.2V to - 5.46V
• 75kn Input Pulldown Resistors
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

Pinout: 28-Lead PLCC (Top View)
SElO

veeo

06
05
LOGIC DIAGRAM

Vee
Ne

S-IN

Veeo
04

00
00

Veco

I
I

01- 06

I
I
I

01- 06

• All VCC and VCCO pins are tied together on the die.

...I

PIN NAMES
Pin

00- 0 7
S-IN
SElO
SEll
ClK
MR
00- 0 7

Function

Parallel Date Inputs
Serial Data Inputs
SHIFT Control
HOlDILOAD Control
Clock
Master Reset
Data Outputs

HOlOIlOAO - - - - - '

SHIFT - - - - - - - - '
elK--------~

MR---------------'

7/96

2-102

REV 3

MOTOROI.A

MC10E241 MC100E241
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
25°C

O°C
Characteristic

Symbol
I'H

Input HIGH Current

lEE

Power Supply Current
10E
100E

min

typ

max

min

typ

85°C
max

min

typ

150

max

Unit

150

IlA

Condition

MA
125
125

125
125

150
150

125
144

150
173

AC CHARACTERISTICS (VEE = VEE (min) to VEE(max); Vee = Veea = GND)
O°C
Symbol

Characteristic

min

typ

25°C
max

min

typ

700

900

625
600

750
725
25

85°C
max

min

typ

700

900

625
600

750
725
25
200
250
-100

ISHIFT

Max. Shift Frequency

700

900

tpLH
tpHL

Propagation Delay to Output
Clk
MR

625
600

750
725

Setup Time
D
SELO (SHIFT)
SELl (HOLD/LOAD)
S-IN

175
350
400
125

25
200
250
-100

175
350
400
125

200
250
-100

175
350
400
125

Hold Time
D
SELO (SHIFT)
SELl (HOLD/LOAD)
S-IN

200
100
50
300

-25
-200
-250
100

200
100
50
300

-25
-200
-250
100

200
100
50
300

-25
-200
-250
100

tRR

Reset Recovery Time

900

600

900

600

900

600

tpw

Minimum Pulse Width
Clk, MR

400

tSKEW

max

Unit

Condition

MHz
ps

975
975

975
975
ps

ps
ps

Within-Device Skew

400

400
60

Rise/Fall Times
tr
20-80%
300
525
BOO
300
525
800
tl
..
..
. .
1. Within-device skew IS defined as Identical transitions on similar paths through a deVice.

ps
300

525

800

FUNCTION TABLE
MR

SELO

SELl

a
a
a

X
X

a
a

ECLinPS and ECLinPS Lite
DL140-Rev4

Function
Outputs LOW
Shift Data
Hold Data
Load Data

2-103

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

3·Bit 4: 1 Mux·Latch

MC10E256
MC100E256

The MC10El100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls are
provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic HIGH
on LEN latches the outputs. The Master Reset (MR) overrides all other
controls to set the Q outputs LOW.

3-BIT 4:1
MUX-LATCH

• 950ps Max. D to Output
• 850ps Max. LEN to Output
• Split Select
• Differential Outputs
• Extended 1OOE VEE Range of - 4.2V to - 5.46V
• 75kn Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)
Dlb

Dla

D2d

D2c

D2b

D2a Veea

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

SEL1A

SEL2

Vee

VEE

Veea

Old

DOa

DOb

DOc

DOd Veeo

• All VCC and VCCO pins are tied together on the die.

FUNCTION TABLE
Pin
SEL2
SELIA
SELIB

State
H
H
H

PIN NAMES
. Operation
Output c/d Data
Inputd Data
Inputb Data

Function

DOx -D2x
SELIA, SELIB
SEL2
LEN
MR
00, 00 - 02, 02

12193

2-104

REV2

Data Inputs
First-stage Select Inputs
Second-stage Select input
Latch Enable
Master Reset
Data Outputs

MOTOROL.A

MC10E256 MC100E256

LOGIC DIAGRAM
DOa
DOb
00

DOc
DOd
D1a
D1b

D1c
D1d
D2a
D2b

[2J

D2c
D2d
SEL1A
SEL18
SEL2
LEN

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)

25'C

D'C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

ECLinPS and ECLinPS Lite
DL140-Rev4

min

typ

max

min

typ

85'C
max

min

typ

150

max

Unit

150

I1A

Condition

rnA

69
69

83
83

2-105

69
69

83
83

69
79

83
96

MOTOROLA

MC10E256 MC100E256
AC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea =GND)
D'C

Symbol

Characteristic

min

typ

Propagalion Delay 10 OulpUI
D
SEL1
SEL2
LEN
MR

550
450
350
350

600
775
650
500
600

SelupTime
D
SEL1
SEL2

400
600
500

Hold Time
D
SEL1
SEL2

IRR
IpW

IPLH
IpHL

min

typ

400

typ

600
775
650
500
600

275
300
250

400
600
500

275
300
250

300
100
200

-275
-300
-250

300
100
200

-275
-300
-250

700

600

700

600

400
600
500

300
100
200

-275
-300
-250

Resel Recovery Time

700

600

Minimum Pulse Widlh
MR

400

Rise/Fall Times
20-80%

min

400
550
450
350
350

275
300
250

Within-Device Skew

900
1050
900
800
825

400

600
775
650
500
600

Ir
If

85'C
max

max

Unit

Condition

ps
550
450
350
350

ISKEW

25'C
max

900
1050
900
800
825

900
1050
900
800
825
ps

ps
ps

400
50

275

475

. .

700

275

475

700

275

475

700

1. Wllhln-devlce skew IS defined as IdentlcaltranSillons on similar paths through a deVice .

MOTOROLA

2-106

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview

Low Voltage 2:8 Differential
Fanout Buffer

MC100E310

ECL/PECL Compatible

For information on the MC100E310,
please refer to the MC100LVE310
datasheet on page 4-14 in
Chapter 4 of this book.

LOW VOLTAGE
2:8 DIFFERENTIAL
FANOUT BUFFER

FN SUFFIX
PLASTIC PACKAGE
CASE 776-02

ECLinPS and ECLinPS Lite
DL140-Rev4

2-107

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

3·Bit Registered Bus Transceiver
The MC10E/MC100E336 contains three bus transceivers with both
transmit and receive registers. The bus outputs (BUSO-BUS2) are
specified for driving a 2SQ bus; the receive outputs (00 - 02) are
specified for SOQ. The bus outputs feature a normal HIGH level (VOH) and
a cutoff LOW level - when LOW, the outputs go to -2.0V and the output
emitter-follower is "off', presenting a high impedance to the bus. The bus
outputs also feature edge slow-down capacitors.
• 2SQ Cutoff Bus Outputs
• SOQ Receiver Outputs

MC10E336
MC100E336

3·BIT REGISTERED
BUS TRANSCEIVER

• Transmit and Receive Registers
• lS00ps Max. Clock to Bus
• 1000ps Max. Clock to 0
o Bus Outputs Feature Internal Edge Slow-Down Capacitors

• Additional Package Ground Pins
• Extended 100E VEE Range of - 4.2V to - S.46V
• 7SkQ Input Pulldown Resistors
The Transmit Enable pins (TEN) control whether current data is held in
the transmit register, or new data is loaded from the AlB inputs. A LOW on
both of the Bus Enable inputs (BUSEN), when clocked through the
register, disables the bus outputs to -2.0V.

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

The receiver section clocks bus data into the receive registers, after
gating with the Receive Enable (RXEN) input.
All registers are clocked by a positive transition of CLKl or CLK2 (or
both).

Additionalleadframe grounding is provided through the Ground pins (GND) which should be connected to OV. The GND pins
are not electrically connected to the chip.
LOGIC DIAGRAM
Pinout: 28-Lead PLCC (Top View)
TEN2 TEN1

Vcco

BUSEN1

GND

BUSEN2

BUS2

RXEN

VCC

VEE

CLK1

Vcco

CLK2

BUS1

GND

A2
B2

BUS2
Q2

TEN1
TEN2
BO

Vcco BUSO GND

• All VCC and Vcca pins are tied together on the die.

RXEN
BUSEN1
BUSEN2
CLK1
CLK2

12/93

2-108

REV 2

MOTOROLA

MC10E336 MC100E336
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea =GND)
QOC

Symbol

Characteristic

min

VCUT

Cui-off Oulpul Vollage 1

-2.10

IIH

Inpul HIGH Currenl
RXEN
All Olher Inpuls

lEE

typ

25°C
max

min

-2.03

-2.10

85°C

typ

max

min

-2.03

-2.10

typ

max

Unit

-2.03

Condition

!1A
225
150

Power Supply Current
10E
100E

225
150

225
150
rnA

125
125

150
150

125
144

150
173

1. Measured with VTT = - 2.10V

AC CHARACTERISTICS (VEE

=VEE (min) to VEE(max); Vee =Veea =GND)
QOC

Symbol
IpLH
IpHL
Is

IpW
Ir
tf

Characteristic
Propagation Delay 10 OulpUI
ClkloO
Clklo BUS
Seluplime
BUS,RXEN
BUSEN
A, BOaia
TEN
Hold lime
BUS, RXEN
BUSEN
A, BOaia
TEN
Minimum Pulse Width
Clk
Rise/Falilimes
20-80% (On)
20 - 80% (BUSn Rise)
20 - 80% (BUSn Fall)

ECLinPS and ECLinPS Lile
0L140-Rev4

min

typ

85°C

25°C
max

min

typ

max

min

typ

max

Unit

Condition

ps
500
825

700
1250

150
100
300
450

-150
-200
-50

450
500
350
200

150
200

100
1800

500
825

700
1250

150
100
300
450

-150
-200
-50

450
500
350
200

1000
1800

500
825

700
1250
-150
-200
-50

150

150
100
300
450

150
200
50
-150

450
500
350
200

150
200
50
-150

1000
1800
ps

150

150
ps

50
-150

ps
400

400

400
ps

300
500
300

450
800
500

700
1000
800

2-109

300
500
300

450
800
500

700
1000
800

300
500
300

450
800
500

700
1000
800

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

3·Bit Scannable Registered
Bus Transceiver
The MC10El100E337 is a 3-bit registered bus transceiver with scan.
The bus outputs (BUSO-BUS2) are specified for driving a 250 bus; the
receive outputs (00 - 02) are specified for 500. The bus outputs feature
a normal HIGH level (VOH) and a cutoff LOW level - when LOW, the
outputs go to - 2.0V and the output emitter-follower is "off", presenting a
high impedance to the bus. The bus outputs also feature edge slow-down
capacitors.

MC10E337
MC100E337

3-BIT SCANNABLE
REGISTERED
BUS TRANSCEIVER

• Scannable Version of E336
• 250 Cutoff Bus Outputs
• 500 Receiver Outputs
• Scannable Registers
• Sync. and Async. Bus Enables
• Non-inverting Data Path
• 1500ps Max. Clock to Bus (Data Transmit)
• 1000ps Max. Clock to 0 (Data Receive)
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

• Bus Outputs Feature Internal Edge Slow-Down Capacitors
• Additional Package Ground Pins
• Extended 1OOE VEE Range of - 4.2V to - 5.46V
• 75kO Input Pulldown Resistors

Both drive and receive sides feature the same logic, including a loopback path to hold data. The HOLD/LOAD function is
controlled by Transmit Enable (TEN) and Receive Enable (REN) on the transmit and receive sides respectively, with a HIGH
selecting LOAD. Note that the implementation of the E337 Receive Enable differs from that of the E336.
A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS)
disables the bus immediately for scan mode.
The SYNCEN input is provided for flexibility when re-enabling the bus after disabling with ABUSDIS, allowing either
synchronous or asynchronous re-enabling. An alternative use is asynchronous-only operation with ABUSDIS, in which case
SYNC EN is tied LOW, or left open. SYNCEN is implemented as an overriding SET control (active-LOW) to the enable flip-flop.
Scan mode is selected by a HIGH at the SCAN input. Scan input data is shifted in through S_IN and output data appears at the
02 output.
All registers are clocked on the positive transition of CLK. Additional lead-frame grounding is provided through the Ground pins
(GND) which should be connected to OV. The GND pins are not electrically connected to the chip.
PIN NAMES
Pin
AO-A2
BO-B2
S-IN
TEN,REN
SCAN
ABUSDIS
SBUSEN
SYNCEN
ClK
BUSO-BUS2
00- 0 2

Function
Data Inputs A
Data Inputs B
Serial (Scan) Data Input
HOlDILOAD Controls
Scan Control
Asynchronous Bus Disable
Synchronous Bus Enable
Synchronous Enable Control
Clock
25n Cutoff Bus Outputs
Receive Data Outputs (02 serves as SCAN_OUT in scan mode)

12/93

2-110

REV2

MOTOROI.A

MC10E337 MC100E337

Pinout: 28-Lead PLCC (Top View)
S8USEN SYNCEN 80

A8USDIS Vcca 00

SCAN

GND

S-IN

BUSO

TEN

Vcc

REN

Vcca

ClK

BUS1

• All VCC and VCCO pins are tied together on the die_

LOGIC DIAGRAM

,..--------c BUS2

,..--t---t---------

-1/<>--

RS=ZO

-1/<>-IN

--r-.:,...-.....+-.........::---

1~-I-WIr--e...=J-I

RAMBus Load

Oa
04

05
-1/<>--

Os
06

- ........,...--06
07
-1/<>---

'--1--1""--- 08
VBB---

MOTOROLA

0.....;.......,.-06
VOH and VOL levels
will vary slightly from
specification table

2-116

Vee- 2.4V

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E411
ECl DC CHARACTERISTICS
D'C

25'C

85'C
Max

Unll

VOH

Output HIGH Voltage 1

-1.020

-0.840

-0.980

-0.890

-0.810

-0.910

-0.720

VOL

Output LOW Voltage 1

-2.420

-2.140

-2.380

-2.250

-2.110

-2.310

-2.020

VIH

Input HIGH Voltage

-1.170

-0.840

-1.130

-0.810

-1.060

-0.720

VIL

Input LOW Voltage

-1.950

-1.480

-1.950

-1.480

-1.950

-1.445

VSB

Output Reference Voltage

-1.38

-1.27

-1.35

-1.25

-1.31

-1.19

VEE

Power Supply Voltage

-4.5

-5.5

-4.5

-5.5

-4.5

-5.5

IIH

Input HIGH Current

150

jJA

lEE

Power Supply Current

rnA

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

150
55

Typ

150

1. Measured with 300n to VEE output pulldown.

PECl DC CHARACTERISTICS
O'C
Symbol

Characteristic

Min

Typ

25'C

85'C

Max

Min

Typ

Max

Min

Max

Unit

VOH

Output HIGH Voltage 1,2

3.98

4.16

4.02

4.11

4.19

4.09

4.28

VOL

Output LOW Voltage 1,2

2.58

2.86

2.62

2.75

2.89

2.69

2.98

VIH

Input HIGH Voltage 1

3.83

4.16

3.87

4.19

3.94

4.28

VIL

Input LOW Voltage 1

3.05

3.52

3.05

3.52

3.05

3.56

VSB

Output Reference Voltage1

3.62

3.73

3.65

3.75

3.69

3.81

VCC

Power Supply Voltage

4.5

5.5

4.5

5.5

4.5

5.5

IIH

Input HIGH Current

150

jJA

lEE

Power Supply Current

rnA

150
55

Typ

150
55

1. These values are for VCC 5.0V. Level Specifications will vary 1:1 with VCC.
2. Measured with 300n to VEE output pulldown.

ECLinPS and ECLinPS Lite
DL140-Rev4

2-117

MOTOROLA

MC10E411
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); Vee = Veca = GND)
D'C
Symbol
tplH
tpHl

Characteristic
Propagation Delay to Output
IN (differential)
IN (single-ended)
ENtoQ

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

Condition

ps
400
350
450

600
650
850

430
380
450

630
680
850

500
450
450

700
750
850

Note 1.
Note 2.

Setup TIme

EN to IN

200

Note 3.

Hold TIme

INtoEN

-200

Note 4.

Release TIme

ENtolN

300

100

300

100

300

100

Note 5.

NoteS.

Note 7.

tskew

Within-Device Skew
Part-to-Part Skew (Diff)

50
200

50
200
250

50
200

Vpp

Minimum Input Swing

250

VCMR

Common Mode Range

-1.6

-0.4

-1.6

-0.4

-1.6

250
-0.4

Note 8.

trltl

Output Rise/Fall TIme

275

600

275

600

275

600

20%-80%

1. The differential propagation delay is deli ned as the delay Irom the crossing points 01 the differential input signals to the crOSSing point 01 the
differential output signals.

[l]

2. The single-ended propagation delay is defined as the delay lrom the 50% point 01 the input signal to the 50% point 01 the output signal.
3. The setup time is the minimum time that EN must be asserted prior to the next transition 01 IN/IN to prevent an output response greater than
.
±75 mV to that IN/IN transition (see Figure 1).
4. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition (see Figure 2).
5. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times (see Figure 3).
6. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
7. Vpp(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The Vpp(min) is AC limited
lor the E411 as a differential input as low as 50 mV will still produce lull Eel levels at the output.
8. VCMR is defined as the range within which the V,H level may vary, with the device still meeting the propagation delay specification. The ViL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

MOTOROLA

2-118

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quint Differential Line
Receiver

MC10E416
MC100E416

The MC10E416/100E416 is a 5-bit differential line receiving device.
The 2.0GHz of bandwidth provided by the high frequency outputs makes
the device ideal for buffering of very high speed oscillators.
A VBB pin is available to AC couple an input signal to the device. More
information on AC coupling can be found in the design handbook section
of this data book.

QUINT DIFFERENTIAL
LINE RECEIVER

The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
The differential inputs have internal clamp structures which will force
the Q output of a gate in an open input condition to go to a LOW state.
Thus, inputs of unused gates can be left open and will not affect the
operation of the rest of the device. Note that the input clamp will take
affect only if both inputs fall 2.5V below VCC.
o Differential D and Q; VBB available
o

600ps Max. Propagation Delay

• High Frequency Outputs
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

• 2 Stages of Gain
o Extended 100E VEE Range of - 4.2V to - 5.46V

• Internal 75k.Q Input Pulldown Resistors
Pinout: 28-Lead PLCC (Top View)

Veeo

LOGIC DIAGRAM

:~:
00

Veeo

• All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin

Function

0[0:4], 0[0:4]

Differential Data Inputs

Q[0:4],0[0:4]

Differential Data Outputs
VBB 0""'---7/

12193

2-119

REV 2

MOTOROLA

MC1 OE416 MC100E416
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
D'C
Symbol

VBB

Characteristic

min

25'C
max

typ

min

typ

85'C
max

min

typ

max

Output Reference Voltage

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

Vpp(DC)

Input Sensitivity

Condition

V
-1.27
-1.26

-1.38
-1.38

10E
100E

Unit

-1.35
-1.38

-1.25
-1.26

150

-1.31
-1.38

-1.19
-1.26

150

IlA
rnA

135
135

162
162

135
135

162
162

135
155

162
186

Common Mode Range
-1.5
-1.5
-1.5
V
0
0
0
2
VCMR
1. Dlfferenllallnput voltage required to obtain a full ECl sWing on the outputs.
2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signal are within the
VCMR range and the input swing is greater than Vpp MIN and < 1.0V

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
D'C
Symbol
tplH
tpHl

Characteristic

min

typ

25'C
max

min

typ

85'C
max

min

typ

max

Propagation Delay to Output

Within-Device Skew

tSKEW

Duty Cycle Skew
tplH-tPHl

Vpp(AC)

Minimum Input Swing

tr
tf

RiselFalilime
20- 80%

Condition

d(Diff)
D(SE)

tSKEW

Unit

250
200

350
350

500
550

250
200

50
±10

100

500
550

. .

±10

350

100

350
350

500
550

50
±10

150
200

250
200

150

350
350

150
200

350

100

200

350

1. Within-device skew IS defined as IdenllCal transitions on similar paths through a deVice .
2. Duty cycle skew defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of
the outputs.
3. Minimum input swing for which AC parameters are guaranteed.

MOTOROLA

2-120

ECLinPS and ECLinPS Lite
Dl140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

3·Bit Differential Flip-Flop
The MC10Ell00E431 is a 3-bit flip-flop with differential clock, data
input and data output.
The asynchronous Set and Reset controls are edge-triggered rather
than level controlled. This allows the user to rapidly set or reset the
flip-flop and then continue clocking at the next clock edge, without the
necessity of de-asserting the seVreset Signal (as would be the case with a
level controlled seVreset).
The E431 is also designed with larger internal swings, an approach
intended to minimize the time spent crossing the threshold region and
thus reduce the metastability susceptibility window.

MC10E431
MC100E431

3-BIT DIFFERENTIAL
FLIP-FLOP

The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the ClK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
Simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
o Edge-Triggered Asynchronous Set and Reset
o Differential D, ClK and Q; VBB Reference Available

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

o 1100MHz Min. Toggle Frequency
o Extended 1OOE VEE Range of - 4.2V to - 5.46V

Pinout: 28-lead PlCC (Top View)
VBB ClK2 ClK2

S2
LOGIC DIAGRAM

ClK1

So
DO

VCC

ClKO

VEE

a:;-

ClKO

il1

81
D1

il1
ClK1

a:;-

ClK1
ClKO ClKO

VCCO

• All VCC and Vcca pins are tied together on the die.

PIN NAMES
Pin
D[O:2], D[O:2]
CLK[0:2], CLK[0:2]
S[0:2]
R[O:2]
VBB
Q[0:2], Q[0:2]

R1
82

Function
Differential Data Inputs
Differential Clock
Edge Triggered Set Inputs
Edge Triggered Reset Input
VBB Reference Output
Differential Data Outputs

ClK2

2-121

ClK2
R2
VBB

5/95

REV 3

•

MOTOROLA

MC10E431 MC100E431
FUNCTION TABLE

Z
X

ClKn

L
H
X
X

Z
Z
X
X

L
L
Z
L

L
L
L
Z

L
H
L
H

=Low to high transition
=Don't Care

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = Veea = GND)
-40'C
Symbol
VBB

Characteristic

Typ

Input HIGH
Current

lEE

Power Supply
Current
10E
100E

Min

Typ

-1.30
-1.26

Max
"':1.27
-1.26

-1.38
-1.38

150

Common Mode
Range

25'C

O'C
Max

Min

85'C

Typ

Max

Min

Typ

Max

Unit

Cond

Output Reference
Voltage
10E -1.43
100E -1.38

IIH

VCMR

Min

-1.35
-1.38

-1.25
-1.26

-1.31
-1.38

150

-1.19
-1.26

j.lA
mA

110
110
-1.5

132
132

110
110

-1.5

132
132

110
110
0

132
132

-1.5

110
127
0

132
152

-1.5

1. VCMR IS referenced to the most poSItive side olthe differential Input signal. Normal specified operallOn IS obtained when the Input signals are
within the VCMR range and the input swing is greater than Vpp.

AC CHARACTERISTICS (VEE = VEE (min) to VEE(max); Vee = Veea = GND)
-40'C
Symbol

Characteristic

fMAX

Maximum Toggle Frequency

tpLH
tpHL

Propagation Delay to Output

Setup Time

Hold Time

tpw

Minimum Pulse Width

tskew

Within-Device Skew

Vpp

Minimum Input Swing

Min

Typ

1000

1400

CLK(Diff)
CLK(SE)
R
S

410
460
500
500

600
600
725
725

D
R
S

250
1100
1100

0
700
700

250

CLK

400

O'Cto 85'C
Max

790
840
975
975

Min

Typ

1100

1400

450
400
550
550

600
600
725
725

200
1000
1000

0
700
700

200

400
50

150

Unit

Condition

MHz
750
800
925
925

1
1

ps
50

150

Max

Rise/Fall Times
275
450
650
2Q--80%
700
250
450
ps
t"tf
1. These setup times define the minimum time the CLK or SET/RESET input must wait after the assertion of the RESET/SET input to assure the
proper operation of the flip-flop.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. Minimum input swing for which AC parameters are guaranteed.

MOTOROLA

2-122

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

4·Bit Serial/Parallel Converter

MC10E445
MC100E445

The MCl 0/1 00E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both
4-bit conversion and a two chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to 00, the second to
01 etc.
• On-Chip Clock +4 and +8

4-81T SERIAU
PARALLEL CONVERTER

• 2.0Gb/s Data Rate Capability
• Differential Clock and Serial Inputs
• VBB Output for Single-Ended Input Applications
• Asynchronous Data Synchronization
• Mode Select to Expand to 8-Bits
• Internal 75kQ Input Pulldown Resistors
• Extended 100E VEE Range of -4.2V to -5.46V
Two selectable serial inputs provide a loopback capability for testing
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from an to On-l. For each additional
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to "swallow"
a clock pulse, effectively shifting a bit from the an to the On-l output (see
liming Diagram B).

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will
function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle
thus allowing for an 8-bit conversion scheme using two E445's. When cascaded in an 8-bit conversion scheme the devices will
not operate at the 2.0Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on
cascading the E445.
For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates
above SOOMHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential
input and bypassed via a O.D1I!F capacitor. The VBBprovides the switching reference for the input differential amplifier. The VBB
can also be used to AC couple an input Signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPSTM data book.
Upon power-up the internal flip-flops will attain a random state. To synchronize multiple E44S's in a system the master reset
must be asserted.
PIN NAMES

SINA SINA

Pin
SINA.SINA
SINB. SINB
SEL
OD-Q3
CLK,CLK
CU4,CU4
CU8,CU8
MODE
SYNCH

Function

SINB

Differential Serial Data Input A
Differential Serial Data Input B
Serial Input Selector Pin
Parallel Data Outputs
Differential Clock Inputs
Differential +4 Clock Output
Differential +8 Clock Output
Conversion Mode 4-Bit/8-Bit
Conversion Synchronizing Input

w
a: MODE Ne Veeo

CJ)

Conversion

SEL

Serial Input

L
H

4-Bit
8-Bit

H
L

A
B

SOUT

Vee

Pinout: 28-Lead PLCC
(Top View)

elK

veeo

CU8 cue Veeo eU4 eU4 Veeo 03

7196

2-123

19
18

SEl

vBB

Mode

I:i:i

SINB

VEE

FUNCTION TABLES

REV 2

MOTOROLA

MC10E445 MC100E445

LOGIC DIAGRAM

SINB
SINB
SINA

1--------10

01-.._---10

oI -......-il-----I

01-.._-+--1

SINA
SEl---..J

SOUl
SOUl

-t4

CU4

ClK

CU4
ClK

CUB
CUB

MOOE---------~~~--~

RESET-------------'
SYNC-----------..J

MOTOROLA

2-124

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E445 MC100E445
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea = GND)
Q'C

Symbol

Characteristic

Min

Typ

25'C
Max

Min

85'C

Typ

Max

Min

Typ

Max

Unit

150

f.1A

IIH

Input HIGH Current

VOH

Ouput HIGH Current
1OE (SOUT Only)
100E (SOUT Only)

-1020
-1025

-790
-830

-980
-1025

-760
-830

-910
-1025

~70

Output Reference Voltage
10E
100E

-1.38
-1.38

-1.27
-1.26

-1.35
-1.38

-1.25
-1.26

-1.31
-1.38

-1.19
-1.26

VSS

lEE

150

Condition

V
1
1

-830

Power Supply Current
10E
100E

mA
154
154

185'
185

154
154

185
185

154
177

185
212

1. The maximum VOH limit was relaxed from standard ECLdue to the high frequency output design. All other outputs are specified with the standard
1OE and 100E VOH levels.

AC CHARACTERISTICS (VEE

=VEE (min) to VEE(max); Vee =Veea =GND)
O'C

Characteristic

Min

fMAX

Maximum Conversion Frequency

2.0

tpLH
tpHL

Propagation Delay to Output
CLKtoQ
CLKtoSOUT
CLKtoCU4
CLKtoCU8

1500
800
1100
1100

1800
975
1325
1325

Setup Time
SINA, SINS
SEL

-100
0

Hold Time
SINA, SINS, SEL

tRR

Reset Recovery Time

tpw

Minimum Pulse Width
CLK, MR

400

tr
tf

Rise/Fall Times
SOUT
Other

100
200

Symbol

ECLinPS and ECLinPS Lite
DL140- Rev 4

Typ

25'C
Max

Min

Typ

85'C
Max

2.0

Min

Typ

Max

2.0

Unit

Condition

Gb/s
NRZ
ps

2100
1150
1550
1550

1500
800
1100
1100

1800
975
1325
1325

-250
-200

-100
0

450

300

500

300

2100
1150
1550
1550

1500
800
1100
1100

1800
975
1325
1325

-250
-200

-100
0

-250
-200

450

300

450

300

500

300

500

300

2100
1150
1550
1550
ps

ps
ps
ps
400

400
ps

225
425

350
650

100
200

2-125

225
425

350
650

100
200

225
425

20%-80%

350
650

MOTOROLA

MC10E445 MC100E445
TIMING DIAGRAMS

ClK
SIN
RESET

On·4

On-3

On·2

On·l

On+l

On+2

On+3

X
X
X
X

<
<
<
<

00
01
02
03

SOUT

On·3
On·2
On·l

On·4

CU4

CUB

On·3

I
\

X
X
X
X

On·4

On·2

On+2
On+3
On

On·l

On+l

On+2

X
X
X
X

On
On+l

On+3

I
\

Timing Diagram A. 1:4 Serial to Parallel Conversion

[2J
ClK
SIN
RESET

On·4

On·3

On·2

On·l

On+l

On+2

01
02
03

On+4

\
I

SYNC
QO

On+3

<
<
<
<

On-4

X
X
X

On·3

SOUT

CUB

I
\

X
X
X

On·2

On·3

On+2
On+3

On·l
On·4

CU4

\
On+l

On·l

I
I

On+l

On+4
On+2

On+3

On+4

r'-

Timing Diagram B. 1:4 Serial to Parallel Conversion With SYNC Pulse

MOTOROLA

2-126

ECLinPS and ECLinPS Lite
DL140- Rev 4

MC10E445 MC100E445
APPLICATIONS INFORMATION

The MC10El100E445 is an integrated 1:4 serial to parallel
converter. The chip is designed to work with the E446 device
to provide both transmission and receiving of a high speed
serial data path. The E445, can convert up to a 2.0Gb/s NRZ
data stream into 4-bit parallel data. The device also provides
a divide by four clock output to be used to synchronize the
parallel data with the rest of the system.

increased. The delay between the two clocks can be
increased until the minimum delay of clock to serial out would
potentially cause a serial bit to be swallowed (Figure 3).

CLOCK - - - , . - - - - - - - - ,
CLOCK --.-1--------.

The E445 features multiplexed dual serial inputs to
provide test loop capability when used in conjunction with the
E446. Figure 1 illustrates the loop test architecture. The
architecture allows for the electrical testing of the link without
requiring actual transmission over the serial data path
medium. The SINA serial input of the E445 has an extra
buffer delay and thus should be used as the loop back serial
input.

E445b
SERIAL
INPUT
DATA

SIN
SIN

SOUT
SOUT

SIN
SIN

030201 00

07060504

030201 00

PARALLEL OUTPUT DATA
PARALLEL
DATA

SOUT
SOUT I-+--r--I/

TO SERIAL
MEDIUM

-I I- 100ps

----lr--

CLOCK ~

PARALLEL
DATA

SINA
SINA
SINB 1-----,.'1
SINB

I---

The E445 features a differential serial output and a divide
by 8 clock output to facilitate the cascading of two devices to
build a 1:8 demultiplexer. Figure 2 illustrates the architecture
for a 1:8 demultiplexer using two E445's; the timing diagram
for this configuration can be found on the following page.
Notice the serial outputs (SOUT) of the lower order converter
feed the serial inputs of the the higher order device. This feed
through of the serial inputs bounds the upper end of the
frequency of operation. The clock to serial output
propagation delay plus the setup time of the serial input pins
must fit into a single clock period for the cascade architecture
to function properly. USing the worst case values for these
two parameters from the data sheet, TPD CLK to SOUT =
1150ps and tS for SIN =-100ps, yields a minimum period of
1050ps or a clock frequency of 950MHz.

BOOps

-I

1--- 1150ps ----1

FROM
SERIAL
MEDIUM

Figure 1. Loopback Test Architecture

Figure 2. Cascaded 1:8 Converter Architecture

With a minimum delay of 800ps on this output the clock for
the lower order E445 cannot be delayed more than 800ps
relative to the clock of the first E445 without potentially
missing a bit of information. Because the setup time on the
serial input pin is negative coincident excursions on the data
and clock inputs of the E445 will result in correct operation.

="~

--Ir--l
~
_

CLOCKB _ _ _ _

Tpd CLK _ _ _ _ _ _ _ _ _ _ _ _1--~1===~.--toSOUT

The clock frequency is significantly lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E445. By
delaying the clock feeding the second E445 relative to the
clock of the first E445 the frequency of operation can be

ECLinPS and ECLinPS Lite
DL140-Rev4

L...-_ _

CLK _ _ _ _ _ _ _ _ _ _ _.1-_---1
Tpd
to SOUT

.I__.!.I

t=-:P:150PS _ _ _

Figure 3. Cascade Frequency Limitation

2-127

MOTOROLA

MC10E445 MC100E445
frequency up to 1.4GHz. The divide by eight clock of the
second E445 should be used to synchronize the parallel data
to the rest of the system as the parallel data of the two E445's
will no longer be synchronized. This skew problem between
the outputs can be worked around as the parallel information
will be static for eight more clock pulses.

Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock inputs
of the E445. By connecting the clock for the second E445 to
the complimentary clock input pin the device will clock a half
a clock period after the first E445 (Figure 4). Utilizing this
Simple technique will raise the potential conversion

CLOCK --r-----..r-----,
CLOCK ---r-+---".'----,
~7oops~

SERIAL
INPUT
OATA

SIN
SIN

SOUT
SOUT

(1.4GHz)

--.J
ClOCKB I

E445b
SIN
SIN

030201 00

030201 QO

07060504

03 Q2 01 00

-I

lOOps

.-----,L-

CLOCK A

Tpd ClK
toSOUT - - , - - - - - - - - - - ' - - - - '
Boops

I---

-I

I - - - 1150ps - - - I

PARALLEL OUTPUT DATA

Figure 4. Extended Frequency 1 :8 Demultiplexer

[2J

ClK
SINa

00
01

____

___

____

x
~X~

_______________

-JX~

~X~

___________________

_______________

___
07(03 a)

__________________________

05(01 a)
06 (02 a)

-JX~

CU4b

CUBa

On+l

On-4

SOUTa

CU4a

On-l

On-3

On·2

___~I

\I...._ _----.JI

\
\

CUBb _ _ _ _~/r-------~

On+2

On-l

SOUTh

____~I
____-JI
____-JI

On-3
On-2

__________________________
__________________________
__________________________

04 (00 a)

On4

___
___
___

-JX~

X
X
X
X
X
X
X
X

On+3
On

On+l

On+2

On+3

On4

On-3

On-2

On-l

I
I
I
I

\
\

On+l

I
I
\
\

Timing Diagram A. 1:8 Serial to Parallel Conversion

MOTOROLA

2-128

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

4·Bit Parallel/Serial Converter

MC10E446
MC100E446

The MC10El100E446 is an integrated 4-bit parallel to serial data
converter. The device is designed to operate for NRZ data rates of up to
1.3Gb/s. The chip generates a divide by 4 and a divide by a clock for both
4-bit conversion and a two chip a-bit conversion function. The conversion
sequence was chosen to convert the parallel data into a serial stream
from bit DO to D3. A serial input is provided to cascade two E446 devices
for a bit conversion applications. Note that the serial output data clocks off
of the negative input clock transition.

4-81T PARALLEU
SERIAL CONVERTER

• On Chip Clock +4 and +8
• 1.5 Gb/s Typical Data Rate Capability
• Differential Clock and Serial Inputs
•
•
•
•
•

VBB Output for Single-ended Input Applications
Asynchronous Data Synchronization
Mode Select to Expand to a Bits
Internal 75k!llnput Pulldown Resistors
Extended 10DE VEE Range of -4.2V to -5.46V

The SYNC input will asynchronously reset the internal clock circuitry.
FN SUFFIX
This pin allows the user to reset the internal clock conversion unit and
PLASTIC PACKAGE
thus select the start of the conversion process.
CASE 776-02
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the internal load clock will
change on every eighth clock cycle thus allowing for an a-bit conversion scheme using two E446's. When cascaded in an a-bit
conversion scheme the devices will not operate at the 1.3Gb/s data rate of a single device. Refer to the applications section of
this data sheet for more information on cascading the E446.
For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates
above 5DOMHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential
input and bypassed via a 0.01 J.lF capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB
can also be used to AC couple an input Signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPSTM data book.
Pinout: 28-Lead PLCC (Top View)

PIN NAMES
Pin

Function
Differential Serial Data Input
Parallel Data Inputs
Differential Serial Data Output
Differential Clock Inputs
Differential +4 Clock Output
Differential +B Clock Output
Conversion Mode 4-Bit/B-Bit
Conversion Synchronizing Input

SIN
DO-D3
SOUT, SOUT
CLK,CLK
CU4,CU4
CUB,CUB

MODE
SYNC

Mode

Conversion

L
H

4-Bit
B-Bit

03 MOOE NC

NC
19
lB

ClK

VBB

VCC

VEE

saUT

SIN

saUT

SIN

Vcca

ClK

FUNCTION TABLES

SYNC
10

Vcco CUB CUB Vcca CU4 CU4 Vcca

7196

2-129

REV 2

MOTOROLA

MC10E446 MC100E446

LOGIC D!AGRAM

Mode

CUB

ClK

CUB

ClK

CU4
CU4

SYNC

MOTOROLA

2-130

ECLinPS and ECLinPS Lite
DL140-Rev4

MC10E446 MC100E446

DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea =GND)
O'C

Symbol

Characteristic

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

150

IlA

IIH

Input HIGH Current

VOH

Output HIGH Voltage
10E (SOUT Only)
100E (SOUT Only)

-1020
-1025

-790
-930

-980
-1025

-760
-930

-910
-1025

-670
-930

VBB

Output Reference Voltage 1DE
100E

-1.38
-1.38

-1.27
-1.26

-1.35
-1.38

-1.25
-1.26

-1.31
-1.38

-1.19
-1.26

lEE

Power Supply Current

151
174

150

Condition

10E
100E

126
126

151
151

126
126

151
151

126
145

1
1

1. The maximum VOH limit was relaxed from standard ECl due to the high frequency output design. All other outputs are specified with the standard
10E and 100E VOH levels.

AC CHARACTERISTICS (VEE

=VEE (min) to VEE(max); Vee =Veea =GND)
O'C

25'C

Symbol

Characteristic

Min

Typ

FMAX

Max Conversion Frequency

1.3

1.6

tplH
tpHl

Propagation Delay to Output
ClKtoSOUTI
ClKtoCU4
ClKtoCU8
SYNC to CU4, CU8

1020
650
800
650

1200
850
1050
850

Setup Time2

SIN, On

-200

Hold Time2

SIN,Dn

900

IRR

Reset Recovery Time

SYNC

500

IpW

Min Pulse Width

ClK, MR

300

tr
If

Rise/Fall Times

SOUT
Other

100
200

Max

85'C
Min

Typ

1.3

1.6

1020
650
800
650

1200
850
1050
850

-450

-200

-450

650

900

650

300

500

300

Min

Typ

1.3

1.6

1020
650
800
650

1200
850
1050
850

-450

-200

650

900

300

500

Max

Unit

Condition

Gb/s
NRZ
ps

1480
1050
1300
1100

300
225
425

100
200

350
650

1480
1050
1300
1100

300
225
425

350
650

100
200

225
425

350
650

20%-80%

1. Propagation delays measured from negative gOing clock edge.
2. Relative to negative clock edge.

Timing Diagrams
elK
RESET
00

(

X
X
X
X

01-1
02-1
03-1

SOUT
CU4

CUB

X
X
X
X

00-1

I
I

X
X
X
X

00-2
01-2
02-2
03-2

01-1

02-1

03-1

00-2

I
\

01-2

02-2

03-2

I
I

Timing Diagram A. 4:1 Parallel to Serial Conversion

ECLinPS and ECLinPS Lite
Dl140-Rev4

2-131

MOTOROLA

MC10E446 MC100E446

Applications Information
The MC10El100E446 is an integrated 4:1 parallel to serial
converter. The chip is designed to work with the E445 device
to provide both transmission and receiving of a high speed
serial data path. The E446 can convert 4 bits of data into a
1.3Gb/s NRZ data stream. The device features a SYNC input
which allows the user to reset the internal clock circuitry and
restart the conversion sequence (see timing diagram A).

ClK - - - . - - - - - - - - - ,
ClK

--r-+------,

E446A

SOUT
SOUT

The E446 features a differential serial input and internal
divide by 8 circuitry to facilitate the cascading of two devices
to build a 8:1 multiplexer. Figure 1 illustrates the architecture
for a 8:1 multiplexer using two E446's; the timing diagram for
this configuration can be found on the following page. Notice
the serial outputs (SOUT) of the lower order converter feed
the serial inputs of the the higher order device. This feed
through of the serial inputs bounds the upper end of the
frequency of operation. The clock to serial output
propagation delay plus the setup time of the serial input pins
must fit into a single ciock period for the cascade architecture
to function properly. Using the worst case values for these
two parameters from the data sheet, TPD CLK to SOUT
1480ps and tS for SIN = -200ps, yields a minimum period of
1280ps or a clock frequency of 780MHz.

SIN
SIN

Serial
Data

SOUT
SOUT

030201 00

0
5

04 Parallel Data 03 <}1 00

r-I.---

CLOCK '

1000ps

---j.j

I-- 600ps

....._ _ _-'

TpdClK
to SOUT - - - - - - - - - - - - ' - - - - '
1000ps

r--

The clock frequency is somewhat lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E446. By
delaying the clock feeding E446A relative to the clock of
E446B the frequency of operation can be increased.

-I

I----- 1600ps ----I

Figure 1. Cascaded 8:1 Converter Architecture

ClK
RESET
DO
Dl

<
<

D2
D3
04(008)
05(018)
06 (D28)
D7(038)

<
<
<
<

X
X
X
X
X
X
X
X

D2-1
03-1
04-1
05-1
06-1
D7-1

SOUT

CU4
CUB

X
X
X
X
X
X
X
X

DO-I
Dll

00-1

I
I

D0-2
D12
D2-2
03-2
04-2
05-2
06-2
D7-2

01-1

02-1

D3-1

04-1

I
\

05-1

D6-1

07-1

00-2

I
I

Timing Diagram B. 8:1 Parallel to Serial Conversion

MOTOROLA

2-132

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

6-Bit D Register Differential
Data and Clock

MC10E451
MC100E451

The MC10E/l00E45l contains six D-type flip-flops with single-ended
outputs and differential data inputs. The common clock input is also
differential. The registers are triggered by a positive transition of the
positive clock (ClK) input.
A HIGH on the Master Reset (MR) input resets all Q outputs to law.
The VBB output is intended for use as a reference voltage for
single-ended reception of ECl signals to that device only. When using for
this purpose, it is recommended that VBB is decoupled to VCC via a
0,01 f.lF capacitor.

6·BIT D REGISTER
DIFFERENTIAL
DATA AND CLOCK

The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
o Differential Inputs: Data and Clock
o VBBOutput

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

o 1100MHz Min. Toggle Frequency
o Asynchronous Master Reset

o Exlended 100E VEE Range of - 4.2V to - 5.46V
o

75kQ Input Pulldown Resistors

il4

03 VCCO
LOGIC DIAGRAM

ClK

oo----f'-..
00

VBB

---<1/

ClK

VCC

Pinout: 28-Lead PLCC
(Top View)

VEE

VCCO

01
OJ 02 52 VCCO 00
• All VCC and VCCO pins are tied together on the die.
PIN NAMES

Pin
00- 0 5
00- 0 5
ClK
ClK
MR
VBB
00- 0 5

Function
+Data Input
- Data Input
+Clock Input
- Clock Input
Master Reset Input
VBB Output
Data Outputs

02 ---\--f"...
02 ----1-ct..;'

03 ----1-r,
03 ---\-1.0GHz
bandwidth to meet the needs of the most demanding system clock.

TRIPLE DIFFERENTIAL
2:1 MULTIPLEXER

Both, separate selects and a common select, are provided to make the
device well suited for both data path and random logic applications.
The differential inputs have internal clamp structures which will force
the Q output of a gate in an open input condition to go to a LOW state.
Thus, inputs of unused gates can be left open and will not affect the
operation of the rest of the device. Note that the input clamp will take
affect only if both inputs fall 2.5V below VCC.
• Differential D and Q; VBB available
• 700ps Max. Propagation Delay
• High Frequency Outputs

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

• Separate and Common Select
• Extended 1OOE VEE Range of -4.2V to -5.46V
o Internal75kn Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)
SEL2

D2a

Yss

D2b

D2b eOMSEL

PIN NAMES
Pin
Dn[0:2]; Dn[0:2]
SEL
COMSEL
VBB
Q[0:2], Q[0:2]

Function
Differential Data Inputs
Individual Select Input
Common Select Input
VBB Reference Output
Differential Data Outputs

SEL1
Dl a

Dl a

Yee

VEE

Vee

Dlb

FUNCTION TABLE
SEL

Data

H
L

SELa

Daa

Vee

Dab

Dab Veeo

• All VCC and VCCO pins are tied together on the die.

12/93

2-137

REV 2

MOTOROLA

MC10E457 MC100E457
LOGIC DIAGRAM

00
DOb
DOb
SELO

D2b
D2b
SEL2 _L-"C---~

COMSEL

DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee =Veea = GND)
-4D'C

Symbol
VBB

Characteristic
Output Reference
Voltage
IDE
lODE

IIH

Input HIGH
Current

lEE

Power Supply
Current
IDE
lODE

Min

Typ

25'C

D'C
Max

Min

Typ

Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

Cond

-1.43
-1.38

-1.30 -1.38
-1.26 -1.38

-1.27 -1.35
-1.26 -1.38

150

-1.25 -1.31
-1.26 -1.38

150

-1.19
-1.26

150

IlA
rnA

92
92

Vpp(DC)

Input Sensitivity

VCMR

CommomMode
Range

-1.5

110
110

92
92

110
110

-1.5

110
110

-1.5

92
106

110
127

50
0

92
92

-1.5

1. Differential Input voltage reqUired to obtain a full ECl sWing on the outputs.
2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The Vil level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

MOTOROLA

2-138

ECLinPS and ECLinPS Lite
Dll40-Rev4

MC10E457 MC100E457
AC CHARACTERISTICS (VEE

=VEE (min) to VEE (max); Vee =Veea =GND)
DOC

Symbol

Characteristic

Min

tpLH
tpHL

Propagation Delay to Output
D (Differential)
D (Single-Ended)
SEL
COMSEL

tskew

Within-Device Skew

tskew

Duty Cycle Skew

Typ

D'Cto85'C
Max

Min

Typ

Max

Unit

Condition

ps
325
275
300
325

tpLH-tpHL

Vpp(AC)

Minimum Input Swing

150

trltf

Rise/Fall Time

125

475
475
500
525

700
750
775
800

375
325
350
375

475
475
500
525

650
700
725
750

±10

150
275

500

150

275

450

2Q-80%

ECLinPS and ECLinPS Lite
DL140-Rev4

2-139

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual ECL Output Comparator
With Latch

MC10E1651

The MC10E1651 is functionally and pin-for-pin compatible with the
MC1651 in the MECl III family, but is fabricated using Motorola's
advanced MOSAIC III process. The MC10E1651 incorporates a fixed
level of input hysteresis as well as output compatibility with 10KH logic
devices. In addition, a latch is available allowing a sample and hold
function to be performed. The device is available in both a 16-pin DIP and
a 20-pin surface mount package.

DUAL ECl OUTPUT
COMPARATOR
WITH lATCH

The latch enable (lENa and lENb) input pins operate from standard
ECl 10KH logic levels. When the latch enable is at a logic high level the
MC10E1651 acts as a comparator, hence Q will be at a logic high level if
VI > V2 (VI is more positive than V2). Q is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state providing the latch enable setup and hold time
constraints are met.

•

• Typ. 3.0 dB Bandwidth> 1.0 GHz

FNSUFFIX

• Typ. V to Q Propagation Delay of 775 ps

PLASTIC PACKAGE
CASE 775-02

• Typ. Output Rise/Fall of 350 ps
• Common Mode Range -2.0 V to +3.0 V
• Individual latch Enables
• Differential Outputs
• 28mV Input Hysteresis

LSUFFIX
CERAMIC PACKAGE
CASE 620-10

LOGIC DIAGRAM
Vla

FUNCTION TABLE

Oa
V2a
LENa-----a

LEN

V1, V2

Function

H
H

V1 >V2
V1 V2 (V1 is more positive than V2). Q is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state, providing the latch enable setup and hold time
constraints are met. The level of input hysteresis is controlled by applying
a bias voltage to the HYS pin.

•

• Typical 3.0 dB Bandwidth> 1.0 GHz

FNSUFFIX
PLASTIC PACKAGE
CASE 775-02

• Typical V to Q Propagation Delay of 775 ps
• Typical Output Rise/Fall of 350 ps
• Common Mode Range -2.0 V to +3.0 V
• Individual latch Enables
• Differential Outputs
• Programmable Input Hysteresis

LSUFFIX
CERAMIC PACKAGE
CASE 620-10

lOGIC DIAGRAM

FUNCTION TABLE

Via
Qa
V2a

LENa--+--o

LEN

V1, V2

Function

H
H
L

V1 >V2
V1

~ -1.2
g

H~STE~ESI~

- :---"

t--,..
~

\~ ~ ~

.§.
20

c---r--

-4 Vref 4

-0.2

AC CHARACTERISTICS

(VEE

Characteristic

Min

Typ

Propagation Delay to Output
Vtoa
LENtoa

600
400

750
575

Setup Time
V

450

Enable Hold Time
V

-so

Minimum Pulse Width
LEN

400

tskew

Within Device Skew
Delay Dispersion
(ECL Levels)

0.0

25°C
Max
900
750

Min

Typ

625
400

775
575

300

450

0.1

0.2

0.3

0.4

0.5

-250

-50

85°C
Max
925
750

Min

Typ

700
500

850
650

300

550

350

-250

-100

-250

Max

Unit

Condition

1050
850
ps
ps
ps

400
15

ps
100
60

Delay Dispersion
(TTL Levels)
Rise/Fall Times
20·80%

-0.1

=-5.2 V ±5%; VCC =+5.0 V ±5%)

tpLH
tpHL

TOE

....... :::::

Figure 2. Hysteresis Programming Voltage

DOC
Symbol

PROGRAMMING VOLTAGE (VOLTAGE ABOVE VEE)

Figure 1. Typical Hysteresis Curve

tr
tf

85°C

o
12

Vin, DIFFERENTIAL INPUT VOLTAGE (mY)

TDL

-1.8
-20 -16 -12 -8

tpw

T = O°C

-1.4

cj -1.6

25°C

3,4
3,5
ps

350
100

6,7
5,6
ps

225

325

475

225

325

475

250

375

500

1. The propagatIon delay IS measured from the crosspoInt of the Input SIgnal and the threshold value to the crosspoInt of the a and a output SIgnals.
For propagation delay measurements the threshold level (VTHR) is centered about an 850 mV input logic swing with a slew rate of 0.75 V/NS.
There is an insignificant change in the propagation delay over the input common mode range.
2. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions.
3. Refer to Figure 4 and note that the input is at 850 mV ECL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input Signal and the threshold value to the crosspoint of the a and Q output Signals.
4. The slew rate is 0.25 V/NS for input rising edges.
5. The slew rate is 0.75 V/NS for input rising edges.
6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is
measured from the crosspoint of the input Signal and the threshold value to the crosspoint of the a and Q output signals.
7. The slew rate is 0.3 V/NS for input rising edges.

APPLICATIONS INFORMATION
The timing diagram (Figure 3) is presented to illustrate the
MC10E1652's compare and latch features. When the signal
on the LEN pin is at a logic high level, the device is operating
in the "compare mode," and the signal on the input arrives at
the output after a nominal propagation delay (tPHL, tPLH). The
input signal must be asserted for a time, ts , prior to the

MOTOROLA

negative going transition on LEN and held for a time, th, after
the LEN transition. After time th, the latch is operating in the
"latch mode," thus transitions on the input do not appear at
the output. The device continues to operate in the "latch
mode" until the latch is asserted once again. Moreover, the
LEN pulse must meet the minimum pulse width (tpw)

2-146

ECLinPS and ECLinPS Lite
DL140- Rev 4

MC10E1652
requirement to effect the correct input-output relationship.
Note that the LEN waveform in Figure 3 shows the LEN
signal swinging around a reference labeled VBBINT. this
waveform emphasizes the requirement that LEN follow
typical ECL 10KH logic levels because VBBINT is the
internally generated reference level, hence is nominally at
the ECL VBB level.
Finally, VOO is the input voltage overdrive and represents
the voltage level beyond the threshold level (VTHR) to which
the input is driven. As an example, if the threshold level is set
on one of the comparator inputs as 80 mV and the input

signal swing on the complementary input is from zero to 100
mV, the positive going overdrive would be 20 mV and the
negative going overdrive would be 80 mV. The result of
differing overdrive levels is that the devices have shorter
propagation delays with greater overdrive because the
threshold level is crossed sooner than the case of lower
overdrive levels. Typically, semiconductor manufactures
refer to the threshold voltage as the input offset voltage
(VOS) since the threshold voltage is the sum of the externally
supplied reference voltage and inherent device offset
voltage.

VBBINT- LEN---.....J

V -r------,.
VTHR

:~~--l---~,t

----'~1~

Figure 3. InpuUOutput Timing Diagram

DELAY DISPERSION
Under a constant set of input conditions comparators have
a specified nominal propagation delay. However, since
propagation delay is a function of input slew rate and input
voltage overdrive the delay dispersion parameters, TOE and
TOT, are provided to allow the user to adjust for these
variables (where TOE and TOT apply to inputs with standard
ECL and TTL levels, respectively).
Figure 4 and Figure 5 define a range of input conditions
which incorporate varying input slew rates and input voltage
overdrive. For input parameters that adhere to these
constraints the propagation delay can be described as:
TNOM ± TOE (or TOT)

where TNOM is the nominal propagation delay. TNOM
accounts for nonuniformity introduced by temperature and
voltage variability, whereas the delay dispersion parameter
takes into consideration input slew rate and input voltage
overdrive variability. Thus a modified propagation delay can
be approximated to account for the effects of input conditions
that differ from those under which the parts where tested. For
example, an application may specify an ECL input with a slew
rate of 0.25 VINS, an overdrive of 17 mV and a temperature
of 25°C, the delay dispersion parameter would be 100 ps.
The modified propagation delay would be
775ps ± 100ps

r---

-O.9V---------,....------""7---1. 07V

INPUT
THRESHOLD
RANGE

L-

-1. 58V
-1.75V------""'--------------

Figure 4. ECL Dispersion Test Input Conditions

ECLinPS and ECLinPS Lite

DL140-Rev4

2.5V----------,.-------""7--2,OVr---

O.5V

l.. -

OV---~~------------

Figure 5. TTL Dispersion Test Input Conditions

2-147

MOTOROLA

2-148

9iigh Performance Eel Data
ECLinPS and ECLinPS Lite

This section contains AC & DC specifications
for each 8, 16 or 2o-Iead SOIC ECLinPS Lite
device type. Specifications common to all device
types can be found in the first part of this section.
While specifications unique to a particular device
can be found in the individual data sheets
following the family specifications.

ECLinPS Lite Family Specifications
& Device Data Sheets

Data Sheet Classification

Advance Information - product in the sampling or
pre-production stage at the time of publication.

Product Preview- product in the design stage at
the time of publication.

ECLinPS and ECLinPS Lite
DL140-Rev4

3-1

MOTOROLA

MOTOROLA
SEMICONDUCTOR GENERAL INFORMATION

ECLinPS Lite™ Single Gate ECl Devices
Features

•
•
•
•

275ps Package Gate Delays
2.0GHz+ Flip-Flop Toggle Frequencies
Space Efficient SOIC Packages
Choice of ECl Compatibility: MECl 10HTM (10El); or ECl
1OOK (1 OOEl)
• Flow-Through Pinouts
• Specified Over Industrial Temperature Range: -40°C to
+85°C
o Extended VEE Range for Both 10El and 100El Devices
ECLinPS Lite is a family of single, essential logic primitives
- gates, muxes, flops etc. - along with translators, low
voltage ECl logic devices and Pll support products, housed
in a space efficient, cost effective standard SOIC packages.
Packaged gates switch in 250ps typ., with flops toggling at
over 2GHz.
ECLinPS Lite offers better AC specs and tighter skews
than even the ECLinPSTM family. At the same time the family
provides superior isolation over multiple gate logic. Its small
package size makes it ideal for pin cards and other
applications that require density, but not at the expense of
signal integrity.
The ECLinPS Lite family utilizes the same MOSAIC IIITM
process as the ECLinPS family to provide state-of-the-art
bipolar process speeds. The small outline SOIC package and
special design techniques serve to enhance the level of
performance even further. The SOIC package shaves over
50% from the propagation delay associated with the
ECLinPS family's 28-lead PlCC package. In addition special

MOTOROLA

design techniques have been applied to decrease output
transition times by nearly 50%, resulting in nearly a 100%
improvement in bandwidth and toggle frequencies over a
standard ECLinPS device.
Like the ECLinPS family, all ECLinPS Lite devices, except
the El89, are offered in 10El and 100El versions for
compatibility with the two existing ECl standards, ECl 10H
and ECl 100K respectively. As with the ECLinPS family the
AC performance of the two versions of ECLinPS Lite devices
are identical, therefore AC performance will not be a factor in
choosing an ECl standard. The rules for mixing 10El and
100El devices in a single design are outlined in the
interfacing section on page 5-29.
The VEE power supply range for both ECLinPS Lite
versions have been extended beyond the levels defined in
the original ECl standard specifications. The lower end of
the 1OOEl VEE limit has been decreased to -5.5V to allow for
interfacing with three level series gated 100K arrays. In
addition the upper end of the 10El VEE limit has been
increased to -4.75V to allow for use in PECl designs which
use a 5V ± 5% supply. Note the -4.75V VEE for 1OEl devices
does not always hold for temperatures less than 25°C (see
individual data sheets), therefore for PECl designs whose
environments can fall below 25°C it is recommended that the
100El devices be used to allow the designer to choose
functions from the entire family.
The transfer curves, switching waveforms and parameter
definitions are identical to those of the ECLinPS family. In
addition the application of ECLinPS Lite devices in a system
follows the same rules as previous ECl families.

3-2

ECLinPS and ECLinPS Lite
DL140-Rev4

EClinPS Lite Family Specifications
Absolute Maximum Ratings
Beyond which device life maybe impaired. 1
Characteristic

=OV)
Input Voltage (VCC =OV)
Power Supply (VCC

Output Current

Continuous
Surge

Operating Temperature Range
Operating Range 1,2

1. Unless otherwise specified on an Individual data sheet.
2. Parametric values specified at:
1OOEL Series:
1OEL Series:

Symbol

Rating

Unit

VEE

-8.0toO

VDC

Oto-6.0

VDC

lout

50
100

rnA

-40 to +85

VEE

-5.7to-4.2

-4.20V to -5.50V
-4.94V to -5.50V

1OEl Series DC Characteristics
VEE

=VEE(min) -

VEE(max); Vee

=GND1
-40'C

Symbol

Characteristic

O'C

25'C

85'C

Min

Max

Min

Max

Min

Max

Min

Max

Unit

VOH

Output HIGH Voltage

-1080

-890

-1020

-640

-980

-810

-910

-720

VOL

Output LOW Voltage

-1950

-1650

-1950

-1630

-1950

-1630

-1950

-1595

VIH

Input HIGH Voltage

-1230

-890

-1170

-840

-1130

-810

-1060

-720

VIL

Input LOW Voltage

-1950

-1500

-1950

-1480

-1950

-1480

-1950

-1445

IlL

Input LOW Current

0.5

0.3

j!A

...

1. 10EL CirCUIts are designed to meet the DC specifications shown In the table after thermal eqUIlibrium has been established. The CircUit IS In
a test sockel or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through
a son resistor to -2.0V except where olherwise specified on the individual data sheets.

100El Series DC Characteristics
VEE =VEE(min) - VEE(max); Vee =GND1
-40'C
Symbol

Characteristic

O'Cto 85'C
Typ

Max

Unit

Condition

VOH

Output HIGH Voltage

-1085

-1005

-880

-1025

-955

-880

VIN = VIH(max)

VOL

Output LOW Voltage

-1830

-1695

-1555

-1810

-1705

-1620

orVIL(min)

VOHA

Output HIGH Voltage

-1095

-1035

VIN = VIH(max)

Output LOW Voltage

-1555

-1610

orVldmin)

VIH

Input HIGH Voltage

-1165

-880

-1165

VOLA

-880

VIL

Input LOW Voltage

-1810

-1475

-1810

-1475

IlL

Input LOW Current

0.5

Min

Typ

Max

Min

0.5

j!A

VIN = VIL(max)

1. This table replaces the three tables traditionally seen In ECL 1OOK data books. The Sf'me DC parameter values at VEE -4.5V now apply across
the full VEE range of-4.2V to-5.5V. Outputs are terminated through a 50n resistor 10 -2.0V except where otherwise specified on the individual
data sheets.

ECLinPS and ECLinPS Lite
DL140-Rev4

3-3

MOTOROLA

Applications Information

Introduction
The ECLinPS Lite family of products is very similar in
design and performance as the multi-gate ECLinPS family.
As a result the design guide and application notes written in
support of the ECLinPS family are equally applicable to the
new ECLinPS Lite family. The reader is encouraged to read
through the ECLinPS data book to answer any general
questions they may have concerning the ECLinPS Lite
family. The following paragraphs will be used to describe
behavior that is unique to the ECLinPS Lite family or which
has not been thoroughly documented in the existing
literature.

single-ended interfaces in mind, however in the 1GHz+
realm of deSigns differential interconnect is predominant. For
differential interconnect systems the criteria for FMAX needs
to be redefined to better describe the reliable operating
frequency range of a device. Under this new set of criteria the
ECLinPS Lite family can be pushed well above 2.SGHz and
thus provide a cost effective means for processing very high
speed signals.

Maximum Frequency/Bandwidth
One of the goals of the ECLinPS Lite family was to provide
means for using ECl in even higher frequency applications.
Much effort was placed in the reduction of the output
transition times as these were the limiting factors of the
frequency capability of the original ECLinPS family. With a
nearly SO% reduction in output edge rates the ECLinPS Lite
family's frequency capability is nearly twice that of the
ECLinPS devices. Some of the 16- and 20-lead ECLinPS
Lite products do not have the faster edge rates as the extra
current required would push the power dissipation beyond
the capabilities of the package.
The data sheets for the flip-flop devices state maximum
toggle frequencies of 2.2GHz, although impressive these
values tend to underestimate the useful bandwidth of the
device. Similarly the buffer devices have a 3db bandwidth
(600mV output swing) of about 1.4GHz, however the devices
can be useful to frequencies well above 2GHz. The trick to
using the ECLinPS Lite devices to their fullest capabilities is
to take advantage of the differential I/O functions. From the
data sheets for the differential devices the minimum input
swing is 1S0mV, a value significantly lower than the
somewhat arbitrary 600mV output chosen as the FMAX fail
criteria. Figure 1 illustrates several ECLinPS Lite devices'
output eye voltage versus input frequency; note for the buffer
type devices the outputs produce a 1S0mV eye pattern for
frequencies well over 3GHz.
Traditionalist may argue that 1S0mV input swings leave no
noise margins for the design, when analyzed further this is
not the case. For single-ended interconnect the worst case
noise margins are ~1S0mV with no common mode noise
rejection capabilities. For a 1S0mV differential input the same
1S0mV of noise margin exists, however in this case the
interface also has common mode noise rejection capability
and thus may provide a safer environment than a standard
single-ended interface.
The purpose of this discussion is to illustrate the potential
of using ECLinPS Lite devices at frequencies well above the
stated maximum limits. The criteria for establishing the
maximum frequency of a device was determined with

MOTOROLA

500

1000

1500

2000

2500

3000

3500

4000

FREQUENCY (MHz)
1000
FLIP-FLOP

$' BOO

.s
w

............

600
>w
I-

::>

400

::>
0

200

lll-

500

1000

1500

2000

2500

............ i'--

3000

3500

4000

FREQUENCY (MHz)

Figure 1. Eye Pattern versus Frequency
Using ECLinPS lite in PECl Designs
PECl is an acronym for Positive ECl and simply
represents using standard ECl devices in a +S.OV
environment. All of the ECLinPS Lite devices, as with the
majority of all ECl devices, will operate as specified when
positive power supplies are used. The reason for the use of
negative power supplies with ECl is due to the fact that the
output levels and internal bias levels are VCC rail referenced.
Because ground is simpler to keep quiet than a power supply,
it was the natural choice forthe VCC bias. Because the output
levels vary 1:1 with VCC, differences in power supply levels
between transmitter and receiver can be problematic. These
problems can be eliminated if differential interconnect is
used. A thorough discussion on this subject can be
found in the PECl application note (Designing With PECl AN1406/D) provided in the Design Guide and Application
Notes chapter (Chapter S) of this book.
With its small size and low power the ECLinPS Lite family
of products will naturally find applications in PECl form in
otherwise TTL or CMOS systems. Many of these applications

ECLinPS and ECLinPS Lite

DL140-Rev4

will be in the area of clock distribution. Because minimizing
skew is the most important aspect of clock distribution
differential interconnect should be used. This not only
minimizes skew, but as previously mentioned, it also
eliminates problems due to VCC variation in PECL designs.
Again, refer to the Motorola application note (ECL Clock
Distribution Techniques - AN1405/D) dealing with using ECL
in clock distribution applications for a more detailed
discussion.

Package Information
The package chosen for the ECLinPS Lite family is the
standard SOIC package. The a-lead, 16-lead and 20-lead
SOICs are plastic surface mount packages with gUll wing,
50mil pitch leads. Figure 3 and Figure 4 illustrate the
recommended PCB solder pads for the SOIC package.
Because the SOIC is a plastic package the long term
reliability of a device is going to be dependent on the
operating junction temperature. As the junction temperature
of the device increases an intermetallic is formed between
the gold bond wire and the aluminum bonding pad. This
intermetallic eventually causes a void to develop and the
affected pin to become an open circuit. For a more detailed
discussion on the subject refer to the Package and Thermal
section of the ECLinPS data book.

0.00111F
IN

0-11---.:---1 '-.;:--.,.---<0

OUT

,/(:)---1--...-0 OUT

50n

Vss

""r O0 0

Figure 2. AC Coupling Architecture
An important aspect of using ECLinPS Lite in clock
distribution schemes is in the interface to the clock source.
By taking advantage of the AC coupling capability of the
EL16, or any other differential input device which also
features a VBB output, ECLinPS Lite products can be
interfaced to clock sources which generate other than ECL
compatible outputs. Probably the most cost efficient and
simplest oscillators to choose are sinusoidal oscillators. By
using the architecture of Figure 2 a sinusoidal oscillators can
be used to drive ECLinPS Lite devices. The only criteria is
that the amplitude of the oscillator input not exceed the upper
or lower end of the CMR range when centered on the VBB
reference. A larger amplitude oscillator output can be used if
a lower DC bias is used or if the output of the oscillator is
voltage divided prior to being coupled into the EL16.

0.160"±O.005"

o-r

0.245" MIN

0.030" ±O.005"

Figure 3. 8-, 16-Lead SOIC Solder Pad Dimensions

To maintain stability during open input situations all of the
differential input devices employ input clamping circuitry.
Because all of the inputs of ECLinPS Lite devices have
internal input pull down resistors when left open the inputs will
pull down to VEE. A clamp voltage will take control of the input
buffer when both inputs pull lower than the clamp voltage.
This clamp voltage does place a lower bound on the CMR
range of a device. In the ECLinPS Lite family the internal
clamp voltage is referenced to the VEE power rail, as a result
if a larger CMR range is necessary the VEE of a device can be
lowered. Each incremental lowering of VEE will increase the
CMR range by an equivalent amount. To minimize the CMR
range of devices, some of the newer members of the
ECLinPS Lite family employ a different open input bias
structure. These devices will pull the true input to VEE and
bias the compliment input to VCcl2. This will force the output
of the input buffer to a LOW state. Refer to specific data
sheets to identify if this newer structure is used.

ECLinPS and ECLinPS Lite

0.050"TYP

LooooJ
----I I.--

Input Clamp Circuitry and CMR Range

DL140-Rev4

---j

0.050"TYP

''''rOOOOl
0.325" ±O.005"

0.420" MIN

LooooJ
----I I.-0.030" ±O.005"

Figure 4. 2D-Lead Wide SOIC Solder Pad Dimensions

3-5

MOTOROLA

225
200
175

'\.

"'-

150

-r---r-- -

B-LEAD

~ 125
CD

100
75

t--

16-LEAD

r-- ~ I---

-r---

2o-LEAD

100

200

300

400

500

600

700

The 8-lead, 16-lead and 20-Iead SOICs exhibit a thermal
resistance as pictured in Figure 5. With this information as
well as the power dissipation of the device in question
(calculated as shown in the thermal section of the ECLinPS
Data Book) the approximate junction temperature and thus
theoretical lifetime can be estimated. ECLinPS Lite devices
are designed with chip power levels that permit acceptable
reliability levels, in most systems, under the conventional
500lfpm (2.5m/s) airflow. In fact, for all systems but those that
operate at the maximum allowed ambient temperatures
ECLinPS Lite devices will prove reliable with little or no
cooling airflow.

800

AIR FLOW (LFPM)

Figure 5. sOle Thermal Resistance

MOTOROLA

3-6

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

4-lnput OR/NOR

MC10EL01
MC100EL01

The MC10EU100EL01 is a 4-input ORINOR gate. The device is
functionally equivalent to the E101 device with higher performance
capabilities. With propagation delays and output transition times
significantly faster than the E101 the EL01 is ideally suited for those
applications which require the ultimate in AC performance.
• 230ps Propagation Delay
• High Bandwidth Output Transitions
• 75k.Q Internal Input Pulldown Resistors
• >1000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT

DO 1

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

8 Vee

PIN DESCRIPTION

D3 4

DC CHARACTERISTICS (VEE

5 VEE

Characteristic

Min

lEE

Power Supply Current 10EL
100EL

VEE

Power Supply Voltage 10EL
-4.75
100EL -4.20

IIH

Input HIGH Current

AC CHARACTERISTICS (VEE

00-03
Q

Data Inputs
Data Outputs

25'C

O'C

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

150

Min

-4.75
-4.20

85'C

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

150

Min

-4.75
-4.20

Typ

Max

Unit

14
16

17
20

-5.2
-4.5

-5.5
-5.5

150

I1A

150

=VEE (min) to VEE(max); VCC = GND)
-40'C

Symbol

FUNCTION

=VEE(min) to VEE(max); VCC = GND)
-40'C

Symbol

Characteristic

D'C

85'C

25'C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

tpLH
tpHL

Propagation Delay to
Output

220

370

120

220

320

130

230

330

150

250

350

tr
tf

Output Rise/Fall Times Q
(20%-80%)

100

225

350

100

225

350

100

225

350

100

225

350

12193

3-7

REV 2

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2.lnput AND/NAND

MC10EL04
MC100ELQ4

The MC10EU100EL04 is a 2-input AND/NAND gate. The device is
functionally equivalent to the E104 device with higher performance
capabilities. With propagation delays and output transition times
significantly faster than the E104 the EL04 is ideally suited for those
applications which require the ultimate in AC performance.
• 240ps Propagation Delay
• High Bandwidth Output Transitions
• 75kn Internal Input Pulldown Resistors
• >1000V ESD Protection
o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

8 VCC

PIN DESCRIPTION

FUNCTION

DO,D1

Data Inputs
Data Outputs

NC 4

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
-4DOC
Symbol

Characteristic

Min

lEE

Power Supply Current 1DEL
100EL

VEE

Power Supply Voltage 10EL
100EL

IIH

Input HIGH Current

AC CHARACTERISTICS (VEE

-4.94
-4.20

DOC

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

DO
01

Min

-4.94
-4.20

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

250
150

Min

-4.75
-4.20

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

Typ

Max

Unit

14
16

17
20

-5.2
-4.5

-5.5
-5.5

V·

250
150

I1A

250
150

=VEE(min) to VEE(max); VCC = GND)

Characteristic

tpLH
tpHL

Propagation Delay to
Output

tr
tf

Output Rise/Fall Times Q
(20%-80%)

DOC

25°C

85°C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

.70

235

410

120

235

360

130

240

370

155

265

395

100

225

350

100

225

350

100

225

350

100

225

350

12193

85°C

Typ

250
150

-4DOC
Symbol

25°C

Typ

REV 2

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC10EL05
MC100EL05

2-lnput Differential AND/NAND
The MC10EU100ELOS is a 2-input differential ANDINAND gate. The
device is functionally equivalent to the E404 device with higher
performance capabilities. With propagation delays and output transition
times significantly faster than the E404 the ELOS is ideally suited for those
applications which require the ultimate in AC performance.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the ELOS
to also be used as a 2-input differential ORINOR gate.
The differential inputs employ clamp circuitry so that under open input
conditions (pulled down to VEE) the input to the AND gate will be HIGH. In
this way, if one set of inputs is open, the gate will remain active to the
other input.

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 27Sps Propagation Delay
• High Bandwidth Output Transitions
• 7Skn Internal Input Pulldown Resistors
• >1000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT

DO 1

8 Vee
PIN DESCRIPTION

FUNCTION

DO,D1

Data Inputs
Data Outputs

5 VEE

12193

3-9

REV2

MOTOROL.A

MC10EL05 MC100EL05
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-4DOC
Symbol
lEE

VEE

IIH

Characteristic

Min

Power Supply Current
1DEL
1DOEL
Power Supply Voltage
10EL -4.75
100EL -4.20

D'C

Typ

Max

18
18

22
22

-5.2
-4.5

-5.5
-5.5

Input HIGH Current

Min

-4.75
-4.20

25°C

Typ

Max

18
18

22
22

-5.2
-4.5

-5.5
-5.5

150

Min

-4.75
-4.20

B5'C

Typ

Max

18
18

22
22

-5.2
-4.5

·-5.5
-5.5

150

Min

-4.75
-4.20

Typ

Max

Unit

18
21

22
25

rnA

-5.2
-4.5

-5.5
-5.5

150

IlA

Unit

150

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
DOC

-4DOC
Symbol

Characteristic

25'C

Min

Typ

Max

Min

Typ

Max

260

440

185

275

390

tpLH
tpHL

Propagation Delay to
Output

135

VPP

Minimum Input SWing1

150

VCMR

Common Mode Range2

-0.4

tr
tf

Output Rise/Fall Times Q
(20%-80%)

100

225

-0.4

350

100

Typ

Max

Min

Typ

Max

185

275

390

215

305

420

150

150
See2

B5°C

Min

225

See2

-0.4

350

100

150

225

See2

-0.4

350

100

ps
mV

225

See2

350

1. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ~40.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 3.0V.

MOTOROLA

3-10

ECLinPS and ECLlnPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2.lnput XOR/XNOR

MC10EL07
MC100EL07

The MC10EU100EL07 is a 2-input XOR/XNOR gate. The device is
functionally equivalent to the E107 device with higher performance
capabilities. With propagation delays and output transition times
significantly faster than the E107 the EL07 is ideally suited for those
applications which require the ultimate in AC performance.
• 260ps Propagation Delay
• High Bandwidth Output Transitions
• 75kQ Internal Input Pulldown Resistors
• >1000V ESD Protection

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

NC 1

8 VCC

PIN DESCRIPTION

NC 4

FUNCTION

00,01
Q

Data Inputs
Data Outputs

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
-40'C
Symbol

Characteristic

lEE

Power Supply Current 10EL
100EL

VEE

Power Supply Voltage 10EL -4.94
100EL -4.20

IIH

Input HIGH Current

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

DO
01

AC CHARACTERISTICS (VEE

Min

-4.94
-4.20

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

250
150

Min

-4.75
-4.20

85'C

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

250
150

Min

-4.75
-4.20

Typ

Max

Unit

14
16

17
20

-5.2
-4.5

-5.5
-5.5

250
150

IlA

250
150

=VEE(min) to VEE(max); Vce = GND)
-40'C

Symbol

25'C

O'C

Typ

Min

Characteristic

O'C

25'C

85'C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

tpLH
tpHL

Propagation Delay to
Output

250

435

140

250

385

150

260

395

170

280

415

tr
tf

Output Rise/Fall Times Q
(20%-80%)

100

225

350

100

225

350

100

225

350

100

225

350

12193

3-11

REV 2

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

1:2 Differential Fanout Buffer

MC10EL11
MC100EL11

The MC10EU100EL11 is a differential 1:2 fanout buffer. The device is
functionally similar to the E111 device but with higher performance
capabilities. Having within-device skews and output transition times
significantly improved over the E111, the EL 11 is ideally suited for those
applications which require the ultimate in AC performance.
The differential inputs of the EL 11 employ clamping circuitry to
maintain stability under open input conditions. If the inputs are left open
(pulled to VEE) the 0 outputs will go LOW.

• 26Sps Propagation Delay
• Sps Skew Between Outputs
• High Bandwidth Output Transitions
DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 7SkQ Internal Input Pulldown Resistors
• >1 OOOV ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

[3J

PIN DESCRIPTION

FUNCTION

D
00,01

Data Inputs
Data Outputs

12193

3-12

REV4

MOTOROI.A

MC10EL11 MC100EL11
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-40'C
Symbol
lEE

VEE

IIH

Characteristic

Min

Power Supply Current
10EL
100EL
Power Supply Voltage
10EL
100EL

Max

26
26

31
31

-5.2
-4.5

-5.5
-5.5

Min

26
26

31
31

-4.75
-4.20

-5.2
-4.5

-5.5
-5.5

150

Min

85°C

Typ

Max

26
26

31
31

-5.2
-4.5

-5.5
-5.5

Min

Typ

Max

26
30

31
36

-5.2
-4.5

-5.5
-5.5

Unit

-4.75
-4.20

150

!lA

=VEE (min) to VEE(max); Vee = GND)

Characteristic

O'C

85'C

25'C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

135

260

385

185

260

335

190

265

340

215

290

365

5
5

20
20

5
5

20
20

5
5

20
20

tpLH
tpHL

Propagation Delay to
Output

tSKEW

Within-Device Skew1
Duty Cycle Skew2

Vpp

Minimum Input SWing3

150

VCMR

Common Mode Range 4

-0.4

tr
tf

Output Rise/Fall Times Q
(20%-80%)

100

1.
2.
3.
4.

Max

V
-4.75
-4.20

-40'C
Symbol

Typ

rnA

Input HIGH Current

AC CHARACTERISTICS (VEE

25'C

O'C

Typ

5
5
150

225

See4

-0.4

350

100

150

225

See4

-0.4

350

100

150

225

See4

-0.4

350

100

225

See4

350

Within-device skew defined as identical transitions on similar paths through a device.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of 040.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 2.5V.

ECLinPS and ECLinPS Lite
DL140-Rev4

3--13

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low Impedance Driver

MC10EL12
MC100EL12

The MC10EU100EL12 is a low impedance drive buffer. With two pairs
of ORINOR outputs the device is ideally suited for high drive applications
such as memory addressing. The device is a function equivalent to the
E112 device with higher performance capabilities. With propagation
delays significantly faster than the E112 the EL12 is ideally suited for
those applications which require the ultimate in AC performance.
• 290ps Propagation Delay
• Dual Outputs for 25n Drive Applications
• 75kn Internal Input Pulldown Resistors

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• >1 OOOV ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION

FUNCTION

00,01
Qa,Qb

Data Inputs
Data Outputs

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
DOC

-40°C
Symbol

Characteristic

Min

lEE

Power Supply Current 10EL
100EL

VEE

Power Supply Voltage 10EL
100EL

IIH

Input HIGH Current

AC CHARACTERISTICS (VEE

-4.94
-4.20

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

Min

-4.94
-4.20

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

150

Min

-4.94
-4.20

8SoC

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

150

Min

-4.94
-4.20

Typ

Max

Unit

14
16

17
20

-5.2
-4.5

-5.5
-5.5

150

).LA

150

=VEE(min) to VEE(max); VCC = GND)
DoC

-40°C
Symbol

2SoC

Typ

Characteristic

85°C

25°C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

tpLH
IPHL

Propagation Delay 10
Oulpul

120

280

500

170

280

450

180

290

450

210

320

480

Ir
tf

Outpul Rise/Fall limes Q
(20%-80%)

150

350

550

150

350

550

150

350

550

150

350

550

12193

3-14

REV2

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual 1:3 Fanout Buffer

MC100EL13

For information on the MC 1OOEL 13,
please refer to the MC 1OOLVEL 13
datasheet on page 4-20 in
Chapter 4 of this book.

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 0-04

ECLinPS and ECLinPS Lite
OL140-Rev4

3-15

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

1:5 Clock Distribution Chip

MC100EL14

For information on the MC100EL 14,
please refer to the MC100LVEL 14
datasheet on page 4-22 in
Chapter 4 of this book.

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 7510·04

MOTOROLA

3-16

ECUnPS and ECLinPS Lite
OL140-Rev4

MOTOROlA
SEMICONDUCTOR TECHNICAL DATA

1 g4 Clock Distribution Chip

MC10EL15
MC100EL15

The MCl OEUl OOEl 15 is a low skew 1:4 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECl or, if
positive power supplies are used, PECl input signal. If a single-ended
input is to be used the VBB output should be connected to the ClK input
and bypassed to ground via a O.D1I1F capacitor. The VSS output is
designed to act as the switching reference for the input of the El 15 under
single-ended input conditions, as a result this pin can only source/sink up
to 0.5mA of current.
The El15 features a multiplexed clock input to allow for the distribution
of a lower speed scan or test clock along with the high speed system
clock. When lOW (or left open and pulled lOW by the input pulldown
resistor) the SEl pin will select the differential clock input.

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 7518-05

The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the lOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification lirnits are referenced to the negative edge of
the clock input.
o 50ps Output-to-Output Skew
o Synchronous Enable/Disable

PIN DESCRIPTION

o Multiplexed Clock Input
o 75kQ Internal Input Pulldown Resistors
o >1 OOOV ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

VCC

FUNCTION

ClK
SClK
EN
SEl
VSS
00-3

Diff Clock Inputs
Scan Clock Input
Sync Enable
Clock Select Input
Reference Output
Diff Clock Outputs

EN SClK ClK ClK VBB SEl VEE
FUNCTION TABLE
ClK

SClK

SEl

l
H
X
X
X

X
X

l
l
H
H

l
l
l
l
H

l
H
l
H
l*

l
H
X

* On next negative transition of
ClKorSClK

5/95

3-17

REV2

MOTOROLA

MC10EL15 MC100EL15
ABSOLUTE MAXIMUM RATINGS1
Symbol

Rating

Unit

Power Supply (VCC = OV)

-8.0toO

VDC

Input Voltage (VCC = OV)

Oto-6.0

VDC

lout

Output Current

50
100

Operating Temperature Range

-40 to +85

°c

VEE

Operating Range 1,2

-5.7to-4.2

VEE

Characteristic

Continuous
Surge

1. Absolute maximum rating, beyond WhiCh, device life may be Impaired, unless otherwise specified on an Individual data sheet.
2. Parametric values specified at: 1OOEL Series: -4.20V to -5.50V
1OEL Series:
-4.94V to -5.50V

10ELSERIES
DC CHARACTERISTICS (VEE = VEE(min) - VEE(max); Vee = GND1)
-40°C
Symbol

Characteristic

O°C

25°C

85°C
Max

Unit

VOH

Output HIGH Voltage

-1080

-890

-1020

-840

-980

-810

-910

-720

VOL

Output LOW Voltage

-1950

-1650

-1950

-1630

-1950

-1630

-1950

-1595

VIH

Input HIGH Voltage

-1230

-890

-1170

-840

-1130

-810

-1060

-720

VIL

Input LOW Voltge

-1950

-1500

-1950

-1480

-1950

-1480

-1950

-1445

IlL

Input LOW Current

0.5

0.3

JlA

Min

Max

Min

Max

Min

Max

Min

1. 10EL CircUits are designed to meet the DC specifications shown In the table after thermal equilibrium has been established. The CirCUit IS In
a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through
a 50n resistor to -2.0V except where otherwise specified on the individual data sheets.
100EL SERIES
DC CHARACTERISTICS (VEE

= VEE(min) -

VEE(max); Vee

= GND1)

-40°C
Characteristic

Symbol

O°Cto 85°C

Min

Typ

Max

Min

Typ

Max

Unit

Condition

VOH

Output HIGH Voltage

-1085

-1005

-880

-1025

-955

-880

VIN = VIH(max)

VOL

Output LOW Voltage

-1830

-1695

-1555

-1810

-1705

-1620

orVIL(min)

VOHA

Output HIGH Voltage

-1095

-1035.

VOLA

Output LOW Voltage

-1555

VIH

Input HIGH Voltage

-1165

-880

-1165

VIL

Input LOW Voltge

-1810

-1475

-1810

IlL

Input LOW Current

0.5

, -

0.5

VIN = VIH(max)

-1610

orVIL(min)

-880

-1475

JlA

VIN = VIL1000V ESD Protection

PLASTIC SOIC PACKAGE
CASE 751-05

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

8 VCC

PIN DESCRIPTION

VBB

FUNCTION

D
Q
VBB

Data Inputs
Data Outputs
Ref. Voltage Output

VEE

12/93

3-20

REV 2

MOTOROLA

MC1 OEL 16 MC1 OOEl 16
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-40°C
Symbol

Characteristic

Min

lEE

Power Supply
Current

10EL
100EL

VBB

Output Reference
Voltage

10EL -1.43
100EL -1.38

VEE

Power Supply
Voltage

10EL -4.75
100EL -4.20

IIH

Input HIGH Current

O°C

Typ

Max

18
18

22
22

-5.2
-4.5

Min

-1.30
-1.26

-1.38
-1.38

-5.5
-5.5

-4.75
-4.20

Max

18
18

22
22

-5.2
-4.5

85°C

25°C

Typ

Min

-1.27
-1.26

-1.35
-1.38

-5.5
-5.5

-4.75
-4.20

150

Typ

Max

18
18

22
22

-5.2
-4.5

Min

-1.25
-1.26

-1.31
-1.38

-5.5
-5.5

-4.75
-4.20

Typ

Max

Unit

18
21

22
26

rnA

-1.19
-1.26

-5.5
-5.5

150

jlA

Unit

-5.2
-4.5

150

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-40°C
Symbol

O°C

25°C

85°C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

tpLH
tpHL

Propagation Delay
to Output
(Diff)
(SE)

125
75

250
250

375
425

175
125

250
250

325
375

175
125

250
250

325
375

205
155

280
280

355
405

tSKEW

Duty Cycle Skew1 (Diff)

Vpp

Minimum Input SWing2

150

VCMR

Common Mode Range3

-0.4

tr
tf

Output Rise/Fall Times Q
(20%-80%)

100

5
150

225

See3

-0.4

350

100

150

225

See 3

-0.4

350

100

150

225

See3

-0.4

350

100

ps
mV

225

See3

350

1. Duty cycle skew IS the difference between a TPLH and TPHL propagallon delay through a device.
2. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of =40.
3. The CMR range is referenced to the most positive side olthe differential input signal. Normal operation is obtained ilthe HIGH level falls within
Ihe specified range and Ihe peak-Io-peakvoltage lies between Vppmin and IV. The lower end oflhe CMR range is dependent on VEE and is
equal 10 VEE + 2.5V.

ECLinPS and ECLinPS Lile
DL140-Rev4

3-21

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low-Voltage Quad
Differential Receiver

MC100EL17

For information on the MC100EL 17,
please refer to the MC100LVEL 17
datasheet on page 4-27 in
Chapter 4 of this book.

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

MOTOROLA

3-22

ECLinPS and ECLinPS Lite
OL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual Differential Data and Clock
D Flip-Flop With Set and Reset

For information on the MC100EL29,
please refer to the MC100LVEL29
datasheet on page 4-29 in
Chapter 4 of this book.

MC100EL29

20"
1

OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

ECLinPS and ECLinPS Lite
0L140-Rev4

3-23

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple D Flip-Flop
With Set and Reset

MC100EL30

For information on the MC100EL30,
please refer to the MC100LVEL30
datasheet on page 4-31 in
Chapter 4 of this book.

OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-04

MOTOROLA

3-24

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

D Flip-Flop
With Set and Reset

MC10EL31
MC100EL31

The MCl OEUl OOEL3l is a D flip-flop with set and reset. The device is
functionally equivalent to the E13l device with higher performance
capabilities. With propagation delays and output transition times
significantly faster than the E13l the EL3l is ideally suited for those
applications which require the ultimate in AC performance.
Both set and reset inputs are asynchronous, level triggered signals.
Data enters the master portion of the flip-flop when clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock.
• 475ps Propagation Delay

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 2.8GHz Toggle Frequency
• 75kQ Internal Input Pulldown Resistors
• > 1OOOV ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

s
TRUTH TABLE

o
eLK

elK

L
H

L
L
H
L
H

L
L
L
H
H

Z
Z
X
X
X

L
H

X
X
X

12193

3-25

REV 2

H
L
Undef

=LOW to HIGH Transition

MOTOROLA

MC10EL31 MC100EL31
DC CHARACTERISTICS (VEE = VEE (min) to VEE(max); Vee = GND)
-40'C
Symbol

Characteristic

Min

lEE

Power Supply
Current

10El
100El

VEE

Power Supply
Voltage

10El -4.75
100El -4.20

IIH

Input HIGH Current

O'C

Typ

Max

27
27

32
32

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

AC CHARACTERISTICS (VEE = VEE(min)

27
27

32
32

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

Typ

Max

27
27

32
32

-5.2
-4.5

-5.5
-S.5

-4.75
-4.20

Typ

Max

Unit

27
31

32
37

-5.2
-4.5

-5.5
-5.5

150

!lA

to VEE(max); Vee = GND)

Min

Typ

2.0

2.5

315
295

465
455

2S'C

O'C
Max

Min

Typ

2.2

2.8

365
345

465
455

Max

Min

Typ

2.2

2.8

375
355

475
465

fMAX

Maximum Toggle
Frequency

tplH
tpHl

Propagation Delay
to Output

ts
IH

Setup Time
Hold Time

150
250

0
100

150
250

0
100

150
250

0
100

tRR

Set/Reset Recovery

400

200

400

200

400

200

tpw

Minimum Pulse Width
ClK, Set, Reset

400

Ir
tf

Output Rise/Fall Times Q
(20%-80%)

100

MOTOROLA

Min

150

-40'C
Characteristic

Symbol

Max

150

8S'C

2S'C

Typ

8S'C
Max

Min

Typ

2.2

2.8

430
400

530
510

150
250

0
100

400

200

Max

Unit
GHz
ps

ClK
S,R

630
630

580
580

400

400
225

350

100

590
590

225

3-26

350

100

645
645
ps
ps

400
225

350

100

ps
225

350

ECLinPS and ECLinPS Lite
Dl140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

+2 Divider

MC10EL32
MC100EL32

The MC10EU100El32 is an integrated +2 divider. The differential
clock inputs and the VBB allow a differential, single-ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a O.01I!F capacitor. Also note that the VBB is designed to be
used as an input bias on the El32 only, the VBB output has limited current
sink and source capability.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random state; the reset
allows for the synchronization of multiple El32's in a system.

••

• 510ps Propagation Delay
• 3.0GHz Toggle Frequency
• High Bandwidth Output Transitions

o SUFFIX

• 75kQ Internal Input Pulldown Resistors

PLASTIC SOIC PACKAGE
CASE 751-05

o >1000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION

VBB

VEE

FUNCTION

ClK
Reset
VBB

Clock Inputs
Asynch Reset
Ref Voltage Output
DataOuputs

5195

3-27

REV3

MOTOROLA

MC10EL32 MC100EL32
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
DOC

-4DOC
Symbol

Charactarlstic

Min

Typ

Max
30
30

lEE

Power Supply
Current

1DEL
100EL

25
25

VEE

Power Supply
Voltage

10EL
l00EL

--5.2
-4.5

Vee

Output Reference 10EL -1.43
Voltage
100EL -1.38

IIH

Input HIGH Current

AC CHARACTERISTICS (VEE

Min

-4.75
-4.20

30
30

-5.2
-4.5

--5.5
--5.5

Min

-4.75
-4.20

Typ

Max

25
25

30
30

--5.2
-4.5

--5.5
-5.5

-1.27 -1.35
-1.26 -1.38

Min

-4.75
-4.20

Typ

Max

Unit

25
29

30
35

--5.2
-4.5

--5.5
--5.5

-1.19
-1.26

150

!1A

-1.25 -1.31
-1.26 -1.38
150

150

=VEE(min) to VEE(max); Vee = GND)

Characteristic

Min

Typ

2.2

3.0

500
540

IMAX

Maximum Toggle
Frequency

tPLH
tpHL

Propagation Delay
CLKtoQ
ResettoQ

360
390

Vpp

Minimum Input Swing1

150

tr
tl

Output Rise/Fall Times Q
(20%-80%)

100

25
25

150

-4DOC
Symbol

Max

-1.30 -1.38
-1.26 -1.38

05°C

25°C

Typ

DOC
Max

640
690

Min

Typ

2.6

3.0

410
440

500
540

590
640

350

100

Min

Typ

2.6

3.0

420
440

510
540

Max

600
640

150

150
225

OsoC

25°C
Max

225

350

100

Min

Typ

2.6

3.D

450
450

540
550

Max

630
650

150
225

350

100

Unit
GHz

ps
mV

225

350

..
Minimum Input sWing lor which AC parameters are guaranteed.

elK

RESET

Figure 1. Timing Diagram

MOTOROLA

3-28

ECLinPS and ECLinPS Lite
OL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

+4 Divider

MC10EL33
MC100EL33

The MC10EU100EL33 is an integrated +4 divider. The differential
clock inputs and the VBB allow a differential, single-ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a 0.01!!F capacitor. Also note that the VBB is designed to be
used as an input bias on the EL33 only, the VBB output has limited current
sink and source capability.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the reset
allows for the synchronization of multiple EL33's in a system.
• 650ps Propagation Delay
• 4.0GHz Toggle Frequency
• High Bandwidth Output Transitions
DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 75kO Internal Input Pulldown Resistors
• >1 OOOV ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION

VBB

FUNCTION

CLK
Reset
VBB
Q

Clock Inputs
Asynch Reset
Ref Voltage Output
DataOuputs

5195

3-29

REV3

MOTOROLA

MC10EL33 MC100EL33
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee = GND)
-4D'C

Symbol

Characteristic

Min

D'C

Typ

Max
33
33

lEE

Power Supply
Current

10EL
lDOEL

27
27

VEE

Power Supply
Voltage

10EL
100EL

-5.2
-4.5

VBB

Output Reference 10EL -1.43
Voltage
100EL -1.38

IIH

Input HIGH Current

Min

-4.75
-4.20

25'C

Typ

Max

27
27

33
33

-5.2
-4.5

-5.5
-5.5

-1.30 -1.38
-1.26 -1.38

Min

-4.75
-4.20

Max

27
27

33
33

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

Typ

Max

Unit

27
31

33
37

-5.2
-4.5

-5.5
-5.5

-1.19
-1.26

150

IlA

Max

Unit

-1.25 -1.31
-1.26 -1.38

-1.27 -1.35
-1.26 -1.38

150

85'C

Typ

150

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-4D'C
Symbol

Characteristic

Min

Typ

3.4

4.2

630
460

fMAX

Maximum Toggle
Frequency

tpLH
tpHL

Propagation Delay
CLKtoQ
ResettoQ

490
310

Vpp

Minimum Input Swing1

150

25'C

D'C
Max

770
610

Min

Typ

3.8

4.2

540
360

630
460

Max

720
560

150

Min

Typ

3.8

4.2

550
360

640
460

85'C
Max

730
560

225

350

100

Typ

3.8

4.2

590
380

670
480

GHz

760
580

150

Output Rise/Fall Times Q
100
225
350
100
tr
(20%-80%)
tf
..
1. Minimum Input sWing for which AC parameters are guaranteed.

Min

225

350

100

ps
mV

225

350

elK

RESET

i
i r - - lI~-+--------+I---i
--+--------~--------~I~I
~

L...---_----'nL..-_--'

Figure 1. Timing Diagram

MOTOROLA

3-30

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

+2, +4, +8 Clock
Generation Chip

MC10EL34
MC100EL34

The MCl 0/1 00El34 is a low skew +2, +4, +8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECl or, if positive power supplies are used,
PECl input signal. In addition, by using the VSS output, a sinusoidal
source can be AC coupled into the device (see Interfacing section of the
ECLinPSTM Data Sook Dl140/D). If a single-ended input is to be used, the
VSS output should be connected to the ClK input and bypassed to ground
via a 0.01 JlF capacitor. The VSS output is designed to acl as the switching
reference for the input of the El34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.

DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05

The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the intemal clock is already in the
lOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple El34s in a system.
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kn Internal Input Pulldown Resistors
• >1000V ESD Protection

PIN DESCRIPTION
PIN

FUNCTION

ClK
EN
MR
VSS
00
01
02

Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff +2 Outputs
Diff +4 Outputs
Diff +8 Outputs
FUNCTION TABLE

LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC

ClK

Vss

ClK

Divide

Hold 00-3

FUNCTION

ResetOa-s

Z = low-to-Hlgh TranSItion
ZZ = High-to-low Transition

VCC

12193

REV2

MOTOROLA

MC10EL34 MC100EL34
AClDe CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-40'C
Characteristic

Symbol

Min

Typ

25'C

O'C
Max

Typ

Max

1100

Min

Typ

85'C
Max

Typ

Max

Max Toggle Frequency

lEE

Power Supply
Current

Vee

Output Reference 10EL -1.43
Voltage
100EL -1.38

IIH

Input High Current

tpLH
tpHL

Propagation CLK....OO
Delay to
CLK....01.2
Output
MR....O

tSKEW

Within-Device Skew

Setup Time EN

400

Hold Time EN

250

Vpp

Minimum Input Swing
ClK

250

VCMR

Common Mode Range
ClK

-2.0

-0.4

-2.0

--{).4

-2.0

--{).4

-2.0

--{).4

275

525

275

525

275

525

275

525

39
39

10EL
100EL

Output Rise/Fall Times Q
(20%-80%)

1100

Min

fMAX

tr
tf

1100

Min

1100

39
39

-1.30 -1.38
-1.26 -1.38

-1.27 -1.35
-1.26 -1.38

150

960
900
750

1200
1140
1060

960
900
750
100

100

-1.25 -1.31
-1.26 -1.38

960
900
750

970
910
790

100

Unit
MHz

39
42

rnA

-1.19
-1.26

150

1210
1150
1090

100

ps
ps
ps
mV

250

250
V

[IJ

Internal Clock
Disabled

ClK

Internal Clock
Enabled

00
01
02

---1

EN
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of ClK after its assertion. The internal dividers will maintain their state
dunng the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same
manner. time and relationship as they would have had the EN signal not been asserted.

Figure 1_ Timing Diagram

MOTOROLA

3-32

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

JK Flip-Flop

MC10EL35
MC100EL35

The MC1 OEU1 OOEL35 is a high speed JK flip-flop. The J/K data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The reset pin is asynchronous and is activated with a logic
HIGH.
o 525ps Propagation Delay
o 2.2GHz Toggle Frequency
o High Bandwidth Output Transitions
o 75k.Q Internal Input Pulldown Resistors
o >1000V ESD Protection
D SUFFIX

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

1°

Vee

PLASTIC SOIC PACKAGE
CASE 751-05

elK

TRUTH TABLE

elK

Qn+1

L
L
H
H

L
H
L
H

Z
Z
Z
Z

L
L
L
L
H

an
L
H
an
L

Z = LOW to HIGH TransItion

12193

3-33

REV 2

MOTOROLA

MC10EL35 MC100EL35
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
DOC

-4DOC
Symbol

Characterisilc

Min

Typ

Max
32
32

lEE

Power Supply
Current

10El
100El

27
27

VEE

Power Supply
Voltage

10El
100El

-5.2
-4.5

IIH

Input HIGH Current

Min

-4.75
-4.20

fMAX
tPlH
IpHl

Propagation Delay
100uiput

32
32

-5.2
-4.5

-5.5
-5.5

-4.75
-4.20

85°C

Typ

Max

27
27

32
32

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

Typ

Max

Unit

27
32

32
37

-5.2
-4.5

-5.5
-5.5

150

!lA

150

=VEE(min) to VEE(max); Vee = GND)

Characteristic
Maximum Toggle
Frequency

27
27

Min

150

DOC

-4DOC
Symbol

Max

150

AC CHARACTERISTICS (VEE

25°C

Typ

ClK
MR

Min

Typ

1.4

2.0

290
225

515
450

Max

740
675

Min

Typ

1.8

2.2

340
275

515
450

25°C
Max

690
625

Min

Typ

1.8

2.2

350
275

525
450

85°C
Max

700
625

Min

Typ

1.8

2.2

395
350

570
525

Max

Unit
GHz

745
700

SelupTime

J, K

150

Hold Time

J, K

250

100

250

100

250

100

250

100

IRR

Reset Recovery

400

200

400

200

400

200

400

200

IpW

Minimum Pulse Widlh
ClK, Resel

400

Ir
If

OUlput Rise/Fall Times Q
(20%-80%)

100

MOTOROLA

400
225

350

100

400
225

3-34

350

100

400
225

350

100

ps
225

350

ECLinPS and ECLinPS Lile
Dl140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

+2, +4/6 Clock Generation Chip

MC100EL38

For information on the MC100EL38,
please refer to the MC100LVEL38
datasheet on page 4-35 in
Chapter 4 of this book.

20~
1

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

ECLinPS and ECLinPS Lite
DL140-Rev4

3-35

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

+2/4, +4/6 Clock
Generation Chip

MC100EL39

For information on the MC 100EL39,
please refer to the MC100LVEL39
datasheet on page 4-39 in
Chapter 4 of this book.

20~
1

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D·04

MOTOROLA

3-36

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Differential Clock D Flip-Flop

MC10EL51
MC100EL51

The MC10EU100EL51 is a differential clock D flip-flop with reset. The
device is functionally similar to the E151 device with higher performance
capabilities. With propagation delays and output transition times
significantly faster than the E151 the EL51 is ideally suited for those
applications which require the ultimate in AC performance.
The reset input is an asynchronous, level triggered signal. Data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs of the EL51 allow the device to be
used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under
open input (pulled down to VEE) conditions .
• 475ps Propagation Delay

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

o 2.8GHz Toggle Frequency
o 75k.Q Internal Input Pulldown Resistors

• >1000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

R 1
R
D 2 i------i D

TRUTH TABLE

VEE

eLK

Z = LOW to HIGH Transition

12/93

3--37

REV 2

MOTOROLA

MC10EL51 MC100EL51
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
DOC

-4DOC
Symbol

Characteristic

Min

lEE

Power Supply
Current

10EL
100EL

VEE

Power Supply
Voltage

10EL
100EL

IIH

Input HIGH Current

-4.75
-4.20

Typ

Max

24
24

29
29

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

25°C

Typ

Max

24
24

29
29

-5.2
-4.5

-5.5
-5.5

150

Min

-4.75
-4.20

85°C

Typ

Max

24
24

29
29

-5.2
-4.5

-5.5
-5.5

150

Min

-4.75
-4.20

Typ

Max

Unit

24
30

29
36

rnA

-5.2
-4.5

-5.5
-5.5

150

ItA

150

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-4DOC
Symbol

Characteristic

fMAX

Maximum Toggle
Frequency

tpLH
tpHL

Propagation Delay
to Output

Min

Typ

1.8

2.8

325
305

465
455

DOC
Max

Min

Typ

2.2

2.8

375
355

465
455

25°C
Max

Min

Typ

2.2

2.8

385
355

475
465

85°C
Max

Min

Typ

2.2

2.8

440
410

530
510

Max

Unit
GHz
ps

CLK
R

605
605

555
555

565
565

620
620

Setup TIme

150

Hold TIme

250

100

250

100

250

100

250

100

tRR

Reset Recovery

400

200

400

200

400

200

400

200

tpw

Minimum Pulse Width
CLK, Reset

400

VPP

Minimum Input Swing 1

150

VCMR

Common Mode Range2

-0.4

tr
tf

Output Rise/Fall Times Q
(20%-80%)

100

400

400
150

225

See2

-0.4

350

100

400

150

225

See2

-0.4

350

100

150

225

See2

-0.4

350

100

225

See2

350

1. Minimum input swing for which AC parameters are guaranteed.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained ifthe HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 2.5V.

MOTOROLA

3-38

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Differential Data and
Clock D Flip~Flop

MC10EL52
MC100EL52

The MC1 OEU1 OOEl52 is a differential data, differential clock D flip-flop
with reset. The device is functionally equivalent to the E452 device with
higher performance capabilities. With propagation delays and output
transition times significantly faster than the E452 the El52 is ideally
suited for those applications which require the ultimate in AC
performance.
Data enters the master portion of the flip-flop when the clock is lOW
and is transferred to the slave, and thus the outputs, upon a positive
transition of the clock. The differential clock inputs of the El52 allow the
device to also be used as a negative edge triggered device.
The El52 employs input clamping circuitry so that under open input
conditions (pulled down to VEE) the outputs of the device will remain
stable.

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 365ps Propagation Delay
• 2.0GHz Toggle Frequency
• 75k.Q Internal Input Pulldown Resistors
PIN DESCRIPTION

• >1000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

FUNCTION

D
ClK

Data Input
Clock Input
Data Output

8 Vee

TRUTH TABLE

7 Q

3-39

ClK

Z = lOW to HIGH Transition

VEE

12193

REV2

MOTOROLA

MC10EL52 MC100EL52
DC CHARACTERISTICS (VEE = VEE(min) 10 VEE(max); Vee = GND)
-4DOC
Symbol

Characteristic

Min

lEE

Power Supply
Current

10EL
100EL

VEE

Power Supply
Voltage

10EL -4.94
100EL -4.20

IIH

Input HIGH Current

DOC

Typ

Max

21
21

25
25

-5.2
-4.5

-5.5
-5.5

Min

-4.94
-4.20

25°C

Typ

Max

21
21

25
25

-5.2
-4.5

-5.5
-5.5

150

Min

-4.75
-4.20

85°C

Typ

Max

21
21

25
25

-5.2
-4.5

-5.5
-5.5

150

Min

-4.75
-4.20

Typ

Max

Unit

21
24

25
29

rnA

-5.2
-4.5

-5.5
-5.5

150

IlA

150

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
DOC

-4DOC
Symbol

j::haracterlstlc

fMAX

Maximum Toggle
Frequency

tpLH
tpHL

Propagation Delay
to Output

Min

Typ

1.8

2.5

225

335

Max

515

Min

Typ

2.2

2.8

275

365

25°C
Max

465

Min

Typ

2.2

2.8

275

365

85°C
Max

465

Min

Typ

2.2

2.8

320

410

Max

Unit
GHz

510

CLK

Setup lime

125

Hold lime

150

tpw

Minimum Pulse Width

400

Vpp

Minimum Input Swing 1

150

VCMR

Common Mode Range2
(10EL)
(100EL)
CLK(10EL)
CLK(100EL)

tr
tf

o
o

Output Rise/Fall limes Q
(20%-80%)

-D.4

-D.4
-D.6
-D.8
100

225

-1.6
-1.2
See3
See3

-D.4
-D.4

350

100

-D.6
-D.8
225

-1.6
-1.2
See3
See3

-D.4
-D.4

350

100

-D.6
-D.8
225

-1.6
-1.2
See3
See3

-D.4
-D.4

350

100

V
-1.6
-1.2
See3
See3

-D.6
-D.8
225

350

1. Minimum input swing for which AC parameters are guaranteed.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV.
3. The lower end of the CMR range is dependent on VEE and is equal to VEE + 2.5V.

MOTOROLA

3-40

ECLinPS and ECLinPS Lite
OL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual Differential
2: 1 Multiplexer

MC100EL56

For information on the MC100EL56,
please refer to the MC100LVEL56
datasheet on page 4-44 in
Chapter 4 of this book.

20~
1

OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

ECLinPS and ECLinPS Lite
DL140-Rev4

3-41

MOTOROLA

MOTOROLA
SEMICONDUCTOR TEGHNICAL DATA

4:1 Differential Multiplexer

MC10EL57
MC100EL57

. The MCl Oil 00ELS7 is a fully differential 4:1 multiplexer. By leaving the
SEL 1 line" open (pulled LOW via the input pulldown resistors) the device
can also be used as a differential 2:1" multiplexer with SELO input
selecting between DO and Dl. The fully differential architecture of the
ELS7 makes it ideal for use in low skew applications such as clock
distribution.
The SELl is the most significant select line. The binary number applied
to the select inputs will select the same numbered data input (i.e., 00
selects DO).
Multiple VBB outputs are .provided for single-ended or AC coupled
interfaces. In these scenarios. "the VBB output should be connected to the
data bar inputs and bypassed via a 0.01 fLF capacitor to ground. Note that
the VBB output can sourcelsink up to O.SmA of current without upsetting
the voltage level.

DSUFFIX
PLASTIC SOIC PACKAGE
CASE 7S1 B-OS

• Useful as Either 4:1 or 2:1 Multiplexer
• VBB Output for Single-Ended Operation
• 7Sk.Q Internal Input Pulldown Resistors
• > 1OOOV ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Vee

SELO SELl

VBBI VBB2

PIN DESCRIPTION
PIN

FUNCTION

DO-3
SELO,l
VBB

Diff Data Inputs
Mux Select Inputs
Reference Output
Data Outputs

VEE

FUNCTION TABLE

SELl

SELO

DATA OUT

L
L

H
H

DO
Dl
D2
D3

ABSOLUTE MAXIMUM RATINGSl
Symbol

Characteristic

=OV)
Input Voltage (VCC =OV)

lout

Output Current

VEE

Power Supply (VCC

Continuous
Surge

Rating

Unit

-8.0toO

VDC

o to-6.0

VDC

SO
100

Operating Temperature Range

-40 to +8S

°c

VEE

Operating Range1,2

-5.7to-4.2

1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at:
10EL Series:
-4.94V to -S.SOV
1OOEL Series:
-4.20V to -S.SOV

1195

3-42

REVI

MOTOROLA

MC10EL5? MC100El5?
10EL SERIES
DC CHARACTERISTICS (VEE = VEE(min) - VEE(max); Vee = GND1)
-40°C
Symbol

Characteristic

O°C

25°C

85°C

Min

Max

Min

Max

Min

Max

Min

Max

Unit

VOH

Output HIGH Voltage

-1080

-890

-1020

-840

-980

-810

-910

-720

VOL

Output lOW Voltage

-1950

-1650

-1950

-1630

-1950

-1630

-1950

-1595

VIH

Input HIGH Voltage

-1230

-890

-1170

-840

-1130

-810

-1060

-720

Vil

Input lOW Voltge

-1950

-1500

-1950

-1480

-1950

-1480

-1950

-1445

III

Input lOW Current

0.5

0.3

J.lA

. .

1. 1OEl CircUits are deSigned to meet the DC specifications shown In the table aiter thermal eqUilibrium has been established. The circUit IS In
a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputfl are terminated through
a 50n resistor to -2.0V except where otherwise specified on the individual data sheets.

100EL SERIES
DC CHARACTERISTICS (VEE = VEE(min) - VEE(max); Vee = GND1)
-4DOC
Symbol

Characteristic

O°Cto 85°C

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage

-1085

-1005

-880

-1025

-955

-880

VIN

VOL

Output lOW Voltage

-1830

-1695

-1555

-1810

-1705

-1620

orVll(min)

VOHA

Output HIGH Voltage

-1095

-1035

VIN

VOLA

Output lOW Voltage

-1555

-1610

orVll(min)

-880

-1165

-1475

-1810

0.5

VIH

Input HIGH Voltage

-1165

Vil

Input lOW Voltge

-1810

III

Input lOW Current

0.5

-880

-1475

J.lA

Condition

VIN

=VIH(max)
=VIH(max)

=VILQJQ
Delay
SEl->QJQ

tSKEW

Input Skew Dn. Dm to Q

Vpp

Minimum Input Swing
ClK

250

VCMR

Common Mode Range
ClK

-2.0

-0.4

-2.0

-0.4

-2.0

-0.4

-2.0

-0.4

125

375

125

375

125

375

125

375

Output Rise/Fall Times Q
(20%-80%)

ECLinPS and ECLinPS Lite
DL140-Rev4

55D
690

350
440

550
690

100

150

Max

IIH

350
440

150

-1.25 -1.31
-1.26 -1.38

Typ

tPlH
tpHl

tr
tf

15D

Typ

360
440

560
690

3BO
460

100

ps
mV

250

250
V

3-43

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2:1 Multiplexer

MC10EL58
MC100EL58

The MC10EU100EL58 is a 2:1 multiplexer. The device is functionally
equivalent to the E158 device with higher performance capabilities. With
propagation delays and output transition times significantly faster than
the E158 the EL58 is ideally suited for those applications which require
the ultimate in AC performance.
• 230ps Propagation Delay
• High Bandwidth Output Transitions
• 75k!:! Internal Input Pulldown Resistors

DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• >1000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

NC 1

FUNCTION TABLE

VCC
SEL

. Da

7 Q

1-----1

Data

MUX
Db

SEL

PIN DESCRIPTION

3 1---..,--1 0

1-------'

FUNCTION

DO,Dl
Q

Data Inputs
Data Outputs

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
-4DOC
Symbol

Characteristic

Min

lEE

Power Supply
Current'

10EL
100EL

VEE

Power Supply
Voltage

10EL -4.94
100EL -4.20

IIH

Max

14
14

17
17

~.2

~.5
~.5

-4.5

Input HIGH Current

AC CHARACTERISTICS (VEE

DOC

Typ

Min

-4.94
-4.20

25°C

Typ

Max

14
14

17
17

~.2

-5.5
-5.5

-4.5

150

Min

-4.75
-4.20

85°C

Typ

Max

14
14

17
17

-5.2
-4.5

-5.5
-5.5

Min

-4.75
-4.20

Typ

Max

Unit

14
16

17
19

rnA

~.2

-5.5
-5.5

150

Unit

-4.5

150

=VEE(min) to VEE(max); VCC = GND)
-4DOC

DOC

25°C

85°C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

tpLH
tpHL

Propagation Delay
DtoO
to Output
SELtoO

60
90

220
250

380
410

110
140

220
250

330
360

120
150

230
260

340
370

140
170

250
280

360
390

tr
tf

Output Rise/FaliTtmes 0
(20%-80%)

100

225

350

100

225

350

100

225

350

100

225

350

Symbol

12193

3-44

REV2

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple 2:1 Multiplexer

MC100EL59

For information on the MC100EL59,
please refer to the MC100LVEL59
datasheet on page 4-47 in
Chapter 4 of this book.

OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

ECLinPS and ECLinPS Lite
0L140-Rev4

3-45

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Coaxial Cable Driver

MC10EL89

The MC10ELJ100El89 is a differential fanout gate specifically
designed to drive coaxial cables. The device is especially useful in Digital
Video Broadcasting applications; for this application, since the system is
polarity free, each output can be used as an idependent driver. The driver
boasts a gain of approximately 40 and produces output swings twice as
large as a standard ECl output. When driving a coaxial cable, proper
termination is required at both ends of the line to minimize signal loss. The
1.6V output swings allow for termination at both ends of the cable, while
maintaining the required 800mV swing at the receiving end of the cable.
Because of the larger, output swings, the device cannot be terminated into
to
the standard -2.0V. All of the DC parameters are tested with a
-3.0V load. The driver accepts a standard differential ECl input and can
run off of the Digital Video Broadcast standard -5.0V supply.

son

• 375ps Propagation Delay
o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 1.6V Output Swings
• 75kn Internal Input Pulldown Resistors
• >1000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION

FUNCTION

D
00,01

Data Inputs
Data Outputs

12193

3-46

REV2

MOTOROLA

MC10EL89
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-40'C
Symbol

Characteristic

Min

O'C

Typ

Max

Min

25'C

Typ

Max

Min

85'C
Typ

Max

Unit

-1.06

-0.96

-0.81

-2.56

-3.05

-2.67

-2.51

-5.5

-4.75

-5.5

150

f1A

Typ

Max

Min

lEE

Power Supply Current

VOH

Output HIGH Voltagel

-1.23

-1.10 -0.98 -1.17 -1.05

-0.93

-1.13

-1.02

-0.90

VOL

Output LOW Voltage1

-2.90

-2.72

-2.56

-3.00

-2.70

VEE

Power Supply Voltage

-4.75

-5.5

-4.75

-2.58 -3.00
-5.5

Input HIGH Current
"H
1. VOH and VOL specified for son to -3.0V load.

-2.70

-4.75

150

AC CHARACTERISTICS (VEE =VEE(min) to VEE(max); Vee
-40'C
Symbol

Characteristic

150

= GND)
D'C

25'C

85'C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

200

340

480

250

340

430

260

350

440

310

400

490

tpLH
tpHL

Propagation Delay to
Output

tSKEW

Within-Device Skew

Vpp

Minimum Input SWing l

150

VCMR

Common Mode Range2

-0.4

tr
tf

Output Rise/Fall TImes Q
(20%-80%)

205

150
See2

-0.4

455

205

330

150

330

See2

-0.4

455

205

150

330

See2

-0.4

455

205

330

See2

455

1. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of =40.
2. The CMR range is referenced to the most positive side olthe differential input signal. Normal operation is obtained ilthe HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range is dependent on VEE and is
equal to VEE + 2.5V.

DC BLOCKING CAPACITORS

75n

I
I
I
I
I

75nCOAX

0.1~75n

r-----------..,
EL89

75n
150n

150n

75nCOAX

0.1~75n

L __________ _

Figure 1. EL89 Termination Configuration

ECLinPS and ECLinPS Lile
DL140-Rev4

3-47

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple ECL to PECL Translator

MC100EL90

For information on the MC100EL90,
please refer to the MC100LVEL90
datasheet on page 4-49 in
Chapter 4 of this book.

20~
1

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-04

MOTOROLA

3-48

ECLinPS and ECLinPS Li1e
DL140- Rev 4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple PECL to ECL Translator

MC100EL91

For information on the MC100EL91,
please refer to the MC100LVEL91
datasheet on page 4-52 in
Chapter 4 of this book.

20~
1

OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

ECLinPS and ECLinPS Lite
0L140-Rev4

3-49

MOTOROLA

ECLinPS Lite Translators

MOTOROLA

3-50

ECLinPS and ECLinPS Lite
DL140- Rev 4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

TTL to Differential PECL
Translator

MC10ELT20
MC100ELT20

The MC10ElT/l00ElT20 is a TTL to differential PECl translator.
Because PECl (Positive ECl) levels are used only +5V and ground are
required. The small outline a-lead SOIC package and the single gate of
the ElT20 makes it ideal for those applications where space,
performance and low power are at a premium. Because the mature
MOSAIC 1.5 process is used, low cost can be added to the list of
features.
The ElT20 is available in both ECl standards: the 1OElT is compatible
with positive MECl 10H logic levels while the 100ElT is compatible with
positive ECl lOOK logiC levels.
• 1.5ns Typical Propagation Delay
o Differential PECl Outputs

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

o Small Outline SOIC Package
o PNP TTL Inputs for Minimal loading
• Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

NC 1

VCC

PIN DESCRIPTION

GND

FUNCTION

Q
D

Diff PECl Outputs
TTL Input
+5.0V Supply
Ground

Vec

GND

1195

3--51

REV2

MOTOROLA

MC10ELT20 MC100ELT20

MAXIMUM RATINGS'
Symbol

Parameter

VCC

DC Supply Voltage (Referenced to GND)

VIN

Input Voltage

lOUT

Current Applied to Output in Low Output State

Operating Temperature Range (In Free-Air)

TSTG

Storage Temperature Range

Symbol

Unit

7.0

OtoVCC

50
100

-40 to 85

'c
'c

Continuous
Surge

-55 to +150

• Maximum Ratings are those values beyond which damage to the device may occur.
Recommended Operating Conditions.

TTL INPUT DC CHARACTERISTICS (VCC

Value

Functional operation should be restricted to the

=4.75V to 5.25V; TA =-40°C to 85°C)

Characteristic

Min

Typ

Max

Unit

VIN=2.7V

100

VIN =7.0V

-0.6

VIN =0.5V

IIH

Input HIGH Current

IIHH

Input HIGH Current

IlL

Input LOW Current

-1.2

VIK
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

Condition

IIN=-18mA

2.0

0.8

PECl OUTPUT DC CHARACTERISTICS (VCC = 4.75V to 5.25V; TA = -40°C to 85°C)
-40'C

O'C

85'C

25'C

Characteristic

Min

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

Condition

VOH

Output HIGH 10ELT1
100ELT1
Voltage

3.920
3.915

4.11
4.12

3.980
3.975

4.16
4.12

4.020
3.975

4.10
4.05

4.19
4.12

4.080
3.975

4.27
4.12

VCC = 5.OV

VOL

Output LOW 10ELT1
100ELT1
Voltage

3.05
3.17

3.350
3.445

3.05
3.19

3.37
3.38

3.05
3.19

3.25
3.30

3.37
3.38

3.05
3.19

3.40
3.35

VCC=5.OV

Symbol

Power Supply Current
ICC
1. Levels Will vary 1:1 with VCC.

AC CHARACTERISTICS (Vcc = 4.75V to 5.25V; TA = -40'C to 85°C)
-40'C
Symbol

Characteristic
Propagation Delay1

tpLH

O'C

25'C

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

0.6

1.2

0.65

1.45

0.9

1.2

1.5

0.6

1.35

0.8

1.1

0.7

1.30

1.5

0.15

1.5

tPHL

Propagation Delay1

0.4

1.0

0.45

1.05

0.5

trllj

Output Rise/Fall TIme

0.15

1.5

0.15

1.5

0.15

fMAX

Maximum Input
Frequency

100

85°C

Min

100

Condition

20--80%

MHz

1. SpeCifications for standard TTL Input signal.

MOTOROLA

3-52

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Differential PECL to TTL
Translator

MC10ELT211
MC100ELT211

The MC10ELT/100ELT21 is a differential PECL to TTL translator.
Secause PECL (Positive ECL) levels are used only +5V and ground are
required. The small outline a-lead SOIC package and the single gate of
the ELT21 makes it ideal for those applications where space,
performance and low power are at a premium. Secause the mature
MOSAIC 1.5 process is used, low cost can be added to the list of
features.
The VSS output allows the ELT21 to also be used in a single-ended
input mode. In this mode the VSS output is tied to the TN input for a
non-inverting buffer or the IN input for an inverting buffer. If used the VSS
pin should be bypassed to ground via a O.01J.LF capacitor.
The ELT21 is available in both ECL standards: the 1OELT is compatible
with positive MECL 10H logic levels while the 100ELT is compatible with
positive ECL 100K logic levels.

••

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

o 3.5ns Typical Propagation Delay
o Differential PECL Inputs
o Small Outline SOIC Package
o 24mA TTL Output
o Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

VCC
PIN DESCRIPTION

FUNCTION

Q
D
VCC
VSS
GND

TTL Output
Diff PECL Inputs
+5.0V Supply
Reference Output
Ground

GND

VBB

7/96

3-53

REV3

MOTOROLA.

MC10ELT21 MC100ELT21

MAXIMUM RATINGS·
Symbol

Parameter

Value

VCC

DC Supply Voltage (Referenced to GND)

Operating Temperature Range (In Free-Air)

TSTG

Storage Temperature Range

• Maximum Ratings are those values beyond which damage to the device may occur.
Recommended Operating Conditions.

Unit

7.0

-40 to 85

°c

-55 to +150

°c

Functional operation should be restricted to the

TTL OUTPUT DC CHARACTERISTICS (Vee = 4.75V to 5.25V; TA = -40 o e to 85°C)
Symbol

Characteristic

VOH

Output HIGH Voltage

VOL

Output lOW Voltage

ICCH

Power Supply Current

Typ

Min

Max

Unit

2.4

IOH=-3·0mA

0.5

IOl=24mA

rnA

-60

rnA

ICCl

Power Supply Current

lOS

Output Short Circuit Current

22
-150

Condition

PECl INPUT DC CHARACTERISTICS (Vee = 4.75V to 5.25V; TA = -40 o e to 85°C)
DOC

-40°C
Symbol

Characteristic

IIH

Input HIGH Current

Min

Max

Min

25°C
Max

150

Min

Typ

150
0.5

85°C
Max

Min

150

Unit

150

I1A

III

Input lOW Current

0.5

Common Mode Range

2.2

Vpp

Minimum
Peak-ta-Peak Input1

200

VIH

Input HIGH
Voltage

10ELT
100ElT

3.770
3.835

4.110
4.120

3.830
3.835

4.16
4.12

3.870
3.835

4.19
4.12

3.930
3.835

4.265
4.120

VCC=5.0V

VIL

Input LOW
Voltage

10ElT
100ELT

3.05
3.19

3.500
3.525

3.05
3.19

3.520
3.525

3.05
3.19

3.520
3.525

3.05
3.19

3.550
3.525

VCC= 5.0V

VBB

Reference
Output

10ELT
100ELT

3.57
3.62

3.70
3.74

3.62
3.62

3.73
3.74

3.65
3.62

3.75
3.74

3.69
3.62

3.81
3.75

VCC= 5.0V

Max

Min

2.2

VCC

200

0.5

Condition

VCMR

VCC

0.5

Max

2.2

VCC

200

IIA

2.2

VCC

200

V
mV

1. 200mV Input guarantees full logic sWing at the output.

AC CHARACTERISTICS (Vee = 4.75V to 5.25V; TA = -40o e to 85°C)
DOC

-40°C

25°C

85°C
Max

Unit

tpLH

Propagation Delay1

2.0

5.5

2.0

5.5

2.0

5.5

2.0

5.5

CL= 20pF

tpHL

Propagation Delay1

2.0

5.5

2.0

5.5

2.0

5.5

2.0

5.5

CL=20pF

Symbol

Characteristic

MOTOROLA

Min

Max

Min

Max

Min

3--1;4

Typ

Condition

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual TTL to Differential
PECL Translator

MC10ELT22
MC100ELT22

The MC10ElT/100ElT22 is a dual TIL to differential PECl translator.
Because PECl (Positive ECl) levels are used only +5V and ground are
required. The small outline 8-lead SOIC package and the low skew, dual
gate design of the ElT22 makes it ideal for applications which require the
translation of a clock and a data signal. Because the mature MOSAIC 1.5
process is used, low cost can be added to the list of features.
The ElT22 is available in both ECl standards: the 1OElT is compatible
with positive MECl 10H logic levels while the 1OOElT is compatible with
positive ECl 100K logic levels.
• 1.5ns Typical Propagation Delay
• <300ps Typical Output to Output Skew
• Differential PECl Outputs

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• Small Outline SOIC Package
• PNP TIL Inputs for Minimal loading
• Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION
PIN

FUNCTION

an
On
VCC
GND

Diff PECl Outputs
TIL Inputs
+5.0V Supply
Ground

7/96

3-55

REV3

MOTOROLA

MC10ELT22 MC100ELT22

MAXIMUM RATINGS'
Symbol

Parameter

VCC

DC Supply Voltage (Referenced to GND)

VIN

Input Voltage

lOUT

Current Applied to Output in Low Output State

Operating Temperature Range (In Free-Air)

TSTG

Storage Temperature Range

Value

Unit

7.0

OtoVCC

50
100

Continuous
Surge

-40 to 85

°C

-55 to +150

°C

• Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.

TTL INPUT DC CHARACTERISTICS (VCC = 4.75V to 5.25V; TA = -40°C to 85°C)
Symbol

Min

Characteristic

IIH

Input HIGH Current

IIHH

Input HIGH Current

IlL

Input LOW Current

Typ

VIK
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

Max

Unit

20
100

IlA
IlA

VIN=7.0V

-0.6

VIN=0.5V

-1.2

2.0

IIN=-18mA

0.8

PECl OUTPUT DC CHARACTERISTICS (VCC

Condition
VIN =2.7V

=4.75V to 5.25V; TA =-40°C to 85°C)

-4D'C

25'C

D'C

85'C

Characteristic

Min

Max

Min

Max

Min

Typ

Max

Mtn

Max

Unit

Condition

VOH

Output HIGH 10ELT1
Voltage
100ELT1

3.920
3.915

4.11
4.12

3.980
3.975

4.16
4.12

4.020
3.975

4.10
4.05

4.19
4.12

4.090
3.975

4.28
4.12

VCC= 5.0V

VOL

Output LOW 10ELT1
100ELT1
Voltage

3.05
3.17

3.350
3.445

3.05
3.19

3.37
3.38

3.05
3.19

3.25
3.30

3.37
3.38

3.05
3.19

3.40
3.35

VCC= 5.0V

Symbol

Power Supply Current
ICC
1. Levels will vary 1.1 With VCC.

AC CHARACTERISTICS (VCC = 4.75V to 5.25V; TA = -40°C
-4D'C
Symbol

to 85°C)

D'C

25'C

85'C

Min

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

Propagation Delay1

0.6

1.2

0.65

1.45

0.9

1.2

1.5

0.6

1.35

tpHL

Propagation Delay1

0.4

1.0

0.45

1.05

0.5

0.8

1.1

0.7

1.30

trltf

Output Rise/Falilime

0.4

1.6

0.4

1.6

0.4

1.6

0.4

1.6

fMAX

Maximum Input
Frequency

100

tpLH

Characteristic

100

Condition

20-80%

MHz

1. Specifications for standard TTL ,"put signal.

MOTOROLA

3-56

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual Differential PECL to
TTL Translator

MC100ELT23

The MC100ElT23 is a dual differential PECl to TTL translator.
Because PECl (Positive ECL) levels are used only +5V and ground are
required. The small outline 8-lead SOIC package and the dual gate
design of the ElT23 makes it ideal for applications which require the
translation of a clock and a data signal. Because the mature MOSAIC 1.5
process is used, low cost can be added to the list of features.
The ElT23 is available in only the ECl lOOK standard. Since there are
no PECl outputs or an external VBB reference, the ElT23 does not
require both ECl standard versions. The PECl inputs are differential;
there is no specified difference between the differential input 10H and
lOOK standards. Therefore, the MC100ElT23 can accept any standard
differential PECl input referenced from a VCC of 5.0V.
DSUFFIX

• 3.5ns Typical Propagation Delay

PLASTIC SOIC PACKAGE
CASE 751-05

• Differential PECl Inputs
• Small Outline SOIC Package
• 24mA TTL Outputs
• Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION
PIN

FUNCTION

an
Dn
VCC
GND

TTL Outputs
Diff PECl Inputs
+5.0V Supply
Ground

7196

3-57

REV 3

MOTOROLA

MC100ELT23

MAXIMUM RATINGS'
Symbol

Value

Parameter

VCC

DC Supply Voltage (Referenced to GND)

Operating Temperature Range (In Free-Air)

TSTG

Storage Temperature Range

UnIt

7.0

-40 to 85

'c
'c

-55 to +150

• Maximum Ratings are those values beyond which damage to the device
Recommended Operating Conditions.

may

occur.

Functional operation should be restricted to the

TTL OUTPUT DC CHARACTERISTICS (Vee = 4.75V to 5.25V; TA = -40o e to 85°e)
Symbol

CharacteristIc

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

ICCH

Power Supply Current

MIn

ICCL

Power Supply Current

lOS

Output Short Circuit Current

IIH

Min

Input HIGH Current

IOH=-3.0mA

0.5

IOL=24mA

rnA

rnA
rnA

=4.75V to 5.25V; TA =-40 o e to 85°C)
DOC

--40'C
Characteristic

CondItIon

--60

26
-150

PECl INPUT DC CHARACTERISTICS (Vee

Symbol

UnIt

Max

Typ

2.4

Max

Min

25'C
Max

150

MIn

Typ

150

85'C
Max

Min

150

Max

Unit

150

Condition

IlL

Input LOW Current

0.5

VCMR

Common Mode Range

2.2

Vpp

Minimum
Peak-to-Peak Inputl

200

VIH

Input HIGH
Voltage

10ELT
100ELT

3.770
3.835

4.110
4.120

3.830
3.835

4.16
4.12

3.870
3.835

4.19
4.12

3.930
3.835

4.265
4.120

VCC= 5.0V

VIL

Input LOW
Voltage

10ELT
100ELT

3.05
3.19

3.500
3.525

3.05
3.19

3.520
3.525

3.05
3.19

3.520
3.525

3.05
3.19

3.550
3.525

VCC=5.0V

Max

MIn

0.5
VCC

0.5

0.5.

2.2

VCC

200

2.2

VCC

2.2

VCC

200

V
mV

1. 200mV Input guarantees full logiC sWing at the output.

AC CHARACTERISTICS (Vce = 4.75V to 5.25V; TA = -40°C to 85°G)
--4D'C
Symbol

D'C

25°C

85'C
Max

UnIt

tPLH

Propagation Delay1

2.0

5.5

2.0

5.5

2.0

5.5

2.0

5.5

CL=20pF

tpHL

Propagation DelayI

2.0.

5.5

2.0

5.5

2.0

5.5

2.0

5.5

CL=20pF

Characteristic

MOTOROLA

Min

Max

Min

Max

Min

Typ

CondItion

ECLinPS and ECLinPS Lite
DL140- Rev 4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

TTL to Differential ECL
Translator

MC10ELT24
MC100ELT24

The MC10ELT/l00ELT24 is a TTL to differential ECL translator.
Because ECL levels are used a +5V, -5.2V (or -4.5V) and ground are
required. The small outline 8-lead SOIC package and the single gate of
the ELT24 makes it ideal for those applications where space,
performance and low power are at a premium .. Because the mature
MOSAIC 1.5 process is used, low cost can be added to the list of
features.
The ELT24 is available in both ECL standards: the 1OELT is compatible
with MECL 10H logic levels while the 100ELT is compatible with ECL
100K logic levels.
• 1.2ns Typical Propagation Delay
o Differential PECL Outputs

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• Small Outline SOIC Package
• PNP TTL Inputs for Minimal Loading
• Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

VEE

VCC
PIN DESCRIPTION

GND

FUNCTION

Q
D
Vce
VEE
GND

Diff ECL Outputs
TTL Input
Positive Supply
Negative Supply
Ground

1195

3-59

REV2

MOTOROLA

MC10ELT24 MC100ELT24

MAXIMUM RATINGS'
Value

Unit

VCC

Symbol

DC Supply Voltage (Referenced'to GND, VCC = -5.2V)

7.0

VEE

DC Supply Voltage (Referenced to GND, VCC = 5.0V)

-B.O

VIN

Input Voltage

lOUT

Current Applied to Output in Low Output State

Operating Temperature Range (In Free-Air)

TSTG

Storage Temperature Range

Parameter

-40 to VCC

50
100

Continuous
Surge

• Maximum Ratings are those values beyond which damage to the device may occur.
Recommended Operating Conditions.

-40 to 85

°C

-55 to +150

°C

Functional operation should be restricted to the

TTL INPUT DC CHARACTERISTICS (Vee = 4.5V to 5.5V; VEE ='-4.2V to -5.5V 100ElT, -4.94V to -5.5V 10ElT;
TA = -40 oe to 85°C)
Symbol

Characteristic

Typ

Min

Max

Unit

j.tA

VIN=2.7V

Condition

IIH

Input HIGH Current

IIHH

Input HIGH Current

100

j.tA

VIN =7.0V

IlL

Input LOW Current

-0.6

VIN =0.5V

-1.2

VIK
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

2.0
0.8

ECl OUTPUT DC CHARACTERISTICS

Characteristic

(Vee = 4.5V to 5.5V; VEE = -4.2V to -5.5V 100ElT, -4.94V to -5.5V 10ElT;
TA = -40 oe to 85°e)

-40°C
Symbol

IIN=-18mA

25°C

O°C

Min

Max

Min

Max

Min

85°C

Typ

Max

Min

Max

Unit

-810
-1025

-720
-880

-1950
-1810

-1595
-1620

VOH

Output HIGH
Voltage

10ELT
l00ELT

-1080
-1085

-890
-880

-1020
-1025

-840
-880

-980
-1025

-855

-810
-880

VOL

Output LOW
Voltage

10ELT
100ELT

-1950
-1830

-1650
-1555

-1950
-1810

-1630
-1620

-1950
-1810

-1705

-1630
-1620

ICC

Power Supply Current

4.5

rnA

lEE

Power Supply Current

12.5

rnA

Condition

AC CHARACTERISTICS (Vee = 4.5V to 5.5V; VEE = -4.2V to -5.5V 100ElT, -4.94V to -5.5V 10ElT; TA = -40°C to 85°C)
-40°C
Symbol

Characteristic
Propagation Delay1

tpLH

O°C

25°C

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

0.7

1.3

0.65

1.25

0.65

0.95

1.25

0.65

1.25

0.80

1.10

0.70

1.30

1.25

0.25

1.25

tpHL

Propagation Delay1

0.4

1.0

0.45

1.05

0.50

trllf

Output Rise/Fall TIme

0.25

1.25

0.25

1.25

0.25

fMAX

Maximum Input
Frequency

100

85°C

Min

100

Condition

20-80%

MHz

1. Specifications for standard TIL Input signal.

MOTOROLA

3-80

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Differential EeL to TTL
Translator

MC10ELT25
MC100ELT25

The MC10ElT/l00ElT25 is a differential ECl to TIL translator.
Because ECl levels are used a +5V, -5.2V (or -4.5V) and ground are
required. The small outline a-lead SOIC package and the single gate of
the ElT25 makes it ideal for those applications where space,
performance and low power are at a premium. Because the mature
MOSAIC 1.5 process is used, low cost can be added to the list of
features.
The VBB output allows the ElT25 to also be used in a single-ended
input mode. In this mode the VBB output is tied to the TN input for a
non-inverting buffer or the IN input for an inverting buffer. If used the VBB
pin should be bypassed to ground via a 0.01 iJ.F capacitor.
The ElT25 is available in both ECl standards: the 1OElT is compatible
with MECl 10H logic levels while the 100ElT is compatible with ECl
lOOK logic levels.

DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 2.6ns Typical Propagation Delay
• Differential ECl Inputs
• Small Outline SOIC Package
o 24mA TIL Outputs
o Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

VEE

VBB

8 Vee

PIN DESCRIPTION
PIN

FUNCTION

D
Q
VCC
VEE
VBB
GND

Diff ECl Inputs
TIL Output
Positive Supply
Negative Supply
Reference Output
Ground

GND

1/95

3-61

REV 2

MOTOROLA

MC10ELT25 MC100ELT25

MAXIMUM RATINGS'
Value

Unit

VCC

Symbol

DC Supply Voltage (Referenced to GND. VEE = -5.2)

Parameter

7.0

VEE

DC Supply Voltage (Referenced to GND. VCC = 5.0)

-8.0

VIN

Input Voltage

lOUT

Current Applied to Output in low Output State

Operating Temperature Range (In Free-Air)

TSTG

Storage Temperature Range

TTL OUTPUT DC CHARACTERISTICS (VCC 4.5V to 5.5V; VEE
TA = -40°C to 85°C)
Characteristic

50
100

-40 to 85

°c

-55 to +150

°c

Continuous
Surge

• Maximum Ratings are those values beyond which damage to the device may occur.
Recommended Operating Conditions.

Symbol

OtoVCC

Functional operation should be restricted to the

=-4.2V to -5.5V 100ELT, -4.94V to -5.5V 1OELT;

Min

Typ

Max

Unit

VOH

Output HIGH Voltage

2.4

VOL

Output lOW Voltage

ICCH

Power Supply Current

ICCl

Power Supply Current

lEE

Power Supply Current

lOS

Output Short Circuit Current

-60

-150

DOC

-40°C

IIH

Characteristic

Min

Input HIGH Current

Max

Min

0.5

IOl=24mA

IlL

Input LOW Current
Common Mode Range

VEE +
2.2

Minimum Peak-ta-Peak

200

25°C
Max

150

VCMR
Vpp

IOH=-3.0mA

(Vcc = 4.5V to 5.5V; VEE = -4.2V to -5.5V 100ELT. -4.94V to -5.5V 1OELT;
TA = -40°C to 85°C)

ECl INPUT DC CHARACTERISTICS

Symbol

Condition

Typ

150

0.5

0.5
VCC

Min

85°C
Max
150

0.5

VEE +
2.2

VCC

200

Min

Max

Unit

150

J1A
J1A

VCC

0.5

VEE +
2.2

VCC

200

VEE +
2.2
200

Condition

Input1
Input HIGH Voltage 10ELT
100ELT

-1230
-1165

-890
-880

-1170
-1165

-840

-1130
-1165

-810
-880

-1060
-1165

-720
-880

-880

VIL

Input LOW Voltage lOELT
100ELT

-1950
-1810

-1500
-1475

-1950
-1810

-1480
-1475

-1950
-1810

-1480
-1475

-1950
-1810

-1445
-1475

Vee

Reference Output

lOELT
100ELT

-1.43
-1.38

-1.30
-1.26

-1.38
-1.38

-1.27
-1.26

-1.35
-1.38

-1.25
-1.26

-1.31
-1.38

-1.19
-1.26

VIH

1. 200mV Input guarantees full logIC sWing at the output.

AC CHARACTERISTICS (VCC =4.5V to 5.5V; VEE

=-4.2V to -5.5V 100ELT. -4.94V to -5.5V 1OELT; TA =-40°C to 85°C)

-40°C
Symbol

O°C

25°C

Characteristic

Min

Max

Min

Max

Min

tplH

Propagation Delay

1.7

3.6

1.7

3.6

tpHl

Propagation Delay

2.6

4.1

2.6

4.1

MOTOROLA

3-62

85°C
Max

Min

Max

Unit

1.7

3.6

1.7

3.6

CL =20pF

2.6

4.1

2.6

4.1

CL =20pF

Typ

Condition

ECLinPS and ECLinPS ltte
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview

MC10ELT26
MC100ELT26

1:2 Fanout Differential PECL
to TTL Translator
The MC10ElTI100ElT26 is a 1:2 fanout differential PECl to TTL
translator. Because PECl (Positive ECl) levels are used only +5V and
ground are required. The small outline S-Iead SOIC package and the 1:2
fanout design of the ElT23 makes it ideal for applications which require
the low skew duplication of a signal in a tightly packed PC board.
Because the mature MOSAIC 1.5 process is used, low cost can be added
to the list of features.

The VBB output allows the ElT26 to also be used in a single-ended
input mode. III this mode the VBB output is tied to the iN input for a
non-inverting buffer or the IN input for an inverting buffer. If used the VBB
pin should be bypassed to ground via a 0.01 J.lF capacitor.
The ElT26 is available in both ECl standards: the 1OElT is compatible
with positive MECl 10H logic levels while the 100ElT is compatible with
positive ECl 100K logic levels.

DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 3.5ns Typical Propagation Delay
• <500ps Typical Output to Output Skew
• Differential PECl Inputs
• Small Outline SOIC Package
• 24mA TTL Outputs
• Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN

FUNCTION

an
D
Vce
VBB
GND

TTL Outputs
Diff PECl Input
+5.0V Supply
Reference Output
Ground

This document contains information on a product under development. Motorola reseIV8S the right to
change or discontinue this product without notice.

1/95

REV 2

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Advance Information

MC10ELT28
MC100ELT28

TTL to Differential PECL/Differential PECL to TTL Translator
The MCl OElT/l OOElT28 is a differential PECl to TTL translator and a
TTL to differential PECl translator in a single package. Because PECl
(Positive ECl) levels are used only +5V and ground are required. The
small outline 8-lead SOIC package and the dual translation design of the
EI!.T28 makes it ideal for applications which are sending and receiving
signals across a backplane. Because the mature MOSAIC 1.5 process is
used, low cost can be added to the list of features.
The ElT28 is available in both ECl standards: the 1OElT is compatible
with positive MECl 10H logic levels while the 100ElT is compatible with
positive ECl lOOK logiC levels.
• 3.5ns Typical PECl to TTL Propagation Delay
• 1.2ns Typical TTL to PECl Propagation Delay

o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• Differential PECl InputslOuputs
• Small Outline SOIC Package
• PNP TTL Inputs for Minimal loading
• 24mA TTL Outputs
o Flow Through Pinouts

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION
PIN

FUNCTION

OTTl
DTTl
OECl
DECl
VCC
GND

TTL Output
TTL Inputs
Diff ECl Outputs
Diff ECl Inputs
+5.0V Supply
Ground

MAXIMUM RATINGS'
Symbol

Parameter

VCC

DC Supply Voltage (Referenced to GND)

Operating Temperature Range (In Free-Air)

TSTG

Storage Temperature Range

Value

Unit

7.0

-40 to 85

°c

-55 to +150

°C

Functional operation should be restricted to the

• Maximum Ratings are those values beyond which damage to the device may occur.
Recommended Operating Conditions.
This document contains information on a new product Specifications and information herein are subject to
change without notice.

1/95

3-64

REV2

MOTOROLA

MC10ELT28 MC100ELT28

TTL OUTPUT DC CHARACTERISTICS (Vee
Symbol

=4.75V to 5.25V; TA =-40 o e to 85°C)

Characteristic

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

ICCH

Power Supply Current

Min

Unit

Max

ICCL

Power Supply Current

lOS

Output Short Circuit Current

29
-150

TTL INPUT DC CHARACTERISTICS (Vee
Symbol

Typ

Condition

IOH=-3·0mA

0.5

IOL=24mA

2.4

-60

=4.75V to 5.25V; TA =-40 oe to 85°C)

Characteristic

Max

Unit

IIH

Input HIGH Current

Min

Typ

!lA

VIN=2.7V

IIHH

Input HIGH Current

100

flA

VIN=7.0V

IlL

Input LOW Current

-0.6

VIN = 0.5V

-1.2

VIK
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

2.0

PECl OUTPUT DC CHARACTERISTICS (Vee = 4.75V to 5.25V; TA

Symbol

IIN=-18mA

V
0.8

--4D'C

Condition

=-40 o e to 85°C)

D'C

2S'C

OS'C

Characteristic

Min

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

Condition

VOH

Output HIGH lDELTI
100ELTI
Voltage

3.920
3.915

4.11
4.12

3.980
3.975

4.16
4.12

4.020
3.975

4.10
4.05

4.19
4.12

4.080
3.975

4.27
4.12

VCC= 5.0V

VOL

Output LOW 10ELTI
100ELTI
Voltage

3.05
3.17

3.350
3.445

3.05
3.19

3.37
3.38

3.05
3.19

3.25
3.30

3.37
3.38

3.05
3.19

3.40
3.35

VCC= 5.0V

Max

Unit

Condition

150

!lA
!lA

1. Levels will vary 1:1 with VCC.

PECl INPUT DC CHARACTERISTICS (Vee = 4.75V to 5.25V; TA = -40 o e to 85°C)
--4D'C
Symbol

Characteristic

IIH

Input HIGH Current

IlL

Input LOW Current

Min

Max
150

0.5

OsoC

25°C

D'C
Min

Max

Min

Typ

150
0.5

Max

Min

150
0.5

0.5

VCMR

Common Mode Range

2.2

VPP

Minimum
Peak-to-Peak Input1

200

VIH

Input HIGH
Voltage

10ELT
100ELT

3.770
3.835

4.110
4.120

3.830
3.835

4.16
4.12

3.870
3.835

4.19
4.12

3.930
3.835

4.265
4.120

VCC= 5.0V

VIL

Input LOW
Voltage

10ELT
100ELT

3.05
3.19

3.500
3.525

3.05
3.19

3.520
3.525

3.05
3.19

3.520
3.525

3.05
3.19

3.550
3.525

VCC= 5.0V

tpLH

Prop
Delay

DECLtoQTTL
DTTLto QECL

2.0
0.6

5.5
1.2

2.0
0.65

5.5
1.45

2.0
0.9

5.5
1.5

2.0
0.6

5.5
1.35

CL=20pF

1.2

Prop
Delay

DECLtoQTTL
DTTLtoQECL

2.0
0.4

5.5
1.0

2.0
0.45

5.5
1.05

2.0
0.5

5.5
1.1

2.0
0.7

5.5
1.3

CL=20pF

0.8

Rise/Fall Times QECL

0.15

1.5

0.15

1.5

0.15

1.5

0.15

1.5

20%-80%

tpHL
tr,tf

VCC

2.2

VCC

200

2.2

VCC

200

2.2

VCC

V
mV

200

1. 200mV Input guarantees full logic sWing at the output.

ECLinPS aAd ECLinPS Lite
DL140-Rev4

3-65

MOTOROLA

3-66

High Performance Eel Data
ECLinPS and ECLinPS Lile

Low-Voltage ECLinPS & E-Lite
Device Data Sheets

Data Sheet Classification

Advance Information - product in the sampling or
pre-production stage at the time of publication.

Product Preview- product in the design stage at
the time of publication.

ECLinPS and ECLinPS Lite
DL140- Rev 4

4-1

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low.Voltage 1:9 Differential
ECL/PECL Clock Driver
The MC100LVE111 is a low skew 1-10-9 differential driver, designed
with clock distribution in mind. The MC100LVE111's function and
performance are similar to the popular MC100E111, with the added
feature of low voltage operation. It accepts one signal input, which can be
either differential or single-ended if the VBB output is used. The signal is
fanned out to 9 identical differential outputs.

MC100LVE111

LOW-VOLTAGE
1:9 DIFFERENTIAL
ECUPECL CLOCK DRIVER

• 200ps Part-to-Part Skew
• 50ps Output-to-Output Skew
• Differential Design
• VBBOutput
• Voltage and Temperature Compensated Outputs
• Low Voltage VEE Range of -3.0 to -3.8V
• 75k.Q Input Pulldown Resistors
The LVE111 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate to
gate skew within a device, and empirical modeling is used to
determineprocess control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50n, even if only
one side is being used. In most applications, all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used, it is necessary to terminate at least the output pairs on the
same package side as the pair(s) being used on that side, in order to
maintain minimum skew. Failure to do this will result in small degradations
of propagation delay (on the order of 10-20ps) of the output(s) being
used which, while not being catastrophic to most designs, will mean a
loss of skew margin.

The MC100LVE111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the LVE111 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE111's
performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination
offers the lowest power by taking advantage of the 1.2V supply as a terminating voltage. For more information on using PECL,
designers should refer to Motorola Application Note AN1406/D.

12194

4-2

REV1

MOTOROLA

MC100LVE111
Qo

Veea

0:;-

19
18

Ci3

Veea

PIN NAMES
Pins

Function

IN, IN

Differential Input Pair
Differential Outputs
VssOutput

00, 00-0 6, 08

Vss

Pinout: 2B-Lead PLCC

Vee

(Top View)

VBB

Cl7 Veea

LOGIC SYMBOL
Qo

00
Q1

0:;Q2

02
Q3

Ci3
IN

[4J

Os
Q6

Os
Q7

Cl7
Qs

Vss---

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA

MC100LVE111
ECL DC CHARACTERISTICS
-4DOC
Symbol

DOC

25°C

85°C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage

-1.025

-0.955

-0.880

-1.025

-0.955

-0.880

-1.025

-0.955

-0.880

-1.025

-0.955

-0.880

VOL

Output LOW Voltage

-1.810

-1.705

-1.620

-1.810

-1.705

-1.620

-1.810

-1.705

-1.620

-1.810

-1.705

-1.620

VIH

Input HIGH Voltage

-1.165

-0.880

-1.165

-0.880

-1.165

-0.880

-1.165

-0.880

VIL

Input LOW Voltage

-1.810

-1.475

-1.810

-1.475

-1.810

-1.475

-1.810

-1.475

VBB

Output Reference
Voltage

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

VEE

Power Supply Voltage

-3.0

-3.8

-3.0

-3.8

-3.0

-3.8

-3.0

-3.8

IIH

Input HIGH Current

150

J1A

lEE

Power Supply Current

Unit

150
55

150

PECL DC CHARACTERISTICS
-4O"C
Symbol

Characteristic

O°C

25°C

85°C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

VOH

Output HIGH Voltage1

2.275

2.345

2.420

2.275

2.345

2.420

2.275

2.345

2.420

2.275

2.345

2.420

VOL

Output LOW Voltage1

1.490

1.595

1.680

1.490

1.595

1.680

1.490

1.595

1.680

1.490

1.595

1.680

VIH

Input HIGH Voltage1

2.135

2.420

2.135

2.420

2.135

2.420

2.135

2.420

VIL

Input LOW Voltage1

1.490

1.825

1.490

1.825

1.490

1.825

1.490

1.825

VBB

Output Reference Volt·
agel

1.92

2.04

1.92

2.04

1.92

2.04

1.92

2.04

VCC

Power Supply Voltage

3.0

3.8

3.0

3.8

3.0

3.8

3.0

IIH

Input HIGH Current

lEE

Power Supply Current

150

150
55

150

3.8

150

J1A

1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with Vcc.

AC CHARACTERISTICS (VEE

=VEE (min) to VEE (max); Vee =Veea =GND)
-4DOC

Symbol

Characteristic

tpLH
tpHL

Propagation Delay to Output
IN (differential)
IN (single·ended)

tskew

Within-Device Skew

Min

Typ

25°C

O°C
Max

Min

Typ

Max

Min

Typ

85°C
Max

Min

Typ

Max

Unit

Condition

ps
400
350

650
700

435
385

50
250

Part-to-Part Skew (Dill)

625
675

440
390

630
680

445
395

50
200

635
685
50
200

Note 1
Note 2
ps

Note 3

Note 4

Vpp

Minimum Input Swing

500

VCMR

Common Mode Range

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

NoteS

t,llf

Output RiseJFalilime

200

600

200

800

200

600

200

600

20%-80%

500

1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
2. The single-ended propagation delay is defined as the delay from the 50% paint of the input Signal to the 50% point of the output signal. See
Definiffons and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. Vpp(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The Vpp(min) is AC limited
for the E111 as a differential input as low as 50 mV will still produce full ECl levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The Vil level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

MOTOROLA

4-4

ECLinPS and ECLinPS Lite
Dl140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low Voltage 16: 1 Multiplexer

MC100LVE164

The MC1 OOLVE164 is a 16:1 multiplexer with a differential output. The
select inputs (SELO, 1, 2, 3 ) control which one of the sixteen data inputs
(AO - A 15) is propagated to the output. The device is functionally
equivalent to the MC100E164 except it operates from a -3.3V supply.
The device is packaged in the 32-lead TQFP. The TQFP has a 7x7mm
body with a O.8mm lead pitch.
Special attention to the design layout results in a typical skew between
the 16 inputs of only 50ps.

LOW VOLTAGE

16:1 MULTIPLEXER
• 850ps Data Input to Output
• Differential Output
• Extended 100E VEE Range of -3.0V to -3.8V
• Internal75kQ Input Pulldown Resistors
Pinout: 32-Lead TQFP (Top View)

•

Al0

SEL3

VCC

SEL2

SEL1

MC100LVE164

SELO

FA SUFFIX
TOFP PACKAGE
CASE 873A-02

LOGIC DIAGRAM

Ao---i

01
Al---t
()

::l:

«
'"

ll!

::;;:

w
w

•••

()

16:1

AI4---t

PIN NAMES
Pin
AO-AI5
SEL[O:3]
O,Q

A1S---t

Function
Data Inpuls
Select Inputs
Output

SELO-----'
SEll _ _ _ _ _.J
SEL2 - - - - - - - - '
SEL3 - - - - - - - - '

6/95

4-5

REV 1

MOTOROLA

MC100LVE164
DC CHARACTERISTICS (VEE =VEE(min) to VEE(max); Vee

=Veea = GND)

-40'C
Symbol

Characteristic

Min

Typ

O'C
Max

Min

. 150

IIH

Input HIGH Current

lEE

Power Supply Current

AC CHARACTERISTICS (VEE

tpLH
tpHL

tSKEW

Within Device Skew1

tr
tf

Rise/Fall Times

Min

Typ

85'C
Max

Min

Typ

150

Max

Unit

150

ItA

=VEE(min) to VEE(max); Vee =Veea = GND)
25'C

O'C

85'C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

A Input
SELO
SEL1
SEL2
SEL3

350
500
400
400
400

600
700
675
675
550

850
900
900
900
700

350
500
400
400
400

600
700
675
675
550

850
900
900
900
700

350
500
400
400
400

600
700
675
675
550

850
900
900
900
700

350
500
400
400
400

600
700
675
675
550

850
900
900
900
700

20%-80%

275

400

550

275

400

550

275

400

550

275

400

Characteristic
Propagation Delay
to Output

25'C
Max
150

-40'C
Symbol

Typ

ps
550

..
Within Device skew IS defined as the difference In the A to Q delay between the 16 different A Inputs.

FUNCTION TABLE
SEL3

SEL2

SEL1

SELO

Data

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
'H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
.All
A12
A13
A14
A15

MOTOROLA

4-6

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low Voltage Dual 1 :4, 1:5
Differential Fanout Buffer
EeL/PECL Compatible
The MC100lVE210 is a low voltage, low skew dual differential ECl
fanout buffer designed with clock distribution in mind. The device features
two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device.
features fully differential clock paths to minimize both device and system'
skew. The dual buffer allows for the fanout of two signals through a single
chip, thus reducing the skew between the two fundamental signals from a
part-ta-part skew down to an output-to-output skew. This capability
reduces the skew by a factor of 4 as compared to using two lVE111 's to
accomplish the same task. The MC100lVE210 works from a -3.3V
supply while the MC1 00E21 0 provides identical function and
performance from a standard -4.5V 100E voltage supply.

MC100LVE210
MC100E210

LOW VOLTAGE
DUAL 1 :4, 1:5 DIFFERENTIAL
FANOUT BUFFER

• Dual Differential Fanout Buffers
• 200ps Part-ta-Part Skew
• 50ps Typical Output-to--Output Skew
• low Voltage ECLJPECl Compatible
• 28-lead PlCC Packaging
For applications which require a single-ended input, the VBB reference
voltage is supplied. For single-ended input applications the VBB
reference should be connected to the ClK input and bypassed to ground
via a 0.01)!f capacitor. The input Signal is then driven into the ClK input.

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 500, even if only
one side is being used. In most applications all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used it is necessary to terminate at least the output pairs
adjacent to the output pair being used in order to maintain minimum skew.
Failure to follow this guideline will result in small degradations of
propagation delay (on the order of 1D-20ps) of the outputs being used,
while not catastrophic to most designs this will result in an increase in
skew. Note that the package corners isolate outputs from one another
such that the guideline expressed above holds only for outputs on the
same side of the package.

The MC100lVE210, as with most ECl devices, can be operated from a positive VCC supply in PECl mode. This allows the
lVE21 0 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the lVE210's
performance to distribute low skew clocks across the backplane or the board. In a PECl environment series or Thevenin line
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage
of VCC-2.OV will need to be provided. For more information on using PECl, designers should refer to Motorola Application Note
AN1406/D.

7/95

4-7

REV 1

MOTOROLA

PIN NAMES
Pins

Function

CLKa, CLKb
QaO:4, QbO:3
VBB

Differential Input Pairs
Differential Outputs
VBBOutput

LOGIC SYMBOL
- - - " ' - - QaO

CLKa

1'""'"'"1"...u-

QaO

--f"o<::--+-+-f'o::---

Qa1

CLKa

Qa1
..............." ' - - - Qa2
or-Y"Ir--

Qa2

' - ' - - " ' - - Qa3
..............,.- Qa3

CLKb

_---1''_-

QbO

1""'""1.""""--f'o::--+-+-......::---

Qb1

CLKb

QbO

Qb1
_4-.f'-._- Qb2
or-Y"I;>--

Qb2

_4-.f'-._-

Qb3

or-........;>-- Qb3
L-.j.......f'_-

Qb4

--........,.- Qb4
VBB---

MOTOROLA

ECLinPS and ECLinPS Lite
DL140-Rev4

MC1OOLVE210 MC100E210
MC100lVE210
ECl DC CHARACTERISTICS
-40'C

O'C

2S'C

8S'C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Outpul HIGH Voltage

-t.OB5

-1.005

-o.BBO

-1.025

-0.955

-o.BBO

-1.025

-0.955

-o.BBO

-1.025

-0.955

-o.BBO

VOL

Output LOW Voltage

-1.B30

-1.695

-1.555

-1.Bl0

-1.705

-1.620

-1.Bl0

-1.705

-1.620

-1.Bl0

-1.705

-1.620

VIH

Input HIGH Voltage

-1.165

-o.BBO

-1.165

-o.BBO

-1.165

-o.BBO

-1.165

-o.BBO

VIL

Input LOW Voltage

-1.810

-1.475

-1.8tO

-1.475

-1.810

-1.475

-1.810

-1.475

VBB

Output Reference
Voltage

-1.3B

-1.26

-1.3B

-1.26

-1.3B

-1.26

-1.38

-1.26

VEE

Power Supply Voltage

-3.0

-3.B

-3.0

-3.8

-3.0

-3.8

-3.0

-3.8

IIH

Input HIGH Current

150

i!A

lEE

Power Supply Current

rnA

Symbol

MC1OOlVE210
PECl DC CHARACTERISTICS
-40'C

Characteristic

2S'C

O'C

8S'C
Typ

Max

Unit

VOH

Output HIGH Voltage1

2.215

2.295

2.42

2.275

2.345

2.420

2.275

2.345

2.420

2.275

2.345

2.420

VOL

Output LOW Voltage1

1.47

1.605

1.745

1.490

1.595

I.S80

1.490

1.595

I.S80

1.490

1.595

1.680

VIH

Input HIGH Voltage1

2.t35

2.420

2.135

2.420

2.t35

2.420

2.135

2.420

VIL

Input LOW Voltage1

1.490

1.825

1.490

1.825

1.490

1.825

1.490

1.825

VBB

Output Reference
Voltage1

1.92

2.04

1.92

2.04

1.92

2.04

1.92

2.04

VCC

Power Supply Voltage

3.0

3.8

3.0

3.8

3.0

3.8

3.0

3.8

IIH

Input HIGH Current

150

i!A

lEE

Power Supply Current

rnA

Symbol

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

1. These values are for VCC =3.3V. level Specifications will vary 1:1 with VCC.

MC1OOlVE210
AC CHARACTERISTICS (VEE

=VEE (min) to VEE (max); Vee =Veea =GND)
-40'C

Symbol

Characteristic

Min

Typ

O'C
Max

Min

Typ

2S'C
Max

Min

Typ

8S'C
Max

Min

Typ

Max

Unit

Condition

tpLH
tpHL

Propagation Delay to Output
IN (differential)
IN (single-ended)

tskew

Within-Device Skew Oa....ab
Oa....Oa,Ob....Ob
Part-to-Part Skew (Diff)

Vpp

Minimum Input Swing

500

Note 4

VCMR

Common Mode Range

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

NoteS

t,ltf

Output Rise/Fall"lirne

200

SOO

200

SOO

200

600

200

SOO

20%-80%

475
400

S75
700
50
50

475
400

75
75
200

675
700
50
30

500
450

75
50
200

500

700
750
50
30

500
450

75
50
200

700
750
50
30

75
50
200

500

Note 1
Note 2
ps

Note 3

1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
3. The within--device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. Vpp(min) is defined as the minimum input differential voltage which will cause no increase in the propagation deiay. The Vpp(min) is AC limited
for the lVE210 as a differential input as low as 50 mV will still produce full ECl levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The Vil level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

ECLinPS and ECLinPS Lite
Dl140-Rev4

4-9

MOTOROLA

MC1 OOLVE21 0 MC1 OOE21 0
MC100E210
ECl DC CHARACTERISTICS
-40·C

25·C

O·C

85·C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage

-1.085

-1.005

-0.880

-1.025

-0.955

-0.880

-1.025

-0.955

-0.880

-1.025

-0.955

-0.880

VOL

Output LOW Voltage

-1.830

-1.695

-1.555

-1.810

-1.705

-1.620

-1.810

-1.705

-1.620

-1.810

-1.705

-1.620

VIH

Input HIGH Voltage

-1.165

-0.880

-1.165

-0.880

-1.165

-0.880

-1.165

-0.880

VIL

Input LOW Voltage

-1.810

-1.475

-1.810

-1.475

-1.810

-1.475

-1.810

-1.475

VBB

Output Reference
Voltage

-1.38

-1.26'

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

V·

VEE

Power Supply Voltage

-5.25

-4.2

-5.25

-4.2

-5.25

-4.2

-5.25

-4.2

IIH

Input HIGH CUrrent

150

jlA

lEE

Power Supply Current

Symbol

MC100E210
PECl DC CHARACTERISTICS
-40·C

O·C

25·C

85·C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage1

3.915

3.995

4.12

3.975

4.045

4.12

3.975

4.045

4.t2

3.975

4.045

4.12

VOL

Output LOW Voltage1

3.170

3.305

3.445

3.19

3.295

3.38

3.19

3.295

3.38

3.19

3.295

3.38

VIH

Input HIGH Voltage1

3.835

4.12

3.835

4.12

3.835

4.12

3.835.

4.12

VIL

Input LOW Voltage1

3.190

3.525

3.190

3.525

3.190

3.525

3.190

3.525

VBB

Output Reference
Voltage!

3.62

3.74

3.62

3.74

3.62

3.74

3.62

3.74

VCC

Power Supply Voltage

4.75

5.25

4.75

5.25

4.75

5.25

4.75

5.25

IIH

Input HIGH CUrrent

150

jlA

lEE

Power Supply Current

Symbol

1. These values are for VCC

=5.0V. Level Specifications will vary 1:1 with Vcc.

MC1OOE210
AC CHARACTERISTICS (VEE

=VEE (min) to VEE (max); Vee =Veea =GND)
-40·C

Symbol

Characteristic

Min

Typ

O·C
Max

Min

'Typ

25·C
Max

Min

Typ

85·C
Max

Min

Typ

Max

Unit

Condition

tpLH
tpHL

Propagation Delay to Output
IN (differential)
IN (single-

::;;

I~ ~

:;;::
-'
0

I§

III

w
w

[AJ

LOGIC SYMBOL
MR
ClKO
ClKO
CLK1
ClK1
ClK_Sel

OaO:1
OaO:1

VBB
fsela
ObO:2
ObO:2
fselb
OeO:3
OCO:3
!sale
OdO:5
OdO:5
fseld

MOTOROLA

4-12

ECLinPS and ECLinPS Lite
DL140-Rev4

MC100LVE222
ECl DC CHARACTERISTICS
-40'C
Symbol

Characteristic

O'C

2S'C

8S'C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage

-1.0B5

-1.005

-{).8BO

-1.025

-{).955

-{).BBO

-1.025

-{).955

-{).BBO

-1.025

-{).955

-{).BBO

VOL

Output LOW Voltage

-1.B30

-1.695

-1.555

-1.Bl0

-1.705

-1.620

-1.Bl0

-1.705

-1.620

-1.Bl0

-1.705

-1.620

VIH

Input HIGH Voltage

-1.165

-{).BBO

-1.165

-{).BBO

-1.165

-{).BBO

-1.165

-{).BBO

VIL

Input LOW Voltage

-1.Bl0

-1.475

-1.Bl0

-1.475

-1.Bl0

-1.475

-1.Bl0

-1.475

Vee

Output Reference

-1.3B

-1.26

-1.3B

-1.26

-1.3B

-1.26

-1.3B

-1.26

...;3.0

-5.25

...;3.0

-5.25

...;3.0

-5.25

...;3.0

-5.25

150

IlA

Voltage
VEE

Power Supply Voltage1

IIH

Input HIGH Current

lEE

Power Supply Current

150

150
BO

150

1. Special thermal handling required for VEE < -a.8V.

PECl DC CHARACTERISTICS
-40'C

Characteristic

Symbol

O'C

2S'C

8S'C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage1

2.215

2.295

2.420

2.275

2.345

2.420

2.275

2.345

2.420

2.275

2.345

2.420

VOL

Output LOW Voltage1

1.470

1.605

1.745

1.490

1.595

1.6BO

1.490

1.595

1.6BO

1.490

1.595

1.6BO

VIH

Input HIGH Voltage1

2.135

2.420

2.135

2.420

2.135

2.420

2.135

2.420

VIL

Input LOW Voltage1

1.490

I.B25

1.490

I.B25

1.490

I.B25

1.490

I.B25

Vee

Output Reference Volt-

1.92

2.04

1.92

2.04

1.92

2.04

1.92

2.04

3.0

5.25

3.0

5.25

3.0

5.25

3.0

5.25

150

agel
VCC

Power Supply Voltage2

IIH

Input HIGH Current

lEE

Power Supply Current

150

150
BO

1. These values are for VCC = 3.3V. level Specifications will vary 1:1 with VCC.
2. Special thermal handling required for VCC > 3.aV.

AC CHARACTERISTICS (VEE

=VEE (min) to VEE (max); Vee =Veea = GND)
-40'C

Symbol

Characteristic

tpLH
tpHL

Propagation Delay to Output
IN (differential)
IN (single-ended)

tskew

Within-Device Skew
Part-ta-Part Skew (Diff)

Min

Typ

O'C
Max

Min

Typ

2S'C
Max

Min

Typ

8S'C
Max

Min

Typ

Max

Unit

Condition

ns
1.0
1.0

1.0
1.0
50
250

1.0
1.0
50
200

Note 1
Note 2

1.0
1.0
50
200

SO
200

Note 3

Vpp

Minimum Input Swing

500

Note 4

VCMR

Common Mode Range

-1.5

-{).4

-1.5

-{).4

-1.5

-{).4

-1.5

-{).4

NoteS

t,ltl

Output Rise/Fall lime

200

600

200

600

200

600

200

600

20%-80%

500

1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing pOint of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. Vpp(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The Vpp(min) is AC limited
for the lVE222 as a differential input as low as 50 mV will still produce full ECl levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The Villevel
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

ECLinPS and ECLinPS Lite
Dl140-Rev4

4--13

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low Voltage 2:8 Differential
Fanout Buffer
ECL/PECL Compatible

MC100LVE310
MC100E310

The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device features
fully differential clock paths to minimize both device and system skew.
The LVE310 offers two selectable clock inputs to allow for redundant or
test clocks to be incorporated into the system clock trees. The
MC100E310 is pin compatible to the National 100310 device. The
MC100LVE310 works from a -3.3V supply while the MC100E310
provides identical function and performance from a standard -4.5V 100E
voltage supply.

LOW VOLTAGE
2:8 DIFFERENTIAL
FANOUT BUFFER

• Dual Differential Fanout Buffers
• 200ps Part-ta-Part Skew
• 50ps Output-to-:.Output Skew
• Low Voltage ECUPECL Compatible
• 28-lead PLCC Packaging
For applications which require a single-ended input, the VBB reference
voltage is supplied. For single-ended input applications the VBB
reference should be connected to the CLK input and bypassed to ground
via a O.Q1!if capacitor. The input signal is then driven into the CLK input.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50n, even if only
one side is being used. In most applications all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used it is necessary to terminate at least the output pairs
adjacent to the output pair being used in order to maintain minimum skew.
Failure to follow this guideline will result in small degradations of
propagation delay (on the order of 1Q-20ps) of the outputs being used,
while not catastrophic to most designs this will result in an increase in
skew. Note that the package corners isolate outputs from one another
such that the guideline expressed above holds only for outputs on the
same side of the package.

FNSUFFIX
PLASTIC PACKAGE
CASE 776-02

The MC1 00LVE31 0, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
LVE31 0 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE310's
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage
of VCC-2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note
AN 1406/D.
.

7/95

4-14

REV 0.1

MOTOROLA

MC1 OOLVE31 0 MC1 OOE31 0
00

Of
23

VEE

CLK_SEL

CLKa

CLKa,ClKb

Vcca

VSS
ClK_SEl

Pinout: 28-Lead PLCC

VCC

VBB

12
5

CLKb

ID Vcca 07

Pins

00:7

(Top View)

CLKa

CLKb

PIN NAMES

elK_SEl

0
1

Function
Differential Input Pairs
Differential Outputs
VSS Output
Input Clock Select

Input Clock
ClKa Selected
ClKb Selected

LOGIC SYMBOL
00

00
01

CIT
02

Q2
CLKa

[AJ

CLKa

CLKb

04
Q4

CLKb

ClK_SEl

as
06

Q6
07

ID
VSB---

ECLinPS and ECLinPS Lite
Dl140-Rev4

4-15

MOTOROLA

MC1OOLVE310 MC100E310
MC1OOlVE310
ECl DC CHARACTERISTICS
O°C

"""O°C

SSOC

25°C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Mpx

Min

Typ

Max

VOH

Output HIGH Voltage

-1.0B5

-1.005

-o.BBO

-1.025

-0.955

-o.BBO

-1.025

-0.955

-o.BBO

-1.025

-0.955

-0.880

VOL

Output LOW Voltage

-t.830

-1.695

-1.555

-1.810

-1.705

-1.620

-1.810

-1.705

-1.620

-1.810

-1.705

-1.620

Symbol

Unit

VIH

Input HIGH Voltage

-1.165

-0.880

-1.165

-o.B80

-1.165

-o.B80

-1.165

-0.880

VIL

Input LOW Voltage

-1.Bl0

-1.475

-1.810

-1.475

-1.Bl0

-1.475

-1.810

-1.475

VSS

Output Relerence
Voltage

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

-1.3B

-1.26

VEE

Power Supply Voltage

~.O

~.8

~.O

~.8

~.O

~.8

~.O

~.8

IIH

Input HIGH Current

150

jlA

lEE

Power Supply Current

150
55

150

150
55

MC1OOlVE310
PECl DC CHARACTERISTICS
O°C

"""O°C
Symbol

Characteristic

ssoC

25°C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage1

2.215

2.295

2.42

2.275

2.345

2.420

2.275

2.345

2.420

2.275

2.345

2.420

VOL

Output LOW Voltage1

1.47

1.605

1.745

1.490

1.595

1.6BO

1.490

1.595

1.680

1.490

1.595

1.680

VIH

Input HIGH Vollage1

2.135

2.420

2.135

2.420

2.135

2.420

2.135

2.420

VIL

Input LOW Voltage1

1.490

I.B25

1.490

I.B25

1.490

I.B25

1.490

1.825

VSS

Output Reference
Voltage1

1.92

2.04

1.92

2.04

1.92

2.04

1.92

2.04

VCC

Power Supply Voltage

3.0

3.8

3.0

3.B

3.0

3.8

3.0

IIH

Input HIGH Current

lEE

Power Supply Current

1. These values are for VCC

150
55

150

3.8

150

jlA

=3.3V. level Specifications will vary 1:1 with VCC.

MC100lVE310
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); Vee = Veea = GND)
O°C

"""O°C
Symbol

Characteristic

tpLH
tpHL

Propagation Delay to Output
IN (differential)
IN (single-ended)

tskew

Within-Device Skew
Part-ta-Part Skew (Diff)

Min

Typ

Max

Min

Typ

25°C
Max

Min

Typ

85°C
Max

Min

Typ

Max

Unit

Condition

ps
525
500

725
750

550
525

75
250

750
775

550
550

75
200

750
BOO

575
600

50
200

775
850
50
200

Note 1
Note 2
ps

Note 3

Vpp

Minimum Input Swing

500

Note 4

VCMR

Common Mode Range

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

NoteS

t,.ttl

Output Rise/Falliime

200

600

200

600

200

600

200

600

20%-80%

500

1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
2. The Single-ended propagation delay is defined as the delay from the 50% point of the input Signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. Vpp(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The Vpp(min) is AC limited
for the lVE310 as a differential input as low as 50 mV will still produce full ECl levels at the output.
5. VCMR Is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

MOTOROLA

4-16

ECLinPS and ECLinPS Lite
Dl140-Rev4

MC100LVE310 MC100E310
MC100E310
ECl DC CHARACTERISTICS
DoC

-40°C
Symbol

Characteristic

25°C

85°C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage

-1.085

-1.005

-0.880

-1.025

-0.955

-0.880

-1.025

-0.955

-0.880

-1.025

-0.955

-0.880

VOL

Output LOW Voltage

-1.830

-1.695

-1.555

-1.Bl0

-1.705

-1.620

-1.Bl0

-1.705

-1.620

-1.810

-1.705

-1.620

VIH

Input HIGH Voltage

-1.165

-o.B80

-1.165

-o.BBO

-1.165

-o.8BO

-1.165

-o.8BO

VIL

Input LOW Voltage

-1.Bl0

-1.475

-1.Bl0

-1.475

-1.810

-1.475

-1.810

-1.475

Output Reference

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

-5.25

-4.2

-5.25

-4.2

-5.25

-4.2

-5.25

-4.2

150

VSS

Voltage
VEE

Power Supply Voltage

Input HtGH Current

lEE

Power Supply CUrrent

150

150
55

150

MC100E310
PECl DC CHARACTERISTICS
DoC

-40°C

25°C

85°C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

VOH

Output HIGH Voltage1

3.915

3.995

4.12

3.975

4.045

4.12

3.975

4.045

4.12

3.975

4.045

4.12

VOL

Output LOW Voltage1

3.170

3.305

3.445

3.19

3.295

3.38

3.19

3.295

3.38

3.19

3.295

3.38

V,H

Input HIGH Voltage1

3.835

4.12

3.835

4.12

3.835

4.12

3.835

4.12

V,L

Input LOW Voltage1

3.190

3.525

3.190

3.525

3.190

3.525

3.190

3.525

VSS

Output Reference
Voltage1

3.62

3.74

3.62

3.74

3.62

3.74

3.62

3.74

VCC

Power Supply Voltage

4.75

5.25

4.75

5.25

4.75

5.25

4.75

5.25

Input HIGH Current

150

lEE

Power Supply Current

Symbol

150

150
55

150

1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with Vcc.

MC100E310
AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); Vee = Veea = GND)
-40°C
Symbol

Characteristic

tpLH
tpHL

Propagation Delay to Output
IN (differential)
IN (single--ended)

tskew

Within-Device Skew
Part-to-Part Skew (Diff)

Min

Typ

O°C
Max

Min

Typ

25°C
Max

Min

Typ

85°C
Max

Min

Typ

Max

Unit

Condition

525
500

725
750

550
525

75
250

750
775

550
550

75
200

750
800

575
600

50
200

Note 1
Note 2

775
850
ps

Note 3

Note 4

VPP

Minimum Input Swing

500

VCMR

Common Mode Range

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

-1.5

-0.4

note 5

tltl

Output RiseJFalilime

200

600

200

600

200

600

200

600

20%-80%

500

1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output Signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12).
3. The within-2000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION

[!]

Vee

DC CHARACTERISTICS (VEE

. Min

Power Supply Current

VEE

Power Supply Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

D
QO,Q1

Data Inputs
Data Outputs

=VEE(min) to VEE(max); VCC = GND)

Characteristic

lEE

FUNCTION

VEE

-40'C
Symbol

-3.0

O'C

Typ

Max

-3.3

-3.8

Min

-3.0

150
Dn
Dn

0.5
-600

2S'C

Typ

Max

-3.3

-3.8

Min

-3.0

Max

-3.3

-3.8

0.5
-600

1196

4-18

Min

-3.0

150

150
0.5
-600

85'C

Typ

REVO

0.5
-600

Typ

Max

Unit

rnA

-3.3

-3.8

150

1IA
1IA

MOTOROLA

MC1 OOLVEL 11
AC CHARACTERISTICS (VEE = VEE (min) to VEE(max); Vee = GND)
-40°C
Symbol

Characteristic

Min

tplH
tpHl

Propagation Delay to
Output

tSKEW

Within-Device Skew 1
Duty Cycle Skew2

Typ

235
S
S

25°C

O°C
Max

Min

385

245

Typ

20
20

5
5

Min

Typ

Max

Min

395

255

330

405

285

S
S

20
20

VPP

Minimum Input Swing3

200

VCMR

Common Mode Range 4
Vpp<500mV
Vpp"SOOmV

-2.1
-1.9

-0.2
-0.2

-2.2
-2.0

-0.2
-0.2

-2.2
-2.0

120

320

120

320

120

tr
tf

Output Rise/Fall TImes Q
(20%-80%)

85°C

Max

200

Typ

5
S

Max

Unit

435

20
20

ps
mV

200

220

-0.2
-0.2

-2.2
-2.0

-0.2
-0.2

320

120

320

1. Within-device skew defined as identical transitions on similar paths through a device.
2. Duty cycle skew is the difference between a TPlH and TPHl propagation delay through a device.
3. Minimum input swing for which AC parameters guaranteed. The device will function properly with input swings below 200mV, however, AC
delays may move outside of the specified range. The device has a DC gain of =40.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak·to-peakvoltage lies between Vppmin and 1V. The lower end olthe CMR range varies 1:1 with VEE. The number
in the spec table assumes a nominal VEE = -a.3V. Note for PECl operation, the VCMR(min) will be fixed at 3.3V -IVCMR(min)1.

800

;;-

600

1t0..
j::"
:::>

400

::9

200

0
0

200

400

600

800

1000

1200

1400

1600

1800

2000

f(MHz)

Figure 1. Output Swing versus Frequency

ECLinPS and ECLinPS Lite
Dl140-Rev4

4-19

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual 1:3 Fanout Buffer

MC100LVEL13
MC100EL13

The MC100lVEL13 is a dual, fully differential 1:3 fanout buffer. The
MC100EL13 is pin and functionally equivalent to the MC100lVEL13 but
is specified for operation at the standard 100E ECl voltage supply. The
low Output-Output Skew of the device makes it ideal for distributing two
different frequency synchronous signals.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are left
open the D input will pull down to VEE, The 5 input will bias around VCcJ2
and the Q output will go lOW.
• Differential Inputs and Outputs
• 2Q-lead SOIC Packaging
OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D"'()4

• 500ps Typical Propagation Delays
• 50ps Output-Output Skews
• Supports Both Standard and low Voltage 100K ECl
• >2000V ESD Protection

Logic Diagram and Pinout: 20-Lead SOIC (Top View)
01a

01a

OOa

02a

VCC

02b

01b

VCC ClKa ClKa ClKb ClKb VCC

01b

PIN NAMES

VEE

Pins

Function

Ona, Qna
Qnb, Qnb
ClKn, ClKn

Differential Clock Outputs
Differential Clock Outputs
Differential Clock Inputs

OOb

MC100LVEL13
DC CHARACTERISTICS (VEE = -3.0V to -3.8V; VCC = GND)
-40°C
Symbol

Characteristic

lEE

Power Supply Current

IIH

Input HIGH Current

IINL

Input LOW Current

Min

Max

Min

0.5
-300

Typ

Max

Min

150

150
Dn
Dn

25°C

O°C

Typ

0.5
-300

4-20

Max

Min

150
0.5
-300

4/95

05°C

Typ

REV 1

0.5
-300

Typ

Max

Unit

rnA

150

IlA
IlA

MOTOROLA

MC100LVEL 13 MC100EL 13
MC100LVEL13
AC CHARACTERISTICS (VEE: -3.0V to -3.BV; Vee: GND)
-40'C
Symbol

Characteristic

Min

Typ

O'C
Max

Min

600

420

Typ

25'C
Max

Min

610

430

Typ

85'C
Max

Min

620

450

Typ

Max

tpLH
tpHL

Propagation Delay
CLK.... Q/Q

tsk(O)

Output-Output Skew
Any Qa.... Qa. Any Qb .... Qb
Any Qa....Any Qb

50
75

tsk(DC)

Duty Cycle Skew
ItPLH-tpHLI

ps
410

640
ps

Vpp

Minimum Input Swing 1

150

1000

150

1000

150

1000

150

1000

VCMR

Common Mode Range2
Vpp <500mV
Vpp ,,500mV

-2.0
-1.8

-0.4
-0.4

-2.1
-1.9

-0.4
-0.4

-2.1
-1.9

-0.4
-0.4

-2.1
-1.9

-0.4
-0.4

230

500

230

500

230

500

230

500

tr
tf

Output Rise/Fall Times Q
(20%-80%)

Unit

mV
V

1. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of =40.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and lV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE ~.3V. Note for PECL operation. the VCMR(min) will be fixed at3.3V -IVCMR(min)1.

MC100EL13
DC CHARACTERISTICS (VEE: -4.2V to -5.5V; Vee: GND)
-40'C
Symbol

Characteristic

lEE

Power Supply Current

IIH

Input HIGH Current

IINL

Input LOW Current

Min

Max

Min

Typ

Max

150
Dn
Dn

25'C

O'C

Typ

Min

85'C

Typ

Max

150

Min

Typ

Max

Unit

rnA

150

!lA
!lA

Max

Unit

150

0.5

~OO

MC100EL13
AC CHARACTERISTICS (VEE: -4.2V to -5.5V; Vee: GND)
-40'C
Symbol

Characteristic

Min

Typ

O'C
Max

Min

600

420

Typ

25'C
Max

Min

610

430

Typ

85'C
Max

Min

620

450

Typ

tpLH
tpHL

Propagation Delay
CLK.... Q/Q

tsk(O)

Output-Output Skew
Any Qa.... Qa. Any Qb....Qb
Any Qa....Any Qb

50
75

tsk(DC)

Duty Cycle Skew
ItPLH-tpHLI

VPP

Minimum Input Swing 1

150

1000

150

1000

150

1000

150

1000

VCMR

Common Mode Range2
Vpp<500mV
Vpp,,500mV

~.2

-0.4
-0.4

~.3

-3.1

-0.4
-0.4

~.3

~.1

-0.4
-0.4

~.3

~.O

~.1

-0.4
-0.4

230

500

230

500

230

500

230

500

tr
tf

Output Rise/Fall Times Q
(20%-80%)

ps
410

640
ps

ps
mV
V

1. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of =40.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = -4.5V. Note for PECL operation. the VCMR(min) will be fixed at5.0V - IVCMR(min)l.

ECLinPS and ECLinPS Lite
DL140-Rev4

4-21

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

1:5 Clock Distribution Chip

MC100LVEL14
MC100EL14

The MC100LVEU100EL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to operate
in ECL or PECL mode for a voltage supply range of -3.0V to -3.BV ( or
3.0V to 3.8V). If a single-ended input is to be used the VSS output should
be connected to the CLK input and bypassed to ground via a O.D1IlF
capacitor. The VSS output is designed to act as the switching reference
for the input of the LVEL14 under single-ended input conditions, as a
result this pin can only source/sink up to O.5mA of current.
The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by' the input
pull down resistor) the SEL pin will select the differential clock input.

20~
OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-04

The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of
the clock input.
• SOps Output-to-Output Skew
• Synchronous Enable/Disable

PIN DESCRIPTION

• Multiplexed Clock Input
• 75kQ Internal Input Pulldown Resistors
• >2000V ESD Protection
• VEE Range of -3.0V to -S.SV

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

Vcc

SCLK ClK

ClK

VBB

SEL

VEE

FUNCTION

CLK
SCLK
EN
SEL
VSS
QQ-4

Diff Clock Inputs
Scan Clock Input
Sync Enable
Clock Select Input
Reference Output
Diff Clock Outputs

FUNCTION TABLE
ClK

SClK

SEL

X
X

L
L

H
H

L
L
L
L

X
X
X

H
L

H
L*

* On next negative transition of
ClKor SCLK

7/95

4-22

REV 1

MOTOROLA

MC100LVEL14 MC100EL14
ABSOLUTE MAXIMUM RATINGS1
Symbol

Characteristic

Rating

Unit

-8.0 to 0

VDC

Oto-6.0

VDC

50
100

=OV)
Input Voltage (VCC =OV)

lout

Output Current

Operating Temperature Range

-40 to +B5

°C

VEE

Operating Rangel ,2

-5.7to-4.2

VEE

Power Supply (VCC

Continuous
Surge

1. Absolute maximum rating, beyond WhiCh, device hfe may be Impaired, unless otherwise specified on an individual data shee\.
2. Parametric values specified at: 1OOEL Series: -4.20V to -5.50V
1DEL Series:
-4.94V to -5.50V

DC CHARACTERISTICS (VEE

=VEE(min) -

VEE(max); Vee

=GND1)
DOC to 85°C

-40°C

Typ

Max

Unit

VOH

Output HIGH Voltage

-1085

-1005

-880

-1025

-955

-8BO

VIN

VOL

Output LOW Voltage

-IB30

-1695

-1555

-IBID

-1705

-1620

orVIL(min)

VOHA

Output HIGH Voltage

-1095

-1035

VIN

Output LOW Voltage

VOLA

-1555

-1610

orVIL(min)

Symbol

Characteristic

Min

Typ

Max

Min

VIH

Input HIGH Voltage

-1165

-BBO

-1165

-8BO

VIL

Input LOW Voltage

-IBID

-1475

-1810

-1475

IlL

Input LOW Current

I1A

CLK
Others

-300
0.5

Condition

=VIH(max)
=VIH(max)

VIN = VIL(max)

1. This table replaces the three tables traditionally seen In ECL lOOK data books. The same DC parameter values at VEE -4.5V now apply across
the full VEE range of-3.0V to -5.5V. Outputs are terminated through a 50U resistor to-2.0V except where otherwise specified on the individual
data sheets.

ECLinPS and ECLinPS Lite
DL140- Rev 4

4-23

MOTOROLA

MC100LVEL14 MC100EL14
MC100LVEL14 AC/DC CHARACTERISTICS (VEE = -3.8V to -3.0V; Vee = GND)
DOC

-40°C
Symbol
lEE

Characteristic

Min

Power Supply Current
100LVEL
100EL

VBB

Output Ref
Voltage

100LVEL
100El

Typ

Max

32
32

40
40

Min

85°C

25°C

Typ

Max

32
32

40
40

Min

Typ

Max

32
32

40
40

Min

Typ

Max

.34

42
42

rnA

-1.43
-1.38

-1.27 -1.35
-1.26 -1.38

-1.30 -1.38
-1.26 -1.38

-1.19
-1.26

150

!lA

630
580
580

830
880
880

200
50

Input High Current
Prop
Delay

tSKEW

Part-to-Part Skew
Within-Device Skew1

Setup Time EN

Hold Time EN

Vpp

Minimum Input Swing ClK

150

VCMR

Common Mode Range2
Vpp<500mV
Vpp;>:500mV

-2.0
-1.8

-{).4
-{).4

-2.1
-1.9

-{).4
-{).4

-2.1
-1.9

-{).4
-{).4

-2.1
-1.9

-{).4
-{).4

230

500

230

500

230

500

230

500

520
470
470

720
770
770

750
800
800

550
500
500

200
50
0

Output Rise/Fall Times Q
(20%-80%)

150

34
-1.31
-1.38

IIH

tr
tf

150

-1.25
-1.26

tpLH
tpHl

CLKtoQ(Difl)
CLKtoQ(SE)
SClKtoQ

Unit

150
580
530
530

680
680
680

200
50

780
830
830
200
50

150

1. Skews are specifIed for identIcal LOW-to-HIGH or HIGH-to-lOW transItions.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE -3.3V. Note for PECl operation, the VCMR(min) will be fixed at 3.3V -IVCMR(min)1.

MC100EL14 AC/DC CHARACTERISTICS (VEE = -4.2V to -5.SV; Vee = GND)
DOC

-40°C
Symbol
lEE

Characteristic

Min

Power Supply Current
100lVEl
100EL

VBB

Output Ref
Voltage

100lVEl
100EL

IIH

Input High Current

tplH
tpHl

Prop
Delay

tSKEW

Part-to-Part Skew
Within-Device Skew1

ClK to Q (Diff)
ClKtoQ(SE)
SClKtoQ

Typ

Max

32
32

40
40

Min

85°C

25°C

Typ

Max

32
32

40
40

Min

Typ

Max

32
32

40
40

Min

Typ

Max

34
34

42
42

Unit
mA

-1.43
-1.38

-1.30
-1.26

520
470
470

720
770
770

-1.38
-1.38

-1.27
-1.26

550
500
500

750
800
800

150

-1.35
-1.38

-1.25
-1.26

-1.19
-1.26

150

!lA

630
580
580

830
880
880

200
50

150

200
50

-1.31
-1.38

580
530
530

200
50

680
680
680

780
830
830
200
50

Setup Time EN

Hold Time EN

Vpp

Minimum Input Swing ClK

150

VCMR

Common Mode Range2
Vpp< 500mV
Vpp;>:500mV

-3.2
-3.0
230

tr
tf

Output Rise/Fall Times Q
(20%-80%)

V
-{).4

-{).4

-3.3
-3.1

500

230

-{).4

-3.3
-3.1

500

230

-{).4

-3.3
-3.1

-{).4
-{).4

500

230

500

1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW trans~ions.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and lV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = -4.5V. Note for PECl operation, the VCMR(min) will be fixed at 5.0V - IVCMR(min)1.

MOTOROLA

4-24

ECLinPS and ECLinPS Lite
DL140- Rev 4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Differential Receiver

MC100LVEL16

The MC1 OOLVEL16 is a differential receiver. The device is functionally
equivalent to the EL 16 device, operating from a low voltage supply. The
LVEL16 exhibits a wider CMR range than its EL16 counterpart. With
output transition times and propagation delays comparable to the EL 16
the LVEL 16 is ideally suited for interfacing with high frequency sources at
3.3V supplies.
The LVEL 16 provides a VBB output for either single-ended use or as a
DC bias for AC coupling to the device. The VBB pin should be used only
as a bias for the LVEL 16 as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to ground via a O.01!!f
capacitor.
Under open input conditions, the Q input will be pulled down to Vee and
the Q input will be biased to VCcJ2. This condition will force the Q output
low.
DSUFFIX

o 300ps Propagation Delay

PLASTIC SOIC PACKAGE
CASE 751-05

o High Bandwidth Output Transitions

• 75kQ Internal Input Pulldown Resistors
o >2000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

VCC

PIN DESCRIPTION

FUNCTION

D
Q
VBB

Data Inputs
Data Outputs
Ref. Voltage Output

Vss 4

5/96

4-25

REV 0

MOTOROLA

MC100LVEL16
DC CHARACTERISTICS (VEE

=VEE (min) to VEE(max); Vee = GND)
-40°C

Symbol

CharacterIstic

MIn

lEE

Power Supply Current

Vee

Output Reference Voltage

-1.3B

VEE

Power Supply Voltage

-3.0

IIH

Input HIGH Current

IlL

Input LOW Current

Max

-3.3

Min

-1.26

-1.3B

-3.B

-3.0

Typ

Max

-3.3

CLK
CLK

0.5
-il00

MIn

-1.26

-1.3B

-3.B

-3.0

150

AC CHARACTERISTICS (VEE

0.5
-il00

85°C

Typ

Max

-3.3

Min

-1.26

-1.3B

-3.B

-3.0

Typ

Max

Unit

-1.26

-3.3

150

150
0.5
-il00

-3.B

150

I1A
I1A

Unit

0.5
-il00

=VEE(min) to VEE(max); Vee = GND)
-40°C

Symbol

25°C

O°C

Typ

25°C

O°C

85°C

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

tpLH
tpHL

Propagation Delay
to Output
(Dill)
(SE)

150
100

275
275

400
450

215
165

290
290

365
415

225
175

300
300

375
425

240
190

315
315

390
440

tSKEW

Duty Cycle Skew 1 (Dill)

Vpp

Minimum Input SWing2

VCMR

Common Mode Range3
Vpp<500mV
Vpp~500mV

tr
tf

Output Rise/Fall Times Q
(20%-BO%)

150

ps
mV
V

-2.0
-1.8
120

220

-0.4
-0.4

-2.1
-1.9

320

120

220

-0.4
-0.4

-2.1
-1.9

320

120

220

-0.4
-0.4

-2.1
-1.9

320

120

-0.4
-0.4
220

320

1. Duty cycle skew IS the difference between a TPLH and TPHL propagation delay through a device.
2. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of =40.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and lV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE -3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V -IVCMR(min)l.

MOTOROLA

4-26

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Low.Voltage Quad
Differential Receiver

MC100LVEL17
MC100EL171

The MC100LVEL17 is a low-voltage, quad differential receiver. The
device is functionally equivalent to the E116 device with the capability of
operation from either a -3.3V or +3.3V supply voltage. The MC1 OOEL 17
is pin and functionally equivalent to the MC100LVEL17, but is specified
for operation at the standard 100E ECL voltage supply.
The LVEL17 provides a VBB output for either single-ended use or as a
DC bias for AC coupling to the device. The VBB pin should be used only
as a bias for the LVEL17 as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to ground via a O.Q1~f
capacitor.
Under open input conditions, the l5 input will be biased at VCC/2 and
the D input will be pulled down to VEE. This operation will force the Q
output LOW and ensure stability.
DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

• 325ps Propagation Delay
• High Bandwidth Output Transitions
o >2000V ESD Protection

• Operates from -3.3/-4.5V (or +3.3/+5.0V) Supply

Logic Diagram and Pinout: 20-Lead SOIC (Top View)
~

m
PIN NAMES
Pins

Function

Data Inputs
Data Outputs
Reference Voltage Output

an
VSS

MC100LVEL17
DC CHARACTERISTICS (VEE

=-3.0V to -3.BV; VCC = GND) Note 1
-4D'C

Symbol

Characteristic

Min

lEE

Power Supply Current

VSS

Output Reference Voltage

IIH

Input HIGH Current

IINL

Input LOW Current

Max

-1.38

-1.26

Min

-1.38

150
Dn
Dn

0.5
-300

25'C

D'C

Typ

Max

31
-1.26

Min

Max

-1.38

150
0.5
-300

..
All other DC charactenstlcs are the same as Standard 100K ECL.

4-27

-1.26

Min

-1.38

150
0.5
-300

4195

85'C

Typ

REV 2

0.5
-300

Typ

Max

Unit

-1.26

150

I'A
I'A

MOTOROLA

MC1 OOLVEL 17 MC1 OOEL 17
MC1 OOLVEL17
AC CHARACTERISTICS (VEE = -3.0V to -3.8V; Vee = GND)
DOC

-4DOC
Symbol

Characteristic

Min

IpLH
IpHL

Propagalion Delay
DloO

Dill
S.E.

!sKEW

Skew OulpUI-lo-OulpUll
Part-Io-Part (Diff) 1
Duly Cycle (Diff)2

Typ

330
280

Max

Min

530
580

340
290

Typ

75
200
25

85'C

25'C
Max

Min

540
590

350
300

Typ

75
200
25

Max

Min

550
600

360
310

Typ

75
200
25

Max

Unit

560
610

75
200
25

Vpp

Minimum Inpul Swing 3

150

VCMR

Common Mode Range 4
Vpp< 500mV
Vpp2:500mV

-2.0
-1.8

-0.4
-0.4

-2.1
-1.9

-0.4
-0.4

...,2.1
-1.9

-0.4
-0.4

-2.1
-1.9

-0.4
-0.4

280

550

280

550

280

550

280

550

OUlpul Rise/Fall TImes
(20%-80%)

Ir
If
1.
2.
3.
4.

150

mV
V

Skews are valid across specified vollage range, part-Io-part skew is for a given temperature.
Duly cycle skew is the difference between a TPLH and TPHL propagalion delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of =40.
The CMR range is referenced to the most positive side of the differenlial inpul signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and tv. The lower end of the CMR range varies 1:1 with VEE. The
numbers In the spec table assume a nominal VEE -3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V -IVCMR(min)l.

MC100EL17
DC CHARACTERISTICS (VEE

=-4.2V to -5.5V; Vee = GND) Note 1
-4D'C

Symbol

Characteristic

Min

lEE

Power Supply Current

VBB

Output Reference Voltage

IIH

Input HIGH Current

IINL

Input LOW Current

Q'C

Typ

Max

-1.38

-1.26

Min

Max

-1.38

-1.26

150
Dn
Dn

0.5
-300

25'C

Typ

0.5
-300

85'C

Typ

Max

-1.38

-1.26

150

Min

Typ

Max

Unit

rnA

-1.38

150
0.5
-300

..
All other DC characteristics are the same as Standard lOOK ECL.

Min

-1.26

150

IlA

0.5
-300

IIA

MC100EL17
AC CHARACTERISTICS (VEE = -4.20V to -S.SV; Vee = GND)
-4D'C
Symbol

Characteristic

Min

IpLH
tpHL

Propagation Delay
DtoO

tSKEW

Skew Output-to-Outputl
Part-to-Part (Dill)1
Duly Cycle (Diff)2

Diff
S.E.

330
280

Typ

D'C
Max

Min

530
580

340
290

Typ

75
200
25

85'C

25'C
Max

Min

540
590

350
300

75
200
25

Typ

Max

Min

550
600

360
310

75
200
25

Typ

Max

Unit

560
610

75
200
25

Vpp

Minimum Input Swing3

150

VCMR

Common Mode Range4
Vpp<500mV
Vpp2:500mV

-3.2
-3.0

-0.4
-0.4

-3.3
-3.1

-0.4
-0.4

-3.3
-3.1

-0.4
-0.4

-3.3
-3.1

-0.4
-0.4

280

550

280

550

280

550

280

550

tr
tf
1.
2.
3.
4.

Output Rise/Fall TImes
(20%-80%)

150

Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
Duly cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ~40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = -4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V -IVCMR(min)1.

MOTOROLA

4-28

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual Differential Data and Clock
D Flip-Flop With Set and Reset

MC100LVEL29
MC100EL29

The MC100LVEL29 is a dual master-slave flip flop. The device
features fully differential Data and Clock inputs as well as outputs. The
MC100EL29 is pin and functionally equivalent to the MC100LVEL29 but
is specified for operation at the standard 1OOE ECL voltage supply. A VBB
output is provided for AC coupling, refer to the interfacing section of the
ECLinPS Data Book (DL140) for more information on AC coupling ECL
signals. Data enters the master latch when the clock is LOW and
transfers to the slave upon a positive transition on the clock input.

The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are left
open the D input will pull down to VEE and the 5 input will bias around
VCcJ2. The outputs will go to a defined state, however the state will be
random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset inputs.
Note that the Set and Reset inputs cannot both be HIGH simultaneously.

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-{)4

• 1100MHz Flip-Flop Toggle Frequency
• 2Q-lead SOIC Package
• S80ps Propagation Delays
TRUTH TABLE
Logic Diagram and Pinout: 20-Lead SOIC (Top View)
~

ill

CLK

L
L
H
L
H

L
L
L
H
H

L
H

Z
Z

X
X
X

L
H
L
H
Undef

H
L
H
L
Undef

=LOW to HIGH Transition

PIN NAMES

elKI

Pins

Function

00-01

Data Inputs
Reset Inputs
Clock Inputs
Set Inputs

Ro-Rl
CLKo-CLKI
So-SI

MC100LVEL29
DC CHARACTERISTICS (VEE = -3.0V to -3.8V; VCC = GND)
-4D'C
Symbol

Characteristic

lEE

Power Supply Current

Vee

Output Reference Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

Min

-1.38

D'C

Typ

Max

Min

-1.26 -1.38
150

On Inputs
Dn Inputs

0.5
-300

25'C

Typ

Max

Min

-1.26 -1.38
150

0.5
-300

4-29

Max

Min

-1.26 -1.38
150

0.5
-300

7/95

85'C

Typ

REV I

0.5
-300

Typ

Max

Unit

-1.26

150

ItA
ItA

MOTOROLA

MC100LVEL29 MC100EL29
MC100LVEL29
AC CHARACTERISTICS (VEE = -3.0V to -3.8V; Vee = GND)
-40°C
Characteristic

Symbol
fMAX

Maximum Toggle
Frequency

tplH
tpHl

Propagation Delay
to Output

ts
tH

Setup Time
Hold TIme

Min

O°C
Max

Typ

Min

1.1
ClK
S,R

25°C

Typ

Max

Min

1.1

480
480

680
700

85°C
Max

1.1

490
490

0
100

Typ

690
710

Typ

Max

1.1

500
500

0
100

Min

700
720

0
100

Unit
GHz

720
740

520
520

0
100

tRR

SeVReset Recovery

100

tpw

Minimum Pulse Width
ClK, Set, Reset

400

Vpp

Minimum Input Swing

150

VCMR 1

Common
Vpp<500mV
Mode RangeVpp,,500mV

-2.0
-1.8

-{).4
-{).4

-2.1
-1.9

-{).4
-{).4

-2.1
-1.9

-{).4
-{).4

-2.1
-1.9

-{).4
-{).4

tr
tf

Output Rise/Fall TImes Q
(20%-80%)

280

550

280

550

280

550

280

550

150

..
The CMR range IS referenced to the most positive side of the differential Input signal. Normal operation IS obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = -3.3V. Note for PECl operation, the VCMR(min) will be fixed at 3.3V -IVCMR(min)1.

MC100EL29
DC CHARACTERISTICS (VEE = -4.2V to -5.5V; Vee = GND)
DOC

-4DOC
Symbol

Characteristic

Min

lEE

Power Supply Current

Vee

Output Reference Voltage

IIH

Input HIGH Current

III

Input lOW Current

Typ

Max

-1.38

-1.26

Min

MC100EL29
AC CHARACTERISTICS (VEE

fMAX
tplH
tpHl

Propagation Delay
to Output

ts
tH

Setup Time
Hold TIme

50
-1.26

Min

Max

-1.38

-1.26

150

0.5
-300

85°C

Typ

Min

Typ

Max

Unit

rnA

-1.26

150

1IA

-1.38

150
0.5
-300

0.5
-300

j.IA

=-4.2V to -5.5V; Vee =GND)

Characteristic
Maximum Toggle
Frequency

35
-1.38

-4DOC
Symbol

Max

150
On Inputs
On Inputs

25°C

Typ

Min

DOC

Typ

Max

1.1
ClK
S,R

Min

Typ

Max

1.1

480
480

680
700

0
100

85°C

25°C
Min

Typ

Max

1.1

490
490

690
710

0
100

500
500

Min

Typ

Max

1.1
700
720

0
100

520
520

Unit
GHz

720
740

0
100

tRR

SeitReset Recovery

100

tpw

Minimum Pulse Width
ClK, Set, Reset

400

Vpp

Minimum Input Swing

150

VCMR1

Common
Vpp<500mV
Mode RangeVpp,,500mV

-3.2
-3.0

-{).4
-{).4

-3.3
-3.1

-{).4
-{).4

-3.3
-3.1

-{).4
-{).4

-3.3
-3.1

-{).4
-{).4

tr
tf

Output Rise/Fall TImes Q
(20%-80%)

280

550

280

550

280

550

280

550

150

..
The CMR range IS referenced to the most positive side of the differential Input signal. Normal operation IS obtained If the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE -4.5V. Note for PECl operation, the VCMR(min) will be fixed at 5.0V -IVCMR(min)l.

MOTOROLA

4-30

ECLinPS and ECLinPS Lite
Dl140 - Rev 4

MOTOROILA
SEMICONDUCTOR TECHNICAL DATA

Triple D Flip-Flop
With Set and Reset

MC100LVEL30
MC100EL30

The MC100lVEl30 is a triple master-slave D flip flop with differential
outputs. The MC100El30 is pin and functionally equivalent to the
MC100lVEl30 but is specified for operation at the standard 100E ECl
voltage supply. Data enters the master latch when the clock input is lOW
and transfers to the slave upon a positive transition on the clock input.
In addition to a common Set input individual Reset inputs are provided
for each flip flop. Both the Set and Reset inputs function asynchronous
and overriding with respect to the clock inputs.
• 1200MHz Minimum Toggle Frequency
DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 0-{)4

• 2a-lead SOIC Packaging
• 550ps Typical Propagation Delays
• Set and Reset Inputs
• Supports both Standard and low Voltage 100K Eel
• Internal Input Pulldown Resistors
• >2000V ESD Protection

logic Diagram and Pinout: 20-lead SOIC (Top View)
Vee

Vee

vee

VEE

TRUTH TABLE
R

ClK

l
l
H
l
H

l
l
l
H
H

l
H

Z
Z
X
X
X

l
H
l
H
Undef

H
l
H
l
Undef

X
X
X

Z = lOW to HIGH Transition
PIN NAMES
8012

elKO

elKl

Pins

Function

00-02
RO-R2
CLKO-CLK2
S012

Data Inputs

5/96

4-31

REV2

Reset Inputs
Clock Inputs
Common Set Input

MOTOROLA

MC100LVEL30 MC100EL30
MC100LVEL30
DC CHARACTERISTICS (VEE = -3.0V to -3.8V; Vee = GND)
--4D'C
Symbol

Characteristic

Min

lEE

Power Supply Current

IIH

Input HIGH Current

25'C

O'C

Typ

Max

Min

Typ

Max

Min

Max

150

85'C

Typ

Min

Typ

Max

Unit

rnA

150

I'A

150

MC100LVEL30
AC CHARACTERISTICS (VEE = -3.0V to -3.8V; Vee = GND)
--4D'C
Symbol

Characteristic

Min

Typ

D'C
Max

Typ

25'C
Max

Min

Typ

85°C
Max

1.2

Typ

tplH
tpHl

Propagation Delay
to Output

ts
tH

Setup Time
Hold Time

150
200

0
100

150
200

0
100

150
200

0
100

150
200

0
100

tRR

Set/Reset Recovery

400

200

400

200

400

200

400

200

Minimum Pulse Width
ClK
Set, Reset
Output Rise/Fall Times Q
(20%-80%)

tr
tl

460
470

690
710

470
480

700
720

Max

1.2

480
490

710
730

Unit
GHz

Maximum Toggle
Frequency
ClK
S,R

1.2

Min

IMAX

tpw

1.0

Min

500
515

730
755

ps
ps
ps
ps

400
650

280

550

280

Typ

Max

Min

280

400
650
550

280

Typ

Max

Min

550

Typ

Max

Unit

rnA

150

I1A

MC100EL30
DC CHARACTERISTICS (VEE = --4.2V to -5.5V; Vee = GND)
--40'C
Symbol

Characteristic

Min

lEE

Power Supply Current

IIH

Input HIGH Current

Max

Min

150

MC100EL30
AC CHARACTERISTICS (VEE

85'C

150

=--4.2V to -5.5V; Vee =GND)
--4DOC

Symbol

25°C

D'C

Typ

Characteristic

Min

Typ

25'C

D'C
Max

Typ

Max

Typ

85'C
Max

Min

Typ

Max

1.2

Unit
GHz

Maximum Toggle
Frequency

tplH
tpHl

Propagation Delay
to Output

ts
tH

Setup Time
Hold Time

150
200

0
100

150
200

0
100

150
200

0
100

150
200

0
100

tRR

Set/Reset Recovery

400

200

400

200

400

200

400

200

tpw

Minimum Pulse Width
ClK
Set, Reset

400
650

CLK
S,R

Output Rise/Fall Times Q
(20%-80%)

MOTOROLA

1.2

Min

IMAX

tr
tl

1.0

Min

460
470

690
710

1.2
700
720

470
480

710
730

480
490

500
515

730
755

280

400
650

400
650
550

280

550

4-32

280

400
650
550

280

550

ECLinPS and ECLinPS Lite
Dl140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview
+2 Divider

MC100LVEL32

The MC100LVEL32 is an integrated +2 divider. The differential clock
inputs and the VBB allow a differential, single-ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a O.01I1F capacitor. Also note that the VBB is designed to be
used as an input bias on the LVEL32 only, the VBB output has limited
current sink and source capability. The LVEL32 is functionally identical to
the EL32, but operates from a low voltage supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random state; the reset
allows for the synchronization of multiple EL32's in a system.
o 510ps Propagation Delay

o SUFFIX
PLASTIC sOle PACKAGE
CASE 751-05

o 3.0GHz Toggle Frequency
o High Bandwidth Output Transitions
o 75k.Q Internal Input Pulldown Resistors
o >1000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

PIN DESCRIPTION

Vas

FUNCTION

CLK
Reset
VBB

Clock Inputs
Asynch Reset
Ref Voltage Output
DataOuputs

VEE

This document contains infonnation on a product under development. Motorola reserves the right to change or
discontinue this product without notice.

5196

4-33

REV 0

MOTOROI.A

MC100LVEL32
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-4D'C
Characteristic

Symbol

Min

Typ

lEE

Power Supply Current

VEE

Power Supply Voltage

-3.0

Vee

Output Reference Voltage

IIH

Input HIGH Current

-1.38

D'C
Max

Min

Typ

25'C
Max

Min

25
-3.0

-3.3

-1.26 -1.38

Typ

Min

-3.8

-3.0

-3.3

Typ

-3.8

-3.0

-3.3

-1.26 -1.38

150

Max

-1.26 -1.38

150

85'C
Max

150

Unit
mA

-3.8

-1.26

150

AC CHARACTERISTICS (VEE = VEE (min) to VEE(max); Vee = GND)
-40'C
Symbol

Characteristic

fMAX

Maximum Toggle
Frequency

tpLH
tpHL

Propagation Delay
CLKtoQ
ResettoQ

VPP

Minimum Input Swing1

tr
tf

Output Rise/Fall limes Q
(20%-80%)

Min

Typ

O'C
Max

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

3.0

500
540

510
540

540
550

150

150
225

225

Unit
GHz

ps
mV

150
225

Max

225

..
MInimum Input sWing for which AC parameters are guaranteed.

elK

RESET

Figure 2. Timing Diagram

MOTOROLA

4-34

ECLinPS and ECLinPS Lite
DL140-Rev4

Ii\IiI 1500V ESD Protection

ClK

Z
ZZ

l
H

l
L
H

FUNCTION

a Low Voltage VEE Range of -3.0 to -3.8V

Pinout: 20-lead SOIC (Top View)
vee

VEE

[2fr] [19] [18J [17] G6J [i5] [14] [E] [i2] [11J

1LiJ
Vee

liil
liJ liJ W liJ liJ LiJ liJ liJ
EN DIV_SEl elK elK Vss MR Vee "5
';, 1"5
~'
~ c.

Z = Low-to-High Transition
ZZ = High-to-low Transition
DIVSEL
0

10/94

4..;35

Divide
Hold QQ-3
ResetQo-3

REV I

02. 03 OUTPUTS
Divide by 4
Divide by6

MOTOROLA

MC100LVEL38 MC100EL38

LOGIC DIAGRAM

00
elK --...,....,...--------f".

elK

00
01

Of
EN----I

Q2
03
MR---------.--------~--~

DIVSEl ---------+--------~-------'
PHASE_OUT
PHASE_OUT

elK
0(+2)

0(-+<\)

'------',

-.J

o (+6)-.J

J I___~nL___~nL___----lnL___----J11
Phase_Ou1(+6) J I_______--JI1L-______----'nL.______
Phase_Ou1(-+<\)

Figure 1. Timing Diagrams

MOTOROLA

4-36

ECLinPS and ECLinPS Lite
DL140-Rev4

MC100LVEL38 MC100EL38
MC100LVEL38
DC CHARACTERISTICS (VEE = -3.BV

to -3.0; Vee = GND)
-40'C

Symbol

Characteristic

lEE

Power Supply Current

VBB

Output Reference Voltage

IIH

Input High Current

Min

Max

-1.38

-1.26

Min

Max

-1.38

-1.26

85'C

Typ

Max

-1.38

-1.26

Min

Typ

Max

Unit

-1.38

150

-1.26

150

Max

Unit

=-3.BV to -3.0; Vee = GND)

Characteristic

Min

fMAX

Maximum Toggle Frequency

1000

tpLH
tpHL

Propagation Delay
CLK -> 0 (Diff)
toOutpul
CLK -> 0 (S.E.)
CLK -> Phase_Out (Dill)
CLK -> Phase_Out (S.E.)
MR->O

760
710
800
750
510

tSKEW

Within-Device Skew 1

25'C

O'C
Max

Typ

Min

Typ

Max

1000
960
1010
1000
1050
810

00- 0 3

All
Part-to-Part

Min

150

-40'C
Symbol

Typ

150

MC100LVEL38
AC CHARACTERISTICS (VEE

25'C

O'C

Typ

00-03 (Diff)

All

Min

Typ

85'C
Max

1000

780
730
820
770
530

980
1030
1020
1070
830

Min

Typ

MHz

1000

800
750
840
790
540

1000
1050
1040
1090
840

850
800
890
840
570

1050
1100
1090
1140
870

50
75

200
240

Setup1ime

EN->CLK
DIVSEL -> CLK

150

Hold1ime

CLK-> EN
CLK -> Div_Sel

150
200

Vpp2

Minimum Input Swing

CLK

250

VCMR3

Common Mode Range

CLK

-0.55

tRR

Reset Recovery Time

tpw

Minimum Pulse Width

CLK
MR

800
700

to tf

Output Rise/Fall1imes 0 (20% - 80%)

280

250

See3

-0.55

100

See3
100

800
700

550

-0.55

280

-0.55

100
800
700

550

280

250

See3

100

ps
ps

800
700
550

280

550

1. Skew IS measured between outputs under Identical transitions .
2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vpp Min and 1.0V. The lower end of the CMR range is dependent on VEE and
is equal to VEE + 1.6SV.

ECLinPS and ECLinPS Lite
DLI40-Rev4

4-37

MOTOROLA

MC100LVEL38 MC100EL38
MC100EL38
DC CHARACTERISTICS (VEE

=-4.2V to -5.46; Vee = GND)
DOC

-40°C
Symbol

Characteristic

lEE

Power Supply Current

Vee

Output Relerence Voltage

IIH

Input High Current

Min

Typ

Max

-1.38

-1.26

Min

25°C

Typ

Max

-1.38

-1.26

150

Min

85°C

Typ

Max

-1.38

-1.26

150

Min

Typ

Max

Unit

-1.38

150

-1.26

150

Max

Unit

MC100EL38
AC CHARACTERISTICS (VEE = -4.2V to -5.46; Vee = GND)
-4DOC
Symbol

Characteristic'

Min

IMAX

Maximum Toggle Frequency

1000

tplH
tpHl

Propagation Delay
ClK ... O(Dill)
to Output
ClK ... 0 (S.E.)
ClK ... Phase_Out (Dill)
elK ... Phase_Out (S.E.)
MR ... O

760
710
800
750
510

tSKEW

Within-Device Skew1

Typ

DOC
Max

Min

Typ

25°C
Max

1000
960
1010
1000
1050
810

00- 0 3
All

Min

Typ

85°C
Max

1000

780
730
820
770
530

980
1030
1020
1070
830

Min

Typ

1000

800
750
840
790
540

1000
1050
1040
1090
940

MHz

850
800
890
940
570

1050
1100
1090
1140
870

50
75

200
240

Part·to·Part

00-03 (Dill)
All

Setup TIme

EIiI ... (;[R
DIVSEl ... CLK

150

Hold TIme

ClK ... EN
ClK ... Div_Sel

150
200

Vpp2

Minimum Input Swing

CLK

250

VCMR3

Common Mode Range

ClK

-0.55

tRR

Reset Recovery TIme

tpw

Minimum Pulse Width

ClK
MR

800
700

tr,tf

Output RlselFall TImes 0 (20% - 80%)

280

250
See3

-0.55

100

250
See3
100

800
700
550

-0,55

280

250
See3
100

800
700
550

-0.55

280

mV
See3

100

800
700
550

280

ps
550

"
I, Skew is measured between outputs under Identical tranSItions,
2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to IOOmV,
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level fails within
the specified range and the peak-to-peak voltage lies between Vpp Min and I.OV. The lower end of the CMR range is dependent on VEE and
is equal to VEE + 1,65V.

MOTOROLA

4-38

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

+2/4, +4/6 Clock
Generation Chip

MC100LVEL39
MC100EL39

The MC100LVEL39 is a low skew +2/4, +4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but
is specified for operation at the standard lOOK ECL voltage supply. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended LVECL or, if positive power supplies are
used, LVPECL input signal. In addition, by using the VSS output, a
sinusoidal source can be AC coupled into the device (see Interfacing
section of the ECLinPSTM Data Book DL 14010). If a single-ended input is
to be used, the VSS output should be connected to the CLK input and
bypassed to ground via a O.ot /!F capacitor. The VSS output is designed to
act as the switching reference for the input of the LVEL39 under
single-ended input conditions, as a result, this pin can only source/sink up
to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL39s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL39, the MR pin need not be exercised as the internal divider
design ensures synchronization between the +2/4 and the +4/6 outputs of
a single device.
• 50ps Output-to-Output Skew

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-04

PIN DESCRIPTION
PIN

FUNCTION

ClK
EN
MR
Ves

Dill Clock Inputs
Sync Enable
Master Reset
Reference Output
Dill +214 Outputs
Dill +4/6 Outputs
Frequency Select Input

00. 0 1
02,03
DIVSEL

FUNCTION TABLE
ClK

Z
ZZ

L
H

L
L
H

FUNCTION

o Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kQ Internal Input Pulldown Resistors
• >2000V ESD Protection

Z = Low-to-High Transition
ZZ = High-to-low Transition

• Low Voltage VEE Range of -3.0 to -3.8V

DIVSELa

Pinout: 2D-lead SOIC (Top View)
VCC

[20] [jS] [j8] [1!]

Gal

[1S] [t4] @l [)?]

VEE

Gil

0
1

1ill LiJWW W liJ LiJ liJliJ liQ] r
Vcc

EN DIVSELb ClK

ClK

Vee

VCC

DIVSELb

0
1

4--39

QQ, Q1 OUTPUTS
Divide by 2
Divide by4

Q2, Q3 OUTPUTS
Divide by 4
Divide by6

NC DIVSEla

3/96

Divide
Hold 00-3
Reset 00-3

REV 2

MOTOROL.A

MC100LVEL39 MC100EL39
LOGIC DIAGRAM
DIVSEla-----------------,

00
elK --f"",,""---f'-...

elK

Q1
02

EN----l

MR-------------J

DIVSElb-----------------'

elK

0(+2)

0(+4)~

L....-_....JI

'L-I_ _...J

0(+6)~
Figure 1. Timing Diagrams

MC100LVEL39
DC CHARACTERISTICS (VEE

=-3.BV to -3.0; Vee = GND)
-40°C

Symbol

Characteristic

lEE

Power Supply Current

Vee

Output Reference Voltage

IIH

Input High Current

Min

O°C

Typ

Max

-1,38

-1.26

Min

59
-1,26

150

MC100LVEL39
AC CHARACTERISTICS (VEE

Min

Typ

Max

59
-1,26

-1.38

150

Min

Typ

Max

Unit

-1.38

150

-1.26

150

JlA

Max

Unit

=-3.BV to -3.0; Vee = GND)
-40°C

Characteristic

Symbol

Typ

-1.38

85°C

25°C
Max

Min

f~AX

Maximum Toggle Frequency

1000

tplH
tpHl

Propagation Delay
to Output

760
710
600

tSKEW

Within-Device Skew1

ClK-->O(Diff)
CLK --> 0 (S.E.)
MR-->O

Typ

O°C
Max

Min

Typ

25°C
Max

1000
960
1010
900

780
730
600

Min

Typ

05°C
Max

800
750
610

Typ

1000

1000
980
1030
900

Min

1000
1050
910

850
800
630

MHz
1050
1100
930

00- 0 3

Part-to-Part

00-03 (Diff)

200

Setup lime

EN -->ern:
DIVSEL-->ClK

250
400

.250
400

250
400

Hold lime

C1R-->EN
CLK --> Div_Sel

100
150

MOTOROLA

4-40

ECLinPS and ECLinPS Lite
DL140-Rev4

MC100LVEL39 MC100EL39

MC100LVEL39 (continued)
AC CHARACTERISTICS (VEE = -3.8V to -3.0; Vee = GND)
QOC

-4QOC
Characteristic

Symbol

Min

Vpp

Minimum Input Swing

ClK

250

VCMR

Common Mode Range3
Vpp<5OOmV

-2.0

Vpp~500mV

tRR

Reset Recovery Time

tpw

Minimum Pulse Width

Typ

Max

Min

Typ

Min

Typ

85°C
Max

250

Min

Typ

Max

Unit
mV

250

V
-0.4
-0.4

-1.8

-2.1
-1.9

-0.4
-0.4

100
ClK
MR

25°C
Max

500
700

-2.1
-1.9

-0.4
-0.4

100
500
700

-2.1
-1.9

-0.4
-0.4
100

100
500
700

ps
ps

500
700

Output RiseiFalilimes a (20% -80%) 280
280
550
550
ps
550
280
550
280
to tf
..
1. Skew IS measured between outputs under Identical transllions .
2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = -3.3V. Note for PECl operation. the VCMR(min) will be fixed at 3.3V - IVCMR(min)1.

MC100EL39
DC CHARACTERISTICS (VEE = -4.2V to -5.46; Vee = GND)
-4QOC
Symbol

Characteristic

lEE

Power Supply Current

VBB

Output Reference Voltage

IIH

Input High Current

Min

Q'C

Typ

Max

-1.38

-1.26

Min

25°C

Typ

Max

-1.38

-1.26

150

Min

85°C

Typ

Max

-1.38

-1.26

Min

Typ

Max

Unit

-1.38

150

-1.26

150

IlA

Max

Unit

MC100EL39
AC CHARACTERISTICS (VEE = -4.2V to -5.46; Vee = GND)
QOC

-4Q'C
Characteristic

Symbol

Min

fMAX

Maximum Toggle Frequency

1000

tplH
tpHl

Propagation Delay
to Output

760
710
600

tSKEW

Within-Device Skew 1

ClK--> a (Diff)
ClK --> a (S.E.)
MR-->a

Typ

Max

Min

Typ

25°C
Max

1000
960
1010
900

780
730
600

Min

Typ

85°C
Max

1000
980
1030
900

800
750
610

Min

Typ

1000
1000
1050
910

850
800
630

MHz
1050
1100
930

aO-a3

Part-to·Part

aO-a3 (Dif!)

200

Setup lime

EN --> CIJ(
DIVSEl-->ClK

250
400

Hold lime

CLK-->EN
ClK --> Div_Sel

100
150

Vpp

Minimum Input Swing

ClK

250

VCMR

Common Mode Range3

Vpp< 500mV
Vpp~5OOmV

-3.2
-3.0

ClK
MR

500
700

tRR

Reset Recovery Time

tpw

Minimum Pulse Width

V
-0.4
-0.4

-3.3
-3.1

100

-0.4
-0.4

-3.3
-3.1

100
500
700

-0.4
-0.4

-3.3
-3.1

100
500
700

-0.4
-0.4
100

500
700

ps
ps

ps
Output RiseiFalilime. a (20% - 80%) 280
550
280
280
550
280
550
550
to tf
..
1. Skew IS measured between outputs under Identical transitions.
2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
3. The CMR range is referenced to the most positive side of the differential input signal. Nonmal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = -4.5V. Note for PECl operation. the VCMR(min) will be fixed at S.QV -IVCMR(min)1.

ECLinPS and ECLinPS Lite
Dl140-Rev4

4-41

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview

Differential Clock D Flip-Flop

MC100LVEL51

The MC100lVEl51 is a differential clock D flip-flop with reset. The
device is functionally equivalent to the El51 device, but operates from a
low voltage supply. With propagation delays and output transition times
essentaially equal to the El51, the lVEl51 is ideally suited for those
applications which require the ultimate in AC performance at 3.3V VCC.
The reset input is an asynchronous, level triggered signal. Data enters
the master portion of the flip-flop when the clock is lOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs 01 the lVEl51 allow the device to
be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under
open input conditions. When left open, the ClK input will be pulled down
to VEE and the ClK input will be biased at VCcJ2.
o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05

• 475ps Propagation Delay
• 2.8GHz Toggle Frequency
• 75kn Internal Input Pulldown Resistors
• >1000V ESD Protection

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

R 1

o
TRUTH TABLE

21----10

VEE
Z

elK

=lOW to HIGH Transition

This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
5/96

4-42

REV 0

MOTOROLA

MC100LVEL51
DC CHARACTERISTICS (VEE

=VEE(min) to VEE(max); Vee = GND)
-40"C

Symbol

Characteristic

Min

lEE

Power Supply Current

VEE

Power Supply Voltage

IIH

Input HIGH Current

Typ

Min

24
-3.0

-3.3

25"C

O"C
Max

lYP

Max

Min

24
-3.8

-3.0

-3.3

lYP

Min

24
-3.B

-3.0

-3.3

Typ

Max

24
-3.B

-3.0

-3.3

150

85"C
Max

Unit
mA

-3.8

150

IlA

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); Vee = GND)
-40"C
Symbol

Characteristic

fMAX

Maximum Toggle
Frequency

tpLH
tpHL

Propagation Delay
to Output

Min

Typ

25"C

O"C
Max

Min

Typ

Max

Min

Typ

85"C
Max

Min

lYP

2.8

2.B

465
455

,475
465

530
510

Max

Unit
GHz
ps

CLK
R

Setup TIme

Hold TIme

100

tRR

Reset Recovery

200

tpw

Minimum Pulse Width
CLK, Reset

400

Vpp

Minimum Input Swing 1

150

VCMR

Common Mode Range2

tr
tf

Output Rise/Fall TImes Q
(20%-BO%)

V
225

225

1. MInimum Input sWing for whIch AC parameters are guaranteed.

ECLinPS and ECLinPS Lite
DL140-Rev4

4-43

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Dual Differential
2: 1 Multiplexer

MC100LVEL56
MC100EL56

The MC100lVEl56 is a dual, fully differential 2:1 multiplexer. The
MC100El56 is pin and functionally equivalent to the MC100lVEL56 but
is specified for operation at the standard 100E ECl voltage supply. The
differential data path makes the device ideal for multiplexing low skew
clock or other skew sensitive signals. Multiple VBB pins are provided to
ease AC coupling input signals (for more information on AC coupling ECl
signals refer to the interfacing section of the ECLinPS data book

Dl140/D).
The device features both individual and common select inputs to
address both data path and random logic applications.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs are left
open the D input will pull down to VEE, The 0 input will bias around VCct2
forcing the Q output lOW.

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-04

• Differential Inputs and Outputs
• 20-lead SOIC Packaging
• 440ps Typical Propagation Delays
• Separate and Common Select
• Supports Both Standard and low Voltage 100K ECl

TRUTH TABLE

• Internal Input Pulldowns

SEl

Data

• >2000V ESD Protection

logic Diagram and Pinout: 20-lead

sOle (Top View)

....r

Vee

DOa

VBBO

SELO

OO~I

DOb

SEll

Dla

Vee

PIN NAMES
Pins

Function

OOa-Ola
OOb-Olb
SELD-SELl
COM_SEL
QO-Ql
QO-Ql

Input Data a
Input Data b
Individual Select Input
Common Select Input
True Outputs
Inverted Outputs

Dla VBBl

4195

4-44

REVt

MOTOROLA

MC100LVEL56 MC100EL56
MC100LVEL56
DC CHARACTERISTICS (VEE = -3.0V to -3.8V; Vee = GND)
-4DOC
Symbol

Characteristic

Min

lEE

Power Supply Current

VBB

Output Reference Voltage -1.38

IIH

Input HIGH Current

"Nl

Input lOW Current

Vpp(DC)

Input Sensitivity1

DOC

Typ

Max

24
-1.26

Min

Typ

Max

-1.38

-1.26

150
Dn
Dn

2SoC
Min

OsoC

Typ

Max

-1.38

-1.26

150

Min

Typ

Max

Unit

rnA

-1.38

150

-1.26

150

I1A

0.5
-600

!LA

1. Differential Input voltage reqUired to obtain a full ECl sWing on the outputs.

MC100LVEL56
AC CHARACTERISTICS (VEE

=-3.0V to -3.8V; Vee =GND)
-4DOC

Symbol

Characteristic

Typ

DOC
Max

Min

540
590
730
730

350
300
440
440

Typ

OsoC

2SoC
Max

Min

550
600
740
740

360
310
440
440

Typ

Max

Min

560
610
740
740

380
330
450
450

tPlH
tpHl

Propagation
Delay
to Output

tSKEW

Within-Device Skew1

tSKEW

Duty Cycle Skew2

Vpp(AC)

Minimum Input Swing 3

150

1000

150

1000

150

1000

VCMR

Common Mode Range 4
Vpp<500mV
Vpp2:500mV

-2.0
-1.8

-0.4
-0.4

-2.1
-1.9

-0.4
-0.4

-2.1
-1.9

200

540

200

540

200

tr
tf

D (Dill)
D(SE)
SEl
COMSEl

Min

Output Rise/Fall Times Q
(20%-80%)

340
290
430
430
40

100

Typ

Max

Unit

580
630
750
750

100

150

1000

-0.4
-0.4

-2.1
-1.9

-0.4
-0.4

540

200

540

100

..
Within-deVice skew IS defined as Identical tranSItions on similar paths through a deVice.

1.
2. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
3. Minimum input swing for which AC parameters are guaranteed.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained ilthe HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE -3.3V. Note for PECl operation. the VCMR(min) will be fixed at 3.3V -IVCMR(min)1.

ECLinPS and ECLinPS Lite
Dl140-Rev4

4-45

MOTOROLA

MC100LVEL56 MC100EL56
MC100EL56
DC CHARACTERISTICS (VEE = -4.2V to -S.SV; Vee = GND)
-40'C
Symbol

Characteristic

Min

lEE

Power Supply Current

VBB

Output Reference Voltage -1.38

IIH

Input HIGH Current

IINL

Input LOW Current

Vpp(DC)

Input Sensitivity1

O'C

Typ

Max

24
-1.26

Min

Max

-1.38

-1.26

150
Dn
Dn

25'C

Typ

Min

85'C

Typ

Max

-1.38

-1.26

150

Min

Typ

Max

Unit

-1.38

150

0.5
-600

-1.26

150

!lA
!lA
V

1. Differential Input voltage required to obtain a full ECL sWing on the outputs.

MC100EL56
AC CHARACTERISTICS (VEE = -4.2V to -S.SV; Vee = GND)
-40'C
Symbol
tpLH
tpHL

Characteristic
Propagation
Delay
·to Output

D (Diff)
D(SE)
SEL
COMSEL

Min

Typ

340
290
430
430

25'C

O'C
Max

Min

540
590
730
730

350
300
440
440

Typ

Max

Min

550
600
740
740

360
310
440
440

Typ

85'C
Max

Min

560
610
740
740

380
330
450
450

tSKEW

Within-Device Skew 1

tSKEW

Duty Cycle Skew2

Vpp(AC)

Minimum Input Swing 3

150

1000

150

1000

150

1000

VCMR

Common Mode Range 4
Vpp<500mV
Vpp<:500mV

-3.2
-3.0

-0.4
-0.4

-3.3
-3.1

-0.4
-0.4

-3.3
-3.1

200

540

200

540

200

tr
tf

Output Rise/Fall TImes Q
(20%-80%)

100

80
100

Typ

100

Max

Unit

580
630
750
750

100

150

1000

-0.4
-0.4

-3.3
-3.1

-0.4
-0.4

540

200

540

..
Within-device skew IS defined as Identical transitions on similar paths through a deVice.

1.
2. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
3. Minimum input swing for which AC parameters are guaranteed.
4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = -4.5V. Note for PECL operation. the VCMR(min) will be fixed at 5.0V -IVCMR(min)1.

MOTOROLA

4-46

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple 2: 1 Multiplexer

MC100LVELS9
MC100ELS9

The MC100LVEL59 is a triple 2:1 multiplexer with differential outputs.
The MC1 OOEL59 is pin and functionally equivalent to the MC100LVEL59
but is specified for operation at the standard 100E ECL voltage supply.
The output data of the muxes can be controlled individually via the select
inputs or as a group via the common select input. The flexibile selection
scheme makes the device useful for both data path and random logic
applications.
o Individual or Common Select Controls
o 20-Lead SOIC Packaging
o 500ps Typical Propagation Delays
o Supports Both Standard and Low Voltage 100K ECL

OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-{)4

o Intemallnput Pulldown Resistors
o >2000V ESD Protection

Logic Diagram and Pinout: 20-Lead sOle (Top View)
Vee

Vee

vee

VEE

TRUTH TABLE
SEL

Data

H
L

a
b

PIN NAMES
2

eOM_SEL DOa

DOb

SELO Dta

Dlb SEll D2a

D2b SEL2

Pins

Function

DOa-Dla
DOb-Dlb
SELO-8EL1
COM_SEL

Input Data a
Input Data b
Individual Seleetlnput
Common Select Input
True Outputs
Inverted Outputs

00-02
0O-Q2

4195

4-47

REV 1

MOTOROI.A

MC100LVEL59 MC100EL59
MC100LVEL59
DC CHARACTERISTICS (VEE = -3.0V to -3.BV; Vee = GND)
DOC

-4DOC
Symbol

Characteristic

lEE

Power Supply Current

IIH

Input HIGH Current

MC100LVEL59
AC CHARACTERISTICS (VEE

Min

Typ

Max

Min

85°C

Typ

Max

150

Min

Typ

Max

Unit

rnA

150

!lA

Max

Unit

690
690
690

150

=-3.0V to -3.BV; Vee =GND)

Characteristic

Min

tpLH
tpHL

Propagation DATA....OIQ
Delay
SEL....QlO
COM_SEL....QlQ

340
340
340

tsk(O)

Output-Output Skew
Any Dn. Drn to 0
Output RiselFalilirnes 0
(20%-80%)

tr
tf

Max

150

DOC

-40°C
Symbol

25°C

Typ

Max

Min

690
690
690

340
340
340

85°C

25°C

Typ

Max

Min

690
690
690

340
340
340

Typ

Max

Min

690
690
690

340
340
340

Typ

ps
100
200

540

200

540

100

100
200

540

200

540

Typ

Max

Unit

rnA

150

!lA

Max

Unit

690
690
690

MC100EL59
DC CHARACTERISTICS (VEE = -4.2V to -5.5V; Vee = GND)
DOC

-4DOC
Symbol

Characteristic

lEE,

Power Supply Current

IIH

Input HIGH Current

Min

Typ

Max

Min

Max

150

85°C

25°C

Typ

Min

Typ

Max

150

Min

150

MC100EL59
AC CHARACTERISTICS (VEE = -4.2V to -5.5V; Vee = GND)
DOC

-4DOC
Symbol

Characteristic

Min

tpLH
tpHL

Propagation DATA.... OiQ
Delay
SEL....QlO
COM_SEL.... QlQ

340
340
340

tsk(O)

Output-Output Skew
Any Dn. Drn to 0

tr
tf

Output Rise/Falilirnes 0
(20%-80%)

MOTOROLA

Typ

Max

Min

690
690
690

340
340
340

Typ

85°C

25°C
Max

Min

690
690
690

340
340
340

Typ

Max

Min

690
690
690

340
340
340

Typ

ps
100
200

540

100
200

540

4-48

100

100
200

540

200

540

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple ECL to PECL Translator
The MC100lVEUEl90 is a triple ECl to PECl translator. The device
receives either standard or low voltage differential ECl signals and
translates them to either standard or low voltage differential PECl output
signals. The lVEl device can handle the low voltage signals while the El
device is designed for the standard signals. It is possible to have low
voltage signals on one side and standard signals on the other if the
lVEl90 is used.

MC100LVEL90
MC100EL9(D

o SOOps Propagation Delays
o Fully Differential Design

• Supports both Standard and low Voltage Operation
o

20-lead SOIC Packaging

A VBB output is provided for interfacing with single ended ECl signals
at the input. If a single ended input is to be used the VBB output should be
connected to the 0 input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a 0.011lF
capacitor. The VBB output is designed to act as the switching reference
for the El90 under single ended input switching conditions, as a result
this pin can only source/sink up to 0.5mA of current.

DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04

To accomplish the level translation the EUlVEl90 requires three
power rails. The VCC supply should be connected to the positive supply,
and the VEE pin should be connected to the negative power supply. The
GND pins as expected are connected to the system ground plain. Both
VEE and VCC should be bypassed to ground via 0.011lF capacitors.
Under open input conditions, the 0 input will be biased at VEE/2 and
the D input will be pulled to VEE. This condition will force the Q output to a
lOW, ensuring stability.

PIN NAMES
Pins

Function

On
an
Ves

Eel Inputs
PEel Outputs
Eel Reference Voltage Output

Logic Diagram and Pinout: 20-Lead sOle (Top View)
Vee

GND

ill

Vee

GND

Vee

7/95

4-49

REV 1

MOTOROLA

MC100LVEL90 MC100EL90

ECl INPUT DC CHARACTERISTICS
-40'C
Symbol

Characteristic

25'C

O'C

Min

Max

Min

Max

Min

-4.2

-5.5

-4.2

-5.5

~.O

~.8

~.O

~.8

Typ

85'C
Max

Min

Max

Unit

-4.2

-5.5

~.O

~.8

-4.2
-3.0

VEE

Power Supply
Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

0.5

Vpp

Minimum Peak-to-Peak

150

EL90
LVEL90

ISO

~.8

150

Condition

150

Input1
VIH

Input HIGH Voltage

-1165

-880

-1165

-880

-1165

-880

-1165

-880

VIL

Input LOW Voltage

-1810

-1475

-1810

-1475

-1810

-1475

-1810

-1475

Vee

Reference Output

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

-1.38

-1.26

8.0

Power Supply Current
8.0
lEE
1. 150mV Input guarantees full logic sWing at the output.

8.0

6.0

8.0

lVPECl OUTPUT DC CHARACTERISTICS
-40'C
Symbol

O'C

25'C

85'C

Characteristic

Min

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

Vee

Power Supply Voltage

3.0

3.8

3.0

3.8

3.0

3.3

3.8

3.0

3.8

VOH

Output HIGH Voltage1

2.215

2.42

2.275

2.42

2.275

2.35

2.42

2.275

2.42

Vee = 3.3V

VOL

Output LOW Voltage1

1.47

1.745

1.49

1.68

1.49

1.60

1.68

1.49

1.68

Vec=3.3V

IGND

Power Supply Current

rnA

Condition

1. Levels Will vary 1:1 wllh Vec.

PECl OUTPUT DC CHARACTERISTICS
-40'C
Symbol

O'C

25'C

Min

Max

Min

Max

Min

Vce

Power Supply Voltage

4.75

5.25

4.75

5.25

4.75

VOH

Output HIGH Voltage1

3.915

4.12

3.975

4.12

3.975

VOL

Output LOW Voltage 1

3.17

3.445

3.19

3.38

3.19

Power Supply Current
IGND
1. Levels Will vary 1:1 With Vcc.

MOTOROLA

4-50

Typ

85'C

Characteristic

Max

Min

Max

Unit

5.25

4.75

5.25

Condition

4.05

4.12

3.975

4.12

Vec=5.0V

3.30

3.38

3.19

3.38

VCC=5.0V

rnA

ECLinPS and ECLinPS Lite
DL140-Rev4

MC100LVEL90 MC100EL90
MC100LVEL90
AC CHARACTERISTICS (VEE = -3.0V to -a.8V; Vee = 3.0V to 3.8V)
-4D'C
Symbol

Characteristic

Min

tpLH
tpHL

Propagation Delay
DtoO

tSKEW

Skew Output-to-Output1
Part-ta-Part (Diff)l
Duty Cycle (Diff)2

Vpp

Minimum Input Swing3

150

VCMR

Common Mode Range 4

See4

tr
tf

Output Rise/Fall Times
(20%-80%)

I.
2.
3.
4.

Diff
S.E.

Typ

390
340
20

D'C
Max

Min

590
640

410
360

100
200

Typ

25'C
Max

Min

610
660

420
370

100
200

230

500

85'C
Max

Min

620
670

460
410

100
200

-{).4

230

500

Max

Unit

660
710

100
200

25
150

150

See4

Typ

150
-{).4

Typ

See4

-{).4

230

500

See4

-{).4

230

500

V
ps

Skews are valid across specified voltage range, part-ta-part skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ~40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV. VCMRmin depends on VEE, Vpp and temperature. At
Vpp < 500mVand -40°C, VCMRisVEE+I.3V;andforD-85°C, VCMRisVEE+I.2V.AtVpp;,500mVand-40'C, VCMR isVEE+l.5V; and for
0-85'C, VCMR is VEE +1.4V.

MC100EL90
AC CHARACTERISTICS (VEE = -4.20V to -5.5V; Vee = 4.5V to 5.5V)
DOC

-4D'C
Symbol

Characteristic

Min

tpLH
tpHL

Propagation Delay
DtoO

Diff
S.E.

tSKEW

Skew Oulput-to-Output1
Part-ta-Part (Diff) 1
Duty Cycle (Diff)2

390
340
20

Minimum Input SWing 3

150

VCMR

Common Mode Range 4

See4

tr
tf

Output Rise/Fall TImes
(20%-80%)

1.
2.
3.
4.

Max

Min

590
640

410
360

100
200

230

Typ

25°C
Max

Min

610
660

420
370

100
200

500

85°C
Max

Min

620
670

460
410

100
200

-{).4

230

500

See4
230

Max

Unit

660
710

100
200

ISO

See4

Typ

150
-{).4

Typ

Vpp

Typ

ISO
-{).4
SOO

See4
230

mV
-{).4
SOO

V
ps

Skews are valid across specified voltage range, part-ta-part skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ~40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and lV. VCMRmin depends on VEE, Vpp and temperature. At
Vpp < SOOmVand -40°C, VCMR is VEE+l.3V;andforD-8SoC, VCMRis VEE+l.2V.AtVpp;,SOOmVand-40°C, VCMRis'VEE+l.SV;andfor
D-SSoC, VCMR is VEE +l.4V.

ECLinPS and ECLinPS Lite
DL140-Rev4

4-S1

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview
Triple PECL to ECL Translator

MC100LVEL91
MC100EL91

The MC100lVEUEl91 is a triple PECl to ECl translator. The device
receives either standard or low voltage differential PECl signals and
translates them to either standard or low voltage differential ECl output
signals. The lVEl device can handle the low voltage signals while the El
device is designed for the standard signals. It is possible to have low
voltage signals on one side and standard signals on the other if the
lVEl91 is used.
•
•
•
•

550ps Propagation Delays
Fully Differential Design
Supports both Standard and low Voltage Operation
2Q-lead SOIC Packaging

A VBB output is provided for interfacing with single ended PECl signals
at the input. If a single ended input is to be used the VBB output should be
connected to the "5 input. The active signal would then drive the D input.
When used the VBB output should be bypassed to ground via a O.D1IlF
capacitor. The VBB output is designed to act as the switching reference
for the El91 under single ended input switching conditions, as aresult this
pin can only sourcefsink up to O.5mA of current.
To accomplish the level translation the EUlVEl91 requires three
power rails. The VCC supply should be connecfed to the positive supply,
and the VEE pin should be connected to the negative power supply. The
GND pins as expected are connected to the system ground plain. Both
VEE and VCC should be bypassed to ground via O.OlIlF capacitors.
Under open input conditions, the "5 input will be biased at VCcJ2 and
the D input will be pulled to GND. This condition will force the Q output to
a low, ensuring stability.

logic Diagram and Pinout: 20-lead sOle (Top View)
Vee

GND

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-04

PIN NAMES
Pins

Function

On
an
PECl_VBB

PECl Inputs
EClOutputs
PECl Reference Voltage Output

Vee

This document contains infonnation on a product under development. Motorola reserves the right to
change or discontinue this product without notice.

7/96

4-52

REV 0.2

MOTOROLA

MC100LVEL91 MC100EL91

lVPECl INPUT DC CHARACTERISTICS
-4D'C
Symbol
VCC

25'C

D'C

85'C

Characteristic

Min

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

Power Supply Voltage

3.0

5.25

3.0

5.25

3.0

3.3

5.25

3.0

5.25

150

(.IA

150

IIH

Input HIGH Current

IlL

Input LOW Current

VIH

Input HIGH Voltage 1

2.135

2.420

2.135

2.420

2.135

2.420

2.135

2.420

VCC = 3.3V

VIL

Input LOW Voltage 1

1.49

1.825

1.49

1.825

1.49

1.825

1.49

1.825

VCC =3.3V

VSS

Reference Outputl

1.92

2.04

1.92

2.04

1.92

2.04

1.92

2.04

Vce=3.3V

0.5

150

Condition

0.5

Power Supply Curremt
IGND
1. DC levels vary 1: 1 with V CC.

(.IA

0.5

6.0

PECl INPUT DC CHARACTERISTICS
D'C

-4D'C
Symbol

85'C

25'C

Characteristic

Min

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

Vec

Power Supply Voltage

4.75

5.25

4.75

5.25

4.75

5.0

5.25

4.75

5.25

IIH

Input HIGH Current

150

(.LA

IlL

Input LOW Current

VIH

Input HIGH Voltage1

3.835

4.120

3.835

4.12

3.835

4.12

3.835

4.120

VCC= 5.0V

VIL

Input LOW Voltage l

3.19

3.525

3.19

3.525

3.19

3.525

3.19

3.525

Vec= 5.0V

VBS

Reference Outputl

3.62

3.74

3.62

3.74

3.62

3.74

3.62

3.75

VCC = 5.0V

150

150
0.5

0.5

150
0.5

0.5

(.LA

6.0

Power Supply Curremt
IGND
1. DC levels vary 1:1 with VCC.

Condition

ECUlVECl OUTPUT DC CHARACTERISTICS
-4D'C
Symbol

D'C

85'C

25'C

Characteristic

Min

Max

Min

Max

Min

VEE

Power Supply
EL91
Voltage
LVEL91

-4.2
-3.0

-5.5
-5.5

-4.2
-3.0

-5.5
-5.5

-4.2
-3.0

Typ

Max

Min

Max

Unit

-5.5
-5.5

-4.2
-3.0

-5.5
-5.5

VOH

Output HIGH Voltage

-1085

-880

-1025

-880

-1025

-955

-880

-1025

-880

VOL

Output LOW Volrage

-1830

-1555

-1810

-1620

-1810

-1705

-1620

-1810

-1620

lEE

Power Supply Current

ECLinPS and ECLinPS Lite
DL140-Rev4

4--53

Condition

MOTOROLA

MC100LVEL91 MC100EL91
MC100LVEL91
AC CHARACTERISTICS (VEE = -3.0V to -3.8V; Vee = 3.0V to 3.8V)
-40'C
Symbol

Characteristic

Min

Typ

25'C

O'C
Max

Min

Typ

Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

tpLH
tpHL

Propagation Delay
DtoO

Diff
S.E.

550
550

tSKEW

Skew Output-to-Output1
Part-ta-Part (Diff) 1
Duty Cycle (Diff)2

75
200
25

Vpp

Minimum Input Swing 3

150

VCMR

Common Mode Range 4
Vpp<500mV
Vpp;,500mV

-2.0
-1.8

Output Rise/Fall Times
(20%-80%)

tr
tf
1.
2.
3.
4.

150

mV
V

-0.4
-0.4

-2.1
-1.9

400

-0.4
-0.4

-2.1
-1.9

400

-0.4
-0.4

-2.1
-1.9

400

-0.4
-0.4
400

Skews are valid across specified voltage range, part-ta-part skew is for a given temperature.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
Minimum input swing for which AC parameters guaranteed. The device has a DC gain of -40.
The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and 1V.

MC100EL91
AC CHARACTERISTICS (VEE = -4.20V to -5.5V; Vee = 4.75V to 5.25V)
-40'C
Symbol

Characteristic

Min

Typ

O'C
Max

Min

Typ

25'C
Max

Min

Typ

85'C
Max

Min

Typ

Max

Unit

tpLH
tpHL

Propagation Delay
DtoO

Diff
S.E.

550
550

tSKEW

Skew Output-to-Output1
Part-ta-Part (Diff)1
Duty Cycle (Diff)2

75
200
25

75
200

75
200
25

VPP

Minimum Input Swing3

150

VCMR

Common Mode Range 4
VPP <500mV
Vpp;'500mV

-3.2
-3.0

tr
tf
1.
2.
3.
4.

Output Rise/Fall Times
(20%-80%)

25
150

150

mV
V

-0.4
-0.4
400

-3.3
-3.1

-0.4
-0.4
400

-3.3
-3.1

-0.4
-0.4
400

-3.3
-3.1

-0.4
-0.4
400

MOTOROLA

4-54

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple PECL to LVPECL
Translator

MC100LVEL92

The MC1 00lVEl92 is a triple PECl to lVPECl translator. The device
receives standard PECl signals and translates them to differential
lVPECl output signals.
• 500ps Propagation Delays
• Fully Differential Design
• 2Q-lead SOIC Package
• 5V and 3.3V Supplies Required
• >1500V ESD
A PECl VBB output is provided for interfacing single ended PECl
signals at the inputs. If a single ended PECl input is to be used the PECl
VBB output should be connected to the 5 input and the active signal will
drive the D input. When used the PECl VBB should be bypassed to
ground via a 0.0111f capacitor. The PECl VBB is designed to act as a
switching reference for the MC100lVEl92 under single ended input
conditions, as a result the pin can only source/sink 0.5mA of current.

DWSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 D-04

To accomplish the PECl to lVPECl level translation, the
MC100lVEl92 requires three power rails. The VCC supply is to be
connected to the standard PECl supply, the lVCC supply is to be
connected to the lVPECl supply, and Ground is connected to the system
ground plane. Both the VCC and lVCC should be bypassed to ground
with a O.Q1l1f capacitor.
Under open input conditions, the 5 input will be biased at a VCct2
voltage level and the D input will be pulled to ground. This condition will
force the "Q" output low, ensuring stability.

logic Diagram and Pinout: 20-Lead sOle (Top View)
VCC

LVCC

VCC

PECL

LVCC

PECL

. D2

Vee

PIN NAMES
Pins

Function

On
an
Vee
lVCC
VCC
GNO

PECl Inputs
lVPEClOutputs
PECl Reference Voltage Output
VCC for lVPECl Output
VCC for PECl Inputs
Common Ground Rail

VCC

vee

1196

4-55

REV 1

MOTOROLA

MC100LVEL92

PECl INPUT DC CHARACTERISTICS
DOC

-4DOC
Symbol

25°C

Characteristic

Min

Max

Min

Max

Min

Vee

Power Supply Voltage

4.5

5.5

4.5

5.5

4.5

IIH

Input HIGH Current

IlL

Input LOW Current

VPP

150

85°C

Typ

Max

Min

Max

Unit

5.5

4.5

5.5

150

l1A

150

Condition

0.5
-600

Minimum Peak-to-Peak
Input1

200

VIH

Input HIGH Voltage2

33B5

4120

33B5

4120

33B5

4120

33B5

4120

VIL

Input LOW Voltage2

3190

3515

3190

3525

3190

3525

3190

3525

Vee=5.0V

VBB

Reference Output2

3620

3740

3620

3740

3620

3740

3620

3740

Vee = 5.0V

Power Supply Current
12
Ivee
1. 150mV Input guarantees full logIc sWIng at the output.
2. DC levels vary 1:1 with VCC.

B.O

Vee = 5.0V

lVPECl OUTPUT DC CHARACTERISTICS
DOC

-4DOC
Symbol
VCC

25°C

85°C

Characteristic

Min

Max

Min

Max

Min

Typ

Max

Min

Max

Unit

Power Supply Voltage

3.0

3.8

3.0

3.8

3.0

3.3

3.8

3.0

3.8

Condition

VOH

Output HIGH Voltage 1

2.215

2.42

2.275

2.42

2.275

2.35

2.42

2.275

2.42

VCC= 3.3V

VOL

Output LOW Voltage 1

1.47

1.745

1.49

1.68

1.49

1.60

1.68

1.49

1.68

VCC=3.3V

IGND

Power Supply Current

rnA

1. DC levels wIll vary 1:1 WIth VCC.

MC100lVEl92
AC CHARACTERISTICS (lVee =3.0V to 3.8V; Vee = 4.5V to 5.5V)
DOC

-40°C
Symbol

Characteristic

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

490
440

590
590

690
740

510
460

610
610

710
760

510
460

610
610

710
760

530
480

630
630

730
780

20
20
25

100
200

20
20
25

100
200

20
20
25

100
200

20
20
25

100
200

Propagation Delay
DtoO

tSKEW

Skew Output-to--Output1
Part-ta-Part (Diff)1
Duty Cycle (Diff)2

Vpp

Minimum Input SWing 3

VCMR

Common Mode Range4
Vpp<500mV

1.3

Vee

Vpp;;o500mV

1.5

Vee

320

580

Output Rise/Fall Times
(20%-80%)

150

85°C

Typ

tPLH
tpHL

tr
tf

Diff
S.E.

25°C

Min

150
-0.2
-0.2

150

1.2

vee
-0.2

1.2

Vee

1.4

vee
-0.2

1.4

320

580

320

1.2

Vee

Vee
-0.2

1.4

Vee

580

320

580

-0.2

-0.2
-0.2
ps

..
Skews are valid across specifIed voltage range, part-ta-part skew IS for a gIven temperature .

1.
2. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.Common Mode Range 4
3. Minimum input swing for which AC parameters guaranteed. The device has a DC gain of ~40.
4. The CMR range is referenced to the most positive side olthe differential input signal. Normal operation is obtained ilthe HIGH level falls within
the specified range and the peak-to-peak voltage lies between Vppmin and IV.

MOTOROLA

4-56

ECLinPS and ECLinPS Lite
DL140-Rev4

High Performance Eel Data
ECLinPS and ECLinPS Lite

This section contains a design guide written
exclusively with the ECLinPS and ECLinPS Lite
product families in mind. The design guide deals
with system design aspects of using the family.
This section is not meant to be a replacement for
the MECL System Design Handbook but rather a
supplement to the information contained in it.

CONTENTS
Design Guide:
System Basics ............................ 5-2
Transmission Line Theory .................. 5-8
System Interconnect ...................... 5-18
Interfacing With ECLinPS .................. 5-29
Packaging and Thermal Information ......... 5-32
Case Outlines ......................... 5-37
Quality and Reliability ..................... 5-43

Application Notes:
ECLinPS Circuit Performance at Standard
VIH Levels (AN1404) ................... 5-45

Design Guide &
Application Notes

ECL Clock Distribution
Techniques (AN1405) .................. 5-53
Designing With PECL (AN1406) ............ 5-60
ECLinPS I/O SPICE Kit (AN1503) .......... 5-69
Metastability and the ECLinPS
Family (AN1504) ...................... 5-79
Interfacing Between LVDS and ECL
(AN1568) ............................. 5-87
Distributor and Worldwide Sales Offices ..... 5-93

ECLinPS and ECLinPS Lite
DL140-Rev4

5-1

MOTOROLA

MOTOROLA
SEMICONDUCTOR DESIGN GUIDE

SECTION 1
System Basics
Power Supply Considerations
The following text gives a brief description of the
requirements and recommendations for treatment of power
supplies in an ECLinPS· system design. A more thorough
narration on the general subject of power supplies can be
found in the Motorola System Design Handbook.
VCCSupply
As with all previous ECl families the ECLinPS logic family
is designed to operate with negative power supplies; in other
words with VCC connected to ground. However, ECLinPS
circuits will work fine with positive power supplies as long as
special care has been taken to ensure a stable, quiet VCC
supply. For more detailed information about using positive
supplies and ECl, designers are encouraged to refer to
Application Note AN1406 on page 5-60. The output voltage
levels for a positive supply system can be determined by
simply subtracting the absolute value of the standard
negative output levels from the desired VCC.
To provide as small an AC impedance as pOSSible, and
minimize power bus IR drops, the VCC supply should have a
dedicated power plane. By providing a full ground plane in
the system the designer ensures that the current return path
for the signal traveling down a transmission line does not
encounter any major obstructions. It is imperative that the
noise and voltage drops be as small as possible on the VCC
plane as the internal switching references and output levels
are all derived off of the VCC power rail. Thus, any
perturbations on this rail could adversely affect the noise
margins of a system.
VEE Supply
To take advantage of increased logic density and
temperature compensated outputs, many designers are
building array options with both, temperature compensated
output levels and a - 5.2V VEE supply. To alleviate any
problems with interfacing these arrays to ECLlnPS 100E
devices, Motorola has specified the operation of 100E
devices to include the standard 10H VEE voltage range.
Moreover, because of the superior voltage compensation of
the bias network, this guarantee comes without any changes
in the DC or AC specification limits. With the availability of
both 10H and 100K compatible devices in the ECLinPS
family, there is generally no need to run 1OE devices at 100K
voltage levels. If, however, this is desired, the 10E devices
will function at 100E VEE levels with, at worst, a small
degradation in AC performance for a few devices due to soft
saturation of the current source device.
Although both the 10E and 100E devices can tolerate
variations in the VEE supply without any detrimental effects, it
is recommended that the VEE supply also have a dedicated
powerplane. If this is not a feasible constraint, care should be

taken so that the IR drops of the VEE bus do not create a VEE
voltage outside of the specification range. To provide the
switching currents resu~ing from stray capacitances and
asymmetric loading, the VEE power supply in an ECl system
needs to be bypassed. It is recommended that the VEE
supply be bypassed at each device with an RF quality O.Q1!1F
capacitor to ground. In addition, the supply should also be
bypassed to ground with a 1.0!1F - 10!1F capacitor at the
power inputs to a board. If a separate output termination
plane is used the VEE supply will be of a static nature as the
output switching current will return to ground via the Vn
supply, thus, the bypassing of every device may be on the
conservative side. If the design is going to include a liberal
use of serial or Thevenin equivalent termination schemes, a
properly bypassed VEE plane is essential.
VnSupply
The output edge rates of the ECLinPS family necessitate
an almost exclusive use of controlled impedance
transmission lines for system interconnect (the details of this
claim will be discussed in a latter section). Thus, unless
Thevenin equivalent termination schemes are going to be
used, a Vn supply is a must in ECLinPS designs. The choice
of using only Thevenin equivalent termination schemes to
save a power supply should not be made lightly as the
Thevenin scheme consumes up to ten times more power
than the equivalent parallel termination to a - 2.0V Vn
supply.
As was the case for the VEE supply, a dedicated power
plane, liberally bypassed as described above, should be
used for the Vn supply. In designs which rely heavily on
parallel termination schemes the Vn supply will be
responsible for returning the switching current of the outputs
to ground, therefore, a low AC impedance is a must. For
bypassing, many SIP resistor packs have bypass capacitors
integrated in their design to supply the necessary bypassing
of the supply. The use of SIP resistors will be discussed more
thoroughly in a later chapter.

Handling of Unused Inputs and Outputs
Unused Inputs
All ECLinPS devices have internal50kn - 75kO pulldown
resistors connected to VEE. As a result, an input which is left
open will be pulled to VEE and, thus, set at a logic lOW.
These internal pulldowns provide more than enough noise
margin to keep the input from turning on if noise is coupled to
the input, therefore, there is no need to tie the inputs to VEE
external to the package. In addition, by shorting the inputs to
VEE external to the package, one removes the current limiting
effect of the pulldown resistor and, under extreme VEE

• Any reference to ECLinPS in this section include the ECLinPS Lite and Low Voltage ECLinPS families.

MOTOROLA

5-2

ECLinPS and ECLinPS Lite
DL140-Rev4

System Basics
conditions, the input transistor could be permanently
damaged. If there are concerns about leaving sensitive
inputs, such as clocks, open, they should be tied low via an
unused output or a quiet connection to Vn.
Unless otherwise noted on the data sheets, the outputs to
differential input devices will go to a defined state when the
inputs are left open. This is accomplished via an internal
clamp. Note that this clamp will only take over if the voltage at
the inputs fall below = - 2.5V. Therefore, if equal voltages of
greater than - 2.5V are placed on the inputs, the outputs will
attain an undefined midswing state.
Unlike saturating logic families, the inputs to an ECLinPS,
or any ECl device, cannot be tied directly to VCC to
implement a logic HIGH level. Tying inputs to VCC will
saturate the input transistor and the AC and DC performance
will be seriously impaired. A logic HIGH on an ECLinPS input
should be tied to a level no higher than 600mV below the VCC
rail and, more typically, no higher than the specified VIHmax
limit. A resistor or diode tree can be used to generate a logic
HIGH level or, more commonly, an output of an unused gate
can be used.

a high state the other switches from a high to a low state
simultaneously, thus, the resultant current change through
the Vcca connection is zero. The current simply switches
between the two outputs. However, for the single-ended
output, the current change flows through the Vcca
connection of the output device. This current change through
the Vcca pin of the package causes a voltage spike due to
the inductance of the pin.

Vee

OUTPUT
CURRENT
FLOW

OUT

SINGLE·ENDED OUTPUT

Unused Outputs
The handling of unused outputs is guided by two criteria:
power diSSipation and noise generation. For single ended
output devices it is highly recommended to leave unused
outputs unterminated as there are no benefits in the
alternative scheme. This not only saves the power
associated with the output, but also reduces the noise on the
VCC line by reducing the current being switched through the
inductance of the VCC pins. For the counters and shift
registers of the family, the count and shift frequencies will be
maximized if the parallel outputs are left unterminated. Of
course, for applications where these parallel outputs are
needed this is not a viable alternative.
For the differential outputs, on the other hand, things are a
little less cut and dry. If either of the outputs of a
complimentary output pair is being used, both outputs of the
pair should be terminated. This termination scheme
minimizes the current being switched through the VCC pin
and, thus, minimizes the noise generated on VCC. If,
however, neither of the outputs of a complimentary pair are
being used it makes most sense to leave these unterminated
to save power. Note that the E111 device has special
termination rules; these rules are outlined on the data sheet
for the device.

VEE

Vee

Veeo

OUT
IN

L-----OOUT

DIFFERENTIAL OUTPUTS

Figure 1.1. Eel Output Structures
Traditionally, manufacturers of ECl products have
attempted to combat this problem by providing a separate
VCC pin for the output device (Vcca, VCCA etc.) and the
internal circuitry. By doing this the noise generated on the
Veca of the output devices would see a high impedance
internal to the chip and not couple onto the the VCC line which
controls the output and internal bias levels. Unfortunately, in
practice the noise generated on the Vcca would couple into
the chip VCC through the collector base capacitance of the
output device, thus, a large portion of the noise seen on the
Vcca line would also be seen on the VCC line.
For the ECLinPS family and its associated edge speeds, it
was decided that multiple Vcca pins would be necessary to
minimize the inductance and the associated noise
generation. A design rule was established so that there
would be no more than three single-ended outputs per Vcca
pin. Initially, the VCC and Vcca pins were kept isolated from

Minimizing Simultaneous Switching Noise
A common occurrence among ECl families is the
generation of crosstalk and other noise phenomena during
simultaneous switching situations. Although the noise
generated in ECl systems is minor compared to other
technologies, there are methods to even further minimize the
problem.
Figure 1.1 below illustrates the two output scenarios of an
ECl device: differential outputs and single-ended outputs.
During switching, the current in the output device will change
by =17mA when loaded in the normal 50n to - 2.0V load.
With differential outputs, as one output switches from a low to

ECLinPS and ECLinPS Lite
DL140-Rev4

Veeo

5-3

MOTOROLA

System Basics
one another. However, it was discovered that in certain
applications the parasitics of the package and the output
device would combine to produce an instability which
resulted in the outputs going into an oscillatory state. To
alleviate this oscillation problem, it was necessary to make
the VCC and VCCO metal common internal to the package.
Subsequent evaluation showed that because of the liberal
use of VCCO pins, the noise generated is equal to or less than
that of previous ECL families.
To further reduce the noise generated there are some
things that can be done at the system level. As mentioned
above, there should be adequate bypassing of the VCC line
and the guidelines for the handling of unused outputs should
be followed. In addition, for wide Single-ended output
devices, an increase in the characteristic impedance of the
transmission line interconnect will result in a smaller time rate
of change of current; thus, reducing the voltage glitch caused
by the inductance of the package. This noise improvement
should, of course, be weighed against the potential slowing of
the higher impedance trace to optimize the performance of
the entire system. In addition, the connection between the
device VCC pins and the ground plane should be as small as
possible to minimize the inductance of the VCC line. Note that
a device mounted in a socket will exhibit a larger amount of
VCC noise due to the added inductance of the socket pins.

Effects of Capacitive Loads
The issue of AC parametric shifts with load capacitance is
a common concern especially with designers coming from
the TTL and CMOS worlds. For ECLinPS type edge speeds,
wire interconnect starts acting like transmission lines for
lengths greater than 1/2". Therefore, for the majority of cases
in ECLinPS designs, the load on an output is seen by the
transmission line and not the output of the driving device. The
effects of load capacitance on transmission lines will be
discussed in detail in the next section.
If the load is close to the driving output «1/2'1, the
resulting degradation will be 15-25ps/pF for both
propagation delays and edge rates. In general, a capacitive
load on an emitter follower has a greater impact on the falling
edge than the rising edge. Therefore, the upper end of the
range given above represents the effect on fall times and the
aSSOCiated propagation delays, while the lower end
represents the effect on the riSing output parameters.
For ECLinPS devices, the capacitive load produced by an
input ranges from 1.2pF to 2.0pF. The majority (~95%) of this
capacitance is contributed by the package with very little
added by the internal input circuitry. For this reason the range
is generally a result of the difference between a corner and a
center pin for the PLCC package. A good typical capacitance
value for a center pin is 1.4pf and for a corner pin 1.7pf. The
capacitances for the other pins can be deduced through a
linear interpolation.

Wired-OR Connections
The use of wired-OR connections in ECL designs is a
popular way to reduce total part count and optimize the
speed performance of a system. The limitation of OR-tying

MOTOROLA

ECL outputs has always been a combination of increased
delay per OR-tie and the negative going disturbance seen at
the output when one output switches from a high to a low
while the rest of the outputs remain high. For high speed
devices the latter problem is the primary limitation due to the
increased sensitivity to this phenomena with decreasing
output transition times. The following paragraph will attempt
to describe the wire-OR glitch phenomena from a physical
perspective.
Figure 1.2 illustrates a typical wire-OR situation. For
simplicity, the discussion will deal with only two outputs;
however, the argument could easily be expanded to include
any number of outputs. If both the A and the B outputs start in
the high state they will both supply equal amounts of current
to the load. If the B output then transitions from a high to a low
the line at the emitter of B will see a sudden decrease in the
line voltage. This negative going transition on the line will
continue downward at the natural fall time of the output until
the A output responds to the voltage change and supplies the
needed current to the load. This lag in the time it takes for A to
correct the load current and return the line to a quiescent high
level is comprised of three elements: the natural response
time of the A output, the delay associated with the trace
length between the two outputs and the time it takes for a
signal to propagate through the package. The trace delay
can be effectively forced to zero by OR-tying adjacent pins.
The resulting situation can then be considered "best case". In
this best case situation, if the delay through the package is
not a significant portion of the transition time of the output, the
resulting negative going glitch will be relatively small
(~100mV). A disturbance of this size will not propagate
through a system. As the trace length between OR-tied
outputs increases, the magnitude of the negative going
disturbance will increase. Older ECL families specified the
maximum delay allowed between OR-tied outputs to prevent
the creation of a glitch which would propagate through a
system.
As this glitch phenomena is a physical limitation, due to
decreased edge rates, ECLinPS devices are susceptible to
the problem to an even greater degree than previous slower
ECL families. The package delay of even the 28-lead PLCC

Figure 1.2. Typical Wire-OR Configuration
is a significant portion of the transition times for an ECLinPS
device. Therefore, even in the best case situation described
above, one can expect an ~200mV glitch on the OR-tied line.
A glitch of this magnitude will not propagate through the
system but it is significantly worse than the best case
situation of earlier ECL families. In fact, as long as the
distance between OR-tied outputs is kept to less than 1/2"
the resulting line disturbance will not be sufficient to
propagate through most systems.

ECLinPS and ECLinPS Lite

DL140-Rev4

System Basics
With this in mind, the following recommendations are
offered for OR-tying in ECLinPS designs. First, OR-tying of
clock lines should be avoided as even in the best case
situation the disturbance on the line is significant and could
cause false clocking in some situations. In addition, wire
ORed outputs should be from the same package and
preferably should be adjacent pins. Non-adjacent outputs
should be within 1/2" of each other with the load resistor
connection situated near the midpoint of the trace (Figure
1.2). By following these guidelines, the practice of
wire-ORing ECl outputs can be expanded to the ECLinPS
family without encountering problems in the system.

DATA

TpDnom

Tpomax
Tponom
Tpomin

A detailed discussion of wire-OR connections in the
ECLinPS world of performance is beyond the scope of this
text. For this reason a separate application note has been
written which deals with this situation in a much more
thorough manner. Anyone planning to use wire-OR
connections in their ECLinPS design is encouraged to
contact a Motorola representative to obtain this application
note.

L
I

OUTPUT

Tponom

ffsO%

Figure 1.3. Delay vs Switching Reference Offset
In addition to these generic differential devices there are
several devices which were designed exclusively for clock
distribution systems. With past ECl families designers were
forced to build clock distribution trees with devices which
were compromises at best. The ECLinPS family, however,
was built around the E111 clock distribution chip; a fully
differential 1:9 fanout device which boasts within part skews
as well as part- to-part skews unequaled in today's market.
Additionally, to further deskew clock lines the E195
programmable delay chip is available. Although static delay
lines can remove built-in path length difference skew, they
cannot compensate for variations in the delays of the devices
in the clock path. The E195 allows the user to delay, a signal
over a 2ns range in ~20ps steps. Through the use of this
device, the designer can match skews between clocks to
20ps.
Although these two devices satisfy the needs for many
ECl designers, they do overlook the needs of a special
subset; the designer who mixes ECl and TIL technologies.
When translating between ECl and TIL, much of the skew
performance gained through the E111 is lost when passed
through the translator and distributed in TIL. To solve this
problem, a new set of translators has been introduced in the
MECl 10H family. The H641 and H643 receive a differential
ECl input and fan out nine TIL outputs with a guaranteed
unparalleled skew between the TIL outputs. The H640 and
H642 take differential ECl inputs and generate low skew TIL
outputs which are ideal for driving clocks in 68030 and 68040
microprocessor systems. By using the ECl aspects of the
E111 to distribute clock lines across the backplane to TIL
cards and receiving and translating these signals with the
H640, H641, H642 or H643, a TIL clock distribution tree can
be deSigned with a performance level unheard of with past
logic families.

Clock Distribution
Clock skew is a major contributor to the upper limit of
operation of a high speed system; therefore, any reduction in
this parameter will enhance the overall performance of a
system. Through the ECLinPS family and new offerings in the
10H family, Motorola is providing devices uniquely designed
to meet the demands of low skew clock distribution.
By far the largest contributor to system skew is the
variation between different process lots of a given device.
This variation is what defines the total delay window specified
in the data sheets. This window can be minimized if the
devices are fully differential due to the output level defined
thresholds which ensure a "centered" input swing. The
propagation delay windows of single-ended ECl and other
logic technologies, are intimately tied to variations in the input
thresholds. As illustrated in Figure 1.3 although the delays,
when measured from the threshold of the input to the 50%
point of the output, are equal; when measured from the
specified 50% point of the input to the 50% point of the
output, the delays will vary with any shift in the switching
reference. Obviously, the magnitude of the delay difference is
also proportional to the edge rate of the input. In addition to
increasing the size of the delay windows, this reference shift
will cause the duty cycle of the output of a device to be
different than that of the input. Unfortunately, these
thresholds are perhaps the most difficult aspects of a logic
device to control. As a result, for the ultimate in low skew
performance differential ECl devices are a must. A quick
perusal of the ECLinPS databook will reveal a relatively large
number of totally differential devices which will lend
themselves nicely to very low skew applications such as
clock distribution.

ECLinPS and ECLinPS Lite
DL140 - Rev 4

5-5

MOTOROLA

System Basics
Through the development of a library of differential
devices, specialized low-skew distribution chips and
high-resolution programmable delay chips, Motorola has
serviced the need for low-skew clock distribution designs.
These offerings open the door for even higher performance
next generation machines. For more information on clock
distribution, designers are encouraged to read Application
Note AN1405 on page 5-53.

Generally, this task is accomplished with the use of a single
or series of D flip-flops as pictured in Figure 1.4. Because the
data signal and the clock signal are asynchronous, the
system designer cannot guarantee that the setup and hold
specifications for the device will be met. This in and of itself
would not cause a problem if it was not for the metastable
behavior of a D flip-flop. The metastable behavior of a flip-flop
is described by the outputs of a device attaining a nondefined
logic level or, perhaps, going into an oscillatory state when
the data and the clock inputs to the flip-flop switch
simultaneously. It has been shown that this metastable
behavior occurs across technology boundaries as well as
across performance levels within a technology.

Metastability Behavior
The metastability behavior and measurement of a flip-flop
is a complicated subject and necessitates much more time
than is available in this forum for a thorough explanation. As a
result, the following description is of an overview nature.
Anyone interested in a more thorough narration on the
subject is encouraged to read Application Note AN1504 on
page 5-79, which contains a more detailed discussion on the
subject.
In many designs, occasions arise where an asynchronous
signal needs to be synchronized to the system clock.

For EeL the characteristic of a flip-flop in a metastable
state is a device whose outputs are in a non-defined state
near the midpoint of a normal output swing. The output will
return randomly to one of the two defined states some time
later (Figure 1.5). The two parameters of importance when
discussing metastability are the metastablity window; the
window in time for which a transition on both the data and the

SYSTEM 1
SYSTEM 1
CLOCK

JU1...

SYSTEM 2
CLOCK

JU1...

SYSTEM 1
OUTPUT

...JLJL

DATA

SYSTEM 2 INPUT

D·FlIP-FLOP

,--

SYSTEM 2

CLOCK

SYSTEM 1
SYSTEM 1
CLOCK

JU1...

SYSTEM 2
CLOCK

Jl.I1....

SYSTEM 1
OUTPUT

.r-L..r""L
DATA

0 - DATA

CLOCK

at---

D·FLlp·FLOP

D·FlIp·FLOP

~CLOCK

SYSTEM 2 INPUT
SYSTEM 2

TDDELAY

Figure 1.4. Clock Synchronization Schemes

MOTOROLA

5-6

ECLinPS and ECLinPS Lite
DL140-Rev4

System Basics

The challenge then becomes, how to characterize
metastability behavior given the above circumstances. The
standard method in the industry is to use Stoll's 1 equation,
combined with the standard MTBF equation, to develop the
following relationship:
MTBF 1 / (2*fC*fD*Tp*10 - (tI't))

where:

Clock Frequency
Data Frequency
FF Propagation Delay
Time Delay Between FF

Clocks
't:
FF Resolution Time
Constant
Note that the clock frequency, data frequency and time
delay between flip-flops are user-defined parameters, thus it
is up to Motorola to provide only the propagation delays and
the resolution time constants for the ECLinPS flip-flops.
The propagation delays are, obviously, already defined
leaving only the resolution time constant yet to be
determined. An evaluation fixture was fabricated and several
ECLinPS flip-flops were evaluated for resolution time
constants.The results of the evaluation showed that the time
constant was somewhat dependent on the part type as all the
flip-flops in the ECLinPS family do not use the same general
design. The time constants range from 125-225 ps
depending on the part type.
As an example, for a system with a 100MHz clock and
75MHz data rate, the required delay between clock edges of
a cascaded flip-flop chain for the E151 register, assuming a't
of 200ps, would be:
MTBF = 1 / (2*1 OOMHz*75MHz*800ps*1 0 - tl200ps)

Figure 1.5. Metastable Behavior of an EeL Flip Flop
clock will cause a metastable output, and the settling time;
the time it takes for a metastable output to return to a defined
state. For the single flip-flop design of Figure 1.3, the data
being fed into system 2 will be in an undefined state and,
thus, unusable if the synchronizing flip-flop enters a
metastable state. Because of this, a more popular design
incorporates multiple flip-flop chains with cascading data
inputs and clock inputs which are delayed with respect to
each other. This redundancy of flip- flops helps to reduce the
probability that the data entering system 2 will be at an
undefined level which could wreak havoc on the logic of that
system. This reduction in probability relies on the fact that
even if the preceding flip-flop goes metastable, it will settle to
a defined state prior to the clocking of the following flip-flop.
Obviously, once the first flip-flop goes metastable there is an
even chance that it will settle in the wrong state and, thus,
information will be lost. However, there are error detection
and correction methods to circumvent this problem. The
larger the flip-flop chain the lower the probability of
metastable data being fed into system 2.

solving for an MTBF of 10 years yields:
t = 3.1 ns, therefore:

Unfortunately for ECLinPS, levels of performance, both
the window width and the settling time, are difficult or
impossible to measure directly. The metastable window for
an ECLinPS flip-flop is assuredly less than S.Ops and most
likely less than 1.0ps based on SPICE level simulation
results. In either case, with today's measuring equipment, it
would be impossible to measure this window width directly.
Although it is feasible to measure the settling time for a given
occurrence, this parameter is not fixed but, rather, is of a
variable length which makes it impossible to provide an
absolute guarantee.

ECLinPS and ECLinPS Lite
DL140- Rev 4

fC:
fD:
T p:
t:

=Ll.t + Tp =3.9ns

So, for an MTBF of 10 years for the above situation the
second flip-flop should be clocked 3.9ns after the first. Similar
results can be found by applying the equation to different
data and clock rates as well as different acceptable MTBF
rates.
1 Stoll, P. "How to Avoid Synchronization Problems,"
VLSI DeSign, November/December 1982. pp. 56-59.

5-7

MOTOROLA

MOTOROLA
SEMICONDUCTOR DESIGN GUIDE

SECTION 2
Transmission Line Theory
Introduction
The EClinPS family has pushed the world of ECl into the
realm of picoseconds. When output transitions move into this
picosecond region it becomes necessary to analyze system
interconnects to determine if transmission line phenomena
will occur. A handy rule of thumb to determine if an
interconnect trace should be considered a transmission line
is if the interconnect delay is greater than 1/8th of the signal
transition time, it should be considered a transmission line
and afforded all of the attention required by a transmission
line. If this rule is applied to the EClinPS product line a
typical PCB trace will attain transmission line behaviors for
any length> 1/4". Thus, a brief overview of transmission line
theory is presented, including a discussion of distributed and
lumped capacitance effects on transmission lines. For a
more thorough discussion of transmission lines the reader is
referred to Motorola's MECl Systems Oesign Handbook.

(Equation 1)
where:
lO = Inductance per unit length (H)
Co = Capacitance per unit length (F)
Propagation Delay
Propagation delay (TPO) is also expressed as a function of
both the inductance and capacitance per unit length of a
transmission line. The propagation delay of the line is defined
by the following equation:
(Equation 2)
If lO is expressed as microHenry's per unit length and
capacitance as picoFarad's per unit length, the units for delay
are nanoseconds per unit length. The propagation velocity is
defined as the reciprocal of the propagation delay:
v=1ITPO=1/"(lO'CO)

Background
Exact transmission line analysis can be both tedious and
time consuming; therefore, assumptions for simplifying these
types of calculations must be made. A reasonable
assumption is that interconnect losses caused by factors
such as bandwidth limitations, attenuation, and distortion are
negligible for a typical PCB trace. The basis for this
assumption is that losses due to the interconnect conductor
are only a fraction of the total losses in the entire interface
scheme. In addition, the conductivity of insulating material is
very small; as a result, the dielectric losses are minimal. A
second, and more fundamental, assumption is that
transmission line behavior can be described by two
parameters: line characteristic impedance (ZO), and
propagation delay (TpO)

Characteristic Impedance
An interconnect which consists of two conductors and a
dielectric, characterized by distributed series resistances and
inductances along with distributed parallel capacitances
between them, is defined as a transmission line. These
transmission lines exhibit a characteristic impedance over
any length for which the distributed parameters are constant.
Since the contribution of the distributed series resistance to
the overall impedance is minimal, this term can be neglected
when expressing the characteristic impedance of a line. The
characteristic impedance is a dynamic quantity defined as
the ratio of the transient voltage to the transient current
passing through a point on the line. Thus, Zo can be
expressed in terms of the distributed inductance and
capacitance of the line as shown by Equation 1.

MOTOROLA

lO and Co can be determined using the easily measured
parameters of line delay (TO), line length (L), and the line
characteristic impedance (ZO) in conjunction with Equations
1 and 2. The propagation delay is defined as the ratio of line
delay to line length:
TpO=TO/l
Combining equations 1 and 2 yields:
CO=TpotZO
lO=TpO'ZO

(Equation 3)
(Equation 4)

Termination and Reflection Theory
Figure 2.1 shows an EClinPS gate driving a loss less
transmission line of characteristic impedance ZO, and
terminated with resistance AT. Modifying the circuit of Figure
2.1 such that the driving gate is represented by its equivalent
circuit gives the configuration shown in Figure 2.2.
For a positive step function VIN, a voltage step VS, travels
down the transmission line. The initial current in the
transmission line is determined by the ratio VstZO. When the
traveling wave arrives at the termination resistor RT, Ohm's

NODE"S:'

Figure 2.1. Typical Transmission Line
Driving Scenario

5-8

ECLinPS and ECLinPS Lite
DL140-Rev4

Transmission Line Theory
Law must be maintained. If the line characteristic impedance
and the termination resistance match (i.e. ZO=RT),the
traveling wave does not encounter a discontinuity at the
line-load interface; thus, the total voltage across the
termination resistance is the incident voltage VS. However, if
mismatches between the line characteristic impedance and
the termination resistance occur, a reflected wave must be
set up to ensure Ohm's Law is obeyed at the line-load
interface. In addition, the reflected wave may also encounter
a discontinuity at the interface between the transmission line
and the source resistance, thereby sending are-reflected
wave back towards the load. When neither the source nor the
load impedance match the line characteristic impedance
multiple reflections occur with the reflected signals being
attenuated with each passage over the transmission line.
The output response of this configuration appears as a
damped oscillation, asymptotically approaching the steady
state value, a phenomenon often referred to as ringing.

IS =Vs/ZO
IR=-VRIZO
Using substitution:
(Equation 5)
Since only one voltage can exist at node "a" at any instant in
time:
(Equation 6)
Combining Equations 5 and 6, and solving for VR yields:

VS,IS

(Equation 7)
Therefore:

The term PL referred to as the load reflection coefficient,
represents the fraction of the voltage wave arriving at the
lineload interface that is reflected back toward the source.
Figure 2.2. Thevenin Equivalent Circuit of Figure 2.1

Similarly, a source reflection coefficient can be derived as:
Ps = (RS-ZO)/(Rs+ZO)

In performing transmission line analysis, designers may
encounter one of three impedance situations:

(Equation 8)

From equations 7 and 8 it is apparent that multiple
reflections will occur when neither the source nor the load
impedances match the characteristic impedance of the line.
A general equation for the total line voltage as a function of
time and distance is expressed by Equation 9.

1. RS < ZO; RT '" Zo
2. RS"'ZO; RT=ZO
3. RS=ZO; RT"'ZO

V(x,t)

where:
RS

= Source Resistance

= Termination Resistance

VA(t)'[U(t-TpD'X) + PL'U(t-TpD(2L-x) +
PL'PS'U(t-TpD(2L+x» +
(PL"2)'(PS'U(t-TpD(4L-x» +
(PL"2)'PS"2)'U(t-TPD(4L+x» + ... J +
VDC
(Equation 9)

where:

Case 1: RS < Ze; RT '" Ze
The initial current in the transmission line is determined by
the ratio VSIZO. However, the final steady state current is
determined by the ratio VS/Ry, assuming ohmic losses in the
transmission line are negligible. For case 1, an impedance
discontinuity exists at the line-load interface which causes a
reflected voltage and current to be generated at the instant
the initial signal arrives at this interface. To determine the
fraction of the traveling wave that will be reflected from the
line-load interface, Kirchoff's current law is applied to node
"a" in Figure 2.2. This results in the following:

VA
TPD
L
x
VDC

= Voltage Entering the Transmission Line
= Propagation Delay of the Line
= Total Line Length
= Distance to an Arbitrary Point on the Line
= Initial Quiescent Voltage of the Line

Finally, the output voltage, VT can be derived from the
reflection coefficient by combining Equations 6 and 7:
VT=(1~ (RT-Zol/(RT+ZO))* Vs

VT=(2'RT/(RT+ZO»'VS
The two possible configurations for the Case 1 conditions
are RT > Zo and RT < Zo. The following paragraphs will
describe these two conditions in detail.

IT = IS + IR where:
IT = VT/RT

ECLinPS and ECLinPS Lite
DL140-Rev4

5-9

MOTOROLA

Transmission Line Theory
Configuration 1:

Ps = (RS - ZO)/(RS+ZO)

Rr > Zo

For the case in which RT> ZO, PL is positive, and the initial
current at node "a" is greater than the final quiescent current:

50)/(6+50)

=- 0.79

From Equation 9, the output voltage VT after one line delay is:
VT(L,TPO) = VA(t)·[1 + PLl + VOC = - 0.71V

IINITIAL > IFINAL

Likewise, after a time equal to three times the line delay, the
output voltage VT is

Hence:
VS/ZO»(VglRT)

VT(L,3TpO) =VA(t)"[PL·PS + PL ··2·PSI + VT(L,TpO) =
-0.83V

Thus, a reflected current, IR, must flow toward the source in
order to attain the final steady state current as shown in
Figure 2.3.
An example of a line mismatched at both ends, with the
termination resistance greater than the load resistance is
shown

I ~IR
T-

(!l

~
is

=(6 -

VSI-_-------...I....-

Additional iterations of Equation 9 can be performed to show
that the ringing asymptotically approaches the final line
voltage of - 0.82V. Ringing is a characteristic response for
transmission lines mismatched at both ends with RT > RO. A
SPICE representation of configuration 1 is illustrated in
Figure 2.5.

1 - ............

TL Zo

in Figure 2.4. The initial steady state output voltage is given
by:
VTI

=(65171 )*(-1.75) =-1.60V

,·r)
RS=RO=6Q

ZQ=50Q

~.:

Configuration 2:

IINITIAL < IFINAL
Hence:

VTF = (65171)*(- 0.9) = - 0.82V
The input voltage is a ramp from -1. 75V to - 0.9V. The initial
voltage traveling down the line is:
Vs = (50/56)"0.85 = 0.76V
From Equations 7 and 8:

MOTOROLA

For the case in which RT Zo

PL =(RT- ZO)/(RT+ZO)

H=1000psJdiv
V=200mVldiv

Figure 2.5. SPICE Results for Circuit of Figure 2.4

The final steady state output voltage is given by:

TIME

=(65 -

50)/(65+50)

=0.13

(VsIZO) < (VS/RT)
The reflected current, IR, flows in the same direction as the
initial source current in order to attain the final steady state
current. The unique characteristic of configuration 2 is the
negative reflection coefficient at both the source and load
ends of the transmission line (Figure 2.6). Thus, signals
approaching either end of the line are reflected with opposite
polarity. In addition, the line voltage is a function of the pulse
duration yielding steps of decreasing magnitude for input
pulse durations greater than the line delay, and a series of
attenuated pulses for input pulse durations less than the line
delay.

5-10

ECLinPS and ECLinPS Lite

DL140- Rev 4

Transmission Line Theory

UJ
C!l

1§
~

volts. Stair-steps are characteristic responses for
transmission lines mismatched at both ends with RT < ZO,
and a pulse width greater than the line delay. Figure 2.8
shows the results of a SPICE simulation for the case
described by configuration 2.

::J

DISTANCE

Figure 2.6. Reflected Voltage Wave for RT < Zo

An example of a line mismatched at both ends, with the
termination resistance less than the line resistance, and the
input pulse width greater than the line delay is shown in
Figure 2.7.

The initial steady state output voltage is defined as:

TIME

VTI = (35/41)*(-1.75) = -1.49V

H=1000psldiv
V=200mV/div

Figure 2.8. SPICE Results for Circuit of Figure 2.7
with Input Pulse Width> Line Delay

The final steady state output voltage is given by

RS=RO=6Q

Figure 2.9 shows the line response for the same circuit as
above, but for the case in which the input pulse width is less
than the line delay. As in the previous example, the initial
steady state voltage across the transmission line is -1.49
volts, and the reflection coefficients are - 0.18 and - 0.79 for
the load and source respectively. However, the intermediate
voltage across the transmission line is a series of
positive· going pulses of decreasing amplitude for each round

ZO=50Q

~)
VINCQ

1/\

Figure 2.7. Transmission Line Model for RT < Zo
VTF = (35/41)'(- 0.9) = - O.77V
For an input pulse from -1.75V to - 0.9V the initial voltage
traveling down the line is:

Vs = (50/56)*0.85 = 0.76V

-.J

From Equations 7 and 8,

'-J\

PL = (35 - 50)/(35+50) = - 0.18
TIME

Ps = (6 - 50)/(6+50) = - 0.79

H=1000psldiv
V=200mVldiv

Figure 2.9. SPICE Results for Circuit of Figure 2.7
with Input Pulse < Line Delay

From Equation 9, the output voltage VT after one line delay is:
VT(L,TpD) = VA(t)"[1 + PLl + VDC = - 0.87V

trip of the reflected voltage, until the final steady state voltage
of 1.49 volts is reached.

Likewise, after a time equal to three times the line delay, the
output voltage VT is:

Shorted Line
The shorted line is a special case of configuration 2 in
which the load reflection coefficient is -1.0, and the
reflections tend toward the steady state condition of zero line
voltage and a current defined by the source voltage and the
source resistance.

VT(L,3TpD)=VA(t)'[PL'PL+PL"2'PS1+VT(L,TPD)=
-0.78V
Additional iterations of Equation 9 can be performed to show
that the output response asymptotically approaches - 0.77

ECLinPS and ECLinPS Lite

DL140-Rev4

5-11

MOTOROLA

Transmission Line Theory
AS= 16.70

Zo=50Q

~r'

the load and source respectively. However, the intermediate
voltage across the transmission line is a series of negative
pulses with the amplitude of each pulse decreasing for each
round trip of the reflected voltage until the final steady state
voltage of zero volts is attained. Again, for this example, the
amplitude of the output response decreases by 50% for each
successive reflection

Figure 2.10. Transmission Line Model
for Shorted Line

{\
~
'"g
:::; '/
w

An example of a shorted line is shown in Figure 2.10. The
transmission line response for the case in which the input
pulse width is greater than the line delay is shown in Figure
2.11. The initial and final steady state voltages across the
transmission line are zero. The source is a step function with
a 0.85 volt amplitude. The initial voltage traveling down the
line is:

Z
Z

iii

Vs = (50/66.7)'0.85 = 0.64V

TIME

From Equations 7 and 8,
PL = (0-50)/(0+50)= -1

Upon reaching the shorted end of the line, the initial voltage
waveform is inverted and reflected toward the source. At the
source end, the voltage is partially reflected back toward the
shorted end in accordance with the source reflection
coefficient. Thus, the voltage at the shorted end of the
transmission line is always zero while at the source end, the
voltage is reduced for each round trip of the reflected voltage.
The voltage at the source end tends toward the final steady
state condition of zero volts across the transmission line. The
values of the source and line characteristic impedances in
this example are such that the amplitude decreases by 50%
with each successive round trip across the transmission line.

Case 2: RS :;:; ZO; RT = Zo
As in Case 1, the initial current in the transmission line is
determined by the ratio of VsfZo. Similarly, since RT = Zo the
final steady state current is also determined by the ratio
VslZo. Because a discontinuity does not exist at the line-load
interface, all the energy in the traveling step is absorbed by
the termination resistance, in accordance with Ohm's Law.
Therefore, no reflections occur and the output response is
merely a delayed version of the input waveform.

,·r'
RS=RO=6Q

\
\

\
"-H=1000psldiv
V=200mVldiv

Figure 2.11. SPICE Results for Shorted Line
with the Input Pulse Width> Line Delay
Figure 2.12 shows the line response for the same circuit
as above, but for the case in which the input pulse width is
less than the line delay. As in the previous example, the initial
and final steady state voltages across the transmission line
are zero, and the reflection coefficients are -1.0 and - 0.5 for

MOTOROLA

Zo=50Q

Figure 2.13. Transmission Line Model
for Matched Termination

"'\
TIME

H=100Opsidiv
V=200mVldiv

due to the choice of source and transmission line
characteristic impedances.

,..- ---..

(

'-V

Figure 2.12. SPICE Results for Shorted Line with
the Input Pulse Width < Line Delay

Ps = (16.7-50)/(16.7+50) = - 0.5

\ II

An example of a line mismatched at the source but
matched at the load is shown in Figure 2.13. For an input
pulse of -1.75V to - 0.9V is given by:
VTI = (50/56)'(-1.75) = -1.56V
The final steady state output voltage is given by
VTF = (50/56)*(- 0.9) = - 0.80V
The source is a step function with an 0.85 volt amplitude. The
initial voltage traveling down the line is:
Vs = (50/56)*0.85 = O.76V

5-12

ECLinPS and ECLinPS Lite
DL140-Rev4

Transmission Line Theory
From Equations 7 and 8,

An example of a line mismatched at the load but matched
at the source is shown in Figure 2.15. For an input pulse of
-1.75V to - 0.9V the initial steady state output voltage is
given by:

PL = (50-50)/(65+50) = 0
Ps = (6-50)/(6+50) = - 0.79

VTI = (65/115)"(-1.75) = - 0.99V

From Equation 9, the output voltage VT after one line delay is:

The final steady state output voltage is given by
VTF = (65/115)"(- 0.9) = - 0.51V

VT(L,TpO) = VA(tnl + PLl + Voc = - 0.80V
Likewise, after a time equal to three times the line delay, the
output voltage VT is:

The source is a step function with a 0.85 volt amplitude. The
initial voltage traveling down the line is:
Vs = (50/100)"0.85 = 0.43V

VT(L,3TpO)=
VA(tnPL"PS + PL""2"PSl + VT(L,TpO) =- 0.80V

From Equations 7 and 8,
PL = (65-50)/(65+50) = 0.13

Thus, the output response attains its final steady state value
(Figure 2.14) after only one line delay when the termination

Ps = (50-50)/(50+50) = 0
From Equation 9, the output voltage VT after one line delay is:

VT(L,TPO) = VA(t)"[1 + PLl + VOC = - 0.51V

Likewise, after a time equal to three times the line delay, the
output voltage VT is:
VT( L,3TpO) = VA(t)"[PL"PS+PL"2"PSl + VT(L,TpO) =
-0.51V

i
TIME

H=400psldiv
V=200mVldiv

Thus, the output response attains its final steady state value
after one line delay when the source resistance matches the
line characteristic impedance. Again, ringing or a stair-step
output does not occur since the load reflection coefficient is
zero (Figure 2.16).

Figure 2.14. SPICE Results for Matched Termination
resistance matches the line characteristic impedance.
Ringing or stair-step output responses do not occur since the
load reflection coefficient is zero.

Case 3: RS = ZO; RT = Zo
When the termination resistance does not match the line
characteristic impedance reflections arising from the load will
occur. Fortunately, in case 3, the source resistance and the
line characteristic impedance are equal, thus, the reflection
coefficient is zero and the energy in these reflections is
completely absorbed at the source; thus, no further
reflections occur.

RS =SOQ

TIME

Zo=SOQ

VINes!
Figure 2.15. Transmission Line Model for Vs = Zo

ECLinPS and ECLinPS Lite
DL140-Rev4

H=400psldiv
V=100mVldiv

Figure 2.16. SPICE Results for Circuit of Figure 2.15

Series Te!7Tlination
Series termination represents a special subcategory of
Case 3 in which the load reflection coefficient is +1 and the
source resistance is made equal to the line characteristic
impedance by inserting a resistor, RST, between and in series
with, the transmission line and the source resistance RO. The

5-13

MOTOROLA

Transmission Line Theory
reflections tend toward the steady state conditions of zero
current in the transmission line, and an output voltage equal
to the input voltage. This type of termination is illustrated by
the circuit configuration of Figure 2.17. The initial voltage
down the line will be only half the amplitude of the input signal
due to the voltage division of the equal source and line
impedances.

Since the load reflection coefficient is unity, the voltage at
the output attains the full ECL swing, whereas the voltage at
the beginning of the transmission line does not attain this
level until the reflected voltage arrives back at the source
termination (Figures 2.17 and 2.18). No other reflections
occur because the source impedance and line characteristic
impedance match.

(Equation 10)
The load reflection coefficient tends to unity, thus, a
voltage wave arriving at the load will double in amplitude, and
a reflected wave with the same amplitude as the incident
wave

Capacitive Effects on Propagation Delay
Lumped Capacitive Loads
The effect of load capacitance on propagation delay must

20= 50il

7r If

/ /

Figure 2.17. Series Terminated Transmission Line

L
will be reflected toward the source. Since the source
resistance matches the line characteristic impedance all the
energy in the reflected wave is absorbed, and no further
reflections occur. This ·source absorption" feature reduces
the effects of ringing, making series terminations particularly
useful for transmitting signals through a backplane or other
interconnects where discontinuities exist.
As stated previously, the signal in the line is only at half
amplitude and the reflection restores the signal to the full
amplitude. It is important to ensure that all loads are located
near the end of the transmission line so that a two step input
signal is not seen by any of the loads.
For the series terminated circuit of Figure 2.17 with RO +
RST = Zo and an input pulse rising from -1. 75V to - 0.9V, the
initial line voltage, VTI is -1.325V and the final line voltage,
Vn; is - 0.9V. The source is a step function with a 0.85 volt
amplitude. The initial voltage traveling down the line is:
Vs = (50/100)"0.85 = 0.43V

VSJ

H=400ps/div
V=200mVldiv
Figure 2.18. SPICE Results for Series
Terminated Line
TIME

be considered when using high performance integrated
circuits such as the ECLinPS family. Although capacitive
loading affects both series and parallel termination schemes,
it is more pronounced for the series terminated case. Figure
2.19a illustrates a series terminated line with a capacitive
load CL. Under the no load condition, CL=0, the delay
between the 50% point of the input waveform to the 50%
point of the output waveform is defined as the line delay TD. A
capacitive load

From Equations 7 and 8,

,·r'

PL = (00 - 50)/(00+50) = 1

RS = Zo

Ps = (50 - 50)/(50+50) = 0
From Equation 9, the output voltage VT after one line
delay is:

VT(L,3TpD) = VA(t)"PLPS+ PL'2'PSl + VT(L,TPD) =
-0.9V

MOTOROLA

Figure 2.19a. Lumped Load
Transmission Line Model

VT(L,TpD) = VA(t)'[1 + PLl + VDC = - 0.9V
Likewise, after a time equal to three times the line
delay, the output voltage VT is:

20 = 50il

placed at the end of the line increases the rise time of the
output Signal, thereby increasing TD by an amount ATD
(Figure 2.19b). Figure 2.20 shows the increase in delay for
load capacitances of 0, 1, 5, 10 and 20 picoFarads.

5-14

ECLinPS and ECLinPS Lite
DL140-Rev4

Transmission Line Theory

LINE
INPUT
THEVENIN EQUIVALENT SERIES TERMINATION

TD
,lTD
LOADED
RESPONSE
UNLOADED
RESPONSE

LINE
DUTPUT

THEVENIN EQUIVALENT PARALLEL TERMINATION

Figure 2.19b. ,lTD Introduced by Capacitive Load
r----VHIGH
tR =0.6a
a= 1.67tR

20%
VLOW ---"'t'/=0

Figure 2.21. Thevenin Equivalent Lumped
Capacitance Circuits
a:

2.0

./'

1.5
TIME

H=1000psldiv
V=200mV/div

,,/

1.0

Figure 2.20. Line Delay vs Lumped Capacitive Load
0.5

The increase in propagation delay can be determined by
using Thevenin's theorem to convert the transmission line
into a single time constant network with a ramp input voltage.
The analysis applies to both series and parallel terminations,
since both configurations can be represented as a single time
constant network with a time constant, 1:, and a Thevenin
impedance Z'.
Figure 2.21 shows the Thevenized versions for the series
and parallel terminated configurations. The Thevenin
impedance for the series configuration is approximately twice
that for the parallel terminated case, thus the time constant
will be two times greater for the series terminated
configuration. Since 1: is proportional to the risetime, the rise
time will also be two times greater; thus the reason for the
larger impact of capacitive loading on the series terminated
configuration.

ECLinPS and ECLinPS Lite
DL140-Rev4

0.0

0.5

1.0

1.5

2.5

2.0

NORMALIZED LlNE·LOAD TIME CONSTANT (Z'C/tR)

Figure 2.22. Normalized Delay Increase Due
to Lumped Capacitive Load
The relationship between the change in delay and the
line-load time constant is shown in Figure 2.22. Both the
delay change (hTO) and the line-load time constant (Z'e) are
normalized to the 20-80% risetime of the input signal. This
chart provides a convenient graphical approach for
approximating delay increases due to capacitive loads as
illustrated by the following example.

5-15

MOTOROLA

Transmission Line Theory
Given a 1000 series terminated line with a 5pF load at the
end of the line and a no load rise time of 400ps, the increase
in delay, dTD, can be determined using Figure 2.22. The
normalized line-load time constant is:

( ~f
'-

Z'C/tR = 1000'5pF/400ps = 1.25

~V
~ f----"

r--

=0.9

I--

Therefore:

r//

:-....

tR=950psJ

TIME

H=1000psldiv
V=l00mVldiv

dTD = 0.9'400ps = 360ps
Thus, 360ps Is added to the no load delay to arrive at the
approximate delay for a 5pF load. For a 1000 line employing
a matched parallel termination scheme, Z' 500, the added
delay is only 240ps. This added delay is significantly less
than the one encountered for the series terminated case.

Thus, when critical delay paths are being designed it is
incumbent on the designer to give special consideration to
the termination scheme, lumped loading capacitance and
line impedance to optimize the delay performance of the
system.
Distributed Capacitive Loads
In addition to lumped loading, capacitive loads may be
distributed along transmission lines. There are three
consequences of distributed capacitive loading of
transmission lines: reflections, lower line impedance, and
increased propagation delay. A circuit configuration for
observing distributed capacitive loading effects is shown in
Figure 2.23.

Figure 2.24. Reflections Due to Distributed
Capacitance
Increasing the number of distributed capacitive loads
effectively decreases the line characteristic impedance as
demonstrated by Figure 2.25. The upper trace shows that
reflections occur for approximately 3.5ns, during which time
the characteristic impedance of the line appears lower(~760)
than actual due to capacitive loading. After the reflections
have ended, the transmission line appears as a short and the
final steady state voltage is reached. The middle trace shows
that decreasing the termination resistance to match the
effective line characteristic impedance produces a response
typical of a properly terminated line. Finally, the lower trace
shows that the original steady state output can be attained by
changing the source resistance to match the load resistance
and the effective characteristic capacitance.

JI~

liJ
1ft

rltiSF
~IIIi ".'0
RS=ZO

'" s

ZO=50'1

-- -- - -

J-i

Figure 2.23. Transmission Line Model for Distributed
Capacitive Load
Each capacitive load connected along a transmission line
causes a reflection of opposite polarity to the incident wave. If
the loads are spaced such that the risetime is greater than
the time necessary for the incident wave to travel from one
load to the next, the reflected waves from two adiacent loads
will overlap. Figure 2.24 shows the output response for a
transmission line with two distributed capacitive loads of
2.0pF separated by a line propagation time of 750ps. The
upper trace, with a 20-80% input signal risetime of 400ps,
shows two distinct reflections. The middle and lower traces
with 2D-80% risetimes of 750 ps and 950ps, respectively,
show that overlap occurs as the risetime becomes longer
than the line propagation delay.

MOTOROLA

I----

LtR =400ps

I tR = 750ps

Using this value and Figure 2.22:
dToftR

1/
I /'-I.
II I;.

LRS= Rr=93'1
f'.,
RS 93n, Rr = 76'1

t---

RS=Rr=76'1J
TIME

H=2000psldiv
V=100mVldiv

Figure 2.25. Characteristic Impedance Changes
Due to Distributed Capacitive Loads
Reduced Line Characteristic Impedance

To a first order approximation the load capacitance (CLl is
represented as an increase in the intrinsic line capacitance
along that portion of the transmission line for which the load
capacitances are distributed. If the length over which the load
capacitances are distributed is defined as "L" the distributed
value of the load capacitance (CD) is given by
CD = CLlL

5-16

(Equation 11)

ECLinPS and ECLinPS Lite

DL140-Rev4

Transmission Line Theory
The reduced line impedance is obtained by adding Co to Co
in Equation 1.
ZO"(LO/CO)

Line Delay Increase
The increase in line delay caused by distributed loading is
calculated by adding the distributed capacitance (CO) to the
intrinsic line capacitance in Equation 2.
TpO = "(LO'CO)

Zo' "(Lot(CO + CO)) = "(LO/(CO'(1+CD/CO)))
TpO'
Zo' = ZOI"(1 + CD/CO)

(Equation 12)

For the circuit used to obtain the traces in Figure 2.25, the
distributed load capacitance is 4pF. From Equation 3, Co is
calculated as

TpO' = TpO '''(1 + CO/CO)

Zo' 9301"(1 + 4pF/8pF) = 760

Thus, the effective line impedance is 170 lower than the
actual impedance while reflections are occurring on the line.

ECLinPS and ECLinPS Lite

DL140- Rev 4

(Equation 1 3)

Once again, for the circuit used to obtain the traces in
Figure 2.25, the distributed load capacitance is 4pF. From the
previous example, the intrinsic line capacitance is 8pF
therefore,

Co = 750ps/930 = 8pF

Hence:

="(LO'(CO+CO))

TpO' = 750ps '''(1 + 4pF/8pF) = 919ps
Thus, the effect of distributed load capacitance on line delay
is to increase the delay by 169ps. From Equation 13 it is
obvious that the larger the Co of the line the smaller will be
the increase in delay due to a distributive capacitive load.
Therefore, to obtain the minimum impedance change and
lowest propagation delay as a function of gate loading, the
lowest charaCteristic impedance line should be used as this
results in a line with the largest intrinsic line capacitance.

5-17

MOTOROLA

MOTOROLA
SEMICONDUCTOR DESIGN GUIDE

SECTION 3
System Interconnect

Introduction
As mentioned earlier, edge rates of the ECLinPS family
are such that most interconnects must be treated as
transmission lines. Thus, a controlled impedance
environment is necessary to produce predictable
interconnect delays as well as limiting the reflection
phenomena of undershoot and overshoot. The three most
common techniques for circuit and/or system interconnect at
high data rates are microstrip, stripline and coaxial cable;
both microstrip and stripline are printed circuit board
methods, whereas coaxial cable is most often used for
interconnecting different parts of a system which are
separated by relatively large distances. For slower speed
applications «300MHz), a twisted pair scheme also works
well. The scope of this writing will not include the twisted pair
technique; however, a detailed discussion of this topic can be
found in the MECL System Design Handbook. Finally,
wirewrap boards are not recommended for the ECLinPS
family because the fast edge speeds exceed the capabilities
of normal wirewrapped connections. Mismatches at the
connections cause reflections which distort the fast signal,
significantly reducing the noise immunity of the system and
perhaps causing erroneous operation.

Printed Circuit Boards
Printed circuit boards (PCB's) provide a reliable and
economical means of interconnecting electrical Signals
between system components. Printed circuit boards consist
of a dielectric substrate over which the conducting printed
circuit material is placed. Three major categories of printed
circuit boards exist:

The most common printed circuit board material used for
digital designs is a glass-epoxy laminate. These boards use
a fiberglass dielectric with copper foils bonded to both sides
of the dielectric material by an epoxy resin. Other substrate
materials include a fiberglass dielectric with a polyimide resin
and fiberglass dielectric with a teflon resin. For multilayer
boards, the inner layers are separated by sheets of prepreg
which acts as both a dielectric material and a bonding agent
between layers.
The choice of substrate material depends on the function
for which the board will be used, the environment in which the
board is to operate, and costs. Table 3.1 lists several physical
qualities which characterize several of the the available PCB
types. Each available substrate material has its own
properties which makes it ideally suited for particular
applications.

Glass-Epoxy
Possesses good moisture absorption, chemical and heat
resistance properties as well as mechanical strength over
standard humidity and temperature ranges. The most widely
used versions are G10 and FR4, the fire resistant version of
G10.

Glass-Polyimide
Good for elevated temperature operation because of its
tight tolerance of the coefficient of thermal expansion. Very
hard material, so it may damage drilling equipment when
being drilled.

1. Single-sided boards

Glass-Teflon

2. Double-sided boards

Good for use when a low dielectric material is required.
Very soft material, so it may be difficult to build features
requiring precise geometries. Relatively expensive material.

3. Multilayer boards

Material

Dielectric
Constant

Dissipation
Factor

Thermal Coefficient
of Expansion

Glass-Epoxy
PTFE
Glass-Polyimide

Tensile
Modulus

4.8 (1.0MHz)

0.022 (1.0MHz)

13 -16 (10-6 o C)

2.5

2.1 (10GHz)

0.0004 (1OGHz)

224 (1 0-6°C)

0.05

4.5 (1.0MHz)

0.10 (1.0MHz)

12-14 (10-6°C)

2.8

Table 3.1. Characteristics of Common PCB Materials

MOTOROLA

5-18

ECLinPS and ECLinPS Lite
DL140-Rev4

System Interconnect
Microstrip
A microstrip line is the easiest printed circuit interconnect
to fabricate because it consists simply of a ground plane and
flat signal conductor separated by a dielectric (Figure 3.1).

I-

-I

h= 100

~~iEi~liDIIELIECITIRlcll

•••

II GROUND PLANE

TRACE WIDTH (mils)

Figure 3.1. Microstrip Line

The characteristic impedance, ZO, of a microstrip line is
given by:

87
Zo = ..J (Er+ 1.41)

(5.98' h) ]
(0.8w+t)

w
t
h

'\
~

(Equation 1)

where:
Er

£=4.8
t=I.4mils

= Relative Dielectric Constant of the Substrate
= Width of the Signal Trace
= Thickness of Signal Trace
= Thickness of the Dielectric

-.....

----

r--

105

125

CHARACTERISTIC IMPEDANCE'Zo(Q)

Figure 3.3. Line Capacitance vs Line Impedance
and Trace Width

Equation 1 is accurate to within ±5% when:
0.1 < w/h < 3.0 and 1 < Er < 15
To mitigate the effects of electric field fringing, an
additional constraint is that the width of the ground plane be
such that it extends past each edge of the signal line by at
least the width of the signal line.

150,-----r--....--.-----r---,
h= mils
~:-----1---+--+-- E =4.8
t=l.4mils

Figure 3.2 is a plot of characteristic impedance as a
function of trace width and dielectric thickness for a dielectric
constant of 4.8 and a trace thickness of 1.4mils (1 ounce
copper). Using the equation for CO, developed in the
previous chapter, and Equation 1, above, the capacitance
per unit length can be calculated for various trace widths.
Figure 3.3 Plots Co vs trace width for several different
dielectric thicknesses. In addition, Figure 3.3 plots Co vs the
characteristic impedance for a microstrip line for the dielectric
constant and trace thickness given above. The propagation
delay for a signal on a microstrip line is described by the
following equation:
TpD = 1.016..J(0.475\:r + 0.67) nslfoot

(eqt2)

h= 100
h=60

where:

=Dielectric Constant of the Board Material

h=30
30

50
70
TRACE WIDTH (mils)

110

Figure 3.2. Microstrip Impedance vs Trace Width

ECLinPS and ECLinPS Lite
DL140-Rev4

Note that the propagation delay is dependent only on the
dielectric constant of the PCB substrate. Figure 3.4 plots the
propagation delay of a microstrip line versus the dielectric
constant of the PCB.

5-19

MOTOROLA

System Interconnect
200

180

.s,
c 160
0..

:3
w

140

0..

II:
0..

120

'-'
z

C§
W
0..

O!!i
W

::J

V
100

b =60
40

b=mils
£=4.8

1-""<'""-+---+---+--- t= 1.4mils

6-7

11
14
TRACE WIDTH (mils)

DIELECTRIC CONSTANT (£r)

Figure 3.4. Propagation Delay vs Dielectric Constant

Figure 3.6. Stripline Impedance vs Trace Width

Stripline
Stripline is a printed circuit board interconnect in which a
signal conductor is placed in a dielectric medium which is
"sandwiched" between two conducting layers (Figure 3.5).

b= mils
£=4.8
t=I.4mils
11
14
TRACE WIDTH (mils)

Figure 3.5. Stripline Structure

ZO=-_,- In[
'I£r

4b
]
0.671t(0.8w + t)

£=4.8
1= 1.4 mils

The characteristic impedance of the stripline is given by:

(Equation 3)

""
where:
Er
w
t

=Relative Dielectric Constant of the Substrate
=Width of the Stripline

1
20

= Thickness of the Stripline
= Distance Between the Two Ground Planes

MOTOROLA

---

100

120

Figure 3.7. Stripllne Capacitance vs Impedance
and Trace Width

w/(b - t) < 0.35 and Vb < 0.25

As was the case with a microstrip line, the capacitance per
unit length of a stripline trace can be calculated using the Co
equation from Chapter 2. The graphs of Figure 3.7 plot the

CHARACTERISTIC IMPEDANCE·ZO (Q)

Equation 3 is accurate for the following dimension ratios:

Once again, using a fairly typical Er of 4.8 and a copper trace
thickness of 1.4 mils, the characteristic impedance of a
stripline interconnect can be plotted for various trace widths
and dielectric thicknesses (Figure 3.6).

------.....

capacitance of a stripline structure for a number of trace
widths as well as the Co versus the characteristic impedance
of the line.
The propagation delay of a stripline trace is governed by
the simple equation:
TPD = 1.016..J£r nslft

5-20

(Equation 4)

ECLinPS and ECLinPS Lite
DL140-Rev4

System Interconnect
where:
Er

= Dielectric Constant of the Board Material

Again, the propagation delay of the trace is dependent only
on the relative dielectric constant of the PCB substrate. Using
Equation 4 the delay of the line can be plotted vs dielectric
constant ( Figure 3.8 ).

inductance per unit length for a transmission line; in other
words, shape variations cause reflections. Bends in printed
circuit traces cause an increase in the capacitance per unit
length and a decrease in the inductance per unit length with a
pronounced effect for angles of 90° or more. Two techniques
available to compensate for shape changes are:
1. Maintain a uniform trace width.

270

Is
"

,B-

230

190

:'w5

"a.0

II:

150

110

2. Cut the corners of the trace such that the length of
the diagonal cut is in the range of 1.6 to 2.0 times
the trace width.

Figure 3.9 illustrates these two techniques.

V
2

DIELECTRIC CONSTANT (Er)
w

Figure 3.B. Strip line Propagation Delay vs
Dielectric Constant

Figure 3.9. Compensation for Capacitive Effects of
Trace Angles

General Information
Since fiberglass-epoxy is by far the most widely used
substrate in the industry, two important considerations should
be mentioned:
1. The propagation delay for microstrip is ~145ps per inch,
whereas that for stripline is ~185ps per inch. Since the
propagation delay is governed by the dielectric of the
substrate, a board material with a lower dielectric constant
than glass-epoxy is required if a lower propagation delay is
desired.
2. Cross coupled noise due to board geometries may require
a substrate material with a lower dielectric constant. For
example, the distance from the signal trace to the ground
plane is a function of the substrate dielectric constant for a
specified line characteristic impedance. Hence, the switching
energy coupled into adjacent traces on the same signal plane
is also a function of the dielectric constant. If the dielectric
thickness and trace width must be maintained for a given line
impedance, the spacing between traces must be increased
to maintain the noise margin. Since the dielectric constant of
glass-epoxy is relatively large, the increase in spacing
between the traces may be unacceptable. So, a substrate
material with a lower dielectric constant may be desirable.
Generally, if the distance between traces is maintained at
twice the distance to the ground plane, coupling between
traces will be minimal.
Finally, printed circuit signal line shape variations playa
significant role in modulating both the capacitance and

ECLinPS and ECLinPS Lite
DL140-Rev4

1.6w-2.Ow

Coaxial Cable
Coaxial cable is a two conductor transmission line
consisting of a concentric inner conductor surrounded by a
dielectric which in turn is surrounded by a tubular outer
conductor (Figure 3.10). It is ideal for transmitting high
frequency signals over long distances because of its well
defined and uniform characteristic impedance. Moreover,
crosstalk is minimized by the ground shield provided by the
outer conductor.
The propagation delay is derived in the same way as a
stripline interconnect and, thus, is described by Equation 4.
Therefore, as with stripline structures, the delay is a function

--Q:

IELECTRIC

OUTPUT
CONDUCTOR

INNER
CONDUCTOR

Figure 3.10. Cross Section of Coaxial Cable
of only the dielectric constant. The characteristic impedance
and capacitance per unit length are parameters specified by
the coaxial cable manufacturer; hence, the designer should
look to the cable manufacturer for these parameters.

5-21

MOTOROLA

System Interconnect
Coaxial Cable Lengths
The ECLinPS family operates with rise times as fast as
several hundred picoseconds; thus, coaxial cable must be
able to transmit these pulses without introducing a significant
distortion. Viewing the ECLinPS output as a single time
constant driver circuit terminated with a 50n load, the
required line bandwidth(fcl can be calculated as follows.

Additional information concerning coaxial cable can be found
in Motorola's MECl System Design Handbook.

Summary of Values
Table 3.2 is a compilation of propagation delays at nominal
dielectric values for the three types of interconnects
discussed.

(Equation 5)

fC=0.35/tR

where:
=10% to 90% Rise Time

Interconnect

TpD

£r

Microslrip
Stripline
Coaxial Cable

145pslin
185pslin
123pslin

4.8
4.8
2.1

Table 3.2 - Comparison of Interconnect Medium
Converting the typical 20% - 80% rise time value of 400ps to
an equivalent 10% - 90% rise time value of 530ps, and using
Equation 5 yields a bandwidth value of fC = 660MHz
Below 1.0GHz the primary loss mechanism in
transmission lines is skin effect, as dielectric losses for
materials such as polyethylene and teflon are insignificant
below this value. Since attenuation due to skin effect is
proportional to the square root of frequency, a log-log plot of
attenuation versus frequency produces a linear result. The
maximum coaxial cable lengths for the ECLinPS family can
be derived from the plot in Figure 3.11.

Termination Techniques
From transmission line theory, a signal propagating down
the line is partially reflected back to the source if the line is not
terminated in its characteristic impedance. The magnitude of
the reflected voltage signal is governed by the load reflection
coefficient, Pl.
Pl = (RT-ZO) I (RT+ ZO)

(Equation 6)

where:
1.48

1.30

iii

1.10

'"g

0.90

= load Impedance, and

= Characteristic Impedance of the Line

When the reflected signal arrives at the source it is
re-reflected back toward the load with a magnitude dictated
by the source reflection coefficient, PS.

~
zW

::J

0.50
0.30
7.6

(Equation 7)

Ps = (RS - ZO) I (RS+ZO)

0.70

where:
7.8

8.0

8.2

8.4

8.6

8.8

9.0

= Source Impedance

= Characteristic Impedance of the Line

LOG FREQUENCY (MHz)

Figure 3.11. Coaxial Cable Attenuation vs Frequency

Typically for an Eel system, the minimum peak-to-peak
signal swing is 600mV. The nominal peak-to-peak signal
swing for the ECLinPS family is approximately 850mV. Thus,
the maximum permissible attenuation is:

loss(dB)

= 20 • log (VINNO)
= 20 • log (0.85/0.6) = 3.0dB.

From Figure 3.11 the loss at 660MHz for RG58/U cable is 15
dB/l00 feet. Therefore, the maximum length is

The reflected signal continues to be re-reflected by the
source and load impedances and is attenuated with each
passage over the transmission line. The output response
appears as a damped oscillation asymptotically approaching
the steady state value. This phenomena is often referred to
as ringing.
The importance of minimizing the reflected Signals lies in
their adverse affect on noise margin and the potential for
driving the input transistors of the succeeding stage into
saturation. Both of these phenomena can lead to less than
ideal system performance. To minimize the potential hazards
associated with reflections on transmission lines three basic
termination techniques are available:
1. Minimizing Unterminated line lengths
2. Parallel Termination

Max length = 100 ft .• (3.0dB/15dB) = 20 ft.

MOTOROLA

3. Series Termination

5-22

ECLinPS and ECLinPS Lite
DL140-Rev4

System Interconnect
Unterminated Lines
Figure 3.12 illustrates an unterminated transmission line.
This configuration is also referred to as a stub or an open line.

Figure 3.12. Unterminated Transmission Line
The function of RE is to provide the drive current for a high
to low transition at the driver output. Since the reflection
coefficient at the load is of opposite polarity to that at the
source, the signal will be reflected back and forth over the
transmission with the polarity changing after each reflection
from the source impedance. Thus, steps appear at the input
to the receiving gate. When RE is too large, steps appear in
the trailing edge of the propagating signal that slows the edge
speed of the input to the receiving gate, subsequently
causing an increase in the net propagation delay. A
reasonable negative-going signal swing at the input of the
receiving gate results when the value of RE is selected to
produce an initial step of 600mV at the driving gate. Hence:
I'ZO> 0.6

(Equation 8)

(VOH - VEE)/(RE + ZO) , Zo <: 0.6

PS = (RO - ZO)/(RO + ZO)

(Equation 11)

The signal is re-reflected back toward the load arriving at time
3TO resulting in undershoot at point B. This re-reflection of
signals continues between the source and load impedances
causing ringing to appear on the output response.
The impetus in restricting interconnect lengths is to
mitigate the effects of overshoot and undershoot. A handy
rule of thumb is that the undershoot can be limited to less
than 15% of the logic swing if the two way line delay is less
than the rise time of the pulse. With an undershoot of < 15%,
the physics of the situation will result in an overshoot which
will not cause saturation problems at the receiving input.
Thus, the maximum line length can be determined using
Equation 12.
Lmax < tR/2'TpO (unit length)

(Equation 12)

where:

= Line Length

= Rise time

tR
TpO

=Propagation Oelay per unit Length

Further, the propagation delay increases with gate loading,
thus, the actual delay per unit length (TPO') is given as:
TpO'

=TpO \/(1 + Co I (L' CO))

Substitution of the modified delay per unit length into
Equation 12 and rearranging yields Equation 13:
tR <: (2 ' L) 'TpO '-./(1 + Co I (L 'CO» (Equation 13)

6.2Z0 <: RE (10E), 4.9Z0 <: RE (100E)

(Equation 9)
Solving Equation 13 for the maximum line length produces:

Load resistors of less than 1800 should not be used because
the heavy load may cause a reduction in noise immunity
when the output is in the high state due to an increased
output emitter-follower VBE drop.
When the driver gate delivers a full ECL swing, the signal
propagates from point A arriving at point B a time TO later. At
point B, the signal is reflected as a function of PL. The input
impedance of the receiving gate is large relative to the line
characteristic impedance, therefore:

PL = (RT-ZO)I (RT+ ZO)

(Equation 10)

A large positive reflection occurs resulting in overshoot.
The reflected signal reaches point A at time 2TO, and a large
negative reflection results because the output impedance of
the driver gate is much less than the line characteristic
impedance (i.e. RO « ZO). In this case, the reflection
coefficient is negative.

ECLinPS and ECLinPS Lite

DL140-Rev4

Lmax = 0.5 ' (-./( (CO I CO) " 2
(Equation 14)
+ (tRlTpO) , , 2) - CO/CO
Assuming a worst case capacitance of 2pF and a rise time of
200 ps for the ECLinPS family gives a value of 0.3 inches for
the maximum open line length.
Table 3.3 shows maximum open line lengths derived from
SPICE simulations for single and double gate loads, a
maximum overshoot of 40% and undershoot of 20% was
assumed. The simulation results indicate that for a 500 line,
a stub length of S; 0.3 inches will limit the overshoot to less
than 40%, and the undershoot to within 20% of the logic
swing. Signal traces will most assuredly be larger than 0.3"
for all but the simplest of interconnects, thus, for most
practical applications, it will be necessary to use ECLinPS
devices in a controlled impedance environment.

5-23

MOTOROLA

System Interconnect

Mlcrostrlp
ZO(Q)

50
68
75
82
90
100

Strlpllne

Fanout = 1

Fanout = 2

Fanout = 1

Fanoul=2

Lmax(ln)

Lmax(in)

L(max) (in)

0.3
0.3
0.3
0.3
100
0.25

0.2
0.15
0.15
0.1
0.1
0.1

0.3
0.25
0.25
0.25
0.25
0.25

0.15
0.1
0.1
0.1
0.1
0.1

Table 3.3. SPICE Derived Maximum Open Line Lengths for ECLinPS Designs

Parallel Termination
When the fastest circuit performance or the ability to drive
distributed loads is desired, parallel termination is the method
of choice. An important feature of the parallel termination
scheme is the undistorted waveform along the full length of
the line. A parallel terminated line is one in which the
receiving end is terminated to a voltage (Vn) through a
resistor (RT) with a value equal to the line characteristic
impedance (Figure 3.13a). An advantage of this technique is
that power consumption can be decreased by a judicious
choice of Vn. For 50n systems, the typical value of Vn is
negative two volts.

Although the single resistor termination to Vn conserves
power, it offers the disadvantage of requiring an additional
supply voltage. An alternate approach to using a single
power supply is to use a resistor divider network as shown in
Figure 3.13b. The Thevenin equivalent of the two resistors is
a single resistor equal to the characteristic impedance of the
line, and terminated to Vn. The values for resistors Rl and
R2 may be obtained from the following relationships:
R2 = (VEE/Vn)· Zo

(Equation 15)

Rl = (R2 • Vn)/(VEE - Vn)

(Equation 16)

For a nominal 1OE supply voltage of - 5.2V and Vn of - 2V:

(Equation 17)

Rl = R2/1.6

(Equation 18)

R2=2.6·

For a nominal 1OOE supply voltage of - 4.5V and Vn of - 2V
Vn

R2 =2.25· Zo

(Equation 19)

Rl =R2/1.25

(Equation 20)

FIGURE 3.13A PARALLEL TERMINATION TO Vn

Table 3.4 provides a reference of values for the resistor
divider network of Figure 3.13b.

ZO(Q)
50
70
75
80
90
100
120
150

Zo
VEE
FIGURE 3.138 THEVENIN EQUIVALENT PARALLEL TERMINATION

Figure 3.13 Parallel Termination Schemes

MOTOROLA

10E

100E

Rl(Q)

R2(Q)

Rl (Q)

R2(Q)

81
113
121
130
146
162
194
243

130
182
195
208
234
260
312
390

90
126
135
144
161
180
216
270

113
158
169
180
202
225
270
338

Table 3.4. Thevenln Termination Resistor Values

5-24

ECLinPS and ECLinPS Lite
DL140-Rev4

System Interconnect
For both configurations, when the equivalent termination
resistance matches the line impedance no reflection occurs
because all the energy in the signal is absorbed by the
termination. Hence, the primary tradeoff between the two
types of termination schemes are power versus power supply
requirements. As mentioned earlier, the Vn scenario
requires an extra power supply; however, the
Theveninization technique will consume 10 fold more DC
power. Fortunately, this extra power consumption will not be
seen on the die, therefore, both techniques will result in the
same die junction temperatures.
ECLinPS output drivers consists of emitter followers
designed to drive a 50Q load into a negative two volt supply
(Vn). Under these conditions, the nominal 1OE output levels
are -1.75 volts at SmA for the low state and - 0.9 volts at
22mA for the high state. For the 100E devices, the nominal
output levels are - 0.955 volts at 20.9mA for the high state
and 1.705 volts at 5.9mA for the low state.
Figure 3.14 shows the nominal output characteristics for
ECLinPS devices driving various load impedances returned
to a negative two volt supply. This plot applies to both 10E
and 100E versions of the ECLinPS family. The output
resistances, RH (high state output resistance) and RL (low
state output resistance), are obtained from the reciprocal of
the slope at the desired operating pOint. Many applications
require loads other than 50Q, the resulting VOH and VOL
levels can be estimated using the following technique.

VOH

VOL

Figure 3.15. Equivalent Model for
Calculating 10E Output Levels
where:
IHOUT = (- 770mV - Vn)/(6Q + Rr)
and
VOL =-1710mV- 8'1 LOUT

(Equation 22)

where:
ILOUT = (-1710mV - Vn) / (8Q + RT)
100E Devices
The equivalent output circuit is shown in Figure 3.16. The
output levels are estimated from Figure 3.16 as follows:

VOH = - 830mV - 6'IHOUT

1!z

(Equation 23)

where:
IHOUT = (- 830mV - Vn) / (60 + RT)

a:
a:

VOH
-830mV

VOL

-40u-__
-2.0

-1.75 -1.5 -1.25

__- L__- L__

-1.0 -0.75 -0.5 -0.25

OUTPUT VOLTAGE (V)

Figure 3.14. ECLlNPS Output Characteristics

VTT

-1660mV

10EDevices
The equivalent output circuit is shown in Figure 3.15. The
output levels are estimated from Figure 3.15 as follows:

VOH = - 770mV - 6'IHOUT

ECLinPS and ECLinPS Lite
Dl140- Rev 4

Figure 3.16. Equivalent Circuit for
Calculating lODE Output Levels

(Equation 21)

5-25

MOTOROLA

System Interconnect
and
VOL = -1660mV - 8 • ILOUT

(Equation 24)

where:
ILOUT = (-1660mV - Vn)/(80 + RT)
SIP Resistors
The choice of resistor type for use as the termination
resistor has several alternatives. Although the use of a
discrete, preferably chip resistor, offers the best isolation and
lowest parasitic additions, there are SIP resistor packs which
will work fine for ECLinPS designs. SIP resistors offer a level
of density which is impossible to obtain using their discrete
counterparts. However, there are some guidelines which the
user should follow when using SIP resistor packs. Always
terminate complimentary outputs in the same pack to
minimize inductance effects on the SIP power pin. Noise
generated on this pin will couple directly into all of the
resistors in the pack. In addition, the SIP package should
incorporate bypass capacitors in the design (Figure 3.17).
These capacitors are necessary to help maintain a solid Vn
level within the package, again mitigating any potential
crosstalk or feed through effects. A 10 pin SIP like the DALE
CSRC-10B21-500J/103M, is suitable for providing 500
terminations while maintaining a relatively noise free
environment to non-switching inputs.

Figure 3.17. Standard EeL 10 pin SIP
Series Termination Technique
Series Damping is a technique in which a termination
resistance is placed between the driver and the transmission
line with no termination resistance placed at the receiving
end of the line (Figure 3.18).
Series Termination is a special case of series damping in
which the sum of the termination resistor (RST) and the
output impedance of the driving gate (RO) is equal to the line
characteristic impedance.

As mentioned in the Transmission line section, series
termination techniques are useful when the interconnect
lengths are long or impedance discontinuities exist on the
line. Additionally, the signal travels down the line at half
amplitude minimizing problems associated with crosstalk.
Unfortunately, a drawback with this technique is the
possibility of a two step signal appearing when the driven
inputs are far from the end of the transmission line. To avoid
this problem, the distance between the end of the
transmission line and input gates should adhere to the
guidelines specified in Table 3.3 from the section on
unterminated lines.

Series Termination Theory
When the output of the series terminated driver gate
switches, a change in voltage (LWB) occurs at the input to the
transmission line:
~VB

where:
VIN
20
RS
RST

= VIN • (20) I (RST + RS + 20)

(Equation 25)

= Internal Voltage Change
= Line Characteristic Impedance
= Output Impedance of the Driver Gate
= Termination Resistance

Since 20

=RST + RS substitution into Equation 25 yields:
(Equation 26)

From Equation 26 an incident wave of half amplitude
propagates down the transmission line. Since the
transmission line is unterminated at the receiving end, the
reflection coefficient at the load is approximately unity;
therefore, the reflection causes the voltage to double at the
receiving end. When the reflected wave arrives at the source
end, its energy is absorbed by the series resistance,
producing no further reflections as the impedance is equal to
the characteristic impedance of the line.
An extension of the series termination technique, using
parallel fanout, eliminates the problem of lumped loading at
the expense of extra transmission lines (Figure 3.19).
RSTn

=Zo=D-

~:r=)

n (TOTAL NUMBER OF LINES)

RST+RO=20

Figure 3.19. Parallel Fanollt using Series Termination

Figure 3.18. Series Termination

MOTOROLA

Calculation of RE
RE functions to establish VOH and VOL levels and to
provide the negative going drive into RST and 20 when the
driver output switches to the low state. The value of RE must

5-26

ECLinPS and ECLinPS Lite

DL140- Rev 4

System Interconnect
be such that the required current is supplied to each
transmission line while not allowing the output transistor to
turn off when switching from a high to a low state. An
appropriate model is to treat the output emitter follower as a
simple switch (Figure 3.20).

VOH = - 0.9V, VSWING = 0.85V, VEE = - 5.2
[- 0.9 - (-5.2)] I RST + RE + ZO) ;" 0.531 I Zo
(Equation 29)
For the 100E series:
VOH = - 0.955V, VSWING = 0.75, VEE = - 4.5V
(Equation 30)

6.56 ' Zo - RST > RE

Figure 3.20. Equivalent Circuit for RE Determination
The worst case scenario occurs when the driver output
emitter follower is cutoff during a negative going transition.
When this happens, the switch can be considered opened
and, at the instant it opens, the line characteristic impedance
behaves as a linear resistor returned to VOH. The model
becomes a simple series resistive network as shown in
Figure 3.21.

Figure 3.19 showed a modification of the series
termination scheme in which several series terminated lines
are driven by a single EeL gate. The principle concern when
applying this technique is to maintain the current in the output
emitter follower below the maximum rated value. The value
for RE can be calculated by viewing the circuit in terrns of
conductances.
(Equation 31)
For the 10E series

11 (7.10'Z01 - RST1) +
11 (7. 1O'Z02 - RST2) +
11 (7.10'Z03 - RSTn)
For the case where
Z01=Z02= .. ·ZOn and RST1=RST2= RSTn
RE:S; (7.10 'ZO - RST) I n

Figure 3.21. Equivalent Circuit with Output Cutoff
The maximum current occurs at the instant the switch
opens and is given by Equation 27.

where n is the number of parallel circuits.
For the 100E series

11 (6.56'Z01 - RST1) +
1 I (6.56'Z02 - RST2) +
1 I (6.56'Z03 - RSTn)

IMAX = (VOH - VEE) I (RE + RST = Zo)(Equation27)
The initial current must be sufficient to generate a transient
voltage equal to half of the logic swing since the voltage at
the receiving end of the line doubles for the series terminated
case. To insure the pull down current is large enough to
handle reflections caused by discontinuities and load
capacitances, the transient voltage is increased by 25%.
Therefore.

(Equation 32)

For the case where
Z01=Z02= .. ·ZOn and RST1=RST2= RSTn
RE :s; (6.56 'ZO - RST) I n

(Equation 33)

where n is the number of parallel circuits.
IINIT = (1.25'VSWING/2) I Zo

(Equation 28)

To satisfy the initial constraints IMAX > liNT
(VOH-VEE)/(RE+RST+ZO»(1.25'VSWING/2) /ZO

When a series terminated line is driving more than a single
EeL load the issue of maximum number of loads must be
addressed. The factor limiting the number of loads is the
voltage drop across the termination resistor caused by the
input currents to the EeL loads when the loads are in the
quiescent high state. A good rule of thumb is to determine if
the loss in high state noise margin is acceptable. The loss in
noise margin is given by

For the 1OE series

EClinPS and EClinPS lite
DL140-Rev4

NMLOSS = IT' (RST + RO)

5-27

(Equation 34)

MOTOROLA

System Interconnect
is 1S01lA. Thus, for the circuit shown in Figure 3.22, in which
three gate loads are present in a son environment, the loss
in high state noise margin is calculated as:

NMLOSS = 3 • 1S01lA • son = 22.SmV

ECLinPS VO SPICE Modeling Kit

Figure 3.22. Noise Margin Loss Example
where:
IT

=Sum of IINH Currents

For the majority of devices in the ECLinPS family the
typical maximum value for quiescent high state input current

MOTOROLA

Due to the heavier reliance on simulation tools for initial
prototyping, Motorola has put together a SPICE modeling kit
aimed at aiding the customer in modeling board interconnect
behavior. The kit includes representative drivers and
receivers as well as the necessary SPICE model parameters.
In addition, tips are provided for simulating a wide range of
output conditions. The kit, in conjunction with today's CAD
tools, can greatly simplify the design and characterization of
critical nets in a design. Anyone interested in using SPICE for
this purpose, is encouraged to read Application Note AN1S03
located on page 5-69.

5-28

ECLinPS and ECLinPS Lite
DL140-Rev4

MOTOROLA
SEMICONDUCTOR DESIGN GUIDE

SECTION 4
Intefacing with ECLinPS
Interfacing to Existing Eel Families
There currently exists two basic standards for high
performance ECl logic devices: 10H and 1OOK. To maximize
system flexibility each member of the ECLinPS family is
available in both of the existing ECl standards: 10E series
devices are compatible with the MECl 10H family; 100E
series devices are compatible with ECl 100K.

100K DRIVING 10H
-0.8
-1.0
~
w

The difference in the DC behavior of the outputs of the two
different standards necessitates caution when mixing the two
technologies into a single ended input design. As illustrated
in Figure 4.1 and Table 4.1, there is no problem when a 10H
device is used to drive a 100K device; however, problems
arise when the scenario is reversed.

...c..
::::>
::::>

;:::

10H
100H
100H
10H

150mV
145mV
130mV
35mV

Table 4-1. Worst-Case Noise Margins of a
Mixed 10H and 100K DeSign
gate-gain delay (delay vs input edge rate) can be assumed or
a more typical value of ±75psins can be used.

ECLinPS and ECLinPS Lile
DL140-Rev4

10H DRIVING 100K
-0.8
100KVOH RANGE
-1.0
~
w -1.2

!:;

...

-1.4

c..

::::>

-1.6

;:::
::::>

c..

-1.8

100K VOL RANGE

NM-Low
150mV
125mV
135mV
130mV

-1.8

TEMPERATURE (0C)

Obviously, a very slow edge rate will amplify differences in
delay paths due to any offset of the VSS switching reference.
This extra delay should be included in speed calculations of a
design. For calculation purposes a worst case ± 200psins

10H >
10H >
100H>
100H>

-1.6

Another area of concern when interfacing to older, slower
logic families, is the behavior of ECLinPS devices with slower
input edge rates. Typically, other than clock inputs, the
ECLinPS family will function properly for edge speeds of up
to 20ns. For edges significantly slower than 20ns, the Schmitt
trigger circuit of Figure 4.2 can be used to sharpen the edge
rates reliably.

NM-High

-1.4

::::>

Fortunately, the ECLinPS family, by offering devices in
both standards, allows the user to integrate higher
performance technology into his design without having to
battle these interface problems.

Drvr> Rcvr

-1.2

TEMPERATURE (0C)

Figure 4.1. InterfaCing 10H ECl and 100K ECl
Clock inputs on flip-flop devices in the ECLinPS family are
especially sensitive to slow edge rates. Flip-flops have been
successfully clocked in a noise free bench setup environment
with edge rates of up to 20ns. However, in ATE systems
where more noise is present, clocking problems arise with
input edge rates of greater than 6.0 or 7.0ns. To ensure
reliable operation in a system with input clock edges slower
than 7.0ns, it is recommended that the signals be buffered

5-29

MOTOROLA

Intefacing with ECLinPS
with an ECLinPS buffer circuit (E122, E116, E101, etc.) or, for
extreme conditions, the Schmitt trigger of Figure 4.2 to
provide the gain necessary to sharpen the edges on the clock
pulse.

......; : - - - - - . - - - , ) OUT

ACCoupling
In some cases, it may be necessary to interface an
ECLinPS design with a signal which lacks any DC offset.The
differential devices in the ECLinPS family are ideally suited
for this application. As pictured in Figure 4.3, the signal can
be AC coupled and biased around the VBB switching
reference of the device. Note that this scheme only works for
a data stream with no DC bias, for data streams such as RZ
or unencoded NRZ DC, restoration must be performed prior
to AC coupling it to an ECLinPS device.
IN

o--J 1----.----(

OUT

0.001j.lF
400Q

50Q

Vas

50Q

Vrr

Vas

50Q

Vrr

Figure 4.2. Schmitt Trigger w/100MV of Hysteresis
Figure 4_3. AC Couple Circuit

Interfacing to TTUCMOS Logic
To interface ECLinPS devices to TTL or CMOS
subsystems there exists several new product offerings, as
well as several existing devices, in the MECl 10KH family
which are ideally suited to the task. These translation devices
are specially suited for clock distribution, DRAM driving as
well as general purpose translation in both single supply and
dual supply environments. In mixed technology
environments, it is recommended that the noisy supplies of
TTL and CMOS circuits be isolated from the ECl supplies.
This can be done either through separate power planes in the
board or a common plane with isolated ECl and TTL power
sub-planes. The planes of common voltages (i.e. ECl VCC
and TTL ground for split supply systems or common VCC and
ground for a single supply system) should then be connected
to a common system ground or power supply through an
appropriate edge connector.

InterfaCing to GaAs Logic
In general GaAs logic is designed to interface directly with
ECl; however, in some instances, the worst case VOH of a
GaAs output can go as high as - 0.3V. An ECLinPS device,
depending on the input structure, may become saturated
when driven with a - 0.3V signal. Application Note AN1404,
on page 5--45, deals exclusively with this phenomenon.

MOTOROLA

The 500 resistor of Figure 4.3 provides the termination
impedance while the VBB pin provides the DC offset. The
capacitor used to couple the signal must have an impedance
of « 500 for all frequency components of the input signal.
Because large capacitors appear somewhat inductive at high
frequencies, it may be necessary to use a small capacitor in
parallel with a larger one to achieve satisfactory operation. In
addition, it is important to bypass the VBB line when used in
this manner to minimize the noise" coupled into the device.
Because the AC signal is biased around VBS, the output of
the ECLinPS device, when AC coupled, will have a duty cyCle
identical to the input. Thus, this type of application is ideal for
transforming high frequency sinusoidal waveforms from an
oscillator into a square wave with a 50% duty cycle. The
E416 device is a specialized line receiver with a much higher
bandwidth than alternative ECLinPS devices; therefore, for
frequencies of > 500MHz, it is recommended that the
designer use this device.
The above mentioned scenario will work fine as long as
the input signal is present, however, if the the inputs to the AC
coupled device are left open, problems may occur. With no
input signal both inputs will go to VBB and an undefined
output, and perhaps, an oscillating output, will result. If a
defined output is necessary for an open input scenario, the
circuit of Figure 4.4 can be used. The resistor tree between
VCC and VBB creates an offset between the two inputs so that
if the driving signal is lost, a stable defined output will occur.

5--30

ECLinPS and ECLinPS Lite
DL140-Rev4

Intefacing with ECLinPS

Vee
2.51ill
IN

o-J 1--+---1 ..........,......------,;----{

OUT

O.OO1 IlF

)-----4--,-{J OUT

generated VBB level. If more current is needed, several gates
can be connected in parallel to provide the extra drive
capability.
Note that the circuit pictured in Figure 4.4 will result in the
Q outputs going high when the inputs are left open. If the
opposite is desired, the resistor to VCC can be tied to the
inverting input and VBB to the non-inverting input.

O.OlIlF

~
Vss

50n

Vas

}-...l.----,.-IO Vss

Figure 4.4. AC Couple Circuit with DC Offset

50n
SINGLE GATE VSS GENERATOR

Unfortunately, this configuration will adversely affect the
duty cycle of the output. Depending on the frequency of the
output, the duty cycle will change due to the longer distance
to threshold on a rising edge as opposed to a falling edge.
With this in mind, it becomes obvious that the smallest
feasible offset would be the best solution. For stability, a
minimum of 25mV is recommended, however, this will not
produce full ECL levels at the outputs of an E116 and, thus,
another differential gate should be used to further amplify the
signal. The gain of the E416, on the other hand, is sufficient to
produce acceptable levels at the outputs for DC input voltage
differences of 25mV. If a 150mV offset is used, full ECL levels
will be seen at the outputs of the E116, however, the price in
duty cycle skew will be high. Of course, if the signal is divided
after it is received, the duty cycle will be restored.
When using the circuit of Figure 4.4 care should be taken
to limit the current sunk by the VBB pin to a maximum of
O.5mA. To achieve an offset of greater than 25mV for the
circuit of Figure 4.4, the DC current will necessarily need to
be greater than O.5mA. To alleviate this dilemma, one of the
gates of the E116 can be configured as pictured in Figure 4.5
to generate a VBB reference with the necessary current
sinking capability. A single gate configured in this way will
source or sink up to 10mA without a significant shift in the

ECLinPS and ECLinPS Lile
DL140-Rev4

Vas

}-+----,.-·O

Vss

Vaa

50n

MULTIPLE GATE Vaa GENERATOR

Vn
Figure 4.5. High Current Ves Generator

5-31

MOTOROLA

MOTOROLA
SEMICONDUCTOR DESIGN GUIDE

SECTION 5
Package and Thermal Information

Package Choice

Reliability of Plastic Packages

ECLinPS is offered in the 28-lead plastic leaded chip
carrier (PLCC) package, a leaded surface mount IC package.
The lead form is of the "J-Iead" type. For detailed dimensions
of the 28-lead PLCC refer to the package description
drawings at the end of this section.

Although today's plastiC packages are as reliable as
ceramic packages under most environmental conditions, as
the junction temperature increases a failure mode unique to
plastiC packages becomes a significant factor in the long
term reliability of the device.
Modem plastiC package assembly utilizes gold wire
bonded to aluminum bonding pads throughout the
electronics industry. As the temperature of the silicon
Ounction temperature) increases, an intermetallic compound
forms between the gold and aluminum interface. This
intermetallic formation results in a significant increase in the
impedance of the wire bond and can lead to performance
failure of the affected pin. With this relationship between
intermetallic formation and junction temperature established,
it is incumbent on the designer to ensure that the junction
temperature for which a device will operate is consistent with
the long term reliability goals of the system.
Reliability studies were performed at elevated ambient
temperatures (125°C) from which an arrhenius equation,
relating junction temperature to bond failure, was
established. The application of this equation yields the table
of Figure 5.2. This table relates the junction temperature of a
device in a plastiC package to the continuous operating time
before 0.1 % bond failure (1 failure per 1000 bonds)
ECLinPS devices are designed with chip power levels that
permit acceptable reliability levels, in most systems, under
the conventional 500 Ifpm (2.5m/s) airflow.

The PLCC was selected as the optimum combination of
performance, physical size and thermal handling in a low
cost standard package. While more exotic packages exist to
improve these qualities still further; the cost of these is
prohibitive for many applications.
The PLCC features considerably faster propagation delay
and reduced parasitics compared to a DIP package of similar
pin-count; two properties that make it eminently suitable for
very high performance logic.
The 28-lead PLCC for the ECLinPS family is available in
tape and reel form to further facilitate automatic pick and
place. The characteristics of the 28-lead PLCC reel are
described in Figure 5.1 below.

General Information
REEL SIZE: 13" (330mm)
TAPE WIDTH: 24mm
UNITSIREEL: 500

Mechanical Polarization

VIEW FROM
TAPE SIDE

LINEAR DIRECTION OF TRAVEL

Figure 5.1. 28-Lead PLCC Tape & Reel Information

Orders must be full reels or multiples of full reels as no
partial reels will be shipped. An R2 suffix has been
established to add to the end of the part number to signify the
desire for tape and reel product. Therefore, to order the
MC10El11FN in tape and reel the part number would
become MC10El11FNR2.

MOTOROLA

Thermal Management
As in any system, proper thermal management is
essential to establish the appropriate trade-off between
performance, density, reliability and cost. In particular, the
designer should be aware of the reliability implication of
continuously operating semiconductor devices at high
junction temperatures.
The increasing popularity of surface mount devices (SMD)
is putting a greater emphasis on the need for better thermal
management of a system. This is due to the fact that SMD
packages generally require less board space than their
through hole counterparts so that designs incorporating SMD
technologies have a higher thermal density. To optimize the
thermal management of a system it is imperative that the
user understand all of the variables which contribute to the
junction temperature of the device.

5-32

ECLinPS and ECLinPS Lile

DL140-Rev4

Package and Thermal Information

=6.376 x 10 -9 e l

11554.267
[273.15+ TJ

Calculating Junction Temperature
The following equation can be used to estimate the
junction temperature of a device in a given environment:

Where:
T = Time to 0.1 % bond failure
Junction
Temp. (OC)

Time (Hrs.)

Time (yrs.)

80
90
100
110
120
130
140

1,032,200
419,300
178,700
79,600
37,000
17,800
8,900

117.8
47.9
20.4
9.1
4.2
2.0
1.0

Figure 5.2 Tj vs Time to 0.1 % Bond Failure
The variables involved in determining the junction
temperature of a device are both supplier and user defined.
The supplier, through lead frame design, mold compounds,
die size and die attach, can positively impact the thermal
resistance and, thus, the junction temperature of a device.
Motorola continually experiments with new package designs
and assembly techniques in an attempt to further enhance
the thermal performance of its products.
It can be argued that the user has the greatest control of
the variables which commonly impact the thermal
performance of a device. Ambient temperature, air flow and
related cooling techniques are the obvious user controlled
variables, however, PCB substrate material, layout density,
size of the air-gap between the board and the package,
amount of exposed copper interconnect, use of
thermally-conductive epoxies and number of boards in a box,
can all have significant impacts on the thermal performance
of a system.
PCB substrates all have different thermal characteristics,
these characteristics should be considered when exploring
the PCB altematives. The user should also account for the
different power dissipations of the different devices in his
system and space them on the PCB accordingly. In this way,
the heat load is spread across a larger area and "hot spots"
do not appear in the layout. Copper interconnect traces act
as heat radiators, therefore, significant thermal dissipation
can be achieved through the addition of interconnect traces
on the top layer of the board. Finally, the use of thermally
conductive epoxies can accelerate the transfer of heat from
the device to the PCB where it can more easily be passed to
the ambient.
The advent of SMD packaging and the industry push
towards smaller, denser designs makes it incumbent on the
designer to provide for the removal of thermal energy from
the system. Users should be aware that they control many of
the variables which impact the junction temperatures and,
thus, to some extent, the long term reliability of their designs.

ECLinPS and ECLinPS Lite
DL140-Rev4

where:

=
=

TJ
Junction Temperature
TA
Ambient Temperature
PD = Power Dissipation
ElJA = Avg Pkg Thermal Resistance (Junction Ambient)
The power dissipation factor is made up of two elements: the
intemal gate power and the power associated with the output
terminations. Essentially, the two contributors can be
calculated separately, then added to give the total power
dissipation for a device.
To calculate the power of the internal gates the user simply
multiplies the lEE olthe device times VEE. Since lEE in ECl is
a constant parameter, frequency need not be factored into
the ·calculations. A worst case or typical number for chip
power can be calculated by using either worst case or typical
data book values for the lEE and VEE of a device.
Next, the power of the outputs needs to calculated so that
the total power dissipation for a device can be determined.
The output power is dependent on the termination resistance
and the termination scheme used to pulldown the outputs.
The most typical termination scheme for ECLinNPS designs
is a parallel termination into - 2.0V. For this scheme, the
following equation describes the power for a single output of
the device:
PDOUT = lOUT' VOUT = (VOUT - (- 2)) RT'VOUT
where:
VOUT = VOH or VOL
RT
= Termination Resistance
The power dissipated in the output of a device is dependent
on the duty cycle of that output. For an output terminated to
Vn the worst case situation would be if the output was in the
high state all of the time, for an output terminated to VEE the
low state will represent worst case. For single ended output
devices, typically the power is calculated with the outputs in
the worst case and for a 50% duty cycle. For differential
outputs, the power for a differential pair is constant since they
are always in complimentary states, therefore, for a given
output, the power will simply be the average of the high and
low state output powers. Figure 5.3 shows the various output
power levels for the different output types and conditions. In
addition, the table includes power numbers for various other
termination resistances and alternative termination schemes.
These numbers can be derived by determining the lOUT and
VOUT forthe different alternatives and applying the equation
above.

5~3

MOTOROLA

Package and Thermal Information

Output Power (mW)
Termination
Resistance

Differential Output
10E

100E

10E

100E

10E

100E

50to-2.0V
68to-2.0V
100to-2.0V

14.3
10.5
7.1

15.0
11.1
7.5

14.3
10.5
7.1

15.0
11.1
7.5

19.8
14.6
9.9

20.0
14.7
10.0

510to-5.2V
330to-5.2V
180to-5.2V

9.7
15.0
27.5

9.8
15.1
27.8

9.7
15.0
27.5

9.8
15.1
27.8

11.8
18.3
33.5

11.7
18.0
33.1

510to-4.5V
330to-4.5V
180to-4.5V

7.8
12.3
22.6

Single-ended Output
(50%) Duty Cycle)

Single-ended Output
(Worst Case)

9.3
14.4
26.4

Figure 5.3 Output Power for Various Termination Schemes

Now that the power dissipation of a device can be
calculated, one needs to determine which level of the
parameter (i.e. typical, max, etc .. ) to use to estimate the long
term reliability of the system. Since this number is statistical
in nature, simply applying the worst case numbers will be
overly pessimistic as these parameters vary statistically
themselves. It is not very likely, for instance, that every
device type will be operating at the maximum specified lEE
level. Assuming all worst case conditions can have a
significant impact on the resulting junction, temperature
estimates leading to erroneous conclusions about the
reliability of the deSign.
Another important parameter for calculating the junction
temperature of a device is the junction-ambient thermal

resistance, 9JA, of the package. 9JA is expressed in °C per
watt (OCfW) and is used to determine the temperature
elevation of the die Ounction) over the external package
ambient temperature. Standard lab measurements of this
parameter for the 28-lead PLCC yields the graph of Figure

5.4.
An alternative calculation scheme for TJ substitutes the
case temperature (TC) and the junction-to-case (9JC)
thermal resistance for their ambient counterparts in the TJ
equation previously mentioned. The 9JC for the 28-lead
PLCC is 32°C/W. This parameter is measured by
submerging the device in a liquid bath and measuring the
temperature of the bath, therefore, it represents an average
case temperature.

80
70

Air Flow (fpm)

0(JA) ('CIW)

0
125
250
500
1000

63.5
52
48
43.5
38

......

r-- r-----

30
20

125

250

375

SOD

625

7SO

875

1000

AIR FLOW (I!pm)

Figure 5_4. Thermal Resistance vs Air Flow for the 28-lead PLCC

MOTOROLA

5--34

ECLinPS and ECLinPS Lite
DL140-Rev4

Package and Thermal Information
The difficulty in using this method arises in the determination
of the case temperature in an actual system. The case
temperature is a function of the location at which the
temperature is measured on the package. Therefore, to use
the 8JC mentioned above, the case temperature would have
to be measured at several different points and averaged to
represent the TC of the device. This, in practice, could prove
difficult and relatively inaccurate.

actual thermocouple temperature measurements may limit
its use.
The equation describing the junction temperature is as
follows:
TJ = 24PD + 0.313TC + 0.687TL °C/W (± 2°C/W)
where:
PD
TC
TL

Junction Temperature Calculation Example
As an example, the power dissipation for a 1OE151, 6-bit
register function, will be calculated for 500 Ifpm airflow; both a
worst case number and a typical number will be calculated.
From the data sheet the typical and maximum lEE's for the
device are 65mA and 85mA respectively. There are six
differential output pairs.
Chip Power =
65mA • 5.2V=338mW typical
85m A * 5.46V = 464mW worst case
Output Power =
«-1.75 - (- 2))/50*1.75 + (- 0.9 (- 2))/50*0.9))/2 =
14.3mW
Total Power Pd =
338mW + 14.3*12 = 510mW typical
464mW + 14.3*12 = 635mW worst case
Junction Temperature =

= Power Dissipation of the Device (W)
= Case Temperature (0C)
= Lead Temperature (0C)

TC is measured at the top-center surface of the package,
taking care that the thermocouple makes good contact with
the case without transporting a significant amount of heat
from the measurement point. The lead temperature is used to
compensate for the differences in the ratio of heat transfer
through the leads and the top surface of the package. This
difference impacts the actual TC of the package. As
mentioned earlier, this method of determining the junction
temperature is effective for almost all environmental
conditions except those that incorporate an external
heatsink. Of all the techniques mentioned in this document,
the application of this equation will lead to the most accurate
assessment of the junction temperature of a device.

Heatsinks
A plastiC fin type heatsink recently developed by EG&G
Engineering for a 40-lead PLCC was modified to fit the
28-lead

TA + 43.5°C/W* 0.510W = TA + 22°C typical
TA + 43.5°C/W* 0.635W = TA + 28°C worst case'
Note that in this case, the worst case junction
temperatures are not significantly larger than the typical
case. This is due mainly to the fact that the device has
differential outputs. A higher lEE, single ended device would
show a much larger discrepancy between the worst case and
typical values.

Limitations to Calculation Technique
The use of the previously described technique for
estimating junction temperatures is intimately tied to the
measured values of the 8JA of the 28-lead PLCC package.
Since this parameter is a function of not only the package, but
also the test fixture, the results may not be applicable for
every environmental condition. The 28-lead PLCC test fixture
used was a 2.24" x 2.24" x 0.062", FR4 type, glass epoxy
board with 1 oz. copper used for interconnects. The copper
represented about 50% coverage of the test fixture.

0.76
(0.030)

Unit: mm (inch)
Min. Value

If the user's actual application does not come close to
approximating this situation it may be necessary to use a
different method for determining the junction temperature of a
device. An empirical equation relating junction temperature
to the actual case temperature and lead temperature of a
device has been established. This equation has the
advantage of being universal for ali environmental
conditions, however, the disadvantage of having to make

ECLinPS and ECLinPS Lite
DL140-Rev4

-I I- -II- (0.020)
0.51

Dimension A

Inches

0.430

10.9

PLCC-28

0.530

13.5

PLCC-44

0.630

PLCC-20

Figure 5.5 - PLCC PCO Solder Pad Dimensions

5-35

MOTOROLA

Package and Thermal Information
PLCC and evaluated. The addition of the heatsink showed a
decrease of 20°CIW in the thermal resistance of the 28-lead
PLCC in a natural convection air flow environment. The test
device was suspended in air to simulate a dense board
application where minimal heat will transfer from the device
to the PCB substrate.
For more detailed information on availability and
performance of heatsinks the user is encouraged to contact
the numerous heatsink vendors.

MOTOROLA

Package Dimensions
Figure 5.5 on the previous page provides recommended
printed circuit board solder pad dimensions for several PLCC
packages. With this information and the 28-lead PLCC
dimensions provided in Figure 5.6, the system designer
should have all of the information necessary to successfully
mount 28-lead PLCC packages on a surface mount PCB.

5-36

ECLinPS and ECLinPS Lite
DL140-Rev4

Case Outlines

Case Outlines
a-Pin Package
o SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
ISSUE P
NOTES:
1. DIMENSIONS A AND BARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M,1982.
3. DIMENSIONS ARE IN MIWMETER.
4. DIMENSION A AND B DO NOTINCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSJON 0 DOES NOT INCWDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127TOTAL IN EXCESS
OF THE 0 DIMENSION AT MAXIMUM MATERIAL
CONDITION.

[±]

DIM
A

* &CJCJcnJ~
~qi.:X; ~~PLANE

C
D
F
G
J
K
M
P
R

SEAliNG

1$1 O.25(O.010)®ITI B ®IA®I

MIl.UMETERS
MIN
MAX
4.80
500
3.80
400
1.35
1.75
0.35
0.49
0.40
1.25
127BSC
0.18
.25
0.10
0.25
7°
0°
5.60
620
025
0.50

16-Pin Packages
o SUFFIX
PLASTIC SOIC PACKAGE
CASE 7518-05
ISSUEJ
NOTES:
1. DIMENSIONING AND TOlERANCING PER ANSI

Y14.5M,1982.
2. CONTROlliNG DIMENSION: MILUMETER.
3. DIMENSIONS A AND B 00 NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION 0 DOES NOT INCLUDE DAM BAR
PROTRUSION. AllOWABLE DAMBAR
PROTRUSION SHALL BE n 127 (0.005) TOTAL
IN EXCESS OF THE 0 DIMENSION AT
MAXIMUM MATERIAL CONDITION.

[±] sFfJl~~

DIM
A
B
C
D
F
G
J
K
M
P
R

_jDL- -CJ-CJ-a -CJ~r.
-t t

[fa a a

D 16PL

1$1 O.25(O.010)®ITI B ®I A®I

ECLinPS and ECLinPS Lite

Dl140-Rev4

5-{37

MILUMETERS
MIN
MAX
980
10.00
4.00
380
1.35
1.75
0.49
035
0.40
1.25
1.27BSC
0.19
025
0.10
025
0°
7°
580
6.20
0.25
0.50

INCHES
MIN
MAX
0.386 0.393
0.150 0157
0.054 0068
0.014 0.019
0.016 0049
O.050BSC
0.008 0.009
0.004 0.009
0°
7°
0.2290.244
0.010 0.019

MOTOROLA

Case Outlines

LSUFFIX
CERAMIC DIP PACKAGE
CASE 620-10
ISSUE V

[±J

-I

[:::::I~

~F1
~~t~
'
~
-"-;! ·
F~~ G~
_qA f\,.J-l JjUl J-l J-l

.--l

o 16PL

JLJ16PL

1-$IO.25(O.010)@ITI8 ®I

1$IO.25(O.010)@ITIA ®I

NOTES:
1, DIMENSIONING AND TOLERANCING PER
ANSI YI4,5M, 1982,
2, CONTROlliNG DIMENSION: INCH.
3, DIMENSION LTO CENTER OF LEAD WHEN
fORMED PARALLEL
4, DIMENSION F MAY NARROW TO 0.76 (0,030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A
B
C
D
E
F
G
H
K
L
M
N

INCHES
MIN
MAX
0.750
0.785
0.240
0295
0.200
0,015
0.020

O.050BSC
0065
O.100BSC
0.008 0.015
0.125
0,170
0.300BSC
15'
0'
0,020 0.040

0.055

MILLIMETERS
MIN
MAX
19.OS 19.93
6.10
7.49
5.08
0.39
0.50
1.27BSC
1,40
1,65
2.54 BSC
0.21
0.38
3,18
4.31
7.62BSC
15'
0'
0.51
1.01

2Q-Pin Packages
OW SUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04
ISSUE E
NOTES:
1, DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
Z CONTRCWNG DIMENSION: MIUJMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION,
4, MAXIMUM MOLD PROTRUSIONO,I50
(0,006) PER SIDE.
5, DIMENSION 0 DOES NOT INCLUDE
DAMBAR PROTRUSION ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF 0 DIMENSION
AT MAXIMUM MATERIAL CONDITION,

~~ .ox 0

DIM
A
B
C
0

1$lo.Ol0(O.25)@ITIA ®I 8®1

G
J
K
M

P
R

MOTOROLA

5-38

MILLIMETERS
MIN
MAX
12.65 12.95
7.40
7.60
2.35
2.65
0.35
0.49
0,90
0.50
1.27BSC
0,32
0.25
0,25
0.10
7'
0'
10,OS 1055
0.25
0.75

INCHES
MIN
MAX
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0019
0.020
0.035
O,05OBSC
0.010
0.012
0.004 0.009
0'
7'
0.395 0.415
0.010 0.029

ECLinPS and ECLinPS Lite
DL140- Rev 4

Case Outlines

FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775-02
ISSUEC

81$1 0.007(0.IBO)@ITI L-M® I N®I

u1$1 0.007(0.IBO)@ITI L-M®I N®I

G11$1 0.010 (0.250)®1 TI L-M® I N®I
VIEW 0-0

I-<----.f-A 1$1 0.007 (O.IBO)@1 TI L-M ® I N® I

i1<----+t--R 1$1 0.007(0.IBO)@ITIL-M®IN®1

~
*

HI$10.007(0.IBO)@ITIL-M®IN®1

t"J I-

1$10.OO7(0.180)@ITIL-M®IN®1

VIEWS

NOTES:
1. DATUMS -L-. -M-. AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION Gl, TAUE POSITION TO BE
MEASURED AT DATUM - T-. SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 10.250)
PER SIDE.
4. DIMENSIONING AND TOLERANC1NG PER ANSI

YI4.SM,1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.01210.300).
DIMENSIONS RAND U ARE DETERMINED ATTHE
OlITERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERlEAD FLASH, BlIT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OFTHE PLASTIC BODY
7. DIMENSION H DOES NOT INCLUDE DAM BAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSIONIS) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.03710.940).
THE DAM BAR INTRUSIONIS) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0635).

ECLinPS and ECLinPS Lite
DL140-Rev4

5-39

DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
Gl
Kl

INCHES
MIN
MAX
0085 0.395
0385 0395
0.165
0180
0090
0.013

0.110

0019
o 050 Bse
0026 0032
0020
0025
0.350
0350

0042
0042
0.042
2°
0310

0.040

0.356
0.356
0048
0.048
0.066
0020
10°
0330

MILIUMETERS
MIN
MAX
9.78 1003
9.78
10.03
4.20
4.57
22.9
2.79
0.33
0.48
1,2785C
0.66
081
0.51
0.84
889
9.04
889
904
1.07
1.21
1.21
1.07
1.07
1.42
0.50
10°
2°
7.88

8.3B

1.02

MOTOROLA

Case Outlines

28-Pin Package
FNSUFFIX
PLASTIC PLCC PACKAGE
CASE 776-02
ISSUE D

BI$I 0.007 (0.180)® I Tll-M® I N®I

YBRK

u 1$1 0.007 (0.180)®1 Tll-M®1 N®I

~
1
'1--_=-_~LL

~t-t

G11$1 0.010(0.250)®ITll-M® I N®I

0
VIEWD-D

i - - - - - - f - - A 1$1 0.OO7(0.180)®ITll-M®1 N®I

~-----I+- RI$10.007(0.180)®ITll-M®1 N®I

rtE~~-----.1

t=:I

VIEWS

1$1 0.010 (0.250)® I Tll-M® I N®I

VIEWS

NOTES:
1. DATUMS -l-. -M-. AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC 80DY AT MOLD PARTING LINE.
2. DIMENSION Gl. TRUE POSITION TO BE
MEASURED AT DATUM -T-. SEATING PLANE.
3. DIMENSIONS RAND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M. 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FlASH, TIE BAR
BURRS. GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BonOM OFTHE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE OAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).

MOTOROLA

I- F 1$10.007(0.180)®ITll-M®1 N®I

5-40

DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
Gl
Kl

INCHES
MIN
MAX
0.485 0.495
0485 0.495
0.165 0.180
0.090
0.110
0.013 0.019

O.050BSC
0,026
0.020
0.025
0.450
0.450

0.042
0.042
042
2°

0.410
0.040

0.032

0.456
0.456

0.048
0.048
0056
0.020
10°
0.430

MILUMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27BSC
0.66
O.Bl
0.51
0.64
11.43 11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
0.50
10°
2°
10.42 10.92
1.02

ECUnPS and ECUnPS Lite

DL140-Rev4

Case Outlines

32-Pin Package
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 873A-Q2
ISSUE A

DETAILY

--I I--

.,r- DETAIL AD
..--.. ~

==- ~

FAB=l ~)--'-

SEATINGI_AC_I

PUNE

lalo.lo(o.o04)IAC

SECTION AE-AE

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLUNG DIMENSION: MILUMETER.
3. DATUM PLANE -All-IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE lEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING UNE.
4. DATUMS-T-.-U-.AND-Z- TO BE DETERMINED
AT DATUM PLANE -AII-.
5. DIMENSIONS SAND VTO BE DETERMINED AT
SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. AlLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOlD MISMATCH AND ARE
DETERMINED AT DATUM PLANE-AII-.
7. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0078(0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.

DIM
A
A1
B
B1
C
D
E
F

DETAIL AD

G
H
J
K
M
N

~ ~
:l!
"'
~ ~
0

p
Q

•

S1
V
V1
W
X

ECLinPS and ECLinPS Lite
DL140-Rev4

5-41

MiLliMETERS
MIN
MAX
7.000BSC
3500BSC
7.000BSC
3500BSC
1.400 1.600
0.300 0.450
1.350 1.450
0.300 .400
0.800BSC
0050 0.150
0.090 0.200
0.500 0.700
12° REF
0.090 0.160
040088C
l'
5'
0.150 0.250
9000BSC
4.S00BSC

9.000BSC
4.5OO88C
0.200 REF
1.000 REF

INCHES
MIN
MAX
O.276BSC
0.138BSC
0.276BSC
0.138BSC
0.055 0.063
0.012
0.Q18
0053 0057
0012 0.016
0.031 BSC
0002 0006
0.004 0.008
0.020 0.028

12° REF
0.004 0.006
0.01688C
I'
5'
0.006 0.010

o35488C
0.17788C
0.35488C

O.1nBSC
0.008 REF

0.039 REF

MOTOROLA

Case Outlines

52-Pin Package
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 848D-03
ISSUEC

VIEWY

PLATING

~
D
--*-

BASEMETAL

tk-D~f
Ifltlo.13(O.005)®ITI L-M®I N®I
SECTION AB-AB
ROTATED 90 CLOCKWISE
0

~
4X82~F, r-o......"...,.,~-::-r::1
~ f ~onaonnnn[Oa~~~\_tr_~~~~
SEATING
PLANE

.-'
VIEWAA

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -If-IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS +. -M- AND -N- TO BE DETERMINED
AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATINGPLANE-T-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
DIM

MILUMETERS

INCHES

A1
B

;OOBSC
10.OIBSC

0.197BSC

1.30
0.20

w
92
93

MOTOROLA

5--42

150
0.40

0.051
OOOB

0.059
016

065 BSC
0.07
0.20

0.026B8
0003
.OOB

12.00IBSC
6.00BSC

o472 BSC

_O.~

VIEWAA

03~'BSC

0.236BSC

tJ~

020REF
1.00 REF

~
0.039 REF

12" REF
5"
13"

12" REF
13"

ECLinPS and ECLinPS Lite

DL140- Rev 4

1M] «ll"ii' (0) IRl «llllA
SEMICONDUCTOR DESIGN GUIDE

SECTION 6
Quality & Reliability
Quality
The Motorola culture is a culture of quality. Throughout all
phases of product development, from defining and designing
to shipping the product, Motorola strives for total customer
satisfaction through "Six Sigma" and "On Time Delivery"
programs.
Defining Products
From the beginning, the goal of the ECLinPS family was to
be "customer" defined. Extensive work was done up front to
identify part types which were perfectly suited to the needs of
our customers. This definition phase ensured a level of
quality for the family in that the customer defines the product
rather than the supplier dictating product types.
Designing Products
Superior quality products start with the design, and the
design of a product starts with an IC process. Extensive work
was done with the MOSAIC III process to ensure a solid
platform for quality products. Process reliability studies were
performed to uncover any weaknesses in the initial process
so that enhancements could be made to strengthen it before
it was released to production. In addition, comprehensive
characterization and correlation work was completed on the
process to ensure the utmost in modeling parameter
accuracy.
The design of the products strictly adhered to the design
rules set forth by the process designers. Conservative,
manufacturable layout rules were followed to minimize the
performance variability due to a marginally manufacturable
product. In addition, the use of statistical modeling methods,
such as factorial and response surface techniques, in the
designing of the IC's leads to products with a reduced
sensitivity to variations in the manufacturing process.
Manufacturing Process
Through SPC and continual engineering work, the
manufacture of the MOSAIC III process is both monitored
and enhanced on a continuous basis. Statistical data is
gathered at both probe and final test through the device data
collection to monitor the distribution of a parameter to its
specification limits. In addition, final quality assurance gates
are set up to guarantee the quality of outgoing product.
Product Characterization
Products are both DC and AC characterized for all data
book environmental conditions prior to the release of the
product to production. The distributions of the parameters are

ECLinPS and ECLinPS Lite
DL140- Rev 4

compared to their specification limits to ensure that Motorola
"manufactures" quality products as opposed to 'testing"
quality products through distribution truncation. In addition,
ongoing AC characterization is performed to enhance the
distributions of the AC parameters of the device. In doing so,
as the distributions warrant, further enhancements to the AC
specifications can be achieved.

Reliability
To ensure the long term reliability of ECLinPS products,
extensive accelerated life testing is performed prior to
production release. This qualification work is performed by
Logic Reliability Engineering, an organization specifically
dedicated to monitoring and guaranteeing the quality and and
reliability of logic products. The accelerated life test consists
of the following:
Operating Life Test: 145°C Mil. Std. 883
Temperature Cycle: -65°C to 150°C Mil. Std. 883
Pressure, Temperature, Humidity (Hermeticity)
A minimum of two lots, 250 die per lot taken from three
different waters in the lot constitute a qualification sample.
Various intermediate readouts are taken to monitor the
performance more closely. In addition, the devices are tested
beyond the specification limits to determine where and how
they will fail.
Another responsibility of the reliability group is that of
failure analysis. This failure analysis service is supported for
both internal purposes and for servicing the needs of our
customers. Analysis entails everything from simple package
examination to internal microprobing to SEM analysis of IC
structures. The results of the analysis are returned to the
customer and if the analysis suggests a potential problem
with the device the information is also passed to the internal
product groups.
RAP: Reliability Audit Program
The Reliability Audit Program (RAP) devised in March
1977 is the Motorola internal reliability audit which is
designed to assess outgoing product performance under
accelerated stress conditions. Logic Reliability Engineering
has overall responsibility for RAP, including updating its
reqUirements, interpreting its results, administration at
offshore locations and monthly reporting of results. These
reports are available at all sales offices. Also available is the
"Reliability and Quality Handbook" which contains data for all
Motorola semiconductors (BRSI8/D).

5-43

MOTOROLA

Quality & Reliability
Rap is a system of environmental and electrical tests
performed periodically on randomly selected samples of
standard products. Each sample receives the tests specified

in Figure 6.1. Frequency of testing is specified per internal
document 12MRM15301A.

45-116PCS'

PTHB
48HRS

PTH
96HRS

INITIAL SEAL'"

I
I

PTH
ADD48HRS

ELECTRICAL
TEST

OPLlFE....
40 HOURS

THERMAL SHOCK
100 CYCLES

SEALIt...
ELECTRICAL
TEST

I
INITIAL SEAL'"

TEMP CYCLE
100 CYCLES

ELECTRICAL
TEST

76-116PCS

116-328 PCS"

SEAL'"

ELECTRICAL
TEST

THERMAL SHOCK
ADD 900 CYCLES

OPLIFE
ADD 210 HRS.

ELIECTRICAL
TEST

ELECTRICAL
TEST

I
OPLlFE·....
ADD750HRS.

TEMP CYCLE
ADD 1000 CYCLES

ELECTRICAL
TEST

I
SCRAP

Figure 6.1. Reliability Audit Program Test Flow
PTH will be run as a substitute if PTHB sockets are not
available. Only required on plastiCS packages.
Thermal Shock will be run if Temp Cycle is not available.
Seal (fine and gross) only required on hermetic
packages.
All units for Op Life to be AC/DC tested before and after
being stressed. All units failing AC after stress will be
analyzed.

PTHB
15psig/121°C/l00% RH at rated VCC or VEE - to be
performed on plastiC encapsulated devices only.
Temp Cycle
Mil. Std. 883, Method 1010, Condition C, - 65°C to 150°C

Op Life
Mil. Std. 883, Method 1005, Condition C (Power plus
Reverse Bias), TA = 145°C.

One sample per month

Notes:
I. All standard 25°C DC and functional parameters will be measured GoINoGo at each readout.
2. Any indicated failure is first verified and then submitted to the Product Analysis Lab for detailed analysis.
3. Sampling to include all package types routinely.
4. Device types sampled will be by generic type within each digitallC product family (MECL, TIL, etc.) and will include all assembly locations
(Korea, Phillipines, Malaysia, etc.).
5. 16 hrs. PTHB is equivalent to = 800 hrs. of 85°C/85% RH THB for VCC" 15V.
6. Only moisture related failures (like corrosion) are criteria for failure on PTHB test.
7. Special device specifications (48A's) for digital products will reference 12MRMI5301 A as a source of generic data for any customer requiring
monthly audit reports.

MOTOROLA

5-44

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1404
Application Note

ECLinPSTM Circuit Performance
at Non-Standard VIH Levels

Prepared by

Todd Pearson
Eel Applications Engineering

This application note explains the consequences of
driving an ECLinPS device with an input voltage HIGH
level (VIH) which does not meet the maximum voltage
specified in the ECLinPS Databook.

ECLinPS is a trademark of Motorola, Inc.

5192

5-45

REV 0

MOTOROLA

AN1404

ECLinPS Circuit Performance at Non-Standard VIH Levels
Introduction

collector-base forward bias to enter the saturation region.

When interfacing ECLinPS devices to various other
technologies times arise where the the input voltages do not
meet the specification limits outlined in the ECLinPS data
book. The purpose of this document is to explain the
consequences of driving an ECLinPS device with an input
voltage HIGH level (VIH) which does not meet the maximum
voltage specified in the ECLinPS Databook.
The results outlined in this document should not be viewed
as guarantees by Motorola but rather as representative
information from which the reader can base design decisions.
It is up to the reader to assess the risks of implementing the
non-standard interface and deciding if that level of risk is
acceptable for the system design. Motorola's guarantee on
VIH will continue to be the specification standards established
for the 10WM and 100K ECl technologies.
Overview
The upper end olthe VIH spec of an ECLinPS, or any other
ECl, input is limited by saturation affects of the input
transistor. Figure 1 below illustrates a typical ECl input
(excluding pulldown resistors and ESD structures); the
structure is a basic differential amplifier configuration. With a
logic HIGH level asserted at the input the collector of that
transistor will be pulled down below the VCC rail by the gate
current passing through the collector load resistor. The
voltage at the collector of the input transistor (VC) will be
dependent on the gate current and the size of the collector
load resistor associated with the input gate.

VBB

Figure 1. Typical ECLlnPS Input Structure
As the input VIH increases towards VCC the collector base
junction of the input transistor becomes forward biased; as this
forward bias condition increases the transistor will move into
the saturation region. The value of VCB at which the transistor
begins to saturate is process dependent and will vary from
logic family to logic family. Fortunately the MOSAIC'" process
used to implement the ECLinPS family incorporates a deep n+
collector doping. This deep collector helps to mitigate the
effects of saturation of transistors by requiring a larger

MOTOROLA

VIHmax and .the ECLinPS Family
As previously mentioned the MOSAIC lifT" process allows
for ECLinPS devices to operate at VIHmax levels somewhat
higher than those specified in the databook, however the
exact value of VIH for which saturation problems will occur
varies from device to device and even among different inputs
for a given device. This variation is a result of the different input
configurations used on the various inputs of ECLinPS
devices.
The easiest way to define an acceptable VIHmax for each
device in the family is to define at what pointthe input transistor
will saturate and specify for each input what the worst case
input transistor collector voltage will be. With this information
designers will be able to determine on a part by part, input by
input basis what input voltage levels will be acceptable fortheir
application.
Simulation Results
The input saturation phenomenon was characterized
through SPICE simulations and the results will be reported in
the following text. For simplicity of simulation a buffer similar to
the E122 was used. Since the outputs of this buffer drive off
chip, the VIHmax performance of this structure will be worse
than the typical input structure. Both a 100K and a 10H style
buffer were analyzed to note any discrepancies between the
two standards. As expected the simulation results showed no
difference in the saturation susceptibility of a 100K versus a
10H style buffer. Therefore the simulation results of only the
1OOK style buffer will be presented to minimize redundancy of
information.
The following text will refer to Figures 4-8 in the appendix of
this document. Figures 4-8 are graphical plots of the input and
output waveforms of an E122 style buffer (structure similar to
that of Figure 1) for various VIH levels. V(in) represents the
input voltage while V(q) and V(qb) represent the output
voltages. The V(vbb) line was included for measurement
purposes only and will be ignored.
Figure 4 represents the "standard" operation of the device
as a standard VIH input was used. Note that in this condition
the propagation delays measure in the 215-225ps range and
the IINH was 42.5I1A. The IINH of this device is simply a
measure of the base current of the input transistor when that
transistor is conducting current. We will be monitoring both of
these conditions as well as any degradation in the output
waveforms as a sign of the input transistor becoming
saturated. As can be seen in Figures 5 and 6 none of the
parameters change for VIH levels of up to -D.4V. With a
collector voltage, VC, of -1.0V these VIH'S correspond to a
collector base forward bias of 600mV. As the VIH of the input
moves closer to VCC, Figures 7 and 8, three phenomena start
to occur: the IINH increases, the delays increase and
significant changes occur to the output low level of the OB pin.

5-46

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1404
In Figure 7 the IINH of the input transistor has more than
doubled from the "standard" level. This increase in base
current leads to an increase in the VOL level as the collector
current must reduce to maintain the constant emitter current.
As the collector current reduces, the IR drop across the
collector load resistor reduces, thus raiSing the VOL level on
the OB output. Although the VOL level has shifted the overall
propagation delay has remained essentially unchanged.
Finally, when the input is switched all the way up to VCC the
VOL level no longer remains in spec as the input base current
has jumped to almost 1ma and there has been significant
degradation in the high-low propagation delay. It is apparent
that for this condition an E122 style buffer will not perform
adequately for most systems.

input voltages are dropped by an additional VBE (~800mV)
before they are fed into the differential amplifier input gate. The
switching reference is also shifted down by one diode drop to
remain centered in the input swing. Obviously this input
structure will represent the "best case" in the area of extended
VIHmax performance. In fact this type of input structure will
allow for input voltages even several hundred millivolts above
the VCC rail. This characteristic makes these type devices
ideal for interfacing with differential oscillators whose outputs
lack any DC offset. In the emitter follower structure the limiting
factor will be the saturation of the emitter follower device
whose collector is at VCC. From the previous simulation
results this would suggest a maximum VIH of +O.6V.
VCC

From this information it can be concluded th'at for a
collector-base forward bias of ,;;600mV there will be no
adverse conditions on the performance of the device. The
performance starts to degrade with further forward bias until at
a forward bias voltage of ~1.0V the device will fail both its DC
and AC specifications.

VBB

ECLinPS Input Structures
There are four basic input structures which will affect the
VIHmax performance of ECLinPS devices. The four structures
are as follows: an internal buffer, an external buffer, an emitter
follower input buffer and a series gated emitter follower input.
The internal buffers are input structures whose outputs
drive other gates internal to the device, the voltage swings of
the input transistor collectors (VC) on these devices will be
~800mV. An external buffer is one in which the outputs are fed
external to the chip, Because of the relatively large base drive
of the output emitter follower for these structures the Vc
voltage will typically be a couple hundred milivolts lower than
for the internal buffer. Note that because of the larger output
swings of a 1OE device, a 1OE style external buffer will require
a VIHmax input level more near the specified value. Both of
these structures are similar to that pictured in Figure 1.
The third and fourth structures are somewhat different in
design than the first two. Figure 2 illustrates an emitter
follower input structure. For the basic emitter follower input the

Figure 2. Emitter Follower Input Structure
The series gate emitter follower input will represent the
absolute worst case situation for a 100E device. Figure 3
represents a series gate emitter follower input for a 1OE and a
100E device. From this figure it is apparent that the lower
switching level (B input level) is going to be much more
susceptible to VIHmax for the 100E device than the 10E
device. The two diode drops used for the 10E device is not
possible for a 1OOE device due to the smaller VEE voltage of a
100E device.
To summarize the external gate will represent the worst
case VIHmax situation for a 10E device while the series gate
emitter follower case will represent worst case for a 100E
device. In either situation the standard emitter follower will
allow the most leeway for non·standard VIHmax performance.

100E Structure _ ....__V"'C"'C'-----
-1.5

V(Q8)

- - - V(V88)

V/
/

-1.0
w

- - - - V(Q)

\\\

/~-

--;T------- ----~'t----V---- / \ " ---- --- II~

'----

-1.75

-2.0

-2.25

---

"'-----

4000

2000
TIME

Figure 4. Input and Output Waveforms for VIH = -0.9
(VOL = -1.8; TpO++ = 215ps; TpO-- = 225ps; IINH = 42.5j.i.A)

-{l.0
- - - V(IN)

-{l.25

I---

- - - - V(Q)
-

-{l.5

-{l.75

[5J

'"~

-1.0

-1.5

-1.75

-2.0

V(Q8)

\\
Y
--~(----------- r-----\1------I

-1.25

- - - V(V88)

--"'

/
/

I--

"- ---------1 - -

r---

/\\,
----

----

4000

2000
TIME

Figure 5_ Input and Output Waveforms for VIH = -0.5
(VOL -1.8; TpO++ 204ps; Tpo- - 207ps; IINH 43.4j.i.A)

MOTOROLA

5-50

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1404
-0.0

---V(IN)
-0.25

- - - - V(O)

-0.5

Y/ / //

C!l

-1.0

~
-1.25

-1.5

-1.75

-2.0

\
_\
\\

-0.75

r-~(------------

\.
.......

-_/

V(OB)

/"'"

__ I '\\" ----- ----

-_.

_---

- - - V(VBB)

--------\1----- - - -

....

2000

4000

TIME

Figure 6_ Input and Output Waveforms for VIH -0_4
(VOL = -1.8; TpD++ = 201ps; TPD-- = 206ps; IINH = 46.7!!A)

-0.0

---V(IN)
-0.25

-0.5

-0.75

X/ /

C!l

~
0

-1.0

-1.25

-1.5

-1.75

-2.0

/
/~

J/
_
......

------- ( - - - - ......

--~~----------

V(OB)

- - - V(VBB)

\
'\\

/'
I

I--

---

I-- - - - - - - - \ \ / - - - - - -

I--

- - - - V(O)

" "- )

----

'v"

2000

4000

TIME

Figure 7_ Input and Output Waveforms for VIH = -0.3
(VOL = -1.8; TPD++ = 196ps; TPo-- = 198ps; IINH = 114.8!!A)

ECLinPS and ECLinPS Lite
DL140-Rev4

5-51

MOTOROLA

AN1404
-0.0

-0.5

-0.75

(!)

:...J

-1.0

g
-1.25

-1.5

-1.75

-2.0

-0.25

./'-

- - - V(IN)

\
\

- - - - V(O)
-

r--

V(OB)

- - - V(VBB)

f--

-------- ----, \

I
Y/
'\''--_.
\'"
-t--- - - r-/ y:--------\
U/' \..,r----- - \ \ ~(
---/'

f---/

2000

----

/
4000

TIME

Figure 8. Input and Output Waveforms for VIH
(VOL -1.8; TPD++ 196ps; TpD- - 287ps; IINH

MOTOROLA

5-52

= 0.0

=912J.lA)

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1405
Application Note

ECL Clock Distribution
Techniques
Prepared by

Todd Pearson
Eel Applications Engineering

This application note provides information on system
design using ECL logic technologies for reducing
system clock skew over the alternative CMOS and TTL
technologies.

7196

5-53

REV 1

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AN1405

ECl Clock Distribution Techniques
INTRODUCTION
The ever increasing performance requirements of today's
systems has placed an even greater emphasis on the design
of low skew clock generation and distribution networks. Clock
skew, the difference in time between "simultaneous" clock
transitions within a system, is a major component of the
constraints which form the upper bound for the system clock
frequency. Reductions in system clock skew allow designers
to increase the performance of their designs without having to
resort to more complicated architectures or more costly, faster
logic. ECl logic technologies offer a number of advantages for
reducing system clock skew over the alternative CMOS and
TTL technologies.

output-to-output skew will be smaller than the duty cycle skew
for TTL and CMOS devices. Because of the near zero duty
cycle skew of a differential ECl device the output-to-output
skew will generally be larger. The output-to-output skew is
important in systems where either a single device can provide
all of the necessary clocks or for the first level device of a
nested clock distribution tree. In these two situations the only
parameter of importance will be the relative position of each
output with respect to the other outputs on that die. Since
these outputs will all see the same environmental and process
conditions the skew will be significantly less than the
propagation delay windows specified in the standard device
data sheet.

IN--...J/

SKEW DEFINITIONS
The skew introduced by logic devices can be divided into
three parts: duty cycle skew, output-to-output skew and
part-to-part skew. Depending on the specific application, each
of the three components can be of equal or overriding
importance.

OUTa

OUTb
OUTc

1--'-Duty Cycle Skew
The duty cycle skew is a measure of the difference between
the TPlH and TpHl propagation delays (Figure 1). Because
differences in TplH and TpHl will result in pulse width
distortion the duty cycle skew is sometimes referred to as
pulse skew. Duty cycle skew is important in applications
where timing operations occur on both edges or when the duty
cycle of the clock signal is critical. The later is a common
requirement when driving the clock inputs of advanced
microprocessors.

Figure 1. Duty Cycle Skew
Output-to-Output Skew
Output-to-output skew is defined as the difference between
the propagation delays of all the outputs of a device. A key
constraint on this measurement is the requirement that the
output transitions are identical, therefore if the skew between
all edges produced by a device is important the
output-to-output skew would need to be added to the duty
cycle skew to get the total system skew. Typically the

MOTOROLA

r-r-

OUTPUT-TO-OUTP UTSKEW

Figure 2. Output-to-Output Skew
Part-to-Part Skew
The part-to-part skew specification is by far the most difficult
performance aspect of a device to minimize. Because the
part-to-part skew is dependent on both process variations and
variations in the environment the resultant specification is
significantly larger than forthe other two components of skew.
Many times a vendor will provide subsets of part-to-part skew
specifications based on non-varying environmental
conditions. Care should be taken in reading data sheets to
fully understand the conditions under which the specified
limits are guaranteed. If the part-to-part skew is specified and
is different than the specified propagation delay windowforthe
device one can be assured there are constraints on the
part-to-part skew specification.
Power supply and temperature variations are major
contributors to variations in propagation delays of silicon
devices. Constraints on these two parameters are commonly
seen in part-to-part skew specifications_ Although there are
situations where the power supply variations could be ignored,
it is difficult for this author to perceive of a realistic system
whose devices are all under identical thermal conditions. Hot
spots on boards or cabinets, interruption in air flow and
variations in IC density of a board all lead to thermal gradients
within a system. These thermal gradients will guarantee that
devices in various parts of the system are under different
junction temperature conditions. Although it is unlikely that a

5--54

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DL140- Rev 4

AN1405
designer will need the entire commercial temperature range, a
portion of this range will need to be considered. Therefore, a
part-to-part skew specified for a single temperature is of little
use, especially if the temperature coefficient of the
propagation delay is relatively large.
For designs whose clock distribution networks lie on a
Single board which utilizes power and ground planes an
assumption of non-varying power supplies would be a valid
assumption and a specification limit for a single power supply
would be valuable. If, however, various pieces of the total
distribution tree will be on different boards within a system
there is a very real possibility that each device will see different
power supply levels. In this case a specification limit for a fixed
VCC will be inadequateforthedesign of the system. Ideally the
data sheets for clock distribution devices should include
information which will allow designers to tailor the skew
specifications of the device to their application environment.
SYSTEM ADVANTAGES OF ECl
Sitew Reductions
ECl devices provide superior performance in all three
areas of skew over their TTL or CMOS competitors. A skew
reducing mechanism common to all skew parameters is the
faster propagation delays of ECl devices. Since, to some
extent, all skew represent a percentage of the typical delays
faster delays will usually mean smaller skews. ECl devices,
especially clock distribution devices, can be operated in either
single-ended or differential modes. To minimize the skew of
these devices the differential mode of operation should be
used, however even in the single-ended mode the skew
performance will be significantly better than for CMOS or
TTL drivers.
VSBnom

OUT_ _ _----'I'-'J
- - - - - DELAYlo
- - - - DELAYnom

inherent differences between the TplH and TpHl delays in
addition to the problems with non-centered switching
thresholds. In devices specifically designed to minimize this
parameter it generally cannot be guaranteed to anything less
than 1ns.
The major contributors to output-to-output skew is IC layout
and package choice. Differences in internal paths and paths
through the package generally can be minimized regardless of
the silicon technology utilized at the die level, therefore ECl
devices offer less of an advantage in this area than for other
skew parameters. CMOS and TTL output performance is tied
closely to the power supply levels and the stability of the power
busses within the chip. Clock distribution trees by definition
always switch simultaneously, thus creating significant
disturbances on the internal power busses. To alleviate this
problem multiple power and ground pins are utilized on TTL
and CMOS clock distribution devices. However even with this
strategy TTL and CMOS clock distribution devices are limited
to SOOps - 700ps output-to-output skew guarantees. With
differential ECl outputs very little if any noise is generated and
coupled onto the internal power supplies. This coupled with
the faster propagation delays of the output buffers produces
output-to-output skews on ECl clock chips as low as SOps.
Two aspects of ECl clock devices will lead to significantly
smaller part-to-part skews than their CMOS and TTL
competitors: faster propagation delays and delay insensitivity
to environmental variations. Variations in propagation delays
with process are typically going to be based on a percentage
of the typical delay of the device. Assuming this percentage is
going to be approximately equivalent between ECl, TTL and
CMOS processes, the faster the device the smaller the delay
variations. Because state-of-the-art ECl devices are atleastS
times faster than TTL and CMOS devices, the expected delay
variation would be one fifth those of CMOS and TTL devices
without even considering environmental dependencies.
The propagation delays of an ECl device are insensitive to
variations in power supply while CMOS and TTL device
propagation delays vary significantly with changes in this
parameter. Across temperature the percentage variation for
all technologies is comparable, however, again the faster
propagation delays of ECl will reduce the magnitude of the
variation. Figure 4 on the following page represents
normalized propagation delay versus temperature and power
supply for the three technologies.

Figure 3. VBB Induced Duty Cycle Skew
ECl output buffers inherently show very little difference
between TPlH and TPHl delays. What differences one does
see are due mainly to switching reference levels which are not
ideally centered in the input swing (see Figure 3). For worst
case switching reference levels the pulse skew of an ECl
device will still be less than 300ps. If the ECl device is used
differentially the variation in the switching reference will not
impact the duty cycle skew as it is not used. In this case the
pulse skew will be less than SOps and can generally be ignored
in all but the highest performance designs. The problem of
generating clocks which are capable of meeting the duty cycle
requirements of the most advanced microprocessors, would
be a trivial task if differential ECl compatible clock inputs were
used. TTL and CMOS clock drivers on the other hand have

ECLinPS and ECLinPS Lite
DLt40-Rev4

low Impedance line Driving
The clock requirements of today's systems necessitate an
almost exclusive use of controlled impedance interconnect. In
the past this requirement was unique to the performance
levels associated with ECl technologies, and in fact
precluded its use in all but the highest performance systems.
However the high performance CMOS and TTL clock
distribution chips now require care in the design and layout of
PC boards to optimize their performance, with this criteria
established the migration from these technologies to ECl is
simplified. In fact, the difficulties involved in designing with
these "slower" technologies in a controlled impedance
environment may even enhance the potential of using ECl
devices as they are ideally suited to the task.

5-55

MOTOROLA

AN1405
1.20

1.05
1.04
is'
w
N

is'
w

1.03

~
c(

::J
c(

:;
0:
0

§'w

1.02

1.01
1.00

ECl

1.10

0.99

'"cE
0

0.98

'"~

a:
a.

1.15

0.97

1.05

a:
a.

0.96
0.95
0.94

0.98

1.02

1.06

1.10

100

TEMPERATURE (Cl)

POWER SUPPLY (NORMALIZED)

Figure 4. TPD vs Environmental Condition Comparison
The low impedance outputs and high impedance inputs of
an ECl device are ideal for driving 50n to 130n controlled
impedance transmission lines. The specified driving
impedance of ECl is 50n, however this value is used only for
convenience sake due to the 50n impedance of most
commonly used measurement equipment. Utilizing higher
impedance lines will reduce the power dissipated by the
termination resistors and thus should be considered in power
sensitive designs. The major drawback of higher impedance
lines (delays more dependent on capacitive loading) may not
be an issue in the poinlto point interconnect scheme generally
used in low skew clock distribution designs.

1800 shifted two phase clocks.
It is true that differential interconnect requires more signals
to be routed on the PC board. Fortunately with the wide data
and address buses of today's designs the clock lines
represent a small fraction of the total interconnect. The final
choice as to whether or not to use differential interconnect lies
in the level of skew performance necessary for the design. It
should be noted that although single-ended ECl provides less
attractive skew performance than differential ECl, it does
provide significantly better performance than equivalent
CMOS and TTL functions.

Differential.lnterconnect
The device skew minimization aspects of differential ECl
have already been discussed however there are other system
level advantages that should be mentioned. Whenever clock
lines are distributed over long distances the losses in the line
and the variations in power supply upset the ideal relationship
between input voltages and switching thresholds. Because
differential interconnect "carries"the switching threshold
information from the source to the load the relationship
between the two is less likely to be changed. In addition for
long lines the smaller swings of an ECl device produce much
lower levels of cross-talk between adjacent lines and
minimizes EMI radiation from the PC board.
There is a cost associated with fully differential ECl, more
pins for equivalent functions and more interconnect to be laid
on a typically already crowded PC board. The first issue is
really a non-issue for clock distribution devices. The
output-to-output and duty cycle skew are very much
dependent on quiet internal power supplies. Therefore the
pins sacrificed for the complimentary outputs would otherwise
have to be used as power supply pins, thus functionality is
actually gained for an equivalent pin count as the inversion
function is also available on a differential device. The
presence of the inverted signal could be invaluable for a
design which clocks both off the positive and negative edges.
Figure 5 shows a method of obtaining very low skew «50ps)

MOTOROLA

ClKa
ClKb

Figure 5.180 0 Shifted Two Phase Clocks
USING ECl WITH POSITIVE SUPPLIES
It is hard to argue with the clock distribution advantages of
ECl presented thus far, but it may be argued that except for all
ECl designs it is too costly to include ECl devices in the
distribution tree. This claim is based on the assumption that at
least two extra power supplies are required; the negative VEE
supply and the negative VTT termination voltage. Fortunately
both these assumptions are false. PECl (Positive ECl) is an
acronym which describes using ECl devices with a positive

5-56

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1405
rather than negative power supply. It is important to
understand that all ECl devices are also PECl devices. By
using ECl devices as PECl devices on a +5 volt supply and
incorporating termination techniques which do not require a
separate termination voltage (series termination, thevenin
equivalent) ECl can be incorporated in a CMOS or TIL
design with no added cost.
The reason for the choice of negative power supplies as
standard for ECl is due to the fact that all of the output levels
and internal switching bias levels are referenced to the VCC
rail. It is generally easier to keep the grounds quieter and equal
potential throughout a system than it is with a power supply.
Because the DC parameters are referenced tothe VCC rail any
disturbances or voltage drops seen on VCC will translate 1:1 to
the output and internal reference levels. For this reason when
communicating with PECl between two boards it is
recommended that only differential interconnect be used. By
using differential interconnect VCC variations within the
specified range will not in any way affect the performance of
the device.

synchronous registered enables will disable the device only
when the clock is already in the lOW state, thus avoiding the
problem of generating runt pulses when an asynchronous
disable is used. The device also provides a muxed clock input
for incorporating a high speed system clock and a lower speed
test or scan clock within the same distribution tree. The
ECLinPS E111 device is used to receive the signals from the
backplane and distribute it on the card. The worst case skew
between all 54 clocks in this situation would be 275ps
assuming that all the loads and signal traces are equalized.

Finally mentioning ECl to a CMOS designer invariably
conjures up visions of space heaters as their perception of
ECl is high power. Although it is true that the static power of
ECl is higher than for CMOS the dynamic power differences
between the technologies narrows as the frequency
increases. As can be seen in Figure 6 at frequencies as low as
20MHz the per gate power of ECl is actually less than for
CMOS. Since clock distribution devices are never static it
does not make sense to compare the power dissipation of the
two technologies in a static environment.

Figure 7. ECl Clock Distribution Tree

Mixed Technology Distribution Networks
20r-------------------------~

CMOS

"'.s..5?
0

ECl

100

FREQUENCY (MHz)

Figure 6. ICC/Gate vs Frequency Comparison

MIXED SIGNAL CLOCK DISTRIBUTION

ECl Clock Distribution Networks
Clock distribution in a ECl system is a relatively trivial
matter. Figure 7 illustrates a two level clock distribution tree
which produces nine differential ECl clocks on six different
cards. The ECLinPS E211 device gives the flexibility of
disabling each of the cards individually. In addition the

ECLinPS and ECLinPS Lite
DL140- Rev 4

Building clock networks in TIL and CMOS systems can be
a little more complicated as there are more alternatives
available. For simple one level distribution trees fanout
devices like the MECl 1OH6451:9 TIL to TIL fanout tree can
be used. However as the number of levels of fanout increases
the addition of ECl devices in an other wise TIL or CMOS
system becomes attractive. In Figure 8 on the next page an
E111 device is combined with a MECl H641 device to produce
81 TIL level clocks. Analyzing the skew between the 81
clocks yields a worst case skew, allowing for the full
temperature and VCC range variation, of 1.25ns. Under ideal
situations, no variation in temperature orVcc supply, the skew
would be only 750ps. When compared with distribution trees
utilizing only TIL or CMOS technologies these numbers
represent ~50% improvement, more if the environmental
conditions vary to any degree. For a 50MHz clock the total
skew between the 81 TIL clocks is less than 6.5% of the clock
period, thus providing the designer extra margin for layout
induced skew to meet the overall skew budget of the design.
Many designers have already realized the benefits of ECl
clock distribution trees and thus are implementing them in
their designs. Furthermore where they have the capability, i.e.
ASICs, they are building their VlSI circuits with ECl
compatible clock inputs. Unfortunately other standard VlSI
circuits such as microprocessors, microprocessor support
chips and memory still cling to TIL or CMOS clock inputs. As a
result many systems need both ECl and TIL clocks within the
same system. Unlike the situation outlined in Figure 8 the ECl
levels are not merely intermediate signals but rather are

5-57

MOTOROLA

AN1405
driving the clock inputs of the logic. As a result the ECl edges
need to be matched with the TIL edges as pictured in Figure 9.

used. The value of the delay element would be a best guess
estimate of the differences in the two propagation delays. It is
highly unlikely that the temperature coefficients of the
propagation delays of the ECl devices, TTL devices and
delay devices would be equal. Although these problems will
add skew to the system, the resultant total skew of the
distribution network will be less than if no ECl chips
were used.

Pll Based Clock Drivers
A potential solution for the problem outlined in Figure 9 is in
the use of phase locked loop based clock distribution chips.
Because these devices feedback an output and lock it to a
reference clock input the delay differences between the
various technology output buffers will be eliminated. One
might believe that with all of the euphoria surrounding the
performance of Pll based clock distribution devices that the
need for any ECl in the distribution tree will be eliminated.
However when analyzed further the opposite appears to be
the case.
Figure 8. ECl to TTL Clock Distribution

eml
,--_..... 1

IL ______ ..J

Figure 9. Mixed ECl and TTL Distribution
An ECl clock driver will be significantly faster than a TIL or
CMOS equivalent function. Therefore to de-skew the ECl and
TIL signals of Figure 9 a delay needs to be added to the input
of the ECl device. Because a dynamic delay adjust would not
lend itself to most production machines a static delay would be

MOTOROLA

For a single board design with a one level distribution
system there obviously is no need for ECL. When, however, a
multiple board system is required where nested levels of
devices are needed ECl once again becomes useful. One
major aspect of part-to-part skew for Pll based clock chips
often overlooked is the dependence on the skew of the various
reference clocks being locked to. As can be seen in Figure 10
the specified part-to-part skew of the device would necessarily
need to be added to the reference clock skew to getthe overall
skew of the clock tree. From the arguments presented earlier
this skew will be minimized if the reference clock is distributed
in ECL. It has not been shown as of yet where a Pll based
ECl clock distribution chip can provide the skew performance
of the simple fanout buffer. From a system standpoint the
buffer type circuits are much easier to design with and thus
given equivalent performance would represent the best
alternative. The extra features provided by Pll based chips
could all be realized if they were used in only the final stage of
the distribution tree.
The MPC973 is a Pll based clock driver which features
differential PECl reference clock inputs. When combined with
the very low skew MC10E111 fanout buffer, very low skew
clock trees can be realized for multiprocessor MPP designs.
There will be a family of devices featuring various technology
compatible inputs and outputs to allow for the building of
precisely aligned clock trees based on either ECl, TIL,
CMOS or differential GTl (or a mixture of all four)
compatible levels.

5-58

ECLinPS and ECLinPS Lite
DL140- Rev 4

AN1405
Conclusion

REFb - - - - - - '

c::J DEVICE SKEW

'--------'I

~ SYSTEM SKEW

Figure 10. System Skew For PLL Clock Distribution

ECLinPS and ECLinPS Lite
DL140- Rev 4

The best way to maximize the performance of any
synchronous system is to spend the entire clock period
performing value added operations. Obviously any portion of
the clock period spent idle due to clock skew limits the
potential performance of the system. Using Eel technology
devices in clock distribution networks will minimize all aspects
of skew and thus maximize the performance of a system.
Unfortunately the VlSI world is not yet Eel clock based so
that the benefits of a totally Eel based distribution tree cannot
be realized for many systems. However there are methods of
incorporating Eel into the intermediate levels of the tree to
significantly reduce the overall skew. In addition the system
designers can utilize their new found knowledge to
incorporate Eel compatible clocks on those VlSI chips of
which they have control while at the same time pressuring
other VlSI vendors in doing the same so that future designs
can enjoy fully the advantages of distributing clocks with EeL.

5-59

MOTOROLA

AN1406
Application Note

Designing With PECL
(ECL at +S.OV)

Prepared by
Cleon Petty
Todd Pearson

Eel Applications Engineering
This application note provides detailed information on
designing with Positive Emitter Coupled Logic (PECL)
devices.

9192

5-60

REVO

MOTOROLA

AN1406

Designing With PECl (ECl at +S.OV)
The High Speed Solution for the CMOSmL Designer

Introduction

for translating between technologies, a significant portion of
the logic would need to be realized using ECL for the overall
system performance to improve. However, for very high speed
subsystem requirements ECL may very well provide the best
system solution.

PECL, or Positive Emitter Coupled Logic, is nothing more
than standard ECL devices run off of a positive power supply.
Because ECL, and therefore PECL, has long been the "black
magic" of the logic world many misconceptions and
falsehoods have arisen concerning its use. However, many
system problems which are difficult to address with TTL or
CMOS technologies are ideally suited to the strengths of ECL.
By breaking through the wall of misinformation concerning the
use of ECL, the TTL and CMOS designers can arm
themselves with a powerful weapon to attack the most difficult
of high speed problems.

Transmission Line Driving
Many of the inherentfeatures of an ECL device make it ideal
for driving long, controlled impedance lines. The low
impedance of the open emitter outputs and high input
impedance of any standard ECL device make it ideally suited
for driving controlled impedance lines. Although designed to
drive 50n lines an ECL device is equally adept at driving lines
of impedances of up to 130n without significant changes in the
AC characteristics of the device. Although some of the newer
CMOSnTL families have the ability to drive 50n lines many
require special driver circuits to supply the necessary currents
to drive low impedance transmission interconnect. In addition
the large output swings and relatively fast output slew rates of
today's high performance CMOSnTL devices exacerbate the
problems of crosstalk and EMI radiation. The problems of
crosstalk and EMI radiation, along with common mode noise
and signal amplitude losses, can be alleviated to a great
degree with the use of differential interconnect. Because of
their architectures, neither CMOS nor TTL devices are
capable of differential communication. The differential
amplifier input structure and complimentary outputs of ECL
devices make them perfectly suited for differential
applications. As a result, for systems requiring signal
transmission between several boards, across relatively large
distances, ECL devices provide the CMOSnTL designer a
means of ensuring reliable transmission while minimizing EMI
radiation and crosstalk.

It has long been accepted that ECL devices provide the
ultimate in logic speed; it is equally well known that the price
for this speed is a greater need for attention to detail in the
design and layout of the system PC boards. Because this
requirement stems only from the speed performance aspect of
ECL devices, as the speed performance of any logic
technology increases these same requirements will hold. As
can be seen in Table 1 the current state-of-the-art TTL and
CMOS logic families have attained performance levels which
require controlled impedance interconnect for even relatively
short distances between source and load. As a result system
designers who are using state-of-the-art TTL or CMOS logic
are already forced to deal with the special requirements of
high speed logic; thus it is a relatively small step to extend their
thinking from a TTL and CMOS bias to include ECL devices
where their special characteristics will simplify the design
task.
Table 1. Relative Logic Speeds
Logic
Family

Typical Output
Rise/Fall

Maximum Open Line
Length (L max)'

10KH

1.0ns

ECLinPS

400ps

FAST

2.0ns

1.5ns

FACT

Figure 1 shows a typical application in which the long line
driving, high bandwidth capabilities of ECL can be utilized.
The majority of the data processing is done on wide bit width
words with a clock cycle commensurate with the bandwidth
capabilities of CMOS and TTL logic. The parallel data is then
serialized into a high bandwidth data stream, a bandwidth
which requires ECL technologies, for transmission across a
long line to another box or machine. The signal is received
differentially and converted back to relatively low speed
parallel data where it can be processed further in CMOSnTL
logic. By taking advantage of the bandwidth and line driving
capabilities of ECL the system minimizes the number of lines
required for interconnecting 'the subsystems without
sacrificing the overall performance. Furthermore by taking
advantage of PECL this application can be realized with a
single five volt power supply. The configuration of Figure 1
illustrates a situation where the mixing of logic technologies
can produce a design which maximizes the overall
performance while managing power dissipation and
minimizing cost.

• Approximate for stnphne Interconnect (Lmax ~ Tr/2Tpd)

System Advantages of Eel
The most obvious area to incorporate ECL into an
otherwise CMOSnTL design would be for a subsystem which
requires very fast data or signal processing. Although this is
the most obvious it may also be the least common. Because of
the need for translation between ECL and CMOS/TTL
technologies the performance gain must be greater than the
overhead required to translate back and forth between
technologies. With typical delays of six to seven nanoseconds

ECLinPS and ECLinPS Lite
DL140-Rev4

5-61

MOTOROLA

AN1406
ECL Serial Data
>200MHz

SeriaVParallel
Conversion

Low Frequency
Information Processing

ECL Serial Data
>200MHz

Figure 1. Typical Use of ECl's High Bandwidth, line Driving Capabilities
Clock Distribution
Perhaps the most attractive area for ECl in CMOS! TTL
designs is in clock distribution. The ever increasing
performance capabilities of today's designs has placed an
even greater emphasis on the design of low skew clock
generation and distribution networks. Clock skew, the
difference in time between "simultaneous" clock transitions
throughout an entire system, is a major component of the
constraints which form the upper bound for the system clock
frequency. Reductions in system clock skew allow designers
to increase the performance of their designs without having to
resort to more complicated architectures or costly, faster logic.
ECl logic has the capability of significantly reducing the clock
skew of a system over an equivalent design utilizing CMOS or
TTL technologies.

Propagation delay variations with environmental conditions
must be accounted for in the specification windows of a
device. As a result because of ECLs AC stability the delay
windows for a device will inherently be smaller than similar
CMOS or TTL functions.

The skew introduced by a logic device can be broken up into
three areas; the part-to-part skew, the within-part skew and
the rise-to-fall skew. The part-to-part skew is defined as the
differences in propagation delays between any two devices
while the within-device skew is the difference between the
propagation delays of similar paths for a single device. The
final portion of the device skew is the rise-to-fall skew or simply
the differences in propagation delay between a rising input
and a failing input on the same gate. The within-device skew
and the rise-to-fall skew combine with delay variations due to
environmental conditions and processing to comprise the
part-to-part skew. The part-to-part skew is defined by the
propagation delay window described in the device data
sheets.

The virtues of differential interconnect in line driving have
already been addressed, however the benefits of differential
interconnect are even more pronounced in clock distribution.
The propagation delay of a signal through a device is
intimately tied to the switching threshold of that device. Any
deviations of the threshold from the center of the input voltage
swing will increase or decrease the delay of the signal through
the device. This difference will manifest itself as rise-to-fall
skew in the device. The threshold levels for both CMOS and
TTL devices are a function of processing, layout, temperature
and other factors which are beyond the control of the system
level designer. Because of the variability of these switching
references, specification limits must be relaxed to guarantee
acceptable manufacturing yields. The level of relaxation of
these specifications increases with increasing logiC depth. As
the depth of the logic within a device increases the input signal
will switch against an increasing number of reference levels;
each encounter will add skew when the reference level is not
perfectly centered. These relaxed timing windows add directly
to the overall system skew. Differential ECl, both internal and
external to the die, alleviates this threshold sensitivity as a DC
switching reference is no longer required. Withoutthe need for
a switching reference the delay windows, and thus system
skew, can be significantly reduced while maintaining
acceptable manufacturing yields.

Careful attention to die layout and package choice will
minimize within-device skew. Although this minimization is
independent of technology, there are other characteristics of
ECl which will further reduce the skew of a device. Unlike their
CMOS!TTl counterparts, ECl devices are relatively
insensitive to variations in supply voltage and temperature.

What does this mean to the CMOSlTTl designer? It means
that CMOSlTTl designers can build their clock generation
card and backplane clock distribution using ECL. Designers
will not only realize the benefits of driving long lines with ECl
but will also be able to realize clock distribution networks with
skew specs unheard of in the CMOSITTl world. Many

MOTOROLA

5-62

ECLinPS and ECLinPS Lile
DL140-Rev4

AN1406
specialized functions for clock distribution are available from
Motorola (MC10/100E111, MC10/100E211, MC10/100El11).
Care must be taken that all of the skew gained using ECl for
clock distribution is not lost in the process of translating
into CMOS/TTL levels. To alleviate this problem the
MC10/100H646 can be used to translate and fanout a
differential ECl input signal into TTL levels. In this way all of
the fanout on the backplane can be done in ECl while the
fanout on each card can be done in the CMOSml levels
necessary to drive the logic.
Figure 2 illustrates the use of specialized fanout buffers to
design a CMOSml clock distribution network with minimal
skew. With SOps output-to-output skew of the MC1 0/1 00E111
and 1ns part-to-part skew available on the MC1 0/1 00H646 or
MC1 0/1 00H641, a total of 72 or 81 TTL clocks, respectively,
can be generated with a worst case skew between all outputs
of only 1.0Sns. A similar distribution tree using octal CMOS or
TTL buffers would result in worst case skews of more than
6ns. This Sns improvement in skew equates to about SO% of
the up/down time of a SOMHz clock cycle. It is not difficult to
imagine situations where an extra SO% of time to perform
necessary operations would be either beneficial or even a life
saver. For more information about using ECl for clock
distribution, refer to application note AN140S/D - ECl Clock
Distribution Techniques.
Part-Part
Skew = Ins

Output-Output
Skew = 50ps

Differential
ECLInput

TIL
Outputs

Etll

TIL
Outputs

ask, although it is true that in a DC state ECl will typically
dissipate more power than a CMOSITTl counterpart, in
applications which operate continually at frequency, i.e .. clock
distribution, the disparity between ECl and CMOSml power
dissipation is reduced. The power dissipation of an ECl
device remains constant with frequency while the power of a
CMOS/TTL device will increase with frequency. As
frequencies approach SOMHz the difference between the
power dissipation of a CMOS or TTL gate and an ECl gate will
be minimal. SOMHz clock speeds are becoming fairly common
in CMosml based designs as today's high performance
MPUs are fast approaching these speeds. In addition,
because ECl output swings are significantly less than those
of CMOS and TTL the power diSSipated in the load will be
significantly less under continuous AC conditions.
It is clear that PECl can be a powerful design tool for
CMOSml deSigners, but where can one get these PECl
devices. Perhaps the most confusing aspect of PECl is the
misconception that a PECl device is a special adaptation of
an ECl device. In reality every ECl device is also a PECl
device; there is nothing magical about the negative voltage
supply used for ECl devices. The only real requirement of the
power supplies is that the potential difference described in the
device data sheets appears across the upper and lower power
supply rails (VCC and VEE respectively). A potential stumbling
block arises in the specified VEE levels for the various ECl
families. The 1OH and 1OOK families specify parametric values
for potential differences between VCC and VEE of 4.94V to
S.46V and 4.2V to 4.8V respectively; this poses a problem for
the CMOSml designer who works with a typical VCC of5.0V
±S%. However, because both of these ECl standards are
voltage compensated both families will operate perfectly fine
and meet all of the performance specifications when operated
on standard CMOSml power supplies. In fact, Motorola is
extending the VEE specification ranges of many of their ECl
families to be compatible with standard CMOSml power
supplies. Unfortunately earlier ECl families such as MECl
10KTM are not voltage compensated and therefore any
reduction in the potential difference between the two supplies
will result in an increase in the VOL level, and thus a decreased
noise margin. For the typical CMOSml power supplies a
10K device will experience an =SOmV increase in the VOL
level. Designers should analyze whether this loss of noise
margin could jeopardize their designs before implementing
PECl formatted 10K using S.OV ± S% power supplies.

Figure 2. Low Skew Clock Fanout Tree

PECl versus ECl
Nobody will argue that the benefits presented thus far are
not attractive, however the argument will be made that the
benefits are not enough to justify the requirements of including
ECl devices in a predominantly CMOSml design. After all
the inclusion of ECl requires two additional negative voltage
supplies; VEE and the terminating voltage VTT. Fortunately this
is where the advantages of PECl come into play. By using
ECl devices on a positive five volt CMOSml power supply
and using specialized termination techniques ECl logic can
be incorporated into CMOSml designs without the need for
additional power supplies. What about power dissipation you

ECLinPS and ECLinPS Lite
DL140-Rev4

The traditional choice of a negative power supply for ECl is
the result of the upper supply rail being used as the reference
for the I/O and intemal switching bias levels of the technology.
Since these critical parameters are referenced to the upper rail
any noise on this rail will couple 1:1 onto them; the result will be
reduced noise margins in the design. Because, in general, it is
a simpler task to keep a ground rail relatively noise free, it is
beneficial to use the ground rail as this reference. However
when careful attention is paid to the power supply deSign,
PECl can be used to optimize system performance. Once
again the use of differential PECl will simplify the designer's
task as the noise margins of the system will be doubled and
any noise riding on the upper VCC rail will appear as common
mode noise; common mode noise will be rejected by the
differential receiver.

5-63

MOTOROLA

AN1406

MECl to PECl DC level Conversion
Although using ECl on positive power supplies is feasible,
as with any high speed design there are areas in which special
attention should be placed. When using ECl devices with
positive supplies the input output voltage levels need to be
translated. This translation is a relatively simple task. Since
these levels are referenced off of the most positive rail, VCC,
the following equation can be used to calculate the various
specified DC levels for a PECl device:
PECl level = VCCNEW -ISpecification levell
As an example, the VOHMAX level for a 1OH device operating
with a VCC of 5.0V at 25°C would be as follows:
PECl level
PECl level

=5.0V - 1-Q.81V1
=(5.0 - 0.81)V =4.19V

The same procedure can be followed to calculate all of the DC
levels, including VBB for any ECl device. Table 2 althe bottom
of the page outlines the various PECl levels for a VCC of 5.0V
for both the 10H and lOOK ECl standards. As mentioned
earlier any changes in VCC will show up 1:1 on the output DC
levels. Therefore any tolerance values for VCC can be
transferred to the device I/O levels by simply adding or
subtracting the VCC tolerance values from those values
provided in Table 2.

thorough discourse on when and where to use the various
termination techniques the reader is referred to the MECl
System Design Handbook (HB2051D) and the design guide in
the ECLinPS Databook (Dl140/D). The parallel termination
scheme of Figure 3 requires an extra Vn power supply for the
impedance matching load resistor. In a system which is built
mainly in CMOSml this extra power supply requirement
may prohibit the use of this technique. The other schemes of
Figure 3 use only the existing positive supply and ground and
thus may be more attractive for the CMOSI TTL based
machine.
Parallel Termination Schemes
Because the techniques using an extra Vn power supply
consume Significantly less power, as the number of PECl
devices incorporated in the design increases the more
attractive the VTT supply termination scheme becomes.
Typically ECl is specified driving 50n into a -2.0V, therefore
for PECl with a VCC supply different than ground the Vn
terminating voltage will be VCC - 2.0V. Ideally the Vn supply
would track 1:1 with VCC, however in theory this scenario is
highly unlikely. To ensure proper operation of a PECl device
within the system the tolerances of the Vn and the VCC
supplies should be considered. Assume for instance that the
nominal case is for a 50n load (Rt) into a +3.0V supply; for a
10HcompatibledevicewithaVOHmaxof-Q.81Vandarealistic
VOlmin of -1 .85V the following can be derived:
IOHmax = (VOHmax - Vn)/Rt
IOHmax = ({5.0 - 0.81} - 3.0)/50 = 23.8mA
IOlmin = (VOlmin - Vn)/Rt
IOlmin = ({5.0 - 0.81} - 3.0)/50 = 3.0mA

PECl Termination Schemes
PECl outputs can be terminated in all of the same ways
standard ECl, this would be expected since an ECl and a
PECl device are one in the same. Figure 3 illustrates the
various output termination schemes utilized in typical ECl
systems. For best performance the open line technique in
Figure 3 would not be used except for very short interconnect
between devices; the definition of short can be found in the
various design guides for the different ECl families. In general
for the fastest performance and the ability to drive distributive
loads the parallel termination techniques are the best choice.
However occasions may arise where a long uncontrolled or
variable impedance line may need to be driven; in this case the
series termination technique would be appropriate. For a more

If +5% supplies are assumed a V CCofVCCnom-5%and a Vn
of Vnnom +5% will represent the worst case. Under these
conditions, the following output currents will result:
IOHmax = ({4.75 -0.81} - 3.15)/50 = 15.8mA
IOlmin ({4.75 - 1.85} - 3.15)/50 OmA

Using the other extremes for the supply voltages yields:

IOHmax 31.8mA
IOlmin = llmA

Table 2. ECUPECL DC Level Conversion for VCC = 5.0V

1OE Characteristics
ooe
Symbol

100E Characteristics

25°e

Oto 85°e

85°e

Min

Max

Min

Max

Min

VOH

-1.02/3.98

-0.84/4.16

-0.98/4.02

-0.81/4.19

-0.92/4.08

-0.735/4.265 -1.025/3.975 -0.880/4.120

VOL

-1.95/3.05

-1.63/3.37

-1.95/3.05

-1.63/3.37

-1.95/3.05

-1.600/3.400 -1.810/3.190 -1.620/3.380

VOHA

VOLA

Max

Min

Max

Unit

-1.610/3.390

-1.035/3.965

VIH

-1.17/3.83

-0.84/4.16

-1.13/3.87

-0.81/4.19

-1.07/3.93

-0.735/4.265 -1.165/3.835 -0.880/4.120

VIL

-1.95/3.05

-1.48/3.52

-1.95/3.05

-1.48/3.52

-1.95/3.05

-1 .450/3.550 -1.810/3.190 -1.475/3.525

VBB

-1.38/3.62

-1.27/3.73

-1.35/3.65

-1.25/3.75

-1.31/3.69

-1.190/3.810 -1.380/3.620 -1.260/3.740

MOTOROLA

5--64

EClinPS and EClinPS lite
DL140-Rev4

AN1406
20

Open Line Termination

Parallel Termination

RS=Zo

Series Termination

Thevenin Parallel Termination

Figure 3. Termination Techniques for ECL/PECl Devices
The changes in the IOH currents will affect the De VOH
levels by =±40mV at the two extremes. However in the vast
majority of cases the De levels for Eel devices are well
centered in their specification windows, thus this variation will
simply move the level within the valid specification window
and no loss of worst case noise margin will be seen. The IOl
situation on the other hand does pose a potential Ae problem.
In the worst case situation the output emitter follower could
move into the cutoff state. The output emitter followers of ECl
devices are designed to be in the conducting "on" state at all
times. If cutoff, the delay of the device will be increased due to
the extra time required to pull the output emitter follower out of
the cutoff state. Again this situation will arise only under a
number of simultaneous worst case situations and therefore is
highly unlikely to occur, but because of the potential it should
not be overlooked.

For the typical setup:
Vee

=5.0V; VEE =GND; VTT =3.0V; and Zo =501.1

R2 = 50 ({5 - O}/{5-3}) = 1251.1
Rl 125 ({5-3}/{3--0)} 83.31.1

checking for VTT
VTT = 5 (125/{125 - 83.3)} = 3.0V
Because of the resistor divider network used to generate
VTT the variation in V will be intimately tied to the variation in
Vee. Differentiating the equation for VTT with respectlo Vee
yields:
dVTT/dVee = R2/(Rl + R2) dVee
Again for the nominal case this equation reduces to:

tNTT = 0.6 !'Nee
So that for 1;.Vee
Thevenin Equivalent Termination Schemes
The Thevenin equivalent parallel termination technique of
Figure 3 is likely the most attractive scheme for the
CMOSml designer who is using a small amount of ECL. As
mentioned earlier this technique will consume more power,
however the absence of an additional power supply will more
than compensate for the extra power consumption. In
addition, this extra power is consumed entirely in the external
resistors and thus will not affect the reliability of the Ie. As is
the case with standard parallel termination, the tolerances of
the VTT and Vee supplies should be addressed in the design
phase. The following equations provide a means of
determining the two resistor values and the resulting
equivalent VTT terminating voltage.
Rl = R2 ({Vee - VTT}/{VTT - VEE)}
R2 = Zo ({Vee - VEE}/{Vee - VTT)}
VTT = Vce (R2/{Rl + R2})

ECLinPS and ECLinPS Lite
DL140-Rev4

=±5% =±0.25V, 1;.VTT =±O.15V.

As mentioned previously the real potential for problems will
be if the VOL level can potentially put the output emitter
follower into cutoff. Because of the relationship between the
Vee and VTT levels the only situation which could present a
problem will be for the lowest value of Vee. Applying the
equation for IOlmin under this condition yields:
IOlmin = ({VOlmin - VTT}/Rt
IOlmin ({4.75 - 1.85) -2.85)/50

=1.0mA

From this analysis it appears that there is no potential for the
output emitter follower to be cutoff. This would suggestlhatthe
Thevenin equivalent termination scheme is actually a better
design to compensate for changes in Vee due to the fact that
these char,ges will affect VTT, although not 1:1 as would be
ideal, in the same way. To make the design even more immune
to potential output emitter follower cutoff the designer can
design for nominal operation for the worst case situation.
Since the designer has the flexibility of choosing the VTT level
via the selection of the Rl and R2 resistors the following
procedure can be followed.

5--65

MOTOROLA

AN1406
let VCC = 4.75V and VTT = VCC - 2.0V = 2.75V
Therefore:
R2 = 119n and R1 = Ben thus:
IOHmax = 23mA and IOlmin = 3.0mA
Plugging in these values forthe equations at the other extreme
for VCC = 5.25V yields:
VTT = 3.05V, IOHmax = 2BmA and IOlmin = 5.2mA
Although the output currents are slightly higher than nominal,
the potential for performance degradation is much less and
the results of any degradation present will be significantly less
dramatic than would be the case when the output emitter
follower is cutoff. Again in most cases the component
manufactures will provide devices with typical output levels;
typical levels significantly reduces any chance of problems.
However it is important that the system designer is aware of
where any potential problems may come from so they can be
dealt with during the initial design.

possible. To minimize the VCC noise of a system liberal
bypassing techniques should be employed. Placing a bypass
capacitorof 0.Q1 !iF to 0.1!iF on the VCC pin of every device will
help to ensure a noise free VCC supply. In addition when using
PECl in a system populated heavily with CMOS and TTL logic
the two power supply planes should be isolated as much as
possible. This technique will help to keep the large current
spike noise typically seen in CMOS and TTL drivers from
coupling into the ECl devices. The ideal situation would be
multiple power planes; two dedicated to the PECl Vcc and
ground and the other two to the CMOSml VCC and ground.
However if these extra planes are not feasible due to board
cost or board thickness constraints common planes with
divided subplanes can be used (Figure 5). In either case the
planes or sub planes should be connected to the system
power via separate paths. Use of separate pins of the board
connectors is one example of connecting to the system
supplies.

Differential Eel Termination
Differential ECl outputs can be terminated using two
different strategies. The first strategy is to simply treat the
complimentary outputs as independent lines and terminate
them as previously discussed. For simple interconnect
between devices on a single board or short distances across
the backplane this is the most common method used. For
interconnect across larger distances or where a controlled
impedance backplane is not available the differential outputs
can be distributed via twisted pair of ribbon cable (use of
ribbon cable assumes every other wire is a ground so that a
characteristics impedance will arise). Figure 4 illustrates
common termination techniques for twisted pair/ribbon cable
applications. Notice that Thevenin equivalent termination
techniques can be extended to twisted pair and ribbon cable
applications as pictured in Figure 4. However for twisted
pair/ribbon cable applications the standard termination
technique picture in Figure 4 is somewhat simpler and also
does not require a separate termination voltage supply. If
however the Thevenin techniques are necessary for a
particular application the following equations can be used:

Standard Twisted Pair Termination

Parallel Twisted Pair Termination

R1 + R2= ZO/2
R3 = R1 (VTT - VEE)/(VOH + VOL - 2VTT)
VTT = (R3{VOH + voLl + R1{VEE})/(R1 + 2R3)
where VOH, VOL, VEE and VTT are PECl voltage levels.
Plugging in the various values for VCC will show that the VTT
tracks with VCC at a rate of approximately 0.7: 1. Although this
rate is approaching ideal it would still behoove the system
designer to ensure there are no potential situations where the
output emitter follower could become cutoff. The calculations
are similar to those performed previously and will not be
repeated.

Noise and Power Supply Distribution
Since ECl devices are top rail referenced it is imperative
that the VCC rail be kept as noise free and variation free as

MOTOROLA

Thevenin Twisted Pair Termination

Figure 4. Twisted Pair Termination Techniques
For single supply translators or dual supply translators
which share common power pins the package pins should be
connected to the ECl VCC and ground planes to ensure the
noise introduced to the part through the power plane is
minimal. For translating devices with separate TTL and ECl

5-66

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1406
;---

...L'

System

CMOSml +5.0V PLANE

"-::F-

:::c

CMOS
Sub System

+S.OV

TTL
Sub System

f---

r--

~
CMOSml GROUND PLANE

PECl +5.0V PLANE

"-::F-

System
Ground

...L'

:::c

ECl
SubSystem

•

Low frequency bypass at the

board input

.. High frequency bypassatthe
individual device level

~
PECl GROUND PLANE

'--

Figure 5. Power Plane Isolation in Mixed logic Systems

power supply pins, the pins should be tied to the appropriate
power planes.

devices. Because different devices have different ESD
protection schemes, and input architectures, the extent of the
potential problem will vary from device to device.

Another concern is the interconnect between two cards with
separate connections to the VCC supply. If the two boards are
at the opposite extremes of the VCC tolerance, with the driver
being at the higher limit and the receiver at the lower limit,
there is potential for soft saturation of the receiver input. Soft
saturation will manifest itself as degradation in AC
performance. Although this scenario is unlikely, again the
potential should be examined. For situations where this
potential exists there are devices available which are less
susceptible to the saturation problem. This variation in VCC
between boards will also lead to variations in the input
switching references. This variation will lead to switching
references which are not ideally centered in the input swing
and cause rise/fall skew within the receiving device. Obviously
the later skew problem can be eliminated by employing
differential interconnect between boards.

Another issue that arises in driving backplanes is situations
where the input Signals to the receiver are lost and present an
open input condition. Many differential input devices will
become unstable in this situation, however, most of the newer
designs, and some of the older designs, incorporate internal
clamp circuitry to guarantee stable outputs under open input
conditions. All olthe ECLinPS (exceptforthe E111), ECLinPS
Lite, and H600 devices, along with the MC1 0125, 1OH 125 and
10114 will maintain stable outputs under open input
conditions.

When using PECl to drive signals across a backplane,
situations may arise where the driver and the receiver are on
different power supplies. A potential problem exists if the
receiver is powered down independent of the driver. Figure 6
(on the following page) represents a generic driver/receiver
pair. From Figure 6, one can see if the receiver is powered
down and presents a path to ground through its VCC pin while
the driver is still powered at +5.0V the base/collector junction
of the input transistor of the receiver will be forward biased and
conduct current. Although the collector load resistor will limit
the current in the situation of Figure 6, the current may still be
enough to damage the junction or exceed the current handling
capability of the base electrode metal stripe. Either of these
situations could lead to degradation of the reliability of the

EClinPS and EClinPS lite
DL140- Rev 4

Conclusion
The use of ECl logic has always been surrounded by
clouds of misinformation; none of those clouds have been
thicker than the one concerning PECL. By breaking through
this cloud of misinformation the traditional CMOS/TTL
designers can approach system problems armed with a
complete set of tools. For areas within their designs which
require very high speed, the driving of long, low impedance
lines or the distribution of very low skew clocks, designers can
take advantage olthe built in features of ECL. By incorporating
this ECl logic using PECl methodologies this inclusion need
not require the addition of more power supplies to
unnecessarily drive up the cost of their systems. By following
the simple guidelines presented here CMOSml designers
can truly optimize their designs by utilizing ECl logic in areas
in which they are ideally suited. Thus bringing to market
products which offer the ultimate in performance at the lowest
possible cost.

5-67

MOTOROLA

AN1406

5.0V-GND

Driver
Receiver

Figure 6. Generic DriverlRecelver Pair

MOTOROLA

5-68

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1503
Application Note

ECLinPSTM I/O SPICE
Modeling Kit

Prepared by

Todd Pearson
ECLinPS Applications Engineering

This application note provides the SPICE information
necessary to accurately model system interconnect
situations for high speed ECLinPS designs. The note
includes information on both the standard ECLinPS
family, as well as the ECLinPS Lite products.

ECUnPS and ECUnPS Ute are trademarks of Motorola, Inc.

10191

5-69

REVO

MOTOROI.A

AN1503

ECLinPS 1/0 SPICE Modeling Kit
Objective
The objective of this kit is to provide customers with enough
circuit schematic and SPICE parameter information to allow
them to perform system level interconnect modeling for the
Motorola ECLinPS and ECLinPS Lite logic families. The
ECLinPS and ECLinPS Lite families are Motorola's highest
performance ECl families. With packaged gate delays of
300ps and output edge rates as low as 175ps these two
families define the state-of-the-art in ECl logic. This kit is not
intended to provide the user with the information necessary to
perform extensive device modeling for any particular
ECLinPS or ECLinPS Lite device. If users wish to perform the
latter type of SPICE modeling they are encouraged to contact·
an ECLinPS Applications Engineer to obtain more detailed
schematics and SPICE parameter information or order
Motorola Application Note AN1560/D, Low Voltage ECLinPS
SPICE Modeling Kit, from the Motorola Literature Distribution
Center.
Schematic Information
The kit contains representative schematics for the different
1/0 circuits used in the ECLinPS and ECLinPS Lite families. In
addition a worst case package model schematic is included for
more accurate system level modeling. The package model
represents the parasitics as they are seen on a corner pin, a
sizable distance from an AC ground. If more typical values are
desired a 20% reduction in the capacitance and the
inductance of the package model can be used. This package
model should be placed on all external inputs to the input
gates, all outputs of the output gates and on the VCC line. If
desired the model can also be placed on the VEE line, however
this is not necessary due to the static nature of VEE.
There is only one schematic, Figure 1, to represent the input
structures of the family. For interconnect purposes this one
schematic will adequately represent all of the ECLinPS
devices except the differential input devices and the simple
gates. The schematic in Figure 1 can be modified to represent
differential devices by simply adding the package model and
the ESD structure to the "VSS" input and using this as the
inverted signal input. For the simple gates the input gate is
actually the output gate represented by Figure 2. Therefore
these devices should be modelled with the circuit of Figure 2
with the appropriate package model and ESD circuitry from
Figure 1 added to the schematic. For the devices in the
ECLinPS Lite family outlined in the appendix whose output
and input buffers are one in the same the ESD circuitry and
package models should be added to the appropriate output
buffer. A list of devices which incorporate this structure is
included in the appendix of this document.

Lite families. Figure 3 shows the circuit configuration for a
multiple output device (ie EI12). Notice the doubling of the
gate current necessary to drive the multiple output emitter
followers. Figure 4 is the typical bidirectional 25n output
structure used for the two bus driving functions currently in the
ECLinPS family. Notice the doubled output emitter follower
(OEF). This is necessary to provide a small enough VSE to
produce an acceptable VOH level while providing the current
necessary for 25n drive. In addition the collector load resistors
have been increased to provide a cutoff Val. Due to the larger
collector load resistor the gate current is increased 3x to
reduce the relative size of the collector load resistors so that
the Ib of the OEF does not produce an IR drop across the
collector load resistor sufficient to create a marginal VOH.
The schematics in Figures 5 and 6 represent the bandwidth
enhanced ECLinPS and ECLinPS Lite devices. Secause the
bandwidth of standard ECLinPS devices are limited by their
rise and fall times, the bandwidth can be enhanced by simply
using higher current levels in the output buffers. This added
current allows the parasitic capacitances olthe gate to charge
and discharge more quickly, thus enhancing the transition
time performance of the device. Thus far two levels of gate
current increase have been used to reach two different
plateaus of performance. The majority of the enhanced
bandwidth ECLinPS and ECLinPS Lite devices utilize the 2x
current increase of Figure 4. A full outline of the devices which
utilize these buffers can be found in the appendix.
The schematics of Figure 7 represent the temperature
compensation networks present in the output structures for
1OOE devices. The output buffer schematics all reference one
of the temperature compensation networks. The temperature
compensation circuitry should be placed as pictured in the
output buffer schematics with land R representing left and
right of the schematic. Obviously for 1OE circuit outputs these
networks can be ignored. Also included in the appendix is the
package model of Figure 8 and the ESD circuitry of Figure 9.
The ECLinPS ESD should be added to any input of an
ECLinPS device being driven by a Signal off chip. The
ECLinPS Lite ESD should be added to both the inputs and
outputs for any ECLinPS Lite device being modelled. Finally
the appropriate package model (8-lead SOIC for ECLinPS
Lite or 28-lead PlCC for ECLinPS) should be included on all
input and output pins and at least the VCC power supply.
Soth the typical and multiple output circuits show differential
inputs and outputs. If the user is simulating a single ended
device the OEF and associated package model and load
resistor of the unneeded output should be deleted from the
schematic. If the user chooses to drive an output cell directly
instead of using the input cell either of the following two driving
approaches can be used:

There are five basic output structures needed to represent
both families. The structure in Figure 2 mentioned above
represents the structure used in the majority of the family, a
simple 50n drive output cell. Figures 3 and 4 represent the
special output functions used in the ECLinPS and ECLinPS

MOTOROLA

5-70

VBB

Rise/Fall

Dill

-1.2V > -1.6V

-1.6V>-1.2V

180ps (20% - 80%)

S.E.

-0.9V > -1.7SV

-1.32SV

180ps (20% - 80%)

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1503
SPICE Parameter Information

schematics to provide output characteristics at or near the
corners of the data book specification limits. First to adjust the
VOH level one simply needs to lower the VCC value below
ground by the amount one wishes to alter the VOH level. This
VCC adjustment will obviously also result in a change in the
VOL level. To change the VOL level independent of the VOH
level the collector load resistors can be increased or
decreased depending on the change desired (Note: VOH will
change slightly due the the IbR drop portion of the VOH level).
The VOL can also be changed by increasing/decreasing the
current in the gate via the current source resistor. In addition to
changing the VOL level, by increasing/decreasing the gate
current the output rise and fall times will decrease/increase
due to the additional current available to charge and discharge
the stray capacitance on the collectors of the output
differential pair. If the user would like to adjust the levels and
transition times of an output gate to represent a corner of the
guaranteed specification the following sequence should be
followed:

In addition to the schematics a listing of the SPICE
parameters for the transistors referenced in the schematics is
included. These parameters represent a typical device of the
given transistor size. Varying these parameters will obviously
affect the voltage levels, the propagation delays, and the
transition times of a device. For the type of modeling for which
this information is intended the actual propagation delay of a
device will not be modelled, as a result variations in this
parameter are meaningless. Furthermore the voltage levels
and transition times can be more easily varied by other means.
This will be addressed in the next section.
All of the resistors referenced in the schematics are
polysilicon resistors and thus there is no need to provide
parasitic capacitance models for these resistors in the nellist.
The only devices needed in the SPICE nellist are illustrated in
the schematics.
modeling Information

1) Adjust the gate current to produce the desired output
slew rate
2) Adjust the VCC for the desired VOH
3) Adjust the collector load resistor for the desired VOL

The bias driver schematics are not included as they were
deemed unnecessary for interconnect simulation, in addition
their use also results in a relatively large increase in
simulation time. Alternatively the internal reference voltages
(VBB and VCS) should be driven with ideal constant voltage
sources. The following table summarizes the voltage levels for
these internal references as well typical input voltage
parameters.
Parameter
VBB
VCS
VIH
VIL
Rise/Fall

Typical Level

Worst Case

-1.325V
VEE + 1.33V
-0.9V (toE); -0.95V (IOOE)
-1.75V (IOE);-1.7V (IOOE)
400ps (20% - 80%)

Data Book
±50mV
Data Book
Data Book
Data Book

Summary
The information included in this kit should provide the user
with all of the information necessary to do SPICE level system
interconnect modeling. The block diagram of Figure 10
illustrates the type of situation which can be effectively
modelled using the ECLinPS I/O SPICE modeling Kit. The
schematic information provided in this document is available
in nellist form through EMAIL or an IBM or Macintosh disk,
although with today's advanced design tools it will probably be
a simpler task to enter the schematics in a good schematic
capture package than it would be to manipulate the generic
nellist. If however the nellist are desired, clarification is
needed or additional information is necessary the user is
encourage to contact any ECLinPS Application Engineering
personnel for assistance.

The schematics and SPICE parameters provided will
provide a somewhat typical output waveshape which may not
represent the worst case system situation. Fortunately there
are some simple adjustments that can be made to the

ECLinPS and ECLinPS Lite
DL140-Rev4

5-71

MOTOROLA

AN1503

Vee

PKG~-----4~-------------'_----'

Rl
2500

R2
2700

R3
2700

o
t---I---o os

Vss

Ves-i~~------------------~~~

R6
6500

R4
3250
RESISTOR Te = 0.405M, 2.2U
VEE

Figure 1. Typical Input Schematic

Vee

PKG>-----<....- - - - -....- - - - - - - - -....- - . ,

o
Vss

RESISTOR Te = 0.405M, 2.2U
03
TN13p5

Ves
Ig =3.5mA

R3
1300

Figure 2. Typical Output Schematic

MOTOROLA

5-72

ECLinPS and ECLinPS Lite

DL140- Rev 4

AN1503

Vcc

p~>-----__----------~~------~~--~---------------.----,

l50n

Q6
TNECLiPS

Q4
TNECliPS

Q7
TNECLiPS

Qa
'---------jPKG

QaB

' - - - - - - - \ PKG

QbB

RESISTOR TC = 0.405M, 2.2U

Figure 3. Multiple Output Schematic
VCC PKG>------Q-------------O-------------------...,

lOon

loon

R3
60n

F=--t....::::'-t-

vBB

~-------

CLOCK

SYSTEM 2

CLOCK

TO DELAY

Figure 1. Clock Synchronization Schemes

MOTOROLA

5-80

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1504

1/
/

CLOCK

DATA: CASE 1

DATA: CASE 2

DATA: CASE 3
TSU

VOUTCASE2

TCLK

THD

Figure 2. Timing Relationships Between Data and Clock Signals for a D Flip-Flop

28.6300 NS

31.1300NS

33.6300 NS

CH.3 = 150.0 mViDIV

TIMEBASE = 500 PSIDIV

Figure 3. Typical Flip-Flop Output Response

ECLinPS and ECLinPS Lile
DL140-Rev4

5-81

MOTOROLA

AN1504
28.6300NS

31.1300 NS
J
I
I

33.6300NS

,,,
,,

I.~
. ,,

.::",. :

, ",

,~.

~,
.. .,,

~.:. ,
~,.

-:~j~ ~).o,,·,l
r

CH. 3 = 150.0 mVlDlV
START =30.8500 NS

.. , ,

TIMEBASE = 500 PSIDIV
DELTA T = 710.0 PS

STOP = 31.5600 NS

Figure 4. Metastable Flip-Flop Output Response

The flip-flop shown in Figure 5 can be divided into two
functional blocks: Master latch and Slave latch. Under optimal
operating conditions the clock is low when data arrives at the
input to the master latch; after the specified set-up time the
clock input is raised to a high level, and the data is latched.
When the clock signal goes to the low state, the slave portion
of the circuit becomes transparent and transfers the latched
data to the output. Changes at the input will have no affect on
the output when the "slave latch" is transparent.

clock differential pair switches from the regenerative to the
data side. If the set-up and hold times are observed the circuit
will function properly. However, if the data and clock signals
change such that the set-up and hold times are violated, the
data differential pair, the regenerative differential pair and the
clock differential pair for the master will share the same switch
current. In addition there will not be enough current to charge
and discharge the transistor parasitic capacitances, creating
an RC feedback loop via the collector nodes of the data and
regenerative differential pairs. Thus the master latch enters a
metastable state which appears at the output since the slave
latch is transparent under these conditions. Theoretically,
there is no upper bound on the length of time this metastable
state can last, although in practice circuits eventually do leave
the metastable region.

The master and slave latches each consist of two
subsections: Data and Regenerative (Figure 5). Since the
master latch accepts signals from external sources it is the
section most susceptible to metastability problems. When the
clock signal goes to a high state the current in the master latch

DATA

MASTER LATCH

VCC

REGENERATIVE

J.1-

DATA
RESET
DATA
SET
CLOCK
CLOCK
VCS

,r1

I-

~ ~ ~ ~I

....,1

...... --'"

.....

REGENERATIVE

.....

-"".

SLAVE
LATCH

DATA

I I

-< --~-~--~

.....

I ""

~
~

--'"

VEE

Figure 5. ECLinPS 0 Flip-Flop

MOTOROLA

5-a2

ECLinPS and ECLinPS Lile
DL140-Rev4

AN1504
Metastable Equations
Flip-flop propagation delay as a function of the input signal
is represented in Figure 6.

I~~m.
TIME

Figure 6. Flip-Flop Response Time Plot
The ordinate is the flip-flop propagation delay time, and the
abscissa is the time that data arrives at the flip-flop input
relative to reference time, TO. For devices with positive set-up
times TO represents the clock transition time with the
difference between ToandTMAxbeingthe minimum allowable
set-up time. Thus data arriving before time TMAX will elicit a
nominal propagation delay, Tp, when clocked. For data
appearing between times TMAX and TFthe propagation delay
will be longer than Tp because the set-up and/or hold times
have been violated; and the device enters the metastable

state. Data occurring at the input after time TF will have no
affect on the output, hence the output does not change and the
propagation delay is defined as zero.
For devices with zero or negative set-up times the same
response plot applies, however the abscissa is shifted such
that the value of TO is no longer the clock transition time. The
same concepts are valid for derivation of metastability
equations for each case: positive, negative or zero set-up and
hold times. To clarify the flip-flop response plot, Figure 7a
illustrates a case in which the propagation delay is Tp. Data
arrives at time TA, allowing the proper set-up time prior to a
clock transition and is maintained at this level for the specified
hold time. Figure 7b is an example in which the propagation
delay is longer than Tp since the data arrives at time TA,
violating the set-up time.
Using the response plot in Figure 6, 5toll 1 developed the
concept of a failure window to facilitate the characterization of
metastability. The value of TW(TO) is the width of the window
for which a propagation delay of time duration TO occurs, and
is the range of data input times relative to the clock input for
which a failure will occur. The value of TO is the maximum
allowable propagation delay; delays longer than TO constitute
a failure. The failure window is described mathematically as:
TW(TO) = Tp*1 0-(At)/1
Where: TW(TO)
Tp
TO

Failure Window Width
Nominal Propagation Delay
Delay After Clock That
Constitutes a Failure
Flip-Flop Resolution Time Constant
Excess Delay (TO - Tp)

1
At

III

(eqt 1)

I I

I I
OATASIGNAL

CLOCK SIGNAL

II
II
II I
II
II

OATASIGNAL

CLOCK SIGNAL

II
I

JL
I

I II

:II
TIME

TMAX TA TO

Figure 7a. Proper Set-Up and Hold Times

ECLinPS and ECLinPS Lite
DL140-Rev4

I
I
I II
I I
I I

TIME

Figure 7b_ Violation of Set-Up and Hold Times

5-83

MOTOROLA

AN1504
This equation only applies for narrow window widths i.e.
those times well up on the response plot of Figure 6.

Test CIrcuitry For Metastable Evaluation
Equation 3 provides the impetus for the design of a
metastability test circuit capable of providing a value of ~, the
flip-flop resolution time constant. Transforming this equation
into a "linear" form by taking the logarithm of both sides yields
Equation 4:

To summarize, when the set-up and hold times are obeyed
the flip-flop will have a nominal propagation delay, Tp. If the
data and clock signals arrive such that the set-up and hold
times are violated there will be an excess delay as indicated in
the response plot of Figure 6. This excess delay is caused by
the flip-flop entering the metastable region. For data signals
arriving much later than the clock signal the flip-flop will not
change state, thus the propagation delay is zero by definition.
The window width is the range of input arrival times relative to
the clock for which the output response does not attain a
defined value within the time period TD. Since TD represents
the maximum allowable delay, the window width represents
the relative range of input times for which a failure will occur.

log MTBF = -log (2*fC*fD*Tp) + LlV~

Plotting log MTBF versus Llt yields a line with slope 1h, and
log MTBF intercept of -log(2*fc*fd*Tp). Thus, the test circuit
must accept the clock and data input frequencies as a function
of Llt and yield MTBF as an output. The circuit configuration
shown in Figure 8 fulfills these criteria.

Equation 1 can be combined with the industry accepted
definition for system level Mean Time Between Failures (eqt.
2)2 to derive an equation yielding Mean Time Between
Failures as a function of system design and semiconductor
device parameters.
MTBF = 1I(2*fC*fD*Tw(TD))
Where: fC
fD
MTBF

The test circuitry can be categorized into five functional
blocks: DUT, adjustable delay portion, comparator section,
counter-set circuitry, and the counter. Starting with the
comparator portion of the circuit, the output of the DUT is fed
into the comparator; if the DUT output falls in the range VBS0.15 volts < VBB < VBB + 0.15 volts, the DUT is defined as
being in a metastable condition(Fig. 9).

(eqt2)

Clock Frequency
Data Frequency

=1/(2*fC*fD*Tp*10-(Llt)/,,)

(eqt4)

For DUT output states in the metastable region the
comparator output attains a logic high level. When the DUT
output does not fall within this range it is in a "defined high or
low level," and the output of the comparator will be at a logic
low level. If the comparator output is at a logic high level,
indicating metastability, the counter-set section sends out a
periodic waveform which increments the counter. If the DUT is
not metastable the output of the 'counter-sef' circuitry is
constant and the counter (HP-8335A) is not incremented. The
total number of counts over a specified time period is a
measure of MTBF.

(eqt3)

The system's designer can use Equation 3 to address the
issue of metastability. ~ and Tp are provided in the ECLinPS
Data Book (DLI40/D). MTBF, fc and fd are system design
parameters. Thus the designer can use this equation to
determine the value of TD.

r--------,

OUT

I
-, I

I
I

(VBB+ 0.15 V)
10E451

Ir;:----, r - - ,

01
02

HP5335A
COUNTER

LT..J

10E107

CLK2

10t:

CLK2

COUNTER

I
I

(VBB-0.15V)

----r-- -r-.J

ADJUSTABLE DELAY

COMPARATOR

COUNTER-SET

FIgure 8. Metastability Test CIrcuit

MOTOROLA

5-84

ECLinPS and ECLinPS Lite

DL140-Rev4

AN1504
Pulse generator #1 (PG 1) supplies the data signal to the
DUT. To ensure asynchronous signals between the DUT data
and clock signals, a separate pulse generator, PG2, provides
the clock signal to the DUT. Generator PG2 also provides the
clocking signal to the comparator circuitry via its inverting
output terminal. Pulse generator PG3 supplies the clock
signals to the E451 portion of the comparator section. To
increase the probability of the DUT entering the metastable
state the DUT data frequency is set at 1.33 times the DUT
clock frequency. The value of Il.t is the delay between the
noninverting clock signals for the DUT and the E451. Finally,
the inverting terminal of PG2 supplies the clock signal for the
counter-set circuitry.

2.---------------------~--_,

u. -2
ID

':E
'"g

-4

-6
-8
2e-9

3e-9

5e-9

4e-9
DELAY (SEC)

Figure 10. Plot of log MTBF versus Delay
VOH

!:i

Vss + 0.15 VOLTS = VHMETA

From Equation 4 the slope of the line is the reciprocal of ~.
Measurements similar to these were performed to
characterize the ECLinPS family as well as D flip-flops from
various vendors. The results are shown in Table 2:

.....
w

Vss

:::>

Il.

:::>
0

Vss - 0.15 VOLTS = VLMETA

>:::>

Table 1. ~ Values for Several Flip-Flops

Device Type

VOL

Figure 9. Output Response Defining the
Metastable Region
To take advantage of the precision 50n input impedance of
the test measurement equipment, the circuit power supplies
are shifted by +2.0 volts. Thus all input signals, bias voltages,
and comparator values have been shifted by +2.0 volts as
shown in Table 1.
Table 1. Eel levels After Translating by +2.0V
Typical (V)
Parameter

Shifted (V)

10E

100E

10E

100E

Vil

-1.75

-1.70

+0.25

+0.30

VIH

-Q.90

-0.95

+1.10

+1.05

VBB

-1.30

+0.70

VCC

0.00

+2.00

VEE

-5.20

-4.50

-3.20

-2.50

VHmeta

-1.15

+0.85

Vlmeta

-1.45

+0.55

+0.85

Results
~

An example of using a log MTBF versus Il.t piotto determine
is shown in Figure 10.

ECLinPS and ECLinPS Lite
OL140-Rev4

Motorola 10E431

125 psec

Motorola 10E151

185 psec

Motorola 10E131

200 psec

Motorola 10H131

718 psec

Signetics 100131

890 psec

Signetics 100151

1172 psec

National 100131

1594 psec

Having determined the value of~, the system designer can
use this information in conjunction with Equation 3 to aid in
optimizing the system design.

Example
As an example, assume the system configuration shown in
Figure 11, in which the output from System 1 is to be
synchronized to System 2 using a 10E151 D flip-flop.
Further, the equivalent output Signal for System 1 is 75 MHz
whereas the clock frequency for System 2, as well as the
synchronizing element, is 100 MHz. Under these conditions
the data and clock inputs to the D flip-flop are asynchronous
and the system designer must consider the possibility of the D
flip-flop entering the metastable state. Therefore the system
designer must determine how long the flip-flop will remain in
the metastable region in order to decide when the data at the
output of the flip-flop will attain a defined state and can be
clocked into System 2.

5-85

MOTOROLA

AN1504
The solution to this dilemma is found with Equation 3:

Thus for an MTBF of 5 years the designer should delay the
clocking of the data from the output of the flip-flop into System
2 by 3.63 nsec.

MTBF = 1/(2*fC*fD*Tp*lo-(dt)h)

Conclusion

The values for fc and fd were specified as 100 MHz and 75
MHz, respectively. Assuming the D flip-flop is a Motorola
1OE151 , a worse case value of propagation delay (Tp) of 800
psec is obtained from the ECLinPS Device Data Book. The
value of t is given in Table 2 as 185 psec. Substituting these
values into Equation 3 yields:

Metastability has become a critical issue with system
designers. In order to better serve our customers, Motorola
has characterized the ECLinPS family for metastability using
the concept of a failure window. The nominal flip-flop
resolution time constant for the ECLinPS family, excluding the
E131 and E431 devices as these flip-flops use alternative
architectures, has been determined to be 185 psec. The
resolution time constantfor the E131 and E431 devices is 200
psec and 125 psec, respectively. Thus the system designer
can use the value of 't in conjunction· with Equation 3 to
determine the metastable induced excess delay for a
specified MTBF. Although this application note does not
present a method for avoiding metastability, it does provide a
means for the designer to quantitatively incorporate
metastability in their designs.

MTBF = 1/(2*fC*fD*Tp*lo-(dV185 psec»
At this point the system designer must specify an
acceptable MTBF. For this example an MTBF of 5 years is
assumed. Therefore the value of dt is calculated to be
dt = 2.83 nsec
From the relationship

References

dt=TD-Tp

1 Stoll, P. "How to Avoid Synchronization Problems" VLSI
Design, November/December 1982. pp. 56-59.
2 Nootbaar, K. "Design, Testing, and Application of a
Metastable-Hardened flip-flop," Wescon/87, Section 16-2 pp.
1-9.

the value of TD is calculated to be
TD = 3.63 nsec

SYSTEM 1
75 MHz
SYSTEM 1
CLOCK

JUL

SYSTEM 1
OUTPUT

JL.SL

JUL

SYSTEM 2 INPUT

D·FUPFLOP

100MHz
SYSTEM 2
CLOCK

DATA

.--

SYSTEM 2

CLOCK

Figure 11. System Example

MOTOROLA

5-86

ECl,inPS and ECLinPS Lite
DL140-Rev4

AN1568
Application Note

Interfacing Between
LVDS and EeL

Prepared by

Andrea Diermeier
Motorola Logic Engineering

5/96

5-87

REV 0

MOTOROLA

AN1568

Interfacing Between lVDS and Eel
Introduction

lVDS levels

lVDS (low Voltage Differential Signaling) signals are
used to interface between today's CMOS or SiCMOS ASICs
supplied with 3.3V. lVDS signals are differential signals with
a swing of 250 to 400 mV and a DC offset of 1.2V. External
components are required for board to board data transfer or
clock distribution.
In advanced systems often only a single supply voltage
(3.3V) is available. low Voltage ECl devices work off this
3.3V supply voltage in the so called lVPECl mode.
InpuVOutput lVPECl levels are related to VCC 3.3V - a
750 mV output swing with 2V offset. This makes them ideal
as peripheral components for ASICs.
lVPECl and lVDS are both differential low voltage
Signals, but with different swing and different offset. The
purpose of this application information is to show the
interfacing between these signal levels. In addition it gives
interface suggestions to and from 5V supplied PECl devices
or negative supplied ECL.

The lVDS levels have been specified by IEEE (IEEE
un-approved Standard P1596.3). There are 2 different
specifications, the general purpose specification with 250 to
400 mV swing and the super low power specification with
reduced swing (150 ... 250mV).
lVDS outputs require a 1oon load between the differential
outputs. This load will in addition terminate the 50n
controlled impedance lines.
Z=50n

lOon

Figure 2. lVDS Output Definition

Eel levels
In ECl circuits all signal levels are related to VCC supply
rail. Traditional ECl designs are supplied with negative
voltages with VCC GND.
Today several applications use ECl devices in the PECl
mode. PECl - Positive ECl is nothing more than supplying
any ECl divide with a positive power supply (+5V).
With the trend to low voltage systems a new generation of
ECl circuitry has been developed. The low Voltage ECl
devices (lVECl) work from a 3.3V power supply either as
negative supplied or more popular from standard VCC
+3.3V and VEE GND as LVPECL.
100E(l) type output DC levels for the different supply
levels are shown in Table 2 on page 5-89.

--..rL.-IL.....

LVDS

Figure 1. Voltage levels

Table 1. LVDS Levels
General Purpose
Specification
Symbol

Parameter

Min

Max

Super Low Power
Specification
Min

Max

Unit

Condition

1374

RL= 100n

RL=1oon

RL=100n

Transmitter
VOH

Output HIGH Voltage

VOL

Output LOW Voltage

925

Vpp

Output Differential Voltage

250

400

VOS

Output Offset Voltage

1125

1275

Input Voltage Range

1474
1025
150

250

Receiver

Differential HIGH Input Threshold
Differential LOW Input Threshold

MOTOROLA

2400

+100
-100

-100

5-88

2000

Vgpd< 950mV

+100

VQod< 950mV

Vand< 950mV

ECLinPS and ECLinPS Lite
DL140-Rev4

AN1568

Table 2. MC100ExxxJMC100Elxx (TA

=0°-85°C)
lVPECl1

PECl2

ECl

Unit

VCC

+3.3

+5.0

GND

VEE

GND

-5.2, -4.5 or -3.3

Symbol

Parameter

VOH

Minimum Output HIGH Level

2.275

3.975

-1.030

VOH

Typical Output HIGH Level

2.345

4.045

-0.955

VOH

Maximum Output HIGH Level

2.420

4.120

-0.880

VOL

Minimum Output LOW Level

1.490

3.190

-1.810

VOL

Typical Output LOW Level

1.595

3.295

-1.705

Maximum Output LOW Level

1.680

3.380

-1.620

VOL
1. VCC assumed 3.3V. All levels vary 1:1 with Vcc.
2. VCC assumed 5V. All levels vary 1:1 with Vcc.
ECl outputs are open emitter outputs, requiring a DC path
to a more negative supply than VOL. This pull down resistor
termination can be used to terminate transmission lines
application specific.
ECl standard DC input levels are related to VCC. Several
devices are available with so called common mode range
inputs. These inputs allow to process signals with small
swings down to 200 mV, 150 mV or even 50 mV signal levels
within an offset range.

Interfacing

Several ECLinPS/ECLinPS Lite devices supply a VSS
(VSS ~ VCC-1.3V) reference voltage. It can been used for
differential capacitive coupling. VSS needs to be decoupled to
GND via a 10 nF capacitance.
The 100fill gives stable known behavior for all signal
conditions.

Capacitive Coupling LVDS to ECL with external biasing
If VSS reference voltage is not available a similar DC
voltage can be generated with a resistor divider. The resistor
values depend on VCcNEE voltages.

Vee

Common mode range inputs are capable to process
differential signals with 150 to 400 mV swing. The lVDS input
processes signals up to 950 mV swing. The DC voltage
levels should be within the input voltage range.
To interface between these 2 voltage levels capacitive
coupling can be used. Only clock or coded signals should be
capacitive coupled.

A capacitive coupling of NRZ signals will cause problems.
Then passive or active interfacing is necessary.

Capacitive Coupling lVDS to ECl
Capacitive Coupling LVDS to ECL using VBB

VEE

Figure 4. Capacitive Coupling lVDS to ECl with
External Biasing

Vee

Examples:
VCC = 5V, VEE = GND:
fill
VCC

=3.3V, VEE =GND:

R1 = 1.2 fill R2 = 3.4
R1

=680 n

=1kn.

In the layout for both interfaces the resistors and the
capacitors should be located as close as possible to the ECl
input.

Capacitive Coupling ECl to lVDS

10nF

Figure 3. Capacitive Coupling lVDS to ECl Using VBB

ECLinPS and ECLinPS Lite
DL140-Rev4

The ECl output requires a DC path. The pulldown
resistors are connected to VEE.
The thevenin resistor pair represent the termination of the
transmission line Z Rl II R2 and generates a DC level of
1.2V.

5-89

MOTOROLA

AN1568
3.3V

Interfacing LVPECL to LVDS in thevenin equation
3.3V

3.3V

Z=500

Figure 5. Capacitive Coupling LVDS to ECL

Capacitive Coupling ECL to LVDS using VOS reference
voltage
Some devices with lVDS interfaces supply Vas reference
voltage. This can be used for capacitive coupling. Beside the
transmission line length is very short, a parallel termination
should be used and placed as close as possible to the
coupling capacitors.
3.3V

Figure 7. Interfacing LVPECL to LVDS in
Thevenin Equation
The thevenin equation resistors terminate the
transmission line Z near the receiver (parallel termination).
Instead of a resistor to VEE, a resistive path to VCC and to VEE
(GND) build the termination of the transmission line. In
transmission line theory these resistors are in parallel for high
frequency signals. They match the line characteristic
impedance.
Rl II (R2 + R3) = Z
Equation 1
The DC condition for point A is VCC - 2V. The DC levels at
the lVDS input (B) are located within the lVDS input
common mode range.
A:
Rl/(RI + R2 + R3)= 2 VNCC
Equation 2
B:

R3/(RI + R2 + R3) = VILNcc

Equation 3

The swing at the lVDS input is decreased dependent on
R2 and R3
Vipp = R3/(R2 + R3) • Vopp
VIH < 2.0 V (2.4 V)
Figure 6. Capacitive Coupling LVDS to ECL Using VOS
Reference Voltage

Interfacing from LVPECL to LVDS
The DC output level of lVPECl is more positive than the
input range of lVDS. All ECl devices need pulldown
resistors. The pulldown resistors in a thevenin equation or
pulldown resistors to GND can be split up into a resistor
divider to generate lVDS levels.
Dependent on the application one of the following
interfaces should be used:

MOTOROLA

Vll>OV
Calculations give non-standard resistor values. When
choosing resistors off the shelf it should be considered to
avoid a cutoff condition also under worst case supply voltage.

Example:
For 500 controlled impedance lines Rl = 1200, R2 =330
and R3=51O.
For any other controlled impedance line the calculation of
the resistive divider is done according to Equation 1,
Equation 2 and Equation 3.

5-90

ECLinPS and ECLinPS Lile
DL140-Rev4

AN1568
Interlacing LVPECL to LVDS with unterminated
transmission line
Unterminated lines can be used for very short
interconnects. For details about recommended maximum
unterminated line length, see Motorola's High Performance
EeL Data Book (DL 140/D). chapter 4 "System
Interconnects".

Interfacing from PECl to lVDS
Interlacing from PECL to LVDS using thevenln parallel
termination
As described for LVPECL to interface from PECL to LVDS
a thevenin equation termination is used.
Near the receiver a +5V power supply connection is
required.

3.3V

VCC=SV

::-

Figure 8. Interfacing LVPECL to LVDS with
Unterminated Transmission Lines
The resistive divider reduces the offset of the signal to be
processed by LVDS.
For example the following resistor values can be used:
R1
56n
R2 = 82n
Parallel termination to GND is possible with a impedance
matching resistor pair (R1 + R2 = Z) using the Figure 8.
Unfortunately this low impedance path causes a high output
current. This will increase the device's power consumption.
The increased die temperature has a negative impact on the
statistic life time of the device.
Please Note: The maximum ratings of the output current
may not be violated.

Figure 10. Interfacing from PECL to LVDS Using
Thevenin Equivalent Parallel Termination

R1 II (R2 + R3) = Z

Equation 4

The DC termination level at A is VCC - 2V. The DC level of
B should be within the LVDS input common mode range.

Interfacing from lVDS to lVPECl

R1/(R1 + R2 + R3)= 2 VNCC

Equation 5

R3/(R1 + R2 + R3) = VILNCC

Equation 6

The swing at the LVDS input is decreased dependent on
R2 and R3
Vipp = R3/(R2 + R3) • Vopp

The common mode range inputs of the low voltage ECL
line receivers are defined wide enough to process LVDS
signals.
3.3V

::-

VIH < 2.0 V (2.4 V)

3.3V

VIL> OV
Calculations give non. standard resistor values. When
choosing resistors off the shelf it should be considered to
avoid a cutoff condition also under worst case condition.
If a 50n controlled impedance line is used the following
resistor values are useful:

::-

Examples:
Z= 50n
or
Z';50n

::-

Figure 9. Interfacing LVDS to LVPECL
This direct interface is possible for all LVELxx devices with
differential common mode range inputs, e.g. MC100LVEL 17,
MC1 OOLVEL 13, MC1 OOLVEL 14, MC100LVEL29,
MC100LVEL39.

ECLinPS and ECLinPS Lile
DL140-Rev4

R1 = 82n

R2 = 100n

R3 = 33Q

R1 =82n

R2=82n

R3=47n

For any other controlled impedance line the calculation of
the resistive divider is done according to Equation 4,
Equation 5 and Equation 6.

5-91

MOTOROLA

AN1568
Interfacing from PEeL to LVDS with untermlnated lines

Interfacing from lVDS to PECl

As described in LVPECL interfacing unterminated lines
can be used for very short interconnections.
E.g. the resistors can be R1 = 330n, R2 = 1S0n.

To translate LVDS signals to PECL a differential LVE Lite
device with extended common mode range inputs (e.g.
MC100EL17) can be used to process and translate LVDS
signals when supplied with SV ± S% supply voltage.

3.3V

5V±5%

Figure 12. Interfacing from lVDS to PEel

Figure 11. Interfacing from PEeL to lVDS with
Untermlnated lines
3.3V

3.3V

Intertace
LVPECL to LVDS

Figure 13. Interfacing from Negative Supplied Eel to lVDS

Figure 14. Interfacing from lVDS to Negative Supplied Eel

Interfacing Between Negative Supplied ECl
and lVDS
Motorola has developed level translators to interface
between the different ECL levels. The MC100LVEUEL90
translates from negative supplied ECL to LVPECL. The
interface from LVPECL to LVDS inputs is done as described
above. For -4.S/-5.2V power supplies the MC100EL90 is

MOTOROLA

used, for -3.3V supplies the MC100LVEL90.
To interface from LVDS to negative supplied ECL the
common mode range of the MC1 OOLVEL91 for -3.3V supply
and the MC1 OOEL91 for -4.S/-S.2V supply is wide enough to
process LVDS signals.

If a +SV supply and a VEE -S.2V ± S% supply is available
the MC10E16S1 can be used.

5-92

ECLinPS and ECLinPS Lite
DL140-Rev4

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MOTOROLA
DL140/D

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