1996_Motorola_High Speed_CMOS_Data 1996 Motorola High Speed CMOS Data

User Manual: 1996_Motorola_High-Speed_CMOS_Data

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®
®

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DL 129/D

MOTOROLA

REV6

High-Speed CMOS Data

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Q2I96
DL129
REV6

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High-Speed CMOS Data

~-i':CE:l\._t;~CJ'"

Function Selector Guide

[IJ

Design Considerations

[2J

Device Data Sheets

[j]

Ordering Information

~

WHAT'S NEW!
DATA SHEETS ADDED

DATASHEETS DELETED

MC74HCU04A

MC54174HC390A

MC54174HC08

MC54174HCT541

MC74HC76

MC54174HC393A

MC54174HC540

MC74HC4020
MC54174HC4040

MC54174HC86A

MC54174HC533A

MC54174HCT540

MC54174HC158

MC54174HC541A

MC54174HC541

MC74HC158A

MC74HCT541A

MC54174HCT161A

MC74HC589A

MC54174HCT163A

MC54174HC597A

MC54174HC164A

MC54174HC4016A

MC54174HC165A

MC74HC4020A

MC54174HC175A

MC54174HC4040A

MC74HC242

MC54174HC4060A

MC54174HC259A

MC74HC4316A

MC54174HC354

MC74HC7266A

NEW INPUT STRUCTURE
As part of Motorola's continuous improvement plan, many of our High-Speed CMOS devices are being redesigned to improve ESD performance.
To maximize the performance with all test models, machine, human body, and charged device; the poly resistor was removed from all device
inputs. This requires that the maximum voltage rating be changed from -1.5V->Vee+1.5V to -Q.5V->Vce+O.5V. The recommended operating
voltage range remains unchanged at OV to Vee. Devices with this structure have their changes reflected on their individual data sheets. Additional
devices will be changed over the next 1-2 years. Motorola's official "Product Change Notification" procedure will be utilized prior to the release of
all modified device types.

9-Wide and Nine-Wide are trademarks of Motorola, Inc.
All other brand names and product names appearing in this publication are registered trademarks or trademarks of their respective holders.

®

MOTOROLA

High-Speed CMOS Data
This book presents technical data for the broad line of High-Speed Logic integrated circuits. Complete
specifications are provided in the form of data sheets. In addition, a comprehensive Function Selector
Guide and a Design Considerations chapter have been included to familiarize the user with these logic
circuits.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes
no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical"
parameters can and do vary in different applications. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Motorola product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products
for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

®

Series D
© Motorola, Inc. 1996
Previous Edition ©Q2/1993
"All Rights Reserved"

Printed in U.S.A.

iii

Table of Contents
Chapter 1. Function Selector Guide

HC and HCT Dynamic Power Dissipation ...
Thermal Management ......................
Capacitive Loading Effects on
Propagation Delay .........................
Temperature Effects on DC and AC
Parameters ...............................
Supply Voltage Effects on Drive Current
and Propagation Delay ......................
Decoupling Capacitors ......................
Interfacing ................................
Typical Parametric Values ...................
Reduction of Electromagnetic
Interference (EMI) ..........................
Hybrid Circuit Guidelines ....................
Schmitt-Trigger Devices ....................
Oscillator Design with High-Speed CMOS .....
RC Oscillators ..........................
Crystal Oscillators .......................
Printed Circuit Board Layout .................
Definitions and Glossary of Terms ...... : ...
HC vs. HCT ............................
"A" versus "Non-A" ......................
Glossary of Terms .......................
Applications Assistance Form .............

Alphanumeric Index ........................ 1-2
Buffers/Inverters ............................ 1-5
Gates ..................................... 1-7
Schmitt Triggers ............................ 1-9
Bus Transceivers ........................... 1-9
Latches ................................... 1-10
Flip-Flops ................................. 1-11
Digital Data Selectors/Multiplexers ............ 1-13
Decoders/Demultiplexers/Display Drivers ...... 1-14
Analog Switches/Multiplexers/
Demultiplexers ............................. 1-16
Shift Registers ............................. 1-18
Counters .................................. 1-19
Miscellaneous ............................. 1-20

Chapter 2. Design Considerations
Introduction ................................ 2-2
Handling Precautions ................... : .... 2-2
Power Supply Sizing ......................... 2-6
Battery Systems. . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
CPO Power Calculation ................... 2-7
Inputs ..................................... 2-8
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
3-State Outputs ......................... 2-12
Open-Drain Outputs ..................... 2-12
InpuVOutput Pins ........................ 2-12
Bus Termination ......................... 2-13
Transmission Line Termination ............ 2-14
CMOS Latch Up ........................... 2-14
Maximum Power Dissipation ................. 2-16
HC Quiescent Power Dissipation .......... 2-16
HCT Quiescent Power Dissipation ......... 2-16

2-16
2-17
2-19
2-20
2-20
2-21
2-21
2-23
2-24
2-24
2-25
2-26
2-26
2-26
2-27
2-28
2-28
2-28
2-28
2-30

Chapter 3. Device Datasheets
........................................... 3-1

Chapter 4. Ordering Information
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . .. 4-2
Case Outlines ............................. 4-2
Motorola Distributors and Worldwide
Sales Offices .............................. 4-14

iv

High-Speed CMOS Data

Function Selector Guide

CONTENTS
Alphanumeric Index ...................... 1-2
Buffers/Inverters .......................... 1-5
Gates .................................... 1-7
Schmitt Triggers ........................... 1-9
Bus Transceivers .......................... 1-9
Latches ................................. 1-10
Flip-Flops ............................... 1-11
Digital Data Selectors/Multiplexers .......... 1-13
Decoders/Demultiplexers/Display Drivers .... 1-14
Analog Switches/Multiplexers/
Demultiplexers ........................... 1-16
Shift Registers ........................... 1-18
Counters ................................ 1-19
Miscellaneous ........................... 1-20

High-Speed CMOS Logic Data

DL129-Rev6

1-1

MOTOROLA

[1J

Function Selector Guide

ALPHANUMERIC INDEX
Page

Device Number
MC541MC74

[1J

MC54174HCOOA
MC54174HCTOOA
MC54174HC02A
MC74HC03A
MC54174HC04A
MC74HCT04A
MC74HCU04
MC74HCU04A
MC54174HC08A
MC54174HCT08A
MC74HC10
MC74HC11
MC54174HC14A
MC5417 4HCT14A
MC74HC20
MC54174HC27
MC74HC30
MC54174HC32A
MC54174HCT32A
MC74HC42
MC74HC51
MC74HC58
MC74HC73
MC54174HC74A
MC74HCT74A
MC74HC75
MC74HC76
MC74HC85
MC54174HC86
MC54174HC86A
MC74HC107
MC74HC109
MC74HC112
MC74HC125A
MC74HC126A
MC54174HC132A
MC74HC133
MC74HC137
MC54174HC138A
MC74HCT138A
MC54174HC139A
MC74HC147
MC74HC151
MC74HC153
MC54174HC154
MC54174HC157A
MC74HCT157A
MC54174HC158
MC74HC158A
MC54174HC160

MOTOROLA

Function

Number

Quad 2-lnput NAND Gate ....................................................... .
Quad 2-lnput NAND Gate ....................................................... .
Quad 2-lnput NOR Gate ........................................................ .
Quad 2-lnput NAND Gate With Open-Drain Outputs ............................... .
Hex Inverter ................................................................... .
Hex Inverter ................................................................... .
Hex Unbuffered Inverter ......................................................... .
Hex Unbuffered Inverter ....................................................... : ..
Quad 2-lnput AND Gate ........................................................ .
Quad 2-lnput AND Gate ........................................................ .
Triple 3-lnput NAND Gate ....................................................... .
Triple 3-ll1put AND Gate ........................................................ .
Hex Schmitt Trigger Inverter ..................................................... .
Hex Schmitt Trigger Inverter ..................................................... .
Dual 4-lnput NAND Gate ....................................................... .
Triple 3-lnput NOR Gate ........................................................ .
B-Input NAND Gate ............................................................ .
Quad 2-lnput OR Gate ......................................................... .
Quad 2-lnput OR Gate ......................................................... .
1--01-10 Decoder ............................................................... .
2-Wide, 2-lnpuV2-Wide, 3-lnput AND-NOR Gate ................................. .
2-Wide, 2-lnpuV2-Wide, 3-lnput AND-OR Gate ................................... .
Dual J-K Flip-Flop With Reset ................................................... .
Dual D Flip-Flop With Set and Reset ............................................. .
Dual D Flip-Flop With Set and Reset ............................................. .
Dual 2-Bit Transparent Latch .................................................... .
Dual J-K Flip-Flop With Set and Reset ........................................... .
4-Bit Magnitude Comparator .................................................... .
Quad 2-lnput Exclusive OR Gate ................................................ .
Quad 2-lnput Exclusive OR Gate ................................................ .
Dual J-K Flip-Flop With Reset ................................................... .
Dual J-K(bar) Flip-Flop With Set and Reset ....................................... .
Dual J-K Flip-Flop With Set and Reset ........................................... .
Quad With 3-State Outputs Non-Inverting Buffer ................................... .
Quad With 3-State Outputs Non-Inverting Buffer ................................... .
Quad 2-lnput NAND Gate With Schmitt Trigger Inputs .............................. .
13-lnput NAND Gate ........................................................... .
1-01-8 Decoder/Demultiplexer With Address Latch ................................. .
1-01-8 Decoder/Demultiplexer ................................................... .
1-01-8 Decoder/Demultiplexer ................................................... .
Dual 1--01-4 Decoder/Demultiplexer .............................................. .
Decimal-ta-BCD Encoder ....................................................... .
B-Input Data Selector/Multiplexer ................................................ .
Dual 4-lnput Data Selector/Multiplexer ............................................ .
1--01-16 Decoder/Demultiplexer .................................................. .
Quad 2-lnput Data Selector/Multiplexer ........................................... .
Quad 2-lnput Data Selector/Multiplexer ........................................... .
Quad 2-lnput Data Selector/Multiplexer ........................................... .
Quad 2-lnput Data Selector/Multiplexer ........................................... .
Presettable Counter ............................................................ .

1-2

3-2

3-6
3-9
3-12
3-16
3-20
3-24
3-28
3-33
3-37

3-40
3-43
3-46
3-51
3-54
3-57
3--60
3--63
3--67
3-70
3-74

3-77
3-80
3-84
3-88
3-92
3-96
3-100
3-106
3-109
3-113
3-117
3-121
3-125
3-125
3-129
3-133
3-136
3-141
3-146
3-150
3-154
3-158
3-163
3-167
3-172
3-176
3-180
3-184
3-189

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide
ALPHANUMER~INDEX
Device Number
MC54IMC74
MC54174HC162
MC54174HC161A
MC54174HC163A
MC54174HCT161A
MC54174HCT163A
MC54174HC164
MC54174HC164A
MC54174HC165
MC54174HC165A
MC74HC173
MC54174HC174A
MC74HCT174A
MC54174HC175
MC54174HC175A
MC74HC194
MC74HC195
MC74HC237
MC54174HC240A
MC74HCT240A
MC54174HC241A
MC54174HCT241 A
MC74HC242
MC54174HC244A
MC54174HCT244A
MC54174HC245A
MC54174HCT245A
MC54174HC251
MC74HC253
MC74HC257
MC54174HC259
MC54174HC259A
MC54174HC273A
MC74HCT273A
MC74HC280
MC74HC299
MC54174HC354
MC54174HC365
MC54174HC366
MC54174HC367
MC74HC368
MC54174HC373A
MC54174HCT373A
MC54174HC374A
MC54174HCT374A
MC54174HC390
MC54174HC390A
MC54174HC393
MC54174HC393A
MC54174HC533A
MC54174HC534A

Function
Presettable Counter ............................................................ .
Presettable Counter ............................................................ .
Presettable Counter ............................................................ .
Presettable Counter ............................................................ .
Presettable Counter ............................................................ .
B-Bit Serial-lnpuVParaliel-Output Shift Register ................................... .
B-Bit Serial-lnpuVParaliel-Output Shift Register ................................... .
B-Bit Serial or Paraliel-lnpuVSerial-Output Shift Register ............................ .
B-Bit Serial or Paraliel-lnpuVSerial-Output Shift Register ............................ .
Quad With 3-State Outputs D Flip-Flop With Common Clock & Reset ................. .
Hex D Flip-Flop With Common Clock & Reset ..................................... .
Hex D Flip-Flop With Common Clock & Reset ...................................... .
Quad D Flip-Flop With Common Clock & Reset .................................... .
Quad D Flip-Flop With Common Clock & Reset .................................... .
4-Bit Bidirectional Universal Shift Register ............................ : ............ .
4-Bit Universal Shift Register .................................................... .
1-01-8 Decoder/Demultiplexer With Address Latch ................................. .
Octal With 3-State Outputs Inverting Buffer/Line Driver/line Receiver .................. .
Octal With 3--State Outputs Inverting Buffer/Line Driver/line Receiver .................. .
Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line Receiver ............ .
Octal With 3--State Outputs Non-Inverting Buffer/Line Driver/Line Receiver ............ .
Quad With 3--State Outputs Inverting Bus Transceiver ............................... .
Octal With 3--State Outputs Non-Inverting Buffer/Line Driver/Line Receiver ............ .
Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line Receiver ............ .
Octal With 3--State Outputs Non-Inverting Bus Transceiver .......................... .
Octal With 3--State Outputs Non-Inverting Bus Transceiver .......................... .
B-Input Data Selector/Multiplexer With 3--State Outputs ............................. .
Dual 4-lnput Data Selector/Multiplexer With 3-8tate Outputs ........................ .
Quad 2-lnput Data Selector/Multiplexer With 3-8tate Outputs ........................ .
B-Bit Addressable Latch/1-o1-8 Decoder .......................................... .
B-Bit Addressable Latchl1-o1-8 Decoder .......................................... .
Octal D Flip-Flop With Common Clock & Reset .................................... .
Octal D Flip-Flop With Common Clock & Reset .................................... .
9-Bit Odd/Even Parity Generator/Checker ......................................... .
B-Bit Bidirectional Universal Shift Register With parallel 110 .......................... .
B-Input Data Selector/Multiplexer With Data and Address Latches, 3--State Outputs ..... .
Hex With 3-State Outputs Non-Inverting Buffer With Separate 2-BiV4-Bit Sections ..... .
Hex With 3--State Outputs Inverting Buffer With Common Enables .................... .
Hex With 3--State Outputs Non-Inverting Buffer With Separate 2-Bit and 4-Bit Sections ..
Hex With 3-State Outputs Inverting Buffer With Separate 2-Bit and 4-Bit Sections ..... .
Octal With 3-8tate Outputs Non-Inverting Transparent Latch ........................ .
Octal With 3-8tate Outputs Non-Inverting Transparent Latch ........................ .
Octal With 3-State Outputs Non-Inverting D Flip-Flop .............................. .
Octal With 3-8tate Outputs Non-Inverting D Flip-Flop .............................. .
Dual 4-Stage Binary Ripple Counter W +2, +5 Sections ............................. .
Dual 4-Stage Binary Ripple Counter W +2, +5 Sections ............................. .
Dual 4-Stage Binary Ripple Counter .............................................. .
Dual 4-Stage Binary Ripple Counter .............................................. .
Octal 3--State Inverting D Flip-Flop ............................................... .
Octal With 3--State Outputs Inverting D Flip-Flop ................................... .

High-Speed CMOS Logic Data
DL129-Rev6

1-3

Page
Number
3-189
3--200
3-200
3-211
3-211
3-221
3-226
3-232
3-238
3-245
3-250
3--254
3-258
3--263
3-269
3-275
3-281
3-286
3-291
3--295
3--300
3--304
3--308
3--312
3--316
3-320
3--325
3-330
3-334
3-339
3-344
3-350
3-355
3-359
3--364
3-371
3--378
3--382
3--386
3--390
3--394
3--399
3--404
3--408
3--412
3--418
3--425
3--430
3--436
3--441

MOTOROLA

[I]

Function Selector Guide

ALPHANUMERIC INDEX
Page

Device Number
MC54/MC74

[1]

MC74HC540A
MC54174HC541A
MC74HCT541 A
MC54174HC563
MC74HC564
MC54174HC573A
MC74HCT573A
MC5417 4HC574A
MC54174HCT574A
MC54174HC589
MC54174HC589A
MC54174HC595A
MC54174HC597
MC5417 4HC597A
MC5417 4HC640A
MC54/74HC646
MC54174HC688
MC74HC4002
MC54174HC4016
MC54174HC4016A
MC74HC4017
MC74HC4020A
MC74HC4024
MC54174HC4040A
MC74HC4046A
MC54174HC4049
MC5417 4HC4050
MC54174HC4051
MC74HC4052
MC54174HC4053
MC54174HC4060
MC5417 4HC4060A
MC54174HC4066
MC5417 4HC4066A
MC74HC4075
MC74HC4078
MC74HC4316
MC74HC4316A
MC54174HC4351
MC54174HC4353
MC74HC4511
MC74HC4514
MC54174HC4538A
MC74HC7266
MC74HC7266A

MOTOROLA

Function

Number

Octal With 3-State Outputs Inverting Buffer/Line Driver/Line Receiver ................ ; .
Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line Receiver ............ .
Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line Receiver ............ .
Octal With 3-State Outputs Inverting Transparent Latch ............................. .
Octal With 3-State Outputs Inverting D Flip-Flop ................................... .
Octal With 3-State Outputs Non-Inverting Transparent Latch ........................ .
Octal With 3-State Outputs Non-Inverting Transparent Latch ........... , ............ .
Octal With 3-State Outputs Non-Inverting D Flip-Flop .............................. .
Octal With 3-State Outputs Non-Inverting D Flip-Flop .............................. .
8-Bit Serial or Parallel-Input/Serial-Output Shift Register With 3-State Outputs ........ .
8-Bit Serial or Parallel-Input/Serial-Output Shift Register With 3-8tate Outputs ........ .
8-Bit Serial-Input/Serial or Parallel-Output Shift Register With Latched 3-State Outputs ..
8-Bit Serial or Parallel-Input/Serial-Output Shift Register With Input Latch ............. .
8-Bit Serial or Parallel-Input/Serial-Output Shift Register With Input Latch ............. .
Octal With 3-8tate Outputs Inverting Bus Transceiver ............ '................... .
Octal With 3-State Outputs Non-Inverting Bus Transceiver & D Flip-Flop ............. .
8-Bit Equality Comparator ....................................................... .
Dual 4-lnput NOR Gate ................ , ........................................ .
Quad Analog Switch/Multiplexer/Demultiplexer ......... , ........................... .
Quad Analog Switch/Multiplexer/Demultiplexer ..............' ................ , ...... .
Decade Counter .................. , ............................................ .
14-8tage Binary Ripple Counter ................................................. .
7-Stage Binary Ripple Counter .... , ... , ................................ , ........ .
12-8tage Binary Ripple Counter ................................................. .
Phase-Locked-Loop With VCO .................................................. .
Hex Inverting Buffer/Logic-Level Down Converter .................................. .
Hex Non-Inverting Buffer/Logic-Level Down Converter ............................. .
8-Channel Analog Multiplexer/Demultiplexer .......... , ............................ .
Dual 4-Channel Analog Multiplexer/Demultiplexer .................................. .
Triple 2-Channel Analog Multiplexer/Demultiplexer .. , .............................. .
14-Stage Binary Ripple Counter With Oscillator ...... , ............................. .
14-Stage Binary Ripple Counter With Oscillator .................................... .
Quad Analog Switch/Multiplexer/Demultiplexer ..................................... .
Quad Analog Switch/Multiplexer/Demultiplexer '................................ : .... .
Triple 3-lnput OR Gate ......................................................... .
8-lnput NOR/OR Gate .......................................................... .
Quad Analog Switch/Multiplexer/Demultiplexer With Separate Analog/
Digital Power Supplies .......................................................... .
Quad Analog Switch/Multiplexer/Demultiplexer With Separate Analog/
Digital Pow~r Supplies ........, .................................................. .
8-Channel Analog Multiplexer/Demultiplexer With Address Latch ..................... .
Triple 2-Channel Analog Multiplexer/Demultiplexer With Address Latch ............... .
BCD-to-7 Segment Latch/Decoder/Display Driver .................................. .
1-01-16 Decoder/Demultiplexer With Address Latch ............................... , .
Dual Precision Monostable Multivibrator Retriggerable, Resetlable) ................... .
Quad 2-lnput Exclusive NOR Gate ............................................... .
Quad 2-lnput Exclusive NOR Gate ............................................... .

1-4

3-445
3-449
3-453
3-457
3-462
3-467
3-471
3-475
3-479
3-483
3-491
3-500
3-508
3-515
3-524
3-528
3-540
3-544
3-547
3-556
3-565
3-573
3-579
3-584
3-590
3-611
3-611
3-615
3-615
3-615
3-627
3-635
3-644
3-653
3-662
3-665
3-669
3-678
3-687
3-687
3-698
3-706
3-714
3-725
3-729

High-Speed CMOS Logic Data
DL129-Rev6'

Function Selector Guide

BUFFERSIINVERTERS
Device
Number
MC54/MC74

Function

HC04A
HCT04A
HCU04
HCU04A
HC14A
HCT14A

Hex Inverter
Hex Inverter with LSTTL-Compatible Inputs
Hex Unbuffered Inverter
Hex Unbuffered Inverter
Hex Schmitt-Trigger Inverter
Hex Schmitt-Trigger Inverter with LSTTL-Compatible
Inputs

HC125A
HC126A
HC240A
HCT240A

Quad 3-State Noninverting Buffer
Quad 3-State Noninverting Buffer
Octal 3-State Inverting Buffer/Line Driver/Line Receiver
Octal 3-State Inverting Buffer/Line Driver/Line Receiver
with LSTTL-Compatible Inputs
Octal 3-State Noninverting Buffer/Line Driver/Line
Receiver

HC241A
HCT241A
HC244A
HCT244A
HC245A
HCT245A

HC365
HC366
HC367
HC368
HC540A
HC541A
HCT541A
HC640A
HC4049
HC4050

Octal 3-8tate Noninverting Buffer/Line Driver/Line
Receiver with LSTTL-Compatible Inputs
Octal 3-8tate Noninverting Buffer/Line Driver/Line
Receiver
Octal 3-8tate Noninverting Buffer/Line Driver/Line
Receiver with LSTTL-Compatible Inputs
Octal 3-State Noninverting Bus Transceiver
Octal 3-8tate Noninverting Bus Transceiver with
LSTTL-Compatible Inputs
Hex 3-8tate Noninverting Buffer with Common Enables
Hex 3-State Inverting Buffer with Common Enables
Hex 3-State Noninverting Buffer with Separate 2-Bit and
4-Bit Sections
Hex 3-State Inverting Buffer with Separate 2-Bit and
4-Bit Sections
Octal 3-State Inverting Buffer/Line Driver/Line Receiver
Octal 3-State Noninverting Buffer/Line Driver/Line
Receiver
Octal 3-State Noninverting Buffer/Line Driver/Line
Receiver with LSTTL-Compatible Inputs
Octal 3-8tate Inverting Bus Transceiver
Hex Inverting Buffer/Logic-Level Down Converter
Hex Noninverting Buffer/Logic-Level Down Converter

High-Speed CMOS Logic Data
DL129-Rev6

1-5

Functional
Equivalent
LSTTL
Device
54n4

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

Number
of
Pins

LS04
LS04
LS04
LS04
LS14
LS14

'4069
'4069
4069
4069
4584
4584

LS/CMOS
LS/CMOS
LS/CMOS
LS/CMOS
LS/CMOS
LS/CMOS

14
14
14
14
14
14

LSI25,LSI25A
LSI26,LSI26A
LS240
LS240

LS
LS
LS
LS

14
14
20
20

LS241

LS

20

LS241

LS

20

LS244

LS

20

LS244

LS

20

LS245
LS245

LS
LS

20
20

LS365,LS365A
LS366,LS366A
LS367,LS367A

LS
LS
LS/CMOS

16
16
16

LS368,LS368A

LS

16

LS540

LS

20

LS541

LS

20

LS541

LS

20

LS
CMOS
CMOS

20
16
16

4503

LS640
4049
4050

MOTOROLA

Function Selector Guide

BUFFERS/INVERTERS (Continued)
HC Devices Have CMOS-Compatible Inputs. HCT Devices Have LSTIL-Compatible Inputs.

Device

# Pins
Quad Device
Hex Device
Octal Device
Nine-Wide Device
Noninverting Outputs
Inverting Outputs
Single Stage (unbuffered)

HC
HCT
04A

HCU
04

HCU
04A

HC
14A

HC
125A

HC
126A

HC
HCT
240A

HC
HCT
241A

HC
HCT
244A

HC
HCT
245A

14

14

14

14

14

14

20

20

20

20

•

•

•

•

•

•
•

•

•

•

•

•
•

•
•

•

•

•

•

•
•
•
•
•

•
•
•
•

•
•
•

•

•

•

•

•

•

Schmitt Trigger
3-State Outputs
Open-Drain Outputs
Common Output Enables
Active-Low Output Enables
Active-High Output Enables
Separate 4-Bit Sections
Separate 2-Bit and 4-Bit Sections

•

•
•
•
•

•

•
•

Transceiver
Direction Control
Logic-Level Down Converter

HC Devices Have CMOS-Compatible Inputs. HCT Devices Have LSTIL-Compatible Inputs.

Device

# Pins
Quad Device
Hex Device
Octal Device
Nine-Wide Device
Noninverting Outputs
Inverting Outputs

HC
365

HC
366

HC
367

HC
368

HC
540A

HC
HCT
541 A

HC
640A

HC
4049

HC
4050

16

16

16

16

20

20

20

16

16

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•
•
•

•

•

•

•

•

•

Single Stage (unbuffered)
Schmitt Trigger
3-State Outputs
Open-Drain Outputs
Common Output Enables
Active-Low Output Enables
Active-High Output Enables
Separate 4-Bit Sections
Separate 2-Bit and 4-Bit Sections
Transceiver
Direction Control
Logic-Level Down Converter

MOTOROLA

•
•
•

•
•
•

•
•
•

•
•
•
•
•
•

•

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide

GATES

Device
Number
MC54/MC74

Function

54n4

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

HCOOA
HCTOOA
HC02A
HC03A
HCOBA

Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate with LSTTL-Compatible Inputs
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate with Open-Drain Outputs
Quad 2-lnput AND Gate

LSOO
LSOO
LS02
LS03
LS08

4011
4001
4001
'4011
4081

LS
LS
LS
LS
LS

14
14
14
14
14

HCT08A
HC10
HC11
HC20
HC27

Quad 2-lnput AND Gate with LSTTL-Compatible Inputs
Triple 3-lnput NAND Gate
Triple 3-lnput AND Gate
Dual 4-lnput NAND Gate
Triple 3-lnput NOR Gate

LS08
LS10
LS11
LS20
LS27

4081
4023
4073
4012
4025

LS
LS
LS
LS
LS

14
14
14
14
14

HC30
HC32A
HCT32A
HC51
*HC58

8-lnput NAND Gate
Quad 2-lnput OR Gate
Quad 2-lnput OR Gate with LSTTL-Compatible Inputs
2-Wide, 2-lnpuV2-Wide, 3-lnput AND-NOR Gates
2-Wide, 2-lnpuV2-Wide, 3-lnput AND-OR Gates

LS30
LS32
LS32
LS51

4068
4071
4071
'4506
'4506

LS
LS
LS
LS

14
14
14
14
14

HC861A
HC132A
HC133
HC4002
HC4075

Quad 2-lnput Exclusive OR Gate
Quad 2-lnput NAND Gate with Schmilt-Trigger Inputs
13-lnput NAND Gate
Dual 4-lnput NOR Gate
Triple 3-lnput OR Gate

LS86
LS132
LS133
'LS25

4070
4093

LS
LS

4002
4075

CMOS
CMOS

14
14
16
14
14

4078
4077

CMOS
LS/CMOS

14
14

HC4078
*HC7266/A

Functional
Equivalent
LSTTL
Device

B-Input NOR/OR Gate
Quad 2-input Exclusive NOR Gate

'LS266

Direct Pin
Compatibility

Number
of
Pins

U3

• Suggested alternative
* Exclusive High-Speed CMOS design

High-Speed CMOS Logic Data
DL129-Rev6

1-7

MOTOROLA

Function Selector Guide

GATES (Continued)
HC Devices Have CMOS-Compatible Inputs.

Device

# Pins

HC
HCT
OOA

HC
02A
. 14

14

Single Device
Dual Device
Triple Device
Quad Device
NAND
NOR
AND
OR

•
•

•

HC
03A

HC
HCT
08A

HC
10

HC
11

HC
20

HC
27

HC
30

HC
HCT
32A

14

14

14

14

14

14

14

14

•
•

•

•

•

•

•

•

•

•

•

•

•

•

•
•
•

Exclusive OR
Exclusive NOR
AND-NOR
AND-QR

•

2-lnput
3-lnput
4-lnput
8-lnput
13-lnput

•

•

•

•

•

•

•

•

•

Schmitt-Trigger Inputs

•

Open-Drain Outputs

HC Devices Have CMOS-Compatible Inputs.
Device

# Pins
Single Device
Dual Device
Triple Device
Quad Device

HC
51

HC
58

HC
861A

HC
132A

HC
133

HC
4002

HC
4075

HC
4078

HC
72661A

14

14

14

14

16

14

14

14

14

•

•

•
•

•
•

NAND
NOR
AND
OR
Exclusive OR
Exclusive NOR
AND-NOR
AND-oR
2-lnput
3-lnput
4-lnput
8-lnput
13-lnput

•

•

•
•

•
•

•
•
•

•
•
•

•

•

•
•

•

•

•
•

•

•

•
•

•

Schmitt-Trigger Inputs
Open-Drain Outputs

MOTOROLA

1-8

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide

SCHMITT TRIGGERS

Device
Number
MC541MC74
HC14A
HCT14A
HC132A

54n4

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

Number
of
Pins

LS14
LS14

4584
4584

LS/CMOS
LS

14
14

LS132

4093

LS

14

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

Number
of
Pins

Functional
Equivalent
LSTTL
Device
Function
Hex Schmitt-Trigger Inverter
Hex Schmitt-Trigger Inverter with LSTTL-Compatible
Inputs
Quad 2-lnput NAND Gate with Schmitt-Trigger Inputs

BUS TRANSCEIVERS
Functional
Equivalent
LSTTL
Device

Device
Number
MC54/MC74
HC245A
HCT245A
HC640A
HC646

54n4

Function
Octal 3-State Noninverting Bus Transceiver
Octal 3-State Noninverting Bus Transceiver, with
LSTTL-Compatible Inputs
Octal 3-State Inverting Bus Transceiver
Octal 3-State Noninverting Bus Transceiver and
D Flip-Flop

LS245
LS245

LS
LS

20 ..
20

LS640
LS646

LS
LS

20
24

HC Devices Have CMOS-Compatible Inputs. HCT Devices Have LSTTL-Compatible Inputs.

Device

# Pins
Quad Device
Octal Device
Buffer
Storage Capability
Inverting Outputs
Noninverting Outputs
Common Output Enable
Active-Low Oulput Enable
Active-High Output Enable
Direction Control

High-Speed CMOS Logic Data
DL129-Rev6

HC
HCT
245A

HC
640A

HC
646

20

20

24

•

•

•

•

•

•
•
•
•

•

•
•
•

•
•
•

•

•

1-9

MOTOROLA

Function Selector Guide

LATCHES

Device
Number
MC541MC74
HC75
HC259
HC373A
HCT373A
HC533A
HC563
HC573A
HCT573A

Functional
Equivalent
LSTTL
Device
54174

Function

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

Number
of
Pins

Dual 2-Bit Transparent Latch
B-Bit Addressable Latch/l-of-8 Decoder
Octal 3-State Noninverting Transparent Latch
Octal 3-State Noninverting Transparent Latch with
LSTTL-Compatible Inputs
Octal 3-State Inverting Transparent Latch

LS75
LS259
LS373,LS573
LS373,LS573

LS
LS
LS373
LS373

16
16
20
20

LS533,LS563

LS533

20

Octal 3-8tate Inverting Transparent Latch
Octal 3-State Noninverting Transparent Latch
Octal 3-8tate Noninverting Transparent Latch with
LSTTL-Compatible Inputs

LS533,LS563
LS373,LS573
LS373,LS573

LS563
LS573
LS573

20
20
20

HC Devices Have CMOS-Compatible Inputs. HCr Devices Have LSTTL-Compatible Inputs.
HC
75

HC
259

HC
HCT
373A

HC
533A

HC
563

HC
HCT
573A

# Pins

16

16

20

20

20

20

Single Device
Dual Device
Octal Device

•

•

•

•

•

•
•

•
•

•
•

•
•

•

•
•

•

•

•

•

Device

Number of Bits Controlled by Latch Enable:
2

8

•

Transparent
Addressable
Readback Capability

•

Noninverting Outputs
Inverting Outputs

•
•
•

Common Latch Enable, Active-Low

•

•

•

•
•
•
•

3-State Outputs
Common Output Enable, Active-Low

•

•

•

These devices are Identical In function and are different In Pinout only: HC/HCT373A and HC/HCT573A

MOTOROLA

1-10

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide

FLIP-FLOPS
Functional
Equivalent
LSTTL
Device

Device
Number
MC54/MC74
HC73
HC74A
HCT74A
HC107

Dual D Flip-Flop with Set and Reset
Dual D Flip-Flop with Set and Reset with
LSTIL-Compatible Inputs
Dual J-K Flip-Flop with Reset

HC109

Dual J-K with Set and Reset

HC112

Dual J-K Flip-Flop with Set and Reset

HC173
HC174A
HCT174A
HC175/A
HC273A
HCT273A
HC374A
HCT374A
HC534A
HC564
HC574A
HCT574A
HC646

54n4

Function
Dual J-K Flip-Flop with Reset

Quad 3-State D Flip-Flop with Common Clock and Reset
Hex D Flip-Flop with Common Clock and Reset
Hex D Flip-Flop with Common Clock and Reset with
LSTTL-Compatible Inputs
Quad D Flip-Flop with Common Clock and Reset
Octal D Flip-Flop with Common Clock and Reset
Octal D Flip-Flop with Common Clock and Reset with
LSTIL-Compatible Inputs
Octal 3-State Noninverting D Flip-Flop
Octal 3-State Noninverting D Flip-Flop with
LSTIL-Compatible Inputs
Octal 3-State Inverting D Flip-Flop
Octal 3-State Inverting D Flip-Flop
Octal 3-State Noninverting D Flip-Flop
Octal 3-State Noninverting D Flip-Flop with
LSTIL-Compatible Inputs
Octal 3-State Noninverting Bus Transceiver and
D Flip-Flop

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

LS73,LS73A,
LS107,LS107A
LS74,LS74A
LS74,LS74A

'4027

LS73,LS73A,
LS107,LS107A
LS109,LS109A

'4027

LS76,LS76A,
LS112, LS112A
LS173,LS173A
LS174
LS174

'4027
4076
4174
4174

LS112,
LS112A
LS/CMOS
LS/CMOS
LS

LS175

4175

'4013
4013

'4027

Number
of
Pins

LS73,
LS73A
LS
LS

14

LS107,
LS107A
LS

14

14
14

16
16
16
16
16

LS/CMOS

16

LS273
LS273

LS
LS

20
20

LS374,LS574
LS374,LS574

LS374
LS374

20
20

LS534,LS564

LS534

20

LS534,LS564
LS374,LS574
LS374,LS574

LS564
LS574
LS

20
20
20

LS646

LS

24

, Suggested alternative

High-Speed CMOS Logic Data
DL129-Rev6

1-11

MOTOROLA

Function Selector Guide

FLIP-FLOPS (Continued)
HC Devices Have CMOS-Compatible Inputs. HCT Devices Have LSTTL-Compatible Inputs.

Device
# Pins
Type
Dual Device
Quad Device
Hex Device
Octal Device
Common Clock
Negative-Transition Clocking
Positive-Transition Clocking

HC
73

HC
HCT
74A

HC
107

HC
109

HC
112

HC
173

HC
HCT
174A

HC
1751A

14

14

14

16

16

16

16

16

J-K

D

J-K

J-K

J-K

D

D

D

•

•

•

•

•

•

•

•

•

•

Common, Active-Low Data Enables
Noninverting Outputs
Inverting Outputs

•
•

•

•
•

•

•
•

•
•

•
•
•
•

.-•

3-8tate Outputs
Common, Active-Low Output Enables
Common Reset
Active-Low Reset
Active-High Reset

•

•

•

•

•

Active-Low Set

•

•

•

•

•
•

•

•

•
•

•
•

•

•
•

•

•

•

•

Transceiver
Direction Control

HC Devices Have CMOS-Compatible Inputs. HCT Devices Have LSTTL-Compatible Inputs.
HC
HCT
273A

HC
HCT
374A

HC
534A

HC
564

HC
HCT
574A

HC
646

# Pins

20

20

20

20

20

24

Type

D

D

D

D

D

D

•
•
•

•
•
•

•
•
•

•
•
•

•
•

•
•
•

•

•

•
•

•
•

Device

Dual Device
Quad Device
Hex Device
Octal Device
Common Clock
Negative-Transition Clocking
Positive-Transition Clocking

•

•

•

•

•

•

•

•

Common, Active-Low Data Enables
Noninverting Outputs
Inverting Outputs

•
•

3-State Outputs
Common, Active-Low Output Enables
Common Reset
Active-Low Reset
Active-High Reset

•

•
•

Active-Low Set

•
•

Transceiver
Direction Control
These devices are Identical In funcllOn and are different In Pinout only: HC73 and HC107
HC374A and HC574A
HC534A and HC564

MOTOROLA

1-12

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide

DIGITAL DATA SELECTORS/MULTIPLEXERS
Functional
Equivalent
LSTTL
Device
54n4

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

Number
of
Pins

a-Input Data Selector/Multiplexer
Dual 4-lnput Data Selector/Multiplexer
Quad 2-lnput Noninverting Data Selector/Multiplexer
Quad 2-lnput Data Selector/Multiplexer with
LSTTL-Compatible Inputs
Quad 2-lnput Data Selector/Multiplexer

LS151
LS153
LS157
LS157

*4512
4539
*4519
*4519

LS
LS/CMOS
LS
LS

16
16
16
16

LS

16

a-Input Data Selector/Multiplexer with 3-State Outputs
Dual 4-lnput Data Selector/Multiplexer with 3-State
Outputs
Quad 2-lnput Data Selector/Multiplexer with 3-State
Outputs

LS251
LS253

*4512
*4539

LS
LS/CMOS

16
16

LS257

*4519

LS

16

Device
Number
MC54/MC74

Function

HC151
HC153
HC157A
HCT157A
HC1581A
HC251
HC253
HC257

LS158

* Suggested alternative

HC Devices Have CMOS-Compatible Inputs.

Device
# Pins

Description

Single Device
Dual Device
Quad Device

HC
151

HC
153

HC
HCT
157A

HC
HCT
157A

HC
158
158A

HC
251

HC
253

He
257

16

16

16

16

16

16

16

16

Oneal
a inputs is
selected

Oneal
4 inputs is
selected

Oneal
two4-bit
words is
selected

Oneal
two4-bit
words is
selected

Oneal
two4-bit
words is
selected

Oneal
a inputs is
selected

14 One 01
4 inputs is
selected

Oneal
two4-bit
words is
selected

•

•

•

•

•

•

•

•
•

•
•

•

•

Data Latch with Active-Low Latch
Enable
Common Address
I-Bit Binary Address
2-Bit Binary Address
3-Bit Binary Address

•
•

•

•

•

•
•

•

Address Latch (Transparent)
Address Latch (Non-transparent)
Active-Low Address Latch Enable
Noninverting Output
Inverting Output

•
•

•

•

•

•

•
•

•
•

•

3-State Outputs
Common Output Enable
Active-High Output Enable
Active-Low Output Enable

High-Speed CMOS Logic Data
DL129-Rev6

•
•

•

1-13

•
•

•

•

•

•

•

•

•

•
•
•

•

MOTOROLA

Function Selector Guide

DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERS

54174

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

1-01-10 Decoder
1-01-8 Decoder/Demultiplexer with Address Latch
1-01-8 Decoder/Demultiplexer
1-01-8 Decoder/Demultiplexer with LSTTL-Compatible
Inputs
Dual 1-01-4 Decoder/Demultiplexer

LS42
LS137
LS138
LS138

'4028
'4028
'4028
'4028

LS
LS
LS
LS

16
16
16
16

LS139

4556

LS/CMOS

16

Decimai-to-BCD Encoder
1-01-16 Decoder/Demultiplexer
1-01-8 Decoder/Demultiplexer with Address Latch
8-Bit Addressable Latchll-01-8 Decoder
BCD-to-Seven-Segment Latch/Decoder/Display Driver

LS147
LS154:LS159
'LS137
LS259
'LS47:LS48,
'LS49

LS
LS

1-01-16 Decoder/Demultiplexer with Address Latch

'LSI54:LSI59

Functional
Equivalent
LSTTL
Device

Device
Number
MC54/MC74

HC42
.HC137
HC138A
HCT138A
HC139A
HC147
HC154
*HC237
··HC259
HC4511
HC4514

Function

Direct Pin
Compatibility

Number
of
Pins

4511

LS
CMOS

16
24
16
16
16

4514:4515

CMOS

24

'4515
'4208

, Suggested alternative
* Exclusive High-Speed CMOS design

MOTOROLA

1-14

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide

DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERS (Continued)
HC Devices Have CMOS-Compatible Inputs.
HC
42

Device

HC
139A

HC
147

HC
154

16

16

16

16

16

24

BCD Address

3-Bit Binary
Address

3-Bit Binary
Address

2-Bit Binary
Address

Any
Combination 01
9 Inputs

4-Bit Binary
Address

One 01 10

One of 8

One 018

One of4

BCD Address of
Highest Input

One of 16

•

•

•

•

•

•
•

•

# Pins
Input Description

HC
HCT
138A

HC
137

Output Description
Single Device
Dual Device

•

•
•

Address Input Latch
Active-High Latch Enable
Active-Low Latch Enable
Active-Low Inputs

•

Active-Low Outputs
Active-High Outputs
Active-Low Output Enable
Active-High Output Enable

•

•

•

•
•

••

•

•

••

Active-Low Reset
Active-Low Blanking Input
Active-High Blanking Input
Active-Low Lamp-Test Input
Phase Input (lor LCD's)
••

Implies the device has two such enables

HC Devices Have CMOS-Compatible Inputs.
HC
237

Device
# Pins

HC
259

HC
4511

HC
4514

16

16

16

24

3-Bit Binary
Address

3-Bit Binary
Address

BCD Data

4-Bit Binary
Address

One 01 8

One of8

7-Segment
Display

One 0116

Single Device
Dual Device

•

•

•

•

Address Input Latch
Active-High Latch Enable
Active-Low Latch Enable

•
•

•
•

•
•

•

•
•

Input Description
Output Description

Active-Low Inputs
Active-Low Outputs
Active-High Outputs

•
•
•

Active-Low Output Enable
Active-High Output Enable

•
•
•

Active-Low Reset
Active-Low Blanking Input
Active-High Blanking Input

•

Active-Low Lamp-Test Input

•

Phase Input (lor LCD's)

High-Speed CMOS Logic Data
DL129-Rev6

1-15

MOTOROLA

Function Selector Guide

ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS

Device
Number
MC54IMC74
HC4016/A
HC4051
HC4052
HC4053
HC4066/A
*HC4316/A
*HC4351
*HC4353

Functional
Equivalent
LSTTL
Device
54174

Function
Quad Analog Switch/Multiplexer/Demultiplexer
8-Channel Analog MultiplexerlDemultiplexer
Dual 4-Channel Analog Multiplexer/Demultiplexer
Triple 2-Channel Analog Multiplexer/Demultiplexer
Quad Analog Switch/Multiplexer/Demultiplexer

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

Number
of
Pins

4016,4066
4051
4052
4053
4066,4016

CMOS
CMOS
CMOS
CMOS
CMOS

14
16
16
16
14

Quad Analog Switch/Multiplexer/Demultiplexer with
Separate Analog and Digital Power Supplies
8-Channel Analog Multiplexer/Demultiplexer with
Address Latch
Triple 2-Channel Analog Multiplexer/Demultiplexer with
Address Latch

*4016

16

*4051

20

*4053

20

* Suggested alternative
* High-Speed CMOS design only

HC Devices Have CMOS-Compatible Inputs.
Device

# Pins
Description

Single Device
Dual Device
Triple Device
Quad Device
1-to-1
2-t0-1
4-to-1
8-t0-1

Multiplexing
Multiplexing
Multiplexing
Multiplexing

Active-High ON/OFF Control
Common Address Inputs
2-Bit Binary Address
3-Bit Binary Address
Address Latch with Active-Low Latch
Enable

HC
4016/A

HC
4051

HC
4052

HC
4053

14

16

16

16

14

4 Independently
Controlied
Switches

A 3-Bit Address
Selects One of 8
Switches

A 2-Bit Address
Selects One of 4
Switches

A 3-Bit Address
Selects Varying
Combinations of
the 6 Switches

4 Independently
Controlied
Switches

•

•

•
•
•

•
•

•
•
•

•
•
•

•
•
•

•

Common Switch Enable
Active-Low Enable
Active-High Enable

•
•

•
•

•
•

Separate Analog and Control Reference
Power Supplies

•

•

•
•

Switched Tubs (for RON and Prop. Delay
Improvement)

MOTOROLA

HC

4066/A

1-16

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide

ANALOG SWITCHES/MUlTIPlEXERS/DEMUlTIPlEXERS (Continued)
He Devices Have CMOS-Compatible Inputs.
Device

# Pins
Description

Single Device
Dual Device
Triple Device
Quad Device
1-to-1
2-t0-1
4-to-1
8-to-1

Multiplexing
Multiplexing
Multiplexing
Multiplexing

Active-High ON/OFF Control

He
4316/A

He
4351

He
4353

16

20

20

4 Independently
Controlled Switches
(Has a Separate
Analog Lower
Power Supply)

A 3-Bit Address
Selects One of 8
Switches
(Has an Address Latch)

A 3-Bit Address
Selects Varying
Combinations of
the 6 Switches
(Has an Address Latch)

•

•

•
•

•
•

•

Common Address Inputs
2-Bit Binary Address
3-Bit Binary Address
Address Latch with Active-Low Latch Enable
Common Switch Enable
Active-Low Enable
Active-High Enable

•
•

Separate Analog and Control Reference Power Supplies

•

•
•

•
•
•

••

••

•
•
•

•
•
•

Switched Tubs (for RON and Prop. Delay Improvement)
•• Implies the device has two such enables

High-Speed CMOS Logic Data
DL129-Rev6

1-17

MOTOROLA

Function Selector Guide

SHIFT REGISTERS

Device
Number
MC541MC74

Functional
Equivalent
LSTTL
Device
54/74

Function

HC164/A
HC165
HC194
HC195
HC299

B-Bit Serial-lnputlParallel-Qutput Shift Register
8-Bit Serial- or ParalleHnputlSerial-Qutput Shift Register
4-Bit Bidirectional Universal Shift Register
4-Bit Universal Shift Register
8-Bit Bidirectional Universal Shift Register with
Parallel 1/0

LS164
LS165
LS194,LS194A
LS196,LS195A
LS299

HC589/A

8-Bit Serial- or Paraliel-lnputlSerial-Qutput Shift Register
with 3-State Output
8-Bit SeriaHnpuVSerial- or Parallel-Qutput Shift Register
with Latched 3-State Outputs
8-Bit Serial- or Paraliel-lnpuVSerial-Qutput Shift Register
with Input Latch

LS589

HC595A
HC597/A

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Direct Pin
Compatibility

Number
of
Pins

LS
LS
LS/CMOS
LS
LS

14
16
16
16
20

LS

16

LS

16

LS

16

*4034
*4021
4194
*4035

*4034

LS595
LS597

* Suggested alternative

*Exclusive High-Speed CMOS design
HC Devices Have CMOS-Compatible Inputs.
HC
1641A

HC
165

HC
194

HC
195

HC
299

589/A

HC
595A

597/A

14

16

16

16

20

16

16

16

•
•

•

•

•

•
•

••

•
•
•

•
•
•

•
•
•
•

•
•
•
•

•

•
•

•
•
•
•

•

•
•
•
•
•
•
•
•

Positive-Transition Clocking
Active-High Clock Enable

•

•

Input Data Enable

•

Device

# Pins
4-Bit Register
8-Bit Register
Serial Data Input
Parallel Data Inputs
Serial Output Only
Parallel Outputs
Inverting Output
Noninverting Output
Serial Shift/Parallel Load Control
Shifts One Direction Only
Shifts Both Directions

•
•

•
•

•

•
•

•

•

•

HC

•
•
•
•

•

Data Latch with Active-High Latch Clock
Output Latch with Active-High Latch Clock

•

3-State Outputs
Active-Low Output Enable
Active-Low Reset

MOTOROLA

••

•

•

1-18

•

•

•

•

•
•
•

HC

•

•

•

•

•

•

•
•
•
•

•
•

High-Speed CMOS Logic Data
DL129-Rev6

Function Selector Guide

COUNTERS

Function

54n4

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX

Presettable BCD Counter with Asynchronous Reset
Presettable 4-Bit Binary Counter with Asynchronous
Reset
Presettable 4-Bit Binary Counter with Asynchronous
Reset with LSTrL-Gompatible Inputs
Presettable BCD Counter with Synchronous Reset
Presettable 4-Bit Binary Counter with Synchronous Reset
Dual 4-Stage Binary Ripple Counter with + 2 and + 5
Sections

LS160,LS160A
LS161,LS161A

4160
4161

LS/CMOS
LS/CMOS

16
16

LS161,LS161A

4161

LS/CMOS

16

LS162,LS162A
LS163,LS163A
LS390

4162
4163

LS/CMOS
LS/CMOS
LS

16
16
16

LS393

'4520
4017
4020
4040
4060

LS
CMOS
CMOS
CMOS
CMOS

14
16
16
16
16

Functional
Equivalent
LSTrL
Device

Device
Number
MC541MC74
HC160
HC161A
HCT161A
HC162
HC163A
HC390/A
HC393/A
HC4017
HC4020/A
HC4040/A
HC4060/A

Dual 4-Stage Binary Ripple Counter
Decade Counter
14-Stage Binary Ripple Counter
12-8tage Binary Ripple Counter
14-Stage Binary Ripple Counter with Oscillator

Direct Pin
Compatibility

Number
of
Pins

, Suggested alternative

HC Devices Have CMOS-Compatible Inputs.
HC
160

HC
161A

HC
162

HC
HCT
163A

HC
390/A

HC
393/A

HC
4017

HC
4020/A

HC
4040/A

HC
4060/A

# Pins

16

16

16

16

16

14

16

16

16

16

Single Device
Dual Device

•

•

•

•

•
•
4

•

•

•

•

•

Device

Ripple Counter
Number 01 Ripple Counter Internal Stages
Number 01 Stages wilh Available Outputs

4

Count Up

•

4-Bit Binary Counter
BCD Counter
Decimal Counter

•

•
•

•
•

•
•

•
•

•

•

4
4

•
•

•

•

12
12

14
10

•

•

•

•

•
•

Separate + 2 Section
Separate + 5 Section

•

On-Ghip Oscillator Capability
Positive-Transition Clocking
Negative-Transition Clocking
Active-High Clock Enable
Active-Low Clock Enable

•

•

•

•

Active-High Count Enable

••

••

••

••

Active-High Reset

•

•
•
•
•

•

•
•
•
•

4-Bit Binary Preset Data Inputs
BCD Preset Data Inputs
Active-Low Load Preset
Carry Output

•

14
12

•
•
•

•
•
•

•

•

•
•
•
•

•

•

•

•

•

•

•

•

•

•• implies the device has two such enables

High-Speed CMOS Logic Data
DL129-Rev6

1-19

MOTOROLA

Function Selector Guide

MISCELLANEOUS DEVICES

Device
Number
MC541MC74
HC85
HC280
HC688
HC4046A
HC4538A

MOTOROLA

Functional
Equivalent
LSTTL
Device
54(74

Function

4-Bit MagnHude Comparator
9-Bit Odd/Even ParRy Generator/Checker
B-Bit Equality Comparator
Phase-Locked Loop
Dual Precision Monostable Multivibrator
(Retriggerable, Resellable)

LS85
LS280
LS688
*LS423

1-20

Functional
Equivalent
CMOS
Device
MC1XXXX
orCDXXXX
*4585
*4531
4046
4538,4528

Direct Pin
Compatibility

Number
of
Pins

LS
LS
LS
CMOS
CMOS

16
14
20
16
16

High-Speed CMOS Logic Data
DL129-Rev6

High-Speed CMOS Data

Design Considerations

CONTENTS
Introduction ............................... 2-2
Handling Precautions ...................... 2-2
Power Supply Sizing ....................... 2-6
Inputs .................................... 2-8
Outputs .................................. 2-9
CMOS Latch Up .......................... 2-14
Maximum Power Dissipation ............... 2-16
Thermal Management ..................... 2-17
Capacitive Loading Effects on
Propagation Delay ........................ 2-19
Temperature Effects on DC and AC
Parameters .............................. 2-20
Supply Voltage Effects on Drive Current
and Propagation Delay .................... 2-20
Decoupling Capacitors .................... 2-21
Interfacing ............................... 2-21
Typical Parametric Values ................. 2-23
Reduction of Electromagnetic
Interference (EMI) ........................ 2-24
Hybrid Circuit Guidelines .................. 2-24
Schmitt-Trigger Devices .................. 2-25
Oscillator Design with High-Speed CMOS ... 2-26
Printed Circuit Board Layout ............... 2-27
Definitions and Glossary of Terms ........ 2-28
Applications Assistance Form . ........... 2-30

MOTOROLA

2-1

High-Speed CMOS Logic Data
DL129-Rev6

121

Design Considerations
INTRODUCTION
CMOS devices have been used for many years in applications where the primary concerns were low power consumption, wide power-supply range, and high noise immunity.
However, metal-gate CMOS (MC14000 series) is too slow
for many applications. Applications requiring high-speed devices, such as microprocessor memory decoding, had to go
to the faster families such as LSTTL. This meant sacrificing
the best qualities of CMOS. The next step in the logic evolution was to introduce a family of devices that were fast
enough for such applications, while retaining the advantages
of CMOS. The results of this change can be seen in Table 1
where HSCMOS devices are compared to standard (metalgate) CMOS, LSTTL, and ALS.
The Motorola CMOS evolutionary process shown in
Figure 1 indicates that one advantage of the silicon-gate
process is device size. The High-Speed CMOS (HSCMOS)
device is about half the size of the metal-gate predecessor,
yielding significant chip area savings. The silicon-gate process allows smaller gate or channel lengths due to the self-

aligning gate feature. This process uses the gate to define
the channel during processing, eliminating registration errors
and, therefore, the need for gate overlaps. The elimination of
the gate overlap significantly lowers the gate capacitance,
resulting in higher speed capability. The smaller gate length
also results in higher drive capability per unit gate width, ensuring .more efficient use of chip area. Immunity enhancements to electrostatic discharge (ESD) damage and latch up
are ongoing. Precautions should still be taken, however, to
guard against electrostatic discharge and latch up.
Motorola's High-Speed CMOS family has a broad range of
functions from basic gates, flip-flops, and counters to buscompatible devices. The family is made up of devices that
are identical in pinout and are functionally equivalent to
LSTTL devices, as well as the most popular metal-gate
devices not available in TTL. Thus, the designer has an
excellent alternative to existing families without having to
become familiar with a new set of device numbers.

METAL GATE CMOS

cl§k 1't9==(j} J___~_P~+

12]

___P_+___~ ____+____p~______N_+___

l]£J

I~I

l~JQEJ.1

1~·~--------------------------120~m----------------------------~-.

HIGH-SPEED
SILICON-GATE
HSCMOS

Figure 1. CMOS Evolution

HANDLING PRECAUTIONS
High-Speed CMOS devices, like all MOS devices, have
an insulated gate that is subject to voltage breakdown. The
gate oxide for HSCMOS devices breaks down at a gatesource potential of about 100 volts. Some device inputs are
protected by a resistor-diode network (Figure 2). New input
protection structure deletes the poly resistor (Figure 3) Using
the test setup shown in Figure 4, the inputs typically withstand a > 2 kV discharge.

SILICON-GATE
CMOS
INPUT

°

I -~'---I"C--"",,,,,,TO
-

SILICON-GATE
CMOS
-150Q
INPUT Q---.J\II./\r----+------.--J\M4-TO CIRCUIT
POLY

Figure 2. Input Protection Network

11
lOMQ

HIGH VOLTAGE
DCSOURCE

CIRCUIT

. T

-

TO INPUT

]100 PF

. °

I
VZAP

!vg~

GROUND

Figure 3. New Input Protection Network

MOTOROLA

-=-

1.5kQ

~UNDERTEST

Figure 4. Electrostatic Discharge Test Circuit

2-2

High-Speed CMOS Logic Data

DL129-Rev6

Design Considerations
Table 1. Logic Family Comparisons
General Characteristics (1) (All Maximum Ratings)
TTL
Characteristic
Operating Voltage Range
Operating Temperature Range
Input Voltage (limits)

CMOS

LS

ALS

MC14000

Hi-5peed

VCC/EE/DD

5±5%

5±5%

3.0 to 18

2.0 to 6.0

V

TA

Oto+70

Oto+70

-40to+85

- 55 to + 125

'c

VIHmin

2.0

2.0

3.54

3.54

V

VILmax

0.8

0.8

1.54

1.04

V
V

VOHmin

2.7

2.7

VDD-0.05

VCC-O.l

VOL max

0.5

0.5

0.05

0.1

IINH

20

20

IINL

-400

-200

Output Current @ Vo (limit)
unless otherwise specified

IOH

-0.4

IOL
DC Noise Margin Low/High

DCM

-

20

Output Voltage (limits)

Input Current

DC Fanout

Unit

Symbol

V
J.lA

±0.3

± 1.0

-0.4

-2.1 @ 2.5V

-4.0@
VCC -0.8 V

rnA

8.0

8.0

0.44 @ 0.4 V

4.0 @ 0.4 V

rnA

0.3/0.7

0.3/0.7

1.454

0.90/1.354

V

20

50(1)2

50(10)2

-

Speed/Power Characteristics (1) (All Typical Ratings)
TTL

CMOS

Symbol

LS

ALS

MC14000

Hi-Speed

Quiescent Supply CurrenVGate

IG

0.4

0.2

0.0001

0.0005

rnA

Power/Gate (Quiescent)

PG

2.0

1.0

0.0006

0.001

mW

Propagation Delay

tp

9.0

7.0

125

8.0

ns

Speed Power Product

-

18

7.0

0.075

0.01

pJ

Clock Frequency (D--F/F)

fmax

33

35

4.0

40

MHz

Clock Frequency (Counter)

fmax

40

45

5.0

40

MHz

LS

ALS

MC14000

Hi-Speed

Unit

SN74LSOO

SN74ALSOO

MC14001B

74HCOO

Typical

(10)3

(5)3

25

(8)310

Maximum

(15)3

10

250

(15)320

Characteristic

Unit

Propagation Delay (1)
CMOS

TTL
Characteristic
Gate, NOR or NAND:
tpLH/tPHL(5)

Flip-Flop, D-type:
tpLH/tpHL(5) (Clock to Q)

Counter:
tPLHitpHL (5) (Clock to Q)

Product No.

ns

SN74LS74

SN74ALS74

MC14013B

74HC74

-

Typical

(25)3

(12)3

175

(23)225

ns

Maximum

(40)3

20

350

(30)332

Product No.

SN74LS163

SN74ALS163

MC14163B

74HC163

-

Typical

(18)3

(10)3

350

(20)322

ns

Maximum

(27)3

24

700

(27)329

Product No.

NOTES:
1. Specifications are shown for the following conditions:
a) VDD (CMOS) = 5.0 V ± 10% for dc tests, 5.0 V for ac tests; VCC (TTL) = 5.0 V ± 5% for dc tests, 5.0 V for ac tests
b) Basic Gates: LSOO or equivalent
c) TA=25'C
d) CL = 50 pF (ALS, HC), 15 pF (LS, 14000 and Hi--Speed)
e) Commercial grade product
2. ( ) fanout to LSTTL
3.( )CL=15pF
4. DC input voltage specifications are proportional to supply voltage over operating range.
5. The number specified is the larger of tpLH and tpHL for each device.

MOTOROLA

2-3

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
The input protection network uses a polysilicon resistor in
series with the input and before the protection diodes. This
series resistor slows down the slew rate of static discharge
spikes to allow the protection diodes time to turn on. Outputs
have a similar ESD protection network except for the series
resistor. Although the on-chip protection circuitry guards
against ESD damage, additional protection may be necessary once the chip is placed in circuit. Both an external series
resistor and ground and VCC diodes, similar to the input
protection structure, are recommended if there is a potential
of ESD, voltage transients, etc. Several monolithic diode arrays are available from Motorola, such as the MAD130 (dual
10 diode array) or the MADII 04 (dual 8 diode array). These
diodes, in chip form, not only provide the necessary protection, but also save board space as opposed to using discrete
diodes.
Static damaged devices behave in various ways, depending on the severity of the damage. The most severely damaged pins are the easiest to detect. An ESD-damaged pin
that has been completely destroyed may exhibit a low-impedance path to VCC orGND. Another common failure mode
is a fused or open circuit. The effect of both failure modes is
that the device no longer properly responds to input signals.
Less severe cases are more difficult to detect because they
show up as intermittent failures or as degraded performance.
Generally, another effect of static damage is increased chip
leakage currents (ICC).
Although the input network does offer significant protection, these devices are not immune to large static voltage discharges that can be generated while handling. For example,
static voltages generated by a person walking across a
waxed floor have been measured in the 4 to 15 kV range
(depending on humidity, surface conditions, etc.). Therefore,

the following precautions should be observed.
1. Wrist straps and equipment logs should be maintained
and audited on a regular basis. Wrist straps malfunction
and may go unnoticed. Also, equipment gets moved
from time to time and grounds may not be reconnected
properly.
2. Do not exceed the Maximum Ratings specified by the
data sheet.
3. All unused device inputs should be connected to VCC or
GND.
4. All low impedance equipment (pulse generators, etc.)
should be connected to CMOS inputs only after the
CMOS device is powered up. Similarly, this type of
equipment should be disconnected before power is
turned off.
5. Circuit boards containing CMOS devices are merely extensions of the devices, and the same handling precautions apply. Contacting edge connectors wired directly
to device inputs can cause damage. Plastic wrapping
should be avoided. When external connectors to a PC
board are connected to an input or output of a CMOS
device, a resistor should be used in series with the input
or output. This resistor helps limit accidental damage if
the PC board is removed and brought into contact with
static generating materials. The limiting factor forthe series resistor is the added delay. The delay is caused by
the time constant formed by the series resistor and input
capacitance. Note that the rnaximum input rise and fall
times should not be exceeded. In Figure 5, two possible
networks are shown using a series resistor to reduce
ESD damage. For convenience, an equation is given for
added propagation delay and rise time effects due to series resistance size.
VCC

D1

CMOS

R1

TO OFF-BOARD
CONNECTION

INPUT

OR
OUTPUT

CMOS
INPUT

OR
D2

OUTPUT

GND '::'
Advantage: R2 < R1 for the same level of
protection. Impact on ac and dc
characteristics is minimized.

Advantage: Requires minimal area

Disadvantage: R1 > R2 for the same level of
protection; therefore, rise and
fall times, propagation delays,
Disadvantage: More board area, higher initial
and output drives are severely
cost.
affected.
NOTE: These networks are useful for protecting the following:
A digital inputs and outputs
C 3-state outputs
B analog inputs and outputs
D bidirectional (I/O) ports
Propagation Delay and Rise TIme vs. Series Resistance

R =_t_

C·k
where:
R=the maximum allowable series resistance in ohms
t= the maximum tolerable propagation delay or rise time in
seconds
C= the board capacitance plus the driven input
capacitance in farads
k= 0.7 for propagation delay calculations
k= 2.3 for rise time calculations
Figure 5. Networks for Minimizing ESO and Reducing CMOS Latch Up Susceptibility

MOTOROLA

2-4

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
6. All CMOS devices should be stored or transported in
materials that are antistatic or conductive. CMOS devices must not be inserted into conventional plastic
"snow", Styrofoam, or plastic trays, but should be left in
their original container until ready for use.
7. All CMOS devices should be placed on a grounded
bench surface and operators should ground themselves prior to handling devices, because a worker can
be statically charged with respect to the bench surface.
Wrist straps in contact with skin are essential and
should be tested daily. See Figure 6 for an example of
a typical work station.
8. Nylon or other static generating materials should not
come in contact with CMOS devices.
9. If automatic handlers are being used, high levels of static electricity may be generated by the movement of the
device, the belts, or the boards. Reduce static buildup
by using ionized air blowers, anti-static sprays, and
room humidifiers. All conductive parts of machines
which come into contact with the top, bottom, or sides
of IC packages must be grounded to earth ground.
10. Cold chambers using C02 for cooling should be
equipped with baffles, and the CMOS devices must be
contained on or in conductive material.
11. When lead straightening or hand soldering is necessary, provide ground straps for the apparatus used and
be sure that soldering iron tips are grounded.
12. The following steps should be observed during wave
solder operations:
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to
earth ground.
b. The loading and unloading work benches should
have conductive tops grounded to earth ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic
or conductive containers prior to being moved to subsequent stations.
13. The following steps should be observed during boardcleaning operations:
a. Vapor degreasers and baskets must be grounded to
earth ground.

b. Brush or spray cleaning should not be used.
c. Assemblies should be placed into the vapor degreaser immediately upon removal from the antistatic or conductive container.
d. Cleaned assemblies should be placed in antistatic or
conductive containers immediately after removal
from the cleaning basket.
e. High velocity air movement or application of solvents
and coatings should be employed only when a static
eliminator using ionized air is directed at the printed
circuit board.
14. The use of static detection meters for production line
surveillance is highly recommended.
15. Equipment specifications should alert users to the presence of CMOS devices and require familiarization with
this specification prior to performing any kind of maintenance or replacement of devices or modules.
16. Do not insert or remove CMOS devices from test sockets with power applied. Check all power supplies to be
used for testing devices to be certain there are no voltage transients present.
17. Double check test equipment setup lor proper polarity
of VCC and GND before conducting parametric or functional testing.
18. Do not recycle shipping rails. Repeated use causes deterioration of their antistatic coating. Exception: carbon
rails (black color) may be recycled to some extent. This
type of rail is conductive and antistatic.

RECOMMENDED READING
"Requirements for Handling Electrostatic-Discharge
Sensitive (ESDS) Devices" EIA Standard EIA-625
Available by writing to:
Global Engineering Documents
15 Inverness Way East
Englewood, Colorado 80112
Or by calling:
1-800-854-7179 in the USA or CANADA or
(303) 397-7956 International
S. Cherniak, "A Review of Transients and Their Means of
Suppression", Application Note-843, Motorola Semiconductor Products Inc., 1982.

NOTES:
1. 1/16 inch conductive sheet stock covering bench-top work

area.
2. Ground strap.
3. Wrist strap In contact with skin.
4. Static neutralizer. (ionized air blower directed at work.)
Primarily for use in areas where direct grounding is
impractical.
5. Room humidifier. Primarily for use in areas where the
relative humidity is less than 45%. Caution: building
heating and cooling systems usually dry the air causing
the relative humidity inside a building to be less than
outside humidity.

Figure 6. Typical Manufacturing Work Station

MOTOROLA

2-5

High-Speed CMOS Logic Data
DL129-Rev6

[2J
2

Design Considerations
1. The recommended power supply voltages should be
observed. For battery backup systems such as the one
in Figure 8, the battery voltage must be at least 2.7 volts
(2 volts for the minimum power supply voltage and
0.7 volts to account for the voltage drop across the series diode).
2. Inputs that might go above the battery backup voltage
should use the HC4049 or HC4050 buffers (Figure 8).
II line power is interrupted, CMOS System A and Buffer
A lose power. However, CMOS System B and Buffer B
remain active due to the battery backup. Buffer A
protects System A from System B by blocking active
inputs while the circuit is not powered up. Also, if the
power supply voltage drops below the battery voltage,
Buffer A acts as a level translator for the outputs from
System B. Buffer B acts to protect System B from any
overvoltages which might exist. Both buffers may be
replaced with current-limiting resistors, however power
consumption is increased and propagation delays are
lengthened.
3. Outputs that are subject to voltage levels above VCC or
below GND should be protected with a series resistor
and/or clamping diodes to limit the current to an acceptable level.

POWER SUPPLY SIZING
CMOS devices have low power requirements and the ability to operate over a wide range of supply voltages. These
two characteristics allow CMOS designs to be implemented
using inexpensive power supplies without cooling fans. In
addition, batteries may be used as either a primary power
source or as a backup.
The maximum recommended power supply voltage for HC
devices is 6.0 V and 5.5 V for HCT devices. Figure 7 offers
some insight as to how this specification was derived. In the
figure, Vs is the maximum power supply voltage and IS is the
sustaining current for the latch-up mode. The value of Vs
was chosen so that the secondary breakdown effect may be
avoided. The low-current junction avalanche region is between 10 and 14 volts at TA 25°C.

=

ICC

~TC\

UP MODE

[2J

SECONDARY
BREAKDOWN

POWER SUPPLY

I
IS

LOW CURRENT
~ JUNCTION
AVALANCHE

------

Vs

BATTERY TRICKLE
RECHARGE

VCC

DATA SHEET MAXIMUM SUPPLY RATING

Figure 7. Secondary Breakdown Characteristics

CMOS
SYSTEM

I

In an ideal system design, the power supply should be designed to deliver only enough current to ensure proper operation of all devices. The obvious benefit of this type of
design is cost savings.

Figure 8. Battery Backup System

BATTERY SYSTEMS
HSCMOS devices can be used with battery or battery
backup systems. A few precautions should be taken when
designing battery-operated systems.
POWER SUPPLY

---,

r------I
I
I
I
I
I
I
I
I

LINE POWER ONLY
SYSTEM

I
I
I
I

r-----------

I

I

BATTERY BACKUP
SYSTEM

- - - - BAnERYTRiCKLE"1

t-__~~__R_E_CH,ARGE

L. _ _ _ _ _ _ _ _ _HC4050
_ _ .J

I
I
I
I
I
I
CMOS
I
SYSTEM
I
I
I
IL. _ _ _ _ _ _ _ _ _ _ _ _
-=_ _ _ _ _ _ _ _ _ _ .JI

A

B

I

.-----4

_

_

I

I

Figure 9. Battery Backup Interface

MOTOROLA

2--6

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
Switch the clock pin while changing the data
pints) such that the output(s) change with
each clock cycle.

Flip-Flops:

CPO POWER CALCULATION

Power consumption for HSCMOS is dependent on the
power-supply voltage, frequency of operation, internal capacitance, and load. The power consumption may be calculated for each package by summing the quiescent power
consumption,lcc _ Vcc,andthe switching power required by
each device within the package. For large systems, the most
timely method is to bread-board the circuit and measure the
current required under a variety of conditions.
The device dynamic power requirements can be calculated by the equation:

Switch one address pin which changes two
Decodersl
Oemultiplexers: outputs.
Data Selectorsl Switch one address input with the corresponding data inputs at opposite logic levels
Multiplexers:
so that the output switches.
Analog
Switches:

Switch one address/select pin which
changes two switches. The switch inputsl
outputs should be left open. For digital
applications where the switch inputs/outputs change between VCC and GND, the
respective switch capacitance should be
added to the load capacitance.

Counters:

Switch the clock pin with the other inputs
biased so that the device counts.

Shift
Registers:

Switch the clock while alternating the input
so that the device shifts altemating 1sand
Os through the register.

Transceivers:

Switch only one data input. Place transceivers in a single direction.

Monostables:

The pulse obtained with a resistor and no
external capaCitor is repeatedly switched.

Parity
Generators:

Switch one input.

Po =(Cl + CPO) VCC2f
=power dissipated in ~W
Cl =total load capacitance present at the output in

where: Po

pF
CpO = a measure of intemal capacitances, called
power dissipation capacitance, given in pF

=supply voltage in volts
f =frequency in MHz

VCC

If the devices are tested at a sufficiently high frequency,
the dc supply current contributes a negligible amount to the
overall power consumption and can therefore be ignored.
For this reason, the power consumption is measured at
1 MHz and the following formula is used to determine the device's CPO value:
CpO =

ICC (dynamic)
VCC-f

-Cl

The resulting power dissipation is calculated using CPO as
follows under no-load conditions.

=CpOVCC2f + VCCICC
Po =CPOVCC 2f + VCCICC + dlCCVCC

(HC)

Switch the lowest priority output.
Switch one input so that approximately onehalf of the outputs change state.

AlUs/Adders:

Switch the least significant bit. The remaining inputs are biased so that the device is
alternately adding 0000 (binary) or 0001
(binary) to 1111 (binary).

Po

(HCT)

(01 + 02 + ... + on)

On HSCMOS data sheets, CpO is a typical value and is
given either for the package or for the individual device (Le.,
gates, flip-flops, etc.) within the package. An example of calculating the package power requirement is given using the
74HCOO, as shown in Figure 10.
From the data sheet:

where the previously undefined variable, on is the duty cycle
of each input applied at TTUNMOS levels.
The power dissipation for analog switches switching digital
signals is the following:
(HC)

Encoders:
Display
Orivers:

=CPOVCC2fin + (CS + CUVCC2fout + VCCICC
=digital switch capacitance, and
fout =output frequency

PD

ICC = 2

where: Cs

Switch one input while the remaining inputts) are biased so that the output(s)
switch.

latches:

Switch the enable and data inputs such that
the latch toggles.

MOTOROLA

at room temperature (per package)

Po = (CPD + CUVCC 2f + VCCICC

In order to determine the CPO of a single section of a device
(i.e., one of four gates, or one of two flip-flops in a package),
Motorola uses the following procedures as defined by
JEDEC. Note: "biased" as used below means "tied to VCC or
GNO."
Gates:

~A

CPO = 22 pF per gate

=(22 pF + 50 pF)(5 V)2(1 kHz) 1.8 ~W
=(22 pF + 50 pF)(5 V)2(1 MHz) 1800 ~w.
P03 =(22 pF) (5 V)2(0 Hz) =0 ~W
P04 =(22 pF)(5 V)2(0 Hz) =0 ~W
PD(total) =VCCICC + P01 + PD2 + P03 + PD4
=10 ~W + 1.81lW + 1800 IlW + 0 ~W
P01

P02

= 18121lW

2-7

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
VCC=5V
VCC
Rl =R2=HIGHZ
f= 1 kHz

Rl

r

R2
f= 1 MHz

lOPF

Figure 12. Input Model for GND :s; Vin :s; VCC
When CMOS inputs are left open-circuited, the inputs may
be biased at or near the typical CMOS switchpoint of 0.45
VCC for HC devices or 1.3 V for HCT devices. At this switch·
point, both the P-channel and the N-channel transistors are
conducting, causing excess current drain. Due to the high
gain of the buffered devices (see Figure 13), the device can
go into oscillation from any noise in the system, resulting in
even higher current drain.

Figure 10. Power Consumption Calculation Example
As seen by this example, the power dissipated by CMOS
devices is dependent on frequency. When operating at very
high frequencies, HSCMOS devices can consume as much
power as LSTTL devices, as shown in Figure 11. The power
savings of HSCMOS is realized when used in a system
where only a few of the devices are actually switching at the
system frequency. The power consumption savings comes
from the fact that for CMOS, only the devices that are switching consume significant power.
100m

5
2
10m
(j)

~

5

~ 4

1= MC7400

UJ

/

13

I..e: F?'"

SN74LSOO

~

SN74ALSOO

HC

0

1/

-s

~

5

a.

100 I! f- MC74HCOO

5
2

I - - t--- HCT

.....
a.
.....
::::l 2
::::l

~ 1m
oc

~

(!J

V

10 I!
2
10 k

.Yr

VCC=5Vdc -

V

2

1

57
2 57.2
57
2 57
2
lOOk
1M
10M
100M
FREQUENCY'@ 50% DUTY CYCLE (Hz)

57

5

Figure 13. Typical Transfer Characteristics
for Buffered Devices

lG

For these reasons, all unused HC/HCT inputs should be
connected either to VCC or GND. For applications with inputs
going to edge connectors, a 100 k.Q. resistor to GND should
be used, as well as a series resistor (RS) for static protection
and current limiting (see Handling Precautions, this chap·
ter, for series resistor consideration). The resistors should be
configured as in Figure 14.

Figure 11. Power Consumption Vs.lnput Frequency
for TTL, LSTTL, ALs, and HSCMOS

INPUTS
A basic knowledge of input and output structures is essential to the HSCMOS designer. This section deals with the various input characteri!1tics and application rules regarding
their use. Output characteristics are discussed in the section
titled Outputs.
All standard HC, HCU and HCT inputs, while in the recommended operating range (GND :s; Vin :s; VCC), can be modeled as shown in Figure 12. For input voltages in this range,
diodes D1 and D2 are modeled as resistors representing the
high-impedance of reverse biased diodes. The maximum input current is 1 !lA, worst case over temperature, when the
inputs are at VCC or GND, and VCC = 6 V.

MOTOROLA

4

3

Vin. INPUT VOLTAGE (V)

FROM
EDGE
CONNECTOR

RS
100kO

Figure 14. External Protection

2-8

High-Speed CMOS Logic Data

DL129-Rev6

Design Considerations
guaranteed output voltages of VOL = 0.1 V and VOH =
VCC - 0.1 V for I lout I :5 20 ILA (:5 20 HSCMOS loads).
The output drives for standard drive devices are such
that 54HC/HCT and 74HC/HCT devices can drive ten LSTTL
loads and maintain a VOL :5 0.4 V and VOH ~ VCC - 0.8 V
across the full temperature range; bus-driver devices can
drive fifteen LSTTL loads under the same conditions.
The outputs of all HSCMOS devices are limited to externally forced output voltages of - 0.5 :5 Vout :5 VCC + 0.5 V.
For externally forced voltages outside this range a latch up
condition could be triggered. (See CMOS Latch Up, this
chapter.)
The maximum rated output current given on the individual
data sheets is 25 mA for standard outputs and 35 mA for bus
drivers. The output short circuit currents of these devices typically exceed these limits. The outputs can, however, be
shorted for short periods of time for logic testing, if the maximum package power diSSipation is not violated. (See individual data sheets for maximum power diSSipation ratings.)
For applications that require driving high capacitive loads
where fast propagation delays are needed (e.g., driving power MOSFETS), devices within the same package may be
paralleled. Paralleling devices in different packages may result in devices switching at different points on the input voltage waveform, creating output short circuits and yielding
undesirable output voltage waveforms.
As a design aid, output characteristic curves are given
for both P-channel source and N-channel sink currents.
The curves given include expected minimum curves for
TA =25°C, 85°C, and 125°C, as well as typical values for
TA =25°C. For temperatures < 25°C, use the 25°C curves.
These curves, Figure 18 through Figure 29, are intended as
design aids, not as guarantees. Unused output pins should
be open-circuited (floating).

For inputs outside of the recommended operating range,
the CMOS input is modeled as in Figure 15 and Figure 16.
Current flows through diode 01 or 02 whenever the input
voltage exceeds VCC or drops below GNO enough to forward
bias either 01 or 02. The device inputs are guaranteed to
withstand from GNO -1.5 V to VCC + 1.5 V and a maximum
current of 20 mAo If this maximum rating is exceeded, the device could go into a latch-up condition. (See CMOS Latch
Up, this chapter.) Voltage should never be applied to any input or output pin before power has been applied to the device's power pins. Bias on input or output pins should be
removed before removing the power. However, if the input
current is limited to less than 20 mA, and this current only
lasts for a brief period of time « 100 ms), no damage to the
device occurs.
Another specification that should be noted is the maximum
input rise (tr) and fall (tf) times. Figure 17 shows the results of
exceeding the maximum rise and fall times recommended by
Motorola or contained in JEOEC Standard No. 7A. The reason for the oscillation on the output is that as the voltage
passes through the switching threshold region with a slow
rise time, any noise that is on the input line is amplified, and
is passed through to the output. This oscillation may have a
low enough frequency to cause succeeding stages to switch,
giving unexpected results. If input rise or fall times are expected to exceed the maximum specified rise or fall times,
Schmitt-triggered devices such as Motorola's HC14 and
HC132 are recommended.

OUTPUTS
All HSCMOS outputs, with the exception of the HCU04,
are buffered to ensure consistent output voltage and current
specifications across the family. All buffered outputs have

/
V
II

,

I

J

Figure 15. Input Model for Vin > VCC or Vin < GNO

You t

3PF

1
I

"

'\

l2PF

I

Figure 17. Maximum Rise Time Violation

Figure 16. Input Model for New ESO Enhanced Circuits

MOTOROLA

2-9

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
STANDARD OUTPUT CHARACTERISTICS
N-CHANNEL SINK CURRENT

P-CHANNEL SOURCE CURRENT

25

-25

«
..§..

«

..§.. 20

I-

f5a:

a:
a:

aa:

zw -20

:::J
()

15

w

~

!3a
"5

.2

a:

:::J

a

(J)

10

I:::J

TYPICAL
-TA=25"C\

5

o

a

1.0
1.5
VOU!' OUTPUT VOLTAGE (V)

/I

!z
w

a
""
z
Ci5

~
"-

!3
a
"5

.2

I

15

V

o~

2.0

0.5

1.0

1.5

2.0

«

..§.. 20

a:
a:

a

15

""Ci5z
~

g:

10

TA=125"C -

1.5
2.0
2.5
3.0
Vout, OUTPUT VOLTAGE (V)

3.5

4.0

I J~r--:: ~ EXPECTED MINIMUM CU~VES'
II
I I I I
O~
I

-5

j
4.5

4.5

4.0

3.5

3.0
2.5
2.0
1.5
Vout, OUTPUT VOLTAGE (V)

Figure 21. VGS
-25

«
..§..

V

z -20

I-

A. II /
II r-x
I I.
~
1/ '" --... EXPECTED MINIMUM CURVES'

TYPICA~TA=250C
TA=25"C /

a:
a:

:::J

()

w

-15

()

a:

:::J

a(J)

'/

I:::J

-10

a..

I:::J

V

a

""=>

-5

/

I V '/'
I- //

w

:::J

a

=- 2.0 V

TA=85"C _

.......-

TYPIC:L TA = 25"C I'" TA=85"C
TA=25"C
,
TA=125"C

!z
w

.
1.0
0.5
Vout, OUTPUT VOLTAGE (V)

TA = 25"C

Figure 20. VGS = 4.5 V
25

EXPECTED MINIMUM', TA, = 25-125"C _

I
I

,

o

....-- ~

Figure 19. VGS

TA= 125"C
I A~
fA,.
I
K
I
'/.
0~
EXPECTED
MINIMUM
CURVES'
5
IV
I I I I I
I
o

10

-5

.2

=2.0 V

/TYPICAL
/ TA=25"C

..§.. 20

"5

EXPECTED MINIMUM', TA = 25-125"C _

Figure 18. VGS

«

TYPICAL
I-- TA = 25"C

:::J

0.5

25

-10

"I-

l/

o /':.

a:
a:

-15

()

""

z
Ci5

1.0

o

0.5

=- 4.5 V

./ ' / TA= 85"C
/'

-

"'TA=125"C

-

f--

1/J, ~
'Ir .::-.; f" EXPECTED MINIMUM CURVES'

l

'I

.2

o
o

1.0

2.0
3.0
4.0
Vout, OUTPUT VOLTAGE (V)

·Figure 22. VGS

5.0

o
6.0

6.0

=6.0 V

5.0

4.0
3.0
2.0
Vout, OUTPUT VOLTAGE (V)

Figure 23. VGS

1.0

o

=- 6.0 V

'The expected minimum curves are not guarantees, but are design aids.

MOTOROLA

2-10

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
BUS-DRIVER OUTPUT CHARACTERISTICS
P-CHANNEL SOURCE CURRENT

N-CHANNEL SINK CURRENT
35

-35

<-

<-

S 30

S

I-

Z

z

UJ

a: 25
a:

UJ

a:
a:

~

(.)

UJ

(.)

~

20

(.)

'"enz

a:
~

a

'"

15

I-

-

TYPICAL
TA= 25°C
\

~

a.

I~

10

~

a

".... ~/

~

'"

2

o~
o

0.5

I~

a.

I-

35

L

[E 25
(.)

~

a:

20

g

15

TA=25°C

~

~ 10
a
I

II'

tl!

a:

1.0

25

(.)

a:

20

~

g

15

~

§ 10
j

S

w

a:
a:

~

(.)

5

'"en

I-

I
_

rll r-----

"

I-

EXPECTED MINIMUMS'

~

a

-10

3.5

4.0

4.5

-5

II RS

j

-15

0

d

TA=125°C -

IJ

:y
o
4.5

4.0

3.5

3.0
2.5
2.0
1.5
Vout, OUTPUT VOLTAGE (V)

1.0

0.5

Figure 27. VGS = - 4.5 V
-35

<-

TA= 25°C
TA = 25°C

S

-30

I-

z

UJ

I

a:
a:
~

(.)

TA = 125°C
I
I
I

'"
en
I-

-25
-20

z

-15

~

a.

I-

a -10
~

hr-I- It+J
} l4
I

I} ~
'.If

5.0

~

=6.0 V

-TA=25°C

I

I I I

- EXPECTED MINIMUMS'

I

-5
0
6.0

6.0

TYPICAL
TA~25°C

TA= asoc
I
I
t--- TA = 125°C

"5

2

Figure 28. VGS

--

TAI= 85

EXPECTED MINIMUMS'

IW

=4.5 V

2.0
3.0
4.0
Vout, OUTPUT VOLTAGE (V)

./

V/ ' /"
J.

1/

-20

=- 2.0 V

/ ' ~=25°C

/1

TYPICAL

-25

~

r" EXPECTED MINIMUMS'

1.0

1.0
0.5
Vout, OUTPUT VOLTAGE (V)

TA,=25°C /

a.

IL~ ~ t-TA=85°C

o
o

-3~

:z

TA-125°C

1.5
2.0
2.5
3.0
Vout, OUTPUT VOLTAGE (V)

I f Wr-

~IEXPEC~ED MINI~UM', ~A = 25-1125°C _

1.5

I-

F 7 ~TYPI6AL

~

~

~

<-

"5

0.5

-

£. r--

-35

2

35
30

.....

Figure 25. VGS

z

Figure 26. VGS

 ?

-=

GND OR VEE

GNDORVEE

Figure 34. Analog 1/0 Pin
BUS TERMINATION
ENABLE INPUT
(LOW = 3-STATE)

Because buses tend to operate in harsh, noisy environments, most bus lines are terminated via a resistor to V CC or
ground. This low impedance to VCC or ground (depending on
preference of a pull-up or pull-down logic level) reduces bus
noise pickup. In certain cases a bus line may be released
(put in a high-impedance state) by disabling all the 3-state
bus drivers (see Figure 35). In this condition all HC/HCT inputs on the bus would be allowed to float. A CMOS input or
1/0 pin (when selected as an input) should never be allowed
to float. (This is one reason why an HCT device may not be a
drop-in replacement of an LSTTL device.) A floating CMOS
input can put the device into the linear region of operation. In
this region excessive current can flow and the possibility of
logic errors due to oscillation may occur (see Inputs, this
chapter). Note that when a bus is properly terminated with
pull-up resistors, HC devices, instead of HCT devices, can
be driven by an NMOS or LSTTL bus driver. HC devices are
preferred over HCT devices in bus applications because of
their higher low level input noise margin. (With a 5 V supply
the typical HC switch pOint is 2.3 V while the switch point of
HCT is only 1.3 V.)
Some popular LSTTL bus termination designs may not
work for HSCMOS devices. The outputs of HSCMOS may
not be able to drive the low value of termination used by
some buses. (This is another reason why an HCT device
may not be a drop in replacement for an LSTTL device.)
However, because low power operation is one of the main
reasons for using CMOS, an optimized CMOS bus termination is usually advantageous.

Figure 35. Typical Bus Line with 3-5tate Bus Drivers

The choice of termination resistances is a trade-off between speed and power consumption. The speed of the bus
is a function of the RC time constant of the termination resistor and the parasitic capacitance associated with the bus.
Power consumption is a function of whether a pull-up or
pull-down resistor is used and the output state of the device
that has control of the bus (see Figure 36). The lower the termination resistor the faster the bus operates, but more power
is consumed. A large value resistor wastes less power, but
slows the bus down. Motorola recommends a termination resistor value between 1 kO and 1 MO. An alternative to a passive resistor termination would be an active-type termination
(see Figure 37). This type termination holds the last logic level on the bus until a driver can once again take control of the
bus. An active termination has the advantage of consuming a
minimal amount of power. Most HC/HCT bus drivers do not
have built-in hysteresis. Therefore, heavily loaded buses
can slow down rise and fall signals and exceed the input rise/
fall time defined in JEDEC Standard No. 7A. In this event,
devices with Schmitt-triggered inputs should be used to
condition these slow signals.

Vee
BUS
Vee

Vee

R

(H) ----t--e

(L)---+-e
..J..

I

BUS

.L

(a) USING A PULL-UP RESISTOR

(b) USING A PULL-DOWN RESISTOR

Figure 36.

MOTOROLA

2-13

High-Speed CMOS Logic Data
DL129-Rev6

121

Design Considerations
shown in Figure 39. Note that the resistor values in Figure 39
are twice the resistor value of Figure 38; this gives a net
equivalent termination value of Figure 38. Even higher values of resistors may be used for either termination method.
This reduces power consumption, but at the expense of
speed and possible signal degradation.

f--I
I
I
I
I

r---

BUS LINES

Vee

Figure 38. Termination Resistors at the Receiver
ENABLE

Vee

Figure 37. Using Active Termination (HC125)

Vee

Rt

TRANSMISSION LINE TERMINATION
When data is transmitted over long distances, the line on
which. the data travels can be considered a transmission line.
(Long distance is relative to the data rate being transmitted.)
Examples of transmission lines include high-speed buses,
long PCB lines,coaxial and ribbon cables. All transmission
lines should be properly terminated into a low-impedance
termination. A low-impedance termination helps eliminate
noise, ringing, .overshoot, and crosstalk problems. Also a
low-impedance termination reduces signal degradation because the .small values of parasitic line capacitance and inductance have lesser effect on a low-impedance line.
The value of the termination resistor becomes a trade-off
between power consumption, data rate speeds, and transmission line distance. The lower the resistor value, the faster
data can be presented to the receiving device, but the more
power the resistor consumes. The higher the resistor value,
the longer it will take to charge and discharge the transmission line through the termination resistor (T =R • C).
Transmission line distance becomes more critical as data
rates increase. As data rates increase, incident (and reflective) waves begin to resemble that of RF transmission line
theory. However, due to the nonlinearity of CMOS digital logic, conventional RF transmission theory is not applicable.
HC devices are preferred over HCT devices due to the fact
that HC devices have higher switch pOints than HCT devices.
This higher switch point allows HC devices to achieve better
incident wave switching on lower impedance lines.
HC/HCT may not have enough drive capability to interface
with some of the more popular LSTTL transmission lines.
(Possible reason why an HCT device may not be a drop-in
replacement of an equivalent TTL device.) This does not
pose a major problem since having larger value termination
resistors is desirable for CMOS type transmission lines.
By increasing the termination resistance value, the CMOS
advantage of low power consumption can be realized.
Motorola recommends a minimum termination resistor value
as shown in Figure 38. The termination resistor should be as
close to the receiving unit as possible. Another method of terminating the line driver, as well as the receiving unit, is

MOTOROLA

R2
Rt =R3=3.0kQ
R2=R4=2kQ

Figure 39. Termination Resistors at
Both the Line Driver and Receiver

CMOS LATCH UP
Typically, HSCMOS devices do not latch up with currents
of 75 mA forced into or out of the inputs or 300 mA for the
outputs under worst case conditions (TA = 125°C and VCC =
6 V). Under dc conditions for the inputs, the input protection
network typically fails, due to grossly exceeding the maximum input voltage rating of-l.5to VCC+ 1.5 V before latchup currents are reached. For most designs, latch up will not
be a problem, but the designer should be aware of it, what
causes it, and how it can be prevented.
Figure 40 shows the layout of a typical CMOS inverter and
Figure 41 shows the paraSitic bipolar devices that are
formed. The circuit formed by the parasitic transistors and re-.
sistors is the basic configuration of a silicon controlled rectifier, or SCR. In the latch-up condition, transistors 01 and 02
are turned on, each providing the base current necessary for
the other to remain in saturation, thereby latching the device
on. Unlike a conventional SCR, where the device is turned
on by applying a voltage to the base of the NPN transistor,
the parasitiC SCR is turned on by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be greater than VCC + 0.5 V or less than - 0.5 V and have sufficient
current to trigger the SCR. The latch-up mechanism is similar for the inputs.
Once a CMOS device is latched up, if the supply current is
not limited, the device can be destroyed or its reliability can
be degraded. Ways to prevent such an occurrence are listed
below.

2-14

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
1. Industrial controllers driving relays or motors is an environment in which latch up is a potential problem. Also,
the ringing due to inductance of long transmission lines
in an industrial setting could provide enough energy to
latch up CMOS devices. Opta-isolators, such as
Motorola's MOC3011, are recommended to reduce
chances of latch up. See the Motorola Semiconductor
Master Selection Guide for a complete listing of
Motorola opta-isolators.
2. Ensure that inputs and outputs are limited to the maximum rated values.

Another method of protection is to use a series resistor
to limit the expected worst case current to the maximum
ratings value. See Handling Precautions for other
possible protection circuits and a discussion of ESD
prevention.
4. Sequence power supplies so that the inputs or outputs
of HSCMOS devices are not active before the supply
pins are powered up (e.g., recessed edge connectors
and/or series resistors may be used in plug-in board applications).
5. Voltage regulating and filtering should be used in board
design and layout to ensure that power supply lines are
free of excessive noise.
6. Limit the available power supply current to the devices
that are subject to latch-up conditions. This can be accomplished with the power-supply filtering network or
with a current-limiting regulator.

-1.5 :5 Vin :5 VCC +1.5 V referenced to GND or
- 0.5 :5 Vin :5 VCC +0.5 V referenced to GND
- 0.5 :5 Vout :5 VCC +0.5 V referenced to GND
lIinl :5 20 mA
lIoutl :5 25 mA for standard outputs
lIoutl :5 35 mA for bus-driver outputs

RECOMMENDED READING

3. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.

Paul Mannone, "Careful Design Methods Prevent CMOS
Latch-Up", EDN, January 26,1984.

P-CHANNEL

N-CHANNEL
INPUT

FIELD OXIDE

Figure 40. CMOS Wafer Cross Section

P-CHANNEL OUTPUT

P - WELL RESISTANCE

~_~+

VCC
VCC

:~-

01

_ _ _---.------'

~'I/VIv
~P:GND
~~-------------------~~------------------P---N~ N+ ~ ----------,JL
-=

GND

02
N- SUBSTRATE RESISTANCE

N-CHANNEL OUTPUT

Figure 41. Latch-Up Circuit Schematic

MOTOROLA

2-15

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
Worst-case ICC occurs at VCC = 6.0 V. The value of ICC at
VCC = 6.0 V, as specified in the data sheets, is used for all
power supply voltages from 2 to 6 V.

MAXIMUM POWER DISSIPATION
The maximum power dissipation for Motorola HSCMOS
packages is 750 mW for both ceramic and plastic DIPs and
500 mW for SOIC packages. The deratings are - 10 mW/oC
from 65°C for plastic DIPs, - 10 mW/oC from 100°C for
ceramic packages, and - 7 mW/oC from 65°C for.SOIC
packages. This is illustrated in Figure 42.

Iz

800

~

SOIC
PACKAGE> -

-

I-

\

s:

PLASTIC_
DIP

I

0
"- 400

/

w

C!l

;2 300

TSSOP
PACKAGE

0

Cf.
::;; 200

~

x

\iDIP

,

~

~ \
~ 1\

"

:::>

::;;

Although HCT devices belong to the CMOS family, their input voltage specifications are identical to those of LSTTL.
HCT parts can therefore be either judiciously substituted for
or mixed with LS devices in a system.
TTL output voltages are VOL = 0.4 V (max) and VOH = 2.4
to 2.7 V (min).
Slightly higher ICC current exists when an HCT device is
driven with VOL = 0.4 V (max) because this voltage is high
enough to partially turn on the N-channel transistor. However, when being driven with a TTL VOH, HCT devices exhibit
large additional current flow (L\ICC) as specified on HCT device data sheets. L\ICC current is caused by the off-rail input
voltage turning on both the P and N channels of the input
buffer. This condition offers a relatively low impedance path
from VCC to GNO. Therefore, the HCT quiescent power dissipation is dependent on the number of inputs applied at the
TTL VIH logic voltage level.
The equation for HCT quiescent power diSSipation is given
by:

CERAMIC

'-

Q 700

en
en 600
0
a:
w 500

HCT QUIESCENT POWER DISSIPATION

100

~\

"

~

~

&?

-40

o
40
80
TA, AMBIENT TEMPERATURE (OC)

120

PD = ICCVCC + TJL\ICCVCC

Figure 42. Maximum Package Power
Dissipation versus Temperature

where TJ = the number of inputs at the TTL VIH level.

Internal heat generation in HSCMOS devices comes from
two sources, namely, the quiescent power and dynamic power consumption.
In the quiescent state, either the P-channel or N-channel
transistor in each complementary pair is off except for small
source-to-drain leakage due to the inputs being either at
VCC or ground. Also, there are the small leakage currents
flowing in the reverse-biased input protection diodes and the
parasitic diodes on the chip. The specification which takes all
leakage into account is called Maximum Quiescent Supply
Current (per package), or ICC, and is shown on all data
sheets.
The three factors which directly affect the value of quiescent power dissipation are supply voltage, device complexity,
and temperature. On the data sheets, ICC is specified only at
VCC = 6.0 V because this is the worst-case supply voltage
condition. Also, larger or more complex devices consume
more quiescent power because these devices contain a proportionally greater reverse-biased diode junction area and
more off (leaky) FETs.
Finally, as can be seen from the data sheets, temperature
increases cause ICC increases. This is because at higher
temperatures, leakage currents increase.

HC AND HCT DYNAMIC POWER DISSIPATION
Dynamic power dissipation is calculated in the same way
for both HC and HCT devices. The three major factors which
directly affect the magnitude of dynamic power dissipation
are load capacitance, internal capacitance, and switching
transient currents.
The dynamic power dissipation due to capacitive loads is
given by the following equation:
PD=CLVCC2f
where Po = power in IlW, CL = capacitive load in pF,
V CC = supply voltage in volts, and f = output frequency driving the load capacitor in MHz.
All CMOS devices have internal parasitic capacitances
that have the same effect as external load capacitors. The
magnitude of this internal no-load power dissipation capacitance, CPO, is specified as a typical value.
Finally, switching transient currents affect the dynamic
power dissipation. As each gate switches, there is a short period of time in which both N- and P-channel transistors are
partially on, creating a low-impedance path from VCC to
ground. As switching frequency increases, the power disSipation due to this effect also increases.
The dynamic power dissipation due to CpO and switching
transient currents is given by the following equation:

HC QUIESCENT POWER DISSIPATION
When HC device inputs are viriually at VCC or GNO potential (as in a totally CMOS system), quiescent power dissipation is minimized. The equation for HC quiescent power
diSSipation is given by:

Po = CPOVCC 2f
Therefore, the total dynamic power dissipation is given by:
Po = (CL + CpO)VCC 2f

PO=VCCICC

MOTOROLA

2-16

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
Total power dissipation for HC and HCT devices is merely
a summation of the dynamic and quiescent power dissipation.
elements. When being driven by CMOS logic voltage levels
(rail to rail), the total power dissipation for both HC and HCT
devices is given by the equation:
Po = VCCICC + (CL + CPO)VCC 2f

TJ

maximum junction temperature

TA

maximum ambient temperature

Po

calculated maximum power dissipation including
effects of external loads (see Power Oissipation
on page 2-16).

SJC

average thermal resistance,,iunction to case

SCA

average thermal resistance, case to ambient

SJA

average thermal resistance, junction to ambient

When being driven by LSTTL logic voltage levels, the total
power dissipation for HCT devices is given by the equation:
Po =VCCICC + VCC!1ICC(o, + 02 + ... + on)
+ (CL + CPO)VCC 2f
where on = duty cycle of LSTTL output applied to each input
of an HCT device.

This Motorola recommended formula has been approved
by RAOC and OESC for calculating a "practical" maximum
operating junction temperature for MIL-M-38510 (JAN) devices.
Only two terms on the right side of equation ( 1 ) can be
varied by the user - the ambient temperature, and the device case-to-ambient thermal resistance, SCA. (To some extent the device power dissipation can also be controlled, but
under recommended use the VCC supply and loading dictate
a fixed power dissipation.) Both system air flow and the package mounting technique affect the SCA thermal resistance
term. 9JC is essentially independent of air flow and external
mounting method, but is sensitive to package material, die
bonding method, and die area.
For applications where the case is held at essentially a
fixed temperature by mounting on a large or temperaturecontrolled heat sink, the estimated junction temperature is
calculated by:

THERMAL MANAGEMENT
Circuit performance and long-term circuit reliability are affected by die temperature. Normally, both are improved by
keeping the IC junction temperatures low.
Electrical power dissipated in any integrated circuit is a
source of heat. This heat source increases the temperature
of the die relative to some reference point, normally the ambient temperature of 25°C in still air. The temperature increase, then, depends on the amount of power dissipated in
the circuit and on the net thermal resistance between the
heat source and the reference point. See page 2-7 for the
calculation of CMOS power consumption.
The temperature at the junction is a function of the packaging and mounting system's ability to remove heat generated
in the circuit - from the junction region to the ambient environment. The basic formula for converting power dissipation
to estimated junction temperature is:
TJ=TA+PO(SJC+SCA)

(2 )

TJ = TA + PO(8JA)
where

TJ=TC+PO(SJC)
(3)
where TC = maximum case temperature and the other parameters are as previously defined.
The maximum and average SJC resistance values for standard IC packages are given in Table 2.

(1)

or

Table 2. Thermal Resistance Values for Standard lIe Packages
Thermal Resistance In Still Air
Package Description
'SJC (OClWatt)

No.
Leads

Body
Style

Body
Material

Body
WxL

Die
Bonds

Die Area
(Sq. Mils)

Flag Area
(Sg.Mils)

Avg.

Max.

14
16
20

OIL
OIL
OIL

Epoxy
Epoxy
Epoxy

1/4" x 3/4"
1/4"x 3/4"
0.35" x 0.35"

Epoxy
Epoxy
Epoxy

4096
4096
4096

6,400
12,100
14,400

38
34
N/A

61
54
N/A

NOTES:
1. All plastic packages use copper lead frames.
2. Body style OIL is "Dual-In· Line."
3. Standard Mounting Method: Dual-In-Line Socket or PIC board with no contact between bottom of package and socket or PIC board.

MOTOROLA

2-17

High-Speed CMOS Logic Oata
0L129-Rev6

121

Design Considerations
AIRFLOW

in the system should be evaluated for maximum junction
temperature. Knowing the maximum junction temperature,
refer to Table 4 or Equation ( 1 ) on page 2-17 to determine
the continuous operating time required to 0.1 % bond failures
due to intermetallic formation. At this time, system reliability
departs from the desired value as indicated in Figure 43.
Air flow is one method of thermal management which
should be considered for system longevity. Other commonly
used methods include heat sinks for higher powered devices, refrigerated air flow and lower density board stuffing.
Since SCA is entirely dependent on the application, it is the
responsibility of the designer to determine its value. This can
be achieved by various techniques including simulation,
modeling, actual measurement, etc.
The material presented here emphasizes the need to consider thermal management as an integral part of system design and also the tools to determine if the management
methods being considered are adequate to produce the desired system reliability.

The effect of air flow over the packages on SJA (due to a
decrease in SCA) reduces the temperature rise of the package, therefore permitting a corresponding increase in power
dissipation without exceeding the maximum permissible operating junction temperature.
Even though different device types mounted on a printed
circuit board may each have different power dissipations, all
will have the same input and output levels provided that each
is subject to identical air flow and the same ambient air temperature. This eases design, since the only change in levels
between devices is due to the increase in ambient temperatures as the air passes over the devices, or differences in
ambient temperature betweeri two devices.
The majority of users employ some form of air-flow cooling. As air passes over each device on a printed circuit
board, it absorbs heat from each package. This heat gradient
from the first package to the last package is a function of the
air flow rate and individual package dissipations. Table 3 provides gradient data at power levels of 200 mW, 250 mW, 300
mW, and 400 mW with an air flow rate of 500 Ifpm. These
figures show the proportionate increase in the junction temperature of each dual in-line package as the air passes over
each device. For higher rates of air flow the change in junction temperature from package to package down the airstream will be lower due to greater cooling.

Table 4. Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C

Time, Hours

Time, Years

80

1,032,200

117.8

90

419,300

47.9

100

178,700

20.4

Table 3. Thermal Gradient of Junction Temperature
(16-Pin Dual-In-Line Package)
Power Dissipation
(mW)

Junction Temperature Gradient
COC/Package)

200

0.4

250

0.5

300

0.63

400

0.88

w

~

Devices mounted on 0.062" PC board with Z axis spacIng of 0.5".
Air flow is 500 "pm along the Z axis.

w

a:

3

~
Cl

Table 4 is graphically illustrated in Figure 43 which shows
that the reliability for plastiC and ceramic devices is the same
until elevated junction temperatures induce intermetallic failures in plastic devices. Early and mid-life failure rates of plastic devices are not effected by this intermetallic mechanism.

I

.%

79,600

9.4

37,000

4.2

130

17,800

2.0

140

8,900

1.0

FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR

•.
0

~

t-~- ~

"
r-p

p"

'

0

°

0
0

~-§-

" "
F.I-r

p
0

'"

P

0

ClO

p"
It
+

p"

1 I III I 1
10

100

1000

TIME, YEARS

PROCEDURE
After the desired system failure rate has been established
for failure mechanisms other than intermetallics, each device

MOTOROLA

110
120

Figure 43. Failure Rate versus Time
Junction Temperature

2-18

High Speed CMOS Logic Data
DL129-Rev6

Design Considerations
tpT = tp + 0.5 VCC (CL - 50 pF)/lOS

CAPACITIVE LOADING EFFECTS
ON PROPAGATION DELAY

where tpT = total propagation delay
tp = specified propagation delay with 50 pF load

In addition to temperature and power-supply effects, capacitive loading effects should be taken into account. The
additional propagation delay may be calculated if the short
circuit current for the device is known. Expected minimum
numbers may be determined from Table 5.
From the equation
.

CL = actual load capacitance
lOS = short circuit current (Table 5)
An example is given here for tPHL of the 74HCOO driving a
150 pF load.
VCC=4.5V

Cdvc

tpHL (50 pF) = 18 ns

1=-dt

CL = 150 pF

this approximation follows:

lOS = 17.3 mA
(0.5)(4.5 V)(150 pF - 50 pF)
)
tpHL (150 pF = 18 ns +
17.3 mA

so
= 18 ns + 13 ns

~t = C~V

=31

I

ns

Another example for CL = 0 pF and all other parameters the
same.

or

~t = C(0.5 VCC)
---'--I-=-=

(0.5)(4.5 V)(O pF - 50 pF)
()
tpHL 0 pF = 18 ns +
17.3 mA

because the propagation delay is measured to the 50% point
of the output waveform (typically 0.5 VCC).
This equation gives the general form of the additional propagation delay. To calculate the propagation delay of a device
for a particular load capacitance, CL, the following equation
may be used.

= 18 ns + (- 6.5 ns)
tPHL = 11.5 ns
This method gives the expected propagation delay and is intended as a design aid, not as a guarantee.

Table 5. Expected Minimum Short Circuit Currents'
Standard Drivers
Parameter

Bus Drivers

Vee

25°e

85°e

125°e

25°e

85°e

125°e

Unit

Output Short Circuit Source Current

2.0
4.5
6.0

1.89
18.5
35.2

1.83
15.0
28.0

1.80
13.4
24.6

3.75
37.0
70.6

3.64
30.0
56.1

3.60
26.6
49.2

mA

Output Short Circuit Sink Current

2.0
4.5
6.0

1.55
17.3
33.4

1.55
14.0
26.5

1.55
12.5
23.2

2.45
27.2
52.6

2.45
22.1
41.7

2.43
19.6
36.5

mA

• These values are mtended as design aids, not as guarantees.

MOTOROLA

2-19

High-Speed CMOS Logic Data
DL129- Rev 6

Design Considerations
TEMPE~ATURE

EFFECTS ON
DC AND AC PARAMETERS

SUPPLY VOLTAGE EFFECTS ON DRIVE
CURRENT AND PROPAGATION DELAY
The transconductive gain, 10utNin, of MOSFETs is proportional to the gate voltage minus the threshold voltage,
V G - VT. The gate voltage at the input of the final stage of
buffered devices is approximately the power supply voltage,
Vce or GND. Because VG =Vec or GND, the output drive
current is proportional to the supply voltage. Propagation delays for CMOS devices are also affected by the power supply
voltage, because most of the delay is due to charging and
discharging internal capacitances. Figure 46 and Figure 47
show the typical variation of current drive and propagation
delay, normalized to Vee = 4.5 V for 2.0 :s; Vec :s; 6.0 V.
These curves may be used with the tables on each data
sheet to arrive at parametric values over the voltage range.

One of the inherent advantages of CMOS devices is that
characteristics of the N- and P-channel transistors, such as
drive current, channel resistance, propagation delay, and
output transition time, track each other over a wide temperature range. Figure 44 shows the temperature relationships
for these parameters. To illustrate the effects of temperature
on noise margin, Figure 45 shows the typical transfer characteristics for devices with buffered inputs and outputs. Note
that the typical switch point is at 45% of the supply voltage
and is minimally affected by temperature.
The graphs in this section are intended to be design aids,
not guarantees.
1.5

I-

1\

./

\

I'

0.5

a:~

~>t.2

."

~/

~~

"'- ........... r-......

!5
0 1.0
01-

--

....Cl

~~0.8

I

-50

I

I

o

I

""0

~~0.4 /"
o

I
100

50

150

0.2
2.0

TA. AMBIENT TEMPERATURE (Oe)

II

~
~ 3.0

TA =1-55~4-

>

I:::>

o

3.0

4.0

~

5.0

6.0

Figure 46. Drive Current versus VCC

I
eL=50pF -

-

I

UJ

13

/'

V

I
I
Vee=5Vdc -

1)

~ 4.0

./

-'

--'

Vee. POWER SUPPLY VOLTAGE (V)

Figure 44. Characteristics of Drive Current,
Channel Resistance, and AC F'arameters
Over Temperature

5.0

V

a:::~

~il!!0.6

IOH.IOL-Re, tPLH. tpHL. trLH. trHL - - -

I

-

~ ~1.4

~.

./
./

offi

-"

~

1.8

~ _1.6
!5

-..

2.0

I

TA = 125°e

;

i

VIL

I

" --'-...

~

I

I-- VIH_

TA = 25°e

r--

II

l

o
o

t.O

2.0

3.0

4.0

5.0

2.0

Vin. INPUT VOLTAGE (V)

4.0

5.0

6.0

Vee. POWER SUPPLY VOLTAGE (V)

Figure 45. Temperature Effects on the HC
Transfer Characteristics

MOTOROLA

3.0

Figure 47. Propagation Delay versus VCC

2-20

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
DECOUPLING CAPACITORS

INTERFACING
HSCMOS devices have a wide operating voltage range
(VCC =2 to 6 V) and sufficient current drive to interface with
most other logic families available today. In this section, various interface schemes are given to aid the designer (see
Figure 50 through Figure 55). The various types of CMOS
devices with their inpuVoutput levels and comments are given in Table 6.
Motorola presently has available several CMOS memories
and microprocessors (see Table 7) which are designed to directly interface with High-Speed CMOS. With these devices
now available, the designer has an attractive alternative to
LSTTUNMOS, and a total HSCMOS system is now possible.
(See SG1 02, CMOS System IC Selection Guide, for more information.)
Device designators are as follows:
HC
This is a high-speed CMOS device with CMOS input
switching levels and buffered CMOS outputs. The
numbering of devices with this deSignator follows the
LSTTL numbering sequence. These devices are
functional and pinout equivalents of LSTTL devices
(e.g., HCOQ, HC688, etc.). Exceptions to this are
devices that are functional and pinout equivalents to
metal-gate CMOS devices (e.g., HC4002, HC4538A,
etc.).
HCU This is an unbuffered high-speed CMOS device with
only one stage between the input and output. Because
this is an unbuffered device, input and output levels
may differ from buffered devices. At present, the
family contains only one unbuffered device, the
HCU04A.
HCT This is a high-speed CMOS device with an LSTTLto-CMOS input buffer stage. These devices are
designed to interface with LSTTL outputs operating at
VCC = 5 V ± 10%. HCT devices have fully buffered
CMOS outputs that directly drive HSCMOS or LSTTL
devices.

The switching waveforms shown in Figure 48 and
Figure 49 show the current spikes introduced to the power
supply and ground lines. This effect is shown for a load capacitance of less than 5 pF and for 50 pF. For ideal power
supply lines with no series impedance, the spikes would
pose no problem. However, actual power supply and ground
lines do possess series impedance, giving rise to noise problems. For this reason, care should be taken in board layouts,
ensuring low impedance paths to and from logic devices.
To absorb switching spikes, the following HSCMOS
devices should be bypassed with good quality 0.022 IlF to
0.1 IlF decoupling capacitors:
1. Bypass every device driving a bus with all outputs
switching simultaneously.
2. Bypass all synchronous counters.
3. Bypass devices used as oscillator elements.
4. Bypass Schmitt-trigger devices with slow input rise and
fall times. The slower the rise and fall time, the larger the
bypass capacitor. Lab experimentation is suggested.
Bypass capacitors should be distributed over the circuit
board. In addition, boards could be decoupled with a 1 IlF
capacitor.

=>

o

>

\
I

n
Cl

z
.£l

I

II1/
II

\
I

I

1/\

In

n

1

it

It

t

1\

11\

!

1\

II

----~~------------------~----VCC

BUFFERED DEVICE: INPUT tr, tf :;; 500 ns, CL < 5 pF

Figure 48. Switching Currents for CL < 5 pF

I

=>

o

>

----~~------------------~----GND

HC OR HCT
DEVICE

\

DIRECT
INTERFACE

LSTIL
DEVICE

Figure 50. HC to LSTTL Interfacing
'-'
9

----~------------------4r-----VCC

IA

A

------~------------------~------GND

LSTIL
DEVICE

BUFFERED DEVICE: INPUT tr, tf:;; 500 ns, CL < 5 pF

Figure 49. Switching Currents for CL

MOTOROLA

=50 pF

DIRECT
INTERFACE

HCT
DEVICE

Figure 51. LSTTL to HCT Interfacing

2-21

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
VCC~2-6V

VDD~3-1SV'

----~--------~--------~-----VCC

----~~----~~~----~~~----GND

-----+--------~--------~-----GND

PULL-UP
RESISTOR

STANDARD
CMOS

Figure 52. LSTTL to HC Interfacing

MCI4049UBI140S0B
OR
HC4049/HC40S0

'VOH must be greater than VIH of low voltage Device;
VDD = 3-18 V may be used if interfacing to 14049UB/140S0B.

Figure 54. High Voltage CMOS to HSCMOS
r---------~----3V

SV

GND----~--------~~------~~----GND

LSTIL
DEVICE

HC4049
OR
HC4oso

HC
DEVICE

GND

GND ---+--------'
HSCMOSI
STANDARD CMOS

Figure 53. LSTTL to Low-Voltage HSCMOS

STANDARD CMOSI
HSCMOS

Figure 55. Up/Down Level Shifting Using
the MC14504B
Table 6. Interfacing Guide
Device

Input Level

Output Level

HCXXX

CMOS

CMOS

LSTIL Functional and Pinout Equivalent Devices

Comments

HC4XXX

CMOS

CMOS

CMOS Functional and Pinout Equivalent Devices

HCUXX

CMOS

CMOS

Used in Linear Applications

HCTXXX

TIL

CMOS

HSCMOS Device with TIL-to-CMOS Input Buffering

HC4049,
HC4050

-O.S s Vin s 15V

CMOS

High-to-Low Level Translators, CMOS Switching Levels

MC14049UB
MC140S0B

- O.S s Vin s 18 V

CMOS

Metal-Gate CMOS High-to-Low Level Translators, CMOS Switching Levels

MC14S04B

CMOS or TIL

CMOS

Metal-Gate CMOS High-to-Low or Low-to-High Level Translator

Table 7. CMOS Me'morles and Microprocessors
CMOS
Memories
MCM6147
MCM61L47
MCM68HC34

MOTOROLA

RECOMMENDED READING
CMOS Microprocessors
MC68HCOI
MC68HC03
MC68HC11A8
MC68HC11D4
MC68HC811A2
MC68HC811D4
MC68HC04P3
MC14680SE2
MC14680SF2

S. Craig, "Using High-Speed CMOS Logic for Microprocessor Interfacing", Application Note-868, Motorola Semiconductor Products Inc" 1982.

MC146805G2
MC14680SH2
MC146870SF2
MC146870SG2
MC68HC05C4
MC68HSCOSC4
MC68HCOSC8
MC68HC80SC4
MC68HCOOO

2-22

High-Speed CMOS Logic Data
DL129'- Rev 6

Design Considerations
tion to the end user. However, this does not hold true for the
mean value of the total devices processed. The mean value,
commonly referred to as a typical value, shifts over processing and therefore varies from lot to lot or even wafer to wafer
within a lot.
As with all processing or manufacturing, the total devices
being produced fit the normal distribution or bell curve of
Figure 56. In order to guarantee a valid typical value, a typical number plus a tolerance, would have to be specified and
tested (see Figure 57). However, this would greatly increase
processing costs which would have to be absorbed by the
consumer.
In some cases, the device's actual values are 50 small that
the resolution of the automatic test equipment determines
the guaranteed limit. An example of this is quiescent supply
current and input leakage current.
Most manufacturers provide typical numbers by one of two
methods. The first method is to simply double or halve, depending on the parameter, the guaranteed limit to determine
a typical number. This would theoretically put all processed
lots in the middle of the process window. Another approach
to typical numbers is to use a typical value that is derived
from the aforementioned experimental lots. However, neither
method accurately reflects the mean value of devices any
one consumer can expect to receive.
Therefore, the use of typical parametric numbers for design purposes does not constitute sound engineering design
practice. Worst case analysis dictates the use of guaranteed
minimum or maximum values. The only possible exception
would be when no guaranteed value is given. In this case a
typical value may be used as a ballpark figure.

TYPICAL PARAMETRIC VALUES
Given a fixed voltage and temperature, the electrical characteristics of High-Speed CMOS devices depend primarily
on design, layout, and processing variations inherent in
semiconductor fabrication.
A preliminary evaluation of each device type essentially
guarantees that the design and layout of the device conforms
to the criteria and standards set forth in the design goals.
With very few exceptions, device electrical parameters, once
established, do not vary due to design and layout.
Of much more concern is processing variation. A digital
processing line is allowed to deviate over a fairly broad processing range. This allows the manufacturer to incur reduced
processing costs. These reduced processing costs are
passed on to the consumer in the form of lower device
prices.
Processing variation is the range from worst case to best
case processing and is defined as the process window. This
window is established. with the aid of statistical process control (SPC). With SPC, when a processing parameter approaches the process window limit, that parameter is
adjusted toward the middle of the window. This keeps process variations within a predetermined tolerance.
Motorola characterizes each device type over this process
window. Each device type is characterized by allowing experimental lots to be processed using worst case and best
case processing. The worst case processed lots usually determine the minimum or maximum guaranteed limit. (Whether the limit is a guaranteed minimum or maximum depends
on the particular parameter being measured.)
In production, these limits are guaranteed by probe and final test and therefore appear independent of process varia-

REJECT
REGION

REJECT
REGION

(a)

(b)

Figure 56.

MEAN (TYP)
VALUE

REJECT
REGION

REJECT
REGION

Figure 57.

MOTOROLA

2-23

High-Speed CMOS Logic Data
DL129-Rev6

121

Design Considerations
REDUCTION OF ELECTROMAGNETIC
INTERFERENCE (EM I)

and polyester SMC with carbon-fiber veil. Several manufacturers who make conductive compounds and additives are
listed below.

Electromagnetic interference (EMI) and radio frequency
interference (RFI) are phenomena inherent in all electrical
systems covering the entire frequency spectrum. Although
the characteristics have been well documented, EMI remains
difficult to deal with due to numerous variables. EMI should
be considered at the beginning of a design, and taken into
account during all stages, including production and beyond.
These entities must be present for EMI to be a factor: (1) a
source of EMI, (2) a transmission medium for EMI, and (3) a
receiver of EMI. Several sources include relays, FM transmitters, local oscillators in receivers, power lines, engine ignitions, arc welders, and lighting. EMI transmission paths
include ground connections, cables, and the space between
conductors. Some receivers of EMI are radar receivers, computers, and television receivers.
For microprocessor based equipment, the source of emissions is usually a current loop on a PC board. The chips and
their associated loop areas also function as receivers of EMI.
The fact is that PC boards which radiate high levels of EMI
are also more likely to act as receivers of EMI.
All logic gates are potential transmitters and receivers of
emissions. Noise immunity and noise margin are two criterion which measure a gate's immunity to noise which could be
caused by EMI. CMOS technology, as opposed to the other
commonly used logic families, offers the best value for noise
margin, and is therefore an excellent choice when consideringEMI.
The electric and magnetic fields associated with ICs are
proportional to the current used, the current loop area, and
the switching transition times. CMOS technology is preferred
due to smaller currents. Also, the current loop area can be
reduced by the use of surface mount packages.
In a system where several pieces of equipment are connected by cables, at least five coupling paths should be taken into account to reduce EMI. They are: (1) common ground
impedance coupling (a common impedance is shared between an EMI source and receiver), (2) common-mode,
field-to-cable coupling (electromagnetic fields enter the loop
found by two pieces of equipment, the cable connecting
them, and the ground plane), (3) differential-mode, field-tocable coupling (electromagnetic fields enter the loop formed
by two pieces of equipment and the cable connecting them),
(4) crosstalk coupling (signals in one transmission line are
coupled into another transmission line), and (5) a conductive
path through power lines.
Shielding is a means of reducing EMI. Some of the more
commonly used shields against EMI and RFI contain stainless steel fiber-filled polycarbonate, aluminum flake-filled
polycarbonate/ABS coated with nickel and copper electrolysis plating or cathode sputtering, nickel coated graphite fiber,

MOTOROLA

SHIELDING MANUFACTURERS
General Electric Co., Plastics Group, Pittsfield, MA
Mobay Chemical Corp., Pittsburgh, PA
Wilson-fiberfillnternational, Evansville, IN
American Cyanamid Co., Wayne, NJ
Fillite U.S.A., Inc., Huntington, WV
Transnet Corp., Columbus, OH
Motorola does not recommend, or in any way warrant the
manufacturers listed here. Additionally, no claim is made that
this list is by any means complete.
RECOMMENDED READING
D. White, K. Atkinson, and J. Osburn, "Taming EMI in Microprocessor Systems", IEEE Spectrum, Vol. 22, Number 12,
Dec. 1985.
D. White and M. Mardiguian, EMI Control Methodology and
Procedures, 1985.
H. Denny, Grounding for the Control of EMI.
M. Mardiguian, How to Control Electrical Noise.
D. White, Shielding Design Methodology and Procedures.
For more information on this subject, contact:
Interference Control Technologies
Don White Consultants, Inc., Subsidiary
State Route 625
P.O. Box D
Gainesville, VA 22065

HYBRID CIRCUIT GUIDELINES
High-Speed CMOS devices, when purchased in chip (die)
form, are useful in hybrid circuits. Most high-speed devices
are fabricated with P wells and N substrates. Therefore, the
substrates should be tied to VCC (+ supply).
Several devices however, are fabricated with N wells and
P substrates. In this case, the substrates should be tied to
GND. The best solution to alleviate confusion about the substrate is the use of nonconductive or insulative substrates.
This averts the necessity of tying the substrate off to either
VccorGND.
For more information on hybrid technology, contact:
International Society for Hybrid Microelectronics
P.O. Box 3255
Montgomery, AL 36109

2-24

High-Speed CMOS Logic D!lta
DL129-Rev6

Design Considerations
signals with long rise and fall times. Positive-going input
noise excursions must rise above the VT+ threshold before
they affect the output. Similarly, negative-going input noise
excursions must drop below the VT_ threshold before they affect the output.
The HC132A can be used as a direct replacement for the
HCOOA NAND gate, which does not have Schmitt-trigger capability. The HC132A has the same pin assignment as the
HCOOA. Schmitt-trigger logic elements act as standard logic
elements in the absence of noise or slow rise and fall times,
making direct substitution possible.
Versatility and low cost are attractive features of CMOS
Schmitt triggers. With six Schmitt triggers per HC14A package, one trigger can be used for a noise elimination application while the other five function as standard inverters.
Similarly, each of the four triggers in the HC132A can be
used as either Schmitt triggers or NAND gates or some combination of both.

SCHMITT-TRIGGER DEVICES
Schmitt-trigger devices exhibit the effect of hysteresis.
Hysteresis is characterized by two different switching threshold levels, one for positive-going input transitions and the
other for negative-going input transitions.
Schmitt triggers offer superior noise immunity when
compared to standard gates and inverters. Applications for
Schmitt triggers include line receivers, sine to square wave
converters, noise filters, and oscillators. Motorola offers six
versatile Schmitt-trigger devices in the High-Speed CMOS
logic family (see Table 8).
The typical voltage transfer characteristics of a standard
CMOS inverter and a CMOS Schmitt-trigger inverter are
compared in Figure 58 and Figure 59. The singular transfer
threshold of the standard inverter is replaced by two distinct
thresholds in a Schmitt-trigger inverter. During a positivegoing transition of Vin, the output begins to go low after the
VT+ threshold is reached. During a negative-going Vin transition, Vout begins to go high after the VT_ threshold is reached.
The difference between VT+ and VT_ is defined as VH, the
hysteresis voltage.
As a direct result of hysteresis, Schmitt-trigger circuits
provide excellent noise immunity and the ability to square up

Table 8. Schmitt-Trigger Devices
HC14A
HCT14A
HC132A

Hex Schmitt-Trigger Inverter
Hex Schmitt-Trigger Inverter with LSTTL Inputs
Quad 2-lnput NAND Gate with Schmitt-Trigger
Inputs

Vee 1-----_.

Vout

Vee
Figure 58. Standard Inverter Transfer Characteristic

Veel-----~-~

Vout

Vee
Figure 59. Schmitt-Trigger Inverter Transfer Characteristic

MOTOROLA

2-25

High-Speed CMOS Logic Data
DL129-Rev6

Design Considerations
Certain constraints must be met while designing this type
of oscillator. Stray capacitance and inductance must be kept
to a minimum by placing the passive components as close to
the chip as possible. Also, at higher frequencies, the
HCU04's propagation delay becomes a dominant effect and
affects the cycle time. A polystyrene capacitor is recommended for optimum performance.

OSCILLATOR DESIGN WITH HIGH-SPEED CMOS
Oscillator design is a fundamental requirement of many
systems and several types are discussed in this section. In
general, an oscillator is comprised of two parts: an active network and a feedback network. The active network is usually
in the form of an amplifier, or an unbuffered inverter, such as
the HCU04. The feedback network is mainly comprised of resistors, capacitors, and depending upon the application, a
quartz crystal or ceramic resonator.
Buffered inverters are never recommended in oscillator
applications due to their high gain and added propagation
delay. For this reason Motorola manufactures the HCU04,
which is an unbuffered hex inverter.
Oscillators for use in digital systems fall into two general
categories, RC oscillators and crystal or ceramic resonator
oscillators. Crystal oscillators have the best performance, but
are more costly, especially for nonstandard frequencies. RC
oscillators are more useful in applications where stability and
accuracy are not of prime importance. Where high performance at low frequencies is desired, ceramic resonators are
sometimes used.

CRYSTAL OSCILLATORS

Crystal oscillators provide the required stability and accuracy which is necessary in many applications. The crystal
can be modeled as shown in Figure 62.
The power dissipated in a crystal is referred to as the drive
level and is specified in mW. At low drive levels, the resonant
resistance of the crystal can be so large as to cause start-up
problems. To overcome this problem, the amplifier (inverter)
should provide enough amplification, but not too much as to
overdrive the crystal.
Figure 61 shows a Pierce crystal oscillator circuit, which is
a popular configuration with CMOS.
1/6 HCU04

RC OSCILLATORS

The circuit in Figure 60 shows a basic RC oscillator using
the HCU04. When the input voltage of the first inverter reaches the threshold voltage, the outputs of the two inverters
change state, and the charging current of the capacitor
changes direction. The frequency at which this circuit oscillates depends upon R1 and C. The equation to calculate
these component values is given in Figure 60.
1/6 HCU04

1/6 HCU04

Rf

Choosing R1
C::2:100pF
1 kQ:::;Rl:::;1 MQ

Power is dissipated in the effective series resistance of the
crystal. The drive level specified by the crystal manufacturer
is the maximum stress that a crystal can withstand without
damage or excessive shift in frequency. R1 limits the drive
level.

1
fose = 2.3 Rl.C

Figure 60. RC Oscillator

Rs

1

0

BUFFER

Figure 61. Pierce Crystal Oscillator Circuit

Rl

0-----f

OSCout2

BUFFER
Vout

R2

1/6 HCU04
OSCou tl

OSCin

2

1------0

==

Ls

1

Cs

Y ==~

CO

L -_ _--!

Values are supplied by the crystal manufacturer
(parallel resonant crystal)

Figure 62. Equivalent Crystal Networks

MOTOROLA

2-26

High-Speed CMOS Logic Data
DL129 - Rev 6

Design Considerations
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency at OSC
Out 2. The frequency should increase very slightly as the dc
supply voltage is increased. An overdriven crystal decreases
in frequency or becomes unstable with an increase in supply
voltage. The operating supply voltage must be reduced or RI
must be increased in value if the overdriven condition exists.
The user should note that the oscillator start-up time is proportional to the value of R1.

supply lines are peak current in output stages during switching and the charging and discharging of parasitic capacitances.
A good power distribution network is essential before decoupling can provide any noise reduction. Avoid using jumpers for ground and power connections; the inductance they
introduce into the lines permits coupling between outputs.
Therefore, use of PC boards with premanufactured ground
connections is advised to connect the device pins to ground.
However, the optimum solution is to use multi-layer PC
boards where different layers are used for the supply rails
and interconnections. Even with double-sided boards, placing the power and ground lines on opposite sides ot the
board whenever possible is recommended. The multi-wire
board is a less expensive approach than the multi-layer PC
board, while retaining the same noise reduction characteristics. As a rule of thumb, there should be several ground pins
per connector to give good ground distribution.
The precautions for ground lines also apply to VCC lines:
1) separate power stabilization for each board; 2) isolate
noise sources; and 3) avoid the use of large, single voltage
regulators.
After all of these precautions, decoupling is an added measure to reduce supply noise. See the Decoupling Capacitors section.

Selecting Rf
The feedback resistor (Rf) typically ranges up to 20 MD. Rt
determines the gain and bandwidth of the amplifier. Proper
bandwidth ensures oscillation at the correct frequency plus
roll-off to minimize gain at undesirable frequencies, such as
the first overtone. Rf must be large enough so as not to affect
the phase of the feedback network in an appreciable manner.
RECOMMENDED READING
D. Babin, "Designing Crystal Oscillators", Machine Design,
March 7,1985.
D. Babin, "Guidelines for Crystal Oscillator Design", Machine
--Design, April 25, 1985.

PRINTED CIRCUIT BOARD LAYOUT
Noise generators on the power supply lines should be
decoupled. The two major sources of noise on the power

MOTOROLA

2-27

High-Speed CMOS Logic Data
DL129-Rev6

Definitions and Glossary of Terms
HCvs. HCT

Input Conditions - (HC) tr = tf = 6 ns, voltage
swing from GND to V CC with 50% duty cycle. (HCT) tr =
tf = 6 ns, voltage swing from GND to 3.0 V with 50% duty
cycle.
Output Conditions - (HC and HCT) waveform must
swing from 10% of (VOH - VoLl to 90% of
(VOH- VOL) and be functionally correct under the given
load condition: CL = 50 pF, all outputs.

Motorola's High-Speed CMOS is intended to give the designer an alternative to LSTTL. HSCMOS, with the faster
speed advantage over metal-gate CMOS (MC14000 series)
and the lower power consumption advantage over LSTTL, is
an optimum choice for new midrange designs. With the advent of high-speed CMOS microprocessors and memories,
the ability to design a 100% CMOS system is now possible.
HCT devices offer a short-term solution to the TTLI
NMOS-to-CMOS interface problem. To achieve this interface capability, some CMOS advantages had to be
compromised. These compromises include power consumption, operating voltage range, and noise immunity.
In most cases HCT devices are drop-in replacements of
TTL devices with significant advantages over the TTL devices. However, in some cases, an equivalent HCT device
may not replace a TTL device without some form of circuit
modification.
The wise designer uses HCT devices to perform logic level
conversions only. In new designs, the designer wants all the
advantages of a true CMOS system and designs using only
HC devices.

VCC Positive Supply Voltage - + dc supply voltage
(referenced to GND). The voltage range over which ICs
are functional.
Vin Input Voltage- DC input voltage (referenced to GND).
Vout Output Voltage - DC output voltage (referenced to
GND).

"A" Versus "Non-A" - Motorola has an on-going device performance enhancement program for the Hi-Speed
CMOS family. This is indicated by the "A" suffix of the device
identification. Some of the characteristics of this "An
enhancement program are improved design, a better quality
process, faster performing AC propagation delays and enhancements to various DC characteristics.
The old "Non-A" process was a 5 micron process that was
modified to run a 3.5 micron family. The new "An process is a
true 3 micron process and gives better process control, with
improved performance and quality.

CL

Load Capacitance - The capacitor value which loads
each output during testing and/or evaluation. This
capacitance is assumed to be attached to each output in
a system. This includes all wiring and stray capacitance.

Maximum Low Level Input Voltage - The worst case
voltage that is recognized by a device as the LOW state.

Hysteresis Voltage - The difference between VT+ and
VT- of a given device with hysteresis. A measure of
noise rejection.

ICC IC Quiescent Supply Current - The current into the
VccpinwhenthedeviceinputsarestaticatVccorGND
and outputs are not connected.
L1ICC Additional Quiescent Supply Current - The current
into the VCC pin when one olthe device inputs is at 2.4 V
with respect to GND and the other inputs are static at
VCC or GND. The outputs are not connected.
lin

Input Current - The current into an input pin with the
respective input forced to Vee or GND. A negative sign
indicates current is flowing out of the pin (source). A
positive sign or no sign indicates current is flowing into
the pin (sink).
lout Output Current - The current out of an output pin. A
negative sign indicates current is flowing out of the pin
(source). A positive sign or no sign indicates current is
flowing into the pin (sink).

Cout Output Capacitance - The capacitance associated
with a three-state output in the high-impedance state.
CPD Power DisSipation Capacitance - Used to determine
devicedynamicpowerdissipation, i.e., PD=CPD VCC 2f
+
VCCICC.
See
POWER
SUPPLY
SIZING for a discussion of CPD.

f max Maximum Clock Frequency - The maximum clocking frequency attainable with the following input and
output conditions being met:

MOTOROLA

VIL

VH

GLOSSARY OF TERMS
Input Capacitance - The parasitic capacitance
associated with a given input pin.

Minimum High Level Input Voltage - The worst case
voltage that is recognized by a device as the HIGH
state.

VOH Minimum High Level Output Voltage - The worst
case high-level voltage at an output for a given output
current (lout> and supply voltage (VCC).
VOL Maximum Low Level Output Voltage - The worst
case lOW-level voltage at an output for a given output
current (loutl and supply voltage (VCC).
VT + Positive-Going Input Threshold Voltage - The
minimum input voltage of a device with hysteresis which
is recognized as a high level. (Assumes ramp up from
previous low leveL)
VT _ Negative-Going Input Threshold Voltage - The
maximum input voltage of a device with hysteresis
which is recognized as a low level. (Assumes ramp
down from previous high level).

"A" versus "Non-A"

Cin

VIH

IIH

2-28

Input Current (High) - The input current when the
input voltage is forced to a high level.

High-Speed CMOS Logic Data
DL129-Rev6

Definitions and Glossary of Terms
IlL

Input Current (Low) - The input current when the
input voltage is forced to a low level.

tTLH Output Low-to-High Transition Time - The time
interval between the 10% and 90% voltage levels of the
rising edge of a switching output.

IOH Output Current (High) - The output current when the
output voltage is at a high level.
IOL

tTHL Output High-to-Low Transition Time - The time
interval between the 90% and 10% voltage levels of the
falling edge of a switching output.
tsu Setup Time - The time interval immediately preceeding the active transition of a clock or latch enable input,
during which the data to be recognized must be
maintained (valid) at the input to ensure proper recognition. A negative setup time indicates that the data at the
input may be applied sometime after the active clock or
latch transition and still be recognized. For HC devices,
the setup time is measured from the 50% level of the
data waveform to the 50% level of the clock or latch
input waveform. For HCT devices, the setup time is
measured from the 1.3 V level (with respect to GND) of
the data waveform to the 1.3 V level (with respect to
GND) of the clock or latch input waveform.

Output Current (Low) - The output current when the
output voltage is at a low level.

IOZ Three-State Leakage Current - The current into or
out of a three-state output in the high-impedance state
with that respective output forced to VCC or GND.
tpLH Low-to-High Propagation Delay (HC) - The time
interval between the 0.5 VCC level of the controlling
input waveform and the 50% level of the output
waveform, with the output changing from low level to
high level. (HCT) - The time interval between the 1.3 V
level (with respect to GND) of the controlling input
waveform and the 1.3 V level (with respect to GND) of
the output waveform, with the output changing from low
level to high level.

th

tPHL High-to-Low Propagation Delay (HC) - The time
interval between the 0.5 VCC level of the controlling
input waveform and the 50% level of the output
waveform, with the output changing from high level to
low level. (HCT) - The time interval between the 1.3 V
level (with respect to GND) of the controlling input
waveform and the 1.3 V level (with respect to GND) of
the output waveform, with the output changing from high
level to low level.
tpLZ Low-Level to High-Impedance Propagation Delay
(Disable Time) - The time interval between the 0.5
V CC level for HC devices (1.3 V with respectto GND for
HCT devices) of the controlling input waveform and the
10% level of the output waveform, with the output
changing from the low level to high-impedance (off)
state.

trec Recovery Time (HC) - The time interval between the
50% level of the transition from active to inactive state of
an asynchronous control input and the 50% level of the
active clock or latch enable edge required to guarantee
proper operation of a device. (HCT) - The time interval
between the 1.3 V level (with respect to GND) of the
transition from active to inactive state of an asynchronous control input and the 1.3 V level (with respect to
GND) of the active clock or latch edge required to
guarantee proper operation of a logic device.

tpHZ High-Level to High-impedance Propagation Delay
(Disable Time) - The time interval between the 0.5
VCC level for HC devices (1.3 Vwith respectto GNDfor
HCT devices) of the controlling input waveform and the
90% level of the output waveform, with the output
changing from the high level to high-impedance (off)
state.

tw

tpZL High-Impedance to Low-Level Propagation Delay
(Enable Time) - The time interval between 0.5 VCC
level (HC) or 1.3 V level with respect to
GND (HCT) of the controlling input waveform and the
50% level (HC) or 1.3 V level with respect to GND (HCT)
of the output waveform, with the output changing from
the high-impedance (off) state to a low level.

tr

tpZH High-Impedance to High-Level Propagation Delay
(Enable Time) - The time interval between the 0.5
VCC level (HC) or 1.3 V level with respect
to GND (HCT) of the controlling input waveform and the
50% level (HC) or 1.3 V level with respect to GND (HCT)
of the output waveform, with the output changing from
the high-impedance (off) state to a high level.

MOTOROLA

Hold Time - The time interval immediately following
the active transition of a clock or latch enable input,
during which the data to be recognized must be
maintained (valid) at the input to ensure proper recognition. A negative hold time indicates that the data at the
input may be changed prior to the active clock or latch
transition and still be recognized. For HC devices, the
hold time is measured from the 50% level of the clock or
latch input waveform to the 50% level of the data
waveform. For HCT devices, the hold time is measured
from the 1.3 V level (with respect to GND) of the clock or
latch input waveform to the 1.3 V level (with respect to
GND) of the data waveform.

tf

2-29

Pulse Width (HC) - The time interval between 50%
levels of an input pulse required to guarantee proper
operation of a logic device. (HCT) - The time interval
between 1.3 V levels (with respect to GND) of an input
pulse required to guarantee proper operation of a logic
device.
Input Rise Time (HC) - The time interval between the
10% and 90% voltage levels on the rising edge of an
input signal. (HCT) - The time interval between the 0.3
V level and 2.7 V level (with respect to GND) on the
rising edge of an input signal.
Input Fall Time (HC) - The time interval between the
90% and 10% voltage levels on the falling edge of an
input signal. (HCT) -- The time interval between the 2.7
V level and 0.3 V level (with respect to GND) on the
falling edge of an input signal.

High-Speed CMOS Logic Data
DL129-Rev6

121

APPLICATIONS ASSISTANCE FORM
In the event that you have any questions or concerns about the performance of any Motorola device listed in this catalog, please
contact your local Motorola sales office or the Motorola Help line for assistance. If further information is required, you can request
direct factory assistance.
Please fill out as much of the form as is possible if you are contacting Motorola for assistance or are sending devices back to
Motorola for analysis. Your information can greatly improve the accuracy of analysis and can dramatically improve the correlation response and resolution time.
Items 4 thru 8 of the following form contain important questions that can be invaluable in analyzing application or device problems. It can be used as a self-help diagnostic guideline or for a baseline of information gathering to begin a dialog with Motorola
representatives.

MOTOROLA Device Correlation/Component Analysis Request Form
Please fill out entire form and return with devices to MOTOROLA INC., R&QA DEPT., 2200 W. Broadway, Mesa, AZ 85202.
1) Name of Person Requesting Correlation: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-

Phone No:
Job Title: _ _ _ _ _ _ __
Company:
2) Alternate Contact: _ _ _ _ _ _ _ _ _ _ _ _ Phone/Position: _ _ _ _ _ _ _ _ _ _ _ _ _.:...._ _ __
3) Device Type (user part number): _ _ _ _ _ _ _ _ _ _ __
4) Industry Generic Device Type: _ _ _ _ _ _ _ _ _ _ _ __
5) # of devices tested/sampled:

# of devices in question':
# returned for correlation:
, In the event of 100% failure, does Customer have other date codes of Motorola devices that pass inspection?
Yes _ _ _

No _ _ _

Please specify passing date code(s) if applicable _ _ _ _ _ _ _ _ __

• If none, does customer have viable alternate vendor(s) for device type?
Yes _ _ _
No _ _' _
Alternate vendor's name _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
6) Date code(s) and Serial Number(s) of devices returned for correlation - If possible, please provide one or two "good" units
(Motorola's and/or other vendor) for comparison: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
7) Describe USER process that device(s) are questionable in:
Incoming component inspection {test system ?}: _ _ _ _ _ _ _ _ _ _ _ __
Design prototyping: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

=

Board test/burn-in: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Other (please describe): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

8) Please describe the device correlation operating parameters as completely as possible for device(s) in question:
> Describe all pin conditions (e.g., floating, high, low, under test, stimulated but not under test, whatever ... ), including any input
or output lOading conditions (resistors, caps, clamps, driving devices or devices being driven ... ). Potentially critical information includes:
Input waveform timing relationships
Input edge rates
Input Overshoot or Undershoot - Magnitude and Duration
Output Overshoot or Undershoot - Magnitude and Duration
> Photographs, plots or sketches or relevent inputs and outputs with voltages and time divisions clearly identified for all waveforms are greatly desirable.
> VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applications and test
systems. Dynamic characteristics of Ground and VCC during device switching can dramatically effect input and internal operating levels, Ground & VCC measurements should be made as physically close to the device in question as possible.
> Are there specific circumstances that seem to make the questionable unit(s) worse? Better?
Temperature _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VCC--------------------------------Input rise/fall time _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Output loading (current!capacitance) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Others _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

> ATE functional data should include pattern with decoding key and critical parameters such as VCC, input voltages, Func step
rate, voltage expected, time to measure.

MOTOROLA

2-30

High-Speed CMOS Logic Data

DL129-Rev6

High-Speed CMOS Data

This section contains the individual device
datasheets for Motorola's High-Speed CMOS
family.

Device Data Sheets

High-Speed CMOS Logic Data
DL129-Rev6

3-1

MOTOROLA

131

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad 2-lnput NAND Gate

MC54/74HCOOA

High-Performance Silicon-Gate CMOS
J SUFFIX
CERAMIC PACKAGE
CASES32-QS

The MC54n4HCOOA is identical in pinout to the LSOO. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTIL outputs.
• Output Drive Capability: 10 LSTIL Loads

N SUFFIX
PLASTIC PACKAGE
CASES4S-QS

• Outputs Directly Interface to CMOS, NMOS and TIL
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1JlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements

DSUFFIX
SOIC PACKAGE
CASE 751A-03

• Chip Complexity: 32 FETs or 8 Equivalent Gates

LOGIC DIAGRAM

A1
81
A2
82
A3

P
P
P
P

2
4

5
9

83

A4
84

DTSUFFIX
TSSOP PACKAGE
CASE 94SG-Q1

10
12
13

3 Y1
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT

6 Y2
Y=AB

Ceramic
Plastic
SOIC
TSSOP

8 Y3

FUNCTION TABLE
11

Y4

Inputs

PIN 14= Vee
PIN7=GND

Output

A

B

L
L

L

H

H

H

H

L

H

H

H

L

Y

Pinout: 14-Lead Packages (Top View)
Vee

84

A4

Y4

83

A3

Y3

A1

81

Y1

A2

82

Y2

GND

10/95

© Motorola, Inc. 1995

3-2

REV 7

®

MOTOROI.A

MC54/74HCOOA
MAXIMUM RATINGS'
Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

Symbol
VCC
Vin
Vout

Parameter
DC Supply Voltage (Referenced to GND)

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

- 65 to + 150

"C

lin

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND:5 (VinorVout):5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

"C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65" to 125"C
Ceramic DIP: -10 mW/"C from 100" to 125"C
SOIC Package: - 7 mW/"C from 65" to 125"C
TSSOP Package: - 6.1 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter

Min

Max

Unit

2.0

6.0

V

a

VCC

V

-55

+ 125

"C

a
a
a

1000
500
400

ns

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

High-Speed CMOS Logic Data
DL129 - Rev 6

VCC =2.0V
VCC =4.5 V
VCC = 6.0 V

3-3

MOTOROLA

MC54/74HCOOA

DC CHARACTERISTICS (Voltages Referenced to GND)

-55 to 25°C

:O:85°C

:O:125°C

Unit

Vout = 0.1V or VCC -o.1V
lIoutl :O: 2OllA

2.0
3.0
4.5
6.0

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

V

Maximum Low-Level Input Voltage

Vout = O.lVor VCC - 0.1V
lIoutl :O: 2OllA

2.0
3.0
4.5
6.0

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
Iioutl :0: 20llA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2048
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

DAD
DAD
DAD

Parameter

VIH

Minimum High-Level Input Voltage

VIL

VOH

Condition

Vin =VIH or VIL

VOL

Maximum Low-Level Output
Voltage

lin

lIoutl
lIout l
Iioutl

2.4mA
4.0mA
5.2mA

Vin = VIH or VIL
lIoutl:O: 20llA
Vin = VIH or VIL

ICC

Guaranteed Limit

VCC
V

Symbol

lIoutl
lIout l
lIoutl

2AmA
4.0mA
5.2mA

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±O.l

±1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = OIlA

6.0

1.0

10

40

IlA

NOTE: Information on tYPical parametric values can be found

In

Chapter 2.

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Guaranteed Limit

Vce
V

-55 to 25°e

:O:85°C

:o:125°C

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tTLH,
lTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

10

10

10

pF

Cin

Parameter

Maximum Input Capacitance

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical
Power Dissipation Capacitance (Per Buffer),

@

25°e, Vec = 5.0 V, VEE = 0 V
22

• Used to determine the no-load dynamic power consumption: Po = CPO Vcc 2j + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-4

High-Speed CMOS Logic Data
DL129- Rev 6

MC54/74HCOOA

--.Ic---- VCC
INPUT
AORB
GND

OUTPUTY

Figure 1. Switching Waveforms

TEST
POINT
OUTPUT
DEVICE
UNDER
TEST

'Includes all probe and jig capacitance

Figure 2. Test Circuit

A--'----'"
B--L-_

o-~CJ

>Cfo-- Y

Figure 3. Expanded Logic Diagram
(1/4 of the Device)

High-Speed CMOS Logic Data
DL129-Rev6

3-5

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad 2-lnput NAND Gate with
LSTTL-Compatible Inputs

MC54/74HCTOOA

High-Performance Silicon-Gate CMOS
.

JSUFFIX
CERAMIC PACKAGE
CASE 632-Qa

The MC54174HCTOOA may be used as a level converter for interfacing
TTL or NMOS outputs to high-speed CMOS inputs.
The HCTOOA is identical in pinout to the LSOO.
•
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
TTUNMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 I1A
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 48 FETs or 12 Equivalent Gates

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A-Q3

ORDERING INFORMATION

A1
B1

[3]

2

A2 4
B2 5
A3 9

B3
A4

B4

10
12
13

0
0
0
0

Ceramic
Plastic

MC54HCTXXAJ
MC74HCTXXAN
MC74HCTXXAD

LOGIC DIAGRAM

SOIC

3 Y1

PIN ASSIGNMENT

6 Y2
Y=AB

8 Y3

A1 [ 1-

14

DVee

B1 I 2

13

h B4

I
A2 I

3

12

A4

4

11

Y4

B2 [ 5

Y1

11 Y4

PIN 14= Vee
PIN7=GND

10

B3

Y2

6

9

A3

GND

7

8 ] Y3

FUNCTION TABLE
Inputs

10195
©,Motorola, Inc. 1995

REV 6

Output

A

B

V

L
L

L
H

H
H

L

H
H
H

H

L

®.MOTOROLA

MC54/74HCTOOA
MAXIMUM RATINGS·
Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

Symbol
VCC
Vin
Vout

Parameter
DC Supply Voltage (Relerenced to GND)

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65 to + 150

°c

TL

Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or Plastic Package
Ceramic Dip

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
vollage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :s (Vin or Vout) :S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mWI'C from 65° to 125°C
Ceramic DIP: -10 mWI'C from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0

500

ns

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall lime (Figure 1)

DC CHARACTERISTICS FOR THE MC54n4HCTOOA (Voltages Referenced to GND)
Guaranteed Limits

Symbol

-55to
25°C

VCC
V

Min

=

4.5
5.5

2.00
2.00

=

4.5
5.5

Parameter

Test Conditions

VIH

Minimum High-Level
Input Voltage

Vout 0.1 orVCC - 0.1 V
lIoutl :S 20 IlA

VIL

Maximum Low-Level
Input Voltage

Vout 0.1 orVcc - 0.1 V
lIoutl :S 20 IlA

VOH

Minimum High-Level
Output Voltage

Vin VIH or VIL
lIoutl s 20 IlA

=

,:s 85°C

Max

Min
2.00
2.00

O.BO
O.BO

4.5
5.5

4.40
5.40

4.5

3.9B

:S 125°C

Max

Min

Max

2.00
2.00

4.40
5.40

V
O.BO
0.80

0.80
0.80

Unit

V
V

4.40
5.40

=

Vin VIH or VIL
lIoutl s 4.0 rnA
VOL

Maximum Low-Level
Output Voltage

=

V

4.5
5.5

=
=
Vin =VCC or GND

4.5

0.26

0.33

0.40

5.5

±0.10

±1.00

±1.00

IlA

5.5

1

10

40

IlA

Vin VIH or VIL
lIoutl 4.0 rnA
lin

Maximum Input Leakage
Current

ICC

Maximum Quiescent Supply Current (per Package)

Vin VCC or GND
lIoutl :S 0 IlA

Additional Quiescent
Supply Current

Vin 2.4 V, Any One Input
Vin V CC or GND, Other Inputs
lout 0 IlA

AICC

3.70

3.B4

Vin VIH or VIL
lIoutl s 20 IlA

=

=
=
=

5.5

0.10
0.10

0.10
0.10

0.10
0.10

;;,,-55°C

25 to 125°C

2.9

2.4

rnA

NOTE: Information on typical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-7

MOTOROLA

MC54174HCTOOA
AC CHARACTERISTICS FOR THE MC54n4HCTOOA (VCC

=5.0 V +- 10%, CL =50 pF, Input tr =tf =6.0 ns)
Guaranteed Limits
-55to 25'e

Symbol

Parameter

Fig.

Min

Max

" 85'e
Min

" 125'e

Max

Min

Max

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A
or B to Output Y

1,2

19

24

28

ns

trLH,
trHL

Maximum Output Transition
lime, Any Output

1,2

15

19

22

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per Gate)'

=5.0 V

15

'Used to determine the no-load dynamic power consumption: Po = CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

INPUT
AORB

TEST POINT

J.:---- 3.0 V

OUTPUT
DEVICE
UNDER
TEST

OUTPUTY

, Includes all probe and jig capacitance

Figure 1. Switching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/4 OF THE DEVICE)

A - - r - -....
Y

B --"---_-'

MOTOROLA

3-8

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC02A

Quad 2-lnput NOR Gate
High-Performance Silicon-Gate CMOS
The MC54174HC02A is identical in pinout to the LS02. The device inputs
are compatible with standard CMOS outputs; with pull up resistors, they are
compatible with LSTTL outputs.

J SUFFIX
CERAMIC PACKAGE
CASE 632-08

•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 64EHl6

•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 40 FETs or 10 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-Q3

DTSUFFIX
TSSOP PACKAGE
CASE 948G-Ql

LOGIC DIAGRAM
Al

2

Bl
A2

5

B2
A3
B3
A4

B4

11
12

D
D
D
D

1 Yl

ORDERING INFORMATION

4 Y2

MC54HCXXAJ
MC74HCXXAN
MC?4HCXXAD
MC?4HCXXADT

Ceramic
Plastic
SOIC
TSSOP

Y=A+B
10 Y3
PIN ASSIGNMENT
13 Y4
PIN 14 = Vee
PIN 7 =GNO

Yl

1·

140 Vee

Al

2

13

Bl

3

12

bY4
b B4
b A4

Y2

4

11

A2

5

B2

6

tOp Y3
9 PB3

GND

7

80 A3

FUNCTION TABLE
Inputs

10195

© Motorola, Inc. 1995

3-9

REV7

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

®

MOTOROLA

MC54174HC02A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA
mA

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mAo

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

-65to+150

'c

TL

Lead Temperature, I mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :s (Vin or Vout) :S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125'C
TSSOP Package: - 6.1 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure I)

0

VCC

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

VCC=2.0V
VCC=4.5V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25'C

:S

85'C

:S

125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
lIoutl :S 20 ~

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVcc-O.1 V
lIoutl :S 20 IlA

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
Iioutl :S 20 ~

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl :S 2.4 mA
lIoull :S 4.0 mA
Iioutl :S 5.2 mA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.7
5.2

VOH

MOTOROLA

3-10

High-Speed CMOS Logic Data
DL129- Rev 6

MC54/74HC02A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

Vee
V

-55to
25°C

,; 85'e

,; 125°C

Unit

Vin = VIH or VIL
Iioutl ,; 20 IlA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Vin = VIH or VIL lIoutl ,; 2.4 mA
Iioutl ,; 4.0 mA
lIoutl ,; 5.2 mA

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.4
0.4
0.4

Parameter

Test Conditions

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

± 1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
Iioutl = 0 J.IA

6.0

1.0

10

40

IlA

Vee
V

-55to
25°C

,; 85'e

,; 125'e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

lin
ICC

NOTE: Information on typical parametnc values can be found

In

Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Cin

Parameter

NOTE: For propagation delays with loads other than 50 pF, and information on tYPical parametric values, see Chapter 2.
Typical
Power Dissipation Capacitance (Per Gate)'

@

25°C, Vee

=5.0 V

22

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TEST POINT
INPUT
AORB

OUTPUT
DEVICE
UNDER
TEST

OUTPUTY
• Includes all probe and jig capacitance

Figure 1. Switching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/4 OF THE DEVICE)
A

Y
B

High-Speed CMOS Logic Data
DL129- Rev 6

3-11

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC03A

Quad 2-lnput NAND Gate
With Open-Drain Outputs
High-Performance Silicon-Gate CMOS

N SUFFIX
PLASTIC PACKAGE
CASE 646--06

The MC74HC03A is identical in pinout to the LS03. The device inputs
are compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a high-performance MOS
N-Channel transistor. This NAND gate can, therefore, with a suitable
pullup resistor, be used in wired-AND applications. Having the output
characteristic curves given in this data sheet, this device can be used as
an LED driver or in any other application that only requires a sinking
current.
•
•
•
•
•
•
•

DSUFFIX
SOIC PACKAGE
CASE 751A-03

14#-

DTSUFFIX
TSSOP PACKAGE
CASE 948G-Ol

Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor
Outputs Directly Interface to CMOS, NMOS and TTL
High Noise Immunity Characteristic of CMOS Devices
Operating Voltage Range: 2 to 6V
Low Input Current: 11lA
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 28 FETs or 7 Equivalent Gates

ORDERING INFORMATION
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT

Plastic
SOIC
TSSOP

DESIGN GUIDE
Criteria
Internal Gate Count'

Value

Unit

7.0

ea

FUNCTION TABLE
Inputs

Output

Internal Gate Propagation Delay

1.5

ns

A

B

V

Internal Gate Power Dissipation

5.0

jlW
pJ

L
H
L
H

Z

0.0075

L
L
H
H

Speed Power Product
, Equivalent to a two-input NAND gate

Z
Z

L

Z = High Impedance

LOGIC DIAGRAM

OUTPUT~VCC

PROTECTION
DIODE

A 1,4,9,12
8 2,5,10,13

Pinout: 14-Lead Packages (Top View)
VCC

84

A4

Y4

83

A3

Y3

AI

81

Yt

A2

82

Y2

GND

3,6,8.11 Y'

~1
PIN 14= VCC
PIN7=GND
• Denotes open-drain outputs

10195

© Motorola, Inc. 1995

3-12

REV7

®

MOTOROLA

MC74HC03A
MAXIMUM RATINGS'
Parameter

Symbol
VCC

DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7.0

V

Yin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lin
lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500
450

mW

Tstg

Storage Temperature

-65to+ 150

"C

TL

Plastic DIPt
SOIC Packaget
TSSOP Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

"C
260

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65" to 125"C
SOIC Package: -7 mW/"C from 65" to 125"C
TSSOP Package: - 6.1 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

"C

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC =2.0V
VCC=4.5V
VCC=6.0 V

DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

VCC
V

-55 to 25"C

';85"C

,;125"C

Unit

Vout = O.lV orVcc -O.lV
Iioutl'; 20(.lA

2.0
3.0
4.5
6.0

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

V

Maximum Low-Level Input Voltage

Vout = O.lV or Vec - O.lV
Iioutl ,; 20(.lA

2.0
3.0
4.5
6.0

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.BO

V

Maximum Low-Level Output
Voltage

Vout = O.lV or Vce - O.lV
Iioutl ,; 20(.lA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0040
0040
0040

Symbol

Parameter

VIH

Minimum High-Level Input Voltage

VIL

VOL

Condition

Vin = VIH or VIL

lIoutl ,; 2AmA
lIoutl ,; 4.0mA
Iioutl ,; 5.2mA

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

(.lA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 01lA

6.0

1.0

10

40

(.lA

IOZ

Maximum Three-State Leakage
Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = Vee or GND

6.0

±0.5

±5.0

±10

(.lA

lin

NOTE: Information on typical parametnc values can be found m Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-13

MOTOROLA

MC74HC03A
AC CHARACTERISTICS (Cl =50pF, Input tr =tf =6ns)
Vee
V

Guaranteed Limit
-55 to 25°e

";05°e

,,;125°e

Unit

tpLZ,
tpZl

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
3.0
4.5
6.0

120
45
24
20

150
60
30
26

180
75
36
31

ns

trlH,

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

Maximum Input Capacitance

10

10

10

pF

Maximum Three-State Output Capacitance
(Output in High-Impedance State)

10

10

10

pF

Symbol

trHl

Cin
Cout

Parameter

NOTE: For propagation delays with loads other than 50 pF, and mformatlon on tYPical parametric values, see Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Buffer)'

= 5.0 V, VEE = 0 V

8.0

'Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-14

High-Speed CMOS logic Data
Dl129-Rev6

MC74HC03A
VCC

1kn

VCC

Rpd

OUTPUT

TEST
POINT

DEVICE
UNDER
TEST

GND
HIGH
IMPEDANCE
VOL

"Includes all probe and jig capacitance

Figure 1. Switching Waveforms

Figure 2. Test Circuit

VCC=5V

1

3
4
VO, OUTPUT VOLTAGE (VOLTS)

5

"The expected minimum curves are not guarantees, but are design aids.

Figure 3. Open-Drain Output Characteristics

VCC

VCC

VCC

A1 _-r--......

o--'-'---1-"--1f-- OUTPUT
B1 -""'-_""
A2 - - r - -......

LED1 --r-.......- - '

B2 --...;.;.;.;;.:./

LED2 - i - - - - - - - _ t _ '

I
I

An

---r1i4\.....

Yn

I

DESIGN EXAMPLE
CONDITIONS: ID '" 1OmA
USING FIGURE NO TAG TYPICAL
CURVE, at ID=10mA, VDS '" O.4V

LED
ENABLE - . - - - - - - - - '
:.B =

Bn~

VCC - VF - Vo
ID
5V - 1.7V - O.4V
10mA

OUTPUT: Y1 • Y2 •...• Yn
= A1B1 • A2B2 •...• AnBn

= 290Q

USE R = 270Q

Figure 4. Wired AND

High-Speed CMOS Logic Data
DL129- Rev 6

Figure 5. LED Driver With Blanking

3-15

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC04A

Hex Inverter
High-Performance Silicon-Gate CMOS
The MC54174HC04A is identical in pinout to the LS04 and the
MC14069. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The device consists of six three-stage inverters.

J SUFFIX
CERAMIC PACKAGE
CASE 632-08

• Output Drive Capability: 10 LSTTL Loads

NSUFFIX
PLASTIC PACKAGE
CASE 646-06

• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
• Low Input Current: 11!A
• High Noise Immunity Characteristic of CMOS Devices

DSUFFIX
SOIC PACKAGE
CASE 751A-03

• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 36 FETs or 9 Equivalent Gates

DTSUFFIX
TSSOP PACKAGE
CASE 948G-01

LOGIC DIAGRAM

A1~Y1

ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT

A2~Y2

A3~Y3

Ceramic
Plastic
SOIC
TSSOP

Y=A

A4~Y4

FUNCTION TABLE

A5~Y5
A6~Y6

Inputs

Outputs

A

Y

L
H

H

L

Pinout: 14-Lead Packages (Top View)
Vee

A6

Y6

A5

Y5

A4

Y4

M

~

A2

W

~

ft

GND

10195

© Motorola, Inc. 1995

3-16

REV7

®.

MOTOROLA

MC54n4HC04A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Relerenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

-65to+150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP Package: -6.1 mW/oC Irom 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

t r, tf

Input Rise and Fall Time
(Figure 1)

High-Speed CMOS Logic Data
DL129-Rev6

VCC=2.0V
VCC=4.5V
VCC=6.0V

3-17

MOTOROLA

MC54174HC04A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

Parameter

S85°C

S;125°C

Unit

VIH

Minimum High-Level Input Voltage

"out = 0.1V or'Vcc-O·1V
lIoutl S; 201lA

2.0
3.0
4.5
6.0

1.50 .
2.10
3.15
4.20

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

V

VIL

Maximum Low~evellnput Voltage

Vout = 0.1V or VCC - 0.1V
lIoutl S; 201lA

2.0
3.0
4.5
6.0.

0.50.
0.90
1.35
1.80

0.50
0.90
1.35
1.80.

0.50
0.90
1.35
1.80

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl S; 201lA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0. 1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

VOH

Condition

Yin =VIH or VIL

VOL

Maximum Low-Level Output
Voltage

lin
ICC

lIoutl S; 2.4mA
lIoutl S; 4.0mA
lIoutl S; 5.2mA

Yin = VIH or VIL
lIoutl S; 201lA
Yin = VIH or VIL

131

VCC
V

Symbol

lIoutl S; 2.4mA
lIoutl S; 4.0mA
lIoutl S; 5.2mA

-55 to 25°C

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 01lA

6.0

1.0

10

40

V

IlA
IlA

NOTE: Information on typical parametric values can be found in Chapter 2.

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Symbol

Parameter

Guaranteed Limit

VCC
V

-55 to 25°C

s;85°C

s;125°C

Unit

tPLH,
tpHL

Maximum Propagation Delay, Input A or B to Output V
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

lTLH,
t"J:HL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

10

10

10

pF

Cin

Maximum Input Capacitance

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°C, VCC
Power Dissipation Capacitance (Per Inverter)'

=5.0 V

20

• Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-18

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC04A

- - - " : - - - - VCC
INPUT A
GND

OUTPUTY

Figure 1. Switching Waveforms

TEST
POINT
OUTPUT
DEVICE
UNDER
TEST

"Includes all probe and jig capacitance

Figure 2. Test Circuit

Xf---Y

A

Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)

High-Speed CMOS Logic Data
DL129-Rev6

3-19

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HCT04A

Hex Inverter
With LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 646-06

The MC74HCT04A may be used as a level converter for interfacing
TTL or NMOS outputs to High-Speed CMOS inputs.
The HCT04A is identical in pinout to the LS04.

DSUFFIX
SOIC PACKAGE
CASE 751A-03

• Output Drive Capability: 10 LSTTL Loads
• TTUNMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5V

DTSUFFIX
TSSOP PACKAGE
CASE 948G-01

• Low Input Current: 1!IA
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 48 FETs or 12 Equivalent Gates

ORDERING INFORMATION
MC74HCTXXAN
MC74HCTXXAD
MC74HCTXXADT

LOGIC DIAGRAM

Plastic
SOIC
TSSOP

A1~Y1
FUNCTION TABLE

A2.~Y2

A3~Y3

Y=A

A4~Y4

Inputs

Outputs

A

y

L
H

H

L

Pin 14= Vee
Pin 7=GND

A5~YS
A6~Y6
Pinout: 14-Lead Packages (Top View)

Vee

AS

Y6

AS

YS

A4

Y4

A1

Y1

A2

Y2

A3

Y3

GND

10/95

© Motorola, Inc. 1995

3-20

REV6

®

MOTOROLA

MC74HCT04A
MAXIMUM RATINGS'
Symbol
VCC
Vin

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500
450

mW

Tstg

Storage Temperature Range

- 65 to + 150

'c
'c

Vout

TL

Plastic DIPt
SOIC Packaget
TSSOP Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/'C from 65' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
TSSOP Package: -6.1 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

'c

0

500

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature Range, All Package Types

tr,tf

Input Rise/Fall Time (Figure 1)

High-Speed CMOS Logic Data
DL129- Rev 6

3-21

MOTOROLA

MC74HCT04A

DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

VCC
V

-55 to 25°C

:585°C

:5125°C

Unit

Vout = 0.1V
lIoutl :5 201lA

4.5
5.5

2.0
2.0

2.0
2.0

2.0
2.0

V

Maximum Low-Level Input Voltage

Vout=VCC-O.1V
lIoutl :5 201lA

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

VOH

Minimum High-Level Output
Voltage

Vin=VIL
lIoutl S2Ol1A

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

4.5

3.98

3.84

3.70

VOL

Maximum Low-Level Output
Voltage

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Symbol

Parameter

Condition

VIH

Minimum High-Level Input Voltage

VIL

lIoutl :5 4.0mA

Vin=VIL
Vin=VIH
Iioutl S 2Ol1A

4.5

0.26

0.33

0.40

Yin = VCC or GND

5.5

±O.1

±1.0

±1.0

I1A

Yin = VCC or GND
lout = OI1A

5.5

1

10

40

IlA

lIoutl :5 4.0mA

Vin=VIH
Maximum Input Leakage Current

ICC

Maximum Quiescent Supply
Current (per Package)

AICC

Additional Quiescent Supply
Current

Yin = 2.4V, Any One Input
Yin = VCC or GND, Other Inputs
lout = OI1A

lin

V

5.5

~-55°C

25 to 125°C

2.9

2.4

mA

1. Information on tYPical parametric values can be found In Chapter 2.
2. Total Supply Current = ICC + LAICC.

AC CHARACTERISTICS (VCC = 5.0V ±1 0%, CL = 50pF, Input tr = tf = 6ns)
Guaranteed Limit
Symbol

:585°C

:5125°C

Unit

tPLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)

15
17

19
21

22
26

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

15

19

22

ns

Maximum Input Capacitance

10

10

10

pF

Cin

Parameter

-55 to 25°C

NOTE: For propagation delays with loads other than 50 pF, and InformaMn on tYPical parametric values, see Chapter 2.
Typical @ 25°C, VCC
Power Dissipation Capacitance (Per Inverter»
>

=5.0 V

22

Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-22

High-Speed CMOS Logic Data
DL129-Rev6

MC74HCT04A

i r - - - - - 3.0V
INPUT A
GND

OUTPUTY

Figure 1. Switching Waveforms

TEST
POINT
OUTPUT
DEVICE
UNDER
TEST

'Includes all probe and jig capacitance

Figure 2. Test Circuit

A

Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)

High-Speed CMOS Logic Data
DL129-Rev6

3-23

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HCU04

Hex Unbuffered Inverter
High-Performance Silicon-Gate CMOS

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

The MC74HCU04 is identical in pinout to the LS04 and the MC14069UB.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six single-stage inverters. These inverters are well
suited for use as oscillators, pulse shapers, and in many other applications
requiring a high-input impedance amplifier: For digital applications, the
HC04 is recommended.
•
•
•
•
•
•
•

D SUFFIX
SOIC PACKAGE
CASE 751 A------Y
Figure 3. Expanded Logic Diagram
(114 of the Device)

MOTOROLA

3-36

High.,-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad 2-lnput AND Gate with
LSTTL-Compatible Inputs

MC54/74HCT08A

High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 632-08

The MC54174HCT08A may be used as a level converter for interfacing
TTL or NMOS outputs to high-speed CMOS inputs.
The HCT08A is identical in pinout to the LS08.
• Output Drive Capability: 10 LSTTL Loads
• TTUNMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 ~A
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 40 FETs or 10 Equivalent Gates

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A-03

ORDERING INFORMATION

LOGIC DIAGRAM

Al~13 Yl
81

Ceramic
Plaslic
SOIC

MC54HCTXXAJ
MC74HCTXXAN
MC74HCTXXAD

2

PIN ASSIGNMENT

A2~Y2
82~
9

Y=A8

A3~
10
Y3

Al [ 1-

14

81 [ 2

13

Yl [ 3

83

A4~12
11 Y4
84 13

PIN 14= Vee
PIN 7=GND

PVee

P84
12 PA4

A2 [ 4

11

82 [ 5

10

Y2 [ 6

9

GND [ 7

8

PY4
P83

PA3
PY3

FUNCTION TABLE
Inputs

B

Y

L
L

L
H
L
H

L
L
L
H

H
H

10195

© Motorola, Inc. 1995

3-37

REV 6

Output

A

®

MOTOROLA

MC54/74HCT08A
MAXIMUM RATINGS'
Paramele~

Symbol
VCC

DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+.7.0

V

Yin

DC Input Voltage (Referenced to GND)

-1.5 toVCC + 1,5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Oljtput Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65to+150

°c

TL

Lead Temperature, 1 mm from case for 10 Seconds
(SOIC or Plastic DIP)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage.
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND " (Vin or Vout) " VCC:
Unused inputs must always be
. tied to an appropriate logic voltage
level (e.g., either GND or Vce).
. Unused outputs must be left open.

°c
°c

260
300

• MaXimum Ratings are those values beyond which damage to the deVice may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mWrC from 65° to 125°C
Ceramic DIP: -10 mW/oCfrom 100° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter
DC Supply Voltage (Referenced to GND)

VCC

Min

Max

4.5

5.5

V

0

VCC

V

-55

+ 125

°c

0

500

ns

DC Input Voltage, Output Voltage (Referenced to GND)

Yin, Vout
TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

Unit

DC CHARACTERISTICS FOR THE MC54174HCT08A (Voltages Referenced to GND)
Guaranteed Limit

Symbol

Parameter

-55to
25°C

Test Conditions

VCC
Volts

Min
2.00
2.00

,;; 85°C
Min

Max

" 125°C

Max

Min

Vout = 0.1 VorVCC -0.1 V
"outl " 20 l1A

4.5
5.5

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
"outl ,;; 2Ol1A

4.5
5.5

VOH

Minimum High-Level
Output Voltage

Yin = VIH or VIL
"outl ,;; 2Ol1A

4.5
5.5

4040
5040

Yin = VIH or VIL
"outl " 4.0 mA

4.5

3.98

Yin = VIH or VIL
"outl " 20 f1A

4.5
5.5

Vin = VIH or VIL
"outl " 4.0 mA

4.5

0.26

0.33

0040

Maximum Input Leakage
Current

Vin = VCC or GND

5.5

±0.10

±1.00

±1:00

f1A

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
"outl = 0 l1A

5.5

1

10

40

l1A

Additional Quiescent
Supply Current

Vin = 204 V, Any One Input
Vin = VCC or GND,
Other Inputs
lout = 0 mA

lin
ICC
dlCC

Maximum Low-Level
Output Voltage

5.5

0.80
0.80

2.00
2.00

Unit

Minimum High-Level Input
Voltage

VOL

2.00
2.00

Max

VIH

0.80
0.80

0.80
0.80

3.84

V
V

4040
5040

4.40
5.40

3.70
0.10
0.10

0.10
0.10

V

0.10
0.10

2e-55°C

25° 10 125°C

2.9

2.4

V

mA

NOTE: Information on tYPical parametric values can be found In Chapter 2.

MOTOROLA

3-38

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HCT08A
AC CHARACTERISTICS FOR THE MC54174HCT08A (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
-55to
25°e

" 85°e

" 125°e

Symbol

Parameter

Fig.

Max

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y

1,2

19

24

28

ns

trLH,
trHL

Maximum Output Transition Time, Any Output

1,2

15

19

22

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Min

Max

Min

Max

Min

NOTE: For propagation delays with loads other than 50 pF, and information on tYPical parametric values, see Chapter 2.
Typical
Power Dissipation Capacitance (Per Gate)"

@

25°e, Vee

=5.0 V

20

"Used to determine the no-load dynamic power consumption: PD = CpD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

-

INPUT
AORB

3.0V

TEST POINT
IC_ _ _ _ GND

OUTPUT
DEVICE
UNDER
TEST

OUTPUTY

10%
" Includes all probe and jig capacitance

Figure 1. Switching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/4 OF THE DEVICE)

A

>---Y

B--~_./

High-Speed CMOS Logic Data
DL129-Rev6

3-39

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triple 3-lnput NAND Gate

'---_M_C_7_4_H_C_1_0_---I1

High-Performance Silicon-Gate CMOS
N SUFFIX
PLASTIC PACKAGE
CASE 646-06

The MC74HC10 is identical in pinout to the LS10. The device inputs are
compatible with standard CMOS outputs; with pullup resistors,· they are
compatible with LSTTL outputs.
•
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 ~
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 36 FETs or 9 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-03

ORDERING INFORMATION
MC74HCXXN
MC74HCXXD

Plastic
SOIC

LOGIC DIAGRAM
PIN ASSIGNMENT

A1~1
81 2
12 Y1
C1

13

A2 3

82~Y2
C2~

3B:CY-

A3 9
83
C3

.

0

11

8

A1

1-

14 ] VCC

81

2

13 ] C1

A2

3

12 ] Y1

82

4

11

J C3

C2

5

10

0 83

Y2

6

9

GND

7

8

0A3
P Y3

Y3

FUNCTION TABLE
PIN 14= VCC
PIN7=GND

Inputs

10195

© Molorola, Inc. 1995

3-40

REV 6

A

B

C

Output
y

L
X
X
H

X
L
X
H

X
X
L
H

H
H
H
L

®

MOTOROLA

MC74HC10
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

mA
mA

lin

DC Input Current, per Pin

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

-65to+150

'c

Tstg

TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'c
260

• MaXimum Ratings are those values beyond which damage to the deVice may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

:5 85'C

:5 125'C

Unit

Minimum High-Level Input
Voltage

Vout = 0.1 V or VCC - 0.1 V
"outl :5 20 !LA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
"outl :5 20 j.lA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
"outl :5 20 !LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL "outl :5 4.0 mA
"outl :5 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin =VIH
IIoutl :5 20 !LA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOL

Maximum Low-Level Output
Voltage

Test Conditions

VCC
V

VIH

VOH

Parameter

-55to
25'C

Yin = VIH or VIL
lin
Ice

"outl :5 4.0 mA
"outl :5 5.2 mA

V

Maximum Input Leakage Current

Yin = Vce or GND

6.0

±0.1

± 1.0

± 1.0

!LA

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = o !LA

6.0

2

20

40

!LA

NOTE: Information on typical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev 6

3-41

MOTOROLA

MC74HC10
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

:s 85°e

:s

125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

95
19
16

120
24
20

145
29
25

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

NOTES:
1. For propagation delays wnh loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Gate»
>

=5.0 V

25

Used to determine the no-load dynamic power consumption: Po = CpO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TEST POINT
J.----:....--VCC
OUTPUT
DEVICE
UNDER
TEST

OUTPUTY

>

Includes all probe and jig capacitance

Figure 1. Switching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/3 OF THE DEVICE)

A
y

B

C

MOTOROLA

3-42

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC11

Triple 3-lnput AND Gate
High-Performance Silicon-Gate CMOS
The MC?4HC11 is identical in pinout to the LS11. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 646-Q6

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 /-LA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. ?A
Chip Complexity: 60 FETs or 15 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-03

ORDERING INFORMATION
MC74HCXXN
MC74HCXXD

Plastic
SOIC

LOGIC DIAGRAM
PIN ASSIGNMENT
A1 ..,1,...-_-r-_____

B1~

C1

~Y1

-'~~3_-1._......; - - - -

A2 :::L::J4
B2~

p6

Y2

C2 -=----l_.......

PVCC
PC1
12 PY1

A1

1-

14

B1

2

13

A2

3

B2

4

11

C3

C2

5

10

B3

Y2

6

9

A3

GND

7

8

PY3

A3 JL:::J10
p8
B3 ·11 - I
Y3
C3....:..:..--l-......·
PIN 14=VCC
PIN 7= GND

FUNCTION TABLE
Inputs

10195

© Motorola,

Inc. 1995

3-43

REV 7

Output

A

B

C

Y

L
X

X
L

X
X

X
H

X
H

L

L
L
L

H

H

®

MOTOROLA

MC74HC11
MAXIMUM RATINGS·
Symbol
VCC
Vin
Vout
lin

Parameter

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

mA
mA

DC Supply Voltage (Referenced to GND)

DC Input Current, per Pin

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

-65to+150

°c

Plastic DIPt
SOIC Packaget

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ,;; (Vin orVout) ,;; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• Maximum Rallngs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°C

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC = 2.0 V
VCC =4.5V
VCC = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

,;; 85°C

,;; 125°C

Unit

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
"outl ,;; 20 I!A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
IIoutl ,;; 20 I!A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
"outl ,;; 20 I!A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL "outl ,;; 4.0 mA
"outl ,;; 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
"outl ,;; 20 I!A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL "outl ,;; 4.0 mA
"outl ,;; 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

I!A

Vin = VCC or GND
lout = 0 I!A

6.0

2

20

40

I!A

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

Test Conditions

-55to
25°C

VIH

VOH

Parameter

VCC
V

V

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-44

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC11
AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Input tr =tf = 6.0 ns)
Guaranteed Limit
Symbol

Vee
V

-55to
25'e

,; 85'e

,; 125'e

Unit

tPlH,
tpHl

Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

trlH,
tTHl

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'C, Vee
Power Dissipation Capacitance (Per Gate),

=5.0 V

27

• Used to determine the no-load dynamic power consumption: Po = CpO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

1.......- - - GND

• Includes all probe and jig capacitance

Figure 1. SWitching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/3 OF THE DEVICE)

A

y

B

c

High-Speed CMOS logic Data
DL129-Rev6

3-45

.MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Hex Schmitt-Trigger Inverter

MC54/74HC14A

High-Performance Silicon-Gate CMOS
The MC54174HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC14A is useful to "square up" slow input rise and fall times. Due
to hysteresis voltage of the Schmitt trigger, the HC14A finds applications
in noisy environments.

J SUFFIX
CERAMIC PACKAGE
CASE 632-OB

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V

DSUFFIX
SOIC PACKAGE
CASE 751A-03

• Low Input Current: 1flA
• High NOise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 60 FETs or 15 Equivalent Gates

DTSUFFIX
TSSOP PACKAGE
CASE 94BG-Ol

LOGIC DIAGRAM
ORDERING INFORMATION

Al~Yl

MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT

A2~Y2

A3~Y3

FUNCTION TABLE

Y=A

A4~Y4

Ceramic
Plastic
SOIC
TSSOP

Pin 14= Vee
Pin 7 = GND

A5~Y5

Inputs

Outputs

A

y

L
H

H
L

A6~Y6
Pinout: 14-Lead Packages (Top View)

Vee

A6

Y6

A5

Y5

A4

Y4

AI

Yl

A2

Y2

A3

Y3

GND

10/95

© Motorola, Inc. 1995

3-46

REV7

®

MOTOROLA

MC54/74HC 14A
MAXIMUM RATINGS'
Parameter

Symbol

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature Range

-65to+150

·C

VCC
Vin
Vout

TL

DC Supply Voltage (Referenced to GND)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

·C

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP

260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/·C from 65· to 125·C
Ceramic DIP: -10 mW/·C from 100· to 125·C
SOIC Package: - 7 mWI"C from 65· to 125·C
TSSOP Package: -6.1 mW/·C from 65· to 125·C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to
GND)

TA

Operating Temperature Range, All Package Types

tr,tf

Input Rise/Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

·C

0
0
0

No Limit"
No Limit"
No Limit"

ns

"When Vin = 50% VCC, ICC> 1mA

High-Speed CMOS Logic Data
DL129- Rev 6

3-47

MOTOROLA

MC54/74HC14A

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Parameter

Condition

Guaranteed Limit

VCC
V

-55 to 25°C

S85°C

s125°C

Unit

VT+max

Maximum Positive-Going Input
Threshold Voltage
(Figure 3)

Vout=O.lV
Iioutl S 2O!LA

2.0
3.0
4.5
6.0

1.50
2.15
3.15
4.20

1.50
2.15
3.15
4.20

1.50
2.15
3.15
4.20

V

VT+min

Minimuin Positive-Going Input
Threshold Voltage
(Figure 3)

Vout = 0.1V
"outl S2O!LA

2.0
3.0
4.5
6.0

1.0
1.5
2.3
3.0

0.95
1.45
2.25
2.95

0.95
1.45
2.25
2.95

V

VT_max

Maximum Negative-Going Input
Threshold Voltage
(Figure 3)

Vout=VCC-0.1V
"outl S2O!LA

2.0
3.0
4.5
6.0

0.9
1.4
2.0
2.6

0.95
1.45
2.05
2.65

0.95
1.45
2.05
2.65

V

VT_min

Minimum Negative-Going Input
Threshold Voltage
(Figure 3)

Vout= VCC-O.1V
"outl S2O!LA

2.0
3.0
4.5
6.0

0.3
0.5
0.9
1.2

0.3
0.5
0.9
1.2

0.3
0.5
0.9
1.2

V

VHmax
Note 2

Maximum Hysteresis Voltage
(Figure 3)

Vout = 0.1V orVcc-0.1V
"outl S2O!LA

2.0
3.0
4.5
6.0

1.20
1.65
2.25
3.00

1.20
1.65
2.25
3.00

1.20
1.65
2.25
3.00

V

VHmin
Note 2

Minimum Hysteresis Voltage
(Figure 3)

Vout = 0.1V or VCC - O.lV
"outl S 20!LA

2.0
3.0
4.5
6.0

0.20
0.25
0.40
0.50

0.20
0.25
0.40
0.50

0.20
0.25
0.40
0.50

V

VOH

Minimum High-Level Output
Voltage

VinSVT_min
"outl S 20!LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Yin = VCC or GND

6.0

iO.l

il.0

il.0

!LA

Yin = VCC or GND
lout = O!LA

6.0

1.0

10

40

!LA

Yin sVT_min

VOL

Maximum Low-Level Output
Voltage

"outl S 2.4mA
"outl S 4.0mA
"outl S 5.2mA

Vin~VT+max

"outl S20!LA
Yin ~VT+ max

lin
ICC

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

"outl S 2.4mA
"outl S 4.0mA
"outl S 5.2mA

V

1. Information on tYPical parametric values along with frequency or heavy load considerations can be found In Chapter 2.
2. VHmin > (VT+ min) - (VT_ max); VHmax = (VT+ max) - (VT_ min).

MOTOROLA

3-48

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC14A

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Symbol

Guaranteed Limit

Vee
V

-55 to 25°e

!S85°e

!S125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tTLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

10

10

10

pF

Cin

Parameter

Maximum Input Capacitance

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Inverter)'
'Used to determine the no-load dynamic power consumption: PD

=5.0 V

22

=CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

INPUT A

OUTPUTY

Figure 1. Switching Waveforms

TEST
POINT
OUTPUT
DEVICE
UNDER
TEST

'Includes all probe and jig capacitance
Figure 2. Test Circuit

High-Speed CMOS Logic Data
DL129-Rev6

3-49

MOTOROLA

MC54/74HC14A

en
~
0

4

G

1

UJ

(!)

!:i0
>

VHtyP

0

j

B
:I:

en
UJ
a: 2

:I:
l-

I-

::>
0-

~

...J

«:

0

c::
~

,f3 4 5

2

Vee, POWER SUPPLY VOLTAGE (VOLTS)
VHtyP = (VT+ typ) - (VT- typ)

Figure 3. Typical Input Threshold, VT+, VT_ versus Power Supply Voltage

A--7
(a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times

(b) A Schmitt-Trigger Offers Maximum Noise Immunity

- - - - - - - - - - - - Vee

. i~~___
- --

i VH--~---~ VT+
Yin
,--/l---~t-1
1
1

1
1
1

1
1
1

y

Vln

VT-

, - - - 1--- 1 - - 1--- 1 -

Vee
VT+

~:-D

GND
1
1

VOH
Vout
VOL

1
1

1
1

1
1

v··l I I r:~

Figure 4. Typical Schmitt-Trigger Applications

MOTOROLA

3-50

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Hex Schmitt-Trigger Inverter
with LSTTL Compatible Inputs

I MC54/74HCT14A I

High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 632-08

The MC54/74HCT14A may be used as a level converter for interfacing
TTL or NMOS outputs to high-speed CMOS inputs.
The HCT14A is identical in pinout to the LS14.
The HCT14A is useful to "square up" slow input rise and fall times. Due to
the hysteresis voltage of the Schmitt trigger, the HCT14A finds applications
in noisy environments.

N SUFFIX
PLASTIC PACKAGE
CASE 646-G6

• Output Drive Capability: 10 LSTTL Loads
• TTUNMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0llA
• In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-G3

ORDERING INFORMATION
MC54HCTXXAJ
MC74HCTXXAN
MC74HCTXXAD

Ceramic
Plastic
SOIC

LOGIC DIAGRAM

A1~Y1

PIN ASSIGNMENT

A2~Y2
A3~Y3

A1

1-

Y1

2

A2

3

Y2

4

A3 [ 5
Y3 [ 6
GND t 7

A4~Y4
A5~Y5

PVee
PA6
12 PY6
11 PA5
10 PY5
9 PA4
8 PY4
14

13

FUNCTION TABLE
Input

A6~Y6

A

Output
y

L
H

H
L

PIN 14:Vee

PIN 7 :GND

10195

© Motorola, Inc. 1995

3-51

REV6

®

MOTOROLA

MC54/74HCT14A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
sOle Packaget

750
500

mW

Tstg

Storage Temperature

-65to+150

°c

lL

Lead Temperature, I mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :5 (Vin orVout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
°c

260
300

• Mru(lmum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mWrC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
Vec
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

°c

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme (Figure I)

.

-

ns

• No Limit when Yin = 50% Vce, ICC> 1 rnA.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Temperature Limit

VCC
Volts

.-55to
25°C

:5 85°C

:5 125°C

Symbol

Parameter

VT+max

Maximum Positive-Going
Input Threshold Voltage

Vout=O.1 VorVcc-O.1 V
1I0uti :5 2Ol!A

4.5
5.5

VT+min

Minimum Positive-Going
Input Threshold Voltage

Vout=O.1 VorVcc-O.1 V
1I0uti :5 20 I!A

4.5
5.5

VT_max

Maximum Positive-Going
Input Threshold Voltage

Vout=O.1 VorVcc-O.1 V
1I0uti :5 20 I!A

4.5
5.5

VT_min

Minimum Positive-Going
Input Threshold Voltage

Vout=O.1 VorVcc-O.1 V
1I0uti :5 2Ol!A

4.5
5.5

VHmax

Maximum Hysteresis
Voltage

Vout=O.1 VorVcc-O.l V
1I0uti :5 20).lA

4.5
5.5

VHmin

Minimum Hysteresis
Voltage

Vout=O.1 VorVcc-O.1 V
1I0uti :5 20 I!A

4.5
5.5

0.4
0.4

0.4
0.4

0.4
04

VOH

Minimum High-Level
Output Voltage

Vin Bout, A = Bout, or A < Bout output, leaving
the other two at a low voltage level. This device also has A > Bin, A Bin, and
A < Bin inputs, eliminating the need for external gates when cascading.

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

DTSUFFIX
TSSOP PACKAGE
CASE 948F-Ol

=

•
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. ?A
Chip Complexity: 248 FETs or 62 Equivalent Gates

ORDERING INFORMATION
MC74HCXXN
MC74HCXXDT

PIN ASSIGNMENT

83[ 1LOGIC DIAGRAM

[3]

10
AD
12
Al
13
A2
15
A3

DATA
INPUTS

BO
Bl
B2
B3

=ING{
INPUTS

16

Vee

A < Bin [ 2

t5

A3

A=Bin [ 3

14

B2

A> Bin [ 4

13

h A2

A> Bout [ 5

5

Plastic
TSSOP

PBl
DAO
9 DBO

11

A < Bout! 7

10

GND [ 8

A _"""N

12 ~ Al

A= Baud 6

6 > Born }
A = Bout OUTPUTS
7
A < Bout

11
14
t

A>Bin
A=Bin
A B
orA B
(Figures 1 and 2)

2.0
4.5
6.0

175
35
30

220
44
37

2.65
53
45

ns

tpLH.
tpHL

Maximum Propagation Delay. Inputs A> B or A = B to Output A < B
(Figures 1 and 2)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLH.
tpHL

Maximum Propagation Delay. Input A = B to Output A = B
(Figures 1 and 2)

2.0
4.5
6.0

145
29
25

180
36
31

220
44
38

ns

trLH.
trHL

Maximum Output Transition TIme. Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF. see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Package)-

=5.0 V

50

- Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations. see Chapter 2.

INPUTS

11=------GND

TEST POINT
OUTPUTS

OUTPUT
DEVICE

UNDER

TEST
OUTPUTS
- Includes all probe and jig capacitance
Figure 1. Switching Waveforms

MOTOROLA

Figure 2. Test Circuit

3-102

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC85
PIN DESCRIPTIONS
outputs should be tied to A < Bin, A = Bin, and A > Bin, respectively, of the succeeding stage.

INPUTS
AO, A1, A2, A3 (Pins 10, 12, 13, 15)

OUTPUTS

Data Nibble A Inputs. The data nibble present at these inputs is compared to Data Nibble B. A3 is the most significant
bit and AO is the least significant bit.

A > Bout (Pin 5)
A-Greater-Than-B Output. This output is at a high voltage level when Nibble A is greater than Nibble B, regardless
of the data present at the cascading inputs. This output is
also high when Nibble A equals Nibble B and the A > Bin input is high (A < Bin and A = Bin are at a low voltage level).

BO, B1, B2, B3 (Pins 9,11,14,1)
Data Nibble B Inputs. The data nibble present at these inputs is compared to Data Nibble A. B3 is the most significant
bit and BO is the least significant bit.

A = Bout (Pin 6)
A-Equals-B Output. This output is high when Nibble A
equals Nibble B and the A = Bin input is high. A < Bin and
A> Bin have no effect when the comparator is in this condition and A = Bin is at a high voltage level.

CONTROLS
A> Bin, A

= Bin, A < Bin (Pins 4, 3, 2)

Cascading Inputs. These inputs determine the states of
the outputs only when Data Nibble A equals Data Nibble B.
The A =Bin input overrides both the A > Bin and A < Bin
inputs.
For single stage operation or for the least significant stage
in cascaded operation, the A < Bin and A> Bin inputs should
be tied to ground and the A = Bin input tied to VCC. Between
cascaded comparators, theA < Bout,A = Bout,andA > Bout

A < Bout (Pin 7)
A-Less-Than-B Output. This output is at a high voltage
level when Nibble A is less than Nibble B, regardless of data
present at the cascading inputs. This output is also high
when Nibble A equals Nibble B and the A < Bin input is high
(A > Bin and A = Bin are at a low voltage level).

FUNCTION TABLE
Data Inputs

Cascading Inputs

Output

A3,B3

A2,B2

A1, B1

AO,BO

A>Bin

A=Bin

ABout

A=Bout

AB3
A3B2
A2< B2

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

H
L
H
L

L
L
L
L

L
H
L
H

A3=B3
A3=B3
A3=B3
A3=B3

A2=B2
A2=B2
A2=B2
A2=B2

A1 >B1
A1 BO
AOBin
A=Bin
A Bout

-

A< Bout

-

A>Bin
A=Bout ' - - - A=Bin
A Bout

B5

A = Bout
A Bin

-

A=Bin
A Bout

B9

A= Bout

B10
B11

High-Speed CMOS Logic Data
DL129-Rev6

3-105

} OUT","

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC86

Quad 2-lnput Exclusive
OR Gate
High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 632-OB

The MC54174HC86 is identical in pinout to the LS86; this device is similar
in function to the MM74C86 and L86, but has a different pinout. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 !-LA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 56 FETs or 14 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-03

ORDERING INFORMATION
MC54HCXXJ
MC74HCXXN
MC74HCXXD

LOGIC DIAGRAM

Ceramic
Plastic
SOIC

A1~3

B1~Y1

PIN ASSIGNMENT

A1 [ 1·

A3~

B3~-·Y3

A4~
B4~·---

14 ]vee

B1[ 2

13 ]84

yj( 3

12 ]A4

A2 [ 4

11 ] Y4

B2 [ 5

10

Y2 [ 6

9

GND[ 7

Y4

J B3
P A3

8 P3

PIN 14 = Vee
PIN 7 = GND
FUNCTION TABLE
Inputs

10195

© Motorola, Inc. 1995

3-106

REVS

Output

Y

A

B

L
L

L

L

H

H
H

L

H
H

H

L

®

MOTOROLA

MC54/74HC86
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

- 65 to + 150

'c

'in
lout

Tstg
TL

.

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications 01 any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND " (Vin or Vout) " VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'c
260
300

Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/'C from 100° to 125°C
SOlC Package: - 7 mW/'C from 65° to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tl

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

'c

a

1000
500
400

ns

0
0

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

" 85°C

" 125°C

Unit

Minimum High-Level Input
Voltage

Vou t=0.1 VorVCc-0.1 V
"outl " 20 ~

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

V,L

Maximum Low-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
1I0uti " 20 ~A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = V,H or V,L
"outl " 20 ~

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = V,H or V,L "outl " 4.0 mA
"outl " 5.2 mA

4.5
6.0

3.98
5.48

3.B4
5.34

3.70
5.20

Yin = V,H or V,L
"outl " 20 ~A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = V,H or V,L "outl " 4.0 mA
"outl " 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

~

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
'out = a ~A

6.0

2

20

40

~

VOL

'in
ICC

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25°C

V,H

VOH

Parameter

VCC
V

NOTE: Information on tYPical parametric values can be lound

High-Speed CMOS Logic Data
DL129-Rev6

In

V

Chapter 2.

3-107

MOTOROLA

MC54/74HC86
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t, = tf = 6 ns)
Guaranteed Limit
Vee
V

-55 to
25°e

s 85°e

s 125°e

Unit

tPLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

120
24
20

150
30
26

180
36
31

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays wilh loads other than 50 pF, see Chapler 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical

@

Power Dissipation Capacitance (Per Gate)'

25°e, Vee

=5.0 V

33

'Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

If

Vcc
INPUT
AORB

TEST POINT
" - - - - - GNO

OUTPUT
DEVICE
UNDER
TEST

OUTPUTY
10%
, Includes all probe and jig capacitance

Figure 1. Switching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/4 of Device)

A
Y

B

MOTOROLA

3--108

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC86A

Product Preview

Quad 2-lnput Exclusive
OR Gate

J SUFFIX
CERAMIC PACKAGE
CASE 632-QB

High-Performance Silicon-Gate CMOS
The MC54174HC86A is identical in pinout to the LS86; this device is
similar in function to the MM74C86 and L86, but has a different pinout. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 646-06

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IJA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 56 FETs or 14 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-Q3

DTSUFFIX
TSSOP PACKAGE
CASE 94BG-Q1
ORDERING INFORMATION

LOGIC DIAGRAM

A1~3

81~Y1

A2~

Ceramic

MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT

6

Plastic
SOIC
TSSOP

PIN ASSIGNMENT

82~Y2

A3~

83~-Y3

A4~

84~Y4
PIN 14= Vee
PIN 7 =GND

Ad 1·

14 ~ Vee

81[ 2

13

yd 3

12 ~A4

A2 [ 4

11 ] Y4

82 [ 5

10

H4
J 83

Y2 [ 6

9] A3

GND [ 7

8 ] Y3

FUNCTION TABLE
Inputs

Output

A

B

V

L
L
H
H

L
H
L
H

L
H
H
L

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10195

© Motorola, Inc. 1995

3-109

REVO

®

MOTOROLA

MC54/74HC86A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

Vout

DC Output Voltage (Referenced to GND)

lin

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
rnA

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

TL

-65to+150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :s; (Vin or Vout) :s; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
°c

260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min·

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

V

-55to
25°C

:s; 85°e

:s; 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
"outl :s; 20llA

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.l VorVCC-O.l V
"outl :s; 20llA

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl :s; 20llA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

Vec
Symbol

VOH

Parameter

Test Conditions

Yin = VIH or VIL

MOTOROLA

"outl :s; 2.4 rnA
lIoutl :s; 4.0 rnA
lIoutl :s; 5.2 mA

3-110

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC86A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

lin
ICC

VCC
V

-55 to
25'C

s 85'C

s 125'C

Unit

Vin ; VIH or VIL
lIoutl s 20llA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Vin ; VIH or VIL lIoutl s 2.4 rnA
lIoutl s 4.0 rnA
lIoutl s 5.2 rnA

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Parameter

Test Conditions

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

Vin ; VCC or GND

6.0

±0.1

± 1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin ; VCC or GND
lout; OIlA

6.0

1.0

10

40

Il A

VCC
V

-55to
2S'C

NOTE: Information on tYPical parametric values can be found In Chapter 2.
AC ELECTRICAL CHARACTERISTICS (CL ; 50 pF, Input t, ; tf ; 6 ns)
Guaranteed Limit

s 8S'C

s 125'C

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
3.0
4.5
6.0

100
80
20
17

125
90
25
21

150
110
31
26

ns

tTLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'C, Vec = 5.0 V
Power DiSSipation Capacitance (Per Gate)"

33

"Used to determine the no-load dynamic power consumption: PD = CpD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev 6

3-111

MOTOROLA

MC54174HC86A
tf
- - - VCC
INPUT
AORB

TEST POINT
- , . ; ; ; - - - - GND
OUTPUT
DEVICE
UNDER
TEST

OUTPUTY

10%
• Includes all probe and jig capacitance

Figure 1. Switching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/4 of Device)

A

Y

B

MOTOROLA

3-112

High-Speed CMOS Logic Data
DL129- Rev 6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC107

Dual J-K Flip-Flop with Reset
High-Performance Silicon-Gate CMOS
The MC74HC107 is identical in pinout to the LS107. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Each flip flops negative edge clocked and has an active-low asynchronous reset.
The HC107 is identical in function to the HC73, but has a different pinout.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A-03

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 92 FETs or 23 Equivalent Gates

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

Plastic
SOIC

PIN ASSIGNMENT
LOGIC DIAGRAM

J1
CLOCK 1
K1
RESET 1
J2

3
12
2

4

01

ill

14

13 ~ RESET 1

2

~

VCC

011 3

12

KlI 4

PK2
10 PRESET2

CLOCK 1

11

021 5

9 ~ CLOCK2

021 6

13

~

J1I 1-

ill 1

GND 1 7

8

PJ2

8
02

CLOCK 2
K2
RESET 2

02

11

FUNCTION TABLE

10

Inputs
Reset Clock

PIN 14= VCC
PIN 7=GND

L
H
H
H
H
H
H
H

10195

© Motorola, Inc. 1995

3-113

REV 6

X

'-'-'-'-L
H

.r

®

Outputs

J

K

X
L
L
H
H
X
X
X

X
L
H
L
H
X
X
X

Q

Q

L
H
No Change
L
H
L
H
Toggle
No Change
No Change
No Change

MOTOROLA

MC74HC107
MAXIMUM RATINGS'
Symbol
VCC
Yin
Vout

Parameter

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V
rnA

DC Supply Vollage (Referenced to GND)

lin

DC Input Current, per Pin

±20

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

-65to+150

°c

Plastic DIPt
SOIC Packaget

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

• Maximum Ratings are those values beyond which damage to the device may occur.
,Functional operation should be restricted to the Recommended Operatin'g Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

VCC
V

-55to
25°C

s 05°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
"outl s 20llA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
1I0uti s 20 IlA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20 I!A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL 1I0uti s 4.0 rnA
1I0uti s 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
1I0uti s 20 I!A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL "outl s 4.0 rnA
1I0uti s 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

± 1.0

I!A

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 I!A

6.0

4

40

80

IlA

VOH

VOL

lin
ICC

Parameter

Maximum Low-Level Output
Voltage

Test Conditions

V

NOTE: Information on typical parametric values can be found In Chapter 2.

MOTOROLA

3-114

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC107
AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Guaranteed limit
Vee
V

~55to

25"e

:s 85"e

:s 125"e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tpLH,
tpHL

Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)

2.0
4.5
6.0

155
31
26

195
39
33

235
47
40

ns

tTLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25"e, Vee
Power Dissipation Capacitance (Per Flip-Flop)'

=5.0 V

35

'Used to determine the no-load dynamic power consumption: PD

=CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed limit
Vee
V

-55to
25"e

:s 85"e

:s 125"e

Unit

tsu

Minimum Setup Time, J or K to Clock
(Figure 3)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Clock to J or K
(Figure 3)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

trec

tf,tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
D1129-Rev6

3-115

MOTOROLA

MC74HC107
SWITCHING WAVEFORMS

,.------VCC
RESET

CLOCK

GND

-

GND

a
tpLH

aORO

trecL

--------

Figure 1.

-

Vcc

50%

CLOCK

GND

Figure 2.

TEST POINT

VCC
JORK
GND

OUTPUT
DEVICE
UNDER
TEST

CLOCK
' - - - - - - - GND

Figure 3.
• Includes all probe and jig capacitance

Figure 4. Test Cir~uit

EXPANDED LOGIC DIAGRAM
RESET

_ _ _ _ _ _ _ _ _ _ _ _1-_ _ _ _ _ _ _ _ _ _ _ _--'

~13~,1~0

K

IT

CL

CLOCK~

MOTOROLA

3-116

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC109

Dual J-K Flip-Flop with
Set and Reset
High-Performance Silicon-Gate CMOS

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

The MC74HC109 is identical in pinouttothe LS109. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two J-K flip-flops with individual set, reset, and
clock inputs. Changes at the inputs are reflected at the outputs with the next
low-to-high transition of the clock. Both Q and Q outputs are available from
each flip-flop.
•
•
•
•
•
•
•

DSUFFIX
SOIC PACKAGE
CASE 751 B-05

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 !-LA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 148 FETs or 37 Equivalent Gates

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

PIN ASSIGNMENT
RESET 1 [ 1-

LOGIC DIAGRAM
SET 1

5
6

Kf
CLOCK 1
Jl

16

VCC

Jl [ 2

15

RESET 2

Kf [ 3

14

J2

CLOCK 1 [ 4

13

K2

SET 1 [ 5

12

CLOCK 2

01 [ 6

11

SET 2

Of [

7

10

02

GND [ 8

9

52

01

4
2

Plastic
SOIC

Of
FUNCTION TABLE

RESET 1

Inputs

SET2

K2
CLOCK 2
J2
RESET 2

Set

11
13

L
H
L
H
H
H
H
H

10 02

12
14
15

Reset Clock
H
L
L
H
H
H
H
H

Outputs

J

K

Q

Q

X

H
L

L
H

W

W

X
X
X
J
J
J
J

X

X
X
X

L
H
L
H

L
L
H
H

L

X

X

X

L
H
Toggle
No Change
H
L
No Change

• Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.

PIN 16= VCC
PIN 8=GND

10/95

© Motorola, Inc. 1995

[j]

3-117

REV6

®

MOTOROLA

MC74HC109
MAXIMUM RATINGS·
Symbol
VCC
Yin
Vout

Parameter

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5toVCC+ 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature

-65to + 150

'C

TL

Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be lell open.

'C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
. Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/'C from 65' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

0

VCC

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

VCC=2.0V
VCC = 4.5 V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl s 20~

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
lIoutl s 20llA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 20llA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Symbol

VOH

Parameter

Test Conditions

Yin = VIH or VIL lIoutl
lIoutl
VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 20~
Yin = VIH or VIL

lin
ICC

lIoutl
lIoutl

s 4.0 mA
s 5.2 mA

V

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND

6.0

4

40

80

IlA

10ut=0~

NOTE: Information on tYPical parametric values can be found

MOTOROLA

s 4.0 mA
s 5.2 mA

In

Chapter 2.

3-118

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC109
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Inputtr =·tf = 6 ns)
Guaranteed Limit
Symbol

Vee
V

,; 85°e

,; 125°e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)

2.0
4.5
6.0

175
35
30

220

ns

37

265
53
45

tpLH,
tpHL

Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

tTLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

-55to
25°e

44

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee = 5.0 V
Power Dissipation Capacitance (Per Flip-Flop)"

40

• Used to determine the no-load dynamic power consumption: PD = CpD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

,; 85°e

,; 125°e

Unit

tsu

Minimum Setup lime, J or K to Clock
(Figure 3)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold lime, Clock to J or K
(Figure 3)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Set or Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

trec

tr,tf

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-119

MOTOROLA

MC74HC109
SWITCHING WAVEFORMS

r-----SET OR
RESET

CLOCK

VCC

-GND

aORO

OORo

Ooro

rec
t } -

CLOCK

50%
________
-J

Figure 1.

__

VCC
GND

Figure 2.

JorK

~
~

TEST POINT

VALlD~
.

tSU}; th

CLOCK - - - - - - '

OUTPUT

:::

DEVICE
UNDER
TEST

-----VCC
50%
GND

Figure 3.

* Includes all probe and jig capacitance

Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM

SET .::.5,..,.tt't---% .
~------------

GND

Figure 3.
• Includes all probe and jig capacitance

Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM
RESET~15~,1~4

________________________~________________________--,

C[

CL

CLOCK~
SET 4,10

MOTOROLA·

3-124

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC125A
MC74HC126A

Quad 3-State
Noninverting Buffers
High-Performance Silicon-Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to the LS125
and LS126. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used
with 3-state memory address drivers, clock drivers, and other bus-oriented
systems. The devices have four separate output enables that are active-low
(HC125A) or active-high (HC126A).

•
',HIIII

~,~

141

NSUFFIX
PLASTIC PACKAGE
CASES4S-QS

D SUFFIX
SOIC PACKAGE
CASE 751A-Q3

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 ~A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates

ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD

Plastic
SOIC

PIN ASSIGNMENT
LOGIC DIAGRAM
HC125A

HC126A

Active-Low Output Enables

Active-High Output Enables

A1
OE1

A2
OE2

4

A3
OE3

A4
OE4

10
12
13

r
r

r~

A2

13

Y1

3

A21 5

10

6

Y2

GND I 7

4~_~-'

__
OE2

14

2

11

_ _2:...-_tr'-...J
3
Y1
OE1

6

PVee
POE4
12 PA4

1-

OE21 4
A1

Y1

I

A1

OE1

Y2

FUNCTION TABLE
HC125A

A3

Y1

~Y4

_~10,"--_tr'-...J
8

OE3

A4

_--"::'--_~...J
11

OE4

Inputs
Y3

PY4

POE3
9 PA3
8 PY3

Output

HC126A
Inputs

A

OE

Y

A

OE

Output
y

H
L
X

L
L
H

H
L
Z

H
L
X

H
H
L

H
L
Z

X = don't care
Z = high impedance
Y4

PIN 14= Vee
PIN 7 =GND

10/95

© Molorala, Inc. 1995

3-125

REV6

®

MOTOROLA

MC74HC125A MC74HC126A
MAXIMUM RATINGS'
Symbol
VCC
Yin
Vout

Parameter

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

±20

rnA
rnA

lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature

-65 to + 150

°c

TL

Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,; (Vln orVout) ,; VCC'
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g" either GND or VCC).
Unused outputs must be left open.

°C
260

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
'Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4,5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed limit
Symbol

VCC
V

-55to
25°C

,; 85°C

,; 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=VCC-O.l V
"outl ,; 20 IJA

2.0
4.5
6.0

1.5
3,15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 V
"outl ,; 20 I1A

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

VOH

,Minimum High-Level Output
Voltage

Vin=VIH
"outl ,; 20 I1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

2.0
4.5
6.0

0.1
0.1
0,1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Parameter

Test Conditions

Vin=VIH
VOL

Maximum Low-Level Output
Voltage

"outl ,; 6.0 rnA
"outl ,; 7.8 rnA

Vin=VIL
"outl s 2Ol1A
Vin=VIL

"outl s 6.0 rnA
"outl ,; 7,8 rnA

V

lin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

I1A

IOZ

Maximum Three--State Leakage
Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

I1A

ICC

Maximum Quiescent Supply
Current (per Package)

Yin = Vee or GND
lout = 0 IJA

6.0

4.0

40

160

I1A

NOTE: Information on typical parametric values can be found In Chapter 2.

MOTOROLA

3-126

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC125A MC74HC126A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Vee
V

-55to
25°e

" 85°e

" 125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)

2.0
4.5
6.0

90
18
15

115
23
20

135
27
23

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)

2.0
4.5
6.0

120
24
20

150
30
26

180
36
31

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)

2.0
4.5
6.0

90
18
15

115
23
20

135
27
23

ns

tTLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Maximum Input Capacitance

-

10

10

10

pF

Maximum Three-State Output Capacitance
(Output in High-Impedance State)

-

15

15

15

pF

Cin
Cout

Parameter

NOTE: For propagation delays with loads other than 50 pF, and Information on typical parametric values, see Chapter 2.
Typical
Power Dissipation Capacitance (Per Buffer),

@

25°e, Vee

= 5.0 V

45

• Used to determine the no-load dynamic power consumption: PD = CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
VCC

OE (HCI25A)

GND
-

VCC

INPUT A

VCC

OE(HCI26A)

11<----- GND

GND

tpLH
OUTPUTY

HIGH
IMPEDANCE

OUTPUTY

VOL
VOH
HIGH
IMPEDANCE

OUTPUTY

Figure 1.

Figure 2.

TEST POINT

TEST POINT
OUTPUT

DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

I

CL'

CONNECTTO VCC WHEN
TESTING tpLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tPHZ and tpZH.

• Includes all probe and jig capacitance

Figure 3. Test Circuit

High-Speed CMOS Logic Data
DL129- Rev 6

1 kn
[
!-='O,;:;.UT;.;,P"'U.;..T....."I/\f'v-__

Figure 4. Test Circuit

3-127

MOTOROLA

MC74HC125A MC74HC126A
HC125A
(1/4 OF THE DEVICE)

Vee

d
J-v

OE------oQ

A

9
HC126A
(1/4 OF THE DEVICE)

Vee
OE

d
J-v

--------1

A

9

MOTOROLA

3-128

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad 2-lnput NAND Gate with
Schmitt-Trigger Inputs

MC54/74HC132A

High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 632-08

The MC54174HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 646--06

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 /lA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 72 FETs or 18 Equivalent Gates

o SUFFIX
SOIC PACKAGE
CASE 751A-03

14#
1

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD

LOGIC DIAGRAM

Ceramic
Plastic
SOIC

PIN ASSIGNMENT

81

A2
Y2
82
Y:AB

A1 [ 1-

14

Vee

81 [ 2

13

84

Y1 [ 3

12

A4

A2 [ 4

11

Y4

82 [ 5

10

83

Y2 [ 6

9

A3

GND [ 7

8

Y3

A3

FUNCTION TABLE
Inputs

Output

A

B

V

L
L
H
H

L
H
L
H

H
H
H
L

PIN 14= Vee
PIN 7= GND

10/95

© Motorola. Inc. 1995

3-129

REV 6

®

ItIIOTOROLA

MC54174HC132A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lin
lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg
TL

Storage Temperature

-65to+150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND S (VinorVouu s VCC.
Unused inputs must always be
lied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
°c

260
300

" Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDeraling - Plastic DIP: -10 mWI"C from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

-

no
limit"

ns

DC Input Voltage, Output Voltage
(Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme (Figure 1)

"When Yin - 0.5 VCC, ICC » qUiescent current.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

25°C

-40°C to
+85°C

-55°Cto
+ 125°C

Unit

VT+max

Maximum Posilive-Going
Input Threshold Voltage
(Figure 3)

Vout=0.1 V
lIoutl s 20!1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VT+mln

Minimum Positive-Going
Input Threshold Voltage
(Figure 3)

Vout=0.1 V
lIoutl s 20!1A

2.0
4.5
6.0

1.0
2.3
3.0

0.95
2.25
2.95

0.95
2.25
2.95

V

VT_max

Maximum Negalive-Going
Input Threshold Voltage
(Figure 3)

Vout=VCC-0.1 V
lIoutl s 20llA

2.0
4.5
6.0

0.9
2.0
2.6

0.95
2.05
2.65

0.95
2.05
2.65

V

VT_min

Minimum Negative-Going
Input Threshold Voltage
(Figure 3)

Vout=VCC-0.1 V
lIoutl s 20!1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

VHmax
Note 2

Maximum Hysteresis Voltage
(Figure 3)

Vout=0.1 VorVcc-0.1 V
lIoutl s 20llA

2.0
4.5
6.0

1.2
2.25
3.0

1.2
2.25
3.0

1.2
2.25
3.0

V

VHmin
Note 2

Minimum Hysteresis Voltage
(Figure 3)

Vout=0.1 VorVcc-0.1 V
lIoutl s 20 !1A

2.0
4.5
6.0

0.2
0.4
0.5

0.2
0.4
0.5

0.2
0.4
0.5

V

NOTE: 1. VHmln > (VT+ min) - (VT_ max); VHmax = (VT+ max) + (VT_ min).
NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-130

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC 132A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOH

Parameter

Test Conditions

Minimum High-Level Output
Voltage

Vin,;;VT- min or VT+ max
lIoutl ,;; 20 j.lA
Vin';; -VT_ min or VT+ max
lIoutl ,;; 4.0 rnA
Iioutl ,;; 5.2 rnA

VOL

Maximum Low-Level Output
Voltage

Vin",VT+ max
lIoutl ,;; 20 j.lA
Iioutl ,;; 4.0 rnA
lIoutl ,;; 5.2 rnA

Vin",VT+max
lin
ICC

VCC
V

-55to
25'C

,;; 85'C

,;; 125'C

Unit

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

j.lA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 j.lA

6.0

1.0

10

40

j.lA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

VCC
V

-55to
25'C

,;; 85'C

,;; 125'C

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tTLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25'C, VCC
Power Dissipation Capacitance (Per Gate),

=5.0 V

24

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TEST POINT
INPUT
AORB

OUTPUT

,"""'---GND

DEVICE
UNDER
TEST

y

• Includes all probe and jig capacitance

Figure 1. Switching Waveforms

High-Speed CMOS Logic Data
DL129-Rev6

Figure 2. Test Circuit

3-131

MOTOfjOLA

MC54174HC 132A

../'"

/""

~"
v--r

v

......-:-: v

y
~

--

...- ~
f--

/'

V

~

~

~
__ f...-- ....-

-

I-"

3
4
5
Vee, POWER SUPPLY VOLTAGE (VOLTS)
VHtyP = (VT + typ) - (VT _ typ)

2

Figure 3. Typical Input Threshold, VT+, VTVersus Power Supply Voltage

Vee

~ Vout
Vin~
(a) A SeHMITI TRIGGER SQUARES UP INPUTS
WITH SLOW RISE AND FALL TIMES

(b) A SeHMITI TRIGGER OFFERS MAXIMUM NOISE
IMMUNITY

-------------------------Vee
I VH
VinL..:.
~ ---VT-

r

~
Ti-I
I
I

~VT+

---

I

I

I

I--VOH

I

I

Vee

v.~~-VT+
1r 1-

GND

Vout
VOL

-VT-

In

I

I

I

I

I

I

v~ 1 I

GND

I r:~

Figure 4. Typical Schmitt-Trigger Applications

MOTOROLA

3-132

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC133

13-lnput NAND Gate
High-Performance Silicon-Gate CMOS
The MC74HC133 is identical in pinout to the LS133. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This NAND gate features 13 inputs which surpasses most random logic
requirements.

N SUFFIX
PLASTIC PACKAGE
CASE 648-0B

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 IlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 68 FETs or 17 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751 8-05

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

Plastic
SOIC

PIN ASSIGNMENT
LOGIC DIAGRAM

A

A

1·

16

Vee

s

2

15

M

14

e

S

0

13

4

E

12

5

F

7

GND

e

0
E
F
G
H

I

G
Y

10

10

Y = A.S.e.O.E.F.G.H.I.J.K.L.M

FUNCTION TABLE

13

Output

15
PIN 16= Vee
PIN 8= GNO

10195

© Motorola, Inc. 1995

H

Y

14
M

[3J

11

11
12

K

6

K

3-133

REV6

Inputs A through M

Y

All inputs H
All other combinations

L
H

®

MOTOROLA

MC74HC133
MAXIMUM RATINGS'
Symbol
VCC

Value

Unit

-O,5to+7,O

V
V

Yin

DC Input Voltage (Referenced to GND)

-l,5to VCC + 1,5

Vout

DC Output Voltage (Referenced to GND)

- 0,5 to VCC + 0,5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

lin

Tstg

.

Parameter
DC Supply Voltage (Referenced to GND)

TL

Plastic DIPt
SOIC Packaget

Storage Temperature

-65to+150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to 'guard against damage
due to high static voltages or electric,
fields, However, precautions 'must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit For proper operation, Yin and
Vout should be constrained to the
rangeGND:s (VinorVout):S VCC,
Unused inputs must always be
. tied to an appropriate logic voitage
level (e,g" either GND or VCC),
Unused outputs must be left open,

"C
"C

260

Maximum Ratings are those values beyond which damage to the device may occur,
Functional operation should be restricted to the Recommended Operating Conditions,
tDerating - Plastic DIP: - 10 mW/"C from 65" to 125"C
SOIC Package: - 7 mWI"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2,

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC= 2,OV
VCC = 4,5 V
VCC =6,OV

Min

Max

Unit

2,0

6,0

V

0

VCC

V

-55

+ 125

"C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

-55to
25"C

:S 85"C

:S 125"C

Unit

Minimum High-Level Input
Voltage

Vout=O,l VorVCc-O,l V
Iioutl :S 20 I1A

2,0
4,5
6,0

1,5
3,15
4,2

1.5
3,15
4,2

1,5
3,15
4,2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O,l VorVCC-O,l V
lIoutl :S 20 I1A

2,0
4,5
6,0

0,3
0,9
1,2

0,3
0,9
1.2

0,3
0,9
1,2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl :S 20 I1A

2,0
4,5
6,0

1,9
4.4
5,9

1.9
4.4
5,9

1,9
4.4
5,9

V

Yin = VIH or VIL lIoutl :S 4,0 mA
lIoutl :S 5,2 mA

4,5
6,0

3,98
5.48

3,84
5,34

3,70
5,20

Yin = VIH or VIL
lIoutl :S 20 I1A

2,0
4,5
6,0

0,1
0,1
0,1

0,1
0,1
0,1

0,1
0,1
0,1

Yin = VIH or VIL lIoutl :S 4.0 mA
lIoutl :S 5,2 mA

4.5
6,0

0,26
0.26

0,33
0,33

0.40
0.40

Maximum Input Leakage Current

Vin = VCC or GND

6,0

±O,l

±l,O

± 1.0

I1A

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0!1A

6,0

2

20

40

I1A

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Test Conditions

VCC
V

VIH

VOH

Parameter

~

V

NOTE: Information on typical parametnc values can be found In Chapter 2,

3-134

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC133
AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

:5

85°e

:5

125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Any Input to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Packager

=5.0 V

27

• Used to determine the no-load dynamic power consumption: Po

=CpO Vee2f + lee Vee. For load considerations, see Chapter 2.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 2. Test Circuit

Figure 1. Switching Waveforms

LOGIC DIAGRAM
A
B

C
D
E

;>o--=--y

G

H

K

M

High-Speed eMOS Logic Data
DL129-Rev6

3-135

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

'----_M_C_7_4_H_C_1_3_7-----11

1-01-8 Decoder/Demultiplexer
with Address Latch
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 64B-OB

The MC74HC137 is identical in pinout to the LS 137. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC137 decodes a three-bit Address to one-of-eight active-low
outputs. The device has a transparent latch for storage of the Address. Two
Chip Selects, one active-low and one active-high, are provided to facilitate
the demultiplexing, cascading, and chip-selecting functions.
The demultiplexing function is accomplished by using the Address inputs.
to select the desired device output, and then by using one of the Chip
Selects as a data input while holding the other one active.
The HC137 is the inverting version of the HC237.
•
•
•
•
•
•
•

DSUFFIX
SOIC PACKAGE
CASE 751 8-05

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 152 FETs or 38 Equivalent Gates

PIN ASSIGNMENT

{M

A
1

A2

LATCH ENABLE

2
3

4

TRANSPARENT
LATCH

AO [ 1-

16

VCC

A1 [ 2

15

YO

A2 [ 3

14 ~ Y1

LATCH ENABLE [ 4

13

CS2 [ 5

12

CS1 [ 6

11

YO

Y7 [ 7

10

Y1

GND [ 8

9

LOGIC DIAGRAM

ADDRESS
INPUTS

Plastic
SOIC

P Y2
~

Y3

P Y4
P Y5
~

Y6

Y2
l-OF-8
DECODER

Y3
Y4

ACTIVELOW
OUTPUTS

Y5
·Y6

FUNCTION TABLE

Y7
Inputs

Outputs

LE CS1 CS2 A2 A1 AO YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
CHIP- {CS1
SELECT
INPUTS C S 2 - - = - - - - - - - - - - - - '

PIN 16=VCC
PIN8= GND

X
X

X
L

H
X

X
X

X
X

X
X

H
H

H
H

H
H

H
H

H
H

H
H

H
H

H
H

L
L
L
L

H
L
H
L
H . L
H
L

L
L
L
L

L
L
H
H

L
H
L
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H

H

L

X

X

X

.

• = Depends upon the Address previously applied while LE was
at a low level.

10/95

© Motorola, Inc. 1995

3-136

REV 6

®

MOTOROLA

MC74HC137
MAXIMUM RATINGS'
Symbol
VCC
Vin
Vout

Parameter

Value

Unit

-0.5to+7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

±20

mA
mA

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

Po

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature

- 65 to + 150

°c

TL

Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND,;; (VinorVout)';; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCe).
Unused outputs must be left open.

°c
260

• MaXimum Ratings are those values beyond which damage to the deVice may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol
VCC
Vin, Vout

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 2)

VCC = 2.0 V
VCC = 4.5 V
VCC= 6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

-55to
25°e

,;; 85°C

,;; 125°C

Unit

Minimum High-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
lIoutl ,;; 20!1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
lIoutl ,;; 20!1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl ,;; 20!1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl ,;; 4.0 mA
lIoutl ,;; 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
lIoutl ,;; 20 !1A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL lIoutl ,;; 4.0 mA
lIoutl ,;; 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

!1A

Vin = VCC or GND
lout = 0!1A

6.0

8

80

160

!1A

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

Test Conditions

Vee
V

VIH

VOH

Parameter

V

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-137

MOTOROLA

MC74HC137
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

,,;; 85°e

,,;; 125°e

Unit

2.0
4.5
6.0

170
34
29

215
43
37

255
51
43

ns

2.0
4.5
6.0

240
48
41

300
60
51

360
72
61

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

2.0
4.5
6.0

195
39
33

245
49
42

295
59
50

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

2.0
4.5
6.0

250
50
43

315
63
54

375
75
64

Maximum Output Transition TIme, Any Output
(Figures 2 and 6)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol
tpLH

Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 6)

tpHL

tpLH

Maximum Propagation Delay, CSl or CS2 to Output Y
(Figures 2, 3 and 6)

tpHL

tpLH

Maximum Propagation Delay, Latch Enable to Output Y
(Figures 4 and 6)

tpHL

ITLH,
ITHL
Cin

ns

ns

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Package)"

=5.0 V

100

"Used to determine the no-load dynamic power consumption: PD = CpD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

,,;; 85°e

,,;; 125°e

Unit

tsu

Minimum Setup TIme, Input A to Latch Enable
(Figure 5)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold TIme, Latch Enable to Input A
(Figure 5)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

tw

Minimum Pulse Width, Latch Enable
(Figure 4)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tr,tf

Maximum Input Rise and Fall TImes
(Figure 2)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

Parameter

NOTE: Information on tYPical parametric values can be found

MOTOROLA

In

Chapter 2.

3-138

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC137
PIN DESCRIPTIONS
ADDRESS INPUTS

Latch Enable (Pin 4)

AO, A1, A2 (Pins 1, 2, 3)

Latch-Enable input. A high level at this input latches the
Address. A low level at this input allows the outputs to follow
the data at the Address pins (CS1 =Hand CS2 =L).

Address inputs. These inputs, when the chip is enabled,
determine which of the eight outputs is selected.

OUTPUTS
CONTROL INPUTS

VO-V7

CS1, CS2 (Pins 6, 5)

Active-low outputs. One of these eight outputs is selected
when the chip is enabled (CS1 = Hand CS2 = L) and the
data on the AO, A1, and A2 inputs correspond to that particular output. The selected output is at a low level while all
others remain at a high level.

Chip-Select inputs. For CS1 at a high level and CS2 at a
low level, the chip is enabled and the outputs follow the address inputs (Latch Enable =L). For any other combination of
CS1 and CS2, the outputs are at a high level.

SWITCHING· WAVEFORMS

J:------ VCC
Vcc

INPUT A

eS2

IpLH

GND

GND

tPLH:.J;
OUTPUTY

OUTPUTY

50%

Figure 1.
Figure 2.

Vee

eSl

vcc

LATCH
ENABLE

GND

OUTPUTY

OUTPUTY
trLH

Figure 3.

Figure 4.

TEST POINT
Vec

OUTPUT

INPUT A

DEVICE
UNDER
TEST

GND
tsu
Vcc

LATCH
ENABLE

GND

I

CL'

* Includes all probe and jig capacitance

Figure 5.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 6. Test Circuit

3-139

MOTOROLA

MC74HC137
EXPANDED LOGIC DIAGRAM

AO

A1

A2
LATCH
ENABLE

CS1

CS2

MOTOROLA

3-140

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

1-01-8 Decoder/Demultiplexer

MC54/74HC138A

High-Performance Silicon-Gate CMOS
The MC54/74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC138A decodes a three-bit Address to one-of-eight active-low
outputs. This device features three Chip Select inputs, two active-low and
one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output; one of the Chip Selects is
used as a data input while the other Chip Selects are held in their active
states.
•
•
•
•
•
•
•

~

16~II~UU

NSUFFIX
PLASTIC PACKAGE
CASE 648-0B

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 I'A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 100 FETs or 29 Equivalent Gates

ADDRESS
INPUTS

DSUFFIX
SOIC PACKAGE
CASE 751B-{)5

DTSUFFIX
TSSOP PACKAGE
CASE 948F-Ol

LOGIC DIAGRAM

l

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

VO

AO

VI
V2
V3

AI
A2

V5
V6

PIN ASSIGNMENT

V7

AO

1·

At! 2

~::

1

3

A2
PIN 16= VCC
PIN 8= GND

_...:.4_ _ _...J

CS2

CS3--~5_ _ _ _~

FUNCTION TABLE
Inputs

Ceramic
Plastic
SOIC
TSSOP

ACTIVE-LOW
OUTPUTS

V4

CHIPSELECT
INPUTS

JSUFFIX
CERAMIC PACKAGE
CASEB20-10

r

4

CS3

5

CSI

6

Y7

7

GND

8

PVCC
PVO
14 PVI
13 PV2
12 PV3
11 PV4
10 PV5
9 PV6
16
15

Outputs

CS1CS2CS3 A2 A1 AO VO V1 V2 V3 V4 V5 V6 V7
X
X
L

X
H
X

H
X
X

X
X
X

X
X
X

X
X
X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L

'L
L
L

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H = high level (steady state); L = low level (steady state);
X = don't care

10195

© Motorola, Inc. 1995

3-141

REV 6

®

MOTOROLA

MC54/74HC138A
MAXIMUM RATINGS'
Symbol

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

-65to+150

'c
'c

VCC
Vin
Vout
lin

Tstg
TL

Parameter
DC Supply Voltage (Referenced to GND)

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guatd against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND:s; (VinorVout):S; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/~C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
TSSOP Package: - 6.1 .w/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall lime
(Figure 2)

VCC = 2.0 V
VCC=4.5V
VCC= 6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55'C to
25'C

:s; 85'C

:s; 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC -0.1 V
lIoutl :s; 20 IlA

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
lIoutl :s; 20 IlA

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

VOH

Minimum High-Level Output
Voltage

Vin = VIH or VIL
Iioutl :s; 20 IlA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl :s; 2.4 rnA
lIoutl :s; 4.0 rnA
lIoutl :s; 5.2 rnA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

MOTOROLA

Parameter

Vee
V

3-142

High-Speed CMOS Logic Data
DL129-Rev6

MC54n4HC138A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

lin
ICC

Vee
V

-55°e to
25°C

s 85°C

s 125°C

Unit

Vin = VIH or VIL
lIoutl s 20 JlA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Vin = VIH or VIL lIoutl s 2.4 mA
lIoutl s 4.0 mA
lIoutl s 5.2 mA

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

I!A

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 I!A

6.0

4

40

160

I!A

Vee
V

-55°C to
25°C

s 85°C

s 125°C

Unit

Parameter

Test Conditions

Maximum Low-Level Output
Voltage

NOTE: InformallOn on tYPical parametric values can be found In Chapter 2.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Parameter

tPLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)

2.0
3.0
4.5
6.0

135
90
27
23

170
125
34
29

205
165
41
35

ns

tpLH,
tpHL

Maximum Propagation Delay, CSl to Output Y
(Figures 2 and 4)

2.0
3.0
4.5
6.0

110
85
22
19

140
100
28
24

165
125
33
28

ns

tPLH,
tpHL

Maximum Propagation Delay, CS2 or CS3 to Output Y
(Figures 3 and 4)

2.0
3.0
4.5
6.0

120
90
24
20

150
120
30
26

180
150
36
31

ns

tTLH,
ITHL

Maximum Output Transition lime, Any Output
(Figures 2 and 4)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

NOTE: For propagation delays with loads other than 50 pF, and information on tYPical parametric values, see Chapter 2.
Typical @ 25°C, Vee
Power Dissipation Capacitance (Per Package)"

=5,0 V

55

"Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-143

MOTOROLA

MC54/74HC138A
SWITCHING WAVEFORMS

VCC

INPUTCSI

GND

OUTPUTY

Figure 1.

Figure 2.

TEST POINT
J:----VCC

OUTPUT
DEVICE
UNDER
TEST

OUTPUTY
ITLH
* Includes all probe and jig capacitance

Figure 3.

Figure 4. Test Circuit

PIN DESCRIPTIONS
ADDRESS

It~PUTS'

Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic high.

AD, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is active-low.

OUTPUTS
YO - Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)

CONTROL INPUTS

Active-low Decoded outputs. These outputs assume a low
level when addressed and the chip is selected. These outputs remain high when not addressed or the chip is not
selected.

CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the

MOTOROLA

3-144

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC 138A
EXPANDED LOGIC DIAGRAM

CS3
CS2

CS1_6~~--------~

High-Speed CMOS Logic Data
DL129-Rev6

3-145

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HCT138A

1-of-8 Decoder/Demultiplexer
with LSTTL Compatible Inputs
High-Performance Silicon-Gate CMOS

N SUFFIX
PLASTIC PACKAGE
CASE 641HJ8

The MC74HCT138A is identical in pinout to the LS138. The HCT138A
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The HCT138A decodes a three-bit Address to one-of-eight active-lot
outputs. This device features three Chip Select inputs, two active-low and
one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output; one of the Chip Selects is
used as a data input while the other Chip Selects are held in their active
states.

DSUFFIX
SOIC PACKAGE
CASE 7518-05
DTSUFFIX
TSSOP PACKAGE
CASE 948F-01

• Output Drive Capability: 10 LSTTL Loads
• TTUNMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 IlA
• In Compliance with the Requirements Defined by JEDEC Standard
Ncr.7A
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates

ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXAD
MC74HCTXXXADT

PiN ASSIGNMENT

LOGIC DIAGRAM

[3J
ADDRESS
INPUTS

r
A1

15
2

A2

YO
Y1
Y2
Y3
Y4

Plastic
SOIC
TSSOP

AO [ 1·

16 ~ VCC

Ad 2

15 ~ YO

Ad 3

14 ] Y1
13

CS3 [ 5

12

csd

PY4
10 PV5

6

Y2
Y3

11

V7 [ 7

ACTIVE-LOW
OUTPUTS

~
~

CS2 [ 4

GND [ 8

9

PV6

Y5
Y6
Y7

CHIPSELECT
INPUTS

I

~::

FUNCTION TABLE
Outputs

Inputs

_....:.4_ _ _-'

CS3-~5------,
Design Criteria

PIN 16=VCC
PIN 8=GND

Value

Units

30.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

JlW

.0075

pJ

Internal Gate Count'

Speed Power Product

CS1CS2 CS3 A2 A1 AO YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L

X
H
X

H
X
X

X
X
X

X
X
X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H
H

L
L
L
L
L
L
L
L

L
L
L
L

L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

L
L
L
L

H = high level (steady state)
L = low level (steady state)
X = don't care

'Equivalent to a two-input NAND gate.

10195

© Motorola, Inc. 1995

X
X
X

3-146

REV 6

®

MOTOROLA

MC74HCT138A
MAXIMUM RATINGS·
Symbol
VCC
Vin
Vout
lin

Parameter

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

DC Supply Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500
450

mW

Tstg

Storage Temperature

-65to+150

°c

TL

Plastic DIPt
SOIC Packaget
TSSOP Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, TSSOP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: - 7 mW;oC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall lime (Figure 1)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

°c

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=O.l VorVCC-O.l V
lIoutl s 20llA

4.5
5.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.l VorVCC-O.l V
lIoutl s 20 I!A

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl s 20llA

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

Vin = VIH or VIL
"outl S 4.0 I!A

4.5

3.98

3.84

3.7

Vin = VIH or VIL
"outl S 20llA

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Symbol

VOH

VOL

Parameter

Maximum Low-Level Output
Voltage

Test Conditions

V

Vin = VIH or VIL
"outl S 4.0 mA

4.5

0.26

0.33

0.4

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

IlA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 I!A

5.5

4.0

40

160

IlA

AICC

Additional Quiescent Supply
Current

Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 IlA

lin

NOTE: Information on typical parametric values can be found

High-Speed CMOS Logic Data
DL129-Rev6

In

5.5

;"-55°C

25°C to 125°C

2.9

2.4

mA

Chapter 2.

3-147

MOTOROLA

MC74HCT138A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
-55to
25°e

s 85°e

s 125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)

30

38

45

ns

tpLH,
tpHL

Maximum Propagation Delay, CS1 to Output Y
(Figures 2 and 4)

27

34

41

ns

tpLH,
tpHL

Maximum Output Transition lime, CS2 or CS3 to Output Y
(Figures 3 and 4)

30

38

45

ns

ITLH,
ITHL

Maximum Output Transition lime, Any Output
(Figures 2 and 4)

15

19

22

ns

500

500

500

ns

10

10

10

pF

Symbol

Parameter

t r, tf

Maximum Input Rise and Fall lime

Cin

Maximum Input Capacitance

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per Enabled Output)'

=5.0 V

51

'Used to determine the no-load dynamic power consumption: PD = CpD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

EXPANDED LOGIC DIAGRAM

CS3
CS2--....._ _

CS1_6~------------~--I

MOTOROLA

3-148

High-Speed CMOS Logic Data
DL129-Rev6

MC74HCT138A
SWITCHING WAVEFORMS

-3V

3V
INPUT A

INPUTCSI

1.3 V

IF-----GND

GND

.~J.
OUTPUT Y

OUTPUTY

1.3 V
trLH

Figure 2.

Figure 1.

11-----3V
INPUT
CS2, CS3

-GND
tPLH

OUTPUTY

Figure 3.

TEST CIRCUIT

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 4.

High-Speed CMOS Logic Data
DL129-Rev6

3-149

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54!74HC139A

Dual 1-01-4 Decoder!
Demultiplexer
High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 62D-l0

The MC54174HC139A is identical in pinout to the LS139. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 1-of-4 decoders, each of which
decodes a two-bit Address to one-of-four active-low outputs. Active-low
Selects are provided to facilitate the demultiplexing and cascading functions.
The demultiplexing function is accomplished by using the Address inputs to
select the desired device output, and utilizing the Select as a data input.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 648-Q8

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 j.lA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 100 FETs or 25 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751 9-05

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD

Ceramic
Plastic
SOIC

LOGIC DIAGRAM
PIN ASSIGNMENT
ADDRESS {ADa
INPUTS
Ala

4

2
3

~~:

PVCC
PSELECTb
14 PAOb

SELECTa [ 1-

16
15

} ACTIVE-LOW
Y2a
OUTPUTS

AO a [ 2

Y3a

YOa [ 4

13

Yl a [ 5

12

SELECTa - ' - - - - - '

Y2a [ 6

PY1b
10 PY2b

14

GND [ 8

Ala [ 3

,

11

Y3a [ 7
ADDRESS { ADb
INPUTS
A1 b 13

DAlb
DYOb

9

DY3b

YOb}
Y1b
ACTIVE-LOW
Y2b
OUTPUTS
Y3b

FUNCTION TABLE
Inputs

SELECTb _1~5_ _--,

Outputs

Select

A1

AO

YO

Y1 Y2

Y3

H
L
L
L
L

X
L
L
H
H

X
L
H
L
H

H
L
H
H
H

H
H
L
H
H

H
H
H
H
L

PIN 16=VCC
PIN8=GND

H
H
H
L
H

x = don't care

10195

© Motorola, Inc. 1995

3-150

REV6

®

MOTOROLA.

MC54174HC139A
MAXIMUM RATINGS·
Symbol

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to + 150

°C

VCC
Vin

Vout
'in

Parameter
DC Supply Voltage (Referenced to GND)

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ,; (Vin or Vout) ,; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol

VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+125

°C

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC = 2.0 V
VCC=4.5V
VCC = 6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25°C

,; 85°C

,; 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
1I0uti ,; 20 IlA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 VorVcC -0.1 V
1I0uti ,; 20 IlA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
1I0uti ,; 20 IlA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Parameter

VCC
V

Vin = VIH or VIL

VOL

Maximum Low-Level Output
Voltage

Vin = VIH or VIL
1I0uil ,; 20 IlA
Vin = VIH or VIL

lin
ICC

1I0uti ,; 4.0 mA
1I0uti ,; 5.2 mA

1I0uti ,; 4.0 rnA
1I0uti ,; 5.2 rnA

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

± 1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
10ut=01lA

6.0

4

40

160

IlA

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-151

MOTOROLA

MC54174HC139A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Vee
V

-55to
25°e

:s 85°e

:s 125°e

Unit

tPLH.
tpHL

Maximum Propagation Delay, Select to Output Y
(Figures 1 and 3)

2.0
4.5
6.0

115
23
20

145
29
25

175
35
30

ns

tpLH.
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 3)

2.0
4.5
6.0

115
23
20

145
29
25

175
35
30

ns

trLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°e, Vee = 5.0 V
Power Dissipation Capacitance (Per Decoder)"

55

• Used to determine the no-load dynamic power consumption: PD

=CpD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS

-':-----Vcc
INPUT A

Vcc

y

GND

tPLH

OUTPUTY

OUTPUTY

50%

trLH

Figure 2.

Figure 1.

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 3. Test Circuit

MOTOROLA

3-152

High-Speed CMOS Logic Data
DL129-Rev6

MC54/7 4HC 139A
PIN DESCRIPTIONS
outputs for that particular decoder follow the Address inputs.
A high level on this input forces all outputs to a high level.

ADDRESS INPUTS
AOa, A1 a , AOb, A1b (Pins 2, 3, 14, 13)
Address inputs. These inputs, when the respective 1-of-4
decoder is enabled, determine which of its four active-low
outputs is selected.

OUTPUTS
YOa - Y3 a, YOb - Y3b (Pins 4 -7,12,11,10,9)
Active-low outputs. These outputs assume a low level
when addressed and the appropriate Select input is active.
These outputs remain high when not addressed or the appropriate Select input is inactive.

CONTROL INPUTS
Selecta, Selectb (Pins 1, 15)
Active-low select inputs. For a low level on this input, the

EXPANDED LOGIC DIAGRAM
(1/2 OF DEVICE)

SELECT

YO

Y1

AO

Y2

Y3
A1

High-Speed CMOS Logic Data
DL129- Rev 6

3-153

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC147

Decimal-Io-BCD Encoder
High-Performance Silicon-Gate CMOS
The MC74HC147 is identical in pinout to the LS147. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device encodes nine active-low data inputs to four active-tow BCD
Address Outputs, ensuring that only the highest order active data line is
encoded. The implied decimal zero condition is encoded when all nine data
inputs are at a high level (inactive).

N SUFFIX
PLASTIC PACKAGE
CASE 64S-oS

o SUFFIX
SOIC PACKAGE
CASE 7518-05

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 IlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 136 FETs or 34 Equivalent Gates

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

Plastic
SOIC

PIN ASSIGNMENT
16

D5 [ 2

15 ~ NC

Ds[ 3

14

D1

D7 [ 4

13

D2

D8 [ 5

12

LOGIC DIAGRAM

D3
DECIMAL
DATA INPUTS
(ACTIVE-LOW)

avCC

D4 [ 1-

D4
D5
D6

AO}
A1
A2
A3

P D3
P D2
11 PD1
10 P D9
9 P AO

A2 [ 6
BCD
ADDRESS
OUTPUTS
(ACTIVE-LOW)

o A3

Ad 7
GND [ 8

NC = NO CONNECTION

D7
D8

FUNCTION TABLE

D9
VCC = PIN 16
GND = PIN 8
NO CONNECTION = PIN 15

09 08 07 06 05 04 03 02 01 A3 A2 A1 AO
H
H
H
H
H
H
H
H
H
L

H
H
H
H
H
H
H
H
L
X

H
H
H
H
H
H
H
L
X
X

10195

© Motorola, Inc. 1995

Outputs

Inputs

3-154

REV 6

H
H
H
H
H
H
L
X
X
X

H
H
H
H
H
L
X
X
X
X

H
H
H
H
L
X
X
X
X
X

H
H
H
L
X
X
X
X
X
X

®

H
H
L
X
X
X
X
X
X
X

H
L
X
X
X
X
X
X
X
X

H
H
H
H
H
H
H
H
L
L

H
H
H
H
L
L
L
L
H
H

H
H
L
L
H
H
L
L
H
H

H
L
H
L
H
L
H
L
H
L

MOTOROLA

MC74HC147
MAXIMUM RATINGS·
Symbol

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

- 65 to + 150

°c

VCC
Vin
Vout
lin

Parameter
DC Supply Voltage (Referenced to GND)

Plastic DIPt
SOIC Packaget

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :5 (Vin or Voutl :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mWI'C from 65° to 125°C
SOIC Package: -7 mWI'C from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

t r, tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC= 4.5 V
VCC= 6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25°C

:5 85°C

:5 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
"outl :5 20 I!A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.l VorVCc-O.l V
"outl :5 20 I!A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Parameter

VCC
V

"outl :5 20 I!A

Yin = VIH or VIL lIoutl :5 4.0 mA
"outl :5 5.2 mA

VOL

Maximum Low-Level Output
Voltage

Vin=VIH
"outl :5 20 I!A

Yin = VIH or VIL lIoutl :5 4.0 rnA
lIoutl :5 5.2 rnA
lin
ICC

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

I!A

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 I!A

6.0

8

80

160

I!A

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-155

MOTOROLA

MC74HC147
AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Input tr = tf = 6 ns)
Guaranteed limit
Vee
V

':'55 to
25"e

s 85"e

s 125"e

Unit

tPlH,
tpHl

Maximum Propagation Delay, Input D to Output A
(Figures 1 and 2)

2.0
4.5
6.0

220
44
37

275
55
47

330
66
56

ns

ITlH,
ITHl

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical

@

Power Dissipation Capacitance (Per Package)'

25°e, Vee

=5.0 V

35

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TEST POINT
OUTPUT

---GND

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 1. Switching Waveforms

MOTOROLA

Figure 2. Test Circuit

3-156

High-Speed CMOS logic Data
Dl129- Rev 6

MC74HC147
EXPANDED LOGIC DIAGRAM

")O.....--=-- AO

04

~.....-....;7_A1

06

::>O--"--A2

DB

5

09

10

High-Speed CMOS Logic Data
DL129-Rev6

14

3-157

A3

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC151

a-Input Data
Selector/Multiplexer
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

The MC74HC151 is identical in pinout to the LS151. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as determined by
the Address Inputs. The Strobe pin must be at a low level for the selected
data to appear at the outputs. If Strobe is high, the Y output is forced to a low
level and the Y output is forced to a high level.
The HC151 is similar in function to the HC251 which has 3-state outputs.
•
•
•
•
•
•

DSUFFIX
SOIC PACKAGE
CASE 7518-05

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard '

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXO

PIN ASSIGNMENT

NO.7A

•

Chip Complexity: 132 FETs or 33 Equivalent Gates

03 [ 1-

16

Vee

02 [ 2

15

04

01 [ 3
DO [ 4

14

05

13

06

Y[ 5

12

07

Y[ 6

11

AD

01

STROBE [ 7

10

AI

02

GNO [ 8

9

A2

LOGIC DIAGRAM

DO 4

DATA
INPUTS

Plastic
SOIC

Y}

03
04 15

05 14

DATA
OUTPUTS

6 Y

FUNCTION TABLE

06 13
07 12

Inputs

A2

At

AO

Strobe

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

AI~~~~~S { ~ -'""_ _-'
STROBE - ' - - - - - - '
PIN 16= Vee
PIN8=GNO

Outputs
y
y
L
00
01
02
03
04
05
06
07

H
00
01
02
03
04
05
06
07

00, 01, "., 07 = the level of the respective
o input.

10195

© Motorola, Inc, 1995

3-158

REV 6

®

MOTOROLA

MC74HC151
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature

-65to+ 150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must, always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
°c

260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time
(Figure 1)

VCC = 2.0 V
VCC = 4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=0.1 VorVcc-0.1 V
lIoutl s 20llA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=0.1 VorVcc-0.1 V
lIoutl s 20llA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl s 20 IlA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
lIoutl s 20 IlA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL lIoutl s 4.0 rnA
Iioutl s 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Vin = Vce or GND

6.0

±0.1

±1.0

±1.0

!lA

Maximum Quiescent Supply
Current (per Package)

Vin = Vce or GND
lout = 0 IlA

6.0

8

80

160

IlA

Symbol

VOH

Parameter

Test Conditions

Vin=VIH
VOL

lin
ICC

Maximum Low-Level Output
Voltage

lIoutl s 4.0 rnA
lIoutl s 5.2 rnA

V

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev 6

3-159

MOTOROLA

MC74HC151
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input D to Output Y or Y
(Figures 1, 3 and 6)

2.0
4.5
6.0

185
37
31

230
46
39

280
56
48

ns

tPLH,
tpHL

Maximum Propagation Delay, Input A to Output Y or Y
(Figures 2 and 6)

2.0
4.5
6.0

205
41
35

255
51
43

310
62
53

ns

tpLH,
tpHL

Maximum Propagation Delay, Strobe to Output Y or Y
(Figures 4, 5 and 6)

2.0
4.5
6.0

125
25
21

155·
31
26

190
38
32

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 6)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

36

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

PIN DESCRIPTIONS
INPUTS

Strobe (Pin 7)

Data inputs. Data on anyone of these eight binary inputs
may be selected to appear on the output.

Strobe. This input pin must be at a low level for the selected data to appear at the outputs. If the Strobe pin is high,
the Y output is forced to a low level and the Youtput is forced
to a high level.

CONTROL INPUTS

OUTPUTS

AO; A1, A2 (Pins 11, 10, 9)

V,

Address inputs. The data on these pins are the binary address of the selected input (see the Function Table).

Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.

00,01, ... , 07 (Pins 4,3,2,1,15,14,13,12)

MOTOROLA

3-160

Y (Pins 5, 6)

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC151
SWITCHING WAVEFORMS

-Vee
INPUTD

INPUT A
11'--------- GND
tpHL

~

VAlID~ VALID Jcvee

50%

tPLH:fo

OUTPU!
YORY

OUTPUTY

50%

f

GND
tPHL

_________

~

tTHL

Figure 1.

Figure 2.

1------- Vee
STROBE

11'------- GND

Y
trHL

Figure 3.

Figure 4.

TEST POINT

.r-----Vee

OUTPUT
DEVICE
UNDER
TEST

-GND
tpLH

trLH
• Includes all probe and jig capacitance

Figure 5.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 6. Test Circuit

3-161

MOTOROLA

MC74HC151
EXPANDED LOGIC DIAGRAM

DO
Dl

4
3

D2 2
D3
DATA
INPUTS

Y}

D4 15

DATA

Y OUTPUTS
D5 14
D6 13
D7 12

ADDRESS
INPUTS

STROBE 7

MOTOROLA

3-162

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC153

Dual 4-lnput Data
Selector/Multiplexer
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

The MC74HC153 is identical in pinout to the LS153. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The Address Inputs select one of four Data Inputs from each multiplexer.
Each multiplexer has an active-low Strobe control and a noninverting
output.

DSUFFIX
SOIC PACKAGE
CASE 7518-05

The HC153 is similar in function to the HC253, which has 3-state outputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 j.lA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 108 FETs or 27 Equivalent Gates

ORDERING INFORMATION

MC74HCXXXN
MC74HCXXXO

PIN ASSIGNMENT
STROBE a [ 1·

LOGIC DIAGRAM

ADDRESS { AO 14
INPUTS
A1 ...!2++-_ _ _ _ _-l
DATAWaRDa
INPUTS

I

DOa
D1
a
D2a
D3a

6
5

Plastic
SOIC

7 Va

16

~ Vee

Ad 2

15

~

D3 a [ 3

14

~AO

D2a [ 4

13

~

D3b

D1a [ 5

12

~

D2b

DOa [ 6

11

~

D1b

Va [ 7

10

GND [ 8

9

~
~

Vb

STROBEb

DOb

4
3

FUNCTION TABLE
Inputs

STROBE a ...1'--_ _--'

DATAWORDb
INPUTS

I

DOb 10
D1b 11
12
D2b
D3b 13

Output

A1

AD

Strobe

Y

X
L
L
H
H

X
L
H
L
H

H
L
L
L
L

L
00
01
02
03

00, 01, 02, and 03 = the level of the
respective data input.

STROBE b . . :1.;:. 5_ _ _-'
PIN 16= Vee
PIN8=GND

10/95

© Motorola, Inc. 1995

3-163

REV 6

®

MOTOROLA

MC74HC153
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature

-65to+150

°c

lin

TL

Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (Vin orVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

Min

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC = 4.5 V
VCC = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

s

85°C

s

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=O.1 VorVCC-0.1 V
lIoutl s 20 IIA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

V,L

Maximum Low-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl s 20 IIA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = V,H or V,L
lIoutl s 20 IIA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Yin = V,H or V,L
VOL

Maximum Low-Level Output
Voltage

'in

s
s

4.0 rnA
5.2 mA

Yin = V,H or V,L
lIoutl s 20llA
Yin = V,H or V,L

ICC

lIoutl
lIoutl

lIoutl
lIoutl

s
s

4.0 rnA
5.2 rnA

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

± 1.0

±1.0

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 IIA

6.0

8

80

160

V

IIA
IIA

NOTE: Information on tYPical parametric values can be found In Chapter 2.

MOTOROLA

3-164

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC153
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr =tf = 6 ns)
Guaranteed Limit
Symbol

Vee
V

-55to
25°e

,,; 85'e

,,; 125'e

Unit

tpLH,
tPHL

Maximum Propagation Delay, Input D to Output Y
(Figures 1, and 4)

2.0
4.5
6.0

140
28
24

175
35
30

210
42
36

ns

tPLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLH,
tpHL

Maximum Propagation Delay, Strobe to Output Y
(Figures 3, and 4)

2.0
4.5
6.0

95
19
16

120
24
20

145
29
25

ns

tTLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per Multiplexer)"

=5.0 V

31

• Used to determine the no-load dynamic power consumption: PD = CpD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
tr

.-Vee

Vee

INPUT D

INPUT A

I"f-----GND

GND

tPLH:fo

OUTPUTY

OUTPUTY

50%

Figure 1.

Figure 2.

TEST POINT
r----Vee

OUTPUT

STROBE

DEVICE
UNDER
TEST

OUTPUTY
trHL
• Includes all probe and jig capacitance

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 4. Test Circuit

3-165

MOTOROLA

MC74HC153
PIN DESCRIPTIONS
DATA INPUTS

Strobe (Pins 1, 15)

DOa - D3a, DOb - D3b (Pins 3, 4, 5, 6, 10, 11, 12, 13)

Active-low Strobe. A low level applied to these pins enables the corresponding outputs.

Data Inputs. With the outputs enabled, the addressed Data
Inputs appear at the Youtputs.

OUTPUTS

CONTROL INPUTS

Va, Vb (Pins 7, 9)

AO, A1 (Pins 2,14)
Address Inputs. These inputs address the pair of Data
Inputs which appear at the corresponding outputs.

Noninverting data outputs.

EXPANDED LOGIC DIAGRAM

DOa
DATA
WORD a
INPUTS

D1a
D2a

4

D3a

NON INVERTING
DATA
OUTPUTS

DOb 10

[3]
DATA
WORDb
INPUTS

D1b 11
D2b 12
D3b 13

ADDRESS
INPUTS

MOTOROLA

3-166

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

1-01-16 Decoder/Demultiplexer

MC54/74HC154

High-Performance Silicon-Gate CMOS
The MC54/74HC154 is identical in pinout to the LS154. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device, when enabled, selects one of 16 active-low outputs. Two
active-low Chip Selects are provided to facilitate the chip-select, demultiplexing, and cascading functions. When either Chip Select is high, all
outputs are high. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output. Then, while holding one
chip select input low, data can be applied to the other chip select input (see
Application Note).
The HC154 is primarily used for memory address decoding and data
routing applications.
•
•
•
•
•
•
•

~

24~'~

1

•
~

24"

1

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 JlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 192 FETs or 48 Equivalent Gates

CHIP {
SELECT eS1
INPUTS CS2

l

ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
YO

1-

24

YO

Y1

2

23

Y1
Y2
Y3
Y4

Y2

3

22

Y3

4

21

Y4

5

20

Y5

6

19

ACTIVE-LOW
OUTPUTS

P Vee
P AD
D A1
D A2

Y6

7

P A3
PeS2
1B P eS1

Y7

B

17

YB

9

Y9

10

PY14
15 PY13

Y10

11

14

D Y12

GND

12

13

PY11

D Y15

16

PIN 24= Vce
PIN 12=GND

10195

© Motorola, Inc. 1995

DWSUFFIX
SOIC PACKAGE
CASE 751 E-04

1

AO 23
A1 22
A2 21
A3 20

NSUFFIX
PLASTIC PACKAGE
CASE 724-03

24~

LOGIC DIAGRAM

BINARY
ADDRESS
INPUTS

JSUm,

CERAMIC PACKAGE
CASE 758-02

3-167

REV 6

®

MOTOROLA

MC54174HC154
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

- 0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC+ 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+150

°c

lin

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
(Ceramic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol

VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to Gl'ilD)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 2)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

s

85°C

s

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl s 20 I!A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC -0.1 V
lIoutl S 20J.lA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl S 20 I!A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl S 4.0 rnA
lIoutl S 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
lIoutl S 20 I!A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL

lin
ICC

lIoutl S 4.0 rnA
lIoutl S 5.2 rnA

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

± 1.0

±1.0

I!A

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
10ut=0 J.lA

6.0

8

80

160

J.lA

NOTE: Information on typical parametric values can be found 10 Chapter 2.

MOTOROLA

'3-i68

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC154
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

-55to
25'e

s 85'e

s 125'e

Unit

tPLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)

2.0
4.5
6.0

190
38
32

240
48
41

285
57
48

ns

tPLH,
tpHL

Maximum Propagation Delay, CS to Output Y
(Figures 2 and 3)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 2 and 3)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

Vee
V

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical

@

Power Dissipation Capacitance (Per Package)'

25'e, Vee

=5.0 V

80

'Used to determine the no-load dynamic power consumption: PD = CpO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

PIN DESCRIPTIONS
INPUTS

when addressed and both chip-select inputs are active.
These outputs remain high when not addressed or a chipselect input is high.

AO, A1, A2, A3 (Pins 23, 22, 21, 20)
Address inputs. These inputs, when the l-of-16 decoder
is enabled, determine which of its sixteen active-low outputs
is selected.

CONTROL INPUTS
CS1, CS2 (Pins 18, 19)

OUTPUTS

Active-low chip-select inputs. With low levels on both of
these inputs, the outputs of the decoder follow the Address
inputs. A high level on either input forces all outputs high.

YO - Y15 (Pins 1 -11, 13 -17)
Active-low outputs. These outputs assume a low level

FUNCTION TABLE
Inputs

Outputs

eS1

eS2

A3

A2

A1

AD

YO

Yl

Y2

Y3

Y4

Y5

V6

Y7

V8

yg

Yl0

Yl1

Y12

Y13

Y14

Y15

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L

L
H
H

H
L
H

X
X
X

X
X
X

X
X

X
X

X

X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H = High Level, L = Low Level, X = Don't Care

High-Speed CMOS Logic Data
DL129-Rev6

3-169

MOTOROLA

MC54/74HC154
SWITCHING WAVEFORMS

INPUT A

VCC

L-----VCC

GND

-GND

tPLH.:fo
OUTPUTY
.

50%

OUTPUTY
trLH

Figure 1.

Figure 2.

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 3. Test Circuit

TYPICAL APPLICATIONS

AO--r-.
Al----1
A2---I
A3---I

AO--r-.

YO
I

Al----1
A2----1

A3----1

yI5
DATA INPUT ---<:I

STROBE

1 OF 16 DEMULTIPLEXER
SELECTED OUTPUT'S LOGIC LEVEL
FOLLOWS LOGIC LEVEL ON DATA INPUT

1 OF 16 DECODER
SELECTED OUTPUT IS LOW

MOTOROLA

3-170

High-Speed CMOS Logic Data
DL129":'" Rev 6

MC54/74HC154
EXPANDED LOGIC DIAGRAM

..----..
CS1
CS2

18

]

19

I

J

'\

2

"

....--...

/

..----..

Y1

3 Y2

23

4

5

Y3

Y4

~

....--...

6 Y5

7
A1

YO

~

....--...

AO

1

--I.-

Y6

~

22

8 Y7

....--...
A2

21

9

-;:=::I

1>-4>

- -

10

~

11

t:::=L....--...

A3

13

t:::f

20

~

t:::=L..----..

~

Y9

Y10

Y11

14 Y12

15

~

~

Y8

Y13

16 Y14

~

17

-t:::::L-

High-Speed CMOS Logic Data
DL129-Rev6

3-171

Y15

MOTOROLA

[3J

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC157A

Quad 2-lnput Data
Selectors/Multiplexers
High-Performance Silicon-Gate CMOS
The MC54174HC157A is identical in pinout to the LS157. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTIL outputs.
This device routes 2 nibbles (A or 8) to a single port (Y) as determined by
the Select input. The data is presented at the outputs in non inverted form. A
high level on the Output Enable input sets all four Y outputs to a low level.
The HC157A is similar in function to the HC257 which has 3-state, outputs.
•
•
•

Output Drive Capability: 10 LSTIL Loads
'
Outputs Directly Interface to CMOS, NMOS, and TIL
Operating Voltage Range: 2.0 to 6.0 V
o Low Input Current: 1.0 ~
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 82 FETs or 20.5 Equivalent Gates

J SUFFIX
CERAMIC PACKAGE
CASE 620-10

N SUFFIX
PLASTIC PACKAGE
CASE 648"{)8

16'

DSUFFIX
SOIC PACKAGE
CASE 7518-05

1

DTSUFFIX
TSSOP PACKAGE
CASE 948F-01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

lOGIC DIAGRAM

~

NIBBLE
A INPUTS

NIBBLE
B INPUTS

r
r
A1

:

2
5

PIN ASSIGNMENT

11

SELECT

14
4

7
9

,6

B1
10
B2
13
B3

SELECT'
OUTPUT
ENABLE

Ceramic
Plastic
SOIC
TSSOP

12

~}
V1
V2
V3

DATA'
OUTPUTS
.

1-

16

AD

2

15

Vee

BO

3

VO

4

OUTPUT
ENABLE
14 J A3
13 ] B3

AI

5

12 ~ V3

Bl [ 6

11 ~ A2

VI [ 7

10 ] B2

GND [ 8

9 ~ V2

15

FUNCTION TABLE

PIN 16= VCC
PIN8=GND

Inputs
Output
Enable

Select

Outputs
VO-V3

H
L
L

X
L
H

L
AD-A3
80-83

x = don't care
AD - A3, 80 - 83 = the levels
of the respective Data-Word
Inputs.

10195

© Motorola, Iny. 1995

3-172

REV6

®

MOTOROLA

MC54/74HC157A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

- 65 to + 150

°c

lin

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC = 6.0 V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

:5 85°C

:5 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl :5 20 f.lA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl :5 20 f.lA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl :5 20 f.lA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl :5 4.0 rnA
"outl :5 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

Vin = VIH or VIL
lIoutl :5 20 f.lA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL lIoutl :5 4.0 rnA
lIoutl :5 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

VOH

VOL

Maximum Low-Level Output
Voltage

High-Speed CMOS Logic Data
DL129-Rev6

3-173

V

MOTOROLA

MC54174HC157A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed limit
VCC
V

-55 to
25°C

s 85°C

s 125°C

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

~

Vin = VCC or GND

6.0

4.0

40

160

IlA

Vec
V

-55to
25°C

s 85°e

s 125°e

Unit

tpLH.
tpHL

Maximum Propagation Delay. Input A or B to Output Y
(Figures 1 and 4)

2.0
4.5
6.0

105
21
18

130
26
22

160
32
27

ns

tPLH.
tpHL

Maximum Propagation Delay. Select to Output Y
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

tpLH.
tpHL

Maximum Propagation Delay. Output Enable to Output Y
(Figures 3 and 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

trLH.
trHL

Maximum Output Transition lime. Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Parameter

lin

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

ICC

Test Conditions

Unit

10ut=0~

NOTE: Information on tYPical parametric values can be found In Chapter 2.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF. Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Cin

Parsmeter

NOTE: For propagation delays with loads other than 50 pF. and information on typical parametric values. see Chapter 2.
Typical @ 25°e. Vec
Power Dissipation Capacitance (Per Package)"

=5.0 V

33

"Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations. see Chapter 2.

PIN DESCRIPTIONS
INPUTS

these outputs when the Output Enable input is at a low level.
The data present on these pins is in its noninverted form. For
the Output Enable input at a high level. the outputs are at a
low level.

AD, Al, A2, A3 (Pins 2, 5,11,14)
Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.

CONTROL INPUTS

BO, Bl, B2, B3 (Pins 3, 6, 10, 13)

Select (Pin 1)

Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level
and the Output Enable input is at a low level. The data is
presented to the outputs in non inverted form.

Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)

OUTPUTS

Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.

YO, Yl, Y2, V3 (Pins 4,7,9,12)
Data outputs. The selected input Nibble is presented at

MOTOROLA,

3-174

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC 157A
SWITCHING WAVEFORMS
Ir

-

VCC
SELECT

INPUTAOR B

11'----- GND

1'----GND

IPLH
OUTPUTY

OUTPUTY

trHL

Figure 2. Y versus Select, Noninverted

Figure 1. HC157A

-VCC
OUTPUT
ENABLE

_---GND

OUTPUTY

trLH

Figure 3. HC157A
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM

AO~2~---------------r~
BO~3~-----------r---r~
A1~~-----~~;-~
B1~~-----~~;-~

NIBBLE
OUTPUTS

A2 -...:1.;,.1____________+-+-,~

DATA
OUTPUTS

B2-...:1~O____________+-+-I~

A3

B3
OUTPUT ENABLE
SELECT

High-Speed CMOS Logic Data
DL129-Rev6

14

13
15

3-175

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad 2-lnput Data
Selector/Multiplexer with
LSTTL Compatible Inputs

MC74HCT157A
N SUFFIX
PLASTIC PACKAGE
CASE 64!HlB

High-Performance Silicon-Gate CMOS
The MC74HCT157A is identical in pinout to the LS157. This device may
be used as a level converter for interfacing TTL or NMOS outputs to High
Speed CMOS inputs.
This device routes 2 nibbles (A or B) to a single port (V) as determined by
the Select input. The data is presented at the outputs in noninverted form. A
high level on the Output Enable input sets all four V outputs to a low level.
The HCT157A is similar in function to the HC257 which has 3-state
outputs.

DSUFFIX
SOIC PACKAGE
CASE 7516-05
ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXAD

• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 itA
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 102 FETs or 25.5 Equivalent Gates

PIN ASSIGNMENT
SELECT

BO

VCC
OUTPUT
ENABLE
A3

A1

Y3

AO

LOGIC DIAGRAM

[3]
NIBBLE
A INPUTS

NIBBLE
B INPUTS

r
r

A1
11
A2
14
A3

93

4

3

7
9

B1
10
B2
13
B3

12

~}
Y1
Y2

DATA
OUTPUTS

GND

Y2

Inputs
Output
Enable

H
L
L

15

Value

Unit

25.5

ea

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

0.005

I!W

Speed Power Product

0.0075

pJ

Internal Gate Count'

A2

B2

FUNCTION TABLE

PIN 16=VCC
PIN8=GND

Design Criteria

B1
Y1

Y3

SELECT
OUTPUT ENABLE

Plastic
SOIC

Outputs
Select

YO-Y3

X

L
AO-A3
80-83

L
H

X = don't care
AD - A3, 80 - 83 = the levels
of the respective Data-Word
Inputs.

, EqUivalent to a two Input NAND gate.

10195

© Motorola, Inc. 1995

3-176

REV 6

®

MOTOROLA

MC74HCT157 A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V

Vin

DC Input Voltage (Referenced to GND)

-1.5toVCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

'in

DC Input Current, per Pin

±20

rnA

'out

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

Po

Power Dissipation in Still Air

750
500

mW

- 65 to + 150

°C

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND S (Vin or Vout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'c
260

• MaxImum RatIngs are those values beyond whIch damage to the deVIce may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall lime (Figure 1)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

°C

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C
2.0
2.0

2.0
2.0

2.0
2.0

V

S

85°C

S

125°C

Unit

V,H

Minimum High-Level Input
Voltage

Vout=O.l VorVCC-O.l V
lIoutl S 20~

4.5
5.5

V,L

Maximum Low-Level Input
Voltage

VoutO.1 VorVcc-O.l V
lIoutl S 20mA

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output
Voltage

Vin = V,H or V,L
lIoutl S 20mA

4.5
5.5

44
5.4

4.4
5.4

4.4
5.4

V

Vin = V,H or V,L
lIoutl S 4.0 mA

4.5

3.98

3.84

3.7

Vin = V,H or V,L
lIoutl S 20 ~A

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

VOH

VOL

'in
ICC

!.ICC

Maximum Low-Level Output
Voltage

V

Vin = V,H or V,L
lIoutl S 4.0 mA

4.5

0.26

0.33

0.4

Vin = VCC or GND

5.5

±0.1

±1.0

±1.0

~A

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND

5.5

4.0

40

160

~A

Additional Quiescent Supply
Current

Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs

Maximum Input Leakage Current

10ut=0~

10ut=0~

5.5

~-55°C

25'C to 125°C

2.9

2.4

rnA

NOTE: InformatIon on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-177

MOTOROLA

MC74HCT157A
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ± 10%. CL =50 pF. Input tr =tf =6.0 ns)
Guaranteed Limit
-55to
25°e

,; 85°e

tpLH.
tpHL

Maximum Propagation Delay. Input A or B to Output Y
(Figures 1 and 4)

27

34

41

ns

tpLH.
tpHL

Maximum Propagation Delay. Select to Output Y
(Figures 2 and 4)

37

46

56

ns

tPLH.
tpHL

Maximum Propagation Delay. Output Enable to Output Y
(Figures 3 and 4)

30

38

45

ns

trLH.
trHL

Maximum Output Transition Time. Any Output
(Figures 1 and 4)

15

19

22

ns

500

500

500

ns

Symbol

t r• tf

Parameter

Maximum Input Rise and Fall Time

s

125°e

Unit

NOTE: For propagation delays with loads other than 50 pF. and information on typical parametric values. see Chapter 2.
Typical @ 25°e. Vee
Power Dissipation Capacitance (Per Transceiver Channel)-

=5.0 V

64

- Used to determine the no-load dynamic power consumption: PD = CpD VCC 2 f + ICC VCC. For load considerations. see Chapter 2.

PIN DESCRIPTIONS
INPUTS

these outputs when the Output Enable input is at a low level.
The data is presented to the outputs in non inverted form. For
the Output Enable input at a high level, the outputs are at a
low level.

AO, A1, A2, A3 (Pins 2,5,11,14)
Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level
and the Output Enable input is at a low level. The data is
presented to the outputs in non inverted form.

CONTROL INPUTS

BO, B1, B2, B3 (Pins 3,6,10,13)

Select (Pin 1)

Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.

Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output

OUTPUTS

VO, V1, V2, V3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at

MOTOROLA

Enable (Pin 15)

Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.

3-178

High-Speed CMOS Logic Data
D1129-Rev6

MC74HCT157A
EXPANDED LOGIC DIAGRAM
AO

2

BO
A1
B1
NIBBLE
INPUTS

A2
B2
A3
B3

11

DATA
OUTPUTS

10
14
13

OUTPUT ENABLE
SELECT

SWITCHING WAVEFORMS
tr

INPUTAORB

3V
SELECT

11<----- GND

1"1<----- GND

tPLH
OUTPUTY

OUTPUTY
trHL

Figure 2.

Figure 1.

TEST POINT
OUTPUT

-VCC
DEVICE
UNDER
TEST

OUTPUT ENABLE
GND
tPLH
OUTPUTY
tTLH

• Includes all probe and jig capacitance

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 4. Test Circuit

3-179

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC158

Quad 2-lnput Data
Selector/Multiplexer
High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 620-10

The MC54174HC158 is identical in pinout to the LS158. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These devices route 2 nibbles (A or B) to a single port (V) as determined by the Select input. The data is presented at the outputs in inverted
form for the HC158. A high level on the Output Enable input sets all four V
outputs to a high level for the HC158.

NSUFFIX
PLASTIC PACKAGE
CASE 64B-OB

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL

DSUFFIX
SOIC PACKAGE
CASE 751B--05

16#

• Operating Voltage Range: 2 to 6V
• Low Input Current: 11lA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements

ORDERING INFORMATION

• Chip Complexity: 74 FETs or 18.5 Equivalent Gates

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

LOGIC DIAGRAM

Ceramic
Plastic
SOIC

FUNCTION TABLE
Inputs

Outputs

Output
Enable

Select

Vo-V3

H

X

L
L

L

H
AD-A3

H

BO-B3

X = Don't Care
AO-A3, BO-B3 = the levels of the respec-

tive Data-Word inputs.

Pinout: 16-Lead Plastic Package (Top View)
Output
Vee Enable

A3

Select

BO

B3

Y3

A2

A1

B1

B2

GND

10/95

© Motorola, Inc. 1995

3-180

REV 7

®

MOTOROLA

MC54/74HC158
MAXIMUM RATINGS'
Symbol
VCC
Vin
Vout

Parameter
DC Supply Vollage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V
mA

lin

DC Input Current, per Pin

±20

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

TL

Storage Temperature

-65to+150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

°c

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Vollage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°C

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time
(Figure 2)

VCC = 2.0 V
VCC=4.5V
VCC = 6.0 V

DC CHARACTERISTICS (Voltages Referenced to GND)

-55 to 25°C

s85°C

S125°C

Unit

Vout = 0.1V orVCC -0.1V
lioutl S 201iA

2.0
4.5
6.0

1.50
3.15
4.20

1.50
3.15
4.20

1.50
3.15
4.20

V

Maximum Low-Level Input Voltage

Vout = O.tV orVcc - O.tV
lioutl S 2011A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lioutl S2011A

2.0
4.5
6.0

1.9
4.4
5.9

t.9
4.4
5.9

t.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

Vin = VCC or GND
lout = 01iA

6.0

8

80

160

Parameter

VIH

Minimum High-Level Input Voltage

VIL

VOH

Condition

Vin =VIH or VIL
VOL

Maximum Low-Level Output
Voltage

ICC

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

1I0uti S 4.0mA
lioutl S 5.2mA

Vin = VIH or VIL
lioutl S2011A
Vin = VIH or VIL

lin

Guaranteed Limit

VCC
V

Symbol

lioutl S 4.0mA
liout' S 5.2mA

V

IiA
IiA

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-181

MOTOROLA

MC54174HC158

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

Guaranteed Limit

Vcc
V

-55 to 25°C

~oC

,,125°C

Unit

tpLH,
tPHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 5)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tpLH,
tpHL

Maximum Propagation Delay, Select to Output Y
(Figures 3 and 5)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tpLH,
tpHL

Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 5)

2.0
4.5
6.0

.115
23
20

145
29
25

175
35
30

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 2 and 5)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

10

10

10

pF

Cin

Maximum Input Capacitance

NOTE: For propagatIOn delays with loads other than 50 pF, and information on tYPical parametric values, see Chapter 2.
Typical @ 25"C, VCC
Power Dissipation Capacitance (Per Package)'

=5.0 V

35

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC.. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS

-

-

VCC

InputAorB

VCC

Select

-=-----

~---------- GND

GND

OutputY

OutputY

trLH

trLH
Figure 2. Y versus Select, Inverted

Figure 1.

TEST
POINT

" - - - - - - GND

OUTPUT
DEVICE
UNDER
TEST

I

CL'

'Includes all probe and jig capacitance
Figure 4. Test Circuit

Figure 3.

MOTOROLA

3--182

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC158
PIN DESCRIPTIONS
INPUTS

The data present on these pins is in its inverted form for the
HC158. Forthe Output Enable input at a high level, the outputs
are at a high level for the HC158.

AO-A3 (Pins 2,5,11,14)
Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158.

CONTROL INPUTS

80-83 (Pins 3,6,10,13)

Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects the
A inputs and a high level selects the B inputs.

Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158.
OUTPUTS

Output Enable (Pin 15)
Output Enable input. A low level on thisinput allows the
selected data to be presented at the outputs. A high level on
this input sets all of the outputs to a high level for the HC158.

YO-Y3 (Pins 4,7,9,12)
Data outputs. The selected input nibble is presented at
these outputs when the Output Enable input is at a low level.

AO 2
4
BO 3

YO

[3J

A1 5

7
B1 6

Y1

Nibble
Inputs

Data
Outputs

A2 11
9

B2 10

Y2

A3 14
12
B3

Output Enable

13

Y3

15

Select

Figure 5. Expanded Logic Diagram

High-Speed CMOS Logic Data
DL129-Rev6

3--183

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC158A

Advance Information
Quad 2-lnput Data
Selector/Multiplexer
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 64S-QS

The MC74HC158A is identical in pinout to the LS158. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These devices route 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in inverted
form for the HC158A. A high level on the Output Enable input sets all four
Y outputs to a high level for the HC158A.

DSUFFIX
SOIC PACKAGE
CASE 7519-05

• Output Drive Capability: 10 LSTTL Loads
• Outputs Direclly Interface to CMOS, NMOS and TTL

DTSUFFIX
TSSOP PACKAGE
CASE 948F-01

• Operating Voltage Range: 2 to 6V
• Low Input Current: 111A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 74 FETs or 18.5 Equivalent Gates

ORDERING INFORMATION

LOGIC DIAGRAM

MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

2

[3J

Nibble
A Inputs

[M

A1
A2
A3

11
14
4

7
Nibble
8 Inputs

[00
81
:

Plastic
SOIC
TSSOP

12

10

~]
Y1
Y2

FUNCTION TABLE
Data
Outputs

Inputs

Y3

13

Select

YO-Y3

H

X

L
L

L
H

H
AO-A3

Pin 16= vee
Pin8=GND

Select

Outputs

Output
Enable

BO-B3

x =Don't Care

Output
Enable

AO-A3, BO-B3 = the levels of the respective Data-Word inputs.

Pinout: 16-Lead Plastic Package (Top View)
Output
Enable

Select

A3

80

83

Y3

A2

82

Y2

A1

81

Y1

GND

This document contains information on a new product. Specifications and information herein are subject to
change without notice.

3/96

© Motorola, Inc. 1996

3-184

REV 0

®

MOTOROLA

MC74HC158A
MAXIMUM RATINGS·
Symbol

Value

Unit

-0.5to + 7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current. per Pin

±20

mA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air,

750
500
450

mW

Tstg

Storage Temperature

VCC
Vin
Vout
lin

TL

Parameter
DC Supply Voltage (Referenced to GND)

Plastic DIPt
SOIC Packaget
TSSOP Packaget

-65to+150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :S (Vin or Vout) :S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'c
'C

260

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125'C
TSSOP Package: - 6.1 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 2)

VCC=2.0V
VCC=3.0V
VCC=4.5V
VCC = 6.0V

Min

Max

2.0

6.0

Unit
V

0

VCC

V

-55

+ 125

'c

0
0
0
0

1000
600
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55'Cto
25'C

:S 85'C

:S 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
lIoutl :S 20 JlA

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 V or VCC - 0.1 V
lIoutl :S 20 JlA

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl :S 20 jlA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl :S 2.4 rnA
lIoutl :S 4.0 rnA
lIoutl :S 5.2 rnA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

VOH

Parameter

VCC
V

High-Speed CMOS Logic Data
DL129-Rev6

3-185

MOTOROLA

MC74HC158A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed limit
Symbol
VOL

lin
ICC

Parameter

Test Conditions
Vin =VIH or VIL
lIoutl s 20!IA

Maximum Low-Level Output
Voltage

VCC
V

-55°Cto
25°C

s 85°C

s 125°C

Unit

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Vin

=VIH or VIL

Maximum Input Leakage Current

Vin

=VCC or GND

6.0

±0.1

±1.0

±1.0

!IA

Maximum Quiescent Supply
Current (per Package)

Vin =VCC or GND
lout =0 I1A

6.0

4

40

160

!IA

VCC
V

-55°C to
25°C

NOTE: Information on tYPical parametric values can be found

In

lIoutl
lIoutl
lIoutl

s 2.4 rnA
s 4.0 rnA
s 5.2 rnA

Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit

s 85°C

s 125°C

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)

2.0
3.0
4.5
6.0

125
85
25
21

155
95
31
26

190
110
38
32

ns

tpLH,
tpHL

Maximum Propagation Delay, CS1 to Output Y
(Figures 2 and 4)

2.0
3.0
4.5
6.0

125
85
25
21

155
95
31
26

190
110
38
32

ns

tpLH,
tpHL

Maximum Propagation Delay, CS2 or CS3 to Output Y
(Figures 3 and 4)

2.0
3.0
4.5
6.0

115
80
23
20

145
90
29
25

175
100
35
30

ns

t-rLH,
t-rHL

Maximum Output Transition Time, Any Output
(Figures 2 and 4)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin·

Parameter

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametnc values, see Chapter 2.
Typical @ 25°C, VCC
Power Dissipation Capacitance (Per Package)'

=5.0 V

35

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-186

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC158A
SWITCHING WAVEFORMS

tr
Vcc
Input Aor B

Vcc
Select
~-----GND

- . ; ; . - - - - - GND

OutputY

OutputY

trLH

trLH

Figure 1.

Figure 2. Y versus Select, Inverted

TEST
POINT

Vcc

Output Enable

- . ; ; . - - - - - GND

OUTPUT
DEVICE
UNDER
TEST

OutputY
·Includes all probe and jig capacitance

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 4. Test Circuit

3-187

MOTOROLA

MC74HC158A
PIN DESCRIPTIONS
INPUTS

The data present on these pins is in its inverted form for the
HCI58A. For the Output Enable input at a high level, the out·
puts are at a high level for the HC158A.

Ao-A3 (Pins 2,5,11,14)
Nibble A inputs. The data present on these pins is trans·
ferred to the outputs when the Select input is at a low level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HCI58A.

CONTROL INPUTS

So-S3 (Pins 3,6,10,13)
Nibble 8 inputs. The data present on these pins is trans·
ferred to the outputs when the Select input is at a high level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158A.

Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects the
A inputs and a high level selects the 8 inputs.

OUTPUTS

Output Enable (Pin 15)
Output Enable input. A low level on thisinput allows the
selected data to be presented at the outputs. A high level on
this input sets all of the outputs to a high level forthe HCI58A.

Vo-V3 (Pins 4,7,9,12)
Data outputs. The selected input nibble is presented at
these outputs when the Output Enable input is at a low level.

AO 2
4
80 3

[3J

YO

A1 5

7
81 6

Y1

Nibble
Inputs

Data
Outputs

A2 11

9
82 10

Y2

A3 14
12
83

Output Enable

13

Y3

15

Select

Figure 5. Expanded Logic Diagram

MOTOROLA

3-188

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC160
MC54/74HC162

Presettable Counters
High-Performance Silicon-Gate CMOS
The MC54/74HC160 and HC162 are identical in pinout to the LS160 and
LS162, respectively. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC160 and HC162 are programmable BCD counters with asynchronous and synchronous Reset inputs, respectively.
•
•
•
•
•
•
•

J SUFFIX
CERAMIC PACKAGE
CASE 62Q-l0

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 ~A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 234 FETs or 58.5 Equivalent Gates

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

DSUFFIX
SOIC PACKAGE
CASE 7516-05

LOGIC DIAGRAM
ORDERING INFORMATION

r

14

CLOCK 2

15

PRESENT
DATA
INPUTS

P1

4

13 01

OOj

12

P2

11

P3

02

BCD OR
BINARY
OUTPUTS

03

PIN ASSIGNMENT

RIPPLE
CARRY
OUT

RESET [ 1-

16

~

CLOCK [ 2

15

~

Pll 4

13

~

P2 [ 5

12 ~ 02

VCC
RIPPLE
] CARRY OUT
14 00

PO [ 3

RESET

10

ENABLE P [ 7

Device

Count
Mode

PIN 16 = VCC
PIN 8 = GND

01

11 ~ 03

P3 [ 6

LOAD - - - - - - '
COUNT { ENABLE P
ENABLES
ENABLE T _ _ _ _ _ _ _...J

Ceramic
Plastic
SOIC

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

GND [ 8

J ENABLET

9 JLOAD

FUNCTION TABLE
Inputs

Reset Mode
Clock

HC160

BCD

Asynchronous

HC162

BCD

Synchronous

.r
.r
.r
.r
.r

Output

Reset'

Load

EnableP

EnableT

Q

L

X

H

L
H
H
H

X
X

X
X

Reset
Load Preset Data
Count
No Count
No Count

H
H
H

H
L

H

X
L

X

• HC162 only. HC160 is an Asynchronous Reset Device
H = high level
L= low level
X = don't care

10/95

© Molorola, Inc. 1995

3-189

REV6

®

MOTOROLA

MC54174HC160 MC54174HC162
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to+ 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

mA

lin

DC Input Current, per Pin

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
.range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., eitner GND or VCC).
Unused outputs must be left open.

°c
260
300

• MaxImum RatIngs are those values beyond whIch damage to the devIce may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall iime
(Figure 1)

0

VCC

V

-55

+125

°c

0
0
0

1000
500
400

ns

VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

s

85°C

s

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout= 0.1 Vor VCC - 0.1 V
1I0uti S 20ilA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
1I0uti s 20 !lA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIout' s 20 !lA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL 1I0uti s 4.0 mA
1I0uti S 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
1I0ut' s 20 !lA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

VOL

Maximum Low-Level Output
Voltage

Vin = VIH or VIL 1I0ut'
1I0uti
lin
ICC

s
s

4.0 mA
5.2 mA

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

!lA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 ilA

6.0

8

80

160

ilA

NOTE: InformatIon on tYPIcal parametric values can be found In Chapter 2.

MOTOROLA

3-190

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC160 MC54/74HC162
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)*
(Figures 1 and 7)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH

Maximum Propagation Delay, Clock to Q
(Figures 1 and 7)

2.0
4.5
6.0

170
34
29

215
43
37

255
51
43

ns

2.0
4.5
6.0

205
41
35

255
51
43

310
62
53

Symbol

Parameter

tpHL

tpHL

Maximum Propagation Delay, Reset to Q (HC160 Only)
(Figures 2 and 7)

2.0
4.5
6.0

210
42
36

265
53
45

315
63
54

ns

tpLH

Maximum Propagation Delay, Enable T to Ripple Carry Out
(Figures 3 and 7)

2.0
4.5
6.0

160
32
27

200
40
34

240
48
41

ns

2.0
4.5
6.0

195
39
33

245
49
42

295
59
50

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

2.0
4.5
6.0

215
43
37

270
54
46

325
65
55

tpHL

tpLH

Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 1 and 7)

tpHL

ns

tpHL

Maximum Propagation Delay, Reset to Ripple Carry Out
(HC160 Only)
(Figures 2 and 7)

2.0
4.5
6.0

220
44
37

275
55
47

330
66
56

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 7) .

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

• Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f max . However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f max in the table above is applicable.
See Applications Information in this data sheet.
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'C, Vce
Power Dissipation Capacitance (Per Package)*

=5.0 V

60

• Used to determine the no-load dynamic power consumption: Po = CpO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-191

MOTOROLA

MC54174HC160 MC54174HC162
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

s

85°e

s

125°e

Unit

tsu

Minimum Setup Time, Preset Data Inputs to Clock
(Figure 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tsu

Minimum Setup Time, Load to Clock
(Figure 5)

2.0
4.5
6.0

135
27
23

170
34
29

205
41
35

ns

tsu

Minimum Setup TIme, Reset to Clock (HC162 only)
(Figure 4)

2.0
4.5
6.0

160
32
27

200
40
34

240
48
41

ns

tsu

Minimum Setup TIme, Enable T or Enable P to Clock
(Figure 6)

2.0
4.5
6.0

200
40
34

250
50
43

300
60
51

ns

th

Minimum Hold TIme, Clock to Preset Data Inputs
(Figure 5)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

th

Minimum Hold TIme, Clock to Load
(Figure 5)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

th

Minimum Hold TIme, Clock to Reset (HC162 only)
(Figure 4)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

th

Minimum Hold Time, Clock to Enable T or Enable P
(Figure 6)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

trec

Minimum Recovery TIme, Reset Inactive to Clock (HC160 only)
(Figure 2)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tree

Minimum Recovery TIme, Load Inactive to Clock
(Figure 5)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset (HC160 only)
(Figure 2)

2.0
4.5
6.0

80

100
20

ns

17

120
24
20

Maximum Input Rise and Fall TImes
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

tr,tf

NOTE: Information on tYPical parametnc values can be found

MOTOROLA

In

16
14

Chapter 2.

3-192

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC160 MC54/74HC162
CONTROL FUNCTIONS

FUNCTION DESCRIPTION

Resetting

The HC160/162 are programmable 4-bit synchronous
counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading, and countenable controls.
The HC160 and HC162 are BCD counters with asynchronous Reset, and synchronous Reset, respectively.

A low level on the Reset pin (pin 1) resets the internal flipflops and sets the outputs (00 through 03) to a low level.
The HC160 resets asynchronously and the HC162 resets
with the rising edge of the Clock input (synchronous reset).
Loading
With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data Input pins (PO, Pl, P2,
P3) into the internal flip-flops and onto the output pins, 00
through 03. The count function is disabled as long as Load is
low.
Although the HC160 and HC162 are BCD counters, they
may be programmed to any state. If they are loaded with a
state disallowed in BCD code, they will return to their normal
count sequence within two clock pulses (see the Output
State Diagram).

INPUTS
Clock (Pin 2)
The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition,
control functions, such as resetting (HC162) and loading
occur with the rising edge of the Clock input.
Preset Data Inputs PO, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. PO (pin 3)
is the least-significant bit and P3 (pin 6) is the most-significant bit.

Count Enable/Disable
These devices have two count-enable control pins: Enable P (pin 7) and Enable T (pin 10). The devices count when
these two pins and the Load pin are high. The logic equation
is:
Count Enable =Enable P • Enable T • Load

OUTPUTS
QO, Q1, Q2, Q3 (Pins 14, 13, 12, 11)

The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a countenable control; Enable T is both a count-enable and a
Ripple-Carry Output control.

These are the counter outputs (BCD or binary). 00 (pin 14)
is the least-significant bit and 03 (pin 11) is the most-significant bit.

Table 1. Count Enable/Disable

Ripple Carry Out (Pin 15)

Ripple Carry Out =

Result at Outputs

Control Inputs

When the counter is in its maximum state (1001 for the
BCD counters or 1111 for the binary counters), this output
goes high, providing an external look-ahead carry pulse that
may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count
state. The logic equation for this output is:

Load

EnableP

EnableT

QO-Q3

Ripple Carry Out

H
L

H

H

Count

H

H

No Count

High when 00-03
are maximum*

X

L

H

No Count

High when 00-03
are maximum*

L
X
X
L
No Count
*00 through 03 are maximum for the HC160 and HC162 when
03 02 0100 = 1001.

Enable T • 00 • 01 • 02 • 03
for BCD counters HC160 and
HC162

OUTPUT STATE DIAGRAMS
HC160 and HC162 BCD Counters

High-Speed CMOS Logic Data
DL129-Rev6

3-193

MOTOROLA

MC54174HC160 MC54/74HC162
SWITCHING WAVEFORMS

,-----VCC
CLOCK

RESET

-GND
tPHL

F-

ANY
OUTPUT
ANY
OUTPUT

tree

CLOCK _ _ _ _ _ _ _ _5_0%...J,

Figure 2.

Figure 1.

-VCC

ENABLET

_~~~

RESET

GND
tsu

RIPPLE
CARRY
OUT

------VCC
CLOCK
-GND

trHL

Figure 3.

raJ

INPUTS
PO, P1,
P2, P3

Figure 4. HC162 Only

VCC
GND

VCC
LOAD

ENABLET
OR
ENABLE P

~

VALlD~ VCC

50%

GND

t s u y ; th

VCC

CLOCK

CLOCK
______
...J

FigureS,

-----VCC
50%
-GND

Figure 6.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 7.

MOTOROLA

3-194

High-Speed CMOS Logic Data
DL129-Rev6

o~

MC54HC160. MC74HC160
BCD Counter with Asynchronous Reset

~cg.

"";;::

@
b
eg.
o

PO

3

P1

4

P2

5

P3

6

~

o

~

r.
~

15

§~~~~
OUT

ENABLE P
Vcc = PIN 16
,GND=PIN8

~

$:

o01

~I

o......
0)

;;::

~:0

o

s;:

RESIT~ ~:
-Y:>o-- ~C

CLOCK

LOAD

~

C>c--LOAD
L..--'---LOAD

o
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A ToggleEnable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from
Preset inputs PO, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (e) high and resets the Q
output of the flip-flop low.

~

$:

o
~

01

~

I

o
......

0)
l\)

MC54174HC160 MC54174HC162
HC~60, HC162 TIMING DIAGRAM

Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to BCD seven.
3. Count to eight, nine, zero, one, two, and three.
4. Inhibit.

U r-~==-===~-------------­
(ASYNCHRONOUS)

RESET (HC160) - - - - ,
RESET (HC162) - - - - ,

! Ir--~~==~------------(SYNCHRONOUS)

LLI

LOAD

.J
Pl .J
P2 .J

I

IU
I

PO

PRESET
DATA
INPUTS

~---4---------------------CLOCK(HC160) - - - h
CLOCK (HC162)

COUNT {ENABLE P
ENABLES

ENABLE T - - - - ! - - 1 - '

OUTPUTS

I

:~===LH
---8---------'---------

02

03 - - - :

RIPPLE

C~~~Y

I
I

t t
RESET

MOTOROLA

:

Ii----,L...--------t--------

I
I
I7 I8

n

1:-0-..,.1-~2--:-3;-,- - - - - - - - -

---COUNT----~I·"--- INHIBIT----

14
..
1

LOAD

3-196

High-Speed CMOS Logic Data
DL129-Rev6

~~

MC54HC160. MC74HC160
BCD Counter with Synchronous Reset

~:::T

1\)1

"'en

lal

Jl~

~

~

000

(')

"'S:

aen

b

~.

o

PO

3

P1

4

P2

5

P3

6

~

!:
!!l

15 RIPPLE
CARRY
OUT
ENABLE P 7
VCC = PIN 16
IGND=PIN8

:)

s::

()
(}1

~

I

()
-'-

0>

RESET 1

s:

~
~

>

CLOCK

LOAD

~

.l..{>

o

R
[:>O---C
L..-":"""---C

[:>0---

LOAD
L..-":"""---LOAD

The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A ToggleEnable flip-flop is a combination of a 0 flip-flop and a T flip-flop. When loading data from
Preset inputs PO, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (e) high and resets the Q
output of the flip-flop low.
.

s::

()
(}1

~I

()

0>

I\)

~

MC54174HC160 MC54/74HC162
TYPICAL APPLICATIONS
CASCADING
N-Blt Synchronous Counters
LOAD------1---------------------~--------------------~--------------.

INPUTS

H=COUNT
L= DISABLE

INPUTS

ENABLE P

H=COUNT
L= DISABLE

INPUTS

ENABLE P
RIPPLE
CARRY
OUT

ENABLET

ENABLE P
RIPPLE
CARRY
OUT

ENABLET

CLOCK

CLOCK

RESET

TO
MORE
SIGNIFICANT
STAGES

RIPPLE
CARRY
OUT

ENABLET
CLOCK

.

.

OUTPUTS

OUTPUTS
CLOCK

NOTE: When used in these cascaded configurations the clock f max guaranteed limits may not apply. Actual performance will depend on
number of stages. This limitation is due to set up times between Enable (Port) and Clock.

Nibble Ripple Counter

INPUTS

INPUTS

INPUTS

LOAD
ENABLE P
ENABLET
LOAD PO P1 P2 P3

LOAD

'- ENABLEP

CLOCK

ENABLET

RESET

I

QO 01 02 Q3

I

I I I I
OUTPUTS

MOTOROLA

LOAD

'- ENABLEP
RIPPLE
CARRY
OUT

CLOCK
R

PO P1 P2 P3

l

-

RIPPLE
CARRY
OUT

ENABLET
CLOCK
R

I

l

'---

ENABLEP
ENABLET

R

I

I

OUTPUTS

3-198

RIPPLE
CARRY
OUT

TO
MORE
f--,SIGNIFICANT
STAGES

CLOCK

0001 02 03

I I I I

PO P1 P2 P3

0001 02 03

I

I I I I
OUTPUTS

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC160 MC54/74HC162
TYPICAL APPLICATION
HC162
OTHER
INPUTS

QO
Ql

OPTIONAL BUFFER
FOR NOISE REJECTION
OUTPUT

Modulo-5 Counter

The HC162 facilitates designing counters of any modulus with minimal external logic. The output is glitch-free due to the
synchronous Reset.

High-Speed CMOS Logic Data

DL129-Rev6

3-199

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC161A
MC54/74HC163A

Presettable Counters
High-Performance Silicon-Gate CMOS
The MC54174HC161A and HCI63A are identical in pinout to the LS161
and LS163. The device inputs are compatible with standard CMOS outputs;
with puliup resistors, they are compatible with LSTTL outputs.
The HC161A and HC163A are programmable 4-bit binary counters with
asynchronous and synchronous reset, respectively.
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard

•

Chip Complexity: 192 FETs or 48 Equivalent Gates

J SUFFIX
.CERAMIC PACKAGE
CASE 620-10

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

NO.7A

16#

DSUFFIX
SOIC PACKAGE
CASE 751B-05

LOGIC DIAGRAM
ORDERING INFORMATION
PO
PRESET
DATA
INPUTS

1

3

14

PI 4

13

5

12

6

11

2

15

P2
P3

CLOCK

~~
Q2

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
} BCDOR
BINARY
OUTPUT

PIN ASSIGNMENT

Q3
RIPPLE
CARRY
OUT

RESET [ 1-

16 PvCC
15 ~ RIPPLE
~ CARRY OUT
14 QO

CLOCK [ 2
PO [ 3

RESET
LOAD

1

pj( 4

13

~

9

P2 [ 5

12

~ Q2

7
COUNT { ENABLEP
ENABLES
ENABLET 10

Device

Count
Mode

Ceramic
Plastic
SOIC

PIN 16= VCC
PIN 8= GND

Binary

Asynchronous

HC163A

Binary

Synchronous

P3 [ 6

11

Q3

ENABLE P [ 7

10

ENABLET

GND [ 8

LOAD

FUNCTION TABLE

Reset Mode

HC161A

~
~
9~

Ql

Inputs
Clock

Reset'

Load

...r
...r
...r
...r
...r

L
H
H
H
H

X
L
H
H
H

Output

Enable P EnableT
X
X
H
L

X
X
H
X
L

X

Q

Reset
Load Preset Data
Count
No Count
No Count

• HC163A only. HC161 A is an Asynchronous Reset Device
H = high level
L= low level
X = don't care

10195

© Motorola, Inc. 1995

3-200

REV 6

®

ItIIOTOROLA

MC54174HC161A MC54174HC163A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65to+150

°c

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time (Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25°C

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
1I0uti s 20llA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
Iioutl s 20 IlA

2.0
4.5
6.0

0.50
1.35
1.80

0.50
1.35
1.80

0.50
1.35
1.80

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
1I0uti s 20llA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

V

Vin = VIH or VIL
1I0uti s 20llA

2.0
4.5
6.0

0.10
0.10
0.10

0.10
0.10
0.10

0.10
0.10
0.10

V

Yin = VIH or VIL 1I0uti s 4.0 rnA
lIoutl s 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

V

VOH

Parameter

VCC
V

Yin = VIH or VIL
VOL

lin
ICC

Maximum Low-Level Output
Voltage

1I0uti s 4.0 rnA
1I0uti s 5.2 rnA

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = !!A

6.0

4

40

160

IlA

o

NOTE: Information on tYPical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-201

MOTOROLA

MC54174HC161A MC54/74HC163A
AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6.0 ns)
Guaranteed Limit
Symbol

Parameter

Fig.

Vee
V

-55to
25°e

s

85°e

s

125°e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)"

1,7

2.0
4.5
6.0

6
30
35

5
24
28

4
20
24

MHz

tpLH

Maximum Propagation Delay, Clock to Q

1,7

2.0
4.5
6.0

120
20
16

160
23
20

200
28
22

ns

1,7

2.0
4.5
6.0

145
22
18

185
25
20

320
30
23

ns

tPHL

tPHL

Maximum Propagation Delay, Reset to Q (HC161A Only)

2, 7

2.0
4.5
6.0

145
20
17

185
22
19

220
25
21

ns

tpLH

Maximum Propagation Delay, Enable T to Ripple Carry Out

3, 7

2.0
4.5
6.0

110
16
14

150
18
15

190
20
17

ns

3, 7

2.0
4.5
6.0

135
18
15

175
20
16

210
22
20

ns

1,7

2.0
4.5
6.0

120
22
18·

160
27
22

200
30
25

ns

1,7

2.0
4.5
6.0

145
22
20

185
28
24

220

ns

tPHL

tpLH

Maximum Propagation Delay, Clock to Ripple Carry Out

tpHL

35
28

tpHL

Maximum Propagation Delay, Reset to Ripple Carry Out
(HC161AOnly)

2, 7

2.0
4.5
6.0

155
22
18

190
26
22

230
30
25

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output

2, 7

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

1,7

-

10

10

10

pF

Cin

" Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine f max • However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the f max in the table above is applicable. See
Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Gate)"

=5.0 V

30

"Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-202

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC161A MC54174HC163A
TIMING REQUIREMENTS (Cl =50 pF, Input tr =tf = 6.0 ns)
Guaranteed limit

Vee
Fig.

V

-55to
25°e

tsu

Minimum Setup Time,
Preset Data Inputs to Clock

5

2.0
4.5
6.0

40
15
12

60
20
18

80
30
20

ns

tsu

Minimum Setup Time,
load to Clock

5

2.0
4.5
6.0

60
15
12

75
20
18

90
30
20

ns

tsu

Minimum Setup Time,
Reset to Clock (HC163A Only)

4

2.0
4.5
6.0

60
20
17

75
25
23

90
35
25

ns

tsu

Minimum Setup Time,
Enable T or Enable P to Clock

6

2.0
4.5
6.0

80
20
17

95
25
23

110
35
25

ns

5

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

Symbol

th

Parameter

. Minimum Hold Time,
Clock to load or Preset Data Inputs

s

85°e

s

125°e

Unit

th

Minimum Hold Time,
Clock to Reset (HC163A Only)

4

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

th

Minimum Hold Time,
Clock to Enable T or Enable P

6

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

trec

Minimum Recovery Time,
Reset Inactive to Clock (HC161A Only)

2

2.0
4.5
6.0

80
15
12

95
20
17

110
26
23

ns

trec

Minimum Recovery Time,
load I nactive to Clock

5

2.0
4.5
6.0

80
15
12

95
20
17

110
26
23

ns

tw

Minimum Pulse Width,
Clock

1

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

tw

Minimum Pulse Width,
Reset (HC161 A Only)

2

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

tr,tf

Maximum Input Rise and Fall Times

High-Speed CMOS logic Data
DL129-Rev6

3-203

MOTOROLA

MC54/74HC161A MC54/74HC163A
FUNCTION DESCRIPTION
The HC161A1163A are programmable 4-bit synchronous
counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading and countenable controls.
The HC161 A and HC163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.

CONTROL FUNCTIONS
Resetting
A low level on the Reset pin (Pin 1) resets the internal flipflops and sets the outputs (00 through 03) to a low level.
The HC161 A resets asynchronously, and the HC163A resets
with the riSing edge of the Clock input (synchronous reset).

INPUTS

Loading

Clock (Pin 2)

With the rising edge of the Clock, a low level on Load (Pin
9) loads the data from the Preset Data input pins (PO, P1, P2,
P3) into the internal flip-flops and onto the output pins, 00
through 03. The count function is disabled as long as Load is
low.

The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition,
control functions, such as resetting and loading occur with
the rising edge of the Clock input.

Count EnablelDisable
These devices have two count-enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:

Preset Data Inputs PO, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. PO (Pin 3)
is the least-significant bit and P3 (Pin 6) is the most-significant bit.

Count Enable

=Enable P • Enable T • Load

The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a countenable control: Enable T is both a count-enable and a
Ripple-Carry Output control.

OUTPUTS
00,01,02,03 (Pins 14,13,12,11)

Table 1. Count Enable/Disable

These are the counter outputs. 00 (Pin 14) is the leastsignificant bit and 03 (Pin 11) is the most-significant bit.

Result at Outputs

Control Inputs

Ripple Carry Out (Pin 15)
When the counter is in its maximum state 1111, this output
goes high, providing an external look-ahead carry pulse that
may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count
state. The logic equation for this output is:
Ripple Carry Out =Enable T • 00 • 01 • 02 • 03

Load

EnableP

EnableT

QO-Q3

Ripple Carry Out

H

H

H

Count

L

H

H

No Count

High when Oo-Q3
are maximum"

X

L

H

No Count

High when Oo-Q3
are maximum"

X

X

L

No Count

L

"aD through 03 are maximum when 03 02 0100 =1111.

OUTPUT STATE DIAGRAMS

Binary Counters

MOTOROLA

3-204

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC161A MC54/74HC163A
SWITCHING WAVEFORMS
,----VCC
CLOCK

RESET

-GND

ANY
OUTPUT

F--

ANY
OUTPUT
CLOCK

50%

_ _ _ _ _ _ _ _---J.

Figure 2.

Figure 1.

-VCC

ENABLET

VCC
-GND

RESET

1<-----GND

tsu

tPLH
RIPPLE
CARRY
OUT --....:.::.:::.:.r

------VCC
CLOCK
-GND

trHL

Figure 3.

INPUTS
PO, P1,
P2, P3

Figure 4. HC163A Only

~------VCC

'--------GND

~------VCC

ENABLET
OR
ENABLE P

LOAD

~

VALlD~ VCC

50%

GND

tsuy;th
VCC

CLOCK

CLOCK
-------'

Figure 5.

-----VCC
50%
-GND

Figure 6.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 7.

High-Speed CMOS Logic Data
DL129-Rev6

3-205

MOTOROLA

~
s:

s:

a

b
:0
a

OOb

S;;

()
01

d

~
.j::>.

I

()
PO

......

3

0>

»
s:
()
01

~

:!!

Ul

c:

iil

.j::>.

PI

I

4

()

!l"

t

0>
W

01

»

;:;:

01

:;'

'"

3i:~

0
0
010

~

o

m

~§
-1>0-

P2

::x:~

~ §.
cn_

..... :::T

Q3P

»»

,I I

~

-(I)

'3o

o~

P3

::::I

o

15

c:

~

~~~~~
OUT

(I)

ENABLE P

(I)

~

Vcc

"")

I

cO'

~

"0

'"'c."

(")

RES",:-:=
LOAD 9

oS:

~g

lOr-

I ~.

:0"
co 0
< OJ

mor

CLOCK

~

LD1t="

LOAD
LOAD

[>----c

C

=PIN 16
, GND = PIN 8

The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A ToggleEnable flip-flop is a combination of a 0 flip-flop and a T flip-flop. When loading data from
Preset inputs PO, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal ciock (C) high and resets the Q
output of the flip-flop low.

MC54n4HC161A MC54/74HC163A
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.
RESET(HC161A) ----,Ur~-:::-::-:::77:==:---------------­
(ASYNCHRONOUS)
RESET (HC163A) - - - - , ! 1 . - - : : : - : = = = : : : : - - - - - - - - - - - - - - L.lJ
(SYNCHRONOUS)
LOAD---~U

pO-------r-------------------------------------------PRESET
DATA
INPUTS

Pl-------r-------------------------------------------P2.J
P3 .J

CLOCK (HC161A) - - - h
CLOCK (HC163A)

COUNT {ENABLE P
ENABLES

ENABLE T _ _ _-L-_+_'

Figure 9. Timing Diagram

High-Speed CMOS Logic Data
DL129- Rev 6

3-207

MOTOROLA

~
s::

s:

~

()

~

OOD

!;

01

4

~I
()

PO

3

....L

m
....L

»
s:
()
01

~

!!

U2

.j:>..

C

a;

...p

I

P1 4

()

......

m
w

t

»

::;:

!!!

:::I
-III

~~

(/10

'f

'"g

!1g
-"":::I

P2

5

::E:-

O~

~
W_

:5.

»:::T

Q3P

-en

,I I

cj

~
n

:::T

a
:::I

P3

6
15 RIPPLE
CARRY
OUT

oC

UJ

::D

i

ENABLE P 7

VCC = PIN 16
,GND=PIN8

)0
:J:

.0.

~
[

o

oS::

~~

cor

I ~.

jJt"l

~ 1,?

",or

:~
£Tt=~
2{:>

LOAD

CLOCK

LOAD

t [>--cC

The flip-flops shown in the circuit diagrams are Toggle-Enable f1ip~flops. A ToggleEnable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from
Preset inputs PO, Pt, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (e) high and resets the Q
output of the flip-flop low.

MC54/74HC161A MC54/74HC163A
TYPICAL APPLICATIONS CASCADING

LOAD------1---------------------~--------------------~--------------.

--INPUTS

H=COUNT
L= DISABLE

ENABLE P

H=COUNT
L= DISABLE

ENABLE P

ENABLE P
RIPPLE
CARRY
OUT

ENABLET

RIPPLE
CARRY
OUT

ENABLET
CLOCK

CLOCK

RESET

TO
MORE
SIGNIFICANT
STAGES

RIPPLE
CARRY
OUT

ENABLET
CLOCK

.

.

OUTPUTS

OUTPUTS

OUTPUTS

CLOCK
NOTE: When used in these cascaded configurations the clock f max guaranteed limits may not apply. Actual performance will depend on
number of stages. This limitation is due to set up times between Enable (Port) and Clock.

Figure 11. N-Bit Synchronous Counters

INPUTS

INPUTS

INPUTS

LOAD
ENABLE P
ENABLET
LOAD PO P1 P2 P3

LOAD

.... ENABLE P

CLOCK

ENABLET

RESET

J

LOAD

.... ENABLE P
RIPPLE
CARRY
OUT

CLOCK
R

PO P1 P2 P3

0001 0203

I

I I I I
OUTPUTS

n

-

RIPPLE
CARRY
OUT

ENABLET
CLOCK
R

T

n

0001 0203

I I I I
OUTPUTS

PO P1

P2 P3

ENABLEP

' - - ENABLET

RIPPLE
CARRY
OUT

CLOCK
R

T

-

TO
MORE
SIGNIFICANT
STAGES

0001 02 03

I

I I I I
OUTPUTS

Figure 12. Nibble Ripple Counter

High-Speed CMOS Logic Data
DL129-Rev6

3-209

MOTOROLA

MC54174HC161A MC54174HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS

HC163A
OTHER
INPUTS

HC163A
00
01

OTHER
INPUTS

OPTIONAL BUFFER
FOR NOISE REJECTION

00
01
02

OUTPUT

03
RESET

Figure 13. Modul0-5 Counter

Figure 14. Modulo-ll Counter

The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch-free due to the
synchronous Reset.

MOTOROLA

3-210

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Presettable Counters
High-Performance Silicon-Gate CMOS

MC54/74HCT161A
MC54/74HCT163A

The MC54174HCT161 A and HCT163A are identical in pinout to the LS161 A
and LS163A. These devices may be used as level converters for interfacing
TTL or NMOS outputs to high speed CMOS inputs.

J SUFFIX
CERAMIC PACKAGE
CASE 620-10

The HCT161 A and HCT163A are programmable 4-bit binary counters with
asynchronous and synchronous reset, respectively.
• Output Drive Capability: 10 LSTTL Loads
• TTL, NMOS Compatible Input Levels

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1 ~A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A

16#

DSUFFIX
SOIC PACKAGE
CASE 7518-05

1

• Chip Complexity: 200 FETs or 50 Equivalent Gates
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD

LOGIC DIAGRAM

Preset
Data
Inputs

[~
PI

14
t3

4

12

P2
P3

6

11

15

Clock

~]

at
a2

BCD or Binary
Outputs

a3
Ripple
Carry Out

Device

Count Mode

Reset Mode

HCT161A
HCT163A

Binary
Binary

Asynchronous
Synchronous

Pinout: 16-Lead Package (Top View)

Reset
Pin 16= VCC
Pin8=GND

Load

Ceramic
Plastic
SOIC

VCC RCO'

QO

Ql

~

Reset Clock

Po

PI

P2

Oa

Enable
T Load

Count [ Enable P
Enables
Enable T 10

FUNCTION TABLE
Inputs
Clock

Reset·

Load

Enable P

EnableT

Output
Q

..r
..r
..r
..r
..r

L
H
H
H
H

X
L
H
H
H

X
X
H
L
X

X
X
H
X
L

Reset
Load Preset Data
Count
No Count
No Count

• RCO = Ripple Carry Out

Enable GND

P

H = High Level; L = Low Level; X = Don't Care
• = HCT163A only. HCT161A is an "Asynchronous-Reset" device.

10195

© Motorola, Inc. 1995

3-211

REV2

®

MOTOROLA

MC54/74HCT161 A MC54/74HCT163A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
Positive DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+150

°c

lin
lout

Tstg
TL

Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
Ceramic DIP

This device contains protection
. circuitry to guard against damage
due to high static voltages or electriC
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW,oCfrom 65° to 125°C
Ceramic DIP: - 10 mW'oC from 100° to 125°C
SOIC Package: -7 mW'oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

4.5

5.5

V

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

0

VCC

V

-55

+ 125

°C

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
Guaranteed Limit

VCC
Symbol

Test Conditions

V

-55to 25°C

VIH

Minimum High-Level Input
Voltage

Vout=O.1 V orVcc=-1.0V
lIoutl s 20 itA

4.5
5.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 V
lIoutl s 20 itA

4.5
5.5

0.80
0.80

0.80
0.80

0.80
0.80

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl S 20 itA

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

Vin = VIH or VIL
lIoutl s 4.0 rnA

4.5

3.98

3.84

3.70

V

Vin = VIH or VIL
lIoutl s 20 itA

4.5
5.5

0.10
0.10

0.10
0.10

0.10
0.10

V

Vin = VIH or VIL
lIoutl s 4.0 rnA

4.5

0.26

0.33

0.40

V

Maximum Input Leakage Current

Vin = Vec or GND

5.5

±0.10

±1.00

± 1.00

itA

ICC

Maximum Quiescent Supply
Current (Per Package)

Vin = Vec or GND
lout-O itA

5.5

4

40

160

ItA

ICC

Additional Quiescent Supply
Current

Vin=2.4V,
Any One Input
VIN = Vec or GND
Other Inputs lout - 0 itA

VOH

VOL

lin

Parameter

Maximum Low-Level Output
Voltage

5.5

$

85°C

$

125'C

~5'C

25to +125°C

2.9

2.4

Unit

rnA

NOTE: Information on typical parametric values can be found In Chapter 2.

MOTOROLA

3-212

High-Speed CMOS LogiC Data
DL129-Rev6

MC54/74HCT161A MC54/74HCT163A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±1 0%: CL = 50 pF, Input tr = tl = 6.0 ns)
Guaranteed Limit
Symbol

Parameter

Fig

- 55 to 25'e

';;85'e

';;125'e

Unit

24

20

MHz

Imax

Maximum Clock Frequency (50% Duty Cycle)"

1,7

30

tpLH

Maximum Propagation Delay Clock to Q

1,7

20

23

28

ns

1,7

25

30

32

ns
ns

tpHL
tpHL

Maximum Propagation Delay Reset to Q (HCT161 A Only)

2,7

25

29

33

tpLH

Maximum Propagation Delay Enable T to Ripple Carry Out

3,7

16

18

20

ns

3,7

21

24

28

ns

1,7

22

25

28

ns

1,7

28

33

35

ns

tpHL
tpLH

Maximum Propagation Delay Clock to Ripple Carry Out

tpHL
tpHL

Maximum Propagation Delay Reset to Ripple Carry Out
(HCT161 A Only)

2,7

24

28

32

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output

2,7

15

19

22

ns

Maximum Input Capacitance

1,7

10

10

10

pF

Cin

" Applies to noncascaded/nonsynchronous clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine Imax. However,
if Ripple Carry Out 01 each stage is tied to the Clock 01 the next stage (nonsynchronously clocked), the Imax in the table above is applicable. See
Applications inlormation in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and inlormation on typical parametric values, see Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per Gater

=5.0 V

60

"Used to determine the no-load dynamic power consumption: Po = CPO VCC 21 + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (VCC = 5.0 V ±10%: CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Fig.

-55to
25'e

';;S5'e

';;125'e

Unit

Minimum Setup Time, Preset Data Inputs to Clock

5

12

18

20

ns

Minimum Setup Time, Load to Clock

5

12

18

20

ns

4

12

18

20

ns

Minimum Setup Time, Enable T or Enable P to Clock

6

12

18

20

ns

Minimum Hold TIme, Clock to Preset Data Inputs

5

3

3

3

ns

Minimum Hold TIme, Clock to Load

5

3

3

3

ns

4

3

3

3

ns

6

3

3

3

ns

2

12

17

23

ns

2

12

17

23

ns

1

12

15

18

ns

1

12

15

18

ns

500

500

500

ns

Symbol
tsu

Parameter

Minimum Setup Time, Reset to Clock

th

Minimum Hold TIme, Clock to Reset

(HCT163A Only)

(HCT163A Only)

Minimum Hold TIme, Clock to En T or En P
trec

Minimum Recovery Time, Reset Inactive to Clock

(HCT161 A Only)

Minimum Recovery TIme, Load Inactive to Clock
tw

Minimum Pulse Width, Clock
Minimum Pulse Width, Reset

tr,tl

(HCT161 A Only)

Maximum Input Rise and Fall TImes

High-Speed CMOS Logic Data
DL129 - Rev 6

3-213

MOTOROLA

MC54/74HCT161 A MC54n4HCT163A
FUNCTION DESCRIPTION
The HCT161 A1163A are programmable 4-bit synchronous
counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading and count-enable
controls.
The HCT161 A and HCT163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.

CONTROL FUNCTIONS
Resetting
A low level on the Reset pin (pin 1) resets the internal flipflops and sets the outputs (00 through 03) to a low level. The
HCT161 A resets asynchronously, and the HCT163A resets
with the rising edge of the Clock input (synchronous reset).
Loading

INPUTS
Clock (Pin 2)
The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting and loading occur with the
rising edge of the Clock input. In addition, control functions,
such as resetting (HCT163A) and loading occur with the rising
~dge of the Clock Input.

With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data input pins (PO, P1, P2,
P3) into the internal flip-flops and onto the output pins, 00
through 03. The count function is disabled as long as Load is
low.
Count Enable/Disable
These devices have two count-enable control pins: Enable
P (Pin 7) and Enable T (Pin 10). The devices count when these
two pins and the Load pin are high. The logic equation is:

Preset Data Inputs PO, P1, P2, P3 (Pins 3, 4, 5, 6)

Count Enable

These are the data inputs for programmable counting. Data
on these pins may be synchronously loaded into the internal
flip-flops and appear at the counter outputs. PO (Pin 3) is the
least-significant bit and P3 (Pin 6) is the most-significant bit.
OUTPUTS

Table 1. Count Enable/Disable

QO, Q1, Q2, Q3 (Pins 14, 13, 12, 11)

Control Inputs

These are the counter outputs. 00 (Pin 14) is the least-significant bit and 03 (Pin 11) is the most-significant bit.

Load

Ripple Carry Out (Pin 15)
When the counter is in its maximum state 1111 , this output
goes high, providing an external look-ahead carry pulse that
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count state.
The logic equation for this output is:
Ripple Carry Out

=Enable T • 00 • 01

=Enable P • Enable T • Load

The count is either enabled or disabled by the control inputs
according to Table 1. In general, Enable P is a count-enable
control: Enable T is both a count-enable and a Ripple-Carry
OutpCJt control.

• 02 • 03

Result at Outputs

Enable Enable
P
T

QO--Q3

Ripple Carry Out
High when 00-03

H

H

H

Count

L

H

H

No Count

are maximum"

X

L

H

No Count

High when 00-03
are maximum"

X

X

L

No Count

L

00 through 03 are maximum when 03 02 01 00

=1111.

OUTPUT STATE DIAGRAM

Binary Counters

MOTOROLA

3-214

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HCT161 A MC54/74HCT163A
SWITCHING WAVEFORMS

~---3.0V

3.0V
Clock

Reset

'-------'4-- - - - - GND
tPHL
Any
Output

Any
Output

!r-3.0V
Clock

1.3Vf

_ _ _ _ _ _ _ _ _.......J.C..-

Figure 1.

-

-

GND

Figure 2.

,.---3.0V
Enable T

Reset

1.3V

I t . - - - - - GND

' - - - - - - - - 4 - - - - GND

~
1.3V

tsu
Ripple
Carry Out

Clock

_ _ _ _ _..L-

th

3.0V

- - - - - - - __

GND

tTHL

Figure 3.

Figure 4. HCT163A Only

,.-------3.0V

Inputs PO,
P1, P2, P3

' - - - - - - - - GND

Enable T
pr
Enable P

r - - - - - - - 3.0V
Load

~

valid~ 3.0V

1.3V

tsu

-1;= th

GND
3.0V

J....l- 1.1.3~ _ _ _ _ _ _ GND

Clock _ _ _ _ _ _ _
Clock

Figure 5.

Figure 6.

TEST
POINT
OUTPUT
DEVICE
UNDER
TEST

'Includes all probe and jig capacitance

Figure 7. Test Circuit

High-Speed CMOS Logic Data
DL129-Rev6

3--215

MOTOROLA

MC54174HCT161 A MC54174HCT163A
14 00

Po 3

11 03

15 Ripple
Carry Out

Enable P
EnableT

:~>-----b!;~

L----Load

Clock

~----~THI>- ~
C

The flip-flops shown in the circuit diagrams are ToggleEnable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data
from Preset inputs PO, P1, P2 and P3, the Load signal is
used to disable the Toggle input (Tn) of the flip-flop. The
logic level at the Pn input is then clocked to the Q output of
the flip-flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal
clock (C) high and resets the Q output of the flip-flop low.

Figure 8. 4-Bit Binary Counter with Asynchronous Reset (MC54174HCT161 A)

MOTOROLA

3-216

High-Speed CMOS Logic Data
DL129- Rev 6

MC54/74HCT161 A MC54174HCT163A

U (Asynchronous)

Reset(HCT161 A)

LWI~-------------------------------------lu
I

Reset (HCT163A)

(Synchronous)

Load

I

PO ______~I---------------------------------------------Preset
Data
Inputs

I
I

P1
P2

--.J

P3

--.J

Clock (HCT161A)
Clock (HCT163A)

II

Count [Enable P
Enables

II

I
II
Enable T -------r--_+'
I
I
00
I
I
I
01
I
I
Outputs

I
I
I
I
02
I
I
I
I
I
03
I
I
I
I
Ripple Carry Out ______- LI__.......I...,..,-...J...,.,......-,-~
I
I
14
15
0
112
I
1 13
Count
II
I

U

~

I
I

n

t t

Reset

I
I
I
I
I

[3J

Ii
I
I
I
I
I
I
I
21

-I-

Inhibit

-

Load

Figure 9. Timing Diagram

High-Speed CMOS Logic Data
DL129-Rev6

3-217

MOTOROLA

MC54174HCT161 A MC54174HCT163A

Po 3

12

------4Tt-[>o- ~

The flip-flops shown in the circuit diagrams are ToggleEnable flip-flops. A Toggle-Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data
from Preset inputs PO, PI, P2 and P3, the Load signal is
used to disable the Toggle input (Tn) of the flip-flop. The
logic level at the Pn input is then clocked to the Q output of
the flip-flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal
clock (C) high and resets the Q output of the flip-flop low.

Figure 10. 4-Bit Binary Counter with Synchronous Reset (MC54174HCT163A)

MOTOROLA

3-218

High-Speed CMOS Logic Data
DL129- Rev 6

MC54/74HCT161A MC54/74HCT163A
TYPICAL APPLICATIONS CASCADING
Load

'I I I I'
Load
H=Count
L=Disabte
H=Count
L=Disable

-.-

Enable P

-

Enable T

'I I I I'
Load

00 010203

-

Ripp,e
Carry
Ou,

'I I I I'
Load

00010203
Ripple
Carry
Out

Enable T

I> Clock

r->C,ock

Reset

00 010203

Rese,

00 010203

Reset

:t

IIII

:t

IIII

:t

,I I I I,

,I I I I,
Outputs

Ou'puts

Clock

00 0 10203

' - - Enable P

Enable P
Enable T

r-~Clock

Reset

Inputs

Inputs

Inputs

Ripple
Carry
Out

To More

r---- Signilicant
Stages

00 0 10 203

IIII

,I I I I,
Outputs

NOTE: When used in these cascaded configurations the clock f max guaranteed limits may not app'y. Actuat performance will
depend on number of stages. This limitation is due to set-up times between Enable (port) and clock.

Figure 11. N-Bit Synchronous Counters

Inputs

Inputs
.----.

r--r

Inputs
.----.

Load
Enable P
Enable T

Load

Clock

Reset

Load

00 010203

Enable T

Load

00010203

""- Enable P

Enable P
Ripple
Carry
Out

Clock

l

I-

Ripple
Carry
Out

' - - Enable T

Clock

Reset

00010203

Reset

:t

,,,,

:t

l

~

00010203

Enable P
EnableT

Ripple
Carry
Out

To More

r---- Significant
Stages

Clock

00010203

Reset

,,,,

:t

00 010203

,,,,

~

~

~

Outputs

Outputs

Outputs

Figure 12. Nibble Ripple Counter

High-Speed CMOS Logic Data
DL129- RevS

3-219

MOTOROLA

· MC54/74HCT16~ A MC54/74HCT163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HCT163A
Other
Inputs

HCT163A

QO
Q1

Other
Inputs

Optional Buffer
for Noise. Rejection
Output

Reset

Figure 13. Modul0-5 Counter

Figure 14. Modulo-11 Counter

The HCT163A facilitates designing counters of any modulus with minimal external logic. The output is glitchfree due to the synchronous Reset.
.

MOTOROLA

3-220

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

8-Bit Serial-Input/
Parallel-Output Shift Register
High-Performance Silicon-Gate CMOS
The MC54/74HC164 is identical in pinout to the LS164. The device inputs
are compatible with standard CMOS outputs; with pull up resistors, they are
compatible with LSTTL outputs.
The MC54/74HC164 is an a-bit, serial-input to parallel-output shift
register. Two serial data inputs, A 1 and A2, are provided so that one input
may be used as a data enable. Data is entered on each rising edge of the
clock. The active-low asynchronous Reset overrides the Clock and Serial
Data inputs.

MC54/74HC164
Da Nat Use far New Designs
THIS DEVICE WILL BE SUPERCEDED
BY MC54/74HC164A IN THE
SECOND QUARTER OF 1996

J SUFFIX
CERAMIC PACKAGE
CASE 632-08

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 IlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A--03

ORDERING INFORMATION

LOGIC DIAGRAM

SERIAL{A1 1
DATA
INPUTS A2

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
QA

DATA
4

5

QB

PIN ASSIGNMENT

QC
QD

10 QE

PARALLEL
DATA
OUTPUTS

11 QF

CLOCK 8

RESET-9
"--------'

Ceramic
Plastic
SOIC

~ VCC

Ad 1·

14

A2 [ 2

13

~ QH

QA[ 3

12

PQG

12 QG

QB [ 4

11

~ QF

13 QH

QC [ 5

10

~ QE

QD [ 6

9

~

GND [ 7

8

PCLOCK

RESET

PIN 14= VCC
PIN 7 =GND

FUNCTION TABLE
Inputs
Reset Clock
L
H
H
H

X

\...
J
J

Outputs

A1

A2 QA QS

X
X
H
D

X
X
D
H

... QH

L
... L
No Change
D QAn ... QGn
D QAn ... QGn
L

D = data input
QAn - QGn data shifted from the preceding
stage on a rising edge at the clock input.

=

10195

© Motorola, Inc. 1995

3-221

REV7

®

MOTOROLA

MC54174HC164
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

- 0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+150

°c

lin

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :s (Vin orVout) :s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., e~her GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbot
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+125

°C

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.OV
VCC=4.5V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

Vce
V

-55to
25°e

:s 85°C

:s

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
"outl :s 20 I1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
"outl :s 20 I1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
"outl :s 20 I1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Yin = VIH or VIL "outl
"outl
VOL

Maximum Low-Level Output
Voltage

lin

4.0 mA
5.2 mA

Yin = VIH or VIL
"outl :s 20 I1A
Yin = VIH or VIL "outl
"outl

ICC

:s
:s

:s 4.0 mA
:s 5.2 mA

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

± 1.0

±1.0

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 I1A

6.0

8

80

160

V

I1A
I1A

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-222

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC164
AC ELECTRICAL CHARACTERISTICS (CL

=50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

:s 85°e

:s 125°e

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpHL

Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)

2.0
4.5
6.0

205
41
35

255
51
43

310
62
53

ns

tTLH,
trHL

Maximum Output Transition lime, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

140

'Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.
TIMING REQUIREMENTS (Input tr = tf

=6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

:s 85°e

:s 125°e

Unit

tsu

Minimum Setup lime, Al or A2 to Clock
(Figure 3)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

th

Minimum Hold Time, Clock to A 1 or A2
(Figure 3)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and FaU Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

trec

tr,tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-223

MOTOROLA

MC54/74HC 164
PIN DESCRIPTIONS
register is completely static, allowing clock rates down to DC
in a continuous or intermittent mode.

INPUTS
A1, A2 (Pins 1, 2)

OUTPUTS

Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A 1 and A2
inputs must be high, thereby allowing one input to be used as
a data-enable input. When only one serial input is used, the
other must be connected to VCC.

QA - QH (Pins 3,4,5,6,10,11,12,13)
Parallel Shift Register Outputs. The shifted data is presented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)

Clock (Pin 8)

Active-Low, Asynchronous Reset Input. A low voltage applied to this input resets all internal flip-flops and sets Outputs QA - QH to the low level state.

Shift Register Clock. A positive-going transition on this pin
shifts the data at each stage to the next stage. The shift

SWITCHING WAVEFORMS

~---VCC

RESET

CLOCK

-GND

Q
Q

I:=.-vcc
CLOCK _ _ _ _ _ _ _ _ _
50-J%!

_

GND

Figure 2.

Figure 1.

TEST POINT

Al0RA2

~
~
Isu

CLOCK

VALlDj=

OUTPUT
:::

t_th_____

-'50%

------'

DEVICE
UNDER
TEST

VCC

- - GND

• Includes all probe and jig capacitance

Figure 3.

MOTOROLA

Figure 4. Test Circuit

3-224

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC 164
EXPANDED LOGIC DIAGRAM

CLOCK

A1

A2

RESET

TIMING DIAGRAM

CLOCK
A1 - - - , . - - - ,

A2----,
RESET~
QA~~_ _ _~r---l~
QB~

QC~
QD~

QE~

____________

__________
r---l~.___________
r---l~________
r---l~____________

r---l~

_________
r---l~_____
r---l~_ __

QF~

r---l~

QG~

QH~

High-Speed CMOS Logic Data
DL129-Rev6

3-225

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

a-Bit Serial-Input!
Parallel-Output Shift Register

MC54!74HC164A

High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 632-Q8

The MC54174HC164A is identical in pinout to the LS164. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTIL outputs.
The MC54174HC164A is an a-bit, serial-input to parallel-output shift
register. Two serial data inputs, A 1 and A2, are provided so that one input
may be used as a data enable. Data is entered on each rising edge of the
clock. The active-low asynchronous Reset overrides the Clock and Serial
Data inputs.

NSUFFIX
PLASTIC PACKAGE
CASE 646-06

• Output Drive Capability: 10 LSTIL Loads
• Outputs Directly Interface to CMOS, NMOS, and TIL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 J.tA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 244 FETs or 61 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-Q3

DTSUFFIX
TSSOP PACKAGE
CASE 948G-Ql

LOGIC DIAGRAM

ORDERING INFORMATION

3

SERIAL{A1
DATA
INPUTS A2

DATA

4

5

OA
Os

RESET 9

Ceramic
Plastic
SOIC
TSSOP

Oc

OD
10 0E

CLOCK 8

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

PARALLEL
DATA
OUTPUTS

PIN ASSIGNMENT

J VCC

11 OF

A1

1-

14

120G
13 0H

A2

2

13 QOH

OA

3

12 aOG

PIN 14 = VCC
PIN 7=GND

~ OF

Os [ 4

11

oc[

10 POE

5

OD [ 6

9 DRESET

GND [ 7

8 DCLOCK

FUNCTION TABLE
Inputs

Outputs

Reset Clock A1

L
H
H
H

X
"\..

J
J

X
X
H
D

A2 QA QB
X
X
D
H

...

QH

L ... L
No Change
D QAn ... QGn
D QAn ... QGn
L

D = data input
QAn - QGn = data shifted from the preceding
stage on a rising edge at the clock input.

3/96

© Motorola, Inc. 1996

3-226

REV 0

®

MOTOROI.A

MC54/7 4HC 164A
MAXIMUM RATINGS'
Symbol
VCC
Yin

Parameter

Value

Unit

-0.5to+7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

DC Supply Voltage (Relerenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA
mA

Vout

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

- 65 to + 150

°c

Tstg

TL

Storage Temperature
Lead Temperature, 1 mm froni Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitl)' to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,; (Vin or Vout) ,; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mWI"C from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

2.0

6.0

Unit
V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55°C to
25°C

,; 85°C

,; 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=0.1 VorVCC-0.1 V
1I0uti ,; 20 ~A

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=0.1 VorVCC-0.1 V
1I0uti ,; 20 ~A

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

Minimum High-Level butput
Voltage

Yin = VIH or VIL
1I0uti ,; 20 ~A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL 1I0uti ,; 2.4 mA
"outl ,; 4.0 mA
"outl ,; 5.2 mA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

VOH

High-Speed CMOS Logic Data
DL129- Rev 6

3-227

MOTOROLA

MC54/74HC164A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

lin

Vee
V

-55°e to
25°C

s 85°C

s 125°C

Unit

Vin =VIH or VIL
lIoutl S 20!,A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Vin =VIH or VIL lIoutl S 2.4 mA
lIoutl S 4.0 mA
lIoutl S 5.2 mA

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Vin =; VCC or GND

6.0

iO.l

il.0

il.0

!LA

6.0

4

40

160

!,A

Vee
V

-55°C to
25°C

Parameter

Test Conditions

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

Vin =VCC or GND
lout =o!LA
NOTE: Information on typical parametric values can be found In Chapter 2.
ICC

Maximum Quiescent Supply
Current (per Package)

AC ELECTRICAL CHARACTERISTICS (Cl =50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Symbol

Parameter

S

85"e

S

125"e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
3.0
4.5
6.0

10
20
40
50

10
20
35
45

10
20
30
40

MHz

tPlH,
tpHl

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

2.0
3.0
4.5
6.0

160
100
32
27

200
150
40
34

250
200
48
42

ns

tpHl

Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)

2.0
3.0
4.5
6.0

175
100
35
30

220
150
44
37

260
200
53
45

ns

ITlH,
tTHl

Maximum Output Transition TIme, Any Output
(Figures 1 and 4)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

-

10

10

10

pF

Maximum Input Capacitance
Cin
NOTES.
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.

Typical @ 25"e, Vee
Power Dissipation Capacitance (Per Package)"

=5.0 V

180

"Used to determine the no-load dynamic power consumption: PD = CpD VCC f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

-55°eto
25"e

S 85"e

S 125"e

Unit

tsu

Minimum Setup TIme, A 1 or A2 to Clock
(Figure 3)

2.0
3.0
4.5
6.0

25
15
7
5

35
20
8
6

40
25
9
6

ns

th

Minimum Hold TIme, Clock to A 1 or A2
(Figure 3)

2.0
3.0
4.5
6.0

3
3
3
3

3
3
3
3

3
3
3
3

ns

MOTOROLA

Parameter

Vee
V

3-228

High-Speed CMOS Logic Data
DL129-Rev6

MC54n 4HC164A
TIMING REQUIREMENTS (Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55'eto
25'e

s 85'e

s 125'e

Unit

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
3.0
4.5
6.0

3
3
3
3

3
3
3
3

3
3
3
3

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
3.0
4.5
6.0

50
26
12
10

60
35
15
12

75
45
20
15

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
3.0
4.5
6.0

50
26
12
10

60
35
15
12

75
45
20
15

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
3.0
4.5
6.0

1000
800
500
400

1000
800
500
400

1000
800
500
400

ns

Symbol
trec

t r, tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-229

MOTOROLA

MC54174HC164A
PIN DESCRIPTIONS
register is completely static, allowing clock rates:down to DC
in a continuous or intermittent mode.

INPUTS
A1, A2 (Pins 1, 2)

OUTPUTS

Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A 1 and A2.
inputs must be high, thereby allowing one input to be used as
a data-enable input. When only one serial input is used, the
other must be connected to VCC.

QA - QH (Pins 3,4,5,6,10,11,12,13)
Parallel Shift Register Outputs. The shifted data is pres, ented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)

Clock (Pin 8)
Shift Register Clock. A positive-going transition on this pin
shifts the data at each stage to the next stage. The shift

Active-Low, Asynchronous Reset Input. A low voltage applied to this input resets all internal flip-flops and sets Outputs QA - QH to the low level state.

SWITCHING WAVEFORMS

~---VCC

RESET

CLOCK

-GND

Q

Q

I:=..-vcc
CLOCK

50%;¥

_ _ _ _ _ _ _ _..J,

-GND

Figure 2.

Figure 1.

TEST POINT

Al0RA2

~
~

VALlD~

SUt

I
CLOCK

:::
lh

- ' 50%

_ _ _ _ _-1

OUTPUT
DEVICE
UNDER
TEST

VCC
-

GND
• Includes all probe and jig capacitance

Figure 4. Test Circuit

Figure 3.

MOTOROLA

3-230

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC 164A
EXPANDED LOGIC DIAGRAM

CLOCK

A1
A2

RESET

TIMING DIAGRAM

CLOCK
A1----A2---RESET~

__~__________
___________
r---l~_________________
r---l~_________
r---l~_____________
r---l~_______

QA~~_ _ _~r---l~

QS---.
QC---.

QD---.
QE - - - .

QF---.

r---l~

r---l~

QG---.

r---l~

QH - - - .

High-Speed CMOS Logic Data
DL129-Rev6

____

3-231

_ ___

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

a-Bit Serial or Parallel-Input!
Serial-Output Shift Register

MC54!74HC165

High-Performance Silicon-Gate CMOS
J SUFFIX
CERAMIC PACKAGE
CASE 62D-10

The MC54n4HC165 is identical in pinout to the LS165. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is an B-bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or iri serial
form. When the Serial ShifVParaliel Load input is low, the data is loaded
asynchronously in parallel. When the Serial ShifVParalielLoad input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
The 2-input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 64B-OB

DSUFFIX
SOIC PACKAGE
CASE 751 8-05

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

Ceramic
Plastic
SOIC

LOGIC DIAGRAM
A 11

PIN ASSIGNMENT

B 12

C 13
PARALLEL
DATA
INPUTS

9 QH

D 14

1---'- OH

1

SERIAL SHIFT!
PARALLEL LOAD
CLOCK

SERIAL
DATA
OUTPUTS

1-

16

VCC

2

15

CLOCK INHIBIT

E

3

14

D

F 4

F

4

13

C

G 5

G

12

B

H

11

A

10

SA

E 3

PIN 16= VCC
PIN 8 = GND

SERIAL{ H
DATA SA 10
INPUT

OH

7

GND [ 8

QH

SERIAL SHIFT/PARALLEL LOAD --'----'
CLOCK
CLOCK INHIBIT 15

Serial Shift!
Parallel Load
L
H
H

FUNCTION TABLE
Inputs
Clock
Inhibit
Clock
X

J
J

Internal Stages
A-H

Output
Operation

X

SA
X

a ... h

QA
a

Qe
b

QH
h

L
L

L
H

X
X

L
H

QAn
QAn

QGn
QGn

Serial Shift via Clock

L
H

QAn
QAn

QGn
QGn

Serial Shift via Clock Inhibit

Asynchronous Parallel Load

H
H

L
L

J
J

L
H

X
X

H
H

X
H

H
X

X
X

X
X

No Change

Inhibited Clock

H

L

L

X

X

No Change

No Clock

X = don't care
QAn - QGn =Data shifted from the preceding stage

10195

© Motorola, Inc. 1995

3-232

REV 6

®

MOTOROLA

MC54/74HC165
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

- 1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

rnA
rnA

lin

DC Input Current, per Pin

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65 to + 150

"C

Tstg

lL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

"C
260
300

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65" to 125"C
Ceramic DIP: -10 mW/"C from 100" to 125"C
SOIC Package: -7 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC = 2.0 V
VCC=4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

"C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

:5 85"C

:5 125"C

Unit

Minimum High-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
lIoutl:5 20~

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
lIoutl :5 20 ~

2.0
4.5
6.0

0.3
0.9
1.2

0.3
09
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl :5 20 !LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl :5 4.0 rnA
lIoutl :5 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

V

Vin = VIH or VIL
lIoutl :5 20 !LA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Vin = VIH or VIL lIoutl :5 4.0 rnA
lIoutl :5 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

~

Vin = VCC or GND
lout = O!1A

6.0

8

80

160

~

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

Test Conditions

-5510
25"C

VIH

VOH

Parameter

VCC
V

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-233

MOTOROLA

MC54/74HC165
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

-55to
25°e

s

s

125°e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
?4

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH
(Figures 1 and 8)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tPLH,
tpHL

Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH
(Figures 2 and 8)

2.0
4.5
6.0

175

265
53
45

ns

30

220
44
37

tPLH,
tPHL

Maximum Propagation Delay, Input H to QH or QH
(Figures 3 and 8)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

ITLH,
ITHL

Maximum Output Transition lime, Any Output
(Figures 1 and 8)

2.0
4.5·
6.0

75
15
13

95
19
16

110
22
19

ns

-

10

10

10

pF

Cin

Parameter

Vee
V

Maximum Input Capacitance

35

85°e

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vec = 5.0 V
Power Dissipation Capacitance (Per Package)"

85

"Used to determine the no-load dynamic power consumption: PD = CPD Vce2f + lee Vee. For load considerations, see Chapter 2.

MOTOROLA

3-234

High-Speed eMOS Logic Data.
DL129- Rev 6

MC54/74HC 165
TIMING REQUIREMENTS (Inpul Ir = If = 6 ns)
Guaranteed Limit
Symbol

-55to
25'e

s 85'e

s 125'e

Unit

tsu

Minimum Setup Time, Parallel Dala Inputs to Serial Shift/Parallel Load
(Figure 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tsu

Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
(Figure 5)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tsu

Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
(Figure 6)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tsu

Minimum Setup Time, Clock to Clock Inhibit
(Figure 7)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
(Figure 4)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

th

Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
(Figure 5)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

th

Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
(Figure 6)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

Minimum Recovery Time, Clock to Clock Inhibit
(Figure 7)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tw

Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse width, Serial Shift/Parallel Load
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

trec

tr,tf

Parameter

Vee
V

NOTE: Information on tYPical parametric values can be found In Chapter 2.

PIN DESCRIPTIONS
applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.

INPUTS

A,

e, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)

Parallel Data inputs. Data on these inputs are asynchronously entered in parallel into the internal flip-flops when the
Serial ShifVParallel Load input is low.

Clock, Clock Inhibit (Pins 2,15)

Serial Data input. When the Serial Shift/Parallel Load input
is high, data on this pin is serially entered into the first stage
of the shift register with the rising edge of the Clock.

Clock inputs. These two clock inputs function identically.
Either may be used as an active-high clock inhibit. However,
to avoid double clocking, the inhibit input should go high only
while the clock input is high.
The shift register is completely static, allowing Clock rates
down to DC in a continuous or intermittent mode.

CONTROL INPUTS

OUTPUTS

Serial Shift/Parallel Load (Pin 1)

QH, QH (Pins 9, 7)

Data-entry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level is

Complementary Shift Register outputs. These pins are the
non inverted and inverted outputs of the eighth stage of the
shift register.

SA (Pin 10)

High-Speed CMOS Logic Data
DL129-Rev6

3-235

MOTOROLA

MC54174HC165
SWITCHING WAVEFORMS

VCC

CLOCK
OR CLOCK INHIBIT

Figure 2. Parallel-Load Mode

Figure 1. Serial-Shift Mode

--~ r----~ r-----VCC
INPUTSA-H
_ _- J ' - - _ _- J ' - - - - GND

-VCC

INPUTH

Il"-----GND
,------VCC
SERIAL SHIFT!
PARALLEL LOAD

-

Figure 3. Parallel-Load Mode

INPUT SA

CLOCK
OR CLOCK INHIBIT

~
~

Figure 4. Parallel-Load Mode

VALlD~

SERIALSHIFTI - L J - = V C C
PARALLEL LOAD
50%
GND

:~:

tSUF,th
CLOCK
OR CLOCK INHIBIT _ _ _ _ _ _ _ _...J.

tSUj;th

-----VCC

______
...J

GND

ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)

trHL

50%

----------VCC

50%

-

GND

-GND

Figure 5. Serial-Shift Mode

Figure 6. Serial-Shift Mode

TEST POINT
OUTPUT

-VCC

DEVICE
UNDER
TEST

-------GND

CLOCK

• Includes all probe and jig capacitance

GND

Figure 7. Serial-Shift, Clock-Inhibit Mode

MOTOROLA

3-236

Figure 8. Test Circuit

High-Speed CMOS Logic Data
DL129-Rev6

MC54n4HC165
EXPANDED LOGIC DIAGRAM
A

B

C

SERIAL SHIFTI
PARALLEL LOAD
SERIAL DATA
INPUTSA

TIMING DIAGRAM

CLOCK
CLOCK INHIBIT

- - - - 1 ._ _ _ _ _ _ _ _ _ _ __

SA1~______
SERIALSHIFTI
PARALLEL LOAD

_+----------------------

-Ur---t-----------~

A~iHI~__~------------------~
B~
C

PARALLEL
DATA
INPUTS

--1!mL-...--+----------------------

D~

-lImL-...--T----------------------

E
F1

IL
I

G~~--r_--------------------

H~~-+------------------

QH

QH
CLOCK

I N H I B l r SERIAL-SHIFTMODE
MODE
PARALLEL LOAD

High-Speed CMOS Logic Data

DL129-Rev6

•

1--'

3-237

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview
a-Bit Serial or Parallel-Input!
Serial-Output Shift Register

MC54!74HC165A
JSUFFIX
CERAMIC PACKAGE
CASE 62D-10

High-Performance. Silicon-Gate CMOS
The MC54/74HC165A is identical in pinout to the LS165. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device is an 8-bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
The 2-input NOR clock may be used either by combining two independent
clock sources or by deSignating one of the clock inputs to act as a clock
inhibit.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 I-lA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

16'

DSUFFIX
SOIC PACKAGE
CASE 751 8-05

1

DTSUFFIX
TSSOP PACKAGE
CASE 948F-01

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Ceramic
Plas1ic
SOIC
TSSOP

LOGIC DIAGRAM

[3J

A 11
B 12
13

PARALLEL
DATA
INPUTS

9

C

D 14
E 3

PIN ASSIGNMENT

~} S~~
QH

SERIAL SHIFT! [
PARALLEL LOAD 1CLOCK 2

DATA
OUTPUTS

3

14

PD

F

4

13

~C

G

5

12

H

6

11

QH

7

lOp SA

GND

8

PIN 16=VCC
PIN 8=GND

SERIAL { H
DATA SA 10
INPUT
SERIAL SHIFTI
PARALLEL LOAD

~ VCC
~ CLOCK INHIBIT

E

F 4
G 5
6

15

16

9

~B
~A

~ QH

CLOCK
CLOCK INHIBIT 15

FUNCTION TABLE
Serial Shift!
Parallel Load

Inputs
Clock
Inhibit
Clock

Internal Stages

Output

.r
.r

X
L
L

SA
X
L
H

A-H
a ... h
X
X

QA
a
L
H

QB
b
·OAn
OAn

OGn
OGn

Serial Shift via Clock

H
H

L
L

.r
.r

L
H

X
X

L
H

OAn
OAn

OGn
OGn

Serial Shift via Clock Inhibit

H
H

X
H

X
X

X
X

No Change

Inhibited Clock

H

L

H
X
L

X

X

No Change

No Clock

L
H
H

X =don't care

X

QH
h

Operation
Asynchronous Parallel Load

OAn - OGn = Data shifted from the preceding stage

This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
10195

© Motorola, Inc. 1995

3-238

REV 0

®

MOTOROLA

MC54/74HC 165A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
rnA

'in
lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

-65to+ 150

"e

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND S (Vin or Vout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or Vce).
Unused outputs must be left open.

"e
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65" to 125"C
Ceramic DIP: -10 mW/"C from 100" to 125"e
SOIC Package: -7 mW/"C from 65" to 125"C
TSSOP Package: - 6.1 mW/"e from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

Vec=2.0V
Vec = 3.0 V
Vec=4.5V
Vec = 6.0 V

Min

Max

Unit

2.0

6.0

V

0

Vec

V

-55

+ 125

"e

0
0
0

1000
600
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

V

-55to
25°C

S 85°C

S 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=O.1 VorVCe-0.1 V
1I0uti S 20 ~A

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.1 VorVCc-O.l V
"outl S 20 ~A

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.80

0.5
0.9
1.35
1.80

0.5
0.9
1.35
1.80

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti S 20~A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL 1I0uti S 2.4 rnA
1I0uti S 4.0 rnA
1I0uti S 5.2 rnA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

V

VCC
Symbol

VOH

Parameter

High-Speed CMOS Logic Data
DL129-Rev6

Test Conditions

3-239

MOTOROLA

MC54/74HC165A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

lin
ICC

Parameter

Test Conditions

=

Maximum Low-Level Output
Voltage

Vin VIH or VIL
"outl s 20 (.IA
Vin

=VIH or VIL

Maximum Input Leakage Current

Vin

Maximum Quiescent Supply
Current (per Package)

Vin VCC or GND
lout =: 0 (.IA

=VCC or GND
=

"outl s 2.4 mA
"outl :5 4.0 mA
"outl :5 5.2 mA

VCC
V

-55to
25°C

:5 85°C

:5 125°C

Unit

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

6.0

. ±0.1

±1.0

± 1.0

itA

40

160

itA

6.0

4

VCC
V

-55to
25°C

NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Symbol

:5 85°C

:5 125°C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)

2.0
3.0
4.5
6.0

10
15
30
50

9
14
28
45

8
12
25
40

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH
(Figures 1 and 8)

2.0
3.0
4.5
6.0

110
36
22
19

125
45
26
23

160
60
32
28

ns

tPLH,
tpHL

Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH
(Figures 2 and 8)

2.0
3.0
4.5
6.0

85
57
25
19

96
63
29
23

106
71
32
27

ns

tpLH,
tpHL

Maximum Propagation Delay, Input H to QH or QH
(Figures 3 and 8)

2.0
3.0
4.5
6.0

110
36
22
19

125
45
26
23

160
60
32
28

ns

iTLH,
tTHL

Maximum Output Transition lime, Any Output
(Figures 1 and 8)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°C, VCC
Power Dissipation Capacitance (Per Package)'

=5.0 V

40

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2! + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-240

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC 165A
TIMING REQUIREMENTS (Input tr =tf =6 ns)
Guaranteed Limit
Symbol

Vee
V

-55to
25°e

" 85°e

" 125°e

Unit

tsu

Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load
(Figure 4)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tsu

Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
(Figure 5)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tsu

Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
(Figure 6)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tsu

Minimum Setup Time, Clock to Clock Inhibit
(Figure 7)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

th

Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
(Figure 4)

2.0
3.0
4.5
6.0

1
1
1
1

1
1
1
1

1
1
1
1

ns

th

Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
(Figure 5)

2.0
3.0
4.5
6.0

1
1
1
1

1
1
1
1

1
1
1
1

ns

th

Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
(Figure 6)

2.0
3.0
4.5
6.0

1
1
1
1

1
1
1
1

1
1
1
1

ns

Minimum Recovery Time, Clock to Clock Inhibit
(Figure 7)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tw

Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)

2.0
3.0
4.5
6.0

70
27
15
13

90
32
19
16

100
36
22
19

ns

tw

Minimum Pulse width, Serial Shift/Parallel Load
(Figure 2)

2.0
3.0
4.5
6.0

70
27
15
13

90
32
19
16

100
36
22
19

ns

Maximum Inpul Rise and Fall Times
(Figure 1)

2.0
3.0
4.5
6.0

tODD

tODD

tODD

ns

800
500
400

800
500
400

800
500
400

trec

Ir, If

Parameter

NOTE: Information on typical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-241

(

MOTOROLA

MC54/74HC 165A
PIN DESCRIPTIONS
INPUTS

applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.

A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)
Parallel Data inputs. Data on these inputs are' asynchronously entered in parallel into the internal flip-flops when the
Serial Shift/Parallel Load input is low.

Clock, Clock Inhibit (Pins 2, 15)
Clock inputs. These two clock inputs function identically.
Either may be used as an active-high clock inhibit. However,
to avoid double clocking, the inhibit input should go high only
while the clock'input is high.
The shift register is completely static, allowing Clock rates
down to DC in a continuous or intermittent mode.

SA (Pin 10)
Serial Data input. When the Serial Shift/Parallel Load input
is high, data on this pin is serially entered into the first stage
of the shift register with the rising edge of the Clock.
CONTROL INPUTS

OUTPUTS,

Serial Shift/Parallel Load (Pin 1)

QH, QH (Pins 9, 7)

Data-entry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level is

Complementary Shift Register outputs. These pins are the
non inverted and inverted outputs of the eighth stage of the
,shift register.

MOTOROLA

3-242

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC165A
SWITCHING WAVEFORMS

VCC

CLOCK
OR CLOCK INHIBIT

Figure 1. Serial-Shift Mode

Figure 2. Parallel-Load Mode

--~ r---~ ,.---VCC

INPUTSA-H

-VCC

INPUTH

_ _- J " - - - - - - '

'----GND

11"-----GND
~----VCC

SERIAL SHIFT!
PARALLEL LOAD

-GND
ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)

trHL

Figure 3. Parallel-Load Mode

INPUT SA

CLOCK
OR CLOCK INHIBIT

~
.

~

Figure 4. Parallel-Load Mode

VALlD~

SERIAL SHIFT!
PARALLEL LOAD

:~~

GND

tsu~th

CLOCK
OR CLOCK INHIBIT _ _ _ _oJ.

Isuj;th
______
.J

~J-=VCC
50%

- - - - - VCC
50%
-GND

Figure 5. Serial-Shift Mode

------VCC
50%
-GND

Figure 6. Serial-Shift Mode

TEST POINT
OUTPUT

-VCC

DEVICE
UNDER
TEST

-----GND

CLOCK
GND

• Includes all probe and jig capacitance

Figure 7. Serial-Shift, Clock-Inhibit Mode

High-Speed CMOS Logic Data
DL129-Rev6

3-243

Figure 8. Test Circuit

MOTOROLA

MC54174HC165A
EXPANDED LOGIC DIAGRAM

B

A

C

F

G

H

SERIAL SHIFTI
PARALLEL LOAD
SERIAL DATA
INPUT SA

TIMING DIAGRAM

CLOCK
CLOCK INHIBIT

----"""1.____________

SA1~_ _ _~-------------Ur---+-----------~
A-.Jj HIL..-_-I--_ _ _ _ _ _ _ _ _ __

SERIALSHIFTI
PARALLEL LOAD

B~

C~L..---~-------------------­
PARALLEL
DATA
INPUTS

D~

E--FmL..-__~-------------------­
Fl

IL
I

G~~~

_ _ _ _ _ _ _ _ __

H~L..---~--------------------

QH.-i-

HH~

OH
CLOCK
I N H I B l r SERIAL-8HIFTMODE
MODE
PARALLEL LOAD

MOTOROLA

I--

3-244

High-Speed CMOS Logic Data

DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC173

Quad 3-State D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS

N SUFFIX
PLASTIC PACKAGE
CASE 64S-QS

The MC74HC173 is identical in pinout to the LS 173. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flip-flops with the rising
edge of the common Clock. When either or both of the Output Enable
Controls is high, the outputs are in a high-impedance state. This feature
allows the HC173 to be used in bus-oriented systems. The Reset feature is
asynchronous and active high.

DSUFFIX
SOIC PACKAGE
CASE 751 6-05

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 /!A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
• Chip Complexity 208 FETs or 52 Equivalent Gates

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

PIN ASSIGNMENT

LOGIC DIAGRAM

DATA
INPUTS

1~~

14

13
D2 12
D3 11

4 00
01
02
03

Plastic
SOIC

1

OEl

le

16

VCC

OE2

2

15

RESET

00

3-STATE
NONINVERTING
OUTPUTS

01

4

14

DO

13

Dl

12

D2

6.

11

D3

CLOCK

7

10

DE2

GND

8

9

DEl.

02
03

DATA- {DEl
ENABLES DE2
RESET--L>!.-----...J
OUTPUT {OEl
ENABLES OE2

VCC = PIN 16
GND= PIN 8

FUNCTION TABLE
Inputs
Output Enables

Output
Data Enables

OEl

OE2

Reset

Clock

DEl

DE2

Data
D

L
L
L
L
L
L
L
L
L
H
H

L
L
L
L
L
L
L
L
H
L
H

H
L
L
L
L
L
L
L
X
X

X
L
H

X
X

X

X

X
X
X
H
L
L
X
X
X
X

X
X
X
X
L
H
X
X
X
X

X

..r
..r
..r
..r
"\...
X
X
X

X
H
X
L
L
X
X

X
X

10195

© Motorola, Inc. 1995

3-245

REV 6

®

Q

L
No Change
No Change
No Change
No Change
L
H
No Change
High Impedance
High Impedance
High Impedance

MOTOROLA

MC74HC173
MAXIMUM RATINGS·
Symbol
VCC
Vin
Vout
lin

Parameter

Value

Unit

- 0.5 to + 7.0

V

DC Input Vo~age (Referenced to GND)

-1.510 Vec + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

DC Supply Voltage (Referenced to GND)

lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, Vec and GND Pins

±75

rnA

PD

Power Dissipation in Still Air

.750
500

mW

-65to+150

°C

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,;; (Vin or Vout) ,;; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open ..

°C
260

* MaXimum Ratings are those values beyond which damage to the deVice may occur.
Functional operation should be restricted to the Recommended Operating Condnions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

. Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

t r, tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0·

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

,;; 85°C

,;; 125°C

Unit

Minimum High-Level Input
Voltage

Vout=O.l VorVCC-O.l V
"outl ,;; 20 I1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.l VorVcc-O.l V
"outl ,;; 2Ol1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
"outl ,;; 2Ol1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL "outl ,;; 6.0 rnA
"outl ,;; 7.8 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
"outl ,;; 20 I1A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOL

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25°C

VIH

VOH

Parameter

VCC
V

Yin = VIH or VIL

"outl ,;; 6.0 rnA
"outl ,;; 7.8 rnA

V

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

± 1.0

I1A

IOZ

Maximum Three-State
Leakage Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

I1A

ICC

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 I1A

6.0

8

80

160

I1A

lin

NOTE: Information on tYPical parametric values can be found in Chapter 2.

MOTOROLA

3-246

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC173
AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Symbol

Vee
V

-55to
25°e

,; 85°e

,; 125°e

Unit

'max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q
(Figures 1 and 5)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpHL

Maximum Propagation Delay, Reset to Q
(Figures 2 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tPZL,
tpZH

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tTLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 5)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Maximum Input Capacitance

-

10

10

10

pF

Maximum Three-State Output Capacitance
(Output in High-Impedance State)

-

15

15

15

pF

Cin
Cout

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Flip-Flop)'

=5.0 V

35

'Used to determine the (lo-Ioad dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr =tf =6 ns)
Guaranteed Limit
Symbol

Vee
V

-55to
25°e

,; 85°e

,; 125°e

Unit

tsu

Minimum Setup Time, Input D or DE to Clock
(Figure 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Clock to Input D or DE
(Figure 4)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

90
18
15

115
23
20

135
27
23

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

trec

t r, tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-247

MOTOROLA

MC74HC173
PIN DESCRIPTIONS
INPUTS

CONTROL INPUT
Reset (Pin 15)

00,01,02,03 (Pins 14, 13, 12, 11)

Asynchronous reset input. A high level on this pin resets all
flip-flops and forces the Q outputs low, if they are not already
in high-impedance state.

4-bit data inputs. Data on these pins, when enabled by the
Data-Enable Controls, are entered into the flip-flops on the
rising edge of the clock.

OE1, OE2 (Pins 9, 10)
Active-low Data Enable Control inputs. When both Data
Enable Controls are low, data at the D inputs are loaded into
the flip-flops with the rising edge of the Clock input. When
either or both of these controls are high, there is no change in
the state of the flip-flops, regardless of any changes at the D
or Clock inputs.

CLOCK (Pin 7)
Clock input.
OUTPUTS
QO, Q1, Q2, Q3 (Pins 3, 4, 5, 6)

OE1, OE2 (Pins 1, 2)

3-state register outputs. During normal operation of the
device, the outputs of the D flip-flops appear at these pins.
During 3-state operation, these outputs assume a highimpedance state.

Output Enable Control inputs. When either or both of the
Output Enable Controls are high, the Q outputs of the device
are in the high-impedance state. When both controls are
low, the device outputs display the data in the flip-flops.

SWITCHING WAVEFORMS
~---VCC

CLOCK

RESET
-GND

Q

Q
CLOCK

vCC

50%
r
_ _ _ _ _ _ _ _--J.
-GND

Figure 2.

Figure 1.

~---VCC

OE
HIGH
IMPEDANCE

Q

INPUTD
ORDE

~

VALlD~ VCC

50%

tsuy.;t

GND

h

-----VCC

Q
HIGH
IMPEDANCE

Figure 3.

MOTOROLA

50%

CLOCK
.

-

-GND

Figure 4.

3-248

High-Speed CMOS Logic Data

DL129 -RevS

MC74HC173
TEST CIRCUITS
TEST POINT

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

i--=-0U=..T,,-P=..UT'--4o-JV1Vknlr-_ [

CONNECT TO Vee WHEN
TESTING tpLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tPHZ and tpZH.

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 6.

Figure 5.

LOGIC DETAIL
VCC

~
pLoo
~

DATA
INPUTS

Vee

~
pL02
~
Vec

~
p.L03
~
DATA- {DEl 9
ENABLES DE2 _1_0""'-~

CLOCK

OUTPUT {OEI
ENABLES
OE2-=-----l

High-Speed CMOS Logic Data
DL129-Rev6

3-249

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Hex D Flip-Flop with
Common Clock and Reset

MC54/74HC174A

High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 620-10

The MC54174HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of six D flip-flops with common Clock and Reset
inputs. Each flip-flop is loaded with a low-to-high transition of the Clock
input. Reset is asynchronous and active-low.

N SUFFIX
PLASTIC PACKAGE
CASE 64!HlB

• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 ~
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 162 FETs or 40.5 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751S-05

ORDERING INFORMATION

LOGIC DIAGRAM

DATA
INPUTS

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD

DO

2 QO

Dl 4

5 Ql

D2 6
D3 11

7 Q2
10 Q3

D4 13

12 Q4

D5 14

15 Q5

NONINVERTING
OUTPUTS

PIN ASSIGNMENT
RESET

Design Criteria

1-

16

~ VCC

15 ~ Q5

QO l 2
DO

3

14

Dl

4

13

PD5
PD4

Ql

5

12

~ Q4

D2

6

11 ~ D3

Q2

7

tOp Q3

GND

8

CLOCK -","9_--11>

RESET -"-1_ _ _ _...J

Ceramic
Plastic
SOIC

PIN 16= VCC
PIN 8= GND

9

PCLOCK

Value

Units

40.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

j.lW

Reset

Clock

D

Q

.0075

pJ

L
H
H
H
H

X

X
H
L
X
X

L
H
L
No Change
No Change

Internal Gate Count"

FUNCTION TABLE
Inputs

Speed Power Product

" Equivalent to a two-input NAND gate.

10195

© Motorola, Inc. 1995

3-250

REV6

.r
.r
L
""\...

®

Output

MOTOROLA

MC54/74HC174A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7.0

V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

-0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65to+150

°C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to evoid applications of any
voltage higher than maximum rated
vOIt.ages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVout) s Vce.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or Vec).
Unused outputs must be left open.

°C
260
300

• MaxImum Ratings are those values beyond whIch damage to the devIce may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mW/oe from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

0

Vce

V

-55

+ 125

°e

0
0
0

1000
500
400

ns

VCC=2.0V
Vce=4.5V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25°C

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVeC-0.1 V
"outl s 20 !LA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
"outl s 20!LA .

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
"outl s 20 !LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

VOH

Parameter

VCC
V

Yin = VIH or VIL
"outl s 4.0 mA
"outl s 5.2 mA
VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL
"outl s 20 !LA
Yin = VIH or VIL
"outl s 4.0 mA
lIoutl s 5.2 mA

High-Speed CMOS Logic Data
DL129-Rev6

3-251

V

MOTOROLA

MC54/74HC 174A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to

Symbol

Parameter

25°C

,; 85°C

,; 125°C

lin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

± 1.0

±1.0

~A

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 ~A

6.0

4.0

40

160

~A

ICC

Test Conditions

Unit

NOTES:
1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2.
2. Total Supply Current = ICC + SL\ICC.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Parameter

Vce
V

-55to
25°e

,; 85°C

,; 125°e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH
tpHL

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

tpLH
tpHL

Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)

2.0
4.5
6.0

110
21
19

140
28
24

160
32
27

ns

trLH
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

10

10

10

pF

Maximum Input Capacitance

Cin

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°C, Vec
Power Dissipation Capacitance (Per Enabled Output)"
"Used to determine the no-load dynamic power consumption: PD

=5.0 V

62

=CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Parameter

Fig.

Vce
V

-55 to 25°C
Min

Max

,; 85°C
Min

,; 125°C

Max

Min

Max

Unit

tsu

Minimum Setup Time, Data to Clock

3

2.0
4.5
6.0

50
10
9.0

65
13
11

75
15
13

ns

th

Minimum Hold Time, Clock to Data

3

2.0
4.5
6.0

5.0
5.0 .
5.0

5.0
5.0
5.0

5.0
5.0
5.0

ns

Minimum Recovery Time, Reset Inactive to Clock

2

2.0
4.5
6.0

5.0
5.0
5.0

5.0
5.0
5.0

5.0
5.0
5.0

ns

tw

Minimum Pulse Width, Clock

1

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

tw

Minimum Pulse Width, Reset

2

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Rise and Fall Times

1

2.0
4.5
6.0

trec

tr,tf

MOTOROLA

3-252

1000
500
400

1000
500
400

1000
500
400

ns

High-Speed CMOS Logic Data
DL129-Rev6

er

Q

tre
Q

50'k
CLOCK - - - - - - - - - - - ' -

Vce

-GND

Figure 2.

Figure 1.

TEST POINT
OUTPUT
VCC

DEVICE
UNDER
TEST

DATA
GND

-----VCC
CLOCK

• Includes all probe and jig capacitance

-GND

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 4. Test Circuit

3-253

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Hex D Flip-Flop with
Common Clock and Reset
with LSTTL Compatible Inputs

MC74HCT174A
N SUFFIX
PLASTIC PACKAGE
CASE 648-08

High-Performance Silicon-Gate CMOS
The MC74HCT174A is identical in pinout to the LS174. This device may
be used as a level converter for interfacing TTL or NMOS outputs to High
Speed CMOS inputs.
This device consists of six D flip-flops with common Clock and Reset
inputs. Each flip-flop is loaded with a low-te-high transition of the Clock
input. Reset is asynchronous and active-low.
•
•
•
•
•
•
•

DSUFFIX
SOIC PACKAGE
CASE 7518-05

Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 I!A
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 178 FETs or 44.5 Equivalent Gates

ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD

PIN ASSIGNMENT

[3]
OATA
INPUTS

2 00

01 4
02 6

5 01
7 02

03 11

10 03

04 13

12 Q4

05 14

15 05

Ie

16

00

2

15

00

3

RESET

LOGIC DIAGRAM

00

Plastic
SOIC

01

4

01

5

02 [ 6

NON INVERTING
OUTPUTS

DVCC

P05
14 P05
t3 P04
12 P04
11 P03
10 P03
9 PCLOCK

02 [ 7

GNO [ 8

FUNCTION TABLE '

CLOCK -"9_---11>

Inputs

RESET -'1_ _ _ _--'

PIN 16= VCC
PIN 8= GNO

Design Criteria

Value

Units

44.5

ea.

1.5

ns

Internal Gate Power Dissipation

0.005

IlW

Speed Power Product

0.0075

pJ

Internal Gate Count"
Internal Gate Propagation Delay

Output

Reset

Clock

D

Q

L
H
H
H
H

X

X
H
L
X
X

L
H
L
No Change
No Change

..r
..r
L
"\..

• EqUivalent to a two-Input NAND gate.

10195

© Motorola, Inc, 1995

3-254

REVS

®

MOTOROLA

MC?4HCT1?4A
MAXIMUM RATINGS·
Symbol

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

Po

Power Dissipation in Still Air

750
500

mW

-65to+ 150

°C

VCC
Vin
Vout
lin

Tstg

TL

Parameter
DC Supply Vollage (Referenced to GND)

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However. precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ,; (Vin orVout) ,; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -·10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

°C

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

85°e

125°C

Unit

VIH

Vout=O.1 orVcc-O.l V
lIoutl ,; 20 flA

4.5
5.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum Low-Level Input
Voltage

V out=O.1 orVCC-O.l V
lIoutl ,; 20 I1A

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl ,; 20 I1A

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

Vin = VIH or VIL
lIoutl ,; 4.0 mA

4.5

3.98

3.84

3.70

Vin = VIH or VIL
lIoutl ,; 20 I1A

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

VOL

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25°C

Minimum High-Level Input
Voltage

VOH

Parameter

Vec
V

V

Vin = VIH or VIL
lIoutl ,; 4.0 mA

4.5

0.26

0.33

0.4

Vin = VCC or GND

5.5

±0.1

±1.0

±1.0

I1A

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 I1A

5.5

4.0

40

160

I1A

AICC

Additional Quiescent Supply
Current

Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 I1A

lin

Maximum Input Leakage Current

5.5

~-55°e

25°C to 125°e

2.9

2.4

rnA

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-255

MOTOROLA

MC?4HCT1?4A
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ± 10%, CL =50 pF, Input tr =tf =6.0 ns)
Guaranteed Limit
-55to
25°e

s 85°e

s 125°e

Unit

fMAX

M'aximum Clock Frequency (50% Duty Cycle)

30

24

20

MHz

tPLH,
tPHL

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

24

30

36

ns

tpHL

Maximum Propagation Delay, Reset toQ
(Figures 2 and 4)

23

28

35

ns

trLH,
trHL.

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

15

19

22

ns

Maximum'lnput Capacitance

10

10

10

pF

Symbol

Cin

Parameter

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°e, Vee

=5.0 V

79

Power Dissipation Capacitance (Per Enabled Output)"

• Used to determine the no-load dynamic power consumption: Po = CpO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL =50 pF, Input tr =tf =6.0 ns)
Guaranteed Limit

Symbol

s

Max

Min

s

85°e
Max

125°e

Fig.

Min

tsu

Minimum Setup Time, Data to Clock

3

10

13

15

ns

th

Minimum Hold Time, Clock to Data

3

5.0

6.0

8.0

ns

Minimum Recovery Time, Reset Inactive to Clock

2

5.0

6.0

8.0

ns

tw

Minimum Pulse Width, Clock

1

15

19

22

ns

tw

Minimum Pulse Width, Reset

2

15

19

22

Maximum Input Rise and Fall Times

1

trec

t r, tf

MOTOROLA

Parameter

-55to 25°e

3-256

500

500

Min

Max

Unit

ns
500

ns

High-Speed CMOS Logic Data
DL129-Rev6

MC?4HCT1?4A
SWITCHING WAVEFORMS

,..------3.0 V

CLOCK
RESET

-GND

Q

Q

CLOCK

Figure 1.

t r e c J - 3.0V
1.3V
_ _ _ _ _ _ _ _- - 1
-GND

Figure 2.

TEST POINT

DATA

~
~

VALlD~

OUTPUT
DEVICE
UNDER
TEST

:::

t s u J , th

-----3.0 V

CLOCK

1.3 V

• Includes all probe and jig capacitance

-GND

______
....J

Figure 3.

Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM
CLOCK
DO~---~--~

RESET
Dl~4_ _ _~_+-~

D2~6_ _ _~_+-~

D3 11

D4 13

D5 14

High-Speed CMOS Logic Data
DL129-Rev6

3-257

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad D Flip-Flop with
Common Clock and Reset

MC54/74HC175

High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 620-10

The MC54174HC175 is identical in pinout to the LS175. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of four D flip-flops with common Reset and Clock
inputs, and separate D inputs. Reset (active-low) is asynchronous and
occurs when a low level is applied to the Reset input. Information at a D input
is transferred to the corresponding Q output on the next positive going edge
of the Clock input.
.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 /lA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity 166 FETs or 41.5 Equivalent Gates

D SUFFIX
SOIC PACKAGE
CASE 751 9-05

ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

Ceramic
Plastic
SOIC

LOGIC DIAGRAM

raJ

2
3
7
6
10
11
15
14

CLOCK

r

4

DATA
INPUTS

5
D1
D2 12
D3 13

00

PIN ASSIGNMENT

00
01

ill
02

Q2

RESET

INVERTING
AND
NONINVERTING
OUTPUTS

03

2

00

3

16

15

DO

4

D1

5

ill

6

11

Q2

01

7

10

02

GND

8

9

Q3

RESET
PIN 16= VCC
PIN 8=GND

PVCC
P03
14 PQ3
13 PD3
12 PD2

1-

QO

CLOCK

FUNCTION TABLE
Reset
L
H
H
H

10195

© Motorola, Inc. 1995

3-258

REV 6

Inputs
Clock

X

.r
.r
L

®

Outputs
D

X
H
L
X

Q

Q

L
H
H
L
L
H
No Change

MOTOROLA

MC54174HC175
MAXIMUM RATINGS'
Symbol

Value

Unit

-0.5to+7.0

V

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget.

750
500

mW

-65to+150

°c

VCC
Yin

Vout

Tstg
TL

Parameter
DC Supply Voltage (Referenced to GND)

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,;; (Vin or Vout) ,;; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol

VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

,;; 85°C

,;; 125°C

Unit

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
1I0uti ,;; 20 ~A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
42

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.l VorVcc-O.l V
1I0uti ,;; 20 ~A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0utl';; 20~

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL 1I0uti ,;; 4.0 mA
1I0uti ,;; 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
1I0uti ,;; 20~A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL 1I0uti ,;; 4.0 mA
1I0uti ,;; 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

~A

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND

6.0

8

80

160

~

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25°C

VIH

VOH

Parameter

Vee
V

V

10ut=0~

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-259

MOTOROLA

MC54174HC175
AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Input tr = tf = 6 ns)
Guaranteed limit
Symbol

Vee
V

-55to
25°e

s

s

125°e

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tplH,
tPHl

Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpHL

Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

85°e

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Flip-Flop)'

=5.0 V

35

'Used to determine the no-load dynamic power consumption: Po = CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed limit
Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

tsu

Minimum Setup Time, Data to Clock
(Figure 3)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Clock to Data
(Figure 3)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
'24
20

ns

tr,tf

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

tree

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-260

High-Speed CMOS Logic Data
Dl129-Rev6

MC54174HC175
SWITCHING WAVEFORMS

,..------VCC
RESET

CLOCK

-GND

Q

OorO
trecJVCC

CLOCK

Figure 1.

50%

---------1

-GND

Figure 2.

00' =hy.;VALO~::
-----VCC
50%
-GND

CLOCK
-

Figure 3.

TEST CIRCUIT

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

* Includes aU probe and jig capacitance

Figure 4.

High-Speed CMOS Logic Data
DL129-Rev6

3-261

MOTOROLA

MC54174HC175
EXPANDED LOGIC DIAGRAM

DO

4

CLOCK

9

Dl

5

a

D

00

C
CR

Q5

a

D

7

C
CR

D2

12

Of

a

D

C
CR

D3

l3J

13

a

D

01

C
CR

10

02

11

Q2

15

03

14

as

RESET

MOTOROLA

3-262

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC175A

Product Preview

Quad D Flip-Flop with
Common Clock and Reset

J SUFFIX
CERAMIC PACKAGE
CASE 620-10

High-Performance Silicon-Gate CMOS
The MC54n4HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of four D flip-flops with common Reset and Clock
inputs; and separate D inputs. Reset (active-low) is asynchronous and
occurs when a low level is applied to the Reset input. Information at a D input
is transferred to the corresponding Q output on the next positive going edge
of the Clock input.
•
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 I1A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity 166 FETs or 41.5 Equivalent Gates

NSUFFIX
PLASTIC PACKAGE
CASE 64B-OB

16#

DSUFFIX
SOIC PACKAGE
CASE 751B-{)5

DTSUFFIX
TSSOP PACKAGE
CASE 94BF-{)1

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

LOGIC DIAGRAM
CLOCK

OATA
INPUTS

9

00
Q5

r'
01

5

02

12

03

13

7
10
11
15
14

01

OT
02

Q2

INVERTING
ANO
NONINVERTING
OUTPUTS

Ceramic
Plastic
SOIC
TSSOP

PIN ASSIGNMENT
16

~ VCC

00 [ 2

15

P03

Q5[ 3

14

pOO

DO [ 4

13

D1 [ 5

12

RESET [ 1e

03

00

RESET
PIN 16 =VCC
PIN 8 = GNO

P03
P02

6

11

~Q2

01[ 7

10

P02

GNO [ 8

9

OT[

PCLOCK

FUNCTION TABLE
Inputs
Reset
L
H
H
H

Clock

D

Outputs
Q
Q

X

X
H
L
X

L
H
H
L
L
H
No Change

..r
..r
L

This document contains information on a product under development. Motorola reserves the right to
change or discontinue this product without notice.

10195

© Motorola, Inc. 1995

3-263

REV 0

®

MOTOROLA

MC54/74HC175A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lin
lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

-65to+150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVouU s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mWI"C from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC =2.OV
VCC=3.0V
VCC = 4.5 V
VCC=6.0V

MIn

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
600
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCc-0.1 V
"outl s 20 !1A

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
42

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
1I0uti s 20!1A

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.80

0.5
0.9
1.35
1.80

0.5
0.9
1.35
1.80

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20!1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL 1I0uti s 2.4 mA
1I0utl s 4.0 mA
1I0uti s 5.2 mA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

VOH

MOTOROLA

Parameter

Test Conditions

3-264

High-Speed CMOS LogiC Data
DL129-Rev6

MC54/74HC175A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

Parameter

Test Conditions
Vin =VIH or VIL
lIoutl :5 20 ~A

Maximum Low-Level Output
Voltage

Vin = VIH or VIL

lin
ICC

lIoutl :5 2.4 mA
lIoutl :5 4.0 mA
lIoutl :5 5.2 mA

VCC
V

-55to
25'C

:5 85'C

:5 125'C

Unit

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Maximum Input Leakage Current

Vin

=VCC or GND

6.0

±0.1

±1.0

±1.0

~A

Maximum Quiescent Supply
Current (per Package)

Vin =VCC or GND
lout =0 ~A

6.0

4

40

160

~A

VCC
V

-55to
25'C

NOTE: Information on typical parametric values can be found in Chapter 2.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

:5 85'C

:5 125'C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
3.0
4.5
6.0

10
15
30
50

9
14
28
45

8
12
25
40

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)

2.0
3.0
4.5
6.0

110
36
22
19

125
45
26
23

160
60
32
28

ns

tpHL

Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)

2.0
3.0
4.5
6.0

90
40
19
16

220
55
22
19

130
70
30
25

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'C, Vce
Power Dissipation Capacitance (Per Flip-Flop)'

=5.0 V

35

* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev6

3-265

MOTOROLA"

MC54174HC175A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit

Vee

-55to

V

25°e

s 85°e

s 125°e

Unit

lsu

Minimum Setup Time, Data to Clock
(Figure 3)

2.0
3.0
4.5
6.0

75
30
15
13

95.
40
19
16

110
55
22
19

ns

th

Minimum Hold Time, Clock to Data
(Figure 3)

2.0
3.0
4.5
6.0

1
1
1
1

1
1
1
1

1
1
1
1

ns

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
3.0
4.5
6.0

1000
800
500
400

1000
800
500
400

1000
800
500
400

ns

Symbol

trec

t r, tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-266

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC175A
SWITCHING WAVEFORMS

r------VCC
RESET

CLOCK

-GND

Q

rec
t :}-

QorO
CLOCK

VCC

50%
------------~

Figure 1.

-GND

Figure 2.

DATA --F=:ALlD=1r-~~~
CLOCK

~F.~

-------'

-----VCC
50%
--GND

Figure 3.

TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 4.

High-Speed CMOS Logic Data
DL129- Rev 6

3-267

MOTOROLA

NlC54174HC175A
EXPANDED LOGIC .DIAGRAM

DO

4

CLOCK

9

D1

5

a

D

C
CR

2

00

3

QO

a

0

01

C
CR

D2

12

Q1

a

0

C
CR

03

[31

13

a

D

C
CR
RESET

MO:rOROLA

10

02

11

Q2

15

03

14

53

1

3-268

. High-Speed CMOS Logic Data

DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC194

4-Bit Bidirectional
Universal Shift Register

•

High-Performance Silicon-Gate CMOS

!i.~
161'1VHII1 1

The MC74HC194 is identical in pinout to the LS194 and the MC14194B
metal gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pull-up resistors, they are compatible with LSTTL
outputs.
This static shift register features parallel load, serial load (shift right and
shift left), hold, and reset modes of operation. These modes are tabulated in
the Function Table, and further explanation can be found in the Pin
Description section.

ORDERING INFORMATION
MC74HCXXXN

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 !lA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity 164 FETs or 41 Equivalent Gates

RESET

I: I
3

INPUTS

13 Oc
12 OD

5

C
D

6

PVCC
POA
14 POB
13 POc
12 POD
11 PCLOCK

1.

SA

2

A

3

B

4

C

5

D

6

SD

7

GND

8

16
15

10p S1
9

PSO

~~ 6~~:LLEL

14
15

4

PAAAllEC
DATA

Plastic

PIN ASSIGNMENT

LOGIC DIAGRAM
SERIAL! SA
DATA
INPUTS SD

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

OUTPUTS

11

CLOCK
MODE { S1
SELECT SO
RESET

Vcc = PIN 16
GND = PIN 8

FUNCTION TABLE
Inputs
Mode
Select
Reset

S1

SO

Serial
Data
Clock

So

Parallel Data

Outputs

SA

A

S

C

0

QA

QS

QC

QD

Operating
Mode

L

X

X

X

X

X

X

X

X

X

L

L

L

L

Reset

H

H

H

X

X

a

b

c

d

a

b

c

d

Parallel Load

H
H

L
L

H
H

X
X

H
L

X
X

X
X

X
X

X
X

H
L

QAn
QAn

QBn
QBn

QCn
QCn

H
H

H
H

L
L

..r
..r
..r
..r
..r

H
L

X
X

X

X
X

X
X

X

X

QBn
QBn

QCn
QCn

QDn
QDn

H
L

H
H
H

L
X
X

L

X
L
H

X
X
X

X
X

X
X
X

X
X
X

X

X

X
X
X

X

H = high level (steady state)
L = low level (steady state)
X = don't care
= transition from low to high level.

..r

X

X
X

X

No Change
No Change
No Change

Shift Left
Hold

a, b, c, d = the level of steady-state Input at Inputs A, B, C, or D, respectively.
QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD, respectively, before
the most recent..r transition of the clock.

10/95

© Motorola. Inc. 1995

Shift Right

3-269

REV6

®

MOTOROLA

[3J

MC74HC194
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

- 0.5 to+ 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to Vce + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lin
lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, Vec and GND Pins

±50

mA

Po

Power Dissipation in Still Air

750

mW

-65to+ 150

°e

Tstg
TL

PlasticDIPt

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than m'aximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND,s (VinorVout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
,level (e.g., either GND or VCC).
Unused outputs must be left open.

°e
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-5Sto
25°C

S

85°C

S

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVcc-O.l V
lIoutl S 20J.lA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
lIoutl S 20J.lA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output

Vin = VIH or VIL
lIoutl S 20 J.LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl S 4.0 mA
lIoutl S 5.2 mA

4.5
6.0

3.98
5.48

3.84.
5.34

3.70
5.20

Vin = VIH or VIL
lIoutl S 20j.lA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1,
0.1

0.1
0.1
0.1

Vin = VIH or VIL lIoutl S 4.0 mA
lIoutl S 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

J.LA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 J.LA

6.0

8

80

160

J.LA

VOH

Voltage

VOL

lin
ICC

Maximum Low-Level Output
Voltage

NOTE: Information on typical parametric values can be found

MOTOROLA

In

V

Chapter 2.

3-270

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC194
AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Inputtr = tf = 6 ns)
Guaranteed Limit

Vee
V

-55to
25°e

125°e

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tplH,
tpHl

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

2.0
4.5
6.0

145
29
25

180
36
31

220
44
38

ns

tPHl

Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

trlH,
trHl

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

:!i

B5°e

:!i

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.

Typical @ 25°e,
Power Dissipation Capacitance (Per Package)'

Vee =5.0 V

90

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr =tf =6 ns)
Guaranteed Limit

Vee
Symbol

V

Parameter

-5510
25°e

tsu

Minimum Setup Time, Parallel Data Inputs to Clock
(Figure 3)

2.0
4.5
6.0

100
20

tsu

Minimum Setup Time, S1 or S2to Clock
(Figure 3)

2.0
4.5
6.0

tsu

Minimum Setup Time, SA or SD to Clock
(Figure 3)

th

:!i

B5°e

:!i

125°e

Unit

150
30
26

ns

17

125
25
21

100
20
17

125
25
21

150
30
26

ns

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

Minimum Hold Time, Clock to any Input (except Reset)
(Figure 3)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

trec

t r, tf

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS logic Data
DL129-Rev6

3--271

MOTOROLA

MC74HC194
PIN DESCRIPTIONS
DATA INPUTS

Reset (Pin 1)

A, B, C, 0 (Pins 3, 4, 5, 6)

A low level applied to this pin resets all stages and forces
all outputs low.

Parallel data inputs.

SO, S1 (Pins 9,10)
Mode-select inputs. These inputs control the mode of operation as described in the function table and below.

SA (Pin 2)
Serial-data input when using shift-right mode.

So (Pin 7)

=

=

Parallel Load Mode (S1 H, SO H)
Data is loaded into the device with a positive transition of
the Clock input.

.

Serial-data input when using shift-left mode.

=

=

Shift Right Mode (S1 L, SO H)
With a positive transition of the Clock input, each bit is
shifted right (in the direction QA toward QD) one stage and
data on the SA Serial Data Input is shifted into stage A.

OUTPUTS
QA, QB, QC, QO (Pins 15,14,13,12)
Parallel data outputs.

Shift Left Mode (S1 = H, SO = L)
With a positive transition of the Clock input, each bit is
shifted left (in the direction QD toward QA) one stage and
data on the SD Serial Data Input is shifted into stage D.

CONTROL INPUTS
Clock (Pin 11)

Hold Mode (S1 = L, SO = L)
Outputs are held.

Clock Input. The shift register is completely static, allowing
Clock rates down to DC in a continuous or intermittent mode.

SWITCHING WAVEFORMS

,----VCC
RESET

CLOCK

-GND

Q

Q

CLOCK

~~I:.-vcc
-GND

50%
________

Figure 1.

Figure 2.

TEST POINT
OUTPUT
VCC

DEVICE
UNDER
TEST

GND
-----VCC
CLOCK
-GND

• Includes all probe and jig capacitance

Figure 4.. Test Circuit

Figure 3.

MOTOROLA

3-272

High-Speed CMOS Logic Data
DL129-Rev6

O;!;;

'co

~:r

~c\,

l-g

:lJ
=>-i4>
-~

~

~

4~ 4~

~ 4~

~~

D
r-C

r

C

~

RESET

~

T

~

J*

-

'-<

CLOCK

'*
-cr
r-

14 ~~~

-

I-

~

4~

~~ ~

;--

-c

-<:D
r- C

rc

r

C 0
Fi.,R

C 0
F),R

~R

~~ ~~

--< D

---

c..!I R

... ...

-...

.... ...

.......

OD

Oc

OB

OA

s:::

PARALLEL DATA OUTPUTS

s:

(")

~

:lJ

~

()

S;

CO

::r:
......

o

oil-

~

MC74HC194
TIMING DIAGRAM
C L O C K .

SO=JH~

MODE-{
SELECT
--L I
INPUTS
S1:.J I I I
RESETI II
rl
SERIAL{ SA
I I
DATA
I I
INPUTS
SD

I

-'1'--------,1-1'-."- - - - I I
I
I r

r-I

I
I

!

I

n

I
I
I

{

I

L:
I.,.,L, I
C --jJHI I I

:
I
I

DILl

I

I

~y...:II----....,11--

::t-H=8-,

PARALLELI :
DATA
OUTPUTS
QC:
QD

r

I~

I

I

B

I

I
I

A--{fHi1
PARALLEL
DATA
INPUTS

I

I

--+-+---!
-*--INHIBIT - - '
RESET

MOTOROLA

3-274

High-Speed CMOS Logic Data

DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC195

4-Bit Universal Shift Register
High-Performance Silicon-Gate CMOS
The MC74HC195 is identical in pinout to the LS195. The device inputs are
compatible with standard CMOS outputs, with pull up resistors, they are
compatible with LSTTL outputs.
This static shift register features parallel load, serial load (shift right), hold,
and reset modes of operation. These modes are tabulated in the Function
Table, and further explanation can be found in the Pin Description section.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 646-06

ORDERING INFORMATION

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 !J.A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 150 FETs or 37.5 Equivalent Gates

MC74HCXXXN

PIN ASSIGNMENT
RESET [ 1_

J[ 2

K[
LOGIC DIAGRAM

SERIAL DATA { J
INPUTS
K

15
14
4

5

"mea
{:
DATA
INPUTS

PARALLEL
DATA
OUTPUTS

Qc
12

C
D

11
10

CLOCK

QA
QB

SERIAL SHIFTI
PARALLEL LOAD

Plastic

16

PVCC

15 P QA
14 P QB

3

A[ 4

13

B[ 5

12

PQC
PQD

C[ 6

11 POD

D[ 7

10 P CLOCK
9

GND [ B

PSERIAL SHIFT!

PARALLEL LOAD

QD
OD

PIN 16 = VCC
PIN B=GND

RESET
FUNCTION TABLE
Inputs
Serial

Parallel

Outputs

Reset

Shift!
Load

Clock

J

K

A

S

C

0

QA

QS

QC

QO

QO

L

X

X

X

X

X

X

X

X

L

L

L

L

H

Reset

H

L

X

X

a

b

c

d

a

b

c

d

d

Parallel Load

H

H

X

X

X

X

X

X

H
H
H
H

H
H
H
H

L
L
H
H

H
L
H
L

X
X

X
X
X

X
X
X
X

X
X
X
X

OAO
L
H

OAO
OAn
OAn
OAn

OCn
OCn
OCn
OCn

OCn
GiCn
GiCn
GiCn

J
L

J
J
J
J

X
X

X

Hold

No Change

GiAn

H = high level (steady state)
L = low level (steady state)
X = don't care
J = transition from low to high level.
a, b, c, d = the level of steady-state input at inputs
A, B, C, or D, respectively.

OSn
OBn
OBn
OBn

Retain First Stage
Reset First Stage
Set First Stage
Toggle First Stage

Serial
Shift

OAO = the level of OA before the indicated steady-state
input conditions were established.
OAn, OBn, OCn the level of 0A. 0B. or OC,
respectively, before the most recent J transition
of the clock.

=

10195

© Motorola. Inc. 1995

Operating Mode

3-275

REV 6

®

ItIIOTOROLA

MC74HC195
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7.0

V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750

mW

Tstg

Storage Temperature

-65to+ 150

°c

TL

Plastic DIPt

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

* Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter

Min

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

s 85°C

s 125'C

Unit

Minimum High-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
lIoutl s 20!lA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.)5
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl s 2O!lA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 20 ItA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl s 4.0 mA
lIoutl s 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
lIoutl s 20 ItA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL lIoutl s 4.0 mA
lIoutl S 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

± 1.0

± 1.0

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 ItA

6.0

8

80

160

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25°C

VIH

VOH

Parameter

VCC
V

V

ItA
ItA

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-276

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC195
AC ELECTRICAL CHARACTERISTICS (CL

=50 pF, Inpullr =If =6 ns)
Guaranteed Limit

Symbol

Parameter

Vee
V

-55to
25°e

,; 85°e

,; 125°e

Unit

f max

Maximum Clock Frequency (50% Duly Cycle)
(Figures 1 and 5)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH,
IpHL

Maximum Propagation Delay, Clock 10 any a or aD
(Figures 1 and 5)

2.0
4.5
6.0

145
29
25

180
36
31

220
44
38

ns

IpLH,
IpHL

Maximum Propagation Delay, Resello any a or aD
(Figures 2 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tTLH,
'THL

Maximum Outpul Transition Time, Any Oulput
(Figures 1 and 5)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Inpul Capacitance

-

10

10

10

pF

Cin

NOTES:
1. For propagation delays with loads other Ihan 50 pF, see Chapter 2.
2. Information on Iypical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Package)'

= 5.0 V

95

• Used to determine the no-load dynamic power consumption: PD = CpD Vee2f + lee Vee. For load considerations, see Chapler 2.
TIMING REQUIREMENTS (Input tr

=If =6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

,; 85°e

,; 125°e

Unit

Isu

Minimum Selup Time, A, B, C, D, J, or K 10 Clock
(Figure 3)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

Isu

Minimum Selup Time, Serial ShifVParaliel Load 10 Clock
(Figure 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

Ih

Minimum Hold Time, Clock 10 A, B, C, D, J, or K
(Figure 3)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

Ih

Minimum Hold Time, Clock 10 Serial ShifVParaliel Load
(Figure 4)

2.0
4.5
6.0

3
3
3

3
3
3

3
3
3

ns

Irec

Minimum Recovery Time, Resellnactive 10 Clock
(Figure 2)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

Iw

Minimum Pulse Widlh, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Iw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tr,tf

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

Parameter

NOTE: InformatIon on typIcal parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-277

MOTOROLA

MC74HC195
PIN DESCRIPTION
DATA INPUTS

J, K (Pins 2, 3)

A, B, C, D (Pins 4, 5, 6, 7)

Shift Control. With Serial Shift/Parallel Load high, J and K
control the mode of operation, as illustrated in the Function
Table.

Parallel data inputs.

OUTPUTS

J=L, K=H

QA, QB, QC, QD, QD (Pins 15, 14, 13, 12, 11)

With a positive .transition of the Clock input, each bit is
shifted to the right (in the direction QA toward QD) one stage
and stage A maintains its previous state.

Parallel data outputs.

CONTROL INPUTS

J=H, K=L

Clock (Pin 10)
Clock input. The shift register is completely static, allowing
Clock rates down to DC in a continuous or intermittent mode.

With a positive transition of the Clock input, each bit is
shifted right (in the direction of QA toward QD) one stage and
the QA output is inverted.

Serial ShiftlParaliel Load (Pin 9)

J=K=L

Shift or load control. A low level applied to this pin allows
data to be loaded from the parallel inputs. Data is loaded with
the positive transition of the Clock input. A high level allows
data to be shifted in the manner dictated by the J and K control inputs.

With a positive transition of the Clock input, each bit is
shifted right (in the direction QA toward QD) one stage and a
low is loaded into stage A.

J=K=H

Reset (Pin 1)

With a positive transition of the Clock input, each bit is
shifted right (in the direction QA toward QD) one stage and a
high is loaded into stage A.

A low level applied to this pin resets all stages and forces
all outputs low.
.

SWITCHING WAVEFORMS

,-------VCC
RESET
-GND
Q

CLOCK

Irec}-

Q

VCC
CLOCK

50%.
-------~

Figure 1.

INPUT
A,B,C,
D,J,ORK

VCC

VCC

SERIAL SHIFT
PARALLEL LOAD

GND

GND
VCC

VCC
CLOCK

CLOCK
-GND

-GND

Figure 4.

Figure 3.

MOTOROLA

-GND

Figure 2.

3-278

High-Speed CMOS Logic Dala
DL129-Rev6

MC74HC195
TEST CIRCUIT
TEST POINT
)

OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 5.

TIMING DIAGRAM
C L O C K .

RESET~~
SERIAL DATA{ J
INPUTS
k

l

SERIAL SHIFT!
PARALLEL LOAD
PARALLEL
DATA
INPUTS

High-Speed CMOS Logic Data
DL129-Rev6

A
B

C

I
I

I

Ij!

rT!

I
~

!!

I
I

!

iI

iI

rnj1L.-+i- - - - - - - -

I
I

I

I

nrhL..--i-------L I
I

L

3-279

I

MOTOROLA

~
~

s:
o

EXPANDED LOGIC DIAGRAM

d

el

SERIAL DATA INPUTS

>

K

o
......

3

CO
01

I

PARALLEL
DATA
INPUTS
D
7

e

B

A
4

SERIAL SHIFT! 9
PARALLEL LOAD

%
~

Vee = PIN 16
GND = PIN8
J:

1[

RESET 1

o

oS:

5@
-co rI

~_

:DO

~

!?

miif

15

00
%

-

PARALLEL DATA OUTPUTS

~
::r

QA
#

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC237

1-of-8 Decoder/Demultiplexer
with Address Latch

rn

High-Performance Silicon-Gate CMOS
The MC74HC237 is identical in pinout to the LS137, but has noninverting
outputs. The device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTIL outputs.
The HC237 decodes a three-bit Address to one-of-eight active-high
outputs. The device has a transparent latch for storage of the Address. Two
Chip Selects, one active-low and one active-high, are provided to facilitate
the demultiplexing, cascading, and chip-selecting functions.
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using one of the Chip
Selects as a data input while holding the other one active.
The HC237 is the noninverting version of the HC137.
•
•
•
•
•
•
•

o SUFFIX
SOIC PACKAGE
CASE 7518-05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

Output Drive Capability: 10 LSTIL Loads
Outputs Directly Interface to CMOS, NMOS, and TIL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 !!A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
N07A
Chip Complexity: 156 FETs or 39 Equivalent Gates

ADDRESS
INPUTS

AO [ 1-

16

A1 [ 2

15

YO

A2 [ 3

14

Y1

LATCH ENABLE [ 4

13

Y2

CS2 [ 5

12

Y3

6

11

Y4

CS1

r

TRANSPAREN
LATCH

A1

14
13

A2

LATCH
ENABLE

12
4

l--OF-8
DECODER

11
10

Plastic
SOIC

PIN ASSIGNMENT

LOGIC DIAGRAM
15

NSUFFIX
PLASTIC PACKAGE
CASE 64B-OB

~

161',YHIIU 1

VCC

YO

Y7

7

10

Y5

Y1

GND

a

9

Y6

L3J

Y2
Y3
Y4

ACTIVEHIGH
OUTPUTS

Y5
Y6

FUNCTION TABLE

Y7
Inputs

6
CHIP" { CS1
SELECT
INPUTS CS2 - ' - - - - - - - - - - - - - '

PIN 16= VCC
PIN a=GND

Outputs

LE CS1 CS2 A2 A1 AD VO V1 V2 V3 V4 V5 V6 Y7
X
X

X
L

H
X

X
X

X
X

X
X

L
L

L
L
L
H
L
L
L
L
L
L

L
L
L
L
H
L
L
L
L
L

L
L
L
L
L
H
L
L
L
L

L
L
L
L
L
L
H
L
L
L

L
L
L
L
L
L
L
H
L
L

L
L
L
L
L
L
L
L
H
L

L
L
L
L
L
L
L
L
L
H

L L L H
L
H
L
L
H
L
L L H L
H
L
L H L L
L
H
L
L H H L
L
L
H
L
H L L L
H
L
H L H L
L
H H L L
H
L
L
H
L
H H H L
L
L
X X X
H H
• = Depends upon the Address previously applied while LE was
at a low level.

10195

© Motorola, Inc. 1995

3-2B1

REV 6

®

.

MOTOROLA

MC74HC237
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Vonage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

mA
mA

lin

DC Input Current, per Pin

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

-65to+ 150

°c

Tstg
TL

Plastic DlPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
,level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

[3]

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC Input Voltage, Output Vonage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme
(Figure 2)

VCC= 2.0 V
VCC=4.5V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

s

85°C

s

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVCc-O.l V
1I0uti s 20 I1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
1I0uti s 20 I1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
12

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
1I0uti s 20 I1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Yin = VIH or VIL 1I0uti
1I0uti
VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20 I1A
Yin = VIH or VIL 1I0uti
1I0uti

lin
ICC

s 4.0 mA
s 5.2 mA

s
s

4.0 mA
5.2 mA

V

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

!LA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 I1A

6.0

8

80

160

I1A

NOTE: Information on typical parametric values can be found In Chapter 2.

MOTOROLA

3-282

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC237
AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

2.0
4.5
6.0

235
47
40

295
59
50

355
71
60

2.0
4.5
6.0

185
37
31

230
46
39

280
56
48

2.0
4.5
6.0

200
40
34

250
50
43

300
60
51

2.0
4.5
6.0

145
29
25

180
36
31

220
44
38

2.0
4.5
6.0

200
40
34

250
50
43

300
60
51

2.0
4.5
6.0

160
32
27

200
40
34

240
48
41

2.0
4.5
6.0

250
50
43

315
63
54

375
75
64

2.0
4.5
6.0

190
38
32

240
48
41

285
57
48

Maximum Output Transition lime, Any Output
(Figures 2 and 6)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol
tpLH

Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 6)

tpHL

tpLH

Maximum Propagation Delay, CS2 to Output Y
(Figures 2 and 6)

tpHL

tpLH

Maximum Propagation Delay, CS1 to Output Y
(Figures 3 and 6)

tpHL

tpLH

Maximum Propagation Delay, Latch Enable to Output Y
(Figures 4 and 6)

tpHL

trLH,
trHL
Cin

$

85°e

$

125°e

Unit
ns

ns

ns

ns

NOTES:
1.· For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee

=5.0 V

100

Power Dissipation Capacitance (Per Package)'

• Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

tsu

Minimum Setup lime, Input A to Latch Enable
(Figure 5)

2.0
4.5
6.0

100
20

th

Minimum Hold lime, Latch Enable to Input A
(Figure 5)

2.0
4.5
6.0

tw

Minimum Pulse Width, Latch Enable
(Figure 4)

tr,tf

Maximum Input Rise and Fall limes
(Figure 2)

Symbol

Parameter

NOTE: Information on tYPical parametnc values can be found

High-Speed CMOS Logic Data
DL129-Rev6

In

$

85°e

$

125°e

Unit

150
30
26

ns

17

125
25
21

50
10
9

65
13
11

75
15
13

ns

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Chapter 2.

3-283

MOTOROLA

MC74HC237
PIN DESCRIPTIONS
ADDRESS INPUTS

Latch Enable (Pin 4)
Latch Enable input. A high level at this input latches the
Address. A low level at this input allows the outputs to follow
the Address (CS1 = Hand CS2 = L).

AD, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is enabled,
determine which of the eight outputs is selected.

OUTPUTS
CONTROL INPUTS

VO-V7 (Pins 15, 14, 13, 12, 11, 10,9,7)
CS1, CS2 (Pins 6, 5)

Active-high outputs. One of these eight outputs is selected
when the chip is enabled (CS1 = Hand CS2 = L) and the
Address inputs correspond to that particular output. The
selected output is at a high level while all others remain at a
low level.

Chip select inputs. For CS1 at a high level and CS2 at a
low level, the chip is enabled and the outputs follOW the data
inputs (Latch Enable = L). For any other combination of CS1
and CS2, the outputs are at a low level.

SWITCHING WAVEFORMS

.p-.---Vcc
CS2

VCC
INPUT A
GND

OUTPUTY

tPL:fo
OUTPUTY
50%

Figure 1.

Figure 2.

-Vcc
CSt

LATCH
ENABLE

I~----GND

OUTPUTY

OUTPUTY
tTHL

Figure 4.

Figure 3.

TEST POINT
OUTPUT

Vcc

DEVICE
UNDER
TEST

GND

-----Vcc
LATCH ENABLE
-GND

• Includes all probe and jig capacitance

Figure 6. Test Circuit

Figure 5.

MOTOROLA

3-284

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC237
EXPANDED LOGIC DIAGRAM

AO 1

A1 2

LATCH
ENABLE
CS1
CS2~5~

________________~

High-Speed CMOS Logic Data
DL129-Rev6

3-285

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Inverting Buffer/
Line Driver/Line Receiver

MC54/74HC240A

High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 732-03

The MC54/74HC240A is identical in pinout to the LS240. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTIL outputs.
This octal noninverting buffer/line driver/line receiver is designed to be
used with 3-state memory address drivers, clock drivers, and other
sub-oriented systems. The device has inverting outputs and two active-low
output enables.
The HC240A is similar in function to the HC241 A and HC244A.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

Output Drive Capability: 15 LSTIL Loads
Outputs Directly Interface to CMOS, NMOS, and TIL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 ~A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 120 FETs or 30 Equivalent Gates

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

20.

DTSUFFIX
TSSOP PACKAGE
CASE 948E-02

1

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXADT

Ceramic
Plastic
SOIC
TSSOP

LOGIC DIAGRAM

[3]

DATA
INPUTS

Al 2

18

A2 4

16

A3 6

14

A4 8

12

Bl
B2
B3

B4

11
13
15
17

OUTPUT { ENABLE A 1
ENABLES ENABLE B 19

YAl

ENABLE A [ 1-

YA2
YA3

INVERTING
OUTPUTS

YB2

19

ENABLE B

YB41 3

18

YAl

17 ~B4

YB31 5

16

A31 6

15

YB21 7

14

A41 8

13

YA2

PB3

PYA3
PB2
12 PYA4
11 PBl

YBll 9

YB3

iJ Vee

20

A1[ 2

A21 4

YA4
YBl

7

PIN ASSIGNMENT

GNDI 10

YB4

FUNCTION TABLE

PIN 20 = Vee
PIN 10 =GND

Inputs
Enable A,
Enable B A,B
L
L
H

L
H
X

Outputs
VA,VB
H
L
Z

Z =high impedance

10/95

© Motorola. Inc. 1995

3-286

REV6

®

MOTOROLA

MC54/74HC240A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

Po

Power Dissipation in StiU Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

-65to+150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND,;; (VinorVout)';; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ralings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mWrC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter

Min

Max

Unit
V

DC Supply Voltage (Referenced to GND)

2.0

6.0

DC Input Voltage, Output Voltage (Referenced to GND)

,0

VCC

V

-55

+125

°c

0
0
0

1000
500
400

ns

TA

Operating Temperature, AU Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VIH

VIL

VOH

Parameter

Test Conditions

,;; 125°C

Unit

1.5
3.15
4.2

1.5
3.15
4.2

V

Vout = 0.1 V
lIoutl ,;; 20 ~A

6.0

1.5
3.15
4.2

Maximum Low-Level Input
Voltage

Vout=VCC-O.l V
lIoutl ,;; 20 ~A

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Vin= VIL
lIoutl ,;; 20 ~A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

6.0

±0.1

±1.0

±1.0

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

High-Speed CMOS Logic Data
DL129-Rev6

~4.5

lIoutl ,;; 6.0 rnA
lIoutl ,;; 7.8 rnA

Vin=VIH
lIoutl';; 20~
Vin =VIH

lin

,;; 85°C

2.0

Minimum High-Level Input
Voltage

Vin=VIL
VOL

VCC
V

-55\0
25°C

lIoutl ,;; 6.0 rnA
lIoutl ,;; 7.8 rnA

Vin = VCC or GND

3-287

V

~

MOTOROLA

MC54174HC240A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25'C

s

s

125'C

Unit

IOZ

Maximum Three-State
Leakage Current

Output in High-Impedance State
Vin =V,L or V,H
Vout =VCC or GND

6.0

±0.5

±5.0

±to

IlA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin =VCC or GND
lout =0!lA

6.0

4

40

160

IlA

VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

NOTE: Information on tYPical parametric values can be found

In

85'C

Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

tpLH,
tPHL

Maximum Propagation Delay, A to VA or B to VB
(Figures 1 and 3)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to VA or VB
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to VA or VB
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-State Output Capacitance (Output in
High-Impedance State)

-

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and Information on typical parametric values, see Chapter 2.
Typical @ 25'C, Vee
POWer Dissipation Capacitance (Per Transceiver Channell'

=5.0 V

32

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-288

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC240A
SWITCHING WAVEFORMS
,..---VCC
ENABLE
-VCC

DATA INPUT
AORB

HIGH
IMPEDANCE

1 " ' " - - - - GND
OUTPUTY

OUTPUT
YAORYB

OUTPUTY
trlH

Figure 2.

Figure 1.

TEST POINT

TEST POINT

1 kn
1-0_U_T_PU_T_+-'VV"v-_

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

':: Cl'

I

CONNECTTO VCC WHEN
TESTING tpLZ AND tPZl·
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH.

I

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 4. Test Circuit

Figure 3. Test Circuit

PIN DESCRIPTIONS
INPUTS

to these pins, the outputs are enabled and the devices function as inverters. When a high level is applied, the outputs
assume the high-impedance state.

A1,A2,A3,A4,B1,B2,B3,B4
(Pins 2, 4, 6, 8,11,13,15,17)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.

OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)

CONTROLS

Device outputs. Depending upon the state of the outputenable pins, these outputs are either inverting outputs or
high-impedance outputs.

Enable A, Enable B (Pins 1, 19)
Output enables (active-low). When a low level is applied

High-Speed CMOS Logic Data
DL129-Rev6

3-289

MOTOROLA

MC54174HC240A
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS

r-------

DATA
INPUT
AORB

I
I
I
I

'

------------------,
ONE OF 8
INVERTERS

Vee

--lI------+----.......-<:1
I
I
I
I
I
I
I
IL

d
J
D------'q

YA
+----'--OR
YB

_____ _

-------------------~

ENABLE A
OR ENABLEB

MOTOROLA

3-290

High-Speed CMOS Logic Data

DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Inverting Buffer/
Line Driver/Line Receiver with
LSTTL-Compatible Inputs

MC74HCT240A
NsUFFIX
PLASTIC PACKAGE
CASE 738-03

High-Performance Silicon-Gate CMOS
The MC74HCT240A is identical in pinout to the LS240. This device may
be used as a level converter for interfacing TTL or NMOS outputs to
High-Speed CMOS inputs. The HCT240A is an octal inverting buffer line
driver line receiver designed to be used with 3-state memory address
drivers, clock drivers, and other bus-oriented systems. The device has
inverting outputs and two active-low output enables.
The HCT240A is the inverting version of the HCT244. See also HCT241.

20~

OW SUFFIX
SOIC PACKAGE
CASE 7510-04

20.

sDsUFFIX
SSOP PACKAGE
CASE 940c-{)3

1

1

•
•
•
•
•
•

Output Drive Capability: 15 LSTTL Loads
TTL NMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 !lA
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
• Chip Complexity: 110 FETs or 27.5 Equivalent Gates

oTsUFFIX
TSSOP PACKAGE
CASE 948E-02

20'.'
1

ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXADW
MC74HCTXXXASD
MC74HCTXXXADT

Plastic
SOIC
SSOP
TSSOP

LOGIC DIAGRAM

18
16
14

PIN ASSIGNMENT

VAl

ENABLE A
VA2

Vee
ENABLE B

Al

VA3

VB4

VAl

VB3

VA2

B4
12
DATA INPUTS
Bl
B2
B3
B4

11

9

13

7

15

5

17

3

VM
VBl

INVERTING
OUTPUTS

A3

VB2
VB3

B3

VB2

VA3

A4

B2

VBl

VM

GND

Bl

VB4
FUNCTION TABLE

OUTPUT { ENABLE A 1
ENABLES ENABLE B 19

PIN 20: Vee
PIN 10:GND

Outputs

Inputs
Enable A,
Enable B

L
L
H

A,B

VA,VB

L
H

H
L
Z

X

Z = High Impedance
X = Don't Care

10/95

© Motorola. Inc. 1995

3--291

REVS

®

MOTOROLA

MC74HCT240A
MAXIMUM RATINGS'
Symbol

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

mA

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air

750
500
450

mW

-65to+150

°C

VCC
Vin
Vout
lin

Tsig
TL

Parameter
DC Supply Voltage (Referenced to GND)

Plastic DIPt
SOIC Packaget
TSSOP or SSOP Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, TSSOP or SSOP Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP or SSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol

VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

t r, tf

Input Rise and Fall Time (Figure 1)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

°C

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

s 85°C

S" 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout 0.1 Vor VCC - 0.1 V
"outl S 20 J!A

4.5
5.5

2
2

2
2

2
2

V

VIL

Maximum Low-Level Input
Voltage

Vo ut=0.1 VorVCc-0.1 V
"outl S 20 J!A

4.5
5.5

0.8
0.8

0.8
0.8

0.8
O.B

V

Minimum High-Level Output
Voltage

Vin V,H or VIL
"outl S 20 J!A

4.5
5.5

4.4
5.4

4.4
5.4

44
5.4

V

4.5

3.98

3.84

3.7

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Symbol

VOH

Test Conditions

Parameter

=

=
=

Vin V,H or V,L
"outl S 6 mA

VOL

Maximum Low-Level Output
Voltage

=

Vin VIH or VIL
"outl S 20 J!A

V

=

Vin VIH or VIL
"outl S 6 mA

=VCC or GND

lin

Maximum Input Leakage Current

Vin

10Z

Maximum Three State
Leakage Current

Output in High-Impedance State
Vin VIL or VIH
Vout VCC or GND

MOTOROLA

=
=

3-292

4.5

0.26

0.33

0.4

5.5

±0.1

±1.0

± 1.0

J!A

5.5

±0.5

±5.0

±10

J!A

High-Speed CMOS Logic Data
DL129-Rev6

MC?4HCT240A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
ICC

~ICC

I

Parameter
Maximum Quiescent Supply
Current (per Package)

I

Additional Quiescent Supply
Current

Test Conditions

VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

5.5

4

40

160

IlA

Vin = VCC or GND
lout = 0 IlA
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 IlA

I

5.5

I
I

----lq

OUTPUT ENABLES
ENABLE A OR ENABLE B

MOTOROLA

3-294

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver

MC54/74HC241 A
J SUFFIX
CERAMIC PACKAGE
CASE 732-03

High-Performance Silicon-Gate CMOS
The MC54n4HC241 A is identical in pinout to the LS241. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTIL outputs.
This octal non inverting buffer/line driver/line receiver is designed to be
used with 3-state memory address drivers, clock drivers, and other
sukH)riented systems. The device has non inverted outputs and two output
enables. Enable A is active-low and Enable B is active-high.
The HC241 A is similar in function to the HC244A and HC240A.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

20.-

Output Drive Capability: 15 LSTIL Loads
Outputs Directly Interface to CMOS, NMOS, and TIL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 !1A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 134 FETs or 33.5 Equivalent Gates

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

1

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW

Ceramic
Plastic
SOIC

LOGIC DIAGRAM
A1 2

18

A2 4

16

A3 6

14
12

A4
DATA
INPUTS

B1
B2
B3

11

9

13

7

15

B4 17

OUTPUT { ENABLE A 1
ENABLES ENABLE B 19

YA1
YA2
YA3
YA4
YB1

NONINVERTING
OUTPUTS

YB2

FUNCTION TABLE

YB3
3

Inputs

YB4

Enable
A
A
L
L
H

PIN 20 = Vee
PIN 1o=GND
Z

3-295

Inputs

VA

Enable
B
B

L
H
Z

H
H
L

Output

L
H
X

VB
L
H
Z

=high impedance

10195

© Motorola, Inc. 1995

L
H
X

Output

REV 6

®

MOTOROLA

MC54174HC241 A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to"" 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lin
lout

DC Output Current, per Pin

±35

mA

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DlPt
SOIC Packaget

750
500

mW

-65 to + 150

'c
'c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
,
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 1'25

'c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=VCC-O.l V
lIoutl s 20~

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 V
lIoutl s 20~

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Vin=VIH
lIoutl s 20llA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

6.0

±0.1

± 1.0

±1.0

Symbol

VOH

Parameter

Test Conditions

Vin=VIH
VOL

Maximum Low-Level Output
Voltage

Yin =VIL
lIoutl S 20llA
Vin=VIL

lin

MOTOROLA

Maximum Input Leakage Current

lIoutl s 6.0 rnA
lIoutl S 7.8 rnA

lIoutl S 6.0 rnA
lIoutl S 7.8 rnA

Yin = VCC or GND

3-296

V

IlA

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC241 A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

10Z

Maximum Three-State
leakage Current

ICC

Maximum Quiescent Supply
Current (per Package)

Test Conditions
Output in High-Impedance State
Vin Vil or VIH
Vout VCC or GND

=
=
Vin =VCC or GND
lout =0 IlA

Vee
V

-55to
25'e

s 85'e

s 125°C

Unit

6.0

±0.5

±5.0

±10

Il A

6.0

4

40

160

Il A

NOTE: InformallOn on typical parametric values along with high frequency or heavy load considerations, can be found In Chapter 2.
AC ELECTRICAL CHARACTERISTICS (Cl

=50 pF, Input tr =tf =6 ns)
Guaranteed Limit

Symbol

Vee
V

-55to
25'e

s 85'e

s125°e

Unit

tplH,
tpHl

Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)

2.0
4.5
6.0

90
18
15

115
23
20

135
27
23

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

tpZl,
tpZH

Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

ITlH,
ITHl

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-8tate Output Capacitance (Output in
High-Impedance State)

-

15

15

15

pF

Parameter

NOTE: For propagation delays with loads other than 50 pF, and information on tYPical parametric values, see Chapter 2.
Typical @ 25°C, Vee
Power Dissipation Capacitance (Per Transceiver Channel),

=5.0 V

34

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
Dl129-Rev6

3-297

MOTOROLA

MC54174HC241 A
SWITCHING WAVEFORMS
,----VCC
ENABLE A

tr
-VCC

DATA INPUT
AORB

ENABLEB

'----GND

I~----GND

HIGH
IMPEDANCE

tpLH
OUTPUT
YA OR YB

OUTPUTY
trHL
OUTPUTY

Figure 1.

Figure 2.

TEST POINT

TEST POINT

1 kQ
I-0.;..U;:..;T.;..PU.;..T~+-"I\i"v-_

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

r

•Y

CL

I

CONNECTTO VCC WHEN
TESTING tpLZ AND tpZL.
CONNECTTO GND WHEN
TESTING tPHZ AND tpZH·

'

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 3. Test Circuit

Figure 4. Test Circuit

PIN DESCRIPTIONS
INPUTS

Enable 8 (Pin 19)

A1,A2,A3,A4,B1,B2,B3,B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Output enable (active-high). When a high level is applied
to this pin, the outputs of the "B" devices are enabled and the
devices function as noninverting buffers. When a low level is
applied, the outputs assume the high-impedance state.

Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs when the outputs are
enabled.

OUTPUTS
CONTROLS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Enable A (Pin 1)
Output enable (active-low). When a low level is applied to
this pin, the outputs of the "A" devices are enabled and the
devices function as noninverting buffers. When a high level is
applied, the outputs assume the high-impedance state.

MOTOROLA

Device outputs. Depending upon the state of the outputenable pins, these outputs are either noninverting outputs or
high-impedance outputs.

3-298

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC241A
LOGIC DETAIL
TO THREE OTHER
"A" BUFFERS

TO THREE OTHER
"B" BUFFERS

-----------------,
TWO OF 8 BUFFERS
Vee

r------DATA
INPUT
A

I

d
J.
D------'q

---+--VA

DATA
INPUT
B

~

J.
D------'q

----r-- VB

L_______

__

_ _________________

~

f31,

1

OUTPUT
ENABLES

ENABLE A

~

ENABLE B

High-Speed CMOS Logic Data
DL129-Rev6

3-299

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver with
LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS

IMC54/74HCT241A I
20

~

n"'\MMi1f] UUU
1

The MC54174HCT241A is identical in pinout to the LS241. This device
may be used as a level converter for interfacing TIL or NMOS outputs to
High-Speed CMOS inputs. The HCT241 A is an octal non inverting buffer/line
driverlline receiver designed to be used with 3-state memory address
drivers, clock drivers, and other bus-oriented systems. The device has
non-inverted outputs and two output enables. Enable A is active-low and
Enable B is active-high.
The HCT241 A is similar in function to the HCT244. See also HCT240.

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

DWSUFFIX
SOIC PACKAGE
CASE 751 0-04

Output Drive Capability: 15 LSTIL Loads
TIUNMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TIL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 IlA
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 118 FETs or 29.5 Equivalent Gates

•
•
•
•
•
•

ORDERING INFORMATION
MC54HCTXXXAJ
MC74HCTXXXAN
MC74HCTXXXAOW

LOGIC DIAGRAM
18

A2 4

16

A3 6

14

A4 8

12

YAl
YA2
YA3
YA4

DATA INPUTS
Bl 11

YBl

B2 13

7 YB2

B3 15

5 YB3

B4 17

OUTPUT { ENABLE A 1
ENABLES ENABLE B 19

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
ENABLE A

Al 2

JSUFFIX
CERAMIC PACKAGE
CASE 732-03

NONINVERTING
OUTPUTS

PVee
PENABLE B
18 PYAl
17 PB4
16 PYA2
15 PB3
14 PYA3
13 PB2
12 PYA4
11 PBl

1-

20

Al

2

19

YB4

3

A2

4

YB3

5

A3

6

YB2

7

A4

8

YBl[ 9
GND [ 10

FUNCTION TABLE
Inputs
Enable A

YB4

L
L
H

PIN 20~ Vee
PIN 10~ GND

Output
A

VA

L
H
X

L
H
Z

Inputs
EnableB
H
H
L

Output
B

VB

L
H
X

L
H
Z

Z = high impedance
X = don't care

10195

© Motorola, Inc. 1995

3-300

REV 6

®

MOTOROI.A

MC54174HCT241 A
MAXIMUM RATINGS'
Symbol
VCC
Vin
Vout
lin

Parameter

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

mA
mA

DC Supply Voltage (Referenced to GND)

DC Input Current, per Pin

lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

mA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ,; (Vin or Vout) ,; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mWI'C from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mWI'C from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

4.5

5.5

V

0

VCC

V

-55

+ 125

°C

0

500

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

Unit

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

-55to
25°C

,; 85°C

,; 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
"outl ,; 20 JJA

4.5
5.5

2
2

2
2

2
2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.l VorVcc-O.l V
"outl ,; 20 JJA

4.5
5.5

0.8
0.8

0.8
0.8

08
0.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
floutl ,; 20 IIA

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

Vin = VIH or VIL
"outl ,; 6 mA

4.5

3.98

3.84

3.7

Vin = VIH or VIL
floutl ,; 20 IIA

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

VOH

VOL

Parameter

VCC
V

Maximum Low-Level Output
Voltage

Test Conditions

V

Vin = VIH or VIL
floutl ,; 6 mA

4.5

0.26

0.33

0.4

Maximum Input Leakage Current

Vin = VCC or GND

5.5

±0.1

±1.0

±1.0

IOZ

Maximum Three-State
Leakage Current

Output in High-Impedance State
Vin = VIL or VIH
Vout = VCC or GND

5.5

±0.5

±5.0

±10

JJA
JJA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 JJA

5.5

4

40

160

JJA

dlCC

Additional Quiescent Supply
Current

Vin - 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 JJA

lin

,,-55°C
5.5

2.9

125°C to 125°C

I

2.4

mA

NOTES:
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2.
2. Total Supply Current = ICC + MICC.

High-Speed CMOS Logic Data
DL129-Rev6

3-301

MOTOROLA

MC54/74HCT241 A
AC ELECTRICAL CHARACTERISTICS (VCC

=5.0 V ± 10%, CL =50 pF, Inpu1 Ir =If =6 ns)
Guaranteed Limit
-55 to
25°e

s 85°e

s 125°e

Unit

IpLH,
IpHL

Maximum Propagalion Delay, A to VA or B 10 VB
(Figures 1 and 3)

23

29

35

ns

IpLZ,
IpHZ

Maximum Propagalion Delay, Output Enable to VA or VB
(Figures 2 and 4)

30

38

45

ns

IpZL,
tpZH

Maximum Propagation D~lay, Output Enable to VA or VB
(Figures 2 and 4)

26

33

39

ns

lTLH,
lTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

12

15

18

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three-State Output Capacitance (Output in High-Impedance
State)

15

15

15

pF

Symbol

Parameter

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical

@

25°e, Vee

Power Dissipation Capacitance (Per Enabled Output)'

=5.0 V

55

'Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
,..,---3V
ENABLE A

ENABLEB

tr

'----GND

~3V

INPUT
AORB

HIGH
IMPEDANCE

1 1 ' - - - - - GND
OUTPUTY

tPLH
OUTPUT
YAOR YB
trHL

OUTPUTY

Figure 1.

Figure 2.

TEST POINT

TEST POINT
1 lin
1-0_U;..T_PU_T_+-'VV'Ir-_

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

, Includes all probe and jig capacitance

CL'

CONNECTTOVCCWHEN
TESTING tpLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tpHZ AND tpZH·

I
'Includes all probe and jig capacitance

Figure 3. Test Circuit

MOTOROLA

..

I

Figure 4. Test Circuit

3-302

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HCT241 A
LOGIC DETAIL
TO THREE OTHER
"A" BUFFERS

r------INPUT

I

TO THREE OTHER
"B" BUFFERS

-----------------,
TWO OF 8 BUFFERS
Vee

J
J.
D---'q

A

---+--VA

J~. .

INPUT
B

---i--VB

D---'q
1.. _ _ _ _ _ _ _

I

OUTPUT
ENABLES

ENABLEA

ENABLE B

High-Speed CMOS Logic Data
DL129-Rev6

3-303

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC242

Quad 3-State Bus Transceiver
High-Performance Silicon-Gate CMOS
The MC74HC242 is identical in pinout to the LS242. The device inputs
are compatible with Standard CMOS outputs; with puliup resistors, they
are compatible with LSTTL outputs.

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

This quad bus transceiver is designed for asynchronous two-way
communications between data buses. The states of the Output Enables
(A-to-B Enable and B-to-A Enable) determine both the direction of data
flow (from A to B or from B to A) and the modes of the Data Ports (input,
output, or high-impedance).

ORDERING INFORMATION
MC74HCXXXN

Plastic

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL

FUNCTION TABLE

• Operating Voltage Range: 2 to 6V

Control Inputs

• Low Input Current: lilA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements

A-to-8
Enable

8-to-A
Enable

H
L
H
L

H
H
L
L

• Chip Complexity: 130 FETs or 32.5 Equivalent Gates

LOGIC DIAGRAM

[3]

A1

AOata
Port

A2
A3

A4

Output
[
EnableS

3

11

4

10

5

9

6

8

O-BENABLE~

A-T

B-TO-AENABLE

13

Data Port Status
A

8

0

I
Z
Z

Z
Z
I

I =Input; 0 =Output. 0
Z = High Impedance

0

=Inverting Output

B1
B2

BOala
Port

B3
B4

Pin 14=VCC
Pin 7= GNO
Pins 2,12 = No Connection

Pinout: 14-Lead Plastic Package (Top View)

A-to-B
Enable

A1
NC = No Connection

10195

© Motorola, Inc. 1995

3-304

REV6

®

MOTOROLA

MC74HC242
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

- 0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

VI/O

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

1110

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

Po

Power Dissipation in Still Air

Tstg

Storage Temperature

TL

±75

rnA

750

mW

-65to+150

DC

Plastic DIPt

DC

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP Package

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND " (Vin orVout) " VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/DC from 65 0 to 125 DC
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter

Min

DC Supply Voltage (Referenced to GND)

Max

Unit

2.0

6.0

.V

0

VCC

V

-55

+ 125

DC

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature Range, All Package Types

tr,tf

Input Rise/Fall Time
(Figure 1)

VCC =.2.0V
VCC =4.5 V
VCC=6.0V

DC CHARACTERISTICS (Voltages Referenced to GND)
-55 to 25 DC

"S5 DC

,,125DC

Unit

Vout= O.lV orVcc-O.1V
lI outl ,,20!LA

2.0
4.5
6.0

1.50
3.15
4.20

1.50
3.15
4.20

1.50
3.15
4.20

V

Maximum Low-Level Input Voltage

Vout = O.lV or VCC - O.lV
lIoutl " 20!LA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl " 20!LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Parameter

VIH

Minimum High-Level Input Voltage

VIL

VOH

Condition

Vin =VIH or VIL
VOL

Guaranteed Limit

VCC
V

Symbol

Maximum Low-Level Output
Voltage

lIoutl " 6.OmA
lIoutl "7.8mA

Vin = VIH or VIL
lI ou tl ,,20!LA
Vin = VIH or VIL

lIoutl " 6.OmA
lIoutl "7.8mA

V

lin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

!LA

10Z

Maximum Three-State Leakage
Current

Output in High-Impedance State
Vin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10.0

!LA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = O!LA

6.0

8

80

160

!LA

NOTE: Informallon on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-305

MOTOROLA

MC74HC242
AC CHARACTERISTICS (Cl =50 pF. Inputtr =tf =6 ns)
Guaranteed Limit

Vee
V

-55 to 25°e

~85°e

~125°e

Unit

tplH.
tpHl

Maximum Propagation Delay. A to B or B to A
(Figures 2 and 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tpLZ.
tpHZ

Maximum Propagation Delay. Output Enable to Output A or B
\Figures 3 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpZl.
tpZH

Maximum Propagation Delay. Output Enable to Output A or B
(Figures 3 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

trlH.
trHl

Maximum Output Transition Time. Any Output
(Figures 2 and 4)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Symbol

Cin
Cout

Parameter

Maximum Input Capacitance

10

10

10

pF

Maximum Three-State Output Capacitance (Output in High Impedance
State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF. and information on typical parametric values. see Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Transceiver)*

=5.0 V

31

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations. see Chapter 2.

PIN DESCRIPTIONS
DATA PORTS

CONTROL INPUTS

A1-A4 (Pins 3,4,5,6) and B1-B4 (Pins 11,10,9,8)

A-to-B Enable (Pin 1) and B-to-A Enable (Pin 13) .

Data on these pins may be transferred between data
Output Enables,
buses. Depending upon the states of
these pins may be inputs. outputs or open circuits (high-impedance).

Data on these Output Enables determine both the direction of the data flow (from A to B or from B to A) and the
states of the outputs (standard or high impedance). according to the Function Table.

the

MOTOROLA

3-306

High-Speed CMOS logic Data
D1129-Rev6

MC74HC242

A(110) - ; - - . , - - - - - - - - - - ; - - i

+--+--+--------_-+-B(I/O)

L ____________ _

A-to-B 1
Enable

B-to-A 13
Enable

Figure 1. Expanded Logic Diagram

SWITCHING WAVEFORMS
r - - - - VCC
VCC

GND
High
Impedance

-""-----GND

VOL
VOH
High
Impedance

Figure 2.

Figure 3.

TEST CIRCUITS
TEST
POINT

TEST
POINT

OUTPUT

OUTPUT

DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

'Includes all probe and jig capacitance

,

CONNECT TO VCC WHEN
[ TESTING tPLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tpHZ and tpZH.

'Includes all probe and jig capacitance

Figure 5.

Figure 4.

High-Speed CMOS Logic Data
DL129-Rev6

.

1~

3-307

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver

MC54/74HC244A
J SUFFIX
CERAMIC PACKAGE
CASE 732-03

High-Performance Silicon-Gate CMOS
The MC54174HC244A is identical in pinout to the LS244. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This octal non inverting bufferlline driverlline receiver is designed to be
used with 3-state memory address drivers, clock drivers, and other
bus-oriented systems. The device has noninverting outputs and two
active-low output enables.
The HC244A is similar in function to the HC240A and HC241A.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 73B-{)3

20.
20.
20"

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

1

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 /!A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
'
Chip Complexity: 136 FETs or 34 Equivalent Gates

SDSUFFIX
SSOP PACKAGE
CASE 940C-03
DTSUFFIX
TSSOP PACKAGE
CASE 94BE-02

1

ORDERING INFORMATION
MC54HCXXXAJ
Ceramic
MC74HCXXXAN
Plastic
MC74HCXXXADW
SOIC
MC74HCXXXASD
SSOP
MC74HCXXXADT
TSSOP

LOGIC DIAGRAM

A1
A2

2

18

4

16
14

A3
A4 8
DATA
INPUTS

B1
B2
B3
B4

12

11
13

ENABLE A
YA2

15

5

17

3

Vee

A1

ENABLE B

YA3

YB4

YA1

A2

B4

YA4

YB3

YA2

YB1
7

PIN ASSIGNMENT

YA1

NON INVERTING
OUTPUTS

B3
YA3
A4

YB2
YB3

B2

YB1

YA4

GND

B1

YB4

FUNCTION TABLE

OUTPUT { ENABLE A 1
ENABLES ENABLE B 19

PIN 20= Vee
PIN 10=GND

Inputs
Enable A,
EnableB A,B'
L
L
H

L
H
X

Outputs
VA,VB
L
H
Z

Z =high impedance

10195

© Motorola, Inc, 1995

3-30B'

REV 6

®

MOTOROLA

MC54/74HC244A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to+ 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

- 1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lin
lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
SSOP or TSSOP Packaget

750
500
450

mW

-65to+150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: - 10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
SSOP or TSSOP Package: - 6.1 mWfOC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

2.0

6.0

Unit
V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

VCC
V

-55to
25°C

:5 85°C

:5 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=VCC-0.1 V
lIoutl :5 20 flA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 V
lIoutl :5 20 flA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Vin=VIH
lIoutl :5 20 flA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

6.0

±0.1

±1.0

±1.0

VOH

Parameter

Test Conditions

Yin =VIH
VOL

Maximum Low-Level Output
Voltage

Vin = VIL
lIoutl :5 20 flA
Vin=VIL

lin

Maximum Input Leakage Current

High-Speed CMOS Logic Data
DL129-Rev6

Iioutl :5 6.0 rnA
lIoutl :5 7.8 rnA

lIoutl :5 6.0 rnA
lIoutl :5 7.8 rnA

Yin = VCC or GND

3-309

V

flA

MOTOROLA

MC54174HC244A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

IOZ

Maximum Three-8tate
Leakage Current

Output in High-Impedance State
Vin =VIL or VIH
Vout =VCC or GND

6.0

±0.5

±5.0

±10

IlA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin =VCC or GND
lout =0 I!A

6.0

4

40

160

IlA

NOTE: Information on tYPical parametric values and high frequency or heavy load considerations can be found In Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Symbol

Parameter

VCC
V

-55to
25'C

s85'C

s125'C

Unit

tPLH,
tpHL

Maximum Propagation Delay, A to VA or B to VB
(Figures 1 and 3)

2.0
4.5
6.0

96
18
15

115
23
20

135
27
23

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to VA or VB
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to VA or VB
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-State Output Capacitance (Output in
High-Impedance State)

-

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25'C, VCC
Power Dissipation Capacitance (Per Buffer»
>

=5.0 V

34

Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS

,----vcc

-Vcc

DATA INPUT
AORB

ENABLE
AORB

1 1 ' - - - - - GND

HIGH
IMPEDANCE

tPLH

OUTPUT
YAORYB

OUTPUTY

OUTPUTY

Figure 1.

MOTOROLA

Figure 2.

3-310

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC244A
TEST CIRCUITS
TEST POINT

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

1 lin

I

CONNECTTO VCC WHEN
TESTING tPLZ AND tpZL·
CONNECT TO GND WHEN
TESTING tpHZ AND tpZH.

• tncludes all probe and jig capacitance

Figure 3. Test Circuit

Figure 4. Test Circuit

PIN DESCRIPTIONS
to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the
outputs assume the high impedance state.

INPUTS
A1,A2,A3,A4,B1,B2,B3,B4
(Pins 2, 4, 6, 8,11,13,15,17)
Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs, when the outputs are
enabled.

OUTPUTS
YA1,YA2, YA3,YA4,YB1,YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)

CONTROLS

Device outputs. Depending upon the state of the outputenable pins, these outputs are either noninverting outputs or
high-impedance outputs.

Enable A, Enable B (Pins 1, 19)
Output enables (active-low). When a low level is applied

LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS

r------I
I

------------------,
ONE OF 8
INVERTERS

I

VCC

DATA
I
INPUT - - " ' - - - I
AORB
I

dJ
P-----'q

I
I
I

YA

t---7"--OR

I
I
I

YB

I1... _ _ _ _ _ _
ENABLEAOR
ENABLE B

High-Speed CMOS Logic Data
D1129-Rev6

3-'311

MOTOROLA

[j]
3

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver with
LSTTL-Compatible Inputs

IMC54/74HCT244A I
J SUFFIX

CERAMIC PACKAGE
CASE 732-Q3

High-Performance Silicon-Gate CMOS
N SUFFIX

The MC54174HCT244A is identical in pinout to the LS244. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High-Speed CMOS inputs. The HCT244A is an octal noninverting buffer
line driver line receiver designed to be used with 3-state memory address
drivers, clock drivers, and other bus-oriented systems. The device has
non-inverted outputs and two active-low output enables.
The HCT244A is the non inverting version of the HCT240. See also
HCT241.
•
•
•
•
•
•

Output Drive Capability: 15 LSTTL Loads
TTL NMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 ~
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 112 FETs or 28 Equivalent Gates

PLASTIC PACKAGE
CASE 73B-03
DWSUFFIX

20#-

SOIC PACKAGE
CASE 751O-Q4

1

SD SUFFIX

20.

SSOP PACKAGE
CASE 940G-03

1

DTSUFFIX

20.

TSSOP PACKAGE.
CASE 948E-Q2

1

ORDERING INFORMATION

MC54HCTXXXAJ
MC74HCTXXXAN
MC74HCTXXXADW
MC74HCTXXXASD
MC74HCTXXXADT

Ceramic
Plastic
SOIC
SSOP
TSSOP

LOGIC DIAGRAM
PIN ASSIGNMENT
18
16
14
12
DATA INPUTS
Bl
B2

11
13

ENABLE A I 1-

YA3
YA4
NON INVERTING
OUTPUTS

YB2
5

B4 17

3

19

PVee
PENABLE B

PYAl

20

All 2

YA2

9 YBl

15

B3

YAl

YB4

3

18

A2

4

17

YB3

5

A3

6

YB2

7

A4

8

YBl

9

GND

10

PB4
16 PYA2
15 PB3
14 PYA3
13 PB2
12 PYA4
11 PBl

YB3
YB4

FUNCTION TABLE
Inputs

OUTPUT { ENABLE A 1
ENABLES ENABLE B 19

Enable A,
EnableB

PIN20= Vee
PIN 10=GND

L
L
H

Outputs

A,B

VA, VB

L
H
X

L
H
Z

Z = high impedance
X = don't care

10195

© Molorola. Inc. 1995

3-312

REV6

®

MOTOROLA

MC54/74HCT244A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5toVCC+1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lin
lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
SSOP or TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

-65to+150

QC

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

QC
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/QC from 65 Qto 125 QC
Ceramic DIP: -10 mW/QC from 100 Qto 125 QC
SOIC Package: -7 mWfOC from 65 Qto 125 QC
SSOP or TSSOP Package: -6.1 mW/QC from 65 Qto 125 QC
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

QC

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25 QC

:5 85 QC

:5 125 QC

Unit

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
1I0uti :5 20 !LA

4.5
5.5

2
2

2
2

2
2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
1I0uti :5 20 !LA

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
1I0uti :5 20 !LA

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

Vin = VIH or VIL
1I0uti :5 6 mA

4.5

3.98

3.84

3.7

Vin = VIH or VIL
lIoutl :5 20 !LA

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Vin = VIH or VIL
lIoutl :5 6 mA

4.5

0.26

0.33

0.4

Vin = VCC or GND

5.5

±0.1

±1.0

±1.0

Symbol

VOH

VOL

lin

Parameter

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

High-Speed CMOS Logic Data
DL129-Rev6

Test Conditions

3-313

V

!LA

MOTOROLA

MC54n4HCT244A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

IOZ

Maximum Three-State
Leakage Current

Output in High-Impedance State
Vin = VIL or VIH
Vout = VCC or GND

5.5

±0.5

±5.0

±10

/lA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
10ut=0/lA

5.5

4

40

160

J.LA

&ICC

Additional Quiescent Supply
Current

Vin = 2.4 V, Any One Input
Vln = VCC or GND, Other Inputs
lout = 0 /lA

Symbol

Parameter

Test Conditions

;::-55°C

25°C to 125°C

2.9

2.4

5.5

mA

NOTES:
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2.
2. Total Supply Current = ICC + UICC.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

-55to
25°C

Parameter

s

85°C

s

125°C

Unit

tPLH,
tpHL

Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)

20

25

30

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)

26

33

39

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)

22

28

33

ns

'TLH,
'THL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

12

15

18

ns

Maximum Input Capacitance

10

10

10

pF

Maximum Three-State Output Capacitance (Output in High-Impedance
State)

15

15

15

pF

Cin
Cout

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°C, VCC = 5.0 V
Power Dissipation Capacitance (Per Enabled Output)*

55

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC Vec. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
~--3V

ENABLE
AORB

tr

-3V

INPUT
AORB

HIGH

11'--'---- GND

IMPEDANCE

tpLH

OUTPUTY

OUTPUT
YA OR YB

OUTPUTY
tTHL

Figure 1.

MOTOROLA

Figure 2.

3-314

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HCT244A
TEST CIRCUITS
TEST POINT

I

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

CONNECT TO VCC WHEN
TESTING tPLZ AND ipZL.
CONNECT TO GND WHEN
TESTING tpHZ AND tpZH.

1 kQ

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 3.

Figure 4.

LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS

r------1

------------------,
ONEOF8
BUFFERS

I
I
I

VCC

DATA INPUT
AOR B --"1---1

d
J
P-----'q

1
1
1
1
1

YA

+--~--OR

I

YB

1
L.. _ _ _ _ _ _

ENABLE A OR ENABLE B

High-Speed CMOS Logic Data
DL129-Rev6

3-315

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

.[ MC54/74HC245A

Octal 3-State Noninverting
Bus Transceiver
High-:-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 732-{J3

The MC54174HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC245A is a 3-state noninverting transceiver that is used for 2-way
asynchronous communication between data buses. The device has an
active-low Output Enable pin, which is used to place the I/O ports into
high-impedance states. The Direction control determines whether data
flows from A to B or from B to A.

N SUFFIX
PLASTIC PACKAGE
CASE 731Hl3

20.

•
•
•
•
•
•

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 308 FETs or 77 Equivalent Gates

1

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW

LOGIC DIAGRAM
Al

A2
A3
A
DATA
PORT

A6
A7

AS

18

3

17

4

16

5

15
14

7

13

8

12

9

11

1
DIRECTION
19
OUTPUT ENABLE

I

Ceramic
Plastic
SOIC

PIN ASSIGNMENT

2

A4
6
AS

OW SUFFIX
SOIC PACKAGE
CASE 7510-04

DIRECTION [ Ie

Bl
B2
B3
B4

B5

B
DATA
PORT

B6
B7

BB

I

20

pVCC

A2[ 3

POUTPUT ENABLE
18 PBl

A3 [ 4

17 ~ B2

A4[ 5

16

A5 [ 6

15

AS [ 7

14 ~ B5

A7[ 8

13

B6

AS[ 9

12

B7

GND[ 10

11

B8

Al [ 2

19

PB3
PB4

PIN 10~GND
PIN20~VCC

FUNCTION TABLE
Control Inputs
Output
Enable

Direction

L

L

Data Transmitted from Bus B to Bus A

L

H

Data Transmitted from Bus A to Bus B

H

X

Buses Isolated (High-Impedance State)

Operation

X = don't care

10195

© Motorola, Inc. 1995

3-316

REV6

®

MOTOROLA

MC54n 4HC245A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5toVCC+l.5

VIIO

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA
mA

11/0

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

mA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

TL

-65to+150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,;; (Vin or Vout) ,;; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
°c

260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC;2.0V
VCC;4.5V
VCC; 6.0 V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

-55to
25°C

,;; 85°C

,;; 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout;O.l VorVCC-O.l V
Iioutl';; 20~

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout; 0.1 V or VCC - 0.1 V
lIoutl ,;; 20 itA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Vir. ; VIH or VIL
lIoutl s 20 itA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin ; VIH or VIL lIoutl ,;; 6.0 rnA
lIoutl ,;; 7.8 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin ; VIH or VIL
lIoutl ,;; 20 itA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin ; VIH or VIL lIoutl ,;; 6.0 rnA
lIoutl ,;; 7.8 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

VOL

Parameter

VCC
V

Maximum Low-Level Output
Voltage

Test Conditions

V

Maximum Input Leakage Current

Vin; VCC or GND, Pin lor 19

6.0

±0.1

±1.0

±1.0

itA

10Z

Maximum Three-State
Leakage Current

Output in High-Impedance State
Vin =VIL or VIH
Vout =VCC or GND, 1/0 Pins

6.0

±0.5

±5.0

±10

itA

ICC

Maximum Quiescent Supply
Current (per Package)

Yin =VCC or GND
lout =0 itA

6.0

4

40

160

~

lin

NOTE: Informalion on tYPical parametrrc values and high frequency or heavy load considerations can be found rn Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-317

MOTOROLA

MC54174HC245A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vce
V

-55to
25°C

oS

"

85°e

oS

125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, A to B, B to A
(Figures 1 and 3)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

I,ls

tpLZ,
tpHZ

Maximum propagation Delay, Direction or Output Enable to A or B
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

_ 140
28
24

165
33
28

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to A or B
(Figures 2 and 4)

2.0
4.5
6.0

110
22
19

140
28
24

165
33
28

ns

tTLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

60
12
'10

75
15
13

90
18
15

ns

Cin

Maximum Input Capacitance (Pin 1 or Pin 19)

-

10

10

,10

- pF

Cout

Maximum Three-State 1/0 Capacitance
(1/0 in High-Impedance State)

-

15

15

15

pF

-'

NOTE: For propagation delays with loads other than 50 pF, and mformatlon on typical parametric values, see Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Transceiver Channel),

=5.0 V

40

• Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS

-v
DIRECTION

,...---VCC
GND

~'--_ _ _ _ _150%

r,----VCC
OUTPUT
ENABLE

Ir
-VCC

INPUT
AORB

HIGH
IMPEDANCE

11'-----GND
IpLH

AORB

OUTPUT
BORA
AORB
trHL

Figure 1.

Figure 2.

TEST CIRCUITS
TEST POINT

TEST POINT

1 kil
I-0.;;,.U;;.;T.;..P.;..UT~+-'V\i'\r-_

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

• Includes all probe and jig capacHance

I

CL'

CONNECT TO VCC WHEN
TESTING IPLZ AND IpZL.
CONNECTTO GND WHEN
TESTING IpHZ AND IpZH

• Includes all probe and jig capacitance

Figure 4.

Figure 3.

MOTOROLA

I

, Y

3-318

High-Speed CMOS Logic Data
DL129-Rev6

MC54n4HC245A
EXPANDED LOGIC DIAGRAM

AI 2
18 Bl
A2 3
17 B2
A3 4
16 B3
A4 5
A
DATA
PORT

15 B4
A5 6

B
DATA
PORT

14 B5

A6 7
13 B6

[3J

A7 8
12 B7

AS 9
11 B8

DIRECTION

OUTPUTENABLE

High-Speed CMOS Logic Data

DL129-Rev6

1

19

3-319

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

I MC54/74HCT245A I

Octal 3-State Noninverting
Bus Transceiver with
LSTTL Compatible Inputs

JSUFFIX
CERAMIC PACKAGE
CASE 732-03

High-Performance Silicon-Gate CMOS
The MC54n4HCT245A is identical in pinout to the LS245. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The MC54n4HCT245A is a 3-state noninverting transceiver that is
used for 2-way asynchronous communication between data buses. The
device has an active-low Output Enable pin, which is used to place the
1/0 ports into high-impedance states. The Direction control determines
whether data flows from A to B or from B to A.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

20..20.
20.
1

Output Drive Capability: 15 LSTTL Loads
TTUNMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 IlA
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 304 FETs or 76 Equivalent Gates

A2
A3
A
DATA
PORT

A4
AS
A6
A7
A8

2

18

3

17

4

16

5

15

6

14

7

13

8

12

9

11

1
DIRECTION
19
OUTPUT ENABLE

Design Criteria

I

I
Value

B1
B2
B3
B4
B5

PIN ASSIGNMENT
B
DATA
PORT

DIRECTION

ea

Internal Gate Propagation Delay

1.0

ns

Internal Gate Power Dissipation

5.0

IlW

0.005

pJ

VCC

B6

A1

B7

A2

B1

B8

A3

B2

A4

B3

AS

B4

A6

B5

A7

B6

A8

B7

GND

B8

Units

76

DTSUFFIX
TSSOP PACKAGE
CASE 948E-02

ORDERING INFORMATION
MC54HCTXXXAJ
Ceramic
MC74HCTXXXAN
Plastic
SOIC
MC74HCTXXXADW
MC74HCTXXXASD
SSOP
MC74HCTXXXADT
TSSOP

PIN 20= VCC
PIN 10=GND

Internal Gate Count'

SDSUFFIX
SSOP PACKAGE
CASE 940G-03

1

LOGIC DIAGRAM
A1

DWSUFFIX
SOIC PACKAGE
CASE 751D-04

OUTPUT ENABLE

FUNCTION TABLE

Speed Power Product

Control Inputs

, EqUivalent to a twD-lnput NAND gate.

Output
Enable

Direction

L

L

Data Transmitted from Bus B to Bus A

L

H

Data Transmitted from Bus A to Bus B

H

X

Buses Isolated (High-Impedance State)

Operation

X =Don't Care

10195

© Motorola. Inc. 1995

3-320

REV 6

®

MOTOROLA.

MC54/74HCT245A
MAXIMUM RATINGS'
Symbol
VCC
Yin
Vout
lin

Parameter

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to Vce + 0.5

V

DC Input Current, per Pin

±20

rnA
rnA

DC Supply Voltage (Referenced to GND)

lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
SSOP or TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

- 65 to + 150

°C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :S (Vin or Vout) :S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
SSOP or TSSOP Package: -6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

4.5

5.5

V

0

VCC

V

-55

+ 125

°c

0

500

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

Unit

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

:S 85°C

:S 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=O.1 VorVCC-O.l V
lIoutl :S 20 /lA

4.5
5.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
lIoutl :S 20 /lA

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIoutl :S 20 /lA

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

Yin = VIH or VIL
lIoutl :S 6.0 rnA

4.5

3.98

3.84

3.7

Yin = VIH or VIL
lIoutl :S 20 /lA

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Symbol

VOH

VOL

lin

Parameter

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

High-Speed CMOS Logic Data
DL129-Rev6

Test Conditions

Yin = VIH or VIL
lIoutl :S 6.0 rnA

4.5

0.26

0.33

0.4

Yin = VCC or GND, Pins 1 or 19

5.5

±0.1

±1.0

±1.D

3-321

V

/lA

MOTOROLA

MC54174HCT245A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

ICC

Maximum Quiescent Supply
Current (per Package)

Vin =VCC or GND
lout =0 IIA

5.5

4.0

40

160

IIA

10Z

Maximum Three-State
Leakage Current

Output in High-Impedance State
Vin =VIL or VIH
Vout =VCC or GND, VO Pins

5.5

±0.5

±5.0

±10

IIA

Additional Quiescent Supply
Current

Vin =2.4 V,.Any One Input
Vin =VCC or GND, Other Inputs
lout =0 IIA

,l1CC

NOTE: Information on typical parametric values can be found
AC ELECTRICAL CHARACTERISTICS (VCC

In

,,-55°C

25°C to 125°C

2.9

2.4

rnA

5.5

Chapter 2.

=5.0 V ± 10%, CL =50 pF, Input tr =tf =6.0 ns)
Guaranteed Limit
-5510
25°C

s 85°C

s 125°C

Unit

tpLH,
tpHL

Maximum Propagation Delay, A to B or B to A
(Figures 1 and 3)

22

28

33

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to A or B
(Figures 2 and 4)
,

30

36

42

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to A or 8
(Figures 2 and 4)

30

36

42

ns

ITLH,
ITHL

Maximum Output Transition Time. any Output
(Figures 1 and 3)

12

15

18

ns

Cin

Maximum Input Capacitance (Pin 1 or 19)

10

10

10

pF

Cout

Maximum Three-State 1/0 Capacitance, (1/0 in High-Impedance State)

15

15

15

pF

Symbol

Parameter

NOTE: For propagation delays With loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°C, VCC
Power Dissipation Capacitance (Per Enabled Output)'

= 5.0 V

97

'Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-322

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HCT245A
SWITCHING WAVEFORMS

¥r---

'i
DIRECTION

---'1\~1.3_V_ _ _ _ _l (.3 V

3.0 V
GND

'Tr---3.0V
OUTPUT
ENABLE

-3.0V

INPUT
AORB

HIGH
IMPEDANCE

I~----GND

IPLH

AORB

OUTPUT
BORA

AORB

ITHL

HIGH
IMPEDANCE

Figure 1.

Figure 2.

TEST POINT

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

I

CONNECTTO VCC WHEN
TESTING IpLZ AND IPZL.
CONNECT TO GND WHEN
TESTING IPHZ AND IPZH-

[3] .
• Includes all probe and jig capacitance

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev6

1 kQ

Figure 4. Test Circuit

3-323

MOTOROLA

MC54n4HCT245A
EXPANDED LOGIC DIAGRAM

/1.1 ....;;2'--_ _ _-1
18 B1
A2 ....:3'--_ _ _--1
17 B2
A3 _4'--_ _t---1
16 B3

A
DATA
PORT

A4....:5'----_--1
15 B4
B
DATA
PORT

A5....:6'----_--1
14 B5
A6....,;7---t---1
13 B6
A7....;;8'----_-I
12 B7
A8....:9'----_--1
11 B8

.,...._-1

DIRECTION --'.1_ _

OUTPUT ENABLE --:.;19,--_#_c:I

MOTOROLA

3-324

High-Speed CMOS Logic Data

DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC251

a-Input Data Selector/
Multiplexer with
3-State Outputs
High-Performance Silicon-Gate CMOS

~

16~ltmmUU

The MC54/74HC251 is identical in pinout to the LS251. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as determined by
the Address Inputs. The Output Enable pin must be a low level for the
selected ~ata to appear at the outputs. If Output Enable is high, both the Y
and the Y outputs are in the high-impedance state. This 3-state feature
allows the HC251 to be used in bus-oriented systems.
The HC251 is similar in function to the HC151 which does not have
3-state outputs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

DSUFFIX
SOIC PACKAGE
CASE 751 B-05

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 ~A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 134 FETs or 33.5 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXO

02

I
I

1e

16

2

15

00

I

4

YI 5

00 4
3

03

;Y}

04 15
05 14

6

02 2

VI
I
ENABLE
GNO I

OUTPU~

pVee

b04
14 b05
13 P06
12 P07
1t bAO
10 bA1
9 PA2

OJ( 3

LOGIC DIAGRAM

01

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
03

OATA
INPUTS

JSUFFIX
CERAMIC PACKAGE
CASE 62(J...10

6
7
8

OATA
OUTPUTS

V

06 13
07 12

FUNCTION TABLE
Inputs

AOORESS {
INPUTS

AO
A1
A2 9
7
OUTPUT ENABLE

Outputs

A2

At

AO

Output
Enable

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

PIN 16 = Vee
PIN 8~GNO

y

Y

Z
00
01
02
03
04
05
06
07

Z
00
01
02
03
04
05
06
07

Z = high impedance
00, 01, ... , 07 =the level of the respective
o input.

10195

© Motorola, Inc. 1995

3-325

REV6

®

MOTOROLA

MC54/74HC251
MAXIMUM RATINGS·
Symbol
VCC

. Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±25

mA

lout

DC Output Current, per Pin

±50

mA

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+150

"C

Tstg
TL

Storage Temperature
Lead Temperature; 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection.
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any.
voltage' higher than maximum rated
voltages to this high-impedance circuit. For proper operation: Yin and
Vout should be constrained to the
rangeGND,; (VinorVout) ,; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

"C
260
300

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65 0 to 125"C
Ceramic DIP: -10 mW/"C from 100 0 to 125"C
SOIC Package: -7 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall lime
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

2.0

6.0

Unit
V

0

VCC

.V

-55

+ 125

"C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

,; 85"C

,; 125"C

Unit

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
lIoutl ,; 20 J.lA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.l VorVCC-O.l V
lIoutl ,; 20 ~A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl ,; 20 ~A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl ,; 4.0 mA
lIoutl ,; 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
lIoutl ,; 20 ~A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL Iioutl ,; 4.0 mA
lIoutl ,; 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOL

Maximum Low-Level Output·
Voltage

Test Conditions

-55to
25"C

VIH

VOH

Parameter

VCC
V

V

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

~A

IOZ

Maximum Three-State
Leakage Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

~A

ICC

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 J!A

6.0

8

80

160

~A

lin

NOTE: Information on tYPical parametric values can be found m Chapter 2.

MOTOROLA

3-326

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC251
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

:s

8s o e

:s

125°e

Unit

tPLH,
tpHL

Maximum Propagation Delay, Input D to Output Y or Y
(Figures 1, 2 and 5)

2.0
4.5
6.0

185
37
31

230
46
39

280
56
48

ns

tpLH,
tpHL

Maximum Propagation Delay, Input A to Output Y or Y
(Figures 3 and 5)

2.0
4.5
6.0

205
41
35

255
51
43

310
62
53

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)

2.0
4.5
6.0

195
39
33

245
49
42

295
59
50

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)

2.0
4.5
6.0

145
29
25

180
36
31

220
44
38

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)

2.0
4.5
6.0

220
44
37

275
55
47

330
66
56

ns

tPZL,
tpZH

Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)

2.0
4.5
6.0

150
30
26

190
38
33

225

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 5)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

-

10

10

10

pF

15

15

15

pF

Cin
Cout

Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)

45
38
ns

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 2s o e, Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

36

• Used to determine the no-load dynamic power consumption: PD = CpD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

PIN DESCRIPTIONS
INPUTS

Output Enable (Pin 7)

Data inputs. Data on one of these eight binary inputs may
be selected to appear on the output.

Output Enable. This input pin must be at a low level for the
selected data to appear at the outputs. If the Output Enable
pin is high, both the Y and Y outputs are taken to the highimpedance state.

CONTROL INPUTS

OUTPUTS

AD, Al, A2 (Pins 11, 10, 9)

V,

Address inputs. The data on these pins are the binary address of the selected input (see the Function Table).

Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.

00,01, ... , 07 (Pins 4, 3, 2, 1, 15, 14, 13, 12)

High-Speed CMOS Logic Data
DL129-Rev6

3-327

Y (Pins 5, 6)

MOTOROLA

MC54174HC251
SWITCHING WAVEFORMS
tr

-VCC

-VCC

INPUTD

___ I

INPUTD

1"-----GND

OUTPUTY

11<-..,-_ _ _ GND

OUTPUT\'
trHL

trHL

Figure 2.

Figure 1.

iy ,I f
VALID

INPUT A

VALID

50%

tPLH
OUTPU!
YORY

50%

x··

,.----VCC
Vcc

OUTPUT
ENABLE
HIGH
IMPEDANCE

GND
YORY

tpHL

_ _ _ ___

~

YORY

Figure 3.

Figure 4.

TEST CIRCUITS
TEST POINT

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST.

• Includes all probe and jig capacitance

I

CONNECT TO VCC WHEN
TESTING tPLZ AND tpZL·
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH.

• Includes all probe and jig capacitance

Figure 6.

FigureS.

MOTOROLA

1 kQ

3-328

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC251
EXPANDED LOGIC DIAGRAM

DO

4

01
02
03
DATA
INPUTS

5Y}

04 15

DATA

Y OUTPUTS
05 14
06 13
07 12

OUTPUT
ENABLE

High-Speed CMOS Logic Data
DL129- Rev 6

3-329

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC253

Dual 4-lnput Data Selector/
Multiplexer with
3-State Outputs

NSUFFIX
PLASTIC PACKAGE
CASE 64S-QS

High-Performance Silicon-Gate CMOS
The MC74HC253 is identical in pinout to the LS253. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The Address inputs select one of four Data inputs from each multiplexer.
Each multiplexer has an active-low Output Enable control and a three-state
noninverting output.
The HC253 is similar in function to the HC153 which does not have
three-state outputs.
•
•
•
•
•
•
•

DSUFFIX
SOIC PACKAGE
CASE 7518-05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
N07A
Chip Complexity 108 FETs or 27 Equivalent Gates

PIN ASSIGNMENT
OUTPUT [
ENABLE a 1e.
A1 [ 2

LOGIC DIAGRAM

I

OATAWORD a
INPUTS

DOa
D1
a
D2a
D3a

D2a [ 4

13

~ D3b

D1a [ 5

12 ~ D2b

Va [ 7

ENABLEb
14 ~ AO

11

~ D1b

10 ~ DOb

GND[ 8

9

~ Vb

6
5
4
3

FUNCTION TABLE
Inputs

OUTPUT....:1_ _ _ _ _ _ _ _.J
ENABLE a

DATAWORDb
INPUTS

~ Vee

DOUTPUT

DOa [ 6
ADDRESS { AO 14
INPUTS
A1 ...:2=-.-+-_ _ _ _ _--1

16
15

D3a [ 3

[aJ

Plastic
SOIC

A1

AO

X

X
L
H
L
H

H
L
L
L
L

L
L
H
H

I

DOb 10
D1b 11
12
D2b
D3b 13

Output
Output
Enable

Y

Z
DO
Dl
D2
D3

DO, D1, D2, and D3 = the level of
the respective Data Inputs.
Z high impedance

=

OUTPUT ...:1.:::.5 _ _ _ _ _ _ _ _.J
ENABLEb PIN 16= Vee
PIN B= GND

10195

© Motorola. Inc. 1995

3-330

REV 6

®

MOTOROLA

MC74HC253
MAXIMUM RATINGS·
Value

Unit

-0.5to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5toVCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

Symbol
VCC
Vin
Vout

Parameter
DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

±20

mA
mA

lout

DC OutpUl Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

- 65 to + 150

°c

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND :5 (Vin orVout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• MaxImum Ratings are those values beyond whIch damage to the devIce may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, VOU!

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC = 4.5 V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed limit
Symbol

:5 85°C

:5 125°C

Unit

Minimum High-Level Input
Voltage

Vou t=O.l VorVcc-O.l V
1I0uti :5 20 flA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.l VorVCC-O.l V
1I0uti :5 20 flA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
1I0uti :5 20 flA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL "oUlI :5 4.0 mA
1I0uti :5 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
"outl :5 20 flA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL "outl :5 4.0 mA
"outl :5 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOL

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25°C

VIH

VOH

Parameter

VCC
V

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

± 1.0

flA

IOZ

Maximum Three-State
Leakage Current

Output in High-Impedance State
Vin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

flA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 flA

6.0

8

80

160

flA

lin

NOTE: InformatIon on tYPIcal parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev 6

3-331

MOTOROLA

MC74HC253
AC ELECTRICAL CHARACTERISTICS (Cl =50 pF, Input tr =tf =6 ns)
Guaranteed limit

Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

tplH,
tpHl

Maximum Propagation Delay, Data to Output Y
(Figures 1 and 3)

2.0
4.5
6.0

140
28
24

175
35
30

210
42
36

ns

tplH,
tpHl

Maximum Propagation Delay, Address to Output Y
(Figures 1 and 3)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tPLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpZl,
tpZH

Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

trlH,
trHl

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-5tate Output Capacitance
(Output in High-Impedance State)

-

15

15

15

pF

Symbol

Parameter

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.

Typical
Power Dissipation Capacitance (Per Multiplexer)"

@

25°e,

Vee = 5.0 V

31

• Used to determine the no-load dynamic power consumption: Po

= CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
~---VCC

OUTPUT
ENABLE
AORD_ _---'tl

HIGH
IMPEDANCE

11t----GND

y
y
y

Figure 2.

Figure 1.

MOTOROLA

3-332

High-Speed CMOS logic Data
DL129-Rev6

MC74HC253
TEST CIRCUITS
TEST POINT

I

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

CONNECTTO VCC WHEN
TESTING tPLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tPHZ AND IPZH.

1 kn

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 3.

Figure 4.

PIN DESCRIPTIONS
DATA INPUTS

Output Enable (Pins 1, 15)

DO a - D3a, DOb - D3b (Pins 3, 4, 5, 6, 10, 11, 12, 13)

Active-low three-state Output Enable. When a low level is
applied to these inputs, the corresponding outputs are enabled. When a high level is applied, the outputs assume the
high-impedance state.

Data inputs. When one of these pairs of inputs is selected
and the outputs are enabled, the outputs assume the state of
the respective inputs.

CONTROL INPUTS

OUTPUTS

AD, A1 (Pins 2,14)
Va, Vb (Pins 7,9)

Address inputs. These inputs select the pair of Data inputs
to appear at the corresponding outputs.

Noninverting three-state outputs.

LOGIC DETAIL

DOa

VCC

d

D1a
DATA-WORD a
INPUTS
D2a

}-"
q

4

D3a
DOb
D1b
DATA-WORDb
INPUTS
D2b
D3b

ADDRESS
INPUTS

10

~

11

}-'b

12
13

q

r
AO

NOINVERTING
OUTPUTS

14

High-Speed CMOS Logic Data
DL129-Rev6

3--333

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC257

Quad 2-lnput Data
Selector/Multiplexer with
3-State Outputs

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

High-Performance Silicon-Gate CMOS
The MC74HC257 is identical in pinout to the LS257. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects a (4-bit) nibble from either the A or B inputs as
determined by the Select input. The nibble is presented at the outputs in
noninverted form when the Output Enable pin is at a low level. A high level on
the Output Enable pin switches the outputs into the high-impedance state.
The HC257 is similar in function to the HC157 which do not have 3-state
outputs.
•
•
•
•
•
•
•

16#
1

ORDERING INFORMATION

I
NlOO~ I

NlM~

A INPUT

A2
A3
BO

B INPUT

B3

16 ~ VCC
15 ~ OUTPUT
ENABLE
14 ~ A3

SELECT [ 1AO [ 2
BO [ 3

LOGIC DIAGRAM

VO [ 4

13

PB3

A1[ 5

12

~ V3

B1[ 6

11

~A2

V1[ 7

10

PB2
9 PV2

GND[ 8
5
11

FUNCTION TABLE

14

Inputs

3

V1

VOl

B1

B2

SOIC

PIN ASSIGNMENT

AO
A1

Plastic

MC74HCXXXN
MC74HCXXXD

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 JlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 108 FETs or 27 Equivalent Gates

[3]

DSUFFIX
SOIC PACKAGE
CASE 7518-05

12

10

V2
V3

NON INVERTING
NIBBLE
OUTPUT

Output
Enable

Select

VO-V3

X

Z
AO-A3
BO-B3

H
L
L

13

Outputs

L
H

X = don't care
Z = high impedance
AO-A3, BO-B3 = the levels of the
respective Nibble Inputs.

SELECT
OUTPUT 15
ENABLE
PIN 16= VCC
PIN8=GND

10195

© Motorola, Inc. 1995

3--334

REV6

®

MOTOROLA

MC74HC257
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA
rnA

lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

Po

Power Dissipation in Still Air

750
500

mW

-65to+150

°C

Tstg

TL

PlasticDIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• MaxImum RatIngs are those values beyond whIch damage to the devIce may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0

1000
500
400

ns

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

t r, tf

Input Rise and Fall "Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

a
0

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl s 2Ol1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Levellnput
Voltage

Vou t=0.1 VorVcc-0.1 V
lIoutl s 2Ol1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 2Ol1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Symbol

VOH

Parameter

Test Conditions

Yin = VIH or VIL lIoutl
lIoutl
VOL

Maximum Low-Level Output
Voltage

s 6.0 rnA
s 7.8 rnA

Yin = VIH or VIL
lIoutl s 2Ol1A
Yin = VIH or VIL

lIoutl
lIoutl

s 6.0 rnA
s 7.8 rnA

V

Maximum Input Leakage ,Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

Il A

IOZ

Maximum Three-State
Leakage Current

Output in High-Impedance State
Vin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

IlA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
10ut=01lA

6.0

8

80

160

!lA

lin

NOTE: InformatIon on tYPIcal parametric values can be found

High-Speed CMOS Logic Data
DL129- Rev 6

In

Chapter 2.

3--335

MOTOROLA

MC74HC257
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

tPLH,
tpHL

Maximum Propagation Delay, Nibble A or B to Output Y
(Figures 1. and 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tpLH,
tPHL

Maximum Propagation Delay, Select to Output Y
(Figures 2 and 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tPZL,
tpZH

Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

trLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-State Output Capacitance
(Output in High-Impedance State)

-

15

15

15

pF

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Package)*

=5.0 V

39

• Used to determine the no-load dynamic power consumption: Po = CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

PIN DESCRIPTIONS
For the Output Enable input at a high level, the outputs are
switched to the high impedance state.

INPUTS
AD, A1, A2, A3 (Pins 2, 5,11,14)

Nibble A input. The data present on these pins is transferred to the output when the Select input is at a low level and
the Output Enable input is at a low level. The data is presented to the outputs in noninverted form.

CONTROL INPUTS

Select (Pin 1)

BO, B1, B2, B3 (Pins 3, 6, 10, 13)

Nibble B input. The logic data present on these pins is
transferred to the output when the Select input is at a high
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.

Nibble select. This input determines the nibble to be transferred to the outputs. A low level on this input selects the A
inputs and a high level selects the B inputs.

OUTPUTS

Output Enable (Pin 15)

VO, V1, V2, V3 (Pins 4,

7, 9, 12)

Output Enable. A low level on this input allows the selected
input data to be presented at the outputs. A high level on this
input forces the outputs into the high-impedance state.

Nibble output. The selected nibble input is presented at
these outputs when the Output Enable input is at a low level.

MOTOROLA

3-336

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC257
SWITCHING WAVEFORMS

-VCC

NIBBLE INPUT
AORB

11'-----GND
tpHL

SELECT

~

tPLH ~

OUTPUTY

OUTPUTY

VALID

50%

I

1:=

VALID

GND

,I

~ 50%

Jcvcc

tpHL

, ' -_ _ __

trHL

Figure 2.

Figure 1.

,.---VCC
OUTPUT
ENABLE
HIGH
IMPEDANCE
OUTPUTY

OUTPUTY

Figure 3.

TEST CIRCUITS
TEST POINT

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

,~

I

CONNECTTO VCC WHEN
TESTING tpLZ AND tpZL·
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH.

• Includes all probe and jig capacitance

Figure 4.

High-Speed CMOS Logic Data
DL129-Rev6

1 kQ

Figure 5.

3-337

MOTOROLA

MC74HC257
EXPANDED LOGIC DIAGRAM
AO 2

BO

A1

B1
NIBBLE
INPUTS

A2

B2

A3

B3

6

NIBBLE
OUTPUT

11

10

14

13

OUTPUT 15
ENABLE

MOTOROLA

3-338

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC259

8-Bit Addressable Latch
1-of-8 Decoder
High-Performance Silicon-Gate CMOS
The MC54/74HC259 is identical in pinout to the LS259. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC259 has four modes of operation as shown in the mode selection
table. In the addressable latch mode, the data on Data In is written into the
addressed latch. The addressed latch follows the data input with all
non-addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one-of-eight decoding or demultiplexing
mode, the addressed output follows the state of Data In with all other outputs
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259 as an addressable
latch, changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the memory
mode.

,.
II ...

J SUFFIX
CERAMIC PACKAGE
CASE 620-10

16_

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

16#

DSUFFIX
SOIC PACKAGE
CASE 7518-05

16

ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 IlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 202 FETs or 50.5 Equivalent Gates

PIN ASSIGNMENT
AO

1-

16

AI

2

15

RESET

14

ENABLE

A2
4

13

DATA IN

01

5

12

Q7

6

11

06

10

05

9

Q4

02
03
GND
400
5 01
6 02

7 03
9 04

8

MODE SELECTION TABLE
NONINVERTING
OUTPUTS

Enable

Reset

Mode

L
H
L
H

H
H
L
L

Addressable Latch
Memory
8-Line Demultiplexer
Reset

10 05

DATA IN 13

Vee

00

LOGIC DIAGRAM

AO 1
ADDRESS { A1 2
INPUTS
A2 3

Ceramic
Plastic
SOIC

1106
12 07

LATCH SELECTION TABLE
Address Inputs
PIN 16= Vee
PIN 8= GND

10/95

© Motorola, Inc. 1995

3-339

REV 6

C

B

A

Latch
Addressed

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

00
01
02
03
04
05
06
07

®

MOTOROLA

[3J

MC54/74HC259
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to + 150

DC

lin

Tstg

TL

.

Storage Temperature

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuil. For proper operation, Vin and
Vout should be constrained to the
range GND :s (Vin or Vout) :S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

DC

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

260
300

Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65 0 to 125 0 C
Ceramic DIP: -10 mW/oC from 100 0 to 125 0 C
SOIC Package: -7 mW/oC from 65 0 to 125 0 C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC

.[3]

Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC= 4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

DC

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

:S 85°C

:S 125 0 C

Unit

VIH

Vout=0.1 VorVcc-0.1 V
lIoutl :S 20 IlA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 VorVcc -0.1 V
lIoutl :S 20 I'A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl :S 20 IlA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl :S 4.0 rnA
lIoutl :S 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
lIoutl :S 20 !1A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL lIoutl :S 4.0 rnA
lIoutl :S 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

I'A

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0!1A

6.0

8

80

160

!1A

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Test Conditions

-SSto
2S oC

Minimum High-Level Input
Voltage

VOH

Parameter

VCC
V

V

NOTE: Information on typical parametric values can be found In Chapter 2.

MOTOROLA

3-340

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC259
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

-55to
25'e

:;; 85'e

:;; 125'e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Data to Output
(Figures 1 and 6)

2.0
4.5
6.0

185
37
31

230
46
39

280
56
48

ns

tpLH,
tpHL

Maximum Propagation Delay, Address Select to Output
(Figures 2 and 6)

2.0
4.5
6.0

215
43
37

270
54
46

325
65
55

ns

tpLH,
tpHL

Maximum Propagation Delay, Enable to Output
(Figures 3 and 6)

2.0
4.5
6.0

200
40
34

250
50
43

300
60
51

ns

tpHL

Maximum Propagation Delay, Reset to Output
(Figures 4 and 6)

2.0
4.5
6.0

155
31
26

195
·39
33

235
47
40

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 6)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

Vee
V

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

30

* Used to determine the no-load dynamic power consumption: PD = CpD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

-55to
25'e

:;; 85'e

:;; 125'e

Unit

tsu

Minimum Setup Time, Address or Data to Enable
(Figure 5)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Enable to Address or Data
(Figure 5)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Reset or Enable
(Figure 3 or 4)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

tr,tf

Parameter

Vee
V

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev 6

3-341

MOTOROLA

MC54/74HC259
SWITCHING WAVEFORMS
vcc

/

DATA IN

-GND
VCC

50%
-GND

ADDRESS
SELECT

DATA IN

-Vcc

GND

GND
OUTPUT 0 ----l.l!-'2..of

OUTPUT 0

Figure 1.

Figure 2.

Vcc
DATA IN

VCC
50%
-GND

ENABLE

[3J

OUTPUTQ

-=:L..f

tPHL

VCC

DATAIN~

-GND
VCC

RESET
-GND

F~H

OUTPUT 0

Figure 4.

Figure 3.

TEST POINT
OUTPUT

DATA IN
OR
ADDRESS
SELECT

DEVICE
UNDER
TEST

ENABLE
• Includes all probe and jig capacitance

FigureS.

MOTOROLA

Figure 6. Test Circuit

3-342

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC259
EXPANDED LOGIC DIAGRAM
DATA INPUT _1;,:;3_ _ _ _ _ _ _ _ _ _- - 1

l

AO

ADDRESS
INPUTS

A1

3T08

DECODER

A2

ENABLE ....;1..;,.4_ _-'

-====::t==---.J

RESETJ1.§..5_ _ _ _

High-Speed CMOS Logic Data
DL129-Rev6

3-343

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview
8-Bit Addressable Latch
1-01-8 Decoder

MC54/74HC259A
JSUFFIX
CERAMIC PACKAGE
CASE 620-10

High-Performance Silicon-Gate CMOS
The MC54174HC259A is identical in pinout to the LS259. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC259A has four modes of operation as shown in the mode selection
table. In the addressable latch mode, the data on Data In is written into the
addressed latch. The addressed latch follows the data input with all
non-addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one-of-eight decoding or demultiplexing
mode, the addressed output follows the state of Data In with all other outputs
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259A as an
addressable latch, changing more than one bit of the address could impose
a transient wrong address. Therefore, this should only be done while in the
memory mode.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE64~8

16#
1

DTSUFFIX
TSSOP PACKAGE
CASE 948F-{)1
ORDERING INFORMATION

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 iJA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 202 FETs or 50.5 Equivalent Gates

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

AO

1-

16

Vee

A1

2

15

RESET

400
5 01

A2

14

ENABLE

00

13

DATA IN

602

01

12

07

7 03
9 Q4
DATAIN 13

Ceramic
Plastic
SOIC
TSSOP

PIN ASSIGNMENT

LOGIC DIAGRAM
1
ADDRESS { ~O 2
INPUTS
1 3
A2

DSUFFIX
SOIC PACKAGE
CASE 751B-

CLOCK

ClK

~

r-

~D

DF:Q~

SR

H

ClK Cl~

I

r-

DEMUX 0

• R

~DSl

r-tSR

r---

a

I
I

C

I

A

'V

I~

SR

H

~~~l

iLf>: ~~iJ!

o t

ClK Cl~

I

I

DEMUX 0 f- 0 FD

~DSl

rl--

I

DEMUX 0 f-

~D
SR

H

ClK Cl~

I

-

0 FF

~DSl

~D

~ ~

ClK Cl~

H

DEMUX 0

OE2

2

r- o FG

Sl

3

o-P-

SR

rl> - ' I
lD

18

MOTOROLA

3-370

Sl

0

R

H

DEMUX 0

0

R

r-tSR

I

L
OEt

0

R

DEMUX 0

1>-4> ~

o FE

Sl

I \. A
B

I

ClK Cl~

H

j

13

I

~ I

6

W

Or-

R
T

I

W

Or-

H

...--

J1.

r- o FC

SR

0

DETAIL OF DEMULTILPLEXER

I

I

~D

Sl

-LreJ~

-+- ~
I

7

W

Or-

R

SR

...--

0 Fa

Sl

I
1.. _ _ _ _ _ _ _ _ _ _ .J
lD

I

ClK Cl~

H

DEMUX 0

'V

J

Sl

DEMUX 0
ClK

I

I

ClK Cl~

H

8

~I

14

J

~I

5

J

~I

15

J

~

ClK ClK

I-

o FH
R

Q

0

&-t

~

17

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

a-Input Data Selector/
Multiplexer With Data and
Address Latches and
3-State Outputs

MC54/74HC354
J SUFFIX
CERAMIC PACKAGE
CASE 732-03

High-Performance Silicon-Gate CMOS
The MC54n4HC354 is identical in pinout to the LS354. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC354 selects one of eight latched binary Data Inputs, as determined by the Address I nputs. The information at the Data Inputs is stored
in the transparent 8-bit Data Latch when the Data-Latch Enable pin is
held high. The Address information may be stored in the transparent
Address Latch, which is enabled by the active-high Address-Enable pin.
The device outputs are placed in high-impedance states when Output
Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.

N SUFFIX
PLASTIC PACKAGE
CASE 738-03

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

20~
1

ORDERING INFORMATION

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW

The HC354 has a clocked Data Latch that is not transparent.
• Output Drive Capability: 15 LSTIL Loads

Ceramic
Plastic
SOIC

• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
Pinout: 20-Lead Package (Top View)

• Low Input Current: 111A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No.7A Requirements
• Chip Complexity: 326 FETs or 81.5 Equivalent Gates

D6

LOGIC DIAGRAM

DATA
INPUTS

DO
01
02
03
04
05
06
07

8
7
6
5
4
3
2
1

03
02
B-BIT
DATA
LATCH
(TRANSPARENT)

B-BIT
MULTIPLEXER

3-STATE
OUTPUT
CONTROL

19

18

v]
y

Dl

3-STATE
DATA
OUTPUTS

DO
Data-Latch
Enable
11 Address-Latch
Enable

DATA-LATCH 9
ENABLE
ADDRESS
INPUTS

14
- ' - - - - - - I ADDRESS
LATCH
AI 13
(TRANS12
A2
PARENT)

[M

ADDRES5-LATCH 11
ENABLE
OUTPUT
ENABLES

PIN 20 =VCC
PIN 10= GND

15
16
OE2 17
OE3

~O"

10195

© Motorola, Inc. 1995

3-371

REV7

®

MOTOROLA

MC54174HC354
MAXIMUM RATINGS'
Symbol

VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature Range

- 65 to + 150

°C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
Ceramic DIP

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

Parameter

Min

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature Range, All Package Types

t r, tf

Input Rise/Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Parameter

Condition

Guaranteed Limit

VCC
V

-55 to 25°C

S85°C

!>125°C

Unit

1.50
3.15
4.20

1.50
3.15
4.20

1.50
3.15
4.20

V

VIH

Minimum High-Level Input Voltage

Vout = 0.1VorVcc-{)·1V
1I0uti !> 201JA

2.0
4.5
6.0

VIL

Maximum Low-Levellnput Voltage

Vout = 0.1V orVcc- 0.1V
1I0uti !>20J.1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti !> 201JA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

6.0

±0.1

±1.0

±1.0

VOH

Yin =VIH or VIL
VOL

lin

MOTOROLA

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

1I0uti !> 6.0mA
1I0uti !> 7.8mA

=

Yin VIH or VIL
1I0uti !> 201JA
Yin

=VIH or VIL

Yin

=VCC or GND

3-372

1I0uti !> 6.0mA
1I0uti !> 7.8mA

V

J.1A

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC354

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Parameter

Condition

IOZ

Maximum Three-State Leakage
Current

ICC

Maximum Quiescent Supply
Current (per Package)

Output in High-Impedance State
Vin VIL or VIH
Vout VCC or GND

=
=
Vin =VCC or GND
lout =OftA

Guaranteed Limit

Vee
V

-55 to 25°C

$85°e

$125°e

Unit

6.0

±0.5

±5.0

±10.0

ftA

6.0

8

80

160

ftA

NOTE: Information on typical parametric values can be found in Chapter 2.

AC CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Vee
V

Guaranteed Limit
-55 to 25°C

$85°e

$125°e

Unit

tPLH,
tpHL

Maximum Propagation Delay, 00-07 to Y or Y
(Figures 2 and 6)

2.0
4.5
6.0

210
42
36

265
53
45

315
63
54

ns

tPLH,
tpHL

Maximum Propagation Delay, Data-Latch Enable to Y or Y
(Figures 3 and 6)

2.0
4.5
6.0

260
52
44

325
65
55

390
78
66

ns

tpLH,
tpHL

Maximum Propagation Delay, AO-A2 to Y or Y
(Figures 2 and 6)

2.0
4.5
6.0

270
54
46

340
68
58

405
81
69

ns

tPLH,
tpHL

Maximum Propagation Delay, Address-Latch Enable to Y or Y
(Figures 3 and 6)

2.0
4.5
6.0

270
54
46

340
68
58

405
81
69

ns

tpLZ,
tpHZ

Maximum Propagation Delay, OE1-0E3 to Y or Y
(Figures 4 and 7)

2.0
4.5
6.0

160
32
27

200
40
34

240
48
41

ns

tpZL,
tpZH

Maximum Propagation Delay, OE1-OE3 to Y or Y
(Figures 4 and 7)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

trLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 6)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Symbol

Cin
Cout

Parameter

Maximum Input Capacitance

10

10

10

pF

Maximum Three-State Output Capacitance (Output in High Impedance
State)

15

15

15

pF

NOTE: For propagallon delays with loads other than 50 pF, and mformatlon on typical parametric values, see Chapter 2.
Typical @ 25°C, Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

48

• Used to determine the no-load dynamic power consumption: Po = CpO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev 6

3-373

MOTOROLA

MC54174HC354
PIN DESCRIPTIONS
DD-D7 (Pins 8-1) DATA INPUTS

ADDRESS-LATCH ENABLE (Pin 11)

These eight data bits are stored in a transparent latch when
the Data-Latch Enable pin is active (high). Once enabled,
changing inputs will not change the contents of the latch.

The latch is transparent to AO, A 1 and A2 when enable is
inactive (low). The Address-Latch contents are unaffected
when enable is held active (high).

AO, A1, A2 (Pins 14,13,12) ADDRESS INPUTS

OE1, OE2, OE3 (Pins 15,16,17) OUTPUT ENABLES

Selects which data bit stored in the Data Latch is routed to
the outputs Y and Y.

Any of the output enable pins inactive (OE1 =High or
OE2=High or OE3=Low) causes the outputs (Y and Y) to be
in high-impedance states.

DATA-LATCH ENABLE (Pin 9)

V, Y (Pins 19,18)

The latch is transparent to 00-07 when enable is inactive
(low). The Data-Latch contents are unaffected when enable
is held active (high).

TIMING REQUIREMENTS (Input tr

These 3-state outputs (when not 3-stated) represent the
data bit in the Data Latch selected by the Address Latch.

=tf =6 ns)
Guaranteed Limit

Vee
V

-55 to 25°e

$85°e

$125°e

Unit

Minimum Setup Time, 00-07 to Data-Latch Enable
(FigureS)

2.0
4.5
6.0

50
10
9

65

75
15
13

ns

13
11

tsu

Minimum Setup Time, AO-A2 to Address-Latch Enable
(Figure 5)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
.13

ns

th

Minimum Hold Time, Data-Latch Enable to 00-07
(FigureS)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

th

Minimum Hold Time, Address-Latch Enable to AO-A2
(Figure 5)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Data-Latch Enable
(Figure 3)

2.0
4.5
6.0

80
16
14

100
20

120
24
20

ns

tw

Minimum Pulse Width, Address-Latch Enable
(Figure 3)

2.0
4.5
6.0

80
16
14

100
20

ns

17

120
24
20

1000
500
400

1000
500
400

1000
500
400

ns

Symbol
tsu

tr,tf

Parameter

2.0
4.5
6.0

Maximum Input Rise and Fall Times
(Figure 1)

17

NOTE: Information on typical parametric values can be found In Chapter 2.

MOTOROLA

3-374

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC354

FUNCTION TABLE
Address Latch Contents #

Inputs

. A2

A1

AD

Data-Latch
Enable

X
X
X

X
X
X

X
X
X

X
X
X

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

Outputs

OE1

OE2

OE3

Y

Y

H

X

X
X

H

X
X

X

L

Z
Z
Z

Z
Z
Z

L

L

L

H

j

j

j

DO
D1
D2
D3
D4
D5
D6
D7

Data-Latch is Transparent

j

DO
D1
D2
D3
D4
D5
D6
D7

H

L

L

H

DOn

New Data is Stored in Data-Latch and is
Not Alterable

j

j

j

j

DOn
D1n
D2n
D3 n
D4n
D5 n
D6 n
D7n

Description
Outputs in High-Impedance States

Q.!n
D2n
D3 n
~
D5 n
D6 n
D7n

# Represents bits in Address-Latch. See Address-Latch Enable pin description.
X =Don't Care; Z =High Impedance; Do--D7 =the data at inputs DO through D7; DOn-D7 n =the data present at inputs DO through D7 when the
Data-Latch Enable pin was taken high.

SWITCHING WAVEFORMS

Vee

00--07
AO-A2

Any Input

>:;,

VerY

VerY

GNO

50%

ITHL

Figure 1.

Figure 2.

OE1,OE2

,-----Vee

OE3

'-----GNO

, - - - - - r i - - - - Vee

Address-

Latch Enable

VerY

'----GNO

VerY
VerY
High

Impedance

Figure 4,

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev6

3-375

MOTOROLA

MC54174HC354

D(}-D7
A(}-A2

Data-Latch
Enable

~

~

valid~ VCC

_

_

GND

IsU~lh
5(;0/.

V

CC

0

_ _ _ _ _ _-1-

----- --

GND

FigureS.

TEST CIRCUITS
TEST
POINT

TEST
POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

'Includes all probe and jig capacitance

'Includes all probe and jig capacitance

Figure 7.

Figure 6.

MOTOROLA

CONNECTTO VCC WHEN
[ TESTING tPLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tPHZ and tpZH.

1ill

3--376

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC354

Output
Enabtes

~O~~

_15_",---,

OE3

:X>--- Used

40

to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
,.----VCC

Ir

OUTPUT ENABLE

INPUT A

HIGH

I ' F - - - - - GND

IMPEDANCE

tpLH

OUTPUTY

OUTPUTY
OUTPUTY

Figure 1.

MOTOROLA

Figure 2.

3-380

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC365
TEST CIRCUITS
TEST POINT

TEST POINT

1 kQ
I-0'-U_T_PU'-T......~I/V\,.-

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

* Includes all probe and jig capacitance

I

Cl'

I

CONNECTTO VCC WHEN
TESTING tplZ AND IPZl.
CONNECT TO GND WHEN
TESTING tpHZ AND tPZH.

• Includes all probe and jig capacitance

Figure 4.

Figure 3.

LOGIC DETAIL

TO OTHERS
FIVE BUFFERS

----------OOEOF6'

r---------

BUFFERS

I

VCC

I

d!

J+v

91

INPUT A - - - - + - 1

I
IL _ _ _ _ _ _ _ _ _

-=

I

_ _ _ _ _ _ _ _ _ _ _ _ _ ...1

OUTPUT ENABLE 1 ----cr-"'\
OUTPUT ENABLE 2

High-Speed CMOS Logic Data
DL129-Rev6

1---.......--1

3--381

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Hex 3-State Inverting Buffer
with Common Enables

MC54/74HC366

High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 62D-l0

The MC54174HC366 is identical in pinout to the LS366. The device inputs
are compatible with standard CMOS outputs; with pull up resistors, they are
compatible with LSTTL outputs.
This device is a high-speed hex buffer with 3-state outputs and two
common active-low Output Enables. When either of the enables is high, the
buffer outputs are placed into high-impedance states. The HC366 has
inverting outputs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 ~A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 78 FETs or 19.5 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN

Ceramic
Plastic

PIN ASSIGNMENT
OUTPUT
ENABLE 1 1AO I 2

LOGIC DIAGRAM

AO --"--t--I

A1-"'--t-I

YO

Y2

A3 -'""-t-I

Y3

M-"'-t-I

Y4

13

Y1

12

5

~ Y5
~A4

A2

6

11 P Y4

Y2

7

10 PA3

GND

8

9

~

Y3

FUNCTION TABLE
Inputs

A5--'"'"-t-I

OUTPUT ENABLE 2 ----....'--~

A1I 4

Y1

A2-"--t-I

OUTPUT ENABLE 1 -'---'"',----...

YO I 3

~ Vee
15 ~ OUTPUT
ENABLE 2
14 PAS
16

PIN 16= Vee
PIN8=GND

Output

Enable

Enable

1

2

A

Y

L
L

L
L

L

H

H
X

X
H

H
X
X

L
Z
Z

X = don't care
Z = high impedance

10195

© Motorola, Inc. 1995

3-382

REV6

®

MOTOROL.A

MC54/74HC366
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA
rnA

lin
lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt

750

mW

Tstg

Storage Temperature

-65to+ 150

°C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND,;; (VinorVout)';; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

.Parameter

Test Conditions

VCC
V

-55to
25°C

,;; 85°C

s

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 V
1I0uti ,;; 20 JlA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=VCC-0.1 V
1I0uti ,;; 2011A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin=VIL
1I0uti S 2Ol1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4 .
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Vin=VIL
VOL

Maximum Low-Level Output
Voltage

1I 0u t' S 6.0 rnA
1I 0u t' S 7.8 rnA

Vin=VIH
1I0uti ,;; 20 JlA
Vin=VIH

1I 0ut' S 6.0 rnA
1I0ut' ,;; 7.8 rnA

V

lin

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

I1A

IOZ

Maximum Three-State Leakage
Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

I1A

ICC

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 JlA

6.0

8

80

160

JlA

NOTE: Information on typical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-383

MOTOROLA

MC54174HC366
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit

Vee
V

-55to
25°e

tpLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)

2.0
4.5
6.0

95
19
16

120
24
20

145
29
25

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)

2.0
4.5
6.0

220
44
37

275
55
47

330
66
56

ns

tPZL,
tpZH

Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)

2.0
4.5
6.0

220
44
37

275
55
47

330
66
56

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Maximum Input Capacitance

-

10

10

10

pF

Maximum Three-State Output Capacitance
(Output in High-Impedance State)

-

15

15

15

pF

Symbol

Cin
Cout

Parameter

s

85°e

s

125°e

Unit

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e,
Power Dissipation Capacitance (Per Buffer)"

Vee =5.0 V

40

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
,..---VCC
OUTPUT ENABLE
J,----VCC
HIGH
IMPEDANCE
OUTPUTY
OUTPUTY
OUTPUTY
trHL

Figure 2.

Figure 1.

TEST CIRCUITS
TEST POINT

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

r

I

CONNECTTO VCC WHEN
TESTING tpLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tpHZ AND tPZH.

CL
'

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 4.

Figure 3.

MOTOROLA

1 kQ
""""rv-_

t-0U_T_P_UT_......

DEVICE
UNDER
TEST

3-384

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC366
LOGIC DETAIL
TO OTHER
FIVE BUFFERS

r---------

----------ONEOF6'
BUFFERS

I

Vee

I

d!

J+v

91

INPUT A - - - - + - - - - I

I

-=

IL _ _ _ _ _ _ _ _ _

I

_ _ _ _ _ _ _ _ _ _ _ _ _ .J

OUTPUT ENABLE 1 ---<4-----..
1-------1
OUTPUT ENABLE 2 -----~YO

>----.:...Yl
>--"':""Y2

A2
10
12

P

3

13 ~ Y5

Yl

5

12 pM

A2

6

11

Y2

7

10 pA3

GND

8

9 ~ Y3

PY4

>--~Y3

FUNCTION TABLE
Y4

Inputs
Enable 1,
Enable 2

14

H

OUTPUT ENABLE 1
PIN 16: Vee
PIN8:GND

Output

A

V

L

L

H
X

H

Z

X = don't care
Z = high impedance

10195

© Motorola. Inc. t995

16 p Vee
15 OUTPUT
ENABLE 2
14 pA5

All 4

L
L

OUTPUT ENABLE 2 15

Ceramic
Plastic.

MC54HCXXXJ
MC74HCXXXN

3-386

REV 6

®

MOTOROLA

MC54174HC367
MAXIMUM RATINGS·
Symbol
VCC
Yin
Vout

Parameter

Value

Unit

-0.5to + 7.0

V

DC Input Voltage (Relerenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

±20

rnA
rnA

lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt

750

mW

Tstg

Storage Temperature

-65 to + 150

"C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,;; (Vin or Vout) ,;; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

"C
260
300

• Mru COUNTER

Ceramic
Plaslic
SOIC

QOa [ 7
GNO [ 8

5,11 QB
4,12
+5
CLOCK B ~~-+- COUNTER

6,10 QC

FUNCTION TABLE

7,9 QO

Clock
B
A

Reset

Action

X

X

H

'-

X

L

X

'-

L

Reset
+2and+5
Increment
+2
Increment
+5

RESET ---:2:.:..'1;. .; 4_ _ _.....
PIN 16= VCC
PIN8=GNO

10195

© Motorola, Inc. 1995

3-412

REV 6

®

MOTOROLA

MC5417 4HC390
MAXIMUM RATINGS'
Symbol
VCC
Vin
Vout

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 toVCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65to+150

"C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic or SOIC DIP)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND :s (Vin or Vout) :S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

"C
260
300

• MaxImum RatIngs are those values beyond whIch damage to the devIce may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65" to 125"C
Ceramic DIP: -10 mWI"C from 100" to 125"C
SOIC Package: - 7 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

2.0

6.0

Unit
V

0

VCC

V

-55

+ 125

"C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25"C

:S 85"C

:S 125"C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVcc-O.l V
1I0uti :S 20 I1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCc-O.l V
1I0uti :S 20 I1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
1I0uti :S 20 I1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL 1I0uti :S 4.0 rnA
1I0uti :S 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VIH or VIL
1I0uti :S 20 I1A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL 1I0uti :S 4.0 rnA
1I0uti :S 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

I1A

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
10ut=0 I1A

6.0

8

80

160

I1A

VOH

VOL

lin
ICC

Parameter

VCC
V

Maximum Low-Level Output
Voltage

V

NOTE: InformatIon on tYPIcal parametnc values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-413

MOTOROLA

MC54174HC390
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Inputtf = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25"e

:s 85"e

:s 125"e

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)

2.0
4.5
6.0

5.4
27
32

4.4
22
26

3.6
18
21

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock A to OA
(Figures 1 and 3)

2.0
4.5
6.0

120
24
20

150
30
26

180
36
31

ns

tPLH,
tpHL

Maximum Propagation Delay, Clock A to OC
(OA connected to Clock B)
(Figures 1 and 3)

2.0
4.5
6.0

290
58
49

365
73
62

435
87
74

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock B to OB
(Figures 1 and 3)

2.0
4.5
6.0

130
26
22

165
33
28

195
39
33

ns

tpLH,
tPHL

Maximum Propagation Delay, Clock B to OC
(Figures 1 and 3)

2.0
4.5
6.0

185
37
31

230
46
39

280
56
48

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock B to 00
(Figures 1 and 3)

2.0
4.5
6.0

130
26
22

165
33
28

195
39
33

ns

tpHL

Maximum Propagation Delay, Reset to any 0
(Figures 2 and 3)

2.0
4.5
6.0

165
33
28

205
41
35

250
50
43

ns

trLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25"C, Vee
Power Dissipation Capacitance (Per Counter)'

=5.0 V

35

'Used to determine the no-load dynamic power consumption: Po = CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25"e

:s 85"e

:s 125"e

Unit

Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

tw

Minimum Pulse Width, Clock A, Clock B
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tf,tf

Maximum Input Rise and Fall1imes
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol
trec

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-414

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC390
PIN DESCRIPTIONS
INPUTS

OUTPUTS

Clock A (Pins 1, 15) and Clock B (Pins 4, 15)

QA (Pins 3,13)

Clock A is the clock input to the + 2 counter; Clock B is the
clock input to the + 5 counter. The internal flip-flops are
toggled by high-to-Iow transitions of the clock input.

Output of the + 2 counter.
Qs, QC, QD (Pins 5, 6, 7, 9, 10, 11)

CONTROL INPUTS

Outputs of the + 5 counter. 00 is the most significant bit.
OA is the least significant bit when the counter is connected
for BCD output as in Figure 4. OB is the least significant bit
when the counter is operating in the bi-quinary mode as in
Figure 5.

Reset (Pins 2,14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip-flops, and forces OA through
00 low.

SWITCHING WAVEFORMS

CLOCK

VCC
RESET

GND

GND
tpHL
Q

Q

tree
CLOCK

Figure 1.

50%C=

VCC
GND

Figure 2.

TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev 6

3-415

MOTOROLA

[3J

MC54/74HC390
EXPANDED LOGIC DIAGRAM
CLOCKA ...;1~.1~5_ _ _-.Q>

---.--+'---.Q>

CLOCK S ....;4.:....;.1:;..2

TIMING DIAGRAM
(QA Connected to Clock B)

CLOCK A

RESET

Qs

Sl'--___________________________
-,
I

QC -,
I

QD -,
I

MOTOROLA

I

I

I

I

3-416

High-Speed CMOS Logic Data
DL129- Rev 6

MC54/74HC390
APPLICATIONS INFORMATION
Each half of the MC54174HC390 has independent + 2 and
+ 5 sections (except for the Reset function). The + 2 and + 5
counters can be connected to give BCD or bi-quinary (2-5)
count sequences. If Output QA is connected to the Clock B
input (Figure 4), a decade divider with BCD output is
obtained. The function table for the BCD count sequence is
given in Table 1.

Table 1. BCD Count Sequence"

To obtain a bi-quinary count sequence, the input signals
connected to the Clock B input, and output QD is connected
to the Clock A input (Figure 5). QA provides a 50% duty cycle
output. The bi-quinary count sequence function table is
given in Table 2.

Table 2. Bi-Quinary Count Sequence""

Output
Count

QD

QC

L
L
0
1
L
L
2
L
L
3
L
L
4
L
H
5
L
H
6
L
H
7
L
H
8
H
L
9
H
L
, OA connected to Clock B Input.

Output

QS

QA

Count

QA

QD

QC

QS

L
L
H
H
L
L
H
H
L
L

L
H
L
H
L
H
L
H

0
1
2
3
4
8
9
10
11
12

L
L
L
L
L
H
H
H
H
H

L
L
L
L
H
L
L
L
L
H

L
L
H
H
L
L
L
H
H
L

L
H

L

H

L

H
L
L
H
L
H
L

"aD connected to Clock A input.

CONNECTION DIAGRAMS
CLOCK A _ _I"""1;,..;.5--01>

CLOCKB

3,13

QA

5,11

QB

CLOCKB ~4"",12"--i-<:I> +5
COUNTER

+5 1-_6
"",,;.:10,- QC
COUNTER
7, 9 QD

1

QD

RESET _2::...:.;;14'--<~_--1

Figure 4. BCD Count

High-Speed CMOS Logic Data
DL129-Rev 6

QA

5,11 QB
6,10 QC
7,9

2,14

RESET

3,13

CLOCK A

Figure 5. Bi-Quinary Count

3-417

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC390A

Product Preview

Dual 4-Stage Binary
Ripple Counter with
+ 2 and + 5 Sections

JSUFFIX
CERAMIC PACKAGE
CASE 620-10

High-Performance Silicon-Gate CMOS
The MC54174HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 4-bit counters, each composed
of a divide-by-two and a divide-by-five section. The divide-by-two and
divide-by-five counters have separate clock inputs, and can be cascaded to
implement various combinations of + 2 and/or + 5 up to a + 100 counter.
Flip-flops internal to the counters are triggered by high-to-Iow transitions
of the clock input. A separate, asynchronous reset is provided for each 4-bit
counter. State changes of the Q outputs do not occur simultaneously
because of internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used as clocks or strobes
except when gated with the Clock of the HC390A.
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard

•

Chip Complexity: 244 FETs or 61 Equivalent Gates

N SUFFIX
PLASTIC PACKAGE
CASE 641Hl8

DSUFFIX
SOIC PACKAGE
CASE 7518-05
DTSUFFIX
TSSOP PACKAGE
CASE 948F-{)1
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Ceramic
Plastic
SOIC
TSSOP

N07A

PIN ASSIGNMENT
CLOCK Aa
RESET a

LOGIC DIAGRAM

1•

16 ~ VCC

2

15

CLOCKAb

14

RESETb

QAa I

. CLOCK A

+2
COUNTER

1,15

CLOCK Sa [ 4

13

QAb

QSa

12

CLOCKSb

QCa

11

QSb

QOa

10

QCb

3,13 QA

GNO

8

QOb

5,11 Qs
CLOCKS

4,12

--'.!..:.:..-+-ct>

+5
COUNTER

6,10 QC
7,9 Qo

FUNCTION TABLE
Clock

RESET ---=2"-,1:.;:,4....._ _-1
PIN 16= VCC
PIN8=GND

A

B

Reset

Action

X

X

H

\...

X

L

X

\...

L

Reset
+2and+5
Increment
+2
Increment
+5

This document contains inlonnation on a product under development. Motorola reserves the right
to change or discontinue this product without notice.

10/95

© Motorola, Inc. 1995

3-418

REV 0

®

MOTOROLA

MC54/74HC390A
MAXIMUM RATINGS'
Symbol
VCC
Vin
Vout

Parameter

Value

Unit

-0.5to+7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

-65 to+ 150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static vo~ages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,,;; (Vin or Vout) ,,;; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: - 7 mWI'C from 65° to 125°C
TSSOP Package: -6.1 mW/oCfrom 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC

Vin, Vout

Parameter
DC Supply

Vo~age

(Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time
(Figure 1)

DC ELECTRICAL CHARACTERISTICS

VCC=2.0V
VCC=3.0V
VCC = 4.5 V
VCC=6.OV

Min

Max

2.0

6.0

Unit
V

0

VCC

V

-55

+ 125

°c

0
0
0
0

1000
600
500
400

ns

(Vo~ages Referenced to GND)

Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

,,;; 85°C

,,;; 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
lIoutl ,,;; 20 (.IA

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 VorVCC -0.1 V
lIoutl ,,;; 20 (.IA

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl ,,;; 20J.1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl ,,;; 2.4 mA
lIoutl ,,;; 4.0 rnA
lIoutl ,,;; 5.2 rnA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

VOH

High-Speed CMOS Logic Data
DL129-Rev6

3-419

MOTOROLA

MC54f74HC390A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

lin
ICC

VCC
V

-55to
25'C

oS B5°C

oS 125°C

Unit

Vin = VIH or VIL
1I0uti oS 20 IlA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Vin = VIH or VIL 1I0uil ::S 2.4 rnA
Iioutl ::S 4.0 rnA
1I0uti ::S 5.2 rnA

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0!lA

6.0

4

40

160

!lA

VCC
V

-55to
25°C

Parameler

Test Conditions

Maximum Low-Level Output
Voltage

NOTE: Information on tYPical parametric values can be found In Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = If = 6 ns)
Guaranteed Limit
Symbol

::S B5°C

::S 125°C

Unil

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)

2.0
3.0
4.5
6.0

10
15
30
50

9
14
28
45

8
12
25
40

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)

2.0
3.0
4.5
6.0

70
40
20
16

80
45
25
21

90
50
30
27

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)

2.0
3.0
4.5
6.0

200
160
35
30

250
185
45
40

300
210
60
50

ns

tPLH,
tpHL

Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)

2.0
3.0
4.5
6.0

70
40
20
16

80
45
25
21

90
50
30
27

ns

tPLH,
tpHL

Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)

2.0
3.0
4.5
6.0

90
56
32
25

105
70
38
31

180
100
45
40

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)

2.0
3.0
4.5
6.0

70
40
20
16

80
45
25
21

90
50
30
27

ns

tpHL

Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)

2.0
3.0
4.5
6.0

80
48
28
21

95
65
32
25

110
75
40
30

ns

MOTOROLA

Parameter

3-420

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC390A
AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Input tl = tl = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

Maximum Output Transition lime, Any Output
(Figures 1 and 3)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
15

110
36
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol
trlH,
tTHL

Cin

Parameter

s

85°e

s

125°e

Unit

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Inlormation on typical parametric values can be lound in Chapter 2.
Typical
Power Dissipation Capacitance (Per Counter)'

@

25°e, Vee

=5.0 V

35

'Used to determine the no-load dynamic power consumption: PD = CPD VCC 21 + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tl = 6 ns)
Guaranteed Limil
Vee
V

-5510
25°e

s 85°e

s 125°e

Unit

Minimum Recovery lime, Reset Inactive to Clock A or Clock B
(Figure 2)

2.0
3.0
4.5
6.0

25
15
5
5

30
20
6
5

40
30
10
7

ns

tw

Minimum Pulse Width, Clock A, Clock B
(Figure 1)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
15

110
36
22
19

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
15

110
36
22
19

ns

Maximum Input Rise and Fall limes
(Figure 1)

2.0
3.0
4.5
6.0

1000
800
500
400

1000
800
500
400

1000
800
500
400

ns

Symbol
trec

II,tl

Parameler

NOTE: Inlormatlon on typical parametric values can be lound

High-Speed CMOS Logic Data
Dl129-Rev6

In Ch~pter

3-421

2.

MOTOROLA

MC54i74HC390A
PIN DESCRIPTIONS
INPUTS

OUTPUTS

Clock A (Pins 1, 15) and Clock B (Pins 4, 15)

QA (Pins 3, 13)

Clock A is the clock input to the + 2 counter; Clock B is the
clock input to the + 5 counter. The internal flip-flops are
toggled by high-te-Iow transitions of the clock input.

Output of the '+ 2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)

CONTROL INPUTS

Outputs of the + 5 counter. 00 is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi-quinary mode as in
Figure 5.

Reset (Pins 2,14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip-flops, and forces QA through
QOlow.

SWITCHING WAVEFORMS

CLOCK

VCC
RESET

GND

' - - - - GND

Q
Q

---------:.=-=---. I
Figure 1.

-

50%~

CLOCK

VCC
GND

Figure 2.

TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 3.

•

MOTOROLA

3-422

High-Speed CMOS Logic Data

DL129-Rev6

MC54/74HC390A
EXPANDED LOGIC DIAGRAM
CLOCKA ....;1:!..:,1..:..5_ _ _-

1::.,.2--.-+_-<1>

CLOCK B ....;4,-,-,

Q

TIMING DIAGRAM

(QA Connected to Clock B)

10111213141516171819101112131415161
CLOCK A

RESET

QB

JI____________________________

-,

QC -;
QD

I

I

-l

High-Speed CMOS Logic Data

DL129-Rev6

I

I

3-423

MOTOROLA

MC54/74HC390A
APPLICATIONS INFORMATION
Each half of the MC54174HC390A has independent + 2
and + 5 sections (except for the Reset function). The + 2 and
+ 5 counters can be connected to give BCD or bi-quinary
(2-5) count sequences. If Output QA is connected to the
Clock B input (Figure 4), a decade divider with BCD output is
obtained. The function table for the BCD count sequence is
given in Table 1.

To obtain a bi-quinary count sequence, the input signals
connected to the Clock B input, and output QD is connected
to the Clock A input (Figure 5). QA provides a 50% duty cycle
output. The bi-quinary count sequence function table is
given in Table 2.

Table 1. BCD Count Sequence·

Table 2. Bi-Quinary Count Sequence··

Output

Output

Count

QO

QC

QS

QA

0
1
2

L
L
L
L
L
L
L
L
H
H

L
L
L
L
H
H
H
H
L
L

L
L
H
H
L
L
H
H
L
L

L
H
L
H
L
H
L
H
L
H

3
4
5
6

7

8
9
• QA connected to Clock S input.

Count

QA

QO

L
L
L
L
L
L
L
3
L
H
4
L
8
H
L
9
H
L
10
H
L
11
H
L
12
H
H
•• QD connected to Clock A input.
0
1
2

QC

QS

L
L
H
H
L
L
L
H
H
L

L
H
L
H
L
L
H
L
H
L

CONNECTION DIAGRAMS
1,15

CLOCK A

+2
COUNTER

1,15

3,13

CLOCK A

,------I
CLOCKB

RESET

I

5,11

4,12
+5
COUNTER
2,14

6,10

7,9

OB

CLOCKB

4 12

Oc

I

2 14

RESET'

3,13

----.J
5,11
+5
COUNTER

00

Figure 4. BCD Count

MOTOROLA

I

I
+2
COUNTER

.1

6,10

7,9

OB

Oc
00

I

Figure 5. Bi-Quinary Count

3-424

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC393

Dual 4-Stage
Binary Ripple Counter
High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 632-08

The MC54174HC393 is identical in pinout to the LS393. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTIL outputs.
This device consists of two independent 4-bit binary ripple counters with
parallel outputs from each counter stage. A + 256 counter can be obtained
by cascading the two binary counters.
Intemal flip-flops are triggered by high-to-Iow transitions of the clock
input. Reset for the counters is asynchronous and active-high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393.

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A-D3

• Output Drive Capability: 10 LSTIL Loads
• Outputs Directly Interface to CMOS, NMOS, and TIL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 f..lA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 236 FETs or 59 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

Ceramic
Plastic
SOIC

PIN ASSIGNMENT

LOGIC DIAGRAM

3,11
CLOCK

1,13

BINARY
COUNTER

4,10
5,9

6,8

RESET

2,12

CLOCK a [ 1·

14

VCC

RESET a [ 2

13

CLOCKb

01a [ 3

12

RESETb

02a [ 4

11

01b

01

03a [ 5

10

02b

02

04a [ 6

9

03b

GND [ 7

8

04b

Q3

04

I
FUNCTION TABLE
PIN 14= VCC
PIN7=GND

Inputs

Clock

Reset

Outputs

X
H
L

H
L
L
L
L

L
No Change
No Change
No Change
Advance to
Next State

..r
""\...

10195

© Motorola, Inc. 1995

3-425

REV 6

®

MOTOROl.A

MC54/74HC393
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Vollage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC+ 1.5

Vout

DC Output Voltage (Referenced to GND)

-0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65 to + 150

°c

lin

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic or SOIC DIP)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND S (Vin or Vout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or Vce).
Unused outputs must be left open.

°c
260
300

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mWI"C from 100° to 125°C
SOIC Package: - 7 mWI"C from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input 'Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°e

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

S 85°C

S 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
lIoutl S 20 J.lA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.l VorVcc-O.l V
lIoutl S 20J.lA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl S 20 J.lA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl S 4.0 rnA
lIoutl S 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
lIoutl S 20J.lA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL
lin
ICC

lIoutl S 4.0 rnA
lIoutl S 5.2 rnA

V

Maximum input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

J.IA

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 J.lA

6.0

8

80

160

J.lA

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-426

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC393
AC ELECTRICAL CHARACTERISTICS (CL

=50 pF, Input tr =tf =6 ns)
Guaranteed Limit

Symbol

Parameter

Vee
V

-55to
25°e

s

85°e

s

125°e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)

2.0
4.5
6.0

5.4
27
32

4.4
22
26

3.6
18
21

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to 01
(Figures 1 and 3)

2.0
4.5
6.0

120
24
20

150
30
26

180
36
31

ns

tPLH,
tpHL

Maximum Propagation Delay, Clock to 02
(Figures 1 and 3)

2.0
4.5
6.0

190
38
32

240
48
41

285
57
48

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock to 03
(Figures 1 and 3)

2.0
4.5
6.0

240
48
41

300
60
51

360
72
61

ns

tPLH,
tpHL

Maximum Propagation Delay, Clock to 04
(Figures 1 and 3)

2.0
4.5
6.0

290
58
49

365
73
62

435
87
74

ns

tpHL

Maximum Propagation Delay, Reset to any 0
(Figures 2 and 3)

2.0
4.5
6.0

165
33
28

205
41
35

250
50
43

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Counter),

=5.0 V

40

• Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°C

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol
trec

tr,tf

Parameter

s

85°C

s

125°e

Unit

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-427

MOTOROLA

MC54/74HC393
PIN DESCRIPTIONS
INPUTS

vided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.

Clock (Pins 1, 13)
Clock input. The internal flip-flops are toggled and the
counter state advances on high-to-Iow transitions of the
clock input.

OUTPUTS

CONTROL INPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)

Reset (Pins 2, 12)
Active-high, asynchronous reset. A separate reset is pro-

Parallel binary outputs Q4 is the most significant bit.

SWITCHING WAVEFORMS

-VCC

RESET

GND

'"----GND
Q

CLOCK

Figure 1.

--------~t=
50%

VCC

GND

Figure 2.
EXPANDED LOGIC DIAGRAM

TEST
POINT
OUTPUT

CLOCK --:.:.1,..:.;13'--_ _ _ _ _a>

DEVICE

UNDER
TEST

• Includes all probe and jig capacitance

Figure 3. Test Circuit

MOTOROLA

3--428

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC393
TIMING DIAGRAM

o

I

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I 10 I 11 I

12

I 13 I 14 I 15 I

0

I

CLOCK
RESET

.Jl_____________________________

Q2

-i

03

-i

L
L
L

04 -;

COUNT SEQUENCE
Outputs
Count

04

03

02

01

0
1
2

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

3
4
5
6
7
8
9

10
11
12
13
14
15

High-Speed CMOS Logic Data
DL129-Rev6

3-429

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC393A

Product Preview

Dual 4-Stage
Binary Ripple Counter

J SUFFIX
CERAMIC PACKAGE
CASE 632-QS

High-Performance Silicon-Gate CMOS
The MC54/74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with puliup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 4-bit binary ripple counters with
parallel outputs from each counter stage. A + 256 counter can be obtained
by cascading the two binary counters.
Internal flip-flops are triggered by high-to-Iow transitions of the clock
input. Reset for the counters is asynchronous and active-high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393A.

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A-Q3
DTSUFFIX
TSSOP PACKAGE
CASE 94SG-Q1

•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 ~
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 236 FETs or 59 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

PIN ASSIGNMENT

LOGIC DIAGRAM

3,11
CLOCK

1,13

BINARY
COUNTER

4,10

5,9
6,8

RESET

2,12

Ceramic
Plastic
SOIC
TSSOP

PVCC
PCLOCK b
12 PRESETb
11 P01b
10 P02b
9 PQ3b

CLOCK a

1-

14

RESET a

2

13

Ql

Q1a

3

Q2

Q2a

4

Q3

Q3 a

5

Q4a

6

Q4

I

GND [ 7

PIN 14= VCC
PIN 7 = GND

8

PQ4b

FUNCTION TABLE
Inputs
Clock

Reset

X
H

H

L

L
L
L
L

No Change
NoChange
No Change
Advance to
Next State

L
J

"\..

Outputs

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10195

© Motorola, Inc. 1995

3-430

REVO

®

MOTOROLA

MC54174HC393A
MAXIMUM RATINGS·
Parameter

Value

Unit

- 0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5toVCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

mA
mA

Symbol
VCC
Yin
Vout
lin

DC Supply Voltage (Referenced to GND)

DC Input Current, per Pin

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOlC Packaget
TSSOP Packaget

750
500
450

mW

Tstg
TL

- 65 to + 150

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOlC or TSSOP Package
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be lell open.

"C
"C

260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/"C from 65" to 125"C
Ceramic DIP: -10 mW/"C from 100" to 125"C
SOlC Package: - 7 mWI"C from 65" to 125"C
TSSOP Package: -6.1 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

2.0

6.0

V

0

VCC

V

-55

+ 125

"C

0
0
0
0

1000
600
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fa" Time
(Figure 1)

VCC=2.0V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V

Unit

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25"C

s 85"C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
"outl s 20 !LA

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
"outl s 20 !LA

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.80

0.5
0.9
1.35
1.80

0.5
0.9
1.35
1.80

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
"outl s 20 !LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

VOH

Parameter

VCC
V

Yin = VIH or VIL

High-Speed CMOS Logic Data
DL129-Rev6

"outl :s; 2.4 mA
"outl :s; 4.0 mA
"outl :s; 5.2 mA

3-431

MOTOROLA

MC54174HC393A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

lin
ICC

Parameter

Test Conditions

=

Maximum Low-Level Output
Voltage

Vin VIH or VIL
lIoutl s 20~
Vin

=VIH or VIL

Maximum Input Leakage Current

Vin

Maximum Quiescent Supply
Current (per Package)

Vin VCC or GND
lout 0 ~A

=VCC or GND
=
=

lIoutl s 2.4 rnA
lIoutl s 4.0 rnA
lIoutl s 5.2 rnA

Vce
V

-55to
25°C

s 85°C

s 125°C

Unit

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

6.0

:to.1

±1.0

±1.0

~

6.0

4

40

160

~

VCC
V

-55to
25°e

s 85°e

s 125°e

Unit

NOTE: Information on tYPical parametric values can be found In Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Inputtr =tf =6 ns)
Guaranteed Limit
Symbol

Parameter

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)

2.0
3.0
4.5
6.0

10
15
30
50

9
14
28
45

8
12
25
40

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)

2.0
3.0
4.5
6.0

70
40
20
16

80
45
25
21

90
50
30
27

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)

2:0
3.0
4.5
6.0

90
56
32
25

105
70
38
31

180
100
45
40

ns

tpLHo
tpHL

Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)

2.0
3.0
4.5
6.0

60
40
30
25

75
55
40
35

90
65
50
42

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)

2.0
3.0
4.5
6.0

200
160
35
30

250
185
45
40

300
210
60
50

ns

tpHL

Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)

2.0
3.0
4.5
6.0

80
48
28
21

95
65
32
25

110
75
40
30

ns

ITLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee = 5.0 V
Power Dissipation Capacitance (Per Counter)'

35

'Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-432

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC393A
TIMING REQUIREMENTS (Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

:s 85°e

:s 125°e

Unit

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
3.0
4.5
6.0

25
15
5
5

30
20
6
5

40
30
10
7

ns

tw

Minimum Pulse Widlh, Clock
(Figure 1)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
15

110
36
22
19

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
15

110
36
22
19

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
3.0
4.5
6.0

1000
800
500
400

1000
800
500
400

1000
800
500
400

ns

Symbol
trec

t r, tf

Parameter

NOTE: Information on typical parametric values can be found

High-Speed CMOS Logic Data
DL129-Rev6

In

Chapter 2.

3-433

MOTOROLA

MC54/74HC393A
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)

vided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.

Clock input. The internal flip-flops are toggled and the
counter state advances on high-to-Iow transitions of the
clock input.

OUTPUTS

CONTROL INPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)

Reset (Pins 2,12)
Active-high, asynchronous reset. A separate reset is pro-

Parallel binary outputs Q4 is the most significant bit.

SWITCHING WAVEFORMS

-VCC

RESET

CLOCK

GND

'-----GND

Q
Q

50%

CLOCK

Figure 1.

C

VCC
GND

Figure 2.
EXPANDED LOGIC DIAGRAM

TEST
POINT
OUTPUT

CLOCK _1.:.:.•.:;13:......._ _ _ _ _-0>

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 3. Test Circuit

MOTOROLA

3-434

High-Speed CMOS logic Data
Dl129-Rev6

MC54/74HC393A
TIMING DIAGRAM

o

I

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

I

11

12

I

13

I

14

I

15

I

0

I

CLOCK

RESET ~L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

L
L
L

02 -;
03 -,
I

04

-1
COUNT SEQUENCE
Outputs

High-Speed CMOS Logic Data
DL129-Rev6

Count

Q4

Q3

Q2

Q1

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

3-435

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC533A

Octal3-State
Inverting D Flip-Flop
High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 732-03

The MC54f74HC533A is identical in pinout to the LS533. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (Le., the outputs change
asynchronously) when Latch Enable is high. The Data appears at the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC533A is identical in function to the HC563 but has the data inputs
on the opposite side of the package from the outputs to facilitate PC board
layout.
This device is similar in function to the HC373A, which has noninverting
outputs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 738-03

OW SUFFIX
SOIC PACKAGE
CASE 7511)..{)4
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 !!A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 256 FETs or 64 Equivalent Gates

PIN ASSIGNMENT
OUTPUT
ENABLE

LOGIC DIAGRAM

DO 3
01 4
02 7
DATA
INPUTS

03 8
04 13

Ceramic
Plastic
SOIC

1-

20

VCC

QO

2

19

07

DO

3

18

07

D1[ 4

17 J 06

01 [ 5

16 ] 06

02 [ 6

15 ] 05

02 [ 7

14 ] 05

03 [ 8

13 ~ 04

03 [ 9

12

uQ4

GNO [ 10

11

J LATCH

INVERTING
OUTPUTS

ENABLE

05 14

FUNCTION TABLE

06 17

Inputs

07 18

LATCH ENABLE 11
OUTPUT ENABLE -'1_ _ _ _--'

PIN 20 = Vcc
PIN10=GNO

Output

Output
Enable

Latch
Enable

D

Q

L
L
L
H

H
H
L
X

H
L
X
X

L
H
No Change
Z

X = Don't Care
Z = High Impedance

10195

© Motorola, Inc. 1995

3-436

REV 2

®

MOTOROLA

MC54/74HC533A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to+ 7.0

V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to Vce + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±35

mA

ICC

DC Supply Current, Vee and GND Pins

±75

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+150

'c

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s Vec.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or Vec).
Unused outputs must be left open.

'c
260
300

• MaXimum Ratings are those values beyond which damage to the deVice may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol
VCC
Vin, Vout

Min

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+125

'c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
lIoutl s 2Ol1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCc-O.l V
lIoutl s 2Ol1A

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
"outl s 2Ol1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

V

Vin = VIH or VIL
lIoutl s 2Ol1A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Vin = VIH or VIL
IIoutl s 6.0 mA
"outl s 7.8 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

V

Vin = Vee or GND

6.0

±0.1

±1.0

±1.0

I!A

Symbol

VOH

Parameter

Test Conditions

Vin = VIH or VIL
IIoutl s 6.0 mA
lIoutl s 7.8 mA
VOL

lin

Maximum Low-Level Output
Volt.age

Maximum Input Leakage Current

High-Speed CMOS Logic Data
DL129-Rev6

3-437

MOTOROLA

MC54/74HC533A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed limit
VCC
V

-55to
25'C

s

s

Symbol

Parameter

Test Conditions

125'C

Unit

IOZ

Maximum Three-State leakage
Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

IlA

ICC

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
1I0uti = 0 J.IA

6.0

4.0

40

160

J.IA

VCC
V

-55to
25'C

85'C

NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed limit
Symbol

s 85'C

s 125'C

Unit

tpLH
tpHL

Maximum Propagation Delay, Input 0 to Q

Parameter

Fig.
1,5

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tPLH
tPHL

Maximum Propagation Delay, Latch Enable to Q

2,5

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

tPLZ
tpHZ

Maximum Propagation Delay, Output Enable to Q

3,6

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpZL
tpZH

Maximum Propagation Delay, Output Enable to Q

3,6

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

ITlH
ITHL

Maximum Output Transition Time, Any Output

1,5

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Tri-State Output Capacitance (Output in Hi-Impedance State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical
Power Dissipation Capacitance (Per Enabled Output)"

25°C, VCC

=5.0 V

36

"Used to determine the no-load dynamic power consumption: Po

MOTOROLA

@

=CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

3-438

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC533A
TIMING REQUIREMENTS (Cl = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Fig.

Parameter

Vee
Volts

-55 to 25°C
Min

Max

:s 85°C
Min

Max

:s 125°C
Min

Max

Unit

tsu

Minimum Setup lime, Input D to latch Enable

4

2.0
4.5
6.0

25
5.0
5.0

30
6.0
6.0

40
8.0
7.0

ns

th

Minimum Hold Time, latch Enable to Input D

4

2.0
4.5
6.0

5.0
5.0
5.0

5.0
5.0
5.0

5.0
5.0
5.0

ns

tw

Minimum Pulse Width, latch Enable

2

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

tr,tl

Maximum Input Rise and Fall limes

1

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

SWITCHING WAVEFORMS

r---VCC

INPUT 0

-VCC

' - - - - - - - GND

Q

Q

trLH

Figure 1.

Figure 2.
~---VCC

VALID
VCC
HIGH
IMPEDANCE

INPUTO

50%

I-LATCH
ENABLE

tsu

......

\w.

th-

I~ GND
VCC

' - - - - - - - - GND
HIGH
IMPEDANCE

Figure 3.

High-Speed CMOS logic Data
DL129-Rev6

Figure 4.

3-439

MOTOROLA

MC54/74HC533A
TEST CIRCUITS
TEST POINT

TEST POINT

OUTPUT

OUTPUT
DEVICE
UNDER
TEST

'Y

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

1 kQ

I

CONNECTTO VCC WHEN
TESTING tPLZ AND tpZL
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH

• Includes all probe and jig capacitance

Figure 5.

Figure 6.

EXPANDED LOGIC DIAGRAM

LATCH
ENABLE
OUTPUT
ENABLE

MOTOROLA

3-440

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC534A

Octal 3-State
Inverting D Flip-Flop
High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 732-03

The MC54174HC534A is identical in pinout to the LS534. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked, in inverted form, to the outputs
with the rising edge of the Clock. The Output Enable input does not affect the
states of the flip-flops, but when Output Enable is high, the outputs are
forced to the high impedance state. Thus, data may be stored even when the
outputs are not enabled.
The HC534A is identical in function to the HC564 which has the data
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
This device is similar in function to the HC374A, which has noninverting
outputs.

N SUFFIX
PLASTIC PACKAGE
CASE 738...{)3

ORDERING INFORMATION

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 ~A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
• Chip Complexity: 282 FETs or 68.5 Equivalent Gates

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
OUTPUT [ 1ENABLE
QO [ 2

LOGIC DIAGRAM

DO 3

DATA
INPUTS

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

20#1

20 ] VCC
19 ] Q7

00 [ 3

18 j 07

01[ 4

17 J 06

Q1 [ 5

16 1 Q6

Q2[ 6

15 ] Q5

D1 4

02 [ 7

14 ] 05

D2 7

03 [ 8

13 J 04

Q3 [ 9

12 J Q4

D3 8
D4 13

INVERTING
OUTPUTS

GND [ 10

11 ] CLOCK

D5 14
06 17
07 18

FUNCTION TABLE
Output
Enable

OUTPUT ENABLE _1_ _ _ _----'

Output

Inputs

CLOCK 11

L
L
L
H

PIN 20= VCC
PIN 10=GNO

Clock

D

Q

J
J

H
L
X
X

L
H
No Change
Z

L,H,~

X

X = Don't Care
Z = High Impedance

10195

© Motorola, Inc. 1995

3-441

REVS

®

MOTOROLA

MC54/74HC534A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

- 1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65to+150

"C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

lin

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

"C
260
300

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65" to 125"C
Ceramic DIP: -10 mW/"C from 100" to 125"C
SOIC Package: -7 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Falll1me
(Figure 1)

VCC=2.0V
VCC=4.5 V
VCC = 6.0 V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

"C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25"C

s 85"C

s 125"C

Unit

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
1I0uti s 20 I!A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
1I0uti s 20 itA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20 I!A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

V

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

Yin = VIH or VIL
1I0uti s 6.0 rnA
1I0uti s 7.8 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

V

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

I!A

VOH

Parameter

VCC
V

Yin = VIH or VIL
1I0uti s 6.0 rnA
1I0uti s 7.8 rnA
VOL

lin

MOTOROLA

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

Yin = VIH or VIL
1I0uti s 20 itA

3-442

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC534A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Vee
V

-55to
25°C

Symbol

Parameter

Test Conditions

,;; 85°C

s 125°C

Unit

IOZ

Maximum Three-State leakage
Current

Output in High-Impedance State
Vin =Vil or VIH
Vout =VCC or GND

6.0

±0.5

±5.0

±10

/lA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin =VCC or GND
lIoutl =0 flA

6.0

4.0

40

160

/lA

Vee
V

-55to
25°C

NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (Cl =50 pF, Inputtr =tf =6.0 ns)
Guaranteed limit

s 85°C

s 125°C

Unit

4.0
20
24

MHz

35

5.0
24
28

125
25
21

155
31
26

190
38
32

ns

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

2,5

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

1,4

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

10

10

10

pF

Maximum Tri-State Output Capacitance (Output in Hi-Impedance State)

15

15

15

pF

Symbol

Parameter

Fig.

f max

Maximum Clock Frequency (50% Duty Cycle)

1,4

2.0
4.5
6.0

6.0
30

tplH
tpHl

Maximum Propagation Delay, Clock to Q

1,4

2.0
4.5
6.0

tpLZ
tpHZ

Maximum Propagation Delay, Output Enable to Q

2,5

tpZl
tpZH

Maximum Propagation Delay, Output Enable to Q

tTLH
ITHl

Maximum Output Transition Time, Any Output

Cin
COUT

NOTE: For propagation delays with loads other than 50 pF, and Information on tYPical parametric values, see Chapter 2.
Typical @ 25°C, Vee
Power Dissipation Capacitance (Per Flip-Flop)"

=5.0 V

34

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (CL =50 pF, Inputtr =tf =6.0 ns)
Guaranteed Limit
Parameter

Symbol

Fig,

Vee
Volts

-55to 25°C
Min

Max

s
Min

85°C
Max

s
Min

125°C
Max

Unit

tsu

Minimum Setup Time, Data to Clock

3

2.0
4.5
6.0

50
10
9.0

65
13
11

75
15
13

ns

th

Minimum Hold Time, Ciock to Data

3

2.0
4.5
6.0

5.0
5.0
5.0

5.0
5.0
5.0

5.0
5.0
5.0

ns

tw

Minimum Pulse Width, Clock

1

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Maximum Input Rise and Fall Times

1

2.0
4.5
6.0

tr,tf

High-Speed CMOS Logic Data
DL129-Rev6

3-443

1000
500
400

1000
500
400

1000
500
400

ns

MOTOROLA

MC54/74HC534A
SWITCHING WAVEFORMS
,.---VCC
OUTPUT
ENABLE
CLOCK
HIGH
IMPEDANCE

o
o

o

HIGH
IMPEDANCE

Figure 1.

Figure 2.

Vce
DATA
GND

'L::

CLOCK

Figure 3.

TEST CIRCUITS
TEST POINT

TEST POINT
1 kn
...O_U_T_PU_T_+-'l/lJ'\r-_

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

'v-

'- CL'

I

CONNECTTO VCC WHEN
TESTING tPLZ AND tpZL
CONNECTTO GND WHEN
TESTING tpHZ AND tpZH

I
• Includes all probe and jig capacitance

Figure 4.

Figure 5.
EXPANDED LOGIC DIAGRAM

CLOCK
OUTPUT
ENABLE

02

MOTOROLA

03

3-444

05

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC540A

Octal 3-State Inverting Buffer/
Line Driver/Line Receiver
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

The MC74HC540A is identical in pinout to the LS540. The device inputs
are compatible with Standard CMOS outputs. External pullup resistors make
them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driverlline receiver designed
to be used with 3-state memory address drivers, clock drivers, and other
bus-----.d :

~OUTPUTy

INPUT A

Lt:=[:J------.J ~ :I
---------------1

OE1
OE2

MOTOROLA

3-452

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HCT541A

Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

High-Performance Silicon-Gate CMOS
The MC74HCT541 A is identical in pinout to the LS541. This device may
be used as a level converter for interfacing TTL or NMOS outputs to high
speed CMOS inputs.
The HCT541 A is an octal non-inverting buffer/line driver/line receiver
designed to be used with 3-state memory address drivers, clock drivers, and
other bus-oriented systems. This device features inputs and outputs on
opposite sides of the package and two ANDed active-low output enables.
•
•
•
•
•
•
•

1

ORDERING INFORMAnON
MC74HCTXXXAN
MC74HCTXXXADW

Output Drive Capability: 15 LSTTL Loads
TTUNMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5V
Low Input Current: 1j.tA
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates

Inputs
OutputY

A1

A3

Data
Inputs

A4
As

A6
A7
AS

Plastic
SOIC

FUNCTION TABLE

LOGIC DIAGRAM

A2

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

20~

OEI

OE2

A

L

L

L

L

L

L

H

H

H

X

X

X

H

X

Z
Z

Z = High Impedance
X = Don't Care

3

4
s
Non-Inverting
Outputs

6
7
S
9

Pinout: 2D-Lead Packages (Top View)
~

Output [OE1 1
Enables . OE2
19

W

~

n

10195

© Motorola, Inc. 1995

n

~

~

~

~

~

PIN20= Vee
PIN 10= GND

3-453

REV 1

®

MOTOROLA

MC?4HCT541 A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V

Vin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±35

mA

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature Range

- 65 to + 150

°c

TL

Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND S (Vin or Vout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

°c

0

500

ns

DC Supply Voltage (Referenced to GND)
DC Input Vo~age, Output Voltage (Referenced to GND)

TA

Operating Temperature Range, All Package Types

tr,tf

Input Rise/Fall TIme (Figure 1)

DC CHARACTERISTICS (Voltages Referenced to GND)

VIH
VIL
VOH

-55 to 25°C

:5B5°C

:5125°C

Unit

2.0
2.0

2.0
2.0

2.0
2.0

V

lIoutl:520~

4.5
5.5

Maximum Low-Level Input Voltage

Vout = 0.1V orVCC- O.IV
1I0uti :5 2OIlA

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output

Vin = VIH or VIL
1I0uti :5 20!LA

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

4.5

3.98

3.84

3.70

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Parameter
Minimum High-Level Input Voltage

Vo~age

Condition
Vout = 0.1V or VCC -0.1V

Vin = VIH or VIL
VOL

Guaranteed Limit

VCC
V

Symbol

Maximum Low-Level Output
Voltage

1I0uti :5 6.0mA

Vin = VIH or VIL
1I0uti :5 20!LA

V

4.5

0.26

0.33

0.40

lin

Maximum Input Leakage Current

Vin = VCC or GND

5.5

±0.1

±1.0

±I.O

IlA

IOZ

Maximum Three-State Leakage
Current

Output in High Impedance State
Vin = VIL or VIH
Vout = VCC or GND

5.5

±C.5

±5.0

±10.0

!LA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = OIlA

5.5

4

40

160

!LA

Additional Quiescent Supply Current

Vin = 2.4V, Any One Input
Vin = VCC or GND, Other Inputs
10ut=01lA

Vin = VIH or VIL

.t\ICC

1I0uti :5 6.0mA

~-55°C

5.5

2.9

I

I

25 to 125°C
2.4

mA

1. Information on typical parametric values can be found In Chapter 2.
2. Total Supply Current = ICC + l:h.ICC.

MOTOROLA

3-454

High-Speed CMOS Logic Data
DL129-Rev6

MC74HCT541A

AC CHARACTERISTICS (V CC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

-55 to 25°e

0505°e

05125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)

23

28

32

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)

30

34

38

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)

30

34

38

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output
(Figures 1 and 3)

12

15

18

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three-State Output Capacitance (Output in High Impedance
State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical

@

Power Dissipation Capacitance (Per Buffer)"

25°e, Vee

=5.0 V

55

'Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS

3.0V
GND
HIGH
IMPEDANCE

GND

VOL
VOH
HIGH
IMPEDANCE

Figure 1.

Figure 2.
TEST CIRCUITS

TEST
POINT

TEST
POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

1kQ

DEVICE
UNDER
TEST

CONNECTTO VCC WHEN
[ TESTING tpLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tpHZ and tpZH.

-='Includes all probe and jig capacitance

'Includes all probe and jig capacitance

Figure 3.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 4.

3-455

MOTOROLA

raJ

MC74HCT541A
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, AS, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) - Data input pins. Data on these pins appear in non-inverted form on the corresponding Y outputs, when the outputs are enabled.

puts are enabled and the device functions as a non-inverting
buffer. When a high voltage is applied to either input, the outputs assume the high impedance state.

OUTPUTS

CONTROLS

V1, V2, V3, V4, V5, V6, Y7, VB (PINS 18, 17, 16, 15, 14,
13, 12, 11) - Device outputs. Depending upon the state of

OE1, OE2 (PINS 1, 19) - Output enables (active-low).
When a low voltage is applied to both of these pins, the out-

the output enable pins, these outputs are either non-inverting outputs or high-impedance outputs.

LOGIC DETAIL
To 7 Other
Buffers

r------------------,
dI
VCC

lOne of Eight

I
I

I
I

Buffers

:J-t--

INPUT A

!+II

OUTPUTY

Lt~D-----1 '":t I
_ _ _ _ _ _ _ _ _ _ _ _-_.J

OE1
OE2

MOTOROLA

3-456

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC563

Octal 3-State Inverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The MC54174HC563 is identical in pinout to the LS563. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is identical in function to the HC533 but has the Data Inputs on
the opposite side of the package from the outputs to facilitate PC board
layout.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears at the outputs
in inverted form. When Latch Enable goes low, data meeting the setup and
hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC573 is the noninverting version of this function.

20

~
U·Yu1MfH gtl u
1

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

DWSUFFIX
SOIC PACKAGE
CASE 7510-04
ORDERING INFORMATION

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 ~A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 202 FETs or 50.5 Equivalent Gates

OUTPUT [ 1ENABLE
00 [ 2

02
OATA
INPUTS

03
04
05

4
5
6
7

06

19 100

01[ 3

18 ] 01

D2 [ 4

17 102
16 ] 03

04 [ 6

15 ] 04

01

05 [ 7

14 105

02

06 [ B

13 ] 06

07( 9

12 ] 07

03
04

INVERTING
OUTPUTS

11 ~ LATCH
ENABLE

GNO [ 10

05
06

07
LATCH
ENABLE
OUTPUT
ENABLE

20 , Vcc

03 [ 5
00

01

Ceramic
Plastic
SOIC

PIN ASSIGNMENT

LOGIC DIAGRAM
00

J SUFFIX
CERAMIC PACKAGE
CASE 732-03

07

FUNCTION TABLE

11

Output

Inputs

1

PIN 20= VCC
PIN 10=GNO

Output
Enable

Latch
Enable

D

Q

L
L
L
H

H
H
L
X

H
L
X
X

L
H
No Change
Z

X = don't care
Z = high impedance

10/95

© Motorola, Inc. 1995

3-457

REV 6

®

MOTOROLA

MC54174HC563
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

- 65 to + 150

°c

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -·7 mWI"C from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5 V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
lIoutl s 20llA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-O.l V
lIoutl s 20llA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 20llA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.\34
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

6.0

±0.1

±1.0

±1.0

. Symbol

VOH

Parameter

Test Conditions

Yin = VIH or VIL lIoutl
lIoutl
VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 20 !LA
Yin = VIH or VIL lIoutl
lIoutl

lin

MOTOROLA

Maximum Input Leakage Current

s 6.0 rnA
s 7.8 rnA

s 6.0 rnA
s 7.8 rnA

Yin = VCC or GND

3-458

V

!LA

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC563
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Vee
V

-55 to
25'e

Symbol

Parameter

Test Conditions

s 85'e

s 125'e

Unit

IOZ

Maximum Three-State Leakage
Current

Output in High-Impedance State
Vin = VIL or VIH
Vout = VCC orGND

6.0

±0.5

±5.0

±10

IlA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
10ut=01lA

6.0

8

80

160

IlA

Vee
V

-55to
25'e

NOTE: Information or, tYPical parametnc values can be found In Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit

s 85'e

s 125'e

Unit

tPLH,
tpHL

Maximum Propagation Delay, Input 0 to Q
(Figures 1 and 5)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLH,
tpHL

Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

trLH,
tTHL

Maximum Output Transition "Time, Any Output
(Figures 1 and 5)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-State Output Capacitance
(Output in High-Impedance State)

-

15

15

15

pF

Symbol

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per Latch),

=5.0 V

37

• Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3--459

MOTOROLA

MC54/74HC563
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

" 85°e

" 125°e

Unit

tsu

Minimum Setup TIme, Input D to Latch Enable
(Figure 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

th

Minimum Hold TIme, Latch Enable to Input D
(Figure 4)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Latch Enable
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
.24
20

ns

t r, If

Maximum Input Rise and Fall TImes
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

Parameter

NOTE: Information on tYPical parametric values can be found

In

Chapter 2.

SWITCHING WAVEFORMS

-VCC

VCC

lATCH
ENABLE

INPUTD
GND
tPlH

tPHl
Q

[3]

Q

50%

trlH

Figure 1.

Figure 2.
VCC

OUTPUT ENABLE

VCC
INPUTD

HIGH
IMPEDANCE

GND

Q

LATCH
ENABLE

GND

Q

Figure 3.

Figure 4.

TEST CIRCUITS
TEST POINT

TEST POINT

1 kn
1-0_U_T_PU_T_+-'VV'Ir-_

OUTPUT
DEVICE
UNDER
TEST

>

DEVICE
UNDER
TEST

Includes all probe and jig capacitance

>

Figure 5.

MOTOROLA

I

Cl'

I

CONNECT TO VCC WHEN
TESTING tpLZ AND tpZl.
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH.

Includes all probe and jig capacitance

FigureS.

3-460

High-Speed CMOS Logic Data
DL129-Rev6

High-Speed CMOS Logic Data
DL129-Rev6

3-461

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC564

Octal3-State
Inverting D Flip-Flop
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

The MC74HC564 is identical in pinout to the LS564. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is identical in function to the HC534A but has the flip-flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
Data meeting the setup time is clocked, in inverted form, to the outputs
with the rising edge of the Clock. The Output Enable input does not affect the
states of the flip-flops, but when Output Enable is high, all device outputs are
forced to the high-impedance state. Thus, data may be stored even when
the outputs are not enabled.
The HC564 is the inverting version of the HC574A.
•
•
•
•
•
•
•

OW SUFFIX
SOIC PACKAGE
CASE751~4

ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXDW

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 282 FETs or 70.5 Equivalent Gates

PIN ASSIGNMENT
OUTPUT
ENABLE
00

1-

20

~

2

19

PQO

LOGIC DIAGRAM

00
01
02
OATA
INPUTS

03
04
05
06
07

CLOCK
OUTPUT
ENABLE

3
4

5
6
7

VCC

01

3

02

4

18 DQ1
17D Q2

03

5

16

~

04

6

15

PQ4

05

Q3

7

14

DQ5

06 [ 8

13

Q6

QO

07 [ 9

12

Q7

Q1

GNO [ 10

11

CLOCK

Q2
Q3
Q4

INVERTING
OUTPUTS

FUNCTION TABLE

Q5

Inputs

Q6
9

Plastic
SOIC

Output
Enable

Q7

11

L
L
L
H

PIN 20 = VCC
PIN10=GNO

Output

Clock

D

Q

.r
.r

H
L
X
X

L
H
No Change

L,H,'X

Z

X = don't care
Z high impedance

=

10195

© Motorola, Inc. 1995

3-462

REV6

®

MOTOROLA

MC74HC564
MAXIMUM RATINGS'
Symbol
VCC
Yin
Vout

Parameter

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

Po

Power Dissipation in Still Air

750
500

mW

-65to+ 150

°c

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC = 4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit

V

-55 to
25°C

:5 85°C

:5 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
lIoutl :5 20 llA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.l VorVCC-O.l V
Iioutl :5 20 J.1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl :5 20 J.1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl :5 6.0 mA
lIoutl :5 7.8 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
lIoutl :5 20J.1A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL lIoutl :5 6.0 mA
lIoutl :5 7.8 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VCC
Symbol

VOH

VOL

Parameter

Maximum Low-Level Output
Voltage

Test Conditions

V

lin

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

J.1A

IOZ

Maximum Three-State Leakage
Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±S.O

±10

J.1A

ICC

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
10ut=0 J.1A

6.0

8

80

160

J.1A

NOTE: Information on tYPical parametnc values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3--463

MOTOROLA

MC74HC564
AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tPlH,
tpHl

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tPZl,
tpZH

Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

ITlH,
tTHl

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

10

10

10

pF

15

15

15

pF

Symbol

Cin
Cout

Parameter

-

Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'C, VCC

=5.0 V

38

Power Dissipation Capacitance (Per Flip-Flop)'

'Used to determine the no-load dynamic power consumption: Po = CPO Vce2f + ICC Vec. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

tsu

Minimum Setup Time, Data to Clock
(Figure 3)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Clock to Data
(Figure 3)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

t r, tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-464

High-Speed CMOS logic Data
DL129-Rev6

MC74HC564
SWITCHING WAVEFORMS

,---VCC
CLOCK

OUTPUT
ENABLE
HIGH
IMPEDANCE
Q

Q

Q

Figure 2.

Figure 1.

VCC
GND

-----VCC
CLOCK
-GND

Figure 3.

TEST CIRCUITS
TEST POINT

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

I

CONNECTTO VCC WHEN
TESTING tpLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH-

• Includes all probe and jig capacitance

Figure 4.

High-Speed CMOS Logic Data
DL129-Rev6

1 kQ

Figure 5.

3-465

MOTOROLA

MC74HC564
EXPANDED LOGIC DIAGRAM

00

2

0

0

19

00

C

01

0

18

01

C

02

4

0

17

Q2

C

03

5

0

16

03

C

04

6

[3]

0

15

04

C

05

0

14

05

C

06

8

0

13

06

C

07

0

12

Q7

C
CLOCK

11

OUTPUT
ENABLE

MOTOROLA

3-466

High-Speed CMOS Logic Data

DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Noninverting
Transparent Latch

MC54/74HC573A

~

High-Performance Silicon-Gate CMOS
The MC54174HC573A is identical in pinout to the LS573. The devices are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HCT373A but has the data
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC573A is the noninverting version of the HC563.

1

NSUFFIX
PLASTIC PACKAGE
CASE 73B-D3

1

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW

01

18 Q1

02
OATA
INPUTS

4

OUTPUT
ENABLE
00

17 Q2

03

16 Q3

04

15 Q4

NONINVERTING
OUTPUTS

VCC
QO

01

Q1

02

Q2

03

Q3

14 Q5

04

Q4

06

13 Q6

05

Q5

07

12 Q7

06

Q6

07

Q7
LATCH
ENABLE

05

7

LATCH ENABLE ...;1-,-1_ _..J
OUTPUT ENABLE - - - -....

GNO

PIN 20 = VCC
PIN 10=GNO

Design Criteria
Internal Gate Count'
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product

Value

Units

54.5

ea.

1.5

ns

5.0

/lW

0.0075

pJ

, Equivalent to a two-input NAND gate.

FUNCTION TABLE
Inputs

Output

Output
Enable

Latch
Enable

D

Q

L
L
L
H

H
H
L
X

H
L
X
X

H
L
No Change
Z

X ~ Don't Care
Z ~ High Impedance

10195

© Motorola, Inc. 1995

Ceramic
Plastic
SOIC

PIN ASSIGNMENT

LOGIC DIAGRAM
19 QO

DWSUFFIX
SOIC PACKAGE
CASE 751D-Q4

20#

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 ~A
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 218 FETs or 54.5 Equivalent Gates

00

J SUFFIX
CERAMIC PACKAGE
CASE 732-Q3

20D''fMM{1f~ UUU

3-467

REV 6

®

MOTOROLA

[3J

MC54174HC573A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

UnIt

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

lin
lout

DC Output Current, per Pin

±35

mA

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65 to + 150

°c

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (Vin orVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

MIn

Max

2.0

6.0

Unit
V

0

VCC

V

-55

+ 125

°C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

s

85°C

s

125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVcc-O.l V
1I0uti s 2Ol1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 V orVcc -0.1 V
1I0uti s 20 /LA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
18

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20 /LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL
1I0uti s 6.0 mA
1I0uti S 7.8 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

VOH

Yin = VIH or VIL
1I0uti s 6.0 mA
1I0uti s 7.8 mA
VOL

lin

Maximum Low-Level Output
Voltage

Maximum Input Leakage Current

Vou t=O.1 VorVCC-O.l V
1I0uti s 20 /LA

NOTE: Information on tYPical parametric values can be found

MOTOROLA

In

V

/LA

Chapter 2.

3-468

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC573A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Vee
V

-55to
25'e

s 85'e

s 125°C

Unit

Symbol

Parameter

Test Conditions

IOZ

Maximum Three-State Leakage
Current

Output in High-Impedance State
Vin ~ VIL or VIH
Vout ~ VCC or GND

6.0

-0.5

-5.0

-10

IlA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin ~ VCC or GND
1I0uti ~ 0 IlA

6.0

4.0

40

160

IlA

Vee
V

-55to
25°C

AC ELECTRICAL CHARACTERISTICS (CL ~ 50 pF, Input tr ~ tf ~ 6.0 ns)
Guaranteed Limit

s 85'e

s 125'e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpLH,
tpHL

Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)

2.0
4.5
6.0

160
32
27

200
40
34

240
48
41

ns

tpLZ,
tPHZ

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpZL,
tpZH

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

ITLH,
ITHL

Maximum Output Transition lime, Any Output
(Figures 1 and 5)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Symbol

Parameter

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three-State Output Capacitance (Output in High-Impedance State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°C, Vee ~ 5.0 V
Power Dissipation Capacitance (Per Enabled Output)'

23

• Used to determine the no-load dynamic power consumption: Po ~ CpO VCc 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (CL ~ 50 pF, Input tr ~ tf ~ 6.0 ns)
Guaranteed Limit
Symbol

Parameter

Fig.

Vee
Volts

- 55 to 25°C
Min

Max

s
Min

85'e
Max

s 125°C
Min

Max

Unit

tsu

Minimum Setup Time, Input 0 to Latch Enable

4

2.0
4.5
6.0

50
10
9.0

65
13
11

75
15
13

ns

th

Minimum Hold Time, Latch Enable to Input 0

4

2.0
4.5
6.0

5.0
5.0
5.0

5.0
5.0
5.0

5.0
5.0
5.0

ns

tw

Minimum Pulse Width, Latch Enable

2

2.0
4.5
6.0

75
15
13

95
19
16

110

ns

tr,tf

Maximum Input Rise and Fall Times

High-Speed CMOS Logic Data
0L129-Rev6

1

3-469

2.0
4.5
6.0

1000
500
400

22
19
1000
500
400

1000
500
400

ns

MOTOROLA

MC54174HC573A
SWITCHING WAVEFORMS
LATCH
ENABLE

-VCC
INPUTD

11'----- GND
tPHL
Q

trHL

Q

Figure 2.

Figure 1.

,----3.0V

OUTPUT
ENABLE

HIGH
IMPEDANCE

Q

INPUTD

~
~

tSU~th
LATCH
ENABLE

Q

VALlD3=

:~:

-VCC

50%
' - - - - - - - GND

Figure 4.

Figure 3.

EXPANDED LOGIC DIAGRAM

TEST POINT

DO

OUTPUT
DEVICE
UNDER
TEST

D1

D2

• Includes all probe and jig capacitance

03

Figure 5. Test Circuit
D4

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

1 kn

I

D5

CONNECT TO VCC WHEN
TESTING tPLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH·

D6

D7

LATCH ENABLE

• Includes all probe and jig capacitance

OUTPUT ENABLE

Figure 6. Test Circuit

MOTOROLA

3-470

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Noninverting
Transparent Latch with
LSTTL Compatible Inputs

MC74HCT573A
NSUFFIX
PLASTIC PACKAGE
CASE 738-03

High-Performance Silicon-Gate CMOS
The MC74HCT573A is identical in pinout to the LS573. This device may
be used as a level converter for interfacing TTL or NMOS outputs to
High-Speed CMOS inputs.
These latches appear transparent to data (Le., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high-impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HCT573A is identical in function to the HCT373A but has the Data
Inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HCT573A is the noninverting version of the HC563.

20.
1

ORDERING INFORMATION
MC74HCTXXXAN
Plastic
MC74HCTXXXADW SOIC

PIN ASSIGNMENT

•
•
•
•
•
•

Output Drive Capability: 15 LSTTL Loads
TTUNMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 10!lA
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
Improved Propagation Delays
50% Lower Quiescent Power

OUTPUT [ 1.
ENABLE
DO l 2

20

PVCC

19

D1

3

18

P00
P01

D2

4

17

D3

5

16

LOGIC DIAGRAM
DO
D1
D2
DATA
INPUTS

2
3
4

D3
D4
D5

7

D6

LATCH ENABLE

PIN 20= Vcc
PIN 10=GND

Design Criteria

Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product

14

P04
P05

D6

8

13

P06

D7

9

12

10

11

POl
PENABLE
LATCH

Inputs

14 05
13 06
12

Internal Gate Count'

15

7

FUNCTION TABLE

11

OUTPUT ENABLE

6

D5

NON INVERTING
OUTPUTS

Ol

D7

P02
P03

D4

GND

19 00
18 01
17 02
16 03
15 04

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

Output

Output
Enable

Latch
Enable

D

Q

L
L
L
H

H
H
L
X

H
L
X
X

H
L
No Change
Z

X = Don't Care
Z = High Impedance

Value

Units

58.5

ea

1.5

ns

5.0

IlW

0.0075

pJ

, Equivalent to a two-input NAND gate.

10195

© Motorola, Inc. 1995

3-471

REV 6

®

MOTOROLA

MC?4HCT5?3A
MAXIMUM RATINGS·
Symbol
VCC
Vin
Vout

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA
rnA

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500

mW

-65to+ 150

°c

Tstg
TL

Plastic D1Pt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND s (VinorVout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

°c

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

S 85°C

s 125°C

Unit

ViH

Minimum High-Level Input
Voltage

Vout=0.1 VorVCC-0.1 V
lIoutl s 20llA

4.5
5.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
lIoutl s 20llA

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
1I0uti s 20llA

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

V

Vin = VIH or VIL
lIoutl s 6.0 mA

4.5

3.98

3.84

3.7

Vin = VIH or VIL
lIoutl s 20 !LA

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Symbol

VOH

VOL

Parameter

Maximum Low-Level Output
Voltage

Test Conditions

V

Vin = VIH or VIL
lIoutl s 6.0 rnA

4.5

0.26

0.33

0.4

Maximum Input Leakage Current

Vin = VCC or GND

5.5

±0.1

± 1.0

±1.0

IlA

10Z

Maximum Three-5tate
Leakage Current

Output in High-Impedance State
Vin = ViL or VIH
Vout = VCC or GND

5.5

±0.5

±5.0

±10

!LA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout S OILA

5.5

4.0

40

160

!LA

LlICC

Additional Quiescent Supply
Current

Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = !LA

lin

o

5.5

~-55°C

25°C to 125°C

2.9

2.4

mA

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-472

High-Speed CMOS Logic Data
DL129-Rev6

MC74HCT573A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Parameter

-55 to
25°e

s 85°e

s 125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input 0 to Output Q
(Figures 1 and 5)

30

38

45

ns

tpLH
tpHL

Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)

30

38

45

ns

TPLZ,
TpHZ

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

28

35

42

ns

tTZL,
lTZH

Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)

28

35

42

ns

tTLH,
tTHL

Maximum Output Transition TIme, any Output
(Figures 1 and 5)

12

15

18

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three-State Output Capacitance
(Output in High-Impedance State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°e, Vee = 5.0 V
Power Dissipation Capacitance (Per Enabled Output)"

48

"Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.
TIMING REQUIREMENTS (VCC =5.0V± 10%, CL= 50 pF, Inputtr= tf= 6.0 ns)
Guaranteed Limit
- 55 to 25°e
Symbol

Parameter

Fig.

Min

Max

s 85°C
Min

Max

s 125°e
Min

Max

Unit

tsu

Minimum Setup Time, Input 0 to Latch Enable

4

10

13

15

ns

th

Minimum Hold Time, Latch Enable to Input 0

4

5.0

5.0

5.0

ns

tw

Minimum Pulse Width, Latch Enable

2

15

t r, tf

Maximum Input Rise and Fall Times

1

High-Speed CMOS Logic Data
DL129-Rev6

3-473

19
500

22
500

ns
500

ns

MOTOROLA

MC74HCT573A
SWITCHING WAVEFORMS
LATCH
ENABLE
INPUTD

11'----- GND

Q

Figure 2.

Figure 1.

,.---3.0V

OUTPUT
ENABLE

~VALlD==t-HIGH
IMPEDANCE

Q

.PUTO

----'~ ~'-::
tsu~ th

LATCH
ENABLE

Q

-3.0V

'{:V
' - - - - - - - GND

Figure 4.

Figure 3.

EXPANDED LOGIC DIAGRAM

TEST POINT

DO

OUTPUT
DEVICE
UNDER
TEST

Dl
D2

• Includes all probe and jig capacitance

D3

Figure 5. Test Circuit
D4

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

1 kQ

D5

I

CONNECT TO VCC WHEN
TESTING tPLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH.

D6

D7

LATCH ENABLE
• Includes all probe and jig capacitance

OUTPUT ENABLE

Figure 6. Test Circuit

MOTOROLA

3-474

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC574A

Octal3-State
Noninverting D Flip-Flop

~

High-Performance Silicon-Gate CMOS
The MC54n4HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge
of the Clock. The Output Enable input does not affect the states of the
flip-flops, but when Output Enable is high, all device outputs are forced to
the high-impedance state. Thus, data may be stored even when the outputs
are not enabled.
The HC574A is identical in function to the HCT374A but has the flip-flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC574A is the noninverting version of the HC564.
•
•
•
•
•
•

JSUFFIX
CERAMIC PACKAGE
CASE 732-Q3

20r~~"UU
1

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

DWSUFFIX
SOIC PACKAGE
CASE 751D--04

20~
1

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 IlA
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 266 FETs or 66.5 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
OUTPUT [ 1ENABLE
DO [ 2

LOGIC DIAGRAM
DO
D1
D2
DATA
INPUTS

D3
D4
D5
D6

2

19

3

18

4

17

5

16

6

15

7

14

8

12

D7
CLOCK

13

20 1 VCC
19

QO

18

Q1
Q2

00

D1[ 3

01

D2 [ 4

17

02

D3 [ 5

16

Q3

D4 [ 6

15

04

03
04

NONINVERTING
OUTPUTS

05

as
07

D5 [ 7

14 ] 05

D6 [ 8

13

D?[ 9

12

Q7

GND [ 10

11

CLOCK

11

OUTPUT ENABLE

Q6

PIN20= Vcc
PIN 10=GND

FUNCTION TABLE
Inputs
Design Criteria

Output

Value

Units

OE

Clock

D

Q

Internal Gate Count'

66.5

ea

Internal Gate Propagation Delay

1.5

ns

L
L
L
H

J'
J'
L,H,'X

H
L
X
X

H
L
No Change
Z

Internal Gate Power Dissipation

5.0

!1W

0.0075

pJ

Speed Power Product

X = Don't Care
Z = High Impedance

, EqUivalent to a two-Input NAND gate.

10195

© Motorola, Inc. 1995

~75

REV 6

®

MOTOROLA

MC54/74HC574A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

- 65 to + 150

·C

'in
lout

Tstg
TL

Storage Temperature

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :$ (Vin or Voutl :$ VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

·C

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

260
300

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/·C from 65· to 125·C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: -7 mW/'C from 65' to 125·C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

-55to
25'C

:$ 85·C

:$ 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
1I0uti :$ 20 ~

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

V,L

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
1I0uti :$ 20 ~

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = V,H or V,L
1I0uti :$ 20 I1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = V,H or V,L
"outl :$ 6.0 rnA
"outl :$ 7.8 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Yin = Vec or GND

6.0

±0.1

±1.0

±1.0

VOH

Parameter

VCC
V

Yin = V,H or V,L
1I0uti :$ 6.0 rnA
1I0uti :$ 7.8 rnA
VOL

lin

Maximum Low--Level Output
Voltage

Maximum Input Leakage Current

Vout=0.1 VorVcc-0.1 V
1I0utl:$ 20~

V

~

NOTE: Information on typical parametric values can be found In Chapter 2.

MOTOROLA

3-476

High-Speed CMOS Logic Data
DL129-Rev6

MC54/7 4HC574A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Vee
V

-55to
25°C

Symbol

Parameter

Test Conditions

:5 85°C

:5 125°C

Unit

10Z

Maximum Three-State Leakage
Current

Output in High-Impedance State
Vin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

(.LA

ICC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
"outl = 0 (.LA

6.0

4.0

40

160

(.LA

Vee
V

-55to
25°C

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

:5 85°C

:5 125°C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

Parameter

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

2.0
4.5
6.0

160
32
27

200
40
34

240
48
41

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tPZL,
tpZH

Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)

2.0
4.5
60

140
28
24

175
35
30

210
42
36

ns

ITlH,
tTHL

Maximum Output Transition Time, any Output
(Figures 1 and 4)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three-State Output Capacitance, Output in High-Impedance State

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and Information on tYPical parametric values, see Chapter 2.
Typical @ 25°C, Vee
Power Dissipation Capacitance (Per Enabled Output)*

=5.0 V

24

• Used to determine the no-load dynamic power consumption: Po = CPO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol

Parameter

Fig.

Vee
Volts

-55 to 25°C
Min

Max

:5 85°C

Min

Max

:5 125°C

Min

Max

Unit

tsu

Minimum Setup Time, Data to Clock

3

2.0
4.6
6.0

50
10
9.0

65
13
11

75
15
13

ns

th

Minimum Hold Time, Clock to Data

3

2.0
4.5
6.0

5.0
5.0
5.0

5.0
5.0
5.0

5.0
5.0
5.0

ns

tw

Minimum Pulse Width, Clock

1

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Rise and Fall Times

1

2.0
4.5
6.0

tr,tl

High-Speed CMOS Logic Data
DL129-Rev6

3-477

1000
500
400

1000
500
400

1000
500
400

ns

MOTOROLA

MC54174HC574A
SWITCHING WAVEFORMS

,---3.0V

HIGH
IMPEDANCE
Q

Q

Figure 1.

Figure 2.

EXPANDED LOGIC DIAGRAM
VCC
GND

DO 2

-----VCC
CLOCK
-GND

01 3

Figure 3.
02 4
TEST POINT

03 5
OUTPUT
DEVICE
UNDER
TEST

04 6

05 7
• Includes all probe and jig capacitance

06 B

Figure 4.

TEST POINT
(

OUTPUT
DEVICE
UNDER
TEST

1 kQ

07 9

I

CONNECT TO VCC WHEN
TESTING tpLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tpHZ AND tpZH.

OUTPUT ENABLE 1

• Includes all probe and jig capacitance

Figure 5. Test Circuit

MOTOROLA

3-478

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Octal 3-State
Noninverting D Flip-Flop with
LSTTL Compatible Inputs
High-Performance Silicon-Gate CMOS

I MC54/74HCT574A I
20

_
.
1

The MC54174HCT574A is identical in pinout to the LS574. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states of
the flip-flops, but when Output Enable is high, all device outputs are
forced to the high-impedance state. Thus, data may be stored even when
the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flip-flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.

NSUFFIX
PLASTIC PACKAGE
CASE 738-03

DWSUFFIX
SOIC PACKAGE
CASE 7510-04
ORDERING INFORMATION

•
•
•
•
•
•

Output Drive Capability: 15 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 !lA
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

MC54HCTXXXAJ
MC74HCTXXXAN
MC74HCTXXXADW

19
18

Dl

17

D2
DATA
INPUTS

16

D3

15

D4
D5
D6

7

14

8

13
12

D7
CLOCK

Dt[ 3
QO
Q1
Q2
Q3
Q4

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
OUTPUT [ 1.
ENABLE
DO [ 2

LOGIC DIAGRAM
DO

JSUFFIX
CERAMIC PACKAGE
CASE 732-03

NONINVERTING
OUTPUTS

Q5
Q6

20

~ VCC

19

PQO
PQl

18

D2 [ 4

17 ~ Q2

D3 [ 5

16

D4 [ 6

15

D5 [ 7

14 ~ Q5

D6 [ 8

13 ~ Q6

D7 [ 9

12

pO?

GND [ 10

11

PCLOCK

PQ3
PQ4

Q7

11

OUTPUT ENABLE

PIN 20 = VCC
PIN 10 = GND

FUNCTION TABLE
Inputs
OE

Design Criteria

Value

Units

71.5

ea

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

~W

0.0075

pJ

Internal Gate Count'

Speed Power Product

L
L
L
H

Output

Clock

.r
.r
L,H,\...
X

D

Q

H
L
X
X

H
L
No Change
Z

x = don't care
Z = high impedance

'EqUivalent to a tWO-input NAND gate.

10195

© Motorola, Inc. 1995

3-479

REV6

®

MOTOROLA

MC54/74HCT57 4A
MAXIMUM RATINGS'
Symbol
VCC
Vin
Vout

Parameter

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

mA
mA

DC Supply Voltage (Referenced to GND)

lin

DC Input Current, per Pin

lout

DC Output Current, per Pin

±35

ICC

DC Supply Current, VCC and GND Pins

±75

mA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65 to + 150

'c

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin orVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'c
260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time (Figure 1)

Min

Max

Unit

4.5

5.5

V

0

VCC

V

-55

+ 125

'C

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=0.1 VorVcc-0.1 V
lIoutl s 20~

4.5
5.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum Low-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
lIoutl s 20 !lA

4.5
5.5

0.8
0.8

0.8
0.8

0.8
0.8

V

Minimum High-Level Output
Voltage

Vin = VIH or VIL
lIout' s 20~

4.5
5.5

4.4
5.4

4.4
5.4

4.4
5.4

Vin = VIH or VIL
lIout' s 6.0 mA

4.5

3.98

3.84

3.7

Vin = VIH or VIL
lIouti s 20~

4.5
5.5

0.1
0.1

0.1
0.1

0.1
0.1

Vin = ViH or VIL
lioutl s 6.0 mA

4.5

0.26

0.33

0.4

Maximum Input Leakage Current

Vin = VCC or GND

5.5

±0.1

±1.0

±1.0

~

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 IlA

5.5

4.0

40

160

~

Symbol

VOH

VOL

lin
ICC

Parameter

Maximum Low-Level Output
Voltage

Test Conditions

V

1. Output In high-Impedance state.
NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-480

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HCT574A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

IOZ

Maximum Three-State Leakage
Current

Vin VIL or VIH (Note 1)
Vout VCC or GND

Additional Quiescent Supply
Current

Vin 2.4 V, Any One Input
Vin VCC or GND, Other Inputs
lout 0 ~A

AICC

Test Conditions

VCC
V

-55 to
25°C

:s 85°C

:s 125°C

Unit

5.5

-0.5

-5.0

-10

~A

=
=

=

=
=

:<:-55°C

25°C to 125°C

2.9

2.4

5.5

mA

1. Output In high-Impedance state.

AC ELECTRICAL CHARACTERISTICS (VCC

=5.0 V ± 10%, CL =50 pF, Input tr =tf =6.0 ns)
Guaranteed Limit
-55to
25°C

:s 85°C

:s 125°C

Unit

fMAX

Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)

30

24

20

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)

30

38

45

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)

28

35

42

ns

tpZH,
tpZL

Maximum Propagation Delay Time, Output Enable to Q
(Figures 2 and 5)

28

35

42

ns

ITLH'

Maximum Output Transition Time, Any Output
(Figures 1, 2 and 4)

12

15

18

ns

Maximum Input Capacitance

10

10

10

pF

Symbol

Parameter

tTHL
Cin

NOTE: For propagation delays with loads other than 50 pF, and information on tYPical parametric values, see Chapter 2.
Typical

@

Power Dissipation Capacitance (Per Flip-Flop)'

25°C, VCC

=5.0 V

58

• Used to determine the no-load dynamic power consumption: Po

=CpO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
-55 to 25°C

tsu

Minimum Setup Time, Data to Clock

3

10

13

15

ns

th

Minimum Hold Time, Clock to Data

3

5.0

5.0

5.0

ns

Minimum Pulse Width, Clock

1

15

Maximum Input Rise and Fall Times

1

tw
t r , If

High-Speed CMOS Logic Data
Dl129-Rev6

3-481

Min

Max

:s 125°C

Min

Parameter

Max

:s 85°C

Fig.

Symbol

19
500

Min

Max

22
500

Unit

ns
500

ns

MOTOROLA

MC54n4HCT57 4A
EXPANDED LOGIC DIAGRAM

DO

ENABLE
OUTPUT

D2

D3

D5

D6

Q5

Q6

1

Q7

SWITCHING WAVEFORMS

,.---3.0V
OUTPUT
ENABLE
HIGH
IMPEDANCE
Q

Q

Figure 1.

Figure 2.
TEST POINT

~
j3C
ISUfi,lh

VALlD~

DAc

OUTPUT

::~

DEVICE
UNDER
TEST

-----3.0 V

1.3 V

CLOCr<------'

-

GND
* Includes all probe and jig capacitance

Figure 3.

Figure 4. Test Circuit
TEST POINT
OUTPUT

1 kQ

DEVICE
UNDER
TEST

I

CONNECT TO VCC WHEN
TESTING IPLZ AND IPZL·
CONNECT TO GND WHEN
TESTING IpHZ AND IPZH-

* Includes all probe and jig capacitance

Figure 5. Test Circuit

MOTOROLA

3--482

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC589

8-Bit Serial or Parallel-Input!
Serial-Output Shift Register
with 3-State Output

;r._

le~t

High-Performance Silicon-Gate CMOS
The MC54/74HC589 is similar in function to the HC597, which is not a
3-state device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an 8-bit storage latch which feeds parallel data to
an 8-bit shift register. Data can also be loaded serially (see Function Table).
The shift register output, QH, is a three-state output, allowing this device to
be used in bus-oriented systems.
The HC589 directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.

J SUFFIX
CERAMIC PACKAGE
CASE 620-10

NSUFFIX
PLASTIC PACKAGE
CASE 641Hl8

D SUFFIX
SOIC PACKAGE
CASE 7518-05

le#

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 (.LA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates

ORDERING INFORMATION

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
LOGIC DIAGRAM
SERIAL {
DATA
SA
INPUT

14

B

1.

16

PVCC

C

2

15

A

14

SA
SERIAL SHIFT!
PARALLEL LOAD
LATCH CLOCK

D
E

A

15

B
PARALLEL
DATA
INPUTS

C
D
E

VCC= PIN 16
GND = PIN8
4

5
G

DATA
LATCH

SHIFT
REGISTER

SHIFT CLOCK
SERIAL SHIFTI
PARALLEL LOAD
OUTPUT ENABLE

9
12

QH

}

12

F

5

G

6

11

SHIFT CLOCK

H

7

10

OUTPUT ENABLE

GND

8

9

PQH

SERIAL
DATA
OUTPUT

11
13
10

10195

© Motorola, Inc. 1995

13

6

H
LATCH CLOCK

4

3-483

REV 6

®

MOTOROLA

[3J

MC54n4HC589
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±35

mA

ICC

DC Supply Current, VCC and GND Pins

±75

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg

Storage Temperature

-65to+150

'C

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
lied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage,. Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC = 4.5 V
VCC = 6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

·C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Vee
V

-55to
25'C

s 85'C

s 125'e

Unit

VIH

Minimum High-Level Input
Voltage

Vou t=0.1 VorVCC-0.1 V
lIoutl s 20 J.IA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=0.1 VorVcc-0.1 V
lIoutl s 20 J.IA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 20 IlA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl s 6.0 rnA
lIoutl s 7.8 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin=VIH
lIoutl s 20 IlA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL lIoutl s 6.0 rnA
lIoutl s 7.8 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

VOL

Parameter

Maximum Low-Level Output
Voltage

Test Conditions

V

lin

Maximum Input Leakage Current

Yin = Vce or GND

6.0

±0.1

± 1.0

±1.0

IOZ

Maximum Three-State Leakage
Current

Output in High-Impedance State
Yin = VIL or VIH
Vout = VCC or GND

6.0

±0.5

±5.0

±10

J.IA
J.IA

ICC

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 J.IA

6.0

8

80

160

j.LA

NOTE: Information on typical parametric values can be found

MOTOROLA

In

Chapter 2.

3-484

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC589
AC ELECTRICAL CHARACTERISTICS (CL

=50 pF. Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55to
25'e

s 85'e

s 125'e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH.
tpHL

Maximum Propagation Delay. Latch Clock to QH
(Figures 1 and 8)

2.0
4.5
6.0

210
42
36

265
53
45

315
63
54

ns

tpLH.
tpHL

Maximum Propagation Delay. Shift Clock to QH
(Figures 2 and 8)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLH.
tpHL

Maximum Propagation Delay. Serial Shift/Parallel Load to QH
(Figures 4 and 8)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLZ.
tpHZ

Maximum Propagation Delay. Output Enable to QH
(Figures 3 and 9)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpZL.
tpZH

Maximum Propagation Delay. Output Enable to QH
(Figures 3 and 9)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tTLH.
ITHL

Maximum Output Transition lime. Any Output
(Figures 1 and 8)

2.0
4.5
S.O

SO
12
10

75
15
13

90
18
15

ns

Maximum Input Capacitance

-

10

10

10

pF

Maximum Three-State Output Capacitance (Output in
High-Impedance State)

-

15

15

15

pF

Symbol

Cin
Cout

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF. see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'e. Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

50

'Used to determine the no-load dynamic power consumption: Po = CpO VCC 2 f + ICC VCC. For load considerations. see Chapter 2.

High-Speed CMOS Logic Data
DL129-RevS

3-485

MOTOROLA

MC54174HC589
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V

-55to
' 25°C

s 85°C

s 125°C

Unit

tsu

Minimum Setup Time, A-H to Latch Clock
(Figure 5)

2.0
4.5
6.0

100
20
17

125,
25
21

150
30
26

ns

tsu

Minimum Setup Time, Serial Data Input SA to Shift Clock
(Figure 6)

2.0
4.5
6.0

100
20

150
30
26

ns

17

125
25
21

tsu

Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock
(Figure 7)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Latch Clock to A-H
(Figure 5)

2.0
4.5
6.0

25
5
5

30
6
6

40
8
7

ns

th

Minimum Hold Time, Shift Clock to Serial Data Input SA
(Figure 6)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Shift Clock
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Latch Clock
, (Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Serial Shift/Parallel Load
(Figure 4)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tr,tf

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Parallel
Inputs
A-H

Data
Latch
Contents

Shift
Register
Contents

Output
QH

Symbol

Parameter

NOTE: Information on typical parametric values can be found In Chapter 2.
FUNCTION TABLE
Inputs

Resulting Function

Output
Enable

Serial Shiftl
Parallel Load

Latch
Clock

Shift
Clock

Serial
Input
SA

Force output into high
impedance state

H

X

X

X

X

X

X

X

Z

Load parallel data into
data latch

L

H

.r

L,H,"'\...

X

a-h

a-h

U

U

Transfer latch contents to
shift register

L

L

L, H,"'\...

X

X

X

U

LRN-4SRN

LRH

Contents of input latch
and shift register are
unchanged

L

H

L, H,"'\...

L, H,"'\...

X

X

U

U

U

Load parallel data into
data latch and shift
register

L

L

.r

X

X

a-h

a-h

a-h

h

Shift serial data into shift
register

L

H

X

.r

D

X

.

SRA=D,
SRN -4SRN+l

SRG -4SRH

Load parallel data in data
latch and shift serial data
into shift register

L

H

.r

.r

D

a-h

a-h

SRA= D,
SRN -4SRN+l

SRG -4SRH

Operation

U = remains unchanged
X = don't care
Z = high impedance

LR = latch register contents
SR = shift register contents
a-h = data at parallel data inputs A-H
D = data (L, H) at serial data input SA

MOTOROLA

• = depends on Latch Clock input

3-486

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC589
SWITCHING WAVEFORMS

Figure 1. (Serial ShiWParaliel Load = L)

=H)

Figure 2. (Serial ShiWParallel Load

,----VCC
OUTPUT
ENABLE
HIGH
IMPEDANCE

Figure 4.

Figure 3.

------~ r------~

r------VCC

A-H
______J

~

_ _ _ _ _ _J

SA
~------GND

LATCH CLOCK

------~

r------...... r-----VCC

______J

~

_ _ _ _ _ _J

~------GND

SHIFT CLOCK

Figure 5.

Figure 6.

TEST POINT
~

SERIAL SHIFT!
PARALLEL LOAD

J:"L
....11 50%

SHIFT CLOCK ________

OUTPUT

--VCC
DEVICE
UNDER
TEST

GND

\\.._____
• Includes all probe and jig capacitance

Figure 7.

High-Speed CMOS Logic Data
DL129-Rev6

Figure 8. Test Circuit

3-487

MOTOROLA

MC54174HC589
TEST CIRCUIT

I

TEST POINT
OUTPUT

CONNECTTO VCC WHEN
TESTING tpLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tpHZ AND tpZH.

1 kn
'v

DEVICE
UNDER
TEST

* Includes all probe and jig capacitance

Figure 9.

PIN DESCRIPTIONS
DATA INPUTS

Shift Clock (Pin 11)

Parallel data inputs. Data on these inputs are stored in the
data latch on the rising edge of the Latch Clock input.

Serial shift clock. A low-te-high transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out QH, being replaced by the data
previously stored in stage G.

SA (Pin 14)

Latch Clock (Pin 12)

A, B, C, D, E, F, G, H (Pins 15, 1,2,3,4,5,6,7)

Data latch clock. A low-te-high transition on this input
loads the parallel data on inputs A-H into the data latch.

Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
ShiWParaliel Load is high. Data on this input is ignored when
Serial ShiWParaliel Load is low.

Output Enable (Pin 10)
Active-low output enable A high level applied to this pin
forces the QH output into the high impedance state. A low
level enables the output. This control does not affect the
state of the input latch or the shift register.

CONTROL INPUTS
Serial ShiftlParallel Load (Pin 13)

OUTPUT

Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register accepts parallel data from the data latch.

MOTOROLA

QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3-state output.

3--4BB

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC589
TIMING DIAGRAM

SHIFT CLOCK
SERIAL DATA
INPUT,SA

l

I
I
I
I
I
I

OUTPUT ENABLE ~
SERIAL SHIFT!
I
PARALLEL LOAD ~ :

~:

LATCH CLOCK ~

~

A

L I
I II
B I L II
I II
I I

IH
I
IL
I
I

I II
D I L II
I II

I
IL
I

ElL
I I

IH
I

C~
PARALLEL
DATA
INPUTS

~
J0.iHl

F

I II
GIL II
I II

I
IL
I

I
I

I

I

~I
IHI

H IL I
QH

r

II
II
II
II
II
II
II
II
II
II
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I

~

ir

II
: IL
II
II L
II
II
II L
II
II
II L
II
II
IIH
II
IIH
II
II
II L
II
II
IIH
II
LI

I
IL
I
IL
I
I
IL
I
I
IL
I
I
IL
I
IL
I
I
IL
I
I
IH
I

I

I
I
II
II
II
I
II
II
II
II
II
II
II
II
II
II
II
II

raJ

~

f

i

RESET LATCH LOAD LATCH PARALLEL LOAD
AND SHIFT REGISTER
SHIFT REGISTER

High-Speed CMOS Logic Data
DL129-Rev6

i

LOAD LATCH

3-489

i

PARALLEL LOAD
SHIFT REGISTER

i

PARALLEL LOAD, LATCH
AND SHIFT REGISTER

MOTOROLA

MC54n4HC589
LOGIC DETAIL
OUTPUT ENABLE ..;.10"--_ _Q
SA 14
SHIFT CLOCK ..;.11'--_ _-1
SERIALSHIFTI..;.13'--_-I
PARALLEL LOAD

-----1

LATCH CLOCK 12

1
1
1

A 15

1
1
1
1
1

1
1

1
1

-----11

r-----

PARALLEL
DATA
INPUTS

1
1

1
1

1
1
1
1
1

1
1
1
1
1

-----1

r---- ----

1.....J

STAGEC'

1

D1.....j

STAGED'

1

C

~------------------------------I

t------------------------------ I
E~
STAGEE'
1
L ______________________________ I

F~

STAGEF'

G~

STAGEG'

1

L ______________________________ I

L____

H7

1

_ ____ 1

1

rr-

1

1
1

DS 1
CR Q

1
1

1

L ____________________________I ' - - - 0 ( ]

'NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.

MOTOROLA

3-490

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview
8-Bit Serial or Parallel-Input!
Serial-Output Shift Register
with 3-State Output

MC54!74HC589A
J SUFFIX
CERAMIC PACKAGE
CASE 620-10

High-Performance Silicon-Gate CMOS
The MC54/74HC589A is similar in function to the HC597, which is not a
3-state device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an B-bit storage latch which feeds parallel data to
an 8-bit shift register. Data can also be loaded serially (see Function Table).
The shift register output, QH, is a three-state output, allowing this device to
be used in bus-oriented systems.
The HC589A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

o SUFFIX
SOIC PACKAGE
CASE 7518-05

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 IlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates

DTSUFFIX
TSSOP PACKAGE
CASE 948F-ol

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Ceramic
Plastic
SOIC
TSSOP

LOGIC DIAGRAM
SERIAL {
DATA
SA
INPUT
A

PIN ASSIGNMENT

14

15

B
PARALLEL
DATA
INPUTS

C

VCC~ PIN 16
GND ~ PIN 8

D
E
F
G

4
5

DATA
LATCH

SHIFT
REGISTER

6

9 QH

H
LATCH CLOCK

SHIFT CLOCK
SERIAL SHIFT!
PARALLEL LOAD
OUTPUT ENABLE

12

} SERIAL
DATA
OUTPUT

B [ 1-

16

C[ 2

15

A

D[ 3

14

SA
SERIAL SHIFT!
PARALLEL LOAD
LATCH CLOCK

E[ 4

13

F[ 5

12

VCC

G[ 6

11

SHIFT CLOCK

H[ 7

10

OUTPUT ENABLE

GND [ 8

9

QH

11
13

10

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10/95

© Motorola, Inc. 1995

3-491

REV 0

®

MOTOROLA

MC54174HC589A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

- 0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

-65to + 150

'c
'c

TL

.

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

260
300

Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDeraling - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
TSSOP Package: - 6.1 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=3.OV
VCC = 4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

'c

0
0
0

1000
TBD
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
1I0uti s 20 itA

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC -0.1 V
1I0uti S 20 I!A

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20 I!A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL 1I0uti S 2.4 mA
1I0uti s 6.0 mA
1I0uti S 7.8 mA

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

Vin=VIH
1I0uti s 20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Symbol

VOH

VOL

Parameter

Maximum Low-Level Output
Voltage

Test Conditions

I!A

Yin = VIH or VIL 1I0uti s 2.4 mA
1I0uti S 6.0 mA
1I0uti S 7.8 mA

MOTOROLA

3-492

V

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC589A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

lin

Maximum Input Leakage Current

Vin

Test Conditions

IOZ

Maximum Three-State Leakage
Current

Output in High-Impedance State
Vin VIL or VIH
Vout = VCC or GND

ICC

Maximum Quiescent Supply
Current (per Package)

Vin VCC or GND
lout = 0 IlA

=VCC or GND

Vee
V

-55to
25'e

s 85'e

s 125'e

Unit

6.0

±0.1

±1.0

±1.0

IlA

6.0

±0.5

±5.0

±10

IlA

6.0

4

40

160

Il A

Vee
V

-55to
25'e

=

=

NOTE: Information on tYPical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr =tf =6 ns)
Guaranteed Limit

s 85'e

s 125'e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)

2.0
3.0
4.5
6.0

6.0
TBD
30
35

4.8
TBD
24
28

4.0
TBD
20
24

MHz

tPLH,
tpHL

Maximum Propagation Delay, Latch Clock to QH
(Figures 1 and 8)

2.0
3.0
4.5
6.0

175
100
40
30

225
110
50
40

275
125
60
50

ns

tpLH,
tpHL

Maximum Propagation Delay, Shift Clock to QH
(Figures 2 and 8)

2.0
3.0
4.5
6.0

'160
90
30
25

200
130
40
30

240
160
48
40

ns

tpLH,
tpHL

Maximum Propagation Delay, Serial Shift/Parallel Load to QH
(Figures 4 and 8)

2.0
3.0
4.5
6.0

160
90
30
25

200
130
40
30

240
160
48
40

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Output Enable to QH
(Figures 3 and 9)

2.0
3.0
4.5
6.0

150
80
27
23

170
100
30
25

200
130
40
30

ns

tPZL,
tpZH

Maximum Propagation Delay, Output Enable to QH
(Figures 3 and 9)

2.0
3.0
4,5
6.0

150
80
27
23

170
100
30
25

200
130
40
30

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 8)

2.0
3.0
4.5
6.0

60
TBD
12
10

75
TBD
15
13

90
TBD
18
15

ns

Symbol

Parameter

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-State Output Capacitance (Output in
High-Impedance State)

-

15

15

15

pF

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical
Power Dissipation Capacitance (Per Package)'

@

25'e, Vee

=5.0 V

50

'Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-493

MOTOROLA

MC54174HC589A
TIMING REQUIREMENTS (Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

" 85°e

" 125°e

Unit

tsu

Minimum Setup lime, A-H to Latch Clock
(Figure 5)

2.0
3.0
4.5
6.0

100
TBD
20
17

125
TBD
25
21

150
TBD
30
26

ns

tsu

Minimum Setup Time, Serial Data Input SA to Shift Clock
(Figure 6)

2.0
3.0
4.5
6.0

100
TBD
20
17

125
TBD
25
21

150
TBD
30
26

ns

tsu

Minimum Setup lime, Serial ShiIVParaliel Load to Shift Clock
(Figure 7)

2.0
3.0
4.5
6.0

100
TBD
20
17

125
TBD
25
21

150
TBD
30
26

ns

th

Minimum Hold lime, Latch Clock to A-H
(Figure 5)

2.0
3.0
4.5
6.0

25
TBD
5
5

30
TBD
6
6

40
TBD
8
7

ns

th

Minimum Hold Time, Shift Clock to Serial Data Input SA
(Figure 6)

2.0
3.0
4.5
6.0

5
5
5
5

5
5
5
5

5
5
5
5

ns

tw

Minimum Pulse Width, Shift Clock
(Figure 2)

2.0
3.0
4.5
6.0

75
TBD
15
13

95
TBD
19
16

110
TBD
23
19

ns

tw

Minimum Pulse Width, Latch Clock
(Figure 1)

2.0
3.0
4.5
6.0

80
TBD
16
14

100
TBD
20
17

120
TBD
24
20

ns

tw

Minimum Pulse Width, Serial ShifVParaliel Load
(Figure 4)

2.0
3.0
4.5
6.0

80
TBD
16
14

100
TBD
20
17

120
TBD
24
20

ns

Maximum Input Rise and Fall limes
(Figure 1)

2.0
3.0
4.5
6.0

1000
TBD
500
400

1000
TBD
500
400

1000
TBD
500
400

ns

Symbol

tr,tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

MOTOROLA

3-494

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC589A
FUNCTION TABLE
Resulting Function

Inputs
SerIal
Input

Parallel
Inputs

Shift
Register
Contents

Output

A-H

Data
Latch
Contents

SA

Output
Enable

Serial Shifll
Parallel Load

Latch
Clock

Shift
Clock

Force output into high
impedance state

H

X

X

X

X

X

X

X

Z

Load parallel data into
data lalch

L

H

L, H,"'\..

X

a-h

a-h

U

U

Transfer latch contents to
shift register

L

L

L, H,"'\..

X

X

X

U

LRN~SRN

LRH

Contents of input latch
and shift register are
unchanged

L

H

L, H,"'\..

L,H,"'\..

X

X

U

U

U

Load parallel data into
data latch and shift
register

L

L

X

X

a-h

a-h

a-h

h

Shift serial data into shift
register

L

H

J

D

X

.

SRA=D,

SRG~SRH

Load parallel data in data
latch and shift serial data
into shift register

L

Operation

J

J

X

SRN~SRN+l

H

J

J

LR = latch register contents
SR = shift register contents
a-h = data at parallel data inputs A-H
D = data (L, H) at serial data input SA

High-Speed CMOS Logic Data
DL129- Rev 6

QH

D

a-h

a-h

SRA= D,
SRN ~SRN+l

SRG~SRH

U = remains unchanged
X = don't care
Z = high impedance
• = depends on Latch Clock input

3-495

MOTOROLA

MC54174HC589A
SWITCHING WAVEFORMS

Figure 1. (Serial Shift/Parallel Load = L)

Figure 2. (Serial Shift/Parallel Load

=H)

,.---VCC
OUTPUT
ENABLE
HIGH
IMPEDANCE

Figure 4.

Figure 3.

- - - - - , . , . - - - - - - ,.----VCC

- - - - . , . - - - - - - ,..----VCC

A-H

SA
_ _ _ _J

- - - - ' ' - - - - - - ' '-----GND

LATCH CLOCK

PA::~:~~:::

_ _ _J

~---GND

SHIFT CLOCK

Figure 6.

Figure 5.

SERIAL SHIFT!

~

dt-lru~I...
50%

____

TEST POINT

-vcc

OUTPUT
DEVICE
UNDER
TEST

_ _ _ GND

• Includes all probe and jig capacitance

Figure 7.

MOTOROLA

Figure 8. Test Circuit

3-496

High-Speed CMOS Logic Data

DL129-Rev6

MC54174HC589A
TEST CIRCUIT

I

TEST POINT
OUTPUT

CONNECT TO VCC WHEN
TESTING tpLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tpHZ AND tpZH-

1 kQ
'Y-

DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 9.

PIN DESCRIPTIONS
DATA INPUTS

Shift Clock (Pin 11)

Parallel data inputs. Data on these inputs are stored in the
data latch on the rising edge of the Latch Clock input.

Serial shift clock. A low-to-high transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out QH, being replaced by the data
previously stored in stage G.

SA (Pin 14)

Latch Clock (Pin 12)

A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Data latch clock. A low-ta-high transition on this input
loads the parallel data on inputs A-H into the data latch.

Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored when
Serial Shift/Parallel Load is low.

Output Enable (Pin 10)
Active-low output enable A high level applied to this pin
forces the QH output into the high impedance state. A low
level enables the output. This control does not affect the
state of the input latch or the shift register.

CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)

OUTPUT

Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register accepts parallel data from the data latch.

High-Speed CMOS Logic Data
DL129-Rev6

QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3-state output.

3-497

MOTOROLA

MC54/74HC589A
TIMING DIAGRAM

SHIFT CLOCK
SERIAL DATA
INPUT,SA

l

I
I
I
I
I
I

OUTPUT ENABLE ~
SERIAL SHIFT!
I
PARALLEL LOAD ~ :

~

LATCH CLOCK ~

~

fl

~

A

L I
I II
B I L II
I II
I I

IH
I
IL
I
I

I II
D I L II
I II

I
IL
I

E

IH
I

I
IL
I
IL
I
I
IL
I

C~
PARALLEL
DATA
INPUTS

--Wt-1l
L

I

[3]

I

L

FJJhl

I II
GIL II
I II

I
IL
I

I
I

~I
IH
I
I
I

H IL I

L

II
II
II

L

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

II
II
II
II

H

:fl
II
II L
:I
II L
II
II
II L
II
II
II L
II
II
IIH
I
IH
I
I
IL
I
I
IH
I

I:II
II
II
II
II
II
II
II
II
II
II
II
jI

II
II
II
II
II
II
II
II
II
II
II
II

I

QH
I

f

f

1

RESET LATCH LOAD LATCH PARALLEL LOAD
AND SHIFT REGISTER
SHIFT REGISTER

MOTOROLA

1

LOAD LATCH

3-498

f

PARALLEL LOAD
SHIFT REGISTER

f

PARALLEL LOAD, LATCH
AND SHIFT REGISTER

High-Speed CMOS Logic Data

DL129-Rev6

MC54/74HC589A
LOGIC DETAIL

OUTPUT ENABLE ...;,;10'--_ _-Q
____________________________________,
SA...;,;14~

SHIFT CLOCK ...;,;11:....-_ _-1
SERIAL SHIFT/...,;;13"---_-I
PARALLEL LOAD

-----1
1
A 15

1

1
1
1
1

1
1
1
1

I

1

1-----

PARALLEL
DATA
INPUTS

1
1
1
1
1
1
1

r---- ---- ------------C 1....j

-----1
1
1
1
1
1
1
1

I
1

STAGE C'

~------------------------------I

I
~------------------------------I
E~L ______________________________ II
F~L ______________________________ II

D .Lj

STAGE 0'

STAGEE'

STAGEF'

6 1
G ---1

L____

H7

STAGE G'

1
1

_ ___ ~

1

r.~~

1

1

1
I D S 1
1
CR Q

1

1

1
L ____________________________1
I L-_-Q
'NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.

High-Speed CMOS Logic Data
DL129- Rev 6

3-499

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

a-Bit Serial-Input/Serial or
Parallel-Output Shift Register
with Latched 3-State Outputs

MC54/74HC595A
JSUFFIX
CERAMIC PACKAGE
CASE 620-10

High-Performance Silicon-Gate CMOS
The MC54174HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8-bit shift register and an 8-bit D-type latch
with three-state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8-bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
•
•
•
.,
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

o SUFFIX
SOIC PACKAGE
CASE 751 6--05

Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 JlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
Improved Propagation Delays
50% Lower Quiescent Power
Improved Input Noise and Latchup Immunity

DTSUFFIX
TSSOP PACKAGE
CASE 948F-Ol

ORDERING INFORMATION

MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

LOGIC DIAGRAM
SERIAL
DATA { A 14
INPUT

r--I---r--,
SHIFT
REGISTER

LATCH

Ceramic
Plastic
SOIC
TSSOP

PIN ASSIGNMENT
15 Q
1 A
QB
2 Qc
3Q
4 D
QE
5 QF

PARALLEL
DATA
OUTPUTS

QBI 1.

16

Qc I 2

15

~ VCC
~ QA

QDI 3

14

~A

QEI 4

13 ~ OUTPUT ENABLE

QF! 5

12

PLATCH CLOCK

QG

6

11 ~ SHIFT CLOCK

6 QG

QH

7

10 ~ RESET

7 QH

GND

8

9

PSQH

SHIFT 11
CLOCK
RESET
LATCH 12
CLOCK
OUTPUT 13
ENABLE

9
} SERIAL
'--1----1----'- SQH
DATA
OUTPUT

VCC= PIN 16
GND= PIN8

10/95

© Motorola, Inc, 1995

3-500

REV 6

®

MOTOROLA

MC54/74HC595A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±35

rnA

ICC

DC Supply Current, VCC and GND Pins

±75

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

- 65 to + 150

°c

Tstg
TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND" (VinorVout)" VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260
300

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage
(Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Unit

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

" 85°C

" 125°C

Unit

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
1I0uti " 20 JlA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.l VorVCC-O.l V
lIoutl " 20JlA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level Output
Voltage, QA - QH

Yin = VIH or VIL
lIoutl " 20 JlA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl " 6.0 rnA
lIoutl " 7.8 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

Yin = VIH or VIL
lIoutl " 20 JlA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL Iioutl " 6.0 rnA
lIoutl " 7.8 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

VOL

Maximum Low-Level Output
Voltage, QA - QH

Test Conditions

-55to
25°C

VIH

VOH

Parameter

VCC
V

V

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-501

MOTOROLA

MC54n4HC595A
DC ELECTRICAL CHARACTERISTICS (Continued)
Guaranteed Limit
Symbol
VOH

Test Conditions

Parameter

=

Minimum High-Level Output
Voltage. SQH

Vin VIH or VIL
"outl s 20 J.LA
Vin

VOL

=VIH or VIL

"outl s 4.0 rnA
"outl s 5.2 rnA

=

Maximum Low-Level Output
Voltage. SQH

Vin VIH or VIL
"outl s 20l1A
Vin

=VIH or VIL

=VCC or GND

"outl s 4.0 rnA
"outl s 5.2 rnA

lin

Maximum Input Leakage Current

Vin

10Z

Maximum Three-State Leakage
Current. QA - QH

Output in High-Impedance State
Vin VIL or VIH
Vout VCC or GND

=
=
Maximum Quiescent Supply
Vin =VCC or GND
ICC
Current (per Package)
lout =0 J.LA
AC ELECTRICAL CHARACTERISTICS (CL =50 pF. Input tr =tf =6.0 ns)

VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

V

6.0

±0.1

±1.0

±1.0

I1A

6.0

±0.5

±5.0

±10

I1A

6.0

4.0

40

160

I1A

Guaranteed Limit

Symbol

Parameter

VCC
V

-55to
25'C

s

s

125'C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)

2.0
4.5
6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

tpLH.
tpHL

Maximum Propagation Delay. Shift Clock to SQH
(Figures 1 and 7)

2.0
4.5
6.0

140
28
24

175
35
30

210
42
36

ns

tpHL

Maximum Propagation Delay. Reset to SQH
(Figures 2 and 7)

2.0
4.5
6.0

145
29
25

180
36
31

220
44
38

ns

tpLH.
tpHL

Maximum Propagation Delay. Latch Clock to QA - QH
(Figures 3 and 7)

2.0
4.5
6.0

140
28
24

175
35
30

210
42
36

ns

tpLZ.
tpHZ

Maximum Propagation Delay. Output Enable to QA - QH
(Figures 4 and 8)

2.0
4.5
6.0

150
30
26

190
38
33

225
45
38

ns

tpZL.
tpZH

Maximum Propagation Delay. Output Enable to QA - QH
(Figures 4 and 8)

2.0
4.5
6.0

135
27
23

170
34
29

205
41
35

ns

tTLH.
trHL

Maximum Output Transition Time. QA - QH
(Figures 3 and 7)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

trLH.
trHL

Maximum Output Transition Time. SQH
(Figures 1 and 7)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Cin

Maximum Input Capacitance

-

10

10

10

pF

Cout

Maximum Three-State Output Capacitance (Output in
High-Impedance State). QA - QH

-

15

15

15

pF

85'C

NOTE: For propagation delays with loads other than 50 pF. and Information on tYPical parametric values. see Chapter 2.
Typical @ 25'C. VCC

=5.0 V

300

Power Dissipation Capacitance (Per Package)·'

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations. see Chapter 2.

MOTOROLA

3-502

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC595A
TIMING REQUIREMENTS (Input tr

=tf =6.0 ns)
Guaranteed Limit

Symbol

Parameter

VCC
V

25°C to
-55°C

s 85°C

s 125°C

Unit

tsu

Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)

2.0
4.5
6.0

50
10
9.0

65
13
11

75
15
13

ns

tsu

Minimum Setup Time, Shift Clock to latch Clock
(Figure 6)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

th

Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)

2.0
4.5
6.0

5.0
5.0
5.0

5.0
5.0
5.0

5.0
5.0
5.0

ns

tree

Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)

2.0
4.5
6.0

50
10
9.0

65
13
11

75
15
13

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

tw

Minimum Pulse Width, Shift Clock
(Figure 1)

2.0
4.5
6.0

50
10
9.0

65
13
11

75
15
13

ns

tw

Minimum Pulse Width, latch Clock
(Figure 6)

2.0
4.5
6.0

50
10
9.0

65
13
11

75
15
13

ns

tr,tf

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

FUNCTION TABLE
Inputs

Operation

Reset

Serial
Input
A

Shift
Clock

Resulting Function
Latch
Clock

Output
Enable

Shift
Register
Contents

latch
Register
Contents

Serial
Output
SQH

Parallel
Outputs
QA-QH

Reset shift register

L

X

X

l,H, ' -

l

l

U

l

U

Shift data into shift
register

H

D

.J

l, H, ' -

l

D -.SRA;
SRN -.SRN+l

U

SRG -.SRH

U

Shift register remains
unchanged

H

X

l,H,'-

l, H, ' -

l

U

U

U

U

Transfer shift register
contents to latch register

H

X

l, H,'-

.J

l

U

SRN -.lRN

U

SRN

Latch register remains
unchanged

X

X

X

l, H,'-

l

·

U

Enable parallel outputs

X

X

X

X

l

Force outputs into high
impedance state

X

X

X

X

H

SR = shift register contents
lR = latch register contents

High-Speed CMOS logic Data
Dl129-Rev6

D = data (l, H) logiC level
U remains unchanged

=

X = don't care
Z = high impedance

3-503

·
·
*

..

.
.

Enabled

.*

*

Z

U

= depends on Reset and Shift Clock Inputs

*. =

depends on latch Clock input

MOTOROLA

MC54174HC595A
PIN DESCRIPTIONS
INPUTS

Latch Clock (Pin 12)

A (Pin 14)

Storage Latch Clock Input. A low-to-high transition on this
input latches the shift register data.

Serial Data Input. The data on this pin is shifted into the
a-bit serial shift register.

Output Enable (Pin 13)
Active-low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (QA-QH) into the highimpedance state. The serial output is not affected by this
control unit.

CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low- to-high transition on this
input causes the data at the Serial Input pin to be shifted into
the a-bit shift register.

OUTPUTS
QA - QH (Pins 15, 1,2,3,4,5,6,7)
Noninverted, 3-state, latch outputs.

Reset (Pin 10)

SQH (Pin 9)

Active-low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The a-bit latch is not affected.

Noninverted, Serial Data Output. This is the output of the
eighth stage of the a-bit shift register. This output does not
have three-state capability.

MOTOROLA

3-504

High-Speed CMOS Logic Data
DL129-Rev6

MC54i74HC595A
SWITCHING WAVEFORMS

VCC

VCC

SHIFT
CLOCK

RESET

-GND
tpHL

OUTPUT
SQH
OUTPUT
SQH

SHIFT
CLOCK

f=VCC
50%,
-GND

Figure 2.

Figure 1.

VCC

OUTPUT
ENABLE

VCC

LATCH
CLOCK

HIGH
IMPEDANCE
OUTPUTQ
QA-QH
OUTPUTS

OUTPUTQ

Figure 3.

SERIAL
INPUT A

LATCH
CLOCK

Figure 4.

&;":1

SHIFT
CLOCK

VCC
GND

LATCH
CLOCK

-VCC

50%

-VCC

=1'0%

\

~a

-VCC

50%

GND

tw

LGND

Figure 5.

Figure 6.

TEST CIRCUITS
TEST POINT

TEST POINT

1 kn
1-0_U_T_PU_T_+-'VV'v-_

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

'- CL'

I

CONNECTTO VCC WHEN
TESTING tpLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tpHZ AND tpZH.

I

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 7.

High-Speed CMOS Logic Data
DL129-Rev6

GND

Figure 8.

3~505

MOTOROLA

raJ

MC54/74HC595A
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE

13

LATCH
CLOCK

12

SERIAL
DATA
INPUT A

14

D
--C

D

Q

I> SRA

>-------(

Q

15

I> LRA

R

LD
--C

D

Q

I> SRS

>-------(

Q

1

aB

I> LRS

R

LD

D

Q

--c I> SRC

>-------(

a

2

QC

~ LRC

R

LD

D

a

--c I> SRD

>-------(

a

3

I> LRD

PARALLEL
DATA
OUTPUTS

R

LD

D

a

--c ~ SRE

>-------(

aD

a

4

~ LRE

R

LD

Q

D

Q

5

--c I> LRF

--c I> SRF
R

LD

a

--c I> SRG

D

a

6

--c I> LRG

R

SHIFT
CLOCK

LD
11

a

D

a

7

--c I> LRH

SRH
R

RESET

MOTOROLA

10

9

3-506

SERIAL
DATA
°iJTPUTSaH

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC595A
TIMING DIAGRAM

SHIFT
CLOCK

~

SERIAL DATA
INPUT A
RESET

_________________Jr_lL..._______

~'-_~

LATCH
CLOCK _ _ _ _ _ _

___JIIL..._____. . .I1L...__________J1
I.

OUTPUT
ENABLE

I

L . ._ _ _ _ _ _ _ _ _ _ _ _ _

~XXI
OB

______________________

OC ______________________~D<~X~~

OD ______________________~D<~X~~~

D<~~

--'1, - ,L-..JI

SERIAL DATA - - - ,
OUTPUT SOH

L . ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

NOTE: ~ implies that the output is in a high-impedance
state.

High-Speed CMOS Logic Data
DL129-Rev6

3-507

MOTOROLA

131

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

a-Bit Serial or Parallel-Input/
Serial-Output Shift Register
with Input Latch

MC54/74HC597
JSUFFIX

High-Performance Silicon-Gate CMOS

CERAMIC PACKAGE
CASE 62D-10

The MC54174HC597 is identical in pinout to the LS597. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of an 8-bit input latch which feeds parallel data to an
8-bit shift register. Data can also be loaded serially (see Function Table).
The HC597 is similar in function to the HC589, which is a 3-state device.

PLASTIC PACKAGE
CASE 64B-l-""--"'-"'-'''--''-'''-''-''--''-t''--''-..l''--''-'''-'''-''''--'''--''''-''-''---''--''--''-..>l--''-'''-'''-'''--''--'''-''-''---'' GND
A-TO-B
SOURCE

~---------------------------GND

~TO-A~~~-*~~~~~~~~~~~~~~~~~~~~~~~~~~~~--VCC

SOURCE~'-"'-"~~-"---"-~~-"--"-~~~~~~~~~~'--"''-'''-'''-''-''--''--''---''-~-''-'''''''~~GND
ADATA PORT
~----~------4------------------------------GND

BDATA PORT

NOTES:
1. B Data Port (output) changes from the level of the storage flip-flop, QA, to the level of A Data Port (input).
2. B Data Port (output) changes from the level of the A Data Port (input) to the level of the storage flip-flop, QA.
3. The A storage flip-flop, A-to-B Source, and A Data Port (input) have simultaneously changed states.

Figure 5. A Data Port

MOTOROLA

=Input, B Data Port =Output

3-536

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC646

-Vcc
OUTPUT ENA8LE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ GND
DIRECTION

-Vcc
----------------------------------GND

Vcc

INTERNALQ8
(FLIP-FLOP 8)

-GND

Vcc

A-T0-8
SOURCE

GND

B-TO-A
SOURCE

~--------------------------GND

ADATA PORT

®
-Vcc

8 DATA PORT

~----------------------GND

®

NOTES:
I. A Data Port (output) changes from the level of the storage flip-flop, OB, to the level of B Data Port (input).
2. A Data Port (output) changes from the level of the B Data Port (input) to the level of the storage flip-flop, OB.
3. The B storage flip-flop, B-to-A Source, and B Data Port (input) have simultaneously changed states for the purpose of this
example. A Data Port (output) is now displaying the voltage level of B Data Port (input).

Figure.6. A Data Port

=Output, B Data Port =Input

PIN DESCRIPTIONS
INPUTS/OUTPUTS

Direction is high, the A data ports are inputs and the B data
ports are outputs. When Direction is low, the A data ports are
outputs and the B data ports are inputs.

AO-A7 (Pins 4-11) and BO-87 (Pins 20-13)
A and B data ports. These pins may function either as inputs to or outputs from the transceivers.

A-to-B Clock, B-to-A Clock (Pins 1, 23)
Clocks for the internal D flip-flops. With a low-to-high
transition on the appropriate Clock pin, data on the A (or B)
inputs are clocked into the internal A (or B) flip-flops. These
clocks are not internally gated with the Output Enable or the
Direction pins, therefore data at the A and B pins may be
clocked into the storage flip-flops at any time.

CONTROL INPUTS
Output Enable (Pin 21)
Active-low output enable. When this pin is low, the outputs
are enabled arid function normally. When this pin is high, the
A and B data ports are in high-impedance states. See the
Function Table.

A-to-B Source, B-to-A Source (Pins 2, 22)

Direction (Pin 3)

Data-source selection pins. Depending upon the states of
these pins (see the Function Table), data at the outputs may
come either from the inputs or from the D flip-flops.

Data direction control. When the Output Enable pin is low,
this control pin determines the direction of data flow. When

High-Speed CMOS Logic Data
DL129-Rev6

3-537

MOTOROLA

MC54/74HC646
--VCC
OUTPUT ENABLE_____________________________________ GND
~-----VCC

HIGH IMPEDANCE
HIGH IMPEDANCE

VOH

VOL

DATA PORT A = INPUT
DATA PORT B =OUTPUT

DATA PORT A = OUTPUT
DATA PORT B = INPUT

Figure 7.

r---VCC
OUTPUT ENABLE
HIGH
IMPEDANCE
OUTPUTAORB

OUTPUTAORB

FigureS.

TEST POINT

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

I

CONNECTTO VCC WHEN
TESTING tpLZ AND tpZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tpZH

• Includes all probe and jig capacitance

• Includes all probe and jig capacitance

Figure 9. Test Circuit

MOTOROLA

1 kU

Figure 10. Test Circuit

3-538

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC646
LOGIC DETAIL

I
I
I
I

I
+-j..-:::20_ BO

HC646
HC648

Iffi

,---+-+-_ _....1
« co
«

1co
(,)

(,)

A1--Ll
6 --

A2~ _ _
A3

~--

A4--

A5~----

A6~
A7~

TBA

SBA
SAB

DIRECTION 3
OUTPUT ENABLE 21

TBA

TAB

TAB

High-Speed CMOS Logic Data

DL129-Rev6

3 539

~=<;1

CBA

~=<;1

CAB

B
A 1 MHz

-=

VCC - :r.;tf = ~
GND..J L..J L CONTROL _ _ _ _ _-'
-Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set-Up

MOTOROLA

Figure 8. Propagation Delays, Analog In to

Analog Out

3-552

High-Speed CMOS Logic Data
Dl129-Rev6

MC54/74HC4016
tf

TEST

1-+--......--0 POINT

I""'F-----GND
tpZl

HIGH
IMPEDANCE

tpZH
HIGH
IMPEDANCE

'Includes all probe and jig capacitance.

Figure 9. Propagation Delay Test Set-Up

POSITION

CD
CD

-::-

POSITION

Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

CD WHEN TESTING tpHZ AND tPZH
® WHEN TESTING tPlZ AND tpZl

VCC

14

VOS

VCC

VCC

tkQ

t4

TEST
POINT

I

Cl'

VCC/2

VCC/2

VCC/2
'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance

Figure 11. Propagation Delay Test Set-Up

NC---+-\

Figure 12. Crosstalk Between Any Two SWitches,
Test Set-Up

I-I----NC

I--~~----<~-O

TO
DISTORTION
METER

SELECTED
CONTROL
INPUT

...rL.rl ON/OFF CONTROL _ _--'
'Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance
Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

Figure 14. Total Harmonic Distortion, Test Set-Up

3-553

MOTOROLA

.MC54174HC4016
0

~ t-...

II

..1

-20

E

CD

I

,
,
,

II
-40 II
-30

-c

,
,

~FUNDAMENTALFREQUENCY

-10

-

-50
-60

- ~-

-

- --

,
,
- - 7 - -

,

~

, I

-

-

- -

-

DEVICE

- --

SOURCE

AI!
11\
•
"I'lil
I\I\JIW', WlJA.l\lAJ\
lIP., ,
•

-70

t1.

-80

[hAlL.!

-90

!

I

-100

I

'I'

1.0

"~,,?,,,, ~
2.0

3.0

FREQUENCY (kHz)

Figure 15. Plot, Harmonic Distortion

APPLICATION INFORMATION
The ON/OFF Control pins should be at Vee or GND logic
levels, Vee being recognized as logic high and GND being
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is advisable
to tie. unused analog inputs and outputs to Vee or GND
through a low value resistor. This minimizes crosstalk and
feedthrough noise that may be picked up by the unused I/O
pins.
The maximum analog voltage swings are determined by
the supply voltages Vee and GND. The positive peak analog
voltage should not exceed Vee. Similarly, the negative peak
analog voltage should not 'go below GND. In the example

below, the difference between Vee and GND is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
analog signal of twelve volts peak-to-peak can be controlled.
When voltage transients above Vee and/or below GND
are antiCipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn-on types able to absorb the
maximum antiCipated current surges during clipping. An alternate method would be to replace the Dx diodes with
MO-sorbs (Motorola high current surge protectors).
MO-sorbs are fast turn-on devices ideally suited for precise
DC protection with no inherent wear-out mechanism.
VCC=12V

+12VOV-

f\ . ANALOGIIO

14 ANALOGOII

V

f\ -+12V
. V- OV

OTHER CONTROL
INPUTS
(VCCOR GND)

Figure 16.12 V Application

Ox

Ox

VCC
OTHER CONTROL
INPUTS
(VCCORGND)

Figure 17. Transient Suppressor Application

MOTOROLA

3-554

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC4016
+5V

+5V

I

R'. R' R' R'

LSrrU
NMOS

~}
r--

ANALOG
SIGNALS

r-HC"T-'
I BUFFER I

Lsrru
NMOS

5

, }ew..

14

14

ANALOG {
SIGNALS

HC4016

~

I

} ANALOG
SIGNALS

HC4016

I

INPUTS

15

1.

f-

14

ANALOG{=
SIGNALS . =

7

1.

R'=2TO 10kQ

a. Us!ng Pull-Up Resistors

b. Using HCT Buffer
Figure 18. LSTTLJNMOS to HCMOS Interface

VCC=5TO 12V

VDD = 5 V

14

ANALOG {
SIGNALS

HC4016

5

7

} ANALOG
SIGNALS

MC14504

11

2
4

6

6

14

10

15

}eoo..
INPUTS

7

Figure 19. TTLJNM05-to-CMOS Level Converter
Analog Signal Peak-to-Peak Greater than 5 V
(Also see HC4316)

CHANNEL 4

CHANNEL 3
COMMON 1/0
CHANNEL 2

CHANNEL 1

INPUT

10F4
SWITCHES

>-__ OUTPUT

r

0.01 I!F

1

2
3 4
CONTROL INPUTS

High-Speed CMOS Logic Data
DL129-Rev6

3-555

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

IMC54/74HC4016A I

Product Preview

Quad Analog Switch/
Multiplexer/Demultiplexer

J SUFFIX
CERAMIC PACKAGE

High-Performance Silicon-Gate CMOS

CASE632~B

The MC54/74HC4016A utilizes silicon-gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFFchannel leakage current. This bilateral switch/multiplexer/demultiplexer
controls analog and digital voltages that may vary across the full
.
power-supply range (from VCC to GND).
The HC4016A is identical in pinout to the metal-gate CMOS MC14016
and MC14066. Each device has four independent switches. The device
has been designed so that the ON resistances (RON) are much more
linear over input voltage than RON of metal-gate CMOS analog switches.
. This device is identical in both function and pinout to the HC4066A. The
ON/OFF Control inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs. For analog
switches with voltage-level translators, see the HC4316A. For analog
switches with lower RON characteristics, use the HC4066A.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE646~6

DSUFFIX
SOIC PACKAGE
CASE751A~3

DTSUFFIX
TSSOP PACKAGE
CASE94BG~1

Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Low Crosstalk Between Switches
Diode Protection on AlllnputslOutputs
Wide Power-Supply Voltage Range (VCC - GND) 2.0 to 12.0 Volts
Analog Input Voltage Range (VCC - GND) = 2.0 to 12.0 Volts
Improved Linearity and Lower ON Resistance over Input Voltage than
the MC14016 or MC14066

ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT

=

• Low Noise
• Chip Complexity: 32 FETs or 8 Equivalent Gates

PIN ASSIGNMENT

XB 1
BON/OFF
CONTROL
CON/OFF
CONTROL
GND

XB~YB

XC~YC
C ON/OFF CONTROL

PYD

9

PYc

7

8

~ Xc

14

ANALOG
OUTPUTSIINPUTS

~

FUNCTION TABLE

XD~YD
DON/OFF CONTROL

10

6

YBl 3

~
~

5

YA[ 2

XA~YA

BON/OFFCONTROL

4

PVCC
A ON/OFF
13 ~ CONTROL
12 ~ DON/OFF
~ CONTROL
11 XD

XA[ 1-

LOGIC DIAGRAM

A ON/OFF CONTROL

Ceramic
Plastic
SOIC
TSSOP

On/Off Control
Input

State of
Analog Switch

L
H

Off
On

~

ANALOG INPUTS/OUTPUTS =XA, XB, XC, XD
PIN 14=VCC
PIN 7= GND
This document contains information on a product under development. Motorola reserves the rtght to change or discontinue this product without notice.

10/95

© Motorola, Inc. 1995

3-,-556

REV 0

®

MOTOROLA ..

MC54174HC4016A
MAXIMUM RATINGS·
Parameter

Symbol

Value

Unit

- 0.5 to + 14.0

V
V

VCC

Positive DC Supply Voltage (Referenced to GND)

VIS

Analog Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

Digital Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Current Into or Out of Any Pin

±25

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

-65to+150

·C

Vin
I

TL

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND :!i (Vin or Vout) :!i VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus .

·C

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/·C from 65· to 125·C
Ceramic DIP: -10 mW/·C from 100· to 125·C
SOIC Package: - 7 mW/"C from 65" to 125"C
TSSOP Package: - 6.1 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

2.0

12.0

V

Analog Input Voltage (Referenced to GND)

GND

VCC

V

Vin

Digital Input Voltage (Referenced to GND)

GND

VCC

V

VIO'

Static or Dynamic Voltage Across Switch

VCC

Positive DC Supply Voltage (Referenced to GND)

V'S

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time, ON/OFF
Control Inputs (Figure 10)

VCC=2.0V
VCC=3.0V
VCC=4.5V
VCC = 9.0 V
VCC = 12.0 V

-

1.2

V

-55

+ 125

·C

0
0
0
0
0

1000
600
500
400
250

ns

• For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

-SSto
2S"C

:!i 8S"C

:!i 12S"C

Unit

VIH

Minimum High-Level Voltage
ON/OFF Control Inputs

Ron = per spec

2.0
3.0
4.5
9.0
12.0

1.5
2.1
3.15
6.3
8.4

1.5
2.1
3.15
6.3
8.4

1.5
2.1
3.15
6.3
8.4

V

V,L

Maximum Low-Level Voltage
ON/OFF Control Inputs

Ron = per spec

2.0
3.0
4.5
9.0
12.0

0.5
0.9
1.35
2.70
3.6

0.5
0.9
1.35
2.70
3.6

0.5
0.9
1.35
2.70
3.6

V

High-Speed CMOS Logic Data
DL129-Rev6

Test Conditions

VCC
V

3-557

MOTOROLA

MC54174HC4016A
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

Symbol

Parameter

s 85°C

s 125°C

Unit

lin

Maximum Input leakage Current.
ON/OFF Control Inputs

Vin = Vce or GND

12.0

±O.1

±1.0

±1.0

IIA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
VIO=OV

6.0
12.0

2
4

20
40

40
160

IIA

s 125°e

Unit

ICC

Test Conditions

NOTE: Information on typical parametric values can be found in Chapter 2.

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Ron

Parameter

Test Conditions

Maximum "ON" Resistance

Vin=VIH
VIS = VCC to GND
IS s 2.0 mA (Figures 1. 2)
Vin=VIH
VIS = VCC or GND (Endpoints)
IS s 2.0 mA (Figures 1. 2)

Vee
V
2.0t
4.5
9.0
12.0
2.0
, 4.5
9.0
12.0

-55to
25°e

s

-

85°e

-

-

200
110
110

160
90
90

Q

240
130
130

-

-

-

90
70
70

115
90
90

140
105
105

Maximum Difference in "ON"
Resistance Between Any Two
Channels in the Same Package

VinVIH
VIS = 1/2 (VCC - GND)
IS s 2.0mA

2.0
4.5
9.0
12.0

-

-

-

20
15
15

25
20
20

30
25
25

loff

Maximum Off-Channel leakage
Current. Any One Channel

"in = Vil
VIO = Vec or GND
Switch Off (Figure 3)

12.0

0.1

0.5

1.0

IIA

Ion

Maximum On-Channel leakage
Current. Any One Channel

Vin=VIH
VIS = VCC or GND
(Figure 4)

12.0

0.1

0.5

1.0

IIA

&Ron

Q

tAt supply voltage (VCC - GND) approaching 3 V the analog switch-on resistance becomes extremely non-linear. Therefore. for low-voltage
operation. it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF. ON/OFF Control Inputs: tr = tf = 6 ns)
Guaranteed Limit
VCC
V

-55to
25°e

tplH.
tPHl

Maximum Propagation Delay. Analog Input to Analog Output
(Figures 8 and 9)

2.0
4.5
9.0
12.0

40
5
5
5

50
7
7
7

60
8
8
8,

ns

tPLZ.
tpHZ

Maximum Propagation Delay. ON/OFF Control to Analog Output
(Figures 10 and 11)

2.0
4.5
9.0
12.0

80
20
20
20

90
25
25
25

110
35
35
35

ns

tpZl.
tpZH

Maximum Propagation Delay. ON/OFF Control to Analog Output
(Figures 10 and 11)

2.0
4.5
9.0
12.0

80
20
20
20

90
25
25
25

100
30
30
30

ns

Symbol

MOTOROLA

Parameter

3-558

s

85°e

s

125°C

Unit

High-Speed CMOS logic Data
Dl129-Rev6

MC54/74HC4016A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Guaranteed Limit
Symbol
C

VCC
V

-55to
25°C

ONIOFF Control Input

-

10

10

10

Control Input = GND
Analog 1/0
Feedthrough

-

35
1.0

35
1.0

35
1.0

Parameter
Maximum Capacitance

-

s

85°C

s

125°C

Unit
pF

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°C, VCC = 5.0 V
Power Dissipation Capacitance (Per Switch)' (Figure 13)

15

'Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND unless noted)
VCC
V

Limit"
25°C
54174HC

4.5
9.0
12.0

150
160
160

MHz

dB

Symbol

Parameter

Test Conditions

BW

Maximum On-Channel Bandwidth or
Minimum Frequency Response
(Figure 5)

fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter Reads - 3 dB
RL=50Q,CL=10pF

Oil-Channel Feedthrough Isolation
(Figure 6)

fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Q, CL = 50 pF

4.5
9.0
12.0

-50
-50
-50

fin = 1.0 MHz, RL = 50 Q, CL = 10 pF

4.5
9.0
12.0

-40
-40
-40

Vin s 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 n, CL = 50 pF

4.5
9.0
12.0

60
130
200

RL = 1'0 kQ, CL = 10 pF

4.5
9.0
12.0

30
65
100

fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin 10 kHz, RL = 600 n, CL = 50 pF

4.5
9.0
12.0

-70
-70
-70

n, CL = 10 pF

4.5
9.0
12.0

-80
-80
-80

-

-

-

Feedthrough Noise, Control to Switch
(Figure 7)

Crosstalk Between Any Two Switches
(Figure 12)

==

==

=

fin = 1.0 MHz, RL = 50

THD

Total Harmonic Distortion
(Figure 14)

=

fin 1 kHz, RL = 10 kQ, CL = 50 pF
THD = THDMeasured - THDSource
VIS = 4.0 VPP sine wave
VIS 8.0 Vpp sine wave
VIS = 11.0 Vpp sine wave

=

Unit

mVpp

dB

%
4.5
9.0
12.0

0.10
0.06
0.04

" Guaranteed limits not tested. Determined by design and verified by qualification ..

High-Speed CMOS Logic Data
DL129-Rev6

3-559

MOTOROLA

MC54/74HC4016A
3000

300

en 2500

en 250

::0

::0

:c

:c
Q. 200

~ 2000

~~ 150

TBO

(.)

~
~ 1500
c;;
UJ
a::
is 1000

~

is 100
"o
a:: 50

"o

a:: 500

o
o

o
o

.25
.50
.75
1.00 1.25
1.5 1.75 2.00
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1a. Typical On Resistance,

Vee = 2.0 V

UJ

100

:c
Q.
(.)

z

[3]

i::!:
en
c;;
UJ
a::

z
0

Vee = 4.5 V

en

100

::0

:c
Q. 80
UJ

TBO

80

'rBO

(.)

z

i::!:
en
c;;
UJ
a::

60

z

60
40

0

40
C:
0

a::

4.5

120

140
120

.5
1.0
1.5
2.0
2.5 3.0
3.5
4.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1b. Typical On Resistance,

160

en
::0

rBO

:5 20

a::

20

o

o

1.0

.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1c. Typical On Resistance,

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Vee =6.0 V

Figure 1d. Typical On Resistance,

Vee = 9.0 V

80
70

en
::0

60

UJ

50

:c
Q.
(.)

TBO

z

i::!:
en
UJ
a::

!Q

PROGRAMMABLE
POWER
SUPPLY

40

.---~r:;;:=~
DEVICE
UNDER TEST

30

z

0

a::"

DC ANALYZER

Vee

20

0

ANALOG IN

10
00

1.0 2.0 3.0 4.0

5.0

6.0 7.0 8.0 9.0 10.011.0 12.0

':' GND

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1e. Typical On Resistance,

MOTOROLA

eOMMONOUT

Vee = 12.0 V

Figure 2. On Resistance Test Set-Up

3-560

High-Speed CMOS Logic Data

DL129-Rev6

MC54/74HC4016A

Vee
Vee

I-I----N/C

7

Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up

fin

Figure 4. Maximum On Channel Leakage Current,
Channel to Channel, Test Set-Up

o-J 1---1';

~n

O.1JlF

o-J 1--+--+-1
O.1JlF
SELECTED
CONTROL
INPUT
7

'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance.

Figure 5. Maximum On-Channel Bandwidth
Test Set-Up

Vee

Vee/2

Figure 6. Off-Channel Feedthrough Isolation,
Test Set-Up

VeC/2

'------GND
Vin';; 1 MHz
tr~tf~6ns

-=

Vee-n n
GND....J L.J L eONTROL _ _ _ _ _--'
'Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

Figure 8. Propagation Delays, Analog In to
Analog Out

3-561

MOTOROLA

MC54174HC4016A
If
TEST

I-+--......-.() POINT

j r : - - - - - GND

HIGH
IMPEDANCE

IPZH
HIGH
IMPEDANCE

'Includes all probe and jig capacitance.

Figure 9. Propagation Delay Test Set-Up

POSITION

-=

CD
®

POSITION

Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

CD WHEN TESTING tpHZ AND tPZH
® WHEN TESTING tPLZ AND tpZl
VCC
14

VCC

VIS

lkn
TEST
POINT

I

Cl'

VCC/2
'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance

Figure 11. Propagation Delay Test Set-Up

NC----H

Figure 12. Crosstalk Between Any Two Switches,
Test Set-Up

1--1----- NC

I-~~_'--O

TO
DISTORTION
METER

SELECTED
CONTROL
INPUT

nn

ON/OFF CONTROL _ _---'
'Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance
Test Set-Up

MOTOROLA

Figure 14. Total Harmonic Distortion, Test Set-Up

3-562

High-Speed CMOS Logic Data
DL129-Rev6

MC54n 4HC4016A

,
~ ~F~NDAJENTA~FREciuENC~
,

-10
-20
-30
-40

II

E

'"

"0

,

t-

--

-50
-60
-70

- -

- -

- -

,
,
,
,
i' ,

- -

-

--

-

DEVICE

~

- --

SOURCE

V Ii\

~
A I\ll
W\
M
lAJ\
lhAU'
~
IV~
W W" , I ,..,

-80

I' Til"

-90
-100

, It "., ,

~.

1.0

2.0

3.0

FREQUENCY (kHz)

Figure 15. Plot, Harmonic Distortion
below, the difference between Vee and GND is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
analog signal of twelve volts peak-to-peak can be controlled.
When voltage transients above Vee and/or below GND
are anticipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn-on types able to absorb the
maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with
MO-sorbs (Motorola high current surge protectors).
MO_sorbs are fast turn-on devices ideally suited for precise
DC protection with no inherent wear-out mechanism.

APPLICATION INFORMATION
The ON/OFF Control pins should be at Vee or GND logic
levels, Vee being recognized as logic high and GND being
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is advisable
to tie unused analog inputs and outputs to Vee or GND
through a low value resistor. This minimizes crosstalk and
feedthrough noise that may be picked up by the unused I/O
pins.
The maximum analog voltage swings are determined by
the supply voltages Vee and GND. The positive peak analog
voltage should not exceed Vee. Similarly, the negative peak
analog voltage should not go below GND. In the example

VCC = 12V
+12V-

f\

OV-'

~ ANALOGI/O

ANALOGOII

f\

-+12V

. V- OV

V

OTHER CONTRO~
INPUTS
(VCCOR GND)

Figure 16. 12 V Application

Dx

Dx
VCC

-=

SELECTED

1..-.----1 CONTROL
INPUT

7

OTHER CONTROL
INPUTS
(VCCORGND)

Figure 17. Transient Suppressor Application

High-Speed CMOS LogiC Data

DL129-Rev6

3-563

MOTOROLA

[3J
3

MC54174HC4016A
+5V

+5V

ANALOG
SIGNALS
R" R' R' R'

LSTTU
NMOS

I

{=
.=

~

I--

5
6
14

14

ANALOG {
SIGNALS

} ANALOG
SIGNALS

r-HCT- '

HC4016

1- ?' ?' 1-

I
I

LSTTU
NMOS

}~

BUFFER

I
I

} ANALOG
SIGNALS

HC4016

INPUTS

15

1-

I--

14

7

1-

R"~2T010kn

a. Using Pull-Up Resistors

b. Using HCr Buffer
Figure 18. LSTTUNMOS to HCMOS Interface

VDD~5

VCC~5TO

V

12V

14

ANALOG {
SIGNALS

} ANALOG
SIGNALS

HC4016

7

MC14504

5

2

9

4

6

11

6

14

14

10

15

}~
INPUTS

7

Figure 19. TTUNM05-to-CMOS Level Converter
Analog Signal Peak-to-Peak Greater than 5 V
(Also see HC4316A)

CHANNEL 4

CHANNEL 3
COMMON 110
CHANNEL 2

CHANNELl

INPUT

1

MOTOROLA

2
3 4
CONTROL INPUTS

3-564

10F4
SWITCHES

>---OUTPUT

r

0.01 flF

High-Speed CMOS Logic Data

DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4017

Decade Counter
High-Performance Silicon-Gate CMOS
The MC74HC4017 is identical in pinout to the standard CMOS
MC14017B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC4017 uses a five stage Johnson counter and decoding logic to
provide high-speed operation. This device also has an active-high, as well
as active-low clock input.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 IlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
• Chip Complexity: 176 FETs or 44 Equivalent Gates

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

16#

DSUFFIX
SOIC PACKAGE
CASE 7518-05

ORDERING INFORMATION

MC74HCXXXXN
MC74HCXXXXD

LOGIC DIAGRAM

Plastic
SOIC

PIN ASSIGNMENT

CLOCK
CLOCK
ENABLE
10

OS[ 1-

16

VCC

00

01[ 2

15

RESET

01

00 [ 3

14 ] CLOCK

02

02 [ 4

13

03

06 [ 5

12 ] CARRY OUT

04

DECADE
OUTPUTS

05
06

CLOCK ENABLE

07[ 6

11 J 09

03 [ 7

10 ] 04

GNO [ 8

9

08

07
08
11
12

RESET 15

09

CARRY OUT

PIN 16= VCC
PIN 8=GND

10/95

©

Motorola. Inc. 1995

3-565

REVS

®

MOTOROLA

MC74HC4017
MAXIMUM RATINGS·
Symbol

VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V

Yin

DC Input Vo~age (Referenced to GND)

-1.5toVCC+ 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature

-65to+150

'C

TL

Plastic DIPt
SOIC Packaget

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circun. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin orVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., enher GND or VCC).
Unused outputs must be left open.

'c

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol

VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme
(Figure 1)

VCC=2.0V
VCC =4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

'C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25'C

s 85'C

s 125'C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
IIoutl s 20 J1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCC-O;1 V
IIoutl s 20 "A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

VOH

Minimum High-Level Output
Voltage

Yin = VIH or VIL
"outl s 20 "A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

6.0

±0.1

± 1.0

±1.0

J1A

6.0

8

80

160

f!A

Yin
VOL

Maximum Low-Level Output
Voltage

ICC

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

=VIH or VIL

IIoutl s 4.0 rnA
IIoutl s 5.2 rnA

=VCC or GND
Yin =VCC or GND
lout =0 J1A

Yin

NOTE: Information on typical parametric values can be found

MOTOROLA

lIoutl s 4.0 rnA
lIoutl s 5.2 rnA

Yin =VIH or VIL
lIoutl s 20 J1A
Yin

lin

=VIH or VIL

In

V

Chapter 2.

3-566

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4017
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

:s 85°e

:s 125°e

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 9)

2.0
4.5
6.0

4.0
20
24

3.2
16
19

2.6
13
15

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Q
(Figures 1 and 9)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

tPLH,
tpHL

Maximum Propagation Delay, Clock to Carry Out
(Figures 2 and 9)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

tpLH,
tpHL

Maximum Propagation Delay, Reset to Q
(Figures 3 and 9)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

tpLH

Maximum Propagation Delay, Reset to Carry Out
(Figures 3 and 9)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

tpLH,
tPHL

Maximum Propagation Delay, Clock Enable to Q
(Figures 4 and 9)

2.0
4.5
6.0

250
50
43

315
63
54

375
75
64

ns

tpLH,
tpHL

Maximum Propagation Delay, Clock Enable to Carry Out
(Figures 5 and 9)

2.0
4.5
6.0

250
50
43

315
63
54

375
75
64

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 8 and 9)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Packager

=5.0 V

35

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129- Rev 6

3-567

MOTOROLA

MC74HC4017
TIMING REQUIREMENTS (Input tr =tf =6 ns)t
Guaranteed Limit
VCC
V

-55to
25°C

s 85°C

s 125°C

Unit

tsu

Minimum Setup Time, Clock Enable to Clock
(Figure 6)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

tsu

Minimum Setup Time, Clock Enable to Clock (Inhibit Count)
(Figure 6)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

th

Minimum Hold Time, Clock to Clock Enable
(Figure 6)

2.0
4.5
6.0

50
10
9

65
13
11

75
15
13

ns

Minimum Recovery Time, Reset to Clock
(Figure 7)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tw

Minimum Pulse Width, Clock Input
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width, Reset Input
(Figure 3)

2.0
4.5
6.0

80
16
14

100
.20
17

120
24
20

ns

tw

Minimum Pulse Width, Clock Enable Input
(Figure 4)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tr,tl

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

trec

Parameter

NOTE: Information on tYPical parametric values can be found

10

Chapter 2.

FUNCTION TABLE
Clock
L
X
X

Clock
Enable

J
\...

X
H
X
L
X

X
H

J
\...

Reset

Output State'

L
L
H
L
L
L
L

no change
no change
reset counter, 00 =H, 01-09 =L, CO =H
advance to next state
no change
no change
advance to next state

X = Don't care
• Carry Out =H for 00, 01, 02, 03, or 04 =H; Carry Out =L otherwise.

PIN DESCRIPTIONS
INPUTS

negative-edge clock input. using Clock (Pin 14) as an
active-high enable pin.

Clock (Pin 14)

OUTPUTS

Counter clock input. While Clock Enable is low, a low-tohigh transition on this input advances the counter to its next
state.

QO-Q9 (Pins 3, 2, 4, 7,10,1,5,6,9,11)
Decoded decade counter outputs. Each of these outputs is
high for one clock period only.

Reset (Pin 15)
Asynchronous counter reset input. A high level at this input
initializes the counter and forces QO and Carry Out to a high,
Q1-Q9 are forced to a low level.

Carry Out (Pin 12)
Cascading output pin. This output is used either as a cascading output or a symmetrical divide-by-ten output. This
output goes low when a count of five is reached and high
when the counter advances to zero or when reset. When the
counters are cascaded this output provides a rising-edge
signal for the clock input of the next counter stage.

Clock Enable (Pin 13)
Active-low clock enable input. A low level on this input allows the device to count. A high level on this input inhibits the
counting operation. This input may also be used as a

MOTOROLA

3-568

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4017
SWITCHING WAVEFORMS

VCC
CLOCK
GND

CLOCK
tPLH
CARRY
OUT
Q

Figure 2.

Figure 1.
VCC
GND

CLOCK
ENABLE

RESET
GND

Q

tw

Figure 4.

Q1-Q9
VCC
GND
QO, CARRY OUT

VCC

CLOCK
ENABLE

GND

Figure 3.

VCC
CLOCK
-

CLOCK
ENABLE

~

VCC

GND

Figure 6.

50%

- - GND
tPLH

tpHL

trHL

CARRY
OUT

QO-Q9,
CARRY OUT

Figure 5.

Figure 8.

TEST POINT
OUTPUT

CLOCK

~

RESET

-~",5_0%_,_ _ _ _ _ _ _
_

DEVICE
UNDER
TEST

VCC

50%

GND

trec

VCC
GND

-

• Includes all probe and jig capacitance

Figure 7.

High-Speed CMOS Logic Data

DL129-Rev6

Figure 9. Test Circuit

3-569

MOTOROLA

[3J

MC74HC4017
TIMIING DIAGRAM

CLOCK

-..1LJl..r

CLOCK
ENABLE

""'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

RESETJlL---~-------------------'1
~__________________~r_l
I
QO _.J'
01

02

-,
I

II~------------------~~

IL

---I.i_____--'r_l
r_l~

04-'
- - I . I - - -_ _ _ _ _

05-'

~I~

OS

______________________

r--l

~I

I~

__________

_ _ _ _ _ _ _ _ _ _ _ ___

r - - l1""'-_ _ _ _ _ _ _ _ _ _ __

~I

-,,

r_l~

______________

r_l~

___________

1lL---_________

111-_______
CARRY .J'
OUT-

MOTOROLA

3-570

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4017
EXPANDED LOGIC DIAGRAM

Q~'-------+---'

c

R

Qb-+-.-----~~~------------~

RESET 15

High-Speed CMOS Logic Data

DL129-Rev6

3-571

MOTOROLA

MC74HC4017
TYPICAL APPLICATIONS
VCC

+5

05

HC4017

01
00
+2

02

+6

06

07
+7
7
+3.---....:-.r 03

16

VCC

RESET

15

14
CLOCK
CLOCK 13
ENABLE
12
CARRY OUT
11
09
10
04

GND

+10
+9
+4

08

-=

+8
1/6 HC04

OUTPUT
BUFFER
(OPTIONAL TO PREVENT SPURIOUS RESEl)

Figure 10 shows a divide by 2 through 10 circuit using one HC4017. Please note that !:lince Reset is asynchronous, the
output pulse widths are narrow.
Figure 10. +2 Through + 10 Circuit

I

-<

C
CE
00

J

I

• •
.....

R

-

HG4017
01 •

r----~

I

R

-<

08 09
I

C
CE
00

.

~

9 DECODED
OUTPUTS

-

HC4017
01 •

• •

08 09
I

I

FIRST STAGE

-= ..

~

¥

8 DECODED
OUTPUTS

I

I

8 DECODED
OUTPUTS

..---..

r;?a

CLOCK

!

R
C
CE
HC4017
01 • • • 08 09
L.,
¥

INTERMEDIATE STAGES

N

-

--LAST STAGE

Figure 11 shows a technique for cascading the counters to extend the number of decoded output states. Decoded outputs
are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Figure 11. Counter Expansion

MOTOROLA

3-572

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4020A

14-5tage Binary Ripple
Counter
High-Performance Silicon-Gate CMOS

NSUFFIX
PLASTIC PACKAGE
CASE 64B-oB

The MC74C4020A is identical in pinout to the standard CMOS
MC14020B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master-slave flip-flops with 12 stages brought
out to pins. The output of each flip-flop feeds the next and the frequency at
each output is half of that of the preceding one. Reset is asynchronous and
active-high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the HC4020A
for some designs.

DSUFFIX
SOIC PACKAGE
CASE 751 8-05

DTSUFFIX
TSSOP PACKAGE
CASE 94BF-01

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 ~A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates

ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT

Plastic
SOIC
TSSOP

FUNCTION TABLI;
LOGIC DIAGRAM
9
7

Q1
Q4
Q5

Clock

Reset

~

L

Output State
No Charge

"""-

L

Advance to Next State

X

H

All Outputs Are Low

Q6

Clock

10
13
12
14
15

Q7
QS
Q9
Q10
Q11
Q12
Q13
Q14

Reset

VCC

Q11

Pin 16 ~ VCC
Pin8 ~GND

11

Q10

QS

Q9

Reset Clock

Q1

10/95

© Motorola, Inc. 1995

3-573

REV1

®

MOTOROLA

MC74HC4020A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Relerenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lin
lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500
450

mW

Tstg

Storage Temperature Range

-65to+150

°c

TL

.

Plastic DIPt
SOIC Packaget
TSSOP Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin orVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP Package: -6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature Range, All Package Types

tr,tf

Input Rise/Fall Time
(Figure 1)

VCC=2.0V
VCC=3.0V
VCC =4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0
0

1000
600
500
400

ns

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Condition

Guaranteed Limit

VCC
V

-55 to 25°C

::;85°C

::;125°C

Unit

VIH

Minimum High-Level Input Voltage

Vout = O.W or VCC-o.W
1I0uti ::;201lA

2.0
3.0
4.5
6.0

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

V

VIL

Maximum Low-Level Input Voltage

Vout = O.lVorVcC- O.lV
lIoutl ::; 2011A

2.0
3.0
4.5
6.0

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl ::; 2011A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

VOH

Parameter

Yin =VIH or VIL

VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL
lIoutl520llA
Yin = VIH or VIL

MOTOROLA

1I0uti ::; 2.4mA
lIoutl ::; 4.0mA
lIoutl ::; 5.2mA

3-574

lIout l
lIout l
1I0uti

2.4mA
4.0mA
5.2mA

V

High-Speed CMOS Logic Data
DL129-Rev6

MC?4HC4020A
DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol
lin
ICC

VCC
V

Guaranteed Limit
-55 to 25°C

~85°C

~125°C

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±D.l

±1.0

±1.0

fiA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
Iciut=OfiA

6.0

4

40

160

fiA

Parameter

Condition

NOTE: Information on typical parametric values can be found

In

Unit

Chapter 2.

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit

VCC
V

-55 to 25°C

~85°C

~125°C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
3.0
4.5
6.0

10
15
30
50

9.0
14
28
50

8.0
12
25
40

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Ql"
(Figures 1 and 4)

2.0
3.0
4.5
6.0

96
63
31
25

106
71
36
30

115
88
40
35

ns

tpHL

Maximum Propagation Delay, Reset 10 Any Q
(Figures 2 and 4)

2.0
3.0
4.5
6.0

45
30
30
26

52
36
35
32

65
40
40
35

ns

tpLH,
tpHL

Maximum Propagation Delay, Qn to Qn+l
(Figures 3 and 4)

2.0
3.0
4.5
6.0

69
40
17
14

80
45
21
15

90
50
28
22

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures l' and 4)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
15

110
36
22
19

ns

10

10

10

pF

Symbol

Cin

Parameter

Maximum Input Capacitance

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
" For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tp = [93.7 + 59.3 (n-l)] ns
VCC = 4.5 V: tp = [30.25 + 14.6 (n-l)] ns
VCC = 3.0 V: tp = [61.5 + 34.4 (n-l)] ns
VCC = 6.0 V: tp = [24.4 + 12 (n-l)] ns
Typical @ 25°C, Vec = 5.0 V
Power Dissipation Capacitance (Per Package)"

38

"Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-575

MOTOROLA

MC74HC4020A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Symbol

Vee
V

Parameter

Guaranteed Limit

-55 to 25'e

,,85'e

,,125'e

Unit

50
30
12
9

ns

Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)

2.0
3.0
4.5
6.0

30
20
5
4

40
25
8
6

tw

Minimum Pulse Width, Clock
(Figure 1)

2.0
3.0
4.5
6.0

70
40
15
13

80
45
19
16

90
50
24
20

ns

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
3.0
4.5
6.0

70
40
15
13

80
45
19
16

90
50
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
3.0
4.5
6.0

1000
800
500
400

1000
800
500
400

1000
800
500
400

ns

tree

tr,tf

NOTE: Information on tYPical parametnc values can be found in Chapter 2.

PIN DESCRIPTIONS
ronously resets the counter to its zero state, thus forcing all a
outputs low.

INPUTS
Clock (Pin 10)

Negative-edge triggering clock input. A high-ta-Iow transition on this input advances the state of the counter.

OUTPUTS

Reset (Pin 11)

Active-high outputs. Each an output divides the Clock
input frequency by 2N.

Q1, Q4-014 (Pins 9,7,5,4,6,13,12,14,15,1,2,3)

Active-high reset. A high level applied to this input asynch-

SWITCHING WAVEFORMS

/r--q-

...10=----, --- VCC

Clock __________

Clock

- O-'I,\.' - :::
5

tw

Reset _ _ _ _ ___'

tPHLj

01

...J/

50% \'-___

Any 0 _ _ _ _

Figure 1.

MOTOROLA

~

c sw.c: :
tree

GND

Figure 2.

3-576

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4020A
SWITCHING WAVEFORMS (continued)

On

1

TEST
POINT

I-

50%

OUTPUT

Vee

DEVICE
UNDER
TEST

·'-tP-LH--Ir---~...Lt·tPH~L---- GND

....Jf 50%

On+t _ _ _

'Includes aU probe and jig capacitance

Figure 3.

Figure 4. Test Circuit

01

06=Pin4
07= Pin6
OS=Pin 13

04

05

09=Pin12
010= Pin 14
011 = Pin 15

012

013

014

Vcc = Pin 16
GND= PinS

Figure 5. Expanded Logic Diagram

High-Speed CMOS Logic Data
DL129-Rev6

3-577

MOTOROLA

MC?4HC4020A
1 2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
Clock ~
Reset
___________________________________________________________________

-U- -U- -U- -U- -U- -U- -U- -U- -U- -U- -U- -U--U-

----,~

.....J1"""1- 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1"""1- 1 -1 -1 -1 -1 -1 -1 -1 -1 ~ 1 -1 -1 -1 -1 -1 -1 -1 ~ 1 -1 -1 -1 -1 -1 -1 ~ 1 -1 -1 -1 -1 -1 ~ 1 -1 -1 -1 -1 ~ 1 -1 -1 -1 ~ 1 -1 -1 ~11"""1-

Q4 _ _ _ _ _ _

05
06

07
08
09
010
012
013
014

Figure 6. Timing Diagram

APPLICATIONS INFORMATION
Time-Base Generator

feeds the HC4020A. Selecting outputs Os, 010, 011, and
012 causes a reset every 3600 clocks. The HC20 decodes
the counter outputs, produces a single (narrow) output pulse,
and resets the binary counter. The resulting output frequency
is 1.0 pulse/minute.

A 60Hz sinewave obtained through a 1.0 Megohm resistor
connected directly to a standard 120 Vac power line is
applied to the input of the MC54174HC14A, Schmitt-trigger
inverter.. The HC14A squares-up the input waveform and

VCC

..c:c,120Vac
60Hz

-!ri
.

<:20pF

I

-=-

-=-

VCC
1/6 of HC14A

HC4020A
Clock

05

13

010

1.0 Pulse/Minute
Output

011
012

Figure 7. Time-Base Generator.

MOTOROLA

3-578

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4024

7 -Stage Binary Ripple Counter
High-Performance Silicon-Gate CMOS
The MC74HC4024 is identical in pinout to the standard CMOS MC14024.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of 7 master-slave flip-flops. The output of each
flip-flop feeds the next and the frequency at each output is half that of the
preceding one. The state of the counter advances on the negative going
edge of the Clock input. Reset is asynchronous and active-high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the HC4024 for
some designs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A-03

ORDERING INFORMATION

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 /lA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 206 FETs or 51.5 Equivalent Gates

MC74HCXXXXN
MC74HCXXXXD

PIN ASSIGNMENT
CLOCK [ 1·

14

VCC

RESET [ 2

13

NC

07 [ 3

12

01

06 [ 4

11

02

LOGIC DIAGRAM
12
11

9
CLOCK
4
3

RESET

05 [ 5

10

NC

01

04 [ 6

9

03

02

GND [ 7

8

NC

03

NC = NO CONNECTION

04
5

05
06

FUNCTION TABLE

07

2

Clock

Reset

Output State

..r

L
L
H

No Change
Advance to Next State
All Outputs are Low

'-

PIN 14=VCC
PIN 7 =GND
PINS 8,10 AND 13 = NO CONNECTION

X

10195

© Motorola, Inc. 1995

Plastic
SOIC

3-579

REV 6

®

MOTOROLA

MC74HC4024
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500

,mW

Tstg

Storage Temperature

-65to+ 150

'c

TL

Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin orVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e,g., either GND or VCC).
Unused outputs must be left open.

'C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

·C

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

VCC
V

s 85'C

s 125'C

Unit

V,H

Minimum High-Level Input
Voltage

Vout = VCC - 0.1 V
lIoutl s 2Ol1A

2.0
4.5
6,0

1.5
3.15
4,2

1.5
3,15
4.2

1.5
3,15
4.2

V

V,L

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
lIoutl s 2Ol1A

2.0
4.5
6.0

0,3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin = V,H or V,L
lIoutl s 20 l1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3,84
5,34

3.70
5,20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Parameter

-55 to
25'C

Vin = V,H or V,L
VOL

Maximum Low-Level Output
Voltage

Vin = V,H or V,L
lIoutl s 2Ol1A
Vin = V,H or V,L

'in
ICC

lIoutl s 4.0 rnA
lIoutl s 5.2 rnA

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

±1,0

l1A

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
'out = 0 l1A

6.0

8

80

160

l1A

NOTE: Information on typical parametric values can be found

MOTOROLA

lIoutl s 4.0 rnA
lIoutl s 5.2 rnA

In

Chapter 2.

3-580

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4024
AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF. Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

5.4
27
32

4.4
22
26

3.6
18
21

MHz

tplH.
tpHl

Maximum Propagation Delay. Clock to Ql'
(Figures 1 and 4)

2.0
4.5
6.0

210
42
36

265
53
45

315
63
54

ns

tpHl

Maximum Propagation Delay. Reset to Any Q
(Figures 2 and 4)

2.0
4.5
6.0

210
42
36

265
53
45

315
63
54

ns

tPlH.
tpHl

Maximum Propagation Delay. QN to QN + 1
(Figures 3 and 4)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

trlH.
trHl

Maximum Output Transition Time. Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF. see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
'For TA = 25°C and Cl = 50 pF. typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tp = [205 + 100(N -1)] ns
VCC = 4.5 V: tp = [41 + 20(N -1)] ns
VCC = 6.0 V: tp = [35 + 17(N -1)] ns
Typical @ 25°e. Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

30

'Used to determine the no-load dynamic power consumption: PD

=CPD VCC 2f + ICC VCC. For load considerations. see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

trec

Minimum Recovery Time. Reset Inactive to Clock
(Figure 2)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

tw

Minimum Pulse Width. Clock
(Figure 1)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tw

Minimum Pulse Width. Reset
(Figure 2)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

tr.tf

Parameter

NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS logic Data
DL129-Rev6

3-581

MOTOROLA

MC74HC4024
PIN DESCRIPTIONS
INPUTS

input resets the counter to its zero state, thus forcing all 0
outputs low.

Clock (Pin 1)
Negative edge triggering clock input. A High to low transition of this input advances the state of the counter.

OUTPUTS

Reset (Pin 2)

Active-high outputs. Each ON output divides the Clock input frequency by 2N.

Q1-Q7 (Pins 12, 11, 9, 6, 5, 4, 3)

Active high asynchronous reset. A high level applied to this

SWITCHING WAVEFORMS

-VCC

RESET

'-----GND

CLOCK

a
01

50% c ' VCC
GND

CLOCK

Figure 1.

Figure 2.

TEST POINT
OUTPUT

~
ON
ON+l

5~ '.tP-LH-. r=--j,PHl, r
50%/,

DEVICE
UNDER
TEST

VCC

GH'

'-

• Includes aU probe and jig capacitance

Figure 3.

MOTOROLA

Figure 4. Test Circuit

3-582

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4024
TIMING DIAGRAM

1

2

3

4

8

16

32

64

128

--u- --u- --u---u---u-

CLOCK~
RESET---,L_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

01~ L-- L-- L-- L-- L--

0 2 - - - - - . r - - L L-- L-- L-- L-- L-03~ L-- L-- L-- L--

I L - L-- L-- L-_ _ _ _ _ _ _----JIL- L-- L-06 _______________________1 L 04

~

IL-

07

EXPANDED LOGIC DIAGRAM

High-Speed CMOS Logic Data
DL129-Rev6

3-583

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC4040A

12-5tage Binary Ripple
Counter
High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 620-10

The MC54f74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master-slave flip-flops. The output of each
flip-flop feeds the next and the frequency at each output is half of that of
the preceding one. The state counter advances on the negative-going
edge of the Clock input. Reset is asynchronous and active-high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the
HC4040A for some designs.
•
•
•
•
•
•
•

NSUFFIX
PLASTIC PACKAGE
CASE 64S-oS

DSUFFIX
SOIC PACKAGE
CASE 7516-05

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 jlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 398 FETs or 99.5 Equivalent Gates

DTSUFFIX
TSSOP PACKAGE
CASE 948F-ol

ORDERING INFORMATION

[3]

MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT

LOGIC DIAGRAM
9
7
6

Clock

Reset

01
02
03
04
05
2
06
4
07
13
08
12
09
14
010
15
011
012

10

11

FUNCTION TABLE
Clock

Reset

~

L

No Charge

L

Advance to Next State
All Outputs Are Low

-.......
X

H

Output State

Pin 16= VCC
Pin8=GND

VCC

011

010

08

09

012

06

05

07

04

Reset

01

02

10195

© Motorola, Inc. 1995

Ceramic
Plastic
SOIC
TSSOP

3-584

REV 1

®

MOTOROLA

MC54174HC4040A
MAXIMUM RATINGS·
Symbol
VCC
Yin
Vout

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

-65to+150

°c

Tstg
TL

Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND " (VinorVout) " VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature Range, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=3.0V
VCC=4.5V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0

1000
600
500
400

ns

0
0

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Condition

Guaranteed Limit

VCC
V

-55 to 25°C

";85°C

,,;125'C

Unit

VIH

Minimum High-Level Input Voltage

Vout = O.lVor VCC -O.lV
1I0uti ";20j.lA

2.0
3.0
4.5
6.0

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

V

VIL

Maximum Low-Level Input Voltage

Vout = O.lVor VCC -O.lV
1I0uti ";20j.lA

2.0
3.0
4.5
6.0

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti ,,; 20j.lA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

VOH

Parameter

Yin =VIH or VIL

VOL

Maximum Low-Level Output
Voltage

High-Speed CMOS Logic Data
DL129-Rev6

Yin = VIH or VIL
lIoutl ";20j.lA

3-585

1I0uti
1I0uti
1I0uti

2.4mA
4.0mA
5.2mA

V

MOTOROLA

MC54174HC4040A
DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol

Parameter

Condition
Vin = VIH or VIL

lin
ICC

lIoutl
"out l
lIout l

2.4mA
4.0mA
5.2mA

Guaranteed Limit

VCC
V

-55 to 25°C

$85°C

$125°C

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Unit

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±O.1

±1.0

±1.0

j.lA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = OJ.lA

6.0

4

40

160

j.lA

NOTE: Information on typical parametric values can be found in Chapter 2.

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

Guaranteed Limit

VCC
V

-55 to 25°C

:S85°C

$125°C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
3.0
4.5
6.0

10
15
30
50

9.0
14
28
45

B.O
12
25
40

MHz

tpLH,
tpHL

Maximum Propagation Delay, Clock to Ql"
(Figures 1 and 4)

2.0
3.0
4.5
6.0

96
63
31
25

106
71
36
30

115
B8
40
35

ns

tpHL

Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)

2.0
3.0
4.5
6.0

45
30
30
26

52
36
35
32

65
40
40

ns

tpLH,
tpHL

Maximum Propagation Delay, Qn to Qn+ 1
(Figures 3 and 4)

2.0
3.0
4.5
6.0

69
40
17
14

BO
45
21
15

90

tTLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
15

110
36
22
19

ns

10

10

10

pF

Cin

Maximum Input Capacitance

35
ns

50
2B
22

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
" For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
Vce = 2.0 V: tp = [93.7 + 59.3 (n-l)J ns
VCC = 4.5 V: tp = [30.25 + 14.6 (n-l)J ns
Vec = 3.0 V: tp = [61.5 + 34.4 (n-l)J ns
VCC = 6.0V: tp = [24.4 + 12 (n-l)J ns
Typical @ 25°C. VCC
Power Dissipation Capacitance (Per Package)"

=5.0 V

31

"Used to determine the no-load dynamic power consumption: Po = CPO VCC 2f + ICC VCC. For load considerations. see Chapter 2.

MOTOROLA

3-586

High-Speed CMOS Logic Data
DL129- Rev 6

MC54174HC4040A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit

Vee
V

-55 to 25°e

,,05°e

,,125°e

Unit

Minimum Recovery lime. Reset Inactive to Clock
(Figure 2)

2.0
3.0
4.5
6.0

30
20
5
4

40
25
8
6

50
30
12
9

ns

tw

Minimum Pulse Width. Clock
(Figure 1)

2.0
3.0
4.5
6.0

70
40
15
13

80
45
19
16

90
50
24
20

ns

tw

Minimum Pulse Width. Reset
(Figure 2)

2.0
3.0
4.5
6.0

70
40
15
13

80
45
19
16

90
50
24
20

ns

1000
800
500
400

1000
800
500
400

1000
800
500
400

ns

Parameter

Symbol
tree

tr.tf

Maximum Input Rise and Fall limes
(Figure 1)

2.0
3.0
4.5
6.0

NOTE: Information on typical parametric values can be found

In

Chapter 2.

PIN DESCRIPTIONS
ronously resets the counter to its zero state. thus forcing all 0
outputs low.

INPUTS

Clock (Pin 10)
Negative-edge triggering clock input. A high-ta-Iow transition on this input advances the state of the counter.

OUTPUTS

Reset (Pin 11)

Active-high outputs. Each On output divides the Clock
input frequency by 2N.

Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4,13,12,14,15,1)

Active-high reset. A high level applied to this input asynch-

SWITCHING WAVEFORMS

....J/

Clock _ _ _ _ _ _ _

--"""---.----VCC
GND

Reset

-----Ql

Any Q

Figure 1.

High-Speed CMOS Logic Data'
DL129-Rev6

50% \ . - VCC

.t j 50%L

Clock

~~ .~::

tPHL

/

GND

50% \'--_ __

Figure 2.

3-587

MOTOROLA

MC54174HC4040A
SWITCHING WAVEFORMS (continued)

On

1

TEST
POINT

f

SO%

OUTPUT

Vcc

DEVICE
UNDER
TEST

''-tP-LH-t;:---~-Lt'tPH~L---- GND

-'t

On+t _ _ _

SO%
-Includes all probe and jig capacitance

Figure 3.

Figure 4. Test Circuit

Ot

04=PinS
OS=Pin3
06=Pin2

02

03

Q7=Pin4
08= Pin 13
09= Pin 12

Oto

011

012

VCC= Pin 16
GND = Pin8

Figure 5. Expanded Logic Diagram

MOTOROLA

3-588

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4040A
1 2
4
8
16
32
64
128
256
512
1024
2048
4096
Clock ~ -U- -U- -U- -U- -U- -U- -U- -U- -U- -UReset

L

-----,L..___________________________

Q1~ L - L - L - L - L - L - L - L - L - L - L

I L -L - L - L - L - L - L - L - L - L - L
s- L - L - L - L - L - L - L - L - '--.: L
_s-L- L-L- L- L- L-L-L- L
_ _ s-L-L-L- L- L-L-L- L
_ _ _ s-L- L- L- L-L-L- L
________ s-L- L- L- L- L- L
__________ s-L- L- L- L- L
_ _ _ _ _ _ _ _ _ _ _ _ _ _ s- L - L - L - L
_________________ s - L - L - L
_________________ s - L - L
__________________ s - L

Q2

Q3 _ _ _ _
Q4
Q5
Q6
Q7

Q8
Q9
Q10
Q11
Q12

Figure 6. Timing Diagram

APPLICATIONS INFORMATION
Time-Base Generator

feeds the HC4040A. Selecting outputs OS, 010, 011, and
012 causes a reset every 3600 clocks. The HC20 decodes
the counter outputs, produces a single (narrow) output pulse,
and resets the binary counter. The resulting output frequency
is 1.0 pulse/minute.

A 60Hz sinewave obtained through a 1.0 Megohm resistor
connected directly to a standard 120 Vac power line is
applied to the input of the MC54/74HC14A, Schmitt-trigger
inverter. The HC14A squares-up the input waveform and

Vee

HC4040A

100M

13

Clock

~
120Vac
60Hz

Vee

Q5
Q10

-=-

-=-

6

1.0 Pulse/Minute
Output

Q11

Figure 7. Time-Base Generator

High-Speed CMOS Logic Data
DL129-Rev6

3-589

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4046A

Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The MC574HC4046A is similar in function to the MC14046 Metal gate
CMOS device. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC4046A phase-locked loop contains three phase comparators, a
voltage-controlled oscillator (VCO) and unity gain op-amp DEMOUT The
comparators have two common signal inputs, COMPIN, and SIGIN. Input
SIGIN and COMPIN can be used directly coupled to large voltage signals, or
indirectly coupled (with a series capacitor to small voltage signals). The
self-bias circuit adjusts small voltage signals in the linear region of the
amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error
signal PC lOUT and maintains 90 degrees phase shift at the center
frequency between SIGIN and COMPIN signals (both at 50% duty cycle).
Phase comparator 2 (with leading-edge sensing logic) provides digital error
signals PC20UT and PCPOUT and maintains a 0 degree phase shift
between SIGIN and COMPIN signals (duty cycle is immaterial). The linear
VCO produ.ces an output signal VCOOUT whose frequency is determined by
the voltage of input VCOIN signal and the capacitor and resistors connected
to pins C1A, Cl B, Rl and R2. The unity gain op-amp output DEMOUT with
an external resistor is used where the VCOIN signal is needed but no loading
can be tolerated. The inhibit input, when high, disables the VCO and all
op-amps to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding,
data synchronization and conditioning, voltage-to-frequency conversion
and motor speed control.
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Low Power Consumption Characteristic of CMOS Devices
Operating Speeds Similar to LSTTL
Wide Operating Voltage Range: 3.0 to 6.0 V

•
•

Low Input Current: 1.0 !!A Maximum (except SIGIN and COMPIN)
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Low Quiescent Current: 80 IlA Maximum (VCO disabled)
High Noise Immunity Characteristic of CMOS Devices
Diode Protection on all Inputs
Chip Complexity: 279 FETs or 70 Equivalent Gates

•
•
•
•

Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Symbol
PCPOUT
PC10UT
COM PIN
VCOOUT
INH
CIA
CIB
GND
VCOIN
DEMOUT
Rl
R2
PC20UT
SIGIN
PC30UT
VCC

N SUFFIX
PLASTIC PACKAGE
CASE 648-08

DSUFFIX
SOIC PACKAGE
CASE 751 B-05
ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD

PIN ASSIGNMENT

1995

~

PCPout [ 1-

16

PClout [ 2

15 ~ PC30ut

COM Pin [ 3

14

VCOout [ 4

13

INH [ 5

~

VCC

SIGin

~ PC20ut
12 ~ R2

CIA [ 6

11 ~ Rl

CIS

7

10

GND

8

9

~
~

DEMout
VCOin

Name and Function
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCOOutput
Inhibit Input
Capacitor Cl Connection A
Capacitor Cl Connection B
Ground (0 V) VSS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage

10/95

© Motorola, tnc.

Plastic
SOIC

3-590

REV6

®

MOTOROLA

MC?4HC4046A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

- 0.5 to + 7.0

V

Vin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500

mW

-65 to + 150

'C

lin

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP and SOIC Packaget

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'C
260

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol

VCC

Parameter
DC Supply Voltage (Referenced to GND)

Min

Max

Unit

3.0

6.0

V

6.0

V

VCC

DC Supply Voltage (Referenced to GND) NON-VCO

2.0

Yin, Vout

DC Input Voltage, Output Voltage (Referenced to GND)

0

VCC

V

-55

+ 125

'C

0
0
0

1000
500
400

ns

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Pin 5)

VCC=2.0V
VCC =4.5 V
VCC = 6.0 V

[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
Volts

-55to
25'C

S:S5'C

s: 125'C

Unit

VIH

Minimum High-Level Input
Voltage DC Coupled
SIGIN, COMPIN

Vou t=O.l VorVcc-O.l V
lIoutl '" 20 !!A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage DC Coupled
SIGIN, COM PIN

Vou t=O.l VorVcc-O.l V
lIoutl '" 20 itA

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

Minimum High-Level
Output Voltage
PCPOUT, PCnOUT

Yin =VIH or VIL
lIoutl ",20 itA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

VOH

Yin =VIH or VIL
lIoutl '" 4.0 rnA
lIoutl '" 5.2 rnA

(conllnued)

High-Speed CMOS Logic Data
DL129-Rev6

3-591

MOTOROLA

MC?4HC4046A
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS - continued (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

Parameter

Test Conditions

Maximum Low-Level
Output Voltage Qa-Qh
PCPOUT, PCnOUT

VCC
Volts

-55to
25°C

S85°C

S125°C

Unit

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Vout=O.1 VorVCC-O.l V
1I0uti S 20 IlA
Vin = VIH or VIL
1I0uti S 4.0 mA
1I0uti S 5.2 mA

Maximum Input Leakage Current
SIGIN, COMPIN

Vin = VCC or GND

2.0
3.0
4.5
6.0

±3.0
±7.0
±18.0
±30.0

±4.0
±9.0
±23.0
±3B.0

±5.0
±11.0
±27.0
±45.0

IlA

IOZ

Maximum Three-State
Leakage Current
PC20UT

Output in High-Impedance State
Vin = VIH or VIL
Vout = VCC or GND

6.0

±0.5

±5.0

±10

IlA

ICC

Maximum Quiescent Supply
Current (per Package)
(VCO disabled)
Pins 3, 5 and 14 at VCC
Pin 9 at GND; Input Leakage at
Pins 3 and 14 to be excluded

Vin = VCC or GND
1I0uti = 0 IlA

6.0

4.0

40

160

IlA

S125°C

Unit

lin

NOTE: Information on tYPical parametric values can be found

In

Chapter 2.

[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol

Parameter

Guaranteed Limit

VCC
Volts

-55 to 25°C

s85°C

tpLH,
tpHL

Maximum Propagation Delay, SIGIN/COMPIN to PC10UT
(Figure 1)

2.0
4.5
6.0

175
35
30

220
44
37

265
53 .
45

ns

tpLH,
tpHL

Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT
(Figure 1)

2.0
4.5
6.0

340
68
58

425
85
72

510
102
87

ns

tpLH,
tpHL

Maximum Propagation Delay, SIGIN/COMPIN to PC30UT
(Figure 1)

2.0
4.5
6.0

270
54
46

340
68
58

405
81
69

ns

tPLZ,
tpHZ

Maximum Propagation Delay, SIGIN/COMPIN Output
Disable Time to PC20UT (Figures 2 and 3)

2.0
4.5
6.0

200
40
34

250
50
43

300
60
51

ns

tpZH,
tpZL

Maximum Propagation Delay, SIGIN/COMPIN Output
Enable TIme to PC20UT (Figures 2 and 3)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

trLH,
trHL

Maximum Output Transition TIme
(Figure 1)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

MOTOROLA

3-592

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4046A
[VCO Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
Volts

-55to
25°C

$ 85°C

$ 125°C

Unit

VIH

Minimum High-Level
Input Voltage
INH

Vou t=0.1 VorVCC-0.1 V
lIoutl $ 20 IJA

3.0
4.5
6.0

2.1
3.15
4.2

2.1
3.15
4.2

2.1
3.15
4.2

V

VIL

Maximum Low-Level
Input Voltage
INH

Vou t=0.1 VorVCC-0.1 V
Iioutl $ 20 IJA

3.0
4.5
6.0

0.90
1.35
1.8

0.9
1.35
1.8

0.9
1.35
1.8

V

VOH

Minimum High-Level
Output Voltage
VCOOUT

Yin = VIH or VIL
Iioutl $ 20 IJA

3.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

3.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL
lIout' $ 4.0 mA
lIoutl $ 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Yin = VCC or GND

6.0

0.1

1.0

1.0

Min

Max

Min

Max

Min

Max

INH=VIL

3.0
4.5
6.0

0.1
0.1
0.1

1.0
2.5
4.0

0.1
0.1
0.1

1.0
2.5
4.0

0.1
0.1
0.1

1.0
2.5
4.0

V

3.0
4.5
6.0

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

kQ

3.0
4.5
6.0

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

3.0
4.5
6.0

40
40
40

No
Limit

Yin = VIH or VIL
lIoutl $ 4.0 mA
Iioutl $ 5.2 mA
VOL

lin

Maximum Low-Level
Output Voltage
VCOOUT

Maximum Input
Leakage Current
INH. VCOIN

Operating Voltage Range at
VVCOIN
VCOIN over the range
specified for R1; For linearity
see Fig. 15A. Parallel value of
R1 and R2 should be> 2.7 kQ
R1

Vout=0.1 VorVcc-0.1 V
lIout' $20 IlA

Resistor Range

R2

C1

Capacitor Range

High-Speed CMOS Logic Data
DL129-Rev6

3-593

V

IJA

pF

MOTOROLA

MC?4HC4046A
[VCO Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF. Input tr = tf = 6.0 ns)
Guaranteed Limit
:s;85D C

-55 to 25 C
D

Symbol

VCC
Volts

Parameter

Min

Max

Min

Max

:s; 125D C
Min

Max

Unit

!;.fIT

Frequency Stability with
Temperature Changes
(Figure 13A. B. C)

3.0
4.5
6.0

fo

VCO Center Frequency
(Duty Factor = 50%)
(Figure 14A. B, C. D)

3.0
4.5
6.0

8NCO

VCO Frequency Linearity

3.0
4.5
6.0

See Figures 15A. B. C

%

avco

Duty Factor at VCOOUT

3.0
4.5
6.0

Typical 50%

%

%/K

3
11
13

MHz

[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit

Symbol
RS

VOFF

RD

Parameter

Test Conditions

VCC
Volts

-55to25 D C
Min

Max

50
50
50

300
300
300

:S;85D C
Min

Max

:s; 125D C
Min

Max

Unit

Resistor Range

At RS > 300 kQ the
Leakage Current can
Influence VDEMOUT

3.0
4.5
6.0

Oflset Voltage
VCOIN to VDEMOUT

Vi = WCOIN = 1/2 VCC;
Values taken over RS
Range.

3.0
4.5
6.0

See Figure 12

mV

Dynamic Output
Resistance at DEMOUT

VDEMOUT = 1/2 VCC

3.0
4.5
6.0

Typical25Q

Q

MOTOROLA

3-594

kQ

High-Speed CMOS Logic Data
DL129-Rev6

MC?4HC4046A
SWITCHING WAVEFORMS

--VCC
,..----VCC
'--------GND
--VCC

-GND

-GND

PCPOUT, PC10UT
PC30UT
OUTPUTS

--VOH
HIGH
IMPEDANCE

'---- -

trLH

Figure 1.

Figure 2.

--VCC
SIGIN
INPUT

TEST POINT
--GND
OUTPUT
--VCC

COMPIN
INPUT

DEVICE
UNDER
TEST

50"10
-1PLZ-

PC20UT
OUTPUT

-

GND

- - HIGH
IMPEDANCE
'--_ _ _ _--' 10"10

'INCLUDES ALL PROBE AND JIG CAPACITANCE
-

VOL

Figure 4. Test Circuit

Figure 3.

High-Speed CMOS Logic Data

DL129-Rev6

3-595

MOTOROLA

MC?4HC4046A
the capacitor. Once the voltage across the capacitor charges
up to Vref of the comparators, the oscillator logic flips the capaCitor which causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then taken to VCO output (Pin 4).
The input to the VCO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the VCO input
accessible without degrading the loop performance, the VCO
input voltage is buffered through a unity gain Op-amp to Demod Output. This Op-amp can drive loads of 50K ohms or
more and provides no loading effects to the VCO input voltage (see Figure 12).
An inhibit input is provided to allow disabling of the VCO
and all Op-amps (see Figure 5). This is useful if the internal
VCO is not being used. A logic high on inhibit disables the
VCO and all Op-amps, minimizing standby power consumption.
'

DETAILED CIRCUIT DESCRIPTION
Voltage Controlled Oscillator/Demodulator Output
The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and Capacitor C1
are selected to determine the center frequency of the VCO
(see typical performance curves Figure 14). R2 can be used
to set the offset frequency with 0 volts at VCO input. For example, if R2 is decreased, the offset frequency is increased.
If R2 is omitted the VCO range is from 0 Hz. The effect of R2
is shown in Figure 24, typical performance curves. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/Hz) is decreased. Thus, for' a
narrow lock range, large swings on the VCO input will cause
less frequency variation.
Internally, the resistors set a current in a current mirror, as
shown in Figure 5. The mirrored current drives one side of

CURRENT
MIRROR
11 +12= 13
, VCOIN

Figure 5. Logie Diagram for VCO

MOTOROLA

3-596

High-Speed CMOS Logic Data

DL129-Rev6

MC74HC4046A
The output of the VCO is a standard high speed CMOS
output with an equivalent LS-TTL fan out of 10. The VCO
output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or
feed external prescalers (counters) to enable frequency synthesis.

COMPIN. The SIGIN and COMPIN have a special DC bias
network that enables AC coupling of input signals. If the signals are not AC coupled, standard 54HC174HC input levels
are required. Both input structures are shown in Figure 6.
The outputs of these comparators are essentially standard
54HC174HC outputs (comparator 2 is TRI-STATEABLE). In
normal operation VCC and ground voltage levels are fed to
the loop filter. This differs from some phase detectors which
supply a current to the loop filter and should be considered in
the design. (The MC14046 also provides a voltage).

Phase Comparators
All three phase comparators have two inputs, SIGIN and

Figure 6. Logic Diagram for Phase Comparators

VCO input voltage must increase and the phase difference
between COMPIN and SIGIN will increase. At an input frequency equal to fmin, the VCO input is at 0 V. This requires
the phase detector output to be grounded; hence, the two input signals must be in phase. When the input frequency is
f max , the VCO input must be VCC and the phase detector inputs must be 180 degrees out of phase.

Phase Comparator 1
This comparator is a simple XOR gate similar to the
54174HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 7. The output of the phase
detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto
if initially out of lock is defined as the capture range. The capture range for phase detector 1 is dependent on the loop filter
design. The capture range can be as large as the lock range,
which is equal to the VCO frequency range.
To see how the detector operates, refer to Figure 7. When
two square wave signals are applied to this comparator, an
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the
phase difference increases, the output duty cycle increases
and the voltage after the loop filter increases. In order to
achieve lock when the PLL input frequency increases, the

High-Speed CMOS Logic Data
DL129-Rev6

PC10UT
VCOIN
--GND

Figure 7. Typical Waveforms for PLL Using
Phase Comparator 1

3-597

MOTOROLA

MC74HC4046A
The XOR is more susceptible to locking onto harmonics of
the SIGIN than the digital phase detector 2. For instance, a
signal 2 times the veo frequency results in the same output
duty cycle as a signal equal to the veo frequency. The difference is that the output frequency of the 2f example is twice
that of the other example. The loop filter and veo range
should be designed to prevent locking on to harmonics.

Phase comparator 2 is more susceptible to noise, causing
the PLL to unlock. If a noise pulse is seen on the SIGIN, the
comparator treats it as another positive edge of the SIGIN
and will cause the output to go high until the VCO leading
edge is seen, potentially for an entire SIGIN period. This
would cause the VCO to speed up during that time. When using PC1, the output of that phase detector would be disturbed
for only the short duration of the noise spike and would cause
less upset.

Phase Comparator 2
This detector is a digital memory network. It consists of
four flip-flops and some gating logic, a three state output and
a phase pulse output as shown in Figure 6. This comparator
acts only on the positive edges of the input signals and is independent of duty cycle.
Phase comparator 2 operates in such a way as to force the
PLL into lock with 0 phase difference between the veo output and the signal input positive waveform edges. Figure 8
shows some typical loop waveforms. First assume that SIGIN
is leading the eOMPIN. This means that the veo's frequency must be increased to bring its leading edge into proper
phase alignment. Thus the phase detector 2 output is set
high. This will cause the loop filter to charge up the veo input, increasing the veo frequency. Once the leading edge of
the COM PIN is detected, the output goes TRI-STATE holding the veo input at the loop filter voltage. If the veo still
lags the SIGIN then the phase detector will again charge up
the veo input for the time between the leading edges of both
waveforms.
If the veo leads the SIGIN then when the leading edge of
the veo is seen; the output of the phase comparator goes
low. This discharges the loop filter until the leading edge of
the SIGIN is detected at which time the output disables itself
again. This has the effect of slowing down the veo to again
make the rising edges of both waveforms coincidental.
When the PLL is out of lock, the veo will be running either
slower or faster than the SIGIN. If it is running slower the
phase detector will see more SIGIN rising edges and so the
output of the phase comparator will be high a majority of the
time, raising the veo's frequency. Conversely, if the veo is
running faster than the SIGIN, the output of the detector will
be low most of the time and the veo's output frequency will
be decreased.
As one can see, when the PLL is locked, the output of
phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is
TRI-STATED, the PCP output is high. This output can be
used to determine when the PLL is in the locked condition.
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase difference
between the COM PIN and the SIGIN. The lock range of the
PLL is the same as the capture range. Minimal power was
consumed in the loop filter since in lock the detector output is
a high impedance. When no SIGIN is present, the detector
will see only VCO leading edges, so the comparator output
will stay low, forcing the VCO to fmin.

MOTOROLA

Phase Comparator 3
This is a positive edge-triggered sequential phase detector using an RS flip-flop as shown in Figure 6. When the PLL
is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN
are not important. It has some similar characteristics to the
edge sensitive comparator. To see how this detector works,
assume input pulses are applied to the SIGIN and COMPIN'S
as shown in Figure 9. When the SIGIN leads the COM PIN,
the flop is set. This will charge the loop filter and cause the
veo to speed up, bringing the comparator into phase with
theSIGIN. The phase angle between SIGIN and COM PIN varies from 0 0 to 360 0 and is 1800 at f o . The voltage swing for
PC3 is greater than for PC2 but consequently has more ripple
in the signal to the VCO. When no SIGIN is present the VCO
will be forced to f max as opposed to fmin when PC2 is used.
The operating characteristics of all three phase comparators should be compared to the requirements of the system
design and the appropriate one should be used.

SIGIN~--JL---~

COMPI~--~ __ SL_vcc
SL -

PC20UT

Z - - ---u--

HIGH IMPEDANCE OFF-8TATE VCOIN J
PCPOUT

GND

'---

-Ur-----------,U--

Figure 8. Typical Waveforms for PLL Using
Phase Comparator 2

PC30UT
VCOIN

--VCC
--GND

Figure 9. Typical Waveform for PLL Using
Phase Comparator 3

3-591\

High-Speed CMOS Logic Data
DL129-Rev6

MC?4HC4046A

CC=31,OV

....

oc

-

:--

o
112 VCC-1.0 V

--

/ V
I ~

/

,

/

-

'CC=4. 5V

-

...-i

........ VCC=6.OV
/
-.... r'\.\ // "
r-rl
~V

......... 1\

112VCC
VI (V)

I---

...- I--?

,.....

....... r--

Figure 10. Input Resistance at SIGIN. COMPIN with
",VI 1.0 V at Self-Bias Point

!. '/
IP'

- -

V

-4.0
112VCC - 500 mV

1/2 VCC+1.0 V

..- VCc=3.0V
,.....1

V"

./

'\

VCC=4. 5V

/"

/

"
r-..

400

4.0

./

'\

s7,"

VCC=~

1

800

112 VCC + 500 mV

112VCC
VI (V)

Figure 11. Input Current at SIGIN. COMPIN with
",VI 500 mV at Self-Bias Point

=

=

DE MOD OUT

15
6.0

Rl=3.0 k!..l
10

>-

!::i

./

V
oV

V

./

V

VCc;:=6.0 YRS=3 OOk
VC?=6.0 VRs=5 Ok

VCC=4.5 VRS=300 k
VC9=4.5 'RS=50 k

1i5

~
'"

0

Rl=I OO k!..l

a-5.O

Rl=300 k!..l

~
zw

3.0
VCOIN(V)

~

1i5

R1 13.0k? I
. / Rl=300 k!..l
./
Rl~100 J!..l

10

././. ::;.--'

5.0

'"

w
=> -5.0
0
w
a:

"-

-10
-15
-100

.--:::: P"

....
/'
-50

C

~
~

z
w
=>
0
w
a:

/

-

"-

VCC =4.5 V
fl = 100 p~; R2 T~; ~VCOIIN = 1~2 vcC( -

0
50
100
AMBIENT TEMPERATURE ('C)

150

10

'"
><->

/

8.0
6.0
4.0
0
-2.0
-4.0
-1).0
-10
-100

150

./

2.0

-8.0

Figure 13B. Frequency Stability versus Ambient
Temperature: VCC 4.5 V

~

~

/

.A ~

Rl=3. ok!..l
Rl=300k!..l
1
Rl=l 00k!..l

.d~

k::::: P""./
V

"

/

-50

VCC=6.0V
Cl = 100 pF; R2 =~; VVCOIN=112 VCC
0
50
100
AMBIENT TEMPERATURE ('C)

150

Figure 13C. Frequency Stability versus Ambient
Temperature: VCC 6.0 V

=

=

High-Speed CMOS Logic Data
DL129-Rev6

0
50
100
AMBIENTTEMPERATURE ('C)

=

1i5

~

>z<->

-50

1100 r R2i~; iVCOlrl13iCC
VCC=3. V

Cl

Figure 13A. Frequency Stability versus Ambient
Temperature: VCC 3.0 V

::i

~ V"

~

9~ -

6.0

15
~

l

Rl=r Ok

Figure 12. Offset Voltage at Demodulator Output as
a Function of VCOIN and RS

--'

/

V

-10

~ P"'"

Rl=l 00 k!..l
Rl=3do k!..l

/

./

-15
-100

o

~

w

a:

"-

vcc=.~=3do k
VCC=3.0 V S=50 k

./

f....-::

V ...... ~

5.0

3-599

MOTOROLA

MC74HC4046A
23
21
19

--

I

70

so

Vee=6.0V

J

i

./

IL

/
h

13

I ..".

II

Vee = 3.0V

II,

RI = 3.0 kn
el =39 pF

7.0 0

0.5

1.0

II
./
'/ ./ .......-

1.5

2.0

2.5

3.0

3.5

V

i""'"

~ i""""

10

RI =3.0kn el =0.1 ~F -

~

".
o0

4.0

0.5

1.0

1.5

VVeOIN(V)

Figure 14A. veo Frequency (fveo) as a Function
of the veo Input VoHage (VVeOIN)
2.0

1 1 1
Vee=4.5V

V

1./
Vee=3.0V

~

o

~

)
o

V

~

0.5

~

1.0

/I/~
~
~~

J11

Vee = S.O v

¥

~

4.0

8
.?

S.OV
3.0V

0

i"-r-.
i"-r-.

I
I- 4.5V

<]

-2.0

0
10

Vee=3.0 V

0.6

""

l/ ./

/. ~ V
:;.~

""

I

I

~
o~

o

0.5

~

V

~~

0.1
4.5

",. IL

1/

I

R1= 300kQ
el =0.1 ~F
1.0

1.5

2.0
2.5
3.0
VveOIN (V)

3.5

4.0

4.5

Figure 140. veo Frequency (fveo) as a Function
of the veo Input Voltage (VVeOIN)

~ ......

I-- I-

...... .....

~

......

I- --

~

el = 39 pF

R2=~;

i""""

;;

;::

fV"
I-'"

- r- - r- -~ ,; i""'"
~
F = .;;F - ... ~
r-

~

-1.0 I-SY
3.0V

4.0

1.0

4.5V
1.0

Vee:"4.5 V "

0.2

Jl ~ ~F

Vee=

0.8

0.3

Figure 14e. veo Frequency (tyeo) as a Function
of the veo Input Voltage (VVeOIN)
2.0

I

8 0.5
..?0.4

3.5

3.5

Vee=6.0~

0.9

0.7

3.0

3.0

1.0

.............. 1/
",/"

2.0
2.5
VveOIN(V)

2.0
2.5
VveOIN(V)

Figure 148. veo Frequency (fveo) as a Function
of the veo Input Voltage (VVeOIN)

RI = 300 kn
el =39pF
1.5

./

./

v

/

20

~

1/

I

8

Vee=S.O,?

./

I

..? 30

I

,/

Vee = 3.0

~40

(/

I

Vee=4.5V-

L 1 L

50

Vee=4.5V- r-

I

I I I
I I L

I(

AV =0.5 V

I I I 1111

./

7

~

MIN

101
RI (kn)

;A

1/2 Vee

MAX

AV = 0.5 V OVER THE Vee RANGE:
FOR veo LINEARITY
fo' = (fl +f2)/2
LINEARITY = (fO' - fO) I fO') x 100%

Figure 15A. Frequency Linearity versus
R1, e1 and Vee

MOTOROLA

Figure 158. Definition of veo Frequency Linearity

3-600

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4046A
106 "'--C-L·-SO-P-F;R-2-.00-;V-V-CO-IN-.1-12-VC-C-FO-R-VC-C-·4-.S-V~-O-6-.0-V;--'

106

CL • 50 pF; R1 .00; VVCOIN. 0 V; Tamb. 25'C

VVCOIN .1/3 VCC FOR VCC· 3.0 V; Tamb· 25'C

105

§:

20

'"
It

I

104

VCC·4.5V,C1.40pF
VCC·4.5V.C1.1.0~F

VCC. 3.0 V, C1.40 pF

VCC·3.0V:C1.1.0~F

103
101

100

Rl (kil)

R2 (kil)

Figure 16. Power Dissipation versus R1

102

103

Figure 17. Power Dissipation versus R2

108

103~--------------~

R1 • R2. 00; Tamb' 25'C

107.
106
"N
;;S
0

VCC·6.0V

u

105

VCC·
6.0V
4.5V
3.0V
6.0V
4.5V
3.0 V
6.0 V
4.5 V
3.0 V

INH· GND; Tamb. 25'C; R2. 00; VveOIN ·1/3 VCC

.?
VCC.4.5 V

104
Vec·3.0V

103

100+-_ _ _ _ _ _~~------~
101
102
RS(kil)

102

107
106

~105

J§

VCC·
6.0V
4.5 V
3.0V
6.0 V
4.5 V
3.0 V
6.0 V
4.5 V
3.0 V

103
Cl (pF)

108

R1 .00; VVCOIN .112 VCC FOR VCC. 4.5 VAND 6.0 v;
VveOIN .113 Vce FOR Vee. 3 0 V; INH. GND; Tamb. 25'e

VCC =4.5 V; R2= ~

107

"N
;;S

104

104

Figure 19. VCO Center Frequency versus C1

Figure 1B. DC Power Dissipation of
Demodulator versus RS

108

102

10 1

'"-=

R2.aOkn

106
105
104

103
R2.100kn

102

103

RMOOkn

101
10 1

102

103

104

105

106

Cl (pF)

10-7

10-6

10-5

10-4

10-3

10-2

10-1

R1Cl

Figure 20. Frequency Offset versus C1

High-Speed CMOS Logic Data
DL129-Rev6

102

Figure 21. Typical Frequency Lock Range (2fL)
versus R1C1

3-601

MOTOROLA

MC?4HC4046A
20~------------------------------,

14

Rl.J.OkQ

Cl=39pF
12

Rl=10kQ

15

10

Rl=20kQ

N

N

I

I

~

d 10
a:

UJ

"-

Rl.JOkQ

~

RMOkQ

UJ

B.O

d 6.0
a:
"4.0

Rl=50kQ

5.0

Rl=3kQ
Rl=10kQ
Rl=20kQ
RMOkQ
Rl=40kQ
R1=50kQ
Rl=l00 kQ
Rl=300kQ

2.0
Rl=l00 kQ

0
Rl=300kQ

-2.0
1.0

102

103

105

100

102

R2 (k,Q)
Figure 22. R2 versus f max

103
R2 (k,Q)

105

106

Figure 23. R2 versus fmin

20~---------------------------------,

Cl=39 pF

N

J

I

~

N

. .~:::==========I

Rl=10kQ
Rl=3.0kQ

____-------------------1Rl~OkQ

....I

____----.....;.--------------t

10

Rl.JO kQ

__---------------1 Rl=40kQ
__------------1 Rl=50kQ

~

_--------------1

Rl=l00kQ

'-__- - - - - - - - - - - - - - 1 Rl=300kQ
0
1.0

101

102

103

R2 (k,Q)
Figure 24. R2 versus Frequency Lock Range (2fL)

MOTOROLA

3-602

High-Speed CMOS Logic Data

DL129-Rev6

MC74HC4046A
APPLICATION INFORMATION
The following information is a guide for approximate values of R1, R2, and C1. Figures 19, 20, and 21 should be used as
references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC
ELECTRICAL CHARACTERISTICS tables.
Phase Comparator 1
R2=~

R2'"

Phase Comparator 2
00

R2=~

R2 '" co

Phase Comparator 3
R2=~

R2 '"

00

• Given to

• Given to and fL

• Given f max and to

• Given to and fL

• Given fmax and to

• Given to and fL

• Use to with Figure
19 to determine
R1 and C1.

• Calculate fmin
fmin =to-fL

• Determine the
value of R1 and
C1 using Figure 19
and use Figure 21
to obtain 2fL and
then use this to
calculate fmin.

• Calculate fmin
fmin =1O-fL

• Determine the
value of R1 and
C1 using Figure 19
and Figure 21 to
obtain 2fL and
then use this to
calculate fmin.

• Calculate fmin:
fmin=fD-fL

(see Figure 23 for
characteristics of
the VCO operation)

• Determine values
of C1 and R2 from
Figure 20.
• Determine R1-C1
from Figure 21.

• Determine values
of C1 and R2 from
Figure 20.
• Determine R1-C1
from Figure 21.

• Determine values
of C1 and R2 from
Figure 20.
• Determine R1-C1
from Figure 21.

• Calculate value of
R1 from the value
of C1 and the
product of R1 C1
from Figure 21 .

• Calculate value of
R1 from the value
of C1 and the
product of R1C1
from Figure 21.

• Calculate value of
R1 from the value
of C1 and the
product of R 1C 1
from Figure 21.

(see Figure 24 for
characteristics of the
VCO operation)

(see Figure 24 for
characteristics of the
VCO operation)

(see Figure 24 for
characteristics of the
VCO operation)

High-Speed CMOS Logic Data
DL129-Rev6

3-603

MOTOROLA

AN1410
Application Note

Configuring and Applying the
MC54/74HC4046A Phase-Locked Loop
A versatile device for 0.1 to 16MHz frequency synchronization

Prepared by
Cleon Petty
Gary Tharalson
Marten Smith
Applications Engineering

12193

© Motorola, Inc. 1996

3-604

REV 1

®

MOTOROLA

Configuring and Applying the
MC54n4HC4046A Phase-Locked Loop
A versatile device for 0.1 to 16MHz frequency synchronization
The MC54174HC4046A (hereafter designated HC4046A)
phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and an output amplifier. The
user of this document should have a copy of the HC4046A
data sheet in Motorola Data Book DL 129 available for details
of device operation and operating specifications. The user
should also be aware that the following information is useful

Ref Osc

Phase Detector

Feedback

:1----1:

for approximating a design but, because of process, layout
and other variables, there can be substantial deviation
between theory and actual results. Therefore, it is highly recommended that prototypes be built and checked before
committing a design to production.
Typical applications for the HC4046A usually involve a configuration such as shown in Figure 1.

Low Pass Filter

I

:1----I:L...-__

v_C_O_---I:

I

I

I

Figure 1. Typical Phase-Locked Loop
VCO/OUTPUT FREQUENCY

There are two components that comprise the I charge for
the HC4046A VCO, 11 and 12. 11 isthe currentthat sets the frequency associated with the VCO input and is a function of Rl,
VCOin, and an internal current mirror that is ratioed at 120/5 =
24, resulting in the equation:

The output frequency, Fo, is calculated as a function of the
Ref Osc input and the +N feedback counter:

(1)

Fo = Ref Osc • N

(5 )

The ability of the loop to emulate the above formula makes it
ideal for multiplying an input frequency by any number up to
the maximum of the VCO. The HC4046A VCO frequency is
controlled by the equation:
VCO freq = f(1 • C)

12 is set by R2 and adds a constant current to limit the Fo min of
the VCO and is a function of Vdd, R2, and an internal current
mirror of ratio 23/5, resulting in the equation:

(2)

12 =

where I is controlled by the external resistors Rl and R2and C
by external capacitor Cext .

(~~~)

The dV of Equation (4) is determined by design to be = 1/3
Vdd. Substituting this and I = 11 + 12 into Equation (4) results in:

Frequency of oscillation is calculated by starting with the
familiar equation:

F

-

VCOin (120)
R1
5

+ (2Vdd)(~)

veo,n (24)

+ (2V
dd)(4.6)
3R2

3R2
Vdd
2Cext s

0-

1=

c dV

(3 )

dt

_

and reworking it to obtain a formula that incorporates all the
detail to fit the HC4046A. First, the charge time of the device
for half-cycle time is obtained as follows:
dt = dVf

and

Fo =

F

2~t

2CdV

I

0 = -1- = 2CdV

=

5

Vdd
2C ext s
3veoin (24)
Rl

+ 2Vdd (4.6)
R2

(7)

2Cext Vdd
It was found by experiment that when the Cext potential
reaches threshold (atVdd/3), the inversion ofthecharging voltage of Cext is forced below ground due to charge coupling.
Therefore, the dV is not just V dd/3 as expected and the charg-

(4 )

where I and dV must be obtained for the HC4046A.

High-Speed CMOS Logic Data
DL129- Rev 6

R1

-

1

or,

(6)

(253 )

3-605

MOTOROLA

131

ing time must start at a point below ground which affects t and
thus, Fo. A undershoot voltage must be added to the equation
for better accuracy in calculating t and Fo. This modifies Equation ( 7 ) as follows:
3VCOin (24)

Fo =

+ 2Vdd (4.6)

Rl

for Cext::; 1OOOpF, adding Cstray to the Cext fixed capacitance
will result in better accuracy.
The gain of a VCO is calculated by knowing f max at VCOin
max and fmin at VCOinmin and calculating the following equation:

R2

2Cext (Vdd

+ 3 * undershoot)

3VCOin(lconstant ratio)
Rl

2Cext (Vdd

VCO gain =

9.2(Vdd)

+~

+ 3 * undershoot)

It was determined by experiment that the undershoot of the
charging waveform is a function of Cext and an on-chip parasitic diode that clamps it at a maximum of -{J.7V. The size of
the Cext capacitor limits the voltage and was found to be near
zerovoltsforCstray=17pF::;C ext::;30pF;thevoltageincreases
at 6 mV/pF for a 30pF::; Cext::; 150pF range of Cext. The onchip diode then takes over and limits the voltage to -0.7V.

(9)

= Mreq/volt

(8 )

Equation ( 8) now contains all the factors to calculate a Fo for
the HC4046A VCO.

f max - fmin.
VCOin max - VCOin min

The gain of the VCO is needed to calculate a suitable loop filter
for a PLL system.
Fo is determined by VCOin and is clamped as a function of a
% of Vdd. The clamp voltage generally follows the slope of
4%N for Vdd changes from 3.5V ::; V dd ::; 6V, starting at 56% at
Vdd = 3.5V and going to 66% at Vdd = 6V. Knowing this limit
point allows picking a VCOin max pOint a few hundred mV
below it and keeps Fo in the linear range of operation. It also
best to pick a VCOin min point at a level of a few hundred mV
above OV for the same reason given above.

It was also foundthatthe Iconstant ratio is a function of R1 and
increases as R1 becomes larger. The change is attributed to
saturation of the current mirror at lower value resistances, and
to voltage divider problems at higher value resistances combined with the resistance of the small FET in the current mirror.
Experimental data shows that Icon stant ratio follows Table 1
somewhat. The ratio goes to,25 somewhere between 9.1 Kn
and 51 Kn, and for those limits, 25 should give reasonable
results. In addition, these numbers seem to hold for a range of
Vdd of 3.0V::; Vdd::; 6V.

As an example, fora C ext=1100pF, R1 = 9.1K, R2 =00, Vdd
=5.0V, and VCOin min = 0.25V, VCOin max can be determined
and a gain calculated as follows. VCOin limit = (4%N)(1.5V) +
56% = (62%)(Vdd) = 3.1V. So, for sake of linearity, choose
VCOin = 2.5V. Using Equation ( 8 ), VCOin min and VCOin max
can be used to calculate Fo min and Fo max as follows:
(3)(0.25)(21.5)
F min =
.
9.1K
= 113.4KHz
2(100*10-12)(5 + 2.1)
o
(3)(2.5)(21.5)

Table 1. Icon stant ratio versus R1
R1 (KQ)

'constant ratio

3,0
5.1
9.1
12
15
30
40
51
110
300

13.5
17.5
21.5
23.0
24.0
26.5
27.0
28.5
29.0
31.0

F max
o

(3)(1)(31)
3iiiiK
0 - 2(0.1 *10-6)(4.5

VCO gain

+ 2.1)

2(100*10-12)(5

= 1.3MHz

= 1.3 * 106-0.11 * 106 = 528.9KHz/V
2.5-0.25

This gain factor will be known as Kvco in the loop filter equations.
R2 is used in applications where a minimum output frequency is desired when VCOin is OV.lt is calculated at VCOin =
OV causing Equation ( 8 ) to become:
Fo =

9.2 (Vdd)
2C (R2) (Vdd + 3' undershoot)

The additional 12 current is a constant that adds to total charge
currentfor Cext and increases the VCOin versus Fo curve by a
theoretical constant amount. In reality, the amount of increase
actually decreases at a slight rate as VCOin increases. The
decrease is slight and the use of Equation ( 8 ) will give adequate accuracy for most applications.

+ 2.1)

= 235Hz
For comparison, from Chart 14D in the HC4046A data sheet,
the Fo based on measurements is approximately 270 Hz.
Thus, the calculated and measured values are not too far
apart taking into consideration such variables as process variation, temperature, and breadboard inaccuracies. The Cstray
of a PCB layout will affect results if the Cext is not ~ Cstray. So

MOTOROLA

~

Then, using Equation ( 9 ), the VCO gain is:

The VCO calculation [Equation ( 8 )] becomes a bit more
accurate by adjusting the VCOin and Iconstant ratio. For example, with R1 =300K, R2=oo,Cext=0.1IlF, VCOin= 1.0V, Vdd=
4.5V, and Iconstant ratio = 31, Equation ( 8 ) yields:

F -

=

The Fmax olthe HC4046A VCO was determined to be about
16MHz. Beyond 16MHz, the output logic swing tends to
reduce and is therefore somewhat useless for driving a CMOS
input. The VCO will operate at = 28MHz but the output has a
VOL= 2.0V and a VOH= 4.5V at Vdd = 5.0V.

3-606

High-Speed CMOS Logic Data
DL129-Rev6

The following table was generated to make calculation of R1
andCext afunction of Fowith Vdd = 5V, VCOin=1V, and room
temperature. Use of the table allows a rough estimate of
(R1 )(Cext) for a given Fo. The final values can be adjusted by
use of Equation ( 8 ), Table 1 forlconstant ratio, rulef; for undershoot voltage, Vdd variations,. and VCOin variations. The
example below shows a typical calculation.

R1
0det Charge Pump Output ~ VCOin

lR~

I

C1

Figure 3. Simple Low Pass Filter B
Table 2. (R1)(C e xt) versus Fo

R1 (n)

150"Cext"~

5.40/Fo
4.15/Fo
3.BO/Fo

9.1K"Rl,,50K

0"C ext,,30
30" Cext" 150
150" Cext" ~

7.50/Fo
5.77/Fo
5.2B/Fo

50K" Rl ,,900K

0"C ext,,30
30" Cext" 150
150" Cext" ~

9.00/Fo
6.921Fo
6.341Fo

3.0K" Rl "9.0K

The equations for calculating loop natural frequency (wn)
and damping factor (d) are as follows:

(R1)(Ce xt)

Cext(pF)
0" Cext" 30
30" Cext" 150

For Filter A (Figure 2):
wn =

d =

0. 5w n
K",KVCO

where K0 = phase detector gain, KVCO = VCO gain, and N =
divide counter.

Assume a desired value of Fo of 1MHz. From Table 2,
choose an R1 range of9.1K~ R1 ~50K and a Cext range of>
150pF; this condition leads to (R1)(Cext) = 5.28/Fo. Thus,
(R1) (Cext> =

K",KVCO
NC1R1

For Filter B (Figure 3):
K",KVCO

wn =

5.28 = 5.28 * 10-6
1 *10 6
d = 0.5wn(R2C1

Now choose a Cext of 200pF. Then, from above result,

+ - KN
K)

(10 )

'" VCO

R1 = 5.28 * 10-6 = 26K
200 *10- 12

Figure 4 shows an active filter using an op amp from Application Note AN535/D.

This appears reasonable and there are standard values for
Cext = 200pF and R1 = 27K. Using these values, Equation (8)
can be adjusted according to the desired Fo min, Fo max, and
Fo center.
0det Charge
Pump Output

>--e--

VCOin

LOW PASS FILTER DESIGN
Figure 4. Op Amp Filter

The design of low pass filters is well known and the intent
here is to simply show some typical examples. Reference
should be made to the HC4046A Data Sheet and to Motorola
Application Note AN535/D - "Phase-Locked Loop Fundamentals" (available through Motorola Literature Distribution).

. For Figure 4, the equations become:
w

Some simple types of low pass filters are shown in Figure 2
and Figure 3.

n

=

C1

wn~1 R2 ,where

(12 )

Op Amp gain is large

From the above equations, it is possible to design a suitable
filter to meet the needs of many PLL applications. The inclusion of R2 in the equations for Figure 3 and Figure 4 permits
the capability to change wn and d separately while Figure 2

Figure 2. Simple Low Pass Filter A

High-Speed CMOS Logic Data
DL129-Rev6

( 11 )

d = K",KVCOR2
2wnNR1

R1
0detCharge Pump Output ~ VCOin

I

= JK,.,KVCO
NC1 R1

3-607

MOTOROLA

equations do not. Normally, a design is easier if wn and d can
be chosen independenlly. Both factors affect the loop acquisition time and stability. A good starting value for d is 0.707 and
Fref/10 for wn.

Recalling that the clamp voltage % at Vdd = 5V is about 62,
then Fmax VCOin limit = (0.62)(5) = 3.1 V, but as described earlier, this needs to be reduced by a factor to bring it into linearity
(~350mV) so the final Fmax VCOin limit = 2.75V.

Manipulation of the equations allows calculation of R1, R2,
and C1 from the other measured, calculated, or picked parameters. For example,

For the Fmin VCOin limit pick 0.25V. This results in a center
frequency VCOin of:
Center freq VCOin

= 2.75 2" 0.25 = 1.25V

(13 )
From Table 2, for picked values of 9.11<5;R1 ::;50K and
30::;C ext ::;150, obtain an estimate for (R1)(C ext) of 5.77/Fo .
Thus, at the Fo center frequency,

(14 )

C1 -_

(R1)(Cext) =

K",KVCO
or alternatively,
NWn2(R1 + R2)'

Now, a reasonable starting point is established for selling the
values of the loop filter and the VCO range. Choosing R1 =
9.1 K, Cext becomes
C

Usually, C1, wn, and d are picked and the remaining parameters calculated.

t = 5.245 * 10-6 = 576pF WHOOPS'
ex
9.1K
.

This value, 576pF, is outside of the original picked range for
Cext; therefore, we need to go back and pick a larger value of
R1, e.g., 42K should be sufficient. Then Cext becomes

DESIGN EXAMPLE
The goal is to design a phase-locked loop that has an Fref of
100KHz, an output Fo of 1 MHz center frequency, and the ability to move from 200KHz to 2M Hz in 100KHz steps.
RetOsc
Fret

5.77 6 = 5.245*10-6
1.1*10

C

t = 5.245 *10-6 = 125pF
ex
42K

and now both R1 and Cext are within selected ranges.
Now calculate Fmax and Fmin using Equation (8) with R1 =
42kn, R2 =00, V dd =5.0V, Iconstantratio=27 (from Table 1. and
R1 = 42kn), Vundershoot = 0.57V (calculated from 6pF/mV
(125pF-30pF) = 0.57V), VCOin min = 0.25V, and VCOin max =
2.75V:

to

(3)(0.25)(27)

+ ~~ 0

F min =
42K
00
o
(2)(125 *1O-12f) [5.0V + 3(0.57V)]

Figure 5. Parametized PLL
To determine N, use equation (1) for Fo min = 200KHz, and
Fo max = 2MHz resulting in the following:

20.25
= 287.4KHz
70.455 * 10-6

N min = 200/100 = 2, and
(3)(2.75)(27)

N max = 2000/100 = 20

+ ~0

F max
42K
00
o
(2)(125 *10-12f) [5.0V + 3(0.57V)]

The results so far indicate the following starting parameters:

A. A VCO with a 10:1 range is required
222.75
= 3.16MHz
70.455 * 10-6

B. wn = Fref/10 = 10KHz
C. d =0.707

Fmax is > the required 2.0MHz, but the Fmin is not low
enough for required application. It is necessary to adjust either
Cext or R1to achieve required specification of 0.2 to 2.0MHz
Fo. Since R1 = 42kn is a standard resistor value, try adjusting
Cext to a higher value, such as 175pF. Because Cext is now>
150pF, the Vundershoot must be adjustedto 0.7V, as per earlier
explanation:

D. R2 =00
E. Vdd = 5.0V
The Fo center frequency ~
Fmax

+ Fmin = 2.0 + 0.2 = 11MHz
2 2 '

MOTOROLA

3-608

High-Speed CMOS Logic Data
DL129-Rev6

So,
(3)(0.25)(27)

Choose Cl to be O.Ol/-lF, N = 10 for approximate mid-range
Fo , and calculate Rl and R2 using Equations ( 13 ) and ( 14 ):

+ ~2;40) 0

R

F min =
42K
~
o
(2)(175 *10-12f) [5.0V + 3(0.7V)]
20.25
104.37 *10- 6

1

+

R _ K",KVCO _
(0.4)(4.86 *10 6)
2 - NCl wn2 - (10)(0.01 * 10-6)(62.83 * 103)2

= 1.944 * 106 = 4924.5Q

= 194.02KHz

394.76

and
(3)(2.75)(27)

R -~_
N
2 - C1 Wn
Cl(K",KVCO)

+ (~}~ 0

F max
42K
~
o
(2)(175*10- 12f) [5.0V + 3(0.7V)]

(2)(0.707)
10
(0.01 *10-6) (62830) (0.01 *10-6)(0.4)(4.86*106)

222.75
= 2.13MHz
104.37 * 10-6

= 2250.52-514.4 = 1736Q

These values are adequate for the specified application.

Then, Rl = 4924.5 -1736 = 3188.5Q.

The next item to determine is the VCO gain factor, KVCO,
using Equation ( 9 ):

Since N is changeable, it is a good idea to check min and
max on wn and d. For more information on why, see Motorola
Application Note AN535/D or the MC4044 Data Sheet in the
MECL Data Book DL1221D. The following examples show
sample calculations for N = 2 and 20.

K
=
f max - fmin
VCO
VCOin max - VCOin min

For N = 20, use Equation ( 10 ) to calculate wn and d:
KVCO

= 2.13*106

- 0.194*106
2.75V - 0.25V

= 7744KHz/V
.

or in radians
(0.4)(4.86 * 106)

(211:) (774.4 *10 3) = 4.86 *106 Rad/sec/V

(20)(0.01 * 10-6 )(3188.5
The final values used for the desired frequency range are
Rl = 42kQ, Cext = 175pF, R2 = 00, VCOin max = 2.75V, and
VCOin min = 0.25V.

+

1736)

= 44.43 * 103 rad/sec, or
= 44.43 * 103 rad/sec '" 7KHz

The next step is to determine the loop filter. Choosing a filter
like the one in Figure 3, calculate the component as follows:

211:
and

K",

Vdd
= 4it
= 5.0
411: = O.4V /rad

wn = 1O~~HZ = 10KHz * 211: = 62.83 * 103rad/sec
(0.5)(44.43 * 103) *

d = 0.707 (for starters), and

[ (1736)(0.01 *10-6)

N=2t020

+

20
]
(0.4)(4.86 * 106)

where
K0 = phase detector gain

= 0.6144

Vdd = output swing

High-Speed CMOS Logic Data

DL129-Rev6

3-609

MOTOROLA

For N=2:

This shows the effect of changing n on loop performance and
for this application is adequate.

Wn max =

(0.4)(4.86 *10 6)
(2)(0.01 *10- 6)(3188.5

If the components are not what is desired, choosing a different wn and/or d allows them to be modified.

+ 1736)

Alternatively, picking different C, R1 or R2 and recalculating
the other parameters can be done. If the filter does not provide
adequate performance, making wn smaller or d larger may
improve stability.

= 140.49 *103 rad/sec, or

_ 140.49 *103 rad/sec = 22.36KHz

-

211:

and
d max = (0.5)(140.49 * 103) *
[(1736)(0.01 *10- 6)

+ (0.4)(4.~6 *10 6)]

= 1.292

Note: Application Note AN535/D can also be found in BR1334/D, Motorola's High Performance Frequency Control Products book, also available
through the literature distibution center.

MOTOROLA

3-610

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC4049
MC54/74HC4050

Hex Buffers/Logic-Level
Down Converters
High-Performance Silicon-Gate CMOS
The MC54/74HC4049 consists of six inverting buffers, and the
MC54174HC4050 consists of six noninverting buffers. They are identical in
pinout to the MC14049UB and MC14050B metal-gate CMOS buffers. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The input protection circuitry on these devices has been modified by
eliminating the VCC diodes to allow the use of input voltages up to 15 volts.
Thus, the devices may be used as logic-level translators that convert from a
high voltage to a low voltage while operating at the low-voltage power
supply. They allow MC14000-series CMOS operating up to 15 volts to be
interfaced with High-Speed CMOS at 2 to 6 volts. The protection diodes to
GND are Zener diodes, which protect the inputs from both positive and
negative voltage transients.
•
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2to 6 V
Low Input Current: 5 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 36 FETs or 9 Equivalent Gates (4049)
24 FETs or 6 Equivalent Gates (4050)

JSUFFIX
CERAMIC PACKAGE
CASE 620-10

N SUFFIX
PLASTIC PACKAGE
CASE 64S-QS

16#

D SUFFIX
SOIC PACKAGE
CASE 7518-05

ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXD

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
LOGIC DIAGRAMS
HC4049
(INVERTING BUFFER)

AO~YO
A1~Y1

PNC
PY5

VCe! 1.

16

HC4050
(NONINVERTING BUFFER)

YO [ 2

15

AO [ 3

14 PA5

AO~YO

Y1 [ 4

13 P NC

A1 [ 5

12

A1~Y1

Y2 [ 6

11

A2 [ 7

10 P Y3

GND[ 8

9 PA3

A2~Y2

A2~Y2

A3~Y3

A3~Y3

A4~Y4

A4~Y4

PY4
PA4

NC ~ NO CONNECTION

FUNCTION TABLE

A5~Y5

Y Outputs

A
Input

HC4049

HC4060

L
H

H
L

L
H

PIN 1 ~ VCC
PIN 8~GND
PINS 13, 16 ~ NO CONNECTION

10/95

© Motorola, Inc. 1995

3-611

REVS

®

MOTOROLA

MC54/74HC4049 MC54174HC4050
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Yin

DC Input Voltage (Referenced to GND)

Vout

DC Output Voltage (Referenced to GND)

lin

Value

Unit

- 0.5 to + 7.0

V

-1.5to+18

V

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

Tstg
TL

Storage Temperature

-65to+ 150

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields referenced to the GND pin,
only. Extra precautions must be
taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance
circuit. For proper operation, the
ranges GND :s Yin :S 15 V and
GND:s Vout :S VCC are recommended.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).

'c
'c

260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C Irom 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin
Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC = 4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC
to 15

V

0

VCC

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

:S 85'C

:S 125'C

Unit

Minimum High-Level Input
Voltage

Vout=VCC-O.l V
1I0uti :S 20 I1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 VorVcc- 0.1 V
1I0uti :S 20 I1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Vin=VIH
1I0uti :S 20 I1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL 1I0uti :S 4.0 mA
1I0uti :S 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
1I0uti :S 20 I1A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL 1I0uti :S 4.0 mA
1I0uti :S 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Yin = VCC or GND
Vin= 15V

6.0
6.0

±0.1
0.5

±1.0
5.0

±1.0
5.0

I1A

Maximum Quiescent Supply
Current (per Package)

Yin = 15 V or GND
lout = 0!1A

6.0

2

20

40

I1A

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25'C

VIH

VOH

Parameter

VCC
V

V

NOTE: Information on tYPical parametric values can be found In Chapter 2.

MOTOROLA

3-612

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4049 MC54/74HC4050
AC ELECTRICAL CHARACTERISTICS (CL =50 pF. Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55to
25'e

:5 85'e

:5 125'e

Unit

tpLH.
tpHL

Maximum Propagation Delay. Input A to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

85
17
14

105
21
18

130
26
22

ns

tTLH.
tTHL

Maximum Output Transition Time. Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

10

10

10

pF

Symbol

Parameter

Maximum Input Capacitance

Cin

NOTES:
1. For propagation delays with loads other than 50 pF. see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'e. Vee = 5.0 V
Power Dissipation Capacitance (Per Buffer)"

27

"Used to determine the no-load dynamic power consumption: PD

INPUT A

=CPD VCC 2f + ICC VCC. For load considerations. see Chapter 2.

-Vcc
INPUT A
11<----- GND

1 1 ' - - - - - GND

OUTPUTY

OUTPUT Y _ _---.:;~
tTLH

Figure 1b. Switching Waveforms (HC4050)

Figure 1a. Switching Waveforms (HC4049)

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

" Includes all probe and jig capacitance

Figure 2. Test Circuit

High-Speed CMOS Logic Data
DL129-Rev6

3-613

MOTOROLA

MC54174HC4049 MC54174HC4050
LOGIC DETAIL
HC4049
(1/6 of the Device)
y

A------1

HC4050
(1/6 of the Device)

A------~~~~t>__y

TYPICAL APPLICATIONS
LSTTL to Low-Voltalge HSCMOS

High-Voltage CMOS to HSCMOS

INo

LSTIL
DEVICE

HC4049
HC4050

HC DEVICE

VDO'1'
STANDARD
CMOS

NOTE: To determine the noise immunity for the LSTTL to 10w-voHage
configuration, use Eq. 1 and Eq. 2:
(TTL) VOH - (CMOS) VIH
Eq. 1
(TTL) VOL - (CMOS) VIL
Eq.2

F'

~

OUT

HC4049
HC4050

HC DEVICE

*Table 1. Supply Examples

For the supply levels shown:
2.4- 3 (75%) = 2.4- 2.25 = 0.15 V
0.4 - 3 (15%) = 0.4 - 0.45 = 0.05 V

Voo

Vee

15 V

2V

12V

5V

12V

3V

Therefore, worst case noise immunity is 50 mY.
For supply levels greater than 4.5 volts use
the 74HCT04A for direct interface to TTL outputs.

MOTOROLA

3-614

High-Speed CMOS Logic Data
DLl29-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Analog Multiplexers/
Demultiplexers

MC54/74HC4051
MC74HC4052
MC54/74HC4053

High-Performance Silicon-Gate CMOS
The MC54n4HC4051, MC74HC4052 and MC54n4HC4053 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON
resistances, and low OFF leakage currents. These analog multiplexers/
demultiplexers control analog voltages that may vary across the complete
power supply range (from VCC to VEE).
The HC4051, HC4052 and HC4053 are identical in pinout to the
metal-gate MC14051B, MC14052B and MC14053B. The Channel-Select
inputs determine which one of the Analog Inputs/Outputs is to be connected,
by means of an analog switch, to the Common Output/Input. When the
Enable pin is HIGH, all analog switches are tumed off.
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal-gate CMOS analog
switches.
For multiplexers/demultiplexers with channel-select latches, see
HC4351, HC4352 and HC4353.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC - VEE) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal-Gate
Counterparts
• Low Noise
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HC4051 -184 FETs or 46 Equivalent Gates
HC4052 - 168 FETs or 42 Equivalent Gates
HC4053 - 156 FETs or 39 Equivalent Gates

J SUFFIX
CERAMIC PACKAGE
CASE 620-10

N SUFFIX
PLASTIC PACKAGE
CASE 648-08
DSUFFIX
SOIC PACKAGE
CASE 751 8-05
DWSUFFIX
SOIC PACKAGE
CASE 751G-02
DTSUFFIX
TSSOP PACKAGE
CASE 948F-Q1
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXD
MC74HCXXXXDW
MC74HCXXXXDT

FUNCTION TABLE - MC54n4HC4051
Control Inputs

LOGIC DIAGRAM
MC54n4HC4051
Single-Pole, 8-Position Plus Common Off

Select
Enable

C

B

A

ON Channels

L
L
L
L
L
L
L
L
H

L
L
L
L
H
H
H
H
X

L
L
H
H
L
L
H
H
X

L
H
L
H
L
H
L
H
X

XO
X1
X2
X3
X4
X5
X6
X7
NONE

XO 13
X1 14
ANALOG
INPUTS/
OUTPUTS

X2 15
12

X3
X4 1

MULTIPLEXER!
DEMULTIPLEXER

X5 5
X6 2
X7 4

AB.!:~~~TTI--"t(

CHANNEL [
SELECT
INPUTS
C....;S'--_ _ _---'

Ceramic
Plastic
SOIC
SOIC Wide
TSSOP

3 X COMMON

OUTPUT/
INPUT

Pinout: MC54n4HC4051 (Top View)
VCC

X1

XO

X3

X

X7

X5

x = Don't Care

ABC

ENABLE....;6'---------'
PIN 16 = VCC
PIN 7 = VEE
PIN 8=GND

X4

X6

Enable VEE

10195

© Motorola, Inc. 1995

3-615

REV7

@ MOTOROLA

MC54/? 4HC4051 MC?4HC4052 MC54/? 4HC4053
FUNCTION TABLE - MC74HC4052
LOGIC DIAGRAM
MC74HC4052
Double-Pole, 4-Position Plus Common Off

Control Inputs
Select
Enable

B

A

ON Channels

L
L
L
L
H

L
L
H
H
X

L
H
L
H
X

YO
YI
Y2
Y3

X SWITCH
ANALOG
INPUTS/OUTPUTS

13

--

VO 1
VI 5
V2 2
V3 4

V SWITCH

X COMMON
OUTPUTS/INPUTS

1

ENABLE-S
=-------------'

NONE

X = Don't Care

3 V

Pinout: MC74HC4052 (Top View)

~10~~:r~~--'7~

CHANNEL-SELECT [ A 9
INPUTS
B--"------'

XO
XI
X2
X3

X2

VCC

PIN 16 = VCC

XXO

XI

X3

A

PIN 7 = VEE
PIN8=GND

VO

VI

Enable VEE

GND

FUNCTION TABLE - MC54174HC4053
LOGIC DIAGRAM
MC54174HC4053
Triple Single-Pole, Double-Position Plus Common Off

Control Inputs
Enable

C

L

L
L
L
L
H
H
H
H
X

L
L
L
L
L
L
L
H

COMMON
OUTPUTS/INPUTS

ANALOG
INPUTS/OUTPUTS

Select
B
A
L
L
H
H
L
L
H
H
X

ON Channels

L
H
L
H
L
H
L
'H
X

ZO
ZO
ZO
ZO
ZI
ZI
ZI
ZI

YO
YO
Yl
YI
YO
YO
YI
YI
NONE

XO
XI
XO
XI
XO
XI
XO
XI

X = Don't Care

CHANNEL-SELECT [
INPUTS

:':';~::'-

____---'
9
C--"------------'
ENABLE..;s:...-------'

PIN 16= VCC
PIN 7 = VEE
PIN8=GND

Pinout: MC54174HC4053 (Top View)
VCC

V

X

VI

VO

ZI

XI

XO

ABC

NOTE: This device allows independent control of each switch_
Channei-Select Input A controls the X-Switch, Input B controls
the Y-SwHch and Input C controls the Z-Switch

MOTOROLA

3-616

ZO

Enable

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4051 MC74HC4052 MC54/74HC4053
MAXIMUM RATINGS'
Symbol
VCC

Parameter
Positive DC Supply Voltage

(Referenced to GND)
(Referenced to VEE)

Value

Unit

-0.5 to + 7.0
- 0.5 to + 14.0

V

VEE

Negative DC Supply Voltage (Referenced to GND)

-7.0 to + 5.0

V

VIS

Analog Input Voltage

VEE-0.5to
VCC+0.5

V

- 0.5 to VCC + 0.5

V

DC Current, Into or Out of Any Pin

±25

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature Range

-65to+150

'c
'c

Vin
I

TL

Digital Input Voltage (Referenced to GND)

Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND :5 (Vin or Vout) :5 VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

260
300

• Maximum Ratmgs are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125'C
TSSOP Package: -6.1 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

2.0
2.0

6.0
12.0

V

-6.0

GND

V

Analog Input Voltage

VEE

VCC

V

Digital Input Voltage (Referenced to GND)

GND

VCC

V

VCC

Positive DC Supply Voltage

VEE

Negative DC Supply Voltage, Output (Referenced to
GND)

VIS
Vin
VIO'

Static or Dynamic Voltage Across Switch

(Referenced to GND)
(Referenced to VEE)

TA

Operating Temperature Range, All Package Types

tr,tf

Input Rise/Fall Time
(Channel Select or Enable Inputs)

VCC=2.0V
VCC=4.5V
VCC = 6.0 V

1.2

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

• For voltage drops across sWitch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out olthe switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

High-Speed CMOS Logic Data
DL129-Rev6

3-617

MOTOROLA

MC54174HC4051 MC74HC4052 MC54174HC4053
DC CHARACTERISTICS -

Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted

-55 to 25°C

,;s5°C

S125°e

Unit

Ron = Per Spec

2.0
4.5
6.0

1.50
3.15
4,20

1.50
3,15
4,20

1.50
3.15
4.20

V

Maximum Low-Level Input Voltage,
Channel-5elect or Enable Inputs

Ron = Per Spec

2.0
4.5
6.0

0.3
0.9
1,2

0.3
0.9
1.2

0,3
0.9
1.2

V

Maximum Input Leakage Current,
Channel-5elect or Enable Inputs

Vin = VCC or GND,
VEE=-6.0V

6.0

±0.1

±1.0

±1.0

itA

Maximum Quiescent Supply
Current (per Packag'e)

Channel Select, Enable and
VIS = VCC or GND; VEE=GND
VIO=OV
VEE=-6.0

6.0
6.0

2
8

20
80

40
160

Parameter

VIH

Minimum High-Level Input Voltage,
Channel-5elect or Enable,lnputs

VIL

lin
ICC

Guaranteed Limit

Vee
V

Symbol

Condition

ItA

NOTE: Information on typical parametric values can be found in Chapter 2.
DC CHARACTERISTICS -

Analog Section
Guaranteed Limit

Symbol
Ron

Parameter
Maximum "ON" Resistance

Condition

Vce

VEE

-55 to 25.o e

,;s5°C

S125°e

Unit

Vin = VIL or VIH; VIS = VCC to
VEE; IS S 2.0 rnA
(Figures 1, 2)

4.5
4.5
6.0

0.0
-4.5
-6.0

190
120
100

240
150
125

280
170
140

n

Vin = VIL or VIH; VIS = VCC or
VEE (Endpoints); IS S 2.0 rnA
(Figures 1, 2)

4.5
4.5
6.0

0.0
-4.5
-6.0

150
100
80

190
125
100

230
140
115

ARon

Maximum Difference in "ON"
Resistance Between Any Two
Channels in the Same Package

Vin = VIL or VIH;
VIS = 1/2 (VCC - VEE);
Is,,2.0mA

4.5
4.5
6.0

0.0
-4.5
-6.0

30
12
10

35
15
12

40
18
14

loff

Maximum Off-Channel Leakage
Current, Any One Channel

Vin = VIL or VIH;
Via = VCC - VEE;
Switch Off (Figure 3)

6.0

-6.0

0.1

0.5

1.0

Maximum Off-Channel HC4051
Leakage Current,
HC4052
Common Channel
HC4053

Vin = VIL or VIH;
Via = VCC - VEE;
Switch Off (Figure 4)

6.0
6.0
6.0

-6.0
-6.0
-6.0

0.2
0.1
0.1

2,0
1,0
1.0

4.0
2.0
2.0

Maximum On-Channel HC4051
Leakage Current,
HC4052
Channel-to-Channel
HC4053

Vin = VIL or VIH;
Switch-t0-5witch =
VCC - VEE; (Figure 5)

6.0
6.0
6.0

-6.0
-6.0
-6.0

0.2
0.1
0.1

2.0
1.0
1.0

4.0
2.0
2.0

Ion

MOTOROLA

3-618

n

itA

itA

High-speed CMOS Logic Data
DL129-Rev6

MC54/74HC4051 MC74HC4052 MC54/74HC4053
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit

Vee
V

-55 to 25°e

"Bsoe

,,125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Channel-Select to Analog Output
(Figure 9)

2.0
4.5
6.0

370
74
63

465
93
79

550
110
94

ns

tpLH,
tpHL

Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Enable to Analog Output
(Figure 11)

2.0
4.5
6.0

290
58
49

364
73
62

430
86
73

ns

tpZL,
tpZH

Maximum Propagation Delay, Enable to Analog Output
(Figure 11)

2.0
4.5
6.0

345
69
59

435
87
74

515
103
87

ns

10

10

10

pF
pF

Symbol

Cin

ClIO

Parameter

Maximum Input Capacitance, Channel-Select or Enable Inputs
Maximum Capacitance
(All Switches Off)

AnalogJlO

35

35

35

Common 011: HC4051
HC4052
HC4053

130
80
50

130
80
50

130
80
50

Feedthrough

1.0

1.0

1.0

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2.
Typical @ 25°e, Vee
CPD

Power Dissipation Capacitance (Figure 13)·

HC4051
HC4052
HC4053

45
80
45

= 5.0 V, VEE = 0 V
pF

• Used to determme the no-load dynamiC power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-619

MOTOROLA

MC54/74HC4051 MC74HC4052 MC5417 4HC4053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Symbol
BW

Parameter
Maximum On-Channel Bandwidth
or Minimum Frequency Response
(Figure 6)

Condition
fin = 1MHz Sine Wave; Adjust fin Voltage to
Obtain OdBm at VOS; Increase fin Frequency
Until dB Meter Reads -3dB;
RL 50Q, CL 10pF

Off-Channel Feedthrough Isolation
(Figure 7)

Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051)

Total Harmonic Distortion
(Figure 14)

95
95
95

120
120
120

2.25
4.50
6.00

-2.25
-4.50
-6.00

-40
-40
-40

Vin " 1MHz Square Wave (tr tf 6ns);
Adjust RL at Setup so that IS = OA;
Enable GND
RL 600Q, CL 50pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

25
105
135

=10kQ, CL =10pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

35
145
190

fin Sine Wave; Adjust fin Voltage to Obtain
OdBm atVIS
fin 10kHz, RL 600Q, CL = 50pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-50
-50
-50

2.25
4.50
6.00

-2.25
-4.50
-6.00

-60
-60
-60

=

=

=1.0MHz, RL =50Q, CL = 10pF
= =

=

=

=

=

=

fin
THO

80
80
80

-50
-50
-50

RL

-

'53

-2.25
-4.50
-6.00

fin
Feedthrough Noise.
Channel-Select Input to Common
1/0 (Figure 8)

'52

2.25
4.50
6.00

=

fin Sine Wave; Adjust fin Voltage to Obtain
OdBm at VIS
fin 10kHz, RL 600Q, CL 50pF

=

=1.0MHz, RL =50Q, CL = 10pF
=

fin = 1kHz, RL 10kQ, CL = 50pF
THO THDmeasured - THDsource
VIS = 4.0Vpp sine wave
VIS 8.0Vpp sine wave
VIS 11.0Vpp sine wave

=

=
=

Unit

25'C
'51

-2.25
-4.50
-6.00

=

=

-

Limit'

VEE
V

2.25
4.50
6.00

=

-

VCC
V

MHz

dB

mVpp

dB

%
2.25
4.50
6.00

-2.25
-4.50
-6.00

0.10
0.08
0.05

• Limits not tested. Determined by design and verified by qualification.

MOTOROLA

3-620

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4051 MC74HC4052 MC54/74HC4053
120

300
fj)

::;;

,

250

......,.;
JL~ /\

:c

§-

200
z
~
en 150

,~ f f

u

---

en
w

,

./

a::

is

100

~

<=

o

50 ~-

a::

o

o

--'

0.25

fj)

::;;

!2.

f\"'t..
\

~/

w

~125'C

'\. I
,~5'C

f. ............

I

0.75

1.0

1.25

1.5

1.75

2.0

<>
Z
~

en
-

" ~55'C

.//

0.50

100

:c

en
w

,,-"
80
60

a::
z

0

C:
0
a::

40

I-- .'

105

!2.
w
u

90
75

z
~
en

. V'

60

en
w
a::

-

0

<=
0

a::

--

I,...- ~

45

z

f..-

~-

1---

-55'C. -

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

=2.0 V

Figure 1b. Typical On Resistance, Vee - VEE

=4.5 V

90

fj)

:c

- - =t
-+-V-

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

120

::;;

~2tA

20

VIS. INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1a. Typical On Resistance, Vee - VEE

. -~. '

-- --

1-- ~-

oo

2.25

~

I-- I-'

-

V

30

~-

1--

-

_.

12~'C

~

~5t--r----..

-

~

- 1--

--:b.
55'C

fj)

::;;

!2.
w

<>
Z
~

en

en
w

0.5 1.0

z

0

C:
0
a::

~

45

.-

.... - ,....-

~

.

,...,·1-

-

25'C

..........-r---

.- -- f - - --

30

-j;:c-

15

oo

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1c. Typical On Resistance, Vee - VEE

125'C

60

a::

15

o
o

75

:c

=6.0 V

Figure 1d. Typical On Resistance, Vee - VEE

=9.0 V

80
70
fj)
::;;

:c

!2.
w
u
z
~

50

en

40

a::

30

en
w
z

0_
<=
0

a::

_.

60

ff--

20

.~

12~'C

~

~rc:

-;;c
-

PROGRAMMABLE
POWER
SUPPLY

I--

-

1--

DC ANALYZER

.----_+==:;- VCC
DE ICE
UNDER TEST

10

o
o

1.0 2.0

3.0

4.0 5.0 6.0 7.0

8.0 9.0 10.0 11.0 12.0

VIS. INPUT VOLTAGE (VOLTS). REFERENCED TO VEE

Figure 1e. Typical On Resistance, Vee - VEE

High-Speed CMOS Logic Data
DL129-Rev6

=12.0 V

Figure 2. On Resistance Test Set-Up

3-621

MOTOROLA

MC54/74HC4051 MC74HC4052 MC54/74HC4053

Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up

Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set-Up

Vcc

Vcc

Vcc

Vas

dB
METER
RL

raJ

'::'

'Includes all probe and jig capacitance

Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set-Up

O.1J.lF

Figure 6. Maximum On Channel Bandwidth,
Test Set-Up

dB

fin o-j 1-+---1-1

METER

TEST

.-+_>---_--0 POINT

RL

Vcc
Vin:;; 1 MHz
VEE
CHANNEL SELECT
VILorVIH - - - - - - - - - - '

VCC-:r;tf=~
GND~

'Includes all probe and jig capacitance

VEE

L ---------~--~
'Includes all probe and jig capacitance

Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set-Up

Figure 7. Off Channel Feedthrough Isolation,
Test Set-Up

MOTOROLA

~

3-622

High-Speed CMOS Logic Data
DL129-Rev6

MC54n4HC4051 MC?4HC4052 MC54/?4HC4053

CHANNEl~
50"!.
SELECT

.'

~~---- VCC

TEST

H--..---o POINT

0

tplH

ANA~~~

Ir
7f

50%

\I

~----GND

tpHl

~'--_ _
~ CHANNELSELECT
'Includes all probe and jig capacitance

Figure 9a. Propagation Delays, Channel Select
to Analog Out

Figure 9b. Propagation Delay, Test Set-Up Channel
Select to Analog Out

Vcc
16
-

VCC

JLrl ANALOG 1/0

ANALOG
IN

1--+--_--0

TEST
POINT

' - - - - - - GND

ANALOG
OUT

'Includes all probe and jig capacitance

Figure 10a. Propagation Delays, Analog In
to Analog Out
.

Figure 10b. Propagation Delay, Test Set-Up
Analog In to Analog Out

CD

1 - - - - - Vec
-

POSITION 1 WHEN TESTING tPHZ AND tpZH
POSITION 2 WHEN TESTING tpLZ AND tpZl

®~------------~

GND

VCC

Vce
16

1kQ

HIGH
IMPEDANCE

TEST
POINT

I

Cl'

-=

ANALOG
OUT

HIGH
IMPEDANCE

Figure 11a. Propagation Delays, Enable to
Analog Out

High-Speed CMOS Logic Data
DL129-Rev6

Figure 11 b. Propagation Delay, Test Set-Up
Enable to Analog Out

3-623

MOTOROLA

MC54174HC4051 MC?4HC4052 MC54174HC4053

VCC

+-+-----0

NC

VCC

11

JLJL _____.....
*Includes all probe and jig capacitance

Figure 12. Crosstalk Between Any Two
Switches, Test Set-Up

Figure 13. Power Dissipation Capacitance,
Test Set-Up

-10
I-H~_~--o

-20

TO
DISTORTION
METER

~ ~F~NDA~ENTA~FREciuENC~

-30
-40
!Xl

"0

-50

- -

~-

-60

\

-70

-90
-100

- - - -DEVICE

- -

- .

".\
It'~
JW V\J IV"
111\ ~ ,hJlJ".
r , I!..,.,
'''1 ,
SOURCE

V 1/\

-80
*Includes all probe and jig capacitance

-- --

,
,
,
,
,
,
,
- - .. ,

I\.

I T

I

1.0

2.0

3.125

FREQUENCY (kHz)

Figure 14a. Total Harmonic Distortion, Test Set-Up

Figure 14b. Plot, Harmonic Distortion

APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
Vee or GND logic levels. Vee being recognized as a logic
high and GND being recognized as a logic low. In this exam·
pie:

Vee or GND through a low value resistor helps minimize
crosstalk and feedthrough noise that may be picked up by an
unused switch.
Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that:

Vee = +5V = logic high
GND = OV = logic low
The maximum analog voltage swings are determined by
the supply voltages Vee and VEE. The positive peak analog
voltage should not exceed Vee. Similarly, the negative peak
analog voltage should not go below VEE. In this example, the
difference between Vee and VEE is ten volts. Therefore,
using the configuration of Figure 15, a maximum analog sig·
nal of ten volts peak-to-peak can be controlled. Unused
analog inputs/outputs may be left floating (I.e., not connected). However, tying unused analog inputs and outputs to

MOTOROLA

Vee - GND = 2 to 6 volts
VEE - GND = 0 to -6 volts
Vee - VEE = 2 to 12 volts
and VEE ~ GND
When voltage transients above Vee and/or below VEE are
antiCipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in Figure
16. These diodes should be able to absorb the maximum
antiCipated current surges during clipping.

3-624

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4051 MC74HC4052 MC54174HC4053

+5V
+5V -

-5V -

~ -7.="'-H

------v

It-':=~ ~-

11
10
9
L-_--'

+5V

------v- -5V

J

TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS

-5V

VEE

Figure 15. Application Example

-=

Figure 16. External Germanium or
Schottky Clipping Diodes

+5V -

4:; -'--~H

VEE -

a. Using Pull-Up Resistors

b. Using HCT Interface

Figure 17. Interfacing LSTTUNMOS to CMOS Inputs

3 X

Figure 18. Function Diagram, HC4051

High-Speed CMOS Logic Data
DL129-Rev6

3-625

MOTOROLA

MC54/74HC4051 MC74HC4052 MC54/74HC4053

3 Y

Figure 19. Function Diagram, HC4052

Figure 20. Function Diagram, HC4053

MOTOROLA

3-626

High-Speed CMOS Logic Data
DL129 - Rev 6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC4060

14-Stage Binary Ripple
Counter with Oscillator
High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 620-10

The MC54/74HC4060 is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master-slave flip-flops and an oscillator with a
frequency that is controlled either by a crystal or by an RC circuit connected
externally. The output of each flip-flop feeds the next, and the frequency at
each output is half that of the preceding one. The state of the counter
advances on the negative-going edge of Osc In. The active-high Reset is
asynchronous and disables the oscillator to allow very low power consumption during standby operation.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may need to be gated with Osc Out 2 of the HC4060.
•
•
•
•
o

•
•

N SUFFIX
PLASTIC PACKAGE
CASE 64B-OB

DTSUFFIX
TSSOP PACKAGE
CASE 94BF-Ol

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 J.lA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 390 FETs or 97.5 Equivalent Gates

ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDT

PIN ASSIGNMENT
012 [ Ie

16

Vee

013 [ 2

15

010

014 [ 3

14

08

06 [ 4

13

09

05 [ 5

12

RESET

04

07 [ 6

11

OSelN

05

04 [ 7

10

ose OUT 1

06

GND [ 8

9

OSeOUT2

LOGIC DIAGRAM
ose OUT lose OUT 2
10

5
4

oselN 11

6
14
13
15

Ceramic
Plastic
TSSOP

07
08
09

FUNCTION TABLE

010
Clock
J
""\...
X

012
,013
014

Reset

Output State

L
L
H

No Change
Advance to Next State
All Outputs are Low

RESET 12
PIN 16= Vee
PIN8=GND

10/95

© Motorola, Inc. 1995

3-627

REV6

®

MOTOROLA

MC54174HC4060
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5toVCC+ 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

±20

rnA
rnA

lin

DC Input Current, per Pin

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
TSSOP Packaget

750
450

mW

- 65 to + 150

DC

Tstg

TL

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or TSSOP Package)
(Ceramic DIP)

This device contains protection
circUitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND:s (VinorVout):S VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

'c
260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
, TSSOP Package: -6.1 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

..

VCC=2.0V
VCC=4.5V
VCC=6.0V

Min

Max

2.5**

6.0

Unit
V

0

VCC

V

-55

,+ 125

'c

0
0
0

1000
500
400

ns

** The OSCillator IS guaranteed to function at 2.5 V minimum. However, parametncs are tested at
2.0 V by driving Pin 11 with an external clock source.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

-55to
25 DC

:S 85'C

:S 125'C

Unit

Minimum High-Level Input
Voltage

Vout=O.1 VorVcc-O.l V
lIoutl :S 20 ~A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
42

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.1 VorVCC-O.l V
lIoutl :S 20 ~A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage (04-010, 012-014)

Yin = VIH or VIL
lIoutl:S 20~

2.0
4.5
'6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin = VIH or VIL lIoutl :S 4.0 rnA
lIoutl :S 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
lIoutl :S 20 ~A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL lIoutl :S 4.0 rnA
lIoutl :S 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOL

Maximum Low-Level Output
Voltage (04-010, 012-014)

Test Conditions

VCC
V

VIH

VOH

Parameter

V

NOTE: Information on tYPical parametnc values can be found In Chapter 2.

MOTOROLA

3-628

High-Speed CMOS Logic Data
DL129-Rev6

MC54n 4HC4060
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (Continued)
Guaranteed Limit
Symbol
VOH

VOL

lin
ICC

VCC
V

-55to
25'C

:s; 85'C

:s; t25'C

Unit

Vin = VCC or GND
1I0uti :s; 20llA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Vin=VCCorGNDlloutl:s; 1.0mA
1I0uti :s; 1.3 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Vin = VCC or GND
1I0uti :s; 20llA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VCC or GND 1I0uti :s; 1.0 rnA
1I0utl:S; 1.3 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

± 1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
lout = 0 IlA

6.0

8

80

160

IlA

VCC
V

-55to
25'C

Parameter

Test Conditions

Minimum High-Level Output
Voltage (Osc Out 1, Osc Out 2)

Maximum Low-Level Output
Voltage (Osc Out 1, Osc Out 2)

V

NOTE: Information on typical parametric values can be found in Chapter 4.

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

:s; 85'C

:s; 125'C

Unit

f max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0
4.5
6.0

5.0
25
29

4.0
20
24

3.4
17
20

MHz

tpLH,
tpHL

Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)

2.0
4.5
6.0

530
106
91

665
133
114

795
159
135

ns

tpLH,
tpHL

Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)

2.0
4.5
6.0

1600
320
272

2000
400
344

2400
480
408

ns

tpHL

Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)

2.0
4.5
6.0

240
48
41

300
60
51

360
72
61

ns

tpLH,
tpHL

Maximum Propagation Delay, QN to QN + 1
(Figures 3 and 4)

2.0
4.5
6.0

125
25
21

155
31
26

190
38
32

ns

ITLH,
ITHL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
* For TA = 25'C and CL = 50 pF, typical propagation delay from Osc In to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tp = [205 + 107.5(N - 1)] ns
VCC = 4.5 V: tp = [41 + 21.5(N -1)] ns
VCC = 6.0 V: tp = [35 + 18.3(N -1)] ns
Typical @ 25'C, VCC = 5.0 V
Power Dissipation Capacitance (Per Package)*

35

* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-629

MOTOROLA

MC54/74HC4060
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Symbol

Vee
V

Parameter

Guaranteed Limit
-55to
25°e
s 85°e
s
100
125
20
25
17
21

Minimum Recovery lime, Reset Inactive to Osc In>
(Figure 2)

2.0
4.5
6.0

tw

Minimum Pulse Width, Osc In
(Figure 1)

2.0
4.5
6.0

80
16
14

tw

Minimum Pulse Width, Reset
(Figure 2)

2.0
4.5
6.0

Maximum Input Rise and Fall limes
(Figure 1)

2.0
4.5
6.0

trec

tr, tf

125°e

Unit

150
30
26

ns

100
20
17

120
24
20

ns

80
16
14

100
20
17

120
24
20

ns

1000
500
400

1000
500
400

1000
500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2.
>Osc In driven with external clock.

PIN DESCRIPTIONS
INPUTS

OUTPUTS
Q4-Q10, Q12-Q14 (Pins 7,5,4,6,14,13,15,1,2,3)

Osc In (Pin 11)

Active-high outputs. Each QN output divides the oscillator
frequency by 2N. The user should note that Q1, Q2, Q3, and
Q11 are not available as outputs.

Negative-edge triggering clock input. A high-ta-Iow transition on this input advances the state of the counter. Osc In
may be driven by an external clock source.

Osc Out 1, Osc Out 2 (Pins 10, 9)
Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator.
(See Figures 4 and 5). When Osc In is being driven with an
external clock source, Osc Out 1 and Osc Out 2 must be left
open circuited. With the crystal oscillator configuration in Figure 6, Osc Out 2 must be left open circuited.

Reset (Pin 12)
Active-high reset. A high level applied to this input asynchronously resets the counter to its zero state (forcing all Q outputs low) and disables the oscillator.

SWITCHING WAVEFORMS
-VCC

RESET

OSCIN

'-----GND

o
01

CLOCK

Figure 2.
Figure 1.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

> Includes all probe and jig capacitance
Figure 3.

MOTOROLA

Figure 4. Test Circuit

3-630

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4060
EXPANDED LOGIC DIAGRAM

e

e

0

e

0

e

0

e

0

e

e

0

e

0

e

0

e

0

e

A
-----

9

ose OUT 2

06= PIN 4
07= PIN 6
08=PIN14
09= PIN 13

010= PIN 15
Vee = PIN 16
GND= PIN8

r---------------------,

I

I
I
I
I

L-OSCIN 1T--oseoUT1 10----oscour2 9 - - J

For 2.0 V,;; VCC';; 6.0 V
10 Rte > RS > 2 Rte
400 Hz,;; I,;; 400 kHz
1= __
1-C- (I in Hz, Rte in ohms, Cte in larads)
3Rte te

Atc
AS

The lormula may vary for other Irequencies.

etc

Figure 5. Oscillator Circuit Using RC Configuration

High-Speed CMOS Logic Data
DL129-Rev6

3-631

MOTOROLA

MC54/74HC4060

r---------------------,
I
I

I
I
I
0sc"TN------1(j OSCOuT1--9 OScOUf2
Rt

~C2
Figure 6. Pierce Crystal Oscillator Circuit

Table 1. Crystal Oscillator Amplifier Specifications
TA =25°C (Input =Pin 11, Output =Pin 10)
Type
Input Resistance, Rin
Output Impedance, Zout (4.5 V supply)
Input Capacitance, Cin
Output Capacitance, Cout
Series Capacitance, C a
3 Vdc supply
Open loop voltage
{ 4 Vdcsupply
gain with output at
5 Vdcsupply
6 Vdc supply
full swing, "

Positive Reactance (Pierce)
60 MQ minimum
200 Q (see text)
5 pFtypical
7 pF typical
5 pF typical
5.0 expected minimum
4.0 expected minimum
3.3 expected minimum
3.1 expected minimum

PIERCE CRYSTAL OSCILLATOR DESIGN

0---101--0
"

=

c~
~~

1

Re

Xe

2

~

Values are supplied by crystal manufacturer (parallel resonant crystal)

Figure 7. Equivalent Crystal Networks

~R
rf-1Xco
T 4:

r

RS[
jXLs
.
Zioad Y'VU
-jXc
-IXcs""C...o ~

~

]Rload

o>----,I...----IV-->---------.I----- e

e

0

0

R
Osc Out 2 _9:.-_.....

----.-..----..-.
06=Pin4
07= Pin 6
OS= Pin 14
09=Pin 13

Osc Out 1 ...;1~0_ _•

010= Pin 15
Vee = Pin 16
GND= PinS

Osc In -'----'
Reset

Figure 5. Expanded Logic Diagram

r-----------------,

,

I,

L___
Osc In

____
11

____

OscOut 1 10

OscOut2

_ __

ee

For 2.0V ~ V ~ 6.0V
1ORtc > RS > 2Rtc
400Hz ~ f ~ 400Khz:

~

Reset ..;.12"----+'----1

9

f = 3 R1 ('.

RS

(f in Hz, Rtc in ohms, etc in farads)

tC'1C

Rtc
etc

The formula may vary for other frequencies.

Figure 6. Oscillator Circuit Using RC Configuration

r-------------------,

,

Reset ..;.12"----t'-;

L___
Osc In

________
11

OscOut 1 10

I,

__~

9 OscOut2

Rf

Rl

el

I

Figure 7. Pierce Crystal Oscillator Circuit

MOTOROLA

3-640

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC4060A
TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA= 25°C; Input = Pin II, Output = Pin 10)
Type

Positive Reactance (Pierce)

Input Resistance, Rin

60MQ Minimum

Output Impedance, Zout (4.5V Supply)

200Q (See Text)

Input Capacitance, Cin

5pFTypicai

Output Capacitance, Cout

7pFTypicai

Series Capacitance, Ca

5pFTypicai

Open Loop Voltage Gain with Output at Full Swing, ex

3VdcSupply
4VdcSupply
5VdcSupply
6VdcSupply

5.0 Expected Minimum
4.0 Expected Minimum
3.3 Expected Minimum
3.1 Expected Minimum

PIERCE CRYSTAL OSCILLATOR DESIGN

Value are supplied by crystal manufacturer (parallel resonant crystal).

Figure 8. Equivalent Crystal Networks

RS

-jXC2

R

Rload

O~~----~~~~I--~O

jXLs
Xload

_1-

, -:- Gin
-'-

-jXCs

~

_1_

-:-

Cout

-'-

NOTE: C =Ct + Cin and R=Rt + Rout. Co is considered as part of
the load. Ca and Rf typically have minimal effect below 2MHz.

Values are listed in Table 1.

Figure 9. Series Equivalent Crystal Load

Figure 10. Parasitic Capacitances of the Amplifier

High-Speed CMOS Logic Data
DL129-Rev6

3-641

MOTOROLA

MC54/74HC4060A
DESIGN PROCEDURES
The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional
impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from
180°C.
Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.
Ze =

- jXCo(Rs + jXLs - jXC s)
.
..
= Re
- JXC o + Rs + JXLs - JXCs

+ jXe

Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.
The maximum Rs for the crystal should be used in the equation.
Step 2: Determine /3, the attenuation, of the feedback network. For a closed-loop gain of 2,Av/3 2,/3 2/Av where Av is the gain
of the HC4060A amplifier.
Step 3: Determine the manufacturer's loading capacitance. For example: A manufacturer may specify an external load capacitance of 32pF at the required frequency.

= =

Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of
100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload (21tfoLS/Q) - Rs where Ls and Rs are crystal
parameters.

=

Step 5: Simultaneously solve, using a computer,
/3 =

Xe

XC· XC2
R . Re

+ XC2

( ) (with feedback phase shift

Xe - Xc

X

Re C2
= XC2 + Xc + --R= XCload

=180°)

(Eq 1 )

(where the loading capacitor is an external load, not including Co)

RXC oXC2 [(XC + XC2)(XC + XC o) - Xc (XC + XC o + XC2)]
Rload = -----=--------::----::--------::---X2 C2 (XC + XC o )2 + R2(XC + XCo + XC2)2

( Eq2)

( Eq3)

Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to Xc is given by C = C1 + Cin.

=

Alternately, pick a value for R1 (Le, let R1 RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that Q
2nfoLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.

the first overtone. Rf must be large enough so as to not affect
the phase of the feedback network in an appreciable manner.

CHOOSING R1

Power is dissipated in the effective series resistance of the
crystal. The drive level specified by the crystal manufacturer
is the maximum stress that a crystal can withstand without
damage or excessive shift in frequency. R1 limits the drive
level.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a function of voltage at Osc Out 2 (Pin 9). The frequency should
increase very slightly as the dc supply voltage is increased.
An overdriven crystal will decrease in frequency or become
unstable with an increase in supply voltage. The operating
supply voltage must be reduced or R1 must be increased in
value if the overdriven condition exists. The user should note
that the oscillator start-up time is proportional to the value of
R1.

ACKNOWLEDGEMENTS AND RECOMMENDED
REFERENCES
The following publications were used in preparing this data
sheet and are hereby acknowledged and recommended for
reading:
Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
D. Babin, "Designing Crystal Oscillators", Machine Design,
March 7,1985.
D. Babin, "Guidelines for Crystal Oscillator Design",
Machine Design, April 25, 1985.
ALSO RECOMMENDED FOR READING:

E. Hafner, "The Piezoelectric Crystal Unit-Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technology, June, 1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.

SELECTING Rf

The feedback resistor, Rf, typically ranges up to 20MQ. Rf
determines the gain and bandwidth of the amplifier. Proper
bandwidth insures oscillation at the correct frequency plus
roll-off to minimize gain at undesirable frequencies, such as

MOTOROLA

=

3-642

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4060A
1
Clock
Reset

2

4

8

16

32

64

128

256

512

1024

2048

4096

8192

16384

I.SlJ'lSLrLJ LJ LJ LJLJ LJLJLJ LJ LJLJ LJ LJ

----,L...-____________________________

04 _ _ _ _ _ _--J~

05

L_ L_ L_ L_ L_ L_ L_ L_ L_ L_

~

L_'L- L _ L _ L _ L _ L _ L _ L _

06

~L_L_L_L_L_L_L_L_

07

~L_L_L_L_L_L_L_

08

~L_L_L_L_L_L_

09

~L_L_L_L_L_
~

010

L_ L_ L_ L_

012

~L_L_L_

013

~L_

014

~

Figure 11. Timing Diagram

High-Speed CMOS Logic Data

DL129-Rev6

3-643

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Quad Analog Switch/
Multiplexer/Demultiplexer

MC54/74HC4066

High-Performance Silicon-Gate CMOS

JSUFFIX
CERAMIC PACKAGE
CASE 632-QB

The MC54174HC4066 utilizes silicon-gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF-channelleakage
current. This bilateral switch/multiplexer/demultiplexer controls analog and
digital voltages that may vary across the full power-supply range (from VCC
toGND).
The HC4066 is identical in pinout to the metal-gate CMOS MC14016 and
MC14066. Each device has four independent switches. The device has
been designed so that the ON resistances (RON) are much more linear over
input voltage than RON of metal-gate CMOS analog switches.
This device is identical in both function and pinout to the HC4016. The
ON/OFF control inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs. For analog
switches with voltage-level translators, see the HC4316.

N SUFFIX
PLASTIC PACKAGE
CASE 646-Q6

DSUFFIX
SOIC PACKAGE
CASE 751A-Q3

• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 12.0 Volts
• Analog Input Voltage Range (VCC - GND) 2.0 to 12.0 Volts
• Improved Linearity and Lower ON Resistance over Input Voltage than
the MC14016 or MC14066 or HC4016
• Low Noise
• Chip Complexity: 44 FETs or 11 Equivalent Gates

DTSUFFIX
TSSOP PACKAGE
CASE 94BG-01

=

ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXD
MC74HCXXXXDT

LOGIC DIAGRAM

PIN ASSIGNMENT

XA~YA
A ON/OFF CONTROL

~
~

ANALOG
OUTPUTS/INPUTS

XC~YC
C ON/OFF CONTROL

~

~ ..... ~~.

13

oAON/OFF

YB [ 3

12

J DON/OFF

[ 4
[
5

11

oXD

10

~ YD

CONTROL
CONTROL

[ 6
[

9

~ Yc

7

8

DXc

On/Off Control
Input

State of
Analog Switch

L
H

On

Off

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
PIN 14= VCC
PIN7=GND

10195

© Motorola, Inc. 1995

14

YA [ 2

FUNCTION TABLE

XO~YO
DON/OFF CONTROL

oVCC

XA [ 1-

XB
BON/OFF
CONTROL
CON/OFF
CONTROL
GND

XB~YB
B ON/OFF CONTROL

Ceramic
Plastic
SOIC
TSSOP

3-644

REV6

®

MOTOROLA

MC54174HC4066
MAXIMUM RATINGS·
Symbol

Parameter

Value

Unit

- 0.5 to + 14.0

V

Analog Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

Digital Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Current Into or Out of Any Pin

±25

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

-65to+150

°c

VCC

Positive DC Supply Voltage (Referenced to GND)

VIS
Vin
I

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ,; (Vin or Vout) ,; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus .

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65° to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125°C
TSSOP Package: - 6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

2.0

12.0

V

VCC

Positive DC Supply Voltage (Referenced to GND)

VIS

Analog Input Voltage (Referenced to GND)

GND

VCC

V

Digital Input Voltage (Referenced to GND)

GND

VCC

V

Vin
VIO'

Static or Dynamic Voltage Across Switch

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time, ON/OFF Control
Inputs (Figure 10)
VCC=2.0V
VCC=4.5V
VCC=9.0V
VCC= 12.0V

-

1.2

V

-55

+ 125

°c

0
0
0
0

1000
500
400
250

ns

• For voltage drops across the sWitch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

,; 85°C

,; 125'C

Unit

VIH

Minimum High-Level Voltage
ON/OFF Control Inputs

Ron = Per Spec

2.0
4.5
9.0
12.0

1.5
3.15
6.3
8.4

1.5
3.15
6.3
8.4

1.5
3.15
6.3
8.4

V

VIL

Maximum Low-Level Voltage
ON/OFF Control Inputs

Ron = Per Spec

2.0
4.5
9.0
12.0

0.3
0.9
1.8
2.4

0.3
0.9
1.8
2.4

0.3
0.9
1.8
2.4

V

lin

Maximum Input Leakage Current
ON/OFF Control Inputs

Vin = VCC or GND

12.0

±0.1

±1.0

± 1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
VIO=OV

6.0
12.0

2
8

20
80

40
160

llA

Symbol

ICC

Parameter

Test Conditions

NOTE: Information on tYPical parametric values can be found

High-Speed CMOS Logic Data
DL129-Rev6

In

Chapter 2.

3-645

MOTOROLA

MC54n4HC4066
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
VCC
V

-55to
25°C

Vin=VIH
VIS = VCC to GND
IS :s; 2.0 mA (Figures 1, 2)

2.0t
4.5
9.0
12.0

-

-

-

170
85
85

215
106
106

255
130
130

Vin=VIH
VIS = VCC or GND (Endpoints)
IS :s; 2.0 mA (Figures 1, 2)

2.0
4.5
9.0
12.0

-

-

-

85
63
63

106
78
78

130
95
95

Maximum Difference in "ON"
Resistance Between Any Two
Channels in the Same Package

Vin =VIH
VIS = 1/2 (VCC - GND)
IS:S; 2.0mA

2.0
4.5
9.0
12.0

-

-

-

30
20
20

35
25
25

40
30
30

loff

Maximum Off-Channel leakage
Current, Any One Channel

Vin =V,l
VIO = VCC or GND
Switch Off (Figure 3)

12.0

0.1

0.5

1.0

~A

Ion

Maximum On-Channel leakage
Current, Any One Channel

Vin =VIH
V'S = VCC or GND
(Figure 4)

12.0

0.1

0.5

1.0

~A

Symbol
Ron

ARon

Parameter

Test Conditions

Maximum "ON" Resistance

:s; 85°C

:s; 125°C

Unit
Q

Q

tAt supply voltage (VCC - GND) approaching 2 V the analog sWltch-on resistance becomes extremely non-linear. Therefore, for low-voltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

VCC
V

-55to
25°C

:s; 85°C

:s; 125°C

Unit

tPlH,
tpHl

Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)

2.0
4.5
9.0
12.0

50
10
10
10

65
13
13
13

75
15
15
15

ns

tPlZ,
tPHZ

Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)

2.0
4.5
9.0
12.0

150
30
30
30

190
38
30
30

225
45
30
30

ns

tPZl,
tpZH

Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 1 1)

2.0
4.5
9.0
12.0

125
25
25
25

160
32
32
32

185
37
37
37

ns

pF

C

Maximum Capacitance

ON/OFF Control Input

-

10

10

10

Control Input = GND
Analog I/O
Feedthrough

-

35
1.0

35
1.0

35
1.0

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'C, VCC = 5.0 V
Power Dissipation Capacitance (Per Switch) (Figure 13,.

15

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-646

High-Speed CMOS logic Data
Dl129-Rev6

MC54/74HC4066
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

Symbol

Parameter

Test Conditions

VCC
V

Limit"
25'C
54n4HC

4.5
9.0
12.0

150
160
160

MHz

dB

BW

Maximum On-Channel Bandwidth or
Minimum Frequency Response
(Figure 5)

fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter Reads - 3 dB
RL=50Q,CL=10pF

-

Off-Channel Feedthrough Isolation
(Figure 6)

Sine Wave
fin
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Q, CL = 50 pF

4.5
9.0
12.0

-50
-50
-50

fin = 1.0 MHz, RL = 50 Q, CL = 10 pF

4.5
9.0
12.0

-40
-40
-40

Vin s 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 Q, CL = 50 pF

4.5
9.0
12.0

60
130
200

RL=10kQ,CL=10pF

4.5
9.0
12.0

30
65
100

Sine Wave
fin
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Q, CL = 50 pF

4.5
9.0
12.0

-70
-70
-70

fin = 1.0 MHz, RL = 50 Q, CL = 10 pF

4.5
9.0
12.0

-80
-80
-80

-

-

THD

Feedthrough Noise, Control to
Switch
(Figure 7)

Crosstalk Between Any Two Switches
(Figure 12)

Total Harmonic Distortion
(Figure 14)

==

==

=

=

fin 1 kHz, RL 10 kQ, CL = 50 pF
THD = THDMeasured - THDSource
VIS = 4.0 Vpp sine wave
VIS = 8.0 Vpp sine wave
VIS = 11.0 Vpp sine wave

Unit

mVpp

dB

%
4.5
9.0
12.0

0.10
0.06
0.04

" Guaranteed limits not tested. Determined by design and verified by qualification.

High-Speed CMOS Logic Data
DL129-Rev6

3-647

MOTOROLA

MC54/74HC4066
120

600

en
::;;

I

500

/

:r:

~

o

400

V

:z

;:!:
en 300

~

1I.i
UJ

a:

is

200

<=

o

a: 100

./

125°C

en
::;;

:r:
Q.

'\

UJ

~

'"

en

1I.i

z
o. 40

~ -55'C

"

Figure 1a. Typical On Resistance,

<=

en

::;;

:r:
Q.

60

UJ

50

0

z

;:!:
en

1I.i
UJ

[3]

a:
z

.." ~

r-

30 ~

0

C
0
a:

--

a:

20

-

~ r--

-25'C

....l-

./
..........5~

~

"

...;;,;",.;,.

~

20

--

0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

4.5

Vee =4.5 V

120

en 100

::;;

:r:
Q.

"

UJ

0

80

-

125'C

:z

;:!:
en 60

-55'C ~

1I.i
UJ

I-"'"

a:
z

0

40

is

a:

20

o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Vin; INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1c. Typical On Resistance,

r--

!-" ............ 25°C

Figure 1b. Typical On Resistance,

10
00

,~

~~

o
o

~

-

~
i.,...- ...40

I--

V

",..

0

25'C
125'C

Vee =2.0 V

...-

70

60

UJ

a:

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

80

80

0

z
.c'
>-'

~~
"'......... r--.

t:;; V'

100

Vee =6.0 V

~

r--

o

----

-

25'C

r-

~ -55'C --

-I

1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1d. Typical On Resistance,

9.0

Vee = 9.0 V

80

en

::;;

70

:r:
Q.

60

UJ

0

50

;:!:
en

40 I,...---

z

1I.i
UJ

a:
:z

30

-

0

<=
0

a:

-

---

~

PROGRAMMABLE
POWER
SUPPLY

25'C
~

+

DC ANALYZER

....------1==:::::;-- VCC

J-

DEVICE
UNDER TEST

55'C

20
ANALOG IN

10
00

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 1e. Typical On Resistance,

MOTOROLA

COMMON OUT

-= GND

12

Vee = 12 V

Figure 2. On Resistance Test Set-Up

3-648

High-Speed CMOS Logic Dala

DL129-Rev6

MC54174HC4066

Vcc
Vcc
I-+----N/C

7

Figure 4. Maximum On Channel Leakage Current,
Test Set-Up

Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up

Vas
fin

0--11---;-1

fin

O.1IlF

0--11--+--;-1
O.1IlF
SELECTED
CONTROL
INPUT

7

"Includes all probe and jig capacitance.

"Includes all probe and jig capacitance.

Figure 5. Maximum On-Channel Bandwidth
Test Set-Up

Vcc

VCC/2

Figure 6. Off-Channel Feedthrough Isolation,
Test Set-Up

VCC/2

' - - - - - - - GND

Vin:51 MHz
Ir =lf=6ns
Vcc-n n
GND --l LJ L CONTROL _ _ _ _ _- '

-=

"Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

Figure 8. Propagation Delays, Analog In to
Analog Out

3-649

MOTOROLA

MC54/74HC4066
tf

S1.

TEST

HI---.--o POINT

Ir=----GND
tpZl

HIGH
IMPEDANCE

tpZH
HIGH
IMPEDANCE

'Includes all probe and jig capacitance.

Figure 9. Propagation Delay Test Set-Up

POSITION

-=

CD
®

POSITION

Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

CD WHEN TESTING tPHZ AND tPZH
® WHEN TESTING tPlZ AND tpZl
VOS
VCC

VCC

1k.Q

14

TEST
POINT

I

VCCORGND

Cl'

SELECTED

'-----1I---i CONTROL
INPUT

VCCI2
'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance.

Figure 11. Propagation Delay Test Set-Up

NlC---+i

Figure 12. Crosstalk Between Any Two Switches,
Test Set-Up

TO

I-I----NIC

I-Hr--~-o DISTORTION

METER

..f1.IL ONIOFF CONTROL _ _----'
'Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance
Test Set-Up

MOTOROLA

Figure 14. Total Harmonic Distortion, Test Set-Up

3-650

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4066
0
-10
-20
-30

I

-40
E
-c

lD

-50

- -

,v

\-

-60
-70
-80
-90

- - --

J\

A
I

I

DEVICE

Ie:-1\1\

'I'

1.0

r,

SOURCE

"
, rp "

~

"IF J ,

2.0

3.0

FREQUENCY (kHz)

Figure 15. Plot, Harmonic Distortion

below, the difference between Vce and GND is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
analog signal of twelve volts peak-to-peak can be controlled.
When voltage transients above Vce and/or below GND
are anticipated on the analog channels, external diodes (Ox)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn-on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Ox diodes with
MO-sorbs (Motorola high current surge protectors).
MO-sorbs are fast turn-on devices ideally suited for precise
DC protection with no inherent wear out mechanism.

APPLICATION INFORMATION
The ON/OFF Control pins should be at VCC or GND logic
levels, Vec being recognized as logic high and GND being
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is advisable
to tie unused analog inputs and outputs to Vec or GND
through a low value resistor. This minimizes crosstalk and
feedthrough noise that may be picked-up by the unused 1/0
pins.
The maximum analog voltage swings are determined by
the supply voltages VCC and GND. The positive peak analog
voltage should not exceed Vec. Similarly, the negative peak
analog voltage should not go below GND. In the example

VCC=12V
+ 12 V -

f\ . ANALOG 1/0

OV-'

ANALOG 011

V

f\ :- + 12 V

. V- OV

VCC
OTHER CONTROL
}
INPUTS
(VCCORGND)

7

Figure 16. 12 V Application

High-Speed CMOS logic Data
D1129-Rev6

':"

SELECTED
' - - - - - I CONTROL
INPUT

}

OTHER CONTROL
INPUTS
(VCCOR GND)

Figure 17. Transient Suppressor Application

3-651

MOTOROLA

[3J
3
.

MC54/74HC4066
+5V

+5V

I

R'

LSnU
NMOS

.

R' R' R'

~

=
-

5
6
15

14

ANALOG {
SIGNALS

} ANALOG
SIGNALS

r-HCT- '

HC4016

?-

14

..L

-

14

ANALOG{=
SIGNALS . =

I
I

LSnU
NMOS

}=.x

BUFFER

I
I

} ANALOG
SIGNALS

HC4016

INPUTS

7

..L

R' = 2 TO 10 k.Q

a. Using Pull-Up Resistors

b. Using HCT Buffer
Figure 18. LSTTUNMOS to HCMOS Interface
VCC=5T012V

VDD=5 V

14

ANALOG {
SIGNALS

} ANALOG
SIGNALS

HC4016

7

MC14504

2

}=~

9

4

6

11

6

14
. 15 .

10

INPUTS

7

Figure 19. TTUNMOS-to-CMOS Level Converter
Analog Signal Peak-to-Peak Greater than 5 V
(Also see HC4316)
.

CHANNEL 4

CHANNEL 3
COMMON 110
CHANNEL 2

CHANNELl

INPUT

>---OUTPUT

10F4
SWITCHES

rO.0 1 f!F
1

2
3 4
CONTROL INPUTS

Figure 20. 4-lnput Multiplexer

MOTOROLA

Figure 21. Sample/Hold Amplifier

3-652

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC4066A

Product Preview

Quad Analog Switch/
Multiplexer/Demultiplexer

J SUFFIX
CERAMIC PACKAGE
CASE 632-0B

High-Performance Silicon-Gate CMOS
The MC54/74HC4066A utilizes silicon-gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFFchannel leakage current. This bilateral switch/multiplexer/demultiplexer
controls analog and digital voltages that may vary across the full
power-supply range (from VCC to GND).
The HC4066A is identical in pinout to the metal-gate CMOS MC14016
and MC14066. Each device has four independent switches. The device
has been designed so that the ON resistances (RON) are much more
linear over input voltage than RON of metal-gate CMOS analog switches.
This device is identical in both function and pinout to the HC4016A.
The ON/OFF control inputs are compatible with standard CMOS outputs;
with pull up resistors, they are compatible with LSTTL outputs. For analog
switches with voltage-level translators, see the HC4316A.

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

DSUFFIX
SOIC PACKAGE
CASE 751A-03

DTSUFFIX
TSSOP PACKAGE
CASE 948G-01

• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Wide Power-Supply Voltage Range (VCC - GND) 2.0 to 12.0 Volts
• Analog Input Voltage Range (VCC - GND) = 2.0 to 12.0 Volts
• Improved Linearity and Lower ON Resistance over Input Voltage than
the MC14016 or MC14066 or HC4016A
• Low Noise
• Chip Complexity: 44 FETs or 11 Equivalent Gates

ORDERING INFORMATION

=

MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT

Ceramic
Plastic
SOIC
TSSOP

PIN ASSIGNMENT
LOGIC DIAGRAM

XA~YA
AON/OFF CONTROL

~

XB~YB
B ON/OFF CONTROL

~

ANALOG
OUTPUTS/INPUTS

CON/OFF CONTROL

13

YB [ 3

12 ~ 0 ON/OFF
CONTROL
11 ~ Xo

VCC

PACONTROL
ON/OFF

10

~ YO

9

PYC

8

~ Xc

FUNCTION TABLE

~

XO~YO
~ .. .. ~~.

o ON/OFF CONTROL

14

YA [ 2

XB [ 4
BON/OFF [
CONTROL 5
CON/OFF r 6
CONTROL
GNO 7

XC~YC

~

XA [ 1·

On/Off Control
Input

State of
Analog Switch

L
H

Off
On

,
ANALOG
INPUTS/OUTPUTS = XA, XB, XC, Xo
PIN 14= VCC
PIN 7 = GNO

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10195

© Motorola, Inc. 1995

3-653

REVO

®

ItIIOTOROLA

MC54/74HC4066A
MAXIMUM RATINGS·
Symbol

Parameter

Value

Unit

-0.5 to + 14.0

V

Analog Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

Digital Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Current Into or Out of Any Pin

±25

mA

PD

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget
TSSOP Packaget

750
500
450

mW

Tstg

Storage Temperature

-65to+150

'c
'c

VCC

Positive DC Supply Voltage (Referenced to GND)

VIS
Vin
I

TL

.

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)

This device contains protection
cirCUitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ~ (Vin or Vout) ~ VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus .

260
300

MaXimum Ratings are those values beyond which damage to the deVice may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/'C from 65' to 125'C
Ceramic DIP: -10 mW/'C from 100' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
TSSOP Package: -6.1 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

Unit

2.0

12.0

V

Analog Input Voltage (Referenced to GND)

GND

VCC

V

Digital Input Voltage (Referenced to GND)

GND

VCC

V

-

1.2

V

-55

+ 125

'c

0
0
0
0
0

1000
600
500
400
250

Parameter

VCC

Positive DC Supply Voltage (Referenced to GND)

VIS
Vin
VIO'

Static or Dynamic Voltage Across Switch

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time, ON/OFF Control
Inputs (Figure 10)
VCC=2.0V
VCC=3.0V
VCC = 4.5 V
VCC=9.0V
VCC= 12.0V

.

ns

For voltage drops across the sWitch greater than 1.2 V (switch on), excessive VCC current may
be drawn; I.e., the current out olthe switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25'C·

~

85'C

~

125'C

Unit

VIH

Minimum High-Level Voltage
ON/OFF Control Inputs

Ron

=Per Spec

2.0
3.0
4.5
9.0
12.0

1.5
2.1
3.15
6.3
8.4

1.5
2.1
3.15
6.3
8.4

1.5
2.1
3.15
6.3
8.4

V

VIL

Maximum Low-Level Voltage
ON/OFF Control Inputs

Ron

=Per Spec

2.0
3.0
4.5
9.0
12.0

0.5
0.9
1.35
2.7
3.6

0.5
0.9
1.35
2.7
3.6

0.5
0.9
1.35
2.7
3.6

V

Maximum Input Leakage Current
ON/OFF Control Inputs

Vin

=VCC or GND

12.0

±0.1

±1.0

± 1.0

I1A

Maximum Quiescent Supply
Current (per Package)

Vin VCC or GND
VIO =OV

=

6.0
12.0

2
4

20
40

40
160

ItA

lin
ICC

NOTE: Information on tYPical parametric values can be found

MOTOROLA

In

Chapter 2.

:Hl54

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4066A
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

Maximum "ON" Resistance

Vce
V

Vin=VIH
VIS = VCC to GND
IS ,; 2.0 rnA (Figures 1, 2)

2.0t
3.0t
4.5
9.0
12.0

Vin=VIH
VIS = VCC or GND (Endpoints)
IS :5 2.0 rnA (Figures 1, 2)

2.0
3.0
4.5
9.0
12.0

Maximum Difference in "ON"
Resistance Between Any Two
Channels in the Same Package

Vin=VIH
VIS = 1/2 (VCC - GND)
IS'; 2.0 rnA

2.0
4.5
9.0
12.0

loff

Maximum Off-Channel leakage
Current, Any One Channel

Vin = Vil
VIO = VCC or GND
Switch Off (Figure 3)

12.0

Ion

Maximum On-Channel leakage
Current, Any One Channel

Vin=VIH
VIS = VCC or GND
(Figure 4)

12.0

Ron

ARon

-55to
25°e

,; 85°C

:5 125°C

Unit

-

-

-

120
70
70

160
85
85

200
100
100

-

-

-

70
50
30

85
60
60

100
80
80

-

-

-

20
15
15

25
20
20

30
25
25

0.1

0.5

1.0

llA

0.1

0.5

1.0

llA

-

-

Q

Q

tAt supply voltage (VCC) approaching 3 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Guaranteed Limit
Parameter

Vec
V

-55to
25°C

,; 85°C

,; 125°C

Unit

tPlH,
tpHl

Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)

2.0
3.0
4.5
9.0
12.0

40
30
5
5
5

50
40
7
7
7

60
50
8
8
8

ns

tpLZ,
tpHZ

Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)

2.0
3.0
4.5
9.0
12.0

80
60
20
20
20

90
70
25
25
25

110
80
35
35
35

ns

tpZl,
tpZH

Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)

2.0
3.0
4.5
9.0
12.0

80
45
20
20
20

90
50
25
25
25

100
60
30
30
30

ns

pF

Symbol

C

Maximum Capacitance

ON/OFF Control Input

-

10

10

10

Control Input = GND
Analog 110
Feedthrough

-

35
1.0

35
1.0

35
1.0

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°C, VCC = 5.0 V
Power Dissipation Capacitance (Per Switch) (Figure 13)'
• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f

High-Speed CMOS logic Data
Dl129-Rev6

3-655

15

+ ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

MC54174HC4066A
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

Symbol

Test Conditions

Parameter

VCC
V

Limit'
25°C
54174HC

Unit

BW

Maximum On-Channel Bandwidth or
Minimum Frequency Response
(Figure 5)

fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter Reads - 3 dB
RL=50n,CL=10pF

4.5
9.0
12.0

150
160
160

MHz

-

Off-Ghannel Feedthrough Isolation
(Figure 6)

fin =0 Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 n, CL = 50 pF

4.5
9.0
12.0

-50
-50
-50

dB

fin = 1.0 MHz, RL = 50 n, CL = 10 pF

4.5
9.0
12.0

-40
-40
-40

Vin s 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
'RL = 600 n, CL = 50 pF

4.5
9.0
12.0

60
130
200

RL= 10kn, CL= 10pF

4.5
9.0
12.0

30
65
100

'in =0 Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 n, CL = 50 pF

4.5
9.0
12.0

-70
-70
-70

fin = 1.0 MHz, RL = 50 n. CL = 10 pF

4.5
9.0
12.0

-80
-80
-80

-

-

THD

Feedthrough Noise, Control to
Switch
(Figure 7)

Crosstalk Between Any Two Switches
(Figure 12)

Total Harmonic Distortion
(Figure 14)

fin=l kHz,RL=10kn,CL=50pF
THD = THDMeasured - THDSource
VIS = 4.0 Vpp sine wave
VIS = 8.0 Vpp sine wave
VIS = 11.0 Vpp sine wave

..

mVpp

dB

%
4.5
9.0
12.0

0.10
0.06
0.04

..

, Guaranteed limits not tested. Determined by deSign and verified by qualification .

MOTOROLA

3-656

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4066A

TBD

Figure 1a. Typical On Resistance,

TBD

Vee =2.0 V

Figure 1 b. Typical On Resistance,

TBD

Figure 1c. Typical On Resistance,

Vee =4.5 V

TBD

Vee = 6.0 V

Figure 1d. Typical On Resistance,

Vee = 9.0 V

PROGRAMMABLE
POWER
SUPPLY

TBD

+

DC ANALYZER

r---=I;;=;-VCC
DEVICE
UNDER TEST

ANALOG IN

Figure 1e. Typical On Resistance,

High-Speed CMOS Logic Data
DL129-Rev6

Vee =12 V

COMMON OUT

Figure 2. On Resistance Test Set-Up

3-657

MOTOROLA

MC54/74HC4066A

Vcc

Vcc

I-+----N/C

7

Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up

Figure 4. Maximum On Channel Leakage Current,
Test Set-Up

Vos

Vs
lin

o-j I---t-l

lin o-j

O.1I1F

I--+--t-l

O.1I1F
SELECTED
CONTROL
INPUT

7

"Includes all probe and jig capacitance.

"Includes all probe and jig capacitance.

Figure 5. Maximum On-Channel Bandwidth
Test Set-Up

VCC

VCC/2

Figure 6. Off-Channel Feedthrough Isolation,
Test Set-Up

VCC/2

-Vcc
'------GND
Vin~ 1 MHz

tr=tl=6ns

Vcc-nL.Jn

GND -'

'-=

L CONTROL _ _ _ _ _---'
ANALOGOI,IT

"Includes all probe and jig capacitance.

Figure 8. Propagation Delays, Analog In to
Analog Out

Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set-Up

MOTOROLA

:Hl58

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4066A

1-+---.--0

TEST
POINT

11'=-----GND
tpZl

HIGH
IMPEDANCE

tpZH
HIGH
IMPEDANCE

'Includes all probe and jig capacitance.

Figure 9. Propagation Delay Test Set-Up

POSITION

CD

-=

POSITION

Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

CD WHEN TESTING tpHZ AND tpZH
® WHEN TESTING tPlZ AND tPZl
Vas

®

VCC

VCC

1kQ

14

TEST
POINT

I

VCCORGND

Cl'

SELECTED

1..----1_-1 CONTROL
INPUT

VCC/2

7

VCC/2
'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance.

Figure 11. Propagation Delay Test Set-Up

N/C----H

Figure 12. Crosstalk Between Any Two Switches,
Test Set-Up

1-t----NlC

I--~~~"--O

TO
DISTORTION
METER

..J1.J"L ON/OFF CONTROL _ _----'
'Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance
Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

Figure 14. Total Harmonic Distortion, Test Set-Up

3-659

MOTOROLA

MC54/74HC4066A

-10
-20

~ ~F0NDAJENTA~FREciuENC~

I
II
-40
-30
E



. }am",

BUFFER

I
I

} ANALOG
SIGNALS

HC4016

INPUTS

15

..L

I
I

LSTTU
NMOS

5

14

14

ANALOG {
SIGNALS

7

..L

R'=2T010kQ

a, Using Pull-Up Resistors

b, Using HCT Buffer
Figure 18. LSTTUNMOS to HCMOS Interface
VCC=5TOI2V

Voo =5 V

14

ANALOG {
SIGNALS

} ANALOG
SIGNALS

HC4016

7

MC14504

1-=2:..-_ _ _ _....::...j
5

4
11

14

[3]

} CONOIDl
INPUTS

15
7
14L-~~-1~10~------~~~~~

Figure 19. TTUNMOS-to-CMOS Level Converter
Analog Signal Peak-to-Peak Greater than 5 V
(Also see HC4316A)

CHANNEL 4

. CHANNEL3
COMMON 110
CHANNEL 2

CHANNEL 1

INPUT

10F4
SWITCHES

>----4>-- OUTPUT

1-.....,.--1
rO.0 1 /1F

1
2
3 4
CONTROL INPUTS

Figure 20. 4-lnput Multiplexer

High-Speed CMOS Logic Data
DL129-Rev6

Figure 21. SamplelHold Amplifier

3-661

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4075

Triple 3-lnput OR Gate
High-Performance Silicon-Gate CMOS
The MC74HC4075 is identical in pinout to the MC14075B. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 ~A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: 42 FETs or 10.5 Equivalent Gates

DSUFFIX
sOle PACKAGE
CASE 751A-03

ORDERING INFORMATION

MC74HCXXXXN
MC74HCXXXXD

Plastic
SOIC

LOGIC DIAGRAM
PIN ASSIGNMENT

Al 1

Bl~Yl
Cl~

At[ 1-

14

Bl [ 2

13 ~ C3

A2 [ 3

12 ~ B3

A2 3

B2 [ 4

11 pA3

C2 [ 5

10

B2~Y2
C2~

oVcc

PY3

9 ~ Yl

Y2 [ 6
GND [ 7

8

~ Cl

A3 11

B3~Y3

C3~

FUNCTION TABLE

PIN 14= Vcc
PIN 7 = GND

Inputs

10195

© Motorola, tnc. 1995

3-662

REV6

Output

A

B

C

y

L
H
X
X

L
X
H
X

L
X
X
H

L
H
H
H

®

MOTOROLA

MC74HC4075
MAXIMUM RATINGS'
Symbol

Value

Unit

-0.5 to + 7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

V

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

mA

lout

DC Output Current, per Pin

±25

mA

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

-65 to + 150

°c

VCC
Yin
Vout

Tstg
TL

Parameter
DC Supply Voltage (Referenced to GND)

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND s; (Vin or Vout) s; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW;oC from 65° to 125°C
SOIC Package: - 7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol
VCC
Yin, Vout

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC~2.0V
VCC ~ 4.5 V
VCC~

6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VIH

VIL

VOH

Parameter

Test Conditions

lin

s; 85°C

s; 125°C

Unit

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

Vout~0.1

Maximum Low-Level Input
Voltage

Vout~0.1

VorVcc-0.1 V
"outl s; 20 IlA

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin ~ VIH or VIL
"outl S; 20 j.IA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

"outl

S;

VorVcc-0.1 V
20 IlA

Maximum Low-Level Output
Voltage

"outl s; 4.0 mA
"outl s; 5.2 mA

Yin ~ VIH or VIL
"outl S; 20 IlA
Yin ~ VIH or VIL

ICC

-55to
25°C

Minimum High-Level Input
Voltage

Yin ~ VIH or VIL
VOL

VCC
V

"outl S; 4.0 mA
"outl s; 5.2 mA

V

Maximum Input Leakage Current

Yin ~ VCC or GND

6.0

±0.1

± 1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Yin ~ VCC or GND
lout~ 0 IlA

6.0

2

20

40

j.IA

NOTE: Information on typical parametric values can be found

High-Speed CMOS Logic Data
DL129-Rev6

In

Chapter 2.

3-663

MOTOROLA

MC74HC4075
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25"e

s; 85"e

s; 125"e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

115
23
20

145
29
25

175
35
30

ns

trLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical

@

25°e, Vee = 5.0 V

Power Dissipation Capacitance (Per Gate)"

26

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

TEST POINT
OUTPUT

-VCC

INPUT
A,BORC

DEVICE
UNDER
TEST

" " - - - - - GND

OUTPUTY
ITHL

Figure

• Includes all probe and jig capacitance

1. Switching Waveforms

Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM
(1/3 of the Device)
A---~~"""
B-----J.~/

Y
C-----j

MOTOROLA

3-664

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4078

8-lnput NOR/OR Gate
High-Performance Silicon-Gate CMOS
The MC74HC4078 is similar to the CD4078B metal-gate CMOS device.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
•
•
•
•
•
•
•

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 IlA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 30 FETs or 7.5 Equivalent Gates

DSUFFIX
SOIC PACKAGE
CASE 751A-03

ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXD

Plastic
SOIC

LOGIC DIAGRAM
PIN ASSIGNMENT
A_.;.2_-\
3 _-I
B_.::C_-;,4_-+-__
D_",,5_-\

9
F --!7-----f---

E -'1*"0- - I

o-.......---=-Y

G --;1.;,-1_ - I
H--!l:o,2_-I

x

Y=AtBtCtDtEtFtG+H
X=A+B+C+D+E+F+G+H

X[ 1-

14 ~ VCC

A[ 2

13 OY

B[ 3

12 OH

C[ 4

11 JG

D[ 5

10 OF

NC [ 6

9JE
8

GND [ 7

j

NC

NC = NO CONNECTION

PIN 14=VCC
PIN 7 =GND
PINS 6, 8 = NO CONNECTION

FUNCTION TABLE

10195

© Motorola, Inc. 1995

3-665

REV 6

Inputs A through H

Outputs
y
X

All Inputs L
All Other Combinations

H
L

®

L
H

MOTOROLA

MC74HC4078
MAXIMUM RATINGS·
Symbol
VCC
Yin
Vout
lin

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

mA
mA

·V

lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

mA

PD

Power Dissipation in Still Air

750
500

mW

-65to+150

'c
'c

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND ,;; (Vin or Vout) ,;; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/'C from 65' to 125'C
SOIC Package: - 7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC = 2.0 V
VCC =4.5 V
VCC=6.0V

Min

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

'c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

Vee
V

-55to
25'C

,;; 85'C

,;; 125'C

Unit

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

0.3
0.9
1.2

0.3
0.9
1.2

V

V

VIH

Minimum High-Level Input
Voltage

Vout = 0.1 Vor VCC - 0.1 V
lIoutl ,;; 20 ItA

2.0
4.5
6.0

VIL

Maximum Low-Level Input
Voltage

Vou t=O.1 VorVCC-O.l V
lIoutl ,;; 20 ItA

2.0
4.5
6.0

0.3
0.9
1.2

Minimum High-Level Output
Voltage

Yin = VIH or VIL
Iioutl ,;; 20 ItA

2.0
4.5
6.0

1.9

1.9

1.9

404

404

404

5.9

5.9

5.9

Yin = VIH or VIL lIoutl ,;; 4.0 mA
lIoutl ,;; 5.2 mA

4.5
6.0

3.98

5048

3.84
5.34

3.70
5.20

Yin = VIH or VIL
Iioutl ,;; 20 ItA

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL lIoutl ,;; 4.0 mA
lIoutl ,;; 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

DAD
DAD

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

± 1.0

±1.0

ItA

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 IlA

6.0

2

20

40

IlA

VOH

VOL

lin
ICC

Maximum Low-Level Output
Voltage

NOTE: Information on typical parametric values can be found

MOTOROLA

In

V

Chapter 2.

3--666

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4078
AC ELECTRICAL CHARACTERISTICS (CL

=50 pF, Input tr =tf =6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Any Input to Output Y
(Figures 1 and 3)

2.0
4.5
6.0

130
26
22

165
33
28

195
39
33

ns

tpLH,
tpHL

Maximum Propagation Delay, Any Input to Output X
(Figures 2 and 3)

2.0
4.5
6.0

140
28
24

175
35
30

210
42
36

ns

tTLH,
trHL

Maximum Output Transition Time, Any Output
(Figures 1, 2, and 3)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values ran be found in Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per (Package)'

=5.0 V

29

• Used to determine the no-load dynamic power consumption: Po = CPO VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

SWITCHING WAVEFORMS
tr

-Vcc

:-Vcc
ANY INPUT

11<----GND

1 1 ' - - - - - GND

OUTPUT X
tTLH

tTHL

Figure 1.

Figure 2.

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance
Figure 3. Test Circuit

High-Speed CMOS Logic Data
DL129-Rev6

3-667

MOTOROLA

MC74HC4078
EXPANDED LOGIC DIAGRAM
A ----'~-......
B-----:L_-'

Jr--.,

E ----''--'''-......
F-----:L_-'

x

G

H-----:L_-'

MOTOROLA

3-668

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4316

Quad Analog Switch/
Multiplexer/Demultiplexer with
Separate Analog and Digital
Power Supplies

NSUFFIX
PLASTIC PACKAGE
CASE 648-08

High-Performance Silicon-Gate CMOS
The MC74HC4316 utilizes silicon-gate CMOS technology to achieve fast
propagation delays, low ON resistances, and low OFF-channel leakage
current. This bilateral switch/multiplexer/demultiplexer controls analog and
digital voltages that may vary across the full analog power-supply range
(from VCC to VEE).
The HC4316 is similar in function to the metal-gate CMOS MC14016 and
MC14066, and to the High-Speed CMOS HC4016 and HC4066. Each
device has four independent switches. The device control and Enable inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs. The device has been designed so that the
ON resistances (RON) are much more linear over input voltage than RON of
metal-gate CMOS analog switches. Logic-level translators are provided so
that the On/Off Control and Enable logic-level voltages need only be VCC
and GND, while the switch is passing signals ranging between VCC and VEE.
When the Enable pin (active-low) is high, all four analog switches are turned
off.
o
o
o
o
o
o

o
o

DSUFFIX
SOIC PACKAGE
CASE 7518-05
ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXD

Plastic
SOIC

PIN ASSIGNMENT
XA [ 1.

16

VA [ 2

15 J
14 ]
]
13

VB [ 3

Logic-Level Translator for On/Off Control and Enable Inputs
Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Diode Protection on All Inputs/Outputs
Analog Power-Supply Voltage Range (VCC - VEE) = 2.0 to 12.0 Volts
Digital (Control) Power-Supply Voltage Range (VCC - GND) 2.0 to
6.0 Volts, Independent of VEE
Improved Linearity of ON Resistance
Chip Complexity: 66 FETs or 16.5 Equivalent Gates

XB
BON/OFF
CONTROL
CON/OFF
CONTROL
ENABLE

=

[ 4
[ 5

VCC
A ON/OFF
CONTROL
DON/OFF
CONTROL
XD

12 ] VD

[ 6

11 ]Yc

[ 7

10

GND [ 8

Xc

9 ] VEE

FUNCTION TABLE
LOGIC DIAGRAM

Inputs
On/Off
Enable
Control

XA~l________-.~

L
L
H

A ON/OFF CONTROL 15

H
L

X

State of
Analog
Switch
On
Off
Off

X = don't care

XB --'-l--------4-<--I
ANALOG
OUTPUTS/INPUTS

B ON/OFF CONTROL
XC~10~________~~

PIN 16=VCC
PIN 8=GND
PIN9= VEE

C ON/OFF CONTROL 6

GND~VEE

XD~13~________~~

DON/OFF CONTROL 14
ENABLE
7
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

10195

© Motorola. Inc. 1995

3-669

REV6

®

MOTOROI.A

MC74HC4316
MAXIMUM RATINGS'
Symbol
VCC

Parameter
Positive DC Supply Voltage

(Ref. to GND)
(Ref. to VEE)

Value

Unit

-0.5to+7.0
-0.5 to + 14.0

V

VEE

Negative DC Supply Voltage (Ref. to GND)

-7.0 to + 0.5

V

VIS

Analog Input Voltage

VEE-O.S
to VCC + 0.5

V

Vin
I

DC Input Voltage (Ref. to GND)

PD

Power Dissipation in Still Air

Tstg

Storage Temperature

TL

-1.5to VCC + 1.5

V

±25

mA

750
500

mW

-65to+ 150

'c
'c

DC Current Into or Out of Any Pin
Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high--1mpedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND s (Vin or Vout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.

260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/'C from 65' to 125'C
SOIC Package: -7 mW/'C from 65' to 125'C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

Unit

VC~

Positive DC Supply Voltage (Ref. to GND)

2.0

6.0

V

VEE

Negative DC Supply Voltage (Ref. to GND)

-6.0

GND

V

VIS

Analog Input Voltage

VEE

VCC

V

Vin

Digital Input Voltage (Ref. to' GND)

GND

VIO'

Parameter

Static or Dynamic Voltage Across Switch

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Control or Enable Inputs)
(Figure 10)

VCC=2.0V
VCC=4.5V
VCC=6.0V

VCC

V

-

1.2

V

-55

+125

'c

0
0
0

1000
500
400

ns

• For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out olthe switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted
Guaranteed Limit
Vec
V

-55to
25'C

s 85'C

s 125'C

Unit

VIH

Minimum High-Level Voltage,
Control or Enable Inputs

Ron = Per Spec

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Voltage,
Control or Enable Inputs

Ron = Per Spec

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

lin

Maximum Input Leakage
Current, Control or Enable
Inputs

Vin = VCC or GND
VEE=-6.0V

6.0

±0.1

±1.0

±1.0

IlA

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
VIO=OV

6.0
6.0

2
8

20
80

40
160

Symbol

ICC

Parameter

Test Conditions

IlA
VEE=GND
VEE=-6.0

NOTE: Information on tYPical parametric values can be found In Chapter 2.

MOTOROLA

3-670

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4316
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE)
Guaranteed Limit
-55to
25'C

VCC
V

VEe
V

Vin=VIH
VIS = VCC to VEE
IS :5 2.0 mA (Figures 1, 2)

2.0'
45
4.5
6.0

0.0
0.0
-4.5
-6.0

-

-

-

210
95
75

230
105
85

250
110
90

Vin=VIH
VIS = VCC or VEE (Endpoints)
IS :5 2.0 mA (Figures 1, 2)

2.0
4.5
4.5
6.0

0.0
0.0
-4.5
-6.0

-

-

-

100
80
70

110
90
80

130
100
90

Maximum Difference in "ON"
Resistance Between Any Two
Channels in the Same Package

Vin=VIH
VIS = 1/2 (VCC - VEE)
IS :5 2.0 rnA

2.0
4.5
4.5
6.0

0.0
0.0
-4.5
-6.0

-

-

-

20
15
10

30
25
20

40
30
25

loff

Maximum Off-Channel Leakage
Current, Any One Channel

Vin=VIL
VIO = VCC or VEE
Switch Off (Figure 3)

6.0

-6.0

0.1

0.5

1.0

IlA

Ion

Maximum On-Channel Leakage
Current, Any One Channel

Vin=VIH
VIS = VCC or VEE
(Figure 4)

6.0

-6.0

0.1

0.5

1.0

IlA

Symbol
Ron

!>Ron

Parameter

Test Conditions

Maximum "ON" Resistance

:5 85'C

:5 125'C

Unit

n

n

• At supply voltage (VCC - VEE) approaching 2 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)
Guaranteed Limit
VCC
V

-55to
25'C

:5 85'C

:5 125'C

Unit

tplH,
tpHl

Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)

2.0
4.5
6.0

50
10
10

75
15
13

90
18
15

ns

tpLZ,
tPHZ

Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)

2.0
4.5
6.0

250
50
43

312
63
54

375
75
64

ns

tpZl,
tpZH

Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)

2.0
4.5
6.0

185
53
45

220
66
56

265
75
68

ns

Maximum Capacitance

-

10

10

10

pF

-

35
1.0

35
1.0

35
1.0

Symbol

C

Parameter

ONIOFF Control
and Enable Inputs
Control Input = GND
Analog 1/0
Feedthrough

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'C, VCC = 5.0 V
Power Dissipation Capacitance (Per Switch) (Figure 13)"

15

• Used to determine the no-load dynamic power consumption: PD = CpD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

High-Speed CMOS logic Data
Dl129-Rev6

3-671

MOTOROLA

MC74HC4316
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
VCC
V

VEE
V

Limit"
25°C

2.25
4.50
6.00

-2.25
-4.50
-6.00

150
160
160

MHz

fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Q, CL = 50 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-50
-50
-50

dB

fin = 1.0 MHz, RL = 50 Q, CL = 10 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-40
-40
-40

Vin s 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 Q, CL = 50 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

60
130
200

RL = 10 kn, CL = 19 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

30
65
100

Sine Wave
fin
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Q, CL = 50 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-70
-70
-70

fin = 1.0 MHz, RL = 50 n, CL = 10 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-80
-80
-80

Symbol

Parameter

Test Conditions

BW

Maximum On-Channel Bal)dwidth or
Minimum Frequency Response
(Figure 5)

fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter
Reads-3 dB
RL= 50 Q, CL= 10 pF

-

Off-Channel Feedthrough Isolation
(Figure 6)

-

-

THD

Feedthrough Noise, Control to
Switch
(Figure 7)

Crosstalk Between Any Two
Switches
(Figure 12)

Total Harmonic Distortion
(Figure 14)

==

==

fin = 1 kHz, RL = 10 kQ, CL = 50 pF
THD = THDMeasured - THDSource
VIS = 4.0 Vpp sine wave
VIS = 8.0 Vpp sine wave
VIS = 11.0 Vpp sine wave

Unit

mVpp

dB

%
2.25
4.50
6.00

-2.25
-4.50
-6.00

0.10
0.06
0.04

• Limits not tested. Determined by design and venfied by qualification.

MOTOROLA

3-672

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4316
3000

300,--,---,---.---.--,---,---,--,---.

,i125 ,C

_ 2500
en

fi'j'

::;

::;

I

I

2501---1---I---+---+--+----I---+---1-----l

Q. 2000
w

Q. 200 1---1'---I---+---+--+----I---+---1-----l
w

:z

:z

Q

t;i

Q

1500

Ci.i
w

~
t;o~

t;i

J

a:
:z 1000

a

!

c:

o

a: 500

....o!!!!: ~

a:

I'

I

o~
o 0.25

150 1---I---j----+---+::."c....-t--">ool:---I---I---1

Ci.i
w

25°C

5
~

100~-+~~~~~~~~--~~~~~-i

...
o~~~~--~~~~~~--~~~~

o

0.50 0.75 1.00 1.25
1.5 1.75 2.00
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1a. Typical On Resistance,

Figure 1 b. Typical On ReSistance,
Vee - VEE = 4.5 V

Vee- VEE =2.0 V

160

120

140
fi'j'

::;
I

125°C

120

Q.
w 100
Q

:z
~
en

Ci.i
w

a:
:z

a

c:
0

80
60
40

a:

20

./

,.,-V

",,'1'

r-

V ,.,-

I--

0.5

1.0 1.5 2.0 2.5

r--..... .....
/1-..""
..........
/.i
55 oC' - .

:z
«
>-'
en
w

a:
:z

0.c:

----

V

30

I-'"

20 V

0

a:

r-

3.0 3.5 4.0

4.5 5.0

-

Ci.i

w

a:
:z

a

40

,::
0

a:

20

------ --

o
o

5.5 6.0

V

1.0

2.0

-

=6.0 V

3.0

r--- .........

---

""i-./r-......
55°C

".-~

.......

4.0

5.0

12~oC
-V
..-.V

......

.......25°C

-

""

r-. .......

......r ' ~

Vee-VEE

........

.......

6.0

7.0

8.0

r-- I--

+

r- i--

9.0

=9.0 V

PROGRAMMABLE
POWER
SUPPLY

r-

DC ANALYZER

r---r::::=~ VCC
DEVICE
UNDER TEST

ANALOG IN

10
00

-~/

........

~

Figure 1 d. Typical On ReSistance,

,.."....

40

Ci.i

I'-..

60

./ t-...

125°C

80

Figure 1c. Typical On Resistance,

Q.
Q

w

Q

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

70

50

Q.

:z
~
en

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

fi'j'

w

I

""

80

60

::;

.......

Vee - VEE

I

_ 100
en

r

,//25°C"

o
o

::;

4.5

1.0 2.0 3.0 4.0

5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 1e. Typical On Resistance,

High-Speed CMOS Logic Data
DL129- Rev 6

Figure 2. On Resistance Test Set-Up

3--673

MOTOROLA

MC74HC4316

Vcc
011

Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up

Figure 4. Maximum On Channel Leakage Current,
Test Set-Up

Vcc

VCC
16

TO dB

1-+--......-_--0 METER

fin O-jl-......---lr-l

TOdB

1-+--_-_--0 METER

O.111F

Vcc -=
SELECTED
CONTROL
INPUT

SELECTED
CONTROL
INPUT

'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance.

Figure 5. Maximum On-Channel Bandwidth
Test Set-Up

1-1-..--..--0

Figure 6. Off-Channel Feedthrough Isolation,
Test Set-Up

TEST .
POINT

'------GND

../UL CONTROL _ _ _ _----'
'Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, Control to Analog Out,
Test Set-Up

MOTOROLA

Figure 8. Propagation Delays, Analog In to
Analog Out

3-674

High-Speed CMOS Logic Data
DL129-Rev6

7

MC74HC4316
VCC

16

.Jl...Jl.. _ _+-I

. J - - - - - - - f . . } - - - - VCC

TEST

I-+-~~--o POINT

' - -_ _ _ _ _.J

' 1 - - - - GND

HIGH
IMPEDANCE

SELECTED
VCC
CONTROL t----'
INPUT

'Includes all probe and jig capacitance.

Figure 9. Propagation Delay Test Set-Up

POSITION

-=

G)

POSITION

Figure 10. Propagation Delay, ON/OFF Control
to Analog Out

G) WHEN TESTING tpHZ AND tpZH

CD WHEN TESTING tPLZ AND tpZL

CD

VCC

VCC

1 k.Q

16

t-+--t--o

I

TEST
POINT
TEST
POINT

50PF '

'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance.

Figure 11. Propagation Delay Test Set-Up

N/C----+-I

Figure 12. Crosstalk Between Any Two Switches,
Test Set-Up (Adjacent Channels Used)

TO

I-I----N/C

I--H~---<~--o DISTORTION

METER

VEE

SELECTED
CONTROL
INPUT

nJL CONTROL _ _ _ _- '
'Includes all probe and jig capacitance.

Figure 13. Power Dissipation Capacitance
Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

Figure 14. Total Harmonic Distortion, Test Set-Up

3-675

MOTOROLA

MC74HC4316
0
-10
-20
-30
-40

f-A
I

II

E

76

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4316
+5V

VCC=5V

ANALOG
SIGNALS

I

{=
.=

=

=}A

16

R' R' R' R' R'

~

•

~

~

HC4316

7
5
6
14
15

TIL

-L

AND
~~

CONTROL 9
INPUTS
8

16

ANALOG {
SIGNALS

} ANALOG
SIGNALS

HC4016

VEE =0
TO- 6V

}

R'=2T010kQ

NALOG
SI GNALS

VEE=O
TO-6V

LSTIU
NMOS

~

9

-L

a. Using Pull-Up Resistors

b. Using HCT Buffer
Figure 18. LSTTUNMOS to HCMOS Interface

VcC= 12V
\Rl

12V
POWER
SUPPLY

GND=6 V

?' R2

~

-:!;

VE E=OV

Rl =R2
VCC

~I12Vpp

ANALOG
INPUT
SIGNAL

ANALOG
OUTPUT
SIGNAL

I

C
VEE

~

12V

Rl =R2
R3=R4

Figure 19. Switching a D-to-12 V Signal Using a
Single Power Supply (GND '# 0 V)

CHANNEL 4

CHANNEL 3
COMMON 1/0
CHANNEL 2

CHANNELl

INPUT

1

rO.

2
3 4
CONTROL INPUTS

Figure 20. 4-lnput Multiplexer

High-Speed CMOS Logic Data

DL129-Rev6

>----4- OUTPUT

10F4
SWITCHES
01 !1F

Figure 21. Sample/Hold Amplifier

3-677

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Product Preview

MC74HC4316A

Quad Analog Switch/
Multiplexer/Demultiplexer with
Separate Analog and Digital
Power Supplies

N SUFFIX
PLASTIC PACKAGE
CASE 648-0B

High-Performance Silicon-Gate CMOS
o SUFFIX
SOIC PACKAGE
CASE 751 8-05

The MC74HC4316A utilizes silicon-gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF--channelleakage
current. This bilateral switch/multiplexer/demultiplexer controls analog and
digital voltages that may vary across the full analog power-supply range
(from VCC to VEE).
The HC4316A is similar in function to the metal-gate CMOS MC14016
and MC14066, and to the High-Speed CMOS HC4016A and HC4066A.
Each device has four independent switches. The device control and Enable
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs. The device has been designed so
that the ON resistances (RON) are much more linear over input voltage than
RON of metal-gate CMOS analog switches. Logic-level translators are
provided so that the On/Off Control and Enable logic-level voltages need
only be VCC and GND, while the switch is passing signals ranging between
VCC and VEE. When the Enable pin (active-low) is high, all four analog
switches are turned off.
•
•
•
•
•
•
•
•

OTSUFFIX
TSSOP PACKAGE
CASE 948G-G1
ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT

PIN ASSIGNMENT

Logic-Level Translator for On/Off Control and Enable Inputs
Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Diode Protection on All Inputs/Outputs
Analog Power-Supply Voltage Range (VCC - VEE) 2.0 to 12.0 Volts
Digital (Control) Power-Supply Voltage Range (VCC - GND) 2.0 to
6.0 Volts, Independent of VEE
Improved Linearity of ON Resistance
Chip Complexity: 66 FETs or 16.5 Equivalent Gates

=

Plastic
SOIC
TSSOP

=

LOGIC DIAGRAM

XA [ 1-

16

YA [ 2

15

YB [

3

14

XB [ 4
BONIOFF
CONTROL [ 5
CONIOFF [ 6
CONTROL
ENABLE [ 7

13

VCC
A ON/OFF
CONTROL
DON/OFF
CONTROL
XD

12

YD

11

Yc

10

Xc

GND [ 8

9

VEE

XA~1________-.~

AON/OFF CONTROL 15

FUNCTION TABLE
Inputs
On/Off
Enable
Control

XB -'-ll------...,~
ANALOG
OUTPUTS/INPUTS

B ON/OFF CONTROL

C ON/OFF CONTROL 6

L
L
H

PIN 16= VCC
PIN 8=GND
PIN 9= VEE
GND2!VEE

H
L
X

State of
Analog
Switch
On
Off
Off

X = don't care

DON/OFF CONTROL 14
ENABLE

7
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10195

© Motorola, Inc. 1995

3-678

REVO

®

MOTOROLA

MC74HC4316A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
Positive DC Supply Voltage

(Ref. to GND)
(Ref. to VEE)

Value

Unit

-0.5to + 7.0
-0.5 to + 14.0

V

VEE

Negative DC Supply Voltage (Ref. to GND)

-7.0 to + 0.5

V

VIS

Analog Input Voltage

VEE-0.5
toVCC+0.5

V

Vin

DC Input Voltage (Ref. to GND)

I
PD

Tstg
TL

- 0.5 to VCC + 0.5

V

±25

mA

750
500
450

mW

-65 to + 150

°c

DC Current Into or Out of Any Pin
Power Dissipation in Still Air

Plastic DIPt
SOIC Packaget
TSSOP Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.

°c
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mWrC from 65° to 125°C
TSSOP Package: -6.1 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

Unit

VCC

Positive DC Supply Voltage (Ref. to GND)

2.0

6.0

V

VEE

Negative DC Supply Voltage (Ref. to GND)

-6.0

GND

V

VIS

Analog Input Voltage

VEE

VCC

V

Vin

Digital Input Voltage (Ref. to GND)

GND

VCC

V

-

1.2

V

-55

+ 125

°c

0
0
0
0

1000
600
500
400

ns

VIO'

Parameter

Static or Dynamic Voltage Across Switch

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall lime
(Control or Enable Inputs)
(Figure 10)

VCC=2.0V
VCC=3.0V
VCC=4.5V
VCC=6.0V

• For voltage drops across the sWitch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out olthe switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25°C

s

85°C

s

125°C

Unit

VIH

Minimum High-Level Voltage,
Control or Enable Inputs

Ron = Per Spec

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Voltage,
Control or Enable Inputs

Ron = Per Spec

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

lin

Maximum Input Leakage
Current, Control or Enable
Inputs

Vin = VCC or GND
VEE=-6.0V

6.0

±0.1

±1.0

±1.0

~

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
VIO=OV

6.0
6.0

2
4

20
40

40
160

ICC

IlA
VEE =GND
VEE=-6.0

NOTE: Information on tYPical parametnc values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-679

MOTOROLA

MC?4HC4316A
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE)
Guaranteed Limit
VCC
V

VEE
V

-55to
25°C

Vin=VIH
VIS = VCC to VEE
IS s 2.0 mA (Figures 1, 2)

2.0*
45
4.5
6.0

0.0
0.0
-4.5
-6.0

-

-

-

160
90
90

200
110
110

240
130
130

Vin=VIH
VIS = VCC or VEE (Endpoints)
IS s 2.0 mA (Figures 1, 2)

2.0
4.5
4.5
6.0

0.0
0.0
-4.5
-6.0

-

-

-

90
70
70

115
90
90

140
105
105

Maximum Difference in "ON"
Resistance Between Any Two
Channels in the Same Package

Vin=VIH
VIS = 1/2 (VCC - VEE)
IS s 2.0mA

2.0
4.5
4.5
6.0

0.0
0.0
-4.5
-6.0

-

-

-

20
15
15

25
20
20

30
25
25

loff

Maximum Off-Channel leakage
Current, Any One Channel

Vin=Vll
VIO = VCC or VEE
Switch Off (Figure 3)

6.0

-6.0

0.1

0.5

1.0

IIA

Ion

Maximum On-Channel leakage
Current, Any One Channel

Vin=VIH
VIS = VCC or VEE
(Figure 4)

6.0

-6.0

0.1

0.5

1.0

IIA

Symbol
Ron

ARon

Parameter

Test Conditions

Maximum "ON" Resistance

s 85 D C

S 125 D C

Unit
Q

Q

* At supply voltage (VCC - VEE) approachmg 2 V the analog sWltch-on resistance becomes extremely non-linear. Therefore, for low-voltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2.

AC ELECTRICAL CHARACTERISTICS (Cl = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)
Guaranteed Limit
VCC
V

-55to
25°C

tplH,
tpHl

Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)

2.0
4.5
6.0

40

tpLZ,
tpHZ

Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)

2.0
4.5
6.0

tpZl,
tpZH

Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)
Maximum Capacitance

Symbol

C

Parameter

ON/OFF Control
and Enable Inputs
Control Input = GND
Analog I/O
Feedthrough

s 85 C

S 125 D C

Unit

60
9
8

ns

5

50
8
7

130
40
30

160
50
40

200
60
50

ns

2.0
4.5
6.0

140
40
30

175
50
40

250
60
50

ns

-

10

10

10

pF

-

35
1.0

35
1.0

35
1.0

6

D

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25 D C, VCC = 5.0 V
Power Dissipation Capacitance (Per Switch) (Figure 13)*

15

* Used to determine the no-load dynamic power consumption: Po = CpO VCC 2f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-680

High-Speed CMOS logic Data
Dl129-Rev6

MC74HC4316A
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol

Parameter

Test Conditions

V

VEE
V

Limit'
25'C

BW

Maximum On-Channel Bandwidth or
Minimum Frequency Response
(Figure 5)

fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter
Reads-3dB
RL = 50 n, CL = 10 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

150
160
160

MHz

-

Off-Channel Feedthrough Isolation
(Figure 6)

fin"" Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 n, CL = 50 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-50
-50
-50

dB

fin = 1.0 MHz, RL = 50 n, CL = 10 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-40
-40
-40

Vin s 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 n, CL = 50 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

60
130
200

RL= 10 kn, CL = 10pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

30
65
100

fin"" Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 n, CL = 50 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-70
-70
-70

fin = 1.0 MHz, RL = 50 n, CL = 10 pF

2.25
4.50
6.00

-2.25
-4.50
-6.00

-80
-80
-80

VCC

-

-

THD

Feedthrough Noise, Control to
Switch
(Figure 7)

Crosstalk Between Any Two
Switches
(Figure 12)

Total Harmonic Distortion
(Figure 14)

..

fin = 1 kHz, RL = 10 kn, CL = 50 pF
THD = THDMeasured - THDSource
VIS = 4.0 Vpp sine wave
VIS = 8.0 Vpp sine wave
VIS = 11.0 Vpp sine wave

Unit

mVpp

dB

%

2.25
4.50
6.00

-2.25
-4.50
-6.00

0.10
0.06
0.04

..

, Limits not tested. Determined by design and venfled by qualification .

High-Speed CMOS Logic Data
DL129-Rev6

3-681

MOTOROLA

MC74HC4316A

TBD

TBD

Figure 1a. Typical On Resistance,
Vee-VEE = 2.0 V

Figure 1 b. Typical On Resistance,
Vee - VEE = 4.5 V

TBD

TBD

Figure 1c. Typical On Resistance,
Vee- VEE = 6.0 V

Figure 1d. Typical On Resistance,
Vee- VEE 9.0V

=

PROGRAMMABLE
POWER
SUPPLY

TBD

+

DCANALVZER

r--~:;;::::::;-" VCC
DEVICE
UNDER TEST

ANALOG IN

Figure 1e. Typical On Resistance,

MOTOROLA

Figure 2. On Resistance Test Set-Up

3-682

High-Speed CMOS Logic Data

DL129-Rev6

MC74HC4316A

VCC
011

Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up

Figure 4. Maximum On Channel Leakage Current,
Test Set-Up

VCC
16

TO dB

1-+--......- .....- - 0 METER

fin

0-11--+---1-1
O.1I1F

TO dB

1-+--....--.--0 METER

SELECTED
CONTROL
INPUT

'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance.

Figure 5. Maximum On-Channel Bandwidth
Test Set-Up

Figure 6. Off-Channel Feedthrough Isolation,
Test Set-Up

Vcc
16
TEST

1-+-.....- .....-0 POINT
SELECTED
CONTROL
INPUT

.nn

'------GND

CONTROL _ _ _ _----'

'Includes all probe and jig capacitance.

Figure 7. Feedthrough Noise, Control to Analog Out,
Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

Figure 8. Propagation Delays, Analog In to
Analog Out

3-683

MOTOROLA

MC74HC4316A
VCC

..JL n

16
ANALOG I/O

ENABLE

TEST

I-+-~p------<1_ OUTPUT

10F4
SWITCHES

I

4

0.01 ~F

CONTROL INPUTS

Figure 21. Sample/Hold Amplifier

Figure 20. 4-lnput Multiplexer

MOTOROLA

3--686

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC54/74HC4351
MC54/74HC4353

Analog Multiplexers/
Demultiplexers with
Address Latch
High-Performance Silicon-Gate CMOS

J SUFFIX
CERAMIC PACKAGE
CASE 732-03

The MC54174HC4351, and MC54174HC4353 utilize silicon-gate CMOS
technology to achieve fast propagation delays, low ON resistances, and low
OFF leakage currents. These analog multiplexers/demultiplexers control
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The Channel-Select inputs determine which one of the Analog Inputs/
Outputs is to be connected, by means of an analog switch, to the Common
Output/Input. The data at the Channel-Select inputs may be latched by
using the active-low Latch Enable pin. When Latch Enable is high, the latch
is transparent. When either Enable 1 (active low) or Enable 2 (active high) is
inactive, all analog switches are turned off.
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal-gate CMOS analog
switches.
For multiplexers/demultiplexers without latches, see the HC4051,
HC4052, and HC4053.
•
•
•
•
•
•

Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC - VEE) = 2.0 to 12.0 V
Digital (Control) Power Supply Range (VCC - GND) 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance than Metal-Gate Types

•
•

Low Noise
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
Chip Complexity: HC4351 - 222 FETs or 55.5 Equivalent Gates
HC4353 - 186 FETs or 46.5 Equivalent Gates

•

N SUFFIX
PLASTIC PACKAGE
CASE 738-03

DWSUFFIX
SOIC PACKAGE
CASE 7510-04

20#
1

ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDW

Ceramic
Plastic
SOIC

PIN ASSIGNMENT
MC54174HC4351

=

X4 [ 1.

20

~

VCC

X6 [ 2

19

~

X2

NC[ 3

18 D X1

X[ 4

xl[

5

X5 [ 6
ENABLE 1 [ 7
ENABLE 2 [ 8
VEE [ 9
GND [ 10

17

16
15

~ xo
~ X3
~A

14 D NC
'13 DB

~C
11 ~ LATCH
ENABLE

12

NC =NO CONNECTION

10195

© Motorola, Inc. 1995

3-687

REV6

@ MOTOROLA

MC54/74HC4351 MC54/74HC4353
LOGIC DIAGRAM
MC54f74HC4351
Single-Pole, 8-Position Plus Common Off and Address Latch
XO
Xl
X2
X3
X4
X5
X6
X7

ANALOG
INPUTS/OUTPUTS

15
CHANNEL-5ELECT { A
INPUTS
B
C
LATCH ENABLE
SWITCH { ENABLE 1
ENABLES ENABLE 2

13
12

CHANNEL
ADDRESS
LATCH

11
7

FUNCTION TABLE
MC54f74HC4351
MULTIPLEXER!
DEMULTIPLEXER

Control Inputs

COMMON
OUTPUT/INPUT

Enable

1

ON
Channel
(LE = H)*

Select

2

B

C

A

L
L
L
L
L
L
L
L
H
X

XO
H
L
L
L
H
L
Xl
L
H
H
L
H
L
X2
H
L
H
X3
H
H
H
L
X4
L
H
H
L
H
X5
H
H
H
L
X6
H
H
H
H
X7
X
X
X
X
None
L
X
X
X
None
X = don't care
* When Latch Enable is low, the Channel
Selection is latched and the Channel
Address Latch does not change states.

PIN20= VCC
PIN 9 = VEE
PIN 10=GND
PINS 3,14 = NC

BLOCK DIAGRAM
MC54f74HC4353
Triple Single-Pole, Double-Position Plus Common Off and Address Latch
PIN ASSIGNMENT
Y1 [ 1-

20

YO

2

19

Y

NC

3

18

X

Zl

4

17

~1

Z

5

16

XO

ZO [ 6

15

A

ENABLE 1 [ 7

14

NC

ENABLE 2 [ 8

13

B

VEE [ 9

12

C

GND [ 10

11

LATCH
ENABLE

COMMON
OUTPUT/INPUT

15
CHANNEL-5ELECT { A 13
INPUTS B
12
C
LATCH ENABLE
SWITCH { ENABLE 1
ENABLES ENABLE 2

11
7
8

CHANNEL
ADDRESS
LATCH

PIN20=VCC
PIN9= VEE
PIN 10=GND
PINS 3,14 = NC

VCC

NC = NO CONNECTION

FUNCTION TABLE

NOTE:
This device allows independent control of each switch. Channel-Select
Input A controls the X Switch, Input B controls the Y Switch, and Input C
controls the Z Switch.

Control Inputs
Enable

On
Channel
(LE= H)*

Select

1

2

C

B

A

L
L
L
L
L
L
L
L
H
X

H
H
H
H
H
H
H
H
X
L

L
L
L
L
H
H
H
H
X
X

L
L
H
H
L
L
H
H
X
X

L
H
L
·H
L
H
L
H
X
X

ZO
ZO
ZO
ZO
Z1
Z1
Zl
Zl

YO
YO
Y1
Y1
YO
YO
Yl
Yl
None
None

XO
Xl
XO
Xl
XO
Xl
XO
Xl

X = Don't Care
* When Latch Enable is low, the Channel Selection
is latched and the Channel Address Latch does not
change states.

MOTOROLA

3-688

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4351 MC54174HC4353
MAXIMUM RATINGS·
Symbol
VCC

Parameter
Positive DC Supply Voltage

(Ref. to GND)
(Ref. to VEE)

Value

Unit

- 0.5 to + 7.0
-0.5to 14.0

V

VEE

Negative DC Supply Voltage (Ref. to GND)

-7.0 to + 0.5

V

VIS

Analog Input Voltage

VEE-0.5
toVCC +0.5

V

Vin

DC Input Voltage (Ref. to GND)

I
Po
Tstg
TL

-1.5to VCC + 1.5

V

DC Current Into or Out of Any Pin

±25

rnA

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65to+ 150

°c

Storage Temperature
Lead Temperature, 1 mm from Case for
(Plastic DIP or SOIC Package)
10 Seconds
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
ranges indicated in the Recommended Operating Conditions.
Unused digital input pins must be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused Analog I/O pins may be left
open or terminated. See Applications Information.

"C
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65" to 125"C
Ceramic DIP: -10 mW/"C from 100" to 125"C
SOIC Package: - 7 mW/oC from 65° to 125"C
For high frequency or heavy load considerations, see Chapter 2.
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

Unit

Positive DC Supply Voltage

(Ref. to GND)
(Ref. to VEE)

2.0
2.0

6.0
12.0

V

VEE

Negative DC Supply Voltage

(Ref. to GND)

-6.0

GND

V

VIS

Analog Input Voltage

VEE

VCC

V

Vin

Digital Input Voltage (Ref. to GND)

GND

VCC

V

-

1.2

V

-55

+ 125

"C

0
0
0

1000
500
400

ns

VCC

VIO·

Parameter

Static or Dynamic Voltage Across Switch

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time,
Channel Select or Enable
Inputs (Figure 9a)

VCC = 2.0 V
VCC = 4.5 V
VCC=6.0V

• For voltage drops across the sWitch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25"C

" 85"C

" 125"C

Unit

VIH

Minimum High-Level Input
Voltage, Channel-Select or
Enable Inputs

Ron = Per Spec

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage, Channel-Select or
Enable Inputs

Ron = Per Spec

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

lin

Maximum Input Leakage
Current, Channel-Select or
Enable Inputs

Vin = VCC or GND,
VEE=-6.0V

6.0

±0.1

±1.0

±1.0

llA

ICC

Maximum Quiescent Supply
Current (per Package)

Channel Select = VCC or GND
Enables = Vec or GND
VIS = VCC or GND VEE=GND
VIO=OV
VEE=-6.0

llA
6.0
6.0

2

8

20
80

40
160

NOTE: Information on tYPical parametric values can be found In Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-689

MOTOROLA

MC54/74HC4351 MC54174HC4353
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
Symbol
Ron

Vee
V

VEE
V

-55to
25°C

s 85°C

s 125°C

Unit

=
=

4.5
4.5
6.0

0.0
-4.5
-6.0

190
120
100

240
150
125

280
170
140

Q

=
=

4.5
4.5
6.0

0.0
-4.5
-6.0

150
100
80

190
125
100

230
140
115

=
=

4.5
4.5
6.0

0.0
"':4.5
-6.0

30
12
10

35
15
12

40
18
14

Q

=
=

6.0

-6.0

0.1

0.5

1.0

itA

6.0

-6.0

0.2

2.0

4.0

6.0

-6.0

0.1

1.0

2.0

Parameter

Test Conditions

Maximum "ON" Resistance

Vin VIL or VIH
VIS VCC to VEE
IS s 2.0 rnA (Figures I, 2)
Vin VIL or VIH
VIS VCC or VEE (Endpoints)
IS s 2.0 rnA (Figures I, 2)

ARon

Maximum Difference in "ON"
Resistance Between Any Two
Channels in the Same Package

Vin VIL or VIH
VIS 1/2 (VCC - VEE)
IS s 2.0 rnA

loff

Maximum Off-Channel Leakage
Current, Any One Channel

Vin VIL or VIH
VIO VCC - VEE
Switch Off (Figure 3)

Maximum Off-Channel Leakage
Current, Common Channel
HC4351

Vin VIL or VIH
VIO VCC - VEE
Switch Off (Figure 4)

=
=

HC4353
Ion

Maximum On-Channel Leakage
Current, Channel to Channel
HC4351

=

Vin VIL or VIH
Switch to Switch
(Figure 5)

=VCC -

itA
VEE

HC4353

6.0

-6.0

0.2

2.0

4.0

6.0

-6.0

0.1

1.0

2.0

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr ,;, tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°C

s 85°C

s 125°C

Unit

tPLH,
tpHL

Maximum Propagation Delay, Channel-Select to Analog Output
(Figure 9)

2.0
4.5
6.0

370
74
63

465
93
79

550
110
94

ns

tpLH,
tpHL

Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)

2.0
4.5
6.0

60
12
10

75
15
13

90
18
15

ns

tpLH,
tpHL

Maximum Propagation Delay, Latch Enable to Analog Output
(Figure 12)

2.0
4.5
6.0

325
65
55

410
82
70

485
97
82

ns

tpLZ,
tpHZ

Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)

2.0
4.5
6.0

290
58
49

365
73
62

435
87
74

ns

tpZL,
tPZH

Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure Ii)

2.0
4.5
6.0

345
69
59

435
87
74

515
103
87

ns

Cin

Maximum Input Capacitance

10

10

pF

Maximum Capacitance Analog I/O

-

10

CI/O

35

35

35

pF

130
50

130
50

130
50

1.0

1.0

1.0

Symbol

Parameter

Enable 1 = VIH, Enable 2 = VIL

Common Oil: HC4351
HC4353

-

Feedthrough
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.

Typical @ 25°C, Vee
CpO

Power Dissipation Capacitance (Per Package) (Figure 14)'

45 (HC4351)
45 (HC4353)

=5.0 V
pF

'Used to determine the no-load dynamiC power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.

MOTOROLA

3-,690

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4351 MC54/74HC4353
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25"e

:s 85"e

:s 125"e

Unit

tsu

Minimum Setup Time, Channel-Select to Latch Enable
(Figure 12)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Latch Enable to Channel Select
(Figure 12)

2.0
4.5
6.0

0
0
0

0
0
0

0
0
0

ns

tw

Minimum Pulse Width, Latch Enable
(Figure 12)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

Maximum Input Rise and Fall Times, Channel-Select, Latch Enable,
and Enables 1 and 2

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

t r, tf

Parameter

NOTE: InformatIon on tYPIcal parametnc values can be found In Chapter 2.

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
Limit'
Symbol

Parameter

Test Condition

BW

Maximum On-Channel Bandwidth or
Minimum Frequency Response
(Figure 6)

fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter
Reads-3 dB
RL = 50 n, CL = 10 pF

Off-Channel Feedthrough Isolation
(Figure 7)

fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 n, CL = 50 pF

-

Feedthrough Noise, Channel Select
Input to Common 0/1
(Figure 8)

Vin :s 1 MHz Square Wave
(tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
Enable=GND
RL = 600 n, CL = 50 pF
RL = 10 kQ, CL = 10 pF

-

Crosstalk Between Any Two Switches
(Figure 13)
(Test does not apply to HC4351)

Total Harmonic Distortion
(Figure 15)

-2.25
-4.50
-6.00

fin = 1 kHz, RL = 10 kn, CL = 50 pF
THD = THDMeasured - THDSource
VIS = 4.0 Vpp sine wave
VIS = 8.0 Vpp sine wave
VIS = 11.0 VPP sine wave

Unit

51

52

53

80
80
80

95
95
95

120
120
120

MHz

dB
2.25
4.50
6.00

-2.25
-4.50
-6.00

-50
-50
-50

2.25
4.50
6.00

-2.25
-4.50
-6.00

-40
-40
-40
mVpp

2.25
4.50
6.00

-2.25
-4.50
-6.00

25
105
135

2.25
4.50
6.00

-2.25
-4.50
-6.00

35
145
190

==

fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 n, CL = 50 pF

fin = 1 MHz, RL = 50 n, CL = 10 pF

THD

2.25
4.50
6.00

25"C
54174HC

VEE
V

==

fin = 1.0 MHz, RL = 50 Q, CL = 10 pF

-

VCC
V

dB
2.25
4.50
6.00

-2.25
-4.50
-6.00

-50
-50
-50

2.25
4.50
6.00

-2.25
-4.50
-6.00

-60
-60
-60

%
2.25
4.50
6.00

-2.25
-4.50
-6.00

0.10
0.08
0.05

• Limits not tested. Determined by design and verified by qualification.

High-Speed CMOS Logic Data
DL129-Rev6

3-691

MOTOROLA

MC54n4HC4351 MC54n4HC4353

en

::;:

:r
Q.

.,
w

250
200

0

z

en

Ci:i
w

150

c::

z

c:

c::"
0

~

100

,/

.J.
. ~'

f-- ~

50 ~-

en

A /\
~.t..,4 ~

::;:

,

:r
Q.

. /v'

"

w

en

",,~25OC-

Ci:i
w

0.75

z

"'~55°C

1.0

1.25

1,5

1.75

2.0

60

c::

0

C
0
c::

I

0.50

~

z

'

",,'

80

0

I

~-'

0,25

.,

I~ ~125°C

(jY

100

40

en

.,
w

0

z

-

en

60

c::

z

45

c::"

30

Ci:i
w

[3]

75

- - - --

0

0

~'

',.......

..-

~-

..... " ~-:-

--

--

en

::;:

:r
Q.

-..... .,
-2t-:

60

z

~
45

en

~C"

Ci:i
w

c::
z

0

C
0
c::

0.5 1,0 1.5 2,0 2,5 3,0 3,5 4,0 4,5 5.0 5.5 6.0

70

:r
Q.

60

0

50

en

40

c::
z

30

c::"

20

.,
w

z

Ci:i
w

c:
0

r-1--

-

-

-

..!-'

'-

1.5

2.0

2,5

3,0

3,5

4,0

4,5

30

f..-

125°C

...

--

-

.",..-1-

-

25°C

'~

---

I - - .. <-;5:c ....

15
2,0

3,0

4,0

5,0

6.0

7.0

Figure 1d. Typical On Resistance, Vee - VEE

12~oC

PROGRAMMABLE
POWER
SUPPLY

-

..-

--j.-55°C-

8.0

9,0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1c. Typical On Resistance, Vee - VEE = 6.0 V

en

1.0

--

1.0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

::;:

1--

-~

75

w

0

15

o

--

Figure 1 b. Typical On Resistance, Vee - VEE = 4.5 V

12koc

~

r-- 1--

- ~
--

..--f--

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

105
90

-"'"

f-- I-""

0,5

2,25

Figure 1a. Typical On Resistance, Vee.., VEE = 2.0 V

::;:

..

~i~

~-

20

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

:r
Q.

,

,,' ,.

- --V

,.-

-21;

DC ANALYZER

+

~-ts:c

=9.0 V

,.-----I==:::::;-- VCC
DEVICE
UNDER TEST

10

ANALOG IN

o

1,0 2.0 3,0 4.0 5,0 6.0 7,0 8,0 9.0 10.0 11.0 12.0
GND

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1e. Typical On Resistance, Vee - VEE = 12.0 V

MOTOROLA

3-692

Figure 2. On Resistance Test Set-Up

High-Speed CMOS Logic Data

DL129-Rev6

MC54/74HC4351 MC54/74HC4353

Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set-Up

Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set-Up

Vee
,..-------:.

Vee

Vas
dB
METER

t-t----o

N/e

RL

'Includes all probe and jig capacitance.

Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set-Up

Vee

,..------,
0.1 J.lF
fin

Figure 6. Maximum On Channel Bandwidth,
Test Set-Up

Vas
dB

o--j 1--+---+-1

METER

TEST

.-.+_-----<_-0 POINT

RL

7
B
9
10

Vee
Vin $ 1 MHz

7
B
9
10

Vee
11

tr =tf = 6 ns
VeennVEE
GND
----~e~H~AN~N~EL~S~E~LE~e~T~
'Includes all probe and jig capacitance.

'Includes all probe and jig capacitance.

Figure 7. Off Channel Feedthrough Isolation,

Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set-Up

Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

3-693

MOTOROLA

MC54174HC4351 MC54174HC4353

TEST

t - t - -......-o POINT
Vcc
CHANNEL SELECT

-"'1/-\:..=--..:1-/1=---- GND

n.n..

ANALOG OUT

_-.","::"=::-::=.-:==-.....J

CHANNEL SELECT
'Includes aU probe and jig capacitance.

Figure 9a. Propagation Delays, Channel Select
to Analog Out

Figure 9b. Propagation Delay, Test Set-Up Channel
Select to Analog Out

Vcc

n.n..
ANALOG
IN

20
ANALOG 1/0

Hf---..--o

-Vcc
,

TEST
POINT

Vcc

7
B
9
10

'-------GND

'Includes aU probe and jig capacitance.

Figure 10b. Propagation Delay, Test Set-Up
Analog In to Analog Out

Figure 10a. Propagation Delays, Analog In to
Analog Out

POSITION

CD
®
VCC

POSITION

CD WHEN TESTING tPHZ AND tpZH
® WHEN TESTING tPLZ AND tpZL

"::"

Vcc

VCC

ENABLE

20

1kll

GND

ANALOG
OUT

HIGH
IMPEDANCE

n.n..

ANALOG
OUT

Figure 11a. Propagation Delay, Enable 1 or 2
to Analog ,Out

MOTOROLA

ENABLE

7
B
9,
10

:r

TEST
POINT
CL'

Figure 11b. Propagation Delay, Test Set-Up
Enableto Analog Out

3-694

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4351 MC54/74HC4353

-vCC

CHANNEL
SELECT

TEST

.-+--_--0 POINT

-GND
-VCC
LATCH
ENABLE 2

-GND

COMMONO!I

50%
CHANNEL SELECT
'Includes all probe and jig capacitance.

Figure 12a. Propagation Delay, Latch Enable to
Analog Out

Figure 12b. Propagation Delay, Test Set-Up
Latch Enable to Analog Out

CHANNEL SELECT

'Includes all probe and jig capacitance.

Figure 13. Crosstalk Between Any Two
Switches, Test Set-Up

Figure 14. Power Dissipation Capacitance,
Test Set-Up

o
-10

VIS

-20

O.IIlF

~n

o-jr-.....,H

TO

-30

I-HP"--'--o DISTORTION

-40

METER

!g -50

I

,
A~F~NDAJENTA~FREciuENC~
,
,
,
,

II
--

-60

7
8
9
10

\

-70

--

-80
_I

1.0

--

-

,

- 'j - -

,

--

- -

DEVICE

--

--

iC-- SOURCE
All
It
W'~ILAJAJ1 ,hJlIw
IT W1\1\. WI,
r ,

V iI\

-90

'Includes all probe and jig capacitance.

t-

A

r

II .,

2.0

~, ""If'

·"1'_

3.125

FREQUENCY (kHz)

Figure 15a. Total Harmonic Distortion, Test Set-Up

High-Speed CMOS Logic Data
DL129-Rev6

Figure 15b. Plot, Harmonic Distortion

3-695

MOTOROLA

MC54174HC4351 MC54174HC4353
APPLICATIONS INFORMATION

ever, tying unused analog inputs and outputs to Vee or GNO
through a low value resistor helps minimize crosstalk and
feedthrough noise that may be picked up by an unused
switch.
Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that:

The Channel Select and Enable control pins should be at
Vee or GNO logic levels. Vee being recognized as a logic
high and GNO being recognized as a logic low. In this
example:
Vee

=+ 5 V =logic high
=0 V =logic low

=2 to 6 volts
GND =0 to- 6 volts

Vee - GNO

GNO

VEE -

The maximum analog voltage swings are determined by
the supply voltages Vee and VEE. The positive peak analog
voltage should not exceed Vee. Similarly, the negative peak
analog voltage should not go below VEE. In this example, the
difference between Vee and VEE is ten volts. Therefore, using the configuration in Figure 16, a maximum analog signal
of ten volts peak-te-peak can be controlled. Unused analog
inputs/outputs may be left floating (i.e., not connected). How-

Vee - VEE = 2 to 12 volts
and VEE

s GNO

When voltage transients above Vee and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Ox) are recommended as shown in
Figure 17. These diodes should be able to absorb the maximum anticipated current surges during clipping.

VCC

+5V- ~ ANALOG
-5V-

-U

Ox

Ox

Ox

Ox

SIGNAL

+5V
7
8
9
10

15
13

}

12

11

TO EXTERNAL CMOS
CIRCUITRY
oTO 5 V DIGITAL
SIGNALS

9
10

-5V

Figure 16. Application Example

Figure 17. External Germanium or
Schottky Clipping Diodes

+5V
+5V-~

VEE-

-U

ANALOG
SIGNAL

VCC

7
8
9
10

1-4-1-H LSTIUNMOS
1-----4>--H CIRCUITRY

'2ksRs.10k

a. Using Pull-Up Resistors

b. Using HCT Interface

Figure 18. Interfacing LSTTUNMOS to CMOS Inputs

MOTOROLA

3--696

High-Speed CMOS Logic Data

DL129-Rev6

MC54/74HC4351 MC54/74HC4353
FUNCTION DIAGRAM HC4351

+-IOI--X2

...--..........r - -

X3

X4

X5

LATCH 11
ENABLE

ENABLE 1 -'----
(.') -15
LJ.J

~

SINK CURRENT
25

I

TYPI6AL
TA·25°C

TA·25"C-= '=-

/'
/ \ V-

TA·85"C

I

20

LJ.J

a:
a:
=>
(.')

TA • 125"C - I - -

I I
5l -10 I / V/ '''l\
~
I I
5
I /~ V
EXPECTED MINIMUM' ~
o -5 II 1/
o I//J
I L
",
I I
4

oS

fZ

I

~V

I

=>

«

~

I

15

I

""

z
1i.i
f-

=>

"f-

I--

=>
0

0

lO

I
I

I~

"

2

VO, OUTPUT VOLTAGE (VOLTS)

/

f

TYPICAL
TA·25°C
TA = 25"C

~

-

TA·85°C

,/ k 1'\

TA·125"C-

~ ~ ~ ,\
~
~

i

[' EXiECTEi MINllUM' 2

4

VO, OUTPUT VOLTAGE (VOLTS)

• The expected minimum curves are not guarantees, but are design aids.

High-Speed CMOS Logic Data

DL129-Rev6

3-703

MOTOROLA

MC74HC4511
EXPANDED LOGIC DIAGRAM

LE

5

A 7

B 1

DATA

A

LE

A

DATA

B

LE

B

[3]
e
C 2

D 6

MOTOROLA

DATA

C

LE

C

DATA

DI----+-+-...J

LE

D1 > - - - - - - - - 1

~704

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4511

Liquid-Crystal Display (LCD) Readout

Incandescent Readout

TYPICAL VALUES
RS=1 MQ
RT=100kn
CT= 0.01 ilF
RS

APPROPRIATE
VOLTAGE

HC4511

LED Readout

OUTPUT

COMMON
CATHODE LED
HC4511
OUTPUT

<
~,

\\-

Gas Discharge Readout

f---

APPROPRIATE
VOLTAGE

.....

VCC

HC4511

OUTPUT

COMMON
ANODE LED
HC4511

Figure 7. Connections to Various Display Readouts

High-Speed CMOS Logic Data
DL129-Rev6

3-705

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC4514

1-of-16 Decoder/Demultiplexer
with Address Latch
High-Performance Silicon-Gate CMOS
The MC74HC4514 is identical in pinout to the MC14514B metal-gate
CMOS device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors; they are compatible with LSTTL outputs.
This device consists of a 4-bit storage latch with a Latch Enable and Chip
Select input. When a low signal is applied to the Latch Enable input, the
Address is stored, and decoded. When the Chip Select input is high, all
sixteen outputs are forced to a low level.
The Chip Select input is provided to facilitate the chip-select, demultiplexing, and cascading functions.
The de multiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using the Chip Select as a
data input.

~-

NSUFFIX
PLASTIC PACKAGE
CASE 724-03

1

24#
1

DWSUFFIX
SOIC PACKAGE
CASE 751E-04

ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXDW

.,
•
•
•
•
•

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input,Current: 1j!A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No.7A
• Chip Complexity: 268 FETs or 67 Equivalent Gates

Plaslie
SOIC

PIN ASSIGNMENT
LATCH
ENABLE

AO
A1

Vee
CHIP
SELECT
A3

Y7

A2

Y6

Y10
Y11

LOGIC DIAGRAM

BINARY
ADDRESS
INPUTS

r'
A1

3
21

A2

4-BIT
STORAGE
LATCH

4-T0-16
LINE
DECODER

A3

LATCH
ENABLE

1

11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15

YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15

Y4

Y8

Y3

Y9

Y1

Y14

Y2

Y15

YO

Y12

GND

Y13

ACTIVE-l-IIGH
OUTPUTS

CHIP
SELECT
PIN 24= VCC
PIN 12=GND

10195

© Motorola, Inc. 1995

3-706

REV 6

®

MOTOROI.A

MC74HC4514
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA
rnA

lin
lout

DC Output Current, per Pin

±25

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500

mW

-65 to + 150

°c

Tstg
TL

Plastic DIPt
SOIC Packaget

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVout) s VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Ret;ommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/"C from 65° to 125"C
SOIC Package: -7 mW/"C from 65" to 125"C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Min

Max

Unit

DC Supply Voltage (Referenced to GND)

Parameter

2

6.0

V

DC Input Voltage, Output Voltage (Referenced to GND)

0

VCC

V

-55

+ 125

"C

0
0
0

1000
500
400

ns

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
V

-55to
25"C

s 85"C

s 125"C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=0.1 VorVcc-0.1 V
1I0uti s 20 j.LA

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout = 0.1 Vor VCC-0.1 V
1I0uti s 2Ol1A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20 j.LA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

4.5
6.0

3.9B
5.4B

3.84
5.34

3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

VOH

Yin = VIH or VIL 1I0uti
1I0uti
VOL

Maximum Low-Level Output
Voltage

Yin = VIH or VIL
1I0uti s 20 j.LA
Yin = VIH or VIL 1I0uti
1I0uti

lin
ICC

s 4.0 mA
s 5.2 mA

s 4.0 rnA
s 5.2 mA

V

Maximum Input Leakage Current

Vin = VCC or GND

6.0

±0.1

±1.0

± 1.0

j.LA

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = 0 j.LA

6.0

8

80

160

I1A

NOTE: Information on tYPical parametric values can be found

High-Speed CMOS Logic Data
DL129-Rev6

In

Chapter 2.

3--707

MOTOROLA

MC74HC4514
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol

Parameter

Vee
V

-55to
25°e

s

05°e

s

125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Chip Select to Output Y
(Figures 1 and 5)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLH

Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 5)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

Maximum Output Transition Time, Any Output
(Figures 1 and 5)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

tpHL

tpLH

Maximum Propagation Delay, Latch Enable to Output Y
(Figures 3 and 5)

tpHL

trLH,
trHL
Cin

ns

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Package)'

=5.0 V

70

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

tsu

Minimum Setup Time, Input A to Latch Enable
(Figure 4)

2.0
4.5
6.0

100
20
17

125
25
21

150
30
26

ns

th

Minimum Hold Time, Latch Enable to Input A
(Figure 4)

2.0
4.5
6.0

5
5
5

5
5
5

5
5
5

ns

tw

Minimum Pulse Width, Latch Enable
(Figure 3)

2.0
4.5
6.0

80
16
14

100
20
17

120
24
20

ns

tr,tf

Maximum Input Rise and Fall Times
(Figure 1)

2.0
4.5
6.0

1000
500
400

1000
500
400

1000
500
400

ns

Symbol

Parameter

s

05°e

s

125°e

Unit

NOTE: Information on tYPical parametric values can be found in Chapter 2.

MOTOROLA

3-708

High-Speed CMOS Logic Data
DL129- Rev 6

MC74HC4514
SWITCHING WAVEFORMS

..I:-----VCC
CHIP
SELECT

VCC

INPUT A

GND
OUTPUTY

1PLH:F
----'f

OUTPUTY

trHL

50%

Figure 2.

Figure 1.

VCC
INPUT A

LATCH
ENABLE

GND
LATCH
ENABLE

OUTPUTY

'-------GND

Figure 4.

Figure 3.

TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 5. Test Circuit

High-Speed CMOS Logic Data
DL129-Rev6

3-709

MOTOROLA

MC74HC4514
FUNCTION TABLE

PIN DESCRIPTIONS

Latch
Enable

Chip
Select

A3

A2

A1

AO

Selected
Output
(High)

H
H
H
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

YO
Y1
Y2
Y3

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

Y4
Y5
Y6
Y7

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

YB
Y9
Y10
Y11

H
H
H
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

Y12
Y13
Y14
Y15

X

H

X

X

X

X

All
Outputs: L

L

L

X

X

X

X

Latched
Data

Address Inputs

ADDRESS INPUTS
AO, A1, A2, A3 (Pins 2, 3, 21, 22)
Address Inputs. These inputs are decoded to produce a
high level on one of 16 outputs. The inputs are arranged
such that A3 is the most-significant bit and AO is the leastsignificant bit. The decimal equivalent of the binary input
address indicates which of the 16 data outputs, YO- Y15, is
selected.
OUTPUTS
YO - Y15 (Pins 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14,
13,16,15)
Active-High Outputs. These outputs produce a high level
when selected (Latch Enable H, Chip Select L) and are at
a low level when not selected.

=

=

CONTROL INPUTS
Latch Enable (Pin 1)
Latch Enable Input. A low level on this input stores the
data on the Address data inputs in the 4-bit latch. A high
level on the Latch Enable input makes the latch transparent
and allows the outputs to follow the inputs. Note that the data
is latched only while the Latch Enable input is at a low level.
Chip Select (Pin 23)
Chip Select Input. A high on this input produces a low level
on all outputs, regardless of what appears at the address or
Latch Enable inputs. A low level on the Chip Select input
allows the selected output to produce a high level.

TIMING DIAGRAM

INPUT A

LATCH ENABLE

CHIP SELECT

OUTPUTY

MOTOROLA

n

_-----'

'---_In U

3-710

1

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4514
EXPANDED LOGIC DIAGRAM

AO 2

DATA

01-----,

LE

A1 ....:3:..-_-1--1

LE

A2 21

[3]

LE

A3 22

LATCH 1
ENABLE

LE

0

CHIP 23
SELECT

High-Speed CMOS Logic Data
DL129-Rev6

3-711

MOTOROLA

MC74HC4514
MICROPROCESSOR MEMORY DECODING

YO

A12

CHIP
SELECT

A11

A3

A10

A2

....

A9

A1

:2

AB

AD

'"
'"

::;;

<:>

+V

LATCH
ENABLE

OOOO-OOFF
01 00-01 FF
0200-02FF
0300-03FF
0400-04FF
0500-05FF
0600-06FF
0700-07FF
OBOO-OBFF
090D-09FF
OAOO-OAFF
OBOO-OBFF
OCOO-OCFF
ODOO-ODFF
OEOO-OEFF
OFOO-OFFF
TO DEVICE SELECTS

YO
HC04

A2

....
....

;;;
<.>

:2

A1

[3]

AO

+V

MOTOROLA

LATCH
ENABLE

3-712

Y11
Y12
Y13
Y14
Y15

100D-1 OFF
110D-11FF
1200-12FF
130D-13FF
140D-14FF
150D-15FF
160D-16FF
170D-17FF
1BOD-1BFF
190D-19FF
1AOD-1AFF
1BOO-1BFF
1COD-1CFF
1D0D-1DFF
1EOO-1EFF
1FOD-1FFF

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC4514
CODE TO CODE CONVERSION -

HEXADECIMAL TO BCD

ttV
A3

'"
..,.
'"
'"

YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7

::;;

ya

-

A2. A1

-

AD

0

C3

LATCH
ENABLE - - <

CHIP
SELECT - - <

.....,....
r-t...
r-t...
~
~

....,..

Y9
Y10
Y11
Y12
Y13
Y14
Y15

~

.......
r"lIf.

r-t...
r"lIf.

....,..

.......

.b

""'.......

r"lIf.

.......
....,..

I-I
1=1 ==
=-

I
I

.......

.......
r"lIf.

~ ~ ~

r-t...

COMMON CATHODE LEDs

.b

R=2k

.......
""'-

rL

~GND

-

"

,/
.........
,/

..AA.
,A

A3
ALLDIOD ESGENERAL
PURPOS EGERMANIUM

'v

L

R= 10 k

-=

High-Speed CMOS Logic Da1a
DL129-Rev6

---{)

Xli
= -= = -=

A2.

..,.

U;
0

A1

::;;
,A

AO

R=2kn

V
HC4050

3-713

HC4050

MOTOROLA

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

I MC54/74HC4538A I

Dual Precision
Monostable Multivibrator
(Retriggerable, Resettable)

JSUFFIX
CERAMIC PACKAGE
CASE 620-10

The MC54fl4HC4538A is identical in pinout to the MC14538B. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the positive
or. the negative edge of an input pulse, and produces a precision output
pulse over a wide range of pulse widths. Because the device has conditioned
trigger inputs, there are no trigger-input rise and fall time restrictions. The
output pulse width is determined by the external timing components, Rx and
C x . The device has a reset function which forces the Q output low and the Q
output high, regardless of the state of the output pulse circuitry.

N SUFFIX
PLASTIC PACKAGE
CASE 648--08

DSUFFIX
SOIC PACKAGE
CASE 7518--05

•
•

Unlimited Rise and Fall Times Allowed on the Trigger Inputs
Output Pulse is Independent of the Trigger Pulse Width
• ± 10% Guaranteed Pulse Width Variation from Part to Part (Using the
Same Test Jig)
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 IlA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
.
•

ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD

PIN ASSIGNMENT
GND [ 1-

Chip Complexity: 145 FETs or 36 Equivalent Gates

16 ] VCC

CXllRX1 [ 2

15 ] GND

RESET 1 [ 3

14 ] CX2lRX2

A1[ 4

13 ] RESET 2

B1[ 5

12 ] A2

LOGIC DIAGRAM

I--..--,\M-VCC

01[ 6

11 ] B2

QT[ 7

10 ] 02

GND [ 8

9] 02

6 01

TRIGGER{ A1
INPUTS B1

I - - . . - - ' \ M - VCC

FUNCTION TABLE

RESET 1...:..-----'

Inputs

TRIGGER { A2
INPUTS
B2

10

02

1---"--02

RESET 2 ..,!1::,.3_ _ _---J

A

B

Q

Q

H
H

..r

H

L

"\..

SL
SL

"lS"
"lS"

H
H

X
H

L
X

L

"\.. ..r

10195

3-714

Outputs

Reset

H
H

PIN 16= VCC
PIN B=GND
RX AND Cx ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND

© Motorola, Inc. 1995

Ceramic
Plastic
SOIC

REV 6

L,H,"\..
L
X
X

H
L,H,..r
X
X

Not Triggered
Not Triggered
Not Triggered
Not Triggered
L
H
Not Triggered

®IfIIOTOROLA

MC54/74HC4538A
MAXIMUM RATINGS'
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

- 1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

lin

DC Input Current, per Pin

lout

A, B, Reset
Cx,R x

±20
±30

mA

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

Po

Power Dissipation in Still Air, Plastic or Ceramic DIPt
SOIC Packaget

750
500

mW

-65 to + 150

°c

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ,; (Vin or Vout) ,; VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°c
260
300

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
Ceramic DIP: -10 mW/oC from 100° to 125°C
SOIC Package: -7 mWrC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Parameter

Min

DC Supply Voltage (Referenced to GND)

Max

Unit

3.0"

6.0

V

0

VCC

V

-55

+ 125

°c

VCC=2.0V
VCC=4.5V
VCC = 6.0 V

0
0
0

1000
500
400

ns

A or B (Figure 5)

-

Rx

External Timing Resistor

VCC < 4.5 V
VCC? 4.5V

1.0
2.0

Cx

External Timing Capacitor

Symbol
VCC
Vin, Vout

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 7)

0

No Limit

··
·

kfl
IlF

'The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx , the leakage of the HC4538A, and leakage due to
board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 IlF/1.0 Mfl. Values of C x > 1.0 IlF
may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise Signals may occur for
Rx> 1.0Mfl.
"The HC4538A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V.
NOTE: Information on typical parametric values can be found in Chapter 2.

High-Speed CMOS Logic Data
DL129-Rev6

3-715

MOTOROLA

MC54/74HC4538A
DC CHARACTERISTICS FOR THE MC54174HC4538A
Guaranteed Limits

Symbol

Parameter

Test Conditions

-55to
25°C

VCC
Volts

Min

1.5
3.15
4.2

Max

s 85°C
Max

Min

s 125°C
Min

VIH

Minimum High-Level
Input Voltage

Vout=0.1 VorVCC-O.l V
"outl s 20 !lA

2.0
4.5
6.0

VIL

Maximum Low-Level
Input Voltage

Vout = 0.1 VorVCC -0.1 V
'''outl s 20!lA

2.0
4.5
6.0

VOH

Minimum High-Level
Output Voltage

Vin = VIH or VIL
"outl s 20!lA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

Vin = VIH or VIL
"outl s -4.0 mA
"outl s -5.2 mA
VOL

Maximum Low-Level
Output Voltage

1.5
3.15
4.2

Max

1.5
3.15
4.2

V

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

V

II

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL
"outl s 4.0 mA
"outl s 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Vin = VIH or VIL
"outl s 20 !lA

Unit

V

lin

Maximum Input
Leakage Current
(A, B, Reset)

Vin = VCC or GND

6.0

±0.1

±1.0

± 1.0

!lA

lin

Maximum Input
Leakage Current
(Rx,Cx)

Vin = VCC or GND

6.0

±50

±500

±500

nA

ICC

Maximum Quiescent
Supply Current
(per package)
Standby State

Vin = VCC or GND
01 and 02 = Low
lout=OflA

6.0

130

220

350

!lA

ICC

Maximum Supply Current
(per package)
Active State

Vin = VCC or GND
01 and 02 = High
lout=O flA
Pins 2 and 14 = 0.5 VCC

MOTOROLA

6.0

3-716

25°C

- 45°C to
85°C

I

I

400

600

-55°C to
125°C

I

800

flA

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4538A
AC CHARACTERISTICS FOR THE MC54174HC4538A (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limits
-55 to
25°C
Vee
Volts

:5 85°C

:5 125°C

Max

Unit

tpLH

Maximum Propagation Delay
Input A or B to 0
(Figures 6 and 8)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpHL

Maximum Propagation Delay
Input A or B to NO
(Figures 6 and 8)

2.0
4.5
6.0

195
39
33

245
49
42

295
59
50

ns

tpHL

Maximum Propagation Delay
Reset to 0
(Figures 7 and 8)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tpLH

Maximum Propagation Delay
Reset to NO
(Figures 7 and 8)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tTLH
tTHL

Maximum Output Transition Time, Any Output
(Figures 7 and 8)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

-

10
25

10
25

10
25

pF

Symbol

Cin

Parameter

Maximum Input Capacitance

(A. B, Reset)
(C x , Rx)

Min

Max

Min

Max

Min

NOTE: For propagailOn delays with loads other than 50 pF, and information on tYPical parametric values, see Chapter 2.
Typical @ 25°C, Vee
Power Dissipation Capacitance (Per Multivibrator)*

=5.0 V

150

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2f + ICC VCC. For load considerations, see Chapter 2.
TIMING CHARACTERISTICS FOR THE MC54174HC4538A (Input tr = tf = 6.0 ns)
Guaranteed Limits

Symbol

Parameter

-55to
25°C

Vee
Volts

Min

Max

:5 65°C

Min

Max

:5 125°C

Min

Max

Unit

trec

Minimum Recovery Time, Inactive to A or B
(Figure 7)

2.0
4.5
6.0

0
0
0

0
0
0

0
0
0

ns

tw

Minimum Pulse Width, Input A or B
(Figure 6)

2.0
4.5
6.0

60
12
10

75
15
13

90
16
15

ns

tw

Minimum Pulse Width, Reset
(Figure 7)

2.0
4.5
6.0

60
12
10

75
15
13

90
16
15

ns

Maximum Input Rise and Fall Times, Reset
(Figure 7)

2.0
4.5
6.0

AorB
(Figure 7)

2.0
4.5
6.0

tr,tl

High-Speed CMOS Logic Data
DL129-Rev6

3-717

1000
500
400

1000
500
400

1000
500
400

ns

No Limit

MOTOROLA

MC54/74HC4538A
OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t
Guaranteed Limits

Conditions

Symbol

Timing Components

Parameter
Output Pulse Width*
(Figures 6 and 8)

t

Rx

=10 kQ, Cx =0.1 ~F

Max

Min

Max

Unit

5.0

0.63

0.77

0.6

0.8

0.59

0.81

ms

±5.0

%

-

Pulse Width Match
Variation (Part to Part)

-

-

±10

%

~s,

typically t

=kRxCx, where the value of k may be found in Figure 1.
IDs

TA = 25°C _ I--

0.7

~

~
w
~
::::l
a.

:r:

5

I

0.5

!::; 0.4

10ms
1 ms

!::; 100 ~s

I
J

~
a.

::::l

100 ms

~

f

0.6

o~

a.

1 ~s
2

3
4
Vcc, POWER SUPPLY VOLTAGE (VOLTS)

I
I

o

1

lMQ

10~s 100kQ

I::::l

-'" 0.3

.1 I .1 I I

./

1 s - VCC=5V, TA = 25°C

V

z

~

Min

-

a::

8

Max

-

o

z
~
en

Min

Pulse Width Match
Between Circuits in the
same Package

'l0.8

I-

" 125°C

" 85°C

VCC
Volts

-

* For output pulse widths greater than 100

~

-55to
25°C

./

10kQ

V

1 kQ

V

,

100 ns
0.00001 0.0001

7

V

V
VV
/'

0.001

/'
./ . / / '
./
/' . / / '
./
....- /'
",/'

V
......V V
V" ...... V ",V
/ ' ,.....
./

/'

./

V

0.01
0.1
CAPACITANCE (~F)

10

100

Figure 2. Output Pulse Width versus
Timing Capacitance

Figure 1. Typical Output Pulse Width Constant, k,
versus Supply Voltage
(For output pulse widths> 100 lis: ~ = kRxC x )

1.1
TA = 25°C _

Rx =100kQ
Cx = 1000 pF

;xl

/'

/

~

1/

:r::2

b~ 0.9
~>

w.,.,

I

~f2 0.8

--

::::..

/

/

::::lo

a.w

I-N
::::l:::;

I

a."" 0.7

I

!::;~

00

I
II

S 0.6

0.5

Rx=1 MQ
Cx =O.1 ~F

1

2

4

5

VCC, POWER SUPPLY VOLTAGE (VOLTS)
Figure 3. Normalized Output Pulse Width
versus Power Supply Voltage

MOTOROLA

3-718

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC4538A
1.1

ffi

I;"

1.05

:e:~

.,.

I=>

I-Z

Qu

s::'n
WN

-

g

0.95

'3, - ~
'3 ~

0.9

~

0.85

~

~fa

V

VCC=6 V

/

V

Rx =10kQ - Cx =O.I!i F - -

/

/
/

ogs
0.8
-75

VCC =3 V

i-L

I I I

-50

-25

0

25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (OC)

Figure 4. Normalized Output Pulse Width
versus Power Supply Voltage

1.03

a:
W

~~

i!:
~
Qu

I I I
"..

1.02 - Rx =10kQ
_ Cx =O.I!iF

i': ~ -::::

~ ~ F""

1.01

~

s::'n

L.;

WN

~g

~ffi

~~
~~

ogs

~

-

VCC=5.5V

0.99

.

0.98

0.97
-75

~ 7'

~

""

..v.I-1

fA
VCC=5V
.. /vC~=4.5V
I I I

'J

-50

I

j I I
-25
0

25

50

75

100

125

150

TA, AMBIENTTEMPERATURE (0C)

Figure 5. Normalized Output Pulse Width
versus Power Supply Voltage

High-Speed CMOS Logic Data
DL129-Rev6

3-719

MOTOROLA

MC54174HC4538A
SWITCHING WAVEFORMS
-tw(H)-

-

50%

1'\

A

Vee
GND

-tw(L)-

8

Vee

50%

-

tpLH

\

/150%
-tPHL

IpLH

t

GND

~

\
\

-tPHL

~

-

~

1\

Q

Q

-

~

I

\

~

------~'\.50%

J-

t1tlf

r

A

10%

Figure 6.

-~

F---------------------------------------------------------GND

r--------Vee

50%
-GND

8

If
~~--------~-----------------------------Vee

RESET

-GND

---i+---- tree - - - - I

tTLH

t------~+Irr

50%

-------I

(RETRIGGERED PULSE)

0----'1

trHL~
90%
10%

tPLH;;
50'1.-.--------------~\
_ _ _ _ _-'

r

....JI

1...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 7.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST

• Includes all probe and jig capacitance

Figure 8. Test Circuit

MOTOROLA

3-720

High-Speed CMOS Logic Data
DL129-Rev6

MC54174HC4538A
PIN DESCRIPTIONS
tors (see the Block Diagram). Polystyrene capacitors are
recommended for optimum pulse width control. Electrolytic
capacitors are not recommended due to high leakages
associated with these type capacitors.

INPUTS
Al, A2 (Pins 4,12)
Positive-edge trigger inputs. A rising-edge signal on
either of these pins triggers the corresponding multivibrator
when there is a high level on the B1 or B2 input.

GND (Pins 1 and 15)
External ground. The external timing capacitors discharge
to ground through these pins.

Bl, B2 (Pins 5,11)
Negative-edge trigger inputs. A falling-edge signal on
either of these pins triggers the corresponding multivibrator
when there is a low level on the A 1 or A2 input.

OUTPUTS
Ql, Q2 (Pins 6, 10)
Noninverted monostable outputs. These pins (normally
low) pulse high when the multivibrator is triggered at either
the A or the B input. The width of the pulse is determined by
the external timing components, RX and eX.

Reset 1, Reset 2 (Pins 3,13)
Reset inputs (active low). When a low level is applied to
one of these pins, the 0 output of the corresponding multivibrator is reset to a low level and the Q output is set to a high
level.

Ql, Q2 (Pins 7,9)
Inverted monostable outputs. These pins (normally high)
pulse low when the multivibrator is triggered at either the A or
the B input. These outputs are the inverse of 01 and 02.

CX1/RX 1 and CX2IRX2 (Pins 2 and 14)
External timing components. These pins are tied to the
common points of the external timing resistors and ,capaci-

LOGIC DETAIL
(1/2 THE DEVICE)

r-UPPER-'

II

REFERENCE
CIRCUIT

II

r-----'
OUTPUT
I

I
I

LATCH

I
I
I
I
I
I
I
I

,-- TRIGGERCONTROLI
I

RESET CIRCUIT

Figure 9.

High-Speed CMOS Logic Data

DL129-Rev6

3-721

MOTOROLA

MC54/74HC4538A
CIRCUIT OPERATION
Figure 12 shows the HC4538A configured in the retriggerable mode. Briefly, the device operates as follows (refer to
Figure 10): In the quiescent state, the external timing capacitor, Cx, is charged to V CC. When a trigger occurs, the Q output goes high and C x discharges quickly to the lower
reference voltage (Vref Lower,., 1/3 VCC). C x then charges,
through Rx , back up to the upper reference voltage (V ref Upper,., 2/3 VCC), at which point the one-shot has timed out
and the Q output goes low.
The following, more detailed description of the circuit operation refers to both the logic detail (Figure 9) and the timing
diagram (Figure 10).

TRIGGER OPERATION
The HC4538A is triggered by either a rising-edge signal at
input A (#7) or a falling-edge signal at input B (#8), with the
unused trigger input and the Reset input held at the voltage
levels shown in the Function Table. Either trigger signal will
cause the output of the trigger-control circuit to go high (#9).
The trigger--control circuit going high simultaneously initiates two events. First, the output latch goes low, thus taking
the Q output of the HC4538A to a high state (#10). Second,
transistor M3 is turned on, which allows the external timing
capacitor, C x , to rapidly discharge toward ground (#11).
(Note that the voltage across Cx appears at the input of both
the upper and lower reference circuit comparator).
When C x discharges to the reference voltage of the lower
reference circuit (#12), the outputs of both reference circuits
will be high (#13). The trigger--control reset circuit goes high,
resetting the trigger-control circuit flip-flop to a low state
(#14). This turns transistor M3 off again, allowing C x to begin
to charge back up toward VCC, with a time constant t RxCx
(#15). Once the voltage across Cx charges to above the lower reference voltage, the lower reference circuit will go low
allowing the monostable multivibrator to be retriggered.

QUIESCENT STATE
In the quiescent state, before an input trigger appears, the
output latch is high and the reset latch is high (#1 in Figure 10). Thus the Q output (pin 6 or 10) of the monostable
multivibrator is low (#2, Figure 10).
The output of the trigger-control circuit is low (#3), and
transistors M1, M2, and M3 are turned off. The external timing capacitor, Cx , is charged to VCC (#4), and both the upper
and lower reference circuit has a low output (#5).
In addition, the output of the trigger-control reset circuit is
low.

=

TRIGGER CYCLE
(AINPUn

I

~

®

~

CD

RX/CX INPUT
(PIN 2 OR 14)

RESET INPUT
(PIN30R 13)

~
______~n~______~n~__~r!Jl
______

12

.

Vref LOWER /

LOWER REFERENCE
CIRCUIT

I--

trr

__________~n~__~~~_____

-----------'LJ

TRIGGER·CONTROL
CIRCUIT OUTPUT '-":~_..J

UPPER REFERENCE
CIRCUIT

RETRIGGER

--I

CD

TRIGGER INPUT A
(PIN 4 OR 12) _ _----l
TRIGGER INPUT 8
(PIN50R11)

TRIGGER CYCLE
(8 INPUT)

0

VrefUPPER

®

II@

II

®

n

~------'

_....;®,--_--,n@

n
n

1-_ _ _ _- '

' - = ' - - - - - - - - - - ' 1-_ _ _ _ _ _- - '

1-_ _--'

u

L..-_ _ _--'

'------

--------------------®-:::20:-'1U,...----------

RESET LATCH

®
QOUTPUT
(PIN60R10)

r-1L--J1

_...;0:;..2_...J1IL:'@:;..9
_ _ _--1
.
I-~-I

1.-_ _ _ _1

f--~-I

I

L--

I-- ~+trr---i

Figure 10. Timing Diagram

MOTOROLA

3-722

High-Speed CMOS Logic Data
DL129-Rev6

MC54/74HC4538A
occurs, the output of the reset latch goes low (#22), turning
on transistor M1. Thus C x is allowed to quickly charge up to
VCC (#23) to await the next trigger signal.
On power up of the HC4538A the power-on reset circuit
will be high causing a reset condition. This will prevent the
trigger-control circuit from accepting a trigger input during
this state. The HC4538A's Q outputs are low and the Q not
outputs are high.

When Cx charges up to the reference voltage of the upper
reference circuit (#17), the output of the upper reference circuit goes low (#18). This causes the output latch to toggle,
taking the Q output of the HC4538A to a low state (#19), and
completing the time-out cycle.
POWER-DOWN CONSIDERATIONS

Large values of C x may cause problems when powering
down the HC4538A because of the amount of energy stored
in the capacitor. When a system containing this device is
powered down, the capacitor may discharge from VCC
through the input protection diodes at pin 2 or pin 14. Current
through the protection diodes must be limited to 30 mA;
therefore, the turn-off time of the VCC power supply must not
be faster than t
VCC.C x /(30 mAl. For example, if
VCC = 5.0 V and C x = 151lF, the VCC supply must turn off no
faster than t (5.0 V).(15IlF)/30 mA 2.5 ms. This is usually
not a problem because power supplies are heavily filtered
and cannot discharge at this rate.
When a more rapid decrease of VCC to zero volts occurs,
the HC4538A may sustain damage. To avoid this possibility,
use an external damping diode, Ox, connected as shown in
Figure 11. Best results can be achieved if diode Ox is chosen
to be a germanium or Schottky type diode able to withstand
large current surges.

RETRIGGER OPERATION

When used in the retriggerable mode (Figure 12), the
HC4538A may be retriggered during timing out of the output
pulse at any time after the trigger-control circuit flip-flop has
been reset (#24), and the voltage across Cx is above the lower reference voltage. As long as the C x voltage is below the
lower reference voltage, the reset of the flip-flop is high, disabling any trigger pulse. This prevents M3 from turning on
during this period resulting in an output pulse width that is
predictable.
The amount of undershoot voltage on RxCx during the
trigger mode is a function of loop delay, M3 conductivity, and
VOO. Minimum retrigger time, trr (Figure 7), is a function of
1) time to discharge RxCx from VOO to lower reference
voltage(T discharge);2)loopdelay(T delay);3)timetocharge
RxCx from the undershoot voltage back to the lower reference voltage (Tcharge).
Figure 13 shows the device configured in the non-retriggerable mode.
An Application Note (AN1558/D) titled Characterization of
Retrigger Time in the HC4538A Dual Precision Monstable
Multivibratoris being prepared. Please consult the factory for
its availability.

=

=

=

RESET AND POWER ON RESET OPERATION

A low voltage applied to the Reset pin always forces the Q
output of the HC4538A to a low state.
The timing diagram illustrates the case in which reset occurs (#20) while Cx is charging up toward the reference voltage of the upper reference circuit (#21). When a reset

DX

Vee
RX
1---0

A
B

1---0

RESET

Figure 11. Discharge Protection During Power Down

High-Speed CMOS Logic Data
DL129-Rev6

3-723

MOTOROLA

131

MC54174HC4538A
TYPICAL APPLICATIONS
RX

RX

RISING-EDGE
TRIGGER

RISING-EDGE
TRIGGER
A

1----0

B

0---0

A

1----0

B

RESET =VCC

RESET = VCC

RX

1---0

A
B

0---0
FALLING-EDGE
TRIGGER

FALLING-EDGE
TRIGGER

RESET = VCC

Figure 12. Retriggerable Monostable Circuitry

RESET = VCC

Figure 13. Non-retriggerable Monostable Circuitry

ONE-5HOT SELECTION GUIDE

~ Jo ~"'I-~ _~1+f -~ ~_1.,Ot-I -:-___S 1.~0-tj_I1)(_S_1-t~_:_10+r_S_1_00+f_S_j.S_~;t ,:,:R
• Limited operating voltage (2-6 V)

1------..

TOTAL OUTPUT PULSE WIDTH RANGE ...
RECOMMENDED PULSE WIDTH RANGE Xlt-----~)(

MOTOROLA

3-724

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC7266

Quad 2-lnput Exclusive
NOR Gate
High-Performance Silicon-Gate CMOS
The MC74HC7266 is identical in pinout to the LS266 and the HC266. The
HC7266 has standard CMOS outputs instead of open-drain outputs.
The de~lce Inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.
•
•
•
•
•
•
•

•

'YI~
14 'nTl111

N SUFFIX
PLASTIC PACKAGE
CASE 646-06

14~

D SUFFIX
SOIC PACKAGE
CASE 751A-03

Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 I-!A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
Chip Complexity: 56 FETs or 14 Equivalent Gates

ORDERING INFORMATION

MC74HCXXXXN
MC74HCXXXXD

Plastic
SOIC

PIN ASSIGNMENT
LOGIC DIAGRAM

PVee
P84

A1 [ 1-

14

81

2

13

Y1 ( 3

12

A4

Y2 [ 4

11

Y4

A2~5
4 Y2

A2

5

10

Y3

82 6

82

6

9

83

GND

7

8

A3

1

A1~
2
Y1
81

8

A3~0
9
Y3
83

12

FUNCTION TABLE

A4~.~

84~Y4

Inputs

PIN 14= Vee
PIN 7 = GND

10/95

© Molorola, Inc. 1995

3-725

REV6

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
H

@ MOTOROLA

MC74HC7266
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to + 7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

-1.5to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature

-65to+150

°c

lin

TL

Plastic DIPt
SOIC Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
range GND " (Vin orVout) " VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: -10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter

Min

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall Time
(Figure 1)

VCC=2.0V
VCC=4.5V
VCC=6.0V

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

" B5°C

" 125°C

Unit

Minimum High-Level Input
Voltage

Vou t=O.1 VorVcc-O.l V
lIoutl " 2Ol1A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vou t=O.1 VorVcc-O.l V
lIoutl " 20 !!A

2.0
4.5
6.0

0.3
0.9
1.2

0.3
0.9
1.2

0.3
0.9
1.2

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl " 2Ol1A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

Yin = VIH or VIL lIoutl " 4.0 rnA
Iioutl " 5.2 rnA

4.5
6.0

3.98
5.48

3.84
5.34

3.70
5.20

Yin = VIH or VIL
lIoutl " 20 !!A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Yin = VIH or VIL lIoutl " 4.0 rnA
lIoutl " 5.2 rnA

4.5
6.0

0.26
0.26

0.33
0.33

0.40
0.40

Maximum Input Leakage Current

Yin = VCC or GND

6.0

±0.1

±1.0

±1.0

!!A

Maximum Quiescent Supply
Current (per Package)

Yin = VCC or GND
lout = o !!A

6.0

2

20

40

I1A

VOL

lin
ICC

Maximum Low-Level Output
Voltage

Test Conditions

-55to
25°C

VIH

VOH

Parameter

VCC
V

NOTE: Information on tYPical parametric values can be found

MOTOROLA

In

V

Chapter 2.

3-726

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC7266
AC ELECTRICAL CHARACTERISTICS ( CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Vee
V

-55to
25°e

s 85°e

s 125°e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
4.5
6.0

120
24
20

150
30
26

180
36
31

ns

tTLH,
tTHL

Maximum Output Transition lime, Any Output
(Figures 1 and 2)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25°e, Vee
Power Dissipation Capacitance (Per Gate)'

=5.0 V

33

• Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

INPUT
AORB

VCC
TEST POINT

" ' - - - - GND

OUTPUT
DEVICE
UNDER
TEST

OUTPUTY

10%
• Includes all probe and jig capacitance
Figure 1. Switching Waveforms

Figure 2. Test Circuit

LOGIC DETAIL
(1/4 of Device)

A

Y
B

High-Speed CMOS Logic Data
DL129-Rev6

3--727

MOTOROLA

MC74HC7266
APPLICATION INFORMATION
Bi q,-L is defined as biphase-Ievel code. Also known as
Manchester Code, this technique utilizes binary phase shift
keying (PSK). The Bi q,-L output shown in Figure 3 carries
both data and synchronization information; therefore, separate data and clock lines are not required to transfer information. A positive-going transition in the middle of the bit
interval indicates a logic zero; a negative-going transition in-

dicates a logic one (see Figure 4).
NRZ-L shown in Figure 3 is non-return-to-zero level
code. This is simply serial data out of a shift register, such as
the HC597.
The Bi q,-L signal must be phase coherent (i.e., no
glitches). Therefore, NRZ-L and clock transitions must be
coincident.

1/4
HC7266

NRZ-L=JD-

BI -L

CLOCK

Figure 3. Biphase--Level Encoder (Manchester Encoder)

NRZ-L --'

CLOCK

Blq,-L
POSITIVE
LOGIC DATA

BIT
INTERVAL

Figure 4. Timing Diagram

MOTOROLA

3-728

High-Speed CMOS Logic Data
DL129-Rev6

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC74HC7266A

Product Preview

Quad 2-lnput Exclusive
NOR Gate

NSUFFIX
PLASTIC PACKAGE
CASE 646-{)6

High-Performance Silicon-Gate CMOS
The MC74HC7266A is identical in pinout to the LS266 and the HC266.
The HC7266 has standard CMOS outputs instead of open-drain outputs.
The device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.

DSUFFIX
SOIC PACKAGE
CASE 751A-{)3

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current 1 J.lA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
NO.7A
• Chip Complexity: 56 FETs or 14 Equivalent Gates

DTSUFFIX
TSSOP PACKAGE
CASE 948G-{)1

ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADT

Plastic
SOIC
TSSOP

LOGIC DIAGRAM

.

Al~1
3 ~

PIN ASSIGNMENT

81 2

A2~5
4 Y2
82 6

Y=A$8
=A8+AB

14

8t[ 2

13

Yl[ 3

12

Y2[ 4

11

A2[ 5

10

82[ 6

9

GND[ 7

8

8

A3~0
9
Y3
83

A4~12
11
Y4

Al[ 1·

~ Vee
~ 84
~A4
~ Y4
~ Y3
~ 83
~ A3

84 13
FUNCTION TABLE

PIN 14= Vee
PIN 7 =GND

Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
H

This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.

10195

© Motorola, Inc. 1995

3-729

REVO

®

MOTOROLA

MC?4HC?266A
MAXIMUM RATINGS·
Symbol
VCC

Parameter
DC Supply Voltage (Referenced to GND)

Value

Unit

-0.5to+7.0

V
V

Yin

DC Input Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

Vout

DC Output Voltage (Referenced to GND)

- 0.5 to VCC + 0.5

V

lin

DC Input Current, per Pin

±20

rnA

lout

DC Output Current, per Pin

±25

rnA

ICC

DC Supply Current, VCC and GND Pins

±50

rnA

PD

Power Dissipation in Still Air

750
500
450

mW

Tstg

Storage Temperature

-65to+ 150

°C

TL

Plastic DIPt
SOIC Packaget
TSSOP Packaget

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Yin and
Vout should be constrained to the
rangeGND s (VinorVouV s VCC.
Unused inputs must always be
tied to an appropriate logic vol.tage
level (e.g., either GND or VCC).
Unused outputs must be left open.

°C
260

• Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
tDerating - Plastic DIP: - 10 mW/oC from 65° to 125°C
SOIC Package: -7 mW/oC from 65° to 125°C
TSSOP Package: -6.1 mWrC from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2.

RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Yin, Vout

Parameter

Min

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr,tf

Input Rise and Fall TIme
(Figure 1)

VCC=2.0V
VCC = 4.5 V
VCC=6.0V

Max

Unit

2.0

6.0

V

0

VCC

V

-55

+ 125

°c

0
0
0

1000
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Test Conditions

VCC
V

s 85°C

s 125°C

Unit

VIH

Minimum High-Level Input
Voltage

Vout=O.l VorVcc-O.l V
1I0uti s 20 I1A

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

V

VIL

Maximum Low-Level Input
Voltage

Vout=O.l VorVCC-O.l V
lIoutl s 20!!A

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

V

Minimum High-Level Output
Voltage

Yin = VIH or VIL
lIoutl s 20!!A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

V

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

VOH

Parameter

-55to
25°C

Yin = VIH or VIL

MOTOROLA

lIoutl s 2.4 rnA
lIoutl s 4.0 rnA
1I0uti s 5.2 rnA

3-730

High-Speed CMOS Logic Data
DL129-Rev6

MC74HC7266A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

Parameter

Test Conditions

=

Maximum Low-Level Output
Voltage

Vin VIH or VIL
lIoutl s 20llA
Vin

lin
ICC

Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)

=VIH or VIL

lIoutl s 2.4 mA
lIoutl s 4.0 mA
lIoutl s 5.2 mA

=VCC or GND
Vin =VCC or GND
lout =0 IlA

Vin

Vee
V

-55to
25'e

s 85'e

s 125'e

Unit

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

6.0

±0.1

±1.0

±1.0

IlA

6.0

1

10

40

Il A

Vee
V

-55to
25'e

NOTE: Information on typical parametric values can be found in Chapter 2.
AC ELECTRICAL CHARACTERISTICS ( CL

=50 pF, Input tr =tf =6 ns)
Guaranteed Limit

s 85'e

s 125'e

Unit

tpLH,
tpHL

Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)

2.0
3.0
4.5
6.0

100
80
20
17

125
90
25
21

150
110
25
19

ns

tTLH,
trHL

Maximum Output Transition lime, Any Output
(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

Maximum Input Capacitance

-

10

10

10

pF

Symbol

Cin

Parameter

NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2.
2. Information on typical parametric values can be found in Chapter 2.
Typical @ 25'e, Vee
Power Dissipation Capacitance (Per Gate)"
"Used to determine the no-load dynamic power consumption: PD

INPUT
AORB

=5.0 V

33

=CpD VCC 2 f + ICC VCC. For load considerations, see Chapter 2.

VCC
TEST POINT

-=----

GND

OUTPUT
DEVICE
UNDER
TEST

OUTPUTY

10%

trLH--

" Includes all probe and jig capacitance

Figure 1. Switching Waveforms

High-Speed CMOS Logic Data
DL129-Rev6

Figure 2. Test Circuit

3-731

MOTOROLA

MC74HC7266A
LOGIC DETAIL
(1/4 of Device)

A
y

B

APPLICATION INFORMATION
Bi cJr-L is defined as biphase-Ievel code. Also known as
Manchester Code, this technique utilizes binary phase shift
keying (PSK). The Bi cJr-L output shown in Figure 3 carries
both data and synchronization information; therefore, separate data and clock lines are not required to transfer information. A positive-going transition in the middle of the bit
interval indicates a logic zero; a negative-9oing transition in-

dicates a logic one (see Figure 4).
NRZ-L shown in Figure 3 is non-return-to-zero level
code. This is simply serial data out of a shift register, such as
the HC597.
The Bi cp-L signal must be phase coherent (Le., no
glitches). Therefore, NRZ-L and clock transitions must be
coincident.

114
HC7266A

NRZ-L=n=>CLOCK

BI -l
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