1996_Motorola_MECL_Data 1996 Motorola MECL Data
User Manual: 1996_Motorola_MECL_Data
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MOTOROLA
® MEeL Data
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04/96
DL122
REV6
DL 122/ D
REV 6
MECL Data
General Information
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MECL10H
[2J
MECL10K
[3J
MECL III
[!]
Carrier Band Modem
[5J
Ordering Information
[6J
ECLinPS, ECLinPS Lite, MECL, MECL 10H, MECL 10K, MECL 10,000, MECL III, MOSAIC,
MTTL and QUIL are trademarks of Motorola Inc.
The brands or product names mentioned are trademarks or registered trademarks of their respective holders.
®
MOTOROLA
MECLData
This book presents technical data for a broad line of MECL integrated circuits. Complete
specifications for the individual circuits are provided in the form of data sheets. In addition,
selector guides are included to simplify the task of choosing the best combination of circuits for
optimum system architecture.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes
no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Motorola assume any liability arising out olthe application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical"
parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including "Typicals" must
be validated for each customer application by customer's technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could
create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products
for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part. Motorola and ® are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Sixth Edition
© Motorola, Inc. 1996
Previous Edition © 1993
"All Rights Reserved"
Printed in U.S.A.
jji
MECLData
DL122-Rev6
WHAT'S NEW!
DATA SHEETS DELETED
MC10H11B
MC10119
MC1672
MC4044
MC10H119
MC1012B
MC1690
MC4316
MC10H423
MC10130
MC4016
MC4324
MC10100
MC10132
MC4018
MC4344
MC1011B
MC10190
MC4024
WHERE ARE THE PHASE-LOCKED LOOP ICs?
To better serve our customers, we have moved all of the MECL Phase-Locked
Loop ICs to our High Performance Frequency Control Products (Hipercomm)
publication. The Hipercomm book (BR1334/D) can be ordered from the
Motorola Literature Distribution Center. Additionally, all of the PLL data sheets
can be accessed via Internet or through the Motorola MFax™ fax-back
systems. See a full listing of Motorola's PLLs on page 1-30 of this book.
Motorola SPS World MFax System
Mfax Access:
Email:
Telephone:
WWW:
RMFAXO@email.sps.mot.com
TOUCH-TONE (602) 244-6609 or 1-800-774-1848
http://Design-NET.com --7 select the Mfax Icon.
A fax of complete, easy-to-use instructions can be obtained with a first-time phone
call into the system, entering your FAX number and then, pressing 1.
Motorola SPS World Marketing Internet Server
Motorola SPS's Electronic Data Delivery organization has set up a World Wide Web Server to
deliver Motorola SPS's technical data to the global Internet community. Technical data such as
the complete Master Selection Guide along with the OEM North American price book are
available on the Internet server with full search capabilities. Other data on the server include
abstracts of data books, application notes, selector guides, and textbooks. All have easy text
search capability. Ordering literature from the Literature Distribution Center is available on line.
Other features of Motorola SPS's Internet server include the availability of a searchable press
release database, technical training information, with on-line registration capabilities, complete
on-line access to the Mfax system for ordering technical literature faxes, an on-line technical
support form to send technical questions and receive answers through email, information on
product groups, full search capabilities of device models, a listing of the Domestic and
International sales offices, and links directly to other Motorola world wide web servers. For more
information on Motorola SPS's Internet server you can request BR13071D from Mfax or LDG.
After accessing the Internet, use the following URL:
http://Design-NET.com
iv
Table of Contents
Chapter 1. General Information
Chapter 2. MECL 10H Data Sheets
High-Speed Logic .....................
MECL Products ......................
MECL Family Comparison .............
Basic Design Considerations ...........
Definitions of Symbols & Abbreviations ..
MECL Positive and Negative Logic ......
1-2
1-2
1-2
1-3
1-6
1-8
Technical Data ........................
General Characteristics ..............
Noise Margin .......................
Switching Parameters ................
Setup and Hold .....................
Testing MECL 10H, 10K and III ........
1-10
1-10
1-12
1-12
1-14
1-14
Operational Data . . . . . . . . . . . . . . . . . . . . ..
System Design Considerations .........
Thermal Management ................
Optimizing Reliability .................
Thermal Effects on Noise Margin ......
Mounting and Heatsink ...............
Circuit Interconnects .................
1-16
1-18
1-18
1-20
1-22
1-22
1-23
MECL 10H Selector Guide ............... 2-2
MECL 10H Introduction .................. 2-3
MECL 10H Data Sheets .................. 2-6
Chapter 3. MECL 10K Data Sheets
MECL 10K Selector Guide ............... 3-2
MECL 10K Data Sheets .................. 3-3
Chapter 4. MECL III Data Sheets
MECL III Selector Guide ................. 4-2
MECL III Data Sheets.. . . .. . .. . . .. . . . . ... 4-3
Chapter 5. Carrier Band Modem
Carrier Band Modem Data Sheet . . . . . . . . .. 5-2
Chapter 6. Ordering Information
Device Nomenclature . . . . . . . . . . . . . . . . . . .. 6-2
Case Outlines ......................... 6-3
Pin Conversion Tables .................. 6-11
Motorola Distributors and Worldwide
Sales Offices .......................... 6-12
Applications Assistance Form ......... 1-28
Phase-Locked Loop les ............ 1-29
v
Numeric Listing
MECL 10H Data Sheets
MC10H016
4-Bit Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6
MC10H100
Quad 2-lnput NOR Gate With Strobe ..................................... .
2-8
MC10H101
Quad OR/NOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-9
MC10H102
Quad 2-lnput NOR Gate.................................................
2-10
MC10H103
Quad 2-lnput OR Gate ..................................................
2-11
MC10H104
Quad 2-lnput AND Gate................................................ .
2-12
MC10H105
Triple 2-3-2-lnput OR/NOR Gate........................................ .
2-13
MC10H106
Triple 4-3-3-lnput NOR Gate ............................................
2-14
MC10H107
Triple 2-lnput Exclusive OR/Exclusive NOR Gate ...........................
2-15
MC10H109
Dual 4-5-lnput OR/NOR Gate ........................................... .
2-16
MC10H113
Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-17
MC10H115
Quad Line Receiver
2-18
MC10H116
Triple Line Receiver
2-19
MC10H117
Dual 2-Wide 2-3-lnput OR-AND/OR-AND Gate ...........................
2-20
MC10H121
4-Wide OR-AND/OR-AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-21
MC10H123
Triple 4-3-3-lnput Bus Driver ............................................
2-22
MC10H124
Quad TTL-to-MECL Translator With TTL Strobe Input. . . . . . . . . . . . . . . . . . . . . . .
2-24
MC10H125
Quad MECL-to-TTL Translator ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-26
MC10H130
Dual Latch ........................................................ ,....
2-28
MC10H131
Dual D Type Master-Slave Flip-Flop ......................................
2-30
MC10H135
Dual J-K Master-8lave Flip-Flop .........................................
2-32
MC10H136
Universal Hexadecimal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-33
MC10H141
Four-Bit Universal Shift Register .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-35
MC10H145
16 x 4 Bit Register File (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-37
MC10H158
Quad 2-lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-40
MC10H159
Quad 2-lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-42
MC10H160
12-Bit Parity Generator-Checker .........................................
2-44
MC10H161
Binary to 1-8 Decoder (Low) . . . .. . . . . .. .... . . ... .. . . . ... .. . . . .. . .. .... . ...
2-45
MC10H162
Binary to 1-8 Decoder (High) .............................................
2-47
MC10H164
8-Line Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-49
vi
MECLData
DL122-Rev6
Numeric Listing
MECL 10H Data Sheets
MC10H165
8-lnput Priority Encoder ................................................. .
2-51
MC10H166
5-Bit Magnitude Comparator ............................................ .
2-54
MC10H171
Dual Binary to 1-4 Decoder (low) ........................................ .
2-57
MC10H172
Dual Binary to 1-4-Decoder (High) ....................................... .
2-59
MC10H173
Quad 2-lnput Multiplexer/ latch .......................................... .
2-61
MC10H174
Dual 4 to 1 Multiplexer .................................................. .
2-63
MC10H175
Qunit latch ............................................................ .
2-65
MC10H176
Hex D Master-Slave Flip-Flop .......................................... ..
2-67
MC10H179
look-Ahead Carry Block ................................................ .
2-69
MC10H180
Dual 2-Bit Adder/Subtractor ............................................. .
2-72
MC10H181
4-Bit Arithmetic logic Unit! Function Generator ............................ .
2-74
MC10H186
Hex D Master-8lave Flip-Flop with Reset ................................. .
2-77
MC10H188
Hex Buffer with Enable .................................................. .
2-79
MC10H189
Hex Inverter with Enable ................................................ .
2-80
MC10H209
Dual 4-5-lnput ORINOR Gate ........................................... .
2-81
MC10H210
Dual 3-lnput 3-Output OR Gate ......................................... .
2-82
MC10H211
Dual 3-lnput 3-Output NOR Gate ........................................ .
2-83
MC10H330
Quad Bus Driver/Receiver with 2-t0-1 Output Multiplexers .................. .
2-84
MC10H332
Dual Bus Driver/Receiver with 4-t0-1 Output Multiplexers ................... .
2-86
MC10H334
Quad Bus Driver/Receiver with Transmit and Receiver latches .............. .
2-88
MC10H350
PECl' to TTL Translator ................................................ .
2-90
MC10H351
Quad TTUNMOS to PECl' Translator .................................... .
2-92
MC10H352
Quad CMOS to PECl' Translator ....................................... ..
2-94
MC10H424
Quad TTL to ECl Translator with ECl Strobe .............................. .
2-96
MC10/100H600
9-Bit TTL/ECl Translator ............................................... .
2-98
MC10/100H601
9-Bit ECL/TTl Translator................................................
2-101
MC1 0/1 00H602
9-Bit latch TTL/ECl Translator...........................................
2-103
MC1 0/1 00H603
9-Bit latch ECL/TTl Translator. . . . .. . . .. .. . . . .. . . . .. . . . . .. . . . . . .. . .. . . .. .
2-105
MC1 0/1 00H604
Registered Hex TTUECl Translator .......................................
2-108
MC10/100H605
Registered Hex ECUTTl Translator.......................................
2-110
vii
Numeric Listing
MECL 10H Data Sheets
MC1 0/1 00H606
Registered Hex TTUPECL Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-113
MC10/100H607
Registered Hex PECUTTL Translator.......... ............................
2-116
MC10/100H640
680301040 PECL-TTL Clock Driver............ ............................
2-119
MC 10/1 00H641
Single Supply PECL- TTL 1:9 Clock Distribution Chip ........................
2-125
MC1 0/1 00H642
680301040 PECL-TTL Clock Driver........................................
2-131
MC10/100H643
Dual Supply ECL-TTL 1:8 Clock Driver....................................
2-138
MC1 0/1 00H644
680301040 PECL-TTL Clock Driver............ ............................
2-141
MC10H645
1:9 TTL Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-144
MC1 0/1 00H646
PECUTTL-TTL 1:8 Clock Distribution Chip..... ............................
2-147
MC1 0/1 00H660
4-Bit ECUTTL Load Reducing DRAM Driver ...............................
2-151
MC1 0/1 00H680
4-Bit Differential ECL Bus/TTL Bus Transceiver ............................
2-156
MC10/100H681
Hex ECL/TTL Transceiver with Latches....................................
2-162
MECL 10K Data Sheets
MC10101
Quad ORINOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
MC10102
Quad 2-lnput NOR Gate .................................................
3-6
MC10103
Quad 2-lnput OR Gate ..................................................
3-9
MC10104
Quad 2-lnput AND Gate .................................................
3-12
MC10105
Triple 2-3-2-lnput ORINOR Gate............. ............................
3-15
MC10106
Triple 4-3-3-lnput NOR Gate ............................................
3-18
MC10107
Triple 2-lnput Exclusive ORI Exclusive NOR Gate ...........................
3-20
MC10109
Dual 4-5-lnput ORINOR Gate ............................................
3-23
MC10110
Dual 3-lnpuV3-0utput OR Gate ..........................................
3-26
MC10111
Dual 3-lnpuV3-0utput NOR Gate .......................... . . . . . . . . . . . . . . .
3-29
MC10113
Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-32
MC10114
Triple Line Receiver .....................................................
3-35 .
MC10115
Quad Line Receiver .....................................................
3-39
MC10116
Triple Line Receiver .....................................................
3-41
MC10117
Dual 2-Wide 2-3-lnput OR-AND/OR-AND Gate ...........................
3-44
MC10121
4-Wide OR-AND/OR-AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-47
viii
Numeric Listing
MECL 10K Data Sheets
MC10123
Triple 4-3-3-lnput Bus Driver ............................................
3-50
MC10124
Quad TTL to MECL Translator ............................................
3-52
MC10125
Quad MECL to TTL Translator ............................................
3-57
MC10129
Quad Bus Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-62
MC10131
Dual Type D Master-Slave Flip-Flop ......................................
3-68
MC10133
Quad Latch ............................................................
3-71
MC10134
Dual Multiplexer With Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-74
MC10135
Dual J-K Master-Slave Flip-Flop.........................................
3-77
MC10136
Universal Hexadecimal Counter ................. '. . . . . . . . . . . . . . . . . . . . . . . . . .
3-80
MC10137
Universal Decade Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-86
MC10138
Bi-Quinary Counter .....................................................
3-91
MC10141
Four Bit Universal Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-94
MC10153
Quad Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-98
MC10154
Binary Counter................................................ ..........
3-101
MC10158
Quad 2-lnput Multiplexer....................................... ..........
3-104
MC10159
Quad 2-lnput Multiplexer....................................... ..........
3-106
MC10160
12-Bit Parity Generator-Checker .........................................
3-108
MC10161
Binary to 1-8 Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-111
MC10162
Binary to 1-8 Decoder (High) .................................. ,..........
3-114
MC10164
8-Line Multiplexer. . . . .. . . .. .. . . .. . . . .... . .. ..... . ... .. . . .. . . .. .. . . . . . . ..
3-116
MC10165
8-lnput Priority Encoder.. . .. . . . . . . . . . ... . . . . . . .... . . . . . . . . .. . .. .. .... ....
3-119
MC10166
5-Bit Magnitude Comparator .............................................
3-124
MC10168
Quad Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-128
MC10170
9+2-Bit Parity Generator! Checker ........................................
3-131
MC10171
Dual Binary to 1-4 Decoder (Low) .. . .... . . . ... . . . . . . . . . . .. . . . .. . . . .. . . ....
3-134
MC10172
Dual Binary to 1-4 Decoder (High) ........................................
3-137
MC10173
Quad 2-lnput Multiplexer/ Latch.. . ... . . . . . . ... . . . . . . .. . . .. . . ... .. .. . . ... ..
3-140
MC10174
Dual 4 to 1 Multiplexer. ... . . ... . . . . . . . . . . . ... . . . .. . .. . . .. . . . .. . . ... . ... ..
3-143
MC10175
Quint Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-145
MC10176
Hex D Master/Slave Flip-Flop ............................................
3-148
ix
Numeric Listing
MECL 10K Data Sheets
MC10178
Binary Counter. . .... . . . .. . . .. . ....... . ... . . . . .. . . . . ... . . ............ ....
3-151
MC10181
4-Bit Arithmetic Logic UniV Function Generator ............ :.. . . . ... . . .. . . ..
3-154
MC10186
Hex D Master-Slave Flip-Flop With Reset .................................
3-159
MC10188
Hex Buffer With Enable..................................................
3-162
MC10189
Hex Inverter With Enable.................................................
3-164
MC10192
Quad Bus Driver ........................................................ 3-166
MC10195
Hex Inverter/Buffer.. .................................................... 3-168
MC10197
Hex AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-170
MC10198
Monostable Multivibrator .................................................
3-172
MC10210
DuaI3-lnpuV3-0utput OR Gate ..........................................
3-180
MC10211
DuaI3-lnpuV3-0utput NOR Gate........................ .................
3-183
MC10212
High Speed Dual3-lnpuV 3-Output ORiNOR Gate......... .................
3-186
MC10216
High Speed Triple Line Receiver ..........................................
3-189
MC10231
High Speed Dual Type D Master-Slave Flip-Flop ...........................
3-192
CHAPTER 4 -
MECL III
MC1648
Voltage Controlled Oscillator............................. .................
4-3
MC1650/MC1651
Dual AID Converter... ...................................................
4-11
MC1658
Voltage Controlled Multivibrator ...........................................
4-21
MC1660
Dual 4-lnput ORiNOR Gate ..............................................
4-25
MC1662
Quad 2-lnput NOR Gate ................................ . . . . . . . . . . . . . . . . .
4-26
MC1670
Master-Slave Flip-Flop ................................. .. . . . .. .. . . .. . . ..
4-27
MC1692
Quad Line Receiver .....................................................
4-30
CHAPTER 5 MC68194
CBM
Carrier Band Modem (CBM) ............................................. .
x
5-2
MECL Data
General Information
MECLData
DL122-Rev6
1-1
MOTOROLA
[I]
SECTION 1 -
HIGH-SPEED LOGIC
High speed logic is used whenever improved system
performance would increase a product's market value. For a
given system deSign, high-speed logiC is the most direct way
to improve system performance and Emitter-Coupled logic
(ECl) is one of today's fastest fonns of digital logic. Emittercoupled logic offers both the logic speed and logic features to
meet the market demands for higher performance systems.
MECl PRODUCTS
Compatibility with MECl 10K and MECl III is a key element
in allowing users to enhance existing systems by increasing
the speed in critical timing areas. Also, many MECl 10H
devices are pin out/functional duplications of the MECl 10K
series devices. The emphasis of this family will be placed on
more powerful logic functions having more complexity and
greater performance. With 1.0 ns propagation delays and
25 mW per gate, MECl 10H is one of the best speed-power
families of any ECl logic family available today.
MECL at +5V(PECL)
Motorola introduced the original monolithic emitter-coupled
logic family with MECl I (1962) and followed this with MECl II
(1966). These two families are now obsolete and have given
way to the MECl III (MC1600 series), MECl 10K, Pll
(MC12000 series) and the new MECl 10H families.
Chronologically the third family introduced, MECl '" (1968)
is a higher power, higher speed logic. Typical 1 ns edge
speeds and propagation delays along with greater than 500
MHz flip-flop toggle rates, make MECl '" useful for
high-speed test and communications eqUipment. Also, this
family is used in the high-speed sections and critical timing
delays of larger systems. For more general purpose
applications, however, trends in large high-speed systems
showed the need for an easy-to-use logic family with
propagation delays on the order of 2 ns. To match this
requirement, the MECl 10,000 Series was introduced in
1971.
An important feature of MECl 10K is its compatibility with
MECl III to facilitate using both families in the same system.
A second important feature is its significant power economy
- MECl 10K gates use less than one-half the power of
MEClill.
Motorola introduced the MECl 10H product family in 1981.
This latest MECl family features 100% improvements in
propagation delay and clock speeds while maintaining power
supply currents equal to MECl 10K. MECl 10H is voltage
compensated allowing guaranteed dc and switching
parameters over a ±5% power supply range. Noise margins
have been improved by 75% over the MECl 10K series.
Any single supply ECl device is also a PECl device,
making the PECl portfolio as large as the existing ECl one.
(Note: The dual supply translator devices cannot operate at
+5V and ground and cannot be considered PECl devices.)
ECl devices in the PECl mode, must have the input/output
DC specifications adjusted for proper operation. ECl levels
(DC) are referenced from the VCC level. To calculate the PECl
DC specifications, ECl levels are added to the new VCC.
EXAMPLE:
=
=
PECl VOH New VCC + ECl VOH, 5.0V + (-0.81 V)
4.190Vand is the max VOH level at 25°C for a PECl
device. Follow the same procedure to calculate all
input/output DC specifications for a device used in a
PECl mode. The Vn supply used to sink the parallel
termination currents is also referenced from the VCC
supply and is VCC-2.0V. The PECl Vn supply +5V
- 2V
+3.0V and should track the VCC supply
one-to-one for specified operation.
=
=
Since ECl is referenced from the VCC rail, any noise on the
VCC supply will be reflected on the output waveshape at a
one-to-one ratio. Therefore, noise should be kept as low as
possible for best operation. Devices in a PECl system cannot
have VCC vary more than 5% to assure proper AC operation.
See Motorola Application Note AN1406/D "Designing With
PECL (ECL at +S.OV!, for more details.
AC performance in the PECl mode is equal to the AC
performance in the ECl mode, if the pitfalls set forth in
Application Note (ANI406/D) are avoided.
MECL FAMILY COMPARISONS
MECL 10K
Feature
1. Gate Propagation Delay
2. Output Edge Speed'
3. Flip-Flop Toggle Speed
4. Gate Power
S. Speed Power Product
MECL10H
10,100 Series
10,200 Series
MECLIII
1.0 ns
1.0 ns
250 MHz min
25mW
2SpJ
2.0 ns
3.5 ns
125 MHz min
25mW
SO pJ
1.5 ns
2.5 ns
200 MHz min
25mW
37 pJ
1.0 ns
1.0 ns
300-500 MHz min
60mW
60pJ
'Output edge speed: MECL 10Kl10H measured 20% to 80%, MECL III measured 10% to 90% of E out.
Figure 1 -
MOTOROLA
GENERAL CHARACTERISTICS
1-2
MECLData
DL122-Rev6
Ambient
Temperature Range
MECL10H
0° to 75°C
MC10H100 Series
-30°C to +85°C
MECL10K
MECLIII
PLL
MC12000 Series
MC1 01 00 Series
MC10200 Series
MC1600 Series
MC12000 Series
Figure 2 - OPERATING TEMPERATURE RANGE
MECL IN PERSPECTIVE
MECL APPLICATIONS
In evaluating any logic line, speed and power requirements
are the obvious primary considerations. Figure 1 and Figure 2
provide the basic parameters of the MECL 10H, MECL 10K,
and MECL III families. But these provide only the start of any
comparative analysis, as there are a number of other
important features that make MECL highly desirable for
system implementation. Among these:
Complementary Outputs cause a function and its
complement to appear simultaneously at the device outputs,
without the use of external inverters. It reduces package count
by eliminating the need for associated invert functions and, at
the same time, cuts system power requirements and reduces
timing differential problems arising from the time delays
introduced by inverters.
High Input Impedance and Low Output Impedance
permit large fan out and versatile drive characteristics.
Insignificant Power Supply Noise Generation, due to
differential amplifier design which eliminates current spikes
even during signal transition period.
Nearly Constant Power Supply Current Drain simplifies
power-supply design and reduces costs.
Low Cross-Talk due to low-current switching in signal
path and small (typically 850 mV) voltage swing, and to
relatively long rise and fall times.
Wide Variety of Functions, including complex functions
facilitated by low power dissipation (particularly in MECL 10H
and MECL 10K series). A basic MECL 10K gate consumes
less than 8 mW in on-chip power in some complex functions.
Wide Performance Flexibility due to differential amplifier
design which permits MECL circuits to be used as linear as
well as digital circuits.
Transmission Line Drive Capability is afforded by the
open emitter outputs of MECL devices. No "Line Drivers" are
listed in MECL families, because evetydevice is a line driver.
Wire-ORing reduces the number of logic devices required
in a design by producing additional OR gate functions with
only an interconnection.
Twisted Pair Drive Capability permits MECL circuits to
drive twisted-pair transmission lines as long as 1000 feet.
Wire-Wrap Capability is possible with the MECL 10K
family because of the slow rise and fall time characteristic of
the circuits.
Open Emitter-Follower Outputs are used for MECL
outputs to simplify signal line drive. The outputs match any line
impedance and the absence of internal pulldown resistors
saves power.
Input Pulldown Resistors of approximately 50 kn permit
unused inputs to remain unconnected for easier circuit board
layout.
Motorola's MECL product lines are designed for a wide
range of systems needs. Within the computer market, MECL
10K is used in systems ranging from special purpose
peripheral controllers to large mainframe computers. Big
growth areas in this market include disk and communication
channel controllers for larger systems and high performance
minicomputers.
The industrial market primarily uses MECL for high
performance test systems such as IC or PC board testers.
However, the high bandwidths of MECL 10H, MECL 10K,
MECL III, and MC12,OOO are required for many frequency
synthesizer systems using high speed phase lock loop
networks. MECL has continued to grow in the industrial
market through complex medical electronic products and high
performance process control systems.
MECLData
DL122-Rev6
BASIC CONSIDERATIONS FOR HIGH-SPEED
LOGIC DESIGN
High-speed operation involves only four considerations
that differ significantly from operation at low and medium
speeds:
1. Time delays through interconnect wiring, which may
have been ignored in medium-speed systems, become highly
important at state-of-the-art speeds.
2. The possibility of distorted waveforms due to reflections
on signal lines increases with edge speed.
3. The possibility of "crosstalk" between adjacent signal
leads is proportionately increased in high-speed systems.
4. Electrical noise generation and pick-up are more
detrimental at higher speeds.
In general, these four characteristics are speed-- and
frequency-dependent, and are virtually independent of the
type of logic employed. The merit of a particular logic family is
measured by how well it compensates for these deleterious
effects in system applications.
The interconnect-wiring time delays can be reduced only by
reducing the length of the interconnecting lines. At logic
speeds of two nanoseconds, an equivalent "gate delay" is
introduced by every foot of interconnecting wiring. Obviously,
for functions interconnected within a single monolithic chip,
the time delays of signals travelling from one function to
another are insignificant. But for a great many externally
interconnected parts, this can soon add up to an appreciable
delay time. Hence, the greater the number of functions per
chip, the higher the system speed. MECL circuits, particularly
those of the MECL 10K and MECL 10H Series are designed
with a propensity toward complex functions to enhance overall
system speed.
1--3
MOTOROLA
rn
Waveform distortion due to line reflections also becomes
troublesome principally at state-of-the-art speeds. At slow
and medium speeds, reflections on interconnecting lines are
not usually a serious problem. At higher speeds, however, line
lengths can approach the wavelength of the Signal and
improperly terminated lines can result in reflections that will
cause false triggering (see Figure 3 and Figure 4). The
solution, as in RF technology, is to employ '1ransmission-line"
practices and properly terminate each signal line with its
characteristic impedance at the end of its run. The
low-impedance, emitter-follower outputs of MECL circuits
facilitate transmission-line practices without upsetting the
voltage levels of the system.
The increased affinity for crosstalk in high-speed circuits is
the result of very steep leading and trailing edges (fast rise and
fall times) of the high-speed signal. These steep wavefronts
are rich in harmonics that couple readily to adjacent circuits.
In the design of MECL 10K and MECL 10H, the rise and fall
times have been deliberately slowed. This reduces the affinity
for crosstalk without compromising other important
performance parameters.
From the above, it is evident that the MECL logic line is not
simply capable of operating at high speed, but has been
specifically deSigned to reduce the problems that are normally
~ssociated with high-speed operation.
-€=8"_
_€=8"_
A
Vn=-2VDC
I
Po
RECEIVING GATE
INPUT A
I
I
I
I,
I I
I.,A,
I
'::
~
I
1\.f.\.LOW
I
' I
I I
n{\
HIGH
HIGH
{V..r-/
I
..
I
I
\
:'
V
RECEIVING GATE
INPUT A
LOW
"(
,
I
~'V
"
\I
Figure 3 - UNTERMINATED
TRANSMISSION LINE
(No Ground Plane Used)
MOTOROLA
Figure 4 -
PROPERLY TERMINATED
TRANSMISSION LINE
(Ground Plane Added)
1-4
MECL Data
DL122-Rev6
GATE CIRCUIT
MULTIPLE
INPUTS
~
DIFFERENTIAL
AMPLIFIER
,...----A---..
BIAS
NElWORK
GATE TRANSFER CURVES
COMPLEMENTARY
OUTPUTS
,...----A---..
~
-o.aoo
VCC2 (GND)~CCl (GND)
-
2. -1 200
J'
OR
-I--+-- -
HIGH (-0.90 V
TYP.)
~
VaB '" -1.29 V
~
~ -1.6001---1+---'\1--
:3 -l.BOO
NOR
LOW (-1.75 V
TYP.)
L -...........J-'-'--".J.....J'----I
-1.400 -1.200
INPUT VOLTAGE
(VOLTS)
A
B~ A+B+C+D
g.:::Tl----6-
VEE (-5.2 V)
A + B + D+ C
GATE SYMBOL
Figure 5 - MECL 10K GATE STRUCTURE AND SWITCHING BEHAVIOR
CIRCUIT DESCRIPTION
The typical MECL 10K circuit, Figure 5, consists of a
differential-amplifier input circuit, a temperature and voltage
compensated bias network, and emitter-follower outputs to
restore dc levels and provide buffering for transmission line
driving. High fan-out operation is possible because olthe high
input impedance of the differential amplifier input and the low
output impedance of the emitter follower outputs.
Power-supply noise is virtually eliminated by the nearly
constant current drain of the differential amplifier, even during
the transition period. Basic gate design provides for
simultaneous output of both the OR function and its
complement, the NOR function. The design of the MECL 10H
gate is unchanged, with two exceptions. The bias network has
been replaced with a voltage regulator, and the differential
amplifier source resistor has been replaced with a constant
current source. (See section 2 for additional MECL 10H
information.)
Power-8upply Connections - Any of the power supply
levels, VTT, VCC, orVEE may be used as ground; however, the
use of the VCC node as ground results in best noise immunity.
In such a case: Vce = 0, VTT = -2.0 V, VEE = -5.2 V.
System Logic Specifications - The output logic swing of
0.85 V, as shown by the typical transfer characteristics curve,
varies from a LOW state of VOL = -1.75 V to a HIGH state of
VOH = -D.9 V with respect to ground.
Positive logic is used when reference is made to logical "O's"
or "1 's." Then
"0" =-1.75 V = LOW
typical
"1" = -0.9 V = HIGH
MECLData
DL122-Rev6
Circuit Operation - Beginning with all logic inputs LOW
(nominal -1.75 V), assume that 01 through 04 are cut off
because their P-N base-emitter junctions are not conducting,
and the forward-biased 05 is conducting. Under these
conditions, with the base of 05 held at -1.29 V by the VBB
network, its emitter will be one diode drop (0.8 V) more
negative than its base, or -2.09 V. (The 0.8 V differential is a
characteristic of this P-N junction.) The base-te-emitter
differential across 01 - 04 is then the difference between the
common emitter voltage (-2.09 V) and the LOW logic level
(-1.75 V) or 0.34 V. This is less than the threshold voltage of
01 through 04 so that these transistors will remain cut off.
When anyone (or all) of the logic inputs are shifted upward
fromthe-1.75 V LOW state to the-D.9 V HIGH state, the base
voltage of that transistor increases beyond the threshold point
and the transistor turns on. When this happens, the voltage at
the common-emitter point rises from -2.09 V to -1.7 (one
diode drop below the -0.9 V base voltage of the input
transistor), and since the base voltage of the fixed-bias
transistor (05) is held at -1.29 V, the base-emitter voltage 05
cannot sustain conduction. Hence, this transistor is cut off.
This action is reversible, so that when the input signal(s)
return to the LOW state, 01 - 04 are again turned off and 05
again becomes forward biased. The collector voltages
resulting from the switching action of 01 - 04 and 05 are
transferred through the output emitter-follower to the output
terminal. Note that the differential action of the switching
transistors (one section being off when the other is on)
furnishes simultaneous complementary signals at the output.
This action also maintains constant power supply current
drain.
1-5
MOTOROLA
DEFINITIONS OF LETTER SYMBOLS AND ABBREVIATIONS
Current:
rn
ICC
Total power supply current drawn from the
positive supply by a MECL unit under test.
VCCI
Most positive power supply voltage (output
·devices). (Usually ground for MECL devices.)
ICBO
Leakage current from input transistor on MECL
devices without pulldown resistors when test
voltage is applied.
VCC2
ICCH
Current drain from VCC power supply with all
inputs at logic HIGH level.
VEE
ICCL
Current drain from VCC power supply with all
inputs at logic LOW level.
VF
IE
Total power supply current drawn from a MECL
test unit by the negative power supply.
VIH
VIH max
IF
Forward diode current drawn from an input of a
saturated logic--te-MECL translator when that
input is at O.4V.
lin
Current into the input of the test unit when a
maximum logic HIGH (VIH max) is applied at that
input.
VIHA
Most positive power supply voltage (current
switches and bias driver). (Usually ground for
MECL devices.)
Most negative power supply voltage for a circuit
(usually -5.2 V for MECL devices).
Input voltage for measuring IF on TTL interface
circuits.
Input logic HIGH voltage level (nominal value).
Maximum HIGH level input voltage: The most
positive (least negative) value of high-level input
voltage, for which operation of the logic element
within specification limits is guaranteed.
Input logic HIGH threshold voltage level.
VIHA min
Minimum input logic HIGH level (threshold)
voltage for which performance is specified.
IINH
HIGH level input current into a node with a
specified HIGH level (VIH max) logic voltage
applied .to that node. (Same as lin for positive
logic.)
VIH min
Minimum HIGH level input voltage: The least
positive (most negative) value of HIGH level input
voltage for which operation of the logic element
within specification limits is guaranteed.
IINL
LOW level input current, into a node with a
specified LOW level (VIL min) logic voltage
applied to that node.
VIL
Input logic LOW voltage level (nominal value).
VIL max
Maximum LOW level input voltage: The most
positive (least negative) value of LOW level input
voltage for which operation of the logic element
within specification limits is guaranteed.
Inpui logic LOW threshold voltage level.
IL
Load current that is drawn from a MECL circuit
output when measuring the output HIGH level
voltage.
10H
HIGH level output current: the current flowing into
the output, at a specified HIGH level output
voltage.
10L
LOW level output current: the current flowing into
the output, at a specified LOW level output
voltage.
lOS
Output short circuit current.
lout
Output current (from a device or circuit, under
such conditions mentioned in context).
IA
Aeverse current drawn from a transistor input of
a test unit when VEE is applied to that input.
lA'
Aeverse current leakage into an input of a
saturated logic MECUPECL translator when that
input is at VCC.
ISC
Short-circuit current drawn from a translator
saturating output when that output is at ground
potential.
Voltage:
VILA
VILA max
Maximum input logic LOW level (threshold)
voltage for which performance is specified.
VIL min
Minimum LOW level input voltage: The least
positive (most negative) value of LOW level input
voltage for which operation of the logic element
within specification limits is guaranteed.
Yin
Vmax
Input voltage (to a circuit or device).
Maximum (most positive) supply voltage,
permitted under a specified set of conditions.
VOH
Output logic HIGH voltage level: The voltage level
at an output terminal for a specified output
current, with the specified conditions applied to
establish a HIGH level at the output.
Output logic HIGH threshold voltage level.
VOHA
VOHA min Minimum output HIGH threshold voltage level for
which performance is specified.
VOH max Maximum output HIGH or high-level voltage for
given inputs.
VOH min
VBS
. Aeference bias supply voltage.
VBE
Base-to-emitter voltage drop of a transistor at
specified collector and base currents.
VCS
Collector-te-base voltage drop of a transistor at
specified collector and base currents.
VCC
General term for the most positive power supply
voltage to a MECL device (usually ground, except
for translator and interface circuits).
MOTOROLA
VOL
Minimum output HIGH or high-level voltage for
given inputs.
Output logic LOW voltage level: The voltage level
at the output terminal for a specified output
current, with the specified conditions applied to
establish a LOW level at the output.
Output logic LOW threshold voltage level.
VOLA
VOLA max Maximum output LOW threshold voltage level for
which performance is specified.
1-6
MECLData
DL122-Rev6
Voltage (cont.):
VOL max
VOL min
VTT
Maximum output LOW level voltage for given
inputs.
Minimum output LOW level voltage for given
inputs.
Line load-resistor terminating voltage for outputs
from a MECL device.
Time Parameters:
tWSA
Address setup time prior to write
twHA
twscs
Address hold time after write
Chip select setup time prior to write
twHCS
Chip select hold time after write
tws
Write disable time
tWR
Write recovery time
Temperature:
t+
Waveform rise time (LOW to HIGH), 10% to 90%,
or 20% to 80%, as specified.
t-
Waveform fall time (HIGH to LOW), 90% to 10%,
or 80% to 20%, as specified.
Maximum temperature at which device may be
stored without damage or performance
degradation.
tr
tf
t+t-+
Same as t+
Same as tPropagation Delay, see Figure 12 on page 1-13.
Propagation Delay, see Figure 12 on page 1-13.
Junction (or die) temperature of an integrated
circuit device.
Ambient (environment) temperature existing in
the immediate vicinity of an integrated circuit
device package.
tpd
Propagation delay, input to output from the 50%
paint of the input waveform at pin x (falling edge
noted by - or rising edge noted by +) to the 50%
point of the output waveform at pin y (falling edge
noted by - or rising edge noted by +). (Cf
Figure 12 on page 1-13.)
eJA
Output waveform rise time as measured from
10% to 90% or 20% to 80% points on waveform
(whichever is specified) at pin x with input
conditions as specified.
Output waveform fall time as measured from 90%
to 10% or 80% to 20% points on waveform
(whichever is specified) at pin x, with input
conditions as specified.
eCA
tx±y±
t x-
fTog
f shift
Tstg
Ifpm
Toggle frequency of a flip-flop or counter device.
Shift rate for a shift register.
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode (Memories)
tw
twso
tWHD
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
MECLData
DL122-Rev6
Thermal resistance of an IC package, junction to
case.
Linear feet per minute.
Thermal resistance of an IC package, case to
ambient.
Miscellaneous:
Read Mode (Memories)
tACS
tRCS
tAA
Thermal resistance of an IC package, junction to
ambient.
1-7
eg
TPin
Signal generator inputs to a test circuit.
Test point at input of unit under test.
TPout
D.U.T.
Test point at output of unit under test.
Cin
Input capaCitance.
Cout
Zout
Po
Output capacitance.
Device under test.
Output impedance.
The total dc power applied to a device, not
including any power delivered from the device to
a load.
RL
Load Resistance.
RT
Rp
Terminating (load) resistor.
An input pull-down resistor (i.e., connected to the
most negative voltage).
P.U.T.
Pin under test.
MOTOROLA
MECL POSITIVE AND NEGATIVE LOGIC
INTRODUCTION
The increasing popularity and use of emitter coupled logic
has created a dilemma for some logic designers. Saturated
logic families such as TTL have traditionally been designed
with the NAND function as the basic logic function, however,
the basic ECl logic function is the NOR function (positive
logic). Therefore, the designer may either design ECl
systems with positive logic using the NOR, or design with
negative logic using the NAND. Which is the more
convenient? On the one hand the designer is familiar with
positive logic levels and definitions, and on the other hand, he
is familiar with implementing systems using NAND functions.
Perhaps a presentation of the basic definitions and
characteristics of positive and negative logic will clarify the
situation and eliminate misunderstanding.
Vee=gnd
VBB =-t.29 volts
e
VEE = -5.2 volts
Tablet
Figure 6 - Basic MECL Gate Circuit and Logic Function
In Positive and Negative Nomenclature.
Circuit diagrams external to Motorola products are Included as a means of illustrating typical semiconductor applications; consequently, complete information sufficient
for construction purposes is not necessarily given. The information in this Application Note has been carefully checked and is believed to be entirely reliable. However,
no responsibility is assumed forinaccuracias. Furthermore, such informatian does not convey to the purchaser of the semiconductor devices described any license under
the patent rights of Motorola Inc. or others.
MOTOROLA
1-8
MECLData
DL122- Rev 6
LOGIC EQUIVALENCIES
Binary logic must have two states to represent the binary 1
and O. With ECL the typical states are a high level of -~
1-0
::»
a..~
-
~
t\
'- -300;
I
11
'I,
'l
-1.750
-
I
I
85°C
::)
kfc
1
-
PROUTPUT
-300
-1.350
I-
0
85°C
250C'
\\
85!C-\ , - , .-{
25°C_
~,
25°~
NORIOUTP~
--=r--30~
-1.6
I
-1.4
-1.2
-30"C-
-to
INPUT VOLTAGE (VOLTS)
TYPICAL lEVEL CHANGE RATES 11 V
Voltage
MECL10H
MECL10K
.wOH/LlVEE
O.OOB
0.016
0.033
LlVOr..!LlVEE
0.020
0.250
0.270
LlVBslLlVEE
0.010
0.14B
0.140
-
MECLData
DL122-Rev6
regardless of power dissipation or junction temperature
differences to reduce loss of noise margin due to thermal
differences.
All of these specifications assume -5.2 V power supply
operation. Operation at other power-supply voltages is
possible, but will result in further transfer curve changes.
Table 6 gives rate of change of output voltages as a function
of power supply.
1-11
MECLIII
MOTOROLA
NOISE MARGIN
would need an additional voltage, to move the inputfrom VOLA
max to VILA max. This constitutes the "safety factor" known as
noise margin. It can be calculated as the magnitude of the
difference between the two specification voltages, or for the
MECL 10K levels shown:
"Noise margin" is a measure of logic circuit's resistance
to undesired switching. MECL noise margin is defined in
terms of the specification points surrounding the switching
threshold. The critical parameters of interest here are those
designated with the "A" subscript (VOHA min, VOLA max,
VIHA min, VILA max) in the transfer characteristic curves.
MECL 10H is specified and tested with:
VOHA min = VOH min
VOLA max =VOL max
VIHA min = VIH min
and
NMLOW
- VILA max - VOLA max
--1.475 V -(-1.630 V)
-155mV.
Similarly, for the HIGH state:
NMHIGH - VOHA min - VIHA min
--0.980 V - (-1.105 V)
-125mV
VILA max = VIL max
Guaranteed noise margin (NM) is defined as follows:
NMHIGH LEVEL = VOHA min - VIHA min
NMLOW LEVEL =VILA max - VOLA max
To see how noise margin is computed, assume a MECL
gate drives a similar MECL gate, Figure 11.
At a gate input (point B) equal to VILA max, MECL gate #2
can begin to enter the shaded transition region.
This is a ''worst case" condition, since the VOLA max
specification point guarantees that no device can enter the
transition region before an input equal to VILA max is reached.
Clearly then, VILA max is one critical point for noise margin
computation, since it is the edge of the transition region.
To find the other critical voltage, consider the output from
MECL gate #1 (point A). What is the most positive value
possible for this voltage (considering worst case
specifications)? From Figure 11 it can be observed that the
VOLA max specification insuresthalthe LOW state OR output
from gate #1 can be no greater than VOLA max·
NotethatVOI:.AmaxismorenegativethanVILAmax·Thus,
with VOLA max althe inpulto gate #2, the transition region is
not yet reached. (The input voltage to gate #2 is still to the left
of VILA max on the transfer curve.)
In order to ever run the chance of switching gate #2, we
Analogous results are obtained when considering the
"NOR" transfer data.
Note that these noise margins are absolute worst case
conditions. The lessor of the two noise margins is that for the
HIGH state, 125 mV. This then, constitutes the guaranteed
margin against signal undershoot, and power or thermal
disturbances.
As shown in the table, typical noise margins are usually
betterthanguaranteed-byabout75mV.ForMECL10Hthe
"noise margin" is 150 mV for NM low and NM high. (See
Section 3 for details.)
Noise margin is a dc specification that can be calculated,
since it is defined by specification points tabulated on MECL
data sheets. However, by itself, this specification does not
give a complete picture regarding the noise immunity of a
system built with a particular set of circuits. Overall system
noise immunity involves not only nOise-margin specifications,
but also other circuit-related factors that determine how
difficult it is to apply a noise signal of sufficient magnitude and
duration to cause the circuilto propagate a false logic state.
In general, then, noise immunity involves line impedances,
circuit output impedances, and propagation delay in addition
to noise-margin specifications. This subject to discussed in
greater detail in the MECL System Design Handbook, HB205.
Figure 11 - MECL Noise Margin Data
-------\S~
-1.475
-1.105
OR
VOHAMIN
t
-0.980
dV
}
GATE
INPUr-
VILA MAX
LOW
STATE
~
---L.---O-
VILA MAX ,
VOLA MAX'
Guaranteed
Worst-Case de
Noise Margin
(V)
Typlealde
Noise Margin
(V)
MECL10H
0.150
0.270
MECL 10K
0.125
0.210
MECLIII
0.115
0.200
Family
C
Margin
Noise Margin Computations
VIHA MIN
Specification Points for Determining Noise Margin
= Low.Noise {.
'VOHA min =VOH min. VOLA max =
VOL max. VIHA min = VIH min and .
VILA max = VIL max for MECL 10H.
Vee (SWITCHING THRESHOLD)
~
VOHAMIN'
HIGH .
} STATE
- f + - t - - - -1.630
GATE
OUTPUT
'dV = High .Noise {
Margin
AC OR SWITCHING PARAMETERS
MOTOROLA
1-12
MECLData
DL122-Rev6
lime-dependent specifications are those that define the
effects of the circuit on a specified input signal, as it travels
through the circuit. They include the time delay involved in
changing the output level from one logic state to another. In
addition, they include the time required for the output of a
circuit to respond to the input signal, designated as
propagation delay, MECL waveform and propagation delay
Figure 12 -
terminologies are depicted in Figure 12. Specific rise, fali, and
propagation delay times are given on the data sheet for each
specific functional block, but like the transfer characteristics,
ac parameters are temperature and voltage dependent.
Typical variations for MECL 10K are given in the curves of
Figure 13 through Figure 16.
TYPICAL LOGIC WAVEFORMS
OVERSHOOT!~-~~~~~~~f~~~~~rf~~~~-~~H:IG;H~L:EVEL
UNDERSHOOT !
SO%
VIHA
VILA
VSS
UNDERSHOOT {
LOW LEVEL
VOUTOR
MECL WAVEFORM TERMINOLOGY
-'T-+'~r
VOUTNOR~
VOUT
+-~
'TPD=T-+T++
T-=TF
MECL III Rise and Fall Times
T+=TR
MECL 10K and MECL 10H Rise and Fall Times
Figure 14 - TYPICAL PROPAGATION DELAY 1+ + versus
VEE AND TEMPERATURE (MECL 10K)
Figure 13 - TYPICAL PROPAGATION DELAY 1- - versus
VEE AND TEMPERATURE (MECL 10K)
2.6
2.S _ I
"'E-
2.3
z
2.2
-
OR
2.4
~
w
0
SOQILOADITO-2.~V
1-:::::=
2.S
J
+8so
2SoCj
-30°c
~
--
t--
2.0
l-
0
a: 1.9
a.
I
1.8
..!.
1.7
1.6
2.3
z
2.1
0
~ 2.1
(!l
-3.6
MECLData
DL122-Rev6
NOR
--
I--!----
-4.4
-5.2
-<>.0
VEE, SUPPLY VOLTAGE (VOLTS)
f--:
~ 2.0
1f
0
1.9
a:
a. 1.8
.... -30°c
I
2.2
(!l
8Soc
2Soc
_
2.4
'wS
0
0
1f
MECL Propagation Delay
I
.1:
1.7
-
so
bLOA~
:-~
.........
-
r-
TO
-~.O V
-
I
I
NOR
OR
......
V
~
85°C I
I
25°C
-30°c
. / 85°C
.-l25°c
-30°c
/
1.6
1.5"
-6.8
-3.6
1-13
-4.4
-5.2
-6.0
VEE, SUPPLY VOLTAGE (VOLTS)
-6.8
MOTOROLA
Figure 15 - TYPICAL FALL TIME (90% to 10%) versus
TEMPERATURE AND SUPPLY VOLTAGE (MECL 10K)
3.9
3.8
w
Ll:
r-..., ...........
Iii'
.s 3.6
:::;; 3.5
i= 3.4
-'
-' 3.3
..C 3.2
3.1
r--
-
85'C I
4.8
25'ci
-aO'C
4.6
w
;::: 4.4
w 4.2
Ul
~
........... .......
r--
3.0
2.9
5.2
5.0
I.
50 Q LOAD TO-2.0V
-_,"-NOR
r-- -
3.7
[I]
50 Q LOAD TO -2.0 V
r-...,-t--
r=::::: ::::::-
:::0
3.8
~
-r-- - r--
"-t--
-4.4
-5.2
-6.0
VEE, SUPPLY VOLTAGE (VOLTS)
3.6
85'C
25'C
-3Q'C
-6.8
........
-----
t-....
~ t--
3.4
3.2
I
NOR
a: 4.0
.£
f-...
-a.6
Figure 16 - TYPICAL FALL TIME (10% to 90%) versus
TEMPERATURE AND SUPPLY VOLTAGE (MECL 10K)
-a.6
- -
85'CI
25'CI
-aO'C
I
dR
85'C
25'C
-3Q'C
I
-4.4
-5.2
-6.0
VEE, SUPPLY VOLTAGE (VOLTS)
I
I
-6.8
SETUP AND HOLD TIMES
Setup and hold times are two ac parameters which can
easily be confused unless clearly defined. For MECL logic
devices, tsetup is the minimum time (SO% - SO%) before the
positive transition of the clock pulse (C) that information must
be present at the Data input (D) to insure proper operation of
the device. The thold is defined similarly as the minimum time
after the positive transition of the clock pulse (C) that the
information must remain unchanged at the Data input (D) to
insure proper operation. Setup and hold waveforms for logic
devices are shown in Figure 17.
Figure 17 - SETUP AND HOLD WAVEFORMS
FOR MECL LOGIC DEVICES
D----'
C-----1f-JI
:---------)('-----
TESTING MECL 10H, MECL 10K AND MECL III
To obtain results correlating with Motorola circuit
specifications certain test techniques must be used. A
schematic of a typical gate test circuit is shown in Figure 18.
This test circuit is the standard ac test configuration for most
MECL devices. (Exceptions are shown with device
specification.)
.
A solid ground plane is used in the test setup, and
capacitors bypass VCC1, VCC2, and VEE pins to ground. All
power leads and signal leads are kept as short as possible.
The sampling scope interface runs directly to the SO-ohm
inputs of Channel A and B via SD-ohm coaxial cable.
Equal-length coaxial cables must be used between the test
set and the A and B scope inputs. A SO-ohm coax cable such
as RGS8/U or RG188A1U, is recommended.
Interconnect fittings should be SD-ohm GR, BNC, Sealectro
Con hex, or equivalent. Wire length should be < X inch from
TPin to input pin and TPout to output pin.
The pulse generator must be capable of 2.0 ns rise and
MOTOROLA
fall times for MECL 1OKand l.S ns for MECL 1OH and MECL
III. In addition, the generator voltage must have an offset to
give MECL signal swings of = ±400 mV about a threshold of
= +0.7 Vwhen VCC = +2.0 and VEE =-3.2 V for ac testing
of logic devices.
The power supplies are shifted +2.0 V, so that the device
under test has only one resistor value to load into the precision
SO-ohm input impedance of the sampling oscilloscope. Use
of this technique yields a close correlation between Motorola
and customer testing. Unused outputs are loaded with a
SD-ohm resistor (10D-ohm for MC10SXX devices) to ground.
The positive supply (VCC) should be decoupled from the test
board by RF type 2S !1F capacitors to ground. The VCC pins
are bypassed to ground with 0.1 !1F, as is the VEE pin.
Additional information on testing MECL 10K and
understanding data sheets is found in Application Note AN701
and the MECL System Design Handbook, HB20S.
1-14
MECLData
DL122-Rev6
Figure 1B -
MECL LOGIC SWITCHING TIME TEST SETUP
CHANNEL A
CHANNELB
• Matched SD-ohm coax
"'. 0.1 j.1F-decouples fixture
..... 25 j.1F-dampens supply variations
PULSEtt
GENERATOR
ttPulse generator must be capable of rise
and fall times 2.0 ns for 10K and
1.0 ns for 10H and MECL III.
NOTE: All power supply levels
are shown shifted 2 volts
positive.
+2.0 V
Vec
MECLData
DL122-Rev6
1-15
-3.2 V
VEE
MOTOROLA
SECTION III -
OPERATIONAL DATA
POWER SUPPLY CONSIDERATIONS
MECL circuits are characterized with the VCC point at
ground potential and the VEE point at -5.2 V. While this MECL
convention is not necessarily mandatory, it does result in
maximum noise immunity. This is so because any noise
induced on the VEE line is applied to the circuit as a
common-mode signal which is rejected by the differential
action of the MECL input circuil. Noise induced into the VCC
line is not cancelled out in this fashion. Hence, a good system
ground at the VCC bus is required for best noise immunity.
Also, MECL 1OH circuits may be operated with VEE at -4.5 V
with a negligible loss of noise immunity.
Power supply regulation which will achieve 10% regulation
or better at the device level is recommended. The -5.2 V
power supply potential will result in best circuit speed. Other
values for VEE may be used. A more negative voltage will
increase noise margins at a cost of increased power
dissipation. A less negative voltage will have just the opposite
effect. (Noise margins and performance specifications of
MECL 1OH are unaffected by variations in VEE because olthe
internal voltage regulation.)
On logic cards, a ground plane or ground bus system should
be used. A bus system should be wide enough to prevent
significant voltage drops between supply and device and to
produce a low source inductance.
Although little power supply noise is generated by MECL
logic, power supply bypass capacitors are recommended to
handle switching currents caused by stray capacitance and
asymmetric circuit loading. A parallel combination of a 1.0 j!F
and a 100 pF capacitor at the power entrance to the board, and
a 0.01 j!F low-inductance capacitor between ground and the
-5.2 V line every four to six packages, are recommended.
Most MECL 1OH, MECL 10K and MECL III circuits have two
VCC leads. VCC1 supplies currenttothe outputtransistors and
VCC2 is connected to the circuit logic transistors. The separate
VCC pins reduce cross-coupling between individual circuits
within a package when the outputs are driving heavy loads.
Circuits with large drive capability, similar to the MC10110,
have two VCC1 pins. All VCC pins should be connected to the
ground plane or ground bus as close to the package as
possible.
For further discussion of MECL power supply
considerations to be made in system designing, see MECL
System Design Handbook, HB205.
POWER DISSIPATION
The power dissipation of MECL functional blocks is
specified on their respective data sheets. This specification
does not include power diSSipated in the output devices due
to output termination. The omission of internal output pulldown
resistors permits the use of external terminations designed to
yield best system performance. To obtain total operating
power dissipation of a particular functional Dlock in a system,
the dissipation of the output transistor, under load, must be
added to the circuit power dissipation.
Table 7 lists the power dissipation in the output transistors
plus that in the external terminating resistors, for the more
MOTOROLA
commonly used termination values and circuit configurations.
To obtain true package power dissipation, one outputtransistor power-~
250
500
AIRFLOW (Ifpm)
Table 9 - THERMAL GRADIENT OF JUNCTION
TEMPERATURE
(16-Pin MECL Dual-ln-Line Package)
Power Dissipation
(mW)
Junction Temperature Gradient
('C/Package)
200
0,4
250
0,5
300
0.63
400
0,88
Devices mounted on 0,062" PC board with Z axis spacing 0.5", Air flow is
500 Ifpm along the Z axis,
The majority of MECL 10H,MECL 10K, and MECL III users
employ some form of air-flow cooling. As air passes over each
device on a printed circuit board, it absorbs heat from each
package. This heat gradient from the first package to the last
package is a function of the air flow rate and individual
package dissipations. Table 9 provides gradient data at power
levels of 200 mW, 250 mW, 300 mW, and 400 mW with an air
flow rate of 500 Ifpm. These figures show the proportionate
MOTOROLA
750
1000
increase in the junction temperature of each dual-in-line
package as the air passes over each device. For higher rates
of air flow the change in junction temperature from package to
package down the airstream will be lower due to greater
cooling.
OPTIMIZING THE LONG TERM RELIABILITY OF
PLASTIC PACKAGES
Todays plastic integrated circuit packages are as reliable as
ceramic packages under most environmental conditions.
However when the ultimate in system reliability is required,
thermal management must be considered as a prime system
design goal.
Modern plastic package assembly technology utilizes gold
wire bonded to aluminum bonding pads throughout the
electronics industry. When exposed to high temperatures for
protracted periods oftime an intermetallic compound can form
in the bond area resulting in high impedance contacts and
degradation of device performance. Since the formation of
intermetallic compounds is directly related to device junction
temperature, it is incumbent on the designer to determine that
the device junction temperatures are consistent with system
reliability goals.
1-20
MECL Data
DL122-Rev6
Predicting Bond Failure Time:
MECL Junction Temperatures:
Based on the results of almost ten (10) years of +125°C
operating life testing, a special arrhenius equation has been
developed to show the relationship between junction
temperature and reliability.
(1) T
=
Power levels have been calculated for a number of MECL
10K and MECL 10H devices in 20 pin plastic leaded chip
carriers and translated to the resulting increase of junction
temperature (8TJ) for still air and moving air at 500 LFPM
using equation 2 and are shown in Table 11.
(6.376 x 10-9)e[ 11554.267 ]
273.15 + T J
Time in hours to 0.1 % bond failure (1 failure
per 1,000 bonds).
Device junction temperature, °C.
Where:T
Table 11 -INCREASE IN JUNCTION TEMPERATURE
DUE TO IIC POWER DISSIPATION.
20 PIN PLASTIC LEADED CHIP CARRIER
And:
=
=
(2) TJ TA + PD8JA TA + 8TJ
Device junction temperature, cC.
Where:TJ
Ambient temperature, cC.
TA
Device power dissipation in watts.
PD
Device thermal resistance, junction to air,
8JA
°ClWatt.
8TJ
Increase in junction temperature due to
on-chip power dissipation.
Device
Type
MC10101
MC10102
MC10103
MC10104
MC10105
MC10106
MC10107
MC10109
MC10110
MC10111
MC10113
MCI0114
MC10115
MC10116
MC10117
MC10121
MC10123
MC10124
MC10125
MC10131
MC10133
MC10134
MC10135
MC10136
MC10138
MC10141
MC10153
MC10158
MC10159
MC10160
MC10161
MC10162
MC10164
MC10165
MC10166
MC10168
MC10170
MC10171
MC10172
MC10173
MC10174
MC1017S
MC10176
MC10178
MC10186
MC10188
MC10189
MC10192
MC10195
MC10197
MC10198
MC10210
MC10211
MC10212
MC10216
MC10231
Table 10 shows the relationship between junction
temperature, and continuous operating time to 0.1% bond
failure, (1 failure per 1,000 bonds).
Table 10- DEVICE JUNCTION TEMPERATURE
versus TIME TO 0.1% BOND FAILURES
Junction
Temperature 'C
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
Table 10 is graphically illustrated in Figure 26 which shows
that the reliability for plastic and ceramic devices are the same
until elevated junction temperatures induces intermetallic
failures in plastiC devices. Early and mid-life failure rates of
plastic devices are not effected by this intermetallic
mechanism.
Figure 26. FAILURE RATE versus TIME
JUNCTION TEMPERATURE
w
!;;:
~
3
~
;
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
~
~ I~
~
~
~
r-~- ~
11'11
~
~
J.
~--g-
P
~
~
~
~
P-,f-H-t-HtH
~
IT
100
"TJ'oC
SIIIIAI,
500LFPM
21.8
14.1
11.4
17.6
17.6
20.8
17.2
13.0
19.8
11.7
AI,
11.4
13.4
11.2
8.4
12.8
MECl10H
Device
Type
MC10H016
MC10H100
MC10H101
MC10H102
MC10H103
MC10H104
MC10H105
MC10Hl06
MC10H107
MC10H109
22.2
7.7
16.1
16.1
14.3
22.6
16.7
14.6
MC10H115
10.9
MC1QH116
17.2
11.1
16.2
13.5
37.6
42.9
10.5
8.5
MC10H117
MC10H121
MC10H123
MC10H124
MC10H125
MC1OH130
MC10H135
MC10H13B
MC10H141
MC10H145
MC10H158
MC10H159
MC10H160
MC10H161
MC1QH162
MC10H164
MC10H165
MC10H166
MC10H171
MC10H172
MC10H173
MC10H174
MC10H175
MC10H176
MC10H179
MC10H180
MC10H181 4
MC10H186
MC10H188
MC10H189
MC10H209
MC10H210
MC10H211
MC10H3304
MC10H332
MC10H334
MC10H350
MC10H351
MC10H352
MC10H424
24.7
24.7
-
24.0
27.3
-
26.9
17.1
34.4
21.9
27.0
31.9
52.3
37.0
42.7
34.4
23.9
25.8
32.0
40.7
40.7
31.3
53.7
43.5
34.4
29.9
41.1
41.1
30.5
31.9
43.7
49.8
38.1
49.6
25.4
24.6
67.0
48.7
27.7
21.2
24.5
24.6
24.3
24.1
30.6
17.2
20.3
32.6
23.2
26.7
21.9
15.2
16.4
20.4
26.0
26.0
20.1
33.6
27.6
21.9
18.9
26.2
26.2
19.3
20.5
27.6
31.3
23.9
31.1
16.4
15.9
43.0
29.9
17.7
13.4
16.0
16.0
15.6
15.6
19.5
MC1QH113
"TJ'oC
Stili AI,
.6.TJ'oC
500lFPM
AI,
48.0
16.6
22.1
18.0
18.0
21.0
17.8
30.0
10.8
13.2
8.7
12.9
7.8
14.8
20.0
11.9
22.8
16.7
17.8
16.7
13.9
23.1
44.2
-
28.2
33.2
61.7
44.3
59.4
25.3
27.3
32.1
41.5
41.5
31.9
56.3
44.4
41.9
41.9
32.6
32.5
45.9
14.5
11.8
11.8
13.5
11.7
10.9
11.7
11.0
9.1
15.0
28.4
-
18.2
21.4
38.5
28.0
36.9
16.4
17.7
20.5
26.7
26.7
20.6
35.8
28.3
26.9
26.9
21.1
21.0
50.9
35.0
42.4
64.4
50.2
25.8
25.8
18.9
25.0
25.0
65.8
52.2
77.8
29.6
32.3
22.6
27.2
38.6
31.8
16.7
16.7
12.5
16.4
16.4
36.1
33.5
49.3
27.2
27.2
37.7
18.1
18.1
24.3
-
-
NOTES:
(1) All ECLoutpuls are loaded with a50 Q resistor and assumed operating at 50%
duty cycle.
(2) ATJ for Eel to TTL translators are excluded since the supply current to the TTL
section Is dependent on frequency, duty cycle and loading.
(3) Thermal Resistance (6JA) measured with PLCC packages solder attached to
traces on 2.24" x 2.24" x 0.062" FR4 type glass epoxy board with 1 ozJsq. fl.
copper (solder-coated) mounted to tester with 3 leads of 24 gauge copper wire.
(4) 28 lead PlCC.
!i!! 1.0t--t-+-H-H*--t-+-H-Itttt-L-t-H+Htti
10
llTJ'oC
MECl10K
1000
TIME, YEARS
MECLDala
DL122-Rev6
1-21
MOTOROLA
Case Example:
[j]
After the desired system failure rate has been established
for failure mechanisms other than intermetallics, each plastic
device in the system should be evaluated for maximum
junction temperature using Table 11. Knowing the maximum
junction temperature refer to Table' 10 or Equation 1 to
determine the continuous operating time required to 0.1 %
bond failures due to intermetallic formation. At this time,
system reliability departs from the desired value as indicated
in Figure 26.
To illustrate, assume that system ambient air temperature
is 55°C (an accepted industry standard for evaluating system
failure rates). Reference is made to Table 11 to determine the
maximum junction temperature for each device for still air and
transverse air flow of 500 LFPM.
Adding the 55°C ambient to the highest, ~TJ listed, 77.8°C
(for the MC1 OH334 with no airflow), gives a maximum junction
temperature of 132.8°C. Reference to Table 10 indicates a
departure from the desired failure rate after about 2 years of
constant exposure to this junction temperature. If 500 LFPM
of air flow is utilized, maximum junction temperature for this
device is reduced to 104.3°C for which Table 10 indicates an
increased failure rate in about 15 years.
Air flow is one method of thermal management which
should be considered for system longeVity. Other commonly
used methods include heat sinks for higher powered devices,
refrigerated air flow and lower density board stuffing.
The material presented here emphasizes the need to
consider thermal management as an integral part of system
design and also the tools to determine if the management
methods being considered are adequate to produce the
desired system reliability.
THERMAL EFFECTS ON NOISE MARGIN
The data sheet dc specifications for standard MECL 10K
and MECL III devices are given for an operating temperature
range from -30°C to +85°C (0° to +75°C for MECL 10H and
memories). These values are based on having an airflow of
500 Ifpm over socket or PIC board mounted packages with no
special heatsinking (i.e., dual-in-line package mounted on
lead seating plane with no contact between bottom of package
and socket or PIC board and fiat package mounted with
bottom in direct contact with non-metalized area of PIC
board),
The designer may want to use MECL devices under
conditions other than those given above. The majority of the
low-power device types may be used without air and with
higher 9JA. However, the designer must bear in mind that
junction temperatures will be higher for higher 9JA, even
though the ambient temperature is the same. Higher junction
temperatures will cause logic levels to shift.
As an example, a 300 mW 16 lead dual-in-line ceramic
device operated at 9JA = 100°CIW (in still air) shows a HIGH
logic level shift of about 21 mV above the HIGH logic level
when operated with 500 Ifpm air flow and a 9JA 50°CIW.
(Level shift ~TJ x 1.4 mV/°G).
If logic levels of individual devices shift by different amounts
(depending on PD and 9JA), noise margins are somewhat
=
MOTOROLA
reduced. Therefore, the system designer must layout his
system bearing in mind that the mounting procedures to be
used should minimize thermal effects on noise margin.
The following sections on package mounting and
heatsinking are intended to provide the designer with
sufficient information to insure good noise margins and high
reliability in MECL system use.
MOUNTING AND HEATSINK SUGGESTIONS
With large high-speed logiC systems, the use of multilayer
printed circuit boards is recommended to provide both a better
ground plane and a good thermal path for heat dissipation.
Also, a multilayer board allows the use of microstrip line
techniques to provide transmission line interconnections.
Two-sided printed circuit boards may be used where board
dimensions and package count are small. If possible, the VCC
ground plane should face the bottom of the package to form
the thermal conduction plane. If signal lines must be placed on
both sides of the board, the VEE plane may be used as the
thermal plane, and at the same time may be used as a pseudo
ground plane. The pseudo ground plane becomes the ac
ground reference under the signal lines placed on the same
side as the VCC ground plane (now on the oppOSite side olthe
board from the packages), thus maintaining a microstrip signal
line environment.
Two-ounce copper PIC board is recommended for thermal
conduction and mechanical strength. Also, mounting holes for
low power devices may be countersunk to allow the package
bottom to contact the heat plane. This technique used along
with thermal paste will provide good thermal conduction.
Printed channeling is a useful technique for conduction of
heat away from the packages when the devices are soldered
into a printed circuit board. As illustrated in Figure 27, this heat
dissipation method could also serve as VEE voltage
distribution or as a ground bus. The channels should terminate
into channel strips at each side or the rear of a plug-in type
printed circuit board. The heat can then be removed from the
circuit board, or board slide rack, by means of wipers that
come into thermal contact with the edge channels.
Figure 27 -
CHANNEUWIPER HEATSINKING ON
DOUBLE LAYER BOARD
=
1-22
MECLData
DL122-Rev6
For operating some of the higher power device types' in 16
lead dual-in-line packages in still air, requiring 8JA <1 OO°CIW,
a suitable heatsink is the IERC LlC-214A2WCB shown in
Figure 2B. This sink reduces the still air8JA to around 55°CIW.
By mounting this heatsink directly on a copper ground plane
(using silicone paste) and passing 500 Ifpm air over the
packages, 8JA is reduced to approximately 35°CIW, permitting
use at higher ambient temperatures than +B5°C (+75°C for
MECL 1OH memories) or in lowering T J for improved reliability.
Figure 28 - MECL HIGH-POWER DUAL-IN-LiNE
PACKAGE MOUNTING METHOD
It should be noted that the use of a heatsink on the top
surface of the dual-in-line package is not very effective in
lowering the 8JA. This is due to the location of the die near the
bottom surface of the package. Also, very little « 10%) of the
internal heat is withdrawn through the package leads due to
the isolation from the ceramic by the solder glass seals and the
limited heat conduction from the die through 1.0 to 1.5 mil
aluminum bonding wires.
INTERFACING MECL TO SLOWER LOGIC TYPES
MECL circuits are interfaceable with most other logiC forms.
For MECurrUDTL interfaces, when MECL is operated atthe
recommended -5.2 volts and TTUDTL at +5.0 V supply,
currently available translator circuits, such as the MC10124
and MC10125, may be used.
For systems where a dual supply (-5.2 V and +5 V) is not
practical, the MC1 OH350 includes four single supply MECL to
TTL translators, or a discrete component translator can be
designed. For details, see MECL System DeSign Handbook
(HB205). Such circuits can easily be made fast enough for any
available TTL. .
MECL also interfaces readily with MOS. With CMOS
operating at +5 V, any of the MECL to TTL translators works
very well.
Specific circuitry for use in interfacing MECL families to
other logic types is given in detail in the MECL System Design
Handbook.
Complex MECL 10K devices are presently available for
interfacing MECL with MaS logic, MaS memories, TTL
three-state circuits, and IBM bus logic levels. See Application
Note AN-720 for additional interfacing information.
CIRCUIT INTERCONNECTIONS
Though not necessarily essential, the use of multilayer
printed circuit boards offers a number of advantages in the
development of high-speed logic cards. Not only do multilayer
boards achieve a much higher package density,
interconnecting leads are kept shorter, thus minimizing
propagation delay between packages. This is particularly
beneficial with MECL III which has relatively fast (1 ns) rise
and fall times. Moreover, the unbroken ground planes made
possible with multilayer boards permit much more precise
control of transmission line impedances when these are used
for interconnecting purposes. Thus multilayer boards are
recommended for MECL III layouts and are justified when
operating MECL 10H and MECL 10K at top circuit speed,
when high-density package is a requirement, or when
transmission line interconnects are used.
POint-to-point back-plane wiring without matched line
terminations may be employed for MECL interconnections if
line runs are kept short. At MECL 10K speeds, this applies to
line runs up to 6 inches, for MECL 10H and MECL III up to 1
inch (Maximum open wire lengths for less than 100 mV
undershoot). But, because of the open-emitter outputs of
MECL 10H, MECL 10K and MECL III circuits, pull-down
resistors are always required. Several ways of connecting
such pull-down resistors are shown in Figure 29 through
Figure 31.
Resistor values for the connection in Figure 29 may range
from 270 ohms to kQ depending on power and load
requirements. (See MECL System Design Handbook.) Power
may be saved by connecting pull-down resistors in the range
of 50 ohms to 150 ohms, to -2.0 Vdc, as shown in Figure 30.
Use of a series damping resistor, Figure 31, will extend
permissible lengths of unmatched-impedance interconnections, with some loss of edge speed.
With proper choice of the series damping resistor, line
lengths can be extended to any length,.' while limiting
overshoot and undershoot to a predetermined amount.
Damping resistors usually range in value from 10 ohms to 100
ohms, depending on the line length, fanout, and line
impedance, the open emitter-follower outputs of MECL 10H,
MECL III and MECL 10K give the system designer all possible
line driving options.
One major advantage of MECL over saturated logic is its
capability for driving matched-impedance transmission lines.
Use of transmission lines retains signal integrity over long
distances. The MECL 10H and MECL 10K emitter-follower
output transistors will drive a 5~hm transmission line
terminated to -2.0 Vdc. This is the equivalent current load of
22 mA in the HIGH logic state and 6 mA in the LOW state.
, 10129,10136, 10H136, and 10137, Max Po > 800 mW.
MECLDala
DL122-Rev6
"'''' Limited only by line attenuation and band-width characteristics.
1-23
MOTOROLA
rn
Parallel termination of transmission lines can be done in two
ways. One, as shown in Figure 32, uses a single resistor
whose value is equal to the impedance (Zo) of the line. A
terminating voltage (VTT) of -2.0 Vdc must be supplied to the
terminating resistor.
Another method of parallel termination uses a pair of
resistors, R1 and R2. Figure 33 illustrates this method. The
following two equations are used to calculate the values of R1
and R2:
Figure 33 -
PARALLEL TERMINATION - THEVENIN
EQUIVALENT
Rl
R2
R1 = 1.6Zo
R2=2.6 Zo
-5.2 V
Another popular approach is the series-terminated
transmission line (see Figure 32 and Figure 33). This differs
from parallel termination in that only one-half the logic swing
is propagated through the lines. The logic swing doubles atthe
end of the transmission line due to reflection on an open line,
again establishing a full logic swing.
Figure 34 -
SERIES TERMINATED LINE
PULL-DOWN RESISTOR TECHNIQUES
Rp
-S.2V
Figure 29
Figure 30
Figure 31
-5.2 V
To maintain clean wave fronts, the input impedance of the
driven gate must be much greater than the characteristic
impedance of the transmission line. This condition is satisfied
by MECL circuits which have high impedance inputs. Using
the appropriate terminating resistor (RS) at point A
(Figure 34), the reflections in the transmission line will be
terminated.
Figure 32 -
PARALLEL TERMINATED LINE
Ipd
~I
VTT(-2·0 V)
MOTOROLA
The advantages of series termination include ease of
driving multiple series-terminated lines, low power
consumption, and low cross talk between adjacent lines. The
disadvantage of this system is that loads may not be
distributed along the transmission line due to the one-half
logic swing present at intermediate points.
For board-ta-board interconnections, coaxial cable may be
used for signal conductors. The termination techniques just
discussed also apply when using coax. Coaxial cable has the
advantages of good noise immunity and low attenuation at
high frequencies.
Twisted pair lines are one of the most popular methods of
interconnecting cards or panels. The complementary outputs
of any MECL function may be connected to one end of the
twisted pair line, and any MECL differential line receiver to the
other as shown in the example, Figure 35. RT is used to
terminate the twisted pair line. The 1 to 1.5 V common-mode
noise rejection of the line receiver ignores common-mode
cross talk, permitting multiple twisted pair lines to be tied into
cables. MECL signals may be sent very long distances
(> 1000 feet) on twisted pair, although line attenuation will limit
bandwidth, degrading edge speeds when long line runs are
made.
If timing is critical, parallel signals paths (shown in
Figure 36) should be used when fanout to several cards is
required. This will eliminate distortion caused by long stub
lengths off a signal path.
Wire-wrapped connections can be used with MECL 10K.
For MECL III and MECL 10H, the fast edge speeds (1 ns)
create a mismatch at the wire-wrap connections which can
cause reflections, thus reducing noise immunity. The
mismatch occurs also with MECL 10K, but the distance
1-24
MECLData
DL122-Rev6
between the wire-wrap connections and the end of the line is
generally short enough so the reflections cause no problem.
Series damping resistors may be used with wire-wrapped
lines to extend permissible backplane wiring lengths. Twisted
pair lines may be used for even longer distances across large
wire-wrapped cards. The twisted pair gives a more defined
characteristic impedance (than a single wire), and can be
connected either single-ended, or differentially using a line
receiver.
The recommended wire-wrapped circuit cards have a
ground plane on one side and a voltage plane on the other side
to insure a good ground and a stable voltage source for the
circuits. In addition, the ground plane near the wire-wrapped
lines lowers the impedance of those lines and facilitates
terminating the line. Finally, the ground plane serves to
minimize cross talk between parallel paths in the signal lines.
Point-ta-point wire routing is recommended because cross
talk will be minimized and line lengths will be shortest.
Commercial wire-wrap boards designed for MECL 10K are
available from several vendors.
Microstrip and Stripline
Microstrip and stripline techniques are used with printed
circuit boards to form transmission lines. Microstrip consists
of a constant-width conductor on one side of a circuit board,
with a ground plane on the other side (shown in Figure 37).
The characteristic impedance is determined by the width and
thickness of the conductor, the thickness of the circuit board,
and the dielectric constant of the circuit board material.
Figure 37 -
PC INTERCONNECTION LINES FOR
USE WITH MECL
Figure 35 - TWISTED PAIR LINE DRIVER/RECEIVER
Stripline is used with multilayer circuit boards as shown in
Figure 37. Stripline consists of a constant-width conductor
between two ground planes.
Refer to MECL System Design Handbook for a full
discussion of the properties and use of these.
Figure 36 -
PARALLEL FANOUT TECHNIQUES
Lr---------cardA
CarnB
Rp
CarnC
-D 1\
r
VEE
EL======J----~---CarnA
EL==::::::==J---,-+--- Card B
EL==::::::==J-~r+-+--- Card C
Rr= Zo (each)
'Multiple output gate e9 MC10110
MECLData
DL122-Rev6
CLOCK DISTRIBUTION
Clock distribution can be a system problem. At MECL 10K
speeds, either coaxial cable or twisted pair line (using the
MC10101 and MC10115) can be used to distribute clock
signals throughout a system. Clock line lengths should be
controlled and matched when timing could be critical. Once
the clocking signals arrive on card, a tree distribution should
be used for large-fanouts at high frequency. An example olthe
application of the technique is shown in Figure 38.
Because of the very high clock rates encountered in MECL
III systems, rules for clocking are more rigorous than in slower
systems.
The following guidelines should be followed for best results:
A. On-card Synchronous Clock Distribution via
Transmission Line
1. Use the NOR output in developing clock chains or trees.
Do not mix OR and NOR outputs in the chain.
2. Use balanced fanouts on the clock drivers.
3. Overshoot can be reduced by using two parallel drive
lines in place of one drive line with twice the lumped load.
1-25
MOTOROLA
Figure 38 - 64 FANOUT CLOCK DISTRIBUTION
(PROPER TERMINATION REQUIRED)
FAI>I-OUT = 4
EACH
OFF
CARD
4. To minimize clock skewing problems on synchronous
sections of the system, line delays should be matched to
within 1 ns.
5. Parallel drive gates should be used when clocking
repetition rates are high, or when high capacitance loads
occur. The bandwidth of a MECl III gate may be extended by
paralleling both halves of a dual gate. Approximately 40 or 50
MHz bandwidth can be gained by paralleling two orthree clock
driver gates.
6. Fanout limits should be applied to clock distribution
drivers. Four to six loads should be the maximum load per
driver for best high speed performance. Avoid large lumped
loads at the end of lines greater than 3 inches. A lumped load,
if used, should be four or fewer loads.
7. For wire-OR (emitter dotting), two-way lines (busses)
are recommended. To produce such lines, both ends of a
transmission line are terminated with 100-ohm impedance.
This method should be used when wire-OR connections
exceed 1 inch apart on a drive line.
MOTOROLA
B. Off-Card Clock Distribution
1. The ORINOR outputs of an MC1660 may be used to drive
into twisted pair lines or into flat, fixed-impedance ribbon
cable. At the far end of the twisted pair on MC1692 differential
line receiver is used. The line should be terminated as shown
in Figure 35. This method not only provides high speed,
board-to-board clock distribution, but also provides system
noise margin advantages. Since the line receiver operates
independently of the VBB reference voltage (differential
inputs) the noise margin from board to board is also
independent of temperature differentials.
LOGIC SHORTCUTS
MECl circuitry offers several logic design conveniences.
Among these are:
1. Wire-OR (can be produced by wiring MECl output
emitters together outside packages).
2. Complementary Logic Outputs (both OR and NOR are
brought out to package pins in most cases).
An example of the use of these two features to reduce gate
and package count is shown in Figure 39.
The connection shown saves several gate circuits over
performing the same functions with non-ECl type logic. Also,
the logic functions in Figure 39 are all accomplished with one
gate propagation delay time for best system' speed.
Wire-ORing permits direct connections of MECl circuits to
busses. (MECl System Design Handbook and Application
Note AN-726).
Propagation delay is increased approximately 50 ps per
wire-OR connection. In general, wire-OR should be limited to
6 MECl outputs to maintain a proper lOW logic level. The
MC1 0123 is an exception to this rule because it has a special
VOL level that allows very high fanout on a bus orwire-OR line.
The use of a single output pull-down resistor is recommended
per wire-OR, to economize on power dissipation. However,
two pull-down resistors per wired-OR can improve fall times
and be used for double termination of busses.
Wire-OR should be done between gates in a package or
nearby packages to avoid spikes due to line propagation
delay. This does not apply to bus lines which activate only one
driver at a time.
Figure 39 - USE OF WIRE-OR AND
COMPLEMENTARY OUTPUTS
A--~--~------~----~----AB+CD
8--~~~----~,
Rp
C
D
E
F
G
C+D+E+F+G
Rp
A+B+E+F+G
Rp
1-26
MECL Data
DL122 - Rev 6
SYSTEM CONSIDERATIONS -
Power Supply Regulation
A SUMMARY OF RECOMMENDATIONS
MECL10H
MECL10K
±S%(I)
10%(2)
10%(2)
20'C
Less Than 2S'C
Less Than 2S'C
1"
8"
1"
Leave Open (3)
Leave Open (3)
Leave Open (3)
Multilayer
Standard 2-8ided or
Multilayer
Multilayer
On-Card Temperature Gradient
Maximum Non-Transmission Line Length
(No Damping Resistor)
Unused Inputs
PC Board
Cooling Requirements
Bus Connection Capability
Maximum Twisted Pair Length
(Differential Drive)
The Ground Plane to Occupy Percent
Area of Card
Wire Wrap may be used
MECLIII
SOO IfpmAir
SOO Ifpm Air
SOO Ifpm Air
Yes (Wire-OR)
Yes (Wire-OR)
Yes (Wire-OR)
Limited By Cable
Response Only,
Usually
>1000'
Limited by Cable
Response Only,
Usually
>1000'
Limited by Cable
Response Only,
Usually
>1000'
>7S%
>SO%
>7S%
Not Recommended
Yes
Not Recommended
Compatible with MECL 10,000
Yes
-
Yes
(1) All dc and ac parameters guaranteed for VEE = -5.2 V ± 5%.
(2) At the devices (functional only).
(3) Except special functions without input pull-down resistors.
MECLData
DL122-Rev6
1-27
MOTOROLA
APPLICATIONS ASSISTANCE FORM
In the event that you have any questions or concerns about the performance of any Motorola device listed in this catalog, please
contact your local Motorola sales office or the Motorola Help line for assistance. If further information is required, you can request
direct factory assistance.
Please fill out as much of the form as is possible if you are contacting Motorola for assistance or are sending devices back to
Motorola for analysis. Your information can greatly improve the accuracy of analysis and can dramatically improve the correlation
response and resolution time.
Items 4thru 8 of the following form contain important questions that can be invaluable in analyzing application or device problems. It
can be used as a self-help diagnostic guideline or for a baseline of information gathering to begin a dialog with Motorola
representatives.
MOTOROLA Device Correlation/Component Analysis Request Form
-Please fill out entire form and return with devices to MOTOROLA INC., R&QA DEPT., 2501 S. Price Rd., Chandler, AZ. 85248.
1) Name of Person Requesting Correlation: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Job Title:
Company: _ _ _ _ _ _ _ _ _ _ _ __
Phone No:
2) Alternate Contact: _ _ _ _ _ _ _ _ _ _ _ _ Phone/Position: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
3) Device Type (user part number): _ _ _ _ _ _ _ _ __
4) Industry Generic Device Type: _ _ _ _ _ _ _ _ _ __
5) # of devices tested/sampled:
# of devices in question":
# returned for correlation:
* In the event of 100% failure, does Customer have other date codes of Motorola devices that pass inspection?
Yes
No
Please specify passing date code(s) if applicable _ _ _ _ _ _ _ _ __
If none, does customer have viable alternate vendor(s) for device type?
Yes
Alternate vendor's name _ _ _ _ __
No
6) Date code(s) and Serial Number(s) of devices returned for correlation - If pOSSible, please provide one or two "good" units
(Motorola's and/or other vendor) for comparison: _ _ _ _ _ _ _ _ _ _ _ __
7) Describe USER process that device(s) are questionable in:
Incoming component inspection {test system = ?}: _ _ _ _ _ _ __
_ _ Design prototyping: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Board testlburn-in: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ Other (please describe): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
8) Please describe the device correlation operating parameters as completely as possible for device(s) in question:
> Describe all pin conditions (e.g. floating, high, low, under test, stimulated but not under test, whatever ...), including any input or
output loading conditions (reSistors, caps, clamps, driving devices or devices being driven ...). Potentially critical information
includes:
Input waveform timing relationships
_ _ Input edge rates
_ _ Input Overshoot or Undershoot _ _ Output Overshoot or Undershoot -
Magnitude and Duration
Magnitude and Duration
> Photographs, plots or sketches of relevant inputs and outputs with voltages and time divisions clearly identified for all waveforms
are greatly desirable.
> VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applications and test
systems. Dynamic characteristics of Ground and Vee during device switching can dramatically effect input and internal
operating levels. Ground & VCC measurements should be made as physically close to the device in question as possible.
> Are there specific circumstances that seem to make the questionable unit(s) worse? Better?
_ _ Temperature _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ VCC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ Input rise/fall time _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ Output loading (current/capacitance) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Others _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
> ATE functional data should include pattern with decoding key and critical parameters such as VCC, input voltages, Func step
rate, voltage expected, time to measure.
MOTOROLA
.
1-28
MECLData
DL122 - Rev 6
SECTION V -
MOTOROLA'S PHASE-LOCKED LOOP
WHERE ARE THE PHASE-LOCKED LOOP ICs?
To better serve our customers, we have moved all of the MECL Phase-Locked
Loop ICs to our High Performance Frequency Control Products (Hipercomm)
publication. The Hipercomm book (BR1334/D) can be ordered from the Motorola
Literature Distribution Center. Additionally, all of the PLL data sheets can be
accessed via Internet or through the Motorola MFax™ fax-back systems. See a
full listing of Motorola's PLLs on page 1-30 of this book.
Motorola SPS World MFax System
Mfax Access:
Email:
Telephone:
WWW:
RMFAXO@email.sps.mot.com
TOUCH-TONE (602) 244-6609 or 1-800-774-1848
http://Oesign-NET.com ~ select the Mfax Icon.
A fax of complete, easy-ta-use instructions can be obtained with a first-time phone
call into the system, entering your FAX number and then, pressing 1.
Motorola SPS World Marketing Internet Server
Motorola SPS's Electronic Data Delivery organization has set up a World Wide Web Server to
deliver Motorola SPS's technical data to the global Internet community. Technical data such as the
complete Master Selection Guide along with the OEM North American price book are available on
the Internet server with full search capabilities. Other data on the server include abstracts of data
books, application notes, selector guides, and textbooks. All have easy text search capability.
Ordering literature from the Literature Distribution Center is available on line. Other features of
Motorola SPS's Internet server include the availability of a searchable press release database,
technical training information, with on-line registration capabilities, complete on-line access to the
Mfax system for ordering technical literature faxes, an on-line technical support form to send
technical questions and receive answers through email, information on product groups, full search
capabilities of device models, a listing of the Domestic and International sales offices, and links
directly to other Motorola world wide web servers. For more information on Motorola SPS's Internet
server you can request BR1307/D from Mfax or LOC.
After accessing the Internet, use the following URL:
http://0esign-NET.com
MECLData
DL122-Rev6
1-29
MOTOROLA
Motorola's Phase-Locked Loop ICs
Available in BR1334/D - Hipercomm
Function
Counter Control Logic
Detectors
MC12002
Analog Mixer
14
P,L
-
MC12040
Phase-Frequency Detector
14,20
P,L
FN
oto +75°C
MCH/K12140
Phase-Frequency Detector
8
-
D
-40 to +70°C
-30 to +85°C
-30 to +85°C
Multivibrators
MC1658
Voltage Controlled Multivibrator
16
P,L
D,FN
MC12100
200MHz Voltage Controlled Multivibrator
20
P
DW,M,FN
Oto +75°C
MC12101
130MHz Voltage Controlled Multivibrator
20
P
DW,M,FN
Oto +75°C
MC1648
Voltage Controlled Oscillator
14
P,L
D,FN
-30 to +85°C
MC12061
Crystal Oscillator
16
P,L
FN
Oto +75°C
MC12147
Low Power Voltage Controlled Oscillator Buffer
8
-40 to +85°C
MC1214B
Low Power Voltage Controlled Oscillator
8
D,SD
-40 to +85°C
MC12149
Ultra Low Power Voltage Controlled Oscillator
8
-
D,SD
D,SD
-40 to +85°C
Oscillators
Prescalers
MC12009
4BOMHz +516 Dual Modulus Prescaler
16
P,L
FN
-30 to +85°C
MC12011
550MHz +8/9 Dual Modulus Prescaler
16
P,L
FN
-30 to +85°C
MC12013
550MHz +10/11 Dual Modulus Prescaler
16
P,L
FN
-30 to +B5°C
MC12015
225MHz +32133 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12016
225MHz +P40/41 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12017
225MHz +64/65 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12018
520MHz +128/129 Dual Modulus Prescaler
B
P
D
-40 to +85°C
MC12019
225MHz +20/21 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12022A
1.1 GHz +64/65, +128/129 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12022B
1.1 GHz +64/65, +128/129 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12022LVA
1.1 GHz +64/65, +128/129 Low Voltage Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12022LVB
1.1 GHz +64/65, + 128/129 Low Voltage Dual Modulus Prescaler
8
P
D
-40 to +B5°C
MC12022SLA
1.1 GHz +64/65, + 128/129 Low Power Dual Modulus Prescaler
8
P
D
-40 to +B5°C
MC12022SLB
1.lGHz+64/65, +128/129 Low Power Dual Modulus Prescaler
8
P
D
-40 to +B5°C
MC12022TSA
1.1 GHz +64/65, +128/129 Low Power Dual Modulus Prescaler With
On-Chip Output Termination
8
P
D
-40 to +85°C
MC12022TSB
1.1 GHz +64/65, +128/129 Low Power Dual Modulus Prescaler With
On-Chip Output Termination
8
P
D
-40 to +85°C
MC12022TVA
1.1 GHz +64/65, + 12B/129 Low Voltage, Low Power Dual Modulus
Prescaler With On-Chip Output Termination
8
P
D
-40 to +85°C
MC12022TVB
1.1 GHz +64/65, + 12B/129 Low Voltage, Low Power Dual Modulus
Prescaler With On-Chip Output Termination
8
P
D
-40 to +85°C
MOTOROLA
1-30
MECLData
DL122-Rev6
Motorola's Phase-Locked Loop ICs
Available in BR1334/D - Hipercomm (continued)
Function
Prescalers
MC12023
225MHz +64 Prescaler
8
P
D
o to +70°C
MC12025
520MHz +64/65 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12026A
1.1 GHz +819, +16/17 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12026B
1.1 GHz +8/9, +16/17 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12028A
1.1 GHz +32133, +84/65 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12028B
1.1 GHz +32133, +64/65 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12031A
2.0GHz +64/65, +128/129 Low Voltage Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12031B
2.0GHz +64/65, +128/129 Low Voltage Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12032A
2.0GHz +64/65, +128/129 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12032B
2.0GHz +64/65, +128/129 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12033A
2.0GHz +32133, +64/65 Low Voltage Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12033B
2.0GHz +32133, +64/65 Low Voltage Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12034A
2.0GHz +32133, +64/65 Dual Modulus Prescaler
8
P
D
-40 to +85°C
MC12034B
2.0GHz +32133, +64/65 Dual Modulus Prescaler
8
P
D
-40to+85°C
MC12036A
1.1 GHz +64/65, +128/129 Dual Modulus Prescaler With Stand-By Mode
8
P
D
-40 to +85°C
MC12036B·
t.1GHz +64/65, +128/129 Dual Modulus PrescalerWith Stand-By Mode
8
P
D
-40 to +85°C
MC12038A
1.1GHz +64/65, +127/128, +255/256 Low Power Dual Modulus
Prescaler
8
P
D
-40 to +85°C
MC12052A
1.1 GHz +64/65, +128/129 Super Low Power Dual Modulus Prescaler
8
-
D,SD
-4010 +85°C
MC12053A
1.1 GHz +64/65, +128/129 Super Low Power Dual Modulus Prescaler
With Stand-By Mode
8
-
D,SD
-40 to +85°C
MC12054A
2.0GHz +64/65, +128/129 Super Low Power Dual Modulus Prescaler
8
-40to+85°C
1.1 GHz +126/128. +254/256 Low Power Dual Modulus Prescaler
8
-
D,SD
MC12058
D, SO
-40to+85°C
MC12066
1.3GHz +64/256 Prescaler
8
-
D
-40 to +85°C
MC12073
1.1 GHz +64 Prescaler
8
P
D
Oto +70°C
MC12074
1.1 GHz +256 Low-Power Prescaler
8
P
D
oto +70°C
MC12075
1.3GHz +64 Prescaler
8
P
D
Oto+85°C
MC12076
1.3GHz +256 Prescaler
8
P
D
MC12078
1.3GHz +256 Prescaler
8
P
D
oto +85°C
oto +85°C
MC12079
2.8GHz +64/128/256 Prescaler
8
P
D
-40 to +85°C
MC120BO
1.1 GHz +10/20/40/80 Prescaler
8
P
D
-40 to +85°C
MC12083
1.1 GHz +2 Low Power Prescaler With Stand-By Mode
8
P
D
-40to+85°C
MC12089
2.8GHz +64/128 Prescaler
8
P
D
-40 to +85°C
MC12090
750MHz +2 UHF Prescaler (Not Recommended for New Designs)
16
P,L
-
Oto+75°C
MC12093
1.1 GHz +21418 Low Power Prescaler With Stand-By Mode
B
-
D,SD
-40to+85°C
MC12095
2.5GHz +214 Low Power Prescaler With Stand-By Mode
8
-
D,SD
-40 to +85°C
MC12098
2.5GHz +8192 Prescaler
8
-
D
-40 to +85°C
MECLData
DL122-Rev6
1-31
MOTOROLA
rn
Motorola's Phase-Locked Loop ICs
Available in BR1334/D - Hipercomm (continued)
Function
Synthesizers
MC12179
500--2800MHz Single Channel Frequency Synthesizer
8
-
D
-4010 +85°C
MC12181
125-1000MHz Frequency Synthesizer
16
-
D
-40to+85°C
MC12202
1.1 GHz Serial Input Synthesizer
16,20
-
D,DT
-40 to +85°C
MC12206
2.0GHz Serial Input Synthesizer
16,20
D,DT
-40to+85°C
MC12207
2.0GHz Serial Input Synthesizer
16,20
-
M,DT
-40 to +85°C
MC12210
2.5GHz Serial Input Synthesizer
16,20
-
D,DT
-40 to +85°C
MOTOROLA
1-32
MECLData
DL122-Rev6
MECL Data
MECL 10H
MECLData
DL122-Rev6
2-1
MOTOROLA
[2J
MECL10H
INTEGRATED CIRCUITS
MC10H100 SERIES
OT075°C
Function Selection - (0 to +75°C)
I
Function
Device
ea••
MC10H100
MC10Hl02
620,648. ns
620,648, n5
MC10Hl06
MC10H211
620, 648, 775
620, 648, 775
NOR Gate
Quad 2-Input with Strobe
Quad 2-lnput
Triple 4-3-3 Input
Dual 3-Input 3-Output
Functfon
Quad 2-lnput
Dual 3-lnput 3-Output
MC10H104
Quad Bus DrlverlReceiver with ?-to-1
Output MUltiplexers
Quad 2-[nput Multiplexers
(Noninvertlng)
Quad 2-lnpul Multiplexers (Inverting)
8-Une Multiplexer
Quad 2-lnput Multiplexer Latch
Oual4-1 Multiplexer
620,648, n5
Complex Gates
QuadORINOR
MC10Hl01
Triple 2-3-2 Input ORINOR
Triple Exclusive ORINOR
Dual 4-6 Input ORINOR
Quad exclusive OR
Dual 2-Wlde OR-AND/OR-AND INVERT
MC10Hl05
MC10Hl07
MC10H109
4-Wide OR-AND/OR-AND INVERT
MC10H121
MC10H188
MC10H189
Hex Buffer w/Enable
Hex Inverter wlEnable
MC10H113
MC10H117
620,648, n5
620,648, n5
620,648, n5
620,648, n5
620,648, n5
620,648, n5
Quad MECL-to-TTl Translator, Single
Power Supply (-5.2 V or +5.0 V)
Quad nUNMOS to MECL Translator
Quad CMOS to MECL Translator
Quad TIL to MECL, Eel Strobe
9-BIt TTL-ECL Translator
9-B1t Eel-TIL Translator
9-Bit LatchITTL-ECL Translator
9-Bit latch/Eel-TIL Translator
Registered Hex TTL-ECl Translator
Registered Hex ECl-TTl Translator
Registered Hex TTL-PECl Translator
Registered Hex PECl-TTL Translator
620,648, n5
620,648, n5
620,648, n5
620,648, n5
620,648, n5
MC10H141
MC10H145
MC10H166
620,648, n5
620,648, n5
620,648, n5
Universal Hexadecimal
Binary Counter
620,648, n5
620, 648, 775
Arithmetic FUnctions
MC10H124
MC10H125
620,648, n5
Look Ahead Cany Block
Dual High Speed AdderlSubtractor
620, 648, 775
4-BnAlU
MC10H350
MC10H351
620,648, n5
732, 7!l8, n5
Spacial Functfon
MC10H352
MC10H424
MC10H/l00H600
MC10H/100H601
MC10H/100H602
MC10H/100H603
732, 738, 775
MC10HJ100H604
MC10H/100H605
MC10H/100H606
MC10HI100H607
4-Bit Universal Shift Register
16 x 4 Bit Register Fite
5-Bit Magnitude Comparator
Quad Bus Driver/Receiver with
Transmit and Receiver Latches
620, 648, 775
776
776
776
n6
n6
n6
n6
MC10H334
732, 738, 775
MC10H/l00H680
n6
MC10H145
620, 648, 775
MC10H123
620, 648, 775
4-a. ECl-TTl Load Reducing DRAM
Driver
Memories
116 x 4 Bit Register File
776
Bus Driver (25 ohm outputs)
Receivers
Triple 4-3-3 Input Bus Driver
(25 Ohms)
Quad Une Receiver
Triple Line Receiver
FII~IOp
758,724, n6
MC10H158
MC10H159
MC10Hl64
MC10H173
MC10H174
Counters
620, 648, 775
Translators
Quad TIL to MECl
Quad MECl to TIL
MC10H330
Data Selector Multiplexer
'AND Gates
Quad AND
Case
4-Bit Differential ECl Bus to Tn. Bus
Transceiver
Hex ECl-TTL Transceiver w/Latches
OR Gate
I
Device
Transceiver.
Quad Bus Driver/Receiver with 2-t0-1
Output Muniplexers
Dual Bus Driver/Receiver with 4-t0-1
Output Multiplexers
Quad Bus DriverlReceiver with
Transmit and Receiver Latches
Latches
Dual 0 Latch
Dual 0 Master Slave Flip-Rop
Dual J-K Master Slave Flip-Flop
Hex 0 Flip-Flop
Quint Latch
Hex 0 Flip-Flop w/Common Reset
MC10H13Q
MC10H131
620,648, n5
MC10H135
MC10H176
MC10H175
MC10H186
620, 648, 775
620, 648, 775
620,648, n5
620, 648, 775
620, 648, 775
Binary to 1-8 (High)
Dual Binary to 1--4 (low)
Dual Binary to 1-4 (High)
8-lnput Priority Encoder
MC10H161
MC10H162
MC10H171
620,648, n5
620,648, ITS
620.648, ITS
MC10H172
MC10H165
620, 648, 775
IDual 4-5 Input ORINOR Gate
MOTOROLA
MC10Hl60
732, 738, 775
MC10H334
732,738, n5
MC10H209
620, 648, 775
MC101100H640
n6
n6
Clock Drivers
68030140 ECl-TTL Clock Driver
Single Supply PEeL-ECl 1:9 Clock
Distribution
68030140 ECl-TTL Clock Driver
Dual Supply ECT- TTl. 1:8 Clock Driver
68030/40 PECl-TTL Clock Driver
1:9 TTL Clock Driver
PCl-TTl-TTl 1:8 Clock Distribution
Chip
620,648, n5
Parity Checker
112-8it Parity Generator/Checker
724, 758, 776
MC10H332
ORINORGate
Encoders Decoders
Binary to 1-8 (low)
MC10H330
620, 648, 775
2-2
MC101100H641
MC101100H642
MC101100H643
MC101100H644
MC10H645
MC101100H646
776
776
n5
776
n6
MECLData
DL122-Rev6
MECL 10H INTRODUCTION
Motorola's MECL 1OH family features 100% improvement
in propagation delay and clock speeds while maintaining
power supply current equal to MECL 10K. This MECL family
is voltage compensated which allows guaranteed dc and
switching parameters over a ±5% power supply range. Noise
margins of MECL 10H are 75% better than the MECL 10K
series over the ±5% power supply range. MECL 10H is
compatible with MECL 10K and MECL III, a key element in
allowing users to enhance existing systems by increasing the
speed in critical timing areas. Also, many MECL 10H devices
are pinouVfunctional duplications of the MECL 10K series
devices.
increase complexity at the gate level; however, the added
performance more than compensates.
The MECL 10H family is being fabricated using Motorola's
MOSAIC I (Motorola Oxide Self Assigned Implanted Circuits).
The switching transistor's geometries obtained in the
MOSAIC I process show a two-fold improvement in !-t, a
reduction of more than 50% in parasitic capacitance and a
decrease in device area of almost 76%.
FIGURE 2 -
MOSAIC versus MECL 10K SWITCHING
TRANSISTOR GEOMETRY
With improved geometry, the MECL1OH switching
transistors (left) are one-seventh the size of the older
MECL 10K transistors (right). Along with the smaller
area comes an improved It and reduced parasitic
capacitances.
FIGURE 1 - MECL 10K versus MECL 10H GATE DESIGN
MECL IOH
MECL 10K
T n rITlnrm n
2 MILS
(51!!)
I
L
4.0MA!
14
EMlnER3p8~
DEVICE AREA
AI
II
II
II
U LWuLW U
I
=592 ~2
I
I
I
1
1
~I
3.35 (85!!)
EMITIER 0.15 x 0.8 MILS
(4~x201')
=
DEVICE AREA 6.7 MIL 2
(4323 ~2)
fr =3.5 GHz
fr =1.6GHz
eCB
eEB
ces
eeB
GEB
ees
=0.16pF
=0.07pF
=0.18pF
I
=0.46pF
=O.18pF
=0.83pF
Figure 2 illustrates the relative size difference between the
junction isolated transistor of MECL 10K and the MOSAIC I
transistor of MECL 10H. This suggests that performance
could be improved twofold at lower power levels. However, at
the gate level, the power of the output transistor cannot be
reduced without sacrificing output characteristics because of
the 50 ohm drive requirements of MECL. In more complex
functions, where part of the delay is associated with internal
gates, MECL 1OH devices use less power than the equivalent
MECL 10K devices and provide an even more significant
improvement in ac performance.
4.0MA!
Table 1. - TYPICAL FAMILY CHARACTERISTICS FOR
10K AND 10H CIRCUITS
The schematics in Figure 1 compare the basic gate
structure of the MECL 1OH to that of MECL 10K devices. The
gate switch current is established with a current source in the
MECL 10H family as compared to a resistor source in MECL
10K. The bias generator in the MECL 10K device has been
replaced with a voltage regulator in the MECL 1OH series. The
advantages of these design changes are: current-sources
permit-matched collector resistors that yield 'correspondingly
better matched delays, less variation in the output-voltage
level with power supply changes, and matched outputtracking rates with temperature. These circuit changes
MECLData
DL122- RevS
10K
Propagation delay (ns)
Power (mW)
Power-speed product (pJ)
Riselfall times (ns) (20-80%)
Temperature range (0C)
Voltage regulated
Technology
2.0
25
50
2.0
-30 to +85
No
Junction
isolated
10H
1.0
25
25
1.0
Oto +75
Yes
Oxide
isolated
VEE=-5·2V
2-3
MOTOROLA
Supply & Temperature Variation
Table 3. -
MECL 10H temperature and voltage compensation is
designed to guarantee compatibility with MECL 10K, MECL
III, MECL Memories and the MC10900 and Macrocell Array
products. Table 1 summarizes some performance
characteristics of the MECL 10K and 10H logic families in a
16-pin DIP. The MECL 10H devices offer typical propagation
delays of 1.0 ns at 25 mW per gate when operated from a VEE
of -5.2 V. The resulting speed-power product of 25 picojoules
is one of the best of any ECL logic family available today.
The operating temperature range is changed from -3O°C to
+85°C of the MECL 10K family to the narrower range of O°C
to 75°C for MECL 1OH. This change matches the constraints
established by the memory and array products. Operation at
-3O°C would require compromises in performance and power.
With few exceptions, commercial applications are satisfied by
O°C min.
Table 2. -
Parameter
tpD
25'C
MlnTypMax
75'C
MinTypMax
Units
0.4 1.0 1.5
0.4 1.0 1.6
0.4 1.0 1.7
ns
Min
Max
Min
Max
Min
Max
tR (2(H!0%)
0.5
1.5
0.5
1.6
0.5
1.7
ns
tF(2(H!0%)
0.5
1.5
0.5
1.6
0.5
1.7
ns
VEE = -5.2 V ±S%
Parameter
tpD
Propagation
delay (ns)"
Delay variation
vs temp (ps/'C)
Delay variation
vs supply (paN)
Typ
Max
Typ
Max
Typ
10K
2.0
2.9
2.0
7.0
80
10H
1.0
1.5
0.5
4.0
0
Max
0
·VEE = -5.2 V, Temp = 25'C
AC speCifications of MECL 10H products appear in Table 2.
In the MECL 1OH family, all ac specifications have guaranteed
minimums and maximums for extremes of both temperature
and supply - a first in ECL logic. In addition, flip flops, latches
and counters will have guaranteed limits for setup time, hold
time, and clock pulse width. The limits in Table 2 are
guaranteed for a power supply variation of ±5%. MECL 10K
typically has a propagation delay (tPD) variation of 80 psNwith
no guaranteed maximum. The typical variation in tpD for
MECL 10H circuits is only 38 ps typically over the entire
specified temperature range and power-supply tolerance,
and is guaranteed not to exceed 300 ps.
The improved performance in temperature over MECL 10K
are a result of the internal voltage regulator. The primary
difference being the flatter tracking rate of the output "0' level
voltage (Vall. This difference does not affect the compatibility
with existing MECL families.
Changes in output "1" level voltages (VOH) with supply
variations are 10 mVN less for the MECL 10H family. VOH
varies with the supply, primarily because of changes in chip
temperature caused by the changes in power dissipation.
However, the current in the MECL 1OH circuits remains almost
constant with supply changes, since the circuits are voltage
compensated and use current sources for all internal emitter
followers ..Threshold voltage (VSS) and output "0" level
MOTOROLA
Typ
Min
MECL 10H AC SPECIFICATIONS
AND TRACKING
()<'C
MlnTypMax
LOGIC LEVEL DC TRACKING RATE FOR
10K AND 10H CIRCUITS
Max
LiVOH/LiT
(mV/'C)
10H
10K
1.2
1.2
1.3
1.3
1.5
1.5
LiVBs!LiT
(mV/,C)
10H
10K
O.B
O.B
1.0
1.0
1.2
1.2
LiVOl!LiT
(mV/'C)
10H
10K
0
0.35
0.75
0.4
0.5
1.0
0.6
0.75
1.55
LiVOH/LiVEE
(mVN)
10H
10K
-20
-30
LiVBs!LiVEE
(mVN)
10H
10K
0
110
10
150
25
190
LiVOtfLiVEE
(mVN)
10H
10K
0
200
20
250
50
320
0
0
voltage (VOL) variations are shown with respectto MECL 10K
in Table 3. In both cases voltage compensation has reduced
the variations significantly.
Noise Margin Considerations
Specification of input voltage levels (VIHA, VILA) are
changed from those of MECL 10K resulting in improved noise
margins for MECL 10H.
The MECL 10K circuits have two sets of output voltage
specifications (VOH, VOHA, and VOL, VOLA). The first output
voltage specification in each set (VOH and VOL) are
guaranteed maximum and minimum output levels for typical
input levels. The second speCification in each set (VOHA and
VoLA> is the guaranteed worst-case output level for input
threshold voltages. System analysis for worst-case noise
margin considers VOHA and VOLA only. The MECL 10H
family has only one set of output voltages (VOH and Vall with
minimum and maximum values specified. The minimum value
of VOH and the maximum value for VOL of the MECL 10H
family is synonymous with the VOHA and VOLA specifications
of MECL 10K family.
The VOH values for the MECL 10H circuits are equal to or
better than the MECL 10K levels at all temperatures. Input
threshold voltages (VIHA and VILA, which are synonymous
with VIH min and VIL max for 10H) are also improved and
Table 4. - NOISE MAI'IGIN versus
POWER-5UPPLY CONDITIONS
VEE
-10%
Parameter
Noise Margin
10H
VEE
-5%
VEE
+5%
VEE
Typ
Min
Typ
Min
Typ
Min
Typ
Min
224
150
227
150
230
150 .233
150
High
VNH (mV)
10K
127
47
166
86
205
125
241
164
Noise Margin
10H
264
150
267
150
270
150
273
150
Low
VNL(mV)
10K
223
103
249
129
275
155
301
181
"Temp = 0 to 75D C
2-4
MECLData
DL122-Rev6
only the MECL 10K series.
Using an all MECL 10K system as a reference, three
possible logic mixes must be considered: MECL 10K driving
MECL 10H; MECL 10H driving MECL 10K; and MECL 10H
driving MECL 10H. The system noise margin for the three
configurations can now be calculated for the following cases
(See Figure 3):
In Case 1, the system uses multiple power supplies, each
independently voltage regulated to some percentage
tolerance. Worst-case is where one device is at the plus
extreme and the other device is at the minus extreme of the
supply tolerance.
In Case 2, a system operates on a single supply or several
supplies slaved to a master supply. The entire system can
drift, but all devices are at the same supply voltage.
In Case 3, a system has excessive supply drops
throughout. Supply gradients are due to resistive drops in VEE
bus.
The analysis indicates that the noise margins for a MECL
1OKll OH system equal or exceed the margins for an all 10K
system for supply tolerance up to ±5%. The results of the
analysis are shown in Figure 3.
guaranteed VIHA has been decreased by 25 mV over the
entire operating temperature range, resulting in a "1" level
noise margin of 150 mV (compared to 125 mV for MECL 10K
circuits). VILA has been decreased by 5.0 mV, providing a "0"
level noise margin equal to the"1" level noise margin. The VOL
minimum of the MECL 10H is more negative than for MECL
10K (-1950 mV instead of-1850 mV). The VOL level for the
MECL 10K family was selected to ensure that the gate would
not saturate at high temperatures and high supply voltages.
The reduction in operating temperature range for the MECL
10H family and the improvement in tracking rate allow the
lower VOL level. The change in this level does not affect
system noise margins. Although some of the interface levels
change with temperature, the changes in voltage levels are
well within the tolerance ranges that would keep the families
compatible. Table 4 lists some noise margins for VEE supply
variations.
The compatibility of MECL 10H with MECL 10K may be
demonstrated by applying the tracking rates in Table 3 to the
dc specifications. The method for determining compatibility is
to show acceptable noise margins for MECL 1OH, MECL 10K
and mixed MECL 10KlMECL 10H systems. The assumption
is that the families are compatible if the noise margin for a
mixed system is equal to or better than the same system using
FIGURE 3 -
NOISE MARGIN versus POWER-SUPPLY VARIATION
Case 1
Case 2
Case 3
lro~-----------------130
130
w~ 110
~~
70
>
50
30
110
~~90
90
~~
~~
wSE
~~ 70
~~, 50
>
3D
10
o
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ABSOLUTE VALUE OF VEE GRADIENT - V
o
-2
-4
-6
-a
-10
VEE REGULATION RELATIVE TO -5.2 V- %
~--~2--~~---~~~~----1~D~
VEE GRADIENT RELATIVE TO ~.2 V - %
A. MECL 10K DRIVING MECL 10K B. MECL 10K DRIVING MECL 10H C. MECL 10H DRIVING MECL 10K D. MECL 10H DRIVING MECL 10H
MECLData
DL122-Rev6
2-5
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Binary Counter
MC10H016
The MC10H016 is a high-speed synchronous, presettable, cascadable
4-bit binary counter. It is useful for a large number of conversion, counting and
digital integration applications.
• Counting Frequency, 200 MHz Minimum
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
• Positive Edge Triggered
-•
MAXIMUM RATINGS
Symbol
Raling
Unit
Power Supply (VCC = O)
VEE
-8.0100
Vdc
Input Voltage (VCC = O)
VI
o to VEE
Vdc
lout
50
100
mA
TA
Oto+75
'c
Tstg
-55 to +150
-55 to +165
'C
Characteristic
Output Current - Continuous
-Surge
Operating Temperature Range
Storage Temperature Range -
Plastic
-Ceramic
25'
0'
Power Supply Current
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%) (See Note)
Characlerisllc
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-l0
75'
Symbol
Min
Max
Min
Max
Min
Max
Unll
VCCI
IE
-
126
-
115
-
126
mA
01
02
~
00
03
fC
CP
Input Current High
All ExceptMR
Pin 12 MR
linH
Input CUrrent Low
linL
0.5
High Output Voltage
VOH
-1.02
-0.84
Low Output Voltage
VOL
-1.95
-1.63
High Input Voltage
VIH
-1.17
-0.84
Low Input Voltage
VIL
-1.95
-1.48
-
450
1190
-
-
-
-
265
700
-
265
700
0.5
-
0.3
-
~
-0.98
-0.81
-0.92
-0.735
Vdc
PE
MR
-1.95
-1.63
-1.95
-1.60
Vdc
CE
P3
-1.13
-0.81
-1.07
-0.735
Vdc
-1.95
-1.48
-1.95
-1.45
Vdc
PO
P2
VEE
PI
AC PARAMETERS
Propagation Delay
Clock to a
ClocktoW
MRtoa
Ipd
Set-upTime
Pn to Clock
CE or I'E to Clock
Iset
Hold Time
ClocktoP n
Clock to CE or J5E
thold
Counting Frequency
fcount
Rise Time
Fall Time
VCC2
ns
1.0
0.7
0.7
2.4
2.4
2.4
1.0
0.7
0.7
2.5
2.5
2.5
1.0
0.7
0.7
2.7
2.6
2.6
2.0
2.5
-
2.0
2.5
-
2.0
2.5
-
1.0
0.5
1.0
0.5
-
1.0
0.5
200
-
200
-
200
-
Ir
0.5
2.0
0.5
2.1
0.5
2.2
ns
tf
0.5
2.0
0.5
2.1
0.5
2.2
ns
-
-
-
Pin assignment is lor Dual-in-Llne Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
ns
TRUTH TABLE
ns
CE
PE
MR
CP
Function
L
H
L
H
X
L
L
H
H
X
L
L
L
L
L
Z
Z
Z
Z
Zl
X
X
H
X
Load Parallel (P n 10 an)
Load Parallel (Pn to an)
Count
Hold
Masters Respond;
Slaves Hold
Resel (an = LOW,
TC = HIGH)
MHz
NOTE:
Each MECL 1OH series circuit has been designed to meet the de specifications shown in the test table,
afterthennal equilibrium has been established. The circuit Is in a test socket or mounted on aprinted circuit
board and transverse air Ilow grealer than 500 Ilpm Is maintained. Outputs are lerminaled Ihrough a
5Cl- I
II
I
I
U
I
I
I
II
I
U
I
I
I
II
I
I
I
U
I
II I
CP
Note that this diagram is provided for understanding of logic operation only. It should not be used for evaluation of
propagation delays as many gate functions are achieved internally without incurring a full gate delay.
z
11210Hl~
L..::-.
Qo-
-CE
PE
CE
!- MR
C
.~
PE
- -MR
MR
Te
C
IpH~ ~
1/210Hl09
11210Hl09
I
PE
MSB
Tc
c
IpUJ ~
IpUJ
I
1
s::
Qo-hm resistor to -2.1 volts.
Pin assignment is for Dual-in-Une Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3193
© Motorola, Inc. 1996
2-22
REVS
®
MOTOROLA
MC10H123
FIGURE 1 -
113 MC10H123
-2.0
VDC
MECLData
DL122-Rev6
50-OHM BUS DRIVER (25-0HM LOAD)
1/3 MC10H123
1/3 MC10H123
RECEIVERS (MECL GATES)
2-23
-2.0
VDC
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad TTL-to-MECL Translator
With TTL Strobe Input
MC10H124
-•
The MC1 OH 124 is a quad translator for interfacing data and control signals
between a saturated logic section and the MECL section of digital systems. The
10H part is a funclionaVpinout duplication of the standard MECL 10K family
part, with 100% improvement in propagation delay, and no increase in
power-supply current.
•
•
Propagation Delay, 1.5 ns Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
MAXIMUM RATINGS
Characteristic
Power Supply (Vcc = 5.0 V)
Power Supply (VEE = -5.2 V)
Symbol
Rating
Unit
VEE
-8.0toO
Vdc
Vdc
5
6
VCC
Oto+7.0
Input Voltage (VCC = 5.0 V) TIL
VI
OtoVCC
Vdc
Output Current - Continuous
lout
50
100
mA
TA
010+75
"C
Tstg
-55 to +150
-55 to +165
"C
-Surge
Operating Temperalure Range
Storage Temperature Range - Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE
lSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PlCC
CASE 775-02
LOGIC DIAGRAM
-I--r--o~-
7
12
10
=-5.2 V ±5%, VCC =5.0 V ± 5.0%)
0"
25"
3
15
75"
11
13
Symbol
Min
Max
Min
Max
Min
Max
Unit
IE
-
72
-
66
-
72
rnA
-
rnA
-
25
-
18
25
25
mA
-
200
50
-
200
50
-
200
50
-
-12.8
-3.2
-
-12.8
-3.2
-
-12.8
-3.2
V(BR)in
5.5
-
5.5
-
5.5
-
Vdc
Input Clamp Voltage
VI
-
-1.5
-
-1.5
-
-1.5
Vdc
High Oulput Voltage
VOH
-1.02
-0.84
-0.98
-0.81
-0.92
-0.735
Vdc
low Outpul Voltage
VOL
-1.95
-1.63
-1.95
-1.63
-1.95
-1.60
Vdc
High Input Vollage
VIH
2.0
-
2.0
-
2.0
-
Vdc
AIN
low Input Voltage
Vil
-
0.8
-
0.8
-
0.8
Vdc
COMMON
STROBE
DIN
BIN
CIN
VEE
VCC
Characteristic
Negative Power
Supply Drain
14
GND = PIN 16
VCC ( +5.0 VDC)= PIN 9
VEE ( -5.2 VDC) = PIN 8
Current
Posilive Power Supply
Drain Current
ICCH
ICCl
Reverse Current
Pin 6
Pin7
IR
Forward Current
IF
Pin 6
Pin7
Input Breakdown
Voltage
16
-
16
ItA
DIP
PIN ASSIGNMENT
mA
NOTE:
Each MECl 10H series circuil has been deSigned 10 meelthe de specificalions shown in the lesl table,
BOUT
GND
AOUT
COUT
BOUT
Dour
AOUT
Dour
Cour
afterthermal eqUilibrium has been established. The circuit is in a tastsacket or mounted on a printed circuit
board and Iransverse air flow grealer than 500 Ifprn is maintained. Oulputs are lenninaled Ihrough a
SD-ohm resistor to -2.0 volts.
Pin assignment is for DUBl-in-Line Package.
For PLeC pin aSSignment. see the Pin Conversion
Tables on page 6-11.
9/96
© Motorola, Inc. 1996
2-24
REV 6
®
MOTOROLA
MC10H124
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%, VCC = 5.0 V ± 5.0%)
Characteristic
AC PARAMETERS
tpd
0.55
2.25
0.55
2.4
0.85
2.95
ns
Rise Time
tr
0.5
1.5
0.5
1.6
0.5
1.7
ns
Fall Time
tf
0.5
1.5
0.5
1.6
0.5
1.7
ns
Propagation Delay
APPLICATIONS INFORMATION
The MC10H124 has TTL-compatible inputs and
MECL complementary open--emitter outputs that allow
use as an inverting/non-inverting translator or as a
differential line driver. When the common strobe input is
at the low-logic level, it forces all true outputs to a MECL
low-logic state and all inverting outputs to a MECL
high-logic state.
MECL Data
DL122-Rev6
An advantage of this device is that TTL-level
information can be transmitted differentially, via balanced
twisted pair lines, to MECL equipment, where the signal
can be received by the MC10H115 or MC10H116
differential line receivers. The power supply
requirements are ground, +5.0 volts, and -5.2 volts.
2-25
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad MECL-to-TTL Translator
MC10H125
The MC10H125 is a quad translator for interfacing data and control signals
between the MECL section and saturated logic section of digital systems. The
10H part is a functional/pinout duplication of the standard MECL 10K family
part, with 100% improvement in propagation delay, and no increase in
power-supply current.
Outputs of unused translators will go to low state when their inputs are left
open.
•
•
-,.
•
Propagation Delay, 2.5 ns Typical
• Voltage Compensated
Improved Noise Margin 150 mV
• MECL 10K-Compatible
(Over Operating Voltage and Temperature Range)
MAXIMUM RATINGS
Symbol
Rating
Unit
VEE
Vee
VI
~.0100
Vdc
Oto+7.0
Vdc
DtoVEE
Vdc
Operating Temperature Range
TA
010 +75
°C
Storage Temperature Range - Plastic
-Ceramic
Tstg
-55 to +150
-55 to +165
°C
°C
Characteristic
Power Supply (Vee' 5.0 V)
Power Supply (VEE' -5.2 V)
Input Voltage (Vec' 5.0 V)
ELECTRICAL CHARACTERISTICS (VEE
(See Note)
Negative Power
Supply Drain
Current
Positive Power Supply
Drain Current
750
250
7
Symbol
Min
Max
Min
Max
Min
Max
Unit
IE
-
44
-
40
-
44
mA
ICCH
-
63
-
leel
40
mA
mA
225
1.5
-
63
-
40
-
145
-
145
1.0
1.0
ItA
ItA
Input Leakage Current
ICBO
-
High Output Voltage
IOH·-l.0mA
VOH
2.5
-
2.5
-
2.5
-
Vdc
Low Output Voltage
IOL.+20 mA
VOL
-
0.5
-
0.5
-
0.5
Vdc
High Input Voltage(l)
VIH
-1.17
-hm resistor to -2.0 volts.
© Motorola, Inc. 1996
L
present.
ns
tr
1.0
an
positive transition of clock
FaU"Time
-
K
Q n +1
for
Rise "Time
Set-upTime
S
N.D. = Not Defined
AC PARAMETERS
Propagation Delay
Set, Reset, Clock
14
L
~
linH
460
800
675
R2 11
RS TRUTH TABLE
......-',:::;=,:.:-:;~"-,
CLOCK J-K TRUTH TABLE'
Max
Input Current High
Pins 6, 7,10,11
Pins 4,5,12,13
Pin 9
-
15
R213 _ _ _....I
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V +5%)
(See Note)
Characteristic
J210
REV 6
®
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Universal Hexadecimal
Counter
MC10H136
-•
The MC10H136 is a high speed synchronous hexadecimal counter. This
10H part is a functional/pinout duplication of the standard MECL 10K family
part, with 100% improvement in counting frequency and no increase in
power-supply current.
•
•
•
• Voltage Compensated
Counting Frequency, 250 MHz Minimum
• MECL 10K-Compatible
Power Dissipation, 625 mW Typical
Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
MAXIMUM RATINGS
Rating
Unit
CIN
Sl
S2
Power Supply (VCC
VEE
-ll.0 10 a
Vdc
OloVEE
Vdc
Output Current - Continuous
lout
50
100
mA
H
L
L
L
L
VI
X
L
TA
Oto+75
"C
H
Tslg
-55 to +150
-5510+165
"C
X
=0)
Inpul Voltage (VCC =0)
-Surge
Operating Temperature Range
Storage Temperature Range - Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE
Symbol
Min
-
L
=-5.2 V +5%)
(See Note)
-
0'
25'
Max
FNSUFFIX
PLCC
CASE 775-02
-
-
Max
Inpul Current Low
linL
0.5
-
0.5
-
0.3
-
JIA
VOH
-1.02
-0.84
-0.98
-0.81
-0.92
-0.735
Vdc
-
275
420
335
240
-
-
165
mA
JIA
275
420
335
240
Low Output Voltage
VOL
-1.95
-1.63
-1.95
-1.63
-1.95
-1.60
Vdc
High Inpul Voltage
VIH
-1.17
-0.84
-1.13
-0.81
-1.07
-0.735
Vdc
Low Input Voltage
VIL
-1.95
-1.48
-1.95
-1.48
-1.95
-1.45
Vdc
0.7
1.0
2.3
4.8
0.7
1.0
2.4
4.9
0.7
1.0
2.5
5.0
0.7
2.5
0.7
2.6
0.7
2.7
AC PARAMETERS
Propagation Delay
ClockloQ
Clock 10 Carry Oul
Carry in 10 Carry
Out
Ipd
Sel-upTIme
Data (DO to C)
Select (S to C)
Carry In (Cin to C)
(Cto Cin)
Isel
Ihold
Counting Frequency
L
L H
L H
L H
L
L
X
X
X
L H X
L H X
H H X
X
L
L
H
H
H
H
L
L
L
L
L
Clock
H
H
H
H
L L
H L
L H
H H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
H
In
H
H
X
X
X X
X X
X X
X X
X X
X
X
X
X
X
X
L
L
L
H
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
H H
X
X
X
X
OUTPUTS
CaiTY
0001 0203
H
H
H
H
H
L
L
H
Cai1Y
Cui
Truth table shows logic states assummg mputs vary In
sequence shown from top to bottom.
.* A clock H is defined as a clock input transition from a
low to a high logic level.
*
ns
2.0
3.5
2.0
0
Hold Time
Data (C 10 DO)
Select (C to S)
Carry In (C to Cin)
(Cin toC)
H
Unit
linH
-
L
L
H
H
H
51 52 DO D1 D2 03
Inpul Currenl High
Pins 5, 6,11,12,13
Pin9
Pin7
Pin 10
430
670
535
380
150
Min
H
H
INPUTS
75'
Max
Operating Mode
Preset (Program)
Increment (Count Up)
Hold Counl
Decrement (Count Down)
Hold Count
Hold (Stop Count)
SEQUENTIAL TAUTH TABLE'
IE
-
165
Min
'c
Power Supply Current
High Outpul Voltage
PSUFFIX
PLASTIC PACKAGE
CASE 64B-08
FUNCTION SELECT TABLE
Symbol
Characteristic
Characteristic
LSUFFIX
CERAMIC PACKAGE
CASE 62D-l0
-
-
2.0
3.5
2.0
0
-
-
-
ns
VCC2
VCC1
02
01
03
ao
CLOCK
COUT
00
03
ns
-0.5
0
2.2
-
-0.5
0
2.2
-
-0.5
0
2.2
fcount
250
-
250
-
250
-
AiseTime
Ir
0.5
2.3
0.5
2.4
0.5
2.5
ns
Pin assignment is for DuaHn-Line Package.
For PLCC pin assignment, see the Pin Conversion
Fall Time
tf
0.5
2.3
0.5
2.4
0.5
2.5
ns
Tables on page 6-11.
a
-
a
-
2.0
3.5
2.0
0
DIP PIN ASSIGNMENT
a
MHz
02
01
82
CIN
VEE
81
NOTE:
Each MECL 10H series circuit has been designed to meet the de specifications shown in the test table, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
air flow greater than 500 linear fpm is maintained. Outputs are terminated through a SO-ohm resistor to -2.0 volts.
9/96
© Molorola, Inc. 1996
2-33
REV 6
®
MOTOROLA
MC10H136
LOGIC DIAGRAM
81 9
CiiiYTn
10
Clock
13
VCC1 = Pin 1
VCC2 = Pm16
VEE = Pin 8
12
00
14
11
15
00
01
01
6
02
2
5
Q2
D3
3
as
4
CBiiYOiit
NOTE: FUP-FLOPS WILL TOGGLE WHEN ALL T INPUTS ARE LOW.
APPLICATION INFORMATION
The MC10H136 is a high speed synchronous counter
that operates at 250 MHz. Counter operating modes
include count up, count down, pre-set and hold count.
This device allows the designer to use one basic counter
for many applications.
MOTOROLA
The 81, 82, control lines determine the operating
modes of the counter. In the pre-set mode, a clock pulse
is necessary to load the counter with the information
present on the data inputs (DO, D1 , D2, and D3)_ Carry out
goes low on the terminal count or when the counter is
being pre-set.
2--34
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Four-Bit Universal Shift
Register
MC10H141
The MC10H14l is a four-bit universal shift register. This device is a
functional/pinout duplication of the standard MECL 10K part' with 100%
improvement in propagation delay and operation frequency and no increase in
power supply current.
-•
• Shift frequency, 250 MHz Min
• Power Dissipation, 425 mW Typical
• Improved Noise Margin 150 mV (over operating voltage and
temperature range)
• Voltage Compensated
• MECL 10K-Compatible
MAXIMUM RATINGS
Symbol
Rating
Unit
Power Supply (VCC = 0)
Characteristic
VEE
-8.0 to 0
Vdc
Input Voltage (VCC = 0)
V,
OtoVEE
Vdc
Output Current- Continuous
-Surge
lout
50
100
rnA
Operating Temperature Range
TA
oto +75
'c
Tstg
-55 to +150
-55 to +165
'C
'C
Storage Temperature Range - Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%)
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
'E
-
112
-
102
-
112
rnA
Input Current High
Pins 5,6,9,11,12,13
Pins 7,10
Pin4
'inH
Input Current Low
linL
-
405
416
510
-
255
260
320
-
255
260
320
0.5
-
0.5
-
0.3
-
-1.02 -0.84 -0.98 -0.81
-
-0.92 -0.735
Low Output Voltage
VOL
-1.95 -1.63 -1.95 -1.63 -1.95
High Input Voltage
VIH
-1.17 -0.84 -1.13 -0.81
L Parallel Entry
L
H Shift Right·
Low Input Voltage
V,L
-1.95 -1.48 -1.95 -1.48 -1.95
01
02
03
Q2n
a3n
DR
L
Shift lett·
OL
QOn
Q1n
02n
H
H
Stop Shift
OOn
Q1n
02n
32n
DIP
PIN ASSIGNMENT
VCC1
02
01
Vdc
03
00
C
OL
OR
00
03
01
-1.60
Vdc
-1.07 -0.735
Vdc
-1.45
VCC2
ItA
Vdc
t~d
1.0
2.0
1.0
2.0
1.1
2.1
ns
Hold limeData, Select
thold
1.0
-
1.0
-
1.0
-
ns
Set-up lime
Data
Select
tset
1.5
3.0
-
1.5
3.0
-
1.5
3.0
-
52
51
VEE
02
ns
-
Rise lime
tr
0.5
2.4
0.5
2.4
0.5
2.4
Fall lime
tf
0.5
2.4
0.5
2.4
0.5
2.4
Ishift
250
-
250
-
250
-
Shift Frequency
DO
Q1n
H
AC PARAMETERS
Propagation Delay
OUTPUTS
OPERATING
MOOE
00n+1 Q1n+1 Q2n+1 03n +1
IlA
VOH
TRUTH TABLE
L
75'
Symbol
High Output Voltage
FN SUFFIX
PLCC
CASE 775-02
input conditions as shown (Pulse Positive transition of
clock input).
Characteristic
-
rs,rs;;
PSUFFIX
PLASTIC PACKAGE
CASE 64S-oS
.. Outputs as exist after pulse appears at ~C" Input WIth
25'
0'
SELECT
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
ns
ns
MHz
NOTE:
Each MECL 1OH series circuit has been designed to meet the de specifications shown in the test table,
after thermal equilibrium has been established. Thecircuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than SOO linear fpm is maintained. Outputs are terminated through
a 50 ohm resistor to -2.0 volts.
9/96
© Motorola, Inc. 1996
2-35
REVS
®
MOTOROLA
MC10H141
LOGIC DIAGRAM
D2
61
62
D1
DO
10F4
DECODER
DR - - - I + - - L J
DL
o
C
03
Q2
01
00
VCC1
PIN 1
6CC2
PIN 16
VEE = PINS
APPLICATION INFORMATION
The MC10H141 is a four-bit universal shift
register which performs shift left, or shift right,
serial/parallel in, and serial/parallel out operations
with no extemal gating. Inputs 81 and 82 control the
four possible operations of the register without
extemal gating of the clock. The flip-flops shift
MOTOROLA
information on the positive edge of the clock. The
four operations are stop shift, shift left, shift right, and
parallel entry of data. The other six inputs are all data
type inputs; four for parallel entry data, and one for
shifting in from the left (DL) and one for shifting in
from the right (DR).
2-36
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
16 x 4 Bit Register File (RAM)
MC10H145
The MC10H145 is a 16 x 4 bit register file. The active-low chip select allows
easy expansion.
The operating mode of the register file is controlled by the WE input. When
WE is "low" the device is in the write mode, the outputs are "low" and the data
present at Dn input is stored at the selected address, when WE is "high," the
device is in the read mode - the data state at the selected location is present
at the an outputs.
•
•
•
•
•
,..
-•
Address Access Time, 4.5 ns Typical
Power Dissipation, 700 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K-Compatible
MAXIMUM RATINGS
Symbol
Rating
Unit
Power Supply (VCC = 0)
Characteristic
VEE
-8.0 to 0
Vdc
Input Voltage (VCC = 0)
VI
OtoVEE
Vdc
Output Current- Continuous
-Surge
lout
50
100
mA
Operating Temperature Range
TA
o to +75
°c
Storage Temperature Range- Plastic
-Ceramic
-55 to +150
-55 to +165
Tstg
MODE
Write "0"
Write "1"
Read
Disabled
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%) (See Note)
25°
0°
75°
Symbol
Min
Max
Min
Max
Min
Power Supply Current
IE
-
160
-
163
-
165
mA
Input Current High
linH
-
375
-
220
-
220
Input Current Low
linL
0.5
!lA
!lA
High Output Voltage
VOH
-1.02 -0.64 -0.96 -0.61
Low Output Voltage
VOL
-1.95 -1.63 -1.95 -1.63 -1.95
High Input Voltage
VIH
-1.17 -0.64 -1.13 -0.61
Low Input Voltage
VIL
-1.95 -1.46 -1.95 -1.46 -1.95
-
0.5
-
0.3
Max
-
-0.92 -0.735
Unit
FNSUFFIX
PLCC
CASE 775-02
INPUT
CS
L
L
L
H
WE
L
L
H
X
OUTPUT
Qn
On
L
H
X
X
L
L
Q
L
Q-State of Addressed Cell
DIP
PIN ASSIGNMENT
Vdc
-1.60
Vdc
-1.07 -0.735
Vdc
-1.45
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
TRUTH TABLE
°C
Characteristic
LSUFFIX
CERAMIC PACKAGE
CASE 62D-l0
Vdc
NOTE:
Each MECL 1OH series circuit has been designed to meet the de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through
a 50·ohm resistor to -2.0 volts.
01
Vee
00
Q2
CS
03
01
WE
DO
03
A3
02
A2
AO
VEE
A1
Pin assignment is for Dual-in-Line Package.
For PlCC pin aSSignment, see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola, Inc. 1996
2-37
REVS
®
MOTOROL.A
MC10H145
AC PARAMETERS
MC10H145
TA 0 to +75'C,
VEE -5.2 Vdc ±5%
=
=
Characteristics
Symbol
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Chip Enable Strobe Mode
Data Setup Prior to Chip Select
Write Enable Setup Prior to Chip Select
Address Setup Prior to Chip Select
Data Hold Time After Chip Select
Write Enable Hold Time After Chip Select
Address Hold Time After Chip Select
Chip Select Minimum Pulse Width
Rise and Fall Time
Address to Output
CStoOutput
Capacitance
Input Capacitance
Output Capacitance
Min
tACS
tRCS
tAA
0
0
0
tw
twSD
twHD
twSA
twHA
twscs
twHCS
tws
twR
6.0
0
1.5
3.5
1.5
0
1.5
1.0
1.0
tCSD
tcsw
leSA
tCHD
tCHW
tCHA
tcs
0
0
0
1.0
0
2.0
4.0
Max
Conditions
ns
Measured Irom 50% of input to 50%
of output. See Note 2.
ns
tWSA=3.5ns
Measured at 50% of input to 50% of
output. tw = 6.0 ns.
ns
Guaranteed but not tested on
standard product. See Figure 1.
ns
Measured between 20% and 80%
points.
pF
Measured with a pulse technique.
4.0
4.0
6.0
--------
4.0
4.0
--
-----
--
--
tr.tf
Cin
Cout
Unit
0.6
0.6
2.5
2.5
---
6.0
8.0
NOTES: 1. Test circuit characteristics: Rr = 50 Q, MC1 OH145. CL " 5.0 pF (including jig and Stray Capacitance). Delay should be derated 30 psipF for
capacitive loads up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
3. For proper use of MECL in a system environment, consult MECL System Design Handbook.
FIGURE 1 -
CHIP ENABLE STROBE MODE
~Ir-------------------~Ir-------
A -----'1'- - -- -- -- -- -- -- ---- -- -JI'-_ __
J+--___+-- TCHA
TCSD
TCSA--foIII--~1- TCS
MOTOROLA
2-38
MECLData
DL122--Rev6
MC10H145
BLOCK DIAGRAM
00
AO
A1
01
02
03
10
~~
"'~
::lc
A2
\!!'"
"O~
"0«~
A3
L - - r - - - - r - - - - r - - - - r - . . r - - - WE
DO
MECLData
DL122-Rev6
01
2-39
02
03
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-lnput Multiplexer
(Non-Inverting)
MC10H158
The MCl OH158 is a quad two channel multiplexer with common input select.
A "high" level select enables input DOO, Dl0, D20 and D30 and a "low" level
select enables input DOl, Dll, D21 and D31. This MECL 10H part is a
functional/pinout duplication of the standard MECL 10K family part, with 100%
improvement in propagation delay and no increase in power-supply current.
-•
• Propagation Delay, 1.5 ns Typical
• Power Dissipation, 197 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Gompatible
MAXIMUM RATINGS
Characteristic
LSUFFIX
CERAMIC PACKAGE
CASE 62G-l0
PSUFFIX
PLASTIC PACKAGE
CASE 646-08
FNSUFFIX
PLCC
CASE 775-{)2
Symbol
Rating
Unit
VEE
-8.0 to 0
Vdc
VI
oto VEE
Vdc
Output Current- Continuous
-Surge
lout
50
100
rnA
Select
DO
01
Operating Temperature Range
TA
oto +75
°c
L
X
L
L
Tstg
-55 to +150
-55 to +165
°c
°c
L
X
H
H
H
L
X
L
H
H
X
H
=0)
Input Voltage (VCC =0)
Power Supply (VCC
Storage Temperature Range- Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%)
25°
0°
Characteristic
Symbol
Min
Max
Power Supply Current
IE
-
53
Input Current High
Pin9
Pins 3-8 and 10-13
linH
Input Current Low
linL
-
Min
-
-
-
475
515
-
0.5
-
0.5
TRUTH TABLE
Q
75°
Max
48
295
320
-
Min
0.3
Max
Unit
53
rnA
DIP
PIN ASSIGNMENT
ItA
295
320
-
ItA
00
VCC
High Output Voltage
VOH
-1.02 -0.84
-0.98
-0.81
-0.92
-0.735
Vdc
01
Q2
Low Output Voltage
VOL
-1.95 -1.63 -1.95
-1.63
-1.95
-1.60
Vdc
011
03
High Input Voltage
VIH
-1.17 -0.84 -1.13 -0.81
-1.07
-0.735
Vdc
010
020
Low Input Voltage
VIL
-1.95 -1.48
-1.48 -1.95
-1.45
Vdc
001
021
000
030
NC
031
-1.95
AC PARAMETERS
Propagation Delay
Data
Select
ns
tpd
0.5
1.0
1.9
2.9
0.5
1.0
1.9
2.9
0.5
1.0
2.0
2.9
Rise Time
tr
0.7
2.2
0.7
2.2
0.7
2.2
ns
Fall Time
tf
0.7
2.2
0.7
2.2
0.7
2.2
ns
VEE
SELECT
Pin assignment is for Dual-in-Line Package.
NOTE:
Each MECL 10H series circuit has been designed to meet the de specifications shown in the test table,
after thermal eqUilibrium has been established. The circuit Is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
a SQ-ohm resistor to -2.0 volts.
3/93
© Motorola, Inc. 1996
2-40
REV 5
®
MOTOROLA
MC10H158
LOGIC DIAGRAM
SELECT 9
001 5
1 00
000 6
011 3
2 01
010 4
021 12
1502
02013
031 10
14 Q3
03011
VCC=PIN 16
VEE = PIN B
MECLData
DL122- Rev 6
2-41'
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-lnput Multiplexer
(Inverting)
MC10H159
The MC10H159 is a quad 2-input multiplexer with enable. This MECL 10H
part is a functionaVpinout duplication of the standard MECL 10K family part,
with 100% improvement in propagation delay and no increase in power-supply
current.
""•
• Propagation Delay, 1.5 ns Typical
• Power Dissipation, 218 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
VEE
-8.0toO
Vdc
VI
OtoVEE
Vdc
lout
50
100
mA
=0)
Input Voltage (VCC =0)
Power Supply (VCC
Output Current- Continuous
-Surge
Operating Temperature Range
Storage Temperature Range- Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE
TA
Oto+75
°C
Tstg
-55 to +150
-55 to +165
°C
°C
25°
Characteristic
Symbol
Power Supply Current
IE
Input Current High
Pin 9
Pins 3-7 and 10-13
linH
Input Current Low
Min
Min
Max
56
-
53
475
515
-
295
320
-
0.5
linL
0.5
VOH
-1.02
Low Output Voltage
VOL
-1.95 -1.63
High Input Voltage
VIH
-1.17 -0.64 -1.13
Low Input Voltage
VIL
-1.95
High Output Voltage
-
-
TRUTH TABLE
Q
L
DO
X
01
L
L
H
L
L
X
H
L
L
H
L
X
H
L
H
H
H
X
X
X
X
L
L
-1.48
-1.95
-
Max
Unit
56
mA
~
DIP
PIN ASSIGNMENT
295
320
-
-0.92
-0.735
~
Vdc
00
VCC
-1.63 -1.95
-1.60
Vdc
Of
Q2
-0.61
-1.07 -0.735
Vdc
011
Q3
-1.46
-1.95
010
020
-0.64 -0.96 -0.61
-1.95
Min
0.3
-1.45
Vdc
AC PARAMETERS
Propagation Delay
Data
Select
Enable
ns
Ipd
0.5
1.0
1.0
2.2
3.2
3.2
0.5
1.0
1.0
2.2
3.2
3.2
0.5
1.0
1.0
2.2
3.2
3.2
tr
0.5
2.2
0.5
2.2
0.5
2.2
ns
Fall Time
tf
0.5
2.2
0.5
2.2
0.5
2.2
ns
NOTE:
Each MECL 1OH sertes circuit has been designed to meet the de speeHications shown in the test table,
aHerthennal equilibrium has been established. The eircun Is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through
a S Outpul
Clock Input -> Output
PSUFFIX
PLASTIC PACKAGE
CASE 64B-OB
TRUTH TABLE
=-5.2 V ±5"10) (See Note)
0"
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
REVS
®
MOTOROLA
MC10H165
8-INPUT PRIORITY ENCODER
controllers, and testing systems.
The input is active when high, (e.g., the three binary
outputs are low when input DO is high). The 03 output is
high when any input is high. This allows direct extension
into another priority encoder when more than eight inputs
are necessary. The MC10H165 can also be used to
develop binary codes from random logic inputs, for
addressing ROMs, RAMs, or for multiplexing data.
The MC10H165 is a device designed to encode eight
inputs to a binary coded output. The output code is that
of the highest order input. Any input of lower priority Is
ignored. Each output incorporates a latch allowing
synchronous operation. When the clock is low the outputs
follow the inputs and latch when the clock goes high. This
device is very useful for a variety of applications in
checking system status in control processors, peripheral
LOGIC DIAGRAM
C4
005
"}
017
).
0213
).
VCC1 = PIN 1
VCC2 = PIN 16
. VEE = PIN B
1
}--
J+v-
. r-I
0310
-;
=!
D
-l
."
=!
-;
-~
~
300
-
201
II'--
1502
~
1403
H }--
."
0512
076
....
-
H.
~J.
0411
069
~
I L-..[I
~
~
"
./
>-
>>-
""\
--./
~
I
>-
I
I'--
Numbers at ends of terminals denote pin numbers for Land P packages.
MOTOROLA
2-52
MECLData
DL122-Rev6
MC10H165
APPLICATION INFORMATION
system conditions, as represented at the encoder inputs,
which has priority in determining the next system
operation to be performed. The binary code showing the
address of the highest priority input present will appear at
the encoder outputs to control other system logic
functions.
A typical application of the Mel OH165 is the decoding
of system status on a priority basis. A 64-line priority
encoder is shown in the figure below. System status lines
are connected to this encoder such that, when a given
condition exists, the respective input will be at a logic high
level. This scheme will select the one of 64 different
64-LINE PRIORITY ENCODER
LBB
I
Iz
MC10H164
112 MC10Hl01
System
Clock
Highest
Pnorily
Input
~?I?r"iP
-...
,
00
,
~
07
:!!
01
U
02
'"
03
i§
C
-:-,
~
00
III
~
U
07
'"
C
-:-,
~
00
:!!
i§
U
07
'"
C
-:-,
~
00
III
~
U
07
"
C
-:-,
~
00
~
~
U
07
'"
C
-:-,
~
DO
is
~
U
07
'"
C
-:-,
~
00
~
,.U
07
C
Lowest
Priority
Input
III
II
·
...
Iz
I
MC10H1M
X7ABC
XO ....... X7 ABC
/ /1
/ /1
Six bit output
word yielding
number of
higheslpriorily
channel present
-;:::==
r-;:::::
01 I-' 02 ~ ....
07
02
at input
~J-
r--
01
BB
r-
'---
03
001-01
Q2
03
001--01
02
Q3
oot-01
02
03
00
01
02
03
DO
01
02
03
00
01
....:.....- 07
03
MECLData
DL122-Rev6
Iz
MC1OH1M
O0i--
- : - 00
,
II
Q2
2-53
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
5-Bit Magnitude Comparator
MC10H166
The MC1 OH166 is a 5-Bit Magnitude Comparator and is a functionaV pinout
duplication of the standard MECL 10K part with 100% improvement in
propagation delay and no increase in power-supply current.
The MC1 OH166 is a high-speed expandable 5-bit comparator for
comparing the magnitude of two binary words. Two outputs are provided: AB. The A = B function can be obtained by wire-ORing these outputs (a
low level indicates A B) or by wire-NORing the outputs (a high level indicates
A B). A high level on the enable function forces both outputs low.
-•
=
=
Propagation Delay, Data-to-Output, 2.0 ns Typical
Power Dissipation 440 mW Typical
o Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
o Voltage Compensated
o MECL 10K-Compatible
o
o
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
VEE
-8.0 to 0
Vdc
=0)
Input Voltage (VCC =0)
Power Supply (VCC
OtoVEE
Vdc
50
100
mA
TA
Oto +75
Tstg
-55 to +150
-55 to +165
°c
°c
°c
. VI
Output Current- Continuous
-Surge
lout
Operating Temperature Range
Storage Temperature Range- Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%) (See Note)
0°
Characteristic
Symbol
Min
25°
Max
Min
LSUFFtX
CERAMIC PACKAGE
CASE 62(}-10
PSUFFIX
PLASTIC PACKAGE
CASE 641HlB
FNSUFFIX
PLCC
CASE 775-02
TRUTH TABLE
Inputs
I
E
A
H
X
L
WORD A
L
L
Outputs
B
A WORD B
L
H
WORD A < WORD B
H
L
I
=WORD B
75°
Max
Min
Max
Unit
DIP
PIN ASSIGNMENT
IE
-
117
-
106
-
117
mA
Input Current High
linH
-
350
-
220
-
220
Input Current Low
linL
0.5
-
0.5
-
0.3
IlA
IlA
VCCI
Vdc
A>B
Vdc
Ahm resistor to -2.0 volts.
For PLCC pin asSignment, see the Pin Conversion
Tables on page 1>-11.
3/93
© Motorola, Inc. 1996
A>B
2-54
REVS
®
MOTOROLA
MC10H166
LOGIC DIAGRAM
A4 109 :::~;JC>-------I
64
A3 12 --...........--....
6S11--...w....~
2A>6
A2 13 -+t"'\r~.!:::I::i-H+___r__....
6214--...w....~
SA-_--.J
60 4-
PIN 1
PIN 16
PINS
E15--------------------------------~
FIGURE 1 AO BO Al Bl
f{l
9-BIT MAGNITUDE COMPARATOR
B2 A3 B3 A4 B4
AS B5 AS B6 A7 B7 AS B8
MC10HI88
bB
AB
A 8 and
A < 8 outputs are fed to the AO and 80 inputs respectively
MECLDala
DL122-Rev6
=
of the next device. The connection for an A 8 output is
also shown. The worst case delay time of serial
expansion is equal to the number of comparators times
the data-to--output delay.
2-55
MOTOROLA
MC10H166
FIGURE 2 - 25-BIT MAGNITUDE
COMPARATOR
[2J
B24
A24
823
A23
B22
A22
821
A21
B20
A20
B4
A4
B3
A3 AB
AI
BO
AD
BI9
AI9
BIB
AlB
BI7
A17
BIS
AIS
BI5
AI5
B4
A4
83
A3 AB
AI
BO
AD
BI4
AI4
BI3
AI3
BI2
AI2
BII
All
BID
AID
B4
A4
83
A3 AB
AI
BO
AD
B9
A9
BB
AB
B7
A7
BB
AS
B5
AS
B4
A4
83
A3
82
A2
BI
AI
BO
AD
MOTOROLA
B4
A4
83
A3 AB
AI
BO
AD
B4
A4
B3
A3 AB
AI
BO
AD
A=B
AB
For shorter delay times than possible with seriai expansion,
devices can be cascaded. Figure 2 shows a 25-bit cascaded
comparator whose worst case delay is two data-tB
AI
BO
AD
2-56
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Binary to 1-4 Decoder
(Low)
MC10H171
-•
The MC1 OH171 is a binary coded 2 line to dual 4 line decoder with selected
outputs low. With either EO or E1 high, the corresponding selected 4 outputs are
high. The common enable E, when high, forces all outputs high.
•
•
•
Propagation Delay, 2 ns Typical
Power Dissipation 325 mW Typical (same as MECL 10K)
Improved Noise Margin 150 mV (over operating voltage and
temperature range)
• Voltage Compensated
• MECL 10K-Compatible
MAXIMUM RATINGS
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-0S
FN SUFFIX
PLCC
CASE 775-{)2
LOGIC DIAGRAM
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
VEE
-8toO
Vdc
10003
Input Voltage (VCC = 0)
VI
Oto VEE
Vdc
11 002
lout
50
100
mA
TA
Oto +75
'C
Tstg
-55 to +150
-55 to +165
'C
Output Current- Continuous
-Surge
Operating Temperature Range
Storage Temperature Range- Plastic
-Ceramic
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
IE
-
85
-
77
85
mA
265
-
IIA
IIA
linH
-
425
-
265
linL
0.5
-
0.5
-
0.3
High Output Voltage
VOH
-1.02 -0.84 -0.98 -0.81
-0.92 -0.735
Low Output Voltage
VOL
-1.95 -1.63 -1.95 -1.63 -1.95
High Input Voltage
VIH
-1.17 -0.84 -1.13 -0.81
Low Input Voltage
VIL
-1.95 -1.48 -1.95 -1.48 -1.95
3013
4012
Symbol
Input Current Low
13000
87
Characteristic
Input Current High
12001
A9
ELECTRICAL CHARACTERISTICS (VEE = --5 2 V +5%)
(See Note)
25'
75'
0'
-
1:014
1:15
VCC1" PIN 1
VCC2" PIN 16
VEE"PIN8
-1.60
Vdc
Vdc
DIP
PIN ASSIGNMENT
Vdc
AC PARAMETERS
VCCl
25'
0'
Characteristic
Propagation Delay
Data
Select
6010
E12
Vdc
-1.07 -0.735
-1.45
5011
Symbol
Min
Max
Min
75'
Max
Min
Max
0.5
0.5
2.0
2.6
0.5
0.5
2.1
2.7
0.5
0.5
E1
013
EO
Unit
ns
tpd
2.2
2.8
VCC2
I:
012
000
Rise Time
tr
0.5
1.7
0.5
1.8
0.5
1.9
ns
011
001
Fall Time
tf
0.5
1.7
0.5
1.8
0.5
1.9
ns
010
002
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
8
003
afterthermaJ equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through
VEE
A
a 5Q-ohm resislor to -2.0 volts.
Pin assignment is for DuaHn-line Package.
For PLCC pin aSSignment, see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola, Inc. 1996
2-57
REV5
®
MOTOROLA
MC10H171
TRUTH TABLE
Enable Inputs
MOTOROLA
Inputs
Outputs
E
EO
El
A
B
010
all
012
013
000
001
002
003
L
L
L
L
L
L
H
L
L
L
L
L
H
X
L
L
L
L
H
L
X
L
L
H
H
L
L
X
L
H
L
H
L
L
X
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
2-58
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Binary to 1-4-Decoder
(High)
MC10H172
-•
The MC1 OH172 is a binary coded 2 line to dual 4 line decoder with selected
outputs high. With either EO or E1 low, the corresponding selected 4 outputs are
low. The common enable E, when high, forces all outputs low.
o
o
o
o
o
Propagation Delay, 2 ns Typical
Power Dissipation 325 mW Typical (same as MECL 10K)
Improved Noise Margin 150 mV (over operating voltage and
temperature range)
Voltage Compensated
MECL 10K-Compatible
MAXIMUM RATINGS
Characteristic
=0)
Input Voltage (VCC =0)
Power Supply (VCC
Symbol
Rating
Unit
VEE
-8toO
Vdc
VI
OtoVEE
Vdc
Output Current- Continuous
-Surge
lout
50
100
rnA
Operating Temperature Range
TA
Oto+75
'C
Tstg
-55 to +150
-55 to +165
'C
Storage Temperature Range- Plastic
-Ceramic
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PlCC
CASE 775-02
LOGIC DIAGRAM
EO 14
10003
11002
12001
A9
13000
3013
67
-
ELECTRICAL CHARACTERISTICS (VEE = -5 2 V +5%) (See Note)
0'
25'
Characteristic
Symbol
Min
Max
Power Supply Current
IE
-
85
Input Current High
linH
-
425
Input Current Low
linL
0.5
-
Min
0.5
4012
75'
Max
Min
Max
Unit
77
-
85
rnA
265
-
265
-
0.3
-
!iA
!iA
High Output Voltage
VOH
-1.02 -0.84 -0.98 -0.81
Low Outpul Voltage
VOL
-1.95 -1.63 -1.95 -1.63 -1.95
High Input Voltage
VIH
-1.17 -0.84 -1.13 -0.81
-1.07 -0.735
Vdc
Low Input Voltage
VIL
-1.95
-1.95
Vdc
-1.48 -1.95 -1.48
-0.92 -0.735
-1.60
-1.45
5011
E15
6010
E12
VCCl = PIN 1
VCC2=PIN 16
VEE=PINB
Vdc
Vdc
DIP
PIN ASSIGNMENT
AC PARAMETERS
0'
Characteristic
Propagalion Delay
Data
Select
Symbol
25'
VCCl
75'
Min
Max
Min
Max
Min
Max
0.5
0.5
2.0
2.6
0.5
0.5
2.1
2.7
0.5
0.5
2.2
2.8
tpd
VCC2
Unit
El
E
ns
013
EO
012
000
Rise lime
tr
0.5
1.7
0.5
1.8
0.5
1.9
ns
Fall lime
If
0.5
1.7
0.5
1.8
0.5
1.9
ns
011
001
010
002
NOTE:
Each MECL 10H selies circuit has been designed to meet the de specifications shown in the test table,
6
003
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated
through a SD-ohm resistor to -2.0 volts.
VEE
A
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola, Inc. 1996
2-59
REV 5
®
MOTOROLA
MC10H172
TRUTH TABLE
Enable Inputs
MOTOROLA
Outputs
Inputs
E
El
EO
A
B
010
all
012
013
000
001
002
003
L
L
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
L
L
L
H
H
L
L
L
H
"L
X
X
X
X
H
L
L
L
L
H
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
L
L
2-60
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-lnput Multiplexer/
Latch
MC10H173
The MC10H173 is a quad 2-input multiplexer with latch. This device is a
functional/pinout duplication of the standard MECL 10K part, with 100%
improvement in propagation delay and no increase in power supply current.
•
•
•
Data Propagation Delay, 1.5 ns Typical
•
Power Dissipation, 275 mW Typical
•
Improved Noise Margin 150 mV (over
operating voltage and temperature range)
,..
•
Voltage Compensated
MECL 10K-Compatible
~
ri~uu
MAXIMUM RATINGS
Characteristic
Power Supply (VCC =0)
Input Voltage (VCC
=0)
Output Current - Continuous
Symbol
Rating
Unit
VEE
-8.0toO
Vdc
VI
OtoVEE
Vdc
lout
50
100
mA
TA
Oto+75
Tstg
-55 to +150
-55 to +165
'c
'c
-Surge
Operating Temperature Range
Storage Temperature Range - Plastic
-Ceramic
Characteristic
Power Supply Current
Input Current High
Pins 3-7 & 10-13
Pin9
75'
25'
Symbol
Min
Max
Min
Max
Min
Max
Unit
IE
-
73
-
66
-
73
mA
-
510
475
-
-
320
300
-
-
320
300
linH
linL
0.5
-
0.5
-
0.3
-
I1A
VOH
-1.02
-{).B4
-{).98
-{).81
-{).92
-{).735
Vdc
Low Output Voltage
VOL
-1.95
-1.63
-1.95
-1.63
-1.95
-1.60
Vdc
High Input Voltage
VIH
-1.17
-{).84
-1.13
-{).81
-1.07
--0.735
Vdc
Low Input Voltage
VIL
-1.95
-1.48
-1.95
-1.48
-1.95
-1.45
Vdc
ns
tpd
0.7
1.0
1.0
Set-upTime
Data
Select
tset
Hold Time
Data
Select
thold
Rise1ime
Fall Time
2.3
3.7
3.6
0.7
1.0
1.0
2.3
3.7
3.6
0.7
1.0
1.0
2.3
3.7
3.6
ns
-
0.7
1.0
-
0.7
1.0
-
-
-
0.7
1.0
-
0.7
1.0
-
0.7
2.4
0.7
2.4
0.7
2.4
ns
0.7
2.4
0.7
2.4
0.7
2.4
ns
0.7
1.0
-
0.7
1.0
tr
tf
SELECT
CLOCK
QDn + 1
H
L
X
L
L
H
aOn
000
001
DIP
PIN ASSIGNMENT
AC PARAMETERS
Propagation Delay
Data
Clock
Select
FNSUFFIX
PLCC
CASE 775-{)2
I1A
High Oulput Voltage
Input CUrrent Low
PsUFFIX
PLASTIC PACKAGE
CASE 648-{)8
TRUTH TABLE
'C
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%) (See Note)
0'
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
ns
NOTE:
Each MECL 1OH series circuit has been designed to meet the de specifications shawn in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated
00
VCC
01
02
011
03
010
020
001
021
000
030
CLOCI<'
031
SELECT
VEE
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
through a 5D-ohm resistor to -2.0 vol Is.
3/93
© Motorola, Inc. 1996
2-61
REVS
®
MOTOROLA
MC10H173
APPLICATION INFORMATION
The MGl 0173 is a quad two--channel multiplexer with
latch. It incorporates common clock and common data
select inputs. The select input determines which data
input is enabled. A high (H) level enables data inputs
DOO, Dl 0, D20, and D30 and a low (L) level enables data
inputs DOl, Dll, D21, D31. Any change on the data input
will be reflected at the outputs while the clock is low. The
outputs are latched on the positive transition of the clock.
While the clock is in the high state, a change in the
information present at the data inputs will not affect the
output information.
LOGIC DIAGRAM
SELECT 9
000 6
----+-+-"-L---"
100
001 5 ----I-I-,L..-"
010 4
---+-+-+-"-L.-
011 3
---1-+.......--£._""
020 13 ---+-+--+-~
2 01
1502
02112 ----t-+--+'~_-"
03011
----t-+--'-L_-"
03110
---+--'""-L.-
1403
CLOCK 7
VCC = PIN 16
VEE = PIN 8
MOTOROLA
2-62
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4 to 1 Multiplexer
MC10H174
The MC10H174 is a Dual 4-t0-1 Multiplexer. This device is a functional!
pinout duplication of the standard MECL 10K part, with 100% improvement in
propagation delay and no increase in power supply current.
•
•
•
•
•
Propagation Delay, 1.5 ns Typical
Power Dissipation, 305 mW Typical
Improved Noise Margin 150 mV (over operating voltage and
temperature range)
Voltage Compensated
MECL 10K-Gompatible
-•
MAXIMUM RATINGS
Characteristic
Symbol
=0)
=0)
Rating
Unit
Power Supply (VCC
VEE
-8.0 to 0
Vdc
Input Voltage (VCC
VI
OtoVEE
Vdc
Output Current- Continuous
-Surge
lout
50
100
rnA
Operating Temperature Range
TA
Oto +75
Tstg
-55 to +150
-55 to +165
'c
'c
'c
Siorage Temperature Range- Plastic
-Ceramic
ENABLE
Characteristic
Power Supply Current
Symbol
Min
Max
IE
-
80
-
475
670
0.5
-
Input Current High
Pins 3-7 & 9-13
Pin 14
linH
Input Current Low
linL
75'
25'
Min
Max
Min
-
73
-
-
300
420
0.5
-
Max
Unit
80
rnA
!lAde
-
300
420
0.3
-
High Output Voltage
VOH
-1.02 -0.84 -0.98 -0.81 -0.92 -0.735
!lA
Vdc
Low Output Voltage
VOL
-1.95 -1.63 -1.95 -1.63 -1.95
-1.60
Vdc
High Input Voltage
VIH
-1.17 -0.84 -1.13 -0.81 -1.07 -0.735
Vdc
Low Input Voltage
VIL
-1.95 -1.48 -1.95 -1.48 -1.95
FN SUFFIX
PLCC
CASE 775-02
Vdc
-1.45
ADDRESS INPUTS
OUTPUTS
E
B
A
Z
H
X
X
L
W
L
L
L
L
XO
YO
L
L
H
Xl
Yl
L
H
L
X2
Y2
L
H
H
X3
Y3
DIP
PIN ASSIGNMENT
VCC1
AC PARAMETERS
Propagalion Delay
Dala
Select (A, B)
Enable
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
TRUTH TABLE
ELECTRICAL CHARACTERISTICS (VEE = -5 2 V +5%)
- (See Note)
0'
LSUFFIX
CERAMIC PACKAGE
CASE 62D-l0
00
VCC2
01
ns
tpd
0.7
1.0
0.4
2.4
2.8
1.45
0.8
1.1
0.4
2.5
2.9
1.5
0.9
1.2
0.5
2.6
3.2
1.7
000
ENABLE
002
010
012
Rise Time
tr
0.5
1.5
0.5
1.6
0.5
1.7
ns
001
Fall Time
If
0.5
1.5
0.5
1.6
0.5
1.7
ns
003
011
NOTE:
Each MECL 1OH series circuit has been designed to meet the dc specifications shown in the test table,
A
013
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated
VEE
through a 50-ohm resistor to -2.0 volts.
B
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
9/96
© Motorola, Inc. 1996
2-63
REV6
®
MOTOROLA
MC10H174
LOGIC DIAGRAM
XO 3
Xl
2Z
X2 4
X3 6
A
7
B
ENABLE 14
[I]
YO
13
Yl
11
Y2
12
Y3
10
15W
VCCl = PIN 1
VCC2= PIN 16
VEpPINB
MOTOROLA
2-64
MECLData
DL122 - Rev 6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quint Latch
MC10H175
The MC10H175 is a quint D type latch with common reset and clock lines.
This MECL 10KH part is a functionaVpinout duplication of the standard MECL
10K family part, with 100% improvement in propagation delay and no increase
in power-supply current.
•
•
•
Propagation Delay, 1.2 ns Typical
Power Dissipation, 400 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
-•
MAXIMUM RATINGS
Characteristic
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current- Continuous
-Surge
Symbol
Rating
Unit
VEE
-8.0toO
Vdc
VI
OtoVEE
Vdc
lout
50
100
rnA
°c
'c
'c
Operating Temperature Range
TA
o to +75
Storage Temperature Range- Plastic
-Ceramic
Tstg
-55 to +150
-5510+165
Min
25'
75'
Characteristic
Symbol
Power Supply Current
IE
Input Current High
Pins 5,6,7,9,10,12,13
Pin 11
linH
Input Current Low
linL
High Output Voltage
VOH
-1.02 -0.84 -0.98
Low Output Voltage
VOL
-1.95
High Input Voltage
VIH
-1.17 -0.84 -1.13 -0.81
Low Input Voltage
VIL
Max
Min
Max
Min
Max
Unit
107
-
97
-
107
rnA
-
565
1120
-
335
660
0.5
-
0.5
-
0.3
-
I1A
-0.81
-0.92
-0.735
Vdc
-1.60
Vdc
-1.07
-0.735
Vdc
-1.95 -1.48 -1.95 -1.48 -1.95
-1.45
Vdc
-
-
-1.63 -1.95 -1.63 -1.95
0.6
0.7
1.0
1.6
2.0
2.3
0.6
0.8
1.0
tset
1.5
Hold Time
thold
0.8
-
0.8
-
0.8
-
Rise Time
tr
0.5
1.8
0.5
1.9
0.5
2.0
ns
Fall Time
tf
0.5
1.8
0.5
1.9
0.5
2.0
ns
1.5
ns
ns
NOTE:
Each MEeL 10H series circuit has been designed to meet the de specifications shown in the test
table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a
printed Circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are
terminated through a 5O-<>hm resistor to -2.0 volts.
2-65
Reset
On+l
L
L
X
H
X
H
X
X
L
L
H
H
L
H
an
an
L
L
VCC2
02
01
03
00
04
D2
D4
Dl
CO
RESET
CT
DO
VEE
D3
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3193
© Motorola, Inc. 1~96
Cl
L
L
H
X
H
X
VCCI
1.7
2.1
2.4
Set-up Time
1.5
CO
L
H
X
X
X
X
DIP
PIN ASSIGNMENT
ns
1.6
1.9
2.2
0
I'A
tpd
0.6
0.7
1.0
FN SUFFIX
PLCC
CASE 775-02
335
660
AC PARAMETERS
Propagation Delay'
Data
Clock
Reset
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
TRUTH TABLE
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%) (See Note)
0'
LSUFFtX
CERAMIC PACKAGE
CASE 62D-l0
REV 5
@
MOTOROl.A
MC10H175
APPLICATION INFORMATION
outputs while the clock is low. The outputs are latched on
the positive transition olthe clock. While the clock is in the
high state, a change in the information present at the data
inputs will not affect the output information. THE RESET
INPUT IS ENABLED ONLY WHEN THE CLOCK IS IN
THE HIGH STATE.
The MC10H175 is a high speed,low power quint latch.
It features five D type latches with common reset and a
common two-input clock. Data is transferred on the
negative edge of the clock and latched on the positive
edge. The two clock inputs are "OR"ed together.
Any change on the data input will be reflected at the
LOGIC DIAGRAM
DO 10
--------""1
1400
D
D112
[l]
1501
C
D
D213
202
C
D
D39
303
C
0
045
404
C06
C17
RESET 11
VCCI =PIN 1
VCC2=PIN 16
VEE= PIN 8
MOTOROLA
2-66
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Master-Slave Flip-Flop
MC10H176
The MC10H176 contains six master slave type D flip-flops with a common
clock. This MECL 10H part is a functional/pinout duplication of the standard
MECL 10K family part, with 100% improvement in clock frequency and
propagation delay and no increase in power-supply current.
•
•
•
Propagation Delay, 1.7 ns Typical
Power Dissipation, 460 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
-, .
•
MAXIMUM RATINGS
Characteristic
Power Supply (Vec = 0)
Symbol
Rating
Unit
VEE
-8.0 to a
Vdc
VI
OtoVEE
Vdc
Output Current- Continuous
-Surge
lout
50
100
mA
Operating Temperature Range
TA
Oto +75
°C
Tstg
-55 to +150
-55 to +165
°C
°C
Input Voltage (VCC = 0)
Storage Temperature Range- Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE
25°
75°
Characteristic
Symbol
Min
Max
Min
Max
Power Supply Current
IE
-
123
-
112
Input Current High
Pins 5,6,7,10,11,12
PinS
linH
-
425
670
-
265
420
0.5
-
0.5
-
Input Current Low
linL
High Output Voltage
VOH
-1.02 --{).B4 --{).SB --{).Bl
Min
-
Max
Unit
123
mA
265
420
0.3
-
IlA
--{).735
Vdc
Vdc
Low Output Voltage
VOL
-1.S5 -1.63 -1.S5 -1.63 -1.S5
-1.60
High Input Voltage
VIH
-1.17 --{).B4 -1.13 --{).Bl
--{).735
Vdc
Low Input Voltage
VIL
-1.S5 -1.48 -1.S5 -1.48 -1.S5
-1.45
Vdc
2.4
ns
t~d
O.S
2.1
O.S
2.2
1.0
DIP
PIN ASSIGNMENT
VCCI
05
01
04
02
03
thold
1.0
-
Rise TIme
tr
0.5
1.B
0.5
I.S
0.5
2.0
ns
Fall TIme
tf
0.5
I.B
0.5
I.S
0.5
2.0
ns
!tQQ_
250
MHz
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test
table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a
printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are
terminated through a 50-0hm resistor to -2.0 volts.
VEE
CLOCK
Pin assignment is for DuaHn-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3/93
2-67
VCC2
00
05
1.5
-
© Motorola, Inc. 1996
H
Q3
-
O.S
-
H
00
1.5
-
250
L
H'
ns
-
-
L
ns
1.5
250
an
H'
Q4
O.S
-
On+l
X
01
tset
Toggle Frequency
a
L
02
Hold TIme
Set-upTIme
C
" A clock H Is a clock transition from
a low to a high state.
AC PARAMETERS
Propagation Delay
FNSUFFIX
PLCC
CASE 775-02
IlA
--{).S2
-1.07
PSUFFIX
PLASTIC PACKAGE
CASE648-0B
CLOCKED TRUTH TABLE
=-5.2 V ±5%) (See Note)
0°
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-l0
REV 5
®
MOTOROI.A
MC10H176
APPLICATION INFORMATION
The MC1 OH176 contains six high-speed, master slave
type "D" flip-flops. Data is entered into the master when
the clock is low. Master-to-slave data transfer takes
place on the positive-going Clock transition. Thus,
outputs may change only on a positive-going Clock
transition. A change in the information present althe data
(D) input will not affect the output information any other
time due to the master-slave construction of this device.
LOGIC DIAGRAM
00
00
01
02
7
3
01
4
02
D3
10-+~
13
03
04
11
--+--t
14
04
05
12-+~
15
05
CLOCK
9
VCC1 = PIN 1
VCC2=PIN 16
VEE = PINS
MOTOROLA
2-68
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Look-Ahead Carry Block
MC10H179
The MCl OH179 is a functionaVpinout duplication of the standard MECL 10K
part, with 100"10 improvement in propagation delay and no increase in power
supply cu rrent.
•
•
Power Dissipation, 300 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
-•
MAXIMUM RATINGS
Characteristic
=0)
Input Voltage (VCC =0)
Power Supply (VCC
Output Current- Continuous
-Surge
Operating Temperature Range
Storage Temperature Range- Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE
Symbol
Rating
Unit
VEE
-8.0 to a
Vdc
VI
OtoVEE
Vdc
lout
50
100
mA
TA
a to +75
Tstg
-55 to +150
-5510+165
'c
'c
Characteristic
Power Supply Current
Symbol
IE
Min
-
25'
Max
Min
79
-
72
Min
-
VCCl
Max
79
Unit
mA
~A
Input Current High
Pins 5 and 9
Pins 4, 7 and 11
Pin 14
Pin 12
Pins 10 and 13
linH
Input Current Low
linL
0.5
-
0.5
-
0.3
-
~
High Output Voltage
VOH
-1.02
-0.84
-0.98
-0.81
-0.92
-0.735
Vdc
Low Output Voltage
VOL
-1.95
-1.63
-1.95
-1.63
-1.95
-1.60
Vdc
High Input Vollage
VIH
-1.17
-0.84
-1.13
-0.81
-1.07
-0.735
Vdc
Low Input Voltage
VIL
-1.95
-1.48
-1.95
-1.48
-1.95
-1.45
Vdc
0.4
1.4
0.4
1.5
0.5
1.7
-
-
-
465
545
705
790
870
-
-
-
275
320
415
465
510
-
-
FNSUFFIX
PLCC
CASE 775-02
'C
75'
Max
P SUFFIX
PLASTIC PACKAGE
CASE 64B-08
DIP
PIN ASSIGNMENT
=-5.2 V ±5"1o) (See Note)
A'
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
275
320
415
465
510
VCC2
GG
PG
CN+4
PO
GO
P3
G3
P2
CN+2
CN
Gl
Pl
VEE
G2
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
AC PARAMETERS
Propagation Delay
Pto PG
G, P, Cnto
CnorGG
ns
tpd
0.6
2.3
0.7
2.4
0.8
2.6
Rise Time
tr
0.5
1.7
0.5
1.8
0.5
1.9
ns
Fall Time
tf
0.5
1.7
0.5
1.8
0.5
1.9
ns
NOTE:
Each MECL 1OH series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is In a test socket or mounted on a printed
circuit board and transverse airflow greater than 500 Ifpm is maintained. Outputs are terminated through
a SD-ohm resistor to -2.0 volts.
3193
© Motorola, Inc. 1996
2-89
REVS
®
MOTOROLA
MC10H179
LOGIC DIAGRAM
G35
P313
G2 9
P2 12
Gl 7
PlIO
GO 4
PINI
PIN16
PINS
PO 14
PG
GG
CN+2
CN+4
PO+Pl +P2+P3
(GO + PI + P2 + P3)(GI + P2 + P3) (G2 + P3) G3
= (CN+PO+Pl)(GO+Pl)Gl
= (CN + PO + PI + P2 + P3)(GO + PI + P2 + P3)(G1+ P2 + P3)
(G2+ P3)G3
=
=
TYPICAL APPLICATIONS
The MCI OH179 is a high-speed, low-power, standard
MECL complex function that is designed to perform the
look-ahead carry function. This device can be used with
the MCI OH 181 4-bit ALU directly, or with the MCl OH180
dual arithmetic unit in any computer, instrumentation or
digital communication application requiring high speed
arithmetic operation on long words.
When used with the MC10H181, the MC10H179
performs a second order or higher look-ahead. Figure 2
shows a 16-bit look-ahead carry arithmetic unit. Second
order carry is valuable for longer binary words. As an
example, addition of two 32-bit words is improved from
30 nanoseconds with ripple-carry techniques. A block
diagram of a 32-bit ALU is shown in Figure 1. The
MCl OH179 may also be used in many other applications.
It can, for example, reduce system package count when
used to generate functions of several variables.
FIGURE 1 - 32-BIT ALU WITH CARRY LOOK-AHEAD
MOTOROLA
2-70
MECLData
DL122-Rav6
MC10H179
FIGURE 2 -
16-BIT FULL LOOK-AHEAD CARRY ARITHMETIC LOGIC UNIT
81
iO Bf
85
A2
Al
A5
B2
I
11 i
3
3
A 8 A 8 A 8 A B
0 0 11 22 3 3
Cn
Cn+4
-M
MC10H181
Gr - - 80
; - - 81 ..BIT ARITliMETIC
LOGIC
UNIT
, - S2
P
53 FO Fl
F2 F3
i4
B13
A14
B9
A6
A9
86
iI
A B A B A B A B
o 0 11 2 2 33
Cn
Cn+4
M
MC10H181
-80
Gir-- 81 ..81T ARITliMETIC
LOGIC UNIT
-S2
P
83 FO F1
F2 Fa
r-
,-
L
A13
Bl0
~8 1 I
All
18;1
1
8
117 j7
Al0
ABABABAB
00112233
Cn
Cn+4
-M
-SO
r-- 81
,-52
MC10H181
.. BIT ARITHMETIC
LOGIC UNIT
83 FO
Fl
F2
F8
F9
FlO Fll
F3
GP
A;2T
B14
I II
A15
B;5
A 8 A 8 A 8 A 8
00 11 2 2 3 3
Cn
Cn +4 ;--M
MC10H181
G- - : - 80
; - - 81 "BIT ARITliMETIC
LOGIC
UNIT
P
82
83 FO
Fl
F2
F3
M
80
81
82
83
FO
Fl
F2
F3
F4
F5
F6
F7
PO
GO
Cn
II I
Pl
Gl P2 G2
MC10H179
CARRY LOOK-AHEAD
Cn+2
I
MECLData
DL122-Rev6
2-71
Cn+4
I
P3
F12 F13 F14 F15
G3
G I-PI--
C15
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-Bit Adder/Subtractor
MC10H180
The MC10H180 is a high-speed, low-power, general-purpose adderl
subtractor. It is designed to be used in special purpose adders/subtractors or in
high-speed multiplier arrays.
Inputs for each adder are Carry-in, Operand A, and Operand B; outputs are
Sum, Sum and Carry-Qut. The common select inputs serve as a control line to
Invert A for subtract, and a control line to Invert B.
-, .
•
• Propagation Delay, 1.8 ns Typical, Operand and Select to Output
• Power Dissipation, 360 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
VEE
-8.0 to 0
Vdc
VI
OtoVEE
Vdc
lout
50
100
rnA
TA
Oto +75
°c
Tstg
-55 to +150
-55 to +165
°c
°c
=0)
Input Voltage (VCC =0)
Power Supply (VCC
Output Current- Continuous
-Surge
Operating Temperature Range
Storage Temperature Range- Plastic
-Ceramic
ELECTRICAL CHARACTERISTICS (VEE
Symbol
Power Supply Current
IE
Input Current High
Pins 4, 12
Pins 7,9
Pins 5,6,10,11
linH
Input Current Low
linL
Min
0.5
25°
Max
95
665
515
410
-
Min
7
9
5
6
4
SELA
SELa
AO
BO
CIN
15
2
14
1
0.5
Max
Min
Max
Unit
86
-
95
rnA
417
320
255
-
417
320
255
-
0.3
-
VOH
-1.02 -0.84 -0.98 -0.81
Low Oulput Voltage
VOL
-1.95 -1.63 -1.95 -1.63 -1.95
High Input Voltage (1)
VIH
-1.17 -0.84 -1.13 -0.81
Low Input Voltage (1)
VIL
-1.95 -1.48 -1.95 -1.48 -1.95
-0.92 -0.735
VCC= PIN 16
VEE= PINS
POSITIVE LOGIC ONLY
A' = A Ell SELA = A8SELA
B' = B Ell SELB =B8SELB
S = CIN(~B'+A'il')+
CIN(A' B' + ~ B')
COUT = CINA' + CINB' + A' B'
!lA
Vdc
Vdc
-1.07 -0.735
Vdc
Vdc
DIP
PIN ASSIGNMENT
ns
tpd
2.4
2.2
1.6
0.7
0.7
0.4
2.5
2.3
1.7
0.8
0.8
0.4
2.8
2.6
1.8
13
!lA
-1.60
-1.45
11
10
12
AC PARAMETERS
0.6
0.6
0.4
FNSUFFfX
PLCC
CASEnlHl2
LOGIC DIAGRAM
75°
High Output Voltage
Propagation Delay
Operand to Output
Select to Output
Carry-in to Output
PSUFFtX
PLASTIC PACKAGE
CASE 648-08
=-5.2 V ±5%) (See Note)
0°
Characteristic
LSUFFfX
CERAMIC PACKAGE
CASE 62Q-l0
RisaTIme
Ir
0.5
2.0
0.5
2.1
0.5
2.2
ns
Fall TIme
If
0.5
2.0
0.5
2.1
0.5
2.2
ns
Sf
SO
COUT
SI
CIN
NOTES:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
afterthermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50-0hm resistor to -2.0 volts.
VCC
SO
COUT
AO
CIN
BO
Al
SELA
Bl
VEE
SELB
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3193
© Motorola, Inc. 1996
2-72
REVS
®
MOTOROLA
MC10H180
FUNCTION SELECT TABLE
SelA
H
H
L
L
Function
SelB
H
S=Aplus B
L
H
L
S =Aminus B
S = B minus A
S - 0 minus A minus B
TRUTH TABLE
FUNCTION
ADD
SUBTRACT
MECLData
DL122-Rev6
INPUTS
INPUTS
SelB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
FUNCTION
Cin
SO
so
Cout
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
H
L
H
L
H
H
L
L
H
L
H
H
L
L
L
L
H
L
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
L
L
H
L
H
H
L
L
H
H
L
H
L
L
H
L
H
L
L
H
H
L
H
AD BO
SelA
2-73
L
SelA Sele AD BO
REVERSE
SUBTRACT
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
Cin
SO
so
Co~t
L
H
L
L
H
L
H
H
L
L
H
H
L
H
L
L
H
L
H
H
H
L
H
H
L
H
L
L
H
H
L
L
H
L
H
H
L
H
H
L
H
L
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Arithmetic Logic Unit/
Function Generator
MC10H181
The MC10H181 is a high-speed arithmetic logic unit capable of performing
16 logic operations and 16 arithmetic operations on two four-bit words. Full
internal carry is incorporated for ripple through operation.
Arithmetic logic operations are selected by applying the appropriate binary
word to the select inputs (SO through S3) as indicated in the tables of
arithmeticllogic functions. Group carry propagate (PG) and carry generate (GG)
are provided to allow fast operations on very long words using a second order
look-ahead. The internal carry is enabled by applying a low level voltage to the
mode control input (M).
When used with the MC10H179, full-carry look-ahead, as a second order
look-ahead block, the MC10H181 provides high-speed arithmetic operations
on very long words.
This 10H part is a functionaVpinout duplication of the standard MECL 10K
family part with 100% improvement in propagation delay and no increase in
power supply current.
~
-•
• Improved Noise Margin, 150 mV (Over Operating Voltage and
Temperature Range)
• MECL 10K - Compatible
• Voltage Compensated
LSUFFIX
CERAMIC PACKAGE
CASE75~2
PSUFFIX
PLASTIC PACKAGE
CASE 724-03
FNSUFFIX
PLCC
CASE77~2
DIP
PIN ASSIGNMENT
MAXIMUM RATINGS
Symbol
Rating
Unit
VCC1
Power Supply (Vee = 0)
VEE
-8.0 to 0
Vdc
FO
M
Input Voltage (VCC = 0)
VI
OtoVEE
Vdc
Output Current- Continuous
-Surge
lout
50
100
mA
Operating Temperature Range
TA
oto +75
Tstg
-55 to +150
-55 to +165
Characteristic
Storage Temperature Range- Plastic
-Ceramic
F1
CN
GG
AO
°c
CN+4
80
°e
°e
F3
81
F2
A1
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse airflow greater than 500 Ifpm is maintained. Outputs are terminated through
a 5(k)hm resistor to -2.0 volts.
FUNCTION SELECT TABLE
LOGIC DIAGRAM
13----...,
Function Select
S3 S2 S1 SO
L
21
21J
18
19
H
16
11
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
10
22
23
L
L
H
H
H
H
H
H
L
H
H
H
L
H
L
H
logic Functions
M is High C = D.C.
F
Arithmetic Operation
M is Low Cn is low
F
F=A
F=A+!J
F=A+B
F= logical '1"
F=A.!J
F=!J
F=A0B
F=A+B
F=A.B
F=A
F=Aplus(A.1l)
F=Aplus(A.B)
F=Atimes2
F=(A+B)plusO
F=(A+B)plus(A.1l)
F=AplusB
F=Aplus(A+B)
F=AEIlB
F=B
F=A+B
F = Logical "Ow
F=A.!J
F=A.B
F=A
F = A minus B minus 1
2-74
PG
S1
83
A2
A3
S2
B2
SO
VEE
S3
Pin aSSignment is for Dual-ir>-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
F=(A+B)plusO
F=(A+B)plus(A.B)
F=Aplus(A+B)
F == minus 1 (two's complement)
F= (A.B) minus 1
F=(A.B)minus1
F=Aminus1
9196
© Motorola, Inc. 1996
VCC2
REV 6
®
MOTOROLA
MC10H181
LOGIC DIAGRAM
8313
8'15
8117
5014
80'0
~.£):>t
AO'l
Bl19
~.£):>t
Alla
B211
~.£):>t
A216
~
,.--
L./
~
[gD
,.--,
~
II
"
gp
,...---.
.~
~
~.£):>t
A310
Ln.-
,FO
~
~
3Fl
7F,
,~
~;:}
839
./
rrr=>
~
"
,
._./
-
~
:::If>-
6F3
,
./
~~
~
M'3
vee1:: Pln1
VCC2:: Pln24
VEE:: Pin 12
MECLData
DLl22-Rev6
2-75
MOTOROLA
MC10H181
ELECTRICAL CHARACTERISTICS (VEE
=-5.2 V ±5.0%) (See Note)
0°
Characteristic
Power Supply Current
Input Current High
Pin 22
Pins 14,23
Pins 13,15,17
Pins 10,16,18,21
Pins 9,11,19,20
Input Current Low
Pins 9-11,19-22
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
+25°
+75 0
Symbol
Min
Max
Min
Max
Min
Max
Unit
IE
-
159
-
145
-
159
rnA
-
720
405
515
475
465
.:....
-
450
255
320
300
275
-
450
255
320
300
275
linH
-,
-
linL
0.5
VOH
VOL
VIH
VIL
-1.02
-1.95
-1.17
1.95
-
-
-0.98
1.95
-1.13
-1.95
ItA
0.3
0.5
-0.84
-1.63
-0.84
1.48
ItA
-0.81
-1.63
-0.81
1.48
-0.735
1.60
-0.735
1.45
-0.92
-1.95
-1.07
1.95
Vdc
Vdc
Vdc
Vdc
NOTE:
Each MECL 1OH series circuit has been designed to meet the de specifications shown in the test table, aflerthermal equilibrium has been established. The circuit is in a test socket
or mounted on a printed ckcuit board and transverse air flow greater than 500 Ifpm Is maintained. Outputs are tenninated through a SO--ohm resistor to -2.0 volls.
AC PARAMETERS
AC Switching Characteristics
O°C
Characteristic
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Input
Output
t++,t-t+.tt++,t+
Cn
Cn
Cn
Cn
Cn
Al
Al
Al
Al
Al
Al
Al
Al
Al
Bl
Bl
Bl
Bl
Bl
Bl
Bl
Sl
Cn+4
Cn+4
Fl
Fl
Fl
Fl
Fl
Fl
AO,Al,A2,A3
AO,Al,A2,A3
AD
PG
PG
GG
GG
Cn+4
Cn+4
Fl
F
SO,S3
SO,S3
AO,A2,A3,C n
AO,A2,A3,C n
AO,A2,A3,Cn
AO,A2,A3,C n
S3,Cn
S3,Cn
SO,Al
SO,Al
S3,Cn
S3,C n
S3,Cn
S3,Cn
t-+,t--
t+,t-
Rise lime, Fal/lime
Propagation Delay
t++,t+
t-+,t-t+,t-
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise Time, Fall Time
Propagation Delay
Rise Time, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Propagation Delay
Rise lime, Fall lime
Conditions t
Symbol
t++,t--
t+,tt++,t--
t+.tt+-,t-+
t+,tt++.t +
t+,t-
t++.t
t+,tt++,t-t+,tt+-,t-+
t+,tt++.t+
I+,tt+ ,I +
t+,tt-+,t+t+,tt+-,t-+
t+,tt+-,t-+
t+,t-
M
M
Sl
Sl
Sl
Sl
Sl
Sl
Sl
Sl
PG
PG
GG
GG
Cn+4
Cn+4
Fl
Fl
Fl
Fl
+25°C
+75°C
Min
Max
Min
Max
Min
Max
Unit
0.7
0.6
2.0
2.0
0.7
0.6
2.0
2.0
0.7
0.7
2.2
2.2
ns
ns
ns
1.0
0.7
3.0
2.2
1.0
0.7
3.0
2.2
1.2
0.7
3.3
2.4
1.5
0.7
1.5
0.9
1.5
0.7
1.5
0.5
2.0
0.7
1.5
0.7
1.5
0.7
2.0
0.5
1.5
0.8
1.5
0.7
1.5
0.7
1.5
0.7
1.3
0.5
3.7
2.0
3.7
2.4
3.7
2.2
3.6
2.0
4.5
2.3
3.8
2.2
3.7
2.2
4.0
2.0
4.2
2.3
4.5
2.0
4.0
2.0
4.1
2.2
4.5
3.2
1.5
0.7
1.5
0.9
1.5
0.7
1.5
0.5
2.0
0.7
1.5
0.7
1.5
0.7
2.0
0.5
1.5
0.8
1.5
0.7
1.5
0.7
1.5
0.7
1.3
0.5
3.7
2.0
3.7
2.4
3.7
2.2
3.6
2.0
4.5
2.3
3.8
2.2
3.7
2.2
4.0
2.2
4.2
2.3
4.5
2.0
4.0
2.2
4.1
2.2
4.5
3.2
1.6
0.7
1.6
0.9
1.6
0.7
1.6
0.5
2.1
0.7
1.6
0.7
1.6
0.7
2.1
0.5
1.6
0.8
1.6
0.7
1.6
0.7
1.6
0.7
1.4
0.5
4.0
2.2
4.0
2.6
3.9
2.4
3.9
2.2
4.8
2.5
4.0
2.4
4.0
2.4
4.3
2.2
4.5
2.5
4.8
2.2
4.3
2.4
4.4
2.4
4.8
3.4
ns
Al,Bl
Al,Bl
AS,B3
AS,B3
A3,B3
A3,B3
A3,S3
A3,S3
PG
PG
Cn+4
Cn+4
GG
GG
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t logiC high lavel (+1.11 Vdc) applied to pins listed. All other
input pins are left floating or tied to +0.31 Vdc.
VCCl VCC2 +2.0 Vdc, VEE -3.2 Vdc
=
MOTOROLA
=
=
2-76
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Master-Slave Flip-Flop
with Reset
MC10H186
The MC1 OH186 is a hex D type flip-flop with common reset and clock lines.
This MECL 10H part is a functional/pinout duplication of the standard MECL
10K family part, with 100% improvement in clock toggle frequency and
propagation delay and no increase in power-supply current.
,.
-•
• Propagation Delay, 1.7 ns Typical
• Power Dissipation, 460 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K-Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
VEE
-8.0 to 0
Vdc
Input Voltage (VCC = 0)
VI
OtoVEE
Vdc
lout
50
100
mA
TA
Oto +75
°c
Tstg
-55 to +150
-55 to +165
°c
°c
Output Current - Continuous
-Surge
Operating Temperature Range
Storage Temperature Range -
Plastic
-Ceramic
25°
Characteristic
Symbol
Power Supply Current
IE
Input Current High
Pins 5.6.7,10,11,12
Pin 9
Pin 1
linH
75°
Min
Min
Max
Min
Max
Max
Unit
-
121
-
110
-
121
mA
-
430
670
1250
-
265
420
765
-
265
420
765
linL
0.5
-
0.5
-
0.3
-
JlA
VOH
-1.02
...(J.84
...(J.98
...(J.81
...(J.92
...(J.735
Vdc
Low Output Voltage
VOL
-1.95
-1.63
-1.95
-1.63
-1.95
-1.60
Vdc
High Input Voltage
VIH
-1.17
...(J.84
-1.13
...(J.81
-1.07
...(J.735
Vdc
Low Input Voltage
VIL
-1.95
-1.48
-1.95
-1.48
-1.95
-1.45
Vdc
tpd
0.7
3.0
0.7
3.0
0.7
3.0
ns
R
C
D
On+1
L
L
X
On
L
L
H'
H'
L
L
H
H
H
L
X
L
DIP
PIN ASSIGNMENT
RESET
AC PARAMETERS
Propagation Delay
FN SUFFIX
PLCC
CASE 775...(J2
* A clock H is a clock transition from
a low to a high state.
IlA
High Output Voltage
Input Current Low
PSUFFIX
PLASTIC PACKAGE
CASE 648...(J8
CLOCKED TRUTH TABLE
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V ±5%) (See Note)
0°
LSUFFIX
CERAMIC PACKAGE
CASE 62Q...l0
VCC
00
05
01
04
Set-upTime
tset
1.5
1.0
1.0
-
ns
1.0
-
1.5
thold
-
1.5
Hold lime
Rise Time
tr
0.7
2.6
0.7
2.6
0.7
2.6
ns
Q2
03
FaUlime
tf
0.7
2.6
0.7
2.6
0.7
2.6
ns
00
05
ftoa
250
250
3.0
-
250
trr
-
-
01
04
Toggle Frequency
Reset Recovery lime
(tl-9+)
3.0
3.0
ns
MHz
ns
03
02
NOTE:
Each MECL 10H series circuit has been designed to meet the de specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated
through a 5D----ID
•
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02
On
MR
TCLKlCLK
Qn+1
l
H
l
l
H
Z
l
H
l
ClK
R
X
I
I
__ -.J
Z
X
=lOW to HIGH Transition
ClK
ClK
TClK
Pinout: 28-Lead PLCC (Top View)
01
25
*
Z
02 VCCT 03
24
1. When using MECl inputs, TClK must be tied to ground (OV).
2. When using only one MECl input, the unused MECl input must be tied
to Vee, and TClK must be tied to ground (OV).
3. When using TClK, both MECl inputs must be tied to VEE (-S.2V).
23
22
04
05 VCCE
21
20
10
00 Qij VEE 01 Of Q2
9/96
© Motorola, Inc. 1996
2-108
REV 1
®
ta
14
VCCE
13
Q3
11
Q2
MOTOROLA
MC10H604 MC100H604
DC CHARACTERISTICS: VEE = VEE (Min) to VEE(Max); VCCE = GND; VCCT = 5.0V + 10%
DOC
Parameter
Symbol
lEE
ECL Power Supply Current
ICCH
ICCL
TTL Power Supply Current
Min
25°C
Max
10H
100H
Min
85°C
Max
Min
Max
Unit
130
130
130
140
130
150
mA
35
45
35
45
35
45
rnA
Max
Unit
145
IlA
IlA
Condition
10H ECl DC CHARACTERISTICS: VCCT = +5.0 V ± 10%; VEE = -5.20 V ±5%
DOC
Parameter
Symbol
Min
25°C
Max
Min
85°C
Max
225
Min
145
Condition
IIH
IlL
Input HIGH Current
Input LOW Current
0.5
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
-1170
-1950
-840
-1480
-1130
-1950
--810
-1480
-1060
-1950
-720
-1480
mV
VBB
Output Bias Voltage
-1400
-1290
-1370
-1270
-1330
-1210
mV
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
-1020
-1950
-840
-1630
-980
-1950
--810
-1630
-910
-1950
-720
-1595
mV
50 Q to -2.0 V
Max
Unit
Condition
145
IlA
0.5
0.5
100H ECl DC CHARACTERISTICS: VCCT = 5.0 V -+ 10%; VEE = -4.2 V to -5.5 V
DOC
Symbol
Min
Parameter
25°C
Min
Max
85°C
Max
225
Min
IIH
IlL
Input HIGH Current
Input LOW Current
145
0.5
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
-1165
-1810
--880
-1475
-1165
-1810
--880
-1475
-1165
-1810
--880
-1475
mV
VBB
Output Bias Voltage
-1400
-1280
-1400
-1280
-1400
-1280
mV
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
-1025
-1810
--880
-1620
-1025
-1810
--880
-1620
-1025
-1810
-880
-1620
mV
0.5
0.5
!lA
50Qto-2.0V
TTL DC CHARACTERISTICS: VCCT= 5.0 V± 10%; VEE =-5.2 V±5% (10H version); VEE =-4.2 V to-5.5 V (100H version)
O°C
Symbol
Min
Parameter
25°C
Max
85°C
Max
Unit
0.8
0.8
V
V
20
100
20
100
!lA
VIN=2.7V
VIN=7.0V
-0.6
-0.6
-0.6
rnA
VIN=0.5V
-1.2
-1.2
-1.2
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
0.8
IIH
Input HIGH Current
20
100
IlL
Input LOW Current
VIK
Input Clamp Voltage
Min
Max
2.0
2.0
Min
2.0
Condition
liN =-18 rnA
AC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = -5.2 V -+ 5% (10H version); VEE = -4.2 V to -5.5 V (100H version)
DOC
Symbol
Parameter
Min
tpLH
tpHL
Propagation Delay CLKtoQ
TCLKtoQ
to Output
MRtoQ
1.5
2.0
1.5
Typ
25°C
Max
Min
3.5
4.0
4.0
1.5
2.0
1.5
Typ
85°C
Max
Min
3.5
4.0
4.0
1.5
2.0
1.5
Typ
Max
Unit
3.5
4.0
4.0
ns
CL=50pF
Condition
ts
Setup Time
1.5
0.5
1.5
0.5
1.5
0.5
ns
CL=50pF
tH
Hold Time
1.5
0.5
1.5
0.5
1.5
0.5
ns
CL=50pF
tpw
Minimum Pulse Width
CLK, MR
ns
CL=50pF
VPP
Minimum Input Swing
tr
tf
Rise/Fall Times
MECLData
DL122-Rev6
1.0
1.0
1.0
mV
150
0.3
1.0
2.0
0.3
2-109
1.0
2.0
0.3
1.0
2.0
ns
20%-80%
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Registered Hex ECL/TTL
Translator
MC10H605
MC100H605
The MC1 0/1 00H605 is a 6-bit, registered, dual supply ECl to TTL
translator. The device features differential ECl inputs for both data and
clock. The TTL outputs feature balanced 24mA sink/source capabilities for
driving transmission lines.
With its differential ECl inputs and TTL outputs the H605 device is ideally
suited for the receive function of a HPPI bus type board-to-board intei1ace
application. The on chip registers simplify the task of synchronizing the data
between the two boards.
A VBB reference voltage is supplied for use with single-ended data or
clock. For single-ended applications the VBB output should be connected to
the "bar" inputs (Dn or ClK) and bypassed to ground via a 0.01!!F capacitor.
To minimize the skew of the device differential clocks should be used.
The ECl level Master Reset pin is asynchronous and common to all
flip-flops. A "HIGH" on the Master Reset forces the Q outputs "lOW".
The device is available in either ECl standard: the 10H device is
compatible with MECl 10HTM logic levels while the 100H device is
compatible with 100K logic levels.
.
VCCE
VCCT
GND
VEE
- --,
1 OF 6 BITS .
I
TRUTH TABLE
an
a
I
I
R
On
MR
TCLKlClK
Qn+1
l
H
X
l
l
H
Z
Z
X
l
H
l
Z = lOW to HIGH Transition
I
ClK
FUNCTION
True ECl Data Inputs
Inverted ECl Data Inputs
Differential ECl Clock Input
ECl Master Reset Input
TIL Outputs
EClVCC
TIL Vee
TIL Ground
EClVEE
00--05
- - -'- - -
Dn--t-----i
Dn - - + - - - - ( : ) 1
PIN
ClK,ClK
MR
lOGIC SYMBOL
I
PIN NAMES
00--05
00--05
• Differential ECl Data and Clock Inputs
• 24mA Sink, 24mA Source TTL Outputs
• Dual Power Supply
• Multiple Power and Ground Pins to Minimize Noise
• 2.0ns Part-to-Part Skew
r ---
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02
Pinout: 28-Lead PLCC(Top View)
I
I
Q3
____ -.J
25
ClK
ClK
vcc;r Q4 GND QS VCCT MR
24
23
22
21
20
19
QO
GNO
MR
10
1-------
11
VBB .....
DO 00 VEE 01 ill 02
D2
MECl 10H is a trademark of Motorola, Inc.
9/96
© Motorola, Inc. 1996
2-110
REV3
®
MOTOROLA
MC10H605 MC100H605
10H ECl DC CHARACTERISTICS (VCCT = +S.OV ±S%; VEE = -S.20V ±S%)
O'C
Symbol
Characteristic
lEE
Supply Current
Min
25'C
Typ
Max
63
75
Min
85'C
Typ
Max
63
75
225
Min
Typ
Max
Unit
61
75
rnA
IIH
Input High Current
IlL
Input Low Current
VIH
Input High Voltage
-1170
-B40
-1130
-810
-1060
-720
mV
VIL
Input Low Voltage
-1950
-14BO
-1950
-14BO
-1950
-1480
mV
VBB
Output Bias Voltage
-1400
-1280
-1370
-1270
-1330
-1210
mV
VDiff
Input Differential Voltage
Vmax
CMRR
Input Common
Reject Range
Mode
Vmin
CMRR
Input Common
Reject Range
Mode
0.5
145
0.5
150
150
mV
0
0
-2800
-3000
-3300
J.lA
J.lA
150
0
-2800
-3000
-3300
145
0.5
Condition
-2800
-3000
-3300
mV
mV
VEE =-4.94
VEE =-5.20
VEE =-5.46
Condition
100H ECl DC CHARACTERISTICS (Vccr = +S.OV ±S%; VEE = -4.SV ±O.3V)
O'C
Characteristic
Symbol
Min
85'C
25'C
Typ
Max
65
75
Min
Typ
Max
65
75
Min
Typ
Max
Unit
70
85
rnA
145
J.lA
J.lA
-1165
-880
mV
-1810
-1475
mV
-1200
mV
0
mV
lEE
Supply Current
IIH
Input High Current
IlL
Input Low Current
VIH
Input High Voltage
-1165
-8BO
-1165
-880
VIL
Input Low Voltage
-1810
-1475
-1810
-1475
VBB
Output Bias Voltage
-1400
-1280
..,1400
-1280
-1400
225
0.5
VDiff
Input Differential Voltage
Vmax
CMRR
Input Common
Reject Range
Mode
Vmin
CMRR
Input Common
Reject Range
Mode
145
0.5
150
150
0
-2000
-2200
-2400
0.5
0
-2000
-2200
-2400
mV
150
-2000
-2200
-2400
mV
VEE =-4.20
VEE =-4.50
VEE =-4.80
• NOTE: DO NOT short the ECL inputs to the TIL VCC.
MECLData
DL122- Rev 6
2-111
MOTOROLA
MC10H605 MC100H605
TTL DC CHARACTERISTICS (VCCT
=+S.OV ±S%; VEE =-S.2V ±S% (10H); VEE =-4.SV ±O.3V (100H))
O'C
Symbol
Max
Supply Current
65
ICCH
Supply Current
65
VOL
Output low Voltage
VOH
Output High Voltage
2.5
lOS
Output Short Circuit
Current
100
AC TEST LIMITS (VCCT
Min
25'C
Typ
ICCl
Characteristic
Min
Max
Typ
Max
Unit
Condition
75
65
75
65
75
rnA
Outputs low
75
65
75
65
75
rnA
Outputs High
0.5
mV
IOl=24mA
mV
IOH=24mA
225
rnA
VOUT=OV
Max
Unit
Condition
ns
P.S.
Across
and Temp
Cl=50pF
ns
Across
P.S.
and Temp
Cl= 50pF
ns
Across
P.S.
and Temp
Cl=50pF
ns
Cl=50pF
0.5
2.5
225
tplH
tpHl
tpHl
tSKEW
Min
0.5
2.5
100
225
100
=+S.OV ±S%; VEE =-S.2V ±S% (10H); VEE =-4.SV ±O.3V (100H»
25'C
O'C
Symbol
85'C
Typ
Characteristic
Min
Typ
Max
Min
Typ
85'C
Max
Min
Typ
Propagation Delay
ClK to 0 (Dill)
ClKtoO(SE)
4.5
4.3
5.3
5.3
6.5
6.7
4.5
4.3
5.4
5.4
6.5
6.7
4.5
4.3
5.6
5.6
6.5
6.7
Propagation Delay
ClK to 0 (Dill)
ClKtoO(SE)
4.0
3.8
5.0
5.0
6.0
6.2
4.0
3.8
5.1
5.1
6.0
6.2
4.0
3.8
5.5
5.5
6.0
6.2
Propagation Delay
MRtoO
2.5
4.9
7.0
2.5
5.2
7.0
3.0
5.8
7.5
1.0
0.3
2.0
0.7
1.0
0.3
2.0
0.7
1.0
0.3
2.0
0.7
Device Skew
Part-to-Part (Dill)
Within-Device
ts
Setup Time
1.5
1.5
1.5
ns
tH
Hold Time
1.5
1.5
1.5
ns
tpw
Minimum Pulse Width
ClK
1.0
1.0
1.0
ns
tpw
Minimum Pulse Width
MR
1.0
1.0
1.0
ns
Vpp
Minimum Input Swing
150
150
150
mV
Peak-toPeak
tr
Rise Time
0.7
1.0
1.5
0.7
1.0
1.5
0.7
1.0
1.5
ns
tV to 2V
tf
Fall Time
0.5
0.7
1.2
0.5
0.7
1.2
0.5
0.7
1.2
ns
tVt02V
tRR
Reset/Recovery Time
2.5
MOTOROLA
2.5
2-112
2.5
ns
MEClData
Dl122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Registered Hex TTL/PECL
Translator
MC10H606
MC100H606
The MC10/100H606 is a 6-bit, registered, single supply TTL to PECl
translator. The device features differential PECl outputs as well as a choice
between either a differential PECl clock input or a TTL clock input. The
asynchronous master reset control is a PECl level input.
With its differential PECl outputs and TTL inputs the H606 device is
ideally suited for the transmit function of a HPPI bus type board-ta-board
interface application. The on chip registers simplify the task of synchronizing
the data between the two boards.
The device is available in either ECl standard: the MEClTM 10H device is
compatible with MECl 10KH logic levels, with a Vec of +5 volts; while the
100H device is compatible with 100K logic levels, with a VCC of +5 volts.
• Differential 50n ECl Outputs
• Choice Between Differential PECl or TTL Clock Input
• Single Power Supply
• Multiple Power and Ground Pins to Minimize Noise
PIN NAMES
lOGIC SYMBOL
1---------,
I
1 OF6 BITS
I
Dn--t--f :>----iD
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02
Q
PIN
FUNCTION
00-05
ClK,ClK
TClK
MR
00-05
00-05
VCCE
VCCT
GND
TTL Dala Inputs
Differential PECl Clock Input
TTL Clock Input
PECl Master Reset Input
True PECl Outputs
Inverted PECl Outputs
PECl VCC (+5.0V)
TTL VCC (+5.0V)
TTUPECl Ground
TRUTH TABLE
ClK
R
I
I
--~
On
MR
TClKlClK
Qn+l
l
H
X
l
l
H
Z
Z
X
l
H
l
Z = lOW to HIGH Transition
ClK
ClK
TClK
Pinout: 28-lead PlCC (Top View)
01
25
02 Vccr 03
24
23
22
D4
05 VCCE
21
20
19
MR
VBB ........- -
*
1. When using PECl inputs, TClK must be tied to ground (OV).
14
VCCE
2. When using only one PECl input, the unused PECl input must be tied
13
Q3
to VBB, and TClK must be tied to ground (OV).
3. When using TClK, both PECl inputs must be tied to ground (OV).
10
co
00 GNO 01 Q1 Q2
11
Q2
MECl 10H is a trademark of Motorola, Inc.
9/96
© Motorola, Inc. 1996
2-113
REVI
®
MOTOROLA
MC10H606 MC100H606
DC CHARACTERISTICS (VCCT
=VCCE =5.0V ±5%)
TA=O"C
Symbol
Characteristic
Min
TA = + 25°C
Typ
Max
18
30
Min
TA=+85°C
Typ
Max
18
30
ICCTL
Supply Current
ICCTH
Supply Current
13
25
13
25
IGND
Supply Current
75
90
75
90
Min
Typ
Max
Unit
Condition
18
30
rnA
Outputs LOW
13
25
rnA
Outputs HIGH
75
95
rnA
TTL DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)
TA=O°C
Symbol
VIH
Characteristic
Input HIGH Voltage
Min
Max
2.0
TA = 25°C
Min
Max
2.0
TA = 85°C
Min
Max
2.0
Unit
Condition
V
V
VIL
Input LOW Voltage
0.8
0.8
0.8
VIK
Input Clamp Voltage
-1.2
-1.2
-1.2
V
IIN=-18mA
IIH
Input HIGH Current
20
100
20
100
20
100
V
VIN=2.7V
VIN=7.0V
IlL
Input LOW Current
-{l.6
-{l.6
-{l.6
rnA
VIN=0.5V
Max
Unit
Condition
145
IlA
10H PECl DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)
TA = O°C
Symbol
IINH
Characteristic
Min
Input HIGH Current
Max
TA = 25°C
Min
255
Max
TA = 85°C
Min
145
IINL
Input LOW Current
0.5
IlA
VIH
Input HIGH Voltage (Note 1.)
3830
4160
3870
4190
3930
4280
mV
VCCT=5.0V
VIL
Input LOW Voltage (Note 1.)
3050
3520
3050
3520
3050
3555
mV
VCCT= 5.0V
VOH
Output HIGH Voltage (Note 1.)
3980
4160
4020
4190
4080
4270
mV
VCCT=5.0V
VOL
Output LOW Voltage (Note 1.)
3050
3370
3050
3370
3050
3400
mV
VCCT=5.0V
VBB
Output Bias Voltage (Note 1.)
3600
3710
3630
3730
3670
3790
mV
VCCT=5.0V
Max
Unit
Condition
145
IlA
0.5
0.5
1. PECL VIL. VIH. VOL. VOH VBB are given for VCCT = VCCE = 5.0V and will vary 1:1 with the power supply.
100H PECl DC CHARACTERISTICS (VCCT
=VCCE =5.0V ±5%)
TA=O°C
Symbol
Characteristic
IINH
Input HIGH Current
Min
Max
TA = 25°C
Min
255
Max
TA = 85°C
Min
145
IINL
Input LOW Current
0.5
IlA
VIH
Input HIGH Voltage (Note 1.)
3835
4120
3835
4120
3835
4120
mV
VCCT=5.0V
VIL
Input LOW Voltage (Note 1.)
3190
3525
3190
3525
3190
3525
mV
VCCT= 5.0V
VOH
Output HIGH Voltage (Note 1.)
3975
4120
3975
4120
3975
4120
mV
VCCT=5.0V
VOL
Output LOW Voltage (Note 1.)
3190
3380
3190
3380
3190
3380
mV
VCCT=5.0V
VBB
Output Bias Voltage (Note 1.)
3600
3720
3600
3720
3600
3720
mV
VCCT= 5.0V
0.5
0.5
1. PECL VIL. VIH. VOL. VOH VBB are given for VCCT = VCCE = 5.0V and will vary 1:1 with the power supply.
MOTOROLA
2-114
MECLData
DL122-Rev6
MC10H606 MC100H606
AC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)
TA=O'C
Symbol
Characteristic
Min
tpD
Propagation Delay
TCLK++
tpD
Typ
TA=+BS'C
TA=+2S'C
Max
Min
Typ
Max
Min
Max
Unit
1.75
3.75
1.75
3.00
3.75
1.75
3.75
ns
Cl= 50pF
Propagation Delay
TCLK-t-
1.75
3.75
1.75
3.00
3.75
1.75
3.75
ns
CL=50pF
tpD
Propagation Delay
CLK++
1.50
3.50
1.50
2.50
3.50
1.50
3.50
ns
Cl=50pF
tpD
Propagation Delay
ClK+-
1.50
3.50
1.50
2.50
3.50
1.50
3.50
ns
Cl=50pF
tpD
Propagation Delay
MR-t-
1.50
3.50
1.50
2.50
3.50
1.75
3.75
ns
CL=50pF
tSKEW
Device Skew
Part-to-Part
Within Device
ns
CL=50pF
1.0
0.3
2.0
0.5
CL=50pF
2.0
0.5
Typ
Condition
2.0
0.5
ts
Setup TIme
1.5
0.5
1.5
0.5
1.5
0.5
ns
tH
HoidTime
1.5
0.5
1.5
0.5
1.5
0.5
ns
CL=50pF
tpw
Minimum Pulse Width
ClK
1.5
1.5
1.0
1.5
ns
Cl=50pF
tpw
Minimum Pulse Width
MR
1.5
1.5
1.5
ns
Cl=50pF
Ir
Rise TIme
2.0
1.0
2.0
2.0
ns
CL=50pF
If
Fall TIme
2.0
1.0
2.0
2.0
ns
CL=50pF
tRES/REC
Reset/Recovery TIme
ns
Cl=50pF
MECLData
DL122-Rev6
2.5
2.0
2.5
2-115
2.0
2.5
2.0
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Registered Hex PECL/TTL
Translator
MC10H607
MC100H607
The MC10H/100H607 is a 6-bit, registered PECl to TTL translator.
The device features differential PECl inputs for both data and clock. The
TTL outputs feature 48mA sink, 24mA source drive capability for driving
high fanout loads or transmission lines. The asynchronous master reset
control is an ECl level input.
With its differential PECl inputs and TTL outputs the H607 device is
ideally suited for the receive function of a HPPI bus type board-ta-board
interface application. The on chip registers simplify the task of
synchronizing the data between the two boards.
FNSUFFIX
PLASTIC PACKAGE
CASE 77fHl2
The device is available in either ECl standard: the 10H device is
compatible with MECl 10HTM logic levels, with a VCC of +5.0 volts, while
the 100H device is compatible with 1OOK logic levels, with a VCC of +5.0
volts.
• Differential ECl Data and Clock Inputs
• 48mA Sink, 15mA Source TTL Outputs
• Single Power Supply
• Multiple Power and Ground Pins to Minimize Noise
Pinout: 28-Lead PLCC (Top View)
03
VCCT
04
TGNO
05
VCCT
MR
02
Os
01
05
00
D4
TGNO
04
ClK
VCCE
ClK
D3
VBB
03
00
Do
EGNO
01
D1
02
52
MECL 10H is a trademark of Motorola, Inc.
9/96
© Motoroia, inc.
1996
2-116
REV 2
®
MOTOROLA
MC10H607 MC100H607
,._.- -
lOGIC DIAGRAM
---
I
- ---.
- --
10F6BITS
I
I
I
I
I
Dn--t-----;-.....
Dn - - + - - - - G I /
'>--l--- an
a
ClK
I
R
I
L __
--------~
ClK
MR
VSS .....- -
PIN NAMES
TRUTH TABLE
Pin
Function
On
MR
TClKlClK
DO-!§
DO-DS
ClK,ClK
MR
00- 0 5
True PECl Data Inputs
Inverted PECl Data Inputs
Differential PECl Clock Input
PECl Master Reset Input
TTL Outputs
l
H
l
l
H
Z
Z
VCCE
VCCT
TGND
EGND
PEClVCC
TTlVCC
TTL Ground
PEClGround
X
Qn
+1
l
H
l
X
Z = lOW to HIGH Transition
DC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)
TA = + 25'C
TA=O'C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
TA = + 85'C
Max
Min
Typ
Max
Unit
70
65
85
80
70
70.
85
85
70
75
85
95
ICCl
TTL Supply Current
100
120
100
120
100
120
rnA
ICCH
TTL Supply Current
100
120
100
120
100
120
rnA
MEClData
Dl122-Rev6
Condition
rnA
ECl Power Supply Current
10H
100H
lEE
2-117
MOTOROLA
MC10H607 MC100H607
10H PECl DC CHARACTERISTICS (VCCT
=VCCE =5.0V ±5%)
TA = 25°C
TA=O°C
Symbol
Characteristic
IINH
Input HIGH Current
Min
Max
Min
255
TA=85°C
Min
145
Max
Unit
145
I1A
Condition
IINl
Input lOW Current
0.5
I1A
VIH
Input HIGH Voltage
3B30
4160
3B70
4190
3930
42BO
mV
VCCT=5.0V
Vil
Input lOW Voltage
3050
3520
3050
3520
3050
3555
mV
VCCT= 5.0V
Output Bias Voltage
3600
3710
3630 3730
3670
3790
VBB
NOTE: PECl Vil. VIH. Val. VOH. VBB are given for VCCT = VCCE = 5.0V and Will vary 1:1 with power supply.
mV
VCCT=5.0V
Max
Unit
Condition
145
IlA
0.5
100H PECl DC CHARACTERISTICS (VCCT
0.5
=VCCE =5.0V +5%)
TA = 25°C
TA = O°C
Symbol
[~]
Max
Characteristic
IIH
Input HIGH Current
Min
Max
Min
Max
255
TA=85°C
Min
145
III
Input lOW Current
0.5
IlA
VIH
Input HIGH Voltage
3B35
4120
0.5
3835
4120
0.5
3835
4120
mV
VCCT=5.0V
Vil
Input lOW Voltage
3190
3525
3190
3525
3190
3525
mV
VCCT= 5.0V
Output Bias Voltage
3600
3720
3600 3720
3600
3720
VBB
NOTE: PECl Vil. VIH. Val. VOH. VBB are given for VCCT = VCCE = 5.0V and Will vary 1:1 with power supply.
mV
VCCT=5.0V
10Hll00H TTL DC CHARACTERISTICS (Vccr = VCCE = 5.0V ±5%)
TA=O°C
Characteristic
Symbol
VOH
Min
Max
2.5
2.0
Output HIGH Voltage
TA=25°C
Min
Max
2.5
2.0
TA = 85°C
Min
Max
2.5
2.0
Unit
Condition
V
IOH =-15mA
IOH=-24mA
Output lOW Voltage
0.55
0.55
V
0.55
IOl=4BmA
Val
NOTE: DC levels such as VOH. Val. etc .• are standard for PECl and FAST deVices. with the exceptions of: IOl = 48mA at 0.5VOl;
and IOH = 24mA at 2.0VOH.
AC CHARACTERISTICS (VCCT = VCCE = 5.0V ±5%)
TA =+ 25°C
TA= + 85°C
Min
Max
Min
Max
Min
Max
Unit
ClKtoQ
5.5
4.6
7.7.
7.7
6.0
4.9
B.2
B.3
6.7
5.9
10.0
10.0
ns
Cl=50pF
MRtoQ
4.4
7.5
4.7
B.l
5.8
10.5
ns
Cl = 50pF
ClK.MR
1.0
TA=O°C
Symbol
Characteristic
Condition
tplH++
tpHH+-
Propagation Delay to Output
tpHl+-
Propagation Delay to Output
tpw
Minimum Pulse Width
tr
Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
0.B-2.0V
tf
Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
0.B-2.0V
ts
Setup Time
1.5
tH
Hold Time
1.5
1.5
1.5
ns
Vpp
Minimum Input Swing
200
200
200
mV
1.0
1.5
1.0
1.5
ns
ns
1. Numbers are for both ++ and - - delay MR to Q.
MOTOROLA
2-11B
MEClData
Dl122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
68030/040
PECL-TTL Clock Driver
MC10H640
MC100H640
The MC1 OH/1 00H640 generates the necessary clocks for the 68030,
68040 and similar microprocessors. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of part-ta-part
skew, within-part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced to
+S.OV) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to SOMHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H640 also
uses differential PECL internally to achieve its superior skew
characteristic.
The H640 includes divide-by-two and divide-by-four stages, both to
achieve the necessary duty cycle skew and to generate MPU clocks as
required. A typicalSOMHz processor application would use an input clock
running at 100MHz, thus obtaining output clocks at SOMHz and 2SMHz
(see Logic Symbol).
The 10H version is compatible with MECL 10HTM ECL logiC levels,
while the 100H version is compatible with 100K levels (referenced
to +S.OV).
68030/040
PECL-TTL CLOCK
DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-
w
2!
I
i--==:
!;;:
'"
w
Z
o
25
50
75
85
25
LOAD (pF)
11
---=
:r
w
10
~
::>
a.
w
~
17
~
5.125VCC
5VCC
4.875VCC
3: 10
w
~
a.
w
::>
f------1p..?-~.="""I- 4.875 VCC
5VCC
5.125VCC
>
~
'"zw
25
50
LOAD (pF)
75
85
25
50
LOAD (pF)
11
75
11
10pF
.,.s
SOpF
25pF
10
-
~
a.
::>
w
~0
10pF
I
~
3:
w
~
::>
a.
w
2!
!;;:
'"zw
a.
25°
85
-
r-10
25pF
r-25°
50°
TEMPERATURE (OC)
Figure 5. Temperature versus Positive Pulse Width
for 100H640 at 50 MHz and +5.0 V Vee
MECLData
DL122-Rev6
--+--;
Figure 4. Negative Pulse Width @ 50 MHz
Out and 25°e Ambient
Figure 3. Positive Pulse Width at
25°e Ambient at 50 MHz Out
w
85
:r
0
~
75
b
a.
3:
50
LOAD (pF)
.,.s
/
E
en
5.25VCC
11
.,.s
3:
5VCC
Figure 2. Negative Pulse Width @ 50 MHz
Out and 25°e Ambient
Figure 1. Positive Pulse Width at
25°e Ambient and 50 MHz Out
b
4.75VCC
50°
TEMPERATURE (OC)
Figure 6. Temperature versus Negative Pulse Width
for Me100H640 @ 50 MHz and +5.0 V Vee
2-123
MOTOROLA
MC10H640 MC100H640
6.2.--------,-----.----,--,
4.7SV
6.01-----+---+, SV ---+---1
5.25 V
:[
)
I-
S.81----l,r---+--T-~¥-+-----+---I
S.61--,...,--+""'7'~~--+-----+---I
S.4I---===-+-----+-----+---I
5·2I------:2"'"'S----5O-"-------I7S- - - - -85I
CLOAO(PF)
Figure 7. TP versus Load Typical at TA = 25°C
OT
RESET, Ii:
Rlrec
I
I
I
/ 4 - - - Rlpw
ao, Ql, Q2, Q3
00, Of
\'-___-'1
1
Q4, Q5 _ _ _ _ _ _ _ _--+-.J
Figure 8. MC10Hl100H640 Clock Phase and Reset Recovery Time After Reset Pulse
:
I
\
--~i~~/
_____L________
I
/
\
\
/
/
L
\~--~;--
~~---------~
AFTER POWER UP
OUTPUTS 04 & 05 WILL SYN WITH POSITIVE EDGES OF Din & 00 --> 03 & NEGATIVE EDGES OF 00 & 01
Figure 9. Output Timing Diagram
MOTOROLA
2-124
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Single Supply PECL-TTL
1:9 Clock Distribution Chip
MC10H641
MC100H641
The MC1 OH/1 00H641 is a single supply, low skew translating 1:9 clock
driver. Devices in the Motorola H600 translator series utilize the 28-lead
PlCC for optimal power pinning, signal flow through and electrical
performance.
SINGLE SUPPLY
PECL-TTL 1:9 CLOCK
DISTRIBUTION CHIP
The device features a 24mA TTL output stage, with AC performance
specified into a 50pF load capacitance. A latch is provided on-chip. When
lEN is lOW (or left open, in which case it is pulled lOW by the intemal
pulldown) the latch is transparent. A HIGH on the enable pin (EN) forces
all outputs lOW. Soth the lEN and EN pins are positive ECl inputs.
The VSS output is provided in case the user wants to drive the device
with a single-ended input. For single-ended use the VSS should be
connected to the D input and bypassed with a 0.01/!F capacitor.
The 10H version of the H641 is compatible with positive MECl10HTM
logic levels. The 100H version is compatible with positive 100K levels.
• PECl-TTl Version of Popular EClinPS E111
• low Skew
• Guaranteed Skew Spec
• latched Input
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
• Differential ECllnternal Design
• VSS Output for Single-Ended Use
• Single +5V Supply
• logic Enable
• Extra Power and Ground Supplies
• Separate ECl and TTL Supply Pins
Pinout: 28-Lead PLCC (Top View)
GT
06
VT
07
VT
08
GT
25
24
23
22
21
20
19
PIN NAMES
GT
VBB
Pins
Function
GT,VT
GE, VE
D,D
Vee
TTL GND, TTL VCC
05
D
VT
D
04
VE
Q0-08
VT
LEN
EN
lEN
03
GE
ECl GND, ECl VCC
Signal Input (Positive ECl)
Vee Reference Output
(Positive ECL)
Signal Outputs (TTL)
Enable Input (Positive ECl)
latch Enable Input
(Positive ECl)
EN
GT
5
GT
02
VT
01
9
10
11
VT
00
GT
MECl 10H is a trademark of Motorola, Inc.
11193
© Motorola, Inc. 1996
2-125
REV 3
®
MOTOROL.A
MC10H641 MC100H641
lOGIC DIAGRAM
TTL Outputs
00
01
02
03
04
05
LEN----I
EN-----'
06
07
06
DC CHARACTERISTICS (VT
=VE =5.0V ±5%)
TA = + 25°C
TA=O°C
Symbol
Min
Typ
Max
Unit
Power Supply Current
PECL
24
30
24
30
24
30
rnA
ICCH
TIL
24
30
24
30
24
30
rnA
27
35
27
35
27
35
rnA
Max
Unit
ICCL
Typ
Max
Min
TA = + 65°C
lEE
Characteristic
Typ
Max
Min
Condition
TTL DC CHARACTERISTICS (VT = VE = 5.0V ±5%)
O°C
Symbol
Characteristic
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
lOS
Output Short Circuit Current
Min
25°C
Max
Min
2.5
85°C
Max
2.5
2.5
0.5
-100
Min
V
0.5
-225
-100
Max
Min
-225
-100
Max
Min
Condition
IOH=-15mA
0.5
V
IOL=24rnA
-225
rnA
VOUT=OV
Max
Unit
175
J.LA
10H PECl DC CHARACTERISTICS
O°C
Symbol
Characteristic
IIH
Input HIGH Current
Min
25°C
225
85°C
175
0.5
0.5
Condition
IlL
Input LOW Current
0.5
VIH
Input HIGH Voltage
3.83
4.16
3.87
4.19
3.94
4.26
V
VE=5.0V1
VIL
Input LOW Voltage
3.05
3.52
3.05
3.52
3.05
3.55
V
VE=5.0v1
J.LA
VE=5.0V1
Output Reference Voltage
3.62
3.73
3.65
3.75
3.69
3.81
V
Vee
1. PECL VIH. VIL. and Vee are referenced to VE and will vary 1:1 with lhe power supply. The levels shown are for VE = 5.0V.
MOTOROLA
2-126
MECLData
DL122-Rev6
MC10H641 MC100H641
100H PECl DC CHARACTERISTICS
DOC
Symbol
Characteristic
IIH
Input HIGH Curren
Min
2SoC
Max
8SoC
Min
Max
225
Min
175
Max
Unil
175
~
Condilion
~A
IlL
Input LOW Current
0.5
VIH
Input HIGH Voltage
3.835
4.120
3.B35
4.120
3.B35
4.120
V
VE=5.0V1
V,L
Input LOW Voltage
3.190
3.525
3.190
3.525
3.190
3.525
V
VE = 5.0V1
VBB
Output Reference Voltage
3.62
3.74
3.62
3.74
3.62
3.74
V
VE = 5.0Vl
0.5
0.5
1. PECL VIH, V'L, and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0V.
AC CHARACTERISTICS (VT
=VE =5.0V ±5%)
TJ=+2SoC
TJ = O°C
Symbol
1.
2.
3.
4.
5.
TJ=+85°C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
tpLH
tpHL
Propagation Delay
DtoO
5.00
5.36
5.50
5.86
6.00
6.36
4.86
5.27
5.36
5.77
5.86
6.27
5.0B
5.43
5.58
5.93
6.0B
6.43
ns
tskew
Device Skew
Part-la-Part
SingleVcc
Output-ta-Output
Condilion
CL = 50 pF1
ps
1000
750
350
1000
750
350
CL= 50pF2
CL=50pF3
CL = 50 pF4
1000
750
350
tpLH
tpHL
Propagation Delay
LEN toO
4.9
6.9
4.9
6.9
5.0
7.0
ns
CL=50pF
tpLH
tpHL
Propagation Delay
ENtoO
5.0
7.0
4.9
6.9
5.0
7.0
ns
CL= 50 pF
tr
tf
Output RiselFail
0.BVto2.0V
1.7
1.6
ns
CL= 50 pF
fMAX
Max Input Frequency
MHz
CL = 50 pFS
1.7
1.6
65
1.7
1.6
65
65
tREC
Recovery lime EN
1.25
ts
Setup lime
0.75
0.50
0.75
1.25
0.50
0.75
1.25
0.50
ns
ns
tH
Hold lime
0.75
0.50
0.75
0.50
0.75
0.50
ns
Propagation delay measurement guaranteed for junction temperatures. Measurements performed at 50MHz input frequency.
Skew window guaranteed for a single temperature across a VCC = VT = VE of 4.75V to 5.25V (See Application Note in this datasheet).
Skew window guaranteed for a single temperature and single VCC = VT = VE
Output-to-output skew is specified for identical transitions through the device.
Frequency at which output levels will meet a O.BV to 2.0V minimum swing.
DETERMINING SKEW FOR A SPECIFIC APPLICATION
The H641 has been designed to meet the needs of very low
skew clock distribution applications. In order to optimize the
device for this application special considerations are
necessary in the determining of the part-to-part skew
specification limits. Older standard logic devices are specified
with relatively slack limits so that the device can be
guaranteed over a wide range of potential environmental
conditions. This range of conditions represented all of the
potential applications in which the device could be used. The
result was a specification limit that in the vast majority of cases
was extremely conservative and thus did not allow for an
optimum system design. For non-critical skew designs this
practice is acceptable, however as the clock speeds of
MECLData
DL122-Rev6
systems increase overly conservative specification limits can
kill a design.
The following will discuss how users can use the
information provided in this data sheet to tailor a part-to--part
skew specification limit to their application. The skew
determination process may appear somewhat tedious and
time consuming, however if the utmost in performance is
required this procedure is necessary. For applications which
do not require this level of skew performance a generic
part-to--part skew limit of 2.5ns can be used. This limit is good
forthe entire ambienttemperature range, the guaranteed Vee
(VT, VEl range and the guaranteed operating frequency range.
2-127
MOTOROLA
MC10H641 MC100H641
Temperature Dependence
A unique characteristic of the H641 data sheet is thai the
AC parameters are specified for a junction temperature rather
than the usual ambient temperature. Because very few
designs will actually utilize the entire commercial temperature
range of a device a tighter propagation delay window can be
established given the smaller temperature range. Because
the junction temperature and not the ambient temperature is
what affects the performance of the device the parameter
limits are specified for junction temperature. In addition the
relationship between the ambient and junction temperature
will vary depending on the frequency, load and board
environment of the application. Since these factors are all
under the control of the user it is impossible to provide
specification limits for every possible application. Therefore a
baseline specification was established for specific junction
temperatures and the information that follows will allow these
to be tailored to specific applications.
Figure 2 illustrates the thermal resistance (in °CIW) for the
28--lead PLCC under various air flow conditions. By reading
the thermal resistance from the graph and multiplying by the
power dissipation calculated above the junction temperature
increase above ambient of the device can be calculated.
70
~
60
w
u
z
~
en
u;
00
:\
"':-...r-.....
w
a:
-'
«
::;;
a:
w
Since the junction temperature of a device is difficult to
measure directly, the first requirement is to be able to
"translate" from ambient to junction temperatures. The
standard method of doing this is to use the power dissipation
of the device and the thermal resistance of the package. For
a TTL output device the power dissipation will be a function of
the load capacitance and the frequency olthe output. The total
power dissipation of a device can be described by the
following equation:
:J:
I-
40
30
r--....,
l"'- t-
o
200
:-r-
600
400
600
AIRFLOW (LFPM)
1000
Figure 2. 0JA versus Air Flow
=
PD (watts) ICC (no load) • VCC +
VS' VCC • f • CL • # Outputs
where:
VS= Output Voltage Swing
f = Output Frequency
CL = Load Capacitance
ICC = lEE + ICCH
=3V
Figure 1 plots the ICC versus Frequency of the H641 with
no load capacitance on the output. Using this graph and the
information specific to the application a user can determine
the power dissipation of the H641.
5
.......
---
Finally laking this value for junction temperature and
applying it to Figure 3 allows the user to determine the
propagation delay for the device in question. A more common
use would be to establish an ambient temperature range for
the H641 's in the system and utilize the above methodology
to determine the potential increased skew of the distribution
network. Note that for this information if the TpD versus
Temperature curve were linear the calculations would not be
required. If the curve were linear over all temperatures a
simple temperature coefficient could be provided.
6.4
V
~
6.2
~
5w
6.0
c
3
z
0
~
5.8
\
~
05.00
o 4.75
o 5.00
D 5.25
10
0-
w
2:
!;{
0-
w
~0
o 4.875
o 5.00
0-
w 10.0
>
• 5.125
~
o 5.00
9.8
10.4
~
w 10.2
~
10
20
3D
40
CAPACITIVE LOAD (pF)
50
9.4
so
0
10
20
3D
40
50
so
CAPACITIVE LOAD (pf)
Figure 4. MC10H642 Negative PW versus Load
@ ±2.5% VCC, TA = 25°C
Figure 3. MC10H642 Positive PW versus Load
@±2.5%VCC, TA = 25°C
10.5 ,--------------------------,
g
~
10.3
~
w
10.1
~
:::>
0-
o opF
9.9
~
~
ffl
z
9.7
9.5
o 25pF
L_-----______
--::
D
SOpF
!'--....~--~
20
40
SO
80
100
TEMPERATURE (0C)
Figure 5. MC10H642 Positive PW versus Temperature,
VCC= 5.0V
MECLDala
DL122-Rev6
Figure 6. MC10H642 Negative PW versus
Temperature, VCC = 5.0V
2-135
MOTOROLA
MC10H642 MC100H642
6.2
6.0
..,.s.
5.8
" 4.75
o 5.00
"8.
>-
5.6
• 5.25
5.4
CAPACITIVE (pF)
Figure 7. MC10H642 + Tpd versus Load, VCC ±5%, TA = 25°C
(Overshoot at 50 MHz with no load makes graph non linear)
DT
RESET, R
R
tpw
---
R
tree
1\
/
/
\
•
OO-'01~======~~-=======~-L~
02-' 07
-------------.-~
\
~
/
/
MCl 011 00H642
Figure 8. Clock Phase and Reset Recovery Time After Reset Pulse
MC10/l00H642
00.01
\,-------,1
r-----
04&05
02-07-------
\'---
__I
After Power Up
Figure 9. Outputs Q2 - . Q7 will Synchronize with Pos Edges of Din & QO - . Q1
MOTOROLA
2-136
MECLData
DL122-Rev6
MC10H642 MC100H642
Switching Circuit PECl:
PECl
USE 0.111F CAPACITORS
FOR DECOUPLING.
USE OSCILLOSCOPE
INTERNAL 50 n LOAD
FOR TERMINATION.
WAVEFORMS: Rise and Fall Times
Propagation Delay -
PECLfITl
PECLfITl
Single Ended
50%/1.5 V
Vin
Vout
Trise
MECLData
DL122-Rev6
Tfall
Vout
------'
2-137
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Supply
ECL-TTL 1:8 Clock Driver
MC10H643
MC100H643
The MC1 OH/1 OOH643 is a dual supply, low skew translating 1:8 clock
driver. Devices in the Motorola H600 translator series utilize the 28-lead
PLCC for optimal power pinning, signal flow through and electrical
perfonnance. The dual-supply H643 is similar to the H641, which is a
single-supply 1:9 version of the same function.
DUAL SUPPLY
ECl-TTl1:8
CLOCK DRIVER
The device features a 48mA TTL output stage, with AC performance
specified into a 50pF load capacitance. A Latch is provided on--chip.
When LEN is LOW (or left open, in which case it is pulled LOW by the
internal pulldowns) the latch is transparent. A HIGH on the enable pin
(EN) forces all outputs LOW.
The 10H version is compatible with MECL 10HTM ECL logic levels. The
100H version is compatible with 100K levels.
• ECL.!TTL Version of Popular ECLinPSTM E111
• Low Skew Within Device 0.5ns
• Guaranteed Skew Spec Part-ta-Part 1.0ns
• Latch
• Differential Internal Design
• VssOutput
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02
• Dual Supply
• ReseVEnable
• Multiple TTL and ECL Power/Ground Pins
Pinout: 28-Lead PLCC (Top View)
0')
0
0
0
0
§
25
24
23
22
....
z(!J
'"
....
z(!J
0
0
'"
0
15
21
20
19
PIN NAMES
IVT2
OGND2
IGND2
02
VCCE
OVT1
VCCE
01
lEN
OGND1
Vaa
00
FUNCTION
PIN
OGND
OVT
IGND
IVT
VEE
VCCE
D,D
Vaa
0O-Q7
EN
lEN
TTL Output Ground (OV)
TTL Output Vce (+5.0V)
Internal TTL GND (OV)
Internal TTL Vce (+5.0V)
ECl VEE (-5.21-4.5V)
ECl Ground (OV)
Signal Input (ECl)
Vaa Reference Output
Signal Outputs (TTL)
Enable Input (Eel)
Latch Enable Input (ECl)
D
~
6
7
Ei
z
~
£!
w
8
w
~
9
10
w
la'i
~
0
ECLinPS and MECl 10H are trademarks of Motorola, Inc.
11/93
© Motorola, Inc. 1996
2-138
REV 3
®
MOTOROLA
MC10H643 MC100H643
LOGIC DIAGRAM
ECLINPUT
o
0_-._......_ .... 0
Q
LEN----'
EN------'
DC CHARACTERISTICS (IVT = OVT = 5.0V ±5%; VEE = -5.2V ±5% (10H Version); VEE = -4.5V +0.3V
(100H Version»
25°C
O°C
Symbol
Characteristic
ECL
lEE
ICCL
Power Supply Current
TTL
ICCH
85°C
Min
Max
Min
Max
Min
Max
Unit
-
42
-
42
-
42
rnA
106
-
106
rnA
Total all OVT
95
rnA
and IVTpins
-
-
106
95
95
Condition
VEE Pins
AC CHARACTERISTICS (lVT = OVT = 5.0V ±5%; VEE = -S.2V ±10% (10H); -4.5V ±O.3V (100H); VCCE = GND)
O°C
Symbol
tpLH
Characteristic
0
tSKEW
Within-Device Skew
tw
Pulse Width Out
HIGH or LOW
@ fout = 50MHz
Ih
Hold Time
tRR
Recovery TIme
LEN
EN
tr
If
Min
Max
Min
Max
Unit
4.0
3.5
3.5
5.0
5.5
5.5
4.1
3.5
3.5
5.1
5.5
5.5
4.4
3.9
3.9
5.4
5.9
5.9
ns
-
0.5
-
0.5
0.5
ns
Condition
0
Minimum Pulse Width
LEN
EN
Rise I Fall TImes
0.8 V -2.0 V
CL=50pF
Note 1
CL=50pF
9.0
11.0
9.0
11.0
9.0
11.0
. ns
Note 2
Setup TIme
0
Ipw
85°C
Max
Propagalion Delay 10 OUlpul
LEN
EN
ts
25°C
Min
0.75
-
0.75
-
0.75
-
ns
0.75
-
0.75
-
0.75
-
ns
1.25
1.25
-
1.25
1.25
-
1.25
1.25
-
ns
1.5
1.5
-
-
ns
-
1.5
1.5
-
-
1.2
-
1.2
-
1.2
ns
1.5
1.5
-
-
-
-
CL= 50pF
1. Within-Device skew defined as identical transitions on similar paths through a device.
2. Pulse width is defined relative to 1.5V measurement points on the ouput waveform.
MECLData
DL122-Rev6
2-139
MOTOROLA
MC10H643 MC100H643
TRUTH TABLE
0
LEN
EN
Q
L
H
L
L
H
L
L
L
H
L
H
aO
L
X
X
X
DC CHARACTERISTICS (lVT
=OVT =5.0V -+5%; VEE =-5.2V +5%
(10H Version); VEE =-4.5V ±O.3V (1 OOH Version))
D'C
Symbol
Characteristic
25'C
85'C
Min
Max
Min
Max
Min
Max
-
2.5
2.0
-
-
Unit
Condition
VOH
Output HIGH Voltage
2.5
2.0
-
2.5
2.0
VOL
Output LOW Voltage
-
0.5
-
0.5
-
0.5
V
IOH=48mA
lOS
Output Short Circuit Current
-100
-225
-100
-225
-100
-225
mA
VOUT=OV
10H DC CHARACTERISTICS (IVT
=OVT =5.0V ±5%; VEE =-5.2V ±5% (10H Version); VEE =-4.5V ±O.3V (100H Version))
25'C
D'C
Symbol
V
Characteristic
85'C
Min
Max
Min
Max
Min
Max
Unit
-
225
-
175
-
175
jlA
IIH
IlL
Input HIGH Current
Input LOW Current
0.5
-
D.5
-
0.5
-
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
-1170
-1950
-a40
-1480
-1130
-1950
-a1O
-1480
-1070
-1950
-735
-1450
mV
VBB
Output Reference Voltage
-1380
-1270
-1350
-1250
-1310
-1190
mV
100H DC CHARACTERISTICS (lVT
Characteristic
25'C
85'C
Min
Max
Min
Max
Min
Max
Unit
-
225
-
175
-
175
jlA
IIH
IlL
Input HIGH Current
Input LOW Current
0.5
-
0.5
-
0.5
-
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
-1165
-1810
-a80
-1475
-1165
-1810
-a80
-1475
-1165
-1810
-a80
-1475
mV
VBB
Output Reference Voltage
-1380
-1260
-1380
-1260
-1380
-1260
mV
MOTOROLA
Condition
=OVT =5.0V ±5%; VEE =-5.2V ±5% (10H); VEE =-4.5V ±O.3V (l00H))
D'C
Symbol
IOH=-3·0mA
IOH=-15mA
2-140
Condition
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
68030/040
PECL-TTL Clock Driver
MC10H644
MC100H644
The MCl OH/l 00H644 generates the necessary clocks for the 68030,
68040 and similar microprocessors. The device is functionally equivalent
to the H640, but with fewer outputs in a smaller outline 2Q-lead PlCC
package. It is guaranteed to meet the clock specifications required by the
68030 and 68040 in terms of part-ta-part skew, within-part skew and
also duty cycle skew.
68030/040
PECL-TTL CLOCK
DRIVER
• Generates Clocks for 68030/040
• Meets 68030/040 Skew Requirements
• TTL or PECl Input Clock
•
• Extra TTL and ECl Power/Ground Pins
• Within Device Skew on Similar Paths is O.S ns
• Asynchronous Reset
• Single +S.OV Supply
The user has a choice of using either TTL or PECl (ECl referenced to
FN SUFFIX
+S.OV) for the input clock. TTL clocks are typically used in present MPU
PLASTIC PACKAGE
systems. However, as clock speeds increase to SOMHz and beyond, the
CASE 775-02
inherent superiority of ECl (particularly differential ECl) as a means of
clock signal distribution becomes increasingly evident. The H644 also
uses differential ECl internally to achieve its superior skew characteristic.
The H644 includes divide-by-two and divide-by-four stages, both to
achieve the necessary duty cycle and skew to generate MPU clocks as required. A typical SOMHz processor application would
use an input clock running at 100MHz, thus obtaining output clocks at SOMHz and 2SMHz (see logic Symbol).
The 10H version is compatible with MECl 10HT" ECl logic levels, while the 100H version is compatible with lOOK levels
(referenced to +S.OV).
Function
Reset (R): lOW on RESET forces all Q outputs lOW and all Q outputs HIGH.
Synchronized Outputs: The device is designed to have the POS edges of the +2 and +4 outputs synchronized.
Select (SEL): lOW selects the ECl input source (DE/DE). HIGH selects the TTL input source (DT).
The H644 also contains circuitry to force a stable slate of the ECl input differential pair, should both sides be left open. In this
case, the DE side of the input is pulled lOW, and DE goes HIGH.
Pinout: 20-Lead PLCC (Top View)
04VT05GT
Ii
GT
VE
Q3
DE
GT
VBB
Q2
i'iE
GT
GE
01
VT
00
SEL
DT
MECL 10H is a trademark of Motorola, Inc.
11193
© Motorola, Inc. 1995
2-141
REV 3
®
MOTOROLA
MC10H644 MC100H644
LOGIC DIAGRAM
00
DE
~Cl)
DE
(ECl)
PIN NAMES
PIN
FUNCTION
GT
VT
VE
GE
DE, DE
VBB
DT
On,On
SEl
DT
(TTl)
TTL Ground (OV)
TTL VCC (+5.0V)
ECl VCC (+5.0V)
ECl Ground (OV)
ECl Signal Input (positive ECl)
VBB Reference Output
TTL Signal Input
Signal Outputs (TTL)
Input Select (TTL)
Reset (TTL)
R
01
02
SEl
(TTl)
Q4
l'i
05
(TTl)
AC CHARACTERISTICS (VT
=VE =5.0 V ±5%)
O°C
Symbol
Characteristic
tPlH
Propagation Delay ECl
DtoOutput
All Outputs
tplH
Propagation Delay TTL
DtoOutput
tskwd'
Within-Device Skew
00,1,4,5
tskwd'
Within-Device Skew
02,03
85°C
25°C
Min
Max
Min
Max
Min
Max
Unit
5.B
6.B
5.7
6.7
6.1
7.1
ns
Cl=50pF
5.7
6.7
5.7
6.7
6.0
7.0
ns
Cl=50pF
0.5
-
0.5
-
0.5
ns
Cl=50pF
0.5
-
0.5
-
0.5
ns
Cl=50pF
-
Condition
tskwd'
Within-Device Skew
All Outputs
-
1.5
-
1.5
-
1.5
ns
Cl= 50pF
tskp-p
Part-te-Part Skew
00,1,4,5
-
1.0
-
1.0
-
1.0
ns
Cl= 50pF
tpD
Propagation Delay
RtoOutput
All Outputs
4.3
7.3
4.3
7.3
4.5
7.5
ns
Cl=50pF
tR
tF
Output Rise/Fall Time
0.BV-2.0V
All Outputs
-
1.6
-
1.6
-
1.6
ns
Cl=50pF
-
135
135
-
MHz
Cl= 50pF
1.5
-
ns
1.25
-
1.25
-'
1.25
-
ns
9.5
10.5
9.5
10.5
9.5
10.5
ns
.
fmax
Maximum Input Frequency
135
TW
Minimum Pulse Width Reset
1.5
1.5
-
trr
Reset Recovery Time
TpW
Pulse Width Out High or
low @ fin = 100 MHz
and Cl = 50 pf
TS
Setup Time
SEltoDE, DT
2.0
-
2.0
-
2.0
-
Hold Time
SElto DE, DT
2.0
-
2.0
-
2.0
-
TH
00,1
Cl=50pf
Relative 1.5V
ns
ns
• Skews are specified for Identical Edges
MOTOROLA
2-142
MEClData
Dl122-Rev6
MC10H644 MC100H644
DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
aOc
Characteristic
Symbol
lEE
ICC
25°C
Min
Unit
65
65
rnA
VE Pin
1 TTL
85
85
85
rnA
Total all VT pins
Max
Unit
aOc
VIH
Vil
Input HIGH Voltage
Input lOW Voltage
IIH
Input HIGH Current
Min
=VE =5.0 V ±5%)
Characteristic
Symbol
Max
Condition
Max
65
TTL DC CHARACTERISTICS (VT
Max
85°C
I ECl
Power Supply Current
Min
Min
25°C
Max
Min
2.0
85°C
Max
2.0
Min
2.0
0.8
0.8
0.8
20
100
20
100
20
100
1IA
VIN=2.7V
VIN=7.0V
-0.6
rnA
VIN=0.5V
III
Input lOW Current
VOH
Output HIGH Voltage
-0.6
-0.6
VOL
Output lOW Voltage
0.5
0.5
VIK
Input Clamp Voltage
-1.2
-1.2
lOS
Output Short Circuit Current
-225
2.5
2.0
2.5
2.0
-100
Condition
V
-225
2.5
2.0
-100
-225
-100
V
IOH=-3·0mA
10H =-24 rnA
0.5
V
IOl=24mA
-1.2
V
liN =-18 rnA
rnA
VOUT=OV
10H PECl DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
25°C
O°C
Characteristic
Symbol
Min
Max
Min
85°C
Max
Unit
175
~A
3.94
3.05
4.28
3.55
V
VE=5.0V
3.75
3.69
3.81
V
VE=5.0V
Max
Min
Max
Unit
175
~A
Max
IIH
III
Input HIGH Current
Input lOW Current
225
0.5
VIH'
Vil'
Input HIGH Voltage
Input lOW Voltage
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
VSS'
Output Reference Voltage
3.62
3.73
3.65
Min
175
0.5
Condition
0.5
100H PECl DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
O°C
Characteristic
Symbol
Min
85°C
25°C
Max
Min
Condition
IIH
III
Input HIGH Current
Input lOW Current
0.5
VIH'
Vil'
Input HIGH Voltage
Input lOW Voltage
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
V
VE =5.0V
VSS'
Output Reference Voltage
3.62
3.74
3.62
3.74
3.62
3.74
V
VE=5.0V
225
175
0.5
0.5
• NOTE: PECl levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0 V.
Only corresponds to ECl Clock Inputs.
MEClData
Dl122-Rev6
2-143
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:9 TTL Clock Driver
MC10H645
The MC1 OH645 is a single supply, low skew, TTL I/O 1:9 Clock Driver.
Devices in the Motorola H600 clock driver family utiize the 28-lead PLCC
for optimal power and signal pin placement.
The device features a 24mA TTL ouput stage with AC performance
specified into a 50pF load capacitance. A 2:1 input mux is provided on
chip to allow for distributing both system and diagnostic clock signals or
designing clock redundancy into a system. With the SEL input held LOW
the DO input will be selected, while the 01 input is selected when the SEL
input is forced HIGH.
1:9 TTL
CLOCK DRIVER
• Low Skew Typically 0.65ns Within Device
• Guaranteed Skew Spec 1.25ns Part-to-Part
• Input Clock Muxing
• Differential ECL Internal Design
• Single Supply
• Extra TTL and ECL Power/Ground Pins
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02
PIN NAMES
PIN
FUNCTION
GT
VT
VE
GE
On
OO-OS
SEL
TTL Ground (OV)
TTL VCC (+5.0V)
ECl VCC (+5.0V)
ECl Ground (OV)
TTL Signal Input
TTL Signal Outputs
TTL Mux Select
LOGIC DIAGRAM
Pinout: 28-Lead PLCC (Top View)
TTL Outputs
TTL
Inputs
GT
06
VT
07
VT
08
GT
00
MUX
00
00
00
D1
01
01
Q
01
GT
NC
02
05
DO
04
VE
VT
SEL
03
GE
GT
NC
Q
01
03
04
05
SEL
06
07
OS
GT
9/96
© Motorola. Inc. 1996
2-144
REV4
02
VT
01
®
VT
00
GT
MOTOROLA
MC10H645
PIN DESCRIPTIONS
Pin
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
04
Description
Signal Output (TTL)
TTL VCC (+5.0V)
Signal Output (TTL)
TTL Ground (OV)
TTL Ground (OV)
Signal Output (TTL)
TTL VCC (+5.0V)
Signal Output (TTL)
TTL VCC (+5.0V)
Signal Output (TTL)
TTL Ground (OV)
No Connection
ECLGround
Select Input (TTL)
VT
03
GT
GT
02
VT
01
VT
00
GT
NC
GE
SEl
Pin
Symbol
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VE
Dl
DO
NC
GT
08
VT
07
VT
06
GT
GT
05
VT
Description
ECL VCC (+5.0V)
Signal Input (TTL)
Signal Input (TTL)
No Connection
TTL Ground (OV)
Signal Output (TTL)
TTL VCC (+5.0V)
Signal Output (TTL)
TTL VCC (+5.0V)
Signal Output (TTL)
TTL Ground (OV)
TTL Ground (OV)
Signal Output (TTL)
TTL VCC (+5.0V)
ABSOLUTE RATINGS (Do nol exceed)
Symbol
Value
Unit
VE(ECL)
Power Supply Voltage
Characteristic
-0.5 to +7.0
V
VT(TTL)
Power Supply Voltage
-0.5 to +7.0
V
VI (TTL)
Input Voltage
-0.5 to +7.0
V
Vout
Disabled 3-8tate Output
0.0 to VT
V
Tstg
Storage Temperature
-6510150
°C
Tamb
Operating Temperature
0.0 to +85
°C
TRUTH TABLE
DO
01
SEL
Q
l
H
X
X
X
X
l
H
l
L
H
H
l
H
L
H
DC CHARACTERISTICS (VT
=VE =5.0V ±5%)
DOC
Symbol
lEE
Characteristic
Power Supply Current
Min
ECl
IceL
VOH
Output HIGH Voltage
VOL
Output lOW Voltage
lOS
Output Short Circuit Current
MEClData
DL122- Rev 6
Min
30
TTL
ICCH
25°C
Max
Min
30
Max
Unit
30
rnA
VEPin
Total all VT pins
30
30
30
rnA
35
35
35
rnA
2.5
2.0
2.5
2.0
0.5
-100
85°C
Max
-225
0.5
-100
2-145
V
2.5
2.0
-225
-100
Condition
IOH=-3·0mA
IOH=-15mA
0.5
V
IOl=24mA
-225
rnA
VOUT=OV
MOTOROLA
MC10H645
TIL DC CHARACTERISTICS (VT
=VE =5.0 V ±5%)
O°C
Symbol
Characteristic
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
IIH
Input HIGH Current
Min
25°C
Max
Min
2.0
B5°C
Max
Min
2.0
Max
2.0
O.B
0.8
0.8
20
100
20
100
20
100
~
VIN=2.7V
VIN =7.0V
-{l.6
rnA
VIN=0.5V
-{l.6
-{l.6
IlL
Input LOW Current
Output HIGH Voltage
VOL
Output LOW Voltage
0.5
0.5
VIK
Input Clamp Voltage
-1.2
-1.2
lOS
Output Short Circuit Current
-225
AC CHARACTERISTICS (VT
2.5
2.0
2.5
2.0
tpLH
tpLH
Propagation Delay
Dl to Output
tpHL
Propagation Delay
DO to Output
Dl to Output
-225
-100
V
10H =-3.0 rnA
IOH=-24mA
0.5
V
IOL=24mA
-1.2
V
IIN=-18mA
rnA
VOUT=OV
-225
-100
Min
Max
Min
Max
Min
Max
Unit
4.8
5.8
4.8
5.B
5.2
6.2
ns
4.8
5.8
4.8
5.8
5.2
6.2
ns
4.8
4.8
5.8
5.8
4.8
4.8
5.8
5.8
5.2
5.2
6.2
6.2
O°C
Propagation Delay
DO to Output Only
2.5
2.0
=VE =5.0V ±5%)
Characteristic
Symbol
Condition
V
VOH
-100
Unit
00-Q8
25°C
85°C
Condition
CL=50pF
ns
tskpp
Part-ta-Part Skew
DO to Output Only
tskwd'
Within-Device Skew
DO to Output Only
tpLH
Propagation Delay
SELtoO
OO-QB
4.5
6.5
5.0
7.0
tr
tf
Output Rise/Fall Time
0.8Vt02.0V
0O-Q8
0.5
0.5
2.5
2.5
0.5
0.5
2.5
2.5
ts
Setup TIme
SEL to D
1.0
1.0
1.0
ns
0.65
0.65
0.65
ns
5.2
7.2
ns
CL=50pF
0.5
0.5
2.5
2.5
ns
CL=50pF
ns
..
1.0
1.0
1.0
, WIthIn-DevIce Skew defIned as IdentIcal transItIons on SImilar paths through a devIce.
DUTY CYCLE SPECIFICATIONS (DOC S TA S 85°C; Duty Cycle Measured Relative to 1.5V)
Symbol
PW
Characteristic
Range of VCC and CL to Meet Min Pulse
Width (HIGH or LOW) at fout :;;50MHz
MOTOROLA
I
VCC
CL
PW
Min
Nom
Max
Unit
Condition
4.875
10.0
9.0
5.0
5.125
50.0
11.0
V
pF
ns
All Outputs
2-146
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PECL/TTL-TTL 1:8 Clock
Distribution Chip
MC10H646
MC100H646
The MC1 OH/1 00H646 is a single supply, low skew translating 1:8 clock
driver. Devices in the Motorola H600 translator series utilize the 28-lead
PLCC for optimal power pinning, signal flow through and electrical
performance. The single supply H646 is similar to the H643, which is a
dual supply 1:8 version of the same function.
PENTIUM
MICROPROCESSOR
PECLfTTL-TTL
CLOCK DRIVER
• PECLlTTL-TTl Version of Popular ECLinPSTM E111
• lowSkew
• Guaranteed Skew Spec
• Tri-State Enable
• Differential Internal Design
• VBB Output
• Single Supply
• Extra TTL and ECl Power/Ground Pins
• Matched High and low Output Impedance
• Meets Specifications Required to Drive the Pentium™ Microprocessor
FNSUFFIX
PLASTIC PACKAGE
The H646 was designed specifically to drive series terminated
CASE 776-02
transmission lines. Special techniques were used to match the HIGH and
lOW output impedances to about 70hms. This simplifies the choice of the
termination resistor for series terminated applications. To match the HIGH an lOW output impedances, it was necessary te
remove the standard lOS limiting resistor. As a result, the user should take care i preventing an output short to ground as the par
will be permanently damaged.
The H646 device meets all of the requirements for driving the 60 and 66MHz Pentium Microprocessor. The device has no Pll
components, which greatly simplifies its implementation into a digital design. The eight copies of the clock allows for
pOint-to-point clock distribution to simplify board layout and optimize signal integrity.
The H646 provides differential PECl inputs for picking up lOW skew PECl clocks from the backplane and distribu1ing it to
TTL loads on a daughter board. When used in conjunction with the MC1 0/1 00E111 , very low skew, very wide clock trees can be
designed. In addition, a TTL level clock input is provided for flexibility. Note that only one of the inputs can be used on a single
chip. For correct operation, the unused input pins should be left open.
The Output Enable pin forces the outputs into a high impedance state when a logic 0 is applied.
The output buffers of the H646 can drive two series terminated, 50Q transmission lines each. This capability allows the H646
to drive up to 16 different point-to-point clock loads. Refer to the Applications section for a more detailed discussion in this area.
The 10H version is compatible with MECl 10HTM ECl logic levels. The 100H version is compatible with 100K levels.
MECL 10H and ECLinPS are trademarks of Motorola, Inc. Pentium is a trademark of Intel Corporation.
8194
© Motorola, Inc. 1996
2-147
REV 1
®
MOTOROLA
MC10H646 MC100H646
...
c
z
c
z
a
0
C!l
a"'
!>0
a
CD
C!l
0
a
25
24
23
22
21
20
19
PIN NAMES
....
PIN
18
03
EN
IGND
02
Pinout: 28-Lead PLCC
OVT
(Top View)
01
15
VCCE
14
VCCE
VEE
VCCE
ECLK,ECLK
VBB
ao-Q7
VBB
OGND
TIL Output Ground (OV)
TIL Output VCC (+5.0V)
Internal TIL GND (OV)
Internal TIL VCC (+5.0V)
ECLVEE(OV)
ECL Ground (5.0V)
Differential Signal Input
(PECL)
VBB Reference Output
Signal Outputs (TIL)
Tri-State Enable Input (TIL)
OGND
OVT
IGND
IVT
IVT
OGND
FUNCTION
EN
12
00
5
~
...J
~
6
7
8
9
10
~
c
w
w
w
Z
~
W
W
>
>
W
>
ECLK
11
IVTOI
~
...J
OVTOI
u
w
OOA
LOGIC DIAGRAM
EN----------------,
00
OGNOO
INTERNAL TIL GROUNO L------
w
w
>
9
10
11
'"
0
is
I~
S2
3/93
© Motorola. Inc. 1996
2-151
REVS
®
MOTOROLA
MC10H660 MC100H660
DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = -5.2 V ±5% (10H version); VEE = -4.2 V to -5.5 V (100H version)
GOC
Symbol
Characteristic
lEE
Power Supply Current
ICCH
25°C
min
85°C
max
Unit
ECL
41.8
44.0
46.2
mA
TTL
77.0
77.1
79.2
mA
94.6
95.7
96.8
rnA
min
max
ICCL
max
min
Condition
TTL CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = -5.2 V ±5% (10H version); VEE = -4.2 V to -5.5 V (100H version)
GOC
Symbol
Characteristic
min
VOH
Output HIGH Voltage
2.6
VOL
Output LOW Voltage
lOS
Output Short Circuit Current'
25°C
max
min
85°C
max
2.6
min
max
2.6
0.50
0.50
0.50
,
,
,
Unit
Condition
V
IOH=-24mA
V
10L= 24 rnA
V
See Note 1
1. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device do not
include a limiting lOS resistor. Minimum recommended load capacitance is 100 pF. Precise output performance and waveforms will depend
on the exact nature of the actual load. The lumped load is of course an approximation to a real memory system load.
[::2J
AC Characteristics: VCCT = 5.0 V± 10%; VEE =-5.2 V ±5% (10H version) VEE =-4.2 V to-5.5 V (100H version)
GOC
25°C
85°C
Symbol
Characteristic
min
ts
Set-up lime, D to LEN
0.5
tn
Hold lime, D to LEN
1.5
1.5
1.5
ns
tw(H)
LEN Pulse Width, HIGH
2.0
2.0
2.0
ns
tR
tF
Output Rise/Falllime
0.8V-2.0V
0.5
2.0
0.5
2.0
0.5
2.0
ns
CL = 200 pF
tpLH
tpHL
Propagation Delay
to Output
D
3.0
4.0
4.5
6.0
8.0
9.5
3.0
4.0
4.5
6.0
B.O
9.5
3.0
4.0
4.5
6.0
8.0
9.5
ns
CL=100pF
CL = 200 pF
CL = 300 pF
50% point of ECL input
to 1.5 V point of TTL
output
LEN
4.3
4.9
5.4
6.9
8.9
10.4
4.3
4.9
5.4
6.9
8.9
10.4
4.3
4.9
5.4
6.9
8.9
10.4
ns
CL=100pF
CL = 200 pF
CL= 300pF
tpHL
Propagation Delay
to Output
R
4.1
4.5
5.0
9.1
8.5
10.0
4.1
4.5
5.0
9.1
8.5
10.0
4.1
4.5
5.0
9.1
8.5
10.0
ns
CL=100pF
CL =200 pF
CL = 300 pF
tpLH
Propagation Delay
to Output
D
3.9
4.8
5.8
5.9
7.2
8.8
3.9
4.8
5.B
5.9
7.2
B.B
4.0
5.0
5.9
6.1
7.4
8.9
ns
CL=100pF
CL =200 pF
CL = 300 pF
50% point of ECL input
to 2.4 V pOint of TTL
output
LEN
4.7
5.5
6.3
7.1
8.3
9.5
4.7
5.5
6.3
7.1
B.3
9.5
4.8
5.6
6.4
7.2
8.4
9.6
ns
CL=100pF
CL=200 pF
CL = 300 pF
Propagation Delay
to Output
D
4.5
6.0
7.0
6.7
9.0
10.6
4.5
6.0
7.0
6.7
9.0
10.6
4.4
6.0
6.9
6.6
9.0
10.3
ns
CL=100pF
CL = 200 pF
CL = 300 pF
50% pOint of ECL input
to 0.8 V point of TTL
output
LEN
4.0
4.9
6.0
6.0
7.3
9.0
4.0
4.9
6.0
6.0
7.3
9.0
4.0
4.9
5.9
6.0
7.3
8.9
ns
CL= 100 pF
CL=200 pF
CL= 300 pF
R
4.3
6.1
7.2
6.5
9.1
10.B
4.3
6.1
7.2
6.5
9.1
10.8
4.3
6.1
7.2
6.5
9.1
10.8
ns
CL=100pF
CL = 200 pF
CL = 300 pF
tpHL
MOTOROLA
max
min
max
max
Unit
Condition
ns
0.5
0.5
2-152
min
MECLData
DL122-Rev6
MC10H660 MC100H660
OUTPUT STRUCTURE
POWER VS FREQUENCY
- Output QOA Structure Shown
INT~~TT~
-typical
POWER VS FREQUENCY
PER BIT
700
IVTOl
OVTOl
PDYNAMIC = CL f VSWING VCC
600
PTOTAl = PSTATIC + PDYNAMIC
500
:;::
E
.,.
l\!0
Q.
QOA
400 +----------.~--____,,._"=------__l
300
-
--0--
+-__________~L---~~--------------~ _
300PF
200 PF
100PF
-+-50PF
200 +-----~~~~~--~~--~----------~ ~ NOLOAD
100
OGNDO
INTERNAL TTL GROUND
0
IGNDOl
0
40
20
aD
60
100
120
FREQUENCY,
MHZ
10H ECl DC Characteristics: VCCT=5.0 V± 10%; VEE = -5.2 V ±5%
25'C
D'C
Symbol
Characteristic
IIH
IlL
Input HIGH Current
Input LOW Current
1.5
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
-1170
-1950
max
min
min
85'C
max
225
max
Unit
145
~A
-720
-1445
mV
mV
145
1.0
-840
-1480
min
1.0
-1130
-1950
-810
-1480
Condition
~
-1060
-1950
100H ECl DC Characteristics: VCCT = 5.0 V ± 10%; VEE = -4.2 V to -5.5 V
DOC
Symbol
Characteristic
IIH
IlL
Input HIGH Current
Input LOW Current
1.5
VIH
VIL
Input HIGH Voltage
Input lOW Voltage
-1165
-1810
MECLData
DL122-Rev6
min
25'C
max
min
225
85°C
max
145
-1165
-1810
2-153
max
Unit
145
~
~
-880
-1475
mV
mV
1.0
1.0
-880
-1475
min
-880
-1475
-1165
-1810
Condition
MOTOROLA
MC10H660 MC100H660
AC TEST SET-UP
CL=100pF
The MC10H/100 H660 ECl-TTl DRAM Address Driver
The Me 1OH/1 OOH660 was designed for use in high capacity,
highly interleaved DRAM memory boards, that directly interface
to a high speed, pipelined EeL bus interface, where new
operations may be initiated to the board at a 50 MHz rate ( e.g.
bipolar RiSe systems).
The following briefly discusses the major design features of
the part over existing semiconductor devices traditionally
used in interfacing DRAMs in high performance system
environments.
1. ECL Translator
High performance memory systems of the past that were
interfaced to EeL buses had to rely on separate EeL
translators and DRAM drivers to interface to large DRAM
arrays, which is acceptable if the module is not highly
interleaved and the bus cycle time is comparable to the DRAM
access time. This becomes inadequate as the cycle time ofthe
interface becomes significantly faster than the address timing
requirements of the RAM, and as the degree of internal board
interleaving increases. These higher performance demands
require that the internal address and control signals
propagated to the DRAM drivers be implemented in EeL, thus
requiring the integration of the driver and translator functions.
Integration of the translator/drive function also reduces
access latency, as well as keeping DRAM timing parameters
from being violated, due to the excessive delays encountered
with separate parts.
2. MOS Drive Capacity
Outputs are specifically designed for driving large numbers
of DRAMs ( '" 300 pF), which reduce the number of parts and
power requirements needed per board. Output voltage levels
are designed specifically for driving DRAM inputs. No EeL
MOTOROLA
translator parts on the market today provide the designer with
this drive capability as well as the flexibility to vary the number
of DRAMs that are driven by the part.
3. Transparent Latch
The latch is added to provide the capability for a memory
controller to propagate new addresses to different banks
without having to wait for the address timing constraints to be
satisfied from a previous memory operation. For system
implementations where this is acceptable, the user has the
capability to keep the latch open, thus having the part act as
an address translatorlbuffer, with minimal performance impact
due to the additional propagation delay incurred from the
internal latch. The latch is controlled within an already existing
DRAM timing signal.
4. 1:2 Output Fanout
This function is useful in that it reduces input loading from
the controller by a factor of two, thus significantly improving
board etch propagation delays from the controller to the large
number of translators, without the addition of EeL glue logic
parts to reduce the loading. In large memory boards, so many
translators are needed that this type of organization is not a
handicap.
5. Low Skew, Low Propagation Delay
Low skew of the part as well as fast propagation delay
enable faster overall DRAM operation to be attained than is
possible with existing parts.
6. Power and Package Pin Layout
The H660 is specifically designed with additional power and
ground pins to greatly improve simultaneous switching
performance over existing driver parts.
2-154
MECLData
DL122-Rev6
MC10H660 MC100H660
OUTPUT WAVEFORMS
simulated
Example 1. An output load consisting of just CL = 50 pF results in
overshoot at the output Q:
," .. ~./ 0
," '
TIME
Example 2. In a memory system application, use of an external
source resistor is suggested. Simulations run with RS = an and
CL 300pF leads to clean waveforms both at the output, Q, and
at point Qp:
=
OP
/
o
H6600UTPUT
..
'j-:-- ~\
w
C!l
:i
;:!:
~
'\
"\ -----"'
j'
17
-2
o
~
0 ..... ~:/
,I
'\
•
.,.
,
1.'~Op
'\
,
'(
I
\
25
"'"--
50
D
75
TIME
MECL Data
DL122-Rev6
2-155
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Differential ECL
Bus/TTL Bus Transceiver
MC10H680
MC100H680
The MC10H/100H680 is a dual supply 4-bit differential ECl bus to TTL
bus transceiver. It is designed to allow the system designer to no longer be
limited in bus speed associated with standard TTL busses. Using a
differential ECl Bus will increase the frequency of operation and increase
noise immunity.
Both the TTL and the ECL ports are capable of driving a bus. The ECl
outputs have the ability to drive 25 n, allowing both ends of the bus line to be
terminated in the characteristic impedance of 50 n. The TTL outputs are
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly
capacitive loads.
The ECl output levels are VOH approximately equal to -1.0 V and Val
cutoff equal to -2.0 V (VTT). When the ECl ports are disabled both EIOx and
EIOxB go to the Val cutoff level. The ECl input receivers have special
circuitry which detects this disabled condition, prevents oscillation, and
forces the TTL output to the low state. The noise margin in this disabled state
is greater than 600 mV. Multiple ECl VCCO pins are utilized to minimize
switching noise.
The TTL ports have standard levels. The TTL input receivers have PNP
input devices to significantly reduce loading. Multiple TTL power and ground
pins are utilized to minimize switching noise.
The control pins (EDIR and ECEB) of the 10H version is compatible with
MECl 10H ECl logic levels. The control pins of the 100H version are
compatible with 100K levels.
•
·•
·•
Differential ECl Bus (25 n) I/O Ports
High Drive TTL Bus I/O Ports
Extra TTL and ECl Power/Ground Pins to Minimize
Switching Noise
Dual Supply
Direction and Chip Enable Control Pins
Pinout: 28-lead PlCC (Top View)
III
UJ
III
'"
;::
(!)
~
S
(!)
;:!
'"
~
~
()
25
24
23
22
21
20
19
a
W
w
Tl0l
EI03B
GT2
VeC04
VTl
EI03
GTl
VeeE
Tloo
EI02B
TDIR
Vee03
PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
EDIR
4
EI02
<:>
a
iIi
0
8
>
!Xl
<:>
Q
w
W
w
>
§
w
S
()
()
>
III
0
iii
•
FNSUFFIX
PLASTIC PACKAGE
CASE 776-02
23
24
25
26
27
28
9/96
© Motorola, Inc. 1996
2-156
Function
Symbol
GTl
TIOO
TDIA
EDIA
EIOO
VCCOl
EIOOB
VEE
EIOl
VCC02
EIOIB
EI02
VCC03
EI02B
VCCE
EI03
VCC04
EI03B
ECEB
TCEB
TI03
GT4
VT2
GT3
TI02
TIOl
GT2
VTl
REV6
TTL Ground 1
TTL I/O Bit 0
TTL Direction Control
ECl Direction Control
ECl 1/0 Bit 0
ECl VCC 1 (OV) - Outputs
ECl 1/0 Bit 0 Bar
ECl Supply (-5.21-4.5V)
ECl VOBit 1
ECl VCC 2 (OV) - Outputs
ECl 1/0 Bit 1 Bar
ECl 1/0 Bit2
ECl VCC 3 (OV) - Outputs
ECl 1/0 Bit 2 Bar
EClVCC (OV)
ECl 1/0 Bit 3
ECl VCC 4 (OV) - Outputs
ECl 1/0 Bit 3 Bar
ECl Chip Enable Bar Control
TTL Chip Enable Bar Control
TTL 1/0 Bit 3
TTL Ground 4
TTL Supply 2 (5V)
TTL Ground 3
TTL 1/0 Bit2
TTL VO Bit 1
TTL Ground 2
TTL Supply 1 (5V)
®
MOTOROLA
MC10H680 MC100H680
TRUTH TABLE
TDIR - Direction Control TTL levels
EDIR - Direction Control ECl levels
TCEB - Chip Enable Bar Control TTL levels
ECEB - Chip Enable Bar Control ECl levels
TIN - TTL Input
TOUT - TTL Output
EIN - ECl Input
EINB - ECl Input Bar
EOUT - ECl Output
EOUTB - ECl Output Bar
H-HIGH
l-lOW
lC - ECl low Cutoff (VTT = -2.0 V)
X - Don't Care
Z - High Impedance
ECEB
TCEB
EDIR
TDIR
EIN
EINB
EOUT
EOUTB
TIN
TOUT
H
X
X
X
X
X
lC
lC
X
Z
ECl and TTL Outputs Disabled
COMMENTS
X
H
X
X
X
X
lC
lC
X
Z
ECl and TTL Outputs Disabled
l
l
H
X
H
lC
NA
H
ECl to TTL Direction
l
l
H
X
lC
H
NA
l
ECl to TTL Direction
l
l
H
X
lC
lC
NA
l
ECl to TTL Direction (l-l Cond.)
l
l
X
H
H
lC
NA
H
ECl to TTL Direction
l
l
X
H
lC
H
NA
l
ECl to TTL Direction
l
l
X
H
lC
lC
NA
l
l
l
l
l
NA
NA
H
lC
H
TTL to ECl Direction
l
l
l
l
NA
NA
lC
H
l
TTL to ECl Direction
ECl to TTL Direction (l-l Cond.)
ABSOLUTE RATINGS (Do not exceed):
Power Supply Voltage
VEE (ECl)
-B.O to 0
Power Supply Voltage
VCCT(TTl)
-0.5 to +7.0
Vdc
VI (ECl)
VI (TTL)
0.0 to VEE
-0.5 to +7.0
Vdc
Input Voltage
Vdc
Disabled 3-State Output
Vout{TTl)
0.0 to VCCT
Vdc
Output Source Current Ccntinuous
lout (ECl)
100
mAdc
Output Source Current Surge
lout (ECl)
200
mAdc
Tstg
-65 to 150
'C
Tamb
0.0 to +75
'C
Storage Temperature
Operating Temperature
MEClData
DL122-Rev6
2-157
MOTOROLA
MC10H680 MC100H680
ECl DC CHARACTERISTICS: VCCT = +5.0 V ±10%, VEE = -5.2 ±5% (10H Version); VEE = -4.2 V to -5.5 V (100H Version)
TA=25°C
TA=O°C
Test
Symbol
Parameter
lEE
Supply Current/ECl
IINH
Input HIGH Current
IINl
Input lOW Current
VOH
VOL
Output HIGH Voltage
Output lOW Voltage
Min
Max
Min
-110
TA=75°C
Min
-110
225
145
0.5
-1100
-2.1
Max
0.5
-840
-2.03
-1100
-2.1
Max
Unit
-110
mA
145
I1A
I1A
-735
-2.03
mV
V
0.3
-810
-2.03
-1100
-2.1
Condition
25Qto-2.1 V
CONTROL INPUTS ONLY
10H ECl DC CHARACTERISTICS: VCCT = +5.0 ±10%, VEE = -5.2 ±5%
TA=O°C
Test
Symbol
Parameter
Input HIGH Voltage
Input lOW Voltage
VIH
Vil
TA = 25°C
TA = 75°C
Min
Max
Min
Max
Min
Max
Unit
-1170
-1950
-840
-1480
-1130
-1950
-810
-1480
-1070
-1950
-735
-1450
mV
Condition
CONTROL INPUTS ONLY
100H ECl DC CHARACTERISTICS: VCCT = +5.0 ±10%, VEE = -4.2 V to -5.5 V
TA=O°C
Test
Symbol
Parameter
Input HIGH Voltage
Input lOW Voltage
VIH
Vil
TA=25°C
TA=75°C
Min
Max
Min
Max
Min
Max
Unit
-1165
-1810
-880
-1475
-1165
-1810
-880
-1475
-1165
-1810
-880
-1475
mV
Condition
TIL DC CHARACTERISTICS: VCCT = +5.0 V ±10%, VEE = -5.2 ±5% (10H Version); VEE = -4.2 V to -5.5 V (100H Version)
. TA=O°C
Test
Symbol
Parameter
VIH
Vil
Standard Input
Standard Input
ViK
Input Clamp
VOH
Output HIGH Voltage
Output HIGH Voltage
Min
TA=25°C
Max
Min
2.0
Max
2.0
TA = 75°C
Min
Max
2.0
0.8
0.8
0.8
-1.2
-1.2
2.5
2.0
Condition
Vdc
-1.2
2.5
2.0
Unit
Vdc
V
2.5
2.0
IIN=-18mA
10H =-3.0mA
IOH=-15mA
VOL
Output lOW Voltage
0.55
0.55
0.55
V
IOl=48mA
IIH"
TTL (Input HIGH)
TTL (Input HIGH)
20
100
20
100
20
100
I1A
Vin=2.7V
Vin =7.0V
Ill"
TTL (Input lOW)
-0.6
-0.6
"':0.6
mA
Vin = 0.5V
ICCl
Supply Current
75
75
75
mA
ICCH
Supply Current
70
70
70
mA
ICCZ
Supply Current
70
70
70
mA
lOS
Output Short Circuit Current
-225
mA
-100
-225
-100
-225
-100
VOUT=OV
• NOTE: TTL Control Inputs only
TIL
VO
DC CHARACTERISTICS ONLY
IIH/IOZH
IILlIOZl
TA = 25°C
TA=O°C
Test
Symbol
Parameter
Output Disable
Current
MOTOROLA
Min
Max
70
200
2-158
Min
Max
70
200
TA = 75°C
Min
Max
Unit
70
200
I1A
Condition
VOUT=2.7V
VOUT=0.5V
MEClData
Dll22-Rev6
MC10H680 MC100H680
ECl TO TTL DIRECTION I AC TEST
TA=O"C
Test
Symbol
TA=25"C
TA=75"C
Parameter
Waveforms
Min
Max
Min
Max
Min
Max
Unit
IplH
IpHl
Propagalion Delay
100uiput
2,4
2.7
4.8
2.7
4.8
2.7
4.8
ns
Cl = 50 pF
Condition
IPZH
IpZl
ECEB to OUlput
Enable Time
2,5,6
3.5
3.5
6.5
6.0
3.5
3.5
6.5
6.0
3.7
3.7
6.7
6.4
ns
Cl=50pF
IpHZ
IpLZ
ECEB to OUlpul
Disable Time
2,5,6
3.5
3.5
8.6
6.5
3.5
3.5
8.6
6.5
3.7
3.7
8.8
7.3
ns
Cl = 50 pF
tpZH
tpZl
TCEB to Output
Enable Time
2,5,6
5.7
5.4
7.7
6.9
5.7
5.4
7.7
6.9
5.9
5.9
7.9
7.4
ns
Cl = 50 pF
tpHZ
tpLZ
TCEB to Output
Disable Time
2,5,6
4.0
4.0
8.5
5.8
4.1
4.2
8.4
6.0
4.2
4.7
8.3
6.5
ns
Cl= 50 pF
Irllf
1.0 to 2.0 Vdc
3
0.4
1.5
0.4
1.5
0.4
1.5
ns
Cl = 50 pF
Parameter
Waveforms
Min
Max
Min
Max
Min
Max
Unit
Condition
tplH
tpHl
Propagation Delay
to Outpul'
1,4
1.8
4.6
1.8
4.6
2.0
4.9
ns
25010-2.0V
tplH
IpHl
ECEB
10 Output
1,4
2.9
5.1
3.0
5.2
3.4
5.7
ns
25010-2.0 V
IplH
tpHl
TCEB
to Output
1,4
3.4
6.3
3.5
6.6
3.8
7.4
ns
25010-2.0 V
trllf
Output Rise/Fall
Time 20%-80%
1,3
1.0
3.4
1.0
3.4
1.0
3.4
ns
250 to-2.0 V
TTL TO ECl DIRECTION I AC TEST
TA=O"C
Test
Symbol
MEClData
Dl122-Rev6
TA = 25"C
2-159
TA=75"C
MOTOROLA
MC10H680 MC100H680
BLOCK DIAGRAM
CONTROL INPUTS
TDIR
EDIR
- - VCCE
TCE
ECE
- - VEE
GND1--
- - VCC01
.......:----If-----4t--- EIOO
TIOO---4HH
....-c:f--+...- - I - - - EIOO
VCCT1 - -
GND2--
TI01 ---4Hf-I
- - VCC02
.........,..---+--.....- -
EI01
EI01
GND3--
- - VCC03
.........~--II-----4t--- EI02
TI02---4HH
/C>-+"'--I--- EI02
VCCT2 - -
GND4--
TI03---4HH
MOTOROLA
- - VCC04
.........:::------41~- EI03
....-()--....- - f - - - EI03
2-160
MECLDala
DL122-Rev6
MC10H680 MC100H680
SWITCHING CIRCUIT AND WAVEFORMS
VCC&VCCO
ECl
TTL
USE 0.1 JlF CAPACITORS
FOR DECOUPLING.
L:V
DEVICE
UNDER
TEST
I
O:EN
ALL
OTHERS
IPZL,IPLZ
O,C
DEVICE
UNDER
TEST
Rl
soon
R2
soon
USE OSCILLOSCOPE
INTERNAL 50 n LOAD
FOR TERMINATION.
CHA
CH B
OSCILLOSCOPE
Figure 1. Switching Circuit ECl
ECLlTTl
Figure 2.
ECLlTTl
50%/1.5 V
VIN
VOUT
TRISE
TFALL
VOUT
Figure 3. WAVEFORMS: Rise and Fall Times
TTL
Figure 4. Propagation Delay - Single Ended
TTL
VE
VE
~I_~PZL
VOUT
Y
_ _....-:VOL
0.3vf
Figure 5. 3-State Output low Enable and Disable
Times
MECLData
DL122- Rev 6
Figure 6. 3-5tate Output High Enable and Disable
Times
2-161
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex ECL/TTL Transceiver
with Latches
MC10H681
MC100H681
The MC10/100H681 is a dual supply Hex ECUTTl transceiver with
latches in both directions. ECl controlled Direction and Chip Enable Bar
pins. There are two latch Enable pins, one for each direction.
The ECl outputs are single ended and drive 50 n. The TTL outputs are
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly
capacitive loads. The high driving ability of the TTL outputs make the device
ideal for bussing applications.
The ECl output levels are standard VOH and Val cutoff equal to -2.0 V
(VTT). When the ECl ports are disabled the outputs go to the Val cutoff
level. Multiple ECl VCCO pins are utilized to minimize switching noise.
The TTL ports have standard levels. The TTL input receivers have PNP
input devices to significantly reduce loading. Multiple TTL power and ground
pins are utilized to minimize switching noise.
The 10H version is compatible with MECl 10H ECl logic levels. The
100H version is compatible with 100K levels.
•
•
•
•
•
•
Separate latch Enable Controls for each Direction
ECl Single Ended 50 n I/O Port
High Drive TTL I/O Ports
Extra TTL and ECl Power/Ground Pins to Minimize
Switching Noise
Dual Supply
Direction and Chip Enable Control Pins
Pinout: 28-lead PlCC (Top View)
...
0
'"
>=
>
t5 >=0
25
24
23
22
on
0
>
IC!l
>=
21
20
19
TI02
18
EI05
VT
17
Veeo
GT
16
EI04
TI01
15
VeeE
VT
14
EI03
GT
13
Veeo
12
EI02
TIOO
7
a:
i5
In
w
U
ti:i
W
...J
w
IW
...J
w
W
>
10
11
0
aiii
0
iii
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FNSUFFIX
PLASTIC PACKAGE
CASE77EHl2
Symbol
TI01
VT
GT
TIOO
DIR
CEB
lEET
lETE
VEE
EIOO
EI01
EI02
VCCO
EI03
VCCE
EI04
VCCO
EI05
TIOS
GT
VT
TI04
GT
VT
TI03
TI02
VT
GT
9/96
© Motorola, Inc. 1996
2-162
REV 2
Description
TIL I/O BIT 1
TIL VCC (5.0 V)
TIlGND(OV)
TIL I/O Bit a
Direction Control (ECl)
Chip Enable Bar Control (ECl)
Latch Enable ECl-TIl Control (ECl)
latch Enable TIl-ECl Control (ECL)
ECl Supply (-5.2/-4.5 V)
ECll/OBITO
ECl I/O BIT 1
ECl I/O BIT2
ECl VCC (0 V) - Outputs
TIL I/O BIT 3
ECl VCC (0 V)
ECl I/O BIT 4
ECl VCC (0 V) - Outputs
ECl I/O BIT5
TILl/OBITS
TIlGND (0 V)
TIL VCC (5.0 V)
TIL I/O BIT4
TIlGND(OV)
TIL VCC (5.0 V)
TIL I/O BIT3
TIL I/O BIT2
TIL VCC (5.0 V)
TIlVCC(OV)
®
MOTOROLA
MC10H681 MC100H681
DIR
CE
Q
o
EIO
LE-TE
TIO
o
Q
LE
LE-ET
TRUTH TABLE
CEe
DIR
LEET
LETE
EOUT
H
X
X
X
Z
Z
L
H
L
L
Z
EIN
L
H
H
L
Z
00
L
L
L
L
TIN
Z
L
L
L
H
00
Z
MECLData
DU22-Rev6
TOUT
• Hex
• Bi-Directional
• ECLlTTl Translation
• Dual Supply
• ECl Outputs, 50 Ohm S.E., VOH/Cutoff
• TTL Outputs, 48 mA Sink, 15 mA Source
• Multi Power and Ground Pins
• Separate lE Controls
2-163
MOTOROLA
MC10H681 MC100H681
ECl DC CHARACTERISTICS: VCCT = +5.0 V ±10%, VEE = -5.2 ±5% (10H Version); VEE = -4.2 V to -5.5 V (100H Version)
TA=O'C
Test
Symbol
Parameter
TA=25'C
TA=75'C
Min
Max
Min
Max
Min
Max
Unit
-
-113
-113
-
-113
mA
Condition
lEE
Supply Current/ECL
IINH
Input HIGH Current
-
225
-
145
-
145
IINL
Input LOW Current
0.5
-
0.5
-
0.3
-
IlA
IlA
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
-1020
-2.1
-840
-2.03
--980
-2.1
-810
-2.03
-920
-2.1
-735
-2.03
mV
V
500to-2.1 V
Condition
10H ECl DC CHARACTERISTICS: VCCT = +5.0 ±10%, VEE = -5.2 ±5%
TA=O'C
Test
Symbol
VIH
VIL
Parameter
Input HIGH Voltage
input LOW Voltage
TA = 25°C
TA=75'C
Min
Max
Min
Max
Min"
Max
Unit
-1170
-1950
-840
-1480
-1130
-1950
-810
-1480
-1070
-1950
-735
-1450
mV
100H ECl DC CHARACTERISTICS: VCCT = +5.0 ±10%, VEE = -4.2 V to -5.5 V
TA=O'C
Test
Symbol
VIH
VIL
Parameter
input HIGH Voltage
Input LOW Voltage
TA = 25°C
TA=75'C
Min
Max
Min
Max
Min
Max
Unit
-1165
-1810
-880
-1475
-1165
-1810
-880
-1475
-1165
-1810
-880
-1475
mV
Condition
ABSOLUTE RATINGS (Do not exceed):
Power Supply Voltage
VEE (ECL)
-8.0 to 0
Vdc
Power Supply Voltage
VCCT(TIL)
-0.5 to +7.0
Vdc
VI (ECL)
VI (TIL)
0.0 to VEE
-0.5 to +7.0
Vdc
Disabled 3-State Output
Vout(TIL)
0.0 to VCCT
Vdc
Output Source Current Continuous
lout (ECL)
100
mAde
Output Source Current Surge
Input Voltage
lout (ECL)
200
mAde
Storage Temperature
Tstg
-65 to 150
'c
Operating Temperature
Tamb
0.0 to + 75
'C
MOTOROLA
2-164
MECL Data
DL122-Rev6
MC10H681 MC100H681
TTL DC CHARACTERISTICS: VCCT = +5.0 V ±10%, VEE = -5.2 -+5% (10H Version); VEE = -4.2 V to -5.5 V (100H Version)
TA= DoC
Test
Symbol
Parameter
Min
TA = 25°C
Max
-
TA = 75°C
Min
Max
Min
Max
Unit
2.0
-
2.0
-
Vdc
-1.2
Vdc
-
V
Condition
VIH
VIL
Standard Input
Standard Input
2.0
-
0.8
VIK
Input Clamp
-
-1.2
VOH
Output HIGH Voltage
Output HIGH Voltage
2.5
2.0
-
VOL
Output LOW Voltage
-
0.55
-
0.55
-
0.55
V
IOL=48mA
IIHIIOZH
IILlloZL
Output Disable
Current
70
200
-
70
200
IJA
VOUT=2.7V
VOUT=0.5V
Supply Current
-
70
200
ICCL
-
63
63
rnA
ICCH
Supply Current
-
63
63
63
rnA
ICCZ
Supply Current
-
63
-
63
-
63
rnA
lOS
Output Short Circuit Current
-225
-100
-225
-100
-225
rnA
-
2.5
2.0
-
63
-100
0.8
-1.2
-
-
-
2.5
2.0
-
0.8
-
IIN=-18mA
IOH =-3.0 rnA
IOH=-15mA
VOUT=OV
ECl TO TTL DIRECTION AC CHARACTERISTICS
TA = DoC
Test
Symbol
TA=25°C
TA=75°C
Max
Unit
tpLH
tpHL
Propagation
Deiay to Output
4.0
7.8
4.0
7.8
4.2
8.0
ns
CL=50pF
tpLH
tpHL
LEETto
Output
5.5
5.5
B.3
7.6
5.5
5.5
8.3
7.6
5.7
5.B
8.5
B.O
ns
CL=50pF
tPZH
tpZL
CEB to Output
Enable Time
5.5
5.3
8.3
8.3
5.5
5.3
8.3
8.3
4.7
5.4
8.5
8.4
ns
CL= 50pF
tpHZ
tpLZ
CEB to Output
Disable Time
3.5
3.5
7.2
5.3
3.5
3.5
7.2
5.3
3.7
4.1
7.3
5.8
ns
CL= 50 pF
t,.rt,
1.0 Vdc to 2.0 Vdc
0.4
2.2
0.4
2.2
0.4
2.2
ns
CL=50pF
Parameter
Min
Max
Min
Max
Min
Condition
TTL TO ECl DIRECTION AC CHARACTERiSTICS
TA = 25°C
TA=O°C
Test
Symbol
Parameter
TA=75°C
Max
Unit
Condition
tpLH
tpHL
Propagation
Delay to Output
1.9
3.9
1.9
3.9
2.2
4.4
ns
50Qto-2.0V
tpHL
tpLH
CEBto
Output
2.2
2.3
4.0
4.6
2.2
2.3
4.0
4.6
2.5
2.7
4.3
5.0
ns
50 Q to-2.0 V
tpHL
tpLH
LETEto
Output
2.4
3.9
2.4
3.9
2.7
4.3
ns
50Qto-2.0V
trlt,
Output Rise/Fall
Time 20%-80%
0.4
2.2
0.4
2.2
0.4
2.2
ns
50Qto-2.0V
MECLData
DL122-Rev6
Min
Max
Min
Max
Min
2-165
MOTOROLA
MC10H681 MC100H681
TEST CIRCUITS AND WAVEFORMS
ECl
TTL
USE O.lIlF CAPACITORS
FOR DECOUPLING.
I
O:EN
DEVICE
UNDER
TEST
OUT
ALL
OTHERS
IPZL,lpLZ
O,C
DEVICE
UNDER
TEST
R1
soon
R2
soon
USE OSCILLOSCOPE
INTERNAL 50 n LOAO
FOR TERMINATION.
CHB
OSCILLOSCOPE
Figure 2. Test Circuit TTL
Figure 1. Test Circuit ECl
ECLlTTl
ECLlTTl
50%/1.5 V
VIN
TFALL
VOUT
Figure 4. Propagation Delay -
Figure 3. Rise and Fall Times
Single Ended
TTL
TTL
VE
VE
VE
I--I~
~I ._~PZL
~
VOUT
VOL
VO~1.5V
0.3Vf
Figure 5. 3-State Output low Enable
and Disable Times
MOTOROLA
I
Figure 6. 3-State Output High Enable
and Disable Times
2-166
MECLData
DL122-Rev6
MECL Data
MECL 10K
MECLData
DL122-Rev6
3-1
MOTOROLA
[3J
MECL10K
INTEGRATED CIRCUITS
MC10,1 00/1 0,200 Series
-3010 85°C
Function Selection - (-30° to +8So C)
Funcllon
Device
Function
Case
NOR Gates
Quad 2-lnput Gate
Triple 4-3-3 Input Gate
Dual3-lnput 3-0utput Gate
Dual3-lnput 3-0utput Gate
MC10l02
MC10l06
MC10lli
MC10211
Dual 0 Master Slave Flip-Flop
Dual J-K Master Slave Flip-Rap
Quad Latch
Hex 0 Master Slave Flip-Flop
Hex 0 Common Reset Flip-Flop
Dual 0 Master Slave Flip-Flop
Quad Latch
Quint Latch
Quad/Common Clock Latch
620,648,775
620,648,775
620,648
620, 648, 775
OR Gates
Quad 2-lnput Gate
Dual 3-lnput 3-0utput Gate
Dual3-lnput 3-0utput Gate
AND Gates
18-lnput Encoder
MC10l0l
MC10l05
MC10l09
MC10212
MC10l07
MC10113
MC10117
620, 648, 775
620,648,775
620, 648, 775
648,775
620, 648, 775
620, 648, 775
620,648,775
MC10121
620, 648, 775
Binary to 1-8 (Low)
Binary to 1-8 (High)
Dual Binary to 1-4 (Low)
Dual Binary to 1-4 (High)
Triple Line Receiver
Decade
Biquinary
Binary Down Counter
MC10161
MC10162
MC10171
MC10172
620, 648, 775
620, 648, 775
620, 648, 775
620, 648, 775
MC10136
MC10137
MC10138
MC10154
MC10178
620, 648, 775
620,648
620, 648, 775
620,648
620, 648, 775
Binary
MC10141
620, 648, 775
MC10198
620, 648, 775
MC10134
MC10158
MC10159
MC10164
MC10173
MC10174
620,
620,
620,
620,
620,
620,
ArithmetiC Functions
MC10114
MC10115
MC10116
MC10123
MC10129
MC10192
MC10216
620,648,775
620,648,775
620,648,775
620, 648, 775
620
620,648,775
620,648,775
5-Blt Magnitude Comparator
4-Bit Arithmetic Function Gen.
Shift Register
14-Blt Universal
Multivlbrators
IMonostable Multlvibrators
Multiplexer
Translators
Dual with Latch
Quad 2-lnput!Noninverting
Quad 2-lnputllnverting
8-Line
Quad 2-lnput!Latch
Dual 4-1
Quad TIL-MECL
Quad MECL-TIL
MOTOROLA
620,648
Counters
Hexadecimal
Une DriversILine Receivers
Quad Bus Driver
MC10165
12-Bit Parity Generator-Checker
9 + 2 Bit Parity
Hex BufferlEnable
Hex Inverter/Enable
Hex Inverter/Buffer
Quad Bus Receiver
620, 648, 775
620, 648, 775
620, 648, 775
620, 648, 775
620, 648, 775
620, 648, 775
620,648
620, 648, 775
648
Parity Generator/Checkers
BuffersJlnverters
Triple Bus Driver
MC10131
MC10135
MC10153
MC10176
MC10186
MC10231
MC10133
MC10175
MC10168
Decoders
Complex Gates
Triple Une Receiver
Quad Une Receiver
Triple Line Receiver
Case
Encoders
Quad 2-lnput Gate
Hex Gate
Quad ORiNOR Gate
Triple 2-3-2 Input ORINOR Gate
Dual 4-5 Input ORiNOR Gate
Dual3-lnput 3-0utput ORiNOR Gate
Triple 2-lnput Exclusive ORINOR Gate
Quad 2-lnput Exclusive ORINOR Gate
Dual2-Wide 2-3 Input OR-AND/OR-AND
INVERT
4-Wide 3-lnput OR-AND/OR-AND
INVERT
Device
Flip-Flop/latches
3-2
648, 775
648, 775
648, 775
648, 775
648, 775
648, 775
MECL Data
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad OR/NOR Gate
MC10101
The MC1 01 01 is a quad 2-input ORINOR gate with one input from each gate
common to pin 12.
PD = 25 mW typ/gate (No Load)
tpd = 2.0 ns typ
t r, tf = 2.0 ns typ (20%-80%)
-•
LOGIC DIAGRAM
4----~r-~~------
10--~~~~~-------
14
13--~~~~~-------
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
FN SUFFIX
PLCC
CASE 77S-Q2
DIP
PIN ASSIGNMENT
11
12
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
15
--+-..-,L-....LI--------
VCC1
VCC1 =PIN 1
VCC2 = PIN 16
VEE = PINS
VCC2
AOUT
DOUT
BOUT
COUT
AoUT
DIN
COMMON
INPUT
BoUT
COUT
AIN
BIN
VEE
CIN
DOUT
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola, Inc. 1996
REVS
®
MOTOROLA
[aJ
MC10101
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
29
linH
4
12
425
850
linL
4
-30°C
Min
12
0.5
0.5
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
20
26
29
mAde
265
535
265
535
!lAde
0.5
0.5
Min
0.3
0.3
!lAde
Output Voltage
Logic 1
VOH
5
5
2
2
-1.060
-1.060
-1.060
-1.060
-0.890
-hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-34
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple Line Receiver
MC10114
The MC1 0114 is a triple line receiver designed for use in sensing differential
signals over long lines. An active current source and translated emitter follower
inputs provide the line receiver with a common mode noise rejection limit of one
volt in either the positive or the negative direction. This allows a large amount of
common mode noise immunity for extra long lines.
Another feature of the MC1 0114 is that the OR outputs go to a logic low level
whenever the inputs are left floating. The outputs are each capable of driving 50
ohm transmission lines.
This device is useful in high speed central processors, minicomputers,
peripheral controllers, digital communication systems, testing and instrumentation systems. The MC10114 can also be used for MOS to MECL interfacing
and it is ideal as a sense amplifier for MOS RAM's.
A VBB reference is provided which is useful in making the MC1 0114 a Schmit
trigger, allowing single-ended driving of the inputs, or other applications where
a stable reference voltage is necessary. See MECL Design Handbook (HB205)
pages 226 and 228.
PD =
tpd =
tpd =
t r, tf=
-•
145 mW typ/pkg
2.4 ns typ (Single Ended Input)
2.0 ns typ (Differential Input)
2.1 ns typ (20% to 80%)
4
9
10
12
13
=:tt=
=:tt=
~
PSUFFIX
PLASTIC PACKAGE
CASE 64S-QS
FNSUFFlX
PLCC
CASE 775-{)2
DIP
PIN ASSIGNMENT
LOGIC DIAGRAM
5
LSUFFIX
CERAMIC PACKAGE
CASE 62(}"'10
VCC1
VCC2
AOUT
COUT
AOUT
COUT
AIN
CIN
AIN
CIN
BOUT
VBB
BOUT
BIN
VEE
BIN
14
15
11
Pin asSignment is for Dual-in-line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
VBB'
VCCpPIN 1
VCC2=PIN 16
VEE = PIN 8
'Vss to be used to supply bias to the MC10114 only and bypassed (when used) with
0.01 ~F to 0.1 ~F capacitor to ground (0 V). VSS can source < 1.0 rnA.
When the input pin with the bubble goes positive, its respective output pin with
bubble goes positive.
3193
© Motorola, Inc. 1996
3-35
REV 5
®
MOTOROLA
MC10114
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
-30'C
Min
+25'C
Max
Min
39
+85'C
Typ
Max
28
35
Min
Max
Unit
39
mAde
linH
4
70
45
45
!!Ade
ICBO
4
1.5
1.0
1.0
!!Ade
Output Voltage
Logic 1
VOH
2
3
-1.060
-1.0S0
-{I.890
-{I.890
-{I.9S0
-{I.9S0
-{I.810
-{I.81 0
-{I.890
-0.890
-{I.700
-{I.700
Vde
Output Voltage
Logic 0
VOL
2
3
-1.890
-1.890
-1.S75
-1.S75
-1.850
-1.850
-1.S50
-1.S50
-1.825
-1.825
-1.S15
-1.615
Vde
Threshold Voltage
Logic 1
VOHA
2
3
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
3
Reference Voltage
VBB
11
-1.420
-1.280
-1.350
-1.230
Common Mode Rejection
Test
VOH
2
3
-1.060
-1.060
-{I.890
-{I.890
-{I.960
-{I.960
-0.810
-{I.81 0
VOL
2
3
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
Min
Max
Min
t4+2+
14-2t4+314-3+
2
2
3
3
1.0
1.0
1.0
1.0
4.4
4.4
4.4
4.4
1.0
1.0
1.0
1.0
(500 Load)
Switching Times
Propagation Delay
-{I.9OO
-{I.980
-{I.91 0
-{I.91 0
-1.630
-1.S30
-1.S55
-1.655
Vde
-1.595
-1.595
Vde
-1.295
-1.150
Vde
-{I.890
-{I.890
-{I.700
-{I.700
Vde
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vde
Typ
Max
Min
Max
ns
2.4
2.4
2.4
2.4
4.0
4.0
4.0
4.0
0.9
0.9
0.9
0.9
4.3
4.3
4.3
4.3
Rise Time
(20 to 80%)
t2+
t3+
2
3
1.5
1.5
3.8
3.8
1.5
1.5
2.1
2.1
3.5
3.5
1.5
1.5
3.7
3.7
Fall Time
(20 to 80%)
t2t3-
2
3
1.5
1.5
3.8
3.8
1.5
1.5
2.1
2.1
3.5
3.5
1.5
1.5
3.7
3.7
MOTOROLA
3-36
MECL Data
DL122-RevS
MC10114
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHmax
VILmln
VIHAmin
VILAmax
-30'C
-0.890
-1.890
-1.205
-1.500
Symbol
Power Supply Drain Current
Input Current
+25'C
...(J.81 0
-1.850
-1.105
-1.475
+85'C
...(J.700
-1.825
-1.035
-1.440
Pin
Under
Test
IE
8
linH
4
VBB
From
Pin
11
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
4
VBe
Unit
4,9,12
5,10,13
mAdc
9,12
5,10,13
!lAdc
9,12
5,10,13
!lAde
VILmin
VIHAmin
VILAmax
linL
4
Output Voltage
Logic 1
VOH
2
3
4
9,12
9,12
4
5,10,13
5,10,13
Vde
Output Voltage
Logic 0
VOL
2
3
9,12
4
4
9,12
5,10,13
5,10,13
Vde
Threshold Voltage
Logic 1
VOHA
2
3
5,10,13
5,10,13
Vde
9,12
5,10,13
5,10,13
Vdc
5,10,13
Vdc
Threshold Voltage
Logie 0
VOLA
2
3
9,12
4
4
9,12
4
9,12
4
Reference Voltage
VBS
11
Common Mode Rejection Test
VOH
2
3
Vdc
VOL
2
3
Vdc
Pulse In
Pulse Out
t4+2+
t4-214+314-3+
2
2
3
3
4
4
4
4
2
2
3
3
5,10,13
5,10,13
5,10,13
5,10,13
Switching Times
(50nLoad)
Propagation Delay
Rise Time
(20 to 80%)
t2+
t3+
2
3
4
4
2
3
5,10,13
5,10,13
Fall Time
(20 to 80%)
t2t3-
2
3
4
4
2
3
5,10,13
5,10,13
MECLData
DL122-Rev6
3-37
ns
MOTOROLA
MC10114
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHH*
VILH*
VIHL*
VILL*
VEE
-30'C
+0.110
-0.890
-1.890
-2.890
-5.2
+25'C
+0.190
-0.850
-1.810
-2.850
-5.2
+85'C
+0.300
-0.825
-1.700
-2.825
-5.2
Symbol
Power Supply Drain Current
Input Current
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHH*
VILH*
VIHL*
VILL*
VEE
(VCC)
Gnd
IE
8
8
1,16
linH
4
8
1,16
linL
4
8,4
1,16
Output Voltage
Logic 1
VOH
2
3
8
8
1,16
1,16
Output Voltage
Logic 0
VOL
2
3
8
8
1,16
1,16
Threshold Voltage
Logic 1
VOHA
2
3
8
8
1,16
1,16
Threshold Voltage
Logic 0
VOLA
2
3
8
8
1,16
1,16
Vee
11
8
1,16
VOH
2
3
8
8
1,16
1,16
8
8
1,16
1,16
Reference Voltage
Common Mode Rejection Test
VOL
Switching Times
2
3
4
4
5
5
(50QLoad)
Propagation Delay
5
4
5
4
-3.2 V
+2.0 V
t4+2+
14-2t4+314-3+
2
2
3
3
8
8
8
8
1,16
1,16
1,16
1,16
Rise TIme
(20 to 80%)
t2+
t3+
2
3
8
8
1,16
1,16
Fail Time
(20 to 80%)
t2t3-
2
3
8
8
1,16
1,16
..
* VIHH = Input Logic 1 level shifted positive one volt for common mode rejection tests
VILH = Input Logic 0 level shifted positive one volt for common mode rejection tests
VIHL = Input Logic 1 level shifted negative one volt for common mode rejection tests
VILL = Input Logic 0 level shifted negative one volt for common mode rejection tests
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear !pm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-38
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Line Receiver
The MC10115 is a quad differential amplifier designed for use in sensing
differential signals over long lines. The base bias supply (VSS) is made available
at pin 9 to make the device useful as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the MC10115 with excellent common mode
noise rejection. If any amplifier in a package is not used, one input of that
amplifier must be connected to VSS (pin 9) 'to prevent upsetting the current
source bias network.
MC10115
-,.
•
PD = 110 mW typ/pkg (No Load)
tpd 2.0 ns typ
t r, tf 2.0 ns typ (20%-80%)
=
=
LOGIC DIAGRAM
4
5
7
6
10
11
13
12
~
~
~
~
VCG1
14
15
VCC1 =PIN 1
VCC2 = PIN 16
VEE=PIN B
'VBB to be used to supply bias to the Mel0llS only and bypassed (when used)
with 0.Q1 ~F to 0.1 ~F capacitor to ground (0 V). VBB can source < 1.0 rnA.
When the input pin with the bubble goes positive, the output goes negative.
FN SUFFIX
PLCC
CASE 77!Hl2
VGG2
AOUT
DOUT
BOUT
GOUT
AIN
DIN
AIN
DIN
BIN
GIN
BIN
GIN
VEE
VBB
Pin assignment is for Oual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3193
3-39
PSUFFIX
PLASTIC PACKAGE
CASE 648-{)S
DIP
PIN ASSIGNMENT
VBB'
© Motorola. Inc. 1996
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
REVS
®
MOTOROLA
MC10115
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
IE
8
29
linH
4
150
ICBO
4
1.5
Power Supply Drain Current
Input Current
-30°C
Min
+25°C
Max
Min
+85°C
Max
Unit
29
mAdc
95
95
!lAdc
1.0
1.0
!lAdc
Max
Typ
Min
26
Output Voltage
Logic 1
VOH
2
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
-1.080
Threshold Voltage
Logic 0
VOLA
2
VBB
9
1.420
1.280
-1.350
-1.230
t4-2+
14+2-
2
2
1.0
1.0
3.1
3.1
1.0
1.0
2.9
2.9
Reference Voltage
-0.980
-0.910
-1.655
Vdc
-1.630
-1.595
Vdc
1.295
-1.150
Vdc
1.0
1.0
3.3
3.3
(50Q Load)
Switching TImes
Propagation Delay
ns
Rise TIme
(20 to 80%)
t2+
2
1.1
3.6
1.1
3.3
1.1
3.7
Fall TIme
(20 to 80%)
t2-
2
1.1
3.6
1.1
3.3
1.1
3.7
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature VIHmax
VIHAmln
VILAmax
-30°C
-0.890
-1.890
-1.205
-1.500
+25°C
-0.810
-1.850
-1.105
-1.475
+85°C
-0.700
-1.825
-1.035
-1.440
Symbol
Pin
Under
Test
IE
8
linH
4
VILmln
Vee
VEE
-5.2
From
Pin
9
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED eELOW
Vee
VEE
(Vce)
Gnd
4,7,10,13
5,6,11,12
8
1,16
7,10,13
5,6,11,12
8
1,16
7,10,13
5,6,11,12
8,4
1,16
VIHmax
VILmln
4
VIHAmin
VILAmax
ICBO
4
Output Voltage
Logic 1
VOH
2
7,10,13
4
5,6,11,12
8
1,16
Output Voltage
Logic 0
VOL
2
4
7,10,13
5,6,11,12
8
1,16
Threshold Voltage
Logic 1
VOHA
2
7,10,13
5,6,11,12
8
1,16
Threshold Voltage
Logic 0
VOLA
2
7,10,13
5,6,11,12
8
1,16
VBB
9
5,6,11,12
8
1,16
-3.2 V
+2.0 V
Reference Voltage
Switching Times
(50QLoad)
Propagation Delay
14-2+
14+2-
2
2
4
4
Pulse In
Pulse Out
4
4
2
2
5,6,11,12
5,6,11,12
8
8
1,16
1,16
Rise TIme
(20 to 80%)
t2+
2
4
2
5,6,11,12
8
1,16
Fall TIme
(20 to 80%)
t2-
2
4
2
5,6,11,12
8
1,16
..
..
Each MECL 10,000 senes cIrcuIt has been deSIgned to meet the dc specIfIcatIons shown In the test table, after thennal eqUlllbnum has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear !pm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-40
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple Line Receiver
MC10116
The MC10116 is a triple differential amplifier designed for use in sensing
differential signals over long lines. The base bias supply (VSS) is made available
at pin 11 to make the device useful as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the MC10116 with excellent common mode
noise rejection. If any amplifier in a package is not used, one input of that
amplifier must be connected to VSS (pin 11) to prevent upsetting the current
source bias network.
Complementary outputs are provided to allow driving twisted pair lines, to
enable cascading of several amplifiers in a chain, or simply to provide
complement outputs of the input logic function.
,..
,.
•
=
=
PD 85 mW typ/pkg (No Load)
tpd = 2.0 ns typ
tr, tf 2.0 ns typ (20%-80%)
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 64S-oS
FNSUFFIX
PLCC
CASEnS-02
DIP
PIN ASSIGNMENT
LOGIC DIAGRAM
4~
10~7
12~14
13
I
I.....--
15
11
VBB'
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PINS
VCC1
VCC2
AOUT
COUT
AOUT
COUT
AIN
CIN
AIN
CIN
BOUT
VBB
BOUT
BIN
VEE
BIN
Pin assignment is for Dual-in-Une Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
'VBB to be used to supply bias to the MCIOl16 only and bypassed (when used)
~F to 0.1 ~F capacitor to ground (0 V). VBB can source < 1.0 rnA.
with
om
When the input pin with the bubble goes positive, the output pin with the bubble
goes positive.
3/93
© Motorola, Inc. 1996
3-41
REVS
®
MOTOROI.A
[3J
MC10116
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
23
~O°C
Min
+25°C
Max
Min
+85°C
Typ
Max
17
21
Min
Max
Unit
23
mAdc
linH
4
150
95
95
!JAdc
ICBO
4
1.5
1.0
1.0
!JAdc
Output Voltage
Logic 1
VOH
2
3
-1.060
-1.060
-{).890
-{).890
-{).960
-{).960
-{).81 0
-{).810
-{).890
-{).890
-{).700
-{).700
Vdc
Output Voltage
Logic 0
VOL
2
3
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
3
-1.080
-1.080
Threshold Vo~age
Logic 0
VOLA
2
3
VBB
11
-1.420
-1.280
-1.350
4+2+
4-2t4+34-3+
2
2
3
3
1.0
1.0
1.0
1.0
3.1
3.1
3.1
3.1
1.0
1.0
1.0
1.0
Reference Voltage
Switching Times
-{).91 0
-{).91 0
-{).980
-{).980
-1.655
-1.655
-1.630
-1.630
Vdc
-1.595
-1.595
Vdc
Vdc
-1.230
-1.295
-1.150
2.0
2.0
2.0
2.0
2.9
2.9
2.9
2.9
1.0
1.0
1.0
1.0
3.3
3.3
3.3
3.3
(50nLoad)
Propagation Delay
ns
Rise Time
(20 to 80%)
t2+
t3+
2
3
1.1
1.1
3.6
3.6
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.7
3.7
Fall Time
(20 to 80%)
t2t3-
2
3
1.1
1.1
3.6
3.6
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.7
3.7
MOTOROLA
3-42
MECLData
DL122-Rev6
MC10116
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmln
VIHAmin
VILAmax
-30'C
-0.890
-1.890
-1.205
-1.500
+25'C
-0.810
-1.850
-1.105
-1.475
+B5'C
-0.700
-1.825
-1.035
-1.440
Symbol
Pin
Under
Test
VIHmax
IE
8
linH
4
ICBO
4
Vee
From
Pin
11
VEE
-5.2
-5.2
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED eELOW
Vee
VEE
(VCC)
Gnd
4,9,12
5,10,13
8
1,16
9,12
5,10,13
8
1,16
9,12
5,10,13
8,4
1,16
VILmin
4
VIHAmin
VILAmax
Output Voltage
Logic 1
VOH
2
3
4
9,12
9,12
4
5,10,13
5,10,13
8
8
1,16
1,16
Output Voltage
Logic 0
VOL
2
3
9,12
4
4
9,12
5,10,13
5,10,13
8
8
1,16
1,16
Threshold Voltage
Logic 1
VOHA
2
3
9,12
5,10,13
5,10,13
8
8
1,16
1,16
2
3
9,12
5,10,13
5,10,13
8
8
1,16
1,16
Threshold Voltage
. Logic 0
Reference Voltage
Switching Times
VOLA
VBB
9,12
4
9,12
4
4
11
5,10,13
(50nLoad)
Propagation Delay
4
Pulse In
Pulse Out
2
14+2+
t4-2t4+3t4-3+
2
2
3
3
4
4
4
4
3
3
5,10,13
5,10,13
5,10,13
5,10,13
2
8
1,16
-3.2 V
+2.0 V
8
8
8
8
1,16
1,16
1,16
1,16
Rise Time
(20 to 80%)
t2+
t3+
2
3
4
4
2
3
5,10,13
5,10,13
8
8
1,16
1,16
Fall Time
(20 to 80%)
t2t3-
2
3
4
4
2
3
5,10,13
5,10,13
8
8
1,16
1,16
..
..
Each MECL 10,000 series CirCUIt has been designed to meet the dc specifications shown In the test table, after thermal eqUIlibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-43
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-Wide 2-3-lnput
OR-AND/OR-AND Gate
MC10117
The MC10117 is a dual2-wide 2-3-input OR-ANO/OR-ANO-Invert gate.
This general purpose logic element is designed for use in data control, such as
digital multiplexing or data distribution. Pin 9 is common to both gates.
-•
Po = 100 mW typ/pkg (No Load)
tpd 2.3 ns typ
In If = 2.2 ns typ (20%-80%)
=
LOGIC DIAGRAM
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE64!HJ8
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
10
11
L-.--r--cJj- 14
12-.-...--....
r - - - < . _ - - 15
13 - - - ' ' - - '
VCC1 =PIN 1
VCC2 = PIN 16
VEE = PIN 8
VCC2
BOUT
AoUT
BOUT
A11N
B11N
A11N
B11N
A2IN
B21N
A2IN
B2IN
VEE
A2'N.B2IN
Pin assignment is for Duat-in-Line Package.
For PLCC pin assignment. see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola. Inc. 1996
VCC1
AoUT
REV5
®
MOTOROLA
MC10117
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
29
linH'
6
9
4
425
560
390
-30'C
Min
+25'C
Max
Min
+B5'C
Typ
Max
Max
Unit
20
26
29
mAdc
265
350
245
265
350
245
/lAdc
0.5
Min
linL
4
0.5
Output Voltage
Logic 1
VOH
2
3
-1.060
-1.060
-0.890
-0.780
-0.960
-0.960
-0.810
-0.700
-0.890
-0.890
0.3
-0.700
-0.590
Vdc
Output Voltage
Logic 0
VOL
2
3
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
3
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
3
4+2+
4-2t4+3t4-3+
2
2
3
3
1.4
1.4
1.4
1.4
3.9
3.9
3.9
3.9
1.4
1.4
1.4
1.4
2.3
2.3
2.3
2.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
3.8
3.8
3.8
3.8
J!Adc
-0.910
-0.910
-0.980
-0.980
-1.630
-1.630
-1.655
-1.655
Vdc
-1.595
-1.595
(SOn Load)
Switching Times
Propagation Delay
Vdc
ns
Rise Time
(20 to 80%)
t2+
1:3+
2
3
0.9
0.9
4.1
4.1
1.1
1.1
2.2
2.2
4.0
4.0
1.1
1.1
4.6
4.6
Fall Time
(20 to 80%)
t2t3-
2
3
0.9
0.9
4.1
4.1
1.1
1.1
2.2
2.2
4.0
4.0
1.1
1.1
4.6
4.6
, Inputs 4, 5, 12 and 13 have same linH limit.
Inputs 6, 7, 10 and 11 have same linH limit.
MECLData
DL122-Rev6
3-45
MOTOROLA
MC10117
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
Power Supply Drain Current
Input Current
IE
B
linH'
6
9
4
linL
4
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
logic 1
VOH
2
3
Output Voltage
Logic 0
VOL
2
3
4,9
2
9
Logic 1
VOHA
VIHAmin
Logic 0
VOLA
Switching Times
(500 load)
Propagation Delay
1.4+2+
1.4-21.4+31.4-3+
2
2
(VCC)
Gnd
8
1,16
4
1,16
1,16
1,16
9
8
1,16
8
8
1,16
1,16
8
8
1,16
1,16
8
8
1,16
1,16
4
8
8
1,16
1,16
4,9
4
4
2
3
VEE
8
8
8
3
Threshold Voltage
VILAmax
4
9
Output Voltage
Threshold Voltage
VILmin
9
4
+1.11V
Pulse In
Pulse Out
-3.2 V
+2.0 V
4
4
4
4
2
2
3
3
8
8
8
8
1,16
1,16
1,16
1,16
3
9
9
9
9
Rise Time
(20 to 80%)
t2+
t3+
2
3
9
9
4
4
2
3
8
8
1,16
1,16
Fall Time
(20 to 80%)
t2t3-
2
3
9
9
4
4
2
3
8
8
1,16
1,16
3
• Inputs 4, 5, 12 and 13 have same linH limit.
Inputs 6, 7, 10 and 11 have same linH limit.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal eqUilibrium has been
established. The circuit Is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-46
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Wide OR-AND/OR-AND
Gate
MC10121
The MC10121 is a basic logic building block providing the simultaneous
OR-AND/OR-AND-Invert function, useful in data control and digital multiplexing
applications.
-•
=
=
PD 100 mW typ/pkg (No Load)
tpd 2.3 ns typ
tr, tf = 2.5 ns typ (20%-80%)
LOGIC DIAGRAM
4----'--_
5
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-10
P SUFFIX
PLASTIC PACKAGE
CASE 64!HJB
FNSUFFIX
PLCC
CASEn5-02
DIP
PIN ASSIGNMENT
7
9
VCC1
VCC2
AOUT
A4IN
AOUT
A41N
10
11
12
13
14
A11N
A4IN
A11N
A31N
15
A11N
A31N
A2IN
A2IN, A31N
VEE
A2IN
VCC1 =PIN 1
VCC2= PIN 16
VEE = PIN8
Pin assignment is for Dual-in--line Package.
For PLCC pin aSSignment, see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola, Inc. 1996
3-47
REVS
®
MOTOROI.A
[3J
MC10121
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Logic 1
Output Voltage
Symbol
Pin
Under
Test
IE
8
29
linH
7
9
10
390
390
495
-30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
20
26
29
mAde
245
245
310
245
245
~dc
310
0.5
0.5
0.5
Min
~dc
0.3
0.3
0.3
linL
7
9
10
0.5
0.5
0.5
VOH
3
2
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
-1.060
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Output Voltage
Logic 0
VOL
3
2
-1.890
-1.890
Threshold Voltage
Logic 1
VOHA
3
2
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
3
2
14+314-3+
14+2+
14-2-
3
3
2
2
1.4
1.4
1.4
1.4
3.6
3.6
3.6
3.6
1.4
1.4
1.4
1.4
2.3
2.3
2.3
2.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
3.5
3.5
3.5
3.5
Switching limes
-0.910
-0.910
-0.980
-0.980
-1.655
-1.655
-1.630
-1.630
Vdc
-1.595
-1.595
(50Q Load)
Propagation Delay
ns
Rise Time
(20 to 80%)
13+
t2+
3
2
0.9
0.9
4.1
4.1
1.1
1.1
.2.5
2.5
4.0
4.0
1.1
1.1
4.6
4.6
Fall TIme
(20 to 80%)
t3t2-
3
2
0.9
0.9
4.1
4.1
1.1
1.1
2.5
2.5
4.0
1.1
1.1
4.6
4.6
MOTOROLA
Vdc
3--48
4.0
MECLData
DL122-Rev6
MC10121
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
VIHmax
VILmin
VIHAmln
VILAmax
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+B5'C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Power Supply Drain Current
Input Current
Output Voltage
Test Temperature
Logic 1
Pin
Under
Test
IE
8
linH
7
9
10
linL
7
9
10
VOH
3
2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
3
2
Threshold Voltage
Logic 1
VOHA
3
2
10,13
3
2
10,13
Switching TImes
(50Q Load)
Propagation Delay
VEE
(VCC)
Gnd
8
1,16
B
B
8
1,16
1,16
1,16
8
8
8
1,16
1,16
1,16
8
8
1,16
1,16
8
8
1,16
1,16
8
8
1,16
1,16
4
8
8
1,16
1,16
VILAmax
4,10,13
VOL
VOLA
VIHAmin
7
9
10
Logic 0
Logic 0
VILmin
7
9
10
Output Voltage
Threshold Voltage
VEE
4,10,13
4
4
4
+1.11V
Pulse In
Pulse Out
-3.2 V
+2.0 V
10,13
10,13
10,13
10,13
4
4
4
4
3
3
2
2
8
8
8
8
1,16
1,16
1,16
1,16
4-2-
3
3
2
2
Rise TIme
(20 to 80%)
t3+
t2+
3
2
10,13
10,13
4
4
3
2
8
8
1,16
1,16
Fall TIme
(20 to 80%)
t3t2-
3
2
10,13
10,13
4
4
3
2
8
8
1,16
1,16
4+314-3+
t4+2+
..
..
Each MECL 10,000 series circuit has been deSigned to meet the dc specifications shown In the test table, after thermal equIlibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
D1122-Rev6
3-49
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple 4-3-3-lnput Bus Driver
MC10123
The MC10123 consists of three NOR gates designed for bus driving
applications on card or between cards. Output low logic levels are specified with
VOL -2.1 Vdc so that the bus may be terminated to -2.0 Vdc. The gate output,
when low, appears as a high impedance to the bus, because the output emitterfollowers of the MC1 0123 are "tumed-off." This eliminates discontinuities in the
characteristic impedance of the bus.
The VOH level is specified when driving a 25-------ID
Pulse Generator
Input Pulse
t+=t-=5.5±0.5ns
(10 to 90%)
Unused Inputs (0)
must be tied to
VccorPin 16
3
50-ohm tennination to ground located in each scope channel input.
02
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin and
TPout to output pin.
Hysteresis
Control
Clock
Reset
Strobe
Unused outputs
connected to a
50-ohm resistor
to ground.
2
03
I
I
I
I
L
11
10
12
~~~"--+2.0 Vdc
NOTE: All power supplies and logic levels are shifted 2 volts positive.
MOTOROLA
3-66
MECLData
DL122-Rev6
MC10129
Figure 3 - DATA to OUTPUT
(Clock and Reset are low, Strobe is high)
Figure 4 - STROBE to OUTPUT
(Data is high, Clock and Reset are low)
,..-_""'-_ _ _ _ _ +1.11 V
, . . - - - +S.ov
Data _ _ _ _.1
Strobe
' - - - - - ' . - - - - +2.4 V
t+
' -_ _ _ +0.31 V
t+
t-
+------0 _ _ _--1'
t-
+1.11 V
+---+I.IIV
o
~------ +0.31 V
"--='-'--
tI2+14+
+0.31 V
tI2-14-
Figure 6 - CLOCK to OUTPUT
(Reset is low, Strobe is high)
\
Figure 5 - RESET to OUTPUT
(Data and Strobe are high)
L-+2.4V
Clock---"'\.
~-..... - - - - - -
, . . - - - - +1.11 V
+1.11 V
' -_ _ _ +0.31 V
Reset------J
~--,.----
+0.31 V
r=----
+1.11 V
£!li!L _ _ _ _
+0.31 V
o ----+.L
"----fJ'
Clock
+S.OV
Data \ ' - - - - - - ' /
J---------+l.ll V
tl1-14-
tl1-14+
' - - - t - - - - - - - - - +0.31 V
Figure 7 - TSET UP AND THOLD WAVEFORMS
1r::'::'T'""""'\.I-+------
+1.11 V
,..-----.,----- +s.oo V
D
O---i"
SO%
' - - - - - +2.400 V
' - - - - - - - +0.31 V
, . . - - - - - - +1.11 V
C - - - - - - . - - - - - - +0.31 V
tll-l4+
O~
t10+14-
MECL Data
DL122-Rev6
3--67
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Type D Master-Slave
Flip-Flop
MC10131
The MCI 0131 is a dual master-slave type 0 flip-flop. Asynchronous Set (S)
and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip-flop
may be clocked separately by holding the common clock in the low state and
using the enable inputs for the clocking function. If the common clock is to be
used to clock the flip-flop, the Clock Enable inputs must be in the low state. In
this case, the enable inputs perform the function of controlling the common
clock.
The output states of the flip-flop change on the positive transition of the
clock. A change in the information present at the data (0) input will not affect the
output information at any other time due to master slave construction.
-•
=235 mW typ/pkg (No Load)
FTog =160 MHz typ
ipd =3.0 ns typ
tf, tf =2.5 ns typ (20%-80%)
Po
LSUFFIX
CERAMIC PACKAGE
CASE 62(}-10
PSUFFIX
PLASTIC PACKAGE
CASE 64EHl8
FNSUFFIX
PLCC
CASE77~
DIP
PIN ASSIGNMENT
LOGIC DIAGRAM
81 5 - - - - - - - ,
Ql
Of
Rl 4
15
Q2
14
-t-----'
Rl
13
R2
-11------.
51
12
52
GEl
11
CE2
Dl
10
D2
VEE
9
Cc
14
CE2 11 - ' - ' _ ' 1
0210
2
VCC2
Q2
Cc 9
R2 13
16
VCCI
---"i
15
82 12 - - - - - - ' "
VCCI = PIN 1
VCC2=PIN 16
VEE = PIN 8
3
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment. see the Pin Conversion
Tables on page 6-11.
CLOCKED TRUTH TABLE
R-S TRUTH TABLE
C
D
Q n+l
R
S
Q n+l
L
X
an
L
L
an
H
L
L
L
H
H
H
H
H
H
L
L
H
H
N.D.
..
C = CE + CC.A dock H IS a clock transition from a
low 10 a high stale.
N.D. = Not Defmed
3/93
© Motorola, Inc. 1996
3-68
REVS
®
MOTOROLA
MC10131
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
62
linH
4
5
6
7
9
525
525
350
390
425
linL
4,5'
6,7,9"
0.5
0.5
-30'C
Min
+25'C
Max
Min
+85'C
Typ
Max
Max
Unit
45
56
62
mAdc
330
330
220
245
265
330
330
220
245
265
IlAdc
Min
0.3
0.3
0.5
0.5
IlAdc
Output Voltage
Logic 1
VOH
2
2t
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
3t
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
2t
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
3t
Switching Times
Clock Input
-0.910
-0.910
-0.980
-0.980
-1.655
-1.655
Vdc
-1.595
-1.595
-1.630
-1.630
(500 Load)
Propagation Delay
Vdc
ns
t9+2t9+2+
t6+2+
ts+2-
2
2
2
2
1.7
1.7
1.7
1.7
4.6
4.6
4.6
4.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
4.5
4.5
4.5
4.5
1.8
1.8
1.8
1.8
5.0
5.0
5.0
5.0
Rise Time
(20 to 80%)
t2+
2
1.0
4.6
1.1
2.5
4.5
1.1
4.9
Fall Time
(20 to 80%)
t2-
2
1.0
4.6
1.1
2.5
4.5
1.1
4.9
Propagation Delay
t5+2+
t12+15+
t5+3tI2+14-
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Propagation Delay
4+2tI3+154+3tI3+14+
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Set Input
ns
Reset Input
ns
ns
Setup Time
tsetup
7
2.5
2.5
2.5
Hold Time
thold
7
1.5
1.5
1.5
ns
Toggle Frequency (Max)
ftog
2
125
125
125
MHz
..
" IndIvIdually test each Input applYing VIH or VIL to Input under test.
t Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
160
JL-
MECLData
DL122-Rev6
3-69
VIHmax
VILmin
MOTOROLA
MC10131
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmln
VIHAmln
VILAmax
VEE
-3DoC
-D.890
-1.890
-1.205
-1.500
-5.2
+25°C
-D.81 0
-1.850
-1.105
-1.475
-5.2
+B5°C
-D.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
4
5
6
7
9
linL
4,5'
6,7,9'
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VILAmax
VIHAmin
4
5
6
7
9
,
,
VEE
(VCC)
Gnd
8
1,16
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
8
8
1,16
1,16
Output Voltage
Logic 1
VOH
2
2t
5
7
8
8
1,16
1,16
Output Voltage
Logic 0
VOL
2
3t
5
7
8
8
1,16
1,16
Threshold Voltage
Logic 1
VOHA
2
2t
5
7
9
8
8
1,16
1,16
2
3t
5
7
9
8
8
1,16
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
9
9
6
6
2
2
2
2
8
8
8
8
1,16
1,16
1,16
1,16
Threshold Voltage
Logic 0
VOLA
(50QLoad)
Switching Times
Clock Input
+l.llVdc
Propagation Delay
t9+2t9+2+
t6+2+
t6+2-
2
2
2
2
7
7
7
Rise Time
(20 to 80%)
t2+
2
Fall Time
(20 to 80%)
t2-
2
t5+2+
tI2+15+
t5+3t12+14-
2
15
3
14
4+2t13+154+3tl3+14+
2
15
3
14
Setup TIme
tsetup
Hold TIme
thold
Toggle Frequency (Max)
ftog
9
2
8
1,16
9
2
8
1,16
5
12
5
12
2
15
3
14
8
8
8
8
1,16
1,16
1,16
1,16
4
13
4
13
2
15
3
14
8
8
8
8
1,16
1,16
1,16
1,16
7
6,7
2
8
1,16
7
6,7
2
8
1,16
2
6
2
8
1,16
Set Input
Propagation Delay
6
9
Reset Input
Propagation Delay
..
6
9
, IndiVidually test each Input applYing VIH or VIL to Input under test.
t Output level to be measured aiter a clock pulse has been applied to the CE Input (Pin 6)
JL-
-
VIHmax
VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5Q-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-70
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Latch
MC10133
The MC10133 is a high speed. low power. quad latch consisting of four
bistable latch circuits with 0 type inputs and gated Q outputs. allowing direct
wiring to a bus. When the clock is high. outputs will follow 0 inputs. Information
is latched on the negative going transition of the clock.
The outputs are gated when the output enable (<3) is low. All four latches may
be clocked at one time with the common clock (CC). or each half may be
clocked separately with its clock enable (CE).
-,.
=
=
Po 310 mW typ/pkg (No Load)
tpd 4.0 ns typ
t r• tf = 2.0 ns typ (20%-80%)
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
LOGIC DIAGRAM
00
3
2 00
DIP
PIN ASSIGNMENT
GO
01
6 01
7
CE
VCC1
16
VCC2
Cc 13
00
2
15
03
CE 12
00
3
14
03
11 02
CE
4
13
Cc
GO
12
CE
15 03
01
11
02
01
10
Gf
VEE
9
02
02 9
G1 10
03 14
--------'~
TRUTH TABLE
G
C
D
H
L
L
L
X
L
H
H
X
X
L
H
On+1
L
an
L
H
VCC1 = PIN 1
VCC2=PIN 16
VEE= PINS
9/96
© Motorola, Inc. 1996
3-71
REV 6
®
MOTOROLA
[3J
MC10133
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
Max
Unit
IE
8
82
75
82
mAde
linH
3
4
5
13
390
425
560
560
245"
265
350
350
245
265
350
350
/lAde
Power Supply Drain Current
Input Current
-30°C
Min
+25°C
Max
Min
Typ
+85°C
Max
Min
0.5
0.3
linL
3
0.5
Output Voltage
Logic 1
VOH
2
2
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vde
Output Voltage
Logic 0
VOL
2
2
2
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.650
-1.650
-1.650
-1.825
-1.825
-1.825
-1.615
-1.615
-1.615
Vde
Threshold Voltage
Logic 1
VOHA
2
2
2
2t
2:1:
2:1:
2
2
-1.080
-1.080
-1.080
-1.080
-1.080
-1.080
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
2
2
2t
2:1:
2:1:
t3+2+
14+2+
t5-2+
tsetup
thold
2
2
2
3
3
1.0
1.0
1.0
2.5
1.5
5.6
5.4
3.2
1.0
1.0
1.0
2.5
1.5
4.0
4.0
2.0
0.7
0.7
5.4
5.4
3.1
1.1
1.2
1.0
2.5
1.5
5.9
6.0
3.4
Switching Times
-0.980
-0.980
-0.980
-0.980
-0.980
-0.980
-0.980
-0.980
/lAde
-0.910
-0.910
-0.910
-0.910
-0.910
-0.910
-0.910
-0.910
-1.630
-1.630
-1.630
-1.630
-1.630
-1.630
-1.655
-1.655
-1.655
-1.655
-1.655
-1.655
Vdc
-1.595
-1.595
-1.595
-1.595
-1.595
-1.595
(Son Load)
Propagation Delay
Vdc
ns
Rise Time
(20 to 80%)
t2+
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
Fall Time
(20 to 80%)
t2-
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
t Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)
.-lL-
VIHmax
VILmin
:I: Data input at proper highllow level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured after
device has latched.
• Latch set to zero state before test.
MOTOROLA
3-72
MECLData
DL122-Rev6
MC10133
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
Symbol
Power Supply Drain Current
Input Current
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Pin
Under
Test
IE
8
linH
3
4
5
13
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
3
linL
3
VOH
2
2
3,4
3,13
Output Voltage
Logic 0
VOL
2
2
2
13
3,5,13
4
Threshold Voltage
Logic 1
VOHA
2
2
2
2t
2:1:
2:1:
2
2
3,4
4
3,4
2
2
2
2t
2:1:
2:1:
3,4
4
4
Switching Times
VOLA
3
3
5
3
3
4
4
13
3
3
VEE
(VCC)
Gnd
8
1,16
8
8
8
8
1,16
1,16
1,16
1,16
8
1,16
8
8
1,16
1,16
8
8
8
1,16
1,16
1,16
8
8
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
13
8
8
8
8
8
8
+1.11V
Pulse In
Pulse Out
5
3
3
3
-3.2 V
+2.0 V
13+2+
4+2+
t5-2+
tsetup
thold
2
2
2
3
3
4
3'
3
4
5
3
3
2
2
2
2
2
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
(50n Load)
Propagation Delay
VILAmax
13
Logic 1
Logic 0
VIHAmin
3
4
5
13
Output Voltage
Threshold Voltage
VILmin
Rise Time
(20 to 80%)
t2+
2
4
3
2
8
1,16
Fall Time
(20 to 80%)
t2-
2
4
3
2
8
1,16
t Oulput level to be measured after a clock pulse has been applied to the clock input (Pin 4)
JL-
-
VIHmax
VILmin
:I: Data input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. levels are measured after
device has latched .
• Latch set to zero state before test.
Each MECl 10,000 series circuit has been designed to meetlhe de specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow grealer than 500 linear fpm is maintained.
Outputs are terminated through a 5
VCC2
02
01
03
00
Cout
CLOCK
03
DO
02
01
52
Cin
ilEE
51
FUNCTION TABLE
Gin
X
SI
S2
L
L
Preset (Program)
Operating Mode
L
L
H
Increment (Gaunt Up)
H
L
H
Hold Count
L
H
L
Decrement (Count Down)
H
H
L
Hold Count
X
H
H
Hold (Stop Count)
Pin assignment Is for Dual-ln--Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola. Inc. 1996
3-80
REV5
®
MOTOROLA
MC10136
LOGIC DIAGRAM
51 9
527_......._~.---,
CiriYTn
10
VCC1 =PIN 1
VCC2=PIN 16
VEE =PINB
Clock
13----_r~~rt----~~_rr_----_+~~+_----_+~
12 DO
14 00
11 01
15 01
602
202
303
503
NOTE: Flip-flops will toggle when all i inputs are low.
SEQUENTIAL TRUTH TABLE"
INPUTS
OUTPUTS
Sl
S2
OD
01
02
03
iii
..
QD
Q1
Q2
Q3
Carry
Out
L
L
L
L
L
L
H
L
H
H
H
H
L
H
H
H
H
H
H
L
L
L
L
L
L
X
X
X
X
X
X
H
X
X
X
X
L
X
X
X
X
X
X
H
X
X
X
X
H
X
X
X
X
X
X
L
X
X
X
X
H
X
X
X
X
X
X
L
X
X
X
X
X
L
L
L
H
H
X
X
L
L
L
L
·H
H
H
H
L
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
L
H
H
H
L
H
H
L
H
Carry
Clock
,.. Truth table shows logic states assuming Inputs vary In sequence shown from top to bottom.
** A clock H is defined as a clock input transition from a low to a high logic level.
MECL Data
DL122-Rev6
3-81
MOTOROLA
MC10136
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Currenl
Inpul Currenl
Symbol
Pin
Under
Test
IE
8
138
linH
5,6,11,12
7
9,10
13
350
425
390
460
-30°C
+25°C
Max
Min
Min
+85°C
Typ
Max
Max
Unit
100
125
138
mAde
220
265
245
290
220
265
245
290
!lAde
Min
0.3
linL
All
0.5
Oulpul Voltage
Logic 1
VOH
14(2.)
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vde
OUlpUI Vollage
Logic 0
VOL
14(2.)
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vde
Threshold Vollage
Logic 1
VOHA
14(2.)
-1.080
Threshold Vollage
Logic 0
VOLA
14(2.)
-1.595
Vde
113+14+
113+14113+4+
tI3+4-
14
14
4
4
0.8
0.8
2.0
2.0
4.8
4.8
10.9
10.9
1.0
1.0
2.5
2.5
3.3
3.3
7.0
7.0
4.5
4.5
10.5
10.5
1.4
1.4
2.4
2.4
5.0
5.0
11.5
11.5
tlO-4tl0+4+
4(3.)
4
1.6
1.6
7.4
7.4
1.6
1.6
5.0
5.0
6.9
6.9
1.9
1.9
7.5
7.5
Dala InpulS
112+13+
tI2-13+
14
14
3.5
3.5
3.5
3.5
3.5
3.5
Select InpulS
t9+13+
17+13+
14
14
6.0
6.0
6.0
6.0
6.0
6.0
Carry In InpUi
110-13+
110+13+
14
14
2.5
1.5
2.5
1.5
3.0
1.5
Dala InpulS
113+12+
113+12-
14
14
0
0
0
0
0
0
Selecl Inputs
113+9+
tI3+7+
14
14
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
Carry In Inpul
t13+10113+10+
14
14
0
0
0
0
0
0
fcounlup
fcountdown
14
14
125
125
125
125
150
150
14+
t14+
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
14-
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
Swilehing limes
(50QLoad)
Propagalion Delay
Clock Inpul
Carry In 10 Carry Out
Setup lime
Hold lime
Counling Frequency
Rise lime
(20 to 80%)
Fall lime
(201080%)
..
0.5
-0.980
!lAdc
-0.910
-1.655
-1.630
Vdc
ns
114-
125
125
MHz
ns
1. IndiVidually test each Input; apply VILmin to pin under test.
2. Measure output after clock pulse V ~ VIH appears at clock input (Pin 13).
IL
3. Before test set all Q outpulS 10 a logic high.
4. To preserve reliable performance, Ihe MCI 0136 (plastic packaged device only) is to be operaled in ambienl temperalures above 70°C only
when 500lfpm blown air or equivalent heat sinking is provided.
MOTOROLA
3--82
MECLData
DL122-Rev6
MC10136
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
Symbol
Power Supply Drain Current
Input Current
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-S.2
+85'C
-0.700
-1.82S
-1.035
-1.440
-S.2
Pin
Under
Test
IE
8
linH
S,6,11,12
7
9,10
13
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmln
1,16
8
8
8
1,16
1,16
1,16
1,16
Notel.
a
1,16
7,9
8
1,16
8
1,16
8
1,16
linL
All
14(2.)
Output Voltage
Logic 0
VOL
14(2.)
7,9
Threshold Voltage
Logic 1
VOHA
14(2.)
7,9
Threshold Voltage
Logic 0
VOLA
14(2.)
7,9
Propagation Delay
Clock Input
+l.llV
(VCC)
Gnd
8
VOH
12
VEE
8
Logic 1
(Son Load)
VILAmax
5,6,11,12
7
9,10
13
Output Voltage
Switching Times
VIHAmin
12
12
8
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
13
13
13
13
14
14
4
4
8
8
8
8
1,16
1,16
1,16
1,16
13
13
10
10
4
4
8
8
1,16
1,16
7,9
7,9
12,13
12,13
14
14
8
8
1,16
1,16
9,13
7,13
14
14
8
8
1,16
1,16
9
9
10,13
10,13
14
14
8
8
1,16
1,16
7,9
7,9
12,13
12,13
14
14
8
8
1,16
1,16
9,13
7,13
14
14
8
8
1,16
1,16
10,13
10,13
14
14
8
8
1,16
1,16
+O.31V
t13+14+
t13+14t13+4+
t13+4-
14
14
4
4
12
Carry In to Carry Out
tl0-4-tl0+4+
4(3.)
4
7
7
Data Inputs
t12+13+
t12-13+
14
14
Select Inputs
t9+13+
17+13+
14
14
Carry In Inputs
tlO-13+
tl0+13+
14
14
Data Inputs
t13+12+
t13+12-
14
14
t13+9+
t13+7+
14
14
t13+10t13+10+
14
14
7
7
fcountup
fcountdown
14
14
7
9
13
13
14
14
8
8
1,16
1,16
14+
t14+
4
14
7
7
13
13
4
14
8
8
1,16
1,16
14-
4
14
7
7
13
13
4
14
8
8
1,16
1,16
Setup Time
Hold Time
Select Inputs
Carry In Inputs
Counting Frequency
Rise Time
(20 to 80%)
Fall Time
(20 to 80%)
tl4-
7
7
7
7
9
1. Individually test each input; apply VILmin to pin under test.
2. Measure output after clock pulse V ~ VIH appears at clock input (Pin 13).
IL
3. Before test set all Q outputs to a logic high.
4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70'C only
when SOOlfpm blown air or equivalent heat sinking is provided.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than SOO linear fpm is maintained.
Outputs are terminated through a SO-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DLl22-Rev6
3--83
MOTOROLA
MC10136
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
NOTE:
!setup is the minimum time before the positive
transition of the clock pulse (C) that information must
be present at the input 0 or S.
thold is the minimum time after the positive transition of the clock pulse (C) that information must
remain unchanged at the input 0 or S.
INPUT PULSE
T+=T-=2.0±O.2NS
(20 TO 80%)
COAX
COAX
CLOCK
INPUT
\
\ TPout
TPin
Clock
QOutput
VEE = -3.2 VOC
C
+0.31 V
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< lf4 inch from TPin to input pin and
TPoutto output pin.
Unused outputs are connected to a
50-0hm resistor to ground.
OorS
CARRY IN
SET UP AND HOLD TIMES
C--_J
MOTOROLA
MECLData
DL122-Rev6
MC10136
APPLICATIONS INFORMATION
To provide more than four bits of counting capability
The MC10136 may also be used as a programmable
several MC1 0136 counters may be cascaded. The Carry
counter. The configuration of Figure 3 requires no
Tn input overrides the clock when the counter is either in
additional gates, although maximum frequency is limited
the increment mode or the decrement mode of operation.
to about 50 MHz. The divider modulus is equal to the
This input allows several devices to be cascaded in a fully
program input plus one (M N + 1), therefore, the counter
synchronous multistage counter as illustrated in Figure 1.
will divide by a modulus varying from 1 to 16.
The carry is advanced between stages as shown with no
A second programmable configuration is also illustrated
external gating. The Carry In of the first device may be left
in Figure 4. A pulse swallowing technique is used to speed
open. The system clock is common to all devices.
the counter operation up to 110 MHz typically. The divider
The various operational modes of the counter make it
modulus for this figure is equal to the program input (M =
useful for a wide variety of applications. If used with MECL
N). The minimum modulus is 2 because of the pulse
III devices, prescalers with input toggle frequencies in
swallowing technique, and the modulus may vary from 2
excess of 300 MHz are possible. Figure 2 shows such a
to 15. This programmable configuration requires an
prescaler using the MC10136 and MC1670. Use of the
additional gate, such as1/2MC10109 and a flip-flop such
MC10231 in place of the MC1670 permits 200 MHz
as 1/2MC10131.
operation.
=
FIGURE 1 -
12 BIT SYNCHRONOUS COUNTER
LSS
I
MsS
I
I
I
00 01 02 03
-
Gin
FIGURE 2 - 300 MHz PRESCALER
GaUl
I
-
I
I
I
00 01 02 03
Gin
GaUl
I
-
I
I
I
00 01 02 Q3
Logic High
Gin
MC10136
51
C
C
C
D
C
Inpul
52
01-+----1 c
03
'-----'TU
Frequency
Input Frequency
Q
5yslem
Clock
32
MCI670
NOTE: S1 and 52 are set either for increment or decrement operation.
FIGURE 3 - 50 MHz PROGRAMMABLE COUNTER
FIGURE 4 -
100 MHz PROGRAMMABLE COUNTER
Program Inpul
t,n .....---\c
Program InpuI
52
MC10136
51
fin-.---\c
Gin
52
51
CaUl
loul
o
112MC10109
1 lout ::;
fin
Program Input + 1
fOUl
112MC10131
L-4-------------------~C
2 Imax " 50 MHz Typ.
3 Divide Ralio is from 1 to 16.
1 lout ::;
fin
Program Inpul
Imax " 110 MHz Typ.
3 DMde Ratio is from 2 to 15.
MECLData
DL122 -
Rev 6
~5
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Universal Decade Counter
MC10137
The MC1 0137 is a high speed synchronous counter that can count up, down,
preset, or stop count at frequencies exceeding 100 MHz. The flexibility of this
device allows the designer to use one basic counter for most applications. The
synchronous count feature makes the MC10137 suitable for either computers
or instrumentation.
Three control lines (81, 82, and Carry In) determine the operation mode of
the counter. Lines 81 and 82 determine one of four operations; preset
(program), increment (count up), decrement (count down), or hold (stop count).
Note that in the preset mode a clock pulse is necessary to load the counter, and
the information present on the data inputs (DO, D1, D2, and D3) will be entered
into the counter. Carry Out goes Iowan the terminal count. The Carry Out on the
MC10137 is partially decoded from 01 and 02 directly, so in the preset mode
the condition of the Carry Out after the Clock's positive excursion will depend on
the condition of 01 and/or 02. The counter changes state only on the positive
going edge of the clock. Any other input may change at any time except during
the positive transition of the clock. The sequence for counting out of improper
states is as shown in the 8tate Diagrams.
PD =
fcount=
tpd =
=
=
-,.
625 mW typ/pkg (No Load)
150 MHztyp
3.3 ns typ (C-9)
7.0 ns typ (C-Cout)
5.0 ns typ (Cin-Cout)
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-l0
PSUFFIX
PLASTIC PACKAGE
CASE 641HlS
PIN ASSIGNMENT
VCC1
2
VCC2
01
00
STATE DIAGRAMS
COUNT UP
GoUT
C
03
DO
02
01
82
CIN
VEE
81
COUNTDOWN
FUNCTION SELECT TABLE
Sl
S2
L
L
Operating Mode
Preset (Program)
L
H
Increment (Count Up)
H
L
Decrement (Count Down)
H
H
Hold (Stop Count)
3/93
© Motorola. Inc. 1996
3-86
REVS
®
MOTOROI.A
MC10137
LOGIC DIAGRAM
51 9
52 7
10
--++.,
canyrn
co
01
c
C
13
Clock
VCC1 =PIN 1
VCC2=PIN 16
VEE = PIN 8
14 00
1200
1501
11 01
202
602
3 03
503
4
CariYOiil
NOTE: Flip-flops will toggle when all i inputs are low.
SEQUENTIAL TRUTH TABLE'
INPUTS
OUTPUTS
Carry
S1
S2
DO
D1
D2
D3
Iii
L
L
L
H
H
X
H
X
H
X
L
L
L
H
H
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
X
X
L
L
H
H
H
H
L
H
H
H
H
L
L
L
L
X
X
X
H
X
X
X
L
X
X
X
..
00
01
02
03
H
H
H
L
H
L
H
L
H
H
H
H
H
H
L
L
L
L
L
H
L
L
H
H
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
H
H
L
H
H
L
H
L
L
L
L
L
L
L
L
H
H
L
Clock
L
L
L
L
Carry
Out
H
H
.. Truth table shows logiC states assuming Inputs vary In sequence shown from top to bottom.
** A clock H is defined as a clock input transition from a low to a high logic level.
MECLData
DL122-Rev6
:HI?
MOTOROLA
MC10137
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
165
linH
5,6,11,12
7
9,10
13
350
425
390
460
-30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
120
150
165
mAdc
220
265
245
290
220
265
245
290
!lAdc
linL
All
0.5
Output Voltage
Logic 1
VOH
14(2.)
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Outpul Voltage
Logic 0
VOL
14(2.)
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
14(2.)
-1.080
Threshold Voltage
Logic 0
VOLA
14(2.)
t13+14+
113+14t13+4+
113+4-
14
14
4
4
0.8
0.8
2.0
2.0
4.8
4.8
10.9
10.9
1.0
1.0
2.5
2.5
3.3
3.3
7.0
7.0
4.5
4.5
10.5
10.5
1.1
1.1
2.4
2.4
5.0
5.0
11.5
11.5
Carry In 10 Carry Out
t1D-4t10+4+
4(3.)
4
1.6
1.6
7.4
7.4
1.6
1.6
5.0
5.0
6.9
6.9
1.9
1.9
7.5
7.5
Data Inputs
t12+13+
112-13+
14
14
3.5
3.5
3.5
3.5
3.5
3.5
Selecl Inputs
19+13+
'7+13+
14
14
7.5
7.5
7.5
7.5
7.5
7.5
Carry In Input
110-13+
113+10+
14
14
4.5
-1.0
3.7
-1.0
4.5
-1.0
Data Inputs
113+12+
t13+12-
14
14
0
0
0
0
0
0
Select Inputs
t13+9+
113+7+
14
14
-2.5
-2.5
-2.5
-2.5
-2.5
-2.5
Carry In Inpul
113+10t10+13+
14
14
-1.6
4.0
-1.6
3.1
-1.6
4.0
fcounlup
fcounldown
14
14
125
125 .
125
125
150
150
14+
t14+
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
"'-
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
Switching Times
(SOn Load)
Propagalion Delay
Clock Inpul
SelupTime
Hold Time
Counling Frequency
Rise Time
(201080%)
Fall Time
(20 to 80%)
..
0.5
Min
0.3
-0.980
!lAdc
Vdc
-0.910
-1.655
-1.630
-1.595
Vdc
ns
114-
125
125
MHz
ns
1. IndiVidually apply VILmin to Pin under lest.
2. Measure oulpul after clock pulse V ~ VIH appears at clock inpul (Pin 13).
IL
3. Before test sel 01 and 02 oulputs 10 a logic low.
MOTOROLA
3-B8
MECLData
DL122-Rev6
MC10137
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+85'C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Power Supply Drain Current
Input Current
Pin
Under
Test
IE
8
linH
5,6,11,12
7
9,10
13
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
1,16
1,16
1,16
1,16
1,16
Note 1.
8
1,16
7,9
8
1,16
8
1,16
8
1,16
linL
All
14(2.)
Output Voltage
Logic 0
VOL
14(2.)
7,9
Threshold Voltage
Logic 1
VOHA
14(2.)
7,9
Threshold Voltage
Logic 0
VOLA
14(2.)
7,9
Propagation Delay
Clock Input
+1.11V
(VCC)
Gnd
8
VOH
12
VEE
8
8
8
8
Logic 1
(500 Load)
VILAmax
5,6,11,12
7
9,10
13
Output Voltage
Switching Times
VIHAmin
12
12
8'
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
13
13
13
13
14
14
4
4
8
8
8
8
1,16
1,16
1,16
1,16
13
13
10
10
4
4
8
8
1,16
1,16
7,9
7,9
12,13
12,13
14
14
8
8
1,16
1,16
9,13
7,13
14
14
8
8
1,16
1,16
9
9
10,13
10,13
14
14
8
8
1,16
1,16
7,9
7,9
12,13
12,13
14
14
8
8
1,16
1,16
9,13
7,13
14
14
8
8
1,16
1,16
10,13
10,13
14
14
8
8
1,16
1,16
+0.31 V
tI3+14+
tI3+14tI3+4+
t13+4-
14
14
4
4
12
Carry In to Carry Out
tl0-4tl0+4+
4(3.)
4
7
7
Data Inputs
tI2+13+
tI2-13+
14
14
Select Inputs
t9+13+
t7+13+
14
14
Carry In Inputs
tl0-13+
tI3+10+
14
14
Data Inputs
tI3+12+
tI3+12-
14
14
tI3+9+
tI3+7+
14
14
tI3+10tl0+13+
14
14
7
7
fcountup
fcountdown
14
14
7
9
13
13
14
14
8
8
1,16
1,16
Setup Time
Hold Time
Select Inputs
Carry In Inputs
Counting Frequency
7
7
7
7
9
9
Rise Time
(20 to 80%)
4+
t14+
4
14
7
7
13
13
4
14
8
8
1,16
1,16
Fall Time
(20 to 80%)
t4tl4-
4
14
7
7
13
13
4
14
8
8
1,16
1,16
..
Individually test each Input; apply VILmin to pin under test.
1.
2. Measure output after clock pulse V ~ VIH appears at clock input (Pin 13).
IL
3. Before test set all Q outputs to a logic high.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122- Rev 6
3-89
MOTOROLA
MC10137
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
\
t7
I~
I
I
I
I
Clock
(b)
i
(a) is the minimum time to wait after the
counter has been enabled to clock it.
I
\
(b) is the minimum time before the counter
has been disabled that it may be clocked.
Y L
(c) is the minimum time before the counter
is enabled that a clock pulse may be
applied with no effect on the state of the
counter.
(d) is the minimum time to wait after the
counter is disabled that a clock pulse may
be applied with no effect in the state of the
counter.
Car~in ~'-____________________~;(
I
I
(c)
~
I
I
-
(b) and (c) may be negative numbers.
\'-________________~i~~~)
VCC1 = VCC2 = +2.0 Vdc
Vin
NOTE:
tsetup is the minimum time before the posnive
transnion of the clock pulse (C) that information must
be present at the input 0 or S.
thold is the minimum time after the posnive
transnion of the clock pulse (C) that information must
remain unchanged at the input 0 or S.
Coax
Coax
Cin
C
DO
,
Input Pulse
t+ = t- = 2.0 ±O.2 ns
(20 to 80%)
Vout
01
Clock Input (o}-.....---o
00
01
Q2
02
TPin
03
03
S1
S2
Cout
I
TPout
+0.31 V
VEE =-3.2Vdc
r _ - - - - - " " - " . - - +1.11 V
C
+0.31 V
50-ohm termination to ground located in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin and
TPout to output pin.
Unused outputs are connected to a
50-0hm resistor to ground.
MOTOROLA
3-90
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Bi-Quinary Counter
MC10138
The MC1 0138 is a four bit counter capable of divide by two, five, or ten
functions. It is composed of four set-reset master-slave flip-flops. Clock
inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous "ser' or
"clear." Individual set and common reset inputs are provided, as well as
complementary outputs for the first and fourth bits.
VII
=
=
PD 370 mW typ/pkg (No Load)
ftog = 150 MHz typ
tr, tf 2.5 ns typ (20%-80%)
-•
LOGIC DIAGRAM
so
11
co
51
15
52
01
10
Q2
6
13
03
53
4
5
2
LSUFFIX
CERAMIC PACKAGE
CASE 62D-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
FNSUFFIX
PLCC
CASE 778-02
DIP
PIN ASSIGNMENT
12
Clod<
Rese;I--l-l-!:::::::;!::==~=l===~~~
14 00
C2
VCC1
7
VCC1
3
=PIN 1; VCC2 =PIN 16; VEE =PIN 8
a3
COUNTER TRUTH TABLES
BCD
BI-QUINARY
(Clock connected to C2
and 03 connected to C1)
(Clock connected to C1
and 00 connected to C2)
COUNT
01
02
03
00
COUNT
00
01
02
03
0
1
2
3
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
0
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
4
5
6
7
L
L
H
L
L
L
L
H
H
L
L
L
L
H
H
H
4
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
8
9
H
L
H
L
L
H
H
H
8
L
H
L
L
L
L
H
H
1
2
3
5
6
7
9
COUNTER STATE DIAGRAM CLOCK CONNECTED TO C2
QO
Q3
Qlj
Q2
Q1
S3
C1
S2
SO
C2
81
RESET
VEE
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
POSITIVE LOGIC
Qlj CONNECTED TO C2
3/93
© Motorola, Inc. 1996
VCC2
Q3
3-91
REVS
®
MOTOROLA
MC10138
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
97
linH
12
5,6,10,11
7
9
350
390
460
650
-30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
70
88
97
mAdc
220
245
290
410
220
245
290
!!Adc
linL
All
0.5
Output Voltage
Logic 1
VOH
3,14(3.)
2,4,13,15 (2.)
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Output Voltage
Logic 0
VOL
3,14(2.)
2,4,13,15 (3.)
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2,4,13,15 (2.)
3,14(3.)
13,15(2.)
-1.080
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2,4,13,15 (3.)
3,14(2.)
13,15(3.)
t12+15+
t12+14+
t7+13+
t7+4+
t7+2+
l?+3+
15
14
13
4
2
3
1.4
1.4
1.4
1.4
1.4
1.4
5.0
5.0
5.2
5.2
5.2
5.2
1.5
1.5
1.5
1.5
1.5
1.5
3.5
3.5
3.5
3.5
3.5
3.5
4.8
4.8
5.0
5.0
5.0
5.0
1.5
1.5
1.5
1.5
1.5
1.5
5.3
5.3
5.5
5.5
5.5
5.5
t12+15t12+14l?+13l?+4l?+2l?+3-
15
14
13
4
2
3
1.4
1.4
1.4
1.4
1.4
1.4
5.0
5.0
5.2
5.2
5.2
5.2
1.5
1.5
1.5
1.5
1.5
1.5
3.5
3.5
3.5
3.5
3.5
3.5
4.8
4.8
5.0
5.0
5.0
5.0
1.5
1.5
1.5
1.5
1.5
1.5
5.3
5.3
5.5
5.5
5.5
5.5
Set Delay
tl1+15+
tl1+14-
15
14
1.4
1.4
5.2
5.2
1.5
1.5
5.0
5.0
. 1.5
1.5
5.5
5.5
Reset Delay
t9+14+
t9+15-
14
15
1.4
1.4
5.2
5.2
1.5
1.5
5.0
5.0
1.5
1.5
5.5
5.5
Switching Times
Propagation
Delay
0.5
Min
0.3
-0.980
-0.980
-0.980
!!Adc
-0.910
-0.910
-0.910
-1.655
-1.655
-1.655
-1.630
-1.630
-1.630
Vdc
-1.595
-1.595
-1.595
(50'1 Load)
Clock Delays
ns
Rise Time
(20 to 80%)
tl4+
t15+
14
15
1.1
1.1
4.7
4.7
1.1
1.1
2.5
2.5
4.5
4.5
1.1
1.1
5.0
5.0
Fall Time
(20 to 80%)
tl4tl5-
14
15
1.1
1.1
4.7
4.7
1.1
1.1
2.5
2.5
4.5
4.5
1.1
1.1
5.0
5.0
fcount
2
15
125
125
125
125
150
150
Counting Frequency
Vdc
..
125
125
MHz
1. IndiVidually test each Input; apply VILmin to pin under test.
2. Set all four flip-flops by applying pulse
3. Reset all four flip-flops by applying pulse
MOTOROLA
n -
...J
L_
JL-
-
VIHmax
VILmin
VIHmax
VILmin
to pins 5, 6, 10, and 11 prior to applying test voltage indicated .
to pin 9 prior to applying test voltage indicated.
3-92
MECLData
DL122- Rev 6
MC10138
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
NOTE: Each MECL 10,000 series circuit has
been designed to meet the de specifications
shown in the test table, aHer thermal equilibrium
has been established. The circuit is in a lest
@
Test Temperature
VIHmax
VILmln
VIHAmin
VILAmax
VEE
-0.890
-1.890
-1.205
-1.500
-5.2
socket or mounted on a printed circuit board and
transverse air flow greater than 500 linear fpm is
-30°C
maintained. Outputs are terminated through a
50-0hm resistor to -2.0 volts. Test procedures
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
aTe shown for only one gate. The other gates are
tested in the same manner.
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Characteristic
Symbol
Power Supply Drain Current
Input Current
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Pin
Under
Test
VIHmax
Logic 1
(VCC)
Gnd
8
9
8
1,16
12
5,6,10,11
7
9
8
8
8
8
1, t6
1,16
1,16
1,16
linL
All
8
1,16
VOH
3,14(3.)
2,4,13,15(2.)
5,6,10,11
8
8
1,16
1,16
5,6,10,11
9
8
8
1,16
1,16
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
Notel.
VOL
3,14(2.)
2,4,13,15 (3.)
Threshold Voltage
Logic 1
VOHA
2,4,13,15 (2.)
3,14(3.)
13,15(2.)
Switching Times
VEE
12
5,6,10,11
7
Logic 0
Logic 0
VILAmax
IE
Output Voltage
Threshold Voltage
VIHAmin
linH
9
Output Voltage
VILmin
VOLA
9
5,6,10,11
9
7,12
2,4,13,15 (3.)
3,14(2.)
13,15(3.)
5,6,10,11
7,12
8
8
8
Pulse In
Pulse Out
9
(son load)
-3.2 V
+2.0 V
tI2+15+
tI2+14+
t7+13+
17+4+
t7+2+
t7+3+
15
14
13
4
2
3
12
12
7
7
7
7
15
14
13
4
2
3
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
tI2+15tI2+1417+13t7+417+2t7+3-
15
14
13
4
2
3
12
12
7
7
7
7
15
14
13
4
2
3
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
Set Delay
tll+15+
tll+l4-
15
14
11
11
15
14
8
8
1,16
1,16
Reset Delay
t9+14+
t9+15-
14
15
9
9
14
15
8
8
1,16
1,16
Propagation Delay
Clock Delays
Rise Time
(20 to 80%)
t14+
t15+
14
15
11
11
14
15
8
8
1,16
1,16
Fall Time
(20 to 80%)
tl4tl5-
14
15
9
9
14
15
8
8
1,16
1,16
fcount
2
15
7
12
2
15
8
8
1,16
1,16
Counting Frequency
..
1. IndiVidually test each Input; apply VILmin to pin under test.
2. Set all four flip-flops by applying pulse
JLJL-
VIHmax
VILmin
-
3. Reset all four flip-flops by applying pulse
MEClData
Dl122-Rev6
-
VIHmax
VILmin
to pins 5, 6, 10, and 11 prior to applying test voltage indicated.
to pin 9 prior to applying test voltage indicated.
3-93
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Four Bit Universal Shift
Register
MC10141
The MC1 0141 is a four-bit universal shift register which performs shift left, or
shift right, serial/parallel in, and seriaVparaliel out operations with no external
gating. Inputs S1 and S2 control the four possible operations of the register
without external gating of the clock. The flip-flops shift information on the
positive edge of the clock. The four operations are stop shift, shift left, shift right,
and parallel entry of data. The other six inputs are all data type inputs; four for
parallel entry data, and one for shifting in from the left (OL) and one for shifting
in from the right (DR).
-, .
•
=
Po 425 mW typ/pkg (No Load)
fShift = 200 MHz typ
tr, tf = 2.0 ns typ (20%-80%)
LOGIC DIAGRAM
02
DO
01
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
P SUFFIX
PLASTIC PACKAGE
CASE 641Hl8
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
81 ~~}-~==~=---~--------~--------~
82
VeC1
03
02
co
01
VCC1 =PINl
VCC2= PIN 16
VEE=PIN8
VCC2
02
01
03
00
C
OL
OR
00
03
01
82
81
VEE
02
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6--11.
TRUTH TABLE
SELECT
OUTPUTS
S1
S2
OPERATING MOOE
L
L
Parallel Entry
00n+1
00
01n+1
01
02n+1
02
03n+1
03
L
H
Shift Right'
01n
02n
03 n
OR
H
L
Shift Left'
OL
OOn
01n
02n
H
H
Stop Shift
OOn
01n
02n
03 n
..
*Qutputs as eXist after pulse appears at "e" ,"put With Input conditions as
shown. (Pulse = Positive transition of clock input).
3/93
© Molorola, Inc. 1996
3-94
REVS
®
MOTOROI.A
MC10141
SHIFT FREQUENCY TEST CIRCUIT
VCC1 =VCC2
+2.0VOC
COAX
25UF,+
VOUT
,+0.1I'F
Coax
All input and output cables to the
scope are equal lengths of 5<1-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin and
TPout to output pin.
16
INPUT
QO
PULSE GENERATOR
DO
01
5<1-ohm termination to ground
located in each scope channel input.
TEST PROCEDURES:
1. SET 01, 02, 03 = +0.31 VOC (LOGIC L)
00=+1.11 VDC(LOGICH)
Q1
02
03
2. APPY CLOCK PULSEn-~IH TO SET QO HIGH.
3. MAINTAIN CLOCK LOW.
IL
SET S1 = +0.31 VOC (LOGIC L)
S2 = +1.11 VOC (LOGIC H)
Q2
S1
03
4. TEST SHIFT FREQUENCY
VEE = -3.2VOC
MECLData
DL122-Rev6
3-95
MOTOROLA
MC10141
ELECTRICAL CHARACTERISTICS
Test limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
112
linH
5
6
7
4
350
350
390
425
-ao°c
Min
+25°C
Max
Min
+B5°C
Typ
Max
Max
Unit
82
102
112
mAde
220
220
245
265
220
220
245
265
!.lAdc
Min
linL
12
0.5
Output Voltage
Logic 1
VOH
3
-1.060
--{).890
--{).960
--{).81 0
--{).890
--{).700
Vdc
Output Voltage
Logic 0
VOL
3
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
(Note 1.)
3
3
3
3
-1.080
-1.080
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
(Note 1.)
3
3
3
3
4+3+
t12+4+
tl0+4+
t4+12+
3
14
14
14
1.7
2.5
5.5
1.5
3.9
Switching TImes
0.3
0.5
--{).980
--{).980
--{).980
--{).980
!.lAdc
--{).91 0
--{).91 0
--{).910
--{).91 0
-1.630
-1.630
-1.630
-1.630
-1.655
-1.655
-1.655
-1.655
Vdc
-1.595
-1.595
-1.595
-1.595
(500 Load)
Propagation Delay
Setup Time (tsetup)
Hold TIme (thold)
ns
1.8
2.5
5.0
1.5
2.9
3.8
2.0
2.5
5.5
1.5
4.2
Rise TIme
(20 to 80%)
t3+
3
1.0
3.4
1.1
2.0
3.3
1.1
3.6
FaUTIme
(20 to 80%)
1:3-
3
1.0
3.4
1.1
2.0
3.3
1.1
3.6
150
200
Shift Frequency
Vdc
fshift
1. These tests to be performed in sequence as shown.
150
P~-VIH
-VIL
P2 n - V I H A
-.J L-VIL
MHz
150
P 3 n - ,VILA
-.J L _ VIL
2. See shift frequency test circuit for test procedures.
3. Reset to zero before performing test.
4. Reset to one before performing test.
MOTOROLA
3-96
MECLData
DL122-Rev6
MC10141
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-3O°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
5
6
7
4
5
6
7
4
linL
12
4,5,6,7,9,
10,11,13
6
Output Voltage
Logic 1
VOH
3
Output Voltage
Logic 0
VOL
3
Threshold Voltage
Logic 1
VOHA
(Note 1.)
3
3
3
3
Threshold Voltage
Logic 0
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VOLA
(Note 1.)
3
3
3
3
VILmin
Hold Time (thold)
VILAmax
12
6
6
6
Note 3.
Note3.
Note 4.
Note 4.
6
Switching Times (SOn Load)
Propagation Delay
Setup Time (tsetup)
VIHAmin
7
6
7
VEE
Pl
P2
P3
(VCC)
Gnd
8
1,16
8
8
8
8
1,16
1,16
1,16
1,16
8
1,16
8
4
1,16
8
4
1,16
8
8
8
8
4
4
4
1,16
1,16
1,16
1,16
8
8
8
8
4
4
4
1,16
1,16
1,16
1,16
-3.2 V
4
4
+2.0 V
'----
4+3+
t12+4+
tl0+4+
t4+12+
3
14
14
14
8
8
8
8
1,16
1,16
1,16
1,16
Rise Time
(20 to 80%)
t3+
3
8
1,16
Fall Time
(20 to 80%)
t3-
3
8
1,16
8
1,16
Shift Frequency
fshift
1. These tests to be performed in sequence as shown.
Note 2.
P~-VIH
-VIL
2. See shift frequency test circuit for test procedures.
3. Reset to zero before performing test.
4. Reset to one before performing test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5()-Qhm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-97
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Latch
MC10153
The MC10153 is a high speed, low power, MECL quad latch consisting of
four bistable latch circuits with 0 type inputs and gated Q outputs. Open
emitters allow a large number of outputs to be wire-ORed together. Latch
outputs are gated, allowing direct wiring to a bus. When the clock is low, outputs
will follow 0 inputs. Information is latched on positive going transition of the
clock. The MC10153 provides the same logic function as the MC10133, except
for inversion of the clock.
-•
Po = 310 mW typ/pkg (No Load)
tpd
tr, tf
=4.0 ns typ
=2.0 ns typ (20%-80%)
LOGIC DIAGRAM
00
3
2 00
GO 5
01
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
6 01
7
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
CE
VCC1
Cc 13
CE
12
02
11 02
Gf 10
03
00
03
CE
Cc
GO
CE
15 03
03 14
VCC1 =PIN1
VCC2=PIN 16
VEE = PIN 8
G
C
0
H
L
L
L
X
H
L
L
X
X
L
H
01
02
01
Gf
VEE
02
Pin assignment Is for Dual-ln-Une Package.
For PlCC pin assignment, see the Pin Conversion
Tables on page 6--11.
TRUTH TABLE
On+1
L
On
L
H
3193
© Motorola, Inc. 1996
VCC2
QO
3-98
REV 5
®
MOTOROI.A
MC10153
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
Max
Unit
IE
S
83
75
83
mAdc
linH
3
4
5
13
390
390
560
460
245
245
350
290
245
245
350
290
!lAdc
-30'C
Min
+S5'C
+25'C
Max
Min
Typ
Max
Min
linL
3
0.5
Output Voltage
Logic 1
VOH
2
2
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-o.S90
-0.890
-0.700
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
2
2
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.650
-1.650
-1.650
-1.825
-1.S25
-1.825
-1.615
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
2
2
2t
2:j:
2:j:
2
2
-1.080
-1.080
-1.080
-1.0S0
-1.080
-1.080
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
2
2
2t
2:j:
2:j:
t3+2+
t4-2+
t5-2+
tsetup
thold
2
2
2
3
3
1.0
1.0
1.0
2.5
1.5
5.6
5.6
3.2
1.0
1.0
1.0
2.5
1.5
4.0
4.0
2.0
0.7
0.7
5.4
5.6
3.1
1.1
1.2
1.0
2.5
1.5
Switching Times
0.3
0.5
frAdc
-0.910
-0.910
-0.910
-0.910
-0.910
-0.910
-0.910
-0.910
-0.980
-0.980
-0.980
-0.980
-0.980
-0.980
-0.980
-0.980
-1.655
-1.655
-1.655
-1.655
-1.655
-1.655
-1.630
-1.630
-1.630
-1.630
-1.630
-1.630
Vdc
-1.595
-1.595
-1.595
-1.595
-1.595
-1.595
(50n Load)
Propagation Delay
Vdc
ns
5.9
6.2
3.4
Rise Time
(20 to 80%)
t2+
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
Fall Time
(20 to 80%)
t2-
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
t Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)
~
-
VIHmax
VILmin
:j: Data input at proper high/low level while clock pulse is high so that device latches ar proper higMow level for test. Levels are measured after
device has latched .
• Latch set to zero state before test.
MECLData
DL122- Rev 6
3-99
MOTOROLA
MC10153
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmin
VIHAmln
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
3
4
5
13
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmln
VILAmax
13
3
4
5
13
VEE
(VCC)
Gnd
8
1,16
8
8
8
8
1,16
1,16
1,16
1,16
linL
3
3
8
1,16
Output Voltage
Logic 1
VOH
2
2
3
3
4
13
8
8
1,16
1,16
Output Voltage
Logic 0
VOL
2
2
2
3,5
3,13
13
3,4
8
8
8
1,16
1,16
1,16
8
B
8
8
B
8
B
B
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
Threshold Voltage
Threshold Voltage
Switching TImes
Logic 1
Logic 0
VOHA
VOLA
2
2
2
2t
2*
2*
2
2
2
2
2
2t
2*
2:/:
(50n Load)
Propagation Delay
3
3
3
t3+2+
4-2+
t6-2+
tsetup
thold
5
3
4
13
3
3
3
13
B
8
B
B
B
B
Pulse In
Pulse Out
-3.2 V
+2.0 V
3
4
5
3
3
2
2
2
2
2
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
4
4
4
5
3
3
3
+1.11 V
2
2
2
3
3
4
4
4
3"
Rise TIme
(20 to 80%)
t2+
2
3
2
8
1,16
Fall Time
(20 to 80%)
t2-
2
3
2
8
1,16
t Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)
JL-
-
VIHmax
VILmin
* Data input at proper high/low level while clock pulse is high so that device latches ar proper high/iow level for test. Levels are measured after
device has latched.
" Latch set to zero state before test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-0hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-100
MECL Data
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Binary Counter
MC10154
The MC10154 is a four-bit counter capable of divide-by-two, divide-byfour, divide-by-eight or a divide-by-sixteen function.
Clock inputs trigger on the positive going edge of the clock pulse. Set and
Reset inputs override the clock, allowing asynchronous "set" or "clear."
Individual Set and common Reset inputs are provided, as well as complementary outputs for the first and fourth bits. True outputs are available at all bits.
LSUFFIX
=
=
PD
370 mW typ/pkg (No Load)
ftoggle = 150 MHz (typ)
tpd
3.5 ns typ (C to 00)
tpd = 11 ns typ (C to 03)
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
LOGIC DIAGRAM
11
so
81
Q()
15
01
82
1S
7
8S
02
5
4
6
2
os
PIN ASSIGNMENT
VCC1
12
Clock 1
10
Clock 2
9
Reset
--_--+---.....------._------'
VCC1 = PIN 1
VCC2= PIN16
VEE = PIN 8
14 00
s Os
VCC2
03
00
Q3
00
Q2
01
S3
CLOCK 1
82
80
Sl
VEE
CLOCK 2
RESET
TRUTH TABLE
INPUTS
S2
S3
R
SO
S1
H
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OUTPUTS
Q1
Q2
C1
C2
QO
X
X
H
X
X
X
X
H
L
H
L
L
H
H
No Count
No Count
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
··
··
··
··
··
··
··
··
··
··
··
···
··
··
···
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L'
L
Q3
• Clock transitions from VIL to VIH may be applied to C1 or C2 or
~ VIH
both for same effect.
VIL
3/93
© Motorola, Inc. 1996
3-101
REVS
®
MOTOROL.A
[3J
MC10154
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
Max
Unit
IE
8
97
88
97
mAdc
linH
12
11
9
390
350
650
245
220
410
245
220
410
IlAdc
-30°C
Min
+25°C
Max
Min
Typ
+85°C
Max
Min
.
0.5
Output Voltage
Logic 1
VOH
14
15
-1.060
-1.060
-{J.890
-{J.890
-{J.960
-{J.960
-0.810
-{J.810
-{J.890
-0.890
-{J.700
-{J.700
Vdc
Output Voltage
Logic 0
VOL
14
15
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
3
14
15
-1.080
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
3
14
15
linL
Switching Times
0.5
0.3
-{J.980
-{J.980
-{J.980
IlAdc
-{J.91 0
-{J.91 0
-0.910
-1.630
-1.630
-1.630
-1.655
-1.655
-1.655
Vdc
-1.595
-1.595
-1.595
Vdc
ns
(500 Load)
Clock Input
Propagation Delay
t12+15+
t12-13t12+4t12-3+
15
13
4
3
1.4
1.9
2.9
3.9
5.0
9.4
12.3
14.9
1.5
2.0
3.0
4.0
3.5
6.0
8.5
11.0
4.8
9.2
12.0
14.5
1.5
2.0
3.0
4.0
5.3
9.8
12.8
15.5
Rise Time
(20 to 80%)
t15+
15
1.1
4.7
1.1
2.5
4.5
1.1
5.0
Fall Time
(20 to 80%)
t15-
15
1.1
4.7
1.1
2.5
4.5
1.1
5.0
tll-15+
t9-15+
15
15
1.4
1.4
5.2
5.2
1.5
1.5
5.0
5.0
1.5
1.5
5.5
5.5
fcount
15
125
Set Input
Reset Input
Counting Frequency
..
125
150
125
MHz
• IndIvIdually test each Input applYIng VIL to Input under test.
MOTOROLA
3-102
MECL Data
DL122-Rev6
MC10154
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30°C
--{l.890
-1.890
-1.205
-1.500
-5.2
Symbol
Power Supply Drain Current
Input Current
+25°C
--{l.81 0
-1.850
-1.105
-1.475
-5.2
+85°C
--{l.700
-1.825
-1.035
-1.440
-5.2
Pin
Under
Test
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
IE
8
9
8
1,16
linH
12
11
9
12
11
9
8
8
8
1,16
1,16
1,16
8
1,16
9
11
8
8
1,16
1,16
11
9
8
8
1,16
1,16
8
8
8
1,16
1,16
1,16
5
11
9
8
8
8
1,16
1,16
1,16
Pulse In
Pulse Out
-3.2 V
+2.0V
12
12
12
12
15
13
4
3
8
8
8
8
1,16
1,16
1,16
1,16
linL
.
Output Voltage
Logic 1
VOH
14
15
Output Voltage
Logic 0
VOL
14
15
Threshold Voltage
Logic 1
VOHA
3
14
15
Threshold Voltage
Logic 0
VOLA
3
14
15
Switching Times
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
.
5
11
9
(50n Load)
Clock Input
Propagation Delay
t12+15+
t12-13t12+4t12-3+
15
13
4
3
Rise Time
(20 to 80%)
t15+
15
12
15
8
1,16
Fall Time
(20 to 80%)
tl5-
15
12
15
8
1,16
tll-l5+
t9-15+
15
15
11
9
t5
15
8
8
1,16
1,16
fcount
15
12
15
8
1,16
Set Input
Reset Input
Counting Frequency
..
• IndiVidually test each Input applYing VIL to Input under test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, aiter thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-103
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-lnput Multiplexer
(Non-Inverting)
MC10158
The MC10158 is a quad two channel multiplexer. A common select input
determines which data inputs are enabled. A high (H) level enables data inputs
000,010,020, and 030 and a low (L) level enables data inputs 001,011,021,
and 031.
-•
Po = 197 mW typ/pkg (No Load)
= 2.5 ns typ (Oata to 0)
3.2 ns typ (Select to 0)
Ir, If = 2.5 ns typ (20%-80%)
tpd
LOGIC DIAGRAM
SELECT9
001 5
LSUFFIX
CERAMIC PACKAGE
CASE 62G-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
100
000 6
011 3
[1J
2 01
010 4
021 12
1502
020 13
031 10
1403
00
VCC
01
02
011
03
010
020
001
021
000
030
NC
031
VEE
SELECT
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
03011
VCC~PIN
16
VEE ~ PIN 8
TRUTH TABLE
Select
DO
X
01
L
Q
L
L
X
H
H
H
L
X
L
H
H
X
H
L
3/93
© Motorola, Inc. 1996
3-104
REVS
®
MOTOROLA
MC10158
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
53
linH
9
5
360
400
-30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
38
48
53
mAdc
225
250
225
250
!lAdc
Min
linL
5
0.5
VOH
1
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Logic 0
VOL
1
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
1
-1.080
Threshold Voltage
Logic 0
VOLA
1
-1.595
Vdc
Output Voltage
Logic 1
Output Voltage
0.5
0.3
-0.910
-0.980
-1.630
-1.655
Switching Times
(SOn Load)
Propagation
Delay
Data Input
Select Input
t5-1t9+1+
1
1
1.3
2.5
3.1
4.8
Rise Time
(20 to 80%)
tl+
1
1.6
Fall Time
(20 to 80%}
t1-
1
1.6
!lAdc
Vdc
ns
1.2
2.4
2.5
3.2
3.0
4.5
1.3
2.5
3.2
4.8
3.4
1.5
2.5
3.3
1.6
3.4
3.4
1.5
2.5
3.3
1.6
3.4
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmln
VIHAmin
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
9
5
linL
5
Output Voltage
Logic 1
VOH
1
Output Voltage
Logic 0
VOL
1
Threshold Voltage
Logic 1
VOHA
1
Logic 0
VOLA
1
Threshold Voltage
Switching Times
(50nLoad)
Propagation Delay
Data Input
Select Input
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
1
1
VIHAmin
VILAmax
9
5
5
5
5
+1.11V
t5-1t9+1+
VILmin
6
+0.31V
VEE
(VCC)
Gnd
8
16
8
8
16
16
8
16
8
16
8
16
8
16
5
8
16
Pulse In
Pulse Out
-3.2 V
+2.0 V
5
9
1
1
8
8
16
16
Rise Time
(20t080%)
tl+
1
5
1
8
16
Fall Time
(20 to 80%}
tI-
l
5
1
8
16
..
..
Each MECL 10,000 series CirCUit has been deSigned to meet the dc specifications shown In the test table, after thermal eqUiltbrlum has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5Q--ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122- Rev 6
3-105
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-lnput Multiplexer
(Inverting)
MC10159
The MC1 0159 is a quad two channel multiplexer with enable. It incorporates
common enable and common data select inputs. The select input determines
which data inputs are enabled. A high (H) level enables data inputs 000, 010,
020, and 030. A low (L) level enables data inputs 001, 011, 021, and 031. Any
change on the data inputs will be reflected at the outputs while the enable is low.
Input levels are inverted at the output.
Po =
-,.
•
218 mW typ/pkg (No Load)
= 2.5 ns typ (Data to 0)
3.2 ns typ (Select to 0)
tr, tf = 2.5 ns typ (20%-80%)
tpd
LOGIC DIAGRAM
SELECT
9
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-10
PSUFFIX
PLASTIC PACKAGE
CASE64~8
FNSUFFIX
PLCC
CASE 77S-02
DIP
PIN ASSIGNMENT
001 5
000 6
011 3
Qlj
VCC
Of
Q2
011
Q3
010
020
001
021
DOO
030
010 4
ENABLE
7
ENABLE
021 12
VEE
02013
031
SELECT
Pin assignment is for Dual-in-LJne Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
031 10
03011
TRUTH TABLE
Enable
L
L
L
L
H
Select
L
L
H
H
X
DO
X
X
L
H
X
01
Q
L
H
X
X
X
H
VCC=PIN 16
VEE = PIN 8
L
H
L
L
3/93
© Motorola, Inc. 1996
3-106
REV5
®
MOTOROI.A
MC10159
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
58
linH
9
5
360
400
--30'C
Min
+25'C
Max
Min
+85'C
Typ
Max
Max
Unit
42
53
58
mAdc
225
250
225
250
I1Adc
Min
linL
5
0.5
Output Voltage
Logic 1
VOH
1
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Output Voltage
Logic 0
VOL
1
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Threshold Voltage
Logic 1
VOHA
1
-1.080
Logic 0
VOLA
1
t5+1t9+1t7+1-
1
1
1
1.1
1.5
1.4
3.8
5.3
5.3
1.2
1.5
1.5
2.5
3.2
2.5
3.3
5.0
5.0
1.1
1.5
1.4
3.8
5.3
5.3
Threshold Voltage
SWitching Times
Propagation
Delay
0.5
0.3
I1Adc
-0.910
-0.980
-1.630
-1.655
Vdc
Vdc
-1.595
(50n Load)
Data Input
Select Input
Enable Input
Vdc
Vdc
ns
Rise lime
(20 to 80%)
tl+
1
1.0
3.7
1.1
2.5
3.5
1.0
3.7
Fall Time
(20 to 80%)
ti-
l
1.0
3.7
1.1
2.5
3.5
1.0
3.7
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
Symbol
Power Supply Drain Current
Input Current
VIHmax
VILmin
VIHAmin
VILAmax
VEE
--30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+85'C
-0.700
-1.825
-1.035
-1.440
-5.2
Pin
Under
Test
IE
8
linH
9
5
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
linL
5
Logic 1
VOH
1
Output Voltage
Logic 0
VOL
1
5
Threshold Voltage
Logic 1
VOHA
1
9
Logic 0
VOLA
1
Switching limes
Propagation Delay
(50n Load)
Data Input
Select Input
Enable Input
1
1
1
VILAmax
5
9
+1.11V
t5+1t9+11]+1-
VIHAmln
9
5
Output Voltage
Threshold Voltage
VILmln
6
3,12
(VCC)
Gnd
8
16
8
8
16
16
8
16
8
16
8
16
6
8
16
8
16
Pulse In
Pulse Out
--3.2 V
+2.0 V
5
9
7
1
1
1
8
8
16
16
6
+0.31V
VEE
Rise lime
(20 to 80%)
tl+
1
9
5
1
8
16
Fall lime
(20 to 80%)
ti-
l
9
5
1
8
16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122- Rev 6
3-107
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
12-Bit Parity Generator-Checker
MC10160
The MC10160 consists of nine Exclusive-OR gates in a single package.
internally connected to provide odd parity checking or generation. Output goes
high when an odd number of inputs are high. Unconnected inputs are pulled to
low logic levels allowing parity detection and generation for less than 12 bits.
PD = 320 mW typ/pkg (No Load)
tpd 5.0 ns typ
t r• tf 2.0 ns typ (20%-80%)
-
=
=
LOGIC DIAGRAM
3---""--4-"",,-_
5---""--6-"",,-_
LSUFFIX
CERAMIC PACKAGE
CASE 62D-l0
PSUFFIX
PLASTIC PACKAGE
CASE 64S-QS
PIN ASSIGNMENT
7---""--9-'H...._
10---""--11-"",,-_
12---""--13-"",,-_
14---""--15-"",,-_
VCCI
OUT
VCCI =PIN 1
VCC2=PIN 16
VEE = PINS
INPUT
OUTPUT
Sumo!
High Level
Inputs
Pin 2
Even
Low
Odd
High
9/96
© Motorola, Inc. 1996
3-108
REV 6
VCC2
IN12
INI
IN11
IN2
IN10
IN3
IN9
IN4
INS
IN5
IN7
VEE
IN6
®
MOTOROLA
MC10160
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
'E
8
86
linH
(Note 1.)
3
4
425
350
-3DoC
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
62
78
86
mAde
265
220
265
220
!lAde
Min
linL
3
0.5
Output Voltage
Logic 1
VOH
2
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vde
Output Voltage
Logic 0
VOL
2
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vde
Threshold Voltage
Logic 1
VOHA
2
-1.080
Threshold Voltage
Logic 0
VOLA
2
t3+2+
t3+2t3--213-2+
t4+2+
4+24-214-2+
2
2
2
2
2
2
2
2
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
8.1
8.1
8.1
8.1
8.1
8.1
8.1
8.1
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Switching Times
0.5
0.3
!lAde
-0.910
-0.980
-1.630
-1.655
Vde
-1.595
(SOn Load)
Propagation Delay
Vdc
ns
Rise Time
(20 to 80%)
t2+
2
1.1
3.5
1.1
2.0
3.3
1.0
3.5
Fal/Time
(2010 80%)
t2-
2
1.1
3.5
1.1
2.0
3.3
1.0
3.5
1. PinS 3,6,7,11,12,15 are similar. Pins 4, 5, 9,10,13,14 are similar.
MECLDala
DL122-Rev6
3--109
MOTOROLA
MC10160
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmin
VIHAmln
VILAmax
VEE
--30°C
--{J.890
-1.890
-1.205
-1.500
--5.2
+25°C
--{J.81 0
-1.850
-1.105
-1.475
-5.2
+85°C
--{J.700
-1.825
-1.035
-1.440
--5.2
Symbol
Pin
Under
Test
IE
8
linH
(Note 1.)
3
4
linL
3
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VEE
(VCC)
Gnd
4,5,9,
10,13,14
8
1,16
3
4
8
8
1,16
1,16
3
8
1,16
4,5,6,7,9,10,
11,12,13,14,15
8
1,16
8
1,16
8
1,16
VIHmax
VILmln
Output Voltage
Logic 1
VOH
2
Output Voltage
logic 0
VOL
2
3,4,5,6,7,9,10,
11,12,13,14,15
Threshold Voltage
logic 1
VOHA
2
4,5,6,7,9,10,
11,12,13,14,15
Threshold Voltage
Logic 0
VOLA
2
3,5,6,7,9,10,
11,12,13,14,15
Switching TImes
(500 load)
Propagation Delay
3
+1.11V
t3+2+
ta+2ta-2ta--2+
4+2+
t4+24-24-2+
2
2
2
2
2
2
2
2
4
4
3
3
VIHAmin
VILAmax
3
4
8
1,16
Pulse In
Pulse Out
--3.2 V
+2.0 V
3
3
3
3
4
4
4
4
2
2
2
2
2
2
2
2
8
8
B
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,16
Rise Time
(20 to 80%)
t2+
2
3
2
8
1,16
Fall TIme
(20 to 80%)
t2-
2
3
2
8
1,16
1. PinS 3,6,7,11,12,15 are similar. Pins 4,5,9,10,13,14 are similar.
Each MECl 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5D-ohm resistor to -2.0 volts. Test proced.ures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-110
MEClData
Dl122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Binary to 1-8 Decoder (Low)
MC10161
The MC10161 is designed to decode a three bit input word to a one of eight
line output. The selected output will be low while all other outputs will be high. The
enable inputs, when either or both are high, force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders. This design provides
the identical 4 ns delay from any address or enable input to any output.
A complete muxldemux operation on 16 bits for data distribution is illustrated
in Figure 1. This system, using the MC10136 control counters, has the
capability of incrementing, decrementing or holding data channels. When both
SO and 81 are low, the index counters reset, thus initializing both the mux and
demux units. The four binary outputs of the counter are buffered by the
MC10101s to send twisted-pair select data to the multiplexer/demultiplexer to
units.
-, .
•
PD = 315 mW typ/pkg (No Load)
tpd = 4.0 ns typ
t r, tf 2.0 ns typ (20%-80%)
=
PSUFFIX
PLASTIC PACKAGE
CASE 64S-oS
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
LOGIC DIAGRAM
soo
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-10
VCC1 =PIN 1
VCC2 = PIN 16
VEE = PINS
VCC1
501
EO
402
VCC2
E1
03
C
02
04
13 Q4
01
05
1205
00
06
A
07
303
11 OS
10
VEE
Q7
B
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
TRUTH TABLE
ENABLE
INPUTS
INPUTS
OUTPUTS
E1
EO
C
B
A
00
01
02
03
04
05
06
07
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
X
X
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
3193
© Molorola, Inc. 1996
3-111
REVS
®
MOTOROLA
MC10161
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
linH
14
linL
14
0.5
VOH
13
13
-1.060
-1.060
-{l.890
-{l.890
-{l.960
-{l.960
-{l.81 0
-{l.81 0
-{l.890
-{l.890
-{l.700
-{l.700
-1.675
-1.850
-1.650
-1.825
-1.615
+2SoC
-3O°C
Min
Max
Min
84
+BSoC
Typ
Max
61
76
350
Min
220
Max
Unit
84
mAdc
220
0.3
0.5
Output Voltage
Logic 1
Output Voltage
Logic 0
VOL
13
-1.890
Threshold Voltage
Logic 1
VOHA
13
13
-1.080
-1.080
Logic 0
VOLA
13
t14+13tl4-13+
13
13
1.5
1.5
6.2
6.2
1.5
1.5
4.0
4.0
6.0
6.0
1.5
1.5
6.4
6.4
Threshold Voltage
-{l.980
-{l.980
-{l.91 0
-{l.91 0
-1.655
-1.630
Propagation Delay
Vdc
Vdc
Vdc
-1.595
(50n Load)
Switching Times
JlAdc
JlAdc
Vdc
ns
Rise Time
(20 to 80%)
t13+
13
1.0
3.3
1.1
2.0
3.3
1.1
3.5
Fall Time
(20 to 60%)
tl3-
13
1.0
3.3
1.1
2.0
3.3
1.1
3.5
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Symbol
Power Supply Drain Current
Input Current
VILmin
VIHAmln
VILAmax
VEE
-3O°C
-{l.690
-1.690
-1.205
-1.S00
-5.2
+2SoC
-{l.61 0
-1.650
-1.105
-1.475
-5.2
+BSoC
-{l.700
-1.625
-1.035
-1.440
-5.2
Pin
Under
Test
VIHmax
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VEE
(VCC)
Gnd
6
2,7,9,14,15
8
1,16
14
6
1,16
8
1,16
8
8
1,16
1,16
2
15
Logic 0
VOL
13
14
Logic 1
VOHA
13
13
14
Logic 0
VOLA
13
2
15
14
(50nLoad)
Propagation Delay
VILAmax
14
13
13
Output Voltage
VIHAmln
IE
14
Threshold Voltage
VILmin
linH
linL
Logic 1
Switching Times
VIHmax
VOH
Output Voltage
Threshold Vo~age
Test Temperature
8
1,16
8
8
1,16
1,16
8
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
t14+13tl4-13+
13
13
14
14
13
13
8
8
1,16
1,16
Rise Time
(20 to 80%)
t13+
13
14
13
8
1,16
Fall Time
(20 to 80%)
t13-
13
14
13
8
1,16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than SOO linear fpm is maintained.
Outputs are terminated through a 50-0hm resistor to -2.0 vo~s. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-112
MECL Data
DL122-Rev6
MC10161
FIGURE 1 -
MECLData
DL122-Rev6
HIGH SPEED 16-BIT MULTIPLEXERIDEMULTIPLEXER
3-113
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Binary to 1-8 Decoder (High)
MC10162
The MC10162 is designed to convert three lines of input data to a
one-of--eight output. The selected output will be high while all other outputs are
low. The enable inputs, when either or both are high, force all outputs low.
The MC10162 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of the two
enable inputs is used as the data input, while the other is used as a data enable
input.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1 olthe MC10161 data sheet.
-•
PD = 315 ns typ/pkg (No Load)
tpd 4.0 ns typ
tr, tf = 2.0 nstyp (200/0-80%)
=
LOGIC DIAGRAM
LSUFFIX
CERAMIC PACKAGE
CASE 62G-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
VCC2
Ef
C
Q4
05
as
Q7
VCC1 = PIN 1
VCC2= PIN 16
B
VEE= PINS
Pin assignment is for DuaHn-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
TRUTH TABLE
INPUTS
OUTPUTS
EO
E1
C
B
A
00
01
02
03
Q4
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
H
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
X
X
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
X
X
L
L
L
as as
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
ID
L
L
L
L
L
L
L
H
L
L
3193
© Motorola. Inc. 1996
3-114
REVS
®
MOTOROLA
MC10162
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
linH
14
linL
14
0.5
-30'C
Min
+25'C
Max
Min
84
+85'C
Typ
Max
61
76
Min
Max
Unit
84
mAdc
220
350
220
0.5
IlAdc
).IAdc
0.3
Output Voltage
Logic 1
VOH
13
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
13
13
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
13
-1.080
Threshold Voltage
Logic 0
VOLA
13
13
-1.595
-1.595
Vdc
tI4+13tl4-13+
13
13
1.5
1.5
6.2
6.2
1.5
1.5
Switching Times
-0.910
-0.980
-1.655
-1.655
-1.630
-1.630
Vdc
(son Load)
Propagation Delay
ns
4.0
4.0
6.0
6.0
1.5
1.5
6.4
6.4
Rise Time
(20 to 80%)
t13+
13
1.0
3.3
1.1
2.0
3.3
1.1
3.5
Fall Time
(20 to 80%)
tl3-
13
1.0
3.3
1.1
2.0
3.3
1.1
3.5
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
Characteristic
Symbol
Power Supply Drain Current
Input Current
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+85'C
-0.700
-1.825
-1.035
-1.440
-5.2
Pin
Under
Test
IE
8
linH
14
linL
14
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
14
14
VEE
(VCC)
Gnd
8
1,16
8
1,16
8
1,16
Output Voltage
Logic 1
VOH
13
14
8
1,16
Output Voltage
Logic 0
VOL
13
13
2
15
8
8
1,16
1,16
Threshold Voltage
Logic 1
VOHA
13
14
8
1,16
Threshold Voltage
Logic 0
VOLA
13
13
2
15
8
8
1,16
1,16
tI4+13+
tl4-13-
13
13
Switching Times
(50n Load)
Propagation Delay
Pulse In
Pulse Out
-3.2 V
+2.0 V
14
14
13
13
8
8
1,16
1,16
Rise Time
(20 to 80%)
t+
13
14
13
8
1,16
Fall Time
(20 to 80%)
t-
13
14
13
8
1,16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-115
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
a-Line Multiplexer
MC10164
The MC1 0164 is a high speed. low power eight-channel data selector which
routes data present at one-of-eight inputs to the output. The data is routed
according to the three bit code present on the address inputs. An enable input
is provided for easy bit expansion.
-,.
•
=
=
PD 310 mW typ/pkg (No Load)
tpd 3.0 ns typ (Data to Output)
t r• tf = 2.0 ns typ (20%-80%)
LOGIC DIAGRAM
A 7
B 9
C 10
Eii86re2
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE641HJ8
FNSUFFIX
PLCC
CASEn5-02
DIP
PIN ASSIGNMENT
15 Z
XO 6
XI
VCC2
5
ENABLE
X2 4
[3J
X3 3
VCC1
Z
X3
X7
X2
X6
X1
X5
X411
X512
VCC1 = PIN 1
VCC2= PIN 16
VEE= PINS
X613
X7 14
XO
X4
A
C
VEE
B
Pin assignment is lor Dual-In-t.ine Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
TRUTH TABLE
ADDRESS INPUTS
ENABLE
C
B
A
Z
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
XO
X1
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
X3
X4
X5
X6
X7
H
X
X
X
L
X2
3193
© Motorola. Inc. 1996
3-116
REV 5
®
MOTOROLA
MC10164
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
linH
2
linL
4
0.5
-30'C
Min
+85'C
+25'C
Max
Min
83
Typ
Max
60
75
425
Min
Max
Unit
83
mAdc
265
265
0.5
IIAdc
0.3
IIAdc
Output Voltage
Logic 1
VOH
15
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
15
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
15
-1.080
Threshold Voltage
Logic 0
VOLA
15
-1.595
Vdc
4+15+
14-15t7+15+
t7-15t2+15t2-15+
15
15
15
15
15
15
1.5
1.5
1.9
1.9
0.9
0.9
4.9
4.9
6.5
6.5
3.5
3.5
1.5
1.5
2.0
2.0
1.0
1.0
3.0
3.0
4.0
4.0
2.0
2.0
4.7
4.7
6.2
6.2
3.1
3.1
1.6
1.6
2.2
2.2
1.0
1.0
5.0
5.0
6.7
6.7
3.3
3.3
Switching Tomes
-0.980
-0.910
Vdc
-1.630
-1.655
(500 Load)
Propagation Delay
ns
Rise Time
(20 to 80%)
t+
15
0.9
3.3
1.1
2.0
3.3
1.2
3.6
Fall Tome
(20 to 80%)
t-
15
0.9
3.3
1.1
2.0
3.3
1.2
3.6
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+85'C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
2
linL
4
Output Voltage
Logic 1
VOH
15
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
4
Logic 0
VOL
15
9
Logic 1
VOHA
15
4,9
Threshold Voltage
Logic 0
VOLA
15
Propagation Delay
VILAmax
4,9
Output Voltage
(500 Load)
VIHAmin
4
Threshold Voltage
Switching Times
VILmin
2
9
VEE
(Vccl
Gnd
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
2
8
1,16
+1.11V
Pulse In
Pulse Out
-3.2 V
+2.0 V
4+15+
14-15t7+15+
17-15t2+15t2-15+
15
15
15
15
15
15
9
9
5
5
7,5
7,5
4
4
7
7
2
2
15
15
15
15
15
15
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
1,16
Rise Tome
(20 to 80%)
t+
15
9
4
15
8
Fall Time
(20 to 80%)
t-
15
9
4
15
8
..
..
1,16
Each MECL 10,000 senes CirCUit has been designed to meet the dc specifications shown In the tesl table, after thermal eqUllibnum has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5G-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-117
MOTOROLA
MC10164
APPLICATION INFORMATION
The MC1 0164 can be used wherever data multiplexing
or parallel to serial conversion is desirable. Full parallel
gating permits equal delays through any data path. The
output of the MC10164 incorporates a buffer gate with
eight data inputs and an enable. A high level on the enable
forces the output low. The MC10164 can be connected
directly to a data bus, due to its open emitter output and
FIGURE 1 -
output enable.
Figure one illustrates how a 1-of-64 line multiplexer
can be built with eight MC10164's wire ORed at their
outputs and one MC10161 to drive the enables on each
multiplexer, without speed degradation over a single
MC1 0164 being experienced.
1-0F-64 LINE MULTIPLEXER
ABC
lout
14
07
MSB
ABC
Q6
[3J
05
lout
Q4
MC10161
as
Q2
Q1
LSB
QO
Zout
ABC
The Bit chosen ;s dependent on six-bit
code present on Inputs 7, 9, 14 of the
MC10161 and the A, B, C Inputs of the
MC10164.
Zou1
ABC
lout
ABC
lout
MOTOROLA
3-118
MECLOata
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
a-Input Priority Encoder
MC10165
The MC1 0165 is a device designed to encode eight inputs to a binary
coded output. The output code is that of the highest order input. Any input
of lower priority is ignored. Each output incorporates a latch allowing
synchronous operation. When the clock is low the outputs follow the
inputs and latch when the clock goes high. This device is very useful for
a variety of applications in checking system status in control processors,
peripheral controllers, and testing systems.
The input is active when high, (e.g., the three binary outputs are low
when input DO is high). The Q3 output is high when any input is high. This
allows direct extension into another priority encoder when more than
eight inputs are necessary. The MC10165 can also be used to develop
binary codes from random logic inputs, for addressing ROMs, RAMs, or
for multiplexing data.
--
=
Po 545 mW typ/pkg (No Load)
tpd = 4.5 ns typ (Data to Output)
tr, tf = 2.0 ns typ (20%-80%)
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 64S-QS
PIN ASSIGNMENT
VCC1
TRUTH TABLE
DATA INPUTS
DO D1 D2 D3 D4 D5 DB
D7
03
H
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
H
L
H
H
H
H
H
H
H
H
L
X
H
L
L
L
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
H
L
L
L
L
L
X
X
X
X
H
L
L
L
L
X
X
X
X
X
H
L
L
L
X
X
X
X
X
X
H
L
L
OUTPUTS
02 01 00
L
L
L
L
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
9/96
© Motorola, Inc: 1996
3-119
REV6
VCC2
01
02
00
03
CLOCK
D2
DO
D5
D7
D4
D1
D3
VEE
DB
®
MOTOROLA
~
MC10165
LOGIC DIAGRAM
C4
DOS
)
017
.2
0213
)-
VCCI = PIN 1
VCC2= PIN 16
VEE.= PINS
1
0310
)
0411
-I
]0--
-L
...,
}-
-L
---L}-
~
D
H.
=!
)
0512
I L.-.t
069
_..L
)
r---'
)
076
~
::::::I
"
)--
>-
-
~ 1502
"\
I-
>-
I
~ 201
.-
J
3-120
300
I-
""
MOTOROLA
l-
r-
-
1403
'--
MECLData
DL122-Rev6
MC10165
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
144
linH
4
5
390
350
linL
4
5
0.5
0.5
-30'C
Min
+25'C
Max
Min
+85'C
Typ
Max
Max
Unit
105
131
144
mAdc
245
220
245
220
!lAdc
0.5
0.5
Min
0.3
0.3
!lAdc
Output Voltage
Logic 1
VOH
2
3
14
15
-1.060
-1.060
-1.060
-1.060
--{).890
--{).890
--{).890
--{).890
-0.960
--{).960
--{).960
--{).960
-0.810
-0.810
--{).81 0
--{).81 0
-0.890
--{).890
-0.890
-0.890
-0.700
--{).700
--{).700
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
3
14
15
-1.890
-1.890
-1.890
-1.890
-1.675
-1.675
-1.675
-1.675
-1.850
-1.850
-1.850
-1.850
-1.650
-1.650
-1.650
-1.650
-1.825
-1.825
-1.825
-1.825
-1.615
-1.615
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
3
14
15
-1.080
-1.080
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
3
14
15
t5+14+
t5-1417+3+
tll+15+
t13+2+
14
14
3
15
2
2.0
2.0
2.0
2.0
2.0
7.0
7.0
7.0
7.0
7.0
3.0
3.0
3.0
3.0
3.0
7.0
7.0
7.0
7.0
7.0
2.0
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
8.0
14-3+
14-14+
14-14-
3(2.)
3(3.)
14(2.)
14(3.)
1.5
1.5
1.5
1.5
4.5
4.5
4.5
4.5
2.0
2.0
2.0
2.0
4.0
4.0
4.0
4.0
1.5
1.5
1.5
1.5
4.5
4.5
4.5
4.5
Setup Time
tsetupH
tsetupL
3
3
6.0
6.0
6.0
6.0
3.4
3.0
6.0
6.0
Hold Time
tholdH
tholdL
3
3
1.0
1.0
1.0
1.0
-2.3
-2.7
1.0
1.0
Switching Times
--{).91 0
-0.910
--{).91 0
-0.910
--{).980
--{).980
--{).980
--{).980
-1.630
-1.630
-1.630
-1.630
-1.655
-1.655
-1.655
-1.655
Vdc
-1.595
-1.595
-1.595
-1.595
ns
(500 Load)
Propagation Delay Data Input
Clock Input
Vdc
i4-3-
Rise Time
(20 to 80%)
t3+
3
1.1
3.5
1.1
2.0
3.3
1.1
3.5
Fall Time
(20 to 80%)
t3-
3
1.1
3.5
1.1
2.0
3.3
1.1
3.5
..
1. The same limit applies for all 0 type Input pins. To test Input currents for other D Inputs, indiVidually apply proper voltage to pin under test.
2. Output latched to low state prior to test.
3. Output latched to high state prior to test.
• To preserve reliable performance, the MCl 0165P (plastic packaged device only) is to be operated in ambienttemperatures above 70'C only when
500 Ifpm blown air or equivalent heat sinking is provided.
MECLData
DL122-Rev6
3-121
MOTOROLA
MC10165
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmin
VIHAmln
VILAmax
VEE
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+85'C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
4
5
linL
4
5
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VEE
(VCC)
Gnd
8
1,16
8
8
1,16
1,16
4
5(1.)
8
8
1,16
1,16
4
4
4
4
8
8
8
8
1,16
1,16
1,16
1,16
8
8
8
8
1,16
1,16
1,16
1,16
8
8
8
8
1,16
1,16
1,16
1,16
6
6
6
6
8
8
8
8
1,16
1,16
1,16
1,16
VILmin
Logic 1
VOH
2
3
14
15
Output Voltage
Logic 0
VOL
2
3
14
15
4
4
4
4
Threshold Voltage
Logic 1
VOHA
2
3
14
15
4
4
4
4
Threshold Voltage
Logic 0
VOLA
2
3
14
15
4
4
Propagation Delay
(500 Load)
VILAmax
4
5(1.)
Output Voltage
Switching Times
VIHAmin
6
6
6
6
6
6
6
6
4
4
+1.11V
+0.31V
Pulse In
Pulse Out
-3.2 V
+2.0
4
4
4
4
4
5
5
7
11
13
14
14
3
15
2
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
7
4
7
4
4
4
3
3
14
14
8
8
8
8
1,16
1,16
1,16
1,16
3
3
4,7
4,7
3
3
8
8
1,16
1,16
3
3
4,7
4,7
3
3
8
8
1,16
1,16
Data Input
t5+14+
t5-1417+3+
tll+15+
t13+2+
14
14
3
15
2
Clock Input
14-3+
t4-314-14+
t4-14-
3(2.)
3(3.)
14(2.)
14(3.)
Setup Time
tsetupH
tsetupL
Hold Time
tholdH
tholdL
Rise Time
(20 to 80%)
t3+
3
4
7
3
8
1,16
Fall Time
(20 to 80%)
!s-
3
4
7
3
8
1,16
1. The same limit applies for all D type input pins. To test input currents for other D inputs, individually apply proper voltage to pin under test.
2. Output latched to low state prior to test.
3. Output latched to high state prior to lest.
• To preserve reliable performance, the MC1 0165P (plastic packaged device only) is to be operated in ambientlemperaturesabove 70'C only when
500 Ifpm blown air or equivalent heat sinking is provided.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, aiter thennal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linearfpm is maintained.
Outputs are terminated through a 50-0hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-122
MECLData
DL122-Rev6
MC10165
connected to this encoder such that, when a given condition
exists, the respective input will be at a logic high level. This
scheme will select the one of 64 different system
conditions, as represented at the encoder inputs, which
has priority in determining the next system operation to be
performed. The binary code showing the address of the
highest priority input present will appear at the encoder
outputs to control other system logic functions.
APPLICATION INFORMATION
A typical application of the MC1 0165 is the decoding of
system status on a priority basis. A 64 line priority encoder
is shown in the figure below. System status lines are
54-LINE PRIORITY ENCODER
LSB
Iz
Iz
MC10164II
1/2MC10101
System
Clock
Highest
Priority
Input
0-:-,
00
0.:.
07
0-;-,
0.:.
~
U
"
DD
0.:.
00
0.:.
0.:.
"
0.:.
01
iii
Q2
ill
'"
0.:.
01
02
03
Q1
iii
02
ill
01
U
02
"
ill
0
U
0-:- 07 '"
MECLData
DL122- Rev 6
03
00
C
,
-
00
ill
0
0-:- DO
r-
0001
02
03
iii
07
07
,
,
02-1-0 MSB
000
0
DD
DO
Q3
ill
C
0-;,
~l
~~ ~
highestprionty
channel present
at input
000
07
DO
-=::
03
ill
C
0-;-,
r::::::=
number of
07
U
DO
01
02
03
Six bit output
wordyieldmg
III
-
C
0-;-,
I
X7 ABC
01
0
07
.......
02
07
DD
II'
III
xo
ill
C
0-;-,
xO ..... X7ABC
U
0
07
MC10164II
X7ABC
aD-
C
0-;-,
Priority
Input
... .
~0:u
C
Lowe~
I xo
Iz
MC10164
03
00
01
Q2
03
3-123
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
5-Bit Magnitude Comparator
MC10166
The MCl 0166 is a high speed expandable 5-bit comparator for comparing
the magnitude of two binary words. Two outputs are provided: A < B and A > B.
A = B can be obtained by NO Ring the two outputs with an additional gate. A
high level on the enable function forces both outputs low. Multiple MC10166s
may be used for larger word comparisons.
-•
PD = 440 mW typ/pkg (No Load)
tpd = D~ta to output 6.0 ns typ
E to output 2.5 ns typ
t r, tf 2.0 ns typ (20%-80%)
=
LOGIC DIAGRAM
A4 9
84 10
LSUFFIX
CERAMIC PACKAGE
CASE 62()-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-B
VCCI
VCC2
A>8
E
A<8
B2
A2 13
B214
3AB
X
L
L
L
Word A = Word B
L
L
L
Word A > Word B
L
H
L
Word A < Word B
H
L
3193
© Motorola, Inc. 1996
3-124
REVS
®
MOTOROLA
MC10166
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
-30°C
Min
+25°C
Max
Min
117
IE
8
linH
5
linL
5
0.5
+85°C
Typ
Max
85
106
350
Min
Unit
117
mAdc
220
220
0.5
Max
0.3
IlAdc
IlAdc
Output Voltage
Logic 1
VOH
2
3
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
3
-1.890
-1.890
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
3
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
3
Data to Output
t9+2+
t9-2tll-2+
tIl +21]+3+
t7-3-
2
2
2
2
3
3
1.0
1.0
1.0
1.0
1.0
1.0
B.O
B.O
8.0
B.O
B.O
8.0
1.0
1.0
1.0
1.0
1.0
1.0
6.0
6.0
6.0
6.0
6.0
6.0
7.6
7.6
7.6
7.6
7.6
7.6
1.0
1.0
1.0
1.0
1.0
1.0
B.4
8.4
8.4
8.4
8.4
B.4
Enable to Output
tI5-3+
tI5+3-
3
3
1.0
1.0
3.8
3.8
1.0
1.0
2.5
2.5
3.6
3.6
1.0
1.0
4.0
4.0
Switching Times
Propagation
Delay
-0.980
-0.980
-0.910
-0.910
-1.630
-1.630
-1.655
-1.655
Vdc
-1.595
-1.595
(50nLoad)
ns
Rise Time
(20 to BO%)
t2+
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
Fall Time
(20 to BO%)
t2-
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
MECLData
DL122- Rev 6
Vdc
3-125
MOTOROLA
MC10166
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Input Current
Test Temperature
VIHmax
VILmln
VIHAmin
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
5
linL
5
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
4,7,10,11,14
5
5
VEE
(VCC)
Gnd
8
1,16
8
1,16
8
1,16
Output Voltage
Logic 1
VOH
2
3
5
4
8
8
1,16
1,16
Output Voltage
Logic 0
VOL
2
3
5,15
4,15
8
8
1,16
1,16
Threshold Voltage
Logic 1
VOHA
2
3
5
4
8
8
1,16
1,16
Threshold Voltage
Logic 0
VOLA
2
3
5
4
15
15
8
8
1,16
1,16
+1.11V
Pulse In
Pulse Out
-3.2 V
+2.0
t9+2+
t9-2tll-2+
t11+2t7+3+
17-3-
2
2
2
2
3
3
12
12
6
6
9
9
11
11
7
7
2
2
2
2
3
3
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
t15-3+
t15+3-
3
3
10
10
15
15
3
3
8
8
1,16
1,16
1,16
Switching Times
Propagation Delay
(50n Load)
Data to Output
Enable to Output
15
15
Rise Time
(20 to 80%)
t2+
2
9
2
8
Fall Time
(20 to 80%)
t2-
2
9
2
8
..
..
1,16
Each MECL 10,000 senes CirCUit has been designed to meet the dc specifications shown In the test table, aiter thermal eqUlhbnum has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-0hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-126
MECL Data
DL122-Rev6
MC10166
APPLICATION INFORMATION
FIGURE 1 - 9-BIT MAGNITUDE
COMPARATOR
AO 60 A1 61 A2 62 A3 53 A4 64
824
A24
823
A23
822
84
A4
620
A20
83
A3 A<8
82
A2
81 A>6
Al
80
AO
819
A19
618
A18
617
A17
616
A16
615
A15
84
A4
63
A3 A<6
62
A2
61 A>8
Al
60
AO
A22
821
A21
614
A14
613
A13
812
A12
811
All
810
Al0
89
A9
AS 65 A6 66 A7 67 AS 68
MC10166
MC10166
A6
AB
A6
Al
60
AO
63
A3 AB
Al
BO
AO
A=6
AB
B4
A4
88
A9
67
A7
66
A6
65
A5
64
A4
83
A3
B2
A2
61
Al
60
AO
83
A3 A<8
82
A2
81 A>6
Al
80
AO
64
A4
63
A3 A<8
82
A2
Bl A>B
Al
60
AO
FIGURE 2 - 25-BIT MAGNITUDE COMPARATOR
MECLData
DL122-Rev6
The MC1 0166 compares the magnitude of two 5-bit
words. Two outputs are provided which give a high level
for A > B and A < B. The A B function can be obtained
by wire-~Ring these outputs (a low level indicates A =
B) or by NORing the outputs (a high level indicates A = B).
For longer word lengths, the MC1 0166 can be serially
expanded or cascaded. Figure 1 shows two devices in
a serial expansion for a 9-bit word length. The A > Band
A < B outputs are fed to the AO and BO inputs
respectively of the next device. The connection for an A
B output is also shown. The worst case delay time of
serial expansion is equal to the number of comparators
times the data-to-output delay.
For shorter delay times than possible with serial
expansion, devices can be cascaded. Figure 2 shows a
25-bit cascaded comparator whose worst case delay is
two data-to--output delays. The cascaded scheme can
be extended to longer word lengths.
=
=
3-127
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Latch
MC10168
The MC10168 is a Quad Latch with common clocking to all four latches.
Separate output enabling gates are provided for each latch, allowing direct
wiring to a bus. When the clock is high, outputs will follow the D inputs.
Information is latched on the negative-going transition of the clock.
PD = 310 mW typ/pkg (No Load)
tpd= GtoQ=2nstyp
DtoQ=3nstyp
CtoQ=4nstyp
t r, If = 2.0 ns typ (200/.-80%)
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
LOGIC DIAGRAM
DO
3
-----""1
PIN ASSIGNMENT
[aJ
VCC1
2 QO
GO 5
hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3-150
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Binary Counter
MC10178
The MC10178 is a four-bit counter capable of divide-by-two,
divide-by-four, divide-by-eight or a divide-by-sixteen function.
Clock inputs trigger on the positive going edge of the clock pulse. Set and
Reset inputs override the clock, allowing asynchronous "set" or "clear."
Individual Set and common Reset inputs are provided, as well as
complementary outputs for the first and fourth bits. True outputs are available at
all bits.
-•
PD = 370 mW Iyp/pkg (No Load)
ftoggle= 150 MHz (typ)
t r, If = 2.7 ns Iyp (20%-80%)
LOGIC DIAGRAM
co
80
11
82
01
81
02
03
83
13
15
12
Clock 1
Clock 2
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PLCC
CASE 775-{)2
DIP
PIN ASSIGNMENT
10
ReselO---4.---+----"*-----.....--------'
14
VCCI
3
ao
03
VCCI =PIN I
VCC2=PIN 16
VEE = PIN 8
TRUTH TABLE
VCC2
03
00
Q3
QO
02
01
S3
CLOCK 1
S2
SO
R
SO
51
52
53
C1
C2
00
01
02
03
81
CLOCK 2
H
L
L
H
L
H
L
H
L
H
X
X
X
X
L
H
L
H
L
H
L
H
VEE
L
L
L
L
L
L
L
L
L
L
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
INPUTS
..
VIL
.-r- VIH
OUTPUTS
**
**
**
**
**
**
**
**
**
....
....
....
..
No Count
No Count
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Pin assignment is for Dual-in-Line Package.
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
For PlCC pin assignment, see the Pin Conversion
Tables on page 6-11.
Clock transition from VIL to VIH may be applied to Cl or C2 or both for
same effect.
3/93
© Motorola. Inc. 1996
RESET
3--151
REV5
®
MOTOROLA
MC10178
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
Max
Unit
IE
8
97
88
97
mAdc
linH
12
11
9
390
350
650
245
220
410
245
220
410
I1Adc
linl
Output Voltage
logic 1
VOH
.
-SO°C
Min
+25°C
Max
0.5
14
15
-1.060
Min
Typ
0.3
0.5
!lAdc
-0.810
-0.810
-0.890
-0.890
-0.700
-0.700
Vdc
-1.060
-0.960
-0.960
-1.675
-1.675
-1.850
-1.850
-1.650
-1.650
-1.825
-1.825
-1.615
-1.615
Vdc
logic 0
VOL
14
15
-1.890
-1.890
Threshold Voltage
logic 1
VOHA
3
14
15
-1.080
-1.080
-1.080
Threshold Voltage
logic 0
VOLA
3
14
15
-0.910
-0.910
-0.910
-0.980
-0.980
-0.980
-1.655
-1.655
-1.655
(500 load)
Propagation
Delay
Clock Input
t12+15+
t12-13t12+4t12-3+
15
13
4
3
1.4
1.9
2.9
3.9
5.0
9.4
12.3
14.9
1.5
2.0
3.0
3.5
6.0
8.5
4.0
Rise Time
(20 to 80%)
t15+
15
1.1
4.7
1.1
Fall Time
(20 to 80%)
t15-
15
1.1
4.7
1.1
t11-15+
t9-15+
15
15
1.4
1.4
5.2
5.2
1.5
1.5
Vdc
-1.595
-1.595
-1.595
-1.630
-1.630
-1.630
Switching Times
Vdc
ns
125
Counting Frequency
15
125
fcount
..
• Individually test each Input applYing Vil to Input under test.
MOTOROLA
Min
-0.890
-0.890
Output Voltage
Set Input
Reset Input
+85°C
Max
3-152
11.0
4.8
·9.2
12.0
14.5
1.5
2.0
3.0
4.0
5.3
9.8
12.8
15.5
2.5
4.5
1.1
5.0
2.5
4.5
1.1
5.0
5.0
5.0
1.5
1.5
5.5
5.5
150
125
MHz
MEClData
Dl122-Rev6
MC10178
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+B5°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Power Supply Drain Current
Input Current
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
IE
8
9
8
1,16
linH
12
11
9
12
11
9
8
8
8
1,16
1,16
1,16
.
.
8
1,16
Output Voltage
Logic 1
VOH
14
15
9
11
8
8
1,16
1,16
Output Voltage
Logic 0
VOL
14
15
11
9
8
8
1,16
1,16
Threshold Voltage
Logic 1
VOHA
3
14
15
8
8
8
1,16
1,16
1,16
Threshold Voltage
Logic 0
VOLA
3
14
15
5
11
9
8
8
8
1,16
1,16
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
t12+15+
tI2-13tI2+4t12-3+
15
13
4
3
12
12
12
12
15
13
4
3
8
8
8
8
1,16
1,16
1,16
1,16
linL
Switching Times
Propagation Delay
5
11
9
(500 Load)
Data Input
Rise Time
(20 to 80%)
t+
15
12
15
8
1,16
Fall Time
(20 to 80%)
t-
15
12
15
8
1,16
tI1-15+
t9-15+
15
15
11
9
15
15
8
8
1,16
1,16
fcount
15
12
15
8
1,16
Set Input
Reset Input
Counting Frequency
..
• IndiVidually test each Input applYing VIL to Input under test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5Q-ohm resistor to -2.0 volts. Test procedures are. shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122- Rev 6
3-153
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Arithmetic Logic Unit/
Function Generator
MC10181
The MC1 0181 is a high-speed arithmetic logic unit capable of performing 16
logic operations and 16 arithmetic operations on two four-bit words. Full
internal carry is incorporated for ripple through operation.
Arithmetic logic operations are selected by applying the appropriate binary
word to the select inputs (SO through 53) as indicated in the tables of
arithmetic/logic functions. Group carry propagate (PG) and carry generate (GG)
are provided to allow fast operations on very long words using a second order
look ahead. The internal carry is enabled by applying a low level voltage to the
mode control input (M).
LSUFFIX
CERAMIC PACKAGE
CASE 623-05
PD = 600 mW typ/pkg (No Load)
tpd (typ): A 1 to F = 6.5 ns
C n to C n + 4 3.1 ns
A 1 to PG 5.0 ns
A1 to GG = 4.5 ns
A1 toC n +4=5.0
=
=
PIN ASSIGNMENT
LOGIC DIAGRAM
13
15
17
14
21
20
18
19
16
11
10
9
22
23
VCC1 = PIN 1
VCC2= PIN 24
VEE=PIN 12
AO
BO
A1
B1
M
F1
CN
GG
AO
CN+4
BO
F3
B1
6
F2
A1
4
PG
Sl
7
A2
B2
A3
B3
Cn
M
8
S3
S2
Sl
SO
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
F=A
F=A+B
F=A+B
F = Logical "1"
F=A.B
F=B
F=A0B
F=A+B
F=A.B
F=AE!)B
F=B
F=A+B
F = Logical "0"
F=A.B
F=A.B
F=A
Arithmetic Operation
M is Low Cn is low
F
F=A
F = A plus (A • B)
F = A plus (A. B)
F=Atimes2
F= (A+ B) plus 0
F= (A+ B) plus (A. B)
F =A plus B
F=Aplus(A+B)
F = (A + B) plus 0
F = A minus B minus 1
F = (A + B) plus (A • B)
F=Aplus(A+B)
F = minus 1 (two's complement)
F=(A.B)minus1
F= (A. B) minus 1
F =A minus 1
9/96
© Motorola, Inc. 1996
VCC2
FO
F1
Logic Functions
M is High C = D.C.
F
Function Select
VCC1
3-154
REV 6
B3
A2
A3
S2
B2
SO
VEE
83
®
MOTOROLA
MC10181
POSITIVE LOGIC DIAGRAM
6313
6215
5117
6014
8020
0--.
.-[>t
ti9=>
.-[>t
ti9=>
A021
8119 ()-<
~
82n ()-<
.-[>t
A21B
63 9
0--.
H>t
A310
~
"-
1-
,
./
8P
J
A118
,,--.,
~- . /
,-
ti9=>
,.--,
"
~
l-n
2FO
,~
~
~
3F1
7F2
,~
./
~
JI
.......
,~./
;::j
-
~
,-
BF3
,
./
~
J
~
~
.......,...
M23
MECLData
DL122-Rev6
3-155
MOTOROLA
MC10181
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Symbol
Pin
Under
Test
Max
Unit
159
145
159
mAde
390
350
390
320
425
425
350
425
350
390
390
350
460
320
245
220
245
200
265
265
220
265
220
245
245
220
290
200
245
220
245
200
265
265
220
265
220
245
245
220
290
200
!lAde
IE
12
Input Current
linH
9
10
11
13
14
15
16
17
18
19
20
21
22
23
Input Leakage Current
linL
9
10
11
13
14
15
16
17
18
19
20
21
22
23
Output Voltage
Logic 1
Output Voltage
Logic 0
VOL
Threshold Voltage
Logic 1
VOHA
Threshold Voltage
Logic 0
VOLA
VOH
·
·
·
·
-30°C
Min
+25°C
Max
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Min
Typ
+85°C
Max
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Min
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
!lAde
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vde
-2.000
-1.675
-1.990
-1.650
-1.920
-1.615
Vde
-0.980
-1.080
-1.655
-0.910
-1.630
Vde
-1.595
Vde
• Test all Input-output combinations according to Funcllon Table .
•• For threshold level test, apply threshold input level to only one input pin at a time.
MOTOROLA
3--156
MECLData
DL122-Rev6
MC10181
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Power Supply Drain Current
Test Temperature
VIHmax
VILmin
VIHAmln
VILAmax
VEE
-30"C
-0.890
-1.890
-1.205
-1.500
-5.2
+25"C
-0.810
-1.850
-1.105
-1.475
-5.2
+85"C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
12
Input Current
linH
9
10
11
13
14
15
16
17
18
19
20
21
22
23
Input Leakage Current
linL
9
10
11
13
14
15
16
17
18
19
20
21
22
23
Output Voltage
Logic 1
VOH
Output Voltage
Logic 0
VOL
Threshold Voltage
Logic 1
VOHA
Threshold Voltage
Logic 0
VOLA
·
·
·
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmln
VILAmax
9
10
11
13
14
15
16
17
18
19
20
21
22
23
.
.
·
9
10
11
13
14
15
16
17
18
19
20
21
22
23
.
.
..
..
..
..
VEE
(VCC)
Gnd
12
1,24
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
12
12
12
12
12
12
12
12
12
12
12
12
12
12
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
1,24
12
1,24
12
1,24
12
1,24
12
1,24
• Test all Input-output combinations according to Function Table .
•• For threshold level test, apply threshold input level to only one input pin at a time.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-0hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-157
MOTOROLA
MC10181
AC Switching Characteristics
-30°C'
+B5°C'
Input
Output
Conditionst
Min
Max
Min
Typ
Max
Min
Max
Unit
Propagation Delay
Rise Time, Fall Time
t++,I-I+,t-
Cn
Cn
Cn+4
Cn+4
AO,A 1,A2,A3
AO,A 1,A2,A3
1.0
1.0
5.1
3.2
1.1
1.0
3.1
2.0
5.0
3.0
1.1
1.0
5.4
3.2
ns
ns
Propagation Delay
I++,t+t-+,I-1+,1-
Cn
Cn
Cn
F1
F1
F1
AO
AO
AO
1.7
1.7
1.3
7.2
7.2
5.3
2.0
2.0
1.5
4.5
4.5
3.0
7.0
7.0
5.0
2.0
2.0
1.5
7.5
7.5
5.3
ns
ns
ns
Rise Time, Fall Time
I++,t+1-+,1-1+,1-
A1
A1
A1
F1
F1
F1
2.6
2.6
1.3
10.4
10.4
5.4
3.0
3.0
1.5
6.5
6.5
3.0
10
10
5.0
3.0
3.0
1.5
10.8
10.B
5.3
ns
ns
ns
Propagalion Delay
Rise Time, Fall Time
1++,1-I+,t-
A1
A1
PG
PG
SO,S3
SO,S3
1.6
O.B
7.0
3.7
2.0
1.1
5.0
2.0
6.5
3.5
2.0
1.1
7.0
3.B
ns
ns
Propagalion Delay
Rise Time, Fall Time
1++,1-1+,1-
A1
A1
GG
GG
AO,A2,A3,Cn
AO,A2,A3,Cn
1.1
1.2
7.4
5.1
2.0
1.5
4.5
4.0
7.0
5.0
1.3
1.2
7.7
5.3
ns
ns
Propagalion Delay
Rise Time, Fall Time
I+-,t-+
I+,t-
A1
A1
Cn+4
Cn+4
AO,A2,A3,Cn
AO,A2,A3,Cn
1.7
1.0
7.3
3.1
2.0
1.0
5.0
2.0
7.0
3.0
2.0
1.0
7.B
3.2
ns
ns
Propagalion Delay
Rise Time, Fall Time
t++,t-+
1+,1-
B1
B1
F1
F1
S3,C n
S3,C n
2.7
1.2
11.3
5.3
3.0
1.5
B.O
3.5
11
5.0
3.0
1.5
11.9
5.3
ns
ns
Propagalion Delay
Rise Time, Fall Time
1++,1-1+,1-
B1
B1
PG
PG
SO,A1
SO,A1
1.6
1.0
7.7
3.6
2.0
1.1
6.0
2.0
7.5
3.5
2.0
1.1
B.O
3.9
ns
ns
Propagalion Delay
Rise Time, Fall Time
1++,1-1+,1-
B1
B1
GG
GG
S3,C n
S3,C n
1.7
1.4
B.2
5.2
2.0
1.5
6.0
3.0
B.O
5.0
2.0
1.2
B.6
5.4
ns
ns
Propagalion Delay
Rise Time, Fall Time
1+-,1-+
1+,1-
B1
B1
Cn+4
Cn+4
S3,C n
S3,Cn
1.B
0.9
B.2
3.1
2.0
1.0
6.0
2.0
B.O
3.0
2.0
1.0
B.7
3.2
ns
ns
Propagalion Delay
Rise Time, Fall Time
t++,t+t+,t-
M
M
F1
F1
-
2.4
1.1
10.3
5.1
3.0
1.5
6.5
4.0
10
5.0
3.0
1.5
10.B
5.3
ns
ns
Propagation Delay
Rise Time, Fall Time
t+-,t-+
1+,1-
S1
S1
F1
F1
A1,B1
A1,B1
2.5
1.0
10.7
5.4
3.0
1.5
6.5
3.0
10
5.0
3.0
1.5
10.B
5.4
ns
ns
Propagalion Delay
Rise Time, Fall Time
I-+,I+1+,1-
S1
S1
PG
PG
A3,B3
A3,B3
1.7
0.8
B.3
5.1
2.0
1.1
6.0
3.0
8.0
5.0
2.0
1.1
8.4
5.2
ns
ns
Propagalion Delay
Rise Time, Fall Time
1+-,1-+
1+,1-
S1
S1
Cn+4
Cn+4
A3,B3
A3,B3
1.6
0.9
9.3
5.3
2.0
1.1
6.0
3.0
9.0
5.0
2.0
1.0
9.9
5.2
ns
ns
Propagalion Delay
Rise Time, Fall Time
1+-,1-+
1+,1-
S1
S1
GG
GG
A3,B3
A3,B3
1.5
0.8
9.6
6.2
2.0
0.8
6.0
3.0
9.0
6.0
1.9
0.8
9.7
6.5
ns
ns
Rise Time, Fall Time
Propagalion Delay
t
+25°C
Symbol
Characteristic
-
• L SuffiX Only
Logic high level (+1.11 Vdc) applied 10 pins listed. All other
inpul pins are left floating or lied 10 +0.31 Vdc.
VCC1 = VCC2 = +2.0 Vdc, VEE = -3.2 Vdc
MOTOROLA
3-15B
MECLDala
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Master-Slave Flip-Flop
With Reset
MC10186
The MC10186 contains six high-speed, master slave type "0" flip-flops.
Clocking is common to all six flip-flops. Data is entered into the master when
the clock is low. Master to slave data transfer takes place on the positive-going
Clock transition. Thus, outputs may change only on a positive-going Clock
transition. A change in the information present at the data (D) input will not affect
the output information any other time due to the master-slave construction of
this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET
ONLY FUNCTIONS WHEN CLOCK IS LOW.
-•
Po = 460 mW typ/pkg (No Load)
ftoggle= 150 MHz (typ)
tr, tf = 2.0 ns typ (20%-80%)
LOGIC DIAGRAM
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
FN SUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
00
RESET
00
01
4
02
VCC
05
01
04
02
03
DO
D5
D1
D4
D2
VEE
D3
CLOCK
13 03
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
14 Q4
CLOCKED TRUTH TABLE
15 05
CLOCK 9
RESET 1 - - - - - ;.....-~
VCC=PIN 16
VEE=PIN B
R
C
D
Qn + 1
L
L
X
L
W
L
On
L
L
H*
H
H
H
L
X
..
L
A clock H IS a clock transition
from a low to a high state.
3/93
© Motorola, Inc. 1996
3-159
REVS
®
MOTOROLA
MC10186
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
121
linH
5
9
1
350
495
920
-30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
88
110
121
mAde
220
310
575
220
310
575
IlAde
Min
linL
5
0.5
Output Voltage
Logic 1
VOH
2t
15t
-1.060
-1.060
--{l.890
--{l.890
--{l.960
--{l.960
--{l.81 0
--{l.81 0
--{l.890
--{l.690
-0.700
--{l.700
Vde
Output Voltage
Logic 0
VOL
2t
15t
-1.690
-1.690
-1.675
-1.675
-1.650
-1.650
-1.650
-1.650
-1.625
-1.625
-1.615
-1.615
Vde
Threshold Voltage
Logic 1
VOHA
2t
15t
-1.060
-1.060
Threshold Voltage
Logic 0
VOLA
2t
15t
tl+3tl+4t9+2+
t9+2-
3
4
2
2
1.6
1.6
1.6
1.6
4.6
4.6
4.6
4.6
1.6
1.6
1.6
1.6
2.5
2.5
3.5
3.5
4.5
4.5
4.5
4.5
1.6
1.6
1.6
1.6
5.0
5.0
5.0
5.0
Switching Times
0.5
0.3
IlAde
--{l.91 0
--{l.91 0
--{l.960
--{l.960
-1.630
-1.630
-1.655
-1.655
Vdc
-1.595
-1.595
(50nLoad)
Propagation Delay
Vde
ns
Rise Time
(20 to 60%)
t2+
2
1.0
4.1
1.1
1.6
4.0
1.1
4.4
Fall Time
(20 to 60%)
t2-
2
1.0
4.1
1.1
1.8
4.0
1.1
4.4
tsetup
2
2.5
2.5
2.5
2.5
'hold
2
1.5
1.5
-1.5
1.5
ns
ftog
2
125
125
150
125
MHz
Setupiime
Hold Time
Toggle Frequency (Max)
t Output level to be measured after clock pulse.
MOTOROLA
ns
V ~ VIH appears at clock input (Pin 9).
IL
3-160
MECLData
DL122-Rev6
MC10186
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
Symbol
Power Supply Drain Current
Input Current
VIHmax
VILmln
VIHAmin
VILAmax
VEE
-30'C
-D.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+85'C
-0.700
-1.825
-1.035
-1.440
-5.2
Pin
Under
Test
IE
8
linH
5
9
1
linL
5
Output Voltage
Logic 1
VOH
2t
15t
Output Voltage
Logic 0
VOL
2t
15t
Threshold Voltage
Logic 1
VOHA
2t
15t
Threshold Voltage
Logic 0
VOLA
2t
15t
tl+3tl+4t9+2+
t9+2-
3
4
2
2
Switching Times
(50n Load)
Propagation Delay
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmln
VIHAmin
VILAmax
8
16
16
16
16
8
16
8
8
16
16
8
8
16
16
8
8
16
16
5
12
8
8
16
16
Pulse In
Pulse Out
-3.2 V
+2.0 V
1,9
1,9
5,9
5,9
3
4
2
2
8
8
8
8
16
16
16
16
5
5
12
5
12
5
12
6
7
+0.31 V
(VCe>
Gnd
8
8
8
5
9
1
+l.llVdc
VEE
Rise Time
(20 to 80%)
t2+
2
5,9
2
8
16
Fall Time
(20 to 80%)
t2-
2
5,9
2
8
16
5,9
2
8
16
5,9
2
8
16
8
16
Setup Time
tsetup
2
Hold Time
thold
2
Toggle Frequency (Max)
ftog
2
t Output level to be measured after clock pulse. V ~ VIH appears at clock input (Pin 9).
IL
Each MECL 10,000 series circuit has been designed to meet the de specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a SD-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122 - Rev 6
3-161
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Buffer With Enable
MC10188
The MC10188 is a high-speed hex buffer with a common Enable input.
When Enable is in the high state, all outputs are in the low state. When Enable
is in the low state, the outputs take the same state as the inputs.
-•
Power Dissipation = 180 mW typ/pkg (No Load)
Propagation Delay= 2.0 ns typ (8 - Q)
2.5 ns typ (A - Q)
LOGIC DIAGRAM
PSUFAX
PLASTIC PACKAGE
CASE 64B-08
FNSUFFIX
PLCC
CASE 775-{)2
DIP
PIN ASSIGNMENT
4
13
10
14
11
15
12
VCCI =PIN 1
VCC2 = PIN 16
VEE = PIN 8
TRUTH TABLE
Inputs
X
y
Output
OUT
L
L
L
L
H
H
H
L
L
H
H
L
3-162
VCCI
VCC2
AOUT
FOUT
BOUT
EOUT
COUT
DOUT
AIN
FIN
BIN
EIN
CIN
DIN
VEE
COMMON
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3193
© Motorola. loc. 1996
LSUFFIX
CERAMIC PACKAGE
CASE 62G-l0
REV 5
®
MOTOROL.A
MC10188
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
Max
Unit
IE
8
46
42
46
mAdc
linH
5
425
265
265
J.lAdc
linH
9
460
290
290
!IAdc
-30'C
Min
+25'C
Max
Min
+85'C
Max
Min
Output Voltage
Logic 1
VOH
2
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
-1.B90
-1.675
-1.B50
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
-1.080
Threshold Voltage
Logic 0
VOLA
2
Enable
Data
tpHL
tpLH
2
2
1.1
1.0
3.9
3.3
1.1
1.0
3.5
2.9
1.1
1.0
3.9
3.3
(20 to 80%)
trLH
trHL
2
1.1
3.7
1.1
3.3
1.1
3.7
Switching TImes
-0.980
-1.655
-0.910
Vdc
-1.595
-1.630
(50ilLoad)
Propagation Delay
Rise/Fall TIme
Vdc
ns
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHmax
VILmln
VIHAmin
VILAmax
VEE
-30'C
-0.890
-1.890
-1.205
-1.500
-5.2
+25'C
-0.810
-1.850
-1.105
-1.475
-5.2
+B5'C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Power Supply Drain Current
Input Current
Pin
Under
Test
VIHAmin
VILAmax
VEE
(Vccl
Gnd
8
B
1,16
5
5
B
1,16
linH
9
9
8
1,16
5
8
1,16
8
1,16
8
1,16
VOH
2
Output Voltage
Logic 0
VOL
2
Threshold Voltage
Logic 1
VOHA
2
Threshold Voltage
Logic 0
VOLA
2
Rise/Fall TIme
VILmin
IE
Logic 1
Propagation Delay
VIHmax
linH
Output Voltage
Switching TImes
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
9
5
(50Q Load)
5
8
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
Enable
Data
tpHL
tpLH
2
2
9
5
2
2
B
8
1,16
1,16
(20 to 80%)
trLH
trHL
2
5
2
8
1,16
..
..
Each MECL 10,000 senes circUit has been designed to meet the dc specifications shown In the test table, after thermal eqUilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5()-Qhm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-163
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Inverter With Enable
MC10189
The MC10189 provides a high-speed Hex Inverter with a common Enable
input. The hex inverting function is provided when Enable is in the low state.
When Enable is in the high state all outputs are low.
PD
tpd
=200 mW typ/pkg (No Load)
=2.0 ns (Y-O)
=2.5 ns (X-a)
-•
LOGIC DIAGRAM
x
OUT
y
2
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
PSUFAX
PLASTIC PACKAGE
CASE64!HJ8
FNSUFFIX
PLCC
CASE 775-02
DIP
PIN ASSIGNMENT
13
10
14
11
15
12
VCCI = PIN 1
VCC2=PIN 16
VEE = PIN a
TRUTH TABLE
Inputs
Output
X
Y
OUT
L
L
H
L
H
L
H
L
L
H
H
L
3-164
VCC2
Four
BOUT
EOUT
COUT
DOUT
AIN
FIN
BIN
EIN
CIN
DIN
VEE
COMMON
Pin assignment is for DuaHn-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3193
© Motorola, Inc. 1996
VCCI
AOUT
REVS
®
MOTOROLA
MC10189
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
linH
linL
"'-30°C
Min
+25°C
Max
+85°C
Max
Unit
44
mAdc
265
265
fl Adc
555
555
fl Adc
Mi~
Max
Min
44
40
5
425
9
890
Output Voltage
Logic 1
VOH
2
-1.060
--D.890
-0.960
--D.81 0
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
-1.890
-1.675
-1.850
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
-1.080
Threshold Voltage
Logic 0
VOLA
2
Enable
Data
tpHL
tpLH
2
2
1.1
1.0
3.9
3.3
1.1
1.0
3.5
2.9
1.1
1.0
3.9
3.3
(20 to 80%)
trLH
trHL
2
1.1
3.7
1.1
3.3
1.1
3.7
Switching Times
-0.980
-1.655
-0.910
-1.630
Vdc
-1.595
Propagation Delay
Rise/FaliTime
Vdc
ns
(50n Load)
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
Characteristic
Power Supply Drain Current
Input Current
VIHmax
VILmln
VIHAmin
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
--D.81 0
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
VILAmax
VEE
(VCC)
Gnd
8
8
1,16
5
5
8
1,16
linL
9
9
8
1,16
8
1,16
8
1,16
8
1,16
VOH
2
Output Voltage
Logic 0
VOL
2
Threshold Voltage
Logic 1
VOHA
2
Threshold Voltage
Logic 0
VOLA
2
Rise/FaliTime
VIHAmin
IE
Logic 1
Propagation Delay
VILmin
linH
Output Voltage
Switching Times
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
5
9
5
5
(50n Load)
8
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
Enable
Data
tpHL
tpLH
2
2
9
5
2
2
8
8
1,16
1,16
(20 to 80%)
trLH
trHL
2
5
2
8
1,16
..
..
Each MECL 10,000 series cIrcUIt has been deSIgned to meet the dc specIfIcatIons shown In the test table, after thermal eqUilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-165
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Bus Driver
MC10192
The MC1 0192 contains four line drivers with complementary outputs. Each
driver has a Data (D) input and shares an Enable (E) input with another driver.
The two driver outputs are the uncommitted collectors of a pair of NPN
transistors operating as a current switch. Each driver accepts 10K MECL input
signals and provides a nominal signal swing of 800 mV across a 50 0 load at
each output collector. Outputs can drive higher values of load resistance,
provided that the combination of IR drop and load return voltage VLR does not
cause an output collector to go more negative than -2.4 V with respect to VCC.
To avoid output transistor breakdown, the load return voltage should not be
more positive than +5.5 V with respect to VCC. When the E input is high, both
output transistors of a driver are nonconducting. When not used, the E inputs,
as well as the D inputs, may be left open.
-•
Open Collector Outputs Drive Terminated Lines or
Transformers
50 kO Input Pulldown Resistors on All Inputs (Unused
Inputs May Be Left Open)
Power Dissipation = 575 mW typ/pkg (No Load)
Propagation Delay= 3.5 ns typ (E - Output)
3.0 ns typ (D - Output)
LSUFFIX
CERAMIC PACKAGE
eASE 62(HO
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
FNSUFFIX
PLCC
CASE 77!Hl2
DIP
PIN ASSIGNMENT
LOGIC DIAGRAM
Zl
4
01
Z1
Z2
Z2
Vec
Z2
Z3
Z1
Z3
Z1
Z4
02 6
Z2
01
Z4
0310
15 Z3
02
04
14
Z3
D4 11
13 Z4
E2 9
12 Z4
E1
03
VEE
E2
Pin assignment is for Dual-in-Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
Vee = PIN 16
VEE =PINB
TRUTH TABLE
Inputs
Output
E
D
Z
Z
H
X
H
H
L
H
H
L
L
L
L
H
Note: Unused outputs must be terminated
to VCC for proper operation.
3/93
© Motorola, Inc. 1996
3-166
REV 5
®
MOTOROI.A
MC10192
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
IE
8
linH
5
linL
5
10H
2
Power Supply Drain Current
Input Current
-30°C
Min
+25°C
Max
Min
Min
Max
Unit
154
mAdc
220
"Adc
140
154
350
0.5
+85°C
Max
220
0.3
0.5
I1Adc
Output Current High
Logic 1
Output Current Low
Logic 0
10L
2
Threshold Current High
Logic 1
10HC
2
Threshold Current Low
Logic 0
10LC
2
13.5
14.0
14.0
mAde
Output Sink Current Low
Logic 0
lOS
2
13.3
13.9
13.3
mAdc
Load Return Voltage Absolute Max
Rating (Note 1.)
2.0
13.5
14.0
2.0
18.0
14.0
19.0
mAdc
2.0
mAde
2.0
5.5
VLR
Output Voltage Low (Note 2.)
18.0
mAdc
5.5
5.5
-2.4
VOLS
V
V
ns
Switching Times
(500 Load)
Propagation Delay
EtoOutput
DtoOutput
tpHL
tpLH
Rise/Fall Time
(20 to 80%)
trLH
trHL
2.0
1.5
6.0
4.5
3.3
1. The 5.5V value is a maximum rating, do not exceed. A 2700 resistor will prevent output transistor breakdown.
2. Limitations of load resistor and load retum voltage combinations. Refer to page 3-166 description.
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
Characteristic
Symbol
Power Supply Drain Current
Input Current
VIHmax
VILmln
VIHAmln
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Pin
Under
Test
IE
8
linH
5
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmln
VIHAmln
VILAmax
5
VEE
(VCC)
Gnd
8
16
8
16
linL
5
5
8
16
10H
2
5,6,10,11
8
16
Logic 0
10L
2
Logic 1
10HC
2
Threshold Current Low
Logic 0
10LC
Output Sink Current Low
Logic 0
lOS
Output Current High
Logic 1
Output Current Low
Threshold Current High
Load Return Voltage Absolute Max
Rating (Note 1.)
Output Voltage Low (Note 2.)
5,6,10,11
8
16
8
16
8
16
8
16
VLR
8
16
VOLS
8
16
5,7,9,10,11
5,10,11
2
5,6,10,11
7,9
6
6
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-0hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122- RevS
3-167
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Inverter/Buffer
MC10195
The MC10195 is a Hex Buffer Inverter which is built using six EXCLUSIVE
NOR gates. There is a common input to these gates which when placed low or
left open allows them to act as inverters. With the common input connected to
a high logic level the MC10195 is a hex buffer, useful for high fanout clock
driving and reducing stub lengths on long bus lines.
-, .
•
PD = 200 mW typ/pkg (No Load)
tpd 2.8 ns typ (B-O)
tpd = 3.8 ns typ (A-Q)
t r, tf 2.5 ns typ (20%-80%)
=
=
LOGIC DIAGRAM
9~A~__~__~~~
6
~~____0~2
LSUFFIX
CERAMIC PACKAGE
CASE 62G-l0
P SUFFIX
PLASTIC PACKAGE
CASE 64!HJ8
FNSUFFIX
PLCC
CASE 77!HJ2
DIP
PIN ASSIGNMENT
VCCI
10 ______+-__.-1L.-"'~1o.....----13
11 -------+--~~L-~
XI"------ 14
VCC2
01
06
Q2
05
03
Q4
61
66
62
65
63
64
VEE
A
Pin assignment is for Dual-in-Line Package.
For PLee pin assignment, see the Pin Conversion
12 ____________IL-"'~Io.....---- 15
Tables on page tHl.
VCCI = PIN 1
VCC2 = PIN 16
VEE = PIN8
TRUTH TABLE
Inputs
Output
A
B
Q
L
L
H
L
H
L
H
L
L
H
H
H
3/93
© Motorola, Inc. 1996
3-168
REV 5
®
MOTOROLA
MC10195
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
54
linH
5
9
425
460
-30°C
Min
+25°C
Max
Min
+B5°C
Typ
Max
Max
Unit
39
49
54
mAdc
265
290
265
290
lIAdc
Min
0.3
linL
5
0.5
Output Voltage
Logic 1
VOH
2
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
-1.890
-1.675
-1.850
-1.650
-1.B25
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
-1.080
Threshold Voltage
Logic 0
VOLA
2
-1.595
Vdc
t5+2t7-4+
tl0+13+
tll-l4t9-14-
2
4
13
14
14
1.1
1.1
1.1
1.1
1.1
4.2
4.2
4.2
4.2
5.2
1.1
1.1
1.1
1.1
1.1
2.8
2.8
2.8
2.8
3.8
4.0
4.0
4.0
4.0
5.0
1.1
1.1
1.1
1.1
1.1
SWitching Times
0.5
lIAdc
-0.910
-0.980
-1.655
-1.630
Vdc
(50n Load)
Propagation Delay
ns
4.4
4.4
4.4
4.4
5.4
Rise TIme
(20 to 80%)
t2+
2
1.1
4.7
1.1
2.5
4.5
1.1
5.0
Fall Time
(20 to 80%)
t2-
2
1.1
4.7
1.1
2.5
4.5
1.1
5.0
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
Symbol
Power Supply Drain Current
Input Current
VIHmax
VILmin
VIHAmln
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500'
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Pin
Under
Test
IE
8
linH
5
9
linL
5
Output Voltage
Logic 1
VOH
2
Output Voltage
Logic 0
VOL
2
Threshold Voltage
Logic 1
VOHA
2
Threshold Voltage
Logic 0
VOLA
2
Switching TImes
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
t5+2t7-4+
tl0+13+
tll-l4t9-14-
VIHAmln
VILAmax
5
9
5
9
5
5
(50n Load)
Propagation Delay
VILmln
2
4
13
14
14
VEE
(VCC)
Gnd
8
1,16
8
8
1,16
1,16
8
1,16
8
1,16
8
1,16
8
1,16
8
1,16
Pulse In
Pulse Out
-3.2 V
+2.0 V
5
2
4
13
14
14
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
7
10
11
9
Rise TIme
(20 to 80%)
t2+
2
5
2
8
1,16
Fall TIme
(20 to 80%)
t2-
2
5
2
8
1,16
..
"
Each MECL 10,000 serres CircUit has been deSigned to meet the dc specifications shown In the test table, after thermal eqUlhbrrum
has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5Q--ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-169
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex AND Gate
MC10197
The MC10197 provides a high speed hex AND function with strobe
capability.
=
=
Po 200 mW typ/pkg (No Load)
tpd 2.8 ns typ (B--Q)
tpd = 3.8 ns typ (A-Q)
tr. If = 2.5 ns typ (20%-80%)
-•
LOGIC DIAGRAM
A
Q
B
13
10 - - - + - - L . - /
14
12 - - - - - L . - /
PSUFFIX
PLASTIC PACKAGE
CASE 648-08
FNSUFFIX
PLCC
CASE 77!Hl2
DIP
PIN ASSIGNMENT
4
7---+--L.-/
11
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
15
VCC1 =PIN 1
VCCFPIN 16
VEE=PIN8
VCC1
VCC2
AoUT
FOUT
BOUT
EOUT
CaUT
DOUT
AIN
FIN
BIN
EIN
CIN
DIN
VEE
COMMON
Pin assignment is for Dual-in-Line Package.
TRUTH TABLE
Inputs
Output
A
B
Q
L
L
L
L
H
L
H
L
L
H
H
H
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
3/93
© Motorola, Inc. 1996
3-170
REVS
®
MOTOROLA
MC10197
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Power Supply Drain Current
Input Current
Symbol
Pin
Under
Test
IE
8
54
linH
5
9
425
460
-30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
39
49
54
mAdc
265
290
265
290
IJAdc
Min
linL
5
0.5
0.5
0.3
Output Voltage
Logic t
VOH
2
-1.060
-0.890
-0.960
-0.810
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
-1.890
-1.675
-1.650
-1.650
-1.825
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
-1.060
Threshold Voltage
Logic 0
VOLA
2
t5+2+
t9+2+
2
2
Switching Times
IJAdc
-0.980
-0.910
-1.655
-1.630
Vdc
-1.595
(50QLoad)
Propagation Delay
Vdc
ns
1.1
1.1
4.2
5.3
1.1
1.1
2.6
3.5
4.0
5.0
1.1
1.1
4.4
5.5
Rise Time
(20 to 80%)
t2+
2
1.1
4.7
1.1
2.5
4.5
1.1
5.0
Fall Time
(20 to 80%)
t2-
2
1.1
4.7
1.1
2.5
4.5
1.1
5.0
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
Characteristic
Power Supply Drain Current
Input Current
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30°C
-0.890
-1.890
-1.205
-1.500
-5.2
+25°C
-0.810
-1.850
-1.105
-1.475
-5.2
+85°C
-0.700
-1.825
-1.035
-1.440
-5.2
Symbol
Pin
Under
Test
IE
8
linH
5
9
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
linL
5
Logic 1
VOH
2
Output Voltage
Logic 0
VOL
2
Threshold Voltage
Logic 1
VOHA
2
9
Threshold Voltage
Logic 0
VOLA
2
9
VILAmax
5
5,9
5
(50Q Load)
Propagation Delay
VIHAmin
5
9
Output Voltage
Switching Times
VILmln
VEE
(VCe>
Gnd
8
1,16
8
8
1,16
1,16
8
1,16
6
1,16
6
1,16
8
1,16
5
8
1,16
+1.11V
Pulse In
Pulse Out
-3.2 V
+2.0 V
1,16
1,16
t5+2+
t9+2+
2
2
9
5
5
9
2
2
8
8
Rise Time
(20 to 80%)
t2+
2
9
5
2
8
1,16
Fall Time
(20 to 80%)
t2-
2
9
5
2
8
1,16
..
..
Each MECL 10,000 series CirCUit has been deSigned to meet the dc specifications shown In the test table, after thermal equIlibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-171
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Monostable Multivibrator
MC10198
The MC1 0198 is a retriggerable monostable multivibrator. Two enable inputs
permit triggering on any combination of positive or negative edges as shown in
the accompanying table. The trigger input is buffered by Schmitt triggers
making it insensitive to input rise and fall times.
The pulse width is controlled by an external capacitor and resistor. The
resistor sets a current which is the linear discharge rate of the capacitor. Also,
the pulse width can be controlled by an external current source or voltage (see
applications information).
For high-speed response with minimum delay, a hi-speed input is also
provided. This input bypasses the internal Schmitt triggers and the output
responds within 2 nanoseconds typically.
Output logic and threshold levels are standard MECL 10,000. Test
conditions are per Table 2. Each "Precondition" referred to in Table 2 is per the
sequence of Table 1.
""•
Po = 415 mW typ/pkg (No Load)
tpd
4.0 ns typ Trigger Inpt to 0
2.0 ns typ Hi-Speed Input to 0
=
Min Timing Pulse Width
Max Timing Pulse Width
Min Trigger Pulse Width
Min Hi-Speed
Trigger Pulse Width
Enable Setup Time
Enable Hold Time
PWOmin
PWO max
PWT
PWHS
~SUFFIX
CERAMIC PACKAGECASE 62D-10
PSUFFIX
PLASTIC PACKAGE
CASE648-0B
FN SUFFIX
PLCC
CASE 77S-02
DIP
PIN ASSIGNMENT
10 ns typ1
>10 ms typ2
2.0 ns typ
3.0 ns typ
I
VCC!
VCC2
HIGH-SPEED
INPUT
Q
tset
thold
1.0 ns typ
1.0 nstyp
Q
1 CExt = 0 (Pin 4 open), RExt = 0
(Pin 6 to VEE)
2 CExt = 10 ~F, RExt = 2.7 k.Q
Nle
CEXT
TRIGGER INPUT
EpOS
N/C
REXT
N/C
EXIPULSE
WIDTH CONTROL
LOGIC DIAGRAM
ENEG
NlC
VEE
VEE
Pin assignment is for Dual-in--Une Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6-11.
4
REXT
Epas
CEXT
Q
EXTERNAL PULSE
WIDTH CONTROL
10
VCC1 =PIN 1
VCC2 = PIN 16
VEE= PINS
ENEG
13
TRIGGER
INPUT
15
HI-SPEED
INPUT
Q
2
TRUTH TABLE
INPUT
OUTPUT
Epos ENea
L
Triggers on both positive & negative input slopes
L
Triggers on positive input slope
L
H
Triggers on negative input slope
H
L
H
H
Trigger is disabled
3/93
© Motorola, Inc. 1996
3-172
REVS
®
MOTOROLA
MC10198
TABLE 1 -
PRECONDITION SEQUENCE
1. AII=O
a.)
b.)
c.)
2. All" 10 ns
f4-"IOns ..... :--" IOns .....
ApplyVIHmaxlo Pin 5 and 10.
Apply VILmin 10 Pin 15.
Ground Pin 4.
a.) Open Pin 1.
b.) Apply -3.0 Vdc 10 Pin 4.
Hold Ihese conditions for
O(Gnd)
~
J
,g
...
~10ns.
-1.0
,
-2.0
-3.0
,
'Ie-
if
-4.0
Pin I __
open
I
-5.0
o
3. Return Pin 4 to Ground and perform test as
indicated in Table 2.
10
I
30
20
I(ns)
TABLE 2 -
CONDITIONS FOR TESTING OUTPUT LEVELS
(See Table 1 for Precondition Sequence)
11-~
L
PI
VIHmax
~
VILmln
P2
11-~
L
VILA max
P3
VILmin
VIHAmax
VILmin
Pins 1, 16 = Vee = Ground
Pins 6, 8 = VEE = -5.2 Vdc
Oulpuls loaded 50 n 10 -2.0 Vdc
Pin Conditions
Test
P.U.T.
5
10
Precondition
2
VOH
3
VOH
Precondition
3
VOL
2
VOL
Precondition
VOHA 2
VOHA 3
Precondition
VOHA 2
VOHA 3
Precondition
VOHA 2
VOHA 3
Precondition
VOHA 2
VOHA 3
Precondition
VOHA 2
VOHA 3
MECLData
DL122-Rev6
13
Pin Conditions
VILmin
P1
VILmin
P1
VILA max
VIHAmin
VILmin
P3
P2
P3
VIH max
VIHmax
P2
P3
VIHmax
VIHmax
P1
P1
Test
15
P.U.T.
Precondition
VOHA 2
VOHA 3
Precondition
VOLA 3
VOLA 2
Precondition
VOLA 2
VOLA 3
Precondition
VOLA 3
VOLA 2
Precondition
VOLA 3
VOLA 2
Precondition
VOLA 3
VOLA 2
Precondition
VOLA 3
VOLA 2
3-173
5
10
13
VIHAmin
VILA max
P1
P1
15
ViLA max
VIHAmin
VILmin
VILmin
P2
P3
VIH max
VIH max
P2
P3
VIHAmin
VILA max
VIH max
VIH max
P1
P1
VIHmax
VIHmax
VIHAmin
VILA max
P1
P1
MOTOROLA
MC10198
ELECTRICAL CHARACTERISTICS
Test Limits
Characteristic
Symbol
Pin
Under
Test
IE
8
110
linH
5,10
13
15
415
350
560
Power Supply Drain Current
Input Current
-30°C
Min
+25°C
Max
Min
+85°C
Typ
Max
Max
Unit
80
100
110
mAdc
260
220
350
260
220
350
(.IAdc
0.5
Min
linL
5
0.5
Output Voltage
Logic 1
VOH
2
3
-1.060
-1.060
-0.890
-0.890
-0.960
-0.960
-0.810
-0.810
-0.690
-0.890
-0.700
-0.700
Vdc
Output Voltage
Logic 0
VOL
2
3
-1.890
-1.890
-1.675
-1.675
-1.650
-1.850
-1.650
-1.650
-1.625
-1.825
-1.615
-1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
3
-1.080
-1.080
Threshold Voltage
Logic 0
VOLA
2
3
tr+Q+
tr-Q+
3
3
2.5
2.5
6.5
6.5
2.5
2.5
High Speed Trigger Input
tHS+Q+
3
1.5
3.2
1.5
Minimum TIming Pulse Width
PWQmin
3
10.0
ns
Maximum TIming Pulse Width
PWQmax
3
>10
ms
ns
Switching TImes
0.3
-0.980
-0.980
(.IAdc
-0.910
-0.910
-1.630
-1.630
-1.655
-1.655
Vdc
-1.595
-1.595
Vdc
(50Q Load)
Trigger Input
Min Trigger Pulse Width
Min Hi--Spd Trig Pulse Width
Rise TIme
(20 to 80%)
Fall TIme
(20 to 60%)
4.0
4.0
5.5
5.5
2.5
2.5
6.5
6.5
ns
2.0
2.8
1.5
3.2
ns
PWT
3
2.0
PWHS
3
3.0
3
1.5
4.0
1.5
3
1.5
4.0
1.5
ns
3.5
1.5
4.0
ns
3.5
1.5
4.0
ns
Enable Setup TIme
tsetup (E)
3
1.0
ns
Enable Hold TIme
thold (E)
3
1.0
ns
1. The monostable IS In the timing mode at the time of this test.
2. CEXT 0 (Pin 4 Open); REXT 0 (Pin 6 tied to VEE).
3. CEXT lOI1F (Pin); REXT 2.7k (Pin 6).
=
=
4.
=
=
~-VIHmax
Pl
MOTOROLA
-
VILmin
3--174
MECL Data
DLl22-Rev6
MC10198
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@
Characteristic
Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
-30°C
-D.890
-1.890
-1.205
-1.500
-5.2
+25°C
-D.81 0
-1.850
-1.105
-1.475
-5.2
+85°C
-D.700
-1.825
-1.035
-1.440
-5.2
Symbol
Power Supply Drain Current
Input Current
Output Voltage
Logic 1
Output Voltage
Logic 0
Threshold Voltage
Logic 1
Threshold Voltage
Logic 0
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
(VCC)
Gnd
6,8
1,4,16
6,8
6,8
6,8
1,4,16
1,4,16
1,4,16
IE
8
5,10
13
15
linL
5
5
6,8
1,4,16
VOH
2
3
13
6,8
6,8
1,4,16
1,4,16
6,8
6,8
1,4,16
1,4,16
6,8
6,8
1,16,4
1,16,4
15
6,8
6,8
1,16,4
1,16,4
VOL
VOHA
VOLA
2
3
5,10
13
15
13(4.)
13(4.)
13
2
3
15
2
15
(SOn Load)
Switching Times
VEE
linH
15
3
Trigger Input
VILAmax
tr+o+
tr-Q+
3
3
+1.11V
Pulse In
Pulse Out
-3.2 V
+2.0 V
10
5
13
13
3
3
6,8
6,8
1,16,4
1,16,4
High Speed Trigger Input
tHS+O+
3
3
6,8
1,16,4
Minimum Timing Pulse Width
PWOmin
3
Note 2.
6,8
1,16,4
Maximum Timing Pulse Width
PWO max
3
Note 3.
6,8
1,16,4
Minimum Trigger Pulse Width
PWT
3
13
3
6,8
1,16,4
PWHS
3
15
3
6,8
1,16,4
Minimum Hi-Spd Trigger Pulse Width
15
Rise Time
(20 to 80%)
3
6,8
1,16,4
Fall Time
(20 to 80%)
3
6,8
1,16,4
Enable Setup Time
tsetup (E)
3
5
3
6,8
1,16,4
Enable Hold Time
thold (E)
3
5
3
6,8
1,16,4
1. The monostable IS In the timing mode at the time of this test.
2. CEXT 0 (Pin 4 Open); REXT 0 (Pin 6 tied to VEE).
3. CEXT 10llF (Pin); REXT 2.7k (Pin 6).
=
=
4.
JLP1
-
=
=
VIHmax
VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 5Q-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
3-175
MOTOROLA
MC10198
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
VCC1 = VCC2 = +2.0 Vdc
Vaut
·:!__tJ:~
5
I
-=---l Epos
I
7
I External Pulse
TPin
i
I
I
I
QI
r
Width Control
10 I -----, ENeg
0+--+--0
Pulse Generator
+1.11V~
13
I
15
I
I
I
I
I
~ Trigger Input
0.1I!F'1'
---I
Input Pulse
Hi-8peed Input
I
I
t+ = t-= 2.0 ± 0.2 ns
(20 to 80%)
6
I
I
4
I
in each scope channel input.
All inpul and oulpul cables lolhe scope
are equal lengths of SG-ohm coaxial
cable. Wire length should be < 114 inch
from TPin 10 inpul pin and TPoul
oulpulpin.
I
I
RExt
~
r1
1 L-----h-J
.
10
I
I
I
I 2
Q~
I
I
CExt
5Q-ohm termination 10 ground localed
3
1 l
Unused outputs are tied to a
5Q-ohm resistor 10 ground.
O.1 I!F
VEE = -3.2 Vdc
Trigger Input
Q
..'"" :£
High-speed
~
Q
MOTOROLA
....
-
eN: =-1----3-176
MECLData
DL122-Rev6
"
MC10198
APPLICATIONS INFORMATION
Circuit Operation:
Figure 2 shows typical curves for pulse width
versus CExt and RExt (total resistance includes Rlnt).
Any low leakage capacitor can be used and RExt can
vary from 0 to 16 k-;)hms.
1.PULSE WIDTH TIMING - The pulse width is determined by the external resistor and capacitor. The
MCl 0198 also has an internal resistor (nominally 284
ohms) that can be used in series with RExt. Pin 7, the
external pulse width control, is a constant voltage node
(-3.60 V nominally). A resistance connected in series
from this node to VEE sets a constant timing current IT.
This current determines the discharge rate of the capacitor:
where
.1.0 Megohm must be used).
" The 1200 ohm resistor and the scope tennination impedance constitute
a 25:1 attenuator probe. Coax shall be CT-070-;;0 or equivalent.
... Bypass only that supply opposite ground .
14
-.
1200
I
OPERATING CHARACTERISTICS
Figure 3 illustrates the circuit schematic for the MC1648.
The oscillator incorporates positive feedback by coupling the
base of transistor 06 to the collector of 07. An automatic gain
control (AGC) is incorporated to limit the current through the
emitter-coupled pair of transistors (07 and 06) and allow
optimum frequency response of the oscillator.
In order to maintain the high 0 of the oscillator, and
provide high spectral purity at the output, transistor 04 is
used to translate the oscillator signal to the output differential
pair 02 and 03. 02 and 03, in conjunction with output
transistor 01, provides a highly buffered output which
produces a square wave. Transistors 09 and 011 provide
the bias drive for the oscillator and output buffer. Figure 4
indicates the high spectral purity of the oscillator output
(pin 3).
When operating the oscillator in the voltage controlled
mode (Figure 6), it should be noted that the cathode of the
varactor diode (D) should be biased at least "2" VSE above
VEE
H
.4V for positive supply operation).
When the MC1648 is used with a constant dc voltage to
the varactor diode, the output frequency will vary slightly
because of internal noise. This variation is plotted versus
operating frequency in Figure 7.
Figure 6. The MC1648 Operating in the
Voltage Controlled Mode
f= ~CC=5Vd
Oscillator Tank Components
(Circuit of Figure 6)
i"""'
i""""
10
f, OPERATING FREQUENCY (MHz)
L
f
......
MHz
0
J,LH
1.0--10
MV2115
100
1Q--60
MV2115
2.3
60-100
MV21 06
0.15
100
BW=I.0kHz Frequency
Meter HP5210A or Equiv
Frequency Deviation = (HP5210A output voltage) (Full Scale Frequency)
1.0Volt
Figure 7. Noise Deviation Test Circuit and Waveform
MOTOROLA
MECLData
DL122-Rev6
MC1648
64
N"
:c
L: Micro Metal Toroidal Core #T44-10,
4 turns of No. 22 copper wire.
56
;;§.
>()
48
:::J
40
zW
fil
c::
"-
I:::J
0I:::J
0
j
L=O.13~H
QL,,100
."
V'
./
32
1200'
1.0k
/
24
/'
16
8
o
MV1401
5.0~F I
""-
I-
-=
10
4
Vin, INPUT VOLTAGE (VOLTS)
Figure 8
..
VCCl = VCC2 = t5.0Vdc
VEEl = VEE2 = GND
• The 1200 ohm resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be CT-070-50 or equivalent.
NOT used in normal operation.
.. Input resistor and cap are for test only. They are NOT necessary for
normal operation.
L: Micro Metal Toroidal Core #T44-10,
20 turns of No. 22 copper wire.
18
N"
:c 16
;;§.
>()
z
w
:::J 14
./~
aw
/
a:
12
I
0
10
j
J
MV1401
,/
8
o
S.OJ!F
4
2
Figure 9
170
./
1:; 150
zw
:::J
aw 130
a:
"-
• The 1200 ohm resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be CT-070-50 or equivalent.
NOT used in normal operation.
.. Input resistor and cap are for test only. They are NOT necessary for
normal operation.
QL,,100
L=O.065J!H
./
;;§.
I:::J
VCCl = VCC2 = tS.OVdc
VEE1 = VEE2 = GND
L: Micro Metal Toroidal Core #T3(}-12,
6 turns of No. 22 copper wire.
190
N"
I "
-=
10
Vin, INPUT VOLTAGE (VOLTS)
:c
1200'
1.0k
/
"-
I:::J
0I:::J
QL,,100
C =500pF
L= l.5B~H
/
110
/
1200'
V
0-
I:::J
0
j
1/
90
/
/'
70
50
o
.......
VCCl = VCC2 = tS.OVdc
VEEl = VEE2 = GND
./
4
10
Vin, INPUT VOLTAGE (VOLTS)
Figure 10
MECLData
DL122-Rev6
4-7
The 1200 ohm resistor and the scope termination impedance constitute a 2S:1 attenuator probe. Coax shall be CT-07(}-SO or equivalent.
NOT used in normal operation.
.. Input resistor and cap are for test only. They are NOT necessary for
normal operation.
MOTOROLA
MC1648
Typical transfer characteristics for the oscillator in the
voltage controlled mode are shown in Figure 8, Figure 9 and
Figure 10. Figure 8 and Figure 10 show transfer
characteristics employing only the capacitance of the
varactor diode (plus the input capacitance of the oscillator,
6.0pF typical). Figure 9 illustrates the oscillator operating in a
voltage controlled mode with the output frequency range
limited. This is achieved by adding a capacitor in parallel with
the tank circuit as shown. The 1.0kn resistor in Figure 8 and
Figure 9 is used to protect the varactor diode during testing. It
is not necessary as long as the dc input voltage does not
cause the diode to become forward biased. The
larger-valued resistor (51kn) in Figure 10 is required to
provide isolation for the high-impedance junctions of the two
varactor diodes.
The tuning range of the oscillator in the voltage controlled
mode may be calculated as:
where
CS
co
f max
j
Co (max)
f min
=j
CO(min)
fmin =
+ Cs
+ Cs
1
2rr. j L(CO(max)
+ CS)
=shunt capacitance (input plus external capacitance)
=varactor capacitance as a function of bias voltage
Good RF and low-frequency bypassing is necessary on
the power supply pins. (See Figure 4)
Capacitors (Cl and C2 of Figure 6) should be used to
bypass the AGC point and the VCO input (varactor diode),
guaranteeing only dc levels at these pOints.
For output frequency operation between 1.0MHz and
50MHz a O.I!!F capacitor is sufficient for Cl and C2. At
higher frequencies, smaller values of capacitance should be
used; at lower frequencies, larger values of capacitance. At
high frequencies the value of bypass capacitors depends
directly upon the physical layout of the system. All bypassing
should be as close to the package pins as possible to
minimize unwanted lead inductance.
The peak-te-peak swing of the tank circuit is set internally
by the AGC circuitry. Since voltage swing of the tank circuit
provides the drive for the output buffer, the AGC potential
directly affects the output waveform. If it is desired to have a
sine wave at the output of the MC1648, a series resistor is
tied from the AGC point to the most negative power potential
(ground if +5.0 volt supply is used, -5.2 volts if a negative
supply is used) as shown in Figure 10.
At frequencies above 100 MHz typ, it may be desirable to
increase the tank circuit peak-te-peak voltage in order to
shape the signal at the output of the MC1648. This is
accomplished by tying a series resistor (1.0kn minimum)
from the AGC to the most positive power potential (+5.0 volts
if a +5.0 volt supply is used, ground if a -5.2 volt supply is
used). Figure 13 illustrates this principle.
APPLICATIONS INFORMATION
The phase locked loop shown in Figure 11 illustrates the
use of the MC1648 as a voltage controlled oscillator. The
figure illustrates a frequency synthesizer useful in tuners for
FM broadcast, general aviation, maritime and landmobile
communications, amateur and CB receivers. The system
operates from a single +5.0Vdc supply, and requires no
internal translations, since all components are compatible.
Frequency generation of this type offers the advantages of
single crystal operation, simple channel selection, and
elimination of special circuitry to prevent harmonic lockup.
Additional features include dc digital switching (preferable
over RF switching with a multiple crystal system), and a
broad range of tuning (up to 150MHz, the range being set by
the varactor diode).
The output frequency of the synthesizer loop is
determined by the reference frequency and the number
programmed at the programmable counter; fout Nfref. The
channel spaCing is equal to frequency (fref).
For additional information on applications and designs for
phase locked-loops and digital frequency synthesizers, see
=
MOTOROLA
Motorola Brochure BR504/0, Electronic Tuning Address
Systems, (ETAS).
Figure 12 shows the MC1648 in the variable frequency
mode operating from a +5.0Vdc supply. To obtain a sine wave
at the output, a resistor is added from the AGC circuit (pin 5)
to VEE.
Figure 13 shows the MC1648 in the variable frequency
mode operating from a +5.0Vdc supply. To extend the useful
range of the device (maintain a square wave output above
175Mhz), a resistor is added to the AGC circuit at pin 5 (1.0
kohm minimum).
Figure 14 shows the MC1648 operating from +5.0Vdc and
+9.0Vdc power supplies. This permits a higher voltage swing
and higher output power than is possible from the MECL
output (pin 3). Plots of output power versus total collector
load resistance at pin 1 are given in Figure 15 and Figure 16
for 100MHz and 10MHz operation. The total collector load
includes R in parallel with Rp of L1 and Cl at resonance. The
optimum value for R at 100MHz is approximately 850 ohms.
MECLData
DL122-Rev6
MC1648
I--"'T""-~fout
fref-
fout = Nfref where
N=Np.P+A
Figure 11. Typical Frequency Synthesizer Application
+5.0Vdc
+5.0Vdc
~-=
1---+--0 Output
Output
I
-=
1.0kmin
12
crlI
-=
12
5
-=
o--lI
-= -=
Figure 12. Method of Obtaining a Sine-Wave Output
MECLData
DL122- Rev 6
I
Figure 13. Method of Extending the Useful Range
of the MCl648 (Square Wave Output)
4-9
MOTOROLA
MC1648
Output
R
+5.0V
,~L~
Bias Point
10
____,-
L1
VCC1
I
Figure 14. Circuit Used for Collector Output Operation
14
i\
12
$
::;;
a:
:;:
.s
f:::>
4
/
0-
f-
a:
V
[1J
10
100
,,/'
0-
f-
:::>
0
1\
a:
w
:;:
0
a..
1000
\
1\
4
o
10,000
'\
~
:::>
0-
o
10
f-
1\
'/
15
~
\.
:::>
0
a:
w
\
$
::;;
~
5
10
100
10,000
1000
TOTAL COLLECTOR LOAD (OHMS)
TOTAL COLLECTOR LOAD (OHMS)
See test circuit, Figure 14, f = 100MHz
C3 = 3.D-35pF
Collector Tank
L 1 = 0.221lH
C1 = 1.D-7.0pF
R = 500-101<11
Rp of L1 and C1 = 111<11 @ 1OOMHz Resonance
Oscillator Tank
L2 = 4 turns #20 AWG 3116" 10
C2 = 1.D-7.0pF
See test circuit, Figure 14, f = 10MHz
C3=470pF
Collector Tank
L1 = 2.7J!H
C1 = 24-200pF
R = 50(1-101<11
Rp of L 1 and C1 = 6.81<11 @ 10MHz Resonance
Oscillator Tank
L2=2.7J!H
C2=16-150pF
Figure 15. Power Output versus Collector Load
MOTOROLA
Figure 16. Power Output versus Collector Load
4-10
MECLOata
0L122 - Rev 6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Duaa AID Converter
MC1650
MC1651
The MC1650 and the MC1651 are very high speed comparators utilizing
differential amplifier inputs to sense analog signals above or below a reference
level. An output latch provides a unique sample-hold feature. The MC1650
provides high impedance Darlington inputs, while the MC1651 is a lower
impedance option, with higher input slew rate and higher speed capability.
The clock inputs (Ca and Cb) operate from MECL III or MECL 10,000 digital
will be at a logic high level provided
levels. When C a is at a logic high level,
is the logic complement of
that V1 > V2 (V1 is more positive than V2).
When the clock input goes to a low logic level, the outputs are latched in their
present state.
Assessment of the performance differences between the MC1650 and the
MC1651 may be based upon the relative behaviors shown in Figures 4 and 7.
ao
ao
ao.
LSUFFIX
CERAMIC PACKAGE
CASE 620-10
LOGIC DIAGRAM
PIN ASSIGNMENT
GND
Vee = +5.0 V= PIN 7, 10
VEE = -5.2V=PIN8
GND = PIN 1, 16
•
•
•
•
•
•
•
PD = 330 mW typlpkg (No Load)
tpd = 3.5 ns typ (MCI650)
= 3.0 ns typ (MCI651)
350 VI~ (MCI650)
Input Slew Rate
= 500Vl~(MCI651)
Differential Input Voltage: 5.0 V (-30'C to +85'C)
Common Mode Range:
-3.0 V to +2.5 V (-30°C to +85°C) (MCI651)
-2.5 V to +3.0 V (-30'C to +85'C) (MCI650)
Resolution: '" 20 mV (-30'C to +85'C)
Drives 50 Q lines
GND
00
01
00
01
CA
Cs
V2A
V1B
VIA
V2B
Vee
Vcc
VEE
NC
=
Number at end of terminal denotes pin number for L package (Case 620).
TRUTH TABLE
C
Vl,V2
OOn+l
H
VI> V2
H
L
VI < V2
L
H
OOn
aO n
H
L
X
X
OOn+l
3/93
© Motorola, Inc. 1996
4-11
REVS
®
MOTOROLA
[1J
MC1650 MC1651
ELECTRICAL CHARACTERISTICS
Test Limits
-30°C
Characteristic
Symbol
Min
+25°C
Max
Min
+85°C
Max
Min
Max
Unit
ICC
IE
25'
55'
mAdc
MC1650
MC1651
lin
10
40
!lAde
MC1650
MC1651
IR
7.0
10.0
!lAde
Output Voltage
Logic 1
VOH
-1.045
-0.875
-0.960·
-0.810
-0.890
-0.700
Vdc
Output Voltage
Logic 0
VOL
-1.890
-1.650
-1.850
-1.620
-1.830
-1.575
Vdc
Threshold Voltage (Nole 2.)
Logic 1
VOHA
-1.065
Threshold Voltage (Note 2.)
Logic 0
VOLA
-1.555
Vdc
Power Supply Drain Current
Positive
Negative
Input Current
Input Leakage Current
Clock Input Current
350
linH
-0.980
-1.630
Vdc
-0.910
-1.600
1. All data IS for 1/2 MC1650 or MC1651, except dala marked (') which refers to the entire package.
2. These tests are done in order indicated. See Figure 5.
3. Maximum Power Supply Voltages (beyond which device life may be impaired): IVEEI + IVCCI ~ 12 Vdc.
4.
All Temperature
VA3
VA4
VAS
VA6
MC1650
+3.0
+2.98
-2.5
-2.48
MC1651
+2.5
+2.48
-3.0
-2.98
MOTOROLA
4-12
MECLData
DL122-Rev6
MC1650 MC1651
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
V,Hmax
V,Lmln
V'HAmln
V,LAmax
VA1
VA2
-30'C
--0.875
-1.890
-1.180
-1.515
+0.02
+0.02
+25'C
--0.810
-1.850
-1.095
-1.485
+0.02 +0.02
+85'C
--0.700
-1.830
-1.025
-1.440
+0.02
VA3
VA4
VA5
VA6
See Note 4.
+0.02
Vee3.
VEE3.
+5.0
-5.2
+5.0
-5.2
+5.0
-5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Symbol
V,Hmax
ICC
'E
4,13
MC1650
MC1651
'in
Input Leakage MC1650
Current
MC1651
'R
Characteristic
Power Supply
Drain Current
Input Current
Pas
Neg
V'HAmin
V,LAmax
VA1
4,13
6,12
6,12
4
13
12
4
13
12
13
Clock Input Current
'inH
4
Output Voltage
VOH
4,13
Logic 1
V,Lmln
VA2
VA3
VA4
VA5
VA6
1,5,11,16
1,5,11,16
1,5,11,16
6
6
1,5,11,16
6,12
1,5,11,16
6,12
1,5,11,16
1,6,12,16
1,16
1,16
1,5,11,16
1,6,12,16
1,16
1,16
5,11
6,12
5,11
5,11
6,12
6,12
5,11
6,12
5,11
5,11
Output Voltage
Logic 0
VOL
4,13
6,12
6,12
5,11
5,11
6,12
6,12
5,11
5,11
6,12
6,12
5,11
6,12
Threshold
Voltage
Note 2.
Logic 1
Threshold
Voltage
Note 2.
Logic 0
13
VOHA
4
4
4
1,5,16
6
1,5,16
6
4
6
6
4
4
1,5,11,16
1,6,12,16
1,16
1,16
1,5,11,16
1,6,12,16
1,16
1,16
6
6
4
13
5,11
6
4
VOLA
(Vee)
Gnd
6
1. All data IS for 1/2 MC1650 or MC1651, except data marked (') which refers to the entire package.
2. These tests are done in order indicated. See Figure 5.
3. Maximum Power Supply Voltages (beyond which device life may be impaired): 'VEE' + IVCCI '" 12 Vdc.
4.
All Temperature
VA3
VA4
VA5
VA6
MC1650
+3.0
+2.98
-2.5
-2.48
MC1651
+2.5
+2.48
-3.0
-2.98
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50--{)hm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MECLData
DL122-Rev6
4-13
MOTOROLA
MC1650MC1651
MC1650 Inputs
CIRCUIT SCHEMATIC
1/2 of Device Shown
-
VCC
7,10
A
(Both Devices)
Gnd
1
Gnd
16
-B
-C
BV1 6
C2Q
30
V2 5
-D
-E
MC1651 Inputs
-A
-B
0-
-C
V1 6
E-
Rp
V2 5
8VEE
-0
Clock
-E
SWITCHING TEST VOLTAGE VALUES
(Volts)
@Test
Temperature
-30'C
VR1
+2.0
+25'C
+2.0
+85'C
+2.0
VR2
VR3
See Note 4
Vx
+1.04
Vxx
+2.0
VCc 1
+7.0
VEE1
-3.2
+1.11
+2.0
+7.0
-3.2
+1.19
+2.0
+7.0
-3.2
-30'C
Characteristic
Symbol
Switching Times
Propagation Delay
(50% to 50%) V-Input
Clock Aperture3
Max
+25'C
Min
Max
+85'C
Min
Max
isetup
tap
Unit
ns
tpd
Clock2
Clock Enable3
Min
2.0
5.0
2.0
5.0
2.0
5.7
2.0
4.7
2.0
4.7
2.0
5.2
-
-
2.5
-
-
-
ns
-
-
1.5
-
-
-
ns
Conditions
(See Figures 1-3)
VR1 to V2, Vx to Clock, P1 to V 1, or,
VR2 to V2, VXto Clock, P2 to V1, or,
VR3 to V2, Vx to Clock, P3 to V1.
VR1 to V2, P1 to V1 and P4 to Clock,
or, VR1 to V1, P1 to V2 and P4 to Clock.
Rise Time (10% to 90%)
t+
1.0
3.5
1.0
3.5
1.0
3.8
ns
Fall Time (10% to 90%)
t-
1.0
3.0
1.0
3.0
1.0
3.3
ns
VR1 to V2, P1 to V1, P4 to Clock
VRto V2, Vx to Clock, P1 toV1.
NOTES:
1. Maximum Power Supply Voltages (beyond which device life
may be impaired:
!vCC I + IVEE I " 12 Vdc.
2. Unused clock inputs may be tied to ground.
3. See Figure 3.
4.
All Temperatures
VR2
VR3
MC1650
+4.9
+4.4
-0.4
-0.9
MC1651
MOTOROLA
4-14
MECLData
DL122-Rev6
MC1650 MC1651
FIGURE 1 -
SWITCHING TIME TEST CIRCUIT @ 25°C
Voutto
Channel B
Vin to Channel A
Coax
m
r-
VCC Gnd---l
P - + - l -....---7-""i+
Q ~--+---I
D
......---+--~c
a ,.....--i-------I
I~
D
Q
I
I
I
c
a
I
I
I
~
I
VEE
L--TF~~
VEE =
-3.2Vdc
Nate: All power supply and logic levels are shawn shifted 2.0 volts positive.
50 ohm termination to ground located in each scope channel input.
All input and output cables to the scape are equal lengths of 50 ohm coaxial cable.
FIGURE 2 -
SWITCHING AND PROPAGATION WAVEFORMS @ 25°C
The pulse levels shown are used to check ae parameters
over the full common-mode range.
v-
CLOCK TO OUTPUT
INPUT TO OUTPUT
C - VIH
/50%---VR
VIL
_ _ _oJ.
PI
,-__ .......r+-___
~
Vin
VIH+2.1 V
VR +2.0V
VIL + 1.9 V
, -.., - - - - - - +1.11 V
Q
P4
C
t+
Test pulses: t +. t_ = 1.5 ± 0.2 ns (10% to 90%)
1=5.0 MHz
50% Duty Cycle
' - - - - - - +0.31 V
Q _ _ _...J
P4: t+. L= 1.5±0.2 ns.
TEST PULSE LEVELS
P1
MECLData
DL122-Rev6
P2
P3
MC1650
MC1651
MC1650
MC1651
MC1650
MC1651
VIH
+2.1 V
+2.1 V
+5.0 V
+4.5 V
--0.3 V
--0.8 V
VR
+2.0 V
+2.0 V
+4.9 V
+4.4 V
--0.4 V
--0.9 V
VIL
+1.9V
+1.9V
+4.8 V
+4.3 V
--0.5 V
-1.0V
4-15
MOTOROLA
MC1650 MC1651
FIGURE 3 -
CLOCK ENABLE AND APERTURE TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
Vout to Channel B
Yin to Channel A
o---4--------+----~c
Q~-+----,
I
I
I
I
i~+
iI
_
I
I
I
D
Q
C
Q
50
I
I"::"
L____ ~---.J
~I
-=-
~
0 VEE =-3.2 Vdc
O.t IlF
50 ohm termination to ground located in each scope channel input
All input and output cables to the scope are equal lengths of 50 ohms coaxial cable.
ANALOG SIGNAL POSITIVE AND NEGATIVE SLEW CASE
VinNegative - - - ,
Yin Positive _ _ _. I
r----------
VR+100mV=+2.1V
-"---------------- VR = 2.0 V
' - - - - - - - - - - VR-100mV=+1.9V
~~~Enable
VIH=+l.ll V
C---+-...---..
50%
~----------- VIL = +0.31 V
, - , , . , - - - '1'
~
----+-----r"'\:::f"v-- '0'
QNegative ----t-----". -,,=-l--'l'
Q Positive
-.-
'-----.0'
tpd
Clock enable time = minimum time between analog and clock signal such that output switches, and tpd
(analog to 0) is not degraded by more than 200 ps.
Clock aperture time
::l'
time difference between clock enable time and time that output dOBS not switch and
V is less than 150 mY.
Note: All power supply and logic levels are shown shifted 2.0 volts positive.
MOTOROLA
4-16
MECLData
DLl22-Rev6
MC1650 MC1651
FIGURE 4 - PROPAGATION DELAY (tpd) versus
INPUT PULSE AMPLITUDE AND CONSTANT OVERDRIVE
TEST CIRCUIT
,----------,
Yin
Vref
0--.---;-1-""I
1
VIH
0--+--+-7"-----1 C
Q P"--I!-----'¥>---O Q
0
1/2 Device
1L
50
Vref=Gnd
50
_ _ _ _ _ _ _ _ _ .J1
I
.".
POSITIVE PULSE DIAGRAM
Positive
Overdrive
-.-:-
50
1
1
Q f"--+I--'VIIIr-....- - O -2.0 V
~
~~ ~:t
~~
Q
NEGATIVE PULSE DIAGRAM
T'
Negative
~~ 1,'O:t{
Q
Input Switching time is constant
at 1.5 ns (10% to 90%).
PROPAGATION DELAY versus PULSE AMPLITUDE
5.0
II II
g
w 4.0 _
~
a:
u
~ 3.0
I I
I I I II III
Overdrive Constant @ 100 mV
- - - Positive Going Pulse
- - - Negative Going Pulse
1
MC1650",,-
I II \ D' i
~
w
MC1651
a
:z 2.0
a
~
(.!J
'>:;--..i ~~
~/'
P
~ 1.0
0
a:
-
Q.
o
0.01
Ipd referenced to PA, PB = 20 mV
i"...:.
0.02
K.
.....-: ",",I-::
0.1
0.2
0.5
1.0
PULSE AMPLITUDE PA, PB (VOLTS)
0.05
2.5
10
PROPAGATION DELAY versus OVERDRIVE
u;-
.s
w
en
US
a:
\\ .\ -;;;;
u
~
a
MC1650
'~
~
w
z
1.0
MC1651 -
~:\
'\
0
~
(.!J
~
~
0
a:
Q.
o
0.01
MECLDala
DL122-Rev6
PA, PB, Constant @ 100 mV
- - - Positive Overdrive (PA)
- - Negative Overdrive (PB)
tpd is measured from Vref on the input
to 50% on the output.
\
2.0
~~
tpd is referenced to 2.5 V overdrive.
I
~
0.02
0.04
0.07 0.1
0.2 0.3
0.5 0.7 1.0
OVERDRIVE (VOLTS)
4-17
IJ
2.5
II I
10
MOTOROLA
MC1650 MC1651
FIGURE 5 -
LOGIC THRESHOLD TESTS (WAVEFORM SEQUENCE DIAGRAM)
+0.02 V
-0.02 V
c
ri
\
Vin
I
I
I
I
VIHA
I
I
VILA
-rI
I
i
!\
i
i
'I"
Q
'a'
"1'
I
Q
'a"
I
I
I
I
I
I
Sequenlial
Tesl Number - - 1
(See TeS1 Table)
I
FIGURE 6 - TRANSFER CHARACTERISTICS (Q versus Vln)
TEST CONFIGURATION
Differential (
I~ut
--+--.
D
0-=.-.....
In
Q
I""'---!--......--.()
Q
112 Device
VIH O - - - I - - i - - - - '...
C
50
I
L _ _ _ _ _ _ _ _ _ ..JI
-2.0Vdc
-2.5 Vdc .. Vref .. +2.5 Vdc
TYPICAL TRANSFER CURVES
IReSOlu~n
L
logic '1'
logic '0"
-2.0
-20
MOTOROLA
-15
-10
-5.0
5.0
10
Vref
Yin, DIFFERENTiAl INPUT VOLTAGE (mV)
4-18
15
20
MECLData
DL122-Rev6
MC1650 MC1651
FIGURE 7 -
OUTPUT VOLTAGE SWING versus FREQUENCY
(A) TEST CIRCUIT
r-----------,
rv
I
I
I
I
I
I
VI
D
V2
Q
112 Device
-::-
C
VIH
Q
Q
50
-2.0Vdc
IL _ _ _ _ _ _ _ _ _ _ ...I
(6) TYPICAL OUTPUT LOGIC SWING versus FREQUENCY
MC1651
0.85
I".....
fi'i
~
~
'"
0.65
~
~
a
~
0.45
c..
0.25
~
0.05
~
0..
20
~
~ 0.65
.......
~
0.45
0.25
75
100\
100
:--.
30
300
~
, "
r'-.. , "\.
'\
50
70
FREQUENCY (MHz)
4-19
200
"\ ,,,\
'\ '\
\\
\
\
+
75 100\ 20? \ ~OO
Input Voltage
mV peik-to-pea~
0.05
20
~\
f
200
F:0.
50
10
MECLData
DL122- Rev 6
"" ........ r-..
"
0..
~
...........
...........
fi'i
0..
1'\.."\
\ \. '\:
\ 1\ 1\\
\
\ \ '\
50
70
FREQUENCY (MHz)
30
-
MC1650
c..
~'\
Inpul Vollage
mV Peak-lo-Peak
0.85
~
\.
!"" ~
50 _
10
§
~
:--.."
100
200
300
MOTOROLA
MC1650 MC1651
FIGURE 8 -INPUT CURRENT versus INPUT VOLTAGE
TEST CIRCUIT
1 To
Vee
1'---0.1 JlF
J:
+5.0Vdc
, __ 7 _ _ _ 1~_-,
Vee
Vee
I
.------'w....;..~+'-
0
Q """'-'--'W1r--1
,.....-J'-----IC
a .......+--'W.".........
I
-2.0Vdc
VIH!~+
0 !I
I
Q
I
I
-
-
e
LVEE
I
I
Q
Gnd
Gnd
o.lr-f--~16
~
VEE
-5.2 Vdc
J
'="
Typical MC1650 (Col1)plementary Input Grounded)
Typical MC1651 (Complementary Input Grounded)
30
-300 e , +25°C"
lo..
/.
~....
;::::-
...,.,.
-
~
-- --
::.--::
..-
--
,..--: )...-"
f - _ f-_
1'1.
--
25
<"
::!.
!z
w
a::
a:
::>
u
e-
+85°C
::>
0..
~
.10
.10
-2.5
-2
MOTOROLA
-1
0
+1
Vin, INPUT VOLTAGE (VOLTS)
+2
-300e,
20
I.--'
---
15
.-3 f -
--:
,
5
-+85°e
.......
-2.5
4-20
+25°e
~,.....
10
-5
+2.5
-
J--
-2
-1
Vin, INPUT VOLTAGE (VOLTS)
2.5
MECLData
DL122-Rev6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Voltage Controlled
Multivibrator
MC1658
The MC1658 is a voltage-controlled multivibrator which provides
appropriate level shifting to produce an output compatible with MECL III
and MECL 10,000 logic levels. Frequency control is accomplished
through the use of voltage-variable current sources which control the
slew rate of a single external capacitor.
The bias filter may be used to help eliminate ripple on the output
voltage levels at high frequencies and the input filter may be used to
decouple noise from the analog input Signal.
Pinout: 16-Lead Package (Top View)
NC
NC
CX2
INF
BIAS
CXl
NC
NC
VOLTAGE
CONTROLLED
MULTIVIBRATOR
:1'_--C~;;~=::II
CASE 620-10
1
1
IL
1
16
I
1
Recommended
for_
New
Designs
_Not
__
______
__
___
I
~
PSUFFIX
PLASTIC PACKAGE
CASE 648-0B
LOGIC DIAGRAM
VCX2
Q
Bias Filter
Q
4
..
3
DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751 8-05
4
FNSUFFIX
PLCC PACKAGE
CASE 775-02
Input Filter
VCCI = Pin 1
VCC2= PinS
VEE=Pin8
7193
© Motorola, Inc. 1996
4-21
REVO
®
MOTOROLA
MC1658
VCC2
5
VCCI
I
Q4
60
VCX2
1000
12 Bias Filter
CXll1
0---+-.....----.....
.--.----~-o14C~
80
80
lk
250
lk
Input Filter 13 o---"'-~~'-+--+----4------If--L
250
500
8
Vee
Figure 1. Circuit Schematic
TEST VOLTAGE VALUES
@Test
Temperature
Vdc±l%
VIH
V/L
V3
IIHA
-30'C
0
-2.0
-1.0
+2.0
+25'C
0
-2.0
-1.0
+2.0
+S5'C
0
-2.0
-1.0
+2.0
Note: SOIC "0" package guaranteed -30'C to +70'C only
MOTOROLA
4-22
MECLOata
0L122-Rev6
MC1658
=-5.2V, Vee =OV [GND] )
ELECTRICAL CHARACTERISTICS (VEE
-30'C
Symbol
IE
+25'C
+B5'C
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Condition
Power Supply Drain Current
-
-
-
32
-
-
mAdc
VIH to VCX Limit Applies for
lor2
VIHto Vex 1
linH
Input Current
-
-
-
350
-
-
~Adc
VOH
Output Voltage "0" HIGH
-1.045
-0.875
-0.96
-0.81
-0.89
-0.7
Vdc
VOL
Output Voltage "0" LOW
-1.89
-1.65
-1.85
-1.62
-1.83
-1.575
Vdc
AC CHARACTERISTICS (VEE
=-3.2V, Vee =+2.0V )
-30'C
Symbol
Characteristic
+25'C
Condition
+85'C
Min
Max
Min
Typ
Max
Min
Max
Unit
(See Figure 2)
-
1.6
2.7
ns
2.7
-
3.0
1.4
3.0
ns
VIHAtoVeX, eX1 4 from Pin
11 to Pin 14
t+
Rise Time (10% to 90%)
-
2.7
r-
Fall Time (10% to 90%)
-
2.7
foscl
Oscillator Frequency
130
-
130
155
175
110
78
100
120
-
-
MHz
-
-
-
3.1
4.5
-
-
-
-
fosc2
TR3
V3 to Vex. Limits Apply for 1
or2
Tuning Ratio Test
VIHA to VCX, eX25 from
Pin 11 to Pin 14
eX25 from Pin 11 to Pin 14
1 Germanium diode (0.4 drop) forward biased from 11 to 14 (11-.J- 14).
2 Germanium diode (0.4 drop) forward biased from 14to 11 (11~ 14).
3 TR = Output frequency at Vex = GND
Output frequency at Vex = - 2.0V
4 eXI =5.0pF connected from pin 11 to pin 14.
5 eX2 = 1OpF connected from pin 11 to pin 14.
VCC
+2.0Vdc
I
Coax
O.I~F
a
Channel "A'
Input 2
Coaxial Cables
(Equal lengths, 50Q)
To Scope
Coax
Channel"B"
Input 2
50 ohm termination to ground located in each scope channel input.
All input and output cables to the scope are equal lengths of 50 ohm
coaxial cable. Wire length should be < 114 inch from TPin to input pin
and TPout to output pin.
Note: All power supply and logiC levels are shown shifted 2.0V positive.
IO. l I!F
-3.2Vdc
-::VEE
Figure 2. AC Test Circuit and Waveforms
MEeLData
DL122-Rev6
4-23
MOTOROLA
MC1658
1000
100
10,000
~
1501M~ZI ~ /?5MHz@5pF
VCC - +5.2 Vde
VEE = aVde .III
en
~
~ 1000
~
~
35MHz@5pF
10
c
Vcx = OVde
Vcx=
/
1 Vde
W~
~
*'
VCx=-2Vde
I l UJJlll }u, LlL
10
100
.A
100
DC CONTROL INPUT = 4 Vde
~
w
u
z
~
13
~
(§
>~
1300
1200
1100
1000
900
800
700
600
W
500
II:
400
300
@
u.
1 20~2
...9
ex (pF) = FREQUENCY-CAPACITANCE PRODUCT AT DESIRED Vcx DESIRED FREQUENCY (MHz) -
V
./
~
V
L
V
./
.L
....
./
-1.8 -1.6 -1.4 -1.2 -1
-0.8 -0.6 -0.4 -0.2
Vex, INPUT VOLTAGE (Vdc)
VEE = -5.2V, VCC = OV.
For Use at VEE = OV, VCC = +5V (VCXP = +5V - VCx)
VCXP = Positive Input VoUage
Figure 5. Frequency Capacitance Product versus Control Voltage (VCX)
MOTOROLA
4--24
MECLDaia
DL122 -Rev 6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4-lnput OR/NOR Gate
MC1660
ELECTRICAL CHARACTERISTICS
-30'C
Characteristic
Symbol
Power Supply Drain Current
IE
Input Current
Switching Times
Propagation Delay
+25'C
Min
Max
Min
linH
-
-
-
t+t-+
0.6
0.6
1.8
1.6
t+,t-
0.6
2.2
Max
+85'C
Min
Max
350
-
-
0.6
0.6
1.7
1.5
0.6
0.6
1.9
1.7
0.6
2.1
0.6
2.3
:~'
AOUT
28
Unit
mAdc
~Adc
ns
Rise Time, Fall Time
(10% to 90%)
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-l0
ns
LOGIC DIAGRAM
AINI
AIN2
AIN3
AIN4
BINI
6
PIN ASSIGNMENT
2 AOUT
7
"~
BIN2 11
14 BOUT
BIN3 12
15 BOUT
BIN4 13
OUT = INI + IN2 + IN3 + IN4
OUT = INI + IN2 + IN3 + IN4
VCCI =PIN 1
VCC2 = PIN 16
VEP PINS
VCCI
VCC2
AOUT
BOUT
AoUT
BOUT
AINI
BIN4
AIN2
BIN3
AIN3
BIN2
AIN4
BINI
VEE
NC
tpd = 0.9 ns typ (510 ohm load)
= 1.1 ns typ (50 ohm load)
Po = 120 mW typ/pkg (No load)
Full Load Current, IL = -25 mAdc max
3/93
© Motorola, Inc. 1996
4-25
REVS
®
MOTOROLA
[IJ
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-lnput NOR Gate
MC1662
ELECTRICAL CHARACTERISTICS
-30'C
+2S'C
+85'C
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
Power Supply Drain Current
IE
-
-
56
-
-
mAde
linH
-
-
-
350
-
-
!lAde
t-+
t+-
0.6
0.6
1.6
1.8
0.6
0.6
1.5
1.7
0.6
0.6
1.7
1.9
t+,t-
0.6
2.2
0.6
2.1
0.6
2.3
Input Current
Switching Times
Propagation Delay
ns
Rise Time, Fall Time
(10% to 90%)
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-l0
ns
LOGIC DIAGRAM
AINI
AIN2
BINI
BIN2
CINI
:~2
~~3
AOUT
PIN ASSIGNMENT
BOUT
10~ 14 COUT
CIN2 II
DINI
12~
DIN2 13
15 DOUT
OUT = INI + IN2
VCCI = PIN I
VCC2 = PIN 16
VEE = PIN 8
tpd
VCCI
VCC2
AoUT
DOUT
BOUT
COUT
AINI
DIN2
AIN2
DINI
BINI
CIN2
BIN2
CINI
VEE
NC
= 0.9 ns typ (510 ohm load)
= 1.1 ns typ (50 ohm load)
=
Po 240 mW typ/pkg (No load)
Full Load Current, IL = - 25 mAde max
3/93
© Motorola, Inc. 1996
4-26
REV5
®
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Master-Slave Flip-Flop
MC1670
Master slave construction renders the MC1670 relatively insensitive to the
shape of the clock waveform, since only the voltage levels at the clock inputs
control the transfer of information from data input (D) to output.
When both clock inputs (C1 and C2) are in the low state, the data input
affects only the "Master" portion of the flip-flop. The data present in the "Master"
is transferred to the "Slave" when clock inputs (C1 "OR" C2) are taken from a
low to a high level. In other words, the output state of the flip-flop changes on the
positive transition of the clock pulse.
While either C1 "OR" C2 is in the high state, the "Master" (and data input) is
disabled.
Asynchronous Set (S) and Reset (R) override Clock (C) and Data (D) inputs.
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-l0
=
Power Dissipation 220 mW typ (No Load)
trog = 350 MHz typ
TRUTH TABLE
R
S
D
C
Q n+1
L
H
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
X
X
X
X
X
X
H
L
N.D.
an
L
an
an
H
an
L
L
L
L
H
H
H
S
H
L
S
H
LOGIC DIAGRAM
5 S-------,
7
NO = Not Defined
C=C1 +C2
Characteristic
Symbol
Power Supply Drain Current
IE
Input Current
Set, Reset
Clock
Data
Switching Times
Propagation Delay
linH
Max
Min
-
-
-
-
-
D
Q3
4
R
VCC1 = Pin 1
VCC2=Pln 16
VEE= Pin 8
1.0
2.7
Rise Time (10% to 90%)
0.9
Fall Time (10% to 90%)
t
0.5
tH"1"
tH"O"
-
-
'TOQ
270
-
Hold Time
Toggle Frequency
-
Max
48
550
250
270
+ 85'C
Min
-
-
-
Max
-
-
Unit
mAdc
~dc
PIN ASSIGNMENT
-
VCC1
ns
tpd
t+
SatupTime
+25'C
Min
tS"1"
ts"O"
1.1
2.5
2.7
1.0
2.1
0.6
0.4
0.5
0.3
0.5
300
NC
1.1
2.9
2.5
1.0
2.9
ns
Q
NC
1.9
0.6
2.3
ns
-
-
-
RESET
NC
SET
NC
-
270
-
ns
ns
NC
CLOCK 1
MHz
3193
4-27
VCC2
Q
VEE
© Motorola, Inc. 1996
Q 2
11
ELECTRICAL CHARACTERISTICS
-30'C
C1-1"--~
9 C2--..._-
REVS
@
DATA
NC
CLOCK 2
MOTOROLA
[IJ
MC1670
FIGURE 1 - TOGGLE FREQUENCY WAVEFORMS
TA=25'C
-+I.IIV
- - - +0.71 VBIAS
-
+0.31 V
t
-.-l
600 MV MIN
The maximum toggle frequency of the MCI670 has been exceeded
when either:
I. The output peak-to-peak voltage swing falls below 600
millivolts.
OR
2. The device ceases to toggle (divide by two).
FIGURE 2 - MAXIMUM TOGGLE FREQUENCY (TYPICAL)
.~
-§?
+1.05
+1.0
+0.95
+0.9
+0.85
+0.8
+0.75
+0.7
+0.65
+0.5
+0.45
+0.4
+0.35
+0.3
+0.25
175
--
I TA=125 ,C I _
VCC = +2.0 VDC VEE = -3.2 VDC -
-- 225
275
Figure 2 illustrates the variation in toggle frequency
with the dc offset voltage (VBias) of the input clock signal.
Figures 4 and 5 illustrate minimum clock pulse width
recommended for reliable operation of the MC1670.
"
./
325
375
425
FTOG
(MHZ)
FIGURE 3 - TYPICAL MAXIMUM TOGGLE FREQUENCY
versus TEMPERATURE
.-'
--
r-
250
-30
25
50
85
TA. AMBIENT TEMPERATURE (OC)
Note: All power supply and logic levels are shown shifted 2.0 volts positive.
MOTOROLA
4-26
MECLData
DL122-Rev6
MC1670
FIGURE 4 -
-
MINIMUM "DOWN TIME" TO CLOCK
OUTPUT LOAD = 50
n
CL~CK
V. t--.
1\
\
OOR
-~
1 J
\J ~
-
--::
/
c::::=
l
II
1.0Ns/DIV.
FIGURE 5 -
MINIMUM "UP TIME" TO CLOCK
OUTPUT LOAD = 50
n
I
1\
.1 '
f
r-
I--
I
v
L .J f\
I
OOR
-0-
CLOCK
1.0Ns/DIV.
MECLData
DL122- Rev 6
4-29
MOTOROLA
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Line Receiver
MC1692
ELECTRICAL CHARACTERISTICS
-30°C
Characteristic
Min
Symbol
+25°C
Max
Min
Max
Power Supply Drain
Current
IE
-
-
-
50
Input Current
lin
-
-
-
250
Input Leakage Current
IR
-
-
-
100
Reference Voltage
Switching Times
Propagation Delay
Rise Time, Fall Time
(10% to 90%)
VBB
-1.375
-1.275 -1.35 -1.25
+85°C
Min
Max
-
-
-
-
-1.3
-1.2
Unit
mAde
~dc
~dc
Vde
LSUFFIX
CERAMIC PACKAGE
CASE 62Q-10
ns
t-+
t+-
0.6
0.6
1.6
1.8
0.6
0.6
1.5
1.7
0.6
0.6
1.7
1.9
t+,t-
0.6
2.2
0.6
2.1
0.6
2.3
ns
LOGIC DIAGRAM
PIN ASSIGNMENT
AINI4~
AIN2 5 ~ 2 AoUT
BINI
BIN2
67~3
~
B
OUT
CIN110~14C
CIN211~
OUT
DIN113~15D
DIN2 12
11 __
LOUT
VBB
VCCI
VCC2
AoUT
BOUT
BOUT
GoUT
AINI
DINI
AIN2
DIN2
BIN2
CIN2
BINI
CINI
VEE
VBB
9
VCCI =PINI
VCC2=PIN 16
VEE=PIN8
tpd = 0.9 ns typ (510 ohm load)
= 1.1 ns typ (50 ohm load)
Po = 220 mW typ/pkg (No Load)
Full Load Current, IL -25 mAdc max
=
9/96
© Motorola, Inc. 1996
4-30
REV6
®
MOTOROLA
MC1692
APPLICATION INFORMATION
The MC1692 quad line receiver is used primarily to
receive data from balanced twisted pair lines, as indicated
in Figure 1. The line is driven with a MC1660 ORiNOR
gate. The MC1660 is terminated with SO ohm resistors to
-2.0 volts. At the end of the twisted pair a 100 ohm
termination resistor is placed across the differential line
receiver inputs of the MC1692.llIustrated in Figure 2 is the
sending and receiving waveforms at a data rate of 400
megabits per second over an 18 foot twisted pair cable.
FIGURE 1 -
The waveform picture of Figure 3 shows a S.O nanosecond pulse being propagated down the 18 foot line. The
delay time for the line is 1.68 ns/foo!.
The MC1692 may also be applied as a high frequency
schmitt trigger as illustrated in Figure 4. This circuit has
been used in excess of 200 MHz. The MC1692 when
loaded into SO ohms will produce an output rising edge of
about 1.S nanoseconds.
LINE DRIVER/RECEIVER
1/4
MC1692
50
VEE =-5.2 VDC
Vn =-2.0 V
FIGURE 3 -
FIGURE 2 - 400 MBS WAVEFORMS
Sending
End
Sending
End
2.0 ns/em
S.Ons/em
Receiving
End
Receiving
PULSE PROPAGATION WAVEFORMS
End
FIGURE 4 - 200 MHz SCHMITT TRIGGER
VEP-5.2V
-1.3~>-----'-f
SL
0.01
500
0.01
50
'----+---IT
llF
IlF
~~~---~--~
100
Vn=-2.0V
MECLData
DL122-Rev6
4-31
MOTOROLA
MOTOROLA
4-32
MECLData
DLI22-Rev6
MECL Data
Carrier Band Modem
MECLData
DLl22-Rev6
5-1
MOTOROLA
[5J
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Carrier Band Modem (CBM)
MC68194
The bipolar LSI MC68194 Carrier Band Modem (CBM) when combined with
the MC68824 Token Bus Controller provides an IEEE 802.4 single channel,
phase--coherent carrier band Local Area Network (LAN) connection. The CBM
performs the Physical Layer function including symbol encoding/decoding,
signal transmission and reception, and physical management. Features
include:
o
o
o
o
o
o
o
o
o
Implements IEEE 802.4 single channel, phase--coherent Frequency Shift
Keying (FSK) physical layer including receiver blanking.
Provides physical layer management including localloopback mode,
transmitter enable, and reset.
Supports data rates from 1 to 10 Mbps. IEEE 802.4 standard uses 5 or
10 Mbps.
Interfaces via standard serial interface to MC68824 Token Bus Controller.
Crystal controlled transmit clock.
Recovery of clocked data through phase-locked loop.
RC controlled Jabber Inhibit Timer.
Single +5.0 volt power supply.
Available in 52-lead Cerquad package.
FJSUFFIX
J-LEAD CERQUAD PACKAGE
CASE 7788-01
PIN ASSIGNMENTS
RXSYM2
VCM·C2
N.C.
VCM·C1
VCC-TIL
VCX
GND-TIL
GND
RESET
TXSYMO
TXSYM1
CPW
MC68194
CBM
41
RPW
SET-PW
TXSYM2
GND
SMREQ'
RXIN'
TXCLK
JAB
EOTDIS'
Vce-OSC
RXIN
FDBK'
FDBK
THRESHOLD
MC68194
TABLE OF CONTENTS
PAGE
SECTION 1 -
1.1
1.2
1.3
1.4
GENERAL DESCRIPTION
TOKEN BUS LAN CARRIER BAND NODE OVERVIEW ......................................
CARRIER BAND MODULATION TECHNIQUE ..............................................
MESSAGE (FRAME) FORMAT ...........................................................
SYSTEM CONFIGURATION .............................................................
5-4
5-4
5-5
5-5
SECTION 2 - SIGNAL DESCRIPTION TABLE ..................................................... 5-7
SECTION 3 - TRANSMITTER
3.1 OVERVIEW ............................................................................ 5-9
3.2 TRANSMIT BUFFER .................................................................... 5-9
3.3 JABBER INHIBIT ...................................................................... 5-10
3.4 CLOCK GENERATOR .................................................................. 5-10
3.4.1
Parallel-Resonant, Fundamental Mode Crystal ..................................... 5-10
3.4.2 Parallel-Resonant, Overtone Mode Crystal ......................................... 5-11
3.4.3 External Clock Source .................. .. . . . . . . .. . . . .. . . .. . . . . . . .. . . . . . . . . . .. . .. 5-11
SECTION 4 -
RECEIVER AMPLIFIER/LIMITER WITH CARRIER DETECT
4.1 OVERViEW ........................................................................... 5-12
4.2 AMPLIFIER ........................................................................... 5-12
4.3 CARRIER DETECT .................................................................... 5-12
SECTION 5 -
5.1
5.2
5.3
SECTION 6 -
6.1
6.2
7.3
DATA RECOVERY
OVERViEW ........................................................................... 5-15
RECEIVER END-OF-TRANSMISSION BLANKING ........................................ 5-16
SECTION 7 -
7.1
7.2
CLOCK RECOVERY
OVERViEW ........................................................................... 5-13
ONE-SHOT ........................................................................... 5-13
PHASE-LOCKED LOOP (PLL) COMPONENTS ........................................... 5-14
5.3.1
Phase Detector (PO) ............................................................ 5-14
5.3.2 Voltage Controlled Multivibrator (VCM) ............................................. 5-14
5.3.3 Loop Filter ..................................................................... 5-14
5.3.4 Loop Characteristics ............................................................ 5-15
SERIAL INTERFACE
OVERViEW ........................................................................... 5-17
PHYSICAL DATA REQUEST CHANNEL .................................................. 5-17
7.2.1 TXCLK- Transmit Clock ........................................................ 5-17
7.2.2 SMREQ* - Station Management Request ......................................... 5-17
7.2.3 TXSYMO, TXSYM1, and TXSYM2 - Transmit Symbols ............................. 5-17
PHYSICAL DATA INDICATION CHANNEL ................................................ 5-17
7.3.1
RXCLK- Receive Clock ........................................................ 5-17
7.3.2 SMIND* - Station Management Indication ......................................... 5-17
7.3.3 RXSYMO, RXSYM1, and RXSYM2 - Receive Symbols ............................. 5-17
SECTION 8 - PHYSICAL MANAGEMENT
8.1
8.2
8.3
8.4
8.5
8.6
OVERViEW ........................................................................... 5-18
RESET ................................................................................ 5-18
INTERNALLOOPBACK ................................................................ 5-18
STANDARD OPERATION ............................................................... 5-18
IDLE .................................................................................. 5-18
COMMAND RESPONSE TIMING ........................................................ 5-18
SECTION 9 -
MECLData
DL122- Rev 6
ELECTRICAL SPECIFICATIONS TABLES ........................................... 5-20
5--3
MOTOROLA
I5l
LYJ
MC68194
SECTION 1
GENERAL DESCRIPTION
1.1 TOKEN BUS LAN CARRIER BAND NODE OVERVIEW
The MC68194 Carrier Band Modem (CBM) is part of
Motorola's solution for an IEEE 802.4 token bus carrier band
local Area Network (LAN) node. The CBM integrates the
function of the single-channel, phase-coherent Frequency
Shift Keying (FSK) physical layer. Figure 1-1 illustrates the
architecture of a token bus lAN node as commonly used in
Manufacturing Automation Protocol (MAP) industrial
communications. Based on the ISO-OSI model, the llC
Sublayer and additional upper layers are typically supported
by a local MPU subsystem, while the IEEE 802.4 token bus
MAC Sublayer and Physical layer are implemented by the
MC68824 Token Bus Controller (TBC) and MC68194 CBM
respectively.
The MC68194 provides the three basic functions of the
physical layer including data transmission to the coax cable,
data reception from the cable, and management of the
physical layer. For standard data mode (also called MAC
mode), the carrier band modem receives a serial transmit data
stream from the MC68824 TBC (called symbols or atomic
symbols), encodes, modulates the carrier, and transmits the
signal to the coaxial cable. Also in the data mode, the CBM
receives a signal from the cable, demodulates the signal,
recovers the data, and sends the received data symbols to the
TBC. Communication between the TBC and CBM is through
a standardized serial interface inconsistent with the IEEE
802.4 DTE-DCE serial interface.
The physical layer management provides the ability to reset
the CBM, control the transmitter, and do loopback testing.
Also, an onboard RC timer provides a "jabber" inhibit function
to turn off the transmitter and report an error condition if the
transmitter has been continuously on for too long. Similar to
the data mode, the CBM management mode makes use of the
TBC serial interface.
1.2 CARRIER BAND MODULATION TECHNIQUE'
The CBM uses phase-coherent frequency shift keying
(FSK) modulation on a single channel system. In this
modulation technique, the two signaling frequencies are
integrally related to the data rate, and transitions between the
two signaling frequencies are made at zero crossings of the
carrier waveform. Figure 1-2 shows the data rate and
signaling frequencies. An {l} is represented as one half cycle
of a signal, starting and ending with a nominal zero amplitude,
whose period is equal to the period of the data rate, with the
phase of one half cycle changing at each successive {l}. An
{H) is represented as one full cycle of a signal, starting and
ending with a nominal zero amplitude whose period is equal
to half the period of the data rate. In a 5 Mbps implementation,
the frequency of {l} is 5.0 MHz and for {H) is 10 MHz. For a
10 Mbps implementation, the frequency of {l} is 10 MHz and
for {H) is 20 MHz. The other possible physical symbol is when
no signal occurs for a period equal to one half of the period of
the data rate. This condition is represented by {off}.
Data Rate
MBPS
Frequency of Lower
Tone MHz{L}
Frequency of Higher
Tone MHz {H}
5
10
5.0
10
10
20
Figure 1-2. Data Rate versus Signaling Frequencies
The specified physical symbols ({l), {H) and {off) are
combined into pairs which are called MAC-symbols. The
MAG-symbols are transferred across the serial link. The
encodings for the five MAC-symbols are shown in Figure 1-3.
Figure 1-4 shows the phase coherent FSK modulation
scheme for ONE, ZERO, and NON-DATA. The IEEE 802.4
document does not specify the polarity used to transmit data
on the physical cable. The receiver must operate without
respect to polarity.
t
Mac-Symbol
LLC
&
UPPER
LAYERS
Silence
Pad-Idle
Pairs
Zero
One
Non-Data
ND1
ND2
ONE
Encoding
{off
{L
{H
{L
off}
L}{H
H}
L}
H}
{H LI
{L HI
Figure 1-3. MAC Symbol Encoding
MODULATOR
I
TRANSMITIER
DEMODULATOR
I
RECEIVER
,
PHYSICAL
LAYER
ZERO
MEDIA
LAYER
H
*
Figure 1-1. IEEE 802.4 Token Bus Carrier Band Node
MOTOROLA
H
ND1
ND2
1 BIT TIME =
11 BIT RATE
1 BITTIME
Figure 1-4. Phase-Coherent Modulation Scheme
5-4
MECLData
DL122-Rev6
MC68194
1.3 MESSAGE (FRAME) FORMAT
1.4 SYSTEM CONFIGURATION
Figure 1-5 illustrates the CBM and peripheral circuitry
required for an IEEE 802.4 carrierband 5 Mbps or 10 Mbps
data rate phase-coherent FSK physical layer. The CBM
communicates with the MAC or TBC through a TTL
compatible serial interface that is consistent with the IEEE
802.4 exposed DTE-DCE interface. Management and
transmission symbol requests are accepted via the CBM
phYSical data request channel (TXSYMD-TXSYM2,
SMREQ*, and TXCLK). The physical data indication channel
(RXSYMD-RXSYM2, SMIND*, and RXCLK) is used to send
received symbols and management responses to the MAC.
The periphery circuitry is primarily associated with interface
to the LAN coaxial cable and data recovery. An external crystal
or clock source is required (20 MHz for 5 Mbps data rate or 40
MHz for 10 Mbps data rate) for onboard timing and transmit
clock. Also, an RC timing network sets the jabber timeout
period.
The coaxial cable interface cornbines the transmit and
receive signal functions. For transmission, the CBM provides
differential drive signals (TXOUT and TXOUT*) whose
signaling is ECL levels referenced to VCC (logic high = +4.1
V, logic low = + 3.3 V) and a gate signal called TXDIS. The
IEEE 802.4 standard puts specific requirements on the signal
transmitted to the cable:
Between +63 dB and +66 dB (1.0 mV, 75 Q) [dBmV]
output voltage level.
Transmitter-off leakage not to exceed -20 dB
(1.0 mV, 75 Q) [dBmV].
Signal transition time window (eye pattern)
dependent on data rate.
Because of this, an external amplifier with waveshaping is
required. The CBM TXOUTITXOUT* outputs provide
complementary signals with virtually no slew, and the TXDIS
is an enable signal helpful for turning the external amp off
"hard" to meet the low level leakage.
On the reception side, the CBM requires a pre-amplifier to
receive the low level signal from the cable. The signal
available at the "F"-connector can range from +10 dB to +66
dB (1.0 mV, 75 Q) [dBmV]. The signal required at the CBM is
about 12 dB above this (net gain through the transformer,
pre-amp, and any filtering). The receiver can be used in full
differential or single-ended mode.
A second part of the receiver function is the signal detect or
carrier detect function. The IEEE 802.4 requires that the
receiver detect a signal of + 10 dBmV or above (i.e., be turned
"on") and report Silence for a signal of +4.0 dBmV or below
(i.e., be turned "off"). Therefore, a 6.0 dB (2:1 voltage ratio)
range or window is defined in which the signal detect must
switCh. The CBM is optimized for this range (including the
pre-amp gain), although it is trimmed via an external
THRESHOLD.
The remaining external components are associated with
clock recovery. A capaCitor and resistor (internal R also
provided) set one-shot timing, and an active filter for a PLL
used in clock and data recovery is required. The active filter
can be implemented via an op amp, or if 5.0 volt operation is
required, an alternate charge pump design can be used. The
Although the CBM only uses MAC symbols one-at-a-time,
the MAC or TBC is responsible for combining the above
defined MAC symbols into messages (more correctly called
frames). For the purposes of the CBM, a simplified frame
format can be used consisting of:
SILENCE II PAD-IDLE I START DELIMITER I DATA I END
DELIMITER II SILENCE
where:
PAD-IDLE
alternating {LL} {HH} pairs which must
occur in octets or groups of eight symbols.
Pad-idle provides a training signal for the
receiver and occurs at the beginning of
every transmission (and between frames
in a multiple frame transmission).
START
DELIMITER
a unique pattern of eight symbols (one
octet) that marks the beginning of a frame.
The pattern is:
NDI ND20NDl ND2000
where NDI is the first symbol transmitted.
DATA
octets of ZERO/ONE patterns that are the
actual data or "information" contained
within the frame.
END
DELIMITER
a unique pattern of symbols that marks the
end of a frame. The pattern is:
NDI ND2 1 NDI ND2 1 {1=O/I} {O/I}
where NDI is the first symbol transmitted.
Note that unlike the Start Delimiter, the last
two bits of the End Delimiter octet are not
always the same. The seventh bit of the
octet is called the I Bit or Intermediate bit
which = 1 when there is more to transmit
and = 0 at the end of a transmission.
A single transmission can consist of one or more frames. In
a multi-frame transmission, Pad-Idle is sent between
consecutive frames to separate them. If an End Delimiter
occurs within a multi-frame transmission its I Bit will = I, and
the last end delimiter will have its I Bit = O.
The CBM accepts a stream of MAC symbols from the TBC
and modulates the phase-coherent transmit signal
accordingly. Conversely, the CBM receives a phase-coherent
signal stream from the cable, decodes the MAC symbols, and
reports them. On transmission there is a direct one-to-one
correlation between MAC symbols requested and the
modulated signal; however, during reception exceptions can
occur. The CBM is allowed to report Silence or the actual
Zero/One pattern during preamble which is done to allow the
receiver to "train" to the incoming signal. Also, if noise in the
system has corrupted the data, it may show up as an incorrect
MAC symbol or the CBM can report a BAD SIGNAL symbol
if an incorrect combination of ND symbols is detected (ND2
without an ND1, ND2 followed by ND2, etc.)
MECLData
DL122 - Rev 6
5-5
MOTOROLA
MC68194
RESET
TXDIS
AMPLIACATION
AND
WAVESHAPING
q
F-GONNECTOR
Figure 1-5. Functional Block Diagram
clock recovery and data decoder is a synchronous design
which provides superior performance minimizing clock jitter.
.Although primarily intended for the IEEE 802.4 carrier band,
the CBM is also an excellent device for point-ta-point data
MOTOROLA
links, fiberoptic modems, and proprietary LANs. The
MC68194 canbe used over a wide range of frequencies and
interfaces easily into different kinds of media .
MECLData
DL122-Rev6
MC68194
SECTION 2
SIGNAL DESCRIPTION
Symbol
Type
Name/Description
TXSYMO-TXSYM2
TTLlI'
TRANSMIT SYMBOLS - These TTL inputs are request channel signals used to send
either serial transmission symbols in the MAC mode or commands in station
management mode. They are synchronized to TXCLK and are normally connected to
the TXSYMX outputs of the MC68824. SMREO* selects the meaning of these signals
as either MAC mode or management mode.
SMREQ*
TTLlI'
STATION MANAGEMENT REQUEST - A TTL input that selects the mode of the
request channel signals TXSYMX. Synchronized to TXCLK, SMREO* is equal to one
for MAC mode and equal to zero for management mode. It is normally driven by the
SMREO* output of the MC68824.
TXCLK
TTLIO
TRANSMIT CLOCK - A TTL clock output generated from the crystal oscillator (it is 1/4
of the oscillator frequency) used to receive request channel symbols from the MC68824.
TXCLK is equal to the data rate of the application (5.0 MHz or 10 MHz for IEEE 802.4).
TXSYMX and SMREO* are synchronized to the positive edge of TXCLK which is
supplied to the MC68824.
RXSYMD-RXSYM2
TTLIO
RECEIVE SYMBOLS - These TTL outputs are indication channel signals used to
provide either serial receive symbols in MAC mode or command confirmation/indication
in station management mode. They are synchronized to RXCLK and are normally
connected to the RXSYMX inputs of the MC68824. SMIND* selects the meaning of
these signals as either MAC mode or management mode.
SMIND'
TTLIO
STATION MANAGEMENT INDICATION - A TTL output that indicates the mode of the
CBM and RXSYMX lines. Synchronized to RXCLK, SMIND* is equal to one for MAC
mode and equal to zero for management mode. It is normally connected to the SMIND*
input of the MC68824.
RXCLK
TTLIO
RECEIVE CLOCK - A TTL clock output used to send indication channel symbols to
the MC68824. Its frequency is nominally equal to the data rate (5.0 MHz or 10 MHz for
IEEE 802.4). RXCLK is generated from a PLL that is locked to the local oscillator during
loopback, station management, orthe absence of received data. During frame reception
the PLL is locked to the incoming received data. RXSYMX and SMIND* are
synchronized to negative edge of RXCLK.
EOTDIS'
TTL/I*
END-OF-TRANSMISSION DISABLE - When low, this TTL input disables the
end-of-transmission receiver blanking required by the IEEE 802.4 Spec, Section
12.7.6.3. When high the blanking works in accordance with the spec requirements.
TXOUT,TXOUT*
ECLIO
TRANSMIT OUTPUTS - A differential output Signal pair (MECL level referenced to
VCC) used to drive the transmitter cirCUitry. The silence or "off' state is both outputs one
(high). The output data stream is phase-ooherent FSK encoded.
OC
TRANSMIT DISABLE - An open collector output used to disable transmitter circuitry.
This output is high when the transmitter is off (TXOUT and TXOUT* both high).
JAB
TTLIO
JABBER - A TTL output signal generated from the jabber-inhibit timer. When equal
to one, JAB indicates the timer has timed-out and an error has occurred.
RESET
TTLlI'
RESET -
TXDIS
A TTL input signal that when high asynchronously resets the CBM.
RXIN, RXIN*
RECEIVER INPUTS - A differential input Signal pair for the receiver amplifierllimiter.
These inputs may be used differentially or single ended.
FDBK, FDBK*
DC FEEDBACK BYPASS - These two pOints are provided to bypass dc feedback
around the receiver amplifier.
'All TTL inputs include a 15 kQ pullup resistor to Vcc.
MECLData
DL122- Rev 6
5-7
MOTOROLA
MC68194
Signal Description (Cont.)
Symbol
Type
Name/Description
THRESHOLD
I
THRESHOLD ADJUST - The receiver threshold detect is trimmed with this pin.
GAIN
o
GAIN - This output can be used to monitor the receiver amplifier output signal. Used
only for test purposes.
CARDET
o
CARRIER DETECT - This output can be used to filter the internal signal that is
sampled to sense carrier detect.
RPW,CPW
PULSE-WIDTH RESISTOR/CAPACITOR - A resistor and capacitor set a one-shot
pulse width used in the clock recovery circuitry.
o
SET-PW
UP', DOWN"
ECUO
PULSE WIDTH TEST POINT one-shot pulse width.
Output test point used for adjusting clock recovery
PLL PHASE DETECTOR OUTPUTS - UP' and DOWN' are the pump-up and
pump-down outputs, respectively, of the PLL digital phase detector. They are MECL
levels referenced to +5.0 volts and are used to drive inputs to an active filter or charge
pump for the PLL.
vcx
VCM CONTROL multivibrator.
VCM-C1, VCM-C2
VCM CAPACITOR - VCM capacitor inputs. VCM frequency is 4X RXCLK.
JAB-RC
JABBER-INHIBIT RC - A resistor-capacitor network connected to this pin sets the
jabber-inhibit time constant.
XTAL,1 XTAL2
CLOCK CRYSTAL - Oscillator circuit inputs may be used with a crystal or an external
clock source. Oscillator frequency is 4X data rate.
The control voltage applied to the PLL voltage controlled
VCC-VCM
VCM POWER - 5.0 ± 5% volts for VCM.
VCC-TXOUT
TXOUT POWER - 5.0 ± 5% volts for TXOUTITXOUr.
VCc-OSC
OSCILLATOR POWER - 5.0 ± 5% volts for oscillator.
VCC-RCV
RECEIVER POWER - 5.0 ± 5% volts for receiver amplifierllimiter.
VCC
LOGIC POWER - 5.0 ± 5% volts for remaining logic.
VCe-TTL
TTL POWER - 5.0 ± 5% volts for TTL output buffers.
GND-TTL, GND-VCM,
GND-LOGIC, GND-OSC,
GND-RCV, GND-SUBS, GND
GROUND- Reference voltage for TTL buffers, VCM, internal logic, oscillator, receiver/
limiter, substrate respectively. Two additional grounds are used to isolate signals.
MOTOROLA
5-8
MECLData
DL122-Rev6
MC68194
SECTION 3
TRANSMITTER
3.1 OVERVIEW
TXDIS
The transmitter function includes the serial interface
decoder, transmit modulator, transmit buffer, jabber inhibit,
and clock generator. (Although the clock generator is not used
exclusively by the transmit function, the generator will be
discussed here.) The MC68194 receives request channel
symbols on the TXSYMX pins which are synchronized to
TXClK. As is described in the Serial Interface discussion,
MAC transmit symbols are input serially (CBM in MAC mode),
decoded, and used to modulate an output signal. The Serial
Interface Decoder is used both for MAC mode to decode data
transmit commands (symbols) and management mode to
decode management commands. The decoded transmit
commands or symbols are used by the Transmit Modulator to
generate phase-coherent signaling as discussed in the CBM
General Description. The transmit buffer receives the
modulated signal and drives differential output signals.
The clock generator provides TXClK and internal clocks of
2 times (2X) and 4 times (4X) TXClK. The 4X clock is actually
the oscillator frequency. These clocks are used to receive the
TX symbols and generate the modulated signal.
I
I
IVCC-TXOUT
TXOUT
RP
TXOUT'
RP
Figure 3-1. Transmitter Outputs
3.2 TRANSMIT BUFFER
8.
The modulated transmit data stream drives the TXOUT and
TXOUT* pins of the MC68194. These pins are
complementary outputs with closely matched edge
transitions. This is useful in helping meet the IEEE 802.4
carrierband requirement for a transmit jitter of less than ± 1%
of the data rate. TXOUT and TXOUT* are generally used to
drive a differential amplifier which is used to achieve the
necessary output level at the cable and meet the rise/fall time
window (or "eye" pattern) of the IEEE 802.4. A third output
called TXDIS is available to gate the amplifier circuitry on or
off.
The TXTOUT and TXTOUT* have ECl levels referenced to
VCC (Figure 3-1). levels are typically 4.11 V for a high and
3.25 for a low. Pulldown resistors are required with the outputs
specified to drive a maximum load of 220 n to ground
reference.
Operation of the transmit outputs is controlled in the
following manner:
6.
Jabber inhibit activated - If the jabber inhibit fires, it
forces the CBM into management mode and disables
the TX outputs. This condition can only be cleared by
a reset condition.
The TXDIS output is an open collector switched current
source. TXDIS sinks a nominal 0.5 mA when the
TXOUTITXOUT* outputs are enabled. TXDIS is off or high
impedance when the transmitter is disabled.
The signaling on the TX outputs and TXDIS is shown in
Figure 3-2. The "off' or silence condition is both TXOUT
outputs high and TXDIS also high. The figure shows an
example of the signal pattern for both leaving and entering a
silence condition.
SILENCE
~~
OFF
Management mode - The TX outputs are always
disabled while the CBM is in management mode. When
leaving management mode the TX outputs remain.
disabled if a RESET command has been issued and an
ENABLE TRANSMITTER and DISABLE lOOPBACK
commands have not been issued. Resetting the CBM
enables internalloopback and disables the transmitter.
o
ND1
ND2
OFF
TXDIS
TXOUT'
7.
MAC (data) mode - After leaving management
mode, the CBM can function in internal loopback (for
test) with the transmitter disabled, out of loopback with
transmitter disabled (receive only), or in standard data
mode with the TX outputs controlled by the modulator.
MECLData
DL122-Rev6
Figure 3-2. Transmitter Output Signaling
5-9
MOTOROLA
MC68194
3.3 JABBER INHIBIT
The jabber inhibit function prevents the transmitter from
transmitting indefinitely. An external resistor and capacitor
pair tied to the CBM JAB-RC pin set the maximum time that
the transmitter is allowed to transmit. When transmission is
attempted for a period longer than the specified time, the
jabber inhibit function forces the transmitter to shut down and
alerts the system that this has been done by generating a
PHYSICAL ERROR indication on the serial interface
indication channel. The error indication is removed only after
a reset has occurred on the RESET pin or after a RESET
command has been received on the station management
interface. The ENABLE TRANSMITTER and DISABLE
LOOPBACK commands can then be used to re-enable the
transmitter outputs. While the PHYSICAL ERROR indication
is present, the normally-low JAB pin of the MC68194 will be
high. This TTL output may be used to turn off external
transmitter circuitry or an isolation relay.
A block diagram of the jabber inhibit function is shown in
Figure 3-3. When edges are present on the TXDATA line, the
jabber capacitor is allowed to charge. When the transmitter
stops transmitting, the capacitor is discharged. The circuit
looks for any edges in the previous 16 TXCLKs before
deciding whether to charge or discharge the capacitor. When
the capacitor voltage reaches the reference threshold, the
comparator switches and the jabber output is latched. The
jabber output is fed back internally and disables the
transmitter. This signal is also brought out to the JAB pin for
use in disabling external transmitter circuitry.
Forthe IEEE 802.4 spec, the jabber timeout must be 0.5 sec
± 25%. An RC time constant of 265 millisec. will give about a
0.5 sec timeout. The maximum resistor size is 125 kQ.
Components should be 10% tolerance or better. Common
values are R = 120 kO and C = 2.2 11F.
3.4 CLOCK GENERATOR
The clock generator is used to generate all of the transmit
timing, TXCLK, and internal CBM timing for station
management and loopback. The generator consists of a
crystal oscillator/buffer that drives + 2 and + 4 stages. The
RJAB
oscillator frequency must be four times (4X) the serial data
rate. As an example, the IEEE 802.4 5 Mbps carrier band
(TXCLK 5.0 MHz) requires an oscillator frequency of 20
MHz. The basic circuit is a single transistor Colpitts oscillator
as shown in Figure 3-4.
The oscillator is used in one of three modes depending on
the data rate and the application:
=
1.
With a parallel-resonant, fundamental mode crystal.
2.
With a parallel-resonant, overtone mode crystal.
3.
With an external clock source.
The fundamental mode can typically be used up to
frequencies of about 20 MHz; this is crystal dependent and
some crystal types can be used as high as 40 MHz. Beyond
the fundamental mode upper limit, an overtone mode crystal
is used. An alternative to a crystal is an external clock source
such as an integrated crystal clock to drive the CBM.
3.4.1 Parallel-Resonant, Fundamental Mode Crystal
Figure 3-4 shows the external crystal and capacitors C1
and C2 used for fundamental mode operation. The crystal
must be parallel resonant with a maximum series resistance
of300.
This configuration is normally used for the IEEE 802.4
5 Mbps carrierband standard. The required transmit
frequency stability is ± 100 ppm (0.01%). It is suggested that
a crystal with a total frequency tolerance (calibration
tolerance, temperature variation, plus aging) of ± 50 ppm to ±
60 ppm be used. The remaining frequency budget is reserved
for the CBM and other components over temperature and
power supply variation.
The series combination of C1 and C2 should be equal to the
specified crystal load (typically 20 pF or 32 pF). Additionally,
C1 and C2 should be large enough to swamp out the CBM
device capacitance. The XTAL 1 input capacitance is typically
1.5 pF to 2.0 pF, and C1 should be at least an order of
magnitude greater (C1 > 20 pF). Also, C1 must be greaterthan
the crystal load capacitance because of the series
combination of C1 and C2. Generally the ratio C1 :C2 is from
1:1 t03:1.
CJAB
JAB PIN
~
--+sv---
VCC
JABRC
_ _ _ _ _ _ _ _ _ ..illl_
+5V
INTERNAL
JABBER INHIBIT
PHYSICAL MANAGEMENT _ _ _...J
OR HARDWARE RESET
TXCLK
Figure 3-3. Jabber Inhibit Block Diagram
MOTOROLA
5-10
MECLDala
DL122- Rev 6
MC68194
frequency the tank circuit impedance will appear capacitive;
therefore, the load to the crystal is C1 in series with the
capacitive reactance of the tank circuit.
This series combination should be equal to the desired
crystal load. Typically, C2 will increase in value as compared
to the fundamental mode situation because of the cancelling
effects of L1. Again the user is directed to the above reference
for optimum selection of components.
For a 20 pF crystal load:
20 pF
=C1C2I(C1 + C2)
and
C2
=20 pF [C1/(C1 -
20 pF)]
Typical values are C1 = 60 pF and C2 = 30 pF.
It is suggested that best results will be had with close
tolerance (5%) NPO ceramic capacitors
trimming should
not be required. If trimming is necessary, a third trimming
capacitor C3 can be placed in series with the crystal.
CapaCitors C1 and C2 will have to be increased in value
because the crystal load now becomes C1 and C2 and C3 in
series. For help in designing the capacitor network the user is
directed to Design of Crystal and Other Harmonic Oscillators,
B. Parzen, Wiley, 1983.
3.4.3 External Clock Source
Figure 3-5 shows the connection used for a TIL compatible
external clock source. XTAL 1 and XTAL2 are tied together
defeating transistor 01. External resistor R1 2.0 kO assures
a high level greater than 3.0 V at an input current of 800 !lAo
The TIL driver must be capable of sinking 2.5 mA.
=
3.4.2 Parallel-Resonant, Overtone Mode Crystal
Figure 3-4 also shows the network used for overtone mode
operation. The crystal is still parallel resonant, but must be
speCified for overtone (harmonic) operation at the desired
frequency. A low series resistance of less than 30 (1 is
recommended.
VCC
VCc-OSC
II
fif:
OVERTONE
':'
':'
FUNDAMENTAL
:==1
':'
':'
TTL
CLOCK
OSC
CBM
I
I
R1 =2kQ
XTAL1
~--~------o-~~
XTAL2
TO
L----o-++--+-... BUFFER
f=~o- -,:It-+- 20kn-+-+"'80 ~
':'
2.5mA
_
+800~
GND-OSC
Figure 3-5. TIL Compatible Clock Source Driving CBM
GND-OscL _ _ _ _
The IEEE 802.4 for 5 Mbps or 10 Mbps data rate carrier
band requires a transmit frequency stability of ± 100 ppm
(0.01 %). The external clock source must be specified for this
stability over temperature.
Figure 3-4. Crystal Oscillator Schematic Shows
Configurations For Both Overtone and
Fundamental Modes
Inductor L1 and capaCitor C2 form a tank circuit that is
parallel resonant at a frequency lower than the desired crystal
harmonic but above the next lower odd harmonic. C3 0.01
IlF is a dc blocking capacitor to ground. At the operating
=
MEeL Data
DL122- Rev 6
5-11
MOTOROLA
MC68194
SECTION 4
RECEIVER AMPLIFIER/LIMITER WITH CARRIER DETECT
4.1 OVERVIEW
The IEEE 802.4 spec provides that the incoming signal
range for good signal is+10dB (1.0 mY, 750) [dBmV]to +66
dB (1.0 mY, 75 0) [dBmV] available at the modem connector.
The IEEE 802.4 further specifies that the modem will report
silence for any signal below +4.0 dB (1.0 mY, 750) [dBmV].
Therefore, the receiver function must amplify any signal of + 10
dBmV and above to limiting for good data recovery, and the
signal detect must switch within the +4.0 dBmV to + 10 dBmV
window, that is, it must be "off' for +4.0 dBmV and below, and
be "on" for +10 dBmV and above. The MC68194 requires a
pre-amplifier of about 12 dB in front of the onboard amplifier
and carrier detect function. Clock and data recovery are
extracted from the amplifiedllimited incoming signal, and the
carrier detect is used to control the clock and data recovery
function based on presence of good signal.
4.2 AMPLIFIER
Figure 4-1 shows a simple block diagram of the receiver
amplifier. Intemally, dc feedback is used to bias the amplifier,
and connection pOints FDBK and FDBK* are provided to ac
bypass the feedback. With both receiver inputs RXIN and
RXIN* available, the device can be wired either for differential
or single-ended operation. Differential is preferred for low
noise.
An extemal preamplifier with gain of about 12 dB is used
with the onboard amplifier. The pre-amp can drive the CBM
either single-ended or differentially. The onboard amplifier
output signal is used in two ways. One path adds an additional
limiter stage and is used to drive the clock and data recovery
stages. The second path is used to develop carrier detect.
In the signal window where carrier detect must be active, the
internal amplifier remains in the linear (non-limiting) range. Its
output is fullwave rectified, and the rectified signal is
compared to an onboard threshold that is temperature and
voltage compensated. The rectified signal is also brought out
to an external lead called CARDET. A capacitor can be added
at this pin which combines with the series 125 0 resistor to
form a low pass filter. This filtering is used to knock any high
frequency noise off of the signal. The output of the comparator
is a series of pulses (when the signal amplitude is sufficiently
large) which are digitally integrated in the internal squelch
signal.
4.3 CARRIER DETECTION THRESHOLD
The carrier detect threshold is internally generated and
compensated for power supply and temperature variation.
The THRESHOLD pin is provided to adjust the threshold via
an external resistor tied to VCC.
~~----------~~C>OR
~~------------4--r~NOR
}TORXMUX
CARDET L
~~~~4A~--~-4~CARDETS~
TO SQUELCH
(A) Receiver Used in Differential Mode
~~-----------L~c>OR
r--L~-------------4~C>NOR
}TORXMUX
CARDETL
~~~~4 A~--~-4> CARDET~ TO SQUELCH
FDBK'
(8) Receiver Used In Single-Ended Mode
Figure 4-1. Receiver Amplifier With Carrier Detect
MOTOROLA
5-12
MECLData
DL122-Rev6
MC68194
SECTIONS
CLOCK RECOVERY
5.1 OVERVIEW
The clock recovery circuitry is a key part of the receive
function providing RX clock, a 2 times (2X) RX clock, and a 4
times (4X) RX clock for data recovery and to send receive
symbols to the MAC. Figure 5-1 is a simplified functional
schematic of the clock recovery logic. The clock recovery is
fed by the output stage of the receive amplifier. The
phase-coherent signal contains frequency components equal
to lX and 2X the serial data rate. Figure 5-2 shows an
example of timing for a 5 Mb/s serial data rate. The RXOUT
signal drives a one-shot with a time period of 75% of 1/2 bit
time; this locks out edges caused by the higher frequency
component. The one-shot is non-retriggerable and is
triggered on both positive and negative going edges. This
produces a pulse for every edge of the lower frequency.
The output of the one-shot is divided by 2 to produce a 50%
duty cycle signal equal in frequency to the lower frequency of
the phase-coherent signal. In turn, the +2 flip-flop output
runs through a multiplexer to a phase-locked loop (PLL)
system. The multiplexer selects the RXOUT signal when
carrier detect is present; otherwise the local oscillator divided
by 4 is selected.
The PLL system consists of a digital phase detector, an
active loop filter, a voltage-controlled multivibrator (VCM),
and a divide-by-4 feedback counter. When in phase lock, the
output of the divide-by-4 feedback counter is locked to the
reference clock. In turn, the VCM 4 times clock is also aligned
with the reference clock as shown in Figure 5-2.
The 4 times clock from the VCM, the 2 times clock, and the
1 times clock are all in phase (when the PLL is phase-locked)
with the reference clock, and are used to do data recovery.
Note that the reference clock can be 180 0 out of phase with the
bit time boundaries (Figure 5-2). This does not affect the 2X
and 4X clocks which are used to sample the data. However,
RXCLK can be out of sync with the bit time boundaries and
special circuitry in the data recovery logic detects and corrects
this condition.
When no valid input signal is available from the receive
amplifier (carrier detect is not asserted), the multiplexer
selects the local clock as a reference. This has the advantages
of:
1. Supply a RXCLK when no data is present.
2. Holding the PLL in frequency lock so that only
phase-lock must be achieved when switching to the
RX signal.
3. Providing a smooth transition for RXCLK when moving
from the local oscillator (at the beginning of a frame)
and vice versa (at the end of a frame). The PLL acts as
an integrator.
The IEEE 802.4 provides a PAD-IDLE or training signal at
the beginning of any transmission. The PAD-IDLE for
phase-coherent FSK is an alternating one and zero pattern,
and the PLL is capable of being locked-in well within the 24
bit times (3 octets). The design goal is to be locked-in within
12-16 bit times. Data recovered during this lockup time at the
MECLData
DL122-Rev6
I
I
I
I
I
I
SELECT
LOCAL
OSC + 4
RXOUT
CBM
,--_ _ _ 2X CLOCK
<1-_-_
4X CLOCK
I
I
I
L
RPW
Figure 5-1. Clock Recovery Logic
beginning of a transmission can be invalid because the PLL
clocks are not sync'ed. As a result the data recovery logic
forces silence for 17-18 bit times after the carrier detect
switches the reference clock (via the multiplexer) at the
beginning of a received transmission.
5.2 ONE-SHOT
As previously stated, the one-shot is used to lock out the
transitions due to the higher frequency component of the
phase-coherent signal. The one-shot is non-retriggerable
and fires off both edges of the incoming RXOUT signal. The
time period should be set to 75% of half the bit time. As an
example, the 5 Mb/s data rate has a 200 nsec bit time and the
one-shot period then has a period of 75 nsec.
NDPAIR
'1'
~nM~1
1/2
RXOUT
75% OF 1!2.:::;:j-\
BITTIME
ONE-5HOT
'0'
"1"
'O'~
I I
I
I-
I
REF CLK (+2)
(SEE NOTE BELOW)
VCM (IN LOCK)
(4X BIT RATE)
I
NOTE: Ref clock can also be 180' out of phase with bit time.
Figure 5-2. Clock Recovery Timing Signals
5-13
MOTOROLA
MC68194
Figure 5-3 shows the arrangement of the external timing
capacitor and resistor. The internal resistor RINT may be used
with or without an external resistor. A test pin is also provided
(SET-PW) to monitor the pulse width.
For 5 Mbps operation, typically RPW = 1.5 k.Q and CPW
= 33pF.
t-----t-:-<>--i~V
I' CEXT
CBM
1
I
_ _ l_RINT:O':'
_J
ONLY
FOR
TEST
The phase detector produces a voltage proportional to the
phase difference between 0i(S) and 00(s)/4. This voltage
after filtering is used as the control signal for the VCM. The PO
has pump-up UP· and pump-down DOWN" outputs with a
typical 800 mV logic swing. UP· produces a low level pulse
equal in width to the amount of time the positive edge of 0i
(REF CLOCK) leads the positive edge of 00/4 (VCM/4).
DOWN· produces a low level pulse equal in width to the
amount of time the positive edge of 0i lags 00/4. Both pulses
will not occur on the same clock cycle as 00/4 must either lead
or lag 0i when the PLL is out of lock. When in-lock, both
outputs produce a very narrow pulse or negative spike.
The gain of the phase detector is equal to (reference
Motorola app note AN532A):
Kp = (Logic swing)/21t = 800 mV/21t = 0.127 V/radian
Rpw
SET-PW
(TP)
NEEDED [
5.3.1 Phase Detector (PO)
5.3.2 Voltage Controlled Multivibrator (VCM)
The operating frequency range of the VCM is determined by
the capaCitor tied to pins VCM-C1 and VCM-C2. The
capaCitor should be selected to put the desired operating
frequency in the center of the VCM tuning range.
The transfer function of the VCM is given by:
-=
i-Pw-j
~=600mv
Ko =Kv/s
Figure 5-3. One-Shot Timing Components
where Kv is the sensitivity in radians per second per volt. Kv
is found by:
5.3 PHASE-LOCKED LOOP (PLL) COMPONENTS
The PLL consists of a digital phase detector (PO), an active
loop filter, a VCM, and a divide-by-4 feedback path. Figure
5-4 shows the fundamental elements of the PLL with their
gain constants. The basic PLL allows the output frequency f 0
to be "Iocked-on" to the input frequency fi with a fixed phase
relationship and to track it in frequency. When "in lock" the
inputs to the phase detector have zero phase error. The input
frequency is referenced to f 0/4.
A PLL follows classic servo theory and equations. In the
following discussion a working knowledge of a PLL is
assumed. For more background and applications information
on PLL, the user is directed to Motorola Application Note
AN535.
0()
i8
0 0 (8)/4
PHASE
DETECTOR
rfo/4
0 e(8)
--..:.-.
FILTER
Kf
Kp
r--
VCM
~
limit) - (Lower frequency limit)]2n:
(Control voltage tuning range)
v
= 21t (Af)ltNcx rad/sN
then
Ko = 21t (Af)/(AVCx)s radlsN
5.3.3 Loop Filter
Since a Type 2 system is required (phase coherent output,
see reference AN535), the loop transfer function of Figure 5-4
takes the form:
G(s) H(s)
=[K (s+a)] 1 s2
Writing the loop transfer function (from Figure 5-4) and
relating it to the above form:
G(s) H(s) = [KpKvKnKf] 1s = [K (s+a)] 1 s2
Ka
Having determined Kp , Ko, and that Kn = 1/4 then Kf (filter
transfer function) must take the form:
Kf = (s+a) 1s
+4
Kn
0 e(s) = ( 1 1 [ 1 + G(s) H(s)] ) 0i(S)
0 0 (s) = ( G(s) 1[ G(s) H(s)] ) 0i(S)
where:
H(s) = Kn
G(s) = Kp Kf Ko
0 0(8)
An active filter of the form shown in Figure 5-5A gives the
desired results, where:
Kf = (R2 C s+l) I R1 C s (for large A)
Kn
=11 N =1/4
Reference: Motorola App Note AN535
The active filter can also be implemented as shown in
Figure 5-58 using an alternate approach of a charge pump.
The advantage of the charge pump design is that it can be
implemented using only a single 5.0 volt supply. Its transfer
function is:
Figure 5-4. PLL Elements and Loop Equations
MOTOROLA
= [(Upper frequency
K
Kf=(RCs+1) ICs
5-14
MECLData
DL122-Rev6
MC68194
e
5.3.4 Loop Characteristics
If an active filter as shown with an op amp is used, the
up·--.-'VIIIr-.......--1
general PLL loop transfer function now becomes:
RLOWPASS
>--+--'\Nv-..- vex
G(s) H(s) = Kp Kf Ko Kn
= Kp [(R2 C s+l) 1 Rl C s1 (Kv/s) (lIN)
~eLOWPASS
Its characteristic equation is set to the form:
=1 + G(s) H(s) =0
=s2 + (Kp Kv R2) s 1 (Rl
C.E.
N) + Kp Kv) 1 (Rl C N)
Relating to the standard form (s2 + 21;0lnS + Oln2) and solving:
Figure 5-5A. Active Filter Using Op Amp
=(Kp Kv) 1 Rl C N
Oln =Natural frequency
I; =damping factor.
Oln 2
Vee
where
DN'
21;0ln
=(Kp KvR2) 1 Rl N
If a change pump loop filter is used, the general PLL loop
transfer function alternately becomes:
G(s) H(s) = Kp Kf Ko Kn
= Kp[(R C s+ 1) 1 C s1 (Kv 1 s) (lIN)
Its characteristics equation is set to the form:
C.E. = 1 + (Gs) (Hs) = 0
s2 + (Kp Kv R) s 1 (N) + (Kp Kv) 1 (C N)
=
vex
Relating to the standard form (s2 + 21;OlnS + Oln 2) and solving:
Figure 5--58. Charge Pump/Filter
Oln2 = (Kp Kv) 1 C N 21;0ln = (Kp Kv R) 1 N
SECTION 6
DATA RECOVERY
6.1 OVERVIEW
1/4, 1/2, and 314 bit time positions. A NON-DATA symbol has
I- BIT TIME-+!
The RXOUT signal from the receive amplifier and clocks
generated by the clock recovery logic are used by the data
recovery logic. The MC68194 recovers the data from the
encoded receive signal by opening sampling windows around
the 114 and 3/4 bit time positions and looking for edges in the
received signal (refer to Figure 6-1 for the encoded data
representations). A data ONE has transitions only althe 0 and
1/2 bit time positions. A data ZERO has transitions at the 0,
MECLData
DL122-Rev6
I 10.51 I
00.250.75
I ONE
ZERO
ND1
ND2
Figure 6-1. Encoded Data Representation
5-15
MOTOROLA
MC68194
transitions at the 0, 1/4, and 1/2 bit time positions (ND1) or at
the 0, 1/2, and 3/4 bit time positions (ND2). NON-DATA
symbols should always occur in pairs; each pair is made up of
one of each type of NON-DATA encoded symbols as shown
in Figure 6-2 (ND1 followed by ND2).
ONEs, ZEROs, and NON-DATA pairs can be easily
decoded by keeping track of the 1/4 and 3/4 bit time position
transitions. The ONEs, ZEROs, and NON-DATA pairs are
then reported on the RXSYMX pins as described in the serial
interface discussion. Two other conditions can also be
reported while receiving in MAC mode - BAD SIGNAL and
SILENCE. BAD SIGNAL is reported when a ND1 symbol is not
followed immediately by a ND2 symbol or when a ND2 symbol
is received and not immediately preceded by a ND1 symbol.
SILENCE is reported when one of four conditions occurs:
1.
2.
3.
4.
G
PAD-IDLE
SEQUENCE
BITTIME
CLOCK IN
PHASE
BITTIME
CLOCK1BO°
OUT OF
PHASE
The PAD-IDLE at the beginning of a transmission is used
as a training signal as described in the clock recovery section.
After the PLL has achieved lock, the recovered clock at this
point may be in phase or 1800 out of phase with the bit time
clock at the sending end. This creates a problem for RXCLK
and the data recovery logic because symbols would be
decoded as the wrong combination of 112 bit time transitions.
Logic in the data recovery circuitry corrects forthis situation.
If the clock is 1800 out of phase, the PAD-IDLE sequence
(ONE, ZERO, ONE, ZERO, ONE, ... ) will be decoded as a
sequence of NON-DATA symbols. Refer to Figure 6-2. In
normal data reception, NON-DATA symbols occur only in
pairs; there are never three or more in a row. Therefore, three
or more NON-DATA symbols occurring in a row indicate that
the bit time clock is 1800 out of phase and the bit time clock
MOTOROLA
ND2
ONE
ND1
ZERO
ND2
BIT TIME
H
I ND21 ND1 I ND21
ND1
IZEROI ONE IZEROI ONE IZEROI
NON DATA INDICATOR
When in internalloopback mode and SILENCE is being
requested on the TXSYMX pins, SILENCE will be
reported on the RXSYMX pins. An internal digital
carrier detect is used during loopback and this signal is
negated when SILENCE is requested on the request
channel.
During end--
0
w
4
V
/
'"~
u.
~
200
.r
--.-./
o
100
200
300
400
CAPpF
Figure 9-3. One Shot Pulse Width versus RextlCext
1
3
2
4
6
VCX(VOLTS)
Figure 9-4. VCM Frequency versus Control Voltage
(VCC 5.0 Vdc & C 68 pF)
=
1000
=
24
23
\
:;;- 22
100
E
'"
21
:c
en
w
19
:c
18
~
\
\
9 20
0
10
'"
4.6Vdc
3.6 VdC
I-
" r-....
17
2.6 Vdc
1
1
10
100
16
1000
20
40
CAPACITANCE (pF)
60
-r--- ~
-r--
80 100 120 140 160 180 200 220
RESISTOR (Kohm)
Figure 9-6. Detected Threshold versus Threshold Resistor
Figure 9-5. VCM Frequency versus Capacitance
800
600
E
400
200
o
/
o
V
L
2
/
3
TIMING CAP (IlF)
Figure 9-7. Jabber Time Constant versus Capacitance
MOTOROLA
5-24
MECLDala
DL122-Rev6
MECL Data
Ordering Dnfoli"mataolm
MECLData
DL122-Rev6
6-1
MOTOROLA
[§J
Device Nomenclatures
MECL Family
Device Nomenclatures
MEeL 10K, MEeL 10HI100H
Me
Motorola
Circuit Identifier
~
T
xxx
yy
-r:
Temperature Range
• 10 = 10K (-30 to +85°C)
• 10H = 10H (0 to +75°C)
• 100H 100K Compatible (0 to +85°C)
Package Type
• P for Plastic
• L for Ceramic
• FN forPLCC
Function Type
=
MEeL III
Me
Motorola
Circuit Identifier
~
XXXX
Y
-r:
Package Type
• P for Plastic
• L for Ceramic
• 0 for Narrow SOIC
• FNforPLCC
Function Type
MOTOROLA
&-2
MECLData
DL122-Rev6
Case Outlines
Case Outlines
A letter suffix to the MECL logic function part number is used to specify the package style (see drawings below). See
appropriate selector guide for specific packaging available for a given device type.
a-Pin Package
DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
ISSUEM
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 19B2.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE 0 DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIU
A
=-7.5f~~
B
C
0
F
G
J
K
M
1$1 0.25 (0.010)®1 TI B ®I A®I
P
R
MILLIMETERS
MIN
MAX
4.80
5.00
360
4.00
1.35
1.75
0.35
0.49
0.40
1.25
127BSC
Q18
0.25
0.10
0.25
0'
7"
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.180 ~196
0.150 0.157
0.054 0.068
0.014 0019
0016 0049
O.050BSC
0.009
0.009
0.007
0004
0'
0229
0.010
7'
0.244
0.019
14-Pin Packages
LSUFFIX
CERAMIC PACKAGE
CASE 632-{)B
ISSUEY
I-
f::::::: L~
~
~I
~Fi
JL
R Ull~A ~
JBjL~' ~
Fjt -- G~ N
DN~
1$10.25(0.010)@ITI A® I
MECLData
DL122 -
Rev 6
/,
.j
JN~
M
1$10.25(0,010)@ITI B@I
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,1982.
2. CONTROWNG DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALUEL
4. DIMESKION F MAY NARROW TO 0.76 (0.000)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A
B
C
D
F
G
J
K
L
M
H
INCHES
MIN
MAX
0.750 0.785
0.245 0.280
0.155 0.200
0.015 0.020
0.055 0.065
O.I00BSC
0.008 0.015
0.125 0.170
0.300BSC
15'
0'
0.020 0.040
MILLIMETERS
MIN
MAX
19.05 19.94
6.23
7.11
5.OS
3.94
0.39
0.50
1.40
1.65
2.S4BSC
0.21
0.38
3.18
4.31
7.62BSC
0'
15'
1.01
051
MOTOROLA
Case Outlines
14-Pin Packages
(continued)
PSUFFIX
PLASTIC PACKAGE
CASE 646-06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSmON AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION l TO CENTER OF LEADS WHEN
FORMED PARALLEl.
3. DIMENSION B DOES NOT INCLUDE MOLD
FlASH.
4. ROUNDED CORNERS OPTIONAL
~-r
I.~~
J.
A
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715 o.no
0.240 0.260
0.145 0.165
0.015 0.021
0.040 0.070
D.1DOBSC
0.052 0.095
0.008 0.015
0.115 0.135
0.300 BOO
10°
0°
O.ot5 0.039
MILLIMETERS
MIN
MAX
18.16 19.56
6.10
6.60
3.69
4.69
0.53
0.38
1.02
1.78
2.54 BOO
1.32
2.41
0.20
0.38
2.92
3.43
7.62BSC
0°
0"
0.39
1.01
16-Pin Packages
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620-10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSIY14.5M.1982.
2. CONTRQLUNG DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
IS
II
/I
fjUL
M
~J~1¥8~P~L~__~~,-~~
i$io.25(O.010)@iriB ®i
i$iO.25(O.010)@iriA ®i
MOTOROLA
6-4
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.760 0.785
0.240 0.295
0.200
0.Q15
0.020
0.050 BOO
0.055
0.065
0.1008SC
0.008 0.015
0.125 0.170
0.3OOOOC
15°
0°
0.020 0.040
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
508
0.39
0.50
1.27BSC
1.40
1.65
2.548SC
0.21
0.38
3.18
4.31
7.82BSC
15°
0°
0.51
1.01
MECLData
DL122 - Rev 6
Case Outlines
i6-Pin Packages
(continued)
PSUFFIX
PLASTIC DIP PACKAGE
CASE 648-08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0270
0.145 0175
0.015
0.021
0040
0.70
0.100BSC
0050 BSC
0008 0.015
0.110
0.295
0"
0020
0.130
0.305
10"
0.040
MILUMETERS
MIN
MAX
1955
685
369
4.44
0.53
039
1.02
1.77
lB.80
6.35
254BSC
t 27BSC
0.21
0.38
2.80
3.30
7.50
7.74
0"
10"
0.51
1.01
o SUFFIX
PLASTIC SOIC PACKAGE
CASE 7518-05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,19B2.
2. CONTROLLING DIMENSION: MilliMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.0061
PER SlOE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAM BAR
PROTRUSION SHALL BE 0.127 (0.0051 TOTAL
IN EXCESS OFTHE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
l±l S~'rl~~
DIM
A
B
C
D
F
~Dt::::lt::::lt::::lt::::lt::::lCld~
-j-l- - - - - -n
D
G
J
K
M
P
R
16PL
1$1 O.25(O.010)@ITIB ®I A®I
MECLData
DL122-Rev6
6-5
MILLIMETERS
MIN
MAX
9.80 1000
3.80
400
1.35
1.75
0.49
035
0.40
1.25
127BSC
0.19
0.25
0.10
0.25
0'
7"
5.80
6.20
025
0.50
INCHES
MIN
MAX
0.386
0.393
0.150 0.157
0054 0.068
0.019
0014
0.016 0049
o050 BSC
0.008
0.009
0.004 0.009
0"
7"
0.229
0.244
0010 0.019
MOTOROLA
Case Outlines
20-Pin Packages
LSUFFIX
CERAMIC DIP PACKAGE
CASE 732-(}3
ISSUE E
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PlANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND 8 INCLUDE MENISCUS.
-A~
~
20
11
,
DIM
A
8
c
C
D
F
G
H
J
INCHES
MIN
MAX
0.940 0.990
0.260 0.295
0.150 0.200
0.015 0.022
0.055
0.065
0.loo8SC
0.020
0.050
O.
0.012
0.125 0.160
0.3OO88C
K
L
M
0°
15°
N
0.010
0.040
PSUFFIX
PLASTIC DIP PACKAGE
CASE 738-03
ISSUE E
NOTES:
1. DIMENSIONING AND TOlERANCING PER ANSI
YI4.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION l TO CENTER OF lEAD WHEN
FORMED PARAllEL
4. DIMENSION 8 DOES NOT INCLUDE MOLD
FLASH.
DIM
A
8
C
D
E
G
J
K
L
M
N
MOTOROLA
6-6
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.190
0.015 0.022
O.05OBSC
O.I0088C
0.008
.015
0.110 0.140
O.30088C
IS'
0'
0.020 0.040
MILUMETERS
MIN
MAX
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.2788C
.2
1
2.54 88C
0.21
0.38
2.80
3.55
7.628SC
IS'
0'
0.51
1.01
2566
MECLDala
DL122-Rev6
Case Outlines
20-Pin Packages
(continued)
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775-Q2
ISSUEC
61$1 0.007(0.180)@l r l L-M® 1N®I
u 1$1 0.007(0.180)@lrl L-M® 1N®I
G11$1 0.010 (0.250)®1 rl L-M® 1N®I
VIEWD-D
\ 4 - - - - - t - A 1$1 0.007(0.180)@lrl
L-M® 1N®I
i1<---""""'I-R 1$1 0.007(0.180)@lrl
L-M®I N®I
~
*
HI$10.007(0.180)@lrIL-M®IN®1
K1
K
' J I- FI$10.007(0.180)@l r IL-M®IN®1
VIEWS
NOTES:
1. DATUMS -L-. -M-, AND -N- DETERMINED
WHERE TOP OF lEAD SHOULDER EXITS PlASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION Gl, TRUE POSITiON TO BE
MEASURED AT DATUM -T-, SEATING PlANE.
3. DIMENSIONS RAND U DO NOT INCLUDE MOLD
FlASH. AllOWABLE MOLD FlASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOlERANCING PER ANSI
Y14.5M,1982.
5. CONTROUJNG DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMAllER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS RAND U ARE DmRMINED AT THE
OUTERMOST EXTREMES OF THE PlASTIC BODY
EXCLUSIVE OF MOLD FlASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAO FlASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PlASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHAll NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHAll NOT CAUSE
THE H DIMENSION TO BE SMAllER THAN 0.025
(0.635).
MECLDala
Dl122-Rev6
6-7
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
Gl
Kl
INCHES
MIN
MAX
0.385
0.395
0.385 0.395
0.165
0.180
0.090
0.110
0.013 0.019
O.050BSC
0026
0.032
0020
0.025
0.350
0.356
0.350
0.356
0.042
0.048
0.042 0.048
0042 0.058
0.020
2"
10"
0.310
0330
0.040
-
MIlliMETERS
MIN
MAX
9.78 10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27BSC
0.66
0.81
0.51
0.64
9.04
889
BB9
9.04
1.07
1.21
1.07
1.21
1.07
1.42
0.50
10"
2"
7.88
B.38
1.02
-
MOTOROLA
Case Outlines
24-Pin Packages
LSUFFIX
CERAMIC DIP PACKAGE
CASE 758--Q2
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M.1982.
2. CONTROLUNG DIMENSION: INCH.
3. DIMENSION L TO CEtlTER OF lEADS WHEN
FORMED PARALLEl.
INCHES
MIN
MAX
1.240 1285
0.285 0.305
0.160
0.200
0.015 0.021
0.045 0.082
O.100BSC
0.008 0.013
0.100 0.165
0.300 0.310
0.020 0.050
0.360 0.400
DIM
A
B
C
D
F
G
J
K
L
N
P
MILLIMETeRS
MIN
MAX
31.50 32.64
7.24
7.75
4.07
5.08
0.38
0.53
1.14
1.57
2.54BSC
0.33
0.20
2.54
4.19
7.87
7.82
0.51
1.27
9.14
10.16
PSUFFIX
PLASTIC DIP PACKAGE
CASE 724-03
ISSUED
NOTES:
1. CHAMFERED COtlTOUR OPTIONAL
2. DIMENSION L TO CENTER OF lEADS WHEN
FORMED PARALLEl.
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.I982.
4. COtITROlLING DIMENSION: INCH.
~c JE\-~,
~rG jG~ E~~IIL ---;1-i -JLJ 24~ '~M
~CD 24PL
1$1 o.2S(o.o10)®lrl A ®I
MOTOROLA
rCl$"I-o.-2S-(O-.Ol-0)"",,®,-rI-'rl-B-::®"'I
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.230 1.265
0.250 0.270
0.145 0.175
0.015 0.020
0.0508SC
0.040 0.060
0.100BSC
0.007 0.012
0.110 0.140
0.300BSC
0'
IS'
0.020 0.040
MILLIMETeRS
MIN
MAX
31.25 32.13
6.35
6.85
3.69
4.44
0.38
0.51
1.27BSC
1.02
1.52
2.54BSC
0.18
0.30
2.80
3.55
7.62BSC
0'
IS'
0.51
1.01
MECLData
DL122-Rev6
Case Outlines
28-Pin Package
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776-02
ISSUE D
BI$I 0.007(0.180)@ITI L-M® 1N®I
YBRK
u 1$1 0.007 (0.180)@ITI L-M® 1N®I
f±l
1
"lI-----=----1I:~
~t-t
G11$1 0.010(0.250)®ITI L-M® 1N ®I
0
VIEWD-D
1------~AI$10.007(0.180)@ITIL-M®IN®1
i+<-------".j-f- RI$10.oo7(0.180)@ITI L-M® 1N®I
rtE~~J~
K
~
VIEWS
1$1 0.010 (0.250)®1 TI L-M® 1N ®I
NOTES:
1. DATIJMS -L-. -M-. AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARIlNG LINE.
2. DIMENSION Gl. TRUE POSITION TO BE
MEASURED AT DATIJM-T-. SEAT1NG PLANE.
3. DIMENSIONS R AND U 00 NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
•. DIMENSIONING AND TOLERANCING PER
ANSI Yl'.5M. 1982.
S. CONTROlliNG DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FlASH. TIE BAR
BURRS. GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAM BAR
PROTRUSION(S) SHAll NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHAll
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MECLData
DL122 - Rev 6
I--FI$10.007(0.180)@ITIL-M®IN®1
6--9
H
J
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
O.05085C
0.026 0032
0.020
K
R
0.025
0450
U
V
W
X
Y
Z
0.450
0.042
0.042
0.042
DIM
A
B
C
E
F
G
Gl
Kl
2'
0.410
0.040
0.456
0.458
0.048
0.046
0.056
0.020
10'
0.430
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27BSC
0.66
0.81
0.51
0.64
11.43 11.58
11.43
11.58
1.07
1.21
1.21
1.07
1.07
1.42
0.50
2'
10'
10.42 10.92
1.02
MOTOROLA
MECL Logic Surface Mount
MECL Logic Surface Mount
WHY SURFACE MOUNT?
Surface Mount Technology is now being utilized to offer
answers to many problems that have been created in the use
of insertion technology.
Limitations have been reached with insertion packages and
PC board technology. Surface Mount Technology offers the
opportunity to continue to advance the State-of-the-Art
designs that cannot be accomplished with Insertion
Technology.
Surface Mount Packages allow more optimum device
performance with the smaller Surface Mount configuration.
Internal lead lengths, parasitic capacitance and inductance
that placed limitations on chip performance have been
reduced.
The lower profile of Surface Mount Packages allows more
boards to be utilized in a given amount of space. They are
stacked closer together and utilize less total volume than
insertion populated PC boards.
Printed circuit costs are lowered with the reduction of the
number of board layers required. The elimination or reduction
of the number of plated through holes in the board, contribute
significantly to lower PC board prices.
Surface Mount assembly does not require the preparation
of components that are common on insertion technology lines.
Surface Mount components are sent directly to the assembly
line, eliminating an intermediate step.
Automatic placement equipment is available that can place
Surface Mount components at the rate of a few thousand per
hour to hundreds of thousands of components per hour. .
Surface Mount Technology is cost effective, allowing the
manufacturer the opportunity to produce smaller units and
offer increased functions with the same size product.
RS-4B1A specification. The antistatic embossed tape
provides a secure cavity sealed with a peel-back cover tape.
GENERAL INFORMATION
MECHANICAL POLARIZATION
TYPICAL
VIEW
FROM
TAPE
SIDE
•
LINEAR DIRECTION
OFTRAVEL
ORDERING INFORMATION
=
• Minimum Lot Size/Device Type 3000 Pieces.
• No Partial Reel Counts Available.
• To order devices which are to be delivered in Tape and
Reel, add the appropriate suffix to the device number
being ordered.
EXAMPLE:
MECL AVAILABILITY IN SURFACE MOUNT
Motorola is now offering MECL 10K and MECL 10H in the
PLCC (Plastic Leaded Chip Carrier) packages.
MECL in PLCC may be ordered in conventional plastic rails
or on Tape and Reel. Refer to the Tape and Reel section for
ordering details.
13 inch (330 mm) Suffix: R2
16mm
1000
• Reel Size
• TapeWidth
• Units/Reel
ORDERING CODE
SHIPMENT METHOD
MC10l01FN
MCl 01 01 FNR2
MC10Hl01FN
MC10Hl01FNR2
MC12015D
MC12015DR2
Magazines (Rails)
13 inch Tape and Reel
Magazines (Rails)
13 inch Tape and Reel
Magazines (Rails)
13 inch Tape and Reel
TAPE AND REEL
DUAL-IN-LINE PACKAGE TO
PLCC PIN CONVERSION DATA
Motorola has now added the convenience of Tape and Reel
packaging for our growing family of standard Integrated Circuit
products. The packaging fully conforms to the latest EIA
The following tables give the equivalent 110 pinouts of
Dual-In-Line (OIL) packages and Plastic Leaded Chip Carrier
(PLCC) packages.
MOTOROLA
6-10
MECLData
DL122-Rev6
Pin Conversion Tables
Pin Conversion Tables
8-Pin OIL to 20-Pin PLCC
8PIN OIL
20 PIN PLCC
14-Pin OIL to 2D-Pin PLCC
14PIN OIL
20 PIN PLCC
16-Pin OIL to 20-Pin PLCC
16 PIN OIL
20 PIN PLCC
2D-Pin OIL to 20-Pin PLCC
20 PIN OIL
20 PIN PLCC
24-Pin OIL to 28-Pln PLCC
24 PIN OIL
28 PIN PLCC
MECLOata
OL122-Rev6
6-11
MOTOROLA
MOTOROLA AUTHORIZED DISTRIBUTOR & WORLDWIDE SALES OFFICES
NORTH AMERICAN DISTRIBUTORS
FAI ......................... (408)434-0369
Future Electronics ............ (408)434-1122
UNITED STATES
ALABAMA
Huntsville
Santa Clara
Arrow/Schweber Electronics ... (205)837-6955
FAI ......................... (205)837-9209
Future Electronics. . . . . . . . . . .. (205)830-2322
HamiltonIHalimark ........... (205)837-8700
Newark ..................... (205)837-9091
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (205)830-1119
ARIZONA
Phoenix
Scottsdale
Alliance Electronics .......... (602)483-9400
Arrow/Schweber Electronics ... (602)431-0030
Newark ..................... (602)966-6340
PENSTOCK ................. (602)967-1620
Time Electronics .....•..... 1-800-789-TIME
Thousand Oaks
Torrance
Time Electronics ........... 1-800-789-TIME
Tustin
Time Electronics ..•........ 1-800-789-TIME
Woodland Hills
.
COLORADO
Lakewood
Agoura Hills
Future Electronics ............ (818)865-0040
Time Electronics Corporate .. 1-800-789-TIME
Calabassas
Arrow/Schweber Electronics . .. (818)880-9686
Wyle Electronics . . . . . . . . . . . .. (818)880-9000
Chatsworth
Time Electronics ........... 1-800-789-TIME
Denver
Newark . . . . . . . . . . . . . . . . . . . .. (303)373-4540
Arrow/Schweber Electronics ... (303)799-0258
HamiitonIHalimark ........... (303)790-1662
PENSTOCK ................. (303)799-7845
Time Electronics ........... 1-800-789-TIME
HamiitonIHalimark ........... (714)789-4100
CulverCitv
Hamilton/l'iallmark ........... (310)558-2000
Garden Grove
Newark ..................... (714-893-4909
Wyle Electronics ............. (303)457-9953
(714)587-0404
(714)753-4778
(714)453-1515
(714)753-9953
(714)863-9953
Los Angeles
Cheshire
FAI .•......•................ (203)250-1319
Future ElectroniCS. . . . . . . . . . .. (203)250-0083
Hamilton/Hallmark ........... (203)271-2844
Southbury
Wallingfort
Arrow7Schweber Electronics ... (203)265-7741
FLORIDA
Altamonte Springs
Future Electronics ............ (407)865-7900
Clearwater
FAI ... , ..................... (818)879-1234
Wyle Electronics ............. (818)880-9000
Manhattan Beach
FAI •........................ (813)530-1665
Future Electronics ............ (813)530-1222
Deerfield Beach
PENSTOCK ................. (310)548-8953
Newberry Park
PENSTOCK. . . . . . . . . . . . . . . .. (805)375-8680
Palo Alto
Newark ..................... (415)812-e300
Riverside
Newark ..................... (909)784-1101
Rocklin
HamiitonlHalimark ........... (916)632-4500
Sacramento
Arrow/Schweber Electronics . .. (305)429-8200
Wyle Electronics ............. (305)420-0500
San Diego
(619)565-4800
(619)623-2888
(619)625-2800
(619)571-7540
(619)453-8211
(619)623-9100
(619)585-9171
San Jose
Arrow/Schweber Electronics ... (408)441-9700
Arrow/Schweber Electronics . .. (408)428-8400
Norcross
Future Electronics ............
Newark . . . . . . . . . . . . . . . . . . . ..
PENSTOCK. . . . . . . . . . . . . . . ..
Wyle Electronics .............
(770)441-7676
(770)448-1300
(770)734-9990
(770)441-9045
IDAHO
Boise
FAI . . . . . . . . . . . . . . . . . . . . . . . .. (208)378-8080
ILLINOIS
Addison
Bensenville
Hamilton/Hallmark ........... (708)797-7322
Chicago
FAI . . . . . . . . . . . . . . . . . . . . . . . .. (708)843-0034
Newark Electronics Corp ...... (312)784-5100
Hoffman Estates
Future Electronics . . . . . . . . . . .. (708)882-1255
Itasca
Arrow/Schweber Electronics ... (708)250-0500
Palatine
Schaumburg
INDIANA
Indianapolis
.
Arrow/Schweber Electronics ... (317)299-2071
Bailey's Electronics ........... (317)848-9958
HamillonIHailmark ........... (317)575-3500
FAI ......................... (317)489-0441
Future Electronics ............ (317)469-0447
Newark ..................... (317)259-0085
Time Electronics ........... 1-e00-789-TIME
FI.Wayne
Newark .................•... (219)484-0766
PENSTOCK ................. (219)432-1277
IOWA
Cedar Rapids
Newark . . . • . . • . . • . . . . . . . . . .. (319)393-3800
Time Electronics ........... 1-800-789-TIME
KANSAS
Kansas City
FAI . . . . . . . . . . . . . . . . . . . . . . . .. (913)381-e800
FI. Lauderdale
FAI . . . . . . . . . . . . . . . . . . . . . • . .. (305)428-9494
Future Electronics . . . . . . . . . . .. (305)438-4043
HamiitonlHalimark ........... (305)484-5482
Newark ..................... (305)486-1151
Time Electronics ........... 1-800-789-TIME
Lenexa
Arrow/Schweber Electronics .... (913)541-9542
HamiitonlHalimark ........... (913)663-7900
Olathe
PENSTOCK. . . . . . . . . . . . . . . .. (913)829-9330
Overland Park
Lake Mary
Arrow/Schweber Electronics ... (407)333-9300
FAI ......................... (916)782-7882
Newark ..................... (916)565-1760
Wyle Electronics ............. (916)63!Hi282
Arrow/Schweber Electronics ... (404)497-1300
Hamilton/Hallmark ..•........ (404)623-4400
Newark ..................... (708)310-9980
Time Electronics .•......... 1-800-789-TIME
CONNECTICUT
Bloomfield
Time Electronics ........... 1-800-789-TIME
Irvine
Duluth
PENSTOCK ................. (708)934-3700
Thornton
Newark ..................... (203)243-1731
Costa Mesa
FAI ......................... (404)447-4767
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ....•........ (404)441-9045
Wyle Laboratories . . . . . . . . . . .. (708)620-0969
FAI ......................... (303)237-1400 .
Future Electronics . . . . . . . . . . .. (303)232-2008
Englewood
CALIFORNIA
MOTOROLA
HamlltonlHalimark ........... (408)435-3500
PENSTOCK ................. (408)730-0300
Time Electronics ........... 1-800-789-TIME
Hamilton/Hallmark ........... (818)594-0404
Tempe
Arrow/Schweber Electronics ...
FAI .........................
Future Electronics ............
Hamilton/Hallmark ...........
Newark .....................
PENSTOCK .................
Wyle ElectroniCS .............
PENSTOCK ................. (818)355-8775 .
Sunnv.vale
Newark ..................... (805)449-1480
FAI ......................... (602)731-4661
Future Electronics ............ (602)968-7140
HamiitonIHalimark ............ (602)414.'lOOO
Wyle Electronics ........ . . . .. (602)804-7000
Arrow/SchweberElectronics ...
FAI .........................
Future Electronics ............
Wyle Laboratories Corporate ..
Wyle Electronics .............
Wyle Electronics ............. (408)727-2500
Sierra Madre
GEORGIA
Atlanta
LargolTampa/S1. Petersburg
HamlitonIHailmark ........... (813)547-5000
Newark ..................... (813)287-1578
Wyle Electronics ............. (813)576-3004
Time Electronics ........... 1-800-789-TIME
Future Electronics ............ (913)649-1531
Newark •.................... (913)677-0727
Time Electronics ........... 1-800-789-TIME
MARYLAND
Baltimore
FAI ......................... (410)312-0833
Columbia
Orlando
FAI ......................... (407)885-9555
Tallahassee
FAI ......................... (904)668-7772
Tampa
PENSTOCK ................. (813)247-7556
Winter Park
HamiitonIHalimark ........... (407)657-3300
PENSTOCK ................. (407)672-1114
6-12
Arrow/Schweber Electronics . .. (301 )596-7800
Future Electronics ............ (410)290-0600
HamiitonIHalimark ........... (410)720-3400
Time Electronics ........... 1-800-789-TIME
PENSTOCK ................. (410)290-3748
Wyle Electronics ............. (410)312-4844
Hanover
Newark ..................... (410)712-e922
MECLData
DL122-Rev6
AUTHORIZED DISTRIBUTORS - continued
UNITED STATES - continued
MASSACHUSETTS
Boston
Newark ..................... (516)567--4200
Arrow/Schweber Electronics ... (508)658-0900
FAI ......................... (508)779-3111
Bolton
Future Corporate ............. (508)779-3000
Burlington
PENSTOCK. . . . . . . . . . . . . . . .. (617)2211-9100
Wyle Electronics ............. (617)271-9953
Peabody
lime Electronics ........... 1-800-7811-TIME
Hamilton/Hallmark ........... (508)532-9893
Woburn
Newark ..................... (617)935-8350
MICHIGAN
Detroit
Grand Rapids
Newark ..................... (616)954-6700
Livonia
Arrow/Schweber Electronics ... (810)455-0850
Future Electronics ............ (313)261~270
Hamilton/Hallmark ........... (313)416~800
lime Electronics ........... 1-800-789-TIME
Troy
Newark . . . . . . . . . . . . . . . . . . . .. (810)583-2899
MINNESOTA
Bloomington
Wyle Electronics .............. (612)853-2280
Burnsville
PENSTOCK .................. (612)882-7630
Eden Prairie
Arrow/Schweber Electronics ... (612)941-5280
FAI ......................... (612)947-0909
Future Electronics. . . . . . . . . . .. (612)944-2200
HamiltoniHalimark ........... (612)881-2600
lime Electronics ........... 1-800-789-TIME
Minneapolis
Newark ..................... (612)331-6350
Earth City
(314)291~350
MISSOURI
SI. Louis
Arrow/Schweber Electronics ... (314)567-6888
Future Electronics ............ (314)469-6805
FAI ......................... (314)542-9922
Newark ..................... (314)453-9400
lime Electronics ........... 1-800-7811-TIME
NEW JERSEY
Bridgewater
PENSTOCK. . . . . . . . . . . . . . . .. (908)575-9490
Cherry Hill
Hamilton/Hallmark ........... (609)424-0110
East Brunswick
Newark ...•................. (908)937-6600
Fairfield
FAI ......................... (201)331-1133
Marlton
Arrow/Schweber Electronics . .. (609)596-8000
FAI ......................... (609)988-1500
Future Electronics. . . . . . . . . . .. (609)596-4080
Pinebrook
Arrow/SchweberElectronics ... (201)227-7880
Wyle Electronics ............. (201)882-8358
Parsippany
Future Electronics. . . . . . . . . . .. (201 )299-0400
Hamilton/Hallmark ........... (201)515-1641
Wayne
lime Electronics ..........• 1-800-7811-TIME
NEW MEXICO
Albu'luerque
Hamilton/Hallmark ........... (505)828-1058
Newark . . . . . . . . . . . . . . . . . . . .. (505)828-1878
PENSTOCK ................. (610)383-9536
Flo Washington
Hauppauge
Arrow/Schweber Electronics ...
Future Electronics ............
Hamilton/Hallmark ...........
PENSTOCK .................
(516)231-1000
(516)234--4000
(516)434-7400
(516)724-9580
Konkoma
Hamilton/Hallmark ........... (516)737-0600
Newark ..................... (215)654-1434
Mt. Laurel
Wyle Electronics ............. (609)4311-9110
Philadelphia
lime Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (609)4311-9110
Pittsburgh
Long Island
FAI ......................... (516)348-3700
Melville
Wyle Laboratories ............ (516)293-8446
Pittsford
Newark .........•........... (716)381--4244
Arrow/Schweber Electronics ... (412)963-6807
Newark ..................... (412)788--4790
lime Electronics ........... 1-800-789-TIME
TENNESSEE
Knoxville
Newark ..................... (615)589-6493
Rochester
FAI ......................... (313)513-0015
Future Electronics ............ (616)699-6800
Hamilton/Hallmark ...........
PENNSYLVANIA
Coatesville
NEW YORK
Bohemia
Arrow/Schweber Electronics ... (716)427-0300
Future Electronics ............ (716)387-9550
FAI ......................... (716)387-9600
HamiltoniHalimark ........... (716)272-2740
lime Electronics ........... 1-800-789-TIME
Syracuse
FAI ......................... (315)451--4405
Future Electronics ............ (315)451-2371
Newark ..................... (315)457--4873
lime Electronics ........... 1-800-789-TIME
TEXAS
Austin
Arrow/SchweberElectronics ... (512)835--4180
Future Electronics ............ (512)502-0991
FAI ........................• (512)348-6426
Hamilton/Hallmark ....•...... (512)2111-3700
Newark ..................... (512)338-0287
PENSTOCK ................. (512)348-9762
lime Electronics ........... 1-800-7811-TIME
Wyle Electronics ............. (512)833-9953
Benbrook
NORTH CAROLINA
Charlolle
PENSTOCK ................. (817)249-0442
FAI ......................... (704)548-9503
Future Electronics ............ (704)547-1107
Carollton
Arrow/SchweberElectronics ... (214)380-6464
Dallas
Raleigh
Arrow/Schweber Electronics ... (919)878-3132
FAI . . . . . . . . . . . . . . . . . . . . . . . .. (919)876-0088
Future Electronics ............ (919)790-7111
HamiitonlHalimark ........... (919)872-0712
Newark ..................... (919)781-7677
lime Electronics ........... 1-800-7811-TIME
FAI ......................... (214)231-7195
Future Electronics ............ (214)437-2437
HamiitoniHalimark ....•...... (214)553--4300
Newark ..............•...... (214)458-2528
lime Electronics .•......... 1-800-789-TIME
Wyle Electronics ............. (214)235-9953
EIPaso
OHIO
Centerville
FAI ......................... (915)577-9531
Arrow/Schweber Electronics ... (513)43~563
Flo Worth
Allied Electronics ............. (817)338-5401
Cleveland
FAI . . . . . . . . . . . . . . . . . . . . . . . .. (216)448-0061
Newark ..................... (216)391-9330
lime Electronics ........... 1-800-7811-TIME
Columbus
Newark ..................... (614)326-0352
lime Electronics ........... 1-800-789-TIME
Dayton
FAI ......................... (513)427-6090
Future Electronics ............ (513)428-0090
Hamilton/Hallmark ........... (513)439-6735
Newark ..................... (513)294-8980
lime Electronics ........... 1-800-7811-TIME
Mayfield Heights
Future Electronics . . . . . . . . . . .. (216)449-6996
Solon
Arrow/Schweber Electronics . .. (216)248-3990
HamiitoniHalimark ........... (216)498-1100
Worthington
HamiitoniHalimark ........... (614)888-3313
OKLAHOMA
Tulsa
FAI ......................... (918)492-1500
Hamilton/Hallmark ........... (918)459-6000
Newark ..................... (918)252~070
OREGON
Beaverton
Arrow/PJmac Electronics Corp..
Future Electronics ............
HamiitoniHalimark ...........
Wyle Electronics .............
Portland
(503)629-8090
(503)645-9454
(503)529-6200
(503)643-7900
FAI ......................... (503)297~020
Newark ..................... (503)297-1984
PENSTOCK. . . . . . . . . . . . . . . .. (503)648-1670
lime Electronics ........... 1-800-7811-TIME
Houston
Arrow/Schweber Electronics ... (713)647-6868
FAI ......................... (713)952-7088
Future Electronics ............ (713)785-1155
Hamilton/Hallmark ........... (713)781-6100
Newark ... . . . . . . . . . . . . . . . . .. (713)894-9334
lime Electronics ........... 1-600-789-TIME
Wyle Electronics ....... . . . . .. (713)8711-9953
Richardson
PENSTOCK ................. (214)479-9215
San Antonio
FAI ......................... (210)738-3330
UTAH
Salt Lake City
Arrow/Schweller Electronics ...
FAI .........................
Future Electronics ............
Hamilton/Hallmark ....•......
Newark .....................
Wyle Electronics .............
(801)973-6913
(801)467-9696
(801)467--4448
(801 )268-2022
(801 )261~660
(801)974-9953
West Valley City
lime Electronics ........... 1-800-7811-TIME
Wyle Electronics ............. (801 )974-9953
WASHINGTON
Bellevue
Almac Electronics Corp. ...... (206)643-9992
Newark ..................... (206)641-9800
PENSTOCK .............. '... (206)454-2371
Bothell
Future Electronics. . . • . . . . . . .. (206)4811-3400
Redmond
HamiitoniHalimark ........... (206)882-7000
lime Electronics ........... 1-800-7811-TIME
Wyle Electronics ............. (206)881-1150
Seattle
.
FAI . . . . . . . . . . . . . . . . . . . . . . . .. (206)485-6616
Wyle Electronics ............. (206)881-1150
MECLData
DL122-Rev6
EH3
MOTOROLA
AUTHORIZED DISTRIBUTORS - continued
UNITED STATES - continued
Edmonton
Ottawa
FAI ......................... (403)438-5888
Future Electronics ............ (403)438-2858
Hamilton/Hallmark ........... (800)663-5500
WISCONSIN
Brookfield
Arrow/Schweber Electronics ... (414)792-0150
Future Electronics ............ (414)879-0244
Wyle Electronics ............. (414)521-9333
Milwaukee
FAI ......................... (414)792-9778
Time ElectroniCS ........... 1-800-789-TIME
New Berlin
Hamilton/Hallmark ...•....... (414)780-7200
Wauwatosa
Newark ..................... (414)453-9100
CANADA
ALBERTA
Calgary
Electro Sonic Inc. ........... (403)255-9550
FAI ......................... (403)291-5333
Arrow Electronics ............
Electro Sonic Inc .............
FAI .........................
Futuna Electronics ............
Hamilton/Hallmark ...........
Saskatchewan
Hamilton/Hallmark ........... (800)663-5500
Vancouver
Arrow Electronics ............
Electro Sonic Inc.............
FAI .........................
Future Electronics ............
HamlitonlHalimark ...........
Electro Sonic Inc. ...........
FAI .........................
Futuna Electronics ............
HamlitonlHalimark ...........
Toronto
(604)421-2333
(604)273-2911
(604)654-1050
(604)294-1166
(604)420-4101
MANITOBA
Winnipeg
(204)783-3105
(204)785-3075
(204)944-1446
(800)663-5500
Arrow Electronics ............
Electro Sonic Inc.............
FAI . . . . . . . . . . . . . . . . . . . . . . . ..
Future Electronics ............
Hamilton/Hallmark ...........
Newark ... . .. . .. . .. . .. .. ....
Future Electronics ....•....... (403)250-5550
Hamilton/Hallmark ...•....... (800)663-5500
(905)670-7769
(416)494-1666
(905)612-9888
(905)612-9200
(905)564-8060
(905)670-2888
QUEBEC
Montreal
ONTARIO
Kanata
Arrow Electronics ............
FAI .........................
Futuna Electronics ............
Hamilton/Hallmark ......•....
(514)421-7411
(514)694-8157
(514)694-7710
(514)335-1000
Quebec City
PENSTOCK ................. (613)592-6088
BRITISH COLUMBIA
(613)226-6903
(613)728-8333
(613)820-8244
(613)727-1800
(613)228-1700
Mississauga
PENSTOCK ................. (905)403-0724
Arrow Electronics ............ (418)687-4231
FAI ......................... (418)682-5775
Future Electronics ............ (418)877-6666
INTERNATIONAL DISTRIBUTORS
AUSTRALIA
AVNET VSI Electronics (Ausl) . . .. (61)2 9878-1299
VeltekAustralia Ply Ltd ..... (61)39574-9300
AUSTRIA
EBV Eleklronik .............. (43) 18941774
SEI/Elbatex GmbH ............ (43) 1 866420
Spoerle Electronic ........... (43) 1 31872700
BELGIUM
Spoerle Electronic. . . . . . . . . .. (32) 2 725 4660
EBVEleklronik ............. (32)27160010
SEI/Rodeleo B. V. ........... (32) 2 460 0560
BULGARIA
MacroGroup ................. (359) 2708140
CZECH REPUBLIC
Spoerle Electronic .............. (42) 2731355
SEI/Elbatex .................. (42) 24763707
Macro Group ................. (42) 23412182
CHINA
Advanced Electronics Ltd. . .. (852)2 305-3633
AVNET WKK Componenls LId. ... (852)2 357-8888
China EI. App. Corp. XlaMan Cc.. (86)106818-9750
Nanco Electronics Supply Lid.. (852) 2 765-3025
........................ or (852) 2 333-5121
Olng Cheng Enterprises Ltd .. (852) 2 493-4202
DENMARK
Arrow Exatec ............... (45) 44 927000
Avnet Nortec AlS ............ (45) 44 880800
EBV Eleklronik ............... (45) 39690511
ESTONIA
Arrow Field Eesll .............. (372) 6503288
Avnet Baltronic ............... (372) 6397000
FINLAND·
Arrow Field OY ............. (35) 807 775 71
Avnet NoMec OY ............. (35) 80613181
FRANCE
Arrow Electronlque ........ (33) 1 49 78 49 78
Avnet Components . . . . . . .. (33) 1 49 65 25 00
EBV Eleklronik ........... (33) 1 64 68 86 00
Future Electronics ............ (33)1 69821111
Newark .................... (33)1-30954060
SEI/Scalb ................ (33) 1 69 19 89 00
GERMANY
AvnetE2000 ............... (49)894511001
EBVEleklronikGmbH ....... (49)8999114-0
Future Electronics GmbH .... (49) 89-957 270
SEIiJermyn GmbH .......... (49) 6431-5080
Newark .................... (49)2154-70011
Saseo Semiconductor ......... (49) 89-46110
Spoerle Electronic .......... (49) 6103-304-0
MOTOROLA
GREECE
ROMANIA
EBV Eleklronik ............... (30) 13414300
HOLLAND
MacroGroup ................. (401)6343129
RUSSIA
EBV Eleklronlk ............ (31) 3465 623 53
Spoerle Electronic ............ (31) 4054 5430
SEI/Rodelco B.V........... (31) 7657 227 00
Macro Group ................ (781) 25311476
SCOTLAND
EBV Eleklronik ............ (44) 161 4993434
SINGAPORE
HONG KONG
AVNETWKK Componenls Ltd. ... (852)2357-8888
NanshingClr. &Chem. Cc. LId ... (852)2333-5121
INDIA
Canyon Products Lid ....... (91) 80 558-7758
Future Electronics ............. (65) 479-1300
Strong Pte. Lid ............... (65) 276-3996
Uraco Technologies Pta Ltd ..... (65) 545-7811
SLOVAKIA
Macro Group ................. (42)89634181
INDONESIA
P.T.Ometraco ............. (62) 21619-6166
SLOVENIA
SEI/Elbat"x ................ (48) 22 6254877
IRELAND
Arrow ..................... (353) 14595540
Future ElectroniCS ............. (353) 6541330
Macro Group ............... (353) 16766904
ITALY
AVNET EMG SRL ............. (39) 2381901
EBV Eleklronik ............... (39) 2 660961
Future Electronics. . . . . . . . . . . .. (39) 2 660941
Silverstar Ltd. SpA ........... (39) 2 661251
JAPAN
AMSC Co .. Ltd .............
Fuji Electronics Co., Ltd .....
Marubun Corponation .......
Nippon Motorola Micro Elec..
OMRON Corporation .......
Tokyo Electron Ltd..........
81-422-54-6800
81-3-3814-1411
81-3-3639-6951
81-3-3280-7300
81-3-3779-9053
81-3-5561-7254
SPAIN
Amitron Arrow .............. (34) 1 3043040
EBV Eleklronik ............. (34) 1 8043256
SEIiSeleoS.A. .............. (34) 16371011
SWEDEN
Arrow-Th:s .................. (46)8362970
Avnet Nortec AB ............ (46) 8 629 14 00
SWITZERLAND
EBV Eleklronik .............. (41) 17456161
SEllElbatexAG ............. (41)564375111
Spoerle Electronic ............ (41) 18746262
S.AFRICA
Advanced .. . .. . . .. .. . . . . . .. (27) 11 4442333
Reuthec Components ....... (27) 11 8233357
THAILAND
Shapiphat Ltd. .. (66)2221-0432 or 2221-5384
KOREA
Jung Kwang Sa . . . . . . . . . . . . .. (82)2278-5333
Lite-On Korea Ltd. ........... (82)2858-3853
Nasca Co. Ltd ........•.•.... (82)23772-6800
LATVIA
Avnet ........................ (371) 8821118
LITHUANIA
Macro Group ................. (370) 7751487
NEW ZEALAND
AVNET VSI (NZ) Ltd .. . . . . . .. (64)9636-7801
NORWAY
Arrow Tahonlc AlS ............ (47)22378440
Avnet Nortec AlS Norway ..... (47) 66 646210
TAIWAN
Avnet-MercuriesCo., Ltd •.. (886)2516-7303
Solomon Technology Corp. .. (886)2788-8989
Strong Electronics Co. Ltd ... (886)2917-9917
UNITED KINGDOM
Arrow Electronics (UK) Ltd .. (44) 1 234 270027
AvnellAcoess . . . . . . . . . . . .. (44) 1 462488500
EBV Eleklronik ........... (44) 1 628783688
Future Electronics Ltd. ..... (44) 1 753763000
Macro Group .............. (44) 1 62860600
Newark .................. (44) 1 420543333
PHILIPPINES
Alexan Commercial ......... (63) 2241-9493
POLAND
Macro Group ................ (48) 22 224337
SEI/Elbatex ................ (48) 22 6254877
Spoerle Electronic ........... (48) 22 6060447
PORTUGAL
Am~ronArrow
............... (35) 114714806
6-14
MECLData
DL122-Rev6
MOTOROLA WORLDWIDE SALES OFFICES
UNITED STATES
ALABAMA
TENNESSEE
Huntsville ........ . . . . . . . .. .. (205)464-<>800
ALASKA . ................... (800)635-8291
ARIZONA
Tempe.. .. .. .. .. .. .. .. .. .... (602)302-8056
TEXAS
Austin ...................... (512)502-2100
Houston .................... (713)251-0006
Plano .................•..... (214)516-5100
VIRGINIA
CALIFORNIA
Calabasas ..................
Irvine .......................
Los Angeles .................
San Diego ..................
Sunnyvale ..................
JAPAN
Knoxville .................... (423)584-4841
(818)878-£800
(714)753-7360
(818)875-8800
(619)541-2163
(408)749-{)510
COLORADO
Denver ..................... (303)337-3434
CONNECTICUT
Wallingford . . . . . . . . . . . . . . . . .. (203)949-4100
FLORIDA
Clearwater .................. (813)524-4177
Maitland .................... (407)628-2636
Pompano 8eachIFt. Lauderdale. . . .. (954)351-£040
GEORGIA
Atlanta ..................... (770)729-7100
IDAHO
Boise .. . .. .. .. . .. . .. .. .. .... (208)323-9413
ILLINOIS
Cbicago/Schaumburg . . . . . . . .. (847)413-2500
INDIANA
Indianapolis ......•........ " (317)571-0400
Kokomo .................... (317)455-5100
Richmond ................... (804)285-2100
UTAH
CSI Inc. .. .. .. .. .. . .. .. .. .... (801 )572-401 0
WASHINGTON
Bellevue .................... (206)454-4160
Seattle Access .............. (206)622-9960
WISCONSIN
Milwaukee/Brookfield ......... (414)792-0122
Field Applications Engineering Available
Through All Sales Offices
CANADA
Cedar Rapids. . . . . • . . . . . . . . .. (319)378-0383
Kansas City/Mission .......... (913)451-£555
MARYLAND
Columbia ................... (410)381-1570
MASSACHUSETTS
Marlborough ................. (508)357-8200
Woburn ..................... (617)932-9700
MICHIGAN
Detroit ...................... (810)347-£800
Literature ................... (800)392-2016
MINNESOTA
Minnetonka ................. (612)932-1500
MISSOURI
SI. Louis .................... (314)275-7380
NEW JERSEY
Fairfield. . . . . . . . . . .. . .. . . .. .. (201 )808-2400
NEW YORK
Fairport ..................... (716)425-4000
Fishkill ...................... (914)898-0511
Hauppauge ................. (516)361-7000
NORTH CAROLINA
Raleigh ..................... (919)870-4355
OHIO
Cleveland ................... (216)349--3100
ColumbusIWorthington ..... '" (614)431-£492
Dayton ..................... (513)438-6800
OKLAHOMA
Tulsa .. . . . . . .. . . . . . . . . . . . . .. (918)459-4565
OREGON
Portland .................... (503)641--3681
PENNSYLVANIA
Colmar ..................... (215)997-1020
Philadelphia/Horsham ........ (215)957-4100
MECLData
DL122-Rev6
KOREA
Pusan ..................... 82(51 )4635-D35
Seoul ....................... 82(2)554-5118
MALAYSIA
Penang ..................... 60(4)228-2514
MEXICO
Mexico City ................. 52(5)282-0230
Guadalajara ................. 52(36)21-8977
Zapopan Jalisco ............. 52(36)78-0750
Marketing ................... 52(36)21-2023
Customer Service ........... 52(36)669-9160
NETHERLANDS
BRITISH COLUMBIA
Vancouver .................. (604)293-7650
ONTARIO
Ottawa ..................... (613)226-3491
Toronto ..................... (416)497-8181
QUEBEC
Montreal .................... (514)333-3300
IOWA
KANSAS
Kyusyu ................... 81-92-725-7583
Gotanda .................. 81--3-£487-8311
Nagoya ................... 81-£2-232--3500
Osaka ..................... 81-£--305-1801
Sendai ................... 81-22-269-4333
Takamatsu ................ 81-878--37-9972
Tokyo .................... 81--3--3440--3311
Best ....................... (31)499861211
PHILIPPINES
Manila . . . . . . . . . . . . . . . . . . . .. (63)2 822-0625
PUERTO RICO
San Juan ................... (809)282-2300
SiNGAPORE .................. (65)4818188
SPAIN
Madrid ...................... 34(1 )457-8204
or .......................... 34(1)457-8254
SWEDEN
Solna ....................... 46(8)734-8800
INTERNATIONAL
SWITZERLAND
AUSTRALIA
Melbourne ................. (61--3)98870711
Sydney .................... (61-2)99661071
BRAZIL
Geneva .................... 41(22)7991111
Zurich ...................... 41(1)730-4074
TAIWAN
Taipei ..................... 886(2)717-7089
Sao Paulo ................. 55(11)815-4200
CHINA
THAILAND
Bangkok . . . . . . . . . . . . . . . . . . .. 66(2)254-4910
Beijing. . . . . . . . . . . . . . . . . . .. 86-10-£8437222
Guangzhou ............... 86-20-87537888
Shanghai ................. 86-21-£3747688
lianjin .. .. .. .. .. .. .. .. .. ... 86-22-5325072
UNITED KINGDOM
Aylesbury ................. 44 1 (296)395252
DENMARK
Denmark ..................... (45) 43488393
FINLAND
Helsinki ................... 358-0--35161191
carphone ................... 358(49)211501
FULL LINE REPRESENTATIVES
CALIFORNIA, Loomis
Galena Technology Group ..... (916)652-0268
NEVADA, Reno
FRANCE
Paris ........................ 33134 635900
Galena Tech. Group .......... (702)746-0642
NEW MEXICO, Albuquerque
GERMANY
LangenhagenlHanover ....... 49(511)786880
Munich ..................... 498992103-0
Nuremberg ................. 4991196--3190
Sindelfingen ................. 497031 79710
Wiesbaden .. .. .. .. .. .. .. .... 49611 973050
S&S Technologies, Inc........ (505)414-1100
UTAH, Salt Lake City
Utah Camp. Sales, Inc........ (801)572-4010
WASHINGTON, Spokane
Doug Kenley ................ (509)924-2322
HONG KONG
Kwai Fang ................ 852-2-£10-£888
Tai Po .................... 852-2-£66-8333
INDIA
Bangalore .................. 91-80-5598615
ISRAEL
Herzlia ..................... 972-5-890222
ITALY
Milan .......................... 39(2)82201
6-15
HYBRID/MCM COMPONENT SUPPLIERS
Chip Supply .................
Elmo Semiconductor .........
Minco Technology Labs Inc....
Semi Dice Inc ................
(407)298-7100
(818)768-7400
(512)834-2022
(310)594-4631
MOTOROLA
MOTOROLA
6-16
MECLData
DL122 - Rev 6
®
MOTOROLA
How to reach us:
USA/ EUROPE / Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 3O:Hl7~2140 or 1--800-441-2447
JAPAN: Nippon Motorola Ltd.; Tatsumt-SPD-JLDC, 6F Seibu-8utsuryu-{;enter,
3-14-2 Tatsumi Koto--Ku , Tokyo 135, Japan. 81-3-3521-8315
Mfa.'": RMFAXO@email.sps.mot.com - TOUCHTONE 602-244--<;609
INTERNET: htlp:IIDesign-NET.com
ASIA/PACIAC: Motorola Semiconductors H.K. Ltd. ; 88 Tai Ping Industrial Pari<,
51 Ting Kok Road , Tai Po, N.T. , Hong Kong . 852-26629298
DL1221D
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:07:14 15:16:03-08:00 Modify Date : 2017:07:14 15:59:15-07:00 Metadata Date : 2017:07:14 15:59:15-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:fc2cc707-c343-ac41-92bc-d67dbeae5855 Instance ID : uuid:2b3a2c65-609d-6046-b85e-96b6f68d8a75 Page Layout : SinglePage Page Mode : UseNone Page Count : 476EXIF Metadata provided by EXIF.tools