1996_Motorola_Master_Selection_Guide 1996 Motorola Master Selection Guide

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SG73/D

MOTOROL.A

MOTOROLA SEMICONDUCTOR

MASTER SELECTION GUIDE

REV 10

Introduction
Semicustom Application Specific Ifl
Integrated Circuits (ASIC) L!J
Microcomputer Components

[2J

Logic: Standard, Special
and Programmable

I3l

Analog and Interface
Integrated Circuits

141

~
~

Communications, Power and Ii:l
Signal Technologies Group Products ~
Product Literature and 'E)l
Technical Training ~
Device Index and 'fl
Subject Index LLJ

MOTOROLA
Master Selection Guide

The information in this book has been carefully checked and is believed to be accurate; however, no responsibility is assumed
for inaccuracies. Furthermore, this information does not convey to the purchaser of semiconductor devices any license under the
patent rights to the manufacturer.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty.
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including ''Typicals'' must be validated for each customer application by customer's technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use
as components in systems intended for surgical implant Into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design
or manufacture of the part. Motorola and ® are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

-NOTEREV. 9 WAS PUBLISHED ELECTRONICALLY ONLY
NO BOOKS WERE PRINTED

© Motorola, Inc. 1996
Previous EdHion © 1995

"All Ri9hts Reserved"
Printed in U.S.A.

Motorola Master Selection Guide

Introduction

ALExiS, Buffalo, Bullet-Proof, BurstRAM, CDA, CMTL, Ceff-PGA, Customer Defined Array, DECAL, Designer's, DIMMIC,
DSPRAM, ECLinPS, ECLinPS LITE, ECL300, E-FETs, EpiBase, Epicap, FIRsT, GEL-PAK, GEMFET, GlobalOptoisolator,
GreenLine, HDC, HDTMOS, H4C Series, H4C Plus, HYPERformance, ICePAK, L2TMOS, MAACPAC, MCML, MDTL, MECL,
MECL 10K, MECL 10H, MECL III, MEGAHERTZ, MCCS, Media Engine, Memorist, MHTL, MicroCool, MicroSIMM, MiniMOS,
MONOMAX, MOSAIC I, MOSAIC II, MOSAIC III, MOSAIC IV, MOSAIC V, MOSFET, Mosorb, MRTL, MTTL, Multi-Pak, MUSCLE,
Mustang, IlSIMM, OACS, OnCE, PHACT, Predix, PowerBase, POWER OPTO, POWERTAP, PRISMCard, QUIL, Rail-To-Rail,
SCANSWITCH, SENSEFET, SLEEPMODE, SMARTDISCRETES, SMARTMOS, SMARTswitch, SORF,
Surmetic,
SWITCH MODE, Symmetric Superscalar, TestPAS, Thermopad, Thermopad II, Thermowatt, TMOS V, Unibloc, UNIT/PAK,
VECOMP, X-Ducer, Z-Switch and ZIP R TRIM are trademarks of Motorola, Inc.
C-QUAM, MOSAIC and TMOS are registered trademarks of Motorola, Inc.

Apollo is a registered trademark of Hewlett Packard Inc.
AutoLogic, NetEd, QuickSim II, QuickPath and Falcon Framework are trademarks of Mentor Graphics Corp.
Concept, Gate Ensemble, Verilog-XL, Veritime and Dracula are trademarks of Cadence Design Systems, Inc.
Daisy is a trademark of Daisy Systems Corporation.
DDCMP and VAX are trademarks of Digital Equipment Corporation.
Design Compiler, HDL Compiler, Test Compiler and DesignWave are trademarks of Synopsys, Inc.
Echelon, LON and NEURON are registered trademarks of Echelon Corporation.
ETHERNET is a trademark of Xerox Corporation.
FACT and FAST are trademarks of National Semiconductor Corporation.
FIDE is a trademark of Aptronix.
GED is a trademark of Valid Logic Systems Inc.
HP/Apolio is a registered trademark of Hewlett-Packard Inc.
i486 and Pentium are registered trademarks of Intel Corporation.
InterTools is a trademark of Intermetrics, Inc.
IBM, IBM PC, PowerPC and SDLC are trademarks of International Business Machines Corporation.
Isotop is a trademark of SGS-Thomson Microelectronics.
LONBuILDER, LONTALK and LONWORKS are trademarks of Echelon Corporation.
Macintosh is a trademark of Apple Computer, Inc.
Mentor Graphics is a trademark of Mentor Graphics Corporation.
Micro8 is a trademark of International Rectifier.
MOTIVE is a registered trademark of Quad Design.
NeXT is a trademark of NeXT Computer, Inc.
ROM68K and SmartROM are trademarks of Integrated Systems, Inc.
SPARC is a trademark of SPARC International, Inc.
Sun-4 is a trademarks of Sun Microsystems Inc.
Thermal Clad is a trademark of the Bergquist Company.
UNIX is a registered trademark of XlOpen Company, Ltd.

All brand names and product names appearing in this document are registered trademarks or trademarks of their
respective holders.

Introduction

Mctcrda Master Se!e~jl)n

GlJi('l~

Master Selection Guide
Where We Stand ...

How To Use This Guide . ..

Total Customer Success

This Selection guide is arranged to provide three-way
assistance to engineers and technicians in making a
first-order selection of components best suited for a specific
circuit or system design.

Service, speed and facility of response, product quality and
reliability are the goals to which we are dedicated. Our
commitment to progress such as Six Sigma performance and
Cycle lime Reduction are symbolic of a culture in which Total
Customer Success is, overwhelmingly, our primary objective.
In today's highly competitive market, selecting the most
effective semiconductor components for a given application
poses a significant challenge. The range of available functions
and the sheer number of components within each unique
product line is staggering. Add to this the number of vendors
capable of satisfying a portion of the overall system demands
and the selection of a cost-effective component complement
can be as time consuming as the design of the system itself.
This is where Motorola occupies a unique position among
semiconductor manufacturers - one that can significantly shorten
the product selection cycle. Please consider these facts:
As a manufacturer of semiconductors since the very
beginning of the technology, Motorola has emerged as a
leading supplier of such components to the world market.
Motorola's product line is the broadest in the industry,
capable of filling 75--80% of the many applications for
semiconductor devices.
In each of its various product categories, Motorola is a
recognized leader, with leading edge products as well as
commodity products for mass applications.
Motorola's vast network of sales offices and distributors,
augmented by manufacturing centers throughout the world,
not only ensures easy communications, cost-effective
pricing and rapid service, but guarantees a continuing
stream of state-of-the-art products based on world-wide
experience and demand.

Motorola Master Selection Guide

If you have a device number that needs identification or
if you want to know if Motorola manufactures a particular
device type:
1. Turn to the Device Index for a complete listing of Motorola
products, and the page numbers where more detailed
information is given for these products.
If you have a device name or acronym and wish to know
if Motorola makes such a device:
2. Look for it in the Subject Index.
If you want an overview of Motorola products for
specific product category:

a

3. Refer to the quick-reference product line guide located at
the front of this publication or use the table of contents
located at the front of each section.
Telephone ASSistance, North America Only
For literature requests or general product information, call
toll-free any weekday, 8:00 a.m. to 4:00 p.m., MST.
To order technical literature by specific document title, i.e.,
SGXXlD or DLXXXlD, or by part number only, call
1--800-441-2447
Non-North American Locations
Please contact your local Motorola Sales Office or
Authorized Distributor.

iii

Introduction

Table of Contents
Semicustom Application Specific
Integrated Circuits .......... 1.0-1
ASIC Preview ...............................
Bipolar .....................................
ECl & ETl Series Arrays ............. " ....
CMOS .....................................
1.0 Micron HDC Series
Sub-Micron H4C & H4CPlus Series. . . . . . . ..
Design Automation Software (OACSTM) .........
Advanced Packaging .........................
Architecture for the 90's CDATM
(Customer Defined Arrays) ...................
CDA- The Architecture of the '90s .........
Bipolar ECl & ETl Series Arrays .................
Third Generation ............................
ETl Series Arrays Extend Design Flexibility. ..
ETl Series Features Mixed ECl-TTl Interface
CMOS ........................................
1.0 Micron CMOS HDCTM Series ..............
Triple-layer Metal ........................
Sub-Micron CMOS H4CTM Series ....... . . . . ..
CDNM Architecture .. . . . . . . . . . . . . . . . . . . . . ..
Sub-Micron CMOS H4CPlus™ Series
Mixed 3.3 V/5.0 V levels .....................
Design Automation Software .....................
The Open Architecture CAD System™ ..........
OACSTM 2.2 and 3.1M Features ................
Advanced Packaging ...........................
Quad Flat Pack Molded Carrier Ring
(QFP-MCR) ................................
MicroCoolTM Quad Flat Pack ...................
Over-Molded Pad Array Carrier (OMPACTM) .....
Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ASIC Regional Design Centers - United States . . ..
ASIC Regional Design Centers - International . . . ..

The M68000 Family ............... 2.2-1
Microprocessors ............................... 2.2-2
Embedded Controllers .......................... 2.2-5
Integrated Processors. . . . . . . . . . . . . . . . . . . . . . . . . .. 2.2-7
Coprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.2-9
DMA Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.2-9
Network Devices ............................... 2.2-9
Data Communication Devices ...... " ........... 2.2-10
General Purpose I/O .............. " ........... 2.2-11
Fiber Distributed Data Interface ................. 2.2-11
DevelopmentTools ............................ 2.2-12
Support Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.2-12

1.1-1
1.1-1
1.1-1
1.1-1
1.1-1
1.1-1
1.1-1
1.1-1
1.1-1
1.1-2
1.1-2
1.1-2
1.1-2
1.1-3
1.1-3
1.1-3
1.1-4
1.1-4

The M88000 RISC Family ......... 2.3-1
Architecture, Performance,
and Software Compatibility . . . . . . . . . . . . . . . . . . . . .. 2.3-2
Microprocessors ............................... 2.3-2
Cache/Memory Management Units ............... 2.3-3

The PowerPC RISC Family
Microprocessors ................. 2.4-1
PowerPCTM RISC Microprocessors . . . . . . . . . . . . . . .. 2.4-2
MPC601 RISC Microprocessor. . . . . . . . . . . . . . . . . .. 2.4-2
MPC602 RISC Microprocessor . . . . . . . . . . . . . . . . . .. 2.4-3
MPC603 RISC Microprocessor. . . . . . . . . . . . . . . . . .. 2.4-3
MPC603e RISC Microprocessor. . . . . . . . . . . . . . . . .. 2.4-6
MPC604 RISC Microprocessor. . . . . . . . . . . . . . . . . .. 2.4-9
MPC604e RISC Microprocessor . . . . . . . . . . . . . . . . .. 2.4-9
MPC620 RISC Microprocessor ................. , 2.4-13
MPC105 PCI Bridge/Memory Controller .......... 2.4-15
MPC106 PCI Bridge/Memory Controller .......... 2.4-16

1.1-5
1.1-6
1.1-6
1.1-6
1.1-7
1.1-7
1.1-7
1.1-7
1.1-8
1.1-8
1.1-8

Single-Chip Microcontrollers (CSIC)

Microcomputer Components .. 2.0-1

Single-Chip Microcontrollers (AMCU) . 2.6-1
M68HC11 Family ............................... 2.6-2
Modular Microcontroller ........................ 2.6-12
The M68HC16 Family ....................... 2.6-14
The M68300 Family ......................... 2.6-19
Development Tools .. ' ......................... 2.6-23
Fuzzy logic .................................. 2.6-26
On-Line Help ................................. 2.6-26
Third-Party Support ........................... 2.6-27

Digital Signal Processors ......... 2.1-1
DSP56100 -l6-Bit Digital Signal Processors .. 2.1-2
DSP56800 -16-Bit Digital Signal Processors .. 2.1-3
DSP56000 - 24-Bit Digital Signal Processors .. 2.1-3
DSP56300 - 24-Bit Digital Signal Processors .. 2.1-6
DSP96002 - 32-Bit Digital Signal Processors ., 2.1-9
DSP56ADC16 - The Analog-To--Digital Converter 2.1-10
DSP Development Tools ........................ 2.1-10
Application Development Systems ............ 2.1-10
Graphical User Interface ..................... 2.1-12
DSP Development Software .................... 2.1-12
Design-In Software Packages . . . . . . . . . . . . . . .. 2.1-12
C-Compiler Packages ....................... 2.1-13
C-Compiler Upgrades . . . . . . . . . . . . . . . . . . . . . .. 2.1-13

'T_L..I _ _ I.

1"" __ .. __ .....

ICUJIICl VI VVlllgll~

2.5-1

M68HC05 CSIC Family ......................... 2.5--2
M68HC08 Family .............................. 2.5--13
Development Tools ........................... 2.5-14
On-Line Help ....... . . . . . . . . . . . . . . . . . . . . . . . . .. 2.5-22

LonWorks Products .............. 2.7-1
NEURON CHIPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
lONWORKS Technology Overview and Architecture ..
lONBulLDER Developer's Workbench ..............
lONWORKS Support Tools . . . . . . . . . . . . . . . . . . . . . . ..
lONWORKS Literature ........... '" " ............

!v

2.7-2
2.7-5
2.7-6
2.7-7
2.7-9

Motorola Master Selection Guide

Table of Contents
Microcomputer Components (continued)

Power Supply Circuits (continued)

Memory Products ................ 2.8-1

Voltage Regulator/Supervisory. . . . . . . . . . . . . . . .. 4.2-5
SCSI Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.2-8
Switching Regulator Control Circuits
Single-Ended ............................... 4.2-9
Single-Ended with On-Chip Power Switch ..... 4.2-11
Very High Voltage Single-Ended with
On-Chip Power Switch ..................... 4.2-11
Double-Ended ............................. 4.2-12
High Voltage Switching Regulator ............. 4.2-13
Special Switching Regulator Controllers
Dual Channel .............................. 4.2-15
Universal Microprocessor .................... 4.2-15
Power Factor ............................... 4.2-15
SuperviSOry Circuits
Overvoltage Crowbar Sensing ................ 4.2-18
Over/Undervoltage Protection ................ 4.2-18
Undervoltage Sensing ....................... 4.2-19
Universal Voltage Monitor. . . . . . . . . . . . . . . . . . .. 4.2-20
Battery Management Circuits
Battery Charger ICs ......................... 4.2-21
Battery Pack ICs . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.2-23
MOSFET/IGBT Drivers
High Speed Dual Drivers. . . . . . . . . . . . . . . . . . . .. 4.2-25
Single IGBT Driver. . . . . . . . . . . . . . . . . . . . . . . . .. 4.2-25
Package Overview ............................ 4.2-26

Fast Static RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Introduction .................................
Application Specific Static RAMs. . . . . . . . . . . . . ..
Asynchronous 6 to 15 ns 5 V Fast Static RAMs ..
Asynchronous 12 to 35 ns 5 V Fast Static RAMs.
Fast Static RAM Modules .....................
Dynamic RAMs ................................
Introduction .................................
DRAM Modules .............................
Dynamic RAMs (HCMOS) ....................

2.8-2
2.8-2
2.8-2
2.8-3
2.8-3
2.8-4
2.8-5
2.8-5
2.8-5
2.8-6

Logic: Standard, Special
and Programmable .......... 3.0-1
Motorola Logic Families: Which Is Best for You? .... 3.1-1
Motorola Programmable Arrays (MPA) ............ 3.1-5
Selection by Function
Logic Functions ............................ 3.1-13
Device Index .................................. 3.1-40
Ordering Information ........................... 3.1-49
Case Outlines ................................. 3.1-53
Packaging Information ......................... 3.1-86
Surface Mount ............................. 3.1-86
Pin Conversion Tables ....................... 3.1-86
Tape and Reel .............................. 3.1-87
Logic Literature Listing ......................... 3.1-88

Power/Motor Control Circuits ..... 4.3-1
Power Controllers .............................. 4.3-2
Zero Voltage Switches . . . . . . . . . . . . . . . . . . . . . . .. 4.3-2
Zero Voltage Controller ....................... 4.3-3
High-Side Driver Switch ...................... 4.3-4
Motor Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.3-4
Brushless DC Motor Controllers ............... 4.3-4
Closed-Loop Brushless Motor Adapter ......... 4.3-7
DC Servo Motor Controller/Driver .............. 4.3-8
Stepper Motor Driver . . . . . . . . . . . . . . . . . . . . . . . .. 4.3-9
Universal Motor Speed Controllers ............ 4.3-10
Triac Phase Angle -Controller ................ 4.3-11
Package Overview ............................ 4.3-12

Analog and Interface
Integrated Circuits .......... 4.0-1
Amplifiers and Comparators ...... 4.1-1
Operational Amplifiers ...........................
Single ......................................
Dual .......................................
Quad .......................................
High Frequency Amplifiers .......................
AGC .......................................
Miscellaneous Amplifiers ........................
Bipolar .....................................
CMOS .....................................
Comparators ...................................
Single ......................................
Dual .......................................
Quad .......................................
Package Overview .............................

4.1-2
4.1-2
4.1-3
4.1-4
4.1-5
4.1-5
4.1-6
4.1-6
4.1-6
4.1-7
4.1-7
4.1-7
4.1-7
4.1-8

Voltage References. . . . . . . . . . . . . .. 4.4-1
Precision Low Voltage References . . . . . . . . . . . . . . .. 4.4-2
Package Overview ............................. 4.4-2

Data Conversion ................. 4.5-1
Data Conversion ...............................
A-D Converters .............................
CMOS ...................................
Bipolar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Sigma-Delta .............................
D-A Converters .............................
CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Sigma-Delta .............................
Package Overview .............................

Power Supply Circuits ............ 4.2-1
Linear Voltage Regulators
Fixed Output ................................ 4.2-2
Adjustable Output. . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.2-4
Special Regulators ............................. 4.2-5

Motorola Master Selection Guide

v

4.5-2
4.5-2
4.5-2
4.5-2
4.5--2
4.5--3
4.5--3
4.5--3
4.5-4

Table of Contents

Table of Contents
Analog and Interface
Integrated Circuits (continued)

Communication Circuits (continued)
Voice Switched Speakerphone with
J.lProcessor Interface .....................
Voice Switched Speakerphone Circuit .......
Family of Speakerphone ICs ...............
Telephone Accessory Circuits
Audio Amplifier ...........................
Current Mode Switching Regulator .........
300 Baud FSK Modems ...................
ADPCM Transcoder ......................
Calling Line Identification (CLiD) Receiver ...
CVSD Modulator/Demodulator .............
Summary of Bipolar Telecommunications
Circuits ................................
Phase-Locked Loop Components ...............
PLL Frequency Synthesizers .................
Phase-Locked Loop Functions ...............
Package Overview ............................

Interface Circuits ................. 4.6-1
High Performance Decoder Driver/Sink Driver . . . . .. 4.6-3
ISO 8802-3[IEEE 802.3]1 OBASE-T Transceiver ... 4.6-3
Hex EIA-485 Transceiver with
Three-State Outputs ........................... 4.6-4
5.0 V, 200 M-BitlSec PR-IV Hard Disk
Drive Read Channel ........................... 4.6-5
Line Receivers ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
EIA Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
Line Drivers ................................... 4.6-7
EIA Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
Line Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
EIA-232-E/V.28 CMOS Drivers/Receivers ...... 4.6-8
Peripheral Drivers ........................... 4.6-8
IEEE 802.3 Transceivers. . . . . . . . . . . . . . . . . . . . .. 4.6-8
ReadlWrite Channel ............................ 4.6-8
Drive Read Channel ...... : . . . . . . . . . . . . . . . . . .. 4.6-8
CMOS Display Drivers .......................... 4.6-9
Package Overview ............................ 4.6-10

4.7-30
4.7-30
4.7-31
4.7-31
4.7-32
4.7-33
4.7-34
4.7-36
4.7-36
4.7-37
4.7-39

Consumer Electronic Circuits ..... 4.8-1
Entertainment Radio Receiver Circuits ............ 4.8-2
Entertainment Receiver RFIIF ................. 4.8-2
C-Quam® AM Stereo Decoders ... . . . . . . . . . . .. 4.8-2
Audio Amplifiers ............................. 4.8-2
Video Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.8-3
Encoders ................................... 4.8-3
TV Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.8-3
Video Capture Chip Sets. . . . . . . . . . . . . . . . . . . . .. 4.8-3
TV Picture-in-Picture ........................ 4.8-3
Comb Filters ................................ 4.8-3
Deflection .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.8-3
TV IF Circuits ............................... 4.8-3
Tuner PLL Circuits ........................... 4.8-4
Modulators ................................ ;. 4.8-4
Video Data Converters ....................... 4.8-4
Monitor Subsystem .......................... 4.8-4
Sound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.8-4
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.8-4
Circuit Descriptions and Diagrams ............. 4.8-5
Package Overview ............................ 4.8-25

Communication Circuits . ......... 4.7-1
RF Communications
Wideband IFs ............................... 4.7-2
Wideband Single Conversion Receivers ........ 4.7-2
Narrowband Single Conversion Receivers ....... 4.7-2
Narrowband Dual Conversion Receivers ........ 4.7-3
Universal Cordless Phone Subsystem IC ....... 4.7-3
Transmitters ................................ 4.7-3
Balanced Modulator/Demodulator .............. 4.7-4
Infrared Transceiver .......................... 4.7-4
Telecommunications
Subscriber Loop Interface Circuit ............. 4.7-11
PBX Architecture (Analog Transmission)
PCM Mono-Circuits ...................... 4.7-12
Dual Tone Multiple Frequency Receiver ..... 4.7-15
ISDN Voice/Data Circuits
Integrated Services Digital Network ......... 4.7-15
Second Generation U-Interface Transceiver .. 4.7-16
Second Generation SIT-Interface Transceiver 4.7-16
Dual Data Link Controller .................. 4.7-17
Voice/Data Communication (Digital Transmission) 4.7-18
Universal Digital Loop Transceiver ........... 4.7-18
ISDN Universal Digital Loop Transceiver II ... 4.7-19
Electronic Telephone Circuit .................. 4.7-19
Tone Ringers ............................... 4.7-20
Speech Networks ........................... 4.7-21
Speakerphone
Voice Switched Speakerphone Circuit ....... 4.7-25

Table of Contents

4.7-27
4.7-28
4.7-29

Automotive Electronic Circuits .... 4.9-1
Voltage Regulators ............................. 4.9-2
Electronic Ignition .............................. 4.9-2
Special Functions .............................. 4.9-3
Package Overview ........................ , ... 4.9-12

Other Analog Circuits ........... 4.10-1
liming Circuits
Singles .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Duals .....................................
Multipliers ....................................
Linear Four-Quadrant Multipliers . . . . . . . . . . . . ..
Smoke Detectors (CMOS) ......................
Package Overview ............................

vi

4.10-2
4.10-2
4.10-2
4.10-2
4.10-3
4.1 Q-4

Motorola Master Selection Guide

Table of Contents
TMOS Power MOSFETs Products .. 5.4-1

Analog and Interface
Integrated Circuits (continued)

TMOS Power MOSFETs ........................ 5.4-1
TMOS Power MOSFETs Numbering System .... 5.4-2
HDTMOSTM Power MOSFETs ................. 5.4-3
TMOS V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.4-5
SMARTDISCRETES Products ................. 5.4-7
N-Channel MOSFETs " . . . . . . . . . . . . . . . . . . . . .. 5.4-8
SO-8 MiniMOS ........................... 5.4-8
S0-8 EZFET . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.4-9
Micro8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.4-9
SOT-223 ................................ 5.4-9
DPAK .................................. 5.4-10
D2PAK ................................. 5.4-11
D3PAK ................................. 5.4-12
TO-220AB .............................. 5.4-13
TO-247 ................................. 5.4-15
TO-264 ...................... , ..... , .... 5.4-16
P-Channel MOSFETs ....................... 5.4-17
SO-8 MiniMOS .......................... 5.4-17
Micro8 .................................. 5.4-17
SOT-223 ............................... 5.4-18
DPAK .................................. 5.4-18
D2PAK ................................. 5.4-19
TO-220AB .............................. 5.4-19
Logic Level MOSFETs ....................... 5.4-20
SOT-223 ............................... 5.4-20
DPAK .................................. 5.4-20
D2PAK ................................. 5.4-21
TO-220AB .............................. 5.4-21
Insulated Gate Bipolar Transistors (IGBTs) ..... 5.4-22
N-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.4-22
Ignition IGBTs . . . . . . . . . . . . . . . . . . . . . . . .. 5.4-22
Standard and Copackaged IGBTs ........ 5.4-22

Tape and Reel Options .......... 4.11-1
Tape and Reel ................................ 4.11-2
AnalogMPQTable ............................. 4.11-4

Communications, Power and
Signal Technologies Group
Products .................. 5.0-1
Small Signal Transistors, FETs
and Diodes ...................... 5.1-1
Bipolar Transistors .............................. 5.1-2
Plastic-Encapsulated Transistors .............. 5.1-2
Plastic-Encapsulated Multiple Transistors . . . . . .. 5.1-8
Plastic-Encapsulated Surface
Mount Transistors .......................... 5.1-10
Metal-Can Transistors ...................... 5.1-17
Field-EffectTransistors ........................ 5.1-19
JFETs ..................................... 5.1-19
MOSFETs ................................. 5.1-21
Surface Mount FETs ........................ 5.1-22
Tuning and Switching Diodes ................... 5.1-24
Tuning Diodes - Abrupt Junction ............. 5.1-24
Tuning Diodes - Hyper-Abrupt Junction ...... 5.1-28
Hot-Carrier (Schottky) Diodes .. . . . . . . . . . . . . .. 5.1-32
Switching Diodes ........................... 5.1-34
Multiple Switching Diodes .................... 5.1-38
GreenLine Devices ............................ 5.1-40

TVSlZeners
Transient Voltage Suppressors I Zener
Regulator and Reference Diodes .. 5.2-1

Bipolar Power Transistors ........ 5.5-1

TVS (Transient Voltage Suppressors) ............. 5.2-2
General-Purpose . . . . . . . . . . . . . . . . . .. . . . . . . . .. 5.2-2
Axial Leaded for Through-hole Designs ...... 5.2-2
Surface Mount Packages ..................... 5.2-9
Overvoltage Transient Suppressors ........... 5.2-15
Zener Diodes ................................. 5.2-16
Voltage Regulator Diodes . . . . . . . . . . . . . . . . . . .. 5.2-16
Notes - Axial Leaded Chart ................. 5.2-20
Notes - Surface Mount Chart . . . . . . . . . . . . . . .. 5.2-23
Voltage Reference Diodes ................... 5.2-31
Current Regulator Diodes ... . . . . . . . . . . . . . . . .. 5.2-31

Bipolar Power Transistors ....................... 5.5-2
Selection by Package ........................ 5.5-2
Plastic TO-220AB . . . . . . . . . . . . . . . . . . . . . . . .. 5.5-3
Plastic T0-218 Type ...................... 5.5-6
Plastic TO-247 Type ...................... 5.5-7
Large Plastic T0-264 . . . . . . . . . . . . . . . . . . . . .. 5.5-8
Plastic T0-225AA Type
(Formerly T0-126 Type) .................. 5.5-8
DPAK - Surface Mount Power Packages .... 5.5-10
Metal T0-204AA (Formerly T0-3).
T0-204AE ............................. 5.5-11
Audio ..................................... 5.5-15
Electronic Lamp Ballasts . . . . . . . . . . . . . . . . . . . .. 5.5-16

Hybrid Power Module Operation .. 5.3-1
Integrated Power Stage IGBT .................... 5.3-2

Motorola Master Selection Guide

vii

Table of Contents

Table of Contents
Communications, Power and
Signal Technologies Group
Products (continued)

Sensors (continued)
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.9-3
Typical Electrical Characteristic Curves ......... 5.9-4
Unibody Cross-sectional Drawings. . . . . . . . . . . .. 5.9-4
Pressure Side Identification ................... 5.9-5
Selector Guide .............................. 5.9-6
Reference Table ............................ 5.9-11
Packaging Options .......................... 5.9-12

Rectifiers ........................ 5.6-1
Rectifier Numbering System ..................... 5.6-2
Application Specific Rectifiers .................... 5.6-3
Low VF Schottky ............................ 5.6-3
MEGAHERTZ ... . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.6-3
SCANSWITCH .............................. 5.6-3
Automotive Transient Suppressors ............. 5.6-3
SWITCHMODETM Rectifiers . . . . . . . . . . . . . . . . . . . . .. 5.6-4
Surface Mount Schottky ...................... 5.6-4
Axial Lead Schottky .. . . . . . . . . . . . . . . . . . . . . . . .. 5.6-6
TG-220 Type Schottky ....................... 5.6-7
TG-218 Types and TG-247 Schottky ........... 5.6-8
POWERTAP II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.6-9
Ultrafast Rectifiers ............................. 5.6-10
Surface Mount Ultrafast ...................... 5.6-10
Axial Lead Ultrafast ......................... 5.6-10
TG-220 Type Ultrafast ...................... 5.6-11
TG-218 Types and TG-247 Ultrafast .......... 5.6-12
POWERTAP II .............................. 5.6-12
Fast Recovery Rectifiers/General
Purpose Rectifiers ....................... 5.6-13
GaAs Rectifiers Power Manager™ ............... 5.6-14

RF Products .................... 5.10-1
RF Discrete Transistors ........................ 5.10-2
RF Power MOSFETs .......... . . . . . . . . . . . . .. 5.10-4
RF Power Bipolar Transistors. . . . . . . . . . . . . . . .. 5.10-6
HF Transistors . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.10-6
VHF Transistors ......................... 5.10-6
UHF Transistors ......................... 5.10-7
900 MHz Transistors ..................... 5.1o-a
1.5 GHz Transistors ..................... 5.10-10
Microwave Transistors ................... 5.10-10
Linear Transistors ....................... 5.10-12
RF Small Signal Transistors ................. 5.10-14
Selection by Package .................... 5.10-15
Plastic SOE Case .................... 5.10-15
Ceramic SOE Case ................... 5.10-17
Selection by Application .................. 5.10-18
Low Noise ........................... 5.10-18
CATV, MATV and Class A Linear ....... 5.10-19
RF Monolithic Integrated Circuits ............... 5.10-20
Switching ................................. 5.10-21
Antenna Switches .. . . . . . . . . . . . . . . . . . . . .. 5.10-21
Receiver Functions ........................ 5.10-21
General Purpose Integrated Circuits ....... 5.10-21
900 MHz Front End. . . . . . . . . . . . . . . . . . . . .. 5.10-21
1.5-2.2 GHz Front End .................. 5.10-21
2.4 GHz Front End ...................... 5.10-22
Transmitter Functions ...................... 5.10-22
General Purpose Integrated Circuits ....... 5.10-22
900 MHz Transmit Chain .... . . . . . . . . . . . .. 5.10-23
1.5-2.2 GHz Transmit Chain ............. 5.10-24
2.4 GHz Transmit Chain .................. 5.10-25
RF Amplifiers ................................ 5.10-26
High Power ............................... 5.10-28
Land Mobile/Portable .................... 5.10-28
TV Transmitters ......................... 5.10-29
Low Power ................................ 5.10-30
CATV Distribution ....................... 5.10-30
CRT Drivers ............................ 5.10-35
Fiber Optic Receivers. . . . . . . . . . . . . . . . . . .. 5.10-35

Thyristors and Triggers ........... 5.7-1
Silicon Controlled Rectifiers ...................... 5.7-2
TRIACs ....................................... 5.7-7
General Purpose ............................ 5.7-7
Thyristor Triggers .............................. 5.7-14
SIDACs ................................... 5.7-14
Programmable Unijunction Transistors - PUT .. 5.7-14
Silicon Bidirectional Switch (SBS) ............. 5.7-14
High Voltage Bidirectional TVS Devices ........ 5.7-14

Optoelectronic Devices ........... 5.8-1
Optoisolators .................................. 5.8-2
Safety Standard Approvals for 6-Pin
Optoisolators ............................... 5.8-2
Regulatory Approval Certification Index ......... 5.8-2
VDE Approved Optoisolators .................. 5.8-3
6-Pin Dual In-line Package. . . . . . . . . . . . . . . . . . . . .. 5.8-6
Small Outline - Surface Mount .................. 5.8-9
POWER OPTO Isolators ....................... 5.8-10

Sensors ......................... 5.9-1
Introduction .................................
The Basic Structure ..........................
Motorola's Patented X-ducer . . . . . . . . . . . . . . . . ..
Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

Table of C"'Alntents

5.9-2
5.9-2
5.9-2
5.9-3

Surface Mount Information ...... 5.11-1
Information for Using Surface Mount Packages .... 5.11-2
Footprints for Soldering ........................ 5.11-5

viii

Motorola Master Selection Guide

Table of Contents
Product Literature
and Technical Training ....... 6.0-1

Communications, Power and
Signal Technologies Group
Products (continued)

Technical Data Services .........................
Motorola Semiconductor Master Selection Guide ..
Semiconductor Data Update Magazine .........
Mfax- Touch-Tone Fax .....................
Internet Server ..............................
Motorola Data and Application Literature ...........
Motorola Application Literature .............. '"
Technical Training ..............................

Tape and Reel Specifications
and Packaging Specifications .... 5.12-1
Tape and Reel Specifications ................... 5.12-2
Embossed Tape and Reel Ordering Information. 5.12-3
Embossed Tape and Reel Data for Discretes ... 5.12-4
Lead Tape Packaging Standards
for Axial-Lead Components ................. 5.12-6
Packaging Specifications ....................... 5.12-7
T0-92 EIA Radial Tape in Fan Fold Box
oronReel ................................. 5.12-7
Fan Fold Box Styles ......................... 5.12-9
Adhesion Pull Tests ......................... 5.12-9
Reel Styles ............................... 5.12-10

Motorola Master Selection Guide

6.1-1
6.1-1
6.1-1
6.1-1
6.1-1
6.1-2
6.1-6
6.1-7

Device Index
and Subject Index ........... 7.0-1
Device Index ................................... 7.1-1
General Index .............. , ...... '" .... , ..... 7.2-1
Subject Index .................................. 7.2-9

ix

Table of Contents

Table of Contents

x

Motorola Master Selection Guide

Semicustom Application Specific
Integrated Circuits

In Brief ...
Motorola
supports
strategic
programs
and
co--development partnerships to accelerate the availability
of advanced processes (CMOS, BiCMOS, Bipolar),
packaging and CAD technology. Extensive research,
manufacturing and financial resources are focused to
develop and maintain leading edge capabilities.

Motorola Master Selection Guide

ASIC Preview ...............................
Bipolar .....................................
ECl& ETlSeriesArrays ...................
CMOS .....................................
1.0 Micron HDC Series
Sub-Micron H4C & H4CPlus Series. . . . . . . ..
Design Automation Software (OACSTM) .........
Advanced Packaging .........................
Architecture for the 90's CDATM
(Customer Defined Arrays) ...................
CDA - The Architecture of the '90s .........
Bipolar ECl & ETl Series Arrays .................
Third Generation ............................
ETl Series Arrays Extend Design Flexibility . ..
ETl Series Features Mixed ECl-TTL Interface
CMOS ........................................
1.0 Micron CMOS HDCTM Series ..............
Triple-layer Metal ........................
Sub-Micron CMOS H4CTM Series .............
CDATMArchitecture ........................
Sub-Micron CMOS H4CPlus™ Series
Mixed 3.3 V/5.0 V levels .....................
DeSign Automation Software .....................
The Open Architecture CAD System™ ..........
OACSTM 2.2 and 3.1 M Features . . . . . . . . . . . . . . ..
Advanced Packaging ...........................
Quad Flat Pack Molded Carrier Ring
(QFP-MCR) ................................
MicroCoolTM Quad Flat Pack. . . . . . . . . . . . . . . . . ..
Over-Molded Pad Array Carrier (OMPACTM) .....
Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ASIC Regional DeSign Centers - United States ....
ASIC Regional Design Centers - International .....

1.0-1

Page
1.1-1
1.1-1
1.1-1
1.1-1

1.1-1
1.1-1
1.1-1
1.1-1
1.1-1
1.1-2
1.1-2
1.1-2
1.1-2
1.1-3
1.1-3
1.1-3
1.1-4
1.1-4
1.1-5
1.1-6
1.1-6
1.1-6
1.1-7
1.1-7
1.1-7
1.1-7
1.1-8
1.1-8
1.1-8

Application Specific Integrated Circuits (ASICs)

Application Specific Integrated Circuits (ASICs)

1.0-2

rviotoroia iviH:Sier Seiectlofi Guide

ASIC Preview
Architecture for the 90's CDA™
(Customer Defined Arrays)

Bipolar
ECl & ETl Series Arrays

Performance, density and power dissipation are critical
issues for next generation ASIC designs. The integration of
large diffused blocks and embedded memory enhances
intra-chip communication and saves board area. The
Customer Defined Array (CDA) concept lets designers
combine array-based, cell based, and full custom logic with
diffused memory blocks on a die. The concept equally
supports Bipolar and CMOS, each with the capability to
incorporate BiCMOS modules.

Motorola's MOSAIC IIITM technology features modified
transistor structures to reduce series base resistance and
collector-base junction capacitance. The result is enhanced
switching speed. Mixed ECLfITL interface compatibility and
high frequency (over 2.5 GHz) operation highlights the ETL
Series.

CMOS
1.0 Micron HOC Series
Sub-Micron H4C & H4CPlus Series

COA -

High density CMOS arrays (HOC Series) are built on 1.0
micron drawn, triple-layer-metal CMOS process. By utilizing
three layers of metal for signal routing, designers can achieve
greater utilization on a channelless architecture.
The sub-micron (0.7IlLeff) H4C Series enables densities
over 300 K gates with 365 picosecond typical gate delay
performance. It's available in Custom Defined Architecture
(CDA).
Motorola's highest performance 0.6 micron CMOS arrays,
the H4CPlus Series, are targeted for mixed 3.3 V and 5 V
applications. The H4CPlus arrays range in density from
28,400 to 178,000 available gates with packages ranging from
128 QFP to 313 OMPAC.

Architecture

The Architecture of the '90s
Methodology

Technology

I

I PROG~~~~ABLEH,_.P.AL_. .

BIPOLAR

Customer
Defined Arrays
CMOS

Design Automation Software
(OACSTM)
Motorola's Open Architecture CAD System (OACS)
provides a complete ASIC development environment using
industry-standard workstations and leading third-party
design and verification tools. The OACS system integrates
sophisticated ASIC design software tools to handle high
performance designs and has the required flexibility to support
future technology advances.

Benefits
• Time-to-market through integration of functional
building blocks and ASIC design methodology.
• Customers can create application specific arrays.
• Diffused RAM optimized for performance and denSity.
• Fixed die sizes for ease of manufacturing.

Advanced Packaging
OMPAC: (Over-Molded Pad Array Carrier), a surface
mount plastic package with solder bumps instead of traditional
pins for interfacing to printed circuit boards.
QFP-MCR: Quad Flat Package in lead counts from 64 to 304
in optional Molded Carrier Ring which provides coplanarity and
lead protection during manufacturing, testing and shipping.
MicroCool QFP: A new QFP-compatible plastic package
with heat slug attached for improved heat dissipation capacity.

Motorola Master Selection Guide

1.1-1

Application Specific Integrated Circuits (ASICs)

Bipolar

Eel & Ell Series Arrays
Third Generation
ETL Series Arrays
Extend Design Flexibility
The ETl Series is flexible enough to simplify translation
between high speed logic families.
Three. base arrays:
MCA750ETl, MCA3200ETl, MCA6200ETl
•
•
•
•
•
•
•
•
•
•

848 to 6915 Equivalent Gates
Channelled Architecture for up to 100% Utilization
Input and Internal ECl Gate Delays - 0.20 ns (Typical)
TIL Input'Translation Cell Delay - 0.55 ns (Typical)
Up to 168 Universal I/O Signal Ports
Bidirectional ECl and TIL I/O Macros
ECl 100 K, Pseudo ECl and TIL logic Interfaces
Programmable Speed/Power levels
Three-level Series Gated Macros
MCA2 and MCA3 ECl Series Library Compatible

Figure 1. MCA6200ETl In Multi-Layer Ceramic
224 Pln-Grld-Array Designed for High Frequency,
Mlxed-Mode Applications

Motorola's MOSAIC III bipolar process offers unexcelled
mixed TIUECl interface capability in a high performance,
mature technology.

ETL Series Features
Mixed ECL-TTL Interface

lOOK
ECLOR PECL
INPUT BUFFERS

The ETl Series offers mixed ECl, PECl (pseudo ECl) and
TIL compatible Interfaces. The Series combines 200 ps typical
gate delays with 2500 MHz operating frequencies. Any signal
pin can be programmed for input, output, or bidirectional
signals in ECl, TIL or PECl logic. MOSAIC III process
technology, combined with innovative design, extensive
macroceli library and versatile I/O structure adds up to
superior performance and flexibility.

TTL INPUT
TRANSLATORS

f---

---

MACRO
CELLS
M-CELLS

-...

lOOK
ECLOR PECL
OUTPUT BUFFERS

-...

TTL OUTPUT
TRANSLATORS

Figure 2. ETl Series Block Diagram

Table 1. ECl & ETl Series Features
Array
Features

MCA
2200ECL

MCA
10000ECL

Technology
Equivalent Gates

MCA
750ETL

MCA
3200ETL

MCA
6200ETL

3570

6915

110

225

M08AICIII

2412

12402

848
24

Internal (Major) Cells

68

414

1/08ignais

108

256

Input/Interface Cells

96

224

Output (0) Cells

96

200

Max Gate Delay (ns)

0.175

0.175

0.2

0.2

0.2

Max 1/0 Frequency (MHz)

1500

1200

2500

2500

2500

Typical Power Dissipation 0Nl

3-6

lQ-30

1-2

4-7

7-12

Application Specific Integrated Circuits (ASiCsj

i.i-2

Universal 1/0 Ports

42

120

168

MQtoiQla Mast6i Selection Guide

CMOS
1.0 Micron CMOS
HDCTM Series
Triple-Layer Metal
Built on a 1.0 micron, triple-layer metal CMOS process, the
HDC Series represents a significant advancement in
microchip technology. By utilizing three layers of metal for
signal routing and power distribution, designers can achieve
maximum utilization on a channelless architecture having
minimum chip dimensions. The result is high performance
combined with 1/0 flexibility and density.
The HDC Series is available in a wide variety of plastic
surface mount packages. The diversity of package style and
pin count lets the designer best match system size, cost and
performance requirements.

Figure 3. Triple-Layer Metal Signal Routing
Enhances Utilization

Features
•
•
•
•
•
•
•
•
•
•
•
•

3,000 to 49,OOO available gates
Up to 70% utilization
Channelless Sea-Of-Gates architecture
1.0 micron drawn gate length (0.8 ~Leff)
Triple layer metal routing and power distribution
Eight transistor, fully utilizable, oxide isolated primary cell
475 picosecond typical gate delay (2-input NAND)
Fixed RAM blocks (single, dual and quad)
5 V CMOS and TTL compatible 1/0 options
Low power consumption of 6 ~W/gate IMHz
110 cells can be paralleled on-chip for 48 mA drive
Pin functions are 100% programmable as 1/0 or power
on plastic packages
• 1000 V ESD protection, latchup immunity to 100 mA
• Comprehensive workstation based CAD support

QFP-MCR
MOLDED CARRIER RING
64-208 PINS

Figure 4. Typical HOC Series Packages

Table 2. HOC Series Features
Available
Gates

#of Die Pads
(Wirebond)

HDC003

3,036

76

HDC006

5,670

96

HDC008

8,208

108

HDC011

11,208

120

Array

Die Size
(mils square)

Package
Pins

88

136

28-68

120

168

28-84

144

182

28-100

168

202

28-100

Available
If0 Cells

HDC016

16,416

136

204

232

68-128

HDC027

27,270

168

264

282

84-160

HDC031

31,290

180

280

295

68-160

HDC049

49,368

216

352

354

160-208

Motorola Master Selection Guide

1.1-3

Application Specific Integrated Circuits (ASICs)

Sub-Micron CMOS
H4CTM Series

¥"" FIXED I/O RING

B

CDA Architecture

RAM

The H4C Series of CMOS Customer Defined ArraysTht (CDA)
provides a new generation of ASICs to capture the functionality
of the sub-micron process. The new fabrication process of the
H4C Series supports speed requirements of 60 MHz processors
with a power dissipation of only 3 !!WIMHzlgate.
The CDA architecture offers the versatility and efficiency of
system design on a single chip by providing large, full~iffused
architectural blocks such as user configurable SRAMs.
Additionally, to ensure high quality ASIC system designs, several
design-for-test implementations and clock skew management
schemes are available.

U

I/OCELLS--

~

>-

MEGAFUNCTIONSI
EMBEDDED BLOCKS

D

GATE ARRAY
STRUCTURE

Figure 5. The CDA Concept: Megafunctions and
Embedded Blocks Within a Gate Array

Features
• 18,080 to 317,968 available gates
• Compatible channelless, Sea-ot-Gates and
CDA architectures
• 0.7 micron effective gate length
• Triple-layer-metal signal routing and power distribution
• Up to 70% gate utilization (smaller arrays)
• 365 picosecond typical gate delay (2-input NAND)
• User configurable, fully diffused SRAM blocks
up to 256K bits
• Low power consumption - 3 !!w/MHzlgate
• 3.3 V and 5.0 V CMOS and TIL compatible I/O cells
• BIST, JTAG (IEEE 1149.1) and LSSD/ESSD scan supported
• Digital PLL to manage clock skew
• Boundary scan embedded in periphery
• Extended workstation-based CAD support for
embedded functions
• Clock tree synthesis and clock skew management

OMPAC

~
....
'

.~
..

MicroCool QFP

Figure 6. Typical H4C Series Packages
Table 3. H4C Series Features
Array

Available Gates

#ofDie Pads

110 Cells

Package Pins

H4C018

18,080

136

160

80-120

H4C027

27,048

160

196

80-128

H4C035

35,392

176

224

80-160

H4C057

57,368

216

284

80-225

H4C086

85,956

256

344

120-225

H4C123

123,136

304

416

160-313

H4C161

161,364

344

476

160-313

H4C195

195,452

376

524

160-375

H4C267

266,832

432

612

447

H4C318

317,968

468

668

447

Application Specific Integrated Circuits (A::il(;s)

;.i-4

Motoiola Mastei Selection Guide

Product Preview

SELF-TERMINATING
DIFFERENTIAL

Sub-Micron CMOS
H4CPluS™ Series
Mixed 3.3 V/S.O V Levels

ENABLE
DATA OUT
DATA IN

The new sub-rnicron CMOS H4CPlus Series is targeted for
mixed 3.3 V and 5 V applications, as well as low-power 3.3 V
systems. The H4CPlus arrays range in density from 28,400 to
178,000 available gates with packages initially ranging from 128
QFP to 313 OMPAC.
A key feature of this family is a powerful I/O buffer aimed at
meeting the requirement for GTl VO levels and capable of
driving backplanes of 50 n transmission lines in today's
high-performance RISC/CISC microprocessor-based systems.
For the highest possible chip--to-chip operating frequencies,
the H4CPlus family introduces Current Mode Transceiver
logic™ (CMTUM) buffers. This new self-terminating I/O method
permits CMOS chip--to-chip interface speeds (using typical
differential or single-ended inputs) to 250 MHz, at low power
dissipation. It also provides a differential interface directly to
industry standard ECLinPSTM logic when used with a +5 V rail.

HIGH-SPEED
OUTPUT
HIGH-SPEED
INPUT

HIGH-SPEED
INPUT
HIGH-SPEED
OUTPUT
SELF-TERMINATED
SINGLE-ENDED

Figure 7. Interfacing H4CPlus Series with Current
Mode Transceiver Logic

OFP-MCR
MOLDED CARRIER
RING

Features:
•
•
•
•

•
•
•

•
•
•
•

0.6 micron effective gate length
Typical gate delay of 280 ps for a NAN2, FO 2 at 5 V
Power dissipation of 1 IlW/gate/MHz at 3.3 V
Standard 5 V high performance or 2.7 V to 3.6 V low
power configurations, with mixed 3.3 V and 5 V
combinations
Single I/O site, 2 rnA to 24 rnA drive, TTL and CMOS
output macros
PECl input buffer macros supporting inputs
to 250 MHz Typical
Current Mode Transceiver logic I/O buffer for
self-terminated, high-speed differential or single-€nded
interfacing to 250 MHz
Separate 5 V and 3.3 V power bussing
Embedded analog Pll' macros for up to 125 MHz clocks
Industry standard JTAG boundary scan built into I/O
macros
DFT methodology support (JTAG, SIST, lSSD, ESSD)

=

d

4

~

...

"

"

...........

......

~ .. J> I> "

.

'* ~
.. J> ..

: :::: :::::;:;;;
...........
".

...... " ,., " .... .,
....................
.. . . . .. . .. ...... " ..
..

I>

........ ~

"

f! . . . . . . . ..
~

"

OMPAC
BALL GRID ARRAY

~

; : ; : : : : : : : ; : :~!

"

. . . '" .. ., . . . f ~ ........
. . . 1> • • • • • 1 • • • •

,'I \

>

"<

,.

MicroCool
OFP

Figure 8. Typical H4CPlus Series Packages

Table 4. H4CPlus Series Features
Available Gates

Die Size
(milS/side)

Die Pads
Wirebond

I/O Cells

Package Pins

H4CP028

28,400

239

176

160

128-169

H4CP048

48,100

287

216

208

128-225

H4CP075

74,520

337

256

256

128-225

H4CP109

109,368

391

304

312

160-313

H4CP146

145,544

438

344

360

160-313

H4CP178

178,000

476

376

400

160-313

Array Name

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Motorola Master Selection Guide

1.1-5

Application Specific Integrated Circuits (ASICs)

Design Automation Software
Motorola has worked closely with several leading
CAD/CAE vendors to integrate the best design tools in the
industry into one system. In many cases, Motorola has been
instrumental in the definition and refining of key third-party
design tools.
To satisfy specific CAD requirements, Motorola has
developed several design tools to perform netlisting and
translation, rule checking, delay and timing calculation, fault
grading and automatic test pattern generation, floorplanning,
test vector analysis and processing.
The OACS 2.2 and 3.1 M features chart briefly describes
Motorola's OACSTM ASIC design system options.

The Open Architecture CAD
System™
The Open Architecture CAD System (OACS) offers a highly
versatile and powerful design environment for the design of
Motorola's H4CPlus, HC4 Series, and HOC Series CMOS
arrays. The OACS integrates several of the industry's most
powerful design tools with Motorola's high-performance tools

Open Architecture
CAD System

into a standard EDIF based CAD environment. The release of
this Design Reference Guide corresponds to the release of
two major versions of OACS: OACS 2.2 and OACS 3.1 M.
OACS 2.2 is Motorola's point tool CAE solution based on
Cadence's ConceptTM schematic editor, Synopsys' synthesis
tools, and Cadence's Verilog™ logic simulator.
OACS 3.1 M is Motorola'S framework based CAE solution
using Mentor's Falcon Framework™. This solution provides
support of Mentor's design entry tools and QuickSim II logic
simulation.

OACSTM 2.2 and 3.1 M Features:
• EDIF 2.0.0 backplane approach to providing an open
design environment
• Supports the following third-party design tools:
• Synopsys' Design Compiler™, HDL Compiler™, Test
Compiler™ (optional) and Design Wave™
• Cadence's Concept™ schematic capture (2.2)
• Cadence's Verilog XLTM simulator and Veritime™ static
timing analysis (2.2)
• Quad Design's MOTIVE® static timing analysis
(optional) (2.2)
• Mentor Graphics' Falcon Framework™ (3.1 M)
• Mentor Graphics' QuickSim IITM simulator and
QuickPath™ static timing analysis (3.1 M)
• Mentor Graphics' AutoLogic™ design synthesis tool
• Cadence's Gate Ensemble™ and Dracula™ phYSical
layout and verification tools (factory only)
• Motorola design tools:
• Memorist™ diffused SRAM compiler (optional)
• Mustang™ automatic test pattern generation (optional)

AtJJJii(;aliun Specific liitegiated Ciicuits (AS!C::;)

•
•

•
•
•

1.1-6

• TestPASTM test vector validation and extraction
• ERC and MARV comprehensive electrical and
manufacturing rules checking
• PrediXTM floorplanning (optional)
Testability support: ESSDILSSD scan, JTAG boundary
scan, BIST, and scan synthesis
Sophisticated delay and timing limits calculations for
accurate simulation and timing analysiS
• Estimated and actual (back-annotated) wire
capacitances
• Includes intrinsic, riselfall time, output pin loading and
distributed RC delays
• Continuous process, temperature, and voltage variation
Clock skew management: clock-tree synthesis, PLL,
timing driven layout
Supports multiple technologies: HDCMOS, H4C,
H4C-CDA-1C, H4CPlus
Supported on HP9000nXX and SUN-4 SPARC®
workstations

Motorola Master Selection Guide

Advanced Packaging
Low cost, high performance systems require excellence in
ASIC packaging technology. MicroCool, QFP-MCR (Quad
Flat Pack in an optional Molded Carrier Ring), and
Over-Molded Pad Array Carrier (OM PAC) packages illustrate
cost effective manufacturing solutions for high lead count,
high frequency applications.

Quad Flat Pack Molded
Carrier Ring (MCR-QFP)
Motorola currently offers the popular EIAJ standard Plastic
Quad Flat Package (QFP) in lead counts from 64 to 240 pins.
The Molded Carrier Ring (MCR) is a coplanarity and lead
protection device for QFP packages. The ring provides lead
protection during manufacturing/testing and shipping.
Standard ring sizes simplify manufacturing across the
range of packages and improve component testability.

Figure 10. 169-lead OverMolded Pad Array Carrier
(OM PAC) Saves Board Space and
Improves Manufacturing Yields

Over-Molded Pad
Array Carrier (OMPACTM)

MicroCooiTMQuad Flat Pack
The MicroCool QFP is a new QFP compatible plastic
package with improved heat dissipation capacity. It has a heat
slug attached to a printed circuit board which supports a
copper lead frame. The package incorporates a molded
carrier ring to maintain pin coplanarity. Lead counts range from
64 to 304 pOints. MicroCool packaging is cost-effective and
capable of meeting high power dissipation (up to 5 W, depending
on temperature and ambient conditions).

OMPAC consists of a thin double metal printed circuit
board, overmolded with plastic. The integrated circuit is
attached to a gold-plated die flag on the substrate with a
silver-filled epoxy. Electrical connections to the integrated
circuits are made using conventional gold ball bonding
techniques.
Primary Advantages Over QFP

Features:

•
•
•
•
•
•
•
•

• Thermally improved footprint compatible version of
MCR-QFP package
• Constructed using PCB with attached leadframe and heat
slug. The die is attached to the slug which is exposed on
the package top surface
• Coplanarity less than 4 mils using MCR techniques-(PCB
material aids good coplanarity by cutting bowing of
plastic)

Eliminates concerns with lead coplanarity
Improved electrical performance
Comparable or better thermal performance
Requires less costly PCB pitch
Smaller size
No risk of lead damage
Improved manufacturing yields
Competitive pricing

DIE ATTACH
EPOXY
GOLD PLATED
DIE ATTACH
SOLDER BALL

Figure 11. Simplified Cross-Sectional View of OMPAC
Figure 9. MicroCool Quad Flat-Pack in
Molded Carrier Ring Lowers Board Cost and
Improves Thermal Performance

Motorola Master Selection Guide

1.1-7

Application Specific Integrated Circuits (ASICs)

Literature
To order any literature item, call or write:
Motorola Semiconductor Products
Literature Distribution Center
P.O. Box 20912, Phoenix, Arizona 85036
(602) 994-6561

Order Number

Description

Order Number

Design Manuals

H4CDM/D
H4CPDM/D
HDCDM/D
MCA3ECUD
MCA3ETlDM/D
MC92005UM/D

H4C Seri.es CMOS Arrays
H4CPlus Series CMOS Arrays
HDC Series CMOS Arrays
MCA3 ECl Series Arrays
MCA3 ETl Series Arrays
SBus Interface Controller

AN1093/D
AN 1095/D
AN1096/D
AN1099/D

Data Sheets

ETUD
H4C/D
H4CP/D
HDC/D
MCA2200ECUD
MCA10000ECUD
MC92005/D

AN1500
MCA3 ETl Series Macrocell Arrays
Sub-micron H4C Series
CMOS Arrays
H4CPlus Series CMOS Arrays
HDC Series CMOS Arrays
MCA2200ECl Macrocell Array
MCA 1OOOOECl Macrocell Array
Slave Interface Controller

AN1502lD
AN1508/D

AN1509/D
AN15121D
AN1514/D

BrochureslSelector Guides/Misc.

SG367/D
BR916/D
BR931/D
BR1400/D

BR1417/D

Description

Application Notes/Article Reprints

ASIC Product Overview
Packaging Manual for ASIC Arrays
Symbols to Silicon (C_LAN)
Open Architecture CAD SystemOACS2.x
Open Architecture CAD System OACS3.xM

AR518/D

AR5221D
AR524/D

ASIC Regional Design Centers -

United States

California, San Jose
(408) 749-{)510

Illinois, Chicago
(708) 490-9500

ASIC Regional Design Centers -

International

European Headquarters,
Germany, Munich
(089) 92103-{)

England, Aylesbury, Bucks
(0296) 395252

Holland, Eindhoven
(04998) 61211

Hong Kong, Silicon Harbour, Tai Po
(852) 666-8333

Japan, Tokyo
(03) 440-3311

Sweden, Stockholm
(08) 734-8800

Appiication Specific Intsgiat6d Ciicuits (AS!Cs)

1.1-8

Delay and TIming Methods for
CMOS ASICs
Clock Distribution
Guidelines for USing the
Mustang™ ATPG System
Test Methodology for
HDC Series Arrays
JTAG Boundary Scan for
H4C/H4CPlus Arrays
Embedded RAM/BIST
High Frequency Design Techs
& Guidelines for Bipolar
Gate Arrays
ASIC Clock Distribution
USing Pll
TestPAS Primer
H4CPlus Series 3.3 VIS V Design
Considerations
Gate Arrays Simplify Translation
between High Speed Logic
Families
Ranking of Gate Array Vendors
ASIC Package Selection

Massachusetts, Marlborough
(508) 481-8100

France, Velizy
(01) 34635900

Italy, Milan
(02) 82201

Motorola Master Selection Guide

Microcomputer Components

In Brief ...
Motorola continues to be a leading supplier of components
for microcomputer systems. The product portfolio includes
digital signal processors; CISC and RISC and PowerPC
advanced microprocessors and complementary fulHunction
peripherals; a comprehensive selection of high-performance
microcontrollers; VLSI functions for Local Operating Network
applications; and a broad range of fast static RAM and dynamic
RAM chips and modules.
Our commitment is to provide state-of-the-art devices
as well as continuing support of established products, with
six-sigma quality and total customer satisfaction.

Motorola Master Selection Guide

Digital Signal Processors ....................... .
The M68000 Family ........................... .
The M88000 RISC Family ...................... .
The PowerPC RISC Family Microprocessors ...... .
Single-Ghip Microcontrollers (CSIC) ............. .
Single-Chip Microcontrollers (AMCU) ........... .
LonWorks Products ............................ .
Memory Products ............................. .

2.0-1

Page
2.1-1
2.2-1
2.3-1
2.4--1
2.5-1
2.6--1
2.7-1
2.8-1

Microcomputer Components

Micfucumputsi Components

2.0-2

Motorola Master Selection Guide

Digital Signal Processors

In Brief ...
Drawing on both design excellence and expertise in
manufacturing, Motorola has created a range of
architecturally compatible Digital Signal Processing chips.
The philosophy behind the DSP families has been to create
compatibility between products as well as conformance to
international standards.
Motorola offers a complete portfolio of 16- and 24-bit
fixed point and 32-bit floating point DSPs.
In addition, we offer a comprehensive array of
development tools to give the designer access to the full
power and versatility of the DSPs with minimum fuss. All the
tools were designed for ease of use and functionality. They
provide a low-cost means of evaluation and greatly simplify
the design and development phase of a DSP project.

Motorola Master Selection Guide

DSP56100 - 16-Bit Digital Signal Processors
DSP56800 - 16-Bit Digital Signal Processors
DSP56000 - 24-Bit Digital Signal Processors
DSP56300 - 24-Bit Digital Signal Processors
DSP96002 - 32-Bit Digital Signal Processors
DSP56ADC16 - The Analog-To-Digital
Converter ................................ .
DSP Development Tools ....................... .
Application Development Systems ........... .
Graphical User Interface .................... .
DSP Development Software ................... .
Design-In Software Packages ............... .
C-Compiler Packages ...................... .
C-Compiler Upgrades ...................... .

2.1-1

Page
2.1-2
2.1-3
2.1-3
2.1-6
2.1-9
2.1-10
2.1-10
2.1-10
2.1-12
2.1-12
2.1-12
2.1-13
2.1-13

Digital Signal Processors

16-/24-/32-Bit Families -Your Complete DSP Solution
DSP56100 - 16-Bit
Digital Signal Processors
The DSP56100 family of HCMOS, low-power, 16--bit
fixed-point general-purpose digital signal processors (DSP)
is ideal for high end speech coding, telecommunications and
control applications. The first DSP56100 family member, the
DSP56156, combines the high-speed core with 8K bytes
RAM, two serial ports, one parallel port, codec, phase-locked
loop (PLL) and On-Chip Emulation (OnCETM). The
DSP56166, the second member of the DSP561 00 family, has
identical package and pinout to the DSP56156 with different
memory configuration and peripherals.

DSP56156 BENCHMARKS
Benchmark

Host
Control
or
Port B 1/0

HG--H7
or
PortBIlO

Instruction Cycles

Real FIR Filter with Data Shift

1 per Tap

LMS Adaptive Real FIR Filter

2 per Tap

Double Integration Sinewave Generation

2 per Sample

Complex FIR Filter with Data Shift

4 per Tap

General Lattice Filter

4 per Tap

Real Cascaded IIR Biquad
Filter Sections (4 coetl.)

5 per Section

PIDLoop

5

Double Precision Multiply

6

[1x3][3x3] Matrix Multiplication

21

DSP56100 Features
AG--A15 ,;.:==~

• Up to 30 Million Instructions per Second (MIPS) at 60
MHz - 33.3 ns Instruction cycle
• Single-cycle 16 x 16--bit parallel Multiply-Accumulate
• 2 x 4G-bit accumulators with extension byte
• Fractional and integer arithmetic with support for
multi precision arithmetic
• Highly parallel instruction set with unique DSP addressing
modes
• Nested hardware DO loops including infinite loops and
DO zero loop
• Two instruction LMS adaptive filter loop
• Fast auto-return interrupts
• Three external interrupt request pins
• Three 16--bit internal data and three 16-bit internal
address buses
• Individual programmable wait states on the external bus
for program, data, and peripheral memory spaces
• Off-chip memory-mapped peripheral space with
programmable access time and separate peripheral
enable pin
• On-chip memory-mapped peripheral registers
• Low Power Wait and Stop modes
• On-Chip Emulation(OnCE) for unobtrusive, processor
speed independent debugging
• Operating frequency down to DC
• 5 V single power supply
• Low Power (HCMOS)

28erial
Interfaces
8810&
8811
or
PortCl/O

DD-D15 '';;.=0.=-1

Timer or
Tout}
Tin
PortCl/O
Power
Ground

1°1>-[l3CIOci< ou;ae::
1«1"'
~~~
~~QICl
< '" ° e:: and jou;
888 PLL ~Cl

:::; :::; :::;
'---v---J

Interrupt and
Mode Control

'---v---J
OnCETM

PART NUMBERS
Part

Description

XC56156FV40

40 MHz in TQFP

XC56156FV50

50 MHz in TQFP

XC56156FE60

60 MHz in CQFP

XC56166FV60

60 MHz in TQFP

Digital Signal Processors

2.1-2

Motorola Master Selection Guide

DSP56800 -

16-Bit Digital Signal Processors

The DSP56800 core family is the first architecture
designed to enable digital signal processing and embedded
microcontroller functionality. This multi-functional approach
supports applications requiring both signal processing and
control functionality, such as wireless messaging, digital
answering machines, feature phones and low-cost wireline
modems.
The first two DSP56800 family members, the DSP56L811
and DSP56L812 are identical except for memory
configuration. The DSP56L811 contains 1K of program RAM
and 2K of data RAM. The DSP56L812 features 22K of
program ROM, 2K of data ROM and 2K of data RAM.

DSP56800 Features
•
•
•
•
•
•
•
•

20 MIPS at 40 MHz
3.3 Volts
Three 16-bit Timers
Two Serial Peripheral Interfaces (SPls)
Serial Synchronous Interface (SSI)
JTAG OnCPM Port
Phase-Locked Loop
16 - 32 general purpose input/output pins. (16 dedicated
and 16 shared with peripherals)
• External bus interface to allow for additional memory
• Support for high-level C and C++ programming
languages
• Streamlined instruction set featuring frequently used DSP
and microcontroller codes, as well as control extensions

On-Chip
Expansion

PART NUMBERS (4Q '96 Availability)
Part

Description

XC56L811 BU40

40 MHz in TOFP

XC56L812BU40

40 MHz in TOFP

DSP56000 - 24-Bit Digital Signal Processors
The DSP56000 Family of 24-bit, fixed-point,
general-purpose digital signal processors is Motorola's
original DSP family and has set the standard for high end DSP
devices with its triple Harvard architecture of seven internal
buses and three parallel execution units - Data ALU,
Address Generation Unit, and Program Controller. Motorola
has retained architectural compatibility with the 24-bit family
into the 16-bit DSP56100 and 32-bit DSP96002 products
helping to preserve our customer software investment.
The DSP56000 Family of HCMOS, 24-bit DSP devices
consists of the DSP56002, DSP56L002, DSP56004,
DSP56005, DSP56007, DSP56L007, DSP56009 and the
transitional DSP56001A. All these products are source code
compatible and are used extenSively in telecommunications,
control and audio applications. The DSP56000 Family's
unique 24-bit architecture has made these products the
industry standard for CD-quality digital audio processing.
The DSP56L002 and DSP56L007 low-voltage devices
operate at 3.3 volts which effectively extends the battery life

Motorola Master Selection Guide

of portable applications up to three times longer than 5 volt
systems.

2.1-3

Digital Signal Processors

DSP56002 BENCHMARKS
Benchmark

Instruction Cycles

Real FIR Filter with Data Shift

1 per Tap

Two Dimensional Convolution
(3x3 coell. mask)

1 per Output

LMS Adaptive Real FIR Filter

3 per Tap

Real Cascaded IIR Biquad
Filter Sections (4 coell.)

4 per Section

Complex FIR Filter with Data Shift

4 per Tap

[1x3][3x3] Matrix Multiplication

17

Division

28

Leroux-Gueguen LPC Analysis:
8th Order
10th Order
16th Order

473
622
1203

Digital Signal Processors

2.1-4

Motorola Master Selection Guide

DSP56000 -

24-Bit Digital Signal Processors (continued)

HO-H70r
PortBllO

Host Control or
PortBllO

• Double buffered peripherals
• Power-saving Wait and Stop modes

DSP56002 F'eatures
• 512 x 24-bit on-chip program RAM and 64 x 24-bit
bootstrap ROM
• Two 256 x 24-bit on-Chip data RAMs
• Two 256 x 24-bit on--chip data ROMs containing sine,
A-law, and ~-Iaw tables
• External memory expansion with 16-bit address and
24-bit data buses
• Bootstrap loading from external data bus, Host Interface,
or Serial Communications Interface
• Byte-wide Host Interface (HI) with Direct Memory Access
(DMA) support
Synchronous Serial Interface (SSI) to communicate with
codecs and synchronous serial devices
- 8-, 12-, 16-, 24-bit word sizes
- Up to 32 software-selectable time slots in network
mode
- Serial Communication Interface (SCI) for full-duplex
asynchronous communications
- 24-bit Timer/Event Counter also generates and
measures digital waveforms
- Up to 25 general-purpose 110 (GPIO) pins
- Three external interrupt request pins; one
non-maskable
- 3.3 V (DSP56L002) and 5 V (DSP56002) power
supply options

AO-A15

RXD} Note
TXD
SCLK
2

DSP56002

ig~}Note

Bus
Control

SCK
SRD
STD

3

PINIT~Note
PLOCK
CKP
4
L,-r-T"""'1r-r-r--r,...r-PCAP

I'"ol~-IF-~ i:!:-'-' 't!:.$l-;ff'
-'
1«o~~g~~><

Cl (/)

880

~

Interrupt and Mode Control
NOTES:
1. On-Chip Emulator Port (OnCE'M)
2. SCI Serial or Port CliO
3. SSI Serial or Port CliO
4. Phase-Locked Loop

DSP56004/DSP56007 Features
• Serial Audio Interface (SAl) includes 2 receivers and
3 transmitters, master or slave capability, and
implementation of 12 S, Sony, and Matshushita audio
protocols; two sets of SAl interrupt vectors
• Serial Host Interface (SHI) features single master
capability, lo-word receive FIFO, and support for 8-,
16-, and 24-bit words
• External Memory Interface (EMI) peripheral providing
glueless connection to DRAM, SRAM, and/or EPROM for
audio delay buffering
• Four dedicated, independent, programmable General
Purpose 110 (GPIO) lines
• DSP56004 memory: 512 words PRAM, 2 x 256 words
data RAM, 2 x 256 words data ROM
• DSP56007 memory: 6400 words PROM, 3200 words
data RAM, 1024 words data ROM
• 3.3 V power supply option available (DSP56L007)
• Bootstrap loading via 12 C, SPI, or byte-wide memory
modes available
• Up to 25 general-purpose 1/0 (GPIO) pins

DSP56000 Family Features
• On--chip Harvard architecture permitting simultaneous
accesses to program and two data memories
• Two 56-bit accumulators including extension byte
• Parallel 24 x 24-bit multiply-accumulate in 1 instruction
cycle (2 clock cycles)
• Double precision 48 x 48-bit multiply with 96-bit result in
6 instruction cycles
• 56-bit addition/subtraction in 1 instruction cycle
• Fractional arithmetic with support for multiprecision
arithmetic
• Hardware support for block-floating point FFT
• Hardware nested DO loops
• Zero-overhead fast interrupts (2 instruction cycles)
• On-Chip Emulation (OnCE) port for unobtrusive,
processor speed-independent debugging
• Software-programmable, Phase-Locked Loop (PLL)
based frequency synthesizer for the core clock
• On-chip peripheral registers memory mapped in data
memory space

Motorola Master Selection Guide

2.1-5

Digital Signal Processors

DSP56000 -

24-Bit Digital Signal Processors (continued)

DSP56005 Features

• Bootstrap loading from Serial Host Interface or External
Memory Interface
'These ROMs may be factory programmed with
data/program provided by the application developer.

• Five Pulse Width Modulators (PWM)
• 24-bit timer/event counter also generates and measures
digital waveforms
- Three with alternate outputs; two with open drain or
TTL outputs
- 9-bit to 16-bit data width
- Alternate outputs independently selectable as active
high or active low
• 16-bit Watchdog tirner
• 4608 x 24-bit on-Chip program RAM and 96 x 24-bit
bootstrap ROM
• Two 256 x 24-bit on-chip data RAMs
• Two 256 x 24-bit on-chip data ROMs containing sine and
arc-tangent tables
• External memory expansion with 16-bit address and
24-bit data buses
• Bootstrap loading from external data bus, Host Interface,
or Serial Communications Interface

PART NUMBERS
Part

Description

XC56001ARC27 Transitional Device. DSP56002 recommended
for new designs
XC56001ARC33 Transitional Device. DSP56002 recommended
for new designs
XC56001AFE27

Transitional Device. DSP56002 recommended
for new designs

XC56001AFE33

Transitional Device. DSP56002 recommended
for new designs

XC56001AFC27

Transitional Device. DSP56002 recommended
for new designs

XC56001AFC33

Transitional Device. DSP56002 recommended
for new designs

DSP56009 Features

DSP56002RC40

40 MHz RAM-based in 132-pin PGA

The memory configurations available differentiate this DSP
from the other family members. The DSP core is fed by a large
program ROM, two independent data RAMs, two data ROMs,
a Serial Audio Interface, Serial Host Interface, External
Memory
Interface,
dedicated
1/0
lines,
on-chip
Phase-Locked Loop (PLL), and On-Chip Emulation
(OnCEm) port.
• Completely pin compatible with DSP56004 and
DSP56007 for easy upgrades
• 5 V power supply
• On-chip Harvard architecture permitting simultaneous
accesses to program and two data memories
• 10240 x 24-bit on-chip program ROM'
• 4608 x 24-bit on-chip X-data RAM and 3072 x 24-bit
on-chip X-data ROM'
• 4352 x 24-bit on-chip Y-data RAM and 1792 x 24-bit
on-chip Y-data ROM'
• 512 x 24-bit on-chip program RAM and 64 x 24-bit
bootstrap ROM
• Up to 2304 x 24-bit from X and V data RAM can be
switched to program RAM giving a total of 2816 x 24-bits
of program RAM

DSP56002FC40

40 MHz RAM-based in 132-pin PQFP

DSP56300 -

66 MHz RAM-based in 132-pin PQFP
40 MHz RAM-based in 144-pin TQFP

XC56002PV66

66 MHz RAM-based in 144-pin TQFP

XCP56002PV80

80 MHz RAM-based in 144-pin TQFP

DSP56L002FC40 Low power 40 MHz RAM-based
PQFP

i~

132-pin

XC56L002PV40

Low power 40 MHz RAM-based in 144-pin
TQFP

XC56004FJ50

50 MHz RAM-based in 8O-pin QFP

XC56004FJ66

66 MHz RAM-based in 80-pin QFP

XC56005PV50

50 MHz RAM-based in 144-pin TQFP

XC56007FJ50

50 MHz ROM-based in 80-pin QFP

XC56007FJ66

66 MHz ROM-based in 80-pin QFP

XC56L007FJ40

Low-power 40 MHz ROM-based in 80-pin
QFP

XC56009PV80

80 MHz ROM-based in 80-pin QFP

24-Bit Digital Signal Processors

The first programmable Motorola DSP product to provide
a true single clock-cycle execution, the DSP56300 core
effectively doubles the number of instructions executed
without increasing clock speed, providing 80 MIPS of
performance at 80 MHz while retaining code compatibility with
the rest of the Motorola DSP offerings. The DSP56300 family
offers a new level of performance in MIPS, a rich instruction
set and low power dissipation, enabling a new generation of
products in wireless, telecommunications, and multimedia.

Digital Signal Processors

DSP56002FC66
XC56002PV40

2.1-6

Several significant architectural enhancements include a
barrel shifter, 24-bit addressing, instruction cache and DMA
functionality. The DSP56301 offers 66/80 MIPS using an
internal 66/80 MHz clock at 3.0 - 3.6 V.

DSP56301 Features
• 66/80 MIPS with a 66180 MHz internal clock at 3.0 - 3.6
volts
• Single clock per instruction execution
• Code compatible with the DSP56000 family

Motorola Master Selection Guide

• Fully-static logic with operation to DC
• Wait, stop and intelligent power control circuitry powers
down unused memories, peripherals and core logic on
each individual instruction

Motorola Master Selection Guide

2.1-7

Digital Signal Processors

DSP56300 -

24-Bit Digital Signal Processors (continued)

• OnCE with added JTAG support for system debugging
and testing
• On-chip PLL
• ALU Enhancements over DSP56000
- Fully pipelined barrel shifter supports bit stream
parsing and generation
- Conditional ALU instruction
-16-bit arithmetic supports cellular and videotelephony
standards
• Address Generation Unit Enhancements over DSP56000
- 24-bit addressing provides 16M word addressing for
Program, X and Y memories
- Program Counter relative addressing improves
operating system and compiler efficiency
- Immediate offset addressing
• Program Controller Enhancements over DSP56000
- Hard stack extension in data memory allows unlimited
stack depth without programmer overhead
- Support for instruction code
• Direct Memory Access Unit
- 6 channel fully concurrent DMA supports 120
Mbytes/sec transfers at 80 MHz
- Dedicated address and data buses support
concurrent memory accesses
- Supports peripheral interrupts, internal and external
memory reads/writes

• Two Enhanced Serial Synchronous Interface modules
• Three independent Timer modules
• Glueless interface to SRAM, Synchronous SRAM, DRAM
and memory mapped peripherals
• Off--<:hip expansion to 224 words for program, X, and Y
memory

DSP56301 On-Chip Memories
•
•
•
•
•

On--<:hip
On-Chip
On--<:hip
On-chip
On-Chip

2048 x 24-bit X data RAM
2048 x 24-bit Y data RAM
3072 x 24-bit Program RAM
1024 x 24-bit Instruction Cache/Program RAM
192 x 24 bit Bootstrap ROM

DSP56302 Features
• 8-bit parallel host port
• 34K words on--<:hip RAM
• 144-pin QFP

DSP56303 Features
• Cost effective version of 56301
• 8-bit parallel host port
• 144-pin QFP

PART NUMBERS
Part

Description

DSP56301 PeripheralsJExternal Buses

XC56301 PW66

66 MHz in 208 TQFP

• Modular peripheral and memory design
• Glueless interface to PCI, ISA, and other DSP56301
buses
• One Serial Communication Interface module

XC56302PV60

60 MHz in 144-pin QFP

XC56303PV66

66 MHz in 144-pin QFP

Digital Signal Processors

2.1-8

Motorola Master Selection Guide

DSP96002 - 32-Bit Digital Signal Processors
The DSP96002 has full architecture compatibility with the
16-bit DSP56100 and 24-bit DSP56000 Families. The
DSP96002 is the first in a family of 32-bit IEEE floating-point
DSP devices. The DSP96002 has two identical memory
expansion ports simplifying network configurations for
multiprocessor and DSP96002 communications. These ports
interface to SRAM, DRAM (operating in their fast access
modes), video RAM or directly to other processors with host
interface logic.
Although designed primarily for image processing, other
proven applications include communications, spectrum
analysis, instrumentation, speech processing and pattern
recognition.

OnCE'M

~
(/) ~
oQ ()
en Ci5 wla:::
Cl Cl

Cl Cl

DSP96002 BENCHMARKS
Benchmark
Real
FIR Filter with Data Shift
V=V'S + V
Lattice Filter with Data Shift
Cascaded IIR Biquad Filter
Sections (4 coel!.)
1024-pOint FFT and bit reversal
Complex
V=V'V+V
FIR Filter with Data Shift
1024-point FFT and bit reversal
Graphics/Image Processing
Divide (32-bit accuracy)
Square Root (32-bit accuracy)
Bezier Cubic Evaluation for
Font Compilation
[4x4][4x4] = [4x4]

Interrupt and
Mode Control

~

I~I~I~

\.....
;;;: C3 <3
~Cl 0 0
wOO 0
a::2:2:2

Instruction Cycles
1 per Tap
2
3 per Tap
4 per Section
12880
4
4 per Tap
20931
7
12
13
67

DSP96002 Features

14
Port A

• DSP96000 family architecture
- Full IEEE Standard 754 compatible for 32-bit (SP)
and 44-bit (SEP) arithmetic
- 20 MIPS, 50 ns instruction cycle at 40 MHz
- 60 million floating-point operations per second
(MFLOPS) at 40 MHz
- Single cycle 32 x 32 --7 96-bit multiply/accumulate
- Ten 96-bit general-purpose data registers
- Zero-overhead nested DO loops
- Two instruction--<:ycle fast interrupts
- Low-power Wait and Stop Modes
- On-Chip Emulation for unobtrusive, fuli-speed
debugging
- 4K byte instruction cache
- Integer mode available
- Single precision mode available
- Timer/Event Counter
• DSP96002 peripherals
- Two 32-bit address and data host ports
- Dual channel DMA controller
• DSP96002 memories
- 1024 x 32 program RAM
- 2 x 512 x 32 data RAM
- 2 x 512 x 32 data ROM (sine and cosine tables)

14
PortB

Control

Control

3
PortA

PortB

Host
Interface
and Control

Host
Interlace
and Control

""

--'
0

PART NUMBERS
Part

Description

XC96002RC33

33 MHz in PGA

XC96002RC40

40MHzin PGA

Motorola Master Selection Guide

2.1-9

Digital Signal Processors

DSP56ADC16 -

The Analog-To-Digital Converter

The
DSP56ADC16
is
a
single--chip,
linear
analog-to--digital (AID) converter. It is an ideal choice for
high-performance digital audio systems, voiclrbandwidth
communication and control applications. It does not require
antialiasing filters and sample-and-hold circuitry because they
are an inherent part of the sigma-delta technology. The
DSP56ADC16 can be easily interfaced to the DSP56001 and
other host processors using its flexible serial interface.
Key Features
•
•
•
•
•
•

16-bit output resolution at 100 kHz from FI R filter
12-bit output resolution at 400 kHz from Comb filter
96-dB dynamic range
9O-dB signal-to-THD ratio
9O-dB signal-to-noise ratio
In-band ripple: <0.001 dB

• Maximum output sample rates:
- FIR filter-l00 kHz
- Comb filter - 400 kHz
• Maximum input sample rate is 6.4 MHz
• Maximum internal clock rate is 12.8 MHz
• DC stability is lO-bits
• Supply voltage is single +5V (±10%)
• Supply current is <100 mA
• Linear-phase imalog front end and internal digital filters
• Simple serial interface to host microprocessors
• Fully differential inputs
PART NUMBERS
Part

Description

DSP56ADC16S

16...iJit in Ceramic DIP

DSP Development Tools
Application Development Systems
Every member of the Motorola Family of 16-, 24- and
32-bit DSPs is supported by a multi-component Application
Development System (ADS) which acts as a tool for
designing, debugging and evaluating real-time DSP target
system equipment. The ADS simplifies evaluation of the
user's prototype hardware/software product by making all of
the essential timing and I/O circuitry easily accessible. Using
an IBM PCTM, Macintosh™ II, a Sun-4™, or Hewlett-Packard
Series 700 as a medium between the user and the DSP
hardware significantly reduces the overall complexity and cost
of development while increasing the capabilities of the
system. With the ADS, DSP programs can be executed in
real-time, single instruction traced or multiple instruction
stepped with registers and/or memory block contents
displayed. The ADS is fully compatible with the CLAS
design-in software package for each product and may act as
an accelerator for testing DSP algorithms.
All Application Development Systems offer an On-Chip
Emulation (OnCETM) circuit for unobtrusive, processor speed
independent debugging. The ADS takes full advantage of this
circuit to allow the user non-intrusive control of the target.
General ADS Features
Soitware• Single/multiple stepping through DSP object programs
• Conditional/unconditional software and hardware
breakpOints
• Program patching using a single-line
assembler/disassembler
• Session and/or command logging for later reference
• Loading and saving of files to/from ADM memory
• Macro command definition and execution
• Display enable/disable of registers and memory
• Debug commands which support multiple DSP
development

Digital Signal Processors

• Hexadecimal/decimal/binary calculator
• Multiple inpuVoutput file access from DSP object
programs
• On-line help screens for each command and register
Hardware• Full speed operation
• Multiple ADM support with programmable ADM
addressing
• Stand-alone operation of ADM after initial development
DSP56156ADS Features
• System commands from within ADS user
interface program
• 16K words of configurable static RAM expandable
to 64Kwords
DSP56002ADS Features
• Host operating system commands from within ADS user
interface program
• 8K132K words of configurable RAM for DSP56002 code
development
• 96-pin euro-card connector for accessing all
DSP56000/1 pins
• 1K words of monitor ROM expandable to 4K words
• Separate connectors for accessing serial or
hosVDMA ports
DSP96000ADS Features
• System commands from within ADS user interface
program
• 128K words of configurable static RAM expandable to
512Kwords
• 2K words of EPROM with sockets expandable to 64K
words
• Full support of multiple data memory maps

2.1-10

Motorola Master Selection Guide

• Two sets of 96-pin connectors provide access to all
DSP96002 pins
• 2K words of EPROM with sockets expandable
to 16K words

Motorola Master Selection Guide

2.1-11

Digital Signal Processors

DSP Development Tools (continued)

Graphical User Interface
For DSP Application Development
Systems and Simulators

PART NUMBERS
Development
Systems

Host Machine

DSP56100ADSA'

IBM PC

DSP56100ADSB

Macintosh II

DSP56100ADSF'

Sun-4

A number of Motorola's DSP development systems and
simulators come with graphical user interface software to
ease working on applications based on our product families.

User Friendly

DSP56100ADSH' Hewlett-Packard Series 700
DSP96000ADSA •

IBM PC

DSP96000ADSB

Macintosh II

DSP96000ADSF'

Sun-4

• GUI works native to three operation systems
-SunOS
- Windows 3.1
-HPUX
• Multiple overlapping windows for the display of debugging
information, command input registers, memory, and
programs
• Pull down menus for ease of use
- Dialog boxes for selecting options of complex
commands
- Tool bar will provide fast access to commonly
performed actions
- Keyboard accelerators will be defined for commonly
executed commands
- Help viewer will be provided for viewing pre-defined
help on selected topics

DSP96000ADSH • Hewlett-Packard Series 700
DSP56002ADSA •

IBM PC

DSP56002ADSB

Macintosh II

DSP56002ADSF •

Sun-4

DSP56002ADSH • Hewlett-Packard Series 700
DSP56004ADSA •

IBM PC

DSP56004ADSB

Macintosh II

DSP56004ADSF •

Sun-4

DSP56004ADSH •

Hewlett-Packard Series 700

DSP56005ADSA *

IBM PC

DSP56005ADSB

Macintosh II

DSP56005ADSF •

Sun-4

DSP56005ADSH •

Hewlett-Packard Series 700

DSP56005ADPTR

Adapter Board

DSP56301ADSA'

IBM PC

DSP56301ADSF'

Sun-4

Debugging Capabilities for C Language and Assembly
• Assembly language symbolic or C Language source code
debugging capabilities

DSP Development Software

DSP56301 ADSH • Hewletl-Packard Series 700
DSP56002ADM

ADM Board for 56002

DSP56004ADM

ADM Board for 56004

DSP56156ADM

ADM Board for 56156

DSP56166ADM

ADM Board for 56166

DSP96000ADM

ADM Board for 96000

DSPPCHOST*

PC compatible host board and interface
software

DSPMACHOST

Macintosh II host board and interface
software

DSPSUN4HOST *

Sun-4 host board and interface software

DSPCOMMAND

16-,24-, 32-bit Command Converter
board and software

DSP56002EVM

Evaluation board and software for
DSP56002

DSP56007EVM

Evaluation board and software for
DSP56007

DSP56009EVM

Evaluation board and software for
DSP56009

-

Design-In Software Packages
The SimulatorlMacro-Assembler/Linker/Librarian software
package is a development system support tool. The Simulator
program imitates the operation of the DSP on a clock-cycle by
clock-cycle basis and gives an accurate measurement of
code execution time. All on-chip peripheral operations,
memory and register updates and exception processing
activities may be functionally simulated.
The full-featured Macro Cross Assembler translates one
or more source files containing instruction mnemonics,
operands, and assembler directives into a Common Object
File Format (COFF) file which is directly loadable by the
Simulator. It supports the full instruction set, memory spaces,
and parallel transfer fields of the DSP.
The Linker relocates and links relocatable COFF object
modules from the Assembler to create an absolute load file
which can be loaded directly into the Simulator. The Librarian
utility will merge separate, relocatable object modules into a
single file allowing frequently used modules to be grouped for
convenient linking and storing.
The assembler and linker now provide support for
assembly language source-level debugging via the simulator.
Global symbols, symbols local to sections, and even
underscore labels may be referenced with all scoping

'Supported by Graphical User Interface

Digital Signal Processors

2.1-12

Motorola Master Selection Guide

constructs intact. In addition, the assembler generates
information about included files and macros. The assembler
and linker also support numbered counters ranging from 0 to
65535.
PART NUMBERS
Simulator/Assembler/
Linker/Library

Host Machine

DSP56100CLASA'

IBM PC

DSP56100CLASB

Macintosh II (consult factory)

DSP56100CLASF'

Sun-4

PART NUMBERS

IGNU C Compiler

IHost Machine

DSP56100 Family
DSP561CCCA

IBM PC

DSP561CCCF

Sun-4

DSP561CCCH

Hewlett-Packard Series 700

DSP56000 Family
DSP56KCCA

IBM PC

DSP56KCCF

Sun-4

DSP56KCCH

Hewlett-Packard Series 700

DSP56100CLASH'

Hewlett-Packard Series 700

DSP56000CLASA •

IBM PC

DSP56000CLASB

Macintosh II (consult factory)

DSP53000 Family

DSP56000CLASF *

Sun-4

DSP563CCA

IBM PC

DSP56000CLASH *

Hewlett-Packard Series 700

DSP563CCF

Sun-4

DSP56300CLASA *

IBM PC

DSP563CCH

Hewlett-Packard Series 700

DSP56300CLASF *

Sun-4

DSP56300CLASH *

Hewlett-Packard Series 700

DSP96000CLASA *

IBM PC

DSP96000CLASB

Macintosh II (consult factory)

DSP96000CLASF *

Sun-4

DSP96000CLASH *

Hewlett-Packard Series 700

-

DSP96000 Family
IBM PC

DSP96KCCF

Sun-4

DSP96KCCH

Hewlett-Packard Series 700

C-Compiler Upgrades

'Supported by Graphical User Interface

Registered users of the earlier versions of the Motorola
OSP C compiler can upgrade to the latest GNU C compiler for
$120. To order, contact a Motorola sales representative or
distributor. Have your registration number ready.

C-Compiler Packages
A full ANSI C compliant compiler, based on GNU
technology, provides higher efficiency and implements more
than 20 major optimization techniques. It has improved in-line
assembly capability and an ANSI C preprocessor. The
package includes the C Compiler, a new COFF Assembler,
Linker, complete ANSI C Libraries, and a new C source level
debugger as well as expanded user's reference manual. The
software package is available for various host computers
listed.

Motorola Master Selection Guide

DSP96KCCA

PART NUMBERS

IGNU C Compiler
DSP56000 Family

I

2.1-13

DSP56KCCAJ
DSP56KCCFJ

IHost Machine

I

IBM PC

Sun-4

Digital Signal Processors

Digital Signal Processors

2.1-14

Motorola Master Selection Guide

The M68000 Family
.. . the Upward Compatible 8-/16-/32-Bit Microprocessor Family

In Brief ...
Page
Microprocessors ............................... 2.2-2
Embedded Controllers .......................... 2.2-5
Integrated Processors. . . . . . . . . . . . . . . . . . . . . . . . . .. 2.2-7
Coprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.2-9
DMA Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.2-9
Network Devices ............................... 2.2-9
Data Communication Devices . . . . . . . . . . . . . . . . . .. 2.2-10
General Purpose 110 ........................... 2.2-11
Fiber Distributed Data Interface ................. 2.2-11
Development Tools ............................ 2.2-12
Support Software .. . .. .. . .. .. . .. .. . .. . .. . .. . ... 2.2-12

An MPU For All Functions
To designers of the most advanced microcomputer
systems, the Motorola M68000 Family of microprocessors
needs no introduction. Products based on its members have
become the standard for systems utilizing the UNIX
operating system and for CAD/CAM engineering
workstations. They are invading the next generation designs
of personal computers and color graphics systems, and they
find widespread implementation in multi-user/multi-tasking
applications and in small business systems. M68000 MPUs
are found in the leading products in fault-tolerant systems
requiring high performance and parallel processing, and
they are the preferred components for artificial intelligence
engines requiring large linear addressing capabilities.
Control applications include graphics, numerical controllers,
robotics, telecommunications switching and PBX voice/data
transmission.
Upward Compatibility
The M68000 MPU Family consists of a line of processors
based on a 32-bit flexible register set, a large linear address
space, a simple yet powerful instruction set and flexible
addreSSing modes. The intemal architecture of the 8-, 16-, and
32-bit MPU versions, and the common instruction set, provide
software compatibility and offer an easy upward migration path
for products requiring increasing levels of processing power.
A Host of Peripherals
A large selection of full--function peripheral chips
complements the processor family. Compatible LSI and VLSI
chips for memory management, data communications, DMA
control, network control, system interfacing, general 110 and
graphics, all simplify system design and reduce design and
manufacturing cost while improving system performance.

Motorola Master Selection Guide

2.2-1

The M68000 Family

Microprocessors
The 68K Family of Microprocessors has revolutionized virtually every segment of the electronic industry. They have set the
standard for performance while still maintaining binary software compatibility from generation to generation. The combination of
low cost and high performance (measured in $/system MIPS) makes every member of the FamiJy a price performance leader. The
M68000 Family provides the widest range of price and performance with choices from 1.6 MIPS to over 100 MIPS.
Table 1.
68000

68020

68030

68040

68060

1.6

5.5

12

35

100

-

0.25

0.5

3.5

15

16M Byte

4G Byte

4G Byte

4G Byte

4G Byte

MIPS
MFLOPS
Address Range
Data Bus

16 bit

32 bit

32 bit

32 bit

32 bit

Clock Speed (MHz)

8-16

16-33

16-50

25-40

50-66

Instruction Cache

-

256 Byte

256 Byte

4K Byte

8K

Data Cache

-

-

256 Byte

4K Byte

8K

Burst Mode

-

-

16 Byte R

16 Byte RIW

16 Byte RIW

General Purpose Registers

16

16

16

16

16

Address Modes

14

18

18

18

18

No

No

Yes

Yes'

Yes'

68881

68882

68882

On-Chip

On-Chip

On-Chip MMU
Floating-Point Solution
*Separate Instruction/Data

-

INTEGER UNIT
INSTRUCTION FETCH CONTROLLER
IA
GENERATE
INSTRUCTION
CACHE - - - , /
FETCH
'--EARLY
DECODE

r--- /'--

I

BRANCH~

INSTRUCTION
ATC

INSTRUCTION
CACHE

fl"

fl"

INSTRUCTION
BUFFER

"'7
DECODE

U

INSTRUCTION
ADDRESS

)

I

B
U
S
C

V

0
N
T
R

DECODE

FLOATINGPOINT
EA
EA
UNIT
GENERATE
GENERATE
EA
EA
EA
FETCH
FETCH
FETCH
FP
INT
INT
EXECUTE
EXECUTE
EXECUTE
INSTRUCTION EXECUTION CONTROLLER

~

INSTRUCTION
CACHE CONTROLLER

I

{}

I

<=
=:>

U

I
I

DATA
CACHE CONTROLLER

V
DATA
ATC

D

DATA
CACHE

0

I

L
L
E
R

I

CONTROL
)

DATA AVAILABLE
WRITE-BACK

II

DATA
ADDRESS

I
OPERAND END BUS

'---

Figure 1. MC68060 Block Diagram

The M68000 Family

2.2-2

Motorola Master Selection Guide

controller activity. Additionally, the integer unit is optimized for
high-level language environments. The MC68040 is
user-object--code compatible with previous members of the
M68000 Family and is specifically optimized to reduce the
execution time of compiler-generated code. The MC68040 is
implemented in Motorola's latest HCMOS technology,
providing an ideal balance between speed, power, and
physical device size.
Instruction execution is pipelined in both the integer unit
and FPU. Independent data and instruction MMUs control the
main caches and the address translation caches (ATCs). The
ATCs speed up logical-to-physical address translations by
storing recently used translations. The bus snooper circuit
ensures cache coherency in multimaster and multiprocessing
applications. The MC68040 FPU is user-object--code
compatible with the MC68882 floating-point coprocessor.
The FPU has been optimized to execute the most commonly
used subset of the MC68882 instruction set, and includes
additional
instruction
formats
for
singleand
double-precision rounding of results.
The MMUs support multiprocessing, virtual memory
systems by translating logical addresses to physical
addresses using translation tables stored in memory. Each
MMU has two transparent translation registers available that
define a one-to-one mapping for address space segments
ranging in size from 16 Mbytes to 4 Gbytes each. The
instruction and data caches operate independently from the
rest of the machine, storing information for fast access by the
execution units. Each cache resides on its own internal
address bus and internal data bus, allowing simultaneous
access to both. The data cache provides writethrough or
copyback write modes that can be configured on a
page-by-page basis.
The MC68040 bus controller supports a high-speed,
nonmultiplexed, synchronous external bus interface, which
allows the following transfer sizes: byte, word (2 bytes), long
word (4 bytes), and line (16 bytes). Line accesses are
performed using burst transfers for both reads and writes to
provide high data transfer rates.

MC68060
Superscalar 32-Bit Microprocessor
The MC68060 is fully compatible with all previous
members of the M68000 family. The MC68060 features dual
on--chip caches, fully independent demand-paged memory
management units (MMUs) for both instructions and data,
dual integer execution pipelines, on--chip floating-point unit
(FPU) and a branch target cache. A high degree of instruction
execution parallelism is achieved through the use of a full
internal Harvard architecture, multiple internal buses,
independent execution units, and dual instruction issue within
the instruction controller. Power management is also a key
part of the MC68060 architecture. The MC68060 offers a
low-power mode of operation that is accessed through the
LPSTOP instruction, allowing for full power-down capability.
The MC68060 design is fully static so that when circuits are
not in use, they do not draw power. Each unit can be disabled
so that power is used only when the unit is enabled and
executing an instruction.
Complete code compatibility with the M68000 family allows
the designer to draw on existing code and past experience to
bring products to market quickly. There is also a broad base
of established development tools, including real-time kernels,
operating systems, languages and applications, to assist in
product design. The functionality provided by the MC68060
makes it the ideal choice for a range of high-performance
computing applications as well as many portable applications
that require low power and high performance.

MC68040
Third-Generation 32-Bit
Microprocessor
The MC68040 is Motorola's third generation of M680OQcompatible, high-performance, 32-bit microprocessors. The
MC68040 is a virtual memory microprocessor employing
multiple, concurrent execution units and a highly integrated
architecture to provide very high performance in a monolithic
HCMOS device. On a single chip, the MC68040 integrates an
MC6803O--compatible integer unit, an IEEE 754--compatible
floating-point unit (FPU), and fully independent instruction
and data demand-paged memory management units
(MMUs), including independent 4K-byte instruction and data
caches. A high degree of instruction execution parallelism is
achieved through the use of multiple independent execution
pipelines, multiple internal buses, and a full internal Harvard
architecture, including separate physical caches for both
instruction and data accesses. The MC68040 also directly
supports cache coherency in multi master applications with
dedicated on-chip bus snooping logiC.
The MC68040 is an enhanced, 32-bit, HCMOS
microprocessor that combines the integer unit processing
capabilities of the MC68030 microprocessor with independent
4K-byte data and instruction caches and an on--chip FPU.
The MC68040 maintains the 32-bit registers available with
the entire M68000 Family as well as the 32-bit address and
data paths, rich instruction set, and versatile addressing
modes. Instruction execution proceeds in parallel with
accesses to the internal caches, MMU operations, and bus

Motorola Master Selection Guide

MC68030
The Second Generation 32-Bit MPU
The 030 started with a high performance 020 core and
added many performance improvement features including
increased internal parallelism, dual on--chip caches with a
burst fillable mode, dual internal data and address buses,
improved bus interface, and on--chip paged memory
management unit.
Two independent 32-bit address buses and two 32-bit
data buses allow the CPU, caches, MMU, and the bus
controller to operate in parallel, so the 030 can, for example,
simultaneously access an instruction from the instruction
cache, data from the data cache and instruction/data from
external memory.
Performance is further enhanced by on--chip instruction
and data caches. Separate 256-byte data and instruction
caches reduce the access time and increase CPU throughput
by providing data and instructions on--chip.

2.2-3

The M68000 Family

MC68030 (continued)
Overall bus requirements are reduced and multiple
processors can run more efficiently thanks to increased
bandwidth of the 030 bus, achieved by the enhanced bus
controller allowing high speed fills of both data and instruction
caches.
The on-chip paged memory management unit translates
logical address to the corresponding physical address in 1/2
the time required by the 020 and MC68851 Paged Memory
Management Unit. Pipelining permits this translation to be
performed in parallel with other functions so that no translation
time is added to any bus cycle.

MC68HC001
Low Power HCMOS 8-/16-/32-Bit
Microprocessor
The MC68HC001 provides a functional extension of the
MC68HCOOO HCMOS 16-/32-bit microprocessor with the
addition of statically selectable 8- or 16-bit data bus
operation. The MC68HC001 is object-code compatible with
the MC68HCOOO, and code written for the MC68HC001 can
be migrated without modification to any member of the
M68000 Family. This is possible because the user
programming model is identical for all members olthe M68000
Family and the instruction sets are proper subsets for the
complete architecture.

MC68020
The Original 32-Bit Performance
Standard
The MC68020, oh twenty, is the industry's leading 32-bit
microprocessor because of high performance, architecture,
ease of design-in, and long-range compatible growth path.
The 020 has a full 32-bit internal and 32-bit external,
regular, symmetrical architecture designed with the customer
in mind. It offers all the functionality of the other M68000
Family MPUs, and maintains software user-code
compatibility which controls the expense of your product
migration.
Programmers appreciate the large general purpose
register set, simple yet powerful instruction set and the many
flexible M68000 addressing modes. The unique on-chip
instruction cache helps provide burst-mode operation to 12.5
MIPS.
The 020 is the proven leader in high performance systems
in office automation, engineering workstations, fault tolerant
computers, parallel processors, telephone switching systems,
and intelligent controllers.

MC68010
A Virtual Memory Enhancement
The MC68010 offers the advantage of Virtual Memory. A
high-speed loop mode operation executes tight software
loops faster to enhance performance. Its instruction
continuation feature has made it the choice for fault-tolerant
and parallel processing systems. The MC68010 can support
a governing operating system which handles the supervisory
chores of any number of subordinate operating systems.

MC68HCOOO
A Micropower Alternative
HCMOS design gives the MC68HCOOO all the functions
and performance of its MC68000 predecessors . . . at
one-tenth of the operating power requirements. With a
maximum power dissipation of only 0.175 watts, the
MC68HCOOO is ideal for high-performance computer
peripherals, industrial controllers, instrumentation and
communications equipment.

The M68000 Family

2.2-4

MC68000
The 16-Bit Foundations
As the first member of the M68000 family, the stateof-the-art technology and advance circuit design concepts
of the MC68000 16-bit MPU started a new trend in
microprocessor architecture. Its seventeen 32-bit data and
address registers permit rapid internal execution of its
powerful yet simple instruction set. It is designed for large
multiprocessing systems and realUme applications with
vectored interrupts, seven priority levels and a 16 megabyte
linear addressing space. It offers mainframe--like performance,
supporting high-level languages and sophisticated operating
systems.
The MC68000 MPU has been joined by more advanced
products with even greater capabilities, yet it satisfies a large .
segment of the existing applications. It is extremely cost
competitive and it remains one of the major growth products
in the entire MPU line.

MC68008
An 8-Bit Compatible Competitor
With an 8-bit data bus and 32-bit internal architecture, the
MC68008 offers performance that competes with a number of
16-bit MPUs. It has the same register set, same instructions,
and the same functionality as the MC68000 with extensive
exception processing. Large modular programs can be
developed and executed efficiently because of the large,
1-megabit non-segmented, linear address space. It is the
choice for high performance, cost effective, 8-bit deSigns,
particularly those requiring a migration path to 16-bit or full
32-bit operation.

Motorola Master Selection Guide

Embedded Controllers
The principle elements of this popular microprocessor family have now been redesigned specifically for embedded applications.
The new 68 ECOxO family including the 68ECOOO, EC020, EC030 and EC040 MPUs are all optimized for cost-sensitive embedded
control designs. The 68ECOxO family offers the high performance of the 680xO family, yet streamlines the feature sets for
embedded applications. The 68ECOxO family completes the triad forming the M68000 family of compatible products: the 680xO
family of computer-class central processing units; the 68300 family of integrated processors; and now, the 68ECOxO family of
embedded microprocessors.
Table 2.
MIPS
Address Range
Data Bus
Clock Speeds

68ECOOO

68EC02O

68EC030

2.5

6.5

10.7

68EC040

29

16M Byte

16M Byte

4G Byte

4G Byte

16 bit

32 bit

32 bit

32 bit

8,10,12,16 MHz

16,25 MHz

25,40 MHz

20, 25, 33* MHz

-

256 Byte

256 Byte

4K Byte

-

256 Byte

4K Byte

Instruction Cache
Data Cache
Burst Fill Caches

-

-

16 Bytes

16 Bytes

General Purpose Registers

16

16

16

16

Address Modes

14

18

18

18

68881168882

68881168882

68881168882

68040

PLCC

PPGA, PQFP

PPGA, CQFP

PGA, CQFP*

Floating Point Hardware
Packages
* Available in the future

This impressive performance is a result of a six-level
pipelined integer unit, independent four-way set-associative
instruction and data caches, and a very high level of on-chip
parallelism. The EC040 also supports multi master and
multiprocessor systems with bus snooping.
By integrating all these features into the EC040, the
microprocessor is able to perform the vast majority of work
on-chip, limiting external memory accesses to allow for higher
system performance with less expensive DRAMs. The result
is virtual immunity to the effects of memory wait states.

MC68EC040
32-Bit High-Performance
Embedded Controller
The 68EC040 is the newest addition to Motorola's
embedded microprocessor family. It is the performance leader
for top-of-the-line embedded applications. The EC040 is
capable of delivering 29 MIPS of sustained performance at 1.2
cycles per instruction with a system cost that is unattainable
by competing architectures.

Motorola Master Selection Guide

2.2-5

The M68000 Family

Embedded Controllers (continued)

MC68EC030

MC68EC020

32-Bit Enhanced Embedded
Controller

32-Bit Embedded Controller

The MC68EC030 is a 32-bit embedded controller that
streamlines the functionality of an MC68030 for the
requirements of embedded control applications. The
MC68EC030 is optimized to maintain performance while
using cost-effective memory subsystems. The rich instruction
set and addressing mode capabilities of the MC68020,
MC68030, and MC68040 have been maintained, allowing a
clear migration path for M68000 systems. The MC68EC030
is object-code compatible with the MC68020, MC68030, and
earlier M68000 microprocessors. Burst-mode bus interface is
provided for efficient DRAM access.
The MC68EC030 has an on--chip data cache and on-chip
instruction cache with 256 bytes each. Dynamic bus sizing is
available for direct interfacing to 8-, 16-, and 32-Bit Devices.
The MC68EC030 includes 32-bit nonmultiplexed address
and data buses, sixteen 32-bit general-purpose data and
address registers, and two 32-bit supervisor stack pOinters
and eight special-purpose control registers. The EC030
provides complete support for coprocessors with the M68000
coprocessor interface. There are two access control registers
that allow blocks to be defined for cacheability protection. The
pipelined architecture, along with increased parallelism,
allows internal caches accesses in parallel with bus transfers
and overlapped instruction execution. The enhanced bus
controller supports asynchronous bus cycles (three clocks
minimum), synchronous bus cycles (two clocks minimum),
and burst data transfers (one clock).

The M68000 Family

2.2-6

The 68EC020, with a complete 32-bit intemal
implementation, has a 32-bit data bus and an on--chip instruction
cache to provide dramatically increased performance over 8and 16-bit microprocessors. In addition, upward migration to
the EC020 is made simple with dynamic bus sizing, allowing
8, 16 and 32-bit peripherals to communicate with the
microprocessor.
Other performance features include advanced bit
manipulation capabilities that provide multiple bit shift operations
in a single instruction cycle. This capability greatly simplifies
and accelerates the bit operations required in graphics
processing and optical recognition applications.

MC68ECOOO
Low-Powered HCMOS
Embedded Controller
The 68ECOOO is a low-power HCMOS derivative of the
68000 optimized for cost-effective embedded processing.
The ECOOO has a flexible data bus that can operate in either
8- or 16-bit modes and a 24-bit address bus that provides
16 Mbytes of memory addressing capability. Electrical
characteristics of the 68ECOOO have been optimized to
ensure easy access to low--cost memories.
The 68ECOOO represents the lowest cost entry point to any
32-bit architecture. Coupled with efficient support for
high-level languages and real-time operating systems, the
68ECOOO provides unparalleled compatible migration paths to
higher performance.

Motorola Master Selection Guide

Each member of the 68300 family contains a core
processor based on the 68000 family, a System Integration
Module (SIM), an on--chip bus and various peripheral
modules. The SIMs include support circuitry such a clock
generation, external chip selects, system protection, timers
and JTAG. The on--chip intermodule bus (1MB) on the
CPU-based 68300s creates a standard interface over which
the CPU and each of the modules communicate. The
peripheral modules include specialized processors, system
controllers, traditional peripherals and memory. Because the
peripheral modules are independent from each other, they can
appear in multiple 68300 devices. With so many major
features incorporated into a single 68300 device, a system
designer can realize improved reliability along with significant
savings in design time, power consumption, cost, board
space, pin count and program development. In a 68300
device, the major functions and glue logiC are all properly
connected, internally timed with the same fast clock, fully
tested and consistently documented.

Integrated Processors
Powerful solutions to cost-, space-, and power-sensitive
embedded applications are provided by the 68300 family of
integrated microprocessors and microcontrollers. The 68300
family combines two of Motorola's greatest strengths - the
32-bit microprocessor architecture of the 68000 family and a
proliferation of peripheral circuits offering a growing family of
integrated solutions.
The 68000 family is based on a proven, expandable
architecture that spans the performance range from 1 to over
29 MIPS. This architecture offers the industry's highest level
of compatibility for both hardware and software. Motorola's
single-chip microcomputers and microcontrollers provide the
industry's broadest selection of peripheral combinations,
insurance that one will fit the need of practically any
application. The 683000 family embraces both of these
concepts.
Table 3

68302

68306

68330

68331

68332

68333

68334

68340

Core Processor

68000

680ECOO

CPU32

CPU32

CPU32

CPU32

CPU32

CPU32

Speeds (MHz)

16,20

16

16,25

16

16

16

16

16,25

DMA

Yes

-

-

-

-

-

Serial Processor

Yes

-

-

-

-

-

Time Processor Unit

-

-

-

-

Yes

Yes

Flash EEPROM

-

-

-

-

-

64K

Yes

Yes

Yes

Yes

-

Yes

Yes

Yes

Timers

1

-

-

1

-

-

AID Converter

-

-

-

-

-

Yes

Yes
1K

Serial 1/0

SRAM

1K

-

-

-

2K

4K

DRAM Controlier

-

Yes

-

-

-

-

Glue Logic (SIM)

Yes

Yes

Yes

Yes

Yes

Yes

-

-

-

-

-

-

3.3 Volts Available

2

Yes

Yes
Yes

combination of architectural and programmable features
concurrent operation of different protocols (HDLC/SDLCTM,
UART, BISYNC, DDCMpTM, or transparent modes) can easily
be achieved. Data concentrators, modems, line cards,
bridges, and gateways are examples of suitable applications
for this device.
The IMP is a Complementary Metal-Oxide Semiconductor
(CMOS) device conSisting of an M68000/MC68008
microprocessor core, a system integration block (SIB), and a
Communications Processor (CP). By integrating the
microprocessor core with the serial ports (in the CP) and the
system peripherals (in the SIB), the IMP is capable of handling
complex tasks such as all ISDN basic rate (2B+D) access
tasks.

MC68302
Integrated Multiprotocol Processor
The MC68302 integrated multiprotocol processor (IMP) is
a very large-scale integration (VLSI) device incorporating the
main building blocks needed for the design of a wide variety
of controllers used in the communications industry. The IMP
is the first device to offer the benefits of a closely coupled,
industry-standard M68000/MC68008 microprocessor core
and a flexible communications architecture. The
three--channel communications device may be configured to
support a number of popular industry interfaces, including
those for the Integrated Services Digital Network (!SDN) basic
rate and terminal adaptor applications. Through a

Motorola Master Selection Guide

Yes

2.2-7

The M68000 Family

Integrated Processors (continued)
storage RAM and dual time bases. In addition to the TPU and
CPU32, the 68332 features the QSM, a 81M and 2-Kbytes of
standby static RAM.

MC68306
Integrated 68ECOO Processor
The 68306 integrated ECOOO processor includes many of
the features commonly found in 68000-based designs. The
68306 includes a 68ECOOO core processor, a 68681 Dual
Universal Asynchronous Receiver Transmitter (DUART),
system integration functions, and a DRAM controller. The
on-chip DRAM controller gives the 68306 the family's
simplest interface to DRAM-based designs. The DRAM
controller easily accommodates 64 Mbytes of memory. The
68306 saves time in the design cycle by providing valuable
68000 system components pre-packaged in one chip.

MC68330
Integrated CPU32 Processor
The 68330 is ideal for applications requiring 32-bit
microprocessor performance without the additional expense
inherent in 32-bit memory systems. The 68330 is the simplest
and lowest priced member of the CPU32-based 68300 family.
The 68330 allows the designer access to the high
performance of the CPU32 along with minimized external glue
logic, while allowing the greatest freedom in selecting needed
peripherals, ASICs or gate arrays.

MC68331
32-Bit Microcontroller

32-Bit Microcontroller
The 68F333 provides the highest level of integration
available to high-performance timing applications such as
avionics and automotive engine control. The 68F333 contains
the CPU32, the TPU and the QSM. It also adds two banks of
flash EEPROM totaling 64-Kbytes, a total of 4-Kbytes of
SRAM (512 bytes separately powered) and an 8-channel,
10-bit analog-to-digital converter. The Single-Chip
Integration Module (SCIM) allows 18 of the external address
and data pins to be converted to I/O pins, resulting in a
single-chip solution suitable for many applications.

MC68334
32-Bit Microcontroller
The 68334 is a streamlined version of the 68332, taking
advantage of the powerful TPU. The 68334 includes the
CPU32 core processor, the TPU, a SIM, 1-Kbyte of SRAM, a
1Q-bit analog-to-digital converter and up to 47 discrete I/O
lines.

MC68340

The 68331 is well suited to applications requiring simple
serial communications and general timing needs. The 68331
contains the CPU32, a SIM, a General Purpose Timer (GPT)
and a Queued Serial Module (QSM). The general purpose
timer is a simple yet flexible timer that provides four modes of
operation with multiple channels for some operations. The
QSM provides two modes of communication: an
asynchronous channel that provides up to 524-Kbits per
second transfer rate and a serial peripheral interface with
separate 16-word receiveitransmit queues.

MC68332
32-Bit Microcontroller
The 68332 is especially suited for high-performance timing
applications such as automotive engine control, precision
motor control and industrial robotics. The powerful Time
Processor Unit (TPU) distinguishes the 68332 providing
optimum performance in controlling time-related activity. It
drastically reduces the need for CPU intervention with its
dedicated execution unit, tri-level prioritized scheduler, data

The M68000 Family

MC68F333

2.2-8

Integrated Multiprotocol Processor
with DMA
The 68340 is excellent for applications requiring
high-speed or block data transfers, such as disk drives and
navigation systems. The combination of general peripherals
and the extremely low power consumption possibilities of the
68340 make it ideal for many battery powered, portable
applications such as hand held computers and data
acquisition systems.
The most distinguishing 68340 feature is the high speed
two channel, 32-bit Direct Memory Access (DMA) controller.
Incorporating the CPU32 and DMA on the same chip
eliminates the usual bus arbitration and synchronization
delays, maximizing data throughout (25-Mbytes per second
on a 16-bit bus).
In addition to the CPU32, a SIM and the DMA, the 68340
contains a 68681/2681-compatible DUART. The 68340 also
has two identical, versatile counter/timers, each with a 16-bit
counter and an 8-bit prescaler with 80 ns resolution.

Motorola Master Selection Guide

Coprocessors

MC68440

MC68851

Dual Direct Memory Access
Controller, DDMA

Paged Memory Management Unit,
PMMU

The DDMA complements the performance capabilities of
M68000 microprocessors by moving blocks of data in a quick,
efficient manner with a minimum of intervention from the MPU.
The DDMA performs memory-to-memory, peripheral-to-memory, and memory-to--peripheral transfers through each
of two completely independent DMA channels. The DDMA
also offers two interrupt vectors per channel and supports both
8-bit and 16-bit data transfers.

The PMMU is a 32-bit memory manager which provides
full support for a demand paged virtual environment with the
68010 or MC68020. It supports a 4-gigabyte addressing
space when used as a coprocessor with the MC68020. An
on-chip address translation cache minimizes translation
delays and maximizes system performance.

MC68881

Network Devices

A Floating Point Coprocessor

MC68824

Designed specifically for arithmetic expansion of the
MC68020 MPUI, this powerful coprocessor can also be used
as a peripheral to all other M68000 family members, and with
non-M68000 processors as well. It performs floating point
math calculations in strict conformance to a full implementation
olthe IEEE Standard for Binary Floating Point Arithmetic (754)
and, in addition to the basic add, subtract, multiply, and divide
functions, it handles full selection of transcendental and
non-transcendental operations. These operations include
root values,
trigonometric functions,
exponentials,
hyperbolics, and logs. All functions are calculated to 80 bits of
extended precision in hardware.

Token Bus Controller, TBC
The TBC is the industry's first single--chip VLSI device to
implement the IEEE 802.4 Media Access Control Sublayer of
the ISO Data Link Layer, as specified by General Motors
Manufacturing Automation Protocol, MAP. The TBC supports
serial data rates of 1, 5, and 10 Mbps and relieves the host
processor of the frame formatting and token management
functions. For efficient transfer of data frames, to and from
memory, the TBC features an on--chip four--channel DMA with
bus master capability, a 32-bit address range, an 8- or 16-bit
data bus, and a 4O-byte FIFO. The MC68824 also offers
support options for network bridges, real-time support and
network monitoring services.

MC68882

MC68184

Enhanced Floating Point
Coprocessor

Broadband Interface Controller

The MC68882 is pin-to-pin hardware and software
compatible with the MC68881 Floating Point Coprocessor and
implements a variety of performance enhancements including
dual-ported registers and an advanced pipeline. Additional
circuitry allows execution of multiple instructions in parallel for
more than twice the Floating Point performance of the
trail-blazing MC68881. Where higher performance
requirements indicate, the MC68882 is a drop-in replacement
for the MC68881.

The MC68184 Broadband Interface Controller (BIC) is a
high--performance interface device for use with the MC68824
Token Bus Controller (TBC) to implement the digital portion of
the physical layer of a broadband IEEE 802.4 token bus node.
The BIC manipulates both data and control for RF transmitter
circuitry and RF receiver circuitry. The CMOS BIC supports
data rates up to 10 Mbps using a duo-binary modulation
technique and provides 20 lines for receiverltransmitter
control with 13 user-defined outputs.
The BIC performs the digital functions of the physical layer
when implementing a broadband token bus node. The modem
side of the BIC provides data and control for the RF
transmitter/receiver circuitry. A standard serial interface is
used to connect the BIC to the MC68824 TBC. The TBC
performs the media access control (MAC) function. The
MC68184 has the ability to scramble and descramble data.

DMA Controllers
MC68450
DMA Controller, DMAC
The DMAC maintains high-performance data movement
for complex M68000 MPU-based systems. While pin
compatible with the MC68440 DDMA, the DMAC offers four
completely independent DMA channels. In addition to all the
features of the DDMA, the DMAC also provides very
sophisticated manipulation of data through sequential and
linked array--chained addressing capabilities.

Motorola Master Selection Guide

MC68185
Twisted-Pair Modem
The MC68185 Twisted-Pair Modem (TPM) is used in
conjunction with a MC68824 Token Bus Controller (TBC), an
RS485 transceiver, and a twisted--pair media to implement a

2.2-9

The M68000 Family

Network Devices: MC68185 -

Twisted-Pair Modem (continued)

low--cost area network (LAN). The MC68824 TBC implements
the layer 2 media access control (MAC) portion of the IEEE
802.4 LAN station and receiver portion for the IEEE 802.2
logical link control (LLC) type 3 as well as providing support for
LLC type 1 and type 2. The TPM interfaces directly to the TBC,
providing physical layer management, including MAC symbol
encoding/decoding at data rates up to 2 Mbps.
The TPM contains an 32 kHz to 20 MHz on--chip crystal
oscillator that generates a transmit clock without external
circuitry. The physical layer management includes local
loopback mode, transmitter enable, and reset. An on-Chip
digital filter provides for noise reduction of received data.

MC68194

X.2S Protocol Controller, XPC
The XPC implements the 1984 CCITT X.25
Recommendation Data Link Procedure (level 2) LAPB. In
addition to handling the lower level communications functions
(HDLC framing, CRC generation/checking, and zero
insertion/deletion), the XPC also independently ha.ndles
higher level communications functions (frame sequencing,
retransmission, flow control, retries limit and timeout
conditions). This allows the host to operate almost totally
isolated from the task of ensuring error-free transmission and
reception of data.

MC68606

Carrierband Modem
The bipolar LSI MC68194Carrierband Modem (CBM),
when combined with the MC68824 Token Bus Controller
(TBC) , provides an IEEE 802.4 single-channel,
phase-coherent carrierband, Local Area Network (LAN)
connection. The CBM performs the physical layer function,
including symbol encoding/decoding, signal transmission and
reception, and phYSical management.
The CBM provides the three basic functions of the physical
layer: data transmission to the coaxial cable, data reception
from the cable, and management of the physical layer. For
standard data mode (also called MAC mode), the CBM
receives a serial transmit data stream from the TBC (called
symbols or atomic symbols), encodes, modulates the carrier,
and transmits the signal to the coaxial cable. Also in the data
mode, the CBM receives a signal from the cable, demodulates
the Signal, recovers the data, and sends the received data
symbols to the TBC. End-of-transmission receiver blanking
as required by IEEE 802.4 is supported. Communication
between the TBC and CBM is through a standardized serial
interface consistent with the IEEE 802.4 DTE-DCE interface.

MC68195

Multi-Link LAPD Controller CCITT
Q.920/Q.921, LAPD
The MC68606 Multi-link LAPD (MLAPD) Protocol
Controller fully implements CCITT Recommendation
0.920/0.921 Link Layer Access Procedure (LAPD) protocol
for ISDN networks. The MLAPD is designed to handle both
signalling and data links in high-performance ISDN primary
rate applications.
This VLSI device provides a cOst-effective solution to
ISDN link-level processing with simultaneous support for up
to 8K logical links. The MC68606 is an intelligent
communications protocol controller compatible with AT&T
specifications for ISDN devices and features low power
consumption and high performance, with an aggregate data
rate in excess of 2.048 Mbps.

Data Communication Devices
MC68681
MC2681
Dual Universal Asynchronous
ReceiverlTransmitter, DUART

Local Talk Adaptor
The MC68195 LocalTalk adaptor (LA) is used in
conjunction with the MC68302 Integrated Multiprotocol
Processor (IMP) to build a network interface to LocalTalk™,
also known as AppleTalk™. LocalTalk refers to the 230.4-kbps
Local Area Network (LAN) that connects multiple Maclntosh™
computers and printers.
The LA provides LocalTalk support for any twp of the three
IMP serial channels. Combinations of multiple LA and/or IMP
devices may be used to support additional LocalTalk
channels. Non-LocalTalk applications can use the LA device
with the IMP to build proprietary HDLC-based LANs at up to
2.5 Mbps using bi-phase space (FMO) encoding.

The M68000 Family

MC68605

2.2-10

The MC68681 features two completely independent
full-duplex asynchronous receiver/transmitter channels that
interface directly to the M68000 microprocessor bus.
Receiver data registers are quadruple buffered and
transmitter data registers are double buffered for minimum
MPU intervention. Each has its own independently selectable
baud rate. Multifunction 6'-bit input port and 8-bit output port,
a 16-bit programmable counter/timer, interrupt handling
capabilities, and a maximum one-megabyte per second
transfer rate make the DUART an extremely powerful device
for complex data communication applications. Full device
functionality with an M6800 bus interface is provided by the
MC2681.

Motorola Master Selection Guide

General Purpose 1/0
MC68230
Parallel InterfacelTimer, PIIT
The PlfT provides versatile double-buffered parallel
interfaces and a system--oriented timer for M68000 systems.
The parallel interfaces operate either in a unidirectional or
bidirectional mode, either 8-- or 16--bit wide. The timer is 24
bits with full programmability and a 5-bit prescaler. The PlfT
has a complete M68000 bus interface and is fully compatible
with the MC68450 DMAC.

MC68901
Multifunction Peripheral, MFP
The MFP provides basic microcomputer function
requirements as a single companion chip to the M68000
Family of Microprocessors. Features provided via a direct
M68000 system bus interface include a full-function,
single--channel
Universal
Serial
Asynchronous
ReceiverfTransmitter (USART) for data communication, an
8--source interrupt controller, eight parallel I/O lines, and four
8--bit timers.

Fiber Distributed
Data Interface
Fiber Distributed Data Interface (FDDI) is defined as a dual
fiber-optic token ring LAN (Local Area Network) that can
support rates up to 100 Mbps. It can accommodate rings with
1,000 stations. Two kilometers between stations, and up to
200 kilometers in total length. This technology is driven by the
need to support high performance distributed computer
systems which are becoming faster and more powerful, thus
imposing a greater need for network speed and bandwidth.
Other uses for FDDI include backbone networks connecting
Ethernet, Token Bus, and Token Ring segments and back end
networks connecting high-speed peripherals. FDDI is an
American National Standards Institute (ANSI) standard.
Motorola's FDDI chip set includes the MC68836, MC6883?,
MC68838, and MC68839.

MC68836
FOOl Clock Generator
The MC68836 FDDI Clock Generator (FCG) implements
part of the Physical Layer (PHY) functions of the FDDI
standard including clock recovery, data recovery, and NRZI

Motorola Master Selection Guide

2.2-11

conversions. The FCG also does a five-bit parallel to serial
conversion during transmission, and a serial to five-bit parallel
conversion during reception. The FCG uses the five-bit
parallel interface to communicate with the MC6883? device.
The FCG directly connects to fiber optic modules through
differential driver/receiver pins. Features include full duplex
operations, 125 MHz clock recovery from incoming serial
NRZI data stream, and 125 MHz transmit clock generation.

MC68837
Elasticity Buffer and Link Manager
The Elasticity Buffer and Link Manager (ELM) implements
the remaining of the PHY functions of the FDDI standard
including data framing, elasticity buffer, encoding, decoding,
smoothing, line state detection, and repeatfilter. The ELM also
implements some Station Management (SMT) functions such
as the Connection Management (CMT), PhYSical Connection
Management (PCM), Physical Connection Insertion (PCI),
and Link Error Monitor (LEM).

MC68838
Media Access Controller
The Media Access Controller (MAC) implements the MAC
portion of the FDDI standard. The MAC protocol is the lower
sub-layer of the ISO OSI data link layer and provides for fair
and deterministic sharing of the phYSical medium, address
recognition, frame check sequence generation and
verification, frame insertion, frame repetition, frame removal,
token generation, and certain error recovery procedures.
Features on the MC68838 include independent receive and
transmit data paths and state machines, bridging support
including a bit order reversal option, a count and void frame
bridge stripping algorithm, and CRC appendage on a per
frame basis. The MAC also contains an interface to Content
Addressable Memory (CAM) for individual and multicast
address recognition.

MC68839
FOOl System Interface
The FDDI System Interface (FSI) is a high performance
interface device which can easily connect to any bus including
high speed processors, little- and big--endian busses, and
multiplexed/non-multiplexed address data busses. Its
primary purpose is to interface the FDDI protocol devices to
the user system bus. FSI features include support for a ring
buffer structure, addressing flexibility, programmable
partitioned 8K bytes internal RAM for temporary data storage,
two 32-bit ports, the ability to sustain up to 250 j.1S bus
latencies, support for synchronous and asynchronous frames,
and the ability to chain multiple buffers per frame.

The M68000 Family

Development Tools
Application Development System
The M68302AOS is a stand-alone board developed by
Motorola that includes software modules (driver code, LAPB,
LAPO, and X.25), a real-time kernel, and a monitor/debugger.
The board consists of the MC68302, memory (512K bytes of
RAM expandable to 1M bytes, 256 bytes of EPROM and
EEPROM), and an MC68681 OUART (to allow all MC68302
serial ports to be available to the user). It is an inexpensive,
ideal platform for software development and testing.

M68ECOxOlDP
Evaluation Boards for Embedded
Controllers
The M68000 family lOP is a board set designed to provide
a low-cost evaluation platform, yet flexible environment for
developing both software and hardware for the family
products. The platform provides the means for M68000
microprocessor and tool evaluation which enables users to
properly select the microprocessor and associated tools for
their next application. Because the turnkey development
system requires the user to do very little to power up the
system and begin development, significant time savings is
realized by reducing the overall time that the product takes to
get to market.
The lOP consists of an M68000 Family microprocessor--based
CPU module as well as a generic lOP motherboard designed

to support each CPU module. The lOP also includes two
software debug monitor programs: Integrated Systems'
ROM68J(TM and Intermetrics' SmartROMTM. This configuration
allows the user to take advantage of an entire suite offeatures,
including
tracing,
assembling,
disassembling
and
downloading, that are offered by the monitors. Optional
software is available to expand the development environment
of the lOP by allowing the user to design, debug and evaluate
the M68000 microprocessor-based applications in real-time
and non-real-time operating system environments. The lOP
also functions as a tool for final test or fault analysis of user
target systems.
The lOP only requires a user-supplied power supply and
an R8-332 ASCII terminal or host computer with an RS-232
serial port. Although the lOP will function using a terminal, the
preferred communication device is a host computer.
Operating the lOP with a host computer allows the user to
develop, compile and debug code using one of many optional
software tools. Once code is developed, the program can be
saved and downloaded to the lOP from the host computer.

M68340EVS
Evaluation System
The M68340EVS is an inexpensive three-board
evaluation and development system which allows the user to
design, debug and evaluate 6834D-based applications. It
interfaces easily to traditional emulation tools and includes its
own software debugger.

Support Software
M68KESW-PC1

M68040FPSP

This Intermetrics software package is for the 68K Family
(68000, 68008, 68HC001, 68010, 68020, 68030, 68EC030,
68040, 683xx). The M68KESW InterTools package includes
C compiler, assemblerllinker, run-time libraries, and one year
of support from Intermetrics.

This software provides 68040 floating point emulation of
unimplemented 68881/68882 functions. Contact factory for
license agreement.

Table 4. Selector Guide
Device Number
MC68000

Package

Speeds

Device Type

64-Lead L', P
68-Lead R, RC', FN

8,10,12,12F'
8,10,12,12F'

Microprocessor

MC68ECOOO

68-LeadFN

8, 10, 12, 16

Embedded Controller

MC68HCOOO

6Head P
68-Lead R, RC', FN
68--Lead FC

8,10,12, 12F', 16
8,10,12,16
8,10,12,16

Microprocessor

MC68l-1cOOl

68--lead R, RC',FN

8,10,12,16

MC68008

48-Lead P
52-Lead FN

8, 10
8, 10

Microprocessor

MC6801 0

64-LeadP
68--Lead R, RC', FN

8,10,12
8,10,12

Microprocessor

.

Not recommended for new deSIgn
All package/speed combinations may not be valid - consu~ factory to verify

The M68000 Family

2.2-12

Motorola Master Selection Guide

Table 4. Selector Guide (continued)

Device Number
MC68020

Package

Speeds

Device Type

114-Lead RC
132-Lead FE'
114-Lead RP
132-Lead FC

12,16,20,25,33
16,20,25
16,20,25
16,20,25

Microprocessor

10D-Lead FG, RP

16,25

Embedded Controller

MC68030

128-Lead RC
124-Lead RP
132-Lead FE

16,20,25,33,40,50
16,20,25,33
16,20,25,33

Microprocessor

MC68EC030

124-Lead RP
132-Lead FE

25,40
25,40

Embedded Controller

MC68040

179--Lead RC

25,33,40

Microprocessor

MC68EC040

179-Lead RC
184-Lead FE

20,25,33
20,25

Embedded Controller

MC68LC040

179-Lead RC
184-Lead FE

20,25,33
20,25

Microprocessor

MC68EC020

MC68040V

184-Lead FE

25,33

Microprocessor

MC68060

223-LeadRC
TBD-Lead FE

50,66
50,66

Microprocessor

MC68184

4D-Lead P, L

-

Network

MC68185

44-Lead FN
68-Lead RC

-

Network

MC68194

52-Lead FJ

-

MC68195

44-Lead FN

-

Network

MC68230

48-Lead P
52-Lead FN

8, 10
8, 10

General Purpose I/O

MC68302

132-Lead RC, FE, FC, FD

16,20

Integrated Processor

MC68306

128-Lead FC
132-Lead FG

16
16

Integrated Processor

MC68330

132-Lead FC

16,25
8,16 @3.3V

Integrated Processor

Network

MC68331

132-Lead FC

16

Integrated Processor

MC68332

132-Lead FC

16

Integrated Processor

MC68340

144-Lead FE
145-Lead RP

16,25
16,25

Integrated Processor

MC68340V

144-Lead FE
145-Lead RP

8,16 @3.3V
8,16@3.3V

Integrated Processor

MC68360

24D-Lead FC
241-Lead RC

0-25
0-25

Integrated Communication
Controller

MC68440

68-Lead L, P
68-Lead R, FN

8,10
8,10

DMA Controller

MC68450

68-Lead L, P
68-Lead R, FN

8,10
8, 10

DMA Controller

MC68605

84-Lead R, RC
84-Lead FN

10,12,16
10,12,16

Network

MC68606

84-LeadRC
84-Lead FN

12, 16
12,16

Network

'I< Not recommended for new design
All package/speed combinations may not be valid - consult factory to verify

Motorola Master Selection Guide

2.2-13

The M68000 Family

Table 4. Selector Guide (continued)
Package

Speeds

Device Type

MC2681

Device Number

40--lead P, L'
44-LeadFN

-

Data Communication

MC68681

4Q-Lead P, L'
44-Lead FN

-

-

Data Communication

MC68824

84-Lead R, RC
84-Lead FN

10,12,16
10,12,16

Network

MC68836

52-LeadFN

MC68837

12Q-LeadKB
12Q-Lead FC

MC68838

120--lead KB
12Q-Lead FC

MC68839

-

-

-

Fiber Distributed Data
Interface
Fiber Distributed Data
Interface

-

Fiber Distributed Data
Interface

184-LeadRC
184-Lead FE

-

Fiber Distributed Data
Interface

MC68851,

132-Lead RC

12,16,20

CoProcessor

MC68881

68-Lead RC, FN

12,16,20

CoProcessor

MC68882

68-Lead RC
68-LeadRN

16,20,25,33,40,50
16,20,25,33,40

CoProcessor

MC68901

48-Lead P
52-Lead FN

-

Genera(Purpose I/O

FC = Plastic Quad (Gull Wing)

FN = Plastic Quad Pack (PLCC)

P = Plastic DIP

FD = Plastic Quad w/Molded Carrier Ring

KB = Ceramic PGA w/Ceramic Lid

R = Pin Grid Array, Solder Lead Finish

FE = Ceramic Quad (Gull Wing)

L = Ceramic DIP

RC = Ceramic PGA, Gold Lead Finish

FG = Plastic Quad Flat Pack (PQFP)

LC = Ceramic DIP, Gold Lead Finish

RP = Plastic Pin Grid Array

• Not recommended for new design
All package/speed combinations may not be valid - consu~ factory to verify

The M68000 Family

2.2-14

Motorola Master Selection Guide

The M88000 RiSe Family

In Brief ...
Page
Architecture, Performance,
and Software Compatibility ..................... . 2.3-2
Microprocessors .............................. . 2.3-2
Cache/Memory Management Units .............. . 2.3-3

Motorola's 88000 Family comes from the only company
committed to long-term upward software compatibility
through such features as hardware interlocked and
protected pipelines. Our goal is to make sure each
generation of the 88000 RISC family delivers a high
performance level while maintaining software compatibility.

Motorola Master Selection Guide

2.3-1

The M88000 RiSe Family

Motorola's 88000 RiSe Microprocessors
... a performance architecture

Architecture, Performance, and
Software Compatibility
The 88000 RISC was designed from the start for
superscaler implementations. In fact, the design of the second
generation 88110 microprocessor is a unique superscaler
implementation called Symmetric Superscalar™. The
Symmetric Superscaler design allows you to execute multiple
instructions in a single clock cycle without any restrictions on
instruction ordering. So there are no wait states or
performance penalties because of out of order instructions.
Also, while other RISC microprocessors may be limited in
the instructions they can execute in a single clock cycle,
members of the 88000 are able to execute multiple
instructions per clock cycle, thus providing the performance
edge required for next generation system designs.

Performance Plus Software
Compatibility
Although high performance is recognized as a key feature
for systems design, software compatibility is also important.
Motorola's 88000 Family comes from the only company
committed to long term upward software compatibility through
such features as hardware interlocked and protected
pipelines. Our goal is to make sure each generation of the
88000 RISC family delivers a high performance level while
maintaining software compatibility. This gives the opportunity
for designing one of the industry's highest performance
systems, while leveraging your largest dollar investment in
new systems, your software.
Software compatibility is also promoted through standards
to provide an open systems environment benefitting system
companies, software developers, and end users because
88000 based systems from different vendors will run all of the
same software.

Microprocessors
MC88100RC
32-Bit RISC Microprocessor
The MC881 00 is the first processor in the 88000 Family of
RISC (reduced instruction set computer) microprocessors.
Implemented with Motorola's HCMOS technology, the
MC88100 incorporates 32-bit registers, data paths, and
addresses. In designing the MC881 00, Motorola has
incorporated a high degree of fine-grain parallelism; four
independent execution units maintain separate, fully
concurrent execution pipelines. Most instructions operate in
one machine cycle or effective concurrent execution can be
accomplished through internal pipelines in one machine cycle.

The M88000 RiSe Family

2.3-2

A common register file provides data sharing and
synchronization control among the execution units through
register scoreboarding.
The MC88100 addresses a variety of applications
reqUiring
high operational
speeds
and
effiCient,
fast-execution architectures. All data manipulation
instructions are nondestructive register to register or register
with immediate operations, allowing both fast operand access
and operand reuse. IEEE 754 floating-point arithmetic is
supported in the processor. Instruction and data memory
space are accessed through separate memory ports, allowing
simultaneous access to dedicated memory areas. The 88000
Family includes the MC88200 CMMU (cache/memory
management unit), which adds high-speed memory caching,
two-level, demand-paged memory management, and
support for shared-memory multiprocessing. The 88000
Family also includes a full line of highly optimizing compilers,
operating systems, development boards, and development
tools.

MC88110RC
32-Bit RISC Microprocessor
The MC8811 0 is the second implementation of the 88000
family of reduced instruction set computer (RISC)
microprocessors. The MC88110 is a Symmetric Superscalar
machine capable of issuing and retiring two instructions per
clock without any special alignment, ordering, or type
restrictions on the instruction stream. Instructions are issued
to multiple execution units, execute in parallel, and can
complete out of order, with the machine automatically keeping
results in the correct program sequence. The SymmetriC
Superscalar design allows sustained performance to
approach the peak performance capability.
The MC88110 uses dual instruction issue and simple
instructions with extremely rapid execution times to yield
maximum efficiency and throughput for 88000 systems.
Instructions either execute in one clock cycle, or effective one
clock cycle execution is achieved through internal pipelining.
Ten independent execution units communicate with a general
register file and an extended register Ii Ie through multiple
80-bit internal buses. Each of the register files has sufficient
bandwidth to supply four operands and receive two results per
clock cycle. Each of the pipelined execution units, including
those that execute floating-point and data movement
instructions, can accept a new instruction and retire a previous
instruction on every clock cycle.
In a single chip implementation, the MC88110 integrates
the central processing unit, floating point unit, graphics
processing unit, virtual memory address translation,
instruction cache, and data cache. The MC88110 maintains
compatibility with MC88100 user application software.

Motorola Master Selection Guide

maintained by MC88204 hardware. The block address
translation cache (BATC) is a 1D-entry cache, loaded by
software, containing translations for 512K-byte memory
blocks. The BATC translations are used for operating system
software or for other memory-resident instructions and data.
In addition, the MMU provides access control for the two
logical address spaces. The CMMU data cache is a 64K-byte,
four-way set-associative cache for instruction or data
storage. The cache incorporates memory-update policies
and
cache--coherency
mechanisms
that
support
multiprocessor applications. The MC88204 CMMU also
includes an MC8810O--compatible processor bus (P bus)
interface and memory bus (M bus) interface.
The MC88204 CMMU is completely software and pin-level
compatible with the MC88200 16K-byte CMMU. The
functionality of the MC88204 is identical to that of the
MC88200. With board layout constraints in mind, a central
processing unit (CPU) may use up to two MC88204 CMMUs
on the data P bus and up to two MC88204 CMMUs on the
instruction P bus to increase data cache and ATC sizes.

Cache/Memory
Management Units
MC88200RC
16-Kilobyte Cache/Memory
Management Unit (CMMU)
The MC88200 CMMU is a high-performance, HCMOS
VLSI device providing zero-wait-state memory management
and data caching. The MMU (memory management unit)
efficiently supports a demand-paged virtual memory
environment
with
two
logical
address
ranges
(user/supervisor) of 4 gigabytes each. Translated addresses
are provided by one oftwo ATCs (address translation caches),
providing address translation in one clock cycle for most
memory accesses. The PATC (page address translation
cache) is a 56-entry, fully associative cache containing
recently used translations for 4-kilobyte memory pages and
is maintained by MC88200 hardware. The BATC (block
address translation cache) is a 1D-entry cache, loaded by
software, containing translations for 512-kilobyte memory
blocks. The BATC translations are used for operating system
software or for other memory-resident instructions and data.
In addition, the MMU provides access control for the two
logical address spaces. The CMMU data cache is a
16-kilobyte, four-way, set-associative cache for instruction
or data storage. The cache incorporates memory-update
policies and cache-coherency mechanisms that support
multiprocessor applications. The MC88200 CMMU also
includes an MC88100--compatible P bus (processor bus)
interface and an M bus (memory bus) interface. A processor
may use two or more CMMUs for increased data cache and
ATC sizes.

MC88410
Secondary Cache Controller
The MC88410 is a highly integrated secondary cache
controller for the MC88110 microprocessor that reduces
memory latency and extends multiprocessing capability for
those seeking the highest level of system performance. Used
with the MCM6211 0 Fast Static RAM, it provides a functionally
complete secondary cache solution for both uniprocessor and
multiprocessor environments. The MC88410 provides tag,
control and buffering for 1/4, 1/2, and 1 Mbyte secondary
cache configurations, all in a single chip cache controller. The
MC88410 eliminates external logic between the processor
and the secondary cache, provides bus arbitration for the
MC88110, and requires no external programming.
The MC88410 and MCM62110 are optimized to provide
low latency memory access to the MC8811 0 processor. Initial
accesses incur only one wait state. Subsequent transactions
in a burst incur zero wait states. Data streaming to the
processor reduces the penalty on secondary cache misses.
The MC88410 expands the MC88110's system flexibility
by providing a choice of secondary cache line size, burst byte
ordering, and system clock frequency. The MC8841 0 extends
the MC88110 multiprocessing capability by significantly
reducing system bandwidth consumption. This increased
available bandwidth, along with the MC88410's hardware
enforced cache
coherency protocol, enable the
implementation of dual bus systems and scalable shared-bus
multiprocessing systems.

MC88204RC
64K-Byte Cache/Memory
Management Unit (CMMU)
The MC88204 CMMU is a high-performance, HCMOS
VLSI device providing zero-wait-state memory management
and data caching. The memory management unit (MMU)
efficiently supports a demand-paged virtual memory
environment with two logical address ranges (user/
supervisor) of 4 Gbytes each. Translated addresses are
provided by one of two address translation caches (ATCs),
providing address translation in one clock cycle for most
memory accesses. The page address translation cache
(PATC) is a 56--entry, fully associative cache containing
recently used translations for 4K-byte memory pages and is

Motorola Master Selection Guide

2.3-3

The M88000 RiSe Family

The M88000 RiSe Family

2.3-4

Motorola Master Selection Guide

The PowerPCTM RISC Family
Microprocessors

In Brief ...
Page
PowerPCTM RISC Microprocessors. . . . . . . . . . . . . . .. 2.4-2
MPC601 RISC Microprocessor. . . . . . . . . . . . . . . . . .. 2.4-2
MPC602 RISC Microprocessor . . . . . . . . . . . . . . . . . .. 2.4-3
MPC603 RISC Microprocessor .. . . . . . . . . . . . . . . . .. 2.4-3
MPC603e RISC Microprocessor. . . . . . . . . . . . . . . . .. 2.4-6
MPC604 RISC Microprocessor . . . . . . . . . . . . . . . . . .. 2.4-9
MPC604e RISC Microprocessor. . . . . . . . . . . . . . . . .. 2.4-9
MPC620 RISC Microprocessor .................. 2.4-13
MPC105 PCI Bridge/Memory Controller .......... 2.4-15
MPC106 PCI Bridge/Memory Controller .......... 2.4-16

The PowerPC architecture is derived from the IBM
Performance Optimized with Enhanced RISC (POWER)
architecture. The PowerPC architecture shares all of the
benefits of the POWER architecture but is optimized for
single-chip implementations. The architecture design
emphasizes parallel instruction execution and high
throughput and allows for exceptional floating-point
performance. The PowerPC architecture is powerful
today and is scalable from palmtops to mainframes.

Motorola Master Selection Guide

2.4-1

The PowerPC RISC Family Microprocessor

PowerPCTM RISC
Microprocessors
The PowerPC Architecture™, developed jointly by
Motorola, IBM, and Apple, is based on the POWER
Architecture™ implemented by the RISC Systeml6000™
family of computers. The PowerPC architecture takes
advantage of recent technological advances in such areas as
process technology, compiler design, and RISC (reduced
instruction set computer) microprocessor design to provide
software compatibility across a diverse family of
implementations, primarily single-chip microprocessors,
intended for a wide range of systems, including
battery-powered personal computers, embedded controllers,
high-end scientific and graphics workstations, and
multiprocessing, microprocessor-based mainframes.
To provide a single architecture for such a broad
assortment of processor environments, the PowerPC
architecture is both flexible and scalable.
The flexibility of the PowerPC architecture offers many
price/performance options. Designers can choose whether to
implement architecturally-defined features in hardware or in
software. For example, a processor designed for a high-end
workstation has greater need for the performance gained from
implementing
floating-point
normalization
and
denormalization in hardware than a battery-powered,
general-purpose computer might.
The PowerPC architecture is scalable to take advantage of
continuing technological advances - for example, the
continued miniaturization of transistors makes it more feasible
to implement more execution units and a richer set of
optimizing features without being constrained by the
architecture.
The PowerPC architecture defines the following features:
• Separate 32-entry register files for integer and
floating-point instructions. The general-purpose registers
(GPRs) hold source and target data for integer arithmetic
instructions, and the floating-point registers (FPRs) hold
source and target data for floating-point arithmetic
instructions.
• Instructions for loading and storing data between the
memory system and either the FPRs or GPRs.
• Uniform-length instructions to allow simplified instruction
pipelining and parallel processing instruction dispatch
mechanisms.
• Nondestructive use of registers for arithmetic instructions
in which the second, third, and sometimes the fourth
operand, typically specify source registers for calculations
whose results are typically stored in the target register
specified by the first operand.
• A precise exception model (with the option of treating
floating-point exceptions imprecisely).
• Floating-point support that includes IEEE-754
floating-point operations.
• The ability to perform both single- and double-precision
floating-point operations.

The PowerPC RISC Family Microprocessor

2.4-2

• A flexible architecture definition that allows certain
features to be performed in either hardware or with
assistance from implementation-specific software
depending on the needs of the processor design.
• User-level instructions for explicitly storing, flushing, and
invalidating data in the on-chip caches. The architecture
also defines special instructions (cache block touch
instructions) for speculatively loading data before it is
needed, potentially reducing the effect of memory latency.
• Definition of a memory model that allows weakly-ordered
memory accesses. This allows bus operations to be
reordered dynamically, which improves overall
performance and in particular reduces the effect of
memory latency on instruction throughput.
• Support for separate instruction and data caches
(Harvard architecture) and for unified caches.
• Support for both big- and little-endian addressing modes.
• Support for 64-bit addressing. The architecture supports
both 32-bit or 64-bit implementations. This document
typically describes the architecture in terms of the 64-bit
implementations in those cases where the 32-bit subset
can be easily deduced.

MPC601 RISC
Microprocessor
The MPC601 is the first implementation of the PowerPC
architecture. The MPC601 implements the 32-bit portion of
the PowerPC architecture, which provides 32-bit effective
(logical) addresses, integer data types of 8, 16, and 32 bits,
and floating-point data types of 32 and 64 bits. For 64-bit
PowerPC implementations, the PowerPC architecture
provides 64-bit integer data types, 64-bit addressing, and
other features required to complete the 64-bit architecture.
The MPC601 is a superscalar processor capable of issuing
and retiring three instructions per clock, one to each of three
execution units. Instructions can complete out of order for
increased performance; however, the MPC601 makes
execution appear sequential.
The MPC601 integrates three execution units-an integer
unit (IU), a branch processing unit (BPU), and a floating-point
unit (FPU). The ability to execute three instructions in parallel
and the use of simple instructions with rapid execution times
yield high efficiency and throughput for MPC601-based
systems. Most integer instructions execute in one clock cycle.
The FPU is pipelined so a single-precision multiply-add
instruction can be issued every clock cycle.
The MPC601 includes an on-Chip, 32-Kbyte, eight-way
set-associative, phYSically addressed, unified instruction and
data cache and an on-chip memory management unit (MMU).
The MMU contains a 256-entry, two-way set-associative,
unified translation look-aside buffer (UTLB) and provides
support for demand paged virtual memory address translation
and variable-sized block translation. Both the UTLB and the
cache use least recently used (LRU) replacement algorithms.

Motorola Master Selection Guide

The MPC601 has a 64-bit data bus and a 32-bit address
bus. The MPC601 interface protocol allows multiple masters
to compete for system resources through a central external
arbiter. Additionally, on-chip snooping logic maintains cache
coherency in multiprocessor applications. The MPC601
supports single-beat and burst data transfers for memory
accesses; it also supports both memory-mapped I/O and I/O
controller interface addressing.
The MPC601 uses an advanced, 3.6--volts (601) or 2.5
volts (601v) CMOS process technology and maintains full
interface compatibility with TTL devices.

The MPC602 has a single bus interface used for
transferring both 32-bit addresses and either 32- or 64-bit
data. This bus is time-multiplexed. The MPC602 interface
protocol allows multiple masters to compete for system
resources through a central external arbiter. The MPC602
provides a three-state coherency protocol that supports the
modified, exclusive, and invalid (MEl) cache states. This
protocol is a compatible subset of the MESI
(modified/exciusive/shared/invalid) four-state protocol and
operates coherently in systems that contain four-state
caches.
The MPC602 uses an advanced, 3.3-V CMOS process
technology and maintains full interface compatibility with TTL
devices.

Block Diagram
Figure 1 provides a block diagram of the MPC601 that
illustrates how the execution units - IU, FPU, and BPU operate independently and in parallel.

Block Diagram
The MPC602 block diagram in Figure 2 illustrates how the
execution units - IU, FPU, BPU, and LSU - operate
independently and in parallel.

MPC602 RISC
Microprocessor

MPC603 RISC
Microprocessor

The MPC602 is a low-cost, low-power implementation of
the PowerPC RISC architecture. The MPC602 implements
the 32-bit portion of the PowerPC architecture, which
provides 32-bit effective addresses, integer data types of 8,
16, and 32 bits, and floating-point data types of 32 and 64 bits.
Floating-point operations involving either 32- or 64-bit data
types in single--precision format are supported; however,
floating;>oint operations involving 64-bit data types in
double-precision format are not implemented in hardware
and are instead trapped for emulation in software.
The MPC602 has four execution units-an integer unit (IU),
a floating;>oint unit (FPU), a branch processing unit (BPU),
and a load/store unit (LSU). The ability to execute four
instructions in parallel and the use of simple instructions with
rapid execution times yield high efficiency and throughput for
MPC602-based systems. Most integer instructions execute
in one clock cycle. The FPU is pipelined such that typically
when the FPU pipeline is full, a single-precision instruction
can complete every clock cycle.
The MPC602 provides dynamic and static power-saving
modes. The three static modes nap, doze, and
sleep - progressively reduce the amount of power
dissipated by the processor.
The MPC602 provides independent on-chip, 4-Kbyte,
two-way set-associative, physically addressed caches for
instructions and data and on-chip instruction and data
memory management units (MMUs). The MPC602 MMUs
contain 32-entry, two-way set-associative, data and
instruction translation lookaside buffers (DTLB and ITLB). The
MPC602 provides an additional memory protection
mechanism not defined by the PowerPC architecture. The
602's protection--only mode can control whether instructions
can be fetched from 4-Kbyte instruction pages and whether
data can be written to 4-Kbyte data pages.

Motorola Master Selection Guide

The MPC603 is the first low-power implementation of the
PowerPC architecture. The MPC603 implements the 32-bit
portion of the PowerPC architecture, which provides 32-bit
effective (logical) addresses, integer data types of 8, 16, and
32 bits, and floating-point data types of 32 and 64 bits. For
64-bit PowerPC implementations, the PowerPC architecture
provides 64-bit integer data types, 64-bit addressing, and
other features required to complete the 64-bit architecture.
The MPC603 provides four software controllable
power-saving modes. Three of the modes (the nap, doze, and
sleep modes) are static in nature, and progressively reduce
the amount of power dissipated by the processor. The fourth
is a dynamic power management mode that causes the
functional units in the MPC603 to automatically enter a
low-power mode when the functional units are idle without
affecting operational performance, software execution or any
external hardware.
The MPC603 is a superscalar processor capable of issuing
and retiring a maximum of three instructions per clock.
Instructions can execute out of order for increased
performance; however, the MPC603 makes completion
appear sequential.
The MPC603 integrates five execution units - an integer
unit (IU), a floating-point unit (FPU), a branch processing unit
(BPU), a load/store unit (LSU) and a system register unit
(SRU). The ability to execute five instructions in parallel and
the use of simple instructions with rapid execution times yield
high efficiency and throughput for MPC603--based systems.
Most integer instructions execute in one clock cycle. The FPU
is pipelined so a single-precision multiply-add instruction can
be issued every clock cycle.

2.4-3

The PowerPC RISC Family Microprocessor

64-8IT DATA BUS
32-BIT DATA BUS

Figure 1. MPC601 Block Diagram

The PowerPC RISC Family Microprocessor

2.4-4

Motorola Master Selection Guide

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Figure 2. MPC602 Block Diagram

Motorola Master Selection Guide

2.4--5

The PowerPC RISC Family Microprocessor

The MPC603 provides independent on--chip, 8-Kbyte,
two-way set-associative, physically addressed caches for
instructions and data and on--chip instruction and data
memory management units (MMUs). The MMUs contain
64-entry, two-way set-associative, data and instruction
translation lookaside buffers (DTLB and ITLB) that provide
support for demand-paged virtual memory address
translation and variable-sized block translation.
The MPC603 has a selectable 32- or 64-bit data bus and
a 32-bit address bus. The MPC603 interface protocol allows
multiple masters to compete for system resources through a
central extemal arbiter. The MPC603 provides a three-state
coherency protocol that supports the Exclusive, Modified, and
Invalid cache states. This protocol is a compatible subset of
the MESI four-state protocol and operates coherently in
systems that contain four-state caches. The MPC603
supports single-beat and burst data transfers for memory
accesses; it also supports both memory-mapped I/O and I/O
controller interface addressing.
The MPC603 uses an advanced, 3.3-V CMOS process
technology and maintains full interface compatibility with TTL
devices.
Block Diagram
Figure 3 provides a block diagram of the MPC603 that
illustrates how the execution units -IU, FPU, BPU, LSU, and
SRU - operate independently and in parallel.
The MPC603 provides address translation and protection
facilities, including an ITLB, DTLB, and instruction and data
BAT arrays. Instruction fetching and issuing is handled in the
instruction unit. Translation of addresses for cache or external
memory accesses are handled by the MMUs.

MPC603e RISC
Microprocessor
The MPC603e is a low-power implementation of the
PowerPC RISC architecture. The MPC603e implements the
32-bit portion of the PowerPC architecture, which provides
32-bit effective addresses, integer data types of 8, 16, and 32
bits, and floating-point data types of 32 and 64 bits.
The MPC603e provides four software controllable
power-saving modes. Three of the modes (the nap, doze, and
sleep modes) are static in nature, and progressively reduce

The PowerPC RISC Family Microprocessor

2.4-6

the amount of power dissipated by the processor. The fourth
is a dynamic power management mode that causes the
functional units in the MPC603e to automatically enter a
low-power mode when the functional units are idle without
affecting operational performance, software execution, or any
external hardware.
The MPC603e is a superscalar processor capable of
issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased
performance; however, the MPC603e makes completion
appear sequential.
The MPC603e integrates five execution units - an integer
unit (IU), a floating-point unit (FPU), a branch processing unit
(BPU), a load/store unit (LSU), and a system register unit
(SRU). The ability to execute five instructions in parallel and
the use of simple instructions with rapid execution times yield
high efficiency and throughput for MPC603e-based systems.
Most integer instructions execute in one clock cycle. The FPU
is pipelined so a single-precision multiply-add instruction can
be issued every clock cycle.
The MPC603e provides independent on--chip, 16-Kbyte,
four-way set-associative, physically addressed caches for
instructions and data and on--chip instruction and data
memory management units (MMUs). The MMUs contain
64-entry, two-way set-associative, data and instruction
translation lookaside buffers (DTLB and ITLB) that provide
support for demand-paged virtual memory address
translation and variable-sized block translation.
The MPC603e has a selectable 32- or 64-bit data bus and
a 32-bit address bus. The MPC603e interface protocol allows
multiple masters to compete for system resources through a
central external arbiter. The MPC603e provides a three-state
coherency protocol that supports the exclusive, modified, and
invalid cache states. This protocol is a compatible subset of
the MESI (modified/exclusive/shared/invalid) four-state
protocol and operates coherently in systems that contain
four-state caches. The MPC603e supports single-beat and
burst data transfers for memory accesses, and supports
memory-mapped I/O accesses.
The MPC603e uses an advanced CMOS process
technology and maintains full interface compatibility with TTL
devices. The MPC603e is implemented in both a 2.5-V
version (PID7V--603e) and a 3.3-V version (PID6--603e).
Block Diagram
Figure 4 provides a block diagram of the MPC603e that
illustrates how the execution units-IU, FPU, BPU, LSU, and
SRU - operate independently and in parallel.

Motorola Master Selection Guide

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Motorola Master Selection Guide

2.4-7

The PowerPC RISC Family Microprocessor

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The PowerPC RISC Family Microprocessor

2.4-8

Motorola Master Selection Guide

MPC604 RISC
Microprocessor

MPC604e RISC
Microprocessor

The MPC604 is an implementation of the PowerPC family
of RISC microprocessors. The MPC604 implements the
PowerPC architecture as it is specified for 32-bit addressing,
which provides 32-bit effective (logical) addresses, integer
data types of 8, 16, and 32 bits, and floating-point data types
of 32 and 64 bits (single-precision and double-precision). For
64-bit PowerPC implementations, the PowerPC architecture
provides additional 64-bit integer data types, 64-bit
addressing, and related features.
The MPC604 is a superscalar processor capable of issuing
four instructions simultaneously. As many as six instructions
can finish execution in parallel. The MPC604 has six
execution units that can operate in parallel-floating-point
unit (FPU), branch processing unit (BPU), load/store unit
(LSU), two single-cycle integer units (SCI Us), and one
multiple-cycle integer unit (MCIU).
This parallel design, combined with the PowerPC
architecture's specification of uniform instructions that allows
for rapid execution times, yields high efficiency and
throughput. The MPC604's rename buffers, reservation
stations, dynamic branch prediction, and completion unit
increase instruction throughput, guarantee in-order
completion, and ensure a precise exception model. (Note that
the PowerPC architecture specification refers to all exceptions
as interrupts.)
The MPC604 has separate memory management units
(MMUs) and separate 18-Kbyte on-chip caches for
instructions and data. The MPC604 implements two
128-entry, two-way set (64-entry per set) associative
translation lookaside buffers (TLBs), one for instructions and
one for data, and provides support for demand-paged virtual
memory address translation and variable-sized block
translation. The TLBs and the cache use least-recently used
(LRU) replacement algorithms.
The MPC604 has a 64-bit external data bus and a 32-bit
address bus. The MPC604 interface protocol allows multiple
masters to compete for system resources through a central
external arbiter. Additionally, on-chip snooping logic
maintains data cache coherency for multiprocessor
applications. The MPC604 supports single-beat and burst
data transfers for memory accesses and memory-mapped
I/O accesses.
The MPC604 uses an advanced, 3.3--V CMOS process
technology and is fully compatible with TTL devices.

The MPC604e is an implementation of the PowerPC family
of RISC microprocessors. The MPC604e implements the
PowerPC architecture as it is specified for 32-bit addreSSing,
which provides 32-bit effective (logical) addresses, integer
data types of 8, 16, and 32 bits, and floating-point data types
of 32 and 64 bits (single-precision and double-precision). For
64-bit PowerPC implementations, the PowerPC architecture
provides additional 64-bit integer data types, 64-bit
addressing, and related features.
The MPC604e is a superscalar processor capable of
issuing four instructions simultaneously. As many as seven
instructions can finish execution in parallel. The MPC604e has
seven
execution
units
that
can
operate
in
parallel - floating-point unit (FPU), branch processing unit
(BPU), condition register unit(CRU), load/store unit (LSU), two
single-cycle integer units (SCI Us), and one multiple-cycle
integer unit (MCIU).
This parallel deSign, combined with the PowerPC
architecture's specification of uniform instructions that allows
for rapid execution times, yields high efficiency and
throughput. The MPC604e's rename buffers, reservation
stations, dynamic branch prediction, and completion unit
increase instruction throughput, guarantee in-order
completion, and ensure a precise exception model. (Note that
the PowerPC architecture specification refers to all exceptions
as interrupts.)
The MPC604e has separate memory management units
(MMUs) and separate 32-Kbyte on-chip caches for
instructions and data. The MPC604e implements two
128-entry, two-way set associative translation lookaside
buffers (TLBs), one for instructions and one for data, and
provides support for demand-paged virtual memory address
translation and variable-sized block translation. The TLBs
and the cache use least-recently used (LRU) replacement
algorithms.
The MPC604e has a 64-bit external data bus and a 32-bit
address bus. The MPC604e interface protocol allows multiple
masters to compete for system resources through a central
external arbiter. Additionally, on--chip snooping logic
maintains data cache coherency for multiprocessor
applications. The MPC604e supports single-beat and burst
data transfers for memory accesses and memory-mapped
I/O accesses.
The MPC604e uses an advanced, 2.5-V CMOS process
technology and is fully compatible with TTL devices.

Block Diagram
Figure 5 provides a block diagram showing features of the
MPC604. Note that this is a conceptual block diagram
intended to show the basic features rather than an attempt to
show how these features are physically implemented on the
chip.

Motorola Master Selection Guide

Block diagram
Figure 6 provides a block diagram of the MPC604e.

2.4-9

The PowerPC RISC Family Microprocessor

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New Features of the MPC604e
Features of the MPC604e that are not implemented in the
MPC604 are as follows:
• Additional special-purpose registers
- HID1 provides four read-only Pll_CFG bits for
indicating the processor/bus clock ratio.
- Three additional registers support the performance
monitor-MMCR1 is a second control register that
includes bits to support the use of two additional
counter registers, PMC3 and PMC4.
• Instruction execution
- Separate units for branch and condition register (CR)
instructions. The BPU is now split into a CR logical
unit and a branch unit, which makes it possible for
branch instructions to execute and resolve before
preceding CR logical instructions. The MPC604e can
still only dispatch one CR logical or branch instruction
per cycle, but it can execute both branch and CR
logical instructions at the same time.
- Branch correction in decode stage. Branch correction
in the decode stage can now predict branches whose
target is taken from the count or link registers if no
updates of the count and link register are pending.
This saves at least one cycle on branch correction
when the mtspr instruction can be sufficiently
separated from the branch that uses the SPR as a
target address.
- Ability to disable the branch target address cache
(BTAC)-HIDO[30] has been defined to allow the
BTAC to be disabled. When HIDO[30] is set, the BTAC
contents are invalidated and the BTAC behaves as if it
were empty. New entries cannot be added until the
BTAC is enabled.
• Improvements to cache implementation
- 32-Kbyte split data and instruction caches. Like the
604, both caches are four-way set associative;
however, each cache has twice as many sets,
logically separated into 128 sets of odd lines and 128
sets of even lines.
- Data cache line-fill buffer forwarding. In the 604 only
the critical double word of a burst operation was made
available to the requesting unit at the time it was burst
into the line-fill buffer. Subsequent data was
unavailable until the cache block was filled. On the
MPC604e, subsequent data is also made available as
it arrives in the line-fill buffer.
- Additional cache copyback buffers. The MPC604e
implements three copyback write buffers (as opposed
to one in the 604). Having multiple copyback buffers
provides the ability for certain instructions to take fuller

The PowerPC RISC Family Microprocessor

2.4-12

advantage of the pipelined system bus to provide
more efficient handling of cache copyback, block
invalidate operations caused by the data cache block
flush (debf) instruction, and cache block clean
operations resulting from the data cache block store
(debst) instruction.
- Coherency support for instruction fetching. Instruction
fetching coherency is controlled by HIOO[23]. In the
default mode, HIOO[23] is 0, GBl is not asserted for
instruction accesses, as is the case with the 604. If
the bit is set, and instruction translation is enabled
(MSR[IR] 1), the GBl signal is set to reflect the M bit
for this page or block. If instruction translation is
disabled (MSR[IR] 0), the GBl signal is asserted.
• System interface operation
- The MPC604e has the same pin configuration as the
MPC604; however, on the MPC604e VOD and AVOD
must be connected to 2.5 Vdc and OVOD must be
connected to 3.3 Vdc. The MPC604e uses split
voltage planes, and for replacement compatibility,
MPC604/MPC604e designs should provide both
2.5-V and 3.3-V planes and the ability to connect
those two planes together and disable the 2.5-V
plane for operation with an MPC604.
- Support for additional processor/bus clock ratios (5:2
and 4:1). Configuration of the processorlbus clock
ratios is displayed through a new MPC604e-specific
register, HID1.
- To support the changes in the cloc!illllLconfiguration,
different precharge timings for the ABB, DBB, ARTRY,
and SHO Signals are implemented internally by the
processor. The precharge timings for ARTRY and
SHO can be disabled by setting HIOO[7].
- No-ORTRY mode. In addition to the normal and fast
l2 modes implemented on the 604, a no-DRTRY
mode is implemented on the MPC604e that improves
performance on read operations for systems that do
not use the DRTRY signal. No-DRTRY mode makes
read data available to the processor one bus clock
cycle sooner than in normal mode. In no-ORTRY
mode, the DRTRY signal is no longer sampled as part
of a qualified bus grant.
• Full hardware support for little-endian accesses.
Little-endian accesses take alignment exceptions for
only the same set of causes as big-end ian accesses.
Accesses that cross a word boundary require two
accesses with the lower-addressed word accessed first.
• Additional enhancements to the performance monitor.

=

=

Motorola Master Selection Guide

MPC620 RISC
Microprocessor
The MPC620 is an implementation ofthe PowerPCTM family
of RISC microprocessors. The MPC620 implements the
PowerPC architecture as it is specified for 64-bit addressing,
which provides 64-bit effective (logical) addresses, integer
data types of 8, 16, 32, and 64 bits, and floating-point data
types of 32 and 64 bits (single-precision and
double-precision). The MPC620 is software compatible with
the 32-bit versions of the PowerPC microprocessor family.
The MPC620 is a superscalar processor capable of issuing
four instructions simultaneously. As many as six instructions
can finish execution in parallel. The MPC620 has six
execution units that can operate in parallel - floating-point
unit (FPU), branch processing unit (BPU), load/store unit
(LSU), two single-cycle integer units (SCIUs), and one
multiple-cycle integer unit (MCIU).
This parallel design, combined with the PowerPC
architecture's specification of uniform instructions that allows
for rapid execution times, yields high efficiency and
throughput. The MPC620's rename buffers, reservation
stations, dynamic branch prediction, and completion unit
increase instruction throughput, guarantee in-order
completion, and ensure a precise exception model.

Motorola Master Selection Guide

The MPC620 has separate memory management units
(MMUs) and separate 32-Kbyte on-chip caches for
instructions and data. The MPC620 implements a 128-entry,
two-way set-associative translation lookaside buffer (TLB)
for instructions and data, and provides support for
demand-paged virtual memory address translation and
variable-sized block translation. The TLB and the cache use
least-recently used (LRU) replacement algorithms.
The MPC620 has a 40-bit address bus, and can be
configured with either a 64- or 128-bit data bus. The MPC620
interface protocol allows multiple masters to compete for
system resources through a central external arbiter.
Additionally, on-chip snooping logic maintains data cache
coherency for multiprocessor applications. The MPC620
supports single-beat and burst data transfers for memory
accesses and memory-mapped I/O accesses.
The MPC620 uses an advanced, 3.3-V CMOS process
technology and is compatible with 3.3-V CMOS devices.

2.4-13

Block Diagram
Figure 7 provides a block diagram showing features of the
MPC620. Note that this is a conceptual block diagram
intended to show the basic features rather than an attempt to
show how these features are physically implemented on the
chip.

The PowerPC RISC Family Microprocessor

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MPC105 PCI
Bridge/Memory Controller
The MPC105 PCI bridge/memory controller (PCIS/MC)
provides a PowerPC reference platform---compliant bridge
between the PowerPC microprocessor family and the
peripheral component interconnect (PCI) bus. PCI support
allows system designers to rapidly design systems using
peripherals already designed for PCI and the other standard
interfaces available in the personal computer hardware
environment. The MPC105 integrates secondary cache
control and a high-performance memory controller that
supports DRAM, SDRAM, ROM, and Flash ROM. The
MPC105 uses an advanced, 3.3-V CMOS process
technology and is fully compatible with TTL devices.
The MPC105 provides an integrated high bandwidth, high
performance, TTL---compatible interface between a 60x
processor, a secondary (L2) cache or secondary 60x
processor, the PCI bus, and main memory.
The MPC105 supports a programmable interface to a
variety of PowerPC microprocessors operating at various bus
speeds. The 60x processor interface uses a subset of the 60x
bus protocol, which enables the interface between the
processor and MPC1 05 to be optimized for performance. The
MPC105's 60x interface allows for a variety of system
configurations by providing support for either a
direct-mapped, lookaside, L2 cache or a secondary 60x
processor. The L2 cache interface generates the arbitration
and support signals necessary to maintain a write-through or

write-back L2 cache. The L2 cache interface supports either
burst SRAMs or asynchronous SRAMs, and L2 data a
per-byte basis. The MPC1 05 features on-chip byte decoding
for L2 data write enables or can be configured to use external
logic for data write enable generation.
The PCI interface connects the processor and memory
buses to the PCI bus, to which 1/0 components are connected,
without the need for "glue" logic. This interface acts as both a
master and slave device.
The memory interface controls processor and PCI
interactions to main memory. It is capable of supporting a
variety of DRAM or SDRAM, and ROM or Flash ROM
configurations as main memory. The maximum supported
memory size is 1 Gbyte of DRAM or SDRAM, with 16 Mbytes
of ROM or 1 Mbyte of Flash ROM.
The MPC1 05 provides hardware support for four levels of
power reduction; the doze, nap, and sleep modes are invoked
by register programming, and the suspend mode is invoked by
assertion of an external signal. The design of the MPC105 is
fully static, allowing internal logic states to be preserved during
all power saving modes. The following sections describe the
programmable power modes provided by the MPC1 05.
Block Diagram
Figure 8 shows the MPC105 in a typical system
implementation. The major functional units within the MPC1 05
are also shown in Figure 1. Note that this is a conceptual block
diagram intended to show the basic features rather than an
attempt to show how these features are physically
implemented on the device.

CONTROL

L2 CACHE
OR
SECONDARY
60X

PROCESSOR

Figure 8. System Implementation and Block Diagram

Motorola Master Selection Guide

2.4-15

The PowerPC RISC Family Microprocessor

MPC106 PCI
Bridge/Memory Controller
The MPC106 provides a PowerPC common hardware
reference platform (CHRP). compliant bridge between the
PowerPC microprocessor family and the Peripheral
Component Interconnect (PC I) bus. PCI support allows
system designers to rapidly design systems using peripherals
already designed for PCI and the other standard interfaces
available in the personal computer hardware environment.
The MPC106 integrates secondary cache control and a
high-performance memory controller. The MPC106 uses an
advanced, 3.3-V CMOS process technology and is fully
compatible with TTL devices.
The MPC106 provides an integrated high-bandwidth,
high-performance, TTL--compatible interface between a 60x
processor, a secondary (L2) cache or secondary 60x
processor, the PCI bus, and main memory.
60x Processor Interface
The MPC106 supports a programmable interface to a
variety of PowerPC microprocessors operating at select bus
speeds. The 60x processor interface of the MPC106 uses a
subset of the 60x bus protocol, supporting single-beat and
burst data transfers. The address bus is 32 bits wide and the
data bus is 64 bits wide. The address and data buses are
decoupled to support pipelined transactions. PCI bus
accesses to system memory space are passed to the 60x
processor bus for snoo~poses. Two signals on the
MPC106, LBCLAIM, and DBGLB, are provided for an optional
local bus slave. The local bus slave must be capable of
generating AACK and TA signals to interact with the 60x
processor(s). Depending on the system implementation, the
processor(s) may operate at the PCI bus clock rate, or at two
orthree times the PCI bus clock rate. The bus is synchronous,
with all timing relative to the rising edge of the bus clock.
L2 Cache/Multiple Processor Interface
The MPC106 provides support for the following
configurations of 60x processors and L2 cache:
• A single 60x processor with no l2 cache
• A single 60x processor plus a direct-mapped, lookaside,
l2 cache
• A single 60x processor plus an external l2 cache
controller or integrated L2 cache module such as the
Motorola MPC2604GA integrated L2 lookaside cache
• Two 60x processors with no L2 cache
• Two 60x processors plus an externall2 cache controller
or integrated L2 cache module such as the Motorola
MPC2604GA integrated l2 lookaside cache

The PowerPC RISC Family Microprocessor

2.4-16

The internal L2 cache controller generates the arbitration
and support signals necessary to maintain a write-through or
write-back l2 cache. The internal l2 cache controller
supports either asynchronous SRAMs, pipelined burst
SRAMs, or synchronous burst SRAMs, using byte parity for
data error detection. When a second 60x ·processor is used,
three signals of the L2 interface (BR1, BG1, and DBG1)
change their functions to allow for arbitration between the 60x
processors. AII60x interface signals of the MPC106, except
the bus request, bus grant, and data bus grant signals, are
shared by the 60x processors. When an external L2 controller
(or integrated L2 cache module) is used, three signals of the
l2 interface (BRl2, BGl2, and DBGL2) changetheirfunctions
to allow the MPC106 to arbitrate between the external cache
and the 60x processor(s).
Memory Interface
The memory interface controls processor and PCI
interactions to main memory and is capable of supporting a
variety of DRAM, or extended data-out (EDO) DRAM and
ROM or Flash ROM configurations as main memory. The
maximum supported memory size is 1 Gbyte of DRAM or EDO
DRAM, with 16 Mbytes of ROM or Flash ROM. The memory
controller of the MPC1 06 supports the various memory sizes
through software initialization of on--chip configuration
registers. Parity or ECC is provided for error detection.
PCI Interface
The MPC106's PCI interface is compliant with the PCI
Local Bus Specification, Revision 2.1, and follows the
guidelines in the PCI System Design Guide, Revision 1.0for
host bridge architecture. The PCI interface connects the
processor and memory buses to the PCI bus, to which I/O
components are connected. The PCI bus uses a 32-bit
multiplexed address/data bus, plus various control and error
signals.
Figure 9 shows the major functional units within the
MPC106. Note that this is a conceptual block diagram
intended to show the basic features rather than an attempt to
show how these features are physically implemented on the
device.

Motorola Master Selection Guide

L2 CACHE
INTERFACE

MEMORY
INTERFACE

L2

60x PROCESSOR
INTERFACE

MEMORY

60x BUS

POWER MANAGEMENT

ERROR/INTERRUPT
CONTROL

CONFIGURATION
REGISTERS

Figure 9. MPC106 Block Diagram

Motorola Master Selection Guide

2.4-17

The PowerPC RISC Family Microprocessor

The PowerPC RISC Family Microprocessor

2.4-18

Motorola Master Selection Guide

Single-Chip
Microcontrollers (CSIC)

In Brief ...
Page
M68HCOS CSIC Family ......................... 2.S-2
M68HC08 Family .............................. 2.S-13
Development Tools ........................... 2.5-14
On-Line Help ........ . . . . . . . . . . . . . . . . . . . . . . . .. 2.S-22

Motorola offers the most comprehensive selection of
high-performance single-chip control systems available
from a single source. Microcontroller device families range
from industry-standard 8-bit controllers to state-of-the-art
16- and 32-bit modular controllers. Within the price and
performance categories of each family, there are a variety of
on-chip capabilities to match specific applications.
Motorola device families are structured so that upward
migration need not involve complete code development.
The M68HC11 Family is upward code compatible with
M6800 and M6801 software, while the M68HC16 family is
source-code compatible with the M68HC11 family.
Motorola's newest 8-bit MCU product line, the M68HC08
family, is fully upward object code compatible with the
M68HCOS and M680S families. In addition, M68300 and
M68HC 16 devices share standard internal modules and
bus configurations.

Motorola Master Selection Guide

2.5-1

Single-Chip Microcontrollers (CSIC)

M68HC05 CSIC Family
It all started with the 68HC05 Family, and Motorola's CSIC
(Customer-Specified Integrated Circuits) approach to
microcontroller design. Today, customers can selectfrom over
70 mask ROM 68HC05 devices and over 30 one-time
programmable (OTP) 68HC705 devices - and that number
is growing all the time, as Motorola continues to develop
derivatives of the 68HC05 based on customer demand.
With so many standard 68HC05 microcontrollers from
which to choose, most customers will find the right device for
an application among these existing devices. For some
high-volume applications, however, a customer may opt for
Motorola to develop a new derivative to meet an application's
precise requirements. The result is a new microcontroller
which can then be added to the selection of standard devices.

M68HC05 Industry Solutions
Motorola's 68HC05 and 68HC08 Families consist of a
variety of microcontroller designs to meet the requirements of
a broad range of applications. The 68HC05 Family, already
over 100 devices strong, offers a wide range of standard
products from which to choose, while the flagship 68HC08
offers a large library of modules from which derivatives can be
developed.

68HC05 General-Purpose
M icrocontrollers
68HC05 C-Family. These flexible, general-purpose
devices feature a wide variety of memory options capable of
handling complex programs. On-Chip SCI provides
asynchronous communications, with software-selectable
baud rates from 75 Hz to 131 kHz. The high-speed,
synchronous 4-wire serial system SPI is ideal for driving
off-chip displays and peripherals.
All C-Family devices include a powerful 16-bit
free-running programmable counter in conjunction with input
capture and output compare functions for simultaneous input
waveform measurement and output waveform generation. A
watchdog timer guards against runaway software in noisy
environments.
The high-packing density of Motorola's HCMOS process
allows standard devices to run at bus frequencies up to
2.1 MHz. Motorola also offers high-speed versions which run
at frequencies up to 4.2 MHz from an 8.4 MHz crystal or
external clock. Low-voltage versions are available for
applications requiring extremely low power consumption to
extend battery life or rninirnize heat dissipation.
68HC05 J-Family. This 20-pin family provides a low-cost,
low pin count, 8-bit upgrade for existing 4-bit applications. It
combines a powerful 68HC05 CPU with a flexible, 15-stage
multifunction timer and real-tirne interrupt capability.
68HC05 K-Family. Our lowest-cost family offers a 16-pin
count and is appropriate for logic replacement.

Single-Chip Microcontroliers (CSIC)

2.5-2

68HC05 P-Family. Born out of the CSIC design concept,
this farnily offers an extrernely cost-cornpetitive 28-lead
family of microcontrollers with a variety of ROM sizes and
special features such as Serial Input/Output Port (SlOP) to
control display drivers and comrnunicate with other
peripherals. Other options include AID input and on-chip
EEPROM for non-volatile data storage. Low-voltage and
high-speed versions are also available.
The flagship 68HC(7)08XL36 OTP and ROM versions are
the first two devices in the 68HC08 Family and are intended
for general purpose uses.

Low-Voltage Microcontrollers
The 68HC05 Family has been capable of 3.0 V operation
since 1980 and includes some 2.2 V selections. Recently,
Motorola announced several 68HC05 microcontrollers
capable of 1.8 Vdc and 500 kHz operation. This new
low-voltage capability affords a greater than threefold power
savings over 3.0 V versions of the same chips, a significant
design consideration for any portable electronic application.
The new devices are collectively designated 68HCL05 and
include the following versions: 68HCL05C4, C8, C12, J1A,
KO, PI, and P4. They are designed to provide lower-power
control technology to accommodate trends in portable
applications toward compactness, lightweight deSign, and
extended battery life.

Automotive
68HC05 B-Family. EEPROM memory in these devices
makes it possible to store information that must be retained
after the power is removed. Applications include electric seat
control (storage of seat positions) and audio systerns (storage
of radio stations).
68HC05 C- and O-Families. These general-purpose
microcontrollers are used for cruise control, ignition systems,
and in-car entertainment systems.
68HC05 J-, K-, and P-Families. With their low pin count
and low cost, these devices are ideal for automotive
applications such as car alarms, power windows, keyless
entry, and air bags.
68HC05 V- and X-Families. Both these groups contain
integrated automotive multiplex interfaces that allow them to
talk to other electronic modules within a vehicle. The V series
adds an on-chip voltage regulator.

Computer
68HC05 BO-Family. These devices are ideal for computer
monitor applications. They include a horizontal and vertical
sync processor as well as 16 channels of pulse-width
modulation.
68HC05 C-Family. These are general purpose devices for
keyboard and monitor control.

Motorola Master Selection Guide

68HC05 J-, P-, and E-Families. These low-cost, low pin
count devices are appropriate for applications like a cordless
PC mouse and trackball.

68HC05 C-Family. This group of microcontrollers has
proven useful as a general-·purpose device for
communications applications.
68HC05 E-Family. Like the 68HC05 B-Series devices
E-Series devices are ideal for number storage and keyboard
interrupt applications.
68HC05 F-Family. These devices - except for the F5,
which features an integrated DTMF receiver - include an
on-chip Dual-Tone Multi-Frequency Generator (DTMG) for
digital transmission and reception, as well as an LED drive for
user information. These features make the F-Family suitable
for a number of telecommunications applications, including
auto dialing, number storage, and display control.
68HC05 J- and P-Families. These low pin count,
low-cost
microcontrollers
have
a
variety
of
telecommunications uses, with features ranging from
EEPROM to multifunction timers.
68HC05 L-Family. With its large LCD driving capability
and low power consumption, this series is well-suited to
applications in hand-held communication equipment. The
on-chip tone generator and display functions can be used in
pager systems to alert users to incoming messages.

Consumer
68HC05 C- and D-Families. The multiple communication
lines (I/O ports, SCI and SPI) and free-running timer in this
group of devices make it possible to execute several tasks in
parallel. These features are used in consumer products like
CD players, automotive entertainment systems, and remote
controls.
68HC05 J-, K-, and P-Families. The free-running timer
in these cost-effective microcontrollers allows multitasking in
applications such as washing machines, oven controls, and
remote controls.
68HC05 L-Family. These low-power, small-footprint
devices can drive large LCD displays, making them ideal for
hand-held consumer products like portable CD players.

Industrial
68HC05 B-Family. On-chip features include EEPROM;
8-channel, 8-bit AID converter; and Pulse Length Modulated
outputs. Typical industrial applications include Programmable
Logic Controllers (PLC) and data acquisition systems.
68HC05 C- and D-Families. These general-purpose
devices can be used in applications such as process control
systems where multiple I/O lines and LED outputs are
required.
68HC05 J- and P-Families. These devices are popular in
low-cost industrial applications such as smoke detectors,
security devices, thermostats, and furnace ignition systems.
68HC05 L-Family. Multi-port controllers with LCD driver,
16-bit timer and watchdog timer on board. Excellent for
display panels requiring tone output and low power
consumption such as thermostats and alarms.
68HC705MC4. This device is intended for use in industrial
motor control and power supply applications.
68HC05 X-Family. These devices have Controlled Area
Network (CAN) controllers with 4K thru 32K ROM for
integrated messaging on factory automation, sensor, and
switch applications.

Television and Video
68HC05 B-Family. These devices are ideal for EEPROM
storage, with 256 bytes of EEPROM to store TV or satellite
channel frequencies and preset volume or brightness levels.
Features include Analog-to-Digital (AID) conversion and
PWM.
68HC05 C- and D-Families. With up to 32K of user ROM,
these devices can be used in the television and video market
as general-purpose microcontrollers.
68HC05 CC-Family. Evolved from the T-Series,
CC-Series devices feature closed-caption Data Slicer (DSL)
and enhanced OSD features for decoding and displaying
closed captions.
68HC05CO. This device has no on-chip user ROM, but is
capable of addressing up to 64K of external memory, making
it ideal for applications that require large amounts of operating
code, like televisions. The 12C bus module and 4 MHz internal
bus speed also allow interconnection with standard TV
peripherals.
68HC05 K- and RC-Families. These devices are used in
remote control applications.
68HC05 T-Family. All T-Family devices have On Screen
Display (OSD) modules that can overlay graphical images
onto television screens. They also contain D/A converters that
can drive analog outputs like volume control, and AID
converters that can be used to automatically adjust the fine
tuning. Some members of the T-Series have 12C interfaces
that can communicate with industry-standard TV peripherals.

Telecommunications
68HC05 B-Family. These devices can
store
user-programmable telephone numbers in 256 bytes of
non-volatile EEPROM memory. They can also communicate
with analog inputs like battery life in hand-held equipment,
using the AID module. The D/A module can be used to control
analog outputs such as telephone volume and line cards.

Motorola Master Selection Guide

2.5-3

Single-Chip Microcontrollers (CSIC)

«

0::

USER ROM-1248 BYTES

LU

I(JJ

a

LU

0::

USER RAM - 64 BYTES

z

0

F
()

«

b:
0

a.

LU

0::

is

~

'"

PA7'
PA6'
PAS'
PA4'
PA3"
PA2"
PAl"
PAO"

'8 rnA SINK CAPABILITY
"EXTERNAL INTERRUPT CAPABILITY

CPU CONTROL

ARITHMETIC/LOGIC
UNIT
ACCUMULATOR

IRQ
M68HCOS
MCU

RESET

11 111 11 1

1

11 111 1 11

LU

1

t;:;

a

LU

0::
Z

STACK POINTER

101010101010101011111

H)

2ch
(IH:>H)

24 Vo

t/

Comments

Packages
56SDIP-B
52 PLCC-FN
64QFP-FU

8i
20

MC68HC05B6

6K

176

256

l6-bit:
(2IC,20C)

8CI+

8ch
(IH:>H)

2ch
(IH:>II)

24 Vo
8i
20

t/

On-Chip Charge Pump
EEPROM Write Protect

56SDIP-B
52 PLCC- FN
64QFP-FU

MC6BHC05B8

7.2SK

176

256

16-bil:
(2IC,20C)

SCI+

8ch
(IH:>H)

2ch
(IH:>II)

24 Va
8i
20

t/

On-Ghip Charge Pump
EEPROM Write Protect

56SDIP-B
52 PLCC- FN
64QFP-FU

MC6BHC05B16

15K

352

256

l6-bit:
(2IC,20C)

SCI+

Bch
(IH:>H)

2ch
(IH:>H)

24 Va

t/

On-Ghip Charge Pump
EEPROM Write Protect

S6SDIP-B
52 PLCC-FN
64 QFP- FU

16ch
(lH:>it)

24 Va

t/

Horizontal and Vertical Sync
Signal Processor

t/

KBI (8 pins)
1 High Current Pin (5 rnA sink)
Mask Option Pullups
High Speed Option (HSCOSC4A)
Low Power Option (HCLOSC4A)
(1.8 V minimum)

40 DIP- P
44 PLCC-FN
44 QFP- FB
42SDIP-B

8i
20

MC68HCOSBD3

3.7SK

12B

MFT, RTI

12C

MC6BHC05C4A

4K

176

16-bit:
(1IC, WC)

SPI
SCI

24 Vo

16-blt:
(1IC,10C)

SlOP

32 Vo

t/

8 High Current Pins (10 rnA
sink) LV?I, On-Chip Charge
Pump

40DIP-P
44 PLCC-FN

16-blt:
(1IC,10C)

SPI
SCI

24 Vo

t/

KBI (8 pins)
1 High Current Pin (5 rnA sink)
Mask Option Pullups
High Speed Option (HSC05CBA)
Low Power Option (HCL05CBA)
(1.8 V minimum)

40DIP-P
44 PLCC- FN
44 QFP- FB
42SDIP-B

MC68HC05C5

5K

176

MC68HC05C8A

BK

176

128

7i

7i

40DIP-P
42SDIP-B

MC68HC05C9A

16K

352

l6-bit:
(1IC, WC)

SPI
SCI

24 Va
7i

t/

KBI (B pins)
1 High Current Pin (5 rnA sink)
Mask Option Pullups
High Speed Option (HSC05C9A)
Low Power Option (HCL05C9A)

40DIP-P
44 PLCC-FN
44QFP-FB
42 SDIP- B

MC68HC05C12

12K

176

16-bit:
(1IC,10C)

SCI
SPI

24 Vo

t/

1 High Current Pin (20 rnA sink)
KBI (8 pins)
Mask Option Pullups (8 pins)
High Speed Option (HSC05C12)
Low Power Option (HCL05C12):
(1.8 V minimum)

4ODIP-P
44 PLCC-FN
44QFP-FB
42 SDIP-B

IH:>H:
Pulse
Accum.
MFT

12C

MC6BHCOSCC1

16K

544

MC68HC05CC2

31.5K

92B

IH:>H:
Pulse
Accum,
MFT

12C

MC68HC05CJ4

4K

224

16-bit:
(1IC, WC)
MFT

SPI
SCI
12C

MC68HC05D9

16K

352

11H:>H:
(1IC.10C)

SCI

MC68HC05D24

24K

352

16-b~:

7i

1 ch
(5-bH)

(6-b~)

1 ch
(5-bit)

8ch
(IH:>H)

32K

352

16-bH:
(1IC,1OG)

MCBBHC05E1

4K

368

MFT. RTI

MCBBHC05E6

6K

12B

160

Single-Chip Microcontrollers (CSIC)

16-bit:
(1IC, WC)
MFT, RTI

OSD
(127 Char
ROM)

31 Vo

Closed Caption Television
NTSC Data Slicer w/int Sync Sep
28 MHz PLL
8 Open Drain 1/0 Pins, 5 V Only

40 DIP-P
42SDIP-B

OSD
(127 Char
ROM)

31 ilo

Closed Caption Television
NTSC Data Slicer wlint Sync Sep
32 MHz PLL
8 Open Drain 1/0 Pins, 5 V Only

42SDIP-B
40DIP-P

24 Va

t/

12C (Slave Only)

44 QFP- FB

Sch
(6-bit)

31 Vo

t/

8 High Current Pins (25 rnA sink)
30 kHz PWM

40DIP-P
44 PLCC- FN

SCI

5ch
(6-bit)

31 Va

t/

8 High Current Pins (24 rnA sink)
30kHz PWM

4ODIP-P
44PLCC-FN

SCI

5ch
(IH:>H)

31 Vo

t/

8 High Current Pins (24 rnA sink)
30 kHz PWM

40 DIP-P
44 PLCC-FN

201/0

t/

32 kHz PLL Clock Synthesizer

28DIP-P
28S0IC-DW

32 i/o
4i

t/

KBI (B pins)
Pin for Extemal LVI

44 QFP- FB
2BSOIC-DW

(1IC.10C)
XC6BHCOSD32

8ch

4ch
(8-bH)

2.5-6

Motorola Master Selection Guide

Table 5. 68HC05 Microcontrollers (continued)
Motorola
Part

EEPROM
(Bytes)

Display
Drive

ROM
(Bytes)

RAM
(Bytes)

MC68HC05F5

5K

224

MFT, RTI

MC68HC05F6

4K

320

16-bit:
(1IC, WC)

SPI

26 ilo
4I
20

MC68HC05F8

8K

320

16-bit:

SPI

50 ilo

Number

Timer

Serial

AID

PWM

(1IC, WC)

I/O

COP

30 ilo
11

01

Mask IRQ

42SDIP-B
44QFP - FB

01

DTMF Generator
KBI (8 pins)
Manchester Encoder/Decoder
a High Current Pins (10 rnA sink)

64 QFP - FU

40 i/o
8I

01

32 kHz PLL - Standby modes

56SDIP-B
64 QFP - FU

48 i/o
16 i

01

KBI (8 pins)
Dual Oscillators - Selectable
Clock
Dual IRQ

80 QFP- FU

20

auto
8K

16-bit:
(1IC, WC)

176

SPI

4 ch
(8--bit)

Dual
SPI

8 ch
(8--bll)

Packages
40 DIP - P
44 PLCC - FN

DTMF Generator
8 High Current Pins (10 rnA sink)
KBI (6 pins)

16-bit:
MC68HC05G1

Comments
DTMF Receiver

RTC

MC68HC05G3

24K

768

16-bit:
(1IC, WC)
B-bit:
Event Cntr

4 ch
(8-btt)

40

12K

64

MFT, RTI

14 i/o

01

KBI (4 pins)
4 High Current Pins (8 rnA sink)
Mask Option Pulldowns (14 pins)
High Speed Version (HSC05J 1A)
Low Power Version (HCL05J1A):
(1.8 V minimum)

20 DIP - P
20S0IC-OW

MC68HC05J3

2K

128

16-bit:
(1IC, tOC)
MFT, RTI

14 ilo

01

14 High Current Pins (8 mA sink)
KBI (4 pins)

20DIP-P
20S01C- DW

MC68HC05KO

O.5K

32

MFT, RTI

10 i/o

01

4 High Current Pins (8 mA sink)
Programmable Pulldowns
(10 pins)
Low Voltage Reset Mask Option
Low power version (HCL05KO):
(1.8 V minimum)

16 DIP - P
16S0IC-DW

MC68HC05K1

O.5K

32

MFT, RTI

10 ilo

01

4 High Current Pins (8 mA sink)
PEP (64 bits)
Programmable Pulldowns
(10 pins)
Low Voltage Reset Mask Option

16DIP-P
16 SOIC-DW

XC68HC05K3

920

64

MFT, RTI

10 i/o

01

KBI (4 pins),
Programmable Pulldowns
(10 pins)
4 High Current Pins (8 mA sink)
On-Chip Charge Pump
1.8 V Operating Voltage

16 DIP - P
16S0IC-DW

MC68HC05L1

4K

128

l6-bit:
(2IC,20C)

6 ch
(8--bit)

64 Segment
LCD:
(3/4 x 12116)

17 i/o
15 i
20

MC68HC05L2

2K

96

16-bit:
(tlC,IOC)
MFT, RTI

I ch
(8--bit)

45 Segment
LCD:
(3 xiS)

13 i/o

01

Programmable Pullups (13 pins)

42SDIP-B

MC68HC05L5

8K

256

16..-.bit:
(1IC, tOC)
RTI
B-bit:
(1IC,10C)

SlOP

156 Segment
LCD:
(1-4 x 27-39)

14 ilo
10i
150

01

KBI (8 pins), Dual Oscillators
8 High Current Pins (10 mA sink)
Programmable Putlups (24 pins),
Open Drain (31 pins), 2.2 V

80 QFP - FU

MC68HC05L7

6K

176

16-bit:
(tiC, WC)
RTC

SCI

960 Segment
LCD:
(8116 x 60)

15 i/o

Mux EBI (13..-.bit Address),
32 kHz PLL, KBI (8 pins),
LVI Tone Generator

128 QFP - FT
Die

MC68HC05L9

6K

176

16-bit:
(1IC,10C)
RTC

SCI

640 Segment
LCD:
(8116 x 40)

27 i/o
2I

Mux EBI (16..-.bit Address),
32 kHz PLL, KBI (8 pins),
LVI Expand LCD to 3K Segments
w/68HC68L9, Tone Generator

128 QFP - FT
Die

MC68HC05L 10

13K

352

l6-bit:
(lIC,10C)
RTC

SPI
SCI

5K - 20K Pixel
LCD

28 ilo

Mux EBI w/MMU (20-bit
Address)
4 Chip Selects, KBI (8 pins)
Tone Generator/OTMF, 32 kHz
PLL
LCD Expansion w/MC141511

128 QFP- FT
Die

MC68HC05J1A

16 PEEP

Motorola Master Selection Guide

2.5-7

56SDIP-B
64 QFP - FU

Single-Chip Microcontrollers (CSIC)

Table 5. 68HC05 Microcontrollers (continued)
Motorola
Part
Number
MC68HC05L 11

MC68HC05L 16

ROM
(Bytes)

RAM
(Bytes)

3K

448

16K

EEPROM
(Bytes)

512

Timer

Serial

16-bit:
(1IC, toC)
RTC

SPI
SCI

l6-bit:
(1IC, toG)
RTI
8-bil:
(1IC, toG)

SlOP

MC68HC05M4

4K

128

l6-bit:
(1IC, toC)
8-bit
Modulo

MC68HC05P1A

2K

128

16-bit:
(1IC, laC)

MC68HC05P3

3K

128

MC68HC05P4

4K

176

128

PWM

Display
Drive
Up to 4QK
Pixel LCD

110

COP

38 i/o

Comments
Mux ESI w/MMU {23-bit

Packages
100 QFP- FU

Address)
4 Chip Selects, KBf (8 pins)
Tone Generator/DTMF, 32 kHz
PLL
LCD Expansion with MC141512
+ MC141514

156 Segment
LCD:
(1-4 x 27-39)

16 i/o
8i
150

'"

KBI (8 pins), Dual Oscillators
8 High Current Pins (10 rnA sink)

80QFP-FU

Programmable Pullups (24 pins)
Open Drain (31 pins), 2.2 V
Operation

6 ch
(8--lJit)

VFD (24 lines)

l6-bit:
(1IC, toG)
MFT, RTI
16-bit:
(1IC, laC)

SlOP

MC68HC05P6

4.5K

176

16-bit:
(1IC, toG)

SlOP

MC68HC05P7

2K

128

16-bit:
(1IC, toC)

SlOP

MC68HC05P8

2K

112

MC68HC05P9

2K

128

l6-bit:
(1IC, toG)

MC68HC05PEO

2K

128

l6-bit:
(tiC, toG)

XC68HC05RC16

16K

350

Infrared
Timer

MC68HC05SCll

6K

128

MC68HC05SC21

6K

128

MC68HC05SC24

3K

MC68HC05SC27

32

AID

MFT, RTI

4 ch
(8-bit)

32 i/o
8i

'"

20 ilo
Ii

'"

2 High Current Pins (20 mAl

22 i/o

'"

KBI (6 pins)
On-Chip Charge Pump

28 DIP - P
28 SOIC-DW

20 i/o
Ii

'"

High Speed Option

28DIP-P
28S0IC-DW

20 Vo
Ii

'"
'"

20 ilo
Ii

4 ch
(8--bit)

16 i/o
4i

4 ch
(8-bit)

20 i/o
Ii

5 V Only

52 PLCC- FN

KBI (8 pins)

28 DIP - P
28 SOIC-DW

Mask Option Pullups (8 pins)

(68HSC05P4)
Low Power Option
(68HCL05P4):
(1.8 V minimum)

28 DIP- P
28 SOIC-DW
28 DIP- P
28S0IC-DW
28DIP-P
28S0IC-DW

'"
'"

LVPI Option on EEPROM
On-Chip Charge Pump

20 ilo

'"

1 High Current Pin (20 mA sink)
PEP (64 bits), KBI (8 pins)
Mask Option Pulldowns (8 pins)
RC Oscillator Option

28DIP-P
28 SOIC- DW

12 i/o

'"

Mask Option Pullups (12 pins)
KBI (12 pins), Low Power Stop
Pin

28 DIP- P
28 SOIC- DW

5 i/o

Security Features, 8K EPROM
Smartcard Applications, 5 V Only

Die
16DIP-P
20S0IC-DW

3K

5 i/o

Security Features
On-Chip Charge Pump
Smartcard Applications

Die
16DIP-P
20S0IC-DW

128

lK

5 ilo

Security Features
On-Chip Charge Pump
Smartcard Applications

Die
16DIP-P
20S0IC-DW

16K

240

3K

5 ilo

'"

Security Features
On-Chip Charge Pump
Smartcard Applications
High Speed Option

Die
l6DIP-P
20 SOIC-DW

XC68HC05SC28

12K

256

8K

5 i/o

'"

Security Features,
On-Chip Charge Pump
Smartcard Applications
High Speed Option

Die
44 PLCC- FN

MC68HC05Tl

8K

320

16-bit
(1IC, lOG)

SlOP

1 ch
(6--bit)

9 ch
(6--bit)

OSD
(64 Char
ROM)

29 ilo
Ii

Open Drain PWM Outputs
5 V Only

40 DIP- P
42 SDIP- B

XC68HC05T2

15K

320

l6-bit:
(1IC, toC)

SlOP

1 ch
(6-bit)

9 ch
(6-bit)

OSD
(64 Char
ROM)

29 ilo
Ii

'"
'"

Open Drain PWM Outputs
5 V Only

40 DIP- P
42SDIP-B

MC68HC05Tl0

12K

320

l6-bit:
(1IC, toG)
RTC

12C

1 ch
(8--lJit)

8 ch
(&-bit)
1 ch
(14--lJit)

OSD
(64 Char
ROM)

20i/o
4i

Open Drain PWM Outputs
KBI (8 pins)
5 VOnly

56SDIP-B

Single-Chip Microcontrollers (CSIC)

SlOP

2,5--8

28DIP-P
28 SOIC-DW

Motorola Master Selection Guide

Table 5. 68HC05 Microcontrollers (continued)
Motorola
Part
Number
MC68HC05T16

ROM
(Bytes)

RAM
(Bytes)

24K

320

EEPROM
(Bytes)

Timer

Serial

AID

PWM

16--bit:

12C

2ch
(5-bil)

9 ch
(7-bn)
1 ch
(14-hit)

(1IC,20C)
8-bitPAC

Display
Drive
OSO
(128 Char
EPROM)

VO

COP

40 Vo

tI'

Comments
12 V Open Drain 1/0 lines
(up to 22)

Packages

56 SDlP-B

4 row aso buffer

Timer output compare functions
do not have output pins

MC68HC05X1

12K

336

16--bit:

SSI

24 i/o

tI'

KBI (8 pins)
SAE Jl850 Serial Mux Interface
5 V Operation Only

44 PLCC-FN

16 i/o

tI'

CAN (Controller Area Network)
KBI (t6 pins)

28S0IC-OW

64QFP-FU

(1IC,20C)
MFT, RTI

l6-bit:
(1IC, tOC)
MFT, RT!

MC68HC05X4

4K

176

MC68HC05X16

15K

352

255

16-bit:
(2IC,20C)

SCI+

8ch
(8-bit)

2 ch
(8-bit)

32 i/o

tI'

CAN (Controller Area Network)
KBI (8 pins)
EEPROM Write Protect

MC68HC05X32

32K

528

255

16-bit:
(2IC,20C)

SCI+

8ch
(8-bit)

2 ch
(8-bit)

32 i/o

tI'

CAN (Controller Area Network)
KBI (8 pins)
EEPROM Write Protect

On-Chip Charge Pump

64QFP-FU

On-Chip Charge Pump

Motorola Master Selection Guide

2.5-9

Single-Chip Microcontrollers (CSIC)

ONE-TIME PROGRAMMABLE (OTP) I EMULATOR MCUs
All 68HC705 products have a standard operating voltage range from 3 V to 5.5 V unless noted in Comments.
All 68HC705 products have a standard operating temperature range from 0 - 70°C.
Contact a Motorola Sales Office for availability of extended temperature versions.

Table 6. One-Time Programmable (OTP)/Emulator MCUs
Motorola
Part

EPROM
(Bytes)

RAM
(Byles)

MC68HC70585

6K

176

MC68HC705B16

15K

352

Number

EEPROM
(Bytes)

255

Serial

AID

PWM

16-blt:
(2IC,20C)

SCI+

8ch
(S-bit)

2ch
(S-bit)

24 Va
8i
20

16-bit:

SCI+

8ch
(8-bit)

2ch
(8-bit)

32 Va

8ch
(8-bit)

2ch
(S-bit)

32 Vo

16ch
(S-bit)

24i1o

(2IC,20C)
XC68HC705B32

32K

528

MC68HC70SBD3

7.75K

256

MC68HC705C4A

4K

255

176

Display
Drive

11mer

16-bit:
(2IC,20C)

SCI+

MFT, ATI

12C

16-bit:
(1IC,10C)

UO

20

24 i/o

SPI
SCI

7i

COP

Comments

'"
'"
'"
'"

Programmable Pul1downs
(16 pins)
EPROM Write Protect

'"

Mask Option Register Pullups
(8 pins)
KBI (8 pins)

On-Chip Charge Pump
EEPROM Write Protect

52PLCC-FN
*52 Cerquad-FS
64 QFP- FU

On-Chip Charge Pump
EEPROM Write Protect

52 PLCC-FN
56SDIP-B
64QFP- FU

Horizontal and Vertical Sync
Signal Processor

8K

304

16-bit:
(1IC,10C)

SPI
SCI

24 i/o
7i

'"

42 SDIP-B
*42 Cersdip - K

40DIP-P
*40Cerdip-S

1 High Current Pin (20 rnA sink)
EPROM Security
MC68HC705CBA

Packages
56SDIP-B
52PLCC-FN

Mask Option Pullups (8 pins)
KBI (8 pins)
1 High Current Pin (20 rnA sink)
High Speed Option (HSC705C8A)

Superset of ROM GSA with more
RAM

40 DIP- P
44PLCC-FN
42 SDIP-B
44 QFP- FB
40 DIP- P
44PLCC-FN
*40 Cerdip-S
42 SDIP- B
44 QFP- FB
*44 Cerquad - FS

EPROM Security

MC68HC705C9A

16K

352

1S-b.:
(1IC,1OC)

SPI
SCI

31 ilo

'"

Mask Option Pullups (8 pins)
KBI (8 pins)
1 High Current Pin (20 rnA sink)
EPROM Security

40 DIP- P
"40 Cerdip-S
"44 Cerquad-FS
44PLCC-FN
42 SDIP- B
44QFP-FB

MC68HC705CJ4

4K

224

16-bit:
(1IC,10C)
MFT

SPI
SCI
12C

29 Vo
3i

8 High Current Pins (lOrnA sink)
12C (Slave Only)

44QFP-FB

XC68HC705D9

16K

352

16-bit:
(1IC,1OC)

SCI

8 High Current Pins (25 rnA sink)
30 kHz PWM

40DIP-P
'44 Cerquad- FS
44 PLCC- FN

MC68HC705E1

4K

368

MFT, ATC
RTI

'"
'"
'"

XC68HC705F6

4K

320

16-bit:
(1IC,10C)

SPI

26 Vo
4i

MC68HC705F8

8K

320

16-bit:
(1IC.1OC)
16-bit:
auto

SPI

50 ilo
20

MC68HC705G1

12K

176

16-b.:
(1IC,1OC)
ATC

SPI

4 ch
(8-bit)

MC68HC705G4

32K

1024

16-bit:
(1IC,10C)
6-bit:
Event Cntr

Dual
SPI

8ch
(S-bit)

MC68HC705J1A

MC68HC705J2

5ch
(6-bit)

31 Vo

20 Vo

4ch
(S-bit)

32 kHz PLL Clock Synthesizer

*28Cerdip-S
28 DIP- P
28S0IC-DW

DTMF Generator
8 High Current Pins (10 rnA sink)
KBI (6 pins)

42 SDIP- B
*42 Cersdip - K
64 QFP-FU
'64CQFP-FZ

'"

DTMF Generator
KBI (8 pins)
8 High Current Pins (10 rnA sink)
Manchester Encoder/Decoder

64 QFP-FU
'64CQFP-FZ

40 Vo
8i

'"

32 kHz PLL

56SDIP- B
*56 Cersdip - K
64QFP- FU
'64 CQFP- FZ

48Vo

'"

KBI (8 pins)
Dual IRQ
Dual Oscillators, Selectable Clock

80QFP-FU
'80CQFP-FZ

KBI (4 pins), EPROM Security
Feature
4 High Current Pins (8 rnA sink)
Mask Option Pulldowns (14 pins)

20DIP-P
20SOIC-DW
'20 Cerdip-S

16i
40

1.2K

64

MFT, RTI

14 Vo

'"

2K

112

MFT. ATI

14 Vo

'"

Single-Chip Microcontrollers (CSIC)

2.5-10

20DIP-P
2OSOIC-DW
*20Cerdip-S

Motorola Master Selection Guide

Table 6, One-Time Programmable (OTP)/Emulator MCUs (continued)
Motorola
Part
Number
MC68HC705K1

EPROM
(Bytes)

RAM
(Bytes)

0.5K

32

EEPROM
(Bytes)

Timer

Serial

AID

Display
Drive

PWM

"0
10 Vo

MFT, RTI

COP

Comments

Packages

'"

4 High Current Pins (8 rnA sink)
PEP (64 bits)

16DIP-P
16S0IC-DW

Programmable Pulldowns (10 pins)

*16Cerdip-S

Low Voltage Reset Mask Option

XC68HC705L1

6K

16-bit:
(2IC,20C)

128

64 Segment

6 ch
(8-bn)

LCD:
(314 x 12116)

17 ilo
15i
20

56SDIP-B
64 QFP- FU
'64CQFP-FZ
*56 Cersdip - K

MC68HC705l5

MC68HC705L16

8K

16K

256

512

16-bit:
(1IC, WC)
RTI
8-bit:
(1IC, WC)

SlOP

16-1>~:

SlOP

156 Segment
LCD:
(1-4 x 27-39)

14 i/o
10 i

KBI (8 pins), Dual Oscillators
8 High Current Pins (10 rnA sink)

SOQFP-FU
'SOCQFP-FZ

Programmable Pullups (24 pins)

150

Open Drain (31 pins)

156 Segment
LCD:
(1-4 x 27-39)

(HC,10C)
RTI

16 ilo
8i
150

'"

KBI (8 pins), Dual Oscillators

B High Current Pins (10 rnA sink)
Programmable Pullups (24 pins)

80QFP- FU
'SO CQFP- FZ

Open Drain (31 pins)

8-I>~:

(HC, WC)
MC68HC705P6

4.5K

16--bit:

176

SlOP

(HC, WC)
MC68HC705P9

MC68HC705T10

2K

12K

128

320

16--bit:
(HC, WC)

SlOP

l6-bit:
(HC, WC)
RTC

12C

16-1>~:

12C

4ch

20 ilo

(8-1>0)

1;

4ch

20 ilo
1i

(a-b~)

1 ch
(8-1>~)

OSD
(64 Char
EPROM)

20 ilo

OSD
(128 Char
EPROM)

40 i/o

8ch
(6-1>it)
1 ch

'"

28DIP-P
2BS01C-DW
*28 Cerdip - S

'"

28DIP-P
28SOIC-DW
"'28 Cerdip-S

Open Drain PWM Outputs

4i

KBI (8 pins)

56 SDIP-B

*56 Cersdip - K

5 V Only

(14-b~)

MC68HC705T16

24K

320

2ch

(HC,20C)
a-bit PAC

(5-bIT)

9 ch
(7-1>it)
1 ch
(14-bit)

'"

12 V Open Drain 110 Lines
(Up to 22)
4 Row aso Buffer
Timer output compare functions

"

LVR, On Chip Charge Pump,

56 SDIP- B
*56 Cersdip - K

do not have output pins
XC68HC705V8

12K

512

128

16-1>~:

SPI

8ch
(B-b~)

(HC, WC)
MFT, RTI
XC68HC705X4

4K

176

1 ch
(6-1>it)

22 ilo

16i1a

16-bit:
(HC, WC)
MFT, ATI

'"

MOLe (Message Datalink
Control)

56 SDIP-B
68 PLCC- FN
68CLCC-FS

5 V Regulator, KBt (16 pins)

56 Cersdip - K

CAN (Controller Area Network)

28SOIC-DW

KBI (16 pins)

"

'Wlndowed packages available only In sample quantities.

Package Definitions

Definitions
CAN
CCTV
COP
DTMF
EBI
IC
12C
IDE

-

ilo
i

-

KBI
LCD
LVI
LVPI
LVR
MDLC

MFT

-

Controller Area Network
Closed Caption Television
Computer Operating Properly (Watch Dog Timer)
Duat-Tone Multi-Frequency
External Bus Interface
Input Capture
Inter-Integrated Circuit
Integrated Device Electronics (18M PCIAT Type)
Bidirectional Input and Output Port Pins
Input Only Port Pins
Key Board Interrupt
Liquid Crystal Display
low Voltage Interrupt
Low Voltage Program Inhibit
Low VoHage Reset
Message Data Link Controller (J1850)
Multi Function Timer
Output Only Port Pins

Motorola Master Selection Guide

oc
OSD
PEEP
PEP
PIO
PLL
PWM
RTC
RTI
SCI
SCI+
SIO
SlOP
SPI
VFD
VREG
WDOG

-

Output Compare
On-Screen Display
Personality EEPROM
Personality EPROM

-

Parallel Input Output (IBM PC/AT Type)

-

Phase-Lock Loop
Pulse-Width Modulation
ReaJ-TIme Clock
Real-Time Interrupt
Serial Communications Interface (asynchronous)
Serial Communications Interface (async. and sync.)

-

Serial Input Output (IBM PC/AT Type)

-

Simple Serial 1/0 Port
Serial Peripheral Interface
Vacuum Fluorescent Display
Voltage Regulator
Watch Dog TImer

2,5-11

8
DW
FA
FB
FE
FN
FS

FT
FU
FZ

K
L

P
S

-

Shrink DIP (70 mil spacing)
Small Outline (Wide-Body SOIC)
7 x 7 mm Quad Flat Pack (OFP)
10 x 10 mm Quad Flat Pack (OFP)
CQFP (windowed) - Samples Only
Plastic Quad (PLCC)
CLCC (windowed) - Samples Only
28 x 28 mm Quad Flat Pack (QFP)

-

t 4 x 14 mm Quad Flat Pack (QFP)

-

COFP (windowed) - Samples Only
Cersdip (windowed) - Samples Only
Ceramic Sidebraze
Dual-in-Line Plastic
Cerdip (windowed) - Samples Only

Single-Chip Microcontroliers (CSIC)

MCU NEW PRODUCTS
All 68HCOS and 68HC70S products have a standard operating voltage range from 3 V to S.S V unless noted in Comments.
All 68HCOS and 68HC70S products have a standard operating temperature range from 0 to 70°C.
Contact a Motorola Sales Office for availability of the following MCUs:

Table 7. MCU New Products
Motorola
Part
Number

RaMI
EPROM
(Bytes)

RAM
(Bytes)

EEPROM
(Bytes)

68HCOSB32

32K

528

256

BBHCOSBD5

7.7SK

68HC05CO

68HCOSE16

Display
Drive

Timer

Serial

AID

PWM

va

COP

16-bit:
(2IC,20C)

SCI+

8ch
(B-bit)

2ch
(B-btt)

32 Vo

II'

On--Chip Charge Pump
EEPROM Wrne Protect

256

MFT, ATI

12C

16ch
(B-btt)

24 i/o

II'

Horizontal and Vertical Sync Signal
Processor

0

512

16-bit:
(lIC, lOG)
MFT

SCI+

18 Vo

II'

Mux or Non-Mux EBI (16-bit)
3 Chip selects, KBI (8 pins)
Programmable Pullups (8 pins)
1 High Current Pin (20 rnA sink)

44PLCC-FN
40 DIP- P
42 SDlP-B

16K

352

320

16-btt:
(2IC,20C)
MFT, RT1

Dual
12C

47 Vo
2i

II'

KBI (8 pins)
LVI
32 kHz Programmable PLL
Perodic Interrupt (0.25, 0.5, 1 s)

440FP-FB
64 OFP- FU
56SDIP-B

64

920
16PEEP

MFT, ATI

10ilo

II'

KBI (4 pins), Programmable
Pulldowns (10 pins), 4 High Current
Pins (8 rnA sink), On-Chip Charge
Pump, 1.8 V EE Read

16DIP-P
16S0IC-DW

20 Vo

II'

KBI (8 pins)
2 High Current Pins
(15mA sink)

28 DIP- P
28S0IC-DW

20ilo

II'

KBI (8 pins)

28 DIP- P
28S0IC-DW

68HC80SK3

68HCOSP7A

2K

128

68HC05P9A

2K

128

16-bit:
(1IC,10C)

SlOP

16-bit:

SlOP

(1IC,10C)
BBHCOSSC26

6K

224

1024

68HC05V7

10K

384

128

68HC705E5

5K

68HC705MC4

4ch
(B-blt)

4 ch
(B-bH)

2 High Current Pins
(15 mAsink)

4ODIP-P
42 SDIP-B

Silo

II'

Smartcard Security Features
On-Chip Charge Pump
High Speed Option

die
44PLCC-FN

22 ito
16i

II'

MDLC (Message Datalink Control)
5 V Power Regulator
KBI (16 pins)
LVR

56SDIP-B
BBPLCC-FN

20 Vo

II'

32 kHz PLL Clock Synthesizer

28 DIP- P
'28 Cerdip-S
28S0IC-DW

22 i/o

II'

1 8-Bit High Current Port
(10 mA Source Pin, 20 mA Max/Port)
1 High Sink Current Pin (10 mAl
Low EMI Pinout
Commutation Mux for PWM
Industrial Motor Control

28DIP-P
'28 Cerdip - S
28S0IC-DW

SPI

384

MFT, ATI

12C

3.5K

176

16-bit:
(2lCor
lIC,10C)
MFT, ATI

SCI

68HC705RC16

16K

350

Infrared
Timer

12 ilo

II'

Mask Option Pullups (12 pins)
KBI (12 pins)

28DIP-P
'28 Cerdip - S
28S0IC-DW

68HC70SRC17

16K

350

Infrared
Timer

12 ito

II'

Mask Option Pullups (12 pins)
KBI (12 pins)
Phase-Locked Loop (PLL)

28DIP-P
*28 Cerdip - S
28S0IC-DW

68HC705SR3

4K

192

8-bitTimer
(7-hit
prescaler)

Mask Option Pullups (24 pins)
KBI (8 pins), LED Drive (8 pins), LVR

40DIP-P
*40 Cerdip - S
42SDIP-B
440FP-FB

68HC70SX32

32K

528

BBHC08XL36

36K

68HC708XL36

36K

2 hi sp
(B-bH
24kHz
Max)

24 Vo

4ch
(B-bit)

32 Va

II'

CAN (Controller Area Network)

640FP-FU

SCI
SPI

43 Vo

II'

8 MHz Intemal Bus (5 V)
Direct Memory Access Module (3 ch)
Programmable PLL, LVIILYR
KBI (8 pins),
Programmable Pullups (8 pins)

56SDIP-B
640FP-FU

SCI
SPI

43 Vo

II'

8 MHz Internal Bus (5 V)
Direct Memory Access Module (3 ch)
Programmable PLL, LVI/LVR
KBI (8 pins),
Programmable Pullups (8 pins)

56SDIP-B
*56 Cersdip - K
64 OFP-FU
'64CQFP-FE

16-bit:
(21C,20C)

SCI+

lK

4 ch 16-bit:
(IC,OC,or
PWM)

lK

4 ch 16-bit:
(IC,OC,or
PWM)

Single-Chip Microcontrollers (CSIC)

6ch
(B-bit)

1 ch
(6-bit)

Packages
52PLCC-FN
56SDIP-B
640FP-FU

lB-bH:
(lIC, lOC)
MFT, RTI

255

8ch
(8-bH)

Comments

8ch
(B-bit)

2ch
(8-bit)

2.5-12

Motorola Master Selection Guide

M68HC08 Family

V"-~

The M68HC08 Family offers a unique combination of
high-speed, low-power, enhanced processing performance
for cost-sensitive 8-bit applications. Full upward object code
compatibility with the world's leading 8-bit microcontroller
allows current M68HC05 users to leverage their resource and
time investment. M68HC08 modular design utilizes a growing
library of on--chip peripherals. The flagship 68HC(7)08X36
OTP and ROM versions for general purpose use are the first
two devices in the family.

i'rrv'

~::>

Features

SERIAL
COMMUNICATIONS
INTERFACE

RAM

• Architecturally Enhanced 8-Bit CPU
• 8 MHz bus speed yields 125 ns minimum instruction
cycle
• 18-bit stack with stack pointer operations and
addressing modes
• 16-bit index register
• 78 new instructions including advanced looping control
• Eight new addressing modes
• Fully upward object code compatible with the M68HC05
and M6805 families
• Direct Memory Access Module
• Memory-ta-memory transfer
• Peripheral-ta-memory and memory-ta-peripheral
transfer
• Timing Interface Module
• Four independently programmable channels
• Input capture, output compare, buffered, and
unbuffered PWM configurations
• Interface Modules
• Serial Communications Interface (UART)
• Serial Peripheral Interface
• System Interface Module
• System Control Modules
• Low Voltage Inhibit, PLL, COP, and System
Integration Module
• Clock Generator Module
• Generates two different clock signals from a
user-selected source

Motorola Master Selection Guide

SERIAL
PERIPHERAL
INTERFACE

ROM/EPROM

K==>
TIMING
INTERFACE
MODULE

CPU08

e

CLOCK
GENERATOR
MODULE

~r

(

V
SYSTEM
CONTROL
MODULE

DIRECT
MEMORY
ACCESS
MODULE

Figure 3. Block Diagram of Typical M68HC08 MCU

2.5-13

Single-Chip Microcontrollers (CSIC)

process. Or, create an MMDS system to add
high-performance, advanced emulation features such as
real-time, dual-ported memory and a real-time bus state
analyzer with an 8K trace buffer. In addition, the MMDS
includes a built-in power supply and is fully enclosed in a
metal case. Both the MMEVS and MMDS include a
host-based Integrated Development Environment (IDE)
comprised of an editor, assembler, and hardware debugger.

M68HC05 Microcontroller
Development Tools
Motorola now offers two fully modular development system
choices: the new Motorola Modular Evaluation System
(MMEVS) and our popular, high-performance Motorola
Modular Development System (MMDS). You can now build a
customized MMEVS or MMDS to emulate the MCU in your
target design in four simple steps. First, order the MMEVS or
MMDS system platform (M68MMPFB0508 or M68MMDS05).
Second, select and order the emulation module (EM) that
contains circuitry specific to emulating the particular HC05/08
MCU in your target application. Third, complete the system by
ordering target cable accessories to connect the MMEVS or
MMDS to your target MCU socket. Finally, select the
appropriate parallel programmer to program your prototype
devices.

Modular Architecture Benefits
The MMEVS replaces Motorola's older-style EVS and
EVM development tool products. A proper subset of the
MMDS architecture, the new MMEVS is fully compatible with
all EM products supported by the MMDS. The MMEVS
extends the emulation performance beyond that of the EVS
and EVM by supporting full, real-time, non-intrusive,
in-circuit emulation for the new high-speed devices
(68HSC05) in the HC05 Family and the new HC08
architecture. The MMEVS also extends emulation support to
all low-voltage HC05/HC08 derivatives. The common
hardware, firmware, and software design of the MMEVS and
MMDS also provide greater flexibility in mixing and matching
Motorola hardware tools with the ever-increasing variety of C
compilers, assemblers, and integrated development
environment product offerings from Motorola's third party
developer companies.

Choosing Between the MMEVS
and MMDS
Build an economical MMEVS system to perform traditional
debugging activities such as executing code in run or step
mode; setting breakpoints; monitoring or modifying CPU
registers, memory and application variables; and creating log
or script files to record test results or automate the testing

CONFIGURATION AND ORDER INFORMATION FOR MMDS/MMEVS
Table 8. Configuration and Order Information for MMOSIMMEVS
In-Circuit Target Cable
Devices

Platform

Emulation
Modules

68HC05A16
68HC705A24

M68MMPFB0508 QB
M68MMDS05

M68EM05A24

68HC05B4IB6/B8/B161B32
68HC705B5/B161B32

M68MMPFB0508 OR
M68MMDS05

M68EM05B32

68HC05BD3IBD5
68HC705BD3IBD5

M68MMPFB0508 OR
M68MMDS05

M68EM05BD3

68HC05BS8
68HC705BS8

M68MMPFB0508 OR
M68MMDS05

M68EM05BS8

68HC05CO

M68MMPFB0508 QB
M68MMDS05

M68EM05CO

68HC05C5
68HC705C5

Package Type

Low Noise
Flexcable

Target Head
Adapter

56SDIP- B

M68CBL05B

M68TB05A24B56

56 SDIP- B

M68CBL05B

M68TB05B32B56

640FP-FU

M68CBL05C

M68TC05B32FU64

52 PLCC-FN

M68CBL05C

M68TC05B32FN52

40 DIP-P

M68CBL05B

M68TB05BD3P40

42SDIP-B

M68CBL05B

M68TB05BD3B42

440FP- FB

M68CBL05C

M68TC05BS8FB44

52 PLCC-FN

M68CBL05B

M68TB05BS8FN52

40 DIP-P

M68CBL05B

M68TB05COP40

42 SDIP-B

M68CBL05B

M68TB05COB42

44PLCC-FN

M68CBL05

M68TC05COFN44

440FP- FB

M68CBL05C

M68TC05COFB44

Surface Mount
Adapter

M68TOS064SAGIt
M68TOP064SAIt

M68TOS044SAGlt
M68TOP044SAMOIt

M68TOS044SAGlt
M68TOP044SAMOIt

Refer to the Configuration and Order Information for Other Motorola Development Tools Section to select a development tool for
the 68HC05C5/68HC705C5.

Single-Chip Microcontrollers (CSIC)

2.5-14

Motorola Master Selection Guide

Table 8. Configuration and Order Information for MMDSIMMEVS (continued)
In-Circuit Target Cable
Platform

Devices

68HC05C4IC4A1C8A1C12A
68HC705C4A1705CBA

68HC05C9/C9A
68HC705C9

M68MMPFB0508 QE!
M68MMDS05

M68MMPFB0508 Q.B
M68MMDS05

Emulation
Modules
M68EM05C9

M68EM05C9

Package Type

Low Noise
Flexcable

Target Head
Adapter

40 DIP-P

M68CBL05B

M68TB05C9P40

44PLCC-FN

M68CBL05C

M68TC05C4FN44

440FP- FB

M68CBL05C

M68TC05C9FB44

42SDIP-B

M68CBL05B

M68TB05C9B42

40 DIP-P

M68CBL05B

M68TB05C9P40

44PLCC-FN

M68CBL05C

M68TC05C9FN44

42SDIP-B

M68CBL05B

M68TB05C9B42

44 OFP-FB

M68CBL05C

M68TC05C9FB44

Surface Mount
Adapter

M68TOS044SAG1t
M68TOP044SAM01t

M68TOS044SAG1t
M68TOP044SAM01t

68HC05CCV
68HC705CCV

Refer to the Configuration and Order Information for Other Motorola Development Tools Section to select a development tool for
the 68HCOSCCV/68HC705CCV.

68HC05CJ4
68HC705CJ4

M68MMPFB0508 QE!
M68MMDS05

M68EM05CJ4

68HC05D9/D241D32

M68MMPFB0508 OR
M68MMDS05

M68HC05D32EM

68HC705D9

68HC05E6
68HC705E6

68HC05F4
68HC705F4

68HC05F6
68HC705F6

M68MMPFB0508 OR
M68MMDS05

M68MMPFB0508 QE!
M68MMDS05

M68MMPFB0508 OR
M68MMDS05

M68EM05E6

M68EM05F4

M68EM05F6

440FP- FB

M68CBL05C

M68TC05CJ4FB44

M68TOS044SAG1t
M68TOP044SAM01t

40DIP-P

M68CBL05B

M68TB05C9P40

44PLCC-FN

M68CBL05C

M68TC05C9FN44

44 OFP- FB

M68CBL05C

M68TC05C9FB44

M68TOS044SAG1t
M68TOP044SAM01t

28S0IC-DW

M68CBL05C

M68TC05E6P28

M68DIP28S0lC

440FP-FB

M68CBL05C

M68TC05E6FB44

M68TOS044SAG1t
M68TOP044SAM01t

M68TC05E6P28

28 DIP-P

M68CBL05C

28S0IC-DW

M68CBL05C

M68TC05E6P28

M68DIP28S0lC

44 OFP-FB

M68CBL05C

M68TC05E6FB44

M68TOS044SAG1
M68TOP044SAM01t

42 SDIP-B

M68CBL05B

M68TB05F6842

440FP-FB

M68CBL05C

M68TC05F6FB44

M68TOS044SAG1t
M68TOP044SAM01t

64 OFP- FU

M68CBL05C

M68TC05F6FU64

M68TQS064SAG1t
M68TQP064SAM01t

68HC05F8
68HC705F8

Refer to the Configuration and Order Information for Other Motorola Development Tools Section to select a development tool for
the 68HC05F8I68HC705F8.

68HC05G1
68HC705G1

M68MMPFB0508 QE!
M68MMDS05

M68EM05G1

68HC05G3
68HC705G4

M68MMPFB0508 OR
M68MMDS05

M68EM05G4

68HC05J1
68HC705J2

M68MMPFB0508 QE!
M68MMDS05

M68HC05JPEM

68HC05J1A
68HC705J1A

M68MMPFB0508 OR
M68MMDS05

M68EM05J1A

68HC05J3
68HC705J3

M68MMPFB0508 OR
M68MMDS05

M68EM05J3

68HC05KO/K1/K3
68HC705K1

M68MMPFB0508 QE!
M68MMDS05

M68EM05K3

68HC05L1
68HC705L1

M68MMPFB0508 QE!
M68MMDS05

M68EM05L1

68HC05L2
68HC705L2

M68MMPFB0508 QE!
M68MMDS05

M68HC05L2EM

Motorola Master Selection Guide

56 SDIP- B

M68CBL05B

M68TB05G1 B56

64QFP- FU

M68CBL05C

M68TC05G1 FU64

M68TOS064SAG1t
M68TQP064SAM01t

80 OFP- FU

M68CBL05E

M68TE05G4FU80

M68TQS080SBG1t
M68TOP080SBM01t

20DIP-P

M68CBL05A

M68TA05J2P20

20S0IC-DW

M68CBL05A

M68TA05J2P20

20 DIP-P

M68CBL05A

M68TA05J2P20

20S0IC-DW

M68CBL05A

M68TA05J2P20

M68DIP20S0lC

20DIP-P

M68CBL05A

M68TA05J2P20

M68DIP20S0lC

20S0IC-DW

M68CBL05A

M68TA05J2P20

M68DIP20S0lC

16 DIP-P

M68CBL05A

M68TA05K1 P16

16S0IC-DW

M68CBL05A

M68TA05K1 P16

M68DIP16S0lC

56 SDIP-B

M68CBL05B

M68TB05L1B56

M68TQS064SAG1t

640FP-FU

M68CBL05C

M68TC05L1FU64

M68TOP064SAM01t

42 SDIP-B

42-SDIP ribbon cable assembly included with M68HC05L2EM.

2.5-15

Single-Chip Microcontrollers (CSIC)

Table 8. Configuration and Order Information for MMDSJMMEVS (continued)
In-Circuit Target Cable
Devices

Platform

Emulation
Modules

Package Type

Flexceble

Target Head
Adapter

Surface Mount
Adapter

M68EML05L16

80 QFP- FU

M68CBL05E

M68TEOSL16FU80

M68TQS080SBG1t
M68TQP080SBM01t

Low Noise

68HC05L5IL16
68HC70SLS/L 16

M68MMPFB0508 OR
M68MMDSOS

68HCOSL7/L9
68HC705L10
68HCOSL11
68HCOSM4

Refer to the Configuration and Order Information for Other Motorola Development Tools Section to select a development tool for
the 68HCOSL7/L9, 68HCOSL 10, 68HC05L11, or 66HCOSM4.

68HCOSP3

M68MMPFBOS08 OR
M68MMDSOS

M68EMOSP3

28 DIP-P

M68CBLOSA

M68TAOSX4P28

28S0IC-DW

M68CBLOSA

M68TAOSX4P28

28 DIP- P

M68CBLOSA

M68TAOSP8P28

28S0IC-DW

68HC05P8

M68MMPFB0508

M68HCOSJPEM

M68CBLOSA

M68TAOSP8P28

68HC05P1/P4IP6/P7/P9
68HC70SP6/70SP9

M68MMPFBOS08 OR
M68MMDSOS

M68HC05P9EM
(Included with
MMDS)

28 DIP-P

M68CBLOSA

M68TAOSP9P28

28S0IC-DW

M68CBL05A

M68TAOSP9P28

M68EM05RC16

28 DIP- P

M68CBL05A

M68TA05RC16P28

28S0IC-DW

M68CBLOSA

M68TA05RC16P28

68HC05RC16
68HC705RC16

M68MMPFB0508 OR
M68MMDS05

68HC05SC11/SC21/SC241
SC27

CONTACT
SALES OFFICE
M68EM05SR3

M68DIP28S0lC

M68DIP28S0lC

M68DIP28S0lC

M68DIP28S0lC

ISO Adapter Included w/EM.

die/card
40 DIP-P

M68CBL05B

M68TB05SR3P40

44 QFP- FB

M68CBL05C

M68TC05SR3FB44

42SDIP-B

M68CBL05B

M68TB05SR3B42

68HC05SR3
68HC705SR3

M68MMPFB0508 OR
M68MMDS05

68HCOST11T2

Refer to the Configuration and Order Information for Other Motorola Development Tools Section to select a development tool for
the 68HC05T11T2.

68HC05T10
68HC70ST10

M68MMPFB0508 QB
M68MMDS05

M68EM05T7

68HCOSV7
68HC70SV8

M68MMPFBOS08 OR
M68MMDS05

M68EMOSV8

68HCOSX4
68HC70SX4

M68MMPFBOS08 OR
M68MMDSOS

M68EM05X4

68HC05X16/X32
68HC70SX32

M68MMPFBOS08 OR
M68MMDSOS

M68EML05X32

56SDIP-B

M68CBL05B

M68TQS044SAG1t
M68TQP044SAM01t

M68TB05T7B56

56 SDIP-B

M68CBLOSB

M68TBOSV8BS6

68 PLCC- FN

M68CBLOSB

M68TBOSV8FN68
M68TA05X4P28

28DIP-P

M66CBL05A

28S0IC-DW

M68CBLOSA

M68TAOSX4P28

M68DIP28S0lC

64QFP-FU

M68CBLOSE

M68TE05X32FU64

M68TQS064SAG1t
M68TQP064SA1t

..

• Development tools that are scheduled for availability dUring 1Q96.
t To support more than one QFP target system, separate purchase of additional TQPACKs is required. Contact your Motorola representative for details.
Each QFP target head includes one TQSOCKET with guides (M68TQSOxxSyG1) and one TQPACK disposable surface mount adapter (M68TQPOxxSy1 (1.2 mm lead
length) or M68TQPOxxSyM01 (1.6 mm lead length». Order additional TQSOCKETs and TQPACKs using part numbers referenced in the Surface Mount Adapters
column to support multiple target systems. Contact your Motorola representative for details.

Single-Chip Microcontroliers (CSIC)

2.5-16

Motorola Master Selection Guide

CONFIGURATION AND ORDER INFORMATION FOR OTHER MOTOROLA
DEVELOPMENT TOOLS (EVM/EVS/ICS)
Table 9. Configuration and Order Information for Other Motorola Development Tools (EVM/EVSJICS)
In-Circuit Target Cable

Low Noise
Devices
68HC05C5
68HC705C5

68HC05CCV
68HC705CCV

68HC05J1A
68HC705J1A

Comments

M68HC05C5EVS

40 DIP-P

Not Available

For DIP package user must
supply a ribbon cable assembly
to interlace to user's target
system.

44 PLCC- P

Not Available

For PLCC package, user has
the option to order
44PLCC05M, which is the
old-iltyle ribbon cable assembly
with PLCC target adapter.

Order
M68HC05CCVEM
and M68HC05PFB

M68HC705JICS

M68HC705KICS

Flexcable

Surface Mount
Adapter

Package Type

42 SDIP-B

M68CBL05B

M68TB05CCVB42

44 QFP- FB

M68CBL05C

M68TC05CCVFB44

20 DIP- P
20S0IC-DW

68HC05KO/KI
68HC705Kl

Target Head
Adapter

Development Tool

16 DIP-P
16S0IC-DW

M68TQS044SAGIt
M68TQP044SAMOlt

20 DIP Ribbon Cable Assembly Included With M68HC705JICS
M68DIP20S0lC

See Above

16 DIP Ribbon Cable Assembly Included With M68HC705KICS
See Above

M68DIP16S0lC

M68HC705KICS In-Circuit
Simulator
For the SOIC package, user
may order M68DIP20S0IC,
which is a 2o-pin DIP to SOIC
adapter.
M68HC705KICS In-Circuit
Simulator
For the SOIC package, user
may order M68DIPI 6S01C,
which is a 16 pin DIP to SOIC
adapter.

68HC05L7/L9

M68HC05L9EVM2

128QFP-FT

Not Available

68HC05Ll0

M68HC05L 1OEVM

128QFP-FT

Not Available

68HC05Lli

M68HC05LtI EVM

100QFP-FU

Not Available

68HC05M4

M68HC05M4EVM

52 PLCC-FN

Not Available

For PLCC package, user has
the option to order 52PLCCU,
which is the old-style ribbon
cable assembly with PLCC
target adapter.

68HC05Tt IT2

M68HC05T2EVS

40 DIP- P

Not Available

For DIP/SDIP package, user
must supply a ribbon cable
assembly to intertace to user's
target system.

Motorola Master Selection Guide

42 SDIP-B

Not Available

44 PLCC- FN

Not Available

2.5-17

For PLCC package, user has
the option to order
44PLCC05M, which is the
old--iltyle ribbon cable assembly
with PLCC target adapter.

Single·Chip Microcontroliers (CSIC)

CONFIGURATION AND ORDER INFORMATION FOR PROGRAMMERS
Table 10. Configuration and Order Informat/on for Programmers
Devices

Comments

Packages Supported

Programmer Boards

52 PLCC- FN
56SDIP-B

M68HC05BPGMR

For QFP package, order M68HC705X32PGMR.

40 DIP- P
42SDIP-B

M68HC705UPGMR

M68HC705UPGMR requires package adapter.
For 40 DIP - P, order M68UPA05BD3P40.
For 42 SDIP - B, order M68UPA05BD3B42.

68HC705C4NC5IC8/C8NC9

40 DIP-PIS
44 PLCC - FNiFS

M68HC05PGMR-2

Order M68ADT05P40FB44 adapter to program
44QFP-FB.

68HC705D9

40 DIP-PIS
44 PLCC - FNiFS

M68HC05PGMR-2

Order M68ADT05P40FB44 adapter to program
44QFP-FB.

68HC705E6

44QFP-FB
28S0IC-DW

M68HC705E6PGMR

68HC705F6

64 QFP - FU/FZ
42SDIP-B/K

M68HC705F6PGMR64

68HC705F8

64 QFP - FU/FZ

M68HC705F8PGMR

68HC705G1

56SDIP-B
64QFP-FU

M68HC705G1 PGMR

68HC705J1A

20DIP-P

M68HC70SJICS

M68HC705JICS In-<:ireuit simulator.
SOIC requires user supplied socket or adapter. (Available
from Yamaichi, part number IC51-Q282-334-1)

68HC705J2IJ3

20 DIP-PIS

M68HC70SJ2PGMR

SOIC requires user supplied socket or adapter. (Available
from Yamaichi, part number IC51-Q282-334-1)

68HC705K1

16DIP-P/S

M68HC705KICS
M68HC705K1GANG

M68HC705K1 GANG Programs up to 8 68HC705K1 S or P.

16S0IC-DW··

M68HC705K1 GANGY

M68HC705K1GANGY Programs up to 8 68HC705K1 S, P,
or OW.

68HC705L1

56 SDIP-BIK
64 QFP - FU/FZ

M68HC705L1PGMR

68HC705L5/L16

80 QFP - FU/FZ

M68HC705L5PGMR

28DIP-P
28S0IC-DW

M68HC705E6PGMR

68HC705B5IB161B32
68HC705BD3

68HC705P3
68HC705P6IP9

28 DIP-PIS

M68HC705P9PGMR

68HC705SR3

40 DIP- P
42 SDIP-B
44QFP-FB

M68HC05SR3PGMRSG

68HC705T10

56 SDIP-B/K

M68HC705T10PGMR

68HC705X4

28 DIP-PIS
28S0IC-DW

M68HC705X4PGMR

68HC705V8

56 SDIP-B
68PLCC-FN

M68HC705V8PGMR

68HC705X32

64QFP-FU
68 PLCC-FN

M68HC705X32PGMR

SOIC requires user supplied socket or adapter.
M68HC05SR3PGMRSG requires package adapter.
For 40 DIP - P, order M68HC05SR3PAP40.
For 42 SDIP - B, order M68HC05SR3PAB42.
For 44 QFP - FB, order M68HC05SR3PAFB44.

..
'Development tools that are scheduled for availability dunng 1096.
··SOIC on M68HC705K1 GANGY only.

Single-Chip Microcontroliers (CSIC)

2.5--18

Motorola Master Selection Guide

THIRD PARTY DEVELOPERS FOR 68HC05 AND 68HC705 FAMILY MCUs
Table 11. Third Party Developers for 68HCOS and 68HC70S Family MCUs

I

Programmers

Sunrise Electronics

USA
USA

Advin Systems Inc.

USA

System General
Corporation

Canada:
Eastern
Western
France
Germany
UK
Hong Kong
Ascend Systems Inc.

USA
Austria!
Germany
France

BP Microsystems

USA
Canada
UK
France
Germany
Hong Kong
Tokyo

Bytek

USA
Netherlands,
UK, Belgium
France
Germany
Hong Kong

Circuit Equipment
Corporation

USA
UK
France

Data 110

USA
Canada
France
Germany
Hong Kong
Japan
Netherlands
UK

E.E. Tools Inc.

Emulation
Technology, Inc.

USA
Canada
Mexico
France
Germany
Japan
France
USA
UK
Germany

(408)243-7000
(800)627-2456
(514) 337-0723
(604) 986-1286
+3313961-1414
+497459-1271
+44 1332-32651
(852)833-5188
(510) 606-2000
(800) 541-3526
+432772-54581

TECI (The Engineers
Collaborative Inc.)

USA

Tribal Microsystems, Inc. USA
Asia

(510) 623-8859
886-2-764-0215

Vel Electronic

+49851-751427

Germany

ICElEvaluation Boards

+33148619528
(800) 225-2102
(713) 688-4600
(905) 602-8550
+441280-700262
+3316941-2801
+49-8856-832616
852-234-166-11
81-3-3817-4980

American Arium

USA

Ashling Microsystems

USA

France
Germany
Dr. Krohn & Stiller

Germany
UK
USA

Emulation Technology,
Inc.

France
USA
UK
Germany

iSystem GmbH

(216) 951-8840
+44 1734-575666
+336185-5767
(206) 88Hl444
(800) 426-1045
(905) 678-Q761
+35 80502-3300
+33-31956-8131
49-89-858-580
81-3-3779-2151
+31-402-582-911
+44-1734-440011
(408) 734-8184

Nash Electronics

USA

Needham's Electronics

USA

(501) 289-6111
(916) 924-8037

Germany
USA

+441628-773070
+3314666-2750
+49 8233-32681
+49896100-0022
+441235-861461
(320) 617 9400
+3316941-2801
(408) 982-0660
+44 1234-266455
+441962-733140
+49 89460-2071
+498104-7044
+498131-25083
(408) 982-0660
(Emulation
Technology Inc)

France

+3362-072-954
(ISIT Societe)

MetaLink Corporation

USA
UK
Canada
Hong Kong
Germany
France

(602) 926-0797
+441491-455907
(613) 226-2365
896-2-501-6699
+498091-55950
+331-39-3956-8131

Orion Instruments

USA
Canada

(408) 747-0440
(416) 609-8396

France

+331-30-54-2222

(Multitest Elect Inc.)

52-5-705-7422
+33 16930-2880
+49 89834-3047
81-538-322822
+3316941-2801
(408) 982-0660
+44 1234 266455
+441962-733140
+49 89-4602071
+4981-047044
(800) 331-7766

(508) 366-3220

. UK

+33 16930-2880
496181-75041
852 29198282

USA

(714) 731-1661
(Eastern Systems)

(407) 994-3520
+3116248-Ql00

Logical Devices

Motorola Master Selection Guide

Japan
France
Germany

(909) 595-7774
(800) 967-4776
(408) 263-6667
81-3-3441-1510
+332015-1133
+41 1982-2050
(800)-336-8321
(802) 525-3458

(BSO France SA)
Pentica Systems

USA
UK
Germany

Sophia Systems

Japan
USA

Vel Electronic

Germany

Yokogawa Digital
Computer Corp

Japan
USA

(800) PENTICA
(617) 275-4419
+44 0734-792101
+497147-3085
(044) 989-7000
(800) 824-9294
+4985175-1427
81-422-56-9101
(408) 747-0400
(Orion Instruments)

2.5-19

Single-Chip Microcontrollers (CSIC)

AssemblerslLinkers/Debuggers
2500 Software Inc.

USA
France

UK

(719) 395-8683
+33 7443-8045
(CK Electronique)
+336185-1914
(Societe L.S.I.T.)
+44 1364-654100
(Greymatter)
+4417183-31022
(System Science)

American Arium

USA

(714) 731-1661

Archimedes Software,
Inc.

USA

(206) 822-8300

Avocet Systems, Inc.

USA

(207) 236-9055
(800) 448-8500

BSOTasking

USA
France
UK
Germany

(617) 894-7800
(800) 458-8276
+33 1-3054-2222
+441252-510014
+49 71-5222090

Byte Craft Ltd.

USA

(519) 888-6511

Cosmic Software

USA
Europe/lntnl
UK

(617) 932-2556
+33 143-995390
+44 1734-880241

HIWARE

USA

(206) 827-4832
(Archimedes)
+33 16013-3668
(CK Electronique Avnet
Group)
+4161331-7151
(HIWARE)
+497031-2895-38
(Diessner)
+44 1734-792101
(Pentica)
+44 1962-733140
(Nohau)
81 3-3293-4716
(Lifeboat)

France

Germany

UK

Japan
IAR Systems

Introl Corp.

USN
Canada
Germany
UK
France
Hong Kong
Japan
USA
UK
France

Japan
Germany

Single-Chip Microcontrollers (CSIC)

P & E Microcomputer
Systems, Inc

USA

(617) 353-9206

PseudoCorp

USA

(541) 683-9173

Software Development
Systems (SDS)

USA
UK
Japan
Asia-Pac.
Germany

(708) 368-0400
+44 1442-876065
+81 (0) 3 3493 7981
+61 (0) 3 720 5344
+49 2534-800170
(H S PGmbH)

TECI (The Engineers
Collaborative Inc.)

USA

(802) 525-3458
(800) 336-8321

Compiler/Real-Time Kernel
Archimedes Software,
Inc.

USA

(206) 822-6300

Avocet Systems, Inc.

USA

(207) 236-9055
(800) 448-8500

BSO Tasking

USA
France
UK
Germany

(617) 894-7800
(800) 458-8276
+33 1-30542222
+44 1252-510014
+49 71-5222090

Byte Craft Ltd.

USA

(519) 888-6511

Cosmic Software

USA
Europe/lntnl
UK

(617) 932-2556
+33 143-995390
+44 1734-880241

Embedded System
Products, Inc.

USA
Europe

(713) 728-9688
+33-143-995-390
(Cosmic Software)

Hi-Tech
(distributed by Avocet
in USA)

UK
Germany

+44-0734-792-101
(Pentica)
+49-7147-3085
(Pentica)

HIWARE

USA
France

(415)-765-5500
Germany
+49 89470-6022
+44 171924-3334
+1-39-61-14-14
2687-1931
03-293-4711
(Lifeboat)

UK

(414) 327-7171
(800) 327-7171
+44171-8331022
(System SCience)
+33 7443-8045
(CK Electronique)
+33 14622-9988
(Micro Sigma SA)
(81) 3 256 5881
(Soft Mart Inc.)
+49 81 04-9074
(Lauterbach GmbH)

Japan

2.5-20

(206) 827-4832
(Archimedes)
+33 16013-3668
(CK Electronique Avnet
Group)
+4161331-7151
(HIWARE)
+497031-2895-38
(Diessner)
+441734-792101
(Pentica)
+44 1962-733140
(Nohau)
81 33293-4716
(Lifeboat)

Motorola Master Selection Guide

Miscellaneous Software and Hardware Support
AMP Incorporated

Canada
Mexico
Europe
Asia/Pacific

(717) 564-0100
(800) 522-6752
(905) 475-6222
(525) 729-0400
+44 1753-676-800
(81) 44-613-8502

Aptronix
(fuzzy logic dev.)

USA

(408) 428-1888

McKenzie (now part of
Berg Electronics)
(adapters, sockets)

USA
Germany

(510) 6512700
+4989150-1001

France

+33 14594-1424

UK

+44 1295-271777

USA

(sockets)

Emulation
Technology, Inc.
(adapters)

France
USA
UK
Germany

+3316941-2801
(408) 982-0660
+44 1234 266455
+441962-733140
+49 89-4602071
+4981-047044

USAR Incorporated
(keyboard encoders)

USA

(212) 226-2042

Yamaichi Elec. Inc.
(sockets)

USA

(408) 456-0797

(Infratron GmbH)
(Green Components)
(Toby Electronics)

+441501-44434
(Neltronic Ltd.)

Motorola Master Selection Guide

2.5-21

Single-Chip Microcontrollers (CSIC)

On-Line Help
Freeware Bulletin Board

CSIC Microcontroller Division
World Wide Web Site
http://design-net.com/csiclCSIC_home.html
The CSIC WWW pages provide a direct line to the latest
information and software for 68HC05 and 68HC08
microcontrollers. The web site provides access to:

The Freeware Data Services are now mirrored on the CSIC
WWW site for easy access. Customers unable to access the
Internet can still access the Freeware development software
and applications software by dial-up modem at 2400 to 9600
baud. To log in:
1. Make sure to set character format to 8-bits, no parity,
1 stop bit

The Latest News and Press Releases

2. Dial (512) 891-FREE (512-891-3733)

Product, Market, and Development Tool Overviews

3. Follow directions from the system

On-Line MCU and Development Tool Selector Guides

The Freeware files are also accessible by anonymous FTP
server:

On-Line Datasheets and Application Notes

freeware.aus.mot.com
(use email address for password)

Development Tool Software Upgrades
Free Development Software
Applications Software
3rd Party Development Tool Information
On-Line Technical Support

Single-Chip Microcontrollers (CSIC)

2.5-22

Motorola Master Selection Guide

Single-Chip
Microcontrollers (AMCU)

In Brief ...
Page
M68HCll Family ............................... 2.6-2
Modular Microcontroller ........................ 2.6-12
The M68HC16 Family ....................... 2.6-14
The M68300 Family ......................... 2.6-19
Development Tools ........................... 2.6-23
Fuzzy Logic .................................. 2.6-26
On-Line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2.6-26
Third-Party Support ........................... 2.6-27

Motorola offers the most comprehensive selection of
high-performance single-chip control systems available
from a single source. Microcontroller device families range
from industry-standard 8-bit controllers to state-<>f-the-art
16- and 32-bit modular controllers. Within the price and
performance categories of each family, there are a variety of
on-chip capabilities to match specific applications.
Motorola device families are structured so that upward
migration need not involve complete code development.
The M68HC11 Family is upward code compatible with
M6800 and M6801 software, while the M68HC16 family is
source-code compatible with the M68HC11 family.
Motorola's newest 8-bit MCU product line, the M68HC08
family, is fully upward object code compatible with the
M68HC05 and M6805 families. In addition, M68300 and
M68HC16 devices share standard internal modules and
bus configurations.

Motorola Master Selection Guide

2.6-1

Single-Chip Microcontrollers (AMCU)

M68HC11 Family
The M68HC11 Family incorporates a flexible central
processing unit and a large number of control-oriented
on-chip peripherals. M68HC11 MCU are upward code
compatible with M6800, M6801, and M68HCOS software.

eight input channels, and most offer 8-bit resolution, although
some provide 1G-bit resolution. A 2 channel, 8-bit DIA is also
available.

Pulse-Width Modulation

Central Processing Unit
The M68HC11 CPU is optimized for low power
consumption and high-performance operation at bus
frequencies up to 4 MHz. Key features include:
• Two 8-bit or one 16-bit accumulator
• Two 16-bit index registers
• Powerful bit-manipulation instructions
• Six powerful addressing modes
• Immediate, Extended, Direct, Indexed, Inherent, and
Relative
• Power saving STOP and WAIT modes
• Memory mapped 1/0 and special functions
• 16x16 Integer and Fractional Divides
• 8x8 Multiply

Some M68HCII Family members have up to six channels
of 8-bit PWM. At a 4 MHz bus frequency, signals can be
produced from 40 KHz to less than 10Hz. PWM signals with
a period greater than one minute are possible in the 16-bit
mode.

Serial Communication

M68HC11 timer architecture is based on a 16-bit free
running counter driven through a software-programmable
prescaler. Features include multiple Input Captures, Output
Compares, Real-Time Interrupt, Pulse· Accumulator, and
Watchdog functions.

All members of the M68HCll Family include a Serial
Peripheral Interface (SPI) and a Serial Communications
Interface (SCI). These on--chip peripherals are designed to
minimize CPU intervention during data transfer.
• The SCI is a full duplex UART-type asynchronous
system that uses standard Non-Return-to-Zero (NRZ)
data format. An on-chip Baud rate generator derives
standard rates from the microcontroller oscillator. Both
transmitter and receiver are double buffered.
• The SPI is a four-wire synchronous communications
interface used for high-speed communication with
specialized peripheral devices and other microcontrollers.
Data is transmitted and received simultaneously; the
Baud rate is software programmable.

On-Chip Memory

Digital

Since its introduction, the M68HC11 Family has provided
versatile combinations of popular memory technologies,
including the first EEPROM on a CMOS microcontroller. The
family has a memory option to fit virtually any application.
• ROM sizes range from 0 to 32K bytes. ROM is typically
factory programmed to contain custom software.
ROMless versions of most M68HC11 Family members
are also available.
• RAM sizes range from 192 bytes to 1.2SK bytes.
M68HCII RAM utilizes a fully static design, and all
devices feature a standby power supply pin for battery
back-up of RAM contents.
• EPROM sizes range from 4K to 32K bytes. EPROM is
especially suited to prototype development and small
production runs. EPROM versions are available in both
windowed and OTP packaging.
• EEPROM sizes range from 0 to 2K bytes. EEPROM is
ideal for storage of calibration, diagnostic, data logging,
and security information. Each M68HC11 device with
EEPROM includes an on-chip charge pump to facilitate
single-supply programming and erasing.

M68HC11 Family I/O is extremely flexible, allowing pins to
be configured to match application requirements. Most I/O
lines are controlled by bits in a Data Direction Register (DDR)
which can configure pins for either input or output. Most lines
have a dedicated port data latch.
Some M68HC11 Family members include a 4--channel
Direct Memory Access (DMA) and a Memory Management
Unit (MMU). The DMA provides fast data transfer between
memories and registers, and includes externally mapped
memory in the expanded mode. The MMU allows up to 1
megabyte of address space in a physical 64 kbyte allocation.
Integrated chip selects help to reduce glue logic.
Several members of the M68HC11 Family also include
programmable chip select circuits. These circuits can be used
to enable external peripherals whenever an access to a
predefined block of memory addresses is made. These
circuits help to reduce extemallogic requirements.

Timer

Digital-to-Analog Conversion
The M68HCII Family provides powerful, on-chip,
multi-channel AID converter systems. Multi-conversion and
multi--channel options allow single or continuous conversion
on single or multiple channels. M68HC11 AID systems have

Single-Chip Microcontrollers (AMCU)

2.6-2

va and .Special Functions

Math Coprocessor
New M68HCll Family members offer a 16-bit on--chip
math coprocessor that accelerates multiply and divide
operations by as much as 10 times. The coprocessor
functions independently of the CPU and requires no special
instructions. The coprocessor is well-suited to low-bandwidth
DSP functions such as closed loop control, servo positioning,
and signal conditioning.

Motorola Master Selection Guide

PULSE ACCUMULATOR

0

ROM-8K BYTES
TIMER

PERIODIC INTERRUPT
RAM-2S6 BYTES

COP WATCHDOG

EEPR0M-512 BYTES

PE7
PES
PES
PE4
PE3
PE2
PE1
PEO

I
L

()

PAl
OC2
OC3

-0:

Ii:

OC4
OCS
IC1
IC2
IC3

~

PA7
PA6
PAS
PA4
PA3
PA2
PA1
PAO

SPI

PDS
PD4
PD3
PD2

SCI

PD1
PD~

UJ

Ii:
0
a..

ND
CONVERTER
M68HC11 CPU

VRH
VRL
RESET
XIRQ
IRQ

XTAL
EXTAL
E
M.QQA
(LlR)
MODB
(VSTBY)

r

I
I
I
I
I
I
I
I
I
I
I

I

a.. a.. a.. a.. a.. a.. a.. a..

~~~~~~~~

1-1-

~-------------------~~

Figure 4. MC68HC11A8 Block Diagram

Motorola Master Selection Guide

2.6-3

Single-Chip rVlicrocontroliers (AMCU)

MODA
(LlR)

MODB
(VSTBY)

XTAL EXTAL

E

IRQ

RESET

INTERRUPT
LOGIC

MODE CONTROL

TIMER
SYSTEM

XIRQ

12 KBYTES ROM

EEPROM 512 BYTES

M68HC11 CPU

RAM 512 BYTES

L

SERIAL
COMMUNICATION
INTERFACE
SCI

VDD

Vss

I
...L

....--_---l

-VRH
-

VRL

AID CONVERTER

~

C>

00
0.. 0..

,....., ->Il:z
00
0..0

~

OC1
OC2/0C1
OC3/0C1
OC4/0C1
IC4/0C5/0C1
IC3
IC2
IC1

I

CHIP
SELECT

r--

~g

>- fIl:z
00
0..0

CSO-CS10
BR
BG
BGACK
FCO
FC1
FC2

I---

GPT

SIM

"--

RXD
TXD
PCSO/SS
PSC1
PSC2
PSC3
SCK
MISO
MOSI

-

r - - r---

U

ADAO
ADA1
ADA2
ADA3
ADA4
ADA5
ADA6
ADA7

DSACKO
AVEC
PF3
OS

EBI

VRH
VRL

Ai':

1MB

0--'

b:g:

~8

--

R/W

r-r-

ADC

A

SRAM

IR011:71

CPU16

--'
Ou..

Il:f>-Il:
Zo
80..

MODCK

~~

CLOCK

DSCLK
DSO
DSI
IPIPE1
IPIPEO
BKPT

TEST

~

I

VSTBY

2.6-14

TSC
TSTME
QUOT

-

Figure 7. MC68HC16Z1 Block Diagram

Single-Chip Microcontroliers (AMCU)

OS
AS
SIZO
SIZ1

~

ADAO
ADA1
ADA2
ADA3
ADA4
ADA5
ADA6
ADA7

~

0
Il:
fZ
0
0

DSACK1
AVEC

~~

'--

IPIPEO/DSO
IPIPE1/DSI
BKPTlDSCLK

Il:ff-Il:
Zo
00..
0

[)i':Ar.KO

DATA [0:15]

~

--'

--'
Ow

_SilO
SIZ1

~

...:0

-~

DS~CK1

--

-

ADDR 0:18

-'

VDDA
VSSA

-

OSM

~-

VSS

--'

0
Il:
>-0
z>Oil:
00
0..

ArR119:23]

TXD
PCSO
PSC1
PSC2
PSC3
SCK
MISO
MOO
SS

VDD

~

BRiCSO
BGlCS1
BGACKlCS2
FCO/CS3
FC1/GS!
FC2/CS5
ADDR19/CSfi
ADDR20/W
ADDR21/.csa
ADDR22LCS9
ADDR23/CS10

FREEZE

r-

RESET
HA
BERR
MODCK
IR01
IR02
IR03
IR04
IR05
IR06
IRQ7
CLKOUT
XTAL
EXTAL
XFC
VDDSYN

--

TSTMEfTSC
FREEZE/OUOT
--'

0
Il:
fz
0
0

-

Motorola Master Selection Guide

CSBOOT

PWMA
PWMB
PCLK
PAl
IC1IPGPO
IC2IPGPl
IC3/PGP2
OCl/PGP3
OC2IOC1/PGP4
OC3/0Cl/PGP5
OC4/0Cl/PGP6
IC4/0C5/0Cl/PGP7

,,,---'

(!:lo

li:g:

OZ
,,-8

ICl
IC2
IC3
OCl
OC2IOCl
OC3/0Cl
OC4/0Cl
IC4IOC5/0Cl

~

,
CHIP
SELECT

,~g
Ii:!z

:;(8

SIM

UI

MISO
MOSI
SCK
QSM

E'CS.l

--

~

PCS3
TxD

EBI

---.J

DSACKO
DSACKl
AVEC
PE3

OS
AS
SIZO
SIZl

1MB

---=t.

r - - .--- .----

ADDR~9/PC6
~DDR23/CSl O/ECLK.

v "-

...---'
OUJ

g:1i:

Zo

8"-

-

DS/PE4
AS/PE5
SIZO/PE6
SIZ1/PE7

~-

DATA [0:15]

...--

05


IPIPEO/DSO

CHIP
SELECTS

BGLCSM.BGACKlCSE
FC2
FCI
FCO

TPUCH[15:0]
T2CUK
VSTBY

CSBOOT
B8!CSQ

VSTBY

ADDR23/GS.1.0/ECLK
ADDR221CS91PC6
ADDR21/CS91PC5
ADDR20lCSllPC4
ADDB19JCS6/PC3
FC2ICS5/PC2
FCl/Eill
FCO/CS3JPCO

CPU16

PADA7/AN7
PADA6/AN6
PADAS/AN5
PADA4IAN4
PADA3/AN3
PADA2/AN2
PADAlIANI
PADAO/ANO

ADDR[l B:l1YPA[7:0]
ADDR[23:0]

TPU
2 KBYTES
STBRAM

ADDR[10:3]/PB[7:0]

2KBYTES
TPURAM

ADC
ADDR[2:0]

VRH
VRL

SIZ1/PE7
S1Z01PE6
AS/PE5
DS/PE4

VDOA
VSSA

EEL
AllECIff2
DSACK1IPEI
DSACKO/PEO

VDD~
VSS~

1MB

EBI
DATA[15:B]/PG[7:0]

-=-

DATA[7:0yPH[7:0]
GPT
PGP7/1C4/0C5/0Cl
PGP6/0C4IOCI
PGP5/0C3IOCI
PGP4IOC2IOCI
PGP3IOCI
PGP2IIC3
PGP111C2
PGPOIICI

IlLW-

IC4IOC5IOCI
OC4/0Cl
OC3/0Cl
OC2/0Cl
OCI
IC3
IC2
ICI

BESET
IJAI..L
BERR

4BKBYTES
FLASH
EEPROM

MCCI
PWMA
PWMB
PCLK
PAl
PMC7ITXDA
PMC6/RXDA
PMC5ITXDB
PMC4IRXDB
PMC3JSS
PMC2/SCK
PMCl/MOSI
PMCO/MISO

PWMA
PWMB
PCLK
PAl

o~

",0

Ii: ~

28

CLOCK

TXDA
RXDA
TXDB
BlmB
SS
SCK
MOSI
MISO

TEST
TSC
QUOT
FREEZE

lBQZIPF7
lBQ6/PF6
lBQ5/PF5
JBQ4/PF4
lBQliPF3
lBQ2/PF2
IRQ1/PFl
MODCLKlPFO
CLKOUT
XTAL
EXTAL
XFC
VDDSYN
TSC
FREEZE/QUOT

vPP

Figure 10. MC68HC916Y1 Block Diagram

Motorola Master Selection Guide

2.6-17

Single-Chip Microcontrollers (AMCU)

Table 18. M68HC16 Family Modular Microcontrollers
Part
Number

ROM

SRAM

EEPROM

Timer

I/O

Serial

ADC

Integration
Module

Package

Comments

MC68HC16Z1

-

lK

-

GPT

46

QSM

8Ch,
lo-Bit

SIM

132-FC
132-FD
144-FM
144-FV

MC68HC16Z2

8K

2K

-

GPT

46

QSM

8Ch,
lo-Bit

SIM

132-FC
132-FD

20 Address Lines,
12 Chip Selects,
Synthesized Clock

MC68HC16Yl

48K

2K

-

TPU+GPT

95

MCCI

8Ch,
lo-Bit

SCIM

16o-FT
16o-FM

20 Address Lines,
9 Chip Selects, Single
Chip or Expanded Mode

lK

2KBEFIash
48KFIash

GPT

70

QSM

8Ch,
IO-Bit

RPSCIM

12o-TH

20 Address Lines,
5 Chip Selects, Single
Chip or Expanded Mode

4K

48K Flash

TPU +GPT

95

MCCI

8Ch,
IO-Bit

SCIM

16o-FT
16o-FM

20 Address Lines,
9 Chip Selects, Single
Chip or Expanded Mode

XC68HC916Xl

XC68HC916Yl

-

Single-Chip Microcontroliers (AMCU)

2.6-18

20 Address Lines,
12 Chip Selects,
Synthesized Clock

Motorola Master Selection Guide

The M68300 Family
The high-performance M68300 family is designed for
embedded control applications. Each M68300 MCU
incorporates a 32-bit M68000-based CPU module (CPU32),
a sophisticated integration module, and a number of
dedicated special-purpose modules. In addition to utilizing a
bus protocol similar to that of the M68020, the system
integration module generates external bus-control signals for

-G0::

~

$1

0..

I-

~l
~

M6800 devices, and provides a variety of programmable
chip-select functions. M68300 devices can be placed in
low-power stop mode to minimize power consumption during
periods of inactivity. The M68300 family provides great design
flexibility, performance, and compatibility with exiting
hardware and software.

CHIP
SELECTS

RAM

--

CSO-CS1

:;:=:::

.BE

agou =:

~

BGACK
FCO
FC1
F2

TPU

~li:
u~

EBI

1MB

-

=:

~
AD-A23
DSACK'
DSACK1
AVEC
RMC
DS
AS
SIZO
SIZ1

=:

CSBGGT
BRieso
BG/CS1BGACKICS2
FCOlCS3
FC1/CS4
FC2ICS5
A19/CSS
A20/cr,2
A21/CS8
A22/CS9A23/CS10

r__
AD-A1B)

-'

Ow

"'l-

1-",

20

80..

:::::
:::::
--

OSACKO
DSACK1

mE

BMC
OS
AS
SIZO
SIZ1

DD-D15

R/W
RFf;FT
lAI

BERR
QSM

IRD1-R
MODCK

-

CPU32

CLOCK

TEST

~LKOUT

XTAl
EXTAl
XFC
Vnn~vN
~

TSTME
DUOT

8", eng
ou
uu
'" en
xen
en ~~ ~:iE IgJ
N

~

1-0.. 0..0..

~

II~ I~

~I

1BQ1

l8Q2
a
?go :=:::::
JBQ3.

IIlQ4
~::::: JB.Q5

lBQ6

IRQ?

r::;

~I-- TSTMEITSC

~I--

u

FREEZE/QUaT

L-

aNTRal

CONTROL
PORTD
IgJ
N
'" uu
8~
ou
enu
xen
1-0.. ~~ 0.. en

:5

uo
en en Ci51~
0 0 o!!:

-8
----

r - _ MOOCK

oen r:s
~ft.l
::;;::;;

~I~ ~

I~ ~ I~
Figure 11. MC68332 Block Diagram

Motorola Master Selection Guide

2.6-19

Single-Chip Microcontrollers (AMCU)

VFPE16K
TPUCHAN15-TPUCHANO
T2CLK
VSTBY
CHIP
SELECTS

RXD
...IXQfOS7
ECS3/QS6
ECS2IOS5

CS800T

llI3ICS!L

8GICSM-

-----ECS1JQS4
PCSOISSlOS3
SCKlOS2
MOSI/OS1
MISO/OSO

BGACKlCSE
FC2
FC1
FCO

OSM

512
BYTES
SRAM

3.5
KBYTES
SRAM

TPU

16KBYTES
FLASH
EEPROM

ADDR23JCSWIECLK
ADDR22!CS9IPC6
ADDR21/CSBIPCS
ADDR20/CS1IPC4
ADDB19iCS6IPC3
FC2/CS5IPC2
FClIEl::1
FCO/CS3JPCO

ADDR[18:11]/PA[7:0]
ADDR[23:0]
ADDR[10:3]IPB[7:0]

ADDR[2:0]
SIZ1/PE7
SJZOIPE6
ASlPE5
IlSIEE4
BMCIPE3
AllEC.lEE2
DSACKlIPE1
DSACKOIPEO
1MB

EBI
DATA[15:8]IPG[7:0]

AN7/PADA7
AN6/PADA6
AN5/PADA5
AN4IPADM
AN3JPADA3
AN2/PADA2
AN1IPADA1
ANO/PADAO
VRH
VRL
PADB7
PADB6
PADB5
PADB4
PADB3
PADB2
PADB1
PADBO

DATA[7:0YPH[7:0]

BlW.-

BESET
HAlT

BERRISCENB
ADC
In

c

-

APPLICATIONS
1/0:

~

GENERAL
1/0

APPLICATION
PROCESSOR

1010
PARAllEL
PORT
SERIAL
PORT

RAM
1K12K BYTES

100

2TIMERJ
COUNTERS
EEPROM
51212K BYTES

ROM
10K BYTES

"-

"\.

CLOCKING
AND
CONTROL

ClK1
ClK2
SERVICE
RESET

Figure 13. MC143120 (32-Lead SOG)

LONWORKS Products

2.7-2

Motorola Master Selection Guide

NEURON CHIPS (continued)
MC143150 Features

application program. The NEURON IC supports a maximum
clock rate of 10 MHz.
Both NEURON CHIPS have eleven I/O pins (10.0 - 10.10)
to provide flexible interfacing to external hardware and access
to two internal timers/counters. 10.4 - 10.7 have optional
pull-up resistors. Pins 10.0 - 10.3 have high current sink
capability (20 mA @ 0.8 V) while the others have a standard
sink capability of 1.4 mA @ 0.4 V. All I/O pins have TTL-level
inputs with hysteresis.
There are two versions of the MC143150 NEURON IC that
offer different cost and technical advantages. The
MC143150FU operates up to a maximum clock rate of 10 MHz
over a temperature range of -40 to +85°C. The
MC143150FUl is a lower cost device that operates up to
5 MHz over the same temperature range and consumes less
power. The key difference between the two ICs is in the cost
saving gained by using an external 200 ns EPROM memory
device with the MC143150FUl as opposed to a 90 ns memory
device for a 10 MHz clock rate with the MC143150FU.

The MC143150 conlains an additionallKofon-chip RAM
(2K total) but no on-board ROM. An external memory
interface allows the system designer to use 42K of the
available 64K of address space for application program
storage. The remaining address space is reserved for
LONTALK communications protocol, operation system, and up
to 34 I/O models which are supplied with the LON BUILDER
Developer's Workbench or NODEBulLDER Development Tool.
The protocol and application code can be located in external
ROM, EEPROM, NVRAM, or battery-backup static RAM. The
MC143150 is available in a 64-pin QFP.

Shared Strengths
Of the three processors on-board each NEURON CHIP, two
(MAC and Network processors) implement a communication
subsystem, enabling the automatic transfer of information
from node to node. The remaining processor handles the

Integrated Circuits
Motorola
Part No.

Description

LeadsPackage

Samples

Production

Document#

MC143120DW

NEURON IC lK RAM/512 EEPROM/10K ROM, 10 MHz, 1.2 11m

32-50G

PhaseOut

Phase Out

MC143120B1DW

NEURON IC lK RAM/512 EEPROM/10K ROM, 10 MHz, 0.8 11m

32--50G

Now

Now

BRl134/D
DL159/D

MC143150FU

NEURON IC 2K RAM/512 EEPROM, 10 MHz, 1.2 11m

64-POFP

Phase Out

Phase Out

MC143150FUl

NEURON IC 2K RAM/512 EEPROM, 5 MHz, 1.2 11m

64-POFP

Now

Now

MC143150B1FU

NEURON IC 2K RAM/512 EEPROM, 10 MHz, 0.8 11m

64-POFP

Phase Out

Phase Out

MC143150B1FUl

NEURON IC 2K RAM/512 EEPROM, 10 MHz, 0.8 11m

32-S0G

1095

1095

MC143120E2DW

NEURON IC 2K RAM/2K EEPROM, 10 MHz, 0.71 11m

32-S0G

4095

1096

Motorola Master Selection Guide

2.7-3

LONWORKS Products

'"'-

r'CP4

MAC
PROCESSOR

en

en

::>
CD

NETWORK
PROCESSOR

en
en
UJ
ex:

Cl
Cl

«

::>
CD

NETWORK
COMM.
PORT

~
Cl

CP3
CP2
CP1

CPO

!:::
CD

a,

!:::

;

APPLICATIONS
1/0:
GENERAL
1/0

APPLICATION
PROCESSOR

1010
PARALLEL
PORT
SERIAL
PORT

RAM
2K BYTES

100

2TIMERI
COUNTERS
EEPROM
512 BYTES
ADDRESS
DATA

"-

""-

RIV!'

CLOCKING
AND
CONTROL

CLK1
CLK2
SERVICE
RESET

E

Figure 14. MCl43150 (64-Lead PQFP)

LONWORKS

Products

2.7-4

Motorola Master Selection Guide

LONWORKS

Technology Overview and Architecture

LONWORKS technology is a complete solution for
implementing distributed control networks. These networks
consist of nodes that communicate with one another over a
variety of communications media using LONTALK protocol, a
common, message-based communications protocol. In a
LONWORKS application, nodes sense, monitor, count,
measure time, manage switches and relays, and respond to
conditions reported by other smart nodes.
LONWORKS technology includes all of the hardware and
firmware functions needed to process data within nodes and
to communicate information among nodes through a variety

of network physical layers. In one convenient package,
designers can now access all the elements required to design,
install, and support control networks. Those elements include:
the MC143150 and MC143120 NEURON CHIPS, LONWORKS
transceivers, the LON BUILDER Developer's Workbench, and
LONTALK protocol.
LONTALK protocol features seven layers, each optimized for
control networks, and is based on the OSI reference model.
LONTALK protocol is embedded within the firmware of
Motorola's NEURON CHIPS and is the foundation of the
LONWORKS technology networking solution.

Networking Medium (Twisted Pair, RF, Power Line, etc.)

Figure 15. MC143150 in a Typical Node Block Diagram

Network Transmission Medium

LONWORKS

Router

Network Transmission Medium

Figure 16. The MC143150 or MC143120 in a LONWORKS Network

Motorola Master Selection Guide

2.7-5

LONWORKS Products

LONBulLDER

Developer's Workbench(1)

Thanks to Echelon's LON BUILDER and NODEBulLDER tools, as
well as Motorola's extensive technical support network, both
system and device manufacturers can.now develop control
networks quickly and inexpensively. These tools provide
developers with everything needed to begin building
LONWoRKs-based products immediately. The NODE BUILDER
Development Tool is used to design individual LONWORKS
products while the LON BUILDER Developer's Workbench
features the tools required to develop systems consisting of
multiple LONWORKS nodes. Best of all, technical support for
LONWORKS technology is available worldwide through
Motorola's 30 LONWORKS design centers.
LON BUILDER Developer's Workbench combines three
development tools - a multi-node development system, a
network manager, and a protocol analyzer - into an
integrated hardware and software development environment.
This development system provides the tools to create
software applications and prototype hardware on a network
ranging from two to hundreds of nodes. The network manager
installs and configures nodes during development, making
them easy to connect, define, and build. The protocol analyzer
monitors the network and interprets its activity.

The LON BUILDER Developer's Workbench includes two PC
interface cards, two LONWORKS transceivers, an expandable
development station with two NEURON CHIP emulator cards,
DOS-based software for compiling, loading, integrating and
testing LONWORKS applications, and Windows-based
software for monitoring and controlling a LONWORKS
application.
The LONWORKS NODE BUILDER Development Tool is used to
design LONWORKS nodes. The NODEBulLDER tool does not
include the system integration and test tools incorporated into
the LON BUILDER Developer's Workbench, but does include all
the tools required to compile, load, and test code for a
LONWORKS node. NODEBulLDER includes Windows-based
software, a PC interface card, a prototype LONWORKS node,
and two LONWORKS transceivers that are used to develop and
test LONWORKS nodes.
The LON BUILDER development tool requires a PC with an
available 8- or 16-bit slot, DOS 3.3 or higher, 64K bytes of
RAM, mouse, and a hard disk with 10M bytes of available
storage. The NODE BUILDER tool requires a Microsoft®
Windows-compatible PC with an available 16-bit slot,
8M bytes of RAM, mouse, and a hard disk.

(1) Motorola supports these tools, but they should be purchased through Echelon Corporation (1-800-258-4566).

LONWORKS Products

2.7-6

Motorola Master Selection Guide

LONWORKS

Support Tools

Motorola's LONBulLDER support tools offer the user a quick
and flexible means to demonstrate or test a LONWORKS based
product which was developed and debugged on the
LONBulLDER Developer's Workbench. The family of tools
consist of NEURON CHIP based development boards, 1/0
application boards, a Differential Direct Connect Transceiver
Board (for the LONBulLDER Developer's Workbench), and a

RJ45

M143204EVK
DIFFERENTIAL
DIRECT
CONNECT
TRANSCEIVER

I/O

GIZMO 4
M143207EVK
I/O INTERFACE
BOARD

RJ45

GIZMO 3

MC143120

M143206EVK
I/O INTERFACE
BOARD

NEURON CHIP

EVALUATION BOARD

RJ45

MC143120/50
sockets

sockets

111~ ~ too

ll
{~:~"d':f:'.{

:"::; i .:;: : x: ':

~! : : .:.

MEMORY

P3~~.~.1
.'d . .

1;31~il

I/O
M143205EVK
NEURON CHIP

M143208EVK
I/OTESBOARD

TEST/PROGRAMMING
BOARD

Figure 17. Evaluation and I/O Interface Boards

Motorola Master Selection Guide

2.7-7

LON WORKS Products

NEURON CHIP Test/Programming Board. The unique
. advantages that these tools offer are:
• The boards all have RJ45 connectors allowing ease of
connectivity.
• The NEURON CHIP boards contain a 5 volt regulator
allowing for a wider range of power supply voltages.
• A common 2 x 10 connector for interface to the NEURON
CHIP I/O pins.

Motorola Support Tools for

• A library of application functions are available from
Motorola .
• An inexpensive means of demonstrating LONWORKS
based products.
This document covers a brief detail on each of the boards.
For further information, contact Motorola'S LONWORKS
applications support team in Austin, Texas at 512-505-8330
or FAX 512-505-8312.

LONWORKS

Motorola
Part No.

Description

Production

M143120EVK

143120 NEURON IC Custom Node Development Board with Socket, Supports all
MC143120 NEURON Chips

M143120B1EVBU

MC143120B1 DW NEURON IC Custom Node Development Board

M143150EVK

MC143150FU NEURON IC Custom Node Development Board

M143150B1EVBU

MC143150B1FU NEURON IC Custom Node Development Board

M143204EVK

Direct Connect Transceiver Board

M143206EVK

NEURON IC I/O Interface Board (Gizmo 3)

M143207EVK

NEURON IC I/O Interface Board (Gizmo 4)

M143208EVK

NEURON IC I/O Interface Test Board (Gizmo 5)

M143213EVK5

NEURON IC RF Radio with EIA-232 Interface (US Version)

M143213EVK6

NEURON IC RF Radio with EIA-232 Interface (European Version)

M143214EVK5

NEURON IC RF Radio with I/O Interface (US Version)

M143214EVK6

NEURON IC RF Radio with I/O Interface (European Version)

M143215EVK5

RF Radio for Router Interface (US Version)

M143215EVK6

RF Radio for Router Interface (European Version)

M143221EVK

EIA-232 EVBU Interface Board

M143222EVK

Intelligent Neuron IC Cards (5 Cards, to be used

M143223EVK

NEURON Chip Card Reader Board (to be used with M143222EVK Cards)

M143226EVK

Intelligent NEURON IC Kit with UART Port

M143232EVK

ADPCM Voice Application Kit

LONWORKS Products

2.7-8

w~h

Document#
BR1139

M143223EVK Card Reader)

Motorola Master Selection Guide

LONWoRKS Literature
Motorola
Document No.

Echelon
No.

Description
LONWORKS Technology Device Data
NEURON CHIP Product Overview
LONWORKS Support Tools

DL159/D
BR1134/D
BR1139/D

Current versions (Q4/95) of the following Engineering Bulletins and Application Notes are incorporated into Motorola
publication DL 159/0, LON WORKS Technology Device Data.
AN1208lD
AN1211/D
AN1216/D
AN 1225/0
AN1247/D
AN1248/D
AN1250/D
AN1251/D
AN 125210
EB146/D
EB147/D
EB148/D
EB149/D
EB150/D
EB151/D
EB1521D
EB153/D
EB155/D
EB157/D
EB159/D
EB161/D
EB167/D
EB168/D
EB169/D
EB170/D
EB171/D
EB1721D
EB173/D
EB174/D
EB175/D

Parallel I/O Interface to the NEURON CHIP
Interfacing DACs and ADCs to the NEURON IC
Setback Thermostat Design Using the NEURON IC
Fuzzy Logic and the NEURON CHIP
MC683XX to NEURON CHIP Parallel I/O Interface
Interfacing the PSD3XX to the MC143150
Low-Cost PC Interface to LONWORKS Based Nodes
Programming the MC143120 NEURON CHIP
MIP Guidelines and Design Issues
005-0003-01 A
005-0006-01B
005-0001-01B
005-0011-01 A
005-0009-01 A
005-o004-D1A
005-0002-01 A
005-0014-01B
005-o019-01B
005-o016-01B
005-o022-o1B
005-0017-01 B
005-0043-01 A
005-o006-01C
005-0032-o1C
005-0010-01 A
005-0013-01 B
005-0024-D1 A
005-0027-o1F
005-0023-01 A
005-007-01G

NEURON CHIP Quadrature Input Function Interface
LONWORKS Installation Overview
Enhanced Media Access Control with Echelon's LONTALK Protocol
Optimizing LONTALK Response Time
NEURON CHIP EIA-485 Transceiver
Scanning a Keypad with the NEURON CHIP
How to Use SNVTs in LONWORKS Applications
Driving a Seven-Segment Display with the NEURON CHIP
Analog-to-Digital Conversion with the NEURON CHIP
Creating Applications with the LON BUILDER Multi-Function I/O Kit
NEURON CHIP-Based Installation of LONWORKS Networks
LONTALK Protocol
A Hybrid System for Fast Synchronized Response
EIA-232C Serial Interfacing with the NEURON CHIP
LONWORKS 78 kbps Self-Healing Ring Architecture
LONTALK Response Time Measurements
NEURON 3150 CHIP External Memory Interface
LONWORKS Custom Node Development
The SNVT Master List and Programmer's Guide
Junction Box and Wiring Guidelines for Twisted Pair LONWORKS Networks
NEURON C Extended Arithmetic Support

The following documents can be ordered from Echelon Corporation.
078-0001-01 A
076-0002-01
076-0140-01

Lon Builder User's Guide
NEURON C Programmer's Guide
NEURON C Reference Guide

Contact Motorola or Echelon (415-855-7400) for additional documentation.

Motorola Master Selection Guide

2.7-9

LONWORKS Products

LoNWORKS Products

2.7-10

Motorola Master Selection Guide

Memory Products

In Brief ...
Motorola's memory product portfolio has been expanded
to support a broad range of engineering applications.
Included in this portfolio are asynchronous devices with
access times of 6 ns at 256K-bit density, 6 ns at 5 V 1
Megabit density, 8 ns at 3.3 V 1 Megabit density, as well as
synchronous FSRAMs with access times as fast as 6 ns and
8.5 ns.
Motorola's Fast Static RAM Division goal is simple:
speed. All of our SRAMs are designed to provide the highest
performance, cost efficient solutions available.
The Dynamic Memory Products Division utilizes
alliances as a vehicle for global customer support in the
DRAM and memory module markets. The product portfolio
consists of high-density DRAMs, standard and custom
memory modules, and PCMCIA Flash cards.

Motorola Master Selection Guide

Fast Static RAMs ... , ............... , .......... .
Introduction ................................ .
Application Specific Static RAMs .............. .
Asynchronous 6 to 15 ns 5 V Fast Static RAMs ..
Asynchronous 12 to 35 ns 5 V Fast Static RAMs.
Fast Static RAM Modules .................... .
Dynamic RAMs ............................... .
Introduction ................................ .
DRAM Modules ............................ .
Dynamic RAMs (HCMOS) ................... .

2.8-1

Page
2.8-2
2.8-2
2.8-2
2.8-3
2.8-3
2.8-4
2.8-5
2.8-5
2.8-5
2.8-6

Memory Products

Fast Static RAMs
Introduction
Mgtorola is designing the fastest, most technologically
advanced fast SRAMs. From 0.8 11m to 0.5 11m with access
times as fast as 5 V 6 ns 256K, 6 ns 1M, 13ns 4M, and
8 ns 3.3 V 1M, these devices are progressively smaller,
faster, and lower cost. These SRAMs are designed to provide
the highest performance, cost efficient solutions available.
Selected fast SRAMs are also available on 2M and 8M
memory modules.

Application specific memories are designed for
high-performance microprocessors that require more
specialization from memory cache than is available from
standard devices. Products include those for use with digital
signal processors as well as a variety of popular
microprocessors.

SYNCHRONOUS
APPLICATION SPECIFIC FAST STATIC RAMs (5 to 35 ns)
3.3 V Supply
OrganiDescription

zatlon

BurstRAMsTM

32Kx32

Packaging

(ns Max)

Technology

Production

MCM63P532

100

(TO) TOFP

7/8/9

HCMOS

1096

Pipelined BurstRAM for PowerPCTM /Pentiumnt MPUs.
Flow-through BurstRAM for PowerPC/Pentium MPUs.

Access Time

Comments

MCM69F536A

100

(TO) TOFP

8.519110112

BiCMOS

Now

MCM69P538A

100

(TO) TOFP

5/617

BiCMOS

Now

Pipelined BurstRAM for PowerPc/Pentium MPUs.

64Kx18

MCM69F618A

100

(TO) TOFP

8.519/10/12

BiCMOS

Now

Row-through BurstRAM tor PowerPClPentium MPUs.

MCM69P618A

100

(TO) TOFP

5/617

BiCMOS

Now

Pipelined BurstRAM for PowerPC/Pentium MPUs.

64Kx18

MCM69T618

119

(ZP) PBGA

5/617

BiCMOS

2096

100 MHz Cache Tag RAM.

32Kx36

Tag RAM

Pin
Count

Motorola
Part Number

SV Supply
Organi-

Motorola

Pin

Pro-

zatio"

Part Number

Count

Packaging

AccessTlme
(nsMax)

Tech-

Description

nology

duct'on

Comments

Integrated
Cache

32Kx36

MPC2604GA

357

(ZP) PBGA

66 MHz

BiCMOS

1096

Integrated L2 cache for PowerPC processors.Two components
for 256KB solution. and four for 512KB.

Solutions
BurstRAMs

64Kx18

32Kx18

MCM67B618A

52

(FN) PLCC

9/10112

BiCMOS

Now

BurstRAM (flow-through) for 4861Pentium. 3.3 V output levels.

MCM67C618A

52

(FN) PLCC

517

BiCMOS

Now

BurstRAM (pipelined) for 4861Pentium. 3.3 V output levels.

MCM67H61BA

52

(FN) PLCC

9110112

BiCMOS

Now

Supports Pentium pipelined address mode.

MCM67J618A

52

(FN) PLCC

517

BiCMOS

Now

Supports Pentium pipelined address mode.

MCM67M61BA

52

(FN) PLCC

9/10112

BiCMOS

Now

BurstRAM (flow-through) for PowerPC. 3.3 V output levels.

MCM67B518

52

(FN) PLCC

9/10/12

BiCMOS

Now

BurstRAM (flow-through) for 486/Pentium. 3.3 V output levels.
Not recommended for new designs.

MCM67C518

52

(FN) PLCC

617/9

BiCMOS

Now

BurstRAM (pipelined) for 486/Pentium. 3.3 V output levels. Not
recommended for new designs.

MCM67H518

52

(FN) PLCC

9/10/12

BiCMOS

Now

Supports Pentium pipelined address mode. Not recommended
for new designs.

MCM67J518

52

(FN) PLCC

617/9

BiCMOS

Now

Supports Pentium pipelined address mode. Not recommended
for new designs.

MCM67M518

52

(FN) PLCC

9/11/14

BiCMOS

Now

BurstRAM (flow-through) for PowerPC. 3.3 V output levels.
Not recommended for new designs.

DSPRAMTM

8Kx24

MCM56824A

52

(FN) PLCC

20125/35

HCMOS

Now

Designed for DSP56001 applications. replaces 3 8Kx8's.

General
Synchronous

128Kx9

MCM670709

B6

(ZP) PBGA

516

BiCMOS

Now

General synchronous separate 1/0 with write pass through.
3.3 V output levels.

256Kx4

MCM670B04

38

400 (WJ) SOJ

5/6

BiCMOS

Now

Graphics; general RISC. Register to register. Revolutionary
pinout. 3.3 V output leve~. Write pass through. Separate I/O.

16Kx16

MCM62990A

52

(FN) PLCC

12/15120125

HCMOS

Now

Designed for advanced RISC-CSIC cache applications

MPC27T416

80

(TO) TOFP

9/10112

BiCMOS

2096

14 tag bits. 2 status bits. Sampling 2096.

8Kx8

MCM62X3OB

28

300 (J) SOJ

15/17

HCMOS

Now

Une buffer for processing digital data.

4Kx12

MCM62973A

44

(FN) PLCC

18/20

HCMOS

Now

Pipelined SRAM with chip select.

MCM62974A

44

(FN) PLCC

18/20

HCMOS

Now

Pipe lined SRAM with output enable.

MCM62975A

44

(FN) PLCC

25130

HCMOS

Now

Output enable.

Memory Products

2.8-2

Motorola Master Selection Guide

ASYNCHRONOUS
6 to 15 ns FAST STATIC RAMS
3.3 V Supply
OrganiDensity

zatian

1M

128Kx8
256Kx4

Count

Packaging
Package width In mils

Access Time
(ns Max)

Technology

Production

MCM6926

32

400 (WJ) SOJ

8110/12115

BiCMOS

1096

Revolutionary pinout.

MCM6929

32

400 (WJ)SOJ

8110/12115

BiCMOS

1096

Revolutionary pinout.

Pin
Count

Packaging
Package width in mils

Access Time
(ns Max)

Technology

Production

Motorola
Part Number

Pin

Comments

5VSupply
OrganiDensity

zalion

Motorola
Part Number

1M

64Kx18

MCM67A618A

52

(FN) PLCC

10112115

SiCMOS

Now

General asynchronous, latched address and data.

128Kx8

MCM6726B

32

400 (WJ) SOJ

8110/12

BiCMOS

Now

Use for new quais and design. Revolutionary

MCM6726C

32

400 (WJ) SOJ

6f7

BiCMOS

Now

Revolutionary pinout.

MCM6729B

32

400 (WJ)SOJ

8110/12

SiCMOS

Now

Use for new quais and design. With output enable.
Revolutionary pinout.

MCM6729C

32

400 (WJ) SOJ

6f7

BiCMOS

Now

Revolutionary pinout.

MCM6706B

28

300 (J) SOJ

8110

BiCMOS

Now

Not recommended for new designs. Potential
substitute MCM6706BR.

MCM6706BR

32

300 (J) SOJ

6m8

BiCMOS

Now

Revolutionary pinout.

Pin
Count

Packaging
Package width in mils

ACC8ssTlme
(ns Max)

Tool>-

Pro-

nology

duction

400 (J) SOJ

12115

HCMOS

2096

Comments

pinout.

256Kx4

256K

32Kx8

12 to 35 ns FAST STATIC RAMS
3.3 V Supply
Density

Organizatlon

1M

64Kx16

MCM6323

44

128KxB

MCM6326

32

400 (J) SOJ

12115

HCMOS

3096

Revolutionary pinout. Samples 2096.

32KxB

MCM6306D

28

300 (J) SOJ

15120/25

HCMOS

Now

3.3 V Fast SRAM

Pin
Count

Packaging
Package width in mils

Access Time
(ns Max)

Technology

duction

36

400 (WJ) SOJ

20/25135

HCMOS

Now

Output enable. Revolutionary pinout.

256K

Motorola
Part Number

Comments
Revolutionary pinout. Samples 1096.

5V Supply
Organizatlon

4M

512KxB

MCM6246

lMx4

MCM6249

32

400 (WJ) SOJ

20/25135

HCMOS

Now

Output enable. Revolutionary pinout.

1M

64Kx16

MCM6223

44

400 (J) SOJ

12/15

HCMOS

2096

Revolutionary pinout. Samples 1096. 3.3 V lias.

128Kx8

MCM62268

32

400 (WJ) SOJ

15117/20/25

HCMOS

Now

Not for new designs. Suggest MCM6226BB.

MCM62268A

32

400 (WJ) SOJ

17120125

HCMOS

Now

Not for new designs. Suggest MCM6226BB.

MCM6226BB

32

300 (J), 400 (WJ) SOJ

15117120/25

HCMOS

1096

Samples 4095.

MCM6326

32

400 (J) SOJ

12/15

HCMOS

3096

Revolutionary pinout. Samples 2096. 3.3 V lIas.

MCM62298

28

400 (WJ) SOJ

15117/20/25

HCMOS

Now

Not for new designs. Suggest MCM6229BB.

256Kx4

256K

Motorola
Part Number

Pro-

Density

Comments

MCM62298A

28

400 (WJ) SOJ

17120/25

HCMOS

Now

Not for new designs. Suggest MCM6229BB.

MCM6229BB

28

300 (J), 400 (WJ) SOJ

15/17120125

HCMOS

1096

Samples 4095.

lMxl

MCM62278

28

300 (J), 400 (WJ) SOJ

15117/20/25

HCMOS

Now

Separate 110. Replaces 6227A

16Kx16

MCM62996

52

(FN) PLCC

12115120125

HCMOS

Now

Choice of 5 V or 3.3 V power supplies for output
buffers. For wide bus applications.

MCM62995A

52

(FN) PLCC

12115120125

HCMOS

Now

DSP96000 and RISC applications. Latched address
inputs.
Replaces MCM6206D.

32Kx8

MCM6206BA

28

300 (J) SOJ

12115/20/25

HCMOS

Now

32Kx9

MCM620S0

32

300 (J) SOJ

15120/25

HCMOS

Now

Motorola Master Selection Guide

2.8-3

Memory Products

j

DEVICEIPART NUMBER DESIGNATORS

SYNCHRONOUS DEVICE

ASYNCHRONOUS DEVICE

~~~~~enl

!fC]7

MC=Oualified
SC= Special

Memory
62=5VCMOS
63 = 3.3 V CMOS
67 = 5 V BiCMOS
69 = 3.3 V BiCMOS

I
B

MotorolaCompone~ntM

~t
Die

Speed (ns)
Pacl\age" (WJ = Wide SOJ,
J = SOJ, FN = PLCC,
TB = TAB)

(Qualified)

Memory

Revi::~~lutiOnary Pinout*

Blank =First qualified Motorola device
= First die size change/spec change
B =Second die size change/spec change
SA = First qualified foundry device

A

Density:
=256K
2=IM
4=4M
6= 16K
8=64K

o

Width:
5=x9

A

B
C

Width:
04=x4
08=x8
09=x9
16=x 16
18=x18
24=x24
32=x32
36=x36

Async w/Address and
Data Latch
= x86 Burst COunt
x86 Burst Count and
Output Register
Dual 110
Flow-Through BurstRAM
x86 Burst Count with Address
Disable

x86 Burst Count with Address Disable
and Output Register
MolOroIa (PowerPC) Bursl Count
Pipellned BurstRAM
Sep.1I0
Cache Tag
Line Buffer

M
P

o

T

" These deSignators apply to current products - future products will not necessarily
follow this scheme.

Ole Revision

=

F
H

NOTE: There are some exceptions to these device numbering schemes, i.e.,
MCM62990A is a CMOS 16Kx 16 and NOT a 512Kx 90 device. MPC designates
devices designed to work with PowerPC microprocessors and support chips.

Pacl\age (WJ = WIde SOJ,
FN = PLCC, J = SOJ,
ZP = PBGA, TO = TOFP)

.

62=5V CMOS
63 = 3.3 V CMOS
67 = 5 V BiCMOS
69 = 3.3 V BiGMOS

o

6""x8

7=x1
8=x4
9=x4withOE

PL¥-~

X

' - - - - - Deplh:
3 = 8K Address Depth
4 = 16K Address Depth
5 = 32K Address Depth
6 = 64K Address Depth
7 = 128K Address Deplh
8 = 256K Address Depth

FAST STATIC RAM MODULES (Contact Fast Static RAM Marketing for Custom Fast SRAM Modules)
PowerPC Processor Applications
Description

Chip Sot

Functionality

Cache Size

Access Time
(Max)

Productlon

Packaging

Motorola
Part Number

PowerPOM Cache
Modules

Motorola MPC105,
Motorola MPC106

Flow-Through Burst

512KB Cache

66 MHz

1096

136 Pin DIMM (SG)

MPC21 03

Asynchronous

256KB Cache

15 ns

1096

PowerPC Cache
Modules with 16K x 15
CacheTag

Motorola MPC105,
Motorola MPC106

Flow-Through Burst

256KB Cache

66 MHz

TBD

182 Pin Card Edge (SG)

MPC2104

Flow-Through Burst

512KB Cache

66 MHz

1096

MPC2105

Flow-Through Burst

1MB

66 MHz

1096

MPC2106

Asynchronous

256KB Cache

15ns

TBD

MPC2107

MPC2101

Pentium and other x86 Processor Applications
Description

ChipSet

Functionality

Cache Size

Accessl1me
(Max)

Production

Packaging

Pentium™ L2 Cache
Modules

Inlel 62430 FX
Triton chip set

Piped Burst

512KB Cache

66 MHz

Now

160 Pin Card Edge (SG)

256KB Cache

66 MHz

Now

Asynchronous

256KB Cache

15 ns

Now

160 Pin Card Edge (SG)

MCM64AF32

Flow-Through Burst

512KB Cache

60/66 MHz

Now

136 Pin DIMM Fonn Factor. (SG)

MCM72BA64

256KBCache

60/66 MHz

Now

Flow-Through Burst

512KB Cache

60166 MHz

Now

Intel 82430 PCI
chip set

Motorola
Part Number
MCM72JG64
MCM64PA32

MCM72BA32
160 Pin Card Edge (SG)

MCM72BF64

VLSI82C590

Asynchronous

256KB Cache

15 ns

Now

160 Pin Card Edge (SG)

MCM64AG32

Corollary, Ross
Computer

Piped Burst

512KB Cache

66 MHz

Now

160 Pin Card Edge (SG)

MCM72CB64

RISC Processor Applications
Description
R4000
Secondary Cache
Modules

Cache Size

Access Time
(Max)

Motorola

Production

Packaging

Part Number

Comments

4MB

12/15/17 ns

Now

80 Pin SIMM (SG)

4MB cache using 4 modules. all Tag options
available.

1MB

12/15/17ns

Now

60 Pin SIMM (SG)

1MB cache using 4 modules, all Tag options
availabte.

MCM44256 Series

MCM4464 Series

Networking and Buffer Applications
Description

Organization

Accessl1me
(Max)

Production

Packaging

Slandard FSRAM
Modules

lMx32

20/25 ns

Now

72 Pin SIMM (SG)

Uses eight 4M SRAMs

MCM321 024

512Kx32

20125 ns

Now

72 Pin SIMM (SG)

Uses four 4M SRAMs

MCM32515

Memory Products

2.8-4

Comments

Motorola
Part Number

Motorola Master Selection Guide

Dynamic RAMs
Introduction
DRAMs offer the lowest cost per bit of any memory.
Because of this, they are popular for a wide range of
applications, particularly in the computing environment.
Motorola's Dynamic Memory Products include DRAM
components, memory modules, and PCMCIA Flash cards.
The 4 and 16 MByte DRAM components are offered in
various organizations and surface mount packaging.
Motorola's DRAM Memory Modules include densities up to
64 MByte in both standard and custom configurations.

All devices are fabricated using HCMOS technology and
operate in a 5-volt power supply. However, specific DRAM
products are designed for use in either a 3.3 Volt or 5-Volt
power supply.
The 68-pin Flash ATA card is fully PCMCIA compatible. It
is available in capacities from 1.8 MBytes to 40 MBytes and
capacities can be doubled using data compression
software.

DRAM MODULES (Contact DRAM Marketing for Custom DRAM Modules)
Motorola

Organi-

Byte

Part

zation

Density

Number

Pin
Count

1MxB

1MB

MCM81430

30

(S)

4Mx8

4MB

MCM84000

30

(AS)

MCM84430

30

(S)

MCM84T430

30

(S)

"~~'

·.•.• J.MfI.: •.•

4Mx9

4MB

'1Mx,18 . . ,2MB

~~~2~~1>81<~',~

tMy~~~4~, .•• 1:::3~.:: I:~SI' 1':.0,..

Access Time
(ns Max)

Operating
Current
(rnA Max)

duction

60/70

240/200

Now

60/70
50/60/70

960/800

Now

30---pad SIMM package

260/220/190

Now

30-pad SIMM package; 2--chlp version

50/60/70

260/220/190

Now

3D-pad SIMM package; 2--chip TSOP version

IP \' ')1 1:\, ~:io~~ (I] Lrf

'

:'"

Comments
3D-pad SIMM package; 2-chip version

~r. j>antxapi'l~a!iOn; 3~ip
:~.~> ,,~~Jl'l7~IMN)ac~i\9'>
.ve\s",.~· •• " .• ,
'" ". ":'" '. ". .... '. '. . ' •

MCM94000

30

(AS). (SC)

60/70

1080/900

Now

30 pad SIMM package for parity application

MCM94430

30

(S)

60/70

340/290

Now

30-pad SIMM package; 3-chip version

MCM94T430

30

(S)

60/70

340/290

Now

I (AP). (AS,S) :!>;!. f",j
•. M<:;t..ff8;>ao .. •. I,.•::~;: •.:: .($).,1ii.<3),.'
i I~il ~!;;~~:
'M9M1810.0

·"··1M i:h.

8O

Pro-

\, r::rr~:,:' ifti,SIM"tj>acki'.9.,'fQ~1,&b,i~p~,"y ;;Pl?,I~'IO" '.
,!",j>ad.J?tI<1.M P'\ck"~,fQ' le'.i''R?MYi'Pl?,)icatlq~

4Mx18

8MB

MCM18400

72

(AS). (AS<3)

60/70

680/580

Now

72 pad SIMM package for 16 bit panty application

8Mx18

16MB

MCM1880a

72

(AS), (ASS)

60/70

6921592

Now

72-pad SIMM package for 16 bit parity application

1Mx32

4MB

MCM3210a

72

(OS)

60/70

960/800

Now

Small outline DIMM package,S V

MCM32103

72

(OG)

80

480

Now

Small outline DIMM package, 3.3 V - TSOP

MCM32Ll03

72

(OG)

80

480

Now

Small outline DIMM package, 3.3 V Low power
TSOP

MCM32116

72

(S).(SS)

60/70

370/310

Now

72-pad SIMM package; Uses 1M x 16 SOJ DRAM

MCM32T116

72

(SH)

60170

370/310

Now

72-pad StMM package; Uses 1M x 16 TSOP DRAM

MGM32130

72

(SH). (SHG). (SSH)

60/70

960/800

Now

72-pad SIMM package; SOJ version

MCM32Tl00

72

(S).(SS)

60/70

960/800

Now

72-pad SIMM package; TSOP version

MGM32216

72

(S). (SG)

60/70

374/314

Now

72-pad SIMM package; Uses 1M x 16 SOJ DRAM

MGM32T216

72

(SH)

60/70

374/314

Now

72-pad SIMM package; Uses 1M x 16 TSOP DRAM

MCM32230

72

(SH). (SHG)

60/70

976/816

Now

72-pad SIMM package; SOJ version

72

(S).(SG)

976/816

Now

72-pad SIMM package; TSOP verSion

72

(ASH). (ASHG)

1040/880/760

Now

2Mx32

8MB

MCM32T200
4Mx32

16MB

MGM32400

'.H3MB,.'.

... 4MX$.2"
4Mx32

16MB

8Mx32

32MB

~X3~.: r<·,\~~"
1Mx36

"MCr..j324'p ..

.

'~',?2,'\

4MB

60/70
50/60/70

r.q tll;~1Y!ln

",1'·(5)',.19.<3)."'.,

LJ

i!384q73;'OO" •••• o>"+~t:Jay.t~,o

TSOP

72-pad SIMM package; SOJ version

.pqiJtJl"",slQ(!d.•mQ,dv.!I>VSi~g ~M,D~A!!A'.·'

MGM32420

72

(AOG)

50/60/70

1040/880/760

Now

MGM32400 small outline package, 5.0 V

MGM32423

72

(AOG)

60/70

880/760

Now

MGM32400 small outline package, 3.3 V - TSOP

MCM32800

72

(ASH). (ASHG)

50/60/70

1056/896/776

Now

72-pad SIMM package; SOJ version

MGM32TaoO

72

(ASH). (ASHG)

50/60flO

1056/896/776

Now

72-pad SIMM package; TSOP version

~:~'4;l.~'~~'.~",' I,,'T,",
MCM36104

....2~k~~,. ". '~Ml"""

'

Packaging

··.MQM{l~OQ··

72

, '72.. '"

>

(Aq).·(ASG). f!;l~"l
,iASH$),'
"
(S). (SG)

"" ',A"'i{/(!OlGj.
(S). (SG)

f\.·;.:;':'lr~: ( tIl il:.f'f'2Q<," ":~~< 1"~;~~,,,a.S:M~~C::?~L. ~f:::!"t :-'::
60/70

I';; i. ~\ tlIll!fO

2Mx36

8MB

MCM36204

72

4Mx36

16MB

MCM36400

72

(AS). (ASG). (ASH).
(ASHG)

MGM36404

72

(ASH). (ASHG)

TSOP

60/70

Jii i

1080/900

Now

·11344(U.44." "

'.>l'l!bV(\,

1098/918

Now

. ,l2c;i>"d'l!II4Mp"l''''l~•• o( 'P".lity'l>ppJicet}''''l. "'.
72 pad SIMM package for EGG pinout parity
application; SOJ version

60/70

1360/1160

Now

50/60170

1170/990/855

Now

72-pad SIMM package for parity application; SOJ
version
EGG pinouts, for parity application; SOJ version

60/70

1384/1184

Now

72-pad SIMM package for parity application; SOJ
version

BMx36

32MB

MCM36800

72

(AS). (ASG)

MGM36804

72

(ASH), (ASHG)

50/60/70

1188/1008/873

Now

EGG pinouts, for parity application; SOJ version

1Mx40

4MB
for EDG

MCM40100

72

(AS). (ASG)

60/70

1200/1000

Now

72 pad SIMM package for EGG application; SOJ
version

2Mx40

8MB
for EDG

MGM40200

72

(AS). (ASG)

60/70

1220/1020

Now

72-pad SIMM package for EGC application; SOJ
version

4Mx40

16MB
forEDC

MCM40400

72

50/60/70

1300/1100/900

Now

Replaces MGM40420; SOJ version

.. ':,::

(SH). (SHG)

;:,>:~~~~~~,,::: r:::;:;~:"::'" :~~,i~~~ tF:! t"i fit ,:.:!;:f!:

':"

8Mx40

':>:>":'
( tl i!:rr\)O~:< ,:.~~;::;. ':-::~\~"". "':""~.~pn,,G~~Q~<,"·
..'\.'

MCM40800

72

(SH). (SHG)

1320/1120/970

Now

72-pad SIMM for EGG application; SOJ version

MGM64100

168

(OG)

60/70

2050/1715

Now

16B-pad DIMM package; SOJ version

MCM64Tl00

168

(AOG)

60/70

828/700

Now

166-pad DIMM package; Using 16M DRAM

50/60/70

...:'

.'.'

72 pad SIMM package for EGG, and parity
application; SOJ version

forEDG
lMx64

8MB

Motorola Master Selection Guide

2.8-5

Memory Products

Organization

Byte
Density

Motorola
Part
Number

Pin
Count

MCM64T116

168

Packaging

Access Time
(ns Max)

Operating
Current
(mAMax)

Production

60/70

828/700

4095

lOG)

2Mx64

16MB

MCM64T216

168

lOG)

60/70

TBO

4095

4Mx64

32M

MCM64400

168

lOG)

60/70

2050/1715

1H96

Comments
16S-pad DIMM package; Uses 1M x 16 TSOP
ORAM
16S-pad DIMM package; Uses 1M x 16 TSOP
ORAM
16S-pad DIMM package

NOTE: Package suffixes are enclosed by ( ) in packaging column
AD/ADG = DIMM/Gold Pad DIMM (Board Rev.)
AS =SIMM (Board Revision)
ASG = Gold Pad SIMM (Board Revision)
ASH = Low Profile SIMM

ASHG = Low Profile Gold Pad SIMM
D/DG =Duallnline Module/Duallnline Gold Pad Module
S = SIMM
SC = Industrial Temperature SIMM

SG = Gold Pad SIMM
SH = Short Height SIMM
SSH = Super Short Height SIMM
SHG = Short Height Gold Pad SIMM

DYNAMIC RAMs (HCMOS) (Contact DRAM Marketing)

1Mx4

Memory Products

MCM4L4100C

20/26

300 SOIN)

60/70

110/100

1096

Low power

MCM54100A

20/26

300 SOIN), 300 IT)SOP

60/70

120/100

Now

Fast page mode cycle time

MCM5L4100A

20/26

300 SOIN), 300 IT)SOP

60/70

120/100

Now

Low power

MCM54100A-C

20/26

300 SOJIN), 300 IT)SOP

70/80

100/85

Now

3.3 V Fast page mode cycle time

MCM54100A-V

20/26

300 SOJIN), 300 IT)SOP

70/80

70/60

Now

3.3 V Fast page mode cycle time

MCM5L4100A-V

=45/45 ns
=45/50 ns
=45/50 ns

20/26

300 SOJIN), 300 IT)SOP

70/80

70/60

Now

Low power, 3.3 V

MCM44400B

20/26

300 SOIN)

60/70

110/100

Now

Fast page mode cycle time = 40/45 ns

MCM4L4400B

20/26

300 SOIN)

60/70

110/100

Now

Low power

=45/45 ns

MCM54400A

20/26

300 SOJIN), 300 IT)SOP

60/70

120/100

Now

Fast page mode cycle time

MCM5L4400A

20/26

300 SOJIN), 300 IT)SOP

60/70

120/100

Now

Low power
Industrial temp range (- 40 to + 85°C)

MCM54400A-C

20/26

300 SOIN)

70/80

100/85

Now

MCM5L4400A-C

20/26

300 SOJIN), 300 IT)SOP

70

100

Now

Low power, industrial temp range (--40 to + 85°C)

MCM54400A-V

20/26

300 SOJIN), 300 IT)SOP

70/80

70/60

Now

3.3 V Fast page mode cycle time = 45/50 ns

MCM5L4400A-V

20/26

300 SOJIN), 300 IT)SOP

70/80

70/60

Now

Low power, 3.3 V

MCM518160B

44/50

60/70

180/150

2096

MCM518165B

44/50

60/70

180/150

2096

1K refresh, EDO, 10 row, 10 column

MCM518165BV

42

70/80

145/120

3096

MCM518165BV

44/50

70/80

145/120

3096

3.3 V version of MCM518165B
3.3 V version of MCM518165B

4001T)SOP

2,8-6

1K refresh, FPM, 10 row, 10 column

Motorola Master Selection Guide

Logic: Standard, Special
and Programmable

In Brief ...
Page
Motorola Logic Families: Which Is Besllor You? .... 3.1-1
Motorola Programmable Arrays (MPA) ............ 3.1-5
Selection by Function
Logic Functions ............................ 3.1-13
Device Index .................................. 3.1-40
Ordering Information ........................... 3.1-49
Case Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3.1-53
Packaging Information ......................... 3.1-86
Surface Mount ............................. 3.1-86
Pin Conversion Tables. . . . . . . . . . . . . . . . . . . . . .. 3.1-86
Tape and Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3.1-87
Logic Literature Listing ......................... 3.1-88

This selector guide is a quick reference to Motorola's vast
offering of standard logic integrated circuits. In TTL, popular
due to its ease of use, low cost, medium-to-high speed
operation and good output drive capability, Motorola offers
both LS and FAST. Motorola's CMOS portfolio includes
MC14000B standard CMOS series devices, High-Speed
CMOS consisting of a full line of products that are pinoutcompatible with many LSTTL and MC14000B standard
CMOS logic devices which offers designers a solution to the
long-standing combined barrier - high speed and low
power. Motorola's Emitter Coupled Logic (MECL) is a
non-saturated form of digital logic which eliminates
transistor storage time permitting very high speed operation.
Motorola offers five versions of MECL: MECL 10K, MECL
1OH, MECL III, and the recently introduced families ECLinPS
(ECL in picoseconds) and ECLinPS Lite. Also included are
timing solution products such as clock drivers, clock
generators and programmable delay chips, high
performance and communications products such as VCO's,
prescalers, and synthesizers, and a wide variety of
translators, low-voltage bus interface and serial data
transmission devices. Field programmable logic and in
particular, field programmable arrays, have become the
solution of choice for logic design implementation in
applications where time to market is a critical product
development factor. In addition, reconfigurable arrays have
been used to enhance Customer product flexibility in ways
that no other technology can match.
The Logic I.C. Division publishes a New Product Calendar
quarterly that reflects any recent device releases and the
approximate dates new devices are expected to be released.
This New Product Calendar, BR13321D, can be ordered from
your nearest Motorola Sales Office or from the Motorola
Literature Distribution Center.

Motorola Master Selection Guide

3.0-1

Logic: Standard, Special and Programmable

Logic: Standard. Special and Programmable

3.0-2

Motorola Master Selection Guide

Motorola Logic Families, Which Is Best for You?
By Gary Tharalson, Motorola, Chandler, AZ
Introduction

By selecting the family whose parameters most closely fit
your needs, you can save many future headaches. Obviously,
before selecting a specific device, a detailed review of the
vendor's data sheet specifications is recommended.

When a logic designer is faced with developing a new
product requiring performance significantly different from the
past, it might be well to examine various logic family
alternatives. Selecting a logic family for a new design from
today's rapidly changing semiconductor technologies can be
a perilous task. With the many choices available, it is easy to
under-kill or over-kill an application with inadequate or
excessive capabilities.

Family Comparison
Table 24. compares some typical characteristics of
several popular logic families available in the market today.
The following sections provide brief explanations of the
various parameters.

Table 24. Logic Family Comparison
Logic Families

Typical Commercial
Parameters
(0° to +70°C)

CMOS

TTUABT

ECL

LS

ALS

ABT

FAST

MG

HC

FACT

LVC

LCX

10KH

lOOK

ECLinPS3

E-Lite

9
33
6

7
45
3

2.7
200
3

3
125
2

25
4
100

8
45
4

5
160
2

3.3
200
3.7

3.5
200
3.6

1
330
1

0.75
400
0.70

0.33
1000
0.50

0.22
2800
0.25

5
5

1.2
1.2

0.005
1.0

12.5
12.5

0.0006
0.04

0.003
0.6

0.003
0.8

0.0001
0.6

lE-04
0.3

25
25

50
50

25
25

73
73

+4.5
to 5.5

+4.5
to 5.5

+4.5
to 5.5

+4.5
to 5.5

+3
to 18

+2
t06

+2
t06

+1.2
t03.6

+2
to 3.6

--4.5
to-5.5

--4.2
to --4.8

--4.2 to
-5.5

--4.5
to-5.5

8

8

32164

20

1

4

24

24

24

500
load

500
load

500
load

50Q
load

N/A
N/A

N/A
N/A

N/A
N/A

N/A

NlA
NlA

NlA
N/A

N/A
N/A

YES
NO

YES
YES

N/A
N/A

N/A
N/A

NlA

NlA

N/A
N/A

22
10

22
10

22
10

22
10

30
30

30
30

30
30

30
30

30
30

28
31

41
31

31/31

33
33

YES
YES
NO
NO
NO

YES
YES
YES
YES
NO

YES
YES
NO
YES
NO

YES
YES
YES
YES
NO

YES
YES
NO
NO
YES

YES
YES
NO
YES
YES

YES
YES
YES
YES
YES

NO
YES
NO
YES
YES

NO
YES
NO
YES
YES

YES
NO
YES
NO
NO

YES
NO
NO
NO
NO

NO
NO
YES
NO
NO

NO
YES
NO
NO
NO

Functional Device Types

190

210

50

110

125

103

80

35

272

64

44

48

40

Relative 1-25 Price/Gate

0.9

1

1.6

1

0.9

0.9

1.4

1.8

1.8

2

10

25

32

Speed
OR Gate Prop Delay (tpLH) ns
D Flip-Flop Toggle Rate
MHz
Output Edge Rate
ns
Power Consumption (Per Gate)
Quiescent
Operating (1 MHz)
Supply Voltage
Output Drive

mW
mW
V
mA

5VToierant
Inputs
Outputs

N/A

DC Noise Margin1
High Input
low Input

%
%

28141

Packaging4
DIP
SO
lCC
SSOP
TSSOP

NOTES:
1. Typical noise margin expressed as a percentage of typical output voltage
swing.
2. Announced plans for Motorola offering.

3. ECLinPS is Available in both 10KH and lOOK compatible versions.
4. A "YES" may not include all devices within a family.

VENDORS REFERENCED (DATA BOOK):
lS
Motorola low power Schottky TTL (DL121)
AlS
Texas Instruments Advanced low power Schottky TTL
(SDAD001B)
ABT
Philips Semiconductor (IC23)
FAST
Motorola Advanced Schottky TTL (DL121)
Motorola 14000 Series Metal Gate CMOS (DlI31)
MG
HC
Motorola High-Speed Silicon Gate CMOS (DlI29)

FACT
lCX
lVC
10KH
lOOK
ECLinPS
E-Lite

Motorola Advanced CMOS (DlI38)
Motorola low-Voltage CMOS (BRI339)
Philips low-Voltage CMOS (IC24)
Motorola 10KH Series ECl (DlI22)
National 1OOK Series ECl (FlOOK)
Motorola Advanced ECl (DlI40)
Motorola (ECLinPS Lite) Advanced ECl (DlI4O)

ECLinPS and ECLinPS Lite are trademarks of Motorola, Inc.
FAST and FACT are trademarks of National Semiconductor Corp.

Motorola Master Selection Guide

3.1-1

logic: Standard, Special and Programmable

Logic Families

CMOS

Although there are many family technologies available,
they can be divided into roughly three broad categories:
Transistor-Transistor Logic (TTL), Complementary MetalOxide Semiconductor logic (CMOS), and Emitter-Coupled
Logic (ECL). TTL and ECL are bipolar technologies differing
in implementation techniques, while CMOS (an MOS
technology) differs in fundamental transistor structure and
operation.

Complementary Metal-Oxide Semiconductor (CMOS)
field--effect transistors differ from bipolar both in structure and
operation. The primary advantages of CMOS are its low power
dissipation and small physical geometry. Advances in design
and fabrication have brought CMOS devices into the same
speed and output drive capability as TTL. Again,
enhancements have resulted in the evolvement of additional
classifications: MG (Metal-Gate CMOS), HC (High-speed
silicon-gate CMOS), and FACl'M (Advanced CMOS).
The most recent evolution in CMOS logic has been in
reducing supply voltage without sacrificing performance. The
new LCX family is one outgrowth of this trend. This family
results from the joint efforts of a triumvirate of companies
including Motorola, National, and Toshiba. Although each
company has done its own design and fabrication, they have
mutually agreed to provide identical performance
specifications. In addition to the 3V operating voltage, LCX
inputs and outputs are tolerant of interfacing with 5V devices.

TTL
The designation "bipolar" essentially refers to the basic
component utilized to build this family of integrated circuits, the
bipolar transistor. By employing a bipolar transistor in a logic
function's output driver as well as the input buffer, it results in
a Transistor-to-Transistor (TTL) direct connection. Older
technologies were interconnected via passive components
such as resistors or diodes.
Since the original TTL design, several enhancements have
been employed to reduce power and increase speed.
Common to these has been the use of Schottky diodes which,
ironically, no longer result in strictly TTL connections.
Consequently, the two names, Schottky and TTL, are used in
combination: LS (Low power Schottky), ALS (Advanced Low
power Schottky), and FAST'M (Advanced Schottky) TTL.
The superior characteristics of TTL compared to CMOS, in
the past, have been its relatively high speed and high output
drive; these advantages are rapidly diminishing as described
in the next section. One family of devices, ABT (Advanced
BiCMOS Technology), utilizes TTL circuitry at the inputs and
outputs, and CMOS technology in between-attempting to
combine the advantages of both bipolar and CMOS.

TYPICAL OF ALL OUTPUTS

TTL

VCC

EQUIVALENT OF EACH INPUT
VCC
OUTPUT
INPUT --.-~I-+-...

INPUTS

CMOS

VSS

Logic: Standard, Special and Programmable

3.1-2

Motorola Master Selection Guide

Eel
---1----1--0

OUTPUT
A. B

Ao-~-------+----~

INPUTS

Bo--+-t-{

VEEO-~--~--------~------4-----------~----~

ECl

(edge) rate is highly load dependent, and again, data sheet
specifics must be compared.

Emitter-coupled logic (ECl) derives its name from the
differential-amplifier configuration in which one side of the
diff-amp consists of multiple-input bipolar transistors with
their emitters tied together. An input bias on the opposite side
of the diff-amp causes the amplifier to operate continuously in
the active mode. Consequently, ECl consumes a relatively
substantial amount of power in both states (one or zero) but
also results in the fastest switching speeds of all logic families.
An inherent benefit of ECl is the narrow switching level swing
between devices (approximately 800 mY) which helps to
reduce noise generation.

Power Consumption

The amount of power an application consumes (and the
subsequent heat generated) is frequently of prime
importance. One of the major differences between the three
families, the power parameter may also limit the designer's
choices.
TTL consumes a moderate amount of power and is nearly
constant over operating frequencies up to about 10 MHz;
above 10 MHz it begins to climb rapidly. Although only a few
milliwatts are consumed by each device, in a complete system
a substantial amount of power may be used.

There have also been many evolutionary advancements in
ECl, the following being some of the most prominent: 100K
(1975), 10KH (1981), and ECLinPSTM (1987). Of most recent
vintage is the ECLinPS Lite™ family of single function devices.
By focusing on simplicity, this family achieves very high
performance, while at the same time reducing package size.

CMOS power consumption, on the other hand, is highly
frequency dependent. In quiescent mode (zero frequency), it
consumes almost no power at all, being measured in
microwatts/device. However, its consumption grows almost
linearly with frequency so that at maximum operating
frequency it may be several milliwatts/device. The great power
reduction advantage of CMOS derives from the fact, that in
most applications, the percentage of the total number of
devices operating at high frequencies at any given time is
small; consequently, the average total power consumed by
the system is greatly diminished.
Since power consumption is proportional to the square of
supply voltage, simply redUCing the operating voltage will
have desirable effects. Unfortunately, speed generally falls off
as well. By designing the lCX family specifically for a lower
supply voltage, it was possible to maintain high overall
performance. The lCX family is also designed to interface with
five volt devices, being tolerant of the differences in I/O levels.
Because of its inherent deSign, ECl is the highest power
consumer at frequencies below approximately 50 MHz;
however, at higher frequencies, TTL and CMOS power
consumption can exceed ECL. The amount of power used by
ECl is fairly constant over its entire operating frequency
range. DeSigners of large, high performance ECl systems
may have to employ somewhat more complex cooling and
power distribution techniques.

Speed

Speed is typically the first parameter at which a designer
looks, and when design engineers are asked what features of
a logic family they would like enhanced, usually they want
more speed. But increased speed often brings along many
potential problems such as: increased noise generation,
higher power consumption, increased component and system
cost, more difficult board layout, etc. An assessment of the
other family parameters is usually required before a final
selection is possible.
In Table 24. ,family speed is compared for three
parameters using typical values: propagation delay through a
simple OR gate, flip-flop toggle frequency, and output
switching time. Typical values can be misleading as they are
frequently specified according to different vendor's criteria, but
they are usually close to an average of min and max values.
For final assessment of a particular component's
performance, the min/max spec's provided in most vendor's
data sheets should be examined. Furthermore, switching

Motorola Master Selection Guide

3.1-3

logic: Standard, Special and Programmable

Supply Voltage

Packaging

The power supply voltage required for TTL and ECL is
restricted to fixed values; only a narrow voltage variation is
allowed for the device to remain within specifications. Since
these families also consume substantial amounts of power,
there is a large current flow through the power lines. To avoid
unacceptable voltage fluctuation, various preventive
measures may be necessary such as remote sensing by the
supply regulator, beefing up power buses and filters, and
utilizing multi-layer PC boards with separate power and
ground planes. Typically, a high-speed energy storage
capacitor is required near each logic device; this capacitor
maintains the correct device voltage during high-current
switching.
An important advantage of CMOS is the large range of
supply voltage over which operation is specified. By allowing
systems to be operated at voltages as low as 2V, not only is
power consumption lowered, but noise generation from fast
signal switching is reduced. It must be noted, however, that
operating speed drops off rapidly as the voltage is reduced. As
mentioned previously, this was a significant reason for
developing the LCX family.
Output Drive

An important characteristic of a logic device is its ability to
drive relatively large loads without significant speed
degradation. The older families within TTL, and especially
CMOS, had only limited drive capability (below 10 mAl. All
advanced logic family versions have significantly increased
drive capacity, and several (FACT, LCX and all ECL) are
capable of driving 50 ohm transmission lines directly.
Furthermore, because of the symmetrical sink/source
capability of FACT and LCX, their rise and fall times are nearly
equal, resulting in balanced delay times.
5V Tolerant Input/Output

Because of the limited number of functions available in the
new low voltage CMOS families, a designer might might have
to mix 3V and 5V devices, each operating from 3V and 5V rails,
respectively. Unless the 3V device was specifically designed
with proper protection to tolerate 5V at its input or output, it may
not survive.
Noise Margin

Noise immunity refers to the resistance of a logic device to
undesired switching. Depending on the input level, a noise
glitch that causes a transient across the input switch pointfrom
either a high or low level can result in erroneous operation.
Clearly, the more voltage difference there is between the
switch point and the normal input high and low levels, the more
immunity a logic family has to erroneous switching. In
Table 24. ,these differences are expressed as a percentage
of the swing between typical output high and low voltage logic
levels. High input noise margin is calculated from the formula:
HNM =

VOH - VIH

, and for low input noise margin,

VOH - VOL
LNM =

VIL - VOL
VOH - VOL

Logic: Standard, Special and Programmable

3.1-4

The venerable Dual-Inline package (DIP) is rapidly being
replaced by Small Outline (SO), Shrink Small Outline (SSOP),
Thin Shrink Small Outline (TSSOP), and Leadless Chip
Carrier (LCG) packages for surface mounting. Savings in
footprint area of up to 90% are possible with these newer
packages.
Device Types

In general, the older the family the larger the quantity of
differentfunctional devices available. This is only natural since
it takes time (and substantial resource investment) to design
and reliably manufacture increaSingly more complex devices.
The newer TTL and CMOS families will undoubtedly grow, but
because of competition from higher integrated devices, will be
more limited in scope.
Cost

Here again, the age of a family has a substantial bearing on
its relative selling price. The older families have benefited
longer from manufacturing learning and volume curve cost
reductions. Newer technologies, because of their inherently
more complex process requirements, increased performance
improvements, and higher cost of production, are priced
higher but should decline over time.
Mix and Match

Many designers have found that the best approach to
achieving their particular application performance goal is to
combine devices from several families. The obvious
advantage of this is to optimize the requirements of selected
portions of a design, whether it is for speed, power
consumption, output drive, cost, etc. Some disadvantages are
that devices must be analyzed and tested for compatibility,
inventories may increase, and some performance parameters
may be compromised.
Conclusion

The diversity of logic families available to today's logic
designer may be likened to a bad news/good news scenario.
The bad news is that you have huge ratios between the
highest and lowest performance values-speeds of 500:1,
power at 100,000:1, output drive at 24:1, etc. The good news
is that you have lots of choices-it wasn't too many years ago
that there were very few. By examining and comparing each
family's parameters, an optimal selection can result.
A few potential users of standard logic devices may worry,
that because of the trends towards higher-integration chips,
some vendors will abandon the older product lines. This may
eventually happen; however, the current demand, prOjected
for at least the next decade, indicates that these families have
a very solid future. The diverse applications that keep arising
for semiconductor products that are inexpensive and reliable
continue to mount. Until some totally revolutionary
development should occur, these "oldies, but goodies" will be
around for a long time to come.

Motorola Master Selection Guide

INTRODUCTION TO
MOTOROLA PROGRAMMABLE ARRAYS

Field programmable logic and in particular, field
programmable arrays, have become the solution of choice
for logic design implementation in applications where time to
market is a critical product development factor. In addition,
reconfigurable arrays have been used to enhance
Customer product flexibility in ways that no other technology
can match.

To reduce design cycles, designers have also turned
towards high level design languages and logic synthesis
tools. Many programmable logic solutions are poorly suited
to this design methodology, however. An incompatibility
exists between logic synthesis algorithms originally
developed for gate level deSign and the block-like
structures found on many programmable logic devices. This
can result in significant under utilization or degraded
performance. In either case a more expensive device is
required. Real gate level programmable devices are ideally
suited to this design methodology.
When schematic based design methods are used, some
programmable logic solutions impose significant constraints
on design implementation to insure satisfactory results. This
imposition tends to bind the design to a particular
programmable device and requires a significant learning
investment. Any design specification changes which impact
design decisions made to fit this imposed structure can
have disastrous effects on utilization and performance and
potentially require a more expensive device or even a costly
redesign. Gate level programmable devices coupled with
sophisticated, timing driven, implementation tools minimize
device specific optimization.
Any design process includes a significant amount of
learning. Usually engineers spend most of this time learning
about product requirements or prototyping critical portions of
the design to prove implementation feasibility. Many
programmable logic solutions are not push bullon; time
must be spent learning programmable device architecture or
implementation tool quirks. Worse yet, the design may
require modification or manual component placement to
meet design targets. The cost? Time to market.
The reconfigurable Motorola Programmable Array (MPA)
and MPA design system maximize application flexibility and
minimize time to market by delivering a gate level, push
bUllon, programmable logic solution.

Microprocessors have traditionally been used to satisfy
time to market and end product flexibility needs. This
solution may not meet performance constraints and lacks
the concurrency possible in an unconstrained hardware
design. Typical design processes, therefore, reach a pOint
where the overall design is partitioned into hardware and
software components. An interface is defined and the
design process continues along two parallel paths.
Sometime later, the software and hardware components
must be integrated. Problems usually develop at this point
because of interface misinterpretation or partitioning that
cannot meet design requirements. This impacts the
hardware, the software and the schedule. If the hardware
design is realized in programmable logic, the hardware can
be manipulated as easily as the software.
Products which adapt to the end users particular
requirements through self directed or end user directed
reconfiguration are becoming more prevalent. As the
number of modes of operation increases, mode specific
hardware becomes a less cost effective solution. In the case
where the end user is truly directing the adaptation,
predetermined hardware solutions become untenable.
Reconfigurable logic enables design solutions where
dynamic hardware-software repartitioning is possible.
Programmable logic not only vastly improves the time
necessary to implement a static design, but significant time
to market and product feature benefits can be realized when
hardware can be dynamically altered as easily as software.

MPA1016

621621
1EEIEE
Motorola Master Selection Guide

MPA1036

MPA1064

IEmIEmI

MPAll00

11111
11111

§!II§!I

3.1-5

Logic: Standard, Special and Programmable

MPA1000
Programmable Arrays
Motorola Programmable Array (MPA) products are a high density, high
performance, low cost, solution for your reconfigurable logic needs. When
used with our automatic high performance design tools, MPA delivers
custom logic solutions in minutes rather than weeks. And the low cost
keeps those solutions competitive throughout the product lifecycle.
The MPA architecture has solved the historical problems associated
with fine grain devices without sacrificing re-programmability, reliability, or
cost. MPA1000 devices are reprogrammable SRAM based products
manufactured on a standard 0.511 Leff CMOS process with logic
capacities from 3,500 to more than 22,000 equivalent FPGA gates. MPA
Logic resources hold a single gate or storage element providing a highly
efficient, adaptable, design implementation medium. Gate level logic
resources, abundant hierarchical interconnection resources and
automatic, timing driven, tools work together to quickly provide design
implementations that meet timing constraints without sacrificing device
utilization.
Staying focused on end product design rather than implementation
tools or device architecture gets the design done faster and, unlike other
programmable solutions, without programmable logic device specificity to
impede future design migration efforts. The combination of automatic
tools and gate level architecture is ideal for traditional schematic driven or
high level language based design methodologies. In fact, logiC synthesis
tools were originally designed for and produce the most efficient results
when targeting gate level devices.
High MPA1000 register count and controlled clock skew is ideal for
designs employing pipelining techniques such as communications. The
unique set of MPA1000 I/O programming options make these devices
suitable for industrial and computer InterfaCing circuits.

MPA1016
MPA1036
MPA1064
MPA1100

PROGRAMMABLE ARRAY
3,500 to 22,000 GATES

•
•
•
•
•
•
•
•

Multiple I/O from 80-200 I/O Pins
Programmable 3V/5V I/O at Any Site
Multiple Packaging Options
Fine Grain Structure Is Optimized for
Logic SyntheSis
Programmable Output Drive,
6/12mA @ 5.0V
High Register Count, with 560-2,900
Flip-Flops
IEEE 1149.1 JTAG Boundary Scan
Eight Low-Skew «1ns) Clocks

MPA1000 Family Members
FPGA
Gates

Part No.

Logic
Cells

Internal
Flip-Flops

I/O Cell
Flip-Flops

Signal I/O
Pads Max.

Packages

Availability

3500

MPA1016FN
MPA1016DD

1600

400

160

80

84-Pin PLCC
128-Pin POFP

April 1996
April 1996

8000

MPA1036FN
MPA1036DD
MPA1036DH
MPA1036HI

3600

900

240

120

84-Pin PLCC
128-Pin POFP
16o-Pin POFP
181-Pin PGA

NOW
April 1996
NOW
NOW

14200

MPA1064DH
MPA1064DK
MPA1064KE

6400

1600

320

160

16o-Pin POFP
208-Pin POFP
224-Pin PGA

April 1996
2096
1096

22000

MPA1100DK
MPAll00HV

10000

2500

400

200

208-Pin POFP
299-PinPGA

3096
3096

Logic: Standard, Special and Programmable

3.1-6

Motorola Master Selection Guide

MPA1000 Design System Product Description
Overview
The Motorola Programmable Array (MPA) design system is a bridge between a design capture environment and Motorola
field programmable arrays. The MPA design system automatically transforms designs into device configurations which, when
loaded into an MPA device, realize a design. A design is automatically analyzed, optimized, transformed into MPA cells,
partitioned, placed and routed based on timing constraints for every path in the design. MPA design tools understand and
optimally utilize the MPA device ·architecture; this eliminates the need to learn a new set of rules and makes these tools ideally
suited for use with logic synthesis. Full incremental design support reduces design implementation time and powerful library
retargeting capabilities allow you to reuse designs which may have been implemented on less capable devices. The MPA
design system operates on existing hardware platforms and supports design capture and simulation tools from more than 10
vendors. All these features plus on-line, hypermedia, help make the MPA design system a powerful yet extremely easy to use
design implementation engine.
Features
• Push Button Implementation

• Layout Delay extraction for post layout simulation

• Optimal Use of MPA Device Resources
• Optimal Results with Gate Level Design Input

• Layout viewer
• Incremental design support

• Library of Common MSI Functions

• On-line, hypermedia, documentation

• Design Flow Manager

• Supports all popular design capture and simulation tools

• Design Retargeter
• Timing Driven with Integrated Static Timing Analysis

• Lowest cost FPGA development systems.
• Instant access; Downloading via the internet (WWW, tip).

Design Importation
•
•
•
•
•

Read Appropriate Rules File
Retarget to MPA Primitives
Macro Expansion
Design Optimization
Design Rule Checks

Constraint Generation
• Read User Constraints
• Path Enumeration
• Path Constraint Generation

Timing Driven Autolayout
•
•
•
•
•

Partition Design Into Clusters
Assign Clusters to Zones
Global Place & Route
Zonal Place & Route
Continuous Slack
Redistribution

1---++---1

Configuration
• Read Stored Layout
• Construct Bitstream

MPA
Device

Motorola Master Selection Guide

3.1-7

Logic: Standard, Special and Programmable

Push Button Design Implementation
The MPA design system minimizes training investment
and automatically generates design implementations which
meet timing constraints.
The gate level logic and abundant hierarchical routing
resources of the MPA device present a rich implementation
media for design implementation. MPA design tools
understand and optimally utilize the MPA device resources
so there are no elaborate rules to learn or design
modifications required to begin design capture. Staying
focused on end product design rather than implementation
tools or device architecture gets the design done faster and,
unlike other programmable solutions, without programmable
logic device specificity to impede future design migration
efforts. The combination of automatic tools and gate level
architecture is ideal for traditional schematic driven or high
level language based design capture methods. In fact, logic
synthesis tools were originally designed for and produce the
most efficient results for targeting gate level devices.
A design is analyzed, optimized, transformed into MPA
cells, partitioned, placed and routed based on timing
constraints for all paths in the design - automatically. A
netlist from one of the popular design capture systems or an
existing XNF or LPM netlist is imported into the MPA design
system. The logic is mapped to a series of MPA cells and
the entire resulting nellist is optimized and checked. Based
on a Simple clock specification, the MPA design system
generates timing constraints for all paths in the design.
During automatic partitioning, placement and routing path
slack time is constantly redistributed insuring only the
resources required to meet timing requirements are
consumed. Because MPA tools implement the design
according to constraints, tool induced design iterations are
virtually eliminated. Completed layouts can be transformed
into device configurations, as well as annotated simulation
netlists. A layout browser is also available.
The MPA design system also includes complete on-line,
hypermedia, help covers the device, the design system and
the integration kits. Integration kits for Viewlogic, Exemplar,
VHDL (1076), Verilog (OVI) and OrCAD are included
(contact your vendor for additional kits).AII these features
add up to a powerful yet extremely easy to use design
implementation engine for the MPA product family.
Design Importation
Designs can be captured using schematics, a high level
language, or a combination of these entry methods using
commercially available design capture and logic synthesis
software and the appropriate interface kit. Alternatively,
existing designs can be retargeted from other
programmable logic devices to the MPA device using
commercial logic synthesis tools or the powerful retargetting
capabilities provided with MPA design system.
DeSign importation begins with a netlist and an optional
clock specification file. The clock specification file provides a
mechanism for the user or design capture tools to document
system level timing requirements. In addition, a rich set of
attributes can be attached to specific components or nets

Logic: Standard, Special and Programmable

3.1-8

within the design to specify timing and design pinout
constraints.
A retargetting rules file is read and the input netlist is
transformed into a series of MPA cells and associated
interconnections. Rules files provide a mechanism to
perform attribute mapping, cell mapping and macro
expansion. By creating custom rule files, the user can
extend the importation process from arbitrary sources. The
MPA design system comes with rules for it's native
library/EDIF. The resulting netlist is optimized to clip unused
logic and remove redundant logic. For example: each MPA
cell has programmable input inversion capability. All
Inverters or non-inverting buffers can be removed from the
nellist and replaced with signal sense information attached
to each input.
A series of design rule checks are performed to insure
design integrity before the layout process begins.
Constraint Generation
Timing constraints, the optimized MPA nellist and static
timing analysis is used to generate path slack constraints for
all paths in the design. Each unique signal pathway
between a register output and a register input throughout
the design are enumerated. The total logic and estimated or
real wire delays along the path are summed. The time
between the active upstream register clock edge and the
next active downstream clock edge minus the downstream
register setup time is subtracted from the total path delay.
This difference is called path slack. If any path in the design
has a negative slack value, the implementation will not
function at the required clock rate(s).
Path constraints are utilized throughout the layout
process to insure that a design implementation which meets
timing constraints is automatically generated. If no clock or
timing specifications are provided, the MPA design system
uses the fastest possible clock based on very small net
delay estimates to generate the path constraints. This
usually results in the best possible implementation, but may
take longer than the time required to generate a satisfactory
rather than best possible result.
Contrast this to other programmable logic design tools
which only provide manual net constraint annotation or net
criticality assignment. In these cases significant effort is
necessary to generate constraints and many costly
iterations are required to tune these constraints for a given
design. If any changes are made to the deSign, another
costly round of iterations is required.
Autolayout
The autolayout process makes use of the hierarchical
organization of the MPA device to minimize run time and
deliver implementations that meet timing requirements.
Designs which have diverse timing requirements are ideally
implemented because path slack estimates are refined
throughout the autolayout process insuring only the
resources required to meet timing requirements are
consumed.
The process begins by flattening the design and
partitioning it into small component groups of approximately
the same size called clusters. A cluster boundary delay

Motorola Master Selection Guide

estimation is applied to pull the most tightly constrained
paths into a minimum number of clusters. The clusters are
then assigned to zones talking into account zonal boundary
delay cost and relative zone placement delay costs. Other
costs like total number of port connections per zone and are
also considered. As assignment proceeds, cluster and zone
boundary delay costs are added to each path and slack is
recomputed.

transformed into an appropriately formatted delay
annotation file or annotated nellist quickly and easily. The
annotated delay information represents the worst case
delays for a given device speed grade.
Chipview

While the MPA design system provides a rich set of
reports describing the implementation of a deSign, a
graphical view of the implementation can be indispensable
for reviewing overall layout quality. Chipview provides a
graphical view of a completed layout. Chipview can be
useful during initial design iterations to visually verify I/O pin
placements before commencing PCB layout, for example.

Next global placement and routing is done. Global routes
begin and end on either I/O cells or port cells. Intrazone
placement and routing is deferred to a later phase. During
global routing all the port cell and I/O cell locations are fixed
and the connections between them established. High fanout
nets are constructed in a highly regular manner to insure
efficient resource utilization. As in partitioning, slack
estimates are refined throughout global routing.

Configuration

A layout can be transformed into a device configuration
which, when loaded into the appropriate MPA device,
produces a physical design realization. Many formatting
options are available. The MPA download pod can be used
to emulate a serial PROM. Using the pod, device
configuration files can be downloaded to a device directly
from the PC or workstation development environment.

Finally the intrazonal placement and routing is done. Cells
assigned to a particular zone are placed and routed to other
zone cells or zone port cells. Port cells and core cells are
constructed to allow port swapping. Core cells can be
routed through if necessary. Allowing core cells to act as
routing cells allows dynamic adjustment of routing resources
within the zone. Dynamic resource adjustment is a powerful
design specific adaptation mechanism.

Integration Kits

The MPA design system can be used with a large number
of commercial electronic design automation software. Figure
X-X shows the currently supported vendors and tools. For
each supported vendor, an integration kit is provided which
facilitates MPA design within that vendors' environment.
Many of these kits are available from Motorola and included
at no charge on the MPA design system CD-ROM. Other
kits can be acquired directly from the vendor. Refer to the
MPA Design System Product List for more irformation.

This process produces a layout from which device
configurations, delay back annotations, and chipviews can
be generated.
Incremental Design Support

When
specification
changes
necessitate design
iterations, simply push the button again. Constraints are
automatically recalculated and auto layout only reworks
those portions of the design which have changed. Full
incremental design support means simple design changes
to facilitate design verification can be made quickly and
easily.

Low Cost, Easy Access

MPA Design systems are easy to use, competitively
priced and widely available. Copies of MPA deSign system
software supporting up to 8000 gates can be downloaded
from
the
World
Wide
Web
(WWW)
@
hUp://Design-NET.com/fpga. Complete kits including
download pod, evaluation board, MPA device, CD-ROM
and documentation can be ordered from your local
authorized Motorola distributor or Motorola sales
representative (see appendix Z).

Delay Back Annotation

Designs can be verified through numerous methods. One
particularly useful method is the annotation of device and
implementation specific delays back into the original
simulation environment to improve system or device level
simulation accuracy. A MPA device layout can be

F~, ~~'~W~H~'NI~.

T~/4

Motorola Master Selection Guide

HPAt

3.1-9

Logic: Standard, Special and Programmable

c8
~.

W
::J

aT

SOFTWARE FLOWS - WORKSTATION and PC

Pen
16o
§I

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0-

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a

to

til
3
3

§.
iD

~

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o

s::
~

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ien
 2000 Volts
• 8-Pin PDIP and SOIC; 2o-Pin PLCC Packages
• Commercial (0 to +70°C) and Industrial (-40 to +85°C)

PSUFFIX
PLASTIC PACKAGE
CASE 626-05

8-Lead Pinouts
(Top View)

8~
1

DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751--05

•
3

2D-Lead Pinout
(Top View)

NC Vpp

NC

4

FNSUFFIX
PlCC PACKAGE
CASE 775--02

NC CEO

NC

NC

VCC

NC

NC

NC

DATA

Vss

NC

NC

PIN NAMES
Pins

Function

DATA
ClK
BESETIOE
CE

Data 1/0
Clock
Reset Input and Output Enable
Chip Enable Input
Ground
Chip Enable Output
Programming Voltage Supply
+4.5 to 6.0V Power Supply
Not Connected

~
CEO
VPP
VCC
NC

ClK NC RESETI NC CE
OE

logic: Standard, Special and Programmable

3.1-12

Motorola Master Selection Guide

Selection by Function
In order to better serve our customers, we have made some modifications to the Selection by Function portion of the Logic
Selector Guide. For easy selection of Logic's newer, more complex functions, as well as standard family functions, refer to the
subject index below. Within the Selection by Function tables on the next 23 pages, you will find functions sorted by these broad
subjects, and then broken down alphabetically into more precise functions.

Logic Functions
ARITHMETIC OPERATORS .................
BOUNCE ELIMINATOR .....................
BUFFERS .................................
BUFFERS, 3-8TATE ........................
BUS INTERFACE ...........................
CBM ......................................
CLOCK DISTRIBUTION CHiPS ..............
CLOCK DRiVERS ..........................
COAX CABLE DRiVERS ....................
COMPARATORS ...........................
CONVERTERS .............................
COUNTERS ...............................
DECODER/DEMULTiPLEXERS ..............
DETECTORS ..............................
DISPLAY DECODE DRiVERS ................
DiViDERS .................................
DRiVER ...................................
EDACs ....................................
ENCODERS ...............................
ENCODER/DECODERS .....................
EXPANDERS ..............................
FLiP-FLOPS ...............................
GATES, AND/NAND ........................
GATES, COMPLEX .........................
GATES, EXCLUSIVE OR/EXCLUSIVE NOR ...
GATES, NOR ..............................
GATES, OR ................................

Motorola Master Selection Guide

3.1-14
3.1-14
3.1-14
3.1-14
3.1-14
3.1-17
3.1-17
3.1-17
3.1-18
3.1-18
3.1-19
3.1-19
3.1-21
3.1-21
3.1-22
3.1-22
3.1-22
3.1-22
3.1-22
3.1-22
3.1-22
3.1-23
3.1-25
3.1-27
3.1-27
3.1-28
3.1-28

3.1-13

INDUSTRIAL CONTROL UNIT ...............
INVERTERS ...............................
INVERTER/BUFFERS,2-STATE .............
LATCHES .................................
MEMORY SUPPORT .......................
MISCELLANEOUS .........................
MULTIPLEXER/DATA SELECTORS ...........
MULTIVIBRATORS .........................
OSCiLLATORS .............................
OSCILLATORITIMERS ......................
PARITY CHECKERS ........................
PHASE-LOCKED LOOP ....................
PRESCALERS .............................
PROGRAMMABLE DELAY CHiPS ............
PROMs ...................................
RAMs .....................................
RECEiVERS ...............................
REGiSTERS ...............................
REGISTER FILES ..........................
SCHMITT TRIGGERS .......................
SCSI BUS TERMINATORS ..................
SHIFT REGiSTERS .........................
SyNTHESiZERS ...........................
TRANSCEiVERS ...........................
TRANSLATORS ............................
VCO ......................................

3.1-29
3.1-29
3.1-29
3.1-30
3.1-31
3.1-31
3.1-31
3.1-33
3.1-34
3.1-34
3.1-34
3.1-34
3.1-34
3.1-35
3.1-35
3.F35
3.1-35
3.1-36
3.1-36
3.1-36
3.1-36
3.1-36
3.1-38
3.1-38
3.1-38
3.1-39

Logic: Standard, Special and Programmable

Selection by Function

I

Description

Tech.

Device(s)

Pins

I DIP I SM

ARITHMETIC OPERATORS

TTL
TTL
TTL
TTL

MC74F181

-

24

N

DW

MC74F381

-

20

N

DW

-

20

N

DW

24

N,J

DW

4-Bit Arithmetic logic UniVFunction Generator

ECl

MC10H181

-

24

P,l,
PW,
lW

FN

ECl

MC10181

P,l

TTL
TTL
TTL

MC74F283

-

24

4-Bit Binary Full Adder With Fast Carry

4-Bit Full Adder

CMOS

MC14008B

9's Complementer

CMOS

MC14561B

BCD Rate Multiplier

CMOS

Carry lookahead Generator

TTL

Dual 2-Bit AdderlSubtractor

ECl

MC10H180

4-Bit Arithmetic logic Unit

MC74F382
SN54lS181

SN74lS181

16

N

D

SN54LS83A

SN74lS83A

14

N,J

D

SN54lS283

SN74lS283

16

N,J

D

-

16

P,l

D

-

14

P

D

MC14527B

-

16

P

DW

MC74F182

-

16

N

D

16

P,l

FN

P,l

ECl

MC10180

-

16

look Ahead Carry Block

ECl

MC10H179

16

P,l

FN

NBCDAdder

CMOS

MC14560B

16

P,l

D

Triple Serial Adder (Negative logic)

CMOS

MC14038B

-

16

l

BOUNCE ELIMINATOR

IHex Contact Bounce Eliminator

ICMOS IMCl4490

16

I P,l I DW

BUFFERS

-

1:2 Differential Fanout Buffer

ECl

MC100lVElll

8

D

2:8 Differential Fanout Buffer

ECl

MC100lVE310

MC100E310

28

FN

Dual 1:3 Fanout Buffer

ECl

MC100lVEL13

MC100EL13

20

Expandable Buffer

DTl

MC832

low Voltage Dual 1:4, 1:5 Differential Fanout Buffer, ECUPECl
Compatible

ECl

MC100lVE210

low-Voltage CMOS Octal Buffer, 3-State, Non-Inverting With 5V
Tolerant Inputs and Outputs

CMOS

MC74lCX244

low-Voltage CMOS Octal Buffer, 3-State, Inverting With 5V
Tolerant Inputs and Outputs

CMOS

low-Voltage CMOS Octal Buffer Flow Through Pinout, 3-State,
Non-Inverting With 5V Tolerant Inputs and Outputs

-

14

MC100E210

DW
P,l

28

FN

20

DW,M,
DT

MC74lCX240

-

20

DW,M,
DT

CMOS

MC74lCX541

-

20

DW,M,
DT

low-Voltage CMOS Octal Buffer Flow Through Pinout, 3-State,
Inverting With 5V Tolerant Inputs and Outputs

CMOS

MC74lCX540

20

DW,M,
DT

low-Voltage Quiet CMOS Octal Buffer

CMOS

MC74lVQ541

-

20

D,M,
SD,DT

low-Voltage Quiet CMOS Octal Buffer, 3-State, Non-Inverting

CMOS

MC74lVQ244

-

20

DW,M,
SD,DT

low-Voltage Quiet CMOS Octal Buffer, 3-State, Inverting

CMOS

MC74lVQ240

-

20

DW,M,
SD,DT

low-Voltage Quiet CMOS Quad Buffer, 3-State, Non-Inverting

CMOS

MC74LVQ125

-

14

D,M,
SD,DT

TTL
TTL

MC74F828

-

24

N

DW

lQ-Bit Buffer/Line Driver (Non-Inverting), With 3-State Outputs

MC74F827

-

24

N

DW

3-Bit Registered Bus Transceiver, 25Q Cutoff Outputs

ECl

MC10E336

BUFFERS, 3-STATE

BUS INTERFACE

1Q-Bit Buffer/Line Driver (Inverting), With 3-State Outputs

logic: Standard, Special and Programmable

3.1-14

MC100E336

28

FN

Motorola Master Selection Guide

Selection by Function

I

Tech.

Description

Device(s)

Pins

I DIP I SM

BUS INTERFACE

3-Bit Scannable Registered Bus Transceiver

ECl

MC10E337

32-Bit to 32116/8-Bit Dynamic READIWRITE Bus Sizer

CMOS

MC68150"33

MC100E337

CMOS

MC68150"40

9-Bit Bus Interface, NINV, 3 State Outputs

TTL

MC74F823

-

28

FN

68

FN

68
24

FN
N

Bus Driver

ECl

MC10128

-

16

l

Dual Bus Driver/Receiver With 4-to-1 Output Multiplexer (25Q)

ECl

MC10H332

-

20

P,l

Hex 3-State Non-Inverting Buffer With Separate 2-Bit and 4-Bit
Sections

CMOS

MC54HC367

MC74HC367

16

N,J

DW
FN

Hex Buffer 4i2-Bitllnverting With 3-State Outputs

TTL

SN54lS368A

SN74lS368A

16

N,J

Hex Buffer 4/2-BitlNon-lnverting With 3-State Outputs

TTL

SN54lS367A

SN74lS367A

16

N,J

D

Hex Buffer Driver, 4+2-Bit, Inverting, With 3-State Outputs

TTL

MC74F368

16

N

D

-

D

Hex Buffer Gated Enable Inverting With 3-State Outputs

TTL

SN54lS366A

SN74lS366A

16

N,J

D

Hex Buffer Gated Enable Non-Inverting With 3-State Outputs

TTL

SN54lS365A

SN74lS365A

16

N,J

D

Hex Buffer/Driver Gated Enable Inverting, With 3-State Outputs

TTL

MC74F366

16

N

D

Hex Buffer/Driver Gated Enable Non-Inverting, With 3-State
Outputs

TTL

MC74F365

-

16

N

D

-

16

N

D

16

P,l

D

Hex Buffer/Driver, 4+2-Bit, Non-Inverting, With 3-8tate Outputs

TTL

MC74F367

Hex With 3-State Outputs Buffer (Non-Inverting)

CMOS

MC14503B

Hex With 3-State Outputs Inverting Buffer With Common Enables

CMOS

MC54HC366

Hex With 3-State Outputs Inverting Buffer With Separate 2-Bit and
4-Bit Sections

CMOS

MC74HC368

Hex With 3-State Outputs Non-Inverting Buffer With Separate
2-Bitl4-Bit Sections

CMOS

MC54HC365

Octal 3-State Non-Inverting Bus Transceiver With lSTTl
Compatible Inputs

CMOS

MC54HCT245A

Octal Bidirectional Transceiver With 3-State Inputs/Outputs
Octal Bidirectional Transceiver With 3-State Outputs

Octal Bidirectional Transceiver With 8-Bit Parity Generator
Checker, With 3-State Outputs

N,J
N

MC74HC365

16

N,J

DT

MC74HCT245A

20

N,J

DW,
SD,DT

20

N

DW

20

N

DW

20

N

DW

20

N

DW

20

N

DW

20

N

DW

CMOS

MC74AC245
MC74ACT245

CMOS

MC74AC620

CMOS

MC74ACT620

CMOS

MC74AC623

CMOS

MC74ACT623

-

CMOS

MC74AC640

-

20

N

DW

CMOS

MC74ACT640

20

N

DW

CMOS

MC74AC643

20

N

DW

CMOS

MC74ACT643

20

N

DW

TTL

MC74F245

-

20

N

DW

24

N

DW

24

N

DW

20

N

DW

TTL

MC74F657A
MC74F657B

Octal Bidirectional Transceiver, With 3-State Inputs/Outputs

TTL

MC74F1245

Octal Buffer With 3-State Outputs

Motorola Master Selection Guide

16
16

-

CMOS

TTL

Octal Buffer/Line Driver With 3-8tate Outputs

MC74HC366

(81lS95)

TTL

SN54lS795

SN74lS795

20

N,J

DW

(81lS96)

TTL

SN54lS796

SN74lS796

20

N,J

DW

(81lS97)

TTL

SN54lS797

SN74lS797

20

N,J

DW

(81lS98)

TTL

SN54lS798

SN74lS798

20

N,J

DW

TTL

SN54lS244

SN74lS244

20

N,J

DW

TTL

MC74F240

20

N

DW

TTL

MC74F241

20

N

DW

-

TTL

MC74F244

20

N

DW

TTL

SN54lS240

SN74lS240

20

N,J

DW

TTL

SN54lS241

SN74lS241

20

N,J

DW

3.1-15

logic: Standard, Special and Programmable

Selection by Function
Description

Tech.

Device(s)

Pins

I DIP I SM

BUS INTERFACE

Octal BufferlLine Driver With 3-State Outputs

Octal Bus Transceiver

TTL

SN54LS540

SN74LS540

20

N,J

DW

TTL

SN54LS541

SN74LS541

20

N,J

DW

CMOS

MC74AC241

20

N

DW

CMOS

MC74AC244

-

20

N

DW

CMOS

MC74ACT244

-

20

N

DW

CMOS

MC74AC540

20

N

DW

20

N

DW

20

N

DW

20

N

DW

20

N

DW
DW

CMOS

MC74ACT540

CMOS

MC74AC541

CMOS

MC74ACT541

CMOS

MC74AC240

-

CMOS

MC74ACT240

-

20

N

CMOS

MC74ACT241

-

20

N

DW

TTL

SN54LS245

SN74LS245

20

N,J

DW

SN74LS623

20

N,J

DW

20

N

DW

20

N,J

DW
DW

TTL

SN54LS623

Octal Bus Transceiver, With 3-State Outputs

TTL

MC74F623

Octal Bus Transceiverllnverting With 3-5tate Outputs

TTL

SN54LS640

TTL

MC74F620

-

20

N

TTL

MC74F640

-

20

N

DW

Octal Bus Transceiver/Non-Inverting With 3-State Outputs

TTL

SN54LS645

20

N,J

DW

Octal Bus Transceiver/Register With 3-State Outputs
Non-Inverting

CMOS

MC74AC652

-

24

N

DW

CMOS

MC74ACT652

N

DW

TTL

MC74F544

24

N

DW

Octal Registered Transceiver Non-Inverting, With 3-State Outputs

TTL

MC74F543

24

N

DW

Octal Transceiver/Register With 3-State Outputs Non-Inverting

CMOS

MC74AC646

24

N

DW

CMOS

MC74ACT646

24

N

DW

CMOS

MC74AC648

24

N

DW

CMOS

MC74ACT648

24

N

DW

Octal Transceiver/Register, With 3-5tate Outputs

TTL

MC74F646

-

24

Octal Registered Transceiver Inverting, With 3-State Outputs

24

N

DW

Octal With 3-State Non-Inverting Buffer/Line Driver/Line Receiver

CMOS

MC54HC241A

MC74HC241A

20

N,J

DW

Octal With 3-State Non-Inverting Buffer/Line Driver/Line Receiver
With LSTTL Compatible Inputs

CMOS

MC54HCT241A

MC74HCT241A

20

N,J

DW

CMOS

MC54HCT244A

MC74HCT244A

20

N,J

DW,
SD,DT

Octal With 3-State Outputs Inverting Buffer/Line Driver/Line
Receiver

CMOS

MC54HC240A

MC74HC240A

20

N,J

DW,
DT

MC74HC540A

20

N,J

DW

20

N

DW,
SD,DT

Octal Transceiver/Register With 3-5tate Outputs Inverting

CMOS

MC54HC540A

Octal With 3-5tate Outputs Inverting Buffer/Line Driver/Line
Receiver With LSTTL Compatible Inputs

CMOS

MC74HCT240A

SN74LS640

SN74LS645

-

Octal With 3-State Outputs Inverting Bus Transceiver

CMOS

MC54HC640A

MC74HC640A

20

N,J

DW

Octal With 3-State Outputs Non-Inverting Buffer/Line Driver/Line
Receiver

CMOS

MC54HC541A

MC74HC541A

20

N,J

DW

Octal With 3-State Outputs Non-Inverting Buffer/Line DriverlLine
Receiver With LSTTL Compatible Inputs

CMOS

MC74HCT541A

20

N

DW

Octal With 3-State Outputs Non-Inverting Buffer/Line DriverlLine
Receiver

CMOS

MC54HC244A

MC74HC244A

20

N,J

DW,
SD,DT

-

Octal With 3-State Outputs Non-Inverting Bus Transceiver

CMOS

MC54HC245A

MC74HC245A

20

N,J

DW

Octal With 3-State Outputs Non-Inverting Bus Transceiver & D
Flip-Flop

CMOS

MC54HC646

MC74HC646

24

N,J

DW

Quad Buffers With 3-State Outputs

TTL

SN54LS125A

SN74LS125A

14

N,J

D

Logic: Standard, Special and Programmable

3.1-16

Motorola Master Selection Guide

Selection by Function

I

Description

Device(s)

Tech.

Pins

I DIP I SM

BUS INTERFACE

Quad 3--State Non-Inverting Buffers
Quad Buffer With 3-State Outputs

CMOS

MC74HC125A

CMOS

MC74HC126A

CMOS

MC74AC125

CMOS

MC74ACT125

CMOS

MC74AC126

-

14

N

14

N

D

14

N

D

14

N

D

14

N

D

14

N

D

14

N

D

14

N

D

14

N,J

D

P,L

FN

D

CMOS

MC74ACT126

TIL

MC74F125

TIL

MC74F126

TIL

SN54lS126A

ECl

MC10192

-

16

Quad Bus Driver/Receiver With 2-t0-1 Output Multiplexer (25f.l)

ECL

MC10H330

P,l

FN

ECl

MC10H334

-

24

Quad Bus Driver/Receiver With Transmit & Receiver Latches
(25f.l)

20

P,L

FN
D

Quad Bus Driver

SN74LS126A

Quad Bus Transceiver/Inverting With 3-State Outputs

TIL

SN54LS242

SN74LS242

14

N,J

Quad Bus Transceiver/Non-Inverting With 3-State Outputs

TIL

SN54lS243

SN74LS243

14

N,J

D

Quad Bus Transceivers With 3--State Outputs

TIL

MC74F242

-

14

N

D

TIL

MC74F243

N

D

MC74HC242

-

14

CMOS

14

N

Quad With 3-8tate Outputs Inverting Bus Transceiver
Triple 3--lnput Bus Driver With Enable (25f.l)

ECL

MC10H423

-

16

P,l

FN

Triple 4-3--3 Input Bus Driver (25f.l)

ECl

MC10H123

16

P,L

FN

ECL

MC10123

-

16

P,L

FN

ISXlG

I MC68194

CBM

ICBM - Carrier Band Modem

*FJ

52

CLOCK DISTRIBUTION CHIPS

1:4 Clock Distribution Chip

ECL

MC10EL15

MC100EL15

16

D

1:5 Clock Distribution Chip

ECL

MC100LVEL14

MC100El14

20

DW

MC100E211

1:6 Differential Clock Distribution Chip

ECL

MC10E211

28

FN

low Voltage 1: 12 Clock Distribution Chip

SXlG

MPC948

-

32

FA

low Voltage 1:9 Clock Distribution Chip

SXlG

MPC947

-

32

FA

Low Voltage 1:9 ECUPECl Clock Distribution Chip

ECL

MC100LVE111

-

28

FN

1:2 Differential Clock Driver

ECl

MC10EL11

1:6 PCI Clock Generator/Fanout Buffer

SXlG

MPC903

SXlG

MPC904

ECl

MC10E111

1 :9 Differential ECUPECl RAMBus Clock Buffer

ECL

MC10E411

1 :9 TIUTTL Clock Distribution Chip

ECl

MC10H645

50 MHz Low Skew CMOS Pll Clock Driver With liP Power Down

CMOS

66 MHz Low Skew CMOS PLl Clock Driver With liP
Power-Down/Power-Up Feature

CLOCK DRIVERS

1:9 Differential Clock Driver With Low Skew, Enable, Vbb

68030/040 PECUTTL Clock Driver

Clock Driver Quad D-Type Flip-Flop w/ Matched Propagation
Delays

CMOS PLL Clock Driver Programmable Frequency, low Skew,
High Fan-Out

Motorola Master Selection Guide

MC100El11

-

8

D

16

D

16

D

28

FN

-

28

FN

-

28

FN

MC88920

-

20

DW

CMOS

MC88921

-

20

DW

MC100E111

ECl

MC10H640

MC100H640

28

FN

ECl

MC10H642

MC100H642

28

FN

ECL

MC10H644

MC100H644

20

TIL

MC74F1803

-

14

N

TIL

MC74F803

N

MC88PL117

-

14

CMOS

52

3.1-17

FN
D
D
FN

Logic: Standard, Special and Programmable

Selection by Function

I

Tech.

Description

Device(s)

CLOCK DRIVERS

Dual Supply ECLfITL 1:8 Clock Driver

ECL

High Frequency PLl Clock Generator

MC10H643
MC12429
MC12439

MC100H643

28

FN

-

28

FN

14

N

14

N

28

FN

CMOS

MC88916*80

160 MHz Version

CMOS

MC88915T*160

133 MHz Version

CMOS

MC88915T'133

-

100 MHz Version

CMOS

MC88915T'100

-

28

FN

70 MHz Version

CMOS

MC88915T*70

28

FN

55 MHz Version

CMOS

MC88915T*55

-

28

FN

low Voltage Pll Clock Driver

SXGL

MPC930

MPC931

32

FA

low Voltage PlL Clock Driver

SXGl

MPC950

MPC951

32

FA

low Voltage PLL Clock Driver

SXGl

MPC956

FA

SXGL

MPC970

-

32

'L:;;;Voitage PLl Clock Driver

ECl

MC10H646

MC100H646

ECl

MC10H641

MC100H641

28

FN

ECL

MC100LVEL38

MC100El38

20

DW

ECl

MC100LVEl39

MC100EL39

20

DW

ECl

MC10El34

MC100EL34

16

D

low Skew CMOS Clock Driver

CMOS

MC88913

low Skew CMOS Clock Driver With Reset

CMOS

MC88914

low Skew CMOS PLl 68060 Clock Driver

CMOS

MC88LV926

low Skew CMOS PLl Clock Driver

CMOS

MC88915*55

CMOS

MC88915*70

CMOS

MC88916*70

Low Skew CMOS Pll Clock Driver With Processor Reset

~kew CMOS Pll Clock Driver

f----.---

PECLfITL to TIL 1: 8 Clock Distribution Chip

r----'
~. Supply PECLfITl 1:9 Clock Distribution Chip
+2, +4/6 Clock Generation Chip (3.3V)

f--'---

+2/4, +4/6 Clock Generation Chip
f---'--_
..

.:.2,4,8 Differential Clock Driver

D
D

20

DW

28

FN

28

FN

20

DW

20

DW

28

FN

28

FN

32

FA

28

FN

COAX CABLE DRIVERS

Fibre Channel Coaxial Cable Driver and Loop Resiliency Circuit
300 MBitls LED Driver for FDDI and Fibre Channel
COMPARATORS

4-Bit Magnitude Comparator

-

TIL

MC74F85

CMOS

MC74HC85

TIL

SN54lS85

CMOS

MC14585B

-

5-Bit Magnitude Comparator

ECl

MC10H166

-

ECl

MC10166

8-Bit Equality Comparator

CMOS

MC54HC688

B-Bit Identity Comparator

CMOS

MC74ACT521

TIL

MC74F521

TIL

SN54lS682

TIL

SN74lS85

MC74HC688

-

16

N

D

16

N

DT

16

N,J

D

16

P,l

D

16

P,l

FN

16

P,l

FN

20

N,J

DW

20

N

20

N

DW

SN74lS682

20

N,J

DW

SN54lS684

SN74lS684

20

N,J

DW

TIL

SN54lS688

SN74lS688

20

N,J

DW

9-Bit Magnitude Comparator

ECl

MC10E166

MC100E166

Dual Analog Comparator With Latch

ECl

MC10E1651

Dual Analog Comparator With Latch (Hi-Perf MC1651)

ECl

MC10E1652

B-Bit Magnitude Comparator

logic: Standard, Special and Programmable

3.1-18

-

FN

28
16,20

l

FN

16,20

l

FN

Motorola Master Selection Guide

Selection by Function

I

Description

Tech.

Device(s)

Pins

I DIP I SM

CONVERTERS

4-Bit Parallel to Serial Converter

ECl

MC10E446

MC100E446

28

4-Bit Serial to Parallel Converter

ECl

MC10E445

MC100E445

28

Dual AID Converter

ECl

MC1650

-

16

l

ECl

MC1651

-

16

l

FN
FN

COUNTERS

-

16

P,l

D

MC74HC4040A

16

N,J

D,DT

MC74AC4040

-

16

N

D

MC14020B

16

P,l

D

16

P,l

D

16

N

D,DT

12-Bit Binary Counter

CMOS

MC14040B

12-Stage Binary Ripple Counter

CMOS

MC54HC4040A

CMOS
14-Bit Binary Counter

CMOS

14-Bit Binary Counter and Oscillator

CMOS

MC14060B

14-Stage Binary Ripple Counter

CMOS

MC74HC4020A

14-Stage Binary Ripple Counter With Oscillator

CMOS

MC74AC4020

-

16

N

D

CMOS

MC54HC4060

MC74HC4060

16

N,J

DT

MC74HC4060A

16

N,J

D,DT

-

16

P

DW

CMOS

MC54HC4060A

3-Digit BCD Counter

CMOS

MC14553B

4-Bit BCD Decade Counter, Asynchronous Reset

TTL
TTL
TTL
TTL
TTL
TTL

SN54lS160A

SN74lS160A

16

N,J

D

SN54lS162A

SN74lS162A

16

N,J

D

20

N

DW

20

N

DW
D

4-Bit Bidirectional Binary Counter, With 3-8tate Outputs
4-Bit Bidirectional Decade Counter, With 3-State Outputs
4-Bit Binary Counter

4-Bit Binary Counter, Synchronous Presettable
4-Bit Binary Counter, Synchronous Reset
4-Bit Up/Down Counter With 3-State Outputs
4-Stage Presettable Ripple Counters
4-Stage Synchronous Bidirectional Counter
5 Cascaded BCD Counters

MC74F569
MC74F568

-

SN54lS93

SN74lS93

14

N,J

SN54lS293

SN74lS293

14

N,J

D

16

P,l

FN

16

P

D

16

P

D

16

N,J

D

ECl

MC10H16

CMOS

MC14161B

CMOS

MC14163B

TTL
TTL
TTL
TTL
TTL
TTL
TTL

SN54lS161A

CMOS

MC14534B

SN74lS161A

SN54lS163A

SN74lS163A

16

N,J

D

SN54lS569A

SN74lS569A

20

N,J

DW

SN54lS196

SN74lS196

14

N,J

D

SN54lS197

SN74lS197

14

N,J

D
D

MC74F168

-

16

N

MC74F169

-

16

N

D

24

P,l

DW

6-Bit Universal Counter, (lookahead Carry)

ECl

MC10E136

7-Stage Ripple Counter

CMOS

MC14024B

8-Bit Bidirectional Binary Counter

TTL
TTL
TTL

MC74F269

ECl

MC10E137

MC100E137

28

8-Bit Synchronous Binary Up Counter

ECl

MC10E016

MC100E016

28

BCD Decade Counter, Synchronous Presettable

MC74F160A

BCD Decade Synchronous Bidirectional Counter

TTL
TTL
TTL

Bi-Quinary Counter

ECl

MC10138

Binary Counter

ECl
ECl

TTL
TTL

8-Bit Bidirectional Binary Counter, With 3-State Outputs
8-Bit Ripple Counter

Binary Counter, Synchronous Presettable, 4-Bit

Motorola Master Selection Guide

3.1-19

MC74F579
MC74F779

MC100E136

-

-

28

FN

14

P,l

D

24

N

DW

20

N

DW

16

N

D
FN
FN

16

N

D

16

N

D

16

N,J

D

-

16

P,l

FN

MC10154

-

16

P,l

MC10178

-

16

P,l

FN

MC74F161A

-

16

N

D

16

N

D

MC74F162A
SN54lS168

MC74F163A

SN74lS168

logic: Standard, Special and Programmable

Selection by Function

I

Tech.

Description

I Pins I DIP I

Device(s)

SM

COUNTERS

-

Counter Control logic

ECl

MC12014

16

P,l

Decade Counter

TTL
TTL

SN54lS90

SN74lS90

14

N,J

D

SN54lS290

SN74lS290

14

N,J

D

CMOS

MC14017B

-

16

P,l

D

CMOS

MC74HC4017

-

16

N

D

TTL
TTL

SN54lS92

SN74lS92

14

N,J

D

Dual 4-Stage Binary Counter

SN54lS393

SN74lS393

16

N,J

D

Dual 4-Stage Binary Ripple Counter

CMOS

MC54HC393

MC74HC393

14

N,J

D

MC74HC390

16

N,J

D

16

P,l

DW

Divide By 12 Counter

Dual 4-5tage Binary Ripple Counter W +2, +5 Sections

CMOS

MC54HC390

Dual BCD Up Counter

CMOS

MC14518B

-

Dual Binary Up Counter

CMOS

MC14520B

16

P,l

DW

Dual Decade Counter

TTL
TTL

SN54lS390

SN74lS390

16

N,J

D

SN54lS490

SN74lS490

16

N,J

D

Industrial Time Base Generator

CMOS

MC14566B

16

P

D

Modulo 16 Binary Synchronous Bidirectional Counter

TTL

SN54lS169

16

N,J

D

Octal Counter

CMOS

MC14022B

-

16

P,l

D

Phase Comparator and Programmable Counter

CMOS

MC14568B

-

16

P,l

D

Presettable 4-Bit BCD Down Counter

CMOS

MC14522B

-

16

P

DW

Presettable 4-Bit Binary Down Counter

CMOS

MC14526B

-

16

P,l

DW

Presettable 4-Bit Binary Up/Down Counter

TTL
TTL

SN54lS191

SN74lS191

16

N,J

D

SN54lS193

SN74lS193

16

N,J

D

Presettable BCD Up/Down Counter

CMOS

MC14510B

16

P

D

Presettable BCD/Decade Up/Down Counter

TTL
TTL

SN54lS190

SN74lS190

16

N,J

D

SN54lS192

SN74lS192

16

N,J

D

Presettable Binary Up/Down Counter

CMOS

MC14516B

16

P,l

D

Presettable Binary/BCD Up/Down Counter

CMOS

MC14029B

16

P,l

D

Presettable Counter

CMOS

MC54HC160

MC74HC160

16

N,J

D

CMOS

MC54HC161A

MC74HC161A

16

N,J

D

CMOS

MC54HCT161A

MC74HCT161A

16

N,J

D

CMOS

MC54HC162

MC74HC162

16

N,J

D

CMOS

MC54HCI63A

MC74HC163

16

N,J

D

MC74HCT163A

16

N,J

D

16

P

D

16

P,l

DW

SN74lS169

-

-

CMOS

MC54HCT163A

Presettable Divide-by-N Counter

CMOS

MC14018B

Programmable Dual Binary/BCD Counter

CMOS

MC14569B

Programmable Modulo-N Counters (N=D-9)

ECl

MC4016

-

16

P,l

ECl

MC4018

-

16

P,l

ECl

MC4316

-

16

P,l

Synchronous 4-Bit Up/Down Counter

TTL

SN54lS669

16

N,J

D

Synchronous Presettable Binary Counter

CMOS

MC74AC161

16

N

D

CMOS

MC74ACT161

16

N

D

CMOS

MC74AC163

16

N

D

CMOS

MC74ACT163

16

N

D

CMOS

MC74AC160

-

16

N

D

CMOS

MC74ACT160

-

16

N

D

CMOS

MC74AC162

16

N

D

CMOS

MC74ACT162

16

N

D

ECl

MC10137

-

16

P,l

Synchronous Presettable Binary-Coded-Decimal Decade Counter

Universal Decade Counter

logic: Standard, Special and Programmable

3.1-20

SN74lS669

Motorola Master Selection Guide

Selection by Function
Description

Device(s)

COUNTERS

Universal Hexadecimal Counter

-

16

P,l

FN

16

P,l

FN

16

N

D

-

16

N

D

16

N,J

D

ECl

MC10H136

ECl

MC10136

CMOS

MC74AC190

1-01-10 Decoder

CMOS

MC74HC42
SN54lS42

SN74lS42

1-01-10 Decoder/Driver Open-Collector

SN54lS145

SN74lS145

1-01-10 Decoder, With 3-State Outputs

TTL
TTL
TTL

1-01-16 Decoder/Demultiplexer

CMOS

MC54HC154

1-01-16 Decoder/Demultiplexer With Address latch

CMOS

MC74HC4514

1-01-4 Decoder, With 3-State Outputs
1-01-8 Decoder, With 3-State Outputs

TTL
TTL

1-01-8 Decoder/Demultiplexer

Up/Down Counter With Preset and Ripple Clock
DECODER/DEMULTIPLEXERS

MC74F537

-

MC74HC154

16

N,J

D

20

N

DW

24

N,J

DW

24

N

DW

MC74F539

-

20

N

DW

MC74F538

-

20

N

DW

CMOS

MC74AC138

16

N

D

CMOS

MC74ACT138

-

16

N

D

TTL

MC74F138

-

16

N

D

CMOS

MC54HC138A

MC74HC138A

16

N,J

D

CMOS

MC74HCT138A

-

16

N

D,DT

TTL

SN54lS138

16

N,J

D

CMOS

MC74HC137

-

16

N

D

CMOS

MC74HC237

-

16

N

D

3-Line to 8-Line Decoders/Demultiplexers With Address latches

TTL

SN54lS137

16

N,J

D

4-Bit Transparent latch/4-to-16 Line Decoder (High)

CMOS

MC14514B

24

P,l

DW

24

P,l

DW

16

N,J

D

1-01-8 Decoder/Demultiplexer With Address latch

SN74lS138

SN74lS137

-

4-Bit Transparent latch/4-to-16 Line Decoder (low)

CMOS

MC14515B

B-Bit Addressable Latch/l-01-8 Decoder

CMOS

MC54HC259

BCD-to-Decimal Decoder/Binary-to-Octal Decoder

CMOS

MC14028B

-

16

P,l

D

Binary to 1-4 Decoder (low)

ECl

MC10171

-

16

P,l

FN

Binary to 1-8 Decoder, (High)

ECl

MC10H162

-

16

P,l

FN

ECl

MC10162

-

16

P,l

FN

ECl

MC10H161

16

P,l

FN

ECl

MC10161

-

16

P,l

FN

TTL
TTL

SN54lS155

SN74lS155

16

N,J

D

SN54lS156

SN74lS156

16

N,J

D

Binary to 1-8 Decoder, (low)
Dual 1-01-4 Decoder
Dual 1-01-4 Decoder Open-Collector

MC74HC259

CMOS

MC74AC139

-

16

N

D

CMOS

MC74ACT139

16

N

D

TTL

MC74F139

-

16

N

D

CMOS

MC54HC139A

MC74HC139A

16

N,J

D

TTL

SN54lS139

SN74lS139

16

N,J

D

ECl

MC10H172

-

16

P,l

FN

ECl

MC10172

-

16

P,l

FN

Dual Binary to 1-4 Deyoder (low)

ECl

MC10H171

-

16

P,l

FN

Dual Binary to 1-01-4 Decoder (Active High Outputs)

CMOS

MC14555B

-

16

P

D

Dual Binary to 1-01-4 Decoder (Active low Outputs)

CMOS

MC14556B

-

16

P

low-Voltage Quiet CMOS 1-01-8 Decoder/Demultiplexer

CMOS

MC74lVQ138

-

16

Analog Mixer

ECl

MC12002

P,l

ECl

MC4044

-

14

Phase-Frequency Detector

14

P,l

ECl

MC4344

-

14

P,l

Dual 1-01-4 Decoder/Demultiplexer

Dual 1-01-4 Decoder/Demultiplexer
Dual Binary to 1-4 Decoder (High)

D
D,M,
SD,DT

DETECTORS

Motorola Master Selection Guide

3.1-21

D

logic: Standard, Special and Programmable

Selection by Function

I

Description

I Pins I DIP I SM

Device(s)

Tech.

DETECTORS

Phase-Frequency Detector

DISPLAY DECODE DRIVERS

BCD-to-Seven Segment Decoder
BCD-to-Seven Segment Decoder/Driver

TIL

SN54LS48

CMOS

MC14558B

TIL

SN54LS47

TIL

SN54LS247

TIL

SN54LS248

TIL

SN54LS249

BCD-to-Seven Segment Latch/Decoder/Display Driver

CMOS

MC74HC4511

BCD-to-Seven Segment Latch/Decoder/Driver

CMOS

MC14511B

BCD-to-Seven Segment Latch/Decoder/Driver for Liquid Crystals

CMOS

MC14543B

BCD-to-Seven Segment Latch/Decoder/Driver With Ripple
Blanking

CMOS

MC14544B

CMOS

MC14513B

CMOS

MC14547B

High Current BCD-to-Seven Segment Decoder/Driver

SN74LS48

16

N,J

D

16

P,L

D

SN74LS47

16

N,J

D

SN74LS247

16

N,J

D

SN74LS248

16

N,J

D

SN74LS249

D

-

16

N,J

-

16

N

D

16

P,L

D,DW

16

P,L

D

18

P,L

-

18

P

16

P,L

DW

16

N,J

D

16

P,L

D

16

N,J

D

DIVIDERS
+ 2 Divider

+4 Divider

Coaxial Cable Driver
300MBit/s LED Driver for FDDI and Fibre Channel

Error Detection-Correction Circuit (IBM Code)
Error Detection-Correction Circuit (Motorola Code)
ENCODERS

1D-Line to 4-Line Priority Encoder

TIL

SN54LS147

8-Bit Priority Encoder

CMOS

MC14532B

8-lnput Priority Encoder

TIL

SN54LS348

ECL

MC10H165

-

16

P,L

FN

ECL

MC10165

-

16

P,L

FN

8-lnput Priority Encoder (Glitchless)

TIL

SN54LS848

16

N,J

D

8-Line to 3-Line Priority Encoder

TIL

MC74F148

16

N

D

TIL

SN54LS148

SN74LS148.

16

N,J

D

TIL

SN54LS748

SN74LS748

16

N,J

D

CMOS

MC74HC147

16

N

D

Decimal-to-BCD Encoder
ENCODERIDECODERS

ICMI Encoder/Decoder

SN74LS147

SN74LS348

SN74LS848

-

-

IMC100SX1230

28

FN

EXPANDERS

14

P,L

14

P,L

MC661

-

14

P,L

MC662

-

14

P,L

DTL

MC844

P,L

MC944

-

14

DTL

14

P,L

Dual 4-lput Expander

HTL

MC669

Expandable Dual 4-lnput Gate (Active Pullup)

HTL

MC660

Expandable Dual 4-lnput Gate (Passive Pullup)

HTL

Expandable Dual 4-lnput Line Driver

HTL

Expandable Dual Power Gate

Logic: Standard, Special and Programmable

3.1-22

Motorola Master Selection Guide

Selection by Function
Description

Device(s)

FLIP-FLOPS

3-Bit Differential Flip-Flop

ECL

MC10E431

MC100E431

28

4-Bit D Flip-Flop Individual Clock, Reset Differential Output

ECl

MC10E131

MC100E131

28

4-Bit D Flip-Flop With Enable

TIL

SN54LS379

SN74lS379

16

N,J

4-Bit D-Type Register With With 3-State Outputs

TIL

SN54lS173A

SN74lS173A

16

N,J

5--Bit Differential Register

ECl

MC10E452

MC100E452

28

FN

6-Bit 2:1 Mux-Register With Common Clock, Asynchronous
Master Reset Single Ended

ECl

MC10E167

MC100E167

28

FN

6-Bit D Register With Common Clock, Asynchronous Master
Reset, Differential Outputs

ECl

MC10E151

MC100E151

28

FN

6-Bit D Register, With Differential Inputs, (Data & Clock) , VBB,
Common Reset

ECl

MC10E451

MC100E451

28

FN

6-Bit Parallel D Register With Enable

CMOS

MC74AC378

-

16

N

CMOS

MC74ACT378

-

16

N

9-Bit Hold Register, 700MHz, With Asynchronous Master Reset

ECl

MC10E143

Clocked Flip-Flop

DTl

MC845

Clocked Flip-Flop

DTl

MC945

D Flip-Flop With Set & Reset

ECl

MC10El31

MC100El31

8

D

Differential Clock D Flip-Flop

ECl

MC10El51

MC100El51

8

D

Differential Data & Clock D Flip-Flop

ECl

MC10El52

MC100El52

8

Dual D Flip-Flop

CMOS

MC74AC74

CMOS

MC74ACT74

CMOS

MC14013B

Dual D Flip-Flop With Set and Reset

CMOS

MC54HC74A

Dual D Flip-Flop With Set and Reset With lSTIl Compatible
Inputs

CMOS

MC74HCT74A

Dual D-Type Positive Edge-Triggered Flip-Flop

TIL

MC74F74

TIL

SN54lS74A

SN74lS74A

ECl

MC100lVEl29

MC100EL29

20

Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual J-K Negative Edge-Triggered Flip-Flop

MC100E143

-

-

FN
FN

28

D
D

D
D
FN

14

P,l

14

P,l

D

14

N

D

14

N

D

14

P,l

D

N,J

D,DT

-

14
,14

N

D

-

14

N

D

16

N,J

MC74HC74A

D
DW

TIL

SN54lS112A

SN74lS112A

16

N,J

D

TIL

SN54lS113A

SN74lS113A

14

N,J

D

TIL

SN54lS114A

SN74lS114A

14

N,J

D

Dual J-K Positive Edge-Triggered Flip-Flop

TIL

SN54lS109A

SN74lS109A

16

N,J

D

Dual J-K Flip-Flop

HTl

MC663

14

P,l

14

N,J

14

P,l

14

P,L

16

N

D

16

N

D

14

N

D

14

N

D

16

N,J

D

16

N

D,DT

16

P,l

D

14

N

D

14

N

D

TIL

SN54lS107A

DTl

MC952

Dual J-K Flip-Flop (Separate Clock and SD, No CD)

DTl

MC953

Dual J-K Flip-Flop Negative Edge Trigger

CMOS

MC74AC112

CMOS

MC74ACT112

CMOS

MC74AC113

CMOS

MC74ACT113

Dual J-K Flip-Flop With Set and Clear

TIL

SN54lS76A

Dual J-K Flip-Flop (Common Clock and CD Separate SD)

Dual J-K Flip-Flop Negative Edge Trigger

Dual J-K Flip-Flop With Set and Reset

CMOS

MC74HC112

Dual J-K Flip-Flop

CMOS

MC14027B

Dual J-K Flip-Flop With Reset

CMOS

MC74HC73

CMOS

MC74HC107

Dual J-K Flip-Flop With Set and Reset

CMOS

MC74HC76

Dual J-K Master-8lave Flip-Flop

ECl

MC10135

ECl

MC10H135

Motorola Master Selection Guide

3.1-23

SN74lS107A

SN74lS76A

-

D

16

N

D

16

P,l

FN

16

P,l

FN

logic: Standard, Special and Programmable

Selection by Function

I

Tech.

Description

I

Device(s)

I I
DIP

SM

16

N

D

14

N,J

D

16

N

D

16

N

D

Pins

FLIP-FLOPS

Dual J-K Negative Edge-Triggered Flip-Flop
Dual J-K Positive Edge-Triggered Flip--:-Flop With Set & Clear

TTL

MC74F112

TTL

SN54LS73A

CMOS

MC74AC109

CMOS

MC74ACT109

Dual J-K Flip--:-Flop With Set and Reset

CMOS

MC74HC109

Dual J-K Positive Edge-Triggered Flip-Flop

TTL

MC74F109

Dual Type-D Master-Slave Flip--:-Flop

ECl

MC10131

ECl

MC10H131

Hex D Flip-Flop

TTL

SN54lS174

Hex D Flip--:-Flop With Enable

TTL

SN54lS378

Hex D Flip-Flop With Master Reset

CMOS

MC74AC174

TTL
CMOS
Hex D Flip--:-Flop

SN74lS73A

-

16

N

D

16

N

D

16

P,l

FN

16

P,l

FN

SN74lS174

16

N,J

D

SN74lS378

16

N,J

D

16

N

D

MC74F174

-

16

N

D

MC74ACT174

-

16

N

D

CMOS

MC14174B

-

16

P,l

D

Hex D Flip--:-Flop With Common Clock & Reset

CMOS

MC54HC174A

MC74HC174A

16

N,J

D

Hex D Flip--:-Flop With Common Clock & Reset

CMOS

MC74HCT174A

N

D

ECl

MC10H176

16

P,l

FN

Hex D Master-8lave Flip--:-Flop With Reset

ECl

MC10H186

16

P,l

FN

ECl

MC10186

16

P,l

FN

Hex D Master-8lave Flip--:-Flop

ECl

MC10176

16

P,l

FN

High Speed Dual D Master-Slave Flip--:-Flop

ECl

MC10231

-

16

Hex D Master-8lave Flip--:-Flop

16

P,l

FN

J-K Flip-Flop

ECl

MC10El35

low-Voltage CMOS Octal D-Type Flip--:-Flop, 3-State,
Non-Inverting With 5V Tolerant Inputs and Outputs

CMOS

MC74lCX374

low-Voltage CMOS Octal D-Type Flip--:-Flop Flow Through Pinout,
3-8tate, Non-Inverting With 5V Tolerant Inputs and Outputs

CMOS

low-Voltage Quiet CMOS Octal D-Type Flip--:-Flop
Low-Voltage Quiet CMOS Octal D-Type Flip--:-Flop Flow Through
Pinout

MC100El35

8

D

-

20

DW,M,

MC74lCX574

-

20

DW,M,
DT

CMOS

MC74lVQ374

-

20

DW,M,
SD,DT

CMOS

MC74lVQ574

-

20

DW,M,
SD,DT

Master-8lave Flip--:-Flop

ECl

MC1670

l

HTl

MC664

-

16

Master-Slave R-S Flip-Flop

14

P,l

Octal 3-8tate Inverting D Flip--:-Flop

CMOS

MC54HC534A

MC74HC534A

20

N,J

DW

Octal 3-State Non-Inverting D Flip--:-Flop With lSTTl Compatible
Inputs

CMOS

MC54HCT374A

MC74HCT374A

20

N,J

DW

Octal D Flip Flop, With 3-8tate Outputs

TTL

MC74F374

N

DW

CMOS

MC74AC273

20

N

DW

CMOS

MC74ACT273

-

20

Octal D Flip-Flop

20

N

DW

Octal D Flip-Flop With 3-8tate OutputsiBroadside Pinout, F374

TTL

MC74F574

-

20

N

DW

Octal D Flip--:-Flop With Clear

TTL

SN54lS273

20

N,J

DW

Octal D Flip--:-Flop With Clock Enable

CMOS

MC74AC377

20

N

DW

CMOS

MC74ACT377

-

20

N

DW

Octal D Flip--:-Flop With Common Clock & Reset

CMOS

MC54HC273A

MC74HC273A

20

N,J

DW,
DT

Octal D. Flip--:-Flop With Common Clock and Reset With lSTTl
Compatible Inputs

CMOS

MC74HCT273A

-

20

N

DW

-

20

N

DW

20

N,J

DW

20

N

DW

Octal D Flip--:-Flop With Enable

TTL

MC74F377

Octal D Flip--:-Flop With Enable! Non-Inverting

TTL

SN54lS377

Octal D Type Flip-Flop With 3-State Outputs

CMOS

MC74AC374

logic: Standard, Special and Programmable

3.1-24

DT

SN74lS273

SN74lS377

-

Motorola Master Selection Guide

Selection by Function
Description

Device(s)

FLIP-FLOPS

CMOS

MC74ACT374

-

20

N

DW

TTL

MC74F534

-

20

N

DW

TTL

SN54LS374

20

N,J

DW

CMOS

MC74AC534

-

20

N

DW

Octal D-Type Flip-Flop WITh 3-State Outputs

CMOS

MC74ACT534

-

20

N

OW

Octal D-Type Latch With 3-State Outputs

CMOS

MC74AC564

-

20

N

DW

CMOS

MC74ACT564

-

20

N

DW

CMOS

MC74AC574

-

20

N

DW

CMOS

MC74ACT574

-

20

N

DW

Octal With 3-State Outputs Inverting D Flip-Flop

CMOS

MC74HC564

-

20

N

DW

Octal With 3-State Outputs Non-Inverting D Flip-Flop

CMOS

MC54HC374A

MC74HC374A

20

N,J

DW,
SD,DT

CMOS

MC54HC574A

MC74HC574A

20

N,J

DW

Octal With 3-State Outputs Non-Inverting D Flip-Flop With LSTTL
Compatible Inputs

CMOS

MC54HCT574A

MC74HCT574A

20

N,J

DW

Octal D Type Flip-Flop With 3-State Outputs

Quad D Flip-Flop

Quad D Flip-Flop With Common Clock & Reset

SN74LS374

CMOS

MC74AC175

-

16

N

D

CMOS

MC74ACT175

-

16

N

D

TTL

MC74F175

-

16

N

D

TTL

SN54LS175

16

N,J

D

CMOS

MC14175B

16

P,L

D

SN74LS175

-

CMOS

MC54HC175

MC74HC175

16

N,J

D

CMOS

MC54HC175A

MC74HC175A

16

N,J

D,SD

Quad D-Type Register With 3-State Outputs

CMOS

MC14076B

-

16

P,L

D

Quad Parallel Register With Enable

TTL

MC74F379

-

16

N

D

Quad With 3-State Outputs D Flip-Flop With Common Clock &
Reset

CMOS

MC74HC173

-

16

N

D

Triple D Flip-Flop With Set and Reset

ECL

MC100LVEL30

MC100EL30

20

DW

GATES, AND/NAND

13-lnput NAND Gate
8-lnput NAND Gate

Dual 4-lnput AND Gate

Dual 4-lnput NAND Buffer
Dual 4-lnput NAND Gate

CMOS

MC74HC133

TTL

SN54LS133

-

SN74LS133

-

16

N

D

16

N,J

D

14

N

D

14

N,J

D

CMOS

MC74HC30

TTL

SN54LS30

CMOS

MC14068B

-

14

P

D

TTL

MC74F21

-

14

N

D

14

N,J

D

14

P,L

D

14

N

D

14

N,J

D

TTL

SN54LS21

CMOS

MC14082B

SN74LS30

SN74LS21

-

TTL

MC74F40

TTL

SN54LS40

CMOS

MC74AC20

-

14

N

D

CMOS

MC74ACT20

14

N

D

14

N

D

14

N

D
D

SN74LS40

TTL

MC74F20

-

CMOS

MC74HC20

-

TTL

SN54LS20

SN74LS20

14

N,J

TTL

SN54LS22

SN74LS22

14

N,J

D

CMOS

MC14012B

-

14

P,L

D

-

14

P,L

D

14

P,L

16

P,L

Dual 4-lnput NAND Gate (Unbuffered)

CMOS

MC14012UB

Expandable NAND Gate

DTL

MC830

ECL

MCI 0197~, __

.~<~~~~

~"

Hex AND Gate

Motorola Master Selection Guide

3.1-25

-

L-_,.._=_,___,

"~'~'-I----~--' ~---~

FN --

Logic: Standard, Special and Programmable

Selection by Function
Device(s)

Description
GATES, AND/NAND

Low-Voltage CMOS Quad 2-lnput AND Gate, 5V-Tolerant Inputs

CMOS

MC74LCX08

-

14

D,DT

Low-Voltage CMOS Quad 2-lnput NAND Gate, 5V-Tolerant Inputs

CMOS

MC74LCXOO

-

14

D,DT

Low-Voltage Quiet CMOS Quad 2-lnput NAND Gate

CMOS

MC74LVQOO

-

14

D,M,
DT,SD

Quad 2-lnput AND Gate

CMOS

MC74AC08

-

14

N

D

CMOS

MC74ACT08

-

14

N

D

TTL

MC74F08

-

14

N

D

CMOS

MC54HC08A

MC74HC08A

14

N,J

D,DT

TTL

SN54LS08

SN74LS08

14

N,J

D

TTL

SN54LS09

SN74LS09

14

N,J

D

ECL

MC10Hl04

-

16

P,L

FN
FN

Quad 2-lnput AND Gate
Quad 2-lnput AND Gate With LSTTL-Compatible Inputs

ECL

MC10l04

-

16

P,L

CMOS

MC14081B

-

14

P,L

D

CMOS

MC54HCT08A

MC74HCT08A

14

N,J

D

-

TTL

MC74F37

14

N

D

TTL

SN54LS26

SN74LS26

14

N,J

D

TTL

SN54LS37

SN74LS37

14

N,J

D

Quad 2-lnput NAND Buffer Open-Collector

TTL

MC74F38

14

N

D

Quad 2-lnput NAND Buffer Open-Collector

TTL

SN54LS38

14

N,J

D

Quad 2-lnput NAND Gate

DTL

MC846

-

14

P,L

DTL

MC849

-

14

P,L

DTL

MC946

-

14

P,L

CMOS

MC74ACOO

-

14

N

CMOS

MC74ACTOO

-

14

N

D

TTL

MC74FOO

-

14

N

D

Quad 2-lnput NAND Buffer

Quad 2-lnput NAND Gate

-

SN74LS38

D

CMOS

MC54HCOOA

MC74HCOOA

14

N,J

D,DT

TTL

SN54LSOO

SN74LSOO

14

N,J

D

TTL

SN54LSOI

SN74LSOI

14

N,J

D

TTL

SN54LS03

SN74LS03

14

N,J

D

CMOS

MC14011B

-

14

P,L

D

Quad 2-lnput NAND Gate (Unbuffered)

CMOS

MC14011UB

-

14

P,L

D

Quad 2-lnput NAND Gate With LSTTL-Compatible Inputs

CMOS

MC54HCTOOA

MC74HCTOOA

14

N,J

D

Quad 2-lnput NAND Gate With Open-Drain Outputs

CMOS

MC74HC03A

-

14

N

D,DT

Triple 3-lnput AND Gate

CMOS

MC74ACII

-

14

N

D

CMOS

MC74ACTII

-

14

N

D

TTL

MC74Fli

-

14

N

D

CMOS

MC74HCli

-

14

N

D

TTL

SN54LSli

SN74LSII

14

N,J

D

TTL

SN54LS15

SN74LS15

14

N,J

D

CMOS

MC14073B

-

14

P,L

D

CMOS

MC74AC10

-

14

N

D

CMOS

MC74ACT10

-

14

N

D

TTL

MC74Fl0

-

14

N

D

CMOS

MC74HC10

-

14

N

D

TTL

SN54LS10

SN74LS10

14

N,J

D

TTL

SN54LS12

SN74LS12

14

N,J

D

CMOS

MC14023B

-

14

P,L

D

CMOS

MC14023UB

-

14

P,L

D

Triple 3-lnput NAND Gate

Triple 3-lnput NAND Gate (Unbuffered)

Logic: Standard, Special and Programmable

3.1-26

Motorola Master Selection Guide

Selection by Function
Description

Tech.

GATES, COMPLEX

-MC100El04-'-r-i-" ._- -=-~J

2-lnput AND/NAND Gate

ECl

MC10ElO4

2-lnput Differential AND/NAND Gate

ECl

MC10ElO5

2-lnput XOR/NOR Gate

ECl

MC10ElO7

2-Wide, 2-lnpuV2-Wide, 3-lnput AND-NOR Gate

CMOS

MC74HC51

2-Wide, 2-lnpuV2-Wide, 3-lnput AND-OR Gate

CMOS

MC74HC58

14

N

2-Wide, 4-lnput AND/OR Invert Gate

SN54lS55

SN74lS55

14

N.J

D

SN54lS54

SN74LS54

14

N,J

D

4-2-3-2 Input AND-OR-Invert Gate

TTL
TTL
TTL

MC74F64

-

14

N

D

4-Bit AND/OR Selector

CMOS

MC14519B

-

16

P

D

4-lnput OR/NOR Gate

ECl

MC10ElOl

4-Wide 4-3-3-3 Input OR-AND Gate

ECl

MC10H119

-

16

P,l

FN

4-Wide 4-3-3-3 Input OR-AND Gate

ECl

MC10119

-

16

P.l

FN

4-Wide OR-AND/OR-AND-Invert Gate

ECl

MC10H121

16

P,l

FN

4-Wide OR-AND/OR-AND-Invert Gate

ECl

MC10121

16

P,l

FN

8-lnput NOR/OR Gate

CMOS

MC74HC4078

-

14

N

D

Dual 2 Wide 2-lnpuV3-lnput AND/OR Invert Gate

TTL

SN54lS51

14

N,J

D

Dual 2-Wide 2-3-lnput OR-AND/OR-AND-Invert Gate

ECl

MC10117

16

P,l

FN

ECl

MC10H117

P,L

FN

Dual 2-Wide 2-lnput, 2-Wide 3-lnput AND-OR-Invert Gate

TTL

MC74F51

Dual 2-Wide 3-lnput OR-AND Gate

ECl

MC10H118

-

ECl

MC10118

-

ECl

MC10Hl09

ECl

MC10109

ECl

MC10H209

Dual 4-lnput NAND, 2-lnput NOR/OR, 8-lnput AND/NAND Gate
(Unbuffered)

CMOS

MC1450tUB

-

Dual 4-lnput OR/NOR Gate

ECl

MC1660

Dual 5-lnput Majority logic Gate

CMOS

MC14530B

Dual Expandable AND OR Invert Gate (Unbuffered)

CMOS

MC14506UB

3-2-2-3-lnput AND/OR Invert Gate

Dual 4-5 Input OR/NOR Gate

Hex NAND/NOR/Invert Gate (Unbuffered)

CMOS

MC14572UB

High Speed Dual 3-lnput 3-Output OR/NOR Gate

ECl

MC10212

"

MC100ElO5

8

MC100ElO7

8

-

14

MC100ElOl

~

r--'~-

N

8

SN74lS51

D

-"[)
D-D

D

--~~

-

--

~.

16
14

N

D

16

P,L

FN

16

P,l

FN

16

P,l

FN

16

P.l

FN

16

P,l

FN

16

P

D

16

l

16

P

16

l

16

P

16

P

D
D

Quad 4-lnput OR/NOR Gate

ECl

MC10El0l

MC100El0l

28

Quad Differential AND/NAND Gate

ECl

MC10E404

MC100E404

28

Quad OR/NOR Gate

ECl

MC10Hl01

-

16

P,l

FN

ECl

MC10l0l

-

16

P,l

FN

Quint 2-lnput AND/NAND Gate

ECl

MC10El04

MC100El04

28

Quint 2-lnput XOR/XNOR Gate

ECl

MC10El07

MC100El07

28

Triple 2-3-2 Input OR/NOR Gate

ECl

MC10Hl05

-

16

P,l

FN

ECl

MC10l05

-

16

P,l

FN

ECl

MC10Hl07

16

P.l

FN

ECl

MC10l07

-

16

P,l

FN

CMOS

MC74AC810

N

DW

MC74ACT810

-

14

CMOS

14

N

DW

CMOS

MC74HC7266

-

14

N

D

TTL

SN54lS266

14

N,J

D

Quad Exclusive NOR Gate

CMOS

MC14077B

-

14

P,l

D

Quad 2-lnput Exclusive OR Gate

CMOS

MC74AC86

-

14

N

D

Triple 2-lnput Exclusive OR/Exclusive NOR Gate

FN
FN

FN
FN

GATES, EXCLUSIVE ORlEXCLUSIVE NOR

Quad 2-lnput Exclusive NOR Gate

Motorola Master Selection Guide

3.1-27

SN74lS266

logic: Standard, Special and Programmable

Selection by Function

I

Description

Tech.

Device(s)

Pins

I DIP I SM

GATES, EXCLUSIVE OR/EXCLUSIVE NOR

Quad 2-lnput Exclusive OR Gate

Quad Exclusive OR Gate

CMOS

MC74ACT86

TTL

MC74F86

CMOS

MC54HC86

TTL
TTL
TTL

SN74lS136

ECl

MC10H113

MC74HC86

-

14

N

D

14

N

D

14

N,J

D

14

N,J

D
D

SN54lS386

SN74lS386

14

N,J

SN54lS86

SN74lS86

14

N,J

D

-

16

P,l

FN

16

P,l

FN

14

P,l

D

16

l

-

14

P

D

16

P,l

FN

14

P,l

D

16

P,l

FN

16

P,l

FN

14

N

D

14

P,l

D

14

P,l

D

14

N,J

D

ECl

MC10113

CMOS

MC14070B

ECl

MC1672

8-lnput NOR Gate

CMOS

MC14078B

Dual 3-lnput 3-0utput NOR Gate

ECl

MC10111

Dual 3-lnput NOR Gate + Inverter (Unbuffered)

CMOS

MC14000UB

Dual 3-lnput, 3-0utput NOR Gate

ECl

MC10H211

Dual 3-lnput, 3-Output NOR Gate

ECl

MC10211

Dual 4-lnput NOR Gate

CMOS

MC74HC4002

CMOS

MC14002B

Dual 4-lnput NOR Gate (Unbuffered)

CMOS

MC14002UB

Dual 5-lnput NOR Gate

TTL

SN54lS260

lOW-Voltage CMOS Quad 2-lnput NOR Gate, 5V-Tolerant Inputs

CMOS

MC74lCX02

Quad 2-lnput NOR Buffer

SN54lS28

SN74lS28

14

N,J

D

Quad 2-lnput NOR Buffer

TTL
TTL

SN54lS33

SN74lS33

14

N,J

D

Quad 2-lnput NOR Gate

CMOS

MC74AC02

14

N

D

CMOS

MC74ACT02

14

N

D

TTL

MC74F02

14

N

D

CMOS

MC54HC02A

MC74HC02A

14

N,J

D,DT

TTL

SN54lS02

SN74lS02

14

N,J

D

ECl

MC10H102

16

P,l

FN

ECl

MC10102

16

P,l

FN

ECl

MC1662

16

l

Quad 2-lnput NOR Gate

CMOS

MC14001B

14

P,l

Quad 2-lnput NOR Gate (Unbuffered)

CMOS

MC14001UB

14

P,l

D

Quad 2-lnput NOR Gate With strobe

ECl

MC10H100

16

P,l

FN

ECl

MC10100

16

P,l

FN

Triple 3-lnput NOR Gate

CMOS

MC54HC27

MC74HC27

14

N,J

D

TTL

SN54lS27

SN74lS27

14

N,J

D

CMOS

MC14025B

-

14

P,l

D

Triple 3-lnput NOR Gate (Unbuffered)

CMOS

MC14025UB

-

14

P,l

D

Triple 4-3-3 Input NOR Gate

ECl

MC10H106

16

P,l

FN

ECl

MC10106

-

16

P,l

FN

ECl

MC10110

P,l

FN

MC10H210

16

P,l

FN

ECl

MC10210

16

P,l

FN

Dual 4-lnput OR Gate

CMOS

MC14072B

14

P

low-Voltage CMOS Quad 2-lnput OR Gate, 5V-Tolerant Inputs

CMOS

MC74lCX32

-

16

ECl

Triple 2-lnput Exclusive-OR Gate
GATES, NOR

SN74lS260
-

14

-

-

D,DT

D

GATES, OR

Dual 3-lnput 3-Output OR Gate

logic: Standard, Special and Programmable

3.1-28

14

D
D,DT

Motorola Master Selection Guide

Selection by Function
Description

Device(s)

GATES,OR

Quad 2-lnput OR Gate

Triple 3-lnput OR Gate

-

CMOS

MC74AC32

CMOS

MC74ACT32

TTL

MC74F32

14

N

D

CMOS

MC54HC32A

MC74HC32A

14

N,J

D,DT
D

14

N

D

14

N

D

CMOS

MC54HCT32A

MC74HCT32A

14

N,J

TTL

SN54lS32

SN74LS32

14

N,J

D

ECl

MC10H103

16

P,l

FN

16

P,l

FN

14

P,l

D

14

N

D

14

P,l

D

16

P

DW

14

P,L

ECl

MC10103

CMOS

MC14071B

CMOS

MC74HC4075

CMOS

MC14075B

-

INDUSTRIAL CONTROL UNIT

IIndustrial Control Unit

ICMOS IMC14500B

INVERTERS

Hex Inverter

-

DTl

MC836

DTl

MC837

DTl

MC936

DTl

MC937

DTL

MC840

9-Bit Buffer

ECl

MC10E122

MC100E122

28

Driver

ECl

MC10EL12

MC100El12

8

Dual Complementary Pair Plus Inverter (Unbuffered)

CMOS

MC14007UB

Hex Buffer With Enable

ECl

MC10H188

ECl

MC10188

Hex Buffer/Non-Inverting

CMOS

MC14050B

Hex Inverter

CMOS

Hex Inverter
Hex Inverter (Without Input Diodes)

14

P,l

14

P,l

14

P,l

14

P,l

INVERTERIBUFFERS,2-STATE

FN
D

14

P

D

16

P,l

FN

16

P,l

FN

16

P,l

D

MC74AC04

-

14

N

D

CMOS

MC74ACT04

-

14

N

D

TTL

MC74F04

-

14

N

D

CMOS

MC54HC04A

MC74HC04A

14

N,J

D,SD,
DT

TTL
TTL

SN54lS04

SN74lS04

14

N,J

D

SN54lS05

SN74lS05

14

N,J

D

Hex Inverter Gate (Unbuffered)

CMOS

MC14069UB

14

P,L

D

Hex Inverter With Enable

ECl

MC10H189

16

P,l

FN

16

P,l

FN

14

N

D,DT

14

N

D

14

N

D

14

P,l

ECl

MC10189

Hex Inverter With lSTTl Compatible Inputs

CMOS

MC74HCT04A

Hex Inverter With open Drain Outputs

CMOS

MC74AC05

CMOS

MC74ACT05

Hex Inverter With Strobe (Active Pullup)

HTl

MC677

Hex Inverter With Strobe (Without Output Resistors)

HTl

MC678

-

14

P,l

Hex Inverter/Buffer

ECl

MC10195

-

16

P,l

FN

CMOS

MC14049B

16

P

D

Hex Inverter/Buffer (Unbuffered)

CMOS

MC14049UB

-

16

P,l

D

Hex Inverting Buffer/logic-level Down Converter

CMOS

MC54HC4049

MC74HC4049

16

N,J

D

MC74HC4050

16

N,J

D

14

N

D

Hex Non-Inverting Buffer/logic-level Down Converter

CMOS

MC54HC4050

Hex Unbuffered Inverter

CMOS

MC74HCU04

Motorola Master Selection Guide

3.1-29

-

logic: Standard, Special and Programmable

Selection by Function

I

Tech.

Description

Device(s)

Pins

I DIP I SM

INVERTER/BUFFERS,2-STATE

Low-Voltage CMOS Hex Inverter, With 5V-Tolerant Inputs

CMOS

MC74LCX04

-

14

D,DT

Low-Voltage QUiet CMOS Hex Inverter

CMOS

MC74LVQ04

-

14

D,M,
SD,DT

Quad 2-lnput Gate (Active Pullup)

HTL

MC672

P,L

HTL

MC668

-

14

Quad 2-lnput Gate (Passive Pullup)

14

P,L

Quad Driver

ECL

MC10E112

Strobed Hex InverteriBuffer

CMOS

MC14502B

MC100E112

28

FN

Triple 3-lnput Gate (Active Pullup)

HTL

MC671

-

Triple 3-lnput Gate (Passive Pull up)

HTL

MC670

-

3-Bit 4:1 Mux-Latch (Integrated E156 & E171)

ECL

MC10E256

MC100E256

28

FN

3-Bit 4:1 Mux-Latch, With Common Enable, Asynchronous Master
Reset, Differential Output

ECL

MC10E156

MC100E156

28

FN

16

P,L

14

P,L

14

P,L

DW

LATCHES

4-Bit D Latch

TTL

SN54LS75

SN74LS75

16

N,J

D

TTL

SN54LS77

SN74LS77

14

N,J

D

N,J

TTL

SN54LS375

SN74LS375

16

5-Bit 2: 1 Mux-Latch, With Common Enable, Asynchronous Master
Reset Differential Output

ECL

MC10E154

MC100E154

28

FN

6-Bit 2: 1 Mux-Latch, With Common Enable, Asynchronous Master
Reset Single Ended

ECL

MC10E155

MC100E155

28

FN

6-Bit D Latch

ECL

MC10E150

MC100E150

28

8-Bit Addressable Latch

CMOS

MC74AC259

CMOS

8-Bit Addressable Latch
8-Bit Bus Compatible Addressable Latch

FN

16

N

D

MC74ACT259

-

16

N

D

TTL

MC74F259

-

16

N

D

TTL

SN54LS259

16

N,J

D

CMOS

MC14099B

16

P

DW

CMOS

MC14599B

CMOS

MC14598B

9-Bit Latch, With Parity

ECL

MC10E175

Dual Latch

ECL

MC10H130

Dual 2-Bit Transparent Latch

CMOS

MC74HC75

Dual 4-Bit Addressable Latch

CMOS

MC74AC256

Dual 4-Bit Latch

D

CMOS

MC74ACT256

TTL

MC74F256

TTL

SN54LS256

CMOS

MC14508B

Dual Latch

ECL

MC10130

Low-Voltage CMOS Octal Transparent Latch, 3-State,
Non-Inverting With 5V Tolerant Inputs and Outputs

CMOS

MC74LCX373

Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout,
3-State, Non-Inverting With 5V Tolerant Inputs and Outputs

CMOS

Low-Voltage Quiet CMOS Octal Transparent Latch

SN74LS259

MC100E175

18

P

18

P,L
FN

28

-

16

P,L

16

N

D

-

16

N

DW

16

N

DW

-

16

N

D

16

N,J

D

24

P,L

DW

16

P,L

FN

FN

20

DW,M,
DT

MC74LCX573

-

20

DW,M,
SD,DT

CMOS

MC74LVQ373

-

20

DW,M,
SD,DT

Low-Voltage Quiet CMOS Octal Transparent Latch Flow Through
Pinout

CMOS

MC74LVQ573

-

20

DW,M,
SD,DT

Octal 3-State Non-Inverting Transparent Latch With LSTTL
Compatible Inputs

CMOS

MC54HCT373A

MC74HCT373A

20

N,J

DW,
SD,DT

Octal D Latch With 3-State Outputs

CMOS

MC74AC563

N

DW

MC74ACT563

-

20

CMOS

20

N

DW

CMOS

MC74AC573

-

20

N

DW

Logic: Standard, Special and Programmable

3.1-30

Motorola Master Selection Guide

Selection by Function
Description

Device(s)

LATCHES

Octal D latch With 3-State Outputs

CMOS

MC74ACT573

-

20

N

DW

Octal Transparent latch With 3-State Outputs

CMOS

MC74AC373

-

20

N

DW

CMOS

MC74ACT373

-

20

N

DW

TTL

SN54lS373

20

N,J

DW

TTL

MC74F373

-

20

N

DW

TTL

MC74F533

-

20

N

DW

CMOS

MC74AC533

-

20

N

DW

CMOS

MC74ACT533

-

20

N

DW

CMOS

MC54HC533A

MC74HC533A

20

N,J

DW

CMOS

MC54HC563

MC74HC563

20

N,J

DW

CMOS

MC54HC373A

MC74HC373A

20

N,J

DW

CMOS

MC54HC573A

MC74HC573A

20

N,J

DW

Octal With 3-State Outputs Non-Inverting Transparent latch With
lSTTl Compatible Inputs

CMOS

MC74HCT573A

-

20

N

DW

Quad latch

ECl

MC10133

-

16

P,l

FN

ECl

MC10153

-

16

P,l

FN

ECl

MC10168

-

16

P

Octal With 3-State Outputs Inverting Transparent latch
Octal With 3-State Outputs Non-Inverting Transparent latch

Quad NAND R-8 latch

CMOS

MC14044B

Quad NOR R-S latch

CMOS

MC14043B

Quad Set/Reset latch

TTL

SN54lS279

Quad Transparent latch

CMOS

MC14042B

Quint latch

ECl

MC10H175

ECl

MC10175

IECl

I MC10H660

IECl

I MC10E197

SN74LS373

16

P

D

16

P,l

D

16

N,J

D

-

16

P,l

D

-

16

P,l

FN

16

P,l

FN

SN74lS279

MEMORY SUPPORT

I4-Bit ECl-TTl load Reducing DRAM Driver

I MC100H660

28

FN

28

FN

MISCELLANEOUS

I Data Separator
MULTIPLEXERIDATA SELECTORS

CMOS

MC74AC151

-

16

N

CMOS

MC74ACT151

-

16

N

D

16-Channel Analog Multiplexer/Demultiplexer

CMOS

MC14067B

-

24

P

DW

1-01--8 Decoder/Demultiplexer

D

16:1 Multiplexer

ECl

MC10E164

MC100E164

28

FN

2-Bit 8:1 Multiplexer

ECl

MC10E163

MC100E163

28

FN

2:1 Multiplexer

ECl

MC10El58

MC100El58

8

D

3-Bit 4:1 Multiplexer, With Split Select Differential Output

ECl

MC10E171

MC100E171

28

FN

4:1 Differential Multiplexer

ECl

MC10El57

MC100EL57

16

D

5-Bit 2:1 Multiplexer, With Differential Output

ECl

MC10E158

MC100E158

28

FN

8-Channel Analog Multiplexer/Demultiplexer With Address latch

CMOS

MC54HC4351

MC74HC4351

20

N,J

DW

8-Channel Analog Multiplexer/Demultiplexer

CMOS

MC54HC4051

MC74HC4051

16

N,J

D,DW
,DT
D

CMOS

MC14051B

-

16

P,l

8-Channel Data Selector

CMOS

MC14512B

-

16

P,l

D

8-lnput Data Selector/Multiplexer

CMOS

MC74HC151

-

16

N

D
D

8-lnput Data Selector/Multiplexer With 3-State Outputs

CMOS

MC54HC251

B-Input Multiplexer

TTL

MC74F151

TTL

SN54lS151

TTL

SN54lS251

TTL

MC74F251

B-Input Multiplexer With 3-8tate Outputs

Motorola Master Selection Guide

3.1--31

MC74HC251

16

N,J

16

N

D

SN74lS151

16

N,J

D

SN74LS251

16

N,J

D

16

N

D

-

-

logic: Standard, Special and Programmable

Selection by Function

I

Description

Device(s)

Tech.

Pins

I DIP I 8M

MULTIPLEXER/DATA SELECTORS

CMOS

MC74AC251

CMOS

MC74ACT251

8-lnput Data Selector/Multiplexer With Data and Address Latchs
and With 3-State Outputs

CMOS

MC54HC354

8-Line Multiplexer

ECl

MC10H164

ECl

MC10164

Dual 4-Channel Analog Data Selector

CMOS

MC14529B

Dual 4-Channel Analog Multiplexer/Demultiplexer

CMOS

MC74HC4052

CMOS

MC14052B

Dual 4-Channel Data Selector/Multiplexer

CMOS

MC14539B

Dual 4-lnput Data Selector/Multiplexer

CMOS

MC74HC153

8-lnput Multiplexer With 3-State Outputs

MC74HC354

-

16

N

16

N

D
D

20

N,J

DW

16

P,l

FN

16

P,l

FN

16

P

D

16

N

D,DW

16

P,l

D

16

P

D

16

N

D

16

N

D

16

N

D

16

N

D

16

N

DW

16

N

DW

16

N

D

16

N

D

Dual 4-lnput Data Selector/Multiplexer With 3-State Outputs

CMOS

MC74HC253

Dual 4-lnput Multiplexer

CMOS

MC74AC153

CMOS

MC74ACT153

CMOS

MC74AC352

CMOS

MC74ACT352

TTL

MC74F153

TTL

MC74F352

TTL

SN54lS153

SN74lS153

16

N,J

D

TTL

SN54lS352

SN74lS352

16

N,J

D

Dual 4-lnput Multiplexer With 3-State Outputs

Dual 4-lnput Multiplexer With 3-State Outputs
Dual4-to-l Multiplexer

CMOS

MC74AC253

-

16

N

DW

CMOS

MC74ACT253

-

16

N

DW

CMOS

MC74AC353

16

N

D

CMOS

MC74ACT353

-

16

N

D

TTL

SN54lS253

SN74lS253

16

N,J

D

TTL

SN54lS353

SN74lS353

16

N,J

D

TTL

MC74F253

16

N

D

TTL

MC74F353

16

N

D

ECl

MC10H174

16

P,l

FN

16

P,l

ECl

MC10174

Dual Differential 2:1 Multiplexer (3.3V)

ECl

MC100lVEL56

Dual Multiplexer With Latch

ECl

MC10134

Dual Multiplexer With latch and Common Reset

ECl

MC10132

low Voltage 16:1 Multiplexer

ECl

MC100lVE164

Quad 2-lnput Multiplexer With Latch

ECl

MC10H173

-

MC100El56

-

20

FN
DW

16

P,l

FN

16

P,l

FN

P,l

FN

16

P

D

16

N,J

D

-

16

N

D

16

N

D

32
16

FA

Quad 2-Channel Analog Multiplexer/Demultiplexer

CMOS

MC14551B

Quad 2-lnput Data Selector/Multiplexer

CMOS

MC54HC158

Quad 2-lnput Data SelectorlMultiplexer With 3-State Outputs

CMOS

MC74HC257

Quad 2-lnput Data Selector/Multiplexer With lSTTl Compatible
Inputs

CMOS

MC74HCT157A

Quad 2-lnput Data Selectors/Multiplexers

CMOS

MC54HC157A

MC74HC157A

16

N,J

D,DT

Quad 2-lnput Multiplexer

TTL

MC74F157A

-

16

N

D

TTL

MC74F158A

-

16

N

D

TTL

SN54lS157

SN74lS157

16

N,J

D

TTL

SN54lS158

SN74lS158

16

N,J

D

Quad 2-lnput Multiplexer (Inverting)

ECl

MC10159

-

16

P,l

FN

Quad 2-lnput Multiplexer (Non-Inverting)

ECl

MC10158

-

16

P,l

FN

logic: Standard, Special and Programmable

3.1-32

MC74HC158

Motorola Master Selection Guide

Selection by Function
Description

Tech.

Device(s)

Pins

I DIP I SM

MULTIPLEXER/DATA SELECTORS

Quad 2-lnput Multiplexer Inverting With 3-State Outputs

CMOS

MC74AC258

CMOS

MC74ACT258

CMOS

MC74ACT257

CMOS

MC74AC257
SN54lS257B

Quad 2-lnput Multiplexer With Storage

TIL
TIL

SN54lS298

Quad 2-lnput Multiplexer, Inverting

CMOS

MC74AC158

CMOS

MC74ACT158

Quad 2-lnput Multiplexer, Inverting Output

ECl

MC10H159

Quad 2-lnput Multiplexer, Inverting, With 3-3tate Outputs

TIL

SN54lS258B

Quad 2-lnput Multiplexer, Non-Inverting

CMOS

MC74AC157

Quad 2-lnput Multiplexer Non-Inverting With 3-State Outputs
Quad 2-lnput Multiplexer With 3-State Outputs

-

16

N

DW

16

N

DW

16

N

D

16

N

D

SN74lS257B

16

N,J

D

SN74lS298

16

N,J

D

16

N

D

SN74lS258B

CMOS

MC74ACT157

Quad 2-lnput Multiplexer, Non-Inverting Output

ECl

MC10H158

-

Quad 2-lnput Multiplexer, With 3-State Outputs

TIL
TIL

MC74F257A

-

MC74F258A

Quad 2-lnput Multiplexer/latch

ECl

MC10173

Quad 2-Port Register

TIL
TIL
TIL
TIL

MC74F398

-

Quad 2:1 Mux, Individual-Select
Quad Analog Switch/Multiplexer
Quad Analog Switch/Multiplexer/Demultiplexer

MC74F399
SN54lS398

SN74lS398

16

N

D

16

P,l

FN

16

N,J

D

16

N

D

16

N

D

16

P,l

FN

16

N

D

16

N

D

16

P,l

FN

20

N

DW

16

N

D

20

N,J

DW

N,J

SN54lS399

SN74lS399

16

ECl

MC10E157

MC100E157

28

CMOS

MC14016B

CMOS

MC14066B

-

D
FN

14

P,l

D

14

P,l

D

CMOS

MC54HC4016

MC74HC4016

14

N,J

D

CMOS

MC54HC4066

MC74HC4066

14

N,J

D,DT

Quad Analog Switch/Multiplexer/Demultiplexer With Separate
Analog/Digital Power Supplies

CMOS

MC74HC4316

16

N

D

Triple 2-Channel Analog Multiplexer/Demultiplexer

CMOS

MC54HC4053

16

N,J

D,DW

CMOS

MC14053B

16

P,l

D

Triple 2-Channel Analog Multiplexer/Demultiplexer With Address
latch

CMOS

MC54HC4353

MC74HC4353

20

N,J

DW

Triple 2:1 Multiplexer

ECl

MC100El59

DW

ECl

MC100lVEl59

-

20

Triple 2:1 Multiplexer (3.3V)

20

DW

Triple Differential 2:1 Multiplexer

ECl

MC100E457

-

28

FN

ECl

MC10E457

-

28

FN

-

20

P

FN

20

P

FN

14

P,l

-

MC74HC4053

-

MULTIVIBRATORS

130MHz Voltage Controlled Multivibrator

ECl

MC12101

200 MHz Voltage Controlled Multivibrator

ECl

MC12100

Dual Monostable Multivibrator

HTl

MC667

CMOS

MC14528B

16

P,l

D

Dual Monstable Multivibrators With Schmitt Trigger Inputs

TIL

SN54lS221

SN74lS221

16

N,J

D

Dual Precision Monostable Multivibrator Retriggerable, Resettable)

CMOS

MC54HC4538A

MC74HC4538A

16

N,J

0

Dual Precision Monostable Multivibrator

CMOS

MC14538B

16

P,l

D,DW

Dual Voltage-Controlled Multivibrator

ECl

MC4024

14

P,l

Monostable Multivibrator

DTl

MC951

-

14

P,l

ECl

MC10198

-

16

P,l

FN

TIL
TIL

SN54lS122

SN74lS122

14

N,J

D

SN54lS123

SN74lS123

14

N,J

D

Retriggerable Monostable Multivibrators

Motorola Master Selection Guide

3.1-33

logic: Standard, Special and Programmable

Selection by Function

I
Description
IVoltage Controlled Multivibrator

Tech.

MULTIVIBRATORS

I Pins I DIP I SM

Device(s)

IMC1658

16

P,l

D,FN

D

OSCILLATORS

-

14

N

16

P,l

14

P,l

14

P,l

D,FN

-

16

P,l

D

14

P,l

D

16

P,l

DW

16

P,l

DW

-

16

P,l

FN

16

P,l

FN

7-Stage Binary Ripple Counter

CMOS

MC74HC4024

Crystal Oscillator

ECl

MC12061

Dual VoltagiH::ontrolied MuHivibrator

ECl

MC4324

low Power Voltage Controlled Oscillator

ECl

MC12148

Voltage Controlled Oscillator

ECl

MC1648

24-Stage Frequency Divider

CMOS

MC14521B

Programmable Oscillator Timer

CMOS

MC14541B

Programmable Timer

CMOS

MC14536B

Quad Precision Timer/Driver

CMOS

MC14415

ECl

MC10H160

ECl

MC10160

12-Bit Parity Generator/Checker, Register-Shiftable, Dill Output

ECl

MC10E160

12--Bit Parity Tree

CMOS

MC14531B

-

16

P

D

9 + 2-Bit Parity Generator-Ghecker

ECl

MC10170

-

16

P,l

FN

9--Bit Odd/Even Parity Generator/Checker

CMOS

MC74HC280

-

14

N

D

SN54lS280

14

N,J

D

9--Bit Parity Generator/Checker

TTL
TTL

MC74F280

14

N

D

Error Detection and Correction Circuit

ECl

MC10E193

8

D,SD

OSCILLATORITIMERS

PARITY CHECKERS

12--Bit Parity Generator/Checker

PHASE-LOCKED LOOP

IPhase-Locked loop

MC100E160

SN74lS280

MC100E193

ICMOS IMC14046B

28

FN

28

FN

16

P,l

8

P

DW

PRESCALERS

1.1 GHz +10/20/40/80 Prescaler

ECl

MC12080

1 .1 GHz +1261128, +254/256 low Power Dual Modulus Prescaler

ECl

MC12058

1.1 GHz +127/128, +2551256 low Power Dual Modulus Prescaler

ECl

MC12038A

1.1 GHz +6/9, +16117 Dual Modulus Prescaler

ECl

MC12026A

ECl

MC12026B

-

1 .1 GHz +2 low Power Prescaler With Stand-By Mode

ECl

MC12083

-

1.1 GHz +21418 low Power Prescaler With Stand-By Mode

ECl

MC12093

1 .1 GHz +256 Prescaler

ECl

MC12074

1.1 GHz +32133, 434/65 Dual Modulus Prescaler

ECl

MC12028A

-

1.1 GHz +32133, 434/65 Dual Modulus Prescaler

ECl

MC12028B

1.1 GHz 434 Prescaler

ECl

MC12073

1.1 GHz +64165, +1281129 Dual Modulus Prescaler

ECl

MC12022A

ECl

MC12022B

ECl

MC12022SlA

ECl

8

D
D,SD

8

P

8

P

D

8

P

D

8

P

D

8

P

D,SD

D

8

P

D

8

P

D

8

P

D

-

8

P

D

8

P

D

8

P

D

8

P

D

MC12022SlB

-

8

P

D

ECl

MC12022TSA

-

8

P

D

ECl

MC12022TSB

8

P

D

1.1 GHz +64165, +1281129 Dual Modulus Prescaler W~h Stand-By
Mode

ECl

MC12036A

8

P

D

ECl

MC12036B

-

8

P

D

1.1 GHz +64165, +1281129 low Voltage Dual Modulus Prescaler

ECl

MC12022lVA

-

8

P

D

ECl

MC12022lVB

-

8

P

D

logic: Standard, Special and Programmable

3.1--34

Motorola Master Selection Guide

Selection by Function
Description

Device(s)

PRESCALERS

1.1 GHz +64/65, +128/129 low Voltage Dual Modulus Prescaler

8

P

8

P

MC12052A

-

8

D,SD

MC12053A

-

8

D,SD

-

8

P

D

8

P

D

8

P

D

8

P

D

8

P

D

8

P

D

8

P

D

-

8

P

D

8

P

D

-

8

P

D

8

P

D

-

8

ECl

MC12022TVA

ECl

MC12022TVB

1.1 GHz +64165, +128/129 Super low Power Dual Modulus
Prescaler

ECl

1.1 GHz +64/65, + 128/129 Super low Power Dual Modulus
Prescaler With Stand-By Mode

ECl

1.3GHz +64 Prescaler

ECl

MC12075

1.3GHz +256 Prescaler

ECl

MC12076

ECl

MC12078

ECl

MC12034A

ECl

MC12034B

ECl

MC12033A

ECl

MC12033B

ECl

MC12032A

ECl

MC12032B

ECl

MC12031A

ECl

MC12031B

ECl

MC12054A

2.5GHz +2, +4 low Power Prescaler With Satnd-By Mode

ECl

MC12095

2.8GHz +64/128/256 Prescaler

ECl

MC12079

ECl

MC12089

225MHz +20/21 Dual Modulus Prescaler

ECl

MC12019

225M Hz +32/33 Dual Modulus Prescaler

ECl

MC12015

225MHz +40/41 Dual Modulus Prescaler

ECl

MC12016

225MHz +64 Prescaler

ECl

MC12023

225MHz +64/65 Dual Modulus Prescaler

ECl

MC12017

2.0GHz +32/33, +64/65 Dual Modulus Prescaler
2.0GHz +32/33, +64/65 low Voltage Dual Modulus Prescaler
2.0GHz +64/65, +128/129 Dual Modulus Prescaler
2.0GHz +64165, +1281129 low Voltage Dual Modulus Prescaler
2.0GHz +64/65, +128/129 Super low Power Dual Modulus
Prescaler

480MHz +5/6 Dual Modulus Prescaler

ECl

MC12009

520MHz + 128/129 Dual Modulus Prescaler

ECl

MC12018

520MHz +64/65 Dual Modulus Prescaler

ECl

MC12025

550MHz+10111 Dual Modulus Prescaler

ECl

MC12013

550MHz +8/9 Dual Modulus Prescaler

ECl

MC12011

750MHz +2 UHF Prescaler

ECl

MC12090

D
D

D,SD

8

D,SD

8

P

8

P

D
D

8

P,l

D

8

P,l

D

8

P,l

D

8

P

D

8

P,l

D

16

P,l

8

P,l

D

8

P

D

16

P,l

16

P,l

16

P,l

PROGRAMMABLE DELAY CHIPS

Programmable Delay Chip (Dig 80ps Anal. 1.6 Pslmv)
Programmable Delay Chip (Digitally Selectable 20ps Res)

1024-Bil Programmable Read Only Memory
32 X 8-Bit Programmable Read Only Memory

1024 X 1-Bit Random Access Memory
256 X 1-Bit Random Access Memory
RECEIVERS

Differential Receiver

ECl

MC10El16

High Speed Triple Line Receiver

ECl

MC10216

low-Voltage Quad Differential Line Receiver

ECl

MC100lVEL17

Quad Bus Receiver

ECl

MC10129

Motorola Master Selection Guide

3.1-35

MC100El16

MC100EL17

-

8
16

D
P,l

DW

20
16

FN

l

logic: Standard, Special and Programmable

Selection by Function

I

Description

Tech.

Devlce(s)

Pins

I DIP I

SM

16

P,l

FN

16

P,l

FN

16

l

RECEIVERS

Quad Line Receiver

-

ECl

MC10Hl15

ECl

MC10115

ECl

MC1692

ECl

MC10El16

MC100El16

28

ECl

MC10E416

MC100E416

28

ECl

MC10Hl16

ECl

MC10114

ECl

MC10116

16 X 4-Bit Register File (RAM)

ECl

MC10H145

4 X 4 Register File Open Collector

SN54lS170

SN74lS170

4 X 4 Register File With 3-State Outputs

TTL
TTL

SN54lS670

SN74lS670

64-Bit Register File (RAM)

ECl

MCM10145

8 X 2 Multiport Register File (RAM)

ECl

MCM10143

TTL
TTL

MC74F13

Dual Schmitt Trigger

CMOS

MC14583B

Hex Inverter Schmitt Trigger

CMOS

MC74AC14

Quint Differential Line Receiver
Triple Line Receiver

FN
FN

-

16

P,l

D,FN

16

P,l

FN

16

P,l

FN

-

16

P,l

FN

16

N,J

D

16

N,J

D

REGISTERS

4 X 4 Multiport Register
Hex Parallel D Register With Enable
REGISTER FILES

-

16

l

24

l

-

14

N

D

14

N,J

D

16

P

D

14

N

D

14

N

D

14

N

D

14

N,J

D

SCHMITT TRIGGERS

Dual 4-lnput NAND Schmitt Trigger

Hex Schmitt Trigger
Hex Schmitt Trigger Inverter

SN54lS13

SN74lS13

-

CMOS

MC74ACT14

TTL
TTL

MC74F14

CMOS

MC14106B

-

14

P,l

D

CMOS

MC14584B

.-

14

P,l

D

SN54lS14

SN74lS14

CMOS

MC54HC14A

MC74HC14A

14

N,J

D,DT

CMOS

MC54HCT14A

MC74HCT14A

14

N,J

D

Quad 2-lnput NAND Gate With Schmitt Trigger Inputs

CMOS

MC54HC132A

MC74HC132A

14

N,J

D

Quad 2-lnput NAND Schmitt Trigger

CMOS

MC74AC132

14

N

D

14

N

D

14

N

D

14

P,l

D

14

N,J

D

-

CMOS

MC74ACT132

TTL

MC74F132

CMOS

MC14093B

TTL

SN54lS132

18-Bit Active SCSI Bus Terminator
('Also Available in 32-Pin QFP Package)

CMOS

MCCS142235

-

24,32

9-Bit Switchable SCSI Bus Term (1100: Active)

CMOS

MCCS142234

D

CMOS

MCCS142233

20

FN

9-Bit Switchable Active SCSI-2 Bus Term (1100) with Volt Reg

CMOS

MCCS142237

-

16

9-Bit Switchable SCSI Bus Term (2200 & 3300: Passive)

16,20

DW,
DT

Quad 2-lnput Schmitt Trigger NAND Gate

SN74lS132

SCSI BUS TERMINATORS

DW,*F
A

SHIFT REGISTERS

l-t0-64-Bit Variable length Shift Register

CMOS

MC14557B

128-Bit Static Shift Register

CMOS

MC14562B

18-Bit Static Shift Register

CMOS

MC14006B

3-Bit Scannable Registered Address Driver, ECl

ECl

MC10E212

logic: Standard, Special and Programmable

3.1-36

MC100E212

16

P,l

14

P,l

14

P,l

28

DW
D
FN

Motorola Master Selection Guide

Selection by Function
Description

Tech.

Device(s)

Pins

I DIP I

SM

SHIFT REGISTERS

4-Bit Bidirectional Universal Shift Register

CMOS

MC74AC194

-

16

N

D

CMOS

MC74ACT194

-

16

N

D

TTL

MC74F194

N

D

MC74HC194

-

16

CMOS

16

N

16

N,J

D

16

N

D

14

N,J

D

--

16

P,L

D

16

N,J

D

16

N

D

TTL

SN54LS194A

TTL

MC74F195

TTL

SN54LS95B

CMOS

MC14035B

4-Bit Shift Register With 3-State Outputs

TTL

SN74LS395

4-Bit Shifter With 3-State

CMOS

MC74AC350

4-Bit Shift Register

SN74LS194A

SN74LS95B
-

CMOS

MC74ACT350

-

16

N

D

TTL

MC74F350

-

16

N

D

CMOS

MC74HC195

-

N

ECL

MC10H141

_.-

16

-

16

P,L

FN

ECL

MC10141

.-

16

P,L

FN

16

P,L

D

-

20

N

DW

N,J

~~~-

4-Bit Shifter, With 3-State Outputs
4-Bit Universal Shift Register

--

CMOS

MC14194B

8-Bit Bidirectional Universal Shift Register With parallel 1/0

CMOS

MC74HC299

B-Bit Parallel-to-Serial Shift Register

TTL

SN54LS165

SN74LS165

16

8-Bit Scannable Register

ECL

MC10E241

MC100E241

28

8-Bit Serial In-Serial Out Shift Register

TTL

MC74F164

14

N

D

8-Bit Serial or Paraliel-lnpuVSerial-Output Shift Register

CMOS

MC54HC165

MC74HC165

16

N,J

D

B-Bit Serial or Paraliel-lnpuVSerial-Output Shift Register With
3-State Outputs

CMOS

MC54HC589

MC74HC589

16

N,J

D

B-Bit Serial or Paraliel-lnpuVSerial-Output Shift Register With
Input Latch

CMOS

MC54HC597

MC74HC597

16

N,J

D

-

D
FN

B-Bit Serial-ln/Paraliel-Out Shift Register

TTL

SN54LS164

SN74LS164

14

N,J

D

B-Bit Serial-lnpuVParaliel-Output Shift Register

CMOS

MC54HC164

MC74HC164

14

N,J

D

8-Bit Serial-lnpuVSerial or Parallel-Output Shift Register With
Latched 3-State Outputs

CMOS

MC54HC595A

MC74HC595A

16

N,J

D,DT

E~L

MC10E141

MC100E141

2B

TTL

SN54LS166

SN74LS166

16

N,J

D

8-Bit Shift Registers With Sign Extend

TTL

SN54LS322A

SN74LS322A

20

N,J

DW

B-Bit Shift/Storage Register With 3-State Outputs

TTL

SN54LS299

SN74LS299

20

N,J

DW

TTL

SN54LS323

SN74LS323

20

N,J

DW

CMOS

MC14014B

16

P,L

D

CMOS

MC14021B

B-Input Shift/Storage Register WISynchronous Reset and Common
1/0 Pins

TTL

8-lnput Universal Shift/Storage Register With Common Parallel 1/0
Pins: With 3-State Outputs

B-Bit Shift Register

8-Bit Static Shift Register

B-Input Universal Shift/Storage Register With Syn ReseVCommon
Parallel 1/0 Pins: With 3-State Outputs

FN

16

P,L

D

MC74F323

-

20

N

DW

CMOS

MC74AC299

-

20

N

DW

CMOS

MC74ACT299

-

20

N

DW

CMOS

MC74AC323

-

20

N

DW

CMOS

MC74ACT323

20

N

DW

8-lnput Universal Shift/Storage Register, W/Common Parallel 1/0
Pins

TTL

MC74F299

-

20

N

DW

B-Stage Shift/Store Register With 3-State Outputs

CMOS

MC14094B

16

P,L

9-Bit Shift Register, 700MHz, With Asynchronous Master Reset

ECL

MC10E142

Dual 5-Bit Shift Register

CMOS

MC14015B

Dual 64-Bit Static Shift Register

CMOS

MC14517B

Motorola Master Selection Guide

3.1-37

MC100E142

-

2B

D
FN

16

P,L

D

16

P

DW

Logic: Standard, Special and Programmable

Selection by Function

I

Tech.

Description

Device(s)

Pins

I DIP I SM

SHIFT REGISTERS

Successive Approximation Register

-

CMOS

MC14549B

CMOS

MC14559B

TTL

SN54lS195A

1.1 GHz Serial Input Synthesizer With +64/65, + 128/129 Prescaler

ECl

MC12202

-

16,20

D,M,
DT

2.0GHz Serial Input Synthesizer With +64/65, +1281129 Prescaler

ECl

MC12206

D,DT

ECl

MC12210

16,20

D,DT

2.7GHz Frequency Synthesizer

ECl

MC12179

-

16,20

2.5GHz Serial Input Synthesizer With +32133, +64/65 Prescaler

8

D

4-Bit Differential ECl BusITTl Bus Transceiver

ECl

MC10H680

ECLlTTl Inverting Bidirectional Transceivers With latch (4-Bit)

ECl

MC10804

Universal 4-Bit Shift Register

SN74lS195A

16

P,l

DW

16

P,l

DW

16

N,J

D

SYNTHESIZERS

TRANSCEIVERS

ECLlTTl Inverting Bidirectional Transceivers With latch (5-Bit)

ECl

MC10805

Hex ECLlTTl Transceiver With latches

ECl

MC10H681

low-Voltage CMOS Octal Transceiver, 3-State, Non-Inverting
With 5V Tolerant Inputs and Outputs

CMOS

MC74lCX245

low-Voltage Quiet CMOS Octal Transceiver, 3-State,
Non-Inverting

CMOS

low-Voltage Quiet CMOS Octal Transceiver/Registered
Transceiver

MC100H680

MC100H681

28

FN

16

l

20

l

28

FN

-

20

M,DW,
DT

MC74lVQ245

-

20

M,DW,
SD,DT

CMOS

MC74LVQ646

-

24

DW,
SD,DT

low-Voltage Quiet CMOS Octal Transceiver/Registered
Transceiver

CMOS

MC74lVQ652

-

24

DW,
SD,DT

Octal Bus Transceiver/Inverting With Open Collector

TTL

SN54lS642

SN74lS642

20

N,J

DW

Octal Bus Transceiver/Non-Inverting With Open Collector

TTL

SN54lS641

SN74lS641

20

N,J

DW

Quad Futurebus Backplane Transceiver, With 3-State Outputs and
Open Collector

TTL

MC74F3893A

-

20

FN

TRANSLATORS

9-Bit ECLlTTl Translator

ECl

MC10H601

MC100H601

28

FN

9-Bit latch ECLlTTl Translator

ECl

MC10H603

MC100H603

28

FN

9-Bit Latch TTUECl Translator

ECl

MC10H602

MC100H602

28

FN

9-Bit TTUECl Translator

ECl

MC10H600

MC100H600

28

FN

Differential ECLlTTl Translator

ECl

MC10ElT25

MC100ElT25

8

D

Differential PECLlTTl Translator

ECl

MC10ElT21

MC100ElT21

8

D

Dual Differential PECLlTTl Translator

ECl

MC100ElT23

Dual TTUDifferential PECl Translator

ECl

MC10ElT22

ECLlTTl Translator (Single P.S. @+ 5.0V)

ECl

MC10H350

Hex ECUMST Translator

ECl

MC10191

MC100ElT22

Hex TTL OR CMOS/CMOS Hex level Shifter

CMOS

MC14504B

Quad CMOS/ECl Translator (Single P.S. @+ 5.0V)

ECl

MC10H352

Quad MECLlTTl Translator

ECl

MC10H125

ECl

MC10125

-

Quad MST/ECl Translator

ECl

MC10190

Quad TTUECl Translator (ECl Strobe)

ECl

MC10H424

Quad TTUMECl Translator

ECl

Quad TTUMECl Translator, With TTL Strobe Input

8

D

8

D

16

P,l

16

P,l

FN

16

P,l

D

20

P,l

FN

16

P,l

FN

16

P,l

FN

-

16

P

-

16

P,l

FN

MC10124

16

P,l

FN

ECl

MC10H124

-

16

P,l

FN

Quad TTUNM08-to-PECL Translator (Single P.S. @+ 5.0V)

ECl

MC10H351

-

20

P,L

FN

Registered Hex ECLlTTl Translator

ECl

MC10H605

MC100H605

28

FN

Registered Hex PECLlTTl Translator

ECl

MC10H607

MC100H607

28

FN

Registered Hex TTUECl Translator

ECl

MC10H604

MC100H604

28

FN

logic: Standard, Special and Programmable

3.1-38

Motorola Master Selection Guide

Selection by Function
Device(s)

Description
TRANSLATORS

Registered Hex TIUPECl Translator

ECl

MC10H606

Triple MECUNMOS Translator

ECl

MC10177

Triple ECl to PECl Translator

ECl

MC100lVEl90

Triple PECl to lVPECl Translator

ECl

MC100lVEl92

TTUDifferential ECl Translator

ECl

MC10ElT24

TIUDifferential PECl Translator

ECl

TIL to Differential PECUDifferential PECl to TIL Translator

MC100H606

MC100El90

28
16

FN
l

20

DW

20

DW

MC100ElT24

8

D

MC10ElT20

MC100ElT20

8

D

ECl

MC10ElT28

MC100ElT28

8

D

Phase-locked-loop With VCO

CMOS

MC74HC4046A

low Power Voltage Controlled Oscillator Buffer

CMOS

MC12147

low Power Voltage Controlled Oscillator Buffer

CMOS

MC12149

-

veo

Motorola Master Selection Guide

3,1-39

-

16

N

D

8

D,SD

8

D,SD

logic: Standard, Special and Programmable

Device Index
MC100E016

3.1-19

MC100EL12

3.1-29

MC100LVEL14

3.1-17

MC100E101

3.1-27

MC100EL13

3.1-14

MC100LVEL17

3.1-35

MC100E104

3.1-27

MC100EL14

3.1-17

MC100LVEL29

3.1-23

MC100E107

3.1-27

MC100EL15

3.1-17

MC100LVEL30

3.1-25

MC100E111

3.1-17

MC100EL16

3.1-35

MC100LVEL38

3.1-18

MC100E112

3.1-30

MC100EL17

3.1-35

MC100LVEL39

3.1-18

MC100E116

3.1-36

MC100EL29

3.1-23

MC100LVEL56

3.1-32

MC100E122

3.1-29

MC100EL30

3.1-25

MC100LVEL59

3.1-33

MC100E131

3.1-23

MC100EL31

3.1-23

MC100LVEL90

3.1-39

MC100E136

3.1-19

MC100EL32

3.1-22

MC100LVEL92

3.1-39

MC100E137

3.1-19

MC100EL33

3.1-22

MC100SX1230

3.1-22

MC100E141

3.1-37

MC100EL34

3.1-18

MC10100

3.1-28

MC100E142

3.1-37

MC100EL35

3.1-24

MC10101

3.1-27

MC100E143

3.1-23

MC100EL38

3.1-18

MC10102

3.1-28

MC100E150

3.1--30

MC100EL39

3.1-18

MC10103

3.1-29

MC100E151

3.1-23

MC100EL51

3.1-23

MC10104

3.1-26

MC100E154

3.1-30

MC100EL52

3.1-23

MC10105

3.1-27

MC100E155

3.1-30

MC100EL56

3.1-32

MC10106

3.1-28

MC100E156

3.1-30

MC100EL57

3.1-31

MC10107

3.1-27

MC100E157

3.1-33

MC100EL58

3.1--31

MC10109

3.1-27

MC100E158

3.1-31

MC100EL59

3.1-33

MC10110

3.1-28

MC100E160

3.1-34

MC100EL90

3.1--39

MC10111

3.1-28

MC100E163

3.1-31

MC100ELT20

3.1-39

MC10113

3.1-28

MC100E164

3.1-31

MC100ELT21

3.1-38

MC10114

3.1-36

MC100E166

3.1-18

MC100ELT22

3.1-38

MC10115

3.1--36

MC100E167

3.1-23

MC100ELT23

3.1-38

MC10116

3.1-36

MC100E171

3.1-31

MC100ELT24

3.1--39

MC10117

3.1-27

MC100E175

3.1-30

MC100ELT25

3.1-38

MC10118

3.1-27

MC100E193

3.1-34

MC100ELT28

3.1-39

MC10119

3.1-27

MC100E195

3.1-35

MC100H600

3.1-38

MC10121

3.1-27

MC100E196

3.1-35

MC100H601

3.1-38

MC10123

3.1-17

MC100E210

3.1-14

MC100H602

3.1-38

MC10124

3.1-38

MC100E211

3.1-17

MC100H603

3.1-38

MC10125

3.1-38

MC100E212

3.1-36

MC100H604

3.1-38

MC10128

3.1-15

MC100E241

3.1-37

MC100H605

3.1-38

MC10129

3.1-35

MC100E256

3.1-30

MC100H606

3.1-39

MC10130

3.1-30

MC100E310

3.1-14

MC100H607

3.1-38

MC10131

3.1-24

MC100E336

3.1-14

MC100H640

3.1-17

MC10132

3.1-32

MC100E337

3.1-15

MC100H641

3.1-18

MC10133

3.1-31

MC100E404

3.1-27

MC100H642

3.1-17

MC10134

3.1-32

MC100E416

3.1-36

MC100H643

3.1-18

MC10135

3.1-23

MC100E431

3.1-23

MC100H644

3.1-17

MC10136

3.1-21

MC100E445

3.1-19

MC100H646

3.1-18

MC10137

3.1-20

MC100E446

3.1-19

MC100H660

3.1-31

MC10138

3.1-19

MC100E451

3.1-23

MC100H680

3.1-38

MC10141

3.1-37

MC100E452

3.1-23

MC100H681

3.1-38

MC10153

3.1-31

MC100E457

3.1-33

MC100LVE111

3.1-17

MC10154

3.1-19

MC100EL01

3.1-27

MC100LVE164

3.1--32

MC10158

3.1-32

MC100EL04

3.1-27

MC100LVE210

3.1-14

MC10159

3.1--32

MC100EL05

3.1-27

MC100LVE310

3.1-14

MC10160

3.1-34

MC100EL07

3.1-27

MC100LVEL11

3.1-14

MC10161

3.1-21

MC100EL11

3.1-17

MC100LVEL13

3.1-14

MC10162

3.1-21

Logic: Standard, Special and Programmable

3.1-40

Motorola Master Selection Guide

Device Index
MC10163

3.1-22

MC10E157

3.1-33

MC10ELT25

3.1-38

MC10164

3.1-32

MC10E158

3.1-31

MC10ELT28

3.1-39

MC10165

3.1-22

MC10E160

3.1-34

MC10Hl00

3.1-28

MC10166

3.1-18

MC10E163

3.1-31

MC10Hl0l

3.1-27

MC10168

3.1-31

MC10E164

3.1-31

MC10Hl02

3.1-28

MC10170

3.1-34

MC10E1651

3.1-18

MC10Hl03

3.1-29

MC10171

3.1-21

MC10E1652

3.1-18

MC10Hl04

3.1-26

MC10172

3.1-21

MC10E166

3.1-18

MC10Hl05

3.1-27

MC10173

3.1-33

MC10E167

3.1-23

MC10Hl06

3.1-28

MC10174

3.1-32

MC10E171

3.1-31

MC10Hl07

3.1-27

MC10175

3.1-31

MC10E175

3.1-30

MC10H109

3.1-27

MC10176

3.1-24

MC10E193

3.1-34

MC10H113

3.1-28

MC10177

3.1-39

MC10E195

3.1-35

MC10Hl15

3.1-36

MC10178

3.1-19

MC10E196

3.1-35

MC10H116

3.1-36

MC10180

3.1-14

MC10E197

3.1-31

MC10H117

3.1-27

MC10181

3.1-14

MC10E211

3.1-17

MC10Hl18

3.1-27

MC10186

3.1-24

MC10E212

3.1-36

MC10Hl19

3.1-27

MC10188

3.1-29

MC10E241

3.1-37

MC10H121

3.1-27

MC10189

3.1-29

MC10E256

3.1-30

MC10H123

3.1-17

MC10190

3.1-38

MC10E336

3.1-14

MC10H124

3.1-38

MC10191

3.1-38

MC10E337

3.1-15

MC10H125

3.1-38

MC10192

3.1-17

MC10E404

3.1-27

MC10H130

3.1-30

MC10193

3.1-22

MC10E411

3.1-17

MC10H131

3.1-24

MC10195

3.1-29

MC10E416

3.1-36

MC10H135

3.1-23

MC10197

3.1-25

MC10E431

3.1-23

MC10H136

3.1-21

MC10198

3.1-33

MC10E445

3.1-19

MC10H141

3.1-37

MC10210

3.1-28

MC10E446

3.1-19

MC10H145

3.1-36

MC10211

3.1-28

MC10E451

3.1-23

MC10H158

3.1-33

MC10212

3.1-27

MC10E452

3.1-23

MC10H159

3.1-33

MC10216

3.1-35

MC10E457

3.1-33

MC10H16

3.1-19

MC10231

3.1-24

MC10ELOl

3.1-27

MC10H160

3.1-34

MC10804

3.1-38

MC10EL04

3.1-27

MC10H161

3.1-21

MC10805

3.1-38

MC10EL05

3.1-27

MC10H162

3.1-21

MC10E016

3.1-19

MC10EL07

3.1-27

MC10H164

3.1-32

MC10El0l

3.1-27

MC10EL11

3.1-17

MC10H165

3.1-22

MC10El04

3.1-27

MC10EL12

3.1-29

MC10H166

3.1-18

MC10El07

3.1-27

MC10EL15

3.1-17

MC10H171

3.1-21

MC10E111

3.1-17

MC10EL16

3.1-35

MC10H172

3.1-21

MC10El12

3.1-30

MC10EL31

3.1-23

MC10H173

3.1-32

MC10El16

3.1-36

MC10EL32

3.1-22

MC10H174

3.1-32

MC10E122

3.1-29

MC10EL33

3.1-22

MC10H175

3.1-31

MC10E131

3.1-23

MC10EL34

3.1-18

MC10H176

3.1-24

MC10E136

3.1-19

MC10EL35

3.1-24

MC10H179

3.1-14

MC10E137

3.1-19

MC10EL51

3.1-23

MC10H180

3.1-14

MC10E141

3.1-37

MC10EL52

3.1-23

MC10H181

3.1-14

MC10E142

3.1-37

MC10EL57

3.1-31

MC10H186

3.1-24

MC10E143

3.1-23

MC10EL58

3.1-31

MC10H188

3.1-29

MC10E150

3.1-30

MC10EL89

3.1-22

MC10H189

3.1-29

MC10E151

3.1-23

MC10ELT20

3.1-39

MC10H209

3.1-27

MC10E154

3.1-30

MC10ELT21

3.1-38

MC10H210

3.1-28

MC10E155

3.1-30

MC10ELT22

3.1-38

MC10H211

3.1-28

MC10E156

3.1-30

MC10ELT24

3.1-39

MC10H330

3.1-17

Motorola Master Selection Guide

3.1-41

Logic: Standard, Special and Programmable

Device Index
MC10H332

3.1-15

MC12028A

3.1-34

MC14012B

3.1-25

MC10H334

3.1-17

MC12028B

3.1-34

MC14012UB

3.1-25

MC10H350

3.1-38

MC12031A

3.1-35

MC14013B

3.1-23

MC10H351

3.1-38

MC12031B

3.1-35

MC14014B

3.1-37

MC10H352

3.1-38

MC12032A

3.1-35

MC14015B

3.1-37

MC10H423

3.1-17

MC12032B

3.1-35

MC14016B

3.1-33

MC10H424

3.1-38

MC12033A

3.1-35

MC14017B

3.1-20

MC10H600

3.1-38

MC12033B

3.1-35

MC14018B

3.1-20

MC10H601

3.1-38

MC12034A

3.1-35

MC14020B

3.1-19

MC10H602

3.1-38

MC12034B

3.1-35

MC14021B

3.1-37

MC10H603

3.1-38

MC12036A

3.1-34

MC14022B

3.1-20

MC10H604

3.1-38

MC12036B

3.1-34

MC14023B

3.1-26

MC10H605

3.1-38

MC12038A

3.1-34

MC14023UB

3.1-26

MC10H606

3.1-39

MC12040

3.1-22

MC14024B

3.1-19

MC10H607

3.1-38

MC12052A

3.1-35

MC14025B

3.1-28

MC10H640

3.1-17

MC12053A

3.1-35

MC14025UB

3.1-28

MC10H641

3.1-18

MC12054A

3.1-35

MC14027B

3.1-23

MC10H642

3.1-17

MC12058

3.1-34

MC14028B

3.1-21

MC10H643

3.1-18

MC12061

3.1-34

MC14029B

3.1-20

MC10H644

3.1-17

MC12073

3.1-34

MC14035B

3.1-37

MC10H645

3.1-17

MC12074

3.1-34

MC14038B

3.1-14

MC10H646

3.1-18

MC12075

3.1-35

MC14040B

3.1-19

MC10H660

3.1-31

MC12076

3.1-35

MC14042B

3.1-31

MC10H680

3.1-38

MC12078

3.1-35

MC14043B

3.1-31

MC10H681

3.1-38

MC12079

3.1-35

MC14044B

3.1-31

MC10SX1130

3.1-18

MC12080

3.1-34

MC14046B

3.1-34

MClOSX1130

3.1-22

MC12083

3.1-34

MC14049B

3.1-29

MC10SX1189

3.1-18

MC12089

3.1-35

MC14049UB

3.1-29

MC12002

3.1-21

MC12090

3.1-35

MC14050B

3.1-29

MC12009

3.1-35

MC12093

3.1-34

MC14051B

3.1-31

MC12011

3.1-35

MC12095

3.1-35

MC14052B

3.1-32

MC12013

3.1-35

MC12100

3.1-33

MC14053B

3.1-33

MC12014

3.1-20

MC12101

3.1-33

MC14060B

3.1-19

MC12015

3.1-35

MC12147

3.1-39

MC14066B

3.1-33

MC12016

3.1-35

MC12148

3.1-34

MC14067B

3.1-31

MC12017

3.1-35

MC12149

3.1-39

MC14068B

3.1-25

MC12018

3.1-35

MC12179

3.1-38

MC14069UB

3.1-29

MC12019

3.1-35

MC12202

3.1-38

MC14070B

3.1-28

MC12022A

3.1-34

MC12206

3.1-38

MC14071B

3.1-29

MC12022B

3.1-34

MC12210

3.1-38

MC14072B

3.1-28

MC12022LVA

3.1-34

MC12429

3.1-18

MC14073B

3.1-26

MC12022LVB

3.1-34

MC12439

3.1-18

MC14075B

3.1-29

MC12022SLA

3.1-34

MC14000UB

3.1-28

MC14076B

3.1-25

MC12022SLB

3.1-34

MC14001B

3.1-28

MC14077B

3.1-27

MC12022TSA

3.1-34

MC14001UB

3.1-28

MC14078B

3.1-28

MC12022TSB

3.1-34

MC14002B

3.1-28

MC14081B

3.1-26

MC12022TVA

3.1-35

MC14002UB

3.1-28

MC14082B

3.1-25

MC12022TVB

3.1-35

MC14006B

3.1-36

MC14093B

3.1-36

MC12023

3.1-35

MC14007UB

3.1-29

MC14094B

3.1-37

MC12025

3.1-35

MC14008B

3.1-14

MC14099B

3.1-30

MC12026A

3.1-34

MC14011B

3.1-26

MC14106B

3.1-36

MC12026B

3.1-34

MC14011UB

3.1-26

MC14161B

3.1-19

Logic: Standard, Special and Programmable

3.1-42

Motorola Master Selection Guide

Device Index
MC14163B

3.1-19

MC14566B

3.1-20

MC54HC27

3.1-28

MC14174B

3.1-24

MC14568B

3.1-20

MC54HC273A

3.1-24

MC14175B

3.1-25

MC14569B

3.1-20

MC54HC32A

3.1-29

MC14194B

3.1-37

MC14572UB

3.1-27

MC54HC354

3.1-32

MC14415

3.1-34

MC14580B

3.1-36

MC54HC365

3.1-15

MC14490

3.1-14

MC14583B

3.1-36

MC54HC366

3.1-15

MC14500B

3.1-29

MC14584B

3.1-36

MC54HC367

3.1-15

MC14501UB

3.1-27

MC14585B

3.1-18

MC54HC373A

3.1-31

MC14502B

3.1-30

MC14598B

3.1-30

MC54HC374A

3.1-25

MC14503B

3.1-15

MC14599B

3.1-30

MC54HC390

3.1-20

MC14504B

3.1-38

MC1648

3.1-34

MC54HC393

3.1-20

MC14506UB

3.1-27

MC1650

3.1-19

MC54HC4016

3.1-33

MC14508B

3.1-30

MC1651

3.1-19

MC54HC4040A

3.1-19

MC14510B

3.1-20

MC1658

3.1-34

MC54HC4049

3.1-29

MC14511B

3.1-22

MC1660

3.1-27

MC54HC4050

3.1-29

MC14512B

3.1-31

MC1662

3.1-28

MC54HC4051

3.1-31

MC14513B

3.1-22

MC1670

3.1-24

MC54HC4053

3.1-33

MC14514B

3.1-21

MC1672

3.1-28

MC54HC4060

3.1-19

MC14515B

3.1-21

MC1692

3.1-36

MC54HC4060A

3.1-19

MC14516B

3.1-20

MC4016

3.1-20

MC54HC4066

3.1-33

MC14517B

3.1-37

MC4018

3.1-20

MC54HC4351

3.1-31

MC14518B

3.1-20

MC4024

3.1-33

MC54HC4353

3.1-33

MC14519B

3.1-27

MC4044

3.1-21

MC54HC4538A

3.1-33

MC14520B

3.1-20

MC4316

3.1-20

MC54HC533A

3.1-31

MC14521B

3.1-34

MC4324

3.1-34

MC54HC534A

3.1-24
3.1-16

MC14522B

3.1-20

MC4344

3.1-21

MC54HC540A

MC14526B

3.1-20

MC54HCOOA

3.1-26

MC54HC541A

3.1-16

MC14527B

3.1-14

MC54HC02A

3.1-28

MC54HC563

3.1-31
3.1-31

MC14528B

3.1-33

MC54HC04A

3.1-29

MC54HC573A

MC14529B

3.1-32

MC54HC08A

3.1-26

MC54HC574A

3.1-25

MC14530B

3.1-27

MC54HC132A

3.1-36

MC54HC589

3.1-37

MC14531B

3.1-34

MC54HC138A

3.1-21

MC54HC595A

3.1-37

MC14532B

3.1-22

MC54HC139A

3.1-21

MC54HC597

3.1-37

MC14534B

3.1-19

MC54HC14A

3.1-36

MC54HC640A

3.1-16

MC14536B

3.1-34

MC54HC154

3.1-21

MC54HC646

3.1-16

MC14538B

3.1-33

MC54HC157A

3.1-32

MC54HC688

3.1-18

MC14539B

3.1-32

MC54HC158

3.1-32

MC54HC74A

3.1-23

MC14541B

3.1-34

MC54HC160

3.1-20

MC54HC86

3.1-28

MC14543B

3.1-22

MC54HC161A

3.1-20

MC54HCTOOA

3.1-26

MC14544B

3.1-22

MC54HC162

3.1-20

MC54HCT08A

3.1-26

MC14547B

3.1-22

MC54HC163A

3.1-20

MC54HCT14A

3.1-36

MC14549B

3.1-38

MC54HCl64

3.1-37

MC54HCT161A

3.1-20

MC14551B

3.1-32

MC54HC165

3.1-37

MC54HCT163A

3.1-20

MC14553B

3.1-19

MC54HC174A

3.1-24

MC54HCT241A

3.1-16

MC14555B

3.1-21

MC54HC175

3.1-25

MC54HCT244A

3.1-16

MC14556B

3.1-21

MC54HC175A

3.1-25

MC54HCT245A

3.1-15

MC14557B

3.1-36

MC54HC240A

3.1-16

MC54HCT32A

3.1-29

MC14558B

3.1-22

MC54HC241A

3.1-16

MC54HCT373A

3.1-30

MC14559B

3.1-38

MC54HC244A

3.1-16

MC54HCT374A

3.1-24

MC14560B

3.1-14

MC54HC245A

3.1-16

MC54HCT574A

3.1-25

MC14561B

3.1-14

MC54HC251

3.1-31

MC660

3.1-22

MC14562B

3.1-36

MC54HC259

3.1-21

MC661

3.1-22

Motorola Master Selection Guide

3.1-43

Logic: Standard, Special and Programmable

Device Index
MC662

3.1-22

MC74AC259

3.1-30

MC74ACT160

3.1-20

MC663

3.1-23

MC74AC273

3.1-24

MC74ACT161

3.1-20

MC664

3.1-24

MC74AC299

3.1-37

MC74ACT162

3.1-20

MC667

3.1-33

MC74AC32

3.1-29

MC74ACT163

3.1-20

MC668

3.1-30

MC74AC323

3.1-37

MC74ACT174

3.1-24

MC669

3.1-22

MC74AC350

3.1-37

MC74ACT175

3.1-25

MC670

3.1-30

MC74AC352

3.1-32

MC74ACT194

3.1-37

MC671

3.1-30

MC74AC353

3.1-32

MC74ACT20

3.1-25

MC672

3.1-30

MC74AC373

3.1-31

MC74ACT240

3.1-16

MC677

3.1-29

MC74AC374

3.1-24

MC74ACT241

3.1-16

MC678

3.1-29

MC74AC377

3.1-24

MC74ACT244

3.1-16

MC68150'33

3.1-15

MC74AC378

3.1-23

MC74ACT245

3.1-15

MC68150'40

3.1-15

MC74AC4020

3.1-19

MC74ACT251

3.1-32

MC68194

3.1-17

MC74AC4040

3.1-19

MC74ACT253

3.1-32

MC74ACOO

3.1-26

MC74AC533

3.1-31

MC74ACT256

3.1-30

MC74AC02

3.1-28

MC74AC534

3.1-25

MC74ACT257

3.1-33

MC74AC04

3.1-29

MC74AC540

3.1-16

MC74ACT258

3.1-33

MC74AC05

3.1-29

MC74AC541

3.1-16

MC74ACT259

3.1-30

MC74AC08

3.1-26

MC74AC563

3.1-30

MC74ACT273

3.1-24

MC74AC10

3.1-26

MC74AC564

3.1-25

MC74ACT299

3.1-37

MC74AC109

3.1-24

MC74AC573

3.1-30

MC74ACT32

3.1-29

MC74AC11

3.1-26

MC74AC574

3.1-25

MC74ACT323

3.1-37

MC74AC112

3.1-23

MC74AC620

3.1-15

MC74ACT350

3.1-37

MC74AC113

3.1-23

MC74AC623

3.1-15

MC74ACT352

3.1-32

MC74AC125

3.1-17

MC74AC640

3.1-15

MC74ACT353

3.1-32

MC74AC126

3.1-17

MC74AC643

3.1-15

MC74ACT373

3.1-31

MC74AC132

3.1-36

MC74AC646

3.1-16

MC74ACT374

3.1-25

MC74AC138

3.1-21

MC74AC648

3.1-16

MC74ACT377

3.1-24

MC74AC139

3.1-21

MC74AC652

3.1-16

MC74ACT378

3.1-23

MC74AC14

3.1-36

MC74AC74

3.1-23

MC74ACT521

3.1-18

MC74AC151

3.1-31

MC74AC810

3.1-27

MC74ACT533

3.1-31

MC74AC153

3.1-32

MC74AC86

3.1-27

MC74ACT534

3.1-25

MC74AC157

3.1-33

MC74ACTOO

3.1-26

MC74ACT540

3.1-16

MC74AC158

3.1-33

MC74ACT02

3.1-28

MC74ACT541

3.1-16

MC74AC160

3.1-20

MC74ACT04

3.1-29

MC74ACT563

3.1-30

MC74AC161

3.1-20

MC74ACT05

3.1-29

MC74ACT564

3.1-25

MC74AC162

3.1-20

MC74ACT08

3.1-26

MC74ACT573

3.1-31

MC74AC163

3.1-20

MC74ACT10

3.1-26

MC74ACT574

3.1-25

MC74AC174

3.1-24

MC74ACT109

3.1-24

MC74ACT620

3.1-15

MC74AC175

3.1-25

MC74ACT11

3.1-26

MC74ACT623

3.1-15

MC74AC190

3.1-21

MC74ACT112

3.1-23

MC74ACT640

3.1-15

MC74AC194

3.1-37

MC74ACT113

3.1-23

MC74ACT643

3.1-15

MC74AC20

3.1-25

MC74ACT125

3.1-17

MC74ACT646

3.1-16

MC74AC240

3.1-16

MC74ACT126

3.1-17

MC74ACT648

3.1-16

MC74AC241

3.1-16

MC74ACT132

3.1-36

MC74ACT652

3.1-16

MC74AC244

3.1-16

MC74ACT138

3.1-21

MC74ACT74

3.1-23

MC74AC245

3.1-15

MC74ACT139

3.1-21

MC74ACT810

3.1-27

MC74AC251

3.1-32

MC74ACT14

3.1-36

MC74ACT86

3.1-28

MC74AC253

3.1-32

MC74ACT151

3.1-31

MC74FOO

3.1-26

MC74AC256

3.1-30

MC74ACT153

3.1-32

MC74F02

3.1-28

MC74AC257

3.1-33

MC74ACT157

3.1-33

MC74F04

3.1-29

MC74AC258

3.1-33

MC74ACT158

3.1-33

MC74F08

3.1-26

Logic: Standard, Special and Programmable

3.1-44

Motorola Master Selection Guide

Device Index
MC74F10

3.1-26

MC74F352

3.1-32

MC74HC10

3.1-26

MC74F109

3.1-24

MC74F353

3.1-32

MC74HC107

3.1-23

MC74F11

3.1-26

MC74F365

3.1-15

MC74HC109

3.1-24

MC74Fl12

3.1-24

MC74F366

3.1-15

MC74HC11

3.1-26

MC74F1245

3.1-15

MC74F367

3.1-15

MC74HCl12

3.1-23

MC74F125

3.1-17

MC74F368

3.1-15

MC74HC125A

3.1-17

MC74F126

3.1-17

MC74F37

3.1-26

MC74HC126A

3.1-17

MC74F13

3.1-36

MC74F373

3.1-31

MC74HC132A

3.1-36

MC74F132

3.1-36

MC74F374

3.1-24

MC74HC133

3.1-25

MC74F138

3.1-21

MC74F377

3.1-24

MC74HC137

3.1-21

MC74F139

3.1-21

MC74F378

3.1-36

MC74HC138A

3.1-21

MC74F14

3.1-36

MC74F379

3.1-25

MC74HC139A

3.1-21

MC74F148

3.1-22

MC74F38

3.1-26

MC74HC147

3.1-22

MC74F151

3.1-31

MC74F381

3.1-14

MC74HC14A

3.1-36

MC74F153

3.1-32

MC74F382

3.1-14

MC74HC151

3.1-31

MC74F157A

3.1-32

MC74F3893A

3.1-38

MC74HC153

3.1-32

MC74F158A

3.1-32

MC74F398

3.1-33

MC74HC154

3.1-21

MC74F160A

3.1-19

MC74F399

3.1-33

MC74HC157A

3.1-32

MC74F161A

3.1-19

MC74F40

3.1-25

MC74HC158

3.1-32

MC74F162A

3.1-19

MC74F51

3.1-27

MC74HC160

3.1-20

MC74F163A

3.1-19

MC74F521

3.1-18

MC74HC161A

3.1-20

MC74F164

3.1-37

MC74F533

3.1-31

MC74HC162

3.1-20

MC74F168

3.1-19

MC74F534

3.1-25

MC74HC163

3.1-20

MC74F169

3.1-19

MC74F537

3.1-21

MC74HCl64

3.1-37

MC74F174

3.1-24

MC74F538

3.1-21

MC74HC165

3.1-37

MC74F175

3.1-25

MC74F539

3.1-21

MC74HC173

3.1-25

MC74F1803

3.1-17

MC74F543

3.1-16

MC74HC174A

3.1-24

MC74F181

3.1-14

MC74F544

3.1-16

MC74HC175

3.1-25

MC74F182

3.1-14

MC74F568

3.1-19

MC74HC175A

3.1-25

MC74F194

3.1-37

MC74F569

3.1-19

MC74HC194

3.1-37

MC74F195

3.1-37

MC74F574

3.1-24

MC74HC195

3.1-37

MC74F20

3.1-25

MC74F579

3.1-19

MC74HC20

3.1-25

MC74F21

3.1-25

MC74F620

3.1-16

MC74HC237

3.1-21

MC74F240

3.1-15

MC74F623

3.1-16

MC74HC240A

3.1-16

MC74F241

3.1-15

MC74F64

3.1-27

MC74HC241A

3.1-16

MC74F242

3.1-17

MC74F640

3.1-16

MC74HC242

3.1-17

MC74F243

3.1-17

MC74F646

3.1-16

MC74HC244A

3.1-16

MC74F244

3.1-15

MC74F657A

3.1-15

MC74HC245A

3.1-16

MC74F245

3.1-15

MC74F657B

3.1-15

MC74HC251

3.1-31

MC74F251

3.1-31

MC74F74

3.1-23

MC74HC253

3.1-32

MC74F253

3.1-32

MC74F779

3.1-19

MC74HC257

3.1-32

MC74F256

3.1-30

MC74F803

3.1-17

MC74HC259

3.1-21

MC74F257A

3.1-33

MC74F823

3.1-15

MC74HC27

3.1-28

MC74F258A

3.1-33

MC74F827

3.1-14

MC74HC273A

3.1-24

MC74F259

3.1-30

MC74F828

3.1-14

MC74HC280

3.1-34

MC74F269

3.1-19

MC74F85

3.1-18

MC74HC299

3.1-37

MC74F280

3.1-34

MC74F86

3.1-28

MC74HC30

3.1-25

MC74F283

3.1-14

MC74HCOOA

3.1-26

MC74HC32A

3.1-29

MC74F299

3.1-37

MC74HC02A

3.1-28

MC74HC354

3.1-32

MC74F32

3.1-29

MC74HC03A

3.1-26

MC74HC365

3.1-15

MC74F323

3.1-37

MC74HC04A

3.1-29

MC74HC366

3.1-15

MC74F350

3.1-37

MC74HC08A

3.1-26

MC74HC367

3.1-15

Motorola Master Selection Guide

3.1-45

Logic: Standard, Special and Programmable

Device Index
MC74HC368

3.1-15

MC74HCTOOA

3.1-26

MC836

3.1-29

MC74HC373A

3.1-31

MC74HCT04A

3.1-29

MC837

3.1-29

MC74HC374A

3.1-25

MC74HCT08A

3.1-26

MC840

3.1-29

MC74HC390

3.1-20

MC74HCT138A

3.1-21

MC844

3.1-22

MC74HC393

3.1-20

MC74HCT14A

3.1-36

MC845

3.1-23

MC74HC4002

3.1-28

MC74HCT157A

3.1-32

MC846

3.1-26

MC74HC4016

3.1-33

MC74HCT161A

3.1-20

MC849

3.1-26

MC74HC4017

3.1-20

MC74HCT163A

3.1-20

MC88913

3.1-18

MC74HC4020A

3.1-19

MC74HCT174A

3.1-24

MC88914

3.1-18

MC74HC4024

3.1-34

MC74HCT240A

3.1-16

MC88915*55

3.1-18

MC74HC4040A

3.1-19

MC74HCT241A

3.1-16

MC88915*70

3.1-18

MC74HC4046A

3.1-39

MC74HCT244A

3.1-16

MC88915T*100

3.1-18

MC74HC4049

3.1-29

MC74HCT245A

3.1-15

MC88915T*133

3.1-18

MC74HC4050

3.1-29

MC74HCT273A

3.1-24

MC88915T*160

3.1-18

MC74HC4051

3.1-31

MC74HCT32A

3.1-29

MC88915T*55

3.1-18

MC74HC4052

3.1-32

MC74HCT373A

3.1-30

MC88915T*70

3.1-18

MC74HC4053

3.1-33

MC74HCT374A

3.1-24

MC88916*70

3.1-18

MC74HC4060

3.1-19

MC74HCT541A

3.1-16

MC88916*80

3.1-18

MC74HC4060A

3.1-19

MC74HCT573A

3.1-31

MC88920

3.1-17

MC74HC4066

3.1-33

MC74HCT574A

3.1-25

MC88921

3.1-17

MC74HC4075

3.1-29

MC74HCT74A

3.1-23

MC88LV926

3.1-18

MC74HC4078

3.1-27

MC74HCU04

3.1-29

MC88PL117

3.1-17

MC74HC42

3.1-21

MC74LCXOO

3.1-26

MC936

3.1-29

MC74HC4316

3.1-33

MC74LCX02

3.1-28

MC937

3.1-29

MC74HC4351

3.1-31

MC74LCX04

3.1-30

MC944

3.1-22

MC74HC4353

3.1-33

MC74LCX08

3.1-26

MC945

3.1-23

MC74HC4511

3.1-22

MC74LCX240

3.1-14

MC946

3.1-26

MC74HC4514

3.1-21

MC74LCX244

3.1-14

MC951

3.1-33

MC74HC4538A

3.1-33

MC74LCX245

3.1-38

MC952

3.1-23

MC74HC51

3.1-27

MC74LCX32

3.1-28

MC953

3.1-23

MC74HC533A

3.1-31

MC74LCX373

3.1-30

MCCS142233

3.1-36

MC74HC534A

3.1-24

MC74LCX374

3.1-24

MCCS142234

3.1-36

MC74HC540A

3.1-16

MC74LCX540

3.1-14

MCCS142235

3.1-36

MC74HC541A

3.1-16

MC74LCX541

3.1-14

MCCS142237

3.1-36

MC74HC563

3.1-31

MC74LCX573

3.1-30

MCH12140

3.1-22

MC74HC564

3.1-25

MC74LCX574

3.1-24

MCK12140

3.1-22

MC74HC573A

3.1-31

MC74LVQOO

3.1-26

MCM10139

3.1-35

MC74HC574A

3.1-25

MC74LVQ04

3.1-30

MCM10143

3.1-36

MC74HC58

3.1-27

MC74LVQ125

3.1-14

MCM10145

3.1-36

MC74HC589

3.1-37

MC74LVQ138

3.1-21

MCM10146

3.1-35

MC74HC595A

3.1-37

MC74LVQ240

3.1-14

MCM10149*25

3.1-35

MC74HC597

3.1-37

MC74LVQ244

3.1-14

MCM10152

3.1-35

MC74HC640A

3.1-16

MC74LVQ245

3.1-38

MPC903

3.1-17

MC74HC646

3.1-16

MC74LVQ373

3.1-30

MPC904

3.1-17

MC74HC688

3.1-18

MC74LVQ374

3.1-24

MPC930

3.1-18

MC74HC7266

3.1-27

MC74LVQ541

3.1-14

MPC931

3.1-18

MC74HC73

3.1-23

MC74LVQ573

3.1-30

MPC947

3.1-17

MC74HC74A

3.1-23

MC74LVQ574

3.1-24

MPC948

3.1-17

MC74HC75

3.1-30

MC74LVQ646

3.1-38

MPC950

3.1-18

MC74HC76

3.1-23

MC74LVQ652

3.1-38

MPC951

3.1-18

MC74HC85

3.1-18

MC830

3.1-25

MPC956

3.1-18

MC74HC86

3.1-28

MC832

3.1-14

MPC970

3.1-18

Logic: Standard, Special and Programmable

3.1-46

Motorola Master Selection Guide

Device Index
SN54LSOO

3,1-26

SN54LS191

3,1-20

SN54LS373

3,1-31

SN54LS01

3,1-26

SN54LS192

3,1-20

SN54LS374

3,1-25

SN54LS02

3,1-28

SN54LS193

3,1-20

SN54LS375

3,1-30

SN54LS03

3,1-26

SN54LS194A

3,1-37

SN54LS377

3,1-24

SN54LS04

3,1-29

SN54LS195A

3,1-38

SN54LS378

3,1-24

SN54LS05

3,1-29

SN54LS196

3,1-19

SN54LS379

3,1-23

SN54LS08

3,1-26

SN54LS197

3,1-19

SN54LS38

3,1-26

SN54LS09

3,1-26

SN54LS20

3,1-25

SN54LS386

3,1-28

SN54LS10

3,1-26

SN54LS21

3,1-25

SN54LS390

3,1-20

SN54LS107A

3,1-23

SN54LS22

3,1-25

SN54LS393

3,1-20

SN54LS109A

3,1-23

SN54LS221

3,1-33

SN54LS398

3,1-33

SN54LS11

3,1-26

SN54LS240

3,1-15

SN54LS399

3,1-33

SN54LSl12A

3,1-23

SN54LS241

3,1-15

SN54LS40

3,1-25

SN54LSl13A

3,1-23

SN54LS242

3,1-17

SN54LS42

3,1-21

SN54LSl14A

3,1-23

SN54LS243

3,1-17

SN54LS47

3,1-22

SN54LS12

3,1-26

SN54LS244

3,1-15

SN54LS48

3,1-22

SN54LS122

3,1-33

SN54LS245

3,1-16

SN54LS490

3,1-20

SN54LS123

3,1-33

SN54LS247

3,1-22

SN54LS51

3,1-27

SN54LS125A

3,1-16

SN54LS248

3,1-22

SN54LS54

3,1-27

SN54LS126A

3,1-17

SN54LS249

3,1-22

SN54LS540

3,1-16

SN54LS13

3,1-36

SN54LS251

3,1-31

SN54LS541

3,1-16

SN54LS132

3,1-36

SN54LS253

3,1-32

SN54LS55

3,1-27

SN54LS133

3,1-25

SN54LS256

3,1-30

SN54LS569A

3,1-19

SN54LS137

3,1-21

SN54LS2578

3,1-33

SN54LS623

3,1-16

SN54LS138

3,1-21

SN54LS2588

3,1-33

SN54LS640

3,1-16

SN54LS139

3,1-21

SN54LS259

3,1-30

SN54LS641

3,1-38

SN54LS14

3,1-36

SN54LS26

3,1-26

SN54LS642

3,1-38

SN54LS145

3,1-21

SN54LS260

3,1-28

SN54LS645

3,1-16

SN54LS147

3,1-22

SN54LS266

3,1-27

SN54LS669

3,1-20

SN54LS148

3,1-22

SN54LS27

3,1-28

SN54LS670

3,1-36

SN54LS15

3,1-26

SN54LS273

3,1-24

SN54LS682

3,1-18

SN54LS151

3,1-31

SN54LS279

3,1-31

SN54LS684

3,1-18

SN54LS153

3,1-32

SN54LS28

3,1-28

SN54LS688

3,1-18

SN54LS155

3,1-21

SN54LS280

3,1-34

SN54LS73A

3,1-24

SN54LS156

3,1-21

SN54LS283

3,1-14

SN54LS748

3,1-22

SN54LS157

3,1-32

SN54LS290

3,1-20

SN54LS74A

3,1-23

SN54LS158

3,1-32

SN54LS293

3,1-19

SN54LS75

3,1-30

SN54LS160A

3,1-19

SN54LS298

3,1-33

SN54LS76A

3,1-23

SN54LS161A

3,1-19

SN54LS299

3,1-37

SN54LS77

3,1-30

SN54LS162A

3,1-19

SN54LS30

3,1-25

SN54LS795

3,1-15

SN54LS163A

3,1-19

SN54LS32

3,1-29

SN54LS796

3,1-15

SN54LS164

3,1-37

SN54LS322A

3,1-37

SN54LS797

3,1-15

SN54LS165

3,1-37

SN54LS323

3,1-37

SN54LS798

3,1-15

SN54LS166

3,1-37

SN54LS33

3,1-28

SN54LS83A

3,1-14

SN54LS168

3,1-19

SN54LS348

3,1-22

SN54LS848

3,1-22

SN54LS169

3,1-20

SN54LS352

3,1-32

SN54LS85

3,1-18

SN54LS170

3,1-36

SN54LS353

3,1-32

SN54LS86

3,1-28

SN54LS173A

3,1-23

SN54LS365A

3,1-15

SN54LS90

3,1-20

SN54LS174

3,1-24

SN54LS366A

3,1-15

SN54LS92

3,1-20

SN54LS175

3,1-25

SN54LS367A

3,1-15

SN54LS93

3,1-19

SN54LS181

3,1-14

SN54LS368A

3,1-15

SN54LS958

3,1-37

SN54LS190

3,1-20

SN54LS37

3,1-26

SN74LSOO

3,1-26

Motorola Master Selection Guide

3,1-47

Logic: Standard, Special and Programmable

Device Index
SN74LS01

3.1-26

SN74LS191

3.1-20

SN74LS374

3.1-25

SN74LS02

3.1-28

SN74LS192

3.1-20

SN74LS375

3.1-30

SN74LS03

3.1-26

SN74LS193

3.1-20

SN74LS377

3.1-24

SN74LS04

3.1-29

SN74LS194A

3.1-37

SN74LS378

3.1-24

SN74LS05

3.1-29

SN74LS195A

3.1-38

SN74LS379

3.1-23

SN74LS08

3.1-26

SN74LS196

3.1-19

SN74LS38

3.1-26

SN74LS09

3.1-26

SN74LS197

3.1-19

SN74LS386

3.1-28

SN74LS10

3.1-26

SN74LS20

3.1-25

SN74LS390

3.1-20

SN74LS107A

3.1-23

SN74LS21

3.1-25

SN74LS393

3.1-20

SN74LS109A

3.1-23

SN74LS22

3.1-25

SN74LS395

3.1-37

SN74LS11

3.1-26

SN74LS221

3.1-33

SN74LS398

3.1-33

SN74LS112A

3.1-23

SN74LS240

3.1-15

SN74LS399

3.1-33

SN74LS113A

3.1-23

SN74LS241

3.1-15

SN74LS40

3.1-25

SN74LS114A

3.1-23

SN74LS242

3.1-17

SN74LS42

3.1-21

SN74LS12

3.1-26

SN74LS243

3.1-17

SN74LS47

3.1-22

SN74LS122

3.1-33

SN74LS244

3.1-15

SN74LS48

3.1-22

SN74LS123

3.1-33

SN74LS245

3.1-16

SN74LS490

3.1-20

SN74LS125A

3.1-16

SN74LS247

3.1-22

SN74LS51

3.1-27

SN74LS126A

3.1-17

SN74LS248

3.1-22

SN74LS54

3.1-27

SN74LS13

3.1-36

SN74LS249

3.1-22

SN74LS540

3.1-16

SN74LS132

3.1-36

SN74LS251

3.1-31

SN74LS541

3.1-16

SN74LS133

3.1-25

SN74LS253

3.1-32

SN74LS55

3.1-27

SN74LS136

3.1-28

SN74LS257B

3.1-33

SN74LS569A

3.1-19

SN74LS137

3.1-21

SN74LS258B

3.1-33

SN74LS623

3.1-16

SN74LS138

3.1-21

SN74LS259

3.1-30

SN74LS640

3.1-16

SN74LS139

3.1-21

SN74LS26

3.1-26

SN74LS641

3.1-38

SN74LS14

3.1-36

SN74LS260

3.1-28

SN74LS642

3.1-38

SN74LS145

3.1-21

SN74LS266

3.1-27

SN74LS645

3.1-16

SN74LS147

3.1-22

SN74LS27

3.1-28

SN74LS669

3.1-20

SN74LS148

3.1-22

SN74LS273

3.1-24

SN74LS670

3.1-36

SN74LS15

3.1-26

SN74LS279

3.1-31

SN74LS682

3.1-18

SN74LS151

3.1-31

SN74LS28

3.1-28

SN74LS684

3.1-18

SN74LS153

3.1-32

SN74LS280

3.1-34

SN74LS688

3.1-18

SN74LS155

3.1-21

SN74LS283

3.1-14

SN74LS73A

3.1-24

SN74LS156

3.1-21

SN74LS290

3.1-20

SN74LS748

3.1-22

SN74LS157

3.1-32

SN74LS293

3.1-19

SN74LS74A

3.1-23

SN74LS158

3.1-32

SN74LS298

3.1-33

SN74LS75

3.1-30

SN74LS160A

3.1-19

SN74LS299

3.1-37

SN74LS76A

3.1-23

SN74LS161A

3.1-19

SN74LS30

3.1-25

SN74LS77

3.1-30

SN74LS162A

3.1-19

SN74LS32

3.1-29

SN74LS795

3.1-15

SN74LS163A

3.1-19

SN74LS322A

3.1-37

SN74LS796

3.1-15

SN74LS164

3.1-37

SN74LS323

3.1-37

SN74LS797

3.1-15

SN74LS165

3.1-37

SN74LS33

3.1-28

SN74LS798

3.1-15

SN74LS166

3.1-37

SN74LS348

3.1-22

SN74LS83A

3.1-14

SN74LS168

3.1-19

SN74LS352

3.1-32

SN74LS848

3.1-22

SN74LS169

3.1-20

SN74LS353

3.1-32

SN74LS85

3.1-18

SN74LS170

3.1-36

SN74LS365A

3.1-15

SN74LS86

3.1-28

SN74LS173A

3.1-23

SN74LS366A

3.1-15

SN74LS90

3.1-20

SN74LS174

3.1-24

SN74LS367A

3.1-15

SN74LS92

3.1-20

SN74LS175

3.1-25

SN74LS368A

3.1-15

SN74LS93

3.1-19

SN74LS181

3.1-14

SN74LS37

3.1-26

SN74LS95B

3.1-37

SN74LS190

3.1-20

SN74LS373

3.1-31

Logic: Standard, Special and Programmable

3.1-48

Motorola Master Selection Guide

Ordering Information
Device Nomenclatures
LS - Low Power Schottky
SN

ww

VV

xxxx v

~ Package Type

J
T
Range~

• N for Plastic (74 Series Only)
• J for Ceramic
• 0 for 150 mil Plastic SOIC (74 Series Only)
• OW for 300 mil Plastic SOIC (74 Series Only)

Standard Prefix

Temperature
• 74 Series (0 to +70°C)
• 54 Series (-55 to +125°C)

Function Type

Family - - - - - - - - - - - - - - - - - '
• LS = Low Power Schottky

FAST
MC

.-

Circuit Identifier

T
~

w

VV

XXXX

L

1

Temperature Range
• 74 Series (0 to +70°C)
Family - - - - - - - - - - - - - - - - - '
• F= FAST

V
Package Type
• N for Plastic (74 Series Only)
• 0 for 150 mil Plastic SOIC (74 Series Only)
• OW for 300 mil Plastic SOIC (74 Series Only)
Function Type

MECL 10K, MECL 10Hl100H
MC

Motorola
Circuit Identifier

~

WWW

xxx

Package Type
• P for Plastic
• L for Ceramic
• FN for PLCC

---------'1

Temperature Range
• 10 = 10K (-30 to +85°C)
• 10H = 10H (0 to +75°C)
• 100H = lOOK Compatible (0 to +85°C)

Motorola Master Selection Guide

VV

-r=

Function Type

3.1-49

Logic: Standard, Special and Programmable

ECLinPS, ECLinPS Lite
MC
Motorola
Circuit Identifier

WWW

1:

xxx yvy

ZZ
1

----.JT

• MC = Fully Qualified Circuit
• XC = Non Reliability Qualified

Package Type
• FN =PLCC
• D = Plastic SOIC
• L = Ceramic DIP
• P = Plastic DIP

Function Type
• yvy = 3-DigHs for ECLinPS
• yv= 2-Digits for ECLinPS Lite

Compatibility Identifier _ _ _ _ _ _---l
• 10 = 10H Compatible (0 to +85°C)
• 100 = 100K Compatible (0 to +85°C)

' - - - - - - - - - - - ECLinPS Family Identifier
• E = ECLinPS
• EL = ECLinPS Lite
• ELT = ECLinPS Lite Translator
• LVE = Low Voltage ECLinPS
• LVEL = Low Voltage ECLinPS Lite

Metal Gate 14000 Series CMOS
MC

T

14XXX YY

I

Motorola Circuit Identifier _ _ _ _
-r---J
Function Type _ _ _ _ _ _ _ _ _ _ _ _---J.

zz

T

_

Identifier (per JEDEC Standard)
• B (or Blank)= Buffered Outputs
• UB = Unbuffered Outputs

Package and Temperature Range
• CL for Ceramic -55 to + 125°C
• CP for Plastic -55 to +125°C
• D/DW for Small Outline Package (Plastic) -55 to + 125°C

High-Speed CMOS
MC

.-.

VV

I

Circuit Identifier

WWW

Y

XXXX

--c...-

I

Temperature Range
• 74 Series (-55 to +125°C)
• 54 Series (-55 to +125°C)

Package Type
• N for Plastic (74 Series Only)
• J for Ceramic (54 Series Only)
• D for 150 mil Plastic SOIC (74 Series Only)
• DW for 300 mil Plastic SOIC (74 Series Only)
Function Type
• XXIX) Same Function and Pin Configuration as
LSTIL
• 4XXX Same Function and Pin Configuration as
CMOS 14000
• 7XX(X) Variation of LSTIL or CMOS 14000
Device

High-Speed CMOS
Specification Identifier
• HC = Buffered High-Speed CMOS
• HCU = Unbuffered High-Speed CMOS'
• HCT = High-Speed CMOS TIL Compatible
'Not Available On All Devices

._.

Circuit Identifier

FACT

~T

Temperature Range Family
• 74AC = FACT (-40 to +85°C)
• 74ACT = TIL Compatible (-40 to +85°C)

Logic: Standard, Special and Programmable

xxx

YY
-,--

Package Type
• N for Plastic
• D for Narrow SOIC
• DW for Wide SOIC

Function Type

3.1-50

Motorola Master Selection Guide

Other Logic Circuits
MC/MCCS

wwwwww

Motorola
I
Circuit Identifier ----l
• MC = Standard Circuit Identifier
• MCCS = Circuit Chip-Set Identifier

x

VV
Package Type
• N for Plastic
• D for Narrow SOIC
• FNforPlCC
• FJ forClCC

Function Type _ _ _ _ _ _ _ _---l
Option Suffix Indicator

--------------1

Option Type

MECL IIIIHTUDTL
MC
Motorola
Circuit Identifier

XXXX

-----.JT

V
L:

Package Type
• P for Plastic
• l for Ceramic
• D for Narrow SOIC
• FN for PlCC
Function Type

LCX Products

.~.

Circuit Identifier

MC

74

LCX

VVVV

I I

Temperature Range
• 74 = -40 to +85°C

zz

~ Package Type
• D for Plastic Narrow JEDEC SOIC
• DW for Plastic Wide JEDEC SOIC
• M for Plastic EIAJ SOIC
• SD for Plastic SSOP
• DT for Plastic TSSOP
Function Type

Family Identifier
• lCX = 5V-Tolerant low-Voltage CMOS

LVQ Products
MC

.-

Circuit Identifier

74

LVQ

VVVV

I I

Temperature Range
• 74 = -40 to +85°C

zz

~ Package Type
• D for Plastic Narrow JEDEC SOIC
• DW for Plastic Wide JEDEC SOIC
• M for Plastic EIAJ SOIC
• SD for Plastic SSOP
• DT for Plastic TSSOP
Function Type

Family Identifier

• lVQ =low-Voltage Quiet CMOS

Motorola Master Selection Guide

3.1-51

logic: Standard, Special and Programmable

Motorola Programmable Arrays (MPA)
MPA

Motorola Programmable
Array Circuit Identifier

~

1XXXX

Family Identifier
• 1XXX = 1000 Series Programmable Array
• 17XXX = 17000 Series Serial EPROM

vv

C
Z

-I

Temperature Range
• Blank = 0 to + 70'C
• -I
= --40 to +85'C (Planned)
Speed Grade
• Consult Factory

L-_ _ _ _ _ _

Package Types

•
•
•
•
•

P
D
FN
FN
DD

=
=
=
=
=

8-Pin DIP
8-Pin SOIC
20-Pin PLCC
84--Pin PLCC
128-Pin PQFP

• DH =
=
• HI =
• KE =
• HV =

• DK

160-Pin PQFP
208-Pin PQFP
181-Pin PGA
224-Pin PGA
299-Pin PGA

MPA Design System Configuration Numbering

TT
MPA

Motorola Programmable
Array Circuit Identifier

x

I

v

L

Temperature Range
• P= PC
• W = Workstation

Development System Identifier
• E = Entry Series (Includes Full MPAI 016/1 036 Device Support)
• S = Standard Series (Includes All MPA1000 Family Support)

Logic: Standard, Special and Programmable

3.1-52

Motorola Master Selection Guide

Case Outlines
8-Pin Packages

L SUFFIX
CERAMIC DIP PACKAGE
CASE 693-03
ISSUE C

ff1I

OPTIONAL LEAD
CONFIGURATION

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEl.
4. DIMENSION F FOR FULL LEADS. HALF LEADS AT
LEAD POSITIONS 1, 4, 5, AND 8.
5. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC BODY.
DIM
A
B
C
0
E
F
G

l±l
SEATING
PLANE

J
K
L
M
N

INCHES
MAX
MIN
0.390 0.430
0.245 0.275
0.170 0.200
0.016 0.020
0.050 BSC
0.050 0.065
0.100 BSC
0.008 0.015
0.125 0.160
0.300 BSC
15°
0°
0.020 0.040

MILLIMETERS
MIN
MAX
9.91
10.92
6.22
6.98
4.32
5.08
0.41
0.51
1.27BSC
1.65
1.27
2.54 BSC
0.20
0.38
4.06
3.18
7.62 BSC
15°
0°
0.51
1.02

P SUFFIX
PLASTIC DIP PACKAGE
CASE 626-05
ISSUE K

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1962.

NOTE 2

DIM
A
B
C
0
F
G
H

-TSEATING
PLANE

J
K
L
M
N

H

Motorola Master Selection Guide

3.1-53

MILLIMETERS
MIN
MAX
9.40 10.16
6.10
6.60
3.94
.45
0.38
0.51
1.02
1.78
2.54BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 Bse
10°
0.76
1.01

INCHES
MIN
MAX
0.370 Q.400
0.240 0.260
0.165 0.175
0.Q15 0.020
0.040 0.070
0.100 BSC
0.030 0.050
0.008 0.012
0.115
0.135
0.300 Bse
10°
0.030 0.040

Logic: Standard, Special and Programmable

8-Pin Packages
DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751-Q5
ISSUE N

1 rLJ,c
~MO

m,
RX450

/"

€h"uT
..........

-1 F L

•

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B 00 NOT INCWDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE 0 DIMENSION AT MAXIMUM
MATERIAL CONDIllON

Dill
A
8
C

D
F

J

G
J
K
M
P
R

IIILLIllETERS
MIN
MAX
4.80
5.00
4.00
3.80
1.35
1.75
0.35
0.49
0.40
1.25
1.27BSC
0.18
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
O~O

INCHES
MIN
!lAX
0.189
.196
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
O.05OBSC
0.007 O. 9
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019

SDSUFFIX
PLASTIC SSOP PACKAGE
CASE 94D-03
ISSUE B

1 1-I 1$10.12(0.005)®lrlu ®lv®1

0.25 (0.010)

8xKREF

ITi8
l_
L

DETAILE
PIN 1

IDENT

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1962.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCWDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
5. DIMENSION K DOES NOT INCWDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13 (0.005)
TOTAL IN EXCESS OF K DIMENSION AT
MAXIMUM MATERIAL CONDITION. DAMBAR
INTRUSION SHALL NOT REDUCE DIMENSION K
BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL
CONDIllON.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.

SECTIONN-N
DIM

A
B

C
D
F

G
H
Jl
K
Kl
L
M

H

Logic: Standard, Special and Programmable

3.1-54

MILLIMETERS
MIN
MAX
2.87
3.13
5.38
5.20
1.73
1.99
0.21
0.05
0.63
0.95
O.
0.44
0.60
0.09
0.20
0.09
0.6
0.25
0.38
0.33
0.25
7.65
7.
8°
0°

INCHES
IIIN
MAX
0.113 0.123
0.205 0.212
0.068 0.078
0.002 0.008
0.024 0.037
0.026
001
0.023
0.003 0.008
0.003 0.006
0.010 0.015
0.010 0.013
.301
0.311
0°
8°

Motorola Master Selection Guide

14-Pin Packages
L,J SUFFIX
CERAMIC DIP PACKAGE
CASE 632--08
ISSUEY

c

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A

SEA1lNG
PLANE

B

~

C
D
F
G

F:JI: D G

J
K

14PL

1"::;$cTl':'-'0.2":-5(::-0.0:C-:
10"-;)@"I-=-rIrA-;;®"'1

1$10.25(0.010)@lrl B ® 1
P,N SUFFIX
PLASTIC DIP PACKAGE
CASE 646-06
ISSUE L

B

!-r'T"TT"T"T"11""T"t"..~7r!---.i

.1

L
M
N

B
C
D
F
G
H
J

K
L
M
N

DSUFFIX
PLASTIC SOIC PACKAGE
CASE 751A--03
ISSUE F

-jGi-

I~~~
PLANE

G
J

1$1 0.25(0.010)@lrl B ® 1A®I

Motorola Master Selection Guide

K
M
P
R

3.1-55

INCHES
MIN
MAX
0.715 0.770
0.240 0.260
0.145 0.185
0.015 0.021
0.040 0.070
O.l00SSC
0.082 0.095
0.008 0.015
0.115 0.135
0.300 SSC
0°
10°
0.Q15 0.039

MILLIMETERS
MIN
MAX
18.16 19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.82 BSC
0°
10°
1.01
0.39

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE 0 DIMENSION AT
MAXIMUM MATERIAL CONDITION
DIM
A
B
C
D
F

c

MILLIMETERS
MIN
MAX
19.05 19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54BSC
0.21
0.38
3.18
4.31
7.82BSC
0°
15°
0.51
1.01

NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL
DIM
A

K

INCHES
MIN
MAX
0.750 0.785
0.245 0.2BO
0.155 0.200
0.Q15 0.020
0.055 0.065
0.100 BSC
0.008 0.Q15
0.125 0.170
0.300 BSC
0°
15°
0.020 0.040

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
127BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 om
0.014 0.019
0.016 0.049
0.050 SSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.Q19

Logic: Standard. Special and Programmable

. 14-Pln Packages
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965-01
ISSUE 0

DETAILP

~i]
-II-b

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOUD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE RARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (h) DOES NOT
INCLUOE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE O.OB (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND
ADJACENT LEAD TO BE 0.46 (O.OIB).
DIM
A
AI
b

VIEWP,

())I

c
D
E

A 1 - .....

e
H.
0.50
L.
M

1-$1 0.13 (0.005)@1

Q

Z

SDSUFFIX
PLASTIC SSOP PACKAGE
CASE 940A-Q3
ISSUE B

1r-

14X K REF
1-$1 0.12(0.005)@ITI u ®I v® 1

fIr"
l ----- I
L

PIN 1
IDENT

0.25 (0.010)

B

A~-L

DETAILE

I-v-I

SECTIONN-N

•

DIM
A
B
C
D

F
J
Jl
K
Kl
L
M

3,1-56

INCitES
MIN
MAX
0.081
0.002 o.oOB
0.014 0.020
0.007
0.011
0.390 0.413
0.201
0.215
0.050 BSC
0291
0.323
0.020 0.033
0.043
0.059
10°
0°
0.02B 0.035
0.056

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,19B2.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSIONIINTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13 (0.005)
TOTAL IN EXCESS OF K DIMENSION AT
MAXIMUM MATERIAL CONDITION. DAMBAR
INTRUSION SHALL NOT REDUCE DIMENSION K
BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -'1-/-.

G
H

Logic: Standard, Special and Programmable

MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
B.20
0.50
0.B5
1.10
1.50
0°
10°
0.70
0.90
1.42

MILLIMETERS
MIN
MAX
6.07
6.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
1.08
1.22
0.09
0.20
0.09
0.16
0.25
0.3B
0.25
0.33
7.65
7.90
BO
0°

INCHES
MIN
MAX
0.238 0249
0.205 0.212
0.06B 0.07B
0.002
O.OOB
0.024 0.037
O.026BSC
0.042 0.048
0.003 0.008
0.003 0.006
0.010 0.015
0.010 0.013
0.301
0.311
BO
0°

Motorola Master Selection Guide

14-Pin Packages
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G-Q1
ISSUE 0
14X K REF

:J:Bl

PIN1
IDENT.

DETAILE

L; }jf
J J1

r

--SECTION N-N

•

NOTES:
1. DIMENSIONING ANDTOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAM BAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DIM
A
B
C
D
F
G
H

J
Jl
K
Kl
L
M

MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
120
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 SSC
0'
8'

INCHES
MIN
MAX
0.193
0.200
0.169
0.177
0.047
0.002
0.006
0.020
0.030
0.026BSC
0.020
0.024
0.004 0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0'
8'

16-Pin Packages
L,J SUFFIX
CERAMIC DIP PACKAGE
CASE 620-10
ISSUE V

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

I'S

/1

1/

fjUL

M

J 16 PL
""I
$-'TI""0.2"-5(-0.0-10--:)@"'"'Ir-Tr-IB--:®=:-'
S 11

1$10.25(0.010)@ITIA ®I

Motorola Master Selection Guide

3.1-57

DIM
A
B
C
D
E
F
G
H
K
L
M
N

INCHES
MIN
MAX
0.750 0.785
0.240
0295
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
15'
0'
0.020
0.040

MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
5.08
0.39
0.50
1.27BSC
1.40
1.65
2.54BSC
0.21
0.38
3.18
4.31
7.62 SSC
15'
0'
0.51
1.01

Logic: Standard, Special and Programmable

16-Pin Packages

P,N SUFFIX
PLASTIC DIP PACKAGE
CASE 648-08
ISSUE R

-

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
D
F
G
H
J
K

L
M
S

INCHES
MIN
MAX
0.740 0.770
0.250 0.270
.7
0.015
0.021
0.040
0.70
0.100 BSC
0.050BSC
0.Q15
0.008
0.110
0.130
0.295 0.305
0°
10°
0.020 0.040

MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
4.44
0.39
0.53
1.02
1.77
2.54 SSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0°
10°
0.51
1.01

o

SUFFIX
PLASTIC SOIC PACKAGE
CASE 7518-05
ISSUEJ
~---ll±ll---~
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

L±l S~~~~

DIM
A
B
C
D
F

~O
~OD
-j-L- - - -D~Pc
-TT
D 0

G
J
K
M

o 16PL

P

1-EI7IO.25(O.010)@ITIB®IA®1

Logic: Standard, Special and Programmable

R

3.1-58

MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27BSC
0.19
0.25
0.10
0.25
7'
0'
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.229
0.244
0.010
0.019

Motorola Master Selection Guide

16-Pin Packages
DWSUFFIX
PLASTIC WIDE SOIC PACKAGE
CASE 751G-02
ISSUE A

NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.SM,1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIM ENS 10M 0 DOES NOT INCLUDE DAM BAR
PROTRUSION. ALLOWABLE DAM BAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF 0 DIMENSION AT MAXIMUM
MATERIAL CONDITION.

DIM
A
B
C
D
F

G
J
K
M

P
R

MILLIMETERS
MIN
MAX
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.278SC
0.25
0.32
0.10
0.25
0°
7°
10.05
10.55
0.25
0.75
10.15

INCHES
MIN
MAX
0,411
0.400
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050BSC
0.010
0.012
0.004
0.009
7°
0°
0.395
0.415
0.010
0.029

M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 966-01
ISSUE a
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS 0 AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND
ADJACENT LEAD TO BE 0 46 ( 0 018)

DETAIL P

~r-

VIEWP~

fimt#ml~
-II-b
A

A1

?-,

(JI):

----

c

ll~
T

DIM
A
A

b

c
D
E

e

1$1 0.13(0.005)@ 1

HE
L
L<
M

a

Z

Motorola Master Selection Guide

3.1-59

MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27BSC
7.40
8.20
0.50
0.85
1.10
1.50
0°
10°
0.70
0.90
0.78

INCHES
MIN
MAX
0.081
0.002
0.008
0.020
0.014
0.007
0.011
0.390
0.413
0.201
0.215
0.050BSC
0.291
0.323
0.020
0.033
0.043
0.059
0°
10°
0.028
0.035
0.031

Logic: Standard, Special and Programmable

16-Pin Packages
SO SUFFIX
PLASTIC SSOP PACKAGE
CASE 9408-03
ISSUE B

1 t-I

16X K REF

1$10.12 (0.005)(01 TI u ® I v ® I

0.25(0.010)

L
PIN1
IDENT

DETAIL E

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI YI4.5M. 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.15 (0.006) PER SIDE.
5. DIMENSION K ODES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAM BAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K
DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR
INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE
THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM
PLANE -W-.

DIM
A
B
C

SECTION N-N

JJ E =s-~
II/ \00
DETAILE~"""

0
F
G
H
J
J1
K
KI
L
M

OTSUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F-01
ISSUE 0
,----,-------,---,----=0

I

INCHES
MIN
MAX
0.238
0.249
0.205
0.212
0.068
0.078
0.002
0.008
0.024
0.037
0.026BSC
0.028
0.035
0.003
0.008
0.003
0.006
0.010
0.015
0.010
0.013
0.301
0.311
0'
8'

,.~

16X KREF

j1$1 0.10(0.004)(0I TI u ®I v®1

1

i=-G"7"7"i1

B

I±I
PIN 1
IDENT.

MILLIMETERS
MIN
MAX
6.07
6.33
5.20
5.38
1.73
1.99
0.21
0.05
0.63
0.95
0.65 BSC
0.73
0.90
0.20
0.09
0.09
0.16
0.25
0.38
0.33
0.25
7.65
7.90
0'
8'

~~J

,---,--------,-~~ ~
A

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M.1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAM BAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7 DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.

DIM
A
B
C

[±]

D
F

G
H
J
J1
K
KI
L
M

Logic: Standard, Special and Programmable

3.1-60

MILLIMETERS
MIN
MAX
4.90
5.10
4.50
4.30
1.20
0.15
0.05
0.50
0.75
0.65 SSC
0.18
0.28
0.09
0.20
0.09
0.16
0.30
0.19
0.19
0.25
6.40 BSC
8'
0'

INCHES
MIN
MAX
0.193
0.200
0.169
0.177
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0'
8'

Motorola Master Selection Guide

18-Pin Packages
L,J SUFFIX
CERAMIC DIP PACKAGE
CASE 726-04
ISSUE G

I-

EB

-I

[:::::]~

OPTIONAL LEAD
CONFIGURATION (I, 9,10,18)

DIM
A
B
C
D
F
G

~~~"
~
jt
-------a

SEATING
PLANE

F

D 18:L

J

T

'I$:-iI=--O.:":'25:"'::(O'-.01-0)--=®"I-'TIr-A--:®~I

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1,
9, 10,AND 18.

1$lo.25(O.010)®ITI B ®I

K
L
M
N

INCHES
MIN
MAX
0.880
0.910
0240 0.295
0.200
0.015
0.021
0.055 0.070
0.100 BSC
0.012
0.008
0.125
0.170
0.300 BSC
IS"
0"
0.020
0.040

MILLIMETERS
MIN
MAX
22.35
23.11
6.10
7.49
5.08
0.38
0.53
1.40
1.78
2.54BSC
0.20
0.30
3.18
4.32
7.82 BSC
IS"
0"
0.51
1.02

P,N SUFFIX
PLASTIC DIP PACKAGE
CASE707-Q2
ISSUEC

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

f~ ::::::::IJ
I-

A

-I

DIM
A
B
C

D
F
G
H

J
K
L
M
N

Motorola Master Selection Guide

3.1-61

MILUMETERS
MIN
MAX
22.22 23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54 SSC
1.02
1.52
0.20
0.30
2.92
3.43
7.82 BSC
IS"
0"
0.51
1.02

INCHES
MAX
MIN
0.875 0.915
0.240 0.260
0.140 0.160
0.014 0.022
0.050 0.070
0.100 BSC
0.040 0.060
0.008 0.012
0.115
0.135
0.300 BSC
IS"
0"
0.020 0.040

Logic: Standard, Special and Programmable

2D-Pin Packages
L,J SUFFIX
CERAMIC DIP PACKAGE
CASE 732-03
ISSUE E

DIM
A
B
C
0
F
G
H

c

I~~)::
:
:~):t,~
UIPIII
I~'7: '

H- t--ll-D

-

NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER. TRUE
POSITION AT SEATING PLANE. AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEl.
3. DIMENSIONS A AND B INCLUDE MENISCUS.

-IG~ K

J
K
L
M
N

SEATING
PLANE

MILLIMETERS
MIN
MAX
23.88
25.15
6.60
7.49
3.81
5.08
0.38
0.56
1.40
1.65
2.54 BSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62 BSC
15°
0°
0.25
1.02

INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.Q15 0.022
0.055 0.065
0.100BSC
0.020 0.050
0.008 0.012
0.125 0.160
0.300 BSC
0°
15°
0.Q10 0.040

-

P,N SUFFIX
PLASTICC DIP PACKAGE
CASE 738-03
ISSUE E

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSIY14.5M,1962.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEl.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
DIM
A
B
C
0
E
G

J
K

L
M
N

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 7510-04
ISSUE E

-11-1r-:$-rlo-.O-10-(O-.2S--:)®=I-Tr-1A--:®=-Sr-IB--;®"'I
20X

D

DIM
A
B
C
0
F
G

J

3.1--62

MILLIMETERS
MIN
MAX
25.66 27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27BSC
1.27
177
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
15°
0°
0.51
1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006)
PER SIDE.
5. DIMENSION 0 DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF 0 DIMENSION
AT MAXIMUM MATERIAL CONDITION.

K
M
P
R

Logic: Standard. Special and Programmable

INCHES
MAX
MIN
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
O.osa BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
15°
0°
0.020 0.040

MILLIMETERS
MIN
MAX
12.65 12.95
7.40
7.60
2.35
2.65
0.35
0.49
O.sa
0.90
1.27BSC
0.25
0.32
0.10
0.25
0°
7°
10.05 10.55
0.25
0.75

INCHES
MIN
MAX
0.499 0.510
0292 0.299
0.093 0.104
0.014 0.Q19
0.020 0.035
O.osa BSC
0.010 0.012
0.004 0.009
0°
7°
0.395 0.415
0.010 0.029

Motorola Master Selection Guide

2o-Pin Packages
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967-01
ISSUE 0

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY,

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAM BAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAM BAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND
ADJACENT LEAD TO BE 0 46 (0018)

DETAILP

DIM
A
A,
b

VIEWP---...

;>-,

c

(;1) :

--

0.13(0.005)@

D
E

•

H.
L
L.
M
Q

Z

SO SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C-03
ISSUE B

DETAILE

Lr-K---J~

W//4

T~K1-1 t

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTER LEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13 (0.005)
TOTAL IN EXCESS OF K DIMENSION AT
MAXIMUM MATERIAL CONDITION. DAMBAR
INTRUSION SHALL NOT REDUCE DIMENSION K
BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.

J1
DIM
A
B

SECTIONN-N

C
D
F
G
H

J
J1
K
K1
L
M

Motorola Master Selection Guide

3.1-63

INCHES
MIN
MAX
0.081
0.002 0.008
0.014 0.020
0.007
0.011
0.486 0.504
0.201
0.215
0.050 SSC
0.291
0.323
0.020
0.033
0.043
0.059
0"
10"
0.028
0.035
0.032

•

0.25 (0.010)

J

MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35 12.80
5.10
5.45
1.27BSC
7.40
8.20
0.50
0.85
1.10
1.50
0"
10"
0.70
0.90
0.81

MILLIMETERS
MIN
MAX
7.07
7.33
5.20
5.38
1.99
1.73
0.05
021
0.63
0.95
0.65BSC
0.59
0.75
0.09
020
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0"
8"

INCHES
MIN
MAX
0.278 0.288
0.205 0.212
0.068 O.D7B
O.OOB
0.002
0.024
0.037
0.026 BSC
0.023
0.030
0.003
0.008
0.003
0.006
0.015
0.010
0.010
0.013
0.301
0.311
0"
8"

Logic: Standard, Special and Programmable

20-Pin Packages
OTSUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E-02
ISSUE A

SECTION N-N

DETAILE

•

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14,5M,1982,
2, CONTROLLING DIMENSION: MILLIMETER,
3, DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS, MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0,15 (0,006) PER SIDE,
4, DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION, INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0,25
(0,010) PER SIDE,
5, DIMENSION K DOES NOT INCLUDE DAM BAR
PROTRUSION, ALLOWABLE DAM BAR
PROTRUSION SHALL BE 0,08 (0,003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION,
6, TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY,
7, DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-,
DIM
A
B
e
0
F
G

H
J
J1

K
K1
L
M

Logic: Standard, Special and Programmable

3.1-64

MILliMETERS
MIN
MAX
6,60
6.40
4,30
4,50
1.20
0,15
0,05
0,50
0,75
0,65 Bse
0,27
0,37
0,09
0,20
0,09
0,16
0,19
0,30
0,19
0,25
6,40 Bse
0°
8°

INCHES
MIN
MAX
0,252 0,260
0,169 0,177
0,047
0,002 0,006
0,020 0,030
0,026BSC
0,011
0.Q15
0,004 0,008
0,004 0,006
0,007 0,012
0,007 0,010
0,252 BSC
0°
8°

Motorola Master Selection Guide

20-Pin Packages
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775--02
ISSUE C

81$1 O.007(O.180)@ITI L-M® 1N®I
u 1$1 O.007(O.180)@ITI L-M®I N®I

G11$1 O.OI0(O.250)®ITI L-M®I N®I
VIEWD-D

I+----+t---AI$I O.007(O.180)@ITIL-M®IN®1

~-----rt-R 1$1 O.007(O.180)@ITI L-M®I N®I

+
~

HI$lo.007(O.180)@ITIL-M®IN®1

K1

K

~ I- F 1$1 O.007(O.180)@ITI L-M®I N®I
VIEWS

•
Motorola Master Selection Guide

NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS RAND U 00 NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0,010
(0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
5. CONTROLLING DiMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAM BAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).

3.1-65

DIM
A
B
C
E
F
G
H

J
K

R
U
V
W
X
Y

Z
G1
K1

INCHES
MIN
MAX
0.385 0.395
0.385 0.395
0.165
0.180
0.090 0.110
0.013 0.019
0.050BSC
0.02
0.032
0.020
0.025
0.350 0.356
0.350 0.356
0.042 0.048
0.042 0.048
0.042 0.056
0.020
10°
2°
0.310 0.330
0.040

MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27BSC
0.66
0.81
0.51
0.84
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
7.88
8.38
1.02

Logic: Standard, Special and Programmable

22-Pin Packages
J SUFFIX
CERAMIC DIP PACKAGE
CASE 736-05
ISSUE E

~------~-A-r-------~

~

OPTIONAL
LEAD
CONFIGURATION

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,1982.
2. CONTROlLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL
4. DIMENSION F FOR FULL LEADS. HALF LEADS
OPTIONAL AT LEAD POSITIONS " 1" 12, AND 22.
5. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

Dill
A

B

C
D

F
G
J
K
L
M
N

INCHES
IIIN
MAX

IILLIMETERS
IIIN
MAX

1.060 1.095
0.360 0.390
0.150 0.215
0.15 0.021
0.050 0.065
0.100 esc
0.008 0.015
0.125 0.170
0.400 BSC
O'
15'
0.20 0.050

2693 27.81
9.15
9.90
3.81
5.46
0.39
0.53
1.27
1.65
2.54BSC
020
0.39
3.18
4.31
10.16SSC
O'
15'
0.51
127

N SUFFIX
PLASTIC DIP PACKAGE

CASE 708-04
ISSUE D

f::::::::::: IJ

NOTES:
1. PDSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MeLD
FLASH.

Dill

iLl
,

,

fl
Logic: Standard. Special and Programmable

3.1-66

A
B
C

D

F
G
H

J
K
L
II
N

MILLIMETERS
IIIN
MAX
27.56 28.32
9.14
8.64
3.94
5.08
0.6
0.56
1.76
1.27
2.54BSC
1.02
1.52
0.20
0.38
2.82
3.43
10.16BSC
O'
IS'
0.51

INCHES

MIN

MAX

1.085 1.115
0.340 0.360
0.155 0.200
0.014 0.022
0.050 0.070
0.100BSC
0.040 0.060
0.008 0.D15
0.115 0.135
0.400BSC
O'
15°
0.020 0.040

Motorola Master Selection Guide

24-Pin Packages
J SUFFIX
CERAMIC DIP PACKAGE
CASE 758-02
ISSUE A

NOTES:
1, DIMENSIONING AND TOLERANCING PER ANSI
YI4,5M,1982,
2, CONTROLLING DIMENSION: INCH,
3, DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEl.
DIM
A
B
C
D
F
G

J
K
L
N
P

INCHES
MIN
MAX
1.240
1,285
0,285
0,305
0,160
0,200
0,015
0,021
0,045
0,062
0,100BSC
0,008
0,013
0,100
0,185
0,300
0,310
0,020
0,050
0,360
0,400

MILLIMETERS
MIN
MAX
32,64
31,50
7,24
7,75
5,08
4,07
0,53
0,38
1,14
1,57
2,64 BSC
0,20
0,33
2,54
4,19
7,62
7,87
0,51
1,27
9,14
10,16

L,J,JW SUFFIX
CERAMIC DIP PACKAGE
CASE 623-{)5
ISSUE M

13

1

NOTES:
1, DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEl.
2, LEADS WITHIN 0,13 (0,005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL),

B

~nrnnnnnnnn""TTTTTTrI2~~
A -----+1.1

DIM
A
B
C
D
F
G

J
K
L
N

Motorola Master Selection Guide

3.1-67

MILLIMETERS
MIN
MAX
31,24
32,77
12.70
15,49
4,06
5,59
0,41
0,51
1.27
1,52
2,64BSC
0,20
0,30
3,18
4,06
15,24BSC
0,51

1,27

INCHES
MIN
MAX
1,230
1.290
0,500
0,610
0,160
0,220
0,016
0,020
0,050
0,060
0,100BSC
0,008
0,012
0,125
0,160
0,600 BSC

0°

15°

0,020

0,050

Logic: Standard, Special and Programmable

24-Pln Packages
N SUFFIX
PLASTIC DIP PACKAGE
CASE 709-02
ISSUE C

DIM
A
B

c

C
D
F
G
H

J

H

I"

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

K
L
M
N

lJ

[±]

NOTES:
1. CHAMFERED CONTOUR OPTIONAL.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,1982.
4. CONTROLLING DIMENSION: INCH.

~c JLJ~-,
. j '~M
1$-1 O.25(O.010)@iTi B @I

o 24PL

1$-1 o.25(o.010)@ITI A @I
P,N,PW SUFFIX
PLASTIC DIP PACKAGE
CASE 649-03
ISSUE D

DIM
A

B
C
D
E
F

G
J
K
L
M
N

DIM
A
B

C
0
F
G
H

c

J
K
L
M
N

P
Q

3.1-68

INCHES
MIN
MAX
1.230 1.265
0.250 0.270
0.145 0.175
0.015 0.020
0.050 BSC
0.040 0.050
0.100 BSC
0.007 0.012
0.110 0.140
0.300 BSC
0°
15°
0.020 0.040

MILUMETERS
MIN
MAX
31.25
32.13
6.35
6.85
3.69
4.44
0.38
0.51
1.27BSC
1.02
1.52
2.54 BSC
0.18
0.30
2.80
3.55
7.62 BSC
0°
15°
0.51
1.01

NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

Q

Logic: Standard, Special and Programmable

INCHES
MIN
MAX
1.235 1.265
0.540 0.550
0.155 0.200
0.014 0.022
0.040 0.050
O.I00BSG
0.065 0.080
0.008 0.015
0.115
0.135
0.600BSG
0°
15°
0.020 0.040

P,N SUFFIX
PLASTIC DIP PACKAGE
CASE 724-03
ISSUE D

1~:::::::::::loo
t

p

MlLUMETERS
MAX
MIN
31.37 32.13
13.72 14.22
5.08
3.94
0.36
0.56
1.02
1.52
2.54BSG
1.65
2.03
0.38
0.20
2.92
3.43
15.24 BSC
0°
15°
0.51
1.02

MILLIMETERS
MIN
MAX
31.50
32.13
13.21
13.72
4.70
5.21
0.38
0.51
1.52
1.02
2.54BSC
1.65
2.16
0.20
0.30
2.92
3.43
14.99 15.49
10
0.51
1.02
0.13
0.38
0.51
0.76

INCHES
MAX
MIN
1.240 1.265
0.520 0.540
0.185 0.205
0.015 0.020
0.040 0.080
0.100BSG
0.065 0.085
0.008 0.012
0.115
0.135
0.590 0.610
10°
0.020 0.040
0.005 0.015
0.020 0.030

Motorola Master Selection Guide

24-Pin Packages
OW SUFFIX
PLASTIC WIDE SOIC PACKAGE
CASE 7S1E-04
ISSUE E

JL

24X

NOTES:
1. OIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0,15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

0

r:1$"1"'=0.""'01"""0("""0.2:-: :5)-;:®: T1::1TI--:-A--;®""'IB--;®~I

DIM
A
B
C
D
F
G
J
K
M

=-~~
l
T::

SEATING
PLANE

I
-.J

22X

G

P

K

R

MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27BSC
0.23
0.32
0.13
0.29
0'
8'
10.05
10.55
0.25
0.75

SO SUFFIX
PLASTIC SSOP PACKAGE
CASE 940D-03
ISSUE B

1 1-I

TT"':
1
L

~

l

PINl
IDENT

Y14.5M,1982.

L

13

r- K--J~

I B T l -W/4
t
J

J1

K1-J

~12~

+---1rU

A~

L-.l...-0-'---'----'---J[±]'------'V-

b

SECTIONN-N

0.25(0.010)

N~~
DETAILE

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAM BAR
PROTRUSION/INTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13 (0.005)
TOTAL IN EXCESS OF K DIMENSION AT
MAXIMUM MATERIAL CONDITION. DAMBAR
INTRUSION SHALL NOT REDUCE DIMENSION K
BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DIM
A
B
C
D
F
G
H
J
Jl

K
Kl
L
M

Motorola Master Selection Guide

•

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI

24X KREF

1$10.12(0.005)®ITlu®lv®1

1124

INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.019
0.014
0.016
0.035
O.osa BSC
0.009
0.013
0.005
0.011
0'
8'
0.395
0.415
0.010
0.029

3,1-69

MILLIMETERS
MIN
MAX
8.07
8.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
0.44
0.60
0.09
0.20
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0'
8'

INCHES
MIN
MAX
0,317 0.328
0.205
0.212
0.068 0.D78
0,002 0.008
0.024 0.037
0.026 BSC
0,017 0.024
0.003 0.008
0.003 0.006
0.010 0.015
0.010 0.013
0.311
0.301
0'
8'

Logic: Standard, Special and Programmable

24-Pin Packages
DTSUFFIX
PLASTIC TSSOP PACKAGE
CASE 948H-Q1
ISSUE 0

•

24XKREF

--Ir--le-I 0.10(0.004)@ITlu ®lv®1
~~~--~~~~~-,-----

1

B

8B

1bfr=r;=rr=;=;=;=;=;=;="i"Fi"F'FF~J
.1

ri·
-T-

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25(0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DIM
A
8
e
D
F
G
H
J
J1
K
K1
L
rot

10 (0.004) I
SEAllNG
PLANE

~I

(t:)

DETAIL

E..-/~

MILUMETERS
MIN
MAX
7.70
7.90
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40BSC
0°
8°

INCHES
MIN
MAX
0.303
0.311
0.169 o.m
0.047
0.002 0.006
0.020 0.030
0.026Bse
0.011
0.015
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 Bse
0°
8°

'N~~ '~:~ 1
DETAILE

logic: Standard, Special and Programmable

3.1-70

- ,

Motorola Master Selection Guide

28-Pin Packages
J SUFFIX
CERAMIC DIP PACKAGE
CASE 733-04
ISSUE C

NOTES:
1. DIMENSIONS A AND S INCLUDES MENISCUS.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4. C0tffi10LLING DIMENSION: INCH.

I"

[±]

~I

ruM
A
B
C
D
F

c

;;!;.;."l~L
S
-J l!J
PLANE

~

f-G

G
J
K
L
M
N

D2:PL

INCHES
MIN
MAX
1.490
1.435
0.500
0.605
0.160
0.230
0.015
0.022
0.065
0.050
0.100BSC
0.008
0.012
0.125
0.160
0.600BSC
15°
0°
0.020
0.050

MILLIMETERS
MAX
MIN
37.84
36.45
12.70
15.36
4.06
5.84
0.38
0.55
1.65
1.27
2.54BSC
0.20
0.30
3.18
4.06
15.24 SSC
15°
0°
0.51
1.27

1$10 o.25(o.o10)®ITI A ®I
N SUFFIX
PLASTIC DIP PACKAGE
CASE 710-02
ISSUE B

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
DIM
A
B
C
D
F

G
H

J
K
L
M
N

Motorola Master Selection Guide

3.1-71

MILUMETERS
MAX
MIN
37.21
36.45
13.72
14.22
3.94
5.08
0.56
0.36
1.02
1.52
2.54BSC
2.16
1.65
0.20
0.38
2.92
3.43
15.24BSC
0°
15°
0.51
1.02

INCHES
MAX
MIN
1.465
1.435
0.540
0.560
0.200
0.155
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.135
0.115
0.600 BSC
0°
15°
0.040
0.020

Logic: Standard, Special and Programmable

28-Pin Packages
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776-
<>

e<>

-l.-,~o-, -'H

ci
'"

-$- ----!

-$-

DETAIL A

t

C

+
L±l
SEATING

SECTIONB-B
VIEW ROTATED 90 ° CLOCKWISE

PLANE

DETAILC

Motorola Master Selection Guide

NOTES:
1. DIMENSIONING AND TOlERANCING PER ANSI
Y14.5M,1982.
2, CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H-IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -8- AND -0- TO BE DETERMINED
AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE-C-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0,25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOlD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAM BAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.

3.1-73

DIM

A
B
C
0
E
F

G
H

J
K
L
M
N
P
Q

R
S
T
U
V
X

MILLIMETERS
MIN
MAX
6.95
7.10
6.95
7.10
1.40
1.60
0.273 0.373
1.30
1.50
0.273
0.80BSC
0.20
0.119
0.197
0.33
0.57
5.6 REF
6°
8°
0.119
0.135
0.40 Bse
10°
5°
0.15
0.25
8.85
9.15
0.15
0.25
jjO
5°
8.85
9.15
1.00 REF

INCHES
MIN
MAX
0.274 0.280
0.274 0.280
0.055 0.063
0.010 0.015
0.051
0.059
0.010
0.031 Bse
0.008
O.OOS 0.008
0.013 0.022
0.220 REF
8°
6°
0.005 0.005
0.016Bse
10°
5°
0.006
0.010
0.348 0.360
0.006 0.010
11°
5°
0.348 0.360
0.039 REF

Logic: Standard, Special and Programmable

40-Pin Packages

J SUFFIX
CERAMIC DIP PACKAGE
CASE 734-04
ISSUE D

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5.1973.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND 8 INCLUDE MENISCUS.
4. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
DIM
A
B
C
0
F

G
J
K
L
M

N

MILLIMETERS
MIN
MAX
51.31
53.24
12.70 15.49
4.06
5.84
0.38
0.56
127
1.65
2.54BSC
0.20
0.30
3.18
4.06
15.24 BSC
15°
5°
0.51
1.27

INCHES
MIN
MAX
2.020
2.096
0.500 0.610
0.160 0.230
0,015 0.022
0.050 0.065
0.100BSC
0.008
0.012
0.125 0.160
0.600BSC
15°
5°
0.020 0.050

1$10 o.25(o.o10)®ITI A ® 1
N SUFFIX
PLASTIC DIP PACKAGE
CASE 711-03
ISSUEC

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D). SHALL
BE WrTHlN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION. IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

DIM
A
B
C
0
F
G
H

J
K
L
M
N

Logic: Standard, Special and Programmable

3.1-74

MILLIMETERS
MIN
MAX
51.69 52.45
13.72 14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54BSC
1.65
2.16
0.20
0.38
2.2
3.43
15.24BSC
0°
15°
0.51
1.02

INCHES
MIN
MAX
2.035 2.065
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.015
.11
0.135
0.600BSC
0°
15°
0.020 0.040

Motorola Master Selection Guide

48-Pin Packages
J SUFFIX
CERAMIC DIP PACKAGE
CASE 74Q-03
ISSUE B

I-

[±]

"I

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL

I~: : : :1::I:::::IT

DIM
A
B
C
D
E
F
G
J
K
L
M
N

INCHES
MIN
MAX
2.376
2.424
0.576
0.604
0.120
0.127
0.Q15
0.021
0.050 BSC
0.030
0.055
0.100BSC
0.008
0.Q13
0.100
0.165
0.600 BSC
10°
0°
0.040
0.060

MILLIMETERS
MIN
MAX
60.36 61.56
14.64 15.34
4.31
3.05
0.381
0.533
1.27BSC
0.762
1.397
2.54 BSC
0.204 0.330
4.19
2.54
15.24BSC
10°
0°
1.016 1.524

N SUFFIX
PLASTIC DIP PACKAGE
CASE 767--02
ISSUE B

t::::::::::::::::::J +

DETAIL X

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARAlLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).

DIM
A
B

C
D
F

G
H

J

o 32PL
1$10.51 (0.020)@ITI A ® 1

Motorola Master Selection Guide

1$10.25(0.010)@ITIB ®I

3.1-75

K
L
M
N

INCHES
MIN
MAX
2.415 2.445
0.540 0.560
0.155
0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.070 BSC
0.008
0.Q15
0.115
0.150
0.600 BSC
15°
0°
n.n2n
.040

MILLIMETERS
MIN
MAX
61.34 62.10
13.72
14.22
3.94
5.08
0.36
0.55
1.02
1.52
2.54BSC
1.79BSC
0.20
0.38
3.81
2.92
15.24 BSC
15°
0°
1.01
0.51

Logic: Standard, Special and Programmable

52-Pin Packages
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 77B--_Q
''' ....,
~G f
_d~t

FiR

4xe3

PLANE

VIEWAA

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H-IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE BOTTOM OF THE
PARTING LINE.
4. DATUMS-L-,-M-AND-N- TO BE DETERMINED AT
DATUM PLANE-I+-.
5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING
PLANE-T-.
6. DIMENSIONS A AND B 00 NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010)
PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM PLANE ·H·.
7. DIMENSION 0 DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018).
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTRUSION 0.07 (0.003).
MIL

ERS

DIll
A1
B
B1

5.00
).00
5.00
0.05

0.394
0.19:
1.70
0.20

0,20
0.75
0.46
0.22
0.35
0.65BSC
0.07
0.20
0.50 REF

VIEWAA

Logic: Standard, Special and Programmable

•
3.1-78

12.Il!tBSC
6.00BSC
).16
0.09
12.00 BSC
tOOBSC

93

INCI
I

12' REF
13'

0.002

0.06i
0.' 08

0.018

O. GO

).009
0.02 BS'
0.003
0.008
0.020 REF

0.236BSC
0.004 0.008
0.472 BSC
.23IBSC

12' REF
13°

Motorola Master Selection Guide

68-Pin Package
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 779-02
ISSUE C

81$1 0.007(0.18)®ITI L-M® 1N®I
ul$1 0.007(0.18)@ITIL-M®IN®1

YBRK

D

G1

D
VIEWD-D

z,....

1
c"

$10.007(0.18)®ITIL-M®IN®1

o

I.

;:n:-- 'i t' lii1.
J

G1----..{

-T-

004 (0.10) 1
SEATING
PLANE

VIEWS

NOTES:
1. DATUMS -l-. -M-, AND -N- DETERMINED WHERE TOP OF
lEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
2. DIMENSION Gl, TRUE POSITION TO BE MEASURED AT
DATUM - T-, SEATING PLANE.
3. DIMENSIONS RAND U DO NOT INCLUDE MOLD FLASH.
AllOWASlE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOlERANCING PER ANSI Y14.5M,
1982.
5. CONTROlliNG DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMAllER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
RAND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH. TIE BAR BURRS, GATE BURRS AND INTERlEAD
FlASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHAll NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHAll NOT CAUSE THE H DIMENSION TO
BE SMAllER THAN a025 (0 635)

0111
A
B
C
E
F
G
H

J
K
R
U
V

W

I-FI$I 0.007(0.18)@ITIL-M®IN®1

X
Y
Z
Gl
Kl

VIEWS

Motorola Master Selection Guide

3.1-79

1$1 0.010 (0.25)®1 TI L-M®I N®I

INCHES
IIIN
MAX
0.995
0.985
0.985 0.995
0.165 0.180
0.090 0.110
0.013
0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.950 0.956
0.950 0.956
0.042 0.048
0.042 0.048
0.042 0.056
0.020
10°
2°
0.910
0.930
0.040

MilliMETERS
MAX
MIN
25.02 25.27
25.02 25.27
4.20
4.57
2.29
2.79
0.33
0048
1.27BSC
0.66
0.81
0.51
0.64
24.13
24.28
24.13
24.28
1.07
1.21
1.07
1.21
1.42
1.07
0.50
10°
2°
23.12 23.62
1.02

Logic: Standard. Special and Programmable

Programmable Array
84-Pin Package
Figure 18. FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 780-01
ISSUE A

BI*I 0.007(0.18)@lrIL-M®IN®1
ul*l 0.007(0.18)@ITIL-M®IN®1

D

Tt
D

X

G1

1$10.010(0.25)®lrIL-M®IN®1
VIEWD-D

A

1$10.007 (0.18)@lrl L-M®I N®I
R

H

1$1 0.007(0.18)@lrIL-M®IN®1

VIEWS

1*1 0.007(0.18)@ITI L-M®I N®I
K1

[1Jo.o04 (0.10) 1
G1

1*1 0.010 (0.25)®1 TI L-M®I N®I

Logic: Standard, Special and Programmable

T

VIEWS

SEATING
PUNE

NOTES:
1. DATUMS -L-. -M-. -N-. AND-PDETERMINED WHERE TOP OF LEAD
SHOULDER EXITS PACKAGE BODY AT MOLD
PARTING UNE.
2. DIMENSION Gl. TRUE POSITION TO BE
MEASURED AT DATUM -T-. SEATING PLANE.
3. DIMENSIONS RAND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M. 1982.
5. CONTROLUNG DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
10.300). DIMENSIONS RAND UARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BOOY
EXCLUSIVE OF MOLD FLASH. TIE BAR
BURRS. GATE BURRS AND INTERLEAD
FLASH. BUT INCWDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INlRUSION. THE DAMSAR
PROTRUSION(5) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.94). THE DAMBAR INTRUSIONIS) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).

3.1-80

l!l!M
A
B

C

INCHES
MAX

r.!!li

1.185
.185
.16

R
U

.1
.11
0.013 0,019
0.050BSC
0.026 0.032
0.020
0.025
1.1
1.1
1.1
1.1

-.lL

.048

E
F

G
H

W
X
Y
Z
Gl
Kl

~

MiLLIMETERS
MIN
MAX

30~5
1~ LaO.l0
1~ ~ ~

~

~

0.042

0.056

2·
1.110
0.040

1•
1.13

4.20

4.7
2.29
2.79
0.33
0.48
1.27BS

-'l.BIl_
0.51
0.64
1
1
1.07
107
1.07
2·
2
1.02

J.81
2.
1.21
1.21
1.42
0.50
1•
7

Motorola Master Selection Guide

Programmable Array
128-Pin Package
Figure 19. DO SUFFIX
PLASTIC QFP PACKAGE
CASE 862A-02
ISSUE B

@

'"

@
----i-i;<)-j-iro.t
Toggle

'1%

Output 4
H-o-+-O_2.5 V/t.O rnA
Output 1
~-O-"-°3.0 V/30 rnA
Output 2

~-O::!:"""°3.0 Vl60 rnA

~==~~~------~,""I

~------~--------------------~O
~----------------------------------~O

~--------------------------------~,""I

MPU

VSS

GaAs Amplifier Supervisory Circuit
MC33169DTB
TA = -40° to +85°C, Case 9488
The MC33169 is a support IC for GaAs
Power Amplifier Enhanced FETs used in
hand portable telephones such as GSM,
PCN, DECT. This,device provides negative
voltages for full depletion of Enhanced
MESFETs as well as a priority management
system of drain switching, ensuring thatthe
negative voltage is always present before
turning "on" the power amplifier. Additional
features include an idle mode input and a
direct drive of the N-Channel drain switch
transistor.
This product is available in two versions,
-2.5 V and -4.0 V. The -4.0 V version is
intended for supplying RF modules for
GSM and DCS1800 application whereas
the -2.5 V version is dedicated for DECT
and PHS systems.
• Negative Regulated Output for Full
Depletion of GaAs MESFETs
• Drain Switch Priority Management
Circuit
• CMOS Compatible Inputs
• Idle Mode Input (Standby Mode) for
Very Low Current Consumption
• Output Signal Directly Drives
N-ChannelFET
• Low Startup and Operating Current

Motorola Master Selection Guide

VBB Double

= VBattery
..L (2.7 to 7.0 V)

~------r---'-------,""

RF
Out

C1
~-----..J~~h

R1

4.2-7

'-L

Analog and Interface Integrated Circuits

SCSI Regulator
Table 5. SCSI Regulator
Vin
(V)

Vout
(V)
Device
MC34268

Min
2.81

I
I

Max

Isink
(mA)

Min

2.89

800

3.9

I
I

Regllne

Regload

Max

(%)

(%)

TJ
(Oe)

Suffix!
Package

20

0.3

0.5

150

D1751 , DT

SCSI-2 Active Terminator Regulator
MC34268D, Dr
TJ = 0° to +125°C, Case 751, 369A
The MC34268 is a medium current, low dropout positive
voltage regulator specifically designed for use in SCSI-2
active termination circuits. This device offers the circuit
designer an economical solution for precision voltage
regulation, while keeping power losses to a minimum. The
regulator consists of a 1.0 V dropout composite PNP/NPN
pass transistor, current limiting, and thermal limiting. These
devices are packaged in the 8-pin SOP-8 and 3-pin DPAK
surface mount power packages.
Applications include active SCSI-2 terminators and post
regulation of switching power supplies.

•
•
•
•
•
•
•
•

2.85 V Output Voltage for SCSI-2 Active Termination
1.0 V Dropout
Output Current in Excess of 800 mA
Thermal Protection
Short Circuit Protection
Output Trimmed to 1.4% Tolerance
No Minimum Load Required
Space Saving DPAK and SOP-8 Surface Mount Power
Packages

Input

Analog and Interface Integrated Circuits

4.2-8

Motorola Master Selection Guide

Switching Regulator Control Circuits
These devices contain the primary building blocks which
are required to implement a variety of switching power
supplies. The product offerings fall into three major categories
consisting of single--ended and double--ended controllers,
plus single--ended les with on-chip power switch transistors.
These circuits operate in voltage, current or resonant modes

and are designed to drive many of the standard switching
topologies. The single--ended configurations include buck,
boost, flyback and forward converters. The double--ended
devices control push-pull, half bridge and full bridge
configurations.

Table 6. Single-Ended Controllers
These single-ended voltage and current mode controllers are designed for use in buck, boost, flyback, and forward
converters. They are cost effective in applications that range from 0.1 to 200 W power output.
Minimum
Operating
Voltage
Range
(V)

Operating
Mode

500
(Uncommitted
Drive Oulpul)

7.01040

Vollage

1000
(Tolem Pole MOSFET
Drive Oulpul)

4.21012

10
(mA)
Max

Reference
(V)

Maximum
Useful
Oscillator
Frequency
(kHz)

Device

(OC)

Suffix!
Package

5.0± 1.5%

200

MC34060A

010+70

D/751 A

MC33060A

-4010+85

D/751 A

MC34129

010 +70

D/751 A

MC33129

-4010+85

D/751 A

UC3842A

010 +70

D/751 A

TA

P/646

P/646

Currenl

1.25±2.0%

300

P/646

P/646

11.51030

5.0±2.0%

111030

5.0± 1.0%

UC2842A

-2510+85

0/751 A

8.21030

5.0±2.0%

UC3843A

010 +70

0/751 A

5.0± 1.0%

UC2843A

-2510+85

0/751 A

UC3844

Oto+70

0/751 A

UC2844

-25 to +85

0/751 A

500

N/626

N/626

N/626

N/626

11.51030

5.0±2.0%

500
(50% Duty
Cvcle Limit)

11 to 30

5.0± 1.0%

8.2 to 30

5.0±2.0%

UC3845

oto +70

D/751 A

5.0± 1.0%

UC2845

-25 to +85

0/751 A

UC3842B

Oto+70

0/751 A

N/626

N/626

Nl626

N/626

11.5t030

Motorola Master Selection Guide

5.0 ± 2.0%

4.2-9

500
(Improved
Oscillator
Specifications
with
Frequency
Guaranteed
at 250 kHz)

01/751
Nl626
UC3842BV

-40 to +105

0/751 A
01/751
Nl626

Analog and Interface Integrated Circuits

Table 6. Single-Ended Controllers (continued)
These single-ended voltage and current mode controllers are designed for use in buck, boost, flyback, and forward
converters. They are cost effective in applications that range from O. t to 200 W power output.

10
(mA)
Max
1000
(Totem Pole MOSFET
Drive Output)

Minimum
Operating
Voltage
Range

(V)

Operating
Mode

Reference
(V)

11 to 30

Current

5.0± 1.0%

8.2 to 30

5.0±2.0%

Maximum
Useful
Oscillator
Frequency
(kHz)
500
(Improved
Oscillator
Specifications
with
Frequency
Guaranteed
at 250 kHz)

Device

TA
("C)

Suffix!
Package

UC2842B

-25 to +85

D/751 A
D1/751
N/626

UC3843B

Oto+70

D/751 A
D1/751
N/626

UC3843BV

--40 to +105

D/751 A
D1/751
N/626

5.0±1.0%

UC2843B

-25 to +85

D/751 A
D1/751
N/626

11.5t030

5.0 ± 2.0%

500
(50% Duty
Cycle Limit)

UC3844B

Oto+70

0/751 A
D1/751
N/626

UC3844BV

--40 to +105

D/751 A
D1/751
N/626

11 to 30

5.0± 1.0%

UC2844B

-25 to +85

D/751 A
D1/751
N/626

8.2 to 30

5.0±2.0%

UC3845B

010+70

D/751 A
D1/751
N/626

UC3845BV

--40 to +105

D/751 A
D1/751
N/626

5.0± 1.0%

UC2845B

-25 to +85

D/751 A
D1/751
Nl626

1000 Source
1500 Sink
(Split Totem Pole
Bipolar Drive Output)

11 to 18

2000
(Totem Pole MOSFET
Drive Output)

9.2 to 30

5.0±6.0%

Current
or
Voltage

5.1 ± 1.0%

MC44602

1000

MC34023

P2I648C

Oto+70

DW/751G
FN1775
P/648

MC33023

--4010 +105

DW1751G
FN/775
P/648

Analog and Interface Integrated Circuits

4.2-10

Motorola Masler Selection Guide

Table 7. Single-Ended Controllers with On-Chip Power Switch
These monolithic power switching regulators contain all the active functions required to implement standard dc-to--dc
converter configurations with a minimum number of external components.

10
(mA)
Max

1500
(Uncommitted
Power Swilch)

Minimum
Operating
Voltage
Range
(V)

Operating
Mode

2.51040

Vollage

Reference
(V)

Maximum
Useful
Oscillator
Frequency
(kHz)

Device

1.25 ± 5.2%(1)

100

IlA78S40

1.25±2.0%

(Oc)

Suffix!
Package

Oto+70

PC/648

-4010 +85

PV/648

TA

MC34063A

010 +70

Dn51
P1/626

MC33063A

-4010 +85

Dn51
P1/626

3400
(Uncommitted
Power Switch)

2.51040

3400(2)
(Dedicated Emitter
Power Swilch)

7.51040

1.25±2.0%
and
5.05±3.0%
5.05±2.0%

72± 12%
Internally
Fixed

5500(3)
(Dedicated Emitter
Power Swilch)

MC34163

010 +70

MC33163

-4010 +85

MC34166

Oto+70

MC33166

-4010+85

MC34167

010 +70

MC33167

-4010+85

P/648C,
DWn51G

D2T/936A,
TH,TV,
T/314D

(1) Tolerance applies over the specified operating temperature range.
(2) Guaranteed minimum. typically 4300 rnA.
(3) Guaranteed minimum, typically 6500 rnA.

Table 8. Very High Voltage Single-Ended Controller with On-Chip Power Switch
This monolithic high voltage switching regulator is specifically designed to operate from a rectified ac line voltage source.
Included are an on--chip high voltage power switch, active off-line startup circuitry and a full featured PWM controller with fault
protection.
Power Switch
Maximum Rating
VOS(V)

lOS (mA)

Startup
Input Max
(V)

500

2000

250

Motorola Master Selection Guide

Operating
Mode
Vollage

(V)

Maximum
Useful
OSCillator
Frequency
(kHz)

Device

TA
(OC)

Suffix!
Package

2.6±3.1%

1000

MC33362

-25 to +125

DWn51N

Feedback
Threshold

4.2-11

Analog and Interface Integrated Circuits

Table 9. Double-Ended Controllers
These double-ended voltage, current and resonant mode controllers are designed for use in push-pull, half-bridge, and
full-bridge converters. They are cost effective in applications that range from 100 to 2000 watts power output.

10
(mA)
Max
500
(Uncommitted
Drive Outputs)

±500
(Totem Pole MOSFET
Drive Outputs)

Minimum
Operating
Voltage
Range
(V)

Operating
Mode

7.0 to 40

Voltage

8.0 to 40

Device

5.0 ± 5.0%(1)

200

TL494

(OC)

Suffix!
Package

o to +70

CN/648

TA

5.0± 1.5%

300

TL594

5.1 ±2.0%

400

SG3525A

-25 to +85

IN/648

Oto+70

CN/648

-25 to +85

IN/648

Oto +70

N/648

SG3527A

±200
(Totem Pole MOSFET
Drive Outputs)
±1500
(Totem Pole MOSFET
Drive Outputs)

Reference
(V)

Maximum
Useful
Oscillator
Frequency
(kHz)

5.0±2.0%

9.6 to 20

Resonant
(Zero
Current)

5.1 ±2.0%

1000

N/648

SG3526

o to +125(2)

Nn07

MC34066

Oto+70

DWn51G

MC33066

-40 to +85

DWn51G

P/648

P/648

Resonant
(Zero
Voltage)

2000

MC34067

Oto +70

DWn51G

MC33067

-40 to +85

DWn51G

MC34025

o to +70

DWn51G

P/648

P/648

2000
(Totem Pole MOSFET
Drive Outputs)

9.2 to 30

Current
or
Voltage

5.1 ±1.0%

1000

FNn75
P/648

MC33025

-40 to +105

DWn51G
FNn75
P/648

(1) Tolerance applies over the specified operating temperature range.
(2) Junction Temperature Range.

Analog and Interface Integrated

Circu~s

4.2-12

Motorola Master Selection Guide

Switching Regulator Control Circuits (continued)

High Voltage Switching Regulator
MC33362DW

TJ = -25 0 to +125°C, Case 751N
The MC33362 is a monolithic high voltage switching
regulator that is specifically designed to operate from a
rectified 120 Vac line source. This integrated circuit features
an on-chip 500 V/2.0 A SenseFET power switch, 250 V active
off-line startup FET, duty cycle controlled oscillator, current
limiting comparator with a programmable threshold and
leading edge blanking, latching pulse width modulator for
double pulse suppression, high gain error amplifier, and a
trimmed internal bandgap reference. Protective features
include cycie-by-cycie current limiting, input undervoltage
lockout with hysteresis, output overvoltage protection, and

thermal shutdown. This device is available in a 16 lead wide
body surface mount package.
• On-Chip 500 V, 2.0 A SenseFET Power Switch
• Rectified 120 Vac Line Source Operation
• On-Chip 250 V Active Off-Line Startup FET
• Latching PWM for Double Pulse Suppression
• Cycie-By-Cycie Current Limiting
• Input Undervoltage Lockout with Hysteresis
• Output Overvoltage Protection Comparator
• Trimmed 1.0% Internal Bandgap Reference
• Internal Thermal Shutdown

20 W Off-Line Converter

AC Input

"'0
Startup Input

.T.

I
I

Motorola Master Selection Guide

4.2-13

.. U::
DC Output

r;"'-''''-'-''"7·-'-- ~ -.--".-.-.-;-:-- - - . - - - - .

Analog and Interface Integrated Circuits

Switching Regulator Control Circuits (continued)

High Voltage Switching Regulator
MC33363DW

TJ = -25° to + 125°C, Case 751 N
The MC33363 is a monolithic high voltage switching
regulator that is specifically designed to operate from a
rectified 240 Vac line source. This integrated circuit features
an on-chip 700 V/l.0 A SenseFET power switch, 450 V active
off-line startup FET, duty cycle controlled oscillator, current
limiting comparator with a programmable threshold and
leading edge blanking, latching pulse width modulator for
double pulse suppression, high gain error amplifier, and a
trimmed internal bandgap reference. Protective features
include cycle-by-cycle current limiting, input undervoltage
lockout with hysteresis, output overvoltage protection, and

thermal shutdown. This device is available in a 16-lead wide
body surface mount package.
• On-Chip 700 V, 1.0 A SenseFET Power Switch
• Rectified 240 Vac Line Source Operation
• On-Chip 450 V Active Off-Line Startup FET
• Latching PWM for Double Pulse Suppression
• Cycle-By-Cycle Current Limiting
• Input Undervoltage Lockout with Hysteresis
• Output Overvoltage Protection Comparator
• Trimmed Internal Bandgap Reference
• Internal Thermal Shutdown

•
DC Output

Analog and Interface Integrated Circuits

4.2-14

Motorola Master Selection Guide

Special Switching Regulator Controllers
These high performance dual channel controllers are
optimized for off-line, ae-to--dc power supplies and dc-to--dc
converters in the flyback topology. They also have
undervoltage lockout voltages which are optimized for off-line

and lower voltage dc-te-dc converters, respectively.
Applications include desktop computers, peripherals,
televisions, games, and various consumer appliances.

Table 10. Dual Channel Controllers

10
(mA)
Max

Minimum
Operating
Voltage
Range
(V)

Operating
Mode

Reference
(V)

Maximum
Useful
Oscillator
Frequency
(kHz)

500

4.0

Voltage

1.25±2.0%

700

Device

TA
(OC)

Suffix!
Package

MC34270

Oto +70

FB/873A

MC34065

Oto +70

DW-Hn51G

MC33065

-40 to +85

DW-Hn51G

MC34065

Oto +70

DW-U751G

MC33065

-40 to +85

DW-U751G

MC34271
±1000
(Totem Pole MOSFET
Drive Outputs)

11 to 20

Current

5.0±2.6%

500

P-H/648

P-H/648
8.2 to 20

P-U648

P-U648

Table 11. Universal Microprocessor Power Supply Controllers
A versatile power supply control circuit for microprocessor-based systems, this device is mainly intended for automotive
applications and battery powered instruments. The circuit provides a power-on reset delay and a Watchdog feature for orderly
microprocessor operation.
Vcc
(V)

Regulated
Outputs

Output
Current (mA)

Min

Max

Reference
(V)

E2PROM Programmable
Output:
24 V (Write Mode)
5.0 V (Read Mode)

150 peak

6.0

35

2.5±3.2%

Key
Supervisory
Features
MPU Reset and
Watchdog
Circuit

Device
TCF5600
TCA5600

TA
(OC)

Package

-40 to +85

707

Table 12. Power Factor Controllers

10
(mA)
Max
±500
(Totem Pole MOSFET
Drive Outputs)

Minimum
Operating
Voltage
Range
(V)

Maximum
Startup
Voltage
(V)

Reference
(V)

9.0 to 30

30

2.5±1.4%

Features

Device

TA
("C)

Undervoltage Lockout,
Internal Startup
Timer

MC34261

Oto+70

Suffix!
Package

Dn51
P/626

MC33261

-4010+85

Dn51

Overvoltage
Comparator,
Undervoltage Lockout,
Internal Startup
Timer

MC34262

Oto+85

Dn51

MC33262

-40 to +105

Dn51

Off-Line High Voltage
Startup Overvoltage
Comparator,
Undervoltage Lockout,
Timer, Low Load Detect

MC33368

-25 to +125

Dn51

P/626

1500
(CMOS Totem Pole
MOSFET Drive
Outputs)

9.0 to 16

Motorola Master Selection Guide

500

5.0± 1.5%

4.2-15

P/626

P/626

Analog and Interface Integrated Circuits

Power Factor Controllers
MC34262D, P

TA =0° to +85°C, Case 751,626
MC33262D, P

TA = 40° to +105°C, Case 751,626
The MC34262, MC33262 series are active power factor
controllers specifically designed for use as a preconverter in
electronic ballast and in off-line power converter applications.
These integrated circuits feature an internal startup timer for
stand alone applications, a one quadrant multiplier for near
unity power factor, zero current detector to ensure critical
conduction operation, transconductance error amplifier,
quickstart circuit for enhanced startup, trimmed internal
bandgap reference, current sensing comparator, and a totem
pole output ideally suited for driving a power MOSFET.

Also included are protective features consisting of an
overvoltage comparator to eliminate runaway output voltage
due to load removal, input .undervoltage lockout with
hysteresis, cycle-by-cycle current limiting, multiplier output
clamp that limits maximum peak switch current, an RS latch
for single pulse metering, and a drive output high state clamp
for MOSFET gate protection. These devices are available in
dual-in-line and surface mount plastic packages.

Vo

330 400 VlO.44 A

Analog and Interface Integrated Circuits

4.2-16

Motorola Master Selection Guide

Power Factor Controllers (continued)
MC33368D

TJ = -25° to +125°C, Case 751 K
The MC33368 is an active power factor controller that
functions as a boost preconverter in off-line power supply
applications. MC33368 is optimized for low power, high
density power supplies requiring minimum board area,
reduced component count, and low power dissipation. The
narrow body SOIC package provides a small footprint.
Integration of the high voltage startup saves approximately
0.7 W of power compared to resistor bootstrapped circuits.
The MC33368 features a watchdog timer to initiate output
switching, a one quadrant multiplier to force the line current to
follow the instantaneous line voltage, a zero current detector
to ensure critical conduction operation, a transconductance
error amplifier, a current sensing comparator, a 5.0 V

reference, an undervoltage lockout (UVLO) circuit which
monitors the VCC supply voltage, and a CMOS driver for
driving MOSFETs. The MC33368 also includes a
programmable output switching frequency clamp. Protection
features include an output overvoltage comparator to
minimize overshoot, a restart delay timer, and cycle-bycycle current limiting.
• Lossless Off-Line Startup
• Output Overvoltage Comparator
• Leading Edge Blanking (LEB) for Noise Immunity
• Watchdog Timer to Initiate Switching
• Restart Delay Timer

D6
1N4934

400 V

RlO
15 k
R5
1.3 M

MTW
14N50E

R2
820 k

C7

~470pF
LEB
9
CS

~
MULT

C8
.001

Rg
10
R7
0.1

Li..>= _ _ _ _

R3

C2

10 k

0.01

Camp

4

~ ~~8

FB

Vref

Vref

Motorola Master Selection Guide

4.2-17

R1
10 k

Analog and Interface Integrated Circuits

Supervisory Circuits
A variety of Power Supervisory Circuits are offered.
Overvoltage sensing circuits which drive "Crowbar" SCRs
are provided in several configurations from a low cost
three-terminal version to 8-pin devices which provide

pin-programmable trip voltages or additional features, such
as an indicator output drive and remote activation capability.
An over/undervoltage protection circuit is also offered.

Overvoltage Crowbar Sensing Circuit
MC3423P1,D

TA = 0° to +70°C, Case 626, 751
This device can protect sensitive
circuitry from power supply transients or
regulator failure when used with an external
"Crowbar" SCR. The device senses
voltage and compares it to an internal 2.6 V
reference. Overvoltage trip is adjustable by
means of an external resistive voltage
divider. A minimum duration before trip is
programmable with an external capacitor.
Other features include a 300 rnA high
current output for driving the gate of a
"Crowbar" SCR, an open-collector
indicator output and remote activation
capability.

Sense 1

Remote

Activation

Over/Undervoltage Protection Circuit
MC3425P1

TA = 0° to +70°C, Case 626
The MC3425 is a power supply
supervisory circuit containing all the
necessary functions required to monitor
over and undervoltage fault conditions.
This device features dedicated over and
undervoltage sensing channels with
independently programmable time delays.
The overvoltage channel has a high current
drive output for use in conjunction with an
external SCR "Crowbar" for shutdown. The
undervoltage channel input comparator
has hysteresis which is externally
programrnable, and an open-collector
output for fault indication.

OV
Sense

UV
Sense

Input Section

Analog and Interface Integrated Circuits

4.2-18

Output Section

Motorola Master Selection Guide

Supervisory Circuits

(continued)

Undervoltage Sensing Circuit
MC34064P-5, D-5
TA = 0° to +70°C, Case 29,751
MC33064P-5, 0-5
TA = -40° to +85°C, Case 29, 751

MC34164P-3,P-5,0-3,0-5
TA

=0° to +70°C, Case 29, 751

Pin numbers in
parenthesis
are for the
D suffix package.

MC33164P-3, P-5, 0-3, 0-5
TA = -40° to +85°C, Case 29,751
The MC34064 and MC34164 are two families of
undervoltage sensing circuits specifically designed for use as
reset controllers in microprocessor-based systems. They
offer the designer an economical solution for low voltage
detection with a single external resistor. Both parts feature a
trimmed bandgap reference, and a comparator with precise
thresholds and built-in hysteresis to prevent erratic reset
operation.
The two families of undervoltage sensing circuits taken
together, cover the needs of the most commonly specified
power supplies used in MCU/MPU systems. Key parameter
specifications of the MC34164 family were chosen to
complement the MC34064 series. The table summarizes
critical parameters of both families. The MC34064 fulfills the
needs of a 5.0 V ± 5% system and features a tighter hysteresis
specification. The MC34164 series covers 5.0 V ± 10% and

3.0 V ± 5% power supplies with significantly lower power
consumption, making them ideal for applications where
extended battery life is required such as consumer products
or hand held equipment.
Applications include direct monitoring of the 5.0 V MPUI
logic power supply used in appliance, automotive, consumer,
and industrial equipment.
The MC34164 is specifically designed for battery powered
applications where low bias current (1/25th of the MC34064's)
is an important characteristic.

Table 13. Undervoltage Sense/Reset Controller Features
MC34X64 devices are specified to operate from 0° to +70°C and MC33X64 devices operate from -40° to +85°C

Device

Standard
Power
Supply
Supported

Typical
Threshold
Voltage
(V)

Typical
Hysteresis
Voltage
(V)

Minimum
Output
Sink
Current (mA)

Power
Supply
Input
Voltage
Range (V)

MC34064IMC33064

5.0V±5%

4.6

0.02

10

1.0to 10

MC34164/MC33164

5.0V±10%

4.3

0.09

7.0

1.0 to 12

3.0V±5%

2.7

0.06

6.0

1.0 to 12

Motorola Master Selection Guide

4.2-19

Maximum
Quiescent
Input
Current

Suffix!
Package

500~
@

P-5/29

Vin=5.0V

0-5/751

20~
@

P-5/29

Vin=5.0V

0-51751

15~
@

P-3129

Yin = 3.0 V

0-31751

Analog and Interface Integrated Circuits

Supervisory Circuits

(continued)

Universal Voltage Monitor
MC34161P, D

TA

MC33161P, D

=0° to +70°C, Case 626,751

TA =-40° to +85°C, Case 626, 751

The MC34161, MC33161 series are universal voltage
monitors intended for use in a wide variety of voltage sensing
applications. These devices offer the circuit designer an
economical solution for positive and negative voltage
detection. The circuit consists of two comparator channels
each with hysteresis, a unique Mode Select Input for channel
programming, a pinned out 2.54 V reference, and two open
collector outputs capable of sinking in excess of 10 mAo Each
comparator channel can be configured as either inverting or
noninverting by the Mode Select Input. This allows over,
under, and window detection of positive and negative
voltages. The minimum supply voltage needed for these
devices to be fully functional is 2.0 V for positive voltage
sensing and 4.0 V for negative voltage sensing.
Applications include direct monitoring of positive and
negative voltages used in appliance, automotive, consumer,
and industrial equipment.
• Unique Mode Select Input Allows Channel Programming
• Over, Under, and Window Voltage Detection
• Positive and Negative Voltage Detection
• Fully Functional at 2.0 V for Positive Voltage Sensing and
4.0 V for Negative Voltage Sensing
• Pinned Out 2.54 V Reference with Current Limit Protection
• Low Standby Current
• Open Collector Outputs for Enhanced Device Flexibility

Vref

Mode
Select
Input 1

Input 2

TRUTH TABLE
Mode Select
Pin7

Input 1
Pin 2

Output 1
Pin6

Input 2
Pin3

Output 2
PinS

GND

0
1

0

0

Channels 1 & 2: Noninverting

1

1

0
1

Vref

0

1

0
1

0
1

1
0

Channell: Noninverting
Channel 2: Inverting

0
1

1

0
1

1
0

Channels 1 & 2: Inverting

'0

VCC (>2.0 V)

Comments

POSITIVE AND NEGATIVE OVERVOLTAGE DETECTOR

InputVS2

Gnd

Output
Voltage
Pins 5, 6

Vee

LED ''On'

Gnd

-VSl

I
I
I
I

VS2

tllJI

--------'

Analog and Interface Integrated Circuits

4.2-20

Motorola Master Selection Guide

Battery Management Circuits
Battery Charger ICs
Battery Fast Charge Controller
MC33340D
TA = -25° to +85°C, Case 751
The MC33340 is a monolithic controllC that is specifically
designed as a fast charge controller for Nickel Cadmium
(NiCd) and Nickel Metal Hydride (NiMH) batteries. This device
features negative slope voltage detection as the primary
means for fast charge termination. Accurate detection is
ensured by an output that momentarily interrupts the charge
current for precise voltage sampling. An additional secondary
backup termination method can be selected that consists of
either a programmable time or temperature limit. Protective
features include battery over- and undervoltage detection,
latched over temperature detection, and power supply input
undervoltage lockout with hysteresis. Provisions for entering

De

Vee 8

Input

Motorola Master Selection Guide

a rapid test mode are available for enhanced end product
testing. This device is available in an economical 8 lead
surface mount package.
• Negative Slope Voltage Detection
• Accurate Zero Current Battery Voltage Sensing
• Programmable 1 to 4 Hour Fast Charge Time Limit
• Programmable Over/Under Temperature Detection
• Battery Over- and Undervoltage Fast Charge Protection
• Rapid System Test Mode
• Power Supply Input Undervoltage Lockout with
Hysteresis
• Operating Voltage Range of 3.0 V to 18 V

4.2-21

Analog and Interface Integrated Circuits

Battery Charger ICs

(continued)

Power Supply
Battery Charger
Regulation Control Circuit
MC33341P, D

TA =-40° to +85°C, Case 626, 751
The MC33341 is a monolithic regulation control circuit that
is specifically designed to close the voltage and current
feedback loops in power supply and battery charger ,
applications. This device features the unique ability to perform
source high-side, load high-side, source low-side, and load
low-side current sensing, each with either an internally fixed
or externally adjustable threshold. The various current
sensing modes are accomplished by a means of selectively
using the internal differential amplifier, inverting amplifier, or a
direct input path. Positive voltage sensing is performed by an
internal voltage amplifier. The voltage amplifier threshold is
internally fixed and can be externally adjusted in all low-side
current sensing applications. An active high drive output is
provided to directly interface with economical optoisolators for
isolated output power systems. This device is available in
8 lead dual-in-line and surface mount packages.

Drive Output
8

Current Sense
Input A

Analog and Interface Integrated Circuits

• Differential Amplifier for High-Side Source and Load
Current Sensing
• Inverting Amplifier for Source Return Low-Side Current
Sensing
• Noninverting Input Path for Load Low-Side Current
Sensing
• Fixed or Adjustable Current Threshold in all Current
Sensing Modes
• Positive Voltage Sensing in all Current Sensing Modes
• Fixed Voltage Threshold in all Current SenSing Modes
• Adjustable Voltage Threshold in all Low-Side Current
SenSing Modes
• Output Driver Directly Interfaces with Economical
Optoisolators
• Operating Voltage Range of 2.3 V to 18 V

Current Sense Input BI
Voltage Threshold Adjust
6

Voltage Sense
Input

Compensation

Gnd

Current
Threshold Adjust

4.2-22

5

Motorola Master Selection Guide

Battery Pack ICs
1 to 4 Cells Lithium Battery Safety IC
MC33344DW
TA

=-40° to +85°C, Case 751 D

The MC33344 is a Lithium Battery Safety Integrated Circuit
designed to control the charge and discharge voltage safety
limits of one to four lithium-ion or lithium polymer
rechargeable cells. This device is designed to be placed inside
the battery pack together with the cells and other external
components, to form a smart battery pack. Its main purpose
is to ensure safe battery pack charging and discharging.
The circuit also protects the integrity of the Li-ion cells. In
effect, it avoids the degradation of the cells in case of
overdischarge by causing the battery pack to go in a zero
current SLEEPMODETM state. This state interrupts any further
leakage of the cells.
Integrated into the MC33344 are two seriesed N-FETs
designed to interrupt the battery charge or discharge current.

• Precision Cell Voltage Measurement with an Accuracy
of 1.0%
• Programmable Voltage and Current Limits
• Automatic Cell Balancing for Optimization of the Charge
of each Cell

Protection Features:
• Zero Current Sleepmode in Order to Avoid the
Degradation of a Cell in the Event of an Undervoltage
Condition
• Overvoltage and Undervoltage Cell Protection
• Overcurrent Protection during Charge and Discharge

Designed for Smart Battery Pack Integration:
• Surface Mount 20 Pin Package
• On-Chip Series N-FETs capable of up to 1.5 A Load
Current

Charge Control:
• Fully programmable for 1 to 4 Lithium-Ion (Li-ion) or
Lithium-Polymer Rechargeable Cells

Ref
Gnd

Motorola Master Selection Guide

Test

Prog1

4.2-23

Prog2

Charge Pump
Output Pin

Analog and Interface Integrated Circuits

Battery Pack ICs

(continued)

1 to 4 Cells Lithium Battery Safety IC
MC33345DTB
TA

=-40° to +85°C, Case 948E

The MC33345 is a Lithium Battery Safety Integrated Circuit
designed to control the charge and discharge voltage safety
limits of one to four lithium-ion or lithium polymer
rechargeable cells. This device is designed to be placed inside
the battery pack together with the cells and other external
components, to form a smart battery pack. Its main purpose
is to ensure safe battery pack charging and discharging.
The circuit also protects the integrity of the Li-ion cells. In
effect, it avoids the degradation of the cells in case of
overdischarge by causing the battery pack to go in a zero
current SLEEPMODpM state. This state interrupts any further
leakage of the cells.

• Precision Cell Voltage Measurement with an Accuracy
of 1.0%
• Programmable Voltage and Curre'lt Limits
• Automatic Cell Balancing for Optimization of the Charge
of each Cell
Protection Features:
• Zero Current Sleepmode in Order to Avoid the
Degradation of a Cell in the Event of an Undervoltage
Condition
• Overvoltage and Undervoltage Cell Protection
• Overcurrent Protection during Charge and Discharge

Charge Control:

Designed for Smart Battery Pack Integration:

• Fully programmable for 1 to 4 Lithium-Ion (Li-ion) or
Lithium-Polymer Rechargeable Cells

• Low Profile 20 Pin Surface Mount Package

Pack +
Over Charge

RC
Over Discharge

RD
VCC
cell 4
V3

cell 3
V2

cell 2
V19-+~

cell 1

Ref
Gnd

Analog and Interface Integrated Circuits

Test

Prog 1 Prog 2

4.2-24

Charge Pump
Output Pin

Motorola Master Selection Guide

MOSFET/IGBT Drivers
High Speed Dual Drivers
(Inverting)

(Noninverting)

MC34151P,D

MC34152P,D

TA = 0° to +70°C, Case 626, 751

TA

MC33151P,D
TA

=0° to +70°C, Case 626, 751

MC33152P,D

=-40° to +85°C, Case 626, 751

TA = -40° to +85°C, Case 626,751

Vcc
These two series of high speed dual MOSFET driver ICs
are specifically designed for applications requiring low current
digital circuitry to drive large capacitive loads at high slew
rates. Both series feature a unique undervoltage lockout
function which puts the outputs in a defined low state in an
undervoltage condition. In addition, the low "on" state
resistance of these bipolar drivers allows significantly higher
output currents at lower supply voltages than with competing
drivers using CMOS technology.
The MC34151 series is pin--compatible with the MMH0026
and DS0026 dual MOS clock drivers, and can be used as
drop-in replacements to upgrade system performance. The
MC34152 noninverting series is a mirror image of the inverting
MC34151 series.
These devices can enhance the drive capabilities of first
generation switching regulators or systems designed with
CMOSnTL logic devices. They can be used in dc-to-dc
converters, motor controllers, capacitor charge pump
converters, or virtually any other application requiring high
speed operation of power MOSFETs.

Logic
Input A

Drive
Output A

Logic
InputB

Drive
OutputB

Single IGBT Driver
MC33153P,D
TA =-40° to +105°C, Case 626, 751
The MC33153 is specifically designed to drive the gate of
an IGBT used for ac induction motors. It can be used with
discrete IGBTs and IBGT modules up to 100 A.
Typical applications are ac induction motor' control,
brushless dc motor control, and uninterruptable power
supplies.
These devices are available in dual-in-line and surface
mount packages and include the following features:
• High Current Output Stage: 1.0 A Source - 2.0 A Sink
• Protection Circuits for Both Conventional and
SenselGBTs
• Current Source for Blanking Timing
• Protection Against Overcurrent and Short Circuit
• Undervoltage Lockout Optimized for IGBT's
• Negative Gate Drive Capability

Motorola Master Selection Guide

Current
Sense
Input
Kelvin
2 Gnd
Blanking
Desatirat
8 opm

Input

4.2-25

Gate
Drive
5 Ouptut

Analog and Interface Integrated Circuits

Power Supply Circuits Package Overview

I
CASE 29
P,ZSUFFIX

CASE 221A
T, KCSUFFIX

CASE 314D
TSUFFIX

CASE 369
DT-1 SUFFIX

CASE 646
PSUFFIX

CASES 648, 648C
N, P, P2 SUFFIX

,
•
•
•

CASE 314A
TH SUFFIX

,
,. ,
•
• •
#-

CASE 751A
D SUFFIX

CASE 751B
D SUFFIX

#

CASE 751K
DSUFFIX

CASE 751N
DWSUFFIX

CASE 936
D2TSUFFIX

CASE 936A
D2TSUFFIX

Analog and Interface Integrated Circuits

,.

CASE 369A
DTSUFFIX

CASE 626
N, P, P1 SUFFIX

CASE 707
N SUFFIX

CASE 751
D, D1 SUFFIX

CASE 751D
DWSUFFIX

CASE 751G
DWSUFFIX

CASE 775
FN SUFFIX

CASE 873A
FB SUFFIX

•

CASE 948B
DTB SUFFIX

4.2-26

CASE 314B
TV SUFFIX

•

•
•
..

CASE 948E
DTB SUFFIX

Motorola Master Selection Guide

Power/Motor Control Circuits

In Brief ...
Page

With the expansion of electronics into more and more
mechanical systems, there comes an increasing demand for
simple but intelligent circuits that can blend these two
technologies. In the past, the task of power/motor control
was once accomplished with discrete devices. But today this
task is being performed by bipolar IC technology due to cost,
size, and reliability constraints. Motorola offers integrated
circuits designed to anticipate the requirements for both
simple and sophisticated control systems, while providing
cost effective solutions to meet the needs of the applications.

Motorola Master Selection Guide

Power Controllers .............................. 4.3-2
Zero Voltage Switch . . . . . . . . . . . . . . . . . . . . . . . . .. 4.3-2
Zero Voltage Controller .. . . . . . . . . . . . . . . . . . . . .. 4.3-3
High-Side Driver Switch ...................... 4.3-4
Motor Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.3-4
Brushless DC Motor Controllers ............... 4.3-4
Closed Loop Brushless Motor Adapter .. . . . . . . .. 4.3-7
DC Servo Motor Controller/Driver .............. 4.3-8
Stepper Motor Driver .... . . . . . . . . . . . . . . . . . . . .. 4.3-9
Universal Motor Speed Controller ............. 4.3-10
Triac Phase Angle Controller ................. 4.3-11
Package Overview ............................ 4.3-12

4.3-1

Analog and Interface Integrated Circuits

Power Controllers
An assortment of battery and ac line-operated controllCs for specific applications are shown. They are designed to enhance
system performance and reduce complexity in a wide variety of control applications.

Zero Voltage Switch
CA3059
TA = -40° to +85°C, Case 646
This device is designed for thyristor control in a variety of
ac power switching applications for ac input voltages of
24 V, 120 V, 208/230 V, and 227 V @ 50160 Hz.
• Protection Circuit (CA3059 only) - A built-in circuit may
be actuated, if the sensor opens or shorts, to remove the
drive circuit from the external triac.

• Limiter-Power Supply - Allows operation directly from
an ac line.
• Differential "On"/"Off" Sensing Amplifier - Tests for
condition of external sensors or input command signals.
Proportional control capability or hysteresis may be
implemented.

• Inhibit Capability (CA3059 only) - Thyristor firing may
be inhibited by the action of an internal diode gate.
• High Power DC Comparator Operation (CA3059 only)
- Operation in this mode is accomplished by connecting
Pin 7 to 12 (thus overriding the action of the
zero-crossing detector).

• Zero-Crossing Detector - Synchronizes the output
pulses to the zero voltage point of the ac cycle.
Eliminates RFI when used with resistive loads.
• Triac Drive - Supplies high current pulses to the external
power controlling thyristor.

AC
Input
Voltage

'NTCSensor
NOTE: Shaded Area Not Included with CA3079.

Analog and Interface Integrated Circuits

Gnd

~------------------------~~--~

4.3-2

Motorola Master Selection Guide

Power Controllers

(continued)

Zero Voltage Controller
UAA1016B

TA = -20° to +1 OO°C, Case 626
This device is designed to drive triacs
with the Zero Voltage technique which
allows RFI free power regulation of
resistive loads. They provide the following
features:
• Proportional Temperature Control Over
an Adjustable Band

220VAC

Temp
Set
Rt

"b

Vref

• Adjustable Burst Frequency (to Comply
with Standards)
• Sensor Fail-Safe
• No DC Current Component Through the
Main Line (to Comply with Standards)
• Negative Output Current Pulses (Triacs
Quadrants 2 and 3)

Load
(NTC)
Temp
Sensor
R3
"b

• Direct AC Line Operation

VAC

• Low External Components Count

Zero Voltage Controller
UAA2016P, D

TA

=-20° to +S5°C, Case 626, 751

The UAA2016 is designed to drive triacs
with the Zero Voltage technique which
allows RFI free power regulation of
resistive loads. Operating directly on the ac
power line, its main application is the
precision regulation of electrical heating
systems such as panel heaters or irons.
A built-in digital sawtooth waveform
permits proportional temperature regulation
action over a ±1 °C band around the set point.
For energy savings there is a programmable
temperature reduction function, and for
security, a sensor failsafe inhibits output
pulses when the sensor connection is
broken. Preset temperature (Le., defrost)
application is also possible. In applications
where high hysteresis is needed, its value
can be adjusted up to 5°C around the set
point. All these features are implemented
with a very low external cornponent count.

Sense Input

Temperature
Reduction

Hysteresis
Adjust
Voltage
Reference

• Zero Voltage Switch for Triacs, up to
2.0 kW (MAC212AS)
• Direct AC Line Operation
• Proportional Regulation of Ternperature
over a 1°C Band
• Programmable Temperature Reduction
• Preset Temperature (Le., Defrost)
• Sensor Failsafe
• Adjustable Hysteresis
• Low External Component Count

Motorola Master Selection Guide

4.3-3

Analog and Interface Integrated Circuits

Power Controllers

(continued)

High-Side Driver Switch
MC3399T,
TJ

=-40

0

ow
to +150°C, Case 3140, 751G

The MC3399T is a high side driver
switch that is designed to drive loads from
the positive side of the power supply. The
output is controlled by a TTL compatible
Enable pin. In the "on" state, the device
exhibits very low saturation voltages for
load currents in excess of 750 mAo The
device also protects the load from positive
or negative-going high voltage transients
by becoming an open circuit and isolating
the transient for its duration from the load.
The MC3399T is fabricated on a Power
BiMOS process which combines the best
features of Bipolar and MOS technologies.
The mixed technology provides higher gain
PNP output devices and results in Power
Integrated Circuits with reduced quiescent
current.

50n

Motor Controllers
This section contains integrated circuits designed for cost effective control of specific motor families. Included are controllers
for brushless, de servo, stepper, and universal type motors.

Brushless DC Motor Controllers
controllers. These ICs provide a choice of control functions
which allow many system features to be easily implemented
at a fraction of the cost of discrete solutions. The following
table summarizes and compares the features of Motorola's
brush less motor controllers.

Advances in magnetic materials technology and integrated
circuits have contributed to the unprecedented rise in
popularity of brush less dc motors. Analog control ICs are
making the many features and advantages of brushless
motors available at a much more economical price. Motorola
offers a family of monolithic integrated brushless dc motor

Table 1. Features Summary for Motorola Brushless DC Motor Controllers
Operating
Voltage Range
(V)

..

iii
E

:!l!0 ..

.cc

al

~:::I

.. j

"1:1"

Output
Drivers

~

ii~~
C"I:I
ai'S

~~

~8

Vee

Ve

Co
:::I...J

".c
.5cn

MC33033

10-30

-

v'

v'

v'

MC33035

10-40

10-30

v'

v'

v'

Device

Analog and Interface Integrated Circuits

l5~f

~!'g :I
~jjjif

60°/300°
and
120°/240°

~

'SJ!!

H
:::Ic

Ow

E
E .. :Ii!

"_0

J~
8.- a.

~.f!!!. 08~

.."
C

f!

~
It_

i:::I

a.

:.5
c~

~~

el

>:::1
...
.eN:::I
<60

uu

~E
:::10

!

~=a

I~~
:::I.e-

"U
"Iii>
;a~

.5~ 1fc5 ~

~

..

1D.5

1!S-

Suffix!
Package

v'

v'

v'

v'

Noninv.
Only

v'

-

-

-

P1738,
DWI751D

v'

v'

v'

v'

Noninv.
and Inv.

v'

v'

v'

v'

P1724,
DW1751E

4.3-4

Motorola Master Selection Guide

Motor Controllers

(continued)

MC33033P, OW

TA

=-40° to +85°C, Case 738, 751 D
Because of its low cost, the MC33033 can efficiently be
used to control brush dc motors as well as brush less. A brush
dc motor can be driven using two of the three drive output
phases provided in the MC33033, while the Hall sensor input
pins are selectively tied to Vref or ground. Other features such
as forward/reverse, output enable, speed control, current
limiting, undervoltage lockout and internal thermal shutdown
will still remain functional.

The MC33033 is a lower cost second generation brushless
dc motor controller which has evolved from the full featured
MC33034 and MC33035 controllers. The MC33033 contains
all of the active functions needed to implement a low cost open
loop motor control system. This IC has all of the key control
and protection functions of the two full featured devices with
the following secondary features deleted: separate
drive-circuit supply and ground pins, the brake input, and the
fault output signal. Like its MC33035 predecessor, the
MC33033 has a control pin which allows the user to select
60°/300° or 120°/240° sensor electrical phasings.

r----...,

L ___ _

Motor

vcco---<>-

Speed Set

l

Faster

RT

CT

Motorola Master Selection Guide

4.3-5

Analog and Interface Integrated Circuits

Motor Controllers

(continued)

MC33035P, OW
TA = -40° to +85°C, Case 724, 751 E

60°/300° or 120°/240° sensor electrical phasings, and access
to both inverting and noninverting inputs of the current sense
comparator. The earlier devices had two part numbers which
were needed to support the different sensor phasings, and the
inverting input to the current sense comparator was internally
grounded. All of the control and protection features of the
MC33034 are also provided in the MC33035.

The MC33035 is a second generation high performance
brush less dc motor controller which contains all of the active
functions required to implement a full featured open loop
motor control system. While being pin-{;ompatible with its
MC33034 predecessor, the MC33035 offers additional
features at a lower price. The two additional features provided
by the MC33035 are a pin which allows the user to select

----,

~----lT~iiiiiiiiiiiiiiiiiiiiiiiiiiiiii~~~~~~nJ~i

~~~I

L

I
I
I
I
I
I
____ J
Motor

Speed Set

i

Faster

Analog and Interface Integrated Circuits

4.3-6

Motorola Master Selection Guide

Motor Controllers

(continued)

Closed Loop Brushless Motor Adapter
MC33039P,D
TA = -40° to +85°C, Case 626, 751
detectors, a programmable monostable, and an internal shunt
regulator. Also included is an inverter output for use in systems
that require conversion of sensor phasing. Although this
device is primarily intended for use with the MC33033/35
brushless motor controllers, it can be used cost effectively in
many other closed loop speed control applications.

The MC33039 is a high performance close loop speed
control adapter specifically designed for use in brush less dc
motor control systems. Implementation will allow precise
speed regulation without the need for a magnetic or optical
tachometer. These devices contain three input buffers each
with hysteresis for noise immunity, three digital edge

Vcc

il>A

To Rotor
Position
Sensors

fout

il>B

il>C

Gnd

Motorola Master Selection Guide

4.3-7

Analog and Interface Integrated Circuits

Motor Controllers

(continued)

DC Servo Motor Controller/Driver
MC33030P,

ow

TA = -40° to +85°C, Case 648C, 751G
A monolithic dc servo motor controller providing all active
functions necessary for a complete closed loop system. This
device consists of an on-chip op amp and window comparator
with wide input common mode range, drive and brake logic
with direction memory, a power H switch driver capable of

1.0 A, independently programmable over current monitor and
shutdown delay, and over voltage monitor. This part is ideally
suited for almost any servo positioning application that
requires sensing of temperature, pressure, light, magnetic
flux, or any other means that can be converted to a voltage.
Motor

Vee
Feedback
Position

Vee
Reference
Position

Analog and Interface Integrated Circuits

4.3-8

Motorola Master Selection Guide

Motor Controllers

(continued)

Stepper Motor Driver
MC3479P, FN

TA = 0° to +70°C, Case 648C, 775
SAA1042AV

TA = -30° to +125°C, Case 648C
These Stepper Motor Drivers provide up to 500 mA of drive
per coil for two phase 6.0 V to 24 V stepper motors. Control
logic is provided to accept commands for clockwise, counter

clockwise and half or full step operation. The MC3479 has an
added Output Impedance Control (OIC) and a Phase A drive
state indicator (not available on SAA1042 devices).

ClK

l2
CW/CCW

Vo
l3

Full/Half
Step

l4
OIC'

Phase A'

Bias/Set

Gnd

, MC3479 Only

Motorola Master Selection Guide

4.3-9

Analog and Interface Integrated Circuits

Motor Controllers

(continued)

Universal Motor Speed Controller
TDA108SC, CD
TA

=-10° to +120°C, Case 648, 7518

The TDA 1085C is a phase angle triac controller having all
the necessary functions for universal motor speed control in
washing machines. It operates in closed loop configuration
and provides two ramp possibilities.

• Soft Start
• Load Current Limitation
• Tachogenerator Circuit Sensing

• On-Chip Frequency to Voltage Converter

• Direct Supply from AC Line

• On-Chip Ramps Generator

• Security Functions Peformed by Monitor

(I)

'"<=

(I)

en
"0
(I)
(I)

Cl.

en

;m

.2'

0

~

"OJ
0
Cl.

§

"0

"0

"en

"en

OJ

en

(I)
(I)

~

D-

0

(I)
(I)

Q;

'Eo

.~

80

:::;
1:
(I)

~~

~~

""'

0

a::g

~

O)

(!)

::;:

il:

Analog and Interface Integrated Circuits

0>

.~
i=

.9
~

(I)

<=
(I)
(!)
Cl.

E
OJ
a:

4.3-10

.~

15
.l!!

en

Cl.

0

.3
"0

~

0

·1

1:

OJ

~
0

.<=

en

Cl.

0

i

en

Q;

<=

<=

"S

.~

15
.!O:!

0

.<=

.<=

0

15

e

0

<=

e

%

]l

"<= ~
" D-:;;"
"l5 ili
~ N 1: $
en
~

0>

(I)

~

0

Motorola Master Selection Guide

Motor Controllers

(continued)

Triac Phase Angle Controller
TDA1185A
TA

=0° to + 70°C, Case 646

This device generates controlled triac triggering pulses and
allows tach less speed stabilization of universal motors by an
integrated positive feedback function.

• Triac Current Sensed to Allow Inductive Loads

• Low Cost External Components Count

• Low Power Consumption: 1.0 mA

• Soft-Start
• Power Failure Detection and General Circuit Reset

• Optimum Triac Firing (2nd and 3rd Quadrants)
• Repetitive Trigger Pulses when Triac Current is
Interrupted by Motor Brush Bounce

Motorola Master Selection Guide

4.3-11

Analog and Interface Integrated Circuits

Power/Motor Control Circuits Package Overview

•

~
CASE 3140
TSUFFIX

CASE 626
B, PSUFFIX

CASE 646

- • #
CASE 724
PSUFFIX

CASE 738
PSUFFIX

CASE 7510
OW SUFFIX

OW SUFFIX

Analog and Interface Integrated Circuits

~
CASE 751
o SUFFIX

•

CASE 751E

CASE 751G
OW SUFFIX

4.3-12

,

CASE 648, 648C
P, V SUFFIX

CASE 751B
o SUFFIX

•

CASE 775
FN SUFFIX

Motorola Master Selection Guide

Voltage References

In Brief ...
Page
Precision Low Voltage References . . . . . . . . . . . . . . .. 4.4-2
Package Overview ............................. 4.4-2

Motorola's line of precIsion voltage references is
designed for applications requiring high initial accuracy, low
temperature drift, and long term stability. Initial accuracies of
±1.0%, and ±2.0% mean production line adjustments can be
eliminated. Temperature coefficients of 25 ppm/oC max
(typically 10 ppm/oC) provide excellent stability. Uses for the
references include D/A converters, AID converters,
precision power supplies, voltmeter systems, temperature
monitors, and many others.

Motorola Master Selection Guide

4.4-1

Analog and Interface Integrated Circuits

Precision Low Voltage References
A family of precision low voltage bandgap reference devices designed for applications requiring low temperature drift.

Table 1. Precision Low Voltage References
Vout
(V)

Typ
1.235± 12 mV
1.235±25 mV

-400 to +85°C

Regline
(mY)
Max

Regload
(mY)
Max

LM285Z-1.2

(Note 1)

1.0
(Note 2)

10
(mA)
Max

ppm/"C
Max

0° to +70°C

20

80Typ

LM385BZ-1.2
LM385Z-1.2
LM385BZ-2.5
LM385Z-2.5

LM285Z-2.5

-

Voutfl'

2.5±38mV
2.5±75 mV

Device

25

MC1403A

40

MC1403

5.0±50 mV

40

MC1404P5

-

6.25±60 mV

40

MC1404P6

-

10±100mV

40

MC1404P10

-

50Typ

TL431C, AC, BC

TL431I, AI, BI

2.5±25mV

2.5 to 37

10

100

Package
Z,D

2.0
(Note 3)

3.014.5
(Note 4)

10
(Note 5)

D

P

6.0
(Note 6)

Shunt Reference
Dynamic Impedance
(z)';;0.5Q

LP,P,D

Notes: 1. Micropower Reference Diode Dynamic Impedance (z) S 1.0 n at IR = 100 ~A.
2. 10!lA SIR S 1.0 mA.
3. 20!lA S IR S 1.0 mAo
4.4.5 V S Vin S 15 VI15 V S Vin S 40 V.
5.0 mA ~ IL ~ 10 mA.
6. (VOU! + 2.5 V) ~ Vin ~ 40 V.

Voltage References Package Overview

I

CASE 29
LP,ZSUFFIX

Analog and Interface Integrated Circuits

~

~

CASE 626
PSUFFIX

CASE 751
DSUFFIX

4.4-2

Motorola Master Selection Guide

Data Conversion

In Brief ...
Page

Motorola's line of digital-te-analog and analog-to-digital
converters include several well established industry
standards.
The AID converters have 7 and B-bit flash converters
suitable for NTSC and PAL systems, CMOS has 8 to 1O-bit
converters, as well as other high speed digitizing applications.
The D/A converters have 6 and 8-bit devices, video
speed (for NTSC and PAL) devices, and triple video DAC
with on-board color palette for color graphics applications.

Motorola Master Selection Guide

Data Conversion ...............................
A-D Converters .............................
CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bipolar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Sigma-Delta .............................
D--A Converters .............................
CMOS ...................................
Sigma-Delta .............................
Package Overview .............................

4.5-1

4.5-2
4.5--2
4.5--2
4.5--2
4.5--2
4.5--3
4.5-3
4.5--3
4.5--4

Analog and Interface Integrated Circuits

Data Conversion
The line of data conversion products which Motorola offers
spans a wide spectrum of speed and resolution/accuracy.
Features, including bus compatibility, minimize extemal parts
count and provide easy interface to microprocessor systems.
Various technologies, such as Bipolar and CMOS, are utilized

to achieve functional capability, accuracy and production
repeatability. Bipolar technology generally results in higher
speed, while CMOS devices offer greatly reduced power
consumption.

Table 1. A-D Converters

Device

Nonlinearity
Max

Conversion
Time/Rate

Input
Voltage
Range

Supplies
(V)

Temperature
Range
('C)

MC145040

±1/2 LSB

1Ol-'S

OtoVDD

+5.0±10%

-40 to +125

Resolution
(Bits)

Suffix!
Package

Comments

CMOS
8

MC145041
MC14549B/
MC14559B

P/738,
DW/751D

Includes Internal
Clock, 11-Ch MUX

2Ol-'S
Successive Approximation
Registers

+3.0 to +18

-40 to +85

P/648

Triple
8-Bit

MC44251

1 LSB

18MHz

1.6to 4.6 V

+5.0±10%

-40 to +85

FN1777

10

MC145050

±1 LSB

211-'s

OtoVDD

+5.0±10%

-40 to +125

P/738,
DW/7510

MC145051

Requires External
Clock, 11-Ch MUX

Compatible with
MC1408 SAR.
8-bit D-A Converter
3 Separate Video
Channels
Requires External
Clock, 11-Ch MUX
Includes Internal
Clock, 11-Ch MUX

441-'s
P/646,
0/751 A

MC145053
8-10

MC14443/
MC14447

±0.5%
Full Scale

300I-'S

Variable
w/Supply

+5.0 to +18

3-1/2 Digit

MC14433

±0.05%
±1 Count

40 ms

±2.0V
±200mV

+5.0 to +8.0
-2.8to-8.0

MC10319

±1 LSB

25 MHz

MC145073

±1 LSB

48 kHz

-40 to +85

Includes Internal
Clock, 5-Ch MUX

I-'P Compatible,
P/648 ,
DW1751G Single Slope,
6-Ch MUX
P/709,
DW1751E

Dual Slope

o to +70

P/709,
DW/751F
Die Form

Video Speed Flash
Converter, Internal
Gray Code
TTL Outputs

-40 to +85

DW/751E

Dual Channel,
Sigma-Delta
architecture

Bipolar
8

Oto 2.0 Vpp
+5.0 and
-3.0to-6.0
Max

Sigma-Delta
16

Analog and Interlace Integrated Circuits

1.9Vpp

4.5-2

4.5 to 5.5

Motorola Master Selection Guide

Table 2. O-A Converters

Device

Accuracy
@25"C
Max

Max
Settling
Time
(± 112 LSB)

Supplies
(V)

Temperature
Range
eC)

MC144110

-

-

+5.0 to +15

o to +85

MC144111

-

-

MC144112

-

-

+2.5 to +5.5

MC44200

±1/2 LSB

30 ns

16,18,20

MC145074

See data
sheet

-

MC145076

See data
sheet

Resolution
(Bits)

Suffix!
Package

Comments

CMOS
6

Triple
8-Bit

P/707,
DW/751D

Serial input, Hex DAC,
6 outputs

P/646,
DW/751G

Serial input, Quad DAC,
4 outputs

-40 to +85

P/646,
D/751 A

Serial input, Quad DAC,
4 outputs

+5.0
±10%

-40 to +85

FU/824A

Triple Video DAC,
55 MHz, TTL

6.0 ns

4.5 to 5.5

-40 to +85

D/751B

Dual Channel,
Sigma-Delta architecture,
MC145076 FIR Filter
available

-

+5.0

-40 to +85

D/751 B

Dual Channel Bit Stream,
144 tap FIR Filter

Sigma-Delta

Motorola Master Selection Guide

4.5-3

Analog and Interface Integrated Circuits

Data Conversion Package Overview

•
-

'"
~
CASE 709
PSUFFIX

CASE 707
PSUFFIX

CASE 751A
DSUFFIX

CASE 751B
DSUFFIX

CASE 751F
DWSUFFIX

CASE 751G
DWSUFFIX

Analog and Interface Integrated CircuHs

CASE 649
PSUFFIX

CASE 648
PSUFFIX

CASE 646
PSUFFIX

CASE 751D
DWSUFFIX

•

CASE 777
FN SUFFIX

4.5-4

-

CASE 738
PSUFFIX

CASE 751E
DWSUFFIX

•

CASE 824A
FUSUFFIX

Motorola Master Selection Guide

Interface Circuits

In Brief ...
Page

Described in this section is Motorola's line of interface
circuits, which provide the means for interfacing with
microprocessor or digital systems and the external world, or
to other systems.
Also included are devices which allow a microprocessor
to communicate with its own array of memory and peripheral
I/O circuits.
The line drivers, receivers, and transceivers permit
communication between systems over cables of several
thousand feet in length, and at data rates of up to several
megahertz. The common EIA data transmission standards,
several European standards, IEEE-488, and IBM 360/370
are addressed by these devices.
The peripheral drivers are designed to handle high
current loads such as relay coils, lamps, stepper motors, and
others. Input levels to these drivers can be TTL, CMOS, high
voltage MOS, or other user defined levels. The display
drivers are designed for LCD or LED displays, and provide
various forms of decoding.

Motorola Master Selection Guide

Enhanced Ethernet Transceiver .................. 4.6-2
High Performance Decoder Driver/Sink Driver . . . . .. 4.6-3
ISO 8802-3[IEEE 802.3]1 OBASE-T Transceiver ... 4.6-3
Hex EIA-485 Transceiver with
Three-State Outputs ... . . . . . . . . . . . . . . . . . . . . . . .. 4.6-4
5.0 V, 200 M-BitlSec PR-IV Hard Disk
Drive Read Channel ........................... 4.6-5
Line Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
EIA Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
Line Drivers ................................... 4.6-7
EIA Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
Line Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-7
EIA-232-E/V.28 CMOS Drivers/Receivers ...... 4.6-8
Peripheral Drivers ........................... 4.6-8
IEEE 802.3 Transceivers ...................... 4.6-8
Read/Write Channel ............................ 4.6-8
Drive Read Channel. . . . . . . . . . . . . . . . . . . . . . . . .. 4.6-8
CMOS Display Drivers .......................... 4.6-9
Package Overview ............................ 4.6-10

4.6-1

Analog and Interface Integrated Circuits

Enhanced Ethernet Transceiver
MC68160FB

TA

= 0° to +70°C, Case 8480

The MC68160 Enhanced Ethernet Interface Circuit is a
BiCMOS device which supports both IEEE 802.3 Access Unit
Interface (AUI) and 10BASE-T Twisted Pair (TP) Interface
media connections through external isolation transformers. It
encodes NRZ data to Manchester data and supplies the
signals which are required for data communication via
10BASE-T or AUI interfaces. The MC68160 gluelessly

interfaces to the Ethernet controller contained in the MC68360
Quad Integrated Communications Controller (QUICC) device.
The MC68160 also interfaces easily to most other
industry-standard IEEE 802.3 LAN controllers. Prior to
twisted pair data reception, Smart Squelch circuitry qualifies
input signals for correct amplitude, pulse width, and sequence
requirements.

RX~--------------~nM~amnCtcM~s~te9rlr

RCLK

Decoder

1+--------------1

ARX+

MFILT .....- - - - - - - - - - - '
ARX-

~~~~~~~~L~~Y---------j

RXLED
RENA_
CLLED

ACX+ w
ACX-

-1

w CLSN .....; = = = ; - - -.......

~TXLED

ATX-

~ TE~~ ~===-.l.rMaiiCheSrterl
~

ATX+

:5
c(

Xt

Twisted
Pair
Polarity
Error
Control

X2 :
TCLK ...f - - - - - -

CSt
CSOIj

CS2
TPEN
APORT
TPAPCE
TPSQEL
TPFULDL
LOOP

~a:

....w~

Mode
Select

TPJABB

Analog and Interface Integrated Circuits

TPTX+ TPTX-

TPLIL

4.6-2

TPSQEL

TPRX-

TPRX+ TPPLR

Motorola Master Selection Guide

High Performance Decoder Driver/Sink Driver
K1

MC34142DW, FN

~to-----------.

..r-,--I:-:;O-::::-:::-:""-~

+H
I

Data In

I

15 I

F..;..UI_ID..,l<:JH-__- t1 Duplex Mode
17'
Select
"I

Duplex Mode
Select

lNKFl H

!

.

VCC .JO\,.J
~t 12!

Collision Test

IITTLICMOS

Collision
Detect TTL/CMOS
Outputs

t
-. I

I
'--

-II Jabber

CI k

Li~o~~::--

,........,

I

OSci~l~tor

TTL/CMOS

41

~Signal

Quality
Error

I 14
I

r- I
•

Gnd

Motorola Master Selection Guide

10 MHz

4.6--3

13 JABB H

I
I
I 22 SQE EN l

TTL/CMOS

I+--t>o-----~
I

L--71-r_19r5-----2&~23~r--------.J
ANA
DIG
CLI(~ !I~t! ClK- ClK
Gnd -=
-= Gnd
20 pF fff 20 pF Out
PWR

SIA
CTlH

b-'''-----.j

TTL/CMOS

~

Link Fail Disable

2knl

-+I

Collision
Announcement

Full Duplex Disable

TXENH

I 4

....---. RX.j

t~ IRX1_61

t

c..s.D~~)l

_

loop l
lOOP:
Back Test

VCC

loop Back
Test Select

5.0 V

~

Duplex
Mode
Select

Analog and Interface Integrated Circuits

Hex EIA-485 Transceiver with Three-State Outputs
MC340S8IS9FTA .
TA = 0° to +70°C, Case 932
The Motorola MC3405819 Hex Transceiver is composed of
six driver/receiver combinations designed to comply with the
EIA-485 standard. Features include three-state outputs,
thermal shutdown for each driver, and current limiting in both
directions. This device also complies with EIA-422 and
CCITT Recommendations V.11 and X.27.
The devices are optimized for balanced multipoint bus
transmission at rates to 20 MBPS (MC34059). The driver
outputsireceiver inputs feature a wide common mode voltage
range, allowing for their use in noisy environments. The
current limit and thermal shutdown features protect the
devices from line fault conditions.
The MC34058/9 is available in a space saving 7.0 mm 48
lead surface mount quad package designed for optimal heat
dissipation.

DE6

• Meets EIA-485 Standard for Party Line Operation
• Meets EIA-422A and CCITT Recommendations V.11 and
X.27
• Operating Ambient Temperature: O°C to +70°C
• Common Mode Driver Output/Receiver Input Range: -7.0
to +12 V
• Positive and Negative Current Limiting
• Transmission Rates to 14 MBPS (MC34058) and 20
MBPS (MC34059)
• Driver Thermal Shutdown at 150°C Junction Temperature
• Thermal Shutdown Active Low Output
• Single +5.0 V Supply, ±10%
• Low Supply Current
• Compact 7.0 mm 48 Lead TQFP Plastic Package
• Skew Specified for MC34059

RE6

DRS

RES

DES

Gnd

36 Gnd

Gnd

35 OAS

OA6

34 OBS

OB6

DR4

DR1

0A4

OA1

OB4

OB1

DE4

DE1

29 RE4

RE1

28 OB3

OB2

10

27 OA3

0A2

11

26 Gnd

Gnd

12

25 Gnd

Gnd

Gnd

Analog and Interface Integrated Circuits

DE2

RE2

RE3

4.~

TSD

Gnd

Motorola Master Selection Guide

5.0 V, 200 M-BitlSec PR-IV Hard Disk Drive Read Channel
MC34250FTA

TA = 0° to +70°C, Case 840F
The Motorola MC34250 is a fully integrated partial
response maximum likelihood disk drive read/write channel
for use in zoned recording applications. This device integrates
the AGC, active filter, 7 tap equalizer, Viterbi detector,
frequency synthesizer, servo demodulator, 8/9 rate (0,4/4)
Encoder/Decoder with write precompensation and power
management in a single 64 pin 10 mm x 10 mm TQFP
package.

• Programmable Asymmetrical Boost of Up to ±40% of
Nominal Filter Group Delay in Both Data and Servo
Modes

FEATURES:

• Fast Acquisition Data Phase locked loop with Zero
Phase Restart

• 7 Tap Continuous Time Transversal Equalizer with 8 Bit
Programmable Tap Weights and Integrated Decision
Directed Sign-Sign least Mean Squared Adaptation
• Internal Offset Cancellation loops

• 50 to 200 MBPS Programmable Data Rate
• Programmable Data Phase locked loop Charge Pump
Current

• 800 mW at 200 MBPS and 5.0 V
• Channel Monitor Output

• Integrated Soft Decision Viterbi Detectors with
Programmable Merge References

• Programmable AGC Charge Pump Currents with
Different Values for Data and Servo Envelope Modes and
Gain Gradient Mode

• Integrated 8/9 Rate (0,4/4) Encoder and Decoder with
Code Scrambler and Descrambler

• Programmable AGC Peak Detector Droop Currents with
Different Values for Data and Servo Envelope Modes

• Programmable 214/8 Bit NRZ Data Interface
• Programmable Write Precompensation Delays locked to
the Frequency Synthesizer

• Separate AGC Charge Pump Outputs for Data and Servo
Modes

• Differential PECl Write Data Outputs
• Programmable Dual Threshold Qualifier or Hysteresis
Comparator Type Pulse Detector for Servo Data
Detection.

• External Write Data Path for DC Erase or Other
Non-Encoded Data

• ERD and Polarity Outputs for Servo Timing and Raw
Encoded Data

• Integrated Write Current DAC

• Integrated 7 pole 0.05° Equiripple Linear Phase Filter with
Programmable Bandwidth from 5.0 MHz to 80 MHz and
Different Values for Both Data and Servo Modes

• Bi-Directional Serial Microprocessor Interface

• Programmable Power Management

• Various Test Modes Controlled Via the Serial
Microprocessor Interface

• Programmable Symmetrical Boost from 0 to 10 dB and
Different Values for Data and Servo Modes

Motorola Master Selection Guide

4.6-5

Analog and Interface Integrated Circuits

»
:J

(f)

!!!.

:g

0

'".,

<
0

Gl

(f)

:z
]23

O

:J

C-

.,~

(f)

(f)

:D

0
.-

m

'"

'"

-u

s::

ttl

ttl

:D

:D

(f)

(f)

(f)

:IJ(J")cn-l-l

CD

ttl

(f)

(f)

:D

(II

b

:D

.....

~
.....
~ ~ .....
-u

~

<:D;gS2Q I

~

I

CDATA~ Mux
CSRVO

8/9 (0,4/4) ENDEC
Synchronization
Byte Detect

h

SYNCDET ~
NRZ(7:0)
C
NRZCLK
~.
READGT
WRITEGT :D
CD
WRITECLK I»

...

C.

0

:::r
I»
::l
::l

Write
Precompensation
SLEEPB U

s:

~

aiii"

s:

irn

I

I

~I

FREF~

Power
Manager

Fre:J,Uency
Synt esizer

g

~

Mode

0

:J

G)

"c:
CD

I

(f)

(f)

I

I

-<
:z
.....
-n
-u

-<
:z
.....
-n

s::

WDATAM

SLATCH
ZoneClk

WCDAC
Data

MCU Interface

J~

::;:
0

z

I
CD

::;:
0

(f)

m

:z
(f)
m

:E
:D
:::;
m

~

c;-

0

:::J

S·
r:::

Coefficients

CD
ii)

g..

WDATAP

tj:gSDATA
SCLK

CD

.s

Line Receivers
Table 1. EIA Standard
S= Single
Ended
D= Differential

Type
of
Output

tprop
Delay
Time
Max (ns)

Party
Line
Operation

Strobe
or
Enable

Power
Supplies
(V)

S

TP

4000

-

-

+5.0

R(1)

85

-

-

MC1489
MC1489A

TP

30

V

V

AM26LS32

PC/648

AM26LS31

MC3486

P/648,
D/751B

MC3487

SN75173
SN75175

N/648,
D/751B

MC75174B

S,D

35

Device

Suffix!
Package

MC14C89B,
AB

P/646,
D/751 A

Receivers
Per
Package

Companion
Drivers
MC1488
MC14C88B

4

Comments
EIA-232-DI
EIA-562
EIA-232-D
EIA-422/423

EIA-422/4231
485

(1) R = Resistor Pull-up, TP = Totem-pole output.

Line Drivers
Table 2. EIA Standard
Output
Current
Capability
(mA)

t prop
Delay
Time
Max (ns)

S= Single
Ended
D= Differential

Party
Line
Operation

Strobe
or
Enable

Power
Supplies

(V)

85

35

D

V

V

+5.0

48

20

15

3500

10

350

60

300

-

S

EIA422 t/
EIA423 -

SID

Device

Suffix!
Package

Drivers
Per
Package

MC75174B

P/648

4

MC3487

P/648,
D1751B

AM26LS31

PC/648

MC26LS31

D1751B

±7.0to
±12

MC14C88B

P/646,
D1751 A

±9.0to
±12

MC1488

±5.0

AM26LS30

PC/648

MC26LS30

D1751B

2 (422)
4(423)

Companion
Receivers

Comments

SN75173
SN75175

EIA-485

MC3486
AM26LS32

EIA-422
with 3-state
outputs

MC14C89B
MC14C89AB

EIA-232-DI
EIA-562

MC1489
MC1489A

EIA-232-D

AM26LS32
MC3486

EIA-422or
EIA-423
Switchable

Table 3. Line Transceivers
Driver
Prop
Delay
(Max ns)

Receiver
Prop
Delay
Max (ns)

20

30

23

23

DE=Driver
Enable
RE =Receiver
Enable
DE,RE

Party
Line
Operation

Power
Supplies

V

+5.0

(V)

Device
MC34050

Drivers
Per
Package

Receivers
Per
Package

D1751B,
P/648

2

2

EIA-4221423

Suffix!
Package

EIA
Standard

DE

MC34051

DE,RE

MC34058

FTAl932

6

6

EIA-485
to 14MBPS

MC34059

FTAl932

6

6

EIA-485
to 20 MBPS

Motorola Master Selection Guide

4.6-7

Analog and Interface Integrated Circuits

Table 4. EIA-232-EIV.28 CMOS Drivers/Receivers
Device
MC145403
MC145404

Suffix!
Package
pn38,
DWn51D

Pins

Drivers

Receivers

Power
SuppUes(V)

20

3

5

±5.0to±12

MC145405

4

4

5

3

MC145406

P/648,
DWn51G,
SD/940B

16

MC145407

pn38,
DWn51D

20

MC145408

pn24,
DWn51E,
SD/940B

24

5

5

±5.0 to±12

MC145583

DWn51F,
VF/940J

28

3

5

+3.3 to +5.0

MC145705

pn38,
DWn51D

20

2

3

+5.0

pn24,
DWn51E

24

MC145706
MC145707

Features

3

+5.0

Charge Pump

On-board ring monitor circuit;
charge pump, power down
Charge Pump, Power Down

2

3

3

Table 5. Peripheral Drivers
Output
Current
Capability
(rnA)
500

Input
Capability

Propagation
Delay Time
Max (Ils)

Output
Clamp
Diode

Off State
Voltage
Max (V)

TTL,CMOS

1.0

V

50

6.0Vt015V
MOS

Device
ULN2803

Drivers
Per
Package

Suffix!
Package

Logic
Function

8

An07

Invert

7

P/648,
Dn51B

ULN2804

TTl,5.0V
CMOS

MC1413, B
(UlN2003A)

8.0Vt018V
MOS

MC1416,B
(UlN2004A)

Table 6. IEEE 802.3 Transceivers
Device

Power
Supply

MC34055

+5.0Vdc

Suffix!
Package

10 BaseT

NRZ

IEEE

Transmit and
Receive over
4 Pins

Raised
ECl,
CMOS

802.3 Type
10BaseT

Transceiver with non-return to zero (NRZ)
interface. Intended for but not restricted to
concentrators and repeator applications.

DW/751E

TTl,CMOS

802.3 Type
10BaseTI
AUI/NRZ

Interfaces gluelessly to Motorola's MC68360
communications controller.

FBl848D

MC68160

Comments

ReadIWrite Channel
Table 7. Hard Disk Drive Read Channel
Device
MC34250

Power
Supply
5.0V

Comments
200 Mbps fully integrated partial response maximum likelihood hard disk
drive read/write channel which equalizes to a PR-IV shape and uses 8/9
rate (0, 4/4) coding.

Analog and Interface Integrated Circuits

4.6-8

TA
(DC)

Suffix!
Package

Oto+70

FTAl840F

Motorola Master Selection Guide

CMOS Display Drivers
range of end equipment such as instruments, automotive
dashboards, home computers, appliances, radios and clocks.

These CMOS devices include digit as well as matrix drivers
for LEOs, LCOs, and VFOs. They find applications over a wide

Table 8. Display Drivers
Display Type
LCD
(Direct Drive)

MuxedLCD
(1/4 Mux)

LED,
Incandescent,
Fluorescent(l )

Muxed LED
(l/4Mux)
Muxed LED
(1/5 Mux)

Input Format

Drive Capability
Per Package

On-Chip
Latch

Display Control

Segment Drive
Current

Device

Parallel BCD

7 Segments

V

Blank

=1.0mA

MC14543B

Blank, Ripple Blank

MC14544B
20 !JA

MC145453

Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUsj

33 Segments
or Dots
48 Segments
or Dots

=200 !JA

MC145000

Parallel BCD

7 Segments

MC145001

44 Segments
or Dots
Blank, Lamp Test

25 rnA

Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUsj

4 Digits +
Decimals

-

Blank

65 rnA

MC14547B

V

Oscillator
(Scanner)

50 rnA
(Peak)

MC14499

Oscillator (Scanner),
Low Power Mode,
Dimming

Ot035mA
(Peak)
Adjustable

MC14489

10mA(2)

MC14495-1

-

MC14558B

5 Characters +
Decimals or 25
Lamps

LED
(Direct Drive)

Parallel Hex

7 Segments +
A thru F Indicator

(Interfaces to
Display Drivers)

Parallel BCD

7 Segments

MC14511B
MC14513B

Blank, Ripple Blank,
Lamp Test

-

Ripple Blank,
Enable

(1) Absolute maximum working voltage = 18 V.
(2) On--<:hip current-limiting resistor.

Table 9. Functions
Device
MCl4489

Function

Package

Multi-Character LED Display/Lamp Driver

738,7510
648,751G

MC14495-1

Hexadecimal-to-7 Segment Latch/Decoder ROM/Driver

MC14499

4-Digit 7-Segment LED Display Decoder/Driver with Serial Interface

707,7510

MC14511B

BCD-to-7-Segment Latch/Decoder/Driver

648,751G

MC14513B

BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking

MC14543B

BCD-to-7-Segment Latch/Decoder/Driver for Liquid Crystals

620,648

MC14544B

BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking

726, 707

MC14547B

High-Current BCD-to-7-Segment Decoder/Driver

620,648

MC14558B

BCD-to-7-Segment Decoder

620,648

726,707

MC145000

48-Segment Serial Input Multiplexed LCD Driver (Master)

709, 776

MC145001

44-Segment Serial Input Multiplexed LCD Driver (Slave)

707, 776

MC145453

33-Segment, Non-Multiplexed LCD Driver with Serial Interface

711,777

Motorola Master Selection Guide

4.6-9

Analog and Interface Integrated Circuits

Interface Circuits Package Overview

- • - - - CASE 620

CASE 646
P SUFFIX

CASE 648
N, P, PC SUFFIX

CASE 707
A SUFFIX

CASE 709
PSUFFIX

CASE 724
PSUFFIX

CASE 726

CASE 738
PSUFFIX

CASE 711
PSUFFIX

CASE 751A
o SUFFIX

CASE 7510
OW SUFFIX

CASE 751B
o SUFFIX

• •
• •

CASE 751E
OW SUFFIX

CASE 751G
OW SUFFIX

CASE 776
FNSUFFIX

CASE 777
FNSUFFIX

CASE 8480
FB SUFFIX

CASE 932
FTASUFFIX

CASE 940B
SO SUFFIX

Analog and Interface Integrated Circuits

•

4.6-10

CASE 751F
OW SUFFIX

•

CASE 840F
FTASUFFIX

CASE 940J
VFSUFFIX

Motorola Master Selection Guide

Communication Circuits

In Brief . ..
RF

Page
RF Communications ................................... 4.7-2
Wideband IFs ...................................... 4.7-2
Wideband Single Conversion Receivers ............... 4.7-2
Narrowband Single Conversion Receivers ............. 4.7-2
Narrowband Dual Conversion Receivers ............... 4.7-3
Universal Cordless Phone Subsystem ICs ............. 4.7-3
Transmitters ....................................... 4.7-3
Balanced Modulator/Demodulator ..................... 4.7-4
Infrared Transceiver ................................ 4.7-4
Telecommunications .................................. 4.7-11
Subscriber Loop Interface Circuit .................... 4.7-11
PBX Architecture (Analog Transmission) .............. 4.7-12
PCM Mono-Circuits ............................ 4.7-12
Dual Tone Multiple Frequency Receiver ............ 4.7-15
ISDN Voice/Data Circuits ........................... 4.7-15
Integrated Services Digital Network ............... 4.7-15
Second Generation U-Interface Transceivers ...... 4.7-16
Second Generation SIT-Interface Transceivers ..... 4.7-16
Dual Data Link Controller ........................ 4.7-17
Voice/Data Communication (Digital Transmission) ...... 4.7-18
Universal Digital Loop Transceiver . . . . . . . . . . . . . . .. 4.7-18
ISDN Universal Digital Loop Transceiver II ......... 4.7-19
Electronic Telephone Circuit ......................... 4.7-19
Tone Ringers ..................................... 4.7-20
Speech Networks ................................. 4.7-21
Speakerphones ................................... 4.7-25
Voice Switched Speakerphone Circuit ............. 4.7-25
Voice Switched Speakerphone with
IlProcessor Interface ........................... 4.7-27
Voice Switched Speakerphone Circuit ............. 4.7-28
Family of Speakerphone ICs ..................... 4.7-29
Telephone Accessory Circuits ....................... 4.7-30
Audio Amplifier ................................. 4.7-30
Current Mode Switching Regulator ................ 4.7-30
300 Baud FSK Modems ......................... 4.7-31
ADPCM Transcoder ............................ 4.7-31
Calling Line Identification (CLlD) Receiver ......... 4.7-32
CVSD ModulatorlDemodulator ................... 4.7-33
Summary of Bipolar Telecommunications Circuits ... 4.7-34
Phase-Locked Loop Components ...................... 4.7-36
PLL Frequency Synthesizers ........................ 4.7-36
Phase-Locked Loop Functions ...................... 4.7-37
Package Overview ................................... 4.7-39

Radio communication has greatly expanded its scope in the
past several years. Once dominated by public safety radio, the
30 to 1000 MHz spectrum is now packed with personal and low
cost business radio systems. The vast majority of this
equipment uses FM or FSK modulation and is targeted at short
range applications. From mobile phones and VHF marine
radios to garage door openers and radio controlled toys, these
new systems have become a part of our lifestyle. Motorola
Analog has focused on this technology, adding a wide array of
new products including complete receivers processed in our
exclusive 3.0 GHz MOSAIC® 1.5 process. New surface mount
packages for high density assembly are available for all of
these products, as well as a growing family of supporting
application notes and development kits.
Telephone & Voice/Data
Traditionally, an office environment has utilized two
distinctly separate wired communications systems:
telecommunications and data communications. Each had its
individual hardware components complement, and each
required its own independent transmission line system: twisted
wire pairs for Telecom and relatively high priced coaxial cable
for Datacom. But times have changed. Today, Telecom and
Datacom coexist comfortably on inexpensive twisted wire pairs
and use a significant number of components in common. This
has led to the development and enhancement of PBX (Private
Branch Exchanges) to the point where the long heralded
"office of the future," with simultaneous voice and data
communications capability at each station, is no longer of the
future at all. The capability is here today!
Motorola Semiconductor serves a wide range of
requirements for the voice/data marketplace. We offer both
CMOS and Analog technologies, each to its best advantage,
to upgrade the conventional analog voice systems and
establish new capabilities in digital communications. Early
products, such as the solid-state single--chip crosspoint
switch, the more recent monolithic Subscriber-LoopInterface Circuit (SLlC), a single--chip CodeC/Filter (MonoCircuit), the Universal Digital Loop Transceivers (UDLT),
basic rate ISDN (Integrated Services Digital Network), and
single--chip telephone circuits are just a few examples of
Motorola leadership in the voice/data area.

Motorola Master Selection Guide

4.7-1

Analog and Interface Integrated Circuits

RF Communications
Table 1. Wideband (FMlFSK) IFs

IF

Mute

RSSI

Max
Data
Rate

V

2.0Mb

Wideband Data IF, includes
datashaper

P/648,
DnS1B

10Mb

Video Speed FM IF

Dn51B

Device

Vee

ICC

Sensitivity
(Typ)

MC13055

3-12 V

25mA

20llV

40 MHz

V

MC13155

3-6 V

7.0mA

IOOIlV

250 MHz

-

Notes

Suffix!
Package

Table 2. Wideband Single Conversion Receivers - VHF

Device

Vee

ICC

Sensitivity
(Typ)

MC33S6

3-9 V

2SmA

30llV

200 MHz

10.7MHz

V

MC13156

2-£ V

5.0mA

2.01lV

500 MHz

21.4MHz

-

MC13158

2-£ V

6.0mA

RF
Input

IF

Mute

RSSI

Max
Data
Rate

Notes

V

500 kb

Includes front end mixer/L.O.

pn38,
DWn51D

CT-2 FM/Demodulator

DWn51E,
FB/873

FM IF/Demodulator with
split IF for DECT

FTB/873

>1.2Mb

Suffix!
Package

Table 3. Narrowband Single Conversion Receivers - VHF

Vee

ICC

12 dB
SINAD
Sensitivity
(Typ)

MC3357

4-8 V

5.0mA

5.01lV

MC3359

4-9 V

7.0mA

2.01lV

MC3361C

2-8 V

6.0mA

Device

RF
Input

IF

Mute

RSSI

Max
Data
Rate

45 MHz

455 kHz

V

-

>4.8kb

60 MHz

V

MC3371

Ceramic Quad
Detector/Resonator

P/648,
Dn51B

Scan output option

pn07,
DWnS1D

Lowest cost receiver

P648,
Dn51B

>4.8kb

RSSI

P/648,
Dn51B

RSSI, Ceramic Quad
Detector/Resonator
3-6 V

1.8mA

1.01lV

500 MHz

V

Suffix!
Package

>2.4 kb

MC3372, A
MC13150

Notes

>9.6 kb

Coilless Detector with
Adjustable Bandwidth

FTB/873,
FTA/977

110
dB

Analog and Interface Integrated Circuits

4.7-2

Motorola Master Selection Guide

RF Communications

(continued)

Table 4. Narrowband Dual Conversion Receivers - FM/FSK - VHF

Device

VCC

ICC

12dB
SINAD
Sensitivity
(Typ)

MC3362

2-7 V

3.0mA

0.7~V

4.0mA

0.4 ~V

MC3363

MC3335

0.7~V

MC13135

1.0~V

RF
Input

IFl

180
MHz

10.7
MHz

IF2
(Limiter
In)

Mute

RSSI

455 kHz

-

V

Data
Rate
> 4.8
kb

r---V

r----

-

Notes

Suffix!
Package

Includes buffered
VCOoutput

Pf724,
DWf751E

Includes RF
amp/mute

DWf751F

Low cost version

DWf751D,
Pf738

Voltage buffered
RSSI, LC Quad
Detector

DWf751E,
P/724

Voltage Buffered
RSSI, Ceramic
Quad Detector

MC13136

Table 5. Universal Cordless Phone Subsystem ICs

Device

VCC

ICC

MC13109

2.0--5.5 V

Active Mode
6.7mA
Inactive Mode

MC13110

2.7-5.5 V

Active Mode
8.2mA
Inactive Mode

MC13111

2.7-5.5 V

Active Mode
8.2mA
Inactive Mode

Voice
Scrambler

Low
Battery
Detect

Programmable
Rx. Tx Trim Gain
and LBO Voltage
Reference

V

-

1

-

FB/848B,
FTAl932

V

V

V

2

V

FB/848B

V

V

-

2

V

FB/848B

Dual
Conversion
Receiver

Universal
DualPLL

V

V

V

V

Compander
and Audio
Interface

Suffix!
Package

40~A

60~

60~

Table 6. Transmitters - AM/FM/FSK
MaxRF
Freq
Out

Max
Mod
Freq

Notes

Suffix!
Package

Device

VCC

ICC

Pout

MC2833

3--8 V

10mA

--30 dBm
to
+10dBm

150 MHz

50 kHz

FM transmitter. Includes two frequency
multiplier/amplifier transistors

P/648,
Df751B

MC13175

2-5 V

40mA

8.0dBm

500 MHz

5.0 MHz

AM/FM transmitter. Single frequency PLL
fout = 8 x fref, includes power down function

Df751B

MC13176

Motorola Master Selection Guide

1.0GHz

fout = 32 x fref, includes power down function

4.7--3

Analog and Interface Integrated Circuits

Table 7. Balanced Modulator/Demodulator
Device

Vce

lec

MC1496

3-5 V

lOrnA

Suffix!
Package

Function
General purpose balanced modulator/demodulator for AM, SSB, FM detection
with Carrier Balance >50 dB

P/646,
0/751 A

Table 8. Infrared Transceiver
12 dB
SINAD
Sensitivity
Device

Vee

Ice

(Typ)

MC13173

3-5 V

6.5 rnA

5.01lV

Max
IF Freq
10.7
MHz

Carr Del

RSSI

Data
Rate

V

V

200 kb

Suffix!
Package

Notes
Includes Single Frequency
PLL for Tx Carrier and Rx Lo

FTBl873

Universal Cordless Telephone Subsystem IC
Me13109FB, FTA
TA

=_40° to +85°C, Case 848B, 932

The MC131 09 integrates several of the functions required
for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space
requirements, and external adjustments. It is designed for use
in both the handset and the base.

• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with No
External Switches
- Universal Design for Domestic and Foreign CT-1
Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector,
and 14-Bit Programmable Counter and 2nd LO with
12-Bit Counter
- Transmit Section Contains Phase Detector and 14-Bit
Counter
- MPU Clock Output Eliminates Need for MPU Crystal

• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna Input
to Audio Output 80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic
Discriminator
• Compander

• Supply Voltage Monitor
- Externally Adjustable Trip Point
• 2.0 to 5.5 V Operation with One-Third the Power
Consumption of Competing Devices

- Expandor Includes Mute, Digital Volume Control and
Speaker Driver
- Compressor Includes Mute, ALC and Limiter

Rxln---

Rx
Out
Carrier
Detect

Data
Out

Tx In

SPI

Tx Out
Low
Battery
Indicator

Tx VCO

Analog and Interface Integrated Circuits

4.7-4

Motorola Master Selection Guide

Universal Cordless Telephone Subsystem IC with Scrambler
MC13110FB
TA = -40° to +85°C, Case 848B
The MC1311 0 integrates several of the functions required
for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space
requirements, and external adjustments. It is designed for use
in both the handset and the base.

• Dual Universal Programmable PLL
- Supports New 25 Channel U.S. Standard with New
External Switches
- Universal Design for Domestic and Foreign CT-1
Standards
- Digitally Controlled Via a Serial Interface Port
- Receive Side Includes 1st LO VCO, Phase Detector,
and 14-Bit Programmable Counter and 2nd LO with
12-Bit Counter
- Transmit Section Contains Phase Detector and 14-Bit
Counter
- MPU Clock Outputs Eliminates Need for MPU Crystal

• Dual Conversion FM Receiver
- Complete Dual Conversion Receiver - Antenna In to
Audio Out 80 MHz Maximum Carrier Frequency
- RSSI Output
- Carrier Detect Output with Programmable Threshold
- Comparator for Data Recovery
- Operates with Either a Quad Coil or Ceramic
Discriminator

• Supply Voltage Monitor
- Provides Two Levels of Monitoring with Separate
Outputs
- Separate, Adjustable Trip Points

• Compander
- Expandor Includes Mute, Digital Volume Control,
Speaker Driver, 3.5 kHz Low Pass Filter, and Programmable Gain Block
- Compressor Includes Mute, 3.5 kHz Low Pass Filter,
Limiter, and Programmable Gain Block

• Frequency Inversion Scrambler/Descrambler
- Can Be Enabled/Disabled Via MPU Interface
- Programmable Carrier Modulation Frequency
• 2.7 to 5.5 V Operation with One-Third the Power
Consumption of Competing Devices

Rxln
Rx PO Out
Rx
Out

Rx PO In
Carrier
Detect
Tx In
Tx Out

Low
Battery
Indicator

Tx VCO

Motorola Master Selection Guide

4.7-5

Analog and Interface Integrated Circuits

Narrowband FM Receiver
MC13135/136P,

ow

TA = -40° to +85°C, Case 724, 751E
The MC13135 is a full dual conversion receiver with
oscillators, mixers, Limiting IF Amplifier, Quadrature
Discriminator, and RSSI circuitry. It is designed for use in
security systems, cordless phones, and VHF mobile and
portable radios. Its wide operating supply voltage range and
low current make it ideal for battery applications. The
Received Signal Strength Indicator (RSSI) has 65 dB of
dynamic range with a voltage output, and an operational
amplifier is included for a dc buffered output. Also, an

improved mixer third order intercept enables the MC13135 to
accommodate larger input signal levels.
• Complete Dual Conversion Circuitry
• Low Voltage: 2.0 to 6.0 Vdc
• RSSI with Op Amp: 65 dB Range
• Low Drain Current: 3.5 mA Typical
• Improved First and Second Mixer 3rd Order Intercept
• Detector Output Impedance: 25 n Typically

Vee

"f 0.t

..

RFin

Audio
Ol!lPut

RSSI
Output

o

Analog and Interface Integrated Circuits

4.7-6

455kHz
Quad Coil
Toko
7MC-0
vDD
V)

.----(j>--t"-:-------t--:-----:----------;-;::-=;:j-~>-=-::::;'"""--:--n-------;:::::;-~-t::>>::-::-~>t,...,.=>~>~:-?!:.,.-:::>

L

>.---".-(;14-- VDG

(Dig. Gnd

r-'........()oo- PDI/8T2

:t~::~~~~~~:l~!=l===~~~~~~~~~~Ff~~Ff~::~F=::~~

"""'.-.,-()01>---

I'

8T1
VAG
(Ana. Gnc

>'-;:::::;:!=;:t:!=t--"9">--.:>:-......--o----l~

TXO

W-~:.::~=~~>-.

RFO

RXI

,-:--'-.....,..-'::--'::-"---'--'-'"""""'"'0-- CF

~6-!:======::::!======~~--_.:.~--"'--....J.
.. >'.
_ _ .i....:. _ _ _ _ _ _ _
____
_ _ _ _ _ _ _ :.;;..i....:..i....:..:,,;,,>
..i....:.>.:.;;. _____ JI
~

~_.

(Battery)
, Indica1es Trimmed Resistor

Motorola Master Selection Guide

4.7-11

Analog and Interface Integrated Circuits

PBX Architecture (Analog Transmission)
PCM Mono-Circuits Codec-Filters (CMOS LSI)
MC145500 Series

MC145554/57/64/67

Case 648, 708, 751G, 776
The Mono-circuits perform the digitizing and restoration of
the analog signals. In addition to these important functions,
Motorola's family of pulse-code modulation mono-circuits
also provides the band-limiting filter functions - all on a single
monolithic CMOS chip with extremely low power dissipation.
The Mono-circuits require no external components. They
incorporate the bandpass filter required for antialiasing and
60 Hz rejection, the AlD-D/A conversion functions for either
U.S. Mu-Law or European A-Law companding formats, the
low-pass filter required for reconstruction smoothing, an
on-board precision voltage reference, and a variety of options
that lend flexibility to circuit implementations. Unique features
of Motorola's Mono-circuit family include wide power supply
range (6.0 to 13 V), selectable on-board voltage reference
(2.5, 3.1, or 3.8 V), and TIL or CMOS I/O interface.
Motorola supplies three versions in this series. The
MC145503 and MC145505 are general-purpose devices in
16 pin packages designed to operate in digital telephone or
line card applications. The MC145502 is the full-feature
device that presents all of the options available on the chip.
This device is packaged in a 22 pin DIP and 28 pin chip carrier
package.

Case 648, 7510, 751G, 738
These per channel PCM Codee-Filters perform the voice
digitization and reconstruction as well as the band limiting and
smoothing required for PCM systems. They are designed to
operate in both synchronous and asynchronous applications
and contain an on-chip precision voltage reference. The
MC145554 (Mu-Law) and MC145557 (A-Law) are general
purpose devices that are offered in 16 pin packages. The
MC145564 (Mu-Law) and MC145567 (A-Law), offered in 20
pin packages, add the capability of analog loop-back and
push-pull power amplifiers with adjustable gain.
All four devices include the transmit bandpass and receive
lowpass filters on-chip, as well as active RC pre-filtering and
post-filtering. Fully differential analog circuit design assures
lowest noise. Performance is specified over the extended
temperature range of -40° to +85°C.
These PCM Codec-Filters accept both industry standard
clock formats. They also maintain compatibility with
Motorola's family of MC3419/MC33120 SLiC products.

Txl------,
TOC

- Tx
+ Tx

TOE
TOO

VAG

CCI
MSI

RXO

RSI
Vref

RxG ....- -.....
ROD
RxO

VSSVOO-

Analog and Interface Integrated Circuits

MC145480P, OW, SO
Case 738, 7510, 940C
This 5.0 V, general purpose per channel PCM Codec-Filter
offers selectable Mu-Law or A-Law companding in 20 pi n 01 P,
SOG and SSOP packages. It performs the voice digitization
and reconstruction as well as the band limiting and smoothing
required for PCM systems. It is deSigned to operate in both
synchronous and asynchronous applications and contains an
on-chip precision reference voltage (1.575 V).
The transmit bandpass and receive lowpass filters, and the
active RC pre-filtering and post-filtering are incorporated, as
well as fully differential analog circuit design for lowest noise.
Push-pull 300 n power drivers with external gain adjust are
also included.
The MC145480 PCM Codec-Filter accepts a variety of
clock formats, including short-frame sync, long-frame sync,
IDL, and GCI timing environments. This device also maintains
compatibility with Motorola's family of Telecom products,
including the
MC145472
U-Interface Transceiver,
MC145474175 SIT-Interface Transceiver, MC145532
ADPCM Transcoder, MC145422126 UDLT-I, MC145421/25
UDLT-II, and MC3419/MC33120 SLiC.

RCE

----

ROC
POI
MulA
VLS

4.7-12

Motorola Master Selection Guide

PBX Architecture (continued)
MC14LC5540P, OW, FU

Case 710, 751F, 873
The MC14LC5540 ADPCM Codec is a single chip
implementation of a PCM Codec-Filter and an ADPCM
encoder/decoder, and therefore provides an efficient solution
for applications requiring the digitization and compression of
voiceband signals. This device is designed to operate over a
wide voltage range, 2.7 V to 5.25 V, and as such is ideal for
battery powered as well as ac powered applications. The
MC14LC5540 ADPCM Codec also includes a serial control
port and internal control and status registers that permit a
microcomputer to exercise many built-in features.

The ADPCM Codec is designed to meet the 32 kbps
ADPCM
conformance
requirements
of
CCITT
Recommendation G.721 (1988) and ANSI T1.301 (1987). It
also meets ANSI T1.303 and CCITT Recommendation G.723
for 24 kbps ADPCM operation, and the 16 kbps ADPCM
standard, CCITT Recommendation G.726. This device also
meets the PCM conformance specification of the CCITT
G.714 Recommendation.

Figure 25. MC14LC5540 ADPCM Codec Block Diagram

Motorola Master Selection Guide

4.7-13

Analog and Interface Integrated Circuits

PBX Architecture (continued)
MC145537EVK
ADPCM Codec Evaluation Kit
The MC145537EVK is the primary tool for evaluation and
demonstration of the MC14LC5540 ADPCM Codec. It
provides the necessary hardware and software interface to
access the many features and operational modes of the
MC14LC5540 ADPCM Codec.
• Provides Stand Alone Evaluation on Single Board
• The kit provides Analog-ta-Analog, Analog-to-Digital or
Digital-to-Analog Connections - with Digital Connections
being 64 kbps PCM, 32 or 24 kbps ADPCM, or 16 kbps
CCITT G.726 or Motorola Proprietary ADPCM
• +5.0 V Only Power Supply, or 5.0 V Plus 2.7 to 5.25 V
Supply

• Easily Interfaced to Test Equipment, Customer System,
Second MC145537EVK or MC145536EVK (5.0 V Only)
for Full Duplex Operation
• Convenient Access to Key Signals
• Piezo Loudspeaker
• EIA-232 Serial Computer Terminal Interface for Control
of the MC14LC5540 ADPCM Codec Features
• Compatible Handset Provided
• Schematics, Data Sheets, and User's Manual Included

Figure 26. MC145537EVK Block Diagram
+5.0 V

- r-

-Gnd

r-

+3.0 V

--

I~I~I~I

Piezo
Speaker

Clock Generation
Circuitry

I

1
5.0 V/3.0 V
Level Shift

I

MC145407
EIA-232 Driver/Receiver

1
Analog
Interface

MC14LC5540
ADPCMCodec

Analog and Interface Integrated Circuits

CIocks

EI A-232

I

SCI

3.0 V/5.0 V
Level Shift
5.0 V/3.0 V

4.7-14

MC68HC705C8
Microcontrolier

Motorola Master Selection Guide

PBX Architecture (continued)
MC145536EVK

ISDN Voice/Data Circuits

Codeo-Filter/ADPCM Transcoder Evaluation Kit
The MC145536EVK is the primary tool for evaluation and
demonstration of the MC145480 Single +5.0 V supply PCM
Codeo-Filter and the MC145532 ADPCM Transcoder (see
"Telephone Accessory Circuits"). The MC145536EVK
provides the necessary hardware needed to evaluate the
many separate operating modes under which the MC145480
and MC145532 are intended to operate.
• Provides Stand Alone Evaluation on a Single Board
• Easily Interfaced to Test Equipment, Customer System,
or Second MC145536EVK
• Convenient Access to Key Signals
• Generous Wire-Wrap Area for Application Development
• The kit provides Analog-to-Analog, Analog-to-Digital, or
Digital-to-Analog Connections - with Digital Connections
Being 64 kbps PCM; 32, 24, or 16 kbps
Motorola Proprietary ADPCM
• Compatible Handset Included
• Schematics, Data Sheets, and User's Manual included

r--------------,
I
I
I
I
I
I

Clocks

Analog
Interlace

Digital
Interlace

I
I
___________ _
IL _
MC145536EVK

Integrated Services Digital Network
ISDN is the revolutionary concept of converting the present
analog telephone networks to an end-to-end global digital
network. ISDN standards make possible a wide variety of
services and capabilities that are revolutionizing
communications in virtually every industry.
Motorola's ISDN product family includes the MC14LC5472
and MC145572 U-Interface Transceivers, the MC145474/75
and MC145574 SIT-Interface Transceivers, MC145488 Dual
Data Link Controller, and the MC68302 Integrated
Multi-Protocol Processor. These are supported by a host of
related devices including the MC145480 +5.0 V PCM
Codeo-Filter, MC145532 ADPCM Transcoder, MC14LC5540
ADPCM Codec, MC145500 family of single-chip
codec/filters, MC145436A DTMF Decoder, MC33120
Subscriber.Loop Interface Circuit, MC34129 Switching Power
Supply Controller, and the MC145406/07 CMOS EIA 232-E
Driverl Receiver family.
Motorola's key ISDN devices fit into four ISDN network
applications: a digital subscriber line card, an NT1 network
termination, an ISDN terminal adapter, and an ISDN terminal.
Digital subscriber line cards are used in central offices, remote
concentrators, channel banks, T1 multiplexers, and other
switching equipment. The NT1 network termination block
illustrates the simplicity of remote U- to SIT-interface
conversion. The ISDN terminal adapter and ISDN terminal
block show how Motorola ICs are used to combine voice and
data in PC compatible boards, digital telephones, and other
terminal equipment. Expanded applications such as a PBX
may include these and other Motorola ISDN circuits. Many
"non-ISDN" uses, such as pairgain applications, are
appropriate for Motorola's ISDN devices as well.

Dual Tone Multiple Frequency Receiver
MC145436AP,

ow

Case 646, 751G
This device contains the filter and decoder for detection of
a pair of tones conforming to the DTMF standard with outputs
in hexadecimal. Switched capacitor filter technology is used
together with digital circuitry for the timing control and output
circuits. The MC145436A provides excellent power-line noise
and dial tone rejection.
Replaces MC145436P, OW.

Motorola Master Selection Guide

4.7-15

Analog and Interface Integrated Circuits

ISDN Voice/Data Circuits (continued)
standard maintenance channel functions. This flexible feature
also allows for easy implementation of proprietary
maintenance functions.

Second Generation
U-Interface Transceivers
MC145572PB

MC145572FN

Second Generation
SIT-Interface Transceivers

Case 777

MC145574PB

The MC145572 fully conforms to ANSI T1.601-1992, the
North American standard for ISDN Basic Access on a single
twisted-wire pair. The transceiver achieves a remarkable 10-7
bit error rate performance on all ANSI specified test loops with
worst-case impairments present. The state-of-the-art 0.65
micron single-chip solution uses advanced design techniques
to combine precision analog signal processing elements with
three digital signal coprocessors to build an adaptively
equalized echo cancelling receiver.
Two modes of handling U-interface maintenance functions
are provided on the MC145572.ln the automatic maintenance
mode the U-interface transceiver handles all ANSI specified
maintenance and channel procedures internally to minimize
your software development effort. Automatic procedures
include generating and monitoring the cyclic redundancy
check, reporting and counting far end block errors (near end
block errors too), handling the ACT and DEA bits, as well as
monitoring and appropriately responding to embedded
operations channel messages.
The MC145572 has 275 mW maximum power dissipation.
It also has an enhanced TDM interface that supports an
on-chip timeslot assigner, GCI and IDL modes of operation.
The optional manual maintenance mode lets you choose
an inexpensive microcontroller, such as a member of
Motorola's MC68HC05 family, to control and augment the

Case 736B

Case 842D

MC145488

DDLC

TA
MC145574
SCP
IDL

MC145574DW
Case 837A
The MC145574 Srr-Interface Transceivers provide a
CCITT 1.430 compatible interface for use in line card, network
termination, and ISDN terminal equipment applications.
Manufactured with Motorola's advanced 0.65 micron CMOS
mixed analog and digital process technology, the MC145574 is
a physical layer device capable of operating in point-to--point
or poinHo-multipoint passive bus arrangements. In addition,
the MC145574 implements the optional NT1 Star topology, NT
terminal mode and TE slave mode.
This
device
features
outstanding
transmission
performance. It reliably transmits over 1 kilometer in a
point-to-point application. Comparable performance is
achieved in all other topologies as well. Other features include
pin selectable terminal or network operating modes, industry
standard microprocessor serial control port, full support of the
multiframing Sand Q channels, a full range of loopbacks, and
low power CMOS operation, with a maximum power
consumption of 90 mW.
The MC145574 has an enhanced TDM interface that
supports GCI, IDL and an on-chip timeslot assigner.

NT1
MC145574

MC145572
GCI

SfT

SIT
Chip

U
Chip

LT
MC145572
IDL
U
Chip

C
SCP

NT1fTA

e
r

a
I
SfT
Chip

MC68302

LT
MC145572

MC145572
IDL
U
Chip

RS232

Analog and Interface Integrated Circuits

o

SCP

4.7-16

f
f
I

c
e

SCP

Motorola Master Selection Guide

ISDN Voice/Data Circuits

(continued)

Dual Data Link Controller
MC14LC5494EVK
U-Interface Transceiver Evaluation Kit discontinued

MCl45488FN
Case 779
The MC145488 features two full-duplex serial HDLC
channels with an on--chip Direct Memory Access (DMA)
controller. The DMA controller minimizes the number of
microprocessor interrupts from the communications
channels, freeing the microprocessor's resources for other
tasks. The DMA controller can access up to 64 kbytes of
memory, and transfers either 8-bit bytes or 16-bit words to or
from memory. The MC145488 DDLC is compatible with
Motorola's MC68000 and other microprocessors.
In a typical ISDN terminal application, one DDLC
communications channel supports the D--channel (LAP D)
while the other supports the B--channel (LAPS). While the
DDLC is ideally suited for ISDN applications, it can support
many other HDLC protocol applications as well.
Some of the powerful extras found on the DDLC include
automatic abort and retransmit of D--channel collisions in
SIT-interface applications, address recognition, automatic
recovery mechanisms for faulty frame correction, and several
system test modes. Address recognition provides a reduction
in the host microprocessor load by filtering data frames not
addressed to the host. The DDLC can compare either SAPI or
TEl fields of LAPD frames. For LAPD (Q.921) applications,
both A and S addresses may be checked.

MC145572EVK
U-Interface Transceiver Evaluation Kit
This kit provides the hardware and software to evaluate the
many configurations under which the MC145572EVK is able
to operate. Used as a whole, it operates as both ends of the
two-wire U interface that extends from the customer premises
(NT1) to the switch line card (LT). The two halves of the b.o~rd
can be physically and functionally separated, providing
independent NT1 and LT evaluation capability.
The kit provides the ability to interactively manipulate
status registers in the MC145572EVK U-Interface transceiver
or in the MC145474n5 SIT-Interface transceiver with the aid
of an external terminal. The device can also be controlled
using the MC68302 Integrated Multiprotocol Processor
application development system to complete a total Sasic
Rate ISDN evaluation solution.

2B1Q U-lnterface

SIT
Interface

IDL.-

NTI Side

IDL
SIT-Interface
Transceiver
I
MC145474
I
__ -.J

1"" - -SCP

LT Side
U-Interface
Transceiver
MCI45572FN

SCP

Gated
Clocks

L---..!f----t---J.. SCP

MCI45572EVK

Motorola Master Selection Guide

4.7-17

Analog and Interface Integrated Circuits

UDLTs utilize a 256 kilobaud Modified Differential Phase
Shift Keyed (MDPSK) burst modulation technique for
transmission to minimize radio frequency, electromagnetic,
and crosstalk interference. Implementation through CMOS
technology takes advantage of
low-power operation,
increased reliability, and the proven capabilities to perform
complex telecommunications functions.

Voice/Data Communication
(Digital Transmission)
2-Wire Universal Digital Loop
Transceiver (UDLT)
MC145422P,

ow Master Station

Case 708, 751 E
MC145426P, OW Slave Station

Case 708, 751E
The UDLT family of transceivers allows the use of existing
twisted-pair telephone lines (between conventional
telephones and a PBX) for the transmission of digital data.
With the UDLT, every voice-only telephone station in a PBX
system can be upgraded to a digital telephone station that
handles the complex voice/data communications with no
increase in cabling costs.
In implementing a UDLT-based system the AID to D/A
conversion function associated with each telset is relocated
from the PBX directly to the telset. The SLiC (or its equivalent
circuit) is eliminated since its signaling information is
transmitted digitally between two UDLTs.
The UDLT master-slave system incorporates the
modulation/demodulation functions that permit data
communications over a distance up to 2 kilometers. It also
provides the sequence control that govems the exchange of
information between master and slave. Specifically, the master
resides on the PBX line card where it transmits and receives
data over the wire pair to the telset. The slave is located in the
telset and interfaces the mono--circuit to the wire pair. Data
transfer occurs in 1Q-bit bursts (8 bits of data and 2 signaling
bits), with the master transmitting first, and the slave responding
in a synchronized half-duplex transmission format.

Functional Features
• Provides Synchronous Duplex 64 kbitslSecond
Voice/Data Channel and Two 8 kbits/Second Signaling
Data Channels Over One 26 AWG Wire Pair Up to 2 km.
• Compatible with Existing and Evolving Telephone Switch
Architectures and Call Signaling Schemes
• Automatic Detection Threshold Adjustment for Optimum
Performance Over Varying Signal Attenuations
• Protocol Independent
• Single 5.0 V to 8.0 V Power Supply
MC145422 Master UDLT
• 2.048 MHz Master Clock
• Pin Controlled Power-Down and Loop-Back Features
• Variable Data Clock - 64 kHz to 2.56 MHz
• Pin Controlled Insertion/Extraction of 8 kbits/Seconds
Channel into LSB of 64 kbitslSecond Channel for
Simultaneous Routing of Voice and Data Through PCM
Voice Path of Telephone Switch
MC145426 Slave UDLT
• Compatible with MC145500 Series and Later PCM
Mono-Circuits
• Automatic Power-Up/Down Feature
• On-Ghip Data Clock Recovery and Generation
• Pin Controlled 500 Hz D3 or CCITT Format PCM Tone
Generator for Audible Feedback Applications

r ______~U::::DL:.!.J_ _ _....

Signaling Input 1

r------------.-

Signaling Input 2

Line
Driver
Output

Receive Data Input

1-----_

\IaIid.Data.

1 - - - -...._

Power Down
T/R Data Clock

1-----1-- I.oop.Sack-

COnvertCi"ock - -

f-----:

I

I Enab~ _

1----- Tone Enable
XTAL In

+
Master
_Only

Slave
Only

XT~~ _ _ _ _ j_
Transmit Enable
Transmit Data
Signal Output 1
Signal Output 2

Analog and Interface Integrated Circuits

4.7-18

Motorola Master Selection Guide

Voice/Data Communication (Digital Transmission)

(continued)

2-Wire ISDN Universal Digital Loop Transceiver II (UDLT II)
MC145421 P,

ow Master

Similar to the MC145422/26 UDLT, but provide
synchronous full duplex 160 kbps voice and data
communication in a 2B + 2D format for ISDN compatibility on
a single twisted pair up to 1 km. Single 5.0 V power supply,
protocol independent.

Case 709,751 E
MC145425P, OW Slave

Case 709, 751 E

Electronic Telephone
The Complete Electronic Telephone Circuit
MC34010P, FN

TA = -20 to +60°C, Case 711,777
0

The conventional transformer-driven telephone handset is
undergoing major innovations. The bulky transformer is
disappearing. So are many of its discrete components,
including the familiar telephone bell. They are being replaced
with integrated circuits that perform all the major handset
functions simply, reliably and inexpensively ... functions such
as 2-to-4 wire conversion, DTMF dialing, tone ringing, and a
variety of related activities.
The culmination of these capabilities is the Electronic
Telephone Circuit, the MC34010. These ICs place all of the
above mentioned functions on a single monolithic chip.
These telephone circuits utilize advanced bipolar analog
(12L) technology and provide all the necessary elements of a
modem tone-dialing telephone. The MC34010 even
incorporates an MPU interface circuit for the indusion of
automatic dialing in the final system .

• DTMF generator uses low cost ceramic resonator with
accurate frequency synthesis technique
• Tone ringer drives piezoelectric transducer and satisfies
EIA-470 requirements
• Speech network provides 2-t0-4 wire conversion with
adjustable sidetone utilizing an electret transmitter
• On-chip regulator insures stable operation over wide
range of loop lengths
• 12L technology provides low 1.4 V operation and high
static discharge immunity
• Microprocessor interface port for automatic dialing features
Also Available

A broad line of additional telephone components for
customizing systems design.

• Provides all basic telephone functions, including DTMF
dialer, tone ringer, speech network and line voltage
regulator

Hook Switch

//r-~
/

Tip

Ring

MC34010
Electret
Microphone

Motorola Master Selection Guide

4.7-19

Analog and Interface Integrated Circuits

Tone Ringers
circuit MUST function when a ringing signal is provided, and
MUST NOT ring when other signals (speech, dialing, noise)
are on the line. The tone ringers described below were
designed to meet those requirements with a minimum of
external components.

The MC34012, MC34017, and MC34117 Tone Ringers are
designed to replace the bulky bell assembly of a telephone,
while providing the same function and performance under a
variety of conditions. The operational requirements spelled
out by the FCC and EIA-470, simply stated, are that a ringer

MC34012P, D

TA = -20° to +60°C, Case 626, 751
• Complete Telephone Bell Replacement
• On-Chip Diode Bridge and Transient
Protection
• Single-Ended Output to Piezo
Transducer
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial and Hook Switch
Transients
• Adjustable Base Frequencies
• Output Frequency to Warble Ratio MC34012-1:80
MC34012-2:160
MC34012-3:40

Ring >------<:H!::F-<..........

MC34017P, D

TA = -20° to +60°C, Case 626, 751
• Complete Telephone Bell Replacement
• On-Chip Diode Bridge and Transient
Protection
• Differential Output to Piezo Transducer
for Louder Sound
• Input Impedance Signature Meets Bell
and EIA Standards
• Rejects Rotary Dial and Hook Switch
Transients
• Output Frequency to Warble Ratio MC34017-1:80
MC34017-2:160
MC34017-3:40

Analog and Interface Integrated Circuits

Ring

"">-----<
Pieza
Sound
Element

4.7-20

Motorola Master Selection Guide

Tone Ringers

(continued)

MC34217P, D

TA = -20° to +60°C, Case 626, 751
•
•
•
•
•
•
•

•
•

Complete Telephone Bell Replacement
On-Chip Diode Bridge
Internal Transient Protection
Differential Output to Piezo Transducer
for Louder Sound
Input Impedance Signature Meets Bell
and EIA Standards
Rejects Rotary Dial and Hook Switch
Transients
Base Frequency and Warble
Frequencies are Independently
Adjustable
Adjustable Base Frequency
Reduced Number of Externals

Ring ...----4"':":i~"....,'"'

Speech Networks
Telephone Speech Network with Dialer Interface
MC34114P, DW

TA = -20° to +70°C, Case 707,751 D
•
•
•
•

Regulated 1.7 V Output for Biasing Microphone
Regulated 3.3 V Output for Powering External Dialer
Microphone and Receive Amplifiers Muted During Dialing
Differential Receive Amplifier Output Eliminates Coupling
Capacitor
• Operates with Receiver Impedances of 150 Q and Higher

• Operation Down to 1.2 V
• Adjustable Transmit, Receive, and Sidetone Gains by
External Resistors
• Differential Microphone Amplifier Input Minimizes RFI
• Transmit, Receive, and Sidetone Equalization on both
Voice and DTMF Signals

Tip 0-------,

Ring 0--------'

Motorola Master Selection Guide

4.7-21

Analog and Interface Integrated Circuits

Speech Networks

(continued)

Cordless Universal Telephone Interface
MC34016DW, P
TA

=-20° to +70°C, Case 7510, 738

The MC34016 is a telephone line interface meant for use
in cordless telephone base stations for CTO, CT1, CT2 and
DECT. The circuit forms the interface towards the telephone
line and performs ali speech and line interface functions like
dc and ac line termination, 2-4 wire conversion, automatic
gain control and hookswitch control. Adjustment of
transmission parameters is accomplished by two 8 bit
registers accessible via the integrated serial bus interface and
by external components.
• DC Masks for Voltage and Current Regulation
• Supports Passive or Active AC Set Impedance
Applications
• Double Wheatstone Bridge Sidetone Architecture
• Symmetrical Inputs and Outputs with Large Signal Swing
Capability
• Gain Setting and Mute Function for Tx and Rx Amplifiers
• Very Low Noise Performance
• Serial Bus Interface SPI Compatible
• Operation from 3.0 V to 5.5 V

FEATURES
Line Driver Architecture
• Two DC Masks for Voltage Regulation
• Two DC Masks for Current Regulation
• Passive or Active Set Impedance Adjustment

• Double Wheatstone Bridge Architecture
• Automatic Gain Control Function
Transmit Channel
• Symmetrical Inputs Capable of Handling Large Voltage
Swing
• Gain Select Option via Serial Bus Interface
• Transmit Mute Function, Programmable via Bus
• Large Voltage Swing Capability at the Telephone Line
Receive Channel
• Double Sidetone Architecture for Optimum Line Matching
• Symmetrical Outputs Capable of Producing High Voltage
Swing
• Gain Select Option via Serial Bus Interface
• Receive Mute Function, Programmable via Serial Bus
Serial Bus Interface
• 3-Wire Connection to Microcontrolier
• One Programmable Output Meant for Driving a
Hookswitch
• Two Programmable Outputs Capable of Driving Low
Ohmic Loads
• Two Eight Bit Registers for Parameter Adjustment

Rx
Outputs

Tx
Inputs

A(lip)
' - - - - t - - - B (Ring)

Analog and Interface Integrated Circuits

4.7-22

Motorola Master Selection Guide

Speech Networks

(continued)

Programmable Telephone Line Interface
Circuit with Loudspeaker Amplifier
MC34216DW
TA

=0° to +70°C, Case 751 F

The MC34216 is developed for use in telephone
applications where besides the standard telephone functions
also the group listening-in feature is required. In cooperation
with a microcontroller, the circuit performs all basic telephone
functions including DTMF generation and pulse-dialing. The
listening-in part includes a loudspeaker amplifier, an
anti-howling circuit and a strong supply. In combination with
the TCA3385, the ringing is performed via the loudspeaker.

FEATURES
Line Driver and Supply
•
•
•
•

DC and AC Termination of the Line
Selectable Masks: France, U.K., Low Voltage
Current Protection
Adjustable Set Impedance for Resistive and Complex
Termination
• Efficient Supply Point for Loudspeaker Amplifier and
Peripherals

Dialing and Ringing
•
•
•
•
•
•

Generates DTMF, Pilot Tones and Ring Signal
Interrupter Driver for Pulse-Dialing
Low Current While Pulse-Dialing
Optimized for Ringing via Loudspeaker
Programmable Ring Melodies
Uses Inexpensive 500 kHz Resonator

Loudspeaking Facility
•
•
•
•
•

Integrated Loudspeaker Amplifier
Peak-to-Peak Limiter Prevents Distortion
Programmable Volume
Anti-Howling Circuitry for Group Listening-In
Interfacing for Handsfree Conversation

Application Areas

Handset Operation
•
•
•
•

• Earpiece Gain Increase Switch
• Microphone Squelch Function
• Transmit Amplifier Soft Clipping

•
•
•
•

Transmit and Receive Amplifiers
Adjustable Sidetone Network
Line Length AGC
Microphone and Earpiece Mute

Corded Telephony with Group Listening-In
Cordless Telephony Base Station with Group Listening-In
Telephones with Answering Machines
Fax, Intercom, Modem
Line +

Handset
Earpiece
Handset
Microphone

Base
Loudspeaker

Line-

Motorola Master Selection Guide

4.7-23

Analog and Interface Integrated Circuits

Speech Networks

(continued)

Telephone Line Interface
TCA3388DP, FP
TA = 0° to +70°C, Case 738, 751 D
The TCA3388 is a telephone line interface circuit which
performs the basic functions of a telephone set in combination
with a microcontroller and a ringer. It includes dc and ac line
termination, the hybrid function with 2 adjustable sidetone
networks, handset connections and an efficient supply point.

•
•
•
•

FEATURES

•
•
•
•

Line Driver and Supply
•
•
•
•

DC and AC Termination of the Telephone Line
Selectable DC Mask: France, U.K., Low Voltage
Current Protection
Adjustable Set Impedance for Resistive and Complex
Termination
• Efficient Supply Point for Peripherals
• Hook Status Detection
Handset Operation
• Transmit and Receive Amplifiers

Double Anti-Sidetone Network
Line Length AGC
Microphone and Earpiece Mute
Transmit Amplifier Soft Clipping

Dialing and Ringing
Interrupter Driver for Pulse-Dialing
Reduced Current Consumption During Pulse-Dialing
DTMF InterfaCing
Ringing via External Ringer

Application Areas
• Corded Telephony
• Cordless Telephony Base Station
• Answering Machines

• Fax
• Intercom
• Modem

Line +

Handset
Earpiece

Handset
Microphone

Line-

Analog and Interface Integrated Circuits

4.7-24

Motorola Master Selection Guide

Speakerphones
Voice Switched Speakerphone Circuit
MC34018P,

ow

TA = -20° to +60°C, Case 710, 751F
MC34018 Speakerphone integrated circuit
The
incorporates the necessary amplifiers, attenuators, and
control functions to produce a high quality hands-free
speakerphone system. Included are a microphone amplifier,
a power audio amplifier for the speaker, transmit and receive
attenuators, a monitoring system for background sound level,
and an attenuation control system which responds to the
relative transmit and receive levels as well as the background
level. Also included are all necessary regulated voltages for
both internal and external circuitry, allowing line-powered
operation (no additional power supplies required). A Chip
Select pin allows the chip to be powered down when not in use.
A volume control function may be implemented with an
external potentiometer. MC34018 applications include
speakerphones for household and business uses, intercom
systems, automotive telephones, and others.

• All Necessary Level Detection and Attenuation Controls
for a Hands-Free Telephone in a Single Integrated
Circuit
• Background Noise Level Monitoring with Long Time
Constant
• Wide Operating Dynamic Range Through Signal
Compression
• On-Chip Supply and Reference Voltage Regulation
• Typical 100 mW Output Power (into 25 0) with Peak
Limiting to Minimize Distortion
• Chip Select Pin for Active/Standby Operation
• Linear Volume Control Function

Electret
Microphone

Speaker
Telephon~

Line'9
----'INv--Receive Volume Control

Motorola Master Selection Guide

4.7-25

Analog and Interface Integrated Circuits

Speakerphones

(continued)

Voice Switched Speakerphone Circuit
MC34118P,

ow

TA = -20 to +60°C, Case 710, 751 F
0

The MC34118 Voice Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain and mute control,
Transmit and Receive attenuators which operate in a
complementary manner, level detectors at input and output of
both attenuators,and background noise monitors for both the
transmit and receive channels. A dial tone detector prevents
the dial tone from being attenuated by the Receive
background noise monitor circuit. Also included are two line
driver amplifiers which can be used to form a hybrid network
in conjunction with an external coupling transformer. A
high-pass filter can be used to filter out 60 Hz noise in the
receive channel, orfor other filtering functions. A Chip Disable
pin permits powering down the entire circuit to conserve power
on long loops where loop current is at a minimum.
The MC34118 may be operated from a power supply, or
it can be powered from the telephone line, requiring typically

5.0 mAo The MC34118 can be interfaced directly to Tip and
Ring (through a coupling transformer) for stand-alone
operation, or it can be used in conjunction with a handset
speech network and/or other features of a featurephone.
• Improved Attenuator Gain Range: 52 dB Between
Transmit and Receive
• Low Voltage Operation for Line-Powered Applications
(3.0 to 6.5 V)
• 4-Point Signal Sensing for Improved Sensitivity
• Background Noise Monitors for Both Transmit and
Receive Paths
• Microphone Amplifier Gain Set by External Resistors Mute Function Included
• Chip Disable for Active/Standby Operation
• On Board Filter Pinned-Out for User Defined Function
• Dial Tone Detector Inhibits Receive Idle Mode During Dial
Tone Presence
• Compatible with MC34119 Speaker Amplifier

(
Ring

Analog and Interface Integrated Circuits

4.7-26

Motorola Master Selection Guide

Speakerphones

(continued)

Voice Switched Speakerphone with ~Processor Interface
MC33218AP,

ow

TA = -40° to +85°C, Case 724, 751E
The MC33218A, Voice Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain, and mute control,
transmit and receive attenuators which operate in a
complementary manner, and level detectors and background
noise monitors for both paths. A dial tone detector prevents
dial tone from being attenuated by the receive background
noise monitor. A Chip Disable pin permits powering down the
entire circuit to conserve power.
Also included is an 8-bit serial Ilprocessor port for
controlling the receive volume, microphone mute, attenuator
gain, and operation mode (force to transmit, force to receive,
etc.). Data rate can be up to 1.0 MHz. The MC33218A can be
operated from a power supply, or from the telephone line,
requiring typically 3.8 mAo It can also be used in intercoms and
other voice-activated applications.

•
•
•
•

Low Voltage Operation: 2.5 to 6.0 V
2-Point Sensing, Background Noise Monitor in Each Path
Chip Disable Pin for Active/Standby Operation
Microphone Amplifier Gain Set by External Resistors Mute Function Included
• Dial Tone Detector to Inhibit Receive Idle Mode During
Dial Tone Presence
• Microprocessor port for controlling:
• Receive Volume Level (16 Steps)
• Attenuator Range (26 or 52 dB, Selectable)
• Microphone Mute
• Force to Transmit, Receive, Idle or Normal Voice
Switched Operation
• Compatible with MC34119 Speaker Amplifier

Tx Output

Rx Input

Vcc
Chip Disable

Motorola Master Selection Guide

4.7-27

Analog and Interface Integrated Circuits

Speakerphones

(continued)

Voice Switched Speakerphone Circuit
MC33219AP, ADW

TA

=-40° to +85°C, Case 724, 751 E

The MC33219A Voice Switched Speakerphone Circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain, and mute control,
transmit and receive attenuators which operate in a
complementary manner, and level detectors and background
noise monitors. A dial tone detector prevents dial tone from
being attenuated by the receive background noise monitor. A
Chip Disable pin permits powering down the entire circuit to
conserve power.
The MC33219A may be operated from a power supply, or
it can be powered from the telephone line requiring typically

4.0 mA. The MC33219A can be interfaced directly to Tip and
Ring (through a coupling transformer for stand-alone
operation, or it can be used in conjuction with a handset
speech network and/or other features of a featurephone.
• Low Voltage Operation: 2.7 to 6.0 V
• 2-Point Sensing, Background Noise Monitor in Each Path
• Chip Disable Pin for Active/Standby Operation
• Microphone Amplifier Gain Set by External Resistors Mute Function Included
• Dial Tone Detector to Inhibit Receive Idle Mode During
Dial Tone Presence
• Volume Control Range: 34 dB
• Compatible with MC34119 Speaker Amplifier

Mute

TxOutput

Speaker

Rx Input
VCC
Chip Disable

Wv
Volume
Control

Analog and Interface Integrated Circuits

4.7-28

Motorola Master Selection Guide

Speakerphones (continued)

Table 9. The Motorola Family of Speakerphone Integrated Circuits
MC34018

MC34118

MC33218A

MC33219A

Two point sensing with slow idle,
background noise monitor in T x
path only

Four point sensing with both fast
and slow idle modes,
background noise monitors in
both Rx and T x paths

Two point sensing with slow idle,
background noise monitors in
both Rx and Tx paths

Two point sensing with slow idle,
background noise monitors in
both Rx and T x paths

No dial tone detector in receive
path

Receive path has dial tone
detector

Receive path has dial tone
detector

Receive path has dial tone
detector

Attenuator Characteristics:
• Range: 44 dB
• Tolerance: ±4.0 dB
• Gain tracking not specified
• White noise is constant

Attenuator Characteristics:
• Range: 52 dB
• Tolerance: ±2.0 dB
• Gain Tracking: <1.0 dB
• White noise reduces with
volume

Attenuator Characteristics:
• Range: 52 or 26 dB
(selectable)
• Tolerance: ±3.0 dB
• Gain Tracking: <1.0 dB
• White noise reduces with
volume

Attenuator Characteristics:
• Range: 52 dB
• Tolerance: ±3.0 dB
• Gain Tracking: <1.0 dB
• White noise reduces with
volume

External hybrid required

Hybrid amplifiers on board

External hybrid required

External hybrid required

Speaker amplifier is on board
(34 dB, 100 mW)

Extemal speaker amplifier
required (MC34119)

External speaker amplifier
required (MC34119)

External speaker amplifier
required (MC34119)

Filtering is external

Configurable filter on board

Filtering is external

Filtering is external

Microphone amplifier has fixed
gain and no muting

Microphone amplifier has
adjustable gain and mute input

Microphone amplifier has
adjustable gain, and can be
muted through IlP port

Microphone amplifier has
adjustable gain and a mute input

Supply Voltage: 4.0 V to 11 V

Supply Voltage: 2.8 V to 6.5 V

Supply Voltage: 2.5 V to 6.5 V

Supply Voltage: 2.7 V to 6.5 V

Supply Current: 6.5 mA typ.,
9.0 mA max

Supply Current: 5.5 rnA typ.,
8.0 mA max

Supply Current: 4.0 mA typ.,
5.0 rnA max

Supply Current: 3.0 mA typ.,
5.0 mAmax

Speaker amplifier reduces gain
to prevent clipping

Receive gain is reduced as
supply voltage falls to prevent
clipping

Receive gain is reduced as
supply voltage falls to prevent
clipping

Receive gain is reduced as
supply voltage falls to prevent
clipping

Volume control is linear. Cannot
override voice switched
operation except through
additional circuitry. Attenuator
gain is fixed at 44 dB (slightly
variable). No microphone mute.

Volume control is linear, and
microphone mute has separate
pin. Cannot override voice
switched operation except
through additional circuitry.
Attenuator gain is fixed at 52 dB.

8-bit IlP serial port controls:
• Volume control (16 steps)
• Microphone mute
• Range selection
(26 dB or 52 dB)
• Force to transmit, idle,
receive, or normal
voice switched operation

Volume control is linear, and
microphone mute has separate
pin. Attenuator range fixed at
52 dB. Cannot override voice
switched operation except
through additional circuitry.

28 Pin DIP and SOIC packages

28 Pin DIP and SOIC packages

24 Pin narrow DIP and SOIC
packages

24 Pin narrow DIP and SOIC
packages

External Required:
• 12 Resistors
• 11 Capacitors (';;1.0 IlF)
• 8 CapaCitors (>1.0 IlF)

Extemal Required:
• 14 Resistors
• 12 CapaCitors (';;1.0 IlF)
• 9 Capacitors (>1.0 IlF)

Extemal Required:
• 12 Resistors
• 11 CapaCitors (';;1.0 IlF)
• 4 CapaCitors (> 1.0 IlF)

External Required:
• 12 Resistors
• 11 CapaCitors (';;1.0 IlF)
• 4 Capacitors (>1.0 IlF)

Temperature Range:
-20° to +60°C

Temperature Range:
-20° to +60°C

Temperature Range:
-40° to +85°C

Temperature Range:
-40° to +85°C

Motorola Master Selection Guide

4.7-29

Analog and Interface Integrated Circuits

Telephone Accessory Circuits
Audio Amplifier
MC34119P, D

CI

TA = 0° to +70°C, Case 626, 751
Differential Gain = 2 x

A low power audio amplifier circuit intended (primarily) for
telephone applications, such as speakerphones. Provides
differential speaker outputs to maximize output swing at low
supply voltages (2.0 V min.). Coupling capacitors to the
speaker, and snubbers, are not required. Overall gain is
externally adjustable from 0 to 46 dB. A Chip Disable pin
permits powering-down to mute the audio signal and reduce
power consumption.

~:

Rt
150 k

•
•
•
•

Drives a Wide Range of Speaker Loads (16 to 1000)
Output Power Exceeds 250 mW with 32 0 Speaker
Low Distortion (THD = 0.4% Typical)
Wide Operating Supply Voltage (2.0 V to 16 V) - Allows
Telephone Line Powered Applications.
Low Quiescent Supply Current (2.5 mA Typical)
• Low Power-Down Quiescent Current (60 !LA Typical)

• Optional

Current Mode Switching Regulator
MC34129P, D

TA = 0° to +70°C, Case 646, 751A

r::-,T:: T::-,.""":~.::- T::::- '" -

I' . . .... .
I

High performance current mode switching regulator for
low-power digital telephones. Unique internal fault timer
provides automatic restart for overload recovery. A start/run
comparator is included to implement bootstrapped operation
ofVCC·
Although primarily intended for digital telephone systems,
these devices can be used cost effectively in many other
applications. On-chip functions and features include:
•
•
•
•
•
•
•

Output

eSoft-Start 112"'

Vee
Vrel 1.25 V

Noninverting
Input
Inverting Input

Current Mode Operation to 300 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle-By-Cycle Current Limiting
Latched-Off or Continuous Retry after Fault Timeout
Soft-Start with Maximum Peak Switch Current Clamp
Internally Trimmed 2% Bandgap Reference
Input Undervoltage Lockout

Analog and Interface Integrated Circuits

::-.",,":,'9

'~gl StarVRun

'1.;-;""'""",""";:''0 Feedback!
PWM Input
.N.,...,..;:...;:.::..;,In

Drive Out

Drive Gnd
~i.;:...::~;""'""",""";l¢ Ramp Input

4.7-30

Motorola Master Selection Guide

Telephone Accessory Circuits

(continued)

The differential line driver is capable of driving 0 dBm into
a 600 n load. The transmit attenuator is programmable in
1.0 dB steps.

300 Baud FSK Modems
MC145442P, ow Modem - CCITT V.21
Case 738, 751 D

ADPCM Transcoder

MC145443P, OW Modem - Bell 103
Case 738, 7510

MC1455320W, L
Case 751G, 620

This powerful modem combines a complete FSK
modulator/demodulator and an accompanying transmit/receive
filter system on a single silicon chip. Designed for bidirectional
transmission over the telephone network, the modem operates
at 300 baud and can be obtained for compatibility with CCITT
V.21 and Bell 103 specifications.
The modem contains an on-board carrier-detect circuit
that allows direct operation on a telephone line (through a
simple transformer), providing simplex, half-duplex, and
full-duplex data communications. A built-in power amplifier is
capable of driving -9.0 dBm onto a 600 n line in the transmit
mode.
CMOS processing keeps power dissipation to a very low
45 mW, with a power-down dissipation of only 1.0 mW ... from
a single 5.0 V power supply. Available in a 20 pin dual-in-line
P suffix, and a wide body surface mount DW suffix.

Carrier
Detect
Adjust

3.579545 MHz

The MC145532 Adaptive Differential Pulse Code
Modulation (ADPCM) Transcoder provides a low cost,
full-duplex, single-channel transcoder to (from) a 64 kbps
PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
• Complies with CCITT Recommendation G.721
(1988)
• Complies with the American National Standard
(T1.301-1987)
• Full-Duplex, Single-Channel Operation
• Mu-Law or A-Law Coding is Pin Selectable
• Synchronous or Asynchronous Operation
• Easily Interfaces with any Member of Motorola's PCM
Codec-Filter Mono-Circuit Family or Other Industry
Standard Codecs
• Serial PCM and ADPCM Data Transfer Rate from
64 kbps to 5.12 Mbps
• Power Down Capability for Low Cost Consumption
• The Reset State is Automatically Initiated when the
Reset Pin is Released.
• Simple Time Slot Assignment Timing for Transcoder
Applications
• Single 5.0 V Power Supply
• Evaluation Kit MC145536 EVK Supports the MG145532
as well as the MC145480 PCM Godec-Filter. (See PBX
Architecture Pages for More Information.)

MC145444H, OW - CCITT V.21
Case 804, 751D
MC145446AFW - CCITT V.21
Case 751M

This device includes the DTMF generator and call progress
tone detector (CPTD) as well as the other circuitry needed for
full-duplex, half-duplex, or simplex 300 baud data
communication over a pair of telephone lines. It is intended for
use with telemeter system or remote control system
applications.

Motorola Master Selection Guide

4.7-31

Vss-

-VDD

Analog and Interface Integrated Circuits

Telephone Accessory Circuits

(continued)

Calling Line Identification (CLIO) Receiver with Ring Detector
MC145447P,

ow

Case 648, 751 G
The MC145447 is designed to demodulate Bell 202
1200 baud FSK asynchronous data. Its primary application is
in products that will be used to receive and display the calling
number, or the message waiting indicator sent to subscribers
from participating central office facilities of the public switched
telephone network. The device also contains a carrier detect
circuit and telephone ring detector which may be used to
power up the device.
Applications include adjunct boxes, answering machines,
feature phones, fax machines, and computer interface
products.

Tip

Ring

Ring Detector On-Chip
Ring Detect Output for MCU Interrupt
Power-Down Mode Less Than 1.0 I-lA
Single Supply: 3.5 V to 6.0 V
Pin Selectable Clock Frequencies: 3.68 MHz,
3.58 MHz, or 455 kHz
• Two-Stage Power-Up for Power Management Control

, - - - - . Raw Data
Out
Cooked
Data Out

•
•
•
•
•

Clock Select
3.58 MHz, 3.68 MHz,
OR 455 kHz

--0

VSS

Calling Line 10 Receiver Evaluation Kit
MC145460EVK

The MC145460EVK is a low cost evaluation platform for
the MC145447. The MC145460EVK facilitates development
and testing of products that support the Bellcore customer
premises equipment (CPE) data interface, which enables
services such as Calling Number Delivery (CND). The
MC145447 can be easily incorporated into any telephone,
FAX, PBX, key system, answering machine, CND adjunct box
or other telephone equipment with the help of the
MC145460EVK development kit.

• Easy Clip-On Access to Key MC145447 Signals
• Generous Prototype Area
• Configurable for MC145447 Automatic or External Power
Up Control
• EIA-232 and Logic Level Ports for Connection to any PC
or MCU Development Platform
• Carrier Detect, Ring Detect and Data Status LEDs
• Optional Tip and Ring Input Protection Network
• MC145460EVK User Guide, MC145447 Data Sheet, and
Additional MC145447 Sample Included

EIA-232 Level
Output
CD, RD, Data
Logic Level
Output
CD, RD, Data

Analog and Interface Integrated Circuits

4.7-32

Motorola Master Selection Guide

Telephone Accessory Circuits

(continued)

Continuously Variable Slope Delta (CVSD) Modulator/Demodulator
MC34115P, ow
TA 0° to +70°C, Case 648, 751G

=

MC3418P, OW
TA 0° to +70°C, Case 648, 751G

=

Provides the AlD-D/A function of voice communications by
digital transmission. Designed for speech synthesis and
commercial telephone applications. A single IC provides both
encoding and decoding.
• Encode and Decode Functions on the Same Chip with a
Digital Input

• CMOS Compatible Digital Output
• Digital Input Threshold Selectable (VCC/2 reference
provided on Chip)
• MC34115 Has a 3--Bit Algorithm (General
Communications)
• MC3418 Has a 4-Bit Algorithm (Commercial Telephone)

Encolil!
Decode

Clock

15

14

Analog Input
Analog Feedback
Digital Data Input
Digital Threshold

Coincidence Output

Digital Output
Syllablic Filter
Gain Control

VCcJ2 Reference

Analog
Output

Motorola Master Selection Guide

Reference
Input
(+)

4.7-33

Filter
Input
(-)

Analog and Interface Integrated Circuits

Telephone Accessory Circuits

(continued)

Table 10. Summary of Bipolar Telecommunication Circuits

I

Function

Suffix!

I

Features

Package

Device

Subscriber Loop Interface Circuits (SUes)
PBX Applications

All gains externally programmable, most BORSHT functions,
current limit adjustable to 100 mA.

U726

MC3419-1

Central Office, Remote Terminals,
PBX Applications

All gains externally programmable, most BORSHT functions,
current limit adjustable to 50 mA, 58 dB Longitudinal Balance,
-21.6 V to -42 V.

pn38,
FNI776

MC33121

Central Office, Remote Terminals,
PBX Applications

All gains externally programmable, most BORSHT functions,
current limit adjustable to 50 mA, 58 dB Longitudinal Balance,
-42 V to -58 V.

pn38,
FNm6

MC33120

Complete Telephone Circuit
POTS Circuit + MPU Dialing

Speech network, tone ringer, dc loop current interface, DTMF
dialer with serial port control.

Tone Ringers
Adjustable Tone Ringer

Single-ended output, meets FCC requirements, adjustable REN,
different warble rates.

P/626,
Dn51

MC34012-1,
2,3

Adjustable Tone Ringer

Differential output, meets FCC requirements, adjustable REN,
different warble rates.

P/626,
Dn51

MC34017-1,
2,3

Adjustable Tone Ringer

Differential output, meets FCC requirements, adjustable REN,
single warble rates.

P/626,
D/751

MC34217

Basic Phone Line Interface

Loop current interface, speech network, line length
compensation, speech/dialing modes, Bell System compliant.

pn07,
DWn51D

MC34014

Cordless Universal Telephone
Interface

Designed for digital cordless phones, SPI interface, double
sidetone network, low noise and distortion.

pn38,
DWn51D

MC34016

Basic Phone Line Interface

Loop current interface, speech network, line length compensation,
speech/dialing modes, Bell System and foreign countries.

pn07,
DWn51D

MC34114

Programmable Telephone Line
Interface Circuit with Loudspeaker
Amplifier

Group listening-in, DTMF and tones generator, ring generator,
country programmable, SPI interface.

DWn51F

MC34216

Telephone Line Interface

Country programmable, double sidetone network, provides strong
supply point.

DPn38,
FPn51D

TCA3388

Complete Speaker Phone with
Speaker Amplifier

All level detection (2 pt.), attenuators, and switching controls,
mike and speaker amp.

pm 0,
DWn51F

MC34018

Complete Speaker Phone with
Hybrid, Filter

All level detection (4 pt.), attenuators, and switching controls,
mike amp with mute, hybrid, and filter.

P/71 0,
DWn51F

MC34118

Complete Speaker Phone with
MPU Interface

All level detection, attenuators, and switching controls, mike amp,
MPU interface for: volume control, mode selection, mike mute.

pn24,
DWn51E

MC33218A

Basic Low Cost Speakerphone

All level detection, attenuators and switching controls, Mike
amplifier with Mute, low voltage operation.

pn24,
DWn51E

MC33219A

Speech Networks

Speakerphone Circuits

Audio Amplifiers
1 Watt Audio Amp

1.0 W output power into 16 n, 35 V maximum.

Dn51

MC13060

Low Voltage Audio Amp

400 mW, 8.0 to 100 n, 2.0 to 16 V, differential outputs,
chip-

r:::

-=

c:
CD

o

~

CSYNCI

-=

'-'
CGLlNES

..,.

~

"-

::0

8

!

"
- 1 'j'l

FLD

ADDR
DECODER

FLD

LS
SFLP
????

>
::>

!!!.

LINE & FLD
CTR

0

r;:;l

IQ

III

::>

c.

:;
!it

::!.
III
n
CD

1

I

i!l.

CD

c.
0

r;"
r:::

m:

~

LINE AND FLO
DECODERS
11

-------~J:lr~;--~~

HIN

:;

!it
IQ

o
Q
...o

T1::'d:
-=

LOOP
FILTER

-=

17 3 2 18

:i"

.s

Video Circuits

(continued)

Set-Top Block Diagram

r------,

I
I
I

I
I
I

IL

_ _ _ _ _ .J

I

~~-___l~,.)

c--iH-___l~'.)

-+-+....--D>--@

R
G
B

y
C

CB

Channel
314

Oigital Sound Section

• In Development

Analog and Interface Integrated Circuits

4.8-18

Motorola Master Selection Guide

Video Circuits

(continued)

PLL Tuning Circuits with 3-Wire Bus
MC44817BD, D

Case 751B
The MC44817/17B are tuning circuits for TV and VCR
tuner applications. They contain on one chip all the functions
required for PLL control of a VCO. The integrated circuits also
contain a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44817 has programmable 512/1024 reference
dividers while the MC44817B has a fixed reference divider of
1024.
The MC44817/17B are manufactured on a single silicon
chip using Motorola's high density bipolar process, MOSAICTM
(Motorola Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (3-Wire
Bus). Data and Clock Inputs are IIC Bus Compatible
• Divide-by-8 Prescaler Accepts Frequencies up to
1.3GHz
• 15 Bit Programmable Divider Accepts Input Frequencies
up to 165 MHz

• Reference Divider: Programmable for Division Ratios 512
and 1024. The MC44817B has a Fixed 1024 Reference
Divider
• 3-State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output
(30 V)
• Four Integrated PNP Band Buffers for 40 mA (VCC1 to
14.4 V)
• Output Options for the Reference Frequency and the
Programmable Divider
• Bus Protocol for 18 or 19 Bit Transmission
• Extra Protocol for 34 Bit for Test and Further Features
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
• Fully ESD Protected

Bands Out 30 rnA
(40 rnA at 0° to ao°C)

VTUN
VCC3

5.0V

7

13

12 11

10

14
12V

.-/.it----..-4-o Amp In
2.7V

Lock

EN ~----+_-rL-..-'--'1

~==~;~~~L.-_~~

Data

Clockr~I--1..-.:;:;:~JI

__--.J
XTAL

Preamp 2

Motorola Master Selection Guide

4.8-19

Analog and Interface Integrated Circuits

Video Circuits

(continued)

PLL Tuning Circuit with 12C Bus
MC44818D
Case 751B
The MC44818 is a tuning circuit for TV and VCR tuner
applications. It contains, on one chip, all the functions required
for PLL control of a VCO. This integrated circuit also contains
a high frequency prescaler and thus can handle frequencies
up to 1.3 GHz. The MC44818 is a pin compatible drop-in
replacementforthe MC44817, where the only difference is the
MC44818 has a fixed divide-by-8 prescaler (cannot be
bypassed) and the MC44817 uses the three wire bus.
The MC44818 has programmable 512/1024 reference
dividers and is manufactured on a single silicon chip using
Motorola's high density bipolar process, MOSAICTM (Motorola
Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (12C Bus).
Data and Clock Inputs are 3-Wire Bus Compatible
• Divide-by-8 Prescaler Accepts Frequencies up to
1.3 GHz

• 15 Bit Programmable Divider Accepts Input Frequencies
up to 165 MHz
• Reference Divider: Programmable for Division Ratios 512
and 1024.
• 3-State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output
(30 V)
• Four Integrated PNP Band Buffers for 40 rnA (VCC1 to
14.4 V)
• Output Options for the Reference Frequency and the
Programmable Divider
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
• Fully ESD Protected

Bands Out 30 mA
(40 mA at 00 to BOaC)
VCC1
5.0V

VTUN
VCC3

7

13

12 11

10

4 Amp In
.........t----1....-o

DTB1

Latches

Lock

XTAL

DTS, EN

Analog and Interface Integrated Circuits

4.8-20

Motorola Master Selection Guide

Video Circuits

(continued)

PLL Tuning Circuits with 12C Bus
MC44824125D
Case 751A, 751B
The MC44824/25 are tuning circuits for TV and VCR tuner
applications. They contain on one chip all the functions
required for PLL control of a VCO. The integrated circuits also
contain a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44824/25 are manufactured on a single silicon chip
using Motorola's high density bipolar process, MOSAICTM
(Motorola Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (12C Bus).
Data and Clock Inputs are 3-Wire Bus Compatible
• Divide-by-8 Prescaler Accepts Frequencies up to
1.3 GHz

• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512
and 1024
• 3-State Phase/Frequency Comparator
• 4 Programmable Chip Addresses
• 3 Output Buffers (MC44824) respectively; 5 Output
Buffers (MC44825) for 10 mAl15 V
• Operational Amplifier for use with External NPN Transistor
• S0-14 Package for MC44824 and S0-16 for MC44825
• High Sensitivity Preamplifier
• Fully ESD Protected

Vcc
5.0 V

10 (12)

UD
6(6)

-(7)

8(9)

9(10)

-(11)

14(16)

1 (1)

BO

PD

2.7V

Gnd

XTAL1
XTAL2

HF Inputt
HF Input2 u---....,.,

MC44825 Pin Numbers ( )

Motorola Master Selection Guide

4.8-21

Analog and Interface Integrated Circuits

Video Circuits

(continued)

PLL Tuning Circuit with 3-Wire Bus
MC44827DTB

Case 948F
The MC44827 is a tuning circuit for TV and VCR tuner
applications. This device contains on one chip all the functions
required for PLL control of a VCO. This integrated circuit also
contains a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44827 is controlled by a 3-wire bus. It has the
same function as the MC44828 which is 12C bus controlled.
The MC44827 and MC44828 can replace each other to allow
conversion between 3-wire bus and 12C bus control.
The MC44827 is manufactured on a single silicon chip
using Motorola's high density bipolar process, MOSAICTM
(Motorola Oxide Self Aligned Implanted Circuits).

The MC44827 has the same features as MC44817 with the
following differences:
• Lower Power Consumption, 200 mW Typical
• Improved Prescaler with Higher Margins for Sensitivity
and Temperature Range. (A typical device is functional in
a temperature range greater than -40 to 100°C.)
• Lock Detector with Push-Pull Output
• No Bypass of Divide-by-8 Prescaler
• TSSOP Package

PLL Tuning Circuit with 12C Bus
MC44828DTB

Case 948F
The MC44828 is a tuning circuit for TV and VCR tuner
applications. This device contains on one chip all the functions
required for PLL control of a VCO. This integrated circuit also
contains a high frequency prescaler and thus can handle
frequencies up to 1.3 GHz.
The MC44828 is controlled by an 12C bus. It has the same
function as the MC44827 which is 3-wire bus controlled. The
MC44827 and MC44828 can replace each other to allow
conversion between 3-wire bus and 12C bus control.
The MC44828 is manufactured on a single silicon chip
using Motorola's high density bipolar process, MOSAlcrM
(Motorola Oxide Self Aligned Implanted Circuits).

Analog and Interface Integrated Circuits

4.8-22

The MC44828 has the same features as MC44818 with the
following differences:
• Lower Power Consumption, 200 mW Typical
• Improved Prescaler with Higher Margins for Sensitivity
and Temperature Range. (A typical device is functional in
a temperature range greater than -40 to 100°C.)
• Lock Detector with Push-Pull Output
• TSSOP Package

Motorola Master Selection Guide

Video Circuits

(continued)

PLL Tuning Circuit with 12C Bus
MC44829D
Case 751A
The MC44829 is a tuning circuit for TV and VCR tuner
applications. It contains, on one chip, all the functions required
for PLL control of a VCO. This integrated circuit also contains
a high frequency prescaler and thus can handle frequencies
up to 1.3 GHz. The circuit has a band decoder that provides
the band switching signal for the mixer/oscillator circuit. The
decoder is controlled by the buffer bits.
The MC44829 has programmable 512/1024 reference
dividers and is manufactured on a single silicon chip using
Motorola's high density bipolar process, MOSAICTM (Motorola
Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (12C Bus)
• Divide-by-8 Prescaler Accepts Frequencies up to
1.3 GHz

• 15 Bit Programmable Divider
• Reference Divider: Programmable for Division Ratios 512
and 1024
• 3-State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output
(30 V)
• Four Programmable Chip Addresses
• Integrated Band Decoder for the Mixer/Oscillator Circuit
• Band Buffers with Low "On" Voltage (0.4 V Maximum at
5.0mA)
• Fully ESD Protected to MIL-STD-883C, Method 3015.7
(2000 V, 1.5 kn, 150 pF)

VTUN

r

Bands Out

8

B6

VCC2

CL

7

14

B5
2.7V

Buffers

PHO

-=T8
Gnd

2

DTB2
POR
CA
SDA
SCL

9

11
10

CL
Data
RL
DTF

T 12pF
D 3.214.0
MHz

l

DTS, EN

Motorola Master Selection Guide

4.8-23

Analog and Interface Integrated Circuits

Video Circuits

(continued)

Advanced PAUNTSC Encoder
MC13077P,

ow

Case 738, 7510
The MC13077 is an economical, high quality, RGB encoder
for PAL or NTSC applications. It accepts red, green, blue and
composite sync inputs and delivers either composite PAL or
NTSC video, and S-Video Chroma and Luma outputs. The
MC13077 is manufactured using Motorola's high density,
bipolar MOSAIC® process.
• Single 5.0 V Supply
• Composite Output

•
•
•
•
•
•
•
•

S-Video Outputs
PAUNTSC Switch able
PAL Squarewave Output
PAL Sequence Resettable
Internal/External Burst Flag
Modulator Angles Accurate to 90°
Burst Position/Duration Determined Digitally
Subcarrier Reference from a Crystal or External Source

Gnd

VCC

i----~---------------------~-----l
3.58/

Divide By Four Ring
Counter

45"
PLL
Off

Divide By 256

0"

4.43 MHz
Latch

I
I
I
I
I
I
I

LPF

3.58/4.43 MHz
In/PLLOff

Rln
Gin

Color
Difference

and
Luma
Matrix

Bin

Analog and Interface Integrated Circuits

4.8-24

Motorola Master Selection Guide

Consumer Electronic Circuits Package Overview

•

CASE 626
PSUFFIX

-

CASE 707
PSUFFIX

CASE 711
PSUFFIX

•

CASE 751
D SUFFIX

CASE 751E
DWSUFFIX

Motorola Master Selection Guide

CASE 646
P SUFFIX

CASE 648
PSUFFIX

CASE 709
PSUFFIX

CASE 710
PSUFFIX

-

CASE 738
H, PSUFFIX

CASE 724
PSUFFIX

CASE 751A
DSUFFIX

CASE 751D
DWSUFFIX

CASE 751B
DSUFFIX

CASE 751F
DWSUFFIX

4.8-25

•

CASE 751G
DWSUFFIX

Analog and Interface Integrated Circuits

Consumer Electronic Circuits Package Overview (continued)

CASE 824, 824A
FBSUFFIX

CASE 824E
FBSUFFIX

•

CASE 859
BSUFFIX

CASE 873
FU SUFFIX

CASE 898
FB, FU, P SUFFIX

•

•

CASE 904
FSUFFIX

Analog and Interface Integrated Circuits

•

•

CASE 777
FN SUFFIX

CASE948F
DTB SUFFIX

4.8-26

Motorola Master Selection Guide

Automotive Electronic Circuits

In Brief ...
Page

Motorola Analog has established itself as a global leader
in custom integrated circuits for the automotive market. With
multiple design centers located on four continents, global
process and assembly sites, and strategically located
supply centers, Motorola serves the global automotive
market needs. These products are key elements in the
rapidly growing engine control, body, navigation,
entertainment, and communication electronics portions of
modern automobiles. Though Motorola is most active in
supplying automotive custom designs, many of yesterday's
proprietary custom devices have become standard products
of today, available to the broad base manufacturers who
support this industry. Today, based on new technologies,
Motorola offers a wide array of standard products ranging
from rugged high current "smart" fuel injector drivers which
control and protect the fuel management system through the
rigors of the underhood environment, to the latest
SMARTMOSTM switches and series transient protectors.
Several devices are targeted to support microprocessor
housekeeping and data line protection. A wide range of
packaging is available including die, flip-chip, and SOICs for
high density layouts, to low thermal resistance multi-pin,
single-in-line types for high power control ICs.

Motorola Master Selection Guide

Voltage Regulators ............................. 4.9-2
Electronic Ignition .............................. 4.9-2
Special Functions .............................. 4.9-3
Package Overview ............................ 4.9-12

4.9-1

Analog and Interface Integrated Circuits

Automotive Electronic Circuits
Table 1. Voltage Regulators
Function

Suffix!
Package

Features

Device

Low Dropout Voltage
Regulator

Positive fixed and adjustable output voltage regulators which
maintain regulation with very low input to output voltage differential.

ZJ29, T/221 A,
T/3140, THl314A,
TV/314B,OT/369A,
OT-1/369,02T/936,
02T/936A,01751

LM2931, C

Low Dropout Dual
Regulator

Positive low voHage differential regulator which features dual 5.0 V
outputs, with currents in excess of 750 mA (switched) and 10 mA
standby, and quiescent current less than 3.0 mA.

T/3140, TH/314A,
TV/314B,02T/936A

LM2935

Automotive Voltage
Regulator

Provides load response control, duty cycle limiting, under/overvoltage
and phase detection, high side MOSFET field control, voltage
regulation in 12 V altemator systems.

OW1751 0

MC33092

Low Dropout Voltage
Regulator

Positive 5.0 V, 500 mA regulator having on-chip power-up-reset
circuit with programmable delay, current limit, and thermal shutdown.

T/3140, TV/314B

MC33267

Low Dropout Voltage
Regulator

Positive 3.3 V, 5.0 V, 12 V, 800 mA regulator.

01751, OT/369A

MC33269

Suffix!
Package

Device

P/626, 01751,
Flip-Chip

MC3334,
MCCF3334

Table 2. Electronic Ignition
Function

Features

Electronic Ignition
Circuit

Used in high energy variable dwell electronic ignition systems with
variable reluctance sensors. Dwell and spark energy are extemally
adjustable. "Bumped" die for inverted mounting to substrate.

Electronic Ignition
Circuit

Used in high energy electronic ignition systems requiring differential
Hall Sensor control. "Bumped" die for inverted mounting to substrate.

OWI751G,
Flip-Chip

MC33093,
MCCF33093

Electronic Ignition
Circuit

Used in high energy electronic ignition systems requiring single Hall
Sensor control. "Bumped" die for inverted mounting to substrate.

OWI751G,
Flip-Chip

MC33094,
MCCF33094

Electronic Ignition
Circuit

Used in high energy electronic ignition systems requiring single Hall
Sensor control. Dwell feedback for coil variation. "Bumped" die for
inverted mounting to substrate.

OWI751G,
Flip-Chip

MC79076,
MCCF79076

Analog and Interface Integrated Circuits

4.9-2

Motorola Master Selection Guide

Table 3. Special Functions
Function

Suffix!
Package

Features

Device

Low Side Protected
Switch

Single automotive low side switch having CMOS compatible input,
1.0 A maximum rating, with overcurrent, overvoltage and thermal
protection.

T/221 A, T-1/314D,
DW/751G

MC3392

Low Current High-Side
Switch

Drives loads from positive side of power supply and protects against
high-voltage transients.

T/314D, DW/751G

MC3399

High-Side TMOS Driver

Designed to drive and protect N-channel power MOSFETs used in
high side swnching applications. Has internal charge pump, externally
programmed timer and fault reporting.

P/626, D/751

MC33091A

MI-Bus Interface
Stepper Motor
Controller

High noise immunity serial communication using MI-Bus protocol to
control relay drivers and motors in harsh environments. Four phase
signals drive two phase motors in either half or full-step modes.

DW/751G

MC33192

Quad Fuel Injector
Driver

Four low side swnches with parallel CMOS compatible input control,
:$ 7.0 rnA quiescent current, 0.25 Q rDS(on) at 25°C independent
outputs with 3.0 A current limiting and internal 65 V clamps.

T/821D, TV/821C

MC33293

Octal Serial Output
Switch

Eight low side switches having 8-bit serial CMOS compatible input
control, serial fault reporting, :$ 4.0 rnA quiescent current, independent
0.45 Q rDS(on) at 25°C outputs with 3.0 A minimum current limiting and
internal 55 V clamps.

P/738, DW/751E

MC33298

Integral Alternator
Regulator

Control device used in conjunction with a Darlington device to monitor
and control the field current in alternator charging systems. "Bumped"
die for inverted mounting to substrate.

D/751A, Flip-Chip

MC33095
MCCF33095

Peripheral Clamping
Array

Protects up to six MPU 1/0 lines against voltage transients.

'/626, D/751

TCF6000

Automotive Direction
Indicator

Detects defective lamps and protects against overvoltage in
automotive turn-signal applications. Replaces UAA1041 B in most
applications.

D/751 , P/626

MC33193

Automotive Wash Wiper
Timer

Standard wiper timer control device that drives a wiper motor relay and
can perform the intermittent, afterwash and continuous wiper timer
functions.

D/751 , P/626

MC33197

Automotive ISO 9141
Serial Link Driver

Interface between the two-wire asynchronous serial communication
interface (SCI) of a microcontroller and a special one-wire care
diagnosis system (DIA).

D/751 A

MC33199

'No Suffix

Motorola Master Selection Guide

4.9-3

Analog and Interface Integrated Circuits

Quad Fuel Injector Driver
MC33293T, MC33293TV
TJ

=-40

0

to +150°C, Case 8210, C
shorted loads, and over temperature condition of outputs. A
shorted load condition will shut off only the specific output
involved while allowing other outputs to operate normally. An
overvoltage condition will shut off all outputs for the
overvoltage duration. A single/dual mode select pin allows
either independent input/output operation or paired output
operation.

The MC33293T is a monolithic quad low-side switching
device having CMOS logic, bipolar/ CMOS analog circuitry,
and OMOS power FETs. All inputs are CMOS compatible.
Each independent output is internally clamped to 65 V, current
limited to ----------_---------- +Vbat
VCC
1 MI

To other
devices

MC33192DW
Osc

Ground
MI-Bus

Ceramic
Resonator

-.e.+-------------------

From MCU
MI-Bus

Automotive Direction Indicator
MC33193P,D
TA = -40° to +125°C, Case 626, 751
The MC33193 is a new generation industry standard
UAA 1041 "Flasher". It has been developed for enhanced EMI
sensitivity, system reliability, and improved wIring
simplification. The MC33193 is pin compatible with the
UAA1041 and UAA 1041 B in the standard application
configuration as shown in Figure 9, without lamp short circuit
detection and using a 20 mO shunt resistor. The MC33193 has
a standby mode of operation requiring very low standby
supply current and can be directly connected to the vehicle's
battery. It includes a RF filter on the Fault detection pin (Pin 7)

Analog and Interface Integrated Circuits

for EMI purposes. Fault detection thresholds are reduced
relative to those of the UAA1041 allowing a lower shunt
resistance value (20 mO) to be use.
• Pin Compatible with the UAA1041
• Defective Lamp Detection Threshold
• RF Filter for EMI Purposes
• Load Dump Protection
• Double Battery Capability for Jump Start Protection
• Internal Free Wheeling Diode Protection
• Low Standby Current Mode

4.9-8

Motorola Master Selection Guide

Automotive Wash Wiper Timer
MC33197D
TA

=-40° to +105°C, Case 751

MC33197P
TA

=-40° to + 125°C, Case 626

The MC33197 is a standard wiper timer control device
designed for harsh automotive applications. The device can
perform the intermittent, after wash, and continuous wiper
timer functions. It is designed to directly drive a wiper motor
relay. The MC33197 requires very few external components
for full system implementation. The intermittent control pin can
be switched to ground or Vbat to meet a large variety of
possible applications. The intermittent timing can be fixed or
adjustable via an external resistor. The MC33197 is built using
bipolar technology and parametrically specified over the
automotive ambient temperature range and 8.0 to 16 V supply
voltage. The MC33197 can operate in both front and rear
wiper applications.

• Adjustable Time Interval of Less Than 500 ms to More
Than 30s
• Intermittent Control Pin Can Be Switched to Ground
or Vbat
• Adjustable After Wipe TIme
• Priority to Continuous Wipe
• Minimum Number of TIming Components
• Integrated Relay Driver With Free Wheeling Protection
Diode
• Operating Voltage Range From 8.0 to 16 V
• For Front Wiper and Rear Wiper Window Applications

R1 =220 Q
R2=22kQ
R3= 1.5 to 22 kQ
R4=4.7kQ
R5=4.7kQ
C1 = 47JlF
C2=100nF

1,.

Switch
Water Pump Motor

1
-=

>--..J\Af.r------,

Gnd

Switch -

Motorola Master Selection Guide

4.9-9

Analog and Interface Integrated Circuits

Automotive ISO 9141 Serial Link Driver
MC33199D

TA

=-40° to +125°C, Case 751A

The MC33199D is a serial interface circuit used in
diagnostic applications. It is the interface between the
microcontroller and the special K and L Lines of the ISO
diagnostic port. The MC33199D has been designed to meet
the "Diagnosis System ISO 9141" specification.
The device has a bi-directional bus K Line driver, fully
protected against short circuits and over temperature. It also
includes the L Line receiver, used during the wake up
sequence in the ISO transmission.
The MC33199 has a unique feature which allows
transmission baud rate up to 200 k baud.

• Electrically Compatible with Specification "Diagnosis
System ISO 9141"
• Transmission Speed Up to 200 k Baud
• Internal Voltage Reference Generator for Line
Comparator Thresholds
• TXD, RXD and LO Pins are 5.0 V CMOS Compatible
• High Current Capability of DIA Pin (K Line)
• Short Circuit Protection for the K Line Input
• Over Temperature Shutdown with Hysteresis
• Large Operating Range of Driver Supply Voltage
• Full Operating Temperature Range
• ESD Protected Pins

Vs

Vee
REF-0UT
LO

REF-IN-L
REF-IN-K
11

RXD
DIA

TXD
Gnd

Analog and Interface Integrated Circuits

4.9-10

Motorola Master Selection Guide

Alternator Voltage Regulator
MC33092DW

TJ = -40° to +125°C, Case 7510
Provides voltage regulation and load response control in
diode rectified 12 V alternator charging systems. Provides
externally programmed load response control of the alternator
output current to eliminate engine speed hunting and vibration
due to sudden electrical loads. Monitors and compares the

system battery voltage to an externally programmed set pOint
value and pulse width modulates an N-channel MOSFET
transistor to control the average alternator field current. In
addition, has duty cycle limiting, under/overvoltage and phase
detection (broken belt) protective features.

Gate

Source

Sense
(Remote)

Lamp
Collector

Supply Reg
(Local)

Lamp Base

Phase

Ground

OscAdjust

Motorola Master Selection Guide

4.9-11

Analog and Interface Integrated Circuits

Automotive Electronic Circuits Package Overview

,

,

CASE 29
ZSUFFIX

CASE 221A
TSUFFIX

-

CASE 314B
TV SUFFIX

, • ,.

CASE 314D
T, T-1 SUFFIX

CASE 369
DT-1 SUFFIX

•

CASE 738
PSUFFIX

~

CASE 314A
TH SUFFIX

CASE 751
DSUFFIX

•

CASE 751G
DWSUFFIX

CASE 369A
DTSUFFIX

~

#
CASE 751 A
DSUFFIX

•

#

CASE 751D
DWSUFFIX

CASE 821C
TV SUFFIX

CASE 751E
DWSUFFIX

CASE 821D
TSUFFIX

•

CASE 936
D2TSUFFIX

Analog and Interface Integrated CircuHs

CASE 626
P, NO SUFFIX

CASE 936A
D2TSUFFIX

4.9-12

Motorola Master Selection Guide

Other Analog Circuits

In Brief ...
A variety of other analog circuits are provided for special
applications with both bipolar and CMOS technologies.
These circuits range from the industry standard analog
timing circuits and multipliers to specialized CMOS smoke
detectors. These products provide key functions in a wide
range of applications, including data transmission,
commercial smoke detectors, and various industrial
controls.

Motorola Master Selection Guide

4.10-1

Page

Timing Circuits .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Singles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Duals .....................................
Multipliers ....................................
Linear Four-Quadrant Multipliers .. . . . . . . . . . . ..
Smoke Detectors (CMOS) ......................
Package Overview ............................

4.10-2
4.10-2
4.10-2
4.10-2
4.10-2
4.10-3
4.1 Q-4

Analog and Interface Integrated Circuits

Timing Circuits

Multipliers

These highly stable timers are capable of producing
accurate time delays or oscillation. In the time delay mode of
operation, the time is precisely controlled by one external
resistor and capacitor. For a stable operation as an oscillator,
the free-running frequency and the duty cycle are both
accurately controlled with two external resistors and one
capacitor. The output structure can source or sink up to 200 mA
or drive TTL circuits. TIming intervals from microseconds
through hours can be obtained. Additional terminals are
provided for triggering or resetting If desired.

Linear Four-Quadrant Multipliers
Multipliers are designed for use where the output voltage is
a linear product of two input voltages. Typical applications
Include: multiply, divide, square, root-mealHlquare, phase
detector, frequency doubler, balanced modulator/demodulator,
electronic gain control.

Multiplier Transfer Characteristics

Singles
MC1455P1, D
TA = 0° to +70°C, Case 626,751
MC1455BP1, D
TA = -40° to +85°C. Case 626, 751
VCC
8
Threshold
Control
VoHage

-4.0 -2.0

7
Discharge

0

2.0

4.0

VX, INPUT VOLTAGE (V)

MC1494P

TA

= 0° to +70°C, Case 648

This device has all the necessary internal regulation and
references. The single-ended output is referenced to ground.

MC1495D, P

TA = 0° to +70°C, Case 751A, 646

Duals
MC3456P
TA =0° to +70°C, Case 646
NE556N, D
TA = 0° to +70°C, Case 646, 751A

Maximum versatility is assured by allowing the user to
select the level shift method.

MC1495BP

TA

=-40° to +125°C, Case 646

Linearity and offset are actually tested over temperature.
This is an improved specification over previous versions.

Analog and Interface Integrated Circuits

4.10-2

Motorola Master Selection Guide

Smoke Detectors (CMOS)
These smoke detector les require a minimum number of
external components. When smoke is sensed, or a low battery
voltage is detected, an alarm is sounded via an external

piezoelectric transducer. All devices are designed to comply
with UL specifications.

Table 1. Smoke Detectors (CMOS)
Low
Battery
Detector

Piezoelectric
Horn Driver

V

V

-

-

V

V
V
V
V
V
V
V

V

V

Recommended
Power Source

Unique
Feature

Ionization-Type
Smoke Detector

Battery

High Input Impedance
FET Comparator

Ionization-Type
Smoke Detector
with Interconnect

Battery

V

Line

-

Photoelectric-Type
Smoke Detector
with Interconnect

Battery

Function

Line

Photo Amplifier

Battery
Line
Ionization-Type
Smoke Detector

Battery

Ionization-Type
Smoke Detector with
Interconnect

Battery

V
(1)

Line
Photo Amplifier
Temporal Pattern
High Input Impedance
FET Comparator
Temporal Pattern

V
(1)

Complies
with
UL217
and UL268

Device
Number

Suffix!
Package

V
V
V
V
V

MC14467-1

P1/646

MC14578

P/648

V
V
V
V

MC145011

V

MC14468
MC14470
MC145010

P/648,
DW1751G

MC145012
MC145013
MC145017

P/648

MC145018

(1) Low-supply detector.

Motorola Master Selection Guide

4.10-3

Analog and Interface Integrated Circuits

Other Analog Circuits Package Overview

CASE 626
P1 SUFFIX

CASE 751
DSUFFIX

Analog and Interface Integrated Circuits

•

CASE 646
N, P, P1 SUFFIX

CASE 751A
DSUFFIX

4.10-4

•

CASE 648
PSUFFIX

CASE 751G
DWSUFFIX

Motorola Master Selection Guide

Tape and Reel Options

In Brief ...
Motorola offers the convenience of Tape and Reel
packaging for our growing family of standard integrated circuit
products. Reels are available to support the requirements of
both first and second generation pick-and-place equipment.
The packaging fully conforms to the latest EIA-481A
specification. The antistatic embossed tape provides a
secure cavity, sealed with a peel-back cover tape.

Motorola Master Selection Guide

Page
Tape and Reel ................................ 4.11-2
Analog MPQTable ............................ 4.11-4

4.11-1

Analog and Interface Integrated Circuits

Tape and Reel

Mechanical Polarization

SOIC DEVICES

PLCC DEVICES

User Direction of Feed
User Direction of Feed

DPAK DEVICES
Typical

User Direction of Feed

Tape Width
(mm)

Devlcell)
per Reel

ReetSlze
(inch)

Device
Suffix

SO-S, SOP--8
S0-14
S0-16

12
16
16

2,500
2,500
2,500

13
13
13

R2
R2
R2

SO-16L, SO-S+8L WIDE
SO-20LWIDE
S0-24L WIDE
S0-28L WIDE
S0-28L WIDE

16
24
24
24
32

1,000
1,000
1,000
1,000
1,000

13
13
13
13
13

R2
R2
R2
R2
R3

PLCC-20
PLCC-28
PLCC-44

16
24
32

1,000
500
500

13
13
13

R2
R2
R2

PLCC-52
PLCC-68
PLCC-64

32
44
44

500
250
250

13
13
13

R2
R2
R2

T0-226AA (TQ-92)(2)

18

2,000

13

RA, RE, RP, or RM
(Ammo Pack) only

DPAK

16

2,500

13

RK

Package

(1) Minimum order quantity is 1 reel. Distributors/OEM customers may break lots or reels at their option, however broken reels may not be returned.
(2) Integrated circuns in T0-226AA packages are available in Styes A and E only, with optional "Ammo Pack" (Suffix RP or RM). The RA and RP configurations
are preferred. For ordering infonnation please contact your local Motorola Semiconductor Sales Office.

Analog and Interface Integrated Circuits

4.11-2

Motorola Master Selection Guide

Tape and Reel

(continued)

TO-92 Reel Styles

STYLE A
(Preferred)

Feed

STYLE E

Feed

~-:::>"':r-------_----.J
Rounded side of transistor and adhesive tape visible.

Flat side of transistor and adhesive tape visible.

TO-92 Ammo Pack Styles
STYLE P
(Preferred)

STYLEM

Adhesive Tape On
TopSide

Adhesive Tape On
Top Side

Rounded Side

Flat Side

Carrier
Strip

Carrier
Strip

Flat side of transistor and
adhesive tape visible.

Rounded side of transistor and
adhesive tape visible.

Style P ammo pack is equivalent to Styles A and 8 of reel pack
dependent on feed orientation from box.

Motorola Master Selection Guide

Style M ammo pack is equivalent to Style E of reel
pack dependent on feed orientation from box.

4.11-3

Analog and Interface Integrated Circuits

Analog MPQ Table
TapeIReel and Ammo Pack

I

Package Type

Package Code

MPQ

Case 775
Case 776
Case 777

0802
0804
0801

1000/reel
5OD/reel
500/reel

Case 751
Case 751A
Case 7518
Case 751G
Case 7510
Case 751E
Case 751F

0095
0096
0097
2003
2005
2008
2009

2500/reel
2500/reel
2500/reel
1000/reel
1000/reel
1000/reel
1000/reel

Case 29
Case 29

0031
0031

2000/reel
2000/Ammo Pack

4.11-4

Motorola Master Selection Guide

PLCC

SOIC

T0-92

Analog and Interface Integrated Circuits

Communications, Power and
Signal Technologies Group Products

In Brief . ..
Page

Many leading semiconductor manufacturers have either
de-emphasized or eliminated discrete components from
their product portfolio. At Motorola, exceptional long-term
growth and outstanding customer acceptance of our
portfolio are the most significant effects of Motorola's
superiority in providing bipolar and MOS transistors, diodes,
thyristors, zeners, opto, RF, rectifier, and sensor devices.
Consistent, ongoing improvements in product
development and packaging processing continue to ensure
Motorola's position as the most broad-based discrete
supplier in the world. The increased use of automatic
placement equipment has driven the trend towards surface
mount packaging.
Motorola continues to expand upon a broad offering of
discrete surface mount packages which continue to
advance state-of-the-art designs that cannot be
accomplished with insertion technology. Surface mount
technology is cost effective, allowing users the opportunity
to utilize smaller units and increased functions with less
board space. In many electronic applications, complex
integrated solutions with a multitude of functions can replace
several active and passive components.
SMARTDISCRETES, RF hybrid amplifiers and modules
and RF monolithic integrated circuits, pressure and
temperature sensors, optoelectronics and hybrid power
modules are a few of the exciting new products which
provide more reliable, intelligent discrete devices. Key
initiatives to raise products and services to a Six Sigma
standard (99.9997% defect-free), reduce total cycle time in
all activities, and provide leadership in the areas of product
and manufacturing ensure that Motorola will continue to be
the manufacturer of choice for all your discrete
semiconductor requirements.

Motorola Master Selection Guide

Small Signal Transistors, FETs and Diodes
5.1-1
TVS/Zeners
TranSient Voltage Suppressors
Zener Regulator and Reference Diodes ......... 5.2-1
Hybrid Power Module Operation .................. 5.3-1
TMOS Power MOSFETs Products ................ 5.4-1
Bipolar Power Transistors ....................... 5.5-1
Rectifiers ...................................... 5.6-1
Thyristors and Triggers .......................... 5.7-1
Optoelectronic Devices .......................... 5.8-1
Sensors ....................................... 5.9-1
RF Products .................................. 5.10-1
Surface Mount Information ...................... 5.11-1
Tape and Reel Specifications
and Packaging Specifications .................. 5.12-1

5.0-1

Communications, Power and
Signal Technologies Group Products

Communications. Power and
Signal Technologies Group Products

5.0-2

Motorola Master Selection Guide

Small Signal Transistors,
FETs and Diodes

In Brief ...
New in this revision is Motorola's GreenLine™ portfolio of
devices. They feature energy-conserving traits superior to
those of our existing line of standard parts for the same
usage. GreenLine devices can actually help reduce the
power demands of your products.
Also, this section highlights semiconductors that are
the most popular and have a history of high usage for the
most applications.
It covers a wide range of Small Signal plastic and
metal-can semiconductors.
A large selection of encapsulated plastic transistors,
FETs and diodes are available for surface mount and
insertion assembly technology. Plastic packages include
TO-92 (TO-226M), 1 Watt T0-92 (T0-226AE), SOT-23,
SC-59, SC-70/S0T-323 and SOT-223. Plastic multiples
are available in 14-pin and 16-pin dual in-line packages for
insertion applications: SO-8, S0-14, and S0-16 for
surface mount applications.
Metal-can packages are available for applications
requiring higher power dissipation or having hermetic
requirements in TO-18 (T0-206AA) and T0-39
(T0-205AD).

Motorola Master Selection Guide

Page

Bipolar Transistors ............................. . 5.1-2
Plastic-Encapsulated Transistors ............. . 5.1-2
Plastic-Encapsulated Multiple Transistors ...... . 5.1-8
Plastic-Encapsulated Surface
Mount Transistors .......................... 5.1-10
Metal-Can Transistors ...................... 5.1-17
Field-Effect Transistors ........................ 5.1-19
JFETs ..................................... 5.1-19
MOSFETs ................................. 5.1-21
Surface Mount FETs ........................ 5.1-22
Tuning and Switching Diodes ................... 5.1-24
Tuning Diodes - Abrupt Junction ............. 5.1-24
Tuning Diodes - Hyper-Abrupt Junction ...... 5.1-28
Hot-Carrier (Schottky) Diodes . . . . . . . . . . . . . . .. 5.1-32
Switching Diodes ........................... 5.1-34
Multiple Switching Diodes .................... 5.1-38
GreenLine Devices ............................ 5.1-40

5.1-1

Small Signal Transistors, FETs and Diodes

l

Bipolar Transistors

1
23

ASE 29-05
TQ-226AE
1-WATT (TQ-92)

Plastic-Encapsulated
Transistors
Motorola's Small Signal TO-226 plastic transistors
encompass hundreds of devices with a wide variety of
characteristics for general-purpose, amplifier and switching
applications. The popular high-volume package combines
proven reliability, performance, economy and convenience to
provide the perfect solution for industrial and consumer design
problems. All devices are laser marked for ease of
identification and shipped in antistatic containers, as part of
Motorola's ongoing practice of maintaining the highest
standards of quality and reliability.

1

J

23

ASE29-G4
TQ-226AA
(TQ-92)

Table 1. Plastic-Encapsulated General-Purpose Transistors
These general-purpose transistors are designed for small-signal amplification from dc to low ratio frequencies. They are
also useful as oscillators and general-purpose switches. Complementary devices shown where available (Tables 1-4).

NPN

PNP

V(BR)CEO
Volts
Min

fT@lc
MHz
Min

Case 29-04 - T0-226AA (T0-92)
MPSB099
MPSA06

MPS8599
MPSA56

2N4410
BC546
BC546A
BC546B
MPSA05
BC182
BC237B
BC337
BC547
BC547A
BC547B
BC547C
MPSA20

BC556
BC556B
MPSA55
MPS2907A

BC212
BC307B
BC327
BC557
BC557A
BC557B
BC557C
MPSA70
-

MPS2222A
2N4401

2N4403

2N4400

2N4402

MPS6602

MPS6652

2N3903

2N3905

2N3904

2N3906

BC548
BC548A
BC548B
BC548C
2N4123
2N4124
BC338

BC558B
2N4125
2N4126
BC328

80
80
80
65
65
65
60
60
50
45
45
45
45
45
45
40
40
40
40
40
40

40
30
30

30
30
30
25
25

I

150
100
60
150
150
150
100
200
200(1)
150
210(1)
150
150
150
150
125
300
200
150
100
200
250
300(1)
300(1)
300(1)
300
200
250
210(1)

hFE @IC

mA

IC
mA
Max

Min

10
10
10
10
10
10
10
50
10
10
10
10
10
10
10
5.0
20
20
20
50
10
10
10
10
10
10
10
10
10

500
500
250
100
100
100
500
600
100
100
800
100
100
100
100
100
600
600
600
1000
200
200
100
100
100
100
200
200
800

100
100
60
120
120
180
100
100
120
200
100
120
120
180
380
40
100
100
50
50
50
100
110
120
200
420
50
120
100

I

Max

300

400
450
220
450
-

300
500
460
630
800
220
450
800
400
300
300
150
150
300
800
220
450
800
150
360
630

I

mA

NF
dB
Max

Style

1.0
100
10
2.0
2.0
2.0
100
150
2.0
2.0
100
2.0
2.0
2.0
2.0
5.0
150
150
150
500
10
10
2.0
2.0
2.0
2.0
2.0
2.0
100

10
10
10
10
10
10
10
10
10
6.0
5.0
10
10
10
10
6.0
4.0
-

1
1
1
17
17
17
1
1
14
17
17
17
17
17
17
1
1
1
1
1
1
1
17
17
17
17
1
1
17

(1) Typical
Devices listed in bold, italic are Motorola preferred devices.
Small Signal Transistors, FETs and Diodes

5.1-2

Motorola Master Selection Guide

Plastic-Encapsulated Transistors (continued)

Table 1. Plastic-Encapsulated General-Purpose Transistors (continued)

NPN

PNP

Case 29-05 BDC01D
BDB01C
MPS6717
MPSW06

V(BR)CEO
Volts
Min

". @

MHz
Min

I

IC

hFE @IC

IC
A

rnA

Max

Min

200
200
200
200
200

0.5
0.5
0.5
0.5
0.5

40
40
40
80
80

I

Max

VCE(sat) @ IC @ IB

I

rnA

Volts
Max

100
100
100
50
50

0.7
0.7
0.7
0.5
0.4

I

I

rnA

rnA

Style

100
100
100
10
10

1
14
1
1
1

TO-226AE (1-WATT T0-92)

BDB02D
BDC02D
BDB02C
MPSW56

100
100
80
80
80

50
50
50
50
50

400
400
400

-

1000
1000
1000
250
250

Table 2. Plastic-Encapsulated Low-Noise and Good hFE Linearity
These devices are designed to use on applications where good hFE linearity and low-noise characteristics are required:
Instrumentation, hi-fi preamplifier.
hFE@ IC

NPN

PNP

Case 29--04 -

-

-

MPS6428
BC239
BC550B
BC550C
MPSA18
MPS3904

BC549B
BC549C
2N5088
2N5089(6)
MPS6521
(1)
(2)
(4)
(5)
(7)
(8)

V(BR)CEO
Volts

Min

I

Max

I

rnA

VT(4)
rnV
Typ

NF(5)
dB
Max

".

MHz
Typ

Style

TQ-226AA (TQ-92)

2N5087
2N5086

BC560B
BC560C

MPS3906
MPS4250
BC559B
BC559C

MPS6523

50
50
50
45
45
45
45
40
40
30
30
30
25
25

250
150
250
120
180
380
500
100
250
200
380
350
450
300

800
500
650
800
450
800

0.1
0.1
0.1
2.0
2.0
2.0
1.0
10
10
2.0
2.0
1.0
1.0
2.0

300

450
800

600

7.0(7)
9.5

-

2.0
3.0
3.5(8)
2.0(1)
2.5
2.5

6.5(1)

-

-

5.0
2.0
2.5
2.5
3.0
2.0
3.0

40(2)
40(2)
100(2)
280
250
250
160
200(2)

250
250
50
50

-

1
1
1
17
17
17
1
1
1
17
17
1
1
1

Typical

Min
VT: Total Input Noise Voltage (see BC4131BC414 and BC4151BC416 Data Sheets) at RS = 2.0 kn, IC = 200 )lA, VCE = 5.0 Volts.
NF: Noise Figure at RS = 2.0 k.Q, IC = 200)lA, VCE = 5.0 Votts. f = 30 Hz to 15 kHz.
Rs= 10 kO, BW= 1.0 Hz, f= 100 MHz
Rs = 5000, BW= 1.0 Hz, f = 10 MHz

Devices listed in bold, italic are Motorola preferred devices.
Motorola Master Selection Guide

5.1-3

Small Signal Transistors, FETs and Diodes

Plastic-Encapsulated Transistors (continued)
Table 3. Plastic-Encapsulated Darlington Transistors
Darlington amplifiers are cascade transistors used in applications requiring very high-gain and input impedance. These
devices have monolithic construction.
hFE@IC

NPN

PNP

V(BR)CEO
Volts

IC
Max

Min

I

I

Max

IT @ IC

VCE(sat) @ IC & IB
rnA

Volts
Max

100
100
100
200
100
100
100
100
100
20

1.5
1.1
1.5
1.1
1.5
1.5
1.5
1.5
1.5
1.0

I

rnA

I

rnA

Min

0.1
0.25
0.1
0.2
0.1
0.5
0.5
0.1
0.1
0.1

125
100
150
125
125
125
200(1)

I

rnA

Style

10
100
500
10
10
10
10

1
1
1
17
1
1
1
1
1
17

Case 29-05 - T0-226AE (1-WATT T0-92)

Case 29-04 - T0-226AA (T0-92)
MPSA29

BC373
MPSA27
BC618
2N6427
2N6426

MPSA77
MPSA75
-

-

MPSA14

MPSA64

MPSA13
BC517

MPSA63
-

100
80
60
55
40
40
40
30
30
30

500
1000
500
1000
500
500
500
500
500
1000

160K
50K
200K
300K
-

10K
10K
10K
10K
10K
20K
30K
20K
10K
30K

-

100
250
100
200
100
500
500
100
100
100

Table 4. Plastic-Encapsulated High-Current Transistors
The following table is a listing of devices that are capable of handling a higher current range for small-signal transistors.

NPN

PNP

V(BR)CEO
Volts
Min

IT @ IC
MHz
Min

I

hFE @IC

rnA

IC
rnA
Max

Min

50
10
50
50
10

1000
500
2000
2000
1000

60
40
75
75
60

I I

VCE(sat) @ IC & IB

I

Max

rnA

Volts
Max

400
160
-

100
150
1000
1000
1000

0.3/0.5
0.5
0.5
0.5
0.5

rnA

I

rnA

Style

100
50
200
200
100

17
14
1
1
1

Case 29-05 - T0-226AE (1-WATT T0-92)

Case 29-04 - T0-226AA (TO-92)
BC489
BC639

BC490
BC640

MPS651

MPS751

MPS650
BC368

MPS750
BC369

80
80
60
40
20

200/150(1)
60
75
75
65

1000
500
2000
2000
1000

(1) Typical

Devices listed in bold, ~alic are Motorola preferred devices.
Small Signal Transistors, FETs and Diodes

5.1-4

Motorola Master Selection Guide

Plastic-Encapsulated Transistors (continued)
Table S. Plastic-Encapsulated High-Voltage Amplifier Transistors
These high-voltage transistors are designed for driving neon bulbs and indicator tubes, for direct line operation, and for
other applications requiring high-voltage capability at relatively low collector current. These devices are listed in order of
decreasing breakdown voltage (V(BR)CEO).

Device
Type

V(BR)CEO
Volts
Min

hFE@ IC

IC
Amp
Max

I

Min

rnA

Case 29-0S - TO-226AE (1-WATT TO-92) -

NPN

Case 29-0S - TO-226AE (1-WATT T0-92) -

PNP

IMPSW92 I

300

0.5

25

IT@IC

VCE(sat) @ IC & IB
Volts
Max

I

rnA

I

rnA

MHz
Min

I

Style

rnA

30

0.5

20

2.0

50

10

10
100
30
10
10
10

0.5
0.75
0.3
0.2
0.5
0.15

10
50
10
20
20
10

1.0
5.0
1.0
2.0
2.0
1.0

-

-

40
50
50
100

10
10
10
10

1
1
1
1
1
1

10
30
10
30
10

20
0.3
0.5
0.3
0.2

20
10
20
10
10

2.0
1.0
2.0
1.0
1.0

50
40
50
40
100

10
10
10
10
10

1
1
1
1
1

Case 29-04 - TO-226AA (T0-92) - NPN
BF844
MPSA44
2N6517
BF393
MPSA42
2N5551

400
400
350
300
300
160

0.3
0.3
0.5
0.5
0.5
0.6

50
40
30
40
40
80

Case 29-04 - TO-226AA (TO-92) BF493S
2N6520
MPSA92
2N6519
2N5401

350
350
300
300
150

0.5
0.5
0.5
0.5
0.6

PNP
40
30
40
45
60

Case 29-04 - TO-226AA (TO-92)

NPN
BF420
BF422

PNP

hFE@ IC

IT@lc

VCE(sat) @ IC & IB

V(BR)CEO
Volts
Min

IC
Amp
Cont

Min

rnA

Volts
Max

rnA

rnA

MHz
Min

rnA

Style

300
250

0.5
0.5

50
50

25
25

2.0
2.0

20
20

2.0
2.0

60
60

10
10

14
14

BF421
BF423

Devices listed in bold, italic are Motorola preferred devices.
Motorola Master Selection Guide

5.1-5

Small Signal Transistors, FETs and Diodes

Plastic-Encapsulated Transistors (continued)

Table 6. Plastic-Encapsulated RF Transistors
The RF transistors are designed for small-signal amplification from RF to VHF/UHF frequencies. They are also used as
mixers and oscillators in the same frequency ranges.

Device
Type

hFE@IC

IC
rnA
Max

V(BR)CEO
Volts
Min

Min

Case 29-04 - TO-226AA (T0-92) - NPN
BF224
MPSH24
MPSH20

MPSH07A(9)
MPS3866
MPSH11
MPSH10

BF199
BF959
MPSH17
MPS918
MPS5179

MPS3563
MPS6595

30
30
30
30
30
25
25
25
20
15
15
12
12
12

50
50
100
25
400

I

30
30
25
20
10
60
60
40
40
25
20
25
20
25

-

100
100

-

50
50

50
50

rnA

I

IT

VCE
V

MHz
Typ

10
10
10
10
5.0
10
10
10
10
10
10
1.0
10
5.0

600
400(2)
400(2)
400(2)
500(2)
650(2)
650(2)
750
600(2)
800(2)
600(2)
2000(3)
800
1200(2)

7.0
8.0
4.0
3.0
50
4.0
4.0
7.0
20
5.0
8.0
3.0
8.0
10

CRE/CRB
pF
Max

NF
dB
Typ

f
MHz

0.28
0.36
0.65
0.3

2.5

100

-

-

-

-

3.2(3)

-

0.9
0.65
0.35
0.65
0.9
1.7

100

-

2.5
3.0
6.0(3)
6.0(3)
5.0(3)
6.0(3)

1.7
1.3

35
200
200
60
200
60

-

-

Style

21
2
2
1
1
2
2
21
21
2
1
1
1
1

Case 29-04 - TO-266AA (T0-92) - PNP

Table 7. Plastic-Encapsulated High-Speed Saturated Switching Transistors
ton & toff @ IC
Device
Type

ns
Max

I

ns
Max

I

V(BR)CEO
Volts
Min

rnA

hFE@IC
Min

I

IT @ IC

VCE(sat) @ IC & IB

rnA

Volts
Max

I I
rnA

rnA

MHz
Min

I

rnA

Style

10
10
30

1
1
1
1

Case 29-04 - T0-226AA (TO-92) - NPN
2N4264
2N4265
MPS3646
MPS2369A

25
25
18
12

35
35
28
18

10
10
300
10

15
12
15
15

40
100
30
40

10
10
30
10

0.22
0.22
0.2
0.2

10
10
30
10

1.0
1.0
3.0
1.0

300
300
350

-

-

12

30

50

0.15

10

1.0

700

10

Case 29-04 - T0-226AA (T0-92) - PNP

IMPS4258 I

15

I

20

I

10

I

(2) Min
(3) Max
(9) AGC Capable

Devices listed in bold, ijalic are Motorola preferred devices.
Small Signal Transistors, FETs and Diodes

5.1-6

Motorola Master Selection Guide

Plastic-Encapsulated Transistors (continued)
Table 8. Plastic-Encapsulated Choppers

oeVlces
. are

Isted'In decreaslng vI(BR)EBO.

Device
Type

hFE @ IC

IC
Arnp(1)
Max

V(BR)EBO
Volts
Min

Min

Case 29-04 - TO-226AA (TQ-92) - NPN

I

for@IC

VCE(sat) @ IC & IB

rnA

Volts
Max

-12

-0.2

I

rnA

I

MHz
Min

rnA

I

rnA

Style

Case 29-{)4 - TQ-266AA (TQ-92) - PNP

I

MPS404A

I

-25

I

-150

I

30

-24

1.0

Table 9. Plastic-Encapsulated Telecom Transistors
These devices are special product ranges intended for use in telecom applications.

Device
Type

V(BR)CEO
Volts

PDrnW
25°C
Arnb

IC
rnA
Cont

hFE@IC@VCE
Min

Case 29-{)4 - TO-226AA (TQ-92) - NPN

I

Max

I

rnA

for

I

Volts

MHz
Min

Style

P2N2222A
PBF259,S(10)

Case 29-04 - TQ-226AA (TQ-92) - PNP
P2N2907A
PBF493,S(11)
(1) Typical
(1 0) "S" version, hFE Min 60 @ Ie 20 mA, VeE 10 v.
(ll)"S" version, hFE Min 40 @ Ie = 0.1 mA, veE = 1.0 V.

=

=

Devices listed in bold, italic are Motorola preferred devices.
Motorola Master Selection Guide

5.1-7

Small Signal Transistors, FETs and Diodes

Plastic-Encapsulated
Multiple Transistors
The manufacturing trend has been toward printed circuit
board design with requirements for smaller packages with
more functions. In the case of discrete components the use of
the multiple device package helps to reduce board space
requirements and assembly costs.
Many of the most popular devices are offered in the
standard plastic DIP and surface mount Ie packages. This
includes small-signal NPN and PNP bipolar transistors,
N-channel and P-channel FETs, as well as diode arrays.

1
CASE 646-06
(TO-116)
STYLE 1

CASE 751 B-05
50-16
STYLE 4

Specification Tables
The following short form specifications include Quad and Dual transistors listed in alphanumeric order. Some columns
denote two different types of data indicated by either bold or italic typeface. See key and headings for proper identification.
This applies to Table 10 and 11 of this section only.

KEY
Unit

Subscript

Po

TYPE NO.

10

Watts
One
Die
Only

VCE
Volts

Alphanumeric listing
type numbers

IC
Amp
Max

Gp

--+11---0 2,4

CASE 318E-04
SOT-223

3

STYLE 2

Typical Characteristics
Diode Capacitance versus Reverse Voltage
20
18

~ 16

"

~ 14

z
~ 12

~ 1~

II

w

32
28

z 24
~ 20

.......

I

ct.

.....

«
()

I

II
II

2

o

~

()

TA = 25°C
f= 1 MHz

6

Ci 4
,.:.

()

~

36

I

"'\

I

I

MM8Vl09LTl
MV209

[5

w

8

40

I I
I I
IMMIBV\O~G~~11

to-..

0.3

0.5

i'
2

3

5

10

,.:. 12

-

20

16

()

8

-

"""

3

30

10

30

VR, REVERSE VOLTAGE (VOLTS)

VR, REVERSE VOLTAGE (VOLTS)

Figure 1. Diode Capacitance

Figure 2. Diode Capacitance

Small Signal Transistors, FETs and Diodes

5.1-28

100

Motorola Master Selection Guide

Tuning Diodes -

Hyper-Abrupt Junction (continued)

40

10

"

UJ

a

z

oi"
if

9

\.

~ 32
24

~
w

"

a
z

i\

(§ 16

a
w
o

w

o

a

MMBV809LT1

I".....

.......

3

o

f-

.......

4

a

.........

o

i'..

i"
o
if
«

MMBV409LT1
MV409

,

-

i'--

f-

a

a

o

1

1

o0.5

10
20
VR, REVERSE VOLTAGE (VOLTS)

4 5

Figure 3. Diode Capacitance

40

~

36
32

a

28

w

o~

........

......

24
20

if
«
~

o

f-

a

i"
0
if

f~1

............

r--....

8

I I I I

r--.....
3

5

10

a
0

,.: 10

....... l- i20

.......

a

o1

30

7

Figure 5. Diode Capacitance

Figure 6. Diode Capacitance
Each Die

~

500

.......

~

..........
..........
100

40

MVAM109/MV7005T1

......

z

i"

30

1000

500

w

20

VR, REVERSE VOLTAGE (VOLTS)

MVAM10S

a

10

VR, REVERSE VOLTAGE (VOLTS)

1000

u::s

MHz-

MMBV609LT1

" ......

0

4

1

........

20

w

0.5

r-....

30

«

0.3

40

z

a

TA ~ 25°C
f~ 1 MHz

o

~

w

a

MMBV3102LT1
.........

16
12

8

50

I I I I III

,

15

Figure 4. Diode Capacitance

I II
I II

r--

8 10

VR, REVERSE VOLTAGE (VOLTS)

~

oi"

..........
I'....

UJ

az

100

,

if

(§ 50

.......

f-

a

(§ 50
f-

a

10

10

4

3

7

VR, REVERSE VOLTAGE (VOLTS)

VR, REVERSE VOLTAGE (VOLTS)

Figure 7. Capacitance versus Reverse Voltage

Figure S. Capacitance versus Reverse Voltage

Motorola Master Selection Guide

5.1-29

Small Signal Transistors, FETs and Diodes

Tuning Diodes -

Hyper-Abrupt Junction (continued)
MVAM115

MVAM125

1000

1000

500

500

u:::-

.......

.s

.......

w

~

~loo
o

u:::-

,

w

~

~ 100

~

i3

cf

«

<-:f-

"' "-

.s

cf

50

<3,.:.

....... I-

o

10

2

50

r- r-

o

6
10
14
VR. REVERSE VOLTAGE (VOLTS)

10

18

Figure g. Capacitance versus Reverse Voltage

2

.s

~

~

i3

......
.....
.......

100

cf

<3

=

c........

........

J'..

1= 1= MVl405

50 t--

w

~
Cl

,.:.
o

26

TA-25°C
1=1 MHz _

~

200

10
14
18
22
VR. REVERSE VOLTAGE (VOLTS)

Figure 10. Capacitance versus Reverse Voltage

500

u:::- 3O0

6

30 t - - r- MVl403
20

/

'"I" r-...r-.., ..... r-.. ..... r-..,

/

r-..
r-.: r::--

r-.. r-..

1/

I

10 t - - r- MVl404

MV7404Tl
2
3
4
5
6
7
VR. REVERSE VOLTAGE (VOLTS)

10

8

Figure 11. Diode Capacitance versus Reverse Voltage
Table 44. Hyper-Abrupt Tuning Diodes for Telecommunications - Single
The following is a listing of hyper-abrupt tuning diodes intended for high frequency. FM radio. and TV tuner applications.

Or @ VR (f =1.0 MHz)
pF
Min

Device

I I
pF
Max

Cap Ratio @ VR

Volts

Min

25
3.0
3.0
2.0
3.0

3.0

J I

Q

3.0V 150 MHz
Min
Max

Max

Volts

4.0
5.0
1.5
1.8
4.5

6.5
6.5
1.9
2.6

3125
3/25

-

2/8
3/25

200
200
200
300
200

5.0

6.5

3/25

200

V(BR)R
Volts

Device
Marking

Case
Style

CV
Curve
Fig

30
30
20
20
30

M4E
M4A
X5
5K
M4C

8
8
8
8
8

1
2
3
4
5

30

M4A

8

Case 182-02 - TQ-226AC (TQ-92)
MV209
MV409

MMBV105GLT1
MMBV109LTf
MMBV409LT1
MMBV809LT1
MMBV3102LTl

1.5
26
26
4.5
20

2.8
32
32
6.1
25

318

-

Case 419-02 - SC-70/S0T-323

IMBV109T1

I

26

I

32

Devices listed in bold. italic are Motorola preferred devices.
Small Signal Transistors. FETs and Diodes

5.1-30

Motorola Master Selection Guide

Tuning Diodes -

Hyper-Abrupt Junction (continued)

Table 45. Hyper-Abrupt Tuning Diodes for Communications - Dual

=1.0 MHz)

CT @ VR (f
Device

pF
Min

I I
pF
Max

Cap Ratio @ VR

Volts

Min

3.0

1.8

I I

Q

Max

Volls

3.0V
Min

2.4

3/8

250

150MHZ
Max

V(BR)R
Volts

Device
Marking

Case
Style

CV
Curve
Fig

20

5L

9

6

Case 318-08 - TO-236AB (SOT-23)
IMMBV609L-r1

26

32

Table 46. Hyper-Abrupt Tuning Diodes for Low Frequency Applications - Single
The following is a listing of AM, hyper-abrupt tuning diodes that have a large capacity range and are designed for low
frequency circuit applications.
CT@ 1.0 MHz
Device

pF
Min

I

pF
Max

. Case 182-02- TO-226AC (T0-92)
MVAM10B
MVAM109
MVAM115
MVAM125

440
400
440
440

i

560
520
560
560

Cap Ratio@VR
Volts

Min

1.0
1.0
1.0
1.0

15
12
15
15

-'

Volts

V(BR)R
Volts

Style

1.0/8.0
1.0/9.0
1.0/15
1.0/25

12
15
18
28

1
1
1
1

CV
Curve
Figure

7

8
9
10

Table 47. Hyper-Abrupt High Capacitance Voltage Variable Diode - Surface Mount
The following are high capacitance voltage variable diodes intended for low frequency applications and circuits requiring
large tuning capacitance.
CT @ f
Device

Min
pF

IR
nA

V(BR)R
Volls

Case 318E-04- SOT-223

=1.0 MHz

I

Max
pF

Cap Ratio
Min

Q
Min

Slyle

CV
Curve
Figure

Pinout: 1-Anode, 2, 4-Cathode, 3-NC
MV7005T1
MV7404T1

Table 48. Hyper-Abrupt High Capacitance Tuning Diodes - Axial Lead Glass Package
CT@VR
Device

pF
Min

I

pF
Max

Case 51-02 - DO-204AA (00-7)
MV1404
MV1403
MV1405

96
140
200

144
210
300

I

Volls

Cap Ralio
C2IC10
Min

Q
2.0 V, 1.0 MHz
Min

V(BR)R
Volts

Style

CV
Curve
Figure

2.0
2.0
2.0

10
10
10

200
200
200

12
12
12

1
1
1

11
11
11

(26) VR = 1.0VNR =9.0 V
(27) VR = 2.0 VNR = 10 V
(28) VR = 1.0 V, f = 1.0 MHz
(29) VR = 2.0 V, f = 1.0 MHz

Devices listed in bold, italic are Motorola preferred devices.
Motorola Master Selection Guide

5.1--31

Small Signal Transistors, FETs and Diodes

II

Hot-Carrier
(Schottky) Diodes

1

~

STYLE 1

1 0--114----0 2
Cathode

1~3
1

CASE 318-0S
To-236AB
SOT-23

•

10

STYLE 9

STYLE 19
l o

3
COMMON CATHODE

~0.9

~

.90
w
(.)

Z

;'!:
[5

............

0.8

r--.....

ct:

t5

li 0.7

-

l"'t l"' 02
b SERIES
3

2.8

I
- TA = 25°C -

I

2

~

.90
w
(.)

z 1.6
;'!:

----

ct:


100
70
50

30

fi)

16 OHMS

300

....

-

a.

::;;

\ ...... .... i-'

-

30

IIII

~