1996_NEC_Dynamic_RAMS 1996 NEC Dynamic RAMS

User Manual: 1996_NEC_Dynamic_RAMS
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NEG Electronics Inc.

NEe

Dynamic RAM
Spring 1996 Data Book

Document No. M10547EJ4VODBU1
©1996 NEG Electronics Inc. All rights reserved.
Printed in the United States of America.

No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics Inc.
(NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE
PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALE ONLY, INCLUDING THE LIMITATION OF LIABILITY,
WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding information
set forth herein or regarding the freedom olthe described devices from patent infringement. NECEL assumes no responsibility for any errors
that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The
devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace
equipment, submarine cables, nuclear reactor controklystems and life support systems. "Standard" quality grade devices are recommended
for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and
visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti·disaster and anticrime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliability requirements
for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or
systems or in any application where failure could result in injury or death. "customers wish to use NECEL devices in applications not intended
by NECEL, customer must contact the responsible NECEL sales people to determine NECEL's willingness to support a given application.

i ,~

11

'~
Iii

Index

i

!j
I.

'/

1Selection Guide 11---------------------

~"

1

;
(I

1

"

Hyper Page Mode (EDO)

64MDRAM

3.3V

+

0.3V 1 - - - - - -

11

;1

,

!f
16M DRAM

Fast Page Mode

I------,--l

5.0V

+ 10% 1 - - - - - -

3.3V

+

0.3V f - - - - - - 263

455

4MDRAM

5.0V ± 1O%,5.0V ± 5%

1M DRAM

5.0V

+ 10% 1 - - - - - - 503

64M DRAM

3.3V

+ 0.3V 1 - - - - - - 585

16M DRAM

5.0V

+ 10% 1 - - - - - - 671

3.3V

+ 0.3V 1 - - - - - - - 773

5.0V

+

4MDRAM

,;,

115

10%

1-------

875

ISynchronous DRAM 1-1------------------ 975
IHow to Use DRAM 1-1------------------ 981
NEC Semiconductor Device Reliability / Quality Control System 1 - - - - - - - - 1067
iii

. . . . - - - - - - - - NOTES FOR CMOS DEVICES - - - - - - - ,

 tRAD (MAX.) and tRCO:li tRco (MAX.)

tAA(MAX.)

tRAD + tv. (MAX.)

tRCD > tRCD (MAX.I

tCAC (MAX.)

tRcO + tCAC (MAX.I

tRAO(MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAc, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD

ii: tRAO(MAX.)

and tRCO i:

tRCD(MAX.) will not cause any operation problems.

2. tCRP(MIN.1 requirement is applied to RAS, CAS cycles.

Reid Cycle
tRAC. 50 ns
Parameter

Symbol

tRAC. 60 ns

tRAC. 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

60

-

70

ns

1

16

-

18

ns

1

30

-

36

ns

1

16

-

18

os

-

ns

Unit Notes

Access Time from RAS

tRAC

-

60

Access Time from CAS

tCAC

13

Access Time from Column Address

tAA

-

26

Access Time from OE

tOEA

-

13

Column Address Lead TIme Referenced to RAS

tRAL

26

30

-

36

Read Command Setup Time

tRCS

0

0

-

0

Read Command Hold Time Referenced to RAS

tRRH

0

0

tRCH

0

-

-

Read Command Hold TIme Referenced to CAS

-

0

Output Buffer Turn·off Delay Time from OE

tOEZ

0

10

0

13

0

6

-

6

-'

6

CAS Hold Time to OE

Not.. 1.

tCHO

0
0

ns
ns

2

-

ns

2

16

ns

3

-

n8

For read cycles, access time is defined as follows:
Input Conditions

Access Time

Access Time from RAS

tRAD;:a; tRAD (MAX.) and tRCD;:a; tRCD (MAX.)

.t RAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.I and tRCD;:ii tRCD (MAX.)

tAA(MAX.)

tRAD + tAA (MAX.I

tRCD > tRCD (MAX.)

tCAC (MAX.I

tRCD + tCAC (MAX.)

tRAO(MAX.1 and tRCD(MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD 5; tRAO(MAX.1 and tRCD

ii:

tRCD(MAX.1 will not cause any operation problems.
2.

Either tRCH(MIN.) or tRRH(MIN.1 should be met in read cycles.

3.

tOEZ(MAX.1 defines the time when the output achieves the condition of Hi-Z and is not referenced to
VOH or VOL.

23

NEe

~PD4264405,4265405

Write Cycle
Parameter

Symbol

tRAc.50 ns

tRAC. 60 ns

tRAc.70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

10

-

10

-

ns

1

-

ns

1

-

ns

-

ns

WE Hold Time Referenced to CAS

twCH

7

WE Pulse Width

twp

7

-

WE Lead Time Referenced to RAS

tRWL

10

-

WE Lead Time Referenced to CAS

tCWL

7

twcs

0

WE Setup Time
OE Hold Time

tOEH

0

Data-in.Setup Time

tDs

0

Data-in Hold Time

tDH

7

-

10
10
10
0
0
0
10

10
12
12
0
0
0
10

Unit Notes

ns
ns
2

ns

3

ns

3

Not.. 1. twPIMIN.1 is applied to late write cycles or read modify write cycles. In early write cycles, twcHIMIN.1
should be met.
2. If twcs

s: twcslMIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the

entire cycle.
3. tOSIMIN.1 and tDHIMIN.1 are referenced to the CAS falling edge in early write cycles. In late write cycles
and read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
tRAC. 60 ns

tRAC. 60 ns

tRAC. 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

tRWC

107

-

133

-

167

RAS to WE Delay Time

tRWO

-

77

-

89

-

ns

64

ns

1

CAS to WE Delay Time

tCWD

27

-

ns

1

47

-

37

tAwo

-

32

39

54

-

ns

1

Parameter
Read Modify Write Cycle Time

Column Address to WE Delay Time

Not. 1.

If twcs

s: tWCSlMIN.1 the cycle

entire cycle. If tRWD

Symbol

Unit Notes

is an early write cycle and the data out will remain Hi-Z through the

s: tRWDIMIN.I, tCWD s: tCWDlMIN.I, tAWO s: tAwoIMIN.I, and tCPWD iii; tCPWDlMIN.I, the cycle is a

read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.

24

5_~--'

___N_E_C
_______________........;IJ.;...P_D42
_ _6440
_ _5_,_42_6_540
__

'I

Hyper 'age Mode
Parameter

Symbol

tRAc.60 ns

tRAC. 60 na

tRAC .70 na
Unit Notei

MIN.

MAX.

MIN.

MAX;

MIN.

MAX.

-

30

-

na

Read I Write Cycle Time

tlf'C

20

-

26

iiAS Pulse Width

tRAIl'

60

126000

60

2600(

70

26001

ns

CAS Pulse Width

tHcM

7

10000

10

10000

12

10000

ns

CAS Precharge Time

tcp

.7

-

10

-

10

~

ns

Access Time from CAS Precharge

lAcP

-

30

-

36

-

40

na

CAS Precharge to WE Delay TIme

tCPWD

41

69

-

ns

tRHCP

30

Read Modify Writa Cycle Time

tHPRWC

62

Data Output Hold Time

tDHc

6

OE to CAS Hold Time

tOCH

6

OE Precharge Time

toeP

6

-

Output Buffer Turn-off Delay from WE

lwEz

0

10

0

13

WE Pulse Width

twpz

7

-

10

-

Output Buffer Turn-off Delay from RAS

tOFR

0

10

0

Output Buffer Turn-off Delay from CAS

tOFC

0

10

0

RAS Hold TIme from

CAS Precharge

-

-

-

62
36
66
6
6
6

-

40
76

-

I

:~

t
2

1

na
ns

-

n8

0

16

ns

10

-

n.

4

13

0

16

ns

3.4

13

0

16

ns

3.4

-

6

5
6

II,

1

I

n.
n.

i

!

3,4

'1.

I:!

i:

,I

11

Note. 1.
2.

II

tHPCIMIN.1 is applied to access time from CAS

I:J

If twcs !1: twCSIMIN.I, the cycle is an early write cycle and the data out will remain Hi - Z through the
entire cycle. If tRWD

s:: tRWDCMIN.I, tCWD ~ tcwDCMIN.I, tAWD ~ tAWDCMIN.I, and tCPWD ~ tCPWDIMINJ, the cycle is

a read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.
3.

tOFCIMAX.I, tOFRIMAX.1 and twEZIMAX.1 define the time when the output achieves the condition of Hi-Z and

4.

To make II0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The

is not referenced to VOH or VOL.
effective specification depends on state af each signal.
(1) RAS, CAS : I~active (at the end of read cycle)

WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE : inactive, OE : inactive ... tOEZ is effective.

---

---

---

---

(3)· Both RASand CAS are inactive or·RAS is active and CAS·is·inactive
(at the end of read cycle)
WE,OE:active and either tRRH or tRCH must be met.. • lwEz, tWPz are effective.

25

NEe

~PD4264405,4265405

Refresh Cycle
tAAc - 50 ns

Parameter

Svmbol

~SetupTime

~ Hold Time ~ before

26

RAS Refresh)

MIN.

MAX.

tCBA

5

tCHR

10

-

RAS Precharge ~ Hold Time

tApe

5

WE Setup Time

twsR

10

WE Hold Time

twHR

15

tAAc.60 n8

MIN.

MAX.

5

-

10'
5
10
15

-

tAAC"

70 n8

MIN.

MAX.

5

-

10
5
10
15

Unit
ns
ns
ns
ns
ns

Note

I~

NEe

yPD4264405, 4265405

---.;;.,.;;;;.;:::::;.;=-------------------------';.;.;;....;;....;.;;;;.;...,;...;;...;;..;;...<..-.;;;;.;;;;...;;....;;..;..,;;;..------

:;.~
i~:~

Ii

Read Cycle

II

IRe

RAS

VIHV,L-

I'i';

j
I'i'

tCSH

'i
I

V,HCAS V,L-

1:1
Address V,HV,L-

.~

!

DE V,HV,L- - ...........................t-'....................+-......,.......-+. . . . .""'"-'....................+-:------;-t---''"t''r---t-'............~
tCAe
tOll
tell

Vot<- ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Hi· Z
I/O Vrx-

tOFR

Data out

Hi·Z

27

NEe

yPD4264405,4265405

Early Write Cycle
tAc
tAp

tFIAS

RAS

V, ...
V,LtcSH

CAS

V,iiV,L-

Address

V,...
V,L-

1/0

V,iiV,L- .........................,"-"........-.;......., "--_ _ _ _ _ _ _ _....JI

Remark DE: Don't care

28

""'-'~...................................................

" - '......................

~~

,I

_ _.:..:N::.::E==C=--_ _ _ _ _ _ _ _ _ _ _ _ _ _...r:.Il::.P..::;D;...;;4~26;:;..44.:....;;.;:0;.:.5:...,4.:.,:2:.:6:;:5:...:.4.;;.;05::;..-._ _ _ :,1
Lite Write Cycle
If<:
lRAS

I

Address

29

,I~

NEe

gPD4264405,4265405

Read Modify Write Cycle
tRWe

tAAs

V,ii-

V,lteSH
!ASH

tACO

Address

V,ii-

V,l-

WE

V,iiVIl-

OE

V,iiVIl-

tOEH

tOEA

tCAe

VO

V,iiVIl-

~--------- - ------- -

tos

toH

Data in

tOLZ

VO

30

VOIiVOl-

Hi-Z

Hi-Z
--.-----------------------------_.

"

_ _.;..N__E~C~_ _ _ _ _ _ _ _ _ _ _ _ _ _.....JL=P...;;;;D__4=2.;;.,64.;..4.;.;0;..;;;.5..:...,...;;.,;42=6;;.,;;5__4.;;.,05;;;...'_ _ _
Hyper Paga Mode Raad Cycle
IRAsp

RAS

VIHVIL-

tHPC

tcSH

CAS

IRp

V'HVIL-

~

Address

WE

VIHVIL-

tHCAS

IRCD

J
~

VIHV'L-

~

IRHCf'

"

e~~~

~~

tHCAS

~
r
-,

~

~~

tHCAS

1~

l®:)

Col.

'-

IRSH

-

~

YI

OE

V'HVIL-

Remark

X.

Col.

fo-

\\\\\\\\\\~
I
L

'-

~~
RH

'\ }i/

~

tAcp

tAcP
fAA
teAe

fAA
teAe

/

~

\\ .\

tRAc
fAA

teAe

VOHVOL-

tcFR
toFe

/////fl '

I

VO

J

Ci
XXX

IR~

~

~

toez

~

~

-------------- _til :J.. ___ ------ -1~

Data out

--0

Data out

~--{)l

Data out

---

In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

31

1

IfI

NEe

yPD4264405,4265405

Hyper Page Mode R.ad Cycl.IWE Control!

tRHCP

tCSH

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

I/O

VOH-

VOL-

••••••••••••••• ':I1:.Z.•••..•••..

Data out

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

32

1',*
.~

NEe

,uPD4264405,4265405!

- - - . . . . . ; ; . . . . ; ; ; ; . . : : : ; ; . ; : : : : ; . . , - - - - - - - - - - - - - - - - - - - - - - - -......=...;;;;.....;;.;;;;.;;;...;;~;;.;;;~..;:.;;;=.~=.~-----~ !

t,

.1

Hyper Page Mode Read Cycle 1i5E Control)

~

tAASP

--"

It
,t

tAHOP

',fl.

teSH

J
Address

~

tAco

~

tHCAS

\\
~

m~

~~
ColA

I

tAf-I

J
1+

CoI.C

XXX

~

tOES

tOEA

~

~

__________ ~;l___________

~

\.. I - -

/
~

tcHO

lACp

,.--,

tell

~~
----

lACp

~

~

~ ~

..........

~

OEA

-!2!4

"'I-io--

tOFR

\\\\

tAA

tOCH

i-

~

.... ---1 tRRI-

J!;AC

teHo

\.-

.. ~H

tAA

~

\\\\\\\\\\\
Remark

COl.sm ).

tAA

toeH

VOH-

/

~~

~~

tAAe

/////!

VO VOL-

r-4

tHCAS

tAAt

Row

WE

~
r----..

tHeAS

r----,

~

V,HV,l-

tRSH

tHPC

~

tOEZ

V

\~\\

,......!2g.."

~ Oata B)-----1~ Data out B ---1~ Data out C __

11!;~_

out

In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

33

NEe

HPD42~4405,4265405

Hyper Pa". Mode Early Writ. Cycl.

Address VII.VIL-

Remarks 1. OE: Don't care
2. In the hyper page mode, read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

34

NEe

If
'i
!~

gPD4264405. 4265405

----~~~~~--------------------------------------~-~~~~~~~~~~--------~.~(
i~
I

Hyper Page Mode Lete Write Cycle

Remark

In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

35

':~

NEe

yPD4264405,4265405

Hyper Paga Mode RNd Modify Write Cycle

V,iiVIL-

V,iiVIL-

Address

V,iiVIL-

V,iiVIL-

V,iiVIL-

I/O VOl....l.-l...l...Tlo....:l....J.......I"-t-l.....l.....l..r~~=---+,.....--..t...I-1--....l....\....l...~~:....rl....J.......I-

VOHHi-Z
110 Vcx.- -------------------------------------------

Data out

Hi-Z

39

NEe

yPD4264405,4265405

Hidden Refresh Cycle (Write)

tAC
tAAs

V,HVIl-

Address

va

V,HVIl-

V,HVIl-

--J..............................................,..._ _

V,HVIl-

L...l.......' - "..........IL........."-..l.......~ 1\._ _ _ _--"

+_I---',........J

Remark OE: Don't care

40

tAC

tAAS

I,

,y

_.......!N~E:=::C~_ _ _ _ _ _ _ _ _ _ _ _ _--.s::.y:.:..P=-D..:.:42=.:::6:...;;4..:.40=.:::5;.:.,...:.4=26::;.;:5;...;;4~O5~_ _ _ :1
Package Drawings

32PIN PLASTIC TSOP(II) (400 mil)
32
detail of lead end

-++-----+------t-

~h~luuu~t~t'oOJ~
01$1

M

@I

NOTE

Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

~Jmmmm

H

I

mmm .~

J

L

ITEM

MILLIMETERS

INCHES

A
B
C

21.17 MAX.
1.075 MAX.
1.27 (T.P.)

0.834 MAX.
0.043 MAX.
0.050 (T.P.)

0

0.42~8:89

0.017±0.003

E
F
G

0.1:t0.05
1.2 MAX.
0.97
11.76:t0.2
10.16:t0.l

0.004%0.002
0.048 MAX.
0.038
0.463:t0.008
0.400:1:0.004

H

0.8:1:0.2

0.031 ~8:883

K

0.145~8:8~g

0.006:t0.00l

L

0.5:t0.l

0.020:8:88~

M

0.21
0.10
3 0 + 70
-3'

0.009
0.004

N

P

I':
,I

I,'

3 0 +7•

-3'

S32G5-50-7 JD2

41

NEe

yPD4264405,4265405

32 PIN PLASTIC SOJ (400 mill

-tt-------+--------i-UQ

16
E

P32LE-400A
NOTE

Each lead centerline is located within 0.12 mm
(0.005 inch) of its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

i

8

21.06:0.2

0.829:0.008

i

C

10.16

0.400

0

11.18:0.2

0.440:0.008

I
I

E

1.005:0.1

0.040:8:g~

I

F

0.74

0.029

!

G

3.5:0.2

0.138:0.008

H

2.545:0.2

0.100:0.008

0.8 MIN.

0.031 MIN.

2.6

0.102

1.27 (T.P.)

0.050 (T.P.)

M

0.40:0.10

0.016:8gg~

N

0.12

0.005

P

9.4:0.20

0.370:0.008

Q

0.1

0.004

T

R 0.85

R 0.033

U

0.20:8~g

0.008:8gg~

J
K

42

INCHES

,

I

:

~
',i!,

PRELIMINARY DATA SHEET

r------------------------------------------------MOS INTEGRATED CIRCUIT

NEe

I'

~PD4264805,4265805
64 M-BIT DYNAMIC RAM
8 M-WORD BY 8-BIT, HYPER PAGE MODE

- - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _

I~

II
Description
The IlPD4264805, 4265805 are 8,388,608 words by 8 bits CMOS dynamic RAMs with optic;mal hyper page mode.
Hyper page mode is a kind of page mode and is useful for the read operation.
The IlPD4264805, 4265805 are packaged in 32-pin plastic TSOP(lI) and 32-pin plastic SOJ.

:1
"II

Features
• Hyper page mode
• Single +3.3 V±0.3V power supply
• 8,388,608 words by 8 bits organization
Access time
(MAX.)

Part number

RJW cycle time
(MIN.)

Hyper page mode
cycle time (MIN.)

I'PD4264805-A50, 4265805-A50

50 ns

84 ns

20 ns

I'PD4264805-A60, 4265805-A60

60 ns

104 ns

25 ns

I'PD4264805-A70, 4265805-A70

70 ns

124 ns

30 ns

• CAS before RAS refresh, RAS only refresh, Hidden refresh
Part number

Row address

Column address

I'PD4264805

AO-A12

AO-A9

I'PD4265805

AO-A11

AO-A10

Refresh

Refresh cycle

RAS only refresh, Normal Read / Write

8,192 cycles/64 ms

CAS before RAS refresh, Hidden refresh

4,096 cycles/64 ms

RAS only refresh, Normal Read / Write

4,096 cycles/64 ms

-CAS before RAS refresh, Hidden refresh

The information In this docum.nt Is sublect to chang. without notlc•.
Document No, M10857EJ2VODSU1

43

NEe

~PD4264805,4265805

Ordering Information
Part number
~PD4264805G5-A50

.

44

Access time
(MAX.)

Package

Refresh

50 ns

~PD4264805G5-A60

60 ns

~PD4264805G5-A70

70 ns

~PD4265805G5-A50

50 ns

~PD4265805G5-A60

60 ns

~PD4265805G5-A70

70 ns

~PD4264805LE-A50

50 ns

~PD4264805LE-A60

60 ns

~PD4?64805LE-A70

70 ns

~PD4265805LE-A50

50 ns

~PD4265805LE-A60

60 ns

~PD4265805LE-A70

70 ns

32-pin Plastic TSOP(II)
(400 mil)
CAS before RAS refresh
RAS only refresh
Hidden refresh
32-pin Plastic SOJ
(400 mil)

I'i

NEe

~PD4264805,4265805

"

Pin Configurations (Marking Side)

,I

~

32-pin Plastic TSOP

(0)

(400 mil)

Vee

1/08

1/01

2

1/08

1107

1/02

3

1/07

29

1/06

1/03

4

28

1/05

1/04

5

GND

NC

6

2

1/02
1/03

4

1/04

5

1::1::

....
"""

Vee
WE

S

RAS

9

32

10

GND

1/06
1::1::

'V 'V

1/05

en ...

26

CAS

Vee

7

.••.
en.

CAS

00

25

OE

WE

8

00

OE

RAS

9

mm

'V 'V

cc

NC

I,

32-pin Plastic SOJ (400 mil)

GND

Vee
1101

,i

D>D>

en en
en en

CICI

A12/NC Note

cc

111111

D>D>

en en

r-r-

GND

A12/NC

AO

10

A11

AO

10

A11

A1

11

A10

A1

11

A10

A2

12

A9

A2

12

A9

A3

13

AS

A3

13

A8

A4

14

A7

A4

14

A7

A5

15

A6

A5

15

A6

Vee

16

GND

Vee

16

GND

Noto

Note A 12 ...J1PD4264805
NC ... J1PD4265805
AO to A12

Address Inputs

1/01 to 1/08
RAS
CAS

Data Inputs/Outputs
Row Address Strobe
Column Address Strobe
Write Enable

WE
OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

45

NEe

J,LPD4264805,4265805

Input/Output Pin Functions
The pP04264805, 4266805 have input pins RAS, CAS, WE, DE, AddressNot• 1 and input/output pins V01 to
Pin name
RAS
(Row address strobe)

Input/
Output
Input

voa.

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function .

• CAS before RAS refresh
CAS

CAS activates data input/output circuit by latching column address and

(Column address strobe)

selecting a digit line connected with the sense amplifier.

AO to AXNote 1

Address bus.

(Address inputs)

Input total 23-bit of address signal, upper bits and lower bits in sequence (address
multiplex method).
Therefore, one word is selected from 8,388,608-word by 8-bit memory cell array.
In actual operation, latch row address by specifying row address and activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (lASR, lAse) and hold time

(tRAH, tCAH)

are specified for the activation of RAS and CAS.
WE

Write control signal.

(Write enable)

Write operation is executed by activating RAS, CAS and WE.

OE

Read control signal.

(Output enable)

Read operation can be executed by activating RAS, CAS and

OE.

If WE is activated during read operation, OE is to be ineffective i" the device.
Therefore, read operation cannot be executed.
1/01 to 1/08
(Data inputs/outputs)

Note1.

Input/
Output

8-bit data bus.
1/01 to 1/08 are used to input/output data.

Part number

Address inputs

Upper bits

Lower bits

IlPD4264805

AO-A12

13

10

IlPD4265805

AO-All

12

11

Hyper Page Mode
The hyper page mode is a kind of page mode with enhanced features. The two major features of the hyper
page mode are as follows.
1. Data output time is extended.
In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead ofthe rising
edge. For this reason, valid data output time in the hyper page ~ode is extended compared with the fast
page mode (=data extend function). In the fast page mode, the data output time becomes shorter as the
CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is
lager than that of the fast page mode even if the CAS cycle time becomes shorter.

46

NEe

~PD4264805,4265805

Hyper Page Mode
The hyper page mode is a kind of page mode with enhanced features. The two majorfeatures ofthe hyper
page mode are as follows.

1. Data output tim. i. axtended.
In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the
CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS cycle time becomes shorter.
2. Th. CAS cycl. tim. in the hyper page mod. i. ahort.r than that in the fut page mod•.
In the hyper page mode, due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while
that in the fast page mode is 40 ns.
In the hyper page mode, read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode allows both read and write operations during one cycle, but the
performance is equivalent to that of the fast page mode in that case.
The following shows a part ofthe hyper page mode read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mod. Reed Cycl.

Address V,HV,L-

V,H- --.-"~-r"T"'T"---+----f+--+--+---f--+-+----+-+-H-L-+.,.....
WE V,LL...L...L-L...L..J

tOEA

V,HOE V,L-

---------1\.
tell

VOH-

Hi·Z

I/O VOL- .----------------------------

_Jj!.:~_

47

NEe

PPD4264805,4265805

Cautions when using the hyper page mode
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/Os to Hi-Zin read cycle, it is necessary to control RAS, CAS, WE, DE as follows. The effective

specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
~: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and tWPZ are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data
output with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

48

___N_E_C
________________--.;....J..LP_D_4_2_6_48_0_5_,4_2_6_5_8_05_ _ _ _ :1

:1

Electrical Specifications
• All voltages are referenced to GND .
• After power up, wait more than 100 }tS(RAS, CAS inactive) and then, execute eight CAS before RAS or
RAS only refresh cycles as dummy cycles to initialize internal circuit.

:1
1\

Absolute Maximum Ratings

"

Symbol

Parameter

Condition

Rating

Unit
V

Voltage on Any Pin Relative to GND

Vr

-0.6 to +4.6

Supply Voltage

Vee

-0.6 to +4.6

V

Output Current

10

20

mA

Power Dissipation

Po

1

W

Operating Ambient Temperature

TA

o to +70

·C

Storage Temperature

T.tg

-!i6to +125

·C

Caution

if

l

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this spacification. Exposure to Absolute Maximum Rating
c~nditions for extended periods may affect device reliability.

Recommended Operating Conditions
Symbol

Parameter

Condition

MIN.

TYP.
3.3

MAX.

Unit

Supply Voltage

Vee

3.0

3.6

V

High Level Input Voltage

VIH

2.0

Vee +0.3

V

Low Level Input Voltage

Vil

-0.3

+0.8

V

Operating Ambient Temperature

TA

0

70

·C

Capacitance ITA = 25

°e, f = 1 MHz)

Parameter
Input Capacitance

Data In put/Output Capacitance

Symbol

Condition

MIN.

TYP.

MAX

Unit

Address

5

pF

CI2

RAS, CAS, WE, OE

7

pF

Cvo

I/O

7

pF

CI1

I

49

NEe

~PD4264805,4265805

DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[~PD4264805J
Parameter
Operating current

Standby current

Symbol
Icc!

Icc2

Test condition

IcC3

(Hyper page model

50

Iccs

1,2,3

tRAC - 60 n.

95
86

10-OmA

1.0

10_OmA

0.5

tRAC = 60 ns

105

tRAC - 60 n.

95

;;= Vcc - 0.2 V

RASCycling

;;= VIH (MIN.I

tRAC - 70 ns

86

RAS ~ VIL (MAX.I

tRAc = 50 ns

106

CAS Cycling

tRAC = 60 ns

95

10=OmA

tRAC = 70 ns

86

liAS Cycling

tRAC. 50 ns

136

tRC = tRC (MIN.I

tRAC = 60 ns

115

10=OmA

tRAc = 70 ns

106

tHPC = tHPC (MIN.I
CAS before RAS
refresh current

tRAC - 60 n.
tRAc -70 n.

CAs i; VIH (MIN.I

tAc = tRC (MIN.I
IcC4

Notes

mA

10=OmA
RAS,

CAS

Operating current

Unit

106

tRC _ tRC(MIN.1

RAS, CAS
RAS only refresh current

MAX.

MIN.

RAS, CAS Cvcling

10=OmA

VI = Oto 3.6 V

Input leakage current

h(L1

Output leakage current

10(LI

High level output voltage

VOH

10= -2.0 mA

Low level output voltage

VOL

10 = +2.0 mA

all other pins not under test - 0 V
Vo = Oto 3.6 V
Output is disabled (Hi-ZJ

mA

mA

1,2,3,4

mA

1,2,5

mA

1,2

-5

+5

pA

-5

+6

pA

2.4

V

0.4

V

NEe

~PD4264805,4265805

blPD42658051
Parameter
Operating current

Standby current
RAS only refresh current

Symbol
Icc,

IcC2

IcC3

Test condition

IcC4

CAS before RAS
refresh current

Iccs

MAX.

Unit

Notes

mA

1.2.3

RAS. CAS Cycling

tRAC = 50 ns

135

tRc = tRC(MIN.)

tRAC = 60 ns

115

10= 0 mA

tRAC = 70 ns

105

RAS. CAS ~ VIH (MIN.)

10

RAS. CAS ~ Vcc - 0.2 V

=0 mA
10 =0 mA

0.5

RAS Cycling

tRAC = 50 ns

135

CAS ~ VIH (MIN.)

tRAC = 60 ns

115

tRC ':' tRC (MIN.)
Operating current
(Hyper page mode)

MIN.

10 = 0 mA

1.0

tRAC = 70 ns

105

RAS ~ VIL (MAX.)

tRAC = 50 ns

105

CAS Cycling

tRAC = 60 ns

95

=tHPC (MIN.)

tRAC = 70 ns

85

lIAS Cycling

tRAC = 50 ns

135

tRC = tRC (MIN.)

tRAC = 60 ns

115

10=OmA

tRAC = 70 ns

105

tHPC

10=OmA

VI = 0 to 3.6 V
all other pins not under test = 0 V

Input leakage current

Ii (L)

Output leakage current

10(LI

High level output voltage

VOH

10 =-2.0 mA

Low level output voltage

VOL

10 = +2.0 mA

Vo = Oto 3.6 V
Output is disabled (Hi-Z)

mA

mA

1.2.3,4

mA

1.2.5

mA

1.2

i'

-5

+5

jJ.A.

-5

+5

jJ.A.

2.4

V

0.4

V

Note. 1. Icc,. IcC3. Icc4 and Iccs depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. Icc, and Icc3 are measured assuming that address can be changed once or less during RAS

~

VIL(MAX.) and CAS ~ VIH(MIN.!.

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
S.

IcC4 is measured assuming that all column address inputs are switched only once during each hyper
page cycle.

51

NEe

~PD4264805,4265805

AC Characteristics (Recommended Operating Conditions unl_ oth_i.. noted)
AC Characteristics Test Conditions
(2) Output timing specification

(1) Input timing specification
VIH (MIN.) = 2.0 V
VIL (MU.)

= 0.8 V

---------------~

·--------:3-1
I
I

..

j

I
I

Ire

IT": 2 ns

I
I

VOH(MIN.) =2.0Vnnn~

L

.'

VOL

(MAX.)

I
I

}-

=0.8 V ------~'-_ _ _ _

_J

'.

tr.~ 2' ns

(3) Loading conditions are 100 pF + 1 TIL

Common to R..d, Write, R..d Modify Write Cycle
Parameter

52

Symbol

tRAC"

70 ns

MAX.

MIN.

MAX.

MIN.

MAX.

-

104

124

10

-

ns

10

10000

70

10000

ns

tRAC"

Read I Write Cycle Time

tRC

84

RAS Precharge Time

tRP

30

CAS Precharge Time

tCPN

7

60 ns

= 60 ns

MIN.

tRAC

40

60

Unit Notes

ns
ns

RAS Pulse Width

tRAS

60

10000

60

CAS Pulse Width

tCAS

7

10000

10

10000

12

10000

ns

RAS Hold Time

tRSH

10

10

12

ns

CAS Hold Time

tCSH

38

-

40

-

60

-

RAS to CAS Delay Time

tRcD

11

37

14

46

14

62

ns

12

36

ns

1

5

-

ns

2

0

-

ns
n.

ns

RAS to Column Address Delay Time

tRAD

9

26

12

30

CAS to RAS Precharge Time

tCRP

6

6

Row Address Setup Time

tAsR

0

12

13

-

16

-

1

50

ns

64

ms

Row Address Hold Time

tRAH

7

Column Address Setup Time

tAsc

0

Column Address Hold Time

tCAH

7

OE Lead Time Referenced to RAS

tOES

0

CAS to Data Setup Time

tCLl

0

OE to Data Setup Time

tOll

0

OE to Data Delay Time

tOED

10

-

Transition Time (Rise and Fall)

tT

1

60

1

50

Refresh Time

tREF

-

64

-

64

0
10
0
10
0
0
0

,0
0

0
0
0

-

n8
ns
n.
ns
ns
ns

1

:,;1,

NEe

p.PD4264805,4265805

-------------------------------...:...-----------------.g

Ii

Not.. 1. For read cycles, access time is defined as follows:
Input Conditions

Access Time

Access Time from RAS

tRAD;:a; tRAD IMAX.) and tRCD;:a; tRCD IMAX.)

tRAC IMAlt)

tRAc IMAlt)

tRAD > tRAD IMAX.) and tRCD;:a; tRCD (MAlt)

tAA (MAlt)

tRAD + tAA IMAlt)

tRCD > tRCD IMAX.)

tCAC (MAlt)

tRCD + tCAC IMAlt)

tRADIMAX.) and tRCDIMAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD i: tRADlMAX.) and tRCD i:
tRCDIMAX.) will not .cause any operation problems.
2.

tCRPIMIN.) requirement is applied to RAS,

CAS cycles.

Read Cycle
tRAC = 50 ns
Symbol

Parameter

tRAC

MIN.

MAX.

MIN.

60

Unit Notes

MAX.

MAX.

-

60

-

70

ns

1

-

18

ns

1

36

ns

1

18

ns

30

35

-

ns

0

-

ns

0

ns

2

tRAC

Access Time from CAS

tCAC

Access Time from Column Address

tAA

-

Access Time from OE

tOEA

-

13

Column Address Lead Time Referenced to RAS

tRAL

25

Read Command Setup Time

tRCS

0

-

Read Command Hold Time Referenced to RAS

tRRH

0

-

0

26

tRAc = 70 ns
MIN.

Access Time from RAS

13

=60 ns

16
30
16

Read Command Hold TIme Referenced to CAS

tRCH

0

-

0

-

0

-

ns

2

Output Buffer Turn-off Delay Time from OE

tOEZ

0

10

0

13

0

15

ns

3

CAS Hold Time to OE

tCHO

5

-

5

-

5

-

ns

0

Not.. 1. For read cycles, access time is defined as follows:
Input Conditions

Access Time

Access Time from RAS

tRAD;:a; tRAD (MAX.) and tRCD;:a; tRCO (MAX.)

tRACIMAlt)

tRAC IMAX.)

tRAD> tRAC IMAX.) and tRCD;:a; tACO (MAX.)

tAAIMAlt)

tRAD + tAA IMAlt)

tRCD> tRCD (MAlt)

tCAC IMAlt)

tRCD + tCAC IMAlt)

tRADIMAX.) and tRCDIMAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD i: tRADIMAlt) and tRCD i:
tRCDIMAX.) will not cause any operation problems;
2.

Either tRCHIMIN.) or tRRHIMIN.) should be met in read cycles.

3.

tOEZIMAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to
VOH or VOL.

53

NEe

~PD4264805,4265805

Write Cycle
Parameter
WE Hold Time Referenced to CAS

Symbol
twcH

tRAC= 1i0 ns

tRAC = 60n8

tRAC -70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

7

-

10

10

1

ns

1

0

-

ns

-

-

0

-

ns

0

-

ns

3

ns

3

WE Pulse Width

twP

7

WE Lead Time Referenced to RAS

tRWL

10

WE Lead Time Referenced to CAS

tCWL

7

WE Setup Time

twcs

0

OE Hold Time

to£H

0

Data-in Setup Time

tos

0

Data-in Hold TIme

tOH

7

-

10
10
10'
0
0
0
10

-

-

10
12
12

10

Unit Notes

ns
ns
ns

2

Not.. 1. twP(MIN.1 is applied to late write cycles or read modify write cycles. In early write cycles, twCH(MIN.1
should be met.
2.

If twcs

s: twCS(MIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the

entire cycle.
3. tOS(MIN.1 and tOH(MIN.1 are referenced to the CAS falling edge in early write cycles. In late write cycles
and read modify write cycles, they are referenced to the

WE falling edge.

Read Modify Write Cycle
Parameter

Symbol

tRAC .1i0 ns
MIN.

MAX.

-

Read Modify Write Cycle Time

tRWC

107

RAS to WE Delay Time

tRWO

64

CAS to WE Delay Time

tcWD

27

Column Address to WE Delay Time

!AWO

39

Not. 1.

If twc:s

tRAC - 60 ns

tRAC .'70 nl

MIN.

MAX.

MIN.

MAX.

133

167

32

-

47

"-

64

-

77

89
37

Unit Notes
ns
ns

1

n8

1

ns

1

s: twCS(MIN.1 the cycle is an early write cycle and the data out wiil remain Hi-Z through the
s: tRWO(MIN.I, tcwo s: tCWO(MIN.I, !AWD s: !AWD(MIN.I, and tcPWO s: tCPWD(MIN.I, the cycle is a

entire cycle. If tRWD

read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.

54

NEe

~PD4264805,4265805

Hyper Page Mode
tRAC
Parameter

Symbol

~

MIN.

50 ns

tRAc - 60 ns

tRAC -70 ns

MAX.

MIN.

MIN.

MAX.

-

MAX.

Unit Notes

Read I Write Cycle Time

tHPC

20

-

25

RAS Pulse Width

tRASP

50

125000

60

25001

CAS Pulse Width

tHCAS

7

10000

10

10000

CAS Prechargl! Time

tcp

7

-

10

-

10

-

ns

Access Time from CAS Precharge

tAcp

-

30

-

36

-

40

ns
ns

ns

30

-

ns

70

126001

ns

12

10000

ns

1

CAS Precharge to WE Delay Time

tCPWD

41

-

52

-

69

RAS Hold Time from CAS Precharge

tRHCP

30

-

35

-

40

Read Modify Write Cycle Time

tHPRWC

52

-

66

-

75

Data Output Hold Time

tOHC

5

5

tacH

6

6

-

OE Precharge Time

tOEP

5

-

6

OE to CAS Hold Time

-

-

5

-

ns

Output Buffer Turn-off Delay from WE

twez

0

10

0

13

0

16

ns

WE Pulse Width

IwPZ

7

-

10

.,....

10

-

ns

4

Output Buffer Turn-off Delay from RAS

tOFR

0

10

0

13

0

16

ns

3.4

Output Buffer Turn-off Delay from CAS

tOFC

0

10

0

13

0

15

ns

3.4

Not•• 1.
2.

5
6

2

ns
ns
ns

3,4

tHPC(MIN.) is applied to access time from CAS
If twcs ~ tWCS(MIN.), the cycle is an early write cycle and the data out will remain Hi - Z through the
entire cycle. If tRWO ~ tRWD(MIN.), tCWD ~ tCWO(MIN.), tAWD ~ tAWD(MIN.), and tCPWD ~ tCPWD(MIN.), the cycle is
a read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.

3.

tOFC(MAlC.), tOFR(MA)(') and tweZ(MAX.) define the time when the output achieves the condition of Hi-Z and

4.

To make I/Osto Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The

is not refereflced to VOH or VOL.
effective specification depends on state of each signal.
(1) RAS, CAS: Inactive (at the end of read cycle)
WE : inactive, OE : active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE : inactive, OE : inactive ... tOEZ is effective.

--

--

--

(3) Both HAS and CAS are inactive or RAS is.activeand CAS is inactive
(at the end of read cycle)
WE,OE:active and either tRRH or tRCH must be met·.. tweZ' IwPZ are effective.

55

NEe

~PD4264805,4265805

Refresh Cycle
tRAC-

Parameter

56

Symbol

60 n8

MIN.

MAX.

-

rn Setup Time
rn Hold Time (m before RAS Refresh)
RAS Prech/;lrge rn Hold Time

tCSR

6

tCHR

10

tRPC

6

WE Setup Time

twsR

10

WE Hold Time (Hidden Refresh Cycle)

twHR

15

tRAC -

MIN.
6
10

60 ns
MAX.

-

10

-

16

-

6

tRAC.

70 ns

MIN.

MAX.

6

10

-

16

-

10
6

Unit
ns
ns
n.

n.
ns

Note

·f

It.

_ _.:..N.::.E=C=-_ _ _ _ _ _ _ _ _ _ _ _ _ _...I.Jl=P...;;D;....4=2;.;;..64...;..8;..;O...;;5~,..;.42=6;..;5...;;8..;.O.;;..5_ _~:ri~

II
,.t

Read Cycle
tAc

RAS

:t

VIHV'L-

,1,'

tCSH

tAco

tASH

tCAS
CAS

VtHV'LtJw.

Address

V'HVIl-

WE

VIHVIl-

tCAC
tOlZ

teu
1/0

VOHV0..-

Hi - Z
-- - - - - - - -- - - - - - - - -- - - - - - -- --- - -- - - - -- - -- - - - - --- --- - -- -- - -- - - - - --

tOFR

Data out

57

NEe

yPD4264805,4265805

Early Write Cycle
tAc

tRAS

Address

VII;V,L-

va

V,HV,L-

Ramark OE: Don't care

58

"I'N
.~

'j
_ _.;..N;;;..E~C=-_ _ _ _ _ _ _ _ _ _ _ _ _ _.....#J._P_D_4_2__
64......8_0_5....
, 4_2_6_5_8_05_ _ _ _ i4
)

!~

~
1

Late Write Cycle
tAC

1;1
'If·

Address

V,iiV,L-

59

NEe

yPD4264805,4265805

Read Modify Write Cycle

tcSH

VII",-

VIl-

Address

Vi.....
VIl-

WE

Vi .....
VIl-

twp

tewD

tOEA

OE

tOEH

Vi .....
VIl-

tos

VO

Vi .....
VIl-

VO VO.....
VOL-

60

toH

Data in

Hi-Z

Hi-Z
--------------.-----------------_.

NEe

pPD4264805,4265805

Hyper Peg. Mod. R.ed Cycle
tAp

RAS

IMPC

leSH

CAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

~

tAHep

V,HV,L-

~

IHCAS

tAco

~

~

J

~~

IHCAS

~

~

tASH

1~

tcP

IMCAS

~

,111
1Iw.

~
Col.

16<
........ t>-

~n

~~

Col.

Col.

100
--- t>-

OE

V,HV,L-

\\\\\\\\\\~
I

IIw:
lAP.
tcAc

VOH- ••.•.......•...1:11;1-..••..••••. 1

lAP.

lAP.

teAe

teAe

~

Data out

~

··0

Data out

~~
"- .1''1
A

~

!AcP

~

...J£!L.,
VOL-

)(

//////
I

VO

tOfA
tOfe

to-

tAep

~

j

xxx:

tA~

~

/

~

\\\\
toEz

··0

Data out

...

Remerk In the hyper page mode. read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

61

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yPD4264805,4265805

Hyper Page Mode Read Cycle (WE Control)
tRASP
tAHCP

tesH

Address

V,HVIl- .

WE

V,HV,l-

OE

V,HV,l-

I/Q

VOHVOl-

•••• __ • _____ • __ tll;~ _________ _

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the

consecutive 'C:AS cycles within the same RA5 cycle.

62

_ _N;;...;;;;.;;E;;;;;;C-=-_ _ _ _ _ _ _ _ _ _ _ _ _ _...t:#l;;;;.P..=;D...:,4;;;.;26;;..4;;.;:8:.=.O.;:;..=5,:,...4;;,;;:2;;.;:6.;;.58;;.;O;;.;:5~_ _~i'i
"

j:1

Hyper Page Mode Reed Cycle 1l)E Control)

RAS V,iiV,L-

IHPc

tcsH

CAS

V,iiV,L-

J

~

V,HV,L-

V,HV,L-

1Iw.

~tIIf-I

ColA- : m

Coi.B:m

Coi.C

)0()(

1M

IIIII!

...

tCHo

tecH

\\\\\\\\\\\

toes

\.. I--'

~~

"-

I" ~

I-- ~'1Roo

\\\\

tCHo
tocP

Pi r-d
o.t. out

I

~

~
,.--. ~

II

\

toEA

~

~ tc~'-I-- ~

)B~----1~

I

tAA

tOCH

IAcP

/~
I

-----------~.:~-----------

)

~ ~

~

~

l' tcLZ •
110 VOL-

~

~~

1RAc
tAA

~LZ

VOH-

I

~

Row

~

tHCAs

~

[\\

~
OE V,HVIl-

~

~

I

WE

~

tRsH

tHCAS

~

tHcAs

tAco

~~

Address

f-'!!--I

til"".

~

toEz

i

\\\

~

8}----I ~ Data out 8.-- ~ Data.,.. c

_1:E~_

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

63

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yPD4264805,4265805

Hyper Page Mode Early Write Cycle
lRASP

Address

IRP

V, ...

VIL-

Remarks 1. OE: Don't care

2. In the hyper page mode, read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

64

1.1

I ,~

_ _.:;...N;;;;..;E=..;;:C~_ _ _ _ _ _ _ _ _ _ _ _ _-.l:Y;.:..P..=.D..;.4;;:.;26:;...4;;.;:;8..=.05,:;,:';...4;;.;:;2;.;:;.6.;:;.;58::;.;:O;;.;:;5~_ _ I~,i
i~
Hyper Paga Mod. Lat. Write Cycle

WE

V,....:
V'L-

OE

V, ...
V'L-

i

I'

i
"

i

Remark

In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

65

NEe

gPD4264805,4265805

Hyper Pa". Mode R..d Modify Write Cycl.

VIHVIL-

Address

VIHVIL-

VIHVIL-

VIHVIL-

VO Va..VOL-

1/0

VIHVIL-

Remark

66

In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same W cycle.

I~

,\

___N_E_C
_______________.....IL_P_D_4_2..;...64_8_0_5....
, _42_6_5......
8_05_ _ _~,f
I"t

I:

Ii

Hyper Page Mode Read and Write Cycle

II

:,

lAp

Address

V,H- -.,........................~oor-+-~,.I-..

V,L- .............->...............T'-. .-,...;O""':'r'-'+-HI---""+---+.......t--r-.......-+r-............-'"-'"-"'-'''''-'...............

I/O

VOH-

Hi-Z

v01.- •••••••••••••••••••••••••••••••·

•.••••.•..l:Ii:1••.••.•..•..•..

I/O

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

67

NEe

gPD4264805,4265805

CAS Before RAS Refresh Cycle

tRAS
VII'..
V"..

Remark Address, OE: Don't care

I/O: Hi ..Z

RAS Only Refresh Cycle

tRAS

V,HV,L..

teRP

Address

Remark WE, OE: Don't care

68

I/O: Hi ..Z

tRP

tRAS

NEe

yPD4264805,4265805

Hidden Ref,..h Cycle (Re.d)
tile

tile

RAS V,HV,LtCRP

CAS V,HV,L-

Address

V,HV,L-

OE V,HV,L- .....".......................>...,;>r->........................+-.............,.....+-==-----+---""""'I.,....-....................-....-t-...........-

tell
I/O V",,Hi-Z
VOL- -------------------------------------------

Data out

Hi-Z

69

NEe

yPD4264805,4265805

Hidden Refresh Cycle (Write'

tAc

tRC

tRAs

RAS

VII••
VIL-

tCRP

CAS

VIHVIL-

Address

VIHVIL-

va

--'~"""""'''''''''''''''~''''..p---+''''''r--'''~-'

VIHVIL-

L...l4...)j~..x...lt.."'-.lIt....lo4...)j-Jf

Remark OE: Don't care

70

1\,,_ _ _ _--"

~lt....lot...lol..x...v...x..;It....lo4...)j~...¥..lt...x..;It....lo4...)j..x.-"-......K.-l~~

_~N....;;;.;;;;E;;..;C~_ _ _ _ _ _ _ _ _ _ _ _ _..s;.Jl;.:..P=-D..;.;42=.:6;..:.4.=.;80;;:5;L.,'"::42=':65==80::':5~----Irl
Package Drawings

:1

,

32PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

-++-----+------+

H

u;
~t--i
O~D:u~~:~DU~
01$1

M

@I

.~

J

L

I
I

NOTE
Each lead centerline is located within 0.21 mm (0.009 Inert, of
its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS
A
21.17 MAX.
1.075 MAX.
B

INCHES

1.27 (T.P.)

0.834 MAX.
0.043 MAX.
0.050 (T.P.)

0

0.42~:8'

0.01710.003

E
F
G
H
I

0.110.OS
1.2 MAX.
0.97
11.7610.2
10.16tO.l

0.00410.002
0.04l! MAX.
0.038
0.46310.008
0.40010.004

J

0.810.2

0.031~:88X

K

0.145~:8i~

0.00610.001

L

0.510.1

0.020~:8rs

M
N

0.21
0.10

0.009
0.004

P

3-+7-

3•• 7-

C

-3"

-3"

S3aG5oIO-7JD2

71

NEe

pPD4264805,4265805

32 PIN PLASTIC SOJ (400 mil)

-t-+-------+-------t-'uo

E

F

criI
M

r:::1~"-1-N"'?=!9::-1

P32LE-400A
NOTE
Each lead centerline is located within 0.12 mm
(0.005 inchl of its true position (T.P.! at maximum material condition.

I ITEM

MILLIMETERS

INCHES

I

0.S29:0.00S

I

B

21.06:0.2

C

10.16

0.400

D

11.1'S:0.2

0.440:1:0.00S

E

1.005:0.1

0.040~gg:

F

0.74

0.029

G

3.5:1:0.2

0.13S:l:0.00S

H

2.545:1:0.2

0.100:0.00S

---~-----~---------!

O.S MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.!·

0.050 (T.P.I

M

0.40:1:0.10

0.016~gg;

N

0.12

0.005

P

9.4:0.20

0.370:l:0·00sI

Q

0.1

0.004

I

T

R 0.S5

R 0.033

u

0.20~bg

O.oos~ggu

---~--------~----

72

.

r--_ _ _
p_R_E_Ll_M_,N_A_Ry_D_I'_:rA_s_H_E__
E_T_ _ _ _ _ _ _ _

MOS INTEGRATED CIRCUIT

NEe

~1
.~
'll

_ _ _ _ _ _J.l_P_D_42_6_4_'6_5_,_42_6_5_'_65_1

~,

,;

64 M-BIT DYNAMIC RAM
4 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE

\
!

--------------------------------------------------------~

,i

'!

Ii

Description
The IlPD4264165, 4265165 are 4,194,304 words by 16 bits CMOS dynamic RAMs with optional hyper page mode.
Hyper page mode is a kind of page mode and is useful for the read operation.
The IlPD4264165, 4265165 are packaged in 50-pin plastic TSOP(ll).

ii
i,

Features
• Hyper page mode
• Single +3.3 V±0.3V power supply
• 4,194,304 words by 16 bits organization
Access time
(MAX.)

R/W, cycle time
(MIN.)

Hyper page mode
cycle time (MIN.)

50 ns

84 ns

20 ns

",PD4264165·A60, 4265165·A60

60 ns

104 ns

25 ns

I1PD4264165·A70, 4265165-A70

70 ns

124 ns

30 ns

Part number
I1PD4264165·A50, 4265165-A50

• CAS before RAS refresh, RAS only refresh, Hidden refresh
Part number
I1PD4264165

I1PD4265165

Row address
AO·A12

AO·A11

Column address
AO-AS

AO-A9

Refresh

Refresh cycle

RAS only refresh, Normal Read I Write

S,192 cycles/64 ms

CAS before RAS refresh, Hidden refresh

4,096 cycles/64 ms

RAS only refresh, Normal Read / Write

4,096 cycles/64 ms

CAS before RAS refresh, Hidden refresh

,The Information In thll document II lubJect to change without notice.
Document No, Ml0694EJ3VODSUl

73

NEe

~PD4264165,4265165

Ordering Information
Part number
jtP04264165G5-A50

74

Access time

(MAX.)

Package

Refresh

50 ns

jtP04264165G5-A60

60 ns

jtP04264165G5-A70

70 n.

jtP04265165G5-A50

50 ns

jtP04265165G5-A60

60 ns

jtP04265165G5-A70

70 ns

50-pin Plastic TSOP(I1)
(400 mil)

CAS before RAS refresh

iiAs only refresh
Hidden refresh

II
.&

_____~
__E:
__c:__________________________________~_P_D_4_2_6_4_1_6_5_,4_2_6_5_1_6_5______~il

II
II

Pin Configurations (Marking Side)

II
SG-pin Plastic TSOP 1111 (400 mil)

50
49
48
47
46
45

Vee
VOl
V02
V03

V04
Vee

GND
V016
V015
V014
V013

GND

V05

44

V012

V06

43

VOll

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VOl 0

~)

V07

V08
NC
Vee

WE

RAS
NC
NC
NC
NC
AO
Al
A2

A3
A4

A5
Vee

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

....
81~

~~
1(11(1
xx
XX

V09

NC
GND
LCAS
UCAS
OE

NC
NC
Al2/NC
All
Al0
A9
A8
A7
A6
GND

"

I

Note A12 ...I1PD4264165
NC ... I1PD4265165
Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe (upper)

AO to A12
1/01 to 1/016
RAS
UCAS
LCAS
WE
OE
Vee
GND
NC

Column Address Strobe (lower)

'.

Write Enable
Output Enable
Power Supply
Ground
No Connection

75

NEe

~PD4264165,4265165

Input/Output Pin Functions
The pPD4264165, 4266166 have input pins RAS, CAS ..... " WE, CE, Ad~ 2 and input/output pins V01 to V016.
Pin name
RAS
(Row ad,dress strobe)

Input/
Output
Input

Function
RAS activates the sense amplifier by latching a
corresponding word line.

~ow

address and selecting a

It refreshes memory cell array of one line selected by the row address.
It also selects the following function •
• CAS before RAS refresh
CAS
(Column address strobe)

CAS activates data input/output circuit by latching column addrass and

AO to AX Note 2

Address bus.
Input total 22-bit of address signal, upper bits and lower bits in sequence (address

selecting a digit line connected with the sense amplifier.

(Address inputs)

multiplex method).
Therefore, one word is selected from 4,194,304-word bV 16-bit memory cell array.
In actual operation, latch row address bV specifying row address end ectivsting RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device whenRAS and CAS are activeted.
Therefore, the address input setup time (Wft, we) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)

Write control signal.

OE

Read control signal.

Write operation is executed bV activating RAS, CAS and WE.

(Output enable)

Read operation can be executed bV activating RAS,

CAS and CE.

If WE is activated during read operation, OE is to be ineffective in the device.

Therefore. read operstion cannot be executed.
1/01 to 1/016
(Data inputs/outputs),

Note1.

Input/
Output

1,6-bit data bus.
1/01 to V016 are used to input/output data.

CAS means UCAS and LCAS.

2.
Part number

Address inputs

Upper bits

Lower bits

IlPD4264165

AO-A12

13

9

IlPD4265165

AO-A11

12

10

Hyper Page Mode
The hyper page mode is a kind of page mode with enhanced features. The two major features of the hyper
page mode are as follows.
1. Data output time is extended.
In the hyper page mode, the output d~ta is held to the next CAS cycle's falling edge, instead ofthe rising
edge. For this reason, valid data output time in the hyper page mode is extended compared with the fast
page mode (=data extend function). In the fast page mode, the data output time becomes shorter as the
CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is
lager than that of the fast page mode even if the CAS cycle time becomes shorter.

76

'~

___N_E_C
________________---.,;.I-L_P_D_42
....,_64_1_6_S,_4_2_6_S_1_6_S_ _ _~'i!
Hyper Page Mode
The hyper page mode is a kind of page mode with enhanced features. The two major features of the hyper
page mode are as follows.
1. Data output time i. extended.
In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the
CAS cycle time becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode i. shorter than that in the fast page mode.
In the hyper page mode, due to the data extend function, the EAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the EAS cycle time in the fast page mode is 25 ns while
that in the fast page mode is 40 ns.
In the hyper page mode, read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode allows both read and write operations during one cycle, but the
performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode read cycle. Specifications to be observed are described
in the next page.
Hyper Page Mode Read Cycle
RAS

V'HV'L-

Address

V'HVIL-

tOCH

tOEA

OE V'HV'Lteu

VOH-

Hi-Z

I/O VOL- .----------------------------

77

NEe

#-,PD4264165,4265165

Cautions when using the hyper page mode

1. CAS access should be used to operate tHPC at the MIN. value.
2. To make 1I0sto Hi-Z in read cycle, it is necessary to control F\AS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cyc tRAO (MAX.) and tRCO;:2 tRCO (MAlt)

tAA (MAlt)

tRAD + tM (MAlt)

tACO> tACO (MAlt)

tCAC (MAlt)

tACO + tCAC (MAlt)

tRAD(MAlt) and tRCO(MAX.) are specified as reference points only ; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tM or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAO S!:; tRAO(MAlt) and tRCO S!:;
tRCO(MAX.) will not cause any operation problems.
2. tCRP(MIN.) requirement is applied to RAS, CAS cycles.

Read Cycle
tRAC. 50 ns
Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

50

-

60

-

70

ns

1

-

30

-

35
0

-

ns

0

-

ns

2

ns

2
3

Unit Notes

Access Time from RAS

tAAC

Access Time from CAS

tCAC

Access Time from Column Address

tM

Access Time from OE

tOEA

-

Column Address Lead Time Referenced to RAS

tRAL

25

Read Command Setup Time

tACS

0

Read Command Hold Time Referenced to RAS

tRRH

0

Read Command Hold Time Referenced to CAS

tRCH

0

Output Buffer Turn-off Delay Time from OE

tOEZ

0

10

0

13

0

15

ns

CAS Hold Time to OE

tCHO

5

-

5

-

5

-

ns

13
25
13

0
0
0

15
30
15

0

18

ns

1

35

ns

1

18

ns

-

ns
I

Not.. 1. For read cycles, access time is defined as follows:
Input Conditions

Access Time

Access Time from RAS

tRAO:;; tRAD (MAx.) and tACO:;; tRCO (MAX.)

t RAC (MAlt)

tRAC (MAlt)

tRAO> tRAO IMAX.) and tACO:;; tReo (MAX.)

tM (MAlt)

tRAO + tM (MAX.)

tRCO > tACO (MAlt)

t CAC (MAlt)

tRCO + tCAC (MAlt I

tRAOIMAltl and tRcoIMAX.1 are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tM or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAO S!:; tRAOIMAltI and tRCO S!:;
tRCOIMAX.1 will not cause any operation problems.
2.

Either tRCHIMIN.1 or tRRHIMIN.) should be met in read cycles.

3.

tOEZIMAX.1 define; the time when the output achieves the condition of Hi-Z and is not referenced to
VOH or VOL.

83

NEe

~PD4264165,4265165

Write Cycle
Parameter

Symbol

tRAC" 50 ns
MIN.

MAX.

twCH

7

WE Pulse Width

twP

7

WE Lead Time Referenced to RAS

tRWl

10

WE Lead Time Referenced to CAS

tCWl

7

-

WE Hold Tima Referenced to CAS

WE Setup Time

twcs

0

OE Hold Time

tOEH

0

Data-in Setup Time

tos

0

Data-in Hold Time

tOH

7

tRAC" 60 ns

tRAC" 70 ns

MIN.

MAX.

MIN.

MAX.

10

-

10

-

10
10
10
0
0
0
10

10
12
12
0
0
0
10

Unit Notes
ns

1

ns

1

ns
ns
ns

2

ns
ns

3

ns

3

Not.. 1. twP(MIN.) is applied to late write cycles or read ,modify write cycles. In early write cycles, twCH(MIN.)
should be met.
2.

If twcs il: tWCS(MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle.

3.

tOS(MIN.) and tOH(MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles
and read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
Parameter

Symbol

tRAC" 50 ns
MIN.

MAX.

-

Read Modify Write Cycle Time

tRWC

107

RAS to WE Delay Time

tRWO

64

CAS to WE Delay Time

tcwo

27

Column Address to WE Delay Time

tAwo

39

Not. 1.

tRAC

=60 ns

tRAC

=70 ns

MIN.

MAX.

MIN.

MAX.

133

-

157

-

77

32
47

89
37
54

Unit Notes
ns
ns

1

ns

1

ns

1

If twcs il: twCS(MIN.) the cycle is an early write cycle and the data out will remain Hi-Z through the
entire cycle. If tRWO il: tRWO(MIN.), tcwo il: tCWO(MIN.), tAwoi: tAWO(MIN.), and tcPWO !?: tCPWD(MIN.), the cycle is a
read modify write cycle and the data out will contain data read from the selected cell. If neither of
the above conditions is met, the state of the data out is indeterminate.

84

If

NEe

Ii

IlPD4264165,4265165

----------------------------------------------------------~~-------------------------------¥
,:~

;i

Hyper Page Mode
Parameter

Symbol

tRAC

=50 ns

tRAC - 60 ns

tRAc -70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

30

-

ns

ooe

70

125001

ns

10000

12

10000

ns

Unit Notes

Read I Write Cycle Time

tHPC

20

-

25

-

RAS Pulse Width

tRASP

50

125000

60

~25

CAS Pulse Width

tHCAS

7

10000

10

CAS Precharge Time

tcp

7

-

10

-

10

-

ns

Access Time from CAS Precharge

tAcp

-

30

-

35

-

40

ns

52

-

59

-

ns

40

-

ns

CAS Precharge to WE Delay Time

tcpwo

41

RAS Hold Time from CAS Precharge

tRHCP

30

Read Modify Write Cycle Time

tHPRWC

52

Data Output Hold Time

tOHC

5

OE to CAS Hold Time

tOCH

5

OE Precharge Time

tOEP

5

-

Output Buffer Turn-off Delay from WE

lwEz

0

10

0

WE Pulse Width

twPz

7

-

Output Buffer Turn-off Delay from RAS

tOFR

0

10

Output Buffer Turn-off Delay from CAS

tOFC

0

10

Not•• 1.
2.

35
66
5

75
5

1

2

ns
ns

5

-

ns

13

0

15

ns

10

-

10

-

ns

4

0

13

0

15

ns

3.4

0

13

0

15

ns

3.4

5
5

5

:1
!1

ns

3.4

tHPC(MIN.1 is applied to access time from CAS

I ,1

If twcs ?; twCS(MIN.I, the cycle is an early write cycle and the data out will remain Hi - Z through the
entire cycle. If tRWD ?; tRWD(MIN.I, tCWD ?; tCWO(MIN.I, tAwo ?; tAWD(MIN.I, and tcpwo s:; tCPWO(MIN.I; the cycle is
a read modify write cycle and the data out will contain data read from the selected cell. H neither of
the above conditions is met, the state of the data out is indeterminate.

3.

tOFC(MAX.I, tOFR(MAX.1 and lwEZ(MAX.1 define the time when the output achieves the condition of Hi-Z and

4.

To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The

is not referenced to VOH or Val.
effective specification depends on state of each signal.
(1) RAS, CAS: Inactive (at the end of read cycle)

WE : inactive, OE : active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE : inactive, OE : inactive ... tOEZ is effective.
(3)-BothRAS and CAS are inactive-Or RAS·is-active and CAS is-inactive
(at the end of read CYcle)
WE,OE:active and either lRRH or tRCH must be met··· lwEz, twPz are effective.

85

NEe

~PD4264165,4265165

Refresh Cycle
tRAc

Parameter

CAS Setup Time
CAS Hold Time ('CAS before lIAS Refresh)

m

86

PreClharge

CAS Hold Time

Symbol

= 50 ns

MIN.

MAX.

tCSR

5

tCHR

10

-

tRPC

5

WE Setup Time

twSR

10

WE Hold Time

twHR

15

tRAC

= 60 ns

tRAc

= 70 ns
Unit

MIN.

MAX.

MIN.

MAX.

5

-

5

-

ns

10

-:-

ns

-'-

10

15

-

15

-

ns

10

10
5

5

ns
ns

Note

NEC

PPD4264165.4265165

------.;;...------------------------''------------------~

'I
'%

il
,{

Read Cycle

l1

~

'1

tRC

",f

tRAS

RAS

I~

tAp

VOlVo.tesH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

tOLl
teLl

U
VO VOHHi-Z
L 1/0
VOL- -- _.- _. __ ••••• -. - ••••• _••••• _-.- _•••• - •• _•• - ••• _•••• _•••••••••••

tClfR

Data out

Hi-Z

87

NEe

yPD4264165,4265165

Upper Byte Read Cycle

t_

RAS

til.

V,HV,LtCSH
tRCO

UCAS

bIIIH
teAs

V,HV,Lt ...H

LCAS

V,HV,Lt_

Address

V,HV,L-

WE

V,HV,L-

tOCH
toE.

tOEA
V,HVIL- _~I.....l....l.-l.+~.l....~y....l.-l...l...+-.l....l.....l~-\'..l...+_ _ _ _"""'f+_...L.tr_---'Y""''''''''''''''''
tc..c
tOl.Z

tOFR

taz
U VO

VOHVOL-

Remark L I/O: Hi-Z

88

Hi -Z

Data out

iii

_ _.;;..N~E~C~_ _ _ _ _ _ _ _ _ _ _ _ _---,IL;;;,;.P...;;;;D....;;4;,;;;;;.264~1;,..;;6~5,:...4.;;.;;2;;.;;;6~5..;;..16;;...;;5~_ _

Ii

Lower Byte Reed Cycle

t ....
RAS

I

t ••

V..VL-

~:

,"

I )~

I~
UCAS

LeAS

Address

V.. VL-

,I

v.. -

"
I,",

'1
'I;
,/

VL-

V..VL-

V..VL-

~-r~,-~r,-r-r'-~r---~-------------------t-H~---1--~r---t7-r7
~~~~T-~~LT

V..VL- ~~~-L~~~~-L~~~-r~~~~-L~---------t+---~r---~~~~~

to,"

tcLZ
LI/o

Remerk

VOtl-

VOl..-

Hi-Z

Data out

Hi-Z

U I/O: Hi-Z

89

NEe

gPD4264165,4265165

Early Write Cycle
tAc

tRAs

tRP

V,...
RAS
V,LtCSH

~

V, ...
LeAS V,L-

Address

u va
L va

~::

V, ...
V,L- L..lo'-ll:~~"-loI~.lL-:1L..lf

Remark OE: Don't care

90

''__ _ _ _ _ _ _ _ _ ................................................__-"-...............................

'\

1*

____~~E~c:~____________________________~g~P~D~4~26~4~1~6~5,~4~2~6~5~16~5~_____ r
.~

'i

Upper Byte Early Write Cycle

!I
',I

tAe

!

RAS

V'HVILtCSH

UCAS

V'HV'L-

LCAS

V,HV,L-

Address

WE

UI/O

I',

V'HV'L-

"

Remark DE, L 110: Don't care

91

NEe

gPD4264165,4265165

Lower Byte Early Write Cycle

.Address

V..VL- ~~~~~~~~~__+-~~~~~~~~~~~~~~-L~~~-L~~

LIfO

V.. VL-

L..>I'-""........~.....................<..j/

Remark OE, U I/O: Don't care

92

" -_ _ _- - "

" - '.....................................................................................................................

NEe

gPD4264165,4265165

Late Write Cycle
tRe
tRAS

Vi....
Vll-

OE

Vi ....
VIL-

UIIO
LIIO

Vi ....
VIL-

93

NEe

yPD4264165,4265165

Upper Byte Late Write Cycle

LeAS·

Addrass

VOHVOL-

V..V ..-

VOH- -,""T-r"-r-T-:r-7""T-r"r----,(
VOL- ~t.....I.....L...L...l-t.....I.....L.J

VOHVOL- ..-.....'-L....L......L-.....--.J

U 1/0

VVOH-

WV\ ....... ~!:.~ .......

IL-~

Remerk L I/O: Don't care

94

Dalain

NEe

pPD4264165,4265165

Lower Byte Lete Write Cycle
"

il"
I

i,

"

tCIH
blaH

LeAS

V,HV,L-

Address

VIiVn.-

WE

V,HV,L-

tCAS

i
I

I
!

I,
OE

V,HV,Lloot

Lila

Remark

V,HV,L-

ZZD-------!'IJ:-~-------

Data in

U I/O: Don't care

95

NEe

yPD4264165,4265165

Read Modify Write Cycle
towc

tRAS

Vi....
V,LtCSH
tAco

Address

V,HV,L-

WE

V,HV,L-

tASH

twp

tcwo

tOEA

OE

V,HV,L-

u VO

V,HV,L-

tOEH

tos

LVO

u VO VOt---0

~
Data out

toEz

--Q

Data out

"

---

Ramark In the hyper page mode, read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

99

NEe

gPD4264165,4265165

Hyper Pege Mode Byte Reed Cycle

~

RASP

tRHCP

tHPC

tCSH
V,HUCAS VIk-

V,HLCAS V,L-

Address

V,HV,L-

WE

V,HV,l-

OE V,HV'L-

.~

tReD

~

,\

~~
Row

tHCAS

~

to,"

tJw.

~
Col.

~

~~

~~

Col.

Col.

~~

~

tOFe

XXX;

t~U
/////If

K:
~~
~

~
~

\ \ \ \ \\\ \ \ \\tRAe
\ ,;::;
tCAe

VOH-

tMRH

~

j

tAep

tAep

tAA

tAA

tCAe

~

~
.J.

~
~

~~

~

tAA

U I/O VOL-

~

J

~

-'~

'1 '-

tASH
tHCAS

tHCAS

toHc

to£z

~

~

---------------~:-:----------~

Data out

--

-

-------- ----i)

Data out

jJ--

tDHe
I4-t

----------------~l:~---------------------------t).
Remerk

100

Data out

-------------------- 11--

1. In the hyper page mode, read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control
UCAS or LCAS simultaneously, or at random.

NEe

yPD4264165,4265165

Hyper Pege Mode Reed Cycle (WE Control)
tRASP
tRHCP

tcSH

Address

V,HVIL-

WE

V,HVIL-

OE

V,HV,l-

U I/O
L I/O

VOHVOl-

Remerk

___________ •••• I:'i:]........•..

In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

101

NEe

yPD4264165,4265165

Hyper Pege Mode Reed Cycle (OE Control)

teSH

UCAS V,H- -;-i+--"'-:!h
LCAS VIl-

Address

V,HVIl-

toEs

WE

VIH~

VIl-

toeH

tCHO
lAc.

OE

V,HVIl-

UI/O VOHHi-Z
L I/O VOl- -------------------------

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

102

",
"

NEe

yPD4264165,4265165

Hyper Pege Mode Eerly Write Cycle

I'{

Address

VII•.
VIL-

I

U VO
L VO

VII<- ~r7l:-"7r"7t""7(""7I. 11-----"'"'\1
VIL-

Remerks ,. OE: Don't care

2. In the hyper page mode, read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

103

NEe

yPD4264165,4265165

Hyper Page Mode Byte Early Write Cycle
tAP

tRASP
tRHCP

V,H-

Address V,L-

U I/O V,HV,L-

L I/O V,HV,L-

Remarks 1. OE: Don't care

2. In the hyper page mode, read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control
UCAS or LCAS simultaneously, or at random.

104

N~
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---IIl_P_D_4_2_6_4_16_5;..;..,_4_2...;...65_1_6;...5_ _ _~Ji
'/:

,i

~\

I!

Hyper Page Moda Late Write Cycle

Ii
tRASP

Iiil

tRHCP

Address

WE

V,HV,L-

OE

V,HV,L-

U I/O
L I/O

V,H- .______
V,L-

tttL _____ _

Remark In the hyper page mode. read. write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

105

NEe

yPD4264165,4265165

Hyper Page Mode Byte Late Write Cycle
tRASP
tAHCP

VII..V,LtCSH

tHPC

tHCAS

tASH

tHCAS

V,HV,L-

V,HV,L-

Address

V,HV,L-

V,HV,L-

V,HV,L-

L-t....J.-L-L..J

U VA V,HV,L-

L

va

V,H- ______ ~LL _______ _
VIl-

Remarks 1. In the hyper page mode, read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control
UCAS or LCAS simultaneously, or at random.

106

i~

___N_E_C
_______________---tIl_P_D_4_2_6_4_16_5,..;.,_4_2_65_1_6-.;.5_ _ _ _~.~;$
Hyper Pege Mode R..d Modify Write Cycle

OE

V,HVIL-

I'
U I/O VOHLIIO VOL-

U I/O
L I/O

V,HVIL-

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

107

NEe

yPD4264165,4265165

Hyper Page Mode Byte Read Modify Write Cycle
tRASP

tHPR

tHCAS

tHCAS

~~ ---V~+------V~----------~r---r---------------~r------------+~r-~-
VIL-

~~ ---V~~----~-4-----------H~~~----------+V---++------------+4---~~
VIL-

Address VI~
VIL-

VI~ -r-r-r+-r-t~::L~===~
VIL-

U 110 VO~
VOL-

L 110 VO~

Hi-Z

VOL- -------------------------------- ---

VI~

U 110 VIL-

LIIO VI~
VIL-

Remarks 1. In the hyper page mode, read, write and read modify write cycles are available for each of

z.

108

the consecutive CAS cycles within the same RAS cycle.
This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control
UCAS or LCAS simultaneously, or at random.

NEe

yPD4264165,4265165

Hyper Page Mode Read and Write Cycle
1RAsp
1RHCP

UCAS
LCAS

Address

WE

V,H- -................."'T"'............~-t-~M
VIL-

U I/O
L I/O

VOHHi-Z
VOL- •• -.-- •• -.- •• - ••••• - ••••• - ••••••

••••••••••':!i:l-••• _•••• _•••••.
11>"

U I/O
LI/O

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same AAS cycle.

109

NEe

yPD4264165,4265165

CAS Before RAS Refresh Cycle

"Remark Address, OE: Don't care

I/O: Hi-Z

RAS Only Refresh Cycle
tRe
tRP

teRP

Address

Remark WE, OE: Don't care

110

I/O: Hi-Z

tRAS

I~

C _ _ _ _ _ _ _ _ _ _ _ _ _ _---lJ.L:;:.;P.....:D:...4.:.;;;2.:.;;;6....:.4...:...16.:....:5:;..:.,....;4;..:;;;2;.;;.6.;;,..51.;;,.;6;;..;;5:...-_ _ _ i~
___N_E..;;;;....;~
i

,:

I~

i:i
ii.

Hidden Refresh Cycle (Re.d)

~

,t

Ii

tRC
tRAS

tRAS

III

RAS

VIHV,L-

tCRP

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE V,HV'L-

OE V,HV,L-

I:,
U VO VOHL VO VOI.-

Hi-Z

-------------------.-.--.------------------

Data out

I.

Hi-Z

I ..

111

NEe

yPD4264165,4265165

Hidden R.'....., Cycle (Write)

tRC

tRC

bIAs

RAS

VII'VIltCRP

~

tCHR

tCPN

VII....
V,L-

Address

vo

Vi ....

V,L-

£..l...........................x..;.............:...JI "'_ _ _ _-JO

Remark OE: Don't care

112

"-l~~...JL....v.....K.....l~~.............x..;.......,"-".......................-"-......................

, ~.

N~
~
-------=::::..----___________
J.Jl~P~D~4~2~64:!..1~6~5'L,~42~6~5~1~65~_ _ _ J
1.;;1

, ~~

Package Drawings

50PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

~+-----------_r------------~

H

~~

k

;tJ

J

L

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM
A

MILLIMETERS
21.17 MAX.
1.0 MAX.
0.8 (T.P.)

INCHES
0.834 MAX.
0.040 MAX.
0.031 (T.P.)

0

0.32~g:g9

0.013±0.003

E
F

0.1±0.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400±0.004

B
C

G

H

0.8±0.2

0.031 ~g:ggg

K

0.145~8:m

0.006±0.001

L

0.5±O.1

O.020~g:gg~

M
N

0.13
0.10
30• 70
-3'

0.005
0.004

P

3-+7-

-3'
S50G5-80-7JF3

113

NEe

yPD4264165,4265165

Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the ",PD42S16165L, 4216165L.

Types of Surface Mount Device
PPD426416SGS.426S16SGS: SO·pin plastic TSOP (n) (400 mill

114

I,
I'

i

Hyper Page Mode (EDO)
16M Dynamic RAM
[S.Ov

+

10%]

115

DATA SHEET

~------------------------------------ ii

NEe

!

MOS INTEGRATED CIRCUIT

,J

~PD42S16405,4216405

;1
1

16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, HYPER PAGE MODE (EDO)

Description
The jlPD42S16405, 4216405 are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional hyper page mode
(EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the jlPD42S16405 can execute CAS before RAS self refresh.
The jlPD42S16405, 4216405 are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ.

Features
Hyper page mode (EDO)
4,194,304 words by 4 bits organization
Single +5.0 V ±10 % power supply
Power
consumption
Active (MAX.)

Access time
(MAX.)

.uPD42S16405-50, 4216405-50

550 mW

50 ns

84 ns

20 ns

.uPD42S 16405-60, 4216405-60

495 mW

60 ns

104 ns

25 ns

JiPD42S16405-70, 4216405-70

440 mW

70 ns

124 ns

30 ns

Part number

RIW cycle time

Hyper page mode (EDO)

(MIN.)

cycle time (MIN.)

jlPD42S16405 can execute CAS before RAS self refresh

Part number
.uPD42S16405

Refresh cycle
4,096 cycles/128 ms

Refresh
CAS before RAS self refresh
CAS before RAS refresh

Power consumption
at standby (MAX.)
1.4 rnW
(CMOS level input)

RAS only refresh
Hidden refresh
JiPD4216405

4,096 cycles/64 ms

CAS before ro\S refresh
RAS only refresh

5.5 mW
(CMOS level input)

Hidden refresh

The information in this document is subject to change without notice.
Document No. M10066EJ4VODSU1

117

NEe

yPD42S16405,4216405

Ordering Information

Part number

Access time
(MAX.)

/lPD42S1640SG3-S0

SO ns

/lPD42S1640SG3-60

60 ns

/lPD42S1640SG3-70

70 ns

Package
26-pin plastic TSOP (II)
(300 mil)

Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh

118

/lPD42S 1640SLA-SO

SO ns

/lPD42S 1640SLA-60

60 ns

/lPD42S1640SLA-70

70 ns

/lPD421640SG3-S0

SO ns

/lPD421640SG3-60

60 ns

/lPD421640SG3-70

70 ns

/lPD421640SLA-SO

SO ns

/lPD421640SLA-60

60 ns

/lPD421640SLA-70

70 ns

Hidden refresh
26-pin plastic SOJ
(300 mil)

26-pin plastic TSOP (II)
(300 mil)

CAS before RAS refresh
RAS only refresh
Hidden refresh

26-pin plastic SOJ
(300 mil)

NEe

I

yPD42S16405,4216405

Pin Configurations (Marking Side)
26-pln Plastic TSOP (II) (300 mil)

II,

26-pin Plastic SOJ (300 mil)

t

GND

Vee

1/01

1/04

1/01

10
2

1/02

1/03

1/02

3

CAS

WE

4

OE

RAS

5

A9

A11

6

A8

A10

8

A7

AO

9

A7
A6

26

Vee

WE

1::1::
'V 'V

RAS

22

A11

....
~

A10

elS

"'(/1

...

5:~

21

GND

,
\:,

1/03

cc
~t

... ...
......
5:~
"'(/1

,~

CAS

1::1::
'V 'V

11"

OE

21

~

A9

l>r;

I,

1

A8

A1

10

A6

A1

10

A2

11

A5

A2

11

A5

A3

12

A4

A3

12

Vee

13

Vee

13

A4
GND

AO to A11

I ,~'

1/04

.. en

'"

AO

26

14

GND

14

: Address Inputs

1/01 to 1/04: Data Inputs/Outputs
RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE
Vee

Output Enable

GND

Ground

Power Supply

119

NEe

yPD42S16405,4216405

Block Diagram

Clock
Generator

Vee

0----

GND 0----

CAS before
RAS Counter
Q;

Memory

"0

8
Q)

0

;=
0

a:

Row
Address
Buffer
AO
to
A11
Column
Address
Buffer

120

co

'"
0

"

Cell
Array
4,096 x 1,024 x 4

1/01
to
1/04

NEe

HPD42S16405,4216405

Input/Output Pin Functions
The JlPD42S16405, 4216405 have input pins RAS, CAS, WE, OE, AO to A 11 and input/output pins 1/01 to 1/04.

Pin name
RAS

Input/Output
Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.

I! refreshes memory cell array of one line selected by the row address.
I! also selects the following function.
• CAS before RAS refresh
CAS

Input

CAS activates data input/output circuit by latching column address and

Input

Address bus.

(Column address strobe)
AOto All

selecting a digit line connected with the sense amplifier.

(Address inputs)

Input total 22-bit of address signal, upper 12-bit and lower 10-bit in sequence
(address multiplex method).
Therefore, one word is selected from 4,194,304-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activati ng RAS.
Then, switch the address bus to column address and activate CAS.

-

-

Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
WE

Input

(Write enable)
OE

Write control signal.

----

-

Write operation is executed by activating RAS, CAS and WE.
Input

(Output enable)

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1101 to 1104
(Data inputs/outputs)

Input/Output

4-bit data bus.

1101 to 1104 are used to input/output data.

121

NEe

yPD42S16405, 4216405

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.

1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle.

The hyper page mode (EDO) allows both read and write operations during one cycle, but the

performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mode (EDO) Read Cycle
RAS

V,HV,LtHPC

CAS

V,HV,L-

Address

V,HV,L-

--r-t----±:-,

teAe
WE

V,HV,LtOCH
tOEA

OE

V,HV,L-

I/O VOHHi-Z
VOL- .----------------------------

122

I

,
1~

___N_E_C
______________-- tRAD (MAX.) and tRCD !> tRCD (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.) and tRCD !> tRCD (MAX.)

tAA (MAX.)

tRAQ

tRCD > tRCD (MAX.)

tCAC (MAX.)

tRCD + tCAC (MAX.)

1i

+ tAA (MAX.)

tRAO(MAX.) and tRCO(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tM or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAO <: tRAO (MAX.) and tRCO <: tRCO (MAX.) will not cause
any operation problems.

3. tCRP (M)N.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the IlPD42S16405.
Read Cycle
Parameter

Symbol

tRAC = 50 ns

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

60

-

70

ns

1

15

-

18

ns

1

30

-

35

ns

1

18

ns

35

ns

Access time from RAS

tRAC

-

50

Access time from CAS

tCAC

13

Access time from column address

IAA

25

Access lime from OE

10EA

-

13

-

Column address lead time referenced to RAS

tRAL

25

-

30

Read command setup time

IRCS

0

-

0

Read command hold time referenced to RAS

tRRH

0

0

15

Unit Notes

Read command hold time referenced to CAS

tRCH

0

-

0

-

0

-

ns

2

Output buffer turn-off delay time from OE

tOEZ

0

10

0

13

0

15

ns

3

CAS hold time to OE

tCHO

5

-

5

-

5

-

ns

0
0

ns
ns

2

Notes 1. For read cycles, access time is defined as follows:
Inpul conditions
tRAD!> tRAD (MAX.) and tRCD !> tRCD (MAX.)
tRAQ> tRAQ (MAX.)

and

tACO

tRCD> tReD (MAX.)

:s;

tACO (MAX.)

Access time

Access time from RAS

tRAC (MAX.)

tRAe (MAX.)

tAA (MAX.)

tRAO

+ tAA (MAX.)

tCAC (MAX.)

tRCO

+

tCAC (MAX.)

tRAO (MAX.) and tRco (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAO <: tRAO (MAX.) and tRCO <: tRCO (MAX.) will not cause
any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

127

NEe

yPD42S16405,4216405

Write Cycle
Parameler
WE hold lime referenced 10 CAS

Symbol
IweH

IRAe = 50 ns

IRAe = 60 ns

IRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

7

-

10

10

-

10

-

0

-

0

-

WE pulse widlh

Iwp

7

WE lead lime referenced 10 RAS

IRWL

10

WE lead lime referenced 10 CAS

ICWL

7

WE selup lime

Iwes

0

OE hold lime

10EH

0

Dala-in selup lime

los

0

Data-in hold time

tOH

7

10
10

0
10

Unil Noles
ns

1
1

-

ns
ns

12

-

0

-

ns

-

ns

3

ns

3

10
12

0
0
10

ns
2

ns

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle.
3. tos (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
Parameler

Symbol

tRAe = 50 ns

IRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

133

157

-

37

-

ns

32

-

54

-

Read modify write cycle time

IRwe

107

RAS to WE delay lime

tRWD

64

CAS 10 WE delay lime

lewD

27

Column address to WE delay lime

tAW"

39

77

47

89

Unit Note

ns

1

ns

1

ns

1

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRwD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tcPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

128

! ;~

i ~~

_____~_E~c:~__________________________~y~P~D~4~2S~1~6~4~05~,_4~2~16~4~o~5______~;1
I:
'I,:

Hyper Page Mode (EDO)

Parameter

tRAC = 50 ns

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MIN.

Unit Notes

Symbol
MAX.

MAX.

Read I Write cycle time

tHPC

20

-

25

-

30

-

ns

RAS pulse width

tRASP

50

125,000

60

125,000

70

125,000

ns

CAS pulse width

tHCAS

7

10,000

10

10,000

12

10,000

ns

CAS precharge time

tcp

7

-

10

-

10

-

ns

Access time from CAS precharge

tACP

-

30

-

35

-

40

ns

CAS precharge to WE delay time

tCPwD

41

-

52

-

59

ns

tRHCP

30

-

35

-

40

-

tHPRWC

52

-

66

-

75

-

ns

Data output hold Time

tOHC

5

-

5

-

5

-

ns

OE to CAS hold time

tOCH

5

-

5

-

5

-

ns

RAS hold time from CAS precharge
Read modify write cycle time

1

2

ns

4

OE precharge time

tOEP

5

-

5

-

5

-

ns

Output buffer turn-off delay from WE

tWEZ

0

10

0

13

0

15

ns

WE pulse width

twpz

7

-

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

10

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFC

0

10

0

13

0

15

ns

3,4

3,4

Notes 1. tHPC (MIN.) is applied to CAS access.

2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1) Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

129

NEe

yPD42S16405,4216405

Refresh Cycle
Parameter

Symbol

tRAO = 50 ns

tRAO = 60 ns

tRAO = 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Note

CAS setup time

tOSR

5

-

5

-

5

-

ns

CAS hold time (CAS before RAS refresh)

tOHR

10

-

10

-

10

-

ns

RAS precharge CAS hold time

tRPC

5

-

5

-

5

-

ns

RAS pulse width (CAS before RAS self refresh)

tRASS

100

100

-

JlS

1

tRPS

90

-

100

RAS precharge time (CAS before RAS self refresh)

-

130

-

ns

1

CAS hold time (CAS before RAS self refresh)

tOHS

-50

-

ns

1

WE setup time

twsR

WE hold time

tWHR

-

-50

110
-50

10

-

15

-

15

Note 1. This specification is applied only to the ttPD42S16405.

130

Unit

10

10

-

ns

15

-

ns

NEe

yPD42S16405,4216405

Read Cycle
tRe
tRAS

RAS

tRP

V'HV'LtesH

CAS

V'HV'L-

Address

V'HV'L-

WE

V'HV'L-

OE

V'HV'L-

tCLZ

IcLz
1/0

VOH-. ___ •••••••••••••••••••••• ~~:.~ •••••••••••••••••••••••••••••••••
VOL-

tOFR

Data out

Hi -Z

131

NEe

yPD42S16405,4216405

Early Write Cycle
tRC
tRAS

VIt+-

V,LtCSH

Address

V,HV,L-

1/0

V,HV,L-

Remark DE: Don't

132

car~

____N~E~C~__________________________~y~P=D~42=S~1~64~O~5~,~42~1~6~4O~5~____~!.~11
::~

11
Late Write Cycle

'~

"

I

tRC
tRAS

!.

V,HV,L-

V,HV,L-

Address

VIH-

V,L-

"
WE

V,HV,L-

tOEH

OE

V,HV,LtOED

1/0

V,HV,L-

~----~~~-------

I:

133

NEe

yPD42S16405,4216405

Read Modify Write Cycle
IRwe
IRAS

V,HV,LleSH

Address

WE

V,HV,L-

OE

V,HV,L-

IDEA

tOEH

IDS

1/0

V,HV,L-

~---------

-

IDH

Dalain
100z

1/0 VOHVOL-

134

Hi-Z

!,/(

NEe

,uPD42S16405, 421640511

----~~~~---------------------------------------c~~~~~~~~~~~------~i

f

I
~.

Hyper Page Mode (EDO) Read Cycle

!I

RAS

~
CAS

V1H-

V,l-

Address

V,HV,l-

WE

V,HV,l-

~

IAHCP

ICSH
tACO

~~
Row

tHCAS

~

~

-.I

~

~
}r-.

tHCAS

tRAL

~

~

Col.

~

~n
COI.)OO

~

~
Col.

It

'-

lASH

tHPC
tHCAS

:1

tAP

tAASP

V,HV,l-

YJ /

!

~
tOFA

'--

IOFC

JO(X )(

I~

I-

/////1

~~
AAH

"\

J//

IwEZ

OE

V,HV,l-

\\\\\\\\\\~
IRAC
IAA
tCAC

~

I/O

VOH-

VOl-

_______________ ttl: __________
_~

tAcp

~

~

~

IACP
lAA
ICAC

lAA
ICAC

Dala oul

~--O

Dala oul

~~

/

\\ ,\
tOEZ

--0

Dala oul

---

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

135

NEe

yPD42S16405,4216405

Hyper Page Mode (EDO) Read Cycle (WE Control)
tRASP

RAS

tRHCP

V,HV,LtesH

CAS

V,HVIL-

Address

V,HVIL-

WE

V,HV,L-

OE

V,HV,L-

I/O

VOHVOL-

•••••••••••••••l:Il:f. ......... .

Data out

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

136

['
!f
-------.;;;;.-------------------------~-----...;......;......;..:....--...;...-...;...-------',.~
'4

NEe

yPD42S16405, 4216405

Hyper Page Mode (EDO) Read Cycle (OE Control)
ASP

-----

RAS V,H-

V,L-

~
tRHCP

lesH

J

CAS

~

IReD

I

~

A

~

CoLA

I

/

~ ~

~~

X)

CoLC

COL8m

/

~

'XX

X

lOCH

--

\\~\\\\\\\

!!'

~

~

~
.......

/
~

----------~;!----------- ~B

eAC
IAA

lOCH

\.. r--

IAcP

4 t-d

~I-I--

~

~

~ I~
r--'I

EA
.1m;

..--!9!4

IclZ

----

\\\\

ICHO

IAcp

~

I~HH
I-IRR

tOES

ICHO

~

..

.. IOFR

IAA

1M

~

/////!

VOH110 VOL-

~

tHCAS

~

tRAG

tOEA

DE

I~

tHeAs

~

tRAL

IR~

V,HV,L-

'-

tRSH

~
Row

WE

~

IHCAS

\\

~

Address

IHPC

IOEZ

/

\\\\

~

~ Data out B}--- ~ Data out B -- ~ Data out C

--fjj~~-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

137

NEe

yPD42S16405,4216405

Hyper Page Mode (EDO) Early Write Cycle

V,H-

V,l-

VIH-

V,l-

Address

V,H-

V,l-

V,H- ~"""'I""""'I"""-'-""
V,l-

I/O

V,HV,l-

l..Jot....ll~...K...lt...lI II._ _ _ _-Ji

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

138

Nee

i

pPD42S16405,4216405

------~~~~----------------------------------------~~~~~~~~~~~~~--------~Il

!l
,~

Hyper Page Mode (EDO) Late Write Cycle

IiI.~

tRP

tRASP

t

RHCP

't

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

Ii

I:
I:

1/0

V,HV,L-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

139

NEe

yPD42S16405,4216405

Hyper Page Mode CEDO) Read Modify Write Cycle

1/0

VOHVOl-

1/0

V,HVIl-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

140

Ii

.~

_ _N_E_C~_ _ _ _ _ _ _ _ _ _ _ _ _. . J1_P_D_42_S;;....1...;.6_40.;....5-,-,
..
_42_1.....;6_4.....;05~_ _ _,:~
;1,

I!.
!~

Hyper Page Mode (EDO) Read and Write Cycle

Ii

tRASP

RAS

tRHCP

V,HV,L-

';1
,of

tCSH

CAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

I
I
I

I/O

VOHHi - Z
VOL- ••••••••••••••••••••••••••••••••

1/0

V,HV,L-

.•........ .f:!l: ?-. ............. .

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

141

NEe

yPD42S16405,4216405

CAS Before RAS Self Refresh Cycle (Only for the JLPD42S16405)

lRASS

ICSR

~\\\\\\\\\\\\\\\\\\\\\\\
Remark Address, OE : Don't care

I/O: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh

CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh

When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 4,096 times within a 64 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh

When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 4,096 times within a 64 ms interval just before and after setting CAS before RAS self refresh.

*

(3) If tRASS(MIN.) is not saisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 JLS), CAS before
RAS refresh cycles will be executed one time.
If 10 JLS < tRAS < 100 JLS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (4,096/128 ms) should be met.
For details, please refer to How to use DRAM User's Manual.

142

I,

i

_ _.;...N_E=..;;;C~_ _ _ _ _ _ _ _ _ _ _ _---t;J.l_P_D...;..4.;;;;;..2S;;;....1;;....;6_40_5;..c.,_4_21_6_4_°5_ _ _ _ 1
1

Ii
CAS Before RAS Refresh Cycle

M

'~

tRC

II

tRC

tRAS

I~
i
\i

V,HV,L-

tCSR

leHR

V,HV,L-

Remark Address, OE: Don't care

1/0: Hi-Z

RAS Only Refresh Cycle

tRAS

tRP

tRAS

V,HV,L-

tCRP

Address

V,HVIL-

Remark WE, OE: Don't care

1/0: Hi-Z

143

NEe

yPD42S16405,4216405

Hidden Refresh Cycle (Read)

ICRP

IRCD

IRC

IRC

lRAS

tRAS

IRSH

ICPN

ICHR

CAS V,HVIL-

WE

V,HV,l-

OE V,H-

V,l- .....;......I....J~....1.-T..............+-~......"-1-l~-:------+--_.J--h-.......l......--'~......r'--+............-"-

IcLZ
Hi - Z
VOl- -------------------------------------------

1/0 VOH-

144

Dala out

__

~N~E~C~________________________~H~P~D~42~S~1~64~O~5~,4_2_1~64_0~5____~1,
Ii

Hidden Refresh Cycle (Write)
lAC

:1
,\

V,H-

Address

~::~

V,H-

1/0

V,HVIL- L-lo(...¥,..K...¥...lt....¥..x..~1(;...l/

' -_ _ _~ "-'.................."'-''''-''..............,..;..................."'"-'....................................

Remark OE: Don't care

Ii!'I

145

NEe

yPD42S16405,4216405
(WE, en Before 'Rn Refresh Cycle)

Test Mode Set Cycle

Remark Address,

DE:

Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
16-bit organization during test mode. Don't care about the input levels of the CAS input AO, A 1.

(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.

(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1": Normal write (all memory cells)
Output = "0": Abnormal write

(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.

(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

146

____~~E~C~________________________~y~P_D_42_S~1~64_0~5~,~42_1~6_40~5____~,
"

:1

Package Drawings

26PIN PLASTIC TSOP(II) (300 mil)

detail of lead end

-+-I~-----+------t-

A

13

.1
H

~&

~

Jl

L

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A
B
C

17.36 MAX.
1.06 MAX.
1.27 (T.P.)

0.684 MAX.
0.042 MAX.
0.050 (T.P.)

0

0.42~8:8¥

0.017±0.003

E
F

0.HO.05
1.2 MAX.
0.97
9.22±0.2
7.62±0.1

0.004±0.002
0.048 MAX.
0.038
0.363±0.008
0.300±0.004

G
H

K

0.8±0.2

0.031 ~8:88~

0.145~8:8~~

0.006±0.001

L

0.5±0.1

0.020~8:88~

M
N

0.21
0.10

0.009
0.004

P

3 +7
-3

I

I

I.

3 +7
-3
S28G3·50-7JD1

147

NEe

fLPD42S16405,4216405

26 PIN PLASTIC SOJ (300 mil)

U

Cl

13

J: -

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

17.3~8:~g

0.681~8:8?S

c

7.62

0.300

0

8A7±0.2

0.333~8:883

E

1.03±0.15

0.041 ~8:88~

F

0.029

K

0.74
3.5±0.2
2.545±0.2
O.B MIN.
2.6
1.27 (T.P.)

M

0.40±0.10

0.016~8:88~

N
P

0.C05

T

0.12
6.73±0.2
0.10
RO.85

u

0.20~8:&g

0.008~8:88~

G
H

Q

0.138±0.00B

0.100±0.008
0.031 MIN.
0.102
0.050 (T.P.)

0.265±0.008
0.004
RO.033

S26LA-300A-l

148

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yPD42S16405,4216405

Recommended Soldering Conditions

j

i·"l
! '·
i

The following conditions (see tables below and next page) must be met for soldering conditions of the
~PD42S16405, 4216405.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).

i.
"

Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
~D42S1640SG3,

421640SG3: 26-pin plastic TSOP (I) (300 mil)

Soldering process

Soldering conditions

Symbol

Infrared ray reflow

Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use _tar to remove
residual flux (water can be used In the second process).

IR35-107-2

VPS

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit :7 daysNote

VP15-107-2

(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first rellow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

Terminal temperature: 300'C or lower,
Time: 3 seconds or lowar (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

149

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yPD42S16405,4216405

,uPD42S18405LA,4218405LA: 28-pln plastic SOJ (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the flrat raflow process, cool the package down to room
temperatura, then start the second reflow process.
2. After the flrat reflow procesa, do not use water to remove
residual flux (water cen be used In the second process).
VPS

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

VP15-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second raflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

150

Terminal temperature: 300'C or lower,
Time: 3 seconds or less (Per side of the package).

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD42S17405,4217405
16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, HYPER PAGE MODE (EDO)

Description
The ,uPD42S 17405,4217405 are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional hyper page mode
(EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the ,uPD42S17405 can execute CAS before RAS self refresh.
The ,uPD42S17405, 4217405 are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ.

Features
Hyper page mode (EDO)
4,194,304 words by 4 bits organization
Single +5.0 V ±10 % power supply
Power
consumption

Part number

Active (MAX.)

Access time
(MAX.)

RfW cycle time
(MIN.)

Hyper page mode (EDO)
cycle time (MIN.)

pPD42S 17405-50, 4217405-50

660 mW

50 ns

84 ns

20 ns

pPD42S17405-60, 4217405-60

605 mW

60 ns

104 ns

25 ns

pPD42S17405-70, 4217405-70

550 mW

70 ns

124 ns

30 ns

,uPD42S17405 can execute CAS before RAS self refresh

Part number
pPD42S17405

Refresh cycle
2,048 cyclesl128 ms

Refresh
CAS before RAS self refresh
CAS before RAS refresh

Power consumption
at standby (MAX.)
1.4 mW
(CMOS level input)

RAS only refresh
Hidden refresh
pPD4217405

2,048 cycles/32 ms

CAS before RAS refresh
RAS only refresh

5.5mW
(CMOS level input)

Hidden refresh

Thalnlormatlon In this document Is subject to change without notice.
Document No. M1 0067EJ5VODSU1

151

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yPD42S17405,4217405

Ordering Information

Part number

Access time
(MAX.)

Package

Refresh

JlPD42S17405G3-50

50 ns

26-pin plastic TSOP (II)

CAS before RAS self refresh

JlPD42S 17405G3-60

60 ns

(300 mil)

CAS before RAS refresh

JlPD42S17405G3-70

70 ns

JlPD42S 17405LA-50

50 ns

JlPD42S17405LA-60

60 ns

RAS only refresh

JlPD42S17405LA-70

70 ns

JlPD4217405G3-50

50 ns

Hidden refresh
26-pin plastic SOJ
(300 mil)

26-pin plastic TSOP (II)
(300 mil)

JlPD4217405G3-60

60 ns

JlPD4217405G3-70

70 ns

JlPD4217405LA-50

50 ns

26-pin plastic SOJ

JlPD4217405LA-60

60 ns

(300 mil)

JlPD4217405LA-70

70 ns

CAS before RAS refresh
RAS only refresh
Hidden refresh

152

!~~
t;

NEe

'i

,uPD42S17405,4217405

!iI!

~
'~

I,~

:,
'i

PIn ConfiguratIons (Marking Side)
28-pln Plastic TSOP (I) (300 mil)

"I

26-pin Plastic SOJ (300 mil)

!i
il,"

GND

Vee

1/01

1/04

1/01

1/02

1/03

1/02

26

Vee

......

WE

5
6

A10
AO
A1
A2

8
9
10
11
12
13

A3

Vee

CAS

"11"11

RAS
NC

~~

.... 1/1

Ii

OE

21

A9

14

A8
A7
A6
A5
A4
GND

Co>

WE

RAS
NC
A10
AO
A1
A2

A3
Vee

10
2
3
4
5
6
8

26

1/04
1/03

... ...

~~
.... 1/1
........
........

.~

CAS

"11"11

21

!i:~
!j;j!!

OE

t

A9

.~

':i)i

~

A8
A7
A6
A5

)0

9

10
11
12
13

GND

A4

14

GND

AO to Al0 : Address Inputs

1101 to 1/04: Data Inputs/Outputs
RAS
CAS
WE
OE

Row Address Strobe
Column Address Strobe
Write Enable

Vee

Output Enable
Power Supply

GND

Ground

NC

No Connection

153

NEe

yPD42S17405,4217405

Block Diagram

Clock
Generator

Vee 0 - - GNOO---

CAS before
RASCounter
Memory
Cell
Array
I/Ot
to
1/04
Row
Address
Buffer

AO
to
AtO
Column
Address
Buffer

154

,1
NEe

----------~~

______________________________________

yPD42S17405, 4217405 __________ii

_c~~~~~~~~~~~

.~

!
II

Input/Output Pin Functions

'1

The jlPD42S 17405, 4217405 have input pins RAS, CAS, WE, OE, AD to A 10 and input/output pins 1/01 to 1/04.

Pin name
RAS

Input/Output
Input

(Row address strobe)

:~

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS
(Column address strobe)

Input

CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.

AD to A1D

Input

Address bus.

(Address inputs)

Input total 22-bit of address signal, upper 11-bit and lower 11-bit in sequence
(address multiplex method).
Therefore, one word is selected from 4, 194,3D4-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.

WE
(Write enable)

Input

OE

Input

Write control signal.

----

-

Write operation is executed by activating RAS, CAS and WE.

(Output enable)

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
I! WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/04
(Data inputs/outputs)

Input/Output

4-bit data bus.

1/01 to 1/04 are used to input/output data.

155

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yPD42S17405, 4217405

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.
1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO) , read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle, but the
performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
Hyper Page Mode (EDO) Read Cycle
VIH-

RAS

VIL-

V,HCAS

VIL-

Address

V,HDE V'L-

110 VOHVOL-

156

--.---1------+....,.

if'
i:

_---IN;...;;;;.;;;E;;;;;,C-=-_ _ _ _ _ _ _ _ _ _ _ _ _..s::.Jl;.;...P.;;;.D..;.;42;:;.;:S:;...;;1~74....;..;O;..;:;5.L...,..;.;42~1;..;..7~40.;;..;5~_ _ _li
Cautions when using the hyper page mode (EDO)
1.

OAS access should be used to operate tHPC at the MIN. value.

2. To make I/0s to HI-Z In read cycle. it Is necessary to control RAS, CAS. WE. OE as follows. The effective
specification depends on the state of each signal.
(1) Both ~ and ~ are Inactive (at the end of read cycle)

WE:

inactive.

O"E:

active

tOFC is effective when ~ is Inactivated before

.Ci\S is

inactivated.

tOFR is effective when ~ is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE,

Oe:

inactive' .... tOEZ is effective.

(3) Both RAS and CAS are Inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE. OE: active and either tRRH or tACH must be met ..... tWEZ and twpz are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive. OE: active ..... tCHO Is effective.
(2) CAS. OE: active ..... tOCH is effective.

157

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yPD42S17405,4217405

Electrical Specifications
All voltages are referenced to GND.
After power up (Vcc ~ VCC(MIN.), wait more than 100 J.IS (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuil.
Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

Parameter

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Po

1

W

Operating ambient temperature

T.

o to +70

Storage temperature

T""

-55 to +125

'c
'c

Caution

Symbol

Condition

Exposing the device to stress above those listed In Absolute Maximum Ratings could cause
permanent damage. The device Is not meant to be operated under conditions outside the limits
described In the operational section ofthls specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

High level input voltage

V,H

2.4

Vee + 1.0

V

Low level input voltage

V,L

-1.0

+0.8

V

Operating ambient temperature

T.

0

70

'C

Parameter

Capacitance (TA

= 25 t, f = 1

Parameter
Input capacitance

Data input/output capacitance

158

Symbol

Condition

MHz)
MAX.

Unit

Cit

Address

5

pF

C'2

RAS, CAS, WE, OE

7

C,IO

I/O

7

Test condition

Symbol

MIN.

TYP.

pF

___N_E_C
______________

- -J; J.l,;.;,.P~D. .;.4=2S~17:._4:. . :.0. :. 5~,4. :. :2: . . :1~7. . :. 40.: . ;5=_

__

~il
~~
..

I

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Operating current

Standby

IIPD42S17405

Icc1

lee2

current

Test condition
RAS, CAS cycling
tRe = tRe (M'N.), 10 = 0 mA

RAS, CAS

~

Vee - 0.2

RAS only refresh current

Operating current

leG3

lee4

(Hyper page mode (EDO))

CAS before RAS

Iccs

refresh current

CAS before RAS

lee6

RAS cycling
tRe = tRe (M'N.I, 10

CAS before RAS refresh:

long refresh current

tRe

(2,048 cycles I 128 ms,

= 0 mA

mA

1,2,3

tRAe

= 60 ns

110

tRAe

= 70 ns

100

:1
.~

2.0

mA

0.25
2.0

= 0 mA

RAS " VIL (MAX.), CAS cycling
tHPe = tHPe (M'N.), 10 = 0 mA

Notes

120

= 0 mA

RAS cycling, CAS ~ V'H (M'N.)
tRe = tRe (M'N.), 10 = 0 mA

Unit

= 50 ns

= 0 mA
V, 10 = 0 mA

RAS, CAS ~ Vee - 0.2 V, 10

MAX.

tRAG

RAS, CAS ~ V'H (M'N.I, 10

RAS, CAS ~ V'H (M'N.I, 10

IIPD4217405

MIN.

1.0

tRAe

= 50

ns

120

tRAe

= 60

ns

110

tRAe

= 70

ns

100

tRAe

= 50

ns

100

tRAe

= 60

ns

90

tRAe

= 70

ns

80

tRAe

= 50

ns

120

tRAe

= 60

ns

110

tRAe

= 70

ns

mA

1,2,3.4

mA

1,2,5

mA

1,2

tRAS" 300 ns

400

!lA

1,2

tRAS'; 1 liS

500

IIA

1,2

250

IIA

2

-10

+10

!lA

-10

+10

IIA

0.4

V

100

= 62.5 liS

RAS, CAS:
Vee - 0.2 V ,; V'H ,; V'H (MAX.)

only for the IIPD42S17405)

o V" VIL'; 0.2 V
Standby:
RAS, CAS

~

Vee - 0.2 V

Address: V'H or VIL
WE, OE: V'H
10
CAS before RAS

lee7

= 0 mA

RAS, CAS:

= 5 ms

self refresh current

tRASS

(only for the IIPD42S17405)

Vee - 0.2 V ,; V'H ,; V'H (MAX.)
o V,; VIL'; 0.2 V

Input leakage current

I'(L)

10

= 0 mA

VI

= 0 to

5.5 V

All other pins not under test
Output leakage current

10(LI

Vo

= 0 to

=0 V

5.5 V

Output is disabled (Hi-Z)
High level output voltage

VOH

10

= -5.0 mA

Low level output voltage

VOL

10

= +4.2

mA

2.4

V

Notes 1. Icc1, Icc3, Icc4, Iccs and lee6 depend on cycle rates (tRC and tHPC).

2. Specified values are obtained with outputs unloaded.
3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS ,,; VIL (MAX.)
and CAS ~ V(H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. IcC4 is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.

159

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yPD42S17405,4217405

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
VIH (MIN.)

= 2.4

V

VIL (MAX.)

= 0.8

V

(2) Output timing specification

---------------~

·--------3 i
I

I

.,1 :..

tr~ 2'ns

iL
I

------=J

VOH (MIN.)

= 2.4

V

VOL (MAX.)

= 0.4

V

I

}-

------~'__ _ _ _

_.J

..: :..

tr~ 2' ns

(3) Output load condition
Vee
8200
I/O--~--"

2900

Common to Read, Write, Read Modify Write Cycle
tRAe

= 70 ns

tRAe

MAX.

MIN.

MAX.

MIN.

MAX.

tRe

84

-

104

124

-

ns
ns

Unit Notes

RAS precharge time

tRP

30

-

40

-

50

-

CAS precharge time

tePN

7

-

10

-

10

-

ns

RAS pulse width

tRAS

50

10,000

60

10,000

70

10,000

ns

CAS pulse width

teAs

7

10,000

10

10,000

12

10,000

ns

Read I Write cycle time

1

RAS hold time

tRSH

10

-

10

-

12

tesH

38

-

40

-

50

-

ns

CAS hold time
RAS to CAS delay time

tReD

11

37

14

45

14

52

ns

RAS to column address delay time

tAAD

9

25

12

30

12

35

ns

2

CAS to RAS precharge time

teRP

5

-

5

-

5

-

ns

3

Row address setup time

IASR

0

0

-

0

-

ns

Row address hold time

tRAH

7

10

-

10

-

ns

Column address setup time

tAse

0

0

-

0

-

ns

Column address hold time

teAH

7

ns

tOES

0

0

-

-

OE lead time referenced to RAS

-

12
0

teL2

0

-

0

-

0

OE to data setup time

tOL2

0

-

0

-

0

-

ns

CAS to data setup time

BE to data delay time

toeD

10

-

13

-

15

-

ns

Transition time (rise and fall)
Refresh time

I
I

160

= 60 ns

tRAe = 50 ns
MIN.

Symbol

Parameter

JlPD42S17405
JlPD4217405

-

10

ns
2

ns
ns

IT

1

50

1

50

1

50

ns

tREF

-

128

-

128

-

128

ms

32

-

32

-

32

4

I--

I,r

1

___N_E.--.,;C=---_ _ _ _ _ _ _ _ _ _ _ _ _---LJ1~P...;::D......;4..::.2S..::...1..:...:7:.....;4:..=0..::...5,!_4.:..:2:....:1...:...7...:...40.::....:5=--_ _---,11
"

I!

Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 f.1S.
If 10 Ils < tRAS < 100 Ils, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions
tRAD ~ tRAD (MAX.)

and

tACO:::; tACO (MAX.)

tRAD> tRAD (MAX.)

and

tRCO

tRCD

>

:S

Access time

tRCO (MAX.)

tRCo (MAX.)

Access time from RAS

tRAC (MAX.)

tRAG (MAX.)

tM (MAX.)

tRAD

+

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

tAA (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the IlPD42S 17405.
Read Cycle
Parameter

Symbol

tRAG

= 50 ns

tRAG

= 60 ns

tRAG

= 70

ns

Unit Notes

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

50

-

60

-

70

ns

1

18

ns

1

35

ns

1

tOEA

-

18

ns

Column address lead time referenced to RAS

tRAL

25

Read command setup time

tRCS

0

ns

0

-

Access time from RAS

tRAC

Access time from CAS

tCAC

Access time from column address

tM

Access time from OE

13
25
13

15
30
15

Read command hold time referenced to RAS

tRRH

0

Read command hold time referenced to CAS

tRCH

0

-

35

ns

2

0

-

0

-

ns

2

Output buffer turn-off delay time from OE

tOEZ

0

10

0

13

0

15

ns

CAS hold time to OE

tCHO

5

-

5

-

5

-

ns

3

30
0
0

0

ns

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD:::; tRAD (MAX.)

and

tRCO

:S

tRCO (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.)

and

tACO

:5:

tRCO (MAX.)

tAA (MAX.)

tRAD

+ tAA (MAX.)

tcAC (MAX.)

tRCO

+

tRCO> tRCO (MAX.)

tCAC (MAX.)

tRAD(MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

161

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yPD42S17405,4217405

Write Cycle
Parameter
WE hold time referenced to CAS

tRAe
Symbol
tweH

= 50 ns

tRAe

= 60 ns

tRAe

= 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

7

-

10

-

10

-

Unit Notes
ns

1
1

WE pulse width

twp

7

-

10

-

10

-

ns

WE lead time referenced to RAS

tRWL

10

-

10

-

12

-

ns

10

-

12

-

ns

0

-

0

-

ns

WE lead time referenced to CAS

tewL

7

WE setup time

twes

0

OE hold time

tOEH

0

-

0

-

0

-

ns

Data-in setup time

tos

0

0

-

0

-

ns

3

Data-in hold time

tDH

7

-

10

-

10

-

ns

3

2

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs 2: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
tRAe
Parameter

Symbol

= 50 ns

tRAe

= 60 ns

tRAe

MIN.

MAX.

MIN.

MAX.

MIN.

= 70 ns

Unit Note

MAX.

Read modify write cycle time

tRWC

107

-

133

-

157

-

ns

RAS to WE delay time

tAWO

64

-

77

-

89

-

ns

1

CAS to WE delay time

tewD

27

-

32

-

37

-

ns

1

Column address to WE delay time

tAWD

39

-

47

-

54

-

ns

1

Note 1. If twcs 2: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD 2: tRWD (MIN.), tCWD 2: tCWD (MIN.), tAWD 2: tAWD (MIN.) and tCPWD 2: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

162

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yPD42S17405, 4217405

Hyper Page Mode (EDO)
tRAC
Parameter

Symbol
MIN.

= 50 ns

tRAC

MAX.

MIN.

= 60 ns
MAX.

tRAC
MIN.

= 70 ns

Unit Notes

MAX.

tHPC

20

-

25

-

30

-

ns

RAS pulse width

tRASP

50

125,000

60

125,000

70

125,000

ns

CAS pulse width

Read I Write cycle time

tHCAS

7

10,000

10

10,000

12

10,000

ns

CAS precharge time

tcp

7

-

10

-

10

-

ns

Access time from CAS precharge

tACP

-

30

-

35

-

40

ns

CAS precharge to WE delay time

tCPWD

41

-

59

-

ns

tRHCP

30

-

52

RAS hold time from CAS precharge

35

-

40

-

ns

tHPRWC

52

-

66

75

5

5

-

ns

5

5

-

5

-

ns

Read modify write cycle time

1

2

Data output hold time

tOHC

5

-

OE to CAS hold time

tacH

5

OE precharge time

tOEP

5

-

Output buffer turn-off delay from WE

tWEZ

0

10

0

13

0

15

ns

3,4

WE pulse width

twpz

7

-

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

10

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFC

0

10

0

13

0

15

ns

3,4

5

ns
ns

4

Notes 1. tHPC (MIN.) is applied to CAS access.

2. If twcs

;:>,

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle. If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEl (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective

specification depends on state of each signal.
(j)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEl is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and tWPl are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

163

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yPD42S17405,4217405

Refresh Cycle
tRAe
Parameter

Symbol

= 50 ns

= 60 ns

tRAe

= 70 ns

Unit Note

MAX.

MIN.

MAX.

MIN.

MAX.

-

5

-

5

ns

10

-

10

-

5

-

ns

100

/lS

1

ns

1

-50

-

ns

1

10

-

10

-

ns

15

-

15

-

ns

CAS setup time

tesR

5

CAS hold time (CAS before RAS refresh)

tCHR

10

RAS precharge CAS hold lime

tRPe

5

RAS pulse width (CAS before RAS self refresh)

tRASS

100

RAS precharge time (CAS before RAS self refresh)

tRPS

90

CAS hold time (CAS before RAS self refresh)

teHs

-50

WE setup time

tWSR

10

WE hold time

tWHR

15

Note 1. This specification is applied only to the JlPD42S17405.

164

tRAe

MIN.

5
100
110
-50

130

ns

I

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_ _;;...N~E=C=--_ _ _ _ _ _ _ _ _ _ _ _ _...t;.;.J1;,;...P=D....;,.42;;;..S;;...1;....;..7_40~5~,_4_2_17;.....4....;;.O....;;..5_ _ _....II~

I.;

Read Cycle
tRe
tRP

tRAS

RAS

V,HVILtesH

CAS

V,HVIL-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HVIL-

tOLZ

leu

1/0

VOH-. _______________________ __ ~! :_~
VOL-

________________________________ _

tOFR

Data out

Hi - Z

165

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yPD42S17405, 4217405

Early Write Cycle
tRe
tRAS

RAS

V,HV,LtesH

CAS

V,HV,L-

Address

1/0

V,HV,L-

Remark OE: Don't care

166

tRP

NEe

yPD42S17405, 4217405

Late Write Cycle
tRC
tRAS

V,HVIL-

V,HVIL-

Address

V,HVIL-

V,HVIL-

tOEH

V,HV,LtOED

1/0

V,H-

~ ____ ~t?

VIL-~

______ _

167

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yPD42S17405,4217405

Read Modify Write Cycle
tRwe
tRAS

tCSH
tReD

Address

tRSH

V,HVIL-

tewD

WE

V,HVIl-

OE

V,HV,L-

tOEA

teAe
1/0

V,HV,L-

~--------- -

tOEH

tos

tOH
Data in

toLZ

1/0

168

VOHVOL-

Hi-Z

Hi-Z

______
N E_C
____________________________

~y~P_D_42_S~1~7~40~5~,~4~21~7~4~o5~____~I.
Ifh
:t

Hyper Page Mode (EDO) Read Cycle

:i
tRASP

RAS

tRHCP

V1H-

CAS

V,HV,L-

~

tRCD

tHCAS

~

tHCAS

~

t: 6 ~ t:=JJ....l...~-'-~........,....->.....p..---+-+--Li-.L...J

V,HV,L- L....>'--"'->I.-"--"--"-",,-"'--'''-'' " -_ _ _ _-"

Remark DE: Don't care

179

NEe
Test Mode Set Cycle (WE,

yPD42S17405,4217405
CAS Before RAS Refresh Cycle)

V,HVIL-

V,HV,L-

V,HVIL-

Remark Address, OE: Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
16-bit organization during test mode. Don't care about the input levels of the CAS input AO, A 1.
(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1": Normal write (all memory cells)
Output = "0": Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

180

,
',~

_____
N_E
__c:____________________________~y_P_D_4_2S~1_7_4~05~,~4_2_1_74_0~5______~iJ
1\

Package Drawings

26PIN PLASTIC TSOP(II) (300 mil)
26
detail of lead end

~~----------1r------------~

llll
B

NOTE

Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

A

17.36 MAX.
1.06 MAX.
1.27 (T.P.)

INCHES
0.684 MAX.
0.042 MAX.
0.050 (T.P.)

B

C

0.42~g:g~

0.017±0.003

0.1 ±0.05
1.2 MAX.
0.97
9.22±0.2
7.62±0.1

0.004±0.002
0.048 MAX.
0.038
0.363±0.008
0.300±0.004

0.8±0.2

0.031~g:gg~

K

0.145~g:m

0.006±0.001

0.5±0.1

0.020~g:gg~

M
N

0.21
0.10

0.009
0.004

P

3 +7
-3

3 +7
-3
S26G3-50-7J01

D

E
F
G

H

181

NEe

yPD42S17405,4217405

26 PIN PLASTIC SOJ (300 mil)
B

26

14

-+-I-----+-------t-

()

0

13
E

J:

-

0jL ,

'-'$"I-N-@=I

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

17.3~g:~g

0.6Bl~g:g?g

C

7.62

0.300

D

B.47±0.2

0.333~g:88~

E

1.03±0.15

0.041 ~g:88~

F

K

0.74
3.5±0.2
2.545±0.2
O.B MIN.
2.6
1.27 (T.P.)

M

0.40±0.10

0.016~g:gg~

N
P

0.005

T

0.12
6.73±0.2
0.10
RO.85

U

0.20~g:6g

0.00B~8:88~

G
H

Q

0.029
0.13B±0.00B
0.100±0.00B

0.031 MIN.
0.102
0.050 (T.P.)

0.265±0.00B

0.004
RO.033

S26LA-300A-1

182

$

NEe

il

yPD42S17405, 4217405

--------------------------------------------------------~~----~~~~~~~~~~--------~~

i
~
i

Recommended Soldering Conditions

,
~

The following conditions (see tables below and next page) must be met for soldering conditions of the
jlPD42S17405, 4217405.

I,

For more details, referto our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
IlPD42S17405G3, 4217405G3: 26-pin plastic TSOP (II) (300 mil)
Soldering process

Soldering conditions

Symbol

Infrared ray reflow

Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. Atter the first reflow process, do not use water to remove
residual flux (water can be used in the second process).

IR35-107-2

VPS

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit :7 daysNote
(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. Atter the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. A tter the first reflow process, do not use water to remove
residual flux (water can be used in the second process).

VP15-107-2

Partial heating method

Terminal temperature: 300'C or lower,
Time: 3 seconds or lower (Per side of the package).

Note

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

183

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yPD42S17405,4217405

.uPD42S17405LA, 4217405LA: 26-pin plastic SOJ (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235·C or lower,
Reflow time: 30 seconds or less (210 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
VPS

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

VP15-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
Partial heating method

Note

Terminal temperature: 300'C or lower,
Time: 3 seconds or less (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25·C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

184

'1\

DATA SHEET

NEe

r------------------------------------------------------------MOS INTEGRATED CIRCUIT

j

'1:

l

_ _ _ _~J1_PD_4_2_S_'_78_0_5_,4_2_,_7_80_5_:1
16 M-BIT DYNAMIC RAM
2 M-WORD BY 8-BIT, HYPER PAGE MODE

II

---------------------;t
':g

~

Description
The .uPD42S 17805,4217805 are 2,097,152 words by 8 bits CMOS dynamic RAMs with optional hyper page mode.
Hyper page mode is a kind of the page mode and is useful for the read operation.
Besides, the .uPD42S17805 can execute CAS before RAS self refresh.
The .uPD42S17805, 4217805 are packaged in 28-pin plastic TSOP (II) and 28-pin plastic SOJ.

Features
Hyper page mode (EDO)
2,097,152 words by 8 bits organization
Single +5.0 V ±10 % power supply
Power
Part number

consumption
Active (MAX.)

Access time
(MAX.)

R/W cycle time
(MIN.)

Hyper page mode
cycle time
(MIN.)

I'PD42S 17805-60, 4217805-60

605 mW

60 ns

104 ns

25 ns

I'PD42S17805-70, 4217805-70

550 mW

70 ns

124 ns

30 ns

The .uPD42S17805 can execute CAS before RAS self refresh

Part number
I'PD42S 17805

Refresh cycle
2,048 cycles/128 ms

Refresh
CAS before RAS self refresh,
CAS before RAS refresh,

Power consumption
at standby (MAX.)
1.4mW
(CMOS level input)

RAS only refresh, H;dden refresh
I'PD4217805

2,048 cycles/32 ms

CAS before RAS refresh,
RAS only refresh,

5.5 mW
(CMOS level input)

Hidden refresh

The information in this document is subject to change without notice.
Document No. Ml 0069EJ4VODSUl

185

NEe

yPD42S17805,4217805

Ordering Information
Part number

Access time
(MAX.)

Package
28-pin Plastic TSOP (II)

jlPD42S17805G5-60

60 ns

jlPD42S17805G5-70

70 ns

(400 mil)

60 ns

jlPD42S17805LE-70

70 ns

jlPD4217805G5-60

60 ns
70 ns

jlPD4217805LE-60

60 ns

jlPD4217805LE-70

70 ns

(400 mil)

Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

28-pin Plastic SOJ

186

CAS before RAS refresh

(400 mil)

28-pin Plastic TSOP (II)

JlP D421 7805G5-70

CAS before RAS self refresh

RAS only refresh
28-pin Plastic SOJ

jlPD42S17805LE-60

Refresh

(400 mil)

Iii,
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II

yPD42S17805,4217805

!~,
,I

If!

i

Pin Configurations (Marking Side)

,I
I~

28-pin Plastic SOJ (400 mil)

28-pin Plastic TSOP (II) (400 mil)

'i

Vee

2

28
27

GND

1/01

1/08

1/01

10
2

28
27

1/02

3

26

1/07

1/02

3

26

1/07

1/03

4

25

1/06

1/03

4

25

1/06

1/04

5

WE

6

RAS

7

......
gOi

NC

8

UlCl

A10

Vee

1::1::

"D"D

GND
1/08

CC

24

1/05

1/04

5

1::1::

24

1/05

"''''
....
~C/l

23

CAS

WE

6

cc

23

CAS

Cl~

22
21

OE

7
8

....gg ....

22
21

OE

A9

RAS
NC

9

20

A8

A10

9

m..-

20

A8

AD

10

19

A7

AD

10

19

A7

A1

11

18

A6

A1

11

18

A6

A2

12

17

A5

12

17

A5

A3

13

16

A4

A2
A3

13

16

A4

Vee

14

15

GND

Vee

14

15

GND

~

UI

"D"D

~~
~C/l

~

~g

m

A9

I,

I

AD to A1D

Address Inputs

1/01 to 1/08: Data InputslOutputs

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE
Vee

Output Enable
Power Supply

GND

Ground

NC

No Connection

187

NEe

yPD42S17805,4217805

Block Diagram

Clock
Generator

Vee

0---

GND 0 - - -

CAS before
RAS Counter
~

"8
~

0

~
a::

co
...0

N

Memory
Cell
Array
2,048 x 1,024 x 8

1/01
to

1/08
Row
Address
Buffer
AO
to
A10
Column
Address
Buffer

188

NEe

yPD42S17805, 4217805

Input/Output Pin Functions
The IlPD42S17805, 4217805 have input pins RAS, CAS, WE, OE, AO to A 10 and input/output pins 1/01 to 1/08.

Pin name
RAS

Input/Output
Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS

Input

(Column address strobe)
AO to A10

CAS activates data input/output circuit.by latching column address

and

selecting a digit line connected with the sense amplifier.
Input

(Address inputs)

Address bus.
Input total 21-bit of address signal, upper 11-bit and lower 10-bit in sequence
(address multiplex method).
Therefore, one word is selected from 2,097,152-word by 8-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.

WE
(Write enable)

Input

OE
(Output enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.

If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
1/01 to 1108
(Data inputs/outputs)

Input/Output

8-bit data bus.
I/O 1 to 1/08 are used to input/output data.

189

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gPD42S17805,4217805

Hyper Page Mode
The hyper page mode is a kind of page mode with enhanced features. The two major features of the hyper
page mode are as follows.

1. Data output time is extended.
In the hyper page mode, the output data is held to the next CAS cycle's falling edge, instead of the rising edge.
For this reason, valid data output time in the hyper page mode is extended compared with the fast page mode
(= data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time

becomes shorter. Therefore, in the hyper page mode, the timing margin in read cycle is larger than that of the
fast page mode even if the CAS cycle time becomes shorter.

2, The CAS cycle time In the hyper page mode is shorter than that in the fast page mode.
In the hyper page mode, due to the data extend function, the CAS cycle time can be shorter than in the fast page
mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode, read (data out) and write (data in) cycles can be executed repeatedly during one RAS
cycle. The hyper page mode allows both read and write operations during one cycle, but the performance is
equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode read cycle. Specifications to be observed are described in
the next page.

Hyper Page Mode Read Cycle
V,HRAS VILtHPC

V,H- ---,,.--t----±___.
CAS

Address

Vll-

V,HVIL-

tCAC

WE

V,HVILtaCH
tOEA

OE

1/0

190

V,HVIL-

VOH-

Hi-Z

VOL- . - - - - - - - - - - - - - - - - - - - - - - - - - - - -

:1

_ _N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.l-Il_PD_4_2_S_1_7_BO_5......,_4_2_17_B_O_5_ _ _ _j

It.
:~

Cautions when using the hyper page mode
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

191

NEe

gPD42S17805,4217805

Electrical Specifications
All voltages are referenced to GND.
After power up (Vcc ? VCC(MIN.)), wait more than 100

JjS

(RAS, CAS inactive) and then, execute eight CAS before

RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter

Symbol

Rating

Unit

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Voltage on any pin relative to GND

Condition

Power dissipation

PD

1

W

Operating ambient temperature

TA

o to +70

°C

Storage temperature

Tstg

-55 to +125

°C

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
Parameter

Condition

MIN.

TYP.

MAX.

Unit

4.5

5.0

5.5

V

2.4

Vee + 1.0

V

-1.0

+0.8

V

70

°C

MAX.

Unit
pF

Vee

High level input voltage

V,H

Low level input voltage

VIL

Operating ambient temperature

TA

0

Capacitance (TA

= 25 °C, f = 1 MHz)

Parameter
Input capacitance

Data input/output capacitance

192

Symbol

Supply voltage

Symbol

Test Condition

MIN.

TYP.

CI1

Address

5

CI2

RAS, CAS, WE, OE

7

CliO

1/0

7

pF

I,

N~

~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~Jl_P_D....;..42_S;;;..,.1:....:.7..;:.8~05;;:..?,_4=2:....:.1..;....78::....;O:....:.5_ _ _~J

I,jt-

t

:I~

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter
Operating current

Standby

I'PD42S17805

Symbol
feel

lee2

current

Test Condition
RAS. CAS Cycling
tRe = tRe IMIN.,. 10 = 0 mA

RAS. CAS" V,H IMIN.I. 10

=0

RAS. CAS" V,H IMIN.I. 10

Operating current

lce3

IcC4

(Hyper page mode)

CAS before RAS

Ices

refresh current

CAS before RAS

ICG6

tRe

(2.048 cycles I 128 ms.

110

tRAe

= 70

ns

100

0.25

mA

Unit

Notes

mA

1.2.3

:1
l.'

mA

2.0

= 0 mA

CAS before RAS refresh:

long refresh current

ns

= 0 mA

RAS ,,; VIL IMAX.I. CAS Cycling
tHPe = tHPe IMIN.I. 10 = 0 mA

=0

= 60

= 0 mA

RAS Cycling. CAS" V,H IMIN.I
tRe = tRe IMIN.I. 10 = 0 mA

RAS Cycling
tRe = tRe IMIN.I • 10

tRAe

2.0

RAS. CAS" Vee - 0.2 V. 10
RAS only refresh current

MAX.

mA

RAS. CAS" Vee - 0.2 V. 10
I'PD4217805

MIN.

it

Ii

1.0

tRAe

= 60

ns

110

tRAe

= 70

ns

100

tRAe

= 60

ns

90

tRAe

= 70

ns

80

tRAe

= 60

ns

110

tRAe

= 70 ns

mA

1,2,3.4

mA

1.2.5

mA

1.2

100

tRAS"; 300 ns

400

)lA

1.2

tRAS ,,; 1 )lS

500

)lA

1.2

250

)lA

2

-10

+10

)lA

-10

+10

)lA

0.4

V

= 62.5 I's

RAS. CAS:
Vee - 0.2 V ,,; V,H ,,; V,H IMAX.I

only for the I'PD42S17805)

o V,,; VIL"; 0.2 V
Standby:

RAS. CAS " Vee -

0.2 V

Address: V,H or VIL
WE. OE: V,H
10

=0

mA

self refresh current

CAS:
tRASS = 5 ms

(only for the I'PD42S17805)

Vee - 0.2 V ,,; V,H ,,; V,H IMAX.'

CAS before RAS

lee7

RAS.

o V,; VIL"; 0.2 V
Input leakage current

Ii ILl

10

=0

V,

= 0 to

mA
5.5 V

All other pins not under test
Output leakage current

10lLI

Vo

= 0 to

=0 V

5.5 V

Output is disabled (Hi-Z)
High level output voltage
Low level output voltage

VOH
VOL

10

= -5.0

10

= +4.2

mA
mA

2.4

V

Notes 1. Icc1. Icc3, Icc4. Icc5 and Icc6 depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS S VIL(MAX.)
and CAS" V,H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.

5. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page cycle.

193

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yPD42S17805,4217805

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

VIH (MIN.)

= 2.4

V

VIL (MAX.)

=

0.8

V

(2) Output timing specification

---------------~

·--------3 [
,
,

",

'
'

:..

tT = 2 ns

[L
, ,

,

..:

VOH (MIN.)

= 2.4

VOL (MAX.)

=

t

0.4

V

------=J

"\ .

V------=-\-.____
..
--I+

,II

IT = 2 ns

(3) Output load condition
VCC
820Q

r

I/O---~--'"

100 pF
CL

290Q

Common to Read, Write, Read Modify Write Cycle
Parameter

tAAC = 60 ns

tAAC = 70 ns

MIN.

MAX.

MIN.

MAX.

124

ns

Unit Notes

Read I Write Cycle Time

tAC

104

RAS Precharge Time

tAP

40

CAS Precharge Time

tCPN

10

-

10

-

RAS Pulse Width

tRAS

60

10,000

70

10,000

ns

CAS Pulse Width

leAS

10

10,000

12

10,000

ns

RAS Hold Time

tASH

10

-

12

-

ns

CAS Hold Time

tCSH

40

-

50

-

ns

RAS to CAS Delay Time

tRCO

14

45

14

52

ns

RAS to Column Address Delay Time

tRAD

12

30

12

35

ns

2

CAS to RAS Precharge Time

tCAP

5

5

3

tASR

0

0

-

ns

Row Address Setup Time
Row Address Hold Time

tRAH

10

-

10

-

ns

Addr~ss

tAse

0

-

0

-

ns

Column Address Hold Time

tC~H

10

-

12

-

ns

OE Lead Time Referenced to RAS

tOES

0

0

tCLZ

0

OE to Data Setup Time

tOLZ

0

OE to Data Delay Time

tOED

13

15

-

ns

CAS to Data Setup Time

-

IT

1

50

1

50

ns

-

128

-

128

ms

32

ms

Column

Setup Time

Transition Time (Rise and Fall)
Refresh Time

I !,PD42S17805

I !,PD4217805
194

Symbol

tREF

32

50

0
0

ns
ns
1

2

ns

ns
ns
ns

4

NEe

yPD42S17805,4217805

Notes 1.

In CAS before RAS refresh cycles, tRAS(MAX.) is 100 /lS.

If 10 Jis < tRAS < 100 /lS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input Conditions

Access Time

s: tRCO (MAX.)

tRAQ::; tRAQ (MAX.)

and

tACO

tRAQ> tRAQ (MAX.)

and

tRCO ::; tRCO (MAX.)

tRCo> tACO (MAX.)

Access Time from RAS

tRAC (MAX.)

tRAG (MAX.)

tAA (MAX.)

tRAQ

+ tAA (MAX.)

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.

3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the JiPD42S 17805.

Read Cycle
Symbol

Parameter
Access Time from RAS
Access Time from CAS

tRAG

= 60 ns

tRAG

= 70 ns

Unit Notes

MIN.

MAX.

MIN.

MAX.

tRAG

-

60

ns

tCAC

15

tAA

30

-

70

-

35
0

18

ns

1

35

ns

1

18

ns

-

ns
ns

0

-

ns

2
3

Access Time from OE

tOEA

-

Column Address Lead Time Referenced to RAS

tAAl

30

Read Command Setup Time

tACS

0

Read Command Hold Time Referenced to RAS

tRRH

0

Read Command Hold Time Referenced to CAS

tACH

0

-

tOEZ

0

13

0

15

ns

tcHO

5

-

5

-

ns

Access Time from Column Address

Output Buffer Turn-off Delay Time from

DE

CAS Hold Time to OE

15

1

0

ns

2

Notes 1. For read cycles, access time is defined as follows:
Input Conditions

s: tACO (MAX,)

tRAQ:O::; tRAQ (MAX.)

and

tACO

tRAD> tRAQ (MAX.)

and

tACO::; tACO (t·.4AX.)

tRCO

>

tACO (MAX.)

Access Time

Access Time from RAS

tRAC (MAX.)

tRAC (MAX.)

tAA (MAX.)

tRAD

+

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

tAA (MAX,)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

195

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yPD42S17805,4217805

Write Cycle
Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.
10

-

ns

1

10

-

ns

1

12

-

ns

10

-

twp

10

tRWL

10

WE Lead Time Referenced to CAS

tCWL

10

WE Setup Time

twes

0

OE Hold Time

tOEH

0

-

WE Hold Time Referenced to CAS
WE Pulse Width
WE Lead Time Referenced to RAS

tWCH

Data-in Setup Time

tos

0

Data-in Hold Time

tOH

10

12
0
0
0
10

Unit Notes

MAX.

ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tweH (MIN.) should
be met.
2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter

Symbol

Read Modify Write Cycle Time

tRWC

tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

133

-

157

-

ns

89

-

ns

1

37

ns

1

54

-

ns

1

RAS to WE Delay Time

tRWD

77

CAS to WE Delay Time

tewD

32

Column Address to WE Delay Time

tAWD

47

Unit

Note

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

196

i
:,~

NEe
PD42S1
2 80 _ _ _~,.,'i
___
_~_ _ _ _ _ _ _ _ _ _ _ _ _ __I:..ll:..::.......=~..::.....:....7:....:8:..:0~5.z....,
~4:::...1:....:7--=...::.~5
Hyper Page Mode
tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

tHPC

25

-

30

-

ns

RAS Pulse Width

tRASP

60

125,000

70

125,000

ns

CAS Pulse Width

tHCAS

10

10,000

12

10,000

ns

tep

10

-

10

-

ns

Access Time from CAS Precharge

tACP

-

35

-

40

ns

CAS Precharge to WE Delay Time

tcPWD

52

-

59

-

ns

RAS Hold Time from CAS Precharge

tRHCP

35

-

40

ns

tHPAWC

66

-

75

-

tDHC

5

-

5

-

ns

tOCH

5

-

5

ns

Parameter
Read / Write Cycle Time

CAS Precharge Time

Read Modify Write Cycle Time
Data Output Hold Time

Symbol

Unit Notes
1

2

ns

OE Precharge Time

tOEP

5

-

5

-

Output Buffer Turn-off Delay from WE

tWEZ

a

13

a

15

ns

WE Pulse Width

twpz

10

-

10

-

ns

4

Output Buffer Turn-off Delay from RAS

tOFR

0

13

0

15

ns

3,4

Output Buffer Turn-off Delay from CAS

tOFC

a

13

0

15

ns

3,4

OE to

CAS Hold Time

4

ns
3,4

Notes 1. tHPC (MIN.) is applied to CAS access.
2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRWD ~ tRWD (MIN.), tCWD ~ leWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected call. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEl (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.

4. To make 1/05 to Hi-Z in read cycle, it is necessary to control RAS, CAS,WE, OE as follows. The effective
specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.

(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEl is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... tWEl and tWPl are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

197

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yPD42S17805,4217805

Refresh Cycle
Symbol

Parameter

tRAe = 60 ns

MAX.

5

-

ns

100

-

/IS

1

130

ns

1

-50

-

ns

1

10

-

ns

15

-

ns

5
10

-

10

RAS Precharge CAS Hold Time

tRPe

5

-

5

RAS Pulse Width (CAS before R.AS Self Refresh)

(CAS before RAS

Refresh)

Note

MIN.

tesR

CAS Hold Time

Unit

MAX.

tCHR

CAS Setup Time

tRASS

100

RAS Precharge Time (CAS before RAS Self Refresh)

tRPS

110

CAS Hold Time (CAS before RAS Self Refresh)

teHs

-50

WE Setup Time

twSR

10

WE Hold Time

twHR

15

Note 1. This specification is applied only to the ,uPD42S17805.

198

tRAe = 70 ns

MIN.

-

ns
ns

NEe

yPD42S17805,4217805

'.
!:J
i

Read Cycle

J

I~.'

tRC

RAS

ii'

tRP

IRAS

I,

I

V,KVILtCSH
tRCO

CAS

Address

WE

tRSH

tCPN

V,KVIL-

V,KVIL-

V,HVll-

OE

tCAC

toLZ
leLZ

I/O

VOKVOL-

Hi - Z

tOFR

Data out

199

NEe

gPD42S17805,4217805

Early Write Cycle

tAC
tRAS

RAS

tAP

V'HVIltCSH

CAS

Address

V'HVll-

VIHVIL-

V'HVIl- ---"1....l.....J.-l.......l..-lo....J.....l..~.l-~+_+_ _ _ _ _ _ _-4-.L....L-L-l.-'-''--''-''-'-t.-t.-t.-L.-L.............._

1/0

V'HVIl- .....,............-><...................."'-'''-''

Remark OE: Don't care

200

.1\-_ _ _ _ _ _ _ _ _- "

"-"-'''-'''-'''--><...J<.....l<................I<....l''-''-'''-''...........

NEe

,uPD42517805, 4217805

_ _ _ _ _ _ _...;;;;;:.-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...L..'--_ _ _ _ _ _ _-'-_ _ _ _ _ _ _ _ __ _ _

Ii

.-!~

i~

it

Late Write Cycle

Ii
tRC

il

tRAS

RAS

V,»VIL-

tCSH

Address

V,~
VIL-

OE

1/0

201

NEe

yPD42S17805,4217805

Read Modify Write Cycle

tRWC
tRAS

RAS

VIH-

VILtCSH
tRCO

tePN

tRSH

CAS

Address

V,HVIL-

tewD

WE

V,HVIL-

tOEA

OE

tOEH

V,HVIL-

tos

110

~---------

tOH

Data in
tOL2

1/0

202

VOlL........~

"-_ _ _ _ _J

Remark OE: Don't care

213

NEe

yPD42S17805,4217805

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)

Remark Address, OE: Don't care

1/0: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
x '16-bit organization during test mode. Don't care about the input levels of the CAS input AO.

(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the celi can be checked.
Output = "1": Normal write (all memory celis)
Output = "0": Abnormal write

(3) Refresh
Refresh in the test mode must be performed with the RAS I CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.

(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

214

Il

NEe

~

.uPD42517805, 4217805

------------------------------------------------------------~---------------~---------------------

Package Drawings

28PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

-+-i-------+------t-

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum materjal condition.

18.63 MAX.
1.075 MAX.
1.27 (T.P.)

INCHES
0.734 MAX.
0.043 MAX.
0.050 (T.P.)

D

0.42~g:g~

0.017±0.003

E
F
G

0.1 ±0.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400±0.004

ITEM
A

B
C

H

MILLIMETERS

0.8±0.2

0031~g:gg~

0.145~g:m

0.006±0.001

0.5±0.1

0020~g:gg~

N

0.21
0.10

0.009
0.004

P

3<>+]0

3 0_30
+70

K

M

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S28G5-50-7J03

215

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28 PIN PLASTIC SOJ (400 mil)

15

-+~---------~-----------T-

u

0

14

P28LE-400A 1

NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

216

ITEM

MILLIMETERS

INCHES

B

1S67~g~5

o 735~gg~~

C

10.16

OAOO

D

11.1S±0.2

0.440~ggg~

E

1.0S±0.15

0.043~ggg~

F

0.74

0.029

G

3.5±0.2

0.13S~ggg~

H

2.545±0.2

0.100±0.00S

I

0.8 MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

OAO±0.10

0.016~ggg~

N

0.12

0.005

P

9AO±0.20

0370~ggg~

Q

0.10

0.004

T

R 0.S5

R 0.033

U

020~g6~

0.008~ggg~

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Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the JLPD42S17805, 4217805.

Types of Surface Mount Device
JLPD42S17805G5,4217805G5

28-pin plastic TSOP (n) (400 mil)

JLPD42S17805LE,4217805LE

28-pin plastic SOJ (400 mil)

217

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[MEMO]

218

yPD42S17805,4217805

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DATA SHEET

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MOS INTEGRATED CIRCUIT

#PD42S18165,4218165

I!

j

1;[,

16 M-BIT DYNAMIC RAM
1 M-WORD BY 16-BIT, HYPER PAGE MODE (EDO),
BYTE READ/WRITE MODE

Description
The ,uPD42S18165, 4218165 are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional hyper page mode
(EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the ,uPD42S18165 can execute CAS before RAS self refresh.
The ,uPD42S18165, 4218165 are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ.

Features
Hyper page mode (EDO)
1,048,576 words by 16 bits organization
Single +5.0 V ± 10 % power supply
Power consumption

Part number

Access time

Active (MAX.)

(MAX.)

R/W cycle time
(MIN.)

Hyper page mode (EDO)
cycle time (MIN.)

.uPD42S18165-60, 4218165-60

880 mW

60 ns

104 ns

25 ns

.uPD42S18165-70, 4218165-70

825 mW

70 ns

124 ns

30 ns

The ,uPD42S18165 can execute CAS before RAS self refresh

Part number
.uPD42S18165

Refresh cycle
1,024 cycles/128 ms

Refresh

Power consumption at standby

CAS before RAS self refresh,
CAS before RAS refresh,

(MAX.)
1.4 mW
(CMOS level input)

RAS only refresh, Hidden refresh
.uPD4218165

1,024 cycles/16 ms

CAS before RAS refresh,
RAS only refresh,

5.5 mW
(CMOS level input)

Hidden refresh

The information in this document is subject to change without notice.
Document No. Ml 0560EJ7VODSUl

219

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yPD42S18165,4218165

Ordering Information

Part number

Access time

Package

(MAX.)

JlPD42St8165G5-60

60 ns

JlPD42S18165G5-70

70 ns

Refresh

50-pin plastic TSOP (II)

CAS before RAS self refresh

(400 mil)

CAS before RAS refresh
RAS only refresh
Hidden refresh

42-pin plastic SOJ
JlPD42S 18165LE-60

60 ns

JlPD42S 18165LE-70

70 ns

JlPD4218165G5-60

60 ns

JlPD4218165G5-70·

70 ns

JlPD4218165LE-60

60 ns

JlPD4218165LE-70

70 ns

(400 mil)

50-pin plastic TSOP (II)
(400 mil)

Hidden refresh
42-pin plastic SOJ

220

CAS before RAS refresh
RAS only refresh

(400 mil)

I

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yPD42S18165, 4218165

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Pin Configurations (Marking Side)

$
Ii"
,'I'

.~

42-pin Plastic SOJ (400 mil)

50-pin Plastic TSOP (II) (400 mil)

i$
1'1

Vee
1/01
1/02
1/03
1/04

Vee
1/05
1/06
1/07
1/08

NC

2
3
4
5
6
7
8
9
10
11

..,..,
CC
""
........

50
49
48
47
46
45
44
43
42
41
40

GND

Vee

1/016

1/01

1/015

1/02

1/014

1/03

1/013

1/04

GND

Vee

1/012

1/05

1/011

1/06

1/010

1/07

1/09

1/08

NC

NC
NC

NN

-0

"'en_
-'"
"'en
NC
NC
WE

RAS
NC
NC
AD
A1
A2
A3
Vee

15
16
17
18
19
20
21
22
23
24
25

elen
enel

'"

WE

36
35
34

NC
LCAS
UCAS

33
32
31
30
29
28
27
26

A9
A8
A7
A6
A5
A4
GND

OE

RAS
NC
NC
AD
A1
A2
A3
Vee

10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

..,..,
cc
""
........
NN

-0

"'en_
-",

en en
'en
m.

m

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

GND
1/016
1/015
1/014
1/013

GND
1/012

II:

1/011
1/010
1/09

NC
LCAS
UCAS
OE

A9
A8
A7
A6
A5
A4

GND

I

I.

AO to A9

Address Inputs
1/01 to 1/016 : Data Inputs/Outputs
Row Address Strobe
RAS
Column Address Strobe (upper)
UCAS
LCAS

Column Address Strobe (lower)

WE

Write Enable

OE

Output Enable
Power Supply

Vee

GND
NC

Ground
No Connection

221

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yPD42S18165,4218165

Block Diagram
RAS
LCAS
UCAS

Clock Generator

WE

Vee

0---

GND

0---

1/01
to
1108

CAS before
RAS Counter
Q;
"0
0

<.>
Q)

0
3

Memory
Cell
Array

0

II:

AO
to
A9

222

XO to X9
Column
Address
Buffer

YOto Y9

1/09

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yPD42S18165, 4218165

Input/Output Pin Functions
The IlPD42S18165, 4218165 have input pins RAS, CAsNote, WE, OE, AD to A9 and input/output pins 1/01 to

1/016.

Pin name
RAS

Input/Output
Input

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.

(Row address strobe)

It also selects the following function.
• CAS before RAS refresh

CAS

CAS activates data input/output circuit by latching column address and

(Column address strobe)

selecting a digit line connected with the sense amplifier.

AO to A9

Address bus.
Input total 20-bit of address signal, upper 10-bit and lower 10-bit in sequence

(Address inputs)

(address multiplex method).
Therefore, one word is selected from 1,048,576-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.

(Output enable)

Therefore, read operation cannot be executed.

1/01 to 1/016
(Data inputs/outputs)

Input/Output

16-bit data bus.
1/01 to 1/016 are used to input/output data.

Note CAS means UCAS and LCAS.

223

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yPD42518165,4218165

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the hyper
page mode (EDO) are as follows.

1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the fast
page mode if the timing margin is the same.
Taking a device whose tRAG is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle, but the
performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mcde (EDO) read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mode (EDO) Read Cycle
VIH-

RAS

CAS

VIl-

V,HVIl-

---.-+---h

Address V,HV,L-

WE

VIHVIL-

VIH-

OE V,L-

1/0 VOHVOL-

224

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f.lPD42S18165,4218165

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Cautions when using the hyper page mode (EDO)

I't

1. CAS access should be used to operate tHPC at the MIN. value.

i\~

2. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective

:l

specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.
3.

In read cycle, the effective specification depends on the state of CAS signal when controlling data output with
the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

225

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yPD42S18165,4218165

Electrical Specifications
CAS means UCAS and LCAS.
All voltages are referenced to GND.
After power up (Vcc

~

VCC(MIN.)), wait more than 100 JLs (RAS, CAS inactive) and then, execute eight CAS before

RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

Parameter

Symbol
Vr

Condition

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Po

1

W

Operating ambient temperature

TA

o to +70

"C

Storage temperature

Tstg

-55 to +125

"C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter

Condition

MIN.

TYP.

5.0

MAX.

Unit

Supply voltage

Vee

4.5

5.5

V

High level input voltage

V,H

2.4

Vee + 1.0

V

Low level input voltage

V,l

-1.0

+0.8

V

0

70

"C

MAX.

Unit
pF

Operating ambient temperature

Capacitance (TA

TA

=25 "C, f = 1 MHz)

Parameter
Input capacitance

Data input/output capacitance

226

Symbol

Test condition

Symbol

MIN.

TYP.

CI1

Address

5

C'2

RAS, CAS, WE, OE

7

ClIO

I/O

7

pF

___
N_E.....-..,;;C~_ _ _ _ _ _ _ _ _ _ _ _ _- -L:.Jl:.:. . P.: :.D. . :. 42~S=-1:. . :8:. . :.1.: :.65=. l,~4: .=2:. .:.1.: :.81. :. .:6:.:5=- _ _ _,~
DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Operating current

ICCl

.uPD42S18165

ICC2

= tRC IMIN.), 10 = 0 mA

RAS, CAS <: V,H IMIN.), 10

RAS, CAS <: V,H IMIN.), 10

Icc,

IcC4

(Hyper page mode (EDO))

CAS before RAS
refresh current

CAS before RAS

= 70 ns

150
2.0

Unit

Notes

mA

1,2,3

mA

0.25
2.0

= 0 mA

1.0
mA

1,2,3,4

mA

1,2,5

mA

1,2

350

.u A

1,2

400

.uA

1,2

250

.uA

2

-10

+10

.uA

Vo = 0 to 5.5 V
Output is disabled (Hi-Z)

-10

+10

.uA

2.4

tRAe

= 60 ns

160

tRAe

= 70 ns

150

RAS ,; VIL IMAX.), CAS cycling
=

tHPC (MIN.),

10 = 0 mA

tRAe

= 60 ns

110

tRAe

= 70 ns

100

tRAe

= 60 ns

160

tRAe

= 70 ns

RAS cycling
tRC

Icc,

tRAe

= 0 mA

= tRC IMIN.), 10 = 0 mA

tHPC

ICG5

160

RAS cycling, CAS <: V,H IMIN.)
tRC

Operating current

= 60 ns

= 0 mA

RAS, CAS <: Vec - 0.2 V, 10
RAS only refresh current

tRAe

= 0 mA

RAS, CAS <: Vcc - 0.2 V, 10
.uPD4218165

MAX.

RAS, CAS cycling
tRC

Standby
current

MIN.

Test condition

= tRC IMIN.), 10 = 0 mA

CAS before RAS refresh:

long refresh current

tRC

(1,024 cycles I 128 ms,

150

tRAS'; 300 ns

= 125.0 .us

RAS, CAS:
VCC - 0.2 V ,; VIH ,; V,H IMAX.)

only for the .uPD42S18165)

o V ,; V,l ,; 0.2 V
Standby:

tRAS

$

1 .us

RAS, CAS <: Vee - 0.2 V
Address: V,H or V,l
WE, OE: V,H

10 = 0 mA
CAS before RAS

Icc7

RAS, CAS:
tRASS = 5 ms
Vce - 0.2 V $ V,H $ V,H (MAX.)
o V ,; V,l ,; 0.2 V

self refresh current
(only for the .uPD42S18165)

10 = 0 mA
Input leakage current

It (L)

V,

= 0 to 5.5 V

All other pins not under test
Output leakage current

lOlL)

High level output voltage

VOH

10 = -2.5 mA

Low level output voltage

VOL

10 = +2.1 mA

=0 V

V
0.4

V

Notes 1, ICC1, Icc3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tHPC).
2, Specified values are obtained with outputs unloaded.

3. ICCl and Icc3 are measured assuming that address can be changed once or less during RAS ~ VIL (MAX.)
and CAS  tAAD (MAX.)

and

tAco $: tRCO (MAX.)

tAA (MAX.)

tAAD

+

tCAC (MAX.)

tRCD

+ tCAC (MAX.)

tRCO> tRCD (MAX.)

tAA (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tM or tCAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD
(MAX.) will not cause any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the JlPD42S18165.
Read Cycle

tRAG
Parameter

= 60 ns

tRAG = 70 ns
Unit Notes

Symbol

Access time from RAS

tRAC

Access time from CAS

tcAC

Access time from column address

tAA

MIN.

MAX.

MIN.

MAX.
70

ns

18

ns

1

35

ns

1

18

ns
ns

-

60

-

15
30
15

35

Access time from OE

tOEA

Column address lead time referenced to RAS

tRAL

30

-

0

0

-

Read command setup time

tRGS

0

Read command hold time referenced to RAS

tRRH

0

Read command hold time referenced to CAS

tRCH

0

-

Output buffer turn-off delay time from OE

tOEZ

0

13

0

CAS hold time to OE

tcHO

5

-

5

0

1

ns
ns

2

ns

2

15

ns

3

-

ns

Notes 1. For read cycles, access time is defined as follows:

Input conditions

Access time

Access time from RAS

tRAD $; tRAD (MAX.)

and

tACO

:5

tRCD (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.)

and

tACO

:5

tRCD (MAX.)

tAA (MAX.)

tRAD

+ tAA (MAX.)

tcAC (MAX.)

tACO

+ tcAC (MAX.)

tRCO> tACO (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating
parameters. They are used to determine which access time (tRAC, tM or !cAC) is to be used for finding
out when output data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD
(MAX.) will not cause any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH
or VOL.

229

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yPD42S18165,4218165

Write Cycle

tRAC = 60 ns
Parameter

Symbol

tRAC = 70 ns
Unit

Notes

-

ns

1

-

ns

1

12

-

ns
ns

ns

3

ns

3

MIN.

MAX.

MIN.

MAX.

10
10

tWCH

10

WE pulse width

twp

10

-

WE lead time referenced to RAS

tRwL

10

-

WE lead time referenced to CAS

tCWl

10

twcs

0

-

12

WE setup time
OE hold time

tOEH

0

-

0

Data-in setup time

tDS

0

-

0

-

Data-in hold time

tDH

10

-

10

-

WE hold time referenced to CAS

0

ns

2

ns

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs ;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
tRAC
Parameter

= 60 ns

tRAC = 70 ns
Unit

Symbol
MIN.

MAX.

MIN.

MAX.

157

-

ns

Read modify write cycle time

tRWC

133

-

Note

RAS to WE delay time

tRWD

77

-

89

-

ns

1

CAS to WE delay time

tCWD

32

-

37

-

ns

1

Column address to WE delay time

tAWD

47

-

54

-

ns

1

Note 1. If twcs ;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRWD ;:: tRWD (MIN.), tCWD ;:: tCWD (MIN.), tAWD;:: tAWD (MIN.) and tCPWD ;:: tCPWD (MIN.), the cycle is a read
modify write cycle and the data out will contain data read from the selected cell. If neither of the above
conditions is met, the state of the data out is indeterminate.

230

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yPD42S18165,4218165

Hyper Page Mode (EDO)

Parameter

Symbol

tRAG = 60 ns

tRAG = 70 ns

MIN.

MAX.

MIN.

MAX.

-

30

-

Unit Notes

Read / Write cycle time

tHPC

25

ns

RAS pulse width

tRASP

60

25,000

70

125,000

ns

CAS pulse width

tHCAS

10

10,000

12

10,000

ns

tep

10

-

10

-

ns

Access time from CAS precharge

tAGP

-

35

-

40

ns

CAS precharge to WE delay time

tCPWD

52

59

RAS hold time from CAS precharge

tRHCP

35

CAS precharge time

1

OE precharge time

tOEP

5

-

5

-

Output buffer turn-off delay from WE

tWEZ

0

13

0

15

ns

WE pulse width

twpz

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFG

0

13

0

15

ns

3,4

Read modify write cycle time

tHPRWC

66

Data output hold time

tOHC

5

OE to CAS hold time

tacH

5

40
75
5
5

ns

2

ns
ns
ns
ns

4

ns
3,4

Notes 1. tHPC (MIN.) is applied to CAS access.

2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle. If tRWD

~

tRWD (MIN.), tCWD

~

tCWD (MIN.), tAWD

~

tAWD (MIN.) and tCPWD

~

tCPWD (MIN.), the cycle is a read

modify write cycle and the data out will contain data read from the selected cell. If neither of the above
conditions is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and
is not referenced to VOH or VOL.
4. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective

specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... tWEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

231

NEe

gPD42S18165,4218165

Refresh Cycle
tRAe
Parameter

Symbol

= 60

MAX.

tRAe = 70 ns

ns

1

-50

-

ns

1

15

-

ns

tCSR

5

-

5

tCHR

10

-

10

RAS precharge CAS hold time

tRPe

5

-

5

tRASS

100

tRPS

110

CAS hold time (CAS before RAS self refresh)

teHs

-50

WE hold time

tWHR

15

Note 1. This specification is applied only to the ,uPD42S18165.

Note

MAX.

CAS hold time (CAS before RAS refresh)

RAS precharge time (CAS before RAS self refresh)

Unit

MIN.

CAS setup time

RAS pulse width (CAS before RAS self refresh)

232

ns

MIN.

100
130

ns
ns
ns
/1S

1

NEe

yPD42S18165, 4218165

Read Cycle
tRC
tRP

tRAS

RAS

V,HVIltCSH

UCAS
LCAS

V,HVIl-

Address

V,HVIl-

WE

V,HVIl-

OE

V,HVIl-

tOLZ
tOFR

leLZ

U 1/0

Lila

VOH- . _________________________ ~!: _~
voL-

________________________________ _

Data out

Hi - Z

233

NEe

yPD42S18165,4218165

Upper Byte Read Cycle
tRe
tRAS
RAS

tRP

V,HVIllesH
tRCO

tRSH

lCAS
UCAS

V,HVIl-

tMRH

LCAS

V,HVIltRAL

Address

V,HVIl-

WE

V,HVIl-

locH
tOES

tOEA

OE

UI/O

Remark L 110: Hi-Z

234

Ii

____~~~E~c:=___________________________~g_P_D_4_2S~18_1_6_5~,4_2_1_8_16_5________,~
11('

Lower Byte Read Cycle
IRe
IRP

tRAS

RAS

tCRP

UCAS

LCAS

Address

WE

OE

VIHVIL-

~~~~+-~~~

V,HVIL-

loLZ

tOFR

leLZ

Lila

VOH-

VQL-

Hi-Z

Dala oul

Hi-Z

Remark U 1/0: Hi-Z

235

NEe

yPD42S18165,4218165

Early Write Cycle
tRC

tRAS

tCSH

Remark OE: Don't care

236

I~

,':,

NEe
PD42S
8 65 4218165
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'-y_
__
1_1_"-,
_ _ _ _ _-:'~I;i
Upper Byte Early Write Cycle
tRC
tRAS

RAS

tRP

V,HVILtCSH

VIH-

UCAS

VIL-

LCAS

Address

WE

V,HVIL-

VIHVIL-

U 1/0

Remark OE, L 1/0: Don't care

237

NEe

yPD42S18165,4218165

lower Byte Early Write Cycle
tRC
tRAS

tRP

RAS

VIH-

Vll-

Address

V,H-

........'I-''--':.......-L...L............L....L...t.....L-L-.............'--'-I.-L...L.................L....L.-<-

V,L- -''--''--'..........l.....l.~-l-....),........~-I_-+

L110

Remark OE, U 110:

238

DC'~'t

care

f

i~

NEe
yPD42S18165, 4218165
l~
-----.:......::....:::::...:::=------------------..L---~----'--------_il~
.~

'I

I:;

:1

Late Write Cycle

!~

i:j

I,

tRC
tRAS

.'

V,HV,L-

UCAS
LCAS

Address

V,HVIL-

VIH-

VIL-

WE

V,HV,L-

OE

VIHV,L-

UI/O
L110

V,HV,LI

I.

239

NEe

yPD42S18165,4218165

Upper Byte Late Write Cycle
tAC
tAAS

RAS

tAP

V,HVIltasH
tRCD

tASH

teAS

UCAS

V,HVIL-

LCAS

Address

OE

tOH

UI/O

YXf)-------~~:-~-------

Remark L I/O: Don't care

240

Data in

II.,

NEe

it

yPD42S18165, 4218165

-~------'---~-----ii~

J
#

Lower Byte Late Write Cycle

1&3

i
tAC

tRAS

RAS

tRP

i'
.1

V1HVIL-

tMAH

UCAS

V,HVILtcSH
tASH

LCAS

tCAS

VIH-

VIL-

Address

WE

OE

VIH-

VIL - L-t-'-<:.....J:.....t:-t..-t.....LJ
tOH

LIIO

'llf)--------~i:-~-------

Data in

Remark L 110: Don't care

241

NEe

yPD42S18165,4218165

Read Modify Write Cycle
tRWC

tRAS

RAS

V,HVILtCSH

tRCo

UCAS
LCAS

tASH

V,HVIL-

tOEH

tos

tDH

Data in

Hi-Z

242

!$

Ii
___I\I_E_C.=;;...._ _ _ _ _ _ _ _ _ _ _ _ _ _--LJ1~P_D_4.:....2..;;;S...,;,1_=_8~16:...:5~,_4_2_18.;;...1......;6...,;,5_ _ _ _ c~

i!
Upper Byte Read Modify Write Cycle
tRWC
tRP

tAAS

RAS

V,HVIL-

tCSH
tACO

tRSH
tCAS

UCAS

VIH-

VIL-

LCAS

V,HVIL-

Address

V,HVIL-

WE

VIL-

OE

U 1/0

U 1/0

Remark

VIH-

VIHVIL-

VIHVIL-

~-------------------

VOH- ........... _.. _............
Hi - Z_................... ..
VOL-

Hi-Z

In this cycle, the input data to Lower I/O is ineffective. The data out of that remains Hi-Z.

243

NEe

yPD42S18165,4218165

Lower Byte Read Modify Write Cycle

tRP

Address

WE

VIHVIL-

VIHVll-

OE

V,HVIL-

LIIO

VOHHi· Z
........ -_ .... -_ .. -- -_ .. -- ............
- .. - .. _.................. -_ ..
VOL-

Remark

244

l:ttlitI)-.................. .

L 1/0

Hi -Z

In this cycle, the input data to Upper 1/0 is ineffective. The data out of that remains Hi-Z.

ii

___N~E=-C-=-_ _ _ _ _ _ _ _ _ _ _ _ _ _~J1~P;..,.;D=-4...;,.;2;;;...;S;....;1;...;;:8...:..1..:...65=..!,_4;.,;;;2...:..1..; ;.8. ;. . 16: . . :;5:. .- _ _--1 1
1

i~
i~

Hyper Page Mode (EOO) Read Cycle
tRASP

RAS

~

V,ltCSH

UCAS
LCAS

IRP

~

tRHCP

VIH-

VIH-

V,l-

~

tACO

~
~

tHCAS

~

.--I

tRSH

tHPC

tHCAS

~

y'-'

VI

V,HV,l-

WE

V,HV,l-

~~
Row

-'

tAAL

tRAD

Address

~

tHCAS

~

>9

Col.

~~

mJl

Col.

~

~
Col.

I~

tOFA

XX X
~
~

III/I}

'---

IOFC

RRH

~

'\

JlI
tWEZ

VIH-

OE

V,l-

\\\\\\\\\\~

tACP

~~

tACP

lAA

IAA

tCAC

tcAC

I

\\\\

tRAG

IAA

~

teAC

~
U I/O
L I/O

VOHVOl-

~

Hi-Z
----------------------------

~

Dala oul

~

--0

Dalaoul

tOEZ

--0

Dala oul

---

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

245

NEe

yPD42S18165,4218165

Hyper Page Mode (EDO) Byte Read Cycle

~

tAASP
tRHCP

V,HRAS
VIltHPC

tCSH

~

UCAS

LCAS

Address

WE

OE

V,HVIl-

V,HVIl-

V,HVIl-

V,HV,L-

tRCD

~

tHCAS

Y

1'\

~

'-

tRSH

tHCAS

~

tHCAS

~

.~ ~

~

~~

tOFR

~
~

~~

'\J

~::= \ \ \ \ \\\ \ \ \ \ \~
tRAC
tM

tCAC

--

~

Col.

t~LJ
/////If
1

'-

J
tMRH

tRAL

Row

l~

lAcp

tACP

tAA

tAA

tCAC

!WEZ-r

~~

J

\\\

~
tDHC
tOEZ

+-+

~

U1/0 ~~:= -------------~i---:---------_1~'__D_at_a_o_ut_04_~-.---_+---+---_-_-_-_--_--+--_--_-_-~-{J'_A.__D_at_a_o_u_t-...J] --

-

tDHC

VOH-

L I/O VOL-

----------------~~:?-------------------------- ~1\__D_at_a_o_ut_II__-_-_--_-_-_-_--_-_-_-_--_-_-_-_--_...J]-~--

Remark 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

246

___N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _ _--'-Jl_P_D_4_2_S_1S_1_6_S......
, 4_2_1_S_16_S_ _ _ _:t
I,
i.~

Hyper Page Mode CEDO) Read Cycle (WE Control)

II
tRASP

I.t

tRHCP

RAS

\
tCSH

UCAS
LCAS

V,HV,l-

Address

V,HV,l-

WE

V,HV,l-

OE

V,l-

VIH-

I.
U 1/0
LIIO

VOHVOl-

.........

-_

-Z
........................... Hi...................................

-_

_-

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

247

NEe

yPD42S18165,4218165

Hyper Page Mode (EDO) Read Cycle (OE Control)

~

RASP

RAS V,HVIl-

~

tRHCP

leSH

UCAS V,HLCAS VIl-

Address

~

-'

tRCO

~

~

tHCAS

..----

/

~

~

/

::i
)()O( X)

tRAL

~

Row

mX

~
Col.A

~

m)

~~
Col.B

~

.-

~
Col.C

10FR

tRAC
tRCH

IAA

IAA

11l11!

lOCH

....

tOEA

~

/

~
~
VOHHi-Z
L 1/0 VOL- -------------------------

Ir----.

~

~

tOES

tacH

tCHO

\\\\\\\\\\\

I"'c-+-'

~

~

~

U 1/0

~

tHCAS

1\\

IR~

WE

P
Ir----!

tHCAS

'-

tRSH

tHPC

lAep

CAe
IAA

r-fo-

Data out A ----

\\\\

tCHO
tACP

'L r-- ~ 'to!
le~

fo-H tRRH

~
~

~

~

~

Ir-->

/
OEA

\\\\

Iolz
tOEZ

~

~ Data out 8}---~~ Data out 81)-- ~ DataoutC

_JU'_

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

248

~_E

_____ __c:____________________________

~y_P_D_4_2S_1_8_1_6~5,~4_2_1_8_16_5______~!1
I~

,

I~

Hyper Page Mode (EDO) Early Write Cycle

I!

1&.

RAS

UCAS
LeAS

Address

UI/O
LIIO

VIH-

VIl-

"""'r-7I:rt"'"7\ Jr-------.J
L..>t........"-"'-"-'"

Remarks 1. OE: Don't care

2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

249

NEe

gPD42S18165,4218165

Hyper Page Mode (EOO) Byte Early Write Cycle
tRASP
tRHCP

tHPC

~'ltHCASJ~

Address

tRSH
tHCAS

tHCAS

tMRH

VIH-

VIL-

U 1/0 V,HVIL-

L 1/0 V,HVIL-

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

250

___
N_E_C_ _ _ _ _ _ _ _ _ _ _ _ _ _--L..J1_P_D_4_2S_1_8_1_6--'S,:.....4_2_1_8_16_S_ _ _- Il'fi
!ti
'I

Hyper Page Mode (EDO) Late Write Cycle

RAS

Address

WE

OE

V,HVIL-

VIHVIL-

U 110

LIIO

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

251

NEe

yPD42S18165,42181~5

Hyper Page Mode (EDO) Byte Late Write Cycle
IRAse
tRHCP

VIHVIL-

lesH
tHCAS

IRSH
tHeAs

VIHVIL-

IMRH

Address

VIHVIL-

VIHVIL-

OE

VIHVIL- L....J[....L....L...L-J

U 1/0

VIHVIL-

L 1/0

VIH-

______ t!i:_~

________ _

VIL-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

252

I~
1,1

_ _N;,....;;..;E=C-=-_ _ _ _ _ _ _ _ _ _ _ _ _--..r::.I1;,;..P..:::..D...:,;42::..;S::..,;1:....::8....:...16::..:5:..z.,....,:4..:::..2..::...;18::....:1:....::6..:::..5_ _ _,i
::,1:

:\

Hyper Page Mode (EDO) Read Modify Write Cycle
tRASP

tRP

RAS

UCAS
LCAS

,i

VIHVIL_

~

,1
'~

Address

VIH-

!

VIL-

WE

OE

UI/O
LIIO

UI/O
LIIO

VIHVIL-

VOHVOL-

V'HVll-

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

253

'I

NEe

,uPD42S18165,4218165

Hyper Page Mode (EDO) Byte Read Modify Write Cycle
IRASP

tHPRWC

IHCAS

IHCAS

VI~ ---r~+-----~~r---------~.r--~----------------~r------------+~~~rV,L-

LeAS

V,HV,LtRAL

Address

V,HV,L-

V,H-

-'-r-r-t--rlF*=t--i=====~

V,L- '-''-'-I...,.....J

V,HV,L-

-->................................"-i"-t--t'

-- Hi-Z
................... -_ .......... .

U 1/0 VOH-

L 1/0 VO~
VOLVI~

U 1/0 V,L-

L 1/0 V,HV,L-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LeAS simultaneously, or at random.

254

j,j

il
P ;;;;.,D4..:.,:2::...::S;...:,1..::...81..:....:6:...::5..!...,4...:..:2::....:1~8-=-16::....:5:...__ _ _ 1!
_ _N--.,;;E;;;;.,C=-_ _ _ _ _ _ _ _ _ _ _ _ _..c.fL.:.....
i

Hyper Page Mode (EDO) Read and Write Cycle
IAASP

RAS

\1

tRHCP

V,H-

1

V,L-

'!

ICSH

UCAS
LCAS

il

V,H-

l

VIL-

i
Address

II,

V,HV,L-

"

WE

OE

U I/O
L I/O

/ V,HV,L-

V,H- -................""T'""'T'".........-.(-.......~

V,L- .....................................,..........,.,...,.......,..-+--t-t---+---+....,~T"""........-h..............'O"";.....,..........................................

VOHHi - Z
VQL- --------------------------------

_.......

los

Hi-Z
_._._.... _. _. ---- _._,

toH

UI/O
LlIO

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

255

NEe

yPD42S18165, 4218165

CAS Before RAS Self Refresh Cycle (Only for the ,uPD42S18165)

tRASS

RAS

UCAS
LeAS
Remark Address, WE, OE: Don't care

L 1/0, U 1/0: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS before
RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with long RAS only
refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 1,024 times within a 16 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 1,024 times within a 16 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS(MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 ,us), CAS before
RAS refresh cycles will be executed one time.
If 10 ,us < tRAS < 100 ,us, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (1,024/128 ms) should be met.
For details, please refer to How to use DRAM User's Manual.

256

1:1:

I':'

____~
__E_c:
____________________________~y_P_D_42_S_1_8_16_5~,_4_21_8_1_6_5______~,f
..~
I

~

i:i.,.

CAS Before RAS Refresh Cycle

I'll

~~
IRC

I
i~

IRC

!

tcSR

UCAS
LCAS

tCHR

V,HVIl-

Remark Address, WE, OE: Don't care

L 1/0, U 1/0: Hi-Z

RAS Only Refresh Cycle
IRC
tRAS

RAS

IRP

tRAS

V,HVIl-

tCRP

UCAS V,HLCAS VIl-

Address

Remark WE, OE: Don't care

L 1/0, U 1/0: Hi-Z

257

NEe

yPD42518165,4218165

Hidden Refresh Cycle (Read)
tRC
tRAS

tRC
tRAS

UCAS V,HLCAS VIL-

Address

WE

OE V,HVIL-

U I/O VOH- ........................
L I/O VOL-

258

Hi -z -- _............ -_ ............... -_ ... ...
-- _............ -_ ........................

Data out

Hi - Z

!;

!

_ _...:...N..::..E-=-.;C=-_ _ _ _ _ _ _ _ _ _ _ _ _---'-Il_P_D_4_2_S_18_1_6_S.:.....,4_2_1_8_1_6S_ _ _ _

I
,'

:f,
'l
I

':,\

Hidden Refresh Cycle (Write)

!~
IRC

IRC

tRAS

RAS

il

tRAS

i

VIH-

VIL-

tcRP

UCAS
LCAS

VIH-

VIL-

Address

V,HV,L-

WE

V,HVIL-

twcs

U 1/0
L 1/0

tWGH

V,HV,L- L....J'-"'-><-""-"-..l<..""-"-'''-''' '--_ _ _ _-'

Remark OE: Don't care

259

NEe

yPD42S18165,4218165

Package Drawings

50PIN PLASTIC TSOP(II) (400 mil)
50

26
detail of lead end

-1---1-------+------t-

H

°l}

I:r
~~VL\

J

I\\J

--WL

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A

21.17MAX.

0.834 MAX.

B

1.0 MAX.

0.040 MAX.

C

0.8 (T.P.)

0.031 (T.P.)

D

0.32:':8:8~

0.013±0.003

E

0.1±0.05

0.004±0.002

F
G

1.2 MAX.

0.048 MAX.

0.97

0.038

H

11.76±0.2

0.463±0.008

K

10.16±0.1

0.400±0.004

0.8±0.2

0.031:':8:88~

0.145:':8:m

0.006±0.001

0.5±0.1

0.020:8:88~

M

0.13

0.005

N

0.10

0.004

P

3°+ 7 -3-

3-+7"
-3S50G5-80-7JF4

260

.~

_ _N_E_C_ _ _ _ _ _ _ _ _ _ _ _ _ _---'-f.1_P_D_42_S_1_B_1_65--','--4_2_1_B_16_5_ _ _ _.11
'"

I '~

I'll

!

42 PIN PLASTIC SOJ (400 mil)

!

Ii
l

If

()

0

21

E

F

I-

10 1 Q

P42LE-400A
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

ITEM

MILLIMETERS

INCHES

B

27 .56~g:~5

1.085~g:g9~

C

10.16

0.400

D

11.18±0.2

0.440±0.008

E

1.08±0.15

0.043~ggg~

F

0.74

0.029

G

3.5±0.2

0.138±0.008

H

2.545±0.2

0.100±0.008

I

0.8 MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

0.40±0.10

0.016~ggg~

N

0.12

0.005

P

9.4±0.20

0.370±0.008

Q

0.10

0.004

T

R 0.85

R 0.033

U

0.20~g:6g

0.008~g:ggi

261

NEe

yPD42S18165,4218165

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the /lPD42S18165. 4218165.

Types of Surface Mount Device
/lPD42S1816SGS:.421816SG5: SO-pin plastic TSOP (II) (400 mil)
/lPD42S1816SLE,421816SLE: 42-pin plastic SOJ (400 mil)

262

Hyper Page Mode (EDO)
16M Dynamic RAM
[3.3V + O.3V]

263

I,

I~

DATA SHEET

!

,I
;--------------------------------~)

NEe

MOS INTEGRATED CIRCUIT

"PD42S16405L, 4216405L

:~

---------------fA'------------------------------------!f
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, HYPER PAGE MODE (EDO)
i~

--------------,i
!

Description

i

The .uPD42S16405L, 4216405L are 4,194,304words by 4 bits CMOS dynamic RAM with optional hyper page mode
(EDO).

11

Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the .uPD42S16405L can execute CAS before RAS self refresh.
The .uPD42S16405L, 4216405L are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ.

Features
Hyper page mode (EDO)
4,194,304 words by 4 bits organization
Single +3.3 V ±0.3 V power supply
Power
Part number

consumption

R/W cycle time
(MIN.)

Hyper page mode (EDO)

(MAX.)

Access time

Active (MAX.)

cycle time (MIN.)

JiPD42S 1640SL-A60, 421640SL-A60

324 mW

60 ns

104 ns

2S ns

JiPD42S1640SL-A70, 421640SL-A70

288 mW

70 ns

124 ns

30 ns

.uPD42S16405L can execute CAS before RAS self refresh

Part number
JiPD42S1640SL

Refresh cycle
4,096 cycles/128 ms

Refresh
CAS before RAS self refresh
CAS before RAS refresh

Power consumption
at standby (MAX.)
0.S4 mW
(CMOS level input)

RAS only refresh
Hidden refresh
JiPD421640SL

4,096 cycles/64 ms

CAS before RAS refresh
RAS only refresh

1.8mW
(CMOS level input)

Hidden refresh

The information in this document is subject to change without notice.
Document No. M10174EJ3VODSU1

265

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~PD42S16405L,4216405L

Ordering Information

Part number

Access time
(MAX.)

Package

Refresh

/lPD42S16405LG3-A60

60 ns

26-pin plastic TSOP (II)

CAS before RAS self refresh

/lPD42S16405LG3-A70

70 ns

(300 mil)

CAS before RAS refresh

/lPD42S 16405LLA-A60

60 ns

26-pin plastic SOJ

/lPD42S16405LLA-A70

70 ns

(300 mil)

/lPD4216405LG3-A60

60 ns

/lPD4216405LG3-A70

70 ns

26-pin plastic TSOP (II)
(300 mil)

/lPD4216405LLA-A60

60 ns

26-pin plastic SOJ

/lPD4216405LLA-A70

70 ns

(300 mil)

RAS only refresh

266

Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

,'~;

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f

~PD42S16405L,4216405L

I

'f

Pin Configurations (Marking Side)

Ii

26-pin Plastic TSOP (II) (300 mil)

~~

26-pin Plastic SOJ (300 mil)

:f
"

26

Vee
1/01

2

1/02

3

WE

4

GND

Vee

1/04

1/01

10
2

1/03

1/02

3

CAS

1::1::
"ll"ll

cc
........

4

DE

RAS

5

A9

A11

6

AS

A10

S

A7

AD
A1

9
10

26

GND

cc
........

A11

6

-III

A10

.... ....
C)
wC)

AD

S
9

A1

10

A6

A2

11

A5

A2

11

AS

A3

12

A4

A3

12

A4

Vee

13

Vee

13

AO to A11

"''''

21

'"
w

14

GND

-III
"''''."
.,,....
0 ....
"'0

....
....

,~

~

CAS

5

g~

i

1/03
1::1::
"ll"ll

RAS

~-

:J!'

1/04

~

if

OE

21

'"

.~

A9

i

'.~

....

AS

> ....

:r-

A7
A6

14

GND

Address Inputs

1/01 to 1/04: Data Inputs/Outputs
RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

267

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~PD42S16405L,4216405L

Block Diagram

RAS
Clock
Generator

CAS
WE

Data
Output
Buffer

Vee

0--

GNDo--

CAS before
RAS Counter
ij;

u

0
0

<0

0

0

'" '".;

Memory
Cell
Array

~

0

0:

4,096 x 1,024 x 4

1/01
to

1/04
Row
Address
Buffer
AO
to
A11
Column
Address
Buffer

268

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,uPD42S16405L, 4216405L

:.1

------------~------------------------------------~------------~------------------~i~

Input/Output Pin Functions
The pPD42S16405L, 4216405L have input pins RAS, CAS, WE, OE, AO to A 11 and input/output pins 1/01 to
1/04.

Pin name
RAS

Input/Output
Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS

Input

CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.

Input

Address bus.
Input total 22-biI of address signal, upper 12-bit and lower 1D-bit in sequence

(Column address strobe)
AD to All
(Address inputs)

(address multiplex method).
Therefore, one word is selected from 4,194,3D4-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (IASA, lAse) and hold time (tAAH, teAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and DE.

(Output enable)

If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/04
(Data inputs/outputs)

Input/Output

4-bit data bus.

1/01 to 1/04 are used to input/output data.

269

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#PD42S16405L,4216405L

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.

1. Oata output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time in the hyper page mode CEOO) Is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle.

The hyper page mode (EDO) allows both read and write operations during one cycle, but the

performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mode CEOO) Read Cycle
RAS

~::~
tHpe

V,HCAS

VIl-

Address

V,HVIl-

--,-+----+......

teAe
WE

VIH-

VIltoeH
tOEA

OE

V,HVIL-

teez
1/0

270

VOHVOL-

Hi-Z

.- ---------------------------

!1

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_ _...;..N..;;;..E.=...;;C~_ _ _ _ _ _ _ _ _ _ _ _.....;J1:......P_D_4_2_S_16_4_0_5_L:;....'4_2_1_64_0_5_L_ _

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,\

Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active

~

:1

;

tOFC is effective when RAS is inactivated before CAS is inactivated.
W
T

tOFR is effective when CAS is inactivated before RAS is inactivated.

,i

(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.

:.

(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.

,:.1"
"

3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.

,~'
II;'

(2) CAS, OE: active ..... tOCH is effective.

271

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~PD42S16405L,4216405L

Electrical Specifications
All voltages are referenced to GND.
After power up (Vcc <: VCC(MIN.)), wait more than 100 /1S (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Symbol

Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

mA

Power dissipation

PD

1

W

Operating ambient temperature

T.

o to +70

"C

TSlg

-55 to +125

"C

Storage temperature

Caution

Condition

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

3.0

3.3

3.6

V

High level input voltage

V,H

2.0

Vee + 0.3

V

Low level input voltage

VIL

-0.3

+0.8

V

Operating ambient temperature

T.

0

70

"C

Parameter

Capacitance (TA = 25

Symbol

'c, f =1 MHz)

Parameter
Input capacitance

Data input/output capacitance

272

Condition

MAX.

Unit

Cil

Address

5

pF

C'2

RAS. CAS. WE. OE

7

CliO

I/O

7

Symbol

Test condition

MIN.

TYP.

pF

l~

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;1

,uPD42S16405L,4216405L

------~--------------------~~------~--------~~

~

~

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Operating current

Standby

/lPD42S16405L

leCI

ICC2

current
/lPD4216405L

RAS only refresh current

Operating current

ICC3

leC4

lee5

CAS before RAS

=0

mA

RAS, CAS" Vee - 0.2 V, 10

=0

=0

mA

RAS, CAS" Vee - 0.2 V, 10

=0

RAS, CAS" V,H (MIN.), 10

lee6

MAX.

Unit

Notes

mA

1,2,3

tRAe

= 60

ns

80

tRAe

= 70

ns

70
0.5

mA

0.15

mA

0.5

tRAe

= 60

ns

80

tRAe

= 70

ns

70

RAS ,; VIL (MAX.), CAS cycling
tHPe = tHPe (MIN.), 10 = 0 mA

tRAe

= 60

ns

90

tRAe

= 70

ns

80

tRAe

= 60

ns

80

tRAe

= 70

ns

70

RAS cycling
= tRe (MIN.),

10

=0

mA

tRe

(4,096 cycles / 128 ms,

= 31.3

It

mA

mA

1,2,3,4

mA

1,2,5

mA

1,2

220

/lA

1,2

150

/lA

2

-5

+5

/lA

-5

+5

/lA

tRAS'; 1 /lS

CAS before RAS refresh:

long refresh current

.tS

2.0

RAS cycling, CAS" V,H (MIN.)
tRe = tRe (MIN.), 10 = 0 mA

tRe

refresh current

MIN.

RAS, CAS cycling
tRe = tRC (MIN.), 10 = 0 mA

RAS, CAS" V,H (MIN.), 10

(Hyper page mode (EDO»
CAS before RAS

Test condition

/ls

RAS, CAS:

only for the /lPD42S16405L)

Vee - 0.2 V " V,H ,; V,H (MAX.)
o V,; VIL'; 0.2 V
Standby:
RAS, CAS" Vee - 0.2 V
Address: V,H or VIL
WE,OE: V,H
10

CAS before RAS

lee7

=0

mA

RAS, CAS:

5 ms

self refresh current

tRASS

(only for the /lPD42S16405L)

Vee - 0.2 V ,; V,H ,; V,H (MAX.)

=

o V,; VIL'; 0.2 V

Input leakage current

Ii (l)

10

=0

V,

= 0 to

mA
3.6 V

All other pins not under test
Output leakage current

10(l)

Va

= 0 to

=0

V

3.6 V

Output is disabled (Hi-Z)
High level output voltage

VOH

10

= -2.0

mA

Low level output voltage

Val

10

= +2.0

mA

V

2.4
0.4

V

Notes 1. Icc1, Icc3, Icc4, Iccs and lee6 depend on cycle rates (tRC and tHPC).

2.
3.

Specified values are obtained with outputs unloaded.
ICCI and Icc3 are measured assuming that address can be changed once or less during RAS $ V(L(MAX.)
and CAS;:: V,H (M(N.).

4.
5.

Icc3 is measured assuming that ali column address inputs are held at either high or low.
Icc4 is measured assuming that ali column address inputs are switched only once during each hyper
page (EDO) cycle.

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~PD42S16405L,

4216405L

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
VIH (MIN.)

= 2.0

VIL (MAX.)

= 0.8 V

V

(2) Output timing specification

---------------~

·--------3 i
I

iL
--..+-+--

I

I

~: 14
tT=2ns

VOH (MIN.)

=

2.0 V -mnn~:-t

VOL (MAX.)

=

0.8 V

j

}-

------~\..._ _ _ _

___J

tT=2ns

(3) Output load condition
Vee
1,180Q

1/0 - - , - . - - - - .
870n

Common to Read, Write, Read Modify Write Cycle
tRAe
Parameter

ns

tRAe = 70 ns
Unit Notes

MIN.

MAX.

MIN.

MAX.

Read 1 Write cycle time

tRe

104

-

124

-

ns

RAS precharge time

tRP

40

-

50

-

ns

CAS precharge time

tePN

10

-

10

-

ns

RAS pulse width

tRAS

60

10,000

70

10,000

ns

CAS pulse width

teAs

10

10,000

12

10,000

ns

RAS hold time

tASH

15

-

20

CAS hold time

tesH

45

-

50

-

ns

RAS to CAS delay time

tRCO

14

45

14

52

ns

2

1

ns

RAS to column address delay time

tRAD

12

30

12

35

ns

2

CAS to RAS precharge time

teRP

5

5

-

ns

3

Row address setup time

tASR

0

0

ns

Row address hold time

tRAH

10

10

-

ns

CAS to data setup time

tell

0

OE to data setup time

tOll

0

OE to data delay time

tOED

13

-

15

-

tT

1

50

1

50

ns

-

128

-

128

ms

64

-

64

Column address setup time

tAse

0

Column address hold time

teAH

10

OE lead time referenced to RAS

tOES

0

Transition time (rise and fall)
Refresh time

I
I

274

= 60

Symbol

pPD42S16405L
pPD4216405L

tREF

ns

0

-

12

-

ns

0

ns

0
0

ns
ns
ns

-

4

i

!~

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,uPD42S16405L, 4216405L
!~
- - - - - - - - - - - - - - - - - - - - - - - - - - - ' - - - - - - - - " ' - - - - - - - - - - - -..~

'if

Notes 1. In

1

CAS before RAS refresh cycles, tRAS(MAX.) is 100 !ls.

,~

If 10 !ls < tRAS < 100 /lS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.

Ii

2. For read cycles, access time is defined as follows:
Input conditions

i~

Access time

~ tRAD (MAX.)

and

tACO

:5

tRCD (MAX.)

tRAC (MAX.)

tRAG (MAX.)

tAAD> tRAQ (MAX.)

and

tACO

:5

tACO (MAX.)

tAA (MAX.)

tRAQ

+

tCAC (MAX.)

tACO

+ tCAC (MAX.)

tRAO

tACO> tACO (MAX.)

¥

Access time from RAS

fAA (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the !lPD42S16405L.

Read Cycle
tRAG = 60 ns
Parameter

tRAG = 70 ns

Symbol
MIN.

MAX.

MIN.

MAX.

Unit

Notes

Access time from RAS

tRAC

-

60

-

70

ns

1

Access time from CAS

tcAC

-

15

18

ns

1

lAA

30

-

35

ns

1

15

-

18

ns

35

-

ns

0

-

ns

Access time from OE

tOEA

-

Column address lead time referenced to RAS

tRAL

30

Read command setup time

tRGS

0

Read command hold time referenced to RAS

tRRH

0

-

0

-

ns

Read command hold time referenced to CAS

tACH

0

-

0

-

ns

2

Output buffer turn-off delay time from OE

tOEZ

0

13

0

15

ns

3

CAS hold time to OE

tGHO

5

-

5

-

ns

Access time from column address

I'

i,

2

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD (MAX.)

and

tRCD

:5

tACO (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAQ (MAX.)

and

tACO

:5

tRCO (MAX.)

tAA (MAX.)

tRAQ

+ tAA (MAX.)

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

tRAQ

:5

tRCD> tRCO (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference pOints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or !cAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD;:: tRAD (MAX.) and tRCD ;:: tRCO (MAX.) will not cause
any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

275

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~PD42S16405L,

4216405L

Write Cycle
tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

tWCH

10
10

-

10

twp

10

WE lead time referenced to RAS

tRWL

15

-

20

WE lead time referenced to CAS

tcWl

10

12

Parameter
WE hold time referenced to CAS
WE pulse width

Symbol

WE setup time

twcs

0

OE hold time

tOEH

0

Data-in setup time

tDS

0

-

Data-in hold time

tDH

10

-

0
0
0
10

Unit

Notes

-

ns

1

-

ns

1

-

ns

*

ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twes

~

twes

(MIN.),

the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
tRAG = 60 ns
Parameter
Read modify write cycle time

tRAG = 70 ns

Symbol
tRWC

Unit

Note

MIN.

MAX.

MIN.

MAX.

133

-

157

-

ns

89

-

ns

1

37

-

ns

1

54

-

ns

1

RAS to WE delay time

tAWD

77

CAS to WE delay time

tewD

32

Column address to WE delay time

tAWD

47

Note 1. If twes ~ twes (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tewD ~ tewD (MIN.), tAwD ~ tAwD (MIN.) and !cPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data ollt is indeterminate.

276

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It

,uPD42S16405L, 4216405L

------------------------------------------~------------~--------------~!~

(1,}

1

~

I"~

IfII

Hyper Page Mode (EDO)
tRAe
Parameter

Symbol

= 60 ns

tRAe

= 70 ns

til

Unit Notes

MIN.

MAX.

MIN.

MAX.

tHPC

25

-

30

-

RAS pulse width

tRASP

60

125,000

70

125,000 ns

CAS pulse width

tHCAS

10

10,000

12

10,000 ns

tep

i~
i~

Read / Write cycle time

ns

10

-

10

-

ns

Access time from CAS precharge

tACP

-

35

-

40

ns

CAS precharge to WE delay time

tCPWD

52

59

-

ns

RAS hold time from CAS precharge

tRHCP

35

40

66

75

-

ns

tHPRWC

-

ns
ns

CAS precharge time

Read modify write cycle time
Data output hold time

tOHC

5

-

5

-

OE to CAS hold time

tacH

5

-

5

ns

OE precharge time

tOEP

5

-

5

-

Output buffer turn-off delay from WE

tWEZ

0

13

0

15

ns

1

2

4

ns
3,4

WE pulse width

twpz

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFe

0

13

0

15

ns

3,4

Notes 1. tHPC (MIN.) is applied to CAS access.
2.

If twcs <:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRwD <:: tRwD (MIN.), tCWD <:: tCWD (MIN.), tAWD ~ tAWD (MIN.) and !cPWD ~ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.

3. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.

(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... tWEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tacH is effective,

277

NEe

#PD42S16405L,4216405L

Refresh Cycle
IAAe = 60 ns
Parameler

Unil
MIN.

MAX.

MIN.

MAX.

Nole

CAS selup lime

lesA

5

-

ns

teHA

10

-

5

CAS hold lime (CAS before RAS refresh)

10

-

ns

RAS precharge CAS hold time

tAPe

5

-

5

-

ns

RAS pulse width (CAS before RAS self refresh)

-

100

-

/lS

1

130

ns

1

ns

1

10

-

15

-

ns

IAASS

100

RAS precharge time (CAS before RAS self refresh)

tRPS

110

CAS hold time (CAS before RAS self refresh)

teHs

-50

WE setup time

tWSR

10

WE hold time

tWHR

15

Note 1. This specification is applied only to the IlPD42S 16405L.

278

IAAe = 70 ns

Symbol

-

-50

ns

!.\

~,

NEe
__...:.......::.==--____________
---'J1:.,...P_D_4_2_S_1_64_0_5_L.;..,_42_1_6_4_0_5L_ _ _~iiI~

1i

...~

Read Cycle

il

tAC
tAP

tRAS

RAS

V,HVIl-

1

tCSH

CAS

Address

WE

OE

V,HVIl-

V,HVII.-

VIH-

VIl-

VIH-

VIl-

tOl.z

!eLz

1/0

VOH- .••••••••••••••••••••••••• ~!:.~
VOl-

................................ .

tOFR

Data out

Hi-Z

279

~PD42S16405L,4216405L

NEe
Early Write Cycle
IRe
lRAS
RAS

IRP

V,HV,LleSH

CAS

V,HV,L-

Address

1/0

V,HV,L-

L.,l.......'->L..................................JI I\._ _ _ _ _ _ _ _ _~

Remark OE: Don't care

280

\!~.l(...K.._'~t...JI~.l(..........................~..........

NEe

~PD42S16405L,

4216405L

Late Write Cycle
tRC
tRAS

V,HVIL-

Address

VIH-

VIL-

WE

OE

V,HVIL-

11

tOED

1/0

~,~= XXXX>-----~~~m----

281

NEe

~PD42S16405L,4216405L

Read Modify Write Cycle
tRWC
tRAS

leSH
tACO

tRSH

V,HVIl-

tOEH

tOB

tDH

Dalain

Hi-Z

282

-li'

_ _N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _ _....:..}1_P_D_4_2S_1_6_4_0_5L.....;;,_4_2_1_64_O_5_L_ _ _

Ii

:1
j

i~

Hyper Page Mode (EDO) Read Cycle

I

tRASP

RAS

CAS

~

tRHCP

V!H-

V,HV,L-

tCSH

~

tHeAS

~
~

Address

WE

V,HV,L-

~

~
~

tHeAS

~

tHeAS

r---\

tRAL

~e~AH ~

V,HV,L-

tRSH

tHPC

tACO

0

~

Col.

~~

m~

Col.

~

~
Col.

il

'---

VIL-

J!I /

~

-,

'--

tOFC

:xx:

t~

tOFR

X
I--

IIII I}

~~
RRH

-VI

"\

tWEZ

OE

V,HV,L-

\\\\\\\\\\~
I

I

IAcp

A

tACP

tAA

1M

tCAC

tcAC

/

~

\\ ,\

tRAC

tAA

~

tCAC

1/0

VOHVOL-

_______________

l::Il~_z,.

~

__________ _<

~

Data out

~

--0

Data out

tOEl

--0

Data out

---

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

283

NEe

~PD42S16405L,4216405L

Hyper Page Mode (EDO) Read Cycle (WE Control)
tRASP

RAS

tRHCP

V,HVILtCSH

CAS

V,HVIL-

Address

V,HVIL-

WE

V,HVIL-

OE

I/O

V,HVll-

VOHVOL-

Hi - Z

------------ .. --- .. -------------

Data out

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

284

NEe

II

,uPD42S16405L,4216405L

-------~~-----------------------~----------~------------:1

Hyper Page Mode (EDO) Read Cycle (OE Control)

~

RASP

RAS

----.
V,H-

tRHCP

'---

VILleSH

~

-'

CAS

tRCO

~

tHCAS

~
~

tR~

~

~

Col.A

Col.B

m

Col.C

>-

+

......

\\\\\\\\\\\

I
~

~

tOCH

tOES

+-+1 tRRH

~

___________I:!i~~___________ ~~ ~

\\\\

tACP

4

~ ~

\... i---'

H~-----.
~

""~"8

----~~

\.-

tOFR

)

tcHO

tACP

~
-----.

~

'XX
CAe
IAA

leHO

~

-o~H

~

I,IOE\

VOH-

II /

IAA

IAA

~

tOCH

1/0 VOL-

tHCAS

~ ~

~~

tRAG

IIIII!

OE

~
,...---

tHCAS

tRAL

Row

WE

tASH

r---"l

[\\

~

Address

IHPC

Data out B

---

II
OEA
t l.Z

tOEZ

~

Data out B --

\\\\

~

~ Data out C

_!i!~~_

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

285

NEe

~PD42S16405L,4216405L

Hyper Page Mode (EDO) Early Write Cycle

Address

V,H-

'r'r"'r"r"r-I:"""'-

VIL-

Remarks 1. OE: Don't care

2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

286

1:1

,!.

NEe

,uPD42S16405L,4216405Li

-~~-=---------------!",-----=-------'l
'~

'~

Hyper Page Mode (EDO) Late Write Cycle

,~

tRP

tRASP

~I:p

tRHCP

RAS

VIH-

VILtCSH

Address

V,HVIL-

WE

V,HVIL-

OE

V,HVIL-

1/0

VIHVIL-

tHPC

tRSH

Hi-Z
.----------------

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

287

NEe

~PD42S16405L,4216405L

Hyper Page Mode (EDO) Read Modify Write Cycle

1/0

VOHVOl-

1/0

V,HVIL-

Remark

In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

288

I,~

,

,I

-i'!

___N_E_C
______________--=Jl_P_D_4_2_S_1_6_40_5_L....;..,_4_2_16_4_0_5_L_ _ _

III"~
Hyper Page Mode (EDO) Read and Write Cycle
tRASP
tRHCP

V'HRAS

VIL-

lesH
VIH-

CAS

Address

WE

OE

VIL-

V,HVIL-

V,HV,L-

V,HVIL-

1/0

VOH- .......................................................
Hi - Z
VOL-

1/0

V,H-

_.-

................Hi -Z
_. _.. - .... - .... -- - .. -

I

VIL-

Remark

In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

289

NEe

~PD42S16405L,4216405L

CAS Before RAS Self Refresh Cycle (Only for the ,uPD42S16405L)

tRASS
VIH-

V,L-

tCSR

V,HVll-

V,HVIL-

Remark Address, OE : Don't care

:\\\\\\\\\\\\\\\\\\\\\\\
I/O : Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 4,096 times within a 64 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 4,096 times within a 64 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS(MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 .us), CAS before

RAS refresh cycles will be executed one time.
If 10

.us < tRAS < 100 .us, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.

And refresh cycles (4,096/128 ms) should be met.
For details, please refer to How to use DRAM User's Manual.

290

II

NEe

.

Ij

,uPD42S16405L, 4216405L

------------------------------------------------------------------~------------------~------------------------~,.!~

I~

'I;
i :~

CAS Before RAS Refresh Cycle

tRAS
VIH-

VILleSR

tCHR

V,HVIL-

Remark Address, OE: Don't care

1/0: Hi-Z

RAS Only Refresh Cycle
IRe
tRAS

IRP

tRAS

V,HVIL-

tCRP
VIH-

VIL-

Address

V,HVIL-

Remark WE, OE: Don't care

I/O: Hi-Z

291

NEe

~PD42S16405L,4216405L

Hidden Refresh Cycle (Read)

RAS V,HVIL-

CAS V,H-

V,L-

Address

WE

VIH-

V,L-

V,H-

V,L-

OE V,H-

V,L-

I/O VOHVOL-

292

IRC

tRC

tRAS

tRAS

t

NEe
,uPD42S16405L,4216405Lf
------'----------------------'--------'------------1
.~

~

IX

Hidden Refresh Cycle (Write)

:,~

tRC
tRAS

RAS

Address

I/O

'~

tRC

:1

tRAS

~

V,H-

V,l-

V,HV,l-

V,H-

V,l- ....,'-"'-"'-l<.......-"--"-"'-'''->I' " -_ _ _ _JI ,,'-l<-"--"-"'-'''-''-'''-'''-l<.......-''--''-'''-'''-''-'''-'''-l<-''--''--''-.>r......>
Remark OE: Don't care

293

NEe

~PD42S16405L,4216405L

Test Mode Set Cycle (WE,

CAS Before RAS Refresh Cycle)
tRC

tRAS

tCSR

tCHR

Remark Address, OE: Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
x 16-bit organization during test mode. Don't care about the input levels of the CAS input AD, A 1.

(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.

(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1": Normal write (all memory cells)
Output = "0": Abnormal write

(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.

(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

294

_~N~E;;;;..C.=;,..._ _ _ _ _ _ _ _ _ _ _ _~J1_P_D_4_2S_1_6_4_05_L~,_4_21_6_4_O_5L_ _ _ _

,.I.:

J

Iii~

Package Drawings

26PIN PLASTIC TSOP(II) (300 mil)

i$

.b

1\1

26

14
detail of lead end

-H~-----+------+-

H

rr:Uf 1.
B

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

+ll
!4-1--

~--

JJJ

L

ITEM

MILLIMETERS

INCHES

A
B

17.36 MAX.
1.06 MAX.
1.27 (T.P.)

0.684 MAX.
0.042 MAX.
0.050 (T.P.)

0

0.42::8:8~

0.017±0.003

E

0.1 ±O.OS
1.2 MAX.
0.97
9.22±0.2
7.62±0.1

0.004±0.002
0.048 MAX.
0.038
0.363±0.008
0.300±0.004

0.8±0.2

0.031 ::8:88~

0.14S::8:8~~

0.006±O.001

O.S±O.l

0.020::8:88~

N

0.21
0.10

0.009
0.004

P

3,+7'
-3'

3, .. 7'
-3'

C

F
G
H

K

M

S26G3-50-7 JD1

295

NEe

~PD42S16405L,

4216405L

26 PIN PLASTIC SOJ (300 mil)

o

0

13
F

J:

-

NOTE

Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

17.3~g:~g

0.6Bl ~g:g~g

c

7.62

0.300

0

8.47±0.2

0.333.;:g:gg~

E

1.03±0.15

0.041 ~g:gg~

F

0.029
0.13B±0.00B
0.100±0.00B
0.031 MIN.
0.102
0.050 (T.P.)

K

0.74
3.5±0.2
2.545±0.2
O.B MIN.
2.6
1.27 (T.P.)

M

0.40±0.10

0.016~g:gg~

N
P
T

0.12
6.73±0.2
0.10
RO.B5

0.005
0.265±0.00B
0.004
RO.033

U

0.20~g:bg

0.00B~8:88~

G

H

Q

S26LA·300A·l

296

:t

___
N_E_C_ _ _ _ _ _ _ _ _ _ _ _ _----!f.1_P_D_4_2_S_16_4_0_5_L"-,4_2_1_6_4_05_L_ _ _---ii:1
i.~
J.

'I

Recommended Soldering Conditions

"~,

"

J

The following conditions (see tables below and next page) must be met for soldering conditions of the
IlPD42S16405L. 4216405L.
For more details. refer to our document"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"

"

~;\

(IEI-1207).
Please consult with our sales offices in case other soldering process is used. or in case the soldering is done
under different conditions.

Types of Surface Mount Device
jlPD42S16405LG3,4216405LG3: 26-pin plastiC TSOP (ll) (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235 °C or lower.
Reflow time: 30 seconds or less (210 °C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-107-2

i

(10 hours pre-baking is required at 125 °C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
VPS

Peak temperature of package: 215 °C or lower.
Reflow time: 40 seconds or less (200 °C or higher).
Number of reflow processes: MAX. 2
Exposure limit :7 daysNote

VP15-107-2

(10 hours pre-baking is required at 125 °C afterwards)
Cautions
1. After the first reflow process. cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
Partial heating method

Note

Terminal temperature: 300 °C or lower.
Time: 3 seconds or lower (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25°C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

297

NEe

~PD42S16405L,4216405L

.uPD42S16405LLA,4216405LLA: 26-pin plastic SOJ (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235 'c or lower.
Reflow time: 30 seconds or less (210 'c or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-207-2

(20 hours pre-baking is required at 125 'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
Peak temperature of package: 215 'c or lower.
Reflow time: 40 seconds or less (200 'C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

VPS

VP15-207-2

(20 hours pre-baking is required at 125 'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

298

Terminal temperature: 300 'C or lower.
Time: 3 seconds or less (Per side of the package).

..~

DATA SHEET

Ij

r-------------------------------------j

NEe

MOS INTEGRATED CIRCUIT

~PD42S17405L,4217405L

I

I

-----=-----~---,t

r

3.3 V OPERATION 16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, HYPER PAGE MODE (EDO)

---------------------------------------------------:i~
'~

J

Description

~
1

The ILPD42S17405L, 4217405L are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional hyper page
mode (EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the ILPD42S17405L can execute CAS before RAS self refresh.
The ILPD42S17405L, 4217405L are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ.

Features
Hyper page mode (EDO)
4,194,304 words by 4 bits organization
Single +3.3 V ±0.3 V power supply
Power
consumption
Active (MAX.)

Part number

R/W cycle time
(MIN.)

Hyper page mode (EDO)

(MAX.)

Access time

cycle time (MIN.)

IlPD42S17405L-A60, 4217405L-A60

360 mW

60 ns

104 ns

25 ns

IlPD42S17405L-A70, 4217405L-A70

324 mW

70 ns

124 ns

30 ns

ILPD42S17405L can execute CAS before RAS self refresh

Part number
IlPD42S17405L

Refresh

Refresh cycle
2,048 cycles/128 ms

CAS before RAS self refresh
CAS before RAS refresh

Power consumption
at standby (MAX.)
0.54 mW
(CMOS level input)

RAS only refresh
Hidden refresh
IlPD4217405L

2,048 cycles/32 ms

CAS before RAS refresh
RAS only refresh
Hidden refresh

1.8mW
(CMOS level input)

The information in this document is subject to change without notice.
Document No. M10068EJ4VODSU1

299

NEe

yPD42S17405L,4217405L

Ordering Information

Part number

Access time
(MAX.)

Package

,uPD42S 17405LG3-A60

60 ns

,uPD42S17405LG3-A70

70 ns

,uPD42S 17405LLA-A60

60 ns

26-pin plastic SOJ

,uPD42S 17405LLA-A70

70 ns

(300 mil)

Refresh

26-pin plastic TSOP (II)

CAS before RA.S self refresh

(300 mil)

CAS before RAS refresh
RAS only refresh

300

,uPD4217405LG3-A60

60 ns

26-pin plastic TSOP (II)

,uPD4217 405LG3-A 70

70 ns

(300 mil)

,uPD4217405LLA-A60

60 ns

26-pin plastic SOJ

,uPD4217405LLA-A70

70 ns

(300 mil)

Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

i

:!

NEe

I,!"

yPD42S17405L,4217405L

Ii
,';
1,1

':;;'

Pin Configurations (Marking Side)
26-pin Plastic TSOP (II) (300 mil)

,t

26-pin Plastic SOJ (300 mil)

it
~'

26

26

GND

GND

Vee

1/01

1/04

1/01

1/04

1/02

1/03

1/02

1/03

Vee

WE

-.:-.:

RAS

00

CAS

"Il"ll
~~

10

WE

RAS

5

A9

NC

6

6

"'en
.......
~

....

21

o~

A2
A3
Vee

8

'"

....
e:> ....
we:>
w

A8
A7

10
11
12
13

OE

~~

"'en
.......
~ ....
o~

21

i
l

A9

11

:1

"'0

"'0

A10
AD
A1

CAS

00
11:111:1

11:111:1

NC

-.:-.:

"Il"ll

OE

4

.t
,~1

14

A6
A5
A4
GND

A10
AD
A1
A2
A3
Vee

8
9
10
11
12
13

.... ....'"
....
~ ....

A8
A7
A6

~

14

A5
A4
GND

AO to A10 : Address Inputs
1/01 to 1/04: Data Inputs/Outputs
RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

301

NEe

yPD42S17405L, 4217405L

Block Diagram

Clock
Generator

Vee 0---GND 0----

CAS before
RAS Counter

G;

"80
Q)

Cl

3:

0

a:

co

;g

Memory
Cell
Array

","

2,048 x 2,048 x 4

1/01
to

1/04
Row
Address
Buffer
AO
to
Al0
Column
Address
Buffer

302

___N_E_C=-_ _ _ _ _ _ _ _ _ _ _ _~J.1!:.:,;P~D:;..4=2:;..;:S......;.1..;...74..;...O:...:5:...::L:.!..,...:..42:::...1.:....:7--=4...::..0..::...;5L::=--_ _~. j.·
,,~

Input/Output Pin Functions
The jtPD42S17405L, 4217405L have input pins RAS, CAS, WE, OE, AO to A10 and input/output pins 1/01 to
1/04.

Pin name
RAS

Input/Output
Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS

Input

CAS activates data input/output circuit by latching column address and

Input

Address bus.
Input total 22-bit of address signal, upper 11-bit and lower 11-bit in sequence
(address multiplex method).

(Column address strobe)
AO to A10
(Address inputs)

selecting a digit line connected with the sense amplifier.

Therefore, one word is selected from 4,194,304-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASA, tAse) and hold time (tAAH, teAH)
are specified for the activation of RAS and CAS.
WE

Input

OE
(Output enable)

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

(Write enable)
Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.

I! WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
1/01 to 1/04

(Data inputs/outputs)

Input/Output

4-bit data bus.
1/01 to 1/04 are used to input/output data.

303

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yPD42S17405L, 4217405L

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.

1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle.

The hyper page mode (EDO) allows both read and write operations during one cycle, but the

performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
Hyper Page Mode (EDO) Read Cycle
RAS

~::=

CAS

V,HVIL-

--r-+----+.....

Address V,HV,L-

WE V,H-

V,L -

OE

304

~::=

",-,,--,"-'-...1-.1

it

NEe

,uPD42S17405L,4217405Li

----------------------------------------------------~--------------~--------------------.~

Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

305

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yPD42S17405L, 4217405L

Electrical Specifications
All voltages are referenced to GND.
After power up (Vcc ~ Vcc (MIN.»), wait more than 100 /lS (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

mA

Power dissipation

Po

1

W

Operating ambient temperature

TA

o to +70

°C

Storage temperature

Tstg

-55 to +125

°C

Parameter

Caution

Symbol

Condition

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

3.0

3.3

3.6

V

High level input voltage

V,H

2.0

Vee + 0.3

V

Low level input voltage

VIL

-0.3

+0.8

V

Operating ambient temperature

TA

0

70

°C

Parameter

Capacitance (TA

Condition

=25 'c, f =1 MHz)

Parameter
Input capacitance

Data input/output capacitance

306

Symbol

MAX.

Unit

C"

Address

5

pF

C'2

RAS, CAS, WE, OE

7

CliO

1/0

7

Test condition

Symbol

MIN.

TYP.

pF

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Operating current

Standby

leet

JlPD42S17405L

ICC2

current
JlPD4217405L

Test condition

MIN.

RAS, CAS cycling
tRC = tRG (MIN.), 10 = 0 mA
RAS, CAS" V'H (M'N.), 10

=0

~

60 ns

tRAe

= 70

ns

=0

=0

mA

RAS, CAS" Vee - 0.2 V, 10

=0

MAX.

Unit

Notes

100

mA

1,2,3

90
0.5

mA

RAS, CAS" Vce - 0.2 V, 10
RAS, CAS" V'H (M'N.), 10

tRAG

mA

0.15

mA

0.5

2.0

RAS only refresh current

ICC3

RAS cycling, CAS" V'H (M'N.)
tRe = tRe (MIN.), 10 = 0 mA

tRAe

= 60 ns

100

tRAe

= 70

ns

90

Operating current

lee4

RAS ,; VIL (MAX.), CAS cycling
tHPC = tHPC (MIN.), 10 = 0 mA

tRAe

= 60

ns

90

tRAe

= 70

ns

80

RAS cycling
tRe = tRe (M'N.), 10

tRAe

= 60

ns

100

tRAe

= 70

ns

(Hyper page mode (EDO))
lee5

CAS before RAS
refresh current
CAS before RAS

Icc,

=0

mA

CAS before RAS refresh:

long refresh current

tRe

(2,048 cycles / 128 ms,

mA

mA

1,2,3,4

mA

1,2,5

mA

1,2

JlA

1,2

90

tRAS'; 1 JlS

200

= 62.5 JlS

RAS, CAS:

only for the JlPD42S17405L)

Vee - 0.2 V ,; V'H ,; V'H (MAX.)

o V,; VIL'; 0.2 V
Standby:
RAS, CAS" Vee - 0.2 V
Address: V'H or VIL

!:

WE, OE: V'H
10
CAS before RAS

lee7

=0

mA

RAS, CAS:

=5

self refresh current

tRASS

(only for the "PD42S17405L)

Vee - 0.2 V ,; V'H ,; V'H (MAX)

150

JlA

-5

+5

JlA

-5

+5

JlA

0.4

V

2

ms

o V,; VIL'; 0.2 V
Input leakage current

Ii(l)

10

=0

V,

= 0 to 3.6 V

mA

All other pins not under test
Output leakage current

10(l)

Vo

= 0 to

=0 V

3.6 V

Output is disabled (Hi-Z)
High level output voltage

VOH

10

= -2.0

mA

Low level output voltage

VOL

10

= +2.0

mA

V

2.4

Notes 1. Icc1, Icc3, Icc4, Iccs and Icc, depend on cycle rates (tRC and tHPC).

2. Specified values are obtained with outputs unloaded.
3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS::; VIL(MAX.)
and CAS;::

V,H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.

307

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yPD42S17405L, 4217405L

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
VIH (MIN.)

= 2.0

V

VIL (MAX.)

= 0.8

V

(2) Output timing specification

---------------~

·--------3 i
I
I

iL

I
I

,
I

------=f

}-

VOH (MIN.)

= 2.0

V

VOL (MAX.)

= 0.8

V------~'-_ _ _ _

I
I

__J_

J: :•

-:--r-IT= 2 ns

IT= 2 ns

(3) Output load condition
Vee
1,1800

r

I/O--~--~

100 PF
Cl

8700

Common to Read, Write, Read Modify Write Cycle
tRAe
Parameter

Symbol

tRAe

= 70 ns

Unit Notes

MAX.

MIN.

MAX.

tRe

104

124

-

ns

50

-

ns

10

RAS precharge time

tRP

40

CAS precharge time

tcPN

10

-

RAS pulse width

tRAS

60

10,000

70

10,000

ns

CAS pulse width

teAs

10

10,000

12

10,000

ns

RAS hold time

tRSH

15

20

tesH

45

-

ns

CAS hold time

-

RAS to CAS delay time

tReD

14

45

14

52

ns

2

RAS to column address delay time

tRAD

12

30

12

35

ns

2

CAS to RAS precharge time

tCRP

5

5

3

tASR

0

ns

10

-

ns

Row address setup time

0

-

ns
ns

0

-

Read I Write cycle time

Row address hold time

tRAH

10

Column address setup time

tAse

0

Column address hold time

tcAH

10

-

OE lead time referenced to RAS

tOES

0

-

CAS to data setup time

tell

b

OE to data setup time

tOlZ

0

OE to data delay time

tOED

13

Transition time (rise and fall)
Refresh time

308

= 60 ns

MIN.

tT

I
I

IlPD42S17405L
IlPD4217405L

tREF

-

50

0

12

0
0
15

ns

ns

ns
ns
ns
ns

1

50

1

50

ns

128

-

128

ms

32

*

ns

-

32

1

4

I---

*

'¢

~

___
N_E_C_ _ _ _ _ _ _ _ _ _ _ _ _......IJ.1-'-P_D_4_2_S_17_4_0..;...S.......
L,..;...4_2_1_74_0..;...S_L_ _ _I]
I"

Notes 1. In CAS before RAS refresh cycles. tRAS (MAX.) is 100 }.ls.

If 10 J.LS < tRAS < 100 J.LS. RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles. access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD (MAX.)

and

tRCO ::; tACO (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.)

and

tRCO ::; tRCO (MAX.)

tAA (MAX.)

tRAD

+ tAA (MAX.)

tCAC (MAX.)

tRCD

+ tcAC (MAX.)

tRAD

$

tACO> tACO (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference pOints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ;:: tRAD (MAX.) and tRCD ;:: tRCO (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the ,uPD42S17405L.

Read Cycle
tRAC = 60 ns

tRAe = 70 ns

Symbol

Parameter
Access time from RAS

tRAG

Unit

Notes

MIN.

MAX.

MIN.

MAX.

-

60

-

70

ns

1

15

18

ns

1

35

ns

1

18

ns

-

ns

0
0

-

Access time from CAS

teAe

Access time from column address

tAA

-

30

tOEA

-

15

Column address lead time referenced to RAS

tRAL

30

35

Read command setup time

tRCS

0

ns

2

0

-

ns

2
3

Access time from OE

Read command hold time referenced to RAS

tARH

0

Read command hold time referenced to CAS

tRCH

0

-

Output buffer turn-off delay time from OE

tOEl

0

13

0

15

ns

CAS hold time to OE

tCHO

5

-

5

-

ns

ns

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD::; tRAD (MAX.)

and

tACO::; tRCO (MAX.)

tRAC (MAX.)

tRAG (MAX.)

tRAD> tAAD (MAX.)

and

tRCO ::; tRCO (MAX.)

tAA (MAX.)

tRAD

+ tAA (MAX.)

tCAC (MAX.)

tRCO

+

tACO> tRCo (MAX.)

tCAC (MAX.)

tRAD(MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

309

NEe

yPD42S17405L,4217405L

Write Cycle
Parameter

tRAe

= 60 ns

tRAe

= 70 ns

MIN.

MAX.

MIN.

MAX.

10

-

ns

1
1

Symbol

Unit Notes

10

-

WE pulse width

twp

10

-

10

-

ns

WE lead time referenced to RAS

tRWL

15

20

tCWL

10

WE setup time

twes

0

OE hold time

tOEH

0

Data-in setup time

tos

0

Data-in hold time

toH

10

-

ns

WE lead time referenced to CAS

-

WE hold time referenced to CAS

tWCH

12
0
0
0
10

ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twes ~ twes (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
tRAe = 60 ns
Parameter

tRAe = 70 ns
Unit

Symbol
MIN.

MAX.

MIN.

Read modify write cycle time

tRwe

133

-

157

RAS to WE delay time

tRWo

77

89

CAS to WE delay time

tCWD

32

-

47

-

Column address to WE delay time

tAWD

37
54

MAX.

-

Note

ns
ns

1

ns

1

ns

1

Note 1. If twes ~ twes (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), lewD ~ tewD (MIN.), tAWD ~ tAWD (MIN.) and !cPWD ~ !cPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

310

j

NEe
______
...;;;;;;;...=-_ _ _ _ _ _ _ _ _ _ _ _ _. . . J1c..:P;"..,:D::....4~2::..:S:.....:1~7....:..4..::....05::...:L::..!.,....:4;.::2~1~74..:...;O:....:5;..::L:.....-.-_ _-yi~IJ
Hyper Page Mode (EDO)

Parameter

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

Unit Notes

Symbol
MAX.

tHPC

25

-

30

-

ns

RAS pulse width

tRASP

60

125,000

70

125;000

ns

CAS pulse width

tHCAS

10

10,000

12

10,000

ns

tcp

10

-

10

-

ns

Access time from CAS precharge

tACP

-

35

-

40

ns

CAS precharge to WE delay time

tcPWD

52

-

59

ns

RAS hold time from CAS precharge

tRHCP

35

-

40

Read I Write cycle time

CAS precharge time

1

tHPAWC

66

-

75

-

Data output hold time

tOHC

5

-

5

-

ns

OE to CAS hold time

tOCH

5

-

5

-

ns

OE precharge time

tOEP

5

-

5

-

ns

Output buffer turn-off delay from WE

tWEZ

0

13

0

15

ns

3,4

WE pulse width

twpz

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFC

0

13

0

15

ns

3,4

Read modify write cycle time

2

ns
ns

4

Notes 1. tHPC (MIN.) is applied to CAS access.

I

2. If twcs ? twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRWD ? tRWD (MIN.), tCWD?' tCWD (MIN.), tAWD? tAWD (MIN.) and tcPWD ? tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions

I'
I.

is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEz (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.

(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... tWEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... taCH is effective.

311

NEe

yPD42S17405L,4217405L

Refresh Cycle

Parameter

tRAe = 70 ns

MAX.

MIN.

MAX.

Unit

CAS setup time

tesR

5

-

5

-

ns

CAS hold time (CAS before RAS refresh)

teHR

10

-

10

tAPe

5

-

5

tRASS

100

-

100

tAPS

110

-

130

CAS hold time (CAS before RAS self refresh)

tcHS

-50

-

-50

WE setup time

tWSR

10

-

10

WE hold time

tWHR

15

-

15

-

ns

RAS precharge CAS hold time
RAS pulse width (CAS before RAS self refresh)
RAS precharge time (CAS before RAS self refresh)

Note 1. This specification is applied only to the ,uPD42S 17405L.

312

tRAe = 60 ns
MIN.

Symbol

Note

ns

I1S

1

ns

1

ns

1

ns
ns

I~
"

i~

____~~~E~c:~________________________~y=P~D_4_2~S_17_4~O_5L~,_4_2_17_4_0_5_L_______ 4
Read Cycle
tRe
tRP

tRAS

RAS

V,HVIltCSH

CAS

V,HV,L-

Address

V,HVIl-

WE

OE

V,HVIL-

V,HVIl-

tOlZ

tell

I/O

VOH- . _________________________ ~!:_~
VOL-

_______________________ _________ _

tOFR

Data out

Hi -Z

313

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yPD42S17405L,4217405L

Early Write Cycle
tRC
tRAS

RAS

tRP

VIHVIL-

tCSH

CAS

VIHVIL-

Address

IIC

V,HVIL-

V,HVIL-

I....JIL...lL..ll'-lL-lL...lL....lL-l£,..;>L..J/ I\-_ _ _ _ _ _ _ _ _-JI "-"-'''--''-'''-'''....>L....l<..-''-'''-''--'''-''-'''-''-''--''

Remark OE: Don't care

314

NEe

gPD42S17405L,4217405L

Late Write Cycle
tRC
tRAS

CAS

Address

tOEH

I
I

!~

315

NEe

yPD42S17405L,4217405L

Read Modify Write Cycle
tRWC
tRAS

tesH
tReD

tRSH

VrH-

VIl-

twp

tOEH

tDS

tDH

Data in

Hi-Z

316

___N_E----.,;C~_ _ _ _ _ _ _ _ _ _ _ __ 1.J1: .:.P. . .: D:. . .;4:. : ;2. .;:. S. . ;.,.17:. . .;4;. .;.O. .:. .5L; ; ; ,l,:. . .4.:. : 2;. :,.1. :. .74~O:. . : 5. : L_ _ _ _I_1
~:

,'g

i

Hyper Page Mode (EDO) Read Cycle

I~
tRASP

RAS

VIH-

Address

VIL-

V,HVIL-

J

~

tHCAS

Row

tHCAS

n

Col.

~

tHCAS

1~

~

~

~~

~

tRAL

x)

mJl n

~~

y/ ~'J

~

Col.

Col.

WE

tOfR

IOFC

J

:xx: x:

I~
V,HVIL-

1

tRSH

tHPC

tRCO

ji
I!

~

VIL-

tcSH

CAS

IRP

~

tRHCP

VIH-

I-

III/I}

~

~

ARH

'\

y/

1

IWEZ

VIH-

OE

VIL-

\\\\\\\\\\~

~--I

tACP

tACP

IAA

IAA

tcAC

tCAC

I

\\\\

tRAC

IAA
tCAC

1/0

Remark

VOHVOL-

~

~

~

---------------I:I!:!-..----------~>

Dala oul

--Q

Dala oul

tOEZ

--{}

Dala oul

~---

In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

317

NEe

yPD42S17405L,4217405L

Hyper Page Mode (EDO) Read Cycle (WE Control)
I RASP
tRHCP

RAS

lesH

CAS

V,HVIl-

Address

V,HVIl-

WE

V,HVIl-

OE

V,HVIl-

1/0

VOH~

VOL-

Remark

.............

Hi -- ......
Z -- ........ -- ..
-_ ..............

In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

318

Data oul

:1

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,uPD42S17405L, 4217405L
--------------------------------~------~------------I'
I~

Hyper Page Mode (EDO) Read Cycle (OE Control)

II
I~

I,
RAS V,HVIL-

CAS

VIHVIL-

Address

WE

VOH-

1/0

VOL-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

319

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yPD42S17405L,4217405L

Hyper Page Mode (EDO) Early Write Cycle

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

320

I}

_____~
__E:_c:
____________________________~y~P=D_4_2S_1_7_4_0_5~L,~4_2_1_7_4~05_L________'i
"

Hyper Page Mode (EDO) Late Write Cycle
tRASP
tRHCP

RAS
tCSH

tHPC

tRSH

V,HVIL-

Address

WE

V,HVIl-

OE

V,HVIl-

1/0

Remark

Hi-Z
,----------------

In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

321

NEe

yPD42S17405L,4217405L

Hyper Page Mode (EDO) Read Modify Write Cycle

V,H-

V,l-

Address

WE

V,H-

V,l-

V,H-

V,l-

I/O

VOHVOl-

I/O

V,HV,l-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

322

NEe

yPD42S17405L,4217405L

Hyper Page Mode (EDO) Read and Write Cycle
tRASP

RAS

tRHCP

V'HVIL-

tCSH

CAS

V'HVIL-

Address

V'HV'L-

WE

V'HV'L-

OE

V'HV'L-

110

VOHHi" Z
VOL- """""" """"- - - --- -- - --- - --- --- ---

___________Ijl:f:. ________ "_""_
tOH

1/0

Remark In the hyper page mode (EDOl, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

323

NEe

yPD42S17405L,4217405L

CAS Before RAS Self Refresh Cycle (Only for the ttPD42S17405L)

tRASS

tCSR

~\\\\\\\\\\\\\\\\\\\\\\\
Remark Address, OE : Don't care

1/0: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 2,048 times within a 32 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 2,048 times within a 32 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 ttS), CAS before
RAS refresh cycles will be executed one time.
If 10 ttS < tRAS < 100 ttS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (2,048/128 ms) should be met.
For details, please refer to How to use DRAM User's Manual.

324

I

II
_ _N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _---.LJl.;.;..P__D_4_2S_1_7_4_0_5L....:.J_4_2_17_4_0_5_L_ _ _:J

,

:,t

CAS Before RAS Refresh Cycle
tRC

tRC
tRAS

tCSR

tCHR

Remark Address, OE: Don't care

1/0: Hi-Z

RAS Only Refresh Cycle
tRC
tRAS

tRP

tRAS

tCAP

Address

Remark WE, OE: Don't care

1/0: Hi-Z

325

NEe

yPD42S17405L, 4217405L

Hidden Refresh Cycle (Read)
tRC

tRC

tRAS

tRAS

V,HRAS VIL-

teRP

CAS

V,HVIL-

Address

WE

OE V,HVIL-

tCLZ

I/O VOHVOl-

326

Hi-Z

Data out

Hi-Z

f

___N_E~C=--_ _ _ _ _ _ _ _ _ _ _ _----t.J1~P_D_4_2_S_17_4-,O_5_L,,-,4_2_1_7_4_05_L_ _ _ _

I~

Hidden Refresh Cycle (Write)
tRC

RAS

I:~

!~.:
!,~

V,HVIL-

tCRP

CAS

II

tRC

tRAS

tRAS

tcPN

V,><-

+--+_""-<-J

VIL- -->->--"-->-.......,.........->--"-,..... _ _

tlO

V,HVIL- L..l"-lj~....K...lt...lL..l"-ll~~

'-_ _ _ _..JI

""""'..3-.x....;......~"""'..3-...............,.......'-'<-"-...................................................

Remark OE: Don't care

327

NEe

yPD42S17405L,4217405L

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)
tAC

Remark Address, OE: Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
16-bit organization during test mode. Don't care about the input levels of the CAS input AO, A 1.
(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1 ": Normal write (all memory cells)
Output = "0": Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

328

,
NEe

.uPD42S17405L, 4217405L

',I

------------~-------------------------------------------L~~~~~~~~~~~~~~----------~1

Package Drawings

26PIN PLASTIC TSOP(II) (300 mil)

detail of lead end

-+-1------+------+

UlJDU.~1.
B

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

H

+~

~J-

-~

~
L
ITEM

MILLIMETERS

A

17.36 MAX.
1.06 MAX.
1.27 (T.P.)

INCHES
0.684 MAX.
0.042 MAX.
0.050 (T.P.)

0

0.42~8:8~

0.017±0.003

E
F
G
H

O.1±O.OS
1.2 MAX.
0.97
9.22±0.2
7.62±0.1

0.004±0.002
0.048 MAX.
0.038
0.363±0.008
0.300±0.004

B
C

K

0.8±0.2

0.031~8:88~

0.145~8:m

0.OO6±0.001

L

0.S±0.1

0.020~8:88~

M
N

0.21
0.10

0.009
0.004

P

3 +7
-3

3 +7
-3

J

S26G3-50-7JD1

329

NEe

yPD42S17405L,4217405L

26 PIN PLASTIC SOJ (300 mil)

o

Cl

13

F

:r -

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

17.3:':8:~g

0.681:':8:8?8

c

7.62

0.300

0

8.47±0.2

0.333:':8:88~

E

1.03±0.15

0.041:':8:g8~

F
G

0.029
0.138±0.008
0.100±0.008
0.031 MIN.
0.102
0.050 (T.P.)

K

0.74
3.5±0.2
2.545±0.2
0.8 MIN.
2.6
1.27 (T.P.)

M

0.40±0.10

0.016:':8:88~

N
P
T

0.12
6.73±0.2
0.10
RO.85

0.005
0.265±0.008
0.004
RO.033

u

0.20:':8:~g

O.OO8:':8:88~

H

Q

S26LA-300A-l

330

NEe
____________________________________
~y~P~D~42~S~1~7~4~O~5L~,~4~2~1~7~4O~5~L~____~ltI}
1
,;

I.I~I

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
tLPD42S17405L, 4217405L.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(lEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
'~

under different conditions.

Types of Surface Mount Device
tLPD42517405LG3, 4217405LG3: 26-pin plastic T50P (II) (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-107-2

(10 hours pre-baking is required at 125'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first rellow process, do not use water to remove
residual flux (water can be used in the second process).
VPS

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit :7 daysNote

VPI5-107-2

(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

Terminal temperature: 300'C or lower,
Time: 3 seconds or lower (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25

Caution

'c and relative

humidity at 65 % or less.

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

331

NEe

.uPD42S17405L, 4217405L

,uPD42S17405llA, 4217405llA: 26-pin plastic SOJ (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235'C or lower.
Reflow time: 30 seconds or less (210 ·C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
VPS

Peak temperature of package: 215'C or lower.
Reflow time: 40 seconds or less (200 ·C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNoto

VPI5-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

Terminal temperature: 300'C or lower.
Time: 3 seconds or less (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

332

---li

,--_ _ _
D_A_T_A_S_H_E_E_T_ _ _ _ _ _ _ _ _ _ _ _

NEe

MOS INTEGRATED CIRCUIT

'(II

J

_ _ _---=Jl~P_D_4_2S_1_7_80_5___.:L,_4_2_17_8_05_L_ il
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
2 M-WORD BY 8-BIT, HYPER PAGE MODE

Description
The JlPD42S17805L, 4217805L are 2,097,152 words by 8 bits CMOS dynamic RAMs with optional hyper page
mode.
Hyper page mode is a kind of the page mode and is useful for the read operation.
Besides, the JlPD42S17805L can execute CAS before RAS self refresh.
The JlPD42S17805L, 4217805L are packaged in 28-pin plastic TSOP (II) and 28-pin plastic SOJ.

Features
Hyper page mode (EDO)
2,097,152 words by 8 bits organization
Single +3.3 V ±0.3 V power supply

Part number

Power
consumption
Active (MAX.)

Access time
(MAX.)

RfW cycle time
(MIN.)

Hyper page mode
cycle time
(MIN.)

pPD42S17805L-A60, 4217805L-A60

360 mW

60 ns

104 ns

25 ns

pPD42S17805L-A70, 4217805L-A70

324 mW

70 ns

124 ns

30 ns

The JlPD42S 17805L can execute CAS before RAS self refresh

Part number
pPD42S 17805L

Refresh cycle
2,048 cycles/128 ms

Refresh
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh

pPD4217805L

2,048 cycles/32 ms

CAS before RAS refresh,
RAS only refresh,
Hidden refresh

Power consumption
at standby (MAX.)
0.54 mW
(CMOS level input)

1.8mW
(CMOS level input)

The information in this document is subject to change without notice.
Document No. Ml0070EJ4VODSUl

333

NEe

yPD42S17805L,4217805L

Ordering Information
Access time
(MAX.)

Package

pPD42S 17805LG5-A60

60 ns

28-pin Plastic TSOP (II)

pPD42S 17805LG5-A70

70 ns

(400 mil)

pPD42S17805LLE-A60

60 ns

28-pin Plastic SOJ

/lPD42S 17805LLE-A70

70 ns

(400 mil)

pPD4217805LG5-A60

60 ns

28-pin Plastic TSOP (II)

Part number

334

/lPD4217805LG5-A70

70 ns

(400 mil)

/lPD4217805LLE-A60

60 ns

28-pin Plastic SOJ

/lPD4217805LLE-A70

70 ns

(400 mil)

Refresh
CAS before RAS self refresh
CAS before

RAs refresh

RAS only refresh
Hidden refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh

17:.
i

NEe

:i
'i

yPD42S17805L,4217805L

~
~i.

Pin Configurations (Marking Side)

,(

28-pin Plastic TSOP (II) (400 mil)

1

28-pin Plastic SOJ (400 mil)

t

"i

28
27

GND

Vee

10

28

GND

1/08

1/01

2

1/08

26

1/07

1/02

1/07

1/06

1/03

25

1/06

CC

25
24

3
4

27
26

1/05

1/04

5

1::1::

.... 1/1

23

CAS

WE

6

22
21

DE

RAS

7

cc
........
.,.,

A9
A8
A7

NC
A10
AD

8
9
10
11

Vee

1/01

2

1/02

3
4

1/03
1/04

5

WE

6

RAS
NC

7

A10
AD
A1
A2
A3
Vee

AD to A1D

8
9
10

1::1::

"11"11

tt

........

"' ....

0",
"'0

...el'"
"'el
'"
",

11
12
13
14

20
19
18
17
16
15

A6

A1

A5
A4
GND

A2
A3
Vee

24

1/05

23

CAS

22

DE

21
20
19

A9
A8
A7

12

18
17

A6
A5

13
14

16
15

A4
GND

"11"11
.... (/1

........

§~

.........
5:

m ...
m

'~

i

:1

i,,'t
:1'

I!"I,

Address Inputs

1/01 to 1/08 : Data Inputs/Outputs
Row Address Strobe
RAS
CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

GND

Power Supply
Ground

NC

No Connection

335

NEe

yPD42S17805L,4217805L

Block Diagram

Clock
Generator

Vee

0---

GNDO---

CAS before
RAS Counter

Q;
"0
0
()



tRAD (MAX.)

and

tACO:::;: tACO (MAX.)

and

tRCO

:$

tACO (MAX.)

tACO> tACO (MAX.)

Access Time

II,

Access Time from RAS

tRAC (MAX.)

tRAC (MAX.)

tAA (MAX.)

tRAD

+

tAA (MAX.)

tCAC (MAK)

tRCo

+

tCAC (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAO <: tRAO (MAX.) and tRCO <: tRCO (MAX.) will not cause
any operation problems.

3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the JlPD42S17805L.
Read Cycle
tAAe
Parameter

= 60

= 70

ns

tRAe

MIN.

MAX.

MIN.

MAX.

ns

-

60

70

ns

1

18

ns

1

35

ns

1

18

ns

Symbol

Unit Notes

tAA

-

30

tOEA

-

15

-

Column Address Lead Time Referenced to RAS

tRAL

30

-

35

tAes

0

-

0

-

ns

Read Command Setup Time
Read Command Hold Time Referenced to RAS

tRRH

0

-

ns

tACH

0

-

0

Read Command Hold Time Referenced to CAS

0

-

ns

2

Output Buffer Turn-off Delay Time from OE

tOEZ

0

13

0

15

ns

3

CAS Hold Time to OE

teHo

5

-

5

-

ns

Access Time from RAS

tRAC

Access Time from CAS

tCAC

Access Time from Column Address
Access Time from OE

15

ns
2

Notes 1. For read cycles, access time is defined as follows:
Input Conditions
tAAD ~ tAAD (MAX.) and tReD
tRAO> tRAD (MAX.)

tACO> tACO (MAX.)

and

~

tReD (MAX.)

tACO:::;: tRCD (MAX.)

Access Time

Access Time from RAS

tRAC (MAX.)

tRAC (MAX.)

tAA (MAX.)

tRAD

+

tAA (MAX.)

tCAC (MAX.)

tRCO

+

tCAC (MAX.)

tRAD(MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD <: tRAD (MAX.) and tRCD <: tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

343

NEe

yPD42S17805L,4217805L

Write Cycle
tRAe

= 60 ns

tRAe

MIN.

MAX.

MIN.

-

10

Symbol

Parameter
WE Hold Time Referenced to CAS

tweH

10

WE Pulse Width

twp

10

WE Lead Time Referenced to RAS

tAWL

10

WE Lead Time Referenced to CAS

tCWL

10

WE Setup Time

twes

0

OE Hold Time

tOEH

0

Data-in Setup Time

tos

0

Data-in Hold Time

tOH

10

= 70 ns

Unit Notes

MAX.
ns

1

ns

1

12

-

12

-

ns

0

-

ns

10

0
0
10

ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
tRAe

= 60 ns

tRAe

MIN.

MAX.

MIN.

MAX.

-

157

37

-

54

-

Symbol

Parameter
Read Modify Write Cycle Time

tRWC

133

RAS to WE Delay Time

tRWD

77

CAS to WE Delay Time

tcWD

32

Column Address to WE Delay Time

tAWD

47

89

= 70 ns

Unit

Note

ns
ns

1

ns

1

ns

1

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD

~

tCWD (MIN.), tAWD

~

tAWD (MIN.) and tCPwD ~ tCPWD (MIN.), the cycle is a read modify write

cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

344

____N__E.=..;C=-_ _ _ _ _ _ _ _ _ _ _ _

- -L:; .JlP:. . . :D: . .4~2=S;. .; ,1.; . 78;:;. .;O=5. .; :L~, 7.; . 80;:;. .;5=L~
4..:. :2;:;. .;1__

_ ___111

II

Hyper Page Mode
IRAC z 60 ns

IRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

tHPC

25

-

3D

-

ns

RAS Pulse Width

tRASP

60

125,000

70

125,000

ns

CAS Pulse Width

Parameter
Read I Write Cycle Time

Symbol

Unit Notes

11

tHCAS

10

10,000

12

10,000

ns

CAS Precharge Time

tcp

10

-

10

-

ns

Access Time from CAS Precharge

tACP

-

35

-

40

ns

CAS Precharge to WE Delay Time

tCPWD

52

59

-

ns

RAS Hold Time from CAS Precharge

tRHCP

35

-

40

-

ns

tHPRWC

66

-

75

ns

1

2

Dala Output Hold Time

tOHC

5

-

5

OE to CAS Hold Time

tOCH

5

-

5

-

OE Precharge Time

tOEP

5

-

5

-

ns

Output Buffer Turn-off Delay from WE

twEZ

0

13

0

15

ns

WE Pulse Width

twpz

10

-

10

-

ns

4

Output Buffer Turn-off Delay from RAS

tOFR

0

13

0

15

ns

3,4

Output Buffer Turn-off Delay from CAS

tOFC

0

13

0

15

ns

3,4

Read Modify Write Cycle Time

ns
ns

4

3,4

Notes 1. tHPC (MIN.) is applied to CAS access.
2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle. If tRWO ~ tAWO (MIN.), tcwo ~ tcwo (MIN.), tAwo ~ tAwo (MIN.) and tcPWO ~ tcPWO (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make 1I0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.

(4)

WE: inactive (in read cycle)

CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

345

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yPD42S17805L,4217805L

Refresh Cycle
Parameter

Symbol

MAX.

-

CAS Setup Time

tesR

5

CAS Hold Time (CAS before RAS Refresh)

teHR

10

RAS Precharge CAS Hold Time

tRPe

5

RAS Pulse Width (CAS before RAS Self Refresh)

tRASS

100

RAS Precharge Time (CAS before RAS Self Refresh)

tRPS

110

CAS Hold Time (CAS before RAS Self Refresh)

teHs

-50

WE Setup Time

tWSR

10

-

WE Hold Time

tWHR

15

-

Note 1. This specification is applied only to the tLPD42S17805L.

346

tRAe = 60 ns
MIN.

tRAe = 70 ns
Unit
MIN.·

MAX.

5

-

10

Note

ns
ns

J1S

1

130

-

ns

1

-50

-

ns

1

10

-

ns

15

-

ns

5
100

ns

'I

-,;i

_____~
__
E_c:=_________________________~y=P~D_4_2~S_1_7~80_5_L~,_42_1_7_8_0_5L______

;J
:\

~

Read Cycle

il

'~'~

IRe
IRP

tRAS

RAS

VrHV1L-

tCSH

CAS

VIH-

VIL-

Address

V,HVIL-

WE

V,HVIL-

OE

V,HVIL-

tOLZ
teLZ

I/O

VOH- .••••••••••••••••••••••• _.~!:.~
VOl-

................................ .

tOFR

Data out

Hi-Z

347

NEe

gPD42S17805L,4217805L

Early Write Cycle
tRe
tRAS

tesH

Address

V,HVIL-

V,HVIL-

1/0

V,HV,L-

Remark OE: Don't care

348

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yPD42S17805L,4217805L

Late Write Cycle
tAC
tRAS

CAS

Address

OE

V,HV,L-

VIH-

V,L-

V,HV,LtOED

1/0

V,H-

~_m~t~m

VIL-~

___ _

349

NEe

yPD42S17805L,4217805L

Read Modify Write Cycle
tRWC
tRAS

V,HV,LtesH

V,HV,L-

Address

V,HV,L-

1/0 VOHVOL-

350

Hi-Z

____~
__E_c:~________________________~y=P~D~4_2~S1_7~8~O~5L~,_4_2~17~8~O~5=L______~I,
:1

Hyper Page Mode Read Cycle
tRASP

RAS

tesH

~
CAS

VIH-

V,L-

tACO

~

J
tRAO

Address

V,HV,L-

WE

V,HV,L-

tHPe
tHCAS

~~
Row

n

Col.

~
~

tHCAS

"--

tASH

~

tHCAS

y--~

Y/

~~

mJl

Col.

~

~
Col.

OE

V,HV,L-

tOFR

:xx:

X
I+-

~~
RRH

\,

////IJ

\\\\\\\\\\~

~

tACP

tM

tAA
teAe

tCAC

'-

tOFC

t~

tACP

'1

~

J

tRAl

~

II

tAP

~

tRHCP

V,HV'L-

I

J//

~

\\ ,\
I'

tRAC

tAA
teAe

1/0

VOHVOL-

~

---------------I:I!:!:.----------~~

I

~
Data out

~

~--<)l

Data out

tOEZ

--{)

Data out

---

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

351

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yPD42517805L,4217805L

Hyper Page Mode Read Cycle (WE Control)
tRASP

RAS

tRHCP

VIH-

V,LtesH

CAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

1/0

VOH-

_______________ l:il:~ _________ _

VOL-

Remark

In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

352

!~

,I;

___N_E_C~_ _ _ _ _ _ _ _ _ _ _ _--C:.:.J1P:.....:D::...4.:..::2:..=S-.:..1-=-78~O:..=5-=Lz....'4.:.:2~1-=-7.=...80~5:..=L:.....-_ _ _
Hyper Page Mode Read Cycle (OE Control)
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~RA~S~P____________________~

RAS VIH- -----,

~

tRHCP

'----

VIltCSH

tRSH

tHPC

tHCAS

V--/J

CAS

I'------4-

~

Address

Q
IASR

~::~

tRAH

tRAl

~

m\>

~

Row

CoLA

I

•.

~I~

~~

CoLS

CoLC

W)

_

~

~O'C

'-

tO'R

'\LX:!L~.l4-ll.-¥)~ ~J........-_

tRAC

tOES

WE

I II1/

~::~I

tOCH

~
DE

VIl-

VOHVOl-

Remark

Hi _Z
-------------------------

\...

/

~
~
liD

~

Ir----

\\\\\\\\\\\

I~

~ Ir----I
~

tcHO

IAcp

1+-__+-t;.::.OC::...H+l

V,H-

\\\\

CAC
IAA

~O

tc:;

~

IAcp

HLJ

~

J
OEA
te

tOEA

~
-..- 1..J2g....

- ___

~

~ I~

~~--- ~

toEl
Data out

'\\\
~

B~--~~

Data out C

--I-!!~~-

In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

353

i

I~

NEe

yPD42S17805L,4217805L

Hyper Page Mode Early Write Cycle

Remarks 1. OE: Don't care
2. In the hyper page mode, read, write and reaa modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

354

~~E~c:=_________________________~g~P~D~4~2~S~1~78~O~5~L~,~42~1~7~8~O~5L~____~i.

_____

Hyper Page Mode Late Write Cycle
tRP

tRASP

tAHCP

tCSH

tHPC

tRSH .

i

.~

I.
Address

WE

V,HVIL-

OE

V,HVIL-

I/O

£

V,HVIL-

r

~,
(

Hi-Z
._---------------

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

355

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yPD42S17805L,4217805L

Hyper Page Mode Read Modify Write Cycle

I/O

Va....
VaL-

I/O

V,HVIL-

Remark In the hyper page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

356

i.~

NEe

Ii
.~

,uPD42517805L, 4217805L

------~~~~------------------------------------~~~~~~~~~~~~~--------~.~

Hyper Page Mode Read and Write Cycle

I!
!.I

:r

~

tRASP

RAS

tAHCP

V,HV,L-

,~

tcSH

CAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

1/0

V,HVIL-

VOHHi - Z
VOL- -- - - - - - - -- - - - - - - - -- - - - - - -- - - - - --

Hi - Z
.............. -_ ........................................
.

tDS

1/0

Remark

tOH

V,HV,l-

In the hyper page mode. read. write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

357

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yPD42S17805L,4217805L

CAS Before RAS Self Refresh Cycle (Only for the JIPD42S17805L)
tRASS

~\\\\\\\\\\\\\\\\\\\\\\\
Remark Address, OE : Don't care

I/O : Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst). the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 2,048 times within a 32 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 2,048 times within a 32 ms interval just before and after setting CAS before RAS self refresh.

(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 JIs), CAS before
RAS refresh cycles will be executed one time.
If 10 JlS < tRAS < 100 JlS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (2,048/128 ms) should be met.
For details, please refer to How to use DRAM User's Manual.

358

,~

,t,

___N_E_C~_____________--L.;..J.lP_D_4_2_S_1_7_8_05_L-",_4_2_1_78_0_5_L_ _ _---::~
'"

CAS Before RAS Refresh Cycle

tRAS

Remark Address, OE: Don't care

110: Hi-Z

RAS Only Refresh Cycle

IRP

tRAS

V,HVIL-

tCRP

V,HVIL-

Address

V,HV,L-

Remark WE, OE: Don't care

1/0: Hi-Z

359

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yPD42S17805L,4217805L

Hidden Refresh Cycle (Read)
tRC

tRC

tRAS

tRAS

V,HRAS VIl-

tRCD

tRSH

tePN

tCHR

CAS V,H-

V,L-

Address

WE

V,HV,L-

OE V,H-

VIl-

teLZ

I/O VOH-

Hi - Z

VOL- ------ --- --- -- -- ---------------------------

360

Data out

',i

I~
___N_E........-.,;;C~_ _ _ _ _ _ _ _ _ _ _ _--'J1~P_D_4_2_S_17_8~O_5---'L,:.-4_2_1_
78_0_5_L_ _ _ _.J

Hidden Refresh Cycle (Write)
tRC
tRAS

RAS

tRC
tRAS

VIH-

VIl-

tCRP

CAS

V'HVIl-

Address

WE

1/0

V'HVIl- .....l>-...l.--l...l....J......l....~'_lo_+--_+-+~q.....l~

V'HV'L-

L...>....................................."'-'''-''' "-_ _ _ _..J

Remark OE: Don't care

361

NEe

yPD42S17805L,4217805L

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)

V,HV,L-

V,HV,L-

V,HVIL-

Remark Address, OE: Don't care

1/0: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
16-bit organization during test mode. Don't care about the input levels of the CAS input AO.
(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Writelread operation
When either a "a" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1 ": Normal write (all memory cells)
Output = "0": Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS I CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

362

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yPD42S17805L, 4217805L

Package Drawings

28PIN PLASTIC TSOP(II) (400 mil)
28

15
detail of lead end

~~---------~----------~-

NOTE
Each lead cente;line is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

18.63 MAX.
1.075 MAX.
1.27 (T.P.)

INCHES
0.734 MAX.
0.043 MAX.
0.050 (T.P.)

0

0.42~g:g~

0.017±0.003

E
F
G
H

0.1±0.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400±O.004

0.8±0.2

0.031~g:gg~

K

0.145~g:m

0.006±0.001

L

0.5±0.1

0.020~g:ggt

M
N

0.21
0.10

0.009
0.004

P

3 0 _30
+ 70

ITEM
A
B
C

MILLIMETERS

70
3 0+
_3 0
S28G5-50-7JD3

363

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yPD42S17805L,4217805L

28 PIN PLASTIC SOJ (400 mil)

15

-+4----------~-----------+-

U

Cl

14

P28LE-400A 1

NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

364

ITEM

MILLIMETERS

INCHES

B

18.67~:~5

0.735~g:g~g

C

10.16

0.400

0

11.18±0.2

0.440~g:gg~

E

1.08±0.15

0.043~g:gg~

F

0.74

0.029

G

3.S±0.2

0.138~g:gg~

H

2.545±0.2

0.100±0.008

I

0.8 MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

0.40±0.10

0.016~g:gg~

N

0.12

0.005

P

9.40±0.20

0.370~g:gg~

Q

0.10

0.004

T

R 0.85

R 0.033

U

0.20~g:6g

O. 008~g:gg~

i,

11

NEe

yPD42S17805L,4217805LI

_ _ _--.-;;.;.;....;;~_ _ _ _ _ _ _ _ _ _ _ _ _ _ ____L=...;::..._.:..~...;..;;.,..::.....::...:...::.?......:..:::..;,...;...,;;...::.....::.~_ _ _~:~

I

,~

1J,

Recommended Soldering Conditions

I

Please consult with our sales offices for soldering conditions of the .uPD42S 17805L, 4217805L.

il
.1

Types of Surface Mount Device
pPD42S17805LG5, 4217805LG5: 28-pin plastic TSOP (H) (400 mil)
.uPD42S17805LLE, 4217805LLE: 28-pin plastic SOJ (400 mil)

365

NEe
[MEMO]

366

yPD42S17805L,4217805L

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

11

_ _ _ _Il_P_D_42_S_16_1_65_L_,_42_1_61_6_5L_1
)

3.3 V OPERATION 16 M-BIT DYNAMIC RAM
1 M-WORD BY 16-BIT, HYPER PAGE MODE(EDO),
BYTE READ/WRITE MODE

:~

Description
The ,uPD42S16165L, 4216165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional hyper page
mode (EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the ,uPD42S16165L can execute CAS before RAS self refresh.
The ,uPD42S16165L, 4216165L are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ.

Features
Hyper page mode (EDO)
1,048,576 words by 16 bits organization
Single +3.3 V ±0.3 V power supply

Power consumption

Part number

Active (MAX.)

Access time
(MAX.)

RfW cycle time
(MIN.)

Hyper page mode
(EDO) cycle time (MIN.)

/lPD42S16165L-A60, 4216165L-A60

396 mW

60 ns

104 ns

25 ns

/lPD42S16165L-A70, 4216165L-A70

360 mW

70 ns

124 ns

30 ns

The ,uPD42S16165L can execute CAS before RAS self refresh
Part number
/lPD42S16165L

Refresh cycle
4,096 cycles I 128 ms

Refresh

Power consumption at standby

CAS before RAS self refresh,

-CAS before RAS refresh,

(MAX.)
0.54 mW
(CMOS level input)

RAS only refresh, Hidden refresh
/lPD4216165L

4,096 cycles I 64 ms

CAS before RAS refresh,
RAS only refresh,

1.8mW
(CMOS level input)

Hidden refresh

The information in this document is subject to change without notice.
Document No. M10075EJ3VODSU1

367

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yPD42S16165L, 4216165L

Ordering Information
Part number

Access time

Package

Refresh

(MAX.)

368

pPD42S16165LG5-A60

60 ns

pPD42S16165LG5-A70

70 ns

pPD42S16165LLE-A60

60 ns

pPD42S16165LLE-A70

70 ns

pPD4216165LG5-A60

60 ns

pP D4216165LG5-A 70

70 ns

pPD4216165LLE-A60

60 ns

pPD4216165LLE-A70

70 ns

50-pin plastic TSOP (II)
(400 mil)

CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh

42-pin plastic SOJ
(400 mil)

Hidden refresh

50-pin plastic TSOP (II)
(400 mil)

CAS before RAS refresh

42-pin plastic SOJ
(400 mil)

RAS only refresh
Hidden refresh

!,
,%

NEe

!,4

yPD42S16165L, 4216165L

"

i. ~

.~

~
"

~

Pin Configurations (Marking Side)

,~

:~

50-pin Plastic TSOP (II) (400 mil)

:~

42-pin Plastic SOJ (400 mil)

i'j

Vee
1101
1/02
1/03
1/04

Vee
1/05
1/06
1/07
1/08

NC

2
3
4
5
6
7
8
9
10
11

1::1::
"CI"CI

cc
..,..,
""'"'"
... cn
"'"'en......

50
49
48
47
46
45
44
43
42
41
40

GND

Vee

1/016

1/01

1/015

1/02

1/014

1/03

1/013

1/04

GND

Vee

1/012

1/05

1/011

1/06

1/010

1/07

1/09

1/08

NC

NC
NC
WE

",

NC
NC
WE

RAS
A11
A10
AO
A1
A2
A3
Vee

15
16
17
18
19
20
21
22
23
24
25

AD to A11

UI",
r-UI
e;)rUle;)
\/I

36
35
34
33
32
31
30
29
28
27
26

NC
LCAS
UCAS
OE

A9
A8
A7
A6
A5

RAS
A11
A10
AO
A1
A2
A3
Vee

10
2
3
4
5
6
7
8
9
1::1::
"CI"CI
10
cc
11
""'"'"
"'cn
",
12
...
UI",
r-UI
13
r-rmr14
m
15
16

..,..,
..."'"' ...

17

18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

,,
I

GND

"

1/016

\

1/015
1/014

i

.~

1/013

,f

GND

I

1/012

;'

1/011
1/010
1/09

NC
LCAS
UCAS
OE

A9
A8
A7
A6
A5
A4
GND

A4

GND

Address Inputs

1/01 to 1/016

Data Inputs/Outputs

RAS

Row Address Strobe

UCAS

Column Address Strobe (upper)

LCAS
WE

Column Address Strobe (lower)
Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

369

NEe

yPD42S16165L,4216165L

Block Diagram
RAS
LCAS
UCAS

Clock Generator

WE

1/01
Vee

0-----

GND 0-----

CAS before
RAS Counter

AO
to
A11

370

Column
Address
Buffer

YO to Y7

1/09
to
1/016
(Upper Byte)

_ _....;.,N....;;,...,;;;E;;...C=-_ _ _ _ _ _ _ _ _ _ _ _ _Jlc; ;P:. . :D; . .4.:. : .2:. ;:S:. . :1~6. .:. .16: . :5:_=L~,. .:.4=_21.:. . :6:. . .:1:. . =6. : . 5=_L_ _ _I.~
'\

¥
Input/Output Pin Functions
The ,uPD42S16165L, 4216165L have input pins RAS, CAS Note, WE, OE, AD to A 11 and input/output pins 1/01
to 1/016.

Pin name
RAS
(Row address strobe)

Input/Output
Input

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It

als~ects the~wing

function.
• CAS before RAS refresh

CAS

CAS activates data input/output circuit by latching column address and

(Column address strobe)

selecting a digit line connected with the sense amplifier.

AO to A11

Address bus.
Input total 20-bit of address signal, upper 12-bit and lower 8-bit in sequence

(Address inputs)

(address multiplex method).
Therefore, one word is selected from 1 ,048,576-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.

--

RAS and CAS are activated.

Each address is taken into the device when
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)

Write control signal.

OE

Read control signal.

(Output enable)

Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.

-- --

-

Write operation is executed by activating RAS, CAS and WE.

--

--

-

Therefore, read operation cannot be executed.
1101 to 1/016

Input/Output

(Data inputs/outputs)

Note

16-bit data bus.
1/01 to 1/016 are used to input/output data.

CAS means UCAS and LCAS.

371

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yPD42S16165L, 4216165L

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.

1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle.

The hyper page mode (EDO) allows both read and write operations during one cycle, but the

performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mode (EDO) Read Cycle
V,HRAS VIL-

VIH----,-+-----t--.
CAS

VIL-

Address V,HVIL-

372

OE

~',:=

1/0

VOL-

!i!

___N_E~C=-_ _ _ _ _ _ _ _ _ _ _ _ _J1=P;....;D;;....4.;..;;;2~S_1...;;..61.;....;6~5=LL....'4...;;..2......;1..;;..6...;...16.;;..;5;..;;:L~_ _-;]
Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

373

NEe

yPD42S16165L,4216165L

Electrical Specifications
CAS means UCAS and LCAS.
All voltages are referenced to GND.
After power up (Vcc

~

VCC(MIN.)), wait more than 100 liS (RAS, CAS inactive) and then, execute eight CAS before

RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Symbol

Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

mA

Power dissipation

Po

1

W

Condition

Operating ambient temperature

TA

a to +70

°C

Storage temperature

T".

-55 to +125

°C

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described In the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

3.0

3.3

3.6

V

High level input voltage

V,H

2.0

Vee + 0.3

V

Low level input voltage

Vil

-0.3

+0.8

V

TA

a

70

°c

Parameter

Symbol

Operating ambient temperature

Capacitance (T A = 25

·c, f = 1 MHz)

Parameter
Input capacitance

Data input/output capacitance

374

Condition

MAX.

Unit

C"

Address

5

pF

C'2

RAS, CAS, WE, OE

7

C,IO

1/0

7

Symbol

Test condition

MIN.

TYP.

pF

1/
1.1

___N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _---t;.;.JlP;,....;D_4_2_S_1_61.....,;6;,.;;.5=L!-,4...;.;;2.....,;1.-;;.6..;;..16.;;....;5;".:;L~_ ____II~

i~

I·'·'

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Operating current

lee1

Test condition

Standby

!,PD42S16165L

lee2

= 60 ns
tRAe = 70 ns

RAS, CAS cycling
tRe

current

MIN.
tRAe

= tRe (MIN.), 10 = 0 mA

RAS only refresh current

lee3

= 0 mA
= 0 mA
RAS, CAS" V,H (MIN.), 10 = 0 mA
RAS, CAS" Vee - 0.2 V, 10 = 0 mA
RAS, CAS" V,H (MIN.), 10

Operating current

Icc.

tRe

(Hyper page mode (EDO))

= tRe (MIN.),

10

= 0 mA

tHPC = tHPC (MIN.), 10

CAS before RAS

lee5

refresh current
ICG6

rnA

RAS cycling
tRe

CAS before RAS

=0

= tRe (MIN.) , 10 = 0 mA

CAS before RAS refresh :

long refresh current

tRe

(4,096 cycles I 128 ms,

Iii

90

mA

1,2,3

i

0.5

l

mA

2.0
0.5

tRAe

RAS ,,; VIL (MAX.), CAS cycling

Notes

0.15

= 60 ns
tRAe = 70 ns
tRAe = 60 ns
tRAe = 70 ns
tRAe = 60 ns
tRAe = 70 ns

RAS cycling, CAS" V,H (MIN.)

.~

Unit

80

RAS, CAS" Vee - 0.2 V, 10

!,PD4216165L

'i
MAX.

90

mA

1,2,3,4

mA

1,2,5

mA

1,2

!,A

1,2

80
110
100
90
80

tRAS"; 1 !,S

220

= 31.3 !,S

RAS, CAS:

only for the !,PD42S16165L)

Vee - 0.2 V ,,; V,H ,,; V,H (MAX.)

o V,,; VIL"; 0.2 V
Standby:
RAS, CAS" Vee - 0.2 V
Address: V,H or VIL
WE, OE: V,H

CAS before RAS

lee7

I

= 0 mA

10

150

!lA

-5

+5

!,A

-5

+5

!,A

RAS, CAS:

2

= 5 ms

self refresh current

tRASS

(only for the !,PD42S16165L)

Vee - 0.2 V ,,; V,H ,,; V,H (MAX.)

o V ,,; V,L ,,; 0.2 V
= 0 mA
V, = 0 to 3.6 V
10

Ii (L)

Input leakage current

All other pins not under test
Output leakage current

10(L)

Vo

=0 V

= 0 to 3.6 V

Output is disabled (Hi-Z)

= -2.0 mA

High level output voltage

VOH

10

Low level output voltage

VOL

10 = +2.0 mA

V

2.4
0.4

V

Notes 1. Icc1, Icc3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS:<;; VIL(MAX.)
and CAS

~

V,H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.

375

NEe

yPD42S16165L, 4216165L

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

(2) Output timing specification

2.0 V ---------------~

VIH (MIN.)

=

VIL (MAX.)

= 0.8

V

·--------3 i
I

iL

I

I

IIi :e

IT= 2 ns

IT = 2 ns

}-

= 2.0

V

VOL (MAX.)

= 0.8

V------~I..._ _ _

I

.,: :..

------=J

VOH (MIN.)

__J

(3) Output load condition
VCC
1,1800
I/O ..---.---~
100 pF

ClI

8700

Common to Read, Write, Read Modify Write Cycle
Parameter

tRAC = 70 ns
MIN.

Unit Notes
MAX.

tRC

104

RAS precharge time

tRP

40

-

CAS precharge time

tCPN

10

-

RAS pulse width

tRAS

60

CAS

Read I Write cycle time

MAX.

50

-

ns

10

-

ns

10,000

70

10,000

ns

124

ns

tCAS

10

10,000

12

10,000

ns

RAS hold time

tASH

10

12

tCSH

40

50

-

ns

CAS hold time

-

RAS to CAS delay time

tACO

14

45

14

52

ns

pulse width

1

ns
2

RAS to column address delay time

tRAD

12

30

12

35

ns

2

CAS to RAS precharge time

teRP

5

5

-

ns

3

Column address hold lime

teAH

10

OE lead time referenced 10 RAS

IOES

a

CAS 10 dala selup time

leLZ

0

OE 10 dala selup lime

loLZ

0

OE to dala delay time

tOED

13

Masked byte wrile hold time referenced 10 RAS

tMRH

a

-

tT

1

50

1

50

ns

tREF

-

128

-

128

ms

-

64

-

64

ms

Row address setup time

IASR

0

Row address hold time

lRAH

10

Column address setup lime

IASC

0

Transition lime (rise and fall)
Refresh time

I IlPD42S16165L
I

376

tRAC = 60 ns
MIN.

Symbol

IlPD4216165L

-

ns

ns

0

-

15

-

ns

0

-

ns

0
10
0
12
0
0

ns
ns
ns
ns

ns

4

!:~

___N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _ _......
yP_D_4_2_S_1_6_16_5_L-<-,_4_21_6_1_6_5_L_ _ _,i
I·j
1

i',r
'i

Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 J1S.

If 10 J1S < tRAS < 100 J1S, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD ~ tRAD (MAX.)

and

tRCD ~ tRCD (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD > tRAD (MAX.)

and

tRCD ~ tRCD (MAX.)

tAA (MAX.)

tRAD

+

tAA (MAX.)

teAC (MAX.)

tRCO

+

teAC (MAK)

tRCD> tRCD (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD

~

tRAD (MAX.) and tRCD

~

tRCD (MAX.) will not cause

any operation problems.
3. tcRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the .uPD42S16165L.
Read Cycle

Parameter

Symbol

= 70 ns

tRAe

= 60 ns

tRAe

MIN.

MAX.

MIN.

MAX.

60

-

70

ns

1

17

-

18

ns

1

30

-

35

ns

1

15

-

18

ns
ns

Access time from OE

tOEA

-

Column address lead time referenced to RAS

tRAL

30

-

35

Read command setup time

tRCS

0

tRRH

0

Read command hold time referenced to CAS

tReH

0

-

0

Read command hold time referenced to RAS

0

-

Output buffer turn-off delay time from OE

tOEZ

0

13

0

CAS hold time to OE

tcHO

5

-

5

Access time from RAS

tRAC

Access time from CAS

tCAC

Access time from column address

tAA

0

Unit Notes

ns
ns

2

ns

2

15

ns

3

-

ns

Notes 1. For read cycles, access time is defined as follows:

Input conditions

Access time

Access time from RAS

tRAD'S tRAD (MAX.)

and

tRCD

$

tRCD (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.)

and

tRCD

'S

tRCD (MAX.)

tAA (MAX.)

tRAD

+

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

tRCD> tRCD (MAX.)

tAA (MAX.)

tRAD (MAX.) and tRCD (MAX,) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD

~

tRCD (MAX.) will not cause

any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

377

NEe

yPD42S16165L,4216165L

Write Cycle
tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

tWCH

10
10

WE lead time referenced to RAS

tRWL

10

WE lead time referenced to CAS

tewL

10

WE setup time

twes

OE hold time

tOEH

-

10

twp

-

Parameter
WE hold time referenced to CAS
WE pulse width

Symbol

Data-in setup time

tos

a
a
a

Data-in hold time

tOH

10

10
12
12

a
a
a
10

Unit Notes
ns

1

ns

1

ns
ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.

2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
Parameter

Symbol

= 70 ns

tRAe

= 60 ns

tRAe

MIN.

MAX.

MIN.

MAX.

-

157

-

ns
ns

1

37

-

ns

1

54

-

ns

1

Read modify write cycle time

tRwe

133

RAS to WE delay time

tRWD

77

CAS to WE delay time

tCWD

32

Column address to WE delay time

IAWO

47

89

Unit

Note

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

378

.!

___
N_E--..,;;C~_ _ _ _ _ _ _ _ _ _ _ _--LJ.l~P-=D-.,;4=2..;:...S..;;....16;....:1-=6..;:...5L=,_4=2~16..;;....1;,...:6...;;.5=L_ _ _-!lj
I ~'

Hyper Page Mode (EDO)

Parameter

Symbol

tRAG

= 60 ns

tRAG

= 70 ns

Unit Notes

MIN.

MAX.

MIN.

MAX.

tHPC

25

-

30

-

ns

RAS pulse width

tRASP

60

25,000

70

125,000

ns

CAS pulse width

tHCAS

10

10,000

12

10,000

ns

tGP

10

-

10

-

ns

Access time from CAS precharge

tACP

-

35

-

40

ns

CAS precharge to WE delay time

tcPWD

52

-

59

-

ns

RAS hold time from CAS precharge

tRHCP

35

-

40

ns

Read I Write cycle time

CAS precharge time

1

2

OE precharge time

tOEP

5

-

5

-

Output buffer turn-off delay from WE

tWEZ

0

13

0

15

ns

WE pulse width

twpz

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFC

0

13

0

15

ns

3,4

Read modify write cycle time

tHPRWC

66

-

75

Data output hold time

tOHC

5

5

OE to CAS hold time

tOCH

5

5

ns
ns
ns

4

ns
3,4

Notes 1. tHPC (MIN.) is applied to CAS access.

2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle. If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEz (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective

specification depends on state of each signal.
(1)

--

--

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tcHO is effective.
CAS, OE: active ...... tacH is effective.

379

NEe

yPD42S16165L,4216165L

Refresh Cycle
Parameter

= 60 ns

tRAe

MAX.

MIN.

MAX.
ns

Unit

Note

CAS setup time

tCSR

5

-

5

CAS hold time (CAS before RAS refresh)

teHR

10

-

10

RAS precharge CAS hold time

tRPe

5

-

5

-

RAS pulse width (CAS before RAS self refresh)

tAASS

100
110

-

-

100
130

-

/1S

tRPS

ns

1
1

CAS hold time (CAS before RAS self refresh)

teHs

-50

-50

1

tWHR

15

-

ns

WE hold time

RAS precharge time (CAS before RAS self refresh)

Note 1. This specification is applied only to the tLPD42S16165L.

380

= 70 ns

tRAe
MIN.

Symbol

-

15

ns
ns

ns

I~

_----:I\I:......::....:E:;;;;;C-=-_ _ _ _ _ _ _ _ _ _ _ _---LJ.1~P...;;;D_4=2S=1..;.,..;6;....;1....;;.6=5L~,_4_2_16_1. ;.,. ;6-.;,.5_L_ _ _t
i

Read Cycle
tRe
tRP

tRAS

RAS

V'HV'LtesH

UCAS
LCAS

Address

WE

OE

V,HVll-

V'HV'L-

V'HVIL-

V,HV,L-

tOLZ
teLZ

U 1/0
L 1/0

VOHVOL-

Hi - Z

tOFR

Data out

Hi - Z

381

NEe

yPD42S16165L,4216165L

Upper Byte Read Cycle
IRe
IRP

tRAS

RAS

V,HV,LleSH

UCAS

V,HV'l-

LCAS

Address

WE

OE

lOll
U 1/0

VOftVOL-

Remark L 1/0: Hi-Z

382

Hi -z

IO'R

IcLz

Dala oul

Hi -Z

it

!i

_ _N;;."".;;...E=..;:C::.....-_ _ _ _ _ _ _ _ _ _ _ _---J,;J.l;.,;,.P~D_4_2~S_16.;,...1....;;6_5_'L,:......4_2_1_6_16_5_L_ _ _ _ ~~
Lower Byte Read Cycle

IRC
IRP

tRAS

RAS

UCAS

LCAS

Address

WE

OE

loLZ

tOFR

leLZ

LIIO

VOHHi-Z
VOl- .----- ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

Dala oul

Hi - Z

Remark U 1/0: Hi·Z

383

NEe

yPD42S16165L,4216t65L

Early Write Cycle
tRe
tRAS

RAS

V'HVIL-

tCSH

UCAS
LCAS

V'HVIL-

Address

V'HVll-

V'HVIL-

U I/O
LI/O

V'HVIL-

Remark OE: Don't care

384

tRP

,:f

_ _,;,...N;;:...E=-...;;C~_ _ _ _ _ _ _ _ _ _ _ _-I:Jl,,-P_D_4_2_S_16_1_6_5L--,,_4_2_1_
61_6_5_L_ _ _

1*
!}

Upper Byte Early Write Cycle

tRC
tRAS

RAS

tRP

V,HVIltcSH

UCAS

VII-!VIl-

LCAS

V,HVIl-

Address

V,H-

V'L-

WE

UI/O

Remark OE, L I/O: Don't care

385

NEe

gPD42S16165L,4216165L

Lower Byte Early Write Cycle

tRC
tRAS

Address

L I/O

V,H-

VIL-

V,HVIL-

Remark OE, U I/O: Don't care

386

tRP

_ _N_E_C~_ _ _ _ _ _ _ _ _ _ _ _-L.J.1_P_D_4_2S_1_6_1_65_L....<.,_4_2_16_1_6_5_L_ _ _,!
Late Write Cycle

tRe
tRAS

UCAS
LCAS

V'HVIL-

Address V'HVIL-

tOEH

V,HV,L-

1-............L-L-f....J

tOED

UI/O
LifO

387

NEe

yPD42S16165L,4216165L

Upper Byte Late Write Cycle

lAC
lAP

tRAS

RAS

V'HVILICSH
tACO

tRSH

teAs

UCAS

V,HVIL-

LCAS

V,H-

Address VIL-

WE

OE

tOH

U 1/0

'tlf) ------ -~! :-~- --- ---

Remark L I/O: Don't care

388

Data in

:!
_ _N_E---.;;C~_ _ _ _ _ _ _ _ _ _ _ _--L.Jl_P_D_4_2S_1_6_1_6_5--,L,,--4_2_1_6_16_5_L_ _ _ _

I

Lower Byte Late Write Cycle

IRe
IRP

tRAS

RAS

V,HVILtMRH

UCAS

VIH-

VIL\cSH
tRCO

LCAS

V,HVIL-

Address

V,HVIL-

tRSH
tCAS

WE

OE

IOH

Lila

ZZZ/-------!:i:-?-------

Dalain

Remark U I/O: Don't care

389

NEe

yPD42S16165L, 4216165L

Read Modify Write Cycle

IRWC
IRAS
VII+V'L-

ICSH
IRCO
UCAS
LCAS

V,HV'L-

Address

V'HV'L-

IRSH

Icwo
WE

V,HV,L-

tOEH

tOEA

OE

V'HV'L-

ICAC
U 1/0

L 1/0

V,HV'L-

~---------

los

IOH
Oalain

IOLZ

UIIO

L 1/0

390

VOHVOL-

Hi-Z

Hi-Z

,

____~~E=c:~________________________~y~P~D~4=2S~1~6~1~6~5L~,~4=2~16~1~6~5=L______~~
I,,!:

Upper Byte Read Modify Write Cycle

IAwe
tRP

tRAS

RAS
tesH
tACO

UCAS

LCAS

Address

WE

tRSH

teAs

V'HVIl-

V,>+Vll-

V,>+VIl-

V,>+VIl-

OE

()()()()()(X)---.......... --.... .

UI/O

UI/O

Vo>+- .... _.. _..................................
Hi-Z
- .. - .. - .. - .... -- .. -

Hi - Z

voL-

Remark In this cycle, the input data to Lower 110 is ineffective. The data out of that remains Hi-Z.

391

NEe

yPD42S16165L,4216165L

Lower Byte Read Modify Write Cycle

tRP

Address

WE

V,HVIL-

LIIO

LIIO

Remark

392

~ .. -- .. -... -.-------

VOH- .............................. - Hi-Z
.................... - .... -.- .... - ..
VOl-

Hi-Z

In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi-Z.

,

i,~

_____~__IE_c:
____________________________~y~P_D_4_2_S_1_6_1_65_L~,_4_2_1_61_6_5_L______~~
I ~ii

Hyper Page Mode (EDO) Read Cycle

IR ASP

RAS

~
VIHVll-

VIl-

tHCAS

~

~

tHCAS

r---I

111
tRAL

~e5H ~

VIH-

~
,..---.

tHCAS

~

J

tRSH

tHPC

tRCO

~

Address

'-

VIL-

tCSH

UCAS
LCAS

~

tAHCP

VIH-

~
11111;

n 1---0

Dala oul

tOEZ

~--<}

Dala oul

~---

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

393

NEe

yPD42S16165L,4216165L

Hyper Page Mode (EDO) Byte Read Cycle

~

tAASP
tRHCP

tHPC

tCSH

UCAS

LCAS

V,HVIL-

V,HVIL-

~

-'

WE

V,HVIL-

V'HVIL-

Y
~

I~

~~
Row

tHCAS

~
~

t~W
111111 I

I~

~

9-

~ ~
Col.

~}

'--

/
tMRH

tOFR

tRAL

Col.

'----

.

tRSH
tHCAS

tHCAS

1\\

~

-'

Address

tRCD

~

~

XXX

Col.

~

xx=:
~
tOFC

~

RRH

\

LXtWEZ

OE V'HVIL-

\ \ \ \ \\\ \ \ \
1

U I/O

~~:~

I_~
tOEA.

tACP

tAA

tAA
tGAG

\\~
tRAG
lAA
tGAG

~~

tACP

~

/

\\ \

~
tOHC

.-

tOEZ

~

_______________~i_-_~ _________ ~

Data out

--- ..

------0

--------

Data out

--

tDHG
+-+

L 1/0

~~:

- - - - - - - - - - - - - - - - ~~: ~- - - - - - - - - - -- - - - - - - - - - - - - --1 ~

Data out

-- -------_ ........ -- ----

--

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

394

I,

I~

I
NEe
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--L../1;.....P_D_4_2_S_1_6_16..;,...5_L-<.,_4_2_1_6_1..;,..6_5L
_ _ _ _t

,

"i
1
l'

~

Hyper Page Mode (EDO) Read Cycle (WE Control)

!1

:t

tRASP

RAS

'I

tRHCP

V,HVIltCSH
tHCAS
VIH-

UCAS
LeAS

VIl-

Address

V,HV,l-

WE

V,HVIl-

OE

VIl-

VIH-

U 1/0

LIIO

VOHVOl-

••••••••••••••• I:I!:.~ ......... .

Data out

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

395

NEe

yPD42S16165L,4216165L

Hyper Page Mode (EDO) Read Cycle (OE Control)

~

tRASP

---,

RAS V,HVIL-

tRHCP

ICSH

~

UCAS V,HLCAS VIL-

-'

WE

V,HVIL-

~

m~

~
CoLA

I
IR~

VDl-

JOO( )

lOCH

~

\.- f--

-----------~~!----------- ~~

Ic~

1-1"-

----

~

\.-

H
IDFR

~fH

...

IRRH

\\\\

ICHD

tACP

,--,

~

IDES
CAC
IAA

I-

/
~

CoLC

1M

ICHD

\\\\\\\\\\\

)

...

I~ ~

~
tecH

~
VDH-

COLBm

~

tOEA

U I/O
L I/O

~~

IRAC
IAA

iLllil

~::=

V /
IRAl

1--+
OE

tHCAS

~

~

VIL-

I~
.....-.

tHCAS

r---:.

\\

RO;'~

Address V,H-

~

IHCAS

tRCD

'-

tASH

tHPC

IAcp

~~
~
~

~

I~
~
~

V
DEA
IDEl

\\\\

~

~ Data out B~--- ~ Data out B --1J ~a ~t C

--fjj~~-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

396

!

N~
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _y'-P_D_4_2_S_1_6_1_65_L-<.,_4_2_1_61_6_5_L_____,'I1
:!

Hyper Page Mode (EDO) Early Write Cycle

UCAS
LCAS

V,I+V'L-

Address V'HVtL-

V'HV'L-

UIIO
L 1/0

V,I+Vll-

L..JL.....K..........'-"-.>f

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

397

NEe

yPD42S16165L,4216165L

Hyper Page Mode (EDO) Byte Early Write Cycle

tRASP
tRHCP

U 1/0 V,>+VIl-

V,>+LlIO VIl-

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

398

'l

NEe

______

~~~~

__________________________________

yPD42S16165L, 4216165L

_c_~~~~~~~~~~~~

.~

_________

~

,~
~

Hyper Page Mode (EDO) Late Write Cycle

'~
i,'~

I~
,~

tAHCP

V'HVILtCSH

UCAS
LCAS

'~-'

tRP

tAASP

RAS

tHPC

tASH

V'HVIL-

Address

V'HVIL-

WE

V'H-'
VIL-

OE

V'HVIL-

U I/O
L I/O

V'HVIL-

Hi-Z
._---------------

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

399

NEe

yPD42S16165L,4216165L

Hyper Page Mode CEDO) Byte Late Write Cycle

tRASP

tAHCP

RAS

V,HVILtHpc

tCSH
tHCAS

UCAS

V'HVIL-

LCAS

V,HVIL-

tRSH
tHCAS

tePN

tMAH

Address V,HVIL-

V,HVIL- L-t......l:....J..-L..J

U I/O

VIH-

VIL-

L 110

V'H- ______ tlJ:.~ ________ _
VIL-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

400

_____~_E~c:=_________________________~H~P~D~4~2~S~16~1~6~5~L,~4~2~1~6~16~5~L~____~!1
,

; I,!

Hyper Page Mode (EDO) Read Modify Write Cycle

V,H-

RAS

VIl-

V,HVIl-

UCAS
LCAS

Address

VIH-

VIl-

WE

OE

U 110
L 1/0

VOHVOL-

U 1/0
L 110

V,HVIl-

Remark In the hyper page mode (EDO), read,write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

401

NEe

yPD42S16165L,4216165L

Hyper Page Mode CEDO) Byte Read Modify Write Cycle

tRP

tRMP

tHPRWC
tHCAS

LeAS

tHCAS

V'HV1L-

tRAL

Address

V'HVIl-

WE V,HVIl- .......'--'~+...J

-Z
--_Hi...........................

U 1/0

L 1/0 VOHVOlV,HU 1/0 VIl-

L 1/0 V,HVIl-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

402

,

___N_E_C"'"--_ _ _ _ _ _ _ _ _ _ _ _- - 'J1I:.:.,;P:. . .; D~4.;.:;2; . .;:S. .:.1. .: . .6~16:. . ; 5;.; ;L~,. . ;,.42:; ;:. .1:. . ; 6;,. ;.1. .; .6. ; . .5L~_ _ _!~
Hyper Page Mode (EDO) Read and Write Cycle

tRASP

RAS

tAHCP

V,HVILtCSH

UCAS
LCAS

V,HVIL-

Address

V,HVIL-

WE

OE

U 1/0
L 1/0

V,HV1L-

V,HVIL-

VOHHi - Z
VOL- ---- ••••••••••••••••••••••••••••

I

Hi-Z
---.--- .... --------.. -- --------.

I

U 1/0

LIIO

Remark

In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

403

NEe

gPD42S16165L,4216165L

CAS Before RAS Self Refresh Cycle (Only for the ,uPD42S16165L)
tRASS

RAS

UCAS
LCAS

Remark Address, WE, OE: Don't care

L 110, U 110: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 4,096 times within a 64 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 4,096 times within a 64 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 ,us), CAS before
RAS refresh cycles will be executed one time.
If 10 ,us < tRAS < 100 ,us, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (4,096/128 ms) should be met.
For details, please refer to How to use DRAM User's Manual.

404

NEe

Ii

,uPD42S16165L, 4216165L

------~~~~~--------------------------------------~~~~~~~~~~~~~~~--------~~i

I'

,5.

CAS Before RAS Refresh Cycle

tRAS

RAS

V,ftV,ltesR

UCAS
LCAS

tCHR

V,HV,l-

Remark Address, WE, OE: Don't care

L I/O, U I/O: Hi-Z

RAS Only Refresh Cycle

tRAS

RAS

tRP

tRAS

V'HV'l-

teRP

UCAS V,HLCAS V'l-

Address V'HV'l-

Remark WE, OE: Don't care

L I/O, U I/O: Hi-Z

405

NEe

yPD42S16165L,4216165L

Hidden Refresh Cycle (Read)

IRC
tRAS

IRC
tRAS

V,I+RAS V'l-

UCAS V,HLCAS V,l-

Address V,I+V,l-

WE

DE V,I+V'l-

U 110 VOl+- __________________ !:'l:.?____________________ _
L 110 VOL-

406

Dalaoul

Hi - Z

I~

___N_E-...;;C~_ _ _ _ _ _ _ _ _ _ _ _--,J.l!;.;...P_D_4_2_S_16_1_6_5.......
L,,--4_2_1_
6_16_5_L_ _ _---'li,~*
Hidden Refresh Cycle (Write)

IRe

IRe
tRAS

tRAS

,I

UCAS V'HLCAS VIL-

~

""Iii,,_
Address

V'HV'l-

twes

WE

V'HV'l-

U 1/0
L110

V'HV'l-

tweH

L..l........................."'-'............~ .._ _ _ _...J' "-"-'......'-JL............." - '.......'-JL..................................-&..............................' - '

I'"

:~

Remark OE: Don't care

407

NEe

yPD42S16165L,4216165L

Package Drawings

50PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

-r~----------~------------~

H

~~

;

;~.

J

L

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A

21.17 MAX.
1.0 MAX.
0.6 (T.P.)

0.634 MAX.
0.040 MAX.
0.031 (T.P.)

0.32~8:8~

0.013±0.003

0.HO.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.046 MAX.
0.036
0.463±O.006
0.400±0.OO4

B
C
D

E
F

G
H
I

K

M
N
P

0.6±0.2

0.031 ~8:88~

0.145~8:m

0.006±0.001

0.5±0.1

0.020~8:88t

0.13
0.10
30+ 70
-3°

0.005
0.004
30+ 70
-3°
S50G5-80-7JF4

408

N_E~c:=_________________________~y~P~D~4=2=S~1~61~6~5~L~,~42~1~6_1~65~L~____~';

_____

42 PIN PLASTIC SOJ (400

mill

11

l

"\

!~
1,1,

B

22

-++-------------~-------------1-

u

0

P42LE-400A

NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

ITEM
B

MILLIMETERS
27 .56~gj5

INCHES
1 . 085":.gg~~

C

10.16

0.400

0

11.lS±0.2

0.440±0.00S

E

1.0S±0.15

0043~ggg~

F

0.74

0.029

G

3.5±0.2

0.13S±0.00S

H

2.545±0.2

0.100±0.00S

I

O.S MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

0.40±0.10

0.016 ... ggg~

N

0.12

0.005

P

9.4±0.20

0.370±0.00S

Q

0.10

0.004

T

R 0.S5

R 0.033

U

0.20~g6g

O.oos:.gggi

409

NEe

gPD42S16165L,4216165L

Recommended Soldering Conditions
The following conditions must be met for soldering conditions of the tLPD42S16165L, 4216165L.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
tLPD42S16165LG5,4216165LG5: 50-pin plastic TSOP (II) (400 mil)
Soldering process

Soldering conditions

Symbol

Infrared ray reflow

Peak temperature of package surface: 235 'C or lower,
Reflow time: 30 seconds or less (210 'C or higher),
Number of rellow processes: MAX. 2
Exposure limit: 7 days""·
(10 hours pre-baking is required at 125 'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).

IR35-107-2

VPS

Peak temperature of package: 215 'C or lower,
Reflow time: 40 seconds or less (200 'C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 days""·
(10 hours pre-baking is required at 125 'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).

VP15-107-2

Partial heating method

Terminal temperature: 300 'C or lower,
Time: 3 seconds or lower (Per side of the package).

Note

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25°C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

tLPD42S16165LLE,4216165LLE: 42-pin plastic SOJ (400 mil)
Please consult with our sales offices for soldering conditions of the tLPD42S16165LLE, 4216165LLE.

410

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD42S18165L,4218165L;ij
____________________________
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
1 M-WORD BY 16-BIT, HYPER PAGE MODE (EDO),
BYTE READ/WRITE MODE

Description
The ,uPD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional hyper page
mode (EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the ,uPD42S18165L can execute CAS before RAS self refresh.
The ,uPD42S18165L, 4218165L are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ.

Features
Hyper page mode (EDO)
1,048,576 words by 16 bits organization
Single +3.3 V ±0.3 V power supply

Power consumption
Active (MAX.)

Part number

Access time
(MAX.)

RIW cycle time
(MIN.)

Hyper page mode (EDO)
cycle time (MIN.)

/IPD42S18165L-A60, 4218165L-A60

540 mW

60 ns

104 ns

25 ns

/IPD42S18165L-A70, 4218165L-A70

504 mW

70 ns

124 ns

30 ns

The ,uPD42S18165L can execute CAS before RAS self refresh
Part number
/IPD42S18165L

Refresh cycle
1,024 cycles 1128 ms

Refresh

Power consumption at standby

CAS before RAS self refresh,
CAS before RAS refresh,

(MAX.)
0.54 mW
(CMOS level input)

RAS only refresh, Hidden refresh
/IPD4218165L

1,024 cycles 1 16 ms

CAS before RAS refresh,
RAS only refresh,
Hidden refresh

1.8mW
(CMOS level input)

The information in this document is subject to change without notice.
Document No. Mt0562EJ6VODSUt

411

NEe

yPD42S18165L,4218165L

Ordering Information
Part number

Access time

Package

Refresh

(MAX.)

412

/lPD42S 18165LG5-A60

60 ns

/lPD42S 18165LG5-A70

70 ns

/lPD42S 18165LLE-A60

60 ns

/lPD42S 18165LLE-A70

70 ns

/lPD4218165LG5-A60

60 ns

/lPD4218165LG5-A70

70 ns

/lPD4218165LLE-A60

60 ns

/lPD4218165LLE-A70

70 ns

50-pin plastic TSOP (II)
(400 mil)
42-pin plastic SOJ
(400 mil)
50-pin plastic TSOP (0)
(400 mil)
42-pin plastic SOJ
(400 mil)

CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

NEe

yPD42S18165L, 4218165L

Pin Configurations (Marking Side)

Vee
1/01
1/02
1/03
1/04

Vee
1/05
1/06
1/07
1/08

NC

2
3
4
5
6
7
8
9
10
11

..,..,
"'11"'11

CC

50
49
48
47
46
45
44
43
42
41
40

GND
1/016
1/015
1/014

15
16

WE

17

RAS
NC
NC
AD
A1
A2
A3

18
19
20
21
22
23
24
25

Vee

AD to A9

1/02
1/03
1/04

GND

Vee

1/012

1/05

1/011

1/06

1/010

1/07

1/09

1/08

NC

NC
NC

...

WE

1""",
"''''
ell""

RAS
NC
NC
AD
A1
A2
A3

"'... ...'"

NC
NC

Vee

1/01

1/013

tt
"'111
",

",el

'"

36
35
34
33
32
31
30
29
28
27
26

"I
!

42-pin Plastic SOJ (400 mil)

50-pin Plastic TSOP (II) (400 mil)

NC
LCAS
UCAS
OE

A9
A8
A7
A6
A5
A4
GND

Vee

10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

18
19
20
21

..,..,
"'11"'11

cc
........

"'111
"'"''''
... ...
"' ...
"''''
ml""
",

1""",
1""1""

m

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

GND
1/016
1/015
1/014
1/013

GND
1/012
1/011
1/010
1/09

NC
LCAS
UCAS
OE

A9
A8
A7
A6
A5
A4

GND

Address Inputs

1/01 to 1/016

Data Inputs/Outputs

RAS

Row Address Strobe

UCAS

Column Address Strobe (upper)

LCAS
WE

Column Address Strobe (lower)
Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

413

NEe

yPD42S18165L, 4218165L

Block Diagram

Clock Generator

0---

Vee

GND 0---

CAS before
RAS Counter

Memory
Cell
Array
XO to X9

AO
to
A9

414

Column
Address
Buffer

YO to Y9

1/09

NEe

II.'.~

,uPD42S18165L, 4218165L

------~~~~~---------------------------------------------c~~~~~~~~~~~~~~~----------~'ill

1('

Input/Output Pin Functions
The ,uPD42S18165L, 4218165L have input pins RAS, CASNo'., WE, OE, AD to A9 and input/output pins 1/01 to

1/016.

Pin name
RAS

Input/Output
Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS

CAS activates data input/output circuit by latching column address and

(Column address strobe)

selecting a digit line connected with the sense amplifier.

AO to A9

Address bus.

(Address inputs)

Input total 20-bit of address signal, upper 10-bit and lower 10-bit in sequence
(address multiplex method).
Therefore, one word is selected from I,048,576-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.

WE

Write control signal.

(Write enable)

Write operation is executed by activating RAS, CAS and WE.

----

--

OE

Read control signal.

(Output enable)

Read operation can be executed by activating RAS, CAS and OE.

I! WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/016

Input/Output

(Data inputsloutputs)

Note

16-bit data bus.

1/01 to 1/016 are used to input/output data.

CAS means UCAS and LCAS.

415

NEe

yPD42S18165L, 4218165L

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.

1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle, but the
performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mode (EDO) Read Cycle
RAS

CAS

Address

0::~

V,H- -~-+---+"'

VIL-

V,H-

VIL-

WE V,H-

VIL-

V,H-

OE VIL-

I/O VOHVOL-

416

.......'-'-'-...t......1

___N_E_C
_______________J.l......P_D_4_2_S_1_8_16_5_L......, _42_1_8_1_6_5L_ _ _--.,'1
ff~
f~
',(1

Cautions when using the hyper page mode (EDO)

'W
f~

1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.

,.~

i,:j
I"',

(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...

f.

tWEZ and twpz are effective.

3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..

f

••

tOCH is effective.

417

NEe

yPD42S18165L,4218165L

Electrical Specifications
CAS means UCAS and LCAS.
All voltages are referenced to GND.
After power up (Vcc

~

VCC(MIN.»), wait more than 100 JIs (RAS, CAS inactive) and then, execute eight CAS

before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter

Symbol

Condition

Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

mA

Power dissipation

Po

1

W

Operating ambient temperature

T.

o to +70

°C

Storage temperature

Tstg

-55 to +125

°C

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthisspecification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
Parameter

Condition

MIN.

TYP.

MAX.

Unit

3.0

3.3

3.6

V

2.0

Vee + 0.3

V

-0.3

+0.8

V

70

°C

Vee

High level input voltage

V,H

Low level input voltage

V,l

Operating ambient temperature

T.

0

Capacitance (TA

=25 'c, f =1 MHz)

Parameter
Input capacitance

Data input/output capacitance

418

Symbol

Supply voltage

Test condition

MAX.

Unit

C"

Address

5

pF

C'2

RAS, CAS, WE, OE

7

CliO

1/0

7

Symbol

MIN.

TYP.

pF

;;'

____~~~E~c:=__________________________ycP~D~4~2~S~1~81~6~5=l~,4~2~1~8~16~5~l~____~i~
DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Operating current

Standby

ICC1

lee2

IIPD42S18165L

current
IIPD4218165L

RAS only refresh current

IcC3

Operating current

Icc<

(Hyper page mode (EDO))

MAX.

Unit

Notes

RAS, CAS cycling

Test condition
tRAe = 60 ns

150

mA

1,2,3

tRe = tRe (M'N.), 10 = 0 mA

tRAe = 70 ns

140

RAS, CAS ~ V'H (M'N.), 10 = 0 mA

lee5

refresh current
CAS before RAS

lee6

long refresh current

0.5

RAS, CAS ~ Vee - 0.2 V, 10 = 0 mA

0.15

RAS, CAS ~ V'H (M'N.), 10 = 0 mA

2.0

RAS, CAS ~ Vee - 0.2 V, 10 = 0 mA

0.5

RAS cycling, CAS ~ V'H (M'N.)

tRAe = 60 ns

150

tRe = tRe (M'N.), 10 = 0 mA

tRAe = 70 ns

140

RAS s V'l (MAX.), CAS cycling

tRAe = 60 ns

110

tRAe = 70 ns

100

RAS cycling

tRAe = 60 ns

150

tAe = tRe (M'N.) , 10 = 0 mA

tRAe = 70 ns

140

CAS before RAS refresh :

tRAS S 1 liS

h-lPC

CAS before RAS

MIN.

= tHPC (MIN.),

10

= 0 rnA

mA

mA

1,2,3,4

mA

1,2,5

mA

1,2

180

IIA

1,2

150

IIA

2

-5

+5

J1A

-5

+5

J1A

tRe = 125.0 liS

(1,024 cycles I 128 ms,

RAS, CAS:

only for the IIPD42S18165L)

Vee - 0.2 V s V'H S V'H (MAX.)

o V S V'l s 0.2 V
Standby:
RAS, CAS ~ Vee - 0.2 V
Address: V'H or V'l
WE, OE: V'H
10= 0 mA
CAS before RAS

lee7

RAS, CAS:

self refresh current

tRASS = 5 ms

(only for the IIPD42S18165L)

Vee - 0.2 V s V'H S V 'H (MAX.)

o V S V'l S 0.2 V
10 = 0 mA
Input leakage current

Ii(l)

V, = 0 to 3.6 V
All other pins not under test = 0 V

10(l)

Output leakage current

Vo = 0 to 3.6 V
Output is disabled (H i-Z)

High level output voltage

VOH

10 = -2.0 mA

Low level output voltage

VOL

10 = +2.0 mA

2.4

V
0.4

V

Notes 1. Icc1, Icc3, Icc4, Icc5 and Icc6 depend on cycle rates (tAC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS ::; VIL (MAX.)
and CAS;:: VIH

(M(N.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.

419

NEe

yPD42S18165L,4218165L

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

(2) Output timing specification

VIH (MIN.)

= 2.0 V ---------------~

VIL (MAX.)

= 0.8

V

iL

.--------:3-!
,

.:

'

I

VOH (MIN.) =

2.0 V

--hh=J

}-

VOL (MAX.) =

0.8 V

.-----~'__ _ _ ___'

I

~: rei

:..

IT= 2 ns

IT = 2 ns

(3) Output load condition

Common to Read, Write, Read Modify Write Cycle
tRAe
Parameter

Symbol
MIN.

tRAe

= 70 ns

MAX.

MIN.

MAX.

Unit Notes

Read I Write cycle time

tRe

104

-

124

RAS precharge time
CAS precharge time

tRP

40

-

50

-

tePN

10

-

10

-

ns

RAS pulse width

tRAS

60

10,000

70

10,000

ns

CAS pulse width

teAS

10

10,000

12

10,000

ns

RAS hold time

tRSH

10

12

tesH

40

50

-

ns

CAS hold time

-

RAS to CAS delay time

tReD

14

45

14

52

ns

2

ns
ns

1

ns

RAS to column address delay time

tRAD

12

30

12

35

ns

2

CAS to RAS precharge time

teRP

5

5

-

ns

3

Row address setup time

tASR

a

a

-

ns

Row address hold time

tRAH

10

-

10

Column address setup time

tAse

a

-

a

-

Column address hold time

tCAH

10

12

-

DE lead time referenced to RAS

tOES

CAS to data setup·time

tell

DE to data setup time

tall

a
a
a

-

DE to data delay time

tOED

13

Masked byte write hold time referenced to RAS

tMRH

Transition time (rise and fall)
Refresh time

I
I

420

= 60 ns

/lPD42S18165L
/lPD4218165L

a
a
a

ns
ns
ns

15

a

-

a

-

IT

1

50

1

50

ns

tREF

-

128

-

128

ms

16

-

16

ms

-

ns
ns
ns
ns
ns

4

I.'

;

NEe

!~

yPD42S18165L,4218165L

________________________________________________________________L -________________~________________________~~

Notes 1. In CAS before RAS refresh cycles, tRAS(MAX) is 100 fJS.
If 10 fJS < tRAS < 100 fJS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions
$; tRAQ (MAX.)

and

tRAD> tRAD (MAX.)

and

tRAQ

tACO

$

tRCD

$ tRCO (MAX.)

tRCO (MAX.)

tRCO> tRCD (MAX.)

Access time

Access time from RAS

tRAG (MAX.)

tRAC (MAX.)

tAA (MAX.)

tRAQ

+

tCAC (MAX.)

tRCD

+ tCAC (MAX.)

tM (MAX.)

tAAD(MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD '" tRAD (MAX.) and tRCD '" tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the jlPD42S18165L.

Read Cycle
Parameter

tRAC

= 60 ns

tRAC

MIN.

MAX.

MIN.

MAX.

Symbol

= 70 ns

Unit Notes

Access time from RAS

tRAC

-

60

-

70

ns

1

Access time from CAS

tCAC

-

17

18

ns

1

Access time from column address

tAA

-

30

35

ns

1

Access time from OE

tOEA

-

15

-

18

ns

Column address lead time referenced to RAS

tRAL

30

-

35

Read command setup time

tRCS

0

0

-

ns

Read command hold time referenced to i"iAS

tARH

0

0

-

ns

2

ns

Read command hold time referenced to CAS

tRCH

0

-

0

-

ns

2

Output buffer turn-off delay time from OE

tOEZ

0

13

0

15

ns

3

CAS hold time to OE

tCHO

5

-

5

-

ns

Notes 1. For read cycles, access time is defined as follows:
Input conditions
$

and

$; tRCO (MAX.)

Access time

Access time from RAS

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.) and tRCD $ tRCD (MAX.)

tM (MAX.)

tRAQ

+ tAA (MAX.)

tRCD > tRCD (MAX.)

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

tRAQ

tRAQ (MAX.)

tRCO

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD '" tRAD (MAX.) and tRCD '" tACD (MAX.) will not cause
any operation problems.

2. Either tACH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

421

NEe

yPD42S18165L,4218165L

Write Cycle
Parameter

Symbol

tRAe

= 60 ns

tRAe

= 70 ns

Unit Notes

MIN.

MAX.

MIN.

MAX.

tWCH

10

-

10

-

ns

1

WE pulse width

twp

10

1

10

WE lead time referenced to CAS

tewL

10

-

12

WE setup time

twes

0

-

0

-

ns

tRWL

-

10

WE lead time referenced to RAS

WE hold time referenced to ~

12

ns
ns
ns

2

OE hold time

tOEH

0

-

0

-

ns

Data-in setup time

tDS

0

0

-

ns

3

Data-in hold time

tDH

10

-

10

-

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH (MIN.) should
be met.
2. If twcs ;;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter

Symbol

tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

133

157

-

ns

89

Unit Note

RAS to WE delay time

tRWD

77

-

1

tewD

32

-

37

-

ns

~ to WE delay time

ns

1

Column address to WE delay time

tAWD

47

-

54

-

ns

1

Read modify write cycle time

tRwe

NOle 1. If twcs;;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD;;:: tRWD (MIN.), tCWD ;;:: tCWD (MIN.), tAWD;;:: tAWD (MIN.) and tCPWD ;;:: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

422

ji

___N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _----'J.1=P_D~4_2._;:.S_1..;...8_16;;...:5~LJ_,_42_1....,;8..;,..1...;;,.6..;;...5L_______:I,
Hyper Page Mode (EDO)
Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

MIN.

MIN.

MAX.

Unit Notes

Read I Write cycle time

IHpc

25

30

-

ns

RAS pulse width

tRASP

60

25,000

70

125,000

ns

CAS pulse width

tHCAS

10

10,000

12

10,000

ns

tcp

10

-

10

-

ns

Access time from CAS precharge

tACP

-

35

-

40

ns

CAS precharge to WE delay time

tcpwo

52

59

ns

RAS hold time from CAS precharge

tRHCP

35

tHPRWC

66

5

15

ns

CAS precharge time

-

MAX.

Data output hold time

tOHC

5

OE to CAS hold time

tOCH

5

OE precharge time

tOEP

5

-

Output buffer turn-off delay from WE

tWEZ

0

13

0

Read modify write cycle time

40
75
5
5

1

2

ns
ns
ns
ns

4

ns
3,4

WE pulse width

twpz

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFC

0

13

0

15

ns

3,4

Notes 1. tHPC (MIN.) is applied to CAS access.
2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle. If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAwD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.

3. tOFC (MAX.), tOFR (MAX.) and twEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make 1/05 to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2)

Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

423

NEe

yPD42S18165L, 4218165L

Refresh Cycle
tRAe = 60 ns
Parameter

Unit
MIN.

MAX.

MIN.

MAX.

-

CAS selup lime

leSR

5

-

5

CAS hold lime (CAS before RAS refresh)

leHR

10

-

10

RAS precharge CAS hold lime

IRPe

5

-

5

IRASS

100

-

100

tRPS

110

130

CAS hold lime (CAS before RAS self refresh)

tCHS

-50

-

wr:. hold lime

tWHR

15

-

RAS pulse widlh (CAS before RAS self refresh)

RAS

precharge lime

(CAS

before

l'iAS self refresh)

Note 1. This specification is applied only to the IlPD42S18165L.

424

tRAe = 70 ns

Symbol

Note

ns
ns
ns
jlS

1

ns

1

-50

-

ns

1

15

-

ns

NEe
,uPD42S18165L,4218165L
1\
-----.,;-..;;;.....;;;;..=-----------------""""'------_..:.-_--------;}
Read Cycle
tRe
tRP

tRAS

RAS

V,HVIL-

tCSH

UCAS
LCAS

V,HVIL-

Address

V,HVIL-

WE

V,HVIL-

OE

V,HV,L-

tOLZ
teLZ

U 1/0

L 1/0

VOHHi - Z
VOL- .-- •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

tOFR

Data out

Hi - Z

425

NEe

yPD42S18165L,4218165L

Upper Byte Read Cycle
IRC
IRP

IRAS

RAS

Address

OE

loLZ

IO'R

IcLZ

U 1/0

VOHVOl-

Remark L I/O: Hi-Z

426

Hi -Z

Dala oul

Hi -Z

,I

__----:.....::...=-=-________________
NEe

~

yPD42S18165L, 4218165L _ _ _ _it

----I;.::.....;~~...:...;:...:...;:...;;..;;;..L.....~~;....;;...;;...;;;...

,~

Lower Byte Read Cycle
tRC
tRP

tRAS

RAS

UCAS

LCAS

Address

WE

OE

V,HV,L-

L-~~~~r-~~~~

V,H-

+ .......-'-"'-'

VIL- _l...-'I-.l.......l....l.4..l...l...l.....l....+-l-l...-'y.......l....l...l...l.....l......l....+-_ _ _ _ _+t_--'+r-_.......

tOll

tOfR

tCLl

L 1/0

VOHVOL-

Hi - 2

Data out

Hi -2

Remark U I/O: Hi-Z

427

NEe

yPD42S18165L,4218165L

Early Write Cycle
IRe
IRAS

RAS

IRP

V,HVILleSH

UCAS V,HLCAS V,L-

Address

U 1/0
L 1/0

V,HV,L- L...l'-ll~....K....L.K...l'-Jj~~

Remark OE: Don't care

428

I\._ _ _ _ _ _ _ _ _~ Y-.l............................."'-'''--'......_...v..........'''--'''-'''--''

_ _ _N_E...;;;;.;....;C=--_ _ _ _ _ _ _ _ _ _ _ _ _Jl=P;""..;D~4.....;;;.2.....;;;.S_1..:...81.;,..;6.....;;;.5_L~,4_2_1_8_16.;,...5.....;;;.L_ _ _--i:,;
Upper Byte Early Write Cycle
tRe
tRAS

RAS

tRP

VIH-

VILtCSH

V,HUCAS

VIL-

LCAS

Address

WE

U 1/0

Remark OE, L 1/0: Don't care

429

NEe

yPD42S18165L,4218165L

Lower Byte Early Write Cycle
tAC
tRAS

LeAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

LIfO

Remark OE, U 1/0: Don't care

430

tRP

NEe

:i

,uPD42S18165L,4218165L

--------~~~~~----------------------------------------------~~~~~~~~~~~~~~~~~----------~,'~
Late Write Cycle
IRC
lRAS

V,HVIL-

UCAS
LCAS

Address

WE

V,HVIL-

V,HVIL-

V,HVIL-

tOEH

OE

V,HVIL-

tOED

U 1/0
LIIO

V,H-

~

____

~t~

_______

VIL-

431

NEe

HPD42S18165L,4218165L

Upper Byte Late Write Cycle

Address

WE

OE

V,HV'LtOH

UI/O

ZZZ> .......

Remark L 1/0: Don't care

432

~!:.~ ...... .

Data in

IX

_ _..;...N...;;;..E-.,;C~_ _ _ _ _ _ _ _ _ _ _ _.....L.;,.J.1P_D_4_2_S_1_81_6_5_L,,-,4_2_1_8_16_5_L_ _ _--;i~
II
"(

Lower Byte Late Write Cycle

I~

I)
j

tRC
tRP

tRAS

RAS

V,HV1L-

tMRH

UCAS

V,HVILtCSH
tRCo

LCAS

V,HVIL-

Address

V,HVIL-

tRSH

teAS

WE

V,H-

V'L-

<-............-..........................

toH

L 1/0

YJ:l) ....... ~i:.~...... .

Data in

Remark U I/O: Don't care

433

NEe

yPD42S18165L,4218165L

Read Modify Write Cycle
tRWC
tRAS

ICSH
IRSH

tRCD

UCAS
LCAS

Address

V,HV,L-

Iwp
V,HV,L-

tOEH

V,HV,L-

los

U 1/0

LlIO

V,HV,L-

~--------- -

IOH

Dalain
IOL2

U 1/0 VOHL 1/0 VOL-

434

Hi-Z

NEe

yPD42S18165L, 4218165L

Upper Byte Read Modify Write Cycle
tRWG

tRP

tRAS

RAS
tesH
tRCD

UCAS

tASH

teAs

VIH-

V,L-

LCAS

V,HVIL-

Address

V,HV,L-

:~

V,HV,L-

OE

V,HV,L-

UI/O

V,HV,L-

U 110

VOH- .••••••••••••••••••••~~:!:
VOL-

wmxr . · · . ·. · · . ·.
............... .

Hi-Z

Remark In this cycle, the input data to Lower I/O is ineffective. The data out of that remains Hi-Z.

435

NEe

yPD42S18165L,4218165L

Lower Byte Read Modify Write Cycle

tAP

Address

WE

V,HV,L-

OE

V,HV,L-

Lila

V,HV,L-

Lila

VOH- •••••••••••••••••••• ~!:.~
VOL-

~ ................... .

............... .

Hi·Z

Remark In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi-Z.

436

'.Jj

NEe
yPD42S18165L,4218165L
j
---;""",,;;;-=-=------------------I::.::.:.....::;,....;.=....:....::....:....::...::...:=z-..:..:::....:...::...:....::..::...:=-----_,4
:.~

ii

Hyper Page Mode (EDO) Read Cycle

*

RAS

UCAS
LCAS

~

tRHCP

VtH-

~

VILtCSH

V,HVIL-

Address

V,HVIL-

WE

VIHVIL-

J

~

tRCO

Row

~

tHCAS

n

Col.

~

tHCAS

}~

r--""

~

~~

tRSH

tHPC
tHCAS

VI

~D

m~

Col.

~

~
Col.

OE

VOHVOL-

'-J

tOFC

I-

~
RRH

~

'j

'\

////1/1

twEZ~

\\\\\\\\\\~
I
I

U 1/0
L 1/0

tOFR

:xx: x:

t~

VIHVIL-

~

J

tRAL

Jl

'I

tRP

tRASP

tRAC
IAA
tCAC

~
............•..l:Il: 1-. •••..••••• ~;

tACP

tAA

tCAC

tCAC

~
Data out

~--I

tACP

tAA

Data out

\\\\
tOEZ

~

··0

/

.. -0

Data out

...

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

437

NEe

,uPD42S18165L,4218165L

Hyper Page Mode (EDO) Byte Read Cycle

~

IRASP
IRHCP

RAS V'HV'LIHPC

ICSH

~

~
~
V'HV'L- ~

IRCD

V'HUCAS
V'L-

LCAS

Address

V'HV'L-

WE

V'HV'L-

'-

IRSH

~

IHCAS

IHCAS

J!

\'
~

~

IHCAS

'--

I
IMRH

j.
~

~~~
Row

toFR

IRAL

Col.

~

~~

~

~

COI.)@;

Col.

I~W
IIII /1 f

~

toFC

XXX

C
~
RRH

"\

~

Ll
twez

OE V'HV'L-

[_~
lOEA.

L

IRAC

......

IDHC

lCAC

~

Va.-

---------------~:-~---------~~

~

/

\\\

~

1M

U 1/0 VO+I-

1M

1M
IcAC

\ \ \ \ \ \ \ \ \ \\\ ~

~i+=-

IACp

IACP

Daiaoul

~--

toez

- -------- --~--_o

Data oul

)--

IDHC

IL 1/0 VO+I-

Va.-

Hi-Z

----------------------------------------------

~

Dalaoul

~--------------------

--

Remarks 1. In the hyper page mode (EDO). read. write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or. it can be used to control UCAS
or LCAS simultaneously. or at random.

438

NEe

yPD42S18165L, 4218165L

Hyper Page Mode (EDO) Read Cycle (WE Control)
tRASP
tRHCP

RAS
tesH

UCAS
LCAS

V,HVIl-

Address

V,HVIl-

WE

V,HV,L-

OE

V,HV,L-

U 1/0

LIIO

VOHVOL-

•••••••••••••••I:!l:,i'; ••••••••.•

Data out

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

439

NEe

yPD42S18165L,4218165L

Hyper Page Mode (EDO) Read Cycle (OE Control)
tRASP

mHCP

RAS V,HV,LtesH

tHPC

UCAS V,H- --:lz--t+----,!:~
LCAS V,L-

Address V,HV,L-

toes

WE

V,HV,L-

locH

tv.
tCHO

!AcP

OE

V,HV,L-

U 1/0 VOHHi-Z
L 1/0 VOL- -------------------------

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

440

NEe

,~

yPD42S18165L, 4218165L

- - - - - - - ' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--L_::;:.,.,;;;;.....;..=...;",.;;....;",.;;.=!-..,;;.,;;;;..;....;;;..:...:....:...::....._ _ _ _,,,"

:'Ii

:/.

Hyper Page Mode (EDO) Early Write Cycle
tAASP

tRP

Address

V,HV,L-

U 1/0
L 1/0

V,HV,L-

L...lL.,lji...ll:....¥....¥..Y ""_ _ _ _- "

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

441

NEe

yPD42S18165L,4218165L

Hyper Page Mode CEDO) Byte Early Write Cycle
tRASP
tRHCP

Address VVIHIL-

WE V,HVIL-

U 110 V,HVIL-

L 1/0 V,HVIL-

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

442

I:;;.

_ _...;;,.N....;;;...;;:E::,.C=-_ _ _ _ _ _ _ _ _ _ _ _ _-..J:::.J.1P:....;D::,.4..:..::2=.:S:...;1:....:8:...,:.1.=.65=.:L=z.,_4:.=2:...:,.1.=.8..:...;16=.:5::,.=L=--_ _ _:'

Hyper Page Mode (EDO) Late Write Cycle

tRASP

RAS

AHCP

V,HVILtCSH

UCAS
LCAS

V,HVIL-

Address

V,HV,L-

tHPC

tRSH

V,HVll-

U 1/0
LlIO

V,H- . ______ ljtL _____ _
V,L-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

443

NEe

yPD42S18165L,4218165L

Hyper Page Mode (EDO) Byte Late Write Cycle
tRASP
tRHCP

tesH

tHPC
tHCAS

tRSH
tHCAS

tMRH

Address

V,HV,L-

UI/O

L 110 V,H- ______ tll:L _______ _
V,L-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

444

,'t

N~
______
~~___________________________ycP~D~4~2~S~1~8~1~65~L~,~4~2~1~81~6~5~L~____~iJJ
i'~

:'

il

Hyper Page Mode (EDO) Read Modify Write Cycle

V,HVIL-

UCAS
LCAS

V,HVIL-

Address

V,HV,L-

WE

V,HV,L-

V,HV,L-

U 1/0

L 1/0

VOHVOL-

U 1/0
L 1/0

VIHV,L-

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive

CAS cycles within the same ro'\S cycle.

445

NEe

yPD42S18165L,4218165L

Hyper Page Mode (EDO) Byte Read Modify Write Cycle
tAP

tRASP

tHPAWC
tHCAS

tHCAS

V'H- --tr-+t---..rr+-----~..--t--------_n------+.I_'lI-_+
V,L-

V'H- --Ir-+i---+-+-----+li.--d-I-------H.--++------I-+---.IVIL-

Address

V'HVIL-

WE

V'HVIL- '-''-'-'-+...1

OE

V'HVIL- --l'--.l.......l.....).....1.-.l,...;yY--V

Hi-Z
----.... __ .. _-- ......

UI/O

LIIO

V'H-

U 1/0 VIL-

L 1/0 V'H-

VIL-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

446

'i

I ~.

NEe

i~

!~

,uPD42S18165L, 4218165L

-----------------------------,;;.;;,;;.....;;;-;.....;;.....;..;...;....;,.~;;L...;.;-.;...;...;....;,.~;;....----__il'~
;~

I ~i:

Hyper Page Mode (EDO) Read and Write Cycle
tRASP

RAS

tRHCP

V,HVILtesH

UCAS
LCAS

Address

WE

V,HV,l-

OE

V,HV,l-

U 1/0
LIIO

. _. _. _.. --.~~:!-...... _....... .

VOHHi - Z
VOl- --- ------ - -- - -- -- - ---------- ••••

UIIO
L110

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive

CAS cycles within the same

~ cycle.

447

NEe

yPD42S18165L, 4218165L

CAS Before RAS Self Refresh Cycle (Only for the /lPD42S18165L)
tRASS

RAS

V,HV,l-

UCAS
LCAS

Remark Address, WE, OE: Don't care

L 110, U 110: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 1,024 times within a 16 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 1,024 times within a 16 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 JlS)' CAS before
RAS refresh cycles will be executed one time.
If 10 JlS < tRAS < 100 JlS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (1,024/128 ms) should be met.
For details, please refer to How to use DRAM User's Manual.

448

___N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _~J1!;.;..P_D_4_2_S_1_81_6__'_S_L:.._,4_2_1_8_16-...,;S_L_ _ _--iJ
I

i,~

CAS Before RAS Refresh Cycle
tAe
tRAS

tesA

UCAS
LCAS

teHA

V,HV,L-

Remark Address, WE, OE: Don't care

L I/O, U I/O: Hi-Z

RAS Only Refresh Cycle

tRAS

tAP

tRAS

VIHVIL-

teAP

UCAS V,HLCAS V,L-

Address

Remark WE, OE: Don't care

L I/O, U I/O: Hi-Z

449

NEe

gPD42S18165L,4218165L

Hidden Refresh Cycle (Read)
tRC

tRC

tRAS

IRAS

V,H-

RAS VIl-

tCRP

UCAS
LeAS

V,HV,L-

Address

V,HVIl-

tRCo

tRSH

tCHR

tCPN

WE V,HV,L-

OE V,HV,L- ....:I....l'-l......l....l......lr-~~.l.....l....+-l-I....ly~-:-_ _ _ _-+___...L+-r_-'.......................

,...-+............-"-

IoLz
U 1/0 VOHL 1/0 VOL-

450

Hi

-z

ICLZ

Data out

I'.'

_ _...:..N..::..E=..:C=--_ _ _ _ _ _ _ _ _ _ _ _~!1L:.:.:P~D:.._4=2=S....;,.18..;;..,.1::....:6=5=L,~4..;.;;:2:;..,;;1_=_8..:..16;:.....;;5__L_ _ _---ii~
Hidden Refresh Cycle (Write)
IRC

IRC
tRAS

V,H-

RAS V,L-

tCRP

UCAS V,HLCAS V,L-

Address

V,HV,L-

WE

V,HV,L-

U 1/0
L 1/0

V,HV,L-

IWCH

!wcs

...><...x......................

'-l...................

~

____

..J'

Remark OE: Don't care

451

NEe

gPD42S18165L, 4218165L

Package Drawings

50PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

-HI------+-----_+_

H

+It-4--

~

al

J

L

NOTE
Each lead centerline is located within 0.13 mm (O.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A
B
C

21.17 MAX.
1.0 MAX.
0.8 (T.P.)

0.834 MAX.
0.040 MAX.
0.031 (T.P.)

0

0.32~g:g~

0.013±0.003

E
F
G
H

0.1±0.OS
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400±0.004

K

M
N

P

0.8±0.2

0.031~g:gg~

0.14S~g:81~

0.006±0.001

0.S±0.1

0.020~8:88~

0.13
0.10
3,+7'
_3'

0.005
0.004
3,+7'
_3'
SSOG5-80-7JF4

452

s"

Ii
------~~~~----------------------------------------~~~~~~~~~~~~~~~--------~~
NEe

,uPD42S18165L,4218165L

42 PIN PLASTIC SOJ (400 mil)

B
22

-++--------------r-------------1-

(J

Cl

21

...,

E

F

P42LE-400A
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

ITEM

MILLIMETERS

INCHES

B

27.56~g:~5

1.085~g:g~~

C

10.16

00400

D

11.18±0.2

Oo440±0.008

E

1.08±0.15

o.043~g:gg~

F

0.74

0.029

G

3.5±0.2

0.138±0.008

H

2.545±0.2

0.100±0.008

I

0.8 MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

Oo4O±0.10

0.016~g:gg~

N

0.12

0.005

P

904±0.20

0.370±0.008

Q

0.10

0.004

T

R 0.85

R 0.033

U

0.20~g:~g

0.008~g:gg~

453

NEe

yPD42S18165L,4218165L

Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the JlPD42S18165L, 4218165L.

Types of Surface Mount Device
JlPD42S1816SLGS,4218165LGS: SO-pin plastic TSOP (II) (400 mil)
JlPD42S1816SLLE,421816SLLE: 42-pin plastic SOJ (400 mil)

454

Hyper Page Mode (EDO)
4M Dynamic RAM
[5.0V + 10%]
[5.0V + 5%]

455

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD42S4210,424210
4 M-BIT DYNAMIC RAM
256K-WORD BY 16-BIT, HYPER PAGE MODE (EDO),
BYTE READ/WRITE MODE

!

-------------------------------!~

f

Description
The ,uPD42S4210, 424210 are 262,144 words by 16 bits CMOS dynamic RAMs with optional hyper page mode
(EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
Besides, the ,uPD42S421 0 can execute CAS before RAS self refresh.
The ,uPD42S421 0, 424210 are packaged in 44-pin plastic TSOP (II) and 40-pin plastic SOJ.

Features
Hyper page mode (EDO)
262,144 words by 16 bits organization
Single power supply
+5.0 V

± 10 %:

,uPD42S4210-60-A, 424210-60-A, 42S421 0-70, 424210-70

+5.0 V ± 5 % : ,uPD42S4210-60-G, 42421 0-60-G

Part number

Power consumption

Access time

RIW cycle time

Hyper page mode

Active (MAX.)

(MAX.)

(MIN.)

(EDO) cycle time (MIN.)

!lPD42S4210-60-A, 424210-60-A

880 mW

60 ns

104 ns

25 ns

!lPD42S421 0-60-G, 424210-60-G

840 mW

60 ns

104 ns

25 ns

!lPD42S421 0-70, 424210-70

825 mW

70 ns

124 ns

30 ns

The ,uPD42S421 0 can execute CAS before RAS self refresh
Part number

Refresh cycle

!lPD42S4210-60-A

512 cycles/128 ms

Power consumption at standby
(MAX.)

CAS before RAS self refresh,
CAS before RAS refresh,

!lPD42S421 0-70
!lPD42S4210-60-G

Refresh

512 cycles/128 ms

RAS only refresh,
Hidden refresh

!lPD424210-60-A

512 cycles/8 ms

!lPD42421 0-70
!lPD424210-60-G

CAS before RAS refresh,
RAS only refresh,

512 cycles/8 ms

Hidden refresh

0.825 mW
(CMOS level input)
0.7875 mW
(CMOS level input)
5.5 mW
(CMOS level input)
5.25 mW
(CMOS level input)

The information in this document is subject to change without notice.
Document No. M10212EJ4VODSU1

457

NEe

yPD42S4210, 424210

Ordering Information
Part number

458

Access time
(MAX.)

Refresh

Package

IlPD42S4210G5-60-A

60

44-pin plastic TSOP (II)

IlPD42S4210G5-60"G

60

(400 mil)

IlPD42S4210G5-70

70

IlPD42S4210LE-60-A

60

40-pin plastic SOJ

IlPD42S4210LE-60-G

60

(400 mil)

IlPD42S4210LE-70

70

IlPD424210G5-60-A

60

44-pin plastic TSOP(II)

IlPD424210G5-60-G

60

(400 mil)

IlPD424210G5-70

70

IlPD424210LE-60-A

60

40-pin plastic SOJ

IlPD424210LE-60-G

60

(400 mil)

IlPD424210LE-70

70

CAS before ~ self refresh
CAS before RAS refresh

RAS

only refresh

Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

NEe

yPD42S421 0, 424210

I~
[1

f,

I

Pin Configurations (Marking Side)
44-pin Plastic TSOP (II) (400 mil)

Vee
1/01
1/02
1/03
1/04

Vee
1/05
1/06
1/07
1/08

1
2
3
4

44
43
42
41
40
39

5
6
7
8
9
10

1::1::

"g"g

22
......

.....
~~

0

38
37
36
35

40-pin Plastic SOJ (400 mil)

GND

Vee

11016

1/01

1/015

1/02

1/014

1/03

1/013

1/04

GND

Vee

11012

1/05

11011

1/06

1/010

1/07

1/09

1/08

..

gg

NC
NC
WE

13
14
15
16

NC
AO
A1

18
19

A2
A3

20
21

Vee

22

17

Q1

32
31
30
29
28
27
26
25
24
23

NC
LCAS
UCAS
OE

A8
A7
A6

A5
A4

WE

RAS
NC
AO
A1

5
6
7
8
9
10
11
12
13
14
15
16
17

A2
A3

18
19

Vee

20

1::1::

"g"g

22...

...

.. ...

~~

0 ..
'-0

m.m

33
32
31
30
29
28
27
26
25
24
23
22
21

GND
1/016
1/015
1/014
1/013

GND
1/012
1/011
1/010
1/09

NC
LCAS
UCAS
OE

A8
A7
A6
A5
A4

GND

GND

AD to A8
1/01 to 1/016

Address Inputs

RAS

Row Address Strobe
Column Address Strobe (upper)

UCAS
LCAS

NC
NC

40
39
38
37
36
35
34

10
2
3
4

Data Inputs/Outputs

Column Address Strobe (lower)

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

459

NEe

yPD42S4210, 424210

Block Diagram

Clock Generator

Vee

0------

GND 0------

CAS before
RAS Counter

XO to XB

AO
to
AB

460

Column
Address
Buffer

YO to YB

1109

NEe

yPD42S4210, 424210

Input/Output Pin Functions
The tLPD42S4210, 424210 have input pins RAS, CAS Note , WE, OE, AO to AS and input/output pins 1101 to
11016.
Pin name
RAS

Input/Output
Input

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.

(Row address strobe)

It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh
CAS
(Column address strobe)

Input

AO to A8
(Address inputs)

Input

CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
Address bus.
Input total 18-bit of address signal, upper 9-bit and lower 9-bit in sequence
(address multiplex method).
Therefore, one word is selected from 262,144-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASA, tASC) and hold time (tAAH, tCAH)
are specified for the activation of RAS and CAS.

WE

Input

-- --

-

Write operation is executed by activating RAS, CAS and WE.

(Write enable)
OE

Write control signal.

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.

(Output enable)

If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
1/01 to 1/016
(Data inputs/outputs)

Note

Input/Output

16-bit data bus.
1/01 to 1/016 are used to input/output data.

CAS means UCAS and LCAS.

461

NEe

yPD42S421 0, 424210

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.

1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time in the hyper page mode CEOO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle.

The hyper page mode (EDO) allows both read and write operations during one cycle, but the

performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mode CEOO) Read Cycle
RAS

~::~
tHPC

CAS

Address

V,HV,L-

--,.-+---......r""'\

V,HV,L-

WE V,H-

V,L-

L..."l.-.t....L...L.J
tOCH
tOEA

OE V,HVIl-

tCLZ

1/0 VOHHi-Z
VOL- .----------------------------

462

1,\
(

_ _....;..N....;;".;;;;E:;:..:C=--_ _ _ _ _ _ _ _ _ _ _ _ _ _~J1;.;...P.:::.D...:..42:;:..S:;:..:4.:...::2:....:.1..:..0,!._4..:..:2:;:..:4;.::2....;..1O.::......-_ _ _Ii

,

"~
}

Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate tHPC at the MIN. value.

.~
~

Ii,

2. To make II0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tcHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

463

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pPD42S421 0, 424210

Electrical Specifications
•

CAS means UCAS and LCAS.

•

All voltages are referenced to GND.

•

After power up (Vcc ~ VCC(MIN.), wait more than 100 JlS

(RAS, CAS inactive) and then, execute eight CAS before

RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

Parameter

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Pc

1

W

Operating ambient temperature

T.

o to +70

·C

Storage temperature

T&t1I

-55 to +125

·C

Caution

Symbol

Condition

Exposing the device to stress above those listed In Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described In the operational section ofthls specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
Parameter
Supply voltage

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Vee

pPD42S4210-So-A, 424210-60-A

4.5

5.0

5.5

V

4.75

5.0

5.25

pPD42S421 0-70, 424210-70
pPD42S4210-So-G,424210-60-G
High level input voltage

V,H

2.4

Vee + 1.0

Low level input voltage

V,L

-1.0

+0.8

V

Operating ambient temperature

T.

0

70

·C

MAX.

Unit
pF

Capacitance (TA = 25

'c, f = 1 MHz)

Parameter
Input capacitance

Data input/output capacitance

464

V

Test condition

Symbol

MIN.

TYP.

C"

Address

5

CI2

RAS, CAS, WE, OE

7

C,/o

1/0

7

pF

NEe

it

,uPD42S4210, 424210

--------------------------------------------------------~~~~~~~~~~~~--------~1

;:'

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter
Operating current

Standby

IIPD42S4210

Symbol
lec1

lee2

current

MAX.

Unit

Notes

RAS, CAS cycling

Test condition
tRAe = 60 ns

MIN.

160

rnA

1,2,3

tRe = tRe (M'N.), 10 = 0 rnA

tRAe = 70 ns

150
2.0

RAS, CAS" V'H (M'N.), 10 = 0 rnA

0.15

RAS, CAS" Vee - 0.2 V, 10 = 0 rnA
IIPD424210

RAS only refresh current

Operating current

lee3

lee4

(Hyper page mode (EDO))
CAS before RAS

Icc.

Ices

long refresh current

1.0

CAS" Vee - 0.2 V, 10 = 0 rnA

RAS cycling, CAS" V'H (M'N.)

tRAe = 60 ns

160

tRe = tRe (M'N.), 10 = 0 rnA

tRAe = 70 ns

150

RAS :; V'L (MAX.), CAS cycling

tRAe = 60 ns

160

tRAG = 70 ns

150

tHPC

refresh current
CAS before RAS

2.0

RAS, CAS" V'H (M'N.), 10 = 0 rnA

RAS,

=

tHPC (MIN.), 10

= a rnA

rnA

rnA

1,2,3,4

rnA

1,2,5

rnA

1,2

RAS cycling

tRAe = 60 ns

160

tRe = tRe (M'N.), 10 = 0 rnA

tRAe = 70 ns

150

CAS before RAS refresh:

tRAS:; 200 ns

200

!IA

1,2

tRAS:; 1 liS

300

!IA

1,2

150

IIA

2

-10

+10

IIA

-10

+10

IIA

tRe = 250.0 liS

(512 cycles I 128 ms,

RAS, CAS:

only for the IIPD42S421 0)

Vee - 0.2 V :; V'H :; V'H (MAX.)

o V:; VIL:; 0.2 V
Standby:
RAS, CAS" Vee - 0.2 V
Address: V'H or VIL
WE, OE: V'H
10 = 0 rnA
~before~

lee7

RAS, CAS:

self refresh current

tRASS = 5 ms

(only for the IIPD42S4210)

Vee - 0.2 V :; V'H :; V'H (MAX.)

o V:; V'L:; 0.2 V
10 = 0 rnA
Input leakage current

Ii (L)

V, = 0 to 5.5 V

IIPD42S4210-60-A, 424210-60-A
IIPD42S421 0-70, 424210-70

V, = 0 to 5.25 V IIPD42S4210-60-G, 424210-60-G
All other pins not under test = 0 V
Output leakage current

10(L)

Vo = 0 to 5.5 V IIPD42S4210-60-A, 42421 0-60-A
IIPD42S421 0-70, 424210-70
Vo = 0 to 5.25 V IIPD42S4210-60-G, 424210-60-G
Output in disabled (Hi-Z)

High level output voltage

VOH

10 =-5.0 rnA IIPD42S4210-60-A, 424210-60-A

V

2.4

IIPD42S421 0-70, 424210-70
10 =-0.1 rnA IIPD42S4210-60-G,424210-60-G
Low level output voltage

VOL

10 = +4.2 rnA IIPD42S4210-60-A, 424210-60-A

0.4

V

IIPD42S421 0-70, 424210-70
10 = +0.1 rnA IIPD42S4210-60-G, 424210-60-G

465

~I:C:

yPD42S4210, 424210

Notes 1. ICC1, IcC3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. ICCl and Icc3 are measured assuming that address can be changed once or less during RAS $ VIL (MAX.)
and CAS ~ VIH (MIN.).
4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.

466

I·r

: :~

_ _..;;...I\I..;;;..E=..;;C~_ _ _ _ _ _ _ _ _ _ _ _ _ _=flP;....D;;....4..;.;;2;;..;;S~4=21..;;...0;...{..,_4_24_2_1.-.;;.0_ _ _-1:.\

Ii
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

'

,,
,
~

V'H(M'N.) =2.4 V ---------------Vll{MAX.)

= 0.8

V

_____________

•

I
I

.:

,

:

:
I
I

t

I

: II

.:

t

!
I

: II

IT = 2 ns

(2) Output timing specification
• ttPD42S4210-60-A,424210-60-A

ttPD42S4210-60-G, 424210-60-G
ttPD42421 0-70, 424210-70

VOH(MIN.)=2.0V

u-u-=J

VOL (MAX.) = 0.8 V

------~'-_ _ _ _

~

..J+

VOH(MIN.)=2.4V

u-u-=f

VOL (MAX.) = 0.4 V

------~'-_ _ _ _

~

..J+

(3) Output loading conditions
ttPD42S4210-60-A, 424210-60-A

• ttPD42S4210-60-G, 424210-60-G

ttPD42S421 0-70, 424210-70
Vee

Vee

110--...---+

1/0 - - . . . - - - - - .

467

NEe

yPD42S421 0, 424210

Common to Read, Write, Read Modify Write Cycle
tRAe = 60 ns
Parameter

tRAe = 70 ns
Unit

Symbol
MIN.

MAX.

MIN.

MAX.

-

ns

Notes

Read I Write cycle time

tRe

104

-

124

RAS precharge time

tRP

40

-

50

CAS precharge time

tePN

10

-

10

-

ns

RAS pulse width

tRAS

60

10,000

70

10,000

ns

CAS pulse width

teAs

10

10,000

12

10,000

ns

RAS hold time

tRSH

10

-

12

-

ns

CAS hold time

tesH

40

-

50

-

ns

RAS to CAS delay time

tReD

14

45

14

50

ns

2

RAS to column address delay time

tAAO

12

30

12

35

ns

2

~ to RAS precharge time

teRP

5

-

5

-

ns

3

Row address setup time

tASR

0

-

0

-

ns

10

-

ns

0

ns

Row address hold time

tRAH

10

Column address setup time

tAse

0

Column address hold time

teAH

10

OE lead time referenced to RAS

tOES

0

ns

-

12

-

0

-

ns

ns

CAS to data setup time

teLZ

0

-

0

tOLZ

0

-

0

-

ns

OE to data setup time
OE to data delay time

tOED

13

-

15

-

ns

Masked byte write hold time referenced to RAS

b.tRH

0

-

0

-

ns

Transition time (rise and fall)

I pPD42S4210
I pPD424210

Refresh time

1

ns

tT

1

50

1

50

ns

tREF

-

128

-

128

ms

-

8

-

8

ms

4

Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 JlS.
If 10 JlS:;; tRAS < 100 JlS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD $ tRAD (MAX.) and tReD

$

tRCD (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.) and tRCD

$

tRCD (MAX.)

tAA (MAX.)

tAAD

+ tAA (MAX.)

teAc (MAX.)

tACO

+

tRCo> tACO (MAX,)

teAc (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the jlPD42S4210.

468

NEe

yPD42S421 0, 424210

Read Cycle
tRAC

tRAC = 60 ns
Parameter

Symbol

~

70 ns

MIN.

MAX.

MIN.

MAX

Unit

Notes

Access time from RAS

tRAC

-

60

ns

1

tCAC

15

-

70

Access time from CAS

20

ns

1

Access time from column address

tAA

30

-

35

ns

1

15

-

20

ns

35

-

ns

-

ns

15

-

ns

Access time from OE

tOEA

-

Column address lead time referenced to RAS

tRAL

30

Read command setup time

tRCS

a

Read command hold time referenced to RAS

tRRH

0

Read command hold time referenced to CAS

tRCH

0

-

Output buffer turn-off delay time from OE

tOEZ

0

15

a
a
a
a

CAS hold time to OE

tCHO

5

-

5

ns

2

ns

2

ns

3

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS
tRAC(IotAX.)

tRAD S tRAD (MAX.) and tRCD s tRCD (IotAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.) and tRCD s tRCD (MAX.)

tAA (MAX.)

tRAD

tRCD> tRCD (MAX.)

tCAC (MAX.)

tRCD + tCAC (MAX.)

+

tAA (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, 1M or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (M)N.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

469

NEe

yPD42S4210, 424210

Write Cycle
Parameter

tRAC = 60 ns
Symbol

tRAC = 70 ns

Unit

Notes

-

ns

1

ns

1

ns

MIN.

MAX.

MIN.

MAX

-

10

WE hold time referenced to CAS

tWCH

10

WE pulse width

twp

10

WE lead time referenced to RAS

tRWL

10

10
12

ns

WE lead time referenced to CAS

tewL

10

twcs

0

-

12

WE setup time
OE hold time

tOEH

0

-

0

-

Data-in setup time

tos

0

-

ns

3

toH

10

-

0

Data-in hold time

10

-

ns

3

0

ns

2

ns

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles. tWCH (MIN.) should
be met.
2. If twcs ~ twcs (MIN.). the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles. they are referenced to the WE falling edge.
Read Modify Write Cycle
tRAC = 60 ns
Parameter

Symbol

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX

-

157

-

Read modify write cycle time

tAWC

133

RAS to WE delay time

tRWo

77

CAS to M

delay time

tewo

32

Column address to WE delay time

tAWo

47

89
37
54

Unit

Note

ns
ns

1

ns

1

ns

1

Note 1. \! twcs ~ twcs (MIN.). the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.

\! tRWD ~ tRWD (MIN.). tCWD ~ tCWD (MIN.). tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met. the state of the data out is indeterminate.

470

NEe

yPD42S421 0, 424210

Hyper Page Mode (EDO)

Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX

Unit

Notes
1

Read I Write cycle time

tHpc

25

-

30

-

ns

RAS pulse width

tRASP

60

125,000

70

125,000

ns

CAS pulse width

tHCAS

10

10,000

12

10,000

ns

CAS precharge time

tcp

10

-

10

-

ns

Access time from CAS precharge

tACP

-

35

-

40

ns

CAS precharge to WE delay time

tCPWD

52

-

59

RAS hold time from CAS precharge

tRHCP

35

-

ns

40

-

ns

75

-

ns

2

tHPRWC

66

Data output hold time

tOHC

5

-

OE to CAS hold time

tOCH

5

-

5

-

ns

OE precharge time

tOEP

5

-

5

-

ns

Output buffer turn-off delay from WE

!wEZ

0

13

0

15

ns

WE pulse width

!wPZ

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

13

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFC

0

13

0

15

ns

3,4

Read modify write cycle time

5

ns
4

3,4

Notes 1. tHPC (MIN.) is applied to CAS access.
2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle. If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.
(2)

tOFR is effective when CAS is inactivated before RAS is inactivated.
Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

471

NEe

yPD42S421 0, 424210

Refresh Cycle
tRAe
Parameter

Symbol
MIN.

MAX.

tRAe
MIN.

CAS setup time

teSR

5

-

5

CAS hold time (CAS before RAS refresh)

tCHR

10

-

10

RAS precharge CAS hold time

tRPe

5

5

tRASS

100

tRPS

110

CAS hold time (CAS before RAS self refresh)

teHs

-50

WE hold time

tWHR

15

-

RAS pulse width (CAS before RAS self refresh)
RAS precharge time (CAS before

R7iS self

refresh)

Note 1. This specification is applied only to the JLPD42S421 o.

472

= 60 ns

100
130
-50
15

= 70 ns

Unit

Note

MAX

-

-

ns
ns
ns
Il S

1

ns

1

ns

1

ns

NEe

pPD42S421 0, 424210

Read Cycle
tRC
tRP

tRAS

RAS

V,HVIltCSH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

tOlZ

teLz
U
1/0
L 1/0

VOHHi - Z
VOL-··· •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

tOFR
Data out

Hi -Z

473

NEe

yPD42S421 0, 424210

Upper Byte Read Cycle
IRe
IRAS
RAS

IRP

V,HV,LlesH

UCAS

V,HV,L-

Address

WE

V,HV,L-

OE

V,HV,L-

loLZ

IOFR

Ictz

U 1/0

VOHVOL-

Remark L I/O: Hi-Z

474

Hi ·Z

Dala oul

Hi· Z

NEe

yPD42S421 0, 424210
I"
i'J
"

Lower Byte Read Cycle

II

tRC
tRAS

RAS

tRP

1.

V,HV,LIMRH

UCAS

V,HV,L-

LCAS

VIHV,L-

Address

V,HV,L:;

I::

WE

V,HV,L-

"

I:
OE

V,H-

.....l...~

V,L- ......:Wu....l....l...+-.l...ww-+....lo.....l....l...~Wu....lo.....l.....l....:f-_ _ _ _--t-+-_.....,.,-_~-+

tOLZ

tOFR

leLZ

LIIO

VQHVO<-

Hi-Z

Data out

Hi-Z

Remark U 1/0: Hi-Z

:1

il

Ij

I;11

I
475

I

I

NEe

yPD42S421 0, 424210

Early Write Cycle
IRC
IRAS

RAS

tRP

V,H-

v,,-

tcsH

UCAS
LCAS

V,HV,L-

Address

V,,'V,L-

U 1/0

LlIO

V,HV,L-

.....l"'-lo..lto.. . .~~..lto.....l..~!'-+_I-

V,HV,L-

'->L..X'-K....................L..X'-K..3 "'_ _ _~_ _ _ _ _ _ _......................................................................................

Remark OE: Don't care

476

_ _ _ _ _ _+

......~-'-.J-..I-....................................................._

NEe

yPD42S421 0, 424210

Upper Byte Early Write Cycle
IRC
IRAS
RAS

tRP

V,HV,LIcsH

UCAS

V,HV,L-

Address

WE

UI/O

,

Remark OE, L 1/0: Don't care

I,

I!
I:

I!

I"

.. ~

1

I

477

NEe

yPD42S421 0, 424210

Lower Byte Early Write Cycle
tAC
tRAS

RAS

tCRP
UCAS

tRP

V,HV,Lt"RH

V,HV,L-

V,HV,L-

Address

V,HV,L-

V,HV,L- ~~""""~~~""""~-+_+-+.L-~,"",,-I..-'-L...l..........K......

Remark U 1/0: Don't care

481

NEe

pPD42S421 0, 424210

Read Modify Write Cycle
l.we
IAAS

leSH
lASH

IACD

UCAS
LCAS

V'HV'L-

Address

V'HV'L-

WE

V'HV'L-

lOEH

10EA

OE

Viii-"
V'Llos

UI/O
LlIO

V'HV'L-

U 1/0 VOHL 1/0 VOL-

482

~--------- Hi-Z

IOH

Data In

Hi-Z

NEe

yPD42S4210, 424210

Upper Byte Read Modify Write Cycle
IRwe
IRP

IRAS

RAS
tCSH

IReD

UCAS

V,HV,L-

LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

IRSH
leAS

OE

U 1/0

U I/O

~ .................. .

VOH- ••••••••••••••••••••~~:!:
VOL-

............... .

Hi -Z

Remark In this cycle, the input data to Lower 1/0 is ineffective. The data out of that remains Hi-Z.

483

NEe

yPD42S421 0, 424210

Lower Byte Read Modify Write Cycle
tRWC
tRAS

RAS

tRP

V,HVIltCAP

UCAS

V,HVILtCSH
tRCO

tRSH

tCAS

LCAS

V,HV,L-

Address

V,HV,L-

WE

OE

L 1/0

~::~ ""lXlXtl»"'~~-X-"X"'"7\. .................. .

L 1/0

VOH- •••••••••••••••••••• ~!:.~
VOL-

............... .

Hi ·Z

Remark In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi·Z.

484

NEe

yPD42S4210, 424210

Hyper Page Mode (EDO) Read Cycle
tRASP

RAS

UCAS
LCAS

~

tRHCP

VIH-

'-

VIL-

V,HVIL-

Address

V,HV,L-

WE

V,HV,L-

J

tesH

~

~
r----.

tHCAS

tRCD

~

&f.~
Row

tASH

tHPC
tHCAS

~

tHCAS

,1/---.

11 /
I

tRAl

~
Col.

]X>9-

~~

m)

Col.

~

~
Col.

OE

V,HV,L-

\\\\\\\\\\~

RRH ~

tACP

tAA

tCAC

tCAC

/

y/

~~
\\\\

tRAC

IAA
tCAe

~

VOHVOL-

~

-'<,

tAA

'-

X

//////1
tACP

I

,1,0:

.~

tOFe

I-

I

U 1/0
L 1/0

tOFR

:xx

tj2

~

_______________J:Il: l:. __________ -<

~

~

Data out

~

~--O

Data out

tOEZ

--0

Data out

---

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

485

NEe

,uPD42S421 0, 424210

Hyper Page Mode (EDO) Byte Read Cycle
RASP

~

tAHCP

tHPC

tesH

V,HUCAS V,L-

V,HLCAS V,L-

Adaess

V,HV,L-

WE

V,HV,L-

OE V,HVn.-

~

tACO

~
~

--.-!

tRSH
tHCAS

tHCAS

r\

'-Y '~

I

~

~

tHCAS

tMRH

j

'"

tRAO

~~~
Row

IoFR

tRAL

~

Col.

~

~~

m

Col.

t~U

~

~ ~

tOFC

lOOC

Col.

C
~
RRH

/////If
~
I_
tOEA,

1M

\\\\\\\\\\\\ ~

~

IcAC

tRAe

~

"Utwez

~~

IAcp
IA.

tACP

"--

I

\\\

~

1M

tDHC

IcAC

tOEl

i+-o

..JE4
U 1/0 VO/i-

Va.-

---------------~:-~---------1~

Data out

~---

-

-------- -----{)

Data out

--

tOHC

.......
LIIO VO/i-

VOL-

Remark

Hi-Z
----------------------------------------------

~

Data out

--------------------

--

1. In the hyper page mode (EDO). read. write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or. it can be used to control UCAS
or LCAS simultaneously. or at random.

486

NEe
___
_..;;;;;...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J;.J1:..:..P...::D;....:4~2...::;,S...;,;42:::...1:.....:0:....!..,.....;4...::;,2...;,;42:::...1:.....:0~---iil'*
~
'~

11,

Hyper Page Mode (EOO) Read Cycle (WE Control)

II

IiI~

tRASP
tRHCP

RAS

','(

tesH

UCAS
LCAS

V'H-

V,L-

Address

WE

V,H-

V,L-

OE

UIIO
LlIO

VQH-

_______________ l:Il:_~ _________ _

Voc-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

1

II
II
'!

ij

IIi!
"

il
.1

i!
487

NEe

yPD42S421 0, 424210

Hyper Page Mode (EDO) Read Cycle (OE Control)
tRASP
tRHCP

RAS V,HVILtesH

tHPe

tRSH

UCAS V,H- ---!.--IH----!h
LCAS VIL-

Address

V,HVIL-

WE

V,HV,L-

tOES
tOCH

Ae
IAA

tCHO
IAcp

OE

V,HVIL-

U 1/0 VOHHi-Z
L 1/0 VOL- -------------------------

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

488

NEe
I'
________________________________________
~y_P_D_4_2_S_4_21_0~,_4_2_4_21_0
--------l
fi.

:~

i~

Hyper Page Mode (EDO) Early Write Cycle
tRASP

tAP

Address

U 1/0

V,H- r71~-X-'K""'l1r'7\

v-----"1i

L 1/0

V,L- L..Jji-lt.~.x....:1L..lf

11--_ _ _---11

Remarks 1. OE: Don't care

2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

489

NEe

yPD42S421 0, 424210

Hyper Page Mode (EDO) Byte Early Write Cycle
tRASP
tRHCP

UCAS V,HVIL-

V,HAddress VIL-

U I/O V,HVIL-

L I/O V,HVIL-

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

490

NEe

,uPD42S4210, 424210

1.1·.

----------------------------------------~-~~~~~~--~------~i

!

,I

Hyper Page Mode (EDO) Late Write Cycle

it
:i

tRASP

II

RHCP

~:

tcSH

Address

V,iiVIL- L-L.....t....,j'--l:...J

V,iiVIL- L-L.....t....,j'--l:...J

UI/O
LlIO

Hi-Z
._---------------

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

491

NEe

yPD42S421 0, 424210

Hyper Page Mode (EDO) Byte Late Write Cycle
tRASP
tRHCP

tHpc

tCSH

lHcAs

tRSH
tHCAS

bARH

Address

V,HVIL-

V,HVIL-

U 1/0 V,HV,L-

L 1/0 V,H- ______ ttj;_~ ________ _
V,L-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

492

NEe

I

yPD42S421 0, 424210

Hyper Page Mode (EDO) Read Modify Write Cycle
IRASP

UCAS
LCAS

Address

V,HVIL-

V,I<...,;"_'..........

Remark OE: Don't care

499

NEe

~PD42S4210,424210

Package Drawings

44 PIN PLASTIC TSOP(II) (400 mil)

44

23
detail of lead end

~

1-+---------------+----------------~

w

a..

H

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

~.

ITEM

MILLIMETERS

INCHES

A

18.63 MAX.
0.93 MAX.
0.8 (T.P.)

0.734 MAX.
0.037 MAX.
0.031 (T.P.)

B
C

0

0.32~8:8~

0.013±0.003

E

0.1±O.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.O02
0.048 MAX.
0.038
0.463±0.008
0.400±0.OO4

F
G
H

0.8±0.2

0.031~8:88g

K

0.145~8:8~~

0.006±0.001

L

0.5±0.1

0.020~8:88~

M

0.13
0.10
3 0_30
+ 70

0.005
0.004

N

P

J

+7"
30_30
S44G!HIO-7JF4

500

NEe

~PD42S4210,424210

40 PIN PLASTIC SOJ (400 mil)

++----------------- + ------------------+

()

Cl

20

T

P

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

26.29~8j5

1.035~8:8?~

10.16
11.18±0.2

0.400
0.440±0.008

E

1.08±0.15

0.043~8:88~

F

G

0.7
3.5±0.2

0.028
0.138±0.00B

H

2.4±0.2

0.094~8:88~

K

O.B MIN.
2.6
1.27(T.P.)

0.031 MIN.
0.102
0.050(T.P.)

c
D

M

0.40±0.10

0.016~8:88t

N
P
T

0.12
9.40±0.20
0.15
RO.B5

0.005
0.370±0.00B
0.006
RO.033

u

0.20~8:6~

0.00B~8:88~

Q

P40LE-400A-2

501

NEe
Recommended Soldering Conditions

Types of Surface Mount Device
J.LPD42S4210G5, 424210G5: 44-pin plastic TSOP (ll) (400 mil)
J.LPD42S4210LE, 424210LE: 40-pin plastic SOJ (400 mil)

502

,uPD42S421 0, 424210

Hyper Page Mode (EDD)
1M Dynamic RAM
[S.Ov + 10%]

503

DATA SHEET

N EC
MOS INTEGRATED CIRCUIT
_ _ _ _ _ _ _..:......-IlP_D_4_21_8_05_1
i

1 M-BIT DYNAMIC RAM
128K-WORD BY 8-BIT, HYPER PAGE MODE (EDO)

Description
The tLPD421S05 is a 131,072 words by S bits CMOS dynamic RAM with optional hyper page mode (EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
The tLPD421S05 is packaged in 2S-pin plastic TSOP (II) and 28-pin plastic SOJ.

Features
Hyper page mode (EDO)
131,072 words by S bits organization
Single +5.0 V ±10 % power supply
CAS before RAS refresh, RAS only refresh, Hidden refresh
• 512 refresh cycles/S ms

Part number

Power consumption
Active (MAX.)

.uP0421805-25-A

550 mW

Access time

RIW cycle time

Hyper page mode (EDO)

Standby (MAX.)

(MAX.)

(MIN.)

cycle time (MIN.)

5.5mW

70 ns

124 ns

25 ns

.uP0421805-30-A

(CMOS level

30 ns

.uP0421805-25

input)

25 ns

.uP0421805-30

30 ns

.uP 0421805-35

35 ns

The information in this document is subject to change without notice.
Document No. M10632EJ5VODSU1

505

NEe

ILPD421805

Ordering Information
Part number

Access time
(MAX.)

506

Hyper page mode (EDO)
cycle time (MIN.)

Package
28-pin plastic TSOP (II)

JlPD421805G5-25 -A

70 ns

25 ns

JlPD421805G5-30-A

70 ns

30 ns

JlPD421805G5-25

70 ns

25 ns

JlPD421805G5-30

70 ns

30 ns
35 ns

JlPD421805G5-35

70 ns

JlPD421805LE-25-A

70 ns

25 ns

JlPD421805LE-3Q-A

70 ns

30 ns

JlPD421805LE-25

70 ns

25 ns

JlPD421805LE-30

70 ns

30 ns

JlPD421805LE-35

70 ns

35 ns

(400 mil)

Refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh

28-pin plastic SOJ
(400 mil)

NEe

,uPD421805

Pin Configurations (Marking Side)
28-pln Plastic TSOP (II) (400 mil)

Vee

1101
1102
1103
1104
NC
WE

RAS
NC
AO
Al
A2

A3
Vee

AO to A8

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1::
."

..~

I
C/I

28
27
26
25
24
23
22
21
20
19
18
17
16
15

28-pln Plastic SOJ (400 mil)

GND
1108
1107
1106
1105
CAS

1101
1/02
1103
1104
NC

OE

WE

NC
A8
A7
A6
A5
A4

GND

Vee

RAS
NC
AO
Al
A2
A3
Vee

10
2
3
4

5
6

7
8
9
10
11
12
13
14

1::
."

c

~

co

...5l

m

28
27
26
25
24
23
22
21
20
19
18
17
16
15

GND
1108
1107
1106
1105
CAS
OE

NC
A8
A7
A6
A5
A4

GND

Address Inputs

1101 to 1108: Data Inputs/Outputs
RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE
Vee

Output Enable
Power Supply

GND

Ground

NC

No Connection

507

NEe

jlPD421805

Block Diagram

Clock
Generator

Vee 0 - GNOo--

CAS before
RASCounter
Memory
Cell
Array
512x256x8

AD
to
A8

508

1/01
to
1/08

NEe

,uPD421805

Input/Output Pin Functions
The JtPD4218D5 has input pins RAS, CAS, WE, OE, AD to AS and input/output pins 1101 to 1108.

Pin name
RAS

InpuVOutput
Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS
(Column address strobe)

Input

CAS activates data inpuVoutput circuit by latching column address and
selecting a digit line connected with the sense amplifier.

AOto A8
(Address inputs)

Input

Address bus.
Input total 17-bit of address signal, upper 9-bit and lower 8-bit in sequence
(address multiplex method).
Therefore, one word is selected from 131,072-word by 8-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, lAse) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.

WE
(Write enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE
(Output enable)

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/08
(Data inputs/outputs)

InpuVOutput

8-bit data bus.
1/01 to 1/08 are used to input/output data.

509

NEe

yPD421805

Hyper Page Mode (EDO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.

1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.

2. The CAS cycle time In the hyper page mode (EDO) Is shorter than that In the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle. The hyper page mode (EDO) allows both read and write operations during one cycle, but the
performance is equivalent to that of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.

Hyper Page Mode (EDO) Read Cycle
RAS

~::~

CAS

V,HV,L-

--r-t----r"\

Address V,HV,L-

WE V,HV,L- "-'r.....~....L..J

VQHHi-Z
1/0 VOL- .----------------------------

510

NEe

,uPD421805

Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive,

DE:

active

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS Is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

511

NEe

,uPD421805

Electrical Specifications
• All voltages are referenced to GND.
• After power up (Vcc;:: VCC (MIN.)), wait more than 100 ps (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Symbol

Rating

Unit

Voltage on any pin relative to GND

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Po

1

W

Operating ambient temperature

T.

oto +70

·C

Storage temperature

Toto

-55 to +125

·C

Caution

Condition

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device Is not meant to be operated under conditions outside the limits
described In the operational section ofthis specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Parameter

Symbol
Vee

4.5

5.0

5.5

V

High level input voltage

V,H

2.4

Vee + LO

V

Low level input voltage

V,L

-1.0

+0.8

V

70

·C

Operating ambient temperature

Capacitance (TA = 25

T.

0

·c, f = 1 MHz)

Parameter
Input capacitance

Data inpuVoutput capacitance

512

Condition

MAX.

Unit

Address

5

pF

CI2

RAS, CAS, WE, OE

7

CliO

I/O

7

Symbol
C"

Test condition

MIN.

TYP.

pF

NEe

IlPD421805

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

Test condition

Operating current

Iccl

RAS, CAS cycling
tRC = tRC (M'N.), 10 - 0 mA

Standby current

Icc>

RAS, CAS  tRAD (MAX.)
tRCO> tRCO (MAX.)

and

tRCO

:s;

tACO (MAX.)

Access time

Access time from RAS

tRAC (MAX.)

tRAC (MAX.)

tAA (MAX.)

tRAD

+

tAA (MAX.)

teAc (MAX.)

tACO

+

teAc (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters·
They are used to determine which access time (tRAC, tAA or tcAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
2. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

515

NEe

,uPD421805

Read Cycle
tHPe

= 25 ns

MIN.

MAX.

tRAe

-

70

teAe

-

20

Access time from column address

tAA

-

30

Access time from OE

tOEA

-

20

Column address lead time referenced to RAS

tRAL

30

Read command setup time

tRCS

0

Read command hold time referenced to RAS

tRRH

0

Read command hold time referenced to CAS

tRCH

Output buffer turn-off delay time from OE
CAS hold time to OE

Parameter

Symbol

Access time from RAS

I JlPD421805-A
I JlPD421805

Access time from CAS

15

tHPe
MIN.

= 30 ns

35

0

tOEl

0

teHo

5

= 35 ns

Unit

Notes

70

ns

1

-

ns

1

1

MIN.

MAX.

70

-

-

-

tHPe

MAX.

20
18
35
20

40

0

-

15

0

-

5

0
0

0

20
40

ns

20

ns

-

ns
ns
ns

2

0

-

ns

2

15

0

15

ns

3

-

5

-

ns

0

Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAQ

Access time from RAS

tACO

:5

tACO (MAX.)

tRAC (MAK)

tRAC (MAX.)

and

tRCO

:5

tACO (MAX.)

tAA (MAX.)

tAAD

+ tAA (MAX.)

teAc (MAX.)

tRCD

+ teAc (MAX.)

tRAD> tRAQ (MAX.)
tRCD

Access time

:5: tRAQ (MAX.) and

> tACO (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tcAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ(MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

516

NEe

,uPD421805

Write Cycle
Parameter

Symbol

WE hold time referenced to CAS

tWCH

tHPe

= 30 ns

tHPe

= 35 ns

MIN.

MAX.

MIN.

MAX.

10

-

12

-

15

a
a
a

-

15

-

twp

10
20

WE lead time referenced to CAS

tCWL

10

WE setup time

twes

OE hold time

tOEH

WE lead time referenced to RAS

tHPe

MAX.

tRWL

WE pulse width

= 25 ns

MIN.

Data-in setup time

tDS

a
a
a

Data-in hold time

tDH

10

12
20
12

a
a
a
12

15
20
15

Unit Notes
ns

1

ns

1

ns
ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2.

If twcs ~ twcs

(MIN.),

the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
Parameter

Symbol

tHPe

= 25 ns

tHPe

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

165

-

Read modify write cycle time

tRWC

165

-

165

RAS to WE delay time

tRWO

89

89

CAS to WE delay time

tewD

34

Column address to WE delay time

tAWD

49

-

37
54

= 30 ns

tHPC

89
39
59

= 35 ns

Unit

Note

ns
ns

1

ns

1

ns

1

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tewD ~ tewD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ !cPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

517

NEe

JlPD421805

Hyper Page Mode (EDO)
Parameter

Symbol

tHPC

= 25 ns

MIN.

MAX.

tHPC
MIN.

= 30 ns

tHPC

MAX.

MIN.

= 35 ns

Unit Notes

MAX.

Read I Write cycle time

tHPC

25

-

30

-

35

-

ns

RAS pulse width

tRASP

70

125,000

70

125,000

70

125,000

ns

CAS pulse width

tHCAS

10

10,000

12

10,000

15

10,000

ns

CAS precharge time

tcp

10

-

10

-

10

-

ns

Access time from CAS precharge

tACP

-

33

-

40

-

45

ns

CAS precharge to WE delay time

tCPWD

54

-

59

-

64

-

ns

RAS hold time from CAS precharge

tRHCP

35

75

83

Data output hold time

tOHC

5

-

5

-

5

-

ns

68

-

45

tHPRWC

-

40

OE to CAS hold time

tOCH

5

5

5

5

5

-

ns

tOEP

-

5

OE precharge time

-

Output buffer turn-off delay from WE

\wEZ

0

15

0

15

0

15

ns

WE pulse width

\wpz

10

-

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

15

0

15

0

15

ns

3,4

Output buffer turn-off delay from CAS

tOFC

0

15

0

15

0

15

ns

3,4

Access time from previous WE
(Hyper page mode. (EDO) read and write cycle)

tAWE

-

55

-

65

-

75

ns

Access time from previous CAS
(Hyper page mode (EDO) write and read cycle)

tAeE

-

55

-

65

-

75

ns

Read modify write cycle time

1

2

ns
ns
4

ns
3,4

Notes 1. tHPC (MIN.) is applied to CAS access.
2. If twcs 2! twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRwD 2! tRWD(MIN.), tcwD 2! tCWD(MIN.), tAWD 2! tAWD (MIN.) and tCPWD 2! tCPWD(MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)

Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2)

Both RAS and CAS are active or either RAS or ~ is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.

(3)

Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.

(4)

WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

518

NEe

,uPD421805

Refresh Cycle
Parameter

Symbol

= 25

ns

tHPe

MIN.

MAX.

MIN.

tHPe

= 30

ns

MAX.

tHPe

= 35 ns

MIN.

MAX.

Unit

CAS setup time

leSR

5

-

5

-

5

-

ns

CAS hold time (CAS before RAS refresh)

tCHR

10

10

-

10

-

ns

RAS precharge CAS hold time

tRPe

5

5

-

5

tWHR

15

15

-

15

-

ns

WE hold time

-

Note

ns

519

NEe

gPD421805

Read Cycle
IRe
IRP

IRAS
RAS

V,HVIllesH

CAS

V,HVIL-

Address

V,HVIl-

WE

V,HVIl-

OE

V,HV,L-

loLZ
leLZ
1/0

520

VOHHi - Z
VOL- .- - - -- -- - - -- - - - -- - -- - -- - -- - -- - -- - - - - - -- - - - -- -- -- - -- - -- - -- --- - ---

tOFR

Dala oul

Hi - Z

NEe

IlPD421805

Early Write Cycle
tRe
tRAS
VIH-

VILtesH

Remark OE: Don't care

521

NEe

gPD421805

Late Write Cycle
tRC
tRAS

V,HVIL-

Address

WE

1/0

522

NEe

,uPD421805

Read Modify Write Cycle
tRWC

tRAS

RAS

tesH
tRSH

tRCO

CAS

Address

V,HVIL-

V,HVIL-

tewD

WE

VIH-

VIl-

tOEH

tOEA

OE

VIH-

VtL-

tCAC

1/0

V,HVIl-

~---------

tos

tOH

Data in
talz

1/0

VaHVal-

Hi-Z

Hi-Z

523

NEe

,uPD421805

Hyper Page Mode CEOO) Read Cycle
IRP

tRASP

RAS

VIH-

CAS

VIL-

lesH

~

~

Address

~
r---,

~

~~
Row

tHCAS

'--

tASH

tHPC

tHCAS

tACD

tRAD

V,HVIL-

~

tRHCP

V,HVIL-

~

1'---'

11

n

~

Col.

~~
COI.)OOJ

D

WE

tOFR

tOFC

'-J

I

:xx

Col.

X
~

I~
V,HVIL-

J

J

tRAL

~

~

tHCAS

I- RRH ~

LLlLI}

"\

-VI
!wEZ

V,HOE

VIL-

\\\\\\\\\\~
I

I/O

VOHVOl-

I
I

Hi -Z
.......................

tACP

4~

tACP

1M

IAA

teAe

teAC

J

\ \ ,\

tRAC

IAA
leAe

~
-------~

~

~

Data out

~

~--<)!

Data out

tOEZ

--{)

Dataoul

-- -

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

524

Ii!,

NEe

~\

,uPD421805

-------------------------------------~-'------------->~

Hyper Page Mode (EDO) Read Cycle (WE Control)
tRASP

RAS

tRHCP

V'HVILtesH

CAS

Address

V,HVIL-

WE

V,HV,L-

OE

1/0

V,HVll-

VOH-

_______________ J::ll: f'. _________ _

voL-

Data out

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

525

NEe

yPD421805

Hyper Page Mode (EDO) Read Cycle (OE Control)
tRASP
tRHCP

RAS V,HV,LtCSH

CAS

V,HVIL-

Address

V,HV,L-

WE

V,HV,L-

tHPC

IRSH

--i...-t+----.i-"'"

toES

tOCH

AC
IAA
tCHO
tAcp

OE

V,HV,L-

VOHHi-Z
1/0 VOL- -------------------------

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

526

Hyper Page Mode (EDO) Early Write Cycle

V,HV,L-

CAS

V,HV,L-

Address

V,HV,L-

V,HV,L-

I:

110

V,HV,L- L..J'-lI"-lf...lL..¥-1I

"

I\._ _ _ _....JI

Remarks 1. DE: Don't care

2. In the hyper page mode (EDD), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

527

NEe

yPD421805

Hyper Page Mode (EDO) Late Write Cycle
tRASP
tRHCP

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

1/0

V,H- . ______ I:!t~ ______ _
V,L-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

528

NEe

,uPD421805

Hyper Page Mode (EDO) Read Modify Write Cycle
tRASP

I/O

VOHVOL-

I/O

V,HV,L-

tRP

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

529

NEe

,uPD421805

Hyper Page Mode (EDO) Read and Write Cycle
tRASP

I"HCP

V,HV,L-

tcsH
CAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

1/0

VOHHi - Z
VOL- - •••••••••••••••••••••••••••••••

1/0

V,HV,L-

Hi-Z
.. ..................................

-_ ........ -_ ...... .

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

530

NEe

,uPD421805

Hyper Page Mode (EDO) Write and Read Cycle
tRASP
tRHCP

tesH

CAS

Address

V,HVIL-

WE

V,HVIL-

OE

V,HVIL-

1/0

VOHVOL-

_____ •• !!i.-.~_ •••.••

Data out

Hi-Z

1/0

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

531

NEe

yPD421805

CAS Before RAS Refresh Cycle

RAS Only Refresh Cycle

tAAS

V,HV,L-

teAP

V,HV,L-

Address

V,HV,L-

Remark WE, OE: Don't care

532

I/O: Hi-Z

tAP

NEe

JLPD421805

Hidden Refresh Cycle (Read)
IRC

lAC

iRAS

IRAS

RAS V,H-

V,L-

CAS V,HVIL-

Address

V,HV,L-

WE

V,HV,L-

OE V,HVIL-

1/0 VOHVOL-

533

NEe

,uPD421805

Hidden Refresh Cycle (Write)
lAC

IRC

IRA.

lRAS

RAS

VIHVIL-

ICRP

CAS

Address

VIHVIL-

VIHVIL-

twcs
WE

1/0

VIL-

VIHVIL-

L.l1t...Jot....lji~..K...K..,;~&....ltI'...JI

Remark OE: Don't care

534

!weH

VIH-

1I._ _ _ _....Jl

"-'~&....ltI.........K.........,~&....ltI........................,................................"-"'-".....

NEe

,uPD421805

Package Drawings

28 PIN PLASTIC TSOP(II) (400 mil)

28

15
detail of lead end

+t-------+--------+
W

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

Il.

ITEM

MILLIMETERS

INCHES

A
B
C

18.63 MAX.
1.075 MAX.
1.27 (T.P.)

0.734 MAX.
0.043 MAX.
0.050 (T.P.)

0

0.42~8:89

0.017±0.003

E
F

0.1±0.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400tO.004.

0.8±0.2

0.031 ~8:88ij

K

0.145~8:8~~

0.006tO.00l

L

0.5tO.l

0.020~8:88~

M

0.21
0.10
3,+7'
_3'

0.009
0.004
3 0 _3'
+ 70

G
H

N

P

S28G5-50-7JD5

535

NEe

yPD421805

28 PIN PLASTIC SOJ (400 mil)
B

+-t---------+------+

F

()

Cl

E

I

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

18.67~gj5

O. 735~g:g?~

C

10.16

0.400

D

11.18±0.2

0.440~g:gg~

E

1.08±0.15

0.043~g:gg~

F

0.6

0.024

G

3.5±0.2

0.138~g:gg~

H

2.4±0.2

0.094~g:gg~

J
K

0.8 MIN.
2.6
1.27(T.P.)

0.031 MIN.
0.102
0.050(T.P.)

M

0.40±0.10

0.016~g:gg~

N

0.12

0.005

P

9.40±0.20

0.370~g:gg~

Q

T

0.15
RO.85

0.006
RO.033

U

0.2o~g:6g

0.008~g:gg~
P28LA·400A·2

536

NEe

,uPD421805

Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the ,uPD421805.

Types of Surface Mount Device
,uPD421805G5: 28-pin plastic TSOP (II) (400 mil)
,uPD421805LE: 28-pin plastic SOJ (400 mil)

537

NEe
[MEMO]

538

,uPD421805

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

,uPD421165

1 M·BIT DYNAMIC RAM
64K·WORD BY 16-BIT, HYPER PAGE MODE (EDO), BYTE READ/WRITE MODE

Description
The JlPD421165 is a 65,536 words by 16 bits CMOS dynamic RAM with optional hyper page mode (EDO).
Hyper page mode (EDO) is a kind of the page mode and is useful for the read operation.
The JlPD421165 is packaged in 44-pin plastic TSOP (II) and 40-pin plastic SOJ.

Features
Hyper page mode (EDO)
65,536 words by 16 bits organization
Single +5.0 V ±10 % power supply
CAS before RAS refresh, RAS only refresh, Hidden refresh
256 refresh cycles/4 ms

Part number

Power consumption
Active (MAX.)

JlPD421165-25-A
JlPD421165-30-A
JlPD421165-25

632.5 mW

Standby (MAX.)
5.5mW

Access time

RIW cycle time

Hyper page mode (EOO)

(MAX.)

(MIN.)

cycle time (MIN.)

70 ns

124 ns

25 ns

(CMOS level
input)

30 ns
25 ns

JlPD421165-30

30 ns

JlPD421165-35

35 ns

The Information In this document is subject to change without notice.
Document No. M10612EJ6VODSU1

539

NEe

yPD421165

Ordering Information
Access time
(MAX.)

Hyper page mode (EDO)

pPD421165G5-25-A

70 ns

25 ns

44-pin plastic TSOP (II)

pPD421165G5-30-A

70 ns

30 ns

(400 mil)

pPD421165G5-25

70 ns

25 ns

pPD421165G5-30

70 ns

30 ns

pPD421165G5-35

70 ns

35 ns

pPD421165LE-25-A

70 ns

25 ns

40-pin plastic SOJ
(400 mil)

Part number

540

cycle time (MIN.)

pPD421165LE-30-A

70 ns

30 ns

pPD421165LE-25

70 ns

25 ns

pPD421165LE-30

70 ns

30 ns

pPD421165LE-35

70 ns

35 ns

Package

Refresh
CAS before RAS refresh

-RAS only refresh
Hidden refresh

NEe

i:

IlPD421165

I
,

I:

Pin Configurations (Marking Side)

I

44-pin Plastic TSOP (n) (400 mil)

II

40-pin Plastic SOJ (400 mil)

J

Vee

1/03

2
3
4

1/04

5

Vee

6

1/05

7
8
9
10

1/01
1/02

1/06
1/07
1/08

1::
"II

...~C

...

44
43
42
41
40
39
38
37
36
35

GND

Vee

1/016

1/01

1/015

1/02

1/014

1/03

1/013

1/04

GND

Vee

1/012

1/05

1/011

1/06

1/010

1/07

1/09

1/08

en

en
en

G)

NC
NC

A3

13
14
15
16
17
18
19
20
21

Vee

22

WE

RAS
NC
AD
A1
A2

32
31
30

NC
LCAS
UCAS
OE

27
25

NC
A7
A6
AS
A4
GND

AO to A7

Address Inputs

1/01 to 1/016

Data Inputs/Outputs

RAS

Row Address Strobe

UCAS
LCAS

Column Address Strobe (upper)
Column Address Strobe (lower)

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND
NC

Ground
No Connection

NC
NC
WE

RAS
NC
AD
A1
A2
A3
Vee

10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39

.~

GND

t

l

1/016
1/015

Ii

1/014
1/013

35
34
33
1::
"II

...C~

...

GND
1/012

1

1/011
1/010

31

1/09

NC
LCAS

en

en
r-

m

UCAS
OE

21

NC
A7
A6
A5
A4
GND

541

NEe

IlPD421165

Block Diagram

RAS
LCAS
UCAS
WE

Clock Generator

Upper
Byte
Control

Vee

0--

GND

0--

CAS before
RAS Counter

Memory
Cell
Array
XOto X7

AO
to
A7

542

Column
Address
Buffer

YO to Y7

1/09

NEe

,uPD421165

Input/Output Pin Functions
The JLPD421165 has input pins RAS, CAsNote, WE, OE, AD to A7 and input/output pins 1101 to 1/016.

Pin name

m

Input/Output
Input

Function
~ activates the sense amplifier by latching a row address and selecting a

(Row address strobe)

corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.

CAS

Input

~ activates data input/output circuit by latching column address and

Input

Address bus.

• CAS before RAS

selecting a digit line connected with the sense amplifier.

(Column address strobe)
AOto A7

refresh

(Address inputs)

Input total 16-bit of address signal, upper 8-bit and lower 8-bit in sequence
(address multiplex method).
Therefore, one word is selected from 65,536-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating

RAS.

Then, switch the address bus to column address and activate CP$.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, lAse) and hold time (tRAH, tCAH)
are specified for the activation of
WE
(Write enable)

Input

OE
(Output enable)

Input

RAS and CAS.

Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If ~ is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/016
(Data inputs/outputs)

Input/Output

16-blt data bus.
1/01 to 1/016 are used to input/output data.

Note CAS means UCAS and LCAS.

543

NEe

,uPD421165

Hyper Page Mode (EOO)
The hyper page mode (EDO) is a kind of page mode with enhanced features. The two major features of the
hyper page mode (EDO) are as follows.
1. Data output time is extended.
In the hyper page mode (EDO), the output data is held to the next CAS cycle's falling edge, instead of the rising
edge. For this reason, valid data output time in the hyper page mode (EDO) is extended compared with the fast
page mode (= data extend function). In the fast page mode, the data output time becomes shorter as the CAS
cycle time becomes shorter. Therefore, in the hyper page mode (EDO), the timing margin in read cycle is larger
than that of the fast page mode even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the hyper page mode (EDO) is shorter than that in the fast page mode.
In the hyper page mode (EDO), due to the data extend function, the CAS cycle time can be shorter than in the
fast page mode if the timing margin is the same.
Taking a device whose tRAC is 60 ns as an example, the CAS cycle time in the fast page mode is 25 ns while that
in the fast page mode is 40 ns.
In the hyper page mode (EDO), read (data out) and write (data in) cycles can be executed repeatedly during one
RAS cycle.

The hyper page mode (EDO) allows both read and write operations during one cycle, but the

performance is equivalent to that .of the fast page mode in that case.
The following shows a part of the hyper page mode (EDO) read cycle. Specifications to be observed are described
in the next page.
Hyper Page Mode (EDO) Read Cycle
RAS

~::~

V,H-

CAS

V,L-

Address

V,H-

-""7-+-----:i::.

V,L-

WE V,HV,L- .............-'-...........1

OE

~::~

I/O VOH-

VQL-

544

NEe

,uPD421165

Cautions when using the hyper page mode (EDO)
1. CAS access should be used to operate tHPC at the MIN. value.
2. To make I/0s to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active

I

tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.

III':"
I

(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ..... tOEZ is effective.

il

(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)

IIJ

WE, OE: active and either tRRH or tRCH must be met ..... tWEZ and twpz are effective.
3. In read cycle, the effective specification depends on the state of CAS signal when controlling data output
with the OE signal.
(1) CAS: inactive, OE: active ..... tCHO is effective.
(2) CAS, OE: active ..... tOCH is effective.

545

NEe

yPD421165

Electrical Specifications
CAS means UCAS and LCAS.
All voltages are referenced to GND.
After power up (Vee 2: Vee (MIN.»), wait more than 100 /.IS (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

Parameter

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Po

1

W

Operating ambient temperature

T.

oto +70

·C

Storage temperature

TSIQ

-55 to +125

·C

Caution

Symbol

Condition

Exposing the device to stress above those listed In Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthls specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
Parameter

Condition

MIN.

TYP.
5.0

MAX.

Unit

5.5

V

Supply voltage

Vee

4.5

High level input voltage

V,H

2.4

Vee + 1.0

V

Low level input voltage

V,L

-1.0

+0.8

V

Operating ambient temperature

T.

0

70

·C

CapaCitance (TA = 25 ·C, f
Parameter
Input capacitance

Data input/output capacitance

546

Symbol

= 1 MHz)
MAX.

Unit

C"

Address

5

pF

CI2

RAS, CAS, WE, OE

7

C,iO

I/O

7

Symbol

Test condition

MIN.

TYP.

pF

NEe

,uPD421165

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter

Symbol

MIN.

Test condition

Operating current

Icc1

RAS, CAS cycling
tRe = tRe (MIN.), 10 = 0 mA

Standby current

lce2

RAS, CAS;' V,H (MIN.), 10 = 0 mA

RAS only refresh current

lee3

Operating current

ICC4

tRAe = 70 ns

Unit

Notes

115

mA

1,2,3

2.0

mA

1.0

RAS, CAS;' Vee - 0.2 V, 10 = 0 mA

(Hyper page mode (EDO))

MAX.

RAS cycling, CAS;' V,H (MIN.)
tRC = tRC (MIN.), 10 = 0 rnA

tRAe = 70 ns

115

mA

1,2,3.4

RAS ,;; VIL (MAX.), CAS cycling

tHPe = 25 ns

115

mA

1,2,5

tHPe = 30 ns

105

tHPe = 35 ns

95

tRAe = 70 ns

115

mA

1,2

-10

+10

J1A

-10

+10

J1A

0.4

V

tHPC

= tHPC (MIN.),

10

= 0 rnA

CAS before RAS
refresh current

Icc,

RAS cycling
tRe = tRe (MIN.), 10 = 0 mA

Input leakage current

Ii (L)

V, = 0 to 5.5 V
All other pins not under test = 0 V

10 (L)

Output leakage current

Vo = 0 to 5.5 V
Output is disabled (Hi-Z)

High level output voltage

VOH

Low level output voltage

VOL

10 =-2.5 mA
10 = +2.1 mA

2.4

V

Notes 1. Icc1, Icc3, Icc4 and Iccs depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.

3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS
and CAS

~

~

V(L (MAX.)

V(H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.

547

NEe

fLPD421165

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
V,HIMIN.)=2.4V
Vll(MAX.)

III

-.-------~----.'
,
,,
,,

0.8 V .------------

Iii I
I
I

I
I

:

: I

I
I

.:

I
,

:.

IT = 2 ns

(2) Output timing specification
JtPD421165-A

JtPD421165
VOHIMIN.)=2.4V

------=J

}-

VOLIMAX.) = 0.4 V

------~'__ _ _ _oJ

(3) Output load condition
Vee
1,6600

110---.---4
5900

548

VOHIMIN.)=2.4V

------=J

}-

VOLIMAX.) = 0.8 V

------~'__ _ _ _-'

I'1

I!

NEe
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-I:.!1.:.,:.P-=D=--4.;.:2=-1=--1-=6....::.5_ _ _--i!1
if;

I~

Common to Read, Write, Read Modify Write Cycle

Parameter

Symbol

tHPe = 25 ns

tHPe = 30 ns

tHPe = 35 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Unit Notes

Read / Write cycle time

tRe

124

-

124

-

124

tRP

50

-

50

-

50

-

ns

RAS precharge time
CAS precharge time

tePN

10

-

10

-

10

-

ns

RAS pulse width

tRAS

70

10,000

70

10,000

70

10,000

ns

CAS pulse width

teAs

10

10,000

12

10,000

15

10,000

ns

RAS hold time

tRSH

20

-

20

-

20

-

ns

CAS hold time

tCSH

70

-

70

-

70

-

ns

RAS to CAS delay time

tAco

20

55

20

52

20

50

ns

RAS to column address delay time

tRAD

15

40

15

35

15

30

ns

1

CAS to RAS precharge time

tcRP

5

5

-

5

-

ns

2

ns

ns

OE to data setup time

tol'

0

OE to data delay time

toeD

15

Masked byte write hold time referenced to RAS

tMRH

0

-

IT

1

50

1

50

1

50

ns

-

4

-

4

-

4

ms

Row address setup time

tASR

0

Row address hold time

tRAH

10

Column address setup time

lAse

0

Column address hold time

tCAH

10

OE lead time referenced to RAS

tOES

0

CAS to data setup time

tel'

0

Transition time (rise and fall)
Refresh time

tREF

0

-

0

10

10
0

-

12

-

15

-

ns

0

-

0

ns

0

-

0

0

-

0

15

-

15

-

0

-

0

-

ns

0

1

ns
ns

ns
ns
ns

Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAD.5 tRAD (MAX.)

and

tRCO

tRAD> tRAD (MAX.)

and

tRCo ~ tRCO (MAX.)

tRCO> tRCo (MAX.)

.s;;

tRCO (MAX.)

Access time

Access time from RAS

tRAC (MAX.)

tRAC (MAX.)

tAA (MAX.)

tRAD

+

tAA (MAX.)

tCAC (MAX.)

tRCO

+

tCAC (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
2. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

549

NEe

,uPD421165

Read Cycle
Parameter

Symbol

tHPC - 25 ns
MIN.

MAX.

Access time from column address

1M

Access time from OE

tcEA

-

Column address lead time referenced to RAS

tRAL

30

Read command setup time

tACS

0

Read command hold time referenced to RAS

tRRH

0

Read command hold time referenced to CAS

tRCH

0

-

Access time from RAS

tRAC

Access time from CAS

IpPD421165-A

tCAC

IpPD421165

70
20
15
30
20

Output buffer turn-off delay time from OE

toez

0

15

CAS hold time to OE

tcHo

5

-

lHpc - 30 ns
MIN.

-

tHPC = 35 ns
MIN.

MAX.

70

-

70

ns

1

-

ns

1

1

20
18
35
20

20
40

ns

20

ns

40

-

ns

0

-

ns

0

ns

2

0

-

ns

2

ns

3

ns

a

-

0

15

0

15

5

-

5

-

35
0
0

Unit Note!

MAX.

Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAD:S tRAD IMAX.) and tRCD :s tRCO IMAX.)
tRAD> tRAD IMAX.) and tRCD
tRCD> tRCD IMAX.)

:s tRCD IMAX.)

Access time

Access time from RAS

tRAcIMAX.)

tRAC(MAX.)

1M IllAX.)

tRAD + 1M IMAX.)

tCAC(MAX.)

tRCD + tCAC IMAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, 1M or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ{MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or
VOL.

550

",

;if

_ _N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--=J1:..-PD:..-4-...:2:....;1_1..;:...65~_ ___I:l

t
;Ii·

!.~

Write Cycle

Parameter

Symbol

tHPe

= 25 ns

tHPe

= 35 ns

MAX.

MIN.

MAX.

MIN.

MAX.

10

12

-

15

-

Data-in setup time

tos

0

Data-in hold time

tOH

10

-

tWCH

= 30 ns

MIN.

-

WE hold time referenced to CAS

tHPe

WE pulse width

twp

10

WE lead time referenced to RAS

tRWl

20

WE lead time referenced to CAS

tCWL

10

WE setup time

twcs

0

OE hold time

tOEH

0

12
20
12
0
0
0
12

15
20
15
0
0
0
15

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH

!~
Unit Notes
i1'
"

"

ns

1

ns

1

ns
ns
ns

2

ns
ns

3

ns

3

(MIN.)

should

be met.
2. If twcs ~ twcs

(MIN.),

the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. I n late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle

Parameter

Symbol

tHPe

= 25 ns

tHPe

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

165

-

Read modify write cycle time

tAWC

165

-

165

RAS to WE delay time

tRWD

89

89

CAS to WE delay time

tewD

34

-

37

Column address to WE delay time

tAwo

49

-

54

= 30 ns

tHPe

89
39
59

= 35 ns

Unit

Note

ns
ns

1

ns

1

ns

1

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

551

NEe

gPD421165

Hyper Page Mode (EDO)
Parameter

Symbol

tHPC = 25 ns

.tHPC = 30 ns

tHPC = 35 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Unit Notes

Read I Write cycle time

tHPC

25

-

30

-

35

-

ns

RAS pulse width

tRASP

70

125,000

70

125,000

70

125,000

ns

CAS pulse width

tHCAS

10

10,000

12

10,000

15

10,000

ns

CAS precharge time

tcp

10

-

10

-

10

-

ns

Access time from CAS precharge

tACP

-

33

-

40

-

45

ns

CAS precharge to WE delay time

tCPWD

54

-

59

-

64

-

ns

RAS hold time from CAS precharge

tRHCP

35

-

40

-

45

-

ns
ns

1

2

tHPAWC

68

-

83

-

tOHC

5

-

75

Data output hold time

5

-

5

-

OE to CAS hold time

tOCH

5

-

5

-

5

OE precharge time

tOEP

5

-

5

-

5

-

Output buffer turn-off delay from WE

tWEZ

0

15

0

15

0

15

ns

WE pulse width

twpz

10

-

10

-

10

-

ns

4

Output buffer turn-off delay from RAS

tOFR

0

15

0

15

0

15

ns

3,4
3,4

Read modify write cycle time

ns
ns

4

ns

Output buffer turn-off delay from CAS

tOFC

0

15

0

15

0

15

ns

Access time from previous WE

tAWE

-

55

-

65

-

75

ns

tACE

-

55

-

65

-

75

ns

3,4

(Hyper page mode (EDO) read modify write cycle)
Access time from previous CAS
(Hyper page mode (EDO) write and read cycle)

Notes 1. tHPC (MIN.) is applied to CAS access.

2. If twcs <': twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If tRWD <': tRWD (MIN.), tCWD <': tCWD (MIN.), tAWD <': tAWD (MIN.) and tCPWD <': tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. tOFC (MAX.), tOFR (MAX.) and twEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
not referenced to VOH or VOL.
4. To make 1/05 to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1) Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.
(3) Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.
(4) WE: inactive (in read cycle)
CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.

552

NEe

yPD421165

Refresh Cycle
Parameter

Symbol

tHPC

= 25 ns

tHPC

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

5

-

5

-

CAS setup time

tcSR

5

CAS hold time (CAS before RAS refresh)

tCHR

10

RAS precharge CAS hold time

tAPe

5

WE hold time

tWHR

15

10
5
15

= 30

ns

tHPC

10
5
15

= 35

ns

Unit

Nole

ns
ns
ns
ns

553

NEe

IlPD421165

Read Cycle
tRe
tRP

tRAS

RAS

UCAS V,HLCAS VIL-

Address

V,HVIL-

WE

OE

tOll
tell

U 1/0

Lila

554

VOHVOl-

............. ____ .... _

........ _

...... _

.... _

Hi - Z

.. _ _ . . . . . . . . _

...... _

...... _

. . . . . . . . . . _ _ . . . . . . . . . . . . . . . . . _ _ . . . . 00 ..

tOFR

Data out

Hi - Z

NEe

yPD421165

Upper Byte Read Cycle
tRe
tRP

tRAS

RAS

VIH-

VIltesH
tRCO

tRSH

tcPN

teAs

UCAS

V,HVIL-

tMRH

LCAS

V,HVIltRAL

Address

VIH-

VIl-

WE

OE

VIH-

VIl-

tCAC

tOll

tOFA

tell
UI/O

Remark

VOHVOL-

Hi -Z

Data out

L 1/0: Hi-Z

555

NEe

,uPD421165

Lower Byte Read Cycle
lAC
IAAS

RAS

lAP

V,HV,L-

V,HV,L-

Address

V,HV,L-

V,HV,L-

OE

V,HV,L- _l...,;I....J"'--l.....l.-+....l.~...\... . .+-~l...,;y"'--l.....l.....l.....l.~...\..+-_ _ _ _ _-I+_-'.,.,r-_...\..+~~.....,

ICAC
IOL2

toFA

ICL2

LlIO

VOHVOL-

Remark U liD: Hi-Z

556

Hi-Z

Dalaoul

Hi-Z

NEe

_~;;"';;::"';~

,uPD4211 6S

_ _ _ _ _ _ _ _ _ _ _ _ _ _--t;..;...._ _ _ _ _ _ _ _:....:.....-_ _

I

.~

,~

I~

Early Write Cycle

'I

tRC
tRP

tRAS

If;

VIH-

VIL-

tCSH

UCAS

V,H-

LCAS

VIl-

Address

---17--++-------,,1----..

>1/---i r- - - - . t - -

1+-_ _ _ _ _ _ _ _ _ _

VIHVIL-

V,HVIL-

U 1/0
LIIO

V,H-

VIl-

L...I....................................."-'"-3 ' -_ _ _ _ _ _ _ _ _,..-1

" ..............-"-"'-"--'''--'.......'-'''-''-......................................

Remark OE: Don't care

557

NEe

yPD421165

Upper Byte Early Write Cycle
IRC
lRAS

RAS

V,HVILICSH

UCAS

V,HVIL-

LCAS

Address

WE

UI/O

Remark DE, L liD: Don't care

558

IRP

____~~E~c:~__________________________________~HP_D_4_2_1_1~65~____~~It
'j

Lower Byte Early Write Cycle

II

IRC

lRAS

RAS

ICRP

UCAS

IRP

V,HVILIMRH

V,HVIL-

V,HV,L-

Address

V,HV,L-

V,HV,L- ......l~......l.....l.~~. .~~....p._+-......,f-+-......'-'..........£...........£...I-......' - '..........£...........£...I-......'-"...................J-.

LIIO

V,HV,L-

L..JL.lI:....lI.....K....K...K..lL.ll:....ll..3 II._ _ _ _..JI '\I;...x.............,;............;...x.............,;............;...x........oX-'............'"""'...............

Remark OE, U 1/0: Don't care

559

NEe

,uPD421165

Late Write Cycle
IRC

IRA.

V,HV,L-

Address

V,HV,L-

V,HV,L-

V,HV,L-

UI/O
LlIO

560

V,HV,L-

NEe

,uPD421165

Upper Byte Late Write Cycle
IRe
IRAS

RAS

IRP

V,HV,LIcsH
IReD

UCAS

V,HV,L-

LCAS

V,HV,L-

IRSH
leAS

Address

OE

V,HV,L-

U 1/0

V,HV,L-

~ ....... ~!:.~ ...... .

Dalain

Remark L 1/0: Don't care

561

NEe

,uPD421165

Lower Byte Late Write Cycle
IRC
IRAS

RAS

IRP

V,HVILtMRH

UCAS

V,HV,LlosH
IACO

LCAS

V,HV,L-

Address

V,HVIL-

WE

OE

lASH
tcAS

V,HV,L- L-L....'--'~~-L-L...L..J

V,HVIL - .................'-'...................J....1
IOH

Lila

ZZX} ....... ~i:.~

Remark U 1/0: Don't care

562

•••••••

"'-~r~_ _ _ _D_al_a_in_ _ _ _-"

" ...........-"-............................................

NEe

,uPD421165

Read Modify Write Cycle
tRWC
tRAS

ICSH
IRCO

tASH

UCAS
LCAS

Iwp

tOEH

los

IOH

Dalain

Hi-Z

563

NEe

,uPD421165

Upper Byte Read Modify Write Cycle
tRWC

tRAS

RAS

tRP

V,HV,LtesH
tReD

tRSH
teAs

UCAS

VIH-

V,L-

LCAS

V,HV,L-

Address

V,HV,L-

WE

OE

U I/O

UI/O

V,HV,L-

V,HVIL-

~-------------------

VOH- , ..
VOL-

Hi - Z- .......... _............ -_ .. ..
---_ ...... -- .. -- -_ .... -_ ..........

Hi -Z

Remark In this cycle, the input data to Lower 1/0 is ineffective. The data out of that remains Hi-Z.

564

I;

NEe

I

yPD421165

Lower Byte Read Modify Write Cycle

lAP

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

L110

V,HV,L-

L110

VOHVOL-

~--- .. -------------Hi-Z_. _... _. -_. _.... .
..... _. _................

Hi-Z

Remark In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi-Z.

565

NEe

,uPD421165

Hyper Page Mode (EDO) Read Cycle
IRP

tAASP

RAS

UCAS
LCAS

V,HV,L-

ICSH

~

IRCD

Address

WE

V,HV,L-

~

tHCAS

tHCAS

,---,

"-

tASH

tHPC

~

-.!
~

V,HV,L-

~

tRHCP

V,HVIl-

~

tHCAS

[r-----,
tRAL

~~
Row

n J

CAC
1M

\\\\

ICHD
IAcp

H'-to!
~

f-+- I.....m...

~

~ ~

Ir--.

J
DEA
tm2
tOEZ

\\\\

j..-!s>!l.

~~~----~ ~ Data out B}--- ~ Data out BI)--..(~ Data out C

_J!U_

In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

569

NEe

,uPD421165

Hyper Page Mode (EDO) Early Write Cycle

VIH-

VIl-

Address

UI/O
Lila

V,H- ...,,...,,...,......r-JI,.-,,. ~-----.I
Vll-

L...l'--"'-"-............."

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.

570

NEe

,uPD421165
I,
-~~~------------_---c::'~=-:"":";::"=-----It.

'I

Hyper Page Mode (EDO) Byte Early Write Cycle

I

IRAsp
tRHCP

~

I·

Ii
LeAS V,HV,L-

Address VVIHIL-

U I/O V,HV,L-

L 1/0 V,HV,L-

Remarks 1. OE: Don't care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LeAS simultaneously, or at random.

571

NEe

,uPD421165

Hyper Page Mode (EDO) Late Write Cycle
tRASP
tRHCP

tCSH

UCAS
LCAS

Address

WE

OE

UI/O

Lila

V'HVIl-

V,HV,L-

L-.l...."-.l-........J

V'HV,L-

L-.l.....I-.l-.l-J

V'HV'L-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

572

,

_---.,;.N....;;;...;;;E;;;;...C=--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----I::=.Yp:.....;D:::..4..:..:2:....:1....:..1.=.;65=----_ _ _!!

i

Hyper Page Mode (EDO) Byte Late Write Cycle

I

tAASP
tRHCP

V,HVIL-

!

,~

ICSH

tHPC

IHCAS

tRSH
tHCAS

V,HVIL-

tMRH

Address

V,HVIL-

I:
WE

OE

I

V,HVIL-

V,HVIL- L......r.....J:~-'-J

U 1/0

V,HV,L-

L 1/0

V,H- ______ tij:_~ ________ _
V,L-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

573

NEe

,uPD421165

Hyper Page Mode (eOO) Read Modify Write Cycle
tRP

RAS

UCAS
LCAS

Address

V,HV,L-

V,HV,L-

WE

U 1/0 VOHL 1/0 VOL-

U 1/0
LIIO

V,HV,L-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

574

II

_ _N_E_c~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-I.J1:::.P-=D:......:4.=.21.:...;1:....=6..=..5_ _-----!!1

ii

Hyper Page Mode (EDO) Byte Read Modify Write Cycle

il

tAASP

RAS

V,HV,L-

"

IHPAWe

IHCAS

LeAS

IHCAS

V,HV,LIRAL

Address

V,HV,L"

I
I

WE V,HV,L- L-t........f....I.+..J

OE

V,HV,L- _:l....:Io....lI...l...l....l....l..+~41

Hi-Z

U 1/0 VOH-

LIIO

V,HU 1/0 V,L-

L 1/0 V,HV,L-

Remarks 1. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of
the consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

575

NEe

,uPD421165

Hyper Page Mode (EDO) Read and Write Cycle
lRASP

RAS

tRHCP

V,HV,LleSH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,H- ......................................~-+............""
V,L-

U I/O
L I/O

VOHHi - Z
VOL- .--------------------------------

_________ J:!t:!-______________ .
IOH

UI/O
LlIO

V,HV,L-

Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

576

NEe

,uPD421165

Hyper Page Mode (EDO) Write and Read Cycle
tRASP

RAS

tRHCP

V,HV,LtesH

UCAS
LCAS

Address

V,HV,L-

WE

OE

V,HV,L-

UIIO
LIIO

VOHVOL-

U 1/0

V,HV,L-

L 1/0

_______ !1i:_?______ _
Data out

Hi-Z

Remark In the hyper page mode (EDO). read. write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

577

NEe

,uPD421165

CAS Before RAS Refresh Cycle

RAS

V,H-

V,L-

UCAS
LCAS

V,H-

V,L-

Remark Address, WE, OE: Don't care

L I/O, U I/O: HI-Z

RAS Only Refresh Cycle

lAP

tCRP

UCAS V,HLCAS V,L-

Address

V,H-

V,L-

Remark WE, OE: Don't care

578

L I/O, U I/O: Hi-Z

Ii

_--.:..N-=E::..C=-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-=J1P;.....;D~4.;;.;;:2;:....:;1....:..1..;;.,.65~_ __!!1
:I
~i

Hidden Refresh Cycle (Read)

.. ~

tRC

!,If

tRC

lRAS

tRAS

RAS V,H-

V,L-

teRP
UCAS
LCAS

Address

WE

tRCD

IRSH

leHR

tCPN

V,HVIL-

V,H-

V,L-

V,HVll-

OE V,HVIL-

--~~~~~~~~~~~~~~_t~--------_1--------~,---~~~~~rL_t~~~-

lelZ

U 1/0 VOH-

L 1/0 VOL-

Hi-Z
-------------------------------------------

Data out

~

I

If
I
[

I
I'~
,;!

~

II
!!
'I

,I

Ii
579

!lII

NEe

,uPD421165

Hidden Refresh Cycle (Write)

,.\.

tAC

tAC

tRAS

tAAS

Address

V,HV,L-

WE

V,HV,L-

twcs

U 1/0
L 1/0

V,H-

V,L- L..l'-lj"-lot...lL...K....K..-'lL.lt...lol~

Remark OE: Don't care

580

II.._ _ _ _....J

!weH

,I;

III

NEe

:!

JlPD421165

------------------------------------------~----~----~!'

:~
Ii

Package Drawings

:~

44 PIN PLASTIC TSOP(ll} (400 mil)

It
l'·

44
detail of lead end

~+---------------+----------------~

H

0I~~~ 4J~;;;'~:;;;;:;;:::;~~.
CDI$I

M

J

@I

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM
A
B
C

MILLIMETERS
18.63 MAX.
0.93 MAX.
0.8 (T.P.)

INCHES
0.734 MAX.
0.037 MAX.
0.031 (T.P.)

0.32~g:g~

0.013±0.003

0.HO.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400±0.004

0.8±0.2

0.031 ~g:gg~

0.145~g:m

0.006±0.001

0.5±0.1

0020~g:gg~

N

0.13
0.10

0.005
0.004

P

3 _3
+ 700

3 _3
+70

D

E
F

G
H

K

M

0

0

0

S44G5-80-7JF4

581

NEe

yPD421165

40 PIN PLASTIC SOJ (400 mil)

21

~---------------+

----------------+ o

0

20

F

E

P

NOTE

Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

INCHES

B

26.29~g:~5

1.035~8:g~~

c

10.16
11.1S±0.2

0.400
0.440±0.00S

E

LOS±0.15

0.043~8:gg9

F

0.7
3.5±0.2

0.02S
0.13S±0.00S

0

G
H

2.4±0.2

0.094~g:ggg

·K

O.S MIN.
2.6
L27(T.P.)

0.031 MIN.
0.102
0.050(T.P.)

M

0.40±0.10

0.016~g:gg~

N
P
T

0.12
9.40+0.20
0.15
RO.S5

0.005
0.370±0.00S
0.006
RO.033

U

0.20~8:6g

o.oos~g:gg~

a

P40LE·400A·2

582

!

NEe

I!
!~

IlPD421165

----~~~~~--------------------------------------------------------~~~~~~----------~!.~
1/
f,

i

Recommended Soldering Conditions

'~

I~

Please consult with our sales offices for soldering conditions of the JlPD421165.

~

Types of Surface Mount Device
JlPD421165G5: 44-pin plastic TSOP (II) (400 mil)
JlPD421165LE: 40-pin plastic SOJ (400 mil)

583

NEe
[MEMO]

584

,uPD421165

ii

II
:~

ii

;1

I
"I,

Fast Page Mode
64M Dynamic RAM

585

PRELIMINARY DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD4264400,

4265400

64 M-BIT DYNAMIC RAM
16 M-WORD BY 4-BIT, FAST PAGE MODE

Description
The .uPD4264400, 4265400 are 16,777,216 words by 4 bits dynamic CMOS RAMs. The fast page mode capability
realize high speed access and low power consumption.
These are packaged in 32-pin plastic TSOP(II) and 32-pin plastic SOJ.

Features
16,777,216 words by 4 bits organization
•

• Single +3.3 V

± 0.3 V power supply

Fast access and cycle time

Part number

Power consumption
Active (MAX.)

JiP D4264400-A50

360 mW

JiPD4265400-A50

468 mW

JiP D4264400-A60

324 mW

JiPD4265400-A60

396 mW

JiPD4264400-A70

288 mW

JiPD4265400-A70

360 mW

JiPD4264400-A80

252 mW

JiP D4265400-A80

324 mW

Standby(MAX.)

1.80 mW

Access time
(MAX.)

R/W cycle time
(MIN.)

Fast page mode
cycle time (MIN.)

50 ns

90 ns

35 ns

60 ns

110 ns

40 ns

70 ns

130 ns

45 ns

80 ns

150 ns

50 ns

(CMOS level
input)

CAS before RAS refresh, RAS only refresh, Hidden refresh
Part number

Row address

Column address

JiPD4264400

AO - A12

AO - A10

JiP D4265400

AO - A11

AO - A11

Refresh
RAS only refresh, Normal read/write

CAS before

RAS refresh, Hidden refresh

RAS only refresh, Normal read/write,

Refresh cycle
8,192 cycles/64 ms
4,096 cycles/64 ms
4,096 cycles/64 ms

CAS before RAS refresh, Hidden refresh

The information in this document is subject to change without notice.
Document No. Ml0B63EJ2VODSUl

587

NEe

yPD4264400,4265400

Ordering Information
Part number

588

Access time
(MAX.)

Package

/lPD4264400G5-A50

50 ns

/lPD4264400G5-A60

60 ns

32-pin plastic TSOP (n)

/lPD4264400G5-A70

70 ns

(400 mil)

/lPD4264400G5-A80

80 ns

Refresh

/lPD4264400LE-A50

50 ns

/lPD4264400LE-A60

60 ns

32-pin plastic SOJ

/lPD4264400LE-A70

70 ns

(400 mil)

/lPD4264400LE-A80

80 ns

RAS only refresh

/lPD4265400G5-A50

50 ns

Hidden refresh

/lPD4265400G5-A60

60 ns

32-pin plastic TSOP (n)

/lPD4265400G5-A70

70 ns

(400 mil)

/lPD4265400G5-A80

80 ns

/lPD4265400LE-A50

50 ns

/lPD4265400LE-A60

60 ns

32-pin plastic SOJ

/lPD4265400LE-A70

70 ns

(400 mil)

/lPD4265400LE-A80

80 ns

CAS before RAS refresh

NEe

yPD4264400,4265400

Pin Configurations (Marking Side)
32-pin Plastic TSOP (II) (400 mil)

32
31

GND

Vee

1/04

1/01

1/03

1/02

NC
NC

NC
NC

~t

NC
CAS

NC

OE

WE

')1;)

A12/NC·'"

Vee
1/01

2

1/02

3
4

NC
NC

5

NC
NC

6
7

WE

AO

8
9
10

A1
A2

11
12

A3

13
14
15
16

RAS

A4

A5
Vee

32-pin Plastic SOJ (400 mil)

"l::"l::
"11"11

CC
......
.,.,

NC

3
4
6
7

RAS

A11

AO

10

21

A10
A9

A1
A2

11
12

A3
A4
A5

17

A8
A7
A6
GND

13
14
15
16

(/!(/!

Vee

GND
1/04
1/03

NC
NC

5

8
9

00
00

32
31

10
2

NC
CAS

"l::"l::
"11"11

......
.,.,
cc

OE

~t

A121NC·o,"

00
00

......
mm

A11
A10
21

A9

17

A8
A7
A6
GND

Note A12 ... .uPD4264400
NC ... .uPD4265400

AO to A12
1/01 to 1/04
RAS
CAS
WE
OE

Address Inputs
Data Inputs/Outputs
Row Address Strobe
Column Address Strobe

Vee

Write Enable
Output Enable
Power Supply

GND

Ground

NC

No Connection

589

NEe

yPD4264400,4265400

Input/Output Pin Functions
The ttPD4264400, 4265400 have input pins RAS, CAS, WE, OE, Address··" and input/output pins 1/01 to 1/04.

Pin name
RAS

Input/Output
Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS

Input

(Column address strobe)
AO to Ax N...

CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.

Input

(Address inputs)

Address bus.
Input total 24-bit of address signal, upper bits and lower bits··" in sequence
(address multiplex method).
Therefore, one word is selected from 16,777,216-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (IAsR, tASe) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.

WE
(Write enable)

Input

OE
(Output enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/04
(Data inputs/outputs)

Input/Output

4-bit data bus.
1/01 to 1/04 are used to input/output data.

Note
Part number

590

Address inputs

Upper bits

Lower bits

I'PD4264400

AO-A12

13

11

I'PD4265400

AO-A11

12

12

NEe

yPD4264400,4265400

Electrical Specifications (Preliminary)
All voltages are referenced to GND.
After power up (Vcc ~ VCC(MIN.»), wait more than 1 00 !l5 (RAS, CAS inactive) and then, execute eight

CAS before

RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Symbol

Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

rnA

Condition

Power dissipation

Po

1

W

Operating ambient temperature

T.

o to +70

Storage temperature

T.,"

-55 to +125

'c
'c

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

3.0

3.3

3.6

V

High level input voltage

V,H

2.0

Vee + 0.3

V

Low level input voltage

VIL

-0.3

+0.8

V

Operating ambient temperature

T.

0

70

'c

Parameter

CapaCitance (T A

Condition

Symbol

=25 ·C, f =1 MHz)

Parameter
Input capacitance

Data input/output capacitance

MAX.

Unit

CI1

Address

5

pF

C'2

RAS, CAS, WE, OE

7

CliO

1/0

7

Symbol

Test condition

MIN.

TYP.

pF

591

NEe

yPD4264400, 4265400

DC Characteristics (Recommended operating conditions unless otherwise noted)
[ItPD4264400]
Parameter
Operating current

Standby current

Symbol
Iccl

IC02

Test condition

MIN.

=50 ns

Icco

(Fast page mode)

refresh current

10-OmA

tRAC = 70 ns

80

tRAC = 80 ns

70

RAS, CAS

~

V,H IMIN.), 10 -

a mA
a mA

1.0

RAS Cycling, CAS

~

V,H IMIN.)

a mA

=50 ns

100

tRAC - 60 ns

90

=70 ns

80

tRAC - 80 ns

70

tRAC

mA

0.5

RAS S VllIMA'<.), CAS Cycling

tRAC

=50 ns

80

tpc = tpc IMIN.), 10 = 0 mA

tRAC = 60 ns

70

=70 ns

60.

mA

1,2,3,4

mA

1,2,5

mA

1,2

50

RAS Cycling

tRAC

=50 ns

130

tRC - IRc IMIN.)

tRAC = 60 ns

110

10 = 0 mA

tRAC

=70 ns

100
90

tRAC - 80 ns

592

1,2,3

90

tRAC = 80 ns
Iccs

mA

tRAC = 60 ns

tRAC

CAS before RAS

100

tRAC

tRAC

1CC4

Notes

RAS, CAS Cycling

tAC - tAC IMIN.), 10 -

Operating current

Unit

tRC = IRc IMIN.)

RAS, CAS ~ Vee - 0.2 V, 10 RAS only refresh current

MAX.

Input leakage current

h'l)

V,=Ot03.6V
All other pins not under test - 0 V

-5

+5

pA

Output leakage current

lOll)

Vo - 0 to 3.6 V
Output is disabled (Hi-Z)

-5

+5

pA

High level output voltage

VOH

10=-2.0 mA

2.4

Low level output voltage

VOl

10= +2.0 mA

V
0.4

V

NEe

yPD4264400,4265400

[JlPD42654001
Parameter

Symbol
lee1

Operating current

Test condition
RAS, CAS Cycling
tRC

= tRC (MIN.)

10 = 0 rnA

MAX.

Unit

Notes

tRAe = 50 ns

MIN.

130

rnA

1,2,3

tRAe = 60 ns

110

tRAe = 70 ns

100

tRAe = 80 ns
Standby current

lee2

RAS only refresh current

Operating current

leco

1CC4

1.0

RAS, CAS;:' Vee - 0.2 V, 10 = 0 rnA

0.5

RAS Cycling, CAS;:' V'H (M'N.)

tRAe = 50 ns

130

tRe = tRe (M'N.), 10 = 0 rnA

tRAe = 60 ns

110

tRAe = 70 ns

100

RAS

~

V'L (MAX.), CAS Cycling

tpc = tpc (M'N.), 10 = 0 rnA

(Fast page mode)

CAS before RAS

Icc.

refresh current

90

RAS, CAS;:' V'H (M'N.), 10 = 0 rnA

tRAe = 80 ns

90

tRAe - 50 ns

80

tRAe = 60 ns

70

tRAe = 70 ns

60

tRAe = 80 ns

50

RASCycling

tRAe = 50 ns

130

= tRC (MIN.)

tRAe - 60 ns

110

tRAe = 70 ns

100

tRC

10 - 0 rnA

rnA

rnA

1,2,3,4

rnA

1,2,5

rnA

1,2

90

tRAG = 80 ns
Input leakage current

h (L)

V, = 0 to 3.6 V
All other pins not under test - 0 V

-5

+5

JJA

Output leakage current

10(L)

VO =0 to 3.6 V
Output is disabled (Hi-Z)

-6

+5

JJA

High level output voltage

VOfi

10 =-2.0 rnA

2.4

Low level output voltage

VOL

10

=+2.0 rnA

V

0.4

V

Notes 1, ICC1, Icc3, Icc4 and Icc5 depend on cycle rates (tRC and tpc).
2, Specified values are obtained with outputs unloaded.

3, Icel and Icc3 are measured assuming that address can be changed once or less during RAS :s
and CAS 2:

VIL (MAX.)

V(H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

593

NEe

yPD4264400,4265400

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions

(1) Input timing specification

(2) Output timing specification

VIH(MIN.) = 2 . 0 V - - - - - -' - - - J L -, - - - ,,
,,
VIL (MAX.) = 0.8 V·------------' :
: '
I

'

I

VOH (MIN.) = 2.0 V
VOL (MAX.)

I

------=J\...___---J}-.

=0.8V------~

_

~

-:--i-IT= 5 ns

IT = 5 ns

(3) Output load condition
VCC

1,1800

1/0 - - - T " - - - i

ClI

100 pF

8700

Common to Read, Write, Read Modify Write Cycle
IRAC

Parameler

IRAC

= 60 ns

IRAC

= 70 ns

IRAC

= 80 ns

Unil Noles
MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Read I Wrile cycle lime

IRC

90

-

110

-

130

-

150

-

ns

RAS precharge lime

IRP

30

40

-

60

-

ns

ICPN

8

10

-

50

CAS precharge lime

-

10

-

10

-

ns

RAS pulse widlh

IRAS

50

10,000

60

10,000

70

10,000

80

10,000

ns

CAS pulse widlh

ICAS

13

10,000

15

10,000

18

10,000

20

10,000

ns

RAS hold lime

tRSH

13

15

-

20

-

ns

ICSH

50

60

-

18

CAS hold lime

-

70

-

80

-

ns

RAS 10 CAS delay lime

tReD

18

37

20

45

20

52

.25

60

ns

1

RAS 10 column address delay lime

lRAO

13

25

15

30

15

35

17

40

ns

1

CAS 10 RAS precharge lime

ICRP

5

-

5

-

5

-

5

-

ns

2

Row address selup lime

IAsR

0

-

0

Row address hold lime

IRAH

8

-

10

Column address selup lime

lAse

0

-

0

Column address hold lime

ICAH

13

15

IOES

0

-

leLl

0

-

0

-

OE lead lime referenced 10

RAS

CAS 10 dala selup lime

0

-

0

-

0

10

-

12

0

-

0

15

15

0

-

0

-

0

-

0

-

0

ns
ns
ns
ns
ns
ns

OE 10 dala selup lime

lOll

0

OE 10 dala delay lime

toED

10

-

13

-

15

-

15

-

IT

3

50

3

50

3

50

3

50

ns

IREF

-

64

-

64

-

64

-

64

ms

Transilion lime (rise and fall)
Refresh lime

594

= 50 ns

Symbol

0

0

ns
ns

NEe

yPD4264400,4265400

Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAD:S tRAD IMAX.) and tRCD
tRAQ> tRAO (MAX.)

and

Access time

:s tRCD IMAX.)

tRCD ~ tRCD (MAX.)

tRCD> tRCO (MAX.)

Access time from RAS

tRAC (MAX.I

tRAC (MAX.)

tAA (MAX.)

tRAQ

+

tAA (MAX.)

teAc (MAX.)

tACO

+

teAc (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operati ng parameters.
They are used to determine which access time (tRAC, tM or tCAC) is to be used for finding out when data
will be available. Therefore, the input conditions tRAD
operation problems.

~

tRAD (MAX.) and tRCD

~

tRCD (MAX.) will not cause any

2. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
Read Cycle
Parameter

Symbol

tRAC

= 50 ns

tRAC

= 60 ns

MIN.

MAX.

MIN.

MAX.

tRAC

= 70 ns

tRAC

MIN.

MAX.

MIN.

= 80 ns

Unit Notes

MAX.

Access time from RAS

tRAC

-

50

-

60

-

70

-

80

ns

1

CAS

tCAC

-

13

15

-

20

ns

1

IAA

-

25

30

-

18

Access time from column address

-

35

40

ns

1

Access time from OE

tOEA

-

13

-

15

-

18

-

20

ns

Column address lead time
referenced to RAS

tRAl

25

-

30

-

35

-

40

-

ns

Read command setup time

tRCS

a

-

a

-

a

-

a

-

ns

Read command hold time
referenced to RAS

tRRH

a

-

a

-

a

-

a

-

ns

2

Read command hold time
referenced to CAS

tRCH

a

-

a

-

a

-

a

-

ns

2

Output buffer turn-off delay
time from OE

tOEl

a

10

a

13

a

15

a

15

ns

3

Output buffer turn-off delay
time from CAS

tOFF

a

10

a

13

a

15

a

15

ns

3

Access time from

Notes 1. For read cycles, access time is defined as follows:
Input conditions
~

Access time

Access time from RAS

tRAO (MAX.)

and

tACO

:s:

tACO (MAX.,

tRAC (MAX.)

tRAC (MAX.)

tRAO> tRAQ (MAX.)

and

tRCO

:s:

tRCO (MAX.)

tAA (MAX.)

tRAQ

+

tM (MAX.)

teAc (MAX.)

tRCD

+

teAc (MAX.)

tRAQ

tRCD> tACO (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD

~

tRCD (MAX.) will not cause

any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.

3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

595

NEe

,uPD4264400,4265400

Write Cycle
Parameter

= 50 ns

tRAe

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

8

-

10

-

10

-

15

-

-

15

WE hold time referenced to CAS

tWCH

WE pulse width

twp

8

WE lead time referenced to RAS

tRWl

13

-

WE lead time referenced to CAS

tewL

13

WE setup time

twes

0

OE hold time

tOEH

0

Data-in setup time

tos

0

-

Data-in hold time

tOH

10

-

= 60 ns

15

-

0

-

10

0
0
10

-

tRAe

= 70 ns

= 80 ns

tRAe
MIN.

Symbol

10
15
15
0

-

0

-

15

-

0

tRAe

15
15
15
0
0
0
15

-

Unit Notes
ns

1

ns

1

ns
ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late' write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle

Parameter

tRAe

=50 ns

tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

153

-

175

-

195

-

Symbol

Read modify write cycle time

tRwe

128

RAS to WE delay time

tRWO

70

CAS to WE delay time

tewD

33

-

Column address to WE delay time

tAWO

45

-

tRAe = 80 ns
Unit

38

-

53

-

83

95
43
60

-

105
45
65

-

Note

ns
ns

1

ns

1

ns

1

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
if tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ 1AWD (MIN.) and !cPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

596

NEe

ij

,uPD4264400, 4265400

------------------------------~~~~~~~--~i'

J

Fast Page Mode
Parameter

Symbol

tRAC = 50 ns
MIN.

tRAC - 60 ns

tRAC - 70 ns

tRAC = 80 ns

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Unit

Fast page mode cycle time

tpc

35

-

40

-

45

-

50

-

ns

Access time from CAS precharge

tACP

-

30

-

35

-

40

-

45

ns

RAS pulse width

tRASP

50

25,OOC

60

125,000

70

125,000

80

tcp

8

-

10

RAS hold time from CAS precharge

tRHCP

30

-

35

Read modify write cycle time

tpRWC

73

83

CAS precharge to WE delay time

tCPWD

50

-

-

CAS precharge time

58

125,000 ns

10

-

10

-

ns

40

-

45

-

ns

90

-

95

-

ns

65

70

Note

ns

1

Note 1. If twcs 2: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tAWD 2: tRWD (MIN.), tCWD 2: tCWD (MIN.), tAWD 2: tAWD (MIN.) and tCPWD 2: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

Refresh Cycle
Parameter

Symbol

tRAC - 50 ns
MIN.

MAX.

tCSR

5

tCHR

10

RAS precharge CAS hold time

tRPC

5

WE setup time

IwsR

10

WE hold time

IwHR

15

-

CAS setup time
CAS hold time

(CAS before RAS refresh)

tRAC - 60 ns

tRAC - 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

5

-

5

-

5

-

ns

-

ns

10
5
10
15

10
5
10
15

10
5
10
15

Unit

Note

no

ns.
ns

597

NEe

yPD4264400,4265400

Read Cycle

tAC
tAP

tAAS

RAS

VIH'VILtCSH

CAS

V,HVIL-

Address V,H-

VIL-

V,HVIL- L-L.L.L.L.L.t-L.L.L.~

tOlZ

tCLZ

1/0

598

VOHVOl-

Hi-Z
- - - - - - - - --- --- - -- - -- - -- --- -- - - - - - - - - - -- - -- - -- - -- ---

Data out

Hi-Z

:\i

_-...,;N.....;;...,;;E;;;;,.C=-_ _ _ _ _ _ _ _ _ _ _ _ _ _.&;.;../lP_D_4_2....;,6_44_0_0-'-,_42_6_5_4_00_ _ _--:!

I

Early Write Cycle

.l

1
tRC
tRAS

RAS

II

tRP

V",VILtCSH

CAS

V,HVIL-

Address V,H-

V,L-

V,HVIL-

1/0

......l_...l.....l.....l....l....l...,;~_...l.....l.+---!-_+-------"I_''-''-'-L-'--'--'-.L-.............'--'....................-''--

V,H-

V,L-

L-l...................................................3 I\._ _ _ _ _ _ _ _ _-JI 'II..:...........................................<....)j'-¥....................................

Remark OE: Don't care

599

NEe

yPD4264400,4265400

Late Write Cycle

tRe
tRAS

V,HV,LtesH

V,HV,L-

Address V,HV,L-

V,HV,L- L-L-L-L-'-''-''-''-'...L...J

V,HV,L-

tOED

1/0

600

V,HV,L-

~ ____ ~~~ ______ _

/\/\/\N""

L....I.................

_~N..;;;;..E=C:::"-_ _ _ _ _ _ _ _ _ _ _ _ _. . . .LJl; .;.,P. .; ; D. . ;,4; ; ;.26.; . .4;. . ;4~0. ;. c0,~4=2=6~54. ;. ;0;. .;.0- - !1
:i

Read Modify Write Cycle

!

IAWe

,
!

V,HV,L-

'i

IcSH
IReD
V,H-

IRSH

--...,.....,+-----11-\. I -_ _ _ _ _ _ICA_S_ _ _ _ _ _ _--J r--jr-----,!--

V,L-

\1

"'

Address

:1

V,HV,LIAWD
lewD

WE

V,HV,L-

IOEA

!

IOEH

I"

OE

V,HV,L-

I/O

V,HV,L-

I

lCAC

~---------

-

IDS

IDH

Dalain
.loLl

1/0 VOHVOL-

Hi-Z

Hi-Z
--------------------------------_.

601

NEe

yPD4264400,4265400

Fast Page Mode Read Cycle
IRP

tRASP

tRHCP

ICSH

Ipc

IRSH

Address V'H-

V'L-

~H-~~-r~,-t-+----t----------+r~~----------+r~~-----------r~~~~~~

V'L- 1....,j......-I.-r'-.1

V'H- ~"'''''~""T'"T'''''"r"M

+ ..........I'-''':-'--1'-++_----H~~........++----H~~........++_----.L.f''_rL................'-'-

V'L- ......->.......

1/0

VOH-

Hi-Z

VOL- - - - - - - - - - - - - - - - - - - - - - - -

Data oul

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

602

NEe

Ii'*

,uPD4264400, 4265400

--~~-----------..L.-;";"""';;;;";';;;;";;"'';;''''';'''';;;;...L......;..;;;'''';;'''';;'';''';;'''';;'---it

i

Fast Page Mode Early Write Cycle

I
,~

Address V,HV,L-

110

V,I1'

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

603

NEe

,uPD4264400, 4265400

Fast Page Mode Late Write Cycle

tRASP

RAS

tRHCP

V,HVILlesH

CAS

lpe

V,HV,L-

Address V,HV,L-

WE

V,HVIL-

OE

V,HV,L-

1/0

V,HHi-Z
V,L- .----------------

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

604

~IEC

~

I~
yPD4264400,4265400
----.,;;.....;;;.,,;;;=~---------------&:::.:.-=-=:...;;...:...::....::...!.......:..:::..::....::.....:....::....::....----ii

:i

Fast Page Mode Read Modify Write Cycle

tRASP

!

tRP

V,HV,l-

CAS

V,HV,l-

,

Address

!!

V,HV,l-

V,H-

','I

i"i

~-r..,..l~,...+=+=::!....~::::==::::;j

V,l- L-L-'--'yr....J

V,H- ...........,,.....,,...........................'"
V,l- .....l~~....l......lo..~..l....,l.,..H_-¥

1/0

VOHVOl-

1/0

V,HV,l-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

605

NEe

yPD4264400,4265400

CAS Before RAS Refresh Cycle
lAC
lRAS

VI~~~-r~--~-----r--------------~--~~----~~-r~~~.,~-r~~~r

WE

V,L-

Remark Address, OE: Don't care

110: Hi-Z

RAS Only Refresh Cycle

lRAB

ICRP

Address VI~
V,L-

Remark WE, OE: Don't care

606

1/0: Hi-Z

IRP

lRAB

__
N_E_C-=-_ _ _ _ _ _ _ _ _ _ _ _---'Jl;....P_D_4_26_4_40_0-'-,_42_6_5_40_0_ _ _
Hidden Refresh Cycle (Read)

tRC

tRC

tRAS

tRAS

I

VIH-- - - - - " ' "
Vll-

tRCD

VIH--

tRSH

tCHR

tCPN

---Ir--++------.t-.

Vll-

Address

VIH-Vll-

VIH-Vll- L-L...<..,;.....'-¥'-K.,.JI

Remark OE: Don't care

608

I\._ _ _ _-JI

~~u.r:...¥..x..¥..l~L.lI...¥..x...lt.,;IL.lL.llu.r:...¥..lt.,;¥..lL.llu.r:~

i

_ _N_E_C"--_ _ _ _ _ _ _ _ _ _ _ _ _-'Jl~P_D_4_26.;;...4....;.4..;..00.;..o:,_4_2..;..65.;;...4...;.0..;..0--- 11

i1

Package Drawings

!i

Ii

32PIN PLASTIC TSOP(II) (400 mil)

v

"

detail of lead end

-t+-----+------+

~+:tpD

D

U

IT]

01$1

M

t:r: ~

uu
u

llll
B

@I

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true pOSition (T.P.) at maximum material condition.

~J

H

;i}

J

,.,
I

L

ITEM

MILLIMETERS
21.17 MAX.
1.075 MAX.

INCHES

C

1.27 (T.P.)

0.834 'MAX.
0.043 MAX.
0.050 (T.P.)

0

0.42~g:g~

0.01HO.003

E
F

0.HO.05
1.2 MAX.
0.97
11.76tO.2
10.16tO.l

0.004tO.002
0.048 MAX.
0.038
OA63tO.008
OAOOtO.004

0.8tO.2

0.031 ~g:ggg

K

0.145~g:m

0.006tO.00l

L

0.5tO.l

0.020~g:88~

M
N

0.21
0.10
30+70
-3'

0.009
0.004

A

B

G
H
I

P

30+7"0
-3
S32G5-50-7JD2

.I

1:1

609

NEe

yPD4264400,4265400

32 PIN PLASTIC SOJ (400 mil)

B

-+-t--------+ - - - - - - - - + - u

Cl

::c

P

P32LE·400A
NOTE
Each lead centerline is located within 0.12 mm
(0.005 inch) of its true position (T.P.) at maximum material condition.

610

ITEM

MILLIMETERS

INCHES

B

21.06±0.2

0.S29±0.00S

C

10.16

0.400

D

11.1S±0.2

0.440±0.00S

E

1.005±0.1

0.040:ggg~

F

0.74

0.029

G

3.5±0.2

0.13S±0.00S

H

2.545±0.2

0.100±0.00S

I

O.S MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

0.40±0.10

0.016:g8~

N

0.12

0.005

P

9.4±0.20

0.370±0.00S

Q

0.1

0.004

T

R 0.S5

R 0.033

U

0.20:86&

0.00s:88~

PRELIMINARY DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD4264800,4265800
64 M-BIT DYNAMIC RAM
8 M-WORD BY 8-BIT, FAST PAGE MODE

Description
The ttPD4264800, 4265800 are 8,388,608 words by 8 bits dynamic CMOS RAMs. The fast page mode capability
realize high speed access and low power consumption.
These are packaged in 32-pin plastic TSOP(II) and 32-pin plastic SOJ.

Features
• Single +3.3 V ± 0.3 V power supply

8,388,608 words by 8 bits organization
•

Fast access and cycle time
Power consumption
Part number
Active (MAX.)
pPD4264S00-A50

37SmW

pPD4265S00-A50

4S6 mW

pPD4264S00-A60

342 mW

pPD4265S00-A60

414 mW

pPD4264S00-A70

306 mW

pPD4265S00-A70

37SmW

pPD4264S00-ASO

270 mW

pPD4265S00-ASO

342mW

Standby(MAX.)

1.S0mW
(CMOS level
input)

Access time
(MAX.)

RIW cycle time
(MIN.)

Fast page mode
cycle time (MIN.)

50 ns

90 ns

35 ns

60 ns

110 ns

40 ns

70 ns

130 ns

45 ns

SO ns

150 ns

50 ns

CAS before RAS refresh, RAS only refresh, Hidden refresh
Row address

Column address

pPD4264S00

Part number

AO - A12

AO - A9

pPD4265S00

AD - All

AD - Al0

Refresh
RAS only refresh, Normal read/write

Refresh cycle
S, 192 cycles/64 ms

CAS before RAS refresh, Hidden refresh

4,096 cycles/64 ms

RAS only refresh, Normal read/write,

4,096 cycles/64 ms

CAS before RAS refresh, Hidden refresh

The information in this document is subject to change without notice.
Document No. Ml0864EJ2VODSUI

611

NEe

yPD4264800,4265800

Ordering Information
Part number

612

Access time
(MAX.)

jlPD4264800G5-A50

50 ns

jlPD4264800G5-A60

60 ns

jlPD4264800G5-A70

70 ns

jlPD4264800G5-A80

80 ns

jlPD4264800LE-A50

50 ns

Package

32~pin

Refresh

plastic TSOP (U)
(400 mil)

jlPD4264800LE-A60

60 ns

32-pin plastic SOJ

jlPD4264800LE-A70

70 ns

(400 mil)

jlPD4264800LE-ABO

80 ns

RAS only refresh

jlPD4265800G5-A50

50 ns

Hidden refresh

jlPD4265800G5-A60·

60 ns

32-pin plastic TSOP (U)

jlPD4265800G5-A70

70 ns

(400 mil)

jlPD4265800G5-A80

80 ns

jlPD4265800LE-A50

50 ns

jlPD4265800LE-A60

60 ns

32-pin plastic SOJ

jlPD4265800LE-A70

70 ns

(400 mil)

jlPD4265800LE-A80

80 ns

CAS before RAS refresh

!:-i
"

NEe

Il

yPD4264800, 4265800

it
i~

Pin Configurations (Marking Side)

il

32-pin Plastic TSOP (ll) (400 mil)

il

32-pin Plastic SOJ (400 mil)

32

GND

Vee

10

32

GND

31

1/08

1/01

2

31

1/08

3

1/07

1/02

3

30

1/07

1/03

4

1/06

1/03

4

29

1/06

1/04

5

1/05

1/04

5

28

1/05

NC

6

GND

NC

6

27

GND

Vee

7

CAS

Vee

7

26

CAS

WE

8

OE

WE

8

OE

RAS

9

RAS

9

"''''....
en
"''''
~~

25

00

24

A121NC·'"

mm

23

A11

Vee

1/01

2

1/02

1::1::
"V "V

CC
........
"''''
Ill:
......

88
G)G)

A121NC··"

en en

1::1::
"V "V

cc
........

....

AD

10

A11

AD

10

A1

11

A10

A1

11

22

A10

A2

12

A9

A2

12

21

A9

A3

13

A8

A3

13

20

A8

A4

14

A7

A4

14

19

A7

A5

15

A6

A5

15

Vee

16

Vee

16

17

GND

A6

17

GND

Note A 12 ... jlPD4264800
NC ... jlPD4265800

AO to A12

Address Inputs

1/01 to 1/08

Data Inputs/Outputs

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

Ii

613

NEe

yPD4264800,4265800

Input/Output Pin Functions
The pPD4264800, 4265800 have input pins RAS, CAS, WE, DE,

Pin name

AddressN~.

Input/Output

and input/output pins 1/01 to 1/08.

Function

RAS
(Row address strobe)

Input

CAS

Input

CAS activates data input/output circuit by latching column address and

Input

Address bus.

(Column address strobe)
AO to Ax""
(Address inputs)

RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

selecting a digit line connected with the sense amplifier.

Input total 23-bit of address Signal, upper bits and lower bits"" in sequence
(address multiplex method).
Therefore, one word is selected from 8,388,50B-word by B-bit memory cell
array.
In actual operation, latch row address by specifying row address and
,activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (IAsR, tAse) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.

WE

Input

OE

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

(Write enable)
Input

(Output enable)

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/08
(Data inputs/outputs)

Input/Output

B-bit data bus.
1/01 to 1/08 are used to input/output data.

Note
Part number

614

Address inputs

Upper bits

Lower bits

JlPD4264800

AO-A12

13

10

JlPD4265800

AO-A11

12

11

NEe

yPD4264800, 4265800

Electrical Specifications (Preliminary)
All voltages are referenced to GND.
After power up(Vcc

~

VCC(MIN.)), wait more than 100 Jls (RAS, CAS inactive) and then, execute eight CAS

before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

mA

Power dissipation

Po

1

W

Operating ambient temperature

TA

o to +70

·C

Storage temperature

Tstg

-55 to +125

·C

Caution

Symbol

Condition

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Supply voltage

Parameter

Vee

3.0

3.3

3.6

V

High level input voltage

V,H

2.0

Vee + 0.3

V

Low level input voltage

Vil

-0.3

+0.8

V

70

·C

Operating ambient temperature

Capacitance (TA

Symbol

Condition

TA

0

Unit

=25 ·C, f =1 MHz)

Parameter
Input capacitance

Data input/output capacitance

MAX.

Unit

C"

Address

5

pF

C"

RAS, CAS, WE, OE

7

ClIO

I/O

7

Symbol

Test condition

MIN.

TYP.

pF

Ii

IlI;i
j

I

I

615

~

NEe

yPD4264800,4265800

DC Characteristics (Recommended operating conditions unless otherwise noted)

[jlPD4264800j
Parameter
Operating current

Symbol
Ice1

MAX.

Unit

Notes

RAS, CAS cycling

Test condition
tRAe = 50 ns

MIN.

105

mA

1,2,3

tRe = tRe (M'N.)

tRAe = 60 ns

95

10 = 0 mA

tRAe = 70 ns

85

tRAe = 80 ns
Standby cu rrent

IC02

RAS, CAS" V'H (M'N.),

75
1.0

10 = 0 mA

RAS only refresh current

Operating current

Ice3

1004

tRAe = 50 ns

105

tRAe = 60 ns

95

tpc = tpe (M'N.), 10 =

(Fast page mode)

CAS before RAS

RAS cycling, CAS" V'H (M'N.)
tRe = tRe (M'N.), 10 = 0 mA

RAS S VIL (MAX.), CAS cycling

Ice5

refresh current

a mA

tRAe = 70 ns

85

tRAe = 80 ns

75

tRAe = 50 ns

85

tRAe = 60 ns

75

tRAC = 70 ns

65

tRAC = 80 ns

55

RAS cycling

tRAC = 50 ns

135

tRC = tRC (M'N.)

tRAe = 60 ns

115

10 = 0 mA

tRAe = 70 ns

105

I'(L}

V, = a to 3.6 V

mA

1,2,3,4

mA

1,2,5

mA

1,2

95

tRAC = 80 ns
Input leakage current

mA

0.5

RAS, CAS" Vee - 0.2 V, 10 = 0 mA

-5

+5

p.A

+5

p.A

All other pins not under test = 0 V

616

Output leakage current

10(L}

VA = 0 to 3.6 V
Output is disabled (Hi-Z)

-5

High level output voltage

VOH

10 =-2.0 mA

2.4

Low level output voltage

VOL

10 = +2.0 mA

V
0.4

V

NEe

yPD4264800,4265800

I

[ttPD42658001
Parameter
Operating current

Symbol
Icc1

RAS only refresh current

Icc3

=

tRC (MIN.)

= 0 mA

10

Icc>

(Fasl page mode)

CAS before RAS

135

mA

1,2,3

tRAC

115

~

10

105
95
1.0

= 0 mA

V,LIMAX.}, CAS cycling

= tpc IMIN.), 10 = 0 mA

RAS cycling

V, = 0 to 3.6 V
All other pins not under test

Output leakage current

lOlL)

Vo = 0 to 3.6 V
Output is disabled (Hi-Z)

High level output voltage

VOH

10

= -2.0 mA

Low level output voltage

VOL

10

= +2.0 mA

mA

0.5

= 50 ns
tRAC = 60 ns
tRAC = 70 ns
IRAC = 80 ns
IRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns

tRC

I'IL)

tRAC

tRAC

= tRC IMIN.)
10 = 0 mA

refresh current

Input leakage current

= tRC IMIN.},

RAS
tpc

Icc.

Notes

10

RAS cycling, CAS" V,H IMIN.)
tRC

Icc.

Unit

= 0 rnA
0.2 V, 10 = 0 mA

RAS, CAS " V,H IMIN.),
RAS, CAS" Vcc -

Operating currenl

MAX.

= 50 ns
= 60 ns
tRAC = 70 ns
tRAC = 80 ns

RAS, CAS cycling
tRC

Standby current

MIN.

Test condition

135

mA

1,2,3,4

mA

1,2,5

mA

1,2

115
105
95
85
75
65
55
135
115
105
95
-5

+5

J1A

-5

+5

ttA

=0 V

V

2.4
0.4

V

Notes 1. Icc1, Icc3, Icc4 and Icc5 depend on cycle rates (tRC and tpc).
2. Specified values are obtained with outputs unloaded.
3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS

~ V,L (MAX.)

and CAS" V,H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.

5. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

617

NEe

yPD4264800,4265800

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

(2) Output timing specification

VIH(MIN.)=2.0V---------~-----'
.
'
,,
,,

VOH(MIN.) =2.0V------~

VIL (MAX.) = 0.8 V·------------ ' :

VOL (MAX.) = 0.8 V------==\-I...
____--'

•

: '

,

,

}-

t

. : :.

---+l---+--

tr=5ns

tr=5ns

(3) Output load condition

VCC

1,1800
I/O ---r-----o

r

100 pF
CL

8700

Common to Read, Write, Read Modify Write Cycle
Parameler

= 50 ns

IRAC

MIN.

MAY.

MIN.

Read I Wrile cycle lime

IRC

90

RAS precharge lime

IRP

30

CAS precharge lime

ICPN

8

-

= 60 ns

lRAC

= 70 ns

lRAC

= 80 ns

Unil Noles

MAX.

MIN.

MAX.

130

-

150

-

60

-

ns

50

10

-

ns

MAX.

MIN.

110

-

40

-

10

-

10

ns

RAS pulse widlh

IRAS

50

10,000

60

10,000

70

10,000

80

10,000

ns

CAS pulse widlh

lCAS

13

10,000

15

10,000

18

10,000

20

10,000

ns

RAS hold lime

IRSH

13

-

15

-

18

-

20

ICSH

50

-

60

-

70

-

80

-

ns

CAS hold lime
RAS 10 CAS delay lime

tRCO

18

37

20

45

20

52

25

60

ns

RAS 10 column address delay lime

IRAD

13

25

15

30

15

35

17

40

ns

1

CAS 10 l'iAS precharge lime

ICRP

5

-

5

-

5

-

5

-

ns

2

Row address selup lime

IASR

0

-

0

-

0

-

0

-

ns

10

-

10

-

12

-

ns

0

-

0

0

-

ns

15

-

15

15

-

ns

0

-

0

-

0

ns

ns

ns

Row address hold time

lRAH

8

Column address selup lime

IASC

0

Column address hold lime

ICAH

13

OE lead lime referenced 10 RAS

IOES

0

-

CAS 10 dala selup lime

IcLZ

0

-

0

-

0

-

0

OE 10 dala selup lime

loLZ

0

-

0

-

0

-

0

-

OE 10 data delay lime

toeD

10

-

13

-

15

-

15

-

tr

3

50

3

50

3

50

3

50

ns

tREF

-

64

-

64

-

64

-

64

ms

Transilion lime (rise and fall)
Refresh lime

618

IRAC
Symbol

ns
ns

1

NEe

yPD4264800,4265800

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time from RAS

Access time

tRAD (MAX.)

and

tRCO

$

tRCO (MAX.)

tRAC (MAX.)

tRAG (MAX.)

tRAQ> tRAQ (MAX.)

and

tRCD

$

tRCO (MAX.)

tAA (MAX.)

tRAD

+ tAA (MAX,)

tcAC (MAX.)

tRCO

+ tcAC (MAX.)

tRAD

$

tACO> tACO (MAX.)

tRAO (MAX.) and tRGD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAG, tAA or tCAG) is to be used for finding out when data
will be available. Therefore, the input conditions tRAD

~

tRAD (MAX.) and tRCD

~

tRCD (MAX.) will not cause any

operation problems.
2. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
Read Cycle
tRAG

= 50

= 60

ns

tRAG

MIN.

MAX.

MIN.

MAX.

ns

tRAG

= 70

ns

tRAG

= 80

ns
Unit

Symbol

Parameter

MIN.

Notes

MAX.

MIN.

MAX.

60

-

70

-

80

ns

1

15

18

ns

1

35

40

ns

1

18

-

20

15

-

20

ns

Access time from RAS

tRAG

-

50

Access time from CAS

tCAC

-

13

-

25

tOEA

13

-

tRAL

25

-

30

-

35

-

40

-

ns

tACS

0

-

0

-

0

-

0

-

ns

tRRH

0

-

0

-

0

-

0

-

ns

2

tRCH

0

-

0

-

0

-

0

-

ns

2

tOEZ

0

10

0

13

0

15

0

15

ns

3

tOFF

0

10

0

13

0

15

0

15

ns

3

tAA

Access time from column address
Access time from OE
Column address lead time

--

referenced to RAS

Read command setup time
Read command hold time
referenced to RAS
Read command hold time

--

referenced to CAS

Output buffer turn-off delay
time from OE
Output

bu~urn-off

delay

time from CAS

30

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD (MAX.)

and

tRCO

$

tACO (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAQ (MAX.)

and

tACO

$

tACO (MAX.)

tAA (MAX.)

tRAD

+

tCAC (MAX.)

tACO

+ tCAC (MAX.)

tRAQ

$

tRCO> tRCO (MAX.)

tAA (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAG, tAA or tCAG) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRGD (MAX.) will not cause
any operation problems.

2. Either tRGH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF(MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced

to VOH or VOL.

619

NEe

yPD4264800,4265800

Write Cycle
Parameler

Symbol

IRAC = 50 ns

IRAC = 60 ns

IRAC = 70 ns

IRAC = 80 ns
Unil Noles

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

IWCH

8

-

10

-

10

-

15

-

ns

1

WE pulse widlh

Iwp

8

-

10

-

10

-

15

-

ns

1

WE lead lime referenced 10 ~

IRWL

13

-

15

-

ns

13

-

15

-

15

ICWL

-

15

WE lead lime referenced 10 CAS

15

-

ns

WE selup lime

twcs

0

-

0

-

0

-

0

-

ns

~holdlime

IOEH

0

0

-

0

-

0

-

ns

0

-

0

-

0

-

ns

3

10

-

15

-

15

-

ns

3

WI::

hold lime referenced 10 CIUl

Dala-in selup lime

los

0

-

Dala-in hold lime

IOH

10

-

15

2

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. I n early write cycles, tWCH (MIN.) should
be met.
2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
IRAC = 60 ns

IRAC = 70 ns

IRAc = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

lRAC = 50 ns
Parameler

Unil

Symbol

Nole

Read modify wrile cycle lime

IRwc

128

-

153

-

175

-

195

-

ns

RAS 10 WE delay lime

IRwo

70

-

83

-

95

-

105

-

ns

1

CAS 10 WE delay lime

lewD

33

38

-

45

-

ns

1

tAWD

45

-

43

Column address 10 WE delay lime

-

60

-

65

-

ns

1

53

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

620

NEe

yPD4264800,4265800

Fast Page Mode
tRAC
Parameter

= 50

= 60 ns

ns

tRAC

MIN.

MAX.

MIN.

MAX.

MIN.

tRAC

-

40

-

= 70

ns

tRAC

= 80

ns

Symbol

Unit
MIN.

45

-

50

-

ns

-

45

ns

tpc

35

tACP

-

30

-

35

-

40

tRASP

50

125,000

60

125,000

70

125,000

80

125,000

ns

tep

8

10

-

10

tRHCP

30

35

-

40

tPRWC

73

83

-

90

95

-

ns

Read modify write cycle time

58

-

-

10

RAS hold time from CAS precharge

-

70

-

ns

Fast page mode cycle time
Access time from CAS precharge
RAS pulse width
CAS precharge time

CAS precharge to WE delay time

tCPWD

50

65

Note

MAX.

MAX.

45

ns

ns
1

Note 1. If twes ~ twes (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD

~

tRWD (MIN.), tewD ~ tCWD (MIN.), tAWD

~

tAWD (MIN.) and tepwD

~

tCPWD (MIN.), the cycle is a read modify write

cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
Refresh Cycle
tRAC
Parameter

= 50

= 60

ns

tRAC

= 70 ns

tRAC

tRAC

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

ns

5

5

5

-

5

10

10

-

10

-

5

-

5

-

ns

-

ns

Unit

CAS hold time (CAS before RAS refresh)

tCHR

10

-

RAS precharge CAS hold time

tRPe

5

-

5

-

WE setup time

tWSR

10

10

-

10

-

10

WE hold time

tWHR

15

-

15

-

15

-

15

CAS setup time

= 80

ns

MIN.

Symbol
tCSR

Note

ns
ns

ns

621

NEe

yPD4264800,4265800

Read Cycle
lAC
lriAs
RAS

IR.

V,HV,L-

ICSH

CAS

V,HV,L-

Address

V,iiV,L-

V,iiV,L-

OE

V,HV,LlCAC
012

leLl

VOH-

1/0 VOL-

622

----------------~~~--------------------------------

Hi-Z
--------_.

NEe

pPD4264800,4265800

Early Write Cycle
tRC
tRAS

RAS

tRP

V,HV,LtCSH

CAS

V,HV,L-

Address

V,HV,L-

WE

1/0

V,L- .....J~~~~~~l...J'-+-II-+______+~:.....L....L...L..L..,j~....L...L...L....~:.....L....L..L-

V,HV,L-

Remark

L.>........................................"""" ....._ _ _ _ _ _ _ _....JI ...........'-"-_ _"'--'............_ _......................................

UJ::

Don't care

623

NEe

pPD4264800,4265800

Late Write Cycle
lAC
V,HV,L-

V,HV,L-

Address

V,HV,L-

WE

V,H-

OE

V,H-

V,L-

V,L-

toeD
1/0

624

V,H- ~nn~t~
VIL-~

_____ n

_ _N_E.....;C~_ _ _ _ _ _ _ _ _ _ _ _ _--LJl_P_D_4_2_64_8_0_0,'-4_2_6_5_80-0----:1

IJ

Read Modify Write Cycle
tRWC
tRAS
V,HV,L-

,>

1
tCSH
tRCO

tRSH

tCAS
CAS

Address

V,HV,LtAWO
tcwo

WE

V,HV,L-

DE

VIHV,L-

tOEH

tOEA

tCAC

110

V,HV,L-

~---------

-

tos

tOH
Data in

tOll

110

VOHVOL-

Hi-Z

Hi-Z

625

NEe·

yPD4264800,4265800

Fast Page Mode Read Cycle
lRASP
IRHCP

ICSH

Ipc

lASH

V'H- -.y..,.-++----h
VIL-

Address

~H- ~-r~7-~~--~----~~T-r-----~~~-----+-~~-r~~

VIL-

L...'-I'-'+.J

1/0 VOl+VOL-

Dala oul

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

626

NEe

yPD4264800,4265800

Fast Page Mode Early Write Cycle

V,HV,L-

Address

V,HV,L-

1/0

V,HV,L-

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

627

NEe

yPD4264800,4265800

Fast Page Mode Late Write Cycle

tRASP

RAS

V,HV,L-

CAS

V,HVIL-

tRHCP

Address

OE

1/0

Hi-Z
.----------------

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

628

NEe

yPD4264800,4265800

Fast Page Mode Read Modify Write Cycle

Vi....
VIL-

Vi ....
VIL-

Address

V,HVIL-

WE

V,HVIL-

Vi....
VIL-

I/O

Vo....
VOL-

1/0

V,HVIL-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

629

NEe

yPD4264800,4265800

CAS Before RAS Refresh Cycle

tRAS

Remark Address, OE: Don't care

110: Hi-Z

RAS Only Refresh Cycle

InAS

V,HVIL-

leRP

Address

Remark WE, OE: Don't care

630

1/0: Hi-Z

IRP

IRAS

NEe

yPD4264800,4265800

Hidden Refresh Cycle (Write)
tRC

tRC

tRAS

tRAS

V,HVIL-

CAS

Address

V,H-

V,L-

1/0

V,H-

V,L- .....'-"'-"...1<.-><-.............."--'''-''

Remark OE: Don't care

632

-+_-+_'l-t.......J

.....l........-'-~.....~~.........,.._ _

I\..-_ _ _ _JI

"...1<..........................,.......'-"-"--"-................"'--'''-'........'-''......-''-.......................

NEe

pPD4264800,4265800
,

Package Drawings

i

32PIN PLASTIC TSOP(II) (400 mil)

'I

,

I
j

17

32

detail of lead end

+-+------+------+--

U II U

':fL
B

NOTE

Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

L

ITEM

MILLIMETERS

A
B

21.17 MAX.
1.075 MAX.

0.043 MAX.

C

1.27 (T.P.)

0.050 (T.P.)

0

0.42~8:8~

0.017±0.003

E

0.HO.05
1.2 MAX.
0.97
11. 76±0.2

0.004±0.002
0.048 MAX.
0.038
0.463±0.008

10.16±0.1

0.400±0.004

0.8±0.2

0.031~8:8g5

K

0.14S~8:8f~

0.006±0.001

L

0.S±0.1

0.020~8:8g~

M

0.21

0.009

N

0.10

0.004

P

3 0 + 70
-3·

F

G
H

INCHES
0.834 MAX.

3 +70
-3·
0

S32G5-50-7JD2

633

NEe

yPD4264800,4265800

32 PIN PLASTIC SOJ (400 mil)

B

-++--------+ - - - - - - - _ + _ U

0

P32LE-400A

NOTE
Each lead centerline is located within 0.12 mm
(0.005 inch) of its true position (T.P.) at maximum material condition.

634

ITEM

MILLIMETERS

INCHES

B

21.06±0.2

C

10.16

0.B29±0.00B
0.400

D

11.1B±0.2

O.440±0.00B

E

1.005±0.1

0040:,:ggg~

F

0.74

0.029

G

3.5±0.2

O.13B±0.00B

H

2.545±0.2

0.100±0.00B

I

O.B MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P)

M

0.40±0.10

0.016:,:ggg~

N

0.12

0.005

P

9.4±0.20

O.370±0.OO8

Q

0.1

0.004

T

R 0.B5

R 0.033

U

0.20:,:g6g

OOOB:,:ggg~

PRELIMINARY DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD4264160,4265160
64 M-BIT DYNAMIC RAM
4 M-WORD BY 16-BIT, FAST PAGE MODE

Descriptio"
The JLPD4264160, 4265160 are 4,194,304 words by 16 bits dynamic CMOS RAMs. The fast page mode capability
realize high speed access and low power consumption.
These are packaged in 50-pin plastic TSOP(II).

Features
• Single +3.3 V ± 0.3 V power supply

4,194,304 words by 16 bits organization
•

Fast access and cycle time
Power consumption
Part number
Active (MAX.)

Standby(MAX.)

JlPD4264160-A50

396 mW

JlPD4265160-A50

504mW

1.BOmW
(CMOS level

JlPD4264160-A60

360mW

JlPD4265160-A60

432mW

JLPD4264160-A70

324mW

JlPD4265160-A70

396mW

JlPD4264160-ABO

2BBmW

JlPD4265160-ABO

360mW

Access time
(MAX.)

RIW cycle time
(MIN.)

Fast page mode
cycle time (MIN.)

50 ns

90 ns

35 ns

60 ns

110 ns

40 ns

70 ns

130 ns

45 ns

80 ns

150 ns

50 ns

input)

CAS before RAS refresh, RAS only refresh, Hidden refresh
Part number
JLPD4264160

JlPD4265160

Row address

Column address

AO - A12

AO-AS

AO - All

AD -A9

Refresh

Refresh cycle

RAS only refresh, Normal read/write

B,192 cycles/64 ms

mrn before RAS refresh, Hidden refresh

4,096 cycles/64 ms

RAS only refresh, Normal read/write,

4,096 cycles/64 ms

CAS before RAS refresh, Hidden refresh

The information in this document is subject to change without notice.
Document No. M10862EJ2VODSU1

635

NEe

yPD4264160, 4265160

Ordering Information
Access time
(MAX.)

Package

SO ns

SO-pin plastic TSOP (U)

/lPD4264160G5-A60

60 ns

(400 mil)

/lPD4264160GS-A70

70 ns

/lPD4264160GS-A80

80 ns

/lPD426S160GS-ASO

SO ns

/lPD426S160GS-A60

60 ns

Part number
/lPD4264160G5-A50

636

/lPD4265160GS-A70

70 ns

/lPD426S160GS-A80

80 ns

Refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh

_.--;;...N.;;;...E=..;;;C~_ _ _ _ _ _ _ _ _ _ _ _- -,JL; ;.;.P. . .; D. . ;.4.; ; .26;. . ;4;.,; .1.; ;. .60; .&.,. . ;.4.; ; .26; . .;5;. .; .1. ; . 6o~- -.;. ~il
:j

Pin Configuration (Marking Side)

50-pin Plastic TSOP (II) (400 mil)

!
1·1'

50

Vee

1/01

1/016

1102

1/015

1/03

1/014

1/04

1/013

Vee

GND

1105

1/012

1/06

1/011

1/07

1/010

1/08

l::l::
'V 'V

NC
WE

II
18

A3
A4
A5
Vee

t

1/09

OE

17

A2

:~~

NC
GND
LCAS
UCAS

Ii
......

Vee

RAS
NC
NC
NC
NC
AD
Al

41

i

GND

31

NC
NC
A121NCAll
Al0
A9
A8
A7
A6
GND

Note A12 ... JlPD4264160
NC ... JlPD4265160

Address Inputs
AO to A12
1/01 to 1/016 : Data Inputs/Outputs
RAS
Row Address Strobe
UCAS
Upper Byte Column Address Strobe
LCAS
Lower Byte Column Address Strobe
WE
Write Enable
OE
Output Enable
Vee
Power Supply
GND
Ground
NC
No Connection

637

NEe

yPD4264160, 4265160

Input/Output Pin Functions
The J'PD4264160, 4265160 have input pins RAS, UCAS, LCAS, WE, OE, AddressN' " and input/output pins
1/01 to 1/016.

Pin name

Input/Output

Function

RAS
(Row address str.obe)

Input

RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selacts the following function.
• CAS before RAS refresh

UCAS, LCAS
(Upper, Lower column
address strobe)

Input

UCAS, LCAS activates data input/output circuit by latching column address
and selecting a digit line connected with the sense amplifier.

AOtoAx(Address inputs)

Input

Address bus.
Input total 22-bit of address signal, upper bits and lower bitsNoto in sequence
(address multiplex method).
Therefore, one word is selected from 4,194,304-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address Input setup time (IAsR, tASe) and hold time (tRAH, tOAH)
are specified for the activation of RAS and CAS.

WE

Input

Wr~e

(Wr~e

Wr~e

enable)

control signal.
operation is executed by activating RAS, CAS and WE.

OE
(Output enable)

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
II WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/016
(Data inputs/outputs)

Input/Output

16-bit data bus.
1/01 to 1/016 are used to Input/output data.

Note
Address Inputs

Upper bits

Lower bits

pPD4264160

AO-AI2

13

9

pPD4265160

AO-All

12

10

Part number

638

__

~N_E~C~________________________~y~P~D~4~26~4~1~60~,~4~26~5~1~60~____~I

if

l

Electrical Specifications (Preliminary)
•

II

!,

CAS means UCAS and LCAS.
All voltages are referenced to GND.

,
~;

After power up (Vee ~ VeC(MIN.), wait more than 100 JlS (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Condition

Symbol

Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

mA

Power dissipation

PD

1

W

Operating ambient temperature

T.

o to +70

"C

Storage temperature

TSIg

-55 to +125

"C

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described In the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

3.0

3.3

3.6

V

2.0

Vee + 0.3

V

-0.3

+0.8

V

70

"C

Supply voltage

Vee

High level input voltage

V,H

Low level input voltage

V,L

Operating ambient temperature

T.

0

Capacitance (TA

r

=25 ·C, f = 1 MHz)

Parameter

!
I

MAX.

Unit

Address

5

pF

Test condition

Symbol

MIN.

TYP.

Input capacitance

C"
C'2

RAS, CAS, WE, OE

7

Data input/output capacitance

Coo

1/0

7

II

pF

639

NEe

yPD4264160,4265160

DC Characteristics (Recommended operating conditions unless otherwise noted)

IIlPD4264160]
Parameter
Operating current

Symbol
ICCI

Test condition

MAX.

Unit

Notes

RAS, CAS Cycling

tRAe _ 50 ns

MIN.

110

mA

1,2,3

tRe = tAC (MIN.)

tRAe

=60 ns

100

10-OmA

tRAC - 70 ns

90

tRAC = 80 ns
Standby current

RAS only refresh current

Iceo

Icc>

~

V,H (MIN.), 10 - 0 mA

1.0

RAS, CAS

~

Vce - 0.2 V, 10 _ 0 iliA

0.5

RAS Cycling, CAS
tRC

Operating current

IcC4

(Fast page mode)

80

RAS, CAS

=tAC

(MIN.),

~

V,H (MIN.)

10 =0 mA

RAS S V,L (MAX.), CAS Cycling
tpc

=tpc

(MIN.),

10 =0 mA

=50 ns

110

tRAC - 60 ns

100

tRAC = 70 ns

90

tRAC

tRAC - 80 ns

80

tRAC - 50 ns

90

tRAe - 60 ns

80

=70 ns

70

tRAC

Icc.

refresh current

640

mA

1,2,3.4

mA

1,2,5

mA

1,2

60

tRAC - 80 ns
CAS before RAS

mA

RAS Cycling

tRAe

=50 ns

140

tRC = tRC (MIN.)

tRAC - 60 ns

120

10=OmA

tRAe

=70 ns
tRAC =80 ns

110
100

Input leakage current

h(l)

V, = Oto 3.6 V
All other pins not under test - 0 V

-5

+5

pA

Output leakage current

10(1l

Vo =Oto 3.6 V
Output is disabled (Hi-Z)

-5

+5

pA

High level output voltage

VOH

10--2.0 mA

2.4

Low level output voltage

VOL

10- +2.0 mA

V
0.4

V

NEe

yPD4264160,4265160

[/lPD426S1601
Parameter

Symbol
Icc,

Operating current

Test condition
RAS. CAS Cycling
tAC

10

Standby current

Icc2

=

tAC (MIN.)

= a mA

R7iS. CAS;" V'H (MIN.j,

MAX.

Unit

Notes

tRAC = 50 ns

MIN.

140

mA

1.2.3

tRAC = 60 ns

120

tRAC = 70 ns

110

tRAC = 80 ns

100
1.0

10 = 0 mA

RAS. CAS;" Vcc - 0.2 V. 10 = 0 mA
RAS only refresh current

Icc.

RAS Cycling. CAS;" V,H (MIN.)

tRAC = 50 ns

140

tRC (MIN.). 10 = 0 mA

tRAC = 60 ns

120

tRAC = 70 ns

110

tRAC = 80 ns

100

RAS S V,L (MAX.). CAS Cycling

tRAC = 50 ns

90

tpc = tee (MIN.). 10 = 0 mA

tRAC = 60 ns

80

tRC

Operating current

IcC4

(Fast page mode)

CAS before RAS

Icc.

refresh current

a

tRAC = 70 ns

70

tRAC = 80 ns

60

~Cycling

tRAC = 50 ns

140

tRC -

tRAC = 60 ns

120

= 70 ns

110

tRC (MIN.)

10 = 0 mA

tRAC

mA

0.5
mA

1.2.3,4

mA

1.2.5

mA

1.2

100

tRAC = 80 ns
Input leakage current

II (L)

V, - 0 to 3.6 V
All other pins not under test = 0 V

-5

+5

J1A

Output leakage current

10(L)

Vo = 0 to 3.6 V
Output is disabled (Hi-Z)

-5

+5

J1A

High level output voltage

VOH

10 =-2.0 mA

2.4

Low level output voltage

VOL

10 = +2.0 mA

V

0.4

V

Notes 1. ICC1, Icc3, Icc4 and Iccs depend on cycle rates (tRC and tpc).

2. Specified values are obtained with outputs unloaded.

3. ICCl and Icc3 are measured assuming that address can be changed once or less during RAS :5 V(L (MAX.)
and CAS;::

V,H (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

641

NEe

yPD4264160,4265160

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

(2) Output timing specification

VIH(MIN.) =2.0V---------~----'
,
V,L (MAX.) - 0.8 V·------------ '
I

,

,

VOH (MIN.) = 2.0 V

1

1'

VOL (MAX.)

I

,

I

.l: .

~
tr=5ns

------=J

'--_

=0.8V------~I..._ _ _ _~_f

tr-5ns

(3) Output load condition
Vee
1,1800

I/O - - - - r - - - ;
100pF

CLI

8700

Common to Read, Write, Read Modify Write Cycle
lRAe = 50 ns
Parameler

lRAe = 60 ns

IRAe = 70 ns

IRAe = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

IRc

90

-

110

-

130

-

150

ns

Symbol

Unit Notes

RAS precharge lime

IRP

30

-

40

-

60

IePN

8

-

10

-

50

CAS precharge lime

10

-

10

-

RAS pulse widlh

lRAS

50

10,000

60

10,000

70

10,000

80

10,000

ns

leAS

13

10,000

15

10,000

18

10,000

20

10,000

ns

15

20

-

ns

80

-

ns

Read I Wrile cycle time

CAS pulse widlh

ns
ns

RAS hold lime

IRSH

13

CAS hold lime

IeSH

50

-

60

-

70

-

tReD

18

37

20

45

20

52

25

60

ns

1

IRAD

13

25

15

30

15

35

17

40

ns

1

CAS to RAS precharge time

teRP

5

-

5

-

ns

2

0

0

-

0

0

-

ns

Row address hold lime

IRAH

8

-

10

-

10

12

-

ns

Column address setup time

lASe

0

-

0

-

0

-

.5

IASR

-

5

Row address selup lime

0

-

ns

Column address hold lime

tCAH

13

-

15

-

15

-

15

-

ns

OE lead lime referenced 10 RAS

IOES

0

0

-

0

-

0

ns

CAS 10 dala selup lime

teLZ

0

0

-

0

-

0

OE to data setup time

loLZ

0

-

0

OE to data delay lime

tOED

Masked byte wrile hold time

IMRH

RAS 10

m

CAS delay lime

to column address delay time

18

0

-

0

10

-

13

15

-

15

0

-

-

-

0

-

0

-

0

-

ns

tr

3

50

3

50

3

50

3

50

ns

tREF

-

64

-

64

-

64

-

64

ms

ns
ns
ns

referenced 10 RAS
Transition lime (rise and fall)
Refresh lime

642

_~N..;;..E=-.;;C~_ _ _ _ _ _ _ _ _ _ _ _ _...£Jl::;.:.P-=D;,...:.4=.;26::....:4:...:.1-=..60::.!,......:4:.=2.=.:65::...:1:..::6-=..0_ _ _

1
;

!:t

Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAO ~ tRAQ (MAX.)

and

tRCO ~ tRCO (hotAX.)

tRAO> tRAD (MAX.)

and

tRCo

tRCo

>

:s;

Access time

tACO (MAX.)

tRCO (MAX.)

Access time from RAS

tRAC (MAX.)

tRAC (MAX.)

tM IMAX.)

tRAQ

+ tAA (MAX.)

teAc (MAX.)

tRCO

+ teAc (MAX.)

tRAO(MAX.) and tRCO(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAO ~ tRAO (MAX.) and tRCO ~ tRCO (MAX.) will not cause
any operation problems.
2. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

Read Cycle
50 ns

tRAC = 60 ns

tRAC = 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

tRAC
Parameter

Symbol

E

Unit Notes

Access time from RAS

tRAC

-

70

-

80

ns

1

13

-

60

teAC

-

50

Access time from CAS

15

18

-

20

ns

1

Access time from column address

1M

-

25

-

30

35

-

40

ns

1

Access time from OE

tOEA

-

13

-

15

-

18

-

20

ns

Column address lead time
referenced to RAS

tRAL

25

-

30

-

35

-

40

-

ns

Read command setup time

tRCS

0

-

0

-

0

-

0

-

ns

Read command hold time
referenced to RAS

tRRH

0

-

0

-

0

-

0

-

ns

2

Read command hold lime
referenced 10 CAS

IRCH

0

-

0

-

0

-

0

-

ns

2

Oulpul buffer lurn-off delay
lime from OE

IOEl

0

10

0

13

0

15

0

15

ns

3

Oulpul buffer lurn-off delay
lime from CAS

IOfF

0

10

0

13

0

15

0

15

ns

3

Notes 1. For read cycles, access time is defined as follows:
Inpul conditions
IRAD ~ IRAD IMAX.) and IRCD ~ IRCD IMAX.)

Access lime

Access lime from RAS

IRAC IMAX.)

IRAC IMAX.)

IRAD > IRAD IMAX.) and IRCD ~ IRCD IMAX.)

1M IMAX.)

IRAD + tM IMAX.)

tACO> tRCO (MAX.)

ICAC IMAX.)

tRCO

+ teAc (MAX.)

tRAO (MAX.) and tRCO (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAO ~ tRAO (MAX.) and tRCO ~ tRCO (MAX.) will not cause
any operation problems.
2. Either tACH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

643

NEe

,uPD4264160, 4265160

Write Cycle
Parameter

tAAC. 50 ns
Symbol

tAAC

MIN.

MAX.

MIN.

=60 ns

tAAC

=70 ns

Unit Notes

MAX.

MIN.

MAX.

MIN.

MAX.

15

-

ns

1

ns

1

0

-

ns

0

-

ns

0

-

ns

3

ns

3

WE hold time referenced to CAS

twcH

8

-

10

-

10

WE pulse width

twP

8

-

10

-

10

WE lead time referenced to RAS

tRWL

13

-

15

WE lead time referenced to CAS

tcwL

13

15

-

15

-

WE setup time

twcs

0

-

15

-

OE hold time

toEH

0

-

0

Data-in setup time

tcs

0

-

0

Data-in hold time

tDH

10

-

10

0

tRAC.80 ns

-

0
0
0
15

-

15
15
15

15

ns
ns

2

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH (MIN.) should

be met.
2. If twcs -..l.-+..\-~I....l...lo.~~-----t---''-t'r...l....L....L-L...I'-L-

1012
ICI2

Ll/O

VOHHi-Z
VOL- .•••••••• : •••••••••••••••••••••••••••••• _•••••••••••••••••••• __ •

Remark U 1/0: Hi·Z

648

Data out

Hi-Z

ii

_---.,;N:.....;;;..:E=C=-_ _ _ _ _ _ _ _ _ _ _ _ _---e;.;.J1.;;...P.;;;..D4...;.;2;;.,;;6....;..4...;;...16;..,;;O~,....;..42;;;..;6;..,;;5....;..1...;;...60~_ ___1,l
I~
Early Write Cycle
tRe
tRAS

RAS
tesH

UCAS
LeAS

Address

U I/O

L 1/0

V,H- ----i,.....-+j-------.I~ 1+-------==-----1 r - - - - i r - - - - - d - - VIL-

~:~=

V,HVIL- ............................."-".............3

Remark OE: Don't care

1'-_ _ _ _ _ _ _ _ _-'1 ........................L-II.......................................................

NEe

yPD4264160,4265160

Upper Byte Early Write Cycle
IRC
IRAS

RAS

IRP

V,HV,LIcSH

UCAS

V,HV,L-

LCAS

V,HV,L-

V,HAddress V,L-

WE

U I/O

V,HVIL-~~~~~~~~~~~~-+__~~~~~~~~-L~~~~~~-L~~~~~

V,HV,L - .......................................'-"'-"-'"

Remark OE, L 1/0: Don't care

650

1\---------_

"-""-'''--''-''...x........-''--''-''''-'........................................''''--'.........................

I,

_~N;;;..E=..;:C~_ _ _ _ _ _ _ _ _ _ _ _ _~Jl;.....P_D_42;.....6;....;4;..;.1..;...60.;...<,,_4_2..;...65.;....1....;;6;..;.0----"11it

il

Lower Byte Early Write Cycle

I

lAC
tRAS
RAS

IRP

V,HV,L-

;1

11

~

IM"H
UCAS

V,HV'L-

I

I

'!
II

Ii
,I

V'HAddress V'L-

V'HV'L- .....l...l.~~~...l.~~~_+--+~,.....,.-'-.I....<'-'-'-..L..I....jr.....t....L...L..I....jr.....t....L..l-L-'r.....t....L..I-'-

LlIO

V'HV,L- L....IiI-X..L.x...:.......I-X.........J6..3

" -_ _ _.....II "-'''-'''-''-..............................................................._____......_

Remark DE, U 110: Don't care

651

NEe

yPD4264160,4265160

Late Write Cycle

lAc
lRAS

RAS

V'HV'LICSH
IRCO

UCAS
LCAS

lASH
!CAS

V'HV'L-

Address V'H-

V'L-

WE

OE

V'HV'L-

VIHV'L- '--1"--'-'-",,-1-1
teED

UltO
LitO

652

'W'\l\ ........j!:!:. •••••••

V,.VIl-~

Data in

i

_---=-N-==E::.:C=-_ _ _

~-------------lJl~P...;;D;;.....4;.;;;2;.;;;.64..;...1;;.,.;;6;..;;.O"-,4. ; .; 2=6;. ; .5. .;.,16. ; . .;O~_ _ _1

Ii

Upper Byte Late Write Cycle

I

IRe
lRAS

RAS

:1

IRP

'I
.~

V,HV,LleBH
IACD

IRSH

leAs

UCAS

V,HV,L-

,

I:

:1

I

'"
:'

LCAS

V,H-

Address V,L-

WE

OE

U 110

V,HV,L-

L -..........L..L-.L-L...<'-'-'

V,HV,L- '--''-'..L..L-.L-''--'"-L...I

VVIH-

W'V\ ....... ~~:.~ ...... .

Il-~

Data in

Remark L 110: Don't care

653

NEe

yPD4264160, 4265160

Lower Byte Late Write Cycle
lAc
tRP

tRAS

RAS

V'HV'l-

UCAS V'HV'L-

tCSH

lASH

tRCD

leAs

LCAS V'HV'L-

Address V'HV'L-

V'HV'L- ...............£...1.........................1

OE

V'H·V'L- ..........L.oJ-..........L.oJ-l-I
tDH

L 1/0

V'H-~ •••••••••••••••••••
Hi-Z
V'L-

Data in

~~~

Remark U 1/0: Don't care

654

________________-T

_ _N_E.;.....;;;...;;C~_ _ _ _ _ _ _ _ _ _ _ _ _. . .Jl_P_D_4_26_4_1_60-'!_4_2_65_1_6_0_--

1

Read Modify Write Cycle

tRWC
bop

tRAS
RAS

V,HV,L-

tAcD
UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

t_
teAs

V,HV,L-

V,H-

...,.....,...=:--1'

V,L- ......"-'..................,...........................,,..................

UIIO
LlIO

~:=

()()()()()()(}................... . ....... .
toLz

Ict..z
U 1/0

VOH-

Hi • Z

LI/O VOL-··········································

Hi·Z

655

NEe

yPD4264160,4265160

Upper Byte Read Modify Write Cycle

lAP

lRAS

V'HV..IOSH

IReD
UCAS

V'HV'L-

LCAS

V..V'L-

Address

V.. V'L-

V'HV'L-

IRSH

~'-'-'J.."'"r'-'~-'''''''

V'HV'L- ";L..l~~~";L..l~-l,,.... .:I...l'-+-+.,..--+~

UI/O

~::=

0000000..............................
10lZ

UI/O

VOH-

Hi·Z

Vrx....:.·········································

Hi-Z

Remark In this cycle, the input data to Lower 1/0 is ineffective. The data out of that remains Hi-Z.

656

NEe

yPD4264160,4265160

Lower Byte Read Modify Write Cycle

tRP

Address

V,HV,L-

WE

V,HVILtoeH

OE

V,HV,L-

Ll/O

~:=

{)()()()(X)(} ..............................
IoLZ
IoLZ

Ll/O

VOHHi·Z
VOL-•••••••••••••••••••••••••••••••••••••••••

Hi·Z

Remark In this cycle, the input data to Upper 1/0 is ineffective. The data out of that remains Hi·Z.

657

NEe

yPD4264160,4265160

Fast Page Mode· Read Cycle

lRASP

RAS

IRHCP

VIHVIL-

leaH
UCAS
LCAS

VIH-

Address

VIH-

WE

OE

U 1/0

LIIO

VIL-

VIL-

VIHVIL-

VIHVIL-

VCIH-

•••••••••••••• l;Il:~ ......... .

VOL-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

658

NEe

yPD4264160,4265160

Fast Page Mode Byte Read Cycle

AASP
RAS

UCAS

LCAS

Address

V,HV,L-

V,HV,L-

V,HV,L-

tRHCP

~

IAeD

teAS

V",V,L-

17
~

~

leAS

V,HV,L-

~~
Row

VQi-

~
Col.

~M

:)00 J

'/////1

COI.)OO

IRes

IACH

IRe~

lRAe
IAA
!cAe

------~i---~--------------------_<- •••••••••••••••••I:I!:~ ....................... .
VOL-

Hi·Z
..... __ ....
_............. .

667

NEe

yPD4264160,4265160

Hidden Refresh Cycle (Write)
lAC
lRAS

VOlVo.-

Address V'HV'l-

UI/O
LI/O

V'HVo.-

Remark OE: Don't care

668

NEe

yPD4264160, 4265160

'!t

--~~~~--------------------------~~~~~~~~----~:!'

,I

Package Drawing

II

:,

50PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

-t-t-------+------t-

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

INCHES

21.17 MAX.
1.0 MAX.
0.8 (T.P.)

0.834 MAX.
0.040 MAX.
0.031 (T.P.)

D

0.32~8:8~

0.013±0.003

E
F

O.HO.OS
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.OO8
0.400±0.004

0.8±0.2

0.031~8:88g

K

0.14S~8:m

0.006±0.001

L

O.S±O.1

0.020~8:88~

M
N

0.13
0.10
3 0 +70
-3'

0.005
0.004
30 +70
-3'
S50G5-8D-7JF3

A
B
C

G
H

P

';

I '~

I'
I
I.

669

NEe
[MEMO]

670

yPD4264160,4265160

Fast Page Mode
16M Dynamic RAM
[S.Ov

+ 10%]

671

DATA SHEET

N EC

MOS INTEGRATED CIRCUIT

:1

_ _ _-..:..Jl_PD_4_2s_16_4_oo~,4_21_64_00_=__,4_2S_1_74_00~,4_21_74_00_1

I

16 M-BIT DYNAMIC RAM
4 M-WORD BY 4-BIT, FAST PAGE MODE

Description
The JLPD42S16400, 4216400, 42S17400, 4217400 are 4,194,304 words by 4 bits CMOS dynamic RAMs. The
fast page mode capability realize high speed access and low power consumption.
These differ in refresh cycle and the JLPD42S16400, 42S17400 can execute CAS before RAS self refresh.
These are packaged in 26-pin plastic TSOP(n) and 26-pin plastic SOJ.

Features
• Single +5.0 V ± 10 % power supply

• 4,194,304 words by 4 bits organization
Fast page mode
•

Fast access and cycle time

Part number

Power consumption
Active (MAX.)

Access time
(MAX.)

RIW cycle time

Fast page mode

(MIN.)

cycle time (MIN.)

550mW

50 ns

90 ns

35 ns

60 ns

110 ns

40 ns

70 ns

130 ns

45 ns

80 ns

150 ns

50 ns

/lPD42S16400-50, 4216400-50
/lPD42S17400-50, 4217400-50

660 mW

/lPD42S16400-60, 4216400-60

495mW

/lPD42S17400-60, 4217400-60

605 mW

/lPD42S16400-70, 4216400-70

440mW

/lPD42S17400-70, 4217400-70

550mW

/lPD42S16400-80, 4216400-80

385mW

/lPD42S17400-80, 4217400-80

495mW

• The JLPD42S16400, 42S17400 can execute CAS before RAS self refresh.

Part number

Refresh cycle

/lPD42S16400

4,096 cycles/128 ms

/lPD42S17400

2,048 cycles/128 ms

/lPD4216400

4,096 cycles/64 ms

/lPD4217400

2,048 cycleS/32 ms

Refresh

Power consumption at standby
(MAX.)

CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh

1.4 mW
(CMOS level input)

CAS before RAS refresh,
RAS only refresh,
Hidden refresh

5.5mW
(CMOS level input)

The Information In this document Is subject to change without notice.
Document No. M11 079EJ6VODSU1

673

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Ordering Information
Part number
pPD42S 16400G3-50

Access time
(MAX.)

Package

50 ns

26-pin plastic TSOP (II)
(300 mil)

pPD42S 17400G3-50
pPD42S 16400G3-60

Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh

60 ns

Hidden refresh

pPD42S17400G3-60
pPD42S16400G3-70

70 ns

pPD42S17400G3-70
pPD42S 16400G3-80

80 ns

pPD42S17400G3-80
pPD42S 16400LA-50

50 ns

(300 mil)

pPD42S17400LA-50
pPD42S 16400LA-60

26-pln plastic SOJ

60 ns

pPD42S17400LA-60
pPD42S16400LA-70

70 ns

pPD42S17400LA-70
pPD42S16400LA-80

80 ns

pPD42317400LA-80
pPD4216400G3-50

50 ns

_.

pPD4216400G3-60

26-pin plastic TSOP (II)
(300 mil)

pPD4217400G3-50
60 ns

70 ns

pPD4217400G3-70
pPD4216400G3-80

80 ns

pPD4217400G3-80
pPD4216400LA-50

50 ns

pPD4216400LA-60

60 ns

pPD4217400LA-60
pPD4216400LA-70

70 ns

pPD4217400LA-70
pPD4216400LA-80
pPD4217400LA-80

674

26-pin plastic SOJ
(300 mil)

pPD4217400LA-50

80 ns

RAS only refresh
Hidden refresh

pPD4217 400G3-60
pPD4216400G3-70

CAS before RAS refresh

I,

NEe

yPD42S16400, 4216400, 42S17400, 4217400

I!'/
'I

Ii
l(

Pin Configurations (Marking Side)
2S-pin Plastic SOJ (300 mil)

26-pin Plastic TSOP (H) (300 mil)

Vee
1/01
1/02
WE

RAS
A111NC Note
A10
AO
A1
A2
A3
Vee

2
3
4
5
6

1::1::1::1::
11111111

gggg

~!!ZI!!Z

8
9
10
11
12
13

~i~1
~

~

26
25
24

GND

Vee

1/04

1/01

1/03

1/02

23
22
21

CAS

WE

19
28
17
16
15
14

Note A11 ... JLPD42S16400,4216400

NC .... JLPD42S17400, 4217400
AO to A11 : Address Inputs
I/O 1 to 1/04: Data Inputs/Outputs
RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

A9

RAS
A11/NCNote

A8
A7

A10
AO

OE

A6
A5
A4
GND

A1
A2
A3
Vee

0
2
3
4
5
6
8
9
10
11
12
13

1::1::1::1::
11111111

ecce

~~tt;
"en--",
....., .... e» .....

g~g~

r-8r-8
l>1j;l>1j;

26
25
24
23
22
21
19
28
17
16
15
14

GND
1/04
1/03

CAS
OE

A9
A8
A7
A6
A5
A4

GND

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Block Diagram

RAS o-----I~
CAS 0 - -.....

Clock
Generator

WE

Vee 0 - GNDo--

CAS before
RASCounter
Memory
Cell
Array
Bit organization Note2

Row
Address
Buffer
AddressNol81
Column
Address
Buffer

Notes 1.

2.

676

Column address

Part number

Row address

pPD42S16400,4216400

AO - A11

AO -A9

pPD42S17400,4217400

AO - Al0

AO - Al0

pPD42S16400, 4216400 ... 4,096 x 1,024 x 4

pPD42S17400, 4217400 .... 2,048 x 2,048 x 4

1/01
to
1/04

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Input/Output Pin Functions
The ,uPD42S16400, 4216400, 42S17400, 4217400 have input pins RAS, CAS, WE, OE, Address Note and
input/output pins 1101 to 1/04.

Pin name
RAS
(Row address strobe)

Function

Input/Output
Input

RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.

Input

CAS activates data input/output circuit by latching column address and

• CAS before RAS refresh
CAS
(Column address strobe)
AO to Ax Note

selecting a digit line connected with the sense amplifier.
Input

Address bus.
Input total 22-bit of address signal, upper bits and lower bits N01e in sequence

(Address inputs)

(address multiplex method).
Therefore, one word is selected from 4, 194,304-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.

(Output enable)

If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/04
(Data inputs/outputs)

Input/Output

4-bit data bus.
1/01 to 1/04 are used to input/output data.

Note
Address inputs

Upper bits

Lower bits

,uPD42S16400, 4216400

AO - A11

12

10

,uPD42S17400, 4217400

AO - Al0

11

11

Part number

677

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Electrical Specifications
•

All voltages are referenced to GND.
After power up (Vcc O!: Vcc

(MIN.)),

wait more than 100 J.LS (RAS, CAS inactive) and then, execute eight CAS

before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Symbol

Condition

Rating

Unit

Voltage on any pin relative to GND

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

PD

1

W

Operating ambient temperature

TA

oto +70

·C

Storage temperature

TaIg

-55 to +125

·C

Caution

Exposing the device to stress above those listed In Absolute Maximum Ratings could ceuse
permanent damage. The device Is not meant to be operated under conditions outside the limits
described In the operational section ofthls specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Parameter

Vee

4.5

5.0

5.5

V

High level input voltage

V,H

2.4

Vee + 1.0

V

Low level input voltage

VOL

-1.0

+0.8

V

Operating ambient temperature

TA

0

70

·C

Capacitance (TA

Condition

= 25 ·c, f = 1 MHz)

Parameter
Input capacitance

Data input/output capacitance

678

Symbol

Symbol

MAX.

Unit

C"

Address

Test condition

MIN.

TYP.

5

pF

C..

RAS,CAS. WE. OE

7

ClIO

I/O

.,

pF

NEe

,uPD42816400, 4216400, 42817400, 4217400

--.....;..-=-=-----------..t:.:.,;:......:::....:..:=~;...:,..:....:..!......,;..=...;~..:..:..~.....:...::..::....:....::......:...::....::..l~.=-:;,.,;;.-..:..:..~

J

_ _ _ ___1:j)

:1

DC Characteristics (Recommended operating conditions unless otherwise noted)

,%

.~
Ij

[,uPD42S16400, 4216400]
Parameter
Operating current

Symbol
lee1

Test condition

MAX.

Unit

Notes

tAAe = 50 ns

100

mA

1,2,3

tAC = tAC (MIN.)

tAAe = 60 ns

90

10 = 0 mA

Standby

/lPD42S16400

Icc2

current

Operating current

lee3

leo.

(Fast page mode)

CAS before RAS

Icc,

refresh current

CAS before RAS
self refresh current

80

tAAC = 80 ns

70

RAS, CAS

~

V,H (MIN.), 10 = 0 mA

2.0

RAS, CAS

~

Vee - 0.2 V, 10 = 0 mA

0.25

1.0

RAS cycling, CAS 

tRAD (MAX.)

and

tRCO ~ tACO (MAX.)

tAA (MAX.)

tRAQ

+

tCAC {t•.,AX.}

tACD

+ tCAC (MAX.)

tRCO> tRCO (MAX.)

tRAC (MAX.)
tAA (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, 1M or tCAC) is to be used for finding out when output
~

data will be available. Therefore, the input conditions tRAD

tRAD (MAX.) and tRCD

~

tRCD (MAX.) will not cause

any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the jlPD42S16400, 42S17400.

Read Cycle
tRAG

= 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

50

-

60

70

ns

1

20

ns

1

30

40

ns

1

13

15

18

-

80

-

-

20

ns

-

40

-

ns

tRAG
Parameter

= 50 ns

tRAG

= 60 ns

tRAG

= 70 ns

Symbol

Unit Notes

Access time from OE

tOEA

-

Column address lead time

tRAl

25

-

30

-

35

Read command setup time

tRCS

0

-

0

-

0

0

0

-

0

-

0

-

ns

tRRH

-

0

Read command hold time

ns

2

tRCH

0

-

0

-

0

-

0

-

ns

2

tOEZ

0

10

0

15

0

15

0

20

ns

3

tOFF

0

10

0

15

0

15

0

20

ns

3

Access time from RAS

tRAG

Access time from CAS

tGAG

Access time from column address

tAA

13
25

15

18
35

referenced to RAS

referenced to RAS
Read command hold time
referenced to CAS
Output buffer turn-off delay
time from OE
Output buffer turn-off delay
time from CAS

Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAQ (MAX.)

and

tRCO

tRAQ> tRAQ (MAX.)

and

tRCO 5 tRCo (MAX.)

tRAD

5

tRCO> tRCO (MAX.)

5

tRCo (MAX.)

Access time

Access time from RAS

tRAC (MAX.)

tRAC (MAX.)

tAA (MAX.)

tRAQ

+ tAA (MAX.)

tCAC (MAX.)

tACO

+ tCAC (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD

~

IRCD (MAX.) will not cause

any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. 10FF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is nol referenced
10 VOH

or

VOL.

683

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Write Cycle
Parameter

Symbol

tRAe

= 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

10

-

10

-

15

-

ns

1

10

-

15

ns

1

20

15

-

ns

0

-

20

-

0

-

ns

0

-

0

-

ns

0

-

0

-

ns

3

ns

3

tRAe

WE hold time referenced to CAS

tWCH

8

WE pulse width

tw.

8

WE lead time referenced to RAS

tAWL

18

WE lead lime referenced to CAS

tCWL

13

WE setup time

twcs

0

OE hold time

tOEH

0

Data-in setup time

tos

0

Data-in hold time

tDH

10

=50 ns

tRAe

10
20
15
0
0
0
10

=60 ns

tRAe

=70 ns

15

15

15

Unit Notes

ns

2

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH (MIN.) should
be met.
2. If twcs 2: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
Parameter

Symbol

=70 ns

tRAe. 50 ns

tRAe = 60 ns

tRAe

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

160

180

-

205

95

-

110

-

40

-

43

50

55

-

60

-

-

Read modify write cycle time

tAWe

133

RAS to WE delay time

tAWO

70

CAS to WE delay time

tCWD

33

Column address to WE delay time

tAWD

45

85

tRAe = 80 ns

70

Unit Note
ns
ns

1

ns

1

ns

1

Note 1. If twcs 2: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD 2: tRWD (MIN.), tCWD 2: tCWD (MIN.), IAWD 2: IAWD (MIN.) and tCPWD 2: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

684

NEe

PD42S16400, 4216400, 42S17400, 4217400

Fast Page Mode
tRAC = 50 ns
Parameter
Fast page mode cycle time

Symbol
tpc

tRAC = 60 ns

tRAC = 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

35

-

40

-

45

-

50

-

Unit
ns

Access time from CAS precharge

tACP

-

30

-

35

-

40

-

45

ns

RAS pulse width

tRASP

50

125,000

60

125,000

70

125,000

80

125,000

ns

10

-

10

-

10

-

ns

35

-

40

-

45

83

-

95

ns

58

-

90

-

70

-

ns

tcp

8

RAS hold time from CAS precharge

tRHCP

30

Read modify write cycle time

tpAWe

73

-

CAS precharge to WE delay time

tCPWD

50

-

CAS precharge time

65

Note

ns

1

Note 1. If twcs 2: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.

If tRWD 2: tRWD (MIN.), tCWD 2: tCWD (MIN.), tAWD 2: tAWD (MIN.) and tCPWD 2: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
Refresh Cycle
tRAC
Parameter

Symbol
MIN.

=50 ns
MAX.

tRAC = 70 ns

tRAC = 80 ns

MIN.

tRAC = 60 ns
MAX.

MIN.

MIN.

MAX.

5

-

5

-

ns

10

-

10

ns

JlS

1

Unit

CAS setup time

tCSR

5

-

5

CAS hold time (CAS before RAS refresh)

tCHR

10

-

10

RAS precharge CAS hold time

MAX.

Note

tRPC

5

-

5

-

5

-

5

RAS pulse width
(CAS before RAS self refresh)

tRASS

100

-

100

-

100

-

100

-

RAS precharge time
(CAS before RAS self refresh)

tRPS

90

-

110

-

130

-

150

-

ns

1

CAS hold time
(CAS before RAS self refresh)

IeHS

-50

-

-50

-

-50

-

-50

-

ns

1

WE setup time

twSR

10

-

10

-

10

10

-

ns

15

-

15

-

-

15

-

ns

WE hold time

tWHR

15

ns

Note 1. This specification is applied only to the ~PD42816400, 42817400.

685

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Read Cycle
lAC
lRAS

Address

laz

1/0 Vo....
VOl-

686

Hi-Z

IRP

NEe

PD42S16400, 4216400, 42S17400, 4217400

Early Write Cycle
lAC
lRAS

RAS

VII''''''~''''''+--+-_____--'t.......I.-C~'''''''I.-C~J...''''''-'-J...''''''-'-

110

Viii-

V'L- L.JI~..K..l~~~'-K.3

11._ _ _ _ _ _ _ _...11

"'..l(..~~..x..;~'_l<........,........................,........- '

Remark OE: Don't care

687

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Late Write Cycle
lAC

I"AS

lOEH

688

NEe

PD42S16400, 4216400, 42S17400, 4217400

Read Modify Write Cycle

tRwe
tRAS

tCSH

tACO

tRSH

,

twp

tOEH

tos

tOH

Data in

H~Z
---------------------------------,

689

~

NEe

yPD42516400,4216400,42517400,4217400

Fast Page Mode Read Cycle

tAASP

IRP

V,HVIL-

tRHCP

lesH

Ipe

tRSH

teRP

VIHVIL-

-,-++----11,

V,HVIL-

V,H- -r~'-+-r-H---!-----hf-I--Ir+------+.r...L....t"-+----+--h!-"T-.r"T'~
V,L-

OE

1/0

L-L-........t...f'-l

V,H- 't'""""f~~~~~"T"""'\.
V,L-

VOH- __________ !il-~_________ _
VOL-

Dala oul

Hi-Z

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

690

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Fast Page Mode Early Write Cycle
tRASP

tRP

V,HV,L-

Address

WE

VII.V,L-

110

V,HVIL- L.lC-lli...ll:....K....x..)f J'.._ _ _ _....JI

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

691

NEe

yPD42516400,4216400,42517400,4217400

Fast Page Mode Late Write Cycle
tAASP

RAS

V,HVIl-

WE

V,HVIl-

OE

V,HVIl-

110

V,HVIl-

tRP
tRHCP

Hi-Z
,----------------

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles

692

within the same RAS cycle.

i,

~

______E_c:=_____________

~H~P=D~42~S~1~6_40~O~,~4=21~6~4~O~O,~4=2=S~17~4~O~O~,4~2~1~7~40~O~____~i.

II

:1

Fast Page Mode Read Modify Write Cycle

II

II

j

V,H-

V,l-

Address

V,H-

V,l-

WE

VIHV,l-

OE

VIHV,l-

1/0 VOHVOl-

1/0

V,HV,l-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

693

NEe

yPD42S16400,4216400,42S17400,4217400

CAS Before RAS Self Refresh Cycle (Only for the

~ ~
Remark Address,

~D42S16400,

42S17400)

:\\\\\\\\\\\\\\\\\\\\\\\
<:5E : Don't care

1/0 : Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before HAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh as follows just before and after setting CAS before RAS self refresh.
,uPD42S16400: 4,096 times within a 64 ms interval
,uPD42S17400: 2,048 times within a 32 ms interval
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh as follows just before and after setting CAS before RAS self refresh.
,uPD42S16400: 4,096 times within a 64 ms interval
,uPD42S17400: 2,048 times within a 32 ms interval
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 .us), CAS before
RAS refresh cycles will be executed one time.
If 10

.us < tRAS < 100 .us, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.

And refresh cycles as follows should be met.
,uPD42S16400: 4,096 times within a 128 ms interval
,uPD42S17400: 2,048 times within a 128 ms interval
For details, please refer to How to use DRAM User's Manual.

694

NEe

PD42S16400, 4216400, 42S17400, 4217400

CAS Before RAS Refresh Cycle

V,~

WE

-,~~~--~~---t--------------~r-~~--~~.,~

______

~.,~

______

~

V'L-

Remark Address, OE: Don't care 1/0: Hi-Z

RAS Only Refresh Cycle

tAAS

RAS

tRP

tRAS

V,~
V'L-

teRP

Address

V'HV'L-

Remark WE, OE: Don't care 1/0: Hi-Z

695

NEe

yPD42S16400,4216400,42S17400,4217400

Hidden Refresh Cycle (Read)

Address

IRe

IRe

tRAS

tRAS

~,:=

WE

lel2

I/O

VOHVOL-

696

Hi-Z

---------------------------------------

Dala oul

Hi-Z

NEe

pPD42S16400, 4216400, 42S17400, 4217400

Hidden Refresh Cycle (Write)
IRC

IRA.

IRC
tRAS

V'HRAS

V'L-

CAS

V'H-

Address

V'L-

V'HVIL-

V'HV'L- -l~....1.....~~--lo...J....4'--_-+_+-....L...L.J

1/0

V'H-

V'L- L..Jj~..l&...K...l'-lll:....lLlLJ~

"--_ _ _....JI "-l1L..ll:....K....lt...lL.lIL..ll:....K....lt....lL...lIL..ll:....K....lt....l<..-'IL..lI:....K.-"-.l<..-'''-'''-''

Remark OE: Don't care

Ii
"

Ii

697

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)
tRe
tRAS

RAS

V,HVIL-

tesR

teHR

Remark Address, OE: Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
x 16-bit organization during test mode. Don't care about the input levels of the CAS input AO, A 1.
(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output

= "1 ": Normal write (all memory cells)

Output = "0": Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, GAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

698

NEe

yPD42S16400, 4216400, 42S17400, 4217400

Package Drawings

26PIN PLASTIC TSOP(II) (300 mil)

detail of lead end

1-~----------~-------------r

A

13

.1
H

DO
01$1

B

M

L

@I

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A
B

17.36 MAX.
1.06 MAX.
1.27 (T.P.)

0.684 MAX.
0.042 MAX.
0.050 (T.P.)

o

0.42~8:8~

0.017±0.003

E
F

0.HO.05
1.2 MAX.
0.97
9.22±0.2
7.62±0.1

0.004±0.002
0.048 MAX.
0.038
0.363±0.008 •
0.300±0.004

c

G
H

0.8±0.2

0.031~8:88§

K

0.145~8:m

0.006±0.001

L

0.5±0.1

0.020~8:88~

M
N

0.21
0.10
3 0+70
-3°

0.009
0.004
3 0+70
-3°
S26G3-5D-7JD1

P

699

NEe

yPD42S16400, 4216400, 42S17400, 4217400

26 PIN PLASTIC SOJ (300 mil)
B

()

Cl

....,

J:

-

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

17.3~8jg

0.6S1~8:8~g

c

7.62

0.300

D

S.47±0.2

0.333~8:88§

E

1.03±0.15

0.041 ~8:88~

F

0.029
0.13S±0.00S
0.100±0.00S
0.031 MIN.
0.102
0.050 (T.P.)

K

0.74
3.5±0.2
2.545±0.2
O.S MIN.
2.6
1.27 (T.P.)

M

0.40±0.10

0.016~8:88~

N
P
T

0.12
6.73±0.2
0.10
RO.S5

0.005
0.265±0.00S
0.004
RO.033

u

0.20~8:~g

0.00s~8:88~

G

H

Q

S26LA·300A·1

700

NEe

yPD42S16400,4216400, 42S17400, 4217400

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
~PD42S16400,4216400,42S17400,4217400.

For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(lEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
~PD42S16400G3,

4216400G3, 42S17400G3, 4217400G3: 26-pin plastic TSOP (ll) (300 mil)

Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235 'c or lower,
Reflow time: 30 seconds or less (210 'C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNota

Symbol
IR35-107-2

(10 hours pre-baking is required at 125 'c afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
VPS

Peak temperature of package: 215 'C,or lower,
Reflow time: 40 seconds or less (200 'c or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNota

VP15-107-2

(10 hours pre-baking is required at 125 'c afterwards)
cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

Terminal temperature: 300 'c or lower,
Time: 3 seconds or lower (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

701

NEe

yPD42S16400, 4216400, 42S17400, 4217400

,uPD42S16400LA, 4216400LA, 42S17400LA, 4217400LA: 26-pln plastic SOJ (300 mil)
Soldering process
Infrared ray rellow

Soldering conditions
Peak temperature of package surface: 235·C or lower,
Rellow time: 30 seconds or less (210 ·C or higher),
Number of rellow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
cautions
1. After the flrat reflow process, cool the package down to room
tempersture, then start the second reflow process.
2. After the flrat reflow proceaa, do not use water to remove
residual flux (water csn be used In the second proceaa).
VPS

Peak temperature of package: 215·C or lower,
Rellow time: 40 seconds or less (200 ·C or higher),
Number of rellow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ·C afterwards)
cautions
1. After the flret reflow process, cool the package down to room
tempereture, then start the second reflow process.
2. After the flrat reflow process, do not use wster to remove
residual flux (water can be used In the second process).

Partial heating method

Terminal temperature: 300·C or lower,
Time: 3 seconds or less (Per side of the package).

Note

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25·C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

702

VP15-207-2

k

II

DATA SHEET

NEe/..--------M-O-S-IN-T-E-G-RA-r-E-o-c-IR-C-U-IT--:!

_ _ _ _ _ _ _ _--=--JlP_D_42_S_17_80_0~,42_1_78_00_1
~

16 M-BIT DYNAMIC RAM
2 M-WORD BY 8-BIT, FAST PAGE MODE

:1

Description
The pPD42S17800, 4217800 are 2,097,152 words by 8 bits CMOS dynamic RAMs. The fast page mode capability
realize high speed access and low power consumption.
These differ in refresh cycle and the PPD42S17800 can execute CAS before RAS self refresh.
These are packaged in 28-pin plastic TSOP (TI) and 28-pin plastic SOJ.

Features
• 2,097,152 words by 8 bits organization

•

Single +5.0 V ± 10 % power supply

• Fast page mode
• Fast access and cycle time

Part number

Power consumption

Access time

RMI cycle time

Fast page mode

Active (MAX.)

(MAX.)

(MIN.)

cycle time (MIN.)

~D42S1780~O,421780~0

605mW

60 ns

110 ns

40 ns

,uPD42S17800-70, 4217800-70

550mW

70 ns

130 ns

45 ns

• The pPD42S17800 can execute CAS before RAS self refresh

Part number

Refresh cycle

Refresh

Power consumption at standby
(MAX.)

,uPD42S17800

2,048 cycleS/128 ms

CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh

1.4mW
(CMOS level input)

,uPD4217800

2,048 cycles/32 ms

CAS before RAS refresh,
RAS only refresh,
Hidden refresh

5.5mW
(CMOS level input)

The Information In this document Is subject to change without notice.
Document No. M11081 EJ5VODSU1

703

NEe

~PD42S17800,4217800

Ordering Information
Access time

(MJlX.)

Package

,uPD42S17BOOG5-60
,uPD42S17BOOG5-70

60 ns
70 ns

2B-pin plastic TSOP (II)
(400 mil)

,uPD42S17BOOLE-60
,uPD42S17BOOLE-70

60 ns
70 ns

2B-pin plastic SOJ
(400 mil)

,uPD4217BOOG5-60
,uPD4217BOOG5-70

60 ns
70 ns

2B-pin plastic TSOP (II)
(400 mil)

,uPD4217800LE-60
,uPD4217BOOLE-70

60 ns
70 ns

2B-pin plastic SOJ
(400 mil)

Part number

704

Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

NEe

#PD42S17800,4217800

Pin Configurations (Marking Side)

Vee

1/01

2

1/02
1/04

3
4
5

WE

6

RAS
NC
A10

7
8
9

1/03

AO
A1
A2
A3
Vee

AO to A10

1::1::

""
tt
"'1/1

cc

.....

II
en

10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

16
15

GND

Vee

1/08

1/01

1/07

1/02

1/06

1/03

1/05

1/04

CAS

WE

OE

A9
A8
A7
A6
A5
A4
GND

I

28-pin Plastic SOJ (400 mil)

2S-pin Plastic TSOP (0) (400 mil)

RAS
NC
A10
AO
A1
A2

A3
Vee

10
2
3
4
5
1::1::
6
i
i
7
....
"'1/1
8
8~
9
ro
mr
m
10
11
12
13
14

""

.....

28
27
26
25
24
23
22
21
20

A9
A8

19
18
17
.16
15

A7
A6
A5
A4
GND

Iii

GND
1/08
1/07
1/06
1/05

CAS

:1

OE

':

:'
I'

: Address inputs

1/01 to 1/08: Data Inputs/Outputs
RAS

Row address strobe

CAS

Column address strobe

WE

Write enable
Output enable

OE
Vcc

Power Supply

GND

Ground

NC

No connection

705

NEe

.uPD 42817800, 4217800

Block Diagram

Clock
Generator

Vee 0-------GND 0--------

CAS before
RASCounler
Memory
Cell
Array

1/01
10

1/08

Row
Address
Buffer
Address-'
Column
Address
Buffer

Notes 1.

2.

706

Pari number

Row address

pPD42Sl7800.42l7800

AO - Al0

IlPD42S17800. 4217800 ... 2.048xl.024x8

,j

NEe
#PD42S17800, 4217800
~
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ' - - - - - - - - . . . . ; . . . . . . ; . . ' - - - - - - - - - - ----I:.;
;~

I·;:l
I

Input/Output Pin Functions
The JlPD42S17800, 4217800 have input pins RAS, CAS, WE, OE, Address Note and
input/output pins 1/01 to 1/08.

Pin name
RAS
(Row address strobe)

Input/Output
Input

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS
(Column address strobe)

Input

CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.

AO to Ax Note
(Address inputs)

Input

Address bus.
Input total 21-bit of address signal, upper bits and lower bits Note in sequence
(address multiplex method).
Therefore, one word is selected from 2,097,152-word by 8-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activati n9 RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.

WE
(Write enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE
(Output enable)

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/08
(Data inputs/outputs)

Input/Output

8-bit data bus.
1/01 to 1/08 are used to input/output data.

Note
Part number
~PD42S17800,4217800

Address inputs

Upper bits

Lower bits

AD - A10

11 bits

10 bits

707

~

NEe

.uPD42S17800, 4217800

Electrical Specifications
• All voltages are referenced to GND.
• After power up (Vee

~

Vee (MIN.». wait more than 100 Jls (RAS. CAS inactive) and then. execute eight CAS

before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter

Symbol

Rating

Unit

Voltage on any pin relative to GND

VT

Condition

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Po

1

W

Operating ambient temperature

T.

o to +70

·C

Storage temperature

Tstg

-55 to +125

·C

Caution

Exposing the device to stress above those listed In Absolute Maximum Ratings could cause
permanent damage. The device Is not meant to be operated under conditions outside the limits
described In the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
Parameter

Condition

MIN.

TYP.

MAX.

Unit

4.5

5.0

5.5

V

2.4

Vee + 1.0

V

-1.0

+0.8

V

70

·C

MAX.

Unit
pF

Vee

High level input voltage

VIH

Low level input voltage

VIL

Operating ambient temperature

T.

0

Capacitance (TA

= 25 'c, f = 1 MHz)

Parameter
Input capacitance

Data inpuVoutput capacitance

708

Symbol

Supply voltage

Symbol

Test condition

MIN.

TYP.

CI1

Address

5

C~

RAS. CAS. WE. OE

7

ClIO

1/0

7

pF

if

NEe
tl PD42S17800,4217800
]1
--.:...:;;.=.;=--------------------!----.,;;....-~~--..;;...;;..----,~

i

,j
i~

[MEMO]

i~

i;l

'1

709

NEe

~PD42S17800!4217800

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter
Operating current

Symbol
Icc1

Test condition
tRC - tRC (MIN.)
lo~

Standby

IIPD42S17800

IC02

current
IIPD4217800

RAS only refresh current

Iccs

0 mA

ICo.

(Fast page mode)

CAS before RAS

ICOO

tRAC = 70 ns

100

2.0

RAS, CAS", V,H (MIN.), 10 = 0 mA

2.0

RAS, CAS", Vcc - 0.2 V, 10 = 0 mA

1.0

RAS cycling, CAS", V,H (MIN.)

CAS before RAS
self refresh current

mA

1,2

400

!IA

1,2

500

!iA

1,2

250

!IA

2

tRAC = 60 ns

70

tRAC = 70 ns

60

=60 ns

110

tRAC = 70 ns

100

RAS cycling

tRAS s 1 liS

mA

1,2,5

100

Standby:
RAS, CAS", Vcc - 0.2 V
Address: V,H or V,l
WE, OE: V,H
10- 0 mA

1,2,3

mA

tRAC = 70 ns

CAS before RAS refresh:
tRAS S 300 ns
tRC - 62.5 !IS
RAS, CAS:
VCC - 0.2 V S V,H S V,H (MAX.)
o V S V,l S 0.2 V

Notes

mA

1,2,3,4

110

tRAC

Unit

mA
tRAC - 60 ns

RAS S V,l (MAX.), CAS cycling

tRC = tRC (MIN.)

Icee

110

0.25

10- 0 mA

CAS before RAS
long refresh current
(2,048 cycles 1128 ms,
only for the IIPD42S17800)

!RAC = 60 ns

RAS, CAS", Vcc - 0.2 V, 10 - 0 mA

tpc - tpc (MIN.), 10 - 0 mA

refresh current

MAX.

RAS, CAS", V,H (MIN.), 10 = 0 mA

tRC = tRC (MIN.), 10 - 0 mA

Operating current

MIN.

RAS, CAS cycling

IccT

RAS, CAS:
tRASS = 5 ms
Vcc - 0.2 V S V,H S V'H(MAX.)
o V S V,l S 0.2 V

Input leakage current

II (l)

V,. Oto 5.5 V
All other pins not under test = 0 V

-10

+10

!iA

Output leakage current

10(l)

Vo = 0 to 5.5 V
Output is disabled (Hi-Z)

-10

+10

!IA

High level output voltage

VOH

10 =-5.0 mA

2.4

Low level output voltage

VOL

(only for the IIPD42S17800)

10= 0 mA

10= +4.2 mA

Notes 1. Iccl, Icc3, IcC4, Ices and Icc6 depend on cycle rates (tAC and tpc).
2. Specified values are obtained with outputs unloaded.

710

V
0.4

V

1,\

NEe

II

~PD42S17800,4217800

I
1

I

3. ICCl and Icc3 are measured assuming that address can be changed once or less during RAS :s;
and

VIL (MAX.)

CAS ~ VIH (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.

II.!

S. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

Ii,.

711

NEe

yPD42S17800,4217800

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

(2) Output timing specification

VIH (MIN.) = 2.4 V ---------------~
VIL(MAX.) =o.av·--------:::::fi
•
I

VOH(MIN.) =2.4V------=J

iL

•
I

--i--l:-'IT=5ns

I
I

I
I

1':

I

VOL (MAX.) = 0.4 V------==\-'_ ___--'

IT=5ns

(3) Output load condition
Vee

I/O--~--....

Common to Read, Write, Read Modify Write Cycle
tRAC = 60 ns
Parameter

Unit Notes
MIN.

MAX.

MIN.

MAX.

130

-

ns

50

ns

10

-

tRC

110

RAS precharge time

tRP

40

CAS precharge time

tCPN

10

-

ns

RAS pulse width

tRAS

60

10,000

70

10,000

ns

CAS pulse width

tCAS

15

10,000

18

10,000

ns

RAS hold time

tRSH

15

-

18

tCSH

60

-

70

-

ns

CAS hold time

tRCD

20

45

20

52

ns

2

tRAD

15

30

15

35

ns

2

tCRP

5

-

5

ns

3

Row address setup time

IASR

0

-

0

-

Row address hold time

tRAH

10

-

10

-

ns

0

ns

ns

RAS to

CAS delay time

RAS to column address delay time
CAS to

FiAS precharge time

ns

tASC

0

Column address hold time

tCAH

15

-

15

OE lead time referenced to RAS

toES

0

-

0

-

CAS to data setup time

tCl2

0

-

ns

tOl2

0

0

-

ns

OE to data delay time

tOED

13

-

0

DE to data setup time

15

-

ns

tT

3

50

3

50

ns

tREF

-

128

-

128

ms

-

32

-

32

ms

Refresh time

PPD42S17800

/lPD4217800

1

ns

Column address setup time

Transition time (rise and fall)

712

tRAC = 70 ns

Symbol

Read I Write cycle time

}-

ns

_ _N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _---'J.1"-P_D_4_2..;;..S_17-.;8~0...;...0,~4=2;..,;,.1~78;;;,...;0~0_ _ _11
,I-(

!~

Notes 1. In CAS before RAS refresh cycles, tRAS (MAX_) is 100 J1S.

II

If 10 J1S < tRAS < 100 J1S, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions
tRAD:::;: tRAQ (MAX.)

and

tACO ~ tRCo (MAX.)

tRAQ> tRAD (MAX.)

and

tRCo

:5

Access time

tACO (MAX.)

tRCO> tACO (MAX.)

It
i

Access time from RAS

tRAC (MAX.)

tRAG (MAX.)

tAA (MAX.)

tRAO

+ tAA (MAX.)

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

i

tRAD (MAX.) and tRCD(MAX.) are specified as reference pOints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tcAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCO (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

Read Cycle
tRAG

= 60 ns

tRAG

= 70 ns

Symbol

Parameter

60

70

ns

1

18

ns

1

35

ns

1

18

ns

30

-

15

tRAL

30

-

35

-

ns

tRCS

0

-

0

-

ns

tRRH

0

-

0

-

ns

2

tRCH

0

-

0

-

ns

2

tOEZ

0

13

0

15

ns

3

tOFF

0

13

0

15

ns

3

Read command hold time
referenced to RAS

-

-

Column address lead time

Read command setup time

MAX.

tAA

tCAC

referenced to RAS

MIN.

tOEA

tRAC

Access time from column address

MAX.

-

Access time from RAS
Access time from CAS

Access time from OE

Unit Notes
MIN.

15

I

Read command hold time
referenced to CAS
Output buffer turn-off delay
time from OE
Output buffer turn-off delay
time from CAS

I~

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAQ:5 tRAQ (MAX.)

and

tRCo

:5

tACO (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAQ> tRAQ (MAX.)

and

tACO

:5

tRCO (MAX.)

tAA (MAX.)

tRAD

+

tCAC (MAX.)

tACO

+ tCAC (MAX.)

tRCO> tACO (MAX.)

tAA (MAX.)

tRAO(MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
i,','

j

They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAO ~ tRAO (MAX.) and tRCO

~

j

tRCO (MAX.) will not cause

any operation problems.

1

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.

j
II

3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

713

~

NEe

#PD42S17800,4217800

Write Cycle
Parameter

Symbol

tRAC - 60 ns

tRAC _ 70 ns
Unit Notes

MIN.

MAX.

MIN.

MAX.

10

-

ns

1

ns

1

-

ns

-

ns

WE hold time referenced to CAS

!weH

10

WE pulse width

twp

10

WE lead time referenced to RAS

tAWL

20

WE lead time referenced to CAS

tCWL

15

-

WE setup time

!wes

0

V,L-

lCAe

~---------

IDEA

IDS

IOH

Dalain
IOLZ

1/0

VOHVOL-

Hi-Z

Hi-Z
--------------------------------_.
I
"

11

I

I;
i~

719

NEe

yPD42S17800,4217800

Fast Page Mode Read Cycle
lAP

IAASP

V,HV,L-

IAHeP

ICSH

V,HV,L-

Ipc

lASH

--+-++----n

V,HV,L-

V,H-

--r'"-r-r-+-:...-Ir-+--!----"""'*..1.....!.+---+t-l-+-I----+--4.jI-.-..................

V,L- ............-""+.1

V,H- 'l""""~t""""!...,.""T"'T""'r-T"'M
V,L-

I/O

VOH-

Hi-Z

VOl- -----------------------

Dala out

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles wi.thin the same Fi'AS cycle.

720

NEe

I

~PD42S17800,4217800

Fast Page Mode Early Write Cycle

V,HVIL-

Address

WE

1/0

V,HVIL-

'1

:;~

V,HV,L-

V,HV,L- L..lL.li~~....K..3

I\._ _ _ _....JI

Remarks 1. OE: Don't care

2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

721

NEe

~PD42S17800,4217800

Fast Page Mode Late Write Cycle
lRASP

IRP
tRHCP

V,HV,L-

V,HV,L-

Address

WE

V,HV,L-

OE

V,HV,L-

I/O

V,HV,L-

Hi-Z
,----------------

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

722

ii

Ii

____
N_E
__
C__________________________~#_P_D_4_2S~1~7~80~O~,~4=21~7~8~OO~____~~,
ii
Fast Page Mode Read Modify Write Cycle

II
I

Address

VII"V,L-

1/0 VooVOL-

1/0

V,H-

V,L-

Remark In the fast page mode, read, write and read modify'write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

~

NEe

pPD42S17800,4217800

CAS Before RAS Self Refresh Cycle (Only for the /LPD42S17800)

V,I+RAS

V,L-

V,I+V,L-

~ ~
Remark Address,

:\\\\\\\\\\\\\\\\\\\\\\\
DE : Don't care

1/0 : Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used indepe.ndently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.

(1) Normal Combined Use orCAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh as follows just before and after setting CAS before RAS self refresh.

/LPD42S17800: 2,048 times within a 32 ms interval

(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh as follows just before and after setting CAS before RAS self refresh.

/LPD42S17800: 2,048 times within a 32 ms interval

(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 JLS), CAS before
RAS refresh cycles will be executed one time.
If 10 JLS < tRAS < 100 JLS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles as follows should be met.

/LPD42S17800: 2,048 times within a 128 ms interval
For details, please refer to How to use DRAM User's Manual.

724

NEe

I

,uPD 42817800, 4217800

CAS Before RAS Refresh Cycle

I

tRAS

V,HV,L-

!',

:1'
,
V,HV,L-

V,HWE

V,L-

Remark Address, OE: Don't care

1/0: Hi-Z

RAS Only Refresh Cycle

tRAS

tRP

tRAS

teRP

V,HV,L-

Address

V,HV,L-

Remark WE, OE: Don't care

1/0: Hi-Z

II
I

725

NEe

~PD42S17800,4217800

Hidden Refresh Cycle (Read)

tAC

tAC

tRAS

tRAS

V,HVIl-

Address

WE

tCLZ

1/0 VOHVOL-

726

Hi-Z

---------------------------------------

Data out

Hi-Z

NEe

#PD42S17800,4217800

Hidden Refresh Cycle (Write)
IRe
IRAS

ICRP

IRC
IRAS

tCPN

V,HV,L-

Address

V,HV,L-

V,HV,L-

1/0

i>---+--+--"-'-'

......l............................,.......->.........

V,HV,L-

L....l.............................................JI "- _ _ _ _-JO "-.l"-lOr...lI....lL...lL..lL...llL...lOr...lI....lL...lL..lt-''''-'................................IL...lO...........

Remark OE: Don't care

727

NEe

~PD42S17800,4217800

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)
tRe
tRAS

V,HVIL-

tesR

teHR

VIH-

V,L-

V,HV,L-

Remark Address, OE: Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
x 16-bit organization during test mode. Don't care about the input level of the CAS input AO.

(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1 ": Normal write (all memory cells)
Output = "0": Abnormal write

(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.

(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

728

NEe

#PD42S17800,4217800

Package Drawings

28PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

-rr----------~------------r

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A
B

18.63 MAX.
1.075 MAX.
1.27 (T.P.)

0.734 MAX.
0.043 MAX.
0.050 (T.P.)

0.42~8:8~
o.ao.os

0.01HO.003

C

0

1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008 •
0.400±0.004

0.8±0.2

0.031 ~8:8gg

0.14S~8:m

0.006±0.001

L

O.S±O.l

0.020~8:88~

M

0.21
0.10
3.+7•
-3·

0.009
0.004
3.+7•
-3·

E
F

G
H
I

K

N

P

S28G5-5D-7JD3

729

NEe

~PD42S17800,4217800

28 PIN PLASTIC SOJ (400 mill

B
15

-+4----------~-----------+-

u

0

14

P2SLE-400A 1

NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (TP.) at
maximum material condition.

730

ITEM

MILLIMETERS

INCHES

B

1S.67~~§5

0735~~~~~

C

10.16

0.400

D

11.1S±0.2

0.440~~~~~

E

1.0S±0.15

0.043~~~~~

F

0.74

0.029

G

3.5±0.2

0.13S~~~~~

H

2.545±0.2

0.100±0.00S

I

O.S MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P)

0.050 (T.P.)

M

0.40±0.10

0.016~~~~~

N

0.12

0.005

P

9.40±0.20

0.370~~~~~

Q

0.10

0.004

T

R 0.S5

R 0.033

U

0.20~~6g

O.oos~~~~i

i

NEe

~PD42S17800,

'I

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
,uPD42S17800, 4217800.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
,uPD42S17800G5, 4217800G5: 28-pin plastic TSOP (D) (400 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235°C or lower,
Reflow time: 30 seconds or less (210°C or higher),
Number of rellow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-107-2

(10 hours pre-baking is required at 125°C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
VPS

Peak temperature of package: 215°C or lower,
Reflow time: 40 seconds or less (200°C or higher),
Number of rellow processes: MAX. 2
Exposure limit: 7 daysNote

VP15-107-2

(10 hours pre-baking is required at 125°C afterwards)
Cautions
1. After the first reflow process, cool the. package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
Partial heating method

Note

Terminal temperature: 300°C or lower,
Time: 3 seconds or lower (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25°C and relative humidity at 65 % or less.

Caution

l

4217800

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

731

NEe

#PD42S17800, 4217800

IlPD42S17800LE, 4217800LE: 28-pin plastic SOJ (400 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface; 235 °C or lower.
Reflow time; 30 seconds or less (210 °C or higher).
Number of reflow processes; MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 °C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.

Symbol
IR35-207-2

2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
VPS

Peak temperature of package; 215 °C or lower.
Reflow time; 40 seconds or less (200 °C or higher).
Number of reflow processes; MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 °C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).

Partial heating method

Terminal temperature; 300 °C or lower.
Time: 3 seconds or less (Per side of the package).

VPI5-207-2

---

Note. Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 °C and relative humidity at 65 % or less.
Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

732

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD42S18160,4218160
16 M-BIT DYNAMIC RAM
1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE

Description
The JlPD42S18160, 4218160 are 1,048,576 words by 16 bits CMOS dynamic RAMs. The fast page mode and
byte read/write mode capability realize high speed access and low power consumption.
These differ in refresh cycle and the JlPD42S18160 can execute CAS before RAS self refresh.
These are packaged in 50-pin plastic TSOP (ll) and 42-pin plastic SOJ.

Features
•

1,048,576 words by 16 bits organization

•

Fast page mode

•

Fast access and cycle time

Part number

•

Single +5.0 V ± 10 % power supply

Power consumption

Access time

RNV cycle time

Fast page mode

Active (MAX.)

(MAX.)

(MIN.)

cycle time (MIN.)

,uPD42S18160-60, 4218160-60

880mW

60 ns

110 ns

40 ns

,uPD42S18160-70, 4218160-70

825mW

70 ns

130 ns

45 ns

• The JLPD42S18160 can execute CAS before RAS self refresh

Part number

Refresh cycle

Refresh

Power consumption at standby
(MAX.)

,uPD42S18160

1,024 cycles/128 ms

CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh

1.4mW
(CMOS level input)

,uPD4218160

1,024 cycles/16 ms

CAS before RAS refresh,
RAS only refresh,
Hidden refresh

5.5mW
(CMOS level input)

The information in this document is subject to change without notice.
Document No. Mt1083EJ5VODSU1

733

NEe

pPD42S18160,4218160

Ordering Information
Access time
Part number

734

(MAX.)

Package
50-pin plastic TSOP
(400 mil)

Refresh

(m

IlPD42S18160GfHlO
IlPD42S18160G5-70

60 ns
70 ns

IlPD42S18160LE-60
IlPD42S18160LE-70

60 ns
70 ns

42-pin plastic SOJ
(400 mil)

IlPD4218160G5-60
IlPD4218160G5-70

60 ns
70 ns

50-pin plastic TSOP (II)
(400 mil)

IlPD4218160LE-60
IlPD4218160LE-70

60 ns
70 ns

42-pin plastic SOJ
(400 mil)

CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

--------- -

NEe

~PD42S18160,4218160

Pin Configurations (Marking Side)
50-pin Plastic TSOP (11)(400 mil)

I

42-pin Plastic SOJ (400 mil)

.!

lil

50

Vee

1/016

1/01

1/02

1/015

1/02

1/015

1/03

1/014

1/03

1/014

1/04

1/013

1104

1/013

Vee

GND

Vee

GND

'l::
"11

1/012

1/05

1/07

t
!!l

1/011
1/010

1106
1107

1/08

!!!Z

1/09

1/08

NC

NC
NC

Vee

1/05

C

1/06

NC

11

g:

c;)

40

9'

....

......

I\)

01

15
16

c

c;)

III

36

WE

RAS
NC
NC
AO
A1
A2
A3

NC
LCAS
UCAS
OE

29

26

Vee

A9
A8
A7
A6
A5
A4
GND

...

1/011

1,\

'I

1/09

roo
1"

31

CO

en

c

NC
LCAS
UCAS
OE

Iii

21

Ij

1/010

CO

...t

I!

1/016

C

...
g:

I

GND

1/012

t
(/I

RAS
NC
NC
AO
A1
A2
A3
Vee

42
41

'l::
"11

WE

CO

NC
NC

1

0

GND

1/01

22

A9
A8
A7
A6
A5
A4
GND

AD to A9

Address Inputs
1/01 to 1/016 : Data Inputs/Outputs
Row Address Strobe
RAS
UCAS

Column Address Strobe (upper)

LCAS

Column Address Strobe (lower)

WE

Write Enable

OE

Output Enable

Vee
GND
NC

Ground
No Connection

Power Supply

735

NEe

#PD42S18160,4218160

Block Diagram
RAS
LCAS
UCAS
WE

Lower
Byte
Control

Clock Generator

Upper
Byte
Control
Vee

0----CAS before
RAS Counter

GND 0-----

Memory
Cell
Array

N0181

Address
Column
Address
Buffer

1/09

Data
Input
Buffer

Notes 1.

Part number

Column address

pPD42S18160, 4218160

AO-A9

2. JlPD42S18160, 4218160 .. · 1,024

736

x 1,024 x 16

NEe

~PD42S18160,4218160

Input/Output Pin Functions
The p.PD42S18160, 4218160 have input pins RAS, CAsNote 1, WE, OE, AddressNote2
and input/output pins 1/01 to 1/016.
Input!
Output

Pin name
RAS

Input

(Row address
strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a corresponding
word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS

Input

(Column address
strobe)
AO to A9 Note 2

CAS activates data input!output circuit by latching column address and selecting a digit
line connected with the sense amplifier.

Input

Address bus.
Input total 20-bit of address signal, upper bits and lower bitsNote 2 in sequence (address

(Address input)

multiplex method).
Therefore, one word is selected from 1,048,576-word by 16-bit memory cell array.
In actual operation, latch row address by specifying row address and activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, IAsc) and hold time (tRAH, tCAH) are specified
for the activation of RAS and CAS.
WE
(Write enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.

(Output enable)

If WE is activated during read operation, DE is to be ineffective in the device.
Therefore, read operation cannot be executed.
1/01 to 1/016

Input!

16-bit data bus.

(Data input!

Output

1/01 to 1/016 are used to input/output data.

output)

Notes 1. CAS means UCAS and LCAS.

2.

Part number
~PD42S18160,4218160

Address inputs
AO-A9

Upper bits

Lower bits

10 bits

10 bits

737

NEe

yPD42S18160,4218160

Electrical Specifications
CAS means UCAS and LCAS.
All voltages are referenced to GND.
• After power up (Vcc 2! VCC(MIN.), wait more than 100 ps (RAS, CAS inactive) and then, execute ~Ight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Parameter

Symbol

Condition

Rating

Unit

Voltage on any pin relative to GND

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Po

1

W

Operating ambient temperature

T.

o to +70

·C

Storage temperature

Totg

-55 to +125

·C

Caution

Exposing the device to stress above those listed In Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described In the operational section ofthls specification. Exposure to Absolute Maximum Rating
conditlons for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

High level input voltage

V,H

2.4

Vee +1.0

V

Low level input voltage

V,L

-1.0

+0.8

V

Operating ambient temperature

T.

0

70

·C

MAX.

Unit

Parameter

Capacitance (T A

Condition

= 25 ·c, f = 1 MHz)

Parameter
Input capacitance

Data input/output capacitance

738

Symbol

Test condition

Symbol

MIN.

TYP.

C"

Address

5

pF

C,.

mrn, miS, WE, OE

7

pF

CliO

1/0

7

pF

NEe

~PD42S18160,4218160

[MEMO]

739

NEe

.uPD42S18160, 4218160

DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current

Standby
current

IIPD42S18160

Symbol
ICCI

IC02

Test condition

tAAC = 60 ns

160

10

tAAC = 70 ns

150

m

0 mA

RAS, OAS ~ V,H (MIN.),

10 = 0 mA

RAS, CAS
Ic,,",

~

RAS cycling, CAS

~

1CC4

(Fast page mode)

CAS before RAS

RAS S V" (MAX.),

Iccs

refresh current

740

lceo

160

tRAC _ 70 ns

150

tAAC = 60 ns

90

tRAC = 70 ns

80

tRAC - 60 ns

160

tRAC - 70 ns

150

CAS" cycling

= tRC (MIN.)

10 = 0 mA

CAS before RAS
long refresh current
(1,024 cycles 1128 ms,
only for the IIPD42S18160)

tRAC = 60 ns

RAS cycling
tRC

mA

1,2,3

mA

1.0

V,H (MIN.)

tpc = tpc (MIN.), 10 = 0 mA

Notes

2.0

Vcc - 0.2 V, 10 = 0 mA

tRC - tRC (MIN.), 10 = 0 mA

Operating current

2.0

Unit

0.25

0.2 V, 10 - 0 mA

R7\S, t::AS ~ V,H (MIN.). 10 = 0 mA

IIPD4218160

MAX.

tAC :. tRC (MIN.)

rom, ~ ~ Vcc -

"Rirn only refresh current

MIN.

RAS, CAS cycling

mA

1,2,3,4

mA

1,2,5

mA

1,2

CAS before RAS refresh:
tRASS 300 ns
tRC - 125.0 /IS
RAS, CAS:
Vcc - 0.2 V S V,H S V,H (MAX.)
o Vs V" S 0.2 V

350

JIA

1,2

Standby:
RAS, CAS ~ Vcc - 0.2 V
Address: V,H or V,L
WE, OE: V,H
10= 0 mA

400

JIA

1,2

250

JIA

2

tRAS S 1 /IS

Self refresh current
(CAS before RAS self
refresh, only for the
IIPD42S18160)

Icc7

RAS, CAS:
tRA55 == 5 ms
Vcc - 0.2 V S V,H S V,H (MAX.)
o V S V,L S 0.2 V
10 = 0 mA

Input leakage current

It (L)

V, = 0 to 5.5 V
All other pins not under test = 0 V

-10

+10

JIA

Output leakage current

10(L)

Vo - 0 to 5.5 V
Output is disabled (Hi-Z)

-10

+10

!IA

High level output voltage

VOH

10 =-2.5 mA

2.4

Low level output voltage

VOL

10= +2.1 mA

0.4

V

V

Notes 1. ICC1, Icc3, Icc4, Icc5 and Icce depend on cycle rates (tAC and tpc).
2. Specified values are obtained with outputs unloaded.
3. ICCI and Icc3 are measured assuming that address can be changed once or less during RAS S VIL (MAX.)
and OAS <:: VIH (MIN.).
4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

NEe

~PD42S18160,

4218160

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
VIH (MIN.)

=

2.4

VIL (MAX.)

=

0.8 V

V

(2) Output timing specification

---------------~

iL

---------:d- i
,

I

,

---+---i+tr= 5 ns

(3) 0",,",

~:

I.

VOH (MIN.)

=

2.4

V

VOL (MAX.)

=

0.4

V

I

uuu=J
}uuu~._____
.
....1

IT= 5 ns

'''d~o~ndition1:::n

eLl

100pF

590n

Common to Read, Write, Read Modify Write Cycle

Parameter

= 70

tRAC = 60 ns

tRAC

MIN.

MAX.

MIN.

MAX.

130

ns

10

-

Symbol

ns
Unit Notes

Read / Write cycle time

tRC

110

RAS precharge time

tRP

40

CAS precharge time

tCPN

10

-

RAS pulse width

tRAS

60

10,000

70

10,000

ns

CAS pulse width

tCAS

15

10,000

20

10,000

ns

50

ns
ns
1

RAS hold time

tRSH

15

-

ns

tcSH

60

-

18

CAS hold time

70

-

ns

RAS to CAS delay time

tRCD

20

45

20

50

ns

2

RAS to column address delay time

tRAD

15

30

15

35

ns

2

CAS to RAS precharge time

teRP

5

-

5

3

tASA

0

-

0

Row address hold time

tRAH

10

-

10

Column address setup time

tASC

0

Column address hold time

tcAH

15

OE lead time referenced to RAS

tOES

CAS to data setup time
OE to data setup time

15

-

ns

Row address setup time

0

-

ns

15

0

-

tCLZ

0

-

0

tOLZ

0

-

0

0

0

ns
ns
ns
ns
ns
ns
ns

OE to data delay time

tOED

13

Masked byte write hold time

tMRH

0

-

IT

3

50

3

50

ns

tREF

-

128

-

128

ms

-

16

-

16

ms

ns

referenced to RAS
Transition time (rise and fall)
Refresh

)lPD42S18160

time
)lPD4218160

741

NEe

#PD42S18160,4218160

Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 JlS.
If 10 JlS < tRAS < 100 JlS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Inpul condilions
IRAO s; lRAO (MAX.) and IRCO

Access lime

IRCO (MAX.)

Access lime from RAS

IRAC (MAX.)

IRAC(MAX.)

IRAO> lRAO (MAX.) and IRCO s; IRCO (MAX.)

1M (MAX.)

IRAO + 1M (MAX.)

IRCO> IRCD (MAX.)

lCAC (MAX.)

IRCO + ICAC (MAX.)

S;

tRAO (MAX.) and tACO (MAX.) are specified as reference pOints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, 1M or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAO ~ tRAO (MAX.) and tRCO ~ tRCO (MAX.) wiff not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

Read Cycle

Parameler

Symbol

IRAC - 60 ns

IRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

Unil Noles

Access lime from RAS

IRAC

-

60

-

70

ns

1

CAS

!CAc

15

-

20

ns

1

30

1

Access lime from column address

IAA

-

ns

toEA

-

15

-

35

Access lime from OE

20

ns

Column address lead lime
referenced 10 RAS

lRAL

30

-

35

-

ns

Read command selup lime

IRCS

-

a
a

-

ns

tRRH

a
a

-

Read command hold time
referenced 10 RAS

ns

2

Read command hold time
referenced 10 CAS

tRCH

a

-

a

-

ns

2

Oulpul buffer lurn-off delay
time from OE

IOEl

a

13

a

15

ns

3

Oulput buffer lurn-off delay
lime from CAS

IOFF

a

13

a

15

ns

3

Access lime from

Notes 1. For read cycles, access time is defined as follows:
Input condilions

742

Access lime

Access time from ~

IRAO s; IRAO (MAX.) and IRCO s; IRCO (MAX.)

lRAC (MAX.)

IRAC (MAX.)

IRAO> IRAO (MAX.) and IRCO s; IRCO (MAX;)

IAA (MAX.)

IRAO + IAA (MAX.)

IRCO> IRCO (MAX.)

tCAC(MAX.)

tRCO + ICAC (MAX.)

tRAO (MAX.) and tRCO (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, 1M or tCAC) is to be used for finding out when output
data wiff be available. Therefore, the input conditions tRAO ~ tRAO (MAX.) and tRCO ~ tRCO (MAX.) wiff not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

NEe

~PD42S18160,4218160

Write Cycle

Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

Unit Notes

WE hold time referenced to ~

tWCH

10

-

10

-

ns

1

WE pulse width

twp

10

-

10

ns

1

WE lead time referenced to RAS

tRWl

20

20

WE lead time referenced to CAS

tCWL

15

15

-

ns

WE setup time

twcs

0

0

-

ns

OE hold time

tOEH

0

-

-

0

-

ns

ns

2

Data-in setup time

tos

0

-

0

-

ns

3

Data-in hold time

tOH

10

-

15

-

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle

Parameter

Symbol

tRAe

=60 ns

tRAe = 70 ns
MIN.

MAX.

158

180

-

ns

95

-

ns

1

ns

1

ns

1

RAS to WE delay time

tRWO

83

CAS to WE delay time

tcwo

38

-

40

Column address to WE delay time

tAwo

53

-

60

tRWe

Note

MAX.

-

Read modify write cycle time

Unit

MIN.

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), !AWD ~ !AWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions [s
met, the state of the data out is indeterminate.

743

NEe

yPD42S18160,4218160

Fast Page Mode

Parameter

Symbol

tRAe

=60 ns

MIN.

tRAe

MAx.

MIN.

=70 ns

Unit

MAX.

Fast page mode cycle time

tpc

40

-

45

-

ns

Access time from CAS precharge

lAep

-

35

-

40

ns

tRASP

60

125,000

70

125,000

ns

tep

10

-

10

ns

tRHCP

35

-

40

Read modify write cycle time

tPRWC

83

-

90

CAS precharge to WE delay time

tePWD

58

-

65

-

RAS pulse width
CAS precharge time
RAS hold time from CAS precharge

Note

ns
ns
ns

1

Note 1. If twes ~ twes (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD

~

tRWD (MIN.), tewD ~ tewD (MIN.), tAWD

~

tAWD (MIN.) and tePWD

~

tePWD (MIN.), the cycle is a read modify write

cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

Refresh Cycle

Parameter

tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

ns

Symbol

Unit

CAS setup time

tesR

5

-

5

CAS hold time (CAS before RAS refresh)

teHR

10

10

RAS preeharge CAS hold time

tRPe

5

-

-

5

-

ns

RAS pulse width
(CAS before RAS self refresh)

tRASS

100

-

100

-

JlS

1

RAS precharge time
(CAS before RAS self refresh)

tRPS

110

-

130

-

ns

1

CAS hold time

teHs

-50

-

-50

-

ns

1

tWHR

15

-

15

-

ns

ns

(CAS before RAS self refresh)
WE hold time

Note 1. This specification is applied only to the ,uPD42S18160.

744

Note

_~N=E=C=--_ _ _ _ _ _ _ _ _ _ _ _- - -,Jl;.;.;. P. . ; ;D_4_2~S1. . ;8_1. ; . 60. ;. :,_4_2_18.; . . 1. . .;.6. ; . O_ _~II
"(

Read Cycle

B

it

IRe
IRAS

RAS

II

tRP

V,HV,LtCSH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

IOLZ

teLz

UIIO

Lila

VOH- • ___________ •••••••••••••• ~!:.~
VOL-

................................ .

Dalaoul

Hi-Z

.,,!

Ii
I~

745

I
I

NEe

~PD42S18160,4218160

Upper Byte Read Cycle
tRC
tRP

tRAS

RAS

V,HV,LtCSH
tRCD

UCAS

tRSH
tCAS

V,HV,LlMRH

LCAS

V,HV,LtRAL

Address

V,HV,L-

WE

V,HV,LtOES
tOEA

OE

VIH-

V,L- .....;.........................,-?-..................-t......,..........-t-".........................,.....t------+--"'-t"r'......'-'.J.....£..............

tCAC

tcLz
U 1/0

VDHVDL-

Remark L 1/0: Hi-Z

746

Hi-Z

Data out

__~~~E~C:=-__________________________~~~P~D~42~S~1~8~16~O~,4~2~1~8~16~O------~I

Ii
."

Lower Byte Read Cycle

If

!f

tRC
tRP

tRAS

RAS

II!

V,HV,L-

l'~

V,HV,L-

LeAS

!l
i!

V,HV,L-

\I

:}
~ ,'\

i '~

Address

V,HV,L-

WE

V,HVu.-

OE

~~~~~~~~

V,HV,L-

tOLZ

teLz

LIIO

VOHVOL-

Hi-Z

Data out

Hi -Z

Remark U 1/0: Hi-Z

1·1

'1

II

747

i

NEe

~PD42S18160,4218160

Early Write Cycle
lAC
lRAS

RAS

V,HV,,IcsH

UCAS
LCAS

V,HV,,-

Address

V,HV,,-

WE

V,HV,L-

UI/O
LIIO

V,HV,L-

Remark OE: Don't care

748

NEe

~PD42S18160,4218160

Upper Byte Early Write Cycle
tRC
tRAS

RAS

tRP

V,HV,LtCSH

V,H-

UCAS

VIL-

LCAS

V,HV,L-

:;\

Address

V,HV,L-

WE

V,HV,L'-

UI/O

l

ij

V,HV,L-

L...lt..lol~...K....K...lL.Jj~...lL.3

"'"--'-----'1 ,,~...K....K...lL_'l~...lL.

..............,L_'I'_"'......................,...................................

Remark OE, L 1/0: Don't care

I

749

I

NEe

~PD42S18160,4218160

Lower Byte Early Write Cycle
IRC

lRAS

V,HV,L-

V,HV,L-

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

Lila

V,HV,L-

Remark OE, U 1/0: Don't care

750

IRP

I

NEe

I'I

~PD42S18160,4218160

i

Late Write Cycle
tAC

RAS

1.1

tAP

IAAS

I'

V,HVILtCSH
tACO

tASH
tCAS

UCAS
LCAS

V,HVIL-

Address

V,HV,L-

WE

V,HV,L-

OE

!J

V,HVIL~

L...i'-'-...................J
toED

UI/O
Ll/O

ZZZ> .......~~:~ .......

tOH

Oatain

i
1

751 .

NEe

~PD42S18160,4218160

Upper Byte Late Write Cycle

LeAS

V,HV,L-

Address

V,HWE

-,,,.....,.....,-r-r-r-r.,-!r-------J

V,L-

OE

tOH

U 1/0

YXJ)-------~!:-~- ------

Remark L 1/0: Don't care

752

Data in

NEe

pPD42S18160,4218160

Lower Byte Late Write Cycle

lAC
lRAs
RAS

IRP

V,HV,L-

,.1
,

I ~

:~

tMRH

UCAS

V,HV,LlesH
tReD

LCAS

V,HV,L-

Address

V,HV,L-

WE

IRSH

leAS

V,HV,L- "-"-'~....L....L...L....L..L...J

IOH

LIIO

V,H- ~ •••• _._!i.i:_~
VIL-~

.. __ ...

Data in

Remark U I/O: Don't care

753

I

NEe

~PD42S18160,4218160

Read Modify Write Cycle
tRWC

tRAS

RAS

tRP

V,HVIltesH
tReD

UCAS
LCAS

V,HVIl-

Address

V,HVIl-

WE

V,HVIl-

tRSH
teAs

OE

U 1/0
L 1/0

U 1/0
L 1/0

754

~ .. -.. -.. -.. -.... -..

VOH- ............... _.. - ...................................
Hi - Z
..
VOL-

Hi -Z

NEe

~PD42S18160,4218160

Upper Byte Read Modify Write Cycle
tRWC

tRP

tRAS

RAS
tesH
tReo

tRSH
teAs

UCAS

Address

WE

OE

U 1/0

V,HVIL-

V,H-

V,L-

V,H-

V,L-

~-------------------

VOH- ____________________ ~~:~ _______________ _

UI/O

Hi -Z

voL-

Remark In this cycle, the input data to Lower I/O is ineffective. The data out of that remains Hi-Z.

755

NEe

~PD42S18160,4218160

Lower Byte Read Modify Write Cycle
IRwe
tRAS

Address

V,HV,L-

WE

V,HVIL-

OE

V,HVIL-

Lila

V,HVIL-

Lila

VOHHi - Z
.................... - ..............................................
- .. ..
VOL-

IRP

~., ............... ..

Hi-Z

Remark In this cycle, the inpLlt data to Upper I/O is ineffective. The data out of that remains Hi-Z.

756

NEe

~PD42S18160,4218160

Fast Page Mode Read Cycle
tRASP
tRHCP

RAS
tesH

UCAS
LCAS

Address

VIH-

V,L-

VIHVIL-

WE

V,HVIL-

OE

V,HVIL-

UIIO
LIIO

VOHVOL-

Remark

....•........ . Ij!:.l,. ......••..

In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

757

NEe

,uPD42S18160,4218160

Fast Page Mode Byte Read Cycle
IRASP

V,HV,L-

IRHCP

Ipc

ICSH

IRSH

ICAS

lCAS

V,HV,Lb.1RH

LeAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

U 1/0

VOHVOL-

Hi -Z
IOEl

L 1/0

VOHVOL-

Hi - Z

Hi - Z

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

758

1;1

____~_E
__c:~__________________________~~_P_D_42_S_1_8_16_0~,4_2_1_8_16_O______~~

I
I!

Fast Page Mode Early Write Cycle

Ij

:!

I
,~

- - V,HRAS VIL-

I

UCAS V,HLCAS V,L-

Address V,HV,L-

U I/O V,HL I/O V,L-

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

759

NEe

~PD42S18160,4218160

Fast Page Mode Byte Early Write Cycle
tRASP

RAS VIH~

tRHCP

VIL~

UCAS

VIHVIL-

LCAS VIH~
VIL~

Address VIH~
VIL~

WE

VIH-

VIL~

U I/O

VIH-

VIL~

L I/O VIH~
VIL~

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

760

NEe

~PD42S18160,4218160

Fast Page Mode Late Write Cycle
tRASP
tRHCP

RAS V,HVIl-

UCAS
LCAS

V,HVIl-

Address V,HV,L-

WE V,H-

V,L-

OE V,HVIl-

U 1/0
L 1/0

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

761

NEe

~PD42S18160,4218160

Fast Page Mode Byte Late Write Cycle
tRASP
tRHCP

V,HV,Ltpe

tesH
teAs

tRSH

teAs

V,HVIL-

tMRH

V,HV,L-

Address

V,HVIL-

V,HVIL-

U I/O V,HVIL-

L 1/0

V,H- _____ .t-lj:_~ ________ _
VIL-

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

762

NEe

~PD42S18160,4218160

I
!

Fast Page Mode Read Modify Write Cycle

RAS V,H-

V,L-

UCAS
LCAS

V,H-

V,L-

V,H-

Address V,L-

WE

V,HV,L-

OE

V,HV,L-

11

Ij
I

U 1/0 VOHLila VQL-

U 1/0 V,H-

Lila VIL-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

763

NEe

~PD42S18160,4218160

Fast Page Mode Byte Read Modify Write Cycle
tRASP

RAS

V,HVIL-

IPRWC
tCAS

LeAS

VIHVILIRAL

Address

WE

VIHVIL-

VIHVIL-

OE

VIHVIL-

U 1/0

l..-.rl>r
l>

l>

26
25
24
23
22
21

GND

19
18

A8
A7

17
16
15

A6
A5

14

GND

1/04
1/03

A9

A4

A 11 '" JlPD42S16400L, 4216400L
NC ... JlPD42S17400L, 4217400L

AO to A11

Address Inputs

1/01 to 1/04

Data Inputs/Outputs

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

777

NEe

,uPD42S16400L, 4216400L, 42S17400L, 4217400L

Block Diagram

OOE

Clock
Generator

Vee 0 - - -

GND~

CAS before
RAS Counter
Memory
Cell
Array

1/01
to
1/04

Row
Address
Buffer
AddressNote 1
Column
Address
Buffer

Notes 1.

Part number

Row address

~PD42Sl6400L,42l6400L

AO -All

AO-A9

~PD42Sl7400L,42l7400L

AO-Al0

AO - Al0

2. ,uPD42S16400L, 4216400L ... 4,096 x 1,024 x 4

778

Column address

,uPD42S17400L, 4217400L ... 2,048 x 2,048 x 4

I

~

______________
-'-_______
-'-_____
---=-_________
---j1511
NEe
.uPD42S16400L,"--____
4216400L,
42S17400L,
4217400L

1%

I!

'.'

Input/Output Pin Functions
The tLPD42S16400L, 4216400L, 42S17400L, 4217400L have input pins RAS, CAS, WE, OE, Address Note and
input/output pins 1/01 to 1/04.

Pin name

Input/Output

RAS

Input

(Row address strobe)

Function
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS

Input

CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.

Input

Address bus.
Input total 22-bit of address signal, upper bits and .Iower bits Note in sequence

(Column address strobe)
AO to Ax Note
(Address inputs)

(address multiplex method).
Therefore, one word is selected from 4,194,304-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tAse) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE
(Output enable)

Input

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
It WE is activated during read operation, OE is to be ineffective in the device.

1/01 to 1/04
(Data inputs/outputs)

Input/Output

Therefore, read operation cannot be executed.

Note

4-bit data bus.
1/01 to 1/04 are used to input/output data.

Address inputs

Upper bits

Lower bits

~PD42S16400L,

4216400L

AO - All

12 bits

10 bits

~PD42S17400L..

4217400L

AO - Al0

11 bits

11 bits

Part number

779

NEe

pPD42S16400L, 4216400L,42S17400L, 4217400L

Electrical Specifications
•

All voltages are referenced to GND.
After power up (Vcc~ Vcc (MIN.)), wait more than 100 /JB (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

VT

-0.5 to +4.6

V

Supply voltage

Vee

-D.5 to +4.6

V

Output current

10

20

mA

Parameter

Symbol

Condition

Power dissipation

Po

1

W

Operating ambient temperature

TA

o to +70

·C

Storage temperature

TSlg

-55 to +125

·C

Caution

Exposing the device to stress above those listed In Absolute Maximum Ratings could cause
permanent damage. The device Is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
Parameter

TYP.

MAX.

Unit

3.0

3.3

3.6

V

2.0

Vee + 0.3

V

-0.3

+0.8

V

70

·C

MAX.

Unit

Address

5

pF

Condition

Vee

High level input voltage

V,H

Low level input voltage

V,L

Operating ambient temperature

TA

0

Capacitance (TA

=25 ·c, f = 1 MHz)

Parameter

780

MIN.

Symbol

Supply voltage

Symbol

Test condition

MIN.

TYP.

Input capacitance

C"
C'2

RAS, CAS, WE, OE

7

Data input/output capacitance

ClIO

1/0

7

pF

NEe

~PD42S16400L,4216400L,42S17400L,4217400L

I

DC Characteristics (Recommended operating conditions unless otherwise noted)

I

IJlPD42S16400L,4216400L]
Parameter
Operating current

Symbol
Icc!

MAX.

Unit

Notes

RAS, CAS cycling

Test condition
tRAe = 60 ns

80

mA

1,2,3

tRe = tRe (MIN.)

tRAe = 70 ns

70

10 = 0 mA

Standby

IIPD42S16400L

le02

MIN.

tRAe = 80 ns

i~

Ii

60

RAS, CAS

~

V,H (MIN.), 10 = 0 mA

0.5

RAS, CAS

~

Vee - 0.2 V, 10 = 0 mA

0.15

RAS, CAS

~

VIH (MIN.), 10 = 0 mA

2.0

RAS, CAS

~

Vee - 0.2 V, 10 = 0 mA

I

mA

I

current
IIPD4216400L

RAS only refresh current

lee3

RAS cycling, CAS

~

VIH (MIN.)

tRe = tRe (MIN.), 10 = 0 mA

Operati ng cu rrent

Icc.

(Fast page mode)

CAS before RAS

Ices

refresh current

CAS before RAS
·Iong refresh current
(4,096 cycles 1128 ms,
only for the IIPD42S16400L)

Ieee

0.5

tRAe = 60 ns

80

tRAe = 70 ns

70

mA

1,2,3,4

mA

1,2,5

mA

1,2

220

ItA

1,2

150

ItA

2

tRAe = 80 ns

60

RAS s V,L (MAX.), CAS cycling

tRAe = 60 ns

70

tpc = tpe (MIN.), 10 = 0 mA

tRAe = 70 ns

60

tRAe = 80 ns

50

RAS cycling

tRAe = 60 ns

80

tRe = tRe (MIN.)

tRAe = 70 ns

70

10 = 0 mA

tRAe = 80 ns

CAS before RAS refresh :
tRe = 31.3 !IS
RAS, CAS:
Vee - 0.2 V S VIH S VIH (MAX.)
o V S VIL S 0.2 V

60

tRAS S 1 liS

Standby:
RAS, CAS ~ Vee - 0.2 V
Address: VIH or VIL
WE, OE: VIH
10 = 0 mA
CAS before RAS
self refresh current
(only for the IIPD42S16400L)

lee7

RAS, CAS:
tRASS = 5 ms
Vee - 0.2 V S VIH S VIH(MAX.)
o V S VIL s 0.2 V
10= 0 mA

Input leakage current

It(L)

VI = 0 to 3.6 V
All other pins not under test = 0 V

-5

+5

ItA

Output leakage current

10(L)

Va = 0 to 3.6 V
Output is disabled (Hi-Z)

-5

+5

ItA

High level output voltage

VOH

10 = -2.0 mA

2.4

Low level output voltage

VOL

10 = +2.0 mA

V
0.4

V

781
-----------------

NEe

jlPD42S16400L, 4216400L,42S17400L, 4217400L

[JlPD42S17400L,4217400L]
Parameter
Operating current

Symbol
lee1

MAX.

Unit

Notes

RAS. CAS cycling

tRAe = 60 ns

100

mA

1.2.3

tRC .. tRC (MIN.)

tRAe

=70 ns
tRAe =80 ns

90

=0 mA
0.2 V. 10 =0 mA

0.5

10
Standby

pPD42S17400L

le02

=0 mA

RAS. CAS

~

pPD4217400L

RAS only refresh current

lee3

RAS. CAS

~

V,H (MIN.). 10 = 0 mA

RAS. CAS

~

Vee - 0.2 V. 10

RAS cycling. CAS

~

V,H (MIN.)

tRe - tRe (MIN.), 10 - 0 mA

Operating current

leo.

(Fast page mode)

RAS

~

V,L (MAX.). CAS cycling

=tpc (MIN.). 10 =0 mA

tpe

lees

refresh cu rrent

RAS cycling
tRe

=0 mA

=tRe (MIN.)

CAS before RAS
long refresh current
(2.048 cycles I 128 rns.
only for the pPD42S17400L)

lee6

0.5

=60 ns
tRAe =70 ns

100

tRAe = 80 ns

80

tRAe

70

tRAe - 70 ns

60

=80 ns
=60 ns

CAS before RAS refresh:
tRe =62.5 JLS
RAS. CAS:
Vee - 0.2 V ~ V,H ~ V,H (MAX.)
o V ~ V,L ~ 0.2 V

1.2.3,4

mA

1.2.5

rnA

1.2

50
100

tRAe = 70 ns
tRAe

mA

90

=60 ns

tRAe

tRAe

10= 0 mA

mA

0.15
2.0

tRAe
CAS before RAS

80

V,H (MIN.). 10

RAS. CAS ~ Vee -

current

MIN.

Test condition

90

=80 ns

80

~

200

jtA

1.2

150

jtA

2

tRAS

1 JLS

Standby:
RAS. CAS ~ Vee - 0.2 V
Address: V,H or V,L
WE. OE: V,H
10= 0 rnA
CAS before RAS
self refresh current
(only for the pPD42S17400L)

lee7

RAS. CAS:
tRASS = 5 ms
Vee - 0.2 V ~ V,H

~

V'H(MAX.)

o V~ VIL~ 0.2 V
10

=0 rnA

" (L)

V, = 0 to 3.6 V
All other pins not under test = 0 V

-5

+5

pA

Output leakage current

10(L)

Vo =0 to 3.6 V
Output is disabled (Hi-Z)

-5

+5

jtA

High level output voltage

VOH

10- -2.0 mA

2.4

Low level output voltage

VOL

10 - +2.0 mA

Input leakage current

V
0.4

V

Notes 1. ICC1. Icc3. Icc4. Icc5 and Icc6 depend on cycle rates (tRC and tpc).

782

2. Specified values are obtained with outputs unloaded.
3. Iccl and Icc3 are measured assuming that address can be changed once or less during RAS S V,L (MAX.)
and CAS;:: V,H (MIN.).
4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

---i!

_----.:.N.....::....:::E::..:C=-_ _ _ _----!.Il_P_D_42_S_1...;.6_40...;"O_L...:....,_42_1_6_40_0_L...:....,_42_S_1_74_0_0_L.:--,4_2_1_74_0_0_L_ _

,t

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification

(MIN.)

=2.0 V

VIL

(MAX.)

= 0.8 V

11

(2) Output timing specification

----------------r1

VIH

i!

VOH

i, L
,

.--------~
i
, '

.. : :4
tr=5ns

(MIN.)

= 2.0 V

n----=J

~

}-

I~

VOL (MAX.) = 0.8 V ------~'______ _ I

---+i--+etr=5ns

(3) Output load condition
Vee

1.180n

I/O

---.---+
870n

Common to Read, Write, Read Modify Write Cycle
lRAC - 60 ns
Parameler

IRAC - 70 ns

lRAC = 80 ns

Symbol

Unil Noles
MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

130

150

-

ns

60

-

ns

CAS precharge lime

IcPN

10

-

10

-

10

-

ns

RAS pulse widlh

IRAS

60

10,000

70

10,000

80

10,000

ns

CAS pulse widlh

ICAS

15

10,000

18

10,000

20

10,000

ns

RAS hold lime

IRSH

15

-

18

20

IcSH

60

-

70

80

-

ns

CAS hold lime

-

RAS 10 CAS delay lime

IRCD

20

45

20

52

25

60

ns

2

RAS 10 column address delay lime

IRAD

15

30

15

35

17

40

ns

2

CAS 10 RAS precharge lime

leRP

5

-

5

-

5

-

ns

3

a

-

Read I Wrile cycle lime

IRC

110

RAS precharge lime

IRP

40

50

Row address selup lime

IASR

a

Row address hold lime

lRAH

10

-

10

Column address selup lime

lASe

0

-

0

Column address hold lime

lCAH

15

OE lead lime referenced 10 RAS

IOES

a

CAS 10 dala selup lime

leLl

0

OE 10 dala selup lime

lOll

a

OE 10 dala delay lime

toED

15

Transilion lime (rise and fall)
Refresh lime

-

0

-

ns

-

ns

0

-

ns

15

ns

ns

a
a

-

0

-

0

0

-

0
20

-

15

ns

12

-

15

ns
ns
ns

IT

3

50

3

50

3

50

ns

IREF

-

128

128

-

128

ms

pPD4216400L

-

64

-

64

ms

pPD4217400L

-

32

-

32

-

32

ms

pPD42S16400L, 42S17400L

64

1

4

783

NEe

,uPD42S16400L,4216400L, 42S17400L, 4217400L

Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 p.s.
If 10 p.s < tRAS < 100 p.s, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions

Access time

tRAD S tRAD (MAX.) and tRCO s tRCD (MAX.)

Access time from RAS
tRAC (MAX.)

tRAC{MAX.)

tRAD > tRAD (MAX.) and tRCD S IRCD (MAX.)

IAA (MAX.)

tRAD + tM (MAX.)

tRCD> tRCD (MAX.)

tCAC(MAX.)

tRCD + tCAC (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference pOints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tACO (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the JLPD42S16400L, 42S17400L.
Read Cycle
Parameter

Symbol

tRAC - 60 ns

tRAC - 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

70

-

80

ns

1

18

-

20

ns

1

35

-

40

ns

1

20

ns

Access time from RAS

tRAC

-

60

Access time from CAS

tCAC

-

15

Access time from column address

IAA

30

Access time from OE

tOEA

-

Column address lead time referenced to RAS

tRAL

30

tRCS

0

Read command hold lime referenced 10 RAS

IRRH

0

Read command hold lime referenced 10 CAS.

IRCH

0

-

35

Read command setup time

Outpul buffer lurn-off delay time from OE

10El

0

Oulpul buffer lurn-off delay lime from CAS

IOFF

0

15

18

40

0

-

0

-

15

0

15

0

15

0

15

0

0
0

0
0

Unit Notes

ns
ns
ns

2

ns

2

20

ns

3

20

ns

3

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access lime

Access time from RAS

IRAD S IRAD (MAX.) and IRCD S IRCD (MAX.)

tRAC (MAX.)

IRAC (MAX.)

IRAD > lRAD (MAX.) and tRCD S IRCD (MAX.)

IAA (MAX.)

IRAD + tM (MAX.)

IRCD > IRCD (MAX.)

tCAC(MAX.)

IRCD + ICAC (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

784

,uPD42S16400L, 4216400L, 42S17400L, 4217400L
'I
NEe
----..:.....--=----=----~-il
Write Cycle
Parameter
WE hold time referenced to CAS

Symbol
tWCH

=70 ns

tRAC

=80 ns

tRAC = 60 ns

tRAC

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

10

-

10

-

15

-

ns

1

15

-

ns

1

20

-

ns

I

Unit Notes

WE pulse width

twp

10

-

10

WE lead time referenced to RAS

tRWL

20

-

20

WE lead time referenced to CAS

tewL

15

-

15

-

15

-

ns

WE setup time

twcs

0

-

0

-

-

ns

OE hold time

tOEH

0

-

0

-

a
a

-

ns

Data-in setup time

tDS

0

0

-

0

-

ns

3

Data-in hold time

tDH

10

-

15

-

15

-

ns

3

2

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles,. twCH (MIN.) should
be met.
2. If twcs 2: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter

Symbol

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

180

-

205

-

95

-

110

-

ns

1

43

-

50

ns

1

60

-

70

-

ns

1

tRWC

160

RAS to WE delay time

tRWD

85

CAS to WE delay time

tewD

40

tAwo

tRAC = 80 ns

tRAC

Read modify write cycle time

Column address to WE delay time

=70 ns

tRAC = 60 ns

55

Unit

Note

ns

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD 2: tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD 2: tAWD (MIN.) and tCPWD 2: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

785

NEe

~PD42S16400L,

4216400L,42S17400L, 4217400L

Fast Page Mode
tRAe
Parameter

= 60 ns

tRAe

= 70 ns

tRAe

= 80 ns

Symbol
MIN.

MAX.

MIN.

MAX.

MIN.

Unit

Fast page mode cycle time

tpe

40

-

45

-

50

-

Access time from CAS precharge

tAep

-

35

-

40

-

45

ns

RAS pulse width

tRASP

60

125,000

70

125,000

80

125,000

ns

tep

10

Read modify write cycle time

tPRWC

83

CAS precharge to WE delay time

tePWD

58

-

ns

35

-

10

tRHCP

-

10

RAS hold time from CAS precharge

CAS precharge time

Note 1.

40
90
65

45
95
70

Note

MAX.
ns

ns
ns
ns

1

If twcs ~ twcs (MIN.I, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN. I, tCWD ~ tCWD (MIN.I, tAWD ? tAWD (MIN.I and tCPWD ? !cPWD (MIN.I, the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

Refresh Cycle
tRAe
Parameter

MIN.

MAX.

-

CAS setup time

tesR

5

CAS hold time (CAS before RAS refresh)

tCHR

10

RAS precharge CAS hold time
RAS pulse width (CAS before RAS self refresh)

= 60 ns

tRAe

= 70 ns

= 80 ns
Unit

tAPe

5

tRASS

100

RAS preeharge time (CAS before RAS self refresh)

tRPS

110

CAS hold time (CAS before RAS self refresh)

teHs

-50

WE setup time

tWSR

10

-

WE hold time

tWHR

15

-

MIN.

MAX.

-

5

-

10

5

-

100

-

100

-

MIN.

MAX.

5
10

5

130

-

150

-50

-

-50

-

10

10
15

Note 1. This specification is applied only to the JlPD42S16400L, 42S17400L.

786

tRAe

Symbol

15

Note

ns
ns
ns
Il S

1

ns

1

ns

1

ns
ns

NEe

,uPD42S16400L, 4216400L, 42S17400L, 4217400L

----------~~----------------~------------~~--------~------------~------------------~~'
!~
I,~;

t

Read Cycle

i
!i

I~

tRe
tRP

tRAS

RAS

V,HVILtesH

CAS

V,HVIL-

Address

WE

V,HVIL-

tCAC

tOll
tell

1/0 VOHVOL-

Hi-Z

Data out

Hi-Z

NEe

~PD42S16400L,4216400L,42S17400L,

Early Write Cycle
IRC
tRAS

RAS

V,HVILICSH

CAS

V,HVIL-

Address

V,HVIL-

WE

V,HV,L-

1/0

V,HV,L-

Remark OE: Don't care

788

IRP

4217400L

NEe

~PD42S16400L,4216400L,

42S17400L,4217400L

Late Write Cycle
tRC
tRAS

RAS

V,HVILtCSH

CAS

V,HVIL-

Address

V,HVIL-

I~

,I

:1
!
i

tOEH

OE

V,HV,LtOED

789

NEe

JlPD42S16400L, 4216400L,42S17400L, 4217400L

Read Modify Write Cycle
tRWC

tRAS

ICSH
IRCO
CAS

V,HVIL-

Address

V,HVIL-

IRSH

tAWD

Icwo
WE

V,HV,L-

IOEH

IDEA
OE

V,HV,L-

1/0

V,HV,L-

ICAC

~---------

-

los

IOH
Dalain

IOLZ

1/0

790

VOHVOL-

Hi-Z

Hi-Z

I,l

NEe

,uPD42S16400L, 4216400L, 42S17400L, 4217400L!

------------------------------------~------------------~------------~------------~~------------------------~Ii

"\

i,1

Fast Page Mode Read Cycle

l

tRP

tAASP
tRHCP

VIH-

,~

VIl-

.j
tCSH

V,H-

tpe

tASH

--Ir--++----.i""""

VIl-

Address

V,H-

-,-r-r-t-r-H--t-----tV-'-++-----flt-"""'-ir-+----t--tV-T"""'........~

VIl- '--L....'-'''-,''-'

VIH-

V,L-

1/0

VOH- __________ ~J-.?_________ _
VOL-

Data out

Hi-Z
-------_.

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

I:
I

I'

:j

Ii
I

I,

I

i'
I~

I'
I,
:"~

i
I

791

NEe

~PD42S16400L,

4216400L,42S17400L, 4217400L

Fast Page Mode Early Write Cycle

V,HVIL-

Address

V,HVIL-

WE

1/0

V,HVIL-

L..l'-lol;...>L..lt...¥...Y ~_ _ _ _---II

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the

consecutive CAS cycles within the same RAS cycle.

792

NEe

~PD42S16400L,4216400L,42S17400L,4217400L

i~

Fast Page Mode Late Write Cycle

tRP

CAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

1/0

V,HVll-

V,HVll-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

,1
"

Il
I

,

I

i.:

1
II.'

793

II

II

NEe

~PD42S16400L,

4216400L, 42S17400L, 4217400L

Fast Page Mode Read Modify Write Cycle

V,HVIL-

V,HVIL-

Address

V,HVIL-

OE

I/O VOHVOL-

1/0

V,HVIL-

Remark

In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

794

NEe

~PD42S16400L,4216400L,42S17400L,4217400L

CAS Before RAS Self Refresh Cycle (Only for the JlPD42S16400L, 42S17400L)

IRASS

RAS

V,HVIL-

I'

r

~

i

il

lesR

CAS

M

V,HVIL-

~
Remark Address, OE : Don't care

:\\\\\\\\\\\\\\\\\\\\\\\

I/O : HI·Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS before
RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with long RAS
only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh as follows just before and after setting CAS before RAS self refresh.
JlPD42S16400L: 4,096 times within a 64 ms interval
JlPD42S17400L: 2,048 times within a 32 ms interval
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh as follows just before and after setting CAS before RAS self refresh.
JlPD42S16400L: 4,096 times within a 64 ms interval
JlPD42S17400L: 2,048 times within a 32 ms interval
(3) If tRASS(MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 JlS), CAS before
RAS refresh cycles will be executed one time.
If 10 JlS < tRAS < 100 JlS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles as follows should be met.
JlPD42S16400L: 4,096 times within a 128 ms interval
JlPD42S17400L: 2,048 times within a 128 ms interval
For details, please refer to How to use DRAM User's Manual.

795

NEe

~PD42S16400L,

4216400L,42S17400L, 4217400L

CAS Before RAS Refresh Cycle

tRAS

tCSA

tCHA

V,HVIL-

VIH-

WE

VIL-

Remark Address, OE: Don't care

110: Hi-Z

RAS Only Refresh Cycle
tRC
tRAS

V,H-

VILtCRP

VIH-

VIL-

Address

V,HV,L-

Remark WE, OE: Don't care. I/O: Hi-Z

796

tRAS

NEe

~PD42S16400L,4216400L,42S17400L,4217400L
!

I
I

Hidden Refresh Cycle (Read)

RAS

tRC

tRC

tRAS

tRAS

tRCO

CAS

I

V,HV,L-

tRSH

tCHR

tCPN

V,HVIL-

tCLZ

110 VOHVOL-

Hi-Z

Data out

Hi-Z

797

NEe

~PD42S16400L,4216400L,

42S17400L,4217400L

Hidden Refresh Cycle (Write)
tRC
tRAS

Address

WE

tRC
tRAS

V,H-

V,l-

V,H-

..>...,;...,.__-+_+-+<--J

V,l- --"-"--"-.>....J................

I/O

V,H-

V,l- ~~.lL..,;IL..lOr...lL....lL.lL...l1...Y

Remark OE: Don't care

798

"--_ _ _-JI 'IL..l1C....ll....lL.lL..lL...lL...lL....lL.lL..lL...lL...lL....lL.lL..lL...lL...lL....lL.lL..lL...lL...lL-1

NEe

~PD42S16400L,4216400L,42S17400L,4217400L

l

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)

I

!~i

:1

Remark Address, OE: Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
x 16-bit organization during test mode. Don't care about the input levels of the CAS input AO, A 1.
(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1": Normal write (all memory cells)
Output = "0": Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS !:lefore RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

799

NEe

~PD42S16400L,4216400L,42S17400L,4217400L

Package Drawings

26PIN PLASTIC TSOP(ll) (300 mil)

detail of lead end

+-t-----+-------+

A

13

.1
H

~~

~

~JJ

L

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A

17.36 MAX.
1.06 MAX.
1.27 (T.P.)

0.684 MAX.
0.042 MAX.
0.050 (T.P.)

0

0.42~g:g~

0.017±0.003

E

0.aO.05
1.2 MAX.
0.97
9.22±0.2
7..62±0.1

0.004±0.002
0.048 MAX.
0.038
0.363±0.008
0.300±0.OO4

0.8±0.2

0.031 ~8:gg~

0.145~g:m

0.006±0.001

0.5±0.1

0.020~g:gg~

0.21
0.10
30+ 70
-3°

0.009
0.004
30+70
-3°
S26G3-5D-7JDl

B
C

F

G
H

K

M
N

P

800

NEe

II

.uPD42S16400L, 4216400L, 42S17400L, 4217400L

----~~------~--------~----~----~-----------i~

il

26 PIN PLASTIC SOJ (300 mil)
B

26

!I
14

~~---------~------------r

U

0

13

"

"

J:

-

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

17.3~8:~g

0.681~8:8~S

c

7.62

0.300

0

8.47±0.2

0.333~8:883

E

1.03±0.15

0.041 ~8:88~

F

0.029
0.138tO.008
0.100tO.008
0.031 MIN.
0.102
0.050 (T.P.) _

K

0.74
3.5±0.2
2.545tO.2
0.8MIN.
2.6
1.27 (T.P.)

M

0.40±0.10

0.016~8:88~

N
P
T

0.12
6.73±O.2
0.10
RO.85

0.005
0.265±0.008
0.004
RO.033

U

0.20~:6g

0.008~8:88~

G
H

a

S28LA-300A-1

801

NEe

pPD42S16400L, 4216400L, 42S17400L, 4217400L

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
~PD42S16400L,4216400L,42S17400L,4217400L.

For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).
'"
.
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
~PD42S16400LG3.

4216400LG3. 42S17400LG3. 4217400LG3: 26-pin plastic TSOP (11)1300 mill

Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210'C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Symbol
IR35-1 07-2

(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the flrat reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the flrat reflow process, do not use water to remove
residual flux lwater can be used In the second process).
VPS

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),

VP15-107-2

Number of reflow processes: MAX. 2
Exposure limi: 7 daysNote
(10 hours pre-baking is required at 125'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux Iwater can be used In the second process).
Partial heating method

Note

---

Exposure limit before soldering after dry-pack paCkage is opened.
Storage conditions: 25 JC and relative humidity at 65 % or less.

Caution

802

Terminal temperature: 300'C or lower,
Time: 3 seconds or lower (Per side of the package).

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

_ _N_E_C~_ _ _ _ _-!..J1_P_D_4_2S_1_6_4_0_0L-,-,_4_2_16_4_0_0_L.:....,4_2_S_1_7_40_0_L....:...,_4_21_7_4_0_0_L_ _ _ 1

!

1,

.uPD42S16400LLA, 4216400LLA, 42S17400LLA, 4217400LLA: 26-pin plastic SOJ (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210'C or higher),
Number of reflow processes: MAX. 2
Exposure lim it: 7 days Note

i

.~

Symbol

1$

~

IR35-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.

2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).

VPS

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit :7 daysNote

VP15-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions

1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.

2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).

Partial heating method

Note

Terminal temperature: 300'C or lower,
Time: 3 seconds or less (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method",

Ii
II

,I
11

!l

'j

!'

IiI ~
Ii

,,
j

803

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NEe
[MEMO]

804

~PD42S16400L,4216400L,42S17400L,4217400L

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

~PD42S17800L,4217800L
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
2 M-WORD BY 8-BIT, FAST PAGE MODE

Description
TheJLPD42S17800L, 4217800L are 2,097,152 words by 8 bits CMOS dynamic RAMs. The fast page mode
capability realize high speed access and low power consumption.
These differ in refresh cycle and the I'PD42S17800L can execute CAS before RAS self refresh.
These are packaged in 28-pin plastic TSOP aI) and 28-pin plastic SOJ.

Features
•

• 2,097,152 words by 8 bits organization

Single +3.3 V ± 0.3 V power supply

• Fast page mode
• Fast access and cycle time

Power consumption

Access time
(MAX)

R/W cycle time

Fast page mode

Active (MAX.)

(MIN.)

cycle time (MIN.)

JLPD42S17800L-A60, 4217800L-A60

360mW

60 ns

110 ns

40 ns

I'PD42S17800L-A70, 4217800L-A70

324mW

70 ns

130 ns

45 ns

Part number

• The I'PD42S17800L can execute CAS before RAS self refresh

Refresh cycle

Refresh

Power consumption at standby
(MAX)

}lPD42S17800L

2,048 cycles/128 ms

CAS before RAS self refresh,
CAS before RAS refresh.
RAS only refresh. Hidden refresh

0.54mW
(CMOS level input)

}lPD4217800L

2.048 cycles/32 ms

CAS before RAS refresh.
RAS only refresh.
Hidden refresh

1.8mW
(CMOS level input)

Part number

The Information In this document is subject to change without notice.
Document No. M110B2EJ5VODSU1

805

~PD42S17800L,4217800L

NEe
Ordering Information
Access time
(MAX.)

Package

,uPD42S17800LG5-A60
JjPD42S17800LG5-A70

60 ns
70 ns

28-pin plastic TSOP (ll)
(400 mil)

JjPD42S17800LLE-A60
.uPD42S17BOOLLE-A70

60 ns
70 ns

28-pin plastic SOJ
(400 mil)

JjPD4217800LG5-A60
.uPD4217800LG5-A70

60 ns
70 ns

28-pin plastic TSOP (II)
(400 mil)

JjPD4217800LLE-A60
.uPD4217800LLE-A70

60 ns
70 ns

28-pin plastic SOJ
(400 mil)

Part number

806

Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh

CAS before RAS refresh
RAS only refresh
Hidden refresh

NEe

II

~PD42S17800L,4217800L

j

'~

I~
I

'j,',

Pin Configurations (Marking Side)

1

,,~

28-pin Plastic TSOP (II) (400 mil)

28-pin Plastic SOJ (400 mil)

:1
,j

Vee

2

28
27

GND

1/01

1/08

1/01

10
2

28
27

1/02

3

26

1/07

1/02

3

26

1/07

1/03

4
5

25
24

1/06

1/03
1/04

25
24

1/06

1/05

4
5

23
22
21
20

CAS

WE

23
22
21

CAS

Vee

1/04
WE

RAS
NC
A10
AD
A1
A2
A3
Vee

6
7
8
9

1::1::

-a-a

CC
........

-1/1
"''''
"'.... ....

~g

1O)ren

",10)

10
11
12
13
14

6
7
8
9

A9
A8

RAS
NC
A10

19
18
17
16

A7
A6
A5
A4

AD
A1
A2
A3

10
11
12
13

15

GND

Vee

14

AD to A1D

Address Inputs

1/01 to 1/08

Data Inputs/Outputs

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

OE

1::1::

-a-a

cc

........

-1/1
"''''
....

~

....

;28
r-rmr-

m

GND
1/08

1

1/05

j

0

1,\
:.;,
;",
i ,~

OE

20

A9
A8

19
18
17
16

A7
A6
A5
A4

15

GND

I
I
I

I~

I~

I
II
I

)

11

I

807

,I'

~PD42S17800L,4217800L

NEe
Block Diagram

Clock
Generator

Vee 0 - - GNOO---

CAS before
RAS Counter
Memory
Cell
Array

1/01
to
1108

Row
Address
Buffer
AddressNole'
Column
Address
Buffer

Note 1.

Part number
#PD42S17800L, 4217800L

Row address

Column address

AO - A10

AO - A9

2. #PD42S17800L, 4217800L ... 2,048 x 1,024 x 8

808

NEe

~PD42S17800L,4217800L

II1

Ii

Input/Output Pin Functions
The tLPD42S17800L, 4217800L have input pins RAS, CAS, WE, OE, Address Note and
input/output pins 1/01 to 1/08.

II

:~

Pin name

InpuVOutput

Function

RAS
(Row address strobe)

Input

RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS
(Column address strobe)

Input

CAS activates data inpuVoutput circuit by latching column address and
selecting a digit line connected with the sense amplifier.

AOtoA10
(Address inputs)

Input

Address bus.
Input total 21-bit of address signal, upper bits and lower bits Note in sequence
(address multiplex method).
Therefore, one word is selected from 2,097,152-word by 8-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.

-

Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASe) and hold time (tRAH, teAH)
are specified for the activation of RAS and CAS.
WE
(Write enable)

Input

OE
(Output enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.

,

Therefore, read operation cannot be executed.

"

!

1/01 to 1108
(Data inputs/outputs)

InpuVOutput

8-bit data bus.
1/01 to 1/08 are used to inpuVoutput data.

I

Note

Part number
tLPD42S17800L,4217800L

Address inputs

Upper bits

Lower bits

AO - A10

11 bits

10 bits

809

NEe

~PD42S17800L,4217800L

Electrical Specifications
All voltages are referenced to GND.
After power up (Vcc  tRAD (MAX.)

and

tRCO ~ tACO (MAX.)

tAA(MAK)

tRAD

+ tM (MAX.)

tCAC (MAX.)

tACO

+ tCAC (MAX.)

tRCO

>

tACO (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference pOints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

Read Cycle
Parameter

Symbol

Access time from RAS

tRAC

Access time from CAS

tCAC

Access time from column address

IAA

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

-

60

70

ns

1

18

ns

1

30

-

35

ns

1

15

Unit Notes

Access time from OE

tOEA

-

15

-

18

ns

Column address lead time referenced to RAS

tRAL

30

35

tRCS

Read command hold time referenced to RAS

tRAH

Read command hold time referenced to CAS

tRCH

Output buffer turn-off delay time from OE

tOEZ

Output buffer turn-off delay time from CAS

tOFF

a
a
a
a
a

-

ns

Read command setup time

13
13

a
a
a
a
a

ns
ns

2

ns

2

15

ns

3

15

ns

3

Notes 1. For read cycles, access time is defined as follows:
Input conditions
tRAD (MAX.)

and

tRCO

tRAD> tRAD (MAX.)

and

tACO:::;; tRCO (MAX.)

tRAD

~

tACO> tACO (MAX.)

~

tRCO (MAX.)

Access time

Access time from RAS

tRAC (MAX.)

tRAC (MAX,)

tAA (MAX.)

tRAD

+ tAA (MAX.)

tCAC (MAX.)

tACO

+ tCAC (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference pOints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.

3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

814

NEe

~PD42S17800L,4217800L

Write Cycle
tRAC
Parameter

= 60 ns

tRAC

MIN.

MAX.

MIN.

tWCH

10

-

10

twp

10

-

10

WE lead time referenced to RAS

tRWl

20

WE lead time referenced to CAS

tCWL

15

WE setup time

twcs

0

OE hold time

tOEH

0

WE hold time referenced to CAS
WE pulse width

= 70 ns

Unit

Notes

-

ns

1

-

ns

1

Symbol

Data-in setup time

tDS

0

Data-in hold time

tDH

10

-

MAX.

0

-

15

-

20
15
0
0

ns
ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs :2! twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle

Parameter

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

Unit

Symbol

Note

MAX.

Read modify write cycle time

tRWC

158

-

180

RAS to WE delay time

tRWD

83

-

95

-

ns

1

CAS to WE delay time

tCWD

38

43

-

ns

1

Column address to WE delay time

tAWD

53

60

-

ns

1

-

ns

Note 1. If twcs:2! twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWO :2! tRWO (MIN.), tcwo :2! tcwo (MIN.), tAWO :2! tAWO (MIN.) and tcPWO :2! tcPWO (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
I't

met, the state of the data out is indeterminate.

I"

:1

Ii
I,

815

NEe

~PD42S17800L,4217800L

Fast Page Mode

Parameter

tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

Unit

Symbol

Fast page mode cycle time

tpe

40

-

45

-

Access time from CAS precharge

tAep

-

35

-

40

ns

RAS pulse width

tRASP

60

125,000

70

125,000

ns
ns

ns

tep

10

-

tRHCP

35

-

10

RAS hold time from CAS precharge

40

-

ns

Read modify write cycle time

tPRWC

83

-

90

-

ns

CAS precharge to WE delay time

tCPWD

58

-

65

-

ns

CAS precharge time

Note 1.

Note

MAX.

1

If twcs;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ;:: tRWD (MIN.), tCWD;:: tCWD (MIN.), tAWD ;:: tAWD (MIN.) and tCPWD ;:: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

Refresh Cycle

Parameter

tRAe = 70 ns

MIN.

MIN.

MAX.

5

Unit
MAX.

CAS setup time

tesR

5

-

CAS hold time (CAS before RAS refresh)

tCHR

10

RAS precharge CAS hold time

tRPe

5

-

RAS pulse width (CAS before RAS self refresh)

tRASS

100

-50

-

10
5

ns
ns

RAS precharge time (CAS before RAS self refresh)

tRPS

110

CAS hold time (CAS before RAS self refresh)

teHs

-50

WE setup time

tWSR

10

-

10

-

ns

WE hold time

tWHR

15

-

15

-

ns

IlPD42S17800L.

100
130

Note

ns

-

Note 1. This specification is applied only to the

816

tRAe = 60 ns
Symbol

IlS

1

ns

1

ns

1

NEe

~PD42S17800L,4217800L

Read Cycle

IRe
IRAS

RAS

IRP

V,HV,LlesH

CAS

V,HV,L-

Address

~~

V,HV,L-

100

leLZ

1/0 Vr:Jri-

VOL-

Hi-Z

Data oul

Hi-Z

817

NEe

~PD42S17800L,4217800L

Early Write Cycle
IRC
tRAS

VIH- ---""'\I

VILleSH

Address

V,HV,l-

1/0

V,HVll-

Remark OE: Don't care

818

_ _N_E_C
_ _ _ _ _ _ _ _ _ _ _ _ _ _....;,..J.1_P_D_42_S_1_78_0_0_L,_4_2_17_8_O_O_L_ _ _rii
'I1
'I

Late Write Cycle

l

Il
II

tRC

').

tAAS

VrHVIl-

CAS

VrHVIl-

Address

VrHVIl-

WE

V,HVIl-

tOEH

OE

VrHVrLtOED

819

NEe

~PD42S17800L,4217800L

Read Modify Write Cycle
tRWC

tAAS
V,HV,LtesH
tACO
CAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

tASH

tCWD

tOEH

tOEA

OE

V,HVIL-

teAe

I/O

V,HV,L-

~---------

tos

tOH
Data in

tOLZ

I/O

820

VOHVOL-

Hi-Z

Hi-Z
--------------------------------_.

NEe

~PD42S17800L,4217800L

Fast Page Mode Read Cycle
tRP

tRASP

RAS

V,H-

tRHCP

V,LtesH

V,H-

tpe

IRSH

-..,-++---'""

V,L-

Address

V,HV,L-

V,HV,L- L...'-'t....."j~~

V,H- ,("""",(,,""",""",~~""""f~~"'T",,,
V,L-

1/0

VOK- __________

.!il-.?_________ _

VOL-

Data oul

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

"

I'

:1

11

II

:~

821

II

NEe

~PD42S17800L,4217800L

Fast Page Mode Early Write Cycle

VIH-

V'L-

Address

V'HVIL-

V'HVIL-

I/O

V'HVIL-

Remarks 1. OE: Don't care

2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

822

NEe

I

~PD42S17800L,4217800L

Fast Page Mode Late Write Cycle

RAS

CAS

V,HVIl-

VIH-

VIl-

Address

WE

V,HV,L-

OE

V,HV,L-

I/O

Remark

In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

823

NEe

pPD42S17800L,4217800L

Fast Page Mode Read Modify Write Cycle

RAS

Address

VtHVIL-

V,HVIL-

1/0

VOHVOL-

1/0

V,HVIL-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

824

NEe

~PD42S17800L,4217800L

CAS Before RAS Self Refresh Cycle (Only for the tLPD42S17800L)

tRASS

tCSA

WE

~\\\\\\\\\\\\\\\\\\\\\\\

V,HVIL-

Remark Address, OE : Don't care

1/0: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh

CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh

When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh as follows just before and after setting CAS before RAS self refresh.

tLPD42S17800L : 2,048 times within a 32 ms interval
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh

When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh as follows just before and after setting CAS before RAS self refresh.

tLPD42S17800L : 2,048 times within a 32 ms interval
(3) If tAASH(MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tAAS < 100 tIS), CAS before

RAS refresh cycles will be executed one time.
If 10 tIS < tAAS < 100 tIS, RAS precharge time for CAS before RAS self refresh (tAPS) is applied.
And refresh cycles as follows should be met.

tLPD42S17800L : 2,048 times within a 128 ms interval
For details, please refer to How to use DRAM User's Manual.

825

~PD42S17800L,4217800L

NEe
CAS Before RAS Refresh Cycle
tRe
tRAS

V,HV,L-

Remark Address, OE: Don't care

1/0: Hi-Z

RAS Only Refresh Cycle

tRAS,

teRP

Address

V,HVIL-

Remark WE, OE: Don't care .1/0: Hi-Z

826

tRP

tRAS

"

NEe

ij

.uPD42S17800L, 4217800L

----~--------------------~--------------~I,~
Hidden Refresh Cycle (Read)

IRC

IRC

tRAS

IRA.

Ii

V,HVIL-

CAS

V,HV,L-

Address

V,HV,L-

WE

j
'i

I'

V,H-

I

Vll-

i

Ii!

OE

V,HV,L-

ICiZ

1/0 VOHVOL-

Hi-Z

Dala oul

Hi-Z

827

~PD42S17800L,4217800L

NEe
Hidden Refresh Cycle (Write)
IRC

IRC

IRAS

IRAS

V,HVIL-

V,HV,L-

Address

V,HVIL-

V,iiV,L- .....!.....:....l.~..l...~~.....:.~_ _-+_-I-~..L.J

1/0

V,HV,L- L...l1L..lL.,lj~....Y.....lL..lt..::L.)£.J/ L-_ _ _ _J

Remark OE: Don't care

828

'\j~....x..lt..::L..IL..,;IL..l"-lo!...ll....Y.....lL..lt..::L.lWlL..lL.,lj~....Y.....lL..lt...lL.l

NEe

~PD42S17800L,4217800L

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)

tAC
tRAS

tesR

teHR

i~

,
"

Remark Address, OE: Don't care

110: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
x 16-bit organization during test mode. Don't care about the input level of the CAS input AO.

(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.

(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to 16 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1": Normal write (all memory cells)
Output = "0": Abnormal write

(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.

(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

829

NEe

yPD42S17800L,4217800L

Package Drawings

28PIN PLASTIC TSOP{lI) (400 mil)

detail of lead end

-HI------+-----_+_

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A

18.63 MAX.
1.075 MAX.
1.27 (T.P.)

0.734 MAX.
0.043 MAX.
0.050 (T.P.)

0

0.42~8:89

0.017±0.003

E
F

0.HO.05
1.2 MAX.
0.97
11.76±0.2
10.16±0.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
0.400±0.004

B
C

G
H

0.8±0.2

0.031~8:88g

K

0.145~8:m

0.006±0.001

L

0.5±0.1

0.020~8:88~

M
N

0.21
0.10
30 + 70
-3"

0.009
0.004
30 + 70
-3"

P

S28G5-50-7JD3

830

NEe

I

~PD42S17800L,4217800L

28 PIN PLASTIC SOJ (400 mil)

-+;----------~-----------+-

u

0

14

P2SLE-400Al

NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

ITEM

MILLIMETERS

INCHES

B

lS.67~g:~5

o. 735~gg~~

C

10.16

0.400

D

11.lS±0.2

0.440~g:gg~

E

1.0S±0.15

0.043~:gg~

F

0.74

0.029

G

3.5±0.2

0.13S~gg~

H

2.545±0.2

0.100±0.00S

I

O.S MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

0.40±0.10

0.016~ggg~

N

0.12

0.005

P

9.40±0.20

0.370~ggg~

Q

0.10

0.004

T

R 0.S5

R 0.033

U

0.20~:6g

O.oos~g:gg~

i

831

NEe

~PD42S17800L,4217800L

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
,uPD42S17800L,4217800L.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
,uPD42S17800LG5, 4217800LG5: 28-pin plastic TSOP (n) (400 mil)
Soldering process

Soldering conditions

Symbol

Infrared ray rellow

Peak temperature of package surface: 235"C or lower,
Reflow time: 30 seconds or less (210 "C or higher),
Number of rellow processes: MAX. 2
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 "C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).

IR35-107-2

VPS

Peak temperature of package: 215"C or lower,
Reflow time: 40 seconds or less (200 "C or higher),
Number of reflow processes: MAX. 2
Exposure limit :7 daysNote

VP15-107-2

(10 hours pre-baking is required at 125 "C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25"C and relative humidity at 65 % or less.

Caution

832

Terminal temperature: 300"C or lower,
Time: 3 seconds or lower (Per side of the package).

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

NEe

~PD42S17800L,4217800L

JlPD42S17800LLE,4217800LLE: 28-pln plastic SOJ (400 mil)
Soldering process

Soldering conditions

Symbol

Infrared ray reflow

Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210'C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ·C afterwards)
cautions
1. After the first reflow proceas, cool the package down to room
temperature, then start the second reflow proceas.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).

IR35-207-2

VPS

Peak temperature of package: 215'C or lower.
Reflow time: 40 seconds or less (200 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ·C afterwards)
cautions
1. After the first reflow proceas, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).

VP15-207-2

Partial heating method

Terminal temperature: 300'C or lower,
Time: 3 seconds or less (Per side of the package).

Note

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

i
I

j.

833

NEe
[MEMO]

834

~PD42S17800L,4217800L

NEe

DATA SHEET
r------------------------------------------------------,

MOS INTEGRATED CIRCUIT

III,I

_ _ _ _ _ _ _ _ _ _IlP_D_42_S1_8_16_0L_,4_21_81_6_0L_!1

i

3.3 V OPERATION 16 M-BIT DYNAMIC R A M ,l'
_ _ _ _1_M_-W_O_R_D_B_Y_1_6-_B_IT_,_F_A_S_T_P_A_G_E_M_O_D_E_,_B_Y_T_E_R_EA_D_'_W_R_IT_E_M_O_D_E
____

It

Description

i'~

The JLPD42S18160L, 4218160L are 1,048,576 words by 16 bits CMOS dynamic RAMs. The fast page mode and
byte read/write mode capability realize high speed access and low power consum..£!!pn.
These differ in refresh cycle and the JLPD42S18160L can execute CAS before RAS self refresh.
These are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ.

!,'j

Ii'\

Features
•

1,048,576 words by 16 bits organization

•

Fast page mode

•

Fast access and cycle time

•

Single +3.3 V ± 0.3 V power supply

Power consumption

Access time

R/IN cycle time

Fast page mode

Active (MAX.)

(MAX.)

(MIN.)

cycle time (MIN.)

,uPD42S 18160L-A60, 421 8160 L-A60

540mW

60 ns

110 ns

40 ns

,uPD42S1 B160L-A70, 421 B160L-A70

504mW

70 ns

130 ns

45 ns

Part number

• The JLPD42S18160L can execute CAS before RAS self refresh

Refresh cycle

Refresh

Power consumption at standby
(MAX.)

,uPD42S18160L

1,024 cycles/12B ms

CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh

0.54mW
(CMOS level input)

,uPD4218160L

1,024 cycles/16 ms

CAS before RAS refresh,
RAS only refresh,
Hidden refresh

1.BmW
(CMOS level input)

Part number

The information in this document is subject to change without notice.
Document No. M1 t 084EJ5VODSU1

835

NEe

~PD42S18160L,4218160L

Ordering Information
Access time
Part number

836

(MAX.)

Package

jlPD42S18160LG5-ASO
jlPD42S18160LG5-A70

60 ns
70 ns

5().pin plastic TSOP (II)
(400 mil)

jlPD42S18160LLE-A60
!'PD42S18160LLE-A70

60 ns
70 ns

42-pin plastic SOJ
(400 mil)

!,PD4218160LG5-ASO
!,PD4218160LG5-A70

60 ns
70 ns

5().pin plastic TSOP (II)
(400 mil)

/lPD4218160LLE-A60
!,PD4218160LLE-A70

60 ns
70 ns

42-pin plastic SOJ .
(400 mil)

R.efresh
CAS before RAS self refresh
CA~ before RAS refresh
RAS only refresh
Hidden refresh

CAS before RAS refresh
RAS only refresh
Hid.den refresh

NEe

,~

.j

~PD42S18160L,4218160L

t~

'1,1;

t
'I,

i;*
ft~

Pin Configurations (Marking Side)

.~

!.,

42-pin Plastic SOJ (400 mil)

50-pin Plastic TSOP (II) (400 mil)

~~

f
"

50

Vee

GND

Vee

0

42
41

1/016

1/01

1/015

1/02

1/015

1/03

1/014

1/03

1/014

1/04

1/013

1104

1/013

Vee

GND

Vee

1::

GND

1/012

1105

C

1/012

I»

1/011

1::
"'II

C

1/06

.j>.

1/011

1/06

1/010

1/07

1/09

1/08

NC

NC
NC

"'II

!!!

1/08

NC

10
11

~

'"r0

C)

41
40

_111
.j>.

!!!

~

NC
NC

15
16

'"r0

NC
LCAS
UCAS

C)

111

WE

RAS
NC
NC
AD
A1
A2
A3
Vee

AD to A9

OE

32

25

29
28
27
26

A9
A8
A7
A6
A5

1/010
1/09

'"r-r-

'~

!i~
;,\

NC
LCAS
UCAS

.j>.

I»

.....

~

~

RAS
NC
NC
AD
A1
A2
A3
Vee

~

0

,!TI

WE

I»

,

.j>.

I»

1/07

,~

1/016

1/01
1/02

1/05

i'l

GND

OE

rr-

m

21

22

A9
A8
A7
A6
A5
A4
GND

A4

GND

Address Inputs

1/01 to 1/016: Data InputslOutputs
RAS

Row Address Strobe

UCAS

Column Address Strobe (upper)

LCAS

Column Address Strobe (lower)

WE

Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

NC

No Connection

837

NEe

~PD42S18160L,4218160L

Block Diagram
RAS
LCAS
UCAS
WE

Lower
Byte
Control

Clock Generator

Upper
Byte
Control

Vee

0---

GND 0---

CAS before
RAS Counter

Memory
Cell
Array

Note 1

Address
Column
Address
Buffer

1/09

Data
Input
Buffer

Notes 1.

Part number
pPD42S18160L,4218160L

Column address
AO·A9

2. ttPD42S18160L, 4218160L·" 1,024 x 1,024 x 16

838

I

j

~

_....;;.N....;....;;E;;;;....C-=--_ _ _ _ _ _ _ _ _ _ _ _ _--!.../l_PD_4_2_S_1_81_6_0......:L,_4_2_18_1_6_0_L_ _ _ _ '~

i.
\~

i.

I~

Input/Output Pin Functions

II

i

The IlPD42S18160L, 4218160L have input pins RAS, CAS Note 1, WE, OE, AddressNote 2
and input/output pins 1/01 to 11016.

I,~
.1.

Input!

Pin name

Function

Output
Input

RAS
(Row address
strobe)

i.

!

RAS activates the sense amplifier by latching a row address and selecting a corresponding
word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.

t
il

Ii

• CAS before RAS refresh
Input

CAS
(Column address
strobe)

line connected with the sense amplifier.

"

j

Input

AO to A9

II

CAS activates data input!output circuit by latching column address and selecting a digit

Address bus.
Input total 20-bit of address signal, upper bits and lower bits Noto 2 in sequence (address
multiplex method).

(Address input)

Therefore, one word is selected from l,048,576-word by 16-bit memory cell array.
In actual operation, latch row address by specifying row address and activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, lAse) and hold time (tRAH, teAH) are specified
for the activation of RAS and CAS.
WE
·(Write enable)

Input

OE

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

(Output enable)

Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/016

Input!

16-bit data bus.

(Data input!

Output

1/01 to 1/016 are used to input/output data.

output)

Notes 1. CAS means UCAS and LCAS.

2_

Part number
JlPD42S18160L,4218160L

Address inputs
AO - A9

Upper bits

Lower bits

10 bits

10 bits

839

NEe

~PD42S18160L,4218160L

Electrical Specifications
• CAS means UCAS and LCAS.
•

All voltages are referenced to GND.
After power up (Vcc ~ VCC(MIN.), wait more than 100 .us(RAS, CAS inactive) and then, execute eight CAS before

RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

Parameter

VT

-0.5 to +4.6

V

Supply voltage

Vee

-0.5 to +4.6

V

Output current

10

20

mA

Power dissipation

Po

1

W

Operating ambient temperature

TA

o to +70

·C

Storage temperature

TSI,

-55 to +125

·C

Caution

Symbol

Condition

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device Is not meant to be operated under conditions outside the limits
described In the operational section ofthlsspeclfication. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

3.0

3.3

3.6

V

High level input voltage

V,H

2.0

Vee +0.3

V

Low level input voltage

V,L

-0.3

+0.8

V

Operating ambient temperature

TA

0

70

·C

Parameter

Capacitance (TA = 25 ·C, f
Parameter
Input capacitance

Data input/output capacitance

840

Symbol

Condition

= 1 MHz)
MAX.

Unit

C"

Address

Test condition

5

pF

C'2

RAS. CAS, WE, OE

7

pF

C,IO

110

7

pF

Symbol

MIN.

TYP.

I

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,uPD42S18160L, 4218160L

---------------~----------,i
I,.

ij

[MEMO]

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841

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~PD42S18160~,4218160L

DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Operating current

Symbol
Icc1

Test condition
RAS, CAS cycling
tRC

Standby
current

pPD42S18160.L

1CC2

= tRC (MIN.), 10 = 0. rnA

RAS, CAS;?: V,H (MIN.), 10

MAX.

Unit

Notes

tRAC = 60. ns

MIN.

150.

rnA

1,2,3

= 70. ns

140.

tRAC

= 0. rnA

0..5

RAS, CAS;?: Vcc - 0..2 V, 10 = 0. rnA
pPD42181SDL

RAS only refresh current

Operating current

Iceo

Icc.

(Fast page mode)
CAS before RAS

Ices

refresh current

rnA

0..15

RAS, CAS;?: V,H (MIN.). 10 = 0. rnA

2.0.

RAS, CAS;?: Vcc - 0..2 V, 10 = 0. rnA

0..5

RAS cycling, CAS;?: V,H (MIN.)

tRAC = So. ns

150.

tRC = tRC (MIN.), 10 = 0. rnA

tRAC = 70. ns

140.

R7iS :s; V,L (MAX.), eAS cycling

tRAC = So. ns

90.

tpc - tpc (MIN.), 10 = 0. rnA

tRAC

= 70. ns

80.

rnA

1,2,3,4

rnA

1,2,5

rnA

1,2

180.

pA

1,2

150.

pA

2

RAS cycling

tRAC = So. ns

150.

tRC = tRC (MIN.), 10 = 0. rnA

tRAC

= 70. ns

140.

tRAS:S; 1 ps

CAS before RAS
long refresh current
(1,0.24 cycles I 128 ms,
only for the pPD42S181SDL)

Icee

CAS before RAS refresh:
tRC - 125.0. JlS
RAS, CAS:
Vcc - 0..2 V :s; V,H :s; V,H (MAX.)
0. V :s; V,L :s; 0..2 V
Standby:
RAS, CAS;?: Vcc - 0..2 V
Address: V,H or V,L
WE, OE: V,H
10 = 0. rnA

Self refresh current
(CAS before RAS self
refresh, on Iy for the
pPD42S1816DL)

Icc7

RAS, CAS:
tRASS - 5 ms
Vcc - 0..2 V :s; V,H :s; V,H (MAX.)
0. V :s; V,L :s; 0..2 V
10 = 0. rnA

Input leakage current

II (L)

V, = 0. to 3.S V
All other pins not under test = 0. V

-5

+5

pA

Output leakage current

10(L)

Vo = 0. to 3.S V
Output is disabled (Hi-Z)

-5

+5

pA

High level output voltage

VOH

10 --2.0. rnA

2.4

Low level output voltage

VOL

10

= +2.0. rnA

V

0..4

V

Notes 1, Icc1, Icc3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tpc).
2. Specified values are obtained with outputs unloaded.
3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS S
V,L (MAX.) and CAS 2: V,H (MIN.).
4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

842

·~

II
___N---.,;E=C-=-_ _ _ _ _ _ _ _ _ _ _ _ _--!..J.1_P_D_42_S_1_8_16_0_L,;....,4_2_1_8_16_0_L_ _ _.ll
,:1/

i'
! ~!

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.~

AC Characteristics (Recommended Operating Conditions unless otherwise noted)

~

i~

AC Characteristics Test Conditions

(1) Input timing specification

(2) Output timing specification

VIH(MIN.)=2.0V---------~-----'
,
,
,,
,

VOH (MIN.) = 2.0 V

VIL (MAX.) = 0.8 V .------------ '

VOL (MAX.)

I

~:

:

:

'

'

I

,

i..

IT =5 ns

------=f

}-

=0.8V.-----~\.._ _ _ _ _....J

II! :..
IT = 5 ns

(3) Output load condition
Vee
1,180n

1/0

--,._----+

100 pF

ClI

870n

Common to Read, Write, Read Modify Write Cycle

Parameter

tRAe = 60 ns

tRAe = 70 ns

MIN.

MAX.

MIN.

MAX.

130

10

-

ns

Symbol

Unit Notes

tRe

110

. RAS precharge time

tRP

40

CAS precharge time

tcPN

10

-

RAS pulse width

tRAS

60

10.000

70

10,000

ns

CAS pulse width

teAs

15

10,000

20

10,000

ns

18

Read I Write cycle time

50

ns
ns

1

hold time

tASH

15

teSH

60

-

70

-

ns

CAS hold time
RAS to CAS delay time

tACO

20

45

20

50

ns

2

RAS

ns

RAS to column address delay time

tRAD

1.5

30

15

35

ns

2

CAS to RAS precharge time

teRP

5

5

3

tASR

0

Row address hold time

tRAH

10

Column address setup time

tAse

0

Column address hold time

teAH

15

OE lead time referenced to RAS

tOES

0

CAS to data setup time

tel2

0

-

0

-

ns

Row address setup time

-

0
10
0
15
0

ns
ns
ns
ns
ns
ns

OE to data setup time

tOl2

0

tOED

13

-

15

-

ns

OE to data delay time
Masked byte write hold time referenced to RAS

tMRH

0

-

0

-

ns

IT

3

50

3

50

ns

tREF

-

128

-

128

ms

-

16

-

16

ms

Transition time (rise and fall)
Refresh time

)lPD42S18160L

)lPD4218160L

0

ns

843

NEe

pPD42S18160L,4218160L

Notes 1. In CAS before RASrefresh cycles, tRAS(MAX.) is 100 JIS.
If 10 J.lS < tRAS < 100 JIS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Inpul condilions

Access lime

Access lime from RAS

IRAD $ IRAD (MAX.) and IRCD $ IRCD (MAX.)

lRAC (MAX.)

IRAC (MAX.)

IRAD > IRAD (MAX.) and IRCD $ IRCD (MAX.)

1M (MAX.)

IRAD + IAA (MAX.)

IRCD> IRCD (MAX.)

lCAC (MAX.)

IRCD + ICAC (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

Read Cycle

Parameler
Access lime from RAS

lRAC = 60 ns

lRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

IRAC

-

60

-

70

ns

1

lCAC

15

-

20

ns

1
1

Symbol

Unil Noles

Access lime from column address

1M

-

30

-

35

ns

Access lime from OE

IOEA

-

15

-

20

ns

Column address lead lime referenced 10 RAS

IRA'

30

-

35

-

ns

Read command selup lime

IRCS

0

-

0

ns

ns

2

Access lime from CAS

Read command hold lime referenced 10 RAS

IRR"

0

-

0

Read command hold lime referenced 10 CAS

IRC"

0

-

0

-

Oulpul buffer lurn-off delay lime from OE

toEZ

0

13

0

15

ns

3

Oulpul buffer lurn-off delay lime from CAS

IOFF

0

13

0

15

ns

3

ns

2

Notes 1. For readcycles, access time is defined as follows:
Inpul condilions
IRAD $ lRAD (MAX.) and IRCD $ IRCD (MAX.)

Access lime
IRAC (MAX.)

Access lime from RAS
IRAC (MAX.)

lRAD> IRAD (MAX.) and IRCD $ IRCD (MAX.)

tAA(MAX.)

IRAD + IAA (MAX.)

IRCD > IRCD (MAX.)

ICAC (MAX.)

IRCD + lCAC (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

844

_ _....;;..N..;;;..;;;;E;;...;C=--_ _ _ _ _ _ _ _ _ _ _ _--=-Jl_P_D4_2_S_18_1_6_0L....:,..,_4_21_8_16_0_L_ _---l!'
11

Write Cycle

Parameter

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

II

Unit Notes

Symbol

WE hold time referenced to CAS

tWCH

10

-

10

-

ns

1

WE pulse width

twp

10

-

10

-

ns

1

WE lead time referenced to RAS

tRWL

20

-

20

-

ns

WE lead time referenced to CAS

tCWL

15

-

15

WE setup time

twcs

0

-

0

OE hold time

tOEH

0

-

0

Data-in setup time

tDS

0

-

0

-

ns

3

Data-in hold time

tDH

10

-

15

-

ns

3

-

-

J,I
I

,i

ns
ns

2

ns

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, twCH (MIN.) should
be met.
2. If twcs

~

twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire

cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
tRAC = 60 ns
Parameter

tRAC - 70 ns
Unit Notes

Symbol
MIN.

MAX.

MIN.

MAX.

-

180

-

ns

95

-

ns

1

40

-

ns

1

60

-

ns

1

Read modify write cycle time

tRWC

158

RAS to WE delay time

tRWD

83

CAS to WE delay time

tewD

38

Column address to WE delay time

tAWD

53

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and .the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

845

NEe

~PD42S18160L,4218160L

Fast Page Mode

Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

MAX.

Unit

Fast page mode cycle time

tpc

40

-

45

-

ns

Access time from CAS precharge

tACP

-

35

-

40

ns

tRASP

60

125,000

70

tcp

10

10

-

ns

RAS hold time from CAS precharge

tRHCP

35

-

40

-

ns

Read modify write cycle time

tPRWC

83

-

90

ns

CAS precharge to WE delay time

tCPWD

58

-

65

-

RAS pulse width
CAS precharge time

Note

125,000 ns

ns

1

Note 1. If twes ~ twes (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tAWD (MIN.), tCWD ~ tewD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
Refresh Cycle

Parameter

Symbol

tRAC

=60 ns

MIN.

MAX.

=70 ns
MAX.

-

CAS setup time

tCSR

5

-

5

CAS hoid time (CAS before RAS refresh)

tCHR

10

-

10

100

-50

-

15

-

RAS preeharge CAS hold time

tRPC

5

RAS pulse width (CAS before RAS self refresh)

tRASS

100

RAS precharge time (CAS before RAS self refresh)

tRPS

110

CAS hold time (CAS before RAS self refresh)

tcHS

-50

-

WE hold time

tWHR

15

-

Note 1. This specification is applied only to the IlPD42S181601.

846

tRAC
MIN.

5

130

Unit

Note

ns
ns
ns

JlS

1

ns

1

ns

1

ns

NEe

I

~PD42S18160L,4218160L

Read Cycle
tRC
tRP

tRAS

RAS

V,HV,LIcsH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L- ---l'--l>....l.~~f-.l'--l>....l....lo...~'--l>....l.+~Jo....l'--l>....l.~+-_ _ _ _+_--"'-t'r....L...L...L-L...,j............(,,_

toll
ICLl

UI/O
LlIO

V"",Hi-Z
VOL- .- - - - - - - - - - - - - - - - - -- - -- - -- - - - - - - - -- - -- - - - - - - - - - - - -- - - - - - - - - - - - --

Data out

Hi-Z

847

NEe

,uPD42S18160L, 4218160L

Upper Byte Read Cycle
lAC
IRP

IRAS

V,HV,LIcsH

IACo

IRSH

lCAS
UCAS

IMRH
LCAS

V,HV,LIRA'

Address

WE

V,HVIL-

V,HVIL- L-L...L..,j:-l:...L+..L..L..L...'-{
IDES

IDEA

V,H-

+ ..................-t....................t-'.................................f------+--"'-t"r-'..................-'-........~

VIL- --'..........................

lCAC

101.2
lru
U 1/0

VOHVQL-

Remark L 110: Hi-Z

848

Hi-Z

Dalaoul

NEe

pPD42S18160L,4218160L

Lower Byte Read Cycle
tRC
tRP

tRAS

V,HV,L-

UCAS

V,HV,L-

Address

WE

OE

V,HV,L- .....;t...J.....J.-l.....l..+.l...;!".".lt...J-+-l.....l...l...~t...J.....J.-l.....l... . .

+-____-+__.L...j+-t......t-I'-'..........L....L.tCAC
tOLZ

tCLZ

LI/O

VOHVOL-

Hi-Z

Data out

Hi -Z

Remark U 110: Hi-Z

849

NEe

~PD42S18160L,4218160L

Early Write Cycle
tAC
tRAS

RAS

V,HVILtesH

UCAS
LCAS

V,HVIL-

Address

V,HVIL-

WE

V,HVIL-

U 1/0
LIIO

V,HVIL-

Remark OE: Don't care

850

____N_E~C=_________________________~~P_D_4_2_S_18_1_60_L_,_42_1_8_16_O_L____~I

:;

Upper Byte Early Write Cycle

I

lAC
IAAS

RAS

lAP

V,HVIL-

II,

leSH

UCAS

V,HVIL-

LCAS

V,HVIL-

Address

V,HV,L-

'I,

WE

V,HV,L-

I)

UI/O

V,HV,L-

i

£.->........................................&.J/

1'----_ ..................................................................................................................

Remark OE, L 1/0: Don't care

851

NEe

~PD42S18160L,4218160L

Lower Byte Early Write Cycle
tAC
tRAS

Remark OE, U I/O: Don't care

852

tAP

NEe

,uPD42S18160L,4218160L

;\

--------------------------------~---------------------1
"

,:~

Late Write Cycle

1'1
,~

i~
tRC

:1.'

'~

tRAS

RAS

VIH-

VILtCSH
tACO

UCAS
LCAS

V,HVIL-

Address

V,HVIL-

WE

tASH

VIHVIL-

OE

tOED

U 1/0
L 1/0

V'HVIL-

"lJ:J) .......':! :"!:. ...... .

toH

Data in

:

I

I,

853

NEe

,uPD42S18160L,4218160L

Upper Byte Late Write Cycle
IRe
IRP

tRAS

RAS

VtH-

VIL-

lesH
IReD

tRSH

leAS
UCAS

LCAS

Address

WE

OE

V,HVIL-

IDH
U I/O

'\lW\ ....... ~!:.~ ...... .

VVIHIL-~

Remark L 1/0: Don't care

854

Dalain

NEe

il

,uPD42S18160L,4218160L

--------~~------------------------------------~------------~------------------'~

ii

~

Lower Byte Late Write Cycle

I

tRC
tRAS

tRP

RAS
tMRH

UCAS

,j

V,HVIL-

11

tCSH
tRCO

,1

tASH

I

I

LCAS

Address

WE

V,HV,L-

OE

V,HV,L- L-'-'~'-'...J..-L-L...L.J
tOH

L 1/0

"llJ)....... ~i:.~...... .

Data in

Remark U I/O: Don't care

855

NEe

pPD42S18160L,4218160L

Read Modify Write Cycle
tAWC

tRP

tAAS

RAS

V,HV,LtCSH
tRCO

UCAS
LCAS

V,HV,L-

Address

V,HVIL-

WE

V,HV,L-

OE

V,HV,L-

UI/O
Lila

UI/O
LIIO

856

tRSH
tCAS

~ .................. .

VOH- •••••••••••••••••••• ~!:.~
VOL-

................ .

Hi ·Z

NEe

pPD42S18160L,4218160L

I

Upper Byte Read Modify Write Cycle
tRWC

tAP

tRAS

RAS
tCSH
tRCD

tASH

teAs

UCAS

LCAS

V,HV,L-

Address

V,HVIL-

WE

V,HV,L-

twp

tOEH

OE

U 1/0

U 1/0

VIHVIL-

VOH-

VOL-

~ ................. ..

Z
.. - .............. -- ...... --- ......Hi
-_ -..............
-_ ........ -_ .... _..

Hi -Z

Remark In this cycle, the input data to Lower 1/0 is ineffective. The data out of that remains Hi-Z.

I~
I

l~

857

I

NEe

~PD42S18160L,4218160L

Lower Byte Read Modify Write Cycle
tRWC

tRP

tRAS

RAS

UCAS

V,HV,LtCSH
tRCD

tRSH

LCAS

Address

V,HV,L-

twp

WE

V,HVIL-

tOEH

OE

V,HV,L-

~ .................. .

Lila

Lila

VDH-

VOL-

Z
------_ .. _---- -- .. --- .. Hi·
--- .......... -_ .. _-------_ ..

Hi-Z

Remark In this cycle, the input data to Upper 1/0 is ineffective. The data out of that remains Hi-Z.

858

.uPD42S18160L,4218160L
Ii
____NEe
-=~------------------------~------~----------~I.~
I

II

Fast Page Mode Read Cycle

!i

·,
II

tRASP
tRHCP

RAS
tCSH

UCAS
LCAS

Address

WE

tRSH

V,HVIl-

VIH-

VIl-

V,HVIl-

OE

UI/O
L 1/0

Remark

VOHVOl-

-Z
..... - ...... _...... --Hi_............
-_ ........ ..

In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

I1

NEe

~PD42S18160L,4218160L

Fast Page Mode Byte Read Cycle
tRP
I~

RASP

RAS

UCAS

LCAS

V,HVIL-

V,HV,L-

V,HV,L-

tRHCP

.

~

.

tesH
tRCO

teAS

tpe

V
~

~

~

teAS

~

V,HV,L-

V,HV,L-

~~ m> m
~

Row

tRAL

~~

Col.

tRCH

IIIII/}

Col.

..-rtJ

tRes

\/

1'1\/

tAep
V,HV,L-

tOlZ
~~

\\\ \\\\\\\\~

JQ )()(

tRCH

-h'" +-r+

r-

~

~

~

Col.

tOEA

OE

'-

J

tRes

WE

'---

I
tMRH

tRAD

Address

~

teAs

~

--.I

'-

tRSH

I+- 9 ttRRH

~

~
tAep

--"\ ?
~

/ / / / / /,

tRAC

I

~EZ
tOFF

tM

teAe

UI/O

VOHVOL-

~~

Hi-Z
--------------------------------

>

Data out ~

''-T'

tAA
teAc

~

Hi-Z

--- --- ----------~>

tAA

LIIO

-Z
-_Hi.. _-_
...

tOEZ

~
Hi-Z

Data out

~

tCAC

VOHVOL-

~

~

~

----------------------------------------------------<

,.----,
Hi-Z
Data out ~-- ----- - ----- ----- - ------- __ e.
~

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

860

~-=c:

~PD42S18160L,4218160L

--~="';=-----------------!---------:~---------i.~
'~'

Fast Page Mode Early Write Cycle

- - VrHRAS VIL-

UCAS VrHLCAS VIL-

Address VrHVrL-

WE VrHVll-

U I/O VrHL I/O VIL-

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle,

II
!1
"

I

1
J~
..

::)

,1
!~

i :~

11
!~

!1
iF

iI
,1

861

'I

!4

NEe

~PD42S18160L,4218160L

Fast Page Mode Byte Early Write Cycle
tRASP
tRHCP

V,H-

Address V,L-

U 1/0 V,HV,L-

L 1/0 V,HVIL-

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

862

____N__
E_c:
____________________________
Fas. Page Mode Late W,'te CY"e

....

~~_PD_4_2_S_1_81_6_0_L,_4_2_1_81_6_0_L____~1
I,

'"oe

RAS V,HVIl-

UCAS V,HLCAS V,l-

Address V,HV,l-

WE V,HV,l-

OE V,HV,l-

U I/O
L I/O

Remark

In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

Ii

!

1'1
I

I,':1

~
I

i

!

i

863

I

I

NEe

flPD42S18160L, 4218160L

Fast Page Mode Byte Late Write Cycle
tRASP
tAHCP

tpe

tesH
teAs

tASH

teAs

Address

UI/O

L 110 V,H- ______ tlj;_?; ________ _
VIL-

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

864

NEe

~PD42S18160L,4218160L

Fast Page Mode Read Modify Write Cycle

RAS V,H-

V,L-

UCAS
LCAS

V,HV,L-

Address V,H-

V,L-

WE

V,HV,L-

OE V,H-

V,L-

U 1/0 VotlL 1/0 VOl.-

U 1/0 V,HL 1/0 V,L-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

865

NEe

,uPD42S18160L,4218160L

Fast Page Mode Byte Read Modify Write Cycle
tRP

tRASP

teAs

teAS

V,HVIL-

LeAS

V,HVILtRAl

Address

WE

V,HVIL-

V,HVIL- .......'--'-'-...,.......J

Hi-Z

U 1/0 VOHVOl-

L I/O VOHVOl-

V,HU 1/0 VIL-

L 1/0 V,HVIl-

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

866

NEe

~PD42S18160L,4218160L

CAS Before RAS Self Refresh Cycle (Only for the .uPD42S18160L)

RAS

V'HVIL-

UCAS
LCAS

V'HVIL-

Remark Address, WE, OE: Don't care

L I/O, U I/O: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh as follows just before and after setting CAS before RAS self refresh .

.uPD42S 18160L: 1,024 times within a 16 ms interval
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh as follows just before and after setting CAS before RAS self refresh .

.uPD42S 18160L: 1,024 times within a 16 ms interval
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS seif refresh cycles (tRAS < 100 .us), CAS befor,e

RAS refresh cycles will be executed one time.
If 10

.us < tRAS < 100 .us, RAS precharge time for CAS before RAS self refresh (tRPS) is applied,

And refresh cycles as follows should be met.

.uPD42S18160L: 1,024 times within a 128 ms interval
For details, please refer to How to use DRAM User's Manual.

867

NEe

.uPD42S18160L,4218160L

CAS Before RAS Refresh Cycle

RAS

V,HVIL-

UCAS
LCAS

V,HV,L-

Remark Address, WE, OE: Don't care

L 1/0, U 1/0: Hi-Z

RAS Only Refresh Cycle
tRe
tRAS
RAS

tR.

V,HV,L-

teR.
UCAS
LCAS

V,HV,L-

Address

V,HV,L-

Remark WE, OE: Don't care.

868

L 1/0, U 1/0: Hi-Z

tRAS

I'

I

pPD42S18160L,4218160L

NEe
Hidden Refresh Cycle (Read)

IRC

IRC
IR. .

IR. .

RAS

V,HV,L-

IRSH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

ICHR

tCPN

V,HV,LlRAC
AA

leAC
lOll
CLl

U 1/0

L 1/0

VOH-

VOL-

•••••••••••••••• .I:I~:.~ ....................... .

Hi-Z
.............................................

869

I

NEe

.uPD42S18160L,4218160L

Hidden Refresh Cycle (Write)
IRC

IRC
tRAS

IRAS

RAS

UCAS
LCAS

Address

V,HVIL-

twcs

WE

V,HV,Llos

U 1/0

LlIO

V,HV,L-

Remark OE:

870

twCH

Don't care

IOH

NEe

~PD42S18160L,4218160L

Package Drawings

50PIN PLASTIC TSOP(II) (400 mil)

detail of lead end

-+-If---------+-----_+_

H

~~

~

J}

L

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

INCHES

21.17 MAX.
1.0 MAX.
0.8 (T.P.)

0.834 MAX.
0.040 MAX ..
0.031 (T.P.)

0

0.32~g:g~

0.013±0.003

E
F

0.aO.05
1.2 MAX.
0.97
11.76±0.2
10.16±O.1

0.004±0.002
0.048 MAX.
0.038
0.463±0.008
O.400±O.OO4

0.8±0.2

0.031~g:ggg

B
C

G
H

K

M
N

P

0.145~g:m

0.006±0.001

0.5±0.1

0.020~g:ggt

0.13
0.10
30 _3°
+ 70

0.005
0.004
3 0 _3°
+ 70

r

SS0G5-80-7JF4

871

NEe

~PD42S18160L,4218160L

42 PIN PLASTIC SOJ (400 mil)

B

-++-------------~--------------+-

u

0

P42LE-400A
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

872

ITEM

MILLIMETERS

INCHES

B

27.56~gj5

1.0S5~gg?~

C

10.16

OAOO

D

11.1S±0.2

OA40±0.00S

E

1.0S±0.15

0.043~ggg~

F

0.74

0.029

G

3.5±0.2

0.13S±0.00S

H

2.545±0.2

0.100±0.00S

I

O.S MIN.

0.031 MIN.

J

2.6

0.102

K

1.27 (T.P.)

0.050 (T.P.)

M

OAO±0.10

0016~ggg~

N

0.12

0.005

P

9.4±0.20

0.370±0.00S

Q

0.10

0.004

T

R 0.S5

R 0.033

U

0.20~g6g

000s~ggg1

NEe

pPD42S18160L,4218160L

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met when soldering JLPD42S18160L.
4218160L.
For more details. refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).
Please consult with our sales offices in case other soldering process is used. or in case the soldering is done
under different conditions.

Types of Surface Mount Device
JLPD42S18160LG5,4218160LG5: 50-pin plastic TSOP (II) (400 mil)
Soldering
process

Soldering conditions
Peak temperature of package surface: 235'C or lower.
Reflow time: 30 seconds or less (210 ·C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNoto

Infrared ray
reflow

Symbol
IR35-107-2

(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room temperature, then stl\rt the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).
Peak temperature of package: 215'C or lower.
Reflow time: 40 seconds or less (200 ·C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNoto

VPS

VP15-107-2

(10 hours pre-baking is required at 125'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).
Partial heating
method

Terminal temperature: 300'C or lower.
Time: 3 seconds or less (Per side of the package).

-

Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25
Caution

'c and relative humidity at 65 % or less.

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

873

NEe

~PD42S18160L,4218160L

IlPD42S18160LLE,4218160LLE: 42-pin plastic SOJ (400 mil)
Soldering

Soldering conditions

process

Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

Infrared ray
reflow

Symbol
IR35-207-2

(20 hours pre-baking is required at 125 ·C afterwards)
Cautions

1. After the first rellow process, cool the package down to room temperature, then start the second reflow process.

2. After the first rellow process, do not use water to remove residuaillux
(water can be used In the second process).

Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),

VPS

VP15-207-2

Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ·C afterwards)
Cautions

1. After the first rellow process, cool the package down to room temperature, then start the second rellow process.

2. Alter the first rellow process, do not use water to remove residuaillux
(water can be used In the second process).

Partial heating
method

Terminal temperature: 300'C or lower,
Time: 3 seconds or less (Per side of the package).

-

Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.
Caution Do not apply more than one soldering method at anyone time, except for "Partial heating

method".

874

Ij
il
:1

II

Ij

II

"

Fast Page Mode
4M Dynamic RAM
[5.0V

+ 10%]

I

I

875

..

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

,uPD424400
4 M-BIT DYNAMIC RAM
1 M-WORD BY 4-BIT, FAST PAGE MODE

Description
The }LPD424400 is a 1,048,576 words by 4 bits CMOS dynamic RAM. The fast page mode capability
realizes high speed access and low power consumption.
The device is packaged in 26-pin plastic TSOP (TI) and 26-pin plastic SOJ.

Features
• 1,048,576 words by 4 bits organization

•

Single +5.0 V ± 10 % power supply

• Fast page mode
• Fast access and cycle time

Power consumption

RJW cycle time

Fast page mode

(MIN.)

cycle time (MIN.)

60ns

120 ns

40 ns

70 ns

140ns

45 ns

BO ns

160 ns

50 ns

Active (MAX.)

Access time
(MAX.)

,uPD424400-60

495mW

,uPD424400-70

440mW

,uPD424400-BO

440mW

Part number

Part number
,uPD424400

Refresh cycle
1,024 cycles/16 ms

Refresh

Power consumption at standby
(MAX.)

CAS before RAS refrEl'Sh,
RAS only refresh,
Hidden refresh

5.5mW
(CMOS level input)

• Multiplexed address inputs ...... Rowaddress: AO - A9, Column address: AO - A9

The Information in this document Is subject to change without notice.
Document No. M11160EJ7VODSU1

877

NEe

yPD424400

Ordering Information

Part number

878

Access time
(MAX.)

JlPD424400GS-60
,uPD424400GS-70
I'PD424400GS-BO

60 ns
70 ns
BO ns

,uPD424400LA-60
,uPD424400LA-70
I'PD424400LA-BO

60 ns
70 ns
BO ns

Package
26-pin plastic TSOP
(300 mil)

Refresh

un

26-pin plastic SOJ
(300 mil)

CAS before RAS refresh
RAS only refresh
Hidden refresh

Address Inputs
AD to A9
1/01 to 1104 : Data InputslOutputs
RAS

Row Address Strobe

CAS
WE

Column Address Strobe
Write Enable

OE

Output Enable

Vee

Power Supply

GND

Ground

!-

879

NEe

,uPD424400

Block Diagram

RAS 0----1
CAS 0---1

Clock
Generator

WE

Vee

0-----

GND 0-----

CAS beiore
RAS Counter

Q;

u

8.,

0

~

a:

Row
Address
Buffer
XO - X9

AO
to
A9
Column
Address
Buffer

880

'

tRAD (MAX.)

and

tRCo

$

tRCD (MAX.)

tAA (MAX.)

tRAD

+

teAc (MAX.)

tRCO

+ teAc (MAX.)

tRCo> tRCo (MAX.)

tAA (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.

Read Cycle
tRAC = 60 ns

tRAC = 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

60

-

70

-

80

ns

1

15

-

20

ns

1

35

-

20

30

40

ns

1

20

-

20

ns

-

40

-

ns

Symbol

Parameter

Unit Notes

Access time from RAS

tRAC

Access time from CAS

tCAC

Access time from column address

tAA

-

tOEA

-

15

-

tRAL

30

-

35

Access time from OE
Column address lead time
referenced to RAS
Read command setup time

tRCS

0

-

0

-

0

tRRH

0

-

0

-

10

-

ns

Read command hold time
referenced to RAS

ns

2

tRCH

0

-

0

-

0

-

ns

2

Output buffer turn-off delay
time from OE

tOEl

0

15

0

15

0

20

ns

3

Output buffer turn-off delay
time from CAS

to"

0

15

0

15

0

20

ns

3

Read command hold time
referenced to CAS

Notes 1. For read cycles, access time is defined as follows:
Input conditions
and

:s:

Access time

Access time from RAS

tRAC (MAX.)

tRAG (MAX.)

tRAD> tRAD (MAX.) and tRCD " tRCD IMAX.)

tAA (MAX.)

tRAD

+ tAA (MAX,J

tACO> tRCD (MAX.)

teAc (MAX.)

tACO

+ teAc (MAX.)

tRAD:S: tRAD (MAX.)

tACO

tRCD (MAX.)

tRAD (MAX.) and tRCD(MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, IAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD;:: tRAD (MAX.) and tRCD ;:: tRCD (MAX.) will not cause
any operation problems.
2. Either tACH (MIN.) or tRRH (MIN.) should be met in read cycles.

3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

886

NEe

,uPD424400

Write Cycle
Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

15

ns

1

ns

1

20

-

-

ns

0

tWCH

15

-

15

WE pulse width

twp

10

10

WE lead time referenced to RAS

tRwL

15

WE lead time referenced to CAS

tCWL

15

WE setup time

twcs

0

-

0

-

OE hold time

tOEH

0

-

0

-

-

0

-

0

15

-

15

WE hold time referenced to CAS

Data-in setup time

tDS

0

Data-in hold time

tDH

15

20
15

15

15
0

-

Unit Notes

ns

ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.

2. If twcs ;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.

3. tos (MIN.) and tOH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.

Read Modify Write Cycle
Parameter

Symbol

tRAC = 60 ns

tRAC = 70 ns

MIN.

MAX.

MIN.

tRAC = 80 ns

MAX.

MIN.

MAX.

Unit

Note

Read modify write cycle time

tRWC

150

-

175

-

210

tRWD

80

90

ns

1

tCWD

35

40

-

105

CAS to WE delay time

-

-

ns

RAS to WE delay time

45

-

ns

1

Column address to WE delay time

tAWD

50

-

55

-

65

-

ns

1

Note 1. If twcs;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWO ;:: tRWD (MIN.), tcwo ;:: tcwo (MIN.), tAWO ;:: tAWO (MIN.) and tcPWO;:: tcPWO (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

I

'11

887

I

NEe

.uPD424400

Fast Page Mode
Parameter
Fast page mode cycle time
Access time from CAS precharge
RAS pulse width
CAS precharge time

tRAC = 60 ns

tRAC = 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

Symbol

Unit

tpc

40

-

45

-

50

-

tACP

-

35

-

40

-

45

ns

tRASP

60

125,000

70

125,000

80

125,000

ns

tcp

10

10

-

10

-

ns

RAS hold time from CAS precharge

tRHCP

35

Read modify write cycle time

tPRWC

80

CAS precharge to WE delay time

tCPWD

55

-

40
85
60

45
95
70

Note

MAX.

-

ns

ns
ns
ns

1

Note 1, If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tCWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and !cPWD ~ !cPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

Refresh Cycle

Parameter

888

tRAC = 60 ns

tRAC = 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MIN.

MAX.

10

-

10

-

ns

10

-

15

ns

Unit

Symbol
MAX.

RAS precharge CAS hold time

tRPe

10

-

10

-

10

-

WE setup time

tWSR

0

-

0

-

10

-

ns

WE hold time

tWHR

10

-

10

-

15

-

ns

CAS setup time

tCSR

10

CAS hold time (CAS before RAS refresh)

tCHR

10

ns

Note

NEe

,uPD424400

Read Cycle
tRe
tRP

tRAS

Address

WE

tou
teu

1/0

VOHVOl-

Hi-Z

Data out

Hi-Z

889

NEe

,uPD424400

Early Write Cycle
tRe
tRAS

tesH

V,HV,L-

Address

VIH-

V,L-

V,ii-

110

V,HV,L-

Remark OE: Don't care

890

...."T""'\

,\"""'''''....,~""T"'T

VIL-

NEe

.uPD424400

Late Write Cycle
tRC
tRAS

RAS

V,HVIL-

CAS

WE

I/O

891

NEe

,uPD424400

Read Modify Write Cycle
tRWC

tRAS

RAS

V,HVILtCSH

tRCO

CAS

V,HVIL-

Address

V,HVIL-

tRSH

tAwD

tcwo

WE

V,HVIL-

OE

V,HVIL-

1/0

V,HVIL-

tOEH

tOEA

tCAC

~---------

-

tos

tOH

Data in
tmz

I/O

892

VOHVOL-

Hi-Z

Hi-Z

NEe

,uPD424400

Fast Page Mode Read Cycle
tAP

tRASP

-----,

tRHCP

tpe

tCSH

CAS

V,HVIL-

J

~

WE

~\

VIL-

~

~

~

A

I~

Col.

:)<:m

r- ~
/////1

m>

)

Col.

tJ

tRCH

II

Remark

tRRH

I

~\\\\
tOES

tACP

~EZ

tAA

~~r~
Data out

:}

1\/

~E Z

----------~!-!---------- ~

XIX

-....

r\ff r\

tAA

~r~

Col.

tRCH

\/

\\\\\\\\\\!{f
VOHVOL-

Y / '--

tAyS

tACH

II

tRAC

I/O

tCPN

I

~~

~~

tAep

OE

teAs

~

tRAL

Row

V,H-

teAs

~
tASR

Address

~
,----.,

teAs

tRCD

'-

tRSH

)-Ijt~ ~

~
~LZ

tM

~~~

Data out

~ljt~

J

11/1111
IA. .
~

Data out

tOFF

Hi-Z
)--------_.

In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

893

NEe

,uPD424400

Fast Page Mode Early Write Cycle

VIH-

VIL-

Address

I/O

V,HVIL-

V,tiV,L-

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

894

NEe

,uPD424400

Fast Page Mode Late Write Cycle
tAP

tAASP
tRHCP

tpe

tRSH

V,HVIL-

Address

V,HVIL-

WE

V,HV,L-

OE

V,HVIL-

1/0

V,HVIL-

Hi-Z
._------------.--

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

895

II

NEe

jiPD424400

Fast Page Mode Read Modify Write Cycle

Address

WE

OE

I/O

I/O

V,HVIL-

VOH-

VOL-

VrHVll-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

896

NEe

.uPD424400
Ii
iii

[MEMO]

IJ

Ii

I

i

I~

I

<\-;

I.:~

,I.

11
897

II

NEe

,uPD424400

CAS Before RAS Refresh Cycle
tRAS

tCSA

tCHR

Remark Address, OE: Don't care

I/O: Hi-Z

RAS Only Refresh Cycle
tRC
tRAS

teRP

Address

Remark WE, OE: Don't care

898

110: Hi-Z

tRP

tRAS

NEe

,uPD424400
I

Hidden Refresh Cycle (Read)

il

IRC

IRC

lRAS

tRAS

i
~i
,,'~

V,HV,L-

"

I
IRCD

CAS

IRSH

ICHR

ICPN

V,HV,L-

!,

II

!l
"

Address

"

V,HV,L-

WE

ICLl

1/0 VOl+VOL-

Hi-Z

Dataoul

Hi-Z

II:
:'1~

I

I
899

I

NEe

,uPD424400

Hidden Refresh Cycle (Write)
IRC

lRAS

V,HVIL-

-----.1

V,tiV,L-

Address

V,HVIL-

V,tiV,L- -->............................>....;..............,..---t-+--'t-J.....J

1/0

V,tiV,L- L..lt...lj~....K.....K...lL..lL..,;¥-J~

Remark OE: Don't care

900

" -_ _ _ _J<

IRC
IRAS

NEe

,uPD424400

Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)

Remark Address,

OE:

Don't care

I/O: Hi-Z

Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
x a-bit organization during test mode. Don't care about the input level of the CAS input AO.

(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.

(2) Write/read operation
When either a "0" or a "1" is written to the input pin in test mode, this data is written to a bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = "1": Normal write (all memory cells)
Output

= "0":

Abnormal write

(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh's internal
counter.

(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.

901

.uPD424400

NEe
Package Drawings

26 PIN PLASTIC TSOP (II) (300 mil)
14
detail of lead end

-+-r--------------+----------------~

J4l

~I

w

NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of
its true position (T.P.) at maximum material condition.

a.

ITEM

MILLIMETERS

INCHES

A
B

17.36 MAX.
1.06 MAX.
1.27 (T.P.)

0.684 MAX.
0.042 MAX.
O.OSO (T.P.)

C
0

0.42~8:89

0.017±0.003

E
F
G
H

O.ltO.OS
1.2 MAX.
1.0
9.22±0.2
7.62±0.1

0.004±0.002
0.048 MAX.
0.039
0.363±0.008
0.300±0.004

0.8±0.2

0.031~8:88~

K

0.14S~8:8~~

0.006±0.001

L

O.S±O.l

0.020~8:88~

M
N

0.21
0.10

P

3 0 _3°
+70

0.009
0.004
3 0 _3°
+70
S28G3-SCl-9JD

902

NEe

.uPD424400

26 PIN PLASTIC SOJ (300 mil)
B

26

14

~~---------------+------------------r

Q

0

o
13

F

E

::c

NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

17.4:8:~5

0.685:8:8?g

C

7.57

0.298

0

8.47±0.2

0.333:8:883

E

1.08±0.15

0.043:8:88~

F

0.6
3.5±0.2

0.024
0.138±0.0·08

H

2.4±0.2

0.094:8:88ij
0.031 MIN.
0.102
0.050(T.P.)

G

K

0.8 MIN.
2.6
1.27(T.P.)

M

0,40±0.10

0.016:8:88~

N
P
T

0.12
6.73±0.20
0.15.
R 0.85

0.005
0.265±0.OQ8
0.006
RO.033

U

0.20:8:6R

0.008:8:88~

Q

P26LA-50A-2

903

NEe

,uPD424400

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
ILPD424400.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(I EI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.

Types of Surface Mount Device
ILPD424400GS: 26-pin plastic TSOP (II) (300 mil)
Soldering process
Infrared ray reflow

Soldering conditions
Peak temperature of package surface: 235 'c or lower,
Reflow time: 30 seconds or less (210 'c or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNoto

Symbol
IR35-107-2

(10 hours pre-baking is required at 125 'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
VPS

Peak temperature of package: 215 'C or lower,
Reflow time: 40 seconds or less (200 'c or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNoto

VP15-107-2

(10 hours pre-baking is required at 125 'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

Terminal temperature: 300 'c or lower,
Time: 3 seconds or lower (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 'C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating

method".

904

NEe

'i

,uPD424400

iii

--------~~----------------------------------------------------~------------------~ii

!~

;~;

~

,uPD424400LA: 26-pin plastic SOJ (300 mil)
Soldering process
Infrared ray reflow

i

Soldering conditions
Peak temperature of package surface: 235 'C or lower.
Reflow time: 30 seconds or less (210 'c or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

I.~

Symbol

i~

IR35-207-2

(20 hours pre-baking is required at 125 'c afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Peak temperature of package: 215 'c or lower.
Reflow time: 40 seconds or less (200 'C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

VPS

VPI5-207-2

(20 hours pre-baking is required at 125 'C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used In the second process).
Partial heating method

Note

Terminal temperature: 300 'c or lower.
Time: . 3 seconds or less (Per side of the package).

---

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25·C and relative humidity at 65 % or less.

Caution

Do not apply more than one soldering method at anyone time, except for "Partial heating
method".

905

NEe
[MEMO]

906

,uPD424400

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

II

iJ

_ _ _ _------.:..Jl_P_D_42_S_4_80_0_,_42_4_8_00_11

4 M-BIT DYNAMIC RAM
it
512 K-WORD BY 8-BIT, FAST PAGE M O D E !'.

_ _ _ _ _ _ _ _ _ il

I~

11

Description

i!

The ,uPD42S4800, 424800 are 524,288 words by 8 bits CMOS dynamic RAMs. The fast page mode capability
realize high speed access and low power consumption.
Besides, the ,uPD42S4800 can execute CAS before RAS self refresh.
These are packaged in 28-pin plastic TSOP(II) and 28-pin plastic SOJ.

Features
524,288 words by 8 bits organization

•

Single +5.0 V ± 10 % power supply

Fast page mode
Fast access and cycle time

Part number

pPD42S4800-60, 424800-60

Power
consumption
Active (MAX.)
577.5 mW

pPD42S4800-70, 424800-70

550.0 mW

pPD42S4800-80, 424800-80
pPD42S4800-10, 424800-10

(MAX.)

R/W cycle time
(MIN.)

Fast page mode
cycle time
(MIN.)

60 ns

110 ns

40 ns

Access time

70 ns

130 ns

45 ns

522.5 mW

80 ns

150 ns

50 ns

440.0 mW

100 ns

180 ns

60 ns

!'
I

The ,uPD42S4800 can execute CAS before RAS self refresh

Part number
pPD42S4800

Refresh cycle
1,024 cycles/128 ms

Refresh
CAS before RAS self refresh,

CAS before FiAS

refresh,

Power consumption
at standby (MAX.)
0.825 mW
(CMOS level input)

RAS only refresh, Hidden refresh
pPD424800

1,024 cycles/16 ms

CAS before RAS refresh,
RAS only refresh,

111

5.5 mW
(CMOS level input)

I'

Hidden refresh

• Multiplexed address inputs ...... Row address: AO-A9, Column address: AO-A8

I
I

I~

Ij
"

Iii
I

II

J

The Information in this document Is subject to change without notice.
Oocument No. M11085EJ7VODSU1

907

NEe

yPD42S4800,424800

Ordering Information
Part number
,uPD42S4800G5-60
,uPD42S4800G5-70

908

Access time
(MAX.)
60 ns

28-pin plastic TSOP (II)

70 ns

(400 mil)

80 ns

,uPD42S4800G5-10

100 ns

,uPD42S4800LE-60

60 ns

28-pin plastic SOJ

,uPD42S4800LE-70

70 ns

(400 mil)

80 ns

,uPD42S4800LE-10

100 ns

,uPD424800G5-60·

60 ns

28-pin plastic TSOP (II)

,uPD424800G5-70

70 ns

(400 mil)

,uPD424800G5-80

80 ns

,uPD424800G5-10

100 ns

jlPD424800LE-60

60 ns

28-pin plastic SOJ

,uPD424800LE-70

70 ns

(400 mil)

80 ns
100 ns

CAS before RAS refresh

Hidden refresh

,uPD42S4800LE-80

,uPD424800LE-10

CAS before RAS self refresh

RAS only refresh

,uPD42S4800G5-80

,uPD424800LE-80

Refresh

Package

~ before

1tl'\S' refresh

RAS only refresh
Hidden refresh

,

NEe

I

yPD42S4800,424800

Pin Configurations (Marking Side)

il

28-pln Plastic TSOP (n) (400 mil)

28

28-pln Plastic SOJ (400 mil)

GND
1/08

1/01

1/08

1/02

1/07

1/02

1/07

1/03

NC
WE

Vee

1/03

1/06

1/05

1/04

1/05

II

CAS

NC

OE

WE

'"

14

15

NC
A8
A7
A6
A5
A4
GND

AD to A9

Address Inputs

1/01 to 1/08

RAS

Data Inputs/Outputs
Row Address Strobe

CAS

Column Address Strobe

WE

Write Enable

OE

Output Enable

Vee

GND

Power Supply
Ground

NC

No Connection

1::1::

Vee

CAS

"11"11

II

RAS
A9
AO
A1
A2
A3

OE

mrm

14

I

GND

1/06

~8

RAS 0
A9
AO
A1
A2
A3

10

"11"11

1::1::

1/04

Vee

28

II

1/01

Vee

.~

15

NC
A8
A7
A6
A5
A4
GND

i'I.
!

i

909

~

NEe

yPD42S4800,424800

Block Diagram

RAS 0----1
CAS 0----1

Clock
Generator

WE

Vee

0------

GND 0------

CAS before
RAS Counter
Memory
Cell
Array

1/01
to

1,024 x 512

Row
Address
Buffer
XO- X9

AD
to
A9
Column
Address
Buffer

910

x8

1/08

NEe

yPD42S4800,424800

Input/Output Pin Functions
The IlPD42S4800, 424800 have input pins RAS, CAS, WE, OE, AO to A9 and input/output pins 1/01 to
1/08.

Pin name

Input/Output

Function

RAS
(Row address strobe)

Input

RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh

CAS
(Column address strobe)

Input

CAS activates data input/output circuit by latching column address and

AO to A9

Input

Address bus.

selecting a digit line connected with the sense amplifier.

(Address inputs)

Input total 19-bit of address signal, upper 10-bit and lower 9-bit in sequence
(address multiplex method).
Therefore, one word is selected from 524,288-word by 8-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASe) and hold time (tRAH. tCAH)
are specified for the activation of RAS and CAS.

WE
(Write enable)

Input

Write control signal.
Write operation is executed by activating RAS, CAS and WE.

OE

Input

Read control signal.

(Output enable)

Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.

1/01 to 1/08
(Data inputs/outputs)

Input/Output

8-bit data bus.
1/01 to 1/08 are used to input/output data.

911

NEe

,uPD4254800, 424800

Electrical Specifications
All voltages are referenced to GND.
After power up (Vcc 2: VCC(MIN.)), wait more than 100 J1S (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.

Absolute Maximum Ratings
Rating

Unit

Voltage on any pin relative to GND

Parameter

VT

-1.0 to +7.0

V

Supply voltage

Vee

-1.0 to +7.0

V

Output current

10

50

mA

Power dissipation

Po

1

W

Operating ambient temperature

TA

o to +70

'C

Storage temperature

Tstg

-55 to +125

'c

Caution

Symbol

Condition

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section ofthis specification. Exposureto Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended Operating Conditions
MIN.

TYP.

MAX.

Unit

Supply voltage

Vee

4.5

5.0

5.5

V

High level input voltage

V,H

2.4

Vee+ 1.0

V

Low level input voltage

VIL

-1.0

+0.8

V

Operating ambient temperature

TA

0

70

'c

Parameter

Capacitance (T A

Condition

=25 ·C, f = 1 MHz)

Parameter
Input capacitance

Data input/output capacitance

912

Symbol

MAX.

Unit

Address

5

pF

C"

RAS, CAS, WE, OE

7

CliO

I/O

7

Symbol
Cil

Test condition

MIN.

TYP.

pF

NEe

yPD42S4800,424800

DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter
Operating current

Symbol
Icc,

Test condition

tRC

10

Standby

IlPD42S4800

Icc2

current
IlPD424800

RAS only refresh current

Icc3

IcC4

(Fast page mode)

=

tRAC

tRC (MtN.)

= 0 mA
~

~

RAS ,;; VIL (MAX.), CAS cycling
t.e

= t.e (M'N.), 10 = 0 mA

tRAC

2
1
105

refresh current

tRC

= tRC (M'N.)

10 = 0 mA

CAS before RAS
long refresh current
(1,024 cycles / 128 ms,
only for the IlPD42S4800)

Ices

1,2,3,4

mA

1,2,5

mA

1,2

95
80
80

= 70 ns

80

= 80 ns
= 100 ns
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
tRAC = 100 ns

RAS cycling

mA

100

70

tRAC

Icc,

mA

0.15

60

tRAC
CAS before RAS

1,2,3

2

tRAC

= tRC (M'N.), 10 = 0 mA

Notes

mA

80

= 60 ns
tRAC = 70 ns
tRAC = 80 ns
tRAC = 100 ns
tRAC = 60 ns

V'H (M'N.)

Unit

105

95

V'H (M'N.), 10

RAS cycling, CAS

MAX.

100

= 0 mA
RAS, CAS ~ Vcc - 0.2 V, 10 = 0 mA
RAS, CAS ~ V'H (M'N.), 10 = 0 mA
RAS, CAS ~ Vcc - 0.2 V, 10 = 0 mA
RAS, CAS

tRC

Operating current

MIN.

= 60 ns
tRAC = 70 ns
tRAC = 80 ns
tRAC = 100 ns

RAS, CAS cycling

105
100
95
80

CAS before RAS refresh :
tRC • 125.0 IlS
RAS, CAS:
Vcc - 0.2 V ,;; V'H ,;; V'H (MAX.)
o V,;; VIL';; 0.2 V

tRAS';; 200 ns

200

J1A

1,2

Standby:
RAS, CAS

tRAS ,;; 1 J1S

300

J1A

1,2

150

J1A

2

-10

+10

J1A

+10

J1A

~

Vcc - 0.2 V

Address: V'H or V'l
WE, OE: V'H
10 = 0 mA
CAS before RAS
self refresh current
(only for the IlPD42S4800)

Icc7

Input leakage current

h(l)

RAS, CAS:
tRASS = 5 ms
Vcc - 0.2 V ,;; V'H ,;; V'H(MAX.)
o V ,;; V'l ,;; 0.2 V
10 = 0 mA
V, = 0 to 5.5 V
All other pins not under test

=0 V

Output leakage current

10(l)

Va = 0 to 5.5 V
Output is disabled (Hi-Z)

-10

High level output voltage

VaH

10

2.4

Low level output voltage

VOL

= -5.0 mA
10 = +4.2 mA

V
0.4

V

Notes 1. ICC1, Icc3, Icc4, Iccs and Icc6 depend on cycle rates (tRC and tpc).
2. Specified values are obtained with outputs unloaded.

913

NEe

yPD42S4800,424800

3. Icc1 and Icc3 are measured assuming that address can be changed once or less during RAS ::;
and CAS ~

Vil (MAX.)

VIH (MIN.).

4. Icc3 is measured assuming that all column address inputs are held at either high or low.
5. Icc4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.

914

NEe

yPD42S4800, 424800

AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions

(1) Input timing specification

VIH IMIN.I

=2.4 V

VIL IMAX.I =

0.8

V

(2) Output timing specification

----------------r1

iL.

·--------3 i
I

I

,

I

I

I

I

,

~ ,[4

---+l---7+-

IT= 5 ns

IT = 5 ns

VOH IMIN.I

= 2.4

V

VOL IMAX.I

= 0.4

V

------=t-

}-

------=\..\..____--'

(3) Output load condition
VCC

I/O~-_---"

Common to Read, Write, Read Modify Write Cycle
tRAe
Parameter

Symbol

= 60 ns

tRAC

= 70 ns

tRAC

= 80 ns

tRAe

= 100 ns

Unit Notes

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

130

150

180

-

ns

Read I Write cycle time

tRC

110

RAS precharge time

tRP

40

CAS precharge time

tCPN

10

-

10

-

10

-

10

-

ns

RAS pulse width

tRAS

60

10,000

70

10,000

80

10,000

100

10,000

ns

CAS pulse width

teAs

15

10,000

20

10,000

20

10,000

25

10,000

ns

25

50

60

70

ns

1

RAS hold time

tRSH

15

-

20

60

70

-

80

-

100

-

ns

tesH

-

20

CAS hold time
RAS to CAS delay time

tRCD

20

45

20

50

25

60

25

75

ns

2

RAS to column address delay time

tRAD

15

30

15

35

17

40

17

50

ns

2

CAS to RAS precharge time

tCRP

5

-

5

-

5

5

3

tASR

0

-

0

-

0

-

ns

Row address setup time

-

10

0

-

15

-

20

-

ns

0

-

0

-

ns

-

ns

Row address hold time

tRAH

10

Column address setup time

tAse

0

Column address hold time

tCAH

15

OE lead time referenced to RAS

tOES

0

CAS to data setup time

tCLl

OE to data setup time

tOll

0

OE to data delay time

tOED

15

Transition time (rise and fall)
Refresh time

I IlPD42S4800
J IlPD424800

0

-

0
15
0
0

a
15

-

IT

3

50

3

50

tREF

-

128

128

-

16

-

16

12
0

0

a
15
3

-

-

0
12

0

a
20

ns

ns
ns
ns

ns

ns

50

3

50

ns

128

-

128

ms

16

ms

16

4

915

NEe

yPD42S4800,424800

Notes 1. In CAS before RAS refresh cycles, tRAS(MAX.) is 100 J.IS.

---

---

If 10 JlS < tRAS < 100 J.IS, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

~ tRAD (MAX.)

and

tRCo

:5

tRCo (MAx')

tRAC (MAX.)

tRAD> tRAD (MAX.)

and

tRCO

$'

tACO (MAX.)

tAA (MAX.)

tRAD

+

tCAC (MAX.)

tRCO

+ tCAC (MAX.)

tAAD

tRCO

>

tACO (MAX.)

tRAC (MAX.)
tAA (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points on Iy ; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when data
will be available. Therefore, the input conditions tRAD

~

~

tRAD (MAX.) and tRCD

tRCD (MAX.) will not cause any

operation problems.

3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the ,uPD42S4800.
Read Cycle
Parameter

tRAG = 60 ns

tRAG = 70 ns

tRAG = 80 ns

tRAG = 100 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

70

-

80

-

100

ns

1

20

-

20

-

25

ns

1
1

Symbol

Unit Notes

Access time from RAS

tRAG

-

60

Access time from CAS

tGAG

-

15

-

tAA

-

30

-

35

-

40

ns

tOEA

-

15

-

20

-

20

-

50

Access time from OE

25

ns

Column address lead time

tRAl

30

-

35

-

40

-

50

-

ns

-

0

-

ns

-

0

-

ns

2

Access time from column address

referenced to RAS
Read command setup time

tRGS

-

a
a

-

tRRH

a
a

-

Read command hold time

-

a
a

tACH

0

-

a

-

0

-

0

-

ns

2

tOEZ

a

15

a

15

a

15

0

20

ns

3

tOFF

0

15

a

15

0

15

0

20

ns

3

referenced to RAS
Read command hold time
referenced to CAS
Output buffer turn-off delay
time from OE
Output buffer turn-off delay
time from CAS

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

tRAD (MAX.)

and

tRCo

$'

tACO (MAX.)

tRAC (MAX.)

tRAC (MAX.)

tRAD> tRAD (MAX.)

and

tRCO

$'

tRCo (MAX.)

tM (MAX.)

tRAD

+

tAA (MAX.)

tcAC (MAX.)

tRCo

+

tCAC (MAX.)

tRAD

$'

tACO> tACO (MAX.)

tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD

~

tRCD (MAX.) will not cause

any operation problems.

2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

916

NEe

yPD42S4800, 424800

Write Cycle
tRAe
Parameter
WE hold time referenced to CAS

Symbol

= 60 ns

tRAe

= 70 ns

tRAe

=. 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

10

-

15

10

-

tWCH

10

WE pulse width

twp

10

WE lead time referenced to RAS

tRWl

15

WE lead time referenced to CAS

tcWL

15

WE setup time

twcs

0

OE hold time

tOEH

0

Data-in setup time

tDS

0

Data-in hold time

tDH

15

-

20
15
0
0
0
15

-

15
20
15
0
0
0
15

= 100 ns

tRAe

MIN.

MAX.

20

-

20
25
20
0
0
0
20

Unit Notes
ns

1

ns

1

ns
ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
tRAe
Parameter

Symbol

= 60 ns

tRAe

= 70 ns

tRAe

= 80 ns

tRAe

= 100 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

175

-

200

-

240

-

Read modify write cycle time

tRWC

150

RAS to WE delay time

tRWD

80

CAS to WE delay time

tewD

35

Column address to WE delay time

tAWD

50

90
40
55

105
45
65

130
55
80

Unit

Note

ns
ns

1

ns

1

ns

1

Note 1. If twcs ~ twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.), tcWD ~ tCWD (MIN.), tAWD ~ tAWD (MIN.) and tCPWD ~ tcPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

917

NEe

yPD42S4800, 424800

Fast Page Mode
Parameler

IAAe = 60 ns

IAAe

MIN.

MAX.

MIN.

Symbol

= 70 ns

IAAe

MAX.

MIN.

= 80 ns

IAAe = 100 ns
Unil

MAX.

MIN.

Fasl page mode cycle lime

Ipe

40

-

45

-

50

-

60

-

ns

Access lime from CAS precharge

IAep

-

35

-

40

-

45

-

55

ns

80

125,000

100

10
45

-

55

-

ns

95

-

115

-

ns

70

-

85

-

ns

tAASP

60

125,000

70

125,000

lep

10

-

10

RAS hold time from CAS precharge

tAHCP

35

-

40

-

Read modify wrile cycle lime

tPRWC

80

-

85

CAS precharge 10 WE delay lime

tCPWD

55

-

60

RAS pulse widlh
CAS precharge lime

-

10

Nole

MAX.

125,000 ns
ns

1

Note 1. If twcs;:: twcs (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ;:: tRWD (MIN.), tCWD;:: tCWD (MIN.), tAWD ;:: tAWD (MIN.) and tCPWD ;:: tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

Refresh Cycle
Parameter

lRAe = 60 ns

IAAe = 70 ns

IAAe = 80 ns

IAAe = 100 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MIN.

MAX.

-

5

-

5

-

ns

10

-

10

-

ns

Unil

Symbol

CAS selup lime

lesA

5

-

5

CAS hold lime (CAS before RAS refresh)

leHA

10

-

10

MAX.

Nole

RAS precharge CAS hold lime

tAPe

5

-

5

-

5

tRASS

100

-

100

-

5

RAS pulse width
(CAS before RAS self refresh)

100

-

100

-

/15

1

tAPS

110

-

130

-

150

-

180

-

ns

1

leHs

-50

-

-50

-

-50

-

-50

-

ns

1

IWHA

10

-

15

-

15

-

20

-

ns

RAS precharge lime

ns

(CAS before RAS self refresh)
CAS hold lime
(CAS before RAS self refresh)

WE hold lime

Note 1. This specification is applied only to the tLPD42S4800.

918

NEe

yPD42S4800,424800

Read Cycle

tRe
tRP

tRAS

RAS

V,HV,LtesH

CAS

V,HV'L-

Address V,HV'L-

V'HV,L-

tOLZ

tell

1/0

VOHVOL-

Hi-Z
- -- -- - - ----- -- - -- - - -- --- -- --- --- ------- - -- - -- --- ---

919

NEe

yPD42S4800,424800

Early Write Cycle

tRC
tRAS

tCSH

Address VII+-

V'L-

1/0

V,HV'L-

Remark OE: Don't care

920

NEe

yPD42S4800,424800

Late Write Cycle

IRC
tRAS

V,HVIL-

Address V,HVIL-

921

NEe

yPD42S4800,424800

Read Modify Write Cycle

tRAS

V,HV'LlesH
tRCO

tCPN

tRSH

Address V'HV,LtAWD

lewD
WE

V'HV'L-

IOEA
OE

VlttV'L-

1/0

V'HV'L-

leAe

~---------

tOEH

IDS

IDH
Dala in

loLZ

1/0

922

VottVOL-

Hi-Z

Hi-Z

NEe

yPD42S4800,424800

Fast Page Mode Read Cycle

tRP

tRASP

RAS

V,HV,L-

tRHCP

tCSH

CAS

tpc

tRSH

V,HV'L-

V,H-

Address V,L-

~H- ~~-r~~T-~---+----------~~r+----------~~r+----------~~T-~~~'
V'L- L..L-'-'-,IRAD (MAX.) and IRCD S IRCD (MAX.)

tAA(MAX.)

IRAD + 1M (MAX.)

IRCD > IRCD (MAX.)

ICAC (MAX.)

tRCD

+ tCAC (MAX.)

tRAD (MAX.) and tACO (MAX.) are specified as reference paints only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the tlPD42S4260.

Read Cycle
Parameler

Symbol

Access lime from RAS

tRAC

Access lime from CAS

!cAc

Access lime from column address

tM

IRAC - 60 ns

lRAC = 70 ns

lRAC - 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

-

60

-

70

15

20

-

30

-

35

-

Unit

Noles

80

ns

1

20

ns

1

40

ns

1

Access lime from OE

IOEA

-

15

-

20

-

20

ns

Column address lead time referenced 10 RAS

lRAL

30

35

-

40

IRcs

0

0

0

Read command hold time referenced 10 RAS

IRRH

0

2

IRCH

0

0

0

-

ns

Read command hold time referenced 10 CAS

-

-

ns

Read command selup lime

-

ns

2

Oulput buffer lurn-off delay lime from OE

loEZ

0

15

0

15

0

20

ns

3

Output buffer lurn-off delay time from CAS

IOFF

0

15

0

15

0

20

ns

3

0

0

ns

Notes 1. For read cycles, access time is defined as follows:
Input conditions

Access time

Access time from RAS

IRAD S IRAD (MAX.) and IRCD s tRCD (MAX.)

lRAC (MAX.)

tRAC (MAX.)

IRAD >IRAD (MAX.) and IRCD S IRCD (MAX.)

1M (MAX.)

IRAD + 1M (MAX.)

tRCD > tRCD (MAX.)

lCAC (MAX.)

IRCD + lCAC (MAX.)

tRAD (MAX.) and tACO (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, lAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ~ tRAD (MAX.) and tRCD ~ tACO (MAX.) will not cause
any operation problems.
2. Either tACH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ (MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.

943

NEe

yPD42S4260,424260

Write Cycle
Parameter

Symbol

tRAC

= 60 ns

tRAC

= 70 ns

tRAC = 80 ns

MIN.

MAX.

MIN.

MAX.

MIN.

-

15

-

15
15

WE hold time referenced to CAS

tWCH

15

WE pulse width

\wP

10

WE lead time referenced to RAS

tRWL

15

WE lead time referenced to CAS

tCWl

15

-

15
20
15

WE setup time

twcs

0

OE hold time

tOEH

0

-

Data-in setup time

tDS

0

-

0

Data-in hold time

tDH

15

-

15

0
0

-

20
20
0

Unit

Notes

-

ns

1

-

ns

1

MAX.

-

-

0

-

20

-

0

ns
ns
ns

2

ns
ns

3

ns

3

Notes 1. twp (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles. tWCH (MIN.) should
be met.
2. If twcs ~ twcs (MIN.). the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles. they are referenced to the WE falling edge.

Read Modify Write Cycle
Parameter

tRAC = 60 ns

tRAC = 70 ns

tRAC = 80 ns

MIN.

MIN.

MAX.

MIN.

MAX.

-

200

-

Symbol

Unit

Read modify write cycle time

tRWC

150

RAS to WE delay time

tRWD

80

CAS to WE delay time

tCWD

35

Column address to WE delay time

lAy_,O

50

MAX.

-

175

40

-

55

-

90

105
45
65

Note

ns
ns

1

ns

1

ns

1

Note 1. If twcs ~ twcs (MIN.). the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ~ tRWD (MIN.). tCWD ~ tCWD (MIN.). tAWD ~ lAWD (MIN.) and tCPWD ~ tCPWD (MIN.). the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met. the state of the data out is indeterminate.

944

NEe

yPD42S4260,424260

Fast Page Mode
Parameler

IRAC = 60 ns

IRAC = 70 ns

IRAC

MIN.

MAX.

MIN.

MAX.

MIN.

z

80 ns

Symbol

Unil

Fasl page mode cycle lime

Ipc

40

-

45

-

50

-

Access lime from CAS precharge

IACP

-

35

-

40

-

45

ns

tRASP

60

125,000

70

125,000

80

125,000

ns

Icp

10

10

-

10

-

ns

RAS hold lime from CAS precharge

IRHCP

35

-

ns

IPRWC

80

100

IePWD

55

-

ns

CAS precharge 10 WE delay lime

-

45

Read modify wrile cycle lime

-

RAS pulse widlh
CAS precharge lime

40
85
60

70

Nole

MAX.
ns

ns

1

Note 1. If twcs 2! twcs (MIN.), the cycle is an early write cycle and the data ciut will remain Hi-Z through the entire cycle.

If tRWO 2! tRWO (MIN.), tcwo 2! tcwo (MIN.), tAWO 2! tAWO (MIN.) and tcPWO 2! tcPWO (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.

Refresh Cycle
lRAC
Parameler

Symbol

=70 ns

lRAC

=80 ns

Unil

Nole

MIN.

MAX.

MIN.

MAX.

10

-

10

-

ns

100

-

100

-

ns

10

-

15

!IS

1

IRpc

10

lRASS

100

-

IRPS

110

-

130

-

150

-

ns

1

ICHS

-50

-

-50

-

-50

-

ns

1

IWHR

10

-

15

-

15

-

ns

IeSR

10

CAS hold lime (CAS before RAS refresh)

ICHR

10

RAS pulse widlh

lRAC

MAX.

CAS selup lime

. RAS precharge CAS hold lime

=60 ns

MIN.

15

10

ns

(CAS before RAS self refresh cycle)
RAS precharge lime
(CAS before RAS self refresh cycle)
CAS hold lime
(CAS before RAS self refresh cycle)
WE hold lime (hidden refresh cycle)

Note 1. This specification is applied only to the JlPD42S4260.

945

NEe

yPD42S4260,424260

Read Cycle
tRC
tRAS

RAS

tRP

V,HV,LtCSH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

tOl2
tCl2
U 1/0

L I/O

946

VooVOL-

~·Z

••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

Data out

Hi ·Z

l

_--.,;....N....;;.E~C=--_ _ _ _ _ _ _ _ _ _ _ _ _--/;;;Jl;.;....P.;;;...D...;.;42=S;.;....4=26;.;....O;;..l,.,......;.4=24...;.;;2=6....;;..O_ _ _i~
,~

Upper Byte Read Cycle
tRe
tRP

tAAS

RAS

V,HV,LtesH

UCAS

V,HV'L-

LeAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

--t-.........................+-.>-...........,.....................................+------t--.....-t'!,............................................

-:o....;.....................

IoLz

teLZ

U 1/0

VOHVOL-

Hi -Z

Data out

Hi -Z

Remark L 110: Hi-Z

947

NEe

yPD42S4260,424260

Lower Byte Read Cycle
lAC
lAP

tRAS

RAS

V,H-

VIl-

UCAS

V,H-

LCAS

VIl-

Address

VIl-

WE

VIl-

OE

V,H-

V,H~~~~~~~~~T

V,H-

VIl- __~~~~~~~~~~~~~-+~~~~~~~__________-+____~~~~~~~~~

IOLZ
leLZ

L110

VOHVOl-

Remark U I/O: Hi-Z

948

Hi-Z

Dalaoul

Hi-Z

"

_~N....;;;".,;;;;E.....;C=--_ _ _ _ _ _ _ _ _ _ _ _ _ _. .J1_P_D_42_S_4_2_60....:.,_4_2_42_6_O
..
_ _ _ _·.~
;,~

Early Write Cycle
tRC
tRAS

RAS

tRP

V,HVILtCSH

UCAS
LCAS

Address

V,HVIL-

VtH-

VIL-

WE

V,HVIL-

U 1/0
L 1/0

V,HVIL-

Remark OE: Don't care

949

NEe

yPD42S4260,424260

Upper Byte Early Write Cycle
tRC
tRAS

RAS

V,HVILtCSH

UCAS

V,HVIL-

LCAS

Address

WE

UI/O

Remark OE, L 110: Don't care

950

tRP

NEe

yPD42S4260, 424260

Lower Byte Early Write Cycle
tRC
tRAS

RAS

tCRP

UCAS

tRP

V,HVIltMRH

VIHVIL-

Address

V,HVIl-

WE

V,HVIl-

L I/O

Remark OE, U 110: Don't care

951

NEe

yPD42S4260, 424260

Late Write Cycle
tRe
tRAS

RAS

V,HVIltCSH

tReo

tASH

teAs
UCAS
LCAS

V,HVIl-

Address

V,HVIl-

WE

V,HVIl-

tOED.

U 110
L 1/0

952

YJ:l) .......~!:!: ...... .

toH
Data in

I

!,
NEe

il
i I,

yPD42S4260, 424260

------~~~~~--------------------------------------------------------~--------------~----------------------~:~
j'

Upper Byte Late Write Cycle
tRe
tRP

tRAS

RAS

VIH-

VIltesH
tRCD

tRSH
teAS

UCAS

V,HVIl-

LCAS

V,HVIl-

Address

WE

OE

V,HVIl-

I-I.-<... .................""'-'-'-..J

V1H-

VIl-

I -............'-''-''-L-L........J

tOH

U 1/0

ZZZ) .......~!:.~ ...... .

Data in

Remark Lila: Don't care

953

NEe

yPD42S4260,424260

Lower Byte Late Write Cycle
tRe
tRP

tRAS

RAS

V,HV,LtMRH

UCAS

V,HVIL-

tesH
tReo
LCAS

Address

WE

tRSH
teAs

V,HV,L-

V,HVIL-

V,HV,L-

tOH

LIIO

VIH-

VIl-

'llf) ....... ~i:.~

Remark U I/O: Don't care

954

•••••••

~.,,-~_ _ _ _D_a_t_a_in_ _ _ _

-Jl

"-"'-'''-'~'-''~'-''-''

.....................-''

!~~
NEe
,uPD42S4260, 424260
-----.....;....;;;;;;....----------------------------......
---.....;---~------------ii~
1:1,

'I

'I

Read Modify Write Cycle

i

I

tRWC

tRP

tRAS

RAS

V,HVIltCSH

tRCO

UCAS
LCAS

Address

WE

tRSH

teAs

V,HVIL-

V,HVIl-

V,HVIl- ...........L-<'--''-'-r''-L-L...J.......L..r'

OE

U 1/0

LlIO

U 1/0

LlIO

~--.--.------ .. ---- ..

VOH- •••••••••••••••••••• ~~.-.~ •••••••••••••••••
VOL-

Hi -Z

11

!I
,J

II
I!

j
i

I
11

II

I:

j

II
955

il

!I

NEe

yPD42S4260,424260

Upper Byte Read Modify Write Cycle
tRWC
tRAS

IRP

RAS
ICSH
tRCO

UCAS

V,HV,L-

LCAS

V,HV,L-

Address

V,HV,L-

tRSH

ICAS

WE

OE

V,HV,L-

U 1/0

V,HV,L-

U 1/0

VOH- .••••••••••••••••••••~~:!:
VOL-

~ .................. .

................

Hi· Z

Remark In this cycle, the input data to Lower 1/0 is ineffective. The data out of that remains Hi·Z.

956

NEe

yPD42S4260,424260

Lower Byte Read Modify Write Cycle

tRP

Address

V,HV,L-

V,HV,L-

OE

Ll/O

Ll/O

V,HV,L-

()()()()()()(} -- .... -- .... -- .....

VOII- •••••••••••••••••••• ~~:.~ ••••••••••••••••

Hi-Z

VOl-

Remark In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi-Z.

957

NEe

yPD42S4260,424260

Fast Page Mode Read Cycle
lRASP

RAS

tRHCP

VII"I-

V,LIcsH

UCAS
LCAS

V,HV,L-

Address

V,HV,L-

WE

V,HV,L-

OE

V,HV,L-

U 1/0
L 1/0

VOHVOL-

•••••••••••••• ~!;.2; •........•

Hi ·Z

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

958

NEe

yPD42S4260,424260

Fast Page Mode Byte Read Cycle

i1
RASP

RAS

UCAS

V'HV'L-

Ipc

teSH

~

tRCD

y

~

~

Address

V'HV'L-

~

V'HV'L-

-'

~~
Row

m m~

~
Col.

t~
WE

V'HV'L-

IMRH

V'HV'L-

~

tAC!

'111111

~~

tRCH

M

~

tRCS

~

!cAe

teLZ

UI/O

Vrx-

______ ~i_:~_____________ ~

..

IV

W
OLZ

'-r

IAA
tCAC

Hi -Z
IAA
tCAC

~
LIIO

Va+Vrx-

~

IDES

,IDEA.
£-"\ I~
J /IIII~

WF

Data out

~ttRRH

ACP

Del

>IT~

t-

"'h- l+r

1'1\/

\\\\\\\\\\\~

1OO )(X

Col.

Col.

ft" I!M-

tRAC
IAA

Va+-

'-

lRAL

IAcp
OE

'-

I

J
l,tRAD,

I

~

~

tCAS

It

~

IRSH
tCAS

!cAs

~
LCAS

~

tRHCP

V'HV'L-

Hi-Z
----------------------------------------------------~

~

--- --- ----------<>

~
~

Hi-Z
Dataout ~-------.

~El

~

).~

--------- ----------------_.
Hi-Z

)----

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS'cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LeAS simultaneously, or at random.

959

NEe

yPD42S4260, 424260

Fast Page Mode Early Write Cycle

V,HRAS VIL-

UCAS V,HLCAS V,L-

Address V,HV,L-

U 1/0 V,HL 1/0 V,L-

Remarks 1. OE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

960

NEe

yPD42S4260,424260

II

Fast Page Mode Byte Early Write Cycle
lRASP
IRHCP

Address VVIHIL-

I.
,

U I/O V,HV,L-

L I/O V,HV,L-

Remarks 1. DE: Don't care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

961

NEe

yPD42S4260, 424260

Fast Page Mode Late Write Cycle
tRASP
tRHCP

RAS V,HV,L-

UCAS
LCAS

V,HV,L-

Address V,HV,L-

WE V,HV,L-

OE V,HV,L-

U 1/0 V,HL 1/0 V,L-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.

962

j

_ _N_E_C....;;;;;...._ _ _ _ _ _ _ _ _ _ _ _ _ _---t:.y;;,;;.P..,;;D:.....,;4;.:;;:2;.::,S....:.,;42::..:6:....:0:..!..I....:.4=-24..:..:2::..:6:....:.0_ _ _:~

II
i'"

I

I~

Fast Page Mode Byte Late Write Cycle

'\

:'~

!

!~

tRASP
tRHCP

tpe

tesH
teAs

UCAS

tRSH

teAS

V,HVIL-

tMAH

LCAS

V,HVIL-

Address

V,HV,L-

WE

OE

V,HVIL-

U 1/0

........<--L-L....L...J

V,HVIL-

L 1/0 V,H- ______ !:lj:_~ ________ _
VIL-

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.

2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

963

NEe

yPD42S4260,424260

Fast Page Mode Read Modify Write Cycle

RAS V,H-

V,L-

UCAS
LCAS

V,HV,L-

Address V,HV,L-

WE

~::~

OE V,HV,L-

U I/O VOHL I/O VOL-

U I/O V,HL I/O V,L-

Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive

CAS cycles within the same RAS cycle.

964

____N
___E=C-=-_ _ _ _ _ _ _ _ _ _ _ _ _ _

- i.Jl: :.P-=D:. . .;4:. : 2~S. .:.:42=.;6:.;:0;.L.,

1

...::,4=.24..:..:2:.;:6:..::;0_ _ _

i

Fast Page Mode Byte Read Modify Write Cycle

It
tRASP

III

t

IPRwe
leAS

I

leAS

t
,I
LeAS

V,HV,LtAAl

Address

WE

V,HV,L-

V,HV,L- '--'~-L+J

Hi-Z
--------... ----_.

U 1/0

L 1/0 VOHVOLV,HU 1/0 V,L-

L I/O V,HV,L-

Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.

965

NEe

yPD42S4260, 424260

CAS Before RAS Self Refresh Cycle (Only for the JlPD42S4260)
tAASS

V,HV,L-

Remark Address, WE, OE:

Don'~

care

L 110, U 110: Hi-Z

Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 512 times within an 8ms interval just before and after setting CAS before RAS
self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh arid RAS only refresh are used in combination, please perform RAS only
refresh 512 times within an 8 ms interval just before and after setting CAS before RAS sel.f refresh.
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 ps), CAS before
RAS refresh cycles will be executed one time.
If 10 JlS < tRAS < 100 ps, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (512/128 ms) should be met.
For details, please refer to How to use DRAM User's Manu!!1.

966

NEe

yPD42S4260,424260

CAS Before RAS Refresh Cycle

UCAS V,HLCAS V,LRemark Address, WE, OE: Don't care

L 110, U 1/0: Hi-Z

RAS Only Refresh Cycle
IRc
tRAS

RAS

IRP

t"AS

V,HV,L-

tCRP

UCAS V,HLCAS V,L-

Address

V,HV,L-

Remark WE, OE: Don't care

L 1/0, U 1/0: Hi-Z

967

NEe

,uPD42S4260, 424260

Hidden Refresh Cycle (Read)
IRC

lRAS

IRAS

IRSH

UCAS
LCAS

ICHR

ICPN

V,HV,L-

Address

WE

OE

V,HV,L-

V,HV,LIRAC

I

U I/O

L 1/0

968

VOHVOL-

C

•••••••••••••••••':!l:~ ........................ .

Hi·Z_--_ ...... .
............

NEe

yPD42S4260, 424260

Hidden Refresh Cycle (Write)
tRC

tRC
tAAS

RAS

V,HVIL-

UCAS
LCAS

V,HVIL-

tRAS

Address

WE

V,HVll-

U I/O
L I/O

Remark OE:

Don't care

969

NEe

yPD42S4260,424260

Package Drawings

44 PIN PLASTIC TSOP(ll) (400 mil)

44
detail of lead end

-t-t--------+--------t-

7
.~.
~~----nn-L-n-nn.

Ie

J

L

NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

A

18.63 MAX.

B
C

0.93 MAX.
0.8 (T.P.)

0.734 MAX.
0.037 MAX.

0

0.32~8:g~

0.013±0.003

E
F

0.)±0.05
1.2 MAX.
0.97
11.76±0.2

0.004±0.002

G
H

0.031 (T.P.)

0.048 MAX.
0.038
0.463±0.008

10.16±0.1

0.400±0.004

0.8±0.2

0.031~8:gg3

0.145~8:8~g

0.006±0.001

L

0.5±0.1

0.020~g:gg~

M

0.005

N

0.13
0.10

P

3 0 _3°
+70

3 0 _3°
+70

K

0.004

S44G5-8D-7JF4

970

NEe

yPD42S4260,424260

40 PIN PLASTIC SOJ (400 mil)
B

40

21

t+-------+--------+ o

CI

20

F

E

n-----~------~==~~

P

NOTE

Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

INCHES

B

26.29~8:~5

1.035~8:8~~

c

10.16
11.1StO.2

0.400
0.440tO.00S

0

E

1.0StO.15

0.043~8:88~

F

0.7
3.5tO.2

0.02S
0.13StO.00S

G
H

2.4tO.2

0.094~8:88~

I
J

0.031 MIN.
0.102
0.050(T.P.)

K

O.S MIN.
2.6
1.27(T.P.)

M

0.40tO.10

0.016~8:88~

N
P
T

0.12
9.40tO.20
0.15
RO.85

0.005
0.370tO.008
0.006
RO.033

u

0.20~8:6g

0.008~8:88~

Q

P40LE-400A-2

971

NEe

yPD42S4260,424260

Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met when' soldering ILPD42S4260.
424260.
For more details. refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(IEI-1207).
Please consult with our sales offices in case other soldering process is used. or in case the soldering is done
under different conditions.

Types of Surface Mount Device
ILPD42S4260G5, 424260G5: 44-pin plastic TSOP (n) (400 mil)
Soldering
process

Soldering conditions
Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210'C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125'C afterwards)

Infrared ray
reflow

Symbol
IR35-107-2

Cautions
1. After the first reflow process, cool the package down to room temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used In the second process),
Peak temperature of package: 215'C or lower.
Reflow time: 40 seconds or less (200 ·C or higher).
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote

VPS

VP15-107-2

(10 hours pre-baking is required at 125 ·C afterwards)
Cautions
1. After the first reflow process, cool the package down to room temperature, then start the second reflow process.
2, After the first reflow process. do not use water to remove residual flux
(water can be used In the second process).
Partial heating
method

Terminal temperature: 300'C or lower.
Time: 3 seconds or less (Per side of the package).

-

Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.
Caution Do not apply more than one soldering method at anyone time, except for "Partial heating
method",

972

NEe

I

pPD42S4260, 424260

.uPD42S4260LE, 424260LE: 4Q-pln plastic SOJ (400 mil)
Soldering
process

Soldering conditions

Infrared ray
reflow

Peak temperature of package surface: 235'C or lower,
Reflow time: 30 seconds or less (210 ·C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ·C afterwards)

Symbol
IR35-207-2

Cautions

1. After the first reflow process, cool the package down to room temperatu re, then start the second reflow process.

2. After the first reflow process, do not use water to remove residual flux
(water can be used In the second process).
Peak temperature of package: 215'C or lower,
Reflow time: 40 seconds or less (200 ·C or higher),

VPS

VPI5-207-2

Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ·C afterwards)
Cautions

1. After the flrat reflow process, cool the package down to room temperature, then start the second reflow process.

2. After the flrat reflow process, do not use water to remove residual flux
(water can be used In the second process).
. Partial heating
method

Note

Terminal temperature: 300'C or lower,
Time: 3 seconds or less (Per side of the package).

-

I
I

Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25'C and relative humidity at 65 % or less.

Caution

i,

Do not apply more than one soldering method at anyone time, except for "Partial heating

I

method".

973

NEe
[MEMO]

974

,uPD42S4260,424260

Synchronous DRAM

975

DATA SHEET

NEe

MOS INTEGRATED CIRCUIT

I.;
~PD4516421,4516821,4516161
II
---------------------------------------------------j

16M-bit Synchronous DRAM

-----------','j
I"

I'J

il

Description

'~

The jlPD4516421, 4516821, 4516161 are high-speed 16,777,216-bit synchronous dynamic random-access
memories, organized as 2,097,152x4x2, 1,048,576x8x2 and 524,288x16x2 (wordxbitxbank), respectively,
The synchronous DRAMs achieve high-speed data transfer using the pipeline architecture,
All inputs and outputs are synchronized with the positive edge of the clock,
The synchronous DRAMs compatible with Low Voltage TTL (LVTTL),
The synchronous DRAMs are packaged in 44-pin TSOP (II) (x4, x8) and 50-pin TSOP (II) (x16),

Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Dual internal banks controlled by A11 (Bank Select)
Programmable burst-length (1, 2, 4, 8 Full Page)
Programmable wrap sequence (Sequential/Interleave)
Programmable CAS latency (2,3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
x4, x8, x16 organization
Single +3,3±0,3 V power supply
LVTTL compatible
Byte control (x16) by LOOM and UDOM
2,048 refresh cycles/32ms
Burst termination by Burst Stop command and Precharge command

Please contact your NEe sales representative
if you need a complete data sheet.

The information in this document is subject to change without notice.
Document No, M1 0429EU2VODSU1

977

NEe

yPD4516421,4516821,4516161

Ordering Information

Part number
I'PD4516421 G5-A 10

(word x bit x bank)

Organization

Clock frequency
MHz (MAX.)

Package

2Mx4x2

100

44-pin Plastic TSOP(II)

83

(400mil)

4516421G5-A12
4516421G5-A13

77

4516421G5-A15
I'PD4516821 G5-A10
4516821 G5-A12

66
1Mx8x2

978

44-pin Plastic TSOP(II)
(400mil)

77

4516821 G5-A13
4516821G5-A15
I'PD4516161 G5-A1 0
4516161G5-A12

100
83
66

512Kx16x2

100
83

4516161G5-A13

77

4516161G5-A15

66

50-pin Plastic TSOP(II)
(400mil)

IiI~

PRELIMINARY DATA SHEET

NEe

-------------M-O-S--IN-T-E-G-R-AT-E-D--C-IR-C-U-IT----~:I
II

~_ _ _ _ _ _ _J.l_PD_4_5_'_64_2_'_-P_C_,_4_5_'6_8_2_'-_P_c_'_45_'_6_'_6'_-_P_c_ _1i
'~;

16M-bit Synchronous DRAM for PC
SDRAM Lite

Description
The PPD4516421-PC, 4516821-PC, 4516161-PC are high-speed 16,777,216-bit synchronous dynamic randomaccess memories, organized as 2,097,152x4x2, 1,048,576xBx2 and 524,288x16x2 (wordxbitxbank), respectively.
The synchronous DRAMs achieve high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
The synchronous DRAMs are packaged in 44-pin TSap (II) (x4, xB) and 50-pin Tsap (II) (x16).

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Dual internal banks controlled by A 11 (Bank Select)
Burst-length: 1. 2, 4
Programmable wrap sequence (SequentiaVlnterleave)
CAS latency: 2, 3
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
x4, xB, x16 organization
Single +3.3±O.3 V power supply
LVTTL compatible
Byte control (x16) by LDOM and UDOM
2,048 refresh cycles/32ms
Burst termination by Precharge command

i1
'\

Ii
:i

Please contact your NEe sales representative
if you need a complete data sheet.

,\

Ii

11,,!

\

'1

IJ

Ii
!

~

"

~...

Document No. M11029EJ2VODSU1

i:'.

Information In thl. do.u....nt Ia .ubJ••t to .h.nge without notl ••.

11

979

II

!l

NEe

pPD4516421-PC, 4516821-PC, 4516161-PC

Ordering Information

Part number
ttPD4516421 G5-A83-PC
4516421 G5-A75-PC

Organization
(word x bit x bank)
2Mx4x2

4516421 G5-A67-PC
4516421 G5-A60-PC
jlPD4516821 G5-A83-PC

Package

83
75

44-pin Plastic TSOP(Jn
(400mil)

67
60
1Mx8x2

83

4516821 G5-A75-PC

75

4516821 G5-A67-PC
4516821 G5-A60-PC

67
60

ttPD4516161 G5-A83-PC
4516161 G5-A75-PC
4516161 G5-A67-PC
4516161 G5-A60-PC

980

Clock frequency
(MHz)

512Kx16x2

83
75
67
60

44-pin Plastic TSOP(II)
(400mil)

50-pin Plastic TSOP(ll)
(400mil)

,,

1

III

'1

"

How to Use DRAM

981

\

NEe

USER'S MANUAL

HOW TO USE DRAM

_

_

_

_

_

_

1

-I

I
i~

I]
1'1
i

Document No. Ml0339EJ2VOUMUl

INTRODUCTION
Purpose

This manual is intended for users who understand DRAM functions and design application systems using DRAMs.

Readers

This manual explains the basic properties of DRAM and their use.

How to read this manual It is assumed that readers of this manual have general knowledge in the fields of

electricity, logic circuits, and memory. For further details on the functions of each device,

l

il
j

please refer to their data sheets.

1

DRAM devices can be divided into 5.0-V and low-voltage operation devices. This manual

1

concentrates on 5.0-V operation devices (For information on low-voltage operation
1

devices, see CHAPTER 10 LOW VOLTAGE OPERATION).
This manual uses the following abbreviations for refresh functions:

Legend

CAS before RAS refresh

~

CRB refresh

CAS before RAS long refresh

~

CBR long refresh

CAS before RAS self refresh

~

CBR self refresh

RAS only refresh

~

ROR

Long RAS only refresh

~

Long ROR

Active low

xxx (top bar over pin or signal name)

Note

Footnote

Caution

Points to be noted

Remark

Supplementary explanations for main text

Numeric representations: decimal ... xxxx
Related documents

Document related to the IlPD42161 00
• IlPD42161 00, 4217100 Data Sheet (lC-2923)
Document related to the IlPD4216400
• IlPD42S16400, 4216400, 42S17400, 4217400 Data Sheet (lC-2922)
Document related to the IlPD42S16160, 4216160, 42S18160
• IlPD42S16160, 4216160, 42S18160, 4218160 Data Sheet (lC-3217)
Document related to the IlPD42S16160L
• IlPD42S16160L, 4216160L, 42S18160L, 4218160L Data Sheet (IC-3218)
Document related to the Hyper Page Mode (HPM)
• IlPD4216165 Data Sheet (lC-3378)

985

~

[MEMO]

986

CHAPTER 1 DEFINITION OF DRAM

1.1 Classification of IC Memory
The CMOS IC memory can be divided into two main categories, namely RAM (RWM) and ROM (Read Only
Memory).
Figure 1-1 shows the classification of the CMOS IC memory.

Figure 1-1. CMOS IC Memory Classification

RAM~DRAM

(RWMl

SRAM

CMOS IC memory {
ROM

(1)

-C PROM
Mask ROM

RAM (Random Access Memory) ...RWM (Read Write Memory)
The RAM can be broadly divided into DRAM and SRAM (See 1.2 DRAM Features). The RAM memory freely
enables high-speed reading and writing.
The ROM also enables reading freely but the RAM generally enables both reading and writing freely. All
data in the RAM are lost by turning off the power.
The DRAM can be further divided into conventional DRAM and high-speed DRAM. High-speed DRAM refers
to synchronous DRAM and Rambus™ DRAM operating in synchronization with a clock and page access
time enabling as compared with conventional DRAMs. This user's manual describes conventional DRAMs.
See each user's manual for the details on the synchronous DRAM and Rambus DRAM.

(2)

ROM (Read Only Memory)
The ROM can be broadly divided into PROM and mask ROM. It is a memory exclusively used for reading
only. Data contained in ROM are retained even if the power is turned off.

As its name indicates, the ROM (Read Only Memory), once written, can be read only and hence cannot be·
generally rewritten. However, some PROM (Programmable ROM) can be rewritten.

'i

987

'II

CHAPTER 1 DEFINITION OF DRAM

1.2 DRAM Features

The DRAM has the following features:
(11 Memo.rv cell structure = 1 transistor + 1 ~«i~~r:
(21 Refreshing r e q u i r e d - - - = -

T

Large density easily provided

(31 Address multiplex method - - - - - - - - - - - '

The following explains the features (1) to (3) of DRAM in comparison with the SRAM.

(11

Memory cell structure

The memory cell stores one-bit data. One 16M DRAM has 16,777,216 (224) memory cells. Figure 1-2 shows
the memory cell structure of DRAM and SRAM.
The DRAM memory cell consists of one transistor and one capacitor and hence is highly integrated as
compared with the SRAM in 6-transistor configuration.
The SRAM memory cell consists of flip-flops (in 6-transistor configuration) and does not use any capacitors.

Figure 1·2. Memory Cell
(a) DRAM

(b) SRAM (CMOS)

Fi","M
Digit line

ICapacitor I
(21

Digit line

Digit line

I Flip-flop I

Refresh operation

The DRAM uses capacitors in memory cells and hence must be refreshed.
The electric charge accumulated in DRAM capacitors tends to discharge little by little (leak) when left as
it is. Therefore, data cannot be saved simply by providing power supply voltage.
Let us call the condition of a cell filled with electric charge as a "high level". If such a cell is left as is, the
electric charge contained in the cell will be lost through leakage and the cell will change to the low level.
The high level must always be maintained to retain data. Refreshing is the operation for constantly amplifying
electric charge to retain data.
The SRAM does not use capacitors and hence does not require refreshing.
Caution

For some cells. the condition of a cell filled with electric charge is called Mlow level n and refreshing
is also required for those cells to maintain the low level for the same reason explained above.

988

CHAPTER 1 DEFINITION OF DRAM

(3)

Address multiplex method
Figure 1-3 shows a diagram of the address multiplex method.
The address multiplex method uses two select inputs. For example, if an address line requires 20 bits, these
20 bits are read in two packets of 10 bits each. By thus reducing in half the number of address pins, high
integration and package miniaturization can be achieved.
The DRAM uses this address multiplex method. For this reason, it can be packaged more compactly than
SRAM for an equal memory density.
Although the SRAM does not use the address multiplex method, it enables easier timing design than DRAM
as data can be transferred using one select input only.

Figure '-3. Address Multiplex Method (for address line requiring 20 bits)
(a)

DRAM type (address multiplex method)
Select input 1

Select input 2

Address {AO~.A9)

(b)

SRAM type (address non-multiplex method)
Select input

Address{AO to'A19}

A comparison of DRAM features and other types of memories is shown in the table below.

Table ,-,.

~

Ie Memory Features

DRAM

SRAM

©
©

Mask ROM

EPROM

Flash Memory

©

0
6

6

©

©

6
0

0
0

Feature

Large density

Data-retention capability

6

Bit unit cost

10

6
6
0
6

Access time

0

©

Compact package

©:

excellent

0: very good

6

©
©
0

©

6: lacking

989

CHAPTER 1 DEFINITION OF DRAM

[MEMO]

990

CHAPTER 2 WORD AND BIT ORGANIZATIONS

This chapter describes word and bit organizations using an example of 16M DRAM.
The word means a memory density controlled by one data I/O pin.
The bit organization means the number of data whose I/O can be controlled at one time. The x 4-bit device has
four data I/O pins and can control I/O of four bits at one time. The x 8-bit device has eight data I/O pins and can
control I/O of 8-bit data at one time. Therefore, word x bit organization forms an entire memory density.
For example, the memory density of 4M words x 1 bit is 4M bits and that of 4M words x 4 bits is 16M bits. The
word x bit organization may be different for the same memory density.
The word and bit organization may be called depth and width, respectively, when Figure 2-1 is viewed from the
side.

Figure 2-1. Simplified Block Diagram
16M DRAM (x 4-bit device)
(4M-word x 4-bitl

16M DRAM (x 8·bit device)
(2 M·word

x a-bit)

Data I/O pins

When a certain address is defined, 4-bit and 8-bit data are selected for x 4-bit and x-8 bit organizations, respectively.
Therefore, if there are address pins available for defining all words (x 4-bit device: 4M bits, x 8-bit device: 2M bits),
the data of all addresses of memory can be selected.

Table 2-1. Number of Memory Cells and Number of Address Pins

~s

DRAM type

Yaxis

X axis
Number of memory cells

Number of address pins

Number of memory cells

Number of address pins

16M DRAM (x 4-bit device)

4K

12

1K

10

16M DRAM (x 8-bit device)

4K

12

512

9

Because the DRAM uses the address multiplex method, the number of address pins is 12 for both DRAMs in
x 4-bit and x 8-bit organizations.

991

CHAPTER 2 WORD AND BIT ORGANIZATIONS

[MEMO]

992

CHAPTER 3 PIN FUNCTIONS

This chapter describes DRAM pin functions based on the .uPD42161 00 (16M-word x 1-bit device) and .uPD4216400
14M-word x 4-bit device).

3_1 Pin Configurations
(a) .uPD4216100LA

(b) .uPD4216400LA

(26-pin Plastic SOJ (300 mil))

(26-pin Plastic SOJ (300 mil))

Vee
DrN
NC
WE

RAS
A11
A10
AO
A1

A2
A3
Vee

4
5
6
S
9
10
11
12
13

"l::

~

C

~

'"g
r-

Jo

Vee

GND
Dour
NC
CAS
NC
A9

1/01
1/02
WE
RAS
A11

AS
A7
A6
A5
A4
GND

A10
AO
A1
A2
A3

Vee

GND
1/04
1/03
CAS

i5E
A9
AS
A7
A6
A5
A4
GND

3:2 Pin Functions (common to ~D4216100 and ~D4216400)
Pin name

I/O

Pin functions

RAS : Row Address Strobe

In

Signal that activates chip and fetches row address

CAS: Column Address Strobe

In

Signal that fetches column address

WE : Write Enable

In

Signal enabling write

Vee: Power Supply
GND: Ground

-

Ground pin

AO-A 11 : Address

In

Address input pin

DIN : Data Input

In

Data input pin

DoUT : Data Output

Out

Remark

Power supply voltage pin

.uPD4216100 only _

Data output pin

OE : Output Enable

In

Signal enabling output

1/01-1/04 : Data Inputs/Outputs

I/O

Data I/O pin

NC : No Connection

-

Not connected to internal memory

.uPD4216400 only

I
I~

Ii

Ii

I

il
.1
993

l~
It

CHAPTER 3 PIN FUNCTIONS

3.3 Pin Function Explanation
The pin functions of RAS, CAS, WE, and OE are explained below.
3.3.1 RAS: Row address strobe
This is a signal that activates chips. When the RAS is activated, DRAM operation begins. When the RAS is
activated, a row address is latched, the corresponding word line is selected, and the sense amplifier circuit is
activated.
The sense amplifier circuit is used to amplify signals in the capacitor.
The RAS is activated when it is low. The" - " (bar) indicates that this signal is activated when it is low.
3.3.2 CAS: Column address strobe
This signal fetches a column address, selects the digit line connected to the sense amplifier, and activates the
data 1/0 circuit.
3.3.3 WE: Write enable
When RAS, CAS, and WE are activated, write operation is enabled. Write operation is divided into two major
groups.
• Early write : WE is activated before or at the same time CAS is activated.
• Late write : WE is activated after CAS is activated.
3.3.4 OE: Output enable
This signal is used to switch between data input and output (for devices with multiple-bit organization only). The
DRAM is divided as shown in Table 3-1 depending on the word and bit organization.

---

Table 3-1. DRAM Word x Bit Organization

xl-bit device

Multiple-bit device

4M DRAM

16M DRAM

4Mx1
1 Mx4,512Kx8,

16 M x 1
4 M x4, 2 M xB,

256 K x 16 etc.

1M

x 16 etc.

In multiple-bit devices, the I/O pin serve both as the input and output pins and therefore 1/0 switching signal (=OE
signal) is required. In x 1-bit devices, OE is not required because the data input pins and data output pins are separate.
The data 1/0 pins used for multiple-bit devices and x l-bit devices are shown in Table 3-2.

--

Table 3-2. Data 1/0 Pins

Input pin

x 1-bit device
DIN

Output pin

DouT

Note n = 4

: x 4-bit device

=B

: x 8-bit device

= 16 : x 16-bit device

994

Multiple-bit device
1/01-I/On Note

.'

II

CHAPTER 3 PIN FUNCTIONS

I,"

In multiple-bit devices, read operation is enabled when DE and then RAS and CAS are activated. At this time,
when WE is activated, DE changes to 'don't care' in the memory and read operation is disabled. Therefore, read!
write operation is enabled only through the control of WE, with DE held active.
Remark

In the read modify write cycle, data are output and input once each in one cycle. For details, see 4,3 Read
Modify Write Cycle.

I
I

11

Il

- I

CHAPTER 3 PIN FUNCTIONS

3.4 Block Diagram
The following two types of DRAM block diagrams are shown.
JlPD42S16160 (1 M-word x 16-bit. 4,096 refresh)
JlPD42S18160 (1 M-word x 16-bit. 1,024 refresh)

Figure 3-1. Block Diagram

996

(a)

jlPD42S16160 (1M-word x 16-bit, 4,096 refresh)

(b)

jlPD42S18160 (1M-word x 16-bit, 1,024 refresh)

CHAPTER 3 PIN FUNCTIONS

3.4.1

Block diagram explanation

The block diagram is explained below.

il
"

111

When RAS is activated:
When RAS is activated, the signal travels to the row decoder, latches a row address, selects the
corresponding word line, and activates the sense amplifier. The RAS also enables activation of CAS (Signal
priority is: RAS>CAS>WE>OE).

:

I~

(21

When CAS is activated:

:1

When CAS is activated, the signal travels to the column decoder, latches a column address, selects the

,I

corresponding digit line, and enables data I/O. The CAS also enables activation of WE and OE.

1/

The UCAS and LCAS control the upper and lower bytes, respectively, thus achieving control in units of bytes
(See CHAPTER 8 BYTE CONTROL).
Also, when the CAS is activated before RAS, the CAS before RAS counter is activated, thus automatically
generating a row address.

(31

When WE is activated:
When WE is activated, data are input.

(41

When OE is activated:
When OE is activated and WE is inactivated, data are output.

I

I
1,1

:!

11

ij

I1

I

I
II

007

CHAPTER 3 PIN FUNCTIONS

[MEMO)

998

CHAPTER 4 OPERATION MODES

Operation modes can be generally divided into read and write. Read consists in extracting effective data from
memory and write consists in inputting effective data into memory.
In this manual, a series of operations required for read operations is called read cycle and a series of operations
for write operations is called write cycle. Before each operation mode is explained, legends used in timing charts
are provided in Table 4-1.
Signal names listed higher in timing charts have precedence over ones listed lower (RAS > CAS> WE > DE).
If WE is low, OE is "don't care" in memory.

Table 4-1. Legend
Notation

Meaning
Low or high level can be input and level can be changed from high to low or vice versa at any

lOOOOO

time.
Input of undefined levels (neither high nor low) is prohibited.

\\\\\
/JJl

High level can be input and level can be changed from high to low at any time. However, lowto-high transition is prohibited.
Low level can be input and level can be changed from low to high at any time. However, highto-low transition is prohibited.

Don't care

Signals of air levels can be input. (Low, high, and undefined levels)

Hi-Z

The output state is neither high nor low level.

(High Impedance)

11

Ii

.1

I

i

II

-

j

CHAPTER 4

OPERATION MODES

4.1 Read Operation
4.1.1 Read cycle
Read cycle is executed by activating RAS and then CAS while WE is not activated and OE is activated. The RAS
latches row addresses and CAS latches column addresses.
Figure 4-1 shows the timing chart for the read cycle.

Figure 4-1. Read Cycle

"

1/0

• - - - _- -_ - - - - - - ____ };!i:L ____ - _- - _______________ _

<1> Defines row address.

RAS

Active

<2> Activates RAS to latch row address.

CAS

Active

<3> Inactivates WE to select read mode.

WE

Inactive

<4> Defines column address.

OE

Active

<5> Activates CAS to latch column address.

I/O

Output

<6> Activates OE to enable output buffer.
<7> Start of data output.

1000

Data out

_!;il·L

CHAPTER 4 OPERATION MODES

4.1.2 Accesstime
The effective access time in the read cycle varies depending on the conditions as shown in Table 4-2.

Table 4-2. Access Time in Read Cycle
"

Input Conditions

s tRAO (MAX.I and tRCO S tRCO (MAX.I tRAC (MAX.I
tRAO > tRAO (MAX.I and tRCO s; tRCO {MAX.I tAA (MAX.I

tRAC {MAX.I

(2)
(3)

tRCO > tRCO (MAX.I

tRCO + tCAC (MAX.I

(1)

tRAO

tCAC (MAX.!

,,~.

Access Time from RAS

Access Time

tRAO + tAA (MAX.I

The tRAO (MAX.I and tRCO (MAX.I are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA, or tCAC) is to be used for finding out when output data will
be available. Therefore, the input conditions tRAO ~ tRAO (MAX.I and tRCO ~ tRCO (MAX.I will not cause any operation problems.
Assuming that the specification is as shown in Table 4-3, an example for Table 4-2 is shown below.

Table 4-3. Specification of a Certain Device (for read cycle)

---

MIN.

MAX.

Unit

tRAO

12

30

ns

tRCO

14

45

tRAC

-

60

tAA

tCAC

(1)

30
15

When tRAc becomes valid IRAS access):

Address

VO

Remark

_______ t:ll-~_ ••••••••••••••••••••••••••••••••••

WE: inactive, OE: active

When tRAO is equal to 30 ns and tRCO is equal to 45 ns, tRAC becomes valid. Data are output in 60 ns after
the RAS is activated.

1001

CHAPTER 4

(2)

OPERATION MODES

When tAA becomes valid (address access):

Remark

WE: inactive, OE: active

When tRAO is equal to 31 ns (tRAO > tRAO IMAX.I) and tRCO is equal to 45 ns, tAA becomes valid.
Therefore, data are output in 61 ns after RAS is activated.
The access time from RAS becomes (tRAO + tAA) and is delayed from RAS access.
(3)

When

tCAC

becomes valid (CAS access):

Address

1/0

Remark

- - - -- - - tll-~_ --- --- ------ -- -- -- ------- --- --- ---

~1I..-";;";;';'~;.....J

WE: inactive, OE: active

The tCAC becomes valid regardless of the value of tRAO when tACO is equal to 46 ns (tACO> tRCO IMAX.I) (the
value of tAAO IMIN.land address setup time need to be observed).
Therefore, data are output in 61 ns after RAS is activated.
The access time from RAS becomes (tRCO + tCAC) and is delayed from RAS access.

1002

CHAPTER 4 OPERATION MODES

4.2 Write Operation
Write operation is enabled by activating RAS, CAS, and WE.
4.2.1 Early write cycle

The early write cycle is executed by activating WE before or at the same time when CAS is activated.

Figure 4-2. Early Write Cycle

.....-<2>

Address

I/O

Remark

OE: don't care
<1> Defines row address.

RAS

Active

<2> Activates RAS to latch row address.

CAS

Active

WE

Active

<4> Defines column address.

OE

Don't care

<5> Activates CAS to latch column address.

I/O

Input

<3> Activates

WE to enable input buffer.

<6> Sets input data.

1003

CHAPTER 4 OPERATION MODES

4.2.2 Late write cycle
The late write cycle is executed by activating WE after activating CAS.

Figure 4-3. Late Write Cycle

....-<2>

Address

1/0

7\J\J\
Hi-Z
~-- •••• - •• - ••••

<1> Defines row address.

RAS

Active

<2> Activates RAS to latch row address.

CAS

Active

<3> Defines column address.

WE

Active

<4> Activates CAS to latch column address.

OE

Don't care

<5> Inactivates OE to select write mode.

I/O

Input

<6> Activates WE to enable input buffer.
<7> Sets input data.

1004

Data in

CHAPTER 4 OPERATION MODES

4.3 Read Modify Write Cycle
Read modify write cycle is a cycle that outputs and inputs data from/to the same address during one cycle (RAS/
CAS cycle). Write is enabled by activating WE while RAS and CAS are active. Read is enabled by activating OE while
RAS and CAS are active. Because x 1-bit devices do not have OE, write and read operations are controlled by activating
or inactivating WE.
The timing charts of the read modify write cycles of x 1-bit and multiple-bit devices are shown in Figure 4-4 and
Figure 4-5, respectively. In either case, if WE is activated after a delay from CAS that exceeds CAS-WE delay time
(tcwD IMIN.I), the read modify write operation is enabled.

Figure 4-4. Read Modify Write Cycle of x1-Bit Device

....-<2>

Address

DoUT ._____________ J:ll-:f_____ •••••• _.

Data out

<1> Defines row address.

RAS

Active

<2> Activates RAS to latch row address.

CAS

Active

<3> Defines column address.

WE

Inactive

<4> Activates CAS to latch column address.

DATA

o.utput

I Active
I Input

<5> Inactivates WE to enable output buffer.
<6> Start of data output.
<7> Activates WE to enable input buffer.
<8> Sets input data.

1005

CHAPTER 4 OPERATION MODES

Figure 4-5. Read Modify Write Cycle of Multiple-Bit Device

Address

I/O

____ • ______ _tlJ:~_ --- --_. -----

I/O •_. -- --- ------ _lii;4, __ ___ ___ ___ _
lIWIrl\,;;,,~.;;..JC

<1> Defines row address.

RAS

Active

<2> Activates RAS to latch row address.

CAS

Active

<3> Defines column address.

WE

Inactive

Active

<4> Activates CAS to latch column address.

OE

Active

<5> Activates OE to enable output buffer.

I/O

Output

Don't care
Input

<6> Start of data output.
<7> Activates WE to enable input buffer.
<8> Sets input data.

1006

CHAPTER 4 OPERATION MODES

4.4 Page Mode
4.4.1

Fast page mode (FPM)

In the fast page mode (FPMl. column addresses are latched by repeatedly activating and inactivating CAS after
RAS has been activated and the row address has been latched. This mode is available for read/write or read modify

:r

i,j

write operations and allows the simultaneous use of read and write operations.

!

Taking the read operation as an example, during normal read operations, data can be output only once during each
RAS cycle, while in the fast page mode, data can be output repeatedly. For this reason, during read operation in

:1

the fast page mode, the access time of the data output first (data output 1) is the same as the access time of normal
read cycles, but the access time of the second and later data output (data output 2, data output N) becomes

:1

successively faster.

!

Figure 4-6. Fast Page Mode Read Cycle

< 1>

CAS toggle operation (operation to repeat activating and inactivating)

<2> Data output 1 corresponding to column address 1
<3> Data output 2 corresponding to column address 2
<4> Data output N corresponding to column address N

1007

CHAPTER 4

OPERATION MODES

4.4.2 Access time in fast page mode
The access time in the fast page mode varies depending on the conditions shown in Table 4-4.

Table 4-4. Access Time in Fast Page Mode Read Cycle

~

Conditions

Valid access time

(1)

"lAsc ~ (tAA IMAX.I - tT - tCAC IMAX.I)

(2)

"lAsc IMIN.I

~

tCAC (MAlO

tASC < (tAA IMAX.I - tT - tCAC IMAX.I)

tAAIMAX.I

Assuming that the specification in Table 4-5, an example in Table 4-4 is shown below (tT = 5 ns).

Table 4-5. Specification of a Certain Memory (for fast page mode)

----

MIN.

MAX.

Unit

30

ns

tCAC

-

tAsc

0

-

tAA

15

Figure 4·7. CAS Access and Address Access

Address

I/O

.••••••••• .!i~L .•••.•.
(11

Remark
(1)

(21

WE: inactive, OE: active

When tCAC becomes valid (CAS access):
Data are output in 31 ns (tAsc + tr + tCAC) after the column address is defined and in 15 ns after CAS is activated.

(2)

When tAA becomes valid (address access):
Data are output in 30 ns after column address is defined and in 25 ns (tAA- tTl after CAS is activated (in the
case of "lAsc

1008

= 0 ns).

CHAPTER 4 OPERATION MODES

4.4.3 Hyper page mode (HPM)
Hyper page mode (HPM) is one type of page modes and is equivalent to EDO. The following describes main
features of hyper page mode in relation to how it differs from the fast page mode (FPM).
(1)

Data output time is extended
In hyper page mode, output data are held until the falling of the next CAS cycle rather than the rising of CAS
to extend data output time (extended data out function). In normal fast page mode, data output time is
reduced when CAS cycle time is shortened. However, in hyper page mode, the extended data out function
increases the timing margin at the reading side even if the CAS cycle time becomes shorter.

(2)

Further shortening in CAS cycle time (tltpc) as compared with fast page mode
According to (1) above, the CAS cycle time can be further shortened in the hyper page mode as compared
with the fast page mode if the timing margin at the reading side is the same. For example, the CAS cycle
time in the hyper page mode is 25 ns while that in the fast page mode is 40 ns for a device with tRAC

=60

ns.
In hyper page mode, read operation (data output) and write operation (data input) can be repeatedly executed
during one RAS cycle as in fast page mode. The read and write operations can exist at the same time with the
performance being equivalent to that of the fast page mode.

1009

CHAPTER4 OPERATION MODES

Figure 4-8. Hyper Page Mode Read Cycle
RASP

Address

~~~page

(

I/O

Fast page
mode

(

I/O

1010

.••• ttg -•.••

CHAPTER 4 OPERATION MODES

4.4.4 1/0 Hi-Z state
In page mode, when I/O is set to Hi-Z state in read cycle, valid signal specifications differ as shown below.

Figure 4-9. 1/0 Hi-Z State
(a) Fast page mode

(1)

(b) Hyper page mode

Address

Address

I/O

I/O

Fast page mode:
The tOFF and tOEZ are applied to set I/O to Hi-Z state and the faster becomes effective.

(2)

Hyper page mode:
The RAS, CAS, WE, and OE need to be controlled as follows to set I/O to Hi-Z state. Valid signal specifications
differ depending on the state of each signal.
• Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
tOFC is effective when RAS is inactivated before CAS is inactivated.
tOFR is effective when CAS is inactivated before RAS is inactivated.
• Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ...... tOEZ is effective.
• Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either tRRH or tRCH must be met ...... twEZ and twpz are effective.
• WE: inactive (in read cycle)

CAS: inactive, OE: active ...... tCHO is effective.
CAS, OE: active ...... tOCH is effective.
In short,
(A) The slower of tOFR and tOFC becomes effective.
(B) The faster of tWEZ and tOEZ becomes effective.
Please note that I/O will not become Hi-Z state even if CAS changes from active to inactive in case of hyper
page mode with RAS: active, WE: inactive and OE: active.

1011

CHAPTER 4 OPERATION MODES

4.4.5 Access time in hyper page mode
When tAA is applied in the hyper page mode, tHPC cannot be operated at the minimum value (See 4.4.2 Access

time in fast page mode for CAS access and address access).
Assuming that the specification in Table 4-6, an example in Figure 4-10 is shown below (tr = 2 ns).

Table 4-6. Specification of a Certain Memory (for hyper page mode)

----

MIN.

MAX.

Unit

tHPC

20

-

ns

tAA

25

tCAC

-

tAsc

0

tDHC

5

-

13

Figure 4-10. CAS Access and Address Access (for hyper page mode)

Address

I/O

. _____ •••• Jii:L •••••• _
(1)

Remark
(1)

(2)

WE: inactive, OE: active

When tCAC becomes valid (CAS access):
Data output time is equal to 10 ns when tHPC is set to the minimum value.
Data output time: (tHPC - tr - tCAC) + tOHC

(2)

= (20 -

2 - 13) + 5

= 10 ns

When tAA becomes valid (address access):
Data output time is equal to 0 ns when tHPC is set to the minimum value and hence 10 ns cannot be secured.
Data output time: (tHPC - tAA) + tDHC

= (20 -

25) + 5

= 0 ns

Therefore, tHPC needs to be set to 30 ns (address access) or tAsc needs to be set to 10 ns (CAS access) to secure
10 ns data output time.

1012

CHAPTER 5 INTERNAL MEMORY OPERATION

This chapter describes the internal operation of memory devices. taking read cycles as an example.

Figure 5-1. Simplified Diagram of Internal Memory
1/2Vcc

PDL------------_4----~--~----~--_4-

(Digit line precharge signal)

Word line

------+-..,...."""==.......,....----+--

SE------------~--~~·

(Sense .amplifier drive signal)

1

Column switch
Digit line

Let us assume that the high level (= 5.0 V) is held by the capacitor in the memory cell and is to be output to the
outside of the memory (read operation). When RAS is not activated. PDL (digit line precharge) is activated and the
digit lines and digit lines are at half of Vce potential.
Assuming that the word line is selected with the row address. activating RAS makes PDL and the word line inactive
and active. respectively. followed by SE (sense amplifier drive) being activated with some delay time. When PDL
is inactivated. the digit lines and digit lines are separated.

CHAPTER 5

INTERNAL MEMORY OPERATION

When the word line is activated, the transistor Ns) is turned on, transferring electric charges in the capacitor (Cs)
to the digit line. Then, the potential of the digit line becomes 1/2 Vee +

0:,

resulting in some voltage difference (=0:)

between the digit lines and digit lines. The difference is amplified by the sense amplifier to 5.0 V and 0 V. When
the capacitor (Cs) holds the low level (= 0 V). the reverse operation is performed (i.e., Digit line = 1/2 Vee Digit lines

= 1/2 Vee.

0:

and

The potential difference is amplified). The column switch is controlled with CAS.

When CAS is inactivated, the column switch is inactivated. When

RAS is inactivated, the transistor (Vs) is turned

off, SE is inactivated, and PDL is activated. The digit lines and digit lines amplified by the sense amplifier to 5.0 V
and 0 V gradually reach 1/2 Vec.
The time it takes for the digit lines and digit lines to change from 5.0 V and 0 V to 1/2 Vee at this time is the RAS
precharge time (tRP). When the RAS precharge time runs short, the sense amplifier may malfunction because the
next operation (the transistor (Vs) is turned on) is made without causing the digit lines and digit lines to reach 1/2
Vee.
Digit lines are connected to the transistors at the output stage. The transistors are controlled with OE (WE in
write operation) .
• When Tr1 = ON and Tr2 = OFF, the high level is output.
• When Tr1

= OFF and Tr2 = ON, the low level is output.
Figure 5-2. Simplified Diagram of Memory Output Stage

Inside memory

Digit line

----r--+----i

Digit line

--"""T-t-+---;

Vee

Outside memory

I/O

1014

CHAPTER 6 REFRESH

This chapter describes the refresh operation, taking the tLPD42S16160 (1 M words x 16 bits) as an example.

6.1 Refresh Cycles and Distributed/Burst Refresh
The refresh cycle of the tLPD42S16160 is 4,096/128 ms.
This expression means that 4,096 refresh cycles are required during each 128 ms interval. The requirement should
be strictly observed, otherwise data stored in memory may be destroyed.
Refresh can be executed in two ways.

(1)

Distributed refresh:
Refresh cycles are executed at intervals. In the case of the tLPD42S16160, refresh cycles are executed every
31.3 tLS (128 ms/4,096).

(2)

Burst refresh:
Refresh cycles are executed in succession. In the case of the tLPD42S16160. 4,096 refresh cycles are
executed in succession.

6.2 Refresh Types
Refresh can be categorized into two main types and further into five sub-types as shown below.

Figure 6-1. Refresh Types
CAS before RAS refresh (CBR refresh)

CAS before RAS long refresh (CBR long refresh)

CAS before RAS self refresh (CBR self refresh)
Refresh
RAS only refresh (ROR)

Long RAS only refresh (Long ROR)

In normal (read/write) mode. CBR refreSh. CBR long refresh. ROR, or long ROR are generally used; in data retain
(with battery backup) mode. CBR self refresh is generally used.

1015

CHAPTER 6 REFRESH

6.3 Refresh Operation
This section describes refreshes used for DRAM. The control method for these refreshes and refresh cycle ratings
are shown in Tables 6-1 and 6-2.
(1)

CBR refresh:
Refresh is executed with (memory) external clock and (memory) internal address signals. In this case, the
refresh cycle rating is 4,096/64 ms.
Addresses are generated by an internal counter which counts automatically. Therefore, 4,096 different
addresses are generated automatically.

(2)

CBR long refresh:
Refresh is executed with external clock and internal address signals. In this case, the refresh cycle rating
is 4,096/128 ms. Compared with the CBR refresh (64 ms). the refresh period is longer (128 ms). Therefore,
the number of refresh times per time interval is smaller than in the case of the CBR refresh, resulting in
lower power consumption (lower average current consumption per time interval).

(3)

ROR and long ROR:
Refresh is executed with external clock and external address signals. In this case, the refresh cycle rating
is4,096/64 ms (4,096/128 ms for long ROR). 4,096 different addresses must be created outside the memory.

(4)

CBR self refresh:
Refresh is executed with internal clock and internal address signals. Memory executes refresh automatically
.under control of the internal clock (no refresh cycle). Therefore, CBR self refresh cannot be used when read
and write operations are executed together and cannot be controlled externally .
. Memories that can assure CBR self refresh can also assure CBR refresh, CBR long refresh, ROR, and long
ROR.

1016

CHAPTER 6

REFRESH

Table 6-1. Refresh Control Methods

~

CBR refresh

Clock

Address

External Clock

Internal Address

External Clock

External Address

Internal Clock

Internal Address

CBR long refresh
ROR
Long ROR
CBR self refresh

Table 6-2. Refresh Cycle Ratings

------

Refresh cycle
CBR refresh

CBR long refresh
ROR
Long ROR
CBR self refresh
Remark

DRAM with self refresh DRAM without self refresh
4,096/128 ms

4,096/64 ms

0
0
0
0
0

0
X

0
X
X

0: Assured, X: Not assured

1017

CHAPTER 6 REFRESH

6.4 CBR Refresh, CBR Long Refresh Cycle
By activating RAS after CAS has been activated, the internal counter is activated and a row address is generated
automatically. One row address is refreshed through this operation (in Figure 6-2, refresh is executed twice).
Refresh is executed with the external clock and internal address signals.

Figure 6-2. CBR Refresh Cycle

(CAS activated before Ris )
Remark

Address, WE, OE: don't care

I/O: Hi-Z

Although the refresh period for the CBR long refresh cycle is longer than that of the CBR refresh cycle, its operation
is exactly the same.

1018

CHAPTER. REFRESH

6.5 ROR and Long ROR Cycles
After RAS has been activated, the row address is latched and refresh is executed. Through this operation, refresh
is completed for one row address.

Figure 6-3. ROR Cycle

Remark

WE, OE: don't care

I/O: Hi-Z

Although the refresh period forthe long ROR refresh cycle is longer than thatofthe ROR refresh cycle, its operation
is exactly the same.

1019

CHAPTER 6 REFRESH

6.6 CBR Self Refresh Cycle
6.6.1

Executing CBR self refresh

In the same way as for the CBR refresh cycle, after activating CAS, activate RAS. By keeping RAS activated for
a set period (tRASS IMIN.I = 100 JJS) or longer, the internal clock and the internal counter are activated and the memory
repeatedly refreshes itself.

Figure 6-4. CBR Self Refresh Cycle

( Hold for set period or longer)

Remark

1020

Address, WE, DE: don't care

liD: Hi-Z

CHAPTER 6

REFRESH

6.6.2 Cautions on use of CBR self refresh
CBR self refresh can be used independently when used in combination with distributAd CBR long refresh;
However, used in combination with burst CBR long refresh or with long ROR (both distributed and burst), the following
cautions must be observed (For information on distributed and burst refresh, see 6.1 Refresh Cycles and Dis·

tributed/Burst Refresh). The p,PD42S16160 is used in the following example.
111

Normal Combined Use of CBR Self Refresh and Burst CBR Long Refresh

I

Let us assume that CBR long refresh is used as shown in Figure 6·5. The RAS must be kept activated (=
tRASS) for 100 p,s or longer to execute CBR self refresh (See 6.6.1 Executing CBR seH refresh).

j

1

In the CBR self refresh, it is not known how many seconds are required to refresh all memory cells.

"

,~
,~

Therefore, if the CBR self refresh is stopped without refreshing all memory cells, an inactive period of up
to approximately 2 tREF occurs, the tREF (= refresh time) requirement cannot be satisfied and data may be
destroyed.
To prevent this from occurring, normally, when CBR self refresh and burst CBR long refresh are used in
combination, execute CBR refresh for 4,096 times within 64 ms just before and after setting CBR self
refresh. Through this CBR refresh, the period when any refresh is not executed will be within the tREF
requirement.

Figure 6-5. Example of Burst CBR Refresh Use

(

Burst CBR long
refresh (128 msl

4,096 x tRc

NCH'efresh period (tRASS <: 100,usl

)

Burst CBR long
refresh 1128 msl

4,096 x tRc

1021

CHAPTER 6 REFRESH

(2)

Normal Combined Use of CBR Self Refresh and Burst Long ROR
The address control method for ROR and CBR refresh differ (ROR: Control from outside memory; CBR
refresh: Control from inside memory).
Let us suppose that refresh is executed in the subsequence word line 1 (W1) to word line 2 (W2) with ROR.
When refresh has been executed up to word line 4,095 (W4,095), CBR self refresh begins. At this time,
if the internal counter (it cannot be controlled from the outside) happens to be set at word line 1 (W1), the
refresh operation is executed in the subsequence .word line 1 (W1) to word line 2 (W2). Under these
conditions, an inactive period of up to approximately 2 tREF occurs for the word line 4,096 (W4,096) (See
CHAPTER 5 INTERNAL MEMORY OPERATION and 6.8 Internal Memory Operation During Refresh).
Execute ROR 4,096 times within an interval of 64 ms or less just before entering or exiting CBR self refresh
to satisfy the tREF requirement.

Figure 6-6. Example of ROR Use
Wl W2 W3

... W4,095

III
ROR - - - - - -

I

W4,096

cl/

CBR self refresh - - - - - - - - - -

Remark

1022

W: Word line

W4,096 was skipped for
one refresh operation.

CHAPTER 6 REFRESH

6.7 Hidden Refresh Cycle
If CBR refresh cycle is.started after a read/write cycle or read modify write cycle operation. it is possible to enter
CBR refresh cycle with CAS activated.
Hidden refresh read cycle is shown in Figure 6-7 as an example.

Figure 6-7. Hidden Refresh Read Cycle

i

I~

:1I

!~

1023

I

CHAPTER 6 REFRESH

6.8 Internal Memory Operation During Refresh
This section explains how the memory operates during refresh using Figure 6-8 as an example.
As explained in CHAPTER 5 INTERNAL MEMORY OPERATION. when RAS is activated. a word line is selected
and activated. The charge in the memory cell connected with this word line is transmitted to the digit line. The signal
voltage difference generated at this time is amplified by the sense amplifier. Refresh consists of the above sequence
of actions.

Figure 6-8. Simplified Circuit Diagram of 16-bit DRAM
Digit line balancer

Word line
Memory cell

Digit line

Sense amplifier

Row
address 1-_4--"
latch
circuit

Address input
AO -"'-1r--o~+I-+-..j
Al~~~--~--~

circuit
Low Hi

Figure 6-8 shows 16-bit DRAM (DRAM with 16 memory cells).
Let us suppose that the high level and the low level are input to the addresses AO and A 1. respectively. to select
the word line (W2) while the high level is retained for all memory cells. Then. the IC-2 becomes the high level. the
word line 2 (W2) is selected and activated. and all memory cells connected to it are refreshed (Because the output
of the IC-6 is also at the high level. the column switch connected to the digit line 2 (D2. D2) is activated. However.
because the column address latch circuit is inactivated by refresh. all column switches are off.). Therefore. all memory
cells are refreshed by selecting all word lines.
In a memory device with 4.096/128 ms refresh cycle. execution of read/write cycle at 4.096 different kinds of
addresses is equivalent to refresh.

1024

CHAPTER 6 REFRESH

6.8.1 Not cell and true cell
Even if data within a memory cell are read after refresh fails and all data are destroyed, they are not always at
the low level. The following provides an any explanation.
There are two types of memory cells, namely Not cell and True cell.

111

Not Cell
The Not cell causes the data retention state of a memory cell to be reversed from the data input from the
outside of memory or output to the outside of memory.
In Figure 6-8, when the output of the IC-2 and IC-6 reaches the high level. the column switches connected
to the word line 2 (W2) and digit lines 2 (02, 02) becomes active, and digit line and digit line become the
low level and high level. respectively. For read operation, the output of IC-1 0 becomes the high level, the
transistor at the ground side is turned on, and hence a low-level signal is output from DouT although the
memory cell retains the high level because WE is inactive and OE is active.
Therefore, the output becomes the low level when the Not cell retains the high level at the memory cell
and the high level when it retains the low level. The same applies to write operation. When a low level
signal is input, the memory cell retains the high level. On the other hand, when the high level is input, it
retains the low level.

(2)

True Cell
The True cell causes the data retention state of a memory cell to be equal to the data input from the outside
of memory or output to the outside of memory. The True cell causes the output to be the high level when
the high level is retained at the memory cell and to be the low level when the low level is retained. The
same applies to write operation.

In Figure 6-8, the memory cell connected to the word lines 2 and 4 (W2, W4) is Not cell and that connected to
the word lines 1 and 3 (W1, W3) is True cell. The following table summarizes the I/O data state and data retention
state of memory cell of Not and True cells.

Table 6-3. I/O Data State and Memory Cell Data Retention State

--------

Not Cell

True Cell

I/O Data State

Data Retention State
of Memory Cell

High level

Low level

Low level

High level

High level

High level

Low level

Low level

According to the above, even if data are destroyed without observing refresh cycle (tREF) and electric charge is
lost from the memory cell, the data output from the inside of the memory is not always at the low level. Also, the
high level cannot always be retained even if a high level signal is input from the outside of memory to all memory
cells.
The above is designed to minimize the interference between adjacent memory cells. In an actual device, the True
and Not cells are aligned carefully, namely the True and Not cells are not always aligned alternately. See CHAPTER

5 INTERNAL MEMORY OPERATION for basic internal memory operation.

1025

CHAPTER 6 REFRESH

6.9 DRAM Refresh Cycles
Various DRAM refresh cycles are shown in the table below.

Table 6-4. Various DRAM Refresh Cycles
Density Bit Organization
1M

x 1

DRAM with Self Refresh Function

DRAM without Self Refresh Function

---

512/8 ms

1,024/128 ms

1,024/16 ms

x4
4M

x 1
x4
x8

16 M

x16

512/128 ms

512/8 ms

x 1

4,096/128 ms

4,096/64 ms

x4

2,048/128 ms

2,048/32 ms

4,096/128 ms

4,096/64 ms

1,024/128 ms

1,024/32 ms

x8
x16

1026

CHAPTER 7 TEST MODE

By using the test mode, the test time can be reduced. The reason for this is that. in the case of 16M DRAM for
example, the memory emulates the x 16-bit organization during test mode (In the case of 4M DRAM, the memory
emulates the x a-bit organization).

Figure 7-1. Test Mode Set Cycle (WE, CBR Refresh Cycle)

Remark
(1)

Address, OE: don't-care

I/O: Hi-Z

Setting the mode
Executing the test mode cycle (WE, CBR refresh cycle) sets the test mode.

(2)

Writelread operation
When either a "0" or a "1" is written to the input pin in test mode, in the case of 16M DRAM, the data
are written to 16 bits of memory cell and in the case of 4M DRAM, the data is written to a bits of memory
cell (independent data can be written to any input pin). The case of 16M DRAM is illustrated in the example
below.
Write Operation during Test Mode for 16M DRAM
• x 1-bit devices: "0" or "1" input from DIN is written sequentially to all 16 bits of memory cells.
• x 4-bit devices: "0" or "1" input from 1/01-1/04 is written sequentially to all16 bits of memory cells

Ii

in four-bit units.

II
Next, when the data are read from the output pin at the same address, the memory cell can be checked.

:1

Output = "1 ": Normal write (all memory cells)
Output = "0": Abnormal write

(3)

Refresh

I!

Refresh in the test mode must be performed with read/write cycle (See 6.8 Internal Memory Operation

,j

During Refresh) or with the WE, CBR refresh cycle. The WE, CBR refresh cycle use the same counter as

:,1

'~

the CBR refresh's internal counter (See 6.3 Refresh Operation).

1,1
'·1

(4)

1"\

Mode Cancellation
The test mode is canceled by executing one cycle of ROR cycle or CBR refresh cycle.

1027

CHAPTER 7 TEST MODE

[MEMO]

1028

CHAPTER 8 BYTE CONTROL

Concerning DRAMs with x 16 bits or more, controlling I/O data in byte (8 bits) units is called byte control.
The byte control mode can be used for read, write, or read modify write operation.

8.1 Byte Read/Write Mode
It is possible to read and write in byte units. Byte control is executed by the following two CASso
• LCAS (LOWER CAS) : Controls read/write operations for 1/01 to 1108 (Lower I/O) .
• UCAS (UPPER CAS) : Controls read/write operations for 1/09 to 1/016 (Upper I/O).
Figures 8-1 and 8-2 show examples controlled by LCAS and UCAS, respectively.

Figure 8-1. Upper Byte Read Cycle

Remark

LOWER I/O: Hi-Z

1029

CHAPTER 8 BYTE CONTROL

Figure B-2. LQwer Byte Read Cycle

Address

LOWER 1/0

Remark

1030

•••••••••••••••••• .':!i:~.........................

UPPER VO: Hi·Z

~'lI-"';;';;";;"";'';;';''''4

.tli·~..

CHAPTER 8 BYTE CONTROL

8.2 Page Mode of Byte Read/Write Mode
In the page mode, there are the following four types of control methods of I/O data according to the toggle
operation (repeated operation of activation/inactivation) of CAS signal.

Table 8-1. Method for Controlling Byte Read/Write Mode

~

(1)

UCAS

LCAS

(1 )

Toggle operation

Inactive

I/O Data Control
8 bits

(2)

Inactive

Toggle operation

8 bits

(3)

Toggle operation

Toggle operation

16 bits

(4)

Toggle operation

Toggle operation

8 bits

UPPER 1/0 Control

The UCAS is toggled while LCAS is inactive to control the UPPER I/O 8-bit data.

(2)

LOWER 1/0 Control

The LCAS is toggled while UCAS is inactive to control the LOWER I/O 8-bit data.

1031

CHAPTER 8

(3)

BYTE CONTROL

All I/O Control

The UCAS and LCAS are toggled simultaneously to control UPPER 1/0 and LOWER 1/0 (aliI/Os) 16-bit data.

(4)

Mixed Control of UPPER I/O and LOWER I/O

The UCAS and LCAS are toggled ih a mix to control each 8-bit data of UPPER I/O and LOWER I/O (No alternate
control is required),

Remark

In the page mode, read, write, and read modify write can be used in a mix by continuing CAS signal during
the same RAS cycle.

1032

CHAPTER 9 INITIALIZING

After turning on, the state of internal DRAM circuits is not known. It is therefore necessary to initialize them to
ensure normal operation.
When turning on power, allow a 1OO-JlS or longer pause (RAS signal inactive) and then be sure to execute eight

;i

or more ROR or CBR refresh cycles as dummy cycles to initialize the internal circuits.

Figure 9-1. Initializing
4.5-5.5

v···················· ....".. - - - - - - - - - - - - - -

Power supply
voltage

Pause of 100.us
or longer
(AAS signal inactivel

Dummy cycle of

8 cycle or more

Guaranteed
operation
period

Input signal

Remark

This dummy cycle of 8 cycles or more is just a dummy cycle and does not guarantee refresh operation.

Unless initializing is executed accurately, the memory may not operate properly even during guaranteed operation
p.eriod.

1033

CHAPTER. INmALIZING

[MEMO]

1034

CHAPTER 10 LOW VOLTAGE OPERATION

DRAM are divided into 5.Q-Voperation devices and low-voltage operation devices. The main differences between
5.Q-V and low-voltage operation devices are shown in Table 10-1 using 16M DRAM (X 16-bit device) as an example.

Table 10-1. Main Differences between 5.o-V and Low-Voltage Operation Devices
5.Q-V Operation Devices

Low-voltage Operation Devices

Part number

JlPD42S 16160-60

JlPD42S16160L-A60

Power supply voltage

5.0V± 10 %

3.3 V ± 0.3 V

(4.5 V to 5.5 V)

(3.0 V to 3.6 V)

= 2.4 V to Vee + 1.0 V
V,L =-1.0 V to +0.8 V
VOH = 2.4 VNOL = 0.4 V

V,H = 2.0 V to Vee + 0.3 V

Operating current

100 mA

90 mA

CBR self refresh current

250 JlA

150 JlA

Input voltage
Output voltage

V,H

V,L

=-0.3 V to +0.8 V
= 0.4 V

VOH = 2.4 VNOL

(data-retention current)
Pin configuration

Same

The 5.0-V operation devices of 16M DRAM all adopt an internal voltage-drop circuit. The internal voltage-drop
circuit causes the power supply voltage (5.0 V) supplied to the memory externally to be dropped inside the memory
and 5.0-V operation devices also operate on 3.3 V inside the memory. Therefore, there is almost no difference
between the current consumption of the 5.Q-V operation device and that of the low-voltage operation device. The
low-voltage operation device of 16M DRAM does not adopt any internal voltage-drop circuit.
I

I
I

:.,I
IJ

!

1035

CHAPTER 10 LOW VOLTAGE OPERATION

[MEMO]

1036

CHAPTER 11 CURRENT CONSUMPTION CALCULATION

The following examples explains an approximate current consumption calculation according to timing.

111

Example 1

"

.,i

.1
RAS/CAS operation

Standby

i

Refresh operation

I

'j

,J

In the example 1, after RAS/CAS operation (read, write, or read modify write cycle) is executed first, refresh

(ROR) is executed. When the RAS precharge time (tRPIMIN.I) exceeds the specification (tR > TRPIMIN.)), standby
current is applied.

(2)

Example 2

operation

Page mode

RAS/CAS
operation

---,
tRPtMN.1

The example 2 executes the page mode. In the first CAS cycle, RAS/CAS operation is applied and the page
mode is applied from the second CAS cycle or thereafter. The RAS precharge time (tRP IMIN.)) when the page

I~

mode ends becomes the precharge of RAS/CAS operation. Therefore, the RAS/CAS operation is obtained

11

by merging the first RAS active period and the RAS precharge period when the page mode ends.

1

l

1

I,

I",~

!

i

!!
1037

CHAPTER 11

CURRENT CONSUMPTION CALCULATION

When the timing shown in the example satisfies the conditions shown in Table 11-1 (extracted from data sheet).
each current consumption (per unit time) is added.

Table 11·1. PPD4216160 DC Characteristics
Parameter
Operating current

Symbol
Icc1

Test Condition

MIN. TYP. MAX.

RAS, CAS Cycling

tRAC = 50 ns

tRG = tRG IMIN.}

tRAC = 60 ns

to=OmA

tRAC = 70 ns
tRAC = 80 ns

Standby current
RAS only refresh current

Icc2
ICG3

RAS, CAS

~

VIH IMIN.}, 10 = 0 mA

RAS, CAS

~

Vcc - 0.2 V, 10 = 0 mA

RAS Cycling, CAS

~

VIH IMIN.}

tRG = tRG IMIN.}, 10 = 0 mA

tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns

Operating current
(Fast page mode)

Icc4

RAS ~ VIL IMAX.!, CAS Cycling
tpc = tPG IMIN.}, 10 = 0 mA

tRAC = 50 ns
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns

CAS before RAS

Iccs

refresh current

RAS Cycling

tRAC = 50 ns

tRC = tRC IMIN.!

tRAC = 60 ns

10 = 0 mA

tRAG = 70 ns

=80 ns

Unit

110
100
90
80

mA

2
1
110
100
90
80
100
90
80
70
110
100
90

mA
mA

mA

mA

Input leakage current

It ILl

VI 0 to 5.5 V
All other pins not under test = 0 V

-10

80
+10

JJ.A

Output leakage current

lo(u

Vo = 0 to 5.5 V

-10

+10

JJ.A

0.4

V
V

tRAC

=

Output is disabled (Hi-Z)
High level output voltage

VOH

Low level output voltage

VOL

10 = -2.5 mA
10 = +2.1 mA

2.4

Current consumption varies depending on operating conditions (See CHAPTER 12 MAIN DRAM CHARACTER·
ISTICS forthe details). Appendix A shows the ratio and compensation which is required for each operating condition.

1038

CHAPTER 12 MAIN DRAM CHARACTERISTICS

12.1 Current Consumption Waveform Diagram
In DRAM, as its name implies, consumption current flows more dynamically as compared with other memories.
There is actually a peak current as shown in Figure 12-1.

Figure 12-1. Current Consumption Waveform Simplified Diagram of RAS/CAS Cycle

Guaranteed value of
current consumption

c

Period

Signal State

Current Consumption

a

RAS/CAS = inactive

b

RAS/CAS =. from inactive to active or vice versa Peak current

c

RAS/CAS = inactive

Almost 0
Slight

When RAS changes from inactive to active state, the sense amplifier becomes active and hence current
consumption is maximized at that instant (peak current). The guaranteed value indicates an average current
consumption and hence the peak current may exceeds the guaranteed value.
As RAS/CAS cycle becomes longer, the average current consumption becomes smaller.

1039

CHAPTER 12

MAIN DRAM CHARACTERISTICS

12.2 Current Consumption Dependence on Power Supply Voltage
Figure 12-2. Current Consumption - Power Supply Voltage Characteristics

Large

···············70 'C

c

o

- - - O'C

"'5.
E

:J
U)

8

E

~.

:;

u

Small
Low

Power supply voltage

High

Current consumption decreases when the power supply voltage is reduced, and increases when the ambient
temperature decreases. As ambient temperature decreases, resistance decreases and internal memory operation
speeds up, resulting in increase in current consumption. The current consumption should be roughly estimated when
the power supply voltage is higher (the worst case).

12.3 Access Time Dependence on Power Supply Voltage
Figure 12-3. Access Time - Power Supply Voltage Characteristics

Slow

··············70 'C
- - - O'C

Q)

E

.'"
U)
U)

~
Fast
Low

Power supply voltage

High

The access time is slower when the power supply voltage decreases, and is faster when the ambient temperature
decreases. The access time should be roughly estimated when the power supply voltage is lower.

1040

CHAPTER 12 MAIN DRAM CHARACTERISTICS

12.4 Current Consumption Dependence on RAS Cycle
Figure 12-4. Current Consumption - Cycle Time Characteristics
Large

§

"a
E
:0

RAS pulse width

\

=fixed

1\\


tRAS = 120 ns
Vee = S.OV

;=

g; 10,

a:

..

UJ

.........

Vl

I'-..

i'-..

t--0

lOS
RAS cycle time Insl

Figure 12-12. RAS Cycle Time - SER Characteristics (3.3-V device)

,

10

tRAS = 120 ns
Vee =3.3 V

..............

I---.......
;=

---

-..........

.......... .......

g; lao
a:

UJ

Vl

,
la'
RAS cycle time Insl

Remark

The data were obtained by measurement using a sample extracted from a specific lot and do not
indicate entire characteristics (they are not the assured values). Use them only for designing
reference.

1046

APPENDIX A DRAM DATA COLLECTION

The following shows the main characteristics of DRAM using 16M DRAM as an example.
The data were obtained by measurement using a sample extracted from a specific lot and do not indicate entire
characteristics (they are not the assured values). Use them only for designing reference.
Normalization indicates the ratio of a value with a certain another value as 1.0.

A.1 Current Consumption Dependence on Power Supply Voltage
Figure A-1. Icc1-Vcc Characteristics 13.3-V device)

1.6.------,...--_-..,--_---,---....--...,

- - 0 °e, 25°C, 85 °e

,.............;............... +..............,............ +............;...............+.............;............... j
j
E

1.31----+---f----i--+-~--+-::7!"'~'----j

! ..............

i

V

+............,./"'
............·7~+·············;·············j

.~ 1.0
Q)

tRc=130ns

,

1",/

vr+·············,···············,······················......+.............;............. j
:

E0.71----;--+--+--+--...;--+--~;----;

~

.
0.4 '::------:-'-----''---~--'--__::"_:---'-----:"
2.7
3.0
3.3
3.6
3.9
•
•••
•

Power supply voltage Vee (V)

1047

APPENDIX A DRAM DATA COLLECTION

Figure A-2. Iccz-Vcc Characteristics (3.3-V device)
2.5r--"""1":--,--"""!":--""--"""'":--.,..-----r:--'
·······----·-i-·----·------

____ 0 0c, 25 oc, 85 0C

._----------+._-------._-- ---·-----·---1· .... -----·--- -------------f,···_···-----

Vi

o~ 2.0t--+---j----+----f--f---+---+---j
]

···························+···········+············1---_····-----i-------------··---_····_--- f----..... ----

E

'.5b----+----+----+----+----+----+---~----~

~

~

········V~··

.. .

.,...:--

r·o:.~~.~.~~,.~_..~.-""+..~-~:
...-...+.,.-...-...-..-...±.I~.~.~.~.~;.~~-.~.~+~..-..-.~.~.;~.~.~.~..:

...-- ____

.~

.. ..

~ 0.51"""''----;-----+----+----+----;-.----+-------:-.-----1

L. . . . . . . . . . . L. . . . . .

~

···························t············+·············I.............

o~--~--~--~--~--------~--~--~

2.7

3.0

3.3

3.6

3.9

Power supply voltage Vee (V)

Remark

Standby refers to the memory condition where no operation is possible (RAS/CAS inactive). Because,
in the case of DRAM, refresh is required for retaining data, data cannot be retained in the standby mode.

Figure A-3. 1CC3-VCC Characteristics (3.3-V device)

'.6.-----.---,...-_.--.,..--_---,.-----.
c

I ............ .;. ............ t ...........+ ............ \...........................+.............,............1 t-Re-=-'-300nos , 25 oc, 85 °C
~ '.3b----+----+----+----+-----+----+---~----~

i ..............

~

G

f"O

I '!)~

~

i

t ...........+............. \.......... r===~

.-q.. . . . ;. . . .

1':--1-"'

~
I·····
.. ~····
...:.····..

···~

+............;.............+.............,.............

~
.
.
~ 0.71----;-----+----;-----+------+----+------;-----;
§
•
~

.............;.............+.............•,............ ··1············+···········

............. ,.............

0.4'----'--...J,.-......•--.l....-..;....-~-2.7
3.0
3.3
3.6
Power supply voltage Vee (V)

1048

___- ...3.9

APPENDIX A DRAM DATA COLLECTION

Figure A-4. 1CC4-Vee Characteristics (3.3-V device)

'.5,....--_-...,..-_--.,.--_--,---_---.
:

.

- - 0 'C, 25 'C, 85'C
tpe =45 ns

~ 1.251----:----I---!---I---!---4----;---I

c

~

a 1 . 0 ,.
--I--,____
o
:...........---r
E
.............i...."'
.......-1"""··········,·············1·············.·············+·············,·············1

~

-----r

~

r·
(ij

75

.............,..........................,..........................,.............t·············,·············1

E
~ 0.51----:----t--+---I---+---+---;---I
·············i············· ..............~............. ·············i·············t··············,···············1
0.25 ......--'--....1.--------..1---'--....1.-------'

2.7

3.0

3.3

3.6

3.9

Power supply voltage Vee M

Figure A-5. Ices-Vee Characteristics (3.3-V device)
1.75.----r--r--_--r--_---r--_--,

.............L. ...................................................1.............

- - 0 'C, 25 'C, 85 'C

1.51----:----1-~--;:--+----;-i- - f - - - i - - - i
j

]

..••..••••.•• j .....••••••.••....•.....•.•, •.•.•••..••••

c

'··"·"·'··'j·············t·,···,'······!·············1

~

:; 1.251---+-----1---+---+--+---+--------;

1,.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
o

.

.

~

,

.

===~

~0.75~~············T··········· ·············i·············
N

~

E

----------.--~--.---------- -----------~----.---...-- ------- ..-.. -~---.---------. ---------.--.; .. -------- .. -

~ 0.51----:----1---;---+---;---+----;---1
j
1
1
:
········ .. ···t-------··---- .--_ ......... +..... -_ ... __..............+-_. __ .__ .... _·_-------·-,1,·---·-·_---0.25L------'---'---~----~_:__-.;....-_:"

2.7

3.0

3.3

3.6

3.9

Power supply voltage Vee M

il
'1I
'.'.1

I
1

1049

APPENDIX A DRAM DATA COLLECTION

Figure A-6. ICC6-Vee Characteristics (3.3-V device)
1.4.---,---;---;--or---r----r--..---,

]

- - 0 'C, 25 'C, 85 'C
tRC = 125 /.Is

c
~

: ./'

~

!~

/~

//

.
1.01---;.-----t---;-./--+.;'='""-+---+----t----1

1~ 7::.>-- / /

~-----------+-------------,-------------I---------------------------+------------+·-----------1

z
0.6 '::--""---::--':---'--~:---'-----:"":---'--....
2.7
3.0
3.3
3.6
3.9
Power supply voltage Vcc (V)

Figure A-7.IcC7-Vcc Characteristics (3.3-V device)

1.5.---_-.....,..-___.:-.-.,....--.--.-..,.....---.....,
;

- - 0 'C, 25 'C. 85

---------------------------+-------------,-------------,-------------;------------+--.---------,-------------1

~1.25r--+---+---+---+---+--!.-+---+-----1

~
-l1i

~

.

---------------------------+-----------+------------1------------+----------+---------------------------

I

~

~ 1.01---;.-----t---;----+~--~i~~~~~--;

13
11

1-------------;·------------j7~-------------1--------------------------,------------__- - .
!

~0.751_""=--_;_----t--_;__-_+--+_--+-___t-___1

§
o

Z

..........

--.~.- ... -....-....-.. -.-...-..~ ..... -... --.. --.-.. -.. --.. ~.-..-.. -.---.

--· .. ·_-·····t-········--_·

0.5'--""--...J...--'-_.....J._------'---'-_.....
2.7
3.0
3.3
3.6
3.9
Power supply voltage Vee (V)

1050

'c

APPENDIX A DRAM DATA COLLECTION

Figure A-S. leel-Vee Characteristics (S.O-V device)
1.5...--""---'--~--""'---;----r--;----'

i

!

]

--GOC
_._.- 25°C
··..........··85°C
tRe=130ns

E

~ 1.0~--~i----~--~i----+---~i----+---~i--~

.~

'1

!

I

•

•

:::::::;;;;:;::::;;;;;~ "".:....::::....:....:" ,;'''';:::::±~::::::::::: :::::::::::::1:::::::::::::

I

I

"c.o

.1'1

I

"0

.§ 0.5r---~----t----+----t---~----t----+--~

1 I

I

.--'-----"-----'-----"-~.--I

oL..---'-----I....4.0

4.5

5.0
5.5
Power supply voltage Vee IV)

6.0

Figure A-9. Iccz-Vee Characteristics (S.O-V device)
2.0....--.......--,--_--.,...--_._-....,.--,.......---,

I
1
•

:

i

--O°C
-'-'- 25°C
.............. 85°C

!

O~-~-~-~-~~-~~~-~--~

4.0

Remark

4.5

5.0
5.5
Power supply voltage Vee IV)

6.0

Standby refers to the memory condition where no operation is possible (RAS/CAS inactive). Because.
in the case of DRAM. refresh is required for retaining data. data cannot be retained in the standby mode.

1051

APPENDIX A DRAM DATA COLLECTION

Figure A-10. 1CC3-VCC Characteristics IS.O-V device)
'.5r---r--,..--r--..,......-"""'!"---,---r---,
.............,................................................................................................ t-RC-=-'-300nosC' 25°C, 85 °C

Jl

'C
~

'"

~'.0~--~---1----~1----+----+----r---~---1

! . . . . . . .,. . . .

. . . . . . . . . . . . . . .,. . . . . . . . . . . . . .

l.............

co

1~05~--~---1----+----+----+---~--~~--~
'C

•

.0;~

E
o

z

·············i·.. ··········

···········-1-············ ·············t············

·············t·············

O~----~----~-----~----~
4.0
4.5
5.0
5.5
6.0
Power supply voltage Vcc (V)

Figure A-11. ICC4-Vcc Characteristics IS.O-V device, fast page mode)
2.0r--..,......--r----;-......,--~-..,......--r---,

--O°C
-.-.- 25°C
............................................................................................................. ······....····85°C
tpc = 45 ns

'C

~ '.5~--~---1----+----+----+----r--~~--,

.g"
E
~

..•.......... j--.....•..... ············f············· ······_-·····i·············

'C

_._._;

~

.gj '.0 ..·

§o
Z

.

.

.-...-.-.....~- ....-.......

......
..
--_._. '._-.....................
........-... ···...·_·····r··········...·
.;

~

L......................+............

............. j..........................f..........................

0.5':--"----:-l:------::":-------::"-::--......:.---:I
4.0
4.5
5.0
5.5
6.0
Power supply voltage Vcc (V)

1052

I
,j

t

II,',

il,

APPENDIX A DRAM DATA COLLECTION

Figure A-12. 1CC4-VCC Characteristics (5.O-V device. hyper page mode)
1.2r----r--""'T"-~--,.._-""'!"'"-....,.--!""""__.

--o·e
_._.- 25·e
··············85·e

]

·············t············· ..-.....-.... ~ ...-.-..-.... ..--........ -{............. ·············r·············

~

tHPC

=30 ns

-t-_. _._";
~W~~~;t..······..···

o

----

"'OID

. _..

.___._0'-;0_.-

~ '.0

....•.......:...•.
. : _....

f······················.
~

......_......

.

-----:------------ --T---

!

----T---

0.8':-------:-'::-----........~------.......----_:'
4.0
4.5
5.0
5.5
6.0
Power supply voltage Vee M

Figure A-13. ICC5-Vcc Characteristics (5.O-V device)
2.0r----r--""'T"-~--,.._-""'!'""-....,.--!""""__.

·············;············· ....·......+....·......·......·..·..·1.......·..................
,

,

- - 0 ·e, 25 ·e, 85·e

,

·t.......... · ..

I,

11

11

o~-~-~----~----~------:'
4.0
4.5
5.0
5.5
6.0

II

Power supply voltage Vee (V)

I,

,!

!l
I,'l
II
"
'I:

II

Ii
I

I
1053

11

I,

APPENDIX A DRAM DATA COLLECTION

Figure A-14. Ieee-Vee Characteristics (S.O-V device)
2.0r--;--"T"-""'!"-....,..---;,..--,.--~-.,

I

]
E
~

'5
<.>

--aoc
_._.- 25'C
.............. 85°C

!

.............1'-..----.--.. .. --..-.---...~-.-.-.. ----.- -----··---···+--·----·····+·····..·..·+·..........·1

.<::

II)

~j ~~==~--~~~==~~~~
._._.+._._.
1.0.

.

f-'-'-'j""'-'-

B ::=:=c:=:= =:=:1=:=:. . . . ·. . . r . ·. . . . . . . . . . . . . . . . . .
al
N

~

-.. -.. ---- ... ~.- .. -...... -- ....---.----.~------ ..----..----.--.- ... ~... ------ .. --. -- ... -.- .... -~.-.-.- ..-----

E
o

z

O~----~-~-~--~~~----~
4.0
4.5
5.0
5.5
6.0
Power supply voltage Vee (V)

Figure A-1S.ICC7-VCC Characteristics (S.O-V device)
2.0r----r---,-----.,.....-----r--....---,

.B
E
~

---DOC
-.-.- 25°C

.............. 85°C

--..-.-..-.. -~.--------.--- ··--·--·------r-------·-··--I....·........,.............. f....•..•..•..!.............(

i3

O~----~-~-~-~~-~----~
4.0
4.5
5.0
5.5
6.0
Power supply voltage Vee (V)

1054

Ij

II'.

APPENDIX A DRAM DATA COLLECTION

A.2 Access Time Dependence on Power Supply Voltage
Figure A-16. Vcc-tRAcCharacteristics (3.3-V device)
1.6r--~-"'--""""-r-"""-"""-""""--r--;--'

--O°C
;
;
•..... ;........... ··········;···········I···········i···········I···········i··········,,··········;···········1 _._.- 25°C
.......j...
.
.............. 85°C

~

1.4

, .•..•••.,

Icc

1.0

:

z

0.8

,

J" ~~'*---+-----

I

'-....:

:

.... '"

.

:

.

········~f: ·,;~~t:::~ "";:::::·C:::::::
\'-l..:
-.;. '-..
+.......
.

...............

.

••.••• ~ .••..•.••..••.••.•.•;......••••. j•..•........ ;•.•••••.••

"+"''''''"--k:::~

0.6 '---'---'---'---'---'---'---'---'---'----'
2.5
2.7
3.0
3.3
3.6
3.9
Power supply voltage Vee IV)

Figure A-17. Vcc-tcAcCharacteristics (3.3-V device)

o

20

~~~_+__

~

" 1.5

:.

",i'.....
.•..

--O°C
_._.- 25°C
..·..·..·....·85°C

!

".

:

~.

.S

'I'of~~~d::
§ 0.5:

:

:

0 :

Z

I --.

--r--:
'

i
...........'...........
1·····.;..··········+··········;······················;···········1···········;··········+
O~~-~~-~-~--~--~~--~--~

2.5

2.7

3.0

3.3

3.6

3.9

Power supply voltage Vee IV)

!

It

'I
1
j!
1055

1
I,.'

1,'•. 1
t.~

APPENDIX A DRAM DATA COLLECTION

Figure A-18. Vcc-tAA Characteristics (3.3-V device)
1.6r-;--;--;---r-~--"-"""'!"-....,..--;----'

!
!
--O°C
-·-.·.i-·------.·- ---------·+---------1-----------;-----------1---·-------,---------+-----·--;-------""-1 _._.- 25°C

~ 1.41-+---+--+--+--+-+-+---+--+---1

..···..--·····85°C

E····~·:~;.1·-····-·-·- ···-·····-·~·····--····I-----------;----------+--·-----+--,,----+---"--,,+,,-,,--,,,-1
§~ 1.2 >'" ......•
;Z
-:~<,------ :.,~<;;:--; --------I----------·i----------+--,,------,--·,,----+-------,,'--,--,,-,--,

~

~

"'~"

"

:

i::~~~t:~~=±==
~~:-.

i

······r·········· ····· __ ·· ..

0.6
2.5

2.7

.'"!.-.- _._...... _.t·········· .-.. ····t······__·· ···········r----······
········_-t·_-_····_-

3.0

3.6

3.3

3.9

Power supply voltage Vee (V)

Figure A-19. Vcc-tAcp Characteristics (3.3-V device)
1. 6 r-""!"""-"T'"-""!"""-"T'"-""!"""-"T'"-""!"""-"T""-""!"""---'

~

2

---O°C

------,----"----- """"--;-"--------I----,,-----;-"'''''''..,.-··,,---'''-''''--,,--t,,-"""-;-----"'---1 _._.- 25°C
....·........·85°C
1.4r-~--~--_7---+--~----r---~--t_--~--l

"~

...... L.......... .......... i. ........__ .... _______ i................ _____.L ...... ----t----------+-,,-.,,---I

15 1 .2 ......~............

j ~;;~_~~~: :~:t:
>'0

i!l 0.8'

~
Z

:.............

-i.

'

0.6 L..-"'--_I----'-_--l.._-'-_...I-_"-----'_--'-_....I
3.6
3.9
2.5
2.7
3.0
3.3
Power supply voltage Vee (V)

1056

,

---""-";. . , -----,, t:::::C~::::::- ,,:::::::::"-' _. .:. ..-

APPENDIX A DRAM DATA COLLECTION

Figure A-20. Vee·toEA Characteristics (3.3-V device)

2.0.........

.

__ 00C

r"t~ ~~,,~--f......,......
~..

•

_._.- 25°C

f..........., ..........1 ··············85 °C

~

@

fO

§oM

! , ..... , . ..~..........

•

~+~~~
.

z

.

_.

::
t······;············t··········j··········· ···········r···········

j--

O~~--~~--~--~--~--~~~~--~

2.5

2.7

3.0

3.3

3.6

3.9

Power supply voltage Vee (VI

1057

APPENDIX A DRAM DATA COLLECTION

Figure A-21. Vee-tRAC Characteristics (S.O-V device)

1.3,--...._-.....,..--_-...,...-....,...---.--_--,

---oce

.............!.........................+.........................+........................i............. _._.- 25 ce

··············85 ce
~ 1.2
Q>

.'E"

~"'~ 1.1

._..•. -------:------------- -._-.••. -----+ .. ---.------- --.--..-...•. ~-.--------.-- ----····-----f------·_----.............. :.....
.............,..•..•....... ·············,·············1·············;················1·············;·············

I~ 1 or---~----~---+----+----+----+----+----;
~

~

~

.

' :

...

:

::::::::~"',,,~,~~ -,+,~,~,.

0.9

· . . '. . 'r'. . '. . '. .,. . ,. .
:

:

f....,.....,=

===+-................... .

......_....L..._.....;..._.....I._ _'--_.l-_-'-_..J
4.5
5.0
5.5
6.0

0.8~_

4.0

Power supply voltage Vee (V)

The 5.0-V operation devices of 16M DRAM all adopt an internal voltage-drop circuit.
The internal voltage-drop circuit causes the power supply voltage (5.0 V) supplied to the memory externally to
be dropped inside the memory and 5.D-V·operation devices also operate on 3.3 V inside the memory. Therefore.
there is almost no difference between the current consumption of a 5.0·V operation device and that of a low-voltage
operation device. The low·voltage operation device of 16M DRAM does not adopt any internal voltage-drop circuit.

1058

APPENDIX A DRAM DATA COLLECTION

Figure A-22. Vcc-tcAc Characteristics (5.O-V device)
1.9,..--...,--.......-_--.,......-_-...,.--_----.

--O'C
··,··· __ ···_-t············· ........_---+.._-_...................._+ .._-_................._o·f············· _ . _ - 25°C
·········_···85°C

u

1.6r---~----r---~----+----+----+----+----;

.~

·············1············· ·············r··························j·············............+............

.§

~ 1.3r---~----t---~----+----+----+----+--~

I Vl5~

li
:as

~

+. . . . . . . . . . . . ~. . . . . . . . . . . . .+. . . . . . . . . . . +. . . . . ..

............

.............1'............ ···. .·..·····r-..·--.............,.............. ·········....r····.....·····
1.0
:
:
~-'--i-'-'1-'-'-;-'-'- -_.-t-_. ._-+-_._.
.
.

0.7 r----+----t----+---+--i---+-----t---;
.
. .
.
.
·············j·························r························r·······················j·············
0.4~------'--....;..-.......I.--'---........-----~

4.0

4.5

5.0

5.5

6.0

Power supply voltage Vee (V)

Figure A-23. Vcc-tAA Characteristics (5.O-V device)
1.5r--~-...,--~---r-'"""'!--r--'"!""""-.,

---O'C

+. . . . . . . . . . . .+. . . . . . . . . . . ·.t.··...······· ::::::::::::::

.............L.......................
~
.~1.25

~8

~~:g

~:~-::::::i::~:"",,'·
."m'~""t""~'~""
"'~'~m",i""""'''''.
'"''''''''''f'''''''''''''
...............
:
:
:
! - - ._._+._.- .__.t-._.- f-'-'-r-'-'-

; 1.0.........

i

...

············-t····__·__·__· ···__·······t············· .-.-..... -..-~.-.--..-..-..

·············t····__··_···

~~O.751---+---+--+---+--+--'--+--+-~
!
j
5

Z

............-1'............ _···--------T------------- -----..--... -"!••••••••••-••••-••• -•••••• ••••• -•••-•••
~

.......------I.-~--.i.---'-_..J

O.5~-----

4.0

4.5

5.0

5.5

6.0

Power supply voltage Vee M

1059

APPENDIX A DRAM DATA COLLECTION

Figure A·24, Vee-tAcp Characteristics (5.O-V devi~)
1.6r----r--.,---r---,---r--,--"""!'---,

-O°C

------------j------------- -------------t------------- ------------+----------- ------------+----------- - - - 25 ·C

~

f6.
151.2

!

! !

-.--.....-..• 85 ·C

4

~

·----········t············ -_.. __.....

i

i

-------------i-~----------- ------------t------------ -------------r----------- -------------1-------------

-~ 1_0 ---..·..-1·..·---·-·

!

_j..... _...... ··········---1············· ..-.........-~-.-........-

i

·t. _- -.. -._- ,. . . . -.- -------·--i----·--

-_·-..

~;;;:::::::: -=::::;'::=:::::=:f== .::::=:;:::::==

_!!! 0_8

___________ .1. ____________ -------------r------------- -------------r------------ ------------T------------

)

0_6
4_0

4_5

5_0

6_0

5_5

Power supply voltage Vee (V)

Figure A·25. Vee-tOEA Characteristics (5.O-V devi~)

.,....-""'"'-_r--r___,

2-5r---"'!""--r-....~.....

---O·C

-------------i------------- ------------}------------- -------------t------------ -------------f------------- ----- 25·C

.---.---.-. 85 ·C

i

,

~ 2_01---+---t--+---+--+---+-----i----l

j---f-- --r- --r--- ---Lea 1.5

I~
"'C

III

~

........_.-i--...........

• •• ··.---··.·i.····.......·

:

---..r. .-.. . . _. . . . t--...-

····...·_..t·_-_··

--_......__..;, ........._...............i-.........-- ..........--.;............. .

--.-j---r-----t-.-

--+.--~--+_.-.

~ 1_01----+----+----+----+----+----+---~----1
,

,

··········t·..·······················f·············

--_··········l'············ ·············r··············..

!

!

j

1

0_5L:--:...----:"~-'-----:~-:...----:~-:...-~

4_0

4_5

5_0

Power supply voltage Vee (V)

1060

5_5

6_0

APPENDIX A DRAM DATA COLLECTION

A.3 Current Consumption Dependence on Cycle Time
Figure A-26. ICC1-tRC Characteristics (S.O-V device)

- - 0 °C, 25°C, 85 °C

w

···r··················· ......................................................... . Vee = 5.5 V
tRAS = 70 ns

-'" 1.5
~
E

ii

\

..\
.................................................................................
.

Cl

"

1
.~

10
. ............\

ro

.................................................................. .

\

1\

oEO.5r--i--rt~tHt--i--ri1i+Ht---r-Ti-HiTH

z

...........................

................ .

~

l"'---

o
10-'

10°

10'

10'

Cycle time tAe (,us)

Figure A-27. 1CC3-tRc Characteristics (S.O-V device)
2.0 r---"'--'--'-IT'T
I"T'TT'T""
1-;---r-r""""'~-'--T"T"T"TTm

...................!. ~. +........................................................ .

t I-~+.\

I

- - 0 °C, 25°C, 85 °C
Vee 5.5 V

tRA'

=
=70 ns

. -..

f...-I
... '....t.. H.+
.. 1+.. f-....-....--t.. -....--t
.. -I
... ri
... -to.tt..tt..-...-....-t
...-....-t
...--t
...-t
...+
.. ttH
...

>1.0~-4.-~~~~--+-~~~tH---+--r+~+tH

I~-g
~

§o

··········f\··········································........................ .
f\

0.51---+--Htt+f+++-+-+-++t+t+t---t--t-+-t-tttt1

Z

Cycle time tAe (,us)

1061

APPENDIX A DRAM DATA COLLECTION

Figure A-28. 1CC4-tPC Characteristics (S.O-V device)

--o°C
_.-'.- 25°C
....··..··..··85°C

]

~

Vee = 5.5 V

I'

~ 2.01----1i--+-I--t\lH-ttt--+-++t+rttli---+-H-t-lf-ttH

~

~

.......................... ~............................................ .

\ •...... r:::::.

]1.0
~

.......

E
o

z

......... - ...... ...... _ _ •......... _. __ "'"

"r-._..

,~-

.... __ . ~::: :::::::::: ::::::. ~:: ::: !: ~

10"

e•

!

10'

Page mode cycle time tpc Cas)

Figure A-29. 1CC4-tHPC Characteristics (S.O-V device)
1 .9 r-"""T"--,rr.,.,-rrn-""""""""T"-;-rT'T"ITT"--;-"""""'T"T"TTIm
--o°C
................ ........................................................... .
~

] 1.6

................

~

~ 1.3
Q)

-_.- 25°C
··············85°C

\\

\,\'

.......................................................... .

r,\
••••••••••••••••••••

1

"8

" ................................................._..__..

\

.,El.0r-~-~~~+--r-~-rHtH--r-~r+~
-6
.. ~
Cl

<0

••••••••••••••••

1°.

7

Z 0.4

--- ••

_.

• •• __ .--_••••••••••••••••• - ••••••••••••••••••• - • • • • • • • •

~:~~~~ ................................. .

.............................

-" _.

•

............................................. := .'".....
' J"~"'_,:~_
.....

••: •••::::: ::::::.:.

Page mode cycle time tHPC (ps)

1062

Vee = 5.5V

APPENDIX A DRAM DATA COLLECTION

Figure A-30. lCC6-tilc Characteristics (S.O-V device)
2.0 r---r--'--rTT1:TiT---r--'-""T""1~TTT"-"T""--rTTTT1i1

--O'C

] 1.91----1-+-I-+~H--+--+_HH_t+t+-_+-H_++_++H -.-.- 25°C
··············85°C
Vee = 5.5 V

c:
~

r----1r-+-I-+H+~-+--r+-HH+H-_+-H_+++tH tRAS=200ns

~1.6 .......................... '~.............................................. .

!a
0:
(3

::~~ ........................................... .

1.3 .............................
1.0

\'~

'. \ \

..................................... ";.~.~ ............................... ..

II 0.7
~

ga 4

•....
................. _.--.

----

....... __ . __ ............._ ... -.- .. .

__ .. _----_._---- ... :

....

t::----.

z .........................................................::::::::::;;;;;:

Cycle time tRc(PS)

Figure A-31.

ICC1-tRAS

Characteristics (S.O-V device)

--O°C
--'-25°C
..--········85°C

8 1.5 1--t-H-fflIYr--tH-+-t-ttt1It--+--+-++ttttt--t-_H-+ttttt Vee = 5.5 V
::

~

r.
~

~......

r~....

..................................

tRP= 60ns

a1---+--+-++f++H--'\'I.. \""..\:.,+-+-++fItt-+-+-++t+Itt----1H-t-1-tttH

'0

.~

......... \~.

".
§ 0.51--r+t+ItItI-+-++-tl'~J.....
;-".....
cr-r++ttttt-+-Hl-tttttl
o
1"':'~
Z
•••• ::::"!--T:tt!ttt-t--I-+tttlfI

"i5

..........., ;;;. t:::::::.::·:.:

10-'

100

la'

la'

RAS pulse width tRAS (ps)

',:,1,
~

1

j

Ij
1063

I

APPENDIX A DRAM DATA COLLECTION

Figure A-32. ICC3-tRAs Characteristics (3.3-V device)
2.0 r--,-.,...,..,.,.rm--""-'-'-!"Tn''''-'''''''-'-''''''''Tm-'''-,....,..,..".".,
- - 0 °e, 25°C, 85 °e

Vee=3.6V
tAP

E

=60 ns

~L5r-++t-+H1H-++-t-++H-H--+-H-+++Ht--1,...--t+HtttI

i·····. . ·. · · · K. . . . . ·.
OJ

u

>- 1.0 J---+-t-++ttttt---'H-\++-+++tH--+-+-H+tttt---t-+++ftttI

co

·......1\ . ·. ·

I~
'0

~O.5r-++t-+~-+~-++H-H--+-H-+++Ht--1,...--t+HHH

§o

f'~~

Z

~ 0-2

10-'

..................... .

10°

10'

102

RAS pulse width tAAS (,us)

Figure A-33. 1CC3-tRAS Characteristics (5.O-V device)
2.0 r-"T"""'1"'TTTTm"---'-'--:M1,-m--;-..,..,-.,.",.r;--;--1"..,.'T!TT'I

--ooe
- ' - ' - 25°C
.............. 85°C

Vee = 5.5 V

i . . . . . . . . . . . . . ..

tAP

~

> 1.0 r-++t-+~'-'\~'

.. rl-HHtttt---t-+-+tttttt-++I-H+tH

§
I~

~

...........................:':~.~..

]0.5r--t-+t-+~~++-t-H~~~--t-+-+tttttt-++I-H+tH
..
=--:.

§

z

.............. "

................
10"

....... t.:::

....... ::·,;:t:$ItmE
....:::
...f:...::F.
...::E
. .~.m
100

RAS pulse width tAAS (,us)

1064

10'

10 2

= 60 ns

APPENDIX A DRAM DATA COLLECTION

Figure A-34. ICC6-tRAS Characteristics (S.O-V device)

3.0 '--'--'-'"n""1"TTT--r"""'''''ITTTT-'-'''-TTTrTn

--O'C
] 2.5

c

-._.- 25 'C

I--f--++-+-+++++--+-H+H-+H--+--++++++H .............. 85 'C
Vee = 5.5 V

~

:>

~ 2.0 t--j--+H-t+ttt--t-H+Hitt--+-t-t-+ttttl

tRe

= 125,u5

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