1996_National_SCAN_Databook 1996 National SCAN Databook
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SCAN
DATABOOK
1996 Edition
Design for Test Solutions with
Boundary Scan
Description of Boundary Scan
Device Description and Characteristics
Loading Specifications, Waveforms,
Quality and Reliability
Characterization Data
••
••
•
••II
III
[II
Boundary Scan Design Support
Application Notes
SCAN CMOS Test Access Logic Datasheets
SCAN ABT Test Access LogiC Datasheets
System Test Support Datasheets
Ordering Information and
Physical Dimensions
III
http://www.national.com
I
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LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITIEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component is any component of a life support
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
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TWX (910) 339·9240
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied. and National reserves the right, at any time
without notice, to change said circuitry or specifications.
http://www.national.com
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Table of Contents
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National Semiconductor's SCAN Data Book offers Design for
Test Solutions to improve R&D development cycle time, reduce test development and manufacturing cost and improve
a customer's end system uptime. Designers, test engineers
and engineering management using concurrent engineering
practices will see life-cycle cost of ownership go down for
systems designed with boundary scan.
The SCAN Family of IEEE 1149.1 (JTAG) compliant devices
simplify integration of design and test.
SCAN Data Book
Product Index and Selection Guide
The Product Index is a numerical list of all device types contained in this book. The Selection Guide groups the products
by function and by family.
Section 1 Design for Test Solutions with Boundary
Scan ................................ 1-1
Describes OFT and boundary scan and why it affects the lifecycle cost of ownership of complex systems. Describes failure modes identified with boundary scan in board and system
level implementations as well as embedded, on-board test.
Section 2
Description of Boundary Scan ........ 2-1
Describes boundary scan architecture: Test Access Port,
TAP controller, and TDI, TOO, TMS, TCK signals; registers
and state diagram; mode of operation.
Section 3
Device Description and
Characteristics ...................... 3-1
CMOS and BiCMOS characteristics of SCAN ABT and SCAN
CMOS 18-bit Test Access Logic are described, including design architecture and performance attributes.
Section 4 Loading SpeCifications, Waveforms,
Quality and Reliability ................ 4-1
Section 5 Characterization Data ................ 5-1
Graphs depicting the propagation performance of the SCAN
CMOS buffers and transceivers.
Section 6
Boundary Scan Design Support ....... 6-1
How to obtain BSDL models and other simulation models.
Sources of information.
iii
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Section 7
Application Notes ............ 7-1
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Section 8
SCAN CMOS Test Access Logic
Datasheets . ................. . 8-1
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Datasheets for 18-bit CMOS devices feature low
power consumption, - 48 mA/64 mA drivers used
for surrounding clusters of non-1149.1 compliant devices in order to make a board fully 1149.1 compliant.
Section 9 SCAN ABT Test Access Logic
Datasheets .................. . 9-1
Datasheets for 18-bit SiCMOS devices. They are
used along the card edge going into a backplane to
provide live insertion/removal capability. Their 250
series resistors on the output eliminate an external
damping resistor and reduce ringing (noise).
Section 10 System Test Support
Datasheets ................ 10-1
These are true "system support" products. These
devices extend boundary scan features from the single board environment to several boards.
The Embedded Boundary Scan Controller,
SCANPSC100F, allows creation of an on-board embedded test environment. It provides the interface
from a target system's microprocessor and memory
to the IEEE 1149.1 Test Access Port. The Hierarchical and Multidrop Addressable JTAG Port,
SCANPSC110F Bridge, provides access to multiple
boards within a system for simultaneous testing of
like boards as well as system partitioning to better
isolate test faults. SCAN EASE in a suite of software
tools that enables test vectors to be embedded within an 1149.1 system; compiles and compresses vectors; controls and applies tests; reports failures; and
includes a graphical user interface.
Section 11
Ordering Information and
Physical Dimensions . ...... . 11-1
Functional description of the ordering codes, package outlines, (JJA information and Dry Pack handling
procedures.
http://www.national.com
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Product Status Definitions
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Data Sheet Identification
Product Status
Advance Information
Formative or
In Design
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First
Production
This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.
No
Identification
Noted
Full
Production
This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
Obsolete
Not In Production
This data sheet contains specifications on a product that has been
discontinued by National Semiconductor Corporation. The data sheet
is printed for reference information only.
•
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Definition
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
v
http://www.national.com
Alpha-Numeric Index
ADC0851 8-Bit Analog Data Acquisition and Monitoring System ...........................•.... 7-54
ADC0858 8-Bit Analog Data Acquisition and Monitoring System ................................ 7-54
AN-881 Design Considerations for Fault Tolerant Backplanes .............................•.... 7-26
AN-889 Design of a Parallel Bus-to-Scan Test Port Converter .............................•.... 7-30
AN-891 Non-Contact Test Access for Surface Mount Technology ..........................•.... 7-22
AN-1003 G.Host JTAG Interface for Graphics Host Reference Design ......................•.... 7-34
AN-1022 Boundary Scan Silicon and Software Enable System Level Embedded Test ............... 7-8
AN-1023 Structural System Test via IEEE Std. 1149.1 with SCANPSC110F Hierarchical &
Multidrop Addressable JTAG Port ......................................................... 7-3
AN-1037 Embedded IEEE 1149.1 Test Application Example ................................... 7-13
SCAN EASE SCAN Embedded Application Software Enabler .................................. 10-54
SCAN18245T Non-Inverting Transceiver with TRI-STATE Outputs .........................•..... 8-3
SCAN18373T Transparent Latch with TRI-STATE Outputs ................................ _.... 8-17
SCAN18374T D Flip-Flop with TRI-STATE Outputs ......................................•.... 8-29
SCAN18540T Inverting Line Driver with TRI-STATE Outputs .............................. _.... 8-41
SCAN18541T Non-Inverting Line Driver with TRI-STATE Outputs .......................... _.... 8-52
SCAN182245A Non-Inverting Transceiver with 250 Series Resistor Outputs ...................... 9-3
SCAN 182373A Transparent Latch with 25!l Series Resistor Outputs ............................ 9-18
SCAN182374A D Flip-Flop with 25!l Series Resistor Outputs .............................•.... 9-31
SCAN182541 A Non-Inverting Line Driver with 250 Series Resistor Outputs .................•.... 9-44
SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support) ..................... 10-3
SCANPSC11 OF SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
(IEEE 1149.1 System Test Support) ...................................................... 10-26
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TRANSCEIVERS
Non-Inverting
SCAN18245T
18-bit
•
•
•
•
•
•
Non-Inverting
SCAN182245A
18-bit
• High performance BiCMOS technology (tpo < 4 ns, typ)
• 25n series resistors in outputs eliminate the need for external terminating
resistors
• Dual output enable control signals
• TRI-STATE outputs for bus-oriented applications
• 25 mil pitch SSOP (Shrink Small Outline Package)
• IEEE 1149.1 (JTAG) Compliant
• Includes CLAMP, IDCODE and HIGHZ instructions
D
SCAN18374T
18-bit
•
•
•
•
•
•
D
SCAN 182374A
18-bit
•
•
•
•
•
•
•
Dual Output Enable Control Signals
IEEE 1149.1 (JTAG) Compliant
Includes CLAMP and HIGHZ Instructions
9-Bit Data Busses for Parity Applications
TRI-STATE@ Outputs for Bus-Oriented Applications
Reduced-Swing Outputs source 32 rnA/sink 64 rnA (Comm), and source
24 mA/sink 48 mA (Military)
• Guaranteed to Drive 50n Transmission Line to TTL Input Levels of O.8V and
2.0V
• TTL Compatible Inputs
• 25 mil Pitch SSOP (Shrink Small Outline Package)
FLIP-FLOPS
Buffered Positive Edge-Triggered Clock
IEEE 1149.1 (JTAG) Compliant
Includes CLAMP and HIGHZ Instructions
9-Bit Data Busses for Parity Applications
TRI-STATE Outputs for Bus-Oriented Applications
Reduced-Swing Outputs source 32 mA/sink 64 mA (Comm), and source
24 mA/sink 48 mA (Military)
• Guaranteed to Drive 50n Transmission Line to TTL Input Levels of O.8V and
2.0V
• TTL Compatible Inputs
• 25 mil Pitch SSOP (Shrink Small Outline Package)
High performance BiCMOS technology (TPO < 4 ns, typical)
25n series resistor outputs eliminate need for external terminating resistors
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
25 mil pitch SSOP (Shrink Small Outline Package)
IEEE 1149.1 (JTAG) Compliant
Includes CLAMP, IDCODE and HIGHZ instructions
vii
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Transparent
SCAN182373A
18-bit
•
•
•
•
•
•
•
Inverting
SCAN18540T
18-bit
(Same Features of the SCAN 18541 T)
Non-Inverting
SCAN18541T
18-bit
•
•
•
•
•
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Non-Inverting
SCAN 182541 A
18-bit
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SYSTEM SUPPORT
Embedded
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Scan
Controller
SCANPSC100F
• Compatible with the IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan
Architecture
• Interfaces up to Two 1149.1 Scan Rings
• Fabricated in FACTTM 1.5JJ- CMOS Process
• Generic Parallel Interface Synchronizes Processor Signals with the SCANPSC1 OaF
Operation Clock, SCK
• 16-Bit Serial Signature Compaction (SSG) at the Test Data in (TOI) Port
• Automatically produces Pseudo-Random Patterns at the Test Data Out (TOO) Port
• 25 MHz Operation
• TTL Compatible Inputs, Outputs are Full-Swing CMOS with 24 mA Source/Sink Capability
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Hierarchical
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Addressable
JTAG Port
SCANPSC110F
• True IEEE1149.1 Hierarchical and Multidrop Addressable Capability
• The 6 Slot Inputs Support Up to 59 Unique Addresses, a Broadcast Address, and 4 Multi-cast
Group Addresses
• 3 IEEE 1149.1-Compatible Configurable Local Scan Ports
• Mode Register Allows Local TAPs to be Bypassed, Selected for Insertion into the Scan Chain
Individually, or Serially in Groups of Two or Three
• 32-bit TCK Counter
• 16-bit LFSR Signature Compactor
• Local TAPs Can Be TRI-STATE Via the OE Input to Allow an Alternate Test Master to Take
Control of the Local TAPs
SCAN
SCAN EASE
• Processor independent-runs on big/little endian and memory- and I/O-mapped
architectures
• Compatible with Teradyne VICTORYTM ATPG and JTAG Technology BTPGTM tools (others
supported upon request)
• Provides automated translation, application and evaluation of ATPG-generated tests in an
embedded system environment
• Includes a Scan Function Library and National's Embedded Boundary Scan Controller
SCANPSC1 OaF device driver to support custom or non-ATPG generated vector applications
• Supports embedded test data log for diagnostic processing
• Includes Microsoft Windows GUI and serial communication tool for system administration and
remote testing
• Supports SCANPSC110F Hierarchical and Multidrop JTAG Addressable Port architecture
Embedded
Application
Software
Enabler
ix
http://www.national.com
Section 1
Design for Test Solutions
with Boundary Scan
II
http://www.national.com
Section 1 Contents
What is DFT? .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Development ................................................................
Board Manufacturing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Field Service. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Economics of Design for Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Where the Failures Are. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Fundamentals .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System-Level Embedded Test .......................................................
The Impact of PC and Communications Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-3
1-3
1-4
1-4
1-5
1-5
1-7
1-9
1-10
1-11
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What is OFT?
Design for Test, or OFT, is being used by many companies
to lower the overall cost of development, manufacturing,
test and field service. Some companies call it "Concurrent
Engineering" and it replaces the "Over-the-wall" method of
product development. In each stage of the product life-cycle, a consideration for testing is made in the earliest stages
of design.
Adding boundary scan to a board does add cost and time to
the design cycle due to the increased cost of boundary scan
compliant components and initial time investment required
to understand the boundary scan architecture and tools.
However, these costs are easily justified when viewing the
benefits and cost savings boundary scan provides at every
stage of a product's life cycle. What was originally developed as a manufacturing test tool offers benefits before,
during and after manufacturing.
National employs boundary scan technology to enable not
just chip testing, but also board testing, system testing, and
in-field service testing.
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TCK/TMS: All devices in the chain are connected in parallel to the TCK and TMS signals. This means
that all the devices' TAP controllers are in the
exact same state and transition simultaneously.
The instruction register allows each device to
include different data registers in the scan
chain and perform different scan operations.
In like fashion as the chip, the boundary scan chain is extended to the board in a serial scan chain. Boards in systems can also be linked in a scan chain.
When placed on a printed circuit board, each 1149.1 component is connected together to form a chain of boundary
scan devices. In Figure 6, note the scan chain connections:
TOI/TOO:
The tester's serial test data out pin is connected to the first device's TDI. The test data is
passed from the first device to the second device via the TOO pin which connects to the second device's TOI pin. This chain formation continues until the last device's TOO pin is connected back to the tester. Therefore, shifting
data into a device's instruction or data registers
requiies that the data passes through every
JTAG device which is connected ahead of the
device in the scan chain. Additionally, as the
data is shifted into the device, the data previously stored in the selected instruction or data
register is shifted out of the chain. The tester
software either reads and evaluates the returning data or masks it out. The Bypass register is
included to shorten the chain when shifting
data through devices which are not participating in a given scan operation.
Dala from Tesler
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____ .. ________________ !_______ ~----------------------------- ___ 1
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TLlF/11587-10
FIGURE 6. 1149.1 Boundary Scan Chain
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Implementing boundary scan on every component on the
board provides the maximum benefit in terms of reduced
tester cost, test development times and concurrent engineering. However, boundary scan can also complement an
ICT in testing structural faults. See Figure 7. This was fully
recognized by ICT tester companies when they developed
their ICT systems and most ICT's now have a connector
dedicated for boundary scan testing. Additionally, these
tester companies included the option of mixing boundary
scan and ICT in their ATPG tools by using ICT component
libraries for non-scan products and BSDL for scan products.
For example, vectors can be automatically generated to
drive signals with boundary scan and compare results using
physical test probes. Many companies have already invested millions of dollars in ICTs and may want to use boundary
scan only where required for inaccessible nodes, non-library
parts, etc. or as a means of cutting ICT fixture costs.
Figure 7 shows two examples of ICT and boundary scan
working together. The lower of the two graphics shows cluster testing. Cluster testing is the testing of a group of devices by applying data to the inputs of the group or cluster and
evaluating the results on the output of the group or cluster.
Cluster testing can vary from testing the interconnects between the components in the cluster to testing the internal
nodes of each component within the cluster.
System Test
National supports the needs of the system design architect
by:
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While boundary scan diagnostics are particularly useful for
telecommunications and workstations, their benefits also
extend to board manufacturers that want to reduce the timeto-market of their products.
For smaller companies or companies in the process of purchasing new ICT equipment, implementing boundary scan
may provide a way to reduce the required ICT features like
number of channels providing a tremendous reduction in the
tester cost where cost ranges from $200K up to $1 M.
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For small companies, we provide the option to expensive
$1 million test equipment. With help from our software and
hardware partners (such as Corelis and JTAG Technologies), National can support total system test solutions with
PC-based boundary scan devices, software, and hardware
solutions.
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system logic, the 1149.1 user can logically extend the internal system logic to the EXT EST function. This feature is
available during the EXTI;:ST instructions for these products
because the state of the outputs is captured along with the
state of the inputs during the rising edge of TCK in the
CAPTURE-DR state. Note that this is contrary to a recommendation of capturing fixed values on the outputs during
EXTEST, but it provides for a feature that would otherwise
not exist.
sarily in its function. The BYPASS register consists of a single shift register stage in order to shorten the board-level
serial scan chain by bypassing some devices while accessing others. This feature is intended to reduce the software
overhead in applying and retrieving serial test data by permitting a shortcut between TDI and TOO of any given integrated circuit in order to expedite access to others.
The BYPASS register must capture a logic low value upon
the rising edge of TCK in the SHIFT-DR state provided that
it is selected by the current instruction. This feature is designed to accompany those devices which incorporate the
32-bit device identification register. (The BYPASS register is
a test data register whose least significant bit is a fixed logic
high.) Upon an initial scan of the data registers connected
across the board, all devices will either connect the BYPASS register or the optional device IDENTIFICATION register in its test data register scan path between TDI and
TDO while in the SHIFT-DR state. (This condition is a result
of power-up or a logic low assertion to TRST to initialize
each 1149.1 device on board.) By shifting the data registers
the retrieval of each logic zero indicates a BYPASS register
connection until the first logic high is read. The logic high
will be the framing bit of a device IDENTIFICATION register
which would then indicate that the following thirty-one bits
are identifiers to the specific device at that location of the
scan chain. The requirement that the BYPASS register capture a logic low value is intended to form the background for
the device IDENTIFICATION register framing bit. Additionally, the logic low value is opposite the value to be produced
in the case of an undriven TDI input pin.
While these cells are sufficient to observe the logic state of
the signal in which they are placed, they have a limitation in
observing the activity of such a signal as in the specific case
of a three-stated output. To determine the activity as well as
the logic state of such an output, two such scan cells are
required. One in the data signal path and another in the
output enable signal path. By observing at both locations
the drive activity and/or logic value can be inferred. In thecase of a single output enable signal controlling more than
one output data path, the output enable signal may be observable and controllable at a single location rather than at
each specific output without loss of functional intent provided that the specific location retain control over all the data
outputs in unison. This provision is included to reduce the
hardware overhead as in the case of a device where such
output enable signals are organized byte-wide.
The order of the required scan cells in the Boundary-Scan
register is undefined by the 1149.1 Standard and hence can
be device specific even if the system function of that device
be identical to another 1149.1-compliant device. In other
words, even if two identical system function devices are
1149.1-compliant there is no guarantee that such devices
will be identical in the structure of the Boundary-Scan register.
A description of the Boundary Scan Register for each device is included in its datasheet.
Device Identification Register
The device identification register is a 32-bit, read only register compliant with IEEE Std. 1149.1. When the IDCODE instruction is active, the identification register is loaded with a
fixed, unique value upon leaving the Capture-DR state. The
10 code register contains information pertaining to the device manufacturer, part number and revision. It is used to
ensure the correct device is properly placed in the correct
location within a boundary scan chain.
An identification (ID) register is included within the National
SCAN ABT Test Access Logic devices. The specific ID register value is provided in the associated device datasheets.
Input Boundary-Scan Register (SCAN ABT only)
The Input Boundary-Scan register operates in a manner
analogous to the full length Boundary-Scan register.
Output Boundary-Scan register (SCAN ABT only)
The Output Boundary-Scan register operates in a manner
analogous to the full length Boundary-Scan register.
Please refer to the device datasheet for a description of its
input and output Boundary-Scan Registers.
BYPASS REGISTER
The BYPASS register is also a test data register and therefore must comply with the definitions surrounding test data
register operation; but its advantage is in its size, not neces-
http://www.national.com
2-10
Section 3
Device Description
and Characteristics
http://www.national.com
Section 3 Contents
Family Comparison Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BiCMOS and CMOS Family Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCAN ABT Test Access Logic................ .............................. ...... ...
SCAN ABT Live Insertion and Power Cycling Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABT Circuit and Design Architecture ....................................... . . . . . . . . .
Threshold and Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic System Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABT Process Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCAN CMOS Test Access Logic.....................................................
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Immunity ..................................................................
Noise Characteristics ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Characteristics ............................................................
Circuit Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·2
3-3
3-3
3-4
3-4
3-6
3-9
3-9
3-11
3-12
3-12
3-12
3-12
3-13
3-13
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Device Description and Characteristics
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Family Comparison Chart
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Depending on system architecture and purpose, devices are
selected to optimize system performance. National offers
CMOS and BiCMOS SCAN families, and the comparison
chart is provided to assist you with your selection criteria.
Speed, power, noise drive, etc. may weight differently in importance depending on whether the end system requires
computing speed, low standby power, low EMI to meet FCC
regulations or must meet anyone of many bus standards.
Significance
BICMOS
CMOS
6.5
8.5
Guaranteed
Speed-tplH ns (A - . B)
Faster system performance
Static Power ICCl
(Outputs Low)
Lower quiescent supply current, less power consumption,
and less cooling required
65mA
0.8mA
Guaranteed Dynamic
Power ICCD (mA/MHz)
Lower system power consumption under heavier loading
conditions
0.2
(Note 3)
not
specified
Ground Bounce
VOlP (5V, 25°C)
Less data disruption, especially when switching multiple
outputs at one time
not
specified
1.5
0.8
0.8
Dynamic Threshold
(5V, 25°C)
VllD
Capacitance
Compatible with 16-bit wide pinout
CIN(pF)
ESD(Note4)
Lower capacitance means less bus loading,
notwithstanding
frequency
2.0
2.0
SSOP
SSOP
5.9
4.0
13.7
20
IOl
15
64
IOH
-32
-32
>2000V
>2000V
ClIO (pF)
Output Drive (mA)
Less data disruption, especially when connected to a bus
VIHD
Packaging
Easier handling
NG = Not Guaranteed; NA = Not Available; NS = Not Specified
Assumptions: Device is SCAN16245T CMOS and SCAN162245A BiCMOS
Note 1: VOLP is measured on '244 function.
Note 2: Specified with 6 outputs switching and no load.
Note 3: ICCD measured 1 bit toggling, OV to 5V, 50% duty cycle, outputs loaded with 50 pF, no resistor.
Note 4: Typical values for HBM ESD.
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BiCMOS and CMOS Family Comparison
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Live insertion
-
Removal of boards without having to power down the
system
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This saves time and eliminates those unwelcome sparks!
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25fl series resistors on the outputs reduce ringing
(noise) and eliminate the need for an external "damping" resistor. In the past, this was used to reduce noise
on CMOS or FCT products.
-
SCAN ABT will power up in TRI-STATE®. Beyond allowing live insertion and board removal, it enables system
power partitioning by electronically switching them offline to save on power. This is particularly beneficial in
remote locations that experience power shortages.
-
SCAN ABT has reduced power during power-up and
power-down TRI-STATE. This reduces the loading on
the bus to which it is attached, taking less time to charge
up all of the capacitance on the circuit using SCAN ABT,
and allowing the bus to run faster.
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SCAN ABT is intended to serve in live insertion backplane
applications. It provides 2nd Levellsolation 1 which indicates
that while external circuitry to control the output enable pin
is unnecessary, there may be a need to implement differentiallength backplane connector pins for Vee and GND. As
well, pre-bias circuitry for backplane pins may be necessary
to avoid capacitive loading effects during live insertion.
Here are other SCAN ABT features:
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SCAN ABT Live Insertion and
Power Cycling Characteristics
SCAN ABT Test Access Logic
When these functions are added to the card edge going into
the backplane, users gain these benefits:
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SCAN ABT provides control of output enable pins during
power cycling via the circuit in Figure 1. It essentially controls the G n pin until Vee reaches a known level.
During power-up, when Vee ramps through the O.OV to O.7V
range, all internal device circuitry is inactive, leaving output
and I/O pins of the device in high impedance. From approximately O.8V to 1.8V Vee, the Power-an-Reset circuitry,
(PaR), in Figure 1 becomes active and maintains device
high impedance mode. The paR does this by providing a
low from its output that resets the flip-flop The output, Q, of
the flip-flop then goes high and disables the NOR gate from
an incidental low input on the G n pin. After 1.8V Vee, the
paR circuitry becomes inactive and ceases to control the
flip-flop. To bring the device out of high impedance, the G n
input must receive an inactive-to-active transition, a high-tolow transition on G n in this case to change the state of the
flip-flop. With a low on the Q output of the flip-flop, the NOR
gate is free to allow propagation of a G n signal.
For more information on power-up and power-down characteristics refer to Application Note AN-881, "Design Considerations for Fault Tolerant Backplanes, "found in Section 7.
TO INTERNAL
TRI-STATE CIRCUITRY
elK
QI----....
RESET
POWER
ON
RESET
TLIF/12133-2
FIGURE 1
1Section 7, Design Considerations for Fault Tolerant Backplanes, Application Note AN-881.
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3-4
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SCAN ABT Live Insertion and
Power Cycling Characteristics (Continued)
During power-down, the Power-an-Reset circuitry will become active and reset the flip-flop at approximately 1.BV
Vee. Again, the Q output of the flip-flop returns to a high and
disables the NOR gate from inputs from the Gn pin. The
device will then remain in high impedance for the remaining
ramp down from 1.BV to O.OV Vee.
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Some suggestions to help the designer with live insertion
issues:
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• The Gn pin can float during power-up until the Power-OnReset circuitry becomes inactive.
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• The Gn pin can float on power-down only after the Power-an-Reset has become active.
The description of the functionality of the Power-an-Reset
circuitry can best be described in the diagram of Figure 2.
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:-.. DEVICE IN HIGH
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VCC (V)
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ELEMENTS INACTIVE
RAMP-UP AND RAMP-DOWN TIME
POWER DOWN CYCLE
POWER UP CYCLE
TL/F/12133-3
FIGURE 2. SCAN ABT Includes Additional Power-On Reset Circuitry Not Otherwise Included in ABT Devices
3-5
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ABT Circuit and Design
Architecture
SCAN ABT performs as ABT devices, except as where noted.
The circuitry for an ABT non-inverting Buffer with TRISTATE control logic is shown in Figure 3. Robust bipolar
components form the dual rail ESO protection networks for
both input and output structures. The 06 and 06 ESO circuits provide protection to the Vee rail and have a high
enough breakdown voltage rating to remain high impedance
(12Z < 100 /LA) during powered-down applications. The
Schottky transistors 05, 07 and 08 provide protection to
the Ground rail and double functionally as highly conductive
undershoot clamps.
The TRI-STATE output structure is formed with Bipolar
components to produce high drive (IOL = 64 mA;
IOH = -32 mAl and high speed TTL compatible logic
swings. The pull-up stage utilizes cascaded emitter followers 03 and 04 to provide high source current drive for the
charging of capacitive loads. The no-load TTL compatible
VOH level is one forward-biased VBE (03) drop and one
forward-biased VFD Schottky diode (04) drop below the
Vee rail yielding typical 3.SV VOH at 5V Vee, 25°C and
10 /LA source current. The ON source impedance of this
pull-up stage is typically less than 10n for source currents
between -5 mA to -40 mA at 25°C. This initial low impedance turn-on characteristic allows the pull-up stage to easily
provide a VOH level of 2V minimum at IOH source current of
-32 mA over the operating Vee and temperature ranges.
At 25°C and source currents above - 50 mA, the pull-up
stage becomes limited by voltage drop across the Rlos resistor and the effective source impedance becomes 25n
typically. Schottky diodes 03, 04 and 05 also provide blocking to insure that the pull-up stage remains high impedance
during power down applications.
When the output is enabled by a logic low on the OE input
and a logic high is on the Data input, the base of 03 is
driven to the Vee rail by the CMOS inverter in the data path.
The open drain CMOS NAND gate is logic high-open (nonconducting) and allows the base of 04 to be driven ON by
03. The CMOS NOR gate goes low turning 01 OFF and
turning ON the CMOS AC/OC Miller Killer circuitry which
grounds the base of 02, quickly turning it OFF. This circuitry
provides an active shunt for any charge coupled by the Miller Effect of the 02 collector-base capacitance during the
low to high output transition. Use of this active circuitry improves output rise time and serves to reduce simultaneous
conduction of pull-up and pull-down stages during LH transitions. The AC/OC Miller Killer circuit is also active when
the output goes to TRI-STATE to prevent 02 base injection
by the LH transitions of other outputs on a bus, therefore
dynamic bus loading will be capacitive only.
Power Down Miller Killer circuitry at the base of 02 is inactive when Vee is applied. When Vee is powered down, the
Power Down Miller Killer circuitry provides an active shunt to
transient energy coupled to the 02 base by its collector
base capacitance. This prevents momentary turn-on of 02
during LH transitions in partial power down bus applications
and maintains the powered off output as only a Hi-Z light
capacitive load (Izz < 100 /LA) to the bus.
Note that 01 drives only the 02 pull-down stage and does
not function as the Phase Splitter driver typical of TTL logic.
The pull-up stage is controlled by CMOS logic independent
of 01. This feature allows the input threshold voltages for
the CMOS logic driving the pull-up stage to be set independent of the logic driving the pull-down stage.
Blocking
Sub 1-micron
CMOS logic
for very low
power and
fast delays
r""'----------------------------..".....O::::::::'-..,
High
impedance
CMOS inputs,
BiPolar ESO
Structures
ABT TRI-STATE Buffer Schematic
diodes
high for
impedance
during
power-off
Proven
BiPolar
Output
Stage for
high drive,
smooth
edges
·open drain
TlIF/12133-1
FIGURE 3. Basic ABT TRI-STATE Buffer Schematic
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3-6
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ABT Circuit and Design
Architecture (Continued)
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The transfer function for the non-inverting ABT Buffer
shown in Figure 4 indicates that the data input switching
threshold for the pull-down stage is approximately 200 mV
lower than the pull-up stage. As the Data input is swept from
logic LOW to logic HIGH, the output switches from active
LOW to high impedance at an input threshold of about 1.3V
at 25·C and a Vee of 5.0V. When the input reaches about
1.5V, the output switches from high impedance to HIGH.
This design feature serves to reduce simultaneous conduction of the stages during switching. Also, the 200 mV offset
in Data input switching thresholds acts like hysteresis and
causes the buffer to be very tolerant of slow data input edge
rates, i.e., edge rates slower than 10 nslV can easily be
tolerated without output oscillation. The switching threshold
is proportional to Vee as indicated in Figure 5 and is quite
stable as a function of temperature as indicated by Figure 6.
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INPUT VOLTAGE, VIN
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1.4
1.6
INPUT VOLTAGE, VIN
2.0
1.8
TL/F/12133-4
FIGURE 4, Buffer Transfer Function
@ Room Temperature
Vee = 5V, T A = 25·C, No Load
1.8
400
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2.0
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TA = 25 0 e
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Vee =5.0"'1.
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With the output enabled by a LOW on the OE input, a LOW
on the Data input forces active LOWS on both the CMOS
inverter and the open drain CMOS NAND gate outputs,
which then simultaneously turn OFF 03 and 04. The CMOS
NOR gate output goes HIGH, turning the AC/DC Miller Killer
circuitry OFF and 01 ON to drive 02 ON. 02 is designed to
easily sink 64 mA IOL' at VOL < O.55V. During HL output
transitions, Schottky diode 01 assists the pull-down stage in
providing a low impedance discharge path for the output
load capacitance. As the stage turns on, part of the charge
on the output load passes through 01 and 01 to momentarily increase the base drive to Q2 and increase 02's current
sink capability. See output characteristics in Figure 7, IOL vs
VOL·
1.0
3.0
I
FIGURE 6, Transfer Function vs Temperature
Vee = 5V DC, No Load
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1.6
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2.8
OUTPUT LOW VOLTAGE, VOL (V)
1.0
TL/F/12133-7
FIGURE 7, Output Low Characteristics
Vee = 5VDC
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1.6
INPUT VOLTAGE, VIN
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1.8
2.0
TLlF/12133-5
FIGURE 5, Transfer Function vs Vee
T A = 25·C, No Load
3-7
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ABT Circuit and Design
Architecture (Continued)
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ABT is designed to be tolerant of controlled live insertion at
the PCB level. Controlled means that the insertion or removal methodology is accomplished in such a way that power to
the PCB is applied in a preferred sequence and that control
signals are provided to the PCB also in the preferred sequence such that output control is asserted to prevent contention of outputs attached to a bus during the power up or
down sequence.
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Tolerant means that ABT is designed and guaranteed to
behave in a predictable manner during controlled PCB live
insertion in systems requiring fault-tolerant or noninterruptable applications. Additionally, ABT has features which facilitate design of systems which must utilize power partitioning
for redundant circuitry or for powering saving of inactive circuits.
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2.0
3.0
4.0
All ABT input, output, and I/O pins are protected with robust
Bipolar components with respect to both Vee and Ground
rails. This circuitry is designed to withstand 2000V
(Human Body Model) and also to provide clamping action
for voltage undershoot while preserving low capacitive loading of the pin. The clamping action by the undershoot clamp
begins aggressively at voltages more negative than - 0.5V
relative to Ground, but this clamp remains non-conductive
at voltages up to 7V. Relative to the Vee rail, the ESO circuitry begins clamping only at voltages greater than 5.5V
above Vee. These ESO circuits remain high impedance and
non-conductive for applied input or output voltages between
-O.4V to 5.5V with Vee = OV to 5.5V.
5.0
OUTPUT HIGH VOLTAGE. YOH
TL/F/12133-8
FIGURE 8" Output High Characteristics
Vee = 5VDC
When the output is disabled by a HIGH on the OE input, the
enable CMOS logic quickly overrides the Data path logic
and cuts off drive to whichever stage is ON. In the case of
an LZ transition, the CMOS NOR gate is driven LOW turning
OFF 01 and turning ON the AC/OC Miller Killer circuitry to
insure 02 is quickly turned off. In the case of a HZ transition,
the CMOS inverter goes hard LOW to turn off 03 and quickly discharge the base of 04 through Schottky diodes 07 and
08. The effect of disable time (tpLZ, tpHZ) being typically
faster than enable time (tpZL' tpZH) inherently helps avoid
bus contention.
ABT CMOS input stages are Hi-Z with or without Vee applied. The IlL, IIH, and IBVI datasheet specification guarantees high DC impedance for inputs with Vee applied. The
VIO specification guarantees Hi-Z inputs with Vee = OV.
High impedance output and I/O pins are capable of maintaining Hi-Z status with Vee = 0 and during the application
or removal of Vee. The ABT data sheet parameters IOZH
and IOZl guarantee < 50 p,A output leakage for applied
VOUT voltages of 2.7V or 0.5V at any Vee between 5.5V
and OV with the output disabled and with the appropriate
logic input voltage maintained on the OE input pin. An additional Izz bus drainage specification guarantees < 100 p,A
output leakage at VOUT = 5.5V with Vee = OV. Therefore,
ABT outputs are guaranteed to remain glitch-free during the
power cycle and at power down Vee = OV. Refer to Application Section for a more detailed discussion of live insertion and powerup/down TRI-STATE capabilities of ABT.
Since the CMOS Enable logic remains active to Vee's well
below 2V, high impedance control can be maintained to
Vee voltages below the turn-on Vee thresholds of the Bipolar output stage. This insures the capability for glitch free
power ON/OFF high impedance outputs with the provision
that the OE input is maintained logic HIGH at or greater than
the data sheet specified 2.0V minimum VIH during the Vee
power ramp. However, since the CMOS logic switching
threshold varies proportional to Vee, a practical worst case
OE logic high of 2.0V or 50% of Vee, will maintain the power ON/OFF TRI-STATE condition during the Vee transition.
http://www.national.com
3-8
Total power consumption under AC conditions comes from
three sources; quiescent power, internal dynamic power,
and output dynamic power.
Threshold and Noise Margin
Figure 9 describes the input signal voltage levels for use
with ABT products. The AC testing input levels follow industry convention which require O.OV for a logic LOW and 3.0V
level for a logic HIGH. DC input levels are typically O.OV to
Vll, and high input levels are typically VIH to VCC. DC testing
uses a combination of threshold and hard levels to assure
datasheet guarantees. Input threshold levels are usually
guaranteed through VOL and VOH tests.
In other words: PTOTAl = POO
Where:
POINT
+
POOUT
POO
= Quiescent Power Dissipation
= Internal Dynamic Power Dissipation
-
POOUT
= Output Power Dissipation
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First the Quiescent power can be derived from the following
equation.
[IC~l. NOOl • vcc]
+
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POINT
POO =
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= Total Power Dissipation
PTOTAl
High level noise immunity is the difference between VOH
and VIH and low level noise immunity is the difference between Vil and VOL. Noise-free VIH or Vil levels should not
induce a switch on the appropriate output of an ABT device.
When testing in an automated environment, extreme caution should be taken to ensure that input levels plus noise
do not go into the transition region.
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[lc~H • NOOH • Vcc]
Dynamic System Power Dissipation
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Where:
One of several advantages to using BiCMOS logic is its low
power when compared to bipolar technologies. As well, it
has reduced dynamic output power because of the reduced
output swing in comparison to CMOS devices. In the static
or quiescent high state, SCAN ABT will consume power like
a pure CMOS device, and in the quiescent low state all power goes to driving the bipolar output pull-down transistor.
POO
= Quiescent Power Dissipation
ICCH
= Quiescent Power Supply Current with All Out-
ICCl
= Quiescent Power Supply Current with All Out-
puts High
puts Low
NOOl = Number of Quiescent Outputs Low
NOOH = Number of Quiescent Outputs High
NOIH
= Number of Quiescent Inputs High
N
= Number of Active Outputs
Dice
= Power Supply Current for Input with VIN other
than Vcc
DC
AC
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FIGURE9
3-9
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Dissipation (Continued)
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[ (N*NS*DL)*Vcc + [(Icco*f*NS)*Vccl
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1. Vcc = 5V
2. The data and control inputs are being driven with OV and
3.4V voltages for logic levels.
3. Data input frequency = 16 MHz @ 50% duty cycle.
4. Cl = 50 pF
5. There are no DC loads on the outputs, Le., outputs are
either unterminated or terminated with an AC shunt termination.
6. Since the output high voltage is produced by a Darlington
transistor pair, the output voltage swing will be assumed
to be Vcc - 1.6V or 5.0 - 1.6V = 3.4V. Therefore VS =
3.4V with Vcc = 5.0V.
For quiescent current, all data inputs and outputs are
switching leaving only the 2 OE inputs static low.
POINT = [(Dlcc*DH*NS)*Voo] +
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Assumptions:
Secondly, a SCAN ABT device will dissipate power internally by charging and discharging internal capacitiance. The
following equation takes into account the duty cycle of inputs and outputs and current due to the internal switching of
capacitances.
Where:
POINT = Internal Dynamic Power Dissipation
Vcc = Power Supply Voltage
Dlcc = Power Supply Current for Input with VIN other
than Vcc (For example, a typical TTL input voltage is considered to be 3.4V)
Note: The farther away an input (VIN) is from threshold
(1.5V), the less power supply current the Ie will consume.
N
DH
DL
ICCl
lcCl
]
Poa = [ N*NaOl *Vcc + [Dl cc*NaIH*Vcc1 +
=
=
=
=
Number of Active Outputs
Duty Cycle for Switching Inputs High
Duty Cycle for Switching Outputs Low
Data book specification for power supply current with all outputs low
Icco = Power consumption coefficient (rnA/MHz) for
1-bit toggling
= Frequency of Outputs
NS
= Number of Outputs Switching
Finally, at high frequencies a significant amount of current is
consumed by a device to drive its output load. SCAN ABT
has an advantage here because of its reduced output swing
compared to CMOS devices. For a simple case, if we assume only capacitive components to the load, we can use
the following equation.
[IC~H*NaOH*Vcc ]
=0+0+0=0
Internal Dynamic Current
ICCl
POINT = [(Dlcc*NS*DH)*Voo] + [(N*NS*DL)*Vcc1
+ [(lcco*f*NS)*Vcc1
POINT = [(2.5e-3*18*0.5)*5.0]
= 5.60 + 1.66 + 144
= 151.3 mW
Finally the Output Current
POUT = [Cl * VS * f] * Vcc
POUT = [50.e-12*3.4V*16e6] * 5.0
= [2.72e-3]*5
= 13.5 mW
Where:
Output Power Dissipation
Load Capacitance
Output Voltage Swing
Output Operating Frequency
Power Supply Voltage
PTOTAl = Poa + POINT + POOUT
= 0 + 151.3 mW + 13.5 mW
PTOTAl = 164.8 mW
Take for an example a SCAN182244A with all 18 outputs
switching at 16 MHz. How much power would be consumed
by the IC in this case?
http://www.national.com
30e-3
[(----;s-*8*0.5)*5.0]
+ [(0.1*16*18)*5.0]
POUT = [Cl * VS * f] * Vcc
POOUT =
=
Cl
=
VS
=
f
=
Vcc
+
3-10
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ABT Process Characteristics
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PROCESS CHARACTERISTICS
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PROCESS FLOW
National's 1.0 jJ.m BCT process combines bipolar and
CMOS transistors in a single process to achieve high speed,
high drive characteristics while maintaining low tri-state
power and the ability to control noise.
National's 1.0 jJ.m BCT process provides a suitable platform
for migration to higher performance levels with minor technology enhancements planned for the near future. In its
present form, the technology supports Interface, Digital, Bus
and Telecom products from National Semiconductor.
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
PROCESS FEATURES
• 18 masking layers using stepper lithography
• 100% ion implantation utilized for dopant placement
• Localized retrograde wells tailored for high performance
• Optimized recessed and field isolation sequence for
CMOS/bipolar
• NMOS LDD (Lightly Doped Drain), PMOS Halo
architecture
• 150A gate oxide
• Self aligned bipolar contact set utilizing minimum
geometries
C
Buried Layer
P-Well
N-Well
Isolation
Sink
Active
Active Strip
Poly
Base
Bipolar Contact
Emitter
P+ Source/Drain
N+ Source/Drain
Contact
Metal 1
Via
Metal 2
Passivation
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PROCESS PARAMETERS
• Bipolar Performance: 10 GHz Ft with gains greater than
100
• Localized retrograde sub-emitter collector
• Advanced planarization on all topographies
• CMOS Performance: 0.5 jJ.m min Left
• PtSi Schottky diodes, all contacts use platinum for
resistance reduction
• Platinum Schottky diodes for TTL
• Typical ESD Performance:
Method
• Barrier metal of TiW
• Dual layer metal of AI-Cu 0.3% for long term reliability
> 2000V, Human Body
• Robust latch-up and punch-through protection with
retrograde wells
• Metal pitch of 3.5 microns
• Advanced interconnect supports superior temperature
cycle performance
ISOLATION
OX
CHANNEL
STOP
N-WELL
P-WELL
CHANNEL
STOP
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BIPOLAR
__--------J
~--------~v
~--------~v---------~
PMOS
NMOS
TL/F/12133-10
FIGURE 10. 1.0 jJ.m BCT Process Cross SectIon
3-11
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3. Terminate all inputs and outputs to ensure proper loading
of the outputs and that the input levels are at the correct
voltage.
SCAN CMOS Test Access Logic
SCAN CMOS features low power consumption. Products
are used in board test by surrounding clusters of nonboundary scan devices to create a fully 1149.1 compliant
board. SCAN CMOS provides adequate drive and buffering
for microprocessors, too. For more information on Advanced CMOS devices, refer to the FACT Databook.
4. Set VOO to 5.0V.
5. Set the word generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measurement.
6. Set the word generator input levels at OV LOW and 3V
HIGH. Verify levels with a digital volt meter.
SCAN CMOS logic is manufactured on a 1.3 Ilm process
and offers a good combination of high speed, low power
dissipation, high noise immunity, wide fanout capability and
high reliability.
VOLP/VOLV and VOHPIVOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50n coaxial cable plugged into a standard
5MB type connector on the test fixture. Do not use an
active FET probe.
Characteristics
Meets or Exceeds JEDEC Standards for 74ACXX
Family
High
-
Performance Outputs
Common Output Structure
Output Sink/Source Current of -24/48 rnA
Transmission Line Driving 50n (Commercial)175n
(Military) Guaranteed
Temperature Range
- Commercial
- Military
ACTIVE
OUTPUTS
J ______ X,.--J
•
OH
V
•
'-----VOL
QUIET
OUTPUT
-40°C to + 85°C
- 55°C to + 125°C
UNDER TEST
Improved ESD Protection Network
~~~ ~~~ ~ ~ ~ ~~ ===: ~~~P
.-----------------.~~
High Current Latch-Up Immunity
TL/F/12133-11
FIGURE 11" Quiet Output Noise Voltage Waveforms
Patented Noise Suppression Circuitry
Note A: VOHV and VOLP are measured with respect to ground reference.
Noise Immunity
Note B: Input pulses have the following characteristics: f
3 ns, tf = 3 ns, skew < 150 ps.
The DC noise immunity of a logic family is also an important
equipment cost factor in terms of decoupling components,
power supply dynamic resistance and regulation as well as
layout rules for PC boards and signal cables.
1 MHz, tr
=
• Measure VOlP and VOlV on the quiet output LOW during
the HL transition. Measure VOHP and VOHV on the quiet
output HIGH during the LH transition.
The input threshold of a device and the output voltage,
IVIL - voLl/iVlH - vOHI at 4.5V Voo, for SCAN CMOS is
1.25V/1.25V.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
Noise Characteristics
VllO and VIHO:
• Monitor one of the switching outputs using a 50n coaxial
cable plugged into a standard 5MB type connector on
the test fixture. Do not use an active FET probe.
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the noise
characteristics of SCAN CMOS.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate. Oscillation is defined as noise
on the output LOW level that exceeds VIL limits, or on
output HIGH levels that exceed VIH limits. The input
LOW voltage level at which oscillation occurs is defined
as VILO.
• Next decrease the input HIGH voltage level on the word
generator, VIH until the output begins to oscillate. Oscillation is defined as noise on the output LOW level that
exceeds VIL limits, or on output HIGH levels that exceed
VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHO.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture or Equivalent
Tektronics Model 7854 Oscilloscope or Equivalent
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF, 500n.
2. Deskew the word generator so that no two channels have
greater than 150 ps skew between them. This requires
that the oscilloscope be deskewed first. Swap out the
channels that have more than 150 ps of skew until all
channels being used are within 150 ps. It is important to
deskew the word generator channels before testing. This
will ensure that the outputs switch simultaneously.
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• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
3-12
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Noise Characteristics (Continued)
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FIGURE 12" Simultaneous Switching Test Circuit
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Secondly, a SCAN CMOS device will dissipate power dynamically by charging and discharging internal capacitance.
This can be calculated by using the following formula:
Output Characteristics
All SCAN CMOS outputs are buffered to ensure consistent
output voltage and current specifications. Two clamp diodes
are internally connected to the output pin to suppress voltage overshoot and undershoot in noisy system applications
which can result from impedance mismatching. The balanced output design allows for controlled edge rates and
equal rise and fall times.
Eq.2.
POINT = [(lOOT· DH • NT) • VOO] +
[ (CpO • Vs • f) .VOO]
POINT = Internal Dynamic Power Dissipation
lOOT = Power Supply Current for a TTL HIGH
Input (VIN = 3.4V)
DH
= Duty Cycle for TTL Inputs HIGH
NT
= Number of TTL Inputs at DH
VOO = Power Supply Voltage
Cpo = Device Power Dissipation Capacitance
Vs
= Output Voltage Swing
f
= Internal Frequency of Operation
All SCAN CMOS devices are guaranteed to source 48 rnA
and sink - 24 rnA. Commercial devices are capable of driving 50n transmission lines.
Circuit Characteristics
POWER DISSIPATION
One advantage to using CMOS logic is its extremely low
power consumption. But DC power consumption is not the
whole picture. Any circuit will have AC power consumption,
whether it is built with CMOS or bipolar technologies.
CPO values are specified for each device and are measured
per JEDEC standards as described in this section. On device data sheets, Cpo is a typical value and is given either
for the package or for the individual stages with the device.
Vs and Voo are the same value and can be replaced by
V002 in the formula.
Total power dissipation of SCAN CMOS device under AC
conditions is a function of three basic sources, quiescent
power, internal dynamic power, and output dynamic power
dissipation.
Thirdly, a SCAN CMOS device will dissipate power dynamically by charging and discharging any load capacitance.
This can be calculated by using the following formula:
Firstly, a SCAN CMOS device will dissipate power in the
quiescent or static condition. This can be calculated by using the formula: (Note: In many datasheets 100, ~Ioo, lOOT,
and Voo are referred to as Icc, ~Icc, ICCT' and Vcc, respectively. There are no differences.)
Eq. 1
PDQ =
PDQ
100
VOO
Eq. 3
100 • VOO
= Quiescent Power Dissipation
= Quiescent Power Supply Current Drain
= Power Supply Voltage
3-13
PDOUT =
PDOUT
CL
Vs
f
Voo
(CL • Vs • f) • Voo
Output Power Dissipation
Load Capacitance
Output Voltage Swing
Output Operating Frequency
= Power Supply Voltage
=
=
=
=
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In many cases the output frequency is the same as the internal operation frequency. Also Vs is similar to VOO and
can be replaced by V002.
The 100 calculations are as follows:
100 Total
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best described as:
Input 100
= (lOOT)
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PDTOTAL = PDQ + PDOYNAMIC or
P~OTAL = PDQ + POINT + PDOUT
The following is an exercise in calculating total dynamic 100
for SCAN CMOS. The device used as an example is the
SCAN18245T. Static 100, lOOT and CPO numbers can be
found in the datasheet. 100 numbers used will be worstcase commercial guarantees. Room temperature power will
be less. These are approximate worst-case calculations.
Eq.4
x (number of TTL inputs)
Cycle)
= (2 x 10- 3 ) x (1) x (0.50)
=
+
Output
x (Duty
1.0 mA per input being toggled at TTL levels
Internal 100 = (VSWING) x (CPO) x (CP freq)
= (5.0) x (41 x 10- 12) x (16 x 10+ 6)
= 3.28 per mA per input being toggled by CP
Output 100 = (VSWING X (CO
CL = 50 pF
= (5.0) x (50
The following assumptions have been made:
=
1. 100 will be calculated per input/output (as per JEDEC
Cpo calculations). The total for the SCAN18245T will be
the calculated 100 x 18.
2. Worst case conditions and JEDEC would require that the
data is being toggled at the clock frequency in order to
change the outputs at the maximum rate (% CP).
x (Q freq)
x 10- 12) x (8 x 10+ 6)
2 mA per output toggled at
% CP
Adding Input, Internal and Output 100 together and multiplying by 18 1/0 per SCAN18245T, the approximate worstcase 100 calculations are as follows:
CL
=
50 pF
100 total
=
100.48 mA or 502.4 mW· at a
CP of 16 MHz
("Power is obtained by multiplying 100 by Voo)
3. The data and clock input signals are derived from TTL
level drivers (OV to 3.0V swing) at 50% duty cycle.
4. The clock frequency is 16 MHz.
5. 100 will be calculated for CL = 50 pF.
6. VOO = 5V.
7. Total POWER dissipation can be obtained by multiplying
total 100 by Voo (5.0V).
8. Quiescent 100 will be neglected in the total 100 calculation because it is 1000 times less than dynamic 100.
9. There is no DC load on the outputs, i.e. outputs are either
unterminated or terminated with series or AC shunt termination.
http://www.national.com
Input 100 + Internal Switching 100
Switching (AC load) 100
3-14
Section 4
Loading Specifications,
Waveforms, Quality and
Reliability
htto:/Iwww.naiional.r.nm
Section 4 Contents
Definition of Terms .................................................................
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Loading and Waveforms .........................................................
Waveforms-Normal Operation ......................................................
Waveforms-Scan Test Operation......................... ...........................
Quiet Output Noise ...................................... . . . . . . . . . . . . . . . . . . . . . . . . . . .
Skew Definitions and Examples ........................... . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characterization and Test Specifications ..............................................
Philosophy ........................................... . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Dynamic (Noise) Characteristics..................... ...........................
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power..........................................................................
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality Information and Communication (QUIC) System.... ...........................
Wafer Level Reliability (WLR) ........................... . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic Discharge Sensitivity (ESD) ............................................
Power Sensitivities for Minimum Geometry Products ..................................
Latchup Testing....... ................................ ...........................
4-2
4-3
4-3
4-4
4-4
4-5
4-6
4-6
4-7
4-8
4-9
4-9
4-9
4-9
4-9
4-9
4-1 0
4-10
4-10
4-1 0
4-11
4-11
4-12
4-14
4-14
(fINational Semiconductor
Loading Specifications, Waveforms,
Quality and Reliability
Definition of Terms
DC Characteristics
10ZH
Currents: Positive current is defined as conventional current flow into a device. Negative current is defined as current flow out of a device. All current
limits are specified as absolute values.
Voltages: All voltages are referenced to the ground pin. All
voltage limits are specified as absolute values.
ISVI
Input HIGH Current (Breakdown Test). The current
flowing into an input when a specified Absolute
MAX HIGH voltage is applied to that inD'It.
ISVIT
1/0 Pin HIGH Current (Breakdown Te~ The current flowing into a disabled (output is high impedance) 1/0 pin when a specified Absolute MAX HIGH
voltage is applied to that 1/0 pin.
ICEX
Output HIGH Leakage Current. The current flowing
into a HIGH output due to the application of a specified HIGH voltage to that output.
ICCH
The current flowing into the Vce supply terminal
when the outputs are in the HIGH state.
ICCl
The current flowing into the Vce supply terminal
when the outputs are in the LOW state.
ICCT
Iccz
III
IIH
10H
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Izz
Vcc
VCD
VID
VIH
VIHD
Vil
Additional Icc due to TIL HIGH levels forced on
CMOS inputs.
The current flowing into the Vcc supply terminal
when the outputs are disabled (high impedance).
Input LOW Current. The current flowing out of an
input when a specified LOW voltage is applied to
that input.
Input HIGH Current. The current flowing into an input when a specified HIGH voltage is applied to that
input.
Output HIGH Current. The current flowing out of an
output which is in the HIGH state.
Output LOW Current. The current flowing into an
output which is in the LOW state.
Output Short Circuit Current. The current flowing
out of an output in the HIGH state when that output
is shorted to ground (or other specified potential).
Output OFF current (LOW). The current flowing out
of a disabled TRI-STATE® output when a specified
LOW voltage is applied to that output.
VllD
VOH
VOHV
VOL
VOlP
VOlV
4-3
Output OFF current (HIGH). The current flowing
into a disabled TRI-STATE output when a specified
HIGH voltage is applied to that output.
Bus Drainage. The current flowing into an output or
1/0 pin when a specified HIGH level is applied to
the output or 1/0 pin of a power-down device.
Supply Voltage. The range of power supply voltages over which the device is guaranteed to operate.
Input Clamp Diode Voltage. The voltage on an input
( -) when a specified current is pulled from that input.
Input Breakdown Voltage. The voltage on an input
of a powered-down device when a specified current
is forced into that input.
Input HIGH Voltage. The minimum input voltage
that is recognized as a DC HIGH-level.
Dynamic Input HIGH Voltage. The minimum input
voltage that is recognized as a HIGH-level during a
Multiple Output Switching (MaS) operation.
Input LOW Voltage. The maximum input voltage
that is recognized as a DC LOW-level.
Dynamic Input LOW Voltage. The maximum input
voltage that is recognized as a LOW-level during
Multiple Output Switching (MaS) operation.
Output HIGH Voltage. The voltage at an output
conditioned HIGH with a specified output load and
Vcc supply voltage.
Minimum (valley) voltage induced on a static HIGH
high output during switching of other outputs.
Output LOW Voltage. The voltage at an output conditioned LOW with a specified output load and Vcc
supply voltage.
Maximum (peak) voltage induced on a static LOW
output during switching of other outputs.
Minimum (valley) voltage induced on a static LOW
output during switching of other outputs.
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AC Characteristics
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three decibels.
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tPZH Output Enable Time (of a TRI-STATE Output) to a
HIGH Level-The time between the 1.5V levels of the input
and output voltage waveforms with the TRI-STATE output
changing from a high impedance (OFF) state to a HIGH
level.
f max Toggle Frequency/Operating Frequency-The
maximum rate at which clock pulses may be applied to a
sequential circuit. Above this frequency the device may
cease to function.
tpZL Output Enable Time (of a TRI-STATE Output) to a
LOW Level-The time between the 1.5V levels of the input
and output voltage waveforms with the TRI-STATE output
changing from a high impedance (OFF) state to a LOW levels.
tpLH Propagation Delay Time-The time between the
specified reference points, normally 1.5V on the input and
output voltage waveforms, with the output changing from
the defined LOW level to the defined HIGH level.
tree Recovery Time-The time between the 1.5V level on
the trailing edge of an asynchronous input control pulse and
the same level on a synchronous input (clock) pulse such
that the device will respond to the synchronous input.
tpHL Propagation Delay Time-The time between the
specified reference points, normally 1.5V on the input and
output voltage waveforms, with the output changing from
the defined HIGH level to the defined LOW level.
AC Loading and Waveforms
tw Pulse Width-The time between 1.5V amplitude points
of the leading and trailing edges of a pulse.
th Hold Time-The interval immediately following the active
transition of the timing pulse (usually the clock pulse) or
following the transition of the control input to its latching
level, during which interval the data to be recognized must
be maintained at the input to ensure its continued recognition. A negative hold time indicates that the correct logic
level may be released prior to the active transition of the
timing pulse and still be recognized.
ts Setup Time-The interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or
preceding the transition of the control input to its latching
level, during which interval the data to be recognized must
be maintained at the input to ensure its recognition. A negative setup time indicates that the correct logic level may be
initiated sometime after the active transition of the timing
pulse and still be recognized.
For Normal Operation Figures 1 and 2 show waveforms for
all propagation delay and pulse width measurements while
Figures:3 and 4 show waveforms for TRI-STATE enable and
disable times. The waveforms shown in Figure 5 describe
setup, hold and recovery times. These diagrams define all
input and output measure points used in testing devices in
the Normal Operation Mode.
For SCAN Test Operation, Figure 8 shows propagation delay waveforms; Figures 9 and 10, TRI-STATE enable and
disable times waveforms; Figure 11 Set up, hold, and recovery time waveforms and Figure 12, Pulse Width waveform.
Figure 6 shows the AC loading circuit used in characterizing
and specifying propagation delays of all devices, unless otherwise specified in the data sheet of a specific device. The
value of the capacitive load (Cd is variable and is defined in
the AC Electrical Characteristics.
The 500n resistor to ground in Figure 6 is intended to slightly load the output and limit the quiescent HIGH-state voltage
to about + 3.5V. Also shown in Figure 6 is a second 500n
resistor from the device output to a switch. For most measurements this switch is open; it is closed for measuring a
device with open-collector outputs and for measuring one
set of the Enable/Disable parameters (LOW-to-OFF and
OFF-to-LOW) of a TRI-STATE output. With the switch
closed, the pair of 500n resistors and the + 7.0V supply
establishes a quiescent HIGH level of + 3.5V, which correlates with the HIGH level discussed in the preceding paragraph.
Figures 7a and 7b describe the input pulse requirements
necessary when testing circuits.
tpHZ Output Disable Time (of a TRI-STATE Output) from
HIGH Level-The time between the 1.5V level on the input
and a voltage 0.3V below the steady state output HIGH level with the TRI-STATE output changing from the defined
HIGH level to a high impedance (OFF) state.
tpLZ Output Disable Time (of a TRI-STATE Output) from
LOW Level-The time between the 1.5V level on the input
and a voltage 0.3V above the steady state output LOW level
with the TRI-STATE output changing from the defined LOW
level to a high impedance (OFF) state.
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FIGURE 2. Propagation Delay, Pulse
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FIGURE 4. TRI-STATE Output Low
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FIGURE 3. TRI-STATE Output High
Enable and Disable Times
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FIGURE 5. Setup Time, Hold
Time and Recovery Time
TL/F/12134-6
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FIGURE 6. Standard AC Test Load
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FIGURE 7a. Test Input Signal Levels
FIGURE 7b. Test Input Signal Requirements
4-5
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FIGURE 10. TRI·STATE Output Low
Enable and Disable Times
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FIGURE 11. Setup Time, Hold
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= 1.5V
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QUIET
OUTPUT
UNDER TEST ~- - - - - - - - - - - - - - - - - - - VOlP
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- - - - - - - - - - - - - - - - - - - VOlV
FIGURE 13. Quiet Output Noise Voltage Waveforms
Note A: VOHV and VOlP are measured with respect to ground reference.
Note B: Input pulses have the following characteristics: f
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Tl/F/12134-13
Skew Definitions and Examples
Minimizing output skew is a key design criteria in today's
high-speed clocking schemes, and National has incorporated skew specifications into the SCAN CMOS family of devices.
Example:
If signal appears at out # 1 in 3 ns and in 4 ns at output # 5,
the skew is 1 ns.
Without skew specifications, a designer must approximate
timing uncertainties. Skew specifications have been created
to help clock designers define output propagation delay differences within a given device, duty cycle and device-to-device delay differences.
This section provides general definitions and examples of
skew.
CLOCK SKEW
Skew is the variation of propagation delay differences between output clock signal(s). See Figure 15.
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Load capacitors are placed
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TL/F/12134-15
FIGURE 15. Clock Output Skew
SOURCES OF CLOCK SKEW
Total system clock skew includes intrinsic and extrinsic skew. Intrinsic skew is defined as the differences in delays between the
outputs of device(s). Extrinsic skew is defined as the differences in trace delays and loading conditions.
INTRINSIC SKEW
EXTRINSIC SKEW
OUT
SKEW DUE TO
DEVICE AND TRACE/LOAD DELAYS
TL/F/12134-16
FIGURE 16. Sources of Clock Skew
Example: 50 MHz Clock signal distribution on a PC Board.
50 MHz signals produces 20 ns clock cycles
Total system skew budget = 10% of clock cycle" = 2ns
If extrinsic skew = 1 ns
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Device skew (intrinsic skew) must be less than 1 nsf
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'Clock Design Rule of thumb.
4-7
http://www.national.com
Skew Definitions and Examples (Continued)
CLOCK DUTY CYCLE
• Clock Duty Cycle is a measure of the amount of time a signal is High or Low in a given clock cycle.
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FIGURE 17. Duty Cycle Calculation
Clock Signal
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Example:
tHIGH and tLOW are each 50% of the clock cycle therefore
the clock signal has a Duty Cycle of 50/50%.
TLIF/12134-1B
FIGURE 18. Clock Cycle
Clock
+
• Clock skew effects the Duty Cycle of a signal.
Skew
Example: 50 MHz clock distribution on a PC board.
TLIF/12134-19
Skew must be guaranteed less than 1 ns at 50 MHz to
achieve 55/45% Duty Cycle requirements of core silicon!
FIGURE 19. Clock Skew
TABLE I
System
Frequency
Skew
tHIGH
tLOW
Duty Cycle
50MHz
50 MHz
50 MHz
o ns
10 ns
12 ns
11 ns
10 ns
8 ns
9 ns
50/50%
60/40%
55/45%
+0-
Ideal Duty Cycle (50/50%) occurs for zero skew.
2ns
1 ns
33 MHz
2 ns
17 ns
15 ns
55/45%
+0-
Note that at lower frequencies, the skew budget is not as tight
and skew does not effect the Duty Cycle as severely as seen at
higher frequencies.
Definition of Parameters
tOSLH. tOSHL (Common Edge Skew)
tOSHL and tOSLH are parameters which describe the delay from one driver to another on the same chip. This specification is the
worst-case number of the delta between the fastest to the slowest path on the same chip. An example of where this parameter
is critical is the case of the cache controller and the CPU, where both units use the same transition of the clock. In order for the
CPU and the controller to be synchronized, toSLH/HL needs to be minimized.
Definition
Example
tOSHL. tOSLH (Output Skew for High-to-Low Transitions):
CLOCK
INPUT
tOSHL = ItPHLMAX - tPHLMINI
Output Skew for Low-to-High Transitions:
OUTPUT 1
tOSLH = ItPLHMAX - tpLHMINI
Propagation delays are measured across the outputs of any
given device.
OUTPUT 2
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4-8
rPulse Width (synchronous logic)
Pulse Width testing is used to define the minimum
pulse duration that a flip-flop or latch input will accept and still function properly. This test is package
and test environment sensitive.
Characterization and Test
Specifications
Philosophy
During the product introduction process for National logic
IC's, a new IC design will undergo a rigorous characterization to baseline its performance. This data is required to
correlate with simulation models, determine product specifications, compare performance to other product, provide a
feedback mechanism to the fabrication process, and for
customer information. National's Logic IC characterizations
are designed to get as much information as possible about
the product and potential customer application performance.
F-Toggle (asynchronous logic)
F-Toggle is the minimum frequency at which the IC
is guaranteed to function under multiple outputs
switching condition with outputs operating in phase.
This test is package and test environment sensitive.
National's logic IC characterization methodology uses past
knowledge of design performance, simulation, and process
parametrics to determine what electrical parameters to
characterize. Characterization samples are selected so that
they have key process parametrics (e.g., Drive, Beta, Vtn,
Vtp Left, etc.) which have been shown to significantly affect
device electrical parameters. Data is acquired and processed using statistical analysis software. Manufacturing test
limits are then set using the knowledge of variations due to
fabrication, package, tester, Vee, temperature, and condition. This allows product to be shipped on demand without
problems or delays.
Measured parameters with 50 pF loading relate the
amount that a static conditioned output will change
in voltage under multiple outputs switching condition
with outputs operating in phase. They are heavily
influenced by the magnitude that Vee and Ground
move internal to the IC.
tpLH
tpHL
Active Propagation Delays
tPZH
tPZL
Enable Propagation Delays
This test is performed to determine what minimum
edge rate can be applied to an input and have the
corresponding output transition with no abnormalities such as glitches or oscillations.
DC Electrical Characteristics
Automated Test Equipment (ATE) DC Tests
DC test data gathered show the performance of an
IC to statically applied voltages and currents.
Functional Shmoo
The function shmoo shows the function operational
window of an IC at a wide range of Vee's and temperatures.
Power Up & Power Down Output Shmoo
Similar to the function shmoo, the power up and
power down output shmoo shows the DC operation
of an output during power up and power down conditions.
Multiple (Simultaneous) Output Switching Propagation
Delays
These tests are used to ensure compliance to the
extended databook specifications and include active
propagation delays, disable and enable times at 50
pF and 250 pF output loads.
Transfer Characteristic (VIN/Vour)
Input Traces (VIN/lIN)
Output Traces (VOL/lOL, VOH/lOH)
Multiple Output Switching Skew
Performance data from the Multiple Output Switching propagation delay testing is analyzed to obtain
information regarding output skew of an IC.
Power
Power-Up Icc Traces
Shows how the supply current reacts to various input conditions during power up.
FMAX (synchronous logic)
FMAX determines the minimum frequency at which
the device is guaranteed to operate for a clocked IC.
This test is package and test environment sensitive.
Icc vs VIN Traces
Traces of lee vs VIN show how the supply current
changes with input voltage.
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tpHZ
Also included are input timing parameters
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Dynamic threshold measures the shift of an IC's input threshold due to noise generated while under
multiple outputs switching condition with outputs operating in phase. This test is package and test environment sensitive.
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Single Output Switching propagation delays
Testing includes measured propagation delays at 50 pF and
250 pF output load capacitances.
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AC Electrical Characteristics
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The following are brief summaries of characterization tests
performed.
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Determines the amount of current an IC will consume at frequency.
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As a matter of policy, it is NSC's goal to design and manufacture product that is 100% defect-free and capable of surviving the qualification tests with zero failures. This policy is
not interpreted as a directive to abandon a qualification program when failures occur or to delay new product releases
until perfection has been achieved. Rather, the policy is intended to focus engineering resources on the identification
and elimination of the design, process, or workmanship deficiencies that are the root causes of the failures and then to
engineer a solution to correct those deficiencies.
Input/Output Capacitance (CIN/COUT)
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cess, or package, share a joint responsibility for demonstrating that the product does conform to NSC standards and to
the standards and expectations of NSC's customers.
Power (Continued)
Testing determines if an IC is susceptible to latch-up
from over-current or over-voltage stresses per
MIL-STD-883 JEDEC method 17.
Results from the initial qualification for the SCAN ABT Advanced Logic families are published in Self Qualification
handbooks. Additional stress testing is performed regularly
as a reliability monitor as part of the Fast Reaction Program
and Long Term Audit Program. The Self Qualification handbook contains the data typically requested by customers as
part of joint qualification programs in addition to detailed
explanations of all tests performed. The Logic self qualification handbook may be obtained by contacting the Customer
Response Center at 1-800-272-9959.
HBM Electrostatic Discharge, Human Body Model
Per MIL-STD-883C method 3015.6.
Quality and Reliability
Introduction
Product qualification is a disciplined, team activity which focuses on demonstrating, through the acquisition and analysis of engineering data, that a device design, fab process, or
package design meets or exceeds minimum standards of
performance. In most cases, this involves running samples
of product through a series of tests which expose the samples to operating stresses far in excess of those which
would be encountered in even the most severe "real life"
operating environment. These tests are called either accelerated stress tests or accelerated life tests. A properly designed qualification test sequence exposes, within a matter
of days or weeks, those design, materials, or workmanship
defects which would lead to device failure in the customer's
application after months or even years of operation.
TABLE II. Qualification Requirements for
Logic Integrated Circuits
Test
In order to be considered a "world class" supplier of semiconductor devices, NSC designs and manufactures products which are capable of meeting the reliability expectations of its most demanding customers. While customer requirements and expectations vary on the subject of reliability requirements for devices, virtually all large users have
general procurement specifications which establish failure
rate goals or objectives for the suppliers of the components
used in their products.
Test
Method
Test/Stress
Conditions
Sample
Size
Each Lot
Operating Life
SOP-5-049-RA 1000 Hours
Method 107
@TA = 125·C
77
High Temperature Storage
SOP-5-049-RA 1000 Hours
@150·C
Method 103
45
Temperature
Cycle
SOP-5-049-RA 1000 Cycles
- 65·C to + 150·C
Method 105
77
Temperature
Cycle with
Preconditioning
SOP-5-049-RA 1000 Cycles
- 65·C to + 150·C
Method 105
TemperatureHumidity-Bias
SOP-5-049-RA 1000 Hours
85·C@85%RH
Method 104
77
77
TemperatureHumidity-Bias
with Preconditioning
Method 112
Method 104
Precondition
plus 100 hours
85·C to 85%RH
Failure rate goals for infant mortality and long-term-failurerate-in-service have been established for all NSC product
lines. These goals are published internally at the beginning
of each fiscal half-year (usually June and December). The
actual performance of the product against these goals is
measured monthly using life test data gathered from various
sources including the Fast Reaction and Long Term Audit
Program. Performance is reviewed every six (6) months by
Reliability and Product Group management and adjusted as
necessary to reflect customer expectations, competitive
data, and/or historical performance trends.
Autoclave
Method 101
500 hours
121·C @15 psig
45
Thermal Shock
Method 106
100 Cycles
- 65·C to + 150·C
22
Salt Atmosphere
Method 209
25 Hours 35·C
Resistance to
Solvents
Method 207
4 Solvents
Lead Integrity
Method 205
Condition as
Appropriate
to Package
Given that product reliability is an overriding corporate objective, and that any deficiency in design, materials, procedures, or workmanship, has a potential for adversely affecting the reliability of the product, Manufacturing and Engineering organizations within NSC, its subsidiaries, and its
sub-contractors, involved in introducing a new device, pro-
Solderability
Method 203
8 Hour Steam
5 secs @260·C
22
Solder Heat
Method 204
12 secs 260·C
22
http://www.national.com
4-10
77
22
3 Each
Solvent
22 Leads
As device complexity increases, the testing sample size required to ensure infant mortality ppm levels in the 0-10 ppm
range will quickly deplete reliability test capacity. While
burn-in eliminates inferior devices, it can also substantially
shorten the lifetimes of "good" devices to an unacceptable
level, creating an expensive and somewhat risky procedure.
New technology advances which minimize geometry, have
moved our device lifetime distributions closer to our customer's expected system life. As device geometries shrink, resulting in higher current densities, electric fields, and chip
temperatures, tighter fab process control and instant feedback become critical.
Quality Information and Communication (QUIC) System
BACKGROUND
National's Quality Assurance Systems Development group
(QASD) maintains a variety of data tracking systems such
as: Electronic Reliability Data Management (ERDM), Failure
Analysis (F/A), Burn-in Board Inventory, and a number of
others.
QUIC users will find a user friendly, menu-driven, real-time
system that gives them a simultaneous-user environment
with timely data inputs from sites around the world. QUIC is
programmed to recognize each individual user of the system at the point of logging on to the mainframe, and provides an appropriate list of menu options consistent with the
user's level of access requirements.
THE GOAL OF WAFER-LEVEL-RELIABILITY TESTINGPROCESS RELIABILITY
Wafer-level-reliability testing represents a proactive, correlation and control approach to ensuring device reliability. WLR
is not meant to replace classical reliability testing. Instead it
is used to supplement existing methods.
National grants access to QUIC by customers that provides
a sufficient level of security over the entire system, thus
precluding the possibility of accidental access (or even
damage) to various files.
WLR testing is used to:
1. Identify shifts in On-Line Process Controls (fab monitors) which affect product reliability.
HOW A CUSTOMER LINKS TO QUIC
2. Reduce process qualification cycle time.
1. Check to make sure you have the hardware components
listed below. (An attached printer is desirable but not imperative.)
3. Improve process qualification success rate.
4. Assess reliability trends of production processes.
IBM/PC compatible computer with at least 128k memory.
5. Quantify the reliability impact of process modifications.
Hayes compatible 1200 baud modem (or 2400,4800 or
9600).
WLR provides faster feedback for fab process control. The
collection of WLR test data during and at the end of wafer
fab processing provide a reliability baseline for each of our
fab processes. Shifts in WLR test results, whether intentional (a process change or qualification) or unintentional (a process control problem), signal an increase or decrease in
product reliability risk. WLR monitoring of production processes using Statistical Quality Control (SQC) techniques
provides engineering with the information required to find
and fix process control problems faster, and to determine
the effectiveness of on-line process controls from a reliability standpoint. In this way, WLR testing is used to link on-line
process controls to the traditional accelerated life testing
methods.
Touch tone phone.
2. Request access to QUIC by contacting your National
sales representative or Customer Service Center at
1-800-272-9959, who will coordinate all activities necessary to provide access for your company and arrange
training (usually handled over the telephone).
3. Identify the person who will be your company's main contact and user of the QUIC system. This person will assume responsibility for the USERID assigned to your
company and will receive training on how to access and
use the QUIC system.
4. National will provide a USERID, password and account
number with appropriate menus and a communications
software package called EXECULlNK, which allows the
customer's PC to talk with NSC's host computer and also
turns the PC into a virtual host terminal, with full-screen
editing capability and full use of program function (PF)
keys. EXECULINK also provides for file transferring between host and PC and spooling of print files to a PC-attached printer.
NATIONAL'S WLR PROGRAM
National developed a corporate-wide WLR program which
continues to implement powerful, new test techniques. WLR
testing has been used effectively to help understand how
process variability affects product reliability. It is also used
to help build-in reliability at the design stage for new process technologies.
WLR tests and test structures have been designed to increase the likelihood and predict a rate of a reliability failure
mechanism occurrence. In addition, National has developed
a partnership with a leading parametric test system supplier.
Working together, a WLR test system was designed and
developed to meet the unique requirements of Wafer-LevelReliability testing. These systems are capable of testing to
the voltage, current, and temperature extremes required for
inducing the desired failure mechanisms in a short period of
time. Some examples of the reliability failure mechanisms
that are monitored using WLR techniques include:
ONGOING IMPROVEMENTS
As we receive feedback from the users of QUIC, we (QASD)
will continue to enhance the "User Friendliness" of the system and add new features which, we hope, will help promote a true sense of teamwork between us and our customers.
Wafer Level Reliability (WLR)
BACKGROUND
Interlayer Dielectric Integrity
The conventional methods of reliability screening, that of
short-term burn-in to eliminate infant mortalities and longterm life tests at high temperature, will soon become impractical for many devices. The reasons for this are tighter
infant mortality ppm requirements, higher costs, and shortened lifetimes.
Unique high voltage testing (to 1500V) is used to test for
dielectric particles, metal hillocks or contamination, and
poor dielectric stop coverage. Designed experiments
4-11
http://www.national.com
Wafer Level Reliability (WLR)
(Continued)
Hot Electron Degradation
Two wafer level tests are performed to indicate device
susceptibility to hot electron damage. First, the maximum
substrate current is measured to indicate the level of impact ionization occurring at the drain edge. Second, gate
current measurements are taken to gauge the magnitude
of electron injection during device operation. Long-term
DC stressing of transistors at peak substrate current conditions is also monitored.
Electromlgratlon
A Standard Wafer Electromigration Accelerated Test
(SWEAT) technique is used to measure the sensitivity of
a metal line to electromigration failures. SWEAT is used
as a relative test of the reliability of a line.
Contact Electromlgration
Risk of failures due to contact spiking and solid phase
epitaxial growth (SPEG) are monitored by forcing current
through specially designed test structures, and monitoring increases in resistance and substrate leakage.
have been successful in correlating the high voltage
WLR test results to fab process monitors (such as deposition temperature and etch selectivity), and to accelerated life test results (Op-life, Temp Cycle, and Thermal
Shock).
Metal Step Coverage
High current testing of large area metal serpentine structures is performed to detect restrictions in the conducting
stripe. Designed experiments have been successful in
correlating the high current WLR test results to fab process monitors such as metal thickness, critical dimensions, and via size.
Mobile Ions
A 200·C hot chuck is used with custom-built high temperature probe cards to accurately measure transistor
threshold voltage shifts for a variety of oxide layers. Other methods for detecting mobile ion contamination include the use of self-heated polysilicon gate test structures and Triangular Voltage Sweep (TVS) test techniques.
Metal Stress Voids
High current resistance measurements are taken before
and after wafers are processed through a series of heating and cooling cycles. This heat treatment is designed
to mimic the high temperature processing incurred during
device assembly (such as a seal-dip furnace), and it has
been shown to accelerate metal void formation when the
stress of the overlying film is high enough. Significant
increases in the final resistance indicate the formation of
metal stress voids.
Gate Oxide Integrity:
JEDEC JRAMP, VRAMP and OBO test techniques are used
to monitor gate oxide quality. The WLR tester is also
used to perform very sensitive leakage current measurements, using a specially designed picoammeter module,
which allows us to detect subtle differences in gate oxide
quality.
Passivation Integrity
A novel wafer-level-autoclave test technique has been
developed which allows us to quantify the level of protection the passivation film provides when the wafer is subjected to a high temperature, high humidity environment.
Electrostatic Discharge
Sensitivity (ESD)
BICMOS LOGIC
National BiCMOS Logic has designed special dual-rail ESD
protection circuitry to increase its level of ESD performance
over non-protected inputs and outputs. This protection is
standard on all BiCMOS Logic designs and was first used in
National's family.
By design, this circuitry limits product vulnerability to both
positive and negative Human Body Model (HBM) ESD and
Electrical Overstress (EOS) voltages by protecting inputs
and outputs connected to Vee as well as ground. Protection
to ground is provided through the transistor 02 and diode
D2, standard Schottky clamp. The path to Vee is protected
through the BVCEO breakdown mechanism of 01. Diode
D1 ensures isolation of the input or output from Vee leakages.
The device design and layout ensures dependable turn-on
characteristics as well as robustness.
ESO protection was achieved with no appreciable affect on
speed or increase in capacitance.
01
01
INTERNAL
CIRCUITRY
INPUT 0 - -....- -
- -....- 0 OUTPUT
02
GND
GND
Figure 21. ESD Protection Circuit
http://www.nationai.com
4-12
TL/F/12134-21
r-
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Electrostatic Discharge
Sensitivity (ESD) (Continued)
I»
C.
CMOS Logic
Circuits which show excellent resistance to ESD-type damage are classified as category "B" of MIL-STD-883C, test
method 3015, and withstand in excess of 4000V typically. It
is guaranteed to have 2000V ESD immunity on all inputs
and outputs. Parts do not require any special handling procedures, however, normal handling precautions should be
observed as in the case of any semiconductor device.
ABT and SCAN ABT logic ESD sensitivity is guaranteed
greater than 2000V, using the MIL-STD-883C, test method
3015 for Human Body Model (HBM) ESD.
Rl
= 10 M!l
1
= 1500!l
R2
~~
HIGH
VOLTAGE
POWER
1
SUP{LY
C1 =
100
pF
Figure 23 shows the ESD test circuit used in the sensitivity
analysis for this specification. Figure 24 is the pulse waveform required to perform the sensitivity test.
J
OUT
High Voltage
R2
~
<
-
;::;:
'<
= 1500!l
I»
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Relay
Ch"~
Regulated
High Voltage
Supply
-
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In
"ce!.
= 800 k!l
1---------0
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3
In
Normal handling precautions should be observed as in the
case of any semiconductor.
(min)
3G!l (max)
CD
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CD
TL/F/12134-22
Figure 22. HBM Test Circuit
R1
S·
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DC
Voltmeter
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= lOOp'
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Terminals
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TLlF/12134-25
FIGURE 23. ESD Test Circuit
100%;----",.........
.,
90%
'"
taECAY :5 350 ns
a.
E
(R2 + R3 ) C1 2: 300 ns
III
~ISE :5 15 ns
"0
36.8%-f--I-----
10%
TIME
TlIF/12134-26
FIGURE 24. ESD Pulse Waveform
4-13
http://www.national.com
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Latchup Testing
Power Sensitivities for Minimum
Geometry Products
Latchup in CMOS and bipolar circuits can vary in severity
from being a temporary condition of excessive Icc current
and functional failure, to total destruction requiring a new
unit. The latchup condition is usually caused by applying a
stimulus that is able to cause a regenerative condition in a
PNP-NPN structure. For a more detailed description of definitions and causes of latchup, see National Semiconductor
Application Note 600 (located in the "FACT Advanced
CMOS Logic Data book" Lit. # 40019).
The demand for high performance process technology capable of sub 4 ns speeds, minimal noise and lower operating voltages drives the microelectronics industry towards
decreasing layout geometries. Advanced process technology minimizes gate widths, gate oxide thickness and junction
depths to improve gate switching speeds. In contrast, the
decreased geometries reduce the ability of the devices built
on advanced processes to resist electrical overstresses. As
geometries decrease, emphasis shifts towards the reduction of environmentally induced electrical overstresses to
ensure system and component reliability.
Market trends continue to drive the need for smaller geometries with reduced power supply voltages. Current 5.0V technologies are migrating towards 3.0V technologies while
3.0V technologies have shown a greater sensitivity to electrical overstresses. Sensitivities to electrical overstresses
have been observed in as large as 1.0 J-Lm geometries.
Device damage from electrical overstresses vary and the
categories include, but are not limited to: Electrical-OverStress (EOS) due to excessive current or voltage exposure
and Electro-Static-Discharge (ESD) be it exposure by Human Body Model, Charged Device Model or Machine Model. Sources of electrically induced overstresses are difficult
to determine; however, investigation of failures from small
geometry devices may show that environmental hazards
such as unregulated and unconditioned power supplies in
the field exceed "Absolute Maximum Ratings" causing unrecoverable device damage.
BICMOS Logic
National has characterized its Advanced BiCMOS logic for
robustness using the JEDEC 17 method and an IMCS 4600
Automated Latchup Test System. The automated test
eqUipment approach to latchup provides a repeatable test
setup and application of test conditions, reduces the
amount of time for evaluation, and provides a more comprehensive set of vectors and stimuli over a shorter period of
time.
The JEDEC 17 method is a standard measurement procedure for the characterization of CMOS integrated circuit
latchup susceptability/immunity, measured under static
conditions. The method allows for overcurrentl overvoltage
stressing of inputs and outputs to detect latchup.
In short, the JEDEC 17 method follows a sequence of:
1.
2.
3.
4.
5.
6.
Advanced processes such as BiCMOS include small dimension current density limited geometries that are sensitive to
electrically induced overstresses. The combination of internal bipolar and CMOS gates provides current capabilities for
maximum device performance. In an unconditioned supply
environment, the bipolar section of a BiCMOS circuit can
source excessive current through the CMOS section and
cause damage due to the CMOS circuit's current density
limited geometries.
In an effort to resolve device sensitivities to electrical overstresses, designers and engineers can reference device databooks. Databook specifications include "Absolute Maximum Ratings" and adherence to this specification is essential in ensuring component and system level reliability.
The time for each parameter as well as the temperature is
critical for correlation of latchup. National characterizes
latchup on the Advanced BiCMOS family at 125°C and with
the critical timing parameters on Table III. Close correlation
can only be accomplished by using the same trigger duration, Vee, test temperature, and magnitude of trigger stimulus.
TABLE III. Critical Timing Parameters
Symbol
1. A. Amerasekera, A. Chatterjee, ':4n Investigation of BiCMOS ESD Protec·
tion Circuit Elements and Applications in Submicron Technologies",
EOS/ESD Symposium, p5B.6.1.
http://www.national.com
Apply power
Setup I/O conditions to place device in desired state
Apply trigger source for desired duration
Measure supply current
Remove power supply if lec ~ test limit
Inspect for electrical damage
4-14
Parameter
Time
Tw
Trigger Duration
500 J-Ls
teool
Cool Down Time
10 ms
Latchup Testing
(Continued)
TABLE IV. Supply and Stimulus Values
For BiCMOS ABT products, logic states are checked for a
susceptability to latchup witil all outputs high, all outputs low
and all outputs in TRI-STATE. If the device is a bidirectional
device, then the logic states are tested in each direction. All
inputs and outputs are tested for each logic state and direction.
TRIGGER
SOURCE (v /1)
Parameter
PVT
Positive Voltage
Trigger
NIT
Negative Current
Trigger
Vee
7.0V
Stimulus
en
"'C
Vee
+ 3V (10V)
(1)
(")
~
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7.0V
-500 mA
Verification of any unusual observations is performed with a
curve tracer manually. For example, when ABT outputs are
brought below ground, the NMOS transistor feeding current
to the bipolar output will turn on and current from Vee will
come out of the output pull-down device. This condition is
unavoidable by design and is not latchup. Thus good analysis of observations will tell one whether latchup has occurred.
Due to the high trigger stresses, devices used for latchup
testing should be discarded and not used for design, production, or other tests. Latchup testing is potentially destructive and may limit the life of a device.
Finally all inputs and outputs have clamp diodes, requiring a
negative current trigger as a stimulus for latchup. The clamp
diodes are designed to allow current flow into ground without injecting carriers into the substrate that could cause a
parasitic PNP-NPN. Supply and stimulus values used by National for latchup testing the ABT family are in Table IV.
'?
Stimulus
o·
::J
Forcing a current in the positive direction overstresses the
inputs and outputs by causing a breakdown. Such breakdowns consume enough power in the breakdown area to
cause the junction permanent damage. PVT stresses the
inputs and output while keeping the input and output devices out of any breakdown region.
ov
S·
CC
Because the ABT and SCAN ABT family is designed for live
insertion, a Positive Voltage Trigger (PVT) and a Negative
Current Trigger (NIT) is applied to the inputs and outputs to
check for latchup.
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TLIF/12134-23
FIGURE 25.
•
4-15
http://www.nationai.com
Latchup Testing
(Continued)
CMOS Logic
The test procedure is as follows; five pulses, each of at
least 2000V, are applied to every combination of pins with a
five second cool-down period between each pulse. The polarity is then reversed and the same procedure, pulse and
pin combination used for an additional five discharges. Continue until all pins have been tested. If none of the devices
from the sample population fails the DC and AC test characteristics, the device shall be classified as category B of MILSTD-883C, TM-3015. Devices that result in ESD immunity in
the 2000V-3999V range are listed as ESD Class 2. Devices
that result in ESD immunity in the 4000 + V range are listed
as ESD Class 3.
In the past a major problem with CMOS has been its sensitivity to latch-up, usually attributed to high parasitic gains
and high input impedance. SCAN CMOS logic is guaranteed
not to latch-up with dynamic currents of 300 rnA forced into
or out of the inputs or the outputs under worst case conditions (TA = 125°C and Voo = 5.5 Voc). At room temperature the parts can typically withstand dynamic currents of
close to 1A. For most designs, latch-up will not be a problem, but the designer should be aware of its causes and
how to prevent it.
SCAN CMOS devices have been specifically designed to
reduce the possibility of latch-up occurring; National Semiconductor accomplished this by lowering the gain of the parasitic transistors, reducing substrate and p-well resistivity to
increase external drive current required to cause a parasitic
to turn ON, and careful design and layout to minimize the
substrate-injected current coupling to other circuit areas.
P-Channel MOS
For further specifications of TM-3015, refer to the relevant
standard. The voltage is increased and the testing procedure is again performed; this entire process is repeated until
all pins fail. This is done to thoroughly evaluate all pins.
Input
N-Channel MOS
N + Substrate
0.008-0.25 ohm-em
TLIF/12134-24
FIGURE 26. Advanced CMOS EPI Process Cross Section with Latch-up Circuit Model
http://www.national.com
4-16
Section 5
Characterization Data
http://www.national.com
Section 5 Contents
Propagation Delay vs. Temperature, Capacitive Loading and Switching Output.............
SCAN 18245T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCAN18373T. ... ......... ..................................................... ....
SCAN18374T............. .........................................................
SCAN18540T......................................................................
SCAN18541T......................................................................
Typical Icc vs. Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . .
5-2
5-3
5-3
5-5
5-8
5-10
5-12
5-14
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n
...
N'
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Propagation Delay vs Temperature
Capacitive Loading and Switching Outputs
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SCAN18245T
tpHL (A to BIB to A) vs Temperature
CL = 50 pF, 1 Output Switching
tpHL (A to BIB to A) vs
# Outputs Switching
CL = 50 pF, TA = +25'C
tpHL (A to BIB to A) vs Temperature
CL = 50 pF, 18 Outputs Switching
12
-.- ~ITIIlt~X.I
10
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-55
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25 45 65 85 105 125
-~5-15
Temperature (C)
5
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25 45 65 85 105125
18
1
Temperature (C)
tpHL (A to BIB to A) vs Load Capacitance
1 Output Switching, TA = + 25'C
Number Outputs Switching
tpLH (A to BIB to A) vs Temperature
CL = 50 pF, 18 Outputs Switching
tpLH (A to BIB to A) vs Temperature
CL = 50 pF, 1 Output Switching
14r---------,---~~__,
12
12~--------+---,~,~~'-'~
10
t.lAX ,
"
. ---- - - - - _+A~
T~P J4.L
O~--------.L-----------'
50
250
150
O~~~~~~~~~~
-55
-~5-15
5
25 45 65 85 105125
Temperature (C)
Capacitance (pr)
tpLH (A to BIB to A) vs # Outputs Switching
CL = 50 pF, TA = +25'C
12
,.
~~x
__ f-f-'
1
... f-
sf
,.....
-55-35-15 5
2545 65
851~5125
tPZH (~ to An/Sn) vs Temperature
CL = 50 pF, 1 Output Switching
....
MAX .". ... -
.. .. .... ....
10r-------. .~..~~..- ..------;
~ii"H:
... f-
i- f--
Temperature (C)
tpLH (A to BIB to A) vs Load Capacitance
1 Output Switching, T A = + 25'C
12
10
o
--
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- - - - - - - -~t.lt
f---"
f--
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----
------~I~
OL-________L -______
18
50
150
Capacitance (prJ
~
250
-55-35-15 5
25 45 65 85105125
Temperature (e)
TL/F/11576-1
5-3
http://www.national.com
ca
as
C
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SCAN 18245T (Continued)
o
*'
tpZH (0£ to An/Sn) vs Temperature
CL = 50 pF, 18 Outputs Switching
;::
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tpZH (OE to An/Sn) vs Outputs Switching
CL = SOpF, TA = +2So C
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tPZL (OE to An/Sn) vs Temperature
CL = 50 pF, 1 Output Switching
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Temperature (c)
-55 -35-15 5 25 45 65 85 105125
Temperatur. (c)
Number Outputs Switching
*'
tpZL (0£ to An/Sn) vs Temperature
CL = 50 pF, 18 Outputs Switching
(oe
tPZL (OE to An/Sn) vs Outputs Switching
CL = 50 pF, TA = +2So C
12f-+--+--t-~-+-+~--~
12
10 f-+-+-+--+---1-
10
10
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CL = 50 pF, 1 Output Switching
TYP @ 4.5V
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Temperature (C)
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CL = 50 pF, TA = +2So C
12
10
.. - ..
- - - - - - _. _. -.
Number Outputs Switching
tpLZ (OE to An/Sn) vs Temperature
CL = 50 pF, 18 Outputs Switching
5. iV
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tpLZ (OE to An/Sn) vs Temperature
CL = 50 pF, 1 Output Switching
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Temperature (C)
tpHZ (OE to An/Sn) vs Outputs Switching
CL = 50 pF, TA = +2SoC
-- "'-I-- - - -t:x
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T~P J 4.~V
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--.
-55 -35-15 5 25 45 65 85 105125
Number Outputs Switching
tpHZ (0£ to An/Sn) vs Temperature
CL = 50 pF, 18 Outputs Switching
10
o
18
1
..... _- ...
o
-55-35-15 5 25 45 65 85105125
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T.mperature (c)
18
Number Outputs Switching
TL/F/11576-2
http://www.nationai.com
5-4
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tpHL (In to On) VI Temperature
CL = 50 pF, 18 Outputl Switching
tpHL (In to On) va Temperature
CL = 50 pF, 1 Output Switching
12
12
--r-- - - -;t:14
10
i--
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10
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r--
TYP @ 5.5V
---------
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I
T~P J 4~
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-55-35-15 5 25 45 65 85105125
16~--------'-----~~~A~X
12~-------.~.~~·-·-·-----1
10
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12
10
8
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Number Outputs Switching
tpHL (LE to On) va Temperature
CL = 50 pF, 18 Outputa Switching
14
-- - --"I'"r
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12
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TYP @ 4.5V
T~pJ~
10
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CL = 50 pF, 1 Output Switching
tpHL (In to On) va Load Capacitance
1 Output Switching, T A = + 25'C
'II
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- - - - - - - -tl~
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MIN
T
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50
150
250
o
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-55-35-15 5 25 45 65 85105125
-55 -35-15 5 25 45 65 85 105125
Tamperatura
Capacitance (pF)
tpHL (LE to On) va # Outputa Switching
CL = 50pF, TA = +25'C
14
tpHL (LE to On) VI Load Capacitance
1 Output Switching, TA = + 25'C
TYP @ 4J.':'."
12
TYP @ 5rl
8_
.....,.........~YP @ 5.5V
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1 Output Switching, T A = + 25'C
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12r---------r-~~~..~--..~
..... ----_
10
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@
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8
---
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Number Outputs Switching
TYP
2 I-r-_ _
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tpLH (In to On) VI # Outputa Switching
CL = 50 pF, TA = +25'C
12
i~
~
f- :.- r- I-:.- r- I--
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Capacitance (pF)
tpLH (In to On) va Temperature
CL = 50 pF, 18 Outputa Switching
10
- -
--
t.lIN
150
50
Number Outputs Switching
12
-----
0L-________L -______
-.
:.- I--
I--
II
11
1
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TY~
......
10
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12
10
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tpLH (In to On) va Temperature
CL = 50 pF, 1 Output Switching
14r-________~~~·~..- ..~~~A~X
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10
Tomperotura
16~--------.-------.~.~
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12
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50
150
250
Capacitance (prj
TL/F/11576-3
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10
TYP
I
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12
dv
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Temperature
tpHL (In to On) va # Outputl Switching
CL = 50 pF, TA = +25'C
http://www.national.com
D)
Sta
SCAN 18373T (Continued)
C
C
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CL = 50 pF, 1 Output Switching
~
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tpLH (LE to On) VI Temperature
CL = 50 pF, 18 Outputl Switching
10
o
12
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-55 -35-15 5 25 45 65 85 105125
-55 -35-15 5 25 45 65 85 105125
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Temperature
Temperatur.
~I~
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o
1
18
(cl
Number Outputs Switching
tPZH (Of to On) VI Temperature
CL = SO pF, 1 Output Switching
tpLH (LE to On) va Load Capacitance
1 Output Switching, TA = + 25"C
l.l.
to
tpZH (Of to On) VI Temperature
CL = SO pF, 18 Outputl Switching
14r---------~------~
12~------~~C-~-------~;~;~X
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10~-f-+-~~-+-4~--~
10 F---------f--
OL---______
50
~
_______ _ J
150
250
OL-~~~-L~~~~~
O~~~~~~~~~~
-55-35-15525456585105125
-55 -35-15 5 25 45 65 85 105125
Capacitance (pF)
Temperature
tpZH (~to On) VB # Outputl Switching
CL = SO pF, TA = +25"C
12
1.!~X.
10
JJll !..I
14
12
11
n
18
1
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-55 -35 -15 5 25 45 65 85 105 125
Temperature
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tpHZ (OE to On) VI Temperature
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10
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-55 -35-15 5 25 45 65 85 105125
Tlmperature
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18
Number Outputs Switching
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-55 -35-15 5 25 45 65 85 105125
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--- -
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TYP @ 4.5V
TYP @ 5.5V
I - -~5.~V
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10
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12
12
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tpHZ (~ to On) VI Temperature
CL = 50 pF, 1 Output Switching
tpZL (~to On) va # Outputl Switching
CL = SOpF, TA = +25"C
' .. _- I-- --~-
I-
I
1
Number Outputs Switching
14
12
~v
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tPZL (O'E to On) VI Temperature
CL = SO pF, 18 Outputl Switching
14
l-
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Temperature
tpZL (Of to On) VI Temperature
CL = 50 pF, 1 Output Switching
10
Trrul~
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o
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Temperature
(cl
TL/F/11576-4
http://www.national.com
5-6
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#define WRITE_PSC (PSC_REG_OFFSET. DATA)
outportb ((int) (PSC_BASE + PSC_REG_OFFSET). DATA)
#define READ_PSC(PSC_REG_OFFSET) inportb((int) (PSC_BASE +
PSC_REG_OFFSET) )
#endif
==
/* If compiling for Corelis board. use Corelis low level
driver for PSC100 */
#if BSM_TYPE
CORELIS_BOARD
#include ·cortest.h·
#define PSC_BASE Ox140
#define WRITE_PSC (PSC_REG_OFFSET. DATA) write_psc(O.
PSC_REG_OFFSET. DATA)
#define READ_PSC (PSC_REG_OFFSET) read_psc(O.
PSC_REG_OFFSET)
#endif
==
These two cases are handled using a conditionally defined
macro. This is the only conditional define in the code, and
the only thing that may change when compiling for one architecture verses another.
Note that the above code also includes an option to define
WRITLPSC and READ_PSC to call functions for a Corelis
ISA card, PC-1149.1/100F, High Speed PC-AT Bus Boundary-Scan controller. This option was extremely helpful in
that it enabled the code development and debug to be performed on a PC, with a SCANPSC100F mounted on an ISA
card, using a high level debugger. Once the code was debugged, it could be compiled for the target embedded system resulting in a great reduction in debug time of the embedded environment.
such as the Embedded Boundary-Scan Controller,
SCANPSC100F, and the Hierarchical and Multidrop Addressable JTAG Port, SCANPSC110F Bridge, that enable
system wide embedded scan testing. With the SCAN EASE
software described in this paper, the task of implementing
embedded scan test has become virtually an "off the shell"
solution.
REFERENCES
[1] IEEE Std. 1149.1-1990, "1£££ Siandard Test Access
Port and Boundary-Scan Architecture': IEEE Computer
Society, 1990.
[2] NSC "SCAN Databook': National Semiconductor,
1996.
National
[3] NSC, "Scan Tutorial Handbook Volume
Semiconductor, 1994.
[4] IEEE Std. 1149.1-1990 Sup. B, "Boundary-Scan Description Language': IEEE Computer Society, 1990.
[5] EichelbergereLindbloomeWaicukauskieWiliiams,
"Structured LogiC Testing': Prentice Hall, 1991.
[6] Motorola, "M68000 Microprocessor User's Manual':
Motorola 1990.
1':
SUMMARY
A OFT strategy that utilizes boundary-scan components
whenever available, will reduce test development cycletime, increase fault coverage, reduce test time, and enable
system level embedded test. Production tests can be
reused for embedded (built-in) test and tools are available
that automate this process. National provides components
http://www.national.com
7-12
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Embedded IEEE 1149.1
Test Application Example
National Semiconductor
Application Note 1037
This application example discusses the implementation of
embedded, system level boundary scan test within an actual
design, the National boundary scan demonstration system.
Its intent is to describe the decisions, actions and results
when applying boundary scan and National's SCAN EASE
Software within a system. For more information see also
AN-1022, "Boundary Scan Silicon and Software Enable
System Level Embedded Test."
Functionally, the system is designed to display messages
and system status information using the LCD display located on each liD card. This message and status information
is driven from the processor card, via the system backplane,
or from EPROMs local to each liD card. To demonstrate
the features and functions of boundary scan, the system
also contains LEOs which display the status of boundary
scan activity.
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HARDWARE DESCRIPTION
TEST OBJECTIVES
The National boundary scan demonstration system is comprised of a multidrop backplane which interconnects a processor card to several system I/O cards. The backplane contains a 16-bit data bus, a 16-bit address bus and several
control signals routed to six connectors. The processor card
consists of a processor core which includes a Motorola
68302 ILP, boot EPROM and working SRAM, a RS232 port
for remote communication, a parallel backplane interface
and an auxiliary parallel port. The I/O cards, each sharing
an identical architecture, include a 16-bit LCD display, an on
board EPROM which stores LCD messages, and a backplane interface. Each liD card also contains logic which
multiplexes data, from either the backplane or EPROM, to
the display.
The fundamental test objective for the National demonstration system was to utilize techniques which could be applied
over the life of the product, including development, manufacturing and in-field operation. With effective prototyping to
ensure functionality and timing performance, printed circuit
board (PCB) structural faults, resulting from manufacturing
errors or in-system board stress (e.g., temperature changes
or mechanical stresses), were the primary focus. Boundary
scan was seen as an effective means of detecting and diagnosing printed circuit board failures at all stages of the product's life cycle.
A specific area of concern during the development of the
test strategy was system level test. Typically, limited tester
access forces system test to rely on functional patterns to
test for even simple interconnect failures. This leads to very
complex test patterns, poor fault coverage and very difficult
failure diagnostics. More importantly, the functional test routines depend on sound interconnects between components
to be effective. Embedded, system-level boundary scan was
perceived as a way to replace many of the functional tests
with simple and easily diagnosable tests.
The number of liD cards can vary within a given system.
While five backplane liD card connectors are available,
only 2 of the 5 slots are typically populated with liD cards.
The multidrop (Le. parallel) backplane architecture enables
cards to populate any of the five connectors and allows
connectors to remain empty. Board addressing is used to
select cards for functional operation.
Con 4
Con 5
Con 6
System Backplane
Processor Card
TLIF/12146-1
FIGURE 1. Demonstration System Layout
7-13
http://www.national.com
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TL/F/12146-2
FIGURE 2. Demonstration Processor Card
Boundary scan was viewed as only a part of the complete
test solution. Functional test routines were still required to
test system memory and confirm effective IlP-to-system peripheral communication. Using the two techniques together
maximized test effectiveness while reducing test development efforts.
To increase the structural fault coverage on nets connected
to devices which are not available with boundary scan, a
"cluster test" can be implemented. A cluster test relies on
at least two boundary scan components and a functional
knowledge of the cluster (Le., cluster of devices) connected
between them. Using one 1149.1 compliant component to
drive test vectors to the cluster and the other to receive
expected data from the cluster, the structural integrity of the
cluster can be evaluated.
IEEE 1149.1 COMPLIANT SYSTEM ARCHITECTURE
To accomplish the boundary scan test objectives, the
1149.1 test strategy covered three aspects of the system:
board and backplane boundary scan test points, system level boundary scan access and embedded boundary scan
control.
As the number and complexity of components increases,
the development of test vectors becomes more difficult and
diagnostic resolution increases. Within the demo system, a
cluster test was implemented on the processor card's auxiliary port (see Figure 2).
Board and Backplane Test Points
The first step in implementing boundary scan is to integrate
1149.1 compliant components into the functional design.
Maximizing the percentage of nets covered by boundary
scan reduces the cost of other techniques and equipment
like in-circuit testers, while increasing the ability to apply the
benefits of boundary scan at later phases of the product's
life cycle. In the case of the National demo system, boundary scan was included on nearly every logic IC which populated the processor card and I/O cards.
On future demo design revisions, boundary scan will be expanded beyond the logic components to include an 1149.1
compliant microprocessor and programmable device (Le.,
integrating the separate, non-1149.1 programmable devices
into a single 1149.1 FPGA or CPLO). These additions will
continue to drive the structural fault coverage towards
100% and also provide non-test capabilities, such as IlP
emulation and in-system FPGA programming via the JTAG
port.
To support backplane interconnect testing, National's 18·bit
SCAN ABT Test Access Logic components were implemented at the backplane interface on both the processor
card and I/O cards. Using 1149.1 compliant SCAN ABT logic (SCAN182245A) provided the required backplane test
points while also creating a hot insertable1 backplane interface. The hot insertable interface allowed failing processor
or I/O cards to be removed or inserted without powering
down the system.
http://www.national.com
System Level Boundary Scan Access and Partitioning
With the 1149.1 components placed on the processor and
I/O cards, the next objective is to interconnect the 1149.1
component TAP signals-TMS, TCK, TOI, TOO and
TRST-at both the board and system levels. For the National demo design, this task was accomplished by adding a 5bit bus to the backplane design and placing a National Hierarchical and
Multidrop Addressable JTAG Port,
7-14
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LSP2
SCANPSC 11 OF
BRIDGE
Edge Connector
BP TAP
TL/F/12146-3
FIGURE 3. Demonstration 1/0 Card
SCANPSC110F bridge, component at the backplane interface of the processor card and each lID card. The
SCANPSC110F bridge provides two key features to efficiently interconnect and partition a 1149.1 compliant system:
The ability to partition a board and system using the
SCANPSC110F bridge simplifies test development, improves test efficiency and allows failures to be diagnosed to
the partition level without using an off-line diagnostics tool.
However, these benefits are only realized if the 1149.1 components are intelligently grouped and connected. The objective for testing the demo system was to test each board as a
separate entity and to test the interconnects between the
boards (I.e., the backplane). Enabling each board to be tested separately was easily accomplished when the
SCANPSC110F bridge was placed at each card's backplane interface and connected to a system wide backplane
TAP. With this interface, the tester TAP signals could be
applied to each board separately.
• System Level Partitioning: The SCANPSC11 OF bridge
provides an addressable, multidrop interface to a single
backplane TAP bus. This multidrop TAP interface is a
perfect fit for this application because it preserves the
ability for cards to be placed in any of the backplane
connectors and for connectors to be left empty without
requiring an entirely new set of boundary scan test vectors. Using a 1149.1 protocol, each SCANPSC110F
bridge and, in turn, each board, can be addressed to
participate in boundary scan test operations.
• Board Level Partitioning: Typically, board level boundary scan components are connected to form a single
chain. The SCANPSC110F bridge provides three local
scan ports (LSPs) which allows board level components
to be partitioned into smaller, more manageable chains.
Using the SCANPSC110F bridge's internal data registers, the LSPs can be configured to individually connect a
single scan chain to the backplane TAP or to simultaneously connect up to three scan chains in series with
the backplane TAP.
With exclusive access to each board, the next critical task
was to select which board components were grouped and
connected to the SCANPSC11 OF bridge LSPs. Again, the
test objectives were considered. To enable the development of an efficient, backplane specific boundary scan test,
the 1149.1 compliant backplane interface components on
each card were exclusively assigned to a single LSP. To
group and assign the remaining 1149.1 compliant, boardlevel components to the other two SCANPSC11 OF bridge
LSPs, each board type was viewed separately.
7-15
http://www.national.com
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CON 6
CON 2 CON 3
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FIGURE 4. Backplane-Hierarchical Connection
For the processor cards, the remaining compliant components were grouped an an internal logic chain and an auxiliary port logic chain. As with the backplane partition, these
groups were selected to enable the development of group
specific tests. The auxiliary port is intended to support a
connection to a 1149.1 compliant sub-system. Assigning the
port's compliant components to a unique LSP allows tests
to be generated specifically for this port (and what is connected to it). The internal logic covers all other board level
1149.1 compliant components.
A similar component group was implemented for each I/O
card. The internal card logic was grouped and assigned to
one LSP while the other LSP was connected directly back to
the backplane connector in order to provide a hierarchical
connection. A hierarchical bridge connection is realized by
connecting one SCANPSC110F bridge's LSP to a second
SCANPSC110F bridge's backplane interface TAP. Hierarchical connections enable board scan chains to be split into
more than the three chains supported by a single bridge.
Hierarchical connections also enable a system to be partitioned into addressable sub-systems. In the case of the
demonstration design, the hierarchical configuration was implemented to show the concept and addressing scheme required to address a bridge and its LSPs hierarchically. Since
each I/O card shares an identical architecture, each I/O
card's LSP3 connects directly to the backplane edge connector. The hierarchical connection is then realized using
backplane routing between Con 5 and Con 6 (see Figure 4 ).
http://www.national.com
Embedded Boundary Scan Test Control
The final step of a boundary scan hardware design is to
provide the means to apply and evaluate the boundary scan
test vectors. For boards and systems which are tested using
an external tester, the hardware implementation simply involves adding an applicable tester interface; e.g., additional
pins on the edge connector, a special purpose connector/
header or vias for ICT probes. For boards and systems
which don't permit physical access, and/or require self-test
or remote test capability, the test control must be embedded within the system.
For designs which require embedded test control, the optimal hardware implementation is one which enables both
embedded and external tester access. This allows the design to benefit from the strengths of each method. The external tester offers the best means of developing tests for
hardware debug and manufacturing. Using the ATPG and
diagnostic tools provided with the external tester, tests can
be easily developed and modified. Once the tests have
been applied, failures can be diagnosed to the net or pin
level automatically. With the tests finalized, and the boards/
system tested, the tests and control are embedded to provide self-test and remote test access capability.
The National demo system hardware was designed to support both embedded and external test application. With the
ability to address each demo card separately using the
SCANPSC11 OF bridge, embedded and external access was
only required on the processor card. The processor card
then acted as the master to test each card and the backplane.
7-16
• Embedded Test: The embedded test capability for the
demo system was implemented using the processor
card's J-lP and the National SCANPSC100F Embedded
Boundary Scan Controller. The SCANPSC100F provides
an efficient, asynchronous interface between the J-lP'S
parallel data bus and the serial 1149.1 TAP, and is fully
supported by the SCAN EASE software tools. The generic, asynchronous interface allows SCANPSC100F to interface with a wide range of processors and operate independent of the processor's operating frequency. The
microprocessor views the SCANPSC1 OOF as a standard
I/O device.
The processor card provided two options to initiate and
evaluate embedded tests. For a power-on or post-reset
self test, an LED display block was included with a separate LED for each card in the system. To initiate/evaluate
tests remotely, the UART on the microprocessor was
configured to provide an RS232 interface and an RS232
connector was added to the processor card. This remote
interface also allows new tests to be downloaded and
results to be uploaded.
• BSDL Selection File: Boundary Scan Description Language files, which are provided by the component vendor
or ASIC designer, define the specific implementation of
1149.1 features with an IC (see National SCAN Databook
Section 6 Boundary Scan Design Support). With VIP, the
user must create a BSDL selection file which provides
the directory path to the BSDL file for each 1149.1 component included in a given test.
• PCB Net List (in BNET Format): A net list is automatically created by the PCB design and layout tool used to
develop the PCB. The user must convert this net list format to a specific format which is read by VIP. This VIP
format, called BNET, contains only the boundary scan
nets. It also defines the connection of 1149.1 components in each boundary scan chain and associates a
tester TAP with each chain.
• Connection File: This file defines the connection between each tester TAP (provided in the BNET file) and
the SCANPSC11 OF bridges LSPs. It also defines how the
SCANPSC110F bridges are connected to the backplane
TAP and to each other (e.g., multidrop or hierarchical).
• External Test: To provide system level access to an external tester, a connector was added to the processor
card. In addition to the required tester signals, this connector included a sense line tied to the output enable pin
on the SCANPSC100F. When the external tester was
connected, the sense line was pulled high disabling the
TAP pins on the SCANPSC100F. This, in turn, disabled
the embedded tester and allowed the external tester,
alone, to control the system TAP.
• Pin Constraint File: This file defines I/O pins in the net
list which are pulled to fixed logic levels, I/O pins which
must remain in the high-impedance state during a test to
avoid bus contention, or system inputs which must maintain a specific logic level during a boundary scan test
(e.g., a reset input pin).
SCAN EASE Software Tools
All three of the tools within SCAN EASE were utilized to
develop and test the demonstration system:
Figure 2 shows the high level connection between the J-lP,
SCANPSC1 OOF and external connector.
• EmbedPrep: This tool was used to translate test vectors
from the JTAG Technologies pattern format (PAT) to Embedded Vector Format (EVF). EVF is a compacted,
A TPG-independent format that is used by the other
SCAN EASE tools. EmbedPrep has no dependence on
system hardware and is discussed further in the Embedding the Test Vectors section.
IEEE 1149.1 TEST EQUIPMENT
Hardware
A wide range of 1149.1 compliant testers are commercially
available, ranging from in-circuit testers to PC-AT cards. For
the demo system, the requirements for the tester hardware
were low cost and portability. Based on these factors, two
testers were selected: the JTAG Technologies PM3705 and
the Corelis 1149.1 /100F PC-AT card.
• EmbedCom: The EmbedCom tool is a Windows-based
GUI which provides a user-friendly interface to the embedded test system. With this GUI, system self-test is
initiated, new tests are downloaded to system RAM, pass
fail information is displayed and datalogs can be uploaded. The GUI allows a user to test the system with no
knowledge of 1149.1 or the embedded test code.
The PM3705 is a portable controller box which connects to
a PC's parallel I/O port. It provides two 1149.1 TAPs and
connects to the demo system via a 10-pin connector. Connectors are placed on each board (per PSC110F bridge
LSP) to support board level test and on the processor card
to support processor card and system level test. The
PM3705 was used primarily for low volume board and system level manufacturing test, and for externally driven infield test using a laptop computer.
• EmbedTest: This tool, provided as ANSI C source code,
contains functions which communicate with the system
hardware and manage the application/evaluation of test
data. Three aspects of the code must be considered
when integrating EmbedTest into a specific design: integrating the EmbedTest functions with the application's
operating system and system application code; mapping
the SCANPSC1 OOF addresses within the system; and implementing the drivers to support the J-lP specific UART
(if serial communication with the EmbedTest code is required).
The Corelis 1149.1/100F PC-AT card is based on National's SCANPSC100F which provides the ideal development
platform for developing and debugging SCAN EASE functions. The SCAN EASE source code can be conditionally
compiled to run directly on a 1149.1/1 OOF PC-AT card. With
a connection to the demo processor card's TAP connector,
SCAN EASE was developed and debugged using a commerically available ANSI C debugger.
EmbedTest was written as multi-level modules. These levels range from the SCANPSC1 OOF device drivers to a module called PG_CTRL which oversees the execution of tests
and initialization of the test hardware. Integration with the
system's operating system and application code is performed at the program control level. For the demo system,
no operating system was implemented. A simple boot up
routine was implemented to initialize the processor card
ATPG (Automatic Test Pattern Generation) Software
Tool
Both the PM3705 and 1149.1/100F PC-AT card are supported by the JTAG Technologies ATPG tool, called VIP
(Vector Interface Package). This tool automatically generates system level 1149.1 structural tests using four userprovided input files:
7-17
http://www.national.com
»
z
.
.......
o
w
.......
DESIGN S4A2_ABT
hardware and run EmbedTest. A self-test was run immediately after power up (or after a manual system reset button
was pressed), then the system polled the RS232 port for
further instruction.
CHAIN
EmbedTest includes three device driver options for mapping
the SCANPSC100F. Two of the three drivers, the PSC100F
in a memory mapped architecture and the PSC100 in an liD
mapped architecture, were included to ensure that the
SCANPSC100F could be implemented with any commercially available microprocessor. For the demo, a Motorola
68K fLP was used and, therefore, the memory mapped driver was selected. EmbedTest uses a conditionally defined
macro to allow the user to easily specify the driver option.
TCK
TAPl
TCKLl
TDI
TOILl
TDO
TMS
TOOLl
TMSLl
TRST
IC_LIST
SCAN182245A
U27
SCAN182541A
U31
The third SCANPSC100F driver option was written to supapplication
of
EmbedTest using the
port the
SCANPSC100F-based Corelis 1149.1/100F PC-AT card.
The demo system was used extensively in the development
of the SCAN EASE tools. The Corelis 1149.1/100F PC-AT
card enabled the majority of code development to occur on
a PC using an ANSI-C debugger. Debugging modifications,
prior to embedding the code within the system, minimized
the time required to program a new EPROM each time a
change to the code was made.
U29
END_IC_LIST
SCAN182373A
END_CHAIN
TAP2
CHAIN
The final aspect of EmbedTest is the serial communication
code. EmbedTest includes two modules which support serial communication. The highest level module interprets the
commands entered using the EmbedCom GUI or generic
emulator, and calls the appropriate EmbedTest application
functions. The other, lower level, module is a UART specific
device driver. For the demo, this device driver was specific
to the Motorola 68K RS232 UART. The device driver configures and controls the UART hardware.
TCK
TDI
TCKL2
TDO
TDOL2
TMS
TMSL2
TDIL2
TRST
IC_LIST
UIO
SCAN18541T
U16
SCAN18374T
U23
SCAN18374T
U22
END_IC_LIST
TEST DEVELOPMENT
SCAN18374T
END_CHAIN
Developing Test Vectors
IPARRALLEL_CONNECTOR_LIST
In a previous section, the concept and benefit of systeml
board test partitioning was discussed. With the partitions
defined in hardware, the next step is to develop tests corresponding to each partition. For the National demo application, separate tests were developed using the JTAG ATPG
tool for each card and for the backplane. When applying
embedded tests using SCAN EASE, each test is applied
and evaluated separately. This enables SCAN EASE to provide passlfail results for each test. For the demo, this level
of resolution was enough to allow boards to be replaced
and then fully diagnosed later using an external tester.
lEND_PARRALLEL_CONNECTOR_LIST
NETLIST
!NETname
ADDISO
ADDISl
• 1/0 Card: Since all liD cards share identical boundary
scan configurations, generating tests to cover every liD
card required only one BNET file, one BSDL selection file
and one constraint file. A unique Connection File was
then created for each I/O card to provide the
SCANPSC110F bridge address and LSP configuration.
Samples of these files are shown in Figures 5 through 8.
Internal Lagle: The internal logic boundary scan test
verifies the structural integrity of boundary scan nets
within each liD card. Some nets are shared between
the internal logic chain (LSP2) and the backplane interface logic chain (LSP1). To access these shared
nets, SCANPSC11 OF bridge is configured in the connection file to serially connect LSP1 and LSP2. The
ATPG then views the LSP1 and LSP2 chains as a
single chain and generates tests accordingly.
ADDIS2
ADDIS3
ADDIS4
ADDIS5
ICname
PINnumber;
U16
42
U23
2
U23
Ul6
15 ;
41
U23
U23
16 ;
U16
39
4
U23
5
U23
18 ;
U16
38
U23
U23
7
19 ;
U16
36
U23
8
U23
U16
21 ;
U23
35
10
U23
22;
FIGURE 5. Sample BNET File
http://www.national.com
7-18
>
Z
SYNTAX_VERSION 1.2
DESIGN 10_INT_2
REVISION UNKNOWN
SYNTAX_VERSION 1.2
DESIGN hierarc
REVISION UNKNOWN
TESTER_CHANNEL TAPl
TESTER_CHANNEL TAP 1
Board address is
decimal 2 (00000010)
The address is the only
item that changes
when creating internal
net test for each I/O card
TAPl and TAP2 chains
defined in BNET
FROM TESTR (PART, ADDRESS, NAME OF LSPs
1-3) CASCADEl (PSCIIOF, 2, TAP1, TAP2,
NONE)
END_CHANNEL
!FROM TESTR (PART, ADDRESS, NAME OF TAPS
1-3 FOR THIS BRIDGE)
CASCADEl (PSCIIOF, 3, NONE, NONE,
CASCADE2)
CASCADE2 (PSCIIOF, 4, TAP1, TAP2, NONE)
END_CHANNEL
.....
I
o
w
........
FIGURE 9. Hierarchical Board Connection File
• Processor Card: The processor card includes boundary
scan nets, but also serves as the test master for the
remainder of the system. This dual role dictates that separate internal processor card tests must be created for
applications with an external tester versus application
with the embedded tester. When applying embedded
tests, the 1149.1 components which access and evaluate the processor's local bus cannot be included in the
boundary scan test. Controlling the local bus with boundary scan would prevent the processor from communicating with board resources required to apply the tests.
When applying tests with an external tester, the processor communication is not required except with dynamic
memory which must be refreshed. Therefore, the local
bus boundary scan nets can be tested.
FIGURE 6. Sample Connection File
PRlMARLIO N;
! input tied to GND - set to sense low
OEl
SO;
! input tied to Vee - set to sense high
DSl
S 1;
!Reset Pin - must remain high
! during test
RSTL
D 1;
Internal Logic (External Tester): The same process
used to generate the internal logic tests for the I/O
card was repeated to generate tests for the I/O card's
internal logic nets. A BNET was created to include the
boundary scan nets including the local bus nets; the
selection file was created to point to the BSDL files; a
constraint file was created to force or sense specific
values; and a connection file was created, in this case,
including all three LSPs in the chain.
FIGURE 7. Sample Constraint File
! path to BSDL files for
! devices involved in test
C:\bst\bstlib\ns182245.dsh
C:\bst\bstlib\ns182373.dsh
C:\bst\bstlib\ns18374.dsh
C:\bst\bstlib\ns18541.dsh
C:\bst\bstlib\ns182541.dsh
The processor card's auxiliary port logic (LSP3) contains a logic component connected between two
boundary scan components. Therefore, testing the
nets between these devices requires that signals pass
through this component. A special list, called a cluster
test, was generated to support this connection. To implement a cluster test, the user must provide a set of
functional vectors for the cluster logic, in this case a
single component. These functional vectors can range
from a full functional vector set to only those vectors
required to detect interconnect faults. For the JTAG
Technologies ATPG tool, VIP, the functional patterns
are passed into a post-process file called the APL file.
The APL file is later compiled by the VIP tool to generate the test vectors.
FIGURE 8. Sample BSDL Selection File
Hierarchical Board Test: (only applies to board populating Con 6): This test verifies the same nets covered in the internal test, but includes an extra
SCANPSC11 OF bridge device in the path between the
I/O card and the backplane TAP. The extra
SCANPSC110F bridge is handled in the connection
file and all other input files are unchanged. The connection file is shown in Figure 9.
Internal Logic (Internal Tester): This test is a subset of the external tester version. For the embedded
test version, boundary scan device outputs which interface the processor local bus were disabled
throughout the test. Forcing the boundary scan outputs to a high impedance state was handled in the
constraint file. A portion of the constraint file is shown
in Figure 10.
7-19
http://www.national.com
II
PRlMARY-IO N',
1 input tied to GND - set to sense low
OEl
SO;
1 input tied to Vee - set to sense high
DSl
S 1;
1 Reset Pin - must remain high during test
RSTL
D 1;
1 Local bus pin - forced to high impedance
Z;
CPUDO
Z;
CPUDl
Z;
CPUD2
Z;
CPUD3
CPUD4
Z;
CPUD5
Z;
Z;
CPUD6
NETLIST
lNETname
BP_AO
BP_Al
BP_A2
BP_A3
Configuration file for backplane test.
FIGURE 10. Processor Card Internal
Logic Constraint File
• Backplane: With tests generated for each board, the
only remaining step is to develop tests to evaluate the
interconnects between boards. For the JTAG Technologies VIP tool, a backplane test is viewed as just another
board test. A BNET file for the boundary scan backplane
nets and a connection file are created to indicate the
SCANPSC110F bridges and LSPs containing components which interface these nets. In the case of the National demo, each card's backplane interface logic was
connected to the SCANPSC110F bridges' LSP1. The
backplane test connection file and BNET file are shown
in Figures 11 and 12.
SYNTAX_VERSION 1.2
DESIGN BCKPLN
REVISION UNKNOWN
TESTER_CHANNEL TAPl
lFROM TESTR (PART, ADDRESS, NAME OF TAPS 1-3
lFOR THIS BRIDGE)
MULTIDROP1 (PSC110F, 1, TAP1, NONE, NONE)
!processor card
MULTIDROP2 (PSCnOF, 2, TAP2, NONE, NONE)
1I/0 card 1
MULTIDROP3 (PSCnOF, 3, TAP3, NONE, NONE)
lI/O card 2
END_CHANNEL
FIGURE 12. Backplane Connection File
1 I/O Card 2
CHAIN
TAP3
TCK
TCKL3
TDI
TDIL3
TDO
TDOL3
TMS
TMSL3
TRST
IC_LIST
U324
SCAN182245A
SCAN18254LA
U328
SCAN182373A
U326
END_IC_LIST
END_CHAIN
lPARRALLEL_CONNECTOR_LIST
FIGURE 11. Backplane BNET File
http://www.national.com
PINnumber;
25
55
55 ;
24
53
53 ;
22
52
52 ;
21
50
FIGURE 11. Backplane BNET File (Continued)
continues ••••
END_IC_LIST
END_CHAIN
ICname
un
U126
U326
un
U126
U326
un
U126
U326
un
U126
Embedding the Test Vectors
At this point, the hardware design is complete, the tests
have been generated and the SCAN EASE code has been
integrated into the system. The last step is to embed the
test vectors into the system memory. This action requires
two phases.
First, the vectors must be converted from the ATPG tool's
output file format to EVF. The JTAG Technologies VIP tool
generates test patterns in a unique file format, called the
pattern format (PAT). To translate the PAT files into EVF
files, the SCAN EASE EmbedPrep tool provides a PAT to
EVF compiler. The compiler, called PAT2EVF, is an executable file which runs on a PC or workstation.
Each PAT file, representing a single test, is entered as an
input to the compiler. PAT2EVF also prompts the user for
information regarding the test name, test type and date. The
test name, test type and date are included in the EVF's file
header, which is later used by SCAN EASE to associate
pass/fail status with the specific test.
7-20
With each PAT file converted to a corresponding EVF file,
the next action required is to actually embed the vectors
into memory. For the demo application, an EPROM programmer was used to embed each EVF file into the processor card's EPROM (the same PROM which contained the
SCAN EASE EmbedTest code). EmbedTest uses a single
locate statement to point to the embedded EVF vectors.
Therefore, the separate EVF files must be appended together before programming the EPROM. EmbedTest uses
the file header to determine where each separate EVF file
starts and ends within this single, appended EVF file.
TEST APPLICATION AND FAILURE DIAGNOSTICS
At all stages of the demonstration system's life cycle, a
combination of external and internal tests were performed.
For PCB prototyping and board/system manufacturing test,
an external test was applied, followed by an embedded test.
For field level test, the opposite order was followed. The
system was tested using the embedded tester and then, if
necessary, tested using the external tester. The order of
testing was dependent on the number of failures expected
and the ability to diagnose failures with the embedded versus external test methods.
During prototyping and manufacturing, each PCB (cards and
backplane) is tested for the first time. Therefore, these
stages have the highest occurrence of PCB interconnect
failures. For the demo application, external testing provided
a quick test application and access to the JTAG Technologies diagnostic tool. With this tool, boundary scan failures
were diagnosed automatically to the pin and/or net level.
This extremely tight resolution facilitated board repairs.
Once the failures were resolved, the embedded tests were
applied to confirm correct operation of the embedded test
routines and to enable execution of the non-boundary scan,
functional test routines.
During field level test of the demo system, the objective was
to quickly confirm that the interconnects were sound and
that the system was functioning. Since the system was already thoroughly tested in manufacturing, the likelihood of a
failure was very low. For this reason, the embedded self-test
was an ideal method of testing the system.
For most field applications, the level of field test resolution
is at the board or SUb-system level. The goal in the field is to
minimize system down time. If a failure is found, the board
or sub-system is removed, replaced and retested. Depending on the cost, the board or SUb-system is discarded or
sent back to a repair depot. A similar goal was used for the
demo system. With a separate test for each demo card and
for the backplane, SCAN EASE was able to provide pass/
fail diagnostics to the card/backplane level. If a failure was
found, three options were available:
• Card Removal: The most simple option was to replace
the card with a spare and diagnose the failure at the
factory using an external tester.
7-21
• Embedded Diagnostics: SCAN EASE supports serial
communication with the National demo system. With this
link, new tests are downloaded to system RAM. These
tests offer tighter diagnostic resolution than the card-level tests which are embedded in system ROM and applied
during power on self-test. For example, the power on test
simply shows that the card is failing. The downloaded
tests may view a specific connection between devices on
the card to determine which internal card connections
are failing.
• Off-line, Pin Level Diagnostics: To provide pin level diagnostics for failing demo cards, an external tester and
off-line diagnostics tool was utilized. The connection was
made on the processor card to disable the embedded
tester and provide access to the entire system. Since the
embedded and external testers were connected at the
same hardware location and since the embedded/external tests were identical, the embedded failures were repeatable on the external tester.
For a system which does not provide external tester access, an alternative method of running off-line, pin level
diagnostics is to use the datalogging option and serial
communication capability provided with SCAN EASE to
upload failing vectors to a file. This file is the converted
to a format that is readable with an off-line tool.
BOUNDARY SCAN BENEFITS REALIZED WITH THE
NATIONAL DEMO APPLICATION
Prototyplng Boards and System
For the initial hardware debug, boundary scan proved to be
a tremendous time saver. It eliminated the structural faults
which are often very difficult and time consuming to debug
using functional techniques. Once we were sure that the
components were effectively placed on each PCB, we were
able to focus our efforts on the primary objective of debugging functional and timing related problems.
Manufacturing Process Verification
Boundary scan provided a means of testing the interconnects for the entire system. With the use of the
SCANPSC11 OF bridge on each card, tests were applied using a single, system wide tester connector, but partitioned
for each card and the backplane. Boundary scan enabled
efficient failure detection, diagnosis to the pin/net level and
PCB repair.
Field Level System Test and Diagnostics
The National demonstration system is transported and presented all over the world. Therefore, the ability to test and
resolve failures in the field was a key requirement of the test
capability. With the ability to embed boundary scan test control within the system, the system interconnects were easily
verified prior to each functional presentation. Additionally,
remote access to the boundary scan vectors and test application code enabled test downloading and result evaluation
to occur using a laptop computer.
http://www.national.com
•
.....
0')
co
National Semiconductor
Application Note 891
John Andrews
:Z Non-Contact Test Access
< for Surface Mount
Technology
IEEE 1149.1-1990
ABSTRACT
Mechanical and chemical process challenges initially limited
acceptance of surface mount technology (SMT). As those
challenges have been overcome, another obstacle has become apparent: electronic test access. Through-hole components on a 100 mil grid allowed physical aceess. SMT
which has provided new levels of packing density has also
denied physical test access. To overcome this challenge,
the Institute of Electrical and Electronics Engineers (IEEE)
has sponsored a new standard, IEEE 1149.1-1990, the
Standard Test Access Port and Boundary-Scan Architecture.
THE SMT ASSEMBLY CHALLENGE
The use of SMT has required the refinement of several
technologies including: photolithographic improvements in
printed circuit etching, computer aided layout to support
routing the large number of interconnects, and soldering to
allow devices to be attached to first one and then the reverse side of the printed wiring board (PWB) without
through-hole mechanical capture.
Equipment to pick and place fragile SMT components with
adequate alignment to the prepared pad area was needed
to assure high yield assembly. Optical alignment systems
replaced the open loop equipment used to assemble boards
with dual-in-line packages. The technology has matured.
SMT has gained wide acceptance.
TRADITIONAL DEFECT DETECTION,
DEFECT ISOLATION
A high yield assembly process, always a target, is important
for SMT printed circuit cards because it can be difficult to
isolate faults. There is risk of assembly damage during repair. If an incorrect diagnosis results in an unnecessary repair, not only are repair costs higher than necessary, but the
risk of damage increases.
Bed-of-Nails test fixtures such as shown in Figure 1 have
provided test access for over twenty years. These fixtures
have at least one test probe per IC pin to provide access for
printed circuit continuity checking. Low voltage PWB interconnect continuity tests are usually run before applying full
power to the PWB. Each connection point on each network
is checked for continuity to all expected connections. In addition, by forcing a sequence of bits onto each output pin
with the bed-of-nails and then reading the signal received
on every other net, it is possible to detect nets that are
shorted together and often to tell which two nets are shorted.
Once interconnection defects have been isolated and repaired, it has been common practice to use the bed-of-nails
to drive each net of the fully powered board to test each
integrated circuit on the assembly. For very simple ICs such
test patterns were readily developed. A few microseconds
were often adequate to determine that a simple IC was
functioning correctly. During these functional tests, the electrical connection of the IC to the printed circuit board was
checked as an integral side effect of the test.
TL/F/11568-1
FIGURE 1. Traditional Bed-ot-Nails PCB Test
Access Method, Now Challenged by Shrinking
Physical Contact Possibilities
Forcing a net with a bed-of-nails contact often required
backdriving an IC's output. It might be necessary to force
several hundred milliamperes into an IC's output to force a
network to the opposite logic level. Backdriving IC outputs
does not improve component lifetime. As IC complexity has
grown, it has taken more test vectors and therefore required
more time backdriving IC outputs.
As SMT allowed packing density to grow, printed circuit layout software began to appear with features that allowed
physical access to continue with traditional bed-of-nails
testing. Figure 2 shows a portion of a layout that supports
continued access. While supporting test access to allow defects to be detected, this defeated the advantage of SMT:
higher packaging density. In addition, layout software became more complex as it was used to help overcome access problems.
TL/F/11568-2
FIGURE 2. Despite Shrinking Component Sizes,
Some Users Have Kept Large Feature-Sized Etch
to Continue to Support Physical Access
To support physical access some manufactures began using bed-of-nails fixtures that could contact both sides of a
PWB. One user, in a personal communication, reported that
these fixtures were so fragile that they might need to be
repaired after testing as few as ten SMT printed circuit
cards. And the time to develop such fixtures often extended
beyond system development time and delayed the start of
high volume production. Some users have reported that developing an SMT bed-of-nails fixture added 10% to their
board development cost.
Paper first published at Surface Mount International, 1992.
http://www.national.com
7-22
IEEE BOUNDARY-SCAN TEST ACCESS
Toward TOO
IEEE 1149.1 was defined to replace the test access provided by a bed-of-nails test fixture. Figure 3 shows an idealized
concept of what was needed. As shown, a scan cell (SC) is
located at each input and at each output pin. An output SC
cell must be able, in test mode, to force the logic state of its
output pin without regard to the state of the system logic.
Similarly, each input SC must be able to monitor the signal
on its input pin. IEEE 1149.1 was developed to provide this
drive/sense capability using, not external test probes, but
internal test circuits.
...., ...,
From System logic
~~------------------~--------~, M2 ~
r-f-~I----'---"";
I
I
,
- - - ~--~ ___ !
F2
I
I
,
ji'---!
Update
From TOI
TLlF/l1S68-4
Toward TOO
From System logic
Update
From TOI
TL/F/l1S68-S
TOI
TCK
TMS
FIGURE 4. With IEEE 1149.1 I/O Pins May Capture
the Data Arriving at a Pin and They May Be Used to
Control Output Pins. Test Circuits Such as These May
Also Test Internal System LogiC. Circuits Such as These
are Added to All System Pins
TOO
TLlF/l1S68-3
FIGURE 3. Bed-of-Nails Test Access Has Been
Replaced by Adding Embedded Test Probes to Each IC
Input and by Providing Test Drivers at Each Output.
Driving Outputs and Sampling Inputs is Called EXTEXT
data into an instruction register. With the flexibility provided
by an instruction register, IEEE 1149.1 is able to support an
almost unlimited number of optional test features.
As its name implies, boundary scan provides a scan path
around the boundary of an IC as shown in Figure 3. Scan
test access is a methodology that allows each IC to provide
test access from within the IC itself, not from an external
array of physical probes.
In 1149.1 the ability to drive test values onto output pins and
to capture input logic states using the test logic is called
EXTEST for external test. Most interconnect faults may be
detected. For example, if a surface mount IC has a lead that
is not attached to the printed circuit module as shown in
Figure 5, the fault can be detected. Assume that this is an
output, if the boundary-scan cell at that pin attempts to
force the connected network, there will no response on the
inputs that should be driven. The input boundary-scan cells
of other ICs will detect a defect when they sample their
input net.
SILICON NAILS
Figure 4 shows an example of the kind of simple circuits
needed to sample IC inputs and to replace the normal, mission mode drive values with test values. At each input we
need a means for capturing the input signal and then shifting it out for external examation by automated test euuipment (ATE). This input circuit has shown in dashed lines
some optional logic that will be discussed later.
The typical output boundary scan circuit is able, with limited
external control signals, to become the source of the logic
state that will drive the external interconnections. This is a
solution to the simple problem of driving and sensing printed
circuit board interconnections to detect process defects.
As shown in Figure 3, a test access port (TAP) controller is
located in each IC to allow the ATE to control the boundary
scan cells. The operation of the TAP controller and the implementation of its instructions have been described in detail in the IEEE standard.(1) The TAP has four dedicated test
pins: Test Data In (TOI), Test Data Out (TOO), Test Clock
(TCK), and Test Mode Select (TMS). TOI and TOO are used
to shift test data in and out of each 1149.1-compliant IC.
TL/F/l1S68-6
FIGURE 5. Lifted IC Leads, Not Accessible with
Bed-ot-Nalls by the Embedded Probes ot the Driving
and Receiving IC, If they Implement Boundary-Scan
Before 1149.1, to force the output driver in the IC with the
lifted pin required that the automated test equipment generate a sequence of test vectors to force the inputs of the IC.
This pattern would indirectly control the IC output. Controlling IC outputs from the inputs requires a complete functional understanding of the IC. This points out another advantage of IEEE 1149.1: PWB interconnect test programs can
be developed without a detailed understanding of the function of each IC on the PWB. This simplification has resulted
in test development time reductions that have compressed
schedules from months to as little as one day'(2)
TCK shifts the data through each chip, while TMS controls a
16-state finite state machine in each IC. The state machine
determines what each IC is doing. For example, an IC may
be sampling its input, shifting data or driving outputs. In fact,
the TMS input together with the TAP controller can shift TOI
7-23
http://www.national.com
•
.....
~
Z
z
Co
Q)
.....
L::::===~-vcc
......- - - - - - - - O l h . r pins
Tl/F/11554-1
FIGURE 1
-
Isolation Circuitry
plane over a range of backplane voltages from O.OV to
5.5V.
Isolation circuitry provides another option for board and
backplane isolation. Again, this solution will provide the
necessary ~ pin biasing to assure a level of 2.0V or to
assure OE maintains ~50% of Vee as Vee powers up
or down for guaranteed high impedance interface to the
backplane.
-
The design of Circuit-1 below provides> 50% of Vee for
the OE pin throughout the Vee ramp then switches to a
voltage level of a logic high once the ACOO reaches its
turn-on Vee. After board insertion, the MAINT switch is
opened and the LOGIC pin becomes the DE control.
Live insertion or removal for this solution requires a technician to manually operate the maintenance switch
(MAINT) to ensure proper biasing of OE and boardbackplane isolation.
VID
VID is a voltage that is measured on an input pin at a
current loading of 1.9 p.A in a power off condition
such as when Vee and the non-measurement pins
are at O.OV.
The curve of VID vs liD in Figure 2 shows the current
leakage of a typical ABT input pin. The ABT inputs
limit loading leakage to < 1.9 p.A over an input voltage range from OV to 5.5V.
0.50
0.40
...
0.30
.3
Clrcult-1
Circuit Board
.;! 0.20
•
Backplane
0.10
••
0.00
5k
V- I-'- t - ro
Io"" r--
TL/F/11554-4
FIGURE 2
LOGIC
-
"'' 1
---------------------.
The curve of VZZ vs IZZ in Figure 3 shows the current leakage of a typical ABT input/output (1/0) pin
and how it loads a bus or backplane over a range of
bus voltages from O.OV to 5.5V. 1/0 pin configurations exhibit combined current characteristics from
components of the input circuitry and output circuitry.
ABT 1/0 pins specify loading leakage at 100 p.A max.
with a typical loading leakage at 3 p.A at room temperature.
TL/F/11554-2
SPECIFICATIONS AND THEIR CONTRIBUTION TO
FAULT TOLERANT SYSTEMS
DC specifications and their characteristic input/ output
curves help map out the loading effects of an interface device on bus or backplane. The loading characteristics of typical ABT input and output pins are shown in Figures 2-4.
National Semiconductor's ABT245 characteristic curves are
used for this demonstration.
-
IZZ
IZZ is a current that is measured on an output pin at
a voltage of 5.5V during a power off condition such
as when Vee and the non-measurement pins are at
O.OV.
ABT245
10.0
B.O
Powered Down Backplane Isolation
The power down leakage characteristics of a bus interface device assist the interface board designer in understanding the effects of loading on his backplane. During
live insertion, the board is not powered up and the instantaneous loading upon contact would look like the
curves of VID and IZZ in Figures 2 and 3. Typically, loading leakages in the + 200 p.A range begin to affect the
VOHIVOL levels in a backplane application. The VID and
IZZ curves illustrate the loading effects on the back-
...
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4.0
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FIGURE 3
7-27
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Vee (V)
TL/F/11554-7
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FIGURE 5. Bus High Effects
http://www.national.com
1
FIGURE 6. Bus Low Effects
7 -28
l>
SUMMARY
ABT interface devices offer glitch free power cycling provided that the DE pin is held at the device specified VIH (2.0V)·
level. In practice, DE will provide an output high impedance
condition if DE maintains a level of :2!50% of Vee through
the OV to 5.5V range. In fact, the DE pin circuitry gains
control once Vee is :2! 1.0V. Interface device output characteristics for Vee levels before 1.0V are controlled through
the isolation circuitry discussed earlier.
ABT designs and specifications recognize the need for
more fault tolerant interface devices. Uve insertion guarantees such as VID/IZZ, IDZLlH and glitch free power cycling
all promote better system uptime, especially for telecom
switching environments. Together with extended AC specifications that reduce the need for complex performance evaluations, ABT live insertion guarantees allow designers to
spend more time on total system performance features and
not worry about the logic.
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MEMORY MAP
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The G.Host maps functions to memory address in Table I.
TABLE I. Memory Map
Address Space
(hexadecimal)
AM29200
Mlcrocontro"er
Selection
Maximum Size
G.Host
Assignment
AM29200
AM29205
ROM BankO
ROM Bank 1
ROM Bank2
Boot Code
Application Code
Self-Test Port
64 Mbyte
Bank Size
User Set
12 Mbyte
Bank Size
User Set
DRAM
Data Memory
64 Mbyte
12 Mbyte
Mapped DRAM
Not Used
16 Mbyte
16 Mbyte
6000000063FF FFFF
VDRAM Transfers
Not Used
64 Mbyte
80000000800000FC
Internal Periperal
Registers
(See the following
table for addresses)
9000000090FF FFFF
PIA Area 0
Not Used
16 Mbyte
4 Mbyte
9100000091FF FFFF
PIA Area 1
Not Used
16 Mbyte
4 Mbyte
9200000092FF FFFF
PIA Area 2
Not Used
16 Mbyte
9300000093FF FFFF
PIA Area 3
Not Used
16 Mbyte
9400000094FF FFFF
PIA Area 4
Not Used
16 Mbyte
9500000090FF FFFF
PIA Area 5
Not Used
16 Mbyte
A" Others
Reserved
0000000003FF FFFF
All ROM Banks
4000000043FF FFFF
All DRAM Banks
5000000050FF FFFF
All Mapped DRAM
PIO CONTROL LINE ASSIGNMENTS
TABLE II. PIO Control Line Assignments
The G.Host assigns the peripheral input/output control lines
of the AM29200 family microcontrollers as follows:
PIO Line
7-39
G.Host Function
Data Direction
PI015
Serial Port CTS
Input
PI014
Serial Port RTS
Output
PI013-PI08
Spares
PI07-PIOO
(Not used)
(Not yet assigned)
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ADDR[0 .. 23]
ADDR[0 .. 23]
JTAG2[1..6]
JTAG3[1 .. 7]
t.4SCctl[I .. 15]
Data_HI[ 16 .. 31]
,
ADDR[0 .. 23]
JTAG2[1..6]
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ADDR[0 .. 23] :
t.4Et.4ctl[ 1.. 16]
Data_HI[ 16 .. 31]
-
t.4B[0 .. 12]
~
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~
ADDR[0 .. 23]
-
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CPU Block
Ser_10[1 .. 4]
DRAD[0 .. 12]
t.4SCctl[ 1.. 15]
Data_HI[ 16 .. 31]
If'
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t.4SCctl[I .. 15]
t.4Et.4ctl[I .. 16]
o
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JTAG2[1..6]
]
4
h
t.4Et.4ctl[I .. 16]
JTAG1[1 .. 5] • ~5
1
JTAG3[1 .. 7] •
DatILHI[ 16 .. 31]
1
JTAG Interface
[
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I
[
0
]
I
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GHOSTSER.sch
System t.4emory Block
~
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~DATA[0 .. 31]
GHOSTt.4Et.4.sch
PP[I .. ll]
PD[I .. 8]
~Data_LO[0 .. 15]
GHOSThpl.SCH
t.4ACH I/O
Parallel
I/o
DRAD[0 .. 12]
DRAD[0 .. 12]
JTAG3[1 .. 7] •
t.4B[0 .. 12]
~
ADDR[0 .. 23]
~
t.4B[0 .. 12]
DATA[0 .. 31]
~
£
~
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Data_LO[0 .. 15]
~
DatILLO[0 .. 15]
~
HSCctL[ 1.. 15[
t.4Et.4ctl[I .. 16]
DATA[0 .. 31]
PD[I .. 8]
PD[I .. 8]
~
:. PD[I .. 8]
"
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HSCctL[ 1.. 15]
PP[I .. 11]
pp[ 1..11]
pp[ 1.. 11]
PIActl[I .. 4]
PIActl[1..4]
~
PP[1..11]
GHOSTPER.sch
PIActl[I .. 4]
JTAG3[1 .. 7] ...
GHOSTIO.sch
GHOSTCPU .sch
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FIGURE 2. Top Level Block Diagram
ADDR[O .. 23]
~E~ctl[ 1.. 16]
Data_HI[ 16 •• 31]
Data_LO[O .• lS]
29200
~ICRO
29205
ADDR[0 .. 23]
...
~
ADDR[0:23]
~EMctl[1:16] ~
~E~ctl[1..16]
...
DatLHI[16 .• 31]
--.J
I.....(
ADDR[O .. 23]
...
~E~ctl[ 1.. 16]
~ICRO
Data HI[16:31]
DatLHI[16 .. 31]
Data LO[0:15]~
DatLLO[O •. lS]
~SCctl[1..1S]
~SCctl[ 1•• 15]
~SCctl[ 1: 15] ~
"'II1II
pp[ 1.. 11]
PP[1..11]
"'II1II
PIActl[1..4]
PP[l: 11]
~
PIActl[l:4]
~
JTAG2[1:6]
~
Ser_10[1:4]
~
PIActl[1..4]
"'II1II
JTAG2[1..6]
Ser _lOr 1. .4]
Ser _lOr 1.. 4]
"'II1II
GHOST200.sch
GHOST20S.sch
,......(
~SCctl[1..1S]
PP[ 1..11]
PIActl[1..4j
::T
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JTAG2[1..6]
Ser _lOr 1..4]
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HI30
HI29
HI28
HI27
HI26
HI25
HI24
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18
139
69
Dot •.
Oat_
O_t_
D.t.
O.t.
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Dot.
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HI23
HI22
HI 1
HI20
H 19
HI 8
HI17
HI16
201
05
8
06
90
7
3
34
D_t_ L015
014
_t_ 013
D_t_ L012
D_t_ 011
D_t. LO 0
D_t. L09
D.t.
8
61
11
124
137
1
65
175
0
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D.t_
D_t.
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1
6
207
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39
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D_t_
D_t_
O_t_
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Data
O_t_
D_t.
D.t.
L07
L06
LOS
L04
0
L02
LOI
LOO
AODRU
ADDR12
ADDR10
ADDR9
ADOR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDRI
16
72
126
165
21
174
49
189
110
60
125
31
136
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~1~l~l~l~l~Ud~kl~l~M~~ ~hl!~ld~§l~ ~
0.. 0..0..0..
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V1~V1V1Vl~V'lV13:;I:...J~:;;:
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--
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DATA 23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
ATA16
1015
1014
1013
1012
1011
1010
109
108
015
014
013
012
011
010
09
08
140
102
159
64
171
195
169
108
DATA 15
IlATA14
DATA13
DATA12
DATAll
OATA10
OAT19
TA8
07
06
05
04
03
02
01
DO
138
173
162
142
101
141
100
54
OATA7
OATA6
DATA5
OATA4
DATA3
DATA2
DATAl
DATAO
114
PIASCO
119
PIASCI
164
PIAOE
PIAWE 197
PIAetil
PIAell2
PIAel13
PIAel14
a..cn~
CD
c:(
107
106
IDS
104
103
102
IDI
100
AU
A12
AID
A9
A8
A7
A6
AS
A4
A3
~
AI
- ..,
"'c
~~
.... o
oooo~occcccccc
~~
~~~~~~~uuuu
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Wzo..~
::Iwcnu
~~~~oooooooooooooooooooooooooooo
-N N"''''
"' .... ""
_
- '"- '!g1'I11111'l11·""·
"'~~1q~q~~1q'iii
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l~l~rrl~!
Vce
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:;;
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::>
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::>'"
:;:::;:;
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"'''' ::>::>
:::.::>
"''''
!!
::E:::::I::::E::::E
::::E::::E::::I::::::E
o
8
16 G ADG433
1 = ON
~SCetl[1..15]
"\
q
100 kP"
~"'"
~_
J5
r--:-
4 RPSD
'-O-NI"")
168
122
6
191
57
8
170
ORAD12
192
ORAOll
66
DAR010
153
ORA09 103
M~
200
DARD7 149
152
150
118
_000::> ~A~ 148
DRA012
ORADll
DRAD10
o
9 G
I
10
l=orr
~SCetl16
Vee
U18C
AOG433
i p...-
1:;;0><_'" g~!g~
i
~~~~~
~PIAetll
ORAD[O .. 12]
.. 4
DRAD 0 .. 12
"'"<
>
JTAG3 1.. 7
>
>
~ACH465
I"
3
RP2C
JTAG35
'2
2 RP2B '3
I kP
3
1 kP
~~
6
7
8
>
>
DATA 0.. 3
PIAetl[I .. 4]
DRA09
DRAD8
RAD7
DRAD6
DRAD5
DRA04
DRAD3
DRAD2
g!~g~
0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z0
z
-~.
1..15
48
023
022
021
020
019
018
017
016
CON
<,~SCell
OATA31
OATA30
OATA29
OATA28
OATA27
OATA26
DATA25
DATA24
1023
1022
1021
1020
1019
1018
1017
1016
~
O-N
~Et.tctl[I .. 16]
47
133
109
96
113
193
46
1
:g~~
~~~~ a...~~~~~~ ~~~~~~~~CD~~~~
~
0.. 12
DATA[O •• 3]
U3
__
>~>S>S>S>~>~>tJ>tl>S>tJ>S>~>S>S>S>S>8>8>S>S>S>tl>S>S
CDV1U .....
~
>
~
o
::>
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o
o
3
UU
ADDRI9
ADDRI8
ADDRI7
ADDRI6
ADDRIS
ADDRU
ADDR13
ADDRI2
ADDRII
ADDR I 0
ADDR9
ADDR8
~~~~~
ADDRS
ADDR4
ADDR3
ADDR2
17
48
I
2
3
•
5
6
7
18
19
AI7
AI6
A IS
AI4
AI3
AI2
All
Al0
A9
A8
A7
A6
~~~!
22
23
24
25
~!~
BYTE
RESET
~E~ctl[I:16]
VCC
12
U.A
.5
DOIS/A-I .3
DOl • • ,
0013 39
0012 ~3;';6-";;";'T'A?T-.
0011i-'3'"".-";;";'T'.,.DO I 0 """32""'-"'niTA?<
009 "3'""0--;;;;""008 .....,..,.4,....-"";;";"""~
~~~ :~
A3
A2
AI
AO
DOS 38
004 "3'""S-";;7T"Q
003 """"33;---;;-;y..-;-• .
002 31
a
19
AND
2
N.C.
N.C.
N.C.
N.C.
N.C.
IS
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22VIO
BWAIT
I~
I
ROMOE
I
RCELO
2
3
AI.
AI3
AI2
All
AIO
A9
A8
A7
A6
AS
H
A3
A2
Al
AO
18
19
20
21
22
23
24
2S
MBIO
JTAG26
DATA31
DATA30
DATA29
DATA28
DATA27
DATA26
DATA2S
DATA2.
r-
Vcc
ADDRI6
ADDRIS
ADDR14
ADDRI3
ADDR12
ADDRII
ADDRIO
ADDR9
ADDR8
ADDR7
ADDR6
ADDRS
ADDR4
ADDR3
ADDR2
MEMCTL1.,
22VIO
UIS
AI7
A16
A IS
~Gl
12
"5ATAi9
Dllii"8
iiAT"Ai7
.S
DATAIS
DOIS/A-I 43
DATAU
DOU 41
DATA 13
0013 39
OATA12
0012 36
DATAl 1
DQll 3.
DATAIO
DOlO 32
DATA9
009 30
DATA8
008.
DATA7
4
007 42
DATA6
D06 40
OATAS
DOS 38
OATH
004 3S
DATA3
D03
002 I-=--;;-;"T"'--DOl
000
~
r-:-::-";':;:':;=~-~'II~
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DATAiO
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J
AIO
All
AI2
AI3
AU
AIS
AI6
AI7
AlB
DATA23
Vcc
BYTE
RESET
-
)
../
RO~CSO
(J)
17
.8
I
nI
~Et.4ctl[I:16]
MBI2
OR2J
;,.
ADDRI9
ADDR18
ADDR17
II
-<
~ ~B[0:12]
16
18
-..J
::::TL1
~B[0:12]
AOOR[O:23]
~
OATA[O:31J
)
U.D
DOI"""29-"'niT..-;cDOO
10
13
14
16
I:
t;
...f
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iiA'iAi6
LVcc
DIRI
DIR2
Vcc
Vcc
Vcc
Vcc
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SS
VSS
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FIGURE 8. FLASH Memory
~
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JTAG LINK
ORAo[a .. 12)
IDRADIO •• 12)
Vee
Vcc
'"'"
'"
i
000
001"1"'0-002 13
003 ......- 16
004 20
DOS 23
006 25
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"''''
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9
~
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~
~
t\:
ViR
MB9
/
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RAS
CAS
TOO
TOI
'----~Al0
VSS
VSS
L.::==::t~! g
~
L.:===:jtl!:
'----------';.£-1 A15
N.C.
L -_ _ _ _ _--'.l'-! A16
L-_ _ _ _ _ _
N.C.
N.C.
N.C.
~
Bl0
v
~_ _-!"!lU.l1-...-
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::~ ....7;;-_ _~.e..L~
~:~ ~'----¥!lg.;1-...-
A17
~-----~~~~
f4
~
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B21
B22
B23
~
Vce
U 13
Vee
r~::t:=:m !~~
A27
B25
B26
A28
B28
3
B27
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g~g
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N.C.
N.C.
N.C.
25
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~~l!---+!~ A8
"""·'lJLL.l...--..J..>4 A9
GND
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~
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ViR
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~
1
CAS
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dvss
~
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N'C'
2
~
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10kP
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A24
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~--I-~~ A26
A27
A28
GZ
t\.
OIRl
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'"
Vce
Vee
Vce
~
Vee
~: ~ ~~----!!.8J.!,ZL-'
B17
B18
B24
B25
B26
B27
B28
GNO
GND
GNO
eND
eND
eND
eND
eND
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L.....
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1-..,
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3
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10 kP
4~~3?11
12
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N.C.
N.C.
N.C.
A18
BU t7::----II.!l..Laj~
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t::
t::
A 10
All
VSS
' - -_ _ _
B24
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VSS
m B20~
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TOO
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B17
B18
A18
ViR
21
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I
I
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MBO
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U9
N'C'
N.C.
N.C.
N.C.
IoICIoI84000
MCM84000
BCASI
BCAS3
BRDbR
BRD/WR
0.1.[0 .. 31)
J
~"r...,oJ"
:::l
ao·
WBr 0 - : 1 i j ) '
WB[0 .. 12j
:::l
TUF/12119-8
!!!..
o
o
FIGURE 9. DRAM (Data) Memory
3
eOO~-N\f
II
AN·1003
a
1
1 RP4A 14
~
~
o
JTAG3[1:7]
:l
!!!.
83
Vee
Vec
(
JTAG3[1 :7]
.....
....
'"
'"
PO[I:8]
PO[I:8]
~
......J!.
~
POI
P02
P03
PD4
P05
PD6
PD7
PD8
~-
~-
,
55
53
52
50
49
47
46
44
43
,...li
......
1.
0)
42
41
39
38
36
35
33
32
30
AeK
PP10
PP9
BUSY
HIS
TCK f.=.=-
Al0
All
A12
A13
Bl0
Bll
B12
B13
<>
A16
A17
A18
PP7
3
26
Vee -
:
5
RP3E
10 kP
10
~
""it
_ tji
'""
'""
Q,
::~
B16
B17
B18
A20
A21
A22
A23
:~~
B20
B21
B22
B23
=>
A26
A27
A28
DIRI
DIR2
Vee
Vee
Vec
Vee
:;~
B26
B27
B28
GNO
GND
GND
GND
GNO
GNO
GNO
GNO
a.
",7
PP8
PPll
'"
PP[I:I1]
>-
3 RP4C 12
6 RP4F' 9
4.7 kP
4.7kP
' y
L.~
f-o
14
2
.!f.3 ~
~
4 f-o
J+.5 f-o
BPOI
BP02
BP03
BP04
BP05
BP06
BPD7
BPD8
2
4
5
7
8
10
11
13
18
6
19
7
20
8
21
9
22
10
23
11
24
..!.L-
Gi
~ G2
PROm
4.7 kP
i9
TOO
TO!
::~
4.7 kP
AUTom
U19
~
4.7 kP
5 RP4E 10
'.
STROBE
(
4.7 kP
2 RP4B 13
' y
~
~
4 RP40 11
SCAN 18245T
STROBE
AUTOFD
~
~
18
19
..4
22
ACK
BUSY
24
II
-hit'
25
13
OB25
Vee
Vec
"TItr
9
RP3F'
10 kP
1 RP5A 14
:tt I",7
r
f-o
U":'::"L,/
6
it"
Ta-
--
.g. f-o
~
JJ...
--
V
4 RP5D 11
UkP
4.7 kP
2 RP5B 13
5 RP5E 10
4.7 kP
4.7 kP
3 RP5C 12
6 RP5F' 9
'y y
4.7 kP
, yy
4.7 kP
TL/F/12119-9
FIGURE 10. Parallel Interface
Vee
0.1 J.LF
U5
16
rVee
V+
V-
Cl
C2+
C2-
T10UT
TllN
PI
TXD
RXD
~
13
RllN
Rl0UT
RTS
T20UT
T21N
h
12
Ser _102
10
Ser _103
Ser _104
CTS
R21N
-...j
Ser _101
R20UT
151
J:,.
co
GND
GND
JTAG1[1..5]
AX202
JTAG 1[ 1:5]
Tt.4S
JTAGll
TDI
JTAG12
TCK
JTAG13
TDD
JTAG14
JTAG15
TRST
D825
TUF/12119-10
FIGURE 11. Serial Port
:T
::::
j
:::l
acr
:::l
~
g
3
eOO~·N\f
II
AN-1003
'::f'
1
:::l
a(:;-
l
MSCctl[ 1•• 15]
MEMctl[1..16] ~
-
<
MSCctill
J2
~In..
ADDR[0 •• 23]
210-3 h
:::l
~
J>
3:
410----
:5 ~
(-)
o
3
~.=.
6~
;..,:0;
7 ""8 ,..
9""100..-
~
A
-
II
5 It-\..
~
TRST rx
TOIB8
TOOB8
TMSB
TCKB
U4C
1
-
171
1
1
INVERT
"'I
~I ~
3:
3:
VI
~
~ ~
0-
~
:;::j
5~~6&El0
~
5
YO'''
100 kP
1 kP
5~P2El011
Vee
-i-
vuJ
U6
RST
-
V
ADDRO
1/ ADDR1
1/ ADDR2
1/
_
12
~
CE_
R/W
STB
AO
A1
A2
DO
~D3
,. ,.. ,... ,...
OND
~~~:C PSC100F
CD
~
tJ)
CD
I
I
I
I
:I::I::I::I:
;;~;;~
26
25
TMSO
GND
TOO
RDY
INT
D7
D6
D5
D4
23
22
21
F-
S1
S2
S3
S4
S5
Vee
TRST
TMSB
TCKB
TOIB
TOOB
GND
~
0
-vVee
JTAG3[1..7]
JTAG37
JTAG33
JTAG31
JTAG32
JTAG24
JTAG23
JTAG25
JTAG21
JTAG22
JTAG15
JTAG13
JTAGll
JTAG14
J
JTAG2 [1..61
~
......... JTAG3[1..7]
-"'>
JTAG2[1..6]
">
JTAGl [1..5]
"">
/
-/
-/
-/_ JTAG1[1..5]
~
6 ~P2I 9
..
"
1 kP
~
7 ~P2G 8
~
19
18
17
16
15
so
<>
INTR3
1 kP
1
00 00
!!~ !!~
III
III
..
III
I
I
I
I
:I::I: :I::I:
~
L---
<
TOI
TCK
TMS1~
~~
U4r
V
OE
VI
'"
PSC110r
r~~~
~~K
4
5
6
7
8
9
10
11
i:/
6
7
8
9
10
11
12
13
14
28
TDlE§ 27
TCKL3 26
25
TMSL3
24
TOOL3
23
TOIL2
22
TCKL2
GND ~
20
TMSL2
19
TOOL2
TOIL 1 18
TCKL 1 17
TMSL1 16
TOOL 1 15
z
""
3:
- i, (")
22Vl0
~
........ MSCctl[ 1..15] ")
/
I~INVERT
22V10
~
4R~2Pll
yyy
-..J
In
o
L6
I RESET
r-+
22Vl0
Vee
AND
n
U7
L...-
VI
17
//
U4E
10 I
~
0
3:
'"
MEMCLK
NN NN
o~
N""
~~
,V------"
Data HI[ 16 •. 31] ....... Data_HI[ 16 •• 31]
TL/F/12119-11
FIGURE 12. JTAG Interface
+5V
Jl
Vee
l..:.o
1
51 0 2
~powrR
~1
0 +5V
vee
r y
n
Vee
vee
r
Vee
Vee
-.,J
~
Vee
:T
1
TUF/12119-12
:l
ao·
FIGURE 13. Power Supply
:l
!!!.
oo
3
£OO~-NV
II
AN-1003
;;r
i
::J
~
<
--
t.tSCc\I[1:15)
)
t.tEt.tctl[1:16)
)
t.tSCc\I[1..15)
o
::J
"1
I
.......
'"'"to,,,] )
,.,
!!!.
o
3
JP1
<
AOOR[O •• 23)
TllTl
JP2
t.tEt.tdl[1..16)
~
"
~
LI
JP5
AOORO
AOOR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDRB
ADDR9
ADDR10
ADDR11
AD DR 12
ADDR 13
ADDR14
ADDR 15
~
1..8) -'PDi1:8l
.......
en
PO[
I\)
JP4
<
JP3
./
JP6
Oa\LLO[O •• 15)
Da\LLO[O: 15) ;:.
<
Da\LHI[ 16 •• 31)
t.tS[O •• 12)
OatLHI[16:31) ).
(
PP[O: 12)
>
TL/F/12119-13
FIGURE 14. HP Logic Analyzer Interface
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co
....
National Semiconductor
D)
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Integration of Analog Test
:s
D)
The application illustrated shows an ADC0858 monitoring
system heat sink temperature, supply voltage and current
limit, the tolerances for each being loaded into the onboard
RAM. If an input exceeds its allowed range, an interrupt is
triggered prompting the host microprocessor to adjust the
tolerances, take other corrective action or simply datalog
the failure.
In this application, an LP2951 low drop-out regulator supplies reference grade power and the conversion voltage reference for the ADC0858. The four low power Op amps of a
CMOS LMC660 scale the inputs to 2.5V and provide a railto-output voltage swing that optimizes the ADC0858's full
scale conversion. A ± O.soC temperature accuracy is provided by an LM 135 temperature sensor. The 0.1 n resistor between CH6 and CH7 serves as a current monitor.
The IEEE 1149.1 standard is a strictly digital standard and
makes no provision for analog test. The IEEE 1149.4 working group has been formed to address the challenging task
of developing analog and mixed signal test standards compatible with the existing digital standard.
One solution available today is the ADC0858 Data Acquisition and Monitoring System. This device is an 8-bit programmable WATCHDOGTM that sequentially checks the voltage
at each of its eight inputs, producing an interrupt when the
voltage is outside a programmed window. Digital readings
can be serially downloaded for evaluation. Device programming is accomplished through a serial data port. Since both
device programming and data downloads are accomplished
via their respective serial ports the device can be readily
connected to an 1149.1 ring using either an Embedded
Boundary Scan Controller, SCANPSC1 OOF or SCAN Hierarchical
and
Multidrop
Addressable
JTAG
Port,
SCANPSC110F Bridge.
Vref
vee
10kn
1--_ _ _ _-+-_..;T;.;.em;.;;:p~in~CHO (+)
Heatsink
Temperature
Monitor
. - - - - - t C H 1 (-)
1.28V
T. Min.
Adj.
AoC08S8
SCANPSC 1oor
r-------I
10kn
I
I
Open
Collector
Data Out I----I~ Tol
2.SV
CH2
+SV:l:S%
Data In I + - - - - - t TOO
38kn
2.SV
CH3
2.SV
CH4
2.SV
CHS
+12V:l:S%
Voltage
Monitors
Cs I + - - - - - t TMS
20kn
-SV:l:S%
4.17kn
20kn
-12V:l:S%
ClK .+-----1 TCK
. - - - - - - - - - - - - - - - - - - I C H 6 (+)
DC Current
t./onitor
0.1 n
1%
Current Sense
Resistor
L . . . - - - - - - - - - - - - - - - - t C H 7 (-) GND
TUF/11575-1
ADC0858CMJ/883 Monitors System Temperature, Voltage and Current
7-53
http://www.national.com
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ADC0851 and ADC0858 8-Bit Analog Data
Acquisition and Monitoring Systems
o
c General Description
< The ADC0851 and ADC0858 are 2 and 8 input analog data
acquisition systems. They can function as conventional multiple input AID converters, automatic scanning AID converters or programmable analog "watchdog" systems. In
"watchdog" mode they monitor analog inputs and determine whether these inputs are inside or outside user programmed window limits. This monitoring process takes
place independent of the host processor. When any input
falls outside of its programmed window limits, an interrupt is
automatically generated which flags the processor; the chip
can then be interrogated as to exactly which channels
crossed which limits.
The advantage of this approach is that its frees the processor from having to frequently monitor analog variables. It
can consequently save having to insert many AID subroutine calls throughout real time application code. In control
systems where many variables are continually being monitored this can significantly free up the processor, especially
if the variables are DC or slow varying signals.
The Auto AID conversion feature allows the device to scan
through selected input channels, performing an AID conversion on each channel without the need to select a new
channel after each conversion.
Key Specifications
•
•
•
•
•
Resolution
Total error
Low power
Conversion time
Limit comparison time
8 Bits
± 112 LSB or ± 1 LSB
50 mW
18 ,...s/Channel
2,...s/Limit
Features
• Watchdog operation signals processor when any
channel is outside user programmed window limits
• Frees microprocessor from continually monitoring
analog signals and simplifies applications software
• 2 (ADC0851) or 8 (ADC0858) analog input channels
• Single ended or differential input pairs
• COM input for DC offsetting of input voltage
• 4 (ADC0851) and 16 (ADC0858), 8-bit programmable
limits
• NSC MICROWIRETM interface
• Power fail detection
• Auto AID conversion feature
• Single 5V supply
• Window limits are user programmable via serial interface
Applications
• Instrumentation monitoring and process control
• Digitizing automotive sensor signals
• Embedded diagnostics
Simplified Block Diagram
RAM
HIGH LIMIT
lOW LIMIT
1----1 ~ ___ J--L-.L.....f ~
5
t----I
11
~:::::~ 13
:pADC0858 ONLY)
10
:
~
. - Vee
'-OGNO
CONTROL lOGIC
SHIFT REGISTERS
CS--------------------~~
ClK --------------------~~
DI--------------------~~
OSC~
CONTROL REGISTERS
TIMING GENERATOR
POWER ON RESET
OSC
1 - - - + DO
1 - - - + EOC
1 - - - + iNr
TL/H/11021-22
FIGURE 1
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7-54
l>
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Connection Diagrams
Q)
U1
...&.
ADC0858
8-Channel MUX
Dual-ln-L1ne Package
ADC0851
2-Channel MUX
Dual-ln-L1ne Package
D)
:::l
a.
l>
C
16
OGNO
Vee
COM PH
OSC
19
CH 1
cs
14
COMPl
cs
18
CH2
ClK
13
vee
OSC
20
CHO
ClK
17
CH3
01
CH1
01
16
CH4
DO
COM
DO
15
CH5
INT
AGNO
INT
14
CH6
EOC
VREF
EOC
13
CH7
12
COM
OGNO
TL/H/ll021-1
VREF
Top View
oo
CHO
Q)
U1
Q)
AGNO
10
TLlH/ll021-2
Top View
ADC0858 PLCC Package
ADC0851 PLCC Package
1:2
~
0
u
>u
CI
Z
g
~
1:2
::::E
0
u
u
VI
0
<..>
u
>
a
I
u
-
I
u
CH 2
ClK
ClK
18
COMPL
NC
17
NC
01
16
CH 0
DO
15
CH 1
INT
14
NC
9
01
17
CH 3
DO
16
CH 4
iNT
15
CH 5
CH 6
EOC
12
10 11 12 13
CI
u
z
u
8
...
CI
..... z
>'" -«
t:l
z
::::E
t:l
CI
0
U
...
CI
..... z
>'" -«
t:l
::::E
r-.
0
U
I
U
TLlH/ll021-4
TL/H/ll021-3
Top View
Top View
Ordering Information
Industrial
(-40°C ~ TA ~ +85°C)
Package
(-55°C
Military
TA ~ + 125°C)
~
Package
ADC0851 BIN,
ADC0851CIN
N16E,16-Pin
Plastic DIP
ADC0851CMJ/883
J16A,16-Pin
Ceramic DIP
ADC0858BIN,
ADC0858CIN
N20A, 20-Pin
Plastic DIP
ADC0858CMJ/883
J20A, 20-Pin
Ceramic DIP
ADC0851 BIV,
ADC0851CIV
V20A, 20-Lead
PLCC
ADC0858BIV,
ADC0858CIV
V20A, 20-Lead
PLCC
7-55
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•
Section 8
SCAN CMOS Test Access
Logic Datasheets
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Section 8 Contents
SCAN18245T Non-Inverting Transceiver with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . .
SCAN 18373T Transparent Latch with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCAN18374T D Flip-Flop with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCAN18540T Inverting Line Driver with TRI-STATE Outputs.............................
SCAN18541T Non-Inverting Line Driver with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . .
8·2
8-3
8-17
8-29
8-41
8-52
IfINational Semiconductor
SCAN18245T
Non-Inverting Transceiver with TRI-STATE® Outputs
General Description
Features
The SCAN18245T is a high speed, low-power bidirectional
line driver featuring separate data inputs organized into dual
9-bit bytes with byte-oriented output enable and direction
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture
with the incorporation of the defined boundary-scan test
logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
•
•
•
•
•
a
•
iii
•
•
II
IEEE 1149.1 (JTAG) Compliant
Dual output enable control signals
TRI-STATE outputs for bus-oriented applications
9-bit data busses for parity applications
Reduced-swing outputs source 32 mA/sink 64 mA
(Comm), source 24 mA/sink 48 mA (Mil)
Guaranteed to drive 50n transmission line to TIL input
levels of 0.8V and 2.0V
TTL compatible inputs
25 mil pitch SSOP (Shrink Small Outline Package)
Includes CLAMP and HIGHZ instructions
Member of National's SCANTM Products
Available as Known Good Die
Ordering Code: See Section 11
Connection Diagram
Tt.IS- 1
810 -
2
\.J
56
~
TOI
55 ~ Ala
DIR1- 3
54 r- CiT
81, -
4
53r-Al1
81 2 GND -
5
52 ~ A 12
6
51
813 -
7
50 - A13
81. -
8
49 -
AI.
Vee
~
eND
Vee -
9
48 -
81s -
10
47 -Als
816 -
11
46 -
GND -
12
45 - eND
817 -
13
44
~
Pin Names
A1(0-8)
B1 (0-8)
A2(0-8)
B2(0-8)
G1, G2
DIR1, DIR2
A16
A17
81a- 14
43 r-Ala
820 -
15
42 ~ A20
821 -
16
41
~A21
GND -
17
40
~
eND
82 2 -
18
39 I- A22
823 -
19
38 I- A23
Vee -
20
37
82. -
21
36 I- A2.
I- Vee
82s -
22
35 I- A2s
GND -
23
34 I- eND
82 6 -
24
33 I- A26
82 7 -
25
32 I- A27
DIR2 -
26
311-G2
82a -
27
30 r- A2a
TOO -
28
29
Description
Side A 1 Inputs or TRI-STATE Outputs
Side B1 Inputs or TRI-STATE Outputs
Side A21nputs orTRI-STATE Outputs
Side B2 Inputs or TRI-STATE Outputs
Output Enable Pins
Direction of Data Flow Pins
Order Number
Description
SCAN 18245TSSC
SCAN 18245TSSCX
SCAN18245TFMQB
5962-9311501 MXA
SSOP in Tubes
SSOP in Tape and Reel
Flatpak Military
Military SMD#
I- TCK
TL/F/l0961-1
8-3
http://www.national.com
Functional Description
Truth Tables
Inputs
Al (0-8)
G1
DIR1
L
L
L
L
H
L
L
H
H
H
L
H
L
X
Z
Inputs
G2
DIR2
L
L
L
L
H
L
L
H
H
X
A2 (0-8)
H
L
H
L
Z
The SCAN18245 consists of two sets of nine non-inverting
bidirectional buffers with TR I-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and
DIR2) LOW enables data from B ports to A ports, when
HIGH enables data from A ports to B ports. The Output
Enable pins (G1 and G2) when HIGH disables both A and B
ports by placing them in a high impedance condition.
I Bl (0-8)
++~
~
H
L
H
L
Z
I B2 (0-8)
++~
~
H
L
H
L
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Block Diagrams
A1, 81, G1 and DlR1
TYPE1
TYPE1
TLlF/l0961-2
Note: BSR stands for Boundary Scan Register.
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8-4
Block Diagrams (Continued)
Tap Controller
TO BSR [79]
TOI
FROt.l BSR [0]
BYPASS
REGISTER
TOO
INSTRUCTION
REGISTER
TMS
INSTRUCTION
TRI-STATE
TCK
TUF/l0961-3
A2, 82, G2 and DIR2
TL/F/10961-4
Note: BSR stands for Boundary Scan Register.
•
8-5
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Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18245T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be
used as a "pseudo 10" code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Instruction Register Scan Chain Definition
TOI
Bypass Register Scan Chain Definition
Logic 0
TOO
lAse
Lse
TL/F/1 0961-1 0
MSB
Instruction Code
00000000
10000001
10000010
00000011
All Others
TLlF/10961-9
~
LSB
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
BYPASS
Scan Cell TYPE1
SCAN OUT
(to next cell)
DATA I N - - - - - . - - - - - - - - - - - - - - - + - - - - - DATA OUT
SHIFLOR ----+--t
SCAN IN
CLOCLOR
(from previous cell)
TLlF/10961-7
Scan Cell TYPE2
SCAN OUT
(to next cell)
1A0DE
------I
DATA I N - - - - r - - - - - - - - - - - - - - i - - - - - - - - - - - t
DATA OUT
SHIFLOR - - - + - - t
UPDATE-DR
SCAN IN
(from previous cell)
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TL/F/10961-B
8-6
Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register
Scan Chain Definition (80 Bits In Length)
TOI
TOO
IN
36
IN
IN
37
IN
IN
38
IN
IN
39
IN
IN
40
IN
41
IN
IN
42
IN
IN
43
IN
44
IN
45
IN
IN
46
IN
IN
47
IN
48
IN
12
IN
49
IN
13
IN
50
IN
51
IN
52
IN
53
10
11
[I
14
IN
15
16
IN
17
TLlF/l0961-25
8-7
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Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register Definition Index
Pin No.
Pin Type
3
54
76
75
74
73
72
DIR1
G1
AOE1
80E1
DIR2
G2
AOE2
80E2
Input
Input
Internal
Internal
Input
Input
Internal
Internal
TYPE1
TYPE1
TYPE2
TYPE2
TYPE1
TYPE1
TYPE2
TYPE2
Control
Signals
71
70
69
68
67
66
65
64
63
A10
A11
A12
A13
A14
A1s
A16
A17
A18
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A1-in
62
61
60
59
58
57
56
55
54
A20
A21
A22
A23
A24
A2s
A26
A27
A28
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A2-in
53
52
51
50
49
48
47
46
45
81 0
81 1
81 2
81 3
81 4
81 5
81 6
81 7
81 8
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
81-out
44
43
42
41
40
39
38
37
36
820
82 1
82 2
823
82 4
82 5
826
827
828
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
82-out
35
34
33
32
31
30
29
28
27
81 0
81 1
81 2
81 3
81 4
81 5
81 6
81 7
81 8
2
4
5
7
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
81-in
Bit No.
79
78
77
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Pin Name
26
31
8
10
11
13
14
8-8
Scan Cell Type
Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register Definition Index (Continued)
Bit No.
Pin Name
Pin No.
Pin Type
Scan Cell Type
26
25
24
23
22
21
20
19
18
82 0
82 1
82 2
823
82 4
82 5
82 6
82 7
82 8
15
16
18
19
21
22
24
25
27
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
82-in
17
16
15
14
13
12
11
10
9
A10
A11
A12
A13
A14
A15
A16
A17
A18
55
53
52
50
49
47
46
44
43
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A1-out
8
7
6
5
4
3
2
1
0
A20
A21
A22
A23
A24
A25
A26
A27
A28
42
41
39
38
36
35
33
32
30
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A2-out
8-9
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Absolute Maximum Ratings
(Note 1)
If MilitaryI Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Storage Temperature
DC Output Source/Sink Current (10)
-20mA
+20mA
Recommended Operating
Conditions
-20mA
+20mA
Supply Voltage (Vee)
SCAN Products
-0.5V to Vee +0.5V
±70mA
DC Vee or Ground Current
Per Output Pin
±70mA
Junction Temperature
SSOP
2000V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and outputlinput loading variables. National does not recommend operation of SCAN circuits outside databook specifications.
-0.5V to + 7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee +0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
- 65°C to + 150°C
ESD (Min)
4.5Vto 5.5V
Input Voltage (VI)
OVtoVee
Output Voltage (VO)
OVtoVee
Operating Temperature (TA)
Commercial
Military
+ 140°C
-40°C to +85°C
- 55°C to + 125°C
Minimum Input Edge Rate dV /dt
VIN from 0.8V to 2.0V
Vee @ 4.5V. 5.5V
125 mV/ns
DC Electrical Characteristics
Commercial
Symbol
Parameter
Vee
(V)
TA
=
+25°C
Typ
Military
TA
=
-55°C to + 125°C TA
Commercial
=
Conditions
-40°C to +85°C Units
Guaranteed Limits
VIH
Minimum High
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee -0.1V
VIL
Maximum Low
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee -0.1V
VOH
Minimum High
Output Voltage
4.5
5.5
3.15
4.15
3.15
4.15
3.15
4.15
V
4.5
5.5
2.4
2.4
2.4
2.4
V
4.5
5.5
2.4
2.4
2.4
2.4
4.5
5.5
0.1
0.1
0.1
0.1
4.5
5.5
0.55
0.55
4.5
5.5
0.55
0.55
0.55
0.55
5.5
±0.1
±1.0
VOL
liN
Maximum Low
Output Voltage
Maximum Input
Leakage Current
Maximum Input
liN
TDI. TMS Leakage
IOLD
10HD
5.5
Minimum Input
Leakage
5.5
tMinimum Dynamic
Output Current
5.5
0.1
0.1
V
0.55
0.55
V
V
±1.0
,..,A
= VIL or VIH
= -32mA
VIN = VIL or VIH
10H = -24mA
lOUT = 50,..,A
= VIL or VIH
= 64mA
VIN = VIL or VIH
10L = 48 mA
VI = Vee. GND
VIN
10L
2.8
3.7
3.6
,..,A
VI
-385
-385
,..,A
VI
-160
-160
-160
,..,A
VI
=
=
=
Vee
GND
GND
94
63
94
mA
VOLD
-40
-27
-40
mA
VOHD
8-10
-50,..,A
VIN
10H
-385
tMaximum test duration 2.0 ms, one output loaded at a time.
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V
=
lOUT
= 0.8V Max
= 2.0V Min
DC Electrical Characteristics (Continued)
Commercial
Symbol
Parameter
Vee
(V)
=
TA
Military
+25°C TA
=
Typ
Maximum I/O
Leakage Current
10ZT
Commercial
-55°C to + 125°C TA
=
-40°C to +85°C
Units
Conditions
p.A
VI (OE) = VIL, VIH
VI = Vcc, GND
Vo = Vcc, GND
Guaranteed Limits
5.5
±0.6
±11.0
±6.0
lOS
Output Short
Circuit Current
5.5
-100
-100
-100
Icc
Maximum Quiescent
Supply Current
5.5
16.0
168
88
p.A
Vo = High
TDI, TMS = Vcc
5.5
750
930
820
p.A
Vo = High
TDI, TMS = GND
Maximum Icc Per Input 5.5
2.0
2.0
2.0
rnA
VI
Icct
rnA (min) Vo
VI
5.5
2.15
2.15
2.15
=
=
=
OV
Vcc-2.1V
Vcc-2.1 V
TDI/TMS Pin, test
rnA
one with the
other floating
·AII outputs loaded; thresholds associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Noise Specifications
Commercial
Symbol
Vee
(V)
Parameter
TA
=
Military
TA
+25°C
Typ
=
Commercial
-55°C to + 125°C TA
=
-40°C to +85°C Units
Fig.
No.
Guaranteed Limits
VOLP
Maximum High
Output Noise (Notes 2, 3)
5.0
1.0
1.5
V
4-13
VOLV
Minimum Low
Output Noise (Notes 2, 3)
5.0
-0.6
-1.2
V
4-13
VOHP
Maximum
Overshoot (Notes 1, 3)
5.0
VOH+ 1.0 VOH+ 1.5
V
4-13
VOHV
Minimum Vcc
Droop (Notes 1, 3)
5.0
VOH-1.0 VOH-1.8
V
4-13
VIHD
Minimum High
Dynamic Input (Notes 1, 4)
Voltage Level
5.5
1.6
2.0
2.0
2.0
V
VILD
Maximum Low
Dynamic Input (Notes 1,4)
Voltage Level
5.5
1.4
0.8
0.8
0.8
V
Note 1: Worst case package.
Note 2: Maximum number of outputs that can switch simultaneously is n. (n-l) outputs are switched LOW and one output held LOW.
Note 3: Maximum number of outputs that can switch Simultaneously is n. (n-l) outputs are switched HIGH and one output held HIGH.
Note 4: Maximum number of data inputs (n) switching. (n-l) input switching OV to 3V. Input under test switching 3V to threshold (VILD)'
AC Electrical Characteristics
Normal Operation: See Section 4
Commercial
Symbol
Parameter
Vee*
(V)
TA = +25°C
CL = 50 pF
Min
tpLH.
tpHL
Propagation Delay
A toB, BtoA
tpLZ.
tpHZ
Disable Time
tPZL,
tPZH
Enable Time
Typ
Military
TA =
Commercial
-
55°C to + 125°C
CL = 50pF
TA = -40°C to +85·C
CL = 50pF
Units
Fig.
No.
Max
Min
Max
Min
Max
5.0
1.6
1.6
7.9
7.9
1.6
1.6
9.0
9.3
1.6
1.6
8.5
8.8
ns
4-1,2
5.0
1.2
1.2
8.6
8.5
1.2
1.2
10.0
9.5
1.2
1.2
9.5
9.0
ns
4-3,4
5.0
1.6
1.6
11.0
8.5
1.6
1.6
12.5
10.0
1.6
1.6
12.0
9.5
ns
4-3,4
·Voltage Range 5.0 is 5.0V ±0.5V.
8-11
http://www.national.com
AC Electrical Characteristics
Scan Test Operation: See Section 4
Commercial
Symbol
Parameter
Vee·
(V)
TA = +25°C
CL = 50 pF
Typ
Military
TA =
Commercial
55°C to + 125°C
CL = 50pF
-
TA =
40°C to + 85°C
CL = 50 pF
-
Units
Fig.
No.
Max
Min
Max
Min
Max
5.0
2.8
2.8
13.2
13.2
2.8
2.8
15.8
15.8
2.8
2.8
14.5
14.5
ns
4-8
Disable Time
TCKtoTDO
5.0
2.0
2.0
11.5
11.5
2.0
2.0
12.8
12.8
2.0
2.0
11.9
11.9
ns
4-9,10
tpZL,
tpZH
Enable Time
TCKto TDO
5.0
2.4
2.4
14.5
14.5
2.4
2.4
16.7
16.7
2.4
2.4
15.8
15.8
ns
4-9,10
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
4.0
4.0
18.0
18.0
4.0
4.0
21.7
21.7
4.0
4.0
19.8
19.8
ns
4-8
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Update-IR State
4.0
4.0
18.6
18.6
4.0
4.0
21.2
21.2
4.0
4.0
20.2
20.2
ns
4-8
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Test Logie
Reset State
5.0
4.4
4.4
19.9
19.9
4.4
4.4
23.0
23.0
4.4
4.4
21.5
21.5
ns
4-8
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
3.2
3.2
16.4
16.4
3.2
3.2
19.6
19.6
3.2
3.2
18.2
18.2
ns
4-9,10
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Update-IR State
5.0
2.8
2.8
18.0
18.0
2.8
2.8
20.9
20.9
2.8
2.8
19.3
19.3
ns
4-9,10
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
2.8
2.8
18.4
18.4
2.8
2.8
21.8
21.8
2.8
2.8
20.0
20.0
ns
4-9,10
tpZL,
tpZH
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
4.0
4.0
18.9
18.9
4.0
4.0
22.6
22.6
4.0
4.0
20.9
20.9
ns
4-9,10
tpZL'
tPZH
Propagation Delay
TCK to Data Out
During Update-IR State
5.0
3.2
3.2
19.9
19.9
3.2
3.2
23.7
23.7
3.2
3.2
21.7
21.7
ns
4-9,10
tpZL,
tPZH
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
3.6
3.6
21.3
21.3
3.6
3.6
24.9
24.9
3.6
3.6
23.3
23.3
ns
4-9,10
Min
tpLH,
tpHL
Propagation Delay
TCKtoTDO
tpLZ,
tpHZ
5.0
'Voltage Range 5.0 is 5.0V ±0.5V.
All Propagation Delays involving TCK are measured from the falling edge of TCK.
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8-12
AC Operating Requirements Scan Test Operation:
Commercial
Symbol
Vcc·
(V)
Parameter
See Section 4
Military
Commercial
Fig.
TA = -55°C to + 125°C TA = -40°C to +85°C
Units
No.
CL = 50pF
CL = 50pF
TA = +25°C
CL = 50pF
Guaranteed Minimum
ts
Setup Time, H or L
Data to TCK (Note 1)
5.0
0.0
0.0
0.0
ns
4-11
tH
Hold Time, H or L
TCK to Data (Note 1)
5.0
6.5
7.5
6.5
ns
4-11
ts
Setup Time, H or L
G 1, G2 to TCK (Note 2)
5.0
0.0
0.0
0.0
ns
4-11
tH
Hold Time, H or L
TCK to G1, G2 (Note 2)
5.0
4.0
4.0
4.0
ns
4-11
ts
Setup Time, H or L
DIR1, DIR2 to TCK (Note 4)
5.0
0.0
0.0
0.0
ns
4-11
tH
Hold Time, H or L
TCK to DIR1, DIR2 (Note 4)
5.0
4.0
4.0
4.0
ns
4-11
ts
Setup Time, H or L
Internal AOE n , BOEn to TCK
(Note 3)
5.0
1.0
1.0
1.0
ns
4-11
5.0
4.0
5.0
4.0
ns
4-11
tH
Hold Time, H or L
TCK to Internal AOE n , BOEn
(Note 3)
ts
Setup Time, H or L
TMStoTCK
5.0
7.0
7.0
7.0
ns
4-11
tH
Hold Time, H or L
TCKto TMS
5.0
2.0
2.0
2.0
ns
4-11
ts
Setup Time, H or L
TDI toTCK
5.0
1.0
1.0
1.0
ns
4-11
tH
Hold Time, H or L
TCKto TDI
5.0
3.5
4.5
3.5
ns
4-11
tw
Pulse Width
15.0
5.0
15.0
5.0
15.0
5.0
ns
4-12
5.0
H
L
fmax
MaximumTCK
Clock Frequency
5.0
25
25
25
MHz
Tpu
Wait Time,
Power Up to TCK
5.0
100
100
100
ns
TON
Power Down
Delay
0.0
100
100
100
ms
'Voltage Range 5.0 is 5.0V ±0.5V.
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: Timing pertains to the TYPEl BSR and TYPE2 BSR after the buffer (BSR 0-8,9-17,18-26,27-35,36-44,45-53,54-62,63-71).
Note 2: Timing pertains to BSR 74 and 78 only.
Note 3: Timing pertains to BSR 72, 73, 76 and 77 only.
Note 4: Timing pertains to BSR 75 and 79 only.
8-13
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IU)
~
N
co
,...
Extended AC Electrical Characteristics
Symbol
Parameter
TA = Comm
Vee = Comm
CL = 50pF
18 Outputs
Switching
(Note 2)
TA = Comm
Vee = Comm
CL = 250pF
(Note 3)
TA = Mil
Vee = Mil
CL = 250 pF
(Note 3)
Units
Max
Min
Max
Min
Max
Min
Max
tpLH,
tpHL
Propagation Delay
Data to Output
2.5
2.5
10.5
10.5
2.5
2.5
11.0
11.0
3.5
3.5
12.0
13.5
3.5
3.5
13.0
14.5
tpZH,
tPZL
Output Enable Time
2.5
2.5
10.5
13.5
2.5
2.5
11.0
14.0
(Note 4)
(Note 4)
ns
tpHZ,
tpLZ
Output Disable Time
2.0
2.0
9.5
10.0
2.0
2.0
10.0
10.5
(Note 5)
(Note 5)
ns
tOSHL
(Note 1)
Pin to Pin Skew
HL Data to Output
0.5
1.0
1.0
ns
tOSLH
(Note 1)
Pin to Pin Skew
LH data to Output
0.5
1.0
1.0
ns
Min
Typ
TA = Mil
Vee = Mil
CL = 50pF
18 Outputs
Switching
(Note 2)
ns
Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (toSHU, LOW to HIGH (toSLH), or any combination switching LOW to HIGH and/or HIGH to LOW.
Note 2: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high, highto-low, etc.)
Note 3: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load. This specification pertains to single output switching only.
Note 4: TRI-STATE delays are load dominated and have been excluded from the datasheet.
Note 5: The Output Disable Time is dominated by the RC network (SOOn, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
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Parameter
Typ
Units
4
pF
Vee
=
5.0V
Input/Output Capacitance
20
pF
Vee
=
5.0V
Power Dissipation
Capacitance
41
pF
Vee
=
5.0V
CIN
Input Pin Capacitance
CliO
CPO
8·14
Conditions
Pad Diagram
56
55
54
53
52
51
50
49
48
10
47
11
46
12
45
13
43
,"",-,---42
15 ---'-1"'1
16
41
17
40
18
39
19
38
20
37
21
36
22
23 24
25
26
27
26
29 NC 30
8-15
31
32
33 34 35
TL/F/l0961-24
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In
~
....co
SCAN18245T Die Information
Z
Die Revision
DlelD
Die Size (X)
Die Size (Y)
Die Thickness
Substrate Bias
Backside Coating
Y8J245
4310 p'm
4310 p'm
14 mil
Vee (optional)
None
Pad Locations
Signal
Number
Signal
Name
1
TMS
2
3
Pad
Location·
Signal
Number
Signal
Name
Pad
Location·
-8.58,77.81
29
TCK
5.54, -77.81
81 0
-19.94,77.81
30
A28
19.94, -77.81
DIR1
-30.50,77.81
31
G2
30.50, -77.81
4
81 1
-40.98,77.81
32
A27
40.98, -77.81
5
81 2
-53.59,77.81
33
A26
53.59, -77.81
6
GNO
-63.73,77.81
34
GNO
63.73, -77.81
7
81 3
-74.47, 77.81
35
A25
74.47, -77.81
8
81 4
-79.73, 62.30
36
A24
79.73, -62.27
9
Vee
-79.73,51.55
37
Vee
79.73, -51.50
-79.73,46.28
79.73, -46.23
10
81 5
-79.73,36.05
38
A23
79.73, -36.02
11
81 6
-79.73,27.48
39
A22
79.73, -27.40
12
GND
-79.72,19.46
40
GNO
79.73, -19.43
13
81 7
-79.73,10.09
41
A21
79.73, -10.06
14
81 8
-79.73,3.46
42
A20
79.73, -3.43
15
820
-79.73, -3.43
43
A18
79.73,3.46
16
821
-79.73, -10.06
44
A17
79.73, 10.09
17
GNO
- 79.72, -19.43
45
GND
79.72,19.46
18
822
-79.73, -27.45
46
A16
79.73,27.43
19
823
-79.73, -36.02
47
A15
79.73,36.05
20
Vee
-79.73, -46.24
48
Vee
79.73, 46.26
-79.73, -51.52
79.73,51.54
21
824
-79.73, -62.27
49
A14
22
825
-74.47, -77.81
50
A13
74.47,77.81
23
GNO
-63.73, -77.81
51
GND
63.73,77.81
24
826
-53.59, -77.81
52
A12
53.59,77.81
79.73,62.30
25
827
-40.98, -77.81
53
A11
40.98,77.81
26
DIR2
-30.50, -77.81
54
G1
30.50, 77.81
27
828
-19.94, -77.81
55
A10
19.94,77.81
28
TOO
-8.58, -77.81
56
TOI
5.54,77.81
·X, Y coordinates measured in mils from center of die.
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8-16
~-------------------------------------------------------------------------------------,
IfI
..
(X)
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~
w
-I
National Semiconductor
SCAN18373T
Transparent Latch with TRI-STATE® Outputs
General Description
Features
The SCAN18373T is a high speed, low-power transparent
latch featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented latch enable and output enable
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture
with the incorporation of the defined boundary-scan test
logic and test access port consisting of Test Data Input
(TOI), Test Data Out (TOO), Test Mode Select (TMS), and
Test Clock (TCK).
•
•
•
•
II
•
III
III
•
a
IEEE 1149.1 (JTAG) Compliant
Buffered active-low latch enable
TRI-STATE outputs for bus-oriented applications
9-bit data busses for parity applications
Reduced-swing outputs source 32 mA/sink 64 mA
(Comm), source 24 mA/sink 48 mA (Mil)
Guaranteed to drive 50.0. transmission line to TTL input
levels of 0.8V and 2.0V
TTL compatible inputs
25 mil pitch SSOP (Shrink Small Outline Package)
Includes CLAMP and HIGHZ instructions
Member of National's SCAN Products
Ordering Code: See Section 11
Connection Diagram
Tt.lS- 1
AOo- 2
"-'
56 I-TOI
55 I-A1o
AO£,- 3
54 I-ALE
A01A02 -
4
531-Al1
5
52 I-AI2
GNO- 6
51 I-GNO
A03 - 7
AO.- 8
50 I-AI3
Vcc A05 -
9
48 I-Vcc
10
47 I-AI5
A06 -
11
46 I-AI6
GNO- 12
49 I-AI.
45 I-GNO
AO-,- 13
44 I-AI7
AOa- 14
.3 I-A1a
15
42 I-B1o
BO o -
B01- 16
GNO- 17
Description
Data Inputs
Latch Enable Inputs
TRI-STATE Output Enable Inputs
TRI-STATE Latch Outputs
Order Number
Description
SCAN18373TSSC
SCAN 18373TSSCX
SCAN 18373TFMQB
5962-9311801MXA
SSOP in Tubes
SSOP in Tape and Reel
Flatpak Military
MilitarySMO #
41 t-Bll
40 I-GNO
B02 -
18
39 I-BI2
B03 -
19
38 I-BI3
Vcc - 20
BO.- 21
37 I-Vcc
B05 - 22
GNO- 23
35 t-B15
24
33 I-BI6
BO-,- 25
32 I-BI7
B06 -
Pin Names
AI(0-8), BI(0-8)
ALE,BLE
AOE1, BOE1
AO(0-8), BO(0-8)
36 t-BI.
341-GNO
BO£,- 26
311-BLE
BOa - 27
TOO- 28
30 I-B1a
291-TCK
TLlF/l0962-1
8-17
http://www.national.com
Truth Table
Functional Description
Inputs
AO (0-8)
ALE
AOE1
AI (0-8)
X
H
L
L
L
X
Z
H
H
L
L
H
L
H
AOo
BlE
BOE1
BI (0-8)
X
H
L
L
L
X
Z
L
H
L
H
BOo
X
Inputs
H
H
L
The SCAN18373T consists of two sets of nine D-type latches with TRI-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs (AI(0-8)
or BI(0-8) enters the latches. In this condition the latches
are transparent, i.e., a latch output will change state each
time its input changes. When Latch Enable is LOW, the
latches store the information that was present on the inputs
a set-up time preceding the HIGH-to-LOW transition of the
Latch Enable. The TRI-STATE standard outputs are controlled by the Output Enable (AOE1 or BOE1) input. When
Output Enable is LOW, the standard outputs are in the 2state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not
interfere with entering new data into the latches.
BO(0-8)
X
=
=
=
Z =
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
AOo = Previous AO before H-to-L transition of ALE
BOo = Previous BO before H-to-L transition of BLE
Logic Diagram
ALE or
BLE
AOEt or
BOEt
ADO or BOO
AOt or BOt
A02 or B02
A03 or B03
AD, or B04
A05 or B05
A06 or B06
Ao., or Bo.,
ADa or BOa
TLIF/10962-13
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
http://www.national.com
8-18
Block Diagrams
Byte-A
TYPE2
TYPEl
ALE
AI [0-8]
TL/F/l0962-2
Tap Controller
TO BSR [41]
FROM BSR [0]
BYPASS
REGISTER
TOI
TOO
INSTRUCTION
REGISTER
INSTRUCTION TRI-STA TE
TMS
TEST
ACCESS
PORT
(TAP)
TCK
TLlF/l0962-3
Byte-B
TYPEl
TYPE2
BI [0-8]
BO [0-8]
TYPEl
INSTRUCTION TRI-STATE
BlE
BOE1
TLlF/l0962-4
Note: BSR stands for Boundary Scan Register.
8-19
http://www.national.com
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN 18373T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be
used as a "pseudo ID" code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Instruction Register Scan Chain Definition
TOI
Bypass Register Scan Chain Definition
Logic 0
TOO
IotSB
LSB
TLlF/10962-10
MSB --+ LSB
Instruction Code
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGHZ
All Others
BYPASS
TL/F/10962-9
Scan Cell TYPE1
SCAN OUT
(to next cell)
DATA IN
SHIFT _OR
-----r--------------t-----
DATA OUT
----+---1
SCAN IN
CLOCK-OR
(from previous cell)
TL/F/10962-7
Scan Cell TYPE2
SCAN OUT
(to next cell)
IotOOE
-------I
--------------+----------I
DATA I N - -......
SHIFLDR
DATA OUT
---+---t
SCAN IN
(from previous cell)
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TL/F/10962-B
8-20
Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register
Scan Chain Definition (42 Bits In Length)
TOI
41
40
39
38
37
TOO
36
35
18
17
34
19
16
33
20
15
32
21
14
31
22
13
30
23
12
29
24
11
28
25
10
27
26
TLlF/10962-25
8-21
http://www.national.com
Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register Definition Index
Bit No.
Pin Name
Pin No.
Pin Type
3
54
Input
Input
Internal
Input
Input
Internal
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
Control
Signals
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A-in
Blo
BI1
BI2
BI3
BI4
Bis
Bis
BI7
Bla
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B-in
17
16
15
14
13
12
11
10
9
AOo
A01
A02
A03
A04
AOs
AOs
A07
AOa
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A-out
8
7
6
5
4
3
2
1
0
BOo
B01
B02
B03
B04
BOs
BOs
B07
BOa
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B-out
41
40
39
38
37
36
AOE1
ACP
AOE
BOE1
BCP
BOE
35
34
33
32
31
30
29
28
27
Ala
AI1
AI2
AI3
AI4
Ais
Ais
AI7
Ala
26
25
24
23
22
21
20
19
18
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26
31
8·22
Scan Cell Type
......
Absolute Maximum Ratings
CO
W
(Note 1)
Storage Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
DC Output Source/Sink Current (10)
-20mA
+20mA
Recommended Operating
Conditions
-20mA
+20mA
Supply Voltage (Vee)
SCAN Products
-0.5V to Vee + 0.5V
±70mA
±70mA
Junction Temperature
SSOP
2000V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of SCANTM circuits outside databook specifications.
-0.5V to + 7.0V
DC'Vee or Ground Current
Per Output Pin
- 65°C to + 150°C
ESD (Min)
4.5Vto 5.5V
Input Voltage (VI)
OV to Vee
Output Voltage (Vo)
OV to Vee
Operating Temperature (TA)
Commercial
Military
+ 140°C
- 40°C to + 85°C
- 55°C to + 125°C
Minimum Input Edge Rate dV/dt
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
DC Electrical Characteristics
Symbol
Parameter
Vee
(V)
Commercial
Military
Commercial
TA =
+ 25°C
TA =
- 55°C to + 125°C
TA =
- 40°C to + 85°C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High
Output Voltage
4.5
5.5
3.15
4.15
3.15
4.15
3.15
4.15
V
VIN
=
4.5
5.5
2.4
2.4
2.4
2.4
V
10H
= -32mA
4.5
5.5
2.4
2.4
2.4
2.4
V
VIN
10H
=
=
4.5
5.5
0.1
0.1
0.1
0.1
4.5
5.5
0.55
0.55
4.5
5.5
0.55
0.55
0.55
0.55
±0.1
± 1.0
VOL
Maximum Low
Output Voltage
liN
Maximum Input
Leakage Current
5.5
liN
Maximum Input Leakage
5.5
TDI, TMS
Minimum Input Leakage
10LD
10HD
tMinimum Dynamic
Output Current
5.5
5.5
lOUT
= -50 p,A
VIL or VIH
VIL or VIH
-24mA
=
0.1
0.1
V
VIN
= VIL or VIH
0.55
0.55
V
10L
=
64mA
V
VIN
10L
=
=
VIL or VIH
48 mA
±1.0
p,A
lOUT
50 p,A
VI
= Vee,GND
2.8
3.7
3.6
p,A
VI
= Vee
-385
-385
-385
p,A
VI
= GND
-160
-160
-160
p,A
VI
= GND
94
63
94
mA
VOLD
=
0.8V Max
-40
-27
-40
mA
VOHD
=
2.0V Min
,
tMaximum test duration 2.0 ms, one output loaded at a time.
8-23
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.......
w
-I
DC Electrical Characteristics (Continued)
Commercial
Symbol
Vee
(V)
Parameter
TA
Military
Commercial
= +25·C TA = -55·Cto + 125·C TA = -40·Cto + 85·C Units
Typ
Conditions
Guaranteed Limits
loz
Maximum Output
Leakage Current
5.5
±0.5
±10.0
±5.0
los
Output Short Circuit
Current
5.5
-100
-100
-100
Icc
Maximum Quiescent
Supply Current
5.5
16.0
168
88
p,A
Vo = Open
TDI, TMS = Vee
5.5
750
930
820
p,A
Vo = Open
TDI, TMS = GND
Maximum Icc per Input 5.5
2.0
2.0
2.0
mA
VI
mA
VI = Vee - 2.1V
TDIITMS Pin,
Test One with the
Other Floating
ICCt
5.5
2.15
2.15
p,A
VI (DE)
mAMin Vo
2.15
= VIL, VIH
= OV
= Vee - 2.1V
•All outputs loaded; thresholds associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Noise Specifications:
See Section 4
Commercial
Symbol
Parameter
Vee
(V)
TA
= +25·C
Military
TA
Typ
VOLP
VOLV
VOHP
VOHV
VIHD
VILD
Commercial
= -55·C to + 125·C TA = -40·C to +85·C Units Fig. No.
Guaranteed Limits
Maximum High
Output Noise
(Notes 2,3)
5.0
1.0
1.5
V
4-13
Minimum Low
Output Noise
(Notes 2, 3)
5.0
-0.6
-1.2
V
4-13
Maximum
Overshoot
(Notes 1,3)
5.0
VOH + 1.0
VOH + 1.5
V
4-13
Minimum Vee
Droop
(Notes 1,3)
5.0
VOH - 1.0
VOH - 1.8
V
4-13
Minimum High
Dynamic Input
Voltage Level
(Notes 1,4)
5.5
1.6
2.0
2.0
2.0
V
Maximum Low
Dynamic Input
Voltage Level
(Notes 1,4)
5.5
1.4
0.8
0.8
0.8
V
Note 1: Worst
case package.
Maximum number of outputs that can switch simultaneously is n. (n -1) outputs are switched LOW and one output held LOW.
Note 3: Maximum number of outputs that can switch simultaneously is n. (n -1) outputs are switched HIGH and one output held HIGH.
Note 4: Maximum number of data inputs (n) switching. (n-1) input switching OV to 3V. Input under test switching 3V to threshold (VILO).
Note 2:
http://www.national.com
8-24
AC Electrical Characteristics
Symbol
Parameter
Vee·
(V)
Commercial
Military
Commercial
TA= +25·C
CL = 50pF
T A = - 55·C to + 125·C
CL = 50 pF
TA = -40·C to + 85·C
CL = 50 pF
Propagation
Delay, Dto
tpLH,
tpHL
Propagation
Delay, LE to
tpLZ,
tpHZ
Disable Time
tpZL,
tPZH
Enable Time
a
a
Units
Fig.
No.
Max
Min
Max
Min
Max
5.0
2.5
2.5
9.0
9.0
2.5
2.5
10.5
10.5
2.5
2.5
9.8
9.8
ns
4-1,2
5.0
2.5
2.5
10.0
10.5
2.5
2.5
11.0
12.0
2.5
2.5
10.5
11.3
ns
4-1,2
5.0
1.5
1.5
9.0
9.5
1.5
1.5
10.5
10.3
1.5
1.5
9.5
10.0
ns
4-3,4
5.0
2.0
2.0
10.9
9.0
2.0
2.0
12.8
10.6
2.0
2.0
11.9
9.7
ns
4-3,4
Units
Fig.
No.
Min
tpLH,
tpHL
Normal Operation: See Section 4
Typ
'Voltage Range 5.0 is S.OV ±O.SV.
AC Operating Requirements NormalOperation:
Symbol
Parameter
Vee·
(V)
See Section 4
Commercial
Military
Commercial
TA = +25·C
CL = 50pF
TA = -55·Cto + 125·C
CL = 50 pF
TA = -40·C to + 85·C
CL = 50 pF
Guaranteed Minimum
ts
Setup Time, H or L
Data to LE
5.0
3.0
3.0
3.0
ns
4-5
tH
Hold Time, H or L
LEto Data
5.0
1.5
1.5
1.5
ns
4-5
tw
LE Pulse Width
5.0
5.0
5.0
5.0
ns
4-2
'Voltage Range 5.0 is 5.0V ±O.SV.
8-25
http://www.national.com
AC Electrical Characteristics
Symbol
Parameter
Vee·
(V)
Scan Test Operation: See Section 4
Commercial
Military
Commercial
TA= + 25°C
CL = 50pF
TA = -55°C to + 125°C
CL = 50 pF
TA= -40°C to + 85°C
CL = 50 pF
Units
Fig.
No.
Min Typ Max
Min
Max
Min
Max
5.0
3.5
3.5
13.2
13.2
3.5
3.5
15.8
15.8
3.5
3.5
14.5
14.5
ns
4-8
Disable Time
TCKto TDO
5.0
2.5
2.5
11.5
11.5
2.5
2.5
12.8
12.8
2.5
2.5
11.9
11.9
ns
4-9.10
tPZL.
tpZH
Enable Time
TCKtoTDO
5.0
3.0
3.0
14.5
14.5
3.0
3.0
16.7
16.7
3.0
3.0
15.8
15.8
ns
4-9.10
tpLH.
tpHL
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
ns
4-8
tpLH.
tpHL
Propagation Delay
TCK to Data Out
during Update-IR State
5.0
ns
4-8
tpLH.
tpHL
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
5.0
ns
4-8
tpLZ.
tpHZ
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
ns
4-9.10
tpLZ.
tpHZ
Propagation Delay
TCK to Data Out
during Update-IR State
5.0
ns
4-9.10
tpLZ.
tpHZ
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
5.0
ns
4-9.10
tPZL.
tpZH
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
ns
4-9.10
tPZL.
tpZH
Propagation Delay
TCK to Data Out
during Update-IR State
5.0
ns
4-9.10
tpZL.
tPZH
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
ns
4-9.10
tpLH.
tpHL
Propagation Delay
TCKto TDO
tpLZ.
tpHZ
5.0
5.0
18.0
5.0
21.7
5.0
19.8
5.0
18.0
5.0
21.7
5.0
19.8
5.0
18.6
5.0
21.2
5.0
20.2
5.0
18.6
5.0
21.2
5.0
20.2
5.5
19.9
5.5
23.0
5.5
21.5
5.5
19.9
5.5
23.0
5.5
21.5
4.0
16.4
4.0
19.6
4.0
18.2
4.0
16.4
4.0
19.6
4.0
18.2
5.0
19.5
5.0
22.4
5.0
20.8
5.0
19.5
5.0
22.4
5.0
20.8
5.0
19.9
5.0
23.3
5.0
21.5
5.0
19.9
5.0
23.3
5.0
21.5
5.0
18.9
5.0
22.6
5.0
20.9
5.0
18.9
5.0
22.6
5.0
20.9
6.5
22.4
6.5
26.2
6.5
24.2
6.5
22.4
6.5
26.2
6.5
24.2
7.0
23.8
7.0
27.4
7.0
25.7
7.0
23.8
7.0
27.4
7.0
25.7
'Voltage Range 5.0 is 5.0V ±0.5V.
All propagation delays Involving TCK are measured from the falling edge of TCK.
http://www.national.com
8-26
AC Operating Requirements Scan Test Operation:
Commercial
Symbol
Vee·
(V)
Parameter
See Section 4
Military
Commercial
TA = +25°C TA = -5S·Cto + 125°C TA = -40°C to +85°C
CL = 50pF
CL = 50 pF
CL = SOpF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time,
Data to TCK (Note 2)
5.0
3.0
3.0
3.0
ns
4-11
tH
Hold Time,
TCK to Data (Note 2)
5.0
4.5
4.5
4.5
ns
4-11
ts
Setup Time, H or L
AOE1, BOEl to TCK (Note 4)
5.0
3.0
3.0
3.0
ns
4-11
tH
Hold Time, H or L
TCK to AOE1, BOEl (Note 4)
5.0
4.5
5.0
4.5
ns
4-11
ts
Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 3)
5.0
3.0
3.0
3.0
ns
4-11
Hold Time, H or L
TCK to Internal
AOE, BOE (Note 3)
5.0
3.0
3.0
3.0
ns
4-11
ts
Setup Time
ALE, BLE (Note 1) to TCK
5.0
3.0
3.0
3.0
ns
4-11
tH
Hold Time
TCK to ALE, BLE (Note 1)
5.0
3.5
4.0
3.5
ns
4-11
ts
Setup Time, H or L
TMSto TCK
5.0
8.0
8.0
8.0
ns
4-11
tH
Hold Time, H or L
TCKtoTMS
5.0
2.0
2.0
2.0
ns
4-11
ts
Setup Time, H or L
TDI toTCK
5.0
4.0
4.0
4.0
ns
4-11
tH
Hold Time, H or L
TCKtoTDI
5.0
4.5
4.5
4.5
ns
4-11
tw
Pulse Width TCK
15.0
5.0
15.0
5.0
15.0
5.0
ns
4-12
25
25
25
MHz
tH
5.0
H
L
f max
MaximumTCK
Clock Frequency
Tpu
Wait Time, Power Up to TCK
5.0
100
100
100
ns
Tdn
Power Down Delay
0.0
100
100
100
ms
5.0
·Voltage Range 5.0 is 5.0V ± 0.5V.
All Input Timing Delays Involving TCK are measured from the rising edge of TCK.
Note 1: Timing pertains to BSR 37 and 40 only.
Note 2: This delay represents the timing relationship between the data Input and TCK at the associated scan cells numbered 0·8,9·17,18·26 and 27·35.
Note 3: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 4: Timing pertains to BSR 38 and 41 only.
8-27
http://www.national.com
ICf)
.....
Cf)
co
,....
Extended AC Electrical Characteristics:
TA = Com
Vee
Symbol
Parameter
tpLH
Propagation Delay
tpHL
Latch Enable
4
TA = Mil
Vee
= Com
TA = Com
= Mil
TA= Mil
CL = 50pF
CL = 50pF
Vee
18 Outputs
18 Outputs
CL = 250pF
CL = 250 pF
Switching
Switching
(Note 3)
(Note 3)
(Note 2)
Min
See Section
Typ
= Com
Vee
= Mil
Units
(Note 2)
Max
Min
Max
Min
Max
Min
Max
3.0
3.0
12.0
12.8
3.0
3.0
12.5
13.5
4.0
4.0
13.5
16.0
4.0
4.0
14.5
16.5
3.0
3.0
11.5
11.5
3.0
3.0
12.0
12.0
4.0
4.0
13.0
14.5
4.0
4.0
14.0
15.5
ns
to Output
tpLH
Propagation Delay
tpHL
Data to Output
tPZH
Output Enable Time
2.5
2.5
10.5
12.5
2.5
2.5
11.0
13.5
(Note 4)
(Note
4)
ns
Output Disable Time
2.0
2.0
10.5
10.5
2.0
2.0
11.0
11.0
(Note
5)
(Note
5)
ns
tpZL
tpHZ
tpLZ
tOSHL
(Note 1)
tOSLH
(Note 1)
Pin to Pin Skew
HL Data to Output
Pin to Pin Skew
LH Data to Output
ns
0.5
1.0
1.0
ns
0.5
1.0
1.0
ns
Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (toSHU. LOW to HIGH (toSLH). or any combination switching LOW to HIGH.
Note 2: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (Le .• alilow-to-high. highto-low. etc.).
Note 3: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load. This specification pertains to single output switching only.
Note 4: TRI-STATE delays are load dominated and have been excluded from the datasheet.
Note 5: The Output Disable Time Is dominated by the RC network (SOon. 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
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Parameter
Typ
Units
Conditions
4.0
pF
Vee = 5.0V
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
13.0
pF
Vee = 5.0V
CPO
Power Dissipation Capacitance
34.0
pF
Vee = 5.0V
8-28
r---------------------------------------------------------------------------------~
'"-I
t;{INational Semiconductor
0l:Io
SCAN18374T
D Flip-Flop with TRI-STATE® Outputs
General Description
Features
The SCAN18374T is a high speed, low-power D-type flipflop featuring separate D-type inputs organized into dual
9-bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and BOUNDARY-SCAN Architecture
with the incorporation of the defined BOUNDARY-SCAN
test logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS), and
Test Clock (TCK).
•
•
•
•
•
•
•
•
•
•
IEEE 1149.1 (JTAG) Compliant
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
9-bit data busses for parity applications
Reduced-swing outputs source 32 rnA/sink 64 rnA
(Comm), source 24 rnA/sink 48 rnA (Mil)
Guaranteed to drive 50n transmission line to TIL input
levels of 0.8V and 2.0V
TIL compatible inputs
25 mil pitch SSOP (Shrink Small Outline Package)
Includes CLAMP and HIGHZ instructions
Member of National's SCAN Products
Ordering Code: See Section 11
Connection Diagram
TtolS- 1
AOo- 2
A0E,- 3
\....../
56
54
53 r-AI,
A02 - 5
GND- 6
52 r-A1 2
A03 - 7
AO.- 8
50
vec - 9
AOs- 10
48 -Vee
51 r-GND
49 -AI.
AOs- 11
GND- 12
45 r-GNO
4<4 -A1 7
AOa- 14
43
~Ala
8°0- 15
Bo,- 16
42
~810
GNO- 17
40 t-GNO
8°2- 18
39 r-812
38 r-81 l
80l -
19
37 r-Vcc
8°5- 22
GNO- 23
35 -81 5
80s -
24
33 -81s
8~-
25
32 -81 7
80 a -
27
TOO- 28
Order Number
Description
SCAN18374TSSC
SCAN 18374TSSCX
SCAN 18374TFMQB
5962-9320701 MXA
SSOP in Tubes
SSOP in Tape and Reel
Flatpak Military
Military SMD #
41 -BI,
vec - 20
80.- 21
BOE,- 26
AO(O-B), BO(O-B)
Description
Data Inputs
Clock Pulse Inputs
TRI-STATE Output
Enable Inputs
TRI-STATE Outputs
~All
47 -Al s
46 -Als
13
AI(O-B), BI(O-B)
ACP, BCP
AOE1, BOE1
~ACP
Ao,- 4
A~-
Pin Names
~TDI
55 .... Alo
36 r-81.
3<4 -GNO
31 -8CP
30 t-81a
29 t-TCK
TL/F/l0963-1
8-29
-4
Q)
Ct.)
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Functional Description
Truth Tables
Inputs
AO(O-S)
ACP
AOE1
AI(O-S)
X
H
L
L
X
Z
....r
....r
L
H
L
H
BCP
BOE1
BI(0-8)
X
H
L
L
X
L
H
Inputs
....r
....r
The SCAN18374 consists of two sets of nine edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The buffered clock and buffered Output Enable
pins are common to all flip-flops. Each set of the nine flipflops will store the state of their individual D inputs that meet
the setup and hold time requirements on the LOW-to-HIGH
Clock (ACP or BCP) transition. With the Output Enable
(AOE1 or BOE1) LOW, the contents of the nine flip-flops are
available at the outputs. When the Output Enable is HIGH,
the outputs go to the high impedance state. Operation of
the Output Enable input does not affect the state of the flipflops.
BO(O-S)
Z
L
H
= HIGH Voltage Level
= LOW Voltage Level
= Immaterial
Z = High Impedance
J" = L·to·H Transition
H
L
X
Logic Diagram
ACP or
BCP
AOE, or
BOE,
TL/F/l0963-13
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
TYPE1
TYPE2
TYPE1
ACP
INSTRUCTION TRI-STATE
AO [o-a]
AI [o-a]
TL/F/l0963-2
Note: BSR stands for Boundary Scan Register
http://www.national.com
8-30
Block Diagrams
(Continued)
Tap Controller
FROM BSR[Oj
TO BSR[41j
BYPASS
REGISTER
TDI
TOO
INSTRUCTION
REGISTER
INSTRUCTION TRI-STATE
TMS
TEST
ACCESS
PORT
(TAP)
TCK
TLlF/l0963-3
Byte-B
BI [o-a]
BCP
BOE1
TL/F/l0963-4
Note: BSR stands for Boundary Scan Register
8-31
http://www.national.com
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
totheSCAN18374Tdevice. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be
used as a "pseudo 10" code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Instruction Register Scan Chain Definition
TOO
TOI
LSB
IoISB
Bypass Register Scan Chain Definition
LogiC 0
TL/F/10963-10
MSB ---+ LSB
Instruction Code
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
HIGHZ
00000011
All Others
BYPASS
TL/F/10963-9
Scan Cell TYPE1
SCAN OUT
(to nlxt cIII)
DATA IN
SHIH _DR
---"""T"--------------t------
DATA OUT
----+---1
SCAN IN
CLOCK-DR
(from previous cell)
TLlF/10963-7
Scan Cell TYPE2
SCAN OUT
(to next cell)
OATA I N - - . . . . . , . - - - - - - - - - - - - - - f - - - - - - - - - - - t
DATA OUT
SHIFLDR - - - + - - t
SCAN IN
CLOCK-DR
UPDATE-DR
(from previous cell)
http://www.national.com
TL/F/10963-8
8-32
.-------------------------------------------------------------------------------------------, CD
~
W
Description of Boundary-Scan Circuitry (Continued)
'"
-t
~
Boundary-Scan Register
Scan Chain Definition (42 Bits In Length)
TOI
41
40
39
38
37
TOO
36
35
18
17
34
19
16
33
20
15
32
21
14
31
22
13
30
23
12
29
24
11
28
25
10
27
26
TL/F/l0963-25
8-33
_ http://www.national.com
Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register Definition Index
Bit No.
Pin No.
Pin Type
3
54
Input
Input
Internal
Input
Input
Internal
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
Control
Signals
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A-in
Blo
BI1
BI2
Bla
BI4
Bis
BI6
BI7
Bla
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B-in
17
16
15
14
13
12
11
10
9
AOo
A01
A02
AOa
A04
AOs
A06
A07
AOa
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A-out
8
7
6
5
4
3
2
1
0
BOo
B01
B02
BOa
B04
BOs
B06
B07
BOa
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B-out
Pin Name
41
40
39
38
37
36
AOE1
ACP
AOE
BOE1
BCP
BOE
35
34
33
32
31
30
29
28
27
Alo
AI1
AI2
Ala
AI4
Ais
AI6
AI7
Ala
26
25
24
23
22
21
20
19
18
http://www.national.com
26
31
8-34
Scan Cell Type
Absolute Maximum Ratings
(Note 1)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of SCANTM circuits outside databook specifications.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee +0.5V
-20mA
+20mA
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
-20mA
+20mA
DC Output Voltage (VO)
DC Output Source/Sink Current (10)
Recommended Operating
Conditions
Supply Voltage (Vee)
SCAN Products
-0.5VtoVee +0.5V
±70mA
DC Vee or Ground Current
Per Output Pin
±70mA
Junction Temperature
SSOP
+140°C
Storage Temperature
OVtoVee
Output Voltage (Vo)
OV to Vee
Operating Temperature (TA)
Commercial
Military
- 40°C to + 85°C
- 55°C to + 125°C
Minimum Input Edge Rate dV /dt
VIN from O.BV to 2.0V
Vee @ 4.5V. 5.5V
- 65°C to + 150°C
ESD (Min)
4.5Vto 5.5V
Input Voltage (VI)
125 mV/ns
2000V
DC Electrical Characteristics
Commercial
Symbol
Parameter
Vee
(V)
TA
=
+25°C
Typ
Military
TA
=
-55°C to + 125°C TA
Commercial
=
-40°C to +85°C Units
Conditions
Guaranteed Limits
VIH
Minimum High
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee -0.1V
VIL
Maximum Low
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee -0.1V
VOH
Minimum High
Output Voltage
4.5
5.5
3.15
4.15
3.15
4.15
3.15
4.15
V
4.5
5.5
2.4
2.4
2.4
2.4
V
4.5
5.5
2.4
2.4
2.4
2.4
4.5
5.5
0.1
0.1
0.1
0.1
4.5
5.5
0.55
0.55
4.5
5.5
0.55
0.55
0.55
0.55
5.5
±0.1
±1.0
VOL
liN
Maximum Low
Output Voltage
Maximum Input
Leakage Current
Maximum Input
liN
TDI. TMS Leakage
Minimum Input
Leakage
10LO
10HO
5.5
5.5
tMinimum Dynamic
5.5
Output Current
V
0.1
0.1
V
0.55
0.55
V
V
±1.0
/-LA
lOUT
= VIL or VIH
= -32mA
VIN = VIL or VIH
10H = -24mA
lOUT = 50/-LA
= VIL or VIH
= 64 mA
VIN = VIL or VIH
IOL = 48mA
VI = Vee. GND
VIN
10L
2.8
3.7
3.6
/-LA
VI
-385
-385
/-LA
VI
-160
-160
/-LA
-50 J-LA
VIN
10H
-385
-160
=
VI
=
=
=
Vee
GND
GND
94
63
94
mA
YOLO
-40
-27
-40
mA
VOHO
= 0.8V Max
= 2.0V Min
tMaximum test duration 2.0 ms, one output loaded at a time.
8-35
http://www.national.com
DC Electrical Characteristics (Continued)
Symbol
Parameter
Commercial
Military
Commercial
Vee
TA = -55°C to + 125°C TA = -40°C to +85°C Units
(V) TA = +25°C
Typ
Guaranteed Limits
Conditions
102
Maximum Output
Leakage Current
5.5
±0.5
±10.0
±5.0
los
Output Short
Circuit Current
5.5
-100
-100
-100
Icc
Maximum Quiescent
5.5
Supply Current
16.0
168
88
itA
Vo = Open
TDI, TMS = Vcc
5.5
750
930
820
itA
Vo = Open
TDI, TMS = GND
5.5
2.0
2.0
2.0
mA VI = Vcc - 2.1V
5.5
2.15
2.15
2.15
ICCt
Maximum Icc
Per Input
itA
VI (OE) = VIL, VIH
mA Vo= OV
(min)
VI = Vec - 2.1V
TDI/TMS Pin, Test One
with the Other Floating
*AII outputs loaded; thresholds associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Noise Specifications:
Symbol
Parameter
Vee
(V)
See Section 4
Commercial
Military
Commercial
TA = +25°C
TA = -55°C to + 125°C
TA = -40°C to +85°C
Units
Fig.
No.
Guaranteed Limits
Typ
Maximum High
Output Noise
(Notes 2,3)
5.0
1.0
1.5
V
4·13
Minimum Low
Output Noise
(Notes 2,3)
5.0
-0.6
-1.2
V
4·13
Maximum
Overshoot
(Notes 1, 3)
5.0
VOH+ 1.0
VOH+1.5
V
4·13
MinimumVcC
Droop
(Notes 1, 3)
5.0
VOH-1.0
VOH-1.8
V
4·13
VIHD
Minimum High
Dynamic Input
Voltage Level
(Notes 1, 4)
5.5
1.6
2.0
2.0
2.0
V
VILD
Maximum Low
Dynamic Input
Voltage Level
(Notes 1, 4)
5.5
1.4
0.8
0.8
0.8
V
VOLP
VOLV
VOHP
VOHV
Note 1: Worst case package.
Note 2: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched LOW and one output held LOW.
Note 3: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched HIGH and one output held HIGH.
Note 4: Maximum number of data inputs (n) switching. (n - 1) input switching OV to 3V. Input under test switching 3V to threshold (VILO).
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8·36
AC Electrical Characteristics NormalOperation:
Commercial
Symbol
Parameter
TA = +25°C
CL = 50 pF
Vee·
(V)
Min
tpLH,
tpHL
Propagation Delay
CPtoQ
tpLZ,
tpHZ
Disable Time
tpZL'
tpZH
Enable Time
Typ
See Section 4
Military
TA
Commercial
= -55°C to + 125°C
CL = 50pF
TA
= -40°C to +85°C
CL = 50pF
Units
Fig.
No.
Max
Min
Max
Min
Max
5.0
2.5
2.5
9.5
10.3
2.5
2.5
11.0
12.0
2.5
2.5
10.5
11.5
ns
4-1,2
5.0
1.5
1.5
9.0
9.0
1.5
1.5
10.5
10.3
1.5
1.5
9.5
10.0
ns
4-3,4
5.0
2.0
2.0
10.9
8.9
2.0
2.0
12.6
10.3
2.0
2.0
12.0
9.5
ns
4-3,4
Units
Fig.
No.
·Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
Symbol
Parameter
Vee·
(V)
Normal Operation: See Section 4
Commercial
Military
TA = +25°C
CL = 50 pF
TA = -55°C to + 125°C
CL = 50pF
Commercial
TA
= -40°C to + 85°C
CL = 50 pF
Guaranteed Minimum
ts
Setup Time, H or L
Data toCP
5.0
3.0
3.0
3.0
ns
4-5
tH
Hold Time, H or L
CPto Data
5.0
1.5
1.5
1.5
ns
4-5
tw
CP Pulse Width
5.0
5.0
5.0
5.0
ns
4-12
f max
Maximum ACP/BCP
Clock Frequency
5.0
100
70
90
MHz
·Voltage Range 5.0 is 5.0V ± 0.5V.
8-37
http://www.national.com
AC Electrical Characteristics Scan Test Operation:
Commercial
Symbol
Parameter
Vee·
(V)
TA = +25·C
CL = 50 pF
See Section 4
Military
TA
=
Commercial
-55·Cto + 125·C
CL = 50pF
TA
=
-40·C to +85·C
CL = 50 pF
Units
Fig.
No.
Min Typ Max
Min
Max
Min
Max
5.0
3.5
3.5
13.2
13.2
3.5
3.5
15.8
15.8
3.5
3.5
14.5
14.5
ns
4-8
Disable Time
TCKtoTDO
5.0
2.5
2.5
11.5
11.5
2.5
2.5
12.8
12.8
2.5
2.5
11.9
11.9
ns
4-9,10
tpZL,
tpZH
Enable Time
TCKto TDO
5.0
3.0
3.0
14.5
14.5
3.0
3.0
16.7
16.7
3.0
3.0
15.8
15.8
ns
4-9,10
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
5.0
5.0
18.0
18.0
5.0
5.0
21.7
21.7
5.0
5.0
19.8
19.8
ns
4-8
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Update-IR State
5.0
5.0
5.0
18.6
18.6
5.0
5.0
21.2
21.2
5.0
5.0
20.2
20.2
ns
4-8
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
5.5
5.5
19.9
19.9
5.5
5.5
23.0
23.0
5.5
5.5
21.5
21.5
ns
4-8
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
4.0
4.0
16.4
16.4
4.0
4.0
19.6
19.6
4.0
4.0
18.2
18.2
ns
4-9,10
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Update-IR State
5.0 .
5.0
5.0
19.5
19.5
5.0
5.0
22.4
22.4
5.0
5.0
20.8
20.8
ns
4-9,10
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Test Logic
ResotState
5.0
5.0
5.0
19.9
19.9
5.0
5.0
23.3
23.3
5.0
5.0
21.5
21.5
ns
4-9,10
tpZL,
tpZH
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
5.0
5.0
18.9
18.9
5.0
5.0
22.6
22.6
5.0
5.0
20.9
20.9
ns
4-9,10
tpZL,
tpZH
Propagation Delay
TCK to Data Out
During Update-IR State
5.0
6.5
6.5
22.4
22.4
6.5
6.5
26.2
26.2
6.5
6.5
24.2
24.2
ns
4-9,10
tpzL,
tPZH
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
7.0
7.0
23.8
23.8
7.0
7.0
27.4
27.4
7.0
7.0
25.7
25.7
ns
4-9,10
tpLH,
tpHL
Propagation Delay
TCKto TDO
tpLZ,
tpHZ
·Voltage Range 5.0 is 5.0V ±0.5V.
All Propagation Delays involving TCK are measured from the falling edge of TCK.
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8-38
AC Operating Requirements Scan Test Operation:
Commercial
Symbol
Vcc'
(V)
Parameter
TA = +25°C
CL = 50pF
See Section 4
Military
Commercial
TA = -55°C to + 125°C TA = -40°C to +85°C
CL = 50 pF
CL = 50 pF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, H or L
Data to TCK (Note 1)
5.0
3.0
4.5
3.0
ns
4-11
tH
Hold Time, H or L
TCK to Data (Note 1)
5.0
4.5
5.5
4.5
ns
4-11
ts
Setup Time, H or L
AOE1, BOE1 to TCK (Note 3)
5.0
3.0
3.5
3.0
ns
4-11
tH
Hold Time, H or L
TCK to AOE1, BOE1 (Note 3)
5.0
4.5
4.5
4.5
ns
4-11
ts
Setup Time, H or L
Internal AOE, BOE
to TCK (Note 2)
5.0
3.0
3.0
3.0
ns
4-11
Hold Time, H or L
TCK to Internal AOE,
BOE (Note 2)
5.0
3.0
3.0
3.0
ns
4-11
ts
Setup Time
ACP, BCP (Note 4) to TCK
5.0
3.0
3.0
3.0
ns
4-11
tH
Hold Time
TCK to ACP, BCP (Note 4)
5.0
3.5
3.5
3.5
ns
4-11
ts
Setup Time, H or L
TMStoTCK
5.0
8.0
8.0
8.0
ns
4-11
tH
Hold Time, H or L
TCKto TMS
5.0
2.0
2.0
2.0
ns
4-11
ts
Setup Time, H or L
TDI toTCK
5.0
4.0
4.0
4.0
ns
4-11
tH
Hold Time, H or L
TCKtoTDI
5.0
4.5
4.5
4.5
ns
4-11
tw
Pulse Width TCK
15.0
5.0
15.0
5.0
15.0
5.0
ns
4-12
tH
5.0
H
L
fmax
MaximumTCK
Clock Frequency
5.0
25
25
25
MHz
Tpu
Wait Time, Power Up
toTCK
5.0
100
100
100
ns
Tdn
Power Down Delay
0.0
100
100
100
ms
'Voltage Range 5.0 is 5.0V ±0.5V.
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: This delay represents the timing relationship between the data Input and TCK at the associated scan cells numbered 0-6,9-17,16-26 and 27-35.
Note 2: This delay represents the timing relationship between AOE, BOE and TCK at scan cells 36 and 39 only.
Note 3: Timing pertains to BSR 36 and 41 only.
Note 4: Timing pertains to BSR 37 and 40 only.
8-39
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Extended AC Electrical Characteristics
TA = Mil
TA = Com
Vee
Symbol
Vee
= Com
CL = 50pF
= Mil
CL = 50pF
18 Outputs
Switching
Parameter
TA = Mil
TA = COM
Vee
18 Outputs
= Com
CL = 250 pF
Vee
= Mil
CL = 250 pF
Switching
(Note 3)
(Note 3)
(Note 2)
(Note 2)
Max
Min
Max
Min
Max
Min
Max
3.0
3.0
11.5
12.5
3.0
3.0
12.0
13.0
4.0
4.0
13.5
16.5
4.0
4.0
14.5
17.0
Min
Typ
Units
tpLH,
Propagation Delay
tpHL
Data to Output
tpZH,
Output Enable Time
2.5
2.5
10.5
12.5
2.5
2.5
11.0
13.5
(Note
4)
(Note
4)
ns
Output Disable Time
2.0
2.0
10.5
10.5
2.0
2.0
11.0
11.0
(Note
5)
(Note
5)
ns
tpZL
tpHZ,
tpLZ
tOSHL
(Note 1)
tOSLH
(Note 1)
Pin to Pin Skew
HL Data to Output
Pin to Pin Skew
LH Data to Output
ns
0.5
1.0
1.0
ns
0.5
1.0
1.0
ns
Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (toSHU, LOW to HIGH (toSLH), or any combination switching LOW to HIGH and/or HIGH to LOW.
Note 2: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., alilow-to-high, highto-low, etc.).
Note 3: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load. This specification pertains to single output switching only.
Note 4: TRI-STATE delays are load dominated and have been excluded from the datasheet.
Note 5: The Output Disable Time is dominated by the RC network (500n, 250 pF) on the output and has been excludod from the datasheet.
Capacitance
Symbol
CIN
COUT
CPO
Typ
Units
Input Pin Capacitance
4_0
pF
Vee
=
5.0V
Output Pin Capacitance
13.0
pF
Vee
=
5.0V
Vee
=
5.0V
Parameter
Power Dissipation
34.0
Capacitance
http://www.national.com
8-40
pF
Conditions
~---------------------------------------------------------------------------------.
-4
co
(J1
"'"
o
tflNational Semiconductor
-f
SCAN18540T
Inverting Line Driver with TRI-STATE® Outputs
General Description
Features
The SCAN18540T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TOO), Test Mode Select (TMS), and Test Clock
(TCK).
•
•
•
•
•
•
•
•
•
•
IEEE 1149.1 (JTAG) compliant
Dual output enable signals per byte
TRI-STATE outputs for bus-oriented applications
9-bit data busses for parity applications
Reduced-swing outputs source 32 mA/sink 64 mA
(Comm), source 24 mA/sink 48 mA (Mil)
Guaranteed to drive 50n transmission line to TIL input
levels of 0.8V and 2.0V
TIL compatible inputs
25 mil pitch SSOP (Shrink Small Outline Package)
Includes CLAMP and HIGHZ instructions
Member of National's SCAN products
Ordering Code: See Section 11
Connection Diagram
Description
Pin Names
TMS- 1
\J
56 I-TOI
Aoo -
2
55 I-Alo
AO~-
3
54 I-AOE2
53 I-All
Ao,-4
Ao2 - 5
GNO- 6
52 I-AI2
Ao3 Ao.-
50 I-AI3
Vee Aos -
Ao6 -
7
~Aoa 800 80;-
51 I-GNO
8
49 -AI.
9
48 -Vee
10
47 -Als
11
46 -A16
45 -GNO
GNO- 12
13
44 -A17
14
43 -Ala
15
42 -Bl o
16
40 -GNO
802 803 -
19
391-BI2
381- BI3
Vee -
20
80.8Os -
21
371-Vee
36 t-BI.
22
35 t-Bls
GND- 23
34 t-GNO
806 -
24
33 t-B16
32 t-B17
~-
25
BO~-
26
31 t-BOE2
8Oa -
27
30 t-Bla
TOO- 28
Truth Tables
Inputs
AO(0-8)
AOE1
AOE2
AI (0-8)
L
H
X
L
L
X
H
L
H
X
X
L
BOE1
BOE2
BI (0-8)
L
H
L
X
H
L
H
X
X
L
L
Z
Z
H
41 -B11
GNO- 17
18
Input pins, A side
AI(O-8)
Input pins, B side
~8)
AOElo AOE2 TRI-STATE Output Enable Input pins, A side
BOE1,BOE2 TRI-STATE Output Enable Input pins, B side
Output pins, A side
7\0(0-8)
Output pins, B side
00(0-8)
Inputs
X
L
H = HIGH Voltage Level
X = Immaterial
29 t-TCK
TLIF/10964-1
8-41
BO (0-8)
L
Z
Z
H
L = LOW Voltage Level
Z = High Impedance
Order Number
Description
SCAN18540TSSC
SCAN 18540TSSCX
SCAN 18540TFMOB
5962-9312701 MXA
SSOP in Tubes
SSOP in Tape and Reel
Flatpak Military
Military SMD #
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b
v
an
co
,..
Block Diagrams
Byte-A
TYPEl
INSTRUCTION TRI-STATE
AI [O-B]
TLlF/10964-2
Tap Controller
TO BSR [41]
FROM BSR [0]
BYPASS
REGISTER
TDI
TDO
INSTRUCTION
REGISTER
INSTRUCTION TRI-STATE
TMS
TCK
TEST
ACCESS
PORT
(TAP)
TLlF/10964-3
Byte-B
TL/F/10964-4
Note: BSR stands for Boundary Scan Register
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8·42
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
The INSTRUCTION register is an 8-bit register which captures the default value of 01001101. The two least significant bits of this captured value (01) are required by IEEE
Std 1149.1. The upper six bits are unique to the
SCAN18540T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification
register. Therefore, this unique captured value can be used
as a "pseudo 10" code to confirm that the correct device is
placed in the appropriate location in the boundary scan
chain.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
Instruction Register Scan Chain Definition
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
TOO
TDI
Bypass Register Scan Chain Definition
Logic 0
IofSB
LSB
TL/F/l0964-10
MSB~
LSB
Instruction Code
TLlF/l0964-9
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGH-Z
All Others
BYPASS
Scan Cell TYPE1
SCAN OUT
(to next coli)
DATA I N - - - " T " " - - - - - - - - - - - - - + - - - - DATA OUT
SHIFT-OR - - - i - - t
SCAN IN
(from provlou. c811)
TLlF/l0964-7
Scan Cell TYPE2
SCAN OUT
(to noxt coli)
IofODE------1
•
DATA IN--""T""-------------+--------~
DATA OUT
SHIFT-OR - - - i - - I
SCAN IN
UPDATE-DR
(from previous coli)
TLlF/l0964-6
8-43
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Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (42 Bits In Length)
TDI
41
40
39
38
37
TDO
36
35
18
17
34
19
16
33
20
15
32
21
14
31
22
13
30
23
12
29
24
11
28
25
10
27
26
TLlF/10964-23
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8·44
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index
Bit No.
Pin Name
Pin No.
Pin Type
3
54
Input
Input
Internal
Input
Input
Internal
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
Control
Signals
Scan Cell Type
41
40
39
38
37
36
AOE1
AOE2
AOE
BOE1
BOE2
BOE
35
34
33
32
31
30
29
28
27
Alo
AI1
AI2
AI3
AI4
Ais
AI6
AI7
Ala
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A-in
26
25
24
23
22
21
20
19
18
Blo
BI1
BI2
BI3
BI4
Bis
BI6
BI7
Bla
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B-in
17
16
15
14
13
12
11
10
9
AOo
A01
A02
A03
A04
AOs
A06
A07
AOa
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A-out
8
7
6
5
4
3
2
1
0
BOo
B01
B02
B03
B04
BOs
B06
B07
BOa
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B-in
26
31
8-45
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Storage Temperature
DC Output Source/Sink Current (10)
-20mA
+20mA
Recommended Operating
Conditions
-20mA
+20mA
Supply Voltage (Vee)
SCAN Products
- 0.5V to Vee + 0.5V
±70mA
DC Vee or Ground Current
Per Output Pin
±70mA
Junction Temperature
SSOP
2000V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of SCAN circuits outside databook specifications.
-0.5V to + 7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee +0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee +0.5V
DC Output Voltage (Vo)
- 65°C to + 150°C
ESD(Min)
4.5Vto 5.5V
Input Voltage (VI)
OVtoVee
Output Voltage (VO)
OVtoVee
Operating Temperature (TA)
Commercial
Military
+ 140°C
- 40°C to + 85°C
- 55°C to + 125°C
Minimum Input Edge Rate dV Idt
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mV/ns
DC Electrical Characteristics
Commercial
Symbol
Parameter
Vee
(V)
TA = +25°C
Typ
Military
Commercial
TA = -55°C to + 125°C TA = -40°C to + 85°C Units
Conditions
Guaranteed limits
VIH
Minimum High
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
or Vee -o.w
Vil
Maximum Low
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
or Vee -0.1V
VOH
Minimum High
Output Voltage
4.5
5.5
3.15
4.15
3.15
4.15
3.15
4.15
V
4.5
5.5
2.4
2.4
4.5
5.5
2.4
2.4
2.4
2.4
4.5
5.5
0.1
0.1
0.1
0.1
4.5
5.5
0.55
0.55
4.5
5.5
0.55
0.55
0.55
0.55
5.5
±0.1
±1.0
VOL
liN
Maximum Low
Output Voltage
Maximum Input
Leakage Current
Maximum Input
liN
TDI,TMS Leakage
10lD
10HD
5.5
Minimum Input
Leakage
5.5
tMinimum Dynamic
Output Current
5.5
2.4
2.4
V
0.1
0.1
V
0.55
0.55
V
VIN = Vil or VIH
10H = -32mA
VIN = Vil or VIH
10H = -24mA
lOUT = 50,..,A
VIN = Vil or VIH
10l = 64mA
VIN = Vil or VIH
IOL = 48 rnA
±1.0
,..,A
VI = Vee,GND
2.8
3.7
3.6
,..,A
VI = Vee
-385
-385
-385
,..,A
VI = GND
-160
-160
-160
,..,A
VI = GND
94
63
94
rnA
VOlD = 0.8V Max
-40
-27
-40
rnA
VOHD = 2.0V Min
tMaximum test duration 2.0 ms, one output loaded at a time.
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V
lOUT = -50,..,A
8-46
DC Electrical Characteristics (Continued)
Symbol
Military
Commercial
Commercial
Vee
TA = +2SoC TA = -SsoC to + 12SoC TA = -40°C to +8SoC Units
(V)
Typ
Guaranteed Limits
Parameter
Conditions
VI (OE) = VIL. VIH
loz
Maximum Output
Leakage Current
5.5
±0.5
±10.0
±5.0
los
Output Short
Circuit Current
5.5
-100
-100
-100
lee
Maximum Quiescent
Supply Current
5.5
16.0
168
88
JiA
Vo = Open
TDI, TMS = Vee
5.5
750
930
820
JiA
Vo = Open
TDI. TMS = GND
Maximum lee Per Input 5.5
2.0
2.0
2.0
rnA
VI
mA
VI = Vee- 2.1V
TDIITMS Pin, Test
One with the
other Floating
leet
2.15
5.5
JiA
mAMin Vo = OV
2.15
2.15
= Vee-2.1V
• All outputs loaded; thresholds associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Noise Specifications:
See Section 4
Commercial
Symbol
Parameter
Vee
(V)
TA
= +2Soc
Military
TA
Commercial
= -SsoC to + 12SoC TA = -40°C to +8SoC Units Fig. No.
Guaranteed Limits
Typ
Maximum High
Output Noise
(Notes 2,3)
5.0
1.0
1.5
V
4·13
Minimum Low
Output Noise
(Notes 2,3)
5.0
-0.6
-1.2
V
4·13
Maximum
Overshoot
(Notes 1, 3)
5.0
VOH+ 1.0
VOH+1.5
V
4·13
Minimum Vee
Droop
(Notes 1. 3)
5.0
VOH-1.0
VOH-1.8
V
4·13
VIHD
Minimum High
Dynamic Input
Voltage Level
(Notes 1, 4)
5.5
1.6
2.0
2.0
2.0
V
VILD
Maximum Low
Dynamic Input
Voltage Level
(Notes 1,4)
5.5
1.4
0.8
0.8
0.8
V
VOLP
VOLV
VOHP
VOHV
Worst case package.
Maximum number of outputs that can switch simultaneously is n. (n-l) outputs are switched LOW and one output held LOW.
Note 3: Maximum number of outputs that can switch simultaneously is n. (n-l) outputs are switched HIGH and one output held HIGH.
Note 4: Maximum number of data inputs (n) switching. (n-l) input switching OV to 3V. Input under test switching 3V to threshold (VILO).
Note 1:
Note 2:
8·47
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I-
o
"1::1"
11)
AC Electrical Characteristics
,....
Normal Operation: See Section 4
CO
Symbol
Parameter
Vee·
(V)
Min
tpLH,
tpHL
Propagation Delay
Data toO
tpLZ,
tpHZ
Disable Time
tpZL,
tPZH
Enable Time
Commercial
Military
Commercial
TA = +25°C
CL = 50 pF
TA = -55°C to + 125°C
CL = 50 pF
TA = -40°C to +85°C
CL = 50pF
Fig.
No.
Max
Min
Max
Min
Max
5.0
2.5
2.5
9.0
9.0
2.5
2.5
10.5
10.5
2.5
2.5
9.8
9.8
ns
4-1,2
5.0
1.5
1.5
10.2
10.2
1.5
1.5
11.2
11.2
1.5
1.5
10.7
10.7
ns
4-3,4
5.0
2.0
2.0
11.8
9.5
2.0
2.0
13.5
11.5
2.0
2.0
12.8
10.5
ns
4-3,4
Typ
·Voltage Range 5.0 is 5.0V ± 0.5V.
http://www.national.com
Units
8-48
AC Electrical Characteristics
Symbol
Parameter
Vcc·
(V)
Min
Scan Test Operation: See Section 4
Commercial
Military
Commercial
TA = +25°C
CL = 50 pF
TA = -55°C to + 125°C
CL = 50 pF
T A = - 40°C to + 85°C
CL = 50 pF
Fig.
No.
Max
Min
Max
Min
Max
5.0
3.5
3.5
13.2
13.2
3.5
3.5
15.8
15.8
3.5
3.5
14.5
14.5
ns
4-8
Disable Time
TCKtoTDO
5.0
2.5
2.5
11.5
11.5
2.5
2.5
12.8
12.8
2.5
2.5
11.9
11.9
ns
4-9,10
tpZL,
tPZH
Enable Time
TCKtoTDO
5.0
3.0
3.0
14.5
14.5
3.0
3.0
16.7
16.7
3.0
3.0
15.8
15.8
ns
4-9,10
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
5.0
5.0
18.0
18.0
5.0
5.0
21.7
21.7
5.0
5.0
19.8
19.8
ns
4-8
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During UpdateIR State
5.0
5.0
5.0
18.6
18.6
5.0
5.0
21.2
21.2
5.0
5.0
20.2
20.2
ns
4-8
tpLH,
tpHL
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
5.5
5.5
19.9
19.9
5.5
5.5
23.0
23.0
5.5
5.5
21.5
21.5
ns
4-8
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During UpdateDR State
5.0
4.0
4.0
16.4
16.4
4.0
4.0
19.6
19.6
4.0
4.0
18.2
18.2
ns
4-9,10
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During UpdateIRState
5.0
5.0
5.0
19.5
19.5
5.0
5.0
22.4
22.4
5.0
5.0
20.8
20.8
ns
4-9,10
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
5.0
5.0
19.9
19.9
5.0
5.0
23.3
23.3
5.0
5.0
21.5
21.5
ns
4-9,10
tpZL,
tPZH
Propagation Delay
TCK to Data Out
During UpdateDR State
5.0
5.0
5.0
18.9
18.9
5.0
5.0
22.6
22.6
5.0
5.0
20.9
20.9
ns
4-9,10
tpZL,
tPZH
Propagation Delay
TCK to Data Out
During UpdateIRState
5.0
6.5
6.5
22.4
22.4
6.5
6.5
26.2
26.2
6.5
6.5
24.2
24.2
ns
4-9,10
tpZL,
tPZH
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
7.0
7.0
23.8
23.8
7.0
7.0
27.4
27.4
7.0
7.0
25.7
25.7
ns
4-9,10
tpLH,
tpHL
Propagation Delay
TCKtoTDO
tpLZ,
tpHZ
Typ
Units
·Voltage Range 5.0 is 5.0V ±O.5V.
All Propagation Delays involving TCK are measured from the falling edge of TCK.
8-49
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•
I-
o
0IIIt'
Ln
CO
,...
AC Operating Requirements Scan Test Operation:
Symbol
Vcc·
(V)
Parameter
See Section 4
Commercial
Military
Commercial
TA = +25°C
CL = 50pF
TA = -55°C to + 125°C
CL = 50pF
TA = -40°C to +85°C
CL = 50 pF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, H or L
Data to TCK (Note 1)
5.0
3.0
3.0
3.0
ns
4-11
tH
Hold Time, H or L
TCK to Data (Note 1)
5.0
4.5
5.5
4.5
ns
4-11
ts
Setup Time, H or L
AOE n , BOE n
to TCK (Note 3)
5.0
3.0
3.0
3.0
ns
4-11
Hold Time, H or L
TCKto AOEn ,
BOE n (Note 3)
5.0
4.5
4.5
4.5
ns
4-11
Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 2)
5.0
3.0
3.0
3.0
ns
4-11
Hold Time, H or L
TCK to Internal
AOE, BOE (Note 2)
5.0
3.0
3.0
3.0
ns
4-11
ts
Setup Time, H or L
TMSto TCK
5.0
8.0
8.0
8.0
ns
4-11
tH
Hold Time, H or L
TCKtoTMS
5.0
2.0
2.0
2.0
ns
4-11
ts
Setup Time, H or L
TDI toTCK
5.0
4.0
4.0
4.0
ns
4-11
tH
Hold Time, H or L
TCKto TDI
5.0
4.5
4.5
4.5
ns
4-11
tw
Pulse Width TCK
15.0
5.0
15.0
5.0
15.0
5.0
ns
4-12
tH
ts
tH
5.0
H
L
fmax
MaximumTCK
Clock Frequency
5.0
25
25
25
MHz
Tpu
Wait Time,
Power Up to TCK
5.0
100
100
100
ns
TON
Power Down Deiay
0.0
100
100
100
ms
·Voltage Range 5.0 Is 5.0V ± 0.5V.
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17,18-26, and 27-35.
Note 2: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 3: Timing pertains to BSR 37, 38, 40 and 41.
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8-50
.......
Q)
Extended AC Electrical Characteristics:
Symbol
TA = Com
Vee = Com
CL = 50 pF
18 Outputs
Switching
(Note 2)
Parameter
See Section 4
.1:10
o
-f
TA = Mil
Vee = Mil
CL = 50 pF
18 Outputs
Switching
(Note 2)
TA = Com
Vee = Com
CL = 250 pF
(Note 3)
TA = Mil
Vee = Mil
CL = 250 pF
(Note 3)
Units
Max
Min
Max
Min
Max
Min
Max
tpLH.
tpHL
Propagation Delay
Data to Output
3.0
3.0
11.0
11.0
3.0
3.0
11.5
11.5
4.0
4.0
13.0
15.0
4.0
4.0
14.0
16.0
tpZH.
tPZL
Output Enable Time
2.5
2.5
11.5
14.0
2.5
2.5
12.5
14.5
(Note 4)
(Note 4)
ns
tpHZ.
tpLZ
Ouput Disable Time
2.0
2.0
11.5
11.5
2.0
2.0
12.0
12.0
(NoteS)
(Note 5)
ns
tOSHL
(Note 1)
Pin to Pin Skew
HL Data to Output
0.5
1.0
1.0
ns
tOSLH
(Note 1)
Pin to Pin Skew
LH Data to Output
0.5
1.0
1.0
ns
Min
Typ
U1
ns
Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (toSHU, LOW to HIGH (toSLH), or any combination LOW to HIGH and/or HIGH to LOW.
Note 2: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., alilow-to-high, highto-low etc.).
Note 3: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load. This specification pertains to single output switching only.
Note 4: TRI-STATE delays are load dominated and have been excluded from the datasheet.
Note 5: The Output Disable TIme is dominated by the RC network (SOOn, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Typ
Units
CIN
Symbol
Input Pin Capacitance
Parameter
4.0
pF
Vee
Conditions
=
5.0V
COUT
Output Pin Capacitance
13.0
pF
Vee
=
5.0V
CPD
Power Dissipation
Capacitance
34.0
pF
Vee
=
5.0V
•
8·51
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I,....
~
ttJNational Semiconductor
SCAN18541T
Non-Inverting Line Driver with TRI-STATE® Outputs
General Description
Features
The SCAN18541T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TO I), Test
Data Out (TOO), Test Mode Select (TMS), and Test Clock
(TCK).
•
•
•
•
•
•
•
•
•
•
IEEE 1149.1 (JTAG) Compliant
Dual output enable signals per byte
TAl-STATE outputs for bus-oriented applications
9-bit data busses for parity applications
Aeduced-swing outputs source 32 mA/sink 64 mA
(Comm), source 24 mA/sink 48 mA (Mil)
Guaranteed to drive 50n transmission line to TIL input
levels of 0.8V and 2.0V
TIL compatible inputs
25 mil pitch SSOP (Shrink Small Outline Package)
Includes CLAMP and HIGHZ instructions
Member of National's SCAN Products
Ordering Code: See Section 11
Pin Names
Connection Diagram
ncs- 1
AOo- 2
A0E,- 3
Ao,- 4
'-'
Pin Names
56 .... TOI
Input Pins, A Side
~S)__ Input Pins, B Side
AOE1, AOE2 TAl-STATE Output Enable Input Pins, A Side
BOE1, BOE2 TAl-STATE Output Enable Input Pins, 8 Side
AO(O-s)
Output Pins, A Side
AO(o-S)
Output Pins, 8 Side
55 -Alo
54 :-AOE2
53
~A~
A02 - 5
GNO- 6
52 -A12
51 ~GNO
A03 - 7
AO.- 8
50
~A13
49
~AI.
Vcc - 9
48 ~Vcc
A05 A06 -
10
47
~A15
11
46
~A16
GNO- 12
45 ~GNO
AO-,- 13
44 ~A7
AOa- 14
43
800- 15
42 ~81o
80,- 16
41 ~8~
Description
AI(O-S)
Truth Tables
I--_-.--_In_p_ut-rs_ _- I AO (0-8)
AOE2 AI (0-8)
L
H
X
~A18
L
i.
X
H
H
X
H
X
Z
Z
L
L
L
GNO- 17
40
~GNO
802- 18
39
~812
803- 19
38 ~813
Vcc - 20
37 ~Vcc
L
L
H
H
80.- 21
36
~81.
H
8°5- 22
35 ~815
X
X
Z
Z
GNO- 23
341-GNO
X
L
X
H
L
L
L
8°6- 24
33 1-8~
80-,- 25
32 ~87
80E,- 26
31
~80E2
80a- 27
30
~818
TOO- 28
29 I-TCK
I--_-.--_In_p_ut-rs_ _- I BO (0-8)
BOE2 BI (0-8)
H
L
X
=
=
Z =
TL/F/10965-1
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= HIGH Voltage Level
8-52
LOW Voltage Level
Immaterial
High Impedance
Order Number
Description
SCAN18541 TSSC
SCAN18541TSSCX
SCAN18541 TFMQ8
5962-9311601 MXA
SSOP in Tubes
SSOP in Tape and Aeel
Flatpak Military
Military SMD#
,-------------------------------------------------------------------------------------------,
~
co
U1
Block Diagrams
~
~
-I
Byte A
TYPE!
AI [0-8]
TL/F/l0965-2
Tap Controller
TO BSR [41]
FROM BSR [0]
BYPASS
REGISTER
TDI
TOO
INSTRUCTION
REGISTER
INSTRUCTION TRI-STATE
TMS
TCK
TEST
ACCESS
PORT
(TAP)
TLlF/l0965-3
Byte B
TL/F/l0965-4
Note: BSR stands for Boundary Scan Register.
8·53
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I,....
"I:t'
Ln
co
,....
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an 8-bit register which captures the default value of 10000001. The two least significant bits of this captured value (01) are required by IEEE
Std 1149.1. The upper six bits are unique to the
SCAN18541T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification
register. Therefore, this unique captured value can be used
as a "pseudo 10" code to confirm that the correct device is
placed in the appropriate location in the boundary scan
chain.
Instruction Register Scan Chain Definition
TOI
TOO
MSB
Bypass Register Scan Chain Definition
Logic 0
lSB
TL/F/l0965-10
MSB~LSB
Instruction Code
TL/F/l0965-9
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGH-Z
All Others
BYPASS
Scan Cell TYPE1
SCAN OUT
(to next cell)
DATA IN
----r--------------f-----
DATA OUT
SHIFT _DR ----4---1
SCAN IN
CLOCK-DR
(from previous cell)
TLlF/l0965-7
Scan Cell TYPE2
SCAN OUT
(to next cell)
DATA I N - - " " " T " - - - - - - - - - - - - - + - - - - - - - - - - I
DATA OUT
SHIFT _DR
---4---1
SCAN IN
UPDATE-DR
(from previous cell)
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TL/F/l0965-B
8-54
~----------------------------------------------------------------------------------~
~
(X)
U1
Description of Boundary-Scan Circuitry (Continued)
~
~
-i
Boundary-Scan Register
Scan Chain Definition (42 Bits In Length)
TDI
41
40
39
38
37
TOO
36
35
18
17
34
19
16
33
20
15
32
21
14
31
22
13
30
23
12
29
24
11
28
25
10
27
26
2
4
TL/F/10965-23
8·55
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Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register Definition Index
Bit No.
Pin Name
Pin No.
Pin Type
3
54
Input
Input
Internal
Input
Input
Internal
Scan Cell Type
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
Control
Signals
41
40
39
38
37
36
AOE1
AOE2
AOE
BOE1
BOE2
BOE
35
34
33
32
31
30
29
28
27
Alo
AI1
AI2
AI3
AI4
AI5
Als
AI7
Ala
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A-in
26
25
24
23
22
21
20
19
18
Blo
BI1
BI2
BI3
BI4
BI5
Bls
81 7
81a
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B-in
17
16
15
14
13
12
11
10
9
AOo
A01
A02
A03
A04
A05
AOs
A07
AOa
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A-out
8
7
6
5
4
3
2
1
0
800
80 1
802
803
804
805
80s
807
80a
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
8-out
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26
31
8-56
Absolute Maximum Ratings
(Note 1)
- 65·C to + 150·C
Storage Temperature
ESD(Min)
2000V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of SCAN Circuits outside databook specifications.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VeC>
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee +0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee +0.5V
DC Output Voltage (Vo)
DC Output Source/Sink Current (10)
-0.5V to + 7.0V
-20mA
+20mA
Recommended Operating
Conditions
-20mA
+20mA
-0.5V to Vee + 0.5V
±70mA
DC Vee or Ground Current
Per Output Pin
Junction Temperature
SSOP
Supply Voltage (VeC>
SCAN Products
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Commercial
Military
Minimum Input Edge Rate dV /dt
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
±70mA
+ 140·C
4.5Vto 5.5V
OVtoVee
OVtoVee
-40·C to + 85·C
- 55·C to + 125·C
125 mV/ns
DC Electrical Characteristics
Commercial
Symbol
Parameter
Vee
(V)
TA
Military
Commercial
= +25·C TA = -55·C to + 125·C TA = -40·C to + 85·C Units
Typ
Conditions
Guaranteed Limits
VIH
Minimum High
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
or Vee -O.W
VIL
Maximum Low
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee -o.w
VOH
Minimum High
Output Voltage
4.5
5.5
3.15
4.15
3.15
4.15
3.15
4.15
V
4.5
5.5
2.4
2.4
2.4
2.4
V
4.5
5.5
2.4
2.4
2.4
2.4
4.5
5.5
0.1
0.1
0.1
0.1
4.5
5.5
0.55
0.55
4.5
5.5
0.55
0.55
0.55
0.55
5.5
±0.1
±1.0
VOL
liN
Maximum Low
Output Voltage
Maximum Input
Leakage Current
Maximum Input
liN
TDI, TMS Leakage
10LO
10HO
0.1
0.1
V
0.55
0.55
V
V
±1.0
p.A
= - 50 p.A
= VIL or VIH
= -32mA
VIN = VIL or VIH
10H = -24mA
lOUT = 50 p.A
VIN
IOH
= VIL or VIH
= 64mA
VIN = VIL or VIH
10L = 48 mA
VIN
IOL
VI = Vee,GND
2.8
3.7
3.6
p.A
VI
-385
-385
-385
p.A
VI
5.5
-160
-160
-160
p.A
tMinimum Dynamic
5.5
Output Current
94
63
94
mA
VOLO
-40
-27
-40
mA
VOHO
Minimum Input
Leakage
5.5
V
lOUT
= Vee
= GND
VI = GND
= 0.8V Max
= 2.0V Min
tMaximum test duration 2.0 ms, one output loaded at a time.
8-57
http://www.national.com
DC Electrical Characteristics (Continued)
Commercial
Parameter
Symbol
Vee
(V)
TA
Military
Commercial
= +2S"C TA = -SS"C to + 12S"C TA = -40"C to +8S"C Units
Typ
Conditions
Guaranteed Limits
loz
Maximum Output
Leakage Current
5.5
±0.5
±10.0
±5.0
lOS
Output Short
Circuit Current
5.5
-100
-100
-100
IcC
Maximum Quiescent
5.5
Supply Current
16.0
168
88
/-LA
Vo = Open
TDI, TMS = Vcc
5.5
750
930
820
/-LA
Va = Open
TDI, TMS = GND
5.5
2.0
2.0
2.0
mA VI
ICet
Maximum Icc
Per Input
5.5
2.15
2.15
2.15
/-LA
VI (OE)
mA Va
(min)
= VIL, VIH
= OV
= Vcc- 2.1V
VI = Vcc- 2.1V
mA TDI/TMS Pin, Test One
with the Other Floating
outputs loaded; thresholds associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
"All
Noise Specifications:
See Section 4
Commercial
Symbol
Parameter
Vee
(V)
TA
= +2S"C
Military
TA
= -SS"C to + 12S"C
Typ
Commercial
TA
= -40"C to +8S"C
Units
Fig.
No.
Guaranteed Limits
Maximum High
Output Noise
(Notes 2, 3)
5.0
1.0
1.5
V
4-13
Minimum Low
Output Noise
(Notes 2,3)
5.0
-0.6
-1.2
V
4-13
Maximum
Overshoot
(Notes 1,3)
5.0
VOH+1.0
VOH+ 1.5
V
4-13
MinimumVcc
Droop
(Notes 1, 3)
5.0
VOH-1.0
VOH-1.8
V
4-13
VIHD
Minimum High
Dynamic Input
Voltage Level
(Notes 1, 4)
5.5
1.6
2.0
2.0
2.0
V
VILD
Maximum Low
Dynamic Input
Voltage Level
(Notes 1, 4)
5.5
1.4
0.8
0.8
0.8
V
VOLP
VOLV
VOHP
VOHV
Worst case package.
Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW.
Nota 3: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.
Note 4: Maximum number of data Inputs (n) switching. (n-1) input switching ov to 3V. Input under test switching 3V to threshold (VILO).
Nota 1:
Nota 2:
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8-58
.....
AC Electrical Characteristics
Symbol
Parameter
Vee·
(V)
tpLH,
tpHL
tpLZ.
tpHZ
Disable Time
tpZL.
tPZH
Enable Time
.....
Commercial
Military
Commercial
TA = +25°C
Cl = 50 pF
TA =
- 55°C to + 125°C
Cl = 50pF
TA =
- 40°C to + 85°C
Cl = 50pF
Typ
Min
Propagation Delay
Data toO
CD
U1
0l:Io
Normal Operation: See Section 4
-I
Units
Fig.
No.
Max
Min
Max
Min
Max
2.5
2.5
10.5
10.5
2.5
2.5
9.8
9.8
ns
4-1.2
5.0
2.5
2.5
9.0
9.0
5.0
1.5
1.5
10.2
10.2
1.5
1.5
11.2
11.2
1.5
1.5
10.7
10.7
ns
4-3.4
5.0
2.0
2.0
11.8
9.5
2.0
2.0
13.5
11.5
2.0
2.0
12.8
10.5
ns
4-3.4
'Voltage Range 5.0 is S.OV ± 0.5V.
AC Electrical Characteristics Scan Test Operation:
Symbol
Parameter
Vee·
(V)
See Section 4
Commercial
Military
Commercial
TA = +25°C
Cl = 50 pF
TA =
-55°C to + 125°C
Cl = 50pF
TA =
-40°C to + 85°C
Cl = 50pF
Max
Min
Max
13.2
13.2
3.5
3.5
15.8
15.8
3.5
3.5
14.5
14.5
ns
4-8
2.5
2.5
11.5
11.5
2.5
2.5
12.8
12.8
2.5
2.5
11.9
11.9
ns
4-9.10
5.0
3.0
3.0
14.5
14.5
3.0
3.0
16.7
16.7
3.0
3.0
15.8
15.8
ns
4-9.10
Propagation Delay
TCK to Data Out
During Update· DR State
5.0
5.0
5.0
18.0
18.0
5.0
5.0
21.7
21.7
5.0
5.0
19.8
19.8
ns
4-8
tpLH.
tpHL
Propagation Delay
TCK to Data Out
During Update·IR State
5.0
5.0
5.0
18.6
18.6
5.0
5.0
21.2
21.2
5.0
5.0
20.2
20.2
ns
4-8
tpLH.
tpHL
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
5.5
5.5
19.9
19.9
5.5
5.5
23.0
23.0
5.5
5.5
21.5
21.5
ns
4-8
tpLZ.
tpHZ
Propagation Delay
TCK to Data Out
During Update·DR State
5.0
4.0
4.0
16.4
16.4
4.0
4.0
19.6
19.6
4.0
4.0
18.2
18.2
ns
4-9.10
tpLZ,
tpHZ
Propagation Delay
TCK to Data Out
During Update·IR State
5.0
5.0
5.0
19.5
19.5
5.0
5.0
22.4
22.4
5.0
5.0
20.8
20.8
ns
4-9.10
tPLZ.
tpHZ
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
5.0
5.0
19.9
19.9
5.0
5.0
23.3
23.3
5.0
5.0
21.5
21.5
ns
4-9,10
tpZL.
tpZH
Propagation Delay
TCK to Data Out
During Update·DR State
5.0
5.0
5.0
18.9
18.9
5.0
5.0
22.6
22.6
5.0
5.0
20.9
20.9
ns
4-9.10
tpLH.
tpHL
5.0
3.5
3.5
tpLZ.
tpHZ
Disable Time
TCKtoTDO
5.0
tpZL.
tPZH
Enable Time
TCK to TOO
tpLH.
tpHL
Max
Fig.
No.
Min
Min
Propagation Delay
TCKtoTDO
Typ
Units
'Voltage Range 5.0 is S.OV ±O.SV.
All Propagation Delays involving TCK are measured from the falling edge of TCK.
8·59
http://www.national.com
AC Electrical Characteristics Scan Test Operation:
Symbol
Vee·
(V)
Parameter
See Section 4 (Continued)
Commercial
Military
Commercial
TA = +2SOC
Cl = SO pF
TA =
-Ssoc to + 12SOC
Cl = SOpF
TA =
- 40°C to + 8SoC
Cl = SOpF
Max
Min
Max
Min
Max
Min
Typ
Units
Fig.
No.
tpZL,
tPZH
Propagation Delay
TCK to Data Out
During Update-IR State
S.O
6.5
6.5
22.4
22.4
6.5
6.5
26.2
26.2
6.5
6.5
24.2
24.2
ns
4-9,10
tpZL,
tPZH
Propagation Delay
TCK to Data Out
During Test Logic
Reset State
5.0
7.0
7.0
23.8
23.8
7.0
7.0
27.4
27.4
7.0
7.0
25.7
25.7
ns
4-9,10
'Voltage Range 5.0 is 5.0V ± 0.5V.
All Propagation Delays involving TCK are measured from the falling edge of TCK.
AC Operating Requirements Scan Test Operation:
Symbol
Vee·
(V)
Parameter
See Section 4
Commercial
Military
Commercial
TA = +2SOC
Cl = SOpF
TA = -Ssoc to + 12SOC
Cl = SOpF
TA = -40°C to +8SOC
Cl = SOpF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, H or L
Data to TCK (Note 1)
5.0
3.0
3.0
3.0
ns
4-11
tH
Hold Time, H or L
TCK to Data (Note 1)
5.0
4.5
5.0
4.5
ns
4-11
ts
Setup Time, H or L
AOE n , BOEn
to TCK (Note 3)
5.0
3.0
3.0
3.0
ns
4-11
Hold Time, H or L
TCKto AOE n ,
BOEn (Note 3)
5.0
4.5
4.5
4.5
ns
4-11
Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 2)
5.0
3.0
3.0
3.0
ns
4-11
Hold Time, H or L
TCK to Internal
AOE, BOE (Note 2)
5.0
3.0
3.0
3.0
ns
4-11
ts
Setup Time, H or L
TMSto TCK
5.0
8.0
8.0
8.0
ns
4-11
tH
Hold Time, H or L
TCKto TMS
5.0
2.0
2.0
2.0
ns
4-11
ts
Setup Time, H or L
TDI toTCK
5.0
4.0
4.0
4.0
ns
4-11
tH
Hold Time, H or L
TCKto TDI
5.0
4.5
4.5
4.5
ns
4-11
tw
Pulse Width TCK
5.0
15.0
5.0
15.0
5.0
15.0
5.0
ns
4-12
tH
ts
tH
H
L
http://www.national.com
8-60
AC Operating Requirements Scan Test Operation:
See Section 4 (Continued)
Commercial
Symbol
Parameter
Military
TA = +2SOC
CL = SOpF
Vee·
(V)
TA
=
Commercial
-Ssoc to + 12SOC
CL = SOpF
TA
=
-40°C to +8SOC
CL = SOpF
Units
Guaranteed Minimum
f max
MaximumTCK
Clock Frequency
5.0
25
25
25
MHz
Tpu
Wait Time, Power Up
toTCK
5.0
100
100
100
ns
TON
Power Down Delay
0.0
100
100
100
ms
·Voltage Range 5.0 Is 5.0V ±0.5V.
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0·8, 9·17, 18·26 and 27·35.
Note 2: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 3: Timing pertains to BSR 37, 38, 40 and 41 only.
Extended AC Electrical Characteristics
Symbol
Parameter
TA = Com
Vee = Com
CL = SOpF
18 Outputs
Switching
(Note 2)
Min
Typ
TA = Mil
Vee = Mil
CL = SOpF
18 Outputs
Switching
(Note 2)
TA = Com
Vee = Com
CL = 2S0pF
(Note 3)
TA = Mil
Vee = Mil
CL = 2S0 pF
(Note 3)
Units
Max
Min
Max
Min
Max
Min
Max
tpLH,
tpHL
Propagation Delay
Data to Output
3.0
3.0
11.0
11.0
3.0
3.0
11.5
11.5
4.0
4.0
13.0
15.0
4.0
4.0
14.0
16.0
tpzH,
tPZL
Output Enable Time
2.5
2.5
11.5
14.0
2.5
2.5
12.5
14.5
(Note 4)
(Note 4)
ns
tpHZ,
tpLZ
Output Disable Time
2.0
2.0
11.5
11.5
2.0
2.0
12.0
12.0
(NoteS)
(Note 5)
ns
tOSHL
(Note 1)
Pin to Pin Skew
HL Data to Output
0.5
1.0
1.0
ns
tOSLH
(Note 1)
Pin to Pin Skew
LH Data to Output
0.5
1.0
1.0
ns
ns
Nota 1: Skew Is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (toSHU, LOW to HIGH (toSLH), or any combination switching LOW to HIGH and/or HIGH to LOW.
Note 2: This specification Is guaranteed but not tested. The limits apply to propagation delays for all paths described switching In phase (I.e., all low· to· high, high·
to-low, etc.).
Note 3: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load. This specification pertains to single output switching only.
Note 4: TRI-STATE delays are load dominated and have been excluded from the datasheet.
Note 5: The Output Disable Time Is dominated by the RC network (500n, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
Typ
Units
Input Pin Capacitance
4.0
pF
Vee
COUT
Output Pin Capacitance
13.0
pF
Vee
CPO
Power Dissipation
Capacitance
34.0
pF
CIN
Parameter
8-61
Conditions
= 5.0V
= 5.0V
Vee = 5.0V
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Section 9
SCAN ABT Test Access
Logic Datasheets
http://www.national.com
Section 9 Contents
SCAN182245A Non-Inverting Transceiver with 25.0 Series Resistor Outputs. . . . . . . . . . . . . . .
SCAN 182373A Transparent Latch with 25.0 Series Resistor Outputs. . . . . . . . . . . . . . . . . . . . . .
SCAN 182374A 0 Flip-Flop with 25.0 Series Resistor Outputs ............................
SCAN 182541 A Non-Inverting Line Driver with 25.0 Series Resistor Outputs. . . . . . . . . . . . . . . .
9-2
9-3
9-18
9-31
9-44
f}1National Semiconductor
SCAN 182245A
Non-Inverting Transceiver with
25n Series Resistor Outputs
General Description
Features
The SCAN182245A is a high performance SiCMOS bidirectional line driver featuring separate data inputs organized
into dual 9-bit bytes with byte-oriented output enable and
direction control signals. This device is compliant with
IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture with the incorporation of the defined
boundary-scan test logic and test access port consisting of
Test Data Input (TOI), Test Data Out (TOO), Test Mode Select (TMS), and Test Clock (TCK).
• High performance BiCMOS technology
• 250 series resistors in outputs eliminate the need for
external terminating resistors
• Dual output enable control signals
• TRI-STATE® outputs for bus-oriented applications
• 25 mil pitch SSOP (Shrink Small Outline Package)
• IEEE 1149.1 (JTAG) Compliant
• Includes CLAMP, IDCODE and HIGHZ instructions
• Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
• Power Up TRI-STATE for hot insert
• Member of National's SCAN Products
Ordering Code: See Section 11
Connection Diagram
Tt.4S -
1
81 0 -
2
\.J
56
to- TOI
55 I- Ala
DlRl- 3
54
to- G1
81 , -
4
53
to- A"
81 2 -
5
GND- 6
52 -A1 2
51 - GND
813 -
7
50 -
81. -
8
49 -
AI.
Vee -
9
48 -
Vee
81 5 -
10
47 - A15
816 -
11
46 -
A16
GND -
12
45 -
GND
81 7 -
13
44 -
A '7
81a -
14
43 -
Ala
A20
82 0 -
15
42 -
82 , -
16
41 -A2,
GND -
17
40 -
GND
82 2 -
18
39 -
A22
82 3 -
19
38 -
A23
Vee -
20
37 -
Vee
82. -
21
36 -
A2.
82 5 -
22
35 I- A25
GND -
23
34 I- GND
82 6 -
24
33
82 7 -
25
32 I- A27
26
31 I- G2
82a -
27
30 I- A2a
29
A1(0-8)
B1 (0-8)
A2(0_8)
B2(0_8)
G1,G2
DIR1, DIR2
Description
Side A 1 Inputs or TRI-STATE Outputs
Side B1 Inputs orTRI-STATE Outputs
Side A2 Inputs or TRI-STATE Outputs
Side B21nputs orTRI-STATE Outputs
Output Enable Pins (Active Low)
Direction of Data Flow Pins
Order Number
Description
SCAN 182245ASSC
SCAN182245ASSCX
SCAN 182245AFMQB
SSOP in Tubes
SSOP Tape and Reel
Flatpak Military
to- A26
DIR2 -
TOO- 28
Pin Names
A '3
to- TCK
TL/FI116S7-1
9-3
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Truth Tables
Functional Description
I
Inputs
A1(0-8)
tG1
DIR1
L
L
L
L
H
L
L
H
H
H
L
H
L
X
Z
~
~
---+
---+
I
A2(0-8)
DIR2
L
L
L
L
H
L
L
H
H
H
L
H
L
X
Z
B1(0-8)
H
L
H
L
Z
Inputs
tG2
The SCAN182245A consists of two sets of nine non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1
and DIR2) LOW enables data from B ports to A ports, when
HIGH enables data from A ports to B ports. The Output
Enable pins (G1 and G2) when HIGH disables both A and B
ports by placing them in a high impedance condition.
~
~
---+
---+
B2(0-8)
H
L
H
L
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
t = Inactive·to-Active transition must occur to enable outputs upon
power-up.
Block Diagrams
A1, 81, G1 and DIR1
TYPE1
TYPE1
A1 [0-8]
B1 [0-8]
TLIF/11657-2
Note: BSR stands for Boundary Scan Register.
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9-4
r-----------------------------------------------------------------------------------------~
Block Diagrams
~
co
N
(Continued)
N
0l:Io
U1
»
Tap Controller
r----.,
fROM BSR[O]
IDCODE
REGISTER
TOI
BYPASS
REGISTER
TOO
INSTRUCTION TRI-STATE
TMS
TCK
TL/F/11657-18
A2, 82, G2 and DIR2
TYPE1
TYPE2
82 [o-a]
A2 [o-a]
TL/F/11657-3
Note: BSR stands for Boundary Scan Register.
9-5
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Description of BOUNDARY-SCAN Circuitry
The INSTRUCTION register is an a-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required to
shift in the a-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR ~ EXIT1-IR ~ UPDATE-IR
will update the SAMPLE/PRELOAD instruction. For more
information refer to the section on instruction definitions.
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data. while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12for
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
Instruction Register Scan Chain Definition
TOI
TOO
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
t.lSB
lSB
Bypass Register Scan Chain Definition
Logic 0
TL/F/11657-10
MSB
Instruction Code
~
LSB
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
TL/F/11657-17
SCAN182245A Product IDCODE
(32-BIt Code per IEEE 1149.1)
Version Entity
0000
Part
Number
Manufacturer Required by
1149.1
10
111111 0000000000 00000001111
MSB
http://www.national.com
1
LSB
9-6
00000011
HIGH-Z
01000001
SAMPLE-IN
01000010
SAMPLE-OUT
00100010
EXTEST-OUT
10101010
IDCODE
11111111
BYPASS
All Others
BYPASS
.....
CO
N
Description of BOUNDARY-SCAN Circuitry (Continued)
N
0l:Io
U1
l>
Scan Cell TVPE1
SCAN OUT
(to next cell)
DATA IN--------,---------------------------------+------------DATAOUT
SHIrT _DR
-----+---1
SCAN IN
(from previous cell)
TLlF/11657-11
Scan Cell TVPE2
SCAN OUT
(to next cell)
MODE
--------1
DATAIN------,---------------------------------+---------------------~
DATA OUT
SHI rT _ DR - - - - . f - - - f
SCAN IN
CLOCK-DR
(from previous cell)
TL/F/11657-12
9·7
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (80 Bits In Length)
TOI
36
IN
37
IN
38
IN
39
IN
IN
40
IN
IN
41
IN
IN
42
IN
IN
43
IN
IN
44
IN
IN
45
IN
IN
46
IN
10
IN
47
IN
11
48
IN
12
IN
49
IN
13
IN
50
IN
14
IN
IN
51
15
IN
52
IN
16
IN
53
IN
17
TL/F/11657-32
http://www.national.com
9·8
Description of BOUNDARY-SCAN Circuitry (Continued)
Input BOUNDARY-SCAN Register
Scan Chain Definition (40 Bits In Length)
When Sample In Is Active
TOI
75
7J.
TOO
71
IN
35
IN
70
34
IN
69
33
68
32
67
31
66
30
65
29
IN
64
28
IN
63
IN
62
26
IN
61
25
IN
60
24
IN
59
23
IN
58
IN
22
IN
57
IN
21
IN
56
IN
20
IN
55
IN
19
IN
54
IN
18
IN
IN
27
•
TL/F/11657-33
9·9
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
Output BOUNDARY-SCAN Register
Scan Chain Definition (40 Bits in Length)
When Sample Out and EXTEST-Out are Active
TOI
TYPE2
73
TOO
72
OUT
36
OUT
37
OUT
OUT
38
OUT
OUT
39
OUT
OUT
40
OUT
OUT
41
OUT
OUT
42
OUT
OUT
43
OUT
OUT
44
OUT
OUT
45
OUT
OUT
46
OUT
10
OUT
47
OUT
11
OUT
48
OUT
12
OUT
49
OUT
13
OUT
50
OUT
14
OUT
51
15
OUT
52
16
OUT
53
OUT
17
TLlF/11657-34
http://www.national.com
9-10
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY·SCAN Register Definition Index
Pin No.
Pin Type
3
54
76
75
74
73
72
DIR1
G1
AOE1
80E1
DIR2
G2
AOE2
80E2
Input
Input
Internal
Internal
Input
Input
Internal
Internal
TYPE1
TYPE1
TYPE2
TYPE2
TYPE1
TYPE1
TYPE2
TYPE2
Control
Signals
71
70
69
68
67
66
65
64
63
A10
A11
A12
A13
A14
A15
A16
A17
A18
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A1-in
62
61
60
59
58
57
56
55
54
A20
A21
A22
A23
A24
A25
A26
A27
A28
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A2-in
53
52
51
50
49
48
47
46
45
81 0
81 1
81 2
81 3
81 4
81 5
81 6
81 7
81 8
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
81-out
44
43
42
41
40
39
38
37
36
82 0
82 1
82 2
82 3
82 4
82 5
826
827
82 8
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
82-out
35
34
33
32
31
30
29
28
27
81 0
81 1
81 2
81 3
81 4
81 5
81 6
81 7
81 8
2
4
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
81-in
Bit No.
79
78
77
Pin Name
26
31
5
7
8
10
11
13
14
9-11
Scan Cell Type
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index (Continued)
Pin No.
Pin Type
26
25
24
23
22
21
20
19
18
B20
B21
B22
B23
B24
B25
B26
B27
B28
15
16
18
19
21
22
24
25
27
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B2-in
17
16
15
14
13
12
11
10
9
A10
A11
A12
A13
A14
A15
A16
A17
A18
55
53
52
50
49
47
46
44
43
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A1-out
8
7
6
5
4
3
2
1
0
A20
A21
A22
A23
A24
A25
A26
A27
A28
42
41
39
38
36
35
33
32
30
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A2-out
Bit No.
http://www.national.com
Pin Name
9·12
Scan Cell Type
r-------------------------------------------------------------------------------------------,
SCAN ABT Live Insertion and Power Cycling Characteristics
I\)
Go
flip-flop. To bring the device out of high impedance. the
input must receive an inactive-to-active transition, a high-tolow transition on
in this case to change the state of the
flip-flop. With a Iowan the Q output of the flip-flop. the NOR
gate is free to allow propagation of a Go signal.
SCAN ABT is intended to serve in Live Insertion backplane
applications. It provides 2nd Levellsolation 1 which indicates
that while external circuitry to control the output enable pin
is unnecessary, there may be a need to implement differential length backplane connector pins for Vee and GND. As
well, pre-bias circuitry for backplane pins may be necessary
to avoid capacitive loading effects during live insertion.
Go
During power-down, the Power-an-Reset circuitry will become active and reset the flip-flop at approximately 1.BV
Vee. Again. the Q output of the flip-flop returns to a high and
disables the NOR gate from inputs from the Go pin. The
device will then remain in high impedance for the remaining
ramp down from 1.BV to O.OV Vee.
Some suggestions to help the designer with live insertion
issues:
SCAN ABT provides control of output enable pins during
power cycling via the circuit in Figure A. It essentially controls the Gn pin until Vee reaches a known level.
During power-up, when Vee ramps through the O.OV to O.7V
range, all internal device circuitry is inactive, leaving output
and I/O pins 01 the device in high impedance. From approximately O.BV to 1.BV Vee, the Power-an-Reset circuitry,
(PaR), in Figure A becomes active and maintains device
high impedance mode. The paR does this by providing a
low from its output that resets the flip-flop The output, 5, of
the flip-flop then goes high and disables the NOR gate from
an incidental low input on the Gn pin. After 1.BV Vee, the
paR circuitry becomes inactive and ceases to control the
Go
• The
pin can float during power-up until the Power-OnReset circuitry becomes inactive.
Go
• The
pin can float on power-down only after the Power-an-Reset has become active.
The description of the functionality of the Power-an-Reset
circuitry can best be described in the diagram of Figure B.
TO INTERNAL
TRI-STATE CIRCUITRY
VCC
ClK
ot--_. . .
RESET
POWER
ON
RESET
TLlF/11657-19
FIGURE A
~
~
I
I
I
I
I
I
I
DEVICE IN HIGH
IMPEDANCE MODE
VCC (v)
I POWER-ON RESET CIRCUIT OFF
I
I
I
I
I
I
I
All CIRCUIT --(oi4z!S~~~~----.._--""T""--___r----......_~__........,;--.._--""T""--___r----......_--__...~~~~~
ELEMENTS INACTIVE
RAMP-UP AND RAt.4P-DOWN TIME
POWER DOWN CYCLE
POWER UP CYCLE
TLlF/11657-20
FIGURES
1Section 7, "Design Consideration for Fault Tolerant Backplanes", Application Note AN-BB1.
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.
9-13
~
co
I\)
http://www.national.com
0l::Io
UI
l>
Absolute Maximum Ratings
(Note 1)
DC Latchup Source Current
Commercial
Military
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
-65°C to + 150°C
Over Voltage Latchup (lID)
Ambient Temperature under Bias
- 55°C to + 125°C
ESD (HBM) Min.
Junction Temperature under Bias
Ceramic
Plastic
- 55°C to + 175°C
- 55°C to + 150°C
Vee Pin Potential to
Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
- 0.5V to + 7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
-500mA
-300 mA
10V
2000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
-0.5Vto +5.5V
-0.5VtoVee
- 55°C to + 125°C
- 40°C to + 85°C
Supply Voltage
Military
Commercial
Twice the Rated IOL (mA)
+ 4.5V to + 5.5V
+ 4.5V to + 5.5V
(AVI.M)
50 mV/ns
20 mV/ns
Minimum Input Edge Rate
Data Input
Enable Input
DC Electrical Characteristics
Symbol
VIH
Vee
Parameter
Min
Typ
Max
Units
Conditions
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
-1.2
V
2.0
Input HIGH Voltage
Vil
Input LOW Voltage
VeD
Input Clamp Diode Voltage
Min
VOH
Output HIGH Voltage
Min
2.5
Min
2.0
V
2.0
V
Mil
VOL
IIH
V
= -18 mA
= -3mA
IOH = -24mA
IOH = -32mA
liN
IOH
Comm
Min
Mil
Min
0.8
V
Comm
Min
0.8
V
Max
5
p.A
= 12 mA
= 15 mA
VIN = 2.7V (Note 1)
Max
5
p.A
VIN
Max
5
p.A
VIN
Output LOW Voltage
Input HIGH Current
All Others
TMS, TOI
IOL
IOl
Vee
VIN
=
=
=
VIN
=
5.5V
=
0.5V (Note 1)
IBVI
Input HIGH Current
Breakdown Test
Max
7
p.A
IBVIT
Input HIGH Current
Breakdown Test (1/0)
Max
100
p.A
IlL
Input LOW Current
Max
-5
p.A
VIN
Max
-5
p.A
VIN
Max
-385
p.A
VIN
All Others
TMS, TOI
VID
Input Leakage Test
0.0
V
4.75
liD
All Other Pins Grounded
IIH + IOZH
Output Leakage Current
Max
50
p.A
VOUT
Output Leakage Current
Max
-50
p.A
VOUT
IOZH
Output Leakage Current
Max
50
p.A
VOUT
IOZL
Output Leakage Current
Max
-50
p.A
VOUT
http://www.national.com
9-14
7.0V
= O.OV
= O.OV
= 1.9 /J-A
IlL + IOZl
Note 1: Guaranteed not tested.
Vee
=
=
=
=
2.7V
0.5V
2.7V
0.5V
DC Electrical Characteristics
(Continued)
Vee
Min
los
Output Short-Circuit Current
Max
-100
ICEX
Output HIGH Leakage Current
Izz
Bus Drainage Test
ICCH
Power Supply Current
Parameter
Symbol
Typ
Max
Units
-275
rnA
Your = O.OV
Max
50
p,A
Your = Vcc
0.0
100
p,A
Your = 5.5V
All Others GND
Your = Vcc; TDI, TMS = Vcc
Conditions
Max
250
p,A
Max
1.0
rnA
Your = Vcc; TDI, TMS = GND
ICCl
Power Supply Current
Max
65
rnA
Your = LOW; TDI, TMS = Vcc
Max
65.8
rnA
Your = LOW; TDI, TMS = GND
Iccz
Power Supply Current
Max
250
p,A
TDI, TMS = Vcc
Max
1.0
rnA
TDI, TMS = GND
Iccr
Additionallcc/lnput
All Other Inputs
Max
2.9
rnA
VIN = Vcc - 2.1V
TDI, TMS inputs
Max
3
rnA
VIN = Vcc - 2.1V
mAl
Outputs Open
One Bit Toggling, 50% Duty Cycle
ICCD
No Load
Dynamic Icc
Max
AC Electrical Characteristics
Symbol
Parameter
Vee·
(V)
Propagation Delay
A to B, B toA
tpLZ
tpHZ
Disable Time
tpZl
tPZH
Enable Time
MHz
NormalOperation: See Section 4
Military
Commercial
TA = -55°C to + 125°C
CL = 50pF
TA = -40°C to + 85°C
CL = 50 pF
Typ
Max
Units
Fig.
No.
Min
Typ
Max
5.0
1.0
1.5
3.1
4.4
5.2
6.5
ns
4-1,2
5.0
1.5
1.5
4.8
5.2
8.6
8.9
ns
4-3,4
5.0
1.5
1.5
5.5
4.6
9.1
8.2
ns
4-3,4
Min
tplH
tpHl
0.2
·Voltage Range 5.0V ± O.5V
9-15
http://www.national.com
BOUNDARY·SCAN Register
Scan Chain Definition (42 Bits In Length)
TOI
41
40
39
38
37
TOO
36
35
18
17
34
19
16
33
20
15
32
21
14
31
22
13
30
23
12
29
24
11
28
25
10
27
26
0
TL/F/11544-23
9·23
http://www.national.com
•
Description of BOUNDARY-SCAN Circuitry (Continued)
Input BOUNDARY-SCAN Register
Scan Chain Definition (22 Bits In Length)
When Sample In Is Active
TDI
41
40
P26
TYPE1
38
37
TDO
P55
TYPE1
35
18
34
19
33
20
32
21
31
22
30
23
29
24
28
25
27
26
TL/F/11544-24
http://www.national.com
9·24
~--------------------------------------------------------------------------------.
~
co
N
Description of BOUNDARY-SCAN Circuitry (Continued)
W
.......
w
l>
Output BOUNDARY-SCAN Register
Scan Chain Definition (20 Bits In Length)
When Sample Out and Extest Out are Active
TDI
TYPE2
39
TYPE2
TDO
36
17
0
16
15
14
13
12
11
10
TLIF 111544-25
9-25
http://www.nationai.com
•
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY·SCAN Register Definition Index
Bit No.
Pin Name
PinNa.
Pin Type
Input
Input
Internal
Input
Input
Internal
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
Control
Signals
Scan Cell Type
41
40
39
38
37
36
AOE1
ALE
AOE
BOE1
BLE
BOE
3
54
35
34
33
32
31
30
29
28
27
Alo
AI1
AI2
Ais
AI4
AIS
AI6
AI7
Ais
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A-in
26
25
24
23
22
21
20
19
18
Blo
BI1
BI2
Bis
BI4
BIS
BI6
BI7
Bis
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B-in
17
16
15
14
13
12
11
10
9
AOO
A01
A02
AOs
A04
AOs
A06
A07
AOs
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A-out
8
7
6
5
4
3
2
1
0
BOo
B01
B02
BOs
B04
BOS
B06
B07
BOa
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B-out
http://www.national.com
26
31
9-26
Absolute Maximum Ratings
(Note 1)
Over Voltage Latchup (I/O)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/DIstributors for availability and specifications.
Storage Temperature
- 65°C to + 150°C
Ambient Temperature under Bias
- 55°C to + 125°C
Note 2: Either voltage limit of current limit is sufficient to protect Inputs.
Recommended Operating
Conditions
- 55°C to + 175°C
- 55°C to + 150°C
Vee Pin Potential to
Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 mA to + 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
2000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Junction Temperature under Bias
Ceramic
Plastic
10V
ESD (HBM) Min
Free Air Ambient Temperature
Military
Commercial
- 55°C to + 125°C
- 40°C to + 85°C
Supply Voltage
Military
Commercial
- 0.5V to + 5.5V
-0.5V to Vee
+ 4.5V to + 5.5V
+ 4.5V to + 5.5V
(~V/~t)
Minimum Input Edge Rate
Data Input
Enable Input
50 mV/ns
20 mV/ns
Twice the Rated 10L (mA)
DC Latchup Source Current
Commercial
Military
-500 mA
-300 mA
DC Electrical Characteristics
Symbol
Vee
Parameter
Min
Typ
Max
Units
Conditions
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
-1.2
V
liN
2.0
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Veo
Input Clamp Diode Voltage
Min
VOH
Output HIGH Voltage
Min
2.5
V
10H = -3 mA
Mil
Min
2.0
V
10H = -24 mA
Comm
Min
2.0
V
10H = -32 mA
Mil
Min
0.8
V
10L = 12 mA
VOL
Output LOW Voltage
IIH
Input HIGH Current
Comm
All Others
TMS, TDI
Min
0.8
V
5
IJ-A
VIN = 2.7V (Note 1)
Max
5
IJ-A
VIN = Vee
Max
5
IJ-A
VIN = Vee
Input HIGH Current
Breakdown Test
Max
7
IJ-A
ISVIT
Input HIGH Current
Breakdown Test (I/O)
Max
100
IJ-A
IlL
Input LOW Current
TMS, TDI
10L = 15 mA
VIN = 7.0V
VIN = 5.5V
Max
-5
IJ-A
VIN = 0.5V (Note 1)
Max
-5
IJ-A
VIN = O.OV
Max
-385
IJ-A
VIN = O.OV
VIO
Input Leakage Test
IIH + 10ZH
Output Leakage Current
Max
50
Lozl
Output Leakage Current
Max
-50
III +
-18 mA
Max
ISVI
All Others
=
0.0
V
4.75
/-LA
110 = 1.9 /-LA
All Other Pins Grounded
VOUT
=
2.7V
VOUT
=
0.5V
10ZH
Output Leakage Current
Max
50
/-LA
VOUT
=
2.7V
10ZL
Output Leakage Current
Max
-50
IJ-A
VOUT
=
0.5V
los
Output Short-Circuit Current
Max
-275
mA
VOUT
=
O.OV
-100
Note 1: Guaranteed not tested.
9-27
http://www.national.com
DC Electrical Characteristics (Continued)
Parameter
Vee
Max
Units
ICEX
Output HIGH Leakage Current
Max
50
p.A
Izz
Bus Orainage Test
0.0
100
p.A
leCH
Power Supply Current
Max
250
p.A
VOUT
= Vee; TOI, TMS = Vce
Max
1.0
mA
VOUT
= Vee; TOI, TMS = GNO
Max
65
mA
VOUT
= LOW; TOI, TMS = Vee
Max
65.8
mA
VOUT
= LOW; TOI, TMS = GNO
Max
250
p.A
TOI, TMS
Max
1.0
mA
TOI, TMS
All Other Inputs
Max
2.9
mA
VIN
= Vee -2.1V
TOI, TMS Inputs
Max
3
mA
VIN
= Vee -2.1V
mAl
Outputs Open
One Bit Toggling, 50% Outy Cycle
Symbol
leCl
Power Supply Current
lecz
Power Supply Current
leCT
leCD
Additionallee/lnput
No Load
Oynamiclee
Min
Typ
0.2
Max
MHz
Conditions
= Vee
VOUT = 5.5V
VOUT
All Others Grounded
= Vee
= GNO
Note 1: Guaranteed not tested.
AC Electrical Characteristics NormalOperation:
See Section 4
Military
Symbol
Parameter
Vce·
(V)
TA
Commercial
= -55°C to + 125°C
CL = 50pF
Typ
Min
Max
TA
= -40°C to +85°C
CL = 50 pF
Min
Typ
Max
3.7
4.5
Units
Fig.
No.
6.5
7.4
ns
4-1,2
tpLH
tpHl
Propagation Oelay
OtoO
5.0
1.2
2.0
tpLH
tpHl
Propagation Oelay
LEtoO
5.0
1.3
1.8
4.1
4.5
7.4
7.3
ns
4-1,2
tpLZ
tpHZ
Oisable Time
5.0
1.6
1.8
4.9
6.0
9.0
10.7
ns
4-3,4
tpZl
tPZH
Enable Time
5.0
1.6
1.0
6.0
5.0
9.5
9.3
ns
4-3,4
·Voltage Range 5.0V ± O.SV
AC Operating Requirements NormalOperation:
See Section 4
Military
Symbol
Parameter
Vec·
(V)
TA
= -55°C to + 125°C
CL = 50pF
Commercial
TA
= -40°C to + 85°C
CL = 50pF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, H or L
Oata to LE
5.0
1.7
ns
4-5
tH
Hold Time, H or L
LEto Oata
5.0
1.6
ns
4-5
tw
LE Pulse Width
5.0
2.3
ns
4-2
·Voltage Range 5.0V ±O.SV
http://www.national.com
9-28
AC Electrical Characteristics Scan Test Operation:
Symbol
Parameter
Vcc·
(V)
See Section 4
Military
Commercial
TA = -55°C to + 125°C
CL = 50pF
TA = -40°C to + 85°C
CL = 50pF
Min
Typ
Fig.
No.
Min
Typ
Max
5.0
3.6
4.8
5.8
7.4
8.6
10.6
ns
4-8
Disable Time
TCKtoTDO
5.0
2.7
4.0
5.6
7.1
9.0
10.9
ns
4-9,10
tPZL
tPZH
Enable Time
TCKto TDO
5.0
5.2
3.6
8.6
6.6
12.5
10.1
ns
4-9,10
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
3.9
5.1
6.4
8.0
9.5
11.6
ns
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Update-IR State
5.0
4.7
5.7
7.7
9.1
11.3
13.1
ns
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
5.5
6.7
9.2
10.7
13.6
15.6
ns
5.0
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Update-DR State
5.0
4.1
4.7
7.7
8.4
12.1
12.7
ns
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Update-IR State
5.0
4.2
4.7
8.3
9.0
13.5
14.0
ns
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Test Logic
Reset State
5.5
6.3
10.1
10.8
15.6
16.2
ns
5.0
tpZL
tpZH
Enable Time
TCK to Data Out
during Update-DR State
5.0
5.8
4.3
9.6
7.7
14.2
11.7
ns
tPZL
tpZH
Enable Time
TCK to Data Out
during Update-IR State
5.0
6.1
4.7
11.0
9.0
16.0
13.7
ns
tPZL
tpZH
Enable Time
TCK to Data Out
during Test Logic
Reset State
7.3
5.8
12.5
10.5
18.3
15.8
ns
tpLH
tpHL
Propagation Delay
TCKtoTDO
tpLZ
tpHZ
5.0
Max
Units
4-8
4-8
4-8
4-9,10
4-9,10
4-9,10
4-9,10
4-9,10
4-9,10
·Voltage Range 5.0V ±O.5V
9-29
http://www.nationai.com
AC Operating Requirements Scan Test Operation:
See Section 4
Military
Symbol
Vee·
(V)
Parameter
TA
=
-55°C to + 125°C
CL = 50pF
Commercial
TA
=
-40°C to + 85°C
CL = 50pF
Fig.
Units
No.
Guaranteed Minimum
ts
Setup Time,
Data to TCK (Note 2)
5.0
2.7
ns
4-11
tH
Hold Time,
Data to TCK (Note 2)
5.0
2.4
ns
4-11
ts
Setup Time, H or L
AOE1, BOE1 to TCK (Note 1)
5.0
5.1
ns
4-11
tH
Hold Time, H or L
TCK to AOE1, BOE1 (Note 1)
5.0
1.8
ns
4-11
ts
Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 3)
5.0
3.5
ns
4-11
Hold Time, H or L
TCK to Internal
AOE, BOE (Note 3)
5.0
1.8
ns
4-11
ts
Setup Time
ALE, BLE (Note 4) to TCK
5.0
5.1
ns
4-11
tH
Hold Time
TCK to ALE, BLE (Note 4)
5.0
1.8
ns
4-11
ts
Setup Time, H or L
TMSto TCK
5.0
7.9
ns
4-11
tH
Hold Time, H or L
TCKto TMS
5.0
1.8
ns
4-11
ts
Setup Time, H or L
TDltoTCK
5.0
6.0
ns
4-11
tH
Hold Time, H or L
TCKto TDI
5.0
3.0
ns
4-11
tw
Pulse Width TCK
5.0
10.3
10.3
ns
4-12
f max
MaximumTCK
Clock Frequency
5.0
50
MHz
tpu
Wait Time, Power Up to TCK
5.0
100
ns
tON
Power Down Delay
0.0
100
ms
tH
H
L
·Voltage Range 5.0V ±0.5V.
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note
1: Timing pertains to BSR 38 and 41 only.
Note 2: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8,9-17,18-26 and 27-35.
Note 3: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 4: Timing pertains to BSR 37 and 40 only.
Capacitance
Parameter
Symbol
Typ
Units
Conditions, T A
=
CIN
Input Capacitance
5.8
pF
Vee = O.OV
COUT (Note 1)
Output Capacitance
13.8
pF
Vee = 5.0V
Note 1: COUT is measured at frequency f
ht1p:llwww.national.com
= 1 MHz. per MIL-STD-883B, Method 3012
9-30
25°C
IfINational Semiconductor
SCAN182374A
D Flip-Flop with 250 Series Resistor Outputs
General Description
Features
The SCAN182374A is a high performance BiCMOS D·type
flip·flop featuring separate D·type inputs organized into dual
9·bit bytes with byte·oriented clock and output enable con·
trol signals. This device is compliant with IEEE 1149.1 Stan·
dard Test Access Port and Boundary Scan Architecture with
the incorporation of the defined boundary·scan test logic
and test access port consisting of Test Data Input (TDI),
Test Data Out (TDO), Test Mode Select (TMS), and Test
Clock (TCK).
• IEEE 1149.1 (JTAG) Compliant
• High performance BiCMOS technology
• 25!l series resistor outputs eliminate need for external
terminating resistors
• Buffered positive edge·triggered clock
• TRI·STATE~ outputs for bus·oriented applications
• 25 mil pitch SSOP (Shrink Small Outline Package)
• Includes CLAMP, IDCODE and HIGHZ instructions
• Additional instructions SAMPLE·IN, SAMPLE·OUT and
EXTEST·OUT
• Power up TRI·STATE for hot insert
• Member of National's SCAN Products
Ordering Code: See Section 11
Connection Diagram
n.4S- 1
'-../
56 I-TOI
AOo- 2
551- Al o
A0E,- 3
54 f-ACP
Ao,- 4
53 I-AII
A02 -
5
52 r-A1 2
GNO- 6
51 f-GNO
A03 A04 Vee -
7
50 I-AI3
8
49 -A1 4
48 -Vee
A05 A06 -
9
10
11
47 -A15
46 -Als
GNO- 12
45 -GNO
A~-
13
44 -A1 7
AOa- 14
43 -Al s
42 -Blo
BOa- lS
Bo,- 16
GND- 17
18
19
39 -B1 2
38 -B13
Vee B04 -
20
37 -Vee
21
36 -B14
35 f-B15
B0E,- 26
BOs - 27
TOO- 28
30 -Bls
29 i-TCK
H
B~-
25
Order Number
Description
Data Inputs
Clock Pulse Inputs
TRI·STATE Output
Enable Inputs
TRI·STATE Outputs
Description
SCAN 182374ASSC
SSOP in Tubes
SCAN 182374ASSCX
SSOP in Tape and Reel
SCAN 182374AFMQB
Flatpak Military
H -GND
33 -Bls
32 -B17
31 -BCP
B06 -
AO(0-8), BO(0-8)
41 -BII
40 -GND
B02 B03 -
B05 - 22
GND- 23
Pin Names
AI(0-8), BI(0-8)
ACP, BCP
AOE1, BC5E 1
TL/F/11545-1
9·31
http://www.national.com
Truth Tables
Functional Description
Inputs
AO(0-8)
ACP
tAOE1
AI(0-8)
X
....r
....r
H
L
L
X
L
H
BCP
tBOE 1
BICO-8)
X
H
L
L
X
L
H
Inputs
....r
....r
H
L
X
The SCAN182374A consists of two sets of nine edge-triggered flip-flops with individual Ootype inputs and TRI-STATE
true outputs. The buffered clock and buffered Output Enable pins are common to all flip-flops. Each set of the nine
flip-flops will store the state of their individual 0 inputs that
meet the setup and hold time requirements on the LOW-toHIGH Clock (ACP or BCP) transition. With the Output Enable (AOE1 or BOE1) LOW, the contents of the nine flipflops are available at the outputs. When the Output Enable
is HIGH, the outputs go to the high impedance state. Operation of the Output Enable input does not affect the state of
the flip-flops.
Z
L
H
BO(0-8)
Z
L
H
= HIGH Voltage Level
= LOW Voltage Level
= Immaterial
Z = High Impedance
.../ = L-to-H Transition
t
= Inactive-te-active transition must occur to
enable outputs upon power-up.
Logic Diagram
TL/F/11545-2
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
TYPE1
TYPE2
ACP
AI [o-a]
TL/F/II545-3
Note: BSR stands for Boundary Scan Register
http://www.national.com
9-32
Block Diagrams (Continued)
Tap Controller
_---"'I
rROt.4 8SR[O]
TOI
TOO
INSTRUCTION TRI-STATE
TMS
TCK
TL/F111545-4
Byte-B
TL/F/11545-5
Note: BSR stands for BOUNDARY·SCAN Register
9·33
http://www.national.com
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Agure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
The INSTRUCTION register is an a-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required to
shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR ~ EXIT1-IR ~ UPDATE-IR
will update the SAMPLE/PRELOAD instruction. For more
information refer to the section on instruction definitions.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
Instruction Register Sscan Chain Definition
TDI
TOO
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
MSB
LSB
Bypass Register Scan Chain Definition
Logic 0
TLlF/11545-28
MSB
Instruction Code
~
LSB
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGH-Z
TL/F111545-27
SCAN 182374A Product IDCODE
(32-Blt Code per IEEE 1149.1)
Version Entity
0000
Per
Number
Manufacturer Required
10
by 1149.1
111111 0000000111 00000001111
MSB
http://www.national.com
1
LSB
9-34
01000001
SAMPLE-IN
01000010
SAMPLE-OUT
00100010
EXTEST-OUT
10101010
IDCODE
11111111
BYPASS
All Other
BYPASS
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , -4
co
N
W
Description of BOUNDARY-SCAN Circuitry (Continued)
.......
.a:.
l>
Scan Cell TYPE1
SCAN OUT
(to next cell)
DATA
IN--------,---------------------------------+------------DATAOUT
SHIFLDR
----+--4
SCAN IN
(from previous cell)
TL/F/11545-19
Scan Cell TYPE2
SCAN OUT
(to next cell)
MODE - - - - - - - 4
DATAIN------~--------------------------------~------------------~
DATA OUT
SHIFT _DR
---+---1
SCAN IN
CLOCK-DR
(from previous cell)
TL/F/11545-20
9-35
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
SCAN182374A Scan Chain Definition (42 Bits In Length)
TOI
41
40
39
38
37
TOO
36
35
18
17
34
19
16
33
20
15
32
21
14
31
22
13
30
23
12
29
24
11
28
25
10
27
26
TlIF/11545-26
http://www.national.com
9-36
Description of BOUNDARY-SCAN Circuitry (Continued)
Input BOUNDARY·SCAN Register
Scan Chain Definition (22 Bits In Length)
When Sample In Is Active
TDI
41
40
38
37
TDO
35
18
34
19
33
20
32
21
31
22
30
23
29
24
28
25
27
26
TL/F/11545-29
9-37
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
Output BOUNDARY-SCAN Register
Scan Chain Definition (20 Bits In Length)
When Sample Out and EXTEST Out are Active
TOI
39
TOO
36
17
16
15
14
13
12
11
10
TL/F/11S4S-30
http://www.national.com
9-38
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY·SCAN Register Definition Index
Pin No.
Pin Type
41
40
39
38
37
36
AOE1
ACP
AOE
BOE1
BCP
BOE
3
54
Input
Input
Internal
Input
Input
Internal
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
Control
Signals
35
34
33
32
31
30
29
28
27
Alo
AI1
AI2
AI3
AI4
Ais
AI6
AI7
Ala
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A-in
26
25
24
23
22
21
20
19
18
Blo
BI1
BI2
BI3
BI4
Bis
BI6
BI7
Bla
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B-in
17
16
15
14
13
12
11
10
9
AOo
A01
A02
A03
A04
AOs
A06
A07
AOa
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A-out
8
7
6
5
4
3
2
1
0
BOo
B01
B02
B03
B04
BOs
B06
B07
BOa
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B-out
Bit No.
Pin Name
26
31
9·39
Scan Cell Type
http://www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Latchup Source Current
Commercial
Military
Storage Temperature
- 65°C to + 150°C
Over Voltage Latchup (I/O)
Ambient Temperature under Bias
- 55°C to + 125°C
Junction Temperature under Bias
Ceramic
Plastic
- 55°C to + 175°C
- 55°C to + 150°C
ESD (HBM) Min.
2000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Vee Pin Potential to
Ground Pin
-0.5Vto +7.0V
Input Voltage (Note 2)
-0.5Vto +7.0V
Input Current (Note 2)
-30 rnA to +5.0 rnA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
-500mA
-300 rnA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
-0.5V to + 5.5V
-0.5VtoVee
- 55°C to + 125°C
-40°C to + 85°C
Supply Voltage
Military
Commercial
Twice the Rated IOl (rnA)
+ 4.5V to + 5.5V
+ 4.5V to + 5.5V
Minimum Input Edge Rate
Data Input
Enable Input
(dV/dt)
50 mV/ns
20 mV/ns
DC Electrical Characteristics
Symbol
Vee
Parameter
Min
VIH
Input HIGH Voltage
Vil
Input LOW Voltage
Veo
Input Clamp Diode Voltage
Min
VOH
Output HIGH Voltage
Min
2.5
VOL
IIH
Typ
Max
Units
Conditions
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
-1.2
V
liN
V
IOH = -3mA
2.0
=
-18 mA
Mil
Min
2.0
V
IOH
Comm
Min
2.0
V
IOH
=
=
Mil
Min
0.8
V
IOl
= 12mA
Comm
Min
0.8
V
IOl = 15mA
-24mA
-32.mA
Output LOW Voltage
Input HIGH Current
All Others
TMS, TDI
5
pA
VIN
5
IlA
VIN = Vee
Max
5
Il A
VIN = Vee
IBVI
Input HIGH Current
Breakdown Test
Max
7
IlA
IBVIT
Input HIGH Current
Breakdown Test(I/O)
Max
100
Il A
IlL
Input LOW Current
All Others
TMS, TDI
= 2.7V (Note 1)
Max
Max
VIN
= 7.0V
VIN
=
= 0.5V (Note 1)
= O.OV
= O.OV
Max
-5
IlA
VIN
Max
-5
IlA
VIN
Max
-385
IlA
VIN
110 = 1.91lA
All Other Pins Grounded
VIO
Input Leakage Test
IIH + IOZH
Output Leakage Current
Max
50
IlA
VOUT
IlL + IOZl
Output Leakage Current
Max
-50
IlA
VOUT
0.0
4.75
V
IOZH
Output Leakage Current
Max
50
Il A
IOZl
Output Leakage Current
Max
-50
pA
Note 1: Guaranteed not tested.
http://www.national.com
9-40
5.5V
= 2.7V
= 0.5V
VOUT = 2.7V
VOUT = 0.5V
DC Electrical Characteristics (Continued)
Vee
Min
los
Output Short·Circuit Current
Max
-100
ICEX
Output High Leakage Current
Max
Izz
Bus Drainage Test
ICCH
Power Supply Current
Symbol
ICCl
Parameter
Power Supply Current
Iccz
Power Supply Current
ICCT
Additionallccllnput
ICCD
Dynamic Icc
Typ
Max
Units
-275
mA
VOUT
= O.OV
50
,..,A
VOUT
= Vcc
0.0
100
,..,A
VOUT = 5.5V
All Others Grounded
Max
250
,..,A
VOUT
= Vcc; TDI, TMS = Vcc
Max
1.0
rnA
VOUT
= Vcc; TDI, TMS = GND
Max
65
rnA
VOUT
= LOW; TDI, TMS = Vcc
Max
65.8
rnA
VOUT
= LOW; TDI, TMS
Max
250
,..,A
TDI, TMS
= Vcc
= GND
Max
1.0
rnA
TDI, TMS
Max
2.9
rnA
VIN
= Vcc - 2.1V
TDI, TMS Inputs
Max
3
rnA
VIN
= Vcc - 2.1V
mAl
Outputs Open
One Bit Toggling, 50% Duty Cycle
No Load
0.2
Max
MHz
See Section 4
Military
Parameter
Vee·
(V)
TA
Propagation Delay
CPtoQ
tpLZ
tpHZ
Disable Time
tPZl
tPZH
Enable Time
Commercial
= -55°C to + 125°C
CL = 50pF
Typ
Max
TA = -40°C to +85°C
CL = 50 pF
Units
Fig.
No.
Min
Typ
Max
5.0
1.4
2.1
4.6
4.9
6.1
6.8
ns
4·1,2
5.0
1.9
1.8
4.6
4.8
8.0
8.7
ns
4·3,4
5.0
2.0
1.4
6.7
6.0
9.4
8.2
ns
4·3,4
Min
tpLH
tpHl
= GND
All Other Inputs
AC Electrical Characteristics Normal Operation:
Symbol
Conditions
·Voltage Range S.OV ±O.SV
AC Operating ReqUirements
NormalOperation: See Section 4
Military
Symbol
Parameter
Vee·
(V)
TA
= -55°C to + 125°C
CL = 50pF
Commercial
TA = -40°C to + 85°C
CL = 50 pF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, H or L
Data to CP
5.0
2.8
ns
4·5
tH
Hold Time, H or L
CPto Data
5.0
2.4
ns
4·5
tw
CP Pulse Width
5.0
0.0
ns
4·2
f max
Maximum ACP/BCP
Clock Frequency
5.0
50
MHz
·Voltage Range S.O is 5.0V ±O.SV.
9·41
http://www.national.com
AC Electrical Characteristics Scan Test Operation:
See Section 4
Military
Symbol
Parameter
Vcc·
(V)
TA
=
Commercial
-55°C to + 125°C
CL = 50 pF
=
-40°C to +85°C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
5.0
2.9
4.0
5.8
7.3
9.5
11.5
ns
4-8
Disable Time
TCKto TDO
5.0
1.9
3.0
5.6
7.1
10.0
12.1
ns
4-9,10
tPZL
tpZH
Enable Time
TCKtoTDO
5.0
4.4
2.7
8.4
6.4
13.2
10.9
ns
4-9,10
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
3.4
4.3
6.5
8.1
10.5
12.7
ns
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Update-IR State
5.0
3.9
4.7
7.8
9.1
12.8
14.5
ns
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
4.7
5.6
9.5
10.9
15.6
17.4
ns
5.0
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Update-DR State
5.0
3.2
3.9
7.8
8.5
13.6
14.2
ns
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Update-IR State
5.0
3.2
3.8
8.6
9.3
15.0
15.6
ns
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Test Logic
Reset State
4.2
5.0
10.2
11.0
18.0
18.5
ns
5.0
tpZL
tpZH
Enable Time
TCK to Data Out
during Update-DR State
5.0
5.0
3.7
9.6
7.7
15.3
13.0
ns
tpZL
tpZH
Enable Time
TCK to Data Out
during Update-IR State
5.0
5.3
4.0
10.8
9.0
17.4
15.1
ns
tPZL
tPZH
Enable Time
TCK to Data Out
during Test Logic
Reset State
6.2
4.7
12.6
10.7
20.4
18.1
ns
Min
tpLH
tpHL
Propagation Delay
TCKtoTDO
tpLZ
tpHZ
Typ
TA
Max
5.0
·Voltage Range 5.0V ±O.5V
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9-42
4-8
4-8
4-8
4-9,10
4-9,10
4-9,10
4-9,10
4-9,10
4-9,10
AC Operating Requirements Scan Test Operation:
See Section 4
Military
Vcc·
(V)
Parameter
Symbol
TA
=
-55°C to + 125°C
CL = 50pF
Commercial
TA
=
-40°C to +85°C
CL = 50pF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time
Data to TCK (Note 2)
5.0
2.7
ns
4-11
tH
Hold Time
Data to TCK (Note 2)
5.0
3.1
ns
4-11
ts
Setup Time, H or L
AOE1, BOEl to TCK (Note 1)
5.0
5.0
ns
4-11
tH
Hold Time, H or L
TCK to AOE1, BOEl (Note 1)
5.0
1.8
ns
4-11
ts
Setup Time, H or L
Internal AOE, BOE to TCK (Note 3)
5.0
3.6
ns
4-11
tH
Hold Time, H or L
TCK to Internal AOE, BOE (Note 3)
5.0
2.1
ns
4-11
ts
Setup Time
ACP, BCP (Note 4) to TCK
5.0
3.4
ns
4-11
tH
Hold Time
TCK to ACP, BCP (Note 4)
5.0
1.8
ns
4-11
ts
Setup Time, H or L
TMStoTCK
5.0
8.7
ns
4-11
tH
Hold Time, H or L
TCKtoTMS
5.0
1.8
ns
4-11
ts
Setup Time, H or L
TDI toTCK
5.0
6.4
ns
4-11
tH
Hold Time, H or L
TCKtoTDI
5.0
3.2
ns
4-11
tw
Pulse Width TCK
5.0
8.2
11.2
ns
4-12
H
L
f max
MaximumTCK
Clock Frequency
5.0
50
MHz
tpu
Wait Time, Power Up to TCK
5.0
100
ns
tON
Power Down Delay
0.0
100
ms
·Voltage Range 5.0V ±0.5V
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: Timing pertains to BSR 38 and 41 only.
Note 2: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.
Note 3: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 4: Timing pertains to BSR 37 and 40 only.
Capacitance T A = 25°C
Symbol
CIN
COUT (Note 1)
Note 1: COUT is measured at frequency f
Typ
Units
Input Capacitance
5.8
pF
Vee
Output Capacitance
13.8
pF
Vee
Parameter
Conditions
= O.OV
= 5.0V
= 1 MHz, per MIL-STD-883B, Method 3012.
9-43
http://www.national.com
<
.....
~
t!lNational Semiconductor
SCAN182541A
Non-Inverting Line Driver with
250, Series Resistor Outputs
General Description
Features
The SCAN182541A is a high performance BiCMOS line
driver featuring separate data inputs organized into dual
9-bit bytes with byte-oriented paired output enable control
signals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary-Scan architecture with the
incorporation of the defined Boundary-Scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TOO), Test Mode Select (TMS), and Test Clock
(TCK).
• IEEE 1149.1 (JTAG) Compliant
• High performance BiCMOS technology
• 250 series resistor outputs eliminate need for external
terminating resistors
• Dual output enable signals per byte
• TRI-STATE® outputs for bus-oriented applications
• 25 mil pitch SSOP (Shrink Small Outline Package)
• Includes CLAMP, IDCODE and HIGHZ instructions
• Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
• Power up TRI-STATE for hot insert
• Member of National's SCAN Products
Ordering Code: See Section 11
Connection Diagram
Tt.lS- 1
AOo- 2
AO~-
3
Ao,- 4
A02 - 5
GND- 6
\.J
56 rTDI
551-Alo
541-AOE2
531-Al1
521-AI 2
511-GND
A03 - 7
AO,- 8
50 rAI3
Vcc - 9
AOs- 10
48 I-Vcc
AOs- 11
46 I-Als
Order Number
47 rAls
451-GND
Ao,- 13
44 rAI7
Description
Input Pins, A Side
Input Pins, B Side
TRI-STATE Output Enable Input Pins, A Side
TRI-STATE Output Enable Input Pins, B Side
Output Pins, A Side
Output Pins, B Side
Description
SCAN 182541 ASSC
SCAN 182541 ASSCX
SCAN 182541 AFMQB
49 I-AI,
GND- 12
Pin Names
AI(O-S)
~S)_
AOE1,AOE2
BOE1, BOE2
AO(O-S)
BO(O-S)
SSOP in Tubes
SSOP in Tape and Reel
Flatpak Military
Truth Tables
Inputs
AOs- 14
431- Als
BOo - 15
Bo,- 16
421-810
tAOE1
tAOE2
AI(O-S)
41 rBll
GND- 17
40l-GND
B02 B03 -
18
391-B12
381- BI3
L
H
X
L
L
X
H
L
H
X
X
L
Vcc BO, -
20
37 rVcc
21
361-BI,
BOs -
22
351-BI s
tBOE1
tBOE2
BI(O-S)
L
H
X
L
L
X
H
L
H
X
X
L
19
GND- 23
341-GND
BOs - 24
Bo,- 25
331- BIs
BO~-
26
BOs - 27
TDO- 28
AO(O-S)
Inputs
321-BI7
311-BOE2
30l-BIs
H
L
291-TCK
TlIF/11543-1
H
Z
Z
L
BO(O-S)
= HIGH Voltage Level
= LOW Voltage Level
X = Immaterial
Z
t
= High Impedance
= Inactive·to-active transition must occur
to enable outputs upon power-up.
http://www.national.com
H
Z
Z
L
9-44
Block Diagrams
Byte A
TYPE1
AI [o-a]
TLlF/11543-2
Tap Controller
TO BSR [41]
FROM BSR [0]
TOI
TOO
INSTRUCTION TRI-STATE
TMS
TCK
TL/F/11543-3
ByteB
TYPE2
TYPE1
BI [o-a]
BO [o-a]
TL/F/11543-4
Note: BSR stands for Boundary Scan Register.
9·45
http://www.national.com
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required to
shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR ~ EXIT1-IR ~ UPDATE-IR will
update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
Instruction Register Scan Chain Definition
TDI
TOO
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
~SB
LSB
TL/F/11543-26
Bypass Register Scan Chain Definition
Logic 0
MSB~LSB
Instruction Code
00000000
10000001
10000010
00000011
01000001
01000010
00100010
10101010
11111111
All Others
TL/F/11543-17
SCAN182541A Product IDCODE
(32-Blt Code per IEEE 1149.1)
LSB
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGH-Z
SAMPLE-IN
SAMPLE-OUT
EXTEST-OUT
IDCODE
BYPASS
BYPASS
Scan Cell TVPE1
SCAN OUT
(to next cell)
DATA IN
---,.-------------+-----
DATA OUT
SHIFLDR - - - - I -.....
SCAN IN
CLOCK-DR
(from previous cell)
TLIF111543-30
Scan Cell TVPE2
SCAN OUT
(to next cell)
M O D E - - - -.....
DATA I N - - . . . . , - - - - - - - - - - - - - - + - - - - - - - - - - t
DATA OUT
SHIFLDR - - - + - - t
SCAN IN
CLOCK-DR
UPDATE.DR
(from previous cell)
http://www.national.com
TL/F/11543-31
9-46
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY·SCAN Register
Scan Chain Definition (42 Bits In Length)
TDI
41
40
39
38
37
TDO
36
35
18
17
34
19
16
33
20
15
32
21
14
31
22
13
30
23
12
29
24
11
28
25
10
27
26
TL/F/11543-27
9·47
http://www.national.com
•
c:r:
....
~
Description of BOUNDARY-SCAN Circuitry (Continued)
N
....co
Input BOUNDARY-SCAN Register
Scan Chain Definition (22 Bits In Length)
When SAMPLE-IN Is Active
TDI
41
40
P26
TYPE1
38
37
TOO
P55
TYPE1
35
18
34
19
33
20
32
21
31
22
30
23
29
24
28
25
27
26
TLlF/11543-28
http://www.national.com
9·48
.....
co
N
C1I
Description of BOUNDARY-SCAN Circuitry (Continued)
~
.....
l>
Output BOUNDARY-SCAN Register
Scan Chain Definition (20 Bits In Length)
When SAMPLE-OUT and EXTEXT Out are Active
TDI
TYPE2
39
TYPE2
TDO
36
17
16
15
14
13
12
11
10
TL/F/11543-29
9-49
http://www.national.com
•
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index
Bit No.
Pin Name
PinNa.
Pin Type
3
54
Input
Input
Internal
Input
Input
Internal
TYPE1
TYPE1
TYPE2
TYPE1
TYPE1
TYPE2
Control
Signals
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A-in
Blo
BI1
BI2
BI3
BI4
Bis
Bis
BI7
Bla
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B-in
17
16
15
14
13
12
11
10
9
AOo
A01
A02
A03
A04
AOs
AOs
A07
AOa
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A-out
8
7
6
5
4
3
2
1
0
BOo
B01
B02
B03
B04
BOs
BOs
B07
BOa
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B-out
41
40
39
38
37
36
AOE1
AOE2
AOE
BOE1
BOE2
BOE
35
34
33
32
31
30
29
28
27
Ala
AI1
AI2
AI3
AI4
Ais
Ais
AI7
Ala
26
25
24
23
22
21
20
19
18
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26
31
9-50
Scan Cell Type
Absolute Maximum Ratings
(Note 1)
Over Voltage Latchup (1/0)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
- 65°C to + 150°C
Ambient Temperature under Bias
- 55°C to + 125°C
Junction Temperature under Bias
Ceramic
Plastic
- 55°C to + 175°C
- 55°C to + 150°C
Vee Pin Potential to
Ground Pin
-0.5V to + 7.0V
Input Voltage (Note 2)
-0.5V to + 7.0V
Input Current (Note 2)
-30 rnA to +5.0 rnA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
2000V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
- 0.5V to + 5.5V
-0.5VtoVee
- 55°C to + 125°C
- 40°C to + 85°C
+ 4.5V to + 5.5V
+ 4.5V to + 5.5V
Minimum Input Edge Rate
Data Input
Enable Input
Twice the Rated 10L (mA)
DC Latchup Source Current
Commercial
Military
10V
EDS (HBM) Min
(6. V /6.t)
50 mV/ns
20 mV/ns
-500 mA
-300 mA
DC Electrical Characteristics
Symbol
Vee
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Veo
Input Clamp Diode Voltage
Min
VOH
Output HIGH Voltage
Min
VOL
Output LOW Voltage
IIH
Input HIGH Current
Min
Typ
Max
Units
Conditions
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
-1.2
V
liN = -18 mA
V
10H = -3mA
10H = -24mA
2.0
2.5
Mil
Min
2.0
V
Comm
Min
2.0
V
10H = -32mA
Mil
Min
0.8
V
10L = 12mA
Comm
All Others
TMS, TDI
Min
0.8
V
Max
5
p.A
VIN = 2.7V (Note 1)
Max
5
p.A
VIN = Vee
Max
5
p.A
10L = 1SmA
VIN = Vee
IBVI
Input HIGH Current
Breakdown Test
Max
7
p.A
IBVIT
Input HIGH Current
Breakdown Test (110)
Max
100
p.A
IlL
Input LOW Current
Max
-5
p.A
VIN = O.5V (Note 1)
Max
-5
p.A
VIN = O.OV
Max
-385
p.A
VIN = O.OV
All Others
TMS, TDI
VIO
Input Leakage Test
0.0
4.75
V
VIN = 7.0V
VIN = 5.5V
110 = 1.9 J-LA
All Other Pins Grounded
IIH + 10ZH
Output Leakage Current
Max
50
p.A
VOUT = 2.7V
IlL + LOZL
Output Leakage Current
Max
-50
p.A
VOUT = 0.5V
10ZH
Output Leakage Current
Max
50
p.A
VOUT = 2.7V
10ZL
Output Leakage Current
Max
-50
p.A
VOUT = 0.5V
los
Output Short-Circuit Current
Max
-275
mA
VOUT = O.OV
-100
Note 1: Guaranteed not tested.
9-51
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DC Electrical Characteristics (Continued)
Symbol
Parameter
Vee
Max
ICEX
Output HIGH Leakage Current
Izz
Bus Drainage Test
ICCH
Power Supply Current
Icel
Power Supply Current
Icez
Power Supply Current
ICCT
Additionallee/lnput
IceD
Dynamic lee
Min
Typ
Max
Units
Conditions
50
p,A
VOUT
VOUT = 5.5V
All Others Grounded
=
Vec
0.0
100
p,A
Max
250
p,A
VOUT
Max
1.0
mA
VOUT
Max
65
mA
VOUT
Max
65.8
mA
VOUT
Max
250
p,A
TDI, TMS
=
=
Vee; TDI, TMS
=
=
LOW; TDI, TMS
Vec; TDI, TMS
LOW; TDI, TMS
=
=
=
=
=
=
Vee
GND
Vee
GND
Vee
Max
1.0
mA
TDI, TMS
All Other Inputs
Max
2.9
mA
VIN
=
Vee - 2.1V
TDI, TMS Inputs
Max
3
mA
VIN
=
Vee - 2.1V
0.2
mAl
MHz
Outputs Open
One Bit Toggling, 50% Duty Cycle
No Load
Max
GND
Note 1: Guaranteed not tested.
AC Electrical Characteristics NormalOperation:
Symbol
Parameter
Vee"
(V)
Military
Commercial
TA = -55°C to + 125°C
CL = 50pF
TA = -40°C to + 85°C
CL = 50 pF
Min
tplH
tpHl
Propagation Delay
Data toO
tplZ
tpHZ
Disable Time
tpZl
tPZH
Enable Time
Typ
Max
Units
Fig.
No.
Min
Typ
Max
5.0
1.0
1.9
3.4
4.1
5.2
6.5
ns
4-1
5.0
2.0
1.9
5.2
5.6
8.7
9.2
ns
4-3,4
5.0
2.4
1.6
6.1
5.1
9.6
8.5
ns
4-3,4
'Voltage Range 5.0V ±O.5V
http://www.national.com
See Section 4
9-52
AC Electrical Characteristics Scan Test Operation:
See Section 4
Commercial
Military
Symbol
Parameter
Vee·
(V)
TA
= -55°C to + 125°C
CL = 50 pF
TA
= -40°C to +85°C
CL = 50 pF
Units
Fig.
No.
Min
Typ
Max
5.0
3.2
4.5
6.0
7.6
9.4
11.3
ns
4-8
Disable Time
TCKto TDO
5.0
2.5
3.7
5.8
7.4
9.9
11.8
ns
4-9,10
tpZL
tPZH
Enable Time
TCKtoTDO
5.0
4.9
3.1
8.6
6.7
12.9
10.7
ns
4-9,10
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
3.7
4.9
6.7
8.3
10.3
12.4
ns
4-8
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Update-IR State
5.0
4.2
5.3
7.9
9.2
12.2
13.8
ns
4-8
tpLH
tpHL
Propagation Delay
TCK to Data Out
during Test Logic Reset State
5.0
5.0
6.2
9.4
10.9
14.6
16.4
ns
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Update-DR State
5.0
3.7
4.3
7.9
8.7
13.0
13.7
ns
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Update-IR State
5.0
3.7
4.3
8.5
9.4
14.2
14.8
ns
tpLZ
tpHZ
Disable Time
TCK to Data Out
during Test Logic Reset State
5.0
4.7
5.5
10.1
10.9
16.6
17.3
ns
tPZL
tPZH
Enable Time
TCK to Data Out
during Update-DR State
5.0
5.5
4.0
9.8
7.9
14.7
12.5
ns
tPZL
tPZH
Enable Time
TCK to Data Out
during Update-IR State
5.0
5.8
4.3
10.9
9.0
16.5
14.4
ns
tPZL
tPZH
Enable Time
TCK to Data Out
during Test Logic Reset State
5.0
6.6
4.9
12.5
10.5
19.1
16.9
ns
Min
tpLH
tpHL
Propagation Delay
TCKtoTDO
tpLZ
tpHZ
Typ
Max
4-8
4-9,10
4-9,10
4-9,10
4-9,10
4-9,10
4-9,10
·Voltage Range 5.0V ± O.5V
•
9-53
http://www.national.com
«
,....
~
II)
AC Operating Requirements Scan Test Operation:
See Section 4
N
co
,....
Military
Symbol
Vcc·
(V)
Parameter
TA
= -55°C to + 125°C
CL = 50pF
Commercial
TA
= -40°C to + 85°C
CL = 50pF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time
Data to TCK (Note 2)
5.0
2.2
ns
4-11
tH
Hold Time
Data to TCK (Note 2)
5.0
1.8
ns
4-11
Setup Time, H or L
BOEn to TCK (Note 1)
5.0
3.7
ns
4-11
tH
Hold Time, H or L
TCK to ACEn , BOEn (Note 1)
5.0
1.8
ns
4-11
ts
Setup Time, H or L
Internal AOE n , BOEn ,
to TCK (Note 3)
5.0
2.7
ns
4-11
Hold Time, H or L
TCK to Internal
AOE n , BOE n (Note 3)
5.0
1.8
ns
4-11
ts
Setup Time, H or L
TMStoTCK
5.0
7.5
ns
4-11
tH
Hold Time, H or L
TCKto TMS
5.0
1.8
ns
4-11
ts
Setup Time, H or L
TDI toTCK
5.0
5.0
ns
4-11
tH
Hold Time, H or L
TCKto TDI
5.0
2.0
ns
4-11
tw
Pulse Width TCK
5.0
10.0
10.8
ns
4-12
fmax
MaximumTCK
Clock Frequency
5.0
50
MHz
tpu
Wait Time, Power Up to TCK
5.0
100
ns
tON
Power Down Delay
0.0
100
ms
ts
ADEn,
tH
H
L
'Voltage Range 5.0V ±0.5V
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: Timing pertains to BSR 38 and 41 or BSR 37 and 40.
Note 2: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.
Note 3: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Capacitance
Symbol
Parameter
= 25°C
Typ
Units
CIN
Input Capacitance
5.8
pF
Vee = O.OV
COUT (Note 1)
Output Capacitance
13.8
pF
Vee = 5.0V
Note 1: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
http://www.national.com
9-54
Conditions, T A
Section 10
System Test Support
Datasheets
http://www.national.com
Section 10 Contents
SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support) ..............
SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
(IEEE 1149.1 System Test Support). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCAN EASE SCAN Embedded Application Software Enabler ............................
10-2
10-3
10-26
10-54
"0
tJ)
o.......
I!fINational Semiconductor
o
o
"T1
SCANPSC100F
Embedded Boundary Scan Controller
(IEEE 1149.1 Support)
General Description
Features
The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in
improving scan throughput when applying serial vectors to
system test circuitry and reduces the software overhead
that is associated with applying serial patterns with a parallel processor. The 'PSC100F operates by serializing data
from the parallel bus for shifting through the chain of 1149.1
compliant components (Le., scan chain). Scan data returning from the scan chain is placed on the parallel port to be
read by the host processor. Up to two scan chains can be
directly controlled with the 'PSC100F via two independent
TMS pins. Scan control is supplied with user specific patterns which makes the 'PSC100F protocol-independent.
Overflow and underflow conditions are prevented by stopping the test clock. A 32-bit counter is used to program the
number of TCK cycles required to complete a scan operation within the boundary scan chain or to complete a
'PSC100F
Built-In
Self
Test
(BISn
operation.
SCANPSC100F device drivers and 1149.1 embedded test
application code are available with National's SCAN Ease
software tools.
• Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
• Supported by National's SCAN Ease (Embedded Application Software Enabler) Software
a Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK
frequencies
• Directly supports up to two 1149.1 scan chains
a 16-bit Serial Signature Compaction (SSG) at the Test
Data In (TDI) port
• Automatically produces pseudo-random patterns at the
Test Data Out (TOO) port
• Fabricated on FACTTM 1.5 J.lm CMOS process
• Supports 1149.1 test clock (TCK) frequencies up to
25 MHz
• TTL-compatible inputs; full-swing CMOS outputs with
24 mA source/sink capability
Ordering Code: See Section 11
Connection Diagrams
Pin Assignment
forLCC
28-Pln SOIC, DIP and Flatpak
RST- 1
SCK- 2
\.J
28 rVee
'1
271-FRZ
[j) !I~l[il
0E-3
26 rTDI
cr--4
251-TCK
GNO [j] ~
ST8- 6
23 rTMSO
04 @) ~
AO- 7
221-GNO
05 !ill ~
06 !iII ~
A2- 9
20 I-ROY
00- 10
19 rlNT
01- 11
181-07
02- 12
17 r06
03- 13
161-05
GNO- 1-4
15 rO-4
STB R/W
.....................
2-4I-TMSI
21 rTDO
Ao
mmliW]
021I11~
03 Ii] ~
R/W- 5
Al- 8
Do A2 A,
~mcr
•
•
~ [J] RST
~ ~ Vee
• Ill! FRZ
• 1m TOI
~ 1m ~
"
!Il DE
mSCK
III II1II II1II II1II II1II II1II II1II.
!iID~IilIUlI~H~~
ROY GNO TM TM TCK
INT
TOO
SO SI
TL/F/l0968-18
TLlF/l0968-1
10-3
Order Number
Description
SCANPSC100FSC
SCANPSC100FSCX
SCANPSC100FFMQB
SCANPSC100FDMQB
SCANPSC100FLMQB
5962·9475001 QYA
5962·9475001QXA
5962-9475001Q3A
SOIC in Tubes
SOIC in Tape and Reel
Military Fiatpak
Military Ceramic DIP
Military Leadless Chip Carrier
Military SMD#, Flatpak
Military SMD#, CDIP
Military SMD#, LCC
http://www.national.com
U.
Q
Q
....
o
U)
A.
Chip Architecture
The 'PSC100 is designed to act together with a parallel bus
host as a serial test bus master. Parallel data is written by
the host to the 'PSC100, which serializes the data for application to a serial test bus. Serial data returning from the
target scan chain(s) is placed on the processor port for parallel reads. Several features are included in the 'PSC100
which make scan test communication more convenient and
efficient.
Test Data In (TDI) receives serial data from the scan chain.
A local control block is associated with each Shifter/Buffer
to provide shift and load control as well as providing full or
empty status. The SSI also provides Test Clock (TCK) Control. TCK is stopped and started depending on the status of
the Shifter/Buffers or the 32-bit Counter. By stopping and
starting TCK, scan operations will proceed only when the
enabled Shifter/Buffers are ready to send and/or receive
serial data.
Figure 1 shows the major functional blocks of the 'PSC100
design. The Parallel Processor Interface (PPI) is an asynchronous, a-bit parallel interface which is used by the host
processor to write and read data. The PPI generates the
necessary internal data, address, and control signals to
complete internal write and read operations.
The 32-bit Counter (CNT32) is a count-down binary counter
included to assist in controlling the SSI. The initial state of
CNT32 is loaded from the parallel port with four consecutive
writes to its address. When enabled, CNT32 is used to program the number of TCKs applied by the SSI to the boundary scan chain(s). The value of CNT32 can also be used to
generate interrupts (Le., when CNT32 reaches terminal
count) and to trigger 'PSC1 00 features, such as, Auto TMS
High (discussed later within this datasheet).
The Serial Scan Interface (SSI) consists of a bank of double-buffered parallel/serial shift registers (Le., a 2 x a bit
FIFO), or Shifter/Buffers. The double buffering improves efficiency by allowing parallel writes or reads to/from one of
the two a-bit FIFOs within the shifter/buffer while the other
FIFO is shifting data to/from the scan chain. Three Shifter/
Buffers are provided for outgoing serial data and one for
incoming serial data. Test Data Out (TOO) is for scanning
out test data while the two Test Mode Select signals
(TMSO/1) are used to provide user specific control data.
The Mode and Status Registers are used to control and
observe the operation of the SSI and CNT32. Each of the
Shifter/Buffers and CNT32 have an associated mode bit
which enables it for participation in on-going operations.
Status bits can be used for polling operations.
Serial Scan Interface
0(7:0)
TOO
Sh ifter/Buffer
Read/Write
Latches
A(2:0)
CE
STB
R/W
SCK
RST
ROY
INT
Synchronizer
and
READ/WRITE
Control
TOI
Shifter/Buffer
TOI
Tt.4S0
Shifter/Buffer
Tt.4S0
Tt.4S1
Sh ifter /Buffer
t.4ode/Status Registers
TCK
32-bit Counter
I
I
·------------l------f------FRZ
DE
TLIF 110968-2
FIGURE 1. 'PSC100 Block Diagram
http://www.national.com
10-4
"'D
en
o
Pin Descriptions
~
Pin
Name
o
o
-n
Description
RST(lnput)
The Reset pin is an asynchronous input that, when low, initializes the 'PSC1 00. Mode bits, Shifter/Buffer and
CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis for
improved noise immunity.
SCK (Input)
The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK. SCK
has hysteresis for improved immunity.
OE (Input)
Output Enable TRI-STATEs all SSI outputs when high. A 20 kn pull-up resistor is connected to automatically
TRI-STATE@ these outputs when this signal is floating.
CE (Input)
Chip Enable, when low, enables the PPI for byte transfers. D(7:0) and RDY are TRI-STATEd if CE is high. CE
has hysteresis for improved noise immunity.
R/W(lnput)
Read/Write defines a PPI cycle-Read when high, Write when low. R/W has hysteresis for improved noise
immunity.
STB (Input)
Strobe is used for timing all PPI byte transfers. D(7:0) are TRI-STATEd when STB is high. All other PPI inputs
must meet specified setup and hold times with respect to this signal. STB has hysteresis for improved noise
immunity.
A(2:0)
(Input)
The Address pins are used to select the register to be written to or read from.
D(7:0) (I/O)
Bidirectional pins used to transfer parallel data to and from the 'PSC1 00.
INT
(Output)
Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active high.
RDY
(TRI-STATE
Output)
Ready is used to synchronize asynchronous byte transfers between the host and the 'PSC100. When low,
RDY signals that the addressed register is ready to be accessed RDY is enabled when CE is low.
TDO
(TRI-STATE
Output)
Test Data Out is the serial scan output from the 'PSC100. TDO is enabled when OE is low.
TMS(1:0)
(TRI-STATE
Output)
The Test Mode Select pins are serial outputs used to supply control logic to the UUT. TMS(1:0) are enabled
when OE is low.
TCK
(TRI-STATE
Output)
The Test Clock output is a buffered version of SCK for distribution in the UUT. TCK Control logic starts and
stops TCK to prevent overflow and underflow conditions. TCK is enabled when OE is low.
TDI (Input)
Test Data In is the serial scan input to the 'PSC100. A 20 kn pull-up resistor is connected to force TDI to a
logic 1 when the TDO line from the UUT is floating.
FRZ (Input)
The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode bit is
set, TCK will be forced high if FRZ goes high. FRZ has hysteresis for improved noise immunity.
10-5
http://www.national.com
LL
0
0
.....
Mode and Status Registers
U)
MODE REGISTER 0 (MOD EO)
0
a.
Blt6
Blt7
TOO
Enable
TOI
Enable
Bit 5
BIt4
CNT32
Enable
Blt3
TMSO
Enable
TMS1
Enable
This register is purely a mode register. All bits are writeable
and readable. The value 00100000 is placed in this register
upon RST low or a synchronous reset operation.
• Bit 7:
• Bit 6:
• Bit 5:
Blt2
Reserved
BitO
Auto TMS High
Enable
LoopAround
Enable
This bit enables the TMSO shifter/buffer
for shift operations. If this bit is set, the
TMSO shifter/buffer will cause TCK to
stop if it is empty.
This bit enables the TMS1 shifter/buffer
for shift operations. If this bit is set, the
TMS1 shifter/buffer will cause TCK to
stop if it is empty.
• Bit 4:
This bit enables the TOO shifter/buffer for
shift operations. If this bit is set, the TOO
shifter/buffer will cause TCK to stop if it is
empty.
This bit enables the TOI shifter/buffer for
shift operations. If this bit is set, the TOI
shifter/buffer will cause TCK to stop if it is
full.
This bit enables the 32-bit counter. If this
bit is set, the counter will cause TCK to
stop if if has not been loaded or if it has
reached terminal count.
Bit 1
• Bit 3:
• Bit 2:
This bit is reserved and should remain as
a logic 0 during all 'PSC100 operations.
• Bit 1:
If this bit is set, TMS will be forced high
when the 32-bit counter is at state
(00000001 )h.
• BitO:
This bit causes TOI to be connected directly back through TOO for Loop-Around
operations.
MODE REGISTER 1 (MODE1)
Blt7
Blt6
BitS
Blt4
Blt3
Blt2
Bit 1
BltO
TOO
Interrupt
Enable
TOI
Interrrupt
Enable
CNT32
Interrupt
Enable
PRPG
Enable
sse
Enable
Freeze
Pin
Enable
Test
LoopBack
Test
LoopBack
This register is purely a mode register. All bits are writeable
and readable. The value 00000000 is placed in this register
upon RS'f low or a synchronous reset operation.
• Bit 7:
If this bit is set and the TOO shifter/buffer
is not full (I.e., one or both 8-bit TOO
• Bit 6:
If this bit is set and the TOI shifter/buffer
is not empty (I.e., one or both 8-bit TOI
FIFOs are full), the INT pin will go high.
• Bit 5:
If this bit is set, and the 32-bit counter is
not loaded or has reached terminal count,
the INT pin will go high.
• Bit 4:
This bit signifies that the TOO shifter/buffer is reconfigured as a 32-Bit Pseudo Random Pattern Generator. If set, and
MOOEO Bit 7 is set, the TOO shifter/buffer will stop TCK until a seed value has
been written to all four of the 8-bit LFSR
segments.
• Bit 3:
This bit signifies that the T01 shifter/buffer is reconfigured as a 16-Bit Serial Signature Compactor. If set, and MOOEO Bit 6
is set, the TOI shifter/buffer will cause
TCK to stop until a seed value has been
written to the two TOI registers.
• Bit 2:
If this bit is set, a high value on FRZ will
force TCK high (see TCK Control Section).
• Bits 1 and 0:
These bits are used to control Test LoopBack operations according to the following table.
FIFOs are empty), the INT pin will go high.
http://www.national.com
10·6
MODE1
Bit 1
MODE1
BltO
0
0
Normal Operation
0
1
Loop-Back TOO to TOI
1
0
Loop-Back TMSO to TOI
1
1
Loop Back TMS1 to TOI
Function
"tJ
Mode and Status Registers (Continued)
en
o
MODE REGISTER 2 (MODE2)
o
o
...&.
."
Write:
Blt7
Not
Used
Blt6
Not
Used
BitS
Not
Used
Bit 3
Bit 4
Not
Used
Blt2
Continuous
Update
Update
Status
Blt3
Blt2
Bit 1
BltO
Reset
Single
Step
CNT32
Read:
Bit7
TOO
Status
Blt6
TOI
Status
Bit 5
CNT32
Status
Blt4
TMS1
Status
TMSO
Status
This register contains both mode and status bits. Bits 4-7
are status bits only. Bit 3 is a status bit during read operations and a mode bit during write operations. Bits 0-2 are
mode bits only. Upon RST low, or a synchronous reset, the
value placed in MOOE2 is 10111000 (Read mode). Latches
used to update status bits 3-7 retain their last state upon
RST and are in an "unknown" state after power-up. To initialize the latches to a known state, they need to be updated
using the Update Status bit (bit 2) or continuous update bit
(bit 3).
• Bit7:
Set high if the TOO shifter/buffer is not
full, i.e., one or both B-bit TOO FIFOs are
ready to be written to.
• Bit 6:
Set high if the TOI shifter/buffer is not
empty, i.e., one or both B-bit TOI FIFOs
are ready to be read from.
Set high if the 32-bit counter has not been
loaded, or has reached terminal count.
• Bit 5:
• Bit 4:
Set high if the TMSO shifter/buffer is not
full, i.e., one or both B-bit TMSO FIFOs are
ready to be written to.
• Bit3
(Read Cycle):
Set high if the TMS1 shifter/buffer is not
full, i.e., one or both B-bit TMS1 FIFOs are
ready to be written to.
• Bit3
(Write Cycle):
If set, will cause all status bits to be continuously updated.
• Bit2
(Read Cycle):
Shows the state of the Continuous Update bit during read operations (Bit 3 during writes).
• Bit2
(Write Cycle):
If set, will cause a pulse to be issued internally that will update all status bits. This
bit will be reset upon completion of the
pulse. The state of this bit is not readable.
It is reset upon RST low.
If set, will cause a synchronous reset of all
functions except the parallel interface.
The value of this bit will return to zero
when the reset operation is complete.
• Bit 1:
• BitO:
Continuous
Update
Bit 1
BltO
Reset
Single
Step
CNT32
shift operations are in progress. The alignment of all registers during shift operations is controlled by a 3-bit counter in
the TCK control block. Enabling or disabling a function in
the middle of a shift operation may disrupt the logic necessary to keep all shifter/buffers byte-aligned.
For example, if the TOO shifter/buffer (already loaded) is
enabled while the 3-bit counter value is 3, the shifter/buffer
will only shift out only five bits of the first byte loaded.
The following bits should not be changed when shift operations are in progress, i.e., when TCK is enabled (see section
on TCK Control).
• MOOEO(7:3)
• MOOE1 (4:3)
• MOOE2(0)
Parallel Processor Interface (PPI)
ADDRESS ASSIGNMENT
The following table defines which register is selected for
access with the address lines, A(2:0).
If set, will cause the 32-bit counter to
count for one SCK cycle (no TCK cycle
will be generated). The value of this bit will
return to zero when the single step operation is complete.
PROGRAMMING RESTRICTIONS
A2
A1
AD
R/W
Function
0
0
0
0
TOO Shifter/Buffer
0
0
0
1
Counter Register 1
0
0
1
0
TOI Shifter/Buffer
0
0
1
1
TOI Shifter/Buffer
O
1
0
0
TMSO Shifter/Buffer
0
1
0
1
Counter Register 2
0
1
1
0
TMS1 Shifter/Buffer
0
1
1
1
Counter Register 3
1
0
0
0
32-Bit Counter
1
0
0
1
Counter Register 0
1
0
1
0
MODEO
1
0
1
1
MODEO
1
1
0
0
MODE1
1
1
0
1
MODE1
1
1
1
0
MODE2
1
1
1
1
MODE2
Because certain mode bits enable shift operations for certain functions, these mode bits should not be changed when
10-7
http://www.national.com
Ll-
e
e
[)
Parallel Processor Interface (PPI)
(Continued)
(J)
D..
TIMING WAVEFORMS
!------ \'=0
~IS=O
I
,r-
R(W
-1
lsl
-\'11
-
STe
\
Is2
I
\'2=:1
X
VALID
A(2:0)
C
X
0(7:0)
l>dl
I - len 1 -----j
I
l>d2
IS3
-
~\'3=:1
X
VALID
- ldiSI
-l>d·i
VALID
~
=!
I
L-
(SEE NOTE 1)
TL/F/l0968-3
FIGURE 2. Write Cycle
---\
-=0
t,=o-
I
,
-\'1=1
1=1'1-
I
STe
\
Is2
I
\'2-1
X
VALID
A(2:0)
len3
ten2
~d3
-
I
I
0(7:0)
(SEE NOTE 2)
-Ienl-j
l>dl
'Pd2
VALID
-~d·1
I
-Idi~
-ldis3
- ldiS1
=!
VALID
TLlF/l0968-4
FIGURE 3. Read Cycle
Note 1: Valid data is provided on the ROY line a tpdl after R/W is asserted low or a tpd2 after valid data is decoded on A2:0. The ROY line will remain high until the
addressed register is ready to participate in the write operation. This condition only applies when writing to a shifter/buffer and is eliminated (i.e., ROY will go low
immediately once valid) when using shifter/buffer status polling (discussed later in this datasheet).
Note 2: Valid data will not appear on 07:0 (and ROY will remain high) until the addressed register is ready to participate in the read operation. When the addressed
register becomes ready (Le., a byte is available to be read), valid data will be placed on the 07:0 bus and the ROY pin will go low allowing the bus cycle to continue.
This read cycle delay only applies when reading the TOI shifter/buffer and is eliminated when using shifter/buffer status poling.
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TIMING WAVEFORMS (Continued)
SCK
V
\~
\
______~yr------~\~______~y ,
\~------~V
R!W
STB
ROY
TLlF/10968-5
FIGURE 4. Consecutive Read/Writes (best case timing)
I
SCK
V
I
V
\
I
:/
\
I
I
\
I
V
\
V
I
R!W
t, • NOT ~ET
STB
\
ROY
~
~
/
/
'----I
/
TLlF/10968-6
FIGURE 5. Consecutive Read/Writes (worst case timing)
Figures 4/5: Figure 4 shows the best case bus cycle timing for SCK and STa during consecutive read or write cycles. The riSing edge of strobe occurs a setup
time, ts4 or before the falling edge of SCK. This allows the cycle to be completed within 1.5 clock SCK clock cycles. Figure 5 shows the worst case bus cycle timing
for SCK and STa during consecutive read or write cycles. The riSing edge of strobe does not meet the ts4 requirement between STa and SCK. Therefore, the
propagation of the Internal PSC100 control and reset Signals is delayed until the next falling edge of SCK. The bus cycle Is then completed 1.5 SCK cycles later
creating a total bus cycle time of 2.5 SCK cycles. If worst case timing is considered for bus cycle timing. ts4 is not a mandatory timing specification.
10·9
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Parallel Processor Interface (PPI)
(Continued)
TIMING WAVEFORMS (Continued)
,\----1
SCK
R!W
__
-JI~
________
,\----IV
,'----t
,'---~V
~~-J
STB
'Pdl
TL/F/l0968-20
FIGURE 6. Read/Write or Write/Read (best case timing)
SCK
V
I
,
:/
,
I
V
,
I
I
V
,
:1
R!W
'-----l
STB
RoY
~
'-----l
/
,'-----l /
TL/F/l0968-7
FIGURE 7. Read/Write or Write/Read (worst case timing)
Note: Figures 6/7: This diagram shows the timing for a read followed by a write (or write followed by a read). Separate Read and Write data/address latches and
control logic allow consecutive read/write or write/read operations to be overlapped (i.e., do not need to wait 2 or 3 SCK cycles between bus cycles). For the best
case timing scenario (Figure 8: rising edge of STB to falling edge of SCK greater than t s4), a new bus cycle can be performed each SCK cycle. For the worst timing
scenario (Figure 7: rising edge of STB to falling edge of SCK is less than ts4), a one SCK cycle delay must be included after each back to back read/write or write/
read sequence.
Note: Figures 4-7assume that the PSC100 register participating in the bus cycle is ready to accept/provide data. For bus cycles involving a PSC100 shifter/buffer(s), the ready status of a shifter/buffer can be checked using the status bits in Mode Register 2 prior to the start of the bus cycle. Polling is required when the
ROY pin is not used to provide a processor "handshake".
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Parallel Processor Interface (PPI)
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All read and write cycles will complete within 2.5 SCK cycles
(worst case). Therefore, by assuring at least 2.5 cycles occur after the rising edge of STB, bus cycles can be completed without using the ROY "handshake". The critical timing
relationship within the PSC100F for write and read operation is between the rising edge of STB and the falling edge
of SCK. The rising edge of strobe latches the address/data
and also generates the internal signals required to complete
read/write within the PSC100F (including a signal with resets the read/write logic and releases the ROY line). The
propagation of these internal signals is initiated on the first
falling edge of SCK after the STB pin is asserted high. If the
rising edge on STB occurs an internal setup time (t s4) or
greater before the falling edge of SCK, the bus cycle can be
completed within 1.5 SCK cycles (see Figure 4). However, if
the internal setup time is not met, the propagation of internal
control/reset signals is delayed until the next falling edge of
SCK (1 SCK cycle later) which effectively completes the
read/write operation and reset the logic for the next bus
cycle within 2.5 cycles (see Figure 5). Synchronizing the
rising edge of STB with the falling edge of SCK to assure
that ts4 is met provides the maximum performance for a
read/write operation. However, the asynchronous interface
can be used effectively with software delays, hardware delays or programmed wait states (to assure 2.5 SCK cycles
are completed) to avoid the need for synchronization.
READ AND WRITE CYCLES
A Write cycle (see Figure 2) is initiated by asserting CE and
R/W low followed by a low on STB a set time later. CE and
STB are gated within the PSC100F and may be asserted
concurrently (Le., zero setup and hold time). The address is
then asserted on A2:0 to indicate which internal address
within the PSC100F will be written to by the processor. An
address decoder within the PSC100F monitors the address
lines for a valid PSC100F register address. Once a valid
address has been decoded, the ROY line becomes active (a
propagation delay time later). The active ROY line will go
low immediately if the addressed register is ready to accept
data. If the addressed register is not ready, the ROY pin will
remain high preventing the processor from completing the
bus cycle. Once the register is ready to receive date (see
Table II), the ROY pin will go low and processor can resume
the write cycle. The processor then forces a high on STB (a
wait time after ROY goes low) which latches the address
(A2:0) and data (07:0) completing the bus cycle. The ROY
line is forced high a propagation delay later.
A Read cycle (see Figure 3) is initiated by asserting CE low
and R/W high followed by a low on STB a set time later. CE
and STB are gated within the PSC100F and may be asserted concurrently (Le., zero setup and hold time). The address
bits (A2:0) are then asserted to indicate which internal address within the PSC1 OOF will be read by the processor. An
address decoder within the PSC100F monitors the address
lines for a valid PSC100F register address. Once a valid
address has been decoded and if the addressed PSC100F
register is ready to be read (see Table II), valid data is
placed on the Oata lines (07:0) a propagation delay later
and the ready line is asserted low. If the addressed register
is not ready (e.g., the TOI shifter/buffer is empty), the ready
line will remain high and hold the bus cycle until the register
contains valid data. ROY will then go low allowing the read
cycle to continue. With the high to low edge on ROY line,
the processor can successfully read the valid data. However, the bus cycle is not completed within the PSC100F until
the rising edge on STB which resets the PSC100F read logic (required prior to the start of the next read cycle).
Consecutive Reads and Writes: Separate control logic
and data/address latches are used for a read and write operation within the PSC100F. This allows a write to occur
after a read (or conversely, a read to occur after a write)
prior to the 1.5/2.5 SCK clock cycle requirements described
above. The timing for a read (or write) followed by a write (or
read) is shown in Figures 5 and 6.
SYNCHRONIZATION
Writes and reads can be synchronized by using any of three
methods: polling, interrupts, or wait state generation:
• Status bits may be polled to see if a register is ready to
be written to or read from. To stabilize the status bits for
read operations, the Update Status bit must be set in
MOOE2 to latch the status.
Important note concerning the use of ROY: The ROY
signal provides a useful "handshake" between the
PSC100F and the processor. However, care must be taken
when using the PSC100F ROY signal to prevent a large (or
indefinite) number of processor generated wait states. For
example, if the TOO shifter/buffer is not enabled for shift
operations and the processor writes to the TOO shifter/buffer address 3 times, the two registers which make up the
TOO shifter/buffer will accept the first two bytes of data, but
since the data is not shifting out, the 3rd byte will be held off
by the ROY Signal indefinitely. An equally severe problem
could result with a finite number of wait states if the application uses dynamic memories. Holding the local bus with the
PSC100F ROY line long enough to violate a ORAM refresh
time will result in lost data within the dynamic memory.
Note: The status bits only provide the state of the shifter/buffers and do
not indicate that an internal write or read is complete. Therefore,
for applications not using the i"iDY signal to monitor the internal
write/read status, timing must be controlled to assure that at least
2.5 SCK cycles are completed between consecutive read or consecutive write cycles.
• Any of three different events can be used to generate
interrupts by forcing the INT pin high, see Table I.
• The ROY pin can be used to hold off the host until the
addressed register is ready to be accessed. As described
above, this pin can also be used to hold off additional
reads/writes until the synchronizer has recovered from
the previous read/write. ROY = 0 signifies that the
'PSC100F is ready to complete the current PPI cycle.
The logic that determines the state of ROY is summarized in Table II.
Writing and Reading without the use of ROY: With use of
worst case PSC1 OOF timing, Write and Read cycles can be
successfully completed without the use of the ROY signal.
Reading from CNT32 can be synchronized for testing by
using the Single Step Counter mode bit.
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Parallel Processor Interface (PPI)
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TABLE I. Interrupt Logic
MODE1(7) = 1 and TOO
Shifter/Buffer Not Full
MODE1(6) = 1 and TDI
Shifter/Buffer Not Empty
1
X
X
X
1
X
0
0
MODE1(5) = 1 and
CNT32 Not Loaded, or at
Terminal Count
X
X
1
0
INT
1
1
1
0
Note: Interrupts are generated using the INT pin. Three events trigger INT high. Each event has its own mode bit associated with it for masking or enabling these
interrupts.
R/W
0
0
0
0
Write
Synchronizer
Busy
1
X
X
X
0
0
1
1
1
X
X
X
TOO
Shifter/Buffer
Full and
A(2:0) = 0
X
1
X
X
0
X
X
X
G
.G
I
TEST-LOGIC
RESET
f
TABLE II. Ready State LogiC
TMSO
TMS1
Shifter/Buffer
Shifter/Buffer
Full and
Full and
A(2:0) = 2
A(2:0) = 3
X
X
X
X
1
X
X
1
0
0
X
X
X
X
X
X
Read
Synchronizer
Busy
X
X
X
X
X
1
X
0
TOI
Shifter/Buffer
Empty and
A(2:0) = 1
X
X
X
X
X
X
1
0
I
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RUN-TEST/
IDLE
II
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I SEL-DR-SCAN : 1
:: SEL-IR-SCAN
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CAPTURE-DR
r1f
I
CAPTURE-IR
!O
~r-.I
SHIFT-DR
I
0
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SHIFT-IR
EXIT1-DR
J-L
41
EXIT1-IR
PAUSE-DR
I
0
I
PAUSE-IR
EXIT2-DR
I
~
EXIT2-IR
~
!1
...
r
L UPDATE-IR
0
0
I
~
TLlF/10968-12
FIGURE 8. 1149.1 (JTAG) TAP Controller State Diagram
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UPDATE-DR
!1
J-L
!1
!1
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!1
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Serial Scan Interface (SSI)
Data is latched (or "sampled") into the boundary scan registers when the TAP controller (see Figure 8 on previous
page) transitions from the Capture-DR state to the Shift-DR
state (if SAMPLE/ PRELOAD is the active instruction). Synchronizing this "transition" (rising edge of TCK with TMS at
logic low) with a known system state is imperative to an
accurate pass/fail assessment. The Freeze Mode provides
a means of asynchronously creating the TCK pulse via an
external PSC100 pin. When the Freeze Pin Enable bit (bit 2
in Mode Register 1) is set, a logic high on the PSC100 FRZ
input pin will cause TCK to go high. Once the transition is
complete, the Freeze Mode can be removed (Le. Freeze Pin
Enable bit returned to logic 0 or Freeze pin forced low) and
the sampled data can be shifted out/evaluated using the
"standard" PSC100 protocol. Figure 9 illustrates the logic
implementation of the Freeze feature. It should be noted
that Freeze mode is simply gated with the TCK output and
does not disable shift operations within the shifter/buffers
or disable CNT32. Therefore, no shifting or TCK counting
using CNT32 should be performed when Freeze mode is
enabled.
The "standard" mode of TCK control uses CNT32 in conjunction with the status registers to start and stop TCK. For
this mode, CNT32 is enabled and loaded with the number of
TCK cycles required to shift the desired bits to/from the
scan chain. The shifter/buffer(s) participating in the shift operation is enabled and provides the necessary full/empty
status to stop TCK for processor writes/reads. This mode of
TCK control provides a systematic protocol for managing
PSC100 operations (specifically, handling partial bytes). Another option for TCK control relies solely on the status of
the shifter/buffers (Le., CNT32 is disabled) to start and stop
TCK. This option eliminates the time required to load
CNT32, but makes management of partial bytes (see shifter/buffer description section) more cumbersome.
TCKCONTROL
TCK CONTROL is the central control block that enables or
disables shift operations and provides byte alignment for
the shifter/buffers. The state of all shifter/buffers and the
32-bit counter (CNT32) is evaluated here and TCK is
stopped and started. A clock enable circuit allows the "TCK
enable" signal to change only when SCK is low; therefore,
TCK always stops low. TCK does not toggle (remains low)
under the following conditions:
• TOO Shifter/Buffer is enabled and empty.
• TOO Shifter/Buffer is enabled in PRPG mode and is not
fully loaded.
• TDI Shifter/Buffer is enabled and full.
• TDI Shifter/Buffer is enabled in SSC mode but is not fully
loaded with an initial value.
• TMSO Shifter/Buffer is enabled and empty.
• TMS1 Shifter/Buffer is enabled and empty.
• CNT32 is enabled but not loaded.
• CNT32 is enabled and has reached terminal count.
Also included within the TCK control block in CNT3, a 3-bit
count up counter. CNT3 is included to maintain byte alignment within the shifter/buffers by providing a signal to toggle between the two a-bit FIFOs which comprise the shifter/
buffer. The toggling operation occurs, in an enabled shifter/
buffer, each time CNT3 counts a TCK cycles or when
CNT32 reaches terminal count. The CNT3 is reset to 0
when CNT32 reaches terminal count or after a PSC100 reset condition.
FREEZE MODE. This mode is included in the TCK control
block to support the 1149.1 SAMPLE operation. The intent
of the SAMPLE instruction is to allow device input and output levels to be observed during normal system operation.
TCK Enable
SCK _ _....1...._ _ _--1
TCK
TL/F/l0966-9
FIGURE 9. TCK Logic
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0(7:0)
Auto TMS High Enable _ _.r-_
CNT32=1--~_
TMS
TLIF/10968-10
FIGURE 10. TMS Shifter/Buffer Block Diagram
other holds its previous state or can accept new parallel
data. Shift register selection changes due to the following
two events:
• CNT3 in TCK Control signals that 8 bits have been shifted. This event is used for basic toggling between each of
the two shift registers.
TMS(1:0} SHIFTER/BUFFERS
The TMS Shifter/Buffer block diagram is shown in Figure
10. These two blocks take parallel data and serialize it for
shift operations through the serial port pins TMSO and
TMS1.
Double-buffering is achieved by configuring the shifter/buffer as a 2 x 8 FIFO. Write and shift operations are controlled
by a local state machine that accepts stimulus from the PPI,
Mode Registers, CNT32 and TCK Control section. The TMS
outputs always change on the falling edge of SCK. The order of shifting is least significant bit first. TMS(1 :0) are
forced high upon RST low. TMS(1:0) are TRI-STATEd when
DE is high.
• CNT32 enabled and at terminal count. This event is used
to account for scan lengths which are not multiples of
eight. When shift register selection changes due to this
signal, any data remaining in the shift register is unused.
AUTO TMS HIGH MODE. This feature is included in the
TMS shifter/buffer block to improve the efficiency of the
PSC100 in supporting shift operations within the 1149.1 devices connected to the SSI. Shifting data and instructions
into 1149.1 compliant devices requires that their TAP controllers be sequenced to the Shift-DR or Shift-IR states (see
Figure 8). Once in this state, shifting occurs by holding TMS
low and clocking TCK. The last bit is shifted when the TAP
controller transitions to the EXIT1 state. This transition requires a logic 1 on TMS. The Auto TMS High feature, enabled by setting bit 1 of Mode Register 0, automatically creates a logic 1 on the TMS lines of the PSC1 00 when CNT32
= 1. Consequently, the last bit is shifted out without having
to load specific TMS data into the shifter/buffer.
Write operations are completed if the shifter/buffer is not
full (independent of whether shifter/buffer is enabled or disabled). Otherwise they are ignored. Shifting occurs when
the following conditions are all true:
• TMS is enabled with its respective mode bit.
• TMS shifter/buffer is not empty.
• TCK is enabled according to the logic in TCK Control.
When shift operations are not enabled, the TMS output retains its last state. During long shift sequences, the TMS
shifter/buffer can be disabled and held static so that shift
operations are concentrated only on TDI and TOO. The
TMS output also retains its last state when Test Loop-Back
operations are in progress.
Note: Auto TMS High mode creates a logic 1 on both TMS lines (i.e., TMSO
and TMS1). Therefore, when using the Auto TMS High feature, all
1149.1 devices connected to the TMS line not partiCipating in the
current JTAG test operations should be placed in the Test·Logic·Reset TAP controller state to prevent inadvertent TAP controller transitions.
Local select circuitry is used to toggle back and forth between the two registers of the "FIFO" when shifting. At any
given time, one register is selected for shift operations. The
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TOO SHIFTER/BUFFER
given time, one register is selected for shift operations. The
other holds its previous state or can accept new parallel
data. Shift register selection changes due to the following
two events:
The TOO Shifter/Buffer block diagram is shown in Figure
11. This block takes parallel data and serializes it for shift
operations through the serial port pin TOO. During normal
shift modes, double-buffering is achieved by configuring the
shifter/buffer as a 2 x a FIFO. This block can also be configured as a 32-bit Pseudo Random Pattern Generator (PRPG)
with two additional a-bit parallel-to-serial shift registers.
Write and shift operations are controlled by a local state
machine that accepts stimulus from the PPI, Mode Registers, CNT32, and the TCK Control section. The TOO output
always changes on the falling edge of SCK. The order of
shifting is least significant bit first. TOO is forced high upon
RST low. TOO is TRI-STATEd when DE is high.
• CNT3 in TCK Control signals that a bits have been shifted. This event is used for basic toggling between each of
the two shift registers.
• CNT32 enabled and at terminal count. This event is used
to account for scan lengths which are not multiples of
eight. When shift register selection changes due to this
signal, any data remaining in the shift register is unused.
PRPG MODE. By setting MOOE1 (4), the TOO Shifter/Buffer
is reconfigured as a 32-bit PRPG (Pseudo Random Pattern
Generator) using the primitive polynomial:
F(X) = X32 + X22 + X2 + X + 1
Write operations are completed if the shifter/buffer is not
full (independent of whether shifter/buffer is enabled or disabled). Otherwise they are ignored.
The PSC100 was developed to support both 1149.1 and
non-1149.1 serial test methodologies. Since 1149.1 compliant devices include boundary scan registers on control pins
(Le. DE), which must remain fixed during boundary scan interconnect testing, generating pseudo-random patterns with
PRPG mode provides limited usefulness for boundary scan
test operations. PRPG mode may provide usefulness in other serial test or non-test related implementations which do
not require fixed bits in the serial chain.
Figure 12 shows a block diagram of the Linear Feedback
Shift Register hookup.
Shifting occurs when the fol!owing conditions are all true:
• TOO is enabled with its respective mode bit.
• TOO shifter/buffer is not empty.
• TCK is enabled according to the logic in TCK Control.
When shift operations are not enabled, the TOO output retains its last state. The TOO output also retains its last state
when Test Loop-Back operations are in progress.
Local select circuitry is used to toggle back and forth between the two registers of the "FIFO" when shifting. At any
0(7:0)
-------~------pis
8-Bit
Shift Register t - + l - - I
8-Bit
pis
Shift Register .....-i-+--I
8-Bit
pis
Shift Register
8-Bit
pis
Shift Register
TOO
TL/F/l0968-11
FIGURE 11. TOO ShIfter/Buffer Block DIagram RegIster Hookup
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Serial Scan Interface (SSI)
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O
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X32
SCK
TL/F/10968-14
FIGURE 12. TOO PRPG Block Diagram
The PRPG is loaded by four PPI writes to the TOO address.
When the PRPG enable bit is set, a pulse is issued internally
that initializes the local parallel load logic such that the
PRPG is loaded sequentially, least significant byte first,
most significant byte last. When in PRPG mode, writes can
be completed at any time; however, shift operations will be
disabled until the PRPG is fully loaded.
shifted to the boundary scan chain. For example, moving
the TAP controllers within the boundary scan chain connected to TMSO from the Pause-OR state to the Run-Test!
Idle state requires a 3-bit (110) sequence on TMSO. To provide correct 3-bit sequence on TMSO, the partial byte would
be written to the TMSO shifter/buffer as:
MSB
LOOP AROUND MODE. This mode, enabled by setting bit 0
in Mode Register 0, will cause data appearing at the TOI
input to be placed directly back on the TOO output. This
feature can be used for read-only scan operations where
data is shifted into TOI while returning the scan chain to its
previous state when shifting is completed. It can also be
used to bypass PSC100 devices connected within a boundary scan chain (Le., a PSC100 located within a chain, but
not providing the JTAG TAP data). Loop around has limited
usefulness in most boundary scan applications since, typically, data in the scan chain is shifted out and evaluated as
new data is shifted into the chain for the next test.
I x I x I x I x I x I 0 I 1 I 1 I -.
TMSO
A subsequent enable and load of CNT32 with decimal 3 and
enable of the TMSO shifter/buffer will initialize the shift operation. Terminal count on CNT32 will complete the shift
operation. Since terminal count on CNT32 will cause the
register selection to change within the shifter/buffer, the
values labeled as "x" will not be used and are treated as
"don't cares".
TOI SHIFTER/BUFFER
The TOI Shifter/Buffer block diagram is shown in Figure 13.
This block shifts in serial data from the TOI port and puts it
in parallel form for read operations at the PPI. Ouring normal
shift modes, double-buffering is achieved by configuring the
shifter/buffer as a 2 x 8 FIFO. This block can also be configured as a 16-bit Serial Signature Compactor (SSC). Write,
read, and shift operations are controlled by a local state
WRITING A PARTIAL BYTE TO THE TMSO, TMS1 OR
TOO SHIFTER/BUFFER. Since the TMSO, TMS1 and TOO
shifter/buffers shift out least significant bit first, the valid
(meaningful) bits within a partial byte (Le., byte containing
<8 valid bits to be shifted to the scan chain) must be stored
and written into the shifter/buffer as the least significant
bits. This will assure that the desired bits will be accurately
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Serial Scan Interface (SSI)
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machine that accepts stimulus from the PPI, Mode Registers, CNT32 and the TCK Controi section. The TOI input
always shifts in data on the ri3ing edge of SCK. The order of
shifting is least significant bit first. The TOI input includes a
pull-up resistor to force a logic 1 when the test data signal
returning from the scan chain is floating.
signal, a partial byte (Le., byte with < eight valid data bits
shifted from the scan chain) will exist in the corresponding shift register. The embedded test software functions
written to support the evaluation of data read from the
TOI shifter/buffer must consider bit placement when
reading and evaluating a partial byte.
Read operations are completed if the shifter/buffer is not
empty and SSC mode is not enabled. Otherwise they are
ignored. Write operations are only possible while in SSC
mode. Otherwise they are ignored.
READING A PARTIAL BYTE FROM THE TDI SHIFTER/
BUFFER. Oata is shifted from the scan chain into each TOI
register from most significant bit to least significant bit. Consequently, the valid (Le., meaningful) bits in a partial byte
shifted into a TOI register will reside in the upper significant
bit locations. For example, if a scan operation involves shifting and evaluating 53 bits returning to TOI, TOI shifter/buffer must be read 7 times (Le., 6 full bytes plus a partial byte
containing 5 meaningful bits). If the last 5 bits shifted back
to the TOI shifter/buffer are 11010, then upon completion of
the shift operation (Le., terminal count on CNT32), the shift
register within the TOI shifter/buffer will contain the following partial byte:
Shifting occurs when the following conditions are all true:
• TOI is enabled with its respective mode bit.
• TOI shifter/buffer is not full.
• TCK is enabled according to the logic in TCK Control.
Local select circuitry is used to toggle back and forth between the two registers of the "FIFO" when shifting. At any
given time, one register is selected for shift operations. The
other holds its previous state or can accept new serial data.
Shift register selection changes due to the following two
events:
MSB
TOI
• CNT3 in TCK Control signals that 8 bits have been shifted in. This event is used for basic toggling between each
of the two shift registers.
~
LSB
x _x-L1_x--.J1
IL--0..J....1-1_0---l...-----'-_L-----'-,
Following a read of a partial byte, the embedded test software must adjust the position of the valid bits read from the
TOI shifter/buffer or the position of the expected data to
assure that an accurate comparison is made (and the nonmeaningful bits are masked).
• CNT32 enabled and at terminal count. This event is used
to account for scan lengths which are not multiples of
eight. When shift register selection changes due to this
TOI
TOO
1t.l50
1t.l51
LF5R
t.lode
LoopBack
t.lode
TL/F/l0968-8
FIGURE 13. TDI Shifter/Buffer Block Diagram
10-17
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Serial Scan Interface (SSI)
(Continued)
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Serial Data
SCK
TL/F/l0968-13
FIGURE 14. TDI SSC Block Diagram
SSC MODE. By setting MOOE1 (3), the TOI Shifter/Buffer is
reconfigured as a 16-bit SSC (Serial Signature Compactor)
using the primitive polynomial:
F(X) = X16 + X12 + X3 + X + 1
chain(s) must be considered when developing Loop-Back
test vectors to prevent undesired shifting of data or TAP
controller transitions within the scan chain.
Within a chain of 1149.1 compliant devices, there are typically one or more input pins which are driven by uncontrolled signals (Le., signals which are not driven to known
logic levels during a boundary scan CAPTURE operation).
These signals are masked during the evaluation of data returning from the scan chain. The SSC within the PSC100
does not provide masking capabilities and, therefore, provides limited usefulness for boundary scan test operations.
SSC mode may provide usefulness in other serial test or
non-test related implementations which contain predictable
data returning into the TOI shifter/buffer.
Figure 14 shows a block diagram of the Linear Feedback
Shift Register hookup.
CNT32 is a 32-bit, count-down binary counter arranged in
four 8-bit segments. CNT32 can be loaded independent of
its enable/disable status. Loading requires four consecutive
writes to its address (least significant byte first). These four
writes must not be interleaved with writes to any other address or the CNT32 write control logic will be re-initialized.
This re-initialization will result in a partially filled counter with
an undesired value. CNT32 is reset each time the counter
hits terminal count or by asserting the RST pin. A synchronous reset condition (setting Mode2(1» does not reset the
counter and a new value must be written to CNT32 to provide the desired number of TCK cycles.
32·BIT COUNTER (CNT32)
SINGLE STEP MODE: All four 8-bit registers are readable
for testability; however, there are no update latches similar
to the ones used for the status bits. To stabilize the counter
for read operations during on-board test, the Single Step
Mode has been added. This allows the user to place CNT32
in any state and then count for one SCK cycle (TCK will not
toggle when in singled step mode). The result can then be
read from the PPI. The counter can be tested by loading it
with values at its boundary conditions, and then clocking for
one cycle to see the results. For example, the counter could
be loaded with the value:
00000001 00000000 00000000 00000000
The SSC is loaded by two PPI writes to the TOI address.
When the SSC enable bit is set, a pulse is issued internally
that initializes the local parallel load logic such that the SSC
is loaded sequentially, most significant byte first, least significant byte last. When in SSC mode, writes can be completed at any time; however, shift operations will be disabled
until the SSC is fully loaded. PPI reads from TOI are ignored
while in SSC mode.
Upon leaving SSC mode an internal pulse causes the TOI
shifter/buffer to be full. Also, local read select logic is initialized such that the signature is read most-significant byte
first.
The next step is to set the Single Step Mode bit so that the
counter counts down to the next state and stops. The next
value is:
TEST LOOP·BACK MODES. This feature provides a means
for testing 'PSC100 functionality by looping data appearing
at the output of an outgoing shifter/buffer (Le., TMSO, TMS1
or TOO) back to the input of the TOI shifter/buffer. The loop
back function is accomplished with a simple multiplexer
(see Figure 13) whose path selection is determined by setting the mode bits in MOOE1 (1 :0). Loop back does not disable TCK or prevent shifting of data in the shifter/buffers to
the scan chain(s) connected to the PSC100. Therefore, the
state and operation of the TAP controllers within the scan
http://www.national.com
00000000
11111111
11111111
11111111
Four read cycles using the PPI will reveal the results of the
test.
Note: CNT32 will not wrap from terminal count (i.e., OOOOOOOOh decremented by 1 will remain unchanged and will not wrap to FFFFFFFFh).
Therefore, CNT32 should be loaded with a non-zero value prior to a
Single Step Mode Operation.
10-18
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Serial Scan Interface (551) (Continued)
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TIMING WAVEFORMS
I
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SCK
J r:~d5TCK
TOO
TMS
- - '----'f
--
--
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1\
~d5
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tpd8
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ten4
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t dis4 ~
tpd7
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It,5
ts5 --
~
TOI
~d8
-
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-
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FRZ
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TL/F/10968-15
FIGURE 15. Serial Scan Interface Timing
Embedded Test Software Support
an IEEE 1149.1 compatible system. SCAN EASE is written
to run on a wide range of processor and memory architectures. SCAN EASE includes the source code (ANSI C) and
is modular to allow user modification based on application
specific needs.
A SCANPSC100 device driver is provided by National to
supply functions for performing write, read and shift operations. National also offers a suite of software tools (called
SCAN EASE) which enables ATPG or custom generated
test vectors to be embedded, applied and evaluated within
10-19
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Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
DC Input Diode Current
VI = -0.5V
VI = vee + 0.5V
Supply Voltage (Vee)
'PSC100F
-0.5Vto +7.0V
(Iud
-20mA
+20mA
DC Input Voltage (VI)
-0.5V to Vee + O.5V
DC Output Source/Sink Current (10)
±50 mA
DC Vee or Ground Current
per Output Pin
±50 mA
DC Latchup Source or Sink Current
OVto Vee
-40°C to +85°C
- 55°C to + 125°C
Minimum Input Edge Rate dV /dt
SCAN "F" Series Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
-20mA
+20mA
DC Output Voltage (Vo)
OVto Vee
Output Voltage (Vo)
Operating Temperature (TA)
Commercial
Military
-0.5V to Vee +O.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
4.5Vto 5.5V
Input Voltage (VI)
125 mV/ns
±300 mA
Junction Temperature
SOIC
+ 140°C
Storage Temperature
- 65°C to + 150°C
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of SCANTM outside of recommended operation conditions.
DC Electrical Characteristics
Commercial
TA =
+ 25°C
Military
=
Commercial
=
Parameter
Vee
(V)
VIH
Minimum High
Input Voltage
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.Wor
Vee - 0.1V
VIL
Maximum Low
Input Voltage
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1Vor
Vee - O.W
VOH
Minimum High
Output Voltage
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
V
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
Symbol
Typ
VOL
Maximum Low
Output Voltage
TA
-55°C to
+ 125°C
TA
-40°C to
+85°C
Units
Conditions
Guaranteed limits
lOUT
= -
50 p,A
VIN = Vil or VIH
10H = -24mA
All Outputs Loaded
lOUT
= -
50 p,A
VIN = Vil or VIH
IOL = 24mA
All Outputs Loaded
VIN = Vee for TDI. OE
VIN = Vee. GND for
All Others
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
p,A
IllR
Maximum Input
Leakage Current
5.5
-385
-385
-385
p,A
VIN = GNDfor
TDI. OE Only
IOLD
Minimum Dynamic
Output Current
50
75
mA
VOlD = 1.65V Max
Maximum Test Duration
2.0 ms. One Output
Loaded at a Time
http://www.national.com
5.5
10-20
=
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o--.
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DC Electrical Characteristics (Continued)
Military
Commercial
Symbol
Vee
TA
(V)
Parameter
=
TA
+25°C
Typ
10HD
Minimum Dynamic
Output Current
loz
Maximum TRI-STATE
Leakage Current
10ZT
Maximum 1/0
Leakage Current
Commercial
=
-55°Cto TA
+ 125°C
."
=
-40°Cto
Units
+ 85°C
Guaranteed Limits
5.5
±0.5
±0.6
-50
-75
mA
VOHD = 3.85V Min
Maximum Test Duration = 2.0 ms,
One Output Loaded at a Time
± 10.0
±5.0
p.A
VIN = Vcc, GND
VIN (OE, R/W, CE, STB)
p.A
VIN = Vcc, GND
Vo = Vcc, GND
VIN(R/W, GE, STB)
± 11.0
±6.0
Icc
Maximum Quiescent
Supply Current
5.5
8
160
80
p.A
Icc max
Maximum Quiescent
Supply Current
5.5
768
920
840
p.A
ICCT
Maximum Icc/Input
ICCTA
Maximum Icc/Input
ICCD
Dynamic Power
Supply Current
(Note 1)
Conditions
=
=
VIL, VIH
TDI, DE Float
TDI,DElow
5.5
0.6
1.60
1.50
mA
VIN = Vcc - 2.1V
Float: TDI, OE
5.5
0.65
1.65
1.65
mA
VIN = Vcc -2.1V
TDI and OE Only
Float Untested Pin
5.5
1.70
2.30
2.30
VIH = Vcc, VIL = 0,
mAl
Vcc = Max, Outputs Open,
MHz
FSCK = 25 MHz
2.30
VIL, VIH
Note 1: This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
AC Electrical Characteristics/Operating Requirements
Commercial
Symbol
Parameter
Military
TA = +25°C
CL = 50 pF
Vee·
(V)
Min
Typ
TA
=
Commercial
-55°C to + 125°C
CL = 50 pF
TA
=
-40°C to + 85°C
CL = 50pF
Max
Min
Max
Min
Max
Units
Fig.
No.
PARALLEL PROCESSOR INTERFACE (PPI)
tpd1
Prop Delay
R/Wto ROY
5.0
5.0
14.0
19.5
5.0
24.0
5.0
24.0
ns
2,3,4
tpd2
Prop Delay
AtoRDY
5.0
5.0
14.0
19.5
5.0
24.0
5.0
24.0
ns
2,3
tpd3
Prop Delay
Ato 0
5.0
5.0
14.0
19.5
5.0
24.0
5.0
24.0
ns
3
tpd4
Prop Delay
STB to ROY
5.0
8.0
14.5
19.0
7.0
24.0
8.0
20.5
ns
2-4,6
ten1
Enable Time
GEto ROY
5.0
2.0
7.0
10.0
2.0
13.0
2.0
11.0
ns
2,3
tdis1
Disable Time
GEto ROY
5.0
1.0
5.5
8.0
1.5
10.0
1.0
9.0
ns
2,3
ten2
Enable Time
GEtoD
5.0
3.0
9.5
13.5
1.5
16.5
3.0
14.5
ns
3
tdis2
Disable Time
GEtoD
5.0
2.5
7.5
11.0
2.5
14.5
2.5
12.0
ns
3
'Voltage Range 5.0 is S.OV ±O.SV.
10-21
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a.
AC Electrical Characteristics/Operating Requirements
Symbol
Vcc'
(V)
Parameter
(Continued)
Commercial
Military
Commercial
TA = +25°C
CL = 50pF
TA = -55°C to + 125°C
CL = 50 pF
TA = -40°C to +85°C
CL = 50pF
Min
Typ
Max
Min
Max
Min
Max
Units
Fig.
No.
PARALLEL PROCESSOR INTERFACE (PPI) (Continued)
t en 3
Enable Time
R/Wto D
5.0
3.0
10.0
14.0
3.0
17.5
3.0
15.0
ns
3
tdis3
Disable Time
R/Wto D
5.0
3.0
8.5
12.5
3.0
16.0
3.0
13.5
ns
3
th1
Hold Time,
R/WtoSTB
5.0
0.5
0.0
0.5
0.5
ns
2-4,6
ts1
Setup Time
R/WtoSTB
5.0
1.0
0.0
1.0
1.0
ns
2-4,6
th2
Hold Time,
AtoSTB
5.0
4.0
2.5
4.5
4.0
ns
2,3
ts2
Setup Time,
AtoSTB
5.0
4.0
1.5
5.0
4.0
ns
2,3
th3
Hold Time,
DtoSTB
5.0
4.0
2.5
4.5
4.0
ns
2
ts3
Setup Time,
DtoSTB
5.0
0.0
-2.0
0.0
0.0
ns
2
ts4
Setup Time,
STB t toSCK
5.0
7.0
5.0
7.5
7.0
ns
4-7
19.5
12.0
20.0
19.5
ns
4,6
18.5
14.0
20.0
18.5
4,6
t
t
t
t
!
Clock Pulse Width
SCK(L)
SCK (H)
5.0
tW1
Pulse Width
STB (H or L)
5.0
5.5
2.0
6.0
5.5
ns
f max
Maximum Frequency
Clock
5.0
25
35
25
25
MHz
tw
'Voltage Range 5.0 is 5.0V ±0.5V.
http://www.nationai.com
10-22
"tJ
AC Electrical Characteristics/Operating Requirements
Symbol
Parameter
Vcc·
(V)
en
o
......
(Continued)
Commercial
Military
Commercial
TA = +25°C
CL = 50 pF
TA = -55°C to + 125°C
CL = 50pF
TA = -40°C to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Min
Max
o
o
"T1
Units
Fig.
No.
SERIAL SCAN INTERFACE (551)
tpd5
Prop Delay
SCKto TCK
5.0
3.0
B.O
11.0
3.0
14.0
3.0
12.0
ns
15
tpd6
Prop Delay
SCKtoTDO
5.0
5.5
12.0
16.0
5.5
19.5
5.5
17.5
ns
15
tpd7
Prop Delay
SCKtoTMS
5.0
4.5
11.0
14.5
4.5
1B.5
4.5
15.5
ns
15
tpd8
Prop Delay
FRZtoTCK
5.0
3.0
B.O
10.5
3.0
13.5
3.0
11.5
ns
15
ten4
Enable Time
OEtoJTAG
5.0
2.0
7.0
10.0
2.0
13.0
2.0
11.0
ns
14
tdis4
Disable Time
OEtoJTAG
5.0
1.0
6.0
9.0
2.0
11.0
1.0
10.0
ns
14
th5
Hold Time, H or L
TDI to SCK (Note 1)
5.0
ts5
Setup Time, H or L
TDI to SCK (Note 1)
5.0
0.5
-1.5
0.5
0.5
0.0
-2.0
0.0
0.0
5.0
3.0
5.5
5.0
6.5
3.5
7.5
6.5
ns
ns
-
15
15
15
r--15
RST RELATED TIMING
tpd
Prop Delay
RSTtoD
5.0
B.O
17.5
24.0
B.O
29.5
B.O
25.5
ns
tpd
Prop Delay
RSTtoRDY
5.0
B.O
19.5
25.5
B.O
31.0
B.O
28.0
ns
tphl
Prop Delay
RSTto INT
5.0
7.0
16.5
24.5
7.0
28.0
7.0
24.5
ns
tplh
Prop Delay
RSTto TDO
5.0
5.5
12.5
17.0
5.5
21.0
5.5
18.5
ns
tplh
Prop Delay
RSTtoTMS
5.0
5.5
12.0
16.0
5.5
20.0
5.5
17.5
ns
tWR
Pulse Width
RST(L)
5.0
6.0
4.0
6.5
6.0
ns
tREe
Recovery Time
SCKfrom RST
5.0
1.0
-0.5
1.0
1.0
ns
Note 1: sse Mode
'Voltage Range 5.0 is 5.0V ±O.5V.
10·23
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<:)
....
Application Note
en
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SCK MINIMUM PULSE WIDTH CALCULATION
o
a SHIFT-ENABLE signal which is generated internal to the
'PSC100, based on the status of the TDI buffer and the
Mode Registers.
The SCANPSC100 Parallel to Serial Converter is intended
to act as the interface between a processor and an IEEE
1149.1 boundary scan chain. When used in this configuration, there is a critical timing situation that is not obvious.
This timing involves the system clock rate at which data
from the scan ring is being read into the 'PSC100's TDI pin
(target TAP controllers in SHIFT-DR or SHIFT-IR states).
We now see the three major timing components which limit
the duration of the SCK pulse width low. There are two minor additional delays which should be noted. The TCK signal from the 'PSC100 needs to arrive at the target device to
be recognized, and this takes a finite amount of time depending on the signal trace length and impedance. Similarly,
the TDO signal of the last target in the chain needs to reach
the TDI pin of the 'PSC1 00, taking a finite amount of time as
well. These two trace delays can be minimized by making
the target device closest to the 'PSC100 the last device in
the chain. See Figure 17.
To fully understand the events which are taking place during
this critical period, it is useful to view the waveforms of interest as they relate in time. See Figure 16. The TCK is derived
internally to the 'PSC100 based on the system clock (SCK)
and clock gating control. The result is that when TCK is
running, it is at the same frequency as SCK but delayed in
time by the SCK-TCK propagation delay.
PROGRAMMING RESTRICTIONS
The TCK signal from the 'PSC100 drives all of the IEEE
1149.1 target devices. On the rising edge of TCK, data present at each scan cell is clocked into it. On the falling edge,
this data is presented at the output of the same scan cell for
the next adjacent cell to read. With regards to the last cell in
a particular target, the falling edge of TCK presents the data
in the last scan cell to the TDO pin, a TCK-TDO propagation
delay later.
Because certain mode bits enable shift operations for certain functions, these mode bits should not be changed when
shift operations are in progress. The alignment of all registers during shift operations is controlled by a three bit counter in the TCK control block. Enabling or disabling a function
in the middle of a shift operation may disrupt the logic necessary to keep all shifter/buffers byte-aligned. For example,
if the TDO shifter/buffer (already loaded) is enabled while
the three bit counter value is three, the shifter/buffer will
only shift out 5 bits of the first byte loaded.
At the 'PSC100, data shifted in through the TDI pin is
clocked in on the rising edge of SCK, not TCK. The reason
for this is that TCK is generated internal to the 'PSC1 00 and
intended to control the boundary scan targets. The 'PSC1 00
is controlled by SCK, therefore the signal to be shifted into
the TDI pin needs to be referenced to SCK not TCK. New
TDI data must be present a TDI-SCK set-up time prior to the
rising edge of SCK in order to guarantee validity. Although
SCK is usually continuous, the TDI buffer is controlled by
The following bits should not be changed when shift operations are in progress, i.e., when TCK is enabled (see TCK
control section):
• MODEO(7:3)
• MODE1 (4:3)
• MODE2(0)
'PSC100
Pw(L)
SCK
~\-
-JI
__
I
---""1"""""\ '
:Td~~_~
TCK
SCK-TCK~
,
I
I
I
TOI
TSIJ
I
I
I
TCI-SCK ,- ,
___
J~
X
_____I---J ,'--________
(From 1149.1 Device)
I
I.
.1
Tdl·--'I
I
--Td2·
I'
I
TCK-TCO:~
1149.1 Device
I
TCK
(From PSC 100)
I
TOO
--------------JX'--------·Trace Delays
Pw(L) minimum = Tpd1
+ Td1 + Tpd2 + Td2 + Tsu
FIGURE 16. System Clock Timing for Accurate TDI Data
http://www.national.com
10-24
TLlF/10968-16
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-
Tt.lS
TDI I - -
r- Tt.lS
TOI
W
-
:::J
:::J
:::J
:::J
1149.1
Device
r
TOO
PSC100
Tt.lS
TDI
R/W
TCK
STB
Tt.lS
TCK
1149.1
Device
r
r-
TOO
I
--------
- --
.....- Tt.lS
TDI
J
..... Tt.lS
TCK I-
rJ
TOO
,
/
/
/
00-07
1149.1
Device
1149.1
Device
AO-A2
--------
-
TOO
TCK
-------------------
I
I
-
TOO
TCK f-<
TL/F110968-17
Note: - - - - - Minimize the lengths of these two traces.
FIGURE 17. SCANPSC100 Location Relative to Targets
10-25
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tflNational Semiconductor
SCANPSC110F SCAN Bridge
Hierarchical and Multidrop Addressable JTAG Port
(IEEE1149.1 System Test Support)
General Description
Features
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove
a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up
to 3 local scan rings which can be accessed individually or
combined serially. Addressing is accomplished by loading
the instruction register with a value matching that of the Slot
inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of
the stable TAP Controller states via a Park instruction. The
32-bit TCK counter enables built in self test operations to be
performed on one port while other scan chains are simultaneously tested.
• True IEEE1149.1 hierarchical and multidrop addressable capability
• The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
• 3 IEEE 1149.1-compatible configurable local scan ports
• Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or
serially in groups of two or three
• 32-bit TCK counter
• 16-bit LFSR Signature Compactor
• Local TAPs can be tri-stated via the OE input to allow
an alternate test master to take control of the local
TAPs
Ordering Code: See Section 11
Connection Diagrams
28·Pin SOIC,
CDiP and Flatpak
0E-1
\...../
28 f-Vcc
50 51 -
2
27 f-TDb
3
26 f-TCK1.3
52 -
4
25 f-TM\3
53 - 5
5.- 6
24 f- 1Oo1.3
55 -
7
22 ~TC~2
Vcc - 8
TR5T- 9
20 f-m5 l2
23 ~TDll2
21
~GND
TM5B-
10
TCKB-
11
18 f-1Oll1
1OI B-
12
17 f-TCK l1
TDOg-
13
16 f-TM5 11
15 f-1O<\ 1
GND- 14
Pin Assignment for LCC
19 f-1O<\2
TLlF/11570-2
Pin Names
TL/F/11570-1
Order Number
Description
SCANPSC110FSC
SCANPSC110FSCX
SCANPSC110FFMQB
SCANPSC110FOMQB
SCANPSC110FLMQB
SOIC in Tubes
SOIC in Table and Reel
Military Flatpak
MilitaryOIP
Military Leadless Chip Carrier
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TCKS
™Ss
TOls
TOOs
TRST
S(0.5)
OE
TCKL(1-3)
TMSL(1-3)
TOIL(1-3)
TO°L(1-3)
10-26
Description
Backplane Test Clock Input
Backplane Test Mode Select Input
Backplane Test Oata Input
Backplane Test Oata Output
Asynchronous Test Reset Input (Active low)
Address Select Port
Local Scan Port Output Enable (Active low)
Local Port Test Clock Output
Local Port Test Mode Select Output
Local Port Test Oata Input
Local Port Test Oata Output
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Table of Contents
GLOSSARY OF TERMS .......................... 10-27
REGISTER DESCRiPTIONS ...................... 10-38
DETAILED PIN DESCRIPTION TABLE ............ 10-28
SPECIAL FEATURES ............................ 10-40
OVERVIEW OF SCAN BRIDGE FUNCTIONS ....... 10-29
BIST Support .................................. 10-40
SCANPSC110F Bridge Architecture .............. 10-29
RESET ....................................... 10-40
SCANPSC110F Bridge State Machines ........... 10-29
Port Synchronization ........................... 10-40
TESTERISCANPSC110F BRIDGE INTERFACE .... 10-32
ABSOLUTE MAXIMUM RATINGS ................. 10-42
REGISTER SET ................................. 10-33
RECOMMENDED OPERATING CONDITIONS ...... 10-42
ADDRESSING SCHEME ......................... 10-33
DC ELECTRICAL CHARACTERISTICS ............ 10-42
HIERARCHICAL TEST SUPPORT ................. 10-33
AC ELECTRICAL CHARACTERISTICS ............ 10-45
LEVEL 1 PROTOCOL ............................ 10-34
AC WAVEFORMS ............................... 10-48
Addressing Modes ............................. 10-34
APPENDIX ..................................... 10-50
Direct Addressing .............................. 10-34
State Diagram for Boundary-Scan TAP Controller .. 10-50
Broadcast Addressing .......................... 10-35
APPLICATIONS EXAMPLE ....................... 10-51
Multi-Cast Addressing .......................... 10-35
LEVEL 2 PROTOCOL ............................ 10-36
Level 2 Instruction Types ....................... 10-36
Individual Level 2 Instruction Descriptions ......... 10-36
TABLE I. Glossary of Terms
LFSR
Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test
data.
LSP
Local Scan Port. A four signal port that drives a "local" (Le. non-backplane) scan chain. (e.g., TCKL1,
TMSL1, TDOL1, TDIL1)
Local
Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANPSC11 OF Bridge Test
Access Port that drives them. The term "local" was adopted from the system test architecture that the
'PSC11 OF Bridge will most commonly be used in; namely, a system test backplane with a 'PSC11 OF
Bridge on each card driving up to 3 "local" scan rings per card. (Each card can contain multiple
'PSC11 OFs, with 3 local scan ports per 'PSC11 OF.)
Park/Unpark
Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the state of
the local TAP controllers (the "local TAP controllers" refers to the TAP controllers of the scan
components that make up a local scan ring). Park is also used to describe the action of parking a LSP
(transitioning into one of the Parked LSP controller states). It is important to understand that when a LSP
controller is in one of the parked states, TMSL is held constant, thereby holding or "parking" the local
TAP controllers in a given state.
TAP
Test Access Port as defined by IEEE Std. 1149.1
Selected/Unselected
Selected and Unselected refers to the state of the 'PSC11 OF Bridge Selection Controller. A selected
'PSC11 OF has been properly addressed and is ready to receive Level 2 protocol. Unselected 'PSC11 OFs
monitor the system test backplane, but do not accept Level 2 protocol (except for the GOTOWAIT
instruction). The data registers and LSPs of unselected 'PSC11 OFs are not accessible from the system
test master.
Active Scan Chain
The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a 'PSC110F is selected with all of its LSPs parked, the active scan chain is the current
scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDls ~ the current
'PSC11 OF register ~ the local scan ring registers ~ a PAD bit ~ TDOs. Refer to Table IV for
Unparked configurations of the LSP network.
Level 1 Protocol
Level 1 is the protocol used to address a 'PSC110F.
Level 2 Protocol
Level 2 is the protocol that is used once a 'PSC11 OF is selected. Level 2 protocol is IEEE Std. 1149.1
compliant when an individual'PSC11 OF is selected.
PAD
A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates the
prop delay that would be added by the 'PSC11 OF LSPN logic between TDILn and TDOL(n+ 1) or TDOs by
buffering and synchronizing the TOIL inputs to the falling edge of TCKs, thus allowing data to be scanned
at higher frequencies without violating set-up and hold times.
LSB
Least Significant Bit, the right-most position in a register (bit 0)
MSB
Most Significant Bit, the left-most position in a register
10-27
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TABLE II. Detailed Pin Description Table
I/O'
Name
Pin #
(SOIC
& LCC)
Description
™Ss
TTL Input w/Pull-Up
Resistor
10
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP
Controller of the SCANPSC11 OF Bridge. Also controls sequencing of the TAPs
which are on the three (3) local scan chains.
TDls
TTL Input w/Pull-Up
Resistor
12
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the
'PSC11 OF through this input pin.
TDOs
TRI-STATEable,
32 mAl64 rnA Drive,
Reduced-Swing,
Output
13
BACKPLANE TEST DATA OUTPUT: This output drives test data from the
'PSC110F and the local TAPs, back toward the scan master controller.
TCKs
TTL Schmitt Trigger
Input
11
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal
that controls all scan operations of the 'PSC11 OF and of the three (3) local scan
ports.
TRST
TTL Input w/Pull-Up
Resistor
9
TEST RESET: An asynchronous reset signal (active low) which initializes the
'PSC11 OF logic.
S(0-5)
TTL Inputs
2,3,4,
5,6,7
SLOT IDENTIFICATION: The configuration of these six (6) pins is used to identify
(assign a unique address to) each 'PSC11 OF on the system backplane.
OE
TTL Input
1
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this activelow control signal TRI-STATEs all three local scan ports on the 'PSC110F, to
enable an alternate resource to access one or more of the three (3) local scan
chains.
TDOL(1-3)
TRI-STATEable,
24 mAl24mA
Drive Outputs
15,19,
24
TEST DATA OUTPUTS: Individual output for each of the three (3) local scan ports.
TDIL(1-3)
TTL Inputs w/Pull-Up
Resistors
18,23,
27
TEST DATA INPUTS: Individual scan data input for each of the three (3) local scan
ports.
TMSL(1-3)
TRI-STATEable,
24mAl24 mA
Drive Outputs
16,20,
25
TEST MODE SELECT OUTPUTS: Individual output for each of the three (3) local
scan ports. TMSL does not provide a pull-up resistor (which is assumed to be
present on a connected TMS input, per the IEEE 1149.1 requirement)
TCKL(1-3)
TRI-STATEable,
24mAl24 mA
Drive Output
17,22,
26
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the three (3) local
scan ports. These are buffered versions of TCKs.
Vee
Power Supply
Voltage
8,28
Power supply pins, S.OV ± 10%.
GND
Ground potential
14,21
Power supply pins OV.
'All pins are active HIGH unless otherwise noted.
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10-28
"'C
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Overview of SCANPSC110F Bridge Functions
0
......
......
OE
TDO a
lOlLl
lO~1
TMS L 1
TCKL 1
TMSa~~~----------~~~1
TCKa ---~----------""--4~1
TRST-....- - -...
JTAG TAP
CONTROLLER
TDIL2
lO~2
TMSL2
TCK L2
.
So
~
•
S2 - - - - - - - - -.......~I
SCAN BRIDGE
S3
• SELECTION CONTROL
S4---------.. . .
~1
S5 -------i~L_ _r_-..J
TDI8 -
CLOCKS
AND
CONTROL
TDb
TDOL3
TMS u
TCKu
.....- -...- - - - -....
MULTi-CAST GROUP REGISTER
INSTRUCTiON REGISTER
32-BIT COUNTER REGISTER
16-BIT LINEAR FEEDBACK SHIFT REGISTER
LFSR SAMPLES DATA RETURNED FROM LSPN
TLlF/11570-3
FIGURE 1. SCANPSC110F Bridge Architecture
instruction register, mode register, and the TAP controller.
Each local port contains all four (4) boundary scan signals
needed to interface with the local TAPs.
SCANPSC110F BRIDGE ARCHITECTURE
Figure 1 shows the basic architecture of the 'PSC110F. The
device's major functional blocks are illustrated here. The
TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and various test
data registers can be scanned to exercise the various functions of the 'PSC110F (these registers behave as defined in
IEEE Std. 1149.1).
SCANPSC110F BRIDGE STATE MACHINES
The 'PSC11 OF is IEEE 1149.1-compatible, in that it supports
all required 1149.1 operations. In addition, it supports a
higher level of protocol, (Level 1), that extends the IEEE
1149.1 Std. to a multi-drop environment.
In multi-drop scan systems, a scan tester can select individual 'PSC110Fs for participation in upcoming scan operations. 'PSC110F "selection" is accomplished by simultaneously scanning a device address out to multiple
'PSC11 OFs. Through an on-chip address matching process,
only those 'PSC110Fs whose statically-assigned address
matches the scanned-out address become selected to receive further instructions from the scan tester. 'PSC110F
selection is done using a "Level-1" protocol, while follow-on
instructions are sent to selected 'PSC110Fs by using a
"Level-2" protocol.
The 'PSC11 OF selection controller provides the functionality
that allows the 1149.1 protocol to be used in a multi-drop
environment. It primarily compares the address input to the
slot identification and enables the 'PSC11 OF for subsequent
scan operations.
The Local Scan Port Network (LSPN) contains multiplexing
logic used to select different port configurations. The LSPN
control block contains the Local Scan Port Controllers
(LSPC) for each Local Scan Port (LSP1, LSP2, and LSP3).
This control block receives input from the 'PSC110F
10-29
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0
'T1
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o
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Overview of SCANPSC110F Bridge Functions (Continued)
a..
SCANPSC 11 OF Bridge-selection
state-machine
'''''-1 Pro\,,,' {
A
State
K'f
State
...
TAP Control
state-machine
7'
Scan port
configuration
state-machines
(3 total)
'''''-, Pro\,,,' {
A
State
'f
TLlF/11S70-4
FIGURE 2. SCANPSC110F Bridge State Machines
these scan port-selection state-machines allows individual
local ports to be inserted into and removed from the
'PSC110Fs overall scan chain.
The 'PSC11 OF contains three distinct but coupled state-machines (see Figure 2). The first of these is the TAP-control
state-machine, which is used to drive the 'PSC110Fs scan
ports in conformance with the 1149.1 Standard (see Figure
17 of appendix). The second is the 'PSC110F-selection
state-machine (Figure 3). The third state-machine actually
consists of three identical but independent state-machines
(see Figure 4), one per 'PSC11 OF local scan port. Each of
The 'PSC110F selection state-machine performs the address matching which gives the 'PSC110F its multi-drop capability. That logic supports single-'PSC11 OF access, multicast, and broadcast. The 'PSC110F-selection state-machine implements the chip's Level-1 protocol.
RESET
AD DR :p SLOT &
ADDR :#: BROADCAST &
ADDR:p MULTI-CAST (MCGR)
GOTOWAIT + RESET
Address =
SLOT
KEY
+ = OR
GOTOWAIT +
RESET
&
= AND
ADDR
=
6-bit address in the Instruction
Register
SLOT = Static address In the 'PSC11 OF
Selection Controller
TL/F/11S70-S
FIGURE 3. State Machine for SCANPSC110F Bridge Selection Controller
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10-30
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Overview of SCANPSC110F Bridge Functions (Continued)
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-n
TLIF/11570-12
FIGURE 4. Local SCANPSC110F Bridge Port Configuration State Machine
The 'PSC110F's scan port-configuration state-machine is
used to control the insertion of local scan ports into the
overall scan chain, or the isolation of local ports from tile
chain. From the perspective of a system's (single) scan controller, each 'PSC11 OF presents only one scan chain to the
master. The 'PSC11 OF architecture allows one or more of
the 'PSC11 OF's local ports to be included in the active scan
chain.
PARKRTI instruction, the Local Port controller enters the
Parked-RTI state in which TMSLn will be held low until the
port is later unparked. While TMSLn is held low, all devices
on that local scan chain remain in their current TAP State
(the RT/TAP controller state in this example).
The 'PSC11 OF's scan port-configuration state-machine implements part of the 'PSC11 OF's Level-2 protocol. In addition, the 'PSC110F provides a number of Level-2 instructions for functions other than local scan port confguration.
These instructions provide access to and control of various
registers within the 'PSC110F. This set instructions includes:
Each local port can be "parked" in one of four stable states
(Parked- TLR, Parked-RT!, Parked-Pause-DR or ParkedPause-IR), either individually or simultaneously with other
local ports. Parking a chain removes that local chain from
the active scan chain. Conversely, a parked chain can be
"unparked", causing the corresponding local port to be inserted into the active scan chain.
BYPASS
EXTEST
SAMPLE/PRELOAD
IDCODE
MODESEL
MCGRSEL
LFSRSEL
As shown in Figure 4, the 'PSC110F's three scan port-configuration state-machines allow each of the part's local
ports to occupy a different state at any given time. For example, some ports may be parked, perhaps in different
states, while other ports participate in scan operations. The
state-diagram shows that some state transitions depend on
the current state of the TAP-control state-machine. As an
example, a local port which is presently in the Parked-RTI
state does not become unparked (Le., enter the Unparked
state) until the 'PSC110F receives an UNPARK instruction
and the 'PSC110F's TAP state-machine enters the RunTest/Idle state.
CNTRSEL
LFSRON
LFSROFF
CNTRON
CNTROFF
GOTOWAIT
Figure 5 illustrates how the 'PSC11 OF's state-machines interact. The 'PSC110F-selection state-machine enables or
disables operation of the chip's three port-selection statemachines. In 'PSC11 OFs which are selected via Level-1 protocol (either as individual 'PSC110Fs or as members of
broadcast or multi-cast groups), Level-2 protocol commands can be used to park or unpark local scan ports. Note
that most transitions of the port-configuration state-machines are gated by particular states of the 'PSC110F's
TAP-control state-machine, as shown in Figures 4 and 5.
Similarly, certain transitions of the scan port-configuration
state-machine can force the 'PSC11 OF's TAP-control statemachine into specific states. For example, when a local port
is in the Unparked state and the 'PSC110F receives a
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II.
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Overview of SCANPSC110F Bridge Functions (Continued)
U)
D.
SCANPSC110F Bridge - Selection State - Machine
RESET
- - i -......r
GOTO,!(AlT+
RESET
GOTO,!(AlT
Local Scan Port Configuration State - Machines (1 per Local Port)
TLlF/llS70-6
FIGURE 5. Relationship Between SCANPSC110F Bridge State Machines
When the instruction register is updated with the address
data, the 'PSC110F's address-recognition logic compares
the six least-significant bits of the instruction register with
the 6-bit assigned address which is statically present on the
S(0-5) inputs. Simultaneously, the scanned-in address is
compared with the reserved Broadcast and Multi-cast addresses. If an address match is detected, the 'PSC11 OF-selection state-machine enters one of the two selected states.
If the scanned address does not match a valid single-slot
address or one of the reserved broadcast/multi-cast addresses, the 'PSC11 OF-selection state-machine enters the
Unselected state.
Note that the SLOT inputs should not be set to a value
corresponding to a mUlti-cast group, or to the broadcast address. Also note that the single-'PSC110F selection process
must be performed for all 'PSC110Fs which are subsequently to be addressed in mUlti-cast mode. This is required
because each such device's Multi-cast Group Register
(MCGR) must be programmed with a multi-cast group number, and the MCGR is not accessible to the test controller
until that 'PSC110F has first entered the Selected-Single'PSC110F state.
Following a hardware reset, the TAP controller state-machine is in the Test-Logie-Reset (TLR) state; the 'PSC11 OFselection state-machine is in the Wait-For-Address state;
and each of the three port-selection state-machines is in the
Parked- TLR state. The 'PSC11 OF is then ready to receive
Level-1 protocol, followed by Level-2 protocol.
TesterlSCANPSC110F Bridge
Interface
An IEEE 1149.1 system tester sends instructions to a
'PSC110F via that 'PSC110F's backplane scan-port. Following test logic reset, the 'PSC11 OF's selection state-machine is in the Wait-For-Address state. When the
'PSC110F's TAP controller is sequenced to the Shift-IR
state, data shifted in through the TDls input is shifted into
the 'PSC11 OF's instruction register. Note that prior to successful selection of a 'PSC11 OF, data is not shifted out of
the instruction register and out through the 'PSC110F's
TDOs output, as it is during normal scan operations. Instead, as each new bit enters the instruction register's
most-significant bit, data shifted out from the least-significant bit is discarded.
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Once a 'PSC110F has been selected, Level-2 protocol is
used to issue commands and to access the chip's various
registers.
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Register Set
The SCANPSC11 OF Bridge includes a number of registers
which are used for 'PSC11 OF selection and configuration,
scan data manipulation, and scan-support operations.
These registers can be grouped as shown in Table III.
Note that when any of these registers is selected for insertion into the 'PSC110F's scan-chain, scan data enters
through that register's most-significant bit. Similarly, data
that is shifted out of the register is fed to the scan input of
the next-downstream device in the scan-chain.
The specific fields and functions of each of these registers
are detailed in the section of this document titled "Data
Register Descriptions".
TABLE III. Registers
Register Name
BSDLName
Description
Instruction Register
INSTRUCTION
'PSC11 OF addressing and instruction-decode
IEEE Std. 1149.1 required register
Boundary-Scan Register
BOUNDARY
IEEE Std. 1149.1 required register
Bypass Register
BYPASS
IEEE Std. 1149.1 required register
Device Identification Register
IDCODE
IEEE Std. 1149.1 optional register
Multi-Cast Group Register
MCGR
'PSC11 OF-group address assignment
Mode Register
MODE
'PSC110F local-port configuration and control bits
Linear-Feedback Shift Register
LFSR
'PSC110F scan-data compaction (signature
generation)
TCK Counter Register
CNTR
Local-port TCK clock-gating (for BISn
Addressing Scheme
Hierarchical Test Support
The SCANPSC11 OF Bridge architecture extends the functionality of the IEEE 1149.1 Standard by supplementing that
protocol with an addressing scheme which allows a test
controller to communicate with specific 'PSC11 OFs within a
network of 'PSC11 OFs. That network can include both mUltidrop and hierarchical connectivity. In effect, the 'PSC11 OF
architecture allows a test controller to dynamically select
specific portions of such a network for participation in scan
operations. This allows a complex system to be partitioned
into smaller blocks for testing purposes.
Multiple SCANPSC11 OF Bridges can be used to assemble a
hierarchical boundary-scan tree. In such a configuration, the
system tester can configure the local ports of a set of
'PSC110Fs so as to connect a specific set of local scanchains to the active scan chain. Using this capability, the
tester can selectively communicate with specific portions of
a target system.
The tester's scan port is connected to the backplane scan
port of a "root" layer of 'PSC11 OFs, each of which can be
selected using multi-drop addressing. A second tier of
'PSC110Fs can be connected to this root layer, by connecting a local port (LSP) of a root-layer 'PSC110F to the backplane port of a second-tier 'PSC110F. This process can be
continued to construct a mUlti-level scan hierarchy.
The 'PSC11 OF provides two levels of test-network partitioning capability. First, a test controller can select entire individual 'PSC110Fs, specific sets of 'PSC110Fs (multi-cast
groups), or all 'PSC110Fs (broadcast). This 'PSC110F-selection process is supported by a "Level-1" communication
protocol. Second, within each selected 'PSC110F, a test
controller can select one or more of the chip's three local
scan-ports. That is, individual local ports can be selected for
inclusion in the (single) scan-chain which a 'PSC11 OF presents to the test controller. This mechanism allows a controller to select specific terminal scan-chains within the
overall scan network. The port-selection process is supported by a "Level-2" protocol.
'PSC110F local ports which are not cascaded into higherlevel'PSC11 OFs can be thought of as the terminal "leaves"
of a scan "tree". The test master can select one or more
target leaves by selecting and configuring the local ports of
an appropriate set of 'PSC11 OFs in the test tree.
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Level 1 Protocol
ADDRESSING MODES
The SCANPSC110F Bridge supports "single" and "multipie" modes of addressing a 'P5C110F. The "single" mode
will select one 'P5C110F and is called Direct Addressing.
More than one 'PSC110F device can be selected via the
Broadcast and Multi-Cast Addressing modes.
TABLE IV. SCANPSC110F Bridge Address Modes
Address Types
Direct Address
Hex Address·
Binary Address··
TDOa State
00 to 3A
XXOOOOOO to XX111 01 0
Normal IEEE Std. 1149.1
Always TRI-5TATED
Broadcast Address
3B
XX111011
Multi-Cast Group 0
3C
XX111100
Always TRI-STATED
Multi-Cast Group 1
3D
XX111101
Always TRI-STATED
Multi-Cast Group 2
3E
XX111110
Always TRI-STATED
Multi-Cast Group 3
3F
XX111111
Always TRI-STATED
• Hex address '7X', 'SX', or 'FX' may be used instead of '3X· .
•• Only the six (6) LSS's of the address is compared to the 5(0-5) inputs. The two (2) MSS's are "don't cares".
DIRECT ADDRESSING
register match the address on the S(0-5) inputs, (see Figure
6) the 'PSC11 OF becomes selected, and is ready to receive
Level 2 Protocol (Le., further instructions). When the
'PSC110F is selected, its device identification register is inserted into the active scan chain.
The 'PSC11 OF enters the Wait-For-Address state when:
1. its TAP Controller enters the Test-Logic-Reset state, or
2. its
instruction
register
is
updated
with
the
GOTOWAITinstruction (while either selected or unselected).
Each 'PSC110F within a scan network must be statically
configured with a unique address via its S(0-5) inputs. While
the 'PSC110F controller is in the Wait-For-Address state,
data shifted into bits 5 through 0 of the instruction register is
compared with the address present on the 5(0-5) inputs in
the Update-IR state. If the six (6) LSBs of the instruction
I
x
COMPARE
rrrrr
All 'P5C110Fs whose 5(0-5) address does not match the
instruction register address become unselected. They will
remain unselected until either their TAP Controller enters
the Test-Logic-Reset state, or their instruction register is updated with the GOTOWAIT instruction.
I
,..------, COMPARES ASSIGNED SLOT VALUE TO THE
SELECT IF SCANNED-IN SLOT VALUE. IF THEY ARE EQUAL,
EQUAL
THEN THIS SPECIFIC SCANPSC 11 OF BRIDGE IS
L--_ _....... SELECTED.
I I I I I I I I
X
a-BIT INSTRUCTION REGISTER
TLlF/11570-7
FIGURE 6. Direct Addressing: Device Address Loaded Into Instruction Register
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~
BROADCAST ADDRESSING
~
MULTI-CAST ADDRESSING
The Broadcast Address allows a tester to simultaneously
select all 'PSC110Fs in a test network. This mode is useful
in testing systems which contain multiple identical boards.
To avoid bus contention between scan-path output drivers
on different boards, each 'PSC110F's TDOs buffer is always tri-stated while in Broadcast mode. In this configuration, the on-chip Linear Feedback Shift Register (LFSR) can
be used to accumulate a test result signature for each board
that can be read back later by direct-addressing each
board's 'PSC11 OF.
o
As a way to make the broadcast mechanism more selective,
the 'PSC110F provides a "Multi-cast" addressing mode. A
'PSC110F's multi-cast group register (MCGR) can be programmed to assign that 'PSC110F to one of four (4) MultiCast groups. When 'PSC110Fs in the Wail-For-Address
state are updated with a Multi-Cast address, all 'PSC110Fs
whose MCGR matches the Multi-Cast group will become
selected. As in Broadcast mode, TDOs is always tri-stated
while in Multi-cast mode.
BROADCAST ADDRESS
SELECTS ALL SCANPSCll0F BRIDGES SIMULTANEOUSLY
8-BIT INSTRUCTION REGISTER
TL/F/11570-8
FIGURE 7. Broadcast Addressing: Address Loaded Into Instruction Register
I
Multi-Cast Group 0:
Multi-Cast
Group
Register
(MCGR)
OR
I
Multi-Cast Group 1 :
OR
I
Multi-Cast Group 2:
OR
Multi-Cast Group 3 :
WHEN MULTiCASTING
(CODE=llll),
SELECT BRIDGES
WHOSE MCGR
VALUE MATCHES
GROUP-SELECT
FIELD IN
SCANNED-IN
ADDRESS
(Multi-Cast Code)
TLlF/11570-9
FIGURE 8. Multi-Cast Addressing: Address Loaded Into Instruction Register
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Q.
Level 2 Protocol
isters (UNPARK, PARKTRL, PARKRTI, PARKPAUSE,
SOFTRESET,
LFSRON,
LFSROFF,
GOTOWAIT,
CNTRON, CNTROFF). These instructions, along with any
other yet undefined Op-Codes, will cause the device identification register to be inserted into the active scan chain.
Once the SCANPSC11 OF Bridge has been successfully addressed and selected, its internal registers may be accessed via Level-2 Protocol. Level-2 Protocol is compliant
to IEEE Std. 1149.1 TAP protocol with one exception: if the
'PSC110F is selected via the Broadcast or Multi-Cast address, TDOB will always be TRI-STATED. (The TDOB buffer
must be implemented this way to prevent bus contention.)
LEVEL 2 INSTRUCTION DESCRIPTIONS
BYPASS: The BYPASS instruction selects the bypass register for insertion into the active scan chain when the
'PSC110F is selected.
Upon being selected, (Le., the 'PSC11 OF Selection controller transitions from the Wait-For-Address state to one of the
Selected states), each of the local scan ports (LSP1, LSP2,
LSP3) remains parked in one of the following four TAP Controller states: Test-Logie-Reset, Run- Test/Idle, Pause-DR,
or Pause-IR and the active scan chain will consist of: TDIB
through the instruction register (or the IDCODE register) and
out through TDOB.
EXTEST: The EXTEST instruction selects the boundaryscan register for insertion into the active scan chain. The
boundary-scan register consists of seven "sample only"
shift cells connected to the S(0-5) and OE inputs. On the
'PSC11 OF, the EXTESTinstruction performs the same function as the SAMPLE/PRELOAD instruction, since there
aren't any scannable outputs on the device.
TDIB ~ Instruction Register ~ TDOB
The UNPARK instruction (described later) is used to insert
one or more local scan ports into the active scan chain.
Table IV describes which local ports are inserted into the
chain, and in what order.
SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction
selects the boundary-scan register for insertion into the active scan chain. The boundary-scan register consists of seven "sample only" shift cells connected to the S(0-5) and OE
inputs.
LEVEL 2 INSTRUCTION TYPES
There are two types of instructions (reference Table V):
IDCODE: The IDCODE instruction selects the device identification register for insertion into the active scan chain.
When IDCODE is the current active instruction the device
identification "OFCOE01 F" Hex is captured upon exiting the
Capture-DR state.
1. Instructions that insert a 'PSC11 OF register into the active
scan chain so that the register can be captured or updated (BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE,
MODESEL, MCGRSEL, LFSRSEL, CNTRSEL).
2. Instructions that configure local ports or control the operation of the linear feedback shift register and counter reg-
TABLE V. Level 2 Protocol and Op-Codes
Hex Op-Code
Binary Op-Code
BYPASS
FF
11111111
Bypass Register
Boundary-Scan Register
Instructions
Data Register
EXTEST
00
00000000
SAMPLE/PRELOAD
81
10000001
Boundary-Scan Register
IDCODE
AA
10101010
Device Identification Register
UNPARK
E7
11100111
Device Identification Register
PARKTLR
C5
11000101
Device Identification Register
PARKRTI
84
10000100
Device Identification Register
PARKPAUSE
C6
11000110
Device Identification Register
GO TOWA IT'"
C3
11000011
Device Identification Register
MODESEL
8E
10001110
Mode Register
MCGRSEL
03
00000011
Multi-Cast Group Register
SOFTRESET
88
10001000
Device Identification Register
LFSRSEL
C9
11001001
Linear Feedback Shift Register
LFSRON
OC
00001100
Device Identification Register
LFSROFF
8D
10001101
Device Identification Register
CNTRSEL
CE
11001110
32-Bit TCK Counter Register
CNTRON
OF
00001111
Device Identification Register
CNTROFF
90
10010000
Device Identification Register
TBD
TBD
Device Identification Register
Other Undefined
·The GOTOWAIT instruction returns both selected and unselected 'PSC11 OFs to the Wait-For-Address state. All other instructions act on selected 'PSC11 OFs
only.
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Level 2 Protocol
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(Continued)
UNPARK: This instruction un parks the Local Scan Port Network and inserts it into the active scan chain as configured
by the Mode register (see Table IV). Unparked LSPs are
sequenced synchronously with the 'PSC110F's TAP controller.
When a LSP has been parked in the Test-Logie-Reset or
Run-Test/Idle state, it will not become unparked until the
'PSC110F's TAP Controller enters the Run- Test/Idle state
following the UNPARK instruction. If an LSP has been
parked in one of the stable pause states (Pause-DR or
Pause-/RJ, it will not become unparked until the 'PSC11 OF's
TAP Controller enters the respective pause state. (See Figures 9, 10, 11, and 12).
in the Pause-DR state, as the 'PSC110F TAP controller is
sequenced into the Update-DR state. When a LSP is
parked, it is removed from the active scan chain.
GO TO WAIT: This instruction is used to return all
'PSC110Fs to the Wait-For-Address state. All unparked
LSPs will be parked in the Test-Logie-Reset TAP controller
state (see Figure 5).
MODESEL: The MODESEL instruction inserts the mode
register into the active scan chain. The mode register determines the LSPN configuration. Bit 7 of the mode register is
a read-only counter status flag.
MCGRSEL: This instruction inserts the multi-cast group register (MCGR) into the active scan chain. The MCGR is used
to group 'PSC110Fs into multi-cast groups for parallel TAP
sequencing (Le., to simultaneously perform identical scan
operations).
PARKTLR: This instruction causes all unparked LSPs to be
parked in the Test-Logie-Reset TAP controller state and removes the LSP network from the active scan chain. The
LSP controllers keep the LSPs parked in the Test-Logie-Reset state by forcing their respective TMSL output with a constant logic" 1" while the LSP controller is in the Parked- TLR
state (see Figure 4 ).
SOFTRESET: This instruction causes all 3 Port configuration controllers (Figure 4) to enter the Parked- TLR state,
which forces TMSLn high; this parks each local port in the
Test-Logie-Reset state within 5 TCKs cycles.
PARKRTI: This instruction causes all unparked LSPs to be
parked in the Run- Test/Idle state. When a LSP n is active
(unparked), its TMSL signals follow TMSs and the LSP n
controller state transitions are synchronized with the TAP
Controller state transitions of the 'PSC110F. When the instruction register is updated with the PARKRTI instruction,
TMSL will be forced to a constant logic "0", causing the
unparked local TAP Controllers to be parked in the RunTest/Idle state. When an LSPn is parked, it is removed from
the active scan chain.
LFSRSEL: This instruction inserts the linear feedback shift
register (LFSR) into the active scan chain, allowing a compacted signature to be shifted out of the LFSR during the
Shift-DR state. (The signature is assumed to have been
computed during earlier LFSRON shift operations.) This instruction disables the LFSR register's feedback circuitry,
turning the LFSR into a standard 16-bit shift register. This
allows a signature to be shifted out of the register, or a seed
value to be shifted into it.
LFSRON: Once this instruction is executed, the linear feedback shift register samples data from the active scan path
(including all unparked TDILn) during the Shift-DR state.
Data from the scan path is shifted into the linear feedback
shift register and compacted. This allows a serial stream of
data to be compressed into a 16-bit signature that can subsequently be shifted out using the LFSRSEL instruction.
The linear feedback shift register is not placed in the scan
chain during this mode. Instead, the register samples the
active scan-chain data as it flows from the LSPN to TDOs.
PARKPAUSE: The PARKPAUSE instruction has dual functionality. It can be used to park unparked LSPs or to unpark
parked LSPs. The instruction places all unparked LSPs in
one of the TAP Controller pause states. A local port does
not become parked until the 'PSC110F's TAP Controller is
sequenced through Exit1-DR/IR into the Update-DR/IR
state. When the 'PSC110F TAP Controller is in the Exitl-DR
or Exit1-IR state and TMSs is high, the LSP controller forces
a constant logic 'a" onto TMSL thereby parking the port in
the Pause-DR or Pause-IR state respectively (see Figure
4). Another instruction can then be loaded to reconfigure
the local ports or to deselect the 'PSC11 OF (Le., MODESEL,
GOTOWAIT; etc.).
LFSROFF: This instruction terminates linear feedback shift
register sampling. The LFSR retains its current state after
receiving this instruction.
CNTRSEL: This instruction inserts the 32-bit TCK counter
shift register into the active scan chain. This allows the user
to program the number of "n" TCK cycles to send to the
parked local ports once the CNTRON instruction is iss~ed
(e.g., for BIST operations). Note that to ensure completion
of count-down, the 'PSC110F should receive at least "n"
TCKs pulses.
CNTRON: This instruction enables the TCK counter. The
counter begins counting down on the first rising edge of
TCKs following the Update-IR TAP controller state and is
decremented on each rising edge of TCKs thereafter. When
the TCK counter reaches terminal count, "00000000" Hex,
TCKL of all parked LSP's is held low. The CNTROFF instruction must be Issued before unparking the LSPs of
a 'PSC110F whose counter has reached terminal count.
This function over-rides the mode register TCK control bit
(bit-3).
If the PARKPAUSE instruction is given to a bridge whose
LSPs are parked in Pause-/R or Pause-DR, the parked LSPs
will become unparked when the 'PSC11 OF's TAP controller
is sequenced into the respective Pause state.
The PARKPAUSE instruction was implemented with this
dual functionality to enable backplane testing (interconnect
testing between boards) with simultaneous Updates and
Captures.
Simultaneous Update and Capture of several boards can be
performed by parking LSPs of the different boards in the
Pause-DR TAP controller state, after shifting the data to be
updated into the boundary registers of the components on
each board. The broadcast address is used to select all
'PSC110Fs connected to the backplane. The PARKPAUSE
instruction is scanned into the selected 'PSC11 OFs and the
'PSC11 OF TAP controllers are sequenced to the Pause-DR
state where the LSPs of all 'PSC11 OFs become unparked.
The local TAP controllers are then sequenced through the
Update-DR, Select-DR, Capture-DR, Exit1-DR, and parked
CNTROFF: This instruction disables the TCK counter, and
TCKL control is returned to the mode register (bit-3).
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Level 2 Protocol
BACKPLANE TAP
LOCAL TAP
(Continued)
Exit 1-/R
Test-Logie-Reset
TL/F/11570-10
FIGURE 9. Local Scan Port Synchronization from Parked-TLR Instruction
BACKPLANE TAP
LOCAL TAP
Exit 1-IR
Run- Test/Idle
TLlF/11570-11
FIGURE 10. Local Scan Port Synchronization from Parked-RTIState
Register Descriptions
Boundary-Scan Register
The boundary-scan register is a "sample only" shift register
containing cells from the S(0-5) and DE inputs. The register
allows testing of circuitry external to the 'PSC11 OF. It permits the signals flowing between the system pins to be sampled and examined without interfering with the operation of
the on-chip system logic.
Instruction Register
The instruction shift register is an 8-bit register that is in
series with the scan chain whenever the TAP Controller of
the SCANPSC11 OF Bridge is in the Shift-IR state. Upon exiting the Capture-IR state, the value "XXXXXX01" is captured
into the instruction register, where "XXXXXX" represents
the value on the S(0-5) inputs.
When the 'PSC110F controller is in the Wait-For-Address
state, the instruction register is used for 'PSC11 OF selection
via address matching. In addressing individual 'PSC11 OFs,
the chip's addressing logic performs a comparison between
a statically-configured (hard-wired) value on that
'PSC110F's slot inputs, and an address which is scanned
into the chip"s instruction register. Binary address codes
"000000" through "111010" ("00" through "3A" Hex) are
reserved for addressing individual 'PSC110Fs. Address
"3B" Hex is for Broadcast mode.
In doing mUlti-cast (group) addressing, a scanned-in address is compared against the (previously scanned-in) contents of a 'PSC11 OF's Multi-Cast Group register. Binary address codes "111110" through "111111" ("3A" through
"3F" Hex) are reserved for multi-cast addressing, and
should not be assigned as 'PSC11 OF slot-input values.
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The scan chain is arranged as follows:
TOls ~ OE ~ S5 ~ S4 ~
S3 ~S2~S1 ~So~ LSPN~TOOs
Bypass Register
The bypass register is a 1-bit register that operates as specified in IEEE Std. 1149.1 once the 'PSC11 OF has been selected. The register provides a minimum length serial path
for the movement of test data between TOls and the LSPN.
This path can be selected when no other test data register
needs to be accessed during a board-level test operation.
Use of the bypass register shortens the serial access-path
to test data registers located in other components on a
board-level test data path.
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Register Description
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(Continued)
Multi-Cast Group Register
2. Scan out the multi-cast group address through the TOls
input of a/l'PSC110Fs. Note that this occurs in parallel,
resulting in the selection of only those 'PSC11 OFs whose
MCGR was previously programmed with the matching
multi-cast group code.
"Multi-cast" is a method of simultaneously communicating
with more than one selected 'PSC11 OF.
The multi-cast group register (MCGR) is a 2-bit register used
to determine which multi-cast group a particular 'PSC110F
is assigned to. Four addresses are reserved for multi-cast
addressing. When a 'PSC11 OF is in the Wait-For-Address
state and receives a mUlti-cast address, and if that
'PSC110F's MCGR contains a matching value for that multicast address, the 'PSC110F becomes selected and is ready
to receive Level 2 Protocol (Le., further instructions).
TABLE VI. Multi-Cast Group Register Addressing
The MCGR is initialized to "00" upon entering the Test-Logic-Reset state.
The following actions are used to perform mUlti-cast addressing:
MCGR
Bits 1,0
Hex Address
Binary Address
00
3C
XX111100
01
3D
XX111101
10
3E
XX111110
11
3F
XX111111
1. Assign all target 'PSC11 OFs to a mUlti-cast group by writing each individual target 'PSC110F's MCGR with the
same multi-cast group code (see Table VI). This configuration step must be done by individually addressing each
target 'PSC11 OF, using that chip's assigned slot value.
TABLE VII. Mode Register Control of LSPN
Mode Register
Scan Chain Configuration (If unparked)
XXXOXOOO
TDis ---. Register ---. TOOs
XXXOXOO1
TOls ---. Register ---. LSP1 ---. PAD ---. TOOs
XXXOX010
TOls ---. Register ---. LSP2 ---. PAD ---. TOOs
XXXOX011
TOls ---. Register ---. LSP1 ---. PAD ---. LSP2 ---. PAD ---. TOOs
XXXOX100
TOls ---. Register ---. LSP3 ---. PAD ---. TOOs
XXXOX101
TOls ---. Register ---. LSP1 ---. PAD ---. LSP3 ---. PAD ---. TOOs
XXXOX110
TOls ---. Register ---. LSP2 ---. PAD ---. LSP3 ---. PAD ---. TOOs
XXXOX111
TDis ---. Register ---. LSP1 ---. PAD ---. LSP2 ---. PAD ---. LSP3 ---. PAD ---. TOOs
XXX1XXXX
TOls ---. Register ---. TOOB (Loopback)
x = don't care
Register = 'PSC1l0F instruction register or any of the 'PSC1l0F test data registers
PAD = insertion of a l·bit register for synchronization
Mode Register
Bit 3 is normally set to logic "0" so that TCKL is free-running
when the local scan ports are parked. When the local ports
are parked, bit 3 can be programmed with logic "1 ", forcing
all of the LSP TCKL'S to stop. This feature can be used in
power sensitive applications to reduce the power consumed
by the test circuitry in parts of the system that are not under
test. Bit 3 of the mode register must be reset to logic
"0" before the UNPARK instruction is executed.
The mode register is an a-bit data register used primarily to
configure the Local Scan Port Network. The mode register
is initialized to "00000001" binary upon entering the TestLogic-Reset state.
Bits 0, 1, 2, and 4 are used for scan chain configuration as
described in Table VII. When the UNPARKinstruction is executed, the scan chain configuration will be as shown in
Table VII above. When all LSPs are parked, the scan chain
configuration will be TOls ---. 'PSC11 OF-register ---. TDOB.
Bit 3 is used for TCKLn configuration, see Table VIII.
Bit 7 is a status bit for the TCK counter. When the counter is
on and has reached terminal count (Zero) Bit 7 of the mode
register will be high (logic "1"). Bit 7 is read-only and will be
low in all other conditions.
TABLE VIII. Test Clock Configuration
Bits 5 and 6 are reserved for future use.
Bit 3
1
LSP n
Parked
TCKLn
Device Identification Register
Stop
The device identification register (IOREG) is a 32-bit register
compliant with IEEE Std. 1149.1. When the IDCODEinstruction is active, the identification register is loaded with the
value "OFCOE01 F" Hex upon leaving the Capture-DR state
(on the rising edge of the TCKB).
0
Parked
Run
1
Unparked
Run
0
Unparked
Run
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7. Bit 7 of the Mode register can be scanned to check the
status of the TCK counter, (MODESEL instruction followed by a Shift-DR). Bit 7 logic "0" means the counter
has not reached terminal count, logic "1" means that the
counter has reached terminal count and the BIST operation has completed.
8. Execute the CNTROFF instruction.
9. Unpark the LSP and scan out the result of the BIST operation (the CNTROFFinstruction must be executed before
unparking the LSP).
Register Descriptions
(Continued)
TABLE IX. Detailed Device Identification (Binary)
Bits 27-12
Bits 11-1
BltO
Part Number
Manufacturer
Identity
1
1111 1100 0000 1110 00000001 111
1
Bits 31-28
Version
0000
Linear Feedback Shift Register
The 'PSC110F contains a "signature compactor" which
supports test result evaluation in a multi-chain environment.
The signature compactor consists of a 16-bit linear-feedback shift register (LFSR) which can monitor local-port scan data as it is shifted "upstream" from the
'PSC110F's local-port network. Once the LFSR is enabled,
the LFSR's state changes in a reproducible way as each
local-port data bit is shifted in from the local-port network.
When all local-port data has been scanned in, the LFSR
contains a 16-bit signature value which can be compared
against a signature computed for the expected results vector.
The LFSR uses the following feedback polynomial:
F(x) = X16 + X12 + X3 + X + 1
The Self test will begin on the rising edge of TCKs following
the Update-DR TAP controller state.
RESET
Reset operations can be performed at three levels. The
highest level resets all 'PSC110F registers and all of the
local scan chains of selected and unselected 'PSC110Fs.
This "Level 1" reset is performed whenever the 'PSC11 OF
TAP Controller enters the Test-Logie-Resetstate. Test-Logie-Reset can be entered synchronously by forcing TMSs
high for at least five (5) TCKs pulses, or asynchronously by
asserting the TRST pin. A "Level 1" reset forces all
'PSC110Fs into the Wait-For-Address state, parks all local
scan chains in the Test-Logie-Reset state, and initializes all
'PSC110F registers.
This signature compactor is used to compress serial data
shifted in from the local scan chain, into a 16-bit signature.
This signature can then be shifted out for comparison with
an expected value. This allows users to test long scan
chains in parallel, via Broadcast or Multi-Cast addressing
modes, and check only the 16-bit signatures from each
module.
The LFSR is initialized with a value of "0000" Hex upon
reset.
32-Blt TCK Counter Register:
The 32-bit TCK counter register enables BIST testing that
requires "n" TCK cycles, to be run on a parked LSP while
another 'PSC11 OF port is being tested. The CNTRSEL instruction can be used to load a count-down value into the
counter register via the active scan chain. When the counter
is enabled (via the CNTRON instruction), and the LSP is
parked, the local TCKs will stop and be held low when terminal count is reached.
The TCK counter is initialized with a value of "00000000"
Hex upon reset.
TABLE X. Reset Configurations for Registers
Register
Initial Hex Value
2
0
Instruction
AA (IDCODElnstruction)
Mode
8
8
LFSR
16
0000
32-Bit Counter
32
00000000
01
The SOFTRESETinstruction is provided to perform a "Level 2" reset of all LSP's of selected 'PSC110Fs. SOFTRESETforces all TMSL signals high, placing the corresponding
local TAP Controllers in the Test-Logie-Reset state within
five (5) TCKs cycles.
The third level of reset is the resetting of individual local
ports. An individual LSP can be reset by parking the port in
the Test-Logie-Reset state via the PARKTLR instruction. To
reset an individual LSP that is parked in one of the other
parked states, the LSP must first be un parked via the UNPARK instruction.
Special Features
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of the
four TAP Controller states: Test-Logie-Reset, Run- Test/
Idle, Pause-DR, or Pause-IR. The 'PSC11 OF is able to park
a local chain by controlling the local Test Mode Select outputs (TMSL(1-3) (see Figure 4). TMSLn is forced high for
parking in the Test-Logic-Reset state, and forced low for
parking in Run- Test/Idle, Pause-IR, or Pause-DR states. Local chain access is achieved by issuing the UNPARK instruction. The LSPs do not become un parked until the
'PSC110F TAP Controller is sequenced through a specified
synchronization state. Synchronization occurs in the RunTest/Idle state for LSPs parked in Test-Logie-Reset or RunTest/Idle; and in the Pause-DR or Pause-IR state for ports
parked in Pause-DR or Pause-IR, respectively.
BIST SUPPORT
The sequence of instructions to run BIST testing on a
parked SCANPSC11 OF Bridge port is as follows:
1. Pre-load the Boundary register of the device under test if
needed.
2. Initialize the TCK counter to 00000000 Hex. Note that the
TCK counter is initialized to 00000000 Hex upon TestLogic-Reset, so this step may not be necessary.
3. Issue the CNTRON instruction to the 'PSC110F, to enable the TCK counter.
4. Shift the PARKRTI instruction into the 'PSC11 OF instruction register and 51ST instruction into the instruction register of the device under test.
Figures 11 and 12 show the waveforms for synchronization
of a local chain that was parked in the Test-Logie-Reset
state. Once the UNPARK instruction is received in the instruction register, the LSPC forces TMSL low on the falling
edge of TCKs.
5. Issue the CNTRSEL instruction to the 'PSC11 OF.
6. Load the TCK counter (Shift the 32-bit value representing
the number of TCKL cycles needed to execute the BIST
operation into the TCK counter register).
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Bit Width
MCGR
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TL/F/11570-15
FIGURE 11. Local Scan Port Synchronization on Second Pass
This moves the local chain TAP Controllers to the synchronization state (Run- Test/Idle), where they stay until synchronization occurs. If the next state of the 'PSC110F TAP
Controller is Run-Test/Idle, TMSL is connected to TMSs
and the local TAP Controllers are synchronized to the
'PSC110F TAP Controller as shown in Figure 12. If the next
state after Update-IR were Select-DR, TMSL would remain
low and synchronization would not occur until the 'PSC11 OF
TAP Controller entered the Run- Test/Idle state, as shown in
Figure 11.
The LSPN can be unparked in one of seven different configurations, as specified by bits 0-2 of the mode register. Using
multiple ports presents not only the task of synchronizing
the 'PSC11 OF TAP Controller with the TAP Controllers of an
individual local port, but also of synchronizing the individual
local ports to one another.
When multiple local ports are selected for access, it is possible that two ports are parked in different states. This could
occur when previous operations accessed the two ports
separately and parked them in the two different states. The
LSP Controllers handle this situation gracefully. Figure 12
shows the UNPARKinstruction being used to access LSP1,
LSP2, and LSP3 in series (mode register = "XXXOX111"
binary). LSP1 and LSP2 become active as the 'PSC110F
controller is sequenced through the Run-Test/Idle state.
LSP3 remains parked in the Pause-DR state until the
'PSC11 OF TAP Controller is sequenced through the PauseDR state. At that point, all three local ports are synchronized
for access via the active scan chain.
Each local port has its own Local Scan Port Controller. This
is necessary because the LSPN can be configured in any
one of eight (8) possible combinations. Either one, some, or
all of the local ports can be accessed simultaneously. Configuring the LSPN is accomplished with the mode register, in
conjunction with the UNPARK instruction.
BACKPLANE TAP
LSP1
HISS
TMSLl
TMSU
--------~~------+--
__________________________________________________- - J
TL/F/11570-14
FIGURE 12. Synchronization of the Three Local Scan Ports (LSP1. LSP2. and LSP3)
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VeC>
-0.5V to + 7.0V
DC Input Diode Current (Ill)
-20mA
VI = -0.5V
+20mA
VI = Vee +0.5V
DC Input Voltage (VI)
- 0.5V to Vee + 0.5V
DC Output Diode Current (10K)
-20mA
Vo = -0.5V
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to Vee +0.5V
DC Output Source/Sink Current (10)
± 50 mA
DC Vee or Ground Current
± 50 mA
per Output Pin
DC Latchup Source or Sink Current
± 300 mA
Junction Temperature
SOIC
+140°C
Storage Temperature
- 65°C to + 150°C
4000V
ESO Last Passing Voltage (Min)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply
temperature, and output/input loading variables. National does not recom·
mended operation of SCAN outside of recommended operation conditions.
Recommended Operating
Conditions
Supply Voltage (VeC>
SCANPSC110F
4.5V to 5.5V
Input Voltage (VI)
OVtoVee
Output Voltage (Vo)
Operating Temperature (TA)
Commercial
Military
OVtoVee
-40°C to + 85°C
- 55°C to + 125°C
Minimum Input Edge Rate dV/dt
SCAN "F" Series Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V. 5.5V
125 mV/ns
DC Electrical Characteristics
Commercial
Symbol
Parameter
Military
Commercial
Vee
(V)
Conditions
Typ
Guaranteed Limits
Minimum High
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
v
VOUT = 0.1Vor
Vee -0.1V
Maximum Low
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1Vor
Vee -0.1V
VOH
(TCKLn. TMSLn,
TOOLn)
Minimum High
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
lOUT = -50/-LA
VIN (TOls. TMSS.
TCKs) = VIH
VOH
(TCKLn. TMSLn.
TOOLn)
Minimum High
Output Voltage
4.5
5.5
3.86
4.86
3.7
4.7
3.76
4.76
V
VOH
(TOOs)
Minimum High
Output Voltage
4.5
5.5
3.15
4.15
3.15
4.15
3.15
4.15
V
VOH
(TOOs)
Minimum High
Output Voltage
4.5
5.5
2.4
2.4
2.4
2.4
V
lOUT = -32mA
All Outputs Loaded
VOH
(TOOs)
Minimum High
Output Voltage
4.5
5.5
2.4
2.4
2.4
2.4
V
lOUT = -24mA
All Outputs Loaded
VOL
(TCKLn. TMSLn.
TOOLn)
Maximum Low
Output Voltage
4.5
5.5
0.1
0.1
0.1
0.1
V
lOUT = +50/-LA
VIN (TOls. ™Ss.
TCKs) = VIL
http://www.national.com
0.001
0.001
10-42
0.1
0.1
lOUT = -24mA
VIN on 8(0.5) and
TOI(1-3) = VIH. VIL
All Outputs Loaded
lOUT = -50/-LA
"0
en
o
.....
.....
DC Electrical Characteristics (Continued)
Commercial
Symbol
Parameter
Vee
(V)
TA
=
25°C
Typ
Military
"T1
TA =
TA =
Units
-55°C to + 125°C - 40°C to + 85°C
Conditions
Guaranteed Limits
Maximum Low
VOL
(TCKLn .TMSLn. Output Voltage
TOOLn)
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
VOL
(TOOs)
Maximum Low
Output Voltage
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VOL
(TOOs)
Maximum Low
Output Voltage
4.5
5.5
0.55
0.55
0.55
0.55
VOL
(TOOs)
Maximum Low
Ouput Voltage
4.5
5.5
0.55
0.55
liN (OE.
TCKs.S(0-5»
Maximum Input
Leakage Current
5.5
±0.1
IIN,MAX
(TRST. TOILn.
TDis. ™Ss)
Maximum Input
Leakage Current
5.5
IIN,MAX
(TRST. TOILn.
TOls. TMSs)
Maximum Input
Leakage Current
IIN,MIN
(TOls. TMSs.
TRST. TOILn)
V
V
lOUT = +24 mA
VIN on S(0-5) and
TOI(1-3) = VIH. VIL
All Outputs Loaded
lOUT
=
+ 50 p.A
V
lOUT = +48mA
All Outputs Loaded
0.55
0.55
V
lOUT = +64mA
All Outputs Loaded
±1.0
±1.0
p.A
2.8
3.7
3.6
,Il-A
5.5
-385
-385
-385
p.A
Minimum Input
Leakage Current
5.5
-160
-160
-160
p.A
5.5
1.6
1.5
ICCT
Maximum Iccllnput
ICCT
(TOls. TMSs.
TRST.TOIU
Maximum Icc/Input
Icc
Maximum Quiescent
5.5
Supply Current
ICC, MAX
Maximum Quiescent
5.5
Supply Current
5.5
Minimum Dynamic
IOLD
(TCKLn. TMSLn. Output Current
TOOLn)
IOLD
(TOOs)
o
Commercial
Minimum Dynamic
Output Current
0.6
=
=
Vcc or
GNO
VIN
=
Vcc
VIN
=
GNO
VIN
=
GNO
mA
VIN
=
Vcc -2.1V
1.75
1.65
rnA
VIN = Vcc -2.1V
Test one at a time with
others floating
16
168
88
p.A
TOls. TMSs. TRST.
TOIL = Vcc
2.35
2.5
2.4
rnA
TOls. TMSs. TRST.
TOIL = GNO
50
75
rnA
YOLO = 1.65V max
VIN (DE) = VIL
(Note 2)
63
94
rnA
YOLO = 0.8V
VIN (TRSn = VIH
(Note 2)
0.6
5.5
5.5
VIN
VIN
94
10-43
http://www.nationaLcom
u..
....
....
o
o
DC Electrical Characteristics (Continued)
en
a.
Commercial
Parameter
Symbol
Vee
(V)
TA
Military
= 25°C
Typ
Minimum Dynamic
10HD
(TCKln. ™Sln• Output Current
TDOln)
Commercial
TA =
TA =
Units
-55°C to + 125°C - 40°C to + 85°C
Conditions
Guaranteed Limits
5.5
-50
-75
rnA
VOHD = 3.85V max
(Note 2)
VOHD = 2.0V max
(Note 2)
10HD
(TDOs)
Minimum Dynamic
Output Current
5.5
-40
-27
-40
mA
loz
Maximum TRI·STATE®
Leakage Current
5.5
±0.5
±10.0
±5.0
JlA
VIN (OE) = VIH
VIN (TRST) = Vil
Vo = Vee. GND
-100
-100
-100
mA
min
Vo = O.OV
(Note 3)
los
(TDOs)
Output Short
Circuit Current
5.5
Note 2: Maximum test duration of 2 ms. One output loaded at a time.
Note 3: Maximum test duration not to exceed 1 second.
Noise Specifications
Commercial
Symbol
Parameter
Vee
(V)
TA
= +25°C
Military
TA
Type
VOlP
VOlV
VOHP
VOHV
VIHD
VllD
Commerlcal
= -55°C to + 125°C TA = -40°C to + 85°C Units Conditions
Guaranteed Limits
Quiet Output
Maximum Dynamic 5.0
VOL
0.3
0.6
V
Figure 14
(Note 4)
Quiet Output
Minimum Dynamic
VOL
0.3
-0.6
V
Figure 14
(Note 4)
Quiet Output
Maximum Dynamic 5.0 VOH + 0.5 VOH + 1.0
VOH
V
Figure 14
(Note 5)
Quiet Output
Minimum Dynamic
VOH
5.0 VOH - 0.7 VOH - 1.2
V
Minimum High
Dynamic Input
Voltage Level
5.5
1.9
2.2
2.2
2.2
V
(Note 6)
Maximum Low
Dynamic Input
Voltage Level
5.5
1.4
0.8
0.8
0.8
V
(Note 6)
5.0
Figure 14
Note 4: Maximum number of outputs that can switch simultaneously is n. (n -1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.
Note 6: Maximum number of data inputs (n) switching. (n -1) input switching OV to 3V. Input under test switching 3V to threshold (VILO).
http://www.national.com
10·44
(Note 5)
AC Electrical Characteristics
Symbol
tpHL.
tpLH
tpHL.
tpLH
tpHL.
tpLH
Parameter
Propagation Delay
TCKs J- to TCKLn
TCKs i to TCKLn
Vee
(V)
Commercial
Military
(Preliminary)
TA = +25°C
Cl = 50pF
TA = -55°C
to + 125°C
CL = 50pF
Commercial
TA
=
-40°C to
+ 85°C
CL = 50 pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
5.0
3.0
2.5
8.5
8.5
12.5
12.5
3.0
2.5
15.0
15.0
3.0
2.5
13.5
13.5
ns
13
5.0
3.0
3.0
10.0
10.0
14.0
14.5
3.0
3.0
16.5
17.0
3.0
3.0
15.0
15.5
ns
13
5.0
3.5
4.5
15.0
14.5
23.0
21.5
3.5
4.5
26.5
24.5
3.5
4.5
25.0
23.0
ns
13
3.0
2.5
9.5
9.0
14.5
13.5
3.0
2.5
17.0
16.5
3.0
2.5
15.5
15.0
ns
13
Propagation Delay
TCKs
TCKs
JJ-
to TDOLn
to TDOLn
Propagation Delay
TCKs
TCKs
J- to TMSLn
J- to TMSLn
tpHL.
tpLH
Propagation Delay
TCKs J- to TDOs
TCKs J- to TDOs
5.0
tpHL.
tpLH
Propagation Delay
TMSs to TMSLn
5.0
2.5
1.5
8.0
7.5
12.0
12.0
2.5
1.5
14.5
14.5
2.5
1.5
13.0
13.0
ns
13
tpLH
Propagation Delay
TRST to TMSLn
5.0
4.5
19.0
26.5
4.5
30.0
4.5
28.5
ns
15
tpZL.
tpZH
Enable Time
TCKs J- to TDOLn
TCKs J- to TDOLn
5.0
4.0
3.0
12.5
11.0
18.5
15.5
4.0
3.0
22.5
19.0
4.0
3.0
20.5
17.0
ns
5.0
1.5
2.0
7.5
8.5
12.0
14.0
1.5
2.0
15.5
17.0
1.5
2.0
13.5
15.0
ns
5.0
4.0
2.5
12.0
9.0
17.0
13.5
4.0
2.5
20.5
16.5
4.0
2.5
18.5
14.5
ns
TCKs J- to TDOs
TCKs J- to TDOs
5.0
2.0
2.0
9.0
9.5
13.0
14.0
2.0
2.0
16.5
17.5
2.0
2.0
14.5
15.5
ns
tpZL.
tpZH
Enable Time
OEtoTDOLn
5.0
3.0
3.0
10.0
10.0
15.0
14.0
3.0
3.0
19.5
17.0
3.0
3.0
17.5
15.0
ns
16
tpLZ.
tpHZ
Disable Time
OE toTDOLn
5.0
1.0
1.0
7.0
8.0
11.0
13.0
1.0
1.0
14.0
15.5
1.0
1.0
12.0
13.5
ns
16
tpZL.
tpZH
Enable Time
OE toTMSLn
5.0
2.0
1.5
8.0
6.5
11.5
10.0
2.0
1.5
14.5
13.0
2.0
1.5
12.5
11.0
ns
16
tpLZ.
tpHZ
Disable Time
OE toTMSLn
5.0
1.0
1.0
5.0
6.0
9.0
10.0
1.0
1.0
12.0
12.5
1.0
1.0
10.0
10.5
ns
16
tpZL.
tpZH
Enable Time
OEtoTCKLn
5.0
2.0
1.5
8.0
6.5
11.5
10.0
2.0
1.5
14.5
13.0
2.0
1.5
12.5
11.0
ns
16
tpLZ.
tpHZ
Disable Time
OE to TCKLn
5.0
1.0
1.0
5.0
6.0
9.0
10.0
1.0
1.0
12.0
12.5
1.0
1.0
10.0
10.5
ns
16
tpLZ.
tpHZ
Disable Time
TRSTtoTDOs
5.0
2.5
3.0
11.0
12.0
16.5
16.5
2.5
3.0
20.0
20.0
2.5
3.0
18.0
18.0
ns
15
tpLZ.
tpHZ
Disable Time
TRST to TDOLn
5.0
2.5
1.5
11.5
11.5
17.5
17.5
2.5
1.5
21.0
21.0
2.5
1.5
19.0
19.0
ns
15
tpLZ.
tpHZ
tPZL.
tpZH
tpLZ.
tpHZ
Disable Time
TCKs J- to TDOLn
TCKs J- to TDOLn
Enable Time
TCKs J- to TDOs
TCKs J- to TDOs
Disable Time
10·45
http://www.national.com
u..
o
......-
oU)
AC Electrical Characteristics (Continued)
D.
Symbol
Parameter
Vee
(V)
Commercial
Military
(Preliminary)
Commercial
TA = +25°C
Cl = 50 pF
TA = -55°C
to + 125°C
Cl = 50pF
TA = -40°C to
+ 85°C
Cl = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time
TMSs to TCKs
t
5.0
3.5
B.O
B.O
B.O
ns
13
tH
Hold Time
TMSs to TCKs
t
5.0
-0.5
4.0
4.0
4.0
ns
13
ts
Setup Time
TOls to TCKs
t
5.0
1.5
6.0
6.0
6.0
ns
13
tH
Hold Time
Tdls to TCKs
t
5.0
1.0
4.0
4.0
4.0
ns
13
ts
Setup Time
Sn to TCKs J,
(in Update-DR state)
5.0
7.5
12.5
12.5
12.5
ns
Hold Time
Sn to TCKs J,
(in Update-DR state)
5.0
-3.0
0.0
0.0
0.0
ns
Setup Time
Sn to TCKs
(in Capture-DR or
Capture-fR state)
5.0
0.0
4.0
4.0
4.0
ns
Hold Time
Sn to TCKs
(in Capture-DR or
Capture-fR state)
5.0
1.5
6.0
6.0
6.0
ns
ts
Setup Time
TOILn to TCKs
t
5.0
-1.5
2.0
2.0
2.0
ns
13
tH
Hold Time
TOILn to TCKs
t
5.0
2.0
6.0
6.0
6.0
ns
13
ts
Setup Time
OEtoTCKs
(in Capture-DR state)
5.0
0.0
4.0
4.0
4.0
ns
Hold Time
OEtoTCKs
(in Capture-DR State)
5.0
0.0
4.0
4.0
4.0
ns
tw
Clock Pulse Width
TCKs (H or L)
5.0
16.0
20.0
24.0
24.0
ns
13
tWl
Clock Pulse Width
TRST(L)
5.0
6.0
10.0
10.0
10.0
ns
15
tH
ts
tH
tH
t
t
t
t
http://www.national.com
10-46
"tJ
en
o
AC Electrical Characteristics (Continued)
Symbol
Vee
(V)
Parameter
-10
-10
Commercial
Military
(Preliminary)
Commercial
TA = +25°C
CL = 50pF
TA = -55°C
to + 125°C
CL = 50 pF
TA = -40°C to
+S5°C
CL = 50 pF
Typ
tREe
Recover Time
TCKs i from TRST
5.0
tOSHL.
tosLH
Output-to-Output Skew
TCKLn
tOSHL.
tOSLH
FMAX
-2.0
o
'11
Units
Fig.
No.
Guaranteed Minimum
2.0
2.0
2.0
ns
15
5.0
1.0
1.0
1.0
ns
(Note 7)
Output-to-Output Skew
TMSLn (unparked)
5.0
2.0
2.0
2.0
ns
(Note 7)
Maximum Clock Frequency
5.0
25
MHz
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (toSHU. or LOW to HIGH (toSLH)' The specification is guaranteed but not tested.
CapaCitance
Typ
Units
Conditions
CIN
Symbol
Input Pin Capacitance
Parameter
5.0
pF
Vee is Open
COUT
Output Pin Capacitance
6.5
pF
Vee is Open
CPO
Power Dissipation Capacitance
50
pF
Vee = 5.0V
10-47
http://www.national.com
LL
C
,...
,...
o
AC Waveforms
U)
)1'
D..
tw
ts
::J<
I
'''"
)K:
\i
ts
* *
~
TCKt.n
~
I
0--
tpD
)K
~
ts
)K
)K
-----------------~--\i
TDctn
I-tpD
Tl/F/11570-16
FIGURE 13. Waveforms for an Unparked SCANPSC110F Bridge In the SHIFT-DR (IR) TAP Controller State
X. .______,.,x'----
o:r~~i~ ____
-
V_-_- ~ ~ ~ ~ ~~~P
QUIET
OUTPUT
UNDER TEST
YaH
" ' - - - - YOl
OHV
~~ ~~~~ ~ ~ ~== ===~ ~~~P
OlV
Note A: VOHV and VOlP are measured with respect to ground reference.
:s: 150 ps.
FIGURE 14. Quiet Output Noise Voltage Waveform
Note B: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew
http://www.national.com
10·48
Tl/F/11570-13
"'tJ
AC Waveforms
en
o
....
(Continued)
....
o
1-------twL-----~
"T1
TRST
lODt.n
lODe
TCKS
TL/F/11S70-1B
FIGURE 15. Reset Waveforms
".
\.
_I
loiS
--I
tEN
.1
I
,
'\I
I
f - 101
\I
c::::1
tEN
I
I
,
'\I
I
I·
I-Iols
~N
."
TCl<
m
Board #2
3
"C
LSP3
LSP1
LSP3
CD
LSP1
'0
o
;:!.
5°
c
m
I
......
o
&.
c.l
1
I
Bridge #1
SCANPSCll0
f
1000001
SLOT 5:0
1
LSP2
J
Parallel Bus Interface
Logic
1 SCAN 182245A 1
~
I
So
..
I
Bridge #2
SCANPSCll0
f
J
1000010 1
I
LSP2
• • • • Boards #3 - #8
Parallel Bus Interface
Logic
1SCAN 182245A 1
SLOT 5:0
I
TRST
TCK
Backplane wiring
to slots # 3 - # 10
HAS
TOO
TOI
TUF/11570-21
FIGURE 19. Testing the Backplane Interconnections
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1
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aci"
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SCAN EASE
SCAN Embedded Application Software Enabler
General Description
Features
National Semiconductor SCAN EASE, a suite of software
tools, enables ATPG or custom generated test vectors to be
embedded within an IEEE 1149.1 compatible system, administers test control and provides remote access.
EmbedPrep-Embedded Test Preparation includes embedded test development tools that convert ATPG output
files, like SVF or PAT, into Embedded Vector Format (EVF)
for use with EmbedTest.
EmbedTest-Embedded Test application code includes
high level code that controls the test flow and communications between the embedded system and a remote system
test administrator. It includes function libraries for controlling IEEE 1149.1 compliant boundary scan chains
(SCAN LI B), and reading test vectors stored in EVF
(EVFLlB). EmbedTest compiles to run on any microprocessor supporting ANSI-C.
EmbedComm-Embedded Test Communication provides a
Windows$ GUI for remote access to EmbedTest running on
an embedded system.
• Processor independent-runs on big/little end ian and
memory- and lID-mapped architectures
• Compatible with Teradyne VICTORYTM ATPG and
JTAG Technology BTPGTM tools (others supported
upon request)
• Provides automated translation, application and evaluation of ATPG-generated tests in an embedded system
environment
• Includes a Scan Function Library and National's Embedded Boundary Scan Controller SCANPSC100F device driver to support custom or non-ATPG generated
vector applications
• Supports embedded test data log for diagnostic processing
• Includes Microsoft Windows GUI and serial communication code for system administration and remote testing
• Supports SCANPSC110F Hierarchical and Multidrop
JTAG Addressable Port architecture
Order Number
Description
SCANEASEV100BSW
SCANEASEV100CSW
SCANEASEV100MSW
Basic Software License
Corporate License
Maintenance Contract
Embedded Test Hardware
SCAN EASE Software
• EmbedPrep
.uP
Compliers C ATPG Output file to
Embedded Vector File (EVF)
• EmbedTest
ANSI C Portable Embedded Test
and Serial Communication Code
,..
ROM
1== t--11
-.1...1.---1
I:::::: I
L.....-----I
• EmbedComm
Windows GUI for Remote
Access to Embedded System
RAM
1..-_ _....~
SCAN
PSC100F
t
+1149.1 Bus
TL/F/12120-1
FIGURE 1. SCAN EASE Enables ATPG Test Vectors to be Embedded
http://www.national.com
10-54
~----------------------------------------------------------------~~
(')
Functional Description
bedTest commands, such as configuration, reporting test
results, downloading new tests and uploading data logs, are
performed over this serial interface.
SCAN EASE does much of the programming work required
by programmers to convert a tester manufacturer's test vectors into embedded test vectors; manages and executes the
test; and provides communications code to download and
initiate tests remotely. SCAN EASE has a user-friendly Windows GUI interface to simplify test administration.
Compatibility
Embedded Application Software Enabler
~r--~~--..,/'re....
~
~
"JTAG Toch. 81PON)
m
Designed for portability and flexibility, both EmbedTest and
EVF run on both big endian and little endian memory architectures; the SCANPSC100F can be either I/O-mapped or
memory-mapped. This flexibility allows same code and test
vectors to run on various machines simply by recompiling
with a C-compiler for the target machine.
EmbedTest also provides a set of functions that enable
communication between the embedded system and a serial
interface for a system administrator or remote computer. Em-
ATPG
(e.g., Teradyne VictoryTM
~
Supporting Hardware
Several of the board level EVF files can be concatenated to
create a system level test. Partitioning tests enables EmbedTest to isolate and report pass/fail information to the
partitioned level-board, module, etc.-without running diagnostic software. EVF test files can be placed in ROM for
power-up self test or down loaded to RAM.
and
m
»
The SCANPSC100F Embedded Boundary Scan Controller
is a 28·lead IC designed to provide a simple, efficient interface between a microprocessor and the 1149.1 Test Access Port (TAP) signals. Its 8-bit asynchronous interface
connects directly to the local bus of many popular processors and allows the test clock (TCK) to run at a different
clock speed than the local bus. The SCANPSC100F supports TCK frequencies up to 25 MHz.
The test development process for embedded system test
begins with generating tests using an off-the-shelf ATPG
tool. A separate set of tests for each board type in the system is created during manufacturing test development.
These tests can be reused for embedded test, too. National's
SCAN EASE tools compile test vectors stored in Serial Vector Format (SVF) or Pattern Format (PAD into EVF, a compact binary format appropriate for embedded applications.
~
»
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EmbedComm
Windows™ GUI
for Remote Access
or
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commU!ication
Link
~
EmbedTest on
Embedded
System
TL/F/12120-2
FIGURE 2. SCAN EASE Works with Existing Board Test Vectors
m
10·55
http://www.national.com
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System Level Test Support
Partitioning tests is important to achieve built-in fault isolation. A natural place to partition tests is at the board or
module interface. Design boards with a 100% scannable
interface to the system back plane by buffering all back
plane signals with boundary scan compliant components
like National's 18-bit wide SCAN Test Access Logic CMOS
and ABT devices. A 100% scannable interface enables
ATPG to generate 100% fault coverage on the back plane.
The SCAN ABT Test Access Logic interface with power-up
TRI-STATE~ for live insertion allows board level tests to be
performed without disturbing back plane signals, too.
The Hierarchical and Multidrop JTAG Addressable Port
SCANPSC110F provides an interface from a single IEEE
1149.1 TAP to "local TAPs" on boards or modules that reside within a system. This enables boards to be pulled or
added to the system without breaking the serial scan chain,
and makes it possible to perform an interrogating infrastructure test to determine the system configuration before applying board-level tests. The SCANPSC11 OF facilitates partitioning of boards and modules within the system for improved fault isolation.
~
~
IEEEE Std. 1149.1 Multi-Dropped System Test Bus
TlIF/12120-3
FIGURE 3. Embedding SCAN EASE for System Level Test
More Detailed Information about
SCAN EASE
An application note is available on National's Web Site
(http://www.nsc.com). and through the National Technical
Support Center (1-800-272-9959) to provide more detailed
information on the SCAN EASE architecture and API (applications programming interface). The SCAN EASE product
includes a reference manual to detail the EVF format, embedded code architecture and functions which comprise the
SCAN EASE tool set.
http://www.national.com
10·56
Section 11
Ordering Information and
Physical Dimensions
III
http://www.national.com
Section 11 Contents
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSOP Package Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dry Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Drawings and Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
Worldwide Sales Offices
11-2
11-3
11-3
11-4
11-5
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Ordering Information
SCAN
S.dally C"t"II.d
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OB = Military grade device with
environmental and burn-in
processing
18-Bit Test Access logic
Function Type
Technology /Designator
T = TTL Input TTL Output CMOS Device
C = CMOS Input/Output CMOS Device
B = Bipolar TTL Device
E = ECl Device
A = BiCMOS Device
F = TTL Input/CMOS Output Ct.40S Device
!!.
IC
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Temperature Range
C = Commercial (-40 0 C to +85°C)
M Military (-55 0 C to + 125 O C)
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SS = 25 mil Pitch (JEDEC) SSOP
f = 25 mil Pitch Ceramic Flatpak
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Serially Controlled
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Part Number
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PSC 11 0
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PSC100
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Technology /Designator
T = TTL Input/TTL Output Ct.40S Device
C = CMOS Input/Output CMOS Device
B = Bipolar TTL Device
E = ECl Device
A = BiCMOS Device
f = TTL Input/CMOS Output CMOS Device
Package/Temp Designator
= 50 ml Pitch (JEDEC) SOIC
SC
Temperature Range
-40°C to +85°C
DMOB = Ceramic DIP, t.4ilitary
Temperature Range, 883
Processing
lMOB = leadless Chip Carrier,
Military Temperature Range,
883 Processing
FMOB = f1atpak, t.4i1itary
Temperature Range, 883
Processing
TL/F/11596-10
SSOP Package Thermal Information
THERMAL RESISTANCE FOR SSOP PACKAGES
Package
Paddle
Dimensions
(mils)
8JA
8JA
8JA
8JA
OLFPM
500LFPM
("C/W)
900LFPM
(OC/W)
8JC
(OC/W)
225 LFPM
("C/W)
N/A
20LD SSOP
110x144
127.0
99.4
90.1
78.5
24LDSSOP
98 x 106
117.0
91.4
82.7
73.5
N/A
24LDSSOP
120 x 150
100.8
81.3
72.1
65.7
25.7
48LDSSOP
190 x 190
75.5
58.0
51.5
44.0
21.5
56LDSSOP
190 x 190
67.8
53.0
47.4
42.1
18.5
THERMAL RESISTANCES FOR THE MILITARY FLATPAK PACKAGES
Cavity
Dimensions
(mils)
8JA
8JA
8JA
8JA
OLFPM
("C/W)
225LFPM
("C/W)
500LFPM
("C/W)
900 LFPM
48LD
250x250
74.4
58.1
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43.9
6.6
56LD
250x250
59.8
47.9
39.0
35.1
3.4
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Dry Pack is moisture proof packing that is used to store
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effect". Humidity collects inside the package by seeping
through the plastic. If moisture is inside the device when the
unit goes through a solder machine, the heat quickly changes the moisture to steam, and the pressurized steam pops
open the package ... thus the popcorn effect.
The Dry Pack bag is hermetically sealed and contains a
small bag of desiccant which further helps to reduce moisture. All of the SCAN 5S-pin SSOP devices will be shipped in
Dry Pack bags. Included with the devices will be the following warning label and instructions for rebake:
D.
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This Bag Contains
MOISTURE SENSITIVE DEVICES
1. Shelf life in sealed bag: 24 months at <40°C and <90% Relative Humidity (RH).
2. Upon opening this bag, devices to be subjected to I.R., V.P.R. or equivalent process
must be:
a. Mounted within 48 hours at factory conditions of <30°C/SO% RH, or
b. Stored at < 10% RH.
3. Devices require baking, before mounting, if:
a. Humidity Indicator Card is > 20% when read at 23°C ± 5°C.
b. 2a or 2b are not met.
4. If baking is required, devices may be baked for:
a. 19 hours at 40°C + 5°C/ - O°C and < 5 % RH for low temperature device
containers, or
b. 8 hours at 125°C ± 5°C for high temperature device containers.
Dry-Pack Seal Date: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
(IF BLANK, SEE BAR CODE LABEL)
BAG SN 045317
Please follow these instructions carefully to avoid the popcorn effect.
http://www.national.com
11-4
MFRLOTNo.
C32729
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NS Package Number E28A
All dimensions are in inches
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A.
0.420 (10.65)
0.393 (10.00)
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0.030 (0.75)x45 0
0.009 (0.25)
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0.713 (18.10)
0.696 (17.70)
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0.050 (1.27)
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0.020 (0.49)
0.013 (0.35)
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0.105 (2.65)
0.092 (2.35)
0.012 (0.30)
L
0.003 (0.10)
0.050 (1.27)
0.015 (0.40)
W28B (REV A)
56 Lead (O.300" Wide) Molded Shrink Small Outline Package, JEDEC
NS Package Number MS56A
All dimensions are in inches [millimeters]
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0.395 0.420
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1-0-10.010[0.25] @IDIAM IBM 1
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1]."0-0.0"
[0.51 - 1.01]
DETAIL E TYP
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0.008 - 0.016 TYP
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NS Package Number WA28D
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All dimensions are in inches [millimeters]
I:
0.740
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0.045-0.090
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t-r-0.026-0.045
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[0.1 0-0.23]
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0.005-0.018
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WA28D [REV Al
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[0.38-0.56]
56 Lead Cerpack
NS Package Number WA56A
All dimensions are in inches [millimeters]
-- 10
11
0.070-0.100
[1.78-2.54]
0.040-0.054
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[1.02-1.37]
0.740 t.AAX
[18.80]
~ 0.005 t.AIN TYP
56
[0.13]
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29
0.250-0.350
[6.35-8.89]
I'"
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0.400
[10.16] MAX
GLASS
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0.376-0.384
[9.55-9.75]
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PIN #1
IDENT
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0.250-0.350
[6.35-8.89]
II 0.004-0.009
TYP
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-l11 ~
~ 0.006-0.0
[0.15-0.25]
0.008-0.012 TYP
[0.20-0.30]
11-7
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28
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0.025 TYP
-l1--[0.64]
III
WA56A [REV Al
http://www.national.com
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
t!JNational Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
For datasheets on new products and devices still in production but not found in a databook, please contact the National
Semiconductor Customer Support Center at 1-800-272-9959.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
ADVANCED BiCMOS LOGIC (ABT, BiCMOS SCAN, LOW VOLTAGE
BiCMOS, EXTENDED TTL TECHNOLOGY) DATABOOK-1996
ABT Description and Family Characteristics • ABT Ratings, Specifications and Waveforms
ABT Applications and Design Considerations • Quality and Reliability
SCAN18xxxA BiCMOS 5V Logic with Boundary Scan. 74LVT Low Voltage 8iCMOS Logic
VME Extended TTL Technology for Backplanes. Advanced BiCMOS Clock Generation and Support
ADVANCED BIPOLAR LOGIC
FAST®, FASTr™, ALS, AS DATABOOK-1995
Introduction to Advanced Bipolar Logic Families • FAST /FASTr/ ALS/ AS. Family Characteristics
Ratings, Specifications and Waveforms • Design Considerations • Datasheets • Ordering and Packaging Information
APPLICATION SPECIFIC ANALOG PRODUCTS DATABOOK-1995
Audio Circuits • Video Circuits • Automotive • Special Functions • Surface Mount
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions • Peripheral Functions • LSIIVLSI Functions • Design Guidelines. Packaging
CLOCK GENERATION AND SUPPORT (CGS) DESIGN DATABOOK-1995
Low Skew Clock Buffers/Drivers • Video Clock Generators • Low Skew PLL Clock Generators
Crystal Clock Oscillators
COP8™ DATABOOK-1994
COP8 Family • COP8 Applications • MICROWIRE/PLUS Peripherals • COP8 Development Support
CROSSVOLTTM LOW VOLTAGE LOGIC SERIES DATABOOK AND
DESIGN GUIDE-1996
LCX Family. LVX Translator Family. LVX Bus Switch Family. LVX Family. LVQ Family. LVT Family
ALCX Family • GTL Family
DATA ACQUISITION DATABOOK-1995
Data Acquisition Systems • Analog-to-Digital Converters • Digital-to-Analog Converters • Voltage References
Temperature Sensors. Active Filters. Analog Switches/Multiplexers. Surface Mount
DATA ACQUISITION DATABOOK SUPPLEMENT-1992
New devices released since the printing of the 1989 Data Acquisition Linear Devices Databook.
http://www.national.com
DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides • Diodes • Bipolar NPN Transistors
Bipolar PNP Transistors. JFET Transistors. Surface Mount Products. Pro-Electron Series
Consumer Series • Power Components • Transistor Datasheets • Process Characteristics
DRAM MANAGEMENT HANDBOOK-1993
Dynamic Memory Control • CPU Specific System Solutions • Error Detection and Correction
Microprocessor Applications
EMBEDDED CONTROllERS DATABOOK-1992
COP400 Family • COP800 Family • COPS Applications • HPC Family • HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals • Microcontroller Development Tools
ETHERNET DATABOOK-1996
Integrated Network Interface Controller Products. 10 Mb/s Physical Layer Transceivers and ENDECs
10 Mb/s Repeater Interface Controller Products. 100 Mb/s Fast Ethernet Protocol Products
Glossary and Acronyms
FDDI DATABOOK-1994
Datasheets • Application Notes
F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1992
Family Overview • 300 Series (Low-Power) Datasheets • 100 Series Datasheets • 11 C Datasheets
Design Guide. Circuit Basics • Logic Design. Transmission Line Concepts • System Considerations
Power Distribution and Thermal Considerations. Testing Techniques. 300 Series Package Qualification
Quality Assurance and Reliability • Application Notes
FACTTM ADVANCED CMOS lOGIC DATABOOK-1993
Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations. 54AC174ACXXX. 54ACT174ACTXXX. Quiet Series: 54ACQ174ACQXXX
Quiet Series: 54ACTQ174ACTQXXX. 54FCT174FCTXXX. FCTA: 54FCTXXXAl74FCTXXXAlB
FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators. FIFOs • Counters • TTL Small Scale Integration • Line Driving and System Design
FAST Characteristics and Testing • Packaging Characteristics
HIGH-PERFORMANCE BUS INTERFACE DATABOOK-1994
QuickRing. Futurebus+ /BTL Devices. BTL Transceiver Application Notes. Futurebus+ Application Notes
High Performance TTL Bus Drivers • PI·Bus • Futurebus + /BTL Reference
IBM DATA COMMUNICATIONS HANDBOOK-1992
IBM Data Communications • Application Notes
INTERFACE DATABOOK-1996
LVDS Circuits, Bus Circuits, Data Transmission Circuits, System Design Guide
liNEAR APPLICATIONS HANDBOOK-1994
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated Circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
lOW VOLTAGE DATABOOK-1992
This databook contains information on National's expanding portfolio of low and extended voltage products. Product datasheets
included for: Low Voltage Logic (lVQ), Linear, EPROM, EEPROM, SRAM, Interface, ASIC, Embedded Controllers, Real Time
Clocks, and Clock Generation and Support (CGS).
http://www.national.com
MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors • Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller • SCSI Bus Interface Circuits • Floppy Disk Controllers • Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits • Rigid Disk Microcontroller Circuits • Disk Interface Design Guide
MEMORY DATABOOK-1994
FLASH. CMOS EPROMs • CMOS EEPROMs • PROMs • Application Notes
MEMORY APPLICATIONS HANDBOOK-1994
FLASH • EEPROMs • EPROMs • Application Notes
OPERATIONAL AMPLIFIERS DATABOOK-1995
Operational Amplifiers. Buffers. Voltage Comparators. Active Matrix/LCD Display Drivers
Special Functions • Surface Mount
PACKAGING DATABOOK-1993
Introduction to Packaging. Hermetic Packages. Plastic Packages. Advanced Packaging Technology
Package Reliability Considerations • Packing Considerations • Surface Mount Considerations
POWER IC's DATABOOK-1995
Linear Voltage Regulators • Low Dropout Voltage Regulators • Switching Voltage Regulators
Motion Control • Surface Mount
PRODUCTS FOR WIRELESS COMMUNICATIONS-1996
Radio Transceiver Components • Baseband Processing Components • Control and Signal Processing Components
Non-Volatile Memory • Audio Interface Components • Support Circuitry • Power Management
Complete Cordless Phone Solution
PROGRAMMABLE LOGIC DEVICE DATABOOK AND
DESIGN GUIDE-1993
Product Line Overview • Datasheets • Design Guide: Designing with PLDs • PLD Design Methodology
PLD Design Development Tools • Fabrication of Programmable Logic. Application Examples
REAL TIME CLOCK HANDBOOK-1993
3-Volt Low Voltage Real Time Clocks • Real Time Clocks and Timer Clock Peripherals • Application Notes
RELIABILITY HANDBOOK-1987
Reliability and the Die. Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process • Reliability and the Hybrid Device • VLSIIVHSIC Devices
Radiation Environment • Electrostatic Discharge • Discrete Device • Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation • Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Military/Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. AN/ Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing
SCAN DATABOOK-1996
Design for Test Solutions. Description of Boundary SCAN • SCAN ABT Test Access Logic • SCAN CMOS Test Access Logic
System Test Devices and Software. Application Notes
TELECOMMUNICATIONS-1994
COMBO and SUC Devices • ISDN • Digital Loop Devices • Analog Telephone Components • Software • Application Notes
VHC ADVANCED CMOS LOGIC DATABOOK-1996
This databook introduces National's Very High Speed CMOS (VHC) and Very High Speed TTL Compatible CMOS (VHCT)
designs. The databook includes Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations • VHC Family Datasheets • VHC Specialty Function Datasheets and related Application Notes.
The topics discussed are the advantages of VHCIVHCT AC Performance, Low Noise Characteristics and Improved Interface
Capabilities.
http://www.national.com
NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS
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Time Electronics
(619) 674·2800
San Jose
Anthem Electronics
(408) 453·1200
Future Electronics Corp.
(408) 434·1122
http://www.national.com
San Jose (Continued)
Hamilton/Hallmark
(408) 435·3500
Pioneer Technology
(408) 954·9100
Zeus Elect. an Arrow Co.
(408) 629·4789
Sunnyvale
Bell Industries
(408) 734·8570
Time Electronics
(408) 734·9890
Tustin
TIme Electronics
(714) 669·0216
Westlake Village
Bell Industries
(805) 373·5600
Woodland Hills
Hamilton/Hallmark
(818) 594·0404
Time Electronics
(818) 593·8400
COLORADO
Denver
Bell Industries
(303) 691·9270
Englewood
Anthem Electronics
(303) 790-4500
Hamilton/Hallmark
(303) 790·1662
Pioneer Technology
(303) 773·8090
Time Electronics
(303) 799·5400
Lakewood
Future Electronics Corp.
(303) 232·2008
CONNECTICUT
Cheshire
Future Electronics Corp.
(203) 250-0083
Hamilton/Hallmark
(203) 271·2844
Meriden
Bell Industries
(203) 639·6000
Shelton
Pioneer Standard
(203) 929·5600
Wallingford
Advent Electronics
(800) 982·0014
Waterbury
Anthem Electronics
(203) 575·1575
FLORIDA
Altamonte Springs
Anthem Electronics
(407) 831·0007
Bell Industries
(407) 339-0078
Future Electronics Corp.
(407) 865·7900
Pioneer Technology
(407) 834·9090
Deerfield Beach
Future Electronics Corp.
(305) 426·4043
Pioneer Technology
(305) 428·8877
Fort Lauderdale
Hamilton/Hallmark
(305) 484·5482
Time Electronics
(305) 484·1864
Indialantic
Advent Electronics
(800) 975-8669
Lake Mary
Zeus Elect. an Arrow Co.
(407) 333·9300
Largo
Future Electronics Corp.
(813) 530·1222
Hamilton/Hallmark
(813) 541·7440
Orlando
Chip Supply
"Die Distributor"
(407) 298·7100
Time Electronics
(407) 841·6566
Winter Park
Hamilton/Hallmark
(407) 657·3300
GEORGIA
Duluth
Anthem Electronics
(404) 931·9300
Hamilton/Hallmark
(404) 623·4400
Pioneer Technology
(404) 623·1003
Time Electronics
(404) 623·5455
Norcross
Future Electronics Corp.
(404) 441·7676
ILLINOIS
Addison
Pioneer Standard
(708) 495·9680
Arlington Heights
Hamilton/Hallmark
(708) 797·7300
Des Plaines
Advent Electronics
(800) 323·1270
Elk Grove Village
Bell Industries
(708) 640·1910
Hoffman Estates
Future Electronics Corp.
(708) 882·1255
Itasca
Zeus Elect. an Arrow Co.
(708) 595·9730
Schaumburg
Anthem Electronics
(708) 884·0200
Time Electronics
(708) 303·3000
INDIANA
Carmel
Hamilton/Hallmark
(317) 575·3500
Fort Wayne
Bell Industries
(219) 422·4300
Indianapolis
Advent Electronics Inc.
(800) 732·1453
Bell Industries
(317) 875·8200
Future Electronics Corp.
(317) 469·0447
Pioneer Standard
(317) 573·0880
IOWA
Cedar Rapids
Advent Electronics
(800) 397·8407
Hamilton/Hallmark
(319) 393·0033
KANSAS
Lenexa
Hamilton/Hallmark
(913) 888·4747
Overland Park
Future Electronics Corp.
(913) 649·1531
KENTUCKY
Lexington
Hamilton/Hallmark
(606) 288·4911
MARYLAND
Columbia
Anthem Electronics
(410) 995·6640
Bell Industries
(410) 290·5100
Future Electronics Corp.
(410) 290·0600
Hamilton/Hallmark
(410) 988·9800
Seymour Electronics
(410) 992·7474
Time Electronics
(410) 720·3600
Gaithersburg
Pioneer Technology
(301) 921·0660
MASSACHUSETTS
Andover
Bell Industries
(508) 474·8880
Bolton
Future Electronics Corp.
(508) 779·3000
Lexington
Pioneer Standard
(617) 861·9200
Newburyport
Rochester Electronics
"Obsolete Products"
(508) 462·9332
Norwood
Gerber Electronics
(617) 769·6000
Peabody
Hamilton/Hallmark
(508) 532·3701
Time Electronics
(508) 532·9777
Wilmington
Anthem Electronics
(508) 657·5170
Zeus Elect. an Arrow Co.
(508) 658·0900
MICHIGAN
Farmington Hills
Advent Electronics
(800) 572·9329
Grand Rapids
Future Electronics Corp.
(616) 698·6800
Pioneer Standard
(616) 698·1800
Livonia
Future Electronics Corp.
(313) 261·5270
O'Fallon
Advent Electronics
(800) 888·9588
Plymouth
Hamilton/Hallmark
(313) 416·5800
Pioneer Standard
(313) 416·2157
MINNESOTA
Bloomington
Hamilton/Hallmark
(612) 881·2600
Eden Prairie
Anthem Electronics
(612) 944·5454
Future Electronics Corp.
(612) 944·2200
Pioneer Standard
(612) 944·3355
Minnetonka
Time Electronics
(612) 931·2131
Thief River Falls
Digi·Key Corp.
"Catalog Sales Only"
(800) 344·4539
NATIONAL SEMICONDUCTOR CORPORATION DISTRIBUTORS (Continued)
MISSOURI
Earth City
Hamilton/Hallmark
(314) 291-5350
Manchester
Time Electronics
(314) 230-7500
St. Louis
Future Electronics Corp.
(314) 469-6805
NEW JERSEY
Camden
Advent Electronics
(800) 255-4771
Cherry Hill
Hamilton! Hallmark
(609) 424-0110
Fairfield
Bell Industries
(201) 227-6060
Pioneer Standard
(201) 575-3510
Marlton
Future Electronics Corp.
(609) 596-4080
Time Electronics
(609) 596-1286
Mount Laurel
Bell Industries
(609) 439-8860
Seymour Electronics
(609) 235-7474
Parsippany
Future Electronics Corp.
(201) 299-0400
Hamilton/ Hallmark
(201) 515-1641
Pine Brook
Anthem Electronics
(201) 227-7960
Wayne
Time Electronics
(201) 785-8250
NEW MEXICO
Albuquerque
Bell Industries
(505) 292-2700
Hamilton/Hallmark
(505) 828-1058
NEW YORK
Binghamton
Pioneer Standard
(607) 722·9300
Commack
Anthem Electronics
(516) 864·6600
Fairport
Pioneer Standard
(716) 381-7070
Hauppauge
Future Electronics Corp.
(516) 234·4000
Hamilton/Hallmark
(516) 434·7400
Time Electronics
(516) 273·01 00
Port Chester
Zeus Elect. an Arrow Co.
(914) 937·7400
Rochester
Future Electronics Corp.
(716) 387·9550
Hamilton/Hallmark
(800) 475·9130
Syracuse
Future Electronics Corp.
(315) 451·2371
Time Electronics
(315) 434·9837
Woodbury
Pioneer Standard
(516) 921·9700
TEXAS
Austin
Anthem Electronics
Seymour Electronics
(512) 388·0049
(516) 496·7474
Future Electronics Corp.
NORTH CAROLINA
Charlotte
Future Electronics Corp.
(704) 547·1107
Morrisville
Pioneer Technology
(919) 460·1530
Raleigh
Anthem Electronics
(919) 782·3550
Future Electronics Corp.
(919)790·7111
Hamilton/Hallmark
(919) 872·0712
OHIO
Beavercreek
Future Electronics Corp.
(513) 426·0090
Cleveland
Pioneer Standard
(216) 587·3600
Columbus
Time Electronics
(614) 794·3301
Dayton
Bell Industries
(513) 435·5922
Bell Industries·Military
(513) 434·8231
Hamilton/Hallmark
(513) 439·6735
Pioneer Standard
(513) 236·9900
Mayfield Heights
Future Electronics Corp.
(216) 449·6996
Solon
Bell Industries
(216) 498·2002
Hamilton/Hallmark
(216) 498·1100
Worthington
Hamilton/Hallmark
(614) 888·3313
OKLAHOMA
Tulsa
Hamilton/Hallmark
(918)254·6110
Pioneer Standard
(918) 665·7840
Radio Inc.
(918) 587·9123
OREGON
Beaverton
Anthem Electronics
(503) 643·1114
Bell Industries
(503) 644·3444
Future Electronics Corp.
(503) 645·9454
Hamilton/Hallmark
(503) 526·6200
Pioneer Technology
(503) 626·7300
Portland
Time Electronics
(503) 684·3780
PENNSYLVANIA
Horsham
Anthem Electronics
(215) 443·5150
Pioneer Technology
(215) 674·4000
Pittsburgh
Pioneer Standard
(512) 502·0991
Hamilton/Hallmark
(512) 258·8848
New Berlin
Hamilton/Hallmark
(414) 780·7200
Waukesha
Bell Industries
(414) 547·8879
West Allis
Advent Electronics
Minco Technology Labs.
"Die Distributor"
(800) 500·0441
CANADA
(512) 834·2022
WESTERN PROVINCES
Burnaby
Hamilton/Hallmark
Pioneer Standard
(512) 835·4000
Time Electronics
(512) 219·3773
Carrollton
Zeus Elect. an Arrow Co.
(214) 380·4330
Dallas
Hamilton/Hallmark
(214) 553·4300
Pioneer Standard
(214) 386·7300
Houston
Future Electronics Corp.
(713) 785·1155
Hamilton/Hallmark
(713) 781·6100
(604) 420·4101
Calgary
Electro SoniC Inc.
(403) 255·9550
Future Electronics Corp.
(403) 250·5550
Zentronics/Pioneer
(403) 295·8838
Edmonton
Future Electronics Corp.
(403) 438·2858
Zentronics/Pioneer
(403) 482·3038
Richmond
Electro Sonic Inc.
Pioneer Standard
(604) 273·2911
(713) 495·4700
Zentronics/ Pioneer
Richardson
Anthem Electronics
(214) 238·7100
Bell Industries
(214) 690·9096
Future Electronics Corp.
(214) 437·2437
Time Electronics
(214) 480·5000
UTAH
Midvale
Bell Industries
(801) 255·9691
Salt Lake City
Anthem Electronics
(801) 973·8555
(604) 273·5575
Vancouver
Future Electronics Corp.
(604) 294·1166
EASTERN PROVINCES
Mississauga
Future Electronics Corp.
(905) 612·9200
Hamilton/Hallmark
(905) 564·6060
Time Electronics
(905) 712·3277
Zentronics/Pioneer
(905) 405·8300
Nepean
Hamilton/Hallmark
Future Electronics Corp.
(613) 226·1700
(801) 467·4448
Zentronics/Pioneer
Hamilton/Hallmark
(801) 266·2022
West Valley City
Time Electronics
(801) 973·0208
WASHINGTON
Bellevue
Bell Industries
(206) 646·8750
Pioneer Technology
(206) 644·7500
Bothell
Anthem Electronics
(206) 483·1700
Future Electronics Corp.
(206) 489·3400
Kirkland
Time Electronics
(206) 820-1525
Redmond
Hamilton/Hallmark
(206) 881·6697
WISCONSIN
Brookfield
Future Electronics Corp.
(414) 879·0244
Pioneer Standard
(613) 226·8840
Ottawa
Electro Sonic Inc.
(613) 728·8333
Future Electronics Corp.
(613) 820·8313
Pointe Claire
Future Electronics Corp.
(514) 694·7710
Quebec
Future Electronics Corp.
(418) 877-6666
Ville St. Laurent
Hamilton/Hallmark
(514) 335·1000
Zentronics/Pioneer
(514) 737·9700
Willowdale
Electro Sonic Inc.
(416) 494·1666
Winnipeg
Electro Sonic Inc.
(204) 783·3105
Future Electronics Corp.
(204) 944·1446
Zentronics/Pioneer
(204) 694·1957
(414) 784·3480
Mequon
Taylor Electric
(414) 241-4321
(412) 782·2300
ht1p:llwww.national.com
IfINational Semiconductor
WORLDWIDE SALES OFFICES
AUSTRALIA
National Semiconductor
(Australia) Pty. Ltd.
Bldg. 16 Business Park Dr.
Monash Business Park
Nottinghill Melbourne
Victoria 3168 Australia
Tel: (39) 558·9999
Fax: (39) 558·9998
BRAZIL
National Semlconductores
Do Brazil Ltda.
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Franco 120·3A
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Tel: (55·11) 212·5066
Fax: (55·11) 212·1181
CANADA
National Semiconductor
(Canada)
5925 Airport Road, Suite 615
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Tel: (416) 678·2920
Fax: (416) 678·2837
National Semiconductor
(Canada)
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Tel: (613) 596·0411
Fax: (613) 596·1613
National Semiconductor
(Canada)
1870 Boul Des Sources,
Suite 101
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Tel: (514) 426·2992
Fax: (514) 426·2710
CHINA
.
National Semiconductor
Beijing China Liaison
Office
Room 613 & 614
Sinochem Mansion
No. A2 Fuxingmenwai Avenue
Beijing 100046, PRC
China
Tel: 86·10-8568601
Fax: 86·10·8568606
National Semiconductor
Shanghai China Liaison
Office
B702, Universal Mansion
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FINLAND
National Semiconductor
(U.K.) Ltd.
Mekaanikonkatu 13
SF·00810 Helsinki
Finland
Tel: (0) 759·1855
Fax: (0) 759·1393
FRANCE
National Semiconductor
S.A.
Parc d'Affaires Technopolis
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Tel: (1) 6918 37 00
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National Semiconductor
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Tel: (0·81·41) 35·0
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HONG KONG
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block
Ocean Centre
5 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737·1600
Fax: (852) 2736-9960
INDIA
National Semiconductor
India Liaison Office
1109, 11th Floor, West Wing
Raheja Towers, M.G. Road
Bangalore 560001 India
Tel: 91-80-559·9467
Fax: 91·80·559·9468
ISRAEL
National Semiconductor Ltd.
Maskit Street
PO Box 3007
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Israel
Tel: (09) 59 4255
Fax: (09) 55 83 22
ITALY
National Semiconductor S.p.A.
Strada 7, Palazzo R/3
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Tel: (02) 57 50 03 00
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JAPAN
National Semiconductor
Japan Ltd.
Sumitomo Chemical
Engineering Center Bldg. 8F
1·7·1, Nakase, Mihama·Ku
Chiba·City,
Chiba Prefecture 261
Japan
Tel: 81·043·299·2300
Fax: 81·043·299·2500
KOREA
National Semiconductor
(Far East) Ltd.
13th Floor, Dai Han
Life Insurance 63 Building
60 Yoido·Dong
Youngdeungpo·KU
Seoul Korea 150·763
Tel: (02) 784·8051/3
(02) 785-0696/8
Fax: (02) 784·8054
MALAYSIA
National Semiconductor
SdnBhd
Bayan Lepas Free Trade Zone
11900 Penang Malaysia
Tel: 4-644-9061
Fax: 4-644·9073
MEXICO
Electronlca NSC de
Mexico SA
Juventino Rosas No. 118-2
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Mexico, 01020 D.E. Mexico
Tel: (525) 661·7155
Fax: (525) 661-6905
PUERTO RICO
National Semiconductor
(Puerto Rico)
La Electronica Bldg.
Suite 312, A.D. #1 KM 14.5
RioPiedias
Puerto Rico 00927
Tel: (809) 758·9211
Fax: (809) 763-6959
SINGAPORE
National Semiconductor
Asia Pacific Pte. Ltd.
200 Cantonment Road # 13·01
South point Singapore 0208
Tel: (65) 225·2226
Fax: (65) 225·7080
SPAIN
National Semiconductor GmbH
Calle Almendralejos, 4
28140 Fuente el Saz del Jarama
Madrid, Spain
Tel: (01) 620 1425
Fax: (01) 620 0612
SWEDEN
National Semiconductor AB
P.o. Box 1009
Grosshandlarv!lgen 7
S·12123 Johanneshov,
Sweden
Tel: (08) 7 22 80 50
Fax: (08) 7 22 90 95
SWITZERLAND
National Semiconductor
(U.K.) Ltd.
Alte Winterthurerstrasse 53
CH-8304 Wallisellen-Ziirich
Switzerland
Tel: (01) 8·30·27·27
Fax: (01) 8·30·19-00
TAIWAN
National Semiconductor
(Far East) Ltd.
9/F, No. 44 Section 2
Chungshan North Road
Taipei, Taiwan, A.O.C.
Tel: (02) 521·3288
Fax: (02) 561-3054
U.K. AND IRELAND
National Semiconductor
(U.K.) Ltd.
1st Floor
Milford House
Milford Street
Swindon, Wiltshire SNllDW
United Kingdom
Tel: (07·93) 614141
Fax: (07-93) 52 21 80
Telex: 444674
UNITED STATES
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: (800) 272·9959
Fax: (800) 737·7018
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