1996_S MOS_Graphics_Products_Data_Book 1996 S MOS Graphics Products Data Book
User Manual: 1996_S-MOS_Graphics_Products_Data_Book
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S-MOS
S Y S T EMS
A Seiko Epson Affiliate
1996
Graphics
Products
Data Boole
s
y
s
T
E
M
s
A Seiko Epson Affiliate
1996
DATABOOK
GRAPHICS
PRODUCTS
For more information on S-MOS products and services, as well as a
continuously updated version of the Graphics Products databook, you
may access the S-MOS web site at http://www.smos.com.
SoMas assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or
a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages.
There are no warranties extended or granted by this document. The information herein is subject to change without notice from SoMas.
January 1996
© Copyright 1996 SoMaS Systems, Inc.
Printed in U.S.A.
000-96-GRA-O.2
THIS PAGE INTENTIONALLY BLANK
s- os
s
Y
S
T
EMS
A Seiko Epson Affiliate
Overview
VGA Graphics
Controllers
Graphic LCD
Controllers
LCD DriverControllers
High-Duty LCD
Segment Drivers
High-Duty LCD
Common Drivers
DCIDC Converters
VFDDrivers
Related Products
Package Information
THIS PAGE INTENTIONALLY BLANK
iv
TABLE OF CONTENTS
TABLE OF CONTENTS
I. OVERViEW .......................................................................................... xiii
II. VGA GRAPHICS CONTROLLERS ....................................................... 1
SPC81 04FOA ............................................................................................................... 5
SPC81 06FOC ............................................................................................................ 21
SPC81 07FOE ............................................................................................................ 53
SPC81 08FOC ............................................................................................................ 69
SPC811 OFOA ............................................................................................................. 87
III. GRAPHIC LCD CONTROLLERS ..................................................... 121
SED1330 ................................................................................................................. 125
SED1335 ................................................................................................................. 139
SED1336 ................................................................................................................. 153
SED1341 ................................................................................................................. 165
SED1345 ................................................................................................................. 185
SED1351 ................................................................................................................. 197
SED1352FOA ........................................................................................................... 215
IV. LCD DRIVER-CONTROLLERS ........................................ ............... 231
SED1200 ................................................................................................................. 237
SED121 0 ................................................................................................................. 253
SED1230 Series ...................................................................................................... 265
SED1278 ................................................................................................................. 287
SED1280 ................................................................................................................. 303
SED1500 Series ...................................................................................................... 307
SED1510 ................................................................................................................. 315
SED1520/21 ............................................................................................................ 329
SED152A ................................................................................................................. 341
SED1522 ................................................................................................................. 343
SED1526 Series ...................................................................................................... 353
SED1530 Series ...................................................................................................... 369
SED1540 ................................................................................................................. 389
SED1560 Series ...................................................................................................... 395
V. HIGH-DUTY LCD SEGMENT DRIVERS ........................................... 421
SED1180 ................................................................................................................. 425
SED1181 ................................................................................................................. 435
SED1181 FLAIDLA ................................................................................................... 443
SED1570 ................................................................................................................. 453
SED1600 ................................................................................................................. 469
SED1601 ................................................................................................................. 479
SED1606DOAIDOB .................................................................................................. 489
SED1620 ................................................................................................................. 503
v
TABLE OF CONTENTS
SED1640 ................................................................................................................. 513
SED1648 ................................................................................................................. 525
SED1681 ................................................................................................................. 539
SED1722/24 ............................................................................................................ 551
SED1742/44 ............................................................................................................ 563
SED1748 ................................................................................................................. 583
SED1752TOA ........................................................................................................... 599
SED1756DOA .......................................................................................................... 615
SED1758 ................................................................................................................. 627
SED1765 ................................................................................................................. 645
SED1766 ................................................................................................................. 657
SED1770171 ............................................................................................................ 673
SED17 AOT ............................................................................................................... 687
VI. HIGH-DUTY LCD COMMON DRiVERS ........................................... 701
SED1190 ................................................................................................................. 705
SED1191 ................................................................................................................. 713
SED1610 ................................................................................................................. 721
SED1630 ................................................................................................................. 727
SED1631 ................................................................................................................. 733
SED1632 ................................................................................................................. 741
SED1633 ................................................................................................................. 747
SED1634 ................................................................................................................. 759
SED1635 ................................................................................................................. 771
SED1651 ................................................................................................................. 783
SED1733 ................................................................................................................. 795
SED1741 ..........................................................................................;...................... 805
SED1743 ................................................................................................................. 819
SED1753 ................................................................................................................. 835
SED1755DOA .......................................................................................................... 849
VII. DC/DC CONVERTERS ................................................................... 863
SCI7660C/MSeries .................................................................................................. 867
SCI7661 C/MSeries .................................................................................................. 873
SCI7654 ................................................................................................................... 879
VIII. VFD DRiVERS ................................................................................ 893
SED2000FOAlOB .................................................................................................... 895
SED2000FVB .......................................................................................................... 899
SED2020FOAlOB .................................................................................................... 901
SED2032FOB .......................................................................................................... 907
IX. RELATED PRODUCTS/MCU .......................................................... 911
X. QA & PACKAGE INFORMATION .................................................... 915
vi
-----------------------------------ALPHANUMERIC INDEX
"'-~
ALPHANUMERIC INDEX
SCI7654COA ................ CMOS DC/DC Converter ........................................................ 879
SCI7654MOA ................ CMOS DC/DC Converter ........................................................ 879
SCI7660COA ................ CMOS DC/DC Converter ........................................................ 867
SCI7660MOA ................ CMOS DC/DC Converter ........................................................ 867
SCI7661 COA ................ CMOS DC/DC Converter ........................................................ 873
SCI7661 MOA ................ CMOS DC/DC Converter ........................................................ 873
SCI7700Y** .................. CMOS Voltage Detector ............................................................. *1
SCI7701Y** .................. CMOS Voltage Detector ............................................................. *1
SCI7710Y** .................. CMOS Voltage Regulator ........................................................... *1
SCI7711Y** .................. CMOS Voltage Regulator ........................................................... *1
SED1180DOA ............... LCD Driver 64 Columns ....................................................... 425*2
SED1180FOA ............... LCD Driver 64 Columns ....................................................... 425*2
SED1180F5A ............... LCD Driver 64 Columns ....................................................... 425*2
SED1181 DLA ............... LCD Driver 64 Columns, Low Voltage ................................. 443*2
SED1181 FOA ............... LCD Driver 64 Columns ....................................................... 435*2
SED1181 F5A ............... LCD Driver 64 Columns ....................................................... 435*2
SED1181 FLA ............... LCD Driver 64 Columns, Low Voltage ................................. 443*2
SED1190DOA ............... LCD Driver 64 Rows ............................................................ 705*2
SED1190FOA ............... LCD Driver 64 Rows ............................................................ 705*2
SED1190F5A ............... LCD Driver 64 Rows ............................................................ 705*2
SED1191 FOB ............... LCD Driver 64 Rows ............................................................ 713*2
SED1191 F5B ............... LCD Driver 64 Rows ............................................................ 713*2
SED1200DOA-OB ......... LCD Driver & Controller, 10 char x 2 line ................................ 237
SED1200FOA-OB .......... LCD Driver & Controller, 10 char x 2 line ................................ 237
SED1200F1 B ............... LCD Driver & Controller, 10 char x 2 line ................................ 237
SED1210DOA-OB ......... LCD Driver & Controller, 8 char x 2 line .................................. 253
SED1210FOA-OB .......... LCD Driver & Controller, 8 char x 2 line .................................. 253
SED122* ...................... LCD Driver & Controller ............................................................. *1
SED1230DAAlBAIGA .. LCD Driver & Controller, 12 char x 4 line ................................. 265
SED1230DAB/BB/GB .. LCD Driver & Controller, 12 char x 4 line ................................ 265
SED1230TOA ............... LCD Driver & Controller, 12 char x 4 line ................................ 265
SED1231DAAlBAIGA .. LCD Driver & Controller, 12 char x 3 line ................................ 265
SED1231DAB/BB/GB .. LCD Driver & Controller, 12 char x 3 line ................................ 265
SED1231TOA ............... LCD Driver & Controller, 12 char x 3 line ................................ 265
SED1232DAAlBAIGA .. LCD Driver & Controller, 12 char x 2 line ................................ 265
SED1232DAB/BB/GB .. LCD Driver & Controller, 12 char x 2 line ................................ 265
SED1232TOA ............... LCD Driver & Controller, 12 char x 2 line ................................ 265
SED1233DAAlBAIGA .. LCD Driver & Controller, 16 char x 4 line ................................ 265
SED1233DAB/BB/GB .. LCD Driver & Controller, 16 char x 4 line ................................ 265
SED1233TOA ............... LCD Driver & Controller, 16 char x 4 line ................................ 265
SED1234DAAlBAIGA .. LCD Driver & Controller, 12 char x 4 line ................................ 265
SED1235DAAlBAIGA .. LCD Driver & Controller, 12 char x 2 line ................................ 265
SED1278DOA-DOH ...... LCD Driver & Controller, 8 char x 2 line .................................. 287
SED1278FOA-FOH ....... LCD Driver & Controller, 8 char x 2 line .................................. 287
*1. Omitted from the 1996 Graphics Data Book.
*2. Discontinued.
vii
ALPHANUMERIC INDEX
SED1280FOA-OC ......... LCD Driver & Controller, 8 char x 2 line .................................. 303
SED1330FBA ............... LCD Controller ........................................................................ 125
SED1330FBB ............... LCD Controller ........................................................................ 125
SED1335FOA ............... LCD Controller, Low Voltage ................................................... 139
SED1335FOB ............... LCD Controller, Low Voltage ................................................... 139
SED1336FOA ............... LCD Controller, NTSC Out.. .................................................... 153
SED1341 FOE/FOC ....... LCD Controller, Digital RGB In ................................................ 165
SED1345FOA ............... LCD Controller, Digital RGB In ................................................ 185
SED1348FOA ............... LCD Controller w/RAMDAC, Dig RGB In ................................... *1
SED1351 FOA ............... LCD Controller, 4 Grey Shades .............................................. 197
SED1351 FLB ............... LCD Controller, 4 Grey Shades, Low Voltage ......................... 197
SED1352FOA ............... LCD Controller, 16 Grey Shades, ISA bus .............................. 215
SED1500F .................... LCD Driver & Controller, 42 x 8 ............................................ 307*2
SED1501 F .................... LCD Driver & Controller, 40 x 10 .......................................... 307*2
SED1502F .................... LCD Driver & Controller, 34 x 16 .......................................... 307*2
SED1503F .................... LCD Driver & Controller, 42 x 8 ............................................ 307*2
SED1507F .................... LCD Driver & Controller, 42 x 7 ............................................ 307*2
SED151 ODOC ............... LCD Driver & Controller, 32 x 4 ............................................... 315
SED151 OFOC ............... LCD Driver & Controller, 32 x 4 ............................................... 315
SED1510FOE ............... LCD Driver & Controller, 32 x 4 ............................................... 315
SED1520DAAlOA ......... LCD Driver & Controller, 61 x 16 ............................................. 329
SED1520DAB/OB ......... LCD Driver & Controller, 61 x 16 ............................................. 329
SED1520FAAlOA ......... LCD Driver & Controller, 61 x 16 ............................................. 329
SED1520FAC/OC ......... LCD Driver & Controller, 61 x 16 ............................................. 329
SED1521 DAAlOA ......... LCD Driver & Controller, 80 Columns ..................................... 329
SED1521 DAB/OB ......... LCD Driver & Controller, 80 Columns ..................................... 329
SED1521 FAAlOA ......... LCD Driver & Controller, 80 Columns ..................................... 329
SED1521 FAC/OC ......... LCD Driver & Controller, 80 Columns ..................................... 329
SED1522DAAlOA ......... LCD Driver & Controller, 69 x 8 ............................................... 343
SED1522DAB/OB ......... LCD Driver & Controller, 69 x 8 ............................................... 343
SED1522FAAlOA ......... LCD Driver & Controller, 69 x 8 ............................................... 343
SED1522FAC/OC ......... LCD Driver & Controller, 69 x 8 ............................................... 343
SED1526DOA ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1526DOB ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1526FOA ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1526TOA ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1527DOA ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1527DOB ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1527FOA ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1527TOA ............... LCD Driver & Controller, 80 x 17 ............................................. 353
SED1528DOA ............... LCD Driver & Controller, 64 x 33 ............................................. 353
SED1528DOB ............... LCD Driver & Controller, 64 x 33 ............................................. 353
SED1528FOA ............... LCD Driver & Controller, 64 x 33 ............................................. 353
SED1528TOA ............... LCD Driver & Controller, 64 x 33 ............................................. 353
SED1530DOA ............... LCD Driver & Controller, 100 x 33 ........................................... 369
SED1530DOB ............... LCD Driver & Controller, 100 x 33 ........................................... 369
*1. Omitted from the 1996 Graphics Data Book.
*2. Discontinued.
viii
ALPHANUMERIC INDEX
SED1530TOA ............... LCD
SED1531 DOA ............... LCD
SED1531 DOB ............... LCD
SED1531TOA ............... LCD
SED1532DOA ............... LCD
SED1532DOB ............... LCD
SED1532TOA ............... LCD
SED1540DOA ............... LCD
SED1540DOB ............... LCD
SED1540FOA ............... LCD
SED1560DOA ............... LCD
SED1560DOB ............... LCD
SED1560TOB ............... LCD
SED1560TQA .............. LCD
SED1561 DOA ............... LCD
SED1561 DOB ............... LCD
SED1561TOB ............... LCD
SED1561TQA .............. LCD
SED1562DOA ............... LCD
SED1562DOB ............... LCD
SED1562TOB ............... LCD
SED1562TQA .............. LCD
SED1570DOA ............... LCD
SED1570DOB ............... LCD
SED1600DAA .............. LCD
SED1600DAB .............. LCD
SED1600FAA ............... LCD
SED1601DAA .............. LCD
SED1601 FAA ............... LCD
SED1606DOA ............... LCD
SED1606DOB ............... LCD
SED1610FAA ............... LCD
SED1620DOA ............... LCD
SED1630DOA ............... LCD
SED1630FOA ............... LCD
SED1631 DOA ............... LCD
SED1631 DOB ............... LCD
SED1632DOA ............... LCD
SED1633D1A ............... LCD
SED1633D1B ............... LCD
SED1634D1 A ............... LCD
SED1634D1 B ............... LCD
SED1635D1 A ............... LCD
SED1635D1 B ............... LCD
SED1640DOB ............... LCD
SED1648DOA ............... LCD
Driver & Controller, 100 x 33 ........................................... 369
Driver & Controller, 132 Columns ................................... 369
Driver & Controller, 132 Columns ................................... 369
Driver & Controller, 132 Columns ................................... 369
Driver & Controller, 132 Columns ................................... 369
Driver & Controller, 132 Columns ................................... 369
Driver & Controller, 132 Columns ................................... 369
Driver & Controller, 73 x 4 ............................................... 389
Driver & Controller, 73 x 4 .. ,............................................ 389
Driver & Controller, 73 x 4 ............................................... 389
Driver & Controller, 102 x 65 ........................................... 395
Driver & Controller, 102 x 65 ........................................... 395
Driver & Controller, 102 x 65 ........................................... 395
Driver & Controller, 102 x 65 ........................................... 395
Driver & Controller, 134 x 33 ........................................... 395
Driver & Controller, 134 x 33 ........................................... 395
Driver & Controller, 134 x 33 ........................................... 395
Driver & Controller, 134 x 33 ........................................... 395
Driver & Controller, 150 x 17 ........................................... 395
Driver & Controller, 150 x 17 ........................................... 395
Driver & Controller, 150 x 17 ........................................... 395
Driver & Controller, 150 x 17 ................................. '" ....... 395
Driver with RAM, 80 Columns ........................................ .453
Driver with RAM, 80 Columns ......................................... 453
Driver 80 Columns .......................................................... 469
Driver 80 Columns .......................................................... 469
Driver 80 Columns ....................................................... 469*2
Driver 80 Columns ....................................................... 479*2
Driver 80 Columns ....................................................... 479*2
Driver 80 Columns .......................................................... 489
Driver 80 Columns .......................................................... 489
Driver 86 Rows ............................................................ 721*2
Driver 128 Columns ..................................................... 503*2
Driver 68 Rows ............................................................ 727*2
Driver 68 Rows ............................................................ 727*2
Driver 100 Rows .......................................................... 733*2
Driver 100 Rows .......................................................... 733*2
Driver 86 Rows ............................................................ 741 *2
Driver 100 Rows .......................................................... 747*2
Driver 100 Rows .......................................................... 747*2
Driver 100 Rows .......................................................... 759*2
Driver 100 Rows .......................................................... 759*2
Driver 100 Rows .......................................................... 771 *2
Driver 100 Rows .......................................................... 771 *2
Driver 80 Columns .......................................................... 513
Driver 80 Columns .......................................................... 525
*1. Omitted from the 1996 Graphics Data Book.
*2. Discontinued.
ix
ALPHANUMERIC INDEX
SED1651 DOA ............... LCD Driver 100 Rows ............................................................. 783
SED1681 DOA ............... LCD Driver 80 Columns ....................................................... 539*2
SED1681 FOA ............... LCD Driver 80 Columns ....................................................... 539*2
SED1722DOA ............... LCD Driver 80 Columns .......................................................... 551
SED1722FOA ............... LCD Driver 80 Columns .......................................................... 551
SED1724DOA ............... LCD Driver 80 Columns .......................................................... 551
SED1724FOA ............... LCD Driver 80 Columns .......................................................... 551
SED1733DOA ............... LCD Driver 100 Rows ............................................................. 795
SED1733FOA ............... LCD Driver 100 Rows ............................................................. 795
SED1741D1B ............... LCD Driver 100 Rows ............................................................. 805
SED1741T1B ............... LCD Driver 100 Rows ............................................................. 805
SED1742D1 B ............... LCD Driver, 160 Columns ....................................................... 563
SED1742TOA ............... LCD Driver, 160 Columns ....................................................... 563
SED1743D1B ............... LCD Driver, 160 Rows ............................................................ 819
SED1743TOA ............... LCD Driver, 160 Rows ............................................................ 819
SED1744D1B ............... LCD Driver, 160 Columns ....................................................... 563
SED1744TOA ............... LCD Driver, 160 Columns ....................................................... 563
SED1748DOB ............... LCD Driver, 160 Columns ....................................................... 583
SED1748TOA ............... LCD Driver, 160 Columns ....................................................... 583
SED1752TOAIB ............ LCD Driver, 160 Columns ....................................................... 599
SED1753DOB ............... LCD Driver, 160 Columns ....................................................... 835
SED1753TOA ............... LCD Driver, 160 Columns ....................................................... 835
SED1755DOA ............... LCD Driver, 160 Columns ....................................................... 849
SED1756DOA ............... LCD Driver, 160 Columns ....................................................... 615
SED1758DOB ............... LCD Driver, 160 Columns ....................................................... 627
SED1758TOA ............... LCD Driver, 160 Columns ....................................................... 627
SED1765DOA ............... LCD Driver, 160 Columns ....................................................... 645
SED1765DOB ............... LCD Driver, 160 Columns ....................................................... 645
SED1765TOA ............... LCD Driver, 160 Columns ....................................................... 645
SED1766DOA ............... LCD Driver, 160 Columns ....................................................... 657
SED1766DOB ............... LCD Driver, 160 Columns ....................................................... 657
SED1766TOA ............... LCD Driver, 160 Columns ....................................................... 657
SED1767TOA ............... LCD Driver, 160 Columns, 40V Out ........................................... *1
SED1767T1 A ............... LCD Driver, 160 Columns, 40V Out ........................................... *1
SED1770DOA ............... LCD Driver, 160 Columns ....................................................... 673
SED1771 DOA ............... LCD Driver, 160 Columns ....................................................... 673
SED1790T .................... LCD Driver, 120 Columns .......................................................... *1
SED17AOT ................... LCD Driver, 240 Columns, 40V Out ........................................ 687
SED1902T .................... LCD Driver, 240 Columns .......................................................... *1
SED2000FVB ............... VFD Driver 20 bits ................................................................... 899
SED2020FOA ............... VFD Driver 16bits x 2 .............................................................. 901
SED2020FOB ............... VFD Driver 16bits x 2 .............................................................. 901
SED2032FOB ............... VFD Driver 16bits x 2 .............................................................. 907
SED2800FVA ............... VFD Driver 20bits x 4 ................................................................. *1
SPC8104FOA ............... Low Voltage LCD Controller - 2.5V ............................................. 5
*1. Omitted from the 1996 Graphics Data Book.
*2. Discontinued.
x
SPC8106FOC
SPC8107FOE
SPC8108FOC
SPC8110FOA
............... Color VGA LCD Controller ........................................................ 21
............... Low Voltage VGA LCD Controller - 3.3V .................................. 53
............... Monochrome VGA LCD Controller ............................................ 69
............... Local Bus VGA LCD Controller ................................................. 87
*1. Omitted from the 1996 Graphics Data Book.
*2. Discontinued.
xi
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THIS PAGE INTENTIONALLY BLANK
xii
I. OVERVIEW
1996
DATABOOK
GRAPHICS
PRODUCTS
xiii
THIS PAGE INTENTIONALLY BLANK
xiv
OVERVIEW
PRODUCT SUMMARY TABLES
The following pages contain product summary tables for all the S-MOS Graphics Products in this Data Book.
xv
I
•
VGA GRAPHICS CONTROLLERS FEATURES MATRIX
SPC8104 FOA
SPC8106FOC
SPC8107FOE
SPC8108FOC
SPC8110F OA
Low Voltage LCD
VGA Controller
Mixed Voltage
Color LCD VGA
Controller
Low Voltage
VGA LCD
Controller
Low Power LCD
VGA Controller
Local Bus
LCD/CRTVGA
Controller
Discontinued?
No
No
No
No
No
Replacement
-
-
-
-
-
CRT Support
No
w/ external
RAMDAC
w/ external
RAMDAC
Yes
8-bit single/dual
x
x
x
16-bit single/dual
x
x
x
x
x
Part Number
Part Name
Color LCD Support
9-bitTFT
No
12-bit TFT
x
18-bit TFT
x
12-bit RGB
Monochrome LCD Support
~.
CPU Bus Interface
x
,
4-bit single panel
x
x
x
x
x
I
8-bit single/dual
panel
x
x
x
x
X
I
ISA-8bit
x
x
x
ISA-16bit
x
x
I
i
x
VL-32bit
x
PC12.0
x
486DX Local bus
Display Resolution
On-chip Color Lookup Table
Maximum Color
Weightings
Frame Buffer Support
(continued)
320x200 to
640x480
320x200 to
640x480
320x200 to
640x480
320x200 to
1024x768
64x4
256x12
64x4
256x6
256x18
256
256
CRT
256
color LCD
256
16
Maximum Grade Shades
Programmable Grayscale
x
320x200 to
64Ox480
64
256
16
64
64
(30,59,11)
(25,50,25)
base
NTSC
(30,59,11)
(30,59,11)
(30,59,11)
(30,59,11)
text
(0,100,0)
(0,100,0)
(0,100,0)
(0,100,0)
(0,100,0)
one 256kx16
DRAM
one 256kx16
DRAM
one 256kx16
DRAM
one 256kx16
DRAM
two 256Kx16
DRAM
i
•
VGA GRAPHICS CONTROLLERS FEATURES MATRIX (continued)
r-------
Part Number
SPC8104 FOA
SPC8106FOC
SPC8107FOE
SPC8108FOC
SPC8110F OA
16
16
16
16
32
Self Refresh DRAM Support
x
x
x
x
x
Selectable CASIWE DRAM Configuration
x
x
x
x
x
Asymmetrical/Symmetrical
x
x
x
x
x
Frame Buffer Data Bus Width (bits)
DRAM Support
Simultaneous Display
Power Save Modes
w/ single panel
LCD
I HIW Activated
I SIW Activated
I/O Interface Voltage
Core Voltage
(# of pins)
1
1
1
1
2
5
5
5
5
2
x
x
x
x
64x64x2
64x64x2
x
x
x
x
5V
x
3.3V
x
5V
3.3V
x
2.5 or 3.3
Sprite/Hardware Cursor (bits)
~:
Yes
x
x
x
x
64x64x2
Hardware Vertical Centering
x
x
Hardware Vertical Expansion
x
x
x
x
x
Bit Block Transfer Engine (BitBLT)
x
Linear Addressing
x
Color Expansion
x
4-stage
4-stage
4-stage
4-stage
32-bit
MClk,max
28.322 MHz
28.322 MHz
28.322 MHz
28.322 MHz
40MHz
PClk,max
28.322 MHz
28.322 MHz
28.322 MHz
28.322 MHz
65MHz
Package
144-pin OFP
144-pin OFP
100-pin OFP
144-pin OFP
208-pin OFP
5
21
53
69
Display Pipeline
Integrated PLL
Page Number
2
87
---------
-
•
GRAPHIC LCD CONTROLLERS
Part Number
Discontinued?
SED1330
SED1335
No
No
Replacement
-
-
SED1336
No
SED1341
-
-
No
SED1345
No
SED1351
No
SED1352
-
-
-
160 chars (5x7)
160 chars (5x7)
CPU
68xx
8
8
8
8, 16
8, 16
Interface
80xx
8
8
8
8, 16
8, 16
(Bits)
MPU
8, 16
8, 16
Internal CGROM
160 chars (5x7)
4
4
1(R or G or B)
4 (R,G,B,I)
ISA
8, 16
Digital
RGB
up to 640x256
up to 640x256
dots at a duty of dots at a duty of
1/256
1/256
Display Size
~:
No
LCD: 640x200,
TV: 256x200
adjusted by HJW adjusted by S/W
640x200
640x200
64Ox350
640x350
640x400
640x400
640x480
640x480
720x350
720x480
max. duty of
1/1024
up to
1024x1 024
1/1024 single
mode,
1/2048 dual
mode,
64Ox480,
320x200
64KB SRAM
64KB SRAM
64KB SRAM
40KB SRAM
40KB SRAM
64KB SRAM
128KB SRAM
Frame Buffer Data
Bus Width (bits)
8
8
8
8
8
16
8/16
fclk,max (MHz)
10
10
10
11.2
12.5
22
fosc (MHz)
10
10
10
34
30
14.29
25
x
x
x
x
x
FOA
x
x
x
x
FLB
x
x
x
x
x
Frame Buffer
Support
Supply voltage 5V
3V
Gray shade
levels
2
x
x
4
x
8
x
16
Display Data
4
Bus (bits)
8
(continued)
x
x
x
x
x
x
x
x
x
x
x
I
•
GRAPHIC LCD CONTROLLERS (continued)
Part Number
SED1330
Control Register
Panel Type Passive
SED1335
x
x
TV
Package
QFP
Page Number
SED1336
SED1341
SED1345
SED1351
Set by ROM or
MPU for panel
size, panel
timing, clock
select
2 layers, data
OR function,
smooth
scrolling,
overlay, inverse
video
x
x
x
FOE
(QFP5-80pin)
FOA
(QFP5-80pin)
FOA
(QFP5-100pin),
FLB
(QFP15-100pin)
FOA
(QFP5-100pin)
165
----
185
197
215
3 layers, smooth 3 layers, smooth LCDflV support,
Set by digital
scrolling, inverse scrolling, inverse 3 layers, smooth switches or MPU
video, text and
video, text and scrolling, inverse
for panel size,
graphic display
graphic display
video, text and
panel timing,
graphic display
clock select
x
SED1352
x
ntsc/pal
FBA
(QFP5-60pin),
FBB
(QFP6-60pin)
FOA
(QFP5-60pin),
FOB
(QFP6-60pin)
125
139
FOA
(QFP6-60pin)
"--- ___~53 __
-
-
Notes: 1. Some packages of certain parts labeled with # are still under development.
~.
-
•
LCD DRIVER-CONTROLLERS (12xx Series)
Part Number
SED
1200
SED
1210
SED
1230
SED
1231
T
E
X
T
Discontinued?
Replacement
Commons
Segments
Duty Cycle
No
No
No
No
No
No
-
-
-
-
-
16
50
16
40
30
65
23
65
16
65
x
x
x
x
113
1/4
1f7
118
1/9
SED
1232
SED
1233
SED
1234
SED
1235
SED
1278
SED
1280
No
No
No
No
-
-
-
-
-
16
80
30
16
62
16
40
16
40
x
x
x
x
x
x
x
-4.5 to
-12
-3 to
-5.5
-3 to
-5.5
x
x
62
1/10
1/11
1/16
1/17
1/23
1/24
1/25
1/30
1/32
1/33
~
x
x
x
x
x
1/48
1/49
1/64
1/65
LCD Voltage (V)
Supply Voltage
CPU Interface
-_..
(continued)
-----
5V
3V
MPU
68xx
80xx
--~
-3.5 to
-5.5
-3.5 to
-5.5
x
x
x
x
x
x
x
x
-4.5 to
-12
x
x
x
x
-4.5 to
-12
x
x
x
x_~_
-4.5 to
-12
x
x
x
x
- - _.... _ - -
-4.5 to
-12
-
-
x
x
x
x
-4.5 to
-12
x
x
x
x
x
x
x
x
x
x
I
•
LCD DRIVER-CONTROLLERS (12xx Series - continued)
Part Number
SED
1200
SED
1230
SED
1231
SED
1232
SED
1233
SED
1234
SED
1235
T
E
X
T
x
x
x
x
x
x
x
x
x
x
x
x
x
SED
1278
SED
1280
x
x
x
x
x
x
x
Fosc,max (KHz)
100
100
39
30
21
26
250
1000
CGROM Size (chars)
160
160
256
256
256
256
240
240
CGRAM size (chars)
4
4
4
4
4
4
8
8
20 char
40 char
48 char
48 char
48 char
48 char
80 char
80 char
1181,
1681
1181,
1681
x
x
Display Data Bus (bits)
1
4
x
8
Display Data RAM size
Companion Chips
~.
SED
1210
48 char
48 char
1181
Integrated DC/DC Converter
x
x
x
Static Icon
x
x
x
x
Contrast Adjustment By Software
x
x
x
x
x
x
x
Master/Slave Operation
Panel Type
Passive
x
x
x
x
x
x
DOA(JIS)
DOB
(ASCII)
DOA(JIS)
DOB
(ASCII)
DOA
DOA
DOA
DOA
DOA
DOA
DOB
DOB
DOB
DOB
DOB
DOB
110
110
110
110
MIM
TFT
Package
Die
AI
Au
DOA DOB
DOC DOE
DOG DOH
COG
QFP
PadPitch (11m)
190
Thin
F1B
Thick
FOA (JIS)
FOB
(ASCII)
FOA (JIS)
FOB
(ASCII)
80
80
# of Pins
TAB
190
2sided
TBB
TBB
TBB
TBB
265
265
265
265
FOA FOB
FOe FOE
FOG FOH
FOA
FOB
FOC
80
100
287
303
4sided
LeadPitch (11m)
Page Number
(continued)
237
253
265
265
-
•
LCD DRIVER-CONTROLLERS (15xx Series)
Part Number
SED
1500
SED
1501
SED
1502
SED
1507
Yes
SED
1503
E
Yes
Discontinued?
Yes
Yes
Replacement
No
No
No
No
No
Commons
Segments
8
42
10
40
16
8
42
7
43
T
Duty Cycle
34
SED
1510
SED
1520
SED
1521
SED
1526
SED
1527
SED
1528
SED
1530
SED
1531
SED
1532
SED
1540
T
&
No
A
P
H
I
C
5
No
G
No
R
No
No
No
No
No
No
No
No
No
No
No
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
61
0
80
33
100
0
132
33
100
4
32
0
8
17
17
33
80
69
80
80
64
4
73
33
17
134
150
x
x
x
1/16
x
x
x
x
x
x
x
x
x
x
x
x
1/17
x
x
x
x
x
x
x
x
x
x
x
x
x
1/23
1/24
x
1/25
1/30
x
x
x
x
x
x
x
1/32
x
x
x
x
1/33
1/48
x
x
x
x
x
x
x
1/49
1/64
1/65
-3 to
-10
-3 to
-10
-3 to
-10
5V
x
3V
x
x
x
x
x
x
x
x
x
MPU
x
x
x
x
x
LCD Voltage (V)
-3 to -3 to
-10
-10
-1.8
to -6
-3.5
to
-13
-3.5
to
-13
x
x
x
x
x
x
x
x
68xx
80xx
Display Data Bus (bits) 1
4
8
(continued)
65/0
102/
165
x
x
1/11
Fosc,max (KHz)
SED
1562
No
x
1/9
1/10
CPU Interface
SED
1561
X
x
1/8
Supply Voltage
SED
1560
Yes
1/3
1/4
117
~:
SED SED
152A 1522
x
32
x
x
x
x
x
x
x
x
32
32
32.
32
18
x
x
x
-6 to
-16
-5 to
-16
-4.5
to
-16
x
-3.5
to
-13
-4.5
to
-16
-4.5
to
-16
-4.5
to
-16
-4.5
to
-16
-4.5
to
-16
-4.5
to
-16
-3.5
to
-11
x
x
x
x
x
x
x
x
x
x
x
x
x
+3.5
to
+13
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
22
x
x
4,18
18
x
18
18
x
x
x
x
x
x
x
x
2,18
2,18
2
2,18
20
_.
x
x
x
x
20
20
22
22
x
•
LCD DRIVER-CONTROLLERS (15xx Series - continued)
Part Number
Display Data RAM size
SED
1500
672
bits
SED
1501
672
bits
SED
1502
672
bits
SED
1503
672
bits
SED
1507
SED
1510
SED
1520
SED
1521
672
bits
128
bits
2560
bits
1520
2560
bits
Companion Chips
SED SED
152A 1522
2560 2560
bits
bits
SED
1527
2640
bits
1527
SED
1528
2640
bits
2x,
3x
2x,
3x
2x,
3x
x
x
x
x
x
x
Integrated DC/DC Converter
SED
1526
2640
bits
SED SED
1530 1531
SED
1532
8580
bits
8580
bits
8580
bits
1635
1532
x
x
x
x
x
x
x
x
x
x
x
x
x
Static Icon
Contrast Adjustment By
Software
Master/Slave Operation
Panel Type
Passive
x
x
x
x
x
x
slave slave
only
only
SED
1540
2560
bits
SED
1560
SED
1561
SED
1562
10790
bits
10790
bits
10790
bits
1630
/31
2x,
3x
1630
/31
2x,
3x
1630
/31
2x,
3x
x
x
x
x
x
x
x
x
x
x
100
100
100
TOB
TOB
TOB
TQA
TQA
TQA
x
x
x
x
x
x
x
x
x
x
x
x
DOC
DOA
DAA
DOA
DAA
DOA
#
DOA
DAA
D*A
D*A
D*A
D*A
D*A
D*A
DOA
DOB
DAB
DOB
DAB
DOB
DAB
D*B
D*B
D*B
D*B
D*B
D*B
DOB
199
199
199
130
130
130
118
118
118
199
FOC
FOC
FAC
FOC
FAC
FOA
FAA
FOA
FAA
FOC
FAC
FOA
FAA
FOA
FOA
FOA
MIM
TFT
Package
Die
AI
Au
g:
QFP
COG
Pad Pitch
(ftm)
Thin
Thick
# of Pins
TAB
FOA
FOA
FOA
FOA
FOA
FOE
(QFP
6-60)
80
80
80
80
80
48
2sided
100
100
100
128
128
128
TOA
TAA
TOA
TAA
TOA
TAA
TOA
TOA
TOA
FOA
100
TOA
TOA
TOA
TBA
4sided
Lead
Pitch (ftm)
Page Number
280
307
307
307
307
307
315
329
329
341
343
353
353
353
369
369
369
389
395
395
-
395
•
HIGH-DUTY LCD SEGMENT DRIVERS
SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED
1180 1181 1181 1570 1600 1601 1606 1620 1640 1648 1681 1722 1724 1742 1744 1748 1752 1756 1758 1765 1766 1770 1771
xLA FON
5A
Yes Yes Yes No Yes Yes No Yes No
No
No
No Yes
No
No
No
No
No
No
No
No
No
No
No SED SED SED No
No
- SED 168x 168x
1606
168x
64
64
80
80
80 128
64
80
80
80
80
80
80 160 160 160 240 240 160 160 160 160 162
Part Number
Discontinued?
Replacement
Resolution of segments
Duty Cycle
1/64
to
1/128
-14 -3 to -14 8 to
to
-12
20
to
-25
-25
LCD Voltage (V)
Supply Voltage
!5V
x
13v
Display Data Bus
(Bits)
static 1/64 1/64 1/100 1/100 11100 1/64 1/100 1/100
to
to
to
to
to
to
to
to
to
1/32 1/128 1/200 1/300 1/300 1/300 1/200 1/300 1/300
1
2
x
x
x
x
x
-12
to
-28
x
x
x
1/8
to
1/32
1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100
to
to
to
to
to
to
to
to
to
to
to
to
1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500
-12 -8 to -12 -8 to -8 to -3 to 14 to 14 to 14 to 14 to 8 to
to
-28
-28 -28 -12
40
to
40
40
40
42
-28
-28
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 to 14 to 14 to 14 to 14 to 5 to
42
42
42
40
40
17
x
x
x
x
x
x
x
x
~
<'
Xscl,max (Mhz)
Companion Chips
Panel Type
(continued)
x
6
1190 1210/
78
Passive
MIM
TFT
x
x
x
0.6
x
6
1191
x
x
x
6.5
x
x
x
x
_.
x
x
x
x
x
x
x
x
18
12
x
12
10
10
1755
1743
1703
1703
1743
1743
x
x
x
x
X
X
7.5
1
12
12
12
12
x
16
x
18
x
7.5
1635 1610/ 1610/ 1630/ 1631/ 1635
30/31 30/31
32
35
1651
1278
1733
1733
1743
1743
1743
1743
x
x
x
x
x
x
x
x
6.6
6.5
x
x
x
10
x
4
x
x
x
x
--
x
x
3
(R,G,B)
4
8
5 to
17
-
'---
-
'------
-
--
,-
L ____ L -____
--
L-_
-
•
HIGH-DUTY LCD SEGMENT DRIVERS (continued)
Part Number
SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED
1180 1181 1181 1570 1600 1601 1606 1620 1640 1648 1681 1722 1724 1742 1744 1748 1752 1756 1758 1765 1766 1770 1771
xLA FOAl
5A
Package
Die
AI
Au
DOA DLA DOA DOA DAA DAA DOA
DOB DAB
DOB
COG
Pad Pitch
190
190 170
153
180
153
DOA DOA DOA DOA
DOB
DOA
125 105
DOA DOA DOA DOA
DOB DOB DOB
D1B D1B DOB
DOA
178
160
160
160 108
108
134
82
134
120
120
673
673
(1lITl)
QFP Thin
FOA
FOA
Thick
F5A FLA F5A
# of Pins
80 80 80
TAB 2 side
Lead Pitch
(11m)
Slim
Page number
s
425
443
435 453
FAA FAA
100 100
FOA FOA FOA
100 100 100
TOA TOA TOA
180 180
TOA#
469
479
489
503 513
TOA
TOA
525
539
551
551
563
563
583
599
TOA
TOB
(flex)
615 627 645
657
Notes:
1. Some packages of certain parts labeld with # are still under development.
-
•
HIGH-DUTY LCD COMMON DRIVERS
Part Number
SED
1190
SED
1191
SED
1610
SED
1630
SED
1631
SED
1632
SED
1633
Discontinued?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Replacement
No
No
No
SED
167x
SED
167x
SED
167x
SED
167x
SED
1634
SED
1635
SED
1651
SED
1733
SED
1741
SED
1743
SED
1753
SED
1755
Yes
Yes
No
No
No
No
No
No
SED
167x
SED
167x
-
-
-
-
-
-
64
64
86
68
100
86
100
100
100
100
100
100
160
120
240
Duty Cycle
1/64
to
1/128
1/64
to
1/128
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/100
to
1/400
1/100
to
1/500
1/100
to
1/500
1/100
to
1/500
11100
to
1/500
LCD Voltage (V)
-14 to -14 to -12 to -12 to -12 to -12 to -12 to -12 to
-28
-28
-28
-25
-25
-28
-28
-28
-8 to
-28
-8 to
-28
14 to
40
14 to
42
14 to
40
8 to
42
8 to
42
x
Resolution of commons
Supply Voltage
5V
x
x
x
x
Data Bus (bits)
1
x
x
x
3V
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2.5
2.5
2.0
2.0
2.0
2.0
2.0
(5V),
1.0
(3V)
2.0
(5V),
1.0
(3V)
2.0
(5V),
1.0
(3V)
2.0
(5V),
1.0
(3V)
2.5
2.5
(5V),
1.25
(3V)
2.5
(5V),
1.25
(3V)
1180/
81
1181
1600/
01
1600/
01
1600/
01/20
1600
1600
1600
1570,
1600
1648
17221
24
17421
44
17421
44
17521
58
1756
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
~.
Clock Frequency, max
(MHz)
Companion Chips
Panel Type
Passive
MIM
TFT
(continued)
-
-_._--_
.. -
- - - - - - - - L ....
___
- _ ...
-
- - - - -
'---...
-
------
-
-
--
-
•
HIGH-DUTY LCD COMMON DRIVERS (continued)
Part Number
Package
Die
AI
Au
COG
Pad Pitch
SED
1190
DOA
SED
1191
DOB
SED
1610
SED
1630
DOA
SED
1631
DOA
DOB
SED
1632
DOA
149
240
SED
1633
D1A
D1B
SED
1634
D1A
D1B
SED
1635
D1A
D1B
SED
1651
DOA
149
149
149
153
SED
1733
DOA
SED
1741
SED
1743
SED
1753
D1B
D1B
DOB
108
108
TOA
TOA
180
TOA
805
819
835
SED
1755
DOA
190
170
(~m)
TAB 2 Sided
Lead
Pitch (~m)
QFP Thin
FOA,
FOB
Thick
F5A,
F5B2
# of Pins
80
Page number
705
~:
FOB
F5B
FAA
FOA
80
713
100
721
80
727
FOA
733
741
Notes:
1. Some packages of certain parts labeled with # are still under development.
747
759
771
783
128
795
849
•
DC/DC CONVERTERS
Part Number
Part Name
SCI7661
SCI7654
DCfDC Converter with voltage
DCfDC Converter with voltage
regulator and temperature
compensation
regulator and temperature
compensation
No
Discontinued?
No
No
Replacement
-
-
-
Maximum output voltage
-20V
-20V
-22V
Maximum output current
30 mA
20 mA
80fN mA
Voltage doubler
yes
yes
yes
Voltage tripler
no
yes
yes
Voltage quadrupler
no
no
yes
-1.2 to -8.0V
-1.2 to -6.0V
-2.0 to -11.0V
Input Voltage
Number of Output Voltage Levels
Conversion Efficiency
Package
~:
SCI7660
CMOS DCfDC Converter
Page number
2
4
4
95%
95%
95%
DIP-8pin(COA)
SOP4-8pin(MOA)
DIP-14pin(COA)
SOP5-14pin(MOA)
SSOP2-16pin(MAA)
SSOP2-16pin (MOA)
AI pad Die (DOA)
867
873
879
CUSTOMER SUPPORT
CUSTOMER TECHNICAL SUPPORT
S-MOS Systems provides Technical Support Services to their customers for all the graphics products. Please
follow the technical support guidelines as listed below for the different graphics product families - VGA LCD
Controllers, LCD Controllers, LCD Driver/Controllers, and LCD Drivers.
On-Line
This databook and new products can be accessed at www.smos.com website.
Technical Manuals
S-MOS provides detailed Technical Manuals on all the graphics products. Customers should contact their
local sales representative or the nearest S-MOS sales office for copies.
Evaluation Boards
Customers may borrow evaluation boards forthe SPC81 xx VGA LCD Controller family and the SED13xx LCD
Controller family by contacting their local sales representative or the nearest S-MOS sales office for a unit.
Technical Support
There are a number of ways to contact Graphics Technical Support personnel at S-MOS. For customers in
the Northeast and North Central United States, please contact the S-MOS Boston office for technical support
on all products. For other regions, please contact S-MOS San Jose.
Sales Inquiries
For pricing, delivery, or any other non-technical inquiry, please contact your local sales representative or SMOS sales office.
West Coast
North East and North Central
South East and South Central
S-MOS Systems, Inc.
S-MOS Systems, Inc.
S-MOS Systems, Inc.
2460 North First Street
301 Edgewater Place Suite 120
4300 Six Forks Road
San Jose, CA 95131
Tel. (617) 246-3600
Suite 430
Tel. (408) 922-0200
Fax (617) 246-5443
Fax (408) 922-0238
Raleigh, NC 27609
Tel. (919) 781-7667
(800) 537-2786
Fax (919) 781-6778
xxix
I
THIS PAGE INTENTIONALLY BLANK
xxx
1996
DATABOOK
GRAPHICS
PRODUCTS
II. VGA GRAPHICS
CONTROLLERS
THIS PAGE INTENTIONALLY BLANK
2
•
VGA.GRAPHICS CONTROLLERS FEATURES MATRIX
SPC8104 FOA
SPC8106FOC
SPC8107FOE
SPC8108FOC
SPC8110F OA
Low Voltage LCD
VGA Controller
Mixed Voltage
Color LCD VGA
Controller
Low Voltage
VGA LCD
Controller
Low Power LCD
VGA Controller
Local Bus
LCD/CRTVGA
Controller
Discontinued?
No
No
No
No
No
Replacement
-
-
-
-
-
CRT Support
No
w/ external
RAMDAC
w/ external
RAMDAC
Yes
8-bit single/dual
x
x
16-bit single/dual
x
x
x
x
x
Part Number
Part Name
Color LCD Support
9-bit TFT
No
x
12-bit TFT
x
18-bit TFT
x
12-bit RGB
Monochrome LCD Support
Co)
CPU Bus Interface
x
4-bit single panel
x
x
x
x
x
8-bit single/dual
panel
x
x
x
x
x
ISA-8bit
x
x
x
ISA-16bit
x
x
x
VL-32bit
x
PC12.0
x
486DX Local bus
Display Resolution
On-chip Color Lookup Table
Maximum Color
x
320x200 to
640x480
320x200 to
640x480
320x200 to
640x480
320x200 to
640x480
320x200 to
1024x768
64x4
256x12
64x4
256x6
256x18
256
256
CRT
256
color LCD
Maximum Grade Shades
256
256
16
64
16
64
64
(30,59,11)
Programmable Grayscale
base
Weightings
NTSC
(30,59,11)
(30,59,11)
(30,59,11)
(30,59,11)
text
(0,100,0)
(0,100,0)
(0,100,0)
(0,100,0)
(0,100,0)
one 256kx16
DRAM
one 256kx16
DRAM
one 256kx16
DRAM
one 256kx16
DRAM
two 256Kx16
DRAM
Frame Buffer Support
(continued)
(25,50,25)
-
I
!
•
VGA GRAPHICS CONTROLLERS FEATURES MATRIX (continued)
SPC8104 FOA
SPC8106FOC
SPC8107FOE
SPC8108FOC
SPC8110F OA
16
16
16
16
32
Self Refresh DRAM Support
x
x
x
x
x
Selectable CASIWE DRAM Configuration
x
x
x
x
x
Asymmetrical/Symmetrical
x
x
x
x
Part Number
Frame Buffer Data Bus Width (bits)
DRAM Support
w/ single panel
LCD
Simultaneous Display
Power Save Modes
I HIW Activated (# of pins)
I SIW Activated
I/O Interface Voltage
Core Voltage
1
1
1
1
2
5
5
5
5
2
5V
x
3.3V
x
5V
3.3V
x
x
x
x
2.5 or 3.3
x
64x64x2
x
x
Sprite/Hardware Cursor (bits)
.j>.
x
Yes
Hardware Vertical Centering
x
x
Hardware Vertical Expansion
x
x
x
x
x
x
64x64x2
64x64x2
x
x
x
x
x
Bit Block Transfer Engine (BitBLT)
x
Linear Addressing
x
Color Expansion
x
4-stage
4-stage
4-stage
4-stage
32-bit
MClk,max
28.322 MHz
28.322 MHz
28.322 MHz
28.322 MHz
40MHz
PClk,max
28.322 MHz
28.322 MHz
28.322 MHz
28.322 MHz
65MHz
Package
144-pin QFP
144-pin QFP
100-pin QFP
144-pin QFP
208-pin QFP
5
21
53
69
87
Display Pipeline
Integrated PLL
Page Number
2
SPC8104FoA
VGA LCD CONTROLLER
•
DESCRIPTION
The SPC81 04 is a low power, mixed 2.5/3.3 volt graphics controller based on VGA architecture and optimized
for driving a 640x480 LCD panel display. VGA standard mode functionality (with the exception of mode 13h)
is supported using standard IBM VGA parameters. A proprietary 64x4-bit gray scale lookup table is provided
to allow re-mapping of the 16 possible gray shades displayed on an LCD panel.
The target markets for this device are small, cost sensitive mixed 2.5V/3.3V hand-held organizers, or other
specialized consumer products where low cost, low power consumption, low component count, and the ability
to run most VGA software on a 640x480 LCD panel display are the major design considerations. This chip
is intended to operate mainly in planar graphics modes.
•
FEATURES
Low power CMOS with 2.5V/3.3V core and
3.3V I/O
•
•
8/16-bit ISA CPU data bus interface
•
Interfaces to a single 256 Kx16 DRAM
•
Vertical interrupt function on IRQ pin
supported
•
Optimized for 640x480 single and dual panel
monochrome LCD displays
Selectable 256 cycle/4 msec or 256 cycle/32
msec DRAM refresh rate, or low power selfrefresh mode
•
Flexible support of LCD panels of various
sizes
•
Supports 0-255 vertical non-display periods
•
Three hardware or software initiated powersave modes
•
Supports 640x480 4-bit monochrome MIM
panels
•
Supports all standard VGA modes except
mode 13h.
•
•
Proprietary internal 64x4 gray scale lookup
table
Power consumption of 60 mW in active mode
and 0.6 mW in "Power Save" mode when
operating at 24 MHz
•
FOA - 128 pin QFP15 package
•
Programmable hardware mapping of VGA
palette-style writes to 16 level LCD gray scale
values
SYSTEM BLOCK DIAGRAM
I
ISABUS
CLOCK
~
I
SPC8104
l
t
DRAM
I
5
MONOCHROME
LCD PANEL
I
SPC8104
•
INTERFACE OPTIONS
28 MHz
50"" Duty xtaVclock
~
16 Bit
ISA BUS
-REFRESH
AEN
-lOR
-lOW
-SMEMR
-SMEMW
IOCHRDY
IRQ2
RESETDRV
, SA[16:0J
LA[23:17J
SD[15:0J
-MEMCSI6
-IOCSI6
BALE
-SBHE
SUSPEND
DOZE
32 kHz
50% duty
52
MEMEN
IOEN
lOR
lOW
MEMR
MEMW
READY
IRQ
RESET
--'
t.l
YD
LP
WF
XSCL
LCD/MIM PANEL
DISPLAY
YD
LP
WF
XSCL
SPC8104
A[16:0J,
LA[23:17J
D[15:0J
UD[3:0J
LD[3:0J
LCDPWR
MEMCS16
IOCSI6ALE
BHE
9:~
~SP-END
I'T)
i~l~ggl~
DOZE
PDCLK
~
I~
OOI"rrIW
,... «<==
~~
0' a:uu
..J:::l
256K X 16 DRAM
Note: Examp[e implementation, actual may vary.
6
UD[3:0J
LD[3:0]
LCDPWR
SPC8104
•
SUPPORTED RESOLUTIONS
Mode
No.
Mode
Type
0
3+
T
T
T
T
T
T
T
T
T
T
T
3++
4
5
G
6
7
G
0+
0++
1
1+
1++
2
2+
2++
3
OE
OF
10
11
12
•
Characters
Resolution
Displayed
Pixels
Gray
Shades
Memory
Segment
8X8
40 X25
320 X200
640 X 400
16
8800
8 X 14
40X25
320 X 350
640 X 350
16
8800
8 X 16
40 X25
320 X400
640 X 400
16
8800
8X8
40X25
320 X200
640 X 400
16
8800
8 X 14
40X25
320 X 350
640 X350
16
8800
8 X 16
40X25
320 X 400
640 X 400
16
8800
8X8
80 X 25
640 X 200
640 X 400
16
8800
8 X 14
80 X 25
640 X 350
640 X 350
16
8800
8 X 16
80 X25
640 X400
640 X 400
16
8800
8X8
80X25
640X200
640 X 400
16
8800
8 X 14
80X25
640 X 350
640 X350
16
8800
T
8 X 16
80X25
640 X 400
640 X 400
16
8800
G
N/A
N/A
N/A
NA
320 X 200
640 X 400
4
8800
N/A
N/A
320 X 200
640 X 400
4
8800
640 X200
640 X400
2
8800
8 X 14
80X25
640 X 350
640 X 350
2
8800
8 X 16
80X25
640 X 400
640 X 400
2
8800
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
320 X 200
640 X 400
16
AOOO
640 X 200
640 X 400
16
AOOO
640 X 350
640 X 350
2
AOOO
640 X350
640 X 350
16
AOOO
640 X 480
640 X 480
2
AOOO
640 X 480
640 X 480
16
AOOO
T
T
G
G
G
G
G
G
7+
OD
Font
SUPPORTED LCD INTERFACES
8-8it Interface
4-Bit Interface
Dual Panel
Single Panel
Single panel
Horizontal
Vertical
Horizontal
Vertical
Horizontal
Vertical
1
241
to
480
1
to
640
1
to
480
1
to
640
1
to
480
to
640
7
I
en
"U
(')
CD
....
• •g
ID
r-
o
(')
~
C
~
~
==
A(23:0]
16-Bit Bus
Control
D[15:0]
-r-
[-
J
J
Bus
Interface
l
-
ClKO
ClKI
SUSPEND
DOZE
PDClK
Memory
Decoder
Clock
Generator/Divider
J
~
~
~
VGA
Ports
~
Sequencer
Jf
Power
Save
--'-.-1.
MA[9:0]
DRAM
Control
~
J
J
1
I
Display
Memory
Address
Generator
MD[15:0]
~
Auxiliary
Ports
~
-f--
~
(XI
Port
Decoder
L
j+-
Map 0
Display
Memory
Interface
Map 3
...
t~
t---
1
t
~
CRT
Controller
.llC--
fr
Attributes
Controller
Graphics
Controller
J
H
look-Up
Table
lCDlMlM
Panel
Interface
r---
UD[3:0]
lD[3:0]
XSCl
lP
YD
WF
lCDPWR
SPC8104
•
•
DC SPECIFICATIONS
Absolute Maximum Ratings
Parameters
Codes
Rating
Units
Vss-0.3 to +7.0
V
Input voltage
VDD
V,N
Vss-0.3 to VDD +0.3
V
Output voltage
VOUT
Vss-0.3 to VDD +0.3
V
Operating temperature
TOPR
o to +70
°C
Storage temperature
TSTG
-65 - +150
°C
Soldering temperature/time
TSOL
-260 for 10 sec max at lead
°C
Supply voltage
•
Recommended Operating Conditions
Parameter
Symbol
Condition
Supply voltage
HVDD
Supply voltage
LVDD
V,N
Input voltage
Operating temperature
•
I
Range
Unit
Min
Typ
Max
Vss = OV
3.0
3.3
3.6
V
Vss = OV
2.25
2.5
3.6
V
Vss
Vss
-
VDD
V
25
70
°C
TOPR
0
Average power consumption
10PR
20
mA
Doze mode 1
IPD1
10
mA
Doze mode 2
IPD2
5
mA
Suspend
IPsus
0.2
mA
5
Input Specifications
Symbol
Condition
Low level input voltage
Parameter
V,L
VDD =MIN
High level input voltage
V,H
VDD = MAX
Positive-going threshold
(CMOS Schmitt inputs)
VT+
VDD = 3.3V
Negative-going threshold
(CMOS Schmitt inputs)
VT.
VDD = 3.3V
0.6
V
Hysteresis voltage
(CMOS Schmitt inputs)
VH
VDD = 3.3V
0.1
V
Input leakage current
liz
VDD = MAX
V,H = VDD
V,L = Vss
-1
Input pin capacitance
C'N
Rpu
8
pF
Pull up resistance
VDD = 3.3V
90
KO
Pull down resistance
RpD
VDD = 3.3V
90
Kg
9
Min
Typ
Max
Unit
0.8
V
2.0
V
2.4
1
V
JlA
SPC8104
•
Output Specifications
Parameter
Symbol
Condition
Min
1011
VOL =Vss +O.4V
TSI, TSIU, C01
3.0
mA
High level output current
IOH1
VOH = VDD -O.4V
TSI, TSIU, C01
-3.0
mA
Low level output current
IOL2
VOL = Vss +O.4V
TS2, CO2
6.0
High level output current
IOHI2
VOH = VDD -O.4V
TS2, CO2
-6.0
Output leakage current
loz
VOH = VDD
or VOL = Vss
-1
Output pin capacitance
COUT
Low level output current
Typ
2.4
Unit
mA
mA
1
8
10
Max
llA
pF
SPC8104
•
SPC8104 PIN OUTS
8~
~
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
IZ~ I'Q" I:;:Q :;;Z
w I':;;" I:;:
:;;
w w
-
Voo CORE
~ :;; :;;
~~U)U)
I~ I~
0~
~
-
~
azl
w
10 :i0 Z " a g;"~
>
0~~g;~~m 0
~g~g~~
~0g,
~
0..
BHE
0
...I
0
0
0
o
N
M
M N
o ~ 0 - 0 ~ 0 ~ 0 0~
:2:~~~:!:~::E~~g
~
~
~
~
>
Vssvo
MD11
ALE
MD5
AO
MD10
A1
MD6
A2
MD9
A3
MD7
A4
MD8
A5
LCAS
A6
VODCORE
VSSI/O
Vss CORE
VDDI/O
WE
A7
UCAS
A8
RAS
SPC8104
A9
MA9
A10
MAB
A11
MAO
A12
MA7
A13
MA1
A14
MA6
Vss CORE
VDDVO
Voo CORE
VSSI/O
A15
MA2
A16
MA5
LA17
MA3
LA1B
MA4
LA19
TSTCO
LA20
UD3
LA21
UD2
LA22
UD1
LA23
VSSI/O
0
UDO
VDD CORE
"
11
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
4B
47
46
45
44
43
42
41
40
39
3B
37
36
35
34
33
I
SPC8104
•
PIN DESCRIPTION
Key
Analog
Input
Output
Bi-directional
Power
A
I
o
I/O
P
CPU Interface
Pin Name
A[0:16],
LA[17:23]
0[0:15]
Type
Pin#
I
100-106,
109-116
119-127
I/O
Description
CPU bus unlatched address inputs. For an 8-bit CPU interface configuration,
LA[20:23] are ignored and LA[17: 19] should be connected to the latched CPU
address SA[17:19].ln Suspend Mode, the address inputs are internally masked
off.
2-10, 13-19 16 bit ISA-Bus data bus. These lines are driven by the chip only during read
cycles, and are in a hi-Z state at all other times. In Suspend Mode, these inputs
are internally masked off.
ALE
I
99
ISA Bus Address Latch Enable. ALE is ignored for an 8-bit CPU interface configuration. In Suspend Mode this input is disabled.
MEMEN
I
92
ISA Bus Memory Enable. This signal should be connected to the -REFRESH
signal on the ISA bus. When this signal is low (e.g. during a system memory
refresh cycle), memory address decoding is disabled.
10R#
I
94
ISA Bus I/O Read Strobe. In Suspend Mode this input is disabled.
10W#
I
93
ISA Bus I/O Write Strobe. In Suspend Mode this input is disabled.
MEMR#
I
91
ISA Bus Memory Read Strobe. In Suspend Mode this input is disabled.
MEMW#
I
90
ISA Bus Memory Write Strobe. In Suspend Mode this input is disabled.
10EN#
I
95
ISA Bus I/O Enable. This input should be connected to the ISA bus AEN signal. When this signal is high, I/O address decoding is dis-abled. In Suspend
Mode this input is disabled.
READY
0
89
ISA Bus READY signal. This output is driven low to force the CPU to insert wait
states during memory cycles. READY is released to high-Z after a transfer is
complete.
RESET
I
84
The active high Reset signal from the CPU clears all internal registers and
forces all signals to their inactive state. During Suspend Mode the RESET input
is ignored.
IRQ
0
83
ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will
cause this signal to be driven from a logic 0 state to a logic 1 (rising-edge
triggered interrupt). Once set, this interrupt must be cleared by a bit in the CRTC
registers. A control bit in the Auxiliary Registers allows this output to be
optionally disabled (tri-stated).
MEMCS16#
0
87
ISA Bus Memory Chip Select 16. Address inputs LA[23: 17] are decoded to drive
this output low when a valid memory address (AXXXXh, BXXXXh) appears on
the bus.
IOCS16#
0
88
ISA Bus Memory Chip Select 16. Address inputs LA[23: 17] are decoded to drive
this output low when a valid SPC 81 041/0 register address appears on the bus.
Note that I/O addresses 3C6h-3C9h does not result in IOCS16# being driven
low (i.e. internal LUT register reads and writes are 8 bit cycles).
I
98
ISA Bus Byte High Enable. In Suspend Mode the this input is disabled.
0
20
Read Acknowledge. This pin goes low during valid I/O or memory reads to the
chip.
BHE#
RDACK#
12
SPC8104
Frame Buffer Memory Interface
Pin Name
Type
Description
Pin#
MA[0:9]
0
MD[0:4]
MD[7:15]
1/0
MD[5:6]
1/0
62,60
RAS#
0
0
51
DRAM Row Address Strobe.
56
DRAM Column Address Strobe for low byte (lCAS#), or Write Enable Strobe
for low byte (lWE#), as determined by logic value on MD[6] during RESET
(see pin mapping table).
UCAS#
(CAS#)
0
52
DRAM Column Address Strobe for high byte (UCAS#), or single Column
Address Strobe (CAS#), as determined by logic value on MD[6] during RESET
(see pin mapping table).
WE#
(UWE#)
0
53
DRAM Write Enable Strobe (WE#), or Write Enable Strobe for high byte
(UWE#), as determined by logic value on MD[6] during RESET (see pin
mapping table).
lCAS#
(lWE#)
48,46,42,
40,39,41,
45,47,49,
50
74,72,70,
68,66,58,
57,59,61,
63,67,69,
71,73
Multiplexed rowlcolumn address bits for video display memory.
Data bits for video display memory. The output drivers of these are placed
into a high-impedance state when RESET is high. On the falling edge
of RESET, the values on MD[3:0] are latched into a read-only Auxiliary
Register and are available to be read as configuration inputs. Also, the values
on MD[5:6] are used to configure other various hardware options - see
"Summary of Configuration Options", for details. Note that there are internal
pullup resistors on the inputs of these pins except MD[5:6].
Clock Inputs
Pin Name
ClKI
Type
I
Pin#
Description
This is the clock source input and should be connected to
an external oscillator.
77
Power Supply
Pin Name
Type
VooCORE
P
Pin#
Description
12,33,55,97,118
Voo supply for core logic.
Voo 1/0
P
1,22,44,65,86,108
Voo supply for 1/0 pins.
VooClKI
P
76
Voo supply for ClKI pin.
Vss CORE
P
11,32,54,96,117
Vss supply for core logic.
Vss 1/0
P
21,43,64,85,107,128
Vss supply for 1/0 pins.
VssClKI
P
75
Voo supply for ClKI pin.
Test Function
Pin Name
Type
Pin #
Description
Drv
TSTCO
I
38
CD
This pin enables the chip's test mode for the core logic. This pin must
always be unconnected or tied to ground.
TSTEN
I
82
CD
This pin enables the chip's test mode for the 1/0 cells. This pin must
always be unconnected or tied to ground.
13
I
SPC8104
LCD Panel Interface
Type
Pin#
YD
Pin Name
0
25
Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the
LCD/MIM panel module on the falling edge of LP, is used by the panel row
drivers (Y drivers) to indicate the start of the vertical frame.
LP
0
26
Latch Pulse output. The falling edge ofthis signal is used to latch a row of display
data in the LCD/MIM panel module's column driver shift registers and to turn on
the row driver (Y driver) for that line.
XSCL
0
23
Shift Clock for LCD panel data or Pixel Clock for MIM panel data. Display data
is clocked out of the chip on the rising edge of this signal, to be shifted into the
LCD/MIM panel module column drivers (X drivers) on each falling edge).
UD[0:3]
0
34-37
Upper panel display data for dual LCD panel mode. For single LCD panel mode,
these bits are the most significant 4 bits of the 8 bit output data to the panel
(PD[4:7]). For 4-bit single LCD panel mode, these bits are the 4 bits of output
data to the panel. For 4-bit MIM panel mode, these bits are driven O.
LD[O:3]
0
28-31
Lower panel display data for dual LCD panel mode. For 8-bit single LCD panel
mode, these bits are the least significant 4 bits of the 8 bit output data to the
panel (PD[0:3]). For 4-bit single LCD panels, these bits are driven O. For 4-bit
MIM panel mode, these are the 4 bits of output data to the panel.
LCDPWR#
0
27
LCD power control. In normal operation this signal is driven low to enable an
external LCD power supply. This signal is driven high when the chip is put into
any power save mode, or if the Sequencer is in a reset state. It can be used
externally to turn off the panel supply voltage and backlight. After a RESET,
this signal is held high until the CRTC is programmed and running.
WF
0
24
LCD Panel Backplane Bias Signal or MIM Panel Data Enable Signal. In LCD
panel mode, the WF signal toggles once per vertical frame period. In MIM panel
mode, this signal goes high whenever display data are valid.
Description
Power Save Mode Control
Type
Pin#
PDCLK
Pin Name
I
79
Power Down Clock. This input may be used to provide a low frequency clock
for generating DRAM refresh in Suspend mode, as an optional alternative to
using the pixel clock or MEMEN input as the DRAM refresh clock source. This
clock input should be driven by a 32 kHz 50% duty cycle clock. The PDCLK
input is used to directly generate the RAS and CAS pulses in Suspend mode.
SUSPEND#
I
80
A low level on this pin puts the chip into the hardware Suspend mode. The
SUSPEND# signal overrides any sofrware initiated power save modes as well
as the DOZE# input pin, and disables the CPU bus interface inputs. CPU
Address and Data inputs are masked when this signal is low. When in Suspend
Mode the UD[3:0], LD[3:0], XSCL, LP, YO and WF Signals are driven into a low
state ( or optionally, a high impendance state) and the LCDPWR# signal is
driven high.
DOZE#
I
81
A low level on this pin puts the chip in Doze mode. The function of the Doze
mode is determined by the Doze Mode Select bits in AUX[03]. This pin is ignored if the SUSPEND# input pin is asserted.
Description
14
SPC8104
Configuration Options
Pin Name
MD[3:0]
Value on this pin at falling edge of RESET is used to configure: (1/0)
Values latched into read-only AUX rOC] bits 7-4 for software use
MD[5]
LCD signals' state in Suspend mode: Low (1), or Hi-Z (0)
MD[6]
2 CAS, 1 WE type DRAM (1), or 1 CAS, 2 WE type DRAM (0)
Multiple Function Pin Descriptions
Pin Name
LCAS#, LWE#
UCAS#, CAS#
WE#, UWE#
Function
MD Line Status
LCAS#
MD [6] = 1
DRAM column address strobe (low byte)
LWE#
MD [6] = 0
DRAM write enable strobe
UCAS#
MD [6] = 1
DRAM column address strobe (high byte)
CAS#
MD [6] =0
DRAM column address strobe
WE#
MD [6] = 1
DRAM write strobe
UWE#
MD [6] =0
DRAM write strobe (high byte)
Mixed Voltage Configurations
Core VDD
Functional Description
1/0 VDD
2.5 V
3.3V
2.5 V
No
Yes
3.3V
No
Yes
15
I
SPC8104
Illustrated below are the display data output which are output from the UDO to UD3, LDO/UD4 to LD3/UD7
and the display on the panel:
Dual Panel - Top
8-bit Single Panel
LD31 LD21 LD11 LDOJ
Dual Panel - Bottom
4-bit Single Panel
•
LCD Panel Pixels
640 DOTS
r
1-1
2-1
1 1-2
1 2-2
!1-639!1-640
12-63912-640
1
1
24o LINES
~I
UPPER LCD PANEL
240 - 1 1 240 - 2 1
241 - 1 1 241 - 2 1
1240 - 6391 240 - 640
1241 - 6391241 - 640
(TOP VIEW)
24o LINES
i_
LOWER LCD PANEL
480-1 !480-2 !
1480 - 6391480 - 640
16
SPC8104
•
MIM Panel Interface
MIM Panel
DATA[3:0]
LP
-----------
d
LlNEl
~~
•• ~ •• - - - - - -
~~16=O~C:lk--__-_~-~~~80~O~C~lk~======~~========~
C - - _______
DATA[3:0]
_6_3_8_6_39_64_0
DATAEN
•
Monochrome Passive STN LCD Panel Interface
4-bit Single Panel
LP : 240 PULSES
I'"
LP : 0/2 PULSES
(SELECTABLE)'
~I'"
~I
LP
WF
LINE 1
UD[3:0]
LlNE2
( L
~: = = = =~_,~lr- I- - - - - :- - - - :- - - - - - I+-I
XSCL
XSCL: 80 CLOCK PERIODS
-------'---'----'----------~~~~·I
_____ ~ ________ ~ ___ _ . I L
UD3-------~--------~--~
UD2
---~--------~--~
UD1
---~--------~--~
UDO
---~--------~--~
, Diagram drawn with 2 LP vertical blank period
Example timing for 320 x 240 display
17
I
SPC8104
•
Monochrome Passive STN LCD Panel Interface
8-bit Single Panel
LP : 480 PULSES
YO
________~~L_ _ _ _ _ _ _ __ _
LP:0/2 PULSES
(SELECTABLE)"
"I"
·1
--------------~
LP
WF
UD[3:0], LD[3:0]
~:
XSCL
LINE 1
========d='
~..
LINE 2
"e" "
ecoe~K-= p-= E-= R-= IO-= -D s-= -= -= -= -= -= -= -= -= -= -= -= -= -= -= - l~"I
.~ ________ ~.~
UD3----···~-------·~··~
UD2
... ~-------.~ .. ~
UDt
... ~-------~ .. ~
UDO
... ~-------.~ .. ~
LD3
... ~-------.~ .. ~
LD2
... ~-------~ .. ~
LOt
... ~-------.~ .. ~
LOO
... ~-------~ .. -~
• Diagram drawn with 2 LP vertical blank periods
18
SPC8104
•
Monochrome Passive STN LCD Panel Interface
8-bit Dual Panel
LP:0/2 PULSES
LP : 240 PULSES
(SELECTABLE),
~----~~~===-------~·~I·~----~·I
YD
----------~~~-----------
------------------~
LP
WF
D[3:0], LD[3:0]
----------------~~
LP _ _ _----'
WF _ _ _ _-----'1'----_ _ _ _ _ _ __
XSCL: 160 CLOCK PERIODS
UD3----···~-------·~···~
UD2
... ~-------.~ ... ~
UD1
... ~-------.~ ... ~
UDO
.. ~-------.~ ... ~
LD3
... ~-------.~ ... ~
LD2
... ~-------.~ ... ~
LD1
... ~-------.~ ... ~
LDO
... ~-------.~ ... ~
• Diagram drawn with 2 LP vertical blank periods
19
I
SPC8104
•
PACKAGE DIMENSIONS
QFP15-128 pin
Unitmm
16.0 ±O.4
14.0 ±O.l
96
65--1-+------.-
97
..,.
ci
+1
o
cO
....
128
ci
+1
ci
II)
+1
C\I
~
....
0
....
0.5 ±O.2
1.0
20
SPC8106Foc
VGALCDCONTROLLER
•
DESCRIPTION
The SPC8106FOC is a versatile mixed voltage VGA graphics controller capable of driving liquid crystal
displays, TFT displays and analog CRT monitors. The controller integrates all LCD interface, sequencing and
color modulation logic into one small form factor 144 pin package. With the addition of an industry standard
,477 compatible RAMDAC, the SPC81 06FOC will also drive a VGA fixed frequency or multifrequency monitor.
The target products for this device are price and power sensitive 80x86 microprocessor based portable
personal computer or other specialized LCD systems where 320 x 200 to 640 x 480 x 256 color LCD panel
displays are the major design criteria.
•
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-power CMOS technology
Hardware VGA compatible
8- or 16-bit ISA support
One 256K x 16 80ns DRAM (self refresh
optional)
64 x 64 x 2-bit pixel hardware cursor
Two-terminal crystal or extemal oscillator
support
Hardware or software power-down
Video BIOS, software driver and utility
support
144-pin QFP package
9- or 12-bit color TFT panel interface for 640
x 480
Single panel or dual panel interface for sizes
320 x 200 to 640 x 480
On-chip 256 x 12 look-up table
16 gray shades or 4096 colors by FRM
64 gray shades by FRM and dithering
Two programmable gray-scale weightings:
NTSC and Green-Only
Vertical centering and expansion for LCDs
Full CRT support with '477 compatible
RAMDAC
Pin Compatible with the SPC8108FOC
Mixed voltage 3.3V/5V operation
SYSTEM BLOCK DIAGRAM
I CLOCKS I
~
ISA
BUS
3.3Vor5V
MONOCHROME
LCD PANEL
3.3V or 5V
SPC8106
~I
l3.3V
or5V
I
DRAM
21
I
or5V
RAMDAC
~
ANALOG
CRT
I
SPC8106Foc
•
INTERFACE OPTIONS
25.175 MHz
28.322 MHz
", -1nfh,e 'I~~ ,~
16 Bit
ISA BUS
·REFRESH ~f--------+
AEN
·IOR
·IOW
·SMEMR
·SMEMW
IOCHRDY
IRQ2 . .
r-----------
RESET DRV
MEMEN
-
IOEN
lOR
lOW
MEMR
MEMW
READY
IRQ
2MQ!
"
...J
0
rl
V
2MQ
"'"
0
"
...J
...J
0
0
RESET
SA[16:0].
LA[23:17]
D[15:0]
.
__.-
·MEMCS16 ..
·IOCS16 .. j - - - BALE ~ j - - -......
·SBHE
..............
SUSPEND - 32KHz
50% duty
l' ~
~rl ~
t-1 ~
LCD DISPLAY
'"
(;l
YD
LP
0
WF
XSCL
UD[3:0]
LD[3:0]
LCDPWR
XSCL2
...J
IREFEN
A[16:0].
LA[23:17]
D[15:0]
SPC8106Foc
MEMCS16
IOCS16
ALE
BHE
_.-------
P[7:0]
PCLK
·DACRD
DACWR
OLIO]
II
OL[2]
OL23
RS2
D477
BLANK
f---J
SUSPEND
PDCLK
IREF
P[7:0]
CLOCK
IWR
IRD
OL[3:0]
RS2
477/471
BLANK
R. G. B
8t477
RAMDAC
~
CRT
MONITOR
~9
Ui"!:::.
0:0
~5"
~~
:CI)i(/)
C)
:::D
»
JJ
A[23:0·
16-BITBUS
CONTRO
3:
PORT
DECODER
I
L
-±
D[15:0·
~
I\)
(11
MEMORY
DECODER
CLK01
CLKI1
CLK02
CLKI2
CLOCK
GENERATOR
PDCLK
POWER
SAVE
1
J
L
r-
JF
ADDRESS
GENERATOR
MD[15:0]
MA[9:0]
DRAM
CONTROL
~
.1-
-±
VGA
PORTS
HARDWARE
CURSOR
.1-
r--
r---
SEQUENCER
r-~
r-
l
C
rMAP 0
DISPLAY
MEMORY
INTERFACE
-1
Ie=-
-
UD[3:0]
LD[3:0]
XSCL
XSCL2
LP
YO
,-
WF
LC-DPVVR
----,
ATTRIBUTE
CONTROLLER
1
LOOK-UP
TABLE
t
GRAPHICS
CONTROLLER
MAP 3
LCD
PANEL
INTERFACE
1
CRT
CONTROLLER
1
-1.1.
I
AUXILIARY
PORTS
CRT
INTERFACE
J
t-- r-
P[7:0]
PCLK
HSYNC
VSYNC
BLANK
DACRD
DACWR
0L23
DLO
OL1
D4n
RS2
U)
"tI
-
o
Q)
.....
o(7)
;r
SPC8106Foc
•
FUNCTIONAL BLOCK DESCRIPTION
Port Decoder
The Sequencer
The Port Decoder decodes CPU-bus I/O cycles
to provide enable and write strobes for the onchip I/O registers.
The Sequencer generates internal signals to
synchronize the operation of the chip as well as
the signals to control the timing of the display
DRAM. The Sequencer also arbitrates between
CPU and video display accesses to the DRAM. It
contains registers that allows selection of character font set, control the structure of the video
memory and allow write masking of the individual
plane of memory.
Auxiliary Ports
The Auxiliary Ports are I/O registers used to
control functions of the chip beyond the basic
VGA register set. Registers are included for controlling the LCD interface circuits as well as the
power save modes.
CRT Controller
VGA Ports
The CRT Controller generates the horizontal and
vertical synchronization signals forthe CRT, single
panel or dual panel LCD display and character
and/or pixel addresses for display data from
DRAM.
The VGA Ports contain the Miscellaneous Output
Status register and the Video Subsystem Enable
register used in VGA mode.
Clock Generation
CRT Interface
The Clock Generation contains oscillator support
for external crystals.
The CRT interface aligns CRT signals to the Pixel
Clock and generates the I/O Control signals for
CPU access to the RAMDAC.
Power Save
The Power Save block contains the logiC to
implement six software controlled and one hardware controlled power down modes.
Address Generator
The Address Generator takes the display and
refresh addresses from the CRT Controller and
converts them into RAS and CAS addresses for
the display DRAM, and multiplexes these display
accesses with CPU memory accesses.
Lookup Table
The Lookup Table consists of a memory array of
256 locations of 12 bits each and hardware to
convert VGA palette writes to gray-scale values.
Attributes Controller
LCD Interface
The Attributes Controller takes in pixel and attribute information from the Graphics Controller
and display DRAM and formats the data into pixel
information which then passes through the lookup
table. It also controls display character attributes
such as blink, underline and horizontal pixel
panning.
The LCD Interface block converts the display
video data from the Lookup Table into LCD
display data. It also generates control signals
necessary to drive single or dual-panel LCD
panels. For monochrome LCD panels, the LCD
interface block generates a maximum 64 gray
shades through frame rate modulation and dithering techniques. For color LCD panels, the LCD
interface block generates 256 simultaneous colors from a possible 4096 colors through frame
rate modulation.
Graphics Controller
The Graphics Controller supplies display memory
data to the Attributes Controller during display
time and provides data translation between the
CPU bus and the display memory during CPU
read or write access cycles.
Hardware Cursor
The Hardware Cursor block generates a 4 gray
shade or color cursor/sprite that can be overlaid
on the LCD or CRT display. The cursor is 64 x 64
pixels or optionally expanded to 128 x 128 through
pixel replication.
Display Memory Interface
The Display Memory Interface is a bridge by
which the chip communicates with the DRAM. It
contains buffers that are used to store recently
fetched DRAM data.
Memory Decoder
The Memory Decoder monitors the CPU-bus
activity and decodes cyclesforthe display DRAM.
It supplies memory access control Signals to the
Sequencer.
26
SPC8106Foc
•
•
DC SPECIFICATIONS
Absolute Maximum Ratings
Symbol
Rating
Units
Vss-0.3 to +7.0
Vss-Q.3 to VDD +0.3
V
Input voltage
VDD
V,N
Output voltage
VOUT
Vss-0.3 to VDD +0.3
V
Operating temperature
TOPR
Oto +70
Storage temperature
TSTG
Soldering temperature/time
TsoL
-65 - +150
-260 for 10 sec max at lead
°C
°C
°C
Parameters
Supply voltage
•
I
Recommended Operating Conditions
Parameter
Supply voltage
Supply voltage
Input voltage
Operating temperature
•
V
Symbol
Condition
HVDD
LVDD
V,N
Vss = OV
Vss = OV
Vss
Value
Typ
5.0
3.3
Min
4.5
3.0
Vss
0
TOPR
Max
5.5
3.6
VDD
70
25
Unit
V
V
V
DC
Input Specifications
Parameter
Low level input voltage
(CMOS inputs)
High level input voltage
(CMOS inputs)
Low level input voltage
(TTL inputs)
High level input voltage
(TTL inputs)
Positive-going threshold
(CMOS Schmitt inputs)
Negative-going threshold
(CMOS Schmitt inputs)
Hysteresis voltage
(CMOS Schmitt inputs)
Positive-going threshold
(CMOS Schmitt inputs)
Negative-going threshold
(CMOS Schmitt inputs)
Hysteresis voltage
(CMOS Schmitt inputs)
Min
Typ
Max
Unit
1.0
V
Symbol
Condition
V,L
VDD=MIN
V,H
VDD= MAX
VIL
VDD=MIN
V,H
VDD = MAX
VT+
VDD =5.0V
VT-
VDD= 5.0V
0.8
V
VH
VDD= 5.0V
0.3
V
VT+
VDD=5.0V
VT-
VDD=5.0V
0.6
V
VH
VDD = 5.0V
0.1
V
Input leakage current
ilz
VDD= MAX
V,H = VDD
V,L = Vss
-1
Input pin capacitance
Pull up resistance
Pull up resistance
Pull down resistance
C'N
Rpu2
Rpu3
RpD
VDD =5.0V
VDD =5.0V
VDD = 5.0V
50
100
100
27
V
3.5
0.8
2.0
V
V
4.0
3.0
8
100
200
200
V
V
1
~
200
400
400
Kg
Kg
Kg
pF
SPC8106Foc
•
Output Specifications
Parameter
Low level olltput current
Symbol
10L2
High level output current
IOH2
Low level output current
lOla
High level output current
IOH3
Low level output current
10L'
High level output current
10H.
Output leakage current
Output pin capacitance
Bidirectional pin capacitance
loz
COUT
CBID
Condition
VOL = Vss + 0.4V
TS2
VOH = VDD - O.4V
TS2
VOL = Vss + 0.4V
TS3
VOH = VDD - O.4V
TS3
VOL = Vss + O.4V
TS4
VOH = VDD - 0.4V
TS4
VOH = VDD or VOL = Vss
Min
Typ
Unit
rnA
-2.0
rnA
12.0
rnA
-4.0
rnA
24.0
rnA
-8.0
rnA
-1
1
8
10
28
Max
6.0
!lA
pF
pF
SPC8106Foc
•
SPC8106 PIN OUT
(/)"'~~OOWIWIX~O
~~~~
29
-~--------~
~O
SPC8106FoC
Cl
-
Cl
«~~~oooo~~~QQ~g~g~~~ggm~~~D~D~D~Dg
It)
<0 I'-
~~ en
0 0 (/)
~~~~~~~~~~~~~~
>
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
I
SPC8106Foc
•
PIN DESCRIPTION
Key
A
I
o
I/O
P
Analog
Input
Output
Bi-directional
Power
30
SPC8106Foc
CPU Interface
Pin Name
Description
Type
Pin#
A[0:16},
LA[17:23]
I
104.. 107,
110 .. 122,
2..4,5 .. 8
CPU bus address inputs. In Suspend Mode, the Address inputs are
internally masked off. If the value on MD[5] at RESET = 1, then the ALE
input pin is used to internally latch LA[19: 17] and A[16:2], allowing these
address bits to be driven by the processor address bus. If the value on
MD[5] at RESET = 0, then standard ISA address timing is assumed, where
pins A[0:16]. LA[17:23] should be connected to the ISA bus signals
SA[0:16]. LA[17:23] respectively.
ALE
I
102
ISA Bus Address Latch Enable. In Suspend Mode the ALE input is disabled.
If the value on MD[5] at RESET =1, then the ALE input is used to internally latch
LA[19: 17] and A[16:2]. allowing these address bits to be driven by the processor
address bus. In this mode, the processor ADS# output should be connected to
this pin. If the value on MD[5] at RESET =0, then standard ISA address timing
is assumed, and only the LA[19:17] inputs are internally latched.
0[0:15]
1/0
125 .. 140
16 bit ISA-Bus data bus. These lines are driven by the chip only during read
cycles, and are in a hi-Z state at all other times. In Suspend Mode, these inputs
are internally masked off.
MEMEN
I
97
ISA Bus Memory Enable. This signal should be connected to the REFRESH#
signal on the ISA bus. When this signal is low (e.g. during a system memory
refresh cycle), memory address decoding is disabled.
10R#
I
94
ISA Bus 1/0 Read Strobe. In Suspend Mode the 10R# input is disabled.
10W#
I
95
ISA Bus 1/0 Write Strobe. In Suspend Mode the 10W# input is disabled.
MEMR#
I
96
ISA Bus System Memory Read Strobe. In Suspend Mode the MEMR# input is
disabled.
MEMW#
I
98
ISA Bus System Memory Write Strobe. In Suspend Mode the MEMW# input
is disabled.
10EN#
I
93
ISA Bus 1/0 Enable. This input should be connected to the ISA bus AEN signal.
When this signal is high, 110 address decoding is disabled. In Suspend Mode
the 10EN# input is disabled.
READY
0
142
ISA Bus READY signal. This output is driven low to force the CPU to insert wait
states during memory cycles. READY is released to high-Z after a transfer is
complete.
RESET
I
141
The active high Reset signal from the CPU clears all internal registers and
forces all signals to their inactive state.
IRQ
0
103
ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will
cause this signal to be driven from a logic 0 state to a logic 1 (rising-edge
triggered interrupt). Once set, this interrupt must be cleared by a bit in the
CRTC registers. A control bit in the Auxiliary Registers allows this output
to be optionally disabled (tri-stated). This pin also is used for the output of
the NAND tree in pin test mode.
MEMCS16#
0
99
ISA Bus Memory Chip Select 16. Address inputs LA[23: 17] are decoded to
drive this output low when a valid memory address (AXXXXh, BXXXXH)
appears on the bus.
IOCS16#
0
100
ISA Bus 1/0 Chip Select 16. Address inputs A[15:0] and 10EN# are decoded
to drive this output low when a valid SPC81 06FOC 1/0 register address appears
on the bus. Note that 1/0 addresses 3C6h-3C9h do not result in IOCS16# being
driven low (Le. RAMDAC and internal LUT register reads and writes are 8 bit
cycles.
BHE#
I
101
ISA Bus Byte High Enable. In Suspend Mode the BHE# input is disabled.
31
I
SPC8106Foc
Video Memory Interface
Type
Pin#
MA[0:9]
Pin Name
0
57,55,
53,51,
48,52,
54,56,
58,20
MD[0:15]
I/O
81,79
77, 75
70, 68
66, 64
63, 65
67,69,74,
76,78,80
RAS#
0
59
DRAM Row Address Strobe for single 256Kx16 DRAM.
LCAS#
(LWE#)
0
62
Multiple Function:
DRAM Column Address Strobe for low byte (LCAS#). For alternate
function see "Multiple Function Pin Descriptions" on page 16.
UCAS#
(CAS#)
0
60
Multiple Function:
DRAM Column Address Strobe for high byte (UCAS#). For alternate
function see "Multiple Function Pin Descriptions" on page 16.
WE#
(UWE#)
0
61
Multiple Function:
DRAM Write Enable Strobe (WE#). For alternate function see
"Multiple Function Pin Descriptions" on page 16.
Description
Multiplexed row/column address bits for video display memory.
Data bits for video display memory. The output drivers of these pins are
placed into a high-impedance state when RESET is high, or when the
Sequencer is in a reset state. On the falling edge of RESET, the values
on MD[3:0] and MD[12:9] are latched into a read-only Auxiliary Register
and are available to be read as configuration inputs. Also, the value on
MD[8:4] and MD[15:13] are used to configure various hardware options.
See "Summary of Configuration Options" for details.
Clock Inputs
Type
Pin#
CLKI1
Pin Name
I
90
This pin, along with CLK01 is the 25.175 MHz 2-terminal crystal interface when
using a 2-terminal crystal as the clock input. If an external oscillator is used as
a clock source, then this pin is the clock input.
CLK01
0
91
This pin, along with CLKI1 is the 25.175 MHz2- terminal crystal interface when
using a 2-terminal crystal as the clock input. If an external oscillator is used as
a clock source, then this pin should be left unconnected.
CLKI2
I
86
This pin, along with CLK02 is the 28.322 MHz 2-terminal crystal interface when
using a 2-terminal crystal as the clock input. If an external oscillator is used as
a clock source, then this pin is the clock input.
CLK02
0
87
This pin, along with CLKI2 is the 28.322 MHz 2-terminal crystal interface when
using a 2-terminal crystal as the clock input. If an external oscillator is used as
a clock source, then this pin should be left unconnected.
Description
32
SPC8106Foc
LCD Panel Interface
Type
Pin#
YO
Pin Name
0
10
Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the
LCD module on the falling edge of LP, is used by the panel row drivers (Y
drivers) to indicate the start of the vertical frame.
Description
LP
0
13
Latch Pulse output. The falling edge of this signal is used to latch a row of display
data in the LCD module's column driver shift registers and to turn on the row
driver (Y driver) for that line.
XSCL
0
12
Shift Clock for LCD data. Display data is clocked out of the chip on the rising
edge of this signal, to be shifted into the LCD panel module column drivers (X
drivers) on each falling edge.
XSCL2
0
9
This second shift clock is used together with XSCL in 8-bit single color panel
mode to shift in alternate sets of display data. XSCL2 is also used alone as the
shift clock in 8-bit dual color panel mode and 4-bit single color panel mode.
UD[0:3]
0
22 .. 25
Upper panel display data for dual panel- dual drive mode. For 8-bit single panelsingle drive mode, these bits are the most significant 4-bits of the 8-bit output
data to the panel (data[7:4]). For 4-bit single panel mode, these bits are the 4
bits of data output to the panel. For 16-bit LCD modes, these outputs are the
multiplexed upper panel data if MD[7] = 1 at RESET, or the lower nibble of the
upper panel data if MD[7]=0 at RESET.
UD[4:7J
0
26 .. 29
When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD
mode upper panel data.
LD[0:3]
0
16.. 19
Lower panel display data for dual panel-dual drive mode. For 8-bit single panelsingle drive mode, these bits are the least significant 4 bits of the 8-bit output
data to the panel (data[3:0]). For 4-bit single panel mode, these outputs are
driven low. For 16-bit LCD modes, these outputs are the multiplexed lower
panel data if MD[7]=1 at RESET, or the lower nibble of the lower panel data if
MD[7]=0 at RESET.
LD[4:7]
0
30 .. 33
When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD
mode lower panel data.
LCDPWR#
0
21
LCD power control. In normal operation this signal is driven low to enable an
external LCD power supply. This Signal is driven high when the chip is put into
any power save mode, when Auxiliary Register 06 bit 0 is set to 1, or when the
Sequencer is in a reset state. It can be used externally to turn off the panel
supply voltage and backlight. After a RESET, this signal is held high until the
CRTC is programmed and running.
WF
0
15
LCD Backplane Bias signal. This output toggles once every n LP periods, as
programmed in Auxiliary Register [00].
33
I
SPC8106Foc
External CRT/RAMDAC Interface
Pin Name
Type
Pin#
0
26 .. 33
When MD[7]=1 at RESET, these pins are the Pixel Data outputs. These 8 bits
are connected to the pixel select inputs of the external RAMDAC.
PCLK
0
34
Pixel Clock. Pixel data is clocked out of the chip on the falling edge of PCLK.
BLANK#
0
44
Blank output. This output is clocked out on the falling edge of PCLK and is driven
low during display blanking periods.
HSYNC#
0
41
Horizontal Sync. This output is clocked out on the falling edge of PCLK and is
driven to indicate the horizontal retrace period. The polarity of this signal is
determined by a control bit in register 3C2h.
VSYNC#
0
42
Vertical Sync. This output is clocked out on the falling edge of PCLK and is
driven to indicate the vertical retrace period. The polarity of this signal is
determined by a control bit in register 3C2h.
DACRD#
0
43
RAMDAC Read Stobe. This signal goes low when a valid read access to the
VGA RAMDAC is decoded by the chip.
DACWR#
0
45
RAMDAC Write Stobe. This signal goes low when a valid write access to the
VGA RAMDAC is decoded by the chip.
RS2
0
46
Register Select 2 output. This output should be connected to the RS2 input of
the RAMDAC (Bt477 or equivalent). The logic level on this output may be set
by setting Auxiliary Register lOB] bit 3. This signal is required to allow CPU
access the control and overlay registers of the external RAMDAC.
0L[0:1]
I/O
39,38
Multiple Function: Overlay Select outputs 1:0. When MD[13] =0 at RESET,
these pins are outputs used to provide sprite/HW cursor function on the CRT
display. In this case, these outputs should be connected to the OL[0:1] inputs
of the RAMDAC (Bt477 or equivalent). They are used by the sprite circuitry to
access the overlay registers in the RAMDAC. For alternate function see
"Multiple Function Pin Descriptions" on page 16.
OL23
0
35
Overlay Select output 2/3. This output should be connected to both the OL2 and
OL3 inputs of the RAMDAC (Bt477 or equivalent). This signal is used by the
sprite circuitry to access the overlay registers in the RAMDAC.
D477
0
40
477 Control Signal. This output should be connected to the 477/471 input of the
RAMDAC (Bt477 or equivalent). This signal is used to access the control
register of the RAMDAC and to allow it to be powered down. The logic level on
this output can be controlled by setting Auxiliary Register lOB] bit 4, and is also
controlled by the power save logic.
IREFEN#
0
47
IREF Enable outout. This signal is used to control the external current reference
source required by the RAMDAC, allowing powering down the analog circuitry
when not required. When this signal is driven low, the external current reference
should be enabled. When this signal is high, the external current reference
should be shut off.
MS[2:0]
1/0
83,82,71
Monitor Sense inputs. These signals should be connected to the monitor sense
lines from the CRT monitor cable. The status of these bits is readable in
Auxiliary Register [08] bits 2:0, and is used by BIOS software to determine the
presence and type of monitor connected. Optionally, the SENSE output of the
RAMDAC may be connected to one of these inputs to allow the BIOS to read
the SENSE signal and detect the monitor. MS[2: 1] can be forced low by the
DCC2 monitor support bits in Auxiliary Register [10] bits 1:0.
P[0:7]
Description
34
SPC8106Foc
Power Save Mode Control
Pin Name
Type
Pin#
SUSPEND#
I
84
A low level on this pin puts the chip into a hardware power down mode. The
SUSPEND# signal overrides any software initiated power down modes, and
disables the ISA-Bus interface inputs except RESET. Address and Data inputs
are also masked when this signal is low. When in Suspend Mode the UD(3:0),
LD(3:0), XSCL, XSCL2, LP, YD and WF signals are driven into a high
impedance or low state (configurable) and the LCDPWR# signal is driven high.
Description
PDCLK
I
143
Power Down Clock. This input may be used to provide a low frequency clock
for generating refresh in Power Save Modes 4 and Suspend, as an optional
alternative to using the pixel clock or sMEMEN input as the refresh clock
source. This clock input should be driven by either a 32kHz 50% duty cycle clock
source, or a 64kHz clock source with a high period as short as possible (but>
minimum RAS low pulse width) to minimize DRAM current consumption during
refresh. The PDCLK input is used to directly generate the RAS and CAS pulses
during Power Save Mode 4 and Suspend.
Power Supply
Pin Name
Type
Pin#
COREVoo
P
14,37,
85,92,
109
IOVDD
P
1,50,73,
124
Vss
P
11,36,
88,89,
108
IOVss
P
49,72,
123, 144
Description
Voo supply for core logic.
VDD supply for interface pins.
Vss supply for core logic.
Vss supply for interface pins.
35
I
SPC8106Foc
Pin Mapping for Various Display Modes
Pin Name
YO
Displav Mode
CRT
LCD
None
YD
RG81
TFT
12-bit RG8
VSYNC#
9-bit
12-bit
VSYNC#
VSYNC#
VSYNC#a
LP
None
LP
HSYNC#
HSYNC#
HSYNC#
HSYNC#a
WF
None
WF
None (forced 0)
None (forced 0)
DATAEN
DATAEN
XCSL
None
XCSL
PCLK
PCLK
PANCLK
PANCLK
XCSL2
None
XCSL2
None (forced 0)
R[3]
R[2]
R[3]
UD[3]
None
UD[3]
None (forced 0)
8[3]
8[2]
8[3]
UD[2]
None
UD[2]
None (forced 0)
8[2]
8[1]
8[2]
UD[1]
None
UD[1]
None (forced 0)
8[1]
8[0]
8[1]
UD[O]
None
UD[O]
None (forced 0)
R[2]
R[1]
R[2]
G[3]
LD[3]
None
LD[3]
D[3]
G[3]
G[2]
LD[2]
None
LD[2]
D[2]
G[2]
G[1]
G[2]
LD[1]
None
LD[1]
D[1]
G[1]
G[O]
G[1]
LD[O]
None
LD[O]
D[O]
R[1]
R[O]
R[1]
OLO
OLO
None
None
8[0]
None
8[0]
OL1
OL1
None
None
G[O]
None
G[O]
OL23
OL23
None
None
R[O]
None
R[O]
Mixed Voltage Configurations
I/O Voo
Core Voo
3.3
5.0
3.3V
OK
OK
5.0V
NO
OK
Summary of Configuration Options
Pin Name
Value on this pin at falling edge of RESET is used to configure: (1/0)
MD [3:0]
Values latched into read-only Aux Reg rOC] bits 3:0 for software use
MD[4]
8-bit I/O interface (1) / 16-bit I/O interface (0)
MD[5]
A [19:2] latched internally by ALE (1) / standard ISA bus ALE - A [16:0] not latched (0)
MD[6]
2 CAS, 1 WE type DRAM (1) / 1 CAS, 2 WE type DRAM (0)
MD[7]
Support 16-bit panel with external logic (1) / support 16-bit panel directly (0)
MD[8]
5 V core operating voltage (1) /3.3 V core operating voltage (0)
MD [12:9]
MD [13]
Values latched into read-only bits 7:4 of Aux Reg rOC] for software use
Pins 38, 39 used for ext. RC for 32 KHz PDCLK (1) / pins 38, 39 used for OL [1 :0] (0)
MD [14]
Internal PDCLK doubling disable (1) / enable (0)
MD [15]
3C3h used as video enable port (1) / 46E8h and 102h used as video enable port (0)
These inputs have internal pullup resistors. Based on the value of the internal pull-ups, the external pull-down
resistors if necessary, should be approximately 15K ohm. This value will provide the correct voltage levels
on power-up without loading the DRAM Data lines (Voo =5.0V).
36
SPC8106Foc
Multiple Function Pin Descriptions
Pin Name
LCAS#, LWE#
UCAS#, CAS#
WE#, UWE#
Function
MD Line Status
LCAS#
MD [6] = 1
LWE#
MD [6] =0
DRAM write strobe (low byte)
UCAS#
MD [6] = 1
DRAM column address strobe (high byte)
CAS#
MD [6] =0
DRAM column address strobe
WE#
MD [6] = 1
DRAM write strobe
UWE#
MD [6] =0
DRAM write strobe (high byte)
OLO
MD [13] =0
Overlay bit 0 used for CRT
HW Cursor/Sprite support
P320
MD [13] = 1
MD[14]=1
32 KHz clock outpur. Used with external RC
when using external PDCLK support
OL1
MD[13]=0
Overlay bit 1 used for CRT
HW Cursor/Sprite support
P321
MD[13]=1
MD[14]=1
32 KHz clock outpur. Used with external RC
when using external PDCLK support
P[O:3]
MD [7] = 1
Lower nibble of the CRT pixel data outputs
UD[4:7]
MD[7] =0
Upper nibble of the 16-bit LCD mode upper
panel data
P[4:7]
MD [7] = 1
Upper nibble of the CRT pixel data outputs
LD[4:7]
MD [7]=0
Upper nibble of the 16-bit LCD mode lower
panel data
OLO, P320
OL1, P321
P[0:3], UD [4:7]
P[4:7], LD [4:7]
Functional Description
DRAM column address strobe (low byte)
37
I
SPC8106Foc
Illustrated below are the display data output which are output from the UDO to UD3, LDO/UD4 to LD3/UD7
and the display on the panel:
UD31UD21UDliUDOI
UD31UD21UDliUDOI LD31 LD21 LDll LDO I
Dual Panel-Top
8-bit Single Panel
LD31LD21LDli LDO I
Dual Panel - Bottom
4-bit Single Panel
•
LCD Panel Pixels
640 DOTS
r
1- 1
2-1
1 1-2
1 2-2
11-63911-640
1
24o LINES
12-63912-640
UPPER LCD PANEL
240 - 1 1 240 - 2 1
1240-6391240-640
241 - 1 1 241 - 2 1
1241- 6391241- 640
(TOP VIEW)
24o LINES
L
LOWER LCD PANEL
480-11480-21
1480-6391480-640
38
SPC8106Foc
•
Monochrome Passive STN LCD Panel Interface
4-bit Single Panel
..
,
LP : 242 PULSES
YO __________~r__lL____________
I
LP
WF
UO[3:0]
LP
WF
XSCL
LINE 1
LINE 2
~
----l~
.
n'--___
XSCL, 80 C"lCK PERIODS
>1
.. ~ ______~ .. ~
UD3----··~-----·~··-...CJ..
UD2
.. ~-----.~ .. _...CJ..
UD1
.. ~-----.~ .. _...CJ..
UDO
.. ~-----.~ .. _...CJ..
Example timing for 320 x 240 panel
39
SPC8106Foc
•
Monochrome Passive STN LCD Panel Interface
8·bit Single Panel
I~
YO
LP : 482 PULSES
--------~~~----------
LP
UD[3:0]
LD[3:0]
LP
-----.rl
~ I~
XSCL _
XSCL: 80 CLOCK PERIODS
~I
nL.....---
.. ~ _______ ~ ..
JL
UD3---··~-------~··~
UD2---··~-------~··~
UD1---··~-------~··~
UDO---··~-------~··~
LD3---··~-------~··~
LD2---··~-------~··~
LD1---··~-------~··~
LDO---··~-------~··~
40
SPC8106Foc
•
Monochrome Passive STN LCD Panel Interface
8-bit Dual Panel
,
YD
LP : 242 PULSES
..
----------~~~-----------
I
LP
UD[3:0]
LD[3:0]
LINE 241
LINE 242
____________________
LP
..
XSCL: 160 CLOCK PERIODS
~Il~
____
.,
XSCL _____ ~ _______ ~ __ ~
UD3-----~-------~--~
UD2-----~-------~--~
UD1-----~-------~--~
UDO-----~-------~--~
_______
r----v
~
~
LD3-----~
LD2 -----
~
-------
__ -"'-----A
~
--
LD1 ----- ~-------~~
--
LDO-----~-------~--~
41
SPC8106Foc
•
Color STN LCD Panel Interface
4-bit Single Panel
LP : 242 PULSES
I'"
YD __________~r__l~____________
LP
WF
UD[3:0]
LP
WF
XSCL2
~
--------9-•
n~
XSCL2, "
CLOCK PER'ODS
__
•
__ ~ ______ ~ __
-.JL
UD3------~------~--~
--~------~--~
UD1
--~------~--~
UDO
--~------~--~
UD2
Example timing for 320 x 240 panel
42
SPC8106Foc
•
Color STN LCD Panel Interface
8-bit Single Panel
.
,
LP : 482 PULSES
YD ________~r_IL_________
·1
______________~r__l~_____
I
LP
UD[3:0]
LD[3:0]
I
LP
~L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
XSCL
UD3 ______.A_=---:..:.:....J\~::.:....A_:...:::::..J\.....:..._=_JL:...:::.:.:..JI..:...:.:..:::JI-
-
-
-
-
-X1--B635X1-R636L___
~
UD2 ____
- - - - - -X1-G636X1--B636L___ ~
UD1 ____
- - - - - -X1-R637X1-G637L___ ~
UDO ____
- - - - - -X1--B637X1-R638L ___ ~
LD3 ____
- - - - - -X1-G638X1--B638L___ ~
LD2 ____
- - - - - -X1-R639X1-G639L___ ~
LD1 ____
- - - - - -X1--B639X1-R640L___ ~
LDO ____
- - - - - -X1-G640X1--B640L ___ ~
43
SPC8106Foc
•
Color STN LCD Panel Interface
8-bit Dual Panel
YD
________ I"
~r--l~
LP : 242 PULSES
___________
LP
UD[3:0]
LD[3:0]
LP
..
XSCl2: 480 CLOCK PERIODS
~1
XSCl2 _ _ .. ~ _______ ~ ..
~
_______
~
JL
r--v
UD3--.. ~
~ .. ---1L.--A
~-------~
r--v
UD2--.. ~
~ .. ---1L.--A
~-------~
r--v
UD1--.. ~
~ .. ---1L.--A
~-------~
r--v
UDO-- .. ~
~ .. ---1L.--A
~-------~
r--v
LD3-- .. ~
~ .. ---1L.--A
LD2
- - .. ~-------~ .. ~
~LDl - - .. ~
- - - - - - X
~-_--
LDO-- .. ~
44
___
X241-8637X241-R639X241-G640L
~
~
r--v
.. ---1L.--A
r--v
.. ---1L.--A
SPC8106Foc
•
Color STN LCD Panel Interface
16-bit Single Panel
YD
________ I"
~r--l~
LP : 482 PULSES
___________
I
LP
UD[7:0]
LD[7:0]
LP~r----
- I..
XSCL: 120 CLOCK PERIODS
~
1
XSCL ___ ~ _______ ~ __ ~
UD7----~-------~--~
UD6----~-------~--~
UD5----~-------~--~
UD4----~-------~--~
~-------~
r--v
UD3----~
~ __ --A--..A
~-------~
r--v
UD2----~
~ __ --A--..A
~-------~
r--v
UD1----~
~ __ --A--..A
~-------~
r--v
UDO----~
~ __ --A--..A
LD7----~-------~--~
LD6----~-------~--~
LD5----~-------~--~
LD4----~-------~--~
~-------~
r--v
LD3----~
~ __ --A--..A
~-------~
r--v
LD2----~
~ __ --A--..A
~-------~
r--v
LD1----~
~ __ --A--..A
~-------~
r--v
LDO----~
~ __ --A--..A
45
SPC8106Foc
•
Color STN LCD Panel Interface
16-bit Dual Panel
YO
LP : 242 PULSES
I'"
--------~~~-----------
LP
UD[7:0]
LD[7:0]
LP
LINE 241
LINE 242
LINE 243 LINE 244
LINE 479
LINE 480
LINE 241
LINE 242
~f-------
-
I...
XSCL: 240 CLOCK PERIODS
.1
XSCL ____ ~ _______ ~ __ ____.JL
UD7----~-------~--·~
UD6----~-------~--~
UD5----~-------~--~
UD4----~-------~--~
UD3 - - - - ~-------~~
-UD2 - - - -
~-------~~
--
UD1---- ~-------~~
'
-UDO - - - - ~-------~~
--
LD7----~-------~--~
LD6----~-------~--~
LD5----~-------~--~
LD4----~-------~--~
LD3----~-------~--~
LD2----~-------~--~
LD1 ----~-------~--~
LDO
----~-------~--~
46
SPC8106Foc
•
Color STN LCD Panel Interface
16-bit Single Panel with External Circuit
LP : 482 PULSES
YD
LP
WF
Pixel Data
LINE 479
I
LP ______~IlL
WF
LINE 480
LINE 1
LlNE2
______________________
=====:JX~============
~I
XSCL
-----~.---
------ ..
- - - -..
1 R1
1 B3
-
-
-
-Xl-B635Xl-G63SL. --
1~Bl
1-G4
-
-
-
-Xl-G636Xl-R639L. --
UDl - - -..
1 G2
1 R5
-
-
-
- - -..
1 R3
1 B5
- - -
UD3
UD2---··
UDO
LD3---··
LD2---··
LDl
- - -..
LDO---··
UD7---"~
UD6---"~
UD5---"~
UD4---"~
-Xt-R637Xl-B639
L ...
-Xl-B637Xl-G640L."_
L. __
1 G1
1 R4
-
-
-
-Xt-R63SXt-B638
l-R2
184
-
-
-
-Xl-B63SX1-G639L. . .
1 82
l-G5
-
-
-
-Xl--G637Xl-R640
1-G3
l-R6
-
-
-
-Xt-R63SX1-B640
l-Al
:====:===~X-
1-B635
1-81
X
:===~X~===X -
1-G636
1 G2
X~==~X
1 R637
l-A2
X'--____-'X
- - - -X
- - - -X
X- - - - -X
X- - - - -X
UD3 - - - - - - - - - -.. ~- - - -
1-B637
L. __
L. __
L
L
L
L
.. .
.. .
.. .
.. .
-~.. .
~-----~ .. .
UD2
..
UDl
.. ~-----~.. .
UDO
..
~-----~ .. .
LD6
- -.. ~
- -.. ~
LD5
- -.. ~
1 B2
LD4
- -.. ~
1-G3
LD7
l-Gl
l-R2
X- X- X- X- -
X
X
X
X
- - -X
- - -X
- - -X
- - -X
LD3 - - - - - - - - - -.. ~- - - -
l-R636
1-8636
1 GS3?
l-R638
L
L
L
L
...
...
...
...
-~.. .
LDl
~-----~.. .
.. ~-----~.. .
LDO
.. ~-----~.. .
LD2
..
47
EXTERNAL CIRCUIT
(required when
MDI7]=1 at reset)
I
SPC8106Foc
•
Color STN LCD Panel Interface
16-bit Dual Panel with External Circuit
LP ; 242 PULSES
YD
LP
WF
Pixel Data
INE 21242 LINE 31243 LINE 41244
LINE 11241
LINE 11241
LINE 21242
-InL..I ____________
LP _ _ _
WF-----~r--------------------
-----~.------ - - -X1-G638X1-B639 L .. _
XSCL
UD3 _____ _
UD2 _ _ _ _.. _ _"-'-=-"-'=-"-='-"-_--''----'''--_/1UD1 _ _ _ _
OM
UDO _____ _
1 R2
l-G3
1-84
- - -
-X1-B638X1-R640L...
-
-
-
-X1-R639X1-G640L __ _
-
-
-
-X1-G639X1-B640L. __
",2,-,4.:..1-'-.:R1=24:;.1-..oG::.2",2;;:.41c;-B=3",-_-,,-_-,,-_...JI- - - -
LD3 _ _ _ _ •• _ _
LD2 _____ _
241--G1 241-82 241-R4
-
LD1 _ _ _ _ . _
241-81 241-R3 241-G4
-
LDO _____ _
241-A2 241-G3 241-84
UD7 _____••
-
-~
-~ __ _
-
-
-
-~ __ _
-
-
-
-~ __ _
X- - - - -X
1-R639
X- - - - -X 1-G639
X
X
__
-
-----.f..~==~==~:===:X- - - - -X 1-G638
X
X- - - - -X 1-B838
---.f-.
UDS - - -•. ---.f-.
UD4 - - -.• ---.f-.
UD6 _ _ _..
-
L
L
L
L
...
...
...
...
UD3 - - - - - -.. ~-----~...
UD2
.•
UD1
•.
~-----~•..
~-----~.•.
UDO
.•
~-----~•..
LD7
LD6
LDS
LD4
_ _.. ---.f-.
_ _.. ---.f-.
_ _.. ---.f-.
_ _.. ---.f-.
241-R1
241-G1
X- - - --X
X-- -- -X
X- -- --X
X-- -- -X
X
X
241-81
X
241-R2
X
241-G638
241-8638
241-R639
241-G639
L
L
L
L
...
...
...
...
LD1
~-----~..•
--~-----~----~-----~---
LDO
.. ~-----~...
L03 - - - - - -••
LD2
48
EXTERNAL CIRCUIT
(required when
MD[7J=1 at reset)
SPC8106Foc
•
Color TFT Panel Interface
Auxiliary Register [00] bit 5=1 and Auxiliary Register [08] bit 1=1
350 Line Mode
61 HRTC PULSES
HRTC 350 PULSES
---~
VSYNC*
HSYNC*
----~---~
R[3:0], G[3:0]. 8[3:0]*
---~~-----------
400 Line Mode
400 PULSES
VSYNC*
~-r------~----r
HSYNC*
----1JlJLr---y-
480 PULSES
VSYNC*
___ r-
---~~-----------
R[3:0], G[3:0]. 8[3:0]*
480 Line Mode
I
I
r----------f---_t_
-~
----1JlJLr---y-
HSYNC*
_ _ _ _J~_ _J\---~_ _ _ _ _ _ _ _ _ __ _
R[3:0], G[3:0]. 8[3:0]*
HSYNC* (400, 480) ~-------HSYNC* (350)
PANCLK*
DATAEN*
R[3:0]*
G[3:0]*
8[3:0]*
~-------- - - - - - - - , - - - - - - - - - - '
SLfULJL ____ J-m~:_~~~~
____ JLJL
--------~
----------------~~------~~-----------~------~
----------------~
~-------------
----------------~~------~~------------
9-bit panels use data bits [2:0]
* Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names
49
I
SPC8106Foc
•
Color TFT Panel Interface
Auxiliary Register [00] bit 5=1 and Auxiliary Register [DB] bit 1=0
UP TO 1023 HRTC PULSES
2-65 HRTC PULSES
VSYNC*2
HSYNC*2
R[3:0], G[3:0], 8[3:0]*2
____~c__~,~---~~_____________
HSYNC*2
CLOCK: 640 CLOCKS
PANCLK*2
DATAEN*2
R[3:0]*2
G[3:0]*2
8[3:0]*2
~ -------- --- ~-------~
=======:~
====:~
----- ------
~-------~
------------ ~-------~
9-bit panels use data bits [2:0]
*1: This number is controlled by Auxiliary Register [06] bit 2
*2: Refer to "Pin Mapping for Various Display Modes" on page 15 for actual pin names
50
SPC8106Foc
•
RGB Mode Panel Interface
12-bit RGB Mode Panel
VSYNC*
HSYNC*
R[3:0J, G[3:0J, 8[3:01'
PCLK: 1280 CLOCKS
PCLK 224 CLOCKS
HSYNC*
__~~I'~~~~~~'[~
___~_J~----
PCLK*
ILJLJ -- - - - - ILIlJLSL
R[3:01'
G[3:01'
8[3:01'
------X
======~~- ------X
======~~-
X- - - - - - -
1-640 X241- 640
~
~-------X1-640X241-640X - - - - - - - ~
X- - - - - - - ~
1-640 X241-640
* Refer to "Pin Mapping for Various Display Modes" on Page 15 for actual pin names.
•
RGBI Mode Dual Panel Interface
RGBI Mode Dual Panel
VSYNC*
'.
HSYNC : 240 PULSES
HSYNC : 2 PULSES
''-----1_
_-----''I'
HSYNC*
I, R, G, S*
PCLK : 1280 CLOCKS
HSYNC*
PCLK*
I, R, G, S*
PCLK : 224 CLOCKS
------j'[ ____ Jf------
------~I~·--------
_______= ------
------·ILJLJ -------lLILJLJL
-X 1-640 X241 -640X
- - - - - - -
* Refer to "Pin Mapping for Various Display Modes" on Page 15 for actual pin names.
51
~
I
SPC8106Foc
•
PACKAGE DIMENSIONS
QFP17-144 pin
Unit: mm
22.0
±O.4
20.0
±O.1
72
109
ci
+1
o
oC\I
1
a
ci
+1
Ll)
..-
0
><
as
~
0
C\I
37
144
l!)
....
ci
+1
o
C\i
...
0.5 ±O.1
JI.
0.2 ±O.1
36
cv)
0-10°
1.0
52
SPC8107FoE
LOW VOLTAGE VGA LCD CONTROLLER
•
DESCRIPTION
The SPC81 07FoE is a single-chip, low-voltage LCD controller based on the VGA architecture and dedicated
to driving a liquid crystal display. The fully VGA-compatible controller core, high-performance CPU interface
and flexible 64 x 4-bit gray-scale lookup table are integrated into a very small footprint 1OO-pin QFP package.
The target markets for this device are low-cost and low-power sub-notebook and handheld products where
low component count and a high performance 80 x 86 microprocessor interface are the major design
considerations.
•
FEATURES
• Low-power CMOS technology
• Package: QFP15-100 pin
• Hardware VGA compatible
• One 256K x 16 self-refresh DRAM
• 3.3 volt core
• Monochrome LCD panel interface, for sizes 320 x
200 to 640 x 480
• Four-stage display pipeline
• On-chip 64 x 4 gray-scale look-up table
• Video BIOS, software driver and utility support
• 16 gray shades by frame rate modulation
• Single two-terminal crystal support
• Three programmable gray-scale weightings
(RGB), base (25, 50, 25), NTSC (30, 59,11), and
text (0, 100, 0)
• High performance ISA & PI bus support
• Five power-down modes
•
BLOCK DIAGRAM
/
I
,-
...
CRYSTAL
I
~
SPC8107
LOWVOLTAGEVGA
LCD CONTROLLER
~
PIBUS
ISABUS
t
256K x 16
DRAM
53
MONOCHROME
LCD
I
SPC8107FoE
•
~
ISA BUS SYSTEM BLOCK DIAGRAM
I
25.175 MHz
32 KHz
tL
REFRESH
IAEN
-lOR
-lOW
-MEMR
-MEMW
-IOCHRDY
OWS
IRQ2
RESETDRV
SAT[19:0]
0[7:0]
SUSPEND
C.Di\~
7 pF
1
P321
MEMEN
IOEN
0
'"'""-
1f
>e
2M
...J
;;2
§!
0
()
...J
()
...J
()
7 pF
1-4~
"-
!OFf
lOW
MEMR
MEMW
READY
OWS
IRQ
RESET
A[19:0]
0[7:0]
YO
LP
XSCL
UD[3;0]
LD[3;0]
LCDPWR
SPC8107
YO
LP
XSCL
UD[3;0]
LD[3;0]
LCDPWR
LCD PANEL
DISPLAY
YO
LP
XSCL
UD[3;0]
LD[3;0]
LCDPWR
LCD PANEL
DISPLAY
_iO'
o~
til~I~I~I~
---
SUSPEND
, ,W
MD5
W - -IUlIUlIUlI
~~~(3(3S
0
«5'
17
-I::J
256K x 16 DRAM
•
PI-BUS SYSTEM BLOCK DIAGRAM
25.175 MHz
r=!D}~ 7 pF
2M
1~
7 pF
f
--
SBHE
PSTART
PCMD
-VGACS
PM/lO
PW/R
PRDY
RESET
A[16:0]
0[15:0]
SBHE
PSTART
PCMD
VGACS
PM/io
PW/R
PRDY
RESET
A[16:0]
0[15:0]
---
--
;;2
0
...J
...J
()
>e
()
YO
LP
XSCL
UD[3;0]
LD[3;0]
LCDPWR
SPC8107
_iO'
o~
SUSPEND
SUSPEND
I~
til~I~I~I~
o~'-:~(3(3S
iO'lUl IUl IUl IW
«5-
...J::J
256K X 16 DRAM
54
SPC8107FoE
•
SPC8107 VIDEO MODES
Mode
Number
(Hex)
0
0+
0++
1
1+
1++
2
2+
2++
3
3+
3++
4
5
6
7
7+
00
OE
OF
10
11
12
13
•
Horizontal
Pixels
Addressable
320
320
360
320
320
360
640
640
720
640
640
720
320
320
640
720
720
320
640
640
640
640
640
320
Vertical
Pixels
Addressable
200
350
400
200
350
400
200
350
400
200
350
400
200
200
200
350
400
200
200
350
350
480
480
200
Horizontal
Pixels
Displayed
320
320
320
320
320
320
640
640
640
640
640
640
320
320
640
640
640
320
640
640
640
640
640
640
Vertical
Pixels
Display~d
200
350
400
200
350
400
200
350
400
200
350
400
200
200
200
350
400
200
200
350
350
480
480
400
Monochrome
LCD Display
(Gray Shades)
16
16
16
16
16
16
16
16
16
16
16
16
4
4
2
2
2
16
16
2
16
2
16
16
SUPPORTED LCD PANELS
8-bit Interface
Dual Panel
Single Panel
Horizontal
Vertical
Horizontal
Vertical
640
400
480
400
480
640
55
4-bit Interface
Single Panel
Horizontal
Vertical
200
320
240
480
320
640
400
480
I
SPC8107FoE
•
FUNCTIONAL BLOCK DIAGRAM
A[16:01
PI-BUS
CONTROL
--1~~---j~=~~------..------~---------,
-il--h-il
OE~O~ER
I
D{15,Oi .-11--1--t-------+----_-~------e---~--_,
~ ;E~O~~~ :~
CU
if>
VDD CORE
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
00
01
02
03
04
05
06
07
RESET
PROY
VSSIIO
>
B
8 do
w
~
(J)(9n..a..a..l-o
>
00 0
Il..
~
~
U
>
0~
10z 0
0
~
~
~ 0
V
~
N
0
~
~
~ 0
N
~
0
~
~~:;;~:;;~:;;~:;;~~
if> 00
> :0
00
M04
M011
M05
M010
M06
M09
M07
M08
LCAS
WE
UCAS
RAS
MA8
MAO
MA7
MA1
MA6
MA2
MA5
MA3
SPC8107
0
~
0
~ ~ M
V
~
o ro m ~ ~ ~ ~ ~ ~ 0
> 0 0 0 0 000 0 r
o
w
"
"8w
8....J
woo
00
(J)
> x
a..
....J
0
>
0
~
~
M
0
0
0
0
....J
....J
....J
....J
~ VDDCORE
I~:s:a...
0
moo
<
~
0
....J
0
~
~
0
~
~
M
~
~
0
0
"'"
U)
>
Note: Pin names on this diagram correspond to the default configuration (PI Bus, 2 CAS, 1 WE DRAM).
59
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDIIO
28
VSSIIO
MA4 27
26
VSSIIO
I
SPC8107FoE
•
PIN DESCRIPTION
Key
C
= CMOS level input
CS
= CMOS level input with hysteresis
COx
= CMOS level output, x denotes cell type
TSx
= Tri-state CMOS level driver, x denotes cell type
= Tri-state CMOS level driver with 100 kQ pull up resistor, x denotes cell type
TSUx
•
CPU Interface - PI-Bus
Note: to configure chip for PI-Bus operation, MD[5] must be held at logic 1 during RESET (there is an internal
pull up for the MD[5] pin, so no pullup resistor is required).
Pin Name
•
Description (when MD [5]
= 1 during RESET)
Type
Pin #
Drv
A[0:16]
I
71 .. 74,77 .. 89
C
CPU bus address inputs. In Suspend Mode, the
Address inputs are internally masked off.
D[0:15]
1/0
90 .. 97,2 .. 9
C
IC03
16 bit PI-Bus data bus. These lines are driven by the
chip only during read cycles, and are in a hi-Z state
at all othertimes. In Suspend Mode, these inputs are
internally masked off.
NGACS
I
69
C
PI-Bus VGA Chip Select. In Suspend Mode, the
NGACS input is disabled.
IPCMD
I
66
C
PI-Bus Command Strobe. In Suspend Mode the
IPCMD input is disabled.
PM/IO
I
67
C
PI-Bus Memory or 110 Select. In Suspend Mode the
PM/IO input is disabled.
PW/R
I
68
C
PI-Bus Write or Read Select. In Suspend Mode the
PW/R input is disabled.
ISBHE
I
70
C
System Byte High Enable. In Suspend Mode the
ISBHE input is disabled.
IPSTART
I
65
CS
PI-Bus Start Strobe. In Suspend Mode the IPSTART
input is disabled.
IPRDY
0
99
TS3
PI-Bus Ready. This output is driven low to terminate
a bus cycle.
RESET
I
98
CS
The active high Reset signal from the CPU clears all
internal registers and forces all signals totheir inactive
state. During Suspend Mode the RESET input is
ignored.
Pin Mapping for ISA/PI Bus Interfaces
Pin No.
PI Bus
Pin Name
ISA Bus Usage
Pin No.
PI Bus
Pin Name
71 ..74,77 .. 89
A[0:16]
A[0:16]
66
IPCMD
IIOR
90 .. 97
D[0:7]
D[0:7]
67
PM/IO
2 ..4
D[8:10]
A[17:19]
68
PW/R
5
D[11]
IRQ
69
NGACS
6
D[12]
lOWS
70
ISBHE
7 .. 9
D[13:15]
PDCLK, P320,
P321
99
IPRDY
IIOW
IMEMR
MEMEN
IMEMW
READY
65
IPSTART
IIOEN
60
ISA Bus Usage
SPC8107FoE
•
CPU Interface - ISA-Bus
Note: to configure chip for ISA Bus operation, MD[5] must be held at logic 0 during RESET with an external
pull-down resistor.
Type
Pin#
Drv
Description (when MD [5] = 1 during RESET)
A[0:19]
I
71 .. 74, 77 .. 89,
C
CPU bus address inputs. In Suspend Mode, the
Address inputs are internally masked off.
D[0:7]
I/O
90 ..97
Pin Name
2 . .4
C
8 bit ISA-Bus data bus. These lines are driven by the
IC03
chip only during read cycles and are in a hi-Z state at
all other times. In Suspend Mode, these inputs are
internally masked off.
MEMEN
I
69
CS
ISA Bus Memory Enable. This signal should be
connected to the IRE FRESH signal on the ISA bus.
When this signal is low (e.g. during a system memory
refresh cycle), memory address decoding is disabled.
/lOR
I
66
C
ISA Bus I/O Read Strobe. In Suspend /lOR is disabled.
/lOW
I
67
C
ISA Bus I/O Write Strobe. In Suspend the /lOW is
disabled.
IMEMR
I
68
C
ISA Bus Memory Read Strobe. In Suspend IMEMR
is disabled.
IMEMW
I
70
C
ISA Bus Memory Write Strobe. In Suspend IMEMW
is disabled.
/lOEN
I
65
CS
ISA Bus I/O Enable. This input should be connected
to the ISA bus AEN signal. When this signal is high,
I/O address decoding is disabled. In Suspend Mode,
the /lOEN input is disabled.
READY
0
99
TS3
ISA Bus READY signal. This output is driven low to
force the CPU to insert wait states during memory
cycles. READY is released to high-Z after a transfer
is complete.
RESET
I
98
CS
The active high Reset signal from the CPU clears all
internal registers and forces all signals to their inactive
state. During Suspend Mode the RESET input is
ignored.
IRQ
0
5
TS3
ISA Bus Vertical Interrupt. When enabled, a Vertical
Retrace Interrupt will cause this signal to be driven
from a logic 0 state to a logic 1 (rising-edge triggered
interrupt). Once set, this interrupt must be cleared by
a bit in the CRTC registers. A control bit in the
Auxiliary Registers allows this output to be optionally
disabled (tri-stated).
lOWS
0
6
TS3
o Wait State. This output is driven low when a valid
I/O access is decoded. This will allow the CPU to
complete the ISA bus I/O access with zero wait
states. When inactive, this output will be tri-stated.
61
I
SPC8107FoE
•
Video Memory Interface
Pin Name
Type
Pin #
Drv
Description
MA[0:8]
a
36, 34, 32, 30,
2?, 31, 33, 35,
3?
C03
Multiplexed row/column address bits for video display
memory.
MA[9]
(/RDACK, or WF)
a
19
C03
Multiplexed row/column address bit 9 (MA[9]), or
Read Acknowledge (/RDACK), or LCD Bias Signal
WF, as determined by the logic value on MD[4] and
MD[?] during RESET.
When MD[?] is latched in as 0, this pin functions as
the LCD Backplane Bias signal WF.
When MD[?] is latched in as 1, then this pin's function
is determined by MD[4] as follows: when MD[4] is
latched in as 1, this pin is configured as address bit
MA[9] which is only required for 256K x 16 DRAMs
which are organized as 1024 x 256 x 16 (Le. 10 row
address bits, 8 column address bits). For other
DRAMs, MA[9] is not required. When MD[4] is latched
in as 0, this pin is configured as the IRDACK signal,
which goes low during valid 1/0 or memory reads to
the chip.
MD[0:15]
1/0
42-49, 52-59
IRAS
a
a
38
C06
DRAM Row Address Strobe.
41
C06
DRAM Column Address Strobe for low byte (/lCAS)
or Write Enable Strobe for low byte (/lWE), as
determined by logic value on MD[6] during RESET
(see pin mapping table).
lUCAS
(/CAS)
a
39
C06
DRAM Column Address Strobe for high byte
(lUCAS) or Single Column Address Strobe (/CAS) as
determined by logic value on MD[6] during RESET.
!WE
(/UWE)
a
40
C06
DRAM Write Enable Strobe(!WE), or Write Enable
Strobe for high byte (/UWE), as determined by
logic value on MD[6] during RESET.
Type
Pin #
Drv
Description
I
60
CS
A low level on this pin puts the chip into a hardware
power save mode. The ISUSPEND signal overrides
any software initiated power save modes, and
disables the PI-Bus interface inputs. Address and
Data inputs are also masked when this signal is low.
When in Suspend Mode the UD(3:0), lD(3:0), XSCl,
YD, lP and WF signals are driven into a high
impedance state (optionally driven low) and the
IlCDPWR signal is driven high.
IlCAS
(/lWE)
•
C/TSU3
Data bits for video display memory. The output
drivers ofthese pins are placed into a high-impedance
state when RESET is high, or when the Sequencer
is in a reset state. On the falling edge of RESET, the
values on MD[3:0] are latched into a read-only
Auxiliary Register and are available to be read as
configuration inputs. Other MD inputs are used to
configure various hardware options. See
Configuration Options below.
Miscellaneous
Pin Name
ISUSPEND
62
SPC8107FoE
•
Clock Inputs
Type
Pin #
ClKI
I
62
.
ClKO
0
63
.
PDClK
I
7
C
Power Down Clock. This input may be used in ISA
bus configuration (MD[5] =0 at RESET) to provide a
low frequency clock for generating refresh in Power
Save Mode 4 and Suspend, as an optional alternative
to using the pixel clock or MEMEN input as the
refresh clock source.
P320
0
8
CO2
P32 Clock Output. This pin is used to support a 50%
duty cycle 32 KHz PDClK input (pin 7). This P320
output is a buffered version of the PDClK input used
to drive an external RC circuit. For a 64 KHz PDClK
input, this output should be left unconnected.
P321
I
9
C
P321 Clock Input. This pin is used to support a 50%
duty cycle 32 KHz PDClK input (pin 7). This P321
input should be connected to an external RC circuit
which generates 100-200 ns delay from P320.
Internally this will be used to generate a 64 KHz
refresh clock with the appropriate low period. For a
64 KHz PDClK input, this pin must be tied high.
Pin Name
•
Description
This pin, along with ClKO is the 2-terminal crystal
interface when using a 2-terminal crystal as the clock
input. If an external oscillator is used as a clock
source, then this pin is the clock input.
This pin, along with ClKI is the 2-terminal crystal
interface when using a 2-terminal crystal as the clock
input. If an external oscillator is used as a clock
source, then this pin should be left unconnected.
Power Supply
Pin Name
•
Drv
Type
Pin #
Voo CORE
P
14,26,64,76
Voo I/O
P
1,51,29
Vss CORE
P
11, 25, 61, 75
Vss I/O
P
50,100,28
Description
Voo supply for core logic.
Voo supply for I/O pins.
Vss supply for core logic.
Vss supply for I/O pins.
Configuration Options
Pin Name
MD[3:0]
Values on this pin at falling edge of RESET is used to configure: (i/O)
Values stored in read-only Aux Reg [02] bits 7:4 for software use
MD[4]
Select the function of output pin 19 as MA[9] (1), or /RDACK (0) - see also MD[7]
MD[5]
PI-bus operation (1) /ISA bus operation (0)
MD[6]
2 CAS, 1 WE type DRAM (1) /1 CAS, 2 WE type DRAM (0)
MD[7]
use MD[4] to configure pin 6 as MA9 or /RDACK (1) / pin 6 is WF output (0)
MD[8]
Reserved
MD[9]
Reserved
63
I
SPC8107FoE
•
LCD Panel Interface
Pin Name
Type
Pin #
Drv
Description
YO
0
10
TS12
Vertical Scanning Start Pulse output. A logic 1 on this
signal, sampled by the LCD module on the falling
edge of LP, is used by the panel row drivers (Y
drivers) to indicate the start of vertical frame.
LP
0
13
TS12
Latch Pulse output. The falling edge of this signal is
used to latch a row of display data in the LCD
module's column driver shift registers and to turn on
the row driver (Y driver) for that line.
XSCL
0
12
TS12
Shift Clock for LCD data. Display data is clocked out
of the chip on the rising edge of this signal to be
shifted into the LCD panel module column drivers (X
drivers) on each falling edge.
UD[0:3]
0
21 .. 24
TS12
Upper panel display data for dual panel mode. For
single panel mode these bits are the most significant
4 bits of the 8 bit output data to the panel (PD[4:7]).
For 4-bit single panel mode, these bits are the 4 bits
of output data to the panel.
LD[0:3]
0
15 .. 18
TS12
Lower panel data for dual panel mode. For 8-bit
single panel mode, these bits are the least significant
4 bits of the 8-bit output data to the panel (PD[0:3]).
For 4-bit single panels, these bits are driven o.
ILCDPWR
0
20
C03
LCD power control. In normal operation this signal is
driven low to enable an external LCD power supply.
This signal is driven high when the chip is put into any
power save mode, or if the Sequencer is in a reset
state. It can be used externally to turn off the panel
supply voltage and backlight. After a RESET, this
signal is held high until the CRTC is programmed and
running.
WF (MA[9] or
IRDACK)
0
19
C03
LCD Backplane Bias Signal. This pin is shared with
the MA9 and IRDACK functions. To use this pin as
WF, the value on MD[?] at RESET must be o. The
WF signal toggles once per vertical frame.
64
SPC8107FoE
•
LCD Panel Pixels
...
640 DOTS
1- 1 1 1- 2
2 -1 1 2 - 2
11-63911-640
12-63912-640
1
1
24o LINES
•
UPPER LCD PANEL
240 - 1 I 240 - 21
241 -1 1241 - 2 1
1240-6391240-640
1241-6391241-640
(TOP VIEW)
24o LINES
LOWER LCD PANEL
480-11480-2 1
1480-6391480-640
65
I
SPC8107FoE
•
LCD Panel Interface
8-Bit Single Panel
LP : 482 PULSES
YD
UD3 - UDO
LD3 - LDO
________~XL__,-___________
~-------------------------------
/
I·
LP
XSCL: 80 CLOCKS
~I
XSCL
UD3, UD2, UD1, UDO "-_fl-"""c...::o~J'C=JU'll'-JL_JL_...J\
LD3, LD2, LD1, LDO "-_fl-"""=~==eJW,,-,,-JL_JL_...J\
1-637,638.
69640
8-Bit Dual Panel
LP : 242 PULSES
YD
LP
UD3 - UDO
LD3 - LDO
___________XL____-------------
WF
/
~--------------------XSCL: 160 CLOCKS
I·
______IIL___________
LP
XSCL
UD3, UD2, UD1, UDO
"-_lL"""=",--====:JL_JL_...J\
L03, LD2, LD1 , LDO "--_JL"""'=:oo-..Jc_241"'·~L·'JL"L.i"s,-,'JL_..Jc_~
41-637,638
'"'
4-Bit Single Panel
LP : 242 PULSES
YD
LP
UD3 - UDO
LD3 - LDO
WF
,~_ _ _ _ _ _~X~SC~L~:160CL_O.~C~K~S~_ _ _ _ _ _•
"
" ~I
LP
XSCL
UD3, UD2, UD1, UDO
66
SPC8107FoE
•
POWER SAVE MODES
Software Power Save Mode 3
One hardware-controlled and five software-controlled Power Save Modes are provided by the
SPC8107.
• No video display accesses to display memory.
• No CPU accesses to display memory.
• Sequencer is halted.
Software Power Save Mode 1
• No display memory refresh.
• No video display accesses to display memory.
• I/O read/write of all registers is allowed.
• Dedicated CPU accesses to display memory.
• /lCDPWR signal forced high.
• Display memory refresh is maintained and is generated from ClKI input (nominally 25 MHz). Refresh rate can be selected: 64 kHz or 8 kHz, (for
256 cycle/4 msec, or 256 cycle/32 msec DRAM,
respectively).
Options
• I/O read/write to all registers except Auxiliary
Registers can be disabled.
• I/O read/write of all registers is allowed.
• Internal clock oscillator cell can be disabled if a 2terminal crystal is used.
• /lCDPWR signal forced high.
• LCD output signals tri-stated or forced low.
Options
Software Power Save Mode 4
• LCD output signals tri-stated or forced low.
• No video display accesses to display memory.
Software Power Save Mode 2
• No CPU accesses to display memory.
Mode 2 has two states. Initially the chip enters
State 1. If no display memory read or write is
detected for about two horizontal lines (approx.
63.5 us), the chip enters State 2. If a display
memory read or write is requested while in State
2, the chip returns to State 1 to service the display
memory access within 3 - 7 Ts periods (ClKI
input).
• Sequencer is halted.
• Display memory refresh maintained.
• I/O read/write of all registers is allowed.
• /lCDPWR Signal forced high.
Options
State 1
• Select MEMEN, PDClK, or ClKI as refresh clock
source (ISA only)
• Same as Power Save Mode 1
• I/O read/write to all registers except Auxiliary
Registers can be disabled.
State 2
• Internal clock oscillator cell can be disabled, if a 2terminal crystal is used.
• No video display accesses to display memory.
• LCD output signals tri-stated or forced low.
• No CPU accesses to display memory.
• DRAM self-refresh mode can be used to maintain
display memory contents.
• Sequencer is halted.
• Display memory refresh is maintained and is generated from ClKI input (nominally 25 MHz). Refresh rate can be selected: 64 kHz or 8 kHz, (for
256 cycle/4 msec, or 256 cycle/32 msec DRAM,
respectively) .
Software Power Save Mode 5
• Video display remains active/visible.
• CPU accesses to display memory allowed.
• I/O read/write of all registers is allowed.
• /lCDPWR signal forced high.
Options
• Internal clock can be slowed by 20%.
Options
• LCD output Signals tri-stated or forced low.
67
I
SPC8107FoE
Hardware Power Save Mode (Suspend Mode)
• No video display accesses to display memory.
• No CPU accesses tolfrom display memory.
• Internal clock oscillator cell will be disabled, if a 2terminal crystal is used.
• Sequencer is halted.
Options
• Display memory refresh maintained.
• DRAM self-refresh mode can be used to maintain
display memory contents.
• No 110 register or memory accesses allowed.
• Select MEMEN, PDClK, or ClKI as refresh clock
source (ISA only).
• IlCDPWR signal forced high.
• LCD output signals tri-stated or forced low.
• All CPU interface input signals are internally
masked off. All CPU interface output signals are
inactive.
68
SPC8108Foc
LOW POWER LCD & CRT VGA CONTROLLER
•
DESCRIPTION
The SPC81 08Foe is a versatile VGA graphics controller capable of driving liquid crystal displays and analog
CRT monitors. The controller integrates all LCD interface, sequencing and gray shading logic into one small
form factor 144 pin package. With the addition of an industry standard '477 type RAMDAC, the SPC81 08Foe
will also drive a VGA fixed frequency or multifrequency monitor.
The target products for this device are price and power sensitive 80x86 microprocessor based subnotebooks
or other specialized LCD systems where a high quality 16 or 64 gray shade VGA image on a 320 x 200 to
640 x 480 LCD panel display are the major design criteria.
•
FEATURES
• Low-power CMOS technology
• Monochrome LCD panel interface for sizes
320 x 200 to 640 x 480
• Hardware VGA compatible
• High-performance 16-bit ISA support
• On-chip 256 x 6 grayscale look-up table
• One 256K x 16 self-refresh DRAM
• 16 gray shades by frame rate modulation
• Four-stage display pipeline
• 64 gray shades by frame rate modulation and
dithering
• 64 x 64 pixel hardware cursor
• Two programmable grayscale weightings (RGB),
NTSC (30,59,11), and text (0,100,0)
• Two-terminal crystals support
• Five power-down modes
• Vertical centering and expansion for LCDs
• Video BIOS, software driver and utility support
• Full CRT support with '477 RAMDAC
• 5 volt operation
• QFP17-144 pin
•
BLOCK DIAGRAM
I CRYSTALS I
~
,--
COLOR OR
MONOCHROME
Leo
.....
0
CX>
"T1
0
0
ii31Ci51~1~1~1 ~I
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
oc:
(jj
CI
r
<
0 0 'i? ~ ~ 0 ~ 2 ~ ." s: < < s: s: s: s: s: s: s: s: ~Io
256K x 16 DRAM
89
256K x 16 DRAM
I
SPC8110FoA
•
486DX-33 LOCAL BUS SYSTEM BLOCK DIAGRAM
Shown with 512KB memory option
Intel 486DX
LOCAL BUS
ADR[31 :2] f - - - - - - - - + I
DAT[31 :0]
BE@:Q]
ADS
ADR[31 :2]
DAT[31 :0]
W/R
CLK
RESET
MONID[2:0] 1 + - - - - - - - '
~:O]
ADS
RDYRTN
RDY 1--------+----1 LRDY
MilO
MilO
SPC8110FOA
W/R
BCLK
RESET
UD[3:0]
LD[3:0]
XSCL
XSCLU
YD
LP
WF
I + - - - - - - - - - j LDEV
LCDBIAS f----r.-/~+---'
LCDLOGIC f---~.../
LCDBACK f---+\--"' -\------'
256K x 16 DRAM
90
SPC8110FoA
•
SPC8110 VIDEO MODES
Mode
No.
(Hex)
Pixels
Addressable
Horiz. Pixels
Displayed
Font Size
Vertical
Pixels
Displayed
No. of Shades
LCD
Mono
LCD
Color
LCD
8X8
8X8
16
8X 14
8 X 14
16
9 X 16
8 X 16
8X8
8X8
350
8 X 14
400
9 X 16
Horizontal
(Chars.)
Vertical
(Rows)
CRT
LCD
0
(40)
(25)
320
320
200
0+
(40)
(25)
320
320
350
0++
(40)
(25)
360
320
400
1
(40)
(25)
320
320
200
1+
(40)
(25)
320
320
1++
(40)
(25)
360
320
CRT
Frame Rate (Hz)
CRT
CRT
(Typical)
Single
Panel
LCD
16
16
70
79
78
16
16
70
79
78
16
16
16
70
79
78
16
16
16
70
79
78
8 X 14
16
16
16
70
79
78
8 X 16
16
16
16
70
79
78
Dual
Panel
LCD
2
(80)
(25)
640
640
200
8X8
8X8
16
16
16
70
79
78
2+
(80)
(25)
640
640
350
8X 14
8 X 14
16
16
16
70
79
78
2++
(80)
(25)
720
640
400
9X 16
8 X 16
16
16
16
70
79
78
3
(80)
(25)
640
640
200
8X8
8X8
16
16
16
70
79
78
3+
(80)
(25)
640
640
350
8X 14
8 X 14
16
16
16
70
79
78
3++
(80)
(25)
720
640
400
9X 16
8 X 16
16
16
16
70
79
78
4
320
200
320
320
200
N/A
N/A
4
4
4
70
79
78
5
320
200
320
320
200
N/A
N/A
4
4
4
70
79
78
6
640
200
640
640
200
N/A
N/A
2
2
2
70
79
78
7
(80)
(25)
640
640
350
8 X 14
8X 14
2
2
2
70
79
78
7+
(80)
(25)
720
640
400
9 X 16
8X 16
2
2
2
70
79
78
OD
320
200
320
320
200
N/A
N/A
16
16
16
70
79
78
OE
640
200
640
640
200
N/A
N/A
16
16
16
70
79
78
OF
640
350
640
640
350
N/A
N/A
2
2
2
70
79
78
10
640
350
640
640
350
N/A
N/A
16
16
16
70
79
78
11
640
480
640
640
480
N/A
N/A
2
2
2
60
79
78
12
640
480
640
640
480
N/A
N/A
16
16
16
60
79
78
13
320
200
320
320
200
N/A
N/A
64
256
256
70
79
78
6A
800
600
800
800
600
N/A
N/A
16
16
16
72
65
72
100
640
400
640
640
400
N/A
N/A
64
256
256
72
79
78
101
640
480
640
640
480
N/A
N/A
64
256
256
72
79
78
72
102
800
600
800
800
600
N/A
N/A
16
16
16
72
65
103
800
600
800
800
600
N/A
N/A
64
256
256
72
a65
72
104
1024
768
1024
1024
768
N/A
N/A
16
16
16
60
N/A
70
105
1024
768
1024
1024
768
N/A
N/A
64
N/A
256
N/A
60
70
108
(80)
(60)
640
640
480
8X8
8X8
16
16
16
60
79
78
109
(132)
(25)
1056
N/A
350
8X 14
N/A
N/A
N/A
16
70
N/A
R
10A
(132)
(43)
1056
N/A
350
8X8
N/A
N/A
N/A
16
70
N/A
N
10B
(132)
(50)
1056
N/A
400
8X8
N/A
N/A
N/A
16
70
N/A
N
10C
(132)
(60)
1056
N/A
480
8X8
N/A
N/A
N/A
16
70
N/A
N
91
I
SPC8110FoA
•
Display Resolution Support
The following three tables show the combinations of modes and display types supported by the SPC811 OFOA
with the maximum 40 MHz MClk.
640 x 480
Dual
Color STN
Panel
Simultaneous
CRT & Dual
Mono STN
Panel
yes
yes
yes
yes
yes
yes
yes
ayes
byes
yes
yes
yes
ayes
yes
yes
yes
yes
yes
planar
eyes
yes
yes
yes
yes
256
yes
yes
yes
ayes
ayes
1024 K
0, 1
yes
yes
yes
yes
yes
1024 K
2, 3, 7
yes
yes
yes
yes
ayes
1024 K
fast ext
byes
yes
yes
yes
yes
1024 K
4,5
yes
yes
yes
yes
yes
1024 K
planar
eyes
yes
yes
yes
yes
1024 K
256
yes
yes
yes
yes
yes
Simultaneous
CRT & Dual
Mono STN
Panel
Simultaneous
CRT & Dual
ColorSTN
Panel
Mode
CRT, TFT,
Single STN
Panel
Dual
Mono STN
Panel
512 K
0, 1
yes
512 K
2, 3, 7
yes
512 K
fast ext
512 K
4,5
512 K
512 K
Memory
Notes:
Simultaneous
CRT & Dual
Color STN
Panel
a. if half frame buffer is disabled.
b. fastext is Fast Text Mode
c. planar is 16 Color Planar Mode
800 x 600
Mode
CRT, TFT,
Single STN
Panel
Dual
Mono STN
Panel
Dual
ColorSTN
Panel
512 K
0,1
yes
yes
yes
-
512 K
2,3,7
-
yes
-
-
512 K
fast ext
byes
yes
yes
512 K
4,5
yes
yes
yes
512 K
planar
eyes
yes
yes
-
-
-
-
Memory
512 K
256
-
yes
-
1024 K
0,1
yes
yes
yes
-
1024 K
2,3,7
1024 K
fast ext
yes
yes
byes
yes
yes
1024 K
4,5
yes
yes
yes
1024 K
planar
eyes
yes
yes
1024 K
256
yes
yes
yes
Notes:
a. fastext is Fast Text Mode
b. planar is 16 Color Planar Mode
92
-
SPC8110FoA
1024 x 768
Dual
ColorSTN
Panel
Simultaneous
CRT & Dual
MonoSTN
Panel
Simultaneous
CRT & Dual
ColorSTN
Panel
-
-
-
Mode
CRT, TFT,
Single STN
Panel
Dual
MonoSTN
Panel
512 K
0, 1
yes
yes
512 K
2,3,7
-
512 K
fast ext
-
yes
-
512 K
4,5
yes
yes
yes
512 K
planar
eyes
yes
512 K
256
-
-
-
1024 K
0, 1
yes
yes
yes
1024 K
2,3,7
-
1024 K
fast ext
-
yes
-
Memory
1024 K
4,5
yes
yes
yes
1024 K
planar
eyes
yes
yes
1024 K
256
yes
yes
-
Notes:
a. fastext is Fast Text Mode
b. planar is 16 Color Planar Mode
93
-
-
I
SPC8110FoA
•
FUNCTIONAL BLOCK DIAGRAM
14.318 MHz - 1 - - - - - - - - - - - - - + 1
1-- - - - - - - - - - - ADR[31:2]
DAT[31:0]
BUS
CONTROL
L
1
-
-
-
-
-
-
-
-
-
-
-I
1
1
Red
Green
Blue
HSYNC
VSYNC
IREF
1
1
1
1
1
1
MA[9:0]
MDA[15:0]
1
MDB[~ .-4+-------.1
CAS[wt
PS1PIN
PS4PIN
32 KHz
1_ _ _ _ _ _
'--_-_-_-_-_-_--'_
T
--1---------------,--.\
XSCLU
XSCL
UD[7:0]
LD[7:0]
LCD
TFTB[1:0]
I-------,+-. LP
Controller IIF
YD
___________ J
WF
I-,--------------~
94
LCDBIAS
LCDLOGIC
LCDBACK
SPC8110FoA
•
FUNCTIONAL BLOCK DESCRIPTION
Host Interface
Display FIFO
This is an 8 stage by 32-bit FIFO that is used to
buffer the video data from display memory.
The Host interface can be programmed to interface to any of the following three standards:
486DX local bus interface, VL-Bus interface, and
PCI interface. It has a one-stage buffer for zero
wait-state write operation.
VGA Palette
This block implements the standard 256 x 18
VGA lookup table.
Clock Generator
DAC
The clock generator contains two PLL's that are
separately programmed to produce the memory
and pixel clocks from a single clock source. The
reference clock is typically 14.318 MHz.
This block functions as a triple 6-bit 65 MHz DAC
to drive the RGB outputs connected to the analog
monitor.
LCD Interface
VGACore
This block contains frame rate modulation and
dithering circuitry for a maximum of 64 shades of
gray in monochrome Single and dual panel modes.
In color LCD mode, it uses frame rate modulation
to generate 4K colors, and additional dithering
techniques for a full 256K colors.
The VGA Core contains the Sequencer, CRTC
Controller, Graphics Controller, Attribute Controller, and the rest of the standard VGA circuitry.
Hardware Cursor
The Hardware Cursor block generates a 4 gray
shade or color, 64 x 64 x 2-bit hardware cursor!
sprite that can be overlaid on the displayed image.
Power Save Logic
This block implements all the power down features of the chip.
Bit Block Transfer (BitBLT) Engine
The Bit Block Transfer Engine performs read,
write, move BLTs, solid fills, destination inversions, and pattern fills. It performs all data alignment and masking at the BLT boundary. It also
performs text expansion to accelerate the writing
of monochrome images. It operates in both 4-bit
planar mode and 8-bit linear (packed-pixel) mode.
95
I
SPC8110FoA
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameters
•
Voo
Input voltage
VIN
Output voltage
VOUT
Storage temperature
TSTG
Soldering temperatureltime
TSOL
Units
-65 - 150
260 for 10 sec max at lead
°C
V
V
V
°C
Recommended Operating Conditions
Parameter
Supply voltage
Supply voltage
Input voltage
Operating temperature
•
Rating
Vss-O.3 to +7.0
Vss-0.3 to Voo +0.3
Vss-O.3 to Voo +0.3
Codes
Supply voltage
Symbol
Condition
HVDD
LVDD
VIN
TOPA
Vss=OV
Vss = OV
Vss
Value
Typ
5.0
3.3
Min
4.5
3.0
Vss
Max
5.5
3.6
VDD
70
25
0
Unit
V
V
V
°C
Input Specifications
Parameter
Low level input voltage
High level input voltage
Pull down resistance
Pull down resistance
Positive-going threshold
CMOS Schmitt Trigger
Negative-going threshold
CMOS Schmitt Trigger
Hysteresis voltage
CMOS Schmitt Trigger
Clock pin capacitance
Input pin capacitance
Input leakage current
Symbol
VIL
VIH
HRpD
LRpD
Condition
VDD =4.5 V/3.0 V
VDD = 5.5 V/3.6 V
VDD= 5.0V
VDD= 3.3V
VT+
VDD= 5.13.3V
VT-
VDD= 5.13.3V
0.6
V
HVH
VDD=5.13.3V
0.1
V
CIN
BCLK,RESET#,REFCLK,
MONID [2:0], TSTENPSIPIN,
PS4PIN, PSCLK
All pins not listed in CIN
VDD=MAX
VIH= VDD
VIL= Vss
CBID
IL
96
Min
Typ
Max
0.8
2.0
25
45
Unit
V
V
50
90
100
180
KQ
2.4
V
4
pF
10
-1
KQ
pF
1
!1A
SPC8110FoA
•
Output Specifications
Parameter
Low level output voltage
Type 2
Type 3
Type 4
High level input voltage
Type 2
Type 3
Type 4
Symbol
Off-state leakage current
loz
VOL
VOH
Condition
VDD = 5 /3.3 V
ioL = 6mA
10L = 12mA
10L = 24mA
VDD = 5 /3.3 V
IOH=-2mA
10H =-4mA
IOH=-8mA
VDD =MAX
V,H= VDD
V,L= Vss
97
Min
Typ
Max
Unit
Vss + 0.3
V
VDD- 0.3
-1
V
1
!LA
I
SPC8110FoA
•
SPC8110 PIN OUT
157
158
1S9
160
161
162
163
164
~~~
167
168
169
170
171
172
173
174
175
176
SOGVss
SOGVDD
GENI02
GENIOl
GENIOO
XSCLU
XSCL
LP
J'
__________~I LI__________~
CVDD
MVss 104
MDA10 103
MOA5 102
MDA11
101
MDA4 100
MDA12 ~
MDA3 98
AVDD
YD
PVoo
LD4
LOS
LOB
LD7
MCLVOD
MCLVss
MVDD
LDO
LOt
LD2
177 LD3
PVDD
178 UD4
179 UD5
180
~:~
~g~
186
187
188
189
190
191
192
193
194
195
196
197
198
199
~~~
~g~
L
TFTB4
TFTB5
WF
LCDBIAS
LCDLOGIC
LCDBACK
ADR2
ADR3
ADR4
ADR5
ADR6
ADR?
ADR8
ADR9
202
~~~s
203
204
205
206
207
208
ADRtO
ADR11
ADR12
ADR13
BCLK
BVss
97
MDA2
MDA14
MOAt
MOA1S
96
95
94
93
MDAO
~~
MVOD
MVss
MDB8
MOB?
90
89
88
87
~g~~
86
MOS10
MOBS
MDB11
85
84
83
~~~: :~
SPC8110FoA
PVss
183 PVoo
184 UOO
185 UOl
MOAt3
I
MDB12 80
MOB3 79
MOB13 78
MDB2 77
MDB14 76
MOBt
75
MOB1S 74
MDBO 73
ADO 72
AD1 71
AD2 70
AD3 69
AD4 68
ADS 67
AD6 ~
AD?
BVoo
c~~~~
AD8
0
BVDD
Note: Pin names correspond to the PCI bus configuration.
Pin placement subject to change.
98
AD9
AD10
AD11
AD12
AD13
AD14
~g~~~~
~~
~
62
6L
60
59
58
57
56
-~
53
SPC8110FoA
•
PIN DESCRIPTION
Key
A
I
o
I/O
P
•
Analog
Input
Output
Bi-directional
Power
CPU Interface
PCIBus
Pin Name
Type
AD [31:0]
I/O
ADR [31:2
Pin #
Description
22-29, 34-41
51,55-61
65-72
PCI multiplexed address and data Bus. These lines are
driven by the chip only during read cycles, and are in a
hi-Z state at all other times.
I
20-3, 206-203,
200-193
Unused VL-bus address inputs. These pins should be tied
high in PCI mode.
C/BE [3:0]#
I
30,43,50,62
PCI bus command and byte enables.
IDSEL
I
31
PCI bus initialization device select.
STOP#
I/O
48
PCI bus stop
FRAME#
I
44
PCI bus cycle frame
IRDY#
I
45
PCI bus initiator ready.
PAR
0
49
Parity. This line is driven by the chip onlyu during read
cycles, and is in a hi-Z state at alii other times. It is always
hi-Z and should be tied high in VL bus mode.
BCLK
I
207
PCI bus clock
TRDY#
I/O
46
PCI bus target ready
DEVSEL#
0
47
PCI bus device select
RST#
I
202
CPU reset. The active low reset signal from the CPU
clears all internal registers and forces all signals to their
inactive state. On the rising edge of the RESET# the
MDA [0 ... 15] bus is latched in for configuration.
99
I
SPC8110FoA
InteI486NL-Bus
Pin Name
Type
Pin #
Description
ADR [31:2]
I
20-3,206-203,
200-193
VL-bus address inputs. These pins should be tied
high in PCI bus mode.
DAT [31:0]
1/0
22-29, 34-41,
51,55-61,
65-72
VL-bus Data inputs. These lines are driven by the chip
only during read cycles, and are in a hi-Z state at all
other times
BE [3:0]#
I
30,43,50,62
VL- bus byte enables.
W/R#
I
31
VL- bus write or read status
M/IO#
I
48
VL- memory or I/O status
ADS#
I
44
VL- bus address data strobe
RDYRTN#
I
45
VL- bus ready return
BCLK
I
207
VL- bus local CPU clock
LRDY#
0
0
46
VL- bus local ready
LDEV#
47
PCI bus local device
RST#
I
202
CPU reset. The active low reset signal from the CPU
clears all internal registers and forces all signals to their
inactive state. On the rising edge of the RESET# the
MDA [0 ... 15] bus is latched in for configuration.
PAR
0
49
Unused (Parity)s. This line is used in PCI mode only. It is
hi-Z state at all times in VL mode and should be tied high
100
SPC8110FoA
•
Video Memory Interface
Pin Name
Type
Pin#
MA[9:0]
0
119,120,
126,128,
130,132,
131,129,
127, 125
MDA[15:0]
I/O
93,95,97,
99,101,
103,108,
110,109,
107,102,
100,98,96,
94,92
MDB[15:0]
I/O
74,76,78, Data bits for video display memory when 1024KB of memory is present
80,83,85, The output drivers of these pins are placed into a high-impedance state
87,89,88 when RESET# is low, or when MClkOFF is active. The inputs have
86,84,82
internal pulldown resistors that have typical values of 50KQ100KQ at 5V/
79,77,
3.3Vrespectively. They should be left open-circuit when only 512KB of
75, 73
memory is attached.
RAS#
0
0
118
DRAM Row Address Strobe
113
DRAM Column Address Strobe for MDA[7:0], or Column Address
Strobe for all bytes, as configured by AUX [03h] bit 7.
CAS[3:1]#
(WE[3:1]#)
0
116-114
WE#
(WE[O]#)
0
117
CAS[O]#
(CAS#)
•
Description
Multiplexed row/column address bits for video display memory.
Data bits for video display memory. The output drivers of these pins are
placed into a high-impedance state when RESET# is low, or when MClkOFF
is active. The inputs have internal pulldown resistors that have
typical values of 50KQ100KQ at 5V/3.3V respectively.
DRAM Column Address Strobes or Write Enable Strobes for {MDB[15:0],
MDA[15:8]}, as configured by AUX[03h] bit 7. CAS[3:2]# (WE[3:2]#)
are unused and should be left open-circuit when only512KB of memory is
present.
DRAM Write Enable Strobe for all bytes or Write Enable Strobe for
MDA[7:0], as configured by AUX[03h] bit 7.
Clock Inputs
Pin Name
Type
Pin#
REFCLK
I
155
This pin is the reference clock used by the internal PLLs to generate all the
necessary clocks. This must be stable during full operation. REFCLK may shut
down only after the chip is totally powered down. Input frequency is typically
14.318 MHz.
Description
PSCLK
I
153
Power Save Clock. This input must be used to provide a low frequency clock
for generating refresh. This clock must be approximately 32 kHz and 50% duty
cycle.
101
I
SPC8110FoA
•
CRT Interface
Type
Pin#
RED,A
GREEN,
BLUE
Pin Name
AO
140,138,
136
Analog outputs from the Video DAC. Internal comparator for monitor sense
is available on all three pins.
HSYNC
0
149
Horizontal Sync. This output is driven to indicate the horizontal retrace period.
In CRT only mode, the polarity of this signal is controlled by register 3C2h, bit
6. In TFT or double scan mode this bit is active low to indicate 640 x 480
resolution. This pin is held low in LCD modes. sThis pin follows the DPMS
standard during power down modes.
VSYNC
0
152
Vertical Sync. This output is driven to indicate the vertical retrace period. In CRT
only mode, the polarity of this signal is controlled by register 3C3h bit 7. In TFT
or double scan mode this bit is active low to indicate 640 x 480 resolution. This
pin is held low in LCD modes. This pin follows the DPMS standard during
power down modes.
IREFA
AI
142
Current reference input for the Video DAC.
I
147-145
MONID[2:0]
•
Description
Monitor ID bits. Connected to the CRT to identify the monitor type.
LCD Panel Interface
Pin Name
Type
Pin#
YD
0
165
Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the
LCD module on the falling edge of LP, is used by the panel row drivers (Y
drivers) to indicate the start of the vertical frame.
Description
LP
0
164
Latch Pulse ouput. The falling edge of this signal is used to latch a row of display
data in the LCD module's column driver shift registers and to turn on the row
driver (Y driver) for that line.
XSCL
0
163
Shift Clock for LCD data. Display data is clocked out of the chip on the rising
edge of this signal, to be shifted into the LCD panel module column drivers (X
drivers) on each falling edge.
Second Shift Clock for some color LCD displays.
XSCLU
0
162
UD[7:0]
LD[7:0]
I/O
180-177,
186-183,
170-167
176-173
Panel display data bus. The data format depends on the specific panel connected. These pins are driven low when the LCD interface is disabled (e.g. CRT only
mode). For 8-bit panels, UD[7:4] and LD [7:4] are driven low.
TFTB[5:4]
0
188-187
TFT display data bus for the two Isb of the color blue. For non-TFT panels, these
two pins are driven low.
LCDBIAS
0
190
LCD power control for the LCD bias circuitry. Active (On) polarity is defined by
the state of MDA[3] on the rising edge of RESET#.
LCDBACK
0
192
LCD power control for the LCD back light. Active (On) polarity is defined by the
state of MDA[1] on the rising edge of RESET#.
LCDLOGIC
0
191
LCD power control for the LCD logic circuitry. Active (On) polarity is defined by
the state of MDA[2] on the rising edge of RESET#.
WF
0
189
LCD Backplane Bias signa/. Output toggling frequency is programmable in an
auxiliary register. For TFT panels, this pin outputs the display enable signals.
102
SPC8110FoA
•
Miscellaneous
Pin Name
Pin#
I
148
This pin, when high, sets the SPC8110FOA into either boundary pin SCAN or
pin output drive test, depending on the state of PS1 PIN. This input has an
internal pull down resistor that has a typical value of 50Kl100Kn at 5 V/3.3 V
respectively.
I/O
121,159,
160,161
Three General purpose I/O pins. Output state of each pin is programmable
to control external devices.
LOOP1
I
143
Connects to Loop Filter Capacitor for PLL 1
LOOP2
I
134
Connects to Loop Filter Capacitor for PLL2
IOUTX[1:0]
A
137, 139
GENI0[3:0]
•
Balanced current output for the DAC.
Power Save Mode Controls
Pin Name
•
Description
Type
TSTEN
Type
Pin#
PS1PIN
I
150
Pin used to initiate a power save mode 1. The polarity of this pin is programmable and has a default polarity of active low. This input has an internal pull
down resistor that has a typical value of 50Kl1 OOK n at 5 V/3.3 V respectively.
When TSTEN is active, the polarity of PS1 PIN selects the test to be either
boundary pin SCAN (PS1 PIN = 1) or pin output drive test (PS1 PIN = 0)
Description
PS4PIN
I
151
Pin used to initiate a power save mode 4. The polarity of this pin is programmable and has a default polarity of active low. This input has an internal pull
down resistor that has a typical value of 50Kl1 OOK n at 5 V/3.3 V respectively.
Power Supply
Pin Name
Type
SOGVDD
P
MVDD
BVDD
Description
Pin #
158,106,54,2
VDD supply for 3.3V core logic
P
112, 91
VDD supply for memory pins
P
32,64
VDD supply for bus interface pins
CVDD
P
154
VDD supply for control interface pins
PVDD
P
166,182
VDD supply for panel interface pins
AVDD
P
135,141
Analog power supply
Vss supply for 3.3 V core logic
Vss supply for memory pins
SOGVss
P
157,105,53,1
MVss
P
111, 124, 104,
90, 81
BVss
P
201, 208, 21, 42, Vss supply for bus interface pins
52,33,63
CVss
P
156
Vss supply for control interface pins
PVss
P
181
Vss supply for panel interface pins
AGND
P
133, 144
Analog ground
MCLVDD
P
122,171
VDD supply for
MCLVss
P
123, 172
Vss supply for
103
I
SPC8110FoA
•
Intel486NL-Bus to PCI Bus Pin Mapping
VL-Bus Name
RST#
RDYRTN#
Pin No.
VL-Bus Name
202
BCLK
IRDY#
45
-
20-3, 206-203,
200-193
W/R#
LDEV#
IDSEL
OAT [31:0]
ADR [31:2]
•
PCIName
RESET#
PCIName
Pin No.
BCLK
207
-
PAR
49
M/IO#
STOP
48
ADS#
FRAME
44
31
LRDY#
TRDY#
46
DEVSEL#
47
BE [3:0]#
C/BE [3:0]
30,43,50,62
AD [31:0]
22-29,34-41,51,
55-61,65-72
MIXED VOLTAGE OPERATION
Mixed Voltage
SOGVoo
MCLVoo
AVoo
BVoo
CVoo
Configuration 1
3.3V
Configuration 2
3.3V
Configuration 3
5.0V
Configuration 4
3.3 V
Configuration 5
3.3 V
Configuration 6
5.0V
Configuration 7
Configuration 8
Configuration 9
5.0V
3.3V
3.3V
Configuration 11
Configuration13
MVoo
3.3 V
5.0V
3.3V
5.0V
3.3V
5.0V
3.3V
5.0V
3.3 V
Configuration 10
Configuration 12
PVoo
5.0V
5.0V
3.3V
Configuration 14
5.0V
Configuration 15
5.0V
Configuration 16
104
3.3 V
5.0V
3.3 V
5.0V
3.3V
5.0V
3.3V
5.0V
SPC8110FoA
•
Default Pin Mapping for the Various LCD and TFT Panel Options
(AUX[07] bit 2 = 0)
TFT
Pin Name
18-Bit
Color
12-Bit
Color
9-Bit
Color
XSClU
XSCl
lP
YO
lD4
lD5
lD6
LD7
lDO
lD1
lD2
LD3
UD4
UD5
UD6
UD7
UDO
UD1
UD2
UD3
TFTB4
TFTB5
WF
lCDBIAS
ClK
ClK
ClK
HS
VS
RO
R1
R2
R3
R4
R5
GO
G1
G2
G3
G4
G5
BO
B1
B2
B3
B4
B5
DE
HS
VS
HS
VS
RO
R1
R2
R3
RO
R1
R2
GO
G1
G2
G3
GO
G1
G2
BO
B1
B2
B3
DE
BO
B1
B2
DE
16-Bit
XSCl
lP
YO
lD4
lD5
L06
L07
lDO
lD1
lD2
lD3
UD4
UD5
UD6
UD7
UDO
UD1
UD2
UD3
WF
(DISP)
105
ColorlCD
8-Bit
Half
8-Bit
Panel
XSClU
XSCl
XSCl
lP
lP
YO
YO
Mono LCD
6-Bit
8-Bit
4-Bit
XSCl
lP
YO
XSCl
lP
YO
UDO
UD1
UD2
UD3
lDO
lD1
lD2
lD3
XSCl
lP
YO
UDO
UD1
UD2
UD3
WF
(DISP)
WF
(DISP)
lDO
lD1
lD2
lD3
lB
lG
lR
UD4
UD5
UD6
UD7
UDO
UD1
UD2
UD3
UDO
UD1
UD2
UD3
UB
UG
UR
WF
(DISP)
WF
(DISP)
WF/DE
(DISP)
I
SPC8110FoA
•
Alternate Pin Mapping for the Various LCD and TFT Panel Options
(AUX[07] bit 2 = 1)
TFT
Color LCD
Pin Name
18-Bit
Color
12-Bit
Color
9-Bit
Color
XSClU
XSCl
lP
YO
lD4
l05
lD6
lD7
LDO
LD1
lD2
lD3
UD4
U05
U06
U07
UOO
U01
UD2
UD3
TFTB4
TFTB5
WF
lCDBIAS
ClK
ClK
ClK
HS
VS
RO
R1
R2
R3
R4
R5
GO
G1
G2
G3
G4
G5
BO
B1
B2
B3
B4
B5
DE
HS
VS
HS
VS
RO
R1
R2
R3
RO
R1
R2
GO
G1
G2
G3
GO
G1
G2
BO
B1
B2
B3
DE
BO
B1
B2
DE
16-Bit
8-Bit
8-Bit
Single
4-Bit x 2
Dual
XSCl
lP
YD
XSCLU
XSCl
lP
YD
XSCl
lP
YD
XSCl
lP
YD
D6
D7
UD2
UD3
D3
D4
D5
lD3
UDO
UD1
DO
D1
D2
WF
(DISP)
lDO
lD1
lD2
WF
(DISP)
UDO
UD1
UD2
UD3
UD4
UD5
lD4
lD5
l06
lD7
UD6
UD7
lDO
lD1
lD2
lD3
WF
(DISP)
.-
106
Mono LCD
UDO
UD1
UD2
U03
lDO
lD1
lD2
lD3
WF
(DISP)
SPC8110FoA
Illustrated below is the display data output as displayed on the panel:
I
4-bit Single Panel
UD3[UD2[UD1[ UDO I
8-bit Dual Panel - Top
8-bit Single Panel
LD3[LD2[LD1[LDO[
8-bit Dual Panel - Bottom
UD7[UD6[UDS[UD4[UD3[UD2[UD1[UDO[
16-bit Dual Panel - Top
16-bit Single Panel
LD7[LD6[LDS[LD4[LD3[LD2[LD1[LDO[
16-bit Dual Panel - Bottom
107
SPC8110FoA
•
LCD Panel Pixels
The figure below shows the pixel layout for a 640x480 dual panel.
640 DOTS
1-1
2-1
l
1-2
1 2-2
11-63911-640
12-63912-640
1
1
24o LINES
UPPER LCD PANEL
240 - 1 1 240 - 2 1
241 - 1 1 241 - 2 1
1240-6391240-640
1241- 6391241- 640
(TOP VIEW)
24o LINES
LOWER LCD PANEL
480-1 1480-2 1
1480-6391480-640
108
SPC8110FoA
•
Monochrome Passive STN LCD Panel Interface
4-bit Single Panel
LP : 240 PULSES
YO
I"
________~r--l~
___________
LP : 0/2 PULSES
(SELECTABLE)"
_______~-I.. ------~~I~
LP
WF
UD[3:0]
LP
WF
XSCL
LINE 1
LINE 2
LINE 3
LINE 4
LINE 239
LINE 240
LINE 1
LINE2
~
----l~:
XSCL' 80 CLOCK PERIODS
•
.. ~ ______~ .. ~
UD3----··~-----·~··~
UD2
.. ~-----.~ .. ~
UD1
.. ~-----.~ .. ~
UDO
.. ~-----.~ .. ~
" Diagram drawn with 2 LP vertical blank period
Example timing for a 320 x 240 panel
109
I
SPC8110FoA
•
Monochrome Passive STN LCD Panel Interface
a-bit Single Panel
LP : 0/2 PULSES
(SELECTABLE)"
LP : 480 PULSES
YD
__________ I"
~r--l~
____________
LP
WF
UD[3:0]. LD[3:0]
LP
WF
LINE 1
LINE 2
LINE 3
LINE 4
LINE 479
LINE 1
LINE 480
LINE 2
~
----1~
.
xsec 00 CU""
"'"'OOS
"I
XSCL ______ ~ ______ ~ __ ____IL
UD3--------~------~--~
--~------~--~
UD1
--~------~--~
UDO
--~------~--~
LD3
--~------~--~
LD2
--~------~--~
LD1
--~------~--~
LDO
--~------~--~
UD2
" Diagram drawn with 2 LP vertical blank period
Example timing for 640 x 480 panel
110
SPC8110FoA
•
Monochrome Passive STN LCD Panel Interface
8-bit Dual Panel
LP : 240 PULSES
YD
I"
----------~~~------------
LP : 0/2 PULSES
(SELECTABLE)'
_______._I_.. ______~~I~
LP
WF
UD[3:0], LD[3:0]
LP
WF
XSCL
LINE 1/241
LINE 21242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 21242
~
-----l'.
xsec '" eCOCK "",ODS
"I
~ ______ ~ __ ~
UD3------~------~--~
--~------~--~
UD1
--~------~--~
UD2
UDO
--~------~--~
L03
.. ~------~ .. ~
LD2
.. ~------~ .. ~
LD1
--~------~--~
LOO
.. ~------~ .. ~
• Diagram drawn with 2 LP vertical blank period
Example timing for 640 x 480 panel
111
I
SPC8110FoA
•
Color Passive STN LCD Panel Interface
6-bit Dual Color Panel
LP: 240 PULSES
YD
I"
_ _ _ _ _ _ _ _ _ _~~L_ _ _ _ _ _ _ _ _ __ _
LP : 0/2 PULSES
(SELECTABLE)*
_______._I_
.. ______·~I~
LP
WF
UD[2:0], LD[2:0]
LP
LINE 11241
LINE 21242
LINE 31243
LINE 41244
LINE 2491479
_ . h_ __
I
-----------
XSCLU: 640 CLOCKS
·1
XSCL~ __ _
-~--~
UD2 - - - - -
UDO - - - - LD2 - - - - LD1
LOO - - - - -
--~
L __ ~
WF
UD1
LINE 1/24
LINE 240/480
1-G1
1-G2
1-G3
1-G4
1-G5
1-G6
1-B1
1-£2
1-83
1-B4
1-85
1-B6
-----~ __ ~
- - - - -
-~
.. ~
241-R1 241-R2 241-R3 241-R4 241-R5 241-R6
- - - - -
~
.. ~
241-G1 241-G2 241-G3 241-G4 241-G5 241-G6
- - - - -~. _~
_---''-_J'--___n_---''-_J'--___n_---'' - - - - -
* Diagram drawn with 2 LP vertical blank period
Example timing for 640 x 480 panel
112
~
__
~
SPC8110FoA
•
Color Passive STN LCD Panel Interface
8-bit Single Color Panel
LP: 480 PULSES
YD
I"
----------~~~------------
LP : 0/2 PULSES
(SELECTABLE)'
-------~-I..------_~~I~
LP
WF
UD[3:0j. LD[3:0j
LINE 1
LINE 2
LINE 3
LINE 479
LINE 4
LINE 480
LINE 1
LINE 2
LP
WF
XSCLU: 640 x 3/16
XSCLU
CLOCK::~I~D_S§ .. ~
----.
XSCL: 640 x 3/16 CLOCK PERIODS
XSCL
-----
- - - - ..
UD3
UD2
UD1
UDO
LD3
LD2
LD1
LDO - - - - -
.. ~
1-R12
-----~ __ ~
1--G12
1-812
-----~._~
1-R13
1-G13
-----~._~
1-B8
1-813
1-R14
-----~ .. ~
1-R9
1-89
1-814
1-814
-----~ •. ~
1-B9
l-Al0
1-R15
1--G15
-----~ .. ~
1-G5
1-81018101815
1R16
-----~ .. ~
1-A6
l-Rll
1-816
-----~ __ ~
1-R1
1-(31
1-81
1-G2
1-<36
1-B6
1-811
l-R2
1-A?
1-87
1-82
1-87
1-RS
l-A3
1-G3
1-88
1-83
1-R4
1-G4
1-84
1 RS
1-85
1-811
1-G16
• Diagram drawn with 2 LP vertical blank period
Example timing for 640 x 480 panel
113
I
SPC8110FoA
•
Color Passive STN LCD Panel Interface
8-bit Dual Color Panel (One Shift Clock)
LP: 240 PULSES
YD
----------~~~------------
LP : 0/2 PULSES
(SELECTABLE)*
_______~-I-~------~~I~
LP
WF
UD[3:0j, LD[3:0j
LINE 11241
INE239f479 LlNE240/480
LINE 21242
LINE 1/241
LP _ _ _---'
WF ______---' _ _ _ _ _ _ _ _ _ _ __
XSCL
UD3 - - - UD2 - - - UD1
UDO - - - LD3 - - - -
LD2 - - - LD1
LDO----
1-R1
1-G2
1-83
1-A5
1-G6
1-87
-----~."~
1-G1
1-82
1-A4
1......(35
1-86
1-AS
-----~ •• ~
1-81
i-R3
1-G4
1-85
1-R?
1-G8
-----~ __ ~
1-R2
1-83
1-84
1-RS
1-87
1-B8
-----~ __ ~
41-06
41-87
-
-
-~ __ ~
_ _P"C'--"-J"'-"-'-'''''''--'---''-Jc,,-,--='=='''-C--'.C.CJ'- - - -
-~ __ ~
241-R1 241-G2 241-83 241-R5
-
41-G8
-
-
-
-
-
~ __ ~
41-G7 241-88
-
-
-
-
-
~_. ~
241-81 241-R3 241-G4 241-85 241-R7
241-R2 241-G3 241-84 241-R6
-
* Diagram drawn with 2 LP vertical blank period
Example timing for 640 x 480 panel
114
SPC8110FoA
•
Color Passive STN LCD Panel Interface
8-bit Dual Color Panel (Two Shift Clocks)
LP: 240 PULSES
YD
________ I"
~r--lL
___________
LP : 0/2 PULSES
(SELECTABLE)*
-------~-I-.. ------~~I~
LP
WF
UD[3:0], LD[3:0]
LINE 1/241
INE 2391479 LINE 240/480
LINE 21242
LINE 1/241
LP
WF
XSCLU: 640 x 3/8 CLOCK PERIODS
XSCLU
------
XSCL
------
L.---+___ ~
-----~ __ --------'I
UD3
UD2
UDt
UDO
LD3
LD2
LDt
LDO - - - -
__
1-R1
1--G2
1-B3
1-RS
1--G6
1-87
-
1-G1
1-82
1-R4
1-G5
1-86
1-RS
- - - -
J'---'----"-'-J'--'--'-'-'CJL-'---='--'\---'--'~L'_____"_,'_'___=_J,1-R2
1-G3
1-84
1-R6
1--<37
241-R1 241-G2 241-83 241-R5
1-B8
41-G6 241-87
-
-
-
-
~_.~
-~ .. ~
-
-~ __ ~
- - - -
-~ .. ~
-
-~ •• ~
-
-
-
-
-
241-G1 241-82 241-R4 241-G5 241-86
41-RB
- - - - -~ __ ~
241-81 241-R3 241-G4 241-85 241-R7
41-G8
-
-
-
-
-~ •• ~
41 G7 241 68
-
-
-
-
-~._~
241 R2 241 G3 241 84 241 R6
* Diagram drawn with 2 LP vertical blank period
Example timing for 640 x 480 panel
115
I
SPC8110FoA
•
Color Passive 5TN LCD Panel Interface
16-bit Single Color Panel
YD
LP : 0/2 PULSES
(SELECTABLE),
LP : 480 PULSES
I'"
_ _ _ _ _ _ _ _ _ _~~L__ _ _ _ _ _ _ _ _ __
·1'"
·1
--------------~~
LP
WF
LINE 1
UD[7:0], LD[7:0]
LINE 2
LINE 3
LINE 479
- - - _ ...
UD7
UD6
UD5
UD4
1 B1
1 A7
1 G12
1 G2
1 B7
1 R13
1-R3
1-GB
1-813
1 B3
1 A9
1 G14
1-RS
1-G10
1 B15
1-85
1-Rff
1-G16
1-G1
1-B6
1-R12
1-R2
1-G7
1-812
1 B2
1-RS
1-G13
UD3
UD2
UD1
UDO
LD7
LD6
LD5
LINE 1
LINE 2
-----------~
LP
WF
XSCL
LINE 480
LD4
LD3
1 B4
f Rl0
1-G15
1-G5
1 B10
1 R16
1 R6
1 G11
1 816
LD2
LD1
LDO
• Diagram drawn with 2 LP vertical blank period
Example timing for640 x 480 panel
116
SPC8110FoA
•
Color Passive STN LCD Panel Interface
16-bit Dual Color Panel
LP: 240 PULSES
YD
LP : 0/2 PULSES
(SELECTABLE)'
_______~-I~------~_I~
LP
WF
UD[7:0], LD[7:0]
LINE 11241
LP _ _ _ _
UNE2I242
LlNE3/243
LlNE4I244
LlNE239I479 LlNE24OI480
LINE 11241
lINE2I242
I
n ...____________
WF _ _ _ _ _ L
_ _ _ _ _ _ _ _ _ _ __
~I
XSCL
UD7, LD7 - - - UD6, LD6 - - - UD5,LD5 - - UD4,LD4 - - UD3,LD3 - - UD2,LD2 - - UD1, LD1
UDO, LDO - - - -
__.J~~:::.~~~~=::::;==~=~=~ -----~_.~
_ _-"-""'''-''-'''''''-.lL_-''_ _IL_.J\_--1' - - - - -
~._~
_ _-"-""'''-'lMldli..IL_-''_ _IL_.J\_....J1 - - - - -
~ __ ~
--~~~~::~=~==~=~=~ ----- ~.-~
_ _-"-!lli
I
I
'">-is
>
8
I~
VRAM Interface
I
!5
S!
S!
~ I~
LCD
1
PINOUT
-~
~ Iwl~
~~~~~~~~~~>~~~~~~~~
xo
....
~~~~~~~~~~~~g§~~~~
xx
>
>
lAcv + 245 ................ Memory control/movement control commands.
= 4tc + tcc + 30 .............................................. All other commands.
129
Remark
CL
= 100 pF
+ 1TTL
SED1330
o
System Bus REAOIWRITE Timing II (6800)
..
E
leYC6
~
¥
:x
RIW
+-tAW6J
~K,
--tEW-
tAH6
:x
AO,CS
~
~
)(
~tDS6--
}
7r
00-07
-'Ie-
(WRITE)
+tACC6 ....
-,f-
I'<;:
(READ)
-'Ie-
IL
Parameter
AO,CS,RIW
DO to D7
E
tOH6
00-07
Signal
tDH6
Symbol
Rating
Min
System cycle time
tCYC6"1
*2
Address setup time
tAW6
30
Address hold time
tAH6
10
Data setup time
tDS6
120
Data hold time
tDH6
10
Max
-
Unit
ns
ns
ns
-
ns
ns
Output disable time
tOH6
10
50
ns
Access time
tACC6
-
120
ns
-
ns
Enable pulse width
tEW
220
*1. tCYC6 means a cycle of (CS.E) not E alone.
*2. tCYC6 = 2" + tEw + tCEA + 75 > tACV + 245 .............. Memory control/movement control commands.
= 4tc + tEW + 30 ............................................ All other commands.
130
Remark
CL=100pF
+ 1 TTL
SED1330
o
Display Memory READ Timing
EXT0
+-----
ICE
------i~~1
--
lw - -
veE
ICYR - - - - - H - - I
I'-~H------
r-------
VAO-VA15
VRIW
--ICEA_~
lACY
~
1----
1.....
--------
VDO-VD7
~-------
Signal
EXT¢O
--
VCE
VAO to VA15
-
VRIW
VDO to VD7
Parameter
Symbol
Rating
Min
Max
Unit
ns
2tc-40
-
tCYR
*1
-
ns
VCE address setup time (fall)
tASC
tc-45
-
ns
VCE address hold time (fall)
tAHC
2tc-40
-
ns
VCE read cycle setup time (fall
tRCS
tc-45
-
ns
VCE read cycle hold time (fall)
tRCH
tc/2 -35
-
ns
Address access time
lAcv
*2
ns
VCE access time
tCEA
-
*3
ns
Output data hold time
tOH2
0
ns
VCE data off time
tCE3
0
-
Clock cycle
tc
100
VCE high-level pulse width
tw
tc-40
VCE low-level pulse width
tCE
Read cycle time
*1. ICYA = 31C
'2. IACV = 31C -120
'3. ICEA = 2tC -120
131
Remark
ns
ns
ns
CL = 100 pF
+ 1TTL
I
SED1330
o
Display Memory WRITE Timing
EXTlj>O
•
VeE
tASC -
..
tCA
tAHC
VAO-VA15
tCYW
tAS
twsc
tWHC
VRIW
tOHC
VDO-VD7
Signal
EXT
cfIJ
VCE
VAO to VA15
VRtW
VOO to VO?
Parameter
Symbol
Rating
Min
Max
Unit
Clock cycle
tc
100
-
ns
VCE HIGH-level pulse width
tw
tc-40
ns
VCE LOW-level pulse width
tCE
2tc-40
-
Write cycle time
tCYW
3tc
-
ns
VCE address hold time (fall)
lAHC
2tc-40
ns
VCE address setup time (fall)
lAsc
tc-55
VCE address hold time (rise)
tCA
5
VRIW address setup time (fall)
lAs
0
VRIW address hold time (rise)
lAH2
15
VCE write setup time (fall)
twsc
tc-55
VCE write hold time (fall)
twHC
2tc-40
VCE data input setup time (fall)
tosc
twsc -10
VCE data input hold time (fall)
tOHC
2tc- 30
-
VRIW data hold time (rise)
tOH2
10'
50
ns
• Lines VDO to VD7 are latched.
132
Remark
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL
= 100 pF
+ HTL
SED1330
o
LCD Control Timing
ROW NO
LP
L -____________
1_fra_m_e~p_e_riO_d_______________
YO
.'
r_::L_
L
WF
YSCL
---!-
WF ----------', ,
YSCL
1 line period
--------,U~.~==============~~==============~.I
UROW64
ROW1
LP
XSCL
XOO-X03
XECL
XSCL
XOO-X03
LP
XECL
WF(8)
YO
YSCL
133
ROW2
I
SED1330
Signal
EXT IjIJ
Parameter
XOO to X03
LP
XECL
YSCL
YO
Max
Unit
tc
100
-
ns
Rising time
tr
35
ns
tf
-
35
ns
Shift clock cycle time
tcx
4tc
-
ns
XSCL clock pulse width
twx
tCX2 - 80
-
ns
X-data hold time
tOH
tCX2 -100
ns
X-data setup time
tos
tCX2 -100
-
Latch data setup time
tLS
tCX2 -100
-
ns
LP signal pulse width
tWL
tCX4- 80
ns
XECL setup time
tl1
tCX3 -100
-
XECL data hold time
tL2
tc-30
tS1
tc-30
-
ns
Enable setup time
Enable delay time
tS1
tc-30
ns
tWXE
tCX3- 80
-
Time allowance of WF delay
tOF
-
100
ns
LP delay time against YSCL
tLD
tCX4 -100
ns
YSCL clock pulse width
tWY
tCX4- 80
-
V-data hold time
tOHY
tCX6 -100
-
ns
XECL clock pulse width
WF
Rating
Min
Clock cycle
Falling time
XSCL
Symbol
134
Remark
ns
ns
ns
ns
ns
Voo = 5.0V ± 10%
CL = 150F
SED1330
o
Oscillator Timing
Voo
CLO
I
YDIS
Power ON
r
EXT 00
Signal
CLO
EXT qIJ
Parameter
Symbol
Rating
Min
Max
Unit
Time to stable CLO output
after power-ON
tosp
-
3
ms
Time to stable CLO after
sleep OFF
toss
-
1
ms
External clock rise time
tRCl
ns
tFCl
-
15
External clock fall time
15
ns
External clock high-pulse width
tWH
*1
*2
ns
External clock low-pulse width
tWl
*1
*2
ns
External clock cycle
tCl
100
-
ns
'1. (Ic - IRCL - IFCL) x 475/1000 < IWH, IWL
'2. (Ic - IRCL - IFCL) x 525/1000> !wH, IWL
135
Remark
--
RES= H
20 pF
SED1330
•
EXAMPLE OF APPLICATION
rlDh8.0MHZ
XG
r - - - CS7
Y7
XO
G1 ~ Y6
AO
At
to
A7
:;J
"::;
AO
f-"
r-v
r----lORa
Chip
Selector
r--
~
DO
to
07
AD
~
-
RES
XOO
to
X03
-'-'
00
W(/)~
~x
~
I~c-~'
-+.
i-u
VL2
i-'1-f"-VL3
I Cll- f"-VL4
VL5
_\L--*AOtoA12 WE
- - -
6E~
J
SRM2064 CS1.,
(RAM7) CS2
6E~
DO to 07
77T
0
VOO
I
J
SRM2064 CS1
(RAM1) CS2" -
DO to 07
77T
0
3l
,IAOto
,
VAt2
A11 - -,
2732
'(EXT.CG)
LOQ.tf-
DE
,,
-~
to
V07
External
CGROM
CGRAM
I
1
f
f
t
Q
u
g!
1/0 Register
VRAM Inteliace
1
;
1
1
Cursor
Address
Controller
;
I
Display
Address
Controller
t
hi
Refresh
Address
Counter
I
t
~
~~
d
~
I
CG ROM
r
l:W' ,
Layered
Display
Controller
t
t
~
y
L
MPU Interface
r~~ rl~ r!~I","
rl~ lb8
Oscillator
Circuit
~~Dt-1~
Q
•
~i
frl
x
LCD Controller
;
Dot Counter
!l:
1
+
I
~
U)
Ci
':;-
~ I~ I~ I~
I
LCD
PINOUT
~~
1U)IOlwl~o~ ~~~m~
~WW~IOOUWOCO~CC~««<
xooool~oczzoc»»»»»>
VD3
)ill
cs
AO
Voo
VAiO
VAll
DO
01
VA12
VA13
02
03
04
05
06
VD2
VA8
VAg
VOl
VDO
VA15
VA14
VA13
VA12
NC
VA1l
VA14
VA15
VA10
VAg
VA8
VA7
VA6
VDO
VOl
~~TnTn~TITnT~Tn~~nT~r-~VD2
NC--~~nnnnnnnTmTmT~
140
XD3
07
06
05
D4
03
02
01
DO
Voo
AD
CS
XD
XG
SELl
SED1335
•
PIN DESCRIPTION
PinNo.
Pin Name
1/0
Functions
SED1335FoA
SED1335FoB
XG
54
17
I
Oscillator terminal
XD
55
18
0
Oscillator terminal
Voo
58
21
+5V
Power supply
36
GND(OV)
Power supply
Vss
13
SEL1,2
53 0 52
16 0 15
I
DO to D7
59 to 60, 1 to 6
22 to 29
1/0
AO
57
20
I
50
13
I
-
RD
WR
51
14
I
CS
56
19
I
MPU interface format selection
Data bus
I
Data type selection
80 series Read strobe signal
68 series "E" clock
80 series Write strobe signal
68 series R/W signal
Chip select
RES
47
10
I
Reset
VA15to VAO
27 ° 28,30 to 43
1 to 6, 50 to 59
0
VRAM address bus
VD7to VDO
19 to 26
42 to 49
I/O
VRAM data bus
VWR
44
7
VRAM write signal
VRD
46
9
VCE
45
8
XD3to XDO
7 to 10
30 to 33
XSCL
12
35
XECL
11
34
LP
14
37
WF
15
38
YSCL
18
41
YD
17
40
0
0
0
0
0
0
0
0
0
0
YDIS
16
39
0
VRAM read signal
VRAM chip enable
Dot data output bus to X driver
Dot data shift clock for X driver
Chip enable shift clock for X driver
Dot data latch pulse
Frame signal
Scan data shift clock for Y driver
Scan data output
Power down signal when display
is OFF
NC: No Connection
•
ELECTRICAL CHARACTERISTICS
•
Absolute Maximum Ratings
(Vss
=OV)
Symbol
Ratings
Unit
Supply voltage
Voo
-0.3 to 7.0
V
Input voltage
VIN
-0.3 to Voo+0.3
V
Power dissipation
Po
300
mW
Parameter
Operating temperature
Top,
-20 to 75
°c
Storage temperature
Tstg
-60 to 150
°C
Soldering temperature and time
Tsol
260°C, 10s (at lead)
-
141
SED1335
•
DC Electrical Characteristics (1)
(Vss = OV, Voo = 4.5 to 5.5V, Ta = -20 to 75°C)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Operating voltage
Voo
4.5
5.0
5.5
V
Register data retention voltag
VOH
2.0
-
6.0
V
High level input voltage
T Low level input voltage
T
L High level output voltage
Low level output voltage
VIHT
p.5xVoO
V
Vss
-
Voo
VILT
O.2xVoo
V
-
-
V
Vss+O.4
V
High level input voltage
C
M Low level input voltage
0 High level output voltage
S
Low level output voltage
sc
Positive trigger threshold volta~
H
VOHT
IOH=-5.0mA
2.4
VOLT
IOL= 5.0mA
-
VIHC
p.8xVoO
-
Voo
V
VILC
Vss
-
O.2xVoo
V
-
V
VOHC
IOH=-2.0mA
f/oo--O.4
VOLC
IOL= 2.0mA
-
Vss+O.4
V
VT+
0.5Voo 0.7Voo 0.8Voo
V
VT-
0.2Voo 0.3Voo 0.5Voo
V
M
I
T
T
Negative trigger threshold voltage
Input leakage current
III
Output leakage current
ILo
Average operating current
lopr
Standby current
IQ
VIN =VooNss
fosc = 1OM Hz, No-load
256 x 200 dot
Sleep
XG, CS, RD = Voo
Voo
001007,
AO,BS, RO,
WR, VOOlo
V07, VAOlo
VAtS, VCE,
VRO, VWR
SELl, SEL2,
YO, XOOlo
X03,XSCL,
YOIS, LP,
WF,CLO,
XECL, YSCL
RES
-
0.05
2.0
0.10
5.0
~
!LA
-
11
15
mA
Voo
-
0.05
20
.~
Voo
Oscillation frequency
fosc
AT X'tal
1.0
MHz
feL
Duty 47.5%
1.0
-
10.0
External clock frequency
10.0
MHz
Feed back resistance
RI
0.5
1.0
3.0
Mil
142
Terminal
XG,XD
SED1335
•
DC Electrical Characteristics (2)
Parameter
Symbol
(Vss = OV, Voo = 2.7 to 4.5V, Ta = -20 to 75°C)
Min
Typ
Max
Unit
Operating voltage
Voo
2.7
3.5
4.5
V
Register data retention voltag
VOH
2.0
6.0
V
High level input voltage
T Low level input voltage
T
L High level output voltage
Low level output voltage
VIHT
0.8xVoo
VILT
Vss
-
High level input voltage
C
M Low level input voltage
0 High level output voltage
S
Low level output voltage
8
e
Positive trigger threshold voitag
H
Condition
VOHT
IOH=-3.0mA
Voo-OA
VOLT
IOL= 3.0mA
-
VIHC
0.8xVoo
VILC
VSS
VOHC
IOH =-1.0mA
Voo-OA
VOLC
IOL= 1.0mA
-
Voo
V
0.2xVoo
V
-
V
Vss+0.4
V
Voo
V
O.2xVoo
V
-
V
VT+
~ss+0.4
0.5Voo 0.7Voo 0.8Voo
VT-
0.2Voo 0.3Voo 0.5Voo
V
V
M
I
T
T
Negative trigger threshold voltagE
Input leakage current
ILl
Output leakage current
ILO
Average operating current
lopr
Standby current
10
VIN = VooNss
f08e = 6.1 MHz, No-load
256 x 200 dot
Sleep
XG, CS, RD = Voo
Oscillation frequency
f08e
ATX'tal
External clock frequency
fCL
Duty 47.5%
Feed back resistance
RI
-
1.0
1.0
0.7
143
V
Terminal
Voo
001007,
AO,CS, RO,
WR, VOOlo
V07, VAOlo
VAt5, VCE,
VRO,VWR
SELt, SEL2,
YO, XOOlo
X03,XSCL,
YOIS, LP,
WF,CLO,
XECL, YSCL
RES
0.05
2.0
j.tA
0.10
5.0
j.tA
7.0
mA
Voo
0.05
20
I1A
Voo
-
8.0
MHz
8.0
MHz
4.0
MO
3.5
{Vo0=3.5\f
XG,XD
I
SED1335
•
o
Timing Diagrams
SOSO-Family Interface Timing
AO,CS
WR,
Rl5
001007
(Wrile)
001007
(Read)
Ta =-20 to 75°C
Signal
Symbol
AO,CS
WR,RD
DO to D7
Parameter
Voo = 4.5 to 5.5V
max
min
Voo = 2.7 to 4.5V
min
max
Unit
tAH8
Address hold time
10
-
10
Address setup time
0
0
-
ns
tAW8
tCYC
System cycle time
See note
See note
-
ns
tee
Strobe pulsewidth
120
150
ns
tOS8
Data setup time
120
tOH8
Data hold time
5
-
5
-
tACC8
RD access time
-
50
-
80
ns
tOH8
Output disable time
10
50
10
55
ns
Note: For memory control and system control commands:
tCYCS =2tc + tcc + tCEA + 75 > lAcv + 245
For ali other commands:
tCYCS = 4tc + tcc + 30
144
120
Condition
ns
ns
ns
CL = 100
pF
SED1335
o
6800-Family Interface Timing
~
E
Jl'
I.
I
tCYC
----...1
..........-tAW6
RfW
~
AO,CS
)<
lEW
III
+I
I-+-----0010 07
1x
IDH6
tDS6 - - - - - - . .
---------<~-~-004------
(Read)
-tl
IAH6
'Ii:
(Wrile)
DO 10 07
.
tAce6-"
. . - toH6
Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH.
Ta
Voo = 4.5 to 5.5V
min
max
Signal
Symbol
AO,
CS,
tCYC6
System cycle time
See note
-
tAW6
Address setup time
tAH6
Address hold time
tOS6
Data setup time
0
0
100
tOH6
Data hold time
-
RJW
DO to 07
E
Parameter
tOH6
Output disable time
0
10
tACC6
Access time
-
85
Enable pulsewidth
120
-
tEW
50
Note: For memory control and system control commands:
tCYC6 = 2tC + tEW + tCEA + 75 > IACV + 245
For all other commands:
tCYC6 = 4tC + lEW + 30
145
Voo = 2.7 to 4.5V
max
min
See note
10
0
120
0
10
75
130
150
Unit
=-20 to 75°C
Condition
ns
ns
ns
ns
ns
ns
ns
ns
CL=
100 pF
I
SED1335
o
Display Memory Read Timing
EXTO
L=lw------. .
ICE
"1
veE
tCYA
~
VAOlo VA15
1
VRO
-
tAHC
r--
IRCS _ _ _ ICEA __
..
tAGV
'1\
I
R twH, twl
Condition
SED1335
o LCD Output Timing
The following characteristics are for a 1/64 duty cycle.
Row
62,63,64,1
2
3 , 4 ,
__________ --,-'_6_0-,--_61--,-_6_2--,,_63--,-,_64---',_ _ __
LP
---------: ...
-:
1 iramelime
n
YO
n
WF
WF
..
1 line lime
Row 64
Row 2
Row 1
n
LP
XOOIOX03 (14) (15)
J
n
--twx ~ _If
t
XSCL
(15) (16)
(15) (16) (1) (2) (3)
(1)
(16)
•
..
lex
los _ _ _ I O H
-+-- tLS ------.
.
K
)<
XOO10 X03
jlLD
twL
LP
WF(8)
-
_ _ IOHV_\
tDF
14I
YO
149
•
;r
V
(1)
I
SED1335
Ta = -20 to 7SoC
Signal
Symbol
Parameter
Voo = 4.S to S.SV
Voo = 2.7 to 4.SV
Unit
min
max
min
max
-
40
40
ns
4tc
ns
tr
Rise time
Fail time
-
30
tf
tcx
Shift clock cycle time
4tc
2tc-10S
0
-
30
ns
twx
XSCL clock pulsewidth
2tc-60
XDOto
X03
tOH
X data hold time
2tc-SO
tos
X data setup time
2tc-100
tLS
Latch data setup time
2tc-SO
LP
twL
LP pulsewidth
4tc-80
tLO
LP delay time from XSC
0
-
WF
tOF
Permitted WF delay
-
SO
-
SO
ns
YO
tOHY
2tc-20
-
2tc-20
-
ns
XSCL
Y data hold time
2tc - 60
2tc -SO
2tc-SO
4tc-120
Condition
ns
ns
ns
CL=
100pF
ns
ns
ns
Note: The SED1335F reads display memory data from the addressofthe top left corner olthe display screen, then scans horizontally
until it reaches the address forthe bottom right corner olthe display screen. Therefore, each line of X-driver data is sent starting
from the left side of the display line.
1S0
SED1335
•
EXAMPLE OF APPLICATION
~f,
10MHz
XG
AO
AO
-
-
A1
to --"
Chip
A7 ---v
-------. Selector
f--
CS
~
lORD
::J
0.
-
"
~
DO
DO
to
to
07
07
AD
Ali
iVA
~
RESET
~
RESET
,---
C;
w
"'
to
X03
dd
~
d
1----
- --- -
'"'~I"'~'JT1"'-"fl~:0'11"''='-_+'----I~
r-------~+_-++_W-':==~=~ ~H
~
I~
Q)
1---- .- --
~
~It-+. V1
1,,1
I:
~!
::je~:
" ,~I I-§-+ V4
-
--- -
§ r-v
'---
(V Driver)
- --- -
~~
+-------1--.j FR
~-----7,~YSCL
,-
I
RES
XOO
- - - - --
LCO
w
m
n
n
'1 ' - - - - - - . " , - - - - - - , . , - - - - - - . " , - - - - '
'2
'2
'2
H
FR
SED1600FJrtFR
~
EI
~x
0
~
aSc
~------*+~-H
"--1
SED1600F
g
EI
~x
' ,
0
M
0.80
rl
SED1600F
I-----~
IIE~ goo'"
tt
..JX
0 .... 0
I
V5
L__________________________
FA
L~~
(_X_O_riv_er_1_ _ _ _ _ _
_UN_'T_ _ _ _
~
[ Recommend X Driver: SED1742F, SED1600F
Recommend Y Driver: SED1743F, SED1610F, SED1631
151
SED1335
•
CHARACTER CODE TABLE (Built-in Character Generator)
Lower 4-bit (DO to 03) of Character Code (Hexadecimal)
4
7
0
3
5
6
8
9 A B C
E
F
..
..
..
·· ·· ·· .....
2
·· .. .......·· · ····....· ···..····· ·· ····· ····· ··...···· ·· .....·· ..· ..... .... ·····
.....· ..·· ·...· .....· ··...· ·.....
..· .....· ·......·· ·.......· .. .. ··· ..... ·· ·...·
....
·
·
....
-E 3 ··........· ·· ......·· .....
...·· ··.....
...· ··...·· ··...·· .....·· ..... ·..· . ····· ......... ····· .··..·
·....·· ·......··· ·........· ·.....
...·. ··.....·· ··....·· ·· · ·· ·· ··.... ·.... ·· ...· ···.....·..· ·· ·· ··..·· ···· ··· · ··· ···..·..···· ··
4 ··
...
· · .....·· ·..... ·· ·....· · . ...· ·.....
co
·
... ·.... ·....
..· ··...··. ·..... ·...· ·· · ·...·
x
....
....· ·......· ·...
·
·
·
·
·
·
·
·
·
·
··.· ·· ·····
.....
.... · ·· .·· ··..... · ·...· ·· · · · · · · · ··· ·· ·· .··· ··· ·.....
5 ·
·· .. ·..· · · ·· ·...· · ··...· ····..· ····· ·· ·· ·· ·..... ·... ..· ...· .....
u.....
. ... ··....· ·.... ·....··· ·.....
.... .....·· ·........· ··.. ..· ..·· ..·· ···..·· ··· ·...... · ·.. .. · ·...·
6 · ....· ·
·
-.....coco 7 .... ·........· ·........· ·........ ·.........· · ·... · ...· ·· · .·.. ·.......· ···..· ...·· ·...·· ··.....· · ·......·..·
··· ..··· ·· ··
·....· ·....·· ··· ·.......· ··.. ··....·· ··· ··· ·· · ··· ······· ·.......·· .....
·
·
.
u
·
·
..
·
· .....
·· · ·
· ....· ·
- A ... ··... · .. · .....
.....· ..· ..·· ·.....
..... .....
.....
...· ....· ·· · ·
·.. . .....
·· . .....
·
..
·......... ...· ··
·
·
....· ..·
·
·
·· .....
·· ··....· . ·.....· ..... ·.·....· ·· · ..... .....
..... .....
.....
--..... B ..... ··..· ·..·· · ·.....· ·. .....
·
·
··· ·· ·· ··
..
· ·..·· ··· ·· .....
·
·
·
·
·
·
·
·
·
·
·
·
·
·
.
· ..· ·· .....· ·· ...·· ···· ·... ..·
·. · ...·· · · · ··...·· .....
·
·
....
...
.....
.....
·
·
·
·
.· ·...·. .....· ·· ·· ·· .....· ··.. .....··
..... .....· ·.· .....
·
..
..... C
·
·
·
·
·
..
····· · · · ··· ·· ·· ··.... ..·· ··· · ·· ·· ·····
...... ·· ·· .....
·· ··· · ··... .....
... · · · · ·..... ·...... .. · ·· .·......
..... ·.....
·
I
.....
·
·
.....
.....
0 ....
·
·
·
·
·
.
.... ··.....· ····· ·... · · .....· .....· ·· · ·· ·· ··..·· ··..··· ·....... ·· ...·· ·
·
· · ·
·
· ··
0
1
2
· ·. ·.....
.....
"
~
0e:;
Q)
"0
Q)
~
Q)
"0
0
Q)
u
..c
0
~
0
0
"
"
-.:t
0
" " ""
:0
~
Q)
..c
OJ
0
1
IIIIIIIIIIIIIIII
152
SED1336
CMOS GRAPHIC LCDfTV CONTROLLER
• For Medium-Scale LCD
• Output to LCD-Screen
• Virtual Screen Display RAM
• Enhanced Control Function
• Simultaneous LCD & TV Display
•
DESCRIPTION
The SED1336 is a CMOS low-power dot matrix liquid crystal graphic display controller with built-in TV
support. The built-in TV support IC is capable of displaying characters and graphic images simultaneously
on TV monitors and flat panels.
The SED1336 has a built-in TV control circuit that generates either NTSC or PAL system synchronous
signals, memory. The device stores the display data in external SRAM that is sent by an 8-bit microcomputer,
and generates all the control signals required by the LCD drivers.
The controller incorporates an internal character generator ROM which supports user-defined characters. An
external CG ROM can also be supported to provide additional characters.
The SED1336 can be interfaced to high-speed microprocessors such as the Intel80xx family or the Motorola
68xx family. The controller supports a set of commands that allow the user to create a layered display of
characters and graphics.
•
FEATURES
• Low-power CMOS fabrication
• Selectable display synthesis
• Compatible with both Intel 80XX and Motorola
68XX high-speed MPU
• Programmable cursor movement
• Multimode display:
2 layers of overlapping character and graphic
• Display duty:
LCD ............... 112 to 1/256 can be selected
3 layers of overlapping graphic
TV ...................................... 256 x 200 dots
•
• Internal and external character generator ROM
• Supports 64K bytes of memory
• Single power supply ..................... 3.0V to 5.5V
• Simultaneous LCD and TV operation
• Package ................... Plastic QFP6-60 pin (FOA)
SYSTEM BLOCK DIAGRAM
-II
DATA
CPU
SED1336
CONTROL
~i
t
I
SRAM
153
I
MONO LCD
TV
II
I
I
SED1336
•
I
BLOCK DIAGRAM:'
Vid~~~~
I
~
External
CGROM
t l
!:;
>
Ig
c
g2
8
I
t
I
,I
Display
Address
Controller
t
hi
Refresh
Address
Counter
I
I
,
110 Register
Dot Counter
t
t
;
I
til
II CO~~lIer II
•
~
I
r
PIN ASSIGNMENT DIAGRAM
X03
07
OS
OS
D4
03
02
01
DO
Vee
AO
CS
XO
XG
SELl
154
";:
~
-'
u
til
x
I
8x
S
8x
LCD Controller
i
I
1:4' , I
Layered
Display
Controller
OSC
~~D~~
g
NC
~
>-
L
i
r~~ rl~ rl~fa: I~« IB8
V03
V02
VOl
VOO
VAIS
VAI4
VAI3
VAI2
VAIl
VAl 0
VA9
VA8
VA7
VAS
CG ROM
LCD WITH
SEDl180/SEDl190
t
MPU Interface
•
f;1
>
I
Cursor
Address
Controller
II
TV
II
S
VRAM Interface
I
I
t
'"
~
S
__ 1
SED1336
•
PIN DESCRIPTION
Name
Number
Type
6 to 1
59 to 50
Output
VRAM address bus
VWR
7
Output
VRAM write signal
VCE
8
Output
Memory control signal
VRAM read signal
VAOto VA5
VA6 to VA15
VRD
9
Output
RES
10
Input
NC
Reset
-
11,60
No connection
CLO
12
Output
RD
13
Input
8080-family: Read signal
6800-family: Enable clock (E)
WR
14
Input
8080-family: Write signal
6800-family: RIW signal
NT/PL
15
Input
NTSC or PAL TV mode select
-
Clock output
SEL1
16
Input
8080- or 6800-family interface select
OSC1
17
Input
Oscillator connection
OSC2
18
Output
Oscillator connection
CS
19
Input
AO
20
Input
VDD
21
Supply
DO to D7
22 to 29
InpuVoutput
XDOto XD3
30 to 33
Output
Data to LCD X-driver
VSD
34
Output
Video data
Data shift clock
I
Chip select
Data type select
3.0 to 5.5V supply
Data bus
XSCL
35
Output
VSS
36
Supply
Ground
LP
37
Output
Latch pulse
WF
38
Output
Frame signal
YDIS
39
Output
Power-down signal when display is blanked
YD
40
Output
Scan start pulse
41
Output
TV sync signal
42 to 49
InpuVoutput
SNC
VDOto VD7
•
•
Description
VRAM data bus
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Rating
Unit
Supply voltage range
VDD
-0.3 to 7.0
V
Input voltage range
VIN
-0.3 to VDD + 0.3
V
Power dissipation
PD
300
Parameter
Operating temperature range
Topr
-20 to 75
mW
DC
Storage temperature range
Tstg
-65 to 150
DC
Tsolder
260
DC
Soldering temperature (10 seconds). See note 1.
1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique
that does not heatstress the package.
2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take
appropriate care with the power supply and the layout of the supply lines.
3. All supply voltages are referenced to Vss = av.
155
SED1336
•
DC Electrical Characteristics
Voo = 4.5 to 5.5V, Vss = OV, Ta = -20 to 75°C
Min
Typ
Max
Supply voltage
Voo
4.5
5.0
5.5
V
Register data retention voltage
VHO
2.0
-
6.0
V
0.05
2.0
/-lA
0.10
5.0
11
15
/-lA
mA
0.05
20.0
/-lA
Parameter
Symbol
Condition
Input leakage current
III
VI = Voo. See note 6.
Output leakage current
IlO
VI = Vss. See note 6.
Operating supply current
lopr
See note 4.
Quiescent supply current
10
Sleep mode,
VOSC1 = Vcs = VRO = Voo
-
Unit
-
10.0
MHz
1.0
10.0
MHz
RI
Measured at crystal,
47.5% duty cycle.
See note 7.
0.5
1.0
3.0
MQ
HIGH-level input voltage
VIHT
See note 1.
0.8Voo
-
Voo
V
LOW-level input voltage
VllT
See note 1.
Vss
0.2Voo
V
HIGH-level output voltage
VOHT
IOH = -5.0 mAo
See note 1.
2.4
LOW-level output voltage
VOLT
IOl = 5.0 mA. See note 1.
-
HIGH-level input voltage
VIHC
See note 2.
0.8Voo
LOW-level input voltage
Vile
See note 2.
Vss
HIGH-level output voltage
VOHC
IOH = -2.0 mA. See note 2. Voo - 0.4
LOW-level output voltage
VOlC
IOH = 1.6 mAo See note 2.
VOlN
IOl = 6.0 mA. See note 5.
Rising-edge threshold voltage
VT+
See note 3.
0.5Voo
0.7Voo
0.8Voo
V
Falling-edge threshold voltage
VT-
See note 3.
0.2Voo
0.3Voo
0.5Voo
V
Oscillator frequency
fosc
Extemal clock frequency
fCl
Oscillator feedback resistance
1.0
TTL
-
Vss + 0.4
V
V
CMOS
-
-
-
-
Vss + 0.4
V
Voo
V
0.2Voo
V
-
V
Vss + 0.4
V
Open-drain
LOW-level output voltage
Schmitt-trigger
Notes:
5. SNC and VSD are n-channel, open-drain outputs. The
voltage on the outputs should not exceed VDD as internal
diodes connect the pins to VDD (SED1336F only).
1. DO to D7, AO, CS, RD, WR, VDO to VD7, VAO to VA 15,
VRD, VWR and VCE are TTL-level inputs.
2. SEL 1 and NTlPL are CMOS-level inputs. YD, XDO to
XD3, XSCL, LP, WF, YDIS and CLO are CMOS-level
outputs.
6. VDO to VD7 and DO to D7 have internal feedback circuits
so that if the inputs become high-impedance, the input
state immediately prior to that is held. Because of the
feedback circuit, input current flow occurs when the
inputs are in an intermediate state.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 Ils. Note that pulses of more than a
few seconds will cause DC voltages to be applied to the
LCD panel.
7. Because the oscillator circuit input bias current is in the
order of IlA, design the printed circuit board so as to
reduce leakage currents.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 x 200 pixel display. The operating supply current can be reduced by approximately 1 mA
by setting both CLO and the display OFF.
156
SED1336
VDD
Parameter
= 3.0 to 4.5V, Vss = OV, T a =-20 to 75°C
Symbol
Condition
Min
Typ
Max
Supply voltage
VDD
See note 8.
3.0
3.5
4.5
V
Register data retention voltage
VHO
2.0
-
6.0
V
Input leakage current
III
Output leakage current
Ilo
Operating supply current
Quiescent supply current
lopr
IQ
=VDD. See note 6.
=Vss. See note 6.
VDD = 3.5V. See note 4.
VI
VI
See note 4.
VOSC1
Sleep mode,
=VCs = VRD
=VDD
Unit
-
0.05
2.0
~A
0.10
5.0
~A
3.5
-
-
7.0
-
0.05
rnA
20.0
~A
8.0
MHz
8.0
MHz
3.0
MQ
RI
Measured at crystal,
47.5% duty cycle.
See note 7.
0.7
-
HIGH-level input voltage
VIHT
See note 1.
0.8VDD
-
VDD
V
LOW-level input voltage
VllT
See note 1.
Vss
-
0.2VDD
V
HIGH-level output voltage
VOHT
IOH =-3.0 rnA.
See note 1.
2.4
-
LOW-level output voltage
VOLT
-
-
Vss + 0.4
V
-
VDD
V
0.2VDD
V
-
Vss + 0.4
V
-
Vss + 0.4
V
Oscillator frequency
fosc
External clock frequency
fCl
Oscillator feedback resistance
1.0
1.0
TTL
IOl
= 3.0 rnA. See note 1.
-
V
CMOS
HIGH-level input voltage
VIHC
See note 2.
0.8VDD
LOW-level input voltage
VllC
See note 2.
Vss
HIGH-level output voltage
VOHC
LOW-level output voltage
VOlC
=-2.0 rnA. See note 2. VDD IOH = 1.6 rnA. See note 2.
VOlN
IOl = 6.0 rnA. See note 5.
Rising-edge threshold voltage
VT+
See note 3.
0.5VDD
0.7VDD
0.8VDD
V
Falling edge threshold voltage
VT-
See note 3.
0.2VDD
0.3VDD
0.5VDD
V
IOH
0.4
-
V
Open-drain
LOW-level output VOltage
-
Schmitt-trigger
Notes:
1. DO to D7, AO, CS, RD, WR, VDO to VD7, VAO to VA15,
VRD, VWR and VCE are TTL-level inputs.
5. SNC and VSD are n-channel, open-drain outputs. The
voltage on the outputs should not exceed VDD as internal
diodes connect the pins to VDD.
2. SEL 1 and NT/PL are CMOS-level inputs. YD, XDO to
XD3, XSCL, LP, WF, YDIS and CLO are CMOS-level
outputs.
6. VDO to VD7 and DO to D7 have internal feedback circuits
so that if the inputs become high-impedance, the input
state immediately prior to that is held. Because of the
feedback circuit, input current flow occurs when the
inputs are in an intermediate state.
3. RES is a Schmitt-trigger input. The pulsewidth on RES
must be at least 200 !ls. Note that pulses of more than a
few seconds will cause DC voltages to be applied to the
LCD panel.
7. Because the oscillator circuit input bias current is in the
order of !lA, design the printed circuit board so as to
reduce leakage currents.
4. fOSC = 10 MHz, no load (no display memory), internal
character generator, 256 x 200 pixel display. The operating supply current can be reduced by approximately 1 mA
by setting both CLO and the display OFF.
8. VDD = 2.7 to 4.5V (SED1335F)
157
I
SED1336
•
a
Timing Diagrams
SOSO-Family Interface Timing
AO,CS
.
--
IAWB~
WR,RD
tCYC
"'-
Icc
~I
IDSB--=:I 'DHBI_
X
(Write)
JK
l-tAccB
DOlo D7
(Read)
~
,It
1_ _ _
DO to D7
tAH8
LIoHB
--1,----1--Ta =-20 to 75°C
Signal
Symbol
AO, CS
WR,RD
DO to D7
Parameter
VDD
=4.5 to 5.5V
min
max
tAHa
Address hold time
10
tAwa
Address setup time
0
tCYC
System cycle time
See note
tec
Strobe pulsewidth
120
tDsa
Data setup time
120
-
VDD
= 3.0 to 4.5V
min
10
0
See note
max
Unit
-
ns
ns
ns
ns
tDHa
Data hold time
5
-
5
-
tAcca
RD access time
-
50
-
70
ns
tOHa
Output disable time
10
50
10
50
ns
Note: For memory control and system control commands:
tCYCS = 2tc + tcc + tCEA + 75 > tACV + 245
For ali other commands:
tCYCS = 4tc + tcc + 30
158
140
120
Condition
ns
ns
CL = 100
pF
SED1336
o
6800-Family Interface Timing
E
¥
I.
RIW
~
I
tCYC
.
----..1
tAW6
.
+1
tEW
)<
>
AO,CS
t AH6
-il
tDH6
I~ tDS6------"
DO to D7
-*
(Write)
----1-~I-- tACC6
DO to D7
(Read)
.1__
__I --
__
tOH6
Note: tCYCS indicates the interval during which CS is LOW and E is HIGH.
Ta =-20 to 75°C
VDD = 4.5 to 5.5V
Symbol
AO,
CS,
tCYC6
System cycle time
See note
tAW6
Address setup time
0
lAH6
Address hold time
0
tDS6
Data setup time
100
tDH6
Data hold time
0
-
tOH6
Output disable time
10
50
lACC6
Access time
-
85
Enable pulsewidth
120
-
140
RtW
DO to D7
E
tEW
Parameter
VDD = 3.0 to 4.5V
Signal
min
max
Note: For memory control and system control commands:
tCYC6 = 2tc + tEW + tCEA + 75 > tACV + 245
For all other commands:
tCYC6 = 4tC + tEW + 30
159
min
max
Unit
-
ns
10
0
-
ns
120
-
ns
0
-
ns
10
70
ns
-
120
ns
-
ns
See note
Condition
ns
CL=
100 pF
I
SED1336
o
Display Memory Read Timing
EXTO
I - tw ------.
.
tCE
'1
VCE
tCYR
I.
~
)<.
VAOto VA15
I--tASC
1.
VRD
--t==:1
tAHC
I--
-tRC8---" I+-tCEAtAcv
teE3
,
tRcH
1
f-+
~
tOH2
VDOto VD?
(SED1335F)
Ta =-20 to 75°C
VDD = 3.0 to 4.5V
Symbol
EXTtjJO
tc
Clock period
100
-
125
-
ns
tw
VCE HIGH-level
pulsewidth
tc-50
-
tc-50
-
ns
tCE
VCE LOW-level
pulsewidth
2tc - 30
-
2tc - 30
-
ns
tCYR
Read cycle time
3tc
-
3tc
-
ns
tASC
Address setup time to
falling edge of VCE
tc-70
-
tc-100
-
ns
lAHC
Address hold time froIT
2tc - 30
falling edge of VCE
-
2tc -40
-
ns
tRCS
Read cycle setup time
tc-45
to falling edge of VCE
-
tc-55
-
ns
tRCH
Read cycle hold time
from rising edge of VC
-
0.5tc
-
ns
tACV
Address access time
tCEA
VCE access time
-
tOH2
Output data hold time
0
tCE3
VCE to data off time
0
-
VCE
VAO to
VA15
VRO
VOO to
V07
Parameter
VDD = 4.5 to 5.5V
Signal
min
max
0.5tc
3tc -100
2tc - 80
-
160
min
0
0
max
Unit
3tc-110
ns
2tc - 85
ns
-
ns
ns
Condition
CL =100 pF
SED1336
o
Display Memory Write Timing
EXT$O
rVCE
~tASC
-I"1} ---
tCE
tw -----.
.
A
tAHC
tCYW
Z[;
)
VAOto VA15
--
twsc
--
tDse
i+tAS_
VRW
VDOto VD7
)
-
-
.
tWHC
.-..-tAH2
~
-l---r~~-.--tDHC
.-tDH2
"
Ta = -20 to 75°C
Signal
Symbol
Parameter
Voo = 4.5 to 5.5V
min
EXT¢O
-
--
Unit
ns
tc-50
-
2tc - 30
-
ns
100
-
125
tw
tc-50
-
tCE
VCE LOW-level pulsewidth
2tc - 30
ns
tCYW
Write cycle time
3tc
-
3tc
-
ns
tAHC
Address hold time from
falling edge of VCE
2tc- 30
-
2tc - 40
-
ns
tASC
Address setup time to
falling edge of VCE
tc -70
-
tc -100
-
ns
tCA
Address hold time from
rising edge of VCE
0
-
0
-
ns
tAS
Address setup time to
falling edge of VWR
0
-
0
-
ns
tAH2
Address hold time
from
-rising edge of VWR
10
-
10
-
ns
twsc
Write setup time to
failing edge of VCE
tc-80
-
tc - 110
-
ns
twHC
Write hold time from
falling edge of VCE
2tc - 20
-
2tc - 20
-
ns
tosc
Data input setup time
to falling edge of VCE
tc-85
-
tc -120
-
ns
tOHC
Data input hold time
2tc- 30
from falling edge of VCE
-
2tc - 30
-
ns
tOH2
Data hold time from
-rising edge of VWR
50
50
ns
5
5
Condition
max
-
Clock period
VCE HIGH-level pulsewidth
VWR
VDOto
VD7
min
tc
VCE
VAOto
VA15
max
Voo = 3.0 to 4.5V
CL=
100pF
Note: VOO to VO? are latching input/outputs. While the bus is high impedance, VOO to VO? retain the write data until the data read
from the memory is placed on the bus.
161
I
SED1336
o
SLEEP IN Command Timing
veE
SLEEP IN write
tWRD
WR
(command input)
YOIS
Ta = -20 to 75°C
Signal
Parameter
Symbol
VDD = 4.5 to 5.5V
min
max
VDD = 3.0 to 4.5V
min
Unit
tWRD
VCE falling-edge delay
time
*1
-
*1
-
ns
tWRL
YDIS falling-edge delay
time
-
*2
-
*2
ns
WR
Condition
max
CL=
100pF
1. tWRD = 18tc + toss + 40 (toss is the time delay from the sleep state until stable operation)
2. tWRL = 36tc x [TC/R] x [UF] + 70
o
External Oscillator Signal Timing
EXT$O
-~/
Ta = -20 to 75°C
Signal
EXT¢O
1.
2.
Symbol
Parameter
VDD = 4.5 to 5.5V
VDD = 3.0 to 4.5V
Unit
min
max
min
max
-
15
-
15
ns
15
15
ns
tRCL
External clock rise time
tFCL
External clock fall time
tWH
External clock
HIGH-level pulsewidth
*1
*2
*1
*2
ns
twL
External clock
LOW-level pulsewidth
*1
*2
*1
*2
ns
tc
External clock period
100
-
125
-
ns
475
(tc - tRCL - tFCL) x 1000 < tWH, tWL
525
(tc - tRCL - tFCL) x 1000> twH, twL
162
Condition
SED1336
o
LCD Output Timing
The following characteristics are for a 1/64 duty cycle.
63,--,-1--=6...:.4...JI_ _ __
__________ --L-=6.::..0...L.::..61'--LI-=6.:;2...L.::..
LP
:....- + - - - - - - - - - 1 f r a m e l i m l E > e - - - - - - - - -
YD ____~r-l~~
________________________~~~____
WF
WF
: ..
.. :
1 line lime
Row 64
Row 1
Row 2
n
LP
XDO 10 XD3 (14) (15)
(16)
n
(15) (16) (1) (2) (3)
(1)
-.J __
Iwx
--I ---- If
(15) (16)
.
...
lex
V
XSCL
IDs:---1 _ I D H
-+--tLS ___________
K
)<
XDO10 XD3
•
!wL
JILD
LP
1\
-IDHYi
~
tDF
1""'--
WF(8)
I
YD
163
.
(1)
I
SE01336
Ta =-20 to 75°C
Signal
Symbol
Parameter
VDD = 4.5 to 5.5V
VDD = 3.0 to 4.5V
Unit
min
max
min
max
-
35
ns
35
ns
4tc
-
ns
ns
tr
Rise time
Fall time
-
30
tf
tex
Shift clock cycle time
4tc
twx
XSCL clock pulsewidth
2tc-60
XOO to
X03
tDH
X data hold time
2tc- 50
tDS
X data setup time
2tc -100
-
2tc -100
tLS
Latch data setup time
2tc- 50
-
2tc- 50
LP
twL
LP pulsewidth
4tc-80
-
4tc-100
tlO
LP delay time from XSC
0
-
0
-
WF
tDF
Permitted WF delay
-
50
-
50
ns
YO
tDHV
Y data hold time
2tc-20
-
2tc -20
-
ns
XSCL
30
2tc - 60
2tc- 50
Condition
ns
ns
CL=
100pF
ns
ns
ns
Note: The SED1336F reads display memory data from the address of the top left corner of the display screen, then scans horizontally
until it reaches the address forthe bottom right corner of the display screen. Therefore, each line of X-driver data is sent starting
from the left side of the display line.
164
SED1341
CMOS VIDEO - LCD INTERFACE (VLI)
•
DESCRIPTION
The SED1341 is a VLI (video-LCD interface) for converting previously separated video signals, intended for
a CRT display, into signals compatible with dot-matrix liquid-crystal displays (LCDs). When sync and data
separators are added, composite video signals can also be processed. Using the SED1341, a compact LCD
monitor can replace a monochrome CRT display without including additional software or hardware.
The frame-buffer memory controlled by the VLI accurately matches the high-frequency video signals to the
low-frequency operation of the LCD unit. Ascreen alignment function forthe adjustment ofthe display position
makes it easy to implement an LCD module that is compatible with CRT display.
Individual selection of the video data screen and LCD panel sizes and a vertical double line display mode allow
the SED1341 to interface LCDs with the video outputs of a variety of personal computers (PCs).
•
•
FEATURES
• Low-power CMOS technology
• Supports single panel and dual panel
• TTL-compatible signal input
• Built-in PLL to generate dot clock
• Supports 4-bit, 8-bit dual panel and 8-bit single
panel
• Screen alignment adjustment via 4-bit bus or
hardware
• Supports screen size from 640 x 200 to 720 x 400
• Supports 40KB SRAM frame buffer
• Horizontal and vertical back porch register
• Duty cycle ............................. 1/100 to 1/496
• Internal oscillator to optimize the frame frequency
to match the LCD timing
• Power-on clear function
• Supports vertical flyback time
• Package ................................ QFP5-80 pin (FOE)
• Single power supply ............. 5V ± 5%
AVAILABLE MODELS
SED1341 Foe and SED1341 FOE. See the functional comparison table at the end of this data sheet.
•
SYSTEM BLOCK DIAGRAM
DIGITALR
DIGITAL G
DIGITALB
PC
D
HSYC
VD
SED1341
VSYC
t
SRAM
165
r------[I
MONO LCD
II
I
SED1341
•
BLOCK DIAGRAM
cD, CD
00-03
Q)
)-<
CS/Sl, WR/S2 ) -
a..
VO,CK
HSC,VSC
PLO-PL3
>--
J
:;:
I~ r---
,--c
>--
scannin: Signal
Generator
Q)
§,~
I
1
lii
~
>.£1
5g
o C
::8
o.E
Q)
'----
I
Address Counter
(Read)
I
;J V DD
;J Vss
1
~
U5$
5
Y
SIP
Converter
J
"
MOO-M07
•
Timing Generator
Address Counter
(Write)
'5
a.
=
¥Y -y
1
~
'----
SO
RES
aSCl aSC2 SEL1-SEL13
PLL Program
Counter/Phase
Comparator
)--
~
~
AO/S5-A2IS3
pca
.- .-
\
MPX
"
I
),
WE
/
::=:r-
MAO-MA15
SED1341 Foc/SED1341 FOE Pin Comparison
PlO
SEl3
Pll
Pl2
SElS
SEl6
SEl7
SEla
TEST/lD3
TESTiLD2
TEST/LDl
TEST/lDO
TEST
SEL1
SEl2
K
VALID
lauD
00-03
~
VALID
twwR
WR
Input, Signal Reference Level; "H"
=2.0V
"L"
=O.SV
(VDD = 5V±5%, VSS = OV, Ta = 0 to 70°C)
Parameter
Min
Typ
CS Setup Time
tsucs
10
CS Hold Time
thCS
10
Ao-A2 Setup Time
tsuA
10
Ao-A2 Hold Time
thA
10
00-03 Setup Time
tsuD
50
00-03 Hold Time
thD
10
twWR
50
-
Pulse Width
Symbol
Condition
176
Max
Unit
-
ns
-
ns
-
ns
-
ns
ns
ns
ns
SED1341
•
Data Set Method By Digital Switch
1 Frame Time (LCD)
SO
S1
S2
S3
S4
I
S5
SO
~4 ~SH~l,-----'[. tWSL
S1
_ __
~~
tsUDS
thDS
DO - 03
==><__-,X
* Input Signal Reference Level; "H" = 2.OV
jIAUD
::::=============
"L" = O.SV
(VDD
Parameter
Symbol
Condition
=5V±5%, VSS = OV, Ta = 0 to 70°C)
Min"
Typ
-
Scanning Signal "H" Pulse Width
twSH
8t1-150
Scanning Signal "OFP' Width
twSL
8t1-150
00-03 Setup Time
tSUDS
100
thDS
0
00-03 Hold Time
*t1 is an oscillation frequency of X'tal oscillation circuit (t1 = 1/foso)
177
Max
-
Unit
ns
ns
ns
ns
SED1341
•
PLL Interface
pce
' - - - - - - - - - - -- - - - - - - - - - 1
HSC
L -_ _ _ _ _ _ _ _ _ _ _ _
CU
~
U
CD
~---------
--,
,,
I
\
CD
\
'-_.I
pce
HSC
CU
--+--+---------------
CD
v-------------------------
Input Signal Reference Level; "H" = 2.0V
"L" = O.BV
(VOO = 5V±5%, Vss = OV, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
CU "ON" Delay Time After HSC
tHU
CL=20pF
22
40
ns
CU "OFP' Delay Time After CK
tcu
CL=20pF
22
40
ns
CU "ON" Delay Time After CK
tco
CL=20pF
22
40
ns
CD "OFF" Delay Time After HSC
tHO
CL =20pF
22
40
ns
PCO Delay Time After CK
tcPCO
CL=20pF
-
35
ns
PCO Pulse Width
twpco
CL= 20pF
tccK-25
-
-
ns
178
SED1341
•
Reset Input
RES---~t
tWRES
I
(VDD = 5V±5%, Vss = OV, Ta = 0 to 70°C)
Parameter
Condition
RES Pulse Width
Input Signal Reference Level; "H" = 2.0V
"L" = O.8V
179
Typ
SED1341
•
EXAMPLE OF APPLICATION: 640 x 200 Dots, 4 bit 2-Bus, 2-Screen Operation
MPU
08C2
,
~
Ck
VD
~ HSC
<3 vsc
uoo,uo3~~~~~§~~~~~§~~§l~~~§~~~~!E~;=~~_
LP
WF
X8CL
VO
H8C
VLI
yOf-----+h
VSC
j
LDO-L03
Dot Matrix LCD Panel
(640 x 200)
8RAM2064C
8RAM2064C
64K8RAM x2
Recommended X Driver: SED1600F
Recommended Y Driver: SED1610F
•
640 x 400 DotsJ640 x 350 Dots Connecting to Memory
I~
15
B
256KSRAM
rm-IC
SRM20256 (32k x B)
640 x 400 Dots/640
x 350 Dots Application Circuit
180
SED1341
•
640 x 480 Dots Connecting to Memory
VLI
C\J
t'-
~
«
Cl
««««
Cl
~C')'C
"H" = VDD x O.8V
"L" = VDD x O.2V
189
I
SED1345
o
X Driver
(VDD = 5V±5%, Vss = OV, Ta = 0 10 70°C)
Parameler
X8CL Cycle Time
X8CL "H" Pulse Widlh
X8CL "L" Pulse Widlh
UDO-3, LDO-3 8elup Time
before X8CL
UDO-3, LDO-3 Hold Time
aflerX8CL
8ymbol
Icsc
IWSCH
twSCL
ISUXD
IHXD
X8CL 10 LP Time
ISL1
X8CL 10 LP Time
ISL2
Condilion
Min
86="H"
211
86 ="L"
411
86="H"
11-20
86 ="L"
211-20
86="H"
11-20
86 = "L"
211-20
86="H"
11-30
86 = "L"
211-30
86="H"
21-30
86 = "L"
211-30
85="H"
LP 10 X8CL Time
LP 10 X8CL Time
X8CL 10 LP Time
ILS1
ILS2
ISL3
85 = "L"
LP 10 X8CL Time
LP Cycle Time
ILS3
ICLP
0.511-30
86 ="L"
11-30
86="H"
11-20
86 ="L"
211-20
86="H"
1.511-50
86 ="L"
311-50
86="H"
11-20
86 = "L"
2t1-20
86="H"
0.511-40
86 = "L"
11-40
86="H"
0.511-40
86 = "L"
11-40
80="H"
32011
80 = "L"
64011
85="H"
LP, Y8CL "H" Pulse Widlh
86="H"
IWLPH
85 ="L"
86="H"
1.511-50
86 ="L"
311-50
86 ="H"
11-40
86 = "L"
2t1-40
LP 8elup Time before XECL
ISULP
85 = "H", 86 = "H"
11-50
LP Hold Time after XECL
IHLP
85 = "H", 86 = "H"
0.511-40
X8CL 10 XECL Time
IES1
85 = "H", 86 = "H"
0.511-30
XECL 10 X8CL Time
IES2
85 = "H", 86 = "H"
0.511-40
IWECH
85 = "H", 86 = "H"
1.5t1-50
IDFR
85 = "H", 86 = "H"
XECL "H" Pulse Widlh
WF OUlput Delay Time After LP, Y8CL
t1 = 2tCCK (tCCK = dot clock cycle)
190
-
Typ
Max
Unil
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
ns
100
ns
ns
ns
ns
SED1345
o
Y Driver
(VDD = 5V±5%, Vss = OV, Ta = 0 to 70°C)
Parameter
YO Setup Time
before LP, YSCL
Symbol
Condition
tSUYD1
S5 ="H"
YO Hold Time
thYD1
after LP, YSCL
YO Setup Time
Min*
Typ
SO = "H"
142t1-100
302t1-100
-
-
ns
SO ="L"
SO="H"
1St1-100
1St1-100
-
-
ns
SO ="L"
-
-
ns
-
-
ns
SO = "H"
SO = "L"
S5= "L"
YO Hold Time
after LP, YSCL
SO="H"
tHYD2
SO ="L"
Unit
S6="H" 141.5t1-100
S6 ="L"
tSUYD2
before LP, YSCL
Max
141t1-100
S6="H" 301.5t1-100
S6 ="L"
301t1-100
S6="H"
17.5t1-100
S6="L"
17t1-100
S6="H"
17.5t1-100
S6= "L"
17t1-100
t1 =2tCCK (tCCK = dot clock cycle)
(VDD = 5V±5%, Vss = OV, Ta = 0 to 70°C)
Parameter
CK Cycle Time
Symbol
Condition
Min
Max
Unit
-
ns
12
-
tr2
-
-
5
ns
tf2
-
tCCK
33
CK "H" Pulse Width
twCKw
12
CK "L" Pulse Width
tWCKL
Input Rise Time
Typ
ns
ns
ns
tSUVD
16
-
5
VO Setup Time Before CK
-
ns
VO Hold Time After CK
tHvD
2
-
-
ns
CK Setup Time Before HSC
tSUCK
20
-
ns
-
-
-
ns
-
ns
Input Fall Time
CK Hold Time After HSC
tHCK
0
HSC Setup Time Before VSC
tSUVH
SO
HSC Hold Time After VSC
tHVM
0
Active Pulse Width HSC
tWH1
StCCK
Non-Active Pulse Width HSC
twH2
64tcCK
191
-
ns
ns
ns
I
SED1345
•
o
Memory Interface
Read Cycle
SRAM Read Cycle
..
MAO to MA15
~
--{
tRC1
..
VALID
'X
MDO to MD7
(Memory --7 VLI)
...
tOH
tACC
VALID
I
(VDD = 5V±5%, Vss = OV, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min
Typ
Read Cycle Time
tRC1
4tCCK
Address Access Time
lAcc
-
-
Output Hold Time
tOH
10
-
192
Max
4tCCK-17
-
Unit
ns
ns
ns
SED1345
o
Write Cycle
Write Cycle
..
tWCl
---
tAS
MAO to MA15
~~
JS
VALID
II
tWPl
~.
WE
--~,----I_~
tow
'II
MOO to M07
~
tWR
_
_
.
(VLI -> Memory)
.,
tOH
~-----
(VOO
Parameter
Symbol
= SV±S%, Vss =OV, T a = 0 to 70°C)
Min'
Typ
Write Cycle Time
tWC1
4tCCK
-
Write Pulse Width
twP1
3tCCK-13
-
Address Setup Time
tAs
O.StccK-14
Address Hold Time
twR
O.StccK-14
-
-
ns
Data Setup Time
tow
3tCCK-38
-
-
ns
Data Hold Time
tOH
S
-
-
ns
input/Output Signal Reference Level: "H"
'tCCK is the cycle time of dot clock (tCCK
=2.0V
Condition
I
.
VALID
"L"
=O.BV
= l/fcK).
193
Max
-
Unit
ns
ns
ns
SED1345
•
o
Register Program
Write Data Using MPU
..
cs
tsucs
tHCS
~
~
II
~
AO to A4
tHA
~.
;X
K
VALID
r-~
tSUD
DO to 03
tWWR
WR
\
(VOO
Min
Typ
CS Setup Time
tsuCS
50
CS Hold Time
tHCSH
50
-
Ao-A4 Setup Time
tSUA
50
-
AO-A4 Hold Time
tHA
50
00-03 Setup Time
tsuo
100
00-03 Hold Time
tHO
50
twWR
50
Parameter
WR Pulse Width
Symbol
Condition
= 5V±5%, VSS = OV, Ta =0 to 70
194
Max
D
C)
Unit
ns
-
-
-
-
ns
ns
ns
ns
ns
ns
SED1345
•
Write Data Using ROM
....
.-1
--------~
AO
A2 -1-/---'
--------~
_________------..JI
A3 - t - + - - - - - - - '
-------- - - - -
A4 - f - - + - - - - - - - - - '
-------- - - - -
A1
..
tRC2
VALID
AO
I
VALID
\1
~4·___
VALID
tSURM
DO to 03 _ _
V_A_LI_D_~)(~_V_A_L_ID_
VA_L_I_D_ _
_ __
Input/output signal level identification voltages:
"H" level- 2.0V
"L" level - O.BV
(VDD = 5V±5%, Vss = OV, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min'
Typ
-
tRC2
Bt1-100
00 to 03 Setup Time
tSURM
100
00 to 03 Hold Time
tHRM
10
ROM Read Cycle Time
• t1 =2tCCK (tCCK is a cycle time of dot clock)
195
Max
-
Unit
ns
ns
ns
SED1345
•
Reset Input
tWRES
RES------~~~~------~j;
(Voo
=5V±5%, Vss =OV, Ta =0 to 70°C)
Condition
Parameter
RES Pulse Width
Input signal reference level: "H" = 2.0V "L" = O.BV
tCCK is a cycle time of dot clock (tCCK = l/fcK)
•
System Configuration
MPUIROM
+5V
66
G
Personal
Computer
B
I
A
67 G
1(1) O..-C\lOO
w ccoo
10:
~<~~=E
I~I~
TEST 71
68 B
65
vsc
I
61 VSC
HSC
60 HSC
CK
64 CK
LP
WF
5
4
YSCL 11
YO 10
XSCL 7
XECL 6
SED1345
UDO 80
UD1 79
UD2 78
2
23
42 Voo
UD3 77
LOO 76
63
LD1 75
LD2 74
L03 73
3
22
43 Vss
62
196
640 x 480
LCD
SED1351
GRAPHICS LCD CONTROLLER
•
DESCRIPTION
The SED1351 F is a graphics LCD controller capable of controlling medium to large resolution displays. It
transfers data from MPU to external frame buffer RAM and converts this data to display signals for LCD
drivers. The SED1351 F can display images with 4 gray shades and support display duty cycle as high as 1/
1024.
The SED1351 F is designed to achieve high efficiency and data throughput to the LCD. It has a cycle steal
mode which allows MPU to access frame buffer RAM without interfering with the display operation. The
SED1351 F can directly interface with up to eight 64K-bit SRAMs or two 256K-bit SRAMs.
The SED1351 F can operate with either 5Vor 3V power supply. The 5Vversion chip is the SED1351 FOAand
the 3V version chip is the SED1351 FLB.
•
FEATURES
• Low-power CMOS technology
• Maximum number of rows
Binary mode ............ 2048
Gray mode .............. 1024
• 8-bit or 16-bit MPU data interface
• Direct interface with 80xx, Z80 and 68xxx MPU
• Maximum number of rows:
Single panel ............ 1024
Dualpanel ............... 2048
• 4- or 8-bit panel data bus for single panel and
4-bit bus for dual panel
• Support logical OR of layers and panel division
• Maximum display sizes when 64K-byte SRAMs
are used:
• Smooth vertical scrolling
• Virtual screen display up to 1024
Binary mode ............ 2048 x 256/1024 x 512
Gray mode .............. 1024 x 256/512 x 512
• Binary mode (on/off only) generates black &
white images
• Available models:
SED1351FoA ............ 5V, OFP5-100 pin
SED1351FLB ............ 3V,OFP15-100 pin
• Gray mode (on/off and two gray steps) generates images with 4 gray shades
•
SYSTEM BLOCK DIAGRAM
CLOCK
DATA
CONTROL
MPU
80xx
Z80
68xxx
~
SED1351F
ADDRESS
t
SRAM
8 of 8K x 8 or
2 of32Kx 8
197
r-- I
MONO LCD
I
I
SED1351
•
INTERFACE WITH 8-BIT MPU (Z-80) AND 64K-BIT SRAM (8 of 8K x 8)
SED1351F
Z80
AO-A15
~
•
L
MEMRO
c.
I
YD
lP
IDECODER~
r
MMU
UDO-UD3,lDO-lDil..
AO-A15
DECODER
~-
IOCS
XSCl
MPUSEl
FR
--
MEMCS
•
VAO-VA12
VDO-VD7
VCSO-VCS7
VWE
MONOlCD
AO-A12
1/01-1108
Q§iO)
WE
gAO-A12
IOREO
1/01-1/08
C5(1)
WE
gAO_A12
1/01-1/08
C5(2)
3AO-A12
~WE
/I
~
DBO-DB7
DO-D7
~
"
RD
~
WR
-
I
]1:
lORD
-IOWR
--
MEMRD
--MEMWR
1101-1108
eS(3)
WE
3 AO-A12
1/01-1/08
CS(4)
WE
gAO_A12
1/01-1/08
eS(5)
+WE
gAO-A12
~-
WAIT
READY
--
RESET
RESET
ClK
MPUlCK
Note: Example implementation, actual may vary.
198
1101-1/08
Q§!6)
WE
§AO-A12
1/01-1/08
C8(7)
~WE
8Kx8
SED1351
•
INTERFACE WITH 16-BIT MPU (8086) AND 64K-BIT SRAM (8 of 8K x 8)
80B6
(Maximum Mode)
8288
'"
"
"
SED1351
MRDc
MEMRi'i
AMWC
MEMWR
"rn
XSCL
iORO
AIOWC
+5V
I iOWR
I
~,MPUSEL
VAO_VA12
VDO_V07
VCsil
Wi'
VCs4
SHE
ilCS6
VOS-VD15
VCsi"
VCs9
MINiM'AX
VCs5
I RESET
READY
Note: Example implementation, actual may vary.
199
VCs7
I
SED1351
•
INTERFACE WITH 16-BIT MPU (68000) AND 256K-BIT SRAM (2 of 32K x 8)
68000
UDO-UD3,lDO-lD3
DACK
~~~
READY
YD
lP
FR
CK
-
FCO,1,2
Decoder
VDO-VD?
I/OH/OB
CS(O)32Kx B
VCSO
--
-
MEMCS
AS
AO-A14
VA1-VA1S
-
10CS
A[16-23]
MONOlCD
XSCl
~I]
-
-
WE
VWE
--
-
FWI
MEMRD
J
"V"'f
lORD
--
r--.
v
~
MEMWR
j
-10WR
A[1-15]
AB1-AB15
-
lDS
ABO
UDS
BHE
Note: Example implementation, actual may vary.
200
I
~
VDB-VD15
-VCS1
~
AO-A14
1/01-I/OB
CS(1)32Kx B
WE
SED1351
•
SUPPORTED RESOLUTIONS
Display
RAM
•
Maximum Display Size
4 Grayscale
Monochrome
SRAM
Type
CPU
Interface
SRAM
Interface
y
X
8K
256
x
256
256
x
128
1 of 8K x 8
8 bit
8 bit
16K
512
x
256
256
x
256
2 of 8K x 8
8 bit
16 bit
8 bit
16 bit
24K
512
x
384
384
x
256
3 of 8K x 8
8 bit
8 bit
32K
512
x
512
512
x
256
4 of 8K x 8
8 bit
16 bit
8 bit
16 bit
1 of 32K x 8
8 bit
8 bit
48K
768
x
512
512
x
384
6 of 8K x 8
8 bit
16 bit
8 bit
16 bit
56K
896
x
512
512
x
448
7 of 8K x 8
8 bit
8 bit
64K
1024
x
512
512
x
512
8 of 8K x 8
8 bit
16 bit
8 bit
16 bit
2 of 32K x 8
8 bit
16 bit
8 bit
16 bit
X
Y
BLOCK DIAGRAM
READY
RESET
MPUSEL, MPUCLK
IOCS,LOWR, lORD
MEMCS, MEMWR, MEMRD
LCDENB
XSCL
ABO -AB15
BHE
LP
YD
WF
DBO-DB15
UDO - UD3
LDO - LD3
OSCl
OSC2
VAO-VA15
VCSO-VCS4
201
VDO - VD15
I
SED1351
•
•
•
ELECTRICAL CHARACTERISTICS
SED1351FOA
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Ratings
Unit
Voo
Vss-0.3 to 7.0
V
V
Input voltage
VI
Vss-0.3 to Voo+0.3
Output voltage
Vo
Vss-0.3 to Voo+0.3
V
Output current/pin
10
±10
rnA
Power dissipation
Po
200
mW
rnA
loo/Iss
±40
Storage temperature
Tstg
-65 to 150
°C
Soldering temperature and time
Tsol
260°C, 10s (at lead)
-
Supply current
•
(Vss = OV)
Recommended Operating Conditions
(Vss
Parameter
Supply voltage
Input voltage
Operating temperature
=OV)
Min
Typ
Max
Unit
4.5
5.0
5.5
V
VI
Vss
-
Voo
V
Topr
-20
-
75
°C
Symbol
Condition
Voo
202
SED1351
o
DC Characteristics (FOA)
Parameter
Static current
Input leakage current (Type 1)
(Ta
Symbol
IDDs
III
High level input voltage 1 (OSC1)
VIH1
Low level input voltage 1 (OSC1)
High level input voltage 2 (Type 2)
Low level input voltage 2 (Type 2)
High level input voltage 3 (Type 3)
Low level input voltage 3 (Type 3)
Hysteresis voltage (Type 3)
High level output voltage 1 (Type 4)
VIL1
VIH2
VIL2
VT+
VTVH
VOH1
Low level output voltage 1 (Type 4)
Vou
High level output voltage 2 (OSC2)
VOH2
Low level output voltage 2 (OSC2)
VOL2
Condition
VIN = VDD, VDD = Max,
Vss, IOH = IOL = 0
VDD = 5.5V,
VIH = VDD,
VIL = Vss
VDD = 5.5V
VDD = 4.5V
VDD = 5.5V
VDD = 4.5V
VDD = 5.5V
VDD = 4.5V
VDD = 5V
VDD = 4.5V
IOH =-2mA
IOL= 6mA
VDD = 4.5V
IOH = -50~A
IOL = 50~A
= -20 to 75°C)
Min
Typ
Max
Unit
-
-
100
~A
-10
-
10
~A
3.5
-
-
V
-
1.0
2.0
-
0.8
V
V
V
V
V
V
V
-
-
4.0
-
-
-
-
0.8
0.3
VDD
-0.4
-
-
-
-
-
-
VDD
-0.4
-
-
-
Vss
+0.4
Vss
+0.4
V
V
V
Note:
Type 1. MEMCS, MEMWR, MEMRD, laCS, IOWR, lORD, MPUCLK. ABO - AB15, BHE. MPUSEL, RESET, OSC
Type 2.
MEMCS, MEMWR, MEMRD, laCS, IOWR, lORD, MPUCLK, ABO - AB15, BHE, DBO - DB15, VDO - VD15
Type 3.
MPUSEL, RESET
Type 4.
DBO - DB15, READY, VAO - VA15, VCSO - VCS4, VDO - VD15, VWE, XSCL, LP, WF, YD, UDO - UD3, LDO - LD3,
LCDENB
203
I
SED1351
•
•
SED1351 FLA
Absolute Maximum Ratings
Parameter
(Vss
Symbol
Ratings
Voo
Vss-0.3 to 7.0
V
Input voltage
VI
Vss-Q.3 to Voo+0.5
V
Output voltage
Vo
Vss-Q.3 to Voo+0.5
V
Output current/pin
10
±24
mA
Supply voltage
Power dissipation
Supply current
Storage temperature
•
= OV)
Unit
Po
200
mW
loo/Iss
±40
mA
Tstg
-65 to 150
DC
Recommended Operating Conditions
(Vss
Parameter
Supply voltage
Input voltage
Operating temperature
Symbol
Condition
Min
Typ
Max
= OV)
Unit
VDD
2.7
-
3.6
V
VI
Vss
VDD
V
Topr
-20
-
75
DC
204
SED1351
o DC Characteristics (FLB)
Parameter
Static current
Input leakage current (Type 1)
(Ta = -20 to 75°C)
Symbol
loos
IL
High level input voltage 1 (OSC1)
Low level input voltage 1 (OSC1)
High level input voltage 2 (Type 2)
Low level input voltage 2 (Type 2)
High level input voltage 3 (Type 3)
Low level input voltage 3 (Type 3)
Hysteresis voltage (Type 3)
High level output voltage 1 (Type 4)
VIH1
VIL1
VIH2
VIL2
Vr+
VrVH
VOH1
Low level output voltage 1 (Type 4)
VOLl
High level output voltage 2 (OSC2)
VOH2
Low level output voltage 2 (OSC2)
VOL2
Min
Condition
VIN = Voo or Vss,
Voo = MAX, IOH = IOL = 0
Voo= MAX,
-1
VIH = Voo,
VIL= Vss
0.7Voo
Voo= MAX
Voo = MIN
Voo=MAX
0.7Voo
Voo =MIN
Voo= MAX
Voo= MIN
Voo = TYP
Voo= MIN
IOH=-1.5mA
IOL= 3mA
Voo = MIN
IOH = -501lA
IOL = 50llA
O.BVoo
0.3
Voo
-0.3
Typ
Max
30
Unit
-
1
IlA
-
0.2Voo
V
V
V
V
V
V
V
V
-
0.2Voo
0.2Voo
-
IlA
-
-
Vss
+0.3
V
Voo
-0.4
-
-
V
-
-
Vss
+0.4
V
Note:
Type 1. MEMCS, MEMWR, MEMRD, IOCS,IOWR,IORD, MPUCLK, ABO - AB15, BHE, MPUSEL, RESET, OSC
Type 2. MEMCS, MEMWR, MEMRD,IOCS, IOWR, lORD, MPUCLK, ABO - AB15, BHE, DBO - DB15, VDO - VD15
Type 3. MPUSEL, RESET
Type 4. DBO - DB15, READY, VAO - VA15, VCSO - VCS4, VDO - VD15, VWE, XSCL, LP, WF, YD, UDO - UD3, LDO - LD3,
LCDENB
205
I
SED1351
•
PIN CONFIGURATION (FOA)
VI>:3
VD11
VD12
VD13
VD14
VD15
LCDENB
X8CL
LP
WF
YD
VI&.
VA1
VAO
VWE
DB15
DB14
DB13
DB12
DB11
DB10
DB9
SED1351FoA
UDO
UD1
UD2
UD3
LDO
LD1
LD2
LD3
05C1
08C2
•
DB9
DB7
DBS
DBS
DB4
DB3
DB2
DB1
PIN CONFIGURATION (FLB)
. .
VDS
VD9
VD10
VD11
VD12
VD13
VD14
VD15
LCDENB
X5CL
LP
WF
YD
UDO
UD1
UD2
UD3
LDO
LD1
LD2
LD3
OSC1
v__
OSC2
Vss
VA4
VA3
VI&.
VA1
VAO
VWE
SED1351FLB
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DBS
DB7
DBS
DB5
DB4
DB3
DB2
DB1
DBO
AB15
AB14
Voo
206
SED1351
•
PIN DESCRIPTION
1. System Connector Terminals (at MPU)
Pin Name
Type
FOA
Pin No.
FLB
Pin No.
DBO to DB15
110
30 to 45
28 to 43
These pins are interfaced with the MPU data bus.
When using an 8-bit MPU, connect DB8 to DB15 to
VDD.
ABO to AB15
I
14 to 29
12 to 27
These pins are interfaced with the MPU address bus.
If multiplexed address signals are used, connect them
via latch circuits. A control register is selected by ABO
to AB3. Correspondence of the MPU address bus to
the VRAM address bus is such that ABi VAi (where
i is a pin number).
Description
Drv
=
BHE
I
13
11
This signal is a bus high enable signal where a 16-bit
MPU is used. It goes "L" (low) when an odd address is
encountered. When using an 8-bit MPU configuration,
connect the BHE pin to VDD.
10CS
I
3
1
This pin selects a control register contained in the
SED1351. It is "L" active, and must be assigned to
MPU 110 space.
10WR
I
4
2
This signal is used for writing data into a control
register contained in the SED1351. It is "L" active, and
must go "L" when it encounters an OUT instruction
from the MPU.
lORD
I
5
3
This signal is used for reading data from a control
register contained inthe SED1351.lt is "L" active, and
must go "L" when it encounters an IN instruction from
the MPU.
MEMCS
I
6
4
This signal is used for selecting VRAM. It is "L" active,
and must be assigned to MPU memory space.
MEMWR
I
7
5
This signal is used for writing data to the VRAM. It is "L"
active, and must go "L" when it encounters a memory
write instruction from the MPU.
MEMRD
I
8
6
This signal is used for reading data from the VRAM. It
is "L" active, and must go "L" when it encounters a
memory read instruction from the MPU.
READY
0
9
7
This signal requests the MPU to wait. It goes "L" by the
falling edge of IOCS or MEMCS. It goes "H" by the
riSing edge of MPUCLK after completion of the
SED1351 internal processing. Since READY is not a
tri-state pin, it needed not be pulled up and must be
connected directly to the READY (WAIT) terminal of
the MPU.
MPUCLK
I
10
8
This pin accepts an MPU clock. The MPU wait state is
cleared by the rising edge of MPUCLK.
MPUSEL
I
12
10
This signal is connected to either VDD or VSS for
selection of an MPU.
MPUSEL
MPUSEL
RESET
I
11
9
=Vss 8-bitMPU (e.g., Z80, V20, i8088)
=Vee 16-bit MPU (e.g., V30, i8086)
The MPU reset signal comes to this pin. It is "H" active,
and initializes a control register.
207
I
SED1351
Combinations of Control Pins
10CS
1
10WR
*
0
0
0
1
MEMCS
MEMWR
1
*
1
1
1
1
0
1
1
1
Read from control register
lORD
*
MEMRD
*
Operation
Invalid
Write to control register
1
1
1
0
0
1
Write to VRAM
1
1
1
0
1
0
Read from VRAM
Note: Any combination other than those listed above will cause a system error.
1
"H" (high)
o
"L" (low)
Don't care
2. VRAM Connector Terminals
FOA
Pin No.
FLB
Pin No.
1/0
68 to 78,
81 to 85
68 to 83
These pins are interfaced with the VRAM data bus.
For a 16-bit MPU configuration, VDO to VD7 must be
connected to even addresses, and VD8 to VD15 to
odd addresses. For an 8-bit configuration, VD8 to
VD15 must be connected to VDD.
VAOto VA12
0
47 to 59
45 to 49,
52 to 59
These pins are interfaced with the VRAM address
bus and chip select pins.
VA13NCS7 to
VA15NCS5
0
60 to 62
60 to 62
VCSOto VCS4
0
67 to 63
67 to 63
The SED1351 has chip select pins that can directly
control eight 64K SRAMs (8K bytes each) or two
256K SRAMs (32K bytes) in the 64K VRAM space.
See Technical Manual for details.
VWE
0
46
44
FOA
Pin No.
FLB
Pin No.
Pin Name
Type
VDO to VD15
Description
Drv
This signal is used for writing data to the VRAM. It is "L"
active, and must be connected to the WE pin of the
VRAM.
3. Oscillator Terminals
Pin Name
Type
OSC1
I
99
97
OSC2
0
100
98
FOA
Pin No.
FLB
Pin No.
2,79
51,100
1,80
50,99
Drv
Description
The OSC1 (input) and OSC2 (output) pins generate clocks for internal operation. They allow crystal
oscillation and external clock input.
4. Power Terminals
Pin Name
Voo
Vss
Type
-
Drv
Description
The power supply pins include two Voos and two
Vsss. Apply +5V or +3V to Voo and OV to Vss. A
capacitor (4.7 J.LF or more) must be connected near
each pair of VooNss pins.
208
SED1351
5. LCD Connector Terminals
Pin Name
Type
FOA
Pin No.
FLB
Pin No.
Description
Drv
UDOto UD3
1/0
91 to 94
89 to 92
LDO/UD4 to
LD3/UD7
0
95 to 98
93 to 96
XSCL
0
87
85
This single is a shift clock for display data transfer.
Take the UDO to UD3, LDO/UD4 to LD3/UD7 display
data into LCDs by the falling edge of XSCL.
LP
0
88
86
This pin provides both a display data latch pulse and
a scan signal transfer clock. Upon completion of transferring the LCD data on one line, display data can be
latched or a scan signal transferred by the falling edge
of LP.
WF
0
89
87
This pin provides a frame signal used for LCD AC
driving.
YD
0
90
88
This pin provides a scanning line start pulse. The
signal is "H" active. Allow the scanning line drive IC to
take in YD by the falling edge of LP.
LCD display data. UDO to UD3 are the upper panel
display data in the signal panel or double panel
drive panel mode. LDO/UD4 to LD3/UD7 are the lower
panel display data in the double panel drive mode.
UDO to UD3, and LDO/UD4 to LD3/UD7 are used for 8bit data transfer in the single panel drive mode.
The SED1351 has two lines of retracing; if two scanning line drive ICs are cascade-connected for the
upper and lower panels in the double panel drive
mode, two lines must be provided between the upper
and lower scanning line drive outputs.
LCDENB
0
86
84
This pin provides the data which is set in bit 1 (D1) of
the mode register (R1). LCDENB goes "L" when the
system is reset; it can be effectively used for LCD
power control.
209
I
SED1351
Illustrated below are the display data which are output from the UDO to UD3, LDO/UD4 to LD3/UD7 and the
display on the panel:
UDa! UD2! UD1! UDO ! •••
UDa! UD2! UDl ! UDa ! LDa! LD2! LDl ! LOa ! •••
Dual Panel - Top
8-bit Single Panel
LDal L021 LDll LDa I •••
D.ual Panel - Bottom
uDaIUD2! UDl ! UDa ! uDa! UD2! uDlluDa
J•••
4-bit Single Panel
•
LCD PANEL PIXELS
...
640 DOTS
1 - 1 11-2 I
2-1 I 2-21
24oLINES
11-63911-640
12-63912-640
UPPER LCD PANEL
240-1 !240-2 !
241 - 1 I 241 - 2 I
!240- 639!240- 640
1241- 6391241- 640
(TOP VIEW)
24oLINES
LOWER LCD PANEL
480-1 !480-2!
!480- 639!480- 640
210
SED1351
•
MONOCHROME LCD PANEL INTERFACE
8-Bit Dual Monochrome Panel (Le. 640 x 480)
YD
LP
WF
UD[3:0]. LD[3:0]
LlNE239i479 LlNE2401480
I
LP _ _ _-'n~
LINE 11241
LINE 21242
_______
WF ________~,L-_______________
XSCL _ _ _ ..
~:C_L_1:~~~ .. ~
UD3---"~-----'~··~
UD2---"~-----'~··~
UD1---"~-----'~··~
UDO---"~-----'~··~
LD3---·-~------~--~
LD2---"~-----'~··~
LD1---"~-----'~··~
LDO-----~------~--~
211
I
SED1351
•
MONOCHROME LCD PANEL INTERFACE
4-Bit Single Monochrome Panel (Le. 320 x 480)
YD
LP
WF
UD[3:0]
LP
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'
WF
----
XSCL _ _ _ ..
JLriJ=LJ=L~~L~8:~~~
.. ___IL
UD3---"~-----'~··~
UD2---"~-----'~"~
UD1---"~-----'~"~
UDO---"~-----'~··~
8-Bit Single Monochrome Panel (Le. 640 x 480)
LP 482 PULSES
------------_~_I~
YD _ _ _ _ _--'
LP~==~~==4=~==~~--~
WF
UD[3:0]. LD[3:0]
I
--'nL-______
_
LP _ _
WF-------,~------------
I
XSCL _____ ..
J L r i J = L J = LSCL : 80 CLOCKS
~
_____ .~ .. ___IL
UD3---"~-----'~"~
UD2---"~-----'~"~
UD1---"~-----'~"~
UDO---"~-----'~"~
LD3---"~-----'~"~
LD2---"~-----'~"~
LD1---"~-----'~"~
LDO---"~-----'~"~
212
SED1351
•
PACKAGE DIMENSIONS
•
SED1351 FDA
Unitmm
QFPS-100pin
25.6±OA
.
ci
+1
~~~:
o
10.30."
J4;;nn;;nn;nnn;;;;;nn;;;nn;;nn;nn;;;;;nnn;;;nn;;;;;nn;nn;;;;;nnn;;;nn~
0_12°
15,tol
D
Actual Size
2.8
•
I
SED1351 FLB
Unitmm
QFP1S-100pin
l6.0±DA
14.0±O.1
h.-"'"' . .'"'
)""DU'DUDUDUDUDU'DU"~" _..
O.5.±O,2
o
Actual Size
1.0
213
THIS PAGE INTENTIONALLY BLANK
214
SED1352FoA
GRAPHICS LCD CONTROLLER
•
DESCRIPTION
The SED1352 is a high duty cycle, graphic display LCD controller capable of displaying a maximum of 16
levels of gray shade on single and dual scan Liquid Crystal Displays. A 16x4100kup table is provided to allow
remapping of the 16 possible gray shades displayed on the LCD panel. The SED1352 can interface to
MC68000 microprocessor, 8/16 bit ISA Bus, and 8/16 bit MPUs with READY (WAIT#) signal with minimum
external "glue" logic. This chip can directly control up to 128 Kbytes of static SRAM.
Optimized for cost and power savings, the SED1352 can operate from 2.7 Volt to 5.5 Volt and from 5 Mhz
to 25Mhz.
•
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
16-bit 16 Mhz MC68000 MPU interface
8/16-bit ISA data bus interface bus
•
Display memory interface:
•
LCD panel configurations:
•
Maximum number of vertical lines:
8/16 bit MPU interface controlled by a READY
(or WAIT#) signal
Option to use built-in index register or directmapping to access one of fifteen internal
registers
2-terminal crystal input for internal or external
crystal oscillator
8/16 bit SRAM interface configurations
Two software power-save modes
One 1 Mbit SRAM(64Kx16)
One or two 32Kbyte SRAM(s)
One or two 8Kbyte SRAM(s)
One 8Kbyte and one 32Kbyte SRAM
Single-panel, single-drive display
Dual-panel, dual-drive display
1,024 lines (single-panel, single-drive
display)
2,048 lines (dual-panel, dual-drive
display)
Low power consumption
Virtual display support
•
•
Packed pixel mode support
Display modes:
2 bit/pixel, 4-level gray-scale display
4 bit/pixel, 16-level gray-scale display
Split screen display support at single-panel
mode
QFP5-100-S2 package
SYSTEM BLOCK DIAGRAM
l
MPU
BOxx
ZBO
6Bxxx
CLOCK
.1
~
SED1352
l
l
SRAM
~
215
B
I
SED1352FoA
•
INTERFACE OPTIONS
J
Interface with 16·bit MC68xxx MPU and 16Kbytes SRAM (2 of 8K x 8)
MC68xxx
SED1352
A20 toA23
FCOto FC1
1
A16 .. A14
IJ
:1 Decoder ~
MEMCS
VD8-15
VDO-7
IOCS
VWE
Decoder
A10 to A19
A1 to A19
DO to 015
DTACK
LOS
UDS
AS
AB1-AB19
DBO-DB15
READY
AB
BHE
VCSO
lOR
VCS1
lOW
VAO-12
RJW
l
~
t
+
I
1
CS
Lf
~
WE
~4Kbit
WE
~4Kbit
CS
1
r
Note: Example implementation, actual may vary.
Interface with 8·bit Z80 MPU and 16Kbytes SRAM (2 of 8K x 8)
Z80
~
MREO
IORO
AO to A15
DO to 07
WAIT
WR
RD
A10 to A15
SED1352
Decoder
MEMCS
Decoder
IOCS
•
•
1
I
~
-RESET
Note: Example implementation, actual may vary.
216
VDO-7
VWE
ABO-AB15
DBO-DB7
READY
MEMW
MEMR VCSO
lOR
VCS1
lOW
VAO-12
RESET
~
t
+
I WE
~4Kbit
CS
Lf
~
I WE
~4Kbit
CS
r
I
SED1352FoA
Interface with 16-bit 8086 MPU and 64Kbytes SRAM (2 of 32K x 8)
8086
(Maximum mode)
-1
8288
ClK
ClK
S2
52
READY
Sf
Sf
RESET 1--<- RESET
so
-
ClK
READY
f---
so
RDY
DEN
,--- DT/R
ALE
8284A
A16-A19
BHE
ADO-AD15
SED1352
MRDC
MEMR
AMWC
MEMW
--
IORC
-AIOWC
A
I
ABO-AB15
AO-A16
BHE
-MEMCS
STB
IOCS
vcso
L----i
~
DBO-DB15
-{>-----lOE
WE
~6Kbit
CS
~
VCS1
-RESET
READY
VD8-15
Note: Example implementation, actual may vary.
Interface with 8-bit ISA Bus and 40Kbytes SRAM (1 of 8K x 8 and 1 of 32K x 8)
8-Bit ISA Bus
REFRESH
SED1352
I
SA16~
MEMCS
SMEMW
MEMW
MEMR
SMEMR
IOeHRDY
SDO-SD?
SAO-SA19
~
~
AEN
SA(1or4) to SA9
lOW
OWS
Decoder
veso
Note: Example implementation, actual may vary.
217
W
I
......
~
I ~6Kbit I
VeS1
........
~
VAO-14
lOR
RESET
I
L
L
t
es
-
Optional
~
I WE
~4Kbi1
ABO-AB19
loes
-L./
--
-
VWE
-
lOW
lOR
RESET
VDO-?
READY
DBO-OB7
SA10-SA15
I
VAO-14
I
L-~~0-D15
WE
~6Kbit
cs
AB16-AB19
M/iO
BHE
-00
t
-
VWE
lOW
Decoder
A16
VDO-7
lOR
W
L
I
I
SED1352FoA
Interface with 16-bit ISA Bus and 128Kbytes SRAM (1 of 128K x 8)
SED1352
16-Bit ISA Bus
REFRESH
SA16~
I
Decoder
MEMCS
VWE
SMEMW
MEMW
SMEMR
MEMR
r-----c
WE
~-
READY
10CHROY
500-5015
SAO-SA19
1-Mbit
OBO-OB1S
SA10-SA1S
AEN
~
SA(10r4) to SA9
ABO-AB19
lacs
VCSO I - - ---+\
LB
VCS1
DB
~
lOW
lOW
-
lOR
lOR
BHE
SBHE
-RESET .
....... ~ RESET
IOCS16
LA17-LA23
MEMCS16
Decoder
I
VAO-1S
AO-15
VOO-7
I/O 1-8
VOS-1S
1/09-16
~
Note: Example implementation, actual may vary.
•
SUPPORTED RESOLUTIONS
Display
RAM
8 Kbyte
Example Display Size
4 Grays
y
x
16 Grays
x
Y
256 x 128
128 x 128
SRAM
Type
1 of 8Kx8
CPU
Interface
SRAM
Interface
8-bit
8-bit
8-bit
8-biV16-bit
16 Kbyte
320 x 200
200 x 160
2 of 8Kx8
16-bit
16-bit
32 Kbyte
512 x 256
256 x 256
1 of 32Kx8
8-bit
8-bit
8-bit
8-bit
40 Kbyte
512 x 320
320 x 256
1 of 8Kx8 and
1 of 32Kx8
64 Kbyte
512 x 512
512 x 256
2 of 32Kx8
128 Kbyte
1024 x 512
512 x 512
1 of 64Kx16
218
8-bit
8-biV16-bit
16-bit
16-bit
16-bit
16-bit
SED1352FoA
•
BLOCK DIAGRAM
lOR, lOW, IOCS,
MEMCS, MEMR,
MEMW,BHE
AB[19:0]
r-------,
'----;::==:::;-+- LCDENB
Bus
Signal
Translation
UD[3:0]
LD[3:0]
LP,YD,
rc----'--------,
READY
WF
I
DB[15:0] -------------~
0
•
•
(fl
Q
()
(fl»
()':l
9~
'"
~I£
.g<
01
.9
DC SPECIFICATIONS
Absolute Maximum Ratings
Parameters
•
~I ~I <1<
0
(fl
Symbol
Rating
Units
Supply voltage
Voo
Vss -0.3 to +6.5
V
Input voltage
VIN
Vss-O.3 to Voo +0.3
V
Output voltage
VOuT
Vss-O.3 to Voo +0.3
Ambient temperature
TA
-55 to 125
V
DC
Storage temperature
Tstg
-65 to 150
DC
Solder temperature/time
TSOL
260 for 10 sec. max at lead
DC
Recommended Operating Conditions
Symbol
Conditions
Min.
Typ
Max.
Units
Supply voltage
VOO(l)
4.5
5.0
5.5
V
Supply voltage
VDO(2)
=OV
Vss =OV
2.7
3.0
3.3
V
Input voltage
VIN
Vss
Voo
Junction temperature
Tj
0
-
115
V
DC
TOPR
0
25
70
DC
Parameter
Operating temperature
Vss
219
SED1352FoA
•
Input Specifications
Parameter
•
Symbol
Conditions
Low level input voltage
CMOS inputs
TTL inputs
Min.
VIL
Voo = Min
Low level input voltage
CMOS inputs
TTL inputs
VIH
Voo= Max
Positive going threshold
CMOS Schmitt inputs
TTL Schmitt inputs
VT+
Voo= 5.0
Negative going threshold
CMOS Schmitt inputs
TTL Schmitt inputs
VT-
Voo= 5.0
0.8
0.6
V
V
Hysteresis voltage
CMOS Schmitt inputs
TTL Schmitt inputs
VH
Voo= 5.0
0.3
0.1
V
V
Input leakage current
liz
Voo= MAX
VIH = Voo
VIL = Vss
Input pin capacitance
CIN
Typ
Max.
Units
1.0
0.8
V
V
3.5
2.0
V
V
4.0
2.4
-1
1
4
V
V
~
pF
Pull down resistance
HRpo
Voo =5.0 V
VI = Voo
Pull down resistance
LRpo
Voo =3.3 V
VI= Voo
90
180
360
KQ
Symbol
Conditions
Min.
Typ
Max.
Units
Vss + 0.4
V
50
100
180
KQ
Output Specifications
Parameter
Low level output voltage
Type 2 - TS2, C02, TS201
Type 3- TS3
Type 4 - TS4, 004
VOL
High level output voltage
Type 2 - TS2, C02, TS201
Type 3- TS3
Type 4 - TS4, 004
VOH
Output leakage current
loz
Output pin capacitance
COUT
6
pF
Bidirectional pin capacitance
CSIO
10
pF
10L = 6 mA
10L = 12 mA
10L= 24 mA
IOL=-2 mA
10L=-4 mA
10L =-8 mA
Voo= MAX
VOH = Voo
VOL = Vss
220
V
Voo - 0.4
-1
1
~
SED1352FoA
•
SED1352 PIN OUTS
LL
tl.
3: -'
XSCL
LCDENB
VOE
IOCS
lOW
lOR
MEMCS
MEMW
MEMR
READY
BHE
OSC1
OSC2
DBO
DB1
DB2
DB3
DB4
DB5
DB6
0
-'
0
:::>
Cii
:;;:
u
>
>
SED1352
•
221
.....
0
>
0
>
VD6
VD5
VD4
VD3
VD2
VD1
VDO
VA10
VA9
VAS
VA?
VA6
VA5
VA4
VA3
VA2
VA1
VAO
RESET
AB19
co
I
SED1352FoA
•
PIN DESCRIPTION
Key
Analog
Input
Output
Bi-directional
Power
A
I
o
I/O
P
Bus Interface
Pin Name
Type
Pin #
DBO-DB15
I/O
94 - 100,
1,4-11
ABO
I
12
AB1-AB19
I
13 - 31
BHE#
I
91
Description
These pins are connected to the system data bus. In 8-bit bus mode,
DB8-DB15 must be tied to VDD.
In MC68000 MPU interface, this pin is connected to the Lower Data Strobe
(LDS#) pin of MC68000. In other bus interfaces, this pin is connected to
the system address bus.
These pins are connected to the system address bus.
In MC68000 MPU interface, this pin is connected to the Upper Data Strobe
(UDS#) pin of MC68000.
In other bus interfaces, this pin is the Bus High Enable input for use with
16-bit system. In 8-bit bus mode, tie BHE# input to VDD.
10CS#
I
84
Active low input to select one of fifteen internal registers.
10W#
I
85
In MC68000 MPU interface, this pin is connected to the RIW# pin of
MC68000.
This input pin will define whether the data transfer is a read (active
high) or write (active low) cycle. In other bus interfaces, this is the
active low input to write data into an internal register.
10R#
I
86
MEMCS#
I
87
In MC68000 MPU interface, this pin is connected to the AS# pin of MC68000.
This input pin will indicate a valid address is available on the address
bus. In other bus interfaces, this is the active low input to read data
from an internal register.
Active low input to indicate the attempt to access the display memory.
MEMW#
I
88
Active low input to write data to the display memory.
MEMR#
I
89
Active low input to read data from the display memory.
READY
0
90
For MC68000 MPU interface, this pin is connected to the DTACK# pin of
MC68000 and will be driven low whenever a data transfer is complete. In other
bus interfaces, this output is driven low to force the system to insert wait states
when needed. READY is released to high-Z after the transfer is completed.
RESET
I
32
Active high input to force all signals to their inactive states.
222
SED1352FoA
Display Memory Interface
Pin Name
Type
Pin #
VDO-VD15
I/O
44-51,
54-61
These pins are connected to the display memory data bus. For 16-bit
interface, VDO-VD7 are connected to the display memory data bus of even
byte addresses and VD8-VD15 are connected to the display memory data bus
of odd byte addresses. The output drivers of these pins are placed into a highZ state when RESET is high. On the falling edge of RESET, the values of VDOVD15, each with internal pull-down resistor, will be latched into the chip to
configure various hardware options.
Description
VAO-VA15
0
33-43,
62-66
These pins are connected to the display memory address bus.
VCS1#
0
69
Active low chip-select output to the second or odd byte address SRAM.
VCSO#
0
68
Active low chip-select output to the first or even byte address SRAM.
VWE#
0
67
Active low output used for writing data to the display memory.
VOE#
0
83
See display memory interface section for details.
See display memory interface section for details.
This pin is connected to the WEI input of the SRAMs.
Active low output to enable reading of data from the display memory.
This pin is connected to the OE# input of the SRAMs.
LCD Interface
Pin Name
Type
Pin#
UD3-UDO
0
70 -73
Description
LD3-LDO
0
74 -77
Lower panel display data for dual panel mode. For 8-bit single panel
mode, these bits are the least significant 4 bits of the 8 bits output data
to the panel (PD[0:3]).
XSCL
0
81
Display data shift clock. Data is shifted into the LCD X-drivers on the falling
edge of this signal.
LP
0
79
Display data latch clock. The falling edge of this signal is used to latch a row
of display data in the LCD X-drivers and to turn on the row driver (Ydriver).
WF
0
0
80
LCD AC-drive signal output.
YD
78
Vertical scanning start pulse. A logic '1' on this signal, sampled by the LCD
module on the falling edge of LP, is used by the panel row driver (Y driver)
to indicate the start of the vertical frame.
LCDENB
0
82
LCD enable signal output. It can be used externally to turn off the panel
supply voltage and backlight.
Upper panel display data for dual panel mode. For single panel mode,
these bits are the most significant 4 bits of the 8 bits output data to the
panel (PD[4:7]).
For 4-bit signel panel mode, these bits are the 4 bits of output data to the panel.
For 4-bit signel panels, these bits are driven 0 (low state).
223
I
SED1352FoA
Clock Inputs
Pin Name
Type
Description
Pin#
OSC1
I
92
This pin, along with OSC2 is the 2-terminal crystal interface when using a 2terminal crystal as the clock input. If an external oscillator is used as a clock
source, then this pin is the clock input.
OSC2
0
93
This pin, along with OSC1 is the 2-terminal crystal interface when using a 2terminal crystal as the clock input. If an external oscillator is used as a clock
source, then this pin should be left unconnected.
Power Supply
Pin Name
Description
Type
Pin#
VDD
P
3,53
Voltage supply.
Vss
P
2,52
Voltage ground.
224
SED1352FoA
Illustrated below are the display data output which are output from the UDO to UD3, LDO/UD4 to LD3/UD7
and the display on the panel:
UD31UD21UD1IUDOI
Dual Panel- Top
8-bit Single Panel
LD31LD21LD1ILDOI
Dual Panel - Bottom
I
4-bit Single Panel
•
LCD PANEL PIXELS
r
I~
640 DOTS
1-1
2-1
! 1-2
1 2-2
!
!1-639!1-640
1
12-6391 2-640
24 o LINES
UPPER LCD PANEL
!240-639!240-640
1241-6391241-640
240-1 !240-2 !
241 - 1 1 241 - 2 1
(TOP VIEW)
24 o LINES
L_
LOWER LCD PANEL
480-1 !480-2!
!480-639!480-640
225
SED1352FoA
•
MONOCHROME PASSIVE STN LCD PANEL INTERFACE
LP : 240 PULSES
LP: 4 PULSES
_______~_I~------·_I~
YD
LP
WF
UD[3:0]
LINE 239
LINE 240
LINE 1
LINE 2
UD3---··~-----·~··~
UD2
.. ~-----.~ .. ~
UD1
.. ~-----.~ .. ~
UDO
.. ~-----.~ .. ~
Example timing for 320 x 240 single panel
226
SED1352FoA
•
MONOCHROME PASSIVE STN LCD PANEL INTERFACE
LP : 480 PULSES
YD
LP : 4 PULSES
_______~-I~------~--I~
LP
WF
UD[3:0], LD[3:0]
LINE 479
LINE 480
LINE 1
LINE 2
UD3------~------~--~
UD2
--~------~--~
UD1
--~------~--~
UDO
--~------~--~
LD3
--~------~--~
LD2
--~------~--~
LD1
LOO
~------~--~
--~------~--~
Example timing for 640 x 480 panel
227
I
SED1352FoA
•
MONOCHROME PASSIVE STN LCD PANEL INTERFACE
LP : 240 PULSES
YD
LP : 2 PULSES
_______._I_·______
·~I~
LP
WF
UD[3:0], LD[3:0]
LP
WF
LINE 11241
LINE 2/242
1
-----4"""'.
UNE3/243
LINE4I244
,,"-"'"
UNE2391479 LlNE2401480
"-OCK
"eo,,,'
LINE 1/241
LINE 21242
>1
XSCL _ _ _ .. ~ ______ ~.~
UD3---··~------~··~
.. ~------~ .. ~
UD2
.. ~------~ .. ~
UDO---··~------~··~
LD3---··~------~--~
LD2---··~------~··~
LD1---··~------~··~
LDO---·-~------~-·~
UD1
Example timing for 640 x 480 panel
228
SED1352FoA
•
PACKAGE DIMENSIONS
QFP5-100-S2 100 pin
Unit: mm
23.2 ± 0.04
..
20.0 ± 0.1
o
+1
o
"-:=
>->->->--
4'
40
i=
70
SED1200F
75
:=,
COM9
~
ai
__ §~~~w~
2
~~m~~~~~~~m~~~m~m8 g 88
~~~2
v""
VLCD
v"
DBO
DB'
r--< DB2
r--< DBS
r--< osc,
r--< OSC2
r--<
~
'or--< WR
r--<
111111111111111111111111
--------~
~
~
r--<
24~
~w~.~N-o~~~8~~~N
I
AIJ
COM8
+
Common Driver
i I
COMl
I-I
COM16
I >------j LCD Poweri Supply I
I LCD Power Divider
Segment Driver
1 1
SEG50
•
50
I Common Generator I
10 x 2 words
(160 bits)
Segment Signal Generator I
J
Dala Controller
60
11
1
DDRAM
CGROM 160 words
PINOUT
64
Address Counter I
Address Controller
r
SEGl
•
TIming Generator I
Write/Read
Controller
CGRAM 5 x adots x 4
(160 bns)
Wrne/Read Controller
L
_f
1
Register
I
Latch
1
Oscillator
r-L Address Counter
~.-oo
RO
CS
L
vss V DD
PIN DESCRIPTION
Pin No. Pin Name I/O
18 to 25 COM1 to
0
40 to 47 COM16
17 to 1 SEG1 to
0
80 to 48 SEG50
I
27
CS
1
28
RD
Functions
LCD Common output
LCD Segment output
Chip select input (active "Low")
Read enable input (active "Low")
Write enable input
29
WR
I
(active "Low" to "High")
"High"; Set character code,
AO
1
26
"Low"; Command
DBOto
Data input
36 to 33
I, I/O
DB3
(except DB3; Data input/output)
30
1 Clock for command
OSC1,
Connect oscillation resistor'
32,31
OSC2
VDD
39
- Supply voltage (+5V) for logic
37
Vss
- GND (OV)
38
VLCD
- Supply voltage for LCD
-
, If an external clock is used, it should be connected to OSC1
and leave OSC2 open.
238
SED1200
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
(Vss
= OV)
Symbol
Rating
Supply voltage (1)
VDD
-0.3 to +7.0
Unit
V
Supply voltage (2)
VLCD
VDD-7.0 to VDD+0.3
V
Input voltage
VI
-0.3 to VDD+0.3
V
Output voltage
Va
-0.3 to VDD+0.3
V
Operating temperature
Topr
-10to+70
Storage temperature
Tstg
-40 to +150
°C
°C
I
239
SED1200
•
DC Electrical Characteristics Parameter
VDD
=5V
Symbol
Voo = 5V, Vss = OV, Ta = -10 to +70°C
Conditions
Terminal
Min
Typ
Max
Unit
5.0
5.5
V
Logic supply voltage
Voo
Voo
4.5
Liquid crystal display
supply voltage
VLCO
VLCO
Voo-5.5
240
Oscillator feedback resistor
-
Voo-3.5
V
310
3SO
kQ
-
100
300
kHz
MHz
RI
Voo = 5.0V, losc = 100 kHz
OSC1,OSC2
Operating frequency (1)
oscillator or external
clock frequency
fosc
Voo = 4.5 to 5.5V
OSC1,OSC2
Operating frequency (2)
<\>
Voo = 4.5 to 5.5V
<\>
-
-
3.2
Voo = 4.5 to 5.5V
OSC1,<\>
45
50
55
%
tr
Voo = 4.5 to 5.5V
OSC1,<\>
-
-
50
ns
External clock duty
External clock rise time
tl
Voo = 4.5 to 5.5V
OSC1,<\>
-
-
50
ns
H-Ievel input voltage (1)
VIH1
Voo = 4.5 to 5.5V
2.0
V
VIL1
Voo = 4.5 to 5.5V
-
Voo
L-Ievel input voltage (1)
CS. RO. WR.
OBOto OB3.
H-Ievel input voltage (2)
VIH2
Voo = 4.5 to 5.5V
External clock fall time
L-level input voltage (2)
VIL2
Voo = 4.5 to 5.5V
H-Ievel input leakage
current
IUH
Voo = 5.5V, VIH = 5.5V
L-Ievel input leakage
current
IUL
Voo
V
0
0
0.2 Voo
V
-
-
1.0
IlA
3.0
10
30
IlA
1-1.01
-
-
mA
1.6
-
-
mA
COM1 to
COM16
1-201
-
-
IlA
COM1 to
COM16
20
-
-
j.lA
COM1 to
COM16
1±81
-
-
j.lA
COM1 to
COM16
1±81
-
-
IlA
SEG1 to
SEG50
1-121
-
-
IlA
SEG1 to
SEG50
12
-
-
IlA
VL21evei
SEG1 to
SEG50
1±41
-
-
IlA
VL31evei
SEG1 to
SEG50
1±41
-
-
IlA
Voo = 5.5V, VIL = OV
10H
Voo = 4.5 to 5.5V,
VOH = 2.4V
10L
Voo = 5.5V,
VOL = O.4V
Common driver output
current (1)
10H
Voo level
Common driver output
current (2)
10L
VLCO level
Common driver output
current (3)
10L
VLt level
VL41evei
Segment driver output
current (1)
10H
Voo level
Segment driver output
current (2)
10L
VLCO level
10L
Voo
IlA
H-Ievel output current
Segment driver output
current (3)
V
O.S Voo
H.OI
Voo = 5.0V, VIL = OV
10L
O.S
-
lipu
Common driver output
current (4)
OSC1
0
-
Input pull-up current
L-Ievel output current
ill
Voo = 4.5V
VLCO = 1.0V
Voltage-divider
resistor in low
impedance state.
1/16 duty
0.5V voltage drop.
Measured on one
pin with other pins
open circuit.
<\>,OSC1,
DBOto
DB3
CS, RD,
WR,AO
DB3
Segment driver output
current (4)
10L
Voltage-divider resistor (1)
Rdt
Normal conditions
30
130
300
kQ
Voltage-divider resistor (2)
Rd2
Low impedance state
3.0
13
30
kn
tRd1/tRd2
1/S Duty
1116 Duty
-
-
tcomd
From WR rising edge to the
end 01 internal processing
100
Voo = 5.0V, VLCO = OV,
losc = 100kHz,
<\>= 1MHz,
CS = RD = WR = AD = 5.0V,
output open
Voltage-divider resistor
low impedance duty
Command execution time
Average operating current
-
240
VOD
11/400
11/200
-
-
-
SO
16/<\>
(MHz)
Ils
150
j.lA
SED1200
•
DC Electrical Characteristics - Voo = 3V
Voo=3V, Vss= OV, Ta=-10to+70°C
Parameter
Symbol
Voo
Logic supply voltage
Liquid crystal display
VLCO
supply voltage
Oscillator feedback resistor
RI
Operating frequency (1)
oscillator or external
fosc
clock frequency
Operating frequency (2)
External clock duty
External clock rise time
tr
External clock fall time
tl
H-Ievel input voltage (1)
VIH1
L-Ievel input voltage (1)
VIL1
H-Ievel input voltage (2)
VIH2
L-Ievel input voltage (2)
VIL2
H-Ievel input leakage
ILIH
current
L-Ievel input leakage
IUL
current
Input pull-up current
hpu
H-Ievel output current
10H
L-Ievel output current
Common driver output
current (1)
Common driver output
current (2)
Common driver output
current (3)
Common driver output
current (4)
Segment driver output
current (1)
Segment driver output
current (2)
Segment driver output
current (3)
Segment driver output
current (4)
Voltage-divider resistor (1)
Voltage-divider resistor (2)
Voltage-divider resistor
low impedance duty
Conditions
Terminal
Voo
Min
2.5
Typ
3.5
Max
4.5
Unit
V
VLCO
Voo-5.5
-
Voo-3.5
V
Voo = 3.0V, fosc = 100 kHz
OSC1,OSC2
2210
290
370
kn
Voo =2.5V
OSC1,OSC2
-
-
300
kHz
Voo= 2.5V
Voo =2.5V
Voo =2.5V
Voo =2.5V
Voo =2.5V
Voo= 2.5V
Voo= 2.5V
Voo =2.5V
OSC1,
OSC1,
OSC1,
CS,RO,WR,
-
-
1.0
VLCO level
10L
VL1 level
10L
VL41evei
10H
Voo level
10L
VLCO level
10L
VL2level
10L
VL3level
Average operating current
100
WR,AO
Voo= 2.5V,
VOH =2.0V
Voo= 2.5V,
VOL = 0.5V
10L
Icomd
eg, RD,
Voo =3.5V
Voo level
Command execution time
,OSC1,
DBOto
DB3
Voo =4.5V
10H
tRd1/tRd2
OSC1
Voo =4.5V
10L
Rd1
Rd2
080 to 083,
m
-
-
0.2Voo
MHz
%
ns
ns
V
V
V
V
-
-
H.OI
I1A
-
-
1.0
!1A
1.0
4.0
15
I1A
200
-
-
mA
200
-
-
mA
1-201
-
-
!1A
20
-
-
!1A
1±81
-
-
!1A
1±81
-
-
!1A
1-121
-
-
!1A
12
-
-
!1A
1±41
-
-
!1A
1±41
-
-
!1A
-
130
13
-
kn
kn
0.8 Voo
0
0.8Voo
50
-
-
50
50
Voo
0.2Voo
-
DB3
Voo - VLCO= 3.5V
Voltage-divider
resistor in low
impedance state.
1/16 duty
0.5V voltage drop
Measured on one
pin with other pins
open circuit.
Normal conditions
Low impedance state
1/8 Duty
1116 Duty
From WR rise time to the
end of internal processing
Voo - Vss = 3.5V,
Voo - VLCO = 1.5V,
fosc = 100kHz, = 500 kHz,
CS = RD = WR = AO = Voo,
output open
241
COM1 to
COM16
COM1 to
COM16
COM1 to
COM16
COM1 to
COM16
SEG1 to
SEG50
SEG1 to
SEG50
SEG1 to
SEG50
SEG1 to
SEG50
-
-
Voo
-
-
16/<1>
(MHz)
!1S
-
60
150
!1A
11/400
111200
-
-
I
SED1200
• AC Electrical Characteristics
o MPU Read Timing
AO----..
CS------..
tCR
RD
1 " - - - tRP ---j."1
tRH
tRD
DB3
-{~~-}2.4V
.
Busy flag
----. 0.4V
(AO, CS, RD, Ill) _ _ _ _ _ _ _~tl~nl"·l-
11____
ir2.0~
~Yo~8V
VDD = 4.5 to 5.5V, Ta = -10 to 70°C
Parameter
Symbol
Condition
Min
Typ
Setup time for AO ~ RD
tAR
0
Setup time for CS ~ RD
tCR
RD delay output time
tRD
-
Input fall time
tl
-
Input rise time
tr
-
Hold time for RD
~
AO
tRA
Hold time for RD
~
CS
tRC
Data hold time
tRH
Read pulsewidth
tRP
0
20
20
10
350
-
Max
Unit
-
ns
250
ns
-
ns
50
ns
50
ns
ns
ns
ns
ns
Note: Load on pin DB3 is CL = 100 pF.
VDD = 2.5 to 4.5V, Ta = -10 to 70°C
Parameter
Min
Typ
RD
tAR
-
0
Setup time for CS ~ RD
tCR
-
0
RD delay output time
tRD
-
Hold time for RD ~ AO
tRA
Setup time for AO
Hold time for RD
~
~
Symbol
CS
Condition
-
-
tRC
Data hold time
tRH
Read pulsewidth
tRP
Input fall time
tf
Input rise time
tr
Note: Load on pin DB3 is CL = 100 pF.
242
0
0
10
400
-
-
-
Max
Unit
-
ns
-
ns
350
ns
-
ns
-
ns
50
ns
50
ns
ns
ns
SED1200
o
MPU Write Timing
AO
--------------------------~
y-----------------~
CS
DBO to DB3 - - - - + - - - - - - - ( 1
-
tew
WR ---------";[
WR
Cycle time
I
(AO,CS, WR
DBO to DB3, <1»
Voo = 5V, Ta = -10 to 70°C
Symbol
Condition
Min
Typ
WR setup time
tAW
0
-
CS -4 WR setup time
tew
0
-
Data setup time
tos
-
120
WR -4 AO hold time
tWA
-
20
WR -4 CS hold time
twe
20
Data hold time
tOH
-
Write pulsewidth
twp
-
tw1W2
Parameter
Max
Unit
ns
-
-
ns
200
-
-
200
-
-
ns
tweye
-
16/<1>
(MHz)
-
-
ns
Input fall time
tf
50
ns
tr
-
-
Input rise time
-
50
ns
AO
-4
Upper write pulse rising edge to
lower write pulse falling edge time
Lower write pulse rising edge to
upper write pulse falling edge time
20
-
ns
ns
ns
ns
ns
VOO = 3V, Ta = -10 to 70°C
Parameter
Symbol
Condition
Min
AO -4 WR setup time
tAW
0
-
CS -4 WR setup time
tew
-
Typ
0
-
Data setup time
tos
120
WR -4 AO hold time
twA
WR -4 CS hold time
twe
-
Data hold time
tOH
twp
-
Upper write pulse rising edge to
lower write pulse falling edge time
tw1W2
Lower write pulse rising edge to
upper write pulse falling edge time
Max
Unit
-
ns
ns
200
-
-
-
200
-
-
ns
tweye
-
16/<1>
(MHz)
-
-
ns
Input fall time
tf
-
-
50
ns
Input rise time
tr
-
-
-
50
ns
Write pulsewidth
243
0
0
100
ns
ns
ns
ns
ns
SED1200
.. AC Characteristics (Write cycle)
Parameter
•
o
(VOO = 5V±10%, Vss
Symbol
=OV, Ta =-10 to +70°C)
Rating
Condition
Typ
Max
-
-
ns
-
ns
-
ns
-
ns
-
ns
AO setup time to WR
tAw
0
CS setup time to WR
tew
0
Data setup time
tos
120
AO hold time after WR
twA
20
CS hold time after WR
twe
20
Data hold time
tOH
20
Write pulse width
twp
200
Input fall time
tHL
Input rise time
tLH
-
Timing Chart
Read cycle
AO
~~--------------------~f
~IAR
lRA~,..----
DB3
O.4V
2.0V
Inpui _
es, RO, eLK)
(AO,
o Write cycle
AO ________________J~----------~~-
DBO to DB3
-+--i==~!---_+--i==~
WR
InpYl. - = : - - - - - es, WR,
li
eLK)
IHL....j ~
(AO,
OBO 10 OB3,
244
Unit
Min
ns
-
ns
50
ns
50
ns
SED1200
•
o
DC Characteristics
VDD = 5V
(Vss = OV, Ta = -10 to +70°C)
Parameter
Symbol
Rating
Condition
Min
logic operating voltage
VDD
4.5
LCD operating voltage
VLCD
VDD-5.5
Typ
5
-
Unit
Max
5.5
V
~DD-3.5
V
RI
VDD=5V, fosc=100kHz
380
kQ
Input voltage; High (1)
VIHI
VDD=4.5 to 5.5V
*1
2.0
-
VDD
V
Input voltage; low (1)
VILI
VDD=4.5 to 5.5V
*1
0
-
0.8
V
Input leakage current; High
IUH
-
1.0
I-l A
Input leakage current; low
IUL
VDD=5.5V, VIL=OV
-
-
1.0
I-l A
Input voltage; High (2)
VIH2
VDD=4.5 to 5.5V
*30.8VDD
VDD
VDD
V
Input voltage; low (2)
VIL2
VDD=4.5 to 5.5V
*3
0
0
0.2VDD
Output current; High
IOH
VOD=5V, VOH=2.4V
*4
1.0
-
Output current; low
IOL
VDD=5V, VOL=O.4V
*4
1.6
-
-
Input pull up current
IIPu
VIL=OV, VOD=5V
*5
3
10
30
I-l A
Resistor as power divider
Rd
30
130
300
kQ
-
100
300
kHz
-
3.2
MHz
-
80
150
I-l A
-
-
16/ClK
Resistor for oscillator
Operating frequency (1)
fosc
Operating frequency (2)
ClK
Operating current
Command execution time
IDD
240
VDD=5.5V, VIH=5.5V *2
*2
VDD=4.5 to 5.5V
VDD=4.5 to 5.5V
VDD=5V, VLCD=OV
*6
fosc=100KHz, ClK=1 MHz
tCOMD
310
(MHz)
V
mA
mA
I-ls
Common output current (1)
IloH VDDCI
VDD=4.5V
20
-
IOL VLCOC
VLCD=1.0V
20
-
-
I-l A
Common output current (2)
Common output current (3)
IIOL VL1cl
1/16 duty drive
8
-
-
I-l A
8
-
-
I-l A
12
-
-
I-l A
12
-
-
I-l A
Common output current (4)
Segment output current (1)
IloL VL4CI
IloL VDDSI
Voltage drop by 0.5V
When one terminal is measured, the others are open.
Segment output current (2)
IOL VLCDS
Segment output current (3)
IIOL VL2S1
4
Segment output current (4)
IloL VL3S1
4
I-l A
I-lA
I-lA
*1. Terminal: CS, RD, WR, AO, DBO to DB3, ClK
*4. Terminal: DB3
*2. Terminal: ClK, OSC1, DBO to DB3
*5. Terminal: CS, RD, WR, AO
*3. Terminal: OSC1 (for external clock)
*6. CS = RD = WR = AO = 5.0V, (open output terminals)
245
I
SED1200
•
DISPLAY COMMAND
2nd input
1st input
Command Name
CSWRRD AO 0B3 OB2 OB1 OBO OB30B20B1 OBO
Note
(07) (06) (05) (04) (03) (02) (01) (DO)
0/1
00=1: Oecrement
00=0: Increment
00-1:-1
00=0: +1
00=1: All dots blinking
00=0: Under line
00_1: ON
00=0: OFF
00=1: ON
00=0: OFF
00=1: ON
00=0: OFF
SET CURSOR DIRECTION
0
0
1
0
0
0
0
0
0
1
0
CURSOR ADDRESS -1/+1
0
0
1
0
0
0
0
0
0
1
1 -1/+1
CURSOR FONT SELECT
0
0
1
0
0
0
0
0
1
0
0
CURSOR BLINK ON/OFF
0
0
1
0
0
0
0
0
1
0
1 ON/OFF
DISPLAY ON/OFF
0
0
1
0
0
0
0
0
1
1
o ON/OFF
CURSOR ON/OFF
0
0
1
0
0
0
0
0
1
1
1 ON/OFF
SYSTEM RESET
0
0
1
0
0
0
0
1
0
0
0
0
Except data RAM and CGRAM
LINE SELECT
0
0
1
0
0
0
0
1
0
0
1
211
00=1: 2 line display (1/16 duty)
00=0: 1 line display (1/8 duty)
0
0
1
0
1
0
(N figure-1) B
0
0
1
0
1
1
(N figure-1) B
SET CHARACTER CODE
0
0
1
1
(CHARACTER CODE)
BUSY FLAG CHECK
0
1
0
0 BF
... .. .
SET CGRAM ADDRESS
0
0
1
0
0
0
SET CGRAM DATA
0
0
1
0
0
1
SET CURSOR
ADDRESS
I
1s1 LINE
1 2nd LINE
AlU
BF
07(03)-1: Busy
07(03)=0: Not Busy
1 0 (Sellower address
0 (Sel CGRAM data)
• =High impedance
Note: Misoperation may be caused when any command other than that listed in the above table is inputted.
246
SED1200
•
APPLICATION FOR CPU
The SED1200 can connect to the address bus or the data bus directly, as shown below.
Out port
Out port
Out port
Out port
Out port
Out port
Out port
I/O port
..
AO
RD
WR
CS
DBO
DB1
DB2
DB3
Clock - - - . ClK
~
~
...
..
~
SED1200
4/8 bit CPU
248
SED1200
•
SED1200F PACKAGE DIMENSIONS
Plastic QFP1-80 pins
SED1200FoB
0.992 ± 0.016 (25.2 ± 0.4)
I
0.102
(2.6)
Plastic QFP14-80 pins
SED1200F1B
0.551 ±o.o16
(14.0 ±o.•)
0.472 ± 0.004
(12.0 ±O.l)
249
SED1200
•
SED1200D PACKAGE DIMENSIONS
Chip size:
Chip thickness:
Pad size:
Pad pitch:
•
5.86 mm x 3.41 mm
0.40 mm x 0.03 mm
0.90 mm x 0.90 mm
0.19 mm
PAD LAYOUT
4,500
4
24
•
1
••••••••••••••••••••
25
80
•
V
•
•
• 0r-• co
• C'i
(0,0)
•
•
::::::::---• V r•
••••••••••••••••••• 65
Lx
40
64
41
250
Monitor Pad
SED1200
•
PAD COORDINATES
unit:
(~m)
Pad No.
Pad Name
X(~m)
y
1
2
3
4
5
6
7
8
9
10
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
2123
1932
1742
1551
1361
1170
980
789
599
408
218
27
-163
-354
-544
-735
-925
-1116
-1306
-1497
-1687
-1878
-2068
-2259
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
-2778
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1552
1429
1238
1048
857
667
476
286
95
-95
-286
-476
-667
-857
-1048
-1238
-1429
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AO
CS
RO
WR
OSC2
OSC1
03
02
01
00
Vss
VLCD
VDD
COM9
251
~m
(~m)
Pad No.
Pad Name
X (~m)
y
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
-2220
-2029
-1839
-1648
-1458
-1267
-1077
-886
-696
-505
-315
-124
66
257
447
638
828
1019
1209
1400
1590
1781
1971
2162
2777
2777
2777
2777
2777
2777
2777
2777
2777
2777
2777
2777
2777
2777
2777
2777
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1552
-1385
-1195
-1004
-814
-623
-433
-242
-52
139
329
520
710
901
1091
1282
1472
I
THIS PAGE INTENTIONALLY BLANK
252
SED1210
CMOS DOT MATRIX LCD CONTROLLER DRIVER
•
DESCRIPTION
The SED1210 is a character LCD controller-driver, capable of driving displays as large as 2 lines of 8
character (5 x 8 pixels), with minimum external components.
The SED121 0 has an internal CGROM consisting of 160 characters (5 x 7) plus the underline cursor, JIS,
ASCII, and four user-programmable characters in RAM.
The SED121 0 has 40 segment output and 16 common output built-in. Thus, one chip is capable of displaying
up to 16 characters. The SED121 0 can display one line of 40 characters using an SED1181 FLA (64 bits) as
an expansion segment driver.
The SED1210 is fabricated using a silicon gate CMOS technology process and features very low power
dissipation. This makes the device suitable for handheld and portable applications.
•
FEATURES
• Low-power CMOS technology
• Built-in RC oscillator
• 40 segment output
• Built-in LCD driver voltage-divider network
• 16 common output
• TTL compatible CPU interface
• Duty: 1/8 or 1/16 (set by command)
• Supply voltage .............. Logic: 2.5V to 5.5V
LCD: 3.5V to 5.5V
• 8-bit CPU data interface, TTL compatible
• Package ........................ QFP5-80 pins (FOB, FOA)
AI pad (DOA)
Au bump (DOB)
• 13 display control commands
• CGROM: 160 characters
• CGRAM: 4 characters
• Display data RAM: 40 x 8 bits (40 characters)
•
SYSTEM BLOCK DIAGRAM
SEGO-SEG49~
I
DATA
CPU
CONTROL
COMO-COM~
v
SED1210
253
8 CHAR x 2 LINES
I
SED1210
•
BLOCK DIAGRAM
V DD
Vss
~---.oSO
SEG40
OSC2
OSC1
SEG1
CGRAM
5x8dotsx4
(160 bits)
WR AD
AO
CS
O..-C\lC"l"
WR
RD
CS
5
10
15
20
25
~ID~~M~~omoo~m~vMN~~NMv~ID~
~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~WWWWWWWWWOOOOOOO
~~~~~~~~OOOOOOOOOOOOOOOOOOOOOOOOO
254
AD
COMB
SED1210
•
PIN DESCRIPTION
Pin Name
No.
Functions
Pin Name
No.
Functions
of Pin
COM1 to 16
LCD common output
16
SEG1 to 40
LCD segment output
40
CS
Chip select input (active "Low")
-
Read enable input
RD
Write enable input
-
WR
1
(active "Low" to "High")
"High" ; Display data
AO
1
"Low" ; Command
Data input
DBO to 7
(except DB7 ; Data input/output
Clock for command execution
•
•
OSC1,OSC2
2
SO
Serial output for Segment driver
1
LP
Latch output for Segment driver
1
SHCL
Shift clock for Segment driver
1
FR
Frame output for Segment driver
1
VL2, VL3
Supply voltage for Segment driver
2
VDD
Supply voltage (2.5V to 5.5V) for logic
1
Vss
GND (OV)
1
1
1
(active "Low")
of Pin
Connect oscillation resistor between OSC1 and OSC2. OSC1
also can be external clock input.
8
VLCD
1
Supply voltage for LCD
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
1
3.5V~VDD-VLCD~5.5V
(Vss = OV Ta = 25 DC)
Symbol
Rating
Unit
Supply voltage (1)
VDD
-0.3 to 7.0
V
Supply voltage (2)
VLCD
VDD-7.0 to VDD+0.3
V
Input voltage
VI
-0.3 to VDD+0.3
V
Output voltage
Va
-0.3 to VDD+0.3
V
Operating temperature
Topr
-20 to 70
DC
Storage temperature
Tstg
-65 to 150
DC
Soldering temperature and time
Tsol
260DC·10s (at lead)
255
-
I
SED1210
•
•
DC CHARACTERISTICS
VDD =5V
Parameter
Liquid crystal display
supply voltage
Oscillator feedback resistor
Vss = OV, Ta = -20 to +?O°C
Symbol
Condition
Min
VLCD
Rf
Typ
VDD - 5.5
VDD = 5.0V,
lose = 100kHz
240
310
Max
Unit
Pin
VDD-3.5
V
VLCD
380
kn
OSC1,OSC2
kHz
OSC1,OSC2
OSC1
Oscillator frequency
losc
VDD = 5.0V, Rf = 300kn
-
100
Operating frequency (1)
oscillator or ex1ernal
clock frequency
fosc
VDD =4.5V
-
-
300
kHz
Operating frequency (2)
<1>
VDD = 4.5 to 5.5V
-
-
3.2
MHz
<1>
VDD = 4.5 to 5.5V
45
50
55
%
OSC1, <1>
-
50
ns
OSC1, <1>
50
ns
OSC1, <1>
VDD
V
0.8
V
CS, RD, WR,
DBOto DB?,
<1>,AO
VDD
V
OSC1
External clock duty
External clock rise tirne
tr
VDD = 4.5 to 5.5V
-
External clock fall time
tf
VDD = 4.5 to 5.5V
-
VIH1
VDD = 4.5 to 5.5V
2.0
H-Ievel input voltage (1)
-
-
L-Ievel input voltage (1)
VIL1
VDD = 4.5 to 5.5V
0
H-Ievel input voltage (2)
VIH2
VDD = 4.5 to 5.5V
0.8 x VDD
VDD
L-Ievel input voltage (2)
VIL2
VDD = 4.5 to 5.5V
0
0
0.2
X
VDD
I
V
OSC1
j.!A
<1>,OSC1,
DBO to DB?
H-Ievel input leakage current
IUH
VDD = 5.5V, VIH = 5.5V
-
-
1-1.0
L-Ievel input leakage current
IUL
VDD = 5.5V, VIL = OV
-
-
1.0
j.!A
<1>,OSC1,
DBO to DB?
Input pull-up current
ilpu
VDD = 5.0V, VIL = OV
3.0
10
30
j.!A
CS, RD,
WR,AO
H-Ievel output current (1)
IOH1
VDD = 4.5 to 5.5V,
VOH = 2.4V
1-1.0
-
-
mA
DB?
L-Ievel output current (1)
10L1
VDD = 4.5 to 5.5V,
VOL = O.4V
1.6
-
-
mA
DB?
-
j.!A
FR, LP
j.!A
XSCL, SO
I
H-Ievel output current (2)
IOH2
VDD = 4.5V, VOH = 4.OV
200
-
L-Ievel output current (2)
IOL2
VDD = 4.5V, VOL = 0.5V
200
Common driver output current (1)
10H
VDD level
1-20
Common driver output current (2)
IOL
Common driver output current (3)
IOL
-
Common driver output current (4)
IOL
Segment driver output current (1)
10H
Segment driver output current (2)
IOL
Segment driver output current (3)
IOL
Voo - VLCD =
VLCD level 3.SV. Dividing
resistor in low
VL1 level
impedance
state. 1/16
VL41evei
duty. 0.5
VDD level voltage drop.
VLCD level Measured on
one pin with
VL21evei
other pins
IOL
VL31evei
IOH
VDD - VLCD = 3.5V
0.5V voltage drop
Segment driver output current (4)
Driver current
IOL
open circuit.
I
20
1±81
1±81
1-121
12
1±41
1±41
-
2
2
j.!A
j.!A
j.!A
j.!A
j.!A
j.!A
j.!A
j.!A
Rd1
Normal conditions
30
130
300
kn
Voltage-divider resistor (2)
Rd2
Low impedance state
3.0
13
30
kn
Voltage-divider resistor
low impedance duty
tRd1/
tRd2
1/8 duty
-
-
-
Command execution time
tcomd
From WR rising edge to
the end 01 internal
processing
-
-
IDD
VDD = 5.0V, VLCD = OV,
losc = 100 kHz,
<1> = 1 MHz, CS = RD =
WFl = AO = 5.0V,
output open
-
80
Average operating current
1/16 duty
256
11/200
SEG1 to
SEG40
j.!A
j.!A
Voltage-divider resistor (1)
11/400
COM1 to
COM 16
16/<1>
j.!s
150
j.!A
VL2, VL3
VDD
SED1210
•
Voo = 3V
Vss=OV, Ta=-20to+70°C
Parameter
Liquid crystal display
supply voltage
Oscillator feedback resistor
Symbol
Condition
Min
VLCD
Rt
VDD =3.0V,
fosc = 100kHz
3.5
210
Typ
Max
Unit
Pin
-
5.5
V
VLCD
290
370
kn
OSC1,OSC2
kHz
OSC1,OSC2
300
kHz
OSC1
1
Oscillator frequency
fosc
VDD = 3.0V, Rt = 300kn
-
100
Operating frequency (1)
oscillator or external
clock frequency
fosc
VDD= 2.5V
-
-
Operating frequency (2)
VDD = 2.5 to 4.5V
-
-
MHz
50
-
%
OSC1,
External clock duty
VDD = 2.5 to 4.5V
-
External clock rise time
tr
VDD = 2.5 to 4.5V
-
-
50
ns
OSC1,
Ex1ernal clock fall time
tt
VDD = 2.5 to 4.5V
-
-
50
ns
H-Ievel input voltage (1)
VIHI
VDD = 2.5 to 4.5V
-
-
V
L-Ievel input voltage (1)
VILI
VDD = 2.5 to 4.5V
V
OSC1,
CS, RD, WR,
DBOto DB7,
,AO
H-Ievel input voltage (2)
VIH2
VDD = 2.5 to 4.5V
0.8 x VDD
-
V
OSC1
L-level input voltage (2)
VIL2
VDD = 2.5 to 4.5V
-
-
0.8 x VDD
-
-
0.2
X
VDD
0.2
X
VDD
V
OSC1
H-Ievel input leakage current
IUH
VDD =4.5V
-
-
-
j.LA
,OSC1,
DBOto DB7
L-Ievel input leakage current
IUL
VDD =4.5V
-
-
-
j.LA
,OSC1,
DBOto DB7
Input pull-up current
ilpu
VDD = 3.5V
-
-
-
IlA
CS,RD,
WR,AO
H-Ievel output current (1)
10Hl
VDD= 2.5V,
VOH =2.0V
200
-
-
IlA
DB7
L-Ievel output current (1)
10Lt
VDD= 2.5V,
VOL = 0.5V
200
-
-
IlA
DB7
H-Ievel output current (2)
IOH2
VDD = 2.5V, VOH = 2.0V
200
-
j.LA
FR,LP
200
-
-
XSCL, SO
-
-
IlA
1-201
L-Ievel output current (2)
10L2
VDD = 2.5V, VOL = 0.5V
Common driver output current (1)
10H
VDD level
Common driver output current (2)
IOL
Common driver output current (3)
IOL
VLCD level 3.5V. Dividing
resistor in low
VLt level impedance
VL41evei state. 1/16
duty. 0.5
VDD level VOltage drop.
VLCD level Measured on
one pin with
VL2level other pins
VL31evei open circuit.
Common driver output current (4)
IOL
Segment driver output current (1)
IOH
Segment driver output current (2)
IOL
Segment driver output current (3)
10L
VOD -
VLCD
Segment driver output current (4)
IOL
Driver current (1)
IOH
Driver current (2)
IOL
Voltage-divider resistor (1)
Rdl
Normal conditions
Voltage-divider resistor (2)
Rd2
Low impedance state
Voltage-divider resistor
low impedance duty
tRdl1
tRd2
1/8 duty
Command execution time
tcomd
Average operating current
IDD
=
VDD - VLCD = 3.5V
0.5V VOltage drop
1/16 duty
20
1±81
1±81
1-121
12
1±41
1±41
-
-
-
-
-
-
2
2
130
13
11/400
11/200
From WR rise time to
the end of internal
processing
-
-
VDD - Vss = 3.5V,
VDD - VLCD = 5V,
= 500kHz,
CS = RD = WR =AO =
VDD, Rt = 300kn
-
60
257
-
16/<1>
-
j.LA
j.LA
j.LA
j.LA
j.LA
IlA
IlA
IlA
IlA
IlA
kn
COM1 to
COM16
SEG1 to
SEG40
VL2, VL3
kn
Ils
IlA
VDD
I
SED1210
•
•
AC CHARACTERISTICS
MPU Read Timing
RD------~
...
tRP ----l~~11 /
I
l----tRD
_
DB?
Input signal
(AD, CS, RD)
={
-----------------~~·tt
Jf
tRH
~
Busy flag
~~2_.4_V_ _ __
¥
O.4V
~jl~_tr_ __
2.0V
. 0.8V
Voo = 5V, Ta = -20 to ?O°C
Symbol
Condition
Min
Typ
Setup time for AD ~ RD
tAR
0
Setup time for CS ~ RD
tCR
RD delay output time*
tRO
-
-
-
Min
Typ
-
Parameter
AD
tRA
Hold time for RD ~ CS
tRC
Data hold time
tRH
Read pulsewidth
tRP
Hold time for RD
~
Input fall time
tf
Input rise time
tr
0
20
20
10
300
Max
-
Unit
ns
ns
200
ns
-
ns
50
ns
50
ns
ns
ns
ns
Note: Load on pin DB? is CL = 100 pF.
VOO = 3V, Ta = -20 to ?O°C
Parameter
Symbol
Condition
Setup time for AD ~ RD
tAR
-
0
Setup time for CS ~ RD
tCR
-
0
RD delay output time"
tRo
-
Hold time for RD ~ AO
tRA
Hold time for RD ~ CS
tRC
Data hold time
tRH
Read pulsewidth
tRP
-
Inputfall time
tf
Input rise time
tr
Note: Load on pin DB? is CL = 100 pF.
258
0
0
10
400
-
-
Max
Unit
-
ns
350
ns
-
ns
50
ns
50
ns
ns
ns
ns
ns
SED1210
•
MPU Write Timing
AO
DBO - DB7
WR
~~~+-----j~~~~~--<
~~----j~--'-~
Input signal _ _ _ __
OW, CS, WR,
DBO to DB7, 0)
I
Atf
VOO = 5V, Ta = -20 to 70°C
Symbol
Condition
Min
Typ
AO
-7
WR setup time
Parameter
tAW
0
CS
-7
WR setup time
tew
0
-
120
-
20
Max
Unit
WR
-7
AO hold time
tWA
-
WR
-7
CS hold time
\we
-
20
-
Data hold time
tOH
20
-
-
Write pulsewidth
twp
200
-
ns
16M>
-
50
lis
ns
50
ns
Min
Typ
0
-
-
ns
0
-
-
ns
120
-
ns
0
200
-
16M>
-
-
Data setup time
tos
Input fail time
tf
Input rise time
tr
-
Symbol
Condition
tweye
Write cycle
-
-
ns
-
ns
ns
ns
ns
ns
VOD = 3V, Ta = -20 to 70°C
Parameter
AO
-7
WR setup time
tAW
CS
-7
WR setup time
tew
Data setup time
tos
WR
-7
AO hold time
tWA
WR
-7
CS hold time
twe
Data hold time
Write pulsewidth
Write cycle
-
tOH
\wp
tweye
Input fail time
tf
Input rise time
tr
259
0
100
-
-
Max
Unit
ns
ns
ns
ns
-
50
lis
ns
-
50
ns
SED1210
•
X-Driver Control Timing
FR
LP
XSCL
so
Voo = 2.5 to 5.5V, Ta = -20 to 70°C
Parameter
Symbol
Condition
Min
Typ
Max
tCCL
-
3.3
10
-
Shift clock "H" pulsewidth
tWHCL
-
1.0
-
Ils
Ils
Shift clock "L" pulsewidth
twLCL
1.0
-
Ils
Delay time for XSCL rise
-7 SO output
toso
-
-
Latch pulse "H" pulsewidth
twHLP
1.0
Latch pulse "L" pulsewidth
tWLLP
-
-
-
Shift clock cycle
Latch time
tLT
Latch hold time
tLH
Delay time for frame signal
tOFR
-
Note: Load capacitance CL = 15 pF
260
300
500
500
-
-
1
-
-
Unit
IlS
Ils
ns
-
ns
-
ns
500
ns
SED1210
•
DISPLAY COMMAND
SET CURSOR DIRECTION
0
0
1
0
0
0
0
0
0
1
CURSOR ADDRESS -1/+1
0
0
1
0
0
0
0
0
0
1
CURSOR FONT SELECT
0
0
1
0
0
0
0
0
1
0
CURSOR BLINK ON/OFF
0
0
1
0
0
0
0
0
1
0
DISPLAY ON/OFF
0
0
1
0
0
0
0
0
1
1
CURSOR ON/OFF
0
0
1
0
0
0
0
0
1
1
Note
DO=l; Decrement
0 DII DO=O; Increment
DO=l;-l
1 -1/+1 DO=O; +1
All dots blinking
o A/U DO=l;
DO=O; Under line
1 ON/OfF
o ON/OfF DO=l;ON
DO=O; OFF
1 ONlOfF
SYSTEM RESET
0
0
1
0
0
0
0
1
0
0
0
DUTY SELECT
0
0
1
0
0
0
0
1
0
0
1 211
SET CGRAM ADDRESS
0
0
1
0
0
0
SET CGRAM DATA
0
0
1
0
0
1
1 0 A3 A2 A1 AO
0 D4 D3 D2 D1 DO
SET CURSOR ADDRESS
0
0
1
0
1 2nd11stA5 A4 A3 A2 A1 AO
SET CHARACTER CODE
0
0
1
1 D7 D6 D5 D4 D3 D2 D1 DO
BUSY FLAG CHECK
0
1
0
0 BF *
Command Name
CSWRRD AO D7 D6 D5 D4 D3 D2 D1 DO
*
*
*
*
*
0
*
Except data RAM and CGRAM
DO=l; 2 line display (1/16 duty)
DO=O; 1 line display (118 duty)
UPPER ADDRESS IS FIXED TO OH
D6=1; Nfigure for second line
D6=O; Nfigure for first line
BF=O; Ready
BF=l; Busy
Note: Misoperation may be caused when any command other than that listed in the above table is inputted.
261
'; High impedance
I
SED1210
•
CHARACTER CODE MAP (SED1210FoB)
0
0
1
Lower 4-bit (04 to 07) of Character Code (Hexadecimal)
2
4
7 8
9 A B C 0
3
5 6
CG RAM AREA
5xBDOTS
E
F
-.. .. .. ·· · · .....·
....
·
·
·
·
.....
·
·
...
·
·
·
- ... ..··· ... ........·····:- ·....···..··:·....··..····..··..····.....·· ··...·· ·.··..·· ··.....··· ·· ..··· ·..· ..... .. ··...···
.... ··· · ·
·. ....· ·....· ··· ··...····....·· .... .... ···· ......
·..·..·· ·· · ·· ··· ·.....
3 ·
·
·
...··.....
...·· ··... ·...· .....·· ... ·· ··· .. .. ···· ...···
·.........· ......· .....·....· ·......·...·· ·.....
· ·...·. ·.....·.· ·....··· · ·· ···.... ··.... ··· ...····.....·· ·· ·· ··..······ ·· ·· ·· ···..·..··· ··...··
4 ·
...··........···..... ·· ·....··· ·· ...· ·.....
..· ··...····..... ··...·· ·· ·· · ·
·....... ·...··....
....··...
·
·
·
·
·
·
·
·
·
·
....·· ·· .····..... ··...· ·· ·· ··· ···· ··· ··· ···· ··· ·· ··· ·· ·····
.... 5 ·
· ·... ..·· ...·· .....
··.. ··..· ·· ···...· ·· ·...·· ··..· ····· ·· ·· ·· ·.....
~
e:!
... ·.... .... ....· .....
... ....· ....
··....· ..·· ..·· ···..·· ·· ·..····.. ..· ·...·
6 ·· ....
....
·
·
·
·
·
·
·
·
·
·
·
....· ·....· ·.... ·....· ·... · ...· ·· ·· ...· ·..· ··..· ...· ··..····· · ·....
·....
....·
-- 7 ....
.....
·
·
·
..
.
....
.....
....
....
·· ·· ·· ···· .....
a
··....· ·....·····.. ·.......· ···.. ··....························· ·.......·· .....
·
·
..
......
....
..
·
·
·
·
...
..
...
..
·
·
-e. A ··......··........·· ·.....
··.· ...·· · ··......·· ····· .....· .....··· ··...·· ··...·· ·· ·· ·....
...· ·...· · ·..· · ·· ··
.....
:
...
:
·
·
·
·
...
:
.....
..
.....
...
...
-.... B ·....····..···..· · ·..··....····· ···........· ·.......··· ·.......·· ·........·····.·.......·.·. ··..·....·..·. ··......······.....·····.....············ ····
·· ·· · ·· ·..· ·....·· ·....·· ··...··... ·... ...· ...·· ·...···....·· ··....·
..
·
·
·
...
·
·
·
... · ·.....·· · · ...· ·...· ·... .....·· ·.....
.... ...· ...· .. ... · .·..··.....·.
:E
·
·
·
C ...· .:.:
·
·
.. ·....
··. ·...···· ...·.. ....
.... ·· ··... ··.....
....
·.....·.·
·
.....···.....
.
· ...···· · ..·....·· ······.......····.......·· ··...····.....
....
·
·
·
·
·
· ·..· ...
· .. ·..... .....
...
..
..
...
·
·
·
·
·
.....
.....
·
·
0
··· ·· ·...····.......·. ··.. ..·· ·······
··· ··· ·······...··· ··· ······ ·· ·......·····.·.....······.. ·····.. .....
· ··· ·· ·· ·
(ij
2
E
·0
CD
"C
CIS
x
CD
~
CD
"C
0
()
CIS
.J::.
()
0
("/)
0
0
:0
I
-=:t
CD
.J::.
C)
262
SED1210
•
EXAMPLE OF APPLICATION (20 characters x 2 lines display)
LCD
16
60
R,
I
CLOCK
In this case, SED1181 FLA is
used because of the large
number displayed characters.
8 bit CPU
SED1210FoB can be connected directly to the address bus or the data bus of a microprocessor, or to a peripheral interface unit.
•
•
DIE SPECIFICATION
PAD LAYOUT
1705
••••••••••••••••••
L
(0,0)
-1705
•••••••••••••••••••
41
•
2930
DIE & PAD SPECIFICATIONS
Die Size:
Die Thickness:
Pad Size:
Pad Pitch:
5.86 mm x 3.41 mm
400 11m
90 11m x 90 11m
190 11m
263
~=~~=~=~-
- --------
- -- ----
-~~=---
SED1210
•
PAD COORDINATES
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pad Name
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
AO
CS
RD
WR
12 CHAR X 4 LINES + ICONS
(0)
---/
6Bxx
BOxx
265
Q]
I
SED1230 Series
•
BLOCK DIAGRAM
r-DO
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
8=
S=
8=
I
,---
Address
Counter
-
Input
Buffer
'---
8=
'---
er-
RES
()-
PIS
Timing
Generator
MPU
Interface
Command
Decoder
Power
Supply
Circuit
=8
CAP1+
CAP1CAP2+
CAP2VR
VOUT
--(
--(
--(
I
9-
~-6
VS1
--(
Cursor
Control
Segment
Drive
Circuit
Static
Icon
--(
rl
e)---
Oscillator
r-
~
cs erWR(E)
Reflesh
Address Counter
CGROM
r-IF
-
RAM
,l
~
I
Common
Drive
Circuit
,l
~
SEGl-60
SEGSl-6
• Existfor only SED1230/1/213.
266
COMl-28
COMSl-3
I
I
I
n- -fnV1V2V3V4V5
SED1230 Series
•
PIN ASSIGNMENT
RES
1F
PIS
VS1
Voo
Vss
CAPS1+
CAPS1CAPS2+
CAPS2VOUT
VR
VO
V1
V2
V3
V4
V5
Vss
Voo
00
01
02
03
04
05
06
07
CS
WR
AO
COMS1'
SEGS1'
•
•
I
PIN DESCRIPTION
Power Supply
No. of
Pins
Pin Name
I/O
Description
Voo
Power
Supply
Common to MPU power supply pin Vee
2
Vss
Power
Supply
Ground
2
V1, V2, V3,
V4,V5
Power
Supply
LCD driver supply voltages. The voltages determined bthe LCD cell is
impedance converted by resistive divider or an operational amplifier. These
voltages should be determined on a Voo-basis so as to satisfy the following
relationship:
Voo ;:: VO ;:: V1 ;:: V2 ;:: V3 ;:: V4 ;:: V5
5
When the internal power supply is ON, the following voltages are generated
on-chip.
SE012320"
V1
V2
VS1
0
1/5 V5
V3
SED1232D"
3/5 V5
2/5 V5
V4
4/5V5
Power supply and voltage output for crystal power circuit
267
1
SED1230 Series
•
LCD Driver Supply
Pin Name
I/O
CAP1+
VOUT
0
0
0
0
0
VR
I
CAP1CAP2+
CAP2-
•
No. of
Pins
Description
DC/DC voltage converter capacitor 1 positive connect
1
DC/DC voltage converter capacitor 1 negative connect
1
DC/DC voltage converter capacitor 2 positive connect
1
DC/DC voltage converter capacitor 2 negative connect
1
DC/DC voltage converter output. Capacitor must be connected between VOUT
and Vss pad.
1
Voltage adjustment pin. Applies voltage between VDD and V5 using a
resistive divider.
1
Microprocessor Interface
Pin Name
I/O
07 (SI),
06 (SCl),
05 to DO
I
AO
No. of
Pins
Description
Data input from the data bus of standard MPU (8-bit or 16-bit).
8
07 and 06 pins are used for serial data input and a serial clock input
respectively when PIS = "l".
I
PIS
07
06
05-00
"L"
"H"
SI
SCL
-
07
06
05-00
AO
AO
AO
CS
CS
CS
Control/display data flag input. This is connected to the lSB of the
microprocessor address bus.
1
When lOW, the data on DO to 07 is command data.
When HIGH, the data on DO to 07 is display data.
RES
I
CS
I
WR(E)
I
PIS
I
This pin is used to initialize the SED1230 and to select the MPU interface
type. For a 68xx MPU interface, initialization occurs after a RES J. edge
transition. For a 80xx MPU interface, initialization occurs after a RES i edge
transition. MPU interface type is selected by input level after the reset.
"H" : 68xx MPU Interface
"L"
80xx MPU Interface
Chip select signal
<80xx MPU Connection>
Active "L"
This is a pin for connecting the WR signal of the 80xx MPU. The signal on
the data bus is fetched when WR signal rises to "H".
<68xx MPU Connection>
Active "l"
This is the enable clock of the 68xx MPU.
Parallel/serial data input select.
PIS
IF
I
"L"
Serial Clock
SCL (06)
Oata
SI (07)
"H"
-
07 - 00
Chip Select
CS
CS
Interface data long select pin.
"H" : 8-bit parallel input
4-bit parallel input
"L"
(When PIS = "l", connect this pin to VDD or Vss.)
268
Oata/Command
AO
AO
1
1
1
SED1230 Series
•
o
LCD Drive Output Signals
SED1230, SED1231, SED1232
Pin Name
COM1-COM28
COMS1 - COMS3
I/O
0
0
No. of
Pins
Description
Common Signal Output Pin (for character)
28'
Common Signal Output Pin (static signal and symbol)
3
COMS1
: Common output for static driver"
COMS2, COMS3 : Common output for symbol display
SEG1 - SEG60
SEGS1 - SEGS6
0
0
Segment Signal Output Pin (for character)
60
7
Segment Signal Output Pin (static signal and symbol)
Segment output for static driver"
SEGS1
SEGS2 - SEGS6 : Segment output for signal output
*
o
For SED1230, 28 pins. For SED1232, 14 pins. For SED1231, 21 pins.
** Output in stand-by mode only.
SED1233
Pin Name
COM1 -COM14
COMS1 - COMS3
I/O
0
0
No. of
Pins
Description
Common Signal Output Pin (for character)
14
Common Signal Output Pin (static signal and symbol)
3
Common output for static driver**
COMS1
COMS2, COMS3 : Common output for symbol display
SEG1-SEG80
SEGS1
0
0
Segment Signal Output Pin (for character)
80
SEGS1
Segment output for static driver'*
**
o
1
Segment Signal Output Pin (for static driver)
Output in stand-by mode only.
SED1234, SED1235
Pin Name
COM1 -COM28
COMS2 - COMS3
SEG1 - SEG60
SEGS2, SEGS6
I/O
0
0
0
0
Description
Common signal output pin (for character)
No. of
Pins
28
Common signal output pin (for symbol)
2
Segment signal output pin (for character)
60
Segment signal output pin (for symbol)
2
269
I
SED1230 Series
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Ratings
Unit
Vss
-5.0 to +0.3
-4.0 to +0.3
V
Driver supply voltage
V5
-16.0 to +0.3
V
Driver supply voltage
V1, V2,
V3, V4
V5 to +0.3
V
Input voltage
VIN
Vss - 0.3 to +0.3
V
Output voltage
VO
Vss - 0.3 to +0.3
V
TOPR
-30 to +85
°C
Parameter
Supply voltage
Operating temperature
Storage
temperature
Vee (Voo)
I TCP
I Chip
TSTR
Voo
Note:
-55 to +100
°C
-65 to +125
°C
1. The voltages shown are based on Voo = OV.
2. Always maintain the LCD driving voltage condition
such that: Voo '" V1 '" V2 '" V3 '" V4 '" V5.
3. If these devices are used over their absolute
maximum rating, they may be permanently damaged. To avoid a malfunction or degraded reliability these devices must be operated within the
boundries defined by the electrical characteristic
conditions for general operation.
(GND)VSS
V5
270
SED1230 Series
•
DC Electrical Characteristics
Parameter
(Vss = -3.6 to -2.4V, Ta = -30 to 85°C, unless otherwise specified)
Symbol
Recommended
Power
Voltage Operation
1
Operational
Vss
Recommended
Operation
VS
Conditions
Min
Typ
Max
Unit
-3.6
-3.0
-2.4
V
-S.S
-3.0
-2.0
V
VS
-11.0
-S.O
V
-4.S
V
VDD
V
V
Applicable Pin
Vss *1
Power
Voltage Operational
2
Operational
*2
-11.0
V1, V2
V1, V2
0.6 x VS
-
Operational
V3, V4
V3, V4
VDD
-
0.4 x VS
Hi-level input voltage
VIHC
*3
0.2 xVss
VDD
V
Low-level input voltage
VILC
*3
Vss
-
0.8 x Vss
V
*3
-1.0
-
1.0
~
COM, SEG
*4
20
40
kn
-
100
~
20
~
-
S
~
VDD *7
-
-
SOO
~
*3
-
5.0
8.0
pF
1.0
-
-
IJ.S
10
-
-3.6
-2.4
I1s
V
-4.0
V
-5.0
V
-4.S
V
Input leakage current
LCD drive ON resistance
III
RON
VIN = VDD or Vss
I
I
Ta = 2SoC
VS=7V
tN=O.1V
During display VS = -7V
Stand-by
Static power consumption
IDD
Sleep
I Power OFF
I OSCON
During access
fcvc = 200kHz
Input pin capacity
CIN
Reset time
tR
VDD *6
VDD
f=1MHz
tRW
*8
*g
Input voltage
Vss
*10
Raised output
voltage
VOUT
Reset "L" pulse width
Built-in
supply
circuit
Ta = 25°C
VDD *S
Voltage
follower
circuit
Reference
voltage
RaiSing 3 times
-10.8
vs(D
Applies to SED1230
-11.0
-
V5®
Applies to SED1231
-11.0
-
-4.5
V
V5@
Applies to SED1232
-11.0
-
-4.5
V
VREG
T. = 25°C
-3.5
-3.1
-2.7
V
Raising 2 times
VOUT
-7.2
*1. Correct operation is assured over the recommended Dperating voltage range. However, during MPU access excessive
voltage variatiDn may degrade operation.
*2. Operating voltage range applies when an external pDwer supply is used.
*3.
DO to D5, D6 (SCL), D7 (SI), AO, RES, CS, WR(E), PIS, IF
*4. This resistance value applies when 0.1 V is applied between output "SEGn", ·SEGSn", "COMn", "COMSn", and each
power supply pin (V1, V2, V3, V4). RON = ·1V/dl.
*5. This applies when the character
I
is displayed and the built-in oscillator and the built-in power supply is used.
*6. This applies when the built-in oscillator circuit is used and power supply are not used in stand-by mode.
*7. This indicates power consumption during writing of vertical bar patterns at constant fCYC. The power consumption
during access is nearly proportional to the access frequency (fovo). Only 100(1) applies when there is no access.
*8. t, (resettime) indicates the interval between the rising edge of an RES signal and completion olthe internal circuit reset.
Therefore, the SED1230 Series does not start normal operation until after the lapse of tr.
*g. t", is the minimum pulse width of the RES signal. For reset to occur, RES must pulse to "L" for a time period greater
than trw.
*10.
Power supply Vss on the primary side is used within the input voltage range if the voltage is doubled or tripled in the
built-in power supply circuit.
271
I
SED1230 Series
•
o
AC Characteristics
System Bus: Write Characteristics 1 (SOSO-Series MPU)
AO, CS
LI
==>s
-IAW8
•
Icyc8
J----ICC-
WR
I
1\
IOH8
los8 ----- ~
DO - 07
--f-~,------
(Vss = -3.6 to -2.4V, Ta = -30 to 85°C)
Parameter
Address hold time
Symbol
tAH8 "3
Address setup time
lAW8
System cycle time
tCYC8
Condition
Applicable Pin
~
AO, CS
"3
Vss = -2.7V
tcc
WR
Vss = -2.7V
tOS8
Data hold time
tOH8
-
30
650
100
-
50
-
100
150
Vss = -2.4V
Data setup time
Typ
30
500
Vss = -2.4V
Control pulse width
Min
DO to 07
*1. The input signal rise time and fall time must both be 15ns or less.
*2. Timing is based on 20% and 80% of Vss.
*3. It is not necessary that AO timing be the same as CS.
272
Max
Unit
-
ns
-
ns
ns
ns
ns
ns
ns
ns
SED1230 Series
o System Bus: Write Characteristics 2 (6800-Series MPU)
..
.
ICYC6
E
..
lEW
-IAW6-
:x
AO,CS
IAH6
K
--~-1- I O S 6 - ..-.IOH6
00 .. 07
I
(Vss = -3.6 10 -2.4V, Ta = -30 10 85°C)
Parameler
Symbol
System cycle time
tCYC6
Address setup time
Address hold time
Data setup time
Data hold time
!AW6
!AH6
tDSS
tDHS
Enable pulse width
tEW
Condition
Applicable Pin
AD, CS
DO to 07
E
500
650
Min
Vss = -2.7V
@ Vss = -2.4V
@
60
30
100
50
100 @ Vss=-2.7V
150 @ Vss = -2.4V
Typ
Max
-
-
ns
-
-
ns
ns
ns
ns
-
ns
*1 . !eves indicates E signal cycle when CS is active. teyes must be ensured after CS becomes active.
*2. The input signal rise time and fall time must both be 15ns or less.
*3. Timing is based on 20% and 80% of Vss.
*4. It is not necessary that AO have the same timing as CS.
273
Unit
SED1230 Series
o Serial Interface
I-
•
tess
----tesH--
/
C8
1-----
t SAS - -..
~ t SAH
--
)l
AD
L(
r--- tseye
\r---tS LW -
8CL
1-----
-J--~--tSDS --~
81
tSHW __ 1\
-- t SDH --
(Vss = -3.6 to -2.4V, Ta = -30 to 85°C)
Parameter
Symbol
System clock cycle
tseys
SCL "H" pulse width
tSHW
SCL "L" pulse width
Condition
Applicable Pin
Min
Typ
-
50
-
-
ns
150
-
-
ns
700
-
-
ns
300
-
tSLW
300
-
Address setup time
tSAS
50
-
Address hold time
tSAH
300
-
tSDS
50
tSDH
Data hold time
CS-SCL time
AO
tess
-
CS
tCSH
*1. The input signal rise time and fall time must both be 15ns or less.
*2. Timing is based on 20% and 80% of Vss.
274
Unit
ns
-
SCL
Max
-
1000
ns
ns
ns
ns
ns
SED1230 Series
•
PACKAGE DIMENSIONS
...
...----.,
g.~ X\f~
--
.
:
g'~ X\f~
BS'G
r []
[]
[~J
o
[J
I
01
o
I
o
I
~
275
OO"Z
OO"Z
I
SED1230 Series
•
SED1230 SERIES COMMAND SUMMARY
Command
Code
AO
WR
D7
D6
D5
D4
(1) Cursor home
0
0
0
0
0
1
(2) Static display
control
0
0
0
0
1
0
(3) Display ON/
OFF control
0
(4) Power save
0
0
0
0
0
0
1
1
0
1
0
· · . .
· ·
D3
D2
D1
Function
DO
Moves cursor to Home position.
SD1 SDO Sets display mode of Symbol.
C
B
· ·
DC
0
D
PS
(SD1, SDO) = (0,
(0,
(1,
(1,
0)
1)
0)
1)
(No display)
(1-2Hz blink)
(3-4Hz blink)
(All display)
Sets cursor ON/OFF (C), cursor blink ON/OFF
(B), double cursor ON/OFF (DC), and display
ON/OFF (D).
C = 1 (cursor ON)
= 0 (cursor OFF)
B = 1 (blink ON)
= 0 (blink OFF)
DC = 1 (double cursor ON)
= 0 (double cursor OFF)
D = 1 (display ON)
= 0 (display OFF)
Sets power save ON/OFF (PS) and oscillator
circuit ON/OFF (0).
PS = 1 (power save ON)
= 0 (power save OFF)
0 = 1 (oscillator circuit ON)
= 0 (oscillator circuit OFF)
(5) Power supply
control
(6) System set
0
0
0
0
0
0
1
1
0
1
1
0
0
N2
VC
N1
VF
.
P
Sets internal feedback register ON/OFF (VR),
voltage regulator ON/OFF (VC), voltage converter ON/OFF (P), and voltage follower ON/
OFF (VF).
VR = 1 (voltage regulator ON)
= 0 (voltage regulator OFF)
VC = 1 (voltage regulator ON)
= 0 (voltage regulator OFF)
VF = 1 (voltage follower ON)
= 0 (voltage follower OFF)
P = 1 (voltage converter ON)
(voltage converter OFF)
=
Sets the CGRAM (CG) to USEDINOT USED
and the number of display lines (N2, N1).
o
CG
CG = 1 (CGRAM USED)
(CGRAM NOT USED)
=
(N2, N1) = (0,0) (2 lines)
(0,1) (3 lines)
(1,0) (4 lines)
o
(7) Electronic
volume register
0
0
0
(8) RAM address
set
0
0
1
(9) RAM writing
1
0
1
1
4
MSB
LSB Sets the value of electronic contrast control
register.
ADDRESS
DATA
Sets the address of DDRAM, CGRAM or symbol
register.
Writes data to DDRAM, CGRAM or symbol
register.
276
SED1230 Series
•
OlE SPECIFICATION
SE012300** ......... 1/30 duty .......... 12 Characters x 4 Lines
SE012310**
SE012320**
SE012330**
SE012340**
SE012350**
.........
.........
.........
.........
.........
Chip Size
Pad Pitch
Chip Thickness
1/23 duty .......... 12 Characters x 3 Lines
1/16 duty .......... 12 Characters x 2 Lines
1/16 duty .......... 16 Characters x 2 Lines
1/30 duty .......... 12 Characters x 4 Lines
1/16 duty .......... 12 Characters x 2 Lines
10.23 x 3.11 mm
110 Ilm (Min.) ............... SE01230/1/2/3
1261lm (Min.) ................ SE01234/5
625 ± 25 Ilm (SE0123*O* A, SE0123*O*B)
525 ± 251lm (SE0123*O*C, SE0123*O*E)
I
1) AI Pad Spec. (SE0123*O* A and SE0123*O*C)
Pad Size
A 86 Ilm x 135 Ilm
B 1351lm x 861lm
2) Au Bump Spec. (SE0123*O*B and SE0123*O*C) (for reference)
Bump Size
Bump Height
80 Ilm x 129 Ilm
B 1291lm x 80 Ilm
22.5 Ilm ± 5.5 Ilm
A
173
86
DODD 00000000000000000000000000000000000000000000000000000000000000000000000000000000 DODD
174
B
0
§
8
B
o
B
B
85
8
+(0,0)
B
0
B
B
0
o
B
§o
193
6'
D
DODD DODD DODD DODD DODD DODD DODD DODD DODD DODO DODD DODO DODD DODD DODD DODD DODD
B
L-~--------------------------------------------------~68~~
277
69
SED1230 Series
•
SE012300"" PAO COOROINATES
No. Pin Name
1
NC
2
NC
NC
NC
Voo
3
4
5
X
y
Coord.
-4793
Coord.
-4683
-4572
-4462
Voo
-4242
-4132
Voo
Voo
-4021
-3911
Vss
Vss
Vss
-3691
-3581
-3470
12
13
Vss
V5
-3360
-3140
14
15
16
17
V5
V5
V5
V4
-3030
-2919
-2809
-2589
18
V4
V4
-2479
6
7
8
9
10
11
19
20
V4
21
22
23
V3
V3
V3
24
25
V3
V2
26
27
V2
V2
28
29
V2
V1
30
31
32
V1
33
34
VO
VO
VO
35
36
37
38
39
40
41
42
V1
V1
VO
VR
VR
VR
VR
VOUT
43
44
VOUT
VOUT
VOUT
45
46
47
CAP2CAP2CAP2-
48
49
50
51
52
53
54
-2368
-2258
-1371
-1371
-1371
-1371
-1371
No. Pin Name
CAP1-
56
57
CAP1CAP1+
2693
2803
3024
58
CAP1+
CAP1+
3134
3244
CAP1+
Vss
3354
3592
Vss
Vss
Vss
3702
3812
3923
Voo
Voo
4143
4253
Voo
Voo
4363
4474
NC
NC
NC
4883
4883
4883
4883
-1371
-1371
-1371
-1371
-1371
63
64
-1371
-1371
62
65
66
67
-1371
-1371
-1371
68
69
70
71
-1371
-1371
72
73
NC
VS1
-1371
PIS
IF
RES
4929
4929
4929
COMS1
COMS2
4929
4929
4929
4929
-2021
-1910
-1371
-1371
74
75
76
-1800
-1690
-1371
-1371
77
78
-1453
-1371
79
COM1
-1342
-1232
-1122
-1371
-1371
-1371
-1371
80
81
82
COM2
COM3
COM4
COM5
-884
-774
-1371
83
84
NC
NC
4947
4836
88
89
NC
NC
COM8
COM9
COM10
4726
4616
4347
14
-1371
-1371
90
91
-1371
-1371
92
93
-1371
-1371
-1371
94
95
96
97
455
565
803
913
1023
1133
1354
CAP2-
1464
1574
1664
CAP2+
CAP2+
1905
2015
CAP2+
CAP2+
CAP1CAP1-
2125
2235
2473
2583
-1371
-1371
65
86
87
98
-1371
-1371
-1371
99
100
101
-1371
-1371
102
103
104
-1371
-1371
-1371
-1371
-1371
4929
4929
4929
4929
4929
-1371
-1371
-1371
-1371
-1371
4929
COM6
COM7
-664
-554
-316
-206
-96
235
345
X
Coord.
55
59
60
61
-1371
-1371
Unit: /lm
COM11
COM12
COM13
COM14
SEGS2
SEGS3
SEGS4
4237
4127
4017
3906
3796
3686
3576
3466
SEG1
SEG2
3355
3245
3135
SEG3
SEG4
SEG5
3025
2915
2804
105
SEG6
2694
106
107
SEG7
SEG8
2584
2474
108
SEG9
2364
y
Coord.
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1343
-1233
-1123
-1013
..g02
-186
-76
34
255
365
475
585
695
806
916
1026
1136
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
No. Pin Name
X
Coord.
109
SEG10
2253
110
111
112
SEG11
SEG12
SEG13
113
114
SEG14
SEG15
2143
2033
1923
1813
115
SEG16
SEG17
1592
1482
SEG18
SEG19
SEG20
1372
1262
1151
120
121
SEG21
SEG22
1041
931
122
123
124
SEG23
SEG24
SEG25
821
711
600
125
126
SEG26
SEG27
490
380
127
128
SEG28
SEG29
270
160
129
130
131
SEG30
SEG31
SEG32
49
-61
-171
132
133
SEG33
SEG34
-281
-391
134
135
136
SEG35
SEG36
SEG37
-502
-612
-722
137
138
SEG38
SEG39
139
SEG40
SEG41
-832
-942
-1053
116
117
118
119
1702
SEG42
-1163
-1273
142
143
144
SEG43
SEG44
-1383
-1493
SEG45
145
146
SEG46
SEG47
-1504
-1714
-1824
147
148
149
SEG48
SEG49
SEG50
SEG51
-1934
SEG52
SEG53
-2375
-2485
SEG54
-2595
-2706
-2816
140
141
150
151
152
153
154
155
156
SEG55
SEG56
SEG57
157
158
SEG58
SEG59
159
160
161
SEG60
SEGS4
SEGS5
162
SEGS6
278
-2044
-2155
-2265
-2926
-3036
-3146
-3257
-3367
-3477
-3587
y
Coord.
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
No. Pin Name
163
164
165
166
167
168
169
170
171
172
173
174
175
X
Coord.
COM28
COM27
COM26
-3697
COM25
COM24
-4028
COM23
COM22
NC
NC
NC
NC
COM21
-4138
-4248
-4359
-4627
-4738
-4848
-4958
-4940
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1136
-4940
1026
COM18
COM17
COM16
-4940
-4940
-4940
-4940
916
806
696
COM15
-4940
585
475
182
COMS3
SEGS1
183
184
185
AO
WR
CS
-4940
-4940
-4940
-4940
365
255
34
-76
-4940
186
187
07
06
-4940
-4940
-186
-296
188
189
190
191
05
04
03
-4940
-4940
-4940
-4940
176
177
178
179
180
181
COM20
COM19
-3808
-3918
y
Coord.
192
02
01
193
DO
-406
-517
-627
-737
-4940
-847
..g57
-4940
-1068
SED1230 Series
•
SED1231D** PAD COORDINATES
X
No. Pin Name
Coord.
NC
-4793
1
2
NC
-4683
-4572
NC
3
4
NC
-4462
-4242
5
VDD
VDD
-4132
6
-4021
7
VDD
VDD
-3911
8
VBS
-3691
9
10
Vss
-3581
11
-3470
Vss
12
VSS
-3360
13
V5
-3140
14
V5
-3030
-2919
15
V5
16
V5
-2809
-2589
17
V4
-2479
18
V4
-2368
19
V4
20
V4
-2258
-2021
21
V3
-1910
22
V3
-1800
23
V3
24
-1690
V3
25
V2
-1453
-1342
26
V2
-1232
27
V2
-1122
28
V2
29
V1
-884
-774
30
V1
-664
31
V1
32
V1
-554
-316
VO
33
-206
VO
34
VO
-96
35
14
VO
36
37
VR
235
38
VR
345
455
39
VR
40
VR
565
41
VOUT
803
42
VOUT
913
VOUT
1023
43
44
VOUT
1133
CAP245
1354
46
CAP21464
CAP21574
47
CAP21684
48
1905
49
CAP2+
2015
50
CAP2+
51
CAP2+
2125
52
CAP2+
2235
CAP12473
53
CAP154
2583
y
Coord.
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
No. Pin Name
55
56
57
CAP1CAP1-
58
59
CAP1+
CAP1+
60
61
62
CAP1+
Vss
63
64
-1371
-1371
65
66
67
-1371
-1371
-1371
68
69
70
-1371
-1371
71
72
-1371
-1371
-1371
73
74
75
-1371
-1371
76
-1371
-1371
78
79
-1371
-1371
-1371
80
81
82
-1371
-1371
83
-1371
-1371
n
64
85
CAP1+
VBB
VBS
VSB
VDD
NC
NC
NC
VS1
-1371
3354
3592
3702
3812
-1371
-1371
-1371
-1371
3923
4143
-1371
4883
4883
-1371
-1371
-1371
SEG11
SEG12
112
113
SEG13
SEG14
114
SEG15
SEG16
115
116
117
118
SEG17
SEG18
SEG19
119
SEG20
SEG21
SEG22
-1371
-1343
120
121
122
123
-1233
-1123
124
125
SEG25
-1013
-902
126
SEG26
SEG27
127
128
129
130
SEG28
SEG29
SEG30
SEG31
SEG23
SEG24
Coord.
2253
2143
1382
1382
1382
2033
1923
1813
1702
1592
1482
1372
1262
1151
1041
1382
1382
1382
1382
1382
1382
1382
1382
1382
931
821
711
1382
1382
1382
600
490
1382
1382
380
270
1382
1382
160
49
-81
-171
1382
1382
1382
4929
4929
255
131
SEG32
COMS2
4929
4929
365
475
132
133
SEG33
SEG34
4929
4929
4929
585
SEG35
SEG36
SEG37
4929
4929
696
806
916
134
135
136
137
-391
-502
-612
-722
1026
138
SEG38
SEG39
-832
-942
4929
4947
1136
1382
139
140
SEG40
SEG41
-1053
1382
1382
4836
4726
4616
1382
1382
1382
141
142
1382
1382
1382
143
SEG42
SEG43
SEG44
-1163
-1273
-1383
4347
4237
1382
1382
144
145
SEG45
SEG46
-1493
-1504
-1714
1382
1382
4127
4017
3906
1382
1382
1382
SEG47
SEG48
SEG49
-1824
3796
1382
1382
146
147
148
149
150
SEG50
SEG51
-2155
-2265
1382
1382
151
152
SEG52
SEG53
-2375
3355
3245
1382
1382
153
154
SEG54
SEG55
3135
1382
155
156
SEG56
SEG57
157
158
SEG58
SEG59
COM1
COM2
COM3
COM4
COM5
COM6
COM7
92
COM9
COM10
-1371
-1371
93
94
COM11
COM12
-1371
-1371
95
COM13
COM14
SEGS2
3686
3576
3466
-186
-76
34
98
99
100
101
SEGS3
SEGS4
SEG1
SEG2
102
103
104
SEG3
SEG4
3025
2915
1382
1382
SEG5
2804
105
SEG6
SEG7
SEG8
SEG9
2694
2584
2474
2364
1382
1382
106
107
108
SEG10
110
111
Coord.
RES
COMS1
-1371
-1371
-1371
-1371
3244
109
y
4929
4929
4929
NC
COM8
-1371
-1371
-1371
-1371
-1371
No. Pin Name
X
PIS
IF
89
90
91
-1371
-1371
2693
2803
3024
3134
4474
4883
4883
-1371
-1371
-1371
-1371
Coord.
-1371
VDO
NC
-1371
-1371
-1371
-1371
Coord.
4253
4363
NC
NC
NC
-1371
-1371
y
VDD
VDD
86
87
88
96
97
Unit: Jlm
X
1382
1382
1382
159
SEG60
160
161
SEGS4
SEGS5
SEGS6
162
279
-281
-1934
-2044
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
-2485
-2595
-2706
-2816
1382
1382
-2926
-3036
1382
-3146
-3257
1382
1382
1382
1382
-3367
-3477
1382
1382
1382
-3587
1382
No. Pin Name
X
y
Coord.
Coord.
163
NC
-3697
1382
164
165
166
NC
NC
NC
1382
1382
167
168
NC
NC
-3808
-3918
-4028
-4138
169
170
171
NC
NC
NC
-4248
-4359
1382
1382
-4627
-4738
172
173
NC
NC
COM21
-4848
-4958
-4940
1382
1362
1382
COM20
COM19
COM18
-4940
-4940
-4940
COM17
COM16
-4940
-4940
COM15
COMS3
-4940
-4940
SEGS1
AO
WR
-4940
-4940
-4940
CS
07
-4940
-4940
06
-4940
-4940
174
175
176
1n
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
05
04
03
02
01
DO
-4940
-4940
-4940
-4940
-4940
1382
1382
1382
1136
1026
916
806
696
585
475
365
255
34
-76
-186
-296
-406
-517
-627
-737
-847
-957
-1068
I
SED1230 Series
•
SED1232D** PAD COORDINATES
X
No. Pin Name
Coord.
NC
-4793
1
NC
-4683
2
3
NC
-4572
-4462
NC
4
VDD
-4242
5
VDD
-4132
6
7
VDD
-4021
VDD
-3911
8
9
Vss
-3691
10
Vss
-3581
11
Vss
-3470
12
Vss
-3360
V5
-3140
13
14
V5
-3030
15
V5
-2919
16
V5
-2809
V4
-2589
17
18
V4
-2479
V4
-2368
19
20
V4
-2258
21
V3
-2021
22
V3
-1910
23
V3
-1800
-1690
24
V3
25
V2
-1453
26
-1342
V2
27
V2
-1232
-1122
28
V2
29
V1
-884
-774
30
V1
31
Vl
-664
32
V1
-554
VO
-316
33
34
VO
-206
35
VO
-96
36
VO
14
37
VA
235
VA
38
345
39
VA
455
40
VA
565
41
VOUT
803
VOUT
913
42
43
VOUT
1023
VOUT
1133
44
45
CAP21354
CAP21464
46
47
CAP21574
48
CAP21684
49
CAP2+
1905
CAP2+
50
2015
51
CAP2+
2125
52
CAP2+
2235
CAP153
2473
54
CAP12583
y
Coord.
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
X
Pin Name
Coord.
CAP12693
CAP12803
3024
CAP1+
CAP1+
3134
CAP1+
3244
CAP1+
3354
Vss
3592
Vss
3702
Vss
3812
Vss
3923
VDD
4143
VDD
4253
VDD
4363
VDD
4474
NC
4883
NC
4883
NC
4883
NC
4883
VS1
4929
PIS
4929
IF
4929
AES
4929
COMSl
4929
COMS2
4929
COM1
4929
COM2
4929
COM3
4929
COM4
4929
COM5
4929
COM6
4929
COM7
4929
NC
4947
NC
4836
NC
4726
NC
4616
COM8
4347
COM9
4237
COM10
4127
COMll
4017
COM12
3906
COM13
3796
COM14
3686
SEGS2
3576
SEGS3
3466
SEGS4
3355
SEGl
3245
SEG2
3135
SEG3
3025
SEG4
2915
SEG5
2804
SEG6
2694
SEG7
2584
SEG8
2474
SEG9
2364
Unit: 11m
y
Coord.
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1343
-1233
-1123
-1013
-902
-186
-76
34
255
365
475
585
696
806
916
1026
1136
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
No. Pin Name
X
Coord.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
2253
2143
2033
1923
1813
1702
1592
1482
1372
1262
1151
1041
931
821
711
600
490
380
270
160
49
-61
-171
-281
-391
-502
-612
-722
-832
-942
-1053
-1163
-1273
-1383
-1493
-1504
-1714
-1824
-1934
-2044
-2155
-2265
-2375
-2485
-2595
-2706
-2816
-2926
-3036
-3146
-3257
-3367
-3477
-3587
280
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEGS4
SEGS5
SEGS6
y
Coord.
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
No.
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
X
Pin Name
Coord.
-3967
NC
NC
-3808
NC
-3918
NC
-4028
NC
-4138
NC
-4248
-4359
NC
NC
-4627
NC
-4738
NC
-4848
NC
-4958
COM14 -4940
COM13 -4940
COM12 -4940
COMll
-4940
COM10 -4940
COM9
-4940
COM8
-4940
COMS3 -4940
SEGSl
-4940
AO
-4940
WA
-4940
CS
-4940
D7
-4940
D6
-4940
D5
-4940
D4
-4940
D3
-4940
D2
-4940
Dl
-4940
DO
-4940
y
Coord.
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1136
1026
916
806
696
585
475
365
255
34
-76
-186
-296
-406
-517
-627
-737
-847
-957
-1068
SED1230 Series
•
SED1233D** PAD COORDINATES
X
No. Pin Name
Coord.
-4793
1
NC
2
NC
-4683
3
NC
-4572
-4462
4
NC
VDD
-4242
5
VDD
-4132
6
VDD
-4021
7
VDD
-3911
8
Vss
-3691
9
10
Vss
-3581
11
-3470
Vss
Vss
-3360
12
13
V5
-3140
14
V5
-3030
-2919
15
V5
16
V5
-2809
-2589
17
V4
18
V4
-2479
-2368
19
V4
20
-2258
V4
21
V3
-2021
-1910
22
V3
23
V3
-1800
-1690
24
V3
25
V2
-1453
-1342
26
V2
-1232
27
V2
-1122
28
V2
-884
29
V1
-774
30
V1
-664
31
V1
32
V1
-554
-316
VO
33
-206
34
VO
VO
-96
35
VO
14
36
37
VR
235
VR
345
38
VR
455
39
40
VR
565
41
VOUT
803
VOUT
913
42
43
VOUT
1023
VOUT
1133
44
CAP245
1354
46
CAP21464
CAP21574
47
48
CAP21684
1905
49
CAP2+
50
CAP2+
2015
51
CAP2+
2125
52
CAP2+
2235
CAP153
2473
54
CAP12583
y
Coord.
No. Pin Name
Unit: 11m
X
Coord.
-1371
55
CAP1-
2693
-1371
56
CAP1-
2803
-1371
57
CAP1+
3024
-1371
58
CAP1+
3134
-1371
59
CAP1+
3244
-1371
60
CAP1+
3354
-1371
61
Vss
3592
-1371
62
Vss
3702
-1371
63
Vss
3812
-1371
64
Vss
3923
-1371
65
VDD
4143
-1371
66
VDD
4253
-1371
67
VDD
4363
-1371
68
VDD
4474
-1371
69
NC
4883
-1371
70
NC
4883
-1371
71
NC
4883
-1371
72
NC
4883
-1371
73
VS1
4929
-1371
74
75
-1371
76
-1371
77
-1371
78
-1371
79
-1371
80
-1371
81
-1371
82
-1371
83
-1371
84
-1371
85
PIS
IF
RES
COMS1
COMS2
COM1
COM2
COM3
COM4
COM5
COM6
COM7
NC
NC
NC
NC
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
4929
-1371
-1371
86
-1371
87
-1371
88
-1371
89
-1371
90
-1371
91
-1371
92
-1371
93
-1371
94
-1371
95
-1371
96
-1371
97
-1371
98
-1371
99
-1371
100
-1371
101
-1371
102
-1371
103
-1371
104
-1371
105
-1371
106
-1371
107
-1371
108
4929
4929
4929
4929
4929
4929
4929
4929
4929
4929
4929
4947
4836
4726
4616
4347
4237
4127
4017
3906
3796
3686
3576
3466
3355
3245
3135
3025
2915
2804
2694
2584
2474
2364
y
Coord.
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1343
-1233
-1123
-1013
-902
-186
-76
34
255
365
475
585
696
806
916
1026
1136
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
No. Pin Name
X
Coord.
109
SEG20
2253
110
SEG21
2143
111
SEG22
2033
112
SEG23
1923
113
SEG24
1813
114
SEG25
1702
115
SEG26
1592
116
117
SEG27
SEG28
1482
1372
118
SEG29
1262
119
SEG30
1151
120
SEG31
1041
121
SEG32
931
122
SEG33
821
123
SEG34
711
124
SEG35
600
125
SEG36
490
126
SEG37
380
127
SEG38
270
128
129
SEG39
SEG40
160
49
130
SEG41
-61
131
SEG42
-171
132
SEG43
-281
133
SEG44
-391
134
SEG45
-502
135
-612
136
SEG46
SEG47
137
SEG48
-832
138
SEG49
-942
139
SEG50
-1053
140
SEG51
-1163
141
SEG52
-1273
-1383
-722
142
SEG53
143
SEG54
-1493
144
SEG55
-1504
145
SEG56
-1714
146
SEG57
-1824
147
148
SEG58
SEG59
-2044
149
SEG60
-2155
150
SEG61
-2265
151
SEG62
-2375
152
SEG63
-2485
153
SEG64
-2595
154
SEG65
-2706
155
SEG66
-2816
-1934
156
SEG67
-2926
157
SEG68
-3036
158
SEG69
-3146
159
SEG70
-3257
160
SEG71
161
SEG72
-3367
-3477
162
SEG73
-3587
281
y
Coord.
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
No.
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
X
Pin Name
Coord.
SEG74
-3967
SEG75
-3808
-3918
SEG76
SEG77
-4028
SEG78
-4138
SEG79
-4248
SEG80
-4359
NC
-4627
NC
-4738
NC
-4848
NC
-4958
COM14
-4940
COM13
-4940
COM12
-4940
COM11
-4940
COM10
-4940
COM9
-4940
COM8
-4940
COMS3
-4940
SEGS1
-4940
AO
-4940
WR
-4940
-4940
CS
07
-4940
06
-4940
05
-4940
04
-4940
03
-4940
02
-4940
01
-4940
00
-4940
y
Coord.
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1382
1136
1026
916
806
696
585
475
365
255
34
-76
-186
-296
-406
-517
-627
-737
-847
-957
-1068
I
SED1230 Series
•
SE012340**
X
No. Pin Name
Coord.
VOO
-4077
1
2
VSS
-3526
3
V5
-2975
4
V4
-2424
V3
-1855
5
V2
-1287
6
7
V1
-719
VO
-151
8
VR
400
9
VOUT
10
968
11
CAP21519
12
CAP2+
2070
13
CAP12638
14
CAP1+
3189
15
VSS
3757
VOO
4308
16
17
(NC)
4883
18
(NC)
4883
19
(NC)
4883
(NC)
4883
20
21
VS1
4929
22
PIS
4924
23
IF
4924
24
RES
4924
25
COMS2
4950
26
COM1
4950
27
COM2
4950
28
COM3
4950
29
COM4
4950
30
COM5
4950
31
COM6
4950
32
COM7
4950
Unit: 11m
y
Coord.
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1343
-1233
-1123
-1013
-903
-184
-57
No. Pin Name
y
X
Coord.
Coord.
X
No. Pin Name
Coord.
33
COM8
4896
1406
65
SEG25
837
34
COM9
4769
1406
66
SEG26
710
35
COM10
4642
1406
67
SEG27
584
36
COM11
4515
1406
68
SEG28
457
37
COM12
4388
1406
69
SEG29
330
38
COM13
4262
1406
70
SEG30
203
39
COM14
4135
1406
71
SEG31
76
40
41
SEGS2
4008
1406
SEG32
SEG1
3881
1406
72
73
SEG33
-51
-177
42
SEG2
3754
1406
74
SEG34
-304
43
SEG3
3627
1406
75
SEG35
-431
44
SEG4
3501
1406
76
SEG36
-558
45
SEG5
3374
1406
77
SEG37
-685
46
SEG6
3247
1406
78
-812
47
SEG7
3120
1406
79
SEG38
SEG39
48
SEG8
2993
1406
80
SEG40
-1065
49
SEG9
2866
1406
81
SEG41
-1192
50
SEG10
2740
1406
82
SEG42
-1319
51
SEG11
2613
1406
83
SEG43
-1446
52
SEG12
2486
1406
84
SEG44
-1572
53
SEG13
2359
1406
85
SEG45
-1699
54
SEG14
2232
1406
86
SEG46
-1826
55
SEG15
2106
1406
87
SEG47
-1953
-938
70
56
SEG16
1979
1406
88
SEG48
-2080
255
57
SEG17
1852
1406
89
SEG49
-2207
382
58
SEG18
1725
1406
90
SEG50
-2333
510
59
SEG19
1598
1406
91
SEG51
-2460
637
60
SEG20
1471
1406
92
SEG52
-2587
764
61
SEG21
1345
1406
93
SEG53
-2714
891
62
SEG22
1218
1406
94
SEG54
-2841
1019
63
SEG23
1091
1406
95
SEG55
-2968
1146
64
SEG24
964
1406
96
SEG56
-3094
282
y
Coord.
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
No.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
X
Pin Name
Coord.
-3221
SEG57
SEG58
-3348
SEG59
-3475
-3602
SEG60
SEGS6
-3729
COM28
-3855
COM27
-3982
COM26
-4109
COM25
-4236
COM24
-4363
COM23
-4679
COM22
-4806
COM21
-4933
-4964
COM20
COM19
-4964
COM18
-4964
COM17
-4964
COM16
-4964
COM15
-4964
COMS3
-4964
AO
-4964
WR
-4964
CS
-4964
07
-4964
06
-4964
05
-4964
04
-4964
03
-4964
-4964
02
01
-4964
DO
-4964
y
Coord.
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1405
1405
1405
1094
966
839
712
584
457
330
202
75
-52
-180
-307
-434
-562
-689
-816
-943
-1071
SED1230 Series
•
SE012350**
No. Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VOO
VSS
V5
V4
V3
V2
V1
VO
VR
VOUT
CAP2CAP2+
CAP1-
y
Coord.
Coord.
-1371
-4077
-3526
-2975
-2424
-1371
-1371
-719
-151
-1371
-1371
-1371
400
968
1519
2070
CAP1+
VSS
16
17
VOO
(NC)
4308
4883
18
19
(NC)
(NC)
4883
4883
20
21
22
(NC)
VS1
4883
4929
4924
23
24
IF
RES
COMS2
COM1
COM2
COM3
COM4
COM5
COM6
COM7
25
26
27
28
29
30
31
32
-1371
-1371
-1371
-1855
-1287
2638
3189
3757
PIS
Unit: Ilm
X
-1371
-1371
-1371
-1371
-1371
-1371
-1371
-1343
-1233
-1123
-1013
-903
-184
4924
4924
--57
70
4950
4950
4950
255
382
4950
4950
510
637
764
891
4950
4950
1019
4950
1146
No. Pin Name
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
X
y
Coord.
Coord.
Coord.
Coord.
1406
1406
1406
1406
4896
1406
65
SEG25
4769
4642
1406
1406
66
67
SEG26
SEG27
837
710
584
COM11
COM12
4515
1406
68
SEG28
457
1406
1406
1406
69
70
71
SEG29
SEG30
101
SEGS2
SEG1
4008
3881
1406
1406
1406
1406
1406
1406
102
103
104
SEG2
SEG3
3754
3627
1406
1406
72
73
74
330
203
76
-51
-177
1406
COM13
COM14
4388
4262
4135
-304
1406
SEG4
SEG5
3501
3374
3247
3120
1406
1406
-431
-558
1406
1406
1406
1406
77
78
79
2993
1406
1406
80
81
SEG40
SEG41
-685
-612
-938
-1065
1406
1406
1406
1406
1406
82
SEG42
-1192
-1319
83
84
85
SEG43
SEG44
SEG45
SEG46
SEG6
SEG7
SEG8
50
51
52
53
54
SEG12
SEG13
SEG14
2486
2359
2232
1406
1406
1406
55
SEG15
SEG16
2106
1979
1406
SEG17
SEG18
1852
SEG19
SEG20
62
SEG21
SEG22
63
64
SEG23
SEG24
1406
1406
75
76
86
87
1406
1406
68
1406
1406
1406
90
91
92
1218
1406
1406
93
94
1091
964
1406
1406
95
96
1725
1598
1471
1345
89
283
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG47
-1446
-1572
-1699
-1826
-1953
SEG48
SEG49
SEG50
-2080
-2207
SEG51
SEG52
SEG53
-2460
-2587
SEG54
SEG55
SEG56
-2333
-2714
-2841
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
1406
-2968
1406
1406
-3094
1406
X
y
SEG57
Coord.
-3221
Coord.
1406
SEG58
SEG59
SEG60
-3348
-3475
-3602
1406
1406
1406
SEGS6
COM28
-3729
1406
1406
No. Pin Name
COM9
COM10
2866
2740
2613
58
59
60
61
y
COM8
SEG9
SEG10
SEG11
56
57
No. Pin Name
X
97
98
99
100
COM27
COM26
COM25
-3855
-3982
-4109
-4236
COM24
COM23
-4363
-4679
1406
1405
COM22
COM21
-4806
-4933
1405
1405
110
111
112
COM20
COM19
COM18
-4964
-4964
-4964
1094
966
113
114
COM17
COM16
-4964
-4964
115
COM15
COMS3
-4964
-4964
AO
WR
CS
-4964
-4964
-4964
120
121
07
06
-4964
-4964
122
123
124
05
04
03
-4964
-4964
-4964
125
126
02
01
-4964
-4964
127
00
-4964
105
106
107
108
109
116
117
118
119
1406
1406
1406
839
712
584
457
330
202
75
--52
-180
-307
-434
--562
-689
-616
-943
-1071
I
SED1230 Series
•
MICROPROCESSOR INTERFACE
The SED1230 Series interfaces to either 8080- or 6800- Series microprocessors. The number of connections
to the microprocessor can be minimized by using a serial interface.
•
8080-Series Microprocessors
~------------~AO
Vee
es
Voo
r:::::::::::::J
Voo
PIS
~
1========1 00-07
Voo
IF
1----------------1 WR
GNO
RES ~----~.------~ RES
Vss
RESET
•
6800-Series microprocessors
AO
Vee
Voo
Voo
PIS
es
ISE0123Xl
00-07
E
GND
RES 1----------..---c(;>---1 RES
Voo
IF
Vss
RESET
•
Serial Interface
T
Vee
Port 4
AO
Port 3
es
Voo
-
Port 1
Port 2
GNO
PIS
ISE0123XI
I MPU I
IF
SI
Sel
RES
RES
1
-J
Vss
&
RESET
284
*
*
THIS PAGE INTENTIONALLY BLANK
286
SED1278
CMOS DOT MATRIX LCD CONTROLLER DRIVER
•
DESCRIPTION
The SED1278 is a character LCD controller-driver, capable of driving displays as large as 2 lines of 8
characters (5 x 8 pixels), with minimum external components.
The SED1278 has an internal CGROM consisting of 240 characters (5 x 7) plus the underline cursor, JIS,
ASCII, and eight user-programmable characters in RAM.
The SED1278 has 40 segment output and 16 common output built-in. Thus, one chip is capable of displaying
up to 16 characters. The SED1278 can display one line of 48 characters using an SED1681 F (80-bit output)
as an expansion segment driver.
The SED1278 is fabricated using a silicon gate CMOS technology process and features very low power
dissipation. This makes the device suitable for handheld and portable applications.
•
FEATURES
• Low-power CMOS technology
• Built-in power on power-on reset
• 40 segment output
• 16 common output
• Built-in RC oscillator
• Built-in LCD driver voltage-divider network
• Duty: 1/8 or 1/16 (set by command)
• TTL compatible CPU interface
• 4/8-bit CPU data interface, TTL compatible
• Supply voltage ................... Logic: 4.5V to 5.5V
LCD: 3.5V to 5.5V
• Two frame AC drive wave form
• CGRAM: ........................................ 8 characters
• Package:
QFP5-80 pins (FaA, FOB, Foc, Foo, FOG, FOH)
• Display data RAM: ... 80 x 8 bits (80 characters)
AI pad (DOA, DaB, Doc, DOD, DOG, DOH)
• CGROM: .................................... 240 characters
• Recommended expansion segment driver:
SED1181 FLA (64 output)
SED1681 F (80 output)
•
SYSTEM BLOCK DIAGRAM
DATA
CPU
SED1278
CONTROL
16COM
XSCL, LP
DO
287
I
SED1278
•
BLOCK DIAGRAM
OSC1 OSC2
DiD
DB?
XSCL
LP
FR
RIW
RS
COM1
,
,
COM16
SEG1
,,
V DD
SEG40
Vss
V1
V2
V3
V4
V5
DO
•
PIN CONFIGURATION
DB1
DBO
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
E_
RIW
RS
DP
FR
VOD
XSCL
LP
V5
V4
V3
V2
V1
OSC2
288
SED1278
•
PIN DESCRIPTION
Symbol
No. of signals
RS
1
Register select signal
Functions
RJW
1
Read/write select signal
E
1
Read/write execute signal
DBOto DB7
8
Data bus
LP
1
Data latching pulse
XSCL
1
Data transfer clock
LCD AC driving signal
FR
1
DO
1
Serial data
COM1 to COM16
16
Common outputs
*1
COM9 to COM16 : non-select for 1/8 duty
COM12 to COM16: non-select for 1/11 duty
SEG1 to SEG40
40
Segment outputs
V1 to V5
5
LCD driving power (V5-c.Vss)
Voo
1
+5V
Vss
1
OV (GND)
OSC1
2
OSC2
*1
•
•
I
Used to connect resistor (typ. 91 KQ) for oscillation;
OSC1 is for external clock input.
RIW
E
0
0
-.r-L
0
1
1
1
0
-.r-L
DD RAM or CG RAM data write cycle
1
1
1
DD RAM or CG RAM data read cycle
RS
Operation
Instruction write cycle
Busy flag read cycle
Address counter read cycle
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Vss
Parameter
Symbol
Rating
= OV, Ta = 25DC)
Unit
Supply voltage (1)
Voo
-0.3 to 7.0
V
Supply voltage (2)
V1 to V5
-0.3 to Voo+0.3
V
V
Input voltage
VI
-0.3 to Voo+0.3
Output voltage
Vo
-0.3 to Voo+0.3
V
Po
300
mW
Operating temperature
Topr
-20 to 75
DC
Storage temperature
Tstg
-65 to 150
DC
Soldering temperature and time
Tsol
260DC'10s (at lead)
Power dissipation
Note: The following condition must always hold true: VDD ;" V1 ;" V2 ;" V3 ;" V4 ;" V5
289
-
SED1278
•
DC Characteristics
Parameter
(Voo = 5.0V ±1 0%, Vss = OV, Ta = -20 to ?5°C)
Symbol
Applicable Pin
Min
"H" level input voltage (1)
VIHI
Condition
DBO-DB?
2.0
"L" level input voltage (1)
VIL1
RS,R/W,E
Vss
"H" level input voltage (2)
VIH2
"L" level input voltage (2)
VIL2
"H" level output voltage (1)
VOHI
IOH=-0.205mA
"L" level output voltage (1)
VOL1
IOL=1.6mA
Typ
Vss
-
2.4
-
Unit
Voo
V
0.8
V
Voo
V
1.0
V
-
-
V
0.4
V
0.9Voo
-
-
-
0.1Voo
V
-
2
10
kO
2.5
10
kO
1
IlA
50
125
250
-
0.5
0.8
IlA
mA
fEXTCL
125
250
350
kHz
Duty
45
50
55
%
-
-
0.2
Ils
-
0.2
Ils
190
2?0
350
kHz
245
250
255
kHz
Voo
V
OSC1
DBO-DB?
"H" level output voltage (2)
VOH2
IOH=-0.04mA
"L" level output voltage (2)
VOL2
IOL=0.04mA
XSCL
LP
DO
Driver-on resistor (COM)
RCOM
IVCOM-Vnl=0.5V
COM1-16
Driver-on resistor (SEG)
RSEG
IVSEG-Vnl=0.5V
SEG1-40
I/O leakage current
IlL
VI=O to Voo
Pull-up MOS current
-Ip
Voo=5V
Supply current
lop
Rf oscillation, from external cloc
VOD=5V, fosc=fcp=270kHz
VOO
VOD-1.0
Max
-
-
V
External clock operation
External clock operating frequency
External clock duty
External clock rise time
trExTCL
External clock fall time
tfEXTCL
Internal clock operation (Rf oscillation)
Oscillation frequency
RI=91kO±2%
fosc
Internal clock operation (Ceramic filter oscillation)
•
o
Oscillation frequency
fosc
Ceramic filter
LCD driving voltage
VLCD
Voo-V5
3.0
-
AC Characteristics
Read cycle
(Voo = 5.0V ± 10%, Vss = OV, Ta = -20 to ?5°C)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
Enable cycle time
tcycE
500
-
-
ns
Enable "H" level pulse width
tWEH
220
-
ns
Enable rise/fall time
trE, tiE
-
25
ns
-
ns
120
ns
-
ns
-
RS, RIW setup time
lAs
40
RS, RIW address hold time
tAH
10
Read data output delay
tRO
Read data hold time
tOHR
CL=100pF
20
290
-
ns
SED1278
o
Write cycle
(VDD
500
-
ns
Enable "H" level pulse width
twEH
220
-
ns
25
ns
-
ns
ns
ns
Conditions
RS, RIW setup time
tAS
40
-
RS, RIW address hold time
tAH
10
-
Data setup time
tDS
60
-
-
Write data hold time
tDH
10
-
-
-
trE, tIE
ns
Timing Chart
Read cycle
RS
V1H1
V1L1
V1H1
V1L1
>
-
-tWEH--
-.
E
V1L1
I-
trE -
~IH1
tAH
VOH1
VOL1
..
V1L1
- - tDHR
~tRD-1
DBO to DB7
tAH
--- tfE
V1H1
1\ V1L1
V1H1
tI
I
l(
---
tAS
V1H1
RJW
o
Unit
Typ
tcycE
Symbol
Enable rise/fall time
o
Max
Min
Enable cycle time
Parameter
•
= 5.0V±10%, Vss = OV, Ta =-20 to 75°C)
Significant
Data
>(~OH1
OL1
tcyCE
•
Write cycle
RS
>
V 1H1
V1L1
V1H1
V1L1
-----
RJW
\
---
t AS
V1L1
-.
V1L1
tAH
11v'L1
-tWEH--
E
K
1/
V1H1
V1H1
---
trE -
\
V1L1
r tDSSignificant
-
V1L1
1--
V1H1
V1L1
DBO to DB7
..
Data
lcyCE
291
tAH
--- tIE
tDH
K~'H1
1L1
.
SED1278
•
DISPLAY COMMAND
Parameter
RS
R!W DB? DB6 DB5 DB4 DB3 DB2 DB1 DBa
CLEAR DISPLAY
a
a
a
a
a
a
a
a
a
CURSOR HOME
a
a
a
0
0
0
0
0
1
·
ENTRY MODE SET
0
0
0
0
0
0
0
1
liD
S
DISPLAY ONIOFF
0
0
0
0
0
0
1
D
C
B
CURSORIDISPLAY SHIFT
0
0
0
0
0
1
SYSTEM SET
0
0
0
0
1
DL
SIC RIL
N
F
Note
1
. ·
. ·
DB1 =1 : Increment, DB1 =0 : Decrement
DBO=1 : The display is shifted.
DBO=O : The display is not shifted.
DB2=1 : Display on DB2=0 : Display off
DB1 =1 : Cursor on
DB1=0: Cursor off
DBO=1 : Brinking on DBO=O : Brinking off
DB3=1 : Shifts display one character
DB2=1 : RighI shift, DB2=0 : Left shift
DB4=1 : 8 bits, DB4=0 : 4 bits
DB3=1 : 2 lines display (1/16 duty),
DB3=0 : 1 line display
(DB2=1 : 5x10 daIs, 1/11 duty )
DB2=0 : 5x7dots, 1/8 duty
SET CGRAM ADDRESS
0
a
0
SET DDRAM ADDRESS
0
0
1
ADD
The address length that can be set is 80 addresses.
READ BUSY FLAGI
ADDRESS COUNTER
a
1
BF
AC
DB7=1 : Busy (instruction not accepted)
DB7=0 : Ready (instruction accepted)
WRITE DATA
1
a
Write Data
READ DATA
1
1
Read Data
1
ACG
• Don't care
292
The address length that can be set is 64 addresses.
SED1278
•
EXAMPLE OF APPLICATION (2 lines x 20 characters)
SED1278
LCD
COM1
COM16
SEG1
16
>
16 x 100 Dots
!:{
60
SEG40
(j)
DO
DO
0
LO
UJ
UJ
0---0
(J)
(J)
001 01
000 ~
SED1181 FLAIDLA
..J
iJi
()
0 (J)
Il.(J)OCo(J)C\J(')(J)
..JXLL»»>
I I
LP
XSCL
FR
VDD
Vss
V2
V3
V5
OSC1
OSC2
~
Rf
SED1278 is usually connected to 8-bit MPU via I/O ports.
293
OPEN
I
SED1278
•
PAD LAYOUT
..
4,500
24
•
1
•••••••••••••••••••• 80
•
Y
•
•
• 0
• "-
"0
ell
X
CG
0>
E- 6 RAM
O>
"0
0
(7)
CG
0
ID 7 RAM
U
~
(8)
ell
.s:::
CG
'0 8 RAM
cry
0
0
(1)
.8
CG
RAM
0
8-
9
(2)
:0
<:lID
$:
0
CG
A RAM
(3)
-'
B
CG
RAM
(4)
C
CG
RAM
(5)
CG
0 RAM
(6)
CG
E RAM
(7)
F
CG
RAM
(8)
.... ............
. .... ...
.....
.... ....
....
... ..... ..........
.....
....
....
.
.... ... ......
... ..........
... ....
..
. . .. .
....
...... .......
......
....
.........................
.. ......
.. ... .... .. ......
.. ..
....
......
..
.
.. ...
.. ......
..... ..
.... ·.........
............
.
. ..
. ..... ..
..........
·· ·...
.
.
.
.......
... ... .......
.. ... ....... ...
··... ............
...........
. ...
...
.. .... . .
....
..
...
·.... ..... .....
..........
,
........ ..
····......
...........
..........
....
. .....
..........
·........
.....
.....
...........
..... . .....
.. . .. .
.......
·
· .......... ...
·· :.... . . :
··· ..· ... .· ... ....
. · ·..· .....
.
·· ·.. .... ..· .....
.....
.. ..·.
.:
·· . ·. ... · ·· :.
..
. ...
·
·
·
·· ···· ..... ·. ...
.....
·...
.. ....
...... ...
.·.. ....
.. .... .
.
..
.... . ..
....
..... .. ........
.... ...
.
... ..........
.. .... ..
..
· ..
......
....
II
....
..
.....
.......
............. . ........
· . .
.... ..
.....
.......
.. ...... ..
............
. ..............
.... ..... .
..
......
........
. ........
.·......
.......
·.....
... .......
. ..
· . ...
. . ..... .
.... ...
.. .......
........
............
.
... ..
· ....
.. . .
.' :": .:::~ .......
·... ...
.
.
. . ....
. . .....
...·.............
··.....
..
..
.
...
. .
.....
.......
...
......
... ... ...
... . ....
. ...... . . .. .
... ..............
.....
.....
...
.
··......
...... .
. ...........
....
.... ..
... . .
......
.................
..
·
.
. .. ...
..................
·... .........
... ... . .. . .. ..
......
·........
.. . .·. ...
... ..
.,
•
• • • • • • • •
II
•••
.... .
·. .............
...... .. . .
....
...
...... .... .
· ................
.... ..
. ... ..
,
........
.......
··· ...
..
.. .. ......
.. . ......
· ...
·.....
...
...
··· ...
..
· ..
... .... .......
....
.
........
·· .....
..
.....
.......
... ...
....
.
.
·
..
.....
....
.
...
.... .....
....
298
· ..
SED1278
•
SED1278FoH/DoH CHARACTER FONT
Higher 4-bit (D4 to D7) of Character Code (Hexadecimal)
23456789ABCD
o
o
CG
RAM
(2)
CG
2 RAM
(3)
CG
3 RAM
(4)
CG
4 RAM
(5)
(ij
E 5
·0
Q)
""C
co
X
Q)
;S 6
Q)
""C
·........
......
. .. ..
·........
.. ......
CG
RAM
(1)
CG
RAM
(6)
CG
RAM
(7)
....
... .........
... .........
. ....
....
......
.... ....
. . I.
·...I........
...... ..
..
·
.
...
.
· ....... .. ..........1. .
.....
... .....
· . ........
.....
..... ..
. . . . .... ...
I
•
(;;
13
7
~
co
..c
()
"0 8
.....
.1. ...
.....·· . .......
...
..••... ....• ... .... ... .
....· ...
. ... . .... ..
I.
..... ......
c;;-
o
(1 )
.9
CG
RAM
(2)
0
e.
:0
9
~
CG
A RAM
--'
(3)
(;;
s:0
CG
B RAM
(4)
CG
C RAM
(5)
.
· .....
... ... ...
.. ........
........
..
···...
..
I. ... ....... ..
... .... .. ..
. ..
···......................
. ...
...
...
........ . . .
·.... ........... ..
..
I.
••
•
••
.......
. .. ..... .
..............
..
.
···· .......
..... ...........
..........
···....
.................. ........
.....
.. .. .... .
CG
RAM
(8)
CG
RAM
••••
.•.•
0
()
••
.. .... ..... ..... ..... .... .
I. .
· ·...... ..
.. ..
.. ......
· :....
. :
·· .. ... . ... ....
..
I.
·
•
..
..... I.
••
••
.. ..
. ... . .. ...
·
· · . ..... : . ... ...
CG
F RAM
(8)
F
···· ..
.... ... . .. .
......
....
..
· .. ..... ..... ...
.
....
.
.
..
.... ... : ...
. ...
· ·
·· ... ...
.... ..
.
... . .. ....
. .......
.... ........
· . ..
.....
... ... ....
.... .
... ......... ...
. .. ..
····........... .....
... ..
... ................ ..
. . .....
... ..
···............
.....
. ........
...
....
.
...
........
...
· ..... .. ..... ......
.'
.........
..
.. ...
···....... ....
.
..
.... . .
...
· ·...
..
....
.... .....
. .. ... .....
. ....... ...........
. .....
.....
....
. ... .
..
·....·. ......
. ....
...
.. ...
...... ....... .
· ...... ...
.
. .... ..... ..
· . . .. ...
. .... . ...
··......... .......
... ..................
. ..... ..
CG
D RAM
(6)
CG
E RAM
(7)
E
.. ...... ...
···· ...
.....
... ..... .... .........
·... .... ..... ..
..... . ...... ..
·.... .. .....
... .....
* Character codes (OOH-OFH) of SED1278F are assigned to the area of character generator RAM (CG RAM). The CG ROM
of the SED1278F is masked; if you wish to have your own CG ROM, consult S-MOS Marketing Department for conversion
of the masked ROM.
301
I
THIS PAGE INTENTIONALLY BLANK
302
SED1280
CMOS DOT MATRIX LCD CONTROLLER DRIVER
•
DESCRIPTION
The SED1280 is a character LCD controller-driver, capable of driving displays as large as 2 lines of 8
characters (5 x 8 pixels), with minimum external components.
The SED1280 has an internal CGROM consisting of 240 characters (5 x 7) plus the underline cursor, JIS,
ASCII, and eight user-programmable characters in RAM.
The SED1280 has 40 segment output and 16 common output built-in. Thus, one chip is capable of displaying
up to 16 characters. The SED1280 can display one line of 48 characters using an SED1681 F (80-bit output)
as an expansions segment driver, since the driver is provided with the SED1278F core. Also, the LSI features
serial data interface to interface to MPU, key matrix controller, LED controller and input/output ports. These
features are suitable for applications such as facsimile machines.
•
• Low-power CMOS technology
• Key matrix scan controller:
Capable of controlling 8 x 10 keys
• 40 segment output
• LED controller:
Capable of controlling 5 x 8 LEDs
• 16 common output
• Duty .................... 1/8 or 1/16 (set by command)
• I/O ports ................................... 3 input, 2 output
• Serial data interface, TTL compatible
• Built-in RC oscillator
• Two-frame AC drive waveform
• Built-in LCD driver voltage-divider network
• CGROM ..................................... 240 characters
• TTL compatible CPU interface
• CGRAM ......................................... 8 characters
•
I
FEATURES
• Display data RAM .... 80 x 8 bits (80 characters)
• Supply voltage: .. Logic .................. 4.5V to 5.5V
LCD ................... 3.5V to 5.5V
• Recommended expansion segment driver:
SED1181 (64-bit output)
SED1681 (80-bit output)
• Package: ............ QFP5-100 pins (FOA, FOB, Foe)
AI pad (OOA, OOB, Doe)
SYSTEM BLOCK DIAGRAM
40SEG
DATA
CPU
SED1280
CONTROL
8 CHAR
16COM
I
303
~
X
2 LINES
I
SED1280
•
BLOCK DIAGRAM
SWS
Register
LED
Register
~
SWS
Driver
SWSI-8
LEI -5
~
(!l
SID
SCK
go
"j;
1=
SOD
lMHz
1278 core
250kHz
00
ICGRAM I
1278
Write
Control
ICGROM I
FF
Test Mode Register
Expansion Output Port
Register
304
SEGI - 40
COMI-16
DATA OUT
XSCL
LP
FR
EOI-2
•
"tI
Z
o
c:
-I
oowwwwwoowwww
WWWOOWWOOWWmmmmmmmmmmm
mmmmmmmmmQQQQQQQQQQQ
QQQQQQQQQ~~~~~~~~~~ro
~N~~mm~oo~o~row~~m~~mo
VSS
V1
V2
V3
V4
V5
LP
c.>
~
XSCL
VDD
FR
DO
SCK
SID
RST
SWC10
SWC9
SWCB
SWC7
SWC6
SWC5
SWC4
SWC3
SWC2
SWC1
SWSB
SWS7
SWS6
SWS5
SWS4
SWS3
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG2B
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG3B
SEG39
SEG40
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COMB
COM7
-"8
.~!
~~~~~n~Cii~§~~
cncn
> >
0
00
•
0
PIN DESCRIPTION
Number
Name
1
OSC1
Oscillator feedback resistor connection or external clock input
Oscillator feedback resistor connection
2
OSC2
3
V1
4
V2
Description
LCD driver voltage monitoring outputs
5
V3
LCD driver supply voltage
6
Vss
Negative supply
7
VDD
Positive supply
8
CK
Serial data clock input
9
SI
Serial data input
10
CS
Active-LOW chip select input
Command/data select input
11
C/O
12 to 15
COMOtoCOM3
16
VREG
17 to 48
SEGO to SEG31
LCD common driver outputs
Regulated voltage monitor output
LCD segment driver outputs
317
I
SED1510
•
PINOUT (SED1510FOE)
SE01510FOE
NC
NC
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
NC
NC
SEGl
SEGO
VREG
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
COM3
COM2
COMl
NC
NC
16
•
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
NC
OSC1
OSC2
V1
V2
V3
VSS
NC
VOO
CK
SI
CS
C/O
COMO
NC
NC
COM1
COM2
COM3
VREG
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
SEGO
SEG1
NC
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
NC
NC
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
NC
SEG14
SEG15
318
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin Name
SEG16
SEG17
SEG18
SEG19
NC
NC
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
NC
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
NC
SED1510
•
AC ELECTRICAL CHARACTERISTICS
Parameter
VOO = OV, Vss = -5.0 ± 0.5V, Ta = -20 to 75°C
Symbol
Condition
Min
Typ
CK period
tCYC
900
tPWL1
-
ns
CK LOW-level pulsewidth
-
CK HIGH-level pulsewidth
tPWH1
-
ns
SI to CK setup time
-
ns
Max
Unit
400
tOW1
-
100
-
CK to SI hold time
tOH1
-
200
-
-
ns
CS LOW-level pulsewidth
tPWL2
7200'1
-
-
ns
CS HIGH-level pulsewidth
tpWH2
-
400
-
ns
tOW2
Referenced to the rising edge
of the first CK cycle
100
-
-
ns
CK to CS hold time
tOH2
Referenced to the rising edge
of the eighth CK cycle
200
-
-
ns
C/O to CK setup time
tOW3
Referenced to the rising edge
of the eighth CK cycle
9
-
-
J.ts
CK to C/O hold time
tOH3
Referenced to the rising edge
of the eighth CK cycle
1
-
-
J.ts
-
50
ns
-
50
ns
-
CS to CK setup time
-
Rise time
tr
Fall time
tl
tPWL2
~
400
8tcYC
-
-
ns
*1. !eye x 8
VOO = OV, Vss = -6.0 to -1.5V, Ta = -20 to 75°C
Parameter
Symbol
Condition
Max
Unit
Min
Typ
10
-
-
4.5
-
-
J.ts
4.5
-
-
J.ts
-
J.ts
-
-
J.tS
J.tS
J.tS
SI to CK setup time
tOW1
-
CK to SI hold time
tOH1
-
CS LOW-level pulsewidth
tPWL2
CS HIGH-level pulsewidth
tPWH2
-
4.5
-
tOW2
Referenced to the rising edge
of the first CK cycle
1.2
-
-
CK to CS hold time
tOH2
Referenced to the rising edge
of the eighth CK cycle
2.3
-
-
J.tS
C/O to CK setup time
tOW3
Referenced to the rising edge
of the eighth CK cycle
100
-
-
J.ts
CK to C/O hold time
tOH3
Referenced to the rising edge
of the eighth CK cycle
11
-
-
J.tS
50
ns
50
ns
CK period
tCYC
CK LOW-level pulsewidth
tPWL1
CK HIGH-level pulsewidth
tPWH1
-
CS to CK setup time
Rise time
tr
Fall time
tl
tPWL2
~
-
*1. !eye x 8
319
1.2
8tcYC
2.3
80'1
-
-
J.ts
J.tS
I
SED1510
~-------------tpWL2
----------------y,-
-----------~'r- t~
DH2
~
CK
81
C/D
•
______~f==~tD~W~l--~-t~D~H~'~====
_____~t------------------tDW3
~I. tDH3~
Timing Measurement
--------~~~g-:-~~-~=~~------g-:~-~~~=~~~~--------
320
SED1510
~----------------------------------------------------------•
•
FUNCTIONAL DESCRIPTION
Command/Data Register
The command/data register c~rises an 8-bit shift register and a 3-bit counter. The counter is reset and reenabled on the falling edge of CS. The CK counter is initialized when the built-in timing generator circuit (CR
oscillating circuit) starts oscillating. The counter is incremented, and the serial input data is shifted into the
register on the rising edge of CK. The data is input msb-first as shown in the following figure.
C/O is sampled, and the register data is latched into either the display data memory or the command decoder
on every eighth rising edge of CK. C/O should be set HIGH when a command is input, and LOW, when display
data is input.
cs
~
I
81
CK
I
-
C=>
C/D
•
Display Data Memory
The format of the 32 x 4-bit memory is shown in the following figure.
o
Address
2
3
4
5
6
o
Bit
2
3
321
7
8· - - - - - 29
30
31
SED1510
Each 8-bit display data byte loaded from the command/data register is stored in two consecutive addresses
as shown in the following figure. The upperfour bits are stored atthe location specified by the address counter,
and the lower four bits, at the next location. The address counter is automatically incremented by two.
~3
~o
~0~7~--0-6-c--0-5-r~04~1
~3
~o
~0~3~1--0-2-'--0-1-'~0~0~
'I
Current Address + 1
Current Address
A single 4-bit word can be written to memory using the Data Memory Write command as shown in the
following figure. The lower four bits are stored at the location specified by the address counter. The
address counter is automatically incremented by one.
o
Note: x
o
x
03
02
01
00
=don't care.
The display data memory address of the SED1511 is automatically incremented by 2 when 8-bit display data
is stored.
Address 0 is automatically set when the built-in timing generating circuit (CR oscillating circuit) starts
oscillating after power on.
Display memory data is output on SEGO to SEG31 in synchronization with the COMO to COM3 output scan.
The correspondence between memory location and display position is shown in the following figure. When
the data is 0, the segment is OFF, and when 1, ON.
SEG SEG SEG SEG SEG SEG SEG SEG
01234567
SEG SEG SEG
29
30
31
0
COMO
COM1
Bit
COM2
2
COM3 -
3
o
2
3
4
5
6
7
29 30 31
~~------------------------------------~/
Address
322
SED1510
•
Address Counter
The 5-bit address counter is used to address display data memory. It is set by the Address Set command,
and automatically increments when data is stored in the memory. The counter automatically resets to 0 when
it increments past 31 as shown in the following figure.
[
•
Add~O
---_~ Address 31
]
Timing Generator
A low-power oscillator can be constructed using an external feedback resistor as shown in the following
figure.
L
J
OSC1~OSC2
RI
Alternatively, an 18 kHz external clock can be input on OSC1, and OSC21eft open, as shown in the following
figure.
l,j-----JC2
External clock
•
Common Counter
The timing generator clock signal is frequency-divided by the common counter to generate both the common
drive timing and the alternating frame timing.
•
Segment and Common Drivers
The 32 segment drivers and the four common drivers are 4-level outputs that switch between VDD and the
V1, V2 and V3 LCD driver voltage levels.
The output states are determined by the display data values and the common counter as shown in the
following figure. The outputs are used to drive a 1/3-bias, 1/4-duty LCD panel.
323
I
SED1510
Frame period
COMO
COM1
COM2
COM3
VooVI
V2
V3 -
COM1
COM2
COM3
0
0
0
0
0
0
All segments are OFF.
VooVI
V2
V3 SEGO
to
SEG31
COMO
0
Segments connected to COMO are ON.
VooVI
V2
V3 -
0
0
0
Segments connected to COM1 are ON.
VooVI
V2
V3 -
0
0
Segments connected to COM1 or COM3 are ON.
VooVI
V2
V3 All sagments are ON.
324
SED1510
•
Commands
The SE0151 OFoc samples C/O on every eighth rising edge of CK. If C/O is HIGH, the command/data register
contents are latched into the command decoder. The command decoder executes the following six
commands.
Address Set
Set the address counter to the value specified by 00 to 04.
02
03
Display ON
Turn all LCO segments ON. The display memory data is not affected.
Note: x
=don't care.
Display OFF
Turn all LCO segments OFF. The display memory data is not affected.
Note: x
=don't care.
Display Start
Retum to normal display mode. The display memory data is output to the display.
x
Note: x
I
x
I
x
I
x
x
I
=don't care.
Memory Write
Store the data 00 to 03 at the location specified by the address counter. The address counter is
automatically incremented by one. The other display memory locations are not affected.
02
Note: x
01
00
=don't care.
Reset
Reset the SE0151 OFoc. The SE0151 OFoc then enters normal operating mode, and the display turns
OFF.
Note: x = don't care.
325
I
SED1510
•
•
APPLICATION NOTE
Supply Voltages
In addition to VDD, there are three LCD supply voltages: V1, V2 and V3. V3 is supplied externally, whereas
V1 and V2 are generated internally. V1 , V2 and V3 are given by the following equations:
=VDD = VDD V3 = VDD V1
1/3 VLCD
V2
2/3 VLCD
VLCD
where VLCD is the LCD drive voltage. The voltages must be such that VDD ;:: V1 ;:: V2 ;:: V3.
LCD supply voltage connections when the LCD drive supply is connected to Vss are shown in Figure 1, below,
and the connections when the drive supply is independent of Vss, in Figure 2.
11
'------j
V ss
VDO
Vss
Figure 1. LCD drive supply connected to Vss
Figure 2. LCD drive supply not connected to Vss
When there is a lot of distortion in the LCD drive waveforms, connect bleeder resistors as shown in the
following figure.
1
VOO
R1
V1
R2
V2
R3
V3
Vss
326
SED1510
•
PAD LAYOUT AND COORDINATES (SED1510DoA)
000000000000
40
45
0
0
0
0
0
0
0
0
0
0
0
0
y
01510DoA
Lx
(0,0)
0
0
0
0
0
0
0
0
0
0
0
0
20
2500 11m
15
000000000000
5
•
Sectional Dimensions
10
•
Pad
o
~
327
Size of Pad Opening
I
SED1510
•
Pad Coordinates
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pad Name
OSC1
OSC2
V1
V2
V3
Vss
VOD
CK
SI
NC
NC
COMO
COM1
COM2
COM3
VREG
SEGO
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
unit:
X
y
-898
-738
-578
-418
-258
-98
63
223
383
543
703
863
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-898
-738
-578
-418
-258
-98
63
224
383
543
703
863
Pad No.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Note: The origin is the center of the chip. The chip size is 2,500 x 2,500.
328
Pad Name
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
X
898
738
578
418
258
98
-63
-223
-383
-543
-703
-863
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
Y
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
898
578
578
418
258
98
-223
-223
-383
-543
-703
-863
~m
SED1520/21
•
DESCRIPTION
The SED1520 is a dot matrix LCD driver LSI intended for display of characters and graphics. The bitaddressable display data which is sent from a microcomputer is stored in a built-in display data RAM and
generates the LCD drive signal.
The SED1520 incorporates innovative circuit design strategies to assure very low current dissipation and a
wide range of operating voltages. With these features, the SED1520 permits the user to implement highperformance handy systems operating from a miniature battery.
In orderforthe userto adaptively configure his system, the SED1520 family offers two application forms. One
form allows an LCD display of 12 characters x 21ines with an indicator with a single chip. The other is dedicated
to driving a total of 80 segments, enabling a medium-size display to be achieved by using a minimum number
of drivers.
•
FEATURES
• Low-power CMOS technology
• Recommended expansion segment driver: 80 bit
• Fast CPU 8-bit data interface (80xx, 68xx)
• Master/slave operation is supported
• Segment output ................................ 61 outputs
• Low power consumption ........................... 30j..lW
• Common output ................................ 16 outputs
• LCD voltage ....................................... 3.5 to 13V
• Duty cycle ........... SED1520 .......... 1/16 to 1/32
SED1521 ............ 1/8 to 1/32
• Single power supply ......................... 2.4 to 7.0V
• Package ................. QFP5-100 pin (FaA, FAA)
QFP15-100 pin (Foc, FAC)
AI pad (DOA, DAA)
Au bump (DaB, DAB)
TAB (TOA)
• Built-in display data RAM ................... 2560 bits
• Rich display command setting
• On-chip CR oscillation circuit
•
SYSTEM BLOCK DIAGRAM
COMO-COM15
28 CHAR
x2
LINES
'I
f
SEGO-SEG60
SEGO-SEG79
FR
SED1520
SED1521
Ck
VDD ~
M/S~
MIS
I ir
J
DATA
L
li J
l>CONTROL
CPU (68xx, 80xx)
329
GND
I
SED1520/21
• SED1520 family specifications:
Product
Applicable
No. of SEG
No. of COM
Name
On Chip
Clock Frequency
External
Driver
Drivers
Drivers
SED1520FoA
18kHz
18kHz
SED1520FoA.
61
16
18kHz
SED1521FoA
80
0
2kHz
SED1520FAA,
61
16
80
0
-
SED1521FoA
SED1520FAA
SED1521 FAA,
-
SED1521FAA
•
2kHz
HD44103CH
BLOCK DIAGRAM
-'
[E
u
ii'
Q
()
J
DISPLAY
TIMING
,.-
GENERATOR
"z a:
UJ
,
---1
>-->- " 0 ~
"o
Do-D7
()
()
UJ
"
a:
UJ
f-
~
-
Ao,CS
(OSCi)
-
(ii
;t
U)
E,R/W
a:
(RD)(WR)
;;:;
UJ
a:
0.
"
""«
z
,.-
::J
-
RES
I --
1i'
""
S
SG o -SG
5"
z
"~
0.
-()LL tW
0 1 0 ~()Q
(/)
w
ro«z ex::
0 0 0 0
BUSY
1: Busy (internal processing) 0: READY status
ADC
1: Rightward (forward) output
0: Leftward (reverse) output
0
6 Write Display Data 1 0 1
ON/OFF 1: Display OFF
0: Display ON
RESET 1: Resetting
0: Normal
Writes the data on the data These commands access a
Write Data
bus to RAM
previously-specified
Reads data from the Display address of the Display RAM,
7 Read Display Data 0 1 1
Read Data
RAM onto the data bus.
after which the column address is incremented by one.
Used to reverse the correspondence between the Display
8 ADC Select
1 0 0 1 0 1 0 0 0
o 0/1 RAM's column addresses and segment driver output ports
0: Rightward (forward) output
9
Static Drive
ON/OFF
10 Duty Select
1 0 0 1 0 1 0 0 1
o 0/1 display operation.
1: Static drive (Power Save) *7
1 0 0 1 0 1 0 1 0
o 0/1
11 Read Modify Write 1 0 0 1 1 1 0 0 0 0 0
12 End
1: Leftward (reverse) output
Selects normal display operation or static all-lit drive
0: Normal display operation
Selects the duty factor for driving LCD cells.
1: 1/32 duty
0: 1/16 duty
Increments the column address counter by one only when
display data is written but not when it is read.
1 0 0 1 1 1 0 1 1 1
o Cancels the Ready Modify Write mode.
1 0 0 1 1 1 0 0 0 1
o Resets the column address counter to 0 and page
Resets the Display START line to the 1st line in the register.
13 Reset
address register to 3.
*7. Power Save mode is entered by selecting static drive in Display OFF status.
336
SED1520/21
•
MPU INTERFACE (Reference)
o (a) SO-family MPU
Voo
I
Vee
Ao
Ao
A2- A 7
CS
--
Vee
-
Decoder
lORa
MPU
--':::-
SED1520
-
-
-
-
RO
RO
WR
WR
-
GNO
RES
I
-
00- 07
Do - 0 7
-cf>-
~
RESET
I
-
RES
Vss Vs
I
?; 7
o
(b) 5S-family MPU
Voo
I
Vee
Ao
Ao
Ao-A'3
CS
Vee
-
Decoder
\fMA
MPU
SED1520
Do - 0 7
GNO
I
E
E
-
RIW
RIW
-
-
RES
RES
~
RESET
--=-
00- 07
Vss Vs
l
7/ T
• The SED1520 (containing an OSCillator) does not have pin
AO, RD (E) and WR (RJiN).
es. The output ORed with es must be applied to pins
337
SED1520/21
•
Typical Connections With LCD Panel (Full dot LCD panel: 1 character = 6 x 8 dots)
o (a) Duty 1/16, 10 characters x 2 lines
,---------J\.
LCD
r' IJ,
16 x 61
1----.... --------------- 61
I
~E~
COM
SED1520
o (b) Duty 1/16, 23 characters x 2 lines
---\
-,;
Ii,
COM
LCD
1------------
---
16 x 141
------- 61
62 ------------------------141
<'E~
<'E~
SED1520
SED1521
•
o (c) Duty 1/32, 33 characters x 4 lines
------11, 1
-y
1
LCD
16
32 x 202
17
,
-
COM
1-----------.. ----.. ------ 61
62-------------------------141
142--------------------------202
<'E~
~E~
~E~
SED1520
Master
SED1521
SED1520
Slave
32
I\-
-
• SED1521 may be omitted. If it is not used, the panel consists of 32 x 122 dots.
Note: Type AA (using external clock) and type OA (containing an oscillator) cannot coexist for the same panel.
338
IJ--
COM
SED1520/21
•
PAD LAYOUT (SED1520D/SED1521D)
00000000000000000000
100
95
90
85
o 1
800
0
0
0
0
0
0
0
05
0
750
0
0
0
0
0
0
y
0
o 10
0
700
0
0
0
0
0
0
0
o 15
0
650
0
0
0
0
0
0
0
o 20
0
600
0
0
0
0
0
0
o 25
0
550
0
0
0
SED1520DAA
0
0
0
0
o 30
0
40
45
50
35
00000000000000000000
+-x
I..
•
AI pad
Chip Specification
Chip size
Chip thickness
Pad size
~I
4.80 mm
•
Chip size
7.04 x 4.BO
0.400 ± 0.025
0.10 x 0.10
Dimensions (mm)
7.04 x 4.BO
Chip thickness
0.525 ± 0.025
Pad size
0.132 x 0.111
Pad pitch
Bump height
339
-'-
Au bump pad
Chip Specification
Dimensions (mm)
7.04mm
0.199 min
0.020 +0.01 to -0.005
I
SED1520/21
•
PAD COORDINATES (SED1520DAB)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pad
Name
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
X
Y
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
504
704
903
1103
6507
6308
6108
5909
5709
5510
5310
5111
4911
4712
4512
4169
3969
3770
3570
3371
3075
2876
2676
2477
2277
2078
1878
1679
1479
1280
1080
881
681
482
159
159
159
159
No.
Pad
Name
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
340
X
Y
1302
1502
1701
1901
2100
2300
2499
2699
2898
3098
3297
3497
2696
3896
4095
4295
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
482
681
881
1080
1280
1479
1679
1878
2078
2277
2477
2676
2876
3075
3275
3474
3674
3948
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pad
Name
SEG3
SEG2
SEG1
SEGO
AO
CS
CL
E(RD)
RIW (WR)
Vss
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Voo
RES
FR
V5
V3
V2
MIS
V4
V1
COMO
COM1
COM2
COM3
COM4
X
Y
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4295
4095
3896
3696
3497
3297
3098
2898
2699
2699
2300
2100
1901
1701
1502
1302
1103
903
704
504
4148
4347
4547
4789
5048
5247
5447
5646
5846
6107
6307
6506
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
SED152A
CMOS DOT MATRIX LCD SEGMENT DRIVER
•
DESCRIPTION
The SED152A is the p-substrate version of the SED1521. It is used as an extension driver for the 8-bit or 16bit MCUs.
Refer to the SED1521 section for more information.
•
FEATURES
• Direct display of data read from display data RAM
RAM bit area
• Very low power dissipation 30llW at 2kHz external clock
• Supply voltages ............. VDD-VSS: 2.4V to 6.0V
VC5-VSS: 3.5V to 6.0V
"0" ...................... LCD off
"1" ...................... LCD on
• Fast 8-bit MPU interface compatible with 80- and
68- family microcomputers
• A variety of command functions, including:
Read/Write Display Data, Display ON/OFF, Set
Address, Set Display Start Line, Set Column
Address, Read Status, Static Drive ON/OFF, Select Duty, Read Modify Write, Select Segment,
Driving Selection, Save Power, etc.
• On-chip LCD driving circuits .. 80 drive set (segment)
• Duty rations to choose from
External input sync ........................... 1/8 to 1/32
341
I
THIS PAGE INTENTIONALLY BLANK
342
SED1522
•
DESCRIPTION
The SED1522 is a graphic LCD controller driver designed for use in a dot matrix LCD (Liquid Crystal Display)
system capable of displaying characters and graphics. The bit-addressable display data which is sent from
an 8-bit microcomputer is stored in a built-in display RAM which generates the signals required for driving
the LCD. The circuitry has been designed to ensure low power consumption and a wide range of operating
voltages, for use in high-performance handheld systems that run on batteries.
The SED1522 can use a single chip to drive an LCD of 13 characters by one line each plus an indicator. The
SED1522 can be used in master-slave combination. Moreover, the SED1521 segment driver is available for
expanding a system to enable 80-port output in order to construct mid-capacity displays using a minimal
number of drivers.
•
FEATURES
• Low-power CMOS technology .................. 30J..LW
• Master/slave operation is supported
• Fast CPU 8-bit data interface (80xx, 68xx)
• LCD voltage ................................... -3.5 to -13V
• Single power supply ......................... 2.4 to 7.0V
• 1/8 to 1/16 duty cycle
• Built-in LCD driver circuit .............. 69 segments
8 commons
• Package ..................... QFP5-100 pin (FOA,
QFP15-100 pin (Foc,
AI pad (DOA,
Au bump (DOB,
• Built-in display data RAM ................... 2560 bits
• Rich display command setting
• On-chip CR oscillation circuit
•
SYSTEM BLOCK DIAGRAM
COMO-COM7
COMO-COM7
14 CHAR x 2 LINES
I
I
SEGO-SEG69
SEGO-SEG69
FR
SED1522
VDD
SED1522
Ck
~
MIS
MIS
iiI'
}
DATA
J I
II 1
DCONTROL
CPU (68xx, 80xx)
343
r".
GND
FAA)
FAC)
DAA)
DAB)
I
SED1522
•
BLOCK DIAGRAM
T
f
!
6
lis
Circuit
80
.----
~ ~~fDO-D7
AO,CS
(OSCI)
RD,WR
(E,RiW)
>-r-
>-~
L
•
*
~
~
~
~
-GfJ
us
Holder
~
~
.2.2
.2
~
~
Display Data Ram
2,560 bit
r' ~
t
V4, V5
COMO - COM7
g f--<
SEGO- SEG68
!':::
Q)
---I
o
~
~ ~ '-8+_________-l
Register
VI, V2, V3,
f--<
jj
.1;
f'\ ~ --', ~
~
I'-----..-j-rt ------'
Low Addresiil,..
B8:0U
~
~
,L,
r:.g
l;;
-
r---<
:5 l;;
E 1:
'--
Line Address Decoder
'1 8 ~
,,_ :!: ~.
co
~
--- ~
Display Start Une Register
~===3:E===~
-
>-1
ir
J
~~~~ ~===3:E:==~
Generator ~
Line Counter
-
!
'--
Input and Output Buffer
Inner Bus
'--
......., Vas
......., VDO
PINOUT
OB2
OBS
OB4
OBS
OB6
OB7
.Y!>o
RES
FR
V5
V3
V2
MIS
V4
Vl
COMO
COMl
COM2
COM3
CO~ ----'ttITIT~~~~ITIT~~~~ITIT~~TIT~~
Model Name
Terminal No.
74
75
SED1522FoA
OSC1
OSC2
SED1522FAA
CS
CL
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG28
SEG30
SEG3l
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG4l
• The Common output COMO to COM7 of the Master LSI
corresponds COM15 to COMB on the Slave LSI.
344
SED1522
•
PIN DESCRIPTION
Terminal Name
DBO-DB?
AO
RES
CS
E
(RD)
-
RIW
(WR)
CL
FR
SEGO-SEG6S
COMO-COM?
(COM15-COMS)
M/S
Selects display data or instructions. HIGH: Display data. LOW: Instructions.
Resets the system and selects the interface type for a 6S-port/SO-port MPU.
HIGH: 6S-port MPU interface. LOW: SO-port MPU interface.
Chip Select input. LOW: Active level sensing.
ReadlWrite Enable signal when a 6S-port MPU is connected.
(Active-LOW Read Enable signal when an SO-port MPU is connected.)
ReadlWrite Select signal when a 6S-port MPU is connected.
HIGH: Read Select LOW: Write Select
(Active-LOW Write Enable input when an SO-port MPU is connected. Rising edge sensing.)
External clock input (only effective with external clock types).
I
LCD Frame (AC-conversion) signal input/output.
Segment output for driving the LCD.
Common output for driving the LCD.
Master/Slave Select signal.
Voo
5V power supply.
Vss
OV power supply (GND level).
V1, V2, V3, V4, V5
•
Function
Data input
Power supplies for driving the LCD. Voo;::V1 ;::V2;::V3;::V4;::V5
CLOCK OPTIONS
Model Name
Operating Clock
Internal oscillator
External clock
1SkHz
1SkHz
SED1522FoA
SED1522DoA
SED1522DoB
SED1522FAA
SED1522DAA
-
2kHz
SED1522DAB
345
Connectable Drivers
Package
SED1522FoA, SED1521 FOA
QFP5-100pin
SED1522DoA,SED1521DoA
AL pad chip
SED1522DoB, SED1521DOB
Au Bump chip
SED1522FAA, SED1521FAA
QFP5-100pin
SED1522DAA, SED1521DAA
AL pad chip
SED1522DAB, SED1521 DAB
Au Bump chip
SED1522
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
(VDD
=OV, VDD <': V1
<': V2 <': V3 <': V4 <': V5)
Symbol
Ratings
Unit
Supply voltage (1)
Vss
-8.0 to 0.3
V
Supply voltage (2)
V5
-16.5 to 0.3
V
V5 to 0.3
V
V1, V2
Supply voltage (3)
V3, V4
Input voltage
VI
Vss-0.3 to 0.3
V
Output voltage
Vo
Vss-0.3 to 0.3
V
PD
250
mW
Topr
-30 to 85
DC
-65 to 150
DC
Permissable loss
Operating temperature
Storage temperature
Soldering temperature
I
I
FP
Tstg
Die
-55 to 125
260 D
C for 10s (at the leads)
Tsol
346
SED1522
•
DC Characteristics
(VDD = OV, Ta = -20 to 75°C)
Parameter
Symbol
Condition
Operating Recommended operation
Vss
voltage (1 )*1 Potential operation
Recommended operation
V5
Operating Potential operation
V1, V2
voltage (2) Potential operation
Potential operation
V3, V4
VIHT
VIHC
HIGH input voltage
VIHT Vss=-3V
VIHC Vss=-3V
VILT
lOW input voltage
HIGH output voltage
LOW output voltage
Input leak current
Output leak current
VllC
VllT
Vss= -3V 10H= -5OIlA
IOL=3mA
IOL=2mA
IOL=120IlA
Vss=-3V
IOL=2mA
Vss=-3V
IOL=2mA
Vss=-3V
IOL=5OIlA
Applicable when FR is in a
high.·impedance stale
IV5=-5,OV
LCO driver ON resistance
RON
Ta=25°C
Static current consumption
External ClK
Oscillator
Active
External ClK
current
Oscillator
consumption
IDDQ
CS=Cl=VDD
During display fCL=2kHz
IDD(I)
Oscillating Irequency
Reset time
V5
V1, V2
V3, V4
IV5=-3.5V
V5=-5V
Rf=1MQ
During display fCL=2kHz
RI=IMQ
During access \oyc=200kHz
V5
O.2xVss
AO,DO-D7,E, RNV, CS O.2xVss
CL, FR, MIS, RES O.2xVss
AO,DO-D7,E,RNV,CS Vss
CL, FR, MIS, RES
Vss
CL, FR, MIS, RES
CL, FR, MIS, RES
00-07
FR
OSC2
00-07
FR
OSC2
00-07
FR
OSC2
00-07
FR
OSC2
Vss
Vss
Vss+2.4
Vss+2.4
0.2xVss
0.2xVss
O.2xVss
O.2xVss
-
-
-
AO.E.RIW,CS,CL,RES,MS pins
-1.0
00-07, FR pins
-3.0
SEGO-68
COMO-7
VDD
-
VDD
VDD
Vss=-3V,
During access toy.,=200kHz
Ta=25°C, 1=1 MHz All input terminals
Rt.=1.0Mn±2%, Vss= -5,OV
losc
Rt.=1.0Mn±2%, Vss= -3.ov
RES
tR
CIN
Min
Typ
-5.0
-5.5
-7.0
-13.0
-13.0
0.6xV5 -
AO,DO-D7,E,RNV,CS Vss+2.0
V5::.-5V,VSS",,-3
IDD(2)
Input terminal capacity
Vss
AO,DO-D7,E,RNV,CS
Vss=-3V
VllC Vss=-3V
VOHT
IOH=-3mA
VOHCl
IOH=-2mA
VOHC2
IOH=-120~
VOHT Vss= -3V 10H= -2mA
VOHCl Vss= -3V 10H= -2mA
VOHC2
VOLT
VOlCI
VOlC2
VOLT
VOlCI
VOlC2
III
IlO
Applicable Terminals
-
-
Max
--4.5
-2.4
-3.5
-
-
-
O.85xVss
-
O.8xVss
-
-
5.0
10.0
0.05
2.0
V
V
V
V
V
-
V
Vss+O.4
Vss+0.4
0.8xVss
0.8xVss
0.8xVss
0.8xVss
1.0
V
V
~A
3.0
7.5
50.0
1.0
5.0
15.0
4.5
-
6.0
300
12.0
500
-
150
300
-
5.0
18
16
8.0
21
21
1000
-
V
-
9.5
1.5
15
11
1.0
V
VDD
0.4xV5
VDD
VDD
VDD
VDD
Vss+0.8
0.8xVss
-
Unit
kn
~A
~A
~A
pF
kHz
*1, A wide range of operating voltages is guaranteed, except in case of abrupt voltage fluctuations during MPU access.
347
~s
I
SED1522
• AC Characteristics
o ReadlWrite timing for the 80-port MPU
Parameter
(Ta = -20 to 75°C, Vss = -5.0V±10%)
Condition
Min
Typ
Max
Unit
Signal
Symbol
AO,CS
tAHS
10
-
-
ns
tAws
20
1000
-
ns
tCYCS
tcc
200
-
ns
Data set-up time
toss
80
-
ns
Data hold time
tOHS
10
-
-
ns
lACcs
-
gO
ns
60
ns
Address hold time
Address set-up time
--
System cycle time
WR,RD
Control pulse width
00-07
RD access time
Output disable time
tOHS
CL=100pF
10
-
ns
*2. The ratings when Vss = -3.0V are approximately 100% higher than when Vss = -5.0V.
*3. The rise or fall time of input signals should be less than 15ns.
o
ReadlWrite timing for the 68-port MPU
(Ta = -20 to 75°C, Vss = -5.0V±10%)
Min
Typ
-
tCYC6 *4
1000
tAW6
20
lAH6
10
Data set-up time
tOS6
80
Data hold time
tOH6
10
-
ns
-
-
60
gO
ns
-
ns
Parameter
System cycle time
Signal
AO, CS
Address set-up time
RIW
Address hold time
00-07
Output disable time
Access time
Enable pulse width
Symbol
tOH6
tACC6
I READ
I WRITE
E
Condition
CL=100pF
10
100
tEW
80
Max
Unit
ns
ns
ns
ns
ns
ns
*4 tCYC6 indicates the cycle during which CS/E are HIGH; it does not indicate the cycle of the E signal.
*5 The ratings when Vss = -3.0V are approximately 100% higher than when Vss = -5.0V.
*6 The rise or fall time of input signals should be less than 15ns.
o
Control timing for 80-portl68-port display
Parameter
Signal
(Ta = -20 to 75°C, Vss = -5.0V±10%)
Condition
Max
Unit
LOW pulse width
twLCL
35
-
-
HIGH pulse width
tWHCL
35
-
-
-
30
150
Ils
Ils
ns
-
30
Rising time
CL
Falling time
FR delay time
Symbol
tr
(Input timing)
tOFR
150
ns
-2.0
0.2
2.0
Ils
(Output timing),
-
0.2
0.4
Ils
CL=100pF
*7. The ratings when Vss = -3.0V are approximately 100% higher than when Vss = -5.0V.
*8. The input timing of the FR delay time is determined by the SED1522 (Slave).
The output timing of the FR delay time is determined by the SED1522 (Master).
348
Typ
(Input timing)
tf
FR
Min
SED1522
•
o
Timing Chart
ReadlWrite timing for the 80-port MPU
AO,CS
=x
-
1 - - IAHB
tAws
1
•
tec
\
WR,RO
(WRITE)
.
tOH8
tose
X
-..
~tACC8 .......
00- 07
o
\
/
l
00- 07
(REAO)
X
.
tevee
tOH8
-t_}-
ReadlWrite timing for the 68-port MPU
.
E
teye6
i
- - - - - tAW6
1\
--"1 ..
IEW _ _
}
R/W
AO,CS
--
~
~ tOS6 -------..
I--- IAH6
K
--I--- IDH6
00- 07
(WRITE)
~tACC6-'"
00- 07
~
(REAO)
o
----r- IOH6
Control timing for 80-portl68-port display
CL
(05e1)
FR
349
I
SED1522
•
DISPLAY COMMANDS
(Based on the 80-port MPU; the RD and WR commands differ for the 68-port MPU)
Command
1 Display ON/OFF
2
Display START
Line
RDWRAO D7 D6 D5 D4 D3 D2 D1 DO
1 0 0 1 0 1 0 1 1 1 0/1
1 0 0 1 1
Column (Segment)
Address Set
1 0 0 0
Display RAM's data or the internal status.
o Display STAR1 Determines the line of RAM data to be displayed at the
address (0-31) display's top line (COMO).
3 Page Address Set 1 0 0 1 0 1 1 1
4
Function
Switches the entire display ON or OFF, regardless of the
o
Page Sets the page of the Display RAM in the page address
(0-3) register.
Column address
Sets the column address of the Display RAM in the column
(0-79)
address register.
Reads the status.
5 Status Read
0 1 0
BUSY
ILl>-OILW
U)oQU)
oC::
:J
"0
3
80 x 33-dot display data RAM
::J
~
~
>0..
is
~
"0
.0
~
Q)
"
E
:.J
-1
Column address decoder
I
Page address
register
E
~II
T
~
Display timing
generator circuit
..('~
7-bit column address register
I
Bus holder
t
t
I
Command decoder
I
I
t
Status
register
t
t
,
~-
~ J~ J ~
SR2
Oscillator
t
*
,,,
Microprocessor Interface
t
f
I/O buffer
f f
~ I
~
[
WR _
CS2_
AD
SR1
RD
CS1
DO
354
D1
!.
:g FR
:.
-D MIS
!.
7-bit column address counter
D2
~
D3 D4
r
[J
DS D6 D7
CL
SED1526 Series
•
SED1526 AND SED1527 PIN ASSIGNMENT
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEGO
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
Index
o
355
I
SED1526 Series
•
•
PIN DESCRIPTION
Power Supply
Pin
I/O
Number
of Pins
Function
VDD
Supply
+5V power supply. Common to microprocessor power supply Vee pin
Vss
Supply
Ground
1
V1 - V5
Supply
LCD driver supply voltages. The Set Power Control command can
switch the master (internal) and external power supply modes of these
pins. When external mode selects, the voltage determined by the LCD
cell is impedance-converted through a resistive divider or an operational amplifier depending on application. Voltages should meet the
following requirement:
5
VDD
~
V1
~
V2
~
V3
~
V4
~
1
V5
When master mode selects, these voltages are generated on the chip:
•
SED1526
SED1527
V1
1/5 V5
1/7 V5
SED1528
1/7 V5
V2
2/5 V5
2/7 V5
217 V5
V3
3/5 V5
5/7 V5
5/7 V5
V4
4/5 V5
6/7 V5
6/7 V5
LCD Driver Supplies
Pin
I/O
CAP1+
VOUT
0
0
0
0
0
VR
I
CAP1CAP2+
CAP2-
Function
DC/DC voltage converter capacitor 1 positive connection
Number
of Pins
1
DC/DC voltage converter capacitor 1 negative connection
1
DC/DC voltage converter capacitor 2 positive connection
1
DC/DC voltage converter capacitor 2 negative connection
1
DC/DC voltage converter output
1
Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
1
356
SED1526 Series
•
Microprocessor Interface
Number
of Pins
Pin Name
I/O
Description
DO - D7
(SI)
(SCl)
I/O
Data input/outputs. The 8-bit bidirectional data buses to be connected
to the standard 4/8-bit microprocessor data buses. When the serial
interface is selected, D7 is serial data input (SI) and D6 is serial clock
input (SCl).
8
AO
I
Control/display data flag is input. It is connected to the lSB of
microprocessor address bus. When low, the data on DO to D7 is control
data. When high, the data on DO to D7 is display data
1
CS1
CS2
I
Chip select input. Data input/output is enabled when CS1 is low and
CS2 is high.
2
RD (E)
I
• Read enable input. When interfacing to an 8080-Series microproces
sor and when RD is low, the SED1526 Series data bus output is
enabled.
1
• When interfacing to ~ 6800-Series microprocessor and when RIW
Enable E is high, RIW input is enabled.
WR (RIW)
• Write enable input. When interfacing to an 8080-Series microprocessor, WR is active low.
1
• When interfacing to a 6800-Series microprocessor, it will be in read
mode when R/W is high and it will be in write mode when RIW is low.
-
= "1"
RIW = "0"
RIW
Read
-
SR1, SR2
I
Write
Microprocessor interface select, and parallel/serial data input select.
SR1
SR2
0
1
1
1
6800 microprocessor bus (parallel input)
1
0
Serial input
0
0
Reset
Type
8080 microprocessor bus (parallel input)
* .!!!.§erial mode, no data can be read from RAM and DO to D5 are HZ.
RD and WR must be high or low.
357
2
I
SED1526 Series
•
LCD Driver Outputs
Number
of Pins
Pin
1/0
Functions
MIS
I
SED1526 Series masterlslave mode select input. Master mode selects when FR and CL are high, and slave mode selects when FR and
CL are low. It will be master mode when MIS is high and it will be slave
mode when MIS is low.
Model
Mode
OSC Circuit
FR
SED1526
SED1527
SED1528
Master
Valid
Output
Slave
Invalid
Input
1
CL
I/O
Clock inpuVouput when SED1526 Series selects master or slave
mode. The Clock Stop command can disable CL output when SED1526
Series is in master mode. It will be in ouput mode when MIS is high and
it will be in input mode when MIS is low.
1
FR
1/0
LCD AC signal inpuVoutput. When SED1526 Series selects master
mode, it must connect to LCD common driver FR pin. It will be output
mode when MIS is high and it will be input mode when MIS is low.
1
SEGn
0
LCD segment driver output. The display RAM and FR signal select the
segment driver output source.
RAM Data
1
0
COMn
0
Internal
1
0
0
Segment Driver-n Output
1
Voo
0
V5
1
V2
0
V3
1527)
or 64
(SED1528)
LCD common driver output. The IC internal scan signal and FR signal
select the common driver output source. The common scan sequence
is reversed in slave mode.
Scan Signal
COMS
FR Signal
FR Signal
1
V5
Voo
1
V1
0
V4
Indicator COM output. COMS pin is equivalent to following COM
output pin when DUTY+1 command is running:
SED1526
1/9 duty
1/17 duty
SED1527
1/17 duty
Indicator
COMS
1/33 duty
SED1528
1/33 duty
COM16
COM8
COM16
output
COM16
of slave
chip
358
80
(SED15261
1527)
or 32
(SED1528)
Common Driver-n Output
0
80
(SED15261
COM32
1
SED1526 Series
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Condition
Voo
-0.3 to +7.0
Voo
-0.3 to +6.0
Driver supply voltage range (1)
V5
-18.0 to +0.3
V
Driver supply voltage range (2)
V1, V2, V3, V4
V5 to +0.3
V
Input voltage range
VIH
-0.3 to Voo +0.3
V
Output voltage range
VO
-0.3 to Voo + 0.3
V
Allowable loss
Po
250
mW
-40 to +85
°C
Supply voltage range
IITriple voltage conversion
Operating temperature range
TOPR
I Flat package
Storage temperature
I Bear chip
Soldering temperature and time
----rt--
TSTG
TsoLDER
Vee
--..!..-...-GND
-65 to +150
-55 to +125
260 • 10 (at leads)
----rt----..,----
V
°C
°C· sec
I
VDD
---'---VSS
-~--
(Microprocessor side)
Unit
V1-V5, VOUT, VREG
(SED1526 series side)
Notes:
1. V1 to V5, VOUT, and VREG voltages are based on VDD = av.
2. Voltages VDD
~
V1
~
V2
~
V3
~
V4 ~ V5 must always be satisfied.
3. If an LSI exceeds its absolute maximum rating, it may be damaged permanently. It is desirable to use it under electrical
characteristics conditions during normal operation. Otherwise, an LSI malfunction or reduced LSI reliability may result.
4. The moisture resistance of the flat package may drop during soldering. Take care not to excessively heat the package resin
during chip mounting.
359
-------------
SED1526 Series
•
DC Characteristics
.
Voo = 5V ±10% Vss = OV. Ta = -40 to 85°C unless otherwise noted
Parameter
Power
Operational
voltage (1)
Operating
Operational
voltage (2) Operational
Operational
High-level input voltage
Symbol
Voo
Min
2.4
Input leakage current
Output leakage current
lCO driver ON resistance
III
ILO
RON
Static current consumption
Input pin capacity
Input voltage
:g Booster output voltage
e
i:3 Voltage regulator
operation voltage
c.. Voltage follower
I:
~ operation voltage
1000
CIN
Voo
VOUT
VOUT
-Vssx3
0.6xV5
V5
0.7 x Voo
Voo= 2.7V
0.8xVoo
Vss
Voo = 2.7V
Vss
IOH=-1mA
0.8xVoo
Voo= 2.7V IOH=-Q.5mA 0.8 x Voo
10H= 1mA
Vss
Voo= 2.7V 10L= 0.5mA
Vss
O.4xVoo
Voo= 2.7V
0.4xVoo
0.2xVoo
0.2xVoo
Voo=2.7V
0.2xVoo
0.2xVoo
Voo=2.7V
-1.0
-3.0
T. = 25°C I V5 = -Q.5V
I V5=-3.5V
CS = Cl=Voo
Ta = 25°C. f = 1MHz
2.4
Triple voltage conversion
-16.5
-16.5
V5 (1)
V5(2)
V5(3)
VREG
Applied to SED1526
Applied to SED1527
Applied to SED1528
Ta=25°C
en
low-level input voltage
V5
V1. V2
V3.V4
VIHC
Condition
VILC
0
:!! High-level output voltage
()
low-level output voltage
VOHC
VOLC
High-level input voltage
VIHS
~ low-level input voltage
VILS
~
:r
()
en
Schmitt voltage
I
·s
ED
Reference voltage
VH
-
-12.0
-16.0
-16.0
-2.0
*1. Although the wide range of operating voltage is guaranteed. a spike voltage change may have an effect on the
voltage assurance during access to the microprocessor.
*2. VOO and V5 operating voltage range. The operating
voltage range applies if an extemal power supply is used.
*3. Pins DO to 05. AO. CS1. CS2. RO (E). WR (RIW). MIS. Cl
and FR.
Typ
-
-
-
-
-
-
5.0
10.0
0.05
5.0
-
-3.1
Max
6.0
Unit
V
Pin
Voo
*1
-3.5
Voo
0.4xV5
Voo
Voo
0.3xVoo
0.2 xVoo
Voo
Voo
0.2 x Voo
0.2xVoo
0.8xVoo
0.8xVoo
0.6xVoo
0.6 x Voo
V
V
V
V
V5
*2
V1. V2
V3. V4
*3
V
*3
V
*4
V
*4
V
*5
V
*5
-
V
*5
~
~
k.O
*6
*7
1.0
3.0
7.5
50.0
3.0
8.0
6.0
~
-4.0
pF
V
V
V
-4.0
(TBO)
(TBO)
-4.0
V
V
V
V
-
SEGO-79
COSO-15
COMS
Voo
Input pins
VOUT
VOUT
*4. Pins DO to 07. FR and CL.
*5. Pins SI (07). SCl (05). SR1 and SR2.
*6. Pins AO. RO (E). WR (R1W). CS1. CS2. MIS. SR1 and
SR2.
*7. Applied if pins DO to 07. FR and Cl are high impedance.
360
SED1526 Series
•
o
Timing Characteristics
System Buses
Read/write characteristics I (8080-Series microprocessor)
Aa
t AH8 ----+
...-
-tAW8 ---..
CS1
(CS2-"1")
•
tCYC8
+---
WR, Ri5
tCCLW - - - - - - . . .
tCCLR
~L
\\
\\
..
I~ tDSS ------"
00-07
~\\
II
+-- tDSH
--'-1
){
(WRITE)
tCCHW
tCCHR
•
\\
}(
~tCH8_
+--tACC8
00-07
(REAO)
VSS = OV, VOO = 5.0V
Parameter
Address hold time
Address setup time
Signal
Symbol
AO
WR
RD
WR
RD
tOS5
taH8
System cycle time
Control
Control
Control
Control
L pulse width (WR)
L pulse width (RD)
H pulse width (WR)
H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
DO - D7
Min
Max
Unit
lAH8
tAW8
5
5
-
ns
ns
tCYC8
250
75
75
145
145
-
ns
tCCLW
tCCLR
tCCHW
tCCHR
80
10
-
ns
ns
-
80
60
ns
ns
tACC8
tCH8
Conditions
± 10%, T a = -40 to +85°C
CL
= 100pF
10
ns
ns
ns
ns
Vss = OV, Voo = 2.7 to 4.5V, Ta = -40 to +85°C
Parameter
Address hold time
Address setup time
Symbol
AO
lAH8
lAw8
10
10
tCYC8
500
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
185
185
285
285
tOS5
taH8
160
20
System cycle time
Control
Control
Control
Control
L pulse width (WR)
L pulse width (RD)
H pulse width (WR)
H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
Notes:
Conditions
Signal
DO - D7
lACC8
tCH8
CL = 100pF
Min
20
Max
-
180
120
1. tCCLW and tCCLR are limited depending on the overlap time of CS1 low (CS2 high) and WR or RD low.
2. The input signal rise and fall times must be within 15 nanoseconds.
3.
All signal timings are limited based on 20% and 80% of VDD voltage.
361
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
SED1526 Series
o
System Buses
Read/write characteristics II (6800-Series microprocessor)
~
AO
~tAH6--..!
.....-..-tAW6~
CSt
(CS2-"t")
tEWLW
t EWLA
\\\l\\
RD(E)
.
II
leye6
.
II
\\
\\
tEWHW
tEWHR
X-
WR(RIW)
I+----
t OS6
--'
. - t OH6
--1
00-07
(WRITE)
I------ IACe6 -----to-
..... t OH6
00-07
(READ)
Vss = OV, Voo = 5.0V
Parameter
± 10%, Ta = -40 to +85°C
Signal
Symbol
System cycle time
AO
tCYC6
250
-
ns
Address setup time
Address hold time
WR
(RIW)
tAW6
tAH6
20
10
-
ns
ns
DO- D7
tOS6
tOH6
80
10
Data setup time
Data hold time
Output disable time
Access time
Enable low
pulse width
Enable high
pulse width
Read
tOH6
tACC6
RD (E)
Write
Read
Conditions
RD (E)
Write
CL = 100pF
Min
10
-
tEWLR
85
tEWLW
75
tEWHR
135
tEWHW
145
Max
-
Unit
ns
ns
60
90
ns
ns
-
ns
-
ns
ns
ns
Vss = OV, Voo = 2.7 to 4.5V, Ta = -40 to +85°C
Parameter
Conditions
Min
Signal
Symbol
System cycle time
AO
tCYC6
500
Address setup time
Address hold time
WR
(RIW)
tAW6
tAH6
40
20
DO- D7
tOS6
tOH6
160
20
Data setup time
Data hold time
Output disable time
Access time
Enable low
pulse width
Enable high
pulse width
Notes:
Read
RD (E)
Write
Read
Write
CL = 100pF
tOH6
IACC6
RD (E)
20
-
Max
ns
120
180
ns
ns
ns
ns
tEWLR
185
tEWLW
145
tEWHR
285
-
tEWHW
325
-
1. IEWHR and tEWHW are limited depending on the overlap time of CS1 low (CS2 high) and RD (E) high.
2. The input signal rise and fall times must be within 15 nanoseconds.
3.
All signal timings are limited based on 20% and 80% of VDD voltage.
362
Unit
-
ns
ns
ns
ns
ns
ns
SED1526 Series
o
Serial Interface
CS1
•
tcss
~
\
(CS2="1 ")
~
t CSH -
,
- tSAH -
tSAS ---+
-
~:
AO
/
~
~
tSCYC
-tSLW-
\ t<-
Serial clock (D6 )
_t
~
Serial data (D7) _ _
D_1_d_a_ta_ _
II
~
1\
-- 5<___
-
-tSHW_t
_ _s_os_D_O_d_at_a_SO_H
D_7_d_a_t_a_
Vss = OV, Voo = 5.0V ± 10%, T a = -40 to +S5°C
Parameter
Serial clock cycle
Serial clock H pulse width
Serial clock L pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS serial clock time
Signal
Symbol
Serial
clock
tSCYC
tSHW
tSLW
500
150
150
AO
tSAS
tSAH
120
200
Serial
data
tsos
tSOH
120
50
CS1
(CS2 = "1")
tcss
tCSH
30
400
Signal
Symbol
Serial
clock
tSCYC
tSHW
tSLW
1000
300
300
-
-
ns
ns
ns
AO
tSAS
tSAH
250
400
-
ns
ns
Serial
data
tsos
tSOH
250
100
-
ns
ns
CS1
(CS2 ="1")
tcss
tCSH
60
SOO
Conditions
Min
Max
Unit
-
ns
ns
ns
-
ns
ns
ns
ns
ns
ns
Vss = OV, Voo = 2.7 to 4.5V, Ta = -40 to +S5°C
Parameter
Serial clock cycle
Serial clock H pulse width
Serial clock L pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS serial clock time
Notes:
Conditions
1. The input signal rise and fall times must be within 15 nanoseconds.
2. All signal timings are limited based on 20% and 80% of VDD voltage.
363
Min
Max
-
Unit
ns
ns
I
SED1526 Series
o
Display Control Timing
FR
Vss
Parameter
Low-level pulse width
Signal
Symbol
Conditions
Min
CL
tWLCL
(TBD)
(TBD)
-
twHCL
(TBD)
(TBD)
-
High-level pulse width
tf
FR
tDFR
-
Signal
Symbol
Conditions
Min
CL
tWLCL
(TBD)
(TBD)
-
twHCL
(TBD)
(TBD)
-
tr
-
tr
Fall time
-
Vss
Parameter
Low-level pulse width
High-level pulse width
Rise time
Fall time
FR delay time
o
Typ
-
Rise time
FR delay time
=OV, VDD = 5.0V ± 10%, Ta =-40 to 85°C
tf
FR
tDFR
Max
-
Unit
J.!s
J.!s
ns
30
120
-
30
120
ns
-1.0
0.2
1.0
J.!s
= OV,VDD =2.7 to 4.5V, Ta =-40 to 85°C
-2.0
Typ
Max
-
Unit
J.!s
J.!s
ns
60
240
60
240
ns
0.4
2.0
J.!s
Output Timing
Vss
Parameter
FR delay time
=OV, VDD =5.0V ± 10%, Ta =-40 to 85°C
Conditions
CL
= 100pF
Vss
Parameter
FR delay time
Notes:
= OV, VDD =2.7 to 4.5V, Ta =-40 to 85°C
Conditions
CL = 100pF
1. The FR delay input timing must be set in slave mode; the FR delay output timing must be set in master mode.
2. All signal timings are limited based on 20% and 80% of Voo voltage.
364
o Reset Timing
i -tRW-t
Reset input
(SR1 and SR2
are lOw.)
.
-
tR~t
~~~~~al circuit ______----'Xr--o-u-r-in-g-re-s-e-t--X-E-n-d-o-f-r-es-e-t-
Vss = OV, Voo = 5.0V ± 10%, Ta = -40 to +85°C
Parameter
Signal
Reset time
Reset low pulse width
Reset inpu
Symbol
Conditions
Min
Typ
tR
1.0
tRw
1.0
-
Max
-
Unit
I1s
I1s
Vss = OV, Voo = 2.7 to 4.5V, Ta = -40 to +85°C
Parameter
Signal
Symbol
Reset inpu
Reset time
Reset low pulse width
Notes:
Conditions
Min
Typ
tR
3.0
tRW
30
-
Max
-
I1s
I1s
1. tR (resettime) represents the period from the rising edge of reset inputto the end of internal circuit reset. The SED1526
Series can operate normally after tR.
2. tRW specifies the minimum pulse width of reset input. The low pulse exceeding tRW is required for reset.
3. The input signal rise and fall times must be within 15 nanoseconds.
4. All signal timings are limited based on 20% and 80% of Voo voltage.
365
_____
Unit
~·~O_""
0
_____ _
I
SED1526 Series
•
Commands
The table below lists all available commands. The SED1526 Series uses a combination of AD, RD and WR
(or R/W) signals to identify data bus signals. Since the chip analyzes and executes each command using the
internal clock only (no external clock is required), its processing speed is very high and its busy check is
usually not required.
SED1526 Series Command Table
Command
Code
AO RD WR D7 D6 D5 D4 D3 D2 Dl
(1)
Display ON/OFF
0
1
0
1
0
1
0
(2)
Initial Display Line
0
1
0
1
1
0
Initial display address
(3)
Set Page Address
0
1
0
1
0
1
1
(4)
Set Column Address
0
1
0
0
(5)
Read Status
0
0
1
(6)
Write Display Data
1
1
0
1
1
1
Function
DO
0/1 Turns on LCD panel when goes
high, and turns off when goes
low.
Specifies RAM display line for
COMO.
1 Page address Sets the display RAM page in
Page Address register.
Column address
Status
0
Sets RAM column address in
Column register.
0
0
Write data
Reads the status information.
Writes data in display RAM.
(7)
Read Display Data
1
0
1
(8)
ADC Select
0
1
0
1
0
1
0
0
0
0
0/1
DO=O
DO = 1
(9)
Static Drive ON/OFF
0
1
0
1
0
1
0
0
1
0
0/1
Normal indication when low, but
full indication when high.
(10) Duty Select
0
1
0
1
0
1
0
1
0
0
0/1
Selects LCD driver duty of 1/8 (1/
16) when low, and 1/16 (1/32)
when high.
(11) Duty+1
0
1
0
1
0
1
0
1
0
1
1
Selects normal LCD driver duty
when low, and selects the duty
added bj' 1 when high.
(12) Read-Modify-Write
0
1
0
1
1
1
0
0
0
0
0
Increments Column Address
counter during each write when
high and during each read when
low.
(13) End
0
1
0
1
1
1
0
1
1
1
0
Releases the ReadlModifylWrite
(14) Reset
0
1
0
1
1
1
0
0
0
1
0
Resets internal functions.
(15) Set Power Control
0
1
0
1
0
1
1
0
(16) Set Electric Control
0
1
0
1
0
0
Electric control value
(17) Clock Stop
0
1
0
1
1
1
0
(18) Power Save
Reads data from display RAM.
Read data
0
Power control Selects various power circuit
functions.
1
- - - - - - - - -
1
-
Sets V5 output voltage to
Electronic Control register.
0/1
Stops clock output at CL when
low, and stops clock when high.
-
A combination of Display OFF and
Static Drive ON commands.
Note: Do not use any other command, or a system malfunction may result.
366
Normal
Inverse
•
PACKAGE DIMENSIONS
Plastic QFP5-128pin-S1
0.929 ± 0.016 (23.6 ±o.•)
0.787 ± 0.004 {20.0 ±O.1)
r+1 r+1
0
'"
:!
~
-H
-H
i
~
~ ~
I
0.071
(1.8)
Unit: inches (mm)
~~~._o
~88888~8~~8~c8$~~~§~~ffi~~~
DCCCCCCCDCDDDDDCDDDDDDDCD
~
COMO
COMT
CCM8
COMO
COM1O
COM"
COM"
COM"
COM14
COM1S
COM16
SEGO
SEGl
SEG2
SEGO
SEo.
SEGS
SEGO
SEG7
SEGS
SEGS
SEG10
SEG,1
SEG12
SE01a
SEG14
SEG15
~
~
~
~
Aluminum pad chip
• Chip size ...........
• Chip thickness ..
• Pad opening .....
• Pad pitch ...........
C
C
ColO
C
C
C
C
C45
C
C
C
C
C'"
C
C
C
C
C55
C
C
C
C
ceo
C
C
C
C
12
~
~
i
:B
Ii
:£
§
[JDDDDDDDDODOCDCDODOCDCDOODODDDODDDDDDD
367
C
C
C
1250
C
C
C
C
120 C
C
C
C
C
1150
C
C
C
C
1100
C
C
C
C
105C
C
C
SEG7B
SEG7B
SEG"
8EG7e
SEG7S
SEG74
SEG73
SEG7'
SEG71
SEG70
SEGS9
SE...
SEG67
SEGSS
BEG"
SE'"
SEGII3
SEG"
SEGSl
SEG60
SEG59
SE. . .
SEG57
SEG56
SEGSS
SEG54
o
5.92 x 4.86mm
O.4mm
81 x 8511m MIN
130l1m MIN
Gold bump chip (reference)
• Chip size ........... 5.92 x 4.86mm
• Chip thickness .. O.4mm
• Bump size ......... 70.9 x 74.711m MIN
• Bump height ..... 22.5 ± 5.511m
SED1526 Series
•
PAD COORDINATES
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PIN
Name
V1
V2
V3
V4
V5
VR
Voo
Your
CAP2CAP2+
CAP1CAP1+
Vss
MIS
SR1
SR2
WR
RO
CS2
CS1
AO
FR
CL
00
01
02
03
04
05
06
07
COMO
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
X
Y
2767
2637
2507
2377
2246
2116
1985
1857
1727
1522
1318
1113
553
356
226
95
-35
-165
-295
-425
-555
-719
-849
-979
-1109
-1239
-1369
-1500
-1630
-1760
-1890
-2069
-2199
-2329
-2459
-2589
-2719
-2802
-2802
-2802
-2802
-2802
-2802
2106
2106
2106
2106
2106
2149
2176
2176
2176
2176
2176
2176
2166
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
2185
1624
1524
1393
1263
1133
1003
No.
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
PIN
Name
COM12
COM13
COM14
COM15
COM16
SEGO
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
368
X
Y
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2802
-2516
-2367
-2218
-2088
-1957
-1827
-1697
-1567
-1437
-1307
-1177
-1046
-916
-786
-656
-526
-396
-266
-135
-5
125
255
873
743
612
482
352
193
63
-67
-197
-327
-457
-588
-718
-848
-978
-1108
-1238
-1368
-1499
-1629
-1759
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
No.
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PIN
Name
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
X
y
385
515
646
776
906
1036
1166
1296
1426
1557
1687
1817
1947
2077
2226
2375
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
2802
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-2185
-1932
-1802
-1672
-1541
-1411
-1281
-1151
-1021
-891
-760
-599
-469
-339
-209
-78
52
182
312
442
572
703
833
963
1093
1223
1353
SED1530 Series
DOT MATRIX LCD DRIVER-CONTROLLER
•
DESCRIPTION
The SED1530 Series are intelligent CMOS LCD controller-drivers with the ability to drive alphanumeric and
graphic displays. The LSI communicates with a high-speed microprocessor, such as the Intel80xx and 68xx
family, through either a serial or 8-bit parallel interface. It stores the data sent from the microprocessor in the
built-in display data RAM (65 x 132 bits) and generates an LCD drive signal.
•
FEATURES
• Low-power CMOS technology
• 32-level contrast adjustment by software
• Direct interface to both 80xx and 68xx MPU
• 2.4V to 6.0V supply voltage
• Support 8-bit parallel and serial interface
• -4.5V to -16V LCD voltage
• On-chip display data RAM ............ 132 x 65 bits
• Operating temperature ................... -40 to 85°C
• On-chip DC/DC converter for LCD voltage
• Low power consumption ............................ 80IJA
• On-chip CR oscillator circuit
• Package
TAB ................................... T**
• Supports master/slave mode
•
•
• Voltage regulator, low-power voltage follower
AI pad Die ....................... D*A
• -.17%/oC temperature gradient
Au bump Die ................... D*B
AVAILABLE MODELS
Name
Duty
SED1530DO*
11.33
LCD Bias SEG Driver COM Driver Display Area
115,111>
100
33
33 x 100
COM single-side assignment
Remarks
SED1530DA*
11.33
115,111>
100
33
33 x 100
COM dual-side assignment
SED1531DO*
111>5
111>,118
132
0
65 x 132
SED1635 is used for COM
SED1532DO*
111>5
111>,118
100
33
65 x 200
COM single-side right assignment
SED1532DB*
111>5
111>,1Al
100
33
65 x 200
COM single-side left assignment
SYSTEM BLOCK DIAGRAM
65 COM
26 CHAR X 4 LINES
-
11132SEG
Data
YSCL
SED1531
CPU
FR
DYO
SED1635
Control
-
II
V1
V4
V5
369
i
r
I
SED1530 Series
•
BLOCK DIAGRAM
~ ------------------ ~
I
r--
c;; ~
g
0 ---- 0
II II
C
0
Segment
Driver
Common
M
Driver
S
II
CAP1+
CAP1CAP2+
CAP2CAP3-
8
Shift
Register
Power
Supply
Circuits
~
Display Data Latch
-
,!!l
:::l
I:!
VOUT
VR
(3
0
:::l
(3
0
:::l
"5
~
I:!
(I)
(I)
I!!
"~.,
:::i
"
.Q.
H
"
"
:::l
:::i
0
()
.,
t::
" ~=
:::i
i
(I)
is
T
Column Address Decoder (132)
Page Address
Register
a:
.Sl
c
Display Data RAM
(132 x 65)
" &
m
:;
%
*.,.,
"c,
"~
.~
ien.,
,----
lii
.,- '--rColumn Address Counter (8 bit)
.,- '--rColumn Address Register (8 bit)
-
I
Display
Timing
Generation
Circuit
FRS
FR
CL
DYO
DOF
MIS
1
I Bus Holder
Command
Decoder
II
I
II
I
I
I
I
I
II
I
1/0 Buffer
MPU Interface
1 1 1 1 1 1 1 1
CSI CS2 AO
Oscillator
Circuit I
I Status
RD WR C86 PIS RES
370
11
11 1
VSl
SED1530 Series
•
PINOUT
1----------------------------------------------------------------------------------.
00
V5
V4
V3
V2
Vl
VOO
VR
V5
CAP2CAP2+
CAP1CAP1+
CAPS-
VOUT
VSS
D7(SI)
06 (SCL)
05
04
03
02
Dl
00
VOO
AD (E)_
WR(RJW)
AO
CBS
CS2
CSl
PIS
RES
MIS
VSl
OOF
CL
OYO
FR
FRS
COMS
0131
•
PINOUT TABLE
Model
Output
SED1530*0*
0
1
SEGO --------------------------------------------------------- SEG99 , COMO -------------------- 31
'COM31 -------------------- 0
SED1530*A*
0
1
COM15 -- 0 ,SEGO --------------------------------------------------------- SEG99 ,COM16 31
COM16 31 :
'COM15 -- 0
SED1531 *0*
00 to 015
: 015 to 031 : 032 ----------------------------- 099 : 0100 to 0115 : 0116 to 0131
S EGO ------------------------------------------------------------------------------------------- SE G 131
SED1532*0*
0
1
--------
SEG99 ---------------------------------------------------------------------------- SEGO ,COM31 -- 0
'COMO-- 31
SED1532*B*
0
1
COMO -- 31 ,SEGO --------------------------------------------------------------------------- SEG99
COM31 -- 0'
Note:
• "0" and "1" indicate the mode of the D3 output mode select register.
371
I
SED1530 Series
•
•
PIN DESCRIPTION
Power Signals
Pin
1/0
Function
Number
of Pins
Voo
Power
Connected to +5V power. Connected with MPU power supply Vee pin.
2
Vss
Power
av, connected to system GND.
1
Vl - V5
Power
Multi-level power for LC driver. Transforms impedance using
resistive voltage divider or op amps in order to apply the voltage
determined for each LC cell. The voltage levels are based on Voo, and
must conform to the relationship below:
6
Voo ;::
va ;:: V2 ;:: V3 ;:: V4 ;:: VS
When the master operation power supply is ON, the internal power
supply circuitry supplies the Vl - V4 voltages shown below. The
voltage levels are selected using the LCD bias set command.
SED1530DO'
1/5 x V5 1/6 x V5
1/5xV51/6xV5
V2
x V5 216 x V5
3/5 x V5 4/6 x V5
4/5 x V5 5/6 x V5
215
V3
V4
•
SED1530DA*, SED1531DO*, SED1532D**
V1
215
x V5
216
x V5
3/5 x V5 4/6 x V5
4/5 x V5 5/6 x V5
LCD Power Circuit Pins
Function
Number
of Pins
Pin
1/0
CAP1+
0
Voltage step-up capacitor, positive side connection pin.
Connect the capacitor between this pin and CAP1-.
1
CAP1-
0
Voltage step-up capacitor, negative side connection pin.
Connect the capacitor between this pin and CAPl +.
1
CAP2+
0
Voltage step-up capacitor, positive side connection pin.
Connect the capacitor between this pin and CAP2-.
1
CAP2-
0
Voltage step-up capacitor, negative side connection pin.
Connect the capacitor between this pin and CAP2+.
1
CAP3-
0
Voltage step-up capacitor, negative side connection pin.
Connect the capacitor between this pin and CAPl +.
1
VOUT
0
Voltage step-up output pin. Connect the capacitor between this
terminal and Vss.
1
VR
I
Voltage regulator pin. Use a resistive voltage divider to provide voltage
between Voo and VS.
1
372
SED1530 Series
•
System Bus Interface Signals
Number
of Pins
Pin
I/O
Function
D7 - DO
(SI)
(SCL)
110
8-bit bi-directional data bus, normally connected to a standard 8-bit or
16-bit MPU data bus.
8
When serial interface is selected:
D7: Serial Data Input Pin (SI)
D6: Serial Clock Input Pin (SCL)
AO
I
Normally the LSB of the MPU address bus is connected to this pin to
provide data/command selection:
1
0: DO - D7 indicate display control data
1: DO - D7 indicate display data
RES
I
Reset to initial settings by setting RES to "L".
1
--
The reset operation is performed according to the RES signal level.
CS1
CS2
I
Chip Select input pins. Data I/O is enabled by the combination below:
Pin Name
I
RD (E)
I
CS1
I
State
CS2
I
"L"
I
"H"
• When connected to an 80-series MPU:
Active "L"
2
1
-
This pin is connected to the RD signal from the MPU. When this
signal is "L" the SED1530 Series data bus is in output mode.
• When connected to a 68-series MPU:
Active "H"
This is the 68-series MPU enable clock input pin.
WR (RIW)
I
• When connected to an 80-series MPU:
Active "L"
1
-
This pin is connected to the WR signal from the MPU. The data
bus signals are retrieved at the rising edge of the WR signal.
• When connected to a 68-series MPU:
This is the read/write control signal input pin.
-
RIW = "H": Read
RJW = "L": Write
C86
I
MPU interface select pin:
1
C86 = "H": the 68-series MPU interface
C86 = "L": the 80-series MPU interface
PIS
I
1
Serial data inpuVparaliel data input selection pin:
PIS
Chip Select
Data/Command
Data
ReadIWrite
"H"
CS1/CS2
AO
DO - 07
RDIWR
"L"
CS1/CS2
AO
SI (07)
Write only
Serial Clock
SCL (06)
Note: RAM data read cannot be performed by serial data input. When
PIS = L, fix DO - D5 to HZ RD, and fix WR to either "H" or "L".
373
I
SED1530 Series
•
LCD Drive Circuit Signals
Number
of Pins
Pin
I/O
Function
M/S
I
This pin selects the master/slave operation of the SED1530 series
chips. The master operation outputs the signals necessaryforthe LCD
display. The slave operations input the signals necessary to synchronize the LCD display.
1
CL
I/O
This is the display clock I/O terminal.
1
When using the SED1530 Series chips in master/slave, the CL pins of
the chips must be connected.
When using in combination with a dedicated common driver, the
common driver YSCL pin must be connected to this pin.
M/S = "H": Output
M/S = "L": Input
FR
I/O
This is the LCD alternating current signal 110 pin.
1
When using the SED1530 Series chips in master/slave, the FR pins of
the chips must be connected. When using an SED1530 Series chip in
master mode, this pin must be connected to the FR pin of the dedicated
common driver.
M/S = "H": Output
M/S = "L": Input
DYO
0
This is the common activation output pin.
1
This pin is used only when the SED1530 Series chip is in master mode.
This pin must be connected to the common driver DIO pin. This pin is
HZ in slave mode.
VS1
DOF
0
110
This pin is used to monitor the voltage of the internal power supply.
1
This is the LCD display blanking control pin.
1
When using the SED1530 Series chips in master/slave, the DOF pins
of the chips must be connected.
When using in combination with a dedicated common driver(SED1635),
the common driver DOFF pin must be connected to this pin.
M/S = "H": Output
M/S = "L": Input
FRS
0
Static drive output pin.
1
This is effective only when in master mode, and is used with the FR pin.
This pin is HZ in slave mode.
(continued)
374
SED1530 Series
•
LCD Drive Circuit Signals (continued)
Pin
110
On
0
(SEG n)
(COMn)
Number
of Pins
Function
LC driver output
133
This output depends on the model type, as shown below:
SED1530*0*
Segment
00 - 099
SED1530*A*
016 - 0115
SED1531 *0*
SED1530*0*
SED1532*B*
00- 0131
00 - 099
032 - 0131
Column
0100 - 0131
00 - 015,
0116 - 0131
\
0100 - 0131
00 - 031
Segment Output Terminal
This is the output for driving the LC segments. Through combining the contents of the display RAM with the FR signal, a single
level can be selected from VDD, V2, V3, and V5:
RAM Data
H
L
Power Save
FR
H
L
H
L
-
I
On Output Voltage
Positive Display
Negative Display
VDD
V2
V5
V3
V2
VDD
V3
V5
VDD
Common Output Terminal
This is the output for driving the LC commons. Through combining the scan data with the FR signal, a single level can be selected
from VDD, V1, V4, and V5:
Scan Data
H
L
Power Save
COMS
0
FR
H
L
H
L
-
On Output Voltage
V5
VDD
V1
V4
VDD
This is a common output pin dedicated for the indicator.
Leave open if not used. This pin is functional only for the SED1530 and
SED1532. It is HZ for the SED1531.
375
1
SED1530 Series
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
(at 3x step-up)
VDD
(at 4x step-up)
Rating
Unit
-0.3 to +7.0
V
-0.3 to +6.0
V
-0.3 to +4.5
V
-18.0 to +0.3
V
Power supply voltage (2)
(VDD reference)
V5
Power supply voltage (3)
(VDD reference)
V1, V2, V3, V4
V5 to +0.3
V
VIN
-0.3 to VDD + 0.3
V
Output voltage
VO
-0.3 to VDD + 0.3
V
Operating temperature
Topr
-30 to +85
°C
-55 to +100
°C
-55 to +125
°C
Input voltage
Storage temperature
TCP
------~t~-----GND _______L -_ _ _ __
Vcc
TSTR
Bare chip
VDD
Vss
-----.t----lr--
VDD
_
VREG
------"------- V1-V5, VOUT
SED1530 Series Chip
System Side
Notes:
1. V1 - V5, VOUT, and the V5 voltage are all values based on VDD = OV.
2. The voltages of V1, V2, V3 and V4 must always fulfill the relationship VDO ;:: V1 ;:: V2 ;:: V3 ;:: V4 ;:: V5.
3. Permanent damage to the LSI may result ifthe absolute maximum ratings are exceeded during use. Under normal operation,
use should be within the range of the electrical characteristics listed. Violations of these conditions may cause the LSI to
malfunction or may cause loss of reliability in the LSI.
376
SED1530 Series
•
DC Characteristics
Vss = OV, VDD = 5V ±10%, Ta = -40 to 85°C
Parameter
Symbol
Condition
Power
Recommended
VDD
supply
operation
voltage
Possible
VDD
(1)
operation
Operating
Possible
V5
VDD reference (VDD = OV)
voltage
operation
(2)
Possible
Vl, V2 VDD reference (VDD = OV)
operation
Possible
V3, V4 VDD reference (VDD = OV)
operation
High-level input voltage
VIHC
VDD =2.7V
Low-level input voltage
VILC
en
VDD =2.7V
0
:2 High-level output voltage
VOHC
10H= lmA
0
VDD =2.7V 10H =-0.5mA
Low-level output voltage
VOLC
10L = lmA
VDD =2.7V 10L= 0.5mA
High-level input voltage
VIHS
'5
VDD =2.7V
'E
.<::
<..> Low-level input voltage
VILS
en
VDD =2.7V
Input leak current
III
VIN = VDD or Vss
Output leak current
ILO
LC driver ON resistance
RON
Ta=25°C IV5=-14.0V
VDD ref.
I V5 =-B.OV
Static consumption current
Isso
VIN = VDD or Vss
150
V5 = -lB.OV VDDref.
Input terminal capacitance
CIN
Ta = 25°C f= lMHz
Oscillator frequency
fosc
Ta = 25°C IVDD = 5.0V
G5
~
Input voltage
VDD
Booster output voltage
VOUT
:!:::
.g
Voltage regulator circuit operating voltage
<:Q.
Voltage follower
~Q.
$:::>
Een operating voltage
0..0
VOUT
lVDD =2.7V
When 3x step-up
When 4x step-up
When 3x
VDD Ref.
set-up
VDD Ref.
Min
4.5
Typ
5.0
Max
5.5
2.4
-
6.0
-16.0
-
-4.0
V
V5
0.4 x V5
-
VDD
V
Vl, V2
V5
-
0.6xV5
V
V3, V4
0.7 X VDD
0.8 X VDD
Vss
Vss
0.8 X VDD
0.8 x VDD
Vss
Vss
0.85 x VDD
0.8XVDD
Vss
Vss
-1.0
-3.0
-
VDD
VDD
0.3 X VDD
0.2 X VDD
VDD
VDD
0.2 X VDD
0.2 XVDD
VDD
VDD
0.15 X VDD
0.2 X VDD
1.0
3.0
3.0
4.5
5.0
15.0
B.O
25
25
6.0
4.5
V
*3
V
*3
V
*5
V
*5
V
*4
V
*4
I1A
*6
*7
19
19
2.4
2.4
-lB.O
V5(2)
Reference voltage
VREG
When applied
VDD Ref.
to the SED1530
When applied
VDD Ref.
to the SED1531
VDD Ref.
Ta = 25°C
377
-
-
-
2.0
3.0
0.01
0.01
5.0
22
22
-
Pin
Vss
*1
k.Q
SEGn
k.Q
COMn
l1A
Vss
V5
I1A
pF
kHz
*3, *4
V
-
V
VOUT
-lB.O
-
-6.0
V
VOUT
-16.0
-
-6.0
V
-16.0
-
-4.6
V
-2.35
V
-2.65
-2.5
*2
l1A
-
lti~
V5(1)
-
Unit
V
I
SED1530 Series
•
Dynamic consumption current value (1) in display, internal power supply ON
Unless otherwise specified, Ta = -40 to 85°C
Parameter
Symbol
Condition
100 (1)
Voo = S.OV, VS - Voo = -B.OV, 2x Step-up
SE01S30
Min
Voo = 3.0V, VS - Voo =-8.0V, 3x Step-up
SE01S31
Voo =S.OV, VS-Voo =-11.0V, 3x Step-up
Voo = 3.0V, VS - Voo = -11.0V, 4x Step-up
SE01S32
•
Typ
Max
Unit
-
41
70
-
llA
llA
llA
llA
llA
llA
48
80
-
96
160
-
118
190
Voo =S.OV, VS-Voo =-11.0V, 3x Step-up
-
96
160
Voo = 3.0V, VS - Voo = -11.0V, 4x Step-up
-
114
190
Remarks
Current consumption in power save mode
(Vss
Characteristic Symbol
Standby
=OV, VDD = 2.7 to 5.5V, Ta = 25°C)
Condition
Min
Typ
Max
Unit
IOOSl
SE01S30, SE01S31, SE01S32
0.Q1
1.0
looS2
SE01S30, SE01S31, SE01S32
-
1.0
2.0
llA
llA
Typical current consumption characteristics:
Dynamic current consumption (1)
LCD display status using an external power supply
•
Notes
*1. Although a broad operating voltage range is guaranteed,
this does not guarantee against sudden voltage changes
during MPU access.
*3. The AO, 00 to OS, 06, 07 (SI).J:'!Q. (E), WR (RIW), CS1,
CS2, FR, MIS, C86, PIS and OOF pins.
*4. The Cl, SCl (06) and RES pins.
*2. The range of operating voltages olthe Voo system and VS
system. See the figure below. The range of operating
voltages applies when the external power supply is used.
*S. The 00 to OS, 06, 07 (SI), FR, FRS, OVO, OOF and Cl
pins.
-
The Range of Operating Voltages
of the Vss and VS Systems
-20
:::1~ ____
-1S
(V)
-----------
-13
Operating
Range
-10
VS-Voo
-5
,
24:
0
*7. Applicable when the 00 to 07, FR, Cl, OVO and OOF
pins are in a high impedance state.
I
----
:3.0
2
I
4
Voo
6
--
*6. The AO, RO, (E), WR (RIW), CS1, CS2, MIS, RES, C86
and PIS pins.
8
M
378
SED1530 Series
•
o
Timing Characteristics
System Bus: ReadlWrite Characteristics I (SO-Series MPU)
AD
CSt
(CS2="t")
WR,RO
00 - 07
(WRITE)
00- 07
(REAO)
VOO = 5.0V ± 10%, Ta = -40 to 85°C
Parameter
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
Signal
AO
WR
RD
WR
RD
00- 07
Symbol
tAHS
tAWS
tCYCS
tCCLW
tCCLR
tCCHW
tCCHR
toss
tOHS
tACCS
tCHS
Conditions
Min
10
10
200
22
77
172
117
CL
= 100pF
Parameter
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
Signal
AO
WR
RD
WR
RD
DO- 07
Symbol
tAHS
tAws
tCYCS
tCCLW
tCCLR
tCCHW
tCCHR
toss
tOHS
tACCS
tCHS
Conditions
CL
= 100pF
-
-
-
20
10
-
-
70
50
10
VOO
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
=2.7 to 4.5V, Ta =-40 to 85°C
Min
25
25
450
44
194
394
244
Max
-
-
40
20
-
-
140
100
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1. The input signal rise time and fall time (tr, If) are specified at 15ns or less. When the cycle time is used at high speed,
the specification is tr + If :s; (tCYCB -tCCLW - tCCHW) or tr + If :s; (tCYCB - tCCLR - tCCHR).
*2. All timings are specified based on 20% and 80% of VDD.
*3. tCCLW and tCCLR are specified by the overlap period of CS1 = "0" (CS2 = "1 ") and WR, RD = "0" level.
379
I
SED1530 Series
o
System Bus: ReadlWrite Characteristics I (S8-Series MPU)
:~ ~~~-W-6--------------------~
r---------------CS1
(CS2="1")
E
DO - D7
(WRITE)
DO- D7
(READ)
VDD
Parameter
Signal
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Enable L
pulse width
Read
Min
E
E
Signal
= 100pF
Enable L
pulse width
Read
Write
50
70
ns
ns
tEWHR
77
-
ns
22
ns
tEWLR
117
tEWLW
172
-
Symbol
Conditions
Min
Unit
-
50
70
ns
ns
DO - 07
tDS6
tDH6
40
20
E
Max
ns
25
25
CL = 100pF
ns
-
tAW6
tAH6
tOH6
tACC6
ns
= 2.7 to 4.5V, Ta =-40 to 85°C
AO
Rm
E
ns
ns
tEwHW
450
Write
Read
10
-
tCYC6
Output disable time
Access time
Enable H
pulse width
ns
ns
tDS6
tDH6
System cycle time
Data setup time
Data hold time
-
DO - 07
VDD
Address setup time
Address hold time
-
10
10
Write
Parameter
20
10
tAW6
tAH6
CL
Unit
ns
AO
Rm
tOH6
tACC6
Max
-
200
Write
Read
Conditions
Symbol
tCYC6
Output disable time
Access time
Enable H
pulse width
= 5.0V ± 10%, Ta =-40 to 85°C
20
ns
ns
ns
ns
tEWHR
194
-
ns
tEWHW
44
-
ns
tEWLR
244
ns
tEWLW
394
-
ns
*1. The input signal rise time and fall time (tr, tI) are specified at 15ns or less. When the cycle time is used at high speed,
the specification is tr + tf ,,; (tCYC8 -tEWLW - IEWHW) or tr + tf ,,; (tCYC6 - tEWLR - tEWHR).
*2. All timings are specified based on 20% and 80% of VDD.
*3. tEWHR and tEWHW are specified by the overlap period of CS1 = "0" (CS2 = "1") and E = "1" level.
380
SED1530 Series
o
Serial Interface
I.....- - - t c s s -
tCSH-----
CS1
(CS2="1")
AO
SCl
SI
VDD = S.OV
Parameter
Conditions
± 10%, T a = -40 to 8SoC
Signal
Symbol
Min
Serial clock period
SCl "H" pulse width
SCl "l" pulse width
SCl
tSCYC
tSHW
tSLW
SOO
1S0
1S0
Address setup time
Address hold time
AO
tSAS
tSAH
120
200
Data setup time
Data hold time
SI
tSDS
tSDH
CS-SCl time
CS
tcss
tCSH
Max
Unit
120
SO
-
ns
ns
ns
30
400
-
-
ns
ns
ns
ns
ns
ns
VDD = 2.7 to 4.SV, Ta = -40 to 8SoC
Signal
Symbol
Serial clock period
SCl "H" pulse width
SCl "l" pulse width
Parameter
SCl
tSCYC
tSHW
tSLW
Conditions
1000
300
300
Address setup time
Address hold time
AO
tSAS
tSAH
2S0
400
Data setup time
Data hold time
SI
tSDS
tSDH
2S0
100
-
CS-SCl time
CS
tcss
tCSH
60
400
-
*1. The input signal rise time and fall time (tr, tI) are specified at 15ns or less.
*2.
All timings are specified based on 20% and 80% of VDD.
381
Min
Max
Unit
-
ns
ns
ns
-
ns
ns
-
ns
ns
ns
ns
I
SED1530 Series
o
Display Control Timing
CL
(OUT)
~
-
\
-. tORE +-
2(
FR
..tOOH
.. tOOL
DYO
VOO = 5.0V
Parameter
FR delay time
OYO "H" delay time
oya "L" delay time
Signal
Symbol
Conditions
Min
Typ
Max
Unit
FR
tDFR
CL = 50pF
80
150
ns
Oya
tDOH
-
70
160
ns
70
160
ns
tDOL
VDD = 2.7 to 4.5V
Parameter
FR delay time
oya "H" delay time
oya "L" delay time
*1.
± 10%, Ta = -40 to 85°C
Signal
Symbol
Conditions
Min
Typ
Max
Unit
FR
tDFR
CL= 50pF
120
240
ns
Oya
tDOH
-
140
250
ns
140
250
ns
tDOL
Effective only when operating in master mode.
*2. All timings are specified based on 20% or 80% of
o
± 10%, T a = -40 to 85°C
VOD.
Reset Timing
RES
Internal
State
Reset in Progress
~
K
_ _ _ _ _ _ _ _ _ _ _ _ _ _- J I
Reset Complete
VDD = 5.0V
Parameter
Signal
Reset time
Reset "L" pulse width
Symbol
Conditions
Min
tR
1.0
RES
tRW
1.0
Signal
Symbol
± 10%, T a = -40 to 85°C
Typ
-
Max
Unit
-
ms
-
ms
VDD = 2.7 to 4.5V, Ta = -40 to 85°C
Parameter
Reset time
Reset "L" pulse width
RES
Conditions
Min
Typ
Max
Unit
tR
3.0
-
-
ms
tRW
3.0
-
-
ms
*1. All timings are specified based on 10% and 90% of
VDD.
382
SED1530 Series
•
Table of Commands for the SED1530 Series
Command
(1)
Display ON/OFF
Code
AO RD WR D7 D6 D5 D4 D3 D2 D1
0
1
0
1
0
1
0
1
1
1
Function
DO
0
1
Turns the LCD display on and off.
0: OFF
1:0N
Determines the RAM display line
displayed to COMO.
(2)
Display start line set
0
1
0
0
1
(3)
Page address set
0
1
0
1
0
1
1
Page address
Sets the display RAM page to the
page address register.
(4)
Column address set, first 4 bits
0
1
0
0
0
0
1
Most significant
column address
bits
Sets the 4 most significant bits of
the display RAM column address
to the register.
(4)
Column address set, last 4 bits
0
1
0
0
0
0
0
Least significant
column address
bits
Sets the 4 least significant bits of
the display RAM column address
to the register.
(5)
Status read
0
0
1
(6)
Write display data
1
1
0
Write data
(7)
Reads display data
1
0
1
Read data
(8)
ADC select
0
1
0
Display start address
Status
1
0
1
0
0
0
0
0
0
Read status data.
Writes to the display RAM.
Reads from the display RAM.
0
0
0
1
Sets the relationship between the
display RAM address and the SEG
output
0: Normal
(9)
Display: Normal/Reverse
0
1
0
1
0
1
0
0
1
1: Reverse
Sets the LCD display to normal/
reverse.
1
0
1
0: Normal display
0: Normal
1: Reverse
Display: All Pixels Lit
(10) Display: All Pixel Lit: ON/OFF
0
1
0
1
0
1
0
0
1
0
0
1
(11) LCD bias set
0
1
0
1
0
1
0
0
0
1
0
Sets the LCD drive voltage ratio.
(12) Read/modify/write
0
1
0
1
1
1
0
0
0
0
0
Increments the column address
counter by 1 when write, zero when
read.
(13) End
0
1
0
1
1
1
0
1
1
1
0
Getsoutof read/modify/write mode.
(14) Reset
0
1
0
1
1
1
0
0
0
1
0
Internal reset.
*
Selects the direction of the COM
output scan.
* = disabled
(15) Output mode register set
0
1
0
1
1
0
(16) Power control set
0
1
0
0
0
1
(17) Electronic volume register set
0
1
0
1
0
0
(18) Standby set
0
1
0
1
0
1
0
0
0
*
1
Operating
mode
0
1
1
0
Selects the power supply circuit
operating mode.
Sets the V5 output voltage to the
electronic volume register.
Electronic
volume level
0
1
Selects the standby mode.
0: OFF
1:0N
A composite command with display: OFF and Display: All Pixels
On.
(19) Power save
Note:
.
1: All pixels lit
Do not use any other command, or a system malfunction may result.
383
I
SED1530 Series
•
MPU INTERFACE (REFERENCE EXAMPLE)
The SED1530 Series chips can be connected to 80-series and 68-series MPUs. Moreover, by utilizing the
serial interface, the connections can be made with fewer signal lines. When multiple SED1530 chips are used,
each can be connected to the MPU and the chips can be selected using the chip select.
•
8o-Series MPU
-1- vDO
T
I
AO
Vee
A1 -A7
lORa
I MPul
DO- D7
AO
-'----
C86
Decoder
I---I----
CS2
~
Vss
ISED15301
Voo
-
RD
RD
-
-
WR
WR
RES
RES
I
•
CS1
DO-D7
-
GND
Voo
~
PIS
-=r
Vss
1
,J,yss
58-Series MPU
-1- VDO
T
I
Vee
AO
AO
Voo
Voo
C86W
I-----VMA I------
A1 - A15
I MPul
Decoder
E
I
CS2
I
E
-
RIW
RES
CS1
SED15301
DO- D7
DO- D7
GND
I---I----
PIS W
RIW
-
~
384
RES
Vss
1
,J,yss
Voo
I
:
SED1530 Series
•
Serial Interface
~1~
I
Vee
V DO
T
AO
A1 - A7
I MPU I
AO
r-I
Decoder
~
Voo
C86
CS1
CS2
1
SI
2
SCL
ISED15301
PIS
-
GND
I
RES
~
=r
RESET
-
• RES
Vss
1
#vss
385
IJVoo
orGN D
rl
Vss
I
SED1530 Series
•
PIN LAYOUT
51
52 00000000000000000000000000000000000000000000000000000 172
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
oo
0
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
o
0
oo
0
0
o
0
o
0
o
0
o
0
86 00000000000000000000000000000000000000000000000000000 138
87
137
6.65 X 4.57 mm
1181lm (Min.)
Chip Size:
Pad Pitch:
(Aluminum Pad Model)
90 X 90 11m
300 11m
SE0153*O'A
Pad Center Size:
Chip Thickness:
(Gold Bump Model)
76 X 76 11m
17 to 28 11m (Typ)
625 11m
SE0153*O'B
Bump Size:
Bump Height:
Chip Thickness:
386
i
SED1530 Series
•
PAD COORDINATES
X
Coord.
0127
2988
1
2
0128
2860
0129
3
2738
4
0130
2614
0131
2490
5
6
COM3
2386
7
FR5
2242
FR
2124
8
9
OYO
2006
10
Cl
1000
11
OOF
1770
12
VSI
1652
13
MIS
1534
14
REG
1416
15
PIS
1298
16
CS1
1180
1062
17
CS2
18
C86
944
826
AO
19
20 WR(W/R)
708
21
RO(E)
590
22
Voo
354
23
DO
236
24
01
236
25
02
118
26
03
0
-118
27
04
05
-236
28
29 06 (SCl) -354
30
07 (31)
-472
-590
31
Vss
VOUT
-708
32
-826
33
CAPS-944
CAP1+
34
CAP1-1062
35
-1180
36
CAP2+
37
CAP2-1298
-1416
38
V5
-1534
39
VR
-1652
40
Voo
V,
-1770
41
V,
42
-1888
-2006
43
V3
-2124
44
V4
V,
-2242
45
No. Pin Name
Y
Coord.
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
2142
Unit: Ilm
No. Pin Name
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
X
Coord.
-2366
-2490
-2614
-2738
-2862
-2986
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-3178
-2986
-2862
-2738
-2614
Y
Coord.
2142
2142
2142
2142
2142
2142
2006
1888
1770
1652
1534
1416
1286
1150
1062
944
826
708
690
472
364
238
118
0
-118
-236
-354
-472
-590
-708
-826
-944
-1062
-1180
-1298
-1418
-1534
-1652
-1770
-1888
-2006
-2142
-2142
-2142
-2142
No. Pin Name
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
387
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
X
Coord.
-2490
-2386
-2242
-2124
-2006
-1888
-1770
-1652
-1534
-1416
-1298
-1180
-1062
-944
-826
-708
-590
-472
-354
-236
-118
0
118
236
354
472
590
708
826
944
1062
1180
1298
1416
1534
1652
1770
1888
2006
2124
2242
2366
2490
2614
2738
Y
Coord.
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
-2142
No. Pin Name
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
090
091
092
093
094
095
096
097
098
099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
X
Coord.
2862
2986
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
3178
Y
Coord.
-2142
-2142
-2006
-1888
-1770
-1652
-1534
-1416
-1298
-1180
-1062
-944
-826
-708
-590
-472
-354
-236
-118
0
118
236
354
472
590
708
826
944
1062
1180
1298
1416
1534
1652
1770
1888
2006
I
THIS PAGE INTENTIONALLY BLANK
388
SED1540
CMOS DOT MATRIX LCD CONTROLLER/DRIVER
•
DESCRIPTION
The SED1540 is an LCD driver-controller intended mainly for segment type liquid crystal displays. The
device communicates with a host microprocessor through an 8-bit parallel data. The SED1540 stores
the data that is sent from the microcomputer in the built-in data display RAM, and generates a liquid
drive signal.
The device is manufactured with a low power consumption CMOS process. These features give the designer
a flexible means of implementing a small to medium size LCD display for a compact, low power system.
•
FEATURES
• Low-power CMOS technology
• Master/slave operation is supported
• Fast CPU 8-bit data interface (80xx, 68xx)
• Recommended expansion driver ........ SED1521
(80-segment driver)
• 1/4 duty cycle
• Built-in LCD driver circuit .............. 73 segments
4 commons
• Low power consumption ................... 30I-lW max
• LCD voltage ....................................... 3.5 to 11V
• Built-in display data RAM ................... 2560 bits
• Single power supply ......................... 2.4 to 7.0V
• Rich display command setting
• Package ............................. QFP5-100 pin (FaA)
AI pad (DOA)
Au bump (Dos)
• On-chip CR oscillation circuit
Clock Source
•
fCl
Frame Frequency
External clock
4 kHz
85/64 Hz
Internalosc.
18 kHz
375/281 Hz
SYSTEM BLOCK DIAGRAM
COMO-COM3
73 SEG x4 COM
SEGO-SEG72
-
RES
CPU
cs
SED1540
DO - 07
80xx
68xx
389
/L
I
SED1540
•
BLOCK DIAGRAM
"'" "'"
a:
0
IL
0
DISPLAY
r----
TIMING
GENERATOR
Oa:
Z
~
«
W
0
" 0
:0;"
OW
r-
DJ-Q7
Ao
,es
'---
'"
'"'"a:
W
E,R/W
"ita:
(RD)(WR)
~
W
W
f-
0
0
::>
«
z
"-
:0;
RES
BUS
HOLDER
~
LINE COUNTER
~
L
0
"
'" '"
0
DISPLAY DATA RAM
0
2560 BITS
0
«
«
z
z
'---
W
SG o -SG72
0
>-
"-
'"
1S
"
'---
V
'---
110 BUFFER
LOW ADDRESS
REGISTER
t
0
:J
::s
~
"
------,I
a:
W
>
ir
0
:0;
::>
"a:(}
~ ---'\
h ::s
t-v' «>'
MIS
t:
::>
r
'"'"a:
~
W
CMo -CM 3
'---
(}
0
0
~
"
W
'"a:
88
r---f:;
a:
0
"'"
V1 ,V 2 ,V 3
-L
OW
W
::>
0
,-L
za:
:o;f:o;z
.""-
a:
~
I
H
a:
W
fz
'---
"
J
LINE ADDRESS DECODER
"6
:0;
I-
L H'-W
-
r---a:
W
fi'i
W
a:
,,0
r----
•
DISPLAY START LINE REGISTER
INTERNAL BUS
390
!
-
~
-
~
SED1540
•
PIN DESCRIPTION
For chip pad locations see Mechanical Specifications.
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Name
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
Number
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
Number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pin
Duty
98
99
1/4
COM2
COM3
1/3
NC
COM2
391
Name
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEGO
AO
OSC1
OSC2
Number
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
E(RD)
R/W(WR)
Vss
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Voo
RES
FR
V3
CS
NC
MIS
V2
V1
COMO
COM1
COM2
COM3
SEG72
I
SED1540
•
PAD LAYOUT
r--------------------------------------,,-~
01
o
o
o
00000000000000000000
100
95
90
~
800
0
0
0
05
0
o
o
o
o
~O
0
0
0
0
700
0
010
o
o
o
o
015
o
o
o
o
om
o
o
o
o
O~
o
o
o
y
0
0
0
650
7.04 mm
0
0
0
0
Wo
0
0
0
0
550
0
0
SED1540
0
0
~
I...
30
35
40
45
50 0
00000000000000000000
4.80 mm
•
I
-~
X
•
AI pad
Chip Specification
•
Dimensions
Die size
4.80 x 7.04 x 0.525 mm
Pad size
100 x 100 J,lm
Au bump pad
Chip Specification
Minimum bump pitch
Bump height
Bump size
392
Dimensions
199 J,lm
20 J,lm +10/-5 J,lm
132x 111 J,lm±20J,lm
SED1540
•
PAD COORDINATES
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pad
Name
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
X
Y
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
5041
704
903
1103
6507
6308
6108
5909
5709
5510
5310
5111
4911
4712
4512
4169
3969
3770
3570
3371
3075
2876
2676
2477
2277
2078
1878
1679
1479
1280
1080
881
681
482
159
159
159
159
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Pad
Name
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
393
X
Y
1302
1502
1701
1901
2100
2300
2499
2699
2898
3098
3297
3497
2696
3896
4095
4295
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
482
681
881
1080
1280
1479
1679
1878
2078
2277
2477
2676
2876
3075
3275
3474
3674
3948
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pad
Name
SEG3
SEG2
SEG1
SEGO
AO
OSC1
OSC2
E (RD)
RIW (WR)
Vss
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
RES
FR
V3
CS
NC
MIS
V2
V1
COMO
COM1
COM2
COM3
SEG72
X
Y
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4295
4095
3896
3696
3497
3297
3098
2898
2699
2499
2300
2100
1901
1701
1502
1302
1103
903
704
504
4148
4347
4547
4789
5048
5247
5447
5646
5846
6107
6307
6506
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
I
THIS PAGE INTENTIONALLY BLANK
394
SED1560 Series
•
DESCRIPTION
The SED1560 Series are intelligent CMOS LCD driver-controllers with the ability to drive alphanumeric and
graphic displays. The SED1560 Series communicates with a high-speed microprocessor, such as the Intel
80XX family or the Motorola 68XX family, through either a serial or an 8-bit parallel interface. It stores the data
sent from the microprocessor in the built-in display data RAM (166 x 65 bits) and generates an LCD drive
signal. These devices incorporate an internal DC/DC converter to generate the negative voltage needed for
LCD contrast. The controllers feature software contrast adjustment by command setting.
The three different versions of the SED1560 Series support the following duty ratios and display sizes:
•
Model
Duty Ratio
SED1560
1/65, 1/64, 1/49, 1/48
SEG x COM
102 x 65
SED1561
1/33, 1/32, 1/25, 1/24
134 x 33
SED1562
1/17, 1/16
150 x 17
FEATURES
• Low-power operation: 8 ~ @ 1 kHz, 6V LCD
• -.17% / °C temperature gradient
• 350 ~ current consumption during CPU access
@ 200 kHz
• On-chip oscillator with external resistor
• 32 levels of contrast adjustment by software
• Direct interface to both 80XX and 68XX, 5 MHz,
zero wait-state
• Supports master/slave operation
• Selectable output configuration
• On-chip display data RAM (166 x 65 bits)
• 2.4V to 6.0V supply voltage
• On-chip DC/DC converter for LCD voltage
• 3.5V to 16V LCD voltage
• On-chip voltage regulator and low-power voltage
follower
•
• Package: TAB ....... (TOB (TQA -
SYSTEM BLOCK DIAGRAMS
/1
20 CHAR x 8 LINES
-
RES
CPU
CS
SED1560
00- 07
80xx
68xx
395
"
2-sided)
4-sided)
I
SED1560
•
SYSTEM BLOCK DIAGRAMS (continued)
COMO-COM32
26 CHAR X 4 LINES
i'
SEGO-SEG133
-
RES
CPU
CS
SED1561
00- 07
80xx
68xx
30 CHAR x 2 LINES
0
RES
-
CPU
CS
SED1562
00- 07
80xx
68xx
396
"
SED1560
•
BLOCK DIAGRAM
000 to 031 032
Vss
Voo
to
0101 0102 to 0165 COM1
r
Voo
V1
V1
Common
and
segment
drivers
V2
V3
V4
Common
and
Commons
segment
only
drivers
Segment
driver
V2
V3
V4
V5
~
-
CAP1+
)-
CAP1-
)--
CAP2+
:r:r-
CAP2-
VR
T1. T2
control
Shift
register
LCD
supply
voltage
gene rator
Shift
register
~
I
166-bit display data latch
WlJ
status
select
-
V5
1/0
buffer
~~
166 x 65-bit display
data RAM
decoder
counter
Display
initial line
register
~
~
166-bit column address decoder
10"
FR
8-bit column address counter
Page
address f - register
SYNC
1'0"
Display
timing
generator
8-bit column address register
CL
CLO
DYO
MIS
Bus holder
Command
decoder
I
I
Status flag
I
Oscillator
OSC1
I
OSC2
V/l
l
MPU interface
11
11
1
I
1
CS1 CS2 AO RD WR CS6 SI SCL PIS RES
397
1/0 buffer
1
1
I
11
D7 D6 D5 D4 D3 D2 D1 DO
SED1560
•
•
PIN DESCRIPTION
Power Supply
Number of Pins
I/O
Name
2
Supply
VDD
Common to MPU power supply pin Vee
Ground
2
Supply
Vss
11
Supply
LCD
voltage
V1 to V5
Description
LCD driver supply voltages. The voltage determined by the LCD cell
is impedance-converted by a resistive divider or an operational
amplifier for application. Voltage levels are based on VDD. The
voltages must satisfy the following relationship:
VDD :2: V1 :2: V2 :2: V3 :2: V4 :2: V5
Master mode select: bias voltages are generated on-chip.
•
SED1560
SED1561
V1
1/9 V5
1/7 V5
1/5 V5
V2
2/9 V5
2/7 V5
2/5 V5
V3
7/9 V5
5/7 V5
3/5 V5
V4
8/9 V5
6/7 V5
4/5 V5
SED1562
LCD Driver Power Supplies
Number of Pins
I/O
Name
1
CAP1+
DC/DC VOltage converter capacitor 1 positive connection
CAP1-
DC/DC voltage converter capacitor 1 negative connection
CAP2+
DC/DC voltage converter capacitor 2 positive connection
CAP2-
DC/DC voltage converter capacitor 2 negative connection
1
0
0
0
0
0
1
I
VR
2
I
T1, T2
1
1
1
VOUT
Description
DC/DC voltage converter output
Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
Liquid crystal power control terminals
T2
Boosting
Circuit
Voltage
Regulation
Circuit
L
L
Valid
Valid
Valid
L
H
Valid
Valid
Valid'
H
H
L
Invalid
Valid
Valid
H
Invalid
Invalid
Valid
T1
Note:
• V/F circuit current capacity enhancement
398
V/F Circuit
SED1560
•
Microprocessor Interface
Number of Pins
I/O
Name
8
I/O
DO to 07
1
I
AO
Description
Data is transferred between the controller and MPU via these pins
Control/display data flag input. This is connected to the LSB of the
microprocessor address bus.
• When LOW, the data on DO to 07 is command data
• When HIGH, the data on DO to 07 is display data
1
I
RES
Reset input. Setting this pin low initializes the SED156X.
2
I
CS1,
CS2
Chip select inputs. Data input/output is enabled when CS1 is LOW
and CS2 is HIGH.
1
I
RD
Read enable input. See note 1.
1
I
WR
Write enable input. See note 2.
1
I
C86
Microprocessor interface select input.
• LOW when interfacing to 8080-series
• HIGH when interfacing to 6800-series
Serial data input
1
I
SI
1
I
SCL
Serial clock input. Data is read on the rising edge of SCL and converted
to 8-bit parallel data.
1
I
PIS
Parallel/serial data input select
PIS
Operating
Mode
Chip
Select
Datal
command
HIGH
Parallel
CS1, CS2
AO
LOW
Serial
CS1, CS2
AO
Data
I/O
DO to
07
SI
Read/
write
RD,WR
Write only
Serial
Clock
SCL
In serial mode, data cannot be read from the RAM, and DO to 07, HZ,
RDandWR must be HIGH or LOW. In parallel mode, SI and SCLmust
be HIGH or LOW.
Notes:
1. When interfacing to 8080-series microprocessors, RD is active-LOW. When interfacing to 6800-series microprocessors, they are active-HIGH.
2. When interfacing to 8080-series microprocessors, WR is active-LOW. When interfacing to 6800-series microprocessors, read mode is selected when WR is HIGH, and write mode is selected when WR is LOW.
399
I
SED1560
•
Oscillator and Display Timing Control
Number of Pins
I/O
Name
Description
2
I
OSCi
Using internal oscillator when MIS = "H", connect resistor Rf to the
OSC 1 and OSC2 pins. The OSC2 pin is used for output of the oscillator
amplifier.
2
I/O
OSC2
When MIS = "L": the OSC2 pin is used for input of oscillation signal. The
OSCi pin should be left open. Fix the CL pin to the VSS level when
using the internal oscillator circuit as the display clock.
1
I
CL
Display clock input. The line counter increments on the rising edge of
CL, and the display pattern is output on the falling edge. When using
the external display clock, OSCi = "H", OSC2 = "L", and reset this LSI
by RES pin.
1
0
CLO
Display clock output. When using the internal oscillator, the clock
signal is output on this pin. Connect CLO to YSCL on the common
driver.
1
I
MIS
Masterlslave select input. Master produces signals for display, and
slave receives them. This is for display synchronization.
Operating Internal Power
FR SYNC OSC1 OSC2 DYO
Mode Oscillator Supply
Open
LOW
Slave
OFF
OFF
I
I
I
0
156X
HIGH Master
ON
ON
I
0
0
0
0
Device
M/S
Note: I = input rnode
o
= output rnode
1
1/0
FR
LCD AC drive signal input/output. Output is selected when MIS is
HIGH, and input is selected when MIS is LOW.
1
I/O
SYNC
Display sync input/output. Output is selected when MIS is HIGH, and
input is selected when MIS is LOW.
1
0
DYO
Start-up output for common driver. Connect to DIO of the common
driver, such as the SED1630.
*
SED1630 has a DIO input.
400
SED1560
•
LCD Driver Outputs
Number of Pins
I/O
Name
Description
166
0
00 to
0165
LCD driver outputs. 00 to 031 and 0102 to 0165 are selectable
segment or common outputs, determined by a selection command.
032 to 0101 are segment outputs only.
For segment outputs, the ON voltage level is given as shown in the
following table:
RAM Data
LOW
HIGH
FR
LCD ON Voltage
Normal Display
Inverse Display
LOW
V3
V5
HIGH
V2
Voo
LOW
V5
V3
HIGH
Voo
V2
For common outputs, the ON voltage is given as shown in the following table:
Scan Data
LOW
HIGH
1
0
COM1
FR
LCD ON Voltage
LOW
V4
HIGH
V1
LOW
Voo
HIGH
V5
LCD driver common output. Common outputs when the "DUTY + 1"
command is executed are as follows:
Device
"DUTY + 1" ON
"DUTY + 1" OFF
SED1560
COM64, COM48
V1 or V4
SED1561
COM32, COM24
V1 or V4
SED1562
COM16
V1 or V4
Common output special for the indicator.
401
I
SED1560
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
-7.0 to 0.03
Vss
-6.0 to 0.3
(when triple voltage conversion)
V
Driver supply voltage range (1)
V5
-18.0 to 0.3
V
Driver supply voltage range (2)
Vi, V2, V3, V4
V5 to 0.3
V
VIN
V
Supply voltage range
Input voltage range
Output voltage range
VO
Vss - 0.3 to 0.3
Vss - 0.3 to 0.3
Operating temperature range
Topr
-30 to 85
°C
Storage temperature range (TCP)
Tstr
-55 to 125
°C
V
Notes:
1.
The voltages shown are based on VDD = OV.
2.
Always keep the condition VDD
3.
If devices are used over the absolute maximum rating, the LSls may be destroyed permanently. It is desirable to use
them under the electrical characteristic conditions for general operation. Otherwise, a malfunction of the LSI may be
caused and LSI reliability may be affected.
4.
For operating temperatures below -30°C, please consult an S-MOS engineer.
~ V1 ~ V2 ~ V3 ~ V4 ~ V5
402
for voltages V1, V2, V3 and V4.
SED1560
•
DC CHARACTERISTICS
VDD = OV, VSS = -5 ± 10%, Ta = -30 tD +85°C unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
Unit
Pin
Power
Recommended
voltage (1) operation
Vss
-5.5
-5.0
-4.5
V
Vss
-6.0
V5
-16.0
voltage (2) Operational
Vi, V2
0.4 x V5
Operational
V3, V4
V5
VIHCl
0.3 x Vss
VIHC2
0.15xVss
-
Condition
Operational
Operating
Operational
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
-2.4
Vss *1
-3.5
V
V5 *2
VDD
V
Vi, V2
0.6 x V5
V
V3, V4
VDD
V
*3
VDD
V
*4
VIHCl
Vss =-2.7V
0.2 x Vss
-
VDD
V
*3
VIHC2
Vss =-2.7V
0.15 x Vss
-
VDD
V
*4
0.7 x Vss
V
*3
0.85 x Vss
V
*4
0.8 x Vss
V
*3
0.85 x Vss
V
*4
VDD
V
*5
VDD
V
OSC2
VDD
V
*5
VDD
V
OSC2
VILCl
Vss
VILC2
Vss
VILCl
Vss =-2.7V
Vss
VILC2
Vss =-2.7V
Vss
VOHCl
10H =-1 mA
0.2 x Vss
VOHC2
10H = -120 J.lA
0.2 x Vss
VOHCl
Vss =-2.7V
10H =-0.5 mA
0.2 x Vss
VOHC2
Vss =-2.7V
10H =-50 J.lA
0.2 x Vss
VOLCl
10L = 1 mA
Vss
VOLC2
10L = 120 J.lA
Vss
0.8 x Vss
V
*5
0.8 x Vss
V
OSC2
VOLCl
Vss =-2.7V
10L= 0.5 mA
Vss
-
0.8 x Vss
V
*5
VOLC2
Vss =-2.7V
10L = 50 J.lA
Vss
-
0.8 x Vss
V
OSC2
*6
Input leakage current
III
Output leakage current
ILO
VIN = VDD or Vss
LCD driver ON resistance
RON
Static power consumption
Isso
150
V5=-18.0V
Input terminal capacity
CIN
Ta = 25°C
Oscillator frequency
fosc
Rf = 1MQ±2%
-1.0
-3.0
Ta = 25°C
LV5 = -14.0V
I V5 =-8.0V
f = 1 MHz
I Vss = -5V
I Vss=-2.7V
1.0
J.lA
3.0
[.lA
*7
00-0166
-
2.0
3.0
kQ
-
3.0
4.5
kQ
*8
0.00
5.0
J.lA
Vss
0.01
15.0
-
5.0
8.0
J.lA
pF
*3 *4
15
18
22
kHz
*9
11
16
21
V5
Reset time
Reset "L" pulse width
Input voltage
Vss
Amplified output voltage
VOUT
Voltage regulator
Q; circuit operation voltage
3:
0
Q. Voltage follower
C
operation voltage
~
.:;
VOUT
.:;
~
·u
III
Reference voltage
Notes:
V5
V5
CD
®
V5@
VREG
-2.4
-18.0
-
Supplied to SED1560
-16.0
Supplied to SED1561
-16.0
Supplied to SED1562
-16.0
Ta = 25°C
-2.35
-6.0
If amplified 3 times
-18.0
* See Notes below.
403
V
*12
V
VOUT
-6.0
V
VOUT
-
-6.0
V
*13
-
-5.0
V
-
-4.5
V
-2.5
-2.65
V
-
I
SED1560
•
When dynamic current consumption (I) is displayed; the built-in power supply is on and T1 = T2 = Low
Test conditions, unless otherwise specified: VDD = OV, Vss = -5V ±10%, Ta = -30 to 85°C
Parameter
Symbol
Condition
SED1560
V5 = -12.5V; 3 times amplified
V5 = --8.0V; 3 times amplified
SED1561
100
(1)
V5 = -6.0V; 2 times amplified
SED1562
•
o
Vss = -2.7V; 3 times amplified
V5 =-6.0V
Typ
Max
Unit
-
169
124
340
250
!-LA
!-LA
53
110
!-LA
-
66
130
!-LA
Remarks
*16
Typical current consumption characteristics
Dynamic current consumption (I), if an external clock and an external power supply are used
Conditions:
(~A)
IDD (1)
(Iss +IS)
40
30
SEO~
':EO\S61
f...---
L
-1
-2
SED1560
SED1561
SED1562
\f-----
-
10
0
The built-in power supply is off but the
external one is used.
.1
\
20
t:t:~
SED1560
SED1561
SED1562
I
-3
-4
-s
V5
V5
V5
-12.5V
-8.0V
-6.0V
fel
fel
fel
4 kHz
2 kHz
1 kHz
External clock:
-
-6
Vss
-7
(V)
Remarks:
o
Min
*14
Dynamic current consumption (I), if the built-in oscillator and the external power supply are used
Conditions:
(~A)
80
SE~S60
100 (1) 60
(Iss +15)
40
o
SED1560
SED1561
SED1562
/" Vs~S61
""-
20
--
".-
-1
-2
~ ,/'"
,..---
-3
---
-4
Vss
-S
SEOJS62
V5
V5
V5
-12.5V
-8.0V
-6.0V
Internal oscillation:
SED1560
SED1561
SED1562
I
-6
The built-in power supply is off but the
external one is used.
-7
(V)
Remarks:
404
*15
RI
RI
RI
1 MQ
1 MQ
1 MQ
SED1560
o
Dynamic current consumption (I), if the built-in power supply is used.
Conditions:
- n'
200
~~61-
150
(1)
V5 = -12.5V;
3 times amplified
SED1561
V5
-B.OV;
3 times amplified
SED1562
V5 = -6.0V;
2 times amplified
f..--
100
SE~562
50
o
SED1560
SED1560
(~A)
IDD
The built-in power supply is on and
T1 =T2 = Low.
I-t'"
Internal oscillation:
I
-1
-2
-3
-4
Vss
-5
-B
=
-7
(V)
SED1560
SED1561
SED1562
Aemarks:
Al
Al
Al
1 Mil
1 Mil
1 Mil
*16
Notes:
*1. Although the wide range of operating voltage is
guaranteed, a spike voltage change during access to the MPU is not guaranteed.
*11.
Specifies the minimum pulse width of RES signal.
The Low pulse greater than "tRw" must be entered
for reset.
*2. The operating voltage range of the VSS and V5
systems. The operating voltage range is applied if
an external power supply is used.
*12.
If the voltage is amplified three times by the builtin power circuit, the primary power Vss must be
used within the input voltage range.
*3.
Pins AO, DO to D7, RD (E),WR (RiW), CS1, CS2,
FR, SYNC, MIS, C86, SI, PIS, T1 AND T2.
*4.
Pins CL, SCL, and RES.
*13. The V5 voltage can be adjusted within the voltage
follower operating range by the voltage regulator
circuit.
*5.
Pins DO to D7, FR, SYNC, CLO, and DYO
*6.
Pins AO, RD (E), WR (RiW), CS1, CS2, CL, MIS,
RES, C86, SI, SCL, PIS, T1, and T2.
*7.
Applied if pins DO to D7, FR, and SYNC are high
impedance.
*14,15,16.
The current consumption is shown if the checker
is used, the display is turned on, the output status
of Case 6 is selected, and the SED1560 is set to
1/64 duty, theSED1561 issetto 1/32 duty, and the
SED1562 is set to 1/64 duty.
*8. The resistance when the 0.1 -volt voltage is applied between the "On" output terminal and each
power terminal (V1, V2, V3 or V4). It must be
within the operating voltage (2).
*9. The relationship between the oscillation frequency,
frarne and Rf value.
*10.
Indicates the current consumed by the separate
IC. The current consumption due tothe LCD panel
capacity and wiring capacity is not included.
"tr" (reset time) indicates the period between the
time when the RES signal rises and when the
internal circuit has been reset. Therefore, the
SED156* is usually operable after "tr" time.
405
*14.
Applied if an external clock is used and if not
accessed by the MPU.
*15.
Applied if the built-in oscillation circuit is used and
if not accessed by the MPU.
*16.
Applied if the built-in oscillation circuit and the
built-in power circuit are used (T1 = T2 = Low) and
if not accessed by the MPU.
I
SED1560
The relationship between oscillator frequency
fose and LCD frame frequency fF is obtained
from the following expression:
40
30
"'" ~
10
Device
SED1560
~
SED1561
0.5
1.0
1.5
2.0
2.5
SED1562
Rf[M]
Duty
fF
1/64
fose/256
1/48
fose/192
1/32
fose/256
1/24
fose/192
1/16
fose/256
(IF indicates not IF signal cycle but cycle 01 LCD AC.)
Oscillator frequency vs. frame vs. Rf
[SED156Xl
200
/
/
[Hz]
100
IF
/
,'/
,/ ,',,/
,','/'/,
,;~
~
a
/'
'
/'/
/'
/'
<<::---~
/'
- - duty 1/64 SED1560
//'
, /'
/'
/
,/
, /'
/
~
/'
4
-
-
--
duty 1/48
duty 1/32 SED1561
- - - - duty 1/24
-----
~
2
-
6
duty 1/16SED1562
8
fcc [KHz]
External clock (fel)
VS.
frame frequency [SED156Xl
-20
-16
5.0V
-15
-13
[VI
V5
2.7V
[mAl
-10
100 (2)
-5
0.1
f---+---T'-I7"---+---I
0.01 f--fi"'-----+---+---I
-2
-2.4 -3.0
-4
-6
-8
om
Vss [VI
0.1
10
f",[MHz]
Operating voltage range for Vss and V5
Power consumption during CPU access cycle
(IDD [2])
406
SED1560
•
RESET
Parameter
Reset time
Reset LOW-level
pulsewidth
•
Symbol
Condition
Min
tR
tR is measured from the rising edge
of RES. The SED156X resumes
normal operating mode after a reset.
1.0
-
-
Ils
1.0
-
-
Ils
tRW
Typ
Max
Unit
DISPLAY CONTROL TIMING
CL
FR
r----
-~.--
tWlCl
tWHCl
-~-tr
-:[+.tl
- ,•. --~ tDFR
I
1,.--
tDSNC
i--
tOOL
-{---
tCOl
i
I
SYNC
I-
tOOH
I
DYO
- - { - tCOH
CLO
•
/
I
Display Control Input Timing
Parameter
Vss
Symbol
Condition
twlCl
35
CL HIGH-level pulsewidth
tWHCL
35
CL rise time
tr
CL fall time
tl
FR delay time
SYNC delay time
30
tDSNC
-1.0
Symbol
Condition
CL HIGH-level pulsewidth
twHCL
35
CL rise time
tr
CL fall time
tf
-
tOFR
-1.0
tOSNC
-1.0
1. Effective only when the SED156X is in the master mode.
2. The FRISYNC delay time input timing is provided in the slave operation.
The FRISYNC delay time output timing is provided in the master operation.
3. Each timing is based on 20% and 80% of Vss.
407
-
Max
Unit
-
Ils
Ils
ns
1.0
Ils
Ils
1.0
ns
=-4.5 to -2.7V, Ta = -30 to 85°C
Min
35
Notes:
30
-1.0
tWLCL
SYNC delay time
-
tOFR
CL LOW-level pulsewidth
FR delay time
Typ
-
VSS
Parameter
= -5.5 to -4.5V, Ta = -30 to 85°C
Min
CL LOW-level pulsewidth
/
Typ
40
40
-
Max
Unit
-
Ils
Ils
ns
1.0
Ils
Ils
1.0
ns
SED1560
•
Display Control Output Timing
Parameter
FR delay time
SYNC delay time
Vss = -5.5 to -4.5V, Ta = -30 to 85°C
Symbol
Condition
Typ
Max
Unit
tOFR
CL= 50 pF
-
60
150
ns
tOSNC
CL=100pF
-
60
150
ns
-
70
160
ns
70
160
ns
40
100
ns
-
40
100
ns
DYO LOW-level delay time
tOOL
DYO HIGH-level delay time
tOOH
CLO to DYO LOW-level
delay time
tCOL
SED156X operating in
master mode only
CLO to DYO HIGH-level
delay time
tCOH
SED156X operating in
master mode only
Min
Vss = -4.5 to -2.7V, Ta = -30 to 85°C
Parameter
Symbol
Condition
Min
Typ
Max
Unit
tOFR
CL = 50 pF
-
120
240
ns
SYNC delay time
tOSNC
CL = 100 pF
120
240
ns
DYO LOW-level delay time
tOOL
140
250
ns
DYO HIGH-level delay time
tOOH
-
140
250
ns
-
100
200
ns
-
100
200
ns
FR delay time
•
CLO to DYO LOW-level
delay time
tCOL
SED156X operating in
master mode only
CLO to DYO HIGH-level
delay time
tCOH
SED156X operating in
master mode only
System Buses: Read/Write Characteristics I (SO-Series MPU)
AO
tCCHR
tCCHW
WR, RD, (CS)
DO to 07
(Write)
00 to 07
(Read)
408
SED1560
Vss = -5.0
Parameter
Address hold time
Address setup time
Signal
Symbol
AO, CS
tAH8
tAW8
10
10
tCVC8
200
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
22
172
117
tOS8
tOH8
20
10
System cycle time
Control
Control
Control
Control
L pulse width (WR)
L pulse width (RD)
H pulse width (WR)
H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
00- 07
Input signal change time
Condition
± 10%, Ta = -30 to 85°C
tr, tl
Max
Unit
-
ns
ns
-
ns
ns
10
70
50
ns
ns
-
15
ns
77
CL = 100pF
tACC8
tCH8
Min
-
ns
ns
ns
ns
ns
Vss = -2.7 to -4.5V, Ta = -30 to 85°C
Parameter
Address hold time
Address setup time
Signal
Symbol
AO, CS
tAH8
tAW8
25
25
tCVC8
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
tOS8
tOH8
40
20
System cycle time
Control
Control
Control
Control
L pulse width (WR)
L pulse width (RD)
H pulse width (WR)
H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
Input signal change time
Notes:
00-07
tACC8
tCH8
Condition
CL = 100pF
Min
Unit
-
ns
ns
450
-
ns
44
194
394
244
-
ns
ns
ns
ns
10
-
tr, tl
Max
-
ns
ns
140
100
ns
ns
15
ns
1. When using the system cycle time in the high-speed mode, it is limited by tr + tf"; (tCYCS - tCCLW - tCCHW) ortr + tf"; (tCYCS
- tCCLR - tCCHR)
2. All signal timings are limited based on 20% and 80% of Vss voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the RD or WR signal is in the low level.
If read/write operation is performed by the RD or WR signal while CS is active, it is determined by the RD or WR signal
timing.
If readlwrite operation is performed by CS while the RD or WR signal is in the low level, it is determined by the CS active
timing.
409
I
SED1560
•
System Buses: ReadlWrlte Characteristics II (58-Series MPU)
.
ICVC6
E
IEWLR
IEWLW
\
1\
/
,!AW6
----=:
IEWHR
IEWHW
I-Ir
y
AO,RW
-..
--K=
!AH6
Ij-O
-1056----
00-07
!AH6
IOH6
~
(WRITE)
--IACC6
DO _ 07
(READ)
--i
:::j-
IOH6
IOH6
J_
---------------~'__ _ _ _
Vss = -5.0V ± 10%, Ta = -30 to 85°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
READ
WRITE
READ
Enable L pulse
width
WRITE
Input signal change time
Enable H pulse
width
Signal
(AO)
RIW
00- 07
E
E
Symbol
tCVC6
tAW6
tAH6
tOS6
tOH6
tOH6
tACC6
tEWHR
tEWHW
tEWLR
tEWLW
tr, tf
Condition
CL = 100pF
Min
200
10
10
20
10
10
Max
-
-
-
50
70
77
22
117
172
-
-
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Vss = -5.0V ± 10%, Ta = -30 to 85°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
READ
WRITE
READ
Enable L pulse
width
WRITE
Input signal change time
Enable H pulse
width
Signal
AO,CS
(CS1,CS2)
RIW
00-07
E
E
Symbol
tCVC6
tAW6
tAH6
tOS6
tOH6
tOH6
tAccs
tEWHR
tEWHW
tEWLR
tEWLW
tr, tf
410
Condition
CL= 100pF
Min
450
25
25
40
20
20
Max
-
-
-
100
140
154
44
244
394
-
-
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SED1560
Notes:
1. When using the system cycle time in the high-speed mode, it is limited by tr + It::; (tCYC6- tEWLW- tEWHW) or tr + tf::; (tCYC6
- tEWLR - tEWHR)
2. All signal timings are limited based on 20% and 80% of Vss voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the E signal is in the high level.
If read/write operation is performed by the E signal while CS is active, it is determined by the E signal timing.
If read/write operation is performed by CS while the E signal is in the high level, it is determined by the CS active timing.
•
Serial Interface
-tcss-
4---tcSH-
~
CS
K
I--- tsAs-~
AD
f
.
K
\
tf-
I
!sCYC
-tSLW-
---;
SCL
-tSAH-
II
i-
tr
-tSDS--~
tSHW
4---tSDH-
~
SI
Vss = -5.0V ± 10%, Ta = -30 to 85°C
Parameter
Signal
Serial clock cycle
Symbol
Condition
Min
tSCYC
500
tSHW
150
SCL low pulse width
tSLW
150
Address setup time
tsAS
120
tSAH
200
tSDS
120
tSDH
50
tcss
30
tCSH
400
tr, tl
-
SCL high pulse width
Address hold time
Data setup time
Data hold time
CS-SCL time
Input signal change time
SCL
AO
SI
CS
411
Max
-
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SED1560
Vss =-5.0V ± 10%, Ta
Parameter
Serial clock cycle
SCL high pulse width
SCL low pulse width
Address setup time
Address hold time
Data setup time
Data hold time
-
CS-SCL time
•
Symbol
tseye
SCL
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tess
tesH
tr, tf
AO
SI
CS
Input signal change time
Note:
Signal
Condition
Min
1000
300
300
250
400
250
100
60
800
-
=-30 to 85°C
Max
-
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*2. All signal timings are limited based on 20% and 80% of Vss voltage .
RESET
When power is turned ON, the SED1560 is initialized on the rising edge of RES. Initial settings are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Display ...................................................... OFF
Display mode ............................................ Normal
n-line inversion ......................................... OFF
Duty cycle ................................................. 1/64
ADC select ............................................... Normal
Read/write modify ..................................... OFF
On-chip power supply ............................... OFF
Serial interface register ............................ Cleared
Display initial line register ......................... Line 1
Column address counter .......................... 0
Page address register .............................. Page 0
Output selection circuit .........................•... Case 6
n-line inversion register ............................ 16
Set the electronic control register to zero (0)
RES should be connected to the microprocessor reset terminal so that both devices are reset at the same
time. RES must be LOW for at least 1 j.ls to correctly reset the SED1560. Normal operation starts 1 i!S after
the rising edge on RES.
If the SED1560 is not properly initialized when power is turned ON, it can lock itself into a state that cannot
be cancelled.
When the Reset command is used, only initial settings 9 to 14 are active.
412
SED1560
•
•
COMMANDS
The Command Set
AO, RD and WR identify the data bus commands. Interpretation and execution of commands are synchronized to the internal clock. Since a busy check is normally not needed, commands can be processed at high
speed. When the serial interface is used, the order of data entry is 07 to DO.
Command
Code
AO
RD
WR
D7
D6
D5
D4
D3
D2
D1
Description
DO
0
Turns the display ON and OFF.
0: OFF
1:0N
Display ON/OFF
0
1
0
1
0
Display START
Line set
0
1
0
0
1
Page address set
0
1
0
1
0
1
1
Page address
Sets the display RAM pages in the
Page Address register.
Column address set
high-order 4 bits
0
1
0
0
0
0
1
High-order
column address
Sets the high-order 4 bits of the display RAM column address in the
register.
Column address set
low-order 4 bits
0
1
0
0
0
0
0
Low-order
column address
Sets the low-order 4 bits of the display
RAM column address in the register.
0
1
1
0
1
0
0
Write data
1
Read data
Status read
Display data write
Display data read
ADCselect
Normal/reverse
display
All indicator ON/OFF
Duty select
Duty + 1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
Determines the RAM display line for
COMO.
Display line address
0
Status
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
Reads the status information.
Writes data in the display RAM.
Reads data from the display RAM.
0
1
1
0
0
0
0
1
Outputs the display RAM address for
SEG.
0: Normal
1: Reversed
Display the LCD image in normal or
reverse mode.
1
0
1
0
0
1
0
0
1
Sets LCD drive duty (1).
1
0
1
Sets LCD drive duty (2).
0: Normal
1: Reversed
Lights all indicators.
0: Normal display
0: 1/24, 48
0: Normal
1: All ON
1: 1/32, 64
1:Duty+1
Sets the line reverse driving and no.
of reverse lines in the line reverse
register.
n-line reverse
register set
0
1
0
0
0
1
1
n-Iine reverse
register release
0
1
0
0
0
1
0
0
0
0
0
Releases the line reverse driving.
Read Modify Write
0
1
0
1
1
1
0
0
0
0
0
Increments by 1 during write of column address counter, and sets to 0
during read.
End
0
0
1
0
0
1
1
1
0
1
1
1
0
Releases the Read Modifywrite mode.
1
1
1
1
0
0
0
1
0
Internal reset.
Output status
register set
0
1
0
1
1
0
0
Built-in power
supply ON/OFF
0
1
0
0
0
1
0
Reset
Power-on
completion
Electronic control
register set
0
0
1
1
0
0
1
1
1
0
1
0
No. of reversed
n-lines
Sets the COM and SEG status in registers.
Output status
0
0
1
1
1
0
0
Electronic control
value
0
0: Power OFF
1
1: Power ON
1
Completes the turn-on sequence
of built-in power supply.
Sets the V5 output voltage in the electronic control register.
A complex command to turn off the
display and light all indicators.
Power save
413
I
SED1560
•
MICROPROCESSOR INTERFACE
The SED1560 Series communicates with a high-speed microprocessor, such as the Intel80XX family or the
Motorola 68XX family, through 8-bit parallel data transfer. The number of connections to the microprocessor
can be minimized by using a serial interface. When used in a multiple-chip configuration, the SED1560 Series
is controlled by the chip select signals from the microprocessor.
T
Vee
AO
AO
Voo
C86
AO to A7
-
Decoder
--
MPU
lORa
-
-
-
GND
~
RD
WR
RES
PIS
LI
C86
~
Vss
1
RESET
I
~
SED156X
DO to D7
DO to D7
RD
WR
RES
CS1
CS2
7fT
8080-series microprocessors
T
Vee
AO
AO to A15
MPU
AO
-
Decoder
VMA
E
RIW
-
GND
I
CS1
CS2
SED156X
DO to D7
DO to D7
RES
Voo
~
E
RIW
RES
PIS
Vss
RESET
7/7'
6800-series microprocessors
414
LI
SED1560
tcss-
tCSH-
)t
C5
:2(
~I<-
~tSAH-
~tSAS-
'}r-
AO
2(
--''''
tSCYC
1\
5CL
tSLW
,
J(
I<-
_f
tf
51
tr
tSDS
tSHW
-tSDH
'\
~
I
Serial interface
•
LCD PANEL INTERFACE EXAMPLES
r------\
r---I
65 x 102
1
~
Commons
rseg me nts
SED1560
(Master)
Case 1
~I
Commons
33 x 134
.i'
~I
I
rsegments
SED1561
(Master)
Commons
Case 4
Single-chip configurations
415
17 x 150
.i'
[Segments
SED1562
I
SED1560
•
PAD LAYOUT
8
046
VS
o V4
o V3
o V2
o V1
o Vee
0000000000000000000000000000000000000000000000
0
0
0
0
0
0
o
o
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SE01S6X
o
o
o
o
o
0
o
0
o
o
o
o
0
0
0
0
o
o
o
0
o
0
o
o
0
0
0
0
FR
SYNC
CLO
OYO
07
06
OS
04
03
02
01
00
Vss
RO
WR
AO
C86
CS2
CS1
0
o
o
0
o
0
o
o
o
PIS
0
SI
SCL
oRES
0
o
MIS
0
0
o Vee
0
o V1
0
o V2
0
o V3
0
o V4
0000000000000000000000000000000000000000000000
VS
0
0120
VOUT
CAP2o CAP2+
o CAP1o CAP1+
o Vss
o T1
o T2
o OSC1
o OSC2
o CL
0
0
VR
VS
8.08 x S.28 mm
100 IJm (min)
62SIJm ±2SlJm
Chip Size
Pad Pitch
Chip thickness
416
SED1560
•
Pad Coordinates
No, Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
V5
V4
V3
V2
V1
Voo
MIS
RES
SCl
SI
PIS
CS1
CS2
C86
AO
WR
RD
Vss
DO
D1
D2
D3
D4
D5
D6
D7
DYO
ClO
SYNC
FR
Cl
OSC2
OSC1
T2
T1
VSS
CAP1+
CAP1CAP2+
CAP2VOUT
V5
VR
Voo
V1
V2
V3
V4
V5
00
01
02
03
04
X
Coord,
3640
3489
3339
3188
3037
2889
2755
2604
2453
2302
2151
2001
1850
1699
1548
1397
1247
1077
945
794
643
493
342
191
40
-111
-261
-412
-563
-714
-865
-1015
-1166
-1317
-1468
-1638
-1789
-1939
-2090
-2241
-2392
-2543
-2674
-2844
-2995
-3146
--3297
-3447
--3598
--3887
--3887
--3887
-3887
--3887
Y
Coord,
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2294
2194
2094
1994
1894
Unit: 11m
No, Pin Name
X
Coord,
Y
Coord,
No, Pin Name
X
Coord,
Y
Coord,
No, Pin Name
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
--3887
-3887
--3887
-3887
--3887
--3887
-3887
-3887
--3887
--3887
--3887
-3887
--3887
-3887
--3887
--3887
--3887
--3887
-3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
--3887
-3887
-3887
-3887
--3887
-3887
--3887
--3711
--3611
-3511
-3411
--3311
--3211
--3111
-3011
-2911
-2811
-2711
-2611
-2511
1794
1694
1594
1494
1394
1294
1194
1094
994
894
794
694
594
494
394
294
194
94
-6
-106
-206
--306
-406
-506
-606
-706
-806
-906
-1006
-1106
-1206
-1306
-1406
-1506
-1606
-1706
-1806
-1906
-2006
-2106
-2206
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
-2411
-2311
-2211
-2111
-2011
-1911
-1811
-1711
-1611
-1511
-1411
-1311
-1211
-1111
-1011
-911
-811
-711
-611
-511
-411
--311
-211
-111
-11
89
189
289
389
489
589
689
789
889
989
1089
1189
1289
1389
1489
1589
1689
1789
1889
1989
2089
2189
2289
2389
2489
2589
2689
2789
2889
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
417
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
COMI
X
Coord,
Y
Coord,
2989
3089
3189
3289
3389
3489
3589
3689
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2487
-2206
-2106
-2006
-1906
-1806
-1706
-1606
-1506
-1406
-1306
-1206
-1106
-1006
-906
-806
-706
-606
-506
-406
--306
-206
-106
-6
94
194
294
394
494
594
694
794
894
994
1094
1194
1294
1394
1494
1594
1694
1794
1894
1994
2094
2194
2294
I
SED1560
• TCP Dimensions (2-sided)
+
x
8.8
D
D
D
D
418
SED1560
•
TCP Dimensions (4-sided)
+
x
0 0
I
0
0
+
>-
G
o
o
0.60
34.9750
419
THIS PAGE INTENTIONALLY BLANK
420
V. HIGH-DUTY LCD
SEGMENT DRIVERS
1996
DATABOOK
GRAPHICS
PRODUCTS
421
THIS PAGE INTENTIONALLY BLANK
422
•
HIGH-DUTY LCD SEGMENT DRIVERS
Part Number
SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED
1180 1181 1181 1570 1600 1601 1606 1620 1640 1648 1681 1722 1724 1742 1744 1748 1752 1756 1758 1765 1766 1770 1771
xLA FOAl
5A
Yes Yes Yes No Yes Yes
No Yes No
No
No
No
No
No
No
No
No
No
No
No
No Yes
No
SED No
No SED SED No
- SED 168x 168x
1606
168x
64
64
64
80
80
80
80
128
80
80
80
80
80 160 160 160 240 240 160 160 160 160 162
Discontinued?
Replacement
Resolution of segments
Duty Cycle
1/64
to
1/128
LCD Voltage (V)
static
to
1/32
-14 -3 to
-12
to
-25
Supply Voltage
15V
13V
Display Data Bus
(Bits)
~
w
1
2
3
(R,G,B)
4
x
x
x
x
1/64 1/64 1/100 1/100 1/100 1/64 1/100 1/100
to
to
to
to
to
to
to
to
1/128 1/200 1/300 1/300 1/300 1/200 1/300 1/300
-14
to
-25
8 to
20
-12
to
-28
x
x
x
x
Panel Type
I Passive
IMIM
ITFT
(continued)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
0.6
1190 1210/
78
x
x
6
1191
x
x
8 to 14 to 14 to 14 to 14 to 5 to
42
42
42
40
40
17
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5 to
17
x
x
x
x
x
x
x
1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100 1/100
to
to
to
to
to
to
to
to
to
to
to
to
1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500 1/500
-12 -8 to -8 to -3 to 14 to 14 to 14 to 14 to 8 to
to
-28 -28 -12
40
40
40
40
42
-28
x
8
Xscl,max (Mhz)
Companion Chips
-12 -8 to
to
-28
-28
1/8
to
1/32
6.6
7.5
7.5
1
12
1635 1610/ 16101 16301 1631/ 1635
30/31 30/31
35
32
1651
1278
1733
x
x
x
x
6.5
x
6.5
x
x
i
10
x
4
x
x
I
X
X
X
X
12
12
12
16
18
1733
1743
1743
1743
1743
x
x
x
x
x
X
X
x
18
12
12
10
10
1755
1743
1703
1703
1743
1743
x
x
x
x
x
x
X
x
x
-
~-
-
-
-
-
~-
-
-
•
HIGH-DUTY LCD SEGMENT DRIVERS (continued)
SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED SED
1180 1181 1181 1570 1600 1601 1606 1620 1640 1648 1681 1722 1724 1742 1744 1748 1752 1756 1758 1765 1766 1770 1771
xLA FON
Part Number
5A
Package
Die
AI
DOA DLA
Au
COG
Pad Pitch
190
(J.tm)
QFP Thin
FOA
Thick
F5A FLA
# of Pins
80
80
TAB 2 side
Lead Pitch
(11m)
Slim
Page number
~
--
425
443
DOA DOA DAA DAA DOA
DOB DAB
DOB
180
190 170
153
FOA
F5A
80
FAA FAA
100 100
153
DOA DOA DOA DOA
DOB
DOA
125 105
DOA DOA DOA DOA
DOB DOB DOB
D1B D1B DOB
DOA
178
160
160
160 108
108
82
134
TOA#
469
479
120
120
673
673
FOA FOA FOA
100 100 100
TOA TOA TOA
180 180
435 453
134
489
503 513
Notes:
1. Some packages of certain parts labeld with # are still under development.
TOA
TOA
525
539
551
551
563
563
583
599
TOA
TOB
(flex)
615 627 645
657
CMOS LCD 64-SEGMENT DRIVER
•
DESCRIPTION
The SED1180 is a dot matrix LCD segment (column) driver for driving high-capacity LCD panel at duty cycles
higher than 1/64. The LSI contains 64-bit shift register for display data. The display data is supplied through
4-bit bus, and serially transferred through 16 x 4 bit shift register. The display data is held in a 64-bit latch
circuit. The LSI converts the level of the latched data to an LCD drive waveform.
The SED1180 is used in conjunction with the SED1190 (64-bit row driver) to drive a large-capacity dot matrix
LCD panel.
•
FEATURES
• Low-power CMOS technology
• Wide range of LCD voltage .......... -14V to -25V
• 64-bit segment (column) driver
• Supply voltage .................................. 5.0V ±10%
• High-speed 4-bit data
• Duty cycle..................................... 1/64 to 1/128
• Package ................................ QFP1-80 pin (FaA)
QFP5-80 pin (F5A)
DIE: AI pad chip (DOA)
• Daisy chain enable support
•
SYSTEM BLOCK DIAGRAM
DO - D3
XSCL
LP,FR
LCD
CONTR
-
YSCL
YD
I
I
SED1190
~
SED1180
SED1180
SED1180
SED1180
~~
~~
~~
~~
256 SEG X 64 COM
DUTY: 1/64
425
I
SED1180
•
I
BLOCK DIAGRAM
o
"
DO
~
01
~
02 ~
03 ~
lP
XSCl
EI
ECl
§
~G
C-
------------ 31
SEG
"
"
LCD Driver
32 bits
level Shifter
32 bits
latch
32 bits
Shift Register
32 bits
w
~
FR
Vss } - - - /
VDD } - - - /
~
~
r
Voltage Control
Control
r'!
~
Shift Register
32 bits
latch
32 bits
level Shifter
32 bits
LCD Driver
32 bits
EO
TEST
~
V2 }---/
V3 } - - - /
~
VSSH
32
•
33
SEG
- - 63
PIN CONFIGURATION
64
41
65
40
80
25
24
426
SED1180
•
Number
Name
Number
Name
Number
Name
Number
Name
1
SEG27
21
SEG7
41
SEG36
61
SEG56
2
SEG26
22
SEG 6
42
SEG37
62
SEG57
3
SEG25
23
SEG 5
43
SEG38
63
SEG58
4
SEG24
24
SEG4
44
SEG39
64
SEG59
5
SEG23
25
SEG3
45
SEG40
65
SEG60
6
SEG22
26
SEG2
46
SEG41
66
SEG61
7
SEG21
27
SEG 1
47
SEG42
67
SEG62
8
SEG20
28
SEG 0
48
SEG43
68
SEG63
9
SEG19
29
EO
49
SEG44
69
VSSH
10
SEG18
30
03
50
SEG45
70
V2
11
SEG17
31
02
51
SEG46
71
V3
12
SEG16
32
01
52
SEG47
72
Vss
13
SEG15
33
DO
53
SEG48
73
Voo
14
SEG14
34
XSCL
54
SEG49
74
TEST
15
SEG13
35
LP
55
SEG50
75
EI
16
SEG12
36
FR
56
SEG51
76
ECL
17
SEG11
37
SEG32
57
SEG52
SEG10
38
SEG33
58
SEG53
77
78
SEG31
18
19
SEG 9
39
SEG34
59
SEG54
79
SEG29
20
SEG 8
40
SEG35
60
SEG55
80
SEG28
SEG30
PIN DESCRIPTION
Pin Name
SEGO to SEG63
Function
Outputs to segment pins of LCD. Output level changes at each latch pulse
LP falling edge.
XSCL
LP
Data shift clock input: display data is shifted in on the falling edge of this signal.
Latch pulse for displayed data, falling edge trigger: display data is latched on the
falling edge of this signal.
FR
LCD AC-drive signal
EI
Active high daisy chain enable input
EO
Active high daisy chain enable output
ECL
Daisy chain enable clock: the daisy chain enable is propagated on the falling
edge of this clock.
DO to 03
4-bit display data input
TEST
Test output
Voo, Vss
Logic power inputs
V2, V3, VSSH
LCD drive power inputs
VSSH: -14V to -23V
Voo ~ V2 ~ V3 ~ VSSH
427
I
SED1180
•
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage (1)
Supply voltage (2)
Symbol
Ratings
Unit
Vss
-7.0 to +0.3
V
-28.0 to +0.3
V
VSSH
V2, V3
VI
Vss - 0.3 to +0.3
V
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-55 to +125
°C
Soldering temperature time
Tsol
260°C, 10 sec (at lead)
-
Input voltage
Notes:
1. All voltage measurements are based on Voo = OV.
2. V2 and V3 must always satisfy the condition VDD <: V2, V3 <: VSSH.
3. Exceeding the absolute maximum ratings can result in permanent damage to the device. Functional operation under these
conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally
stressing the package during board assembly.
428
SED1180
•
•
ELECTRICAL CHARACTERISTICS
DC Electrical Characteristics
Parameters
Supply voltage (1)
Supply voltage (2)
Symbol
Condition
Rating
Unit
Min
Typ
Max
Vss
-S.S
-S.O
-4.S
V
V2
VSSH
-
VDD
V
V3
VSSH
-
VDD
V
VSSH
HIGH-level input voltage
(VDD = OV, VSS = -S.O V ± 10%, Ta = -20 to 7S°C)
Recommended VSSH
-2S.0
-
-14.0
V
Operable VSSH (see note)
-2S.0
-
-S.O
V
0.2Vss
-
VDD-0.3
V
Vss-D.3
-
O.SVss
V
-
V
-
VIH
LOW-level input voltage
VIL
HIGH-level output voltage
VOH
IOH = -0.6 ma
-0.4
VOL
IOL= 0.6 ma
-
Vss+O.4
V
Input leakage current
III
-
O.OS
2.0
IlA
Output leakage current
ILO
o V5,VI5, Vss
o V 5,V05, Vss
-
O.OS
S.O
IlA
MHz
LOW-level output voltage
Shift clock
XSCL
Frame signal
FR
Input capacitance
CI
Ta = 2SoC
RSEG
VSSH = -20.0 V
VOH = VDD = -O.S V
VOL = VSSH = +O.S V VSSH = -14.0 V
SEG bit
VSSH =-9.0 V
Segment output on
resistance
VSSH =-S.O V
Quiescent current
Operating current for the
logic
Operating current for the
LCD
10
Isso
IssHo
VSSH = -2S V, VSSH = -S.S V, VI = VDD
FR cycle = 16.7 ms
ECl cycle = 13 IlS
FR cycle = 16.7 ms
ECl cycle = 13 IlS
(continued)
429
Vss =-S.OV,
VIH = VDD,
VIL = Vss,
lP cycle=130 IlS,
XSCL=1.S MHz,
(duty SO%)
All data input
reversed bit by
bit. All output
pins are open.
Vss =-4.S V,
V2 =-4.0 V,
V1 =-16.0 V,
VSSH = -20.0 V,
VIH = VDD,
VIL = VSS,
XSCL=1.S MHz,
(duty SO%),
all data input
reversed bit by
bit. All output
pins are open.
-
6.0
1/60
-
S
S.O
S.O
pF
-
1.9
2.9
2.4
3.9
-
3.6
7.0
-
11.S
SOO.O
-
O.OS
30
IlA
-
90
200
IlA
-
40
SO
IlA
kQ
I
SED1180
•
DC Electrical Characteristics (continued)
Parameters
Symbol
Condition
Rating
Min
Typ
Max
Unit
tcLC
166
-
-
ns
Shift clock "H" width
tWCLH
63
ns
Shift clock "L" width
-
Shift clock cycle
tWCLL
63
Data setup time
tos
50
Data hold time
tOH
30
-
ns
ns
ns
Enable clock "H" width
tWECH
See note 4
100
-
-
ns
Enable clock "L" width
tWECL
See note 4
100
tEOS
See note 4
50
-
ns
Enable data setup time
-
Enable data hold time
tEOH
Seenote 4
20
-
-
ns
Enable clock delay time
tEOR
See note 4
-10
-
ns
ns
tECS
See note 4
70
-
Latch pulse "H" width
tWLPH
See nOle 2
110
-
-
ns
Latch pulse "L" width
tWLPL
220
-
ns
Latch timing
tLT
100
-
ns
Latch hold time
tLH
0
tLOS
See notes 3 & 4
140
-
ns
Latch pulse data setup time
-
Latch pulse data hold time
tLoH
See notes 3 & 4
50
-
-
ns
Permissible frame signal delay
tOFR
-500
-
500
-
See note 4
Enable clock setup time
Input signal rise time
tr
Input signal fall time
tf
Enable output delay
tpo
See note 4
20
-
See note 4
150
ns
ns
ns
ns
Notes:
1. While the drive is guaranteed to operate without error within this voltage range, the output resistance of the segment drivers
will be higher than that in the recommended operating range. It is suggested that the drive capability of the driver under these
conditions is tested using the target panel.
2. tWlPH
= 160 ns (min) when LP is used as EI data.
3. tWlPH = 250 ns (min) when EO is reset by LP.
4. Applies to the SED1180F only.
5. tf, tf < (tClC - tWClH - tWCll) / 2 and tf, If ~ 50 ns.
430
SED1180
•
•
AC ELECTRICAL CHARACTERISTICS
Data 1/0 Timing
1 line period
FR
lP
Enlarged
FR
lP
~------------~~------------~~
EI
ECl
.... JLfVUL......... .
XSCl
DO
to
I
D3
EO
~
FR
-----------------.----tW-L-P-H--.---~---tF-R---.-
lP
EI
ECl
XSCl
DO
to
D3
EO
431
VIH= 0.2 xVss
VIL = 0.8 x Vss
SED1180
•
Segment Drive Timing
LP
~"VIL
:x
FR
~
VIH
" VIL
..
tFRSU
~
-tLPSO-
:x
SEG out
VIH
Parameters
'--Vn -O.5V
,Vn +O.5V
VOO,V2
V2, V3, VSSH
= 0.2Vss; VIL = 0.8Vss (VDD =OV, Vss = -S.O V ±10%, Ta = -20 to 7S°C)
Rating
Symbol
Condition
LP-SEG output delay time
tLPSD
VssH=-14.0 to -2S.0 V
-
-
4.S
/.ls
FR-SEG output delay time
tFRSD
CL= 100 pF
-
-
4.S
/.ls
432
Min
Typ
Max
Unit
SED1180
•
TYPICAL SYSTEM CONNECTION
(64 x 640 pixels, 1/64 duty ratio)
'2
... YSCL SED1190
lP
YSC l
YO
YOI S
..
•
•
lAT
OIN
INH<
a
~
-n'"
:Ill'!
<
!?
:::
R
-
SEG
a
63 -
SEG
SEG
a
63 -
a
63 -
a
<
'"'"
+~C
V2
Cz +
SEG
63
;::.
Rt
V1
64 x 640 Full Dot Graphic Display
"
+
LCD PANEL
COM
63
0-----63 64--- 127 128 - - - 191 - - - - - 576 -----639
Vss
Voo
I
I
I
I
I
I
SE01180
SE01180
SE01180
SE01180
1
2
3
10
,. EI
4
5R
EOr-- EI
FR lP
EO- EI
FR lP
EO f-- - - - - ---- EI
EO
FRlP
FR lP
V3
+
C
R
V4
0
----~
4
4
0
+
L
Voo, Vss
V2, V3
4
C
R
:0
,
-1 1000 1
-----
VSSH
FR
lP
ECl ,XSCl
001003
----
------ -
2
2
2
4
4
4
Notes:
1. Current limiting resistors
2. Bypass Vss and VSSH with capacitors of at least 0.01 J.lF
433
-----
j
4
I
THIS PAGE INTENTIONALLY BLANK
434
CMOS LCD 64-SEGMENT DRIVER
•
DESCRIPTION
The SED1181 is a dot matrix LCD segment (column) driver for driving high-capacity LCD panel at duty cycles
higher than 1/64. The LSI contains 64-bit shift register for display data. The display data is supplied through
LCD controller, and serially transferred through 16 x 4 shift register. The display data is held in a 64-bit latch
circuit. The LSI converts the level of the latched data to an LCD drive waveform.
The SED1181 is used in conjunction with the SED1191 (64-bit row driver) to drive a large-capacity dot-matrix
LCD panel.
•
FEATURES
• Low-power CMOS technology
• Wide range of LCD voltage .......... -14V to -25V
• 64-bit segment (column) driver
• Supply voltage ................................. 5.0V ± 10%
• Serial 2-bit input data
• Package ................................ QFP1-80 pin (FOA)
QFP5-80 pin (FSA)
• Duty cycle ..................................... 1/64 to 1/128
• Daisy chain enable support
•
I
SYSTEM BLOCK DIAGRAM
DO - 01 (SERIAL DATA)
XSCL
LCD
CONTR
LP,FR
YSCL
r--YO
~
I SED1191 ~
SED1181
SED1181
SED1181
SED1181
~~
~~
~~
~~
256 SEG X 64 COM
DUTY: 1/64
435
SED1181
•
BLOCK DIAGRAM
o
DO
LP
01
FR
~
Vss
31
f
LCD Driver
32 bit
Level Shift
32 bit
Latch
32 bit
Shift Register
32 bit
~
XSCL
- -- -SEG- - -- -
I-
000
r--
Voltage Control
Shift Register
32 bit
Latch
32 bit
Level Shifter
32 bit
LCD Driver
32 bit
001
I-
VDD
V2 'r
V3 'r
VSSH
'r
32
•
PIN CONFIGURATION
64
41
65
40
80
25
24
436
SED1181
•
Number
Name
Number
Name
Number
Name
Number
Name
1
SEG27
21
SEG7
41
SEG36
61
SEG56
2
SEG26
22
SEG 6
42
SEG37
62
SEG57
3
SEG25
23
SEG 5
43
SEG38
63
SEG58
4
SEG24
24
SEG4
44
SEG39
64
SEG59
5
SEG23
25
SEG 3
45
SEG40
65
SEG60
6
SEG22
26
SEG2
46
SEG41
66
SEG61
7
SEG21
27
SEG 1
47
SEG42
67
SEG62
8
SEG20
28
SEGO
48
SEG43
68
SEG63
9
SEG19
29
000
49
SEG44
69
VSSH
10
SEG18
30
NC
50
SEG45
70
V2
11
SEG17
31
NC
51
SEG46
71
V3
12
SEG16
32
01
52
SEG47
72
Vss
13
SEG15
33
DO
53
SEG48
73
Voo
14
SEG14
34
XSCL
54
SEG49
74
001
15
SEG13
35
LP
55
SEG50
75
NC
16
SEG12
36
FR
56
SEG51
76
NC
17
SEG11
37
SEG32
57
SEG52
77
SEG31
18
SEG10
38
SEG33
58
SEG53
78
SEG30
19
SEG9
39
SEG34
59
SEG54
79
SEG29
20
SEG8
40
SEG35
60
SEG55
80
SEG28
PIN DESCRIPTION
Pin Name
Function
DO
Serial data input to upper shift register
01
Serial data input to lower shift register
SEGO to SEG 31
Segment driver outputs supplied by the upper shift register
SEG 32 to SEG 63
Segment driver outputs supplied by the lower shift register
XSCL
Data shift clock input
LP
Data latch pulse input
FR
LCD frame signal input
000
Serial data output from upper shift register
001
Serial data output from lower shift register
Voo, Vss
Logic circuitry power inputs
VSSH, V2, V3
LCD drive power inputs
Voo > V2 > V3 > VSSH
437
I
SED1181
•
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage (1)
Symbol
Ratings
Unit
Vss
-7.0 to +0.3
V
-28.0 to +0.3
V
VSSH
Supply voltage (2)
V2, V3
VI
Vss -0.3 to +0.3
V
Operating temperature
Input voltage
Topr
-20 to +75
°C
Storage temperature
Tstg
-65 to +150
°C
Soldering temperature, time
Tsol
260°C, 10 sec (at lead)
oct Sec
Notes:
1. All voltages are based on a Voo of
av.
2. V2 and V3 must satisfy the condition Voo GDGDGDG4:::::::::::::::XillGXIX
ooolooqi::::: :::::::::::::::::::::::::::::::::~~:::::::::::::::::::x:=x=:x=
FR
--------------------------.---I-DF-'~~~~:~~-------------
LP
IWLPL ----~I
1 . _ - - - - - IWLPL
XSCL
DO 1001
00010001
VIH
=x______________-' ~______~x~________
=0.2 x VSS
VIL = 0.8 x VSS
440
SED1181
•
AC Electrical Characteristics
Parameter
Symbol
Conditions
Rating
Min
Typ
Unit
Data setup time
tDS
SO
Data hold time
tDH
30
-
Latch pulse "H" time
tWLPH
110
-
-
ns
Latch pulse "L" time
-
ns
tCLC
166
Shift clock "H" width
tWCLH
63
Shift clock "L" width
tweLL
63
-
Max
-
Shift clock cycle time
tWLPL
220
-
Latch hold time
tLT
100
XSCL to LP fall time
tLH
0
-
tDFR
-SOO
Permissible frame signal delay
Input signal rise time
Input signal fall time
Data output delay time
•
VSS = -S.O V ± 10%, Ta = -20 to 7SoC
tr
tf
tpD
0
SOO
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
ns
-
-
20
-
1S0
-
I
Segment Drive Output Timing
LP
" \ , , , VIL
~----------------------
FR
v~
VIH
~k----------------~--~
VIL
...
• tFRSU
---tLPSDL /"V----O-.-5V- VDO ,V2
n
V
SEG out
/"'...,,, Vn +O.5V
_ _ _ _ _ _ _ _ _ _ _- J
V2,V3,VSSH
VIH = 0.2Vss; VIL = O.BVss; Vn: VDD, V2, V3, VSSH; (Vss = -S.O V ±10%, Ta = -20 to 7S°C)
Rating
Symbol
Condition
Lp·SEG output delay time
tLPSD
VssH=-3.0 to -12.0 V,
FR·SEG output delay time
tFRSD
CL= 100 pF
Parameter
441
Min
-
Typ
-
Max
Unit
4.S
~s
4.S
~s
THIS PAGE INTENTIONALLY BLANK
442
CMOS DOT MATRIX EXTENSION LCD DRIVER
• 64-bit high voltage output
• Display duty factor: static to 1/32
• CMOS high-voltage process
•
DESCRIPTION
The SED1181 FLA is an expansion segment (column) driver suitable for driving high-contrast, small capacity
dot matrix liquid crystal displays with a duty from static to 1132. It is best suited for expanding the segment
drive capability of LCD controllers such as the SED1278F, the SED1210F, or a 4-bit microcomputer.
•
FEATURES
•
•
•
•
•
•
Low-power CMOS technology
64-bit segment (column) driver
Serial input data
Duty cycle ..................................... Static to 1/32
Suitable for use with a wide range of LCD controllers
•
•
•
•
Capable of a serial cascade connection
Wide range of LCD voltage ......... -3.0V to -12V
Supply voltage ................................ 2.4V to 6.0V
Package ................................ QFP5-80 pin (FLA)
DIE: AI pad chip (DLA)
SYSTEM BLOCK DIAGRAM
40SEG
DATA
CPU
\)
SED1278
CONTROL
16 COM>
20 CHAR x 2 LINES
~
w
en
~
XSCL, LP
DO
443
SED1181FLA
I
SED1181 FLAlFoA
•
,
BLOCK DIAGRAM
----SEG- ----
o
31
~
DO
LP
LCD Driver
32 bit
Level Shift
32 bit
Latch
32 bit
Shift Register
32 bit
W
XSCL
D1
FR
~
VSS
~
DOO
r
Voltage Control
Shift Register
32 bit
Latch
32 bit
Level Shifter
32 bit
LCD Driver
32 bit
D01
~
VDD
V2
V3 ,r-------'
Vss H
32
•
33
- - - - SEG- - - - -
63
PIN CONFIGURATION
64
41
65
40
SED1181FLA
80
25
24
444
SED1181 FLAlFoA
Number
Number
Number
Name
Name
Number
Name
SEG56
1
SEG27
21
SEG7
41
SEG36
61
2
SEG26
22
SEG6
42
SEG37
62
SEG57
SEG58
3
SEG25
4
SEG24
23
24
SEG23
25
5
6
7
•
Name
SEG22
SEG21
26
27
SEG5
SEG4
43
SEG38
63
44
SEG39
64
SEG59
SEG3
45
SEG40
65
SEG60
SEG2
46
SEG41
66
SEG61
SEG 1
47
SEG42
67
SEG62
SEG43
68
SEG63
8
SEG20
28
SEGO
48
29
DOO
49
SEG44
69
VSSH
50
SEG45
70
V2
9
SEG19
10
SEG18
30
NC
11
SEG17
31
NC
51
SEG46
71
V3
12
SEG16
32
D1
52
SEG47
72
Vss
33
34
DO
53
SEG48
73
Voo
XSCL
54
SEG49
74
D01
NC
13
SEG15
14
SEG14
15
SEG13
35
LP
55
SEG50
75
16
SEG12
36
FR
56
SEG51
76
NC
17
SEG11
37
SEG32
57
SEG52
77
SEG31
18
SEG10
38
SEG33
58
SEG53
78
SEG30
19
SEG9
39
SEG34
59
SEG54
79
SEG29
20
SEG8
40
SEG35
60
SEG55
80
SEG28
PIN DESCRIPTION
Pin Name
Function
I/O
DO
I
Serial data input to upper shift register
D1
I
Serial data input to lower shift register
SEGO to SEG31
0
Segment driver outputs supplied by the upper shift register (output level changes
at each latch pulse LP falling edge)
SEG32 to SEG65
0
Segment driver outputs supplied by the lower shift register
XSCL
I
Data shift clock input for display data - falling edge
LP
I
Data latch pulse input for display data - falling edge
FR
I
LCD frame signal input
000
0
Serial data output from upper shift register DO
001
0
Serial data output from lower shift register 01
Voo, Vss
I
Logic circuitry power inputs
V2, V3, VSSH
I
LCD drive power inputs. Voo > V2 > V3 > VSSH
445
I
SED1181 FLAlFDA
•
ABSOLUTE MAXIMUM RATINGS
Symbol
Ratings
Unit
Vss
-7.0 to 0.3
V
Supply voltage (2)
VSSH
-15.0 to 0.3
V
Supply voltage (3)
V2, V3
-15.0 to 0.3
V
Input voltage
VIN
Vss -0.3 to 0.3
V
Output voltage
Vo
Vss -0.3 to 0.3
V
Permissible power dissipation
Pd
250
mW
Operating temperature
Topr
-30 to 85
Storage temperature
Tstg
-65 to 150
Soldering temperature, time
Tsol
260 o e, 10 sec
°e
°e
°e, s
Parameter
Supply voltage (1)
Notes:
1. All voltages are based on a Voo of OV.
2. V2 and V3 must satisfy the condition Voo 2: V2, V3 2: VSSH.
3. Exceeding the absolute maximum ratings can cause permanent damage to the device. Functional operation under these
conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally
stressing the package during board assembly.
446
SED1181 FLAlFoA
•
•
ELECTRICAL CHARACTERISTICS
DC Electrical Characteristics
Parameter
Supply voltage (1)
Ta = -30 to 8SoC (unless otherwise specified)
Vss = -S.OV ±10% (unless otherwise specified)
Rating
Condition
Symbol
Unit
Min
Typ
Max
Vss
-6.0
-S.O
-2.4
V
V2
VSSH
-
Voo
V
V3
VSSH
Voo
V
-3.0
V
-2.S
V
Voo+0.3
V
V
High-level input voltage
VIH
0.2Vss
-
Low-level input voltage
VIL
Vss-O.3
-
0.8Vss
High-level output voltage
VOH
IOH=-O.6mA
-0.4
V
VOL
IOL=0.6 mA
-
-
Low-level output voltage
Vss+0.4
V
Supply voltage (2)
VSSH
Input leak current
III
Output leak current
ILO
Transmission clock
XSCL
Frame cycle
FR
Input pin capacity
CIN
SEG output ON
resistance
RSEG
Recommended operation VSSH
Potential operation VSSH • 2
-12.0
oV !> VIN !> Vss
oV !> VOUT!> VSS
Ta=2SoC
Ll VON = 0.1 V
Ta=2SoC
-8.0V
VSSH -S.OV
-3.0V
Static current consumption
Logic power supply's
average current
consumption
LC~'s average current
consumption
10
IssOP
IssHOP
-12.0
VssH=-12.0V, Vss=-6.0V,
VIN= Voo
Vss = -S.O V, VIH = Voo, VIL = Vss,
FR cycle = 16.7 ms (duty SO%)
LP cycle = S20 ILS,
XSCL = 400 kHz (duty SO%)
All data input: Inverted at each bit
All output pins are open.
Vss = -4.S V, V2 = -4.8 V,
V3 = -7.2 V, VSSH = -12.0 V
Other conditions are identical to
those for Iss OP
-
O.OS
2.0
ILA
0.05
S.O
!LA
-
600
kHz
1/60
-
sec
-
S.O
8.0
pF
-
3.0
5.0
-
kQ
16.0
-
-
0.05
30.0
!LA
-
250
300
!LA
-
8
10
!LA
Notes:
1. The voltage values are based on a Voo of 0 V.
2. The driver will operate with a value of VSSH in this range, however the ON source impedance of a segment drive can be higher
than that at the recommended value of VSSH. It is recommended that the drivers are tested with the LCD panel they will be
used with, to determine a suitable value for VSSH.
447
I
SED1181 FLAlFoA
•
AC Electrical Characteristics
Parameter
Shift clock cycle
(Vss = -6.0 to -2.4V, Ta = -30 to 85°C)
Symbol
Conditions
Rating
Typ
Max
-
-
/.lS
tClC
1.66
Shift clock pulse width (High)
twClH
450
Shift clock pulse width (Low)
twCll
600
Data set-up time
tos
100
Data hold time
tOH
30
Latch pulse width (High)
twlPH
200
Latch pulse width (Low)
twlPl
600
tLT
200
Latch timing cycle
Latch hold time
Permissible frame signal delay time
Input signal rise time
Input signal fall time
Serial data output delay time
Unit
Min
-
ns
ns
ns
ns
ns
ns
tlH
100
-
tOFR
-500
0
500
ns
tr
ns
tpo
20
-
50
tt
-
448
ns
ns
50
ns
250
ns
SED1181 FLNFoA
•
Display Data Input/Output Timing
_ _ 1 line period
FR
2
3
4
5
29
30
31
2
32
3
LP
FR
LP
31
32
33
34
n-l
n
............... ~............. ~
XSCL
001001
3:::::::::::::::~~:::::::::::::::~
ooolooqi::::: :::::::::::::::::::::::::::::::::~~::::::::::::::::::::x=x=x=
FR
LP
IWLPL .......•....•...
........ IWLPL
XSCL
001001
___--'x'--___
00010001
VIH = 0.2 x VSS
VIL = 0.8 x VSS
449
I
SED1181 FLAIFOA
•
Segment Drive Output Timing
LP
VIH = 0.2 x VSS
VIL = 0.8 x VSS
~k-VIL
X ..
FR
~
VIH
"
VIL
• tFRSU
-tLPSO-
X
f-V n -O.5V
SEG out
k- Vn +O.5V
VOO,V2
V2, V3,VSSH
Vn:VDD, V2,V3, VSSH
(VSS = -6.0 to -2.4V, Ta = -30 to 85°C)
Item
Symbol
Condition
Rating
Min
Typ
Max
Unit
LP-SEG output delay time
tLPSD
VSSH= -3.0 to -12.0 V,
-
-
4.5
IJS
FR-SEG output delay time
tFRSD
CL= 100 pF
-
-
4.5
IJS
450
SED1181 FLAlFoA
• PAD LAYOUT
64
Chip size .................................. 4.85mm x 3.57mm
Chip thickness .................................. 0.4 ± 0.03mm
Pad size ............................... 0.1 04mm x 0.1 04mm
Pad pitch ............................... '" ................. 0.19mm
Chip metalization .................. '" ........................... AI
41
000000000000000000000000
65
0
0
o
o
o
o
o
o
o
o
o
0
0
Note: Connect underside to GND or insulate
0
0
o
o
0
0
0
o
o
0
o
0
yBOO
L:
40
0
0
0
0
0
025
000000000000000000000000
1
M
X
•
PAD COORDINATION
Pad
Number Name
1
SEG27
2
SEG26
3
SEG25
4
SEG24
5
SEG23
SEG22
6
7
SEG21
8
SEG20
9
SEG19
10
SEG18
11
SEG17
12
SEG16
13
SEG15
14
SEG14
15
SEG13
16
SEG12
17
SEG11
18
SEG10
19
SEG9
20
SEG8
21
SEG7
22
SEG6
23
SEG5
24
SEG4
25
SEG3
26
SEG2
27
SEG1
X
Y
(~m)
(~m)
155
423
614
804
995
1185
1375
1566
1756
1947
2137
2327
2518
2708
2899
3089
3279
3470
3660
3851
4041
4231
4422
4690
4690
4690
4690
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
345
536
726
Pad
Number Name
28
SEGO
29
DOO
30
NC
31
NC
D1
32
33
DO
34
XSCL
35
LP
36
FR
37
SEG32
38
SEG33
SEG34
39
40
SEG35
41
SEG36
42
SEG37
43
SEG38
44
SEG39
45
SEG40
46
SEG41
47
SEG42
48
SEG43
49
SEG44
50
SEG45
51
SEG46
52
SEG47
53
SEG48
54
SEG49
451
X
Y
(~m)
(~m)
4690
4690
4690
4690
4690
4690
4690
4690
4690
4690
4690
4690
4690
4690
4422
4231
4041
3851
3660
3470
3279
3089
2899
2708
2516
2327
2137
916
1107
1297
1488
1678
1868
2059
2249
2440
2630
2820
3011
3201
3392
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
Pad
Number Name
55
SEG50
56
SEG51
57
SEG52
SEG53
58
59
SEG54
SEG55
60
SEG56
61
62
SEG57
SEG58
63
64
SEG59
65
SEG60
SEG61
66
67
SEG62
SEG63
68
VSSH
69
V2
70
71
V3
72
Vss
73
VDD
74
D01
75
NC
76
NC
77
SEG31
78
SEG30
79
SEG29
80
SEG28
X
Y
(~m)
(~m)
1947
1756
1566
1375
1185
995
804
614
423
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
155
3415
3415
3415
3415
3415
3415
3415
3415
3415
3392
3201
3011
2820
2630
2440
2249
2059
1868
1676
1488
1297
1107
916
726
536
345
I
SED1181 FLAlFoA
•
REFERENCE CIRCUIT EXAMPLES
(12 characters, 4 lines, 1/16 duty cycle)
SED12?8F
COM1
I
I
I
COM16
~
LCD
16 x 100 dots
R
Lf~/>
40
60
SEG1
I
I
I
SEG40
0
en
en
W
I
LP
XSCL
FR
I
VDD
Vss
V2
V3
V5
OSC1
OSC2
Lvv)
(20 characters, 2 lines, 1/16 duty)
16
common
-------------------------40 segments
L---
~
I
COM16 SEG1
---------- -
60 segments
I
SEG10
COM1
OSC1
I
SO
SHCL
V2
V3
it
DO to 06
Voo Vss VSSH
j
I IIII~
L-.
I
DO
SEGO
SEG59
OSCL
LP
SED1181FLA
FR
SED1210
LP
~
FR
OSC2 DBO
AD l"R VLCD
VL2
ct> lo-ii DB? CS RD VssVoo VL3
Clock ----<
------------------------
- -
Vcc
--
8-bitMPU
J
GND
452
i
01
t
001
SED1570
•
DESCRIPTION
The SED1570 is an BO-segment LCD driver for driving the LCD panel. The SED1570 features internal display
RAM. The display data is stored in RAM and it generates the LCD waveforms.
The LSI offers the "self-refresh mode." It means that no data will transfer from the display controller to the
SED1570 if the contents of the data do not change.
The device allows configuration of an ultra-low-power display system, since the display data is nottransferred
unless the display data is changed.
The SED1570 is used in conjunction with the SED1635 common (100 output row driver) to support LCD
panels from midrange to VGA size. The device is suitable for applications that require low power
consumption.
•
FEATURES
• Low-power CMOS process technology
• High-speed data (4-bit parallel) transfer
• Supports the self-refresh mode
• Daisy chain support
• LCD driver output ................... BO
• Non-bias display off function
• Output shift direction-pin selection
• Duty cycle..... ........... .... ....... .... 1/64 to 1/200
• Display RAM ........................... 200 x BO bits
• Optimize the LCD power offset bias for Voo
• Supply voltage ........................ 2.7 to 5.5V
• Package .................................. AI pad (DoA)
• LCD voltage ............................ B.O to 20V
•
SYSTEM BLOCK DIAGRAM
00- 03
XSCL
LP,FR
LCD
CONTR
-
YSCL
YO
I
ISE01635~
•
ISE01635~
SE01570
SE01570
SE01570
SE01570
~~
~~
~~
~~
320 SEG x 200 COM
DUTY: 1/200
453
I
SED1570
•
BLOCK.DIAGRAM
X1 ----------------XBO
voo
VO
T
>-----
V3
V5
VSS
VEE
.(')
>---->-----
Level Shifter
{~
FR
DOFF
La1ch 80 OUT
J
.(')
XSCL
00-03
~
Row
Address
Counter
Decoder
YO
LP
,~
():::
~
Display RAM
200x80
V
/";.
Control
Gate
Data
Control
6
Data Register 80 bit
1
~
JI
1'1 .
Enable Shift Register
20b~
I
SHL
I
•
•
T
LCD Driver
80 OUT
V1
Enable
Control
r-
EI01
EI02
BLOCK DESCRIPTION
Enable Shift Register
The order of the display data latched is reversed by the SHL input.
•
Enable Control and Data Control
If the enable signal is disabled (EIO ="H"), the internal clock signal and the data bus are fixed to "L"_ This is
a power-save mode.
To use multiple segment drivers, connect in cascade format the EIO pin of each driver, and connect the EIO
pin of the first driver to the "Vss" pin;
The enable control circuit automatically detects when the BO-bit data has been read and automatically
transfers the enable signal. As a result, a control signal by a control LSI is not necessary.
454
SED1570
•
Display RAM
This is a static RAM (200 x 8 bits) that stores the LCD data.
The display RAM data (80 bits) for the low address is read out to the latch with the trailing edge ofthe LP signal.
In addition, with the trailing edge of the LP signal, the contents of the data register are moved to the write
register. The contents of the write register are then written in the display RAM area for the low address. The
low address is then incremented.
If the XSCL signal does not come in after the trailing edge of the LP signal, the mode is changed to the selfrefresh mode. The write register does not write data in the display RAM and the low address is incremented.
The mode is then changed to the read-out mode to read the next line.
•
Low Address Counter Decoder
This selects a line ofthe display RAM in sequence. This decoder catches the "H" ofthe OY signal atthe trailing
edge ofthe LP signal, and resets the low address counter. Itthen initializes the selected address ofthe display
RAM. In a normal operation, the decoder is incremented after the writing operation into the display RAM. (The
writing operation is caused by the trailing edge of the LP signaL) In the self-refresh mode, the decoder is
incremented without the writing operation into the display RAM.
•
Data Register
This 80-bit register controls the write operation into the display RAM. The data is written in the display RAM
with the trailing edge of the LP signal. In the self-refresh mode, the data is not written in the display RAM.
•
Control Circuit
The control circuit detects the self-refresh mode, allows the write register to write the data into the display
RAM, and controls the low address count signal.
•
Latch
This reads the 80-bit data for the low address of the display RAM with the trailing edge of the LP signal, and
sends the output signal to the level shifter.
•
Level Shifter
This is the level interface circuit that converts the Signal voltage level from VDD - Vss to VDD - VEE (LCD driver
power).
•
LCD Driver
DOFF
00-03
FR
The LCD driver outputs the LCD driver Voltage.
H
The table to the right shows the relationship
between the display signals (03 - ~O), LCD ACdrive waveform (FR) and the segment output
voltage.
H
L
L
455
-
H
L
H
L
-
X Output
Voltage
VO
V5
V2
V3
VO
I
SED1570
•
PIN DESCRIPTION
Pin Name
1/0
X1-XSO
0
No. of
Pins
Function
LCD drive segment (column) output
SO
The output changes with the LP's trailing edge.
00-03
I
Display data input
4
XSCL
I
Display data ·shift clock input
1
Reads the display data (DO - 03) into the data register with a trailing
edge.
LP
I/O
Display data latch clock input
1
• The display RAM data (specified by the low address shift register) is
read into the latch with a leading edge, and the LCD display data is
output.
• For a specified low address, the contents of the write register are
written in the display RAM.
E101, EI02
I
• Resets the enable control circuit.
Enable I/O
2
• Configured by SHL.
• Output is reset to "H" by LP input. When the SO-bit display data is
read, the output falls to "L" automatically.
• To connect in cascade format, connect these pins to the next level
EIO.
SHL
I
Shift direction and input/output select input
1
• If the display data is entered in the input (03, 02, 01, DO) in the orde
of (a1, a2, a3, a4) (b1, b2, b3, b4) ... (t1, t2, t3, t4), the relationship 0
the display data and the segment output is as given in the table belo It.
SHL
DOFF
I
Xn (SEG output)
80
L
a1
79
a2
H
t4
t3
78
77
76
75
a3
a4
b1
b2
t2
11
54
53
...
...
...
EIO
6
5
4
3
2
1
1
53
54
11
t2
13
14
0
I
b2
b1
a4
a3
a2
a1
I
0
2
Forced blank input
1
In the "L" level, the segment output is forced to the VO level.
The display RAM data is maintained.
FR
I
LCD AC drive signal input
1
YO
I
Scan start input
1
• Resets the low address counter decoder.
• The number of scanned lines (number of low addresses) for the
display RAM is determined by the number of LP pulses, which are
input in one YO cycle.
YO, V2,
V3, V5
Power
supply
LCD drive power input
VEE
Power
supply
LCD drive power input Voo - VEE
1
Voo, Vss
Power
supply
LogiC power input
2
4.
Voo ~ Vo ~ V2 ~ V3 ~ Vs ~ VEE
Voo: connect to the system Vss pin.
Vss: connect to the system GND.
456
SED1570
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Condition
Supply voltage 1
Vss
-7.0 to +0.3
V
Supply voltage 2
VEE
-22.0 to +0.3
V
Supply voltage 3
Unit
VO, V2,V3, V5
VEE - 0.3 to VDD + 0.3
V
Input voltage
VI
VSS - 0.3 to VDD + 0.3
V
Output voltage
Va
Vss - 0.3 to VDD + 0.3
V
EIO output current
101
20
mA
Operating temperature
TaPR
-40 to +85
Storage temperature 1
TSTG1
-65 to +150
Storage temperature 2
TSTG2
-55 to +100
DC
DC
DC
Notes:
1. All voltages are given relative to VDD = OV.
2. For storage temperature 1 - Plastic package
For storage temperature 2 - TAB mounted
3.
va, V2, V3 and V5 must satisfy the condition VDD ~ va ~ V2 ~ V3 ~ V5 ~ VEE
Voo
- VOO
I
-2.7V!
VSS
- VO
"f
V2
-20V
------V3
- - - - - - - V5, VEE
4. Exceeding the absolute maximum ratings can cause permanent damage to the device. Function operation under these
conditions is not implied.
457
I
SED1570
•
DC Characteristics
Parameter
VDD
Symbol
Condition
Supply voltage
Vss
Recommended
operating voltage
VEE
Vss = -2.7 to -S.SV
Supply voltage (2)
VO
Supply voltage (3)
V2
Supply voltage (4)
=VO =OV, VSS =-5.0V ±1 0%, Ta =-40 to 85°C
Min
Typ
Max
Unit
Pin
-S.S
-S.O
-2.7
V
Vss
-20.0
-
-8.0
V
VEE
Recommended value
VDD-2.S
V
VO
2/9 VEE
V
V2
V3
Recommended value
-
Supply voltage (S)
VS
Recommended value
VEE
Input high voltage
VIH
Vss = -2.7 to -S.SV
0.2' Vss
-
VDD
Recommended value
VDD-0.4
-
Input low voltage
VIL
Output high voltage
VOH
Vss = -2.7 IloH = -0.6mA
Output low voltage
VOL
to-S.SV
-
7/9 VEE
V
V3
VEE + 2.S
V
VS
V
EI01, EI02, FR,
DO to 03, YO, LP,
SHL, DOFF, XSCL
0.8' Vss
-
VDD+0.4
V
Vss :> VIN :> VDD
-
-
2.0
~A
DO to 03, LP, FR,
YO, XSCL, SHL,
DOFF
ILifO
Vss :> VIN :> VDD
-
-
S.O
~A
EI01, EI02
Iss
VS = -20.0 to -1 O.OV
VIH VDD, VIL = Vss
-
-
2S
~
Vss
RSEG
6VON = O.SV, VO = VDD, V3
= 7/9' VEE, V2 2/9' VEE,
VEE VS = -14.0V
-
1.0
1.4
Kn
Xl to X80
IDDT
Vss = -S.OV, VIH = VDD,
VIL = Vss, fxscL = 4.0MHz,
FLP = 14kHz, fFR = 70Hz,
Checkered pattern,
non-burden
-
0.3
0.8
mA
IDDs
fxscL = 0 Hz = Vss,
Another place is same as
IDDT item
-
70
200
~
Average current
consumption (2)
lEE
Vss = -S.OV, VO = O.OV,
V2=-4.0V, V3=-16V,
lEE = VS -20.0V,
Another place is same as
IDDTitem
-
2S
70
~
VEE
Input capacitance
CI
-
-
8
pF
DO to 03, LP, FR,
YO, XSCL, SHL,
DOFF
-
-
lS
pF
E101, EI02
Input leakage current
I/O leakage current
Static current
On resistance
Data
transfer
mode
Average
current
consumption (1)
Selfrefresh
mode
I/O capacitance
III
CliO
IloL= 0.6mA
=
=
=
=
Freq. = 1 MHz, Ta = 2SoC,
Simple substance of CHIP
-
V
-
V
EI01, EI02
VDD
458
SED1570
•
AC Characteristics
° Input Timing
VIH= 0.2 Vss
VIL= 0.8 Vss
YO
....... IYDH-
IYDS"
~
FR
-IWLH~
-IWLL-
~
LP
XSCL
,
Z
•
Ic
•
~
-IDS--
1'\
-ILD----.
'"
•
•
ILH
f"-,
/
.-IDH"
~
00-03
-IDF'"
-IWCH-
i---IWCL
K
I
~------ISUE--
EIO
(IN)
Vss = -5.5 to -2.7V, Ta = -40 to 85°C
Parameter
Symbol
Conditions
Min
Max
Unit
tc
250
-
ns
XSCL high-level pulse width
twCH
70
ns
XSCL low-level pulse width
twCl
70
-
Oata setup time
tDS
50
-
ns
XSCL cycle time
ns
Oata hold time
tDH
50
-
ns
XSCL"<-... --7 LP "<-...
tlD
80
-
ns
LP "<-... --7 XSCL "<-...
tlH
140
-
ns
LP high-level pulse width
tWlH
75
ns
LP low-level pulse width
tWll
75
-
FR phase difference
tDF
-300
EIO setup time
tSUE
50
YO setup time
tYDS
80
YO hold time
tYDH
Rise/fall time
tr, tf
• Recommended IWLH value
z
Ie
459
+300
ns
ns
ns
80
-
-
30
ns
ns
ns
SED1570
° Output Timing
VIH = 0.2 Vss
VIL= 0.8 Vss
FR
LP
XSCL
EIO
(OUT)
Xn
VDD = -5.5 to -2.7V, VEE = -8.0 to -20.0V, Ta = -40 to 85°C
Parameter
Symbol
EIO reset time
tER
EIO output delay time
tDel
LP
~
Xn output delay time
tlSD
FR
~
Xn output delay time
tFRSD
Conditions
Cl = 15pF
(EIO)
Cl=100pF
460
I
IVss =-2.7V
Min
Max
Unit
-
150
ns
95
ns
400
ns
-
400
ns
SED1570
•
•
TIMING DIAGRAMS
Sample of 1/200 duty
YD~
200
LP
1
2
3
199
4
200
n1
2
199
3
200
IL
1
~ ____ ~ ____ ~
LATCH
X
DATA __~__~
___L--L~L--
L
ffi
LP
Jl
XSCL
lLSlILIL---~--JlJLJlSl
DO-D3
20. X 1
.
DIOCX
WRITE
X
Flame 0
462
Line 2
X
Line 3
X
READ
Line 2
c:
~
X
Flame 0
Line 4
READ
Line 3
x=
C
SED1570
•
•
SELF-REFRESH FUNCTION
Setting Self-Refresh Mode
The self-refresh mode functions as follows:
If the displayed contents do not change, there is no transfer of the display data from the display controller to
the SED1570. The SED1570 automatically detects this and power-down is displayed.
The SED1570 is set to the self-refresh mode by maintaining the shift clock (XSCLK) in the "L" level for 1
horizontal display period (LP signal cycle) after the row data for 1 line has been input. The SED1570 checks
the mode (whether or not the mode is changed to the self-refresh mode) every 1 horizontal display period.
During 1 horizontal display period in which XSCL stops working, the display data is not written into the
SED1570 display RAM.
To stop XSCL, terminate display data (DO - D3) transfer from the display controller (because of the power
down), and set XSCL to "H" or "L". At this time, the display control must periodically send the LP, YD, and
FR signals to the SED1570 the same way as when data is transferred. The SED1570 inputs these signals,
reads the display data periodically from the internal display RAM and refreshes the display.
The display-off function is available in the self-refresh mode.
•
Cancelling Self-Refresh Mode
The self-refresh mode is cancelled as follows:
The display controller inputs the shift clock (XSCL) into the SED1570 for one horizontal display period or
longer. This should be down with the trailing edge of the LP signal and in the data transfer timing. After the
mode is cancelled, the line data, which has been sent in the horizontal display period, is written in the display
RAM at the time of the next trailing edge of the LP signal.
If the SED1570s are connected in cascade format, the self-refresh modes of all SED1570s are not
cancelledunless the appropriate number of the XSCL clocks for the cascaded SED1570s are entered.
463
I
SED1570
•
•
LCD DRIVER POWER SUPPLY
Generating LCD Drive Voltages
To obtain individual voltage levels for LCD driver, register-split the potential between V5 - Voo and drive the
LCD with the voltage follower using the operation amplifier. When using an operation amplifier,
and Voo
are separated.
va
va
However, if the potential of
is lower than Voo potential and the potential difference increases, the LCD
within the range between OV and 2.5V. If an
driver capability decreases. To avoid this, set Voo and
operation amplifier is not used, connect
and Voo.
va
va
If there are direct resistors on the V5 (Voo) power line, voltage falls in V5 (VOD) at the LSI power pins. This
V2 ;:: V3 ;:: V5 ;:: VEE)
is caused by 15 at the time of signal change. As a result, the relationship (VOD ;::
for intermediate potential of LCD cannot be maintained and the LSI may be damaged.
va ;::
To insert a protective resistor, the voltage must be stabilized according to the capacity.
GND
13
-14
Vss
GNDI------~~--------------~----~--~------..
15
12
t
t1, t3 0
t2, t4 0
t
POWER
ON
•
t
POWER
OFF
System Power-Up
This LSI has high-LCD drive voltage. As a result, if the logic power is being floated and high voltage is applied
in the LCD driver, the LSI may be damaged because of the excess current.
Until the LCD drive voltage is stabilized, use the display off function (DOFF) to set the potential of the LCD
level.
drive output to
va
Follow the sequence given below when turning the power on/off.
To turn on the power:
-
Turn on the logic power.
~
Turn the LCD driver on.
(or turn them on simultaneously)
To turn off the power:
-
Turn off the LCD driver.
~
Turn off the logic power.
(or turn them off simultaneously)
To avoid excess current, insert the high-speed fuse in series with the LCD power. Select the appropriate value
for a protective resistor according to the capacity of an LCD cell.
464
SED1570
•
•
EXAMPLE OF APPLICATION
Constitution of LCD
SHL= [L]
YD
YSCL
SHL
FR
V5
V4
V3
V2
V1
VO
,~DI01 ~~
; t---Ei ~
I. D"" ~ 1-(
640 x 200 DOT
t---- ~t\
~o
Ei
L1J
'-1--f-I---
rJ)
DI02
Fv
1/200 DUTY
<80~
SHL= [H]
Vss
LP
SED1570
EI01
EI02
CD
~80~
,I
J
®
llll
llll
DOFF
LP
---
XSCL
---
DO-D3
--
-
465
~80~
SED1570 ~
lEI01
EI02
SED1570
EI01
EIOj
®
J
J 11
I
SED1570
•
PAD DIMENSIONS
31
00000 0
32
0 0 0
0 0
0 0
0 0
0
0
DOD 0
0
0 0
0 0 0 0
0 0
0
o
o 99
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
49
o
o
o
g D1570DOAO
DOD 0 0
0 0
0 0
0
0 0 0
0
DOD 0
0 0
0 0
0 0
0 0 0 0 0
0 0
81
50
Chip size .................... 8.04 mm x 3.51 mm
Pad center size .......... 100
~m
x 100
~m
Pad pitch .................... 170 ~m (min.)
Chip thickness ............ 400
466
~m
± 25
~m
(AI pad)
o 82
SED1570
•
•
PAD COORDINATES
SED1570F Pad Center Coordinates
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Pin
Name
X75
X76
X77
X78
X79
X80
EI02
VDD
SHL
DO
01
02
03
YO
VEE
V5
V3
V2
VO
FR
XSCL
DOFF
LP
VSS
EI01
X1
X2
X3
X4
X5
X6
X7
X8
X
y
3640
3432
3224
3016
2808
2600
2340
2080
1820
1560
1300
1040
780
520
260
0
-260
-520
-780
-1040
-1300
-1560
-1820
-2080
-2340
-2600
-2808
-3016
-3224
-3432
-3640
-3862
-3862
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1595
1452
1282
Pad
No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Pin
Name
X9
X10
X11
X12
X13
X14
X15
X16
X17
X18
X19
X20
X21
X22
X23
X24
X25
X26
X27
X28
X29
X30
X31
X32
X33
X34
X35
X36
X37
X38
X39
X40
X41
X
y
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3862
-3641
-3406
-3171
-2936
-2701
-2466
-2231
-1996
-1761
-1526
-1291
-1056
-821
-586
-351
-116
119
1112
942
772
602
432
262
92
-78
-248
-418
-588
-758
-928
-1098
-1268
-1438
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
467
Pad
No.
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Pin
Name
X42
X43
X44
X45
X46
X47
X48
X49
X50
X51
X52
X53
X54
X55
X56
X57
X58
X59
X60
X61
X62
X63
X64
X65
X66
X67
X68
X69
X70
X71
X72
X73
X74
X
y
354
589
824
1059
1294
1530
1765
2000
2235
2470
2705
2940
3175
3410
3645
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
3862
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1595
-1438
-1268
-1098
-928
-758
-588
-418
-248
-78
92
262
432
602
772
942
1112
1282
1452
I
THIS PAGE INTENTIONALLY BLANK
468
CMOS BO-SEGMENT LCD DRIVER
• 80-bit High Voltage Output
.1/100 to 11300 Display Duty
•
DESCRIPTION
The SED1600 is a dot matrix LCD segment (column) driver for driving a high-capacity LCD panel at duty
cycles higher than 1/100 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1600, the LCD driving voltage, VO, is isolated from the VDD supply. This provides the
ability to adjust the offset bias independently of VDD. These unique features allow the SED1600 to interface
with a variety of LCD panels. The SED1600 does not require a controller to output an enable signal to
implement daisy chain technology. This provides for easy interfacing with the LCD controllers such as the
SED1330, SED1351, SED1335, orthe SED1341.
The SED1600 is used in conjunction with the SED1610 (86-row driver), SED1630 (68-bit row driver),
SED1631 (1 OO-row driver), SED1632 (86-bit row driver), SED1633 (1 OO-bit row driver), and SED1634 (100bit driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• Daisy chain enable support
• 80-bit segment (column) driver
• Selectable output shift direction
• High-speed 4-bit data bus with enable chain technology
• No enable signal by controller is required
• Duty cycle ............................... 1/100 to 1/300
• Supply voltage ........................ 5.0V
• Shift clock frequency .............. 6MHz max
• Package ..... QFP5-1 00 pin (FAA)
DIE: AI pad chip (DAA)
Au bump (DAB)
• Wide range of LCD voltage .... -12 to -28V
• Ability to adjust offset bias of the LCD source from
VDD
•
SYSTEM BLOCK DIAGRAM
DO- D3
XSCL
LCD
CONTR
LP,FR
-"
YSCL
-
YD
I
j
SED1600
(1 )
~~
I DRIVER
ROW .. ~
.
•
I
I
•
•
---------
n*80 SEG
DUTY: 11100 - 1/300
100-300
469
I
I
SED1600
(n)
~~
± 10%
I
SED1600
•
BLOCK DIAGRAM
O~'"
ClClCl
WWW
(/J(/H/J
VDD
VSS
VO
LCD Driver
SO bit
V2
V3
V5
FR
LP
DO
01
02
03
SHL
EI01
EI02
XSCL
•
PINOUT
EI02
DO
01
02
~g
* [ NC
NC
NC
VDD
Vss
SED1600
VO
V2
V3
V5
SHL
XSCL
LP
FR
EI01
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
• NC: No Connection
470
SED1600
•
PIN DESCRIPTION
Pin Name
1/0
SEGO to SEG79
0
LCD driving segment (column) outputs
Each output changes at the falling edge of LP.
DO TO 03
I
Display data inputs.
XSCL
I
Shift clock of display data (falling edge trigger).
LP
I
Latch pulse of display data (falling edge trigger).
E101, EI02
1/0
SHL
I
Function
Enable 1/0, which is controlled by SHL input. Output is reset by LP, and
automatically falls when 80 bits of data are taken in.
Shift direction selection and EIO pin I/O control.
When data (a, b, c, d) (e, f, g, h) ...... (w, x, y, z) are input to pins (03, 02, 01,
DO) respectively, the following relation is established between the data and
segment outputs:
SEG
SHL
EIO
79 78 77 76 75 74 73 72 ...... 3
•
•
2
1
0
1
Output
Input
Input
Output
L
a
b
c
d
e
f
g
h ...... w
x
y
z
H
z
y
x
w
v
u
t
s ...... d
c
b
a
FR
I
Vaa, Vss
Power
Supplies
Logic circuit power.
Vaa: 0 V (GND)
Vss: -5.0 V
VO, V2, V3, V5
Power
Supplies
LCD driving power.
V5: -12 to -28 V
Vaa :?: VO :?: V2 > V3 :?: V5
I
AC signal of LCD driving outputs.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
2
(Vaa
Symbol
Ratings
Supply voltage (1)
Vss
-7.0 to +0.3
V
Supply voltage (2)
V5
-30.0 to +0.3
V
Supply voltage (2)
=OV)
Unit
VO, V2, V3*
V5 -0.3 to +0.3
V
Input voltage (1)
VI
Vss -0.3 to +0.3
V
Output voltage (1)
Vo
Vss -0.3 to +0.3
V
Output current (1)
10
20
mA
Output current (2)
10SEG
20
rnA
Allowable power dissipation
Pa
300
mW
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-65 to +150
°C
Soldering temperature, time
Tsol
260°C, 10 sec (at lead)
* YO, V2 and V3 must always satisfy the condition Voo ;" VO ;" V2 ;" V3 ;" V5.
471
-
SED1600
•
(Unless otherwise specified, Voo = VO = OV,
Vss = -5.0 V ± 10%, Ta = -20 to 85°C)
DC Electrical Characteristics
Parameter
Operating voltage
Recommended op. voltage
Minimum operating voltage
Symbol
Condition
Vss
Pin
Min
Typ
Vss
-5.5
-5.0
V5
V5
-28.0
Operating voltage
-
Recommended value
VO
-2.5
Operating voltage
V2
Recommended value
V2
3/9·V5
Recommended value
Operating voltage
V3
"H" input voltage
VIH
"L" input voltage
VIL
"H" output voltage
VOH
10H =-0.6 mA
"L" output voltage
VOL
10L = 0.6 mA
Input leakage current
Stand-by current
V3
V5
EI01, E102, 0.2Vss
XSCL, LP,
0010 03,
FR,SHL
III
ILiIO
VSS 0;;, VI 0;;, 0 V
loos
V5 = -12.0 to -28,0 V
VIH = Voo, VIL = Vss
RSEG
I~VoNI = 0.5V V5 -14.0V
-8.0V
Current dissipation (1)
ISSOI
Current dissipation (2)
Iss02
Input capacitance
CI
Vss = -5.0 V, VIH = VDD
VIL = Vss, fxscL =1.92 MHz
fLP = 12 kHz, Frame periDd
= 60 Hz; Input data:
Inverted bit by bit, No-load
Vss = -5.0 V, V2 = -4.0 V
V3=-16.0V, V5=-20.0V
All other conditions are
same as ISS01
CliO
472
V
V
-8.0
-
0
V
VO
V
-
6/9·V5
V
-
-
V
-0.4
0010 03, LP
XSCL, SHL, FA
E101, EI02
-
-
Voo
-
2.0
4,5
3,0
8.0
Vss
-
120
500
!lA
V5
-
20
100
IlA
SEGO to
SEG79
00 to 03, LP
XSCL, SHL, FA
E101, EI02
Ta = 25°C
-4.5
-12.0
-
-20.0V
Output resistance
Unit
-
E101, EI02
VSS 0;;, VI 0;;, 0 V
-
Max
0.8Vss
-
V
V
Vss+0.4
V
2.0
IlA
5.0
IlA
-
25
IlA
1.5
3.5
kQ
-
-
8.0
pF
-
-
15.0
pF
SED1600
•
AC Electrical Characteristics
(Vss = -5.0 V ±1 0%, T a = -20 to 85°C)
Parameter
XSCL period
Conditions
Symbol
tr,
tcCL
tt s; 10 ns
Min
Typ
Max
Unit
166
-
-
ns
XSCL "H" pulse width
tWCLH
70
-
-
ns
XSCL "L" pulse width
tWCLL
70
-
-
ns
tos
60
-
-
ns
ns
Data setup time
Data hold time
tOH
40
-
XSCL-rise to LP-rise time
tLD
0
-
XSCL-fall to LP-fall time
tSL
70
-
LP-rise to XSCL-rise time
tLS
70
-
LP-fall to XSCL-fall time
tLH
70
-
LP "H" pulse width
tWLPH
70
-
ns
ns
ns
ns
LP "L" pulse width
tWLPL
230
-
Allowable FR delay time
tOFR
-500
-
500
ns
Enable "H" setup time
tsuEIH
40
-
-
ns
Enable "H" hold time
thEIH
0
tsuEIL
0
-
-
ns
Enable "L" setup time
ns
ns
ns
Enable "L" hold time
thEIL
0
-
-
ns
Input signal rise time
tr
-
50'
ns
Input signal fall time
tl
-
-
50'
ns
tr and tf are provided to prevent a malfunction which may occur when noise is mixed with a slowdown signal. To assure high-speed XSCL, both tr and tf must satisfy the following relation:
* Note: The specifications for
t t
r, f<
tcCl - (twClH + tWCll)
2
473
I
SED1600
• Timing Chart
o Input Timing
~~--------------
FR
LP
XSCL
00 to 03
EIO output CD
EIO output
®
~
/
\~.--------------~
CDthrough
\'---
® each show a cascade number of the driver.
V 1H =0.2 Vss
V1L =0.8 Vss
FR
LP
XSCL
00 to 03
EI01
EI02
474
SED1600
o Output Timing
FR
V 1H = 0.2 Vss
V 1L = 0.8 Vss
LP
XSCL
EI01
EI02
Vn-Q.5V
Vn+ .5V
Vn =
V2, V3, V5
SEG output
va,
(Vss = -5.0 V ±1 0%, T a = -20 to 85°C)
Parameter
Conditions
Min
Typ
Max
Unit
(LP-rise to disable) time
tpdEOLLP
Symbol
XSCL= "L"
I
-
70
ns
(XSCL-fall to disable) time
tpdEOLCL
LP="H"
I
70
ns
(XSCL-fall to enable) time
tpdEOHCL
-
CL=15pF
-
(LP-fall to SEG output) time
tpdSLP
V5 = -12.0 to -28.0 V
-
(FR to SEG output) delay time
tpdSFR
CL = 100 pF
-
475
100
ns
4.5
Ils
4.5
JlS
I
SED1600
•
EXAMPLE OF APPLICATION (SE01600)
(for 200 x 640 DOT MATRIX LCD)
----------------------,
LP - - - - ! - - - - - , -__I
YD
~
Ei
w
(J)
0
Vss
Vss
200 x 640 DOT MATRIX
LCD PANEL
Voo
vo
gj
Ei
W
!!l.
a:
w
...J
V1
V2
V3
...J
0
a:
V4
I-
z
0
V5
U
VSSH
22ll
.. _----------,
WF
.
I
I
---~---r--------~+_--+_-4_r--_r
XOOroXD3--~---~------+--~~--~-+---4_
XSCL
----------------------~
Note:
• Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (O.01IlF) near pins Vss and V5 of each LSI
for noise protection.
476
SED1600
•
•
PAD LAYOUT I PAD COORDINATION
SED1600DAA (AL PAD)
80
85
90
95
100
75
70
65
60
Lx
1
10
5
15
20
Chip Specification
•
55
00000000000000000000000000000000
0
0
0
0
0
0
0
0
Y
0
0
0
0
0
0
0
0
0
0
0
0
(0,0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
016000..
00000000000000000000000000000000
25
50
45
40
35
30
Dimension (mm)
Chip size
5,59 x 3.50
Pad pitch
0.160 min.
Chip thickness
0.40±0.025
Pad surface area
0.10mm
I
SED1600DAB (AU PAD)
I-
80
153.1l!' Pitch
75
70
B5
60
55
-I
50
00000000000000000000000000000000
$-.0:: 85
~g
~o.
~fi
'IIt:t:
90
.. a.
"--
t~ 95
.... ~£
(I):t:
~o.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Y
L
(0,0)
X
01600DAB
45
.0::
~
40 ~
o:i
~
35
00000000000000000000000000000000
100 1
I.
5
10
15
153.6~
20
25
Pitch
30
.1 20/1
Chip Specification
Dimension (mm)
Chip size
5.59 x 3.50
Pad pitch
0.153 min.
Chip thickness
0.525 ±O.025
477
THIS PAGE INTENTIONALLY BLANK
478
CMOS DOT MATRIX HIGH DUTY LCD DRIVER
• 80-bit High Voltage Resistant Output
.1/100 to 11300 in Display Duty
• CMOS High Voltage Resistant Process
•
DESCRIPTION
The SED1601 is an 80-output dot matrix LCD segment (column) driver for driving a high-capacity LCD panel
at duty cycles higher than 111 00 (up to 1/300). The LSI has a wide range of the LCD driving voltages. Due
to the architecture of the SED1601, the LCD driving voltage, VO, is isolated from Voo supply. This provides
the ability to adjust the offset bias independently of Voo. These unique features allow the SED1601 to
interface with a variety of LCD panels. The SED1601 does not require a controller to output an enable signal
to implement daisy chain technology. This provides for easy interfacing with LCD controllers such as the
SED1330, SED1351, SED1335 or the SED1341.
The SED1601 is used in conjunction with the SED161 0 (86 row driver) or the SED1630 (68-bit row driver)
and SED1631 (100 row driver) or the SED1632 (a6-bit row driver), SED1633 (100-bit row driver) and
SED1634 (100-bit row driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• Daisy chain enable support
• 80-bit segment (column) driver
• No enable signal by controller is required
• High-speed a-bit bus
• Wide range of LCD voltage .... -12V to -28V
• Duty cycle ............................... 1/100 to 1/300
• Supply voltage ........................ 5.0V ± 10%
• Output shift direction pin selectable
• Package ....... QFP5-100 pin (FAA)
DIE: AI pad chip (DAA)
• Shift clock frequency .............. 6.5MHz max
• Ability to adjust offset bias of the LCD source from
Voo
•
SYSTEM BLOCK DIAGRAM
DO-D7
XSCL
LCD
CONTR
LP,FR
YSCL
f--
YD
il
SED1630~
•
SED1630~
SED1601
SED1601
SED1601
SED1601
-~~
~
~~
~~
320 SEG x 136 COM
DUTY: 1/136
479
I
SED1601
•
BLOCK DIAGRAM
~
o~'"
ClClCl - - - - - - - - - - Cl
www
w
000000
00
VDD
Vss
VO
LCD Driver
V2
BObi!
V3
V5
FA
LP
DO
Dl
D2
D3
D4
D5
D6
D7
SHL
EIOI
EI02
XSCL
•
PINOUT
EI02
00
01
02
03
04
05
06
07
Voo
Vss
VO
SED1601
LP
.~
FR
100
V2
V3
V5
SHL
XSCL
EI01
1
480
SEG49
SEG46
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG38
SEG35
SEG34
SEGSS
SEG32
SEG31
SEG30
SED1601
•
PIN DESCRIPTION
Pin Name
I/O
0
SEGO to SEG79
Function
LCD driving segment (column) outputs.
Each output changes at the falling edge of LP.
DO TO 07
I
Display data inputs.
XSCL
I
Shift clock of display data (falling edge trigger).
LP
I
E101, EI02
I/O
SHL
I
Latch pulse of display data (falling edge trigger).
Enable I/O, which is controlled by SHL input. Output is reset by LP, and
automatically falls when 80 bits of data are taken in.
Shift direction selection and EIO pin I/O control.
When data (a, b, c, d, e, f, g, h) (i, j, k, I, m, n, 0, p) ...... (s, t, u, v, w, x, y, z) are
input to pins (07, 06, 05, 04, 03, 02, 01, ~O) respectively, the following
relation is established between the data and segment outputs:
SEG
SHL
•
•
EIO
79 78 77 76 75 74 73 72 ...... 3
2
1
0
1
2
g
h ...... w
x
y
z
Output
Input
t
s ...... d
c
b
a
Intput
Output
L
a
b
c
d
e
f
H
z
y
x
w
v
u
FR
I
Voo, Vss
Power
Supplies
Logic circuit power.
Voo: 0 V (GNO)
Vss: -5.0 V
VO,V2,V3,V5
Power
Supplies
LCD driving power.
V5: -12 to -28 V
Voo ~ VO ~ V2 > V3
I
AC signal of LCD driving outputs.
~
V5
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voo =0 V)
Parameter
Symbol
Ratings
Unit
Supply voltage (1)
Vss
-7.0 to +0.3
V
Supply voltage (2)
V5
-30.0 to +0.3
V
Supply voltage (2)
VO, V2, V3*
V5 -0.3 to +0.3
V
Input voltage (1)
VI
Vss -0.3 to +0.3
V
Output voltage (1)
Vo
Vss -0.3 to +0.3
V
Output cu rrent (1)
10
20
mA
Output current (2)
10SEG
20
mA
Po
300
mW
°C
Allowable power dissipation
Operating temperature
Topr
-20 to +75
Storage temperature
Tstg
-65 to +150
Soldering temperature, time
Tsol
260°C, 10 s (at lead)
• VO, V2 and V3 must always satisfy the condition: Vee ~ VO ~ V2 ~ V3 ~ VS.
481
°C
-
SED1601
•
(Unless otherwise specified, Voo = VO = OV,
Vss = -5.0 V ± 10%, Ta = -20 to 75°C)
DC Electrical Characteristics
Pin
Min
Typ
Max
Unit
Operating voltage (1)
Parameter
Vss
Vss
-5.5
-5.0
-4.5
V
Recommended op. voltage
Minimum operating voltage
V5
V5
-28.0
-
-12.0
V
Operating voltage (2)
VO
Recommended value
VO
-2.5
Operating voltage (3)
V2
Recommended value
V2
5/9·V5
Operating voltage (4)
V3
Recommended value
"H" input voltage
VIH
"L" input voltage
VIL
"H" output voltage
VOH
"L" output voltage
VOL
10L= 0.6 mA
III
Vss:s; VI:S; 0 V
ILila
VSS:S;VI:S; OV
loos
V5 = -12.0 to -28.0 V
VIH = Voo, VIL = Vss
Input leakage current
Stand-by current
Symbol
Condition
10H =-0.6 mA
V3
V5
EIOI, E102,
XSCL, LP, 0.2Vss
001007,
FR,SHL
-0.4
E101, EI02
001007, LP
XSCL, SHL, FR
E101, EI02
Voo
RSEG
Current dissipation (1)
Issol
Current dissipation (2)
Iss02
Input capacitance
CI
Ta = 25°C
CliO
482
-
Vss+O.4
V
-
2.0
-
5.0
!lA
!lA
25
!lA
1.4
3.5
0
V
VO
V
4/9·V5
V
-
V
0.8Vss
V
-
V
1.7
4.5
2.7
8.0
VSS
-
120
500
I1A
V5
-
20
100
I1A
-
-
8.0
pF
15.0
pF
It.VoNI = O.SV V5 -14.0V SEGOto
SEG79
-8.0V
VSS = -S.O V, VIH = VDD
VIL = Vss, fxscL = 1.92 MHz
fLP = 12 kHz, Frame period
= 60 Hz; Input data:
Inverted bit by bit; No·load
Vss - -S.O V, V2 = -4.0 V
V3 =-16.0 V, VS =-20.0 V
All other conditions are
same as ISSOI
-
-
-
-20.0V
Output resistance
-
-8.0
001007, LP
XSCL, SHL, FR
E101, EI02
kQ
SED1601
•
AC Electrical Characteristics
Parameter
XSCL period
(Vss
=-5.0 V ±10%, Ta =-20 to 75°C)
Symbol
Conditions
Min
Typ
Max
Unit
tCCL
tr,tt:S;10ns
166
-
-
ns
XSCL "H" pulse width
tWCLH
70
-
-
ns
XSCL "L" pulse width
tWCLL
70
tos
60
-
ns
Data setup time
-
ns
Data hold time
tOH
40
-
tLD
0
XSCL-fall to LP-fall time
tSL
70
LP-rise to XSCL-rise time
tLS
70
-
-
ns
XSCL-rise to LP-rise time
LP-fall to XSCL-fall time
tLH
70
-
-
ns
500
ns
ns
ns
ns
LP "H" pulse width
tWLPH
70
LP "L" pulse width
tWLPL
230
Allowable FR delay time
tOFR
-500
Enable "H" setup time
tsuEIH
40
-
-
ns
Enable "H" hold time
thEIH
0
-
-
ns
Enable "L" setup time
tsuEIL
0
-
ns
ns
ns
Enable "L" hold time
thEIL
0
-
-
Input signal rise time
tr
-
-
50'
ns
Input signal fall time
tl
-
-
50'
ns
ns
• Note:
The specifications for tr and tf are provided to prevent a malfunction which may occur when noise is mixed with a slow-down
signal. To assure high-speed X8CL, both tr and tf must satisfy the following relation:
t t
r, f<
tcCL - (tWGLH + tWGLL)
2
483
I
SED1601
•
o
Timing Chart
Input Timing
==x~
FR
_______________________
LP
XSCL
DO to 07
EIO output CD
EIO output
® ----\~.--------------~/
CDthrough
\~---
® each show a cascade number of the driver.
V 1H = 0.2 Vss
V 1L = 0.8 Vss
FR
LP
XSCL
DO to 07
EI01
EI02
484
SED1601
o Output Timing
)
FR
LP
/
V 1H = 0.2 Vss
V 1L = 0.8 Vss
\
"i
XSCL
lpdEOLLP~
EI01
EI02
l.tpdEOHCL1
~tpdSLP-
i.tPdEOLC\JiOH
J
= 0.2 Vss
V oL =0.8Vss
-tpdSFR-
SEG
J Vn-Q.5V
Vn +O.5V
output
Vn = VO, V2, V3, V5
(Vss = -5.0 V ±10%, Ta = -20 to 75°C)
Parameter
(LP-rise to disable) time
Symbol
Conditions
Min
I
-
-
-
-
70
ns
-
100
ns
4.5
!1s
4.5
!1s
tpdEOLLP
XSCL= "L"
(XSCL-fall to disable) time
tpdEOLCL
LP="H"
(XSCL-fall to enable) time
tpdEOHCL
J
CL = 15 pF
(LP-fall to SEG output) time
tpdSLP
V5 = -12.0 to -28.0 V
-
(FR to SEG output) delay time
tpdSFR
CL=100pF
-
485
Typ
Max
Unit
70
ns
I
SED1601
•
EXAMPLE OF APPLICATION (SE01601)
--------1
LP
r----YSCL CD
-SHL
I
I
I
YD
- - - -
DI01
Vss
Vss
r-- SHL
a:
-'
-'
Vt
DI02
ill
0
a:
IZ
0
()
11R~
DI02
I
I
I
Rrf:
V5
I
'
-
LCD PANEL
~
0
~ -f-1~:~
iii
220*
fil
6
if>
--------1 "
WF
I
I
XSC L
XDO tDXD7
I
---------I
79
79 - f l - o
EI02CDEIOt
EI02®EIOt.
VDD
6
;. I 220
I
I
~ VssH
FR~
'---sEDi63o
Rr+
: V4
200 x 640 DOT MATRIX
0
,+--V
.c
FR 1+ '"
r----~ YSCL@
~ SHL
C. DIOt
Rp8
V3
:
'---sEDi63o
Rp8
V2
I
I
I
I
:2
I
FR~ ~
~
DI02
L. DIOt
vo
0
~
H-,J
~ YSCL®
+
VDD
(for 200 x 640 DOT MATRIX LCD)
8
---,"
()Q
SHL
Cl,)oc..CC
XO....JIJ..
--l '"
()Q
~
79-fl-o
-------
SHL
EI02®E10t.
...J r-SHL
~
()Q
U)0a...a:
UJoa..O::
XO...JLL
XCl....J1J..
-- --- ----
=====~
I
----
• Note: Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01I-lF) near pins Vss and V5 of each
LSI for noise protection.
486
SED1601
•
PAD LAYOUT (SED1601DAA)
80F
: 80
75
70
65
60
55
51F
51 :
ODDDDDDDDDDDDDDDDDDDDDDDDDDDDDDO
D
D 50
D
D
D
85
L
Y
D
D
D
D
D
90
95
D
D
D
D
B
D
D
D
D
D
X
D
B 40
(0,0)
D
D
D
D
D
D
D
100
(0,0)
D
D
D
D
D
D
D
D
D
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
,
,
: 1
1F
5
10
Chip Size
Pad Pitch
Pad Dimension
Chip Thickness
15
20
6.20mm x 4.59mm
0.18mm (MIN.)
0.1 mm x 0.1 mm
0.4mm±O.025mm
487
45
25
30 :
30F
35
I
SED1601
•
PAD COORDINATES (SED1601DAA)
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pad Name
SEGO
SEGl
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEGll
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
X
-2700
-2503
-2306
-2109
-1912
-1714
-1534
-1354
-1174
-994
--813
--833
-453
-273
-93
88
268
448
628
808
989
1169
1349
1529
1709
1907
2104
2301
2498
2695
2925
2925
2925
2925
2925
2925
2925
2925
2925
2925
Y
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-2120
-1895
-1669
-1443
-1217
-991
--811
--831
-450
-270
-90
Pad No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pad Name
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
X
2925
2925
2925
2925
2925
2925
2925
2925
2925
2925
2685
2498
2301
2104
1907
1709
1529
1349
1169
989
808
628
448
268
88
-93
-273
-453
-633
-813
-994
-1174
-1354
-1534
-1714
-1912
-2109
-2306
-2503
-2700
Y
90
270
451
631
811
991
1217
1443
1689
1896
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
2120
Pad No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pad Name
EI02
00
01
02
03
04
05
06
07
VOO
VSS
VO
V2
V3
V5
SHL
XSCL
LP
FR
EI01
X
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
-2925
y
1896
1669
1443
1217
991
811
631
451
270
90
-90
-270
-450
--831
--811
-991
-1217
-1443
-1669
-1895
·1
Pad No.
1F
30F
51F
80F
y
Pad Name
X
SEGO
-2925 -2120
SEG29
2925 -2120
SEG50
2925 2120
SEG79
-2925 2120
·1 These pads are located at the corner: Pad Nos. 1F, 30F, 51 F, and 80F. They have the same function as Pad Nos. 1,
30,51, and 80.
488
SED1606DoAlDoB
CMOS LCD SEGMENT DRIVER
•
DESCRIPTION
The SED1606 is an 80-output segment (column) driver for use in combination with an SED163S. It is provided
with high-vision measure of the LCD display and adopts high speed inable chain system for low power
operation and slim chip shape suitable for minimizing of the LCD panel. Also, low voltage operation of the
logic power source suits a wide range of applications .
•
FEATURES
•
LCD driver output number ........................................... 80
•
Ultra-slim chip
•
•
Low current consumption
Low voltage operation ................................................. -2.7V max.
•
Wide range of liquid crystal drive voltage .................... -8 to -28V
•
High speed and low power data transfer is possible by adoption of the 4-bit bus inable chain system.
Shift clock frequency:
6.SMHz (at -2.7V)
10.0MHz (at -4.SV)
•
Non-bias display off function
•
Pin selection of the output shift direction is available
•
Offset bias regulation of the liquid crystal power is possible depending on the Voo level
•
Logic system power source ......................................... -2.7 to -S.SV
•
Product shapes
489
I
SED1606DoAlDoB
•
BLOCK DIAGRAM
00----------------- 079
VO
V2
80 bit
LCD Driver
V5
i
V3
{t
Level Shifter 80 bit
t
FR
{~
LP
Latch 80 bit
Vss
{~
VDD
Data Register 80 bit
00-03
XSCL
EI01
SED1606
EI01 CD EI02
<80~
SED1606 .1
EI01 ® EI02 j
III
~80>
---
-
III
------
XSCL
SHL
DLO-3
501
1 SED1606
I EI01 ® EI02
llj I
I
THIS PAGE INTENTIONALLY BLANK
502
CMOS DOT MATRIX HIGH DUTY LCD DRIVER
• CMOS 128-Bit Segment Driver
• High Voltage Resistant Output
.1/100 to 11300 in Display Duty
• CMOS High Voltage Resistant Process
•
DESCRIPTION
The SED1620 is a 128 output dot matrix LCD segment (column) driver for driving high-capacity LCD panels
at duty cycles higher than 1/100 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1620, the LCD driving voltage VO is isolated from VDD supply. This provides the ability
to adjust the offset bias independently of VDD. These unique features allow the SED1620 to interface with a
variety of LCD panels. The SED1620 does not require a controller to output an enable Signal to implement
daisy chain technology. This provides for easy interfacing with the LCD controllers such as the SED1330,
SED1335, SED1351 orthe SED1341.
The SED1620 is used in conjunction with the SED161 0 (86 row driver) or the SED1630 (68-bit row driver)
and SED1631 (100 row driver), SED1632 (86-row driver), SED1633 (100-row driver), SED1634 (100-row
driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• Daisy chain enable support
• 128-bit segment (column) driver
• No enable signal by controller is required
• High-speed 4-bit bus
• Wide range of LCD voltage .... -12V to -28V
• Duty cycle ............................... 1/100 to 1/300
• Supply voltage ........................ 5.0V ±1 0%
• Shift clock frequency .............. 4MHz max
• Package .................................. AI pad chip (DOA)
for chip on glass
• Ability to adjust offset bias of the LCD source from
VDD
•
SYSTEM BLOCK DIAGRAM
LCD
CONTR
DO- D3
XSCL
LP,FR
YSCL
YD
f--
IJ
lSED1631~
•
ISED1631~
SED1620
SED1620
SED1620
~2~
~2~
~2~
384 SEG x 200 COM
DUTY: 1/200
503
I
SED1620
•
B.LOCK DIAGRAM
o 1 ---------
127
'. SHL ¢----tr-------,
ER
EL
Level Shifter 128 bits
LPR
LPL
Register 2
XSCLR
XSCLL
128 bits
Register 1 128 bits
DOR
DOL
D1R
D1L
D2R
D2L
D3R
D3L
FRR
FRL
~~J-----~
Vss
Voo
¢-----;~-~~6----I
Voltage Control
L -_ _ _ _ _- - - '
VO
V2
V3
V5
504
SED1620
• PIN DESCRIPTION
Pin Name
Function
LCD driving segment (column) outputs
Each output changes at the falling edge of LP
SEGO to SEG127
DOR to D3R
DOL to D3L
Display data inputs
XSCLR, XSCLL
Shift clock of display data (falling edge trigger).
LPR,LPL
Latch pulse of display data (falling edge trigger).
Enable 1/0, which is controlled by SHL input. Output is reset by LP, and automatically
falls when 128 bits of data are taken in
ER,EL
1/0 terminal configuration and register 1 shift direction select input.
DOR to DOL to
XSCLR XSCLL
D3R
D3L
SHL
SHL
LPR
LPL
ER
EL
FRR
FRL
0
I
I
0
H
0
I
0
I
0
I
0
I
L
I
0
I
0
I
0
I
0
SHL=H
1SEGO
I
- 127 1 127
126
125
124
123
...
4
3
2
1
0
I
y
x
w
v
...
e
d
c
b
a
126
125
124
123
4
3
2
1
0
b
c
d
e
...
...
v
w
x
y
z
Data
z
SHL=L
1SEGO -1271127
I
FR
I
a
AC signal of LCD driving outputs.
Logic circuit power. Voo: 0 V (GND)
Vss: -5.0 V
Voo, Vss
V1, V2, V3, V5
•
•
Data
LCD driving power. V5: -12 to -28 V
Voo ~ VO ~ V2 > V3 ~ V5
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voo = OV)
Parameter
Symbol
Ratings
Unit
Supply voltage (1)
Vss
-7.0 to +0.3
V
Supply voltage (2)
V5
-30.0 to +0.3
V
V5 -0.3 to +0.3
V
V
Supply voltage (2)
VO, V2, V3*
Input voltage (1)
VI
Vss -0.3 to +0.3
Output voltage (1)
Vo
Vss -0.3 to +0.3
V
Output current (1)
10
20
mA
Output current (2)
10SEG
Allowable power dissipation
Po
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-55 to +150
°C
• VO, V2 and V3 must always satiSfy the condition VDD ;:: VO ;:: V2 ;:: V3 ;:: V5.
505
20
mA
300
mW
I
SED1620
• DC Electrical Characteristics
(Unless otherwise specified, Voo = VO = 0 V, Vss = -S.O V
Parameter
Operating voltage (1)
Recommended op. voltage
Minimum operating voltage
Symbol
Conditions
Vss
VS
Min
Typ
Max
Unit
Vss
-S.S
-S.O
-4.S
V
-
-12.0
V
VS
-28.0
Operating voltage (2)
-
Recommended value
VO
-2.S
Operating voltage (3)
V2
Recommended value
V2
3/9·VS
Operating voltage (4)
V3
Recommended value
"H" input voltage
VIH
"L" input voltage
VIL
"H" output voltage
VOH
10H =-0.6 rnA
"L" output voltage
VOL
10L= 0.6 rnA
Input leakage current
Stand-by current
Output resistance
E101. EI02
001003. LP
III
Vss
~VI~O
V
XSCL. SHL. FR
ILila
Vss
~VI~O
V
E101, EI02
loos
VS = -12.0 to -28.0 V
VIH = Voo, VIL = Vss
RSEG
IdVoNI = 0.5V Ivsl-14.0V
Current dissipation (1)
Issol
Current dissipation (2)
Iss02
Input capacitance
V3
VS
EIOI. E102. 0.2Vss
XSCL. LP.
001003.
FR SHL
-0.4
-
CI
Vss = -S.O V, VIH = Voo,
VIL= Vss,
fxscL = 1.92 MHz.,
fLP = 12 kHz,
Frame period = 60 Hz;
Input data: Inverted bit
by bit; No-load
VSS = -5.0 V, V2 = -4.0 V
V3 = -16.0 V, V5 = -20.0 V
All other conditions are
same as ISS01
S06
-
-
0
V
VO
V
6/9·VS
V
-
V
0.8Vss
-
V
V
-
Vss+O.4
V
2.0
j.lA
-
S.O
j.lA
Voo
-
2S
j.lA
SEGOto
SEG127
-
2.0
4.S
kQ
Vss
-
180
SOO
j.lA
VS
-
80
160
j.lA
-
-
8.0
pF
1S.0
pF
001003, LP
CliO
-
-8.0
-
XSCL. SHL. FR
E101, EI02
Ta=2SoC
± 10%, Ta = -20 to 7S°C)
Pin
SED1620
•
AC Electrical Characteristics
(Vss = -5.0 V ±1 0%, Ta = -20 to 75°C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
tCCL
tr, tt ::; 10 ns
250
-
-
ns
-
ns
-
ns
-
ns
XSCLperiod
XSCL "H" pulse width
twCLH
100
XSCL "L" pulse width
twCLL
100
Data setup time
tos
80
Data hold time
tOH
60
XSCL-rise to LP-rise time
tLD
0
-
-
ns
XSCL-fall to LP-fall time
tSL
100
-
-
ns
LP-rise to XSCL-rise time
tLS
100
-
-
ns
tLH
100
-
100
-
-
ns
tWLPH
LP-fall to XSCL-fall time
LP "H" pulse width
ns
ns
LP "L" pulse width
twLPL
260
-
Allowable FR delay time
tOFR
-500
500
ns
Enable "H" setup time
tsuEIH
70
-
-
ns
Enable "H" hold time
thEIH
40
-
-
ns
Enable "L" setup time
tsuEIL
0
thEIL
0
-
ns
Enable "L" hold time
Input signal rise time
tr
Input signal fall time
tt
-
-
ns
ns
150'
ns
150'
ns
• Note: The specifications for tr and tf are provided to prevent a malfunction which may occur when noise is mixed with a slowdown signal. To assure high-speed XSCL, both tr and tt must satisfy the following relation:
t t
T,
f<
tCCL - (tWCLH + twCLL)
2
507
I
SED1620
• Timing Chart
o Input Timing
==x~
FR
_____________________
LP
XSCL
DO to 03
ER
EL outputG)
ER
~
EL output@\'--_
_ _ _ _ _ _ _ _ _-'/
\'---
G)through ® each show a cascade number of the driver.
V 1H =0.2 Vss
V1L = 0.8 Vss
FR
LP
XSCL
DO to 03
ER
EL
508
SED1620
o Output Timing
FR
V1H = 0.2Vss
V1L = 0.8 Vss
LP
XSCL
ER
EL
SEG output
(Vss = -5.0 V ±10%, T a = -20 to 75°C)
Parameter
Symbol
Conditions
(LP-rise to disable) time
tpdEOLLP
XSCL= "L"
I
(XSCL-fall to disable) time
tpdEOLCL
LP="H"
I
(XSCL-fall to enable) time
tpdEOHCL
CL = 15 pF
(LP-fall to SEG output) time
tpdSLP
V5 = -12.0 to -28.0 V
(FR to SEG output) delay time
tpdSFR
CL= 100 pF
(I/O to Oil) delay time
CL=15pF*
* Except for ER and EL
509
Min
Typ
Max
Unit
-
-
100
ns
-
100
ns
-
100
ns
4.5
l1S
4.5
115
30
l1s
I
SED1620
• EXAMPLE OF APPLICATION (SED1620DoA)
(for 200 x 640 DOT MATRIX LCD)
----------------------,
LP
------+-------.-_1
YO
1-----------I
I
I
I
I
I
Vss
Vss
-------1~,__.,_---=~
200
+
x 640 DOT MATRIX
LCD PANEL
: Voo --------,-j---..,j--.j
I
I
I
I
V1
I
: V2 ~o--+-,-hl
I
I
: V3 ---1r--+----,-j---.j
I
:V4 ---1~-+----,-j-j--.j
I
I
: V5 ---1~+-"WIr-j----'----r_+_t_------'
I
: VSSH
I
2211
.. _----------, *
WF-_ _ _,~,---t_-----~--~-~-t__r_+_~~_r
XSCL ---~--_+--------~~--_+-~r---+_
XOOtoX03-~---+------_o~--+---_+_--+--~
----------------------~
Note: • Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01 JlF) near pins
Vss and V5 of each LSI for noise protection.
510
SED1620
• PAD LAYOUT
• PAD COORDINATES
O.125mm
Opening
I
Chip name D1620DOA (Aluminum pattern)
Chip size
10.5 x 3.BBmm
Chi thickness
0.25 ±O.03mm
Pad size
0.11 x 0.11 mm (Opening)
Pad pitch
Min.0.125mm
Note: 1. NC: Not connected
2. 2 pads Voo are supplied, and should be used to reduce the
power source impedance
511
THIS PAGE INTENTIONALLY BLANK
512
SED1640
•
DESCRIPTION
The SED1640 is an 80-output dot matrix LCD segment (column) driver for driving high-capacity LCD panels
at duty cycles higherthan 1/100 (up to 1/300). The LSI has a wide range of LCD driving voltages. The offset
bias regulation of the liquid crystal power is possible depending on the VDD level. These unique features allow
the SED1640 to interface with a variety of LCD panels. The device does not require a controller to implement
an enable daisy chain technology.
The SED1640 is used in conjunction with the SED1651 (1 OO-output row driver) or the SE01635 (1 OO-bit row
driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• Daisy chain enable support
• 80-bit segment (column) driver
• Pin selection of the output shift direction
• High-speed 4-bit bus
• LCD voltage ............................ -8 to -28V
• Duty cycle ............................... 1/100 to 1/300
• Supply voltage ........................ 2.7 to 5.5V
• Unbiased display off function
• Package .................................. Slim DIE (Dos)
• Shift clock frequency .. '" ., ....... 10MHz max
I
• Ability to adjust offset bias of the LCD source from
VDD
•
SYSTEM BLOCK DIAGRAM
00- 03
XSCL
LCD
CONTR
LP,FR
YSCL
f--
YO
Ii
I SE01635
t
SE01640
SED1640
SE01640
SE01640
~~
~~
~~
~~
tJ:.QQ:"
ISE01635~
320 SEG x 200 COM
DUTY: 1/200
513
SED1640
•
BLOCK DIAGRAM
00 - - - - - - - - - - - - - 079
t
t
VO
V2
LCD Driver
80 bit
V5
i
V3
~~
80-bit Level Shift
t
FR
DSPOFF
LP
80-bit Latch
Vss
~
Voo
~
~~
EI01
I
80-bit Data Register
{r
00- 03
XSCL
~~
~
-'
~~
Enable Shift Register
514
~
SHL
~--c EI02
SED1640
•
•
BLOCK DESCRIPTION
Enable Shift Register
The enable shift register is a bi-directional shift register where the direction of the shift is selected by the SHL
input. The output of this shift register is used to store the data bus signals in the data register.
When the enable signal is in a disable state, the internal clock signal and data bus are fixed at "L", placing
the chip in power save mode.
When multiple segment drivers are used, the EIO terminals of the various drivers are cascade connected and
the EIO terminal of the first driver is connected to Voo.
The enable control circuit automatically senses and sends the enable signal when 80 bits worth of data have
been received, eliminating the need for a control signal from the control LSI.
•
Data Register
This is a register to convert the data bus signal from serial to parallel using the output of the enable shift
register. Consequently, the relationships between the serial display data and the segment output are
determined independently of the shift clock input number.
•
Latch
The latch receives the contents of the data registers when triggered by the falling edge of the LP, and outputs
them to the level shifter.
•
Level Shifter
The level shifter is a level interface circuit which converts the signal voltage level from a logic circuit level to
the LC driver voltage level.
•
LCD Driver
The LCD driver outputs the LC drive voltage.
The relationship between the data bus signal, the AC signal FR, and the segment output voltage is as follows:
DSPOFF
Data Bus Signal
H
H
L
L
-
515
FR
o Output Voltage
H
va
L
V5
H
V2
L
V3
-
va
I
SED1640
• PIN DESCRIPTION
I/O
Function
No. of Pins
00 to 079
0
LCD drive segment output; the output changes at the
LP falling edge.
80
DO to 03
I
Display data input
4
XSCL
I
Shift clock input of display data (falling edge trigger)
1
LP
I
Latch pulse input of display data (falling edge trigger)
1
Enable I/O
2
Pin Name
EI01
I/O
EI02
The terminals are set to the input or output according to
the SHL input signal level. The output is reset by LP
input. When the 80-bit data is read, the signal automatically goes high.
I
SHL
Used for shift direction selection and I/O control output
of EIO terminal.
1
If data sets (a, b, c, d) (e, f, g, h) ... (w, x, y, z) are entered
in this sequence in terminals (03, 02, 01, ~O), the data
and segment output are processed as follows:
SHL
Output
EIO
79 78 77
1
a
EI01
L
a
b
y
z
Output
Input
H
z
y
b
a
Input
Output
... 2
c ... x
x ... c
EI02
Note: The relationship between the data and segment
output is determined regardless of the number of
shift clocks.
AC conversion signal input of LCD drive output
1
Voo, Vss
Power supply
Logic power supply Voo : OV, Vss: -2.7 to -5.5Vdc
3
VO, V2,V3,V5
Power supply
Power supply for LCD drive circuit
Voo:OV
V5: -8 to -28Vdc
Voo ~ VO ~ V2 ~ 6/9 V5
3/9 V5 ~ V3 ~ V5
*1
8
Forced blank input
1
FR
I
OSPOFF
I
When the signal level is low, the output is forcibly set to
VOlevel.
Note: if this function is used, the SE01631 cannot be
used as a pair.
*1. A pair of
va to V5 must always be connected to their dedicated LCD power supplies.
516
Total: 107
SED1640
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Power voltage (1)
Vss
-7.0 to +0.3
V
Power voltage (2)
V5
-30.0 to +0.3
V
Power voltage (3)
YO, V2, V3
V5 - 0.3 to Voo + 0.3
V
Input voltage
VI
Vss - 0.3 to Voo + 0.3
V
Output voltage
VO
Vss - 0.3 to Voo + 0.3
V
101
20
mA
Operating temperature
EIO output current
TOPR
-40 to +85
Storage temperature 1
TSTG1
-65 to +150
Storage temperature 2
TSTG2
-55 to +100
°C
°C
°C
Notes:
1. All voltages are based on Voo =
av.
2. Storage temperature 1 defines the storage temperature of the separate chip, and storage temperature 2 defines the TAB
mounted chip.
3. The
va, V2 and V4 voltages must always satisfy the following:
Voo ;:, va ;:, C2 ;:, C3 ;:, V5
VDD
-5V
VO
VSS-_.L--
V2
-28V
V3
V5
4. If the logic power supply is floating or if it exceeds Vss = -2.6Vdc when the LCD drive is powered, the LSI may be destroyed
permanently. Care must be taken especially when the system power supply is turned on or off.
517
I
SED1640
•
DC Characteristics
VDD = VO = OV, VSS = -5.0 Vdc ± 10%, Ta = -40 to +85°C unless otherwise specified.
Parameter
Symbol
Conditions
Pin Name
Min
Typ
Max
Unit
Vss
-5.5
-5.0
-2.7
V
V5
-28.0
-
-12.0
V
-
-
-8.0
V
VDD
V
-
V
V5
-
6/9 x V5
V
0.2 xVss
-
-
V
-
0.8 x Vss
V
-
-
Vss+0.4
V
-
-
2.0
!!A
Power voltage 1
Vss
Recommended
operating voltage
V5
Vss = -2.7 to -5.5Vdc
Operation voltage
V5
Function
V5
Power vOltage 2
VO
Recommended value
VO
VDD - 2.5
Power voltage 3
V2
Recommended value
V2
3/9 x V5
Power voltage 4
V3
Recommended value
V3
High-level input current
VIH
E101, E102,
FR, DOtoD3,
XSCL, SHL,
LP, DSPOFF
Vss = -2.7 to -5.5Vdc
Low-level input current
VIL
High-level output current
VOH
Low-level output voltage
VOL
Vss = 2.71 10H = 0.6mA
to 5.5V 1 10L= 0.6mA
E101, EI02
VDD - 0.4
-
V
Input leakage current
Iu
Vss ::; VIN ::; VDD
00 to 03, LP.
FR. XSCL.
SHL. OSPOFF
InpuVoutput leakage
current
IUlo
Vss ::; VIN ::; VDD
E101, EI02
-
-
5.0
!!A
Static current
Iss
V5 = -28.0 to -14.0Vdc
VIH = VDD, VIL = Vss
Vss
-
-
25
!!A
RSEG
!!.VON = 0.5, V5 = -20.0V, V3 =
13115xV5, V2=2115xV5, VO=
00 to 079
-
1.5
2.5
KQ
00 to 0159
-
-
90
Q
Vss = -5.0Vdc, VIH =
VDD, VIL = Vss, fxscL =
2.69MHz, fLP =
16.8KHz, fFR = 70Hz,
Input data: Stripe
display, no load
Vss
-
0.10
0.2
mA
Vss = -3.0Vdc, other
conditions as above
Vss
-
0.07
0.15
mA
V5
-
0.02
0.05
mA
DO to 03, LP,
FR,XSCL,SHL,
OSPOFF
-
-
8
pF
E101, EI02
-
-
15
pF
Output
resistance
Deviation in chip
ON resistance
Operating current (1)
t.RsEG
Iss
t.VON = 0.5
VO = +36.0V, 1/24
Operating current (2)
15
VO = O.OV, Vss = -5.0V,
V3 = -18.6Vdc, V2 =9.3Vdc, V5 = -28.0Vdc,
others as for Iss
Input capacitance
CI
Freq. = 1MHz, Ta
separate chip
InpuVoutput capacitance
=25°C
CliO
518
SED1640
•
o
AC Characteristics
Input Timing Characteristics
FR
tOF
LP
XSCL
00-03
EI01,2
(IN)
Vss = -5.0V ± 0.5V, Ta = -40 to 85°C
Parameter
XSCL cycle time
Symbol
Conditions
Min
40
XSCL high-level pulse width
twCH
30
XSCL low-level pulse width
twCl
30
Data setup time
tDS
30
Data hold time
tDH
20
XSCL to LP rise time
tlD
0
tlH
40
*3
Unit
ns
100
LP to XSCL fall time
Max
-
te
ns
ns
ns
ns
ns
ns
LP high-level pulse width
twlH
FR delay allowance time
tDF
-900
+900
ns
EIO setup time
tSUE
35
-
ns
ns
Vss = -4.5 to -2.7V, Ta = -40 to 85°C
Parameter
XSCL cycle time
Symbol
Conditions
tc
Min
153
-
ns
Vss=-3.0V
*2
133
-
ns
ns
Vss = -2.7V
*3
75
Vss=-3.0V
*3
65
-
-900
+900
ns
Vss = -2.7V
50
ns
Vss=-3.0V
40
-
twCH
50
XSCL low-level pulse width
twCl
50
Data setup time
tDS
50
Data hold time
tDH
30
XSCL to LP rise time
tlD
0
tlH
LP high-level pulse width
twlH
FR delay allowance time
tDF
EIO setup time
tSUE
*1. Equivalent to 6.5MHz
*2. Equivalent to 7.5MHz
Unit
*1
XSCL high-level pulse width
LP to XSCL fall time
Max
Vss=-2.7V
Vss=-2.7V
75
Vss=-3.0V
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
*3. ''twLH" defines the time when LP is high and XSCL
is low.
519
I
SED1640
•
AC Characteristics
o Output Timing Characteristics
FR _ _ _ _ _ _ _ _ _ _ _ _
LP
~
----------->r
XSCL
EI01,2
(OUT)
SEG _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~~
_ _ __
VSS = -5.0V ± 0.5V, V5 = -12.0 to -28.0V
Parameter
Conditions
Min
Max
Unit
CL = 15pF (EIO)
-
90
ns
Symbol
EIO reset time
tER
EIO output delay time
tDCL
Delay time from LP to segment output
tLSD
Delay time from FR to segment output
tFRSD
CL = 100pF
(D ... n)
-
55
ns
20D
ns
400
ns
Vss = -4.5 to -2.7V, V5 = -12.D to -28.DV
Parameter
EIO reset time
EIO output delay time
Conditions
Symbol
tER
tDCL
Delay time from LP to segment output
tLSD
Delay time from FR to segment output
tFRSD
CL=
15pF
(EIO)
Vss=-2.7V
Vss =-2.7V
CL = 1DDpF
(O ... n)
52D
Min
Max
Unit
-
15D
ns
-
95
ns
85
ns
4DO
ns
800
ns
SED1640
•
Timing Diagram (assuming 1/200 duty) (This diagram is provided only as a reference)
200
1
2
3
4
1
2
3
199
X
~
X
200
1
LP~ ___________ ~ ___________ ~
LATCH
DATA
~
~
~
X X X
~
X X X
--fl
LP
n<-·_ _
XSCL~----~----~----~
,
DO - D3
I
20
EIOG)
~
1
•
~
2
~
~
3
CD
2?
I
X
1
--.-Ji• •
~I-_ _ _ _ _ _
~
~
2
®
3 ----
~
2?
:
~
1
~
2
~
3
----=:~==:=::;:===~=
•
~1-----------------4
EIO® ~I---------------------------'f----EIO®
(1) to (n) indicate driver cascade numbers.
*
LP
LATCH
DATA
FR
For high-speed data transmission, it is necessary to lengthen the XSCL period in the LP
pulse insertion timing to ensure the specified values of LP ~ XSCL (tLH).
~)
~)
H
I
~
H
L »)
DSPOFF
VO
V2
V3
V5
521
I
L
I
SED1640
•
PAD LAYOUT
100
~
75
60
50
45
40
95
90
85
80
70
85
55
000000000000000000000000000000000000000000000000000000000000
105
§
(0,0)
B 000 0
5
ODD
ODD
0
0
o
0
0
0
0
0
15
10
~ 35
o
+
B
0 0 0
20
0
000
~
30
25
• Chip size "'"'''''''''''''''''' 11 ,59 x 1.40 mm
• Pad pitch """""".,,"""" 1051lm (Min)
• Chip thickness """"""" 625 Ilm ± 251lm
(1) SED1640DoB Au bump specifications (reference)
Bump size A""""""""""""". 106 Ilm x 80 Ilm x 4 Ilm """"""""".
Bump size B """"""""""""". 861lm x 91 Ilm x 41lm """""""""".
Bump size C """""""",,"",," 86 Ilm x 681lm x 4 Ilm """""""""".
Bump size D """""" .... " .. ,, .... 82 Ilm x 741lm x 41lm .... " .... " ...... ".
Bump height A to D .. " .. " .. ,,"" 22.5 ± 5.51lm ........ " .. " .. " .... "" .. " ......
522
(Pad
(Pad
(Pad
(Pad
(Pad
Nos.
Nos.
Nos.
Nos.
Nos.
2 to 26)
1,27,37,98)
28 to 36, 99 to 107)
38 to 97)
1 to 107)
SED1640
•
PAD COORDINATES
Pad
No,
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Pin
Name
VO
V2
V3
V5
Vss
Dummy
SHL
Dummy
Dummy
VDD
DSPOFF
FR
LP
XSCL
DO
D1
D2
Dummy
D3
Dummy
Vss
V5
V3
V2
VO
EI01
00
01
02
03
04
05
06
07
08
09
010
011
012
013
X
y
-5345
-5164
-4984
-4594
-4091
-3839
-3587
-3065
-2828
-2590
-2086
-1583
-1079
1079
1583
2086
2590
3065
3587
3839
4091
4594
4984
5164
5345
5644
5644
5644
5644
5644
5644
5644
5644
5644
5644
5644
5269
5090
4912
4733
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-541
-544
-426
-320
-215
-109
-4
102
207
313
418
546
553
553
553
553
Pad
No,
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Pin
Name
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
X
y
4554
4376
4197
4019
3840
3661
3483
3304
3126
2947
2768
2590
2411
2233
2054
1875
1697
1518
1340
1161
982
804
625
447
268
89
-89
-268
-447
-625
-804
-982
-1161
-1340
-1518
-1697
-1875
-2054
-2233
-2411
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
523
Pad
No,
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
1
Pin
Name
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
EI02
X
y
-2590
-2768
-2947
-3126
-3304
-3483
-3661
-3840
-4019
-4197
-4376
-4554
-4733
-4912
-5090
-5269
-5644
-5644
-5644
-5644
-5644
-5644
-5644
-5644
-5644
-5644
-5644
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
553
546
418
313
207
102
-4
-109
-215
-320
-426
-544
I
THIS PAGE INTENTIONALLY BLANK
524
SED1648
LCD SEGMENT DRIVER
•
DESCRIPTION
The SED1648 is an 80-output dot matrix LCD segment (column) driver for driving high-capacity LCD panels
at duty cycles higher than 1/100 (up to 1/300). The LSI has a wide range of the LCD driving voltages. The
offset bias regulation of the liquid crystal power is possible depending on the VDD level. These unique features
allow the SED1648 to interface with a variety of LCD panels. The device does not require a controller to
implement an enable daisy chain technology.
The SED1648 is used in conjunction with the SED1651 (100-output row driver) orthe SED1635 (100-bit row
driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• Daisy chain enable support
• 80-bit segment (column) driver
• Pin selection of the output shift direction
• High-speed 4-bit bus
• LCD voltage ..................................... -8 to -28V
• Duty cycle .................................. 1/100 to 1/300
• Supply voltage ................................. 2.7 to 5.5V
• Shift clock frequency .................... 10 MHz max
• Package .......................... AI pad slim DIE (DOA)
• Ability to adjust offset bias of the LCD source
relative to VDD
•
SYSTEM BLOCK DIAGRAM
DO - 03
XSCL
LCD
CONTR
LP,FR
YSCL
r----YO
I
SED1648
I SED1651
•
I
~
~
I SED1651 !
100
'I
I
~~
SED1648
.~~
160 X 200 dots
DUTY: 1/200
v~
525
I
SED1648
•
BLOCK DIAGRAM
00
079
- -- -- --- -- - - ---- -
va
~
...-r
LCD Driver
80 bits
V5
~V3
1r
-..
Vss
V2
VDD ~
Level Shifter
80 bits
0
FR
DSPOFF v
Latch
80 bits
LP
ir
Data Register
80 bits
03-0a
XSC L -/
EIO 1
...-
ir
L.-.
T
Enable Shift Register
526
~
SHL
;., EI02
SED1648
•
•
BLOCK DESCRIPTION
Enable Shift Register
The enable shift register is a bidirectional shift register where the direction of the shift is selected by the SHL
input. The output of this shift register is used to store the data bus signals in the data register.
When the enable signal is in a disable state, the internal clock signal and data bus are fixed at "L", placing
the chip in power save mode.
When multiple segment drivers are used, the EIO terminals of the various drivers are cascade connected and
the EIO terminal of the first driver is connected to VDD.
The enable control circuit automatically senses when 80 bits worth of data have been received, and sends
the enable signal, thus eliminating the need for a control signal from the control LSI.
•
Data Register
This is a register to convert the data bus signal from serial to parallel using the output of the enable shift
register. Consequently, the relationships between the serial display data and the segment output is
determined independently of the shift clock input number.
•
Latch
The latch receives the contents of the data registers when triggered by the falling edge of the LP, and outputs
them to the level shifter.
•
Level Shifter
The level shifter is a level interface circuit which converts the signal voltage level from a logic circuit level to
the LC driver voltage level.
•
LCD Driver
The LCD driver outputs the LC drive Voltage.
The relationship between the data bus signal, the AC signal FR, and the segment output voltage is as follows:
DSPOFF
Data
Bus Signal
H
H
L
L
-
FR
Voltage
o Output
H
va
L
V5
H
V2
L
V3
-
va
527
I
SED1648
•
PIN DESCRIPTION
No. of
Pins
Pin Name
1/0
00 to 079
a
Segment (column) output to drive LC.
Output transition occurs on falling edge of LP.
80
DO to 03
I
I
I
1/0
Display data input.
4
XSCL
LP
EI01
EI02
SHL
Function
Display data shift clock input (triggers on falling edge)
1
Display data latch pulse input (triggers.on falling edge)
1
Enable 1/0
2
This is set to input or output depending on the level of the SHL input. The
output is reset by the LP input, and once the 80-bit data reception is complete,
the terminals automatically rise to "H".
I
Shift direction select and EIO terminal 1/0 control input.
1
When the data has been input to terminals (03, 02, ... , DO) in the order (a3,
a2, a1, aO) (b3, b2, b1, bO) ... (t3, t2, t1, to), the relationship between the data
and the segment output is as shown in the table below:
SHL
o Output
79
78
77
L
a3
H
to
a2
t1
a1
t2
Note:
...
...
...
2
t2
a1
1
t1
a2
0
to
a3
EIO
1
2
0
I
I
0
The relationship between the data and the segment output is
independent of the shift clock number.
FR
I
LC drive output AC signal input
VDD, Vss
Power
Power source for logic: VDD : OV
VO, V2,
V3,V5
Power
LC drive circuit power:
VDD
OV
V5
-8 to -28V
VDD ~ VO ~ V2 ~ 6/9 x V5
3/9 x V5 ~ V3 ~ V5
DSPOFF
I
1
Vss : -2.7 to -5.5V
4
8
*1
1
Forced blank input.
"L" level outputs are forced to the VO level.
Total 107 (of which 5 are NC)
Note:
*1. The pairs VO-V5 must each be attached to the LCD power source.
528
SED1648
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Power voltage (1)
Parameter
Vss
-7.0 to +0.3
Unit
V
Power voltage (2)
V5
-30.0 to +0.3
V
Power voltage (3)
V
VO,V2,V3
V5 - 0.3 to VDD + 0.3
Input voltage
VI
Vss - 0.3 to VDD + 0.3
V
Output voltage
VO
Vss - 0.3 to VDD + 0.3
V
10
20
mA
Operating temperature
EIO output current
TOPR
-40 to +85
°C
Storage temperature 1
TSTG1
-65 to +150
°C
Notes:
1. All voltages are given relative to Voo
= OV.
2. Storage temperature 1 is the recommendation for the chip itself.
3. Ensure that the relationship between
va, V2 and V3 is always as follows: Voo ;::: va ;: : V2 ;::: V3 ;::: V5
System Side
VCC
_. Voo , , - - - . . , - - - - - - i
GND
-5V
I
-5V
Voo
VO
,
~---VSS--
V2
-28V
V3
V5
4. The LSI may be permanently damaged if the logic system power is floating or Vss is less than or equal to -2.6V when
power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning
the power on and off.
529
I
SED1648
•
Unless otherwise specified, Voo = VO = OV,
Vss =-5.0V ± 10%, Ta =-40 10 85°C
DC Electrical Characteristics
Parameter
Symbol
Conditions
Applicable Pins
Min
Typ
Max
Unit
Vss
-S.S
-S.O
-2.7
V
Vss = -2.7 to -S.SV
VS
-2B.0
-
-12.0
V
VS
Function
VS
-
-
-B.O
V
Power voltage (2)
VO
ReCommended value
VO
VDD -2.S
Power voltage (3)
V2
Recommended value
V2
3/9 x VS
Power voltage (4)
V3
Recommended value
V3
VS
High-level input voltage
VIH
Vss = -2.7 to -S.SV
0.2 x Vss
Low-level input voltage
VIL
EI01, EI02,
FR, 00- 03,
XSCL, SHL,
LP,OSPOFF
High-level output vOltage
VOH
E101, EI02
VDD - 0.4
Low-level output voltage
VOL
Power voltage (1)
Vss
Recommended operating
voltage
VS
Possible operating
voltage
Input leakage current
Iu
110 leakage current
IUIO
Static current
Iss
Output resistance
Average operating
consumption current (1)
RSEG
Iss
Vss " VIN " VDD
V
DO - D3, LP,
FR, XSCL,
SHL,DSPOFF
-
-
2.0
!LA
E101, EI02
-
-
S.O
!LA
Vss
2S
!LA
00 - 079
-
1.S
1.9
Kn
Vss
-
0.10
0.2
mA
Freq. = 1MHz,
Ta = 2SoC, Chip alone
I/O terminal capacitance
CliO
530
-
- - - - - r0.07
Vss = -3.0V; other
pararneters are the
same as for Vss = -SV
CI
V
Vss + 0.4
1--:-.-----
Input terminal capacitance
V
-
-
Vss =-S.OV,
VIH = VDD, VIL = Vss,
fXSCL = 2.69MHz,
fLP = 16.BKHz,
fFR = 70Hz;
Input data: checker
pattern display, no load
Vss=-S.OV,
VO = O.OV, V2 = -9.3V,
V3 = -1B.6V,
VS = -2B.OV; other
parameters are the
same as for the Iss item
V
6/9 x VS
-
IWON = O.SV,
VS =-20.0V,
V3 = 13/1S x VS,
V2 = 2/1S x VS,
VO = VDD, Ta = 2SoC
IS
V
O.B x Vss
Vss " VIN " VDD
VS = -2B.0 to -14.0V,
VIH = VDD, VIL = Vss
Average operating
consumption current (2)
VDD
VDD
-
Vss = iloH = -D.6mA
-2.7 to IIOL = 0.6mA
-S.SV
-
-
V
V
0.1S-
VS
-
0.02
O.OS
mA
DO - D3, LP,
FR, XSCL,
SHL, DSPOFF
-
-
B
pF
E101, EI02
-
-
1S
pF
SED1648
•
o
AC Characteristics
Input Timing Characteristics
VIH=0.2 Vss
VIL=0.8 Vss
FR
1---- tc---+i
LP
XSCL
03-00
J-tsuE-EI01.2
(IN)
----------------Vss = -5.0 ± 0.5V. Ta = -40 to 85°C
Parameter
Symbol
Conditions
Min
Max
Unit
XSCL high-level pulse width
tWCH
-
XSCL low-level pulse width
twCl
-
30
-
ns
Data setup time
tos
-
20
-
ns
Data hold time
tOH
-
10
-
ns
XSCL ~ LP rising edge
tlO
40
-
ns
tlH
LP high-level pulse width
twlH
-
0
LP ~ XSCL falling edge
40
-
ns
+900
ns
XSCL frequency
tc
*3
ns
30
-
100
Allowable FR delay
tOF
-
-900
EIO setup time
tSUE
-
35
-
ns
ns
ns
VSS = -4.5 to -2.7V. Ta = -40 to 85°C
Parameter
XSCL frequency
Symbol
tc
XSCL high-level pulse width
twCH
XSCL low-level pulse width
tWCl
Data setup time
tos
Data hold time
tOH
XSCL ~ LP rising edge
tlO
LP ~ XSCL falling edge
LP high-level pulse width
Allowable FR delay
EIO setup time
Notes: *1. At 6.5 MHz.
*2. At 7.5 MHz.
Conditions
tlH
twlH
tSUE
Unit
153
-
ns
Vss =-3.0V
*2
133
-
ns
-
50
-
ns
-
15
50
ns
ns
0
-
Vss =-2.7V
75
-
ns
Vss=-3.0V
65
ns
ns
30
Vss=-2.7V
*3
75
-
Vss=-3.0V
*3
65
-
-900
+900
ns
ns
ns
ns
Vss=-2.7V
60
-
ns
Vss=-3.0V
50
-
ns
*3. twlH specifies when LP is "H" and XSCL is "L".
*4. The tr and If input signals are specified at 20 ns.
531
Max
*1
-
tOF
Min
Vss=-2.7V
I
SED1648
o
Output Timing Characteristics
VIH = 0.2 Vss
VIL= 0.8 Vss
FR
----------------------~>f:.====~-t-F-RS-D------------~-----------------
LP
XSCL
VIH = 0.2 Vss
'--------------\----- VOL = 0.8 Vss
EI01,2
(OUT)
On
(SEG)
-------------------------------------------.1. r - - - - - - - - - -
Vn-Q.5
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - ' 1 ' - - - - - - Vn+0.5
VDD = -5.0 ± 0.5V, V5 = -12.0 to -28.0V
Parameter
EIO reset time
EIO output delay time
LP ~ SEG output delay time
FR ~ SEG output delay time
Symbol
Conditions
Min
Max
Unit
tER
tDCL
CL = 15pF (EIO)
-
90
tLSD
tFRSD
CL = 100pF (On)
-
ns
ns
ns
Symbol
Conditions
55
200
400
ns
VDD = -4.5 to -2.7V, V5 = -12.0 to -28.0V
Parameter
EIO reset time
tER
EIO output delay time
tDCL
LP ~ SEG output delay time
FR ~ SEG output delay time
tLSD
tFRSD
CL = 15pF (EIO)
CL = 100pF (On)
Notes: '1. The tr and If input signals are specified at 20 ns.
532
Min
-
Max
150
Unit
ns
Vss=-2.7V
-
85
ns
Vss=-3.0V
-
75
-
400
ns
ns
800
ns
SED1648
•
Timing Diagram
Timing diagram (assuming 1/200 duty). (This diagram provided only as a reference.)
200
LP
LATCH
DATA
FR
XSCL
2
3
4
199
200
1
2
199
200
1
=±:=k:=x=x=x=--~~~:::~
---1
i
LP
1
~---~---~
L-
!
:--------
---fl
r1L-___
~-_--flnSUL_-~--n+_JlJ1JL
DO-D3~~~~
:
:
:
,
'
EloCD
--l
:
EIO®
If-:_ _ _ _ _ _ _ _ _ _---'
I
n'-____
EIO@ ~
CD - ® indicate driver cascade numbers.
LP
LATCH
DATA
FR
DSPOFF
~~~
•
I
I
:
I::
L
I
I
:
I::
V2
I
~~~
H
~:L
L:::H
,
,
H
:
:
:'--_ _L_
! - i_ _ _
,
VO
' I
,
················111 • • •·. .• • ·• • •·• • • • • • .·• •.•+··r.
m
••••••••••••
V3
V5
533
- - - - - " - - -_ _ _ _ _ "
___
"
______ "
"c_"~~
SED1648
•
LCD DRIVING POWER
•
Method of Forming Each Voltage Level
The simplest way to obtain the voltage levels for driving the LCs is to use resistive voltage dividers between
V5 and VDD, and to drive the LCs with op amp voltage followers.
In consideration of the use of op amps,
separate terminals.
va (the highest electrical level) and VDD are separated and given
va
However, when the voltage level of
is below VDD and the voltage difference between the two is large, the
performance of the LC output driver is reduced. Therefore, ensure that the voltage gap between
and VDD
is in the range of
2.5V.
va
av -
When op amps are not going to be used, connect
va to VDD.
Permanent damage may result to the LSI when there is serial resistance in the V5 or VDD power lines. This
is because the voltage drop that will occur at V5 or VDD when the signal changes will cause the power level
relationships within the LCD (i.e., VDD ~
~ V2 ~V3 ~ V5) to fail.
va
When a guard resistance is inserted, voltage stabilization using a capacitance is necessary.
•
Cautions During Power Up and Power Down
Because of the high voltage of the LC driving system of this LSI, if the power to the logic system is floating
or if Vss is greater than or equal to -2.6V when a high voltage is applied to the LC driving system, or if the
LC driving Signal is output before the LC driving system voltage stabilizes, then too much current will flow,
causing damage to the LSI.
It is recommended that the display off function (DSPOFF) be used to keep the LCD driver output level at
until the LCD drive system voltage stabilizes.
va
Follow the sequences below during power up and power down:
Power up: Logic system on
~
LC drive system on (or simultaneous)
Power down: LC drive system off
~
Logic system off (or simultaneous)
As a way to prevent excessive current, insert a high-speed fuse or guard resistance in series with the LC
power source.
The optimal value of the guard resistance must be selected based on the capacitance of the LC cells.
V
t1
VDD
Vss
- ---
V5
----------- I---------~-.
t2
-
.
'/
Power
ON
DSPOFF
....
.... ..
-
---- -----Power
OFF
t3
VDD --------------Vss
.. t
534
t1, 12, t3
as
SED1648
•
•
EXAMPLE OF CONNECTION
Large Screen LCD Structure Diagram
R
V5
Vss
V5
YD
YSCL
SHL
V4
V3
V1
VO VDD
,.. DI01 U; ~
r-------
co
0
~o
[DI02 11 V
FR
~~
SEL
(GND)
-r-------
DI01
640 X 200 DOT
~
~8
~~
DI02
1/200 DUTY
DI3 = H or L
VDD
LP
XSCL
SHL
DSPOFF
DLO -3
V2
~8D>-
~80,>-
SED1648
EI01
EI02
SED1648
EI01
EI02
CD
®
It t t
It tt 1
~8D>----------------
----------------
535
SED1648
EI01
EI02
®
lllj
I
SED1648
•
PAD LAYOUT
90
80
60
70
40
50
000000000000000000000000000000000000000000000000000000000000 Do
DOD 0
5
DOD
DOD
o
o
DO
DO
~O,O)
o
~D
o
10
0
0
0
15
0
0 DO
0
20
DOD DO
25
Chip size .................. 11 .93 mm x 1.45 mm
Chip thickness ......... 400 !1m (TYP)
AI Pad Specifications (SED1648DoA)
: chip edge
------------------~---------~-------T--
DD[~pu-a D ~151u-a,
"
[lrJ
[J [1,.L 0----- - - i
:- 178u --: (min)
I
l
________ j=_~~~~_·~~·~-_L(_~i_nl __
J____
chip edge
Pad a aperture (X, V): ................... 100 x 120!1m PAD No. 38-97
Pad b aperture (X, V): ................... 110 x 110!1m PAD No. 28-37, 98-107
Pad c aperture (X, V): ................... 110 x 110!1m PAD No. 1-27
536
!
----------
-~--
SED1648
•
PAD COORDINATES
Unit:~m
Y
Pad
No.
Pad
Name
X
Coord.
Coord.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
EI02
VO
V2
V3
V5
Vss
-5653
-5297
-5117
-4936
-4547
-4091
-3839
-3587
-3065
-2828
-2590
-2086
-1583
-1079
1079
1583
2086
2590
3065
3587
3839
4091
4594
4984
5164
5345
5653
5814
5653
5814
5653
5814
5653
5814
5653
5814
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-560
-414
-305
-196
-86
23
132
241
351
460
NC
SHL
NC
NC
VDD
OSPOFF
FR
LP
XSCL
00
01
02
NC
03
NC
Vss
V5
V3
V2
VO
EI01
00
01
02
03
04
05
06
07
08
Y
Pad
No.
Pad
Name
X
Coord.
Coord.
37
38
39
40
41
42
43
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
5653
5268
5090
4911
4732
4554
4375
4197
4018
3839
3661
3482
3304
3125
2946
2768
2589
2411
2232
2053
1875
1696
1518
1339
1160
982
803
625
446
267
89
-89
-267
-446
-625
-803
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
044
537
Y
Pad
No.
Pad
Name
X
Coord.
Coord.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
-982
-1160
-1339
-1518
-1696
-1875
-2053
-2232
-2411
-2589
-2768
-2946
-3125
-3304
-3482
-3661
-3839
-4018
-4197
-4375
-4554
-4732
-4911
-5090
-5268
-5653
-5814
-5653
-5814
-5653
-5814
-5653
-5814
-5653
-5814
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
569
460
351
241
132
23
-86
-195
-305
-414
I
THIS PAGE INTENTIONALLY BLANK
538
BO-BIT EXPANSION LCD DRIVER
•
DESCRIPTION
The SED1681 is an 80-bit expansion segment (column) driver suitable for driving high-contrast, smallcapacity dot matrix liquid crystal displays with a duty from 1/8 to 1/32. It is best suited for expanding the
segment drive capability of LCD controllers such as the SED1278F, or a 4-bit microcomputer.
•
FEATURES
• Low-power CMOS technology
• Capable of a serial cascade connection
• 80-bit segment (column) driver
• Wide range of LCD voltage ........ -3.0V to -12V
• Serial input data
• Duty cycle ................................... 1/8 to 1/32
• Supply voltage ............................ 2.4V to 6.0V
• Package .......................... QFP5-100 pin (FOA)
DIE: AI pad chip (DOA)
• Suitable for use with a wide range of LCD controllers
•
I
SYSTEM BLOCK DIAGRAM
40SEG
DATA
CPU
SED1278
CONTROL
16COM>
-U
24 CHAR
X
2 LINES
(9
UJ
rJ)
0
00
XSCL, LP
DO
539
SED1681
SED1681
•
BLOCK DIAGRAM
Vss Voo
SEGO 1
VO
2 - - - - - -
LCD Driver
80 bits
V2
V3
V5 V"'''---.------'
FR
LPn-------------~
DI
DO
SHL
XSCLn-----------------------~
540
79
SED1681
_PINOUT
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG4l
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG3l
SEG30
NC
NC
NC
NC
Voo
NC
FR
NC
DO
DI
SED1681
XSCL
SHL
Index
95
NC
0
LP
Vss
V2
V3
VO
V5
NC
NC : No Connection
• PIN DESCRIPTION
Pin/Pad
Number
Name
Input!
Output
1 to 30,
SEGO to
51 to 100 SEG79
0
Liquid crystal segment drive outputs
Segment outputs change on the falling edge of the LP input signal.
Description
40
XSCL
I
Shift clock input
Shift register data is shifted on the falling edge of this signal.
37
LP
I
Display data strobe. Data from the shift register is strobed on to the display
data latch on the falling edge of this signal.
41
01
I
Serial data input
42
DO
0
Serial data output
I
Shift direction select
This pin selects the data shift direction from bit 0 towards bit 79 or in reverse.
I
Liquid crystal frame signal input
39
SHL
44
FR
46
Voo
-
36
Vss
32 to 35
Vo, V2,
V3, Vs
-
31,38,
43,45,
47 to 50
NC
-
Logic power supply
Ground
LCD drive voltage supply inputs
These voltages should satisfy the following conditions:
Voo? Vo, Voo? V2? 1/2 x VS, 1/2 x Vs? V3 ? vs
No connection
541
I
SED1681
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voo
=OV)
Symbol
Ratings
Unit
Supply voltage (1)
Vss
-7.0 to 0.3
V
Supply voltage (2)
Vs
-15.0 to 0.3
V
Supply voltage (3)
V
Parameter
Va, V2, V3
-15.0 to 0.3
Input voltage
VIN
Vss -0.3 to 0.3
V
Output voltage
Va
Vss -0.3 to 0.3
V
Po
300
mW
Operating temperature
Topr
-20 to 75
°C
Storage temperature
Tstg
-65 to 150
°C
Soldering temperature, time
Tsol
260°C, 10 sec (at lead)
Power dissipation
-
Notes:
1. All voltages are based on Voo = OV.
2. Never use wave soldering to mount packages, or any other method that applies excessive thermal stress to a
package, as this will reduce its heat dissipation capacity.
542
SED1681
•
DC Electrical Characteristics
(Unless otherwise specified, VDD = Vo = 0 V, Vss = -S.O V
Parameter
Symbol
Condition
± 10%, T a = -20 to 7S°C)
Pin
Min
Typ
Max
Unit
-S.O
-2.4
V
Supply voltage (1)
Vss
Vss
-6.0
Recommended
operating voltage
V5
V5
-12.0
-
-3.0
V
V
Permitted operating voltage
V5
Operational limits *1
V5
-12.0
V2
Recommended value
V2
1/2 x V5
-
-2.S
Supply voltage (2)
VDD
V
Supply voltage (3)
V3
Recommended value
V3
V5
-
1/2 x V5
V
High-level input voltage
VIH
Low-level input voltage
VIL
High-level output voltage
VOH
Low-level output voltage
VOL
Input leakage current
III
Output leakage current
ILO
Quiescent current
10
Output resistance
RSEG
DI, XSCL 0.2xVss
LP, SHL,
FR
IOH =-0.6 mA
IOL = 0.6 mA
o V ~ VIN~VSS
o V ~ VOUT~ Vss
V5 = -12.0 V
Vss = -6.0 V, VIH = vcc
~VON =
0.1 V
Ta = 2SoC
V5 =-8.0V
V5 =-S.OV
Vs =-3.0V
Supply current (1)
Issop
Vss = -s.o V, VIH = VDD
VIL = Vss, LP = S20 !-Ls,
fXSCL = 400 kHz.,
FR = 16.7 ms, all data
inputs are alternate I and
data, all output open.
DO
-
VDD
V
Vss
-
0.8xVss
V
-0.4
-
-
-
-
V
Vss+O.4
V
O.OS
2.0
!-LA
DO
-
O.OS
s.o
!-LA
VDD
-
O.OS
30
!-LA
-
1.S
3.0
3.0
8.0
-
10.0
SO.O
Vss
-
2S0
3S0
!-LA
Vs
-
10
16
!-LA
-
S
8
pF
SHL, FR
XSCL, LP
SEGO
to
SEG79
kQ
o
Supply current (2)
Isop
Input pin capacitance
CIN
Vss = -4.SV, V2 = -4.8V
V3=-7.2 V,
VSSH = -12.0 V; Other
conditions as for Iss OP
SHL, FR
XSCL, LP
Ta = 2SoC
*1. This parameter specifies the range of V5 over which operation is possible. The driver ON-resistance for the particular
LCD panel being used may result in VS exceeding the recommended operating range. The VS operating vOltage should
be determined experimentally and component changes made, if necessary, to ensure operation within the recommended range
S43
I
SED1681
•
o
AC Electrical Characteristics
Input Timing
FR
LP
_ _
---'F'·'"~_tD_FR
_ _
- t l T - I T - tlH
XSCL
-twell
01
tDS-
-tDH
(Vss
Parameter
Symbol
Shift clock period
tCLC
Shift clock High-level pulse width
tWCLH
Shift clock Low-level pulse width
tWCLL
Conditions
=-6.0 V to -2.4 V, Ta =-20 to 75°C)
Min
1.0
450
450
Typ
I-ls
-
ns
-
-
ns
500
50
50
ns
Shift clock to latch pulse interval
tLT
Latch hold time
tLH
Frame signal delay time
tOFR
-500
-
Input signal rise time
tr
Input signal fall time
tt
-
-
tos
Data hold time
tOH
Latch pulse High-level pulse width
twLPH
544
Unit
-
140
100
200
200
100
Data setup time
Max
-
ns
ns
ns
ns
ns
ns
ns
SED1681
o
Output Timing
--------------~1-
FR
tFRSD ----
LP
XSCL
](~----+->--.)(
DO
----------~
SEG
~-----
____________________________
--=K~
_____
(VSS = -6.0 V to -2.4 V, V5 = -12.0 V to -3.0 V, Ta = -20 to 75°C)
Parameter
Serial data output delay time
LP-SEG output delay time
FR-SEG output delay time
Symbol
Condition
Min
tPD
CL= 15 pF
-
tLPSD
CL= 100 pF
tFRSD
545
Typ
Max
Unit
-
250
ns
-
4.5
Ils
-
4.5
Ils
I
SED1681
• Timing Chart
16
1
2
3
4
15 16
1
2
3
15 16
1
LP~ ____ ~ ____ ~
LATCH
DATA
If-:_____
LP
~~_ _ _ _ _ _ _~
XSCL
L51SUL---
---~
X 0 X 1 X 2 --- X76X 77X 78 X79--- ~ 0 X 1 X 2 X3 ---_X"-----Ll.X--'X"-
010
SHL
=
Vss
SEGO
SEG79
SHL =V DD
SEGO
SEG79
LP
LATCH
DATA
FR
X X X
:X :X X X X: : : : _--Ll.X----'-X>.--"'-X--LlX--,X01.-
FR
~\\
'
,
,
~\'\
"
L :
;1
:
H )
X
79
X
0
X
0
X
79
~\
~\
H
I
L 1\
-RJULfL
~
L '
I
:H
~~~
-•• ·H';-t1-H
V3
------
--'
~-------
------------------
------ -- ----------- --------------------V5
------
-------~
---------------------
546
--'
--
---
---
SED1681
• EXAMPLE OF APPLICATION
eSED1278
------\
24 CHAR x 2 LINES
r-I
0
16
"t"'"
(!)
~--------------.
w
(!)
w
en
~
0
..,.
en
CQM16
COM1
SED1278
c
'"
C\I
CO)
Il)
~~ > > >
DO
01
1-0
0-------------------0)
I'w
(!)
(!)
en
XSCL
LP
FR
FR
SED1681
J!;~~gz~
I
547
OPEN
en
XSCL
LP
DO
W
Voo
SHL
t
I
SED1681
•
PAD LAYOUT
30
25
20
15
10
5
00000000000000000000000000000000 100
L
o
o
o
0
0
0
Y
o
350
o
o
o
0
4°Bo
B90
X
(0,0)
o
0
0
0
o
o
45 0
0
~
0
o
w
~
0
0
0
B
0
B
~~~
00000000000000000000000000000000
55
60
65
70
75
80
Chip Specification
Dimension (mm)
Chip size
5.59 x 3.50
Pad pitch
0.160 min.
Chip thickness
0.40 ±0.025
Pad size
0.10 xO.10
548
SED1681
• PAD COORDINATES
Pad
Number Name
1
SEG29
2
SEG28
SEG27
3
SEG26
4
SEG25
5
SEG24
6
SEG23
7
SEG22
8
SEG21
9
SEG20
10
11
SEG19
12
SEG18
13
SEG17
SEG16
14
15
SEG15
16
SEG14
17
SEG13
18
SEG12
19
SEG11
SEG10
20
21
SEG9
22
SEG8
SEG7
23
24
SEG6
25
SEG5
26
SEG4
27
SEG3
SEG2
28
29
SEG1
30
SEGO
31
NC
32
V5
Va
33
34
V3
Unit = Ilm
X
(Ilm)
(Ilm)
-2461
-2261
-2069
-1885
-1709
-1538
-1366
-1203
-1040
--880
-720
-560
-400
-240
--80
80
240
400
560
720
880
1040
1203
1366
1538
1709
1885
2069
2261
2461
2632
2632
2632
2632
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1588
-1548
-1374
-1206
-1040
Y
Pad
Number Name
V2
35
36
Vss
37
LP
38
NC
39
SHL
40
XSCL
41
01
42
00
43
NC
44
FR
45
NC
46
VDD
47
NC
48
NC
49
NC
NC
50
51
SEG79
52
SEG78
SEG77
53
54
SEG76
55
SEG75
56
SEG74
57
SEG73
58
SEG72
SEG71
59
SEG70
60
61
SEG69
62
SEG68
SEG67
63
64
SEG66
65
SEG65
66
SEG64
67
SEG63
68
SEG62
549
X
(Ilm)
(Ilm)
2632
2632
2632
2632
2632
2632
2632
2632
2632
2632
2632
2632
2632
2632
2632
2632
2461
2261
2069
1885
1709
1538
1366
1203
1040
880
720
560
400
240
80
-80
-240
-400
--881
-721
-561
-401
-241
-81
79
239
399
559
719
879
1039
1204
1372
1546
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
Y
Pad
Number Name
69
SEG61
70
SEG60
71
SEG59
72
SEG58
73
SEG57
74
SEG56
75
SEG55
76
SEG54
77
SEG53
78
SEG52
79
SEG51
SEG50
80
81
SEG49
82
SEG48
83
SEG47
84
SEG46
SEG45
85
SEG44
86
87
SEG43
88
SEG42
89
SEG41
90
SEG40
91
SEG39
92
SEG38
SEG37
93
94
SEG36
95
SEG35
96
SEG34
97
SEG33
98
SEG32
99
SEG31
100 SEG30
y
X
(Ilm)
(Ilm)
-560
-720
-880
-1040
-1203
-1366
-1538
-1709
-1885
-2069
-2261
-2461
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
-2632
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1588
1546
1372
1204
1039
879
719
559
399
239
79
--81
-241
-401
-561
-721
-881
-1041
-1206
-1374
-1548
I
THIS PAGE INTENTIONALLY BLANK
550
SED1722/24
CMOS LCD DRIVER
• CMOS 80-Bit Segment Driver
•
DESCRIPTION
The SED1722/24 is an ao dot matrix LCD segment (column) driver for driving high-capacity LCD panels at
duty cycles higher than 1/100 (up to 1/500). The LSI features a wide range of LCD drive voltages.
The device uses a high-speed daisy-chain enable system which decreases power consumption and
eliminates the need for separate enable signals for each driver.
The SED1722/24 is used in conjunction with the SED1733F (1 OO-bit output common driver) to drive a largecapacity dot matrix LCD panel.
•
•
FEATURES
• Low-power high-speed CMOS technology
• Supports display blanking
• aO-bit segment (column) driver
• Low output resistance
• High-speed data bus .............. 4-bit (SED1722)
a-bit (SED1724)
• Ability to adjust offset bias of the LCD source from
• Duty cycle ............................... 1/100 to 1/500
• Low output impedance ........... 1KQ
VDD
• Shift clock frequency .............. 12 MHz
• Wide range of LCD voltage .... 14 to 40V
• Adjustable LCD drive voltages
• Supply voltage ........................ 4.5 to 5.5V
• Selectable output shift direction
• Package .................. QFP-5 100 pins (FOA)
AI pad (DOA)
SYSTEM BLOCK DIAGRAM
DO - D3, DO-D7 (SED1724)
XSCL
LCD
CONTR
LP, FR
YSCL
YD
320 SEG x 200 COM
DUTY: 1/200
551
I
SED1722124
• BLOCK DIAGRAM
eSED1722
eSED1724
GNO Vee
t
V2,V3
VOOH
GNO
00··························· 079
t
11
~ Voltage
control
,
FR
Vee
t
t
r
V2, V3
LCD driver,
BObits
VOOH
GNO
/\.
FR
Level shifter, BO bits
I\,
INH
LP
INH
LP
Latch, BO bits
/\
Two-way shift register
00-03
~
control
SHL
EI01
EI02
XSCL
~
Enable
control
t
j4
Jr
00-03
04-07
I
SHL
EI01
EI02
I
XSCL
552
00··························· 079
SED1722124
• PIN DESCRIPTION
Pin Name
I/O
Q'ty
Function
00 to 79
0
To output the driving segment (column).
The output changes at the LP fall edge.
DO to D3
(SED1722)
I
To input display data.
H: Selection data, L: Non-selection data
4
DO to D7
(SED1724)
I
To input display data.
H: Selection data, L: Non-selection data
8
I
To input shift clock for display data (fall edge trigger)
1
To input latch pulse for display data (fall edge trigger)
Enable input and output:
Input or output is set on the SHL input level.
Output is reset by an input to LP and falls to "L" automatically
when 80-bit data is completely fetched in.
1
2
To select shift direction and to input input-output control data for
the EIO terminal.
When the data are input to (DO, D1 ,.. D7) terminals in the order of
(a, b, .. g, h), (i, .. 0, p) ... (s, t, .. y, z), relations between data and
segment outputs come to be as per the following table:
1
80
-------------- . --- - -------------------------------------------------------- -- - --
XSCL
LP
EI01
EI02
I
I/O
SHL
I
SHL
o (SEG Output)
4
......
77
c
d
e
......
x
y
Z
x
w
v
......
c
b
a
1
2
H
a
b
L
Z
Y
I
EIO
3
0
78
79
1
2
Input Output
Output Input
Note: The relations between data and segment outputs are
set irrespectively to number of shift locks.
FR
To input AC signal for LCD driving output.
1
Vee, GND
Power
Supply
Logic power supply, GND: 0 V, Vee: +5 V
2
VDDH
Power
Supply
Power supply for LCD driving circuit
VDDH: +14 V to 40 V, (Liquid crystal driving selection level)
1
V2, V3
Power
Supply
Power supply for driving liquid crystal
VDDH ~ V2 ~ 7/9 VDDH, 2/9 VDDH ~ V3
2
-
INH
I
I
~
GND
Forced blank input
Output on the "L" level are forced to non-selection level.
553
1
SED1722124
•
•
ELECTRICAL CHARACTERISITCS
Absolute Maximum Ratings
Parameter
(GND
= 0 V)
Symbol
Ratings
Unit
Supply voltage (1)
Vee
-{).3 to +7.0
V
Supply voltage (2)
VDDH
-0.3 to +45.0
V
Supply voltage (3)
V2, V3
-0.3 to VDDH +0.3
V
V
Input voltage
VI
-0.3 to Vee +0.3
Output voltage
Vo
-0.3 to Vee +0.3
V
EIO output current
101
20
mA
LCD circuit output current
102
20
mA
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-65 to +150
°C
Note 1. Let the V2 and V3 voltages maintain the condition, VDDH '" V2 '" V3 '" GND, all the time.
VDDH
V2
40V
VCC
V3
5V
GND
GND
Note 2. If the logic circuit power supply comes to float power-supply voltage supply voltage is applied to the liquid crystal driving
circuit, the LSI may be broken permanently. So, prevent the logic circuit power supply from floating. Pay special
attention to the power supply sequence when the system is switched on or off.
554
SED1722124
• DC Electrical Characteristics
(Unless otherwise specified, GND=OV, Vee= +5.0V±10%, Ta= -20 to 75°C)
Terminal
Min
Typ
Max
Unit
Supply voltage (1)
Vee
Vee
4.5
5.0
5.5
V
Recommended supply voltage
VOOH
VOOH
14.0
40.0
V
Operable voltage
VOOH
VOOH
8.0
-
-
V
Supply voltage (2)
V2
Recommendation value
V2
7/9VDDH
-
VOOH
V
Supply voltage (3)
V3
Recommendation value
GND
-
2/9VDDH
V
High level input voltage
VIH
V3
E101. E102.
DO to D3:
(SED1722)
0.8Vee
-
Vee
V
Low level input voltage
VIL
GND
-
0.2Vee
V
High level output voltage
VOH
IOH =-0.6 mA
Vcc-O.4
-
Vee
V
Low level output voltage
VOL
IOL = 0.6 mA
GNO
0.4
V
-
-
2.0
IlA
EI01, EI02
-
-
5.0
IlA
GND
-
-
25
IlA
*1
-
0,7
1.8
00 to
079
-
0,8
2.2
1.0
2.6
Vee
-
0,5
1,5
mA
VOOH
-
0.2
1.5
mA
-
-
8
pF
-
-
15
pF
Parameter
Input leak current
Symbol
III
Condition
Function
DO to D7
(SED1724).
XSCL. SHL.
FR. LP, INH
EI01, EI02
DO to D3:
(SED1722)
GND :2: VIN:2: Vee
DO to D7
(SED1724),
SHL, XSCL,
LP, FR, INH
Input-output leak current
Static current
Output resistance.
ILi/O
GND :2: VIN :2: Vee
IGNO
VOOH = 14.0 to 40.0 V
VIH = Vee, VIL = GND
RSEG
Current consumed (1)
Ice
Current consumed (2)
looH
dVON
=0.5V
VooH=+30.0V
VooH=+20.0V ]
VOOH=+ 14.0V
VCC = +5.0 V, VIH = Vcc,
VIL = GND, fXSCL =5.38 MHz,
fLP =33.6 kHz, fFR =70 Hz;
Input data: To be inverted
1 bit/1H. No load
Vcc - +5.0 V, V3 - +4.0 V,
V2 = +26.0 V, VOOH =+30.0V
Other conditions are same as
those of Icc
kQ
DO to D3:
(SED1722)
Input terminal capacity
CI
DO to D7
Freq.=1 MHz, Ta = 25°C
I/O terminal capacity
(SED1724),
SHL, XSCL,
LP, FR, INH
EI01, EI02
CliO
*1. The output resistance is specified within the ranges of the supply voltages (2) and (3).
555
I
SED1722124
• AC Electrical Characteristics
o Input Timing Characteristics
VIH = 0.8 x Vcc
VIL = 0.2 x Vcc
FR
~--- tWLH ----LP
·1
to~
~
____________
~
__________
XSCL
00-03: SED1722
00-07: SED1724
_______________________________~tSUE~
EI01,2
(IN)
(Vcc
Parameter
Condition
Symbol
= 5 0 V +10%
-
Ta
=-20 to 75°C)
Min
Typ
Max
Unit
tc
83
--
--
ns
XSCL high level pulse width
tWCH
30
--
--
ns
XSCL low level pulse width
tWCL
30
--
ns
XSCLcycie
Data setup time
tos
30
---
--
ns
Data hold time
tOH
20
--
--
ns
XSCL to LP rise time
tLD
0
ns
tLH
200
---
--
LP to XSCL fall time
--
ns
70
--
--
ns
LP high level pulse width
twLH
see note
FR delay allowable time
tOF
-300
--
300
ns
EIO setup time
tSUE
36
--
--
ns
Note: twLH is the time when LP is "H" and XSCL is "L"
556
SED1722124
o Output Timing Characteristics
FR
---------------------------------~---------V----0-8-X-V-IH =
ee
tFRSD-
LP
tER ...
VIL = 0.2 x Vee
I-ILSD-
XSCL
I-~
EI01,2
VOH = 0.8 xVe e
VOL = 0.2 x Ve e
(OUT)
::xr::
INH
I"
ILSD
o output
K
(Vee = +5.0 V ±100/0, VDDH = 14.0 to 40.0 V, Ta = -20 to 75°C)
Parameter
Symbol
EIO reset time
tER
EIO output delay time
tDeL
LP to output delay time
tLSD
FR to output delay time
tFRSD
INH to output delay time
tpdlNH
Conditions
CL = 15 pF
CL = 100 pF
557
Min
Typ
Max
Unit
-
-
120
ns
-
-
45
ns
0.5
~
-
-
0.7
Ils
-
-
0.5
Ils
I
SED1722/24
•
Timing Diagram
When it is 1/240 duty (example for reference)
4
240
LP
Latch Data
_ _~U-~L-~~~-U~
239
240
2
239
----~
FR
I
LP
XSCL
DO to D7
10
X 1 Z2
Z
3
EIOG)~~'"
EIC?®_
EIO@
CD
to @ are the driver's cascade numbers.
* In high-speed data transmission, the XSCL period may need
to be longer in the LP pulse insertion timing, so as to secure
the LP --.. XSCL (tLH) standard.
LP
n~n~n~nYI
-----.J
Latch Data
~I
,
FR
H
,
,
:
L
II
240
____ .JLrLJLJLfL ____ ~
xZ Z Z Z
ZZ Z
~I
~I
II
:
L
:
558
: H
iI
H
SED1722124
• EXAMPLE OF REFERENCE CIRCUIT
(Combination of SED1722 with SED1733)
00-03~~~~~
SHL
LP
XSCL
0101 ---t-1r-----i
YSCL---tTr-----i
SHL ---r-Tt-t-H
FR --t-tTt--INH --H-I-t--
Liquid crystal panel
(640 x 400 dots)
(Combination of SED1724 with SED1733)
00 - 07
SHL
LP
XSCL
~~:~:~~ I
EI02
EI01
SE01724
0101
YSCL
!-
SHL
+::c
L
0101
...
~
0102
(')~
f2-----V
Ei
Liquid crystal panel
(640 x 400 dots)
0103lJ5~
-----v
. r- 0104
·llli
~
f2 t-v
!-
t--E
~~
EI01
E102j'
SE01724
0102 Ei
0103lJ5 ~
t-v
0104
0101
FR
INH
~
(')
EI01
EI02
SE01724
0101:
~~
L-t 0103lJ5~
Ei
0102
50
0104
559
0 01 EI01
EI02
SE01724
~8~
I
SED1722124
•
•
PACKAGE DIMENSIONS
SED1722FoA, SED1724FoA
~~~~~~~~;~~~~~~~~~oog
O ••--------------~
50
51
29
28
52
53
27
26
54
55
56
25
24
23
57
58
59
80
22
21
20
81
62
63
19
18
17
16
15
SED1722FoA/
SED1724FoA
64
65
66
67
68
69
14
13
12
11
10
9
8
7
6
5
70
71
72
73
74
75
4
76
3
77
78
2
o
79 __~~~~~~~~~~~~~
1
0
NC: No connection is required
•
Plastic QFP5-100 pin
25.6 ± 0.4
20±O.1
I ~ -.
~~IMUUUUUIIIIIMIUUUIIIIIIIII111J:J
1.5:±O3
2.8
560
0-12'
SED1722124
• PAD LAYOUT (SED1722DoA, SED1724DoA)
1 100
DO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000000000000000
y
L,
(0,0)
DO
00000000000000000000
DO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DO
5.81 mm x 5.20 mm
Chip Dimensions
Pad pitch
0.160 mm (Min.)
Chip thickness
0.400 ±O.025 mm
Aluminum pad opening
100 Ilm x 100 Ilm (all terminals)
• PAD COORDINATES
Pad
Number Name
1
050
2
051
052
3
4
053
5
054
6
055
056
7
8
057
058
9
10
059
11
060
12
061
13
062
14
063
15
064
16
065
17
066
18
067
19
068
20
069
21
070
22
071
23
072
24
073
25
074
26
075
27
076
28
077
078
29
30
079
31
EI02
32
EIOl
00
33
34
01
X
(11m)
-2488
-2488
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2738
-2488
-2000
-1750
-1500
-1300
Y
(11m)
2432
2432
2222
2022
1835
1660
1485
1310
1135
960
785
610
435
260
85
-85
-260
-435
-610
-785
-960
-1135
-1310
-1485
-1660
-1835
-2022
-2222
-2432
-2432
-2432
-2432
-2432
-2432
Pad
Number Name
02
35
36
03
37
NCID4
NC/05
38
NC/06
39
40
NC/07
41
SHL
42
XSCL
43
INH
44
LP
45
FR
46
vcc
47
V2
48
V3
49
GNO
VDDH
50
51
00
52
01
02
53
54
03
04
55
56
05
57
06
58
07
59
08
60
09
61
010
62
011
012
63
64
013
014
65
66
015
67
016
68
017
X
(11m)
-1100
-900
-700
-500
-300
-100
100
300
500
700
900
1100
1300
1500
1750
2000
2488
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
561
Y
(11m)
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2432
-2222
-2022
-1835
-1660
-1485
-1310
-1135
-960
-785
-610
-435
-260
-85
85
260
435
Pad
Number Name
018
69
70
019
71
020
72
021
73
022
74
023
75
024
76
025
77
026
78
027
79
028
80
029
81
030
82
031
032
83
84
033
034
85
86
035
87
036
037
88
89
038
90
039
91
040
92
041
93
042
94
043
95
044
96
045
97
046
047
98
99
048
100
049
X
(11m)
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2738
2488
2000
1750
1500
1300
1100
900
700
500
300
100
-100
-300
-500
-700
-900
-1100
-1300
-1500
-1750
-2000
Y
(11m)
610
785
960
1135
1310
1485
1660
1835
2022
2222
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
I
THIS PAGE INTENTIONALLY BLANK
562
SED1742/44
• CMOS 160-bit Segment Driver
• High Voltage LCD Driver
•
DESCRIPTION
The SED1742/SED1744 is a 160 dot matrix LCD segment (column) driver for driving high-capacity LCD
panels at duty cycles higher than 1/100 (up to 1/500). The LSI features a wide range of LCD voltages. The
upper and lower LCD drive voltages (VO, V5) are independent ofthe chip supplies. This enables the LCD drive
bias voltages to be supplied from an external source. The device uses a daisy-chain enable system which
decreases power consumption and eliminates the need for separate enable signals for each driver.
The SED1742/44 is used in conjunction with the SED17 43 (160-bit common driver) to drive a large-capacity
dot matrix LCD panel.
•
FEATURES
• Ability to adjust offset bias of the LCD source from
VDD
• Low-power high-speed CMOS technology
• 160-bit segment (column) driver
• High-speed data bus ... .4-bit (SED1742)
8-bit (SED1744)
• Daisy chain enable support
• Duty cycle ..................... 1/100 to 1/500
• Wide range of LCD voltage .... 14 to 40V
• Adjustable LCD drive voltages
• Supply voltage ........................ 2.7 to 5.5V
• Unbiased display off function
• Package .................................. TAB (TOA)
Au bump (016)
• No enable signal by controller is required
• Adjustable offset bias of the LCD according to
VDDH and GND
• Shift clock frequency .... 12M Hz max at VDD = 5V
•
SYSTEM BLOCK DIAGRAM
DO-D3, DO-D7 (SED1744)
XSCL
LCD
CONTR
LP, FR
YSCL
-
YD
"l
SED1742
I
~6~
I SED1742
~6~
ISED1743~
~
ISED1743~
320 SEG x 480 COM
DUTY: 1/480
~
ISED1743~
563
I
SED1742144
• BLOCK DIAGRAM
e SED1742
eSED1744
00----
----- 0159
00--------------- 0159
VO 00------1
VO 00------1
V2
V500------1
V5
V3
VDDH
VDDH
FR
FR
INH
LP
INH
LP
Vee
GND
Vee
GND
DO-D3
XSCL
EI01
DO-D7
• SHL
• EI02
XSCL
EI01
564
SHL
EI02
SED1742144
• PIN DESCRIPTION
Pin Name
00 to 159
-
DO to 03
(SED1742)
I
--.-.---------
DO TO 07
(SED1744)
Function
I/O
Q'ty
LCD crystal segment (column) output
The output varies at the LP trailing edge.
160
Display data input
4
- - - - - -------------------------------------------------------- ----I
Display data input
8
XSCL
I
Display data shift clock input (triggered at the trailing edge)
1
LP
I
Display data latch pulse input (triggered at the trailing edge)
1
Enable I/O. Set to input or output according to SHL input level.
The output is reset at the LP input and set to "L" when a 160-bit data
fetch is complete.
2
E101, EI02
SHL
I/O
I
Shift direction selection and EIO terminal I/O control input (SED1744)
When the data (a, b, .. g, h) (i, .. 0, p) ... (s, t, .. y, z) are input in this
sequence to the terminals (DO, 01, .. 07), the relation between the data
and the segment output is as shown in the table below.
o (SEG Output)
SHL
159 158 157 156 155
1
EIO
......
2
1
0
L
a
b
c
d
e
......
x
y
z
H
z
y
x
w
v
......
c
b
a
1
2
I
Output Input
Input Output
Note: The relation between the data and the segment output is
determined independently of the number of shift locks.
Input of signal to AC electrify the liquid crystal drive output
1
Vcc, GND
FR
Power
Source
Logic power source. GND: 0 V; Vce: +3, +5 V
2
YO, V2, V3, V5
VDDH
Power
Source
Liquid crystal drive power source VDDH: +14 V to 40 V; GND: 0 V
VDDH ~ VO > V2 ~ 7/9 VDDH, 2/9 VDDH ~ V3 > V5 ~ GND
5
I
Forced blank input
The signal forces the output to be set to V5 level at the "L" level.
1
Test input normally fixed at "L" level.
1
INH
TEST
I
565
SED1742144
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Ratings
Unit
Supply voltage range (1)
Vee
-0.3 to +7.0
V
Supply voltage for LCD (1)
VDDH
-0.3 to +45.0
V
Supply voltage for LCD (2)
VO, V2,V3, V5
GND -0.3 to VDDH +0.3
V
Input voltage (4)
VI
GND -0.3 to VCC +0.3
V
Output voltage
Va
GND -0.3 to VCC +0.3
V
Parameter
EIO output current
101
20
rnA
Operating temperature
Topr
-20 to +75
°C
Storage temperature 1 (3)
Tstg1
-65 to +150
°C
Storage temperature 2 (3)
Tstg2
-55 to +150
°C
Logic supply
Vee
3*
V
VDDH
14 to 28*
V
Segment driver supply voltage range
VDDH
VO
V2
40V
Vee
5V
V3
V5
GND
GND
Notes: 1. The voltage is based at GND = 0 V
2. Voltage VO, V2, V3 and V5 should satisfy the condition: VDDH ~ VO ~ V2 ~ V3 ~ V5 ~ GND.
3. The storage temperature 1 is specified for a single chip and the storage temperature 2 is for TCP
mounting.
4. WARNING: The LSI may be externally broken if the logic system power source floats or decreases below
Vee =2.9 V while voltage is applied to the liquid crystal drive system power source. Special care should
be taken for the power source sequence when turning the system power on and off.
566
SED1742/44
• DC Electrical Characteristics
(Unless stated otherwise GND=V5=OV, Vee= +5.0V±10%, Ta = -20 to 75°C)
Terminal
Min
Typ
Max
Logic supply voltage (1)
Vee
Vee
3.0
5.0
5.5
V
Operation voltage recommended
VOOH
VOOH
14.0
-
40.0
V
Segment driver input supply voltage
VOOH
VOOH
8.0
-
Segment driver input supply voltage (2)
VO
VO
VOOH-2.5
-
Parameter
Condition
Symbol
Function
Value recommended
Segment driver input supply voltage (2)
V2
Value recommended
V2
7/9VoOH
-
Segment driver input supply voltage (2)
V3, V5
Value recommended
V3, V5
EI01. EI02.
GND
-
0.8Vee
-
-
-
High-level input voltage
VIH
DO to 03:
Vee = 3.0 to 5.5 V
Low-level input voltage
VIL
VOOH
2/9VoOH
-
Unit
V
V
V
V
V
SED1742
DO to 07:
SE01744
0.2Vee
V
XSCL.L~
SHL. FR.INH
High-level output voltage
VOH
Low-level output voltage
VOL
-
-
V
-
-
0.4
V
-
-
2.0
f.lA
EI01, EI02
-
-
5.0
f.lA
GND
-
-
25
f.lA
00 to
0159
-
0.9
2.5
-
1.0
3.0
Vcc = +5.0 V, VIH = Vcc.
VIL = GND, fxSCL =5.38 MHz,
fLP =33.6 kHz, fFR =70 Hz
Input data: Display
checkered, No load
Vce ~ -+3~0-V; -Other - - - - - conditions: same as
Vcc= +5.0 V
Vee
-
0.4
1.2
------
-- - - -
------
0.2
0.6
VDDH = VO = +30.0 V,
Vcc = +5.0 V, V3 = +4.0 V,
V2 = +26.0 V, V5 = 0.0 V;
Other conditions: same as
Vcc = +5.0 V
VOOH
-
0.5
1.5
mA
Freq.=1 MHz, Ta = 25°C
Single chip
DO to D3:
SED1742
DO 10 07:
-
-
8
pF
-
-
15
pF
Vcc = 3 to 5.S V
IOH = -0.6 mA
EI01. EI02
IOL = 0.6 mA
Vcc-O.4
DO to 03:
Low-level input
SE01742
Iu
GND
:0;
VIN :0; Vee
leakage current
Input: leakage current output
Static current
Output resistance
LP. FR. XSCL.
SHL.INH
IU/O
GND
IGNO
VOOH = 14.0 to 40.0 V
VIH = Vee, VIL = GND
RSEG
:0;
VIN:O; Vee
tNON
=0.5V
condition
recommended
Average Operation
current consumed (1)
Average Operation
current consumed (2)
Input capacitance
I/O terminal capacity
Notes:
DO to 07:
SED1744
lee
looH
CI
VooH=+30.0V
VOOH=+20.0V
1. The voltage is based at GND=OV.
2. Voltage Yo, V2, and V3 should satisfy the condition: VooH>Vo>V2>V3>Vs>GND
567
mA
SE01744
LP. FR. XSCL.
SHL.INH
EI01, EI02
CliO
kQ
I
SED1742144
• Operating Voltage Range VCC-VOOH
The maximum LCD supply voltage, VDDH depends on Vcc as shown in the following figure.
Specify the VDDH voltage within the VCC-VDDH operation.
(V)
VDDH
50
40
30
20
10
0
2.0
3.0
4.0
Vee
5.0
6.0
(V)
• AC Electrical Characteristics
o Input Timing Characteristics
FR
LP
XSCL
DO-D3: SED1742
DO-D7: SED1744
EI01,2
(IN)
______________________________~tSUE----.
Note: Adjust the timing of the LP pulse input at high-speed operation, excluding one clock of XSCL.
Parameter
XSCL cycle
Symbol
tWCH
XSCL low-level pulse width
twCL
Data setup time
tDS
Data hold time
tDH
XSCL _
tLD
LP -
XSCL breaking time
LP high-level pulse width (1)
(Vcc = 5 0 V -+10% , Ta = -20 to 75°C)
Min
Typ
Max
Unit
tc
XSCL high-level pulse width
LP rise time
Condition
tLH
twLH
FR delay allowance time
tDF
EIO setup time
tSUE
83
30
30
30
30
-
-
ns
-
-
ns
-5
60
45
-
-
ns
-
-
ns
-
-
ns
300
-
ns
-300
35
Note: tWLH defines the time duration when the LP is "H" and the XSCL is "L".
568
-
ns
ns
ns
ns
SED1742144
(Vcc
Parameter
Condition
Symbol
= 3.0 to 4.5 V, T a =-20 to 75°C)
Min
Typ
tc
125
-
XSCL high-level pulse width
tWCH
50
-
XSCL low-level pulse width
tWCL
50
-
Data setup time
tDS
50
Data hold time
tDH
XSCL _
tLD
tLH
LP -
LP rise time
XSCL breaking time
LP high-level pulse width (1)
FR delay allowance time
EIO setup time
Max
Unit
ns
-
-
30
-
-
ns
0
-
ns
120
-
tWLH
90
-
-
tDF
-600
-
600
ns
70
-
XSCL cycle
tSUE
-
ns
ns
ns
ns
ns
ns
Note: tWLH defines the time duration when the LP is "H" and the XSCL is "L"
o Output Timing Characteristics
I
FR
tFRSDLP
tER -.
l---tLSD-
XSCL
I-~
E101,2
(OUT)
K
SEG
(VCC
Parameter
EIO reset time
Symbol
tER
EIO output delay time
tDCL
LP -
tLSD
FR -
SEG output delay time
SEG output delay time
= +5.0 V -+10%, VDDH = 14.0 to 40.0 V)
Min
Condition
CL
CL
tFRSD
= 15 pF (EIO)
-
= 100 pF (On)
-
(VCC
Parameter
EIO reset time
EIO output delay time
Symbol
tER
tDCL
LP -
SEG output delay time
tLSD
FR -
SEG output delay time
tFRSD
Condition
CL
= 15 pF (EIO)
CL
= 100 pF (On)
569
Typ
Max
Unit
120
ns
-
45
ns
-
200
ns
-
400
ns
-
= 3.0 to 4.5 V, VDDH = 14.0 to 2B.0 V)
Min
-
-
Typ
Max
Unit
-
240
ns
-
72
ns
400
ns
BOO
ns
SED1742144
•
o
Timing Diagrams
1/240 Duty Cycle
240
239
2
4
x
Latch data -----.Jp--f''--.Ll--'--'----1.CL
240
X X X X -===---,X,-,--X,-,,---,-,-X_
r---+--------~
FR
239
____ JLJLJLJL.JL ____ ~
LP
----~
LP
--CD
EIOCD
-
J
®~
I
I
EIO@
---
l
-
Notes:
1. The circled numerals 1 to n denote the position of the device in the chain.
2. One cycle of XSCL should be lengthened tio satisfy tLH when high-speed data transfer takes place.
570
SED1742144
LP~
,
,
,
Latchdata~
FR
H,
L '
H :
: H
::!-,I - - - -
INH
VO
------"1"--_.-
I
I
I
. L __
"::.'tE
•. . . . . . . . . . . . . . . .• .•=E
'.• .• .•FE
.••. ••.••.••.• .••. ••. •. •. •. •. •.• •. • • • • • • .•.• . . . . . .
•
•
FUNCTIONAL DESCRIPTION
Enable Shift Register
The enable shift register is a bi-directional shift register, where the shift direction is selected by SHL. SHL is
also used to latch data from the data bus into the data register. The effect of SHL on the shift direction and
on the input data sequence is shown in the following table.
Data Sequence and Shift Direction
SHL
LCD Outputs
Shift Direction
0159
0158
0157
...
02
01
00
EI01
L
a
b
c
...
x
y
z
Output
Input
H
z
y
x
...
c
b
a
Input
Output
EI02
When the enable signal is inactive, the SED1742 is in standby mode with the internal clock stopped and the
data bus held LOW. When multiple SED1742s are used, the enable input of the first device should be
connected to ground and the enable input of each successive device should be connected to the enable
output of the preceding device.
When 160 data bits have been latched into the SED1742, the enable output edge goes LOW, eliminating the
need for an external control circuit.
•
Data Register
The data register converts the input data into parallel display driver data under the control of the enable shift
register.
571
I
SED1742144
•
•
APPLICATION NOTES
Voltage Levels
The recommended method of generating the LCD drive voltages, VO to VS, is with a voltage divider between
VODH and VGND, buffered with voltage followers.
The lower drive level, VS, is not necessarily at VGND, and separate pins are used for the voltage levels when
op-amps are used. A maximum voltage differential between VS and VGNO of 2.SV is recommended since the
driver efficiency decreases as the differential increases. Connect VS to GND when not using op-amps.
The resistances of the voltage divider resistors should be as low as possible and within power supply
constraints.
Note that fluctuations in IDDH can cause dips in the VDDH supply. The device will be damaged if the voltage
dips below the point where the relationship VDDH (VO) ~ V2 ~ V3 ~ VS ~ VGND breaks down. A stabilized power
supply may be required when using the resistor network.
•
Data Latch
The data latch latches the data into the level shifter on the falling edge of LP.
•
Level Shifter
The level shifter converts the logic-level signals from the latch into the LCD driver input voltage levels.
•
LCD Drivers
The LCD drivers generate the AC LCD drive waveforms. The output voltages are determined by the polarity
of the FR signal, as shown in the following table.
Driver Output Voltage
INH
Input Data
H
H
L
L
X
x = don'! care
S72
FR
Output Voltage
H
VO (VDDH)
L
VS
H
V2
L
V3
X
VS
SED1742144
•
Power-Up and Power-Down Precautions
As the driver circuitry operates at high voltage, care should be taken when applying and removing power to
the SED17 42 to prevent damage. If the driver supply is applied when the logic supply is either not connected
or below 2.9V, excess current will flow into the SED1742 and damage the device. Normal operation is
guaranteed if the correct power-up and power-down sequences are followed.
Power-Up Sequence:
Power should be applied to Vee before, or at the same time as, power is applied to the driver circuitry.
Power-Down Sequence:
Power should be removed from Vee after, or at the same time as, power is removed from the driver
circuitry.
The SED1742 can also be damaged if the LCD output drivers start operating before the driver supplies
stabilize. INH should be held LOW to hold the driver outputs at V5 until the driver supplies have stabilized.
As an extra precaution, insert a fast-blow fuse in series with the driver supply.
I
573
SED1742144
•
PAD LAYOUT FOR SED1742D18
140
o
o
o
o
o
o
o
o
o
o
130
110
120
100
90
000000000000000000000000000000000000000000000000000000DOODDD
o
o
o
150 0
o
o
o
o
o
o
o
01742018
160 0
o
o
o
L
o
o
o
o
o
170
o
(0,0)
o
o
o
0
o
70
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
180 0
o
o
o
80
o
o
o
o
o
o
o
o
o
o
o
o
o
60
o
00000000000000000000000000000000000000000000000000000 0
10
20
30
40
50
Chip Size ., ... " ... " ...... 7,30mm x 4.48mm
Chip Thickness ".,., ... 5251lm ± 251lm
Pad Pitch ,.... ,.... ,... ,... 1081lm (Min.)
Gold bump dimensions (SED1742D1 B):
Size A .. " ... 94 x 134 ± 20llm (pads 1-15, 39-183)
Size B ... " .. 115 x 148 ± 20llm (pads 16-33, 38)
Size C ." .... 115 x 134 ± 20llm (pads 34-37)
unit: Ilm
•
PAD COORDINATES
No.
1
2
3
4
5
6
7
8
9
10
11
12
Pad
Name
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
Coordinates
X
Y
-3228
-2064
-3120
-2064
-3012
-2064
-2903
-2064
-2795
-2064
-2687
-2064
-2578
-2064
-2470
-2064
-2362
-2064
-2253
-2064
-2145
-2064
-2037
-2064
No.
13
14
15
16
17
18
19
20
21
22
23
24
Pad
Name
0157
0158
0159
EI02
EI01
GNO
00
01
02
03
NC
NC
Coordinates
X
Y
-1929
-2064
-1820
-2064
-1712
-2064
-1550
-2058
-1417
-2058
-1284
-2058
-1151
-2058
-1018
-2058
-885
-2058
-752
-2058
-2058
-619
-486
-2058
574
No.
25
26
27
28
29
30
31
32
33
34
35
36
Pad
Name
NC
NC
SHL
XSCL
TEST
INH
LP
Vee
FR
V5
V3
V2
Coordinates
X
Y
-353
-2058
-220
-2058
-87
-2058
46
-2058
179
-2058
312
-2058
445
-2058
578
-2058
711
-2058
872
-2026
1034
-2026
1195
-2026
SED1742144
Pad
Coordinates
Pad
No.
Name
X
Y
No.
Name
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
VO
VDDH
1357
1550
1712
1820
1929
2037
2145
2253
2362
2470
2578
2687
2795
2903
3012
3120
3228
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
-2026
-2058
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-1841
-1733
-1625
-1516
-1408
-1300
-1191
-1083
-975
-866
-758
-650
-542
-433
-325
-217
-108
0
108
217
325
433
542
650
758
866
975
1083
1191
1300
1408
1516
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
Coordinates
X
3474
3474
3474
3195
3087
2978
2870
2762
2553
2545
2437
2328
2220
2112
2004
1895
1787
1679
1570
1462
1354
1245
1137
1029
921
812
704
596
487
379
271
162
54
-54
-162
-271
-379
-487
-596
-704
-812
-921
-1029
-1137
-1245
-1354
-1462
-1570
-1679
575
Pad
Coordinates
Y
No.
Name
X
Y
1625
1733
1841
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
096
097
098
099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
-1787
-1895
-2004
-2112
-2220
-2328
-2437
-2545
-2653
-2762
-2870
-2978
-3087
-3195
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
1841
1733
1625
1516
1408
1300
1191
1083
975
866
758
650
542
433
325
217
108
0
-108
-217
-325
-433
-542
-650
-758
-866
-975
-1083
-1191
-1300
-1408
-1516
-1625
-1733
-1841
I
SED1742144
•
PAD LAYOUT FOR SED1744D1B
140
o
130
110
120
90
100
000000000000000000000000000000000000000000000000000000000000
150 0
o
o
o
017441B
o
o
o
o
o
o
160 0
o
o
o
o
o
o
L
o
o
170
(0,0)
o
0
o
o
o
o
o
o
o
o
o
180 0
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
80
70
60
00000000000000000000000000000000000000000000000000000 0
10
20
30
40
50
Chip Size .................. 7.30mm x 4.48mm
Chip Thickness ......... 525f.lm
± 25f,tm
Pad Pitch .................. 108f,tm (Min.)
Gold bump dimensions (SED1744sD1 B):
Size A ....... 94 x 134 ± 20f,tm (pads 1-15, 39-183)
Size B ....... 115 x 148 ± 20f,tm (pads 16-33, 38)
Size C ....... 115 x 134 ± 20f,tm (pads 34-37)
unitf,tm
•
PAD COORDINATES
No.
1
2
3
4
5
6
7
8
9
10
11
12
Pad
Name
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
Coordinates
X
Y
-3228
-2064
-3120
-2064
-3012
-2064
-2903
-2064
-2795
-2064
-2687
-2064
-2578
-2064
-2470
-2064
-2362
-2064
-2253
-2064
-2145
-2064
-2037
-2064
No.
13
14
15
16
17
18
19
20
21
22
23
24
Pad
Name
0157
0158
0159
EI02
EI01
GNO
00
01
D2
D3
D4
05
Coordinates
Y
X
-2064
-1929
-2064
-1820
-1712
-2064
-2058
-1550
-1417
-2058
-1284
-2058
-1151
-2058
-1018
-2058
-2058
-885
-752
-2058
-619
-2058
-2058
-486
576
No.
25
26
27
28
29
30
31
32
33
34
35
36
Pad
Name
06
07
SHL
XSCL
TEST
INH
LP
Vee
FR
V5
V3
V2
Coordinates
X
Y
-353
-2058
-220
-2058
-2058
-87
46
-2058
179
-2058
312
-2058
445
-2058
578
-2058
711
-2058
872
-2026
1034
-2026
1195
-2026
SED1742144
Pad
Coordinates
Pad
Pad
Coordinates
Coordinates
No.
Name
X
Y
No.
Name
X
Y
No.
Name
X
Y
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
VO
VDDH
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
1357
1550
1712
1820
1929
2037
2145
2253
2362
2470
2578
2687
2795
2903
3012
3120
3228
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
3474
-2026
-2058
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-2064
-1841
-1733
-1625
-1516
-1408
-1300
-1191
-1083
-975
-866
-758
-650
-542
-433
-325
-217
-108
0
108
217
325
433
542
650
758
866
975
1083
1191
1300
1408
1516
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
3474
3474
3474
3195
3087
2978
2870
2762
2553
2545
2437
2328
2220
2112
2004
1895
1787
1679
1570
1462
1354
1245
1137
1029
921
812
704
596
487
379
271
162
54
-54
-162
-271
-379
-487
-596
-704
-812
-921
-1029
-1137
-1245
-1354
-1462
-1570
-1679
1625
1733
1841
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
096
097
098
099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
-1787
-1895
-2004
-2112
-2220
-2328
-2437
-2545
-2653
-2762
-2870
-2978
-3087
-3195
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
-3474
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
2064
1841
1733
1625
1516
1408
1300
1191
1083
975
866
758
650
542
433
325
217
108
0
-108
-217
-325
-433
-542
-650
-758
-866
-975
-1083
-1191
-1300
-1408
-1516
-1625
-1733
-1841
577
I
SED1742144
•
SED1742 TAPE-CARRIER PACKAGE
•
Tape-Carrier Pinout
EI02
EI01
GNO
DO
01
02
03
04
05
06
07
SHL
XSCL
TEST
INH
LP
Vee
FR
V5
V3
V2
VO
VDDH
o
159
0
158
0
157
o
o
155
o
o
o
o
578
156
3
2
1
0
SED1742144
•
Tape-Carrier Dimensions
:±:
x
1-------~·0+9£----_+-------------__I
o
o
o
o
8L·0
'"
0
0
+1
-
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II
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579
SED1742144
•
SED1744 TAPE-CARRIER PACKAGE
•
Tape-Carrier Pinout
o
o
o
o
o
EI02
EI01
GNO
00
01
02
03
04
05
06
07
SHL
XSCL
TEST
INH
LP
Vee
FR
V5
V3
V2
VO
VOOH
o
o
o
o
580
159
158
157
156
155
3
2
1
0
SED1742144
•
Tape-Carrier Dimensions
1:
x
I<------~"Of
98------1----------------I
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..... 1 0
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I
THIS PAGE INTENTIONALLY BLANK
582
SED1748
LOW-POWER 160-BIT LCD SEGMENT DRIVER
•
DESCRIPTION
The SED1748 is a 160-bit dot matrix LCD segment (column) driver for driving high-capacity LCD panels at
duty cycles higher than 1/100 (up to 1/500). The LSI features a wide range of LCD drive voltages. The upper
and lower LCD drive voltages (VO, V5) are independent of the chip supplies. This enables the LCD drive bias
voltages to be supplied from an external source. The device uses a daisy-chain enable system which
decreases power consumption and eliminates the need for separate signals for each driver.
The SED1748 is used in conjunction with the SED1743 (160-bit common driver) to drive a large-capacity dot
matrix LCD panel.
•
FEATURES
• Low-power, high-speed CMOS technology
• 160-bit segment (column) driver
• Ability to adjust offset bias of the LCD source
from Voo
• High-speed 8-bit data bus
• High-speed daisy chain enable support
• Duty cycle ............................. 1/100 to 1/500
• Adjustable offset bias of the liquid crystal according to the VO and GND
• Adjustable LCD drive voltages
• Wide range of LCD voltages ........... 8 to 42V
• Unbiased display off function
• Supply voltage ............................ 2.7 to 5.5V
• Adjustable offset bias of the LCD according to
VooHand GND
• Package ............................... Au bump (DOB)
TAB (TOA)
• Shift clock frequency16MHz max at Voo = 5V
•
SYSTEM BLOCK DIAGRAM
DO- D7
XSCL
LCD
CONTR
LP,FR
YSCL
~
'l
SED1748
i
1
~~
~6~
ISED1743~
l
•
SED1743 [
J--
160
SED1748
320 SEG x 480 COM
DUTY: 1/480
+
ISED1743~
583
I
SED1748
•
BLOCK DIAGRAM
00······ ···································0159
VO
LCD driver: 160-bits
V5
V2
V3
Level shifter: 160-bits
FR
DSPOF
LP
Latch: 160-bits
Vee
GND
DO-D7
XSCL
EI01
Bidirectional Shift Register
584
SHL
EI02
SED1748
•
•
BLOCK DESCRIPTION
Enable Shift Register
The enable shift register is a bi-directional shift register, where the shift direction is selected by SHL. When
the enable signal is inactive, the SED1748 is in standby mode, where the internal clock is stopped and the
data bus held LOW. When multiple SED1748s are used, the enable input of the first device should be
connected to ground and the enable input of each successive device should be connected to the enable
output of the preceding device. When 160 data bits have been latched into the SED1748, the enable output
goes LOW, eliminating the need for an external control circuit.
•
Data Register
The data register converts the input data into parallel display driver data under the control of the enable
shift register.
•
Data Latch
The data latch latches the data into the level shifter on the falling edge of LP.
•
Level Shifter
The level shifter converts the logic-level signals from the latch into the LCD driver input voltage levels.
•
LCD Drivers
The LCD drivers generate the AC LCD driver waveforms. The output voltages are determined by the polarity
of the FR signal, as shown in the following table:
DSPOF
Input Data
H
H
L
L
-
FR
H
L
H
L
-
Output
Voltage
VO
V5
V2
V3
V5
585
I
SED1748
•
PIN DESCRIPTION
No. of
Pins
Pin Name
I/O
Function
00 to 0159
0
DO to 07
I
Display data input
8
XSCL
I
Display data shift clock input (trailing edge triggered)
1
LP
I
Display data latch clock input (trailing edge triggered)
1
E101, EI02
I/O
Enable 1/0
2
LCD driver segment (column) output
The output changes with the LP's trailing edge.
160
• Configured by SHL.
• Output is reset to "H" by LP input. When the 160-bit display data is read,
the output falls to "L" automatically.
SHL
I
Shift direction and input/output select input
1
• If the display data is entered in the input (DO, 01, ... , 07) in the order of
(aO, a1, ... , a6, a7) (bO, b1, ... , b6, b7), ..... , (to, t1, ... , t6, t7), the
relationship of the display data and the segment output is as given in the
table below.
SHL
L
H
EIO
Output
157
...
2
1
aO
158
a1
a2
...
t5
t7
t6
t5
...
a2
159
1
2
t6
0
t7
0
I
a1
aO
I
0
FR
I
LCD AC driver signal input
1
Vee,GND
Power
supply
Logic power input
GND: OV, Vee: +3.3V, +5V
2
YO, V2,
V3, V5
Power
supply
LCD driver power input
GND: OV, VO: +14 to +42V
VO ~ V2 ~ 7/9 x VO
219 x VO ~ V3 ~ V5 ~ GND
4
DSPOF
I
Compulsion bias input
1
When the "L" level, the output is compelled to the V5 level.
* If you use this function, you cannot use to combine with the SED1703.
586
SED1748
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Unit
Supply voltage 1
Vee
-0.3 to +7.0
V
Supply voltage 2
VO
--0.3 to +45.0
V
Supply voltage 3
VO,V2,V3, V5
GND - 0.3 to VO + 0.3
V
Input voltage
VI
GND - 0.3 to Vee + 0.3
V
Output voltage
VO
GND - 0.3 to Vee + 0.3
V
EIO output voltage
101
20
rnA
Parameter
Operating temperature
TOPR
-30 to +85
°C
Storage temperature 1
TSTG1
-65 to +150
°C
Storage temperature 2
TSTG2
-55 to +100
°C
Notes:
1. All voltages are given relative to GND =
av.
2. For storage temperature 1 - Die
For storage temperature 2 - TAB mounted
3.
va, V2, and V3 must satisfy the condition Voo ~ va ~ V2 ~ V3 ~ V5 ~ VEE
va
V2
42V
V3
VCC
V5
5V
GND
GND
4. This LSI has high LCD driver voltage. As a result, if the logic power is being floated and Vcc ::; 2.6V in the LCD driver, the
LSI may be damaged because of the excess current.
587
I
SED1748
•
DC Electrical Characteristics
Parameter
Symbol
Supply voltage (1)
Vcc
Recommended
operating voltage
VO
Operation voltage
VO
Supply voltage (2)
Supply voltage (3)
High-level input current
VIH
Low-level input current
V,l
High-level output current
VOH
Low-level output voltage
Val
Conditions
Pin Name
Min
Typ
Max
Unit
Vcc
2.7
-
5.5
V
VO
14.0
-
40.0
V
VO
8.0
42.0
V
V2
V2
7/9 x VO
V3
V3
GNO
-
0.8 x Vcc
-
Function
E101, E102,
FR,00to07,
XSCL, SHL,
LP,OSPOF
I 10H = 0.6mA
I 10l= 0.6mA
Vcc=
2.7 to
O.ov
E101, EI02
-
V
2/9 x VO
-
V
V
-
0.2 xVcc
-
-
V
-
0.4
V
Vcc - 0.4
V
Input leakage current
III
GNO :;; Y,N :;; Vcc
00to07, LP,
FR, XSCL,
SHL, OSPOF
-
-
2.0
IlA
Input/output leakage
current
ILiIO
GNO :;; VIN :;; Vcc
E101, EI02
-
-
5.0
IlA
Quiescent current
IGND
VO = 14.0 to 42.0V
V,H = Vcc, V,l = GNO
GNO
-
-
25
J.lA
00 to 0159
-
00 to 0159
-
-
90
Q
Vcc = +5.0V, V,H = Vcc,
V,l + GNO, fXSCl =
5.38MHz, flP=33.6KHz,
fFR = 70Hz, Input data:
Shimatsu display, no
load
Vcc
-
0.5
1.1
mA
Vcc = +3.0V, other conditions as above
Vcc
-
0.2
0.6
mA
0.15
0.9
mA
Segment ON
resistance
Oeviation in chip
ON resistance
Operating current (1)
RSEG
Ll.RsEG
Icc
I
LI. VON VO = +36.0V, 1/24
I
=0.5V VO = +26.0V, 1/20
Ll.VON =0.5
VO = +36.0V, 1/24
0.62
1.9
0.68
2.0
KQ
Operating current (2)
10
VO=+30.0V, Vcc=+5.0V,
V3 = +4.0V, V2 = +26.0V,
V5 = O.OV, other conditions as for Icc
VO
-
Input capacitance
C,
Freq. = 1MHz, Ta = 25°C
chip package
OOto 07, LP,
FR, XSCL,
SHL,OSPOF
-
-
8
pF
E101, EI02
-
-
15
pF
Input/output capacitance
CliO
588
SED1748
•
Operating Voltage Range for Vee and VO
Va
(V)
50
42
40
30
28
20
10
o
2.0
2.7 3.0
5.0
4.0
Vee
589
(V)
6.0
I
SED1748
•
o
AC Electrical Characteristics
Input Timing
FR
LP
XSCL
DO - D7
EI01,2
_ _ _ _ _ _"'~.---- tSUE - - - - - . j . !
(IN)
VCC
Parameter
XSCL cycle time
=5.0V ± 10%, T a =-30 to 85°C
Symbol
Conditions
Min
tc
tr, tl:::; 11 ns
62
ns
40
35
-
ns
+300
ns
tWCH
20
XSCL low-level pulse width
twCl
20
Data setup time
tos
10
Data hold time
tOH
10
LP rising edge
tlO
-5
XSCL falling edge
tlH
30
LP
~
~
LP high-level pulse width
tWlH
Unit
-
XSCL high-level pulse width
XSCL
Max
ns
ns
ns
ns
ns
ns
ns
FR phase difference
tOF
-300
EIO setup time
tSUE
30
-
ns
Input signal change time
tr, fl
-
50
ns
VCC
Parameter
=2.7 to 4.5V, Ta =-30 to 85°C
Symbol
Conditions
Min
tc
tr, tl:::; 15ns
100
Max
Unit
XSCL high-level pulse width
tWCH
35
XSCL low-level pulse width
twCl
35
-
Data setup time
tos
15
-
ns
Data hold time
tOH
10
ns
~
LP rising edge
tlO
-10
XSCL falling edge
tlH
60
75
-
65
-
ns
XSCL cycle time
XSCL
LP
~
LP high-level pulse width
twlH
ns
ns
ns
ns
ns
ns
tOF
-300
EIO setup time
tSUE
40
-
ns
Input signal change time
tr, fl
-
50
ns
FR phase difference
590
+300
ns
SED1748
o
Output Timing
FR
0.8 x Vee
0.2 x Vee
----------------£tFRSD-
LP
XSCL
0.8 xVee
0.2 x Vee
EI01,2
(OUT)
Vn- 0.5
Vn + 0.5
SEG
Vcc = 5.0V
Parameter
± 10%, VO = 14.0 to 42.0V
Symbol
Conditions
Min
Max
EIO reset time
tER
-
120
ns
EIO output delay time
tDCL
CL = 15pF
(EIO)
-
45
ns
CL = 100pF
(On)
-
200
ns
-
400
ns
LP
-?
SEG delay time
tLSD
FR
-?
SEG delay time
tFRSD
VCC
Unit
=2.7 to 4.5V, VO = 14.0 to 28.0V
Symbol
Conditions
Min
Max
EIO reset time
tER
-
ns
tDCL
CL = 15pF
(EIO)
240
EIO output delay time
85
ns
400
ns
800
ns
Parameter
LP
-?
SEG delay time
tLSD
FR
-?
SEG delay time
tFRSD
CL = 100pF
(On)
591
Unit
I
SED1748
•
o
Timing Diagrams
1/240 Duty Cycle
x
DATA
FR
X
X
X
X
X
X
X
X
I
---------------- - - - - - - - - - - - - - --
- - - - - - --,
-
LP
~*~------------------------------------~n~---
XSCL
nlsLn:JL---~---SLJLJLJL---JliSLJ
,
'
,
X
20
DO - D7
1
X
2
:.
EIOG)
---J
EIO®
~
X
3
I
~~'~~~~~
G)
X 20 X
1
2
®
.'.
X
3 ---
I
X 20 X
.,
1
X
2
X
-~~~--~
3
---
X
20
X
1
LJ
LP
LATCH
DATA
FR
~)
~)
~»
,
,
~)
,
H'
I
:
,
'L?)
,
,
,
~
)
: H
H
DSPOF
V'J
V2
V3
V5
f - :-: - ;- -- :- )±--------------- : : : -: : :-: : : :
::::::- - ~-----:
':::::-i- :--- -
-~'-:-
-------- -- ---)------------ ------ ----------- -------
-------------
~
-)
-- - --
---
-------
-
- --
------
NOTES:
CD
1. The circled numerals
to@ denote the position of the device in the chain.
2. When transferring data at high speed, one cycle of XSCL must be lengthened to satisfy tLH.
592
-
X
SED1748
•
•
LCD DRIVER POWER SUPPLY
Generating LCD Driver Voltage
To obtain individual voltage levels for LCD driver, register-split the potential between VO-GND and drive the
LCD with the voltage follower using the operation amplifier. When using the operation amplifier, V5 and GND
are separated. However, if the potential of V5 is higher than the GND potential and the potential difference
increases, the LCD driver capability decreases. To above this, set V5 and GND within the range from a to
2.5V. If an operation amplifier is not used, connect V5 and GND. If there are direct resistors on the va (GND)
power line, voltage falls in va (GND) at the LSI power pins. This is caused by 10 at the time of signal change.
As a result, the relationship (Va ~ V2 ~ V3 ~ V5 ~ GND) for intermediate potential of LCD cannot be maintained
and the LSI may be damaged.
To insert a protective resistor, the voltage must be stabilized according to the capacity.
•
Power-Up/Power-Down Sequence
This LSI has high LCD driver voltage. As a result, if the logic power is being floated and Vcc:s:; 2.6V is applied
in the LCD driver, the LSI may be damaged because of the excess current.
Until the LCD driver voltage is stabilized, use the display off function (DSPOF) to set the potential of the LCD
drive output to V5 level.
Follow the sequence given below when turning the power on/off.
To turn on the power:
I
1. Turn on the logic power
2. Turn the LCD driver on
(or turn them on simultaneously)
To turn off the power:
1. Turn off the LCD driver
2. Turn off the logic power
(or turn them off simultaneously)
To avoid excess current, insert the high-speed fuse in series with the LCD power. Selectthe appropriate value
for a protective resistor according to the capacity of an LCD cell.
593
SED1748
•
TYPICAL APPLICATION
V5
V4
V3
V2
V1
VO
VDU------i
===;:r:t=:l
VSCL
DSPOF
SHL--rt-H.L!.Lj
640 X 480 DOT
(VOL) --++-H--I
(1/240 DUTY)
11480 DUTY
FR--+t-H-I
594
SED1748
•
PAD LAYOUT
160
150
140
120
130
110
100
90
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
170
El
El
El
El
El
D
El
El
D
El
El
D
D
D
El
El
D
D
180
D
~~
§
200
El
D
§
§
§
§
D
D
D
El
El
D
D
D
D
El
El
D
204 LEl=-_----=D::.:D::.:D::.:D::.:D::.:D::.:D=.D=D=D=D=D=D=D=Dc::Dc::Dc::D:=D:=D:=D:.=D:.=D:.=D::.;:D::.;:D:.:D:.:D:.:D::..:D::.:D::.:D::.:D::.:D::.:D=.D=.D=.D=.D=D=D=D=D=D_D_'7.....:48_Doe-=.JEl
20
10
30
40
Chip size .................. 7.30mm x 4.48mm
Pad pitch ................. 81.7l1m (Min.)
Chip thickness ......... 52511m ± 2511m
1) Au bump dimensions (SED1748DoB)
• Size A : 97Jlm x 88Jlm
• Size B : 82Jlm x 80Jlm
ro
§
El
D
190
80
± 4Jlm (pads 1 to 44)
± 4Jlm (pads 45 to 48,
66 to 81, 168 to 183, 201 to 204)
• Size C : 82Jlm x 70Jlm ± 4Jlm (pads 49 to 65, 184 to 200)
• Size D : 65Jlm x 164Jlm ± 4Jlm (pads 82 to 85, 164 to 167)
• Size E : 53Jlm x 164Jlm ± 4Jlm (pads 86 to 163)
595
60
~
I
SED1748
•
PAD COORDINATES
No.
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
GNO
GNO
EJ02
EI02
FR
FR
OSPOFF
OSPOFF
LP
LP
XSCL
XSCL
00
00
01
01
02
02
03
03
D4
D4
05
D5
D6
D6
D7
D7
EI01
EI01
SHL
SHL
NC
NC
Vee
Vee
V5
V5
V3
V3
V2
V2
VO
VO
00
01
02
03
04
05
06
07
08
09
y
X
Coord.
Coord.
-2757
-2630
-2500
-2373
-2244
-2117
-1987
-1860
-1731
-1604
-1474
-1347
-1218
-1091
-961
-834
-705
-578
-448
-321
-192
-{)5
65
192
321
448
578
705
834
961
1091
1218
1347
1474
1604
1731
1860
1987
2117
2244
2373
2500
2630
2757
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2080
-2055
-2055
-2040
-2040
-2024
-2024
-2009
-2009
-2088
-1978
-1868
-1758
-1652
-1551
-1451
-1350
-1249
-1149
UnitJ.Lm
No.
Pin Name
X
Coord.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
B4
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3492
3512
3419
3326
3233
3145
3064
2982
2900
2819
2737
2655
2574
2492
2410
2328
2247
2165
2083
2002
1920
1838
1757
1675
1593
1511
1430
1348
y
Coord.
-1048
-947
-846
-745
-645
-544
-444
-343
-242
-142
-41
65
175
285
395
505
616
726
836
946
1056
1167
1277
1387
1497
1607
1718
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
y
No. Pin Name
X
Coord.
Coord.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
1266
1185
1103
1021
940
858
776
694
613
531
449
368
286
204
123
41
-41
-123
-204
-286
-368
-449
-531
-{)13
-694
-776
-858
-940
-1021
-1103
-1185
-1266
-1348
-1430
-1511
-1593
-1675
-1757
-1838
-1920
-2002
-2083
-2165
-2247
-2328
-2410
-2492
-2574
-2655
-2737
-2819
-2900
-2982
-3064
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
2051
596
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
No.
Pin Name
X
Coord.
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
-3145
-3233
-3326
-3419
-3512
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
-3492
y
Coord.
2051
2051
2051
2051
2051
1718
1607
1497
1587
1277
1167
1056
946
836
726
616
505
395
285
175
65
-41
-142
-242
-343
-444
-544
-{)45
-746
-846
-947
-1048
-1149
-1249
-1350
-1451
-1551
-1652
-1758
-1868
-1978
-2088
SED1748
•
EXTERNAL PACKAGE DIAGRAM
o
"'
C!G:!"":
~oo
~~~
:;:;:;
ttF
MAX 1.5
Q
l
MAX 1.5
g
+
x
D
D
I
D
~------~------~pp
28.97~
~I
O.025:tMD6
597
THIS PAGE INTENTIONALLY BLANK
598
(PRELIMINARY)
SED1752ToA
CMOS LCD SEGMENT DRIVER
•
DESCRIPTION
The SED1752 Series is a single-chip LCD driver for high-capacity color dot-matrix STN liquid crystal display
(LCDs). It incorporates 240 segment (column) driver outputs and is designed for use in conjunction with the
SED1743 common (row) driver.
The SED1752 uses a daisy-chain enable system which decreases power consumption and eliminates the
need for separate enable Signals for each driver.
•
FEATURES
• 240 LCD segment drive outputs
.8-bitdata
• Adjustable LCD drive voltage relative to ground
and VDDH
• Wide +8 to +42 voltage of LCD drive voltages
(Vee = 3 to 5.5V)
• Zero-bias display disable function
• Daisy-chained inpuVoutput enables
• Tape-carrier package
TOA ....... Slim TAB (9.3mm)
• 2.7 to 5.5V supply
• Low-power, high-speed data transfer - 20MHz
clock frequency at Vee = 5V ± 10% and 10MHz
clock frequency at Vee = 2.7V.
TOB ....... Ultra Slim TAB (7.3mm)
• Duty cycles up to 1/500
•
SYSTEM BLOCK DIAGRAM
00-07
XSCL
LCD
CONTR
LP,FR
YSCL
t---
il
SE01752
:
•
..
ISE01753~
•~
640x3x480
COLORSTN
599
SE01752
~4~
~~
ISE01753
:
I
SED1752ToA
•
BLOCK DIAGRAM
0240
VDDHL
VOL
V2L
V3L
V5L
01
I
~--
LCD driver
240 bit
~-~----~~
VDDHR
VOR
V2R
V3R
V5R
FR
DSPOF
LP
Vcc
GNDL
DO-D7
XSCL
EI02
•
•
GNDR
¢==~I=====:J
~
~ Bidirectional Shift Register I-+-~~O ~~1
E
FUNCTION OF EACH BLOCK
Enable Shift Register
The enable shift register is a bidirectional shift register of which the shift direction is being selected by the SHL
input and the shift register output is used to store data bus signals into the data register.
When the enable signal is in disabled state, the internal clock signal and the data bus are fixed to "L", thus
going into a power saving mode.
When using a multiple number of segment drivers, make cascade connections of EIO terminals of respective
drivers to connect the EIO terminal of the top driver to "GND". Since the enable control circuit automatically
senses completion of receiving 240 bit equivalent data to transfer the enable signal automatically, control
signal of a separate control LSI is not needed.
•
Data Register
This register works to make sseries or parallel conversion of data bus signals according to the enable shift
register output. Consequently, the relations between the serial display data and segment outputs are
determined independent from the number of the shift clock inputs.
•
Latch
It takes in the content of the data register at the falling edge trigger to transfer the output to the level shifter.
600
SED1752ToA
•
Level Shifter
---
DSPOF
This is a level interface circuit to convert the
voltage level of signals from the logic operation
level to LCD drive level.
Data Bus
Signals
H
H
•
LCD Driver
L
It outputs the LCD driving voltage.
--
L
FR
Voltage
Outputs of
the Driver
H
Vo
L
V5
H
V2
L
V3
--
V5
In the table to the right are the relations between
data bus signals, alternating current signal FR
levels and segment output voltages.
•
Timing Diagram
In case of 1/240 Duty (an example)
240
239 240
Latch Data
f - - t - - - - - - - ____
LP
XSCL
DO to 07
x XXXX
__~~~~~-u--u--
FR
239 240
____ JLJUVLJL ____ ~
LP
--:-30=---".,-,,,,,,,r:-
XX X
--.-J
.---r-nn----r-nn----J1f--fl-J
X 30X
1
X2 X 3 -- X30X
("
1
X 2 X 3 --- X 30 X
CD to @ stands for the cascade numbers of the driver.
* When making high speed data transfer, it becomes necessary to secure
a longer XSCL cycle when determining the LP pulse insertion timing in order
to maintain the specified value of LP --> XSCL (tLH).
LP
Latch Data
FR
nnnn
----' f---1 f---1 f---1 Y I
~I
~I
~I1/
,
H
L
II
/I
,
'H
H
L
DSPOF
601
X
Jr----
-I
®
1
I
SED1752ToA
•
PIN DESCRIPTION
Pin Name
01 - 0240
0
Number
of Pins
Description
I/O
LCD driving segment (column) output.
240
The output varies at the falling edge of LP.
DO - 07
I
Display data input terminals
8
XSCL
I
For input of the shift clock signals of the display data (falling edge
trigger)
1
LP
I
For input of the latch pulse signals of the display data (falling edge
trigger)
1
Enable 1/0.
2
EI01
EI02
I/O
Setting to I or 0 is determined by the SHL input level.
The output is reset by the LP input and when 240 bit equivalent data
are received, it falls to "L" automatically.
SHL
I
Shift direction selection and EIO terminal I/O control signal input.
1
When data are input to terminals Do, 0" ... , 07 in the order of Fa, F"
... , F7first, and in the order of LO, L 1, outputs are as follows:
F (First), L(Last)
EIO
Output
SHL
0240
0239
0238
L
LO
L1
L2
H
F7
F6
F5
(Note)
03
02
01
EI01
EI02
...
F5
F6
F7
Input
Output
...
L2
L1
LO
Output
Input
The relations between the data and segment outputs are
determined independently from the number of the shift
clocks.
Vee, GNDL,
GNDR
Power
supply
Logic operation power supply: GND: OV
Vee: +3.3, +5V
VDDHL, VDDHR
Power
supply
LCD drive circuit power supply VDDH
VOL, VOR
LCD drive circuit power supply VA
V2L, V2R
LCD drive circuit power supply V2
V3L, V3R
LCD drive circuit power supply V3
GND: OV
VOOH: 14-42V
VOOH?Vo?Vi27/9Vo
2/9Vo?,V3?,V5?GND
10
LCD drive circuit power supply Vs
V5L, V5R
DSPOF
2
I
1
For forced bias fixed input.
"L" level output is forcefully made to Vs level.
* When using this function, combined use with SED1703 is not
applicable.
Total
602
268
SED1752ToA
•
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Supply voltage (1)
Vee
-0.3 to +7.0
V
Supply voltage (2)
VDDH
-0.3 to +45.0
V
Supply voltage (3)
Vo, V2, V3, V5
-0.3 to VDDH + 0.3
V
Input voltage
VI
-0.3 to Vee + 0.3
V
Output voltage
Vo
-0.3 to Vee + 0.3
V
101
20
mA
Working temperature
TOPR
-30 to +85
Storage temperature
TSTG
-55 to +100
DC
DC
EIO output current
Notes:
1. All the voltage ratings are based on GND =
av.
2. The storage temperature 1 is applicable to independent chips and the storage temperature 2 is applicable to the TCP
modular state.
3. Va, V2, V3 and Vs should always be in the order of VDDH
~
Va ~ V,
~
V3 ~ Vs ~ GND.
VDDH
VO
V2
42V
V3
V5
Vee
5V
GND
4.
GND
If the logic operation power goes into a floating state or if Vee drops to 2.6V or below while the LCD driving power is
being applied, the LSI may be damaged. Therefore, keep from occurrence of the aforementioned status.
Specifically, pay close attention to the power supply sequence at times of turning the systern power on and off.
603
I
SED1752ToA
•
ELECTRICAL CHARACTERISTICS
•
DC Characteristics
Unless otherwise specified, GND = Vs = 0, Vcc = +5.0V ±10%,
Ta =-30 to ±85°C
Parameter
Symbol
Applicable
Pin
Condition
Min
Supply voltage (1)
Vee
2.7
VO
-
Vee
Recommended working
voltage
VOL, VDDHL
14.0
Typ
-
Workable voltage
VO
Function only
VOR, VDDHL
Supply voltage (2)
V2
Recommended value
V2L,V2R
7/9 Va
Supply voltage (3)
V,
Recommended value
V3L,V3R
GND
-
High level input voltage
V,H
VDD= 2.7-5.5V
0.8 Vee
-
Low level input voltage
V,L
E101, E102, FR
DO-D7, XSCL
SHL, LP,
DSPOF
High level output vOltage
VOH
E101, EI02
Vec-O.4
Low level output voltage
VOL
Input leak current
I/O leak current
III
ILllo
Vee =
2.75.5V
I
I
10H =-0.6mA
GND
~ VIN~
GND
Static current
IGND
Va = 14.0 - 42.0V
V,H = GND, V,L = GND
Output resistance
RSEG
/l,.VON
Va= +36.0V,
=0.5V
1/24
Recom- Va= +26.0V,
mended 1/20
condition
/l,.VON = 0.5V
Va = +36.0V, 1/24
In-chip deviation 01 output
resistance
Mean working current
consumption (1)
/l,.RsEG
Icc
I/O terminal capacity
C,iO
Freq. = 1 Mhz
Ta = 25°C
Independent
chips
V
2/9 Va
V
0.2Vee
V
V
-
V
V
DO-D7, LP, FR
XSCL, SHL
DSPOF
-
-
2.0
~
E101, EI02
-
-
5.0
25
IlA
IlA
Kn
-
0.65
0.85
-
0.70
1.0
-
-
95
n
mA
0.75
1.7
-
0.3
0.9
VOL, VOR
-
0.25
1.4
mA
DO-D7, LP, FR
XSCL,SHL, DSPOF
-
-
8
pF
EI01, EI02
-
-
15
pF
Vee
Vee = +3.0V
Other conditons are the
same as those when
Vee + 5V.
CI
V
Va
-
Vee = +5.0V, V,H = Vee
V,L = GND, IxseL = 5.38MHz
ILP = 33.6KHZ, IFR = 70Hz
input data: Checkered
indication, no-load
Input terminal capacity
42.0
0.4
010240
Va = +30.0V
Vee = +5.0V, V3 = +4.0V
V2 = +26.0V, V5 = +O.OV
Other conditions are
the same as those in the
IDD column
V
V
-
010240
10
-
5.5
40.0
-
GND
Mean working current
-
Unit
-
10L = 0.6mA
GND ~ V,N ~ Vee
8.0
Max
604
SED1752ToA
•
Working voltage range Vee - Vo
The Vo voltage should be set up within the Vee - Vo working voltage range given below.
Vo
(V)
50
42
40
30
28
20
I
10
o
2.0
2.7
5.0
4.0
3.0
Vee
605
(V)
6.0
SED1752ToA
•
o
AC Characteristics
Input Timing Characteristics
-----------------------------------~--~t-D-F----------------------
FR
LP
XSCL
00-07
_____________~~ot------- tSUE -----.~
EI01,2
(IN)
Parameter
XSCLcycie
Symbol
Conditions
Min,
tc
*3, *5
All timing signals are based
on 20% and 80% of Vcc
55
-
ns
20
-
ns
ns
XSCL high level pulse duration
twCH
XSCL low level pulse duration
tWCL
Data setup time
tos
10
Data hold time
tOH
10
~
tLO
0
tLH
35
XSCL
LP
~
LP rise time
XSCL fall time
LP high level pulse duration
FR delay allowance
tWLH
ns
ns
ns
40
*2
35
-300
+300
ns
30
-
ns
-
50
ns
*4
606
ns
*1
tOF
tr, tf
Units
-
EIO setup time tSUE
Input signal variation time
20
Max.
ns
ns
SED1752ToA
Vcc = 5.0V ± 10%,
Parameter
XSCL cycle
T. = 30 to
85°C
Symbol
Conditions
Min.
Max.
Units
tc
*3, *5
All timing Signals are based
on 20% and 80% of Vcc
100
-
ns
35
-
ns
-
ns
-
ns
XSCL high level pulse duration
tWCH
XSCL low level pulse duration
twCL
35
Data setup time
tos
15
Data hold time
tOH
10
XSCL ~ LP rise time
tLO
-10
LP ~ XSCL fall time
tLH
60
LP high level pulse duration
tWLH
*1
75
*2
65
ns
ns
ns
ns
ns
FR delay allowance
tOF
-300
EIO setup time
tSUE
40
-
ns
Input signal variation time
tr,
-
50
ns
tt
*4
+300
ns
Notes: *1. The '1WLH" specifies the time when the LP is at "H" and, at the same time, when XSCL is at "L", when LP is being input
while the XSCL is at "L".
*2. The "\wLH" (its definition is same as *1) when LP rises while XSCL is at "H".
*3. High speed operation of the shift clocks (XSCL) should only be made under a condition of tr + tf $ (te - tweL - tweH).
*4. When making high speed data transfer using continuous shift clocks, tr + tf of the LP signals should be up to (te + tweH
- tLD - \wLH - tLH) at the maximum.
*5. When '1c" is set to 60ns or less, ''T.'' must be 55°C or less.
607
I
SED1752ToA
•
o
AC Characteristics
Output Timing Characteristics
FR
LP
XSCL
EI01,2
(OUT)
SEG
Vcc = 5.0V ± 10%, Va = +14.0 to +42.0V
Symbol
Conditions
Min.
Max.
Units
EIO reset time
tER
ns
tOCL
55
ns
LP ~ SEG output delay time
tLSO
-
120
EIO output delay time
CL=15pf
(EIO)
200
ns
400
ns
Parameter
FR
~
SEG output delay time
tFRSO
CL = 100 pf
(0 n)
VCC = 2.7-4.5V, Va = +14.0 to +2B.OV
Symbol
Conditions
Min.
Max.
Units
EIO reset time
tER
ns
tOCL
B5
ns
LP ~ SEG output delay time
tLSO
-
240
EIO output delay time
CL = 15 pf
(EIO)
400
ns
-
BOO
ns
Parameter
FR
~
SEG output delay time
tFRSO
CL=100pf
(0 n)
60B
SED1752ToA
•
LCD Driving Power Supply
•
Setting up respective voltage levels
When setting up respective voltage levels for LCD drive, it is the best way to resistively divide the potential
between Vo - GND to drive the LCD by means of voltage follower using an operation amplifier.
In consideration of the case of using an operation amplifier, the LCD driving minimum potential level V5 and
GND are separated and independent terminals are used.
However, since the efficacy of the LCD driving output driver deteriorates when the potential of V5 goes up
beyond the GND potential to enlarge the potential difference, always keep the potential difference of V5- Vss
at OV to 2.5V.
When a resistance exists in series in the power supply line of Vo (GND), 10 at signal changes cause voltage
drop at Vo (GND) of the supply terminals of the LSI, disabling it to maintain the relations of the LCD with
intermediate potentials of (VDDH ;::: Vo ;::: V2 ;::: V3 ;::: V5;::: GND), thus leading to breakdown or destruction of the
LSI.
When using a protective resistor, do not fail to stabilize the voltage using an appropriate capacitance.
•
Precautions when turning the power on and off
Since the LCD drive voltage of these LSls is comparatively high, if a high voltage of 30V or more is applied
to the LCD drive circuit with the logic operation power made floating or with the Vee lowered to 2.6V or less,
or when the LCD drive signals are output before applied voltage to the LCD drive circuits is stabilized, excess
current flows through to possibly lead to breakdown or to destroy the LSI.
It is therefore suggested to maintain the potential of the LCD drive output to V51evel until the LCD drive circuit
voltage is stabilized, using the display off function (DSPOFF).
Maintain the following sequences when turning the power on and off:
• When turning the power on:
Turn on the logic operation power -7 turn on the LCD drive power or turn them on simultaneously.
• When turning the power off:
Turn off the LCD drive power -7 turn off the logic operation power or turn them off simultaneously.
For protection against excessive current, insert a quick melting fuse in series in the LCD drive power line.
When using a protective resistor, select the optimum resistance value depending on the capacitance of the
LCD cells.
609
I
SED1752ToA
•
A Connection Example
•
Block diagram of a large-plane LCD
YOU
YSCL
OSPOF
SHL
~
V5
SE01743
0101
~
V4
V3
V2
Vl
VO
-,/
7fT
SEL
~
-,/
~
~
0102
SE01743
0101
~
1920 X 480 DOT
-,/
?.E_L____ ~ ---------------------------------------------------------------013
[0102
-,/
-;Ii
(YOL)
-
FR
S~01743
0101
~-;i SEL
0102
~
-,/
1fi
LP
XSCL
SHL
DLO-7
(1/240 DUTY)
11480 DUTY
~
-,/
~24~
~240~
-<24~
-<240~
SE01752
EIOl
EI02
SE01752
EI02
EIOl
SE01752
EIOl
EI02
SE01752
EIOl
EI02
Ill]
!
610
SED1752ToA
•
SED1752T TCP Pin Arrangement Example
Note: This drawing is not meant to determine the contour of the TCP.
Oamy
Oamy
Oamy
0240
0239
0238
0237
0240
VDDHL
VOL
V2L
V3L
V5L
GNOL
Vee
NC
EI02
DO
01
02
03
04
05
06
07
XSCL
OSPOF
LP
EI01
FR
SHL
NC
NC
GNOR
V5R
V3R
V2R
VOR
VO-OHR
01
I
,
04
03
02
01
Oamy
Oamy
Oamy
611
.
----~
-.----
..
SED1752ToA
•
Dimensional Outline Drawing
•
SED1752ToA
For Reference
X(+)
612
SED1752ToA
•
SED1752TDB
For Reference
i 7.40
o
,
j
il~-I !
I I
J
J
II
:
':'=1-- I
"
'I'
i
I
1
,
I
I
I wi
I~
I
I
~I
. --!t-
I
II
I,
i
I
-I
~·rmm
]
w
D D
r-°,03±""~1
\)
~D
I---~I
I--- (0.070)-~
MAXO.05
~
"-
I
\
MINO.02O
613
X(+)
I
THIS PAGE INTENTIONALLY BLANK
..
614
(PRELIMINARY)
SED1756DoA
CMOS LCDSEGMENTDRWER
•
DESCRIPTION
The SED1756 is an LCD segment (column) driver designed for extremely high-capacity dot-matrix liquid
crystal panels. It is designed for use in conjunction with the SED1755 common (row) drivers.
The SED1756 features a wide range of liquid crystal drive voltages, LCD display of high quality, and daisychain enable system that decreases power consumption. It offers a wide range of applications.
•
FEATURES
• 240 LCD segment drive outputs
• Liquid crystal drive in wide range of voltage:
8 to 24V
• Pin-selectable output shift direction
• Low-power, high-speed data transfer:
16MHz clock frequency at 5V ± 10%
and 1OMHz clock frequency at 3V
• Zero-bias display disable function
• Chip configuration long from side to side
• Adjustable LCD drive voltage relative to ground
and VOOH
• 2.7 to 5.5V supply
• Chip AI pad die for COG
•
I
BLOCK DIAGRAM
0240----------------01
VOOHL
VOL 0 - - - - - + /
~~t 0 - - - - - + /
VOOHR
LCD Driver 240 bit
V5L 0 - - - - - + /
1+----0 VOR
1+----0 ~~~
1+----0 V5R
FR
DSPOF
LP
Vee
GND
GNDL
GNDR
DO-D7
XSCL
SHL
EI02
EI01
TEST
615
SED1756DoA
•
•
BLOCK FUNCTIONS
Enable Shift Register
•
Latch
Collects the contents of the data register at the LP
fall edge trigger, and transmits the output to the
level shifter.
The enable shift register is a bidirectional shift
register which shift direction is selected by the
SHL input.
The shift register output is used to store the data
bus signal in the data register.
•
When the enable signal is disabled, the internal
clock signal and data bus are fixed to "L", and it
enters the power save mode.
When using multiple segment drivers, cascade
connection is to be made on the EIO terminals of
the drivers and the EIO terminal of the first driver
is to be connected to the "GND".
Level Shifter
Level interface circuit used to convert the voltage
level of the signal from the logic system level to
the liquid crystal drive level.
•
LCD Driver
Outputs liquid crystal drive Voltage.
The enable control circuit automatically detection
that collection of the 240-bit data is completed,
and automatically transmits the enable signal, so
there is no need of the control signal by the
control LSI.
The relation between the data bus Signal, alternating signal FR, and segment output voltage is
as shown below.
DSPOF
•
Data Register
Data Bus
Signal
H
H
This register is used for serial/parallel conversion
of the data bus signal by the enable shift register
output. Thus, the relation between the serial
display data and the segment output is decided
regardless of the shift clock inputs.
L
L
616
-
FR
Driver Output
Voltage
H
Va
L
Vs
H
V2
L
V3
-
Vs
SED1756DoA
•
TIMING DIAGRAM
When it is 1/240 duty (example for reference)
240
234
239
Latch Data
---4~~
__
240
2
3
239
240
_____ JLJUUUL _____ ~
LP
W_~~LL_
FR
LP
---Sf-IUlSL---Sf-IUlSL---
XSCL
2 ---X-,-----3 -- - X 30 X
DO to 07 ----'-30-----,--r-1--X--r-
~I"
CD
EIOCD
I
-
1 X 2 X 3 - - - X 30 X
EI~® EIO@
1 X 2 X 3 -- -
-'-X-'--3-'--0~~'--'-
~I
®
I
L
-
I
CD to ® are the driver's cascade numbers.
* In high-speed data transmission, the XSCL period may need
to be longer in the LP pulse insertion timing, so as to
secure the LP -> XSCL (tLH) standard.
LP~I
Latch Data ~
L
r--HI
L
--~--~I
FR
H
L
H
II
DSPOF
(V3 -
I
V5
----I
----------c
617
L
SED1756DoA
•
PIN DESCRIPTION
Pin Name
Description
I/O
Numbers of Pins
000240
0
Liquid crystal drive segment (column) output
The output changes at the edge of LP fall.
240
DO- D7
I
Display data input
8
XSCL
I
Display data shift clock inpuit (Fall edge trigger)
1
LP
I
display data latch puilse input (Fall edge trigger)
1
Enable input.output
Set at input or output by the SHL input level.
Output is reset by input of LP, and automatically
falls to "L" as soon as 240 bits of data is collected.
2
Shift durection selection, and EIO terminal
inpuVoutput control input
When data is inpiut to the (DO, D1, .... D7)
terminals in sequence of (FO, F1, .... F6, F7)
(LO, L 1, .... L6, L7), the relation between the data and the
segmnent is as follows.
1
EI01
EI02
I/O
SHL
I
S
o Output
H
3
2
1
EI01
EI02
H
LO
L1
L2
....
F5
F6
F7
Input
Output
L
F7
F6
F5
....
L2
L1
LO
Output
Input
L
240 239 238
Note:
FR
I
EIO
The relation between the data and shift segment
output is decided regardless of the number of
clocks.
Liquid crystal drive output alternating signal input.
1
Vee, GND
Power
supply
Logical power supply GND: 0 V Vee: +3.3, +5 V
2
VOOHL, VOOHR
VOL, VOR
V2L, V2R
V3L, V3R
VSL, VSR
GNDL, GNDR
Power
supply
Liquid crystal drive power supply
GND: 0 V, VOOH: + 14 to +42V
Vo ? V2 ? 7/9 Vo
2/9 Vo? V3?' Vs ? GND
DSPOF
I
Forced bias fixed input
The output is forced to the V5 level at the "L" level.
TEST
I
Non Connect
1
1
sTotal182
618
SED1756DoA
•
PAD DIMENSIONS
1
D
..J
D
...J
D
...J
D
...J
D
D
...J...J
§»»~
CJ
>
D
o
I-
:CO
~I~
CJ)
UJ
I-
U)
DODO
~
~
a.. a::
oCJ)~
D
0
0
C\I
Z
....J
()
CJ)
CJ
0
is
D
D
00000000
0
()
()
!"--.U')('t),....
>
is
0000
CO'¢'NO
0000
30
o
0
0
0
0
a::
CI
a: a:
0:
a: c:
U>
C'?
C\I
0
0
:c
z»»§l
CJ
>
>-
Chip Size:
17.04mm x 2.30mm
Chip Thickness: 400llm (Typ.)
-------------1-----!
CHIP EDGE
"
:-- 140IlmD~(Mm'
,
,
: 70~m 1
,~
CHIP EDGE
(X,Y) 90 x 90 11m
619
T
I
I
SED1756DoA
•
PAD COORDINATES
Pad No.
Pad Name
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VOOHl
-8295
-7895
-7495
-7095
-6695
-6295
-5095
-4495
-4095
-3895
-3695
-3495
-3095
-1895
-1295
3295
3695
3895
4095
4295
4495
4695
4895
5095
6295
6695
7095
7495
7895
8295
VOL
V2L
V3l
VSl
GNOL
TEST
SHL
---
OSPOF
FR
LP
XSCL
GNO
EI02
EI01
Vee
07
06
05
04
03
02
01
00
GNOR
VSR
V3R
V2R
VOR
VOOHR
Y
-980
-968
-968
-968
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-980
-968
-968
-968
-980
Pad No.
Pad Name
X
31
32
33
34
35
36
37
38
01
02
03
04
05
06
07
08
8365
8295
8225
8155
8085
8015
7945
7875
Y
824
994
824
994
824
994
824
994
-7875
-7945
-8015
-8085
-8155
-8225
-8295
-8365
824
994
824
994
824
994
824
994
r
263
264
265
266
267
268
269
270
X of On : 8435- (70xn) 11m
Y of On : n = odd 824 11m
n = even 994 11m
620
0233
0234
0235
0236
0237
0238
0239
0240
SED1756DoA
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Codes
Ratings
Supply voltage (1)
Vcc
-0.3 - +7.0
V
Supply voltage (1)
V
-0.3 - +45.0
V
Supply voltage (3)
Parameters
Units
Yo, V2, V3, Vs
GNO-0.3 - V +0.3
V
Input voltage
VI
GNO-0.3 - Vcc +0.3
V
Output voltage
Vo
GNO-0.3 - Vcc +0.3
V
EIO output current
10
20
mA
Working temperature
Topr
-40 - +85
°C
Storage temperature 1
Tstg1
-65 - +150
°C
av.
va, V2, V3 voltages shall always maintain the condition of va ;:: V2 ;:: V3 ;:: V5 ;:: GND.
Note 1: All stated voltages assume that GND =
Note 2:
va
V2
42V
V3
V5
Vee
5V
GND
GND
Note 3: Avoid floating status of the logical powersupplyduring application of liquid crystal drive power, orfall of the power below
Vee = 2.6V; the LSI may be destroyed permanently. Special notice is required for the power sequence when turning
on or off the system power.
621
I
SED1756DoA
•
DC Characteristics
Parameter
Unless otherwise specified, GND = Vs = OV, Vcc = +5.0V
Symbol
Condition
Supply voltage (1)
Recommended working
voltage
Workable voltage
Supply voltage (2)
Supply voltage (3)
High level input voltage
Vee
VOOH
-
VOOH
V2
V3
V,H
Function only
Recommended value
Recommended value
Vee= 2.7- 5.5V
Low level input voltage
V,L
High level output voltage
Low level output voltage
VOH
VOL
Input leak current
VCC = 2.7 to 5.5 V
Vee =
2.75.5V
I
I
10H =-o.6mA
IOL=0.6mA
III
GNO ,,; V,N"; Vee
I/O leak current
Rest current
ILlio
IGNO
GNO ,,; V,N"; Vee
Output resistance
RSEG
Output resistance
In-chip deviation
Mean working current
consumption (1)
ARsEG
Icc
Mean working current
consumption (2)
IODH
Input terminal capacity
CI
I/O terminal capacity
CliO
Applicable
Pin
Vee
VooHL, VOOHR
Vo = 14.0 - 42.0V
V,H = Vee, V,L = GNO
AVON
Vo = +36.0V, 1/24
=0.5V
Recom- Vo = +26.0V, 1/20
mended
condition
AVON = 0.5V
Vo = +36.0V, 1/24
Vee = +5.0V, V,H = Vee
V,L = GNO, IxseL = 5.38MHz
ILP = 33.6KHZ, IFR = 70Hz
input data: check display,
no-load
Min
Typ
Max
Unit
2.7
14.0
5.0
-
5.5
40.0
V
V
8.0
-
42.0
VDOH
2/9 VDDH
-
-
V
V
V
V
-
-
0.2Vee
V
Vee-O.4
-
-
-
-
GND+O.4
V
V
-
-
2.0
J1A
-
-
5.0
25
J1A
-
0.9
1.4
KQ
-
1.0
1.5
010240
-
-
95
Q
Vee
-
0.75
1.7
mA
-
0.3
0.9
-
0.25
1.4
mA
VOL, VOR
V2L, V2R
V3L, V3R
E101, E102, FR
00-07, XSCL
SHL, LP,
OSPOF
E101, EI02
00-07, LP, FR
XSCL,SHL
OSPOF
E101, EI02
GNO
010240
Vee = +3.0V
Other conditons are the
same as those when
Vee + 5V.
Va =+30.0V
VODHl, VDDHR
Vee = +5.0V, V3 = +4.0V
V2 = +26.0V, V5 = +O.OV
Other conditions are
the same as those in the
Icc column
Freq. = 1 Mhz
00-07, LP, FR
Ta = 25°C
XSCL,SHL, OSPOF
Independent
EI01, EI02
chips
622
± 10%, Ta = -40 to 85°C
7/9 VDOH
GNO
0.8 Vee
J1A
-
-
8
pF
-
-
15
pF
SED1756DoA
•
Operation Voltage Range Vee - VOOH
The VOOH voltatge must be set within the following Vee - VOOH operation voltage range.
VDDH
(V)
50
42
40
30
28
20
I
10
o
2.0
2.7
4.0
3.0
Vee
623
5.0
(V)
6.0
SED1756DoA
•
o
AC Characteristics
Input Timing
VIH = 0.8 x Vee
VIL = 0.2 x Vee
FR
LP
XSCL
07-00
EI01,2
(IN)
________________________~~~tsuE
Vcc = 5.0V ± 10%, Ta = -40 to 85°C
Parameter
Symbol
tc
Conditions
-
Min.
XSCL high level pulse duration
twCH
20
XSCL low level pulse duration
tWCL
Data setup time
tos
Data hold time
tOH
~
tLD
tLH
-
LP high level pulse width
tWLH
*1
EIO setup time
tSUE
-
Symbol
Conditions
Min.
tc
Vcc = 2.7V
Vee = 3.0V
115
100
-
ns
XSCL high level pulse duration
tWCH
35
-
ns
tWCL
Data setup time
tos
20
-
ns
Data hold time
tOH
-
35
XSCL low level pulse duration
10
ns
~
tLD
-
-
ns
ns
XSCLcycie
XSCL
LP
~
LP rise time
XSCL fall time
62
Max.
-
Units
ns
-
ns
ns
35
-
15
-
ns
20
15
10
-5
40
ns
ns
ns
ns
ns
Vcc = 2.7 to 4.5V, Ta = -40 to 85°C
Parameter
XSCLcycie
XSCL
LP
~
LP rise time
XSCL fall time
tLH
-5
Vcc =2.7V
Vcc = 3.0V
75
65
Max.
LP high level pulse width
tWLH
Vcc = 2.7V *1
Vcc = 3.0V *1
75
65
-
EIO setup time
tSUE
Vcc = 2.7V
Vcc = 3.0V
30
25
-
*1 . •
•
•
•
Units
ns
ns
ns
tWLH prescribes the LP "H" and XSCL "L" time, when LP is input during the "L" period of XSCL.
tWLH when LP rises from the XSCL "H" period (the definition is the same as the above *1)
It is limited to t, + trt ~ (te - tweL - tweH), when the shift clock (XSCL) is operated in high-speed mode.
When high-speed data transmission is done with contino us shift clock, the maximum of the LP signal" + tf is (te + tweH
- tLD - !wLH -ILH).
624
SED1756DoA
•
o
AC Characteristics
Output Timing
VIH
VIL
1_
.
FR
LP
=0.8 X VCC
=0.2 X VCC
~!
XSCL
EI01,2
(OUT)
On - - - - - - - - - - - - - - - - - - - - - - , L / - - - (SEG) - - - - - - - - - - - - - - - - - - - - - 4 ' - - - - -
Vee
Parameter
= 5.0V ± 10%, VDDH = 14.0 to 42.0V, Ta =-40 to 85°C
Conditions
Min.
Max.
Units
tER
CL = 15 pF
(EIO)
-
90
ns
-
50
ns
200
ns
300
ns
EIO output delay time
tDeL
LP --t SEG output delay time
tLSD
FR --t SEG output delay time
tFRSD
CL = 100 pF
(On)
Vee
Symbol
EIO reset time
tER
EIO output delay time
tDeL
LP --t SEG output delay time
tLSD
FR --t SEG output delay time
Vn + 0.5
Symbol
EIO reset time
Parameter
Vn -0.5
=2.7 to 4.5V, VDDH = 14.0 to 28.0V, Ta =-40 to 85°C
Conditions
CL
(EIO)
CL
= 100 pF
(On)
tFRSD
Min.
= 15 pF
Vee
Vee
=2.7V
= 3.0V
Max.
Units
240
ns
85
75
ns
-
400
ns
-
600
ns
-
625
-
-----
..
__.._ - - - - - - - - - - _.._ - - - - ---_._ .. _.. _...__... _._--
I
SED1756DoA
•
FOR REFERENCE
-------------------------------
XSCL
DO-D7
T
I I T
SHL
EI02
GN'l= EI01
_flee
SED1756(1)
01
SED1755(1)
DI02
YSCL
DIO
YSCL
-
1
J
I
240
SHL
SEL
DI3
DI01
SED1756 x 8
--------
10240
SHL
EI02
EI01
j
SED1756(8)
01
I
240
10240
0240
r----
~
DSPOF
I I
IIlI
640 x 3 x 480 dots
1/240 duty
240
r---01
---------------------------------------------------------------
-
SED1755(1)
DI02
YSCL
0240
r----
I--- ~
DSPOF
l
J
SHL
SEL
DI3
DI01
240
r---01
01
I
240
10240
SED1756(1)
EI01
DJ EI02
GND
SHL
-------
DSPOF
DO-D7
XSCL
-------
-------
Vo
V1
V2
R
Va
V4
GND --~----------------. Vs
626
240
10240
SED1756(8)
SED1756 x 8
EI02
EI01
---- GN~ SHL
FR
VDDH
I
------:~I
1 I I
LP
01
Vee
SED1758
LOW-POWER 160-BIT LCD SEGMENT DRIVER
•
DESCRIPTION
The SED1758 is a 160-bit dot matrix LCD segment (column) driver for driving high-resolution color STN LCD
panels at duty cycles higher than 1/100 (up to 1/500). The LSI features a wide range ofthe LCD drive voltages.
The device uses a daisy-chain enable system which decreases power consumption and eliminates the need
for separate enable signals for each driver.
The SED1758 is used in conjunction with the SED1743 (160-bit common driver) to drive a large-capacity dot
matrix LCD panel.
•
FEATURES
• Low-power, high-speed CMOS technology
• 160-bit segment (column) driver
• Ability to adjust offset bias of the LCD source from
VDD
• High-speed 8-bit data bus
• High-speed daisy chain enable support
• Duty cycle .................................. 1/100 to 1/500
• Adjustable offset bias of the liquid crystal according to the VDDH and GND
• Adjustable LCD drive voltages
• LCD voltage ......................................... 8 to 42V
• Unbiased display off function
• Supply voltage ................................. 2.7 to 5.5V
• Adjustable offset bias of the LCD according to
VDDH and GND
• Shift clock frequency. 16MHz max at VDD
•
• Package
TOA .................. Slim TAB (9.3mm)
TOB .................. Bending TAB
TOG .................. Ultra slim TAB (7.3mm)
=5V
SYSTEM BLOCK DIAGRAM
DO - D7
XSCL
LP,FR
LCD
CONTR
-
YSCL
YD
I
SED1758
1
'I
~6~
~6~
SED1743~
•
SED1743~
SED1758
320 SEG x 480 COM
DUTY: 1/480
J
SED1743~
627
I
SED1758
•
BLOCK DIAGRAM.
01
----------------------
0160
----------------------
VOOHL
VOOHR
LCD Driver
160 bits
{r
Level Shifter
160 bits
t
FR
11
DSPOF
Latch
160 bits
LP
0
Vee ~
GND
~
Data Register
160 bits
'1J
00-07
~
XSCL
EI01
,
{r
Bidirectional Shift Register
1
SHL
EI02
628
\
SED1758
•
•
BLOCK DESCRIPTION
Enable Shift Register
The enable shift register is a bidirectional shift register where the direction of the shift is selected by the SHL
input. The output of this shift register is used to store the data bus signals in the data register.
When the enable signal is in a disable state, the internal clock signal and data bus are fixed at "L", placing
the chip in power save mode.
When multiple segment drivers are used, the EIO terminals of the various drivers are cascade connected and
the EIO terminal of the first driver is connected to GND. (See the example of connection, below.)
The enable control circuit automatically senses when 160 bits worth of data have been received, and sends
the enable signal, thus eliminating the need for a control signal from the control LSI.
•
Data Register
This is a register to convert the data bus signal from serial to parallel using the output of the enable shift
register. Consequently, the relationships between the serial display data and the segment output is
determined independently of the shift clock input number.
•
Latch
The latch receives the contents of the data registers when triggered by the falling edge of the LP, and outputs
them to the level shifter.
•
Level Shifter
The level shifter is a level interface circuit which converts the signal voltage level from a logic circuit level to
the LC driver voltage level.
•
LCD Driver
The LCD driver outputs the LC drive voltage.
The relationship between the data bus signal, the AC signal FR, and the segment output voltage is as follows:
DSPOFF
Data
Bus Signal
H
H
L
L
-
FR
Voltage
Driver
o Voltage
H
VO
L
V5
H
V2
L
V3
-
V5
629
I
SED1758
•
PIN DESCRIPTION
No. of
Pins
Pin Name
I/O
Function
00 to 0160
0
Segment (column) output to drive LC.
Output transition occurs on falling edge of LP.
DO to 07
I
Display data input.
8
XSCL
I
Display data shift clock input (triggers on falling edge)
1
LP
I
Display data latch pulse input (triggers on falling edge)
1
EI01
EI02
I/O
Enable I/O
2
SHL
I
160
This is set to input or output depending on the level of the SHL input. The
output is reset by the LP input, and once the 160-bit data reception is
complete, the terminals automatically fall to "L".
Shift direction select and EIO terminal I/O control pin.
1
When the data has been input to terminals (DO, 01, ... , 07) in the order (aO,
a1, ... , a6, a7) (bO, b1, ... , b6, b7) ... (to, t1, ... , t6, t7), the relationship between
the data and the segment output is as shown in the table below:
SHL
L
H
Note:
o Output
01
02
a7
to
a6
t1
03
a5
...
t2
...
EIO
0158
0159
0160
1
2
t2
a5
t1
a6
to
a7
I
0
0
I
The relationship between the data and the segment output is
independent of the shift clock number.
FR
I
LC drive output AC signal input
1
Vee, GND
Power
Power source for logic: GND : OV Vee: +3.3, +5V
2
VOOHl, Val,
V2l, V3l,
VSl, VDDHR,
VOR, V2R,
V3R, VSR
Power
LC drive circuit power:
GND: OV
VDDH ~ VO ~ V2 ~ 7/9 x VO
2/9 x VO ~ V3 ~ V5 ~ GND
10
DSPOFF
I
VOOH: + 14 to +42V
Forced bias set input.
1
"L" level input forces the bias to the V5 level.
• When this function is used, it cannot be used in combination with the
SED1703.
Total: 187
630
SED1758
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Unit
Power voltage (1)
Parameter
Vee
-0.3 to +7.0
V
Power voltage (2)
VDDH
-0.3 to +45.0
V
Power voltage (3)
YO, V2, V3, V5
GND - 0.3 to Vee + 0.3
V
Input voltage
VI
GND - 0.3 to Vee + 0.3
V
Output voltage
VO
GND - 0.3 to Vee + 0.3
V
EIO output current
101
20
mA
°c
°c
°c
Operating temperature
TOPR
-30 to +85
Storage temperature 1
TSTG1
-65 to +150
Storage temperature 2
TSTG2
-55 to +100
Notes:
1. All voltages are given relative to GND = OV.
2. Storage temperature 1 is the recommendation for the chip itself, and storage temperature 2 is the recommendation for
the chip mounted on a TCP.
3. Ensure that the relationship between YO, V2, V3 and V5 is always as follows: VDDH ;:: VO ;:: V2 ;:: V3 ;:: V5 ;:: GND.
VDDH
VO
V2
42V
V3
VCC
V5
5V
GND
GND
4. The LSI may be permanently damaged if the logic system power is floating or Vcc is less than or equal to 2.6V when
power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning
the power on and off.
631
I
SED1758
•
Unless otherwise specified, GND =VS =OV,
Vec =+S.OV ±10%, Ta = -30 to +8SoC
DC Electrical Characteristics
Applicable Pins
Min
Power voltage (1)
Parameter
Symbol
Vcc
Conditions
Vcc
2.7
Recommended operating
voltage
VO
VOL, VOOHL
VOR, VOOHR
Possible operating
voltage
VO
Function
Typ
Max
Unit
5.5
V
40.0
V
-
42.0
V
VO
V
2/9xVO
V
14.0
-
8.0
Power voltage (2)
V2
Recommended value
V2L, V2R
7/9xVO
Power voltage (3)
V3
Recommended value
V3L, V3R
GND
-
High-level input voltage
VIH
Vcc = 2.7 to 5.5V
0.8xVcc
-
Low-level input voltage
VIL
EI01, EI02,
FR,DO-D7,
XSCL, SHL,
LP,DSPOFF
High-level output voltage
VOH
EI01, EI02
Vcc-0.4
Low-level output voltage
VOL
-
Input leakage current
III
Vcc=
2.7 to
5.5V
IOH=--{).6mA
IOL= O.6mA
-
V
-
0.4
V
2.0
I!A
EI01, EI02
-
-
5.0
GND
-
25
I!A
I!A
01 - 0160
-
0.85
2.6
KQ
-
0.90
2.6
GND ~ VIN ~ Vcc
VO = 14.0 to 42.0V,
VIH = Vcc, VIL = GND
Output resistance
RSEG
AVON =
0.5V
Recommended
value
VO=+36.0V,
1/24
VO=+26.0V,
1/20
AVON = 0.5V
VO = +36.0V, 1/24
01 - 0160
Vcc =+5.0V,
VIH = Vcc, VIL = GND,
fxSCL = 5.38MHz,
fLP = 33.6KHz,
fFR = 70Hz;
Input data: checker
pattern display, no load
Vcc
10
VO =+30.0V,
Vcc = +5.0V, V3 = +4.0V,
V2 = +26.0V, V5 = O.OV;
other parameters are the
same as for the Icc item
Input terminal capacitance
CI
Freq. = 1 MHz,
Ta = 25°C, Chip alone
0.5
90
Q
1.1
mA
---
---
-
0.2
0.6
mA
VO
-
0.15
0.9
mA
DO - D7, LP,
FR,XSCL,
SHL, DSPOFF
-
-
8
pF
EI01, EI02
-
-
15
pF
Vcc = +3.0V; other
parameters are the
same as for Vcc = 5V
Average operating
consumption current (2)
-
--- --
-:-;-----
I/O terminal capacitance
-
ILIIO
Icc
V
-
IGNO
Average operating
consumption current (1)
0.2 xVcc
DO - 07, LP,
FR,XSCL,
SHL, DSPOFF
I/O leakage current
ARsEG
-
V
GND ~ VIN ~ Vcc
Static current
Output resistance
deviation within the chip
-
-
CliO
632
SED1758
•
o
AC Characteristics
Input Timing Characteristics
FR
LP
XSCL
DO- D7
EI01,2
(IN)
____________~~~.r---------tSUE--------~.,
VCC = 5.0V ± 10%, T. = -30 to 85°C
Parameter
XSCL frequency
Symbol
Conditions
Min
tc
tr, If ::; 11 ns *3
62
Max
-
ns
-
20
-
ns
10
ns
-5
-
ns
ns
ns
XSCL high-level pulse width
twCH
XSCL low-level pulse width
twCL
Data setup time
tDS
Data hold time
tDH
XSCL ~ LP rising edge
tLD
-
LP ~ XSCL falling edge
tLH
-
30
*1
40
*2
35
+300
LP high-level pulse width
twLH
20
10
Unit
ns
ns
ns
ns
Allowable FR delay
tDF
-
-300
EIO setup time
tSUE
-
30
-
ns
Input signal conversion time
tr,1f
*4
-
50
ns
Symbol
Conditions
Min
tc
tr, If < 15ns *3
100
-
ns
-
35
ns
-
15
-
ns
-
-10
-
*1
75
ns
*2
65
-
VCC = 2.7 to 4.5V, Ta = -30 to 85°C
Parameter
XSCL frequency
XSCL high-level pulse width
twCH
XSCL low-level pulse width
tWCL
Data setup time
tDS
Data hold time
tDH
XSCL ~ LP rising edge
tLD
LP ~ XSCL falling edge
tLH
LP high-level pulse width
tWLH
Allowable FR delay
tOF
EIO setup time
tSUE
-
Input signal conversion time
tr,1f
*4
35
10
60
Max
Unit
ns
ns
ns
ns
ns
-300
+300
ns
40
-
ns
-
50
ns
Notes: *1. twLH indicates the time when LP is "H" and XSCL is "L" when LP is input during the interval when XSCL is "L".
*2. twLH when LP rises beginning during the interval when XSCL is "H" (where the definition is the same as in "*1").
*3. When the shift clock (XSCL) is set to high-speed operation, the constraint that follows holds true:
tr+lf::; (tc -twCL - twCH).
*4.
During high-speed data transfer with continuous shift clock, the maximum LP signal tr + If is
(tc + twCH - tLD - tWLH - tLH).
633
=- -------------
~~===~~.=-
I
SED1758
o
Output Timing Characteristics
FR
------------------------------------> XSCL (tLH) standard values.
LP
LATCH
DATA
FR
~)
~»
,
,
~)
I
~
~)
,
H;
~
,
: L)
,
'H )
,
H
---'----l
DSPOF
VO
V2
~
:
]'~'1"
.
....-
._ . . ;.
.
_.
±S";';
...
,
V3
V5
_..
-
.-
--
;
'.
.
) . . . . . . . - _... _:
.- .....
---- -- --- ------ --- - --- -------- --
..
...
. .... ..j
.- _... - .. ... ...
635
-
.
'
..
----
..
)~"
)
...
--- --- --- -- ---
.
._.
- - ---
I
SED1758
•
RANGE OF OPERATING VOLTAGES Vee - VO
It is necessary to set the voltage of va in the range of voltages Vee -
Va
va shown in the figure below:
(V)
50
42
40
30
28
20
10
o
2.0
2.7 3.0
4.0
Vee
636
5.0
(V)
6.0
SED1758
•
LCD DRIVING POWER
•
Method of Forming Each Voltage Level
The simplest way to obtain the voltage levels for driving the LCs is to use resistive voltage dividers between
VO and GND, and to drive the LCs with op amp voltage followers.
In consideration of the use of op amps, VS (the lowest voltage setting for driving LCs) and GND are separated
and given separate terminals.
However, when the voltage level of VS is above GND and the voltage difference between VS and GND
is large, the performance of the LC output driver is reduced. Therefore, ensure that the voltage gap
between VS and GND is in the range of OV to 2.SV.
Permanent damage may result to the LSI when there is serial resistance in the va or GND power line. This
is because, a voltage drop will occur at va or GND of the LSI power terminal (depending on the 10 when the
signal is changed), causing the power level relationships within the LCD (i.e., VDDH Z va Z V2 Z V3 z VS z
GND) to fail.
When a guard resistance is inserted, voltage stabilization using a capacitance is necessary.
•
Cautions During Power Up and Power Down
Because of the high voltage of the LC driving system of this LSI, if the power to the logic system is floating
or if Vcc is less than or equal to 2.6V when a high voltage of 30V or more is applied to the LC driving system,
or if the LC driving signal is output before the LC driving system voltage stabilizes, then too much current will
flow, causing damage to the LSI.
It is recommended that the display off function (DSPOF) be used until the LC drive system voltage stabilizes,
and that the LC drive output voltage be put to the VS level.
Follow the sequences below during power up and power down:
Power up: Logic system on
~
LC drive system on (or simultaneous)
Power down: LC drive system off
~
Logic system off (or simultaneous)
In orderto prevent excessive current, insert a high-speed fuse in series with the LC power source. The optimal
value of the guard resistance must be selected based on the capacitance of the LC cells.
637
I
SED1758
•
•
EXAMPLE OF CONNECTION
Large Screen LCD Structure Diagram
~I~
V5
V4
V3
V2
V1
VO
YOU - - - - - - - I
YSCL
DSPOF
==:::;It:::I
SHL--,f-H-'!L.J
640 x480 DOT
(YDL) ---+H-I--t
(1/240 DUTY)
11480 DUTY
FR--+f-H-I
638
SED1758
•
PAD LAYOUT
Ei ~ 8 2!i )g ~ 2i
~
0
0
0
'"
00 00000000
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
0
VDDHL
DSPOF
0
0
0
0
0
0
0
0
El
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
0
0
0
0
El
D
0
0
XSCL
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
0
0
EIOl
0
0
EI02
0
0
0
D
D
D
D
D
D
D
D
D
D
D
r--.
D
D
D
D
D
D
D
D
D
D
D
D
...-0
El
D
0
0
0
0
0
0
0
0
0
0
0
"R
VDP-R
"R
0
0
0
0
D
0
0
00 00000000
~~~~~~~
639
-,-.
-
--
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08'
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eo,
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g:
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Ii)
0
0
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gl~
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0
0
0
0
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El
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D
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D
0
0
0
0
0
0
0
El
D
""'w
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
CJ
D
D
D
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0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
D112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
D143
0135
0136
0137
0138
0139
D140
0141
0142
0143
0144
0145
gi:~
0148
0149
0150
0151
0152
0153
I
SED1758
•
PAD COORDINATES
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin
Name
NC
V3L
V3L
V2L
V2L
VOL
VOL
VOOHL
VOOHL
GNO
GNO
NC
SHL
NC
OSPOF
NC
NC
FR
NC
LP
NC
NC
XSCL
NC
EI01
NC
NC
EI02
NC
VCC
VCC
NC
07
NC
06
NC
NC
05
NC
04
NC
NC
03
NC
02
NC
NC
01
NC
00
X
y
-5953
-5834
-5692
-5419
-5292
-5035
-4907
-4748
-4620
-4491
-4364
-4235
-4033
-3743
-3541
-3250
-3121
-2920
-2629
-2428
-2137
-2008
-1806
-1561
-1288
-994
-865
-637
-345
-119
7
136
427
628
919
1121
1250
1540
1742
2033
2234
2363
2654
2855
3146
3347
3477
3767
3969
4259
-915
-915
-927
-915
-915
-915
-915
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
-937
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
Name
NC
VOR
VOR
V2R
V2R
VOOHR
VOOHR
V3R
V3R
NC
V5R
V5R
NC
0160
0159
0158
0157
0156
0155
0154
NC
0153
0152
0151
0150
0149
0148
0147
0146
0145
0144
0143
0142
0141
0140
0139
0138
0137
0136
0135
0134
0133
0132
0131
0130
0129
0128
0127
0126
0125
X
y
4461
4620
4748
5005
5132
5390
5517
5692
5834
5953
5946
5946
5967
5967
5967
5967
5967
5967
5967
5967
5972
5878
5784
5690
5596
5509
5428
5348
5268
5187
5107
5027
4947
4866
4786
4706
4626
4545
4465
4385
4304
4224
4144
4064
3983
3903
3823
3743
3662
3582
-937
-937
-937
-937
-937
-937
-937
-927
-915
-915
-604
-497
-311
-188
-64
58
182
305
429
552
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
640
Pin
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Pin
Name
0124
0123
0122
0121
0120
0119
0118
0117
0116
0115
0114
0113
0112
0111
0110
0109
0108
0107
0106
0105
0104
0103
0102
0101
0100
099
098
097
096
095
094
093
092
091
090
089
088
087
086
085
084
083
082
081
080
079
078
077
076
075
X
y
3502
3421
3341
3261
3181
3100
3020
2940
2859
2779
2699
2619
2538
2458
2378
2298
2217
2137
2057
1976
1896
1816
1736
1655
1575
1495
1415
1334
1254
1174
1093
1013
933
853
772
692
612
532
451
371
291
210
130
50
-39
-130
-210
-290
-370
-451
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
SED1758
Pin
Pin
No.
Name
X
y
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
074
073
072
071
070
069
068
067
066
065
064
063
062
061
060
059
058
057
056
055
054
053
052
051
050
049
048
047
046
045
044
043
042
041
040
039
038
037
036
035
034
033
032
031
030
029
028
027
026
025
-531
-611
-692
-772
-852
-932
-1013
-1093
-1173
-1254
-1334
-1414
-1494
-1575
-1655
-1735
-1815
-1896
-1976
-2056
-2137
-2217
-2297
-2377
-2458
-2538
-2618
-2698
-2779
-2859
-2939
-3020
-3100
-3180
-3260
-3341
-3421
-3501
-3581
-3662
-3742
-3822
-3903
-3983
-4063
-4143
-4224
-4304
-4384
-4465
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
Pin
Pin
No.
Name
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
024
023
022
021
020
019
018
017
016
015
014
013
012
011
010
09
08
NC
07
06
05
04
03
02
01
NC
V5L
V5L
X
y
-4545
-4625
-4705
-4786
-4866
-4946
-5026
-5107
-5187
-5267
-5348
-5428
-5508
-5595
-5690
-5784
-5878
-5972
-5967
-5967
-5967
-5967
-5967
-5967
-5967
-5967
-5946
-5946
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
924
552
429
305
182
58
-64
-188
-311
-497
-604
641
I
SED1758
•
DIAGRAM OF EXTERNAL DIMENSIONS (for reference) (SED1758ToA)
28.976
I~
17.00
!
!
~I
-~i
I
I
I
I
I'-Tl
i
r~I
I 111
L_~
I
r
I
.li
I
L
l
--=1 IIl
,-",~9'L.!
II
I
t-jl
I
-I
I~
I~
I
-- \
i'
I
I
TI
I
I
L,
X( +)
642
SED1758
•
DIAGRAM OF EXTERNAL DIMENSIONS (for reference) (SED1758To B)
@
0,~I
~
~! '~d ~i
i
~
,
~~--
----.\..
--
___ I
-I
~.
!
643
I
SED1758
•
DIAGRAM OF EXTERNAL DIMENSIONS (for reference) (SED1758ToG)
+--
I
------
- - - - -
~----D
Y(+)
~----.~
----~-
[-l
I
~I
I
====~
----
~j-i
__
~.'C=~-------
[]
1--1
~'
- -----------
:-fr-:-~-i~~·
644
SED1765
CMOS HIGH DUTY LCD SEGMENT DRIVER
•
DESCRIPTION
The SED1765 is a segment (column) driver for high-capacity dot matrix liquid crystal panels. It incorporates 160
high-voltage segment (column) drivers, and is designed for use in conjunction with the SED1703F common (row)
driver device.
The SED1765 uses a PWM (Pulse Width Modulation) technique to provide 16, 8, or 4-level gray-scale displays
without ghosting. The LCD drivers have been designed for low on output resistance making the SED1765
suitable for MIM LCD panels, and yielding gray-scale displays with few contrast disparities .
•
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16, 8 or 4-level PWM gray-scale LCD driver
Supports gray-scale gamma correction
Two parallel 4-bit inputs
160 LCD drive outputs
Maximum clock speed of 12 MHz allows a 640x480 pixel display with daisy-chain enable.
Speeds up to 16 MHz are possible using external enable generation
Wide 14 to 40 V range of LCD drive voltages
Display blanking function
Output shift direction is pin-selectable
Automatic enable signal propagation allows cascade connection and decreases power consumption
Adjustable LCD drive voltage offset relative to ground and supply
Logic circuitry uses single 5.0V ±1 0% power supply
CMOS Si-gate process
Packages:
AI pad chip: SED1765DOA
Au bump pad chip: SED1765DOB
Also available in tab
645
I
SED1765
•
BLOCK DIAGRAM
00 -------- 0159
VDDH Vee GND
VO
V5
V2
V3
FR
INH
GCP
RES
LP
DOlo D3
D410 D7
SHL
EI01
EI02
XSCL
T
•
FUNCTIONAL DESCRIPTION
•
1.1 Gray-Scale Control Circuit
This circuit divides the gray-scale generation clock input on pin GCP, passes it to the decoder block. The divider
circuit is reset on the falling edge of the RE3 or LP inputs or when the INH input is LOW.
•
1.2 Data Control Circuit
This circuit reorders the gray-scale data input on the DO to D3 and D4 to D7 pins, into the order specified by the
SHL input, and puts them on the internal data bus. It holds all data bus lines LOW if the device is disabled by
the control signal from the enable controller.
•
1.3 Enable Controller
This circuit causes the data bus and the internal clock to be held LOW, and puts the device into power save mode,
if the enable signal is inactive.
In systems with more than one segment driver, the enable inputs and outputs are cascaded, and the enable input
at the head of the chain connected to ground. The enable controller counts the number of input data bits, and
sets the enable output LOW to allow the next device in the chain to start loading data. This configuration
eliminates the need for the controlling device to generate enable control signals.
The EIO output is reset HIGH by the LP input.
646
SED1765
•
1.4 Shift Register
Segment data shift register. The latch A control signal is shifted by the shift clock. The direction of data shift is
selected by the SHL pin as shown in the figure below.
o (SEG Output)
SHL
159
•
158
......
......
......
157
L
AO
BO
A1
H
B79
A79
B78
EIO
2
1
0
1
B78
A79
B79
Output
Input
A1
BO
AO
Input
Output
2
1.5 Latch A
The gray-scale data present on the internal data bus is latched successively by the latch control signal from the
shift register.
• 1.6 Latch B
The data in latch A is latched in on the falling edge of LP.
•
1.7 Decoder
This circuit is locked to the signal from the gray-scale controlier, and generates a pulse width corresponding to
the gray-scale data value.
•
1.8 Level Shifter
The level shifter converts the logic-level signal from latch B to the voltage levels required by the LCD drivers.
•
1.9 LCD Drivers and Voltage Control Circuit
The LCD drivers drive individual columns of the display matrix with the voltage determined by the inhibit signal
INH, the frame signal FR, and the latched display data. This is shown in the table below.
INH
Data
H
H
L
L
-
647
FR
SEG Output Voltage
H
VO
L
V5
H
V2
L
V3
H
V2
L
V3
I
SED1765
•
PIN DESCRIPTION
Pin Name
00 to 0159
DO to 03, 04 to 07
XSCL
Function
Segment drive outputs
4-bit gray-scale data inputs. DO and 04 are the LSBs of each 4-bit nibble.
Segment data shift clock input. Data is shifted into the driver on the falling edge of XSCL.
Segment data latch strobe. Data is latched on the falling edge of LP.
LP
EI01, EI02
GCP
Daisy chain enable input/outputs configured by SHL
Gray-scale reference clock input.
PWM waveform reset input. The PWM waveform is reset to the OFF level by the falling
RES
edge of this input.
Shift direction select input. This signal configures EI01, EI02 and selects the shift
SHL
register shift direction. An is input on DO to 03 and Bn on 04 to 07.
FR
LCD AC-drive waveform input.
INH
Display blanking input. When LOW, all outputs go to "off" levels.
Vee, GND
Logic power supply inputs.
Test input. Tie low
T
•
ELECTRICAL CHARACTERISTICS
•
Absolute Maximum Ratings
Parameter
Supply voltage (1)
Symbol
Rating
Unit
Vee
-0.3 to +7.0
V
Supply voltage (2)
VDDH
-0.3 to +45.0
V
Supply voltage (3)
~o, V2, V3, V5
-0.3 to VDDH+0.3
V
VI
-0.3 to Vee+0.3
V
Operating temperature
Input voltage
Topr
-20 to +75
Storage temperature 1
Tstg
-65 to +150
°C
DC
Notes: 1. All voltages are with respect to ground.
2. Drive voltages should always be such that VDDH~VO~V2~V3~V5~ground.
VDDH
VO
V2
40V
Vcc
V3
5V
V5
GND
3. The device may be permanently damaged if the LCD power supplies are applied while the 5V logic supply is floating.
Pay particular attention to the power-on and power-off sequence.
648
SED1765
•
DC Characteristics
Parameter
Ta=-20 to 75°C, V5=OV, Vee=5.0V±10% unless otherwise noted
Symbol
Condition
Applicable
Rating
Signal
Min
Typ
Unit
Max
Supply voltage (1)
Vee
Vee
4.5
5.0
Supply voltage (2)
VDDH
VDDH
14.0
-
40.0
V
Input voltage
VO
VO
VOOH-2.5
-
VDDH
V
Input voltage (1)
V2
V2
17/9xVoDf
Input voltage (2)
V3,V5
V3,V5
GND
-
VO~V2~V3~V5
Recommended
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
HIGH-level output voltage
VOH
IOH=-0.4 mA
LOW-level output voltage
VOL
IOH=O.4 mA
III
GND:5VI:5Vee
Input leakage current
I/O leakage current
Quiescent current
All input 0.8xVcc
pins.
GND5VI5Vee
ILi/O
IGND
VDOH=14.0 to 40.0 V
EI01,EIO
resistance
VDDH=10.0V
Ro
VOH=0.5V
See note 1.
VDDH=20.0V
Vcc-O.4
GND
All pins
V
VDDH
V
2.9xVOOH
V
0.2xVec
V
0.2xVec
V
Vee
V
0.4
V
-
-
2.0
ItA
EI01, EI02
-
-
5.0
ItA
GND
-
-
25
ItA
~xceptEIO
VIH=Vee, VIL=GND
Segment output ON
GND
5.5
-
2.0
6.5
-
1.5
3.5
1.3
3.0
Vee
-
2.5
5.0
mA
VDDH
-
0.5
1.2
mA
All pins
-
-
8.0
pF
-
-
15.0
pF
00 to
0159
VDDH=30.0V
k.Q
Vee=5.0V, VIH=Vee,
VIL=GND,
fxaeL=10.6MHz,
Operating current (1)
fcc
fLP=33.8kHz,
1116=0.54 MHz,
FR=70 Hz, DO to
D7=FOFO ... , alternating
Vee=5.0V, V5=OV, V3=4V,
Operating current (2)
IDDH
V2=26V,VO=VDDH=30V,
other conditions same as Icc
Input capacitance
C1
T a=25°C, Freq.=1 MHz
See note 2.
I/O capacitance
See note 2.
exceptE10
CLO
Ta=25°C, Freq.=1 MHz
1. Within the specified ranges of YO, V2, V3 and V4
2. Applies to chip part only.
649
EI01, EI02
I
SED1765
• AC Characteristics
• Input Timing
IF~H=1r_tDF~
FR
LP
_
tLO
==:j I
_ _
11:
XSCL
DO to D7
EIO ________________________________. l+--tSUE~
\k,--._ _ _ _ _ _ __
(IN)
RES
GCP
_
) -
INH
~H L
)+--twR~l_
_
~I:.~~~---tHG
---L
1'_.______ts_G_______
'1.------.
twGL - - - - - - - . {
i--tWN-Y
Note: For timing for LP pulse input, omit one XSCL clock cycle.
Ta=-20 to 75°C, Vcc=5.0V±10%
Parameter
Symbol
Condition
Rating
Unit
Min
Typ
Max
tc
71
twCH
30
-
ns
XSCL High pulse width
-
XSCL Low pulse width
twCL
30
-
-
ns
EIO setup time
tSUE
30
tos
30
-
ns
Data setup time
-
-
ns
-
ns
-
ns
-
ns
XSCL-period
Data hold time
tOH
20
XSCL~LP
rising edge
tLO
10
LP~XSCL
rising edge
tLH
100
LP pulse width
tWLH
RES pulse width
twR
100
INH low pulse width
twN
100
GCP high pulse width
twGH
80
GCP low pulse width
twGL
80
FR delay time
tOF
-300
GCP setup time
tSG
100
tHG
100
GCP hold time
,.
See note.
Note: tWLP indicates the time XSLC is LOW as well as the time that LP is HIGH.
650
80
-
+300
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
SED1765
•
Output Timing
GCP
-------------1'--------------tGSD-
LP
1-
'l-tER--1
EIO
(OUT)
--I
tLPSD
tDCL
XSCL
FR
I-
tFRSD---.
INH
1-----
tlHSD
x:
SEG Out
(on)
Ta=-20 to 75°C, VooH=14.0V to 40.0V
Parameter
Rating
Condition
Symbol
Min
EIO output reset time
tER
CL=15 pF
-
120
-
40
ns
2.0
!is
-
2.0
!lS
2.0
!is
-
2.0
!lS
tOCL
LP---.SEG (On) output delay time
tLPSO
SEG---.LP (On) output delay time
tFRSO
INH---.SEG (On) output delay time
tlHSO
-
tGSO
-
GCP---.SEG (On) output delay time
651
Unit
Max
-
EIO output delay time
CL=100 pF
Typ
ns
I
SED1765
•
MECHANICAL SPECIFICATIONS
• Pad Layout
000000000000000000000000000000000000000000000000000000
g
o
o
o
o
o
o
o
o
o
g 186
0
0
0
0
0
0
0
0
0
OLD
g
g
o
o
o
o
o
o
o
o
o
o
o
o
o
g
y
o
o
o
o
o
X
0
0
0
0
0
g
0
0
0
0
0
0
g
D1765D08
o
o
0
0
0
0
0
0
0
g
0
0
000000000000000000000000000000000000000000000000000000
Chip size: 8.80 x 5.62
Pad pitch: 0.134 mm min .
• AI pad (SED1765DoA)
Chip thickness: 0.400 ± 0.025 mm
Pad size, type A: 100 x 100 Ilm (All pads except 36,37,38,39,40)
Pad size, type B: 160 x 100 Ilm (Pads 36,37,38,39,40)
• Au bump pad (SED1765DoB)
Chip thickness: 0.525 ± 0.025 mm
Pad size, type A: 102 x 100 ± 20 Ilm (All pads except 36,37,38,39,40)
Pad size, type B: 186 x 100 ± 20 Ilm (Pads 36,37,38,39,40)
Note: Sizes are specified as x-dimension x y-dimension. X is parallel to the scribe-line.
652
SED1765
•
Pad Coordinates
Pad
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
EI02
EI01
GNO
00
01
02
03
04
05
06
07
NC
SHL
XSCL
TEST
INH
LP
RES
GCP
Vee
FR
VO
V5
V3
V2
VDDH
00
01
02
03
04
05
06
07
08
09
X
Y
3950
3814
3678
3542
3406
3270
3134
2998
2862
2726
2590
2454
2318
2182
1998
1858
1718
1578
1438
1298
1158
1018
878
738
598
458
318
178
38
-102
-242
-382
-522
-662
-802
-1032
-1262
-1492
-1722
-1952
-2182
-2318
-2454
-2590
-2726
-2862
-2998
-3134
-3270
-3406
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
Pad
Number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
653
Name
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
X
Y
-3542
-3678
-3814
-3950
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-3954
-3820
-3686
-3552
-3418
-3284
-3150
-3016
-2882
-2748
2643
2643
2643
2643
2379
2243
2107
1971
1835
1699
1563
1427
1291
1155
1019
883
747
611
475
339
203
67
-69
-205
-341
-477
-613
-749
-885
-1021
-1157
-1293
-1429
-1565
-1701
-1837
-1973
-2109
-2245
-2381
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
I
SED1765
•
Pad Coordinates (cont.)
Pad
Number
Name
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
0100
0101
0102
0103
0104
0105
0108
0107
0108
0109
X
y
-2614
-2480
-2346
-2212
-2078
-1944
-1810
-1676
-1542
-1408
-1274
-1140
-1006
-872
-738
-604
-470
-336
-202
-68
68
202
336
470
604
738
872
1006
1140
1274
1408
1542
1676
1810
1944
2078
2212
2346
2480
2614
2748
2882
3016
3150
3284
3418
3552
3686
3820
3954
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
Pad
654
Number
Name
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
X
Y
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
-2381
-2245
-2109
-1973
-1837
-1701
-1565
-1429
-1293
-1157
-1021
-885
-749
-613
-477
-341
-205
-69
67
203
339
475
611
747
883
1019
1155
1291
1427
1563
1699
1835
1971
2107
2243
2379
SED1765
•
TYPICAL APPLICATION CIRCUIT
DO to 07
GCP
LP
RES
I11111
YOU
YSCL
I-
SHL
LOAD
L
r-;::
EI01
EI02
T SE01766
EI01
EI02
T SE01766
EI01
EI02
T SE01766
EI01
EI02
T SE01766
~6~
~6~
~6~
~6~
~
0101
r-v
0102
0103
~
,---v
[0104
~
0101
~
FR
INH
I-
IV
YOU
r-
0102
0103
I - 0104
--V
~
~
1- 0101
I-
~
~~ 0102
0103
- I - 0104
640 X 480 DOT
1/2400UTY
~
IV
~
IV
SED1703
~6~
-<16~
-<16~
-<16~
EI01
EI02
T SE01766
EI01
EI02
T SE01766
EI01
EI02
T SE01766
EI02
EI01
T SE01766
111111
XSCL
SHL
DO to 07
655
I
THIS PAGE INTENTIONALLY BLANK
656
SED1766
160 SEGMENT DRIVER WITH GRAY SCALE
•
DESCRIPTION
The SED1766 is a 160-bit output LCD segment (column) driver for driving high-capacity LCD panels at duty
cycles higher than 1/100 (up to 1/500). The LSI uses a PWM (Pulse Width Modulation) algorithm to achieve
16-,8- and 4-level gray-scale display without ghosting. Also, an external pulse controller circuit can be used
to control the gray-scale pulse position within the horizontal interval.
This device has been designed for low output resistance, making the SED1766 suitable for STN-type LCD
panels, and yielding gray-scale displays with few contrast disparities.
The LSI features a wide range of LCD drive voltages.
The device uses a high-speed daisy-chain enable system which decreases power consumption and
eliminates the need for separate enable signals for each driver.
The SED1766 is used in conjunction with the SED17 43 common drivers to support a large-capacity STN-type
dot matrix LCD panel.
•
FEATURES
•
•
•
•
•
•
•
•
•
•
Low-power high-speed CMOS technology
160-bit segment (column) driver
Supports 4-,8-, and 16-level gray scale
Supports gray-scale gamma correction
Two parallel 4-bit input data
Shift clock frequency .............. 16 MHz
Duty cycle ............................... 1/100 to 1/500
Adjustable LCD drive voltages
Selectable output shift direction
•
•
•
•
Supports display blanking
Supports high-speed data transfer
Low output resistance
Ability to adjust offset bias of the LCD source from
VDD
• Wide range of LCD voltage .... 14 to 40V
• Supply voltage ........................ 4.5 to 5.5V
• Package .................................. TAB (TOA)
AI pad (DOA)
Au bump (Dos)
SYSTEM BLOCK DIAGRAM
DO-D7
XSCL
LCD
CONTR
LP,FR
YSCL
t--YD
il
SED1766
SED1766
SED1766
SED1766
~6~
~6~
~6~
~6~
ISED1743~
•
•
ISED1743~
ISED1743~
640 x 480
DUTY: 1/480
657
I
SED1766
•
I
BLOCK DIAGRAM
VDDH
V2
V3
VO
Vee
00 -------- 0159
GND
,----;:::====;----1·.. LCD Driver
1
160 bits
V5
FFr ___
~~-
INH
GCP
RES
LP
00 to 03
04 to 07
SHL
EI01
EI02
shift register
XSCL
T
658
SED1766
•
PIN DESCRIPTION
Pin Name
InpuVOutput
00 to 0159
0
Segment drive outputs
DO to D3, D4 to D7
I
4-bit gray-scale data inputs. DO and D4 are the LSBs of each 4-bit nibble.
XSCL
I
Segment data shift clock input. Data is shifted into the driver on the falling edge of XSCL.
LP
I
Segment data latch strobe. Data is latched on the falling edge of LP.
E101, EI02
I/O
GCP
I
Function
Daisy chain enable input/outputs configured by SHL.
Gray-scale reference clock input.
PWM mode control input
RES
I
See timing diagrams. VOFF refers to drive voltages V2 and V3, VON refers to
drive voltages VO and V5. Before RES pulse: VOFF-WON transition mode.
After RES pulse: VON-WOFF transition mode.
Shift direction select input.
SHL
I
FR
I
LCD AC-drive waveform input.
INH
I
Display blanking input. When LOW, all outputs go to OFF levels.
This signal configures E101, EI02 and selects the shift register shift direction.
An is input on DO to D3 and Bn on D4 to D7.
Vcc
-
Logic power supply
Vo, V2, V3, V5, VDDH
-
These voltages should satisfy the following conditions.
GND
I
Ground
LCD drive voltage supply inputs
VDDH~VO>V~7/9VDDH, 2/9VDDH~V3>V5~GND
T
I
Test input
Tie low.
•
ELECTRICAL CHARACTERISTICS
•
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply voltage (1)
Vce
-0.3 to +7.0
V
Supply voltage (2)
VDDH
-0.3 to +45.0
V
Supply voltage (3)
~a, V2, V3, V5
--0.3 to VDDH+0.3
V
VI
-0.3 to Vee+0.3
V
Operating temperature
Topr
-20 to +75
Storage temperature 1
Tstg
-65 to +150
°c
°c
Input voltage
Note:
Drive voltages should satisfy the following conditions: VDDH ~ va ~ V2
~
V3 ~ V5 ~ GND
VDDH
VO
V2
40V
Vce
V3
V5
5V
GND ______L -_ _ _ _ _ _
659
~
_ _ _ _ _ _ _ _ _ _ _ ___
SED1766
•
DC Characteristics
Parameter
T a=-20 to 75°C, V5=OV, unless stated otherwise
Symbol
Condition
Rating
Pin
Typ
Max
4.5
5.0
5.5
-
Supply voltage (1)
Vee
Vee
Supply voltage (2)
VOOH
VOOH
14.0
VO
VO
!vDDH-2.f
V2
719xVDDf
V3,V5
GND
Input voltage
Input voltage (1)
V2
Input voltage (2)
V3, V5
VO~V2~V3~V5
All input 0.8xVec
HIGH-level input voltage
VIH
LOW·level input voltage
VIL
HIGH·level output voltage
VOH
IOH=-O.4 mA
LOW·level output voltage
VOL
IOH=0.4mA
III
GND:,>VI:,>Vec
Input leakage current
I/O leakage current
Quiescent current
ILllo
IGNO
pins.
GND:,>VI:,>Vee
VooH=14.0 to 40.0 V
resistance
VooH=10.0V
Ro
VON=0.5V
VooH=20.0V
V
V
VOOH
V
~.9XVDDH
V
Vee
V
V
V
0.4
V
-
2.0
~A
-
5.0
~
-
25
~
-
2.0
6.5
1.5
3.5
-
1.3
3.0
Vee
-
2.5
5.0
mA
VOOH
-
0.5
1.2
mA
All pins
-
-
8.0
pF
-
-
15.0
pF
Vcc-O.4
GND
All pins
~xcept EIO
EI01, EI02
GND
00 to
0159
VooH=30.0V
See note 1.
40.0
VOOH
Vee
EI01, EI02
GND
V
p.2xVec
VIH=Vce, VIL=GND
Segment output ON
Unit
Min
-
kQ
Vee=5.0V, VIH=VCC,
VIL=GND,
fxseL=10.8MHz,
Operating current (1)
lee
fLP=33.8kHz,
fGep=0.54 MHz,
FR=70 Hz, DO to
D7=FOFO ... , alternating
Vce = 5.0V, V5 = OV, V3 = 4V,
Operating current (2)
IOOH
V2 = 26V, VO = VOOH = 30V,
other conditions same as lec
Input capacitance
C1
Ta=25°C, Freq.=1 MHz
See note 2.
I/O capacitance
except E10
ClIO
Ta=25°C, Freq.=1 MHz
See note 2.
Notes: 1. Within the specified ranges of VO, V2, V3 and V4.
2. Chip package only.
660
EI01, EI02
SED1766
•
o
AC Characteristics
Input Timing
::
~~~~~-_-_-_-_-----1-;=- t-w-lH- - {- r~tO_F:f
__________________
l~tlH-
tLD==11
XSCL
DO to D7
.I- tSUE -
EIO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1______________
(IN)
RES
GCP
_~f=tWR =t'----_
J~~"
1
~~~------.-(~-=-t-HG----
L
__
I
Note: For timing of LP pulse input, omit one XSCL clock cycle.
T a=-20 to 75°C, Vcc=5.0V±10% unless stated otherwise
Parameter
Shift clock period
Symbol
tc
Condition
Rating
Min
Typ
IC operating alone
62
Using enable transfer functior
83
-
100
-
Shift clock HIGH-level pulsewidth
tWCH
25
Shift clock LOW-level pulsewidth
twCl
25
EIO setup time
tSUE
36
Data setup time
tos
30
Data hold time
tOH
20
Shift clock to latch pulse interval
tlO
0
Latch hold time
tlH
200
LP pulsewidth
twlH
RES pulsewidth
twR
See note
80
Max
Unit
ns
ns
-
ns
-
ns
ns
ns
-
ns
-
ns
-
ns
ns
twN
100
-
twGH
80
-
-
ns
GCP HIGH-level pulsewidth
GCP LOW-level pulsewidth
twGl
80
-
-
ns
FR delay time
tOF
-300
GCP setup time
tSG
Applicable to
200
-
GCP hold time
tHG
LP and RES signal
200
-
INH pulsewidth
Note: tWlP indicates the time XSLC is LOW as well as the time that LP is HIGH.
661
ns
+300
ns
-
ns
-
ns
SED1766
•
Output Timing
)--
GCP
-GSD-
LP
I
l-tER-1
tLPSD
EIO
(OUT)
--I tDCL
XSCL
f
FR
-tFRSD-
INH
I
tlHSD
x:
OiOut
VH=0.8xVcc, VL=0.2xVcc, Ta=-20 to 75°C, VDDH=14.0 to 40.0V unless stated otherwise
Parameter
Symbol
Rating
Condition
Min
Typ
Unit
Max
EIO output reset time
tER
-
-
120
EIO output delay time
tDCL
-
45
-
-
0.6
JlS
-
0.8
JlS
-
0.6
Jls
0.6
Jls
CL=15 pF
LP to segment output delay time
tLPSD
FR to segment output delay time
tFRSD
INH to segment output delay time
tlHSD
-
GCP to segment output delay time
tGSD
-
CL=100 pF
662
ns
SED1766
• Timing Diagrams
o 11240 Duty Cycle
240
2
4
3
239
3
239
240
=~=:::>C)C)(
Latch DATA
If-'
----7-,_ _ _ _ _ _ _
------------ ------------RES
2
'-----__ JLILJLJLJL_JLJLJL
LP
FR
240
~
n
-~
------------- ----------------
------------- - - - --,
-llf-'_____________________ -----"L
~
,
LPJl, - - - - - - - - - - - - - - - - ---------- - - - - - - '
XSCL~-~-~-JlDt
:
:
DOtoD7~~~~
CD~
®
'-----__________ ~
EIO®~
---I'------~
'CD
EIO
,
VH=0.8xVcc
VL=O.2xVcc
Notes:
1. Circled numerals denote the position of the device in the cascade chain.
2. With high-speed data transfer, it is necessary to delay the transition of XSCL following the LP pulse falling edge, to ensure that
the minimum LP to XSCL time specification is met.
o
16-level gray-scale data and LCD output waveforms
1··---FR
~r----------~I
I
LP
SEGi
1
I
2
I
3
I
,
4
I
,
5
I
----"1
nil
I2 I3 I
4
I
5
I
~r--
I n-ll n I
_ -.I1......fLJL
••••••••••.. :• :.••••.• ~
•••••.••••••••••••••.••••••••• JLI
.•.••..•... ~~
~
. . . . . . . . . . . . :....:......
.......... ,....,.....
,,
,:
COMi
I n-ll
1 Frame
__________
. . . . . . . . . . . _. . . . . . . .
........
.......
..
E1J2
U •. · · · · •
:.
1-'-
Off-·r
.... n
' . . . . . . . . . . - . . . V4
'.
...
. .. V5
'VO
··_··-JfL ---.--,[ ~~
1....1_·_ _
Selection inierVai
...
'. (1 horizontal interval) .
4-0n
.. V5
....
Jl" .
SEGi
to
COMi
....
663
I
SED1766
LP~~--------------------------------------~----~
Gray
scale data
Gray
scale
0302 01 DO
RES
GCP
0
0
0
0
0
1
0
0
0
1
0
2
0
0
1
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
,
---T---;-+-+-r~+--r-r+-~~--r-F=~~=±,=±,~~=±,=c,~,~,==~,~,=±,=±,~~==~==
, ,
, ,
,, ,
,,,
,
,
, ,,
,,
,
,,
, ,,
11
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
---l---J~'-----------------------------------------------------L-r--rl---
15
1
1
1
1
,
---.Jr'-----------------------------------------------------------;'~
Note: (00, 01, 02, 03) also refer to (04, 05, 06, 07)
664
VON
VOFF
SED1766
o 8-level gray-scale data and LCD output waveforms
I
I
I
------------------------------------------------------FL-
I
Gray
scale
LP.J1I
Gray
scale data
RES~----------------------------~~----------------------------+
0302 01 DO
0
1
0
0
GCP
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
I
I
I
I
21
31
51
61
I
I
I
I
I
I
I
I
I
I
I
7
I
h
I
8 1
I
I
91
I
I
I
I
10
I
I
I
I
I
I
I
111
121
I
I
I
I
I
I
131
I
I
I
14
I
~~'--------------------------------------------------~
1
7
1
1
:
L---T---~I-
I
~r--------------------------------------------~~
1
o 4-level gray-scale data and LCD output waveforms
Gray
scale
Note:
Gray
scale da1a
0302 01 DO
0
1
1
0
0
1
1
1
0
1
2
1
1
1
0
3
1
1
1
1
LP-.I1
I
RES I
GCP
fL
I
n
n
I
11
I
I
I
n
I
12
I
I
I
~
3H
n
I
n
I
14
15
I
I
I
I
I
I
I
~
16
I
I
I
I
I
I
:
I
I
I
I
~
I
LJ
The segment outputs change state on the falling edge of the fifteenth GCP pulse following an LP or RES pulse,
regardless of the value of the gray-scale data.
665
I
SED1766
o
Right-hand PWM mode 16-level gray-scale data and LCD output waveforms
Gray
scale
Gray
scale data
~
I
LP-.Il
03 02 01 DO
GCP
I
I
I
I
I
I
I
I
I
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
L
L
4
0
1
0
0
!-
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
L
12
1
1
0
0
L
13
1
1
0
1
14
1
1
1
0
L
L
15
1
1
1
1
L
I
I
I
~
L
L
L
I
I
I
I
!~
I
I
I
I
I
L
~
666
SED1766
o
Right-hand PWM mode 8-level gray-scale data and LCD output waveforms
Gray
scale
Gray
scale data
LP~~--------------------~~
,
03 02 01 00
,
GCP_...' __--'
0
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
L
,
5
1
1
0
1
L
,
6
1
1
1
0
L
7
1
1
1
1
L
,
L
,
L
,
,
o
L
Right-hand PWM mode 4-level gray-scale data and LCD output waveforms
Gray
scale
Gray
scale data
LP~~--------------------~~
,
03 02 01 00
________~n~----------~
,
0
1
1
0
GCp __~i________~n~
,,
,
0
,
1
1
1
0
1
L
,
2
1
1
1
0
3
1
1
1
1
L
,
,
i
,
,
,
i
L
667
I
SED1766
•
•
TYPICAL APPLICATION CIRCUITS
Large-screen LCD, 1/240 duty cycle
DOlo D7
GCP
LP
RES
IIIIII
r:c--
YDU
YSCL
t- DI01
~
SHL
LOAD
r;:: DI02
----v
'-D103
~
[DI04
----v
rr- g:g~
r- DI04
----v
FR
INH
YOL
EI01
EI02
T SED1766
EI01
EI02
T SED1766
EI01
EI02
T SED1766
EI01
EI02
T SE01766
~6~
~6~
~6~
~ey
~
DI01
~
~
----v
r-
~
DI01
~
f-~
----v
f-~ 0102
' - f-t-
g:~
640 X 480 Pixels
1/240 DUTY
~
----v
SYo1703
~6~
~6~
~E101
XSCL
SHL
DOlo D7
•
~6~
W
EI01J{EI01
EI02
T SE01766
T SE01766
..--<16~
W
EI01
EI02
T SED1766
EI01
EI02
T SED1766
IIIIII
Large-screen LCD, 1/480 duty cycle
DOIOD7~~~~~ii~~i~~i~~i
GCP
XSCL
LP
RES
YDU --H-fnirrtl
YSCL --+-.+-1
SHL --'-+++'-1
LOAD -t++-t+-l
FR-+}++H
INH -1++-1+-1
668
SED1766
•
PAD LAYOUT (SED1766DOA and SED1766DOB)
000000000000000000000000000000000000000000000000000000
0
0
0
0
o
o
o
186
0
o
o
o
o
0
0
0
0
0
o
o
0
OLD
o
0
8o
80
y
o
o
o
0
0
o
0
0
8o
X
o
o
o
80
0
0
0
0
0
0
0
o
o
o
o
o
o
o
o
o
0
0
0
8
D1766DOB
o
o
0
0
8
0
0
000000000000000000000000000000000000000000000000000000
I
Chip size: 8.80 x 5.62
Pad pitch: 0.134 mm min.
* AI pad (SED1766DoA)
Chip thickness: 0.525 ± 0.025 mm
Pad size, type A: 100 11m x 100 11m (All pads except 36,37,38,39,40)
Pad size, type B: 160 11m x 100 11m (Pads 36,37,38,39,40)
* Au bump pad (SED1766Dos)
± 0.025 mm
102 11m x 100 11m ± 20 11m (All pads except 36,37,38,39,40)
186 11m x 100 11m ± 20 11m (Pads 36, 37, 38, 39, 40)
Chip thickness: 0.525 mm
Pad size, type A:
Pad size, type B:
Note: Sizes are specified as x-dimension x y-dimension. X is parallel to the scribe-line.
669
SED1766
•
PAD COORDINATES
Pad
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
EI02
EI01
GNO
00
01
02
03
04
05
06
07
NC
SHL
XSCL
TEST
INH
LP
RES
GCP
Vee
FR
V2
V3
V5
VO
VDDH
00
01
02
03
04
05
06
07
08
09
X
Y
3950
3814
3678
3542
3406
3270
3134
2998
2862
2726
2590
2454
2318
2182
1998
1858
1718
1578
1438
1298
1158
1018
878
738
598
458
318
178
38
-102
-242
-382
-522
-662
-802
-1032
-1262
-1492
-1722
-1952
-2182
-2318
-2454
-2590
-2726
-2862
-2998
-3134
-3270
-3406
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
2643
Pad
Number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
670
Name
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
X
y
-3542
-3678
-3814
-3950
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-4230
-3954
-3820
-3686
-3552
-3418
-3284
-3150
-3016
-2882
-2748
2643
2643
2643
2643
2379
2243
2107
1971
1835
1699
1563
1427
1291
1155
1019
883
747
611
475
339
203
67
-69
-205
-341
-477
-613
-749
-885
-1021
-1157
-1293
-1429
-1565
-1701
-1837
-1973
-2109
-2245
-2381
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
SED1766
Pad
Number
Name
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
0100
0101
0102
0103
0104
0105
0108
0107
0108
0109
X
Y
-2614
-2480
-2346
-2212
-2078
-1944
-1810
-1676
-1542
-1408
-1274
-1140
-1006
-872
-738
-604
-470
-336
-202
-68
68
202
336
470
604
738
872
1006
1140
1274
1408
1542
1676
1810
1944
2078
2212
2346
2480
2614
2748
2882
3016
3150
3284
3418
3552
3686
3820
3954
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
-2643
Pad
671
Number
Name
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
X
y
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
4230
-2381
-2245
-2109
-1973
-1837
-1701
-1565
-1429
-1293
-1157
-1021
-885
-749
-613
-477
-341
-205
-69
67
203
339
475
611
747
883
1019
1155
1291
1427
1563
1699
1835
1971
2107
2243
2379
I
en
m
C
.....
•
m
D
MAX 1.0
MAX 0.8
MAX 0.15
~
m
::0
z
»
r
"tI
»
o
~
C>
m
c
~
m
z
en
o
z
en
g~
a
+1
~
cia
_)(.i+J
+1
'"m
gj
o
(J)
'"
I\)
,,,,Qzill-'\
X 11.51
\
Y -5.755
'_'
"'-"1'18
ill
1 -> 2 --- -> 158 -> 159
L
Output
Input
159 -> 158 -> --- -> 2 -> 1 -> 0
Test input: Normally L.
Pulldown is not built in.
Buffer ability adjustment input:
Vdl
Vd2
The buffer ability for output transfer and that for liquid crystal drive
I
can be varied by the voltage applied to the terminal.
Vdl: Output transfer buffer ability adjustment
VDDH
-
2
Vss
Vd2: Liquid crystal drive buffer ability adjustment
VA
VB
I
Ve
Analog signal input:
Inputs image signals (R, G, and B).
t
3
t
160
t
1
-
2
-
3
Liquid crystal drive segment output:
Outputs the level, based on the analog Signal input
SEGO
-
0
SEG159*
(VA, VB and Ve) data as a sample holder.
The input/output are corresponded as
VA ->SEGO, 3, 6"', VB -> SEG1 , 4, 7"', Ve -> SEG2, 5, 8 " ..
Sample hold reference voltage input;
Reference power of the sample hold circuit;
VeoM
I
VDDH
P
Power supply for high voltage LCD drive circuit.
VDD
P
Power supply for logic circuit.
To input the central electric potential of the analog signal
input (VA, VB, Ve) is the standard.
Vss
P
LSI's common GND:
Shall be externally connected among Vss terminals.
(*) In the case of SED1n1DOA, this is up to 162 outputs and
SEG 162, and the number of terminals increases by two.
676
1
Total: 183
(NC3)
SED1770n1
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Vss=OV)
Parameter
Symbol
Rating
Unit
Supply voltage (1)
VDD
-0.3 to +7.0
V
Supply voltage (2)
VDDH
-0.3 to +25.0
V
Input voltage *1
VID
-0.3 to VDD+0.3
V
Input voltage *2
VIA
-0.3 to VDDH+0.3
V
Storage temperature
Tstg
-65 to +150
°C
Operating temperature
Topr
-20 to +75
°C
Notes: 1. Applies to EI01, EI02, XSCL, LP, OE, SHL, TEST1, and TEST2.
2. Applies to VA, VB, Vc, Vd1, Vd2, and VCOM.
•
DC Characteristics
Parameter
VDDH=15V, and Ta= -20 to +75°C unless otherwise noted)
(Vss=OV, VDD=5V+10%,
Symbol
Condition
Applicable
Rating
Min
Signal
Supply voltage (1)
VDD
VDD
4.5
Supply voltage (2)
VDDH
VDDH
VDD
"H" input voltage
VIH
"L" input voltage
VIL
Input terminal capacity
CID
Ta= 25°
Input leak current
ILiD
0< VI < VDD
"H" output voltage
VOH
IOH=-O.4mA
"L" output voltage
VOL
IOL = O.4mA
ClIO
Ta = 25°C
a < VI < VDD
Input/output
terminal capacity
*1
Vss
ILIIO
Analog input capacity
CIA
Vc
dVO
SEGO
Gv
"1" output current
IOH
*3
"0" output current
IOL
*4
Current consumption (1)
IDD
*5
Current consumption (2)
IDDH
*5
VDD
V
0.2·VDD
V
S.O
pF
VDD
V
Vss
-
0.4
V
-
-
15.0
pF
-
-
15.0
IJ.A
~DDH-l.5
V
SO
pF
SEG 161
-
EI01, EI02, XSCL, LP, OE, SHL, TEST1, TEST2
XSCL, LP, OE, SHL, TEST1, TEST2
Vd2 = 12V, Vvideo = 13V, OE = H
Vd2 = 12V, Vvideo=2V, OE=H
fXSCL = 10MHz, 1H = 63.5I1S, Vvideo=+2-+ 13V, TOE (OE=H) = lOllS, without load
677
V
VDD-O.~
-
Input/output gain
V
IJ.A
VA, VB, Vss+1.5
voltage deviation
-
5.5
17.0
2.0
EI02
Vvideo
-
Unit
Max
-
-
EI01
Input/output leak current
Notes: 1.
2.
3.
4.
5.
-
*2
Analog input voltage
Between-output
O.S·VD[
Typ
-
MAX- MIN = 100
mV
95
-
105
%
-
0.1
-
mA
-
0.1
-
mA
-
-
5
mA
15
mA
I
SED1770n1
•
AC Characteristics
Vss
o
=OV, VDD = 5V±10%, VDDH = 15V, and Ta =-20 to +75°C unless otherwise noted.
Input Timing Characteristics
t
tWLH_
900~o( .
LP
---------------
10%
tLO
",'
~f----__II.
_
----------------------------tLH -
I
XSCL
r-
{tSUE
Parameter
Symbol
Ii
\
/
EIO
---..-..-1
.....+0... . - - - tc
tWCH
..
tc
100
XSCL "H" pulse width
twCH
40
XSCL "L" pulse width
twCL
40
XSCL-to-LP rise time
tLD
40
LP pulse width
LP-to-XSCL time
EIO setup time
.
Rating
Condition
Min
XSCL cycle
tWGL
Typ
-
Max
Unit
-
ns
-
Ils
ns
ns
2.5
-
tLH
1
-
-
Ils
tSUE
50
-
-
ns
*1
tWLH
Notes: 1. Time of XSCL=L and LP=H.
678
ns
SED1770n1
o Output Timing Characteristics
LP
XSCL
tDCL
EIO
90%
10%
SEGout
tL_S_D~~.~9_0_o/c_O
______________________
Parameter
0
Symbol
EIO output delay time
tDCL
EIO output reset time
tER
LP-to-SEGout delay time
tLSD
_________________________
10%
Condition
CL
= 15pF
Rating
Min
Typ
Max
Unit
-
-
40
ns
-
-
12.0
ns
Variable by Vdl and Vd2
*1
Notes: 1. Vd1 = Vd2= 12V, Vvideo= 2-13V, load capacity = 100pF, OE = "H".
679
-
-
15
Ils
I
SED1770n1
•
Signal Timing Example (with specifications of SHl = H, 160 outputs, 1:1 correspondence)
XSCL
EI01 (in)
t t t
----~--~~--------~(~
EI02 (out)
'-------+-VA ________~~S~EG=O~__~S=E=G~3~__~;~:------~I~s=E~G1~5~9~1___
VB __________~-=SE~G~1~__~S=E~G~4~~;~;~~SE~G~1~57~1--------ve ______________~1~S=EG=2~__~__~;~:__~I_S~E~G~15~8~1_____
Sampling is started from the rising edge of the next XSCL after EI01 has fallen.
-I
1-----1H
OE~
~______~,~~--~____~,~
't---1h
Lpn,
-l
I
I~
EloJ
,
h
'
,i------J
L--.f--I~
I
sa~----~~n~:--~,,~~-----+~n~i--~(~~----~
Ves
\
i
~---n
u
:
:~-~--I(~
:\
I
~
~
/ , / /
? ?
/
)~
/
/
/
i~
/
/
Sa : Analog switch input of the sampling circuit
Ves: Electric potential of the sampling capacitor
Idr : Size of the drive current
680
i
i~
i ~~
SEGout-r
Idr
: r
'Iil!
/
(
[
?'~
SED1770n1
•
ALUMINUM MASTER SLICE OPTIONS
On this LSI, the following switchings are available by the aluminum master slice options.
•
Switching of number of output pins
(1) 160 outputs : Outputs EIO at the time of SEG158 sampling.
At this time, the SEG160 and 161 terminals are placed in the NC status.
(2) 162 outputs : Outputs EIO at the time of SEG160 sampling.
Note: This applies if SHL = H. If SHL
•
= L, the first output becomes SEG159 with (1), and SEG161
Correspondence between the shift register and the sampling analog switch
(1) Shift registers and analog switches shall be corresponded at the ratio of 1:1.
(2) One shift register stage shall be connected with three analog switches; and the shift register shall operate
for every 3 stages.
(1) 1 : 1 Correspondence
Shift
Register
(2) 1 : 3 Correspondence
VA
VA
VB
VB
Vc
Vc
Analog
Switch
Analog
Switch
3n+1
3n+2
,
,
Shift
Register
3(n+1)
3n
3(n+1)
S~iP
3n
3n+1
3n+2
SEG Output
[n
=0 -53]
Correspondence with product names
SED1770DOA: Selects 160 outputs for 1) and 1:1 correspondence for 1)
SED1771 DOA: Selects 162 outputs for 1) and 1:3 correspondence for 2)
681
3(n+1)
I
SEG Output
•
with (2).
3(n+1)
SED1770n1
•
PAD LAYOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[J
0
0
0
0
0
0
0
0
0000000000000000000000000000000000000000000000000000000000000000000000
0
<{O
185
0
0
0 00
~
0
1'-0
1'-0
y
Lx
~o
00
0
0
0
(0,0)
0
0
0
0
0
0
0
0
0
0000000000000000000000000000000000000000000000000000000000000000000000
Die size:
Pad pitch:
x
y
11.27mm x 3.79mm
0.12mm (min)
* Metallic bump specifications
Die thickness:
0.25mm
± 0.025mm
Y
X
Bump Size
PAD No.
Bump size A
350l-lm x 150l-lm ± 2Ol-lm
Bump size B
200l-lm x 150l-lm ± 2Ol-lm
D ................. i.., .... ,...
UUllltJ .,ILv V
I"\~
•• _ "
~;:)J..l111 A
...
~I"'\"._
I;:)UI-lIII I
I
,...n .. _
LV).!III
23,24,28,29,30,31
15,16,17,18,19,20,21,22,25,26,27,
32,33,34,35,36,37
,....,,,'-_ .... 1-,- _ _ I
(The X in X and Y of the bump size shall be the direction parallel to the scribe line.)
682
_""_
I V'"'" '"dll dDuv"
SED1770n1
•
Unit = 11m
PAD COORDINATES
Pad
Number Name
1
SEG148
SEG149
2
SEG150
3
SEG151
4
SEG152
5
SEG153
6
SEG154
7
SEG155
8
SEG156
9
10
SEG157
11
SEG158
12
SEG159
13 SEG160*
14 SEG161*
15
TEST1
16
OE
17
LP
18
XSCL
19
SHL
20
EI02
21
EI01
22
TEST2
23
Vss
24
VOOH
25
Vd1
26
Vd2
27
VCOM
28
Vss
29
VOD
VOOH
30
Vss
31
VA
32
33
(NC)
VB
34
35
(NC)
36
Vc
37
(NC)
SEGO
38
39
SEG1
40
SEG2
41
SEG3
42
SEG4
43
SEG5
44
SEG6
X
Y
5210
5090
4970
4850
4730
4610
4490
4370
4250
4130
4010
3890
3770
3650
3400
3150
2900
2650
2400
2150
1900
1650
1270
830
440
190
-60
-450
-890
-1330
-1770
-2150
-2400
-2650
-2900
-3150
-3400
-3650
-3770
-3890
-4010
-4130
-4250
-4370
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
Pad
Number Name
SEG7
45
46
SEG8
47
SEG9
48
SEG10
49
SEG11
50
SEG12
51
SEG13
52
SEG14
SEG15
53
SEG16
54
SEG17
55
SEG18
56
SEG19
57
SEG20
58
SEG21
59
60
SEG22
61
SEG23
62
SEG24
SEG25
63
SEG26
64
SEG27
65
66
SEG28
67
SEG29
SEG30
68
SEG31
69
SEG32
70
71
SEG33
SEG34
72
73
SEG35
74
SEG36
75
SEG37
76
SEG38
77
SEG39
SEG40
78
SEG41
79
SEG42
80
SEG43
81
82
SEG44
SEG45
83
84
SEG46
SEG47
85
SEG48
86
SEG49
87
SEG50
88
X
y
-4490
-4610
-4730
-4850
-4970
-5090
-5210
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5436
-5100
-4980
-4860
-4740
-4620
-4500
-4380
-4260
-4140
-4020
-3900
-3780
-3660
1699
1699
1699
1699
1699
1699
1699
1343
1223
1103
983
863
743
623
503
383
263
143
23
-97
-217
-337
-457
-577
-697
-817
-937
-1057
-1177
-1297
-1417
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
683
Pad
Number Name
SEG51
89
SEG52
90
SEG53
91
SEG54
92
SEG55
93
94
SEG56
SEG57
95
SEG58
96
97
SEG59
SEG60
98
SEG61
99
SEG62
100
SEG63
101
102
SEG64
103
SEG65
104
SEG66
SEG67
105
SEG68
106
SEG69
107
SEG70
108
109
SEG71
110
SEG72
111
SEG73
SEG74
112
SEG75
113
SEG76
114
SEG77
115
116
SEG78
117
SEG79
SEG80
118
SEG81
119
SEG82
120
SEG83
121
SEG84
122
123
SEG85
124
SEG86
SEG87
125
SEG88
126
SEG89
127
SEG90
128
129
SEG91
130
SEG92
131
SEG93
SEG94
132
X
y
-3540
-3420
-3300
-3180
-3060
-2940
-2820
-2700
-2580
-2460
-2340
-2220
-2100
-1980
-1860
-1740
-1620
-1500
-1380
-1260
-1140
-1020
-900
-780
-660
-540
-420
-300
-180
-60
60
180
300
420
540
660
780
900
1020
1140
1260
1380
1500
1620
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
I
SED1770n1
Pad
Number Name
133
SEG95
134
SEG96
SEG97
135
SEG98
136
SEG99
137
138 SEG100
139 SEG101
140 SEG102
141 SEG103
142 SEG104
143 SEG105
144 SEG106
145 SEG107
146 SEG108
147 SEG109
148 SEG110
149 SEG111
150 SEG112
(*)
X
Y
1740
1860
1980
2100
2220
2340
2460
2580
2700
2820
2940
3060
3180
3300
3420
3540
3660
3780
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
Pad
Number Name
151 SEG113
152 SEG114
153 SEG115
154 SEG116
155 SEG117
156 SEG118
157 SEG119
158 SEG120
159 SEG121
160 SEG122
161 SEG123
162 SEG124
163 SEG125
164 SEG126
165 SEG127
166 SEG128
167 SEG129
168 SEG130
X
y
3900
4020
4140
4260
4380
4500
4620
4740
4860
4980
5100
5436
5436
5436
5436
5436
5436
5436
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1699
-1417
-1297
-1177
-1057
-937
-817
-697
SEG160 and 161 become NC in the case of SED1770DoA
684
Pad
Number Name
169 SEG131
170 SEG132
171 SEG133
172 SEG134
173 SEG135
174 SEG136
175 SEG137
176 SEG138
177 SEG139
178 SEG140
179 SEG141
180 SEG142
181 SEG143
182 SEG144
183 SEG145
184 SEG146
185 SEG147
X
y
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
5436
-577
-457
-337
-217
-97
23
143
263
383
503
623
743
863
983
1103
1223
1343
SED1770n1
•
EXTERNAL PACKAGE DIMENSIONS
I
I
I
.L _ _
I
~=+~_
IllC::::~j
L_
L_~-u
685
THIS PAGE INTENTIONALLY BLANK
686
SED17AOT
CMOS LCD SEGMENT DRIVER
•
DESCRIPTION
The SED17AOT is a segment LCD driver for dot-matrix STN liquid crystal display (LCDs). It incorporates 240
segment (column) driver outputs and is designed for use in conjunction with the SED1753 common (row)
driver.
Contributing to making clearer LCD picture quality, this IC employs the high-speed enable chain method and
is slim-chip configuration which is more advantageous for miniaturization olthe LCD panel. SED17 AOT is also
capable of low-voltage and high-speed logic operations and fits to a wide range of applications .
•
FEATURES
•
Number of LCD drive output segments ....................... 240
•
Low voltage operation ................................................. 2.7V min.
•
High duty drive ............................................................ 1/500 (an example)
•
Wide LCD drive voltage range .................................... +8 to +42V (Voo = 3 to 5.5V)
•
High speed and low power consumption data transfer is possible by adoption of the 8-bit bus enable chain
method:
Shift clock frequencies: ............................................... 30.0MHz (5V±10%)
20.0MHz (3.0V)
18.0MHz (2.7V)
•
Slim-chip configuration
•
Non-bias display-off function
•
Pin-selection of the output shift direction is available
•
Offset bias regulation of LCD power for respective VOOH and GND levels is possible
•
Logic operation power supply ..................................... 2.7 to 5.5V
•
Shipped status ............................................................ TCP SED17 AOT**
•
This IC is not radiation resistant
687
I
SED17AOT
•
BLOCK DIAGRAM
0240 - ------------------------------------- 01
VDDHL
VOL
V2L
V3L
V5L
VDDHR
LCD Driver
240 Dot
r
-
VOR
V2R
V3R
V5R
(I
Level Shifter : 240 Bit
lr
FR
DSPOF
Latch : 240 Bit
LP
11
Vee
GNDL
1*
I
DO-D7
(I t
~
XSCL
EI02
r
Data Register : 240 Bit
Bidirectional Shift Register
688
1
GNDR
y SHL
:"l EI01
SED17AOT
•
PIN DESCRIPTION
Pin Name
1/0
Numbers of Pins
Description
010240
0
LCD driveing segment (column) output
The output varies at the falling edge of LP .
240
DO- D7
I
Display data input terminals
8
XSCL
I
For input of the shift clock signals of the display data
(Falling edge trigger)
1
LP
I
For input of the latch pulse signals of the display data
(Falling edge trigger)
1
Enable 1/0
Set to I or 0 is determined by the SHL input level.
The output is reset by the LP input and when 240 bit
equivalent data are recieved, it falls to "L" automatically
2
Shift durection selection, and EIO terminal 1/0 control
signal input
When data are input to terminals DO, D1, .... D7
in order of FO, F1, .... F7 first, and in the order of
LO, L 1, outputs are as follows is as follows:
1
EI01
EI02
1/0
SHL
I
F (First), L (Last)
S
EIO
Output
I
H
0240 0239 0238
03
02
01
EI01
L
F7
F6
F5 ....
L2
L1
LO
0
I
H
LO
L1
L2
F5
F6
F7
I
0
L
Note:
FR
I
....
EI02
The relation between the data and segment output are determined independently from the number of the shift clocks.
1
For input of alternating current LCD drive signals
Vee, GNDL,
GNDR
Power Logic operation power supply: GND: 0 V Vee: +3, +5 V
supply
3
VDDHl, VDDHR
VOL, VOR
V2l, V2R
V3l, V3R
V5l, V5R
Power LCD drive circuit power supply VDDH
supply
"
VO
"
V2
"
V3
"
V5
10
DSPOF
I
GND: 0 V, VDDH: 14 -42V
VDDH;::: Vo;::: V2;::: 7/9 Vo
2/9 Vo;::: V3;::: V5;::: GND
1
For forced bias fixed input
"L" level output is forcefully made to V5 level.
* When using this function, comvined use with SED1703
is not applicable
Total
689
268
SED17AOT
•
FUNCTION OF EACH BLOCK
•
Enable Shift Register
•
When the enable signal is in disabled state, the
internal clock signal and the data bus are fixed to
"L", thus going into a power saving mode.
When using multiple number of segment drivers,
make cascade connection of EIO terminals of
respective drivers to connect the EIO terminal of
the top driver to "GND".
Latch
It takes in the content of the data register at the
falling edge trigger to transfer the output to the
level shifter.
The enable shift register is a bidirectional shift
register of which the shift direction is being selected by the SHL input and the shift register
output is used to store data bus signals into the
data register.
•
Level Shifter
This is a level interface circuit to convert the
voltage level of signals from the logic operation
level to LCD drive level.
•
Since the enable control circuit automatically
senses completion of receiving 240 bit equivalent
data to transfer the enable signal automatically,
control signal of a separate control LSI is not
needed.
LCD Driver
It outputs the LCD driving voltage.
Given below are the relations between data bus
signals, alternating current signal FR levels and
segment output voltages.
---
DSPOF
•
Data Register
Data Bus
Signal
H
This register works to make series or parallel
conversion of data bus signals according to the
enable shift register output. Consequently, the
relations between the serial display data and
segment outputs are determined independently
from the number of shift clock inputs.
H
L
L
690
-
FR
Driver Output
Voltage
H
Vo
L
Vs
H
V2
L
V3
-
V5
SED17AOT
•
TIMING DIAGRAM
In case of 1/240 Duty (an example)
240
234
239 240
Latch Data
2
239 240
-----~-----~
LP
x
----P--r~~~~-u~
X X X X~ ~ ~ ~ ~ _---"-'-X---'-'X'----'X'-'-----_
f--+-----------~
FR
LP
XSCL
"X'-3-
DO to 07 --'---30~X~1--,Xc-r-2
---JVUUl----JVUUl----m
EIOG)
EIC?®
EIO@
X30 X 1X2X3
~I"
G)
m
X30 X 1X2 X3
m.
'Xr--3'-0-"'X~1"X~
--I
®
1
-
I
-
L
-
G) to @ stands for the cascade numbers of the driver.
* When making high speed data transfer, it becomes necessary to secure
a longer XSCL cycle when determining the LP pulse insertion timing in order
to maintain the specified value of LP ~ XSCL (tLH).
nnnn
~ ~ ~ L-(
LP
-.J
Latch Data
~(
,
FR
H
,
1
,
L
«
~(
~(
«
:
'I
---RJLJUL
,
DSPOF
..........................(
V2
V3·
V5
.......................(
691
,
~
'H
(E-I_L-i-----l.
VO
,
H
L
I
SED17AOT
•
ELECTRICAL CHARACTERISTICS
•
Absolute Maximum Ratings
Parameters
Supply voltage (1)
Codes
Ratings
Units
Vee
VOOH
Vo, V2, Va, Vs
V,
Vo
-0.3 to +7.0
-0.3 Vee +0.3
V
V
V
V
V
101
20
mA
Working temperature
Topr
-30 to +85
°C
Storage temperature
Tstg
-55 to +100
°C
Supply voltage (2)
Supply voltage (3)
Input voltage
Output voltage
EIO output current
-0.3 to +45.0
-0.3 to VOOH +0.3
-0.3 to Vee +0.3
Note 1: All the voltage ratings are based on GND =OV.
Note 2: The storage temperature 1 is applicable to independent chips and the storage temperature 2 is applicable to the TCP
modular state.
Note 3: Yo, V2, V3 and V5 should always be in the order of VDDH ~ Vo ~ V2 ~ V3 ~ V5 ~ GND.
VDDH
VO
V2
42V
V3
V5
Vee
5V
GND
GND
Note 4: If the logic operation power goes into a floating state or if Vee drops to 2.6V or below while the LCD driving power is
being applied, the LSI may be damaged. Therefore, keep from occurrence of the aforementioned status.
Specifically, pay close attention to the power supply sequence at times of turning the system power on and off.
692
SED17AOT
•
DC Characteristics
Parameter
Unless otherwise specified, GND = VS = OV, Vcc = +S.OV ± 10%, Ta = -30 to 8SoC
Symbol
Supply voltage (1)
Recommended working
voltage
Workable voltage
Supply voltage (2)
Supply voltage (3)
High level input voltage
Vee
VO
-
VO
V2
V3
V,H
Function only
Recommended value
Recommended value
VDD= 2.7-5.5V
Low level input voltage
V,l
High level output voltage
Low level output voltage
VOH
Val
Input leak current
III
I/O leak current
Static current
ILllo
IGNO
Output resistance
RSEO
In-chip deviation of output
resistance
Mean working current
consumption (1)
ARsEG
Icc
Mean working current
consumption (2)
10
Input terminal capacity
CI
1/0 terminal capacity
CliO
Applicable
Pin
Vee
VOL, VOOHL
Condition
Vee =
2.75.5V
VOR,VOOHL
V2L, V2R
V3L, V3R
E101, E102, FR
00-07, XSCL
SHL, LP,
OSPOF
E101, EI02
L 10H =-0.6mA
I
10l= 0.6mA
GNO $ V,N $ Vee
GNO $ V,N $ GNO
Va = 14.0 - 42.0V
V,H = GNO, V,l = GNO
AVON
Va = +36.0V,
=0.5V
1/24
Recom- Va = +26.0V,
mended 1/20
condition
AVON = 0.5V
Va = +36.0V, 1/24
00-07, LP, FR
XSCL, SHL
OSPOF
E101, EI02
GNO
000240
010240
Vee = +5.0V, V,H = Vee
V,l = GNO, Ixsel = 5.38MHz
flP = 33.6KHZ, fFR = 70Hz
input data: Checkered
indication, no-load
Vee
Vee = +3.0V
Other conditons are the
same as those when
Vee +5V.
Va = +30.0V
Va
Vee = +5.0V, V3 = +4.0V
V2 = +26.0V, V5 = +O.OV
Other conditions are
the same as those in the
lee column
Freq. = 1 Mhz
DO-07, LP, FR
Ta = 25°C
XSCL,SHL, OSPOF
Independent
EI01, EI02
chips
693
Min
Typ
Max
Unit
2.7
14.0
-
5.5
40.0
V
V
8.0
7/9 Va
GNO
0.8 Vee
-
42.0
Va
2/9 Va
-
V
V
V
V
-
-
0.2Vee
V
Vec-O.4
-
-
-
-
0.4
V
V
-
-
2.0
IlA
-
-
5.0
25
IlA
IlA
1m
-
-
-
0.80
1.1
-
0.85
1.2
-
-
95
Q
-
0.75
1.7
mA
-
0.3
0.9
-
0.25
1.4
mA
-
-
8
pF
-
-
15
pF
I
SED17AOT
•
Working Voltage Range Vee - Vo
The Vo voltage should be set up within the Vee - Vo working voltage range given below.
Vo
(V)
50
42
40
30
28
20
10
o
2.0
2.7
3.0
4.0
Vee
694
5.0
(V)
6.0
SED17AOT
• AC Characteristics
o Input Timing Characteristics
Parameter
XSCLcycie
XSCL high level pulse duration
XSCL low level pulse duration
Data setup time
Data hold time
XSCL ~ LP rise time
LP ~ XSCL fall time
LP high level pulse duration
FR delay allowance
EIO setup time
Input signal variation time
DSPOF signal variation time
Parameter
XSCLcycie
XSCL high level pulse duration
XSCL low level pulse duration
Data setup time
Data hold time
XSCL ~ LP rise time
LP ~ XSCL fall time
LP high level pulse duration
FR delay allowance
EIO setup time
Input signal variation time
DSPOF signal variation time
Symbol
tc
tWCH
twCL
tos
tOH
tLO
tLH
twLH
tOF
tSUE
trl, tfl
fr2, tf2
Symbol
tc
twCH
twCL
Conditions
*2
All timing signals are based
on 20% and 80% of Vcc
*1
Min.
33
9
9
5
5
-0
25
15
-300
5
*3
-
Conditions
Vcc = 3.0 to 4.5V
*2
All timing signals are based
on 20% and 80% of Vcc
I
tos
tOH
tLD
tLH
twLH
tOF
tSUE
tr, tf
fr2, tf2
*1
*3
Min.
50
55
15
15
10
10
-0
30
25
-300
10
-
Max.
-
+300
50
100
Max.
+300
50
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: *1. The "!wLH" specifies the time when the LP is set at "H" and, at the same time, when XSCL is at "L", when LP is being
input while XSCL is at "L".
*2. High speed operation of the shift clocks (XSCL) should only be made under a condition of tr + tf S; (te - \weL - \weH).
*3. When the making high speed data transfer using conditions shift clocks, tr + tf of the LP signals should be up to (te +
\weH - tLD - \wLH - tLH) at the maximum.
695
I
SED17AOT
o Output Timing Characteristics
FR
LP
XSCL
EI01,2
(OUT)
___________t_DC_L_~
SEG
Vcc = +5.0V ± 10%, Vo = +14.0 to +42.0V
Parameter
EIO reset time
EIO output delay time
LP ~ SEG output delay time
FR ~ SEG output delay time
Symbol
tER
tOCl
tlSO
tFRSO
Conditions
Min.
Cl=15pF
(EIO)
-
Cl=100pF
(0 n)
Max.
Units
50
25
200
400
ns
ns
ns
ns
VCC = +2.7 to 4.5V, Vo = +14.0 to +2S.0V
Parameter
EIO reset time
EIO output delay time
LP ~ SEG output delay time
FR ~ SEG output delay time
Symbol
tER
tOCl
tLso
tFRSO
Conditions
Cl=15pF
(EIO)
Cl = 100 pF
(0 n)
696
Min.
Max.
Units
-
SO
50
400
SOO
ns
ns
ns
ns
SED17AOT
•
A CONNECTION EXAMPLE
--------- -- - - --- -- --- - - ---
XSCL
DO-D7
XSCL UOO
-07
O~POF FRSHLLP
J_VCC
GN'l:" EI01
EI02
SED17AO(1)
01 1
240
SE~~~~~~ 8
I
I
I
XSCL UOO OSPOF FR LP
SHL
EI01
EI02
SED17AO(8)
01 1
10240
U
VCC
-07
240
10240
SED1753(1) 01
DI01
-
DIO
YSCL
t
120
1£
SHL
[
DI02
SEL
DI3
-
0120
640
X 3 x 480 dots
1/240 duty
SED1753(2)
01
DI01
-
t
1£
120
SHL
SEL
DI3
0120
DI02
-------------------------------------------------------
SED1753(3) 01
' - - DI01
~'--
t
120
£
SHL
SEL
DI3
0120
[
DI02
SED1753(4) 01
DI01
t
120
£
SHL
SEL
DI3
0120
DI02
024~
240
D£ EI02
GND
SHLuoo
EI01
XSCL -07 OSPOF FR LP
LP
1
I
I
02401
101
SED17AO(1)
101
XSCL -07 OSPOF FR LP
------
FR
----- -
DSPOF
LDO-D7
XSCL
- - ----- - ---
697
240
SED17AO(8)
SED17AOx8
EI02
EI01
---- GN~ SHLuoo
I
I
SED17AOT
•
TCP PIN ARRANGEMENT EXAMPLE (FOR REFERENCE)
Oany
Oany
Oany
0240
0239
0238
0237
VOOHL
VOL
V2L
V3L
V5L
GNOL
Vee
NC
EI02
DO
01
02
03
04
05
06
07
XSCL
OSPOF
LP
EI01
FR
SHL
NC
NC
GNOR
V5R
V3R
V2R
VOR
VOOHR
,
04
03
02
01
Oany
Oany
Oany
698
SED17AOT
•
PACKAGE DIMENSIONS
-1
_ i
I:
~I
,I
~I
L-J
9\78"OXltl/ll
9vB"OX\iVl!
D
I
I
!
!
I
00';::<::
699
------J
I
THIS PAGE INTENTIONALLY BLANK
700
VI. HIGH-DUTY LCD
COMMON DRIVERS
1996
DATABOOK
GRAPHICS
PRODUCTS
701
THIS PAGE INTENTIONALLY BLANK
702
•
HIGH-DUTY LCD COMMON DRIVERS
Part Number
SED
1190
SED
1191
SED
1610
Discontinued?
Yes
Yes
Yes
Yes
Yes
Yes
Replacement
No
No
No
SED
167x
SED
167x
SED
167x
SED
1630
SED
1631
SED
1632
SED
1633
Yes
SED
1634
Yes
SED
1635
Yes
SED
167x
SED
167x
SED
167x
SED
1651
SED
1733
SED
1741
SED
1743
SED
1753
No
No
No
No
No
-
-
-
-
-
SED
1755
No
-
64
64
86
68
100
86
100
100
100
100
100
100
160
120
240
1/64
to
1/128
1/64
to
1/128
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/64
to
1/300
1/100
to
1/400
11100
to
1/500
1/100
to
1/500
1/100
to
1/500
1/100
to
1/500
LCD Voltage (V)
-14 to -14 to -12 to -12 to -12 to -12 to -12 to -12 to
-28
-28
-25
-25
-28
-28
-28
-28
-8 to
-28
-8 to
-28
14 to
40
14 to
42
14 to
40
8 to
42
8 to
42
x
Supply Voltage
5V
x
x
x
Data Bus (bits)
1
x
x
x
x
3V
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2.5
2.5
2.0
2.0
2.0
2.0
2.0
(5V),
1.0
(3V)
2.0
(5V),
1.0
(3V)
2.0
(5V),
1.0
(3V)
2.0
(5V),
1.0
(3V)
2.5
2.5
(5V),
1.25
(3V)
2.5
(5V),
1.25
(3V)
1180/
81
1181
1600/
01
1600/
01
1600/
01/20
1600
1600
1600
1570,
1600
1648
17221
24
17421
44
17421
44
17521
58
1756
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
-.J
Clock Frequency, max
(MHz)
o
w
Companion Chips
Panel Type
Passive
MIM
TFT
(continued)
-
L_
!
I
Duty Cycle
Resolution of commons
I
I
I
•
HIGH-DUTY LCD COMMON DRIVERS (continued)
Part Number
Package
Die
AI
Au
SED
1190
DOA
SED
1191
DOB
SED
1610
SED
1630
DOA
SED
1631
DOA
DOB
SED
1632
DOA
149
240
SED
1633
D1A
D1B
SED
1634
D1A
D1B
SED
1635
D1A
D1B
SED
1651
DOA
149
149
149
153
SED
1733
DOA
SED
1741
SED
1743
SED
1753
D1B
D1B
DOB
108
108
TOA
TOA
180
TOA
819
835
COG
I P""
-..j
~
Pad Pitch
(11m)
TAB 2 Sided
Lead
Pitch (11m)
QFP Thin
FOA,
FOB
F5A,
Thick
F5B2
# of Pins
80
705
""mbo<
SED
1755
DOA
190
170
I
i
I
i
FOB
F5B
FAA
FOA
80
713
100
721
80
727
FOA
733
741
Notes:
1. Some packages of certain parts labeled with # are still under development.
747
759
771
783
128
795
805
849
SED1190
CMOS LCD 64·COMMON DRIVERS
•
DESCRIPTION
The SED1190 is a dot matrix LCD common (row) driver for driving high-capacity LCD panel at duty cycles
higher than 1/64. The LSI uses two serially connected, 32-bit shift registers to hold the display data, and level
shifter converts the TTL level 64-bit parallel data from the shift registers to levels suitable for use by the LCD
drive circuitry. The SED1190 generates common drive signals using the voltages supplied to LCD drive
voltages pins.
The SED1190 is used in conjunction with the SED1180 (64-bit row driver) to drive a large capacity dot matrix
LCD panel.
•
FEATURES
• Low-power CMOS technology
• Wide range of LCD voltage: -14V to -25V
• 64-bit common (row) driver
• Supply voltage: 5.0V ±10%
• Display blanking
• Package: ............................... QFP1-80 pin (FaA)
QFP5-80 pin (FSA)
DIE: AI pad chip (DOA)
• Duty cycle: 1/64 to 1/128
• Daisy chain enable support
•
SYSTEM BLOCK DIAGRAM
I
DO - 03
XSCL
LP, FR
LCD
CONTR
-
YSCL
YO
I
I SE01190 ~
SE01180
SE01180
SE01180
SE01180F
~~
~6~
~~
~~
256SEG x 64 COM
DUTY: 1/64
705
SED1190
•
BLOCK DIAGRAM
o - - - - - -COM- - - - -
LAT
01
:1
>-j
Latch
b
FR
Voo
V2
V3
VSSH
32 bits
Level Shifter
32 bits
--
Shift Register
32 bits
----<
Voltage Control
r
~
VSS
LCD Driver
,---.
YSCL
31
)-----J'
)-----J'
'}----/
~
Shift Register
32 bits
Level Shifter
32 bits
LCD Driver
32 bits
DO
--
'}----/
'}----/
32
------COM-----
63
• PIN CONFIGURATION
DO
VSSH
V.
NC
NC
NC
NC
V,
Vss
V DD
NC
01
LAT
INH
FR
YSCL
SED1190
o
Index
706
COM39
COM38
COM3?
COM36
COM35
COM34
COM33
COM32
COMO
COM1
COM2
COM3
COM4
COM5
COM6
COM?
SED1190
Number
Name
Number
Name
Number
Name
Number
Name
1
COM31
21
COM11
41
COM40
61
COM60
2
COM30
22
COM10
42
COM41
62
COM61
3
COM29
23
COM 9
43
COM42
63
COM62
4
COM28
24
COM 8
44
COM43
64
COM63
5
COM27
25
COM7
45
COM44
65
DO
6
COM26
26
COM 6
46
COM45
66
VSSH
7
COM25
27
COM 5
47
COM46
67
V4
8
COM24
28
COM4
48
COM47
68
NC
9
COM23
29
COM3
49
COM48
69
NC
10
COM22
30
COM2
50
COM49
70
NC
11
COM21
31
COM 1
51
COM50
71
NC
12
COM20
32
COMO
52
COM51
72
V1
13
COM19
33
COM32
53
COM52
73
Vss
14
COM18
34
COM33
54
COM53
74
Voo
15
COM17
35
COM34
55
COM54
75
NC
16
COM16
36
COM35
56
COM55
76
01
17
COM15
37
COM36
57
COM56
77
LAT
18
COM14
38
COM37
58
COM57
78
19
COM13
39
COM38
59
COM58
79
INH
FR
20
COM12
40
COM39
60
COM59
80
YSCL
NC = Not connected
•
I
PIN DESCRIPTION
Pin Name
Function
COMO to COM63
LCD common drive outputs
01
Serial data input
Transparent latch control input:
LAT
LAT
H
L
01
01 latch output
H
H
L
L
X
01 latch
DO
Serial data output
YSCL
Serial data shift clock. Data is shifted through the controller on the falling
edge of this clock
FR
LCD AC-drive signal input
INH
Active-low blanking input
Voo, Vss
Logic power supply inputs
V1, V4, VSSH
LCD drive power inputs
Voo 2 V1 2 V4 2 VSSH
707
SED1190
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Supply voltage (1)
Symbol
Ratings
Unit
Vss
-7.0 to +0.3
V
-28.0 to +0.3
V
VSSH
Supply voltage (2)
V1, V4
VI
Vss -0.3 to +0.3
V
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-55 to +125
°C
Soldering temperature and time
Tsol
260, 10
°C, S
Input voltage
Notes:
1. All voltages referenced to a VDD of 0 V.
2. V1 and V4 must satisfy the relationship VDD
~
V1, V4
~ VSSH
3. Exceeding the absolute maximum ratings can cause permanent damage to the device. Functional operation under these
conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally
stressing the package during board assembly.
708
SED1190
•
DC Characteristics
Parameter
Supply voltage (1)
(VDD = OV, VSS = -S.O V ±10%, Ta = -20 to 7S°C)
Symbol
Vss
V1
V4
Supply voltage (2)
Recommended VSSH
VSSH
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
VIH
VIL
VOH
VOL
Input leakage current
Output leakage current
Shift clock
Frame signal
Input capacitance
III
ILO
YSCL
Common output on
resistance
ReOM
Quiescent current
Conditions
FR
CI
10
Operable VSSH (see note)
10H =-0.6 mA
10L = 0.6 mA
OV"?:.VI"?:.VSS
o V"?:. Vo"?:. Vss
Ta = 2SoC
I
Rating
Typ
-S.O
0.2Vss
Vss-o.3
-0.4
-
-
-
Max
-4.S
VDD
VDD
-14.0
-5.0
VDD+0.3
0.8Vss
-
Unit
V
V
V
V
V
V
V
V
V
Vss+0.4
2.0
J.lA
S.O
2.S
J.lA
MHz
1/60
8.0
1.0
1.3
2.0
30.0
S
pF
-
O.OS
-
O.OS
-
VSSH = -20.0 V
VSSH=-14.0V
VSSH =-9.0V
VSSH =-S.OV
-
S.O
0.8
0.9
1.3
3.0
VSSH = -2S V, VSSH = -S.S V,
VI= VDD
-
O.OS
30
J.lA
-
3.0
8.0
J.lA
-
3.0
8.0
J.lA
2S.0
SO.O
J.lA
VOH = VDD -o.S V
VOL = VSSH +O.S V
COM bit
SED
1190
Min
-S.S
VSSH
VSSH
-2S.0
-2S.0
-
kll
Vss =-S.OV,
VIH =VDD,
VIL= Vss,
YSCLcycie =
Operating current for
the logic
Iss
FR cycle = 16.7 ms
130 J.lS
(duty SO%), All
"H" output
terminals are
opened at every
data input all
1/128 duty.
VSS =-4.S V,
V1 =-2.0 V,
V4=-18.0V,
YSCL cycle =
Operating current for LCD
IssH
FR cycle = 16.7 ms
130 J.lS
(duty SO%), All
"H" output
terminals are
opened at every
Pull up MOS current
-Ip
data input of
1/128 duty.
Vss = -S.O V, VIL = -S.O V
Applicable to LAT input terminals
10.0
Note: Error free operation is guaranteed in this range butthe output resistance olthe LCD drivers is higher than in the recommended
operating range. It is suggested that the driver is tested with the target LCD panel to determine if performance is acceptable.
709
I
SED1190
•
o
AC Electrical Characteristics
110 Signal Timing
FA
LAT
'--
==>k !
I
I
n: n:t.t--Jn
--J
~
I
X
I
o. ' 1 ' 2
3
n
L-J
x=::
I
63 ' 0
1.'
2
3
n:Lf-ln n: n . n
~y
I
L...J
I
~
~
63
n
~~
0
n
L....J
1
n
L...J
L.
I
DI~~~
DATA~~~
I
I
0:
1:
I
2
3
YSCL~
63:
I
0
1:
2
3
63
0
1
,
,
~
==~~
DO
'0 is the data of COMO
*63 is the data of COM63
LAT
01
YSCL
FA
DO
-------------------~--------VOO
Parameter
Latch pulse cycle time
Latch pulse "H" width
Latch pulse "L" width
Shift clock cycle time
Shift clock "H" time
Shift clock "L" time
Data setup time
Data hold time
Data shift timing
Data shift hold time
Permissible frame signal delay
Input signal rise time
Input signal fall time
Data output delay time
• tr, If =(ICYL -
twLH - twLTL)
Symbol
tCYL
twLTH
twLL
tCYC
twCLH
twCLL
tos
tOH
tST
tSTH
tOFR
tr
tt
tpo
Conditions
-
-
CL = 15pF
12 where If ~ SOns.
710
= OV, Vss =-5.0V ± 10%, Ta =-20 to 75°C
Min
400
180
180
400
110
110 (240)
100 (70)
30
0
125
-500
Typ
Max
-
-
0
500
-
-
170
-
30
..
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SED1190
•
Common Drive
YSCL
~
VIL
:x
FR
i<-
VIH
"
VIL
~
•
-tCLCD-
:x
COM out
tFRCD
'-Vn-Q.5V
Vn +O.5V
VDD ,V1
V1, V4, VSSH
-tIHCD-
INH
r _
_A
\.
VIH = 0.2 x VSS
VIL = 0.8 x VSS
VDD = OV, VSS = -5.0V ± 10%, Ta = -20 to 75°C
Parameter
Symbol
YSCL - COM output delay time
tCLCD
RF - COM output delay time
tFRCD
INH - COM output delay time
tlHCD
Conditions
VSSH = -14.0 to
-25.0V
CL = 100pF
711
Min
Typ
Max
Unit
-
-
3.0
I1s
3.0
I1s
3.0
I1s
-
I
SED1190
•
EXAMPLE OF APPLICATION
(64 x 640 pixels, 1/64 duty ratio)
*2
.. YSCL SED1190
LP
YSC L
YD
YDI S
~
.. LAT
.. DIN
.. INH<
r-----v'
:B~
<
!?
:.
-~
Rt
R
~
~
C/O
64 x 640 Full Dot Graphic Display
SEG
63 - 0
SEG
63 - 0
SEG
63 - 0
SEG
63 - 0
SED1180
SED1180
SED1180
SED1180
1
2
3
10
C
V2
C~+
LCD PANEL
COM
0
Voo
V1
I
I
I
I
I
I
63
0-----63 64---127 128 --- 191 ----- 576 -----639
Vss
F+
0
~
4
5R
EI
EO 4. EI
FR lP
EO-- EI
EO 1 - - - - - - - _ EI
FR lP
FR lP
FRlP
V3
+
z C
+~C
Voo. Vss
V2, V3
4
R
V4
----~
4
0
0
R
4
:0
*1
...! 1000
Vss H
------
FR
lP
ECl ,XSCl
DO loD3
-----------
2
4
2
4
Notes:
1. Current limiting resistors
2. Bypass Vss and VSSH with capacitors of at least 0.01 J.lF
712
2
4
EO
-----
i.
4
SED1191
CMOS LCD 64-COMMON DRIVER
•
DESCRIPTION
The SED1191 is a dot matrix LCD common (row) driver for driving high-capacity LCD panel at duty cycles
higher than 1/64. The LSI uses two serially connected, 32-bit shift registers to hold the display data, and level
shifter converts the TTL level 64-bit parallel data from the shift registers to levels suitable for use by the LCD
drive circuitry. The SED1191 generates common drive signals using the voltages supplied to LCD drive
voltages pins.
The SED1191 is used in conjunction with the SED1181 (64-bit row driver) to drive a large-capacity dot-matrix
LCD panel.
•
FEATURES
• Low-power CMOS technology
• Wide range of LCD voltage: -14V to -25V
• 64-bit common (row) driver
• Supply voltage: 5.0V ± 10%
• Display blanking
• Package: ............................... QFP1-80 pin (FOB)
QFP5-80 pin (F5B)
DIE: AI pad (DoA)
• Duty cycle: 1/64 to 1/128
• Daisy chain enable support
•
SYSTEM BLOCK DIAGRAM
I
DO (SERIAL DATA)
XSCL
LCD
CONTR
LP, FR
YSCL
~
YD
il
I SED1191~
SED1181
SED1181
SED1181
SED1181
~~
~~
~~
~~
256 SEG x 64 COM
DUTY: 1/64
713
SED1191
•
I
BLOCK DIAGRAM
o -- -- - -COM- - - --
01
~
b
Latch
----------.
YSCL
----.
FR
VSS
VDD
V1
V4
VSSH
)-----------/
)-----------/
)-----------/
)-----------/
)-----------/
~
~
LCD Driver
32 bits
Level Shifter
32 bits
Shift Register
32 bits 1---1----
Voltage Control
~
Shift Register
32 bits
Level Shifter
32 bits
LCD Driver
32 bits
32 - - - - - - COM-
•
31
----
4--1----
DO
r-
63
PINOUT
DO
VSSH
V.
NC
NC
NC
NC
V,
Vss
VDD
NC
01
YSCL
INH
FR
NC
SED1191
o
Index
714
COM39
COM38
COM3?
COM36
COM35
COM34
COM33
COM32
COMO
COM1
COM2
COM3
COM4
COM5
COM6
COM?
SED1191
•
Number
Name
Number
Name
Number
Name
Number
Name
1
COM31
21
COM11
41
COM40
61
COM60
2
COM30
22
COM10
42
COM41
62
COM61
3
COM29
23
COM9
43
COM42
63
COM62
4
COM28
24
COM 8
44
COM43
64
COM63
5
COM27
25
COM7
45
COM44
65
DO
6
COM26
26
COM6
46
COM45
66
VSSH
7
COM25
27
COM 5
47
COM46
67
V4
8
COM24
28
COM4
48
COM47
68
NC
9
COM23
29
COM 3
49
COM48
69
NC
10
COM22
30
COM2
50
COM49
70
NC
11
COM21
31
COM 1
51
COM50
71
NC
12
COM20
32
COMO
52
COM51
72
V1
13
COM19
33
COM32
53
COM52
73
Vss
14
COM18
34
COM33
54
COM53
74
VDD
15
COM17
35
COM34
55
COM54
75
NC
16
COM16
36
COM35
56
COM55
76
01
17
COM15
37
COM36
57
COM56
77
YSCL
18
COM14
38
COM37
58
COM57
78
19
COM13
39
COM38
59
COM58
79
INH
FR
20
COM12
40
COM39
60
COM59
80
NC
PIN DESCRIPTION
Pin Name
COMO to COM63
Function
LCD common drive outputs
01 •
Serial data input
DO
Serial data output
YSCL
Serial data shift clock. Data is shifted through the controller on the
falling edge of this clock
FR
LCD AC-drive signal input
INH
Active-low blanking input
VDD, Vss
Logic power supply inputs
V1, V4, VSSH
LCD drive power supply inputs
VDD ~ V1 ~ V4 ~ VSSH
715
I
SED1191
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Supply voltage (1)
Symbol
Ratings
Unit
Vss
-7.0 to +0.3
V
-28.0 to +0.3
V
VSSH
Supply voltage (2)
V1, V4
VI
Vss -0.3 to +0.3
V
Operating temperature
Topr
-20 to +75
Storage temperature
Tstg
-55 to +125
Soldering temperature and time
Tsol
260, 10
°e
°e
°e, S
Input voltage
Notes:
1. All voltages referenced to a VDD of 0 V.
2. V1 and V4 must satisfy the relationship VDD
~
V1, V4
~
VSSH
3. Exceeding the absolute maximum ratings can cause permanent damage to the device. Functional operation under these
conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally
stressing the package during board assembly.
716
SED1191
•
DC Characteristics
(Voo = OV, Vss = -s.O V ±10%, Ta = -20 to 7S°C)
Parameters
Symbol
Supply voltage (1)
Vss
V1
V4
VSSH
VIH
VIL
VOH
VOL
III
ILO
YSCL
FR
CI
Supply voltage (2)
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
Shift clock
Frame signal
Input capacitance
COM output on
resistance
Quiescent current
Operating current for
the logic
RCOM
IQ
Issop
Operating current for LCD ISSHOP
Condition
Rating
Min
Typ
Max
-S.O
-4.S
-S.S
VSSH
Voo
Voo
VSSH
-2S.0
-14.0
0.2xVss
Voo+0.3
Vss-0.3
0.8xVss
-0.4
Vss+O.4
O.OS
2.0
O.OS
S.O
2.S
1/60
S.O
8.0
-
IOH =-0.6 mA
IOL= 0.6 mA
OV";' VI";'VSS
V.,;, Vo";'Vss
-
o
Ta = 2SoC
VSSH = -14.0 V, VOH = Voo-O.S V,
VOL = VSSH+O.S V COM.! bit
VSSH = -18.0 V, Vss = -S.S V,
VI= Voo
FR cycle = 130 Ils
FR cycle = 130 Ils
Vss =-S.O V,
VIH = Voo,
VIL = Vss,
YSCL cycle =
130llS
(duty SO%), All
"H" output
terminals are
opened at every
data input all
1/128 duty.
Vss =-4.S V,
Vl=-1.8V,
V4 = -16.2 V,
VSSH = -18.0 V,
YSCL cycle =
130llS
(duty SO%), All
"H" output
terminals are
opened at every
data input of
1/128 duty.
Unit
V
V
V
V
V
V
V
V
IlA
IlA
MHz
Sec
pF
-
2.0
4.0
kQ
-
O.OS
30.0
IlA
-
3.0
8.0
IlA
I
-
70
100
IlA
Note: Errorfree operation is guaranteed in this range but the output resistance of the LCD drivers is higher than in the recommended
operating range. It is suggested that the driver is tested with the target LCD panel to determine if performance is acceptable.
717
SED1191
•
o
AC Characteristics
110 Signal
FR
,,~,
==x~+:
,
,
0'
YSCL
1:
________~~x~~____________x===
2
3
0
~
,
2
3
o
63
,
Ol~
~
,
,
,
DO
,
,
,
I
,
I
==~~
*0 is the data of COMO
*63 is the data of COM63
YSCL
01
-tDFR){
J£<~D
FR
DO
(VOO
=OV, Vss =-5.0 V ±1 0%, Ta =-20 to 75°C)
Rating
Parameter
Symbol
Conditions
Unit
Min
Typ
Max
500
-
ns
Shift lock cycle time
tCYC
Shift lock "H" width
tWCLH
110
-
-
ns
Shift lock "L" width
twCLL
240
-
-
ns
tos
70
-
ns
Data hold time
tOH
30
-
-
ns
Permissible frame signal delay
tOFR
-500
0
500
ns
Input signal rise time
tr
-
-
50
ns
Input signal fall time
tt
-
-
50
ns
170
ns
Data setup time
Data output delay time
tpo
CL
Note: Ir, If = (ICYL - twLH - IWLTL) / 2 where If ~ 50 ns.
718
= 15 pF
30
SED1191
o
Common Drive
YSCL
~'VIL
~ ..
FR
f-
VIH
"
VIL
~ tFRCD
~tCLCD-
~
COM out
f-Vn-O.5V
"Vn +O.5V
X___
VDD ,V1
V1, V4, VSSH
~tIHCD-
INH _ _ _
VIH = 0.2 x Vss; VIL = 0.8 x Vss (Vss = -5.0 V ±10%, Ta = -20 to 75°C)
Parameter
Rating
Symbol
Conditions
YSCL-COM output delay time
tcLCD
VssH=-14.0 to -18.0V
-
RF-COM output delay time
tFRCD
CL= 100 pF
INH-COM output delay time
tlHCD
-
719
Min
Unit
Typ
Max
-
3.0
I!s
3.0
Ils
3.0
I!s
I
SED1191
•
PAD LAYOUT
65
1
80
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
0000000000000000
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
JMI .c~~~::9:ccccccccc
25
(0,0)
o 64
o
o
o
o
o
o
o 41
40
X
Die size "." .. """" 4.80 x 4.98 mm
Pad pitch """"" ...... 190 ~m (min.)
Die thickness .................... 400 ~m
•
PAD COORDINATES
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Name
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
X
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
516
762
1009
~m
Y
4826
4636
4446
4255
4065
3874
3684
3494
3303
3113
2922
2732
2542
2351
2181
1970
1780
1590
1399
1209
1018
828
570
379
155
155
155
No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Name
COM4
COM3
COM2
COMl
COMO
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
720
X
1255
1502
1748
1995
2241
2488
2734
2981
3227
3474
3720
3967
4213
4645
4645
4645
4645
4645
4645
4645
4645
4645
4645
4645
4645
4645
4645
Y
155
155
155
155
155
155
155
155
155
155
155
155
155
379
570
828
1018
1209
1399
1590
1780
1970
2161
2351
2542
2732
2922
No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
COM54
COM55
COM56
COM57
COM 58
COM 59
COM60
COM61
COM62
COM63
DO
VSSH
V4
NC
NC
NC
NC
Vl
VSS
VDD
NC
DI
LAT
INH
FR
YSCL
X
4645
4645
4645
4645
4645
4645
4645
4645
4645
4645
4254
4008
3761
3515
3268
3022
2775
2529
2282
2036
1789
1543
1296
1050
803
557
Y
3113
3303
3494
3684
3874
4065
4255
4446
4636
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
4826
CMOS 86 ROWS LCD DRIVER
•
DESCRIPTION
The SED161 0 is an 86 output dot matrix LCD common (row) driver for driving a high-capacity LCD panel at
duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1610, the LCD driving voltage VO is isolated from Voo. This provides the ability to
adjust the offset bias independently of Voo. These unique features allow the SED1610 to interface with a
variety of LCD panels.
The SED161 0 is used in conjunction with the SED1600 (80 segment driver) or the SED1601 (80 segment
driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• Selectable output shift direction
• 86-bit common (row) driver
• Wide range of LCD voltage .... -12 to -28V
± 10%
• Duty cycle............................... 1/64 to 1/300
• Supply voltage ........................ S.OV
• Display blanking available
• Package .................. QFPS-100 pins (FAA)
• Shift clock frequency .............. 2MHz max.
• Ability to adjust offset bias of the LCD source from
Voo
•
I
SYSTEM BLOCK DIAGRAM
DO - 07
XSCL
LP,FR
LCD
CONTR
-
YSCL
YO
I
SED1601
I SED1610 r
86
v
+
I SED1610 I
~
86
~
I
I
~~
SED1601
~~
160 SEG X 172 COM
DUTY: 1/128
-V
721
en
m
C
~
•
•m
c::
o(')
"oZ
r
~
-I
C
:;
C>
880
~
088888
zl~
I
r
~§~~~~5~~g~~~~~iiil~
~
I\)
COM2
COM3
COM4
COMS
COM6
COM7
COMS
COM9
COM10
COMll
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM2l
COM22
COM23
COM24
COM25
COM26
COM27
COM2S
COM29
COM30
COM3l
~o
o
.~!
0000000000000000000Z
00000000000000000000
ggggggggggg~~~ggggg
~~~wwwww~~~~~~~~~~~
row~~m~oo~o~~w~mm~oo~o
COMBO
COM79
COM7S
COM77
COM76
COM75
COM74
COM73
COM72
COM7l
COM70
COM69
COM6S
COM67
COM66
COM65
COM64
COM63
COM62
COM6l
COM60
COM59
COMS8
COMS7
COM56
COM55
COM54
COM53
COM52
COM5l
Olg
"T1
0
0
r~
;JJ
...«
~a
~
:c
»
s::
< 0<
U>
U>
0
00<
--00
gasr
~Q.~
COMO
COM1
COM2
(fJ
:::r
co;:j!
&ffil
::.<9.
~
r
CD
"'05
a>&(fJ
::+2:
""
~
r
~8
Q:~
...... <.
~
COM86
o
2
0')
.....
o
SED1610
• PIN DESCRIPTION
Pin name
COMO to
COM 85
INH
YSCL
0101,0102
SHL
Functions
Voo, Vss
VO, V1, V4, V5
Contents of
Shift Register
H
Controls all common outputs to nonselect
level (V4 when FR = L, V1 when FR = H)
(low active)
H
Shift clock of serial data (falling edge
trigger).
L
L
Fixed to "L"
FR
COMO-85
H
V5
L
H
VO
V1
L
V4
V1
H
L
V4
(Select level)
(Non select level)
(Non select level)
Serial transfer data 1/0, which is controlled
by SHL input. Output changes at falling
edge of YSCL.
Shift direction selection and 010 pin contra.
010
SHL COM output shift directio
1
L
R
FR
INH
LCD driving common (row) outputs. Each
output changes at the falling edge of YSC .
854
85
0
.0
2
Input Output
Output Input
AC signal of LCD driving outputs.
Logic circuit power. Voo: 0 V (GND)
Vss: -5.0 V
LCD driving power. V5: -12 to -28 V
Voo;:::VO>V1 >V4>V5
•
ELECTRICAL CHARACTERISTICS
•
Absolute Maximum Ratings
(Voo = 0 V)
Parameter
Symbol
Ratings
Unit
Vss
-7.0 to +0.3
V
Supply voltage (2)
V5
-30.0 to +0.3
V
Supply voltage (2)
VO,V1,V4
V5 -0.3 to +0.3
V
Input voltage (1)
VI
Vss -0.3 to +0.3
V
Output voltage (1)
Vo
Vss -0.3 to +0.3
V
Output current (1)
10
20
mA
Output current (2)
Supply voltage
(1)
10SEG
20
mA
Operating temperature
Topr
-20 to +75
Storage temperature
Tstg
-65 to +150
DC
DC
Soldering temperature, time
Tsol
260 D
C, 10 s (at lead)
Allowable power dissipation
Po
300
723
mW
I
SED1610
• DC Electrical Characteristics
(Unless otherwise specified, VOD = VO = 0 V, Vss = -5 0 V +10% , Ta = -20 to 75°C)
Pin
Min
Typ
Max
Unit
Parameter
Symbol
Condition
Operating voltage (1)
Vss
Vss
-5.5
-5.0
-4.5
V
Recommended operating voltage
Minimum operating voltage
V5
V5
-28.0
-
-12.0
V
VO
-2.5
Operating voltage (2)
VO
"H" input voltage
VIH
"L" input voltage
VIL
"H" output voltage
VOH
10H = --0.6 mA
"L" output voltage
VOL
10L= 0.6 mA
Input leakage current
Stand-by current
III
0101.0102, 0.2Vss
YSCL, FR,
SHL,INH
Vss
0101,0102
YSCL,
SHLINH FR
0101,0102
~VI~OV
ILllo
Vss ~
VI~
loos
V5= -12.0 to -28.0 V
VIH = Voo, VIL = Vss
0V
Voo
RSEG
Current dissipation (1)
ISSOl
Current dissipation (2)
Iss02
Input capacitance
CI
Ta = 25°C
ClIO
~
-
0
V
-
V
-
0.8Vss
V
-
-
V
Vss+O.4
V
2.0
~
5.0
~
25
~
1.1
1.8
1.2
2.0
2.0
4.0
Vss
-
7
15.0
/lA
V5
-
7
15.0
~
-
-
8.0
pF
15.0
pF
Min
Typ
Max
Unit
-
-
lAVoN I =0.5 V V5 -14.0V COMO to
COM85
-B.OV
Vss - -5.0 V, VIH = Voo.
VIL = Vss, fvSCL = 7.7kHz.,
Frame period = 60 Hz;
Input data: "H" every 1/128
duty No-load
Vss = -5.0 V, V1 = -2.0 V
V4 = -18.0 V, V5 = -20.0 V
All other conditions are
same as Iss01
-
-
-
-20.0V
Output resistance
--0.4
-B.O
YSCL,SHL,
INH,FR
0101,0102
kQ
• AC Characteristics
o Input Timing
Parameter
Conditions
Symbol
tCCL
500
YSCL "H" pulse width
twCLH
70
YSCL "L" pulse width
YSCL period
tWCLL
330
Data setup time
tos
100
Data hold time
tOH
10
Allowable FR delay time
tOFR
-500
Input signal rise time
tr
Input signal fall time
tf
-
724
ns
ns
ns
ns
ns
500
ns
50
ns
50
ns
SED1610
o Output Timing
(Vss = -5.0 V ±10%, Ta = -20 to 75°C)
Parameter
(YSCL-fall to 010) Delay time
Symbol
Conditions
Min
Typ
Max
Unit
tpdDOCL
CL = 15 pF
30
-
300
ns
-
-
3.0
lis
-
-
3.0
!lS
(YSCL-fall to COM output)
Delay time
tpdCCL
(INH to COM output) Delay time
tpdCINH
(FR to COM output) Delay time
tpdCFR
V5 = -12.0 to -28.0 V
CL = 100 pF
• Timing Chart
o Input Timing
VIH = 0.2Vss
VIL= 0.8Vss
J--------J----y
\
FR
1..- tWCLH'" tOFR
1---t,- ~rr=-_ ___.lI ....I-----tWCLL ------1.~1 r---~=iI~1 - t t
YSCL
1
0101
0102
..
\~.tDS" .tOH
XXXXX4
tCCL--------.~1
=i-I
~XXXXXXXXXXXXXXXX'----XZ
I
o Output Timing
X
FR
VIH = 0.2Vss
VIL = 0.8Vss
\
YSCL
f.---
tpdoOCL - - -
~ VOH =0.2Vss
VOL = 0.8Vss
0101
0102
I--- tpdCCL - INH
~
-
- - tpdCFRtpdCINH
•
~
COM
725
Vn-0.5
Vn + 0.5
SED1610
• EXAMPLE OF APPLICATION (SED1610FAA)
(for 200 x 640 DOT MATRIX LCD)
1---------------------,
LP - - - - } - - ,- - - - .__1
,
,
1
I_~~_-_ _-_-_-_-_-_-_~'---t+--i
:
,,
1
,r
I
,,
u:-
: Vss - - -___..-...____-=:...0
'
: Voo
-..----'-+--+~
o
:vo
-1~-""7f--+~
~
a:
w
::l
~z
8
200 x 640 DOT MATRIX
I
~
:: V1
,
:, V2
,
,,, V3
,,
,
: V4
LCD PANEL
---<~---+---:;:-H
---~---+-.,--hl
~f---+---,-t--+---J
: V5 -'~-+--A.A'v-I----',,--;-+-+----'
,
: VSSH
.. _----------,
WF
:
XSCL ---~--__+---------~---I____'-+_r--_r
XDOtoXD3 - - - t - - - + - - - - - - - - ( - - - - + - - - - + - - - o > - - - + _
I ______________________ J
Note: • Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01 !1F) near pins
Vss and V5 of each LSI for noise protection.
726
CMOS DOT MATRIX HIGH DUTY LCD DRIVER
• CMOS S8-bit Common Driver
• High Voltage Resistant Output
• CMOS High Voltage Resistant Process
•
DESCRIPTION
The SED1630 is a 6S output dot matrix LCD common (row) driver for driving a high-capacity LCD panel at
duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1630, the LCD driving voltage VO is isolated from Voo. This provides the ability to
adjust the offset bias independently of Voo. These unique features allow the SED161 0 to interface with a
variety of LCD panels.
The SED1630 is used in conjunction with the SED1600 (SO segment driver) or the SE01601 (SO segment
driver) or the SED1620 (12S-bit segment driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• 6S-bit common (row) driver
• Ability to adjust offset bias of the LCD source from
Voo
• Duty cycle..... .... .... ............... ... 1/64 to 1/300
• Selectable output shift direction
• Display blanking available
• Wide range of LCD voltage .... 12V to 2SV
• Shift clock frequency .............. 2MHz max
• Supply voltage ........................ S.OV ± 10%
• Low-power CMOS technology
• Package ..................... QFPS-SO pins (FOA)
•
I
SYSTEM BLOCK DIAGRAM
00-07
XSCL
LP,FR
LCD
CONTR
-
YSCL
YO
I
SE01630 Ja8
CO~
t_
J
SE01630 68
t--
SE01601
SE01601
SE01601
SE01601
~~
~~
~~
~~
320 SEG x 136 COM
DUTY: 1/136
CO~
727
=====~==~=~.--.
--_.-."-"
I
SED1630
•
I
BLOCK DIAGRAM
~::. ::.o~------------- 8~
88
Voo
~
Vss
~
-------------
VI
V4
~.
VO
V5
FR
Voltage
Control
Circuit
t
t
LCD Driver
68 bits
<
<
~
Level Shifter
68 bits
J
DIOI
YSCL
• PIN CONFIGURATION
Pin name
Functions
COMO to
COM 67
LCD drive common outputs.
YSCL
COM4O
CQM39
COM,.
SHL
COM37
VDD
COM36
vss
vo
v,
V4
v.
SEOI630
D101, DI02
COM"
COM33
CQM32
COM31
COM30
COMO
COM29
COM28
COM27
COM1
-~TiiiTiii#rr=m;:rr#im=m;:~ITiT~i=rn~iC1
Active low Blanking controlled input.
Data is shifted into the driver on the falling
edge of this signal.
Serial data input/output pins.
Configured by SHL.
COM35
0101
COM2
YSCL
COM41
INH
FR
DI02
• PIN DESCRIPTION
COM42
om
>
i
INH
COM67
r'
Shift Register
68 bits
t
SHL
INH
~
SHL
FR
Voo, Vss
YO, V1, V4, V5
728
Shift direction and input/output select input
COM output shift
DIO
SHL
direction
1 I 2
L
0
~ 67 Input IOutput
R 67
~ 0 Output I Input
LCD AC drive signal input.
Logic power inputs
LCD drive power inputs.
Voo~VO~V1 ~V4~V5
SED1630
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Characteristics
Parameter
Supply voltage (1)
Symbol
Ratings
-7.0 to 0.3
Unit
Vss
V5
-30.0 to 0.3
V
VO, V1, V4
V5 -0.3 to 0.3
V
Input pin voltage
VI
Vss -0.3 to 0.3
V
Output pin voltage
Vo
Vss -0.3 to 0.3
V
Output pin current (1)
10
20
mA
Output pin current (2)
10eoM
20
mA
Po
300
mW
Supply voltage (2)
Allowable power dissipation
V
Operating temperature
Topr
-20 to 75
°C
Storage temperature
Tstg
-65 to 150
°C
Soldering temperature, time
Tsol
260°C, 10 s
-
Notes: 1. All voltages are given relative to VDD =0 V
2. VO,V1 and V4 must satisfy the condition
Voo ~ VO ~ V1 ~ V4 ~ V5
3. Exceeding the absolute maximum ratings can cause permanent damage to the device.
Functional operation under these conditions is not implied.
4. Moisture resistance of flat package can be reduced by the soldering process.
Care should be taken to avoid thermally stressing the package during board assembly.
I
729
SED1630
• DC Electrical Characteristics
(Unless otherwise specified, Voo = VO = 0 V Vss = -S 0 V +
- 10% Ta = -20 to 7S0C)
Parameter
Condition
Pin
Min
Typ
Max
Vss
Vss
-S.S
-S.O
-4.S
V
Recommended operating voltage
VS
VS
-2.8
-
-12.0
V
Supply voltage (3)
VO
Recommended value
VO
-2.S
-
0
V
Supply voltage (4)
V1
Recommended value
V1
2/9·VS
Voo
V
Supply voltage (S)
V4
Recommended value
V4
VS
-
7/9·VS
V
High-level input voltage
VIH
Low-level input voltage
VIL
High-level output voltage
VOH
10H =-0,3 mA
Low-level output voltage
VOL
10L = 0.3 mA
Vu
Vss
•
I SED1631 jTI(>
SED1620
SED1620
SED1620
~2~
~2~
~~
384 SEG x 200 COM
DUTY: 1/200
733
SED1631
•
BLOCK DIAGRAM
0
.....
C\J
:2:2 : 2 - - - - - - - - - - - - -
888
~
:2
8
voo
Vss
V1
V4
LCD Driver
va
100 bits
vs
FR
0101
0102
YSCL 0 - - - - - - - - - - 1
SHL 0 - - - - - - - - - - - - '
INH
• PIN DESCRIPTION
Pin Name
Function
I/O
COMO to COM99 100t0112 LCD drive common outputs.
1 to 96
Active low blanking control input.
INH
98
YSCL
100
Data is shifted into the driver on the falling edge of this signal.
0101,0102
108,
97
Serial data input/output pins. Configured by SHL.
Shift direction and input/output select input.
SHL
SHL
FR
99
010
COM Data Shift Direction
101
L
0
• 99
H
99
.
LCD AC drive signal input.
Voo, Vss
102, 103
Logic power inputs.
VO,V1,V4,V5
104,105,
106,107
LCD drive power inputs.
734
0
1
2
input
output
output
input
SED1631
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VDD
Parameter
Ratings
= 0 V)
Unit
Supply voltage (1)
Symbol
Vss
-7.0 to 0.3
V
Supply voltage (2)
V5
-30.0 to 0.3
V
Supply voltage (3)
V
VO, V1, V4
V5 -0.3 to 0.3
Input voltage
VI
Vss -0.3 to 0.3
V
Output voltage
Vo
Vss -0.3 to 0.3
V
Output current (1)
10
20
mA
Output current (2)
10COM
20
mA
mW
PD
300
Operating temperature
Power dissipation
Topr
-20 to 75
°C
Storage temperature
Tstg
-65 to 150
°C
Notes: 1. All voltages are given relative to VDD =0 V
2. VO,V1 and V4 must satisfy the condition VDD ~ VO ~ V1 ~ V4 ~ V5
3. Exceeding the absolute maximum ratings can cause permanent damage to the device.
Functional operation under these conditions is not implied.
4. Moisture resistance of flat package can be reduced by the soldering process.
Care should be taken to avoid thermally stressing the package during board assembly.
I
735
SED1631
• DC Electrical Characteristics
(Unless otherwise stated, VDD = VO
Parameter
=OV, Vss = -S.OV +- 10%, Ta =-20 to 7S°C)
Pin
Min
Typ
Max
Unit
Operating voltage (1)
Vss
Vss
-S.S
-S.O
-4.S
V
Recommended operating voltage
Minimum operating voltage
VS
VS
-2B.0
-12.0
V
-8.0
V
Operating voltage (2)
VO
Recommended value
VO
-2.S
-
0
V
Operating voltage (3)
Vi
Recommended value
Vi
2/9·VS
-
VDO
V
Operating voltage (4)
V4
Recommended value
V4
VS
-
7/9·VS
V
High level input voltage
VIH
0101,0102,
YSCL,.£f!,
SHL,INH
-
-
Symbol
Low level input voltage
VIL
High level output voltage
VOH
Low level output voltage
10H =-0.3 mA
0101.0102
VOL
10L = 0.3 mA
Vu
Vss -<;,VI-<;' OV
VU/O
VSS-<;,VI-<;'OV
loos
VS = -12.0 to -2B.0 V
VIH = Voo, VIL = Vss
Input leakage current
Stand-by current
Output resistance
Condition
RCOM
Current dissipation (1)
Iss1
Current dissipation (2)
Iss2
Input capacitance
CI
CliO
-0.4
YSCL. SHL,
INH.FR
0101.0102
-
Voo
-
VS=-20.0V V1. V4
Output level
VS 14.0V
COMO to
VS=-O.BV
COM99
I~VoNI = 0.5V
VS=-20.0V va, V5
Output level
VS 14.0V
COMO to
VS=-B.OV
COM99
Vss =-5.0 V, VIH =VDD,
V = Vss, fvSCL = 12 kHz,
Vss
Frame frequency = 60 Hz;
Input data inverted
bit by bit, No-load
Vss = -5,0 V, V1 =-2,0 V
V4 =-18.0 V, V5 = -20,0 V
VS
All other conditions are
same as 1551
YSCL, SHL.
INH,FR
Ta = 2SoC
0101,0102
• AC Electrical Characteristics
o Input Timing
Parameter
-
-
-
V
V
V
2.0
~A
S.O
~A
2S
~A
0.40
O.SO
(0.60)
0.60
0.70
(0.90)
O.BO
1.00
(1.20)
1.20
1.40
(1.20)
kg
-
7
1S.0
~A
-
7
1S.0
~A
-
-
B.O
pF
-
-
1S.0
pF
-
-
(VSS = -S.O V ± 10%, Ta = -20 to 7S°C)
Symbol
Conditions
Min
Typ
YSCL High-level pulse width
tWCLH
70
YSCL Low-level pulse width
tWCLL
330
tos
100
-
Data setup time
O.BVss
V
Vss+O.4
-
YSCL period
-
tCCL
SOO
Max
Unit
-
ns
-
ns
ns
ns
Data hold time
tOH
10
-
-
ns
Allowable FR delay time
tOFR
-SOO
-
SOO
ns
-
SO
ns
SO
ns
Input signal rise time
tr
-
Input signal fall time
tl
736
SED1631
• AC Electrical Characteristics
o Output Timing
(Vss = -5.0 V ±100/0, Ta = -20 to 75°C)
Parameter
(YSCL-fall to 010) Delay time
•
o
Symbol
Conditions
Min
Typ
Max
Unit
tpdDOCL
CL = 15 pF
30
-
300
ns
-
-
3.0
~s
3.0
~s
3.0
~s
(YSCL-fall to COM output) Delay time
tpdCCL
(INH to COM output) Delay time
tpdCINH
(FR to COM output) Delay time
tpdCFR
V5 = -12.0 to -28.0 V
CL= 100pF
-
-
Timing Chart
Input Timing
VIH = 0.2Vss
VIL = 0.8Vss
3'-----------1----1---Y
FR
t
. -tWCLH - - - tDFR
t,-rr=I.. _ _-J 1....1 - - - - - - tWCLL
1
0101
0102
o
- - - - - 1... 1
r - - - = :......
!"J,I
--- tf
1\
YSCL
!eCL
..
\~.tDS" .tDH:~_/
XXXXX4
jxxxxxxxxxxxxXXXX'---_M
I
Output Timing
~(
FR
VIH = 0.2Vss
VIL = 0.8Vss
\
YSCL
-tpdDOCL _
K
VOH =0.2Vss
VOL = 0.8Vss
0101
0102
-tpdCCL-
INH
~
- - tpdCFR -----.. - - - tpdCINH
•
X
COM
737
Vn -0.5
Vn + 0.5
SED1631
• EXAMPLE OF APPLICATION
(for 200 x 640 DOT MATRIX LCD)
--------1
LP
YO
,----------
,----
I
I
I
f---
0102
Vss
I
~
: Vss
ow
I
I
I
cr:
: V1
~
w
-'
-'
acr:
f-
z
a
()
VO
: V4
Rr*
Rr*
11Rr*
Rr*
I
I
I
Rr*-
I
I
I
: V2
I
I
I
I
V3
I
V5
I
I
7
: VssH
I
:
1- ____________ _
t--.
:2
0"
200 x 640 DOT MATRIX
'
~
SHL ®
-. g:g~
FR
~
LCD PANEL
§
SE5163W
VDD
6
1
0
g
220
EiW
6
220
--------1
WF
XSC L
XDO toXD3
b
FR~
p---. YSCL
+
: VDD
f-+-,/
~
I
I
0
~
0101
I
LL
YSCLQ)
SHL
79 -fl-o
7911--0
E102Q)E101
-'~
SHL
EI02®EI01_r -------
EI02®EI0}
,,2
U)oc...tl:
XO...JLL
-J (')
C')
Ll
SHL
(1)00..0::
XO...JIJ..
-------
11
4
..J
,,2
XO...JLL.
(f)
I
SHL
,,2
ClJoa...cr:
*1
I
I
---------I
79-fls~~
~~~~~=~~
I
-------
Note: * Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01 J.lF) near pins
Vss and V5 of each LSI for noise protection.
738
SED1631
• PAD LAYOUT (SED1631 DOA)
No.
2
3
4
5
6
30
40
~
E
~
~
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20
10
1
000000000000000000000000000000000000
0
0
B 110
0
0
0
0
0
0
0
0
Y
Lx
(0,0)
o 100
000000000000000000000000000000000000
60
70
80
90
I-
0
0
0
0
0
0
0
.1
2011
148.81lm Pitch
8
9
10
111
: 12
13
14
115
! 16
117
18
119
120
12'
X
Pad
Name I(~m)
COM5 12604
CO~6 L24!)5
COM, 12306
COM8 12158
OM9 12009
COM10 11860
OMI
COM12 11562
COMI 11414
COM14 1265
COM15 116
COM'" 967
COMI
818
ICOM18 670
COM19 521
I COM20 372
ICOM21 223
I COM22 74
COM23 1-74
I COM24 1-223
122 I COM,26 I"sE'
123 COM27 1-670
24 COM28 1--a18
1 25 I COM29 1--1J§7
126 COM3O f-j116
COM: 1-1265
128 COM32 1-1414
129
130 COM34 -171'
131
Chip size
Chip thickness
Pad Size
6,03mm x 4,01 mm
0.400mm ±0,025mm
108mm x 110mm
(X)
(Y)
132
133 I COM37 -2158
134
135
136
137 I COM41 -2847
138
739
Y
'ad
X
(~m) INo. I Name , (~m)
1839 139
1839 ,~
Y
X
Y
(~m)
(~m)
(~)
372
521
670
818
967
16
.1265
1414
,1562
1-1839
'ad
INo. Name
1260 77 COM81
1092 78 COM82
924 79 COM83
756 1 80 COM84
588 181 COM85
420 182 COM86
252 183 COM87
84 184 COM88
-64 185 COM89
-252 186 COM90
-420 187 COM91
-588 BB COM92
-756 89 COM93
_4 90 COM94
-1092 91 COM95
-1260 92 COM96
-1428 93 COM97
1839 141
1839 42
1839 43 ICOM47 1-2847
1839 44
1839 45
OM49 1-284,
1839 46
1839 47 ICOM51 1-284,
1839 48
OM52 1-284,
1839 49 ICOM53 1-2847
1839 50 ICOM54 1-284,
1839 51 ICOM55 1-2847
1839 52 ICOM56 1-2847
1839 53 ICOM57 1-2847
1839 54 OM58 1-2847
1839 55 ICOM59 1-2847
1839 56 ICOt,,160 1c2B47 ~1596 94
1839 57 ICOM61 1-2604 -1834 95
1839 58 ICOM62 1-2455 -1834 96
OM6: 1-2306 -1834 97
1839 59
1839 60
OM64 1-2158 -1834 98
1839 61
OM65 1-2009 -1839 99
1839 62
OM66 1-1860 -1839 100
OM6,
-1839 101
1839 63
1839 64 COM68 1-1562 -1839 102
OM69
1839 65
1839 66
OM70 1-1265 -1839 104
1839 67 ICOJvl71
16 -1839 105
COM72
1839 68
1--1l67 -1839 100
1839 69 COM73 1--a18 -1839 107
1839 70 ICOM74 1--a70 -1839 108
1839 71 COM75 1~21 -1839 109
1839 72 COM76 1...,'372 -1839 l1C
1839 73 COM77 1-223 -1839 111
1839 74 OM78 -74 -1839
1596 75 COM79 74 -1839
1428 76 COMBO 223 -1839
l::11
m
CQM98
COM99
0102
INH
FR
l::'83~
1-1839
1-1839
1-1839
1-1839
1-1839
1-1839
1-1839
1-1839
11860 1-1839
'2009 1-1839
12158 1-1839
12306 1-1839
12455 1-1839
12604 1-1839
12847 1-1596
12_84, I ~1428
1284, 1-1260
1284, 1-1092
1284,
-924
1284, _-7~
12847 ..,ss8
YSCL
SHL 1284,
Vo
1284:.
vss 1284,
va 12847
VI
1264,
V4 12847
V5
1284,
0101 1284,
COMO 12847
QMl 1,~847
COM2 12847
COM3 12847
OM4 1284,
-420
-252
--a4
84
252
420
588
756
924
092
1260
1428
1596
I
SED1631
•
PADLAYOUT(SED1631DoB)
Pad
No.
2
3
4
5
6
D
D
D
10
1
30
20
000000000000000000000000000000000000
;g
a.
~
~
50
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
D
D
B 110
40 D
D
D
CD
~ D
!!l
D
~ D
Y
L
(0,0)
X
g§
D
D
D
D
D
D
D
100
ODODODOQOODDDDOOODODDDOOOODDODOODOOO
60
I.
70
80
148.8~m Pitch
90
.12011
6
9
, 10
X
Y
Name I bun)
(~) No.
COM5 1~04 ~834. ~9
COM6 12455 1834 40
OM; 12306 '1834 41
OM8 12158 1834 42
COM9 12009 1834 43
I GOM' 11_ 1834 44
COM1
1834 45
ICOM12 1'582 1834 48
ICOM13 11414 1834 47
ICOM14 11265 1834 48
ICOM1
, 12 ICOM11
113 ICOMl'
, 14 ICOM1I
15
OM'
.16
OM20
~
ICOM21
116
967
818
1834
1834
1834
670
521
372
1834
1834
1834
1834
1834
223
74
-74
120
121
122
123
124
25
126 COM30 -1'
127
128 COM32 -141,
129
30
Chip size
Chip thickness
Bump size
Bump height
6,03mm X 4,01 mm
0,S2Smm ±0,02Smm
11711m x 10SI1m ±2Ol1m
20mm + 10/Sl1m
131
132
33
134
135
136
137
138
740
1834
1834
1834
1834
1834
1834
1834
1834
1834
'M
~
I Name ! !!Un)
OM48 -2842
ICOM50 1-2842
ICOM51 1-2842
ICOM52 1-2842
49 ICOM53 1-2842
50 ICOM54 1-2842
51 ICOM55 1-2842
52 ICOM56 1-2842
OM5, 1-2842
53
54
55
OM58 1-2842
:OM59 1-2842
I'I!d
It
"L
OMBO 1-2842
56
57
OM6' 1-2604
58 ICOM82 1-2455
59 :OM63 1-2306
-1596 194 COM98 12842 1-1428
-1834 195
OM99 12842 1-1260
-1834 196 0102 12842 1-1092
-1834 19,
INH
2842 -924
OM64 1-2158 -1834 198
FR
2842 -756
-1834
YSCl
2842 -688
ICOM65 1-2009
199
2842 -420
COM86
1100 SHl
COMB7 1-1711 -1834 101
voo
2842 -252
60
61
82
63
64 ICOM68
65 COMB9
1834. 68
1834 67 COM71 1-1116
1834 ,68
OM72 1-96,
1834 69 COM73 1-!l18
1834 170 COM74 -!l70
1834 71 COM75 -621
1834
1834
1834
1596
1428
'!
(JIm)
(~m) No. , Name I(~)
1260
COM81 372 1-1834
1092 ,78 COM82 521 j-l834
COM83 670 1-1834
924
756 180 COM84 818 1-1834
588 81 'COM85 967 1-1834
420 j82 COM86 11116 1-1834
252 ,83 COM87 11265 1-1834
84 !84. ICO'-188 11414 1-1834
-84 i 65 COM89 11582 1-1834
-252 186 COM90 1711 1-1834
-420 187 ICOM91 11860 1-1834
-688 ! 88 ICOM92 12009 1-1834
-756 189 COM93 12158 1-1834
-924 190 COM94 12306 1-1834
-1092 19' COM95 12455 1-1834
-1260 192
OM96 12604 1-1834
-1428 193 COM97 12842 1-1596
1'02
103
-1834
'-1834
,-1834
1-1834
104
105
106
10i
1-1834 108
1-1834
72
OM76 -372 1-1834
173 COM?: -223 1-1834
174 COM78 -74 1-1834 111:
175 COM79 74 1-1834
176 COM80 223 1-1834
Vss
0191
COMO
COMl
2842.
2842
2842
2842
2842
2842
2842
2842
-!l4
84
252
420
568
756
924
1092
OM2
COM3
COM4
2842
2842
2842.
1260
1428
15!!6
VO
VJ.
V4
V5
CMOS DOT MATRIX HIGH DUTY LCD DRIVER
•
•
•
•
•
CMOS 86-bit Common Driver
High Voltage Resistant Output
Max 1/300 in Display Duty
CMOS High Voltage Resistant Process
DESCRIPTION
The SED1632 is an 86 output dot matrix LCD common (row) driver for driving a high-capacity LCD panel at
duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1632, the LCD driving power is isolated from Voo. This provides the ability to adjust
the offset bias independently of Voo. These unique features allow the SED1632 to interface with a variety of
LCD panels.
The SED1632 is used in conjunction with the SED1600 (80 segment driver), the SED1601 (80 segment
driver) and the SED1620 (128 segment driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• Selectable output shift direction
• 86-bit common (row) driver
• Wide range of LCD voltage .... -12 to -28V
• Duty cycle ............................... 1/64 to 1/300
• Supply voltage ........................ 5.0V ± 10%
• Display blanking available
• Package ......................... DIE: AI pad (DOA)
• Shift clock frequency .............. 2MHz max
• Ability to adjust offset bias of the LCD source from
Voo
•
I
SYSTEM BLOCK DIAGRAM
DO - D3
XSCL
LP,FR
LCD
CONTR
-
YSCL
YD
I
SED1600
SED1632
t 86
I
I
~~
)
v
•~
SED1600
~~
128 SEG x 128 COM
DUTY: 1/128
SED1632
741
,.-~-
....
,~~~,
SED1632
•
BLOCK DIAGRAM
~
888------------- 8
0
.....
C\I
>--->----
Voo
Vss
Vl
V4
-------------
R I-
VO
V5
LCD Driver
B6-bit
Vottage
Control
t
FR
I
<--r
level Shifter
86-bit
~ ~
0101
YSCl
Shift ReQister
86-blt
-'
t
SHl
i
INH
r'~
0102
• PIN DESCRIPTION
Pin Name
COMO to COM85
-INH
YSCL
0101,0102
Function
LCD driving common (row) outputs_
Each output changes at the falling edge of YSCL.
Controls all common outputs to nonselect level (V4 when FR = L, V1 when
FR = H) (lOW active). Contents of shift register are cleared.
Shift clock of serial data (falling edge trigger).
Serial transfer data I/O, which is controlled by SHL input. Output changes
at falling edge of YSCL.
Shift direction selection and 010 pin control.
SHL
FR
010
COM Data Shift Direction
SHL
1
L
85
H
85
~
•
Input
Output
0
Output
Input
AC Signal of LCD driving outputs.
Voo, Vss
Logic circuit power.
VO,V1,V4,V5
LCD driving power.
VOD: OV (GND)
Vss: -5.0 V
V5: -12 to -28V
VDD;;:: VO ;;:: V1 > V4;;:: V5
742
2
0
SED1632
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voo
Parameter
= 0 V)
Ratings
Unit
Supply voltage (1)
Symbol
Vss
-7.0 to +0.3
V
Supply voltage (2)
V5
-30.0 to +0.3
V
Supply voltage (2)
VO, V1, V4
V5 -0.3 to +0.3
V
Input voltage (1)
VI
Vss -0.3 to +0.3
V
Output voltage (1)
Vo
Vss --0.3 to +0.3
V
Output current (1)
10
20
mA
Output current (2)
10SEG
20
mA
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-65 to +150
°C
Soldering temperature, time
Tsol
260°C, 10s (at lead)
Allowable power dissipation
Po
300
mW
Notes: 1. VO, V1 and V4 must always satisfy the condition Voo ~ VO ~ V1 ~ V4 ~ V5.
2. If the power supply for the logic circuit is floated while the liquid crystal driving power supply is applied,
the LSI can be irreparably damaged. Be especially careful when the system power is being turned on
or off.
I
743
SED1632
• DC Electrical Characteristics
(Unless otherwise specified, Voo = VO
Parameter
Operating voltage (1)
Recommended operating voltage
Minimum operating voltage
Symbol
Condition
VS$
VS
=0 V, Vss = -S.O V +10%,
Ta = -20 to 7S0C)
Pin
Min
Typ
Vss
-S.S
VS
Max
Unit
-S.O
-4.S
V
-2B.0
-
-12.0
-
Operating voltage (2)
VO
Recommended value
VO
-2.S
Operating voltage (4)
Vi
Recommended value
Vi
2/9·VS
Recommended value
V4
VS
Operating voltage (S)
V4
"H" input voltage
VIH
"L" input voltage
VIL
"H" output voltage
VOH
10H =-0.3 mA
"L" level output voltage
VOL
10L = 0.3 mA
III
Vss :5,VI:5, 0 V
YSCL, SHL,
INH,FR
IU/o
VSS:5, VI:5,O V
Stand-by current
loos
VS = -12.0 to -2B.0 V
VIH = Voo, VIL = vss
Output resistance
RSEG
VS=-20.0V Vi,
lAVoN I VS=-14.0V V4 COMO to
=0.5 v VS=-20.0V VO, COMBS
VS=-14.0V VS
Input leakage current
0101.0102. 0.2Vss
YSCL, FR,
SHL, INH
Current dissipation (1)
Iss01
Current dissipation (2)
Iss02
Vss = -5.0 V, V1 = -2.0 V
V4=-18.0V, V5 =-20.0 V
All other conditions are
same as Iss01
Input capacitance
CI
Ta = 2SoC
CliO
0
V
Voo
V
7/9·VS
-
-
O.BVss
V
-
V
Vss+O.4
V
-
2.0
jlA
0101,0102
-
S.O
jlA
Voo
-
-
2S
jlA
-
0.40
-0.4
-
0.60
0.70
O.SO
O.BO
1.00
1.20
kQ
1.40
Vss
-
7
1S.0
jlA
VS
-
7
1S.0
jlA
YSCL, SHL,
INH,FR
-
-
B.O
pF
0101,0102
-
-
1S.0
pF
(Vss = -S.O V ±10%, Ta = -20 to 7S0C)
Conditions
Symbol
Min
Typ
Max
tcCL
SOO
-
YSCL "H" pulse width
tWCLH
70
-
YSCL "L" pulse width
tWCLL
330
Data setup time
tos
100
-
Data hold time
tOH
10
-
-
Allowable FR delay time
tOFR
-SOD
YSCL period
V
V
-
• AC Characteristics
o Input Timing
Parameter
V
-
0101,0102
Vss = -5.0 V, VIH = VDD,
VIL = Vss, fYSCL = 12 kHz,
Frame period = 60 Hz;
Input data: "H" every
1/200 duty No-load
-B.O
Unit
ns
ns
ns
ns
ns
-
SOO
ns
Input signal rise time
tr
-
-
SO
ns
Input signal fall time
If
-
-
SO
ns
744
SED1632
o Output Timing
(Vss = -5.0 V ±1 0%, T a = -20 to 75°C)
Parameter
(YSCL-fall to 010) Delay time
•
o
Symbol
Conditions
Min
Max
Unit
tpdDOCL
CL= 15 pF
30
-
300
ns
-
-
3.0
I1s
-
-
3.0
I1s
(YSCL-fall to COM output) Delay time
tpdCCL
(INH to COM output) Delay time
tpdCINH
(FR to COM output) Delay time
tpdCFR
V5 = -12.0 to -28.0 V
CL = 100 pF
Typ
Timing Chart
Input Timing
VIH = 0.2Vss
VIL = 0.8Vss
FR
t
--tWCLH t,- !.-
-tDFR
..
3'----------1----
1 - - - -
tWCLL -----j.~1 r----.~·I - - tf
~
YSCL
I
0101
0102
o
..
tCCL
\~.tDS" .tDH~1
XXXXX4
~XXXXXXXXXXXXXXXX'----XZ
I
Output Timing
~
FR
VIH = 0.2Vss
VIL = 0.8Vss
\
YSCL
-
tpdDOCL - - -
~
0101
DI02
-
INH
tpdCCL ---.
~
- - - - tpdCFR
- - - tpdCINH
-•
}
COM
outputs
745
VOH = 0.2Vs s
VOL = 0.8Vss
Vn -0.5
Vn +0.5
SED1632
• EXAMPLE OF APPLICATION
(for 200 x 640 DOT MATRIX LCD)
I-----------------~----I
,
LP
------~--------~~.I
YD
1-----------,
,
I
Vss
: Vss --------~~""-=~
200
,
,,: Voo --.-----++--J
x 640
DOT MATRIX
LCD PANEL
,,, VO
,,, V1
,,: V2
,,,
,,
,,, V3
,,: V4
,,, V5
,,
,
,,
,,
,,
,
,: VSSH
L
,
,
SED1632
220
___________ ,
WF---------r-------r------------~----~_+--~--+_--~--~--~
XSCL ------~------~------------------~_+------+_~~------_r
,
XDOtOXD3---,'------~--------------~------~----_+----~----~:: ______________________
J
Note: * Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01 IlF) near pins
Vss and V5 of each LSI for noise protection .
• PAD LAYOUT
Pad
81
.............................
51
Y
Lx
(0.0)
100
••••••••••••••••••••••••••••••
30
1
Chip size
6.03mm x 4.01 mm
Chip thickness
0.400mm ±0.025mm
Pad surface area
1OOmm x 100mm
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
746
Name
X
(~m)
COM2 -2852
COM3 2612
COM4 2382
COM5 2162
COM6 1942
COM7 1742
COM8 1542
COM9 1342
COM10 1142
COM11 962
COM12 -782
COM13 -602
COM14 -422
COM15 -252
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
82
82
252
422
602
782
962
1142
1342
1542
1742
1942
2162
2382
2612
2852
2852
2852
2852
2852
Y
Pad
X
(~m) No. Name
(Mm)
-1844 35 COM36 2852
-1844 36 COM37 2852
1844 37 COM38 2852
1844 38 COM39 2852
-1844 39 COM40 2852
1844 40 COM41 2852
1844 41 COM42 2852
-1844 42 COM43 2852
-1844 43 COM44 2852
1844 44 COM45 2852
1844 45 COM46 2852
-1844 46 COM47 2852
-1844 47 COM48 2852
-1844 48 COM49 2852
-1844 49 COM50 2852
-1844 50
NC
2852
-1844 51 COM51 2852
1844 52 COM52 2612
-1844 53 COM53 2382
-1844 54 COM54 2162
1844 55 COM55 1942
1844 56 COM56 1742
-1844 57 COM57 1542
-1844 58 COM58 1342
1844 59 COM59 1142
-1844 60 COM60 962
-1844 61 COM61 782
-1844 62 COM62 602
-1844 63 COM63 422
-1844 64 COM64 252
-1664 65 COM65 84
-1484 66 COM66 -a4
-1304 67 COM67 254
-1124 68 COM68 -423
Y
Pad
No. Name
69 COM69
70 COM70
71 COM71
72 COM72
73 COM73
-a6 74 COM74
86
75 COM75
255
76 COM76
425 77 COM77
594 78 COM78
764 79 COM79
944 80 COM80
1124 81 COM81
1304 82 COM82
1484 83 COM83
1664 84 COM84
1844 85 COM85
1844 86 DI02
1844 87
INH
1844 88
FR
1844 89 YSCL
1844 90
SHL
1844 91
Voo
Vss
1844 92
1844 93
Vo
1844 94
V1
1844 95
V4
1844 96
V5
1844 97 DI01
1844 98 COMO
1844 99 COM1
1844 100
NC
1844
1844
X
Y
(~m)
(~m)
(~m)
-944
-764
594
-425
-255
-593
-762
932
1112
-1292
1472
1652
-1832
-2012
2212
2412
-2632
-2852
-2852
-2852
-2852
-2852
2852
1844
1844
1844
1844
1844
1844
1844
-2852
-2852
2852
2852
2852
2852
2852
-2852
2852
-2852
-2852
-2852
-2852
2852
1844
1844
1844
1844
1844
1844
1666
1489
1313
1137
961
794
628
462
295
129
-38
-425
-594
-764
-944
-1124
-1304
-1484
-1664
LOW-POWER 100-BIT LCD COMMON DRIVER
•
DESCRIPTION
The SED1633 is a 1OO-output dot matrix LCD common (row) driver for driving high-capacity LCD panels at
duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of LCD driving voltages, and has its
maximum drive voltage, VO, isolated from Voo for flexibility of bias voltage generation.
The SED1633 is used in conjunction with the SED1648 (80-output segment driver) or the SED1600 (80-bit
segment driver) to drive a large-capacity dot matrix LCD panel).
•
FEATURES
• Low-power CMOS technology
• Non-biased display off function
• 100-bit (50 x 2 structure) common (row) driver
• Pin selection of the output shift direction
• Duty cycle ..................................... 1/64 to 1/300
• LCD voltage ...................................... -8 to -28V
• Low output impedance 50 on typ (V1, V4 level)
700n typ (VO, V5 level)
• Supply voltage .................................. 2.7 to 5.5V
• Package ......................................... AI pad (D1A)
Au bump (D18)
• Duty cycle ................................... 1/100 to 1/300
• Ability to adjust offset bias of the LCD relative to
Voo
•
SYSTEM BLOCK DIAGRAM
I
DO- D3
XSCL
LCD
CONTR
LP,FR
YSCL
t---
YD
II
--
SED1648
I SED1633 !
•
I SED1633i
100
100
~
-V
i
'i
~~
SED1648
~~
160 X 200 dots
DUTY: 1/200
~
-V
747
SED1633
•
I
BLOCK DIAGRAM
r
O .....
C\I
0>
aaa
a
:2: :2: :2:
0>
000 ---------------------- ~
r,
VD
Vs
~~ -..--
V1
~
~
--- - ------ ----- ---- ---
fc
V4
VO Q--V5
c>-----
Voltage
Control
Circuit
1
FR
LCD Driver
100 bit
r
<~
Level Shifter
100 bit
011
YSCL
SEL
013
(
?
....
<~
Shift Register
50 x 2 bits
• i
748
.)
DO
SED1633
•
•
BLOCK DESCRIPTION
Shift Register
This is a bidirectional shift register for common data transmission.
•
Shift Direction
COM 0
--7
COM 99
•
COM 99
--7
COM 0
Level Shifter
This is a level interface circuit for shifting the signal voltage from the logic system level to the LCD driver
system level.
•
LCD Drivers and Voltage Controller Circuit
Outputs the LCD driver voltage.
The relationships between the content of the shift register, the alternating signal FR, and the common output
voltage are as shown in the table below:
Contents of
Shift Register
FR
H
L
•
COM Output Voltage
H
V5
L
VO
H
V1
L
V4
Select level
I
Non-select level
PIN DESCRIPTION
Pin Name
I/O
COMOCOM99
0
011,013
I
YSCL
FR
Voo, Vss
No. of
Pins
Function
LCD driver common (row) output
100
Changes on the falling edge of the YSCL signal.
Serial data input for the 100 bit shift register. 013 is the intermediate shift
input. (When 013 is unused, tie it to Voo or Vss.)
2
I
Serial data shift clock input. Scanning data is shifted at the falling edge.
1
I
LCD driver output AC signal input
1
Power
Power source for logic. Voo: OV (GND). Vss: -5.0V
2
YO, V1,
V4, V5
Power
Power source for LCD driver. V5: -12 to -28 V
Voo 2 VO 2 V1 > V4 2 V5
4
SEL
I
Shift Register Operating Configuration Selection:
SEL
H
L
DO
0
Shift Register Configuration
50x 2
100 xl
Shift register data output.
1
013
Input
HfL
1
The output changes with the falling edge of the YSCL signal.
Total: 112
749
SED1633
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Unit
Power voltage (1)
Vss
-7.0 to +0.3
V
Power voltage (2)
V5
-30.0 to +0.3
V
Power voltage (3)
VO, V1, V4
V5 - 0.3 to + 0.3
V
V
Parameter
Input voltage
VI
Vss - 0.3 to + 0.3
Output voltage
VO
Vss - 0.3 to + 0.3
V
Output current (1)
10
20
mA
Output current (2)
10COM
20
mA
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-65 to +150
°C
Notes: *1. The voltages are all relative to Voo = OV.
*2.
Ensure that the relationship between
va, V1, and V4 is always as follows:
Voo
~
va ~ V1 ~ V4 ~ V5.
*3. The LSI may be permanently damaged if the logic system power is floating or Vss is less than or equal to -2.6V when
power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning
the power on and off.
750
SED1633
•
Unless otherwise specified, VDD =VO =OV,
Vss = -5.0V ± 10%, Ta = -40 to 85°C
DC Electrical Characteristics
Applicable Pins
Min
Typ
Max
Unit
Power voltage (1)
Parameter
Symbol
Vss
Conditions
Vss
-5.5
-5.0
-2.7
V
Recommended operating
voltage
V5
V5
-2B.0
-
-12.0
V
Possible operating
voltage
V5
Function
V5
-
-
-B.O
V
Power voltage (2)
VO
Recommended value
VO
-2.5
V
V1
V4
Recommended value
V1
V4
2/9 x V5
V5
-
0
Power voltage (3)
Power voltage (4)
Voo
7/9 x V5
V
High-level input voltage
VIH
Vss = -2.7 to -5.5V
VIL
011, YSCL,
SEL, 013, FR
0.2 x Vss
Low-level input voltage
-
-
High-level output voltage
VOH
00
-0.4
-
10H =-0.3mA
1-:-:------
-
V
O.B x Vss
V
-
V
10H =-Q.2mA
(Vss = -2.7 to -4.5V)
Low-level output voltage
VOL
10L= 0.3mA
f-------
-
-
Vss + 0.4
V
-
-
2.0
f!A
-
5.0
f!A
25
I-lA
O.BO
KQ
IOL=0.2mA
(V5S = -2.7 to -4.5V)
III
Vss::; VIN::; OV
YSCL, SEL,
013, FR
I/O leakage current
ILO
Vss::; VIN::; OV
011,00
-
Static current
1005
V5 = -12.0 to -2B.OV
VIH = Voo, VIL = Vss
Voo
-
Input leakage current
Output resistance
RCOM
AIVONI
=0.5V
V5 =-20.0V
V5 = -14.0V
*(V5 = -B.OV)
V5 =-20.0V
V5=-14.0V
*(V5 = -B.OV)
Average operating
current consumption (1)
1551
VSS = -5.0V, VIH = Voo,
VIL = Vss, fvscL = 12KHz,
Frame frequency =
60KHz, Input data: 1/200,
"H" is without load on
each duty cycle
-
When
output·
tingthe
COMO
V1. V4
levels
COM99
When
output-
-
*Refer·
ling the
VO. V5
levels
V55
1-:-:------
Input terminal capacitance
I/O terminal capacitance
1552
CI
V55 = -5.0V, V1 = -2.0V,
V4=-1B.OV,
V5 = -20.0V; other
parameters are the
same as for 1551
Ta = 25°C
CliO
751
-
f---
-
Vss = -3.0V; other
parameters are identical
Average operating
current consumption (2)
-
ence
value
0.40
0.50
(0.60)
1.00
(1.20)
0.60
0.70
(0.90)
(1.BO)
7
15
1.20
1.40
I-lA
-5- -To-
V5
-
7
15
I-lA
YSCL, SEL,
013, FR
-
-
B
pF
011,00
-
-
15
pF
I
SED1633
•
o
AC Characteristics
Input Timing Characteristics
VIH = O.2Vss
Vil =O.8Vss
FR
-tWClH ....-
....
1
tr-
-tOFR
3'-----------1-----1----
I~..o--------twcll ------1_.1
r----+-9"1 - t f
1\
YSCL
1
011
013
..
tCCl
\~.. los. .. tOH:.~)
~XXXXXXXXXXXXXXXX~_M
XXXXX4
Vss = -5.0 ± 10%, Ta = -40 to 85°C
Input signal rise time
Parameter
Symbol
tr
Conditions
Min
-
Input signal fall time
If
-
Max
Unit
50
ns
50
ns
ICCl
500
-
ns
YSCL high-level pulse width
tWClH
70
-
ns
YSCL low-level pulse width
!wCll
330
-
ns
Data setup time
tos
100
ns
Data hold time
tOH
10
-
Allowable FR delay
tOFR
-500
YSCL frequency
500
ns
ns
Vss = -2.7 to -4.5V, Ta = -40 to 85°C
Parameter
Symbol
Input signal rise time
Ir
Input signal fall time
If
Conditions
Min
-
Max
Unit
50
ns
50
ns
tCCl
1000
-
ns
YSCL high-level pulse width
tWClH
160
ns
YSCL low-level pulse width
tWCll
330
-
Data setup time
tos
200
-
ns
Data hold time
tOH
10
-
ns
Allowable FR delay
tDFR
-500
500
ns
YSCL frequency
752
ns
SED1633
o
Output Timing Characteristics
FR
----------~~~----~~~--
VIH = 0.2Vss
Vll = 0.8Vss
\
YSCL
-tpdDOCL_
DO
III
-----------+-+-----4~
VOH - 0. 2Vss
VOL = 0.8Vss
--tpdCCL--
- - tpdCFR--
COM
V Vn-0.5
outputs _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~/! Vn + 0.5
Vss = -5.0V ± 10%, T a = -40 to 85°C
Parameter
Symbol
Conditions
Min
Max
30
300
ns
Unit
(YSCL fall
--7
DO) delay time
tpdOOCL
CL= 15pF
(YSCL fall
--7
COM output) delay time
tpdCCL
V5 = -12.0 to -28.0V
-
3.0
Ils
tpdCFR
CL = 100pF
-
3.0
115
(FR
--7
COM output) delay time
Vss = -2.7 to -4.5V, Ta = -40 to 85°C
Parameter
Symbol
Conditions
Min
Max
(YSCL fall
--7
DO) delay time
tpdDOCL
CL= 15pF
60
600
ns
(YSCL fall
--7
COM Dutput) delay time
tpdCCl
V5 = -12.0 to -28.0V
-
3.0
tpdCFR
CL= 100pF
-
3.0
Ils
Ils
(FR
--7
COM output) delay time
753
Unit
I
SED1633
•
Timing Diagram
1 frame
DI1
•
I_
1 frame
(2001;~}~~~):-
SEL= "L"
For a 1/200 duty cycle
'-------------~
------J1f
YSCL
FR
IC
Internal
shift
00
register
02 _ _+------'
~--
01 - - 4 - "
100 lines
DO
•
•
LCD DRIVING POWER
Method of Forming Each Voltage Level
The simplest way to obtain the voltage levels for driving the LCs is to use resistive voltage dividers, as shown
in the example connection figure. Because a high quality display requires precise and stable voltage levels,
the values of the dividing resistances must be set at the low end olthe tolerance range of the power capacity.
When there is the need to operate with low power, the values of the voltage dividing resisters must be set
high, and the Les must be driven by an op amp voltage follower. In consideration of the use of op amps, va
(the highest voltage setting for driving LCs) and VDD are separated and given separate terminals.
However, when the voltage level of va is below VDD and the voltage difference between the two is large, the
performance of the LC output driver is reduced. Therefore ensure that the voltage gap between va and VDD
is in the range of av to 2.5V.
Connect
•
va and VDD when an op amp is not used.
Cautions During Power Up and Power Down
Because of the high voltage of the LC driving system 01 this LSI, if the power to the logic system is floating
when a high voltage is applied to the LC driving system, then too much current will flow, causing damage to
the LSI.
Follow the sequences below during power up and power down:
Power up: Logic system on
~
LC drive system on (or simultaneous)
Power down: LC drive system off
~
Logic system off (or simultaneous)
In order to prevent excessive current, insert a guard resistance of at least 22 Q in series with V5.
754
SED1633
•
•
EXAMPLE OF CONNECTION
Connections for a 640 x 300 dot matrix LCD
GW-:~
~ r---v
f mM
,
,
,
---------~
LP
,
YOU
YOL
1---
u:::-
~
o
w
en
~
I V2
w
-'
-'
o
,,: V3
!z
o
,: V4
: V5
,,
,
cr:
Q
SEL
640 x 300 DOT
------------------------------------
"'r-v
(1/150 Duty)
o~
w
VOO
E102G) EIOl
6
g
220
220&
---------t1
XOO toXD3
0
"'r
~ 79_t~SE~
-
xsc L
,....
DO
R~
WF
~---------------
Note:
fDl3
Rr+
: Vss H
@M
L'~~rrnf---~
~~CL ~~
11Rr*-
;. I
YSCL
013
SEL
",DO,
Rr+
Rr*-
,
~~~
-~
12r
i
+
,
,
,,: V1
: vo
cr:
v,,
i Voo
0
~r
-
:Vss
,,
u:
~
ow
,,
,,,
,,
,,
,,,
,,
----- YSCl
013
...
SEL
,
,
,
_ _ _ _ _ _ _ _ _ .J
Ei
w
6
'"
4
-,'"
C.l'
SHL
t~SE~
79-t~~~~
79 __
EI02@EIOl
-,'"
u'
--------
SHL
(/}OO-o:
XO....JI.L
0000...0:
f f ! f
f f ! f
EI02®EIO~~
SHL
..J
Cf)
u'
(1)00..0:
xo..Ju..
XO-lI.L
------
tt t
t
--~=====~
------
*1. A guard resistance must be used to prevent excessive current. Moreover, a bypass capacitor (O.OlI1F) should be used
near the Vss and V5 pins of each LSI to prevent noise.
I
755
SED1633
•
PAD LAYOUT
20
30
10
000000000000000000000000000000000000
1
40
.s:::
.8
.6.
E
::J.
0
cO
CD
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
y
Lx
(0,0)
D1633D1B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
110
100
000000000000000000000000000000000000
60
70
80
148.81Jm pitch
SED1663D1A Specifications (The AI Pad Model)
90
-------~
SED1663D1B Specifications (The Au Bump Model)
Chip size ................. 6.03 mm x 4.01 mm
Chip size ................. 6.03 mm x 4.01 mm
Chip thickness ........ 0.400 mm
Chip thickness ........ 0.525 mm
Pad opening ........... 101 mm (X) x 110 mm (Y)
(where the Y direction is the
direction of the chip center line)
Bump size ............... 117 !-1m x 105 !-1m
+10 !-1m
756
Bump height: .......... 20 !-1m
(reference values) -5 !-1m
SED1633
•
PAD COORDINATES
Applicable to the SED1633D1A and SED1633D1B.
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Pad
Name
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
X
Coord.
2604
2455
2306
2158
2009
1860
1711
1562
1414
1265
1116
967
818
670
521
372
223
74
-74
-223
-372
-521
-670
-818
-967
-1116
-1265
-1414
-1562
-1711
-1860
-2009
-2158
-2306
-2455
-2604
-2842
-2842
Y
Coord.
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1596
1428
Pad
No.
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pad
Name
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM 56
COM57
COM58
COM 59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
Unit: J.lm
X
Coord.
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2604
-2455
-2306
-2158
-2009
-1860
-1711
-1562
-1414
-1265
-1116
-967
-818
-670
-521
-372
-223
-74
74
757
Y
Coord.
1260
1092
924
756
588
420
252
84
-84
-252
-420
-588
-756
-924
-1092
-1260
-1428
-1596
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
Pad
No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Pad
Name
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM!;!7
COM98
COM99
DO
DI3
FR
YSCL
SEL
VDD
Vss
VO
V1
V4
V5
DI1
COMO
COM1
COM2
COM3
COM4
X
Coord.
223
372
521
670
818
967
1116
1265
1414
1562
1711
1860
2009
2158
2306
2455
2604
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
Y
Coord.
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1596
-1428
-1260
-1092
-924
-756
-588
-420
-252
-84
84
252
420
588
756
924
1092
1260
1428
1596
I
THIS PAGE INTENTIONALLY BLANK
758
LOW-POWER 100-BIT LCD COMMON DRIVER
•
DESCRIPTION
The SED1634 is a 100 (50 x 2) output dot matrix LCD common (row) driver for driving high-capacity LCD
panels at duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of the LCD driving voltages,
and has its maximum drive voltage, YO, isolated from VDD for flexibility of bias voltage generation.
The SED1634 is used in conjunction with the SED1648 (80-output segment driver) or the SED1600 (80-bit
segment driver) to drive a large-capacity dot matrix LCD panel.
•
FEATURES
• Low-power CMOS technology
• 100-bit (50
• Non-biased display-off function
x 2 structure) common (row) driver
• Pin selection of the output shift direction
• Duty cycle: ......................... 1/64 to 1/300
• LCD voltage: ...................... -12 to -28V
• Low output impedance:
500n typ (V1, V4level)
700n typ (VO, V5 level)
• Package: ............................ AI pad (D1A)
Au bump (018)
• Supply voltage: .................. 2.7 to 5.5V
• Ability to adjust offset bias of the LCD relative to
VDD
•
I
SYSTEM BLOCK DIAGRAM
00- 03
XSCL
LCD
CONTR
LP,FR
YSCL
-
YO
I
ISE01634~
SE01600F
SE01600F
SE01600F
SE01600F I
~~
~~
~~
~~.
1
ISE01634~
320 SEG x 200 COM
DUTY: 1/200
759
.• __.__ ..
_.,,~·O
...• _ ... __ ..._.
--=-.-.~=.=.-===~==~-CO=
.....
__ .__ _ - - - - - - ..
SED1634
•
BLOCK DIAGRAM
0,...(\1
0>
~ ~ ~ ------------------ ~
uuu
0u
Voo
VSS
V1
V4
1
X
I
y
VO Q---V5
--------------- - --
Q-------
Voltage
Control
Circuit
t
FR
LCD Driver
(100 bit)
I----
r--
<
<
~
Level Shifter
(100 bit)
DO
YSCL
SEL
013
Shift Register
(50 x 2 bits)
1
I
'"
y
~
1
I
760
1--9
012
SED1634
•
•
BLOCK DESCRIPTION
Shift Register
This is a bidirectional shift register for common data transmission.
•
Shift Direction
COM 99
COM 0
•
-t
-t
COM 0
COM 99
Level Shifter
This is a level interface circuit for shifting the signal voltage from the logic system level to the LCD driver
system level.
•
LCD Drivers and Voltage Controller Circuit
Outputs the LCD driver voltage.
The relationships between the contents ofthe shift register, the alternating signal FR, and the common output
voltage are as shown in the table below:
Contents of
Shift Register
FR
H
H
L
L
•
COM Output Voltage
V5
Select level
VO
H
V1
L
V4
I
Non-select level
PIN DESCRIPTION
No. of
Pins
Pin Name
1/0
COMOCOM99
0
LCD driver common (row) output.
Changes on the falling edge of the YSCL signal.
012,013
I
Serial data input for the 100 bit shift register. 013 is the intermediate shift
input. (When 013 is unused, tie it to Voo or Vss.)
YSCL
I
I
Serial data shift clock input. Scanning data is shifted at the falling edge.
1
LCD driver output AC signal input
1
FR
Function
100
2
Voo, Vss
Power
Power source for logic. Voo: OV (GND). Vss: -5.0V
2
VO, V1,
V4,V5
Power
Power source for LCD driver. V5: -12 to -28 V
Voo ~ VO ~ V1 > V4 ~ V5
4
SEL
I
Shift Register Operating Configuration Selection:
1
DO
0
SEL
Shift Register Configuration
DI3
H
50x2
Input
L
100 x 1
H/L
1
Shift register data output.
The output changes with the falling edge of the YSCL signal.
Total: 112
761
. SED1634
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Condition
Unit
Power voltage (1)
Vss
-7.0 to +0.3
V
Power voltage (2)
V5
-30.0 to +0.3
V
Power voltage (3)
VO,V1,V4
V5 - 0.3 to + 0.3
V
V
Input voltage
VI
Vss - 0.3 to + 0.3
Output voltage
VO
Vss - 0.3 to + 0.3
V
Output current (1)
10
20
mA
Output current (2)
10COM
20
mA
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-65 to +150
°C
Notes: *1. The voltages are all relative to VDD = av.
*2. Ensure that the relationship between va, V1, and V4 is always as follows: VDD '" va '" V1 '" V4 '" vs.
*3. The LSI may be permanently damaged if the logic system power is floating or Vss is greater than or equal to -2.6V
when power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning
the power on and off.
762
SED1634
•
Unless otherwise noted, VDD = VO = OV,
Vss = -S.OV ± 10%, Ta = -40 to 8SoC
DC Electrical Characteristics
Applicable Pins
Min
Typ
Max
Unit
Power voltage (1)
Vss
Vss
-5.5
-5.0
-2.7
V
Recommended operating
voltage
V5
V5
-28.0
-
-12.0
V
Possible operating
voltage
V5
Function
V5
-
-
-8.0
V
Parameter
Symbol
Conditions
Power voltage (2)
VO
Recommended value
VO
-2.5
-
0
V
Power voltage (3)
Power voltage (4)
V1
V4
Recommended value
Recommended value
V1
V4
219 x V5
V5
-
Voo
7/9 xV5
V
High-level input voltage
VIH
Vss = -2.7 to -5.5V
VIL
012, YSCL,
SEL, 013, FR
0.2 xVss
Low-level input voltage
0.8xVss
High-level output voltage
VOH
10H =-o.3mA
...,---10H =-D.2mA
(Vss = -2.7 to -4.5V)
DO
-0.4
-
Low-level output voltage
VOL
~L=0.3mA
-
-
Vss+0.4
V
-
2.0
f1A
f1A
f1A
--
___
-
-
V
V
V
10L= 0.2mA
(Vss = -2.7 to -4.5V)
Input leakage current
III
VSS,,;VIN";OV
YSCL, SEL,
013, FR
-
012,00
-
-
5.0
Voo
-
-
25
I/O leakage current
ILo
VSS,,;VIN";OV
Static cu rrent
loos
V5 = -12.0 to -28.0V
VIH = Voo, VIL = Vss
Output resistance
RCOM
~IVONI
=0.5V
V5=-20.0V
V5=-14.0V
*(V5 = -B.OV)
-
0.40
0.50
(0.60)
0.80
1.00
(1.20)
-
0.60
0.70
(0.90)
1.20
1.40
(1.80)
-
7
15
--
-5
-10-
V5
-
7
15
f1A
YSCL,SEL,
013, FR
-
-
8
pF
012,00
-
-
15
pF
When
output·
V1.V4
-
COM99
levels
V5 =-20.0V
V5=-14.0V
*(V5 = -B.OV)
COMO
ling the
When
outputtingthe
"Refer·
VO.V5
enca
value
Kn
levels
Average operating
consumption current (1)
ISS1
Vss = -5.0V, VIH = Voo,
VIL = Vss, fvSCL = 12KHz,
Frame frequency =
60KHz, Input data: 1/200,
"H" is without load on
each duty cycle
Vss
-:-;-----Vss = -3.0V; other
parameters are identical
Average operating
consumption current (2)
Input terminal capacitance
I/O terminal capacitance
1SS2
CI
Vss = -5.0V, V1 = -2.0V,
V4=-18.0V,
V5 = -20.0V; other
parameters are the
same as for Iss1
Ta = 25°C
CliO
763
f1A
I
SED1634
•
o
AC Characteristics
Input Timing Characteristics
VIH = O.2Vss
VIL= O.8Vss
FR
--~~-..
~tWCLH-- - t O F R -
t r--
YSCL
It
tWCLL - -
\
~
tCCL
xxxxxxxf______~xxxxxxxxxxx~~xzz
tOS-' .. tOH
DI2
DI3
--I-tf
Unless otherwise noted, Vss = -5.0 ± 10%, To = -40 to 85°C
Parameter
Symbol
Input signal rise time
tr
Inputsignal fall time
tf
Conditions
Min
-
Max
Unit
50
ns
50
ns
ns
ns
tCCL
500
YSCL high-level pulse width
twCLH
70
YSCL low-level pulse width
twCLL
330
Data setup time
tDS
100
-
Data hold time
tDH
10
-
Allowable FR delay
tDFR
-600
YSCL frequency
500
ns
ns
ns
ns
Unless otherwise noted, Vss = -2.7 to -4.5V, Ta = -40 to 85°C
Parameter
Symbol
Input signal rise time
tr
Input signal fall time
tf
Conditions
Min
-
Max
Unit
50
ns
50
ns
tCCL
1000
-
ns
YSCL high-level pulse width
twCLH
160
-
ns
YSCL low-level pulse width
tWCLL
330
tDS
200
-
ns
YSCL frequency
Data setup time
ns
Data hold time
tDH
10
-
ns
Allowable FR delay
tDFR
-600
500
ns
764
SED1634
o Output Timing Characteristics
VIH =O.2Vss
VIL - 0 BVss
FR
X
\ I.-
YSCL
-tpdDOCLVOH = O.2Vss
L(
DO
VOL = O.BVss
~ ~~_____________v_n__)t
tpdCCL--- t CFR -
__________________________
COMn
O_.5_V
Vn+O.5V
Unless otherwise noted, Vss = -5.0V ± 10%, T. = -40 to 85°C
Symbol
Conditions
Min
Max
(YSCL fall ~ DO) delay time
tpdDOCL
CL = 15pF
30
300
ns
(YSCL fall ~ COM output) delay time
tpdCCL
tpdCFR
-
3.0
(FR ~ COM output) delay time
V5 = -12.0 to -28.0V
CL= 100pF
IJ.S
IJ.S
Parameter
3.0
Unit
Unless otherwise noted, Vss = -2.7 to -4.5V, T. = -40 to 85°C
Parameter
(YSCL fall ~ DO) delay time
Conditions
Symbol
IpdDOCL
CL = 15pF
(YSCL fall ~ COM output) delay time
tpdCCL
(FR ~ COM output) delay time
tpdCFR
V5 = -12.0 to -28.0V
CL = 100pF
765
Min
Max
Unit
60
600
ns
-
3.0
IJ.S
3.0
Ils
I
SED1634
•
Timing Diagram
1 Frame
Fora 11200
Duty Cycle
Dl2
'--------~
YSCL
----JIJ
FR
Re~~fters[::
Within
Thole
097
---t----'
COM98[=~~
-V4
-V5·
COM97[=~~
......
-V4 .... .
-V5·
766
SED1634
•
•
EXAMPLE OF CONNECTION
Connections for a 640 x 300 dot matrix LCD
--
iL
:;:
0W'"
(fJ
lL"
LO
'"0
-- - - - - - - - - - - - - - - -
LP
VOU
VOL
- -,
~-
I-------------~
,,,
Vss
, Vss
,,
Voo
,,,
,, VO
V1
W
~
a:
w
V2
...J
...J
V3
a:
V4
0
V5
0
fZ
()
WF--------T-------r---~--------------r1--~--+_--rf--~--+_
XDOtoXD3
---+------~------------~~----~----rf----~----_+_
,
- - - - - -- - - - - - - -- - - - - - - - - - - --
Note:
*1. A guard resistance must be used to prevent excessive current. A bypass capacitor (0.01 ~F) should be used near the
Vss and V5 pins of each LSI to prevent noise.
I
767
SED1634
•
PAD LAYOUT
1...._ _ _ _ _ _ _1_48_._8!-llm_P_it_Ch_ _ _ _ _ _ _---...1 20/1
o
o
~
.c
.8
0:
E
:::i.
o
CD
o
0
~
0
0
0
0
0
0
110
OLD
o
o
o
o
o
y
o
0
o
o
o
o
o
o
B
(0,0)
000000000000000000000000000000000000
60
70
80
.c
.8
0:
E
0
0
0
X
B
a:)
10
20
30
000000000000000000000000000000000000
0
0
0
0
0
0
0
0
:::i.
100
C!
co
CD
90
1....---------------------...1
20/1
148.81lm Pitch
SED1634D1A Specifications (The AI Pad Model)
SED1634D1B Specifications (The Au Bump Model)
Chip size ................. 6.03 mm x 4.01 mm
Chip size ................. 6.03 mm x 4.01 mm
Chip thickness ........ 0.400 mm
Chip thickness ........ 0.525 mm
Pad opening ........... 101 mm (X) x 110 mm (Y)
(where the Y direction is the
direction ofthe chip center line)
Bump size ............... 117 Ilm x 1051lm
+10 Ilm
768
Bump height: .......... 20 Ilm
(reference values) -5Ilm·
SED1634
•
PAD COORDINATES
Applicable to the SED1634D1A and SED1634D1B.
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Pin
Name
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
X
Coord.
2604
2455
2306
2158
2009
1860
1711
1562
1414
1265
1116
967
818
670
521
372
223
74
-74
-223
-372
-521
-670
-818
-967
-1116
-1265
-1414
-1562
-1711
-1860
-2009
-2158
-2306
-2455
-2604
-2842
-2842
Y
Coord.
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1596
1428
Pad
No.
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pin
Name
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
Units:
X
Coord.
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2842
-2604
-2455
-2306
-2158
-2009
-1860
-1711
-1562
-1414
-1265
-1116
-967
-818
-670
-521
-372
-223
-74
74
769
Y
Coord.
1260
1092
924
756
588
420
252
84
-84
-252
-420
-588
-756
-924
-1092
-1260
-1428
-1596
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
Pad
No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Pin
Name
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
012
013
FR
YSCL
SEL
VDD
Vss
VO
V1
V4
V5
010
COMO
COM1
COM2
COM3
COM4
X
Coord.
223
372
521
670
818
967
1116
1265
1414
1562
1711
1860
2009
2158
2306
2455
2604
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
~m
Y
Coord.
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1596
-1428
-1260
-1092
-924
-756
-588
-420
-252
-84
84
252
420
588
756
924
1092
1260
1428
1596
I
THIS PAGE INTENTIONALLY BLANK
770
LCD COMMON DRIVER
•
DESCRIPTION
The SED1635 is a dot matrix LCD common (row) driver for use with high-capacity, high duty cycle LCD
panels. The SED1635 has 100 common driver outputs and can operate at a duty cycle of up to 1/300. The
driver is used with the SED1640D. The driver is designed to work over a wide range of LCD drive voltages
and has its maximum drive voltage, YO, isolated from Voo for flexibility of bias voltage generation.
The driver's pad layout is designed for easy mounting on boards and the bi-direction of driver output order
can be selected. The driver has 100 LCD outputs with high resistance voltage and low output impedance.
As a result, the driver achieves the maximum driver usage for the 1/200 duty panel.
•
FEATURES
• 100 common drive outputs
• Adjustable offset bias of LCD power for Voo
level
• Output resistance:
soon typical, at V1 and V4 levels
700n typical, at VO and V5 levels
• Wide range of LCD drive voltages: 12 - 28V
(absolute maximum rated voltage is 30V)
• Duty ratio from 1/64 to 1/300
• Logic power supply: -2.7V to -5.5V
• Maximum configuration: 640 x 480 pixels
when used with the SED1640D
• CMOS Si-Gate process
• Package chip
SED1635D1A:
• Selectable shift direction
SED1635D1B:
•
BLOCK DIAGRAM
o
COM
99
T··. . . . . . .
V1
V4
VO
V5
FR
Voltage
Control
Circuit
,
--r
LCD Driver
100 bit
('t
Voo
Level Shifter
100 bit
Vss
("r
0101
,
YSCL
SHL
Shift Register
100 bit
I
DOFF
0102
771
AI pad
Gold bump
I
SED1635
•
•
I
BLOCK DESCRIPTION
Shift Register
!
The shift register shifts common data bi-directionally through the driver.
•
Level Shifter
This is the level interface circuit that converts a signal voltage level from the logic level to the LCD driver level.
•
LCD Driver and Voltage Control Circuit
The LCD driver voltage is output.
The relationship among the blanking control signal (DOFF ), shift register contents, the LCD AC-drive
waveform (FR) and the common output level are given in the table below.
DOFF
Shift Register Data
H
H
L
L
Fixed to L
FR
H
L
H
L
-
COM Output Level
V5
VO
V1
V4
VO
772
(Selected level)
(Not selected level)
SED1635
•
PIN DESCRIPTION
Pin Name
1/0
COMO to COM99
0
LCD drive common low.
Changes with YSCL falling edge.
0101,0102
1/0
Serial data 1/0 of 100-bit bidirectional shift register.
Serial data input/output pin. Configured by SHL.
Output changes with YSCL falling edge.
2
YSCL
I
Serial data shift clock input.
Data is shifted into the driver on the falling edge of this signal.
1
SHL
I
Shift direction and input/output selection input.
1
DOFF
I
Functions
No. of pins
100
SHL
L
COM data shift direction
0101
0102
0-->99
Input
Output
H
99 --> 0
Output
Input
Active low blanking control input.
The shift register contents are cleared by low-level input,
and all common output instantly changes to the VO level.
FR
I
Voo, Vss
Power
supply
Logic power input.
LCD AC drive signal input.
Voo: OV (GND)
VO, V1, V4, V5
Power
supply
LCD drive power input.
V5: -12V - -28V
Voo <': V- <': V1 <': V4 <': V5
1
1
Vss: -5.0V
2
4
Total 112
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Unit
Supply voltage 1
Parameter
Vss
-7.0 to +0.3
V
Supply voltage 2
V5
-30.0 to +0.3
V
Supply voltage 3
VO, V1, V4
V5 - 3.0 to +0.3
V
Input voltage
VI
Vss - 0.3 to +0.3
V
Output voltage
Va
Vss - 0.3 to +0.3
V
Output current 1
VO
20
mA
Output current 2
loeaM
20
mA
PO
300
mW
Power dissipation
Operating temperature
TaPR
-40 to +85
°C
Storage temperature
TSTG
-65 to +150
°C
1. All voltages are given relative to Voo = OV.
2. YO, V1, and V4 must satisfy the condition Voo ;::, VO ;::, V1 ;::, V4 ;::, 5
3. Exceeding the absolute maximum ratings can cause permanent damage to the device. Function operation under these
conditions is not implied.
773
I
SED1635
•
DC Electrical Characteristics
Unless otherwise stated, VDD = VO = OV, Vss = -5.0V ± 10%, Ta = -40 to B5°C
Parameter
Symbol
Conditions
Pin
Min
Typ
Max
Unit
Vss
-5.5
-5.0
-2.7
V
V5
-2B.0
-
-12.0
V
-
-B.O
V
Supply voltage 1
Vss
Recommended
operating voltage
V5
Minimum operating
voltage
V5
Supply voltage 2
VO
Recommended value
VO
-2.5
Supply voltage 3
V1
Recommended value
V1
2/9 x V5
Supply voltage 4
V4
Recommended value
High-level output voltage
VIH
Low-level output voltage
VIL
Vss = -2.7 to -5.5V
V5
Vss = -2.7 to -5.5V
10H =-0.3 mA
High-level output voltage
VOH
--,----
Input, I/O leakage current
Static current
VOH
10L =-0.2 mA
(Vss = -2.7 to -4.5V)
7/9 x V5
O.B x Vss
-
-
V
V
V
V
-
-
Vss + 0.4
V
-
2.0
j.!A
YSCL, SHL,
DOFF, FR
-
ILiIO
Vss:S VIN:S OV
D101, DI02
-
-
5.0
j.!A
IDDs
V5 = -12.0 to -2B.0
VIH = VDD, VIL = Vss
VDD
-
-
25
j.!A
V1, V4
Output
Level COMO
to
YO, V5 COM99
Output
Level
-
Vss
-
RCOM
#VON
=0.5V
(V5 =-B.OV)
V5 =-20.0V
(V5 =-B.OV)
IS81
Vss = -5.0V, VIH = VDD,
VIL = Vss, fYSCL = 12 kHz,
Frame frequency = 60 Hz,
Input data: "H" every
1/200 no-load
Vss =-3.0V
Iss2
CI
Vss=-5V, V1 =-2V, V4=
-1BV, V5 = -20V, other
conditions are same as Iss1
Ta = 25°C
CliO
774
O.BO
0.40
0.50
1.00
(0.60)
(1.20)
0.60
1.20
0.70
1.40
(0.90)
(1.BO)
7
15
--- -5
--,-.-----
Input capacitance
V
V
Vss:S VIN :SOV
V5 = -14.0V
Current consumption (2)
-
0
VDD
III
V5 =-20.0V
Current consumption (1)
-0.4
------
V5=-14.0V
Output resistance
V5
0.2 xVss
-
D101, DI02
IOL =-0.3 mA
Low-level output voltage
V4
D101, D102,
YSCL, SHL,
DOFF, FR
--
10H =-0.2 mA
(Vss = -2.7 to -4.5V)
-
'--
KQ
j.!A
-10
V5
-
7
15
j.!A
YSCL, SHL,
DOFF, FR
-
-
B
pF
D101, DI02
-
-
15
pF
SED1635
•
o
AC Electrical Characteristics
Input Timing
VIH= 0.2 Vss
Vll= 0.8 Vss
-~1---
FR
-
Ir +
YSCL
-If
-IOF""
~ tWClH-
•
•
twell
~
~f',
Z
•
los-
~f',
•
teel
-tOH+
DI01
DI02
Vss
Parameter
Condition
Min
=-5.0 ± 10%, Ta =-40 to 85°C
Max
Unit
Input signal rise time
tr
-
-
50
ns
Input signal fall time
tf
-
50
ns
tCCl
500
tWClH
70
YSCL "L" pulse width
twCll
330
Data setup time
tDS
100
-
ns
YSCL "H" pulse width
-
Data hold time
tDH
10
-
ns
Allowable FR delay time
tDFR
-500
-
500
ns
YSCLperiod
Symbol
Typ
ns
ns
ns
Vss = -2.7 to 4.5V, Ta = -40 to 85°C
Parameter
Symbol
Input signal rise time
tr
Input signal fall time
tf
YSCL period
Condition
Min
-
tCCl
1000
YSCL "H" pulse width
twClH
160
YSCL "L" pulse width
tWCll
330
Data setup time
tDS
200
Data hold time
tDH
10
Allowable FR delay time
tDFR
-500
775
Max
Unit
-
50
ns
-
50
ns
-
ns
-
-
ns
Typ
500
ns
ns
ns
ns
I
SED1635
o Output Timing
VIH=0.2Vss
~
FR
VIL= 0.8 V ss
YSCL
-
tpdDOCL--
0101
VOH=0.2 Vss
~K
0102
VOL = 0.8 VSS
- - tpdCCL -----
DOFF
~
- - tpdCFR -------+
•
tpdCDOFF
~
Vn-0.5
~
COM
Vn + 0.5
Vss
Parameter
Symbol
YSCL fall edge to 010 delay
tpdDOCL
YSCL fall edge to COM delay
DOFF to COM delay
FR to COM delay
Condition
CL
tpdCCL
tpdCDOFF
VS
tpdCFR
= 1SpF
=-12.0 to -28.0V
CL = 100pF
Min
=-S.O ± 10%, Ta =-40 to 8SoC
Max
Unit
30
Typ
-
300
ns
-
-
3.0
Ils
-
-
3.0
Ils
Vss = -2.7 to 4.SV, Ta = -40 to 8SoC
Parameter
Symbol
Condition
Min
Max
Unit
YSCL fall edge to 010 delay
tpdDOCL
CL = 1SpF
60
-
400
ns
YSCL fall edge to COM delay
tpdCCL
-
-
3.0
Ils
-
-
3.0
Ils
DOFF to COM delay
FR to COM delay
tpdCDOFF
tpdCFR
VS
=-12.0 to -28.0V
CL = 100pF
776
Typ
SED1635
•
Timing Chart
__
1 Frame
SHL = "L"
1/200Duty
(200 Line)
DI01
YSCL
FR
Jl
______ Sl
______ YL
JUlJlJlJ1f------JUlJlJlJ1f ------JLJUl
I ,--,- - - - ------_---1
-------I
f - ,-
DOFF
--7------- ------
-
-------~~::---1
~
00
,
______ ~ _ ______ --i-1---l:_
!
Shift
Register
". n
~
,
,
~ --- -- - ,
,
,
,
n'----,- ----------+-:.---'---,--'
~------~---------:-DI02
. - - - 100 Line
n
--R
_
,--,_ . ; . - -_ _----'
VO
V1
COM1
V4
V5
VO
V1
COM2
V4
V5
777
L-_'-_
I
SED1635
•
•
LCD DRIVER POWER SUPPLV
Generating LCD Drive Voltages
The easiest way to generate LCD drive voltage is by the split resistors. To obtain a high quality display, it is
mandatory that voltage levels be precise and stable. Setthe split resistor values as low as the system's power
capacity allows. In particular, when low power is required, set the split resistors high and, instead, drive each
level with the voltage follower using the operation amplifier. To use an operation amplifier, VO and Voo are
separated in this device. (VO is the maximum potential level forthe LCD driver.) However, if the VO potential
falls below the Voo potential and, as a result, the potential difference is large, the LCD driver capability
decreases. To avoid this, set the Voo and VO within OV to 2.5V. If an operation amplifier is not used, connect
the VO and Voo.
•
System Power-Up
This LSI has high LCD drive voltage. As a result, if the logic power is being floated and high voltage is applied
in the LCD driver, the LSI may be damaged because of the excess current.
Follow the sequence given below when turning power on or off.
To turn on the power
-
Turn on the logic power
~
Turn the LCD driver on
(or turn them on simultaneously)
To turn off the power
-
Turn off the LCD driver
~
Turn off the logic power
(or turn them off simultaneously)
778
SED1635
•
PAD DIMENSIONS
-1
40
o
o
o
o
o
o
10
30
20
000000000000000000000000000000000000
0
0
0
0
110
0
0
OLD
o
~
B
.0.
E
:::l.
0
cO
~
50
y
o
o
~
o
o
o
o
o
o
o
o
1
0
0
0
X
~
(QO)
0
100
0
0
0
0
0
0
0
000000000000000000000000000000000000
60
70
1...- - - - - - - - -
80
148.8~m pitch
(1) Aluminum pad chip specification
Chip size ................ 6.03 x 4.01 x 0.400 mm
Hole in pad ............ 108 x 110 11m
(2) Gold bumped chip specification (reference)
Chip size ................ 6.03 x 4.01 x 0.525 mm
Bumping size ......... 117 x 105 11m (±20 11m)
Bumping height... ... 20 +1 Ol1m
-5 11m
779
90
~I
I
SED1635
•
•
PAD COORDINATES
SED1635DoA PAD COORDINATES
Unit: 11m
Pad
No.
Pin
Name
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
2604
2455
2306
2158
2009
1860
1711
1562
1414
1265
1116
967
818
670
521
372
223
74
-74
-223
-372
-521
-670
-818
-967
-1116
-1265
-1414
-1562
-1711
-1860
-2009
-2158
-2306
-2455
-2604
-2847
-2847
-2847
-2847
Y
Pad
No.
Pin
Name
X
Y
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1839
1596
1428
1260
1092
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2604
-2455
-2306
-2158
-2009
-1860
-1711
-1562
-1414
-1265
-1116
-967
-818
-670
-521
-372
-223
-74
74
223
372
521
670
818
924
756
588
420
252
84
-84
-252
-420
-588
-756
-924
-1092
-1260
-1428
-1596
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
780
Pad
No.
Pin
Name
81 COM85
82 COM86
83 COM87
84 COM88
85 COM89
86 COM90
87 COM91
88 COM92
89 COM93
90 COM94
91 COM95
92 COM96
93 COM97
94 COM98
95 COM99
96
0102
97
DOFF
98
FR
99
YSCL
100
SHL
101
VDD
102
Vss
103
VO
104
V1
105
V4
106
V5
107
0101
108 COMO
109 COM1
110 COM2
111 COM3
112 COM4
X
Y
967
1116
1265
1414
1562
1711
1860
2009
2158
2306
2455
2604
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
2847
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1839
-1596
-1428
-1260
-1092
-924
-756
-588
-420
-252
-84
84
252
420
588
756
924
1092
1260
1428
1596
SED1635
•
SED1635DoB PAD COORDINATES
Unit: I-lm
Pad
No.
Pin
Name
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
2604
2455
2306
2158
2009
1860
1711
1562
1414
1265
1116
967
818
670
521
372
223
74
-74
-223
-372
-521
-670
-818
-967
-1116
-1265
-1414
-1562
-1711
-1860
-2009
-2158
-2306
-2455
-2604
-2847
-2847
-2847
-2847
Y
Pad
No.
Pin
Name
X
Y
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1834
1596
1428
1260
1092
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2847
-2604
-2455
-2306
-2158
-2009
-1860
-1711
-1562
-1414
-1265
-1116
-967
-818
-670
-521
-372
-223
-74
74
223
372
521
670
818
924
756
588
420
252
84
-84
-252
-420
-588
-756
-924
-1092
-1260
-1428
-1596
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
781
Pad
No.
Pin
Name
X
Y
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
0102
DOFF
FR
YSCL
SHL
Voo
Vss
VO
V1
V4
V5
0101
COMO
COM1
COM2
COM3
COM4
967
1116
1265
1414
1562
1711
1860
2009
2158
2306
2455
2604
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
2842
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1834
-1596
-1428
-1260
-1092
-924
-756
-588
-420
-252
-84
84
252
420
588
756
924
1092
1260
1428
1596
I
THIS PAGE INTENTIONALLY BLANK
782
SED1651
LOW-POWER 100-BIT LCD COMMON DRIVER
•
DESCRIPTION
The SED1651 is a 1OO-output dot matrix LCD common (row) driver for driving high-capacity LCD panels
at duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of the LCD driving voltages,
and has its maximum drive voltage, VO, isolated from VDD for the flexibility of bias voltage generation.
The SED1651 is used in conjunction with the SED1648 (80-outputsegment driver) or the SED1640 (80bit segment driver) to drive a large-capacity dot matrix LCD panel.
•
•
FEATURES
• Low-power CMOS technology
• Non-biased display off function
• 100-bit common (row) driver
• Pin selection of the output shift direction
• Low output impedance ..................... 750Q (typ)
• LCD voltage ...................................... -8 to -28V
• Duty cycle ..................................... 1/64 to 1/300
• Supply voltage .................................. 2.7 to 5.5V
• Ability to adjust offset bias of the LCD relative to
VDD
• Package .......................... Slim AI pad DIE (DOA)
SYSTEM BLOCK DIAGRAM
I
DO- D3
XSCL
LP,FR
LCD
CONTR
-
YSCL
YD
I
SED1648
SED1651
•
SED1651
~
I
I
100
~
-V
,I
1
SED1648
~~
~~
160 X 200 dots
DUTY: 1/200
783
I
SED1651
•
BLOCK DIAGRAM
00----------------- 099
1--
---------
----I
VO
Vi
LCD Driver
100 bits
V4
V5
}
FR
{'r
Level Shifter
100 bits
Vss
{'r
Voo
DI01
Bidirectional Shift Register
50 x 2 bits
YSCL
+
SHL
r
DSPOFF
SEL
DI3 DI02
•
•
BLOCK DESCRIPTION
Enable Shift Register
This is a bidirectional shift register used for transmitting common data. The shift register has a 50 x 2 bit
structure, and is selectable to 50 x 2 bits or 100 bits depending on the setting of SEL.
When the 50 x 2 bit configuration is selected, the input for the second 50 bit shift register is 013.
•
Level Shifter
The level shifter is a level interface circuit which converts the signal voltage level from a logic circuit level to
the LC driver voltage level.
•
LCD Driver
The LCD driver outputs the LC drive voltage.
The relationship between the display blanking signal DSPOFF, the contents of the shift register, the AC signal
FR, and the On output voltage is as follows:
DSPOFF
Contents of Shift Register
H
H
L
L
-
o Output Voltage
FR
H
V5
L
va
H
Vi
L
V4
-
va
784
(Select level)
(Non-select level)
-
SED1651
•
PIN DESCRIPTION
Pin Name
I/O
00 to 099
0
0101
0102
I/O
013
I
No. of
Pins
Function
Common (row) output to drive LC.
Output transition occurs on falling edge of YSCL.
100
50 x 2 bit bi-directional shift register serial data I/O.
2
This is set to input or output depending on the level of the SHL input.
Output transition occurs on falling edge of YSCL.
1
Scan pulse input terminal of the 50 x 2 structure.
When SEL = L, 013 = Vss or GND.
SEL
I
1
Bi-directional shift register operating mode select input
H: 50 x 2 (013 input) L: 100
YSCL
I
Serial data shift clock input (shifts scan data on falling edge).
1
SHL
I
Shift direction select and 010 terminal 1/0 control input.
1
010
o Output Shift Direction
SHL
L
0
-7
49
50
-7
99
1
I
H
99
-7
50
49
-7
0
0
2
0
I
When SEL = "H", the 013 input is input to 050 (SHL = "L") or 049 (SHL = "H").
When SEL = "L", the 013 input is ignored and the 010 input is continuously
shifted.
DSPOFF
I
LC display blanking control input. A low level clears the shift register,
immediately causing all common outputs to go to VO.
1
FR
I
LC drive output AC signal input.
1
Voo, Vss
Power
Power source for logic:
3
Voo: OV (GND)
Vss: -2.7 to -5.5V
VO, V1,
V4, V5
Power
LC Drive Circuit Power:
V5: -8 to -28V
Voo
~VO ~
V1 > V4
~
8
V5
Total 119
785
~~~-~
---~
----
I
SED1651
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Condition
Unit
Power voltage (1)
Vss
-7.0 to +0.3
V
Power voltage (2)
V5
-30.0 to +0.3
V
Power voltage (3)
YO, V1, V4
V5 - 0.3 to + 0.3
V
Input voltage
VI
Vss - 0.3 to + 0.3
V
Output voltage
VO
Vss - 0.3 to + 0.3
V
Output current (1)
10
20
mA
Output current (2)
Parameter
10COM
20
Operating temperature
Topr
-40 to +85
mA
DC
Storage temperature (1)
Tstg1
-65 to +150
DC
Notes: *1. The voltages are all relative to VDD = OV.
*2.
Ensure that the relationship between YO, V1, V4, and V5 is always as follows: VDD
~
VO
~
V1
~
V4
~
V5.
System Side
Vcc
•
5V
GND
---VDD---,--------,----------- VDD
VO
,
-5V
I
--- Vss --"'---
V1
-28V
~
V4
V5
*3. The LSI may be permanently damaged if the logic system power is floating or Vss is less than or equal to -2.6V when
power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning
the power on and off.
786
SED1651
•
Unless otherwise specified, VDD = VO = OV,
Vss = -5.5 to -2.7V, Ta = -40 to 85°C
DC Electrical Characteristics
Applicable Pins
Min
Typ
Max
Unit
Power voltage (1)
Vss
Vss
-5.5
-5.0
-2.7
V
Recommended operating
voltage
V5
V5
-28.0
-
-12.0
V
Possible operating
voltage
V5
V5
-
-
-8.0
V
Power voltage (2)
VO
VO
-2.5
Power voltage (3)
Power voltage (4)
V1
V4
219 x V5
V5
-
High-level input voltage
VIH
Low-level input voltage
VIL
V1
V4
0101. 0102. FR,
YSCL. SHL. 013,
OSPOFF.SEL
High-level output voltage
VOH
Low-level output voltage
VOL
Parameter
Input leakage current
Symbol
III
Conditions
Function operation
1/0 leakage current
ILiIO
VSS~VIN ~OV
loos
V5 = -12.0 to -28.0V
VIH = Voo, VIL = Vss
Output resistance
Average operating
consumption current (1)
1/0 terminal capacitance
V
Vss + 0.4
V
2:0
!lA
-
-
5,0
VOO
-
25
!lA
!lA
0101,0102
Voo-0.4
-
V
RCOM
AIVONI = 0.5V, VO = Voo,
V1 = -1.5V, V4 = -18,5V,
V5=-20,OV
00 to 099
-
0.75
1.0
Kn
ISSl
Vss = -5.0V, VIH = Voo,
VIL = Vss, fvSCL = 12KHz,
Frame frequency = 60 Hz,
Input data: 1/200;
Ta = 25°C, Each duty
cycle is "H", no load
Vss
-
7
15
!lA
1--- - -
-
5
V5
-
YSCL, SHL, SEL,
OSPOFF, FR, 013
0101,0102
Vss = -3.0V; other
parameters are the same
as for Vss = -5.0V
Input terminal capacitance
V
-
r-----
Average operating
consumption current (2)
0.8 x Vss
VSCL. SHL, 013,
OSPOFF, FR, SEL
Static cu rrent
-
-
10L= 0.3mA
VSS~VIN ~OV
-
V
V
-
0101,0102
10H =-Q.3mA
0.2 x Vss
0
Voo
7/9 x V5
Iss2
CI
VSS = -5.0V, VO = OV,
V1 =-1.5V, V4=-18.5V,
VEE =V5 = -20.0V;
other parameters are
the same as for ISSl
Ta = 25°C
CliO
787
f--- f--10
!lA
7
15
!lA
-
-
8
pF
-
-
15
pF
I
SED1651
•
o
AC Characteristics
Input Timing Characteristics
VIH = 0.2 x Vss
VIL =0.8 x Vss
FR
--~'-------. IItWCLL-
.tWCLH"
YSCL
-
.tOFR
tr
11
t,
V
•
tCCL
•
• tos'" ... tOH
0101
0102
013
Vss = -5.0 ± 10%, T. = -40 to 85°C
Parameter
Min
Max
Unit
Input signal rise time
tr
-
50
ns
Input signal fall time
If
-
50
ns
tCCL
500
-
ns
YSCL high-level pulse width
tWCLH
70
ns
YSCL low-level pulse width
twCLL
330
Data setup time
tos
100
Data hold time
tOH
10
-
Allowable FR delay
tOFR
-300
YSCL frequency
Symbol
Conditions
300
ns
ns
ns
ns
Vss = -4.5 to -2.7V, Ta = -40 to 85°C
Max
Unit
Input signal rise time
Parameter
Symbol
tr
Conditions
Min
-
50
ns
Input signal fall time
If
-
50
ns
tCCL
1000
·ns
YSCL high-level pulse width
twCLH
160
-
YSCL low-level pulse width
twCLL
330
-
ns
Data setup time
tos
200
-
ns
Data hold time
tOH
10
-
ns
Allowable FR delay
tOFR
-500
YSCL frequency
788
500
ns
ns
SED1651
o Output Timing Characteristics
VIH = 0.2 x Vss
VIL = 0.8 x Vss
)<
FR
YSCL
- - tpdDOCL - -
0101
0102
Vo H = 0.2 x Vss
Vo L=0.8xVss
K
-tpdCCL -
OSPOFF
)<
-tpdCFR,--tpdCDOFF-
Vn -0.5
Vn + 0.5
:x
On
Vss = -S.OV ± 10%, T. = -40 to 8SoC
Symbol
Conditions
Min
Max
Unit
(YSCL fall -7 010) delay time
tpdDOCL
CL= 1SpF
-
3S0
ns
(YSCL fall -7 On output) delay time
tpdCCL
(DSPOFF -7 On output) delay time
tpdCDOFF
VS = -12 to -28.0V
-
1.0
115
CL= 100pF
-
1.0
I1s
Parameter
(FR -7 On output) delay time
tpdCFR
Vss = -4.S to -2.7V, T. = -40 to 8SoC
Symbol
Conditions
Min
Max
Unit
(YSCL fall -7 010) delay time
tpdDOCL
CL= 1SpF
-
400
ns
(YSCL fall -7 On output) delay time
IpdCCL
(DSPOFF -7 On output) delay time
tpdCDOFF
VS = -12 to -28.0V
-
2.0
I1s
CL= 100pF
-
2.0
I1s
Parameter
(FR -7 On output) delay time
tpdCFR
789
I
SED1651
o Timing Diagram
Timing diagram (assuming 1/200 duty). (This diagram provided only as a reference)
1 frame
:~
:
0101
(013)
YSCL
FR
SHL = "L"
1/200 duty
~,
n
(200 lines)
,
rtl
-----~
:
,
I
-------IL
,
J1rulJU1J-------J1rulJU1J-------JUlJl
I
------~
;
------~
-
' - - - ;
-----'I---'
OSPOFF
,
,
,
~ ______ ~ ______ ~r-----'
Q1,
~I---:,
Shift
Register
:
n
,n
_____
,
~------~---------J
*
0102
:"'~1--_1_0_0_lin_e_s_----jRL._ _-+,_ _ _ _ _ _---,nL._ _+-___
:(*SEL=H, during 013 input. 50 lines):
,,
,
,,
~~m'f
00
• • • • • ··.r ••· n.•
,
u-_-_-_-__-_
_.::::~1-:
~i •••• :•••• nmm. nmnn.•.-. -:-: m! .~_::::: m1:: mnnn
,
,
.mi···jmj•••. n. ••••••.·.·••••••• +nmn.:.:.:::::J.
~: ·.:··i. m. _.•.. mnnnnn:::-:-:mj ••·~·nL ••••••••••••••••·.·.....1.-.·...
~~ nnllmjnninum _
. . _.. m.:.:.:.:::::j. m
~: :••••'nn...:---.:.mnL ••••••·~n·l •••••._•••••••••.•••• j ••••••••••
~~
o
1
,
02
790
,
SED1651
•
LCD DRIVING POWER
•
Method of Forming Each Voltage Level
The simplest way to obtain the voltage levels for driving the LCs is to use resistive voltage dividers between
VS and Voo, and to drive the LCs with op amp voltage followers.
In consideration of the use of op amps, VO and Voo are separated and given separate terminals. When op
amps are not going to be used, connect VO to Voo.
When a resistive voltage divider is used, select the lowest resistances allowed by the system power supply
tolerances.
Permanent damage may resultto the LSI when there is serial resistance in the Voo power line. This is because
the voltage drop that will occur at Voo will cause the power level relationships within the LCD (i.e., VOO;:>: VO
;:>: V1 > V4 ;:>: VS) to fail.
When a guard resistance is inserted, voltage stabilization using a capacitance is necessary.
•
Cautions During Power Up and Power Down
Because of the high voltage of the LC driving system of this LSI, if the power to the logic system is floating
or if Vss is less than or equal to -2.SV when a high voltage is applied to the LC driving system, then too much
current will flow, causing damage to the LSI.
It is recommended that the display off function (DSPOFF) be used to keep the LCD driver output level at VO
until the LCD drive system voltage stabilizes.
Follow the sequences below during power up and power down:
Power up: Logic system on
~
LC drive system on (or simultaneous)
Power down: LC drive system off
~
Logic system off (or simultaneous)
As a way to prevent excessive current, insert a high-speed fuse or guard resistance in series with the LC
power source.
The optimal value of the guard resistance must be selected based on the capacitance of the LC cells.
V
VDD
Vss
VS
....
t1
....
II
~
\
----------- 1 - - - - - - - - - - - - - ' ------------Power
ON
DSPOFF
t2
-~
t1,t2,t3 Os
Power
OFF
t3
....--..
VDD ---------------Vss
791
... _------- ..
-----
I
SED1651
•
•
EXAMPLE OF CONNECTION
Large Screen LCD Structure Diagram
R
V5
Vss
V5
YO
YSCL
SHL
FR
SEL
(GND)
~
0101
~
V4
V3
VO Vee
u:; ~
~o
0101
-~
640 x 200 OOT
~
~8
~1
0102
1/2000UTY
013= H orL
Vee
LP
XSCL
SHL
OSPOFF
010 -3
V1
<00
[Dl02 mV
~::::
V2
<,,80~
<,,80>
SE01648
EI01
EI02
CD
SE01648
EI01
EI02
ttttt
t t t t,
®
-----
------
------
-----------
------
792
<,,80>
SE01648
EI01
EI02
®
t
flq
SED1651
•
PAD LAYOUT
109
110
o
+Y
o
o
0 0
119
00
30
29
00000000000000000000000000000000000000000000000000000000000000000000000000000000 0
DO
0
0
0
0
0
0
0
0
0
0
0
00
0
X
0
DO
0
0
0
0
0
0
0
0
00
20
19
Chip size .................. 13.43 mm x 1.76 mm
Chip thickness ......... 400 11m (TYP)
AI Pad Specifications (SED1651DOA)
[JJ [JJ,L
: - 475u ~ (min)
I
-- - -- -- -- ~, -- -- - - - - -- -- -- - -:, --- - -- -- - - ---chip edge
--
-
'-
Pad a aperture (X, Y): ................... 110 x 110 11m PAD No. 30-109
Pad b aperture (X, Y): ................... 110 x 110 11m PAD No. 20-29,110-119
Pad c aperture (X, V): ................... 110 x 110 11m PAD No. 1-19
793
I
SED1651
•
PAD COORDINATES
Pad
No.
Pad
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0102
VO
Vi
V4
V5
Vss
SEL
SHL
013
YSCL
Voo
OSPOFF
FR
Vss
V5
V4
Vi
VO
0101
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
X
Unit: /-lm
Coord.
Y
Coord.
Pad
No.
Pad
Name
-5985
-5510
-5035
-4560
-4038
-3164
-2280
-1767
-1064
-181
770
1283
2176
2879
3753
4560
5035
5510
5985
6560
6430
6560
6430
6560
6430
6560
6430
6560
6430
6079
5925
5771
5617
5463
5310
5156
5002
4848
4694
4540
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-709
-610
-466
-321
-177
-32
112
257
401
545
690
727
727
727
727
727
727
727
727
727
727
727
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
021
022
023
024
025
026
027
028
029
030
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
X
Coord.
Y
Coord.
Pad
No.
Pad
Name
Coord.
Y
Coord.
4386
4232
4078
3924
3771
3617
3463
3309
3155
3001
2847
2693
2539
2385
2232
2078
1924
1770
1616
1462
1308
1154
1000
846
693
539
385
231
77
-77
-231
-385
-539
-693
-846
-1000
-1154
-1308
-1462
-1616
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
-1770
-1924
-2078
-2232
-2385
-2539
-2693
-2847
-3001
-3155
-3309
-3463
-3617
-3771
-3924
-4078
-4232
-4386
-4540
-4694
-4848
-5002
-5156
-5310
-5463
-5617
-5771
-5925
-6079
-6430
-6560
-6430
-6560
-6430
-6560
-6430
-6560
-6430
-6560
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
727
690
545
401
257
112
-32
-177
-321
-466
-610
X
794
SED1733
• CMOS 1~O-Bit Common Driver
• High-Voltage LCD Driver
•
DESCRIPTION
The SED1733 is a 100-bit output LCD common (row) driver for driving high-capacity LCD panels at duty
cycles higher than 1/100 (up to 1/500). The LSI features a wide range of LCD drive voltages.
The device uses a high-speed daisy-chain enable system which decreases power consumption and
eliminates the need for separate signals for each driver.
The SED1733 is used in conjunction with the SED1722 or SED1724 segment drivers to support a largecapacity dot matrix LCD panel.
•
FEATURES
• Low-power high-speed CMOS technology
• Low output resistance
• 100-bit common (row) driver
• Duty cycle ............................... 1/1 00 to 1/500
• Ability to adjust offset bias of the LCD source from
• Adjustable LCD drive voltages
• Wide range of LCD voltage .... 14 to 40V
VDD
• Selectable output shift direction
• Supply voltage ........................ 4.5 to 5.5V
• Supports display blanking
• Package .................. QFP-5 128 pins (FaA)
AI pad (DOA)
• Supports high-speed data transfer
•
I
SYSTEM BLOCK DIAGRAM
00-07
XSCL
LCD
CONTR
LP, FR
YSCL
f----
YD
~
I SED1733 ~
t
I SED1733
~
SED1724
SED1724
SED1724
SED1724
~~
~~
~~
~~
320 SEG x 200 COM
DUTY: 1/200
795
SED1733
•
I
BLOCK DIAGRAM
00 01--------------------- 099
VDDH
Vee
~
------
GNO t---
---- ---------- ------------------
r--
V1
LCO driver,
100 bits
V4
L-..
Voltage
Control f-----------o.
V5 ~ Circuit
f
FR
I
Level shifter, 100 bits
H
0101
YSCL
SHL
Two-way shift register,
50 x 2 bits
i
INH
0102
796
0103
J
0104
SED1733
• PIN DESCRIPTION
Pin Name
00 to 099
0101,0102
I/O
Function
o
Q'ty
LCD crystal common (row) outputs
The output changes at the YSCL fall edge.
100
0103,0104
To input and output serial data of 50 x 2 bits two-way shift register.
Input or output is set by SHL input. Output changes at the YSCL fall edge.
YSCL
To input shift clock of serial data. Scanning data is shifted at the fall edge.
SHL
To input the selection of shift direction and input-output control of
010 terminal.
I/O
010
o (Output shift direction)
SHL
4
1,3
L
o
----------------------.. 99
H
99
----------------------..
2,4
Input Output
0
Output Input
To input blanking control of liquid crystal display.
Low level input brings all common outputs to non-section level.
INH
FR
Vee, GND
V1, V4, V5,
VDDH
To Input AC signal of liquid crystal driving output.
1
Power
Supply
Logic power supply. GND: 0 V; Vee: +5.0 V
2
Power
Power supply for liquid crystal driving
VDDH: +14 V to +40 V; VDDH ~ V1 ~ 8/9 VDDH; 1/9 VDDH
VDDH, V5: Selection level, V1, V4: Non-selection level
Supply
4
~
V4
~
V5
~
VDDH,
Total: 114 pins
•
•
FUNCTIONAL DESCRIPTION
Shift Register
•
Bidirectional data shift register.
•
The LCD drivers drive individual columns of the
display matrix with the voltage determined by the
inhibit signal /INH, the frame signal FR, and the
latched display data. This is shown in the table
below.
Level Shifter
The level shifter converts the logic-level signals
from the latch to the voltage levels required by the
LCD drivers.
/INH
Data
H
H
L
L
-
LCD Drivers and Voltage Control Circuit
FR
SEG Output Voltage
H
V5
L
VDDH
H
V1
L
V4
H
V1
L
V4
797
Selected
Deselected
Deselected
I
SED1733
•
TIMING CHART
en
Q)
c
o
o
,....
-------- ------ -- -- ------ - ----- - - - -- --t---
en
Q)
c
o
o
--------- ---- - -- r-
------1-- ---- j - - - - -
--t--- ----
en
Q)
.!:
o
o
-------- ---- - -- -- ------1-
-----j-----
--t---
r
Q)
en '
E
~
u..
g
~
en
Q)
c
~
o
o
----- ---- - --I-
'-
II:
u..
II
I~
o
a
,....
a
»
I 1»
1
C\I
a
'1 >1
1
C\I
0
SED1733
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Ratings
Unit
Supply voltage (1)
Parameter
Vee
-0.3 to +7.0
V
Supply voltage (2)
VOOH
-0.3 to +45.0
V
Supply voltage (3)
V1, V4, V5
-0.3 to VOOH +0.3
V
Input voltage
VI
-0.3 to Vee +0.3
V
Output voltage
Vo
-0.3 to Vee +0.3
V
010 output current
101
102
20
mA
20
mA
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-65 to +150
°C
LCD circuit output current
Note 1. Let the VOOH, V1, V4 and V5 voltages maintain the condition, VOOH ~ V1 ~ V4 ~ V5 ~ GNO, all the time.
VOOH
V1
40V
V4
VCC
V5
5V
GND
GND
Note 2. If the logic circuit power supply comes to float while voltage is applied to the power supply of the liquid crystal
driving circuit, the LSI may be broken permanently. So, prevent the logic circuit power supply from floating.
Pay special attention to the power supply sequence when the system is switched on or off.
799
I
SED1733
• DC Electrical Characteristics
Supply voltage (1)
(Unless otherwise specified, GNO = 0 V, Vee = +5.0 V ±10%, Ta = -20 to 75°C)
Applicable
Typ
Max
Condition
Min
Unit
Terminal
Vee
Vee
4.5
5.0
5.5
V
Recommended supply voltage
VOOH
Operable voltage
VOOH
Parameter
Symbol
VOOH
14.0
-
VOOH
B.O
-
VOOH
V
1/9VDDH
V
0101
O.BVee
to 0104
FR, YSCL, GNO
INH, SHL
-
Vee
V
-
0.2Vec
V
0101
Vcc-O.4
to 0104
GNO
-
Vee
V
-
0.4
V
Function
Supply voltage (2)
V1
Recommendation value
V1
8/9VDDH
Supply voltage (3)
V4, V5
Recommendation value
V4, V5
GNO
High level input voltage
VIH
Low level input voltage
VIL
High level output voltage
VOH
IOH =-0.3 mA
Low level output voltage
VOL
IOL = 0.3 mA
Input leak current
Input-output leak current
Static current
V
V
III
GNO $ VIN $ Vee
ILila
GNO $ VIN $ Vee
0101
to 0104
-
-
5.0
f.lA
IGNO
VOOH = 14.0 to 40.0 V
VIH = Vee, VIL = GNO
GNO
-
-
25
f.lA
*1
-
0.7
1.B
00 to
099
-
O.B
2.2
1.0
2.6
Vee
-
30
60
f.lA
VOOH
-
45
120
f.lA
-
-
B
pF
-
-
15
pF
ReaM
I'NON
=0.5V
VooH=+20.0V ]
VOOH=+ 14.0V
Current consumed (1)
Icc
Vcc = +5.0 V, VIH = Vee.
VIL = GNO, fyseL =33.6 kHz,
fFR =70 Hz; Input data: 1/480,
"H" is input every duty.
Common has no load.
Current consumed (2)
looH
Vee = +5.0 V, V4 = +4.0 V,
Vi = +26.0 V, VOOH =+30.0V
Other conditions are same
as those of IDD
Input terminal capacity
CI
I/O terminal capacity
-
FR, YSCL,
INH, SHL
VooH=+30.0V
Output resistance
40.0
CliO
Freq.=1 MHz, Ta = 25°C FR, YSCL,
INH, SHL
Solid chip
0101
to EI04
-
-
2.0
f.lA
*1 The output resistance is specified within the ranges of the supply voltages (2) and (3).
BOO
kQ
SED1733
• AC Electrical Characteristics
o Input Timing Characteristics
VIH = 0.8 x Vee
VIL = 0.2 x Vee
FR
I l.-tweLH •
tr YSCL ~IX
rr
'\
.- t
_
DFR
J'-1
-'t\,~_ _
•
~"'X"'X""X"7"CX"'X-";X""X""X~__~XZ2
tDS'-' .-. tDH
0101 - 0104
tceL
"'X"'X"'X"7"CX"""X:-7'
Parameter
Condition
Symbol
(VCC = 5 0 V -+10% Ta = -20 to 75°C)
Min
Typ
Max
Unit
Input signal rise time
tr
-
-
50
ns
Input signal rise time
tf
-
-
50
ns
tCCL
400
-
-
ns
YSCL high level pulse width
twCLH
70
-
-
ns
YSCL low level pulse width
tWCLL
330
-
ns
Data setup time
tDS
100
-
-
Data hold time
tDH
40
-
-
ns
-300
-
300
ns
YSCL cycle time
FR delay allowable time
o
~_ _-'·>ll ~tf
tweLL
tDFR
ns
I
Output Timing Characteristics
)<
FR
'"
YSCL
0101 0104
VIH= 0.8 x Vec
VIL= 0.2 x Vee
0.8 x Vec
- - tpdDOCL - - , 0H 0.2 x Vec
0=
.- tpdCCL-
INH
I..
o output
Parameter
Symbol
YSCL fall to 010 delay time
tpdDOCL
YSCL fall to 0 delay time
tpdCCL
INH to 0 output delay time
tpdCINH
FR to 0 output delay time
tpdCFR
-
tpdCFR---+
tpdCINH
x:
(VCC = +5 0 V -+10% , VDDH = +40 0 V Ta = -20 to 75°C)
Conditions
Min
Typ
Max
Unit
CL = 15 pF
CL = 100 pF
801
-
300
ns
0.7
~s
-
-
0.7
~s
-
-
0.7
~s
-
SED1733
•
PACKAGE DIMENSIONS (SED1733FoA)
&lO:>?>51(lre
!=;j~llJ~K1gjNC1il~~~~~;":~;::!~~'"
o-go--t3o~----
o
1
Ne
VDOH
Ne
~f
v,
SED1733FOA
vee
Ne
FR
GNO
i~t
"'04
OK"
.
0102
0101
Ne
~ ~~
Ne
~~
o "
~~
•
PLASTIC QFP5-128PIN-S1
Unit: inch (mm)
~
-0.929 ± 0.016 (23.6 ± 0.4)_
0.787 ± 0.004 (20.0 ± 0.1) ----~
'"
'"
f+1
'"
g
ci
ci
+1
+1
;;;
"'
fw~;;
+1
+1 +1
~ 0~ci
-
1
802
~
SED1733
• PAD LAYOUT
DDDOCOOODDDODDCDDDCCDDIJDDDDD[JClDDCl
D
D
D
D
D
D
D
D
D
D
D
D
Y
D
D
D
D
D
D
D
D
~
D
o D
D
[:l D
D
~
D
(0,0)
D
o D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Lx
120
8
g
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDIJ
1
33
6.10 mm x 5.30 mm
Chip Dimensions
Pad pitch
0.170 mm (Min.)
Chip thickness
0.400 ±O.025 mm
Aluminum pad opening
100 J.lm x 100 J.lm (all terminals)
• PAD COORDINATES
Pad
Number Name
1
092
2
093
094
3
095
4
096
5
097
6
7
098
099
8
NC
9
10
DI01
11
DI02
12
DI03
13
DI04
14
INH
15
SHL
16
YSCL
17
GND
18
FR
19
Vee
20
V1
21
V4
22
V5
23
NC
24
VOOH
25
NC
26
00
27
01
28
02
29
03
30
04
31
05
32
06
33
07
34
08
35
09
010
36
37
011
012
38
39
013
40
014
X
Y
(Ilm)
(Ilm)
-2882
-2620
-2420
-2230
-2050
-1870
-1700
-1530
-1360
-1190
-1020
-850
-680
-510
-340
-170
0
170
340
510
680
850
1020
1190
1360
1530
1700
1870
2050
2230
2420
2620
2882
2882
2882
2882
2882
2882
2882
2882
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2482
-2060
-1880
-1700
-1530
-1360
-1190
Pad
Number Name
41
015
42
016
017
43
44
018
45
019
46
020
47
GND
48
021
49
022
023
50
024
51
025
52
026
53
54
027
028
55
029
56
57
030
031
58
59
032
60
033
034
61
62
035
036
63
037
64
65
038
66
039
040
67
041
68
042
69
70
043
71
044
72
045
73
046
047
74
75
048
76
049
GND
77
78
050
79
051
052
80
X
Y
(Ilm)
(Ilm)
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2882
2620
2420
2230
2050
1870
1700
1530
1360
1190
1020
850
680
510
340
170
0
-170
-1020
-850
-680
-510
-340
-510
803
-340
-170
0
170
340
510
680
850
1020
1190
1360
1530
1700
1880
2060
2250
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
Pad
Numbe Name
81
053
054
82
83
055
84
056
85
057
058
86
87
059
88
060
89
061
062
90
91
063
92
064
93
065
94
066
067
95
96
068
97
069
98
070
071
99
100
072
101
073
074
102
103
075
104
076
105
077
106
078
107
GND
108
079
109
080
110
081
111
082
112
083
113
084
114
085
115
086
116
087
117
088
118
089
119
090
120
091
X
Y
(Ilm)
(Ilm)
-680
-850
-1020
-1190
-1360
-1530
-1700
-1870
-2050
-2230
-2420
-2620
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
-2882
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2482
2250
2060
1880
1700
1530
1360
1190
1020
850
680
510
340
170
0
-170
-340
-510
-680
-850
-1020
-1190
-1360
-1530
-1700
-1880
-2060
-2250
I
THIS PAGE INTENTIONALLY BLANK
804
SED1741
•
DESCRIPTION
The SED1741 is a 100 (50 x 2) dot matrix LCD common (row) driver for driving high-capacity LCD panels
at duty cycles higher than 11100 (up to 1/500). The LSI features a wide range of LCD drive voltages. The
device uses a daisy-chain enable system which decreases power consumption and eliminates the need for
separate enable signals for each driver.
The SED1741 is used in conjunction with the SED1742/44 (160-bit segment driver) to drive a large-capacity
dot matrix LCD panel.
•
FEATURES
• 100-bit (50 x 2) common (row) driver
• Ability to adjust offset bias of the LCD source from
Voo
• Duty cycle ..................... 11100 to 1/500
• Pin selectable output shift direction
• Adjustable LCD drive voltages
• Low output impedance ... ........ 1Kn
• Low-power high-speed CMOS technology
• Unbiased display off function
• LCD voltage....... ............ ......... 14 to 42V
• Adjustable offset bias of the LCD according to
VOOH and GND
• Supply voltage ........................ 2.7 to 5.5V
• Package .................................. Au bump (018)
TAB (TOA)
• Built-in circuit for clock stop detection
•
SYSTEM BLOCK DIAGRAM
I
00 - 03
XSCL
LCD
CONTR
LP,FR
YSCL
~
YO
'1
SE01742T
I
1
SED1742T
~6~
SED1741
1
SE01741
•
SE01741
I
~6~
tWo v)
t--
t}Q!L
v
320 SEG X 300 COM
DUTY: 1/300
~
v
805
.......•.•.• - .......
-----------
SED1741
•
I
BLOCK DIAGRAM
o 0 - -- -- - --- - -- -- --- - - 0
VO
Q-j___----.J
V5
()-j___----.J
100-bit LCD Driver
99
~---{)
V1
~---o
V4
VDDH
FR 0----------'
INH A------ 0
sec
I
SED1753
•
EXAMPLE OF REFERENCE CIRCUIT
------
XSCL
UOO-07
- - -- - - -- - - -- - - --
T
I I
I I T J~ee
SHL
EI02
GN~ EI01
III j Vee
-------
SE01752(1)
01
l
I~
l
IJ
I
l
J
SE01752(B)
240
1
0240
01
640
X 3 x 480 dots
1/240 duty
I
240
0240
1
SE01753(1)
01
0101
f----YSCL
FR
OSPOF
120
SHL
SEL
013
f-----------
0102
0120
SE01753(2)
01
0101
f----YSCL
FR
OSPOF
120
SHL
SEL
013
r------
0102
0120
- - --
'--
SHL
EI02
c1iEJ)_E~~"JL EI01
---------------- -----------------------------
SE01753(3)
01
0101
f----YSCL
FR
OSPOF
120
SHL
SEL
013
-
0120
[
DI",
l
£
SE01753(4) 0
0101
~
YSCL
FR
OSPOF
120
SHL
SEL
013
0102
0120
01
oj
GNO
LP
FR
OSPOF
LOO-07
XSCL
I
240
1
01
0240
I
240
1
0240
SE01752(1)
SE01752(B)
SE01752 xB
EI01 r---- -------- EI02
EI01
EI02
---- GN~ SHL
SHL
::::::::::_:~ II
1 I I
11
- - - --
846
SED1753
•
Example of LCD Power Supply Circuits
• The LCD drive power supply (Va - V5) requires
the addition of smoothing capacitors on the
appropriate places in the LCD module.
Va
VDDH
• Va, V" V4andV5aresuppliedto SED1753, and
Va, V2, V3 and V5 are supplied to SED1752.
• The logic power supply Vee is supplied to all
ICs.
R
GND
•
o
• It is necessary to add bypass capacitors to the
appropriate locations between GND - Vee and
GND - VDDH to eliminate noise, thereby stabilizing the power supply voltage. It is recommended that the power supplies for high-voltage application (GNDR, GNDL) use a different
system than the lines forthe power supplies for
logic (GND).
V5
TCP
An SED1753T** TCP Pinout Example
VODHL
01
VOL
02
V1L
03
V4L
04
V5L
GNO
0101
FR
OSPOF
SHL
SEL
013
YSCL
0102
Vee
VSR
V4R
0117
ViR
0118
VOR
0119
VDDHR
0120
Note: The external dimensions of the TCP are not specified.
847
I
SED1753
•
External Dimension Diagram
IOutput Terminal Part Pattern Shape
I
,_o.lH:~"_"_1
IL)~---'c-----;!'---'~-----L
_I
i---
MAXO.15 - - - '
L--..
MIN 0.04
(0.019) - _ ,
Note lProducl Pitch; 31p (14.25 mm)
Note 2Resist location tolerance: ± 0.3
~I
-I
1
I
I
:
I
I
L---EJ
I
J
848
SED1755DoA
CMOS LCD COMMON DRIVER
•
DESCRIPTION
The SED1755 is an LCD common (row) driver designed for extremely high-capacity dot matrix liquid crystal
panels. It incorporates 240 high-voltage, low-impedance common drivers in a 2 x 120 format, enabling high
driver effectiveness with displays of 1/240, 1/300 and 1/480 duty cycles. It is designed for use in conjunction
with the SED1756 segment (column) driver.
The SED1755 features a wide range of liquid crystal drive voltages, an LCD display of high quality and chip
layout long from side to side to minimize the LCD panel. It offers a wide range of applications.
•
FEATURES
• 240 (120 x 2) LCD common drive outputs
• Adjustable LCD drive voltage
• 0.3KQ (typ.) low output impedance
• Liquid crystal drive in wide range of voltage
8 to 42V
• High-duty drive available ........ 1/480
• 2.7 to 5.5V supply
• Package: .... DOA .... AI pad die for chip on glass
• Pin-selectable output shift direction
• Zero-bias display disable function
• Chip configuration long from side to side
•
SYSTEM BLOCK DIAGRAM
I
DO-D7
XSCL
LCD
CONTR
LP,FR
I YSCL
~
SED1756
...
~4~
~~
SED1753
~
~
SED1753
640x3x480
~
849
SED1756
SED1755DoA
•
BLOCK DIAGRAM
0240
01
VOOHL
VOOHR
VOL
VOR
V1L
240 bit
LCD Driver
V4L
V5L
GNDR
240 bit
Level Shifter
GND
Vee
n-------------~
DI02
YSCL
V4R
V5R
GNDL
FR
V1R
240 bit
Bidirectional Shift Register
DI01
)-------
SHL
DSPOF
TEST
DI3 SEL
850
SED1755DoA
•
•
FUNCTIONAL DESCRIPTION
Shift Register
The shift register is a bidirectional shift register. SEL is used to select the operating mode (120 x 20-bit or 240bit) of the shift register. The input of the lower 120-bit will be the 013 when the 120 x 20-bit is selected.
The effect of SHL on the shift direction and on the input data sequence is shown in the following table.
•
0101
Output Shift Direction
SHL
H
240
L
1
-----.
-----.
121
120
120
121
-----.
-----.
1
240
0102
Output
Input
Input
Output
Level Shifter
The level shifter converts the logic-level signals from the latch into the LCD driver input voltage levels.
•
LCD Drivers
It outputs the LCD driving voltage. Given below are the relations between data bus signals, alternating current
signal FR levels and segment output voltages.
IDSPOF
Data
H
H
L
L
-
FR
Output Voltage
H
V5
L
VO
H
V1
L
V4
-
V5
Selected
Deselected
-
I
851
SED1755DoA
•
TIMING CHART
SHL="L"
1/480 Duty
,
:..
0101
(013)
YSCL
FR
1 Frame
JT1
(480I"OS) _____
____ ~
~------~------Jlrul
l'
,
1 - - - .
-
DSPOF
JTl
.:
-
-
-
-
-
--J'-----I
'-----If-----.
L
-
-
.
'
,
,
-
~-----~-----~
Shift
Register 01:
n
,n
_____ ~<------'
~---------LJL-----~
0102
:.. *
,
02
L ._ _ _ _
n
~,----------------~
L-____~------__
,
,
~;
·n~:.~_~
!
,
,
1IJ-----I (f:----}
,
,
03
___
.nl....................... .... r•
: ...n.
~:+ ....... n.. n~:::: .. ni ..l i n n..
~: ...
01
240Iines--R:
,
,
: (* SEL=H, 013 Input 120 lines) :
,
,
,
,
~; I
,
,
n
,
,
ttn---- -ljC ------J nnn
852
SED1755DoA
•
PIN DESCRIPTION
Pin Name
01 to
0240
0101
0102
I/O
0
I/O
013
I
SEL
I
YSCL
I
SHL
DSPOF
I
I
FR
GND, Vee
VOL, VIL, V4L,
VSL, VOOHL, V4L,
VOR, V1R, V4R,
VSR, VOOHR,
GNDL, GNDR
TEST
I
Power
supply
Power
supply
I
Description
Common (low) output for LCD drive
Changes at the falling edge of YSCL
120x2bit bidirectional shift register scan pulse.
Set at the input or output by SHL input.
The output changes at the falling edge of YSCL
The input of scan pulsre whrn 120x20 mode.
013 is tied to GND when SEL is LOW.
Cidirectional shift register operation mode
Selection input
H: 120x2 (013 input L: 240
Serial data shift clock input.
Shifts the scan data at the falling edge.
Shift durection selection, and 010 terminal I/O control output
The blankimg control input for the display of LCD.
All common outputs are made to ?V5 level by "L" input
For input of alternating current LCD drive signals.
Logic operation power supply: GND: OV,
Vee: 2.7 to 5.5V
LCD drive curcuit power supply
GND: OV, VOOH: 8V4 to 42V
VOOH ~ VO ~ V1 ~ 8/9V
1/9VoOH ~ V4 ~ V5 ~ GND
Non connect
Numbers of Pins
240
2
1
1
1
1
1
2
12
1
I
853
SED1755DoA
•
PAD DIMENSION
~
o
0
~1""""""!""""'9iIN .... ,i""""~lil,iNil'I'lil,','r'RiSi'iIIIIIII','JIiIiIjl'~
263
24
+
000000
o
0000000
o
o
DO
23
0
0
0
0
0
"""~
QcQ
c
c
Chip Size:
17.04mm x 2.50mm
Chip Thickness ~OOl1m (Typ.)
-------------1--- --!
CHIP EDGE
i
-]:}_T
[JODT
ODTEJwi
I--- 15511m
I
I
I
--.:
70l1m
I
I
~15511m
•
I
---I
I
I
[J [li
i--
200l1m _ _: (Min.) 16811m -j189111m
I
I
----------------------CHIP EDGE
(X, Y) 90 x 90 11m
854
SED1755DoA
•
PAD COORDINATES
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Pad Name
VDDHL
VOL
V2L
V3L
V5L
GNOL
TEST
SHL
OSPOF
FR
LP
YSCL
GNO
0102
013
0101
Vee
GNOR
V4R
V5R
V1R
VOR
VDDHA
X
-8295
-7895
-7495
-7095
-6695
-6295
-5095
-4895
-4495
-4095
-3895
-3695
-3095
-1895
-1495
-1295
3295
6295
6695
7095
7495
7895
8295
X of On
YofOn
Y
-1059
-1059
-1059
-1059
-1059
-1059
-1082
-1082
-1082
-1082
-1082
-1082
-1082
-1082
-1082
-1082
-1082
-1059
-1059
-1059
-1059
-1059
-1059
Pad No.
24
25
26
27
28
29
30
31
Pad Name
01
02
03
04
05
06
07
08
X
8365
8295
8225
8155
8085
8015
7945
7875
Y
923
1093
923
1093
923
1093
923
1093
256
257
258
259
260
261
262
263
0233
0234
0235
0236
0237
0238
0239
0240
-7875
-7945
-8015
-8085
-8155
-8225
-8295
-8365
923
1093
923
1093
923
1093
923
1093
8435- (70 x n) 11m
h = odd
923 11m
n = even : 109311m
855
I
SED1755DoA
•
•
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameters
Codes
Ratings
Units
Vee
VOOH
Vo, V1, V4, Vs
VI
Vo
10
-0.3 to +7.0
20
V
V
V
V
V
rnA
Working temperature
Topr
-40 to +85
°C
Storage temperature
Tstg 1
-65 to +150
°C
Supply voltage (1)
Supply voltage (2)
Supply voltage (3)
Input voltage
Output voltage
EIO output current
(Note 1): All the voltage ratings are based on GND =
-0.3 to +45.0
GND -0.3 to VOOH + 0.3
GND -0.3 to Vee + 0.3
GND -0.3 to Vee + 0.3
av.
(Note 2): The storage temperature 1 is applicable to independent chips and the storage temperature 2 is applicable to the TCP
modular state.
(Note 3): Vo, V2, V3, and Vs should always be in the order of VDDH ~ Vo ~ V2 ~ V3 ~ Vs ~ GND.
VDDH
VO
V1
42V
V4
V5
Vee
5V
GND
GND
(Note 4): If the logic operation power goes into a floating state or if Vee drops to 2.6V or below while the LCD driving power is
being applied, the LSI may be damaged. Therefore, keep from occurrence of the aforementioned status.
Specifically, pay close attention to the power supply sequence at times of turning the system power on and off.
856
SED1755DoA
•
DC Characteristics
Parameter
Unless otherwise specified, GND = Vs = OV, Vee = +5.0V
Symbol
Applicable
Pin
Condition
Min
± 10%, Ta = -40 to +85°C
Typ
5.5
V
40.0
V
8.0
-
42.0
V
8/9 Va
VDDH
V
GND
-
1/9 VDDH
V
0.8 Vee
-
Vee
2.7
VOOH
Vee = 2.7 TO 5.5V
Val, VDDHl
14.0
Workable voltage
VDDH
Function only
VOR, VDDHl
Supply voltage (2)
V,
Recommended value
V1L, V1R
Supply voltage (3)
V.
V,H
Recommended value
V,", V.R
High level input voltage
Vee= 2.7-5.5V
Low level input voltage
V,l
D101, D102, FR
YSCL, SHL,
SEL, DI3
DSPOF
-
-
High level output voltage
VOH
D101, DI02
Vec-OA
Low level output voltage
Val
Input leak current
Vee
III
Vee =
2.75.5V
I
10H =-O.3mA
I
IOl=0.3mA
GND ~ VIN~ Vee
-
V
-
V
1 YSCL, SHL,
D13, FR, SEL
DSPOF
-
-
2.0
!JlA
-
-
5.0
25
IlA
IlA
Kn
GND~VIN~Vee
D101, DI02
GND
Output resistance
ReaM
!NON
Va = +36.0V, 01=0.5V
1/24
0240
Recom- Va = +26.0V,
mended 1/20
condition
ilVON = 0.5V
V = +36.0V, 1/24
Mean working current
consumption (1)
ilReoM
Icc
Va = +30.0V = VDDH
Vee = +5.0V, V1 = 28.0V
V. = +2.0V, V5 = +O.OV
Other conditions are
the same as those in the
IDD column
Input terminal capacity
CI
I/O terminal capacity
C,iO
Freq. = 1 Mhz
Ta = 25°C
Independent
chips
0.35
0048
-
0.37
0.5
n
0.15
30
IlA
9
20
-
0.3
0.9
-
8
20
IlA
SHL,FR
YSCL,SEL, DSPOF
-
-
8
pF
D101, DI02
-
-
15
pF
Vee
Vee = +3.0V
Other conditons are the
same as those when
Vee + 5V.
IDDH
-
95
Vee = +5.0V, V,H = Vee
V,l = GND, f SCL = 5.38MHz
1/480, fFR = 70Hz
input data: Checkered
indication, no-load
Mean working current
consumption (2)
V
-
Va = 14.0 - 42.0V
V,H = V,l = GND
In-chip deviation of output
resistance
0.2 Vee
V
-
IGND
ILiIO
-
-
Rest cu rrent
I/O leak current
Unit
-
-
Recommended working
voltage
Supply voltage (1)
Max
VDDHL, VDDHA
857
-
-
I
SED1755DoA
•
Working Voltage Range Vee - VOOH
The VDOH voltage should be set up within the Vee - VDOH working voltage range given below.
VDDH
(V)
50
42
40
30
28
20
10
o
2.0
2.7
3.0
5.0
4.0
Vee
858
(V)
6.0
SED1755DoA
•
AC Characteristics
o
Input Timing
V1H =0.8 x Vcc
V1L =0.2 x Vcc
FR
t,-
*"~ F"',1
YSCL
- - - tWCLL - - - -
7/
"'-k-
..
tDSr--
I
DI01
~
DI02
-
I
t DFR . .
I',
tCCL------
I
r~=t<
>C
X
(VCC = 5.0V
Parameter
YSCLcycie
Symbol
Conditions
Min.
tCCl
-
400
YSCL high level pulse duration
tWClH
55
YSCL low level pulse duration
tWCll
330
Data setup time
los
50
Data hold time
tOH
40
Input signal rise time
lr
Input signal fall time
tr
(VCC
Parameter
Symbol
Conditions
Min.
!eCl
-
800
YSCL high level pulse duration
twClH
Vcc=2.7V
100
Vcc=3.0V
80
-
tWCll
Data setup time
tos
Data hold time
tOH
Input signal rise time
te
Input signal fall time
tr
Note:
tDFR: The changing point and the timing of LP falling are basically 0 ns.
859
± 10%, Ta = -40 tD 85°C)
Max.
Units
-
ns
-
ns
50
ns
50
ns
ns
ns
ns
= 2.7 to 4.5V, Ta =-40 to 85°C)
YSCL cycle
YSCL low level pulse duration
+tj
660
90
70
-
Max.
-
Units
ns
ns
ns
ns
ns
50
ns
50
ns
I
SED1755DoA
•
o
AC Characteristics
Output Timing
V1H ~ 0,8 x Vee
~:
FR
YSCL
V1L ~ 0,8 x Vee
""
+---- tpdDOCL-=:1
0101
VOH = 0,8 x Vee
0102
VOL ~ 0,8 x Vee
l-tpdCCL -
OSPOF
1
On
I..
~tdCFR-
~____________
P
________________________t~p_dD_O_F_F
(COM)
-
(Vee
Parameter
= 5,OV ± 10%, VOOH = 14,0 to 42,OV, Ta =-40 to 85°C)
Symbol
Conditions
YSCL~
010 output delay time
tpdOOCL
CL = 15 pf
YSCL~
On output delay time
tpdCCL
CL = 100 pf
10SPOF ---t On output delay time
FR
---t
On output delay time
tpdCOOFF
tpdCFR
-
Symbol
Conditions
010 output delay time
tpdOOCL
CL = 15 pf
YSCL~
On output delay time
tpdCCL
CL = 100 pf
10SPOF
---t
FR
---t
On output delay time
tpdCOOFF
tpdCFR
860
Max,
Units
100
ns
200
ns
500
ns
350
ns
= 2,7 to 4,5V, VODH = 14,0 to 28,OV, Ta =-40 to 85°C)
YSCL~
On output delay time
Min,
-
(Vee
Parameter
Vn-O.5
- - - - - - - - - - - - - vn+O,5
Min.
-
Max,
Units
200
ns
400
ns
750
ns
600
ns
SED1755DoA
•
CONNECTION EXAMPLE (FOR REFERENCE)
- -- - - -- - - - ------------ - - ---
XSCL
DO-D7
II
SHL
EI02
GN~ EI01
ht~ee
SED1756 x 8
DIO
YSCL
-
~
l
J
SED1755(1)
DI02
YSCL
FR
DSPOF
SHL
SEL
DI3
DI01
I
240
~-
t
J
SED1755(1)
DI02
YSCL
FR
DSPOF
SHL
SEL
DI3
DI01
~
Vee
SED1756(8)
10240
01
I
240
10240
0240
~
640
240
X
3 x 480 dots
1/240 duty
~
01
--------- ----
-
SHL
EI02
EI01
--------
SED1756(1)
01
I I I
- - - -- --
- -- ---
- -
-- - - - --
- - -
- - - --
-
- -- --
- - - -
-- --
0240
~
240
~
01
01
I
240
10240
SED1756(1)
EI01
DJ EI02
GND
SHL
SED1756
----
1
-------
Vo
VDDH
V1
V2
R
V3
V4
GND __L -_ _ _ _ _ _ _ _ _ _ _ _ _ _- .
X
8
GN~
I
240
Vs
861
10240
SED1756(8)
EI02
EI01
SHL
::::::::::::-:~ II
1 I I
LP
FR
DSPOF
DO-D7
XSCL
01
I
SED1755DoA
•
•
LCD DRIVING POWER SUPPLY
Setting Up Respective Voltage Levels
When setting up respective voltage levels for LCD drive, it is the best way to resistively divide the potential
between Vo - GND to drive the LCD by means of voltage follower using an operation amplifier.
In consideration of the case of using an operation amplifier, the LCD driving minimum potential level V5 and
GND are separated and independent terminals are used.
However, since the efficacy of the LCD driving output driver deteriorates when the potential of V5 goes up
beyond the GND potential to enlarge the potential difference, always keep the potential difference of V5 - Vss
at OV to 2.5V.
When a resistance exists in series in the power supply line of Vo (GND), 10 at signal changes causes voltage
drop at Vo (GND) of the supply terminals of the LSI disabling it to maintain the relations of the LCD with
intermediate potentials of (VOOH ~ Vo ~ V2 ~ V3 ~ V5 ~ GND), thus leading to breakdown or destruction of the
LSI.
When using a protective resistor, do not fail to stabilize the voltage using an appropriate capacitance.
•
Precautions When Turning the Power On and Off
Since the LCD drive voltage of these LSls is comparatively high, if a high voltage of 30V or more is applied
to the LCD drive circuit with the logic operation power made floating or with the Vee lowered to 2.6V or less,
or when LCD drive signals are output before applied voltage to the LCD drive circuits is stabilized, excess
current flows through to possibly lead to breakdown or to destroy the LSI.
It is therefore suggested to maintain the potential of the LCD drive output to V51evel until the LCD drive circuit
voltage is stabilized, using the display off (DSPOF).
Maintain the following sequences when turning the power on and off:
When turning the power on:
Turn on the logic operation power --7 turn on the LCD drive power or turn them on simultaneously
When turning the power off:
Turn off the LCD drive power --7 turn off the logic operation power or turn them off simultaneously
For protection against excess current, insert a quick melting fuse in series in the LCD drive power line. When
using a protective resistor, select the optimum resistance value depending on the capacitance of the LCD
cells.
862
VII. DCIDC CONVERTERS
1996
DATABOOK
GRAPHICS
PRODUCTS
863
THIS PAGE INTENTIONALLY BLANK
864
•
DCfDC CONVERTERS
Part Number
SCI7660
SCI7661
SCI7654
CMOS DCfDC Converter
DCfDC Converter with voltage
regulator and temperature
compensation
DCfDC Converter with voltage
regulator and temperature
compensation
Discontinued?
No
No
No
Replacement
-
-
-
Maximum output voltage
-20V
-20V
-22V
Maximum output current
30 mA
20 mA
80fN mA
Part Name
Voltage doubler
yes
yes
yes
Voltage tripler
no
yes
yes
Voltage quadrupler
Input Voltage
Number of Output Voltage Levels
Conversion Efficiency
Package
no
no
yes
-1.2 to -8.0V
-1.2 to -6.0V
-2.0 to -11.0V
2
4
4
95%
95%
95%
01 P-8pin(COA)
SOP4-8pin(MOA)
DIP-14pin(COA)
SOP5-14pin(MOA)
SSOP2-16pin(MAA)
SSOP2-16pin (MOA)
AI pad Die (DOA)
867
873
879
CXl
~
Page number
-
THIS PAGE INTENTIONALLY BLANK
SCI7660C/MSeries
CMOS DC/DC CONVERTER
•
DESCRIPTION
The SC17660C/M CMOS DC/DC Converter features high operational performance with low power dissipation.
The booster generates a doubled output voltage from the input.
It is possible to drive an LSI that needs another power supply other than the main power supply (LCD drivers,
Analog LSI, etc.). Its very low power requirement makes it ideal to supply handy equipments with power.
•
•
FEATURES
• High performance with low power dissipation
• Simple conversion of Voo(+5V) to -VI(-5V), +2VI (+10V)
• Output current ................................................................................
• Power conversion efficiency ...........................................................
• Cascade connection (two device connected Voo=5V, Vo=-10V)
• Low power .............................................. .......................................
• On-chip CR oscillator
• Package .........................................................................................
BLOCK DIAGRAM
R
Ideal for dry cell battery
SCI7660COA ..... DIP-8pin (plastic)
SCI7660MoA ..... SOP4-8pin (plastic)
SCI7660DoA ..... DIE
•
+
VI
CR Oscillator!
I
PIN CONFIGURATION
NCO I
CAP1+ CAP1-
OSC1
OSC2
30mA Max (Voo=5V)
95% Typ
1
~ Voltage Converter I
l Vo
867
OSC2
2
7
Vo
OSC1
3
6
CAP-
Voo
4
5
CAP+
SCI7660C/M
•
•
PIN DESCRIPTION
Function
Pin Name
Pin No.
OSC1
3
OSC2
2
Voo
4
Power supply terminal (positive, system supply Vcc)
CAP1+
5
Terminal for connection of capacitor for booster (positive)
CAP1-
6
Terminal for connection of capacitor for booster (negative)
Vo
7
Output terminal at doubling
VI
8
Power supply terminal (negative, system supply GND)
Oscillation resistor connection terminal
VOLTAGE RELATIONS
VCC
1st side
~~~)
VDD
------
(-5V) ------
•
VI
= ov
----,;-------.1-
= -5V _ _-,-l
Vo
=2VI =-10V
2nd side
----'--
ABSOLUTE MAXIMUM RATINGS
Parameter
(Voo=OV, Ta=25°C)
Symbol
Ratings
Unit
V
Input voltage
VI
-10.0 to 0.5
Output voltage
Vo
-20.0 to VI
V
Power dissipation
Po
300
mW
Operating temperature
Topr
-30 to 85
°C
Storage temperature
Tstg
-65 to 150
°C
Soldering temperature and time
Tsol
260°C, 10s (atlead)
-
Note: When this IC is soldered in the solder-reflow process, be sure to maintain the reflow furnace temperature
at the curve shown in "Figure 3-5 Reflow Furnace Temperature Curve" of DATA BOOK. And this IC cannot
be exposetl to high temperature of the solder dipping.
•
(Voo=OV, Ta=-30° to 85°C)
ELECTRICAL CHARACTERISTICS
Parameter
Input voltage
Symbol
Conditions
Output voltage
Vo
Booster current consumption
lopr
Min
-8.0
VI
-16.0
Typ
-
Max
Unit
-1.2
V
-
V
70
~
~
Q
Stationary current
IQ
RL=OO, VI=-8V
-
-
2.0
Output impedance
Ro
10=10mA, VI=-5V
-
80
120
Booster power conversion efficiency
RL=OO, Rosc=1 MQ, VI=-5V
40
Pelf
10=5mA, VI=-5V
90
95
-
Input leakage current
III
OSC1 terminal, VI=-8V
-
-
2.0
Oscillation frequency
fosc
Rosc=1MQ, V1=-5V
16
20
24
868
%
~
kHz
SCI7660CIM
•
CIRCUIT DESCRIPTION
• C-R Oscillator
The SCI7660C/M contains a G-R oscillator for internal oscillation. It consists of an external resistor Rose
connected between the OSC1 pin and OSC2 pin.
OSC1 . - - -~
OSC1
Rose
OSC2
External clock
OSC2
C·R Oscillation
Open
External Clock Operation
• Voltage Converters
The voltage converters double the input supply voltage (VI) using clocks generated by the CoR oscillator. A
doubled voltage can be obtained with a booster capacitor between CAP+ and CAP-, and with an external
smoothing capacitor between VI and Yo.
10~F
5V
8
1MQ
C2
2
7
3
6
4
5
+
+
10~F
Vo=-10V
(2V\)
I
Vee
I
VDD = OV -------.,----.,(+SV) - : I
I
I
GND ---:- VI = -SV - - - ,
I
(-SV)
--+I
Vo
=2V\ =-10V
:
I
I
----'--,-
Typical doubled voltage relations
869
.---.--.-.. ----.---... -.. . ". . ====
-~
I
SCI7660CIM
• Negative Voltage Conversion + Positive Voltage Conversion (This circuit produces outputs of -1 OV
and +3.8V from the -5V input by combination of voltage doubler circuit and positive voltage conversion
circuit.)
voo=ov
-,--'----V02 = 3.BV
Voo = OV
VI
=-5V
--..------f--.----'------'--------'--------r-
--Vo1=-10V
V02 = 3.BV
870
SCI7660CIM
•
PACKAGE DIMENSIONS
Plastic DIP-8pin
0.382Max
(9.7Max)
0.358 ± 0.004
(9.1 ±0.1)
cr-
Index
0.300
(7.62)
•
0.0102:8:8&14
(0.25 ::. 8:8~)
0.100 ±0.010
(2.54 ± 0.25)
unit: inch (mm)
Plastic SOP4-8pin
,-t-I----
0.197 ± 0.008
1"8 (5.0±0.2) r5
I
Index
04
i~jrrt--_~
EEFi co~
(')~
coco
o
·
ci~
0.050 0.014+0.004 8!;!?
(1.27) (0.35 0.1) 0
±
e.
0.022
(0.55)
unit: inch (mm)
871
THIS PAGE INTENTIONALLV BLANK
872
SCI7661 C/Mseries
CMOS DC/DC CONVERTER
•
DESCRIPTION
The SCI7661 C/M CMOS DC/DC Converter features high operational performance with low power dissipation.
It consists of two major parts: the booster circuitry and the regulator circuitry. The booster generates a doubled
output voltage (-2.4V to -12V) or tripled output voltage (-3.6V to -18V) from the input (-1.2V to -6V). The
regulator is capable of setting the output to any desired voltage. The regulated voltage can be given one of three
threshold temperature gradients.
•
FEATURES
•
•
•
•
•
•
•
•
•
•
High performance with low power dissipation
Simple conversion of VIN (-5V) to IVINI (+5V), 2 IVINI (+ 10V), 2 VIN (-10V) or 3 VIN (-15V)
On-chip output voltage regulator
Power conversion efficiency .......................................................... Typ 95%
Temperature gradient for LCD power supply ................................ 0.1 %/oC, O.4%/oC or 0.6%/oC
Power off by external signals - Stationary current at power off ... Max 21lA
Cascade connection - two devices connected ............................. VIN=-5V, VOUT=-20V
On-chip C-R oscillator
Package ......................................................................................... SCI7661CoA .. DIP-14pin (plastic)
SCI7661 MOA .. SOP5-14pin (plastic)
BLOCK DIAGRAM
•
ascI
aSC2
PIN CONFIGURATION
CAP1+
VDD
CAP1-
ascI
CAP2+
OSC2
TCI
TC2
CAP1CAP1+
CAP2-
Poff
CAP2+
v reg
CAP2-
Poff
TCI
RV
TC2
V reg
VIN
VOUT
RV
VOUT
,
,
~ Booster ---.::+.---Regulator - - -.,
:
'
873
The same pin configuration in DIP and SOP
I
SCI7661C/M
•
PIN DESCRIPTION
I
I
Pin Name
I
Function
Pin No.
CAP1+, CAP1-
1,2
Terminal for connection of capacitor for doubler
CAP2+, CAP2-
3,4
Terminal for connection of capacitor for tripler
TC1, TC2
5,6
Temperature gradient selection terminal
VIN
7
Power supply terminal (negative, system supply GND)
VOUT
8
Output terminal at tripling
Vreg
9
Regulated voltage output terminal
RV
10
Regulated voltage control terminal
Vreg output ON/OFF control terminal
Poff
11
OSC2,OSC1
12, 13
VDD
14
Oscillation resistor connection terminal
Power supply terminal (positive system supply Vcc)
(VDD=OV)
• ABSOLUTE MAXIMUM RATINGS
Parameter
Input supply voltage
Input terminal voltage
Symbol
Ratings
VI
-20/N*' to 0.5
VI
Unit
V
VIN-0.5 to 0.5
*2
V
VouT-0.5 to 0.5
*3
V
Output voltage
Vo
min. -20.0
V
Allowable loss
Pd
300
mW
Operating temperature
Topr
-30 to 85
Storage temperature
Tstg
-55 to 150
Soldering temperature and time
Tsol
260°C, 10s (at lead)
*1 N=2: Doubler;
N=3: Tripier
*2 OSC1, Poff
*3 TC1, TC2, RV
*4
°C
°C
*4 Plastic package
Additional Note: When this IC is soldered in the solder-reflow process, be sure to maintain the reflow furnace
temperature at the curve shown in "Figure 3-5 Reflow Furnace Temperature Curve" of DATA BOOK. And
this IC cannot be exposed to high temperature of the solder dipping.
874
SCI7661C/M
•
ELECTRICAL CHARACTERISTICS
Parameter
Input supply voltage
Output voltage
(VDD=OV, VIN=-5V, Ta=-30° to 85°C)
Symbol
Conditions
VI
Vo
Vreg
Min
Typ
-6.0
Max
Unit
-1.2
V
-18.0
RL=OO, RRv=1MQ, Vo=-18V
V
-18.0
-2.6
V
-18.0
-3.2
V
Regulator operating voltage
VOUT
Booster current consumption
lopr1
RL=OO, Rosc=1 MQ
60
100
IlA
Regulator current consumption
lopr2
RL=OO, RRv=1MQ, Vo=-15V
5.0
12.0
IlA
10
TC2=TC1 =VOUT, RL=OO
Oscillation frequency
fosc
Rosc=1MQ
Output impedance
ROUT
louT=10mA
Stationary current
Booster power conversion efficienc
Regulated output voltage fluctuatior
Peff
louT=5mA
tNreg
-18V 4: 80/N
mA
N = step-up voltage multiplier VOUT. VREG terminal
Input current
Output current
210
mW
Operating temperature
TOPR
-30
85
°C
Storage temperature
TSTG
-55
150
°C
Soldering temperature/time
TsoL
260 X 10
°CoS
Allowable loss
Pd
At the leads
Note 1: Operating the chip under conditions exceeding the absolute rated values above may result in misoperation and
permanent damage to the chip. Moreover, the reliability of the chip will be seriously compromised even if the chip
appears to function normally for a time.
Note 2: Relationships of voltage levels with the external system
The common power supply for the SCI7654 is the highest voltage level (Voo). Because of this, the values
in this specification are all expressed in terms of a Voo =0 V reference, and consequently caution is required
regarding voltage levels when connecting to the external system.
882
SCI7654
•
Relationship of Voltage Levels
System Side
SCI7654 Side
Vee
(+5V)
VDD
(OV)
5V
GND
(OV)
:
VIN
(-5V)
10V
- - -
-------
-------
2 x Step-up
-10V
15V
- - - - --------
-15V
3 x Step-up
20V
- - - -
4 x Step-up
-20V
I
883
SCI7654
•
ELECTRICAL CHARACTERISTICS
•
DC Characteristics
Parameter
If not otherwise indicated, Ta = -30°C to +85°C, Voo = OV, Y,N = -5.0V
Symbol
Max
Unit
Input power supply voltage 1
VIN1
For 4X step-up voltage
Conditions
-5.5
Min
Typ
-2.0
V
Input power supply voltage 2
For 3X step-up voltage
-7.3
-2.0
V
Input power supply voltage 3
Y,N'
V,N3
For 2X step-up voltage
-11
-2.0
V
Input power supply voltage N
V,NN
When used with high multiplier step-up
-22/N
voltages using an external diode. "N" is the
step-up multiplier.
-2.0
V
Step-up initial input power
supply voltage
VSTA
"N" is the step-up multiplier,
louT<200 IlA FC = Voo
-22/N
-2.4
V
Step-up output voltage
VOUT
-22
Regulator input voltage
VRI
-22
V
-2.0
V
-2.0
V
250
Q
Regulator output voltage
VREG
REG = 0, VRI =-22V, RRV = 1MQ
Step-up output impedance
ROUT
louT = 10 mA, for 4X step-up voltage
180
Pen
10uT= 2 mA
For 4X step-up voltage
C1, C2, C3, COUT = 10 IlF (tantalum)
95
Step-up converter operating
consumption current 1
IOPR1
FC = Voo, Pam = Y,N,
POFF2 = Voo with no load
C1, C2, C3, COUT = 10 IlF (tantalum)
150
220
j.lA
Step-up converter operating
consumption current 2
IOPR2
FC = Y,N, Pam = Y,N,
POFF' = Voo with no load
C1, C2, C3, COUT = 10 IlF (tantalum)
600
800
IlA
Regulator operating consumption
current
IOPVR
10
15
IlA
5.0
j.lA
0.5
IlA
Step-up output conversion efficiency
Idle current
10
VRI ~20V, with no load
RRv= 1MQ
POFF1
FC
Input leakage current
ILiN
=
VIN, POFF2
=
VIN
%
=Voo
Applicable terminals:
Pam, POFF2, FC TC1, TC2
Regulated output saturation
resistance
RSAT
(Note 1)
0O--------..:========::j::c::)x:{>-t>--? 0017
902
SED2020FOAlOB
•
•
PINOUT
SED2020FoA
41
29
28
42
46
24
23
SED2020FoA
19
5
18
6
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
Pin
Name
812
CK2
LH2
VOOL
V88
VOOH
NC
0011
0012
0013
0014
0015
Number
13
14
15
16
17
18
19
20
21
22
23
24
Pin
Name
0016
0017
0018
0019
0020
NC
NC
NC
802
NC
NC
NC
Number
25
26
27
28
29
30
31
32
33
34
35
36
903
Pin
Name
NC
801
NC
NC
NC
0010
009
008
007
006
005
004
Number
37
38
39
40
41
42
43
44
45
46
Name
003
002
001
NC
NC
BK2
BK1
LH1
CK1
811
I
SED2020FOAlOB
•
SED2020FoB
23
3.3
34
22
SED2020FoB
44
12
11
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
Pin
Name
VOOH
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
Number
12
13
14
15
16
17
18
19
20
21
22
Pin
Name
NC
NC
NC
802
NC
NC
NC
NC
801
NC
NC
Number
23
24
25
26
27
28
29
30
31
32
33
904
Pin
Name
0010
009
008
007
006
005
004
003
002
001
NC
Number
34
35
36
37
38
39
40
41
42
43
44
Name
BK2
BK1
NC
LH1
CK1
811
812
CK2
LH2
VOOL
V88
SED2020FOAlOB
•
PIN DESCRIPTION
Number
SED2020FoA
SED2020FoB
Description
Name
1
40
SI2
2
41
CK2
Serial data input clock 2
3
42
LH2
Active-HIGH data latch input 2
4
43
VDDL
5
44
VSS
6
1
VDDH
7
36
NC
8 to 17
2 to 11
D011 to D020
18 to 20
12 to 14
NC
21
15
S02
22 to 25
16 to 19
NC
26
20
S01
Serial data input 2
5V logic supply input
Ground
30 to 70V output driver supply input. Referenced to Vss
No connection
Parallel data outputs
No connection
Serial data output 2
No connection
Serial data output 2
27 to 29
21,22
NC
30 to 39
23 to 32
D010 to D01
40,41
33
NC
No connection
42
34
BK2
Active-HIGH blanking input 2. Used to disable output
circuitry while parallel data is being latched.
43
35
BK1
Active-HIGH blanking input 1. Used to disable output
circuitry while parallel data is being latched.
44
37
LH1
Active-HIGH data latch input 1
45
38
CK1
Serial data input clock 1
46
39
SI1
Serial data input 1
No connection
Parallel data outputs
I
905
THIS PAGE INTENTIONALLY BLANK
906
SED2032FoB
CMOS VFD DRIVER
•
DESCRIPTION
The SED2032FoB is a CMOS LSI dot-matrix vacuum fluorescent display anode or grid driver. It has 32
high-voltage outputs in 2 x 16 blocks.
The SED2032FoB is TTL, LSTTL, CMOS and HSCMOS compatible, allowing direct interface to a wide
range of standard devices. It has independent serial inputs and outputs for each 16-element block
which feature data transfer rates of up to 4 Mbits/s. All inputs have internal pull-ups and serial outputs
have a minimum fanout of one standard TTL load.
The serial data transfer system simplifies controller requirements. The SED2032FoB can also be
configured for 4-bit parallel data transfer.
The SED2032FoB uses a 5V logic supply and a 30 to 70V display supply, and is available in 60-pin
plastic flatpacks .
•
FEATURES
• 32 anode or grid output drivers
• 70V, 10mA anode or grid drive capability
• Can be configured for 4-bit parallel data transfer
• Automatic shutdown circuit
• Up to 4 Mbits/s serial data transfer rate
• Diasy-chain data transfer system for cascaded
operation
• 5V logic supply
• 30 to 70V display supply
• 60-pin plastic flatpack (QFP2-60pin [FOB])
• Silicon-gate CMOS technology
I
907
SED2032FoB
•
I
BLOCK DIAGRAM
r
•
Internal Circuitry
I~
CL
01
5~Q
cLYciY
a:
CL
908
o
~
SED2032FoB
•
PINOUT
45
31
46
30
SED2032FoB
16
60
15
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin
Name
0015
0014
0013
0012
0011
0010
009
008
007
006
005
004
003
002
001
Number
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin
Name
NC
NC
NC
BK2
BK1
LH1
CK1
SI1
SI2
CK2
LH2
VOOL
VSS
NC
VOOH
Number
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
909
Pin
Name
0017
0018
OP19
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
Number
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
0032
NC
NC
NC
NC
S02
NC
NC
NC
S01
NC
NC
NC
NC
0016
I
THIS PAGE INTENTIONALLY BLANK
910
IX. RELATED PRODUCTS
MCU
1996
DATABOOK
GRAPHICS
PRODUCTS
911
THIS PAGE INTENTIONALLY BLANK
912
IX. Related Products
IX. RELATED PRODUCTS
S-MOS carries a line of 4- and a-bit MCU ICs with built-in LCD drive and control functions, as summarized
below. Contact S-MOS for more information.
Part Number
SMC
LCD
Driver
Voltage
Range (V)
Twin
Clock
ROM
(x12)
RAM
(x4)
"1/0
621A
32SEG
314 COM
2.2 to 3.5
32KHz
455KHz
4096
208
22
6215
50SEG
314 COM
2.2 to 3.5
32KHz
455KHz
4096
488
34/44SEG 2.2 to 5.5
1-4 COM
32KHz
455KHz
4096
(Previously
6214)
621C
Package
'QFP
Available
Infrared remote control circuit, analog comparator,
LCD driver, watchdog timer,
SVD
80
Yes
25
Infrared remote control circuit, 2 analog comparators,
LCD driver, programmable
timer, watchdog timer, BLD
100
Yes
256
18
(80pin)
24
100pin)
Resistance to frequency
converter, LCD driver,
infrared remote control circuit, watchdog timer
80/100
10/94
48/60
Yes
Features
623A
623LA
20SEG
3/4 COM
1.8 to 3.5
0.9 to 2.0
N
N
1024
80
12
Low cost, stopwatch timer,
clock synchronous serial
port, LCD driver, SVD
6232
62L32
62A32
38SEG
3/4 COM
1.8 to 3.5
0.9 to 1.7
2.2 to 3.5
N
N
32K,500K
2048
144
21
Event counter, analog
comparator, stopwatch
timer, LCD driver,
watchdog timer, BLD
80
Yes
6233
62L33
62A33
40SEG
3/4 COM
1.8t03.5
0.9 to 1.7
2.2 to 3.5
N
N
32K,500K
3072
256
21
Event counter, analog
comparator, stopwatch
timer, LCD driver,
watchdog timer, BLD, SVD
100
Yes
6235
62L35
62A35
48SEG
314 COM
1.8 to 3.5
0.9 to 1.7
2.2 to 3.5
N
N
32K,500K
4096
576
25
Event counter, 2 analog
comparators, stopwatch
timer, LCD driver, watchdog timer, sound generator
100
Yes
6237
62L37
26SEG
3/4 COM
1.8 to 3.5
0.9 to 2.0
N
N
1024
80
12
Low cost, stopwatch timer,
LCD driver, SVD
60
Yes
624A
40SEG
8116 COM
1.8t05.5
32 KHz
500K-2M
6144
640
44
Dot matrix LCD driver,
external data memory access, watchdog timer,
counter, SIO, stopwatch
timer
128
Yes
624C
51 SEG
8/16 COM
1.8t05.5
32KHz
500K-2M
5120
1152
44
Dot matrix LCD driver,
external data memory access, watchdog timer,
serial port, sound generator
144
Yes
6244
40SEG
8116 COM
1.8t05.5
32KHz
500K-2M
4096
384
32
Dot matrix LCD driver,
watchdog timer, sound
generator, SVD, SIO
128
Yes
6247
64SEG
8/16 COM
0.9 to 3.6
32KHz
200KHz
8192
data
1792
disp
256
48
Dot matrix LCD driver,
external memory device
control, watchdog timer,
serial port
160
Yes
6248
51 SEG
8116 COM
1.8t05.5
32KHz
500K-2M
8192
768
44
Dot matrix LCD driver,
external data memory access, watchdog timer,
SIO, SVD
144
Yes
(Previously
6214)
(continued)
913
I
IX. Related Products
(continued)
Part Number
SMC
LCD
Driver
Voltage
Range (V)
Twin
Clock
ROM
(x12)
RAM
(x4)
**1/0
6251
62L51
26SEG
2-4 COM
1.8to 3.5
0.9 to 2.0
N
N
1024
80
12
6256
60SEG
2-5 COM
1.2 to 3.6
32KHz
1MHz
6144
640
6262
62L62
62A62
NONE
2.2 to 5.0
0.8 to 3.5
2.2 to 5.0
N
N
32K
500K-1M
2048
6266
NONE
2.2 to 3.5
38.4K
500K
6274
32 SEG
1-4 COM
2.4 to 5.5
6281
62L81
26SEG
3/4 COM
6282
62L82
62A82
Package
*QFP
Available
Low cost, resistance to
frequency converter, LCD
driver, SVD, counter, stopwatch timer
60/64
Yes
24
2 sensors (2 channels) R/F
converters, LCD driver
circuit, timebase counter,
SVD circuit
Die only
Yes
128
32
No LCD driver, synchronous
serial port, programmable
timer, watchdog timer, SIO,
event counter
44/88
Yes
6144
1024
40
No LCD driver, asynchronous & synchronous serial
ports, 2 analog comparators,
watchdog timer event
counter, 2 timers, BLD
60
Yes
32KHz
500KHz
4096
512
21
Dual slope AID, stopwatch
timer, LCD driver, two opamps, watchdog timer, SIO
100
Yes
1.8to 3.5
0.9 to 3.5
N
N
1024
96
15
Low cost, melody circuit,
analog comparator, LCD
driver, stopwatch timer,
counter, BLD
64
Yes
42138 SEG
4/8 COM
2.2 to 5.5
0.9 to 3.5
2.2 to 3.5
N
N
32K,1M
2048
144
15
Melody circuit, analog
comparator, LCD driver,
counter, stopwatch timer
80
Yes
62T3
32SEG
1-4COM
2.2 to 5.5
N
3072
488
21
DTMF circuit, pulse generator, LCD driver, stopwatch
timer, watchdog timer,
counter, BLD
80
6/94
6292
22SEG
2-4 COM
2.2 to 5.5
Y
2048
128
13
LCD driver, supply voltage
detector, measure temperature and humidity by
external sensor
64
9/94
88316
67SEG
16COM
1.8to 5.5
32KHz
B.2MHz
27
8-bit MCU with dot matrix
LCD driver, external program and data memory access, stopwatch timer,
watchdog timer, analog
comparator
160
Yesw/
Assembler
16Kx8 2KxB
Features
7/94 C
compiler
B8112
None
1.8 to 5.5
32KHz
B.2MHz
12Kx8 256xB
24
Power generator, voltage
detector, MCU built
especially for connection
external LCD drivers
BO
9/94
88308
57 SEG
1.Bto 5.5
32KHz
BKx8 256 x B
22
Up to 8.2 MHz (5V)
operation 16 levels of LCD
contrast controlled by
software
160
7/94
914
1996
DATABOOK
X. QA & PACKAGE
INFORMATION
GRAPHICS
PRODUCTS
915
THIS PAGE INTENTIONALLY BLANK
916
SPECIFICATIONS AND CHARACTERISTICS
1. SPECIFICATIONS AND CHARACTERISTICS
1.1 Electrical Characteristics
To fully utilize the CMOS IC it is important to understand the circuit, its characteristics and its specifications.
This chapter discusses the absolute maximum ratings, the recommended operating conditions and the electrical
characteristics of CMOS integrated circuits.
Please note that the voltage value is based on a high level power supply (VDD) or on a low level power supply
(Vss).
1.1.1 Absolute Maximum Ratings
The absolute maximum ratings of a specification are the highest levels at which the circuit will safely operate.
Exceeding this level may result in damage to, or destruction of, the circuit. It is, therefore, necessary to monitor such
things as supply voltage, input voltage and the ambient temperature.
(1)
Operating Voltage
This is the maximum voltage allowed at the power supply terminals. It is important not to let the voltage
exceed the specification, not only in the stationary state, but also in the transient state, during power supply
turn on, and includes noise on the power supply line. When the voltage exceeds the specification, it may cause
some damage to the IC and may adversely effect its reliability.
(2)
Input Voltage
This is the maximum voltage allowed into the input terminal. When voltage exceeding the specification
is applied, the IC may lose functions because of damage to the input protection resistors or diodes.
(3)
Output Current
This is the maximum value of current flow to or from the output. Generally, this is not specified for devices
which have small output capacity. This value is provided for ICs, such as drivers which require a large amount
of current.
(4)
Power Dissipation
This value shows the allowable dissipation for the device. It depends on the thermal characteristics of
its package. For devices which must supply large amounts of output, this specifies the limitation of the output
current.
(5)
Operating Temperature
The ambient temperature range at which the IC will function reliably.
(6)
Storage Temperature
The range of storage temperatures when no voltage is being applied on the IC. This is a very important
factor, especially during air transportation.
(7)
Soldering Temperature and Time
Maximum temperature and time allowed for soldering.
917
I
SPECIFICATIONS AND CHARACTERISTICS
1.1.2 Recommended Operating Conditions
The recommended operating conditions, such as supply voltage, input conditions, and external components,
are the conditions necessary for the IC to function properly to meet the electrical characteristics. The operating
conditions may be in the same column as the electrical characteristics.
1.1.3 Electrical Characteristics
AC and DC electrical characteristics are provided for each input pin and power supply pin. These
characteristics are measured at either the ambient temperature specified or in the range of the operating
temperatures specified under the worst conditions.
1.2
Symbol Definitions
SYMBOLS
Co
CG
CI
CliO
CL
Co
fxxx
fmax
fCLK
fosc
H
100
IDOA
1000
IDOS
Ii
III
IIH
IlL
10
10H
IOL
ILO
Iss
L
Po
RI
RL
Ta
Tj
Topr
Tstg
Tsol
Voo
VI
PARAMETERS
EXPLANATION
Static capacitance between output terminal and power supply
Drain Capacitance
terminal on the oscillation circuit.
Static capacitance between input terminal and power supply
Gate Capacitance
terminal on the oscillation circuit.
Static capacitance between the input terminal and the power
Input Capacitance
supply terminal.
Static capacitance between the 1/0 terminal and the power
Input/Output Capacitance
supply terminal.
Loading Capacitance
Loading static capacitance for the external components
Static capacitance between the output terminal and the power
Output Capacitance
supply terminal
XXX Frequency
XXX indicates either the function or the terminal name
Maximum Clock Frequency
Maximum Frequency input to the IC from an external pin
Clock Frequency
Clock Frequency input to the IC from an external pin
Oscillation Frequency
Oscillation Frequency
High level
Logical "H" level
(Voo) Supply Current
Supply current flows into the IC from the Voo external terminal
Average Operating Current
Average supply current flows into the IC from the Voo external
terminal
Operating Supply Current
Voo supply current while operating
Standby Supply Current
Voo supply current while standby
Input Current
Current which flows to the input terminal
Input Leakage Current
Leakage current which flows to the input terminal
High Level Input Current
The input current at the "H" level input
Low Level Input Current
The input current at the "L" level input
Output Current
Current which flows through the output terminal
High Level Output Current
Output current when the output terminal voltage is VOH
Low Level Output Current
Output current when the output terminal voltage is VOL
Leak current flowed when the power voltage is applied to the
Output Leakage Current
output terminal when in the 'off (high impedance)' condition
(Vss) Supply Current
Current flowed out of the Vss terminal
Low Level
Logical "L" level
Power Dissipation
Allowable consumption of the electric power
Input Resistance
Built-in resistance for pulling up and pulling down the input
Loading Resistance
Loading resistance for the external components
Ambient Temperature
Ambient temperature of the IC
Junction Temperature
Junction temperature of the IC
Operating Temperature
Surrounding temperature of the IC in operation
Storage Temperature
Temperature of storage area the IC
Soldering Temperature and TimE Soldering temperature and time
Supply voltage or the operating voltage applied to the VDD
(Voo) Supply Voltage
terminal
Input Voltage
Voltage applied to the input terminal
918
SPECIFICATIONS AND CHARACTERISTICS
1.2
Symbol Definitions (cont.)
SYMBOLS
Vila
VIH
VIL
Va
VOH
VOL
Vrip
Vss
VSSn
VSTA
VSTP
-
PARAMETERS
Input/Output Voltage
HiQh Level Input VoltaQe
Low Level Input Voltage
Output Voltage
High Level Output Voltage
Low Level Output Voltage
Ripple Voltage
(Vss) Supply Voltage
VSSn Supply Voltage
Oscillation Start Voltage
Oscillation Stop Voltage
"H", "L" or High Impedance
X
"H" or "L"
Z
High Impedance
ta
Access Time
tACC
Address Access Time
tACE
Chip Enable Access Time
tACS
Chip Select Access Time
tc
tRC
twc
tf
th
Cycle Time
Read Cycle Time
Write Cycle Time
Fall Time
Hold Time
tDH
Data Hold Time
tAH
Address Hold Time
tOE
Output Enable Delay Time
tOH
Output Hold Time
tpd
Propagation Delay Time
tpHL
Low Level Propagation Time
tpLH
High Level Propagation Time
tr
Rise Time
tsu
Set-up Time
lAs
Address Set-up Time
tDS
Data Set-up Time
tpw
tRP
twp
tWR
Pulse Width
Read Pulse Width
Write Pulse Width
Write Recovery Time
EXPLANATION
Voltage applied to the I/O terminal
Input voltaQe which can be judQed as "H" level
Input voltage which can be judged as "L" level
Voltage generated from or applied to the output terminal
Voltage at the "H" level output
Voltage at the "L" level output
Ripple voltage Amplitude
Supply voltage applied to the Vss terminal
N times pressurized power supply terminal or its voltage level
VoltaQe for automatic startinQ
Voltage when oscillation stops
Unfixed or unprovided level or high impedance
Unfixed or unprovided level
High impedance condition in three states
Time between the input of prescription and the output of the
valid data
Time required for obtaining the output of valid data after the
address is given
Time required for obtaining the output of the valid data after
the chip enable siQnal is Qiven
Time required for obtaining the output of the valid data after
chip select signal is given
Time from the start point of a complete operation to the start
point of the next operation
Time required for one read cycle
Time required for one write cycle
Time required for the signal changed from "H" to "L"
Time required for the synchronous input to be held stable after
the active clock edge
Time required for the data input to be held stable after the
active clock edge
Time required for the address input to be held stable after the
active clock edge
Time required for obtaining a valid output data after the output
enable signal is given
Time required for the output data to be held stable after the
active clock edge
Delay time between the active clock edge and the output
change
Delay time between the active clock edge and the output
change from High to Low
Delay time between the active clock edge and the output
change from Low to High
Time for changing the signal from Low to High
Time required for the synchronous input remained stable
before the next clock edge
Time required for the address input remained stable before the
next clock edge
Time required for the data input remained stable before the
next clock edge
Pulse width
Pulse width of the read signal
Pulse width of the write signal
Same as the address hold time tAH
919
I
QUALITY ASSURANCE
2. QUALITY ASSURANCE
S-MOS Systems, Inc., supported by the foundation of results acquired through experience in the adoption of
low-power CMOS LSI for SEIKO quartz watches, has been providing highly reliable products that have set new
standards in the industry.
Today extremely high reliability is demanded of our customers' products. In step with this trend, extremely high
reliability is demanded of semiconductor components.
To meet this demand in the market, we utilize a product quality assurance program which guarantees the
highest quality in our products.
Our quality assurance program is as follows:
2.1
Quality Assurance System for Development of New Products
Our quality assurance efforts begin with a market survey to determine the user's specific needs. After the
survey is completed, an analysis is made. Based on this analysis, an initial design is made. Next the initial design
goes through prototype production and quality evaluation stages. Once these steps are completed, a new product,
made according to the user's specifications is created. Fig. 2-1 shows the typical stages of new product development
from initial planning to commercial production.
Planning
•
Test
Sample
Test Data, Field Data and Process Capabilities are
used to compare the preliminary specs with the user's
requirements. Market potential is also checked at this
time.
•
The test sample is evaluated for basic design capabilities and for conformance to the product specifications.
•
The engineering sample is evaluated for quality
assurance within the scope of the manufacturing conditions.
•
The Production Sample is evaluated to determine if
the quality level is achievable with the equipment
available and under the existing manufacturing conditions.
_-,----'----,
Engineering .------Sample
,----'----,
Commercial ....1------1
Sample
Fig. 2·1
New Product Development Flow
920
QUALITY ASSURANCE
2.1.1 Design
Market surveys are done so the designers know the exact specifications required by the user. Based on the
information received, designs for the projected product are made. A "reliability" design is made using the data from
reliability tests, field quality studies, past problems and available quality or reliability related information. Design
staffs are given the purpose, environment and other factors relating to the application of a product to aid in its design.
2.1.2 Quality Evaluation
The quality evaluation is in two parts, the design evaluation and the reliability evaluation. The design evaluation
determines if the target functions and performance level have been reached. The reliability evaluation verifies that
long term quality is assured.
The reliability evaluation is done based on the particular objectives of the product. The evaluation is carried
out under pre-established guidelines. It is performed according to EIAJ-IC-121 (Electronics Industries Association)
standards and with MIL-STD-750B/883C and JIS-C7021 (Japanese Industrial Standards) where applicable. The
application, environment and uniqueness of the manufacturing process are also taken into consideration.
2.1.3 Decision to Start Commercial Production
The decision is made whether or not to start commercial production after the sample or prototype production
and quality evaluation are completed. This decision is based upon production capabilities, data verification on yield,
reliability test results and the user's evaluation of the engineering sample.
2.2
Quality Assurance Systems for Commercial Production
Quality and reliability are assured by design checks in the Engineering and Manufacturing Departments and
with verification of the finished product. Once in commercial production, quality control checks are made at various
stages. Quality control begins at the assembly line. Inspections follow during the intermediate and final processes,
ending with the shipping inspection. A quality assurance flow chart is shown in Fig. 2-2.
2.2.1 Manufacturing Environment Control
Due to the sensitive nature of semiconductor devices, extreme care must be used during the manufacturing
process. The manufacturing is done in a "clean room" where temperature, humidity and dust are carefully monitored
and controlled.
2.2.2 Control of Manufacturing and Measuring Equipment
Important elements of building reliability into a product are maintaining and controlling the manufacturing and
measuring equipment. This equipment is used to monitor and control line conditions and/or to do intermediate
inspections. With the evolution of devices to higher integrations and improved reliability, the production process
must be controlled at a higher level. Routine checks and periodic inspections insure that we achieve these high
standards.
2.2.3 Process Inspection
Quality Assurance is based on the theory that quality is built into the product. The inspection at each processing
stage assures high quality. The inspection results are fed back into each process in order to stabilize the entire
operation. These inspections also prevent defective parts from moving to the next process stage.
Figs. 2-3 and 2-4 show typical wafer process and assembly flow.
2.2.4 Shipping Inspection
The final inspection is performed when the product is ready to ship to reverify that the product meets our high
standards. The electrical characteristics are 100% tested, and the environmental characteristics are tested on a lot
sample basis. External visual inspection is also performed.
The shipping inspection is performed according to the category of the product. An example of the inspection
process is shown in Table 2-1.
921
I
QUALITY ASSURANCE
••
Dept.
r---
0
U
Materials
Sales
Inspection
.
Supply of
materials
~
C
••
Manufacturing
I
0
{)
1>
::J
I
(/)
'-
I
Wafer
process
Quality
Control
..
..
I
Flow of product!
sample
Flow of data and
information
I
Intermediate
inspection
I
II
Acceptance
inspection
Design
Engineering
Dicing
I
Intermediate
inspection
I
I
Die attach
Wire bonding
I
Molding
I
I
(Screening)
I,Change
Design /proces~ I
Change
Reliability
test
Shipping insp.
I
I
J
Packing
-0
I
Shipping of
product
"
Quality data
I
Oi
E
0
u;
::J
t
I
r--
I
Prototype
manufacture
"
Implementation
of the change
I
I
I
Quality data
analysis
t
Failure
information/
defective
product
obtained
Failure
information
analysis
0
I
t
t
t
Failure
analysis
Failure
analysis
Failure
analysis
I
,
I
'--
I
Reliability
evaluation
Action taken
I I
,
I
Action taken
t
I
Q
,
II
Action taken
I
Result of
analysis
~
-
Fig. 2-2
Flow of Quality Assurance Activities in Commercial Production
922
Failure
analysis
Result of
analysis
QUALITY ASSURANCE
Equipment Evaluation
I LI___p_ro_c_e_s_s_F_IO_W_ _---'1 LI__p_r_o_c_e_ss_E_v_a_lu_a_tio_n_---'
Wafer: Resistivity, Thickness
Flatness
Visual inspection
Particle check
C-VTest
C-VTest
Temperature check
n : > - - - - - Thickness, Visual Inspection
Coater: Photoresist Thickness
Aligner: Distortion check
Focus check
Lamp check
Mask : Defect check (by NJS)
Pattern Size
Pattern Size
:;::>----- Pattern Resolution
C-VTest
Temperature check
-:;:,_ _ _ _ Sheet Resistivity
Diffusion Depth
Vth Shift
~---- Sheet Resistivity
Particle check
- : ; : , - - - - AI Thickness, Step coverage
Particle check
C-VTest
V threshold, B, B VDS
>---- Visual Inspection
Fig. 2-3
Quality Assurance System for Wafer Production
923
I
QUALITY ASSURANCE
Main Flow
Check Items
Lead Frame
Inspection
Silver Epoxy
Au-wire
Die & Wire Inspection
Pull Test
Epoxy Compound
Thickness
Mark Ink
Inspection
Electrical
characteristics
External visual
Lot Sampling
Temperature Cycle
Bum-in
etc.
Fig. 2-4
Plastic Package Assembly Flowchart
924
QUALITY ASSURANCE
Table 2-1
Example of Shipping Inspection
o : Each lot is inspected for quality assurance.
D: Specific lot is inspected to understand process levels.
Shipping Inspection for Pellet
No.
1
'--""';P'---" (Sampling)
Process
Electrical characteristics
(100%)
Standard condition
Control Point
Wafer process
2
Resistance to heat
i
3
Bondability
i
4
Electrical characteristics!
i
5
Temperature cycle
i
6
High temperature with bia
i
7
Visual inspection
(method)
Determined by product type
Exposed to high temperature
for short time
Wire pull
Die shear strength
Determined by product types
-55°C to 125°C (for 30 Min. at each
temperature)
125°C with Max. rated voltage
applied
Wafer process!
inspection
Microscope
process
Shipping Inspection for Plastic package
No.
Process
Wafer process!
8
Screening
Standard condition
Control Point
Assembling
(method)
Burn-in
Determined by product types
process
(Sampling)
9
10
Electrical characteristics
(100%)
Visual inspection (100%)
i
Assembling
Determined by product types
Visually checked
process
11
Temperature cycle
12
characteristics!
Electrical
Wafer process!
Visual inspection
13
High temperature
with bias
NO GO
14
i
Pressure cooking
Assembling
Moisture resistance
i
Assembling
Wafer process!
Assembling
(with bias)
process
925
Determined by product types!
visually checked
process
process
15
-55°C to 125°C (for 30 minutes
at each temperature)
125°C with Max. rated voltage
applied
2 atmospheric (vapor) pressure
(at 121°C)
85°C, 85% RH with Max. rated
voltage applied
I
QUALITY ASSURANCE
2.3
Reliability Testing
The reliability test includes environmental testing, life testing and mechanical testing, These tests are made
in accordance with EIAJ-IC-121 as the prime standard, and with MIL-STO-750B/883C and JIS where applicable,
The way the product is used, the application and the environment in which the product is operated are some of the
factors taken into consideration when the conditions are set for the reliability test. It is important to conduct tests of
new products under conditions that simulate how the product is to be used, In addition, standard tests are performed,
Table 2-2 summarizes the reliability test items and the factors associated with defects, Table 2-3 gives an
example of typical conditions for reliability testing,
Table 2-2
Factors
associated
with
defects
Reliability Test Items and Factors Associated with Defects
c
0
~
c
(5
,!Q
c
0
0
c
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~
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0
~
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c
'5
c
~
OJ
c
'5
c
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0
.0
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~
~
:0
~
OJ
0
:2
a..
Ci
3:
c:i
~~
!
;:i
~
Hl)(,. .
e.
•
~0-12'
O.B±o.2
~l
~o
ci:t
~~0-12'
.5 ± 0.2
0.051
(1.3)
1-,·
Plastic QFP9-196pin
Plastic QFP16-240pin-Sl (under development)
,m, (43.2 ± , .•) - - .
-1
4 ,2 ±.o"(34.6±,.•)
r1.260±O.008 (32.0 ± 0.2)-----
1.575 ± 0.008 (40.0 ± 0.2)----+
99
157
\
rC
~;
0.063
(1.6)
156
r
+
--+- .JM~o':.L.~
!
~
~
1.701 ±
53
1J~O,020 ± 0.004 J~.OO8 ± 0.004 52
47
T1~~
I_1""--
J
208
J~:~04IIO.012±o.00446
(065±") -
5~
Index
Index
or-
~!
~~
~'"
~~ .)il.
184
180
98"
~
!
~
[
121
1B1
120t
~
cf
-- -
1..i1. 0(0.65
.026 ±CI.004
± 1l.1) J~
(O.3 ± 0.1)
~~
-;1;
§";'
~ ~
59-
-
~ ~
iil~
Index
1
h~
i,
,!~
.'r:r--~~.-"
u
.~
8~
de.
0.2
0.020
~
J.
61
~
O.O20±O.OO8
. to.:!
Ir014
(0.35)
0.051
(1.3)
938
r
+
O.OO8 ± ~.00260
... JO.2±O.05)
II
•
0.063
(1.8)
~~
J
240
58
.6±
r
~~
:il '"§.
':l
Index
196
~
ii
PACKAGE INFORMATION
Plastic QFPs
Unit: inch (mm)
Plastic QFP1-46pin
~-----------------------------------,
1.031 ±O,O'6
(26.2±o.4)
0.122
(3.1)
939
I
THIS PAGE INTENTIONALLY BLANK
940
.-
S-MOS
S
Y
S
T
EM
S
A Seiko Epson Affiliate
"""'...,USA
4300 Six Forks Road
Suite 430
Raleigh, NC 27609
Tel: (919) 781-7667
Fax: (919) 781-6778
. . . . .ftI
USA
301 Edgewater Place
Suite 120
VVakefield,~ 01880
Tel: (617) 246-3600
Fax: (617) 246-5443
H.... OIIIee
S-MOS Systems, Inc.
2460 North First Street
San Jose, CA 95131
Tel: (408) 922-0200
Fax: (408) 922-0238
GDB-lJ96-10M
Printed in U.S.A.
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